Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 31
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 25
1 23:44:45.817570 lava-dispatcher, installed at version: 2024.03
2 23:44:45.817763 start: 0 validate
3 23:44:45.817890 Start time: 2024-06-04 23:44:45.817883+00:00 (UTC)
4 23:44:45.818019 Using caching service: 'http://localhost/cache/?uri=%s'
5 23:44:45.818148 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-libcamera%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 23:44:46.084530 Using caching service: 'http://localhost/cache/?uri=%s'
7 23:44:46.085256 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 23:44:46.353107 Using caching service: 'http://localhost/cache/?uri=%s'
9 23:44:46.354071 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 23:44:46.616441 Using caching service: 'http://localhost/cache/?uri=%s'
11 23:44:46.617154 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-libcamera%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 23:44:46.883811 Using caching service: 'http://localhost/cache/?uri=%s'
13 23:44:46.884592 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 23:44:47.148191 validate duration: 1.33
16 23:44:47.149555 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 23:44:47.150143 start: 1.1 download-retry (timeout 00:10:00) [common]
18 23:44:47.150727 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 23:44:47.151321 Not decompressing ramdisk as can be used compressed.
20 23:44:47.151784 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-libcamera/20240313.0/arm64/initrd.cpio.gz
21 23:44:47.152139 saving as /var/lib/lava/dispatcher/tmp/14172980/tftp-deploy-2o3salbj/ramdisk/initrd.cpio.gz
22 23:44:47.152490 total size: 5628151 (5 MB)
23 23:44:47.161540 progress 0 % (0 MB)
24 23:44:47.169391 progress 5 % (0 MB)
25 23:44:47.176103 progress 10 % (0 MB)
26 23:44:47.180244 progress 15 % (0 MB)
27 23:44:47.184141 progress 20 % (1 MB)
28 23:44:47.187223 progress 25 % (1 MB)
29 23:44:47.190101 progress 30 % (1 MB)
30 23:44:47.192846 progress 35 % (1 MB)
31 23:44:47.195065 progress 40 % (2 MB)
32 23:44:47.197536 progress 45 % (2 MB)
33 23:44:47.199447 progress 50 % (2 MB)
34 23:44:47.201549 progress 55 % (2 MB)
35 23:44:47.203559 progress 60 % (3 MB)
36 23:44:47.205253 progress 65 % (3 MB)
37 23:44:47.207156 progress 70 % (3 MB)
38 23:44:47.208761 progress 75 % (4 MB)
39 23:44:47.210588 progress 80 % (4 MB)
40 23:44:47.212176 progress 85 % (4 MB)
41 23:44:47.213767 progress 90 % (4 MB)
42 23:44:47.215332 progress 95 % (5 MB)
43 23:44:47.216800 progress 100 % (5 MB)
44 23:44:47.217021 5 MB downloaded in 0.06 s (83.14 MB/s)
45 23:44:47.217193 end: 1.1.1 http-download (duration 00:00:00) [common]
47 23:44:47.217473 end: 1.1 download-retry (duration 00:00:00) [common]
48 23:44:47.217578 start: 1.2 download-retry (timeout 00:10:00) [common]
49 23:44:47.217679 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 23:44:47.217826 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 23:44:47.217899 saving as /var/lib/lava/dispatcher/tmp/14172980/tftp-deploy-2o3salbj/kernel/Image
52 23:44:47.217997 total size: 54682112 (52 MB)
53 23:44:47.218097 No compression specified
54 23:44:47.219714 progress 0 % (0 MB)
55 23:44:47.233812 progress 5 % (2 MB)
56 23:44:47.248298 progress 10 % (5 MB)
57 23:44:47.262357 progress 15 % (7 MB)
58 23:44:47.276389 progress 20 % (10 MB)
59 23:44:47.290364 progress 25 % (13 MB)
60 23:44:47.304170 progress 30 % (15 MB)
61 23:44:47.318152 progress 35 % (18 MB)
62 23:44:47.332450 progress 40 % (20 MB)
63 23:44:47.346305 progress 45 % (23 MB)
64 23:44:47.360483 progress 50 % (26 MB)
65 23:44:47.374229 progress 55 % (28 MB)
66 23:44:47.388061 progress 60 % (31 MB)
67 23:44:47.401661 progress 65 % (33 MB)
68 23:44:47.415485 progress 70 % (36 MB)
69 23:44:47.429194 progress 75 % (39 MB)
70 23:44:47.443122 progress 80 % (41 MB)
71 23:44:47.457051 progress 85 % (44 MB)
72 23:44:47.470877 progress 90 % (46 MB)
73 23:44:47.485012 progress 95 % (49 MB)
74 23:44:47.499616 progress 100 % (52 MB)
75 23:44:47.499855 52 MB downloaded in 0.28 s (185.02 MB/s)
76 23:44:47.500005 end: 1.2.1 http-download (duration 00:00:00) [common]
78 23:44:47.500243 end: 1.2 download-retry (duration 00:00:00) [common]
79 23:44:47.500328 start: 1.3 download-retry (timeout 00:10:00) [common]
80 23:44:47.500411 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 23:44:47.500542 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 23:44:47.500608 saving as /var/lib/lava/dispatcher/tmp/14172980/tftp-deploy-2o3salbj/dtb/mt8192-asurada-spherion-r0.dtb
83 23:44:47.500667 total size: 47258 (0 MB)
84 23:44:47.500727 No compression specified
85 23:44:47.501794 progress 69 % (0 MB)
86 23:44:47.502064 progress 100 % (0 MB)
87 23:44:47.502231 0 MB downloaded in 0.00 s (28.86 MB/s)
88 23:44:47.502352 end: 1.3.1 http-download (duration 00:00:00) [common]
90 23:44:47.502570 end: 1.3 download-retry (duration 00:00:00) [common]
91 23:44:47.502652 start: 1.4 download-retry (timeout 00:10:00) [common]
92 23:44:47.502733 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 23:44:47.502839 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-libcamera/20240313.0/arm64/full.rootfs.tar.xz
94 23:44:47.502904 saving as /var/lib/lava/dispatcher/tmp/14172980/tftp-deploy-2o3salbj/nfsrootfs/full.rootfs.tar
95 23:44:47.502967 total size: 69067788 (65 MB)
96 23:44:47.503028 Using unxz to decompress xz
97 23:44:47.510847 progress 0 % (0 MB)
98 23:44:47.702310 progress 5 % (3 MB)
99 23:44:47.902018 progress 10 % (6 MB)
100 23:44:48.106537 progress 15 % (9 MB)
101 23:44:48.268411 progress 20 % (13 MB)
102 23:44:48.443777 progress 25 % (16 MB)
103 23:44:48.644049 progress 30 % (19 MB)
104 23:44:48.761635 progress 35 % (23 MB)
105 23:44:48.857442 progress 40 % (26 MB)
106 23:44:49.055119 progress 45 % (29 MB)
107 23:44:49.262593 progress 50 % (32 MB)
108 23:44:49.465787 progress 55 % (36 MB)
109 23:44:49.683183 progress 60 % (39 MB)
110 23:44:49.871216 progress 65 % (42 MB)
111 23:44:50.063910 progress 70 % (46 MB)
112 23:44:50.254354 progress 75 % (49 MB)
113 23:44:50.465877 progress 80 % (52 MB)
114 23:44:50.638715 progress 85 % (56 MB)
115 23:44:50.826003 progress 90 % (59 MB)
116 23:44:51.026907 progress 95 % (62 MB)
117 23:44:51.225834 progress 100 % (65 MB)
118 23:44:51.231887 65 MB downloaded in 3.73 s (17.66 MB/s)
119 23:44:51.232135 end: 1.4.1 http-download (duration 00:00:04) [common]
121 23:44:51.232427 end: 1.4 download-retry (duration 00:00:04) [common]
122 23:44:51.232518 start: 1.5 download-retry (timeout 00:09:56) [common]
123 23:44:51.232602 start: 1.5.1 http-download (timeout 00:09:56) [common]
124 23:44:51.232755 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 23:44:51.232823 saving as /var/lib/lava/dispatcher/tmp/14172980/tftp-deploy-2o3salbj/modules/modules.tar
126 23:44:51.232883 total size: 8603924 (8 MB)
127 23:44:51.232947 Using unxz to decompress xz
128 23:44:51.236999 progress 0 % (0 MB)
129 23:44:51.256815 progress 5 % (0 MB)
130 23:44:51.281548 progress 10 % (0 MB)
131 23:44:51.307871 progress 15 % (1 MB)
132 23:44:51.332414 progress 20 % (1 MB)
133 23:44:51.357891 progress 25 % (2 MB)
134 23:44:51.382508 progress 30 % (2 MB)
135 23:44:51.405697 progress 35 % (2 MB)
136 23:44:51.431260 progress 40 % (3 MB)
137 23:44:51.455637 progress 45 % (3 MB)
138 23:44:51.479400 progress 50 % (4 MB)
139 23:44:51.503613 progress 55 % (4 MB)
140 23:44:51.527769 progress 60 % (4 MB)
141 23:44:51.551412 progress 65 % (5 MB)
142 23:44:51.578174 progress 70 % (5 MB)
143 23:44:51.603173 progress 75 % (6 MB)
144 23:44:51.628516 progress 80 % (6 MB)
145 23:44:51.651994 progress 85 % (7 MB)
146 23:44:51.675481 progress 90 % (7 MB)
147 23:44:51.704451 progress 95 % (7 MB)
148 23:44:51.732269 progress 100 % (8 MB)
149 23:44:51.737753 8 MB downloaded in 0.50 s (16.25 MB/s)
150 23:44:51.738069 end: 1.5.1 http-download (duration 00:00:01) [common]
152 23:44:51.738406 end: 1.5 download-retry (duration 00:00:01) [common]
153 23:44:51.738499 start: 1.6 prepare-tftp-overlay (timeout 00:09:55) [common]
154 23:44:51.738592 start: 1.6.1 extract-nfsrootfs (timeout 00:09:55) [common]
155 23:44:53.259145 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14172980/extract-nfsrootfs-vz806a3u
156 23:44:53.259347 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 23:44:53.259448 start: 1.6.2 lava-overlay (timeout 00:09:54) [common]
158 23:44:53.259615 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14172980/lava-overlay-ajh6rcwo
159 23:44:53.259744 makedir: /var/lib/lava/dispatcher/tmp/14172980/lava-overlay-ajh6rcwo/lava-14172980/bin
160 23:44:53.259848 makedir: /var/lib/lava/dispatcher/tmp/14172980/lava-overlay-ajh6rcwo/lava-14172980/tests
161 23:44:53.259945 makedir: /var/lib/lava/dispatcher/tmp/14172980/lava-overlay-ajh6rcwo/lava-14172980/results
162 23:44:53.260042 Creating /var/lib/lava/dispatcher/tmp/14172980/lava-overlay-ajh6rcwo/lava-14172980/bin/lava-add-keys
163 23:44:53.260178 Creating /var/lib/lava/dispatcher/tmp/14172980/lava-overlay-ajh6rcwo/lava-14172980/bin/lava-add-sources
164 23:44:53.260302 Creating /var/lib/lava/dispatcher/tmp/14172980/lava-overlay-ajh6rcwo/lava-14172980/bin/lava-background-process-start
165 23:44:53.260426 Creating /var/lib/lava/dispatcher/tmp/14172980/lava-overlay-ajh6rcwo/lava-14172980/bin/lava-background-process-stop
166 23:44:53.260548 Creating /var/lib/lava/dispatcher/tmp/14172980/lava-overlay-ajh6rcwo/lava-14172980/bin/lava-common-functions
167 23:44:53.260669 Creating /var/lib/lava/dispatcher/tmp/14172980/lava-overlay-ajh6rcwo/lava-14172980/bin/lava-echo-ipv4
168 23:44:53.260791 Creating /var/lib/lava/dispatcher/tmp/14172980/lava-overlay-ajh6rcwo/lava-14172980/bin/lava-install-packages
169 23:44:53.260911 Creating /var/lib/lava/dispatcher/tmp/14172980/lava-overlay-ajh6rcwo/lava-14172980/bin/lava-installed-packages
170 23:44:53.261031 Creating /var/lib/lava/dispatcher/tmp/14172980/lava-overlay-ajh6rcwo/lava-14172980/bin/lava-os-build
171 23:44:53.261153 Creating /var/lib/lava/dispatcher/tmp/14172980/lava-overlay-ajh6rcwo/lava-14172980/bin/lava-probe-channel
172 23:44:53.261274 Creating /var/lib/lava/dispatcher/tmp/14172980/lava-overlay-ajh6rcwo/lava-14172980/bin/lava-probe-ip
173 23:44:53.261392 Creating /var/lib/lava/dispatcher/tmp/14172980/lava-overlay-ajh6rcwo/lava-14172980/bin/lava-target-ip
174 23:44:53.261511 Creating /var/lib/lava/dispatcher/tmp/14172980/lava-overlay-ajh6rcwo/lava-14172980/bin/lava-target-mac
175 23:44:53.261630 Creating /var/lib/lava/dispatcher/tmp/14172980/lava-overlay-ajh6rcwo/lava-14172980/bin/lava-target-storage
176 23:44:53.261752 Creating /var/lib/lava/dispatcher/tmp/14172980/lava-overlay-ajh6rcwo/lava-14172980/bin/lava-test-case
177 23:44:53.261876 Creating /var/lib/lava/dispatcher/tmp/14172980/lava-overlay-ajh6rcwo/lava-14172980/bin/lava-test-event
178 23:44:53.261995 Creating /var/lib/lava/dispatcher/tmp/14172980/lava-overlay-ajh6rcwo/lava-14172980/bin/lava-test-feedback
179 23:44:53.262113 Creating /var/lib/lava/dispatcher/tmp/14172980/lava-overlay-ajh6rcwo/lava-14172980/bin/lava-test-raise
180 23:44:53.262391 Creating /var/lib/lava/dispatcher/tmp/14172980/lava-overlay-ajh6rcwo/lava-14172980/bin/lava-test-reference
181 23:44:53.262514 Creating /var/lib/lava/dispatcher/tmp/14172980/lava-overlay-ajh6rcwo/lava-14172980/bin/lava-test-runner
182 23:44:53.262634 Creating /var/lib/lava/dispatcher/tmp/14172980/lava-overlay-ajh6rcwo/lava-14172980/bin/lava-test-set
183 23:44:53.262753 Creating /var/lib/lava/dispatcher/tmp/14172980/lava-overlay-ajh6rcwo/lava-14172980/bin/lava-test-shell
184 23:44:53.262874 Updating /var/lib/lava/dispatcher/tmp/14172980/lava-overlay-ajh6rcwo/lava-14172980/bin/lava-install-packages (oe)
185 23:44:53.263020 Updating /var/lib/lava/dispatcher/tmp/14172980/lava-overlay-ajh6rcwo/lava-14172980/bin/lava-installed-packages (oe)
186 23:44:53.263136 Creating /var/lib/lava/dispatcher/tmp/14172980/lava-overlay-ajh6rcwo/lava-14172980/environment
187 23:44:53.263231 LAVA metadata
188 23:44:53.263296 - LAVA_JOB_ID=14172980
189 23:44:53.263357 - LAVA_DISPATCHER_IP=192.168.201.1
190 23:44:53.263454 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:54) [common]
191 23:44:53.263519 skipped lava-vland-overlay
192 23:44:53.263590 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 23:44:53.263667 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:54) [common]
194 23:44:53.263727 skipped lava-multinode-overlay
195 23:44:53.263796 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 23:44:53.263870 start: 1.6.2.3 test-definition (timeout 00:09:54) [common]
197 23:44:53.263941 Loading test definitions
198 23:44:53.264025 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:54) [common]
199 23:44:53.264094 Using /lava-14172980 at stage 0
200 23:44:53.264389 uuid=14172980_1.6.2.3.1 testdef=None
201 23:44:53.264476 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 23:44:53.264560 start: 1.6.2.3.2 test-overlay (timeout 00:09:54) [common]
203 23:44:53.265034 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 23:44:53.265248 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:54) [common]
206 23:44:53.265835 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 23:44:53.266056 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:54) [common]
209 23:44:53.266661 runner path: /var/lib/lava/dispatcher/tmp/14172980/lava-overlay-ajh6rcwo/lava-14172980/0/tests/0_lc-compliance test_uuid 14172980_1.6.2.3.1
210 23:44:53.266815 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 23:44:53.267014 Creating lava-test-runner.conf files
213 23:44:53.267074 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14172980/lava-overlay-ajh6rcwo/lava-14172980/0 for stage 0
214 23:44:53.267161 - 0_lc-compliance
215 23:44:53.267254 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
216 23:44:53.267336 start: 1.6.2.4 compress-overlay (timeout 00:09:54) [common]
217 23:44:53.273098 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
218 23:44:53.273197 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:54) [common]
219 23:44:53.273279 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
220 23:44:53.273359 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
221 23:44:53.273441 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:54) [common]
222 23:44:53.436059 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
223 23:44:53.436447 start: 1.6.4 extract-modules (timeout 00:09:54) [common]
224 23:44:53.436570 extracting modules file /var/lib/lava/dispatcher/tmp/14172980/tftp-deploy-2o3salbj/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14172980/extract-nfsrootfs-vz806a3u
225 23:44:53.661340 extracting modules file /var/lib/lava/dispatcher/tmp/14172980/tftp-deploy-2o3salbj/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14172980/extract-overlay-ramdisk-yaqxgmws/ramdisk
226 23:44:53.876255 end: 1.6.4 extract-modules (duration 00:00:00) [common]
227 23:44:53.876422 start: 1.6.5 apply-overlay-tftp (timeout 00:09:53) [common]
228 23:44:53.876514 [common] Applying overlay to NFS
229 23:44:53.876584 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14172980/compress-overlay-xa51di_c/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14172980/extract-nfsrootfs-vz806a3u
230 23:44:53.883076 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
231 23:44:53.883189 start: 1.6.6 configure-preseed-file (timeout 00:09:53) [common]
232 23:44:53.883277 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
233 23:44:53.883366 start: 1.6.7 compress-ramdisk (timeout 00:09:53) [common]
234 23:44:53.883446 Building ramdisk /var/lib/lava/dispatcher/tmp/14172980/extract-overlay-ramdisk-yaqxgmws/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14172980/extract-overlay-ramdisk-yaqxgmws/ramdisk
235 23:44:54.183364 >> 130337 blocks
236 23:44:56.179156 rename /var/lib/lava/dispatcher/tmp/14172980/extract-overlay-ramdisk-yaqxgmws/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14172980/tftp-deploy-2o3salbj/ramdisk/ramdisk.cpio.gz
237 23:44:56.179605 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
238 23:44:56.179728 start: 1.6.8 prepare-kernel (timeout 00:09:51) [common]
239 23:44:56.179826 start: 1.6.8.1 prepare-fit (timeout 00:09:51) [common]
240 23:44:56.179927 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14172980/tftp-deploy-2o3salbj/kernel/Image']
241 23:45:09.140570 Returned 0 in 12 seconds
242 23:45:09.241587 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14172980/tftp-deploy-2o3salbj/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14172980/tftp-deploy-2o3salbj/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14172980/tftp-deploy-2o3salbj/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14172980/tftp-deploy-2o3salbj/kernel/image.itb
243 23:45:09.624406 output: FIT description: Kernel Image image with one or more FDT blobs
244 23:45:09.624775 output: Created: Wed Jun 5 00:45:09 2024
245 23:45:09.624846 output: Image 0 (kernel-1)
246 23:45:09.624912 output: Description:
247 23:45:09.624978 output: Created: Wed Jun 5 00:45:09 2024
248 23:45:09.625040 output: Type: Kernel Image
249 23:45:09.625100 output: Compression: lzma compressed
250 23:45:09.625160 output: Data Size: 13061430 Bytes = 12755.30 KiB = 12.46 MiB
251 23:45:09.625219 output: Architecture: AArch64
252 23:45:09.625278 output: OS: Linux
253 23:45:09.625334 output: Load Address: 0x00000000
254 23:45:09.625391 output: Entry Point: 0x00000000
255 23:45:09.625446 output: Hash algo: crc32
256 23:45:09.625499 output: Hash value: ecfb5096
257 23:45:09.625552 output: Image 1 (fdt-1)
258 23:45:09.625605 output: Description: mt8192-asurada-spherion-r0
259 23:45:09.625659 output: Created: Wed Jun 5 00:45:09 2024
260 23:45:09.625711 output: Type: Flat Device Tree
261 23:45:09.625763 output: Compression: uncompressed
262 23:45:09.625814 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
263 23:45:09.625866 output: Architecture: AArch64
264 23:45:09.625917 output: Hash algo: crc32
265 23:45:09.625969 output: Hash value: 0f8e4d2e
266 23:45:09.626021 output: Image 2 (ramdisk-1)
267 23:45:09.626072 output: Description: unavailable
268 23:45:09.626123 output: Created: Wed Jun 5 00:45:09 2024
269 23:45:09.626182 output: Type: RAMDisk Image
270 23:45:09.626235 output: Compression: Unknown Compression
271 23:45:09.626286 output: Data Size: 18735187 Bytes = 18296.08 KiB = 17.87 MiB
272 23:45:09.626338 output: Architecture: AArch64
273 23:45:09.626389 output: OS: Linux
274 23:45:09.626440 output: Load Address: unavailable
275 23:45:09.626492 output: Entry Point: unavailable
276 23:45:09.626543 output: Hash algo: crc32
277 23:45:09.626593 output: Hash value: 21ebb2af
278 23:45:09.626644 output: Default Configuration: 'conf-1'
279 23:45:09.626695 output: Configuration 0 (conf-1)
280 23:45:09.626746 output: Description: mt8192-asurada-spherion-r0
281 23:45:09.626797 output: Kernel: kernel-1
282 23:45:09.626848 output: Init Ramdisk: ramdisk-1
283 23:45:09.626899 output: FDT: fdt-1
284 23:45:09.626950 output: Loadables: kernel-1
285 23:45:09.627001 output:
286 23:45:09.627208 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
287 23:45:09.627321 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
288 23:45:09.627427 end: 1.6 prepare-tftp-overlay (duration 00:00:18) [common]
289 23:45:09.627521 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:38) [common]
290 23:45:09.627598 No LXC device requested
291 23:45:09.627676 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
292 23:45:09.627758 start: 1.8 deploy-device-env (timeout 00:09:38) [common]
293 23:45:09.627836 end: 1.8 deploy-device-env (duration 00:00:00) [common]
294 23:45:09.627903 Checking files for TFTP limit of 4294967296 bytes.
295 23:45:09.628403 end: 1 tftp-deploy (duration 00:00:22) [common]
296 23:45:09.628502 start: 2 depthcharge-action (timeout 00:05:00) [common]
297 23:45:09.628594 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
298 23:45:09.628721 substitutions:
299 23:45:09.628786 - {DTB}: 14172980/tftp-deploy-2o3salbj/dtb/mt8192-asurada-spherion-r0.dtb
300 23:45:09.628848 - {INITRD}: 14172980/tftp-deploy-2o3salbj/ramdisk/ramdisk.cpio.gz
301 23:45:09.628905 - {KERNEL}: 14172980/tftp-deploy-2o3salbj/kernel/Image
302 23:45:09.628963 - {LAVA_MAC}: None
303 23:45:09.629019 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14172980/extract-nfsrootfs-vz806a3u
304 23:45:09.629074 - {NFS_SERVER_IP}: 192.168.201.1
305 23:45:09.629128 - {PRESEED_CONFIG}: None
306 23:45:09.629181 - {PRESEED_LOCAL}: None
307 23:45:09.629234 - {RAMDISK}: 14172980/tftp-deploy-2o3salbj/ramdisk/ramdisk.cpio.gz
308 23:45:09.629287 - {ROOT_PART}: None
309 23:45:09.629339 - {ROOT}: None
310 23:45:09.629391 - {SERVER_IP}: 192.168.201.1
311 23:45:09.629443 - {TEE}: None
312 23:45:09.629495 Parsed boot commands:
313 23:45:09.629547 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
314 23:45:09.629725 Parsed boot commands: tftpboot 192.168.201.1 14172980/tftp-deploy-2o3salbj/kernel/image.itb 14172980/tftp-deploy-2o3salbj/kernel/cmdline
315 23:45:09.629811 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
316 23:45:09.629895 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
317 23:45:09.629984 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
318 23:45:09.630066 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
319 23:45:09.630137 Not connected, no need to disconnect.
320 23:45:09.630216 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
321 23:45:09.630301 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
322 23:45:09.630371 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-9'
323 23:45:09.633985 Setting prompt string to ['lava-test: # ']
324 23:45:09.634355 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
325 23:45:09.634460 end: 2.2.1 reset-connection (duration 00:00:00) [common]
326 23:45:09.634559 start: 2.2.2 reset-device (timeout 00:05:00) [common]
327 23:45:09.634651 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
328 23:45:09.634828 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-9']
329 23:45:23.786969 Returned 0 in 14 seconds
330 23:45:23.888283 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
332 23:45:23.889817 end: 2.2.2 reset-device (duration 00:00:14) [common]
333 23:45:23.890388 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
334 23:45:23.890883 Setting prompt string to 'Starting depthcharge on Spherion...'
335 23:45:23.891298 Changing prompt to 'Starting depthcharge on Spherion...'
336 23:45:23.891723 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
337 23:45:23.893793 [Enter `^Ec?' for help]
338 23:45:23.894313
339 23:45:23.894738
340 23:45:23.895100 F0: 102B 0000
341 23:45:23.895442
342 23:45:23.895843 F3: 1001 0000 [0200]
343 23:45:23.896181
344 23:45:23.896523 F3: 1001 0000
345 23:45:23.896857
346 23:45:23.897158 F7: 102D 0000
347 23:45:23.897498
348 23:45:23.897847 F1: 0000 0000
349 23:45:23.898152
350 23:45:23.898501 V0: 0000 0000 [0001]
351 23:45:23.898806
352 23:45:23.899105 00: 0007 8000
353 23:45:23.899469
354 23:45:23.899833 01: 0000 0000
355 23:45:23.900148
356 23:45:23.900448 BP: 0C00 0209 [0000]
357 23:45:23.900749
358 23:45:23.901092 G0: 1182 0000
359 23:45:23.901417
360 23:45:23.901721 EC: 0000 0021 [4000]
361 23:45:23.902020
362 23:45:23.902341 S7: 0000 0000 [0000]
363 23:45:23.902712
364 23:45:23.903030 CC: 0000 0000 [0001]
365 23:45:23.903331
366 23:45:23.903674 T0: 0000 0040 [010F]
367 23:45:23.903988
368 23:45:23.904341 Jump to BL
369 23:45:23.904646
370 23:45:23.904944
371 23:45:23.905240
372 23:45:23.905535 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
373 23:45:23.905851 ARM64: Exception handlers installed.
374 23:45:23.906209 ARM64: Testing exception
375 23:45:23.906535 ARM64: Done test exception
376 23:45:23.906836 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
377 23:45:23.907139 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
378 23:45:23.907445 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
379 23:45:23.907875 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
380 23:45:23.908187 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
381 23:45:23.908487 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
382 23:45:23.908786 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
383 23:45:23.909086 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
384 23:45:23.909384 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
385 23:45:23.909720 WDT: Last reset was cold boot
386 23:45:23.910023 SPI1(PAD0) initialized at 2873684 Hz
387 23:45:23.910467 SPI5(PAD0) initialized at 992727 Hz
388 23:45:23.910835 VBOOT: Loading verstage.
389 23:45:23.911140 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
390 23:45:23.911441 FMAP: Found "FLASH" version 1.1 at 0x20000.
391 23:45:23.911835 FMAP: base = 0x0 size = 0x800000 #areas = 25
392 23:45:23.912146 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
393 23:45:23.912452 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
394 23:45:23.912757 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
395 23:45:23.913057 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
396 23:45:23.913355
397 23:45:23.913705
398 23:45:23.914062 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
399 23:45:23.914430 ARM64: Exception handlers installed.
400 23:45:23.914736 ARM64: Testing exception
401 23:45:23.915065 ARM64: Done test exception
402 23:45:23.915410 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
403 23:45:23.915736 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
404 23:45:23.916056 Probing TPM: . done!
405 23:45:23.916414 TPM ready after 0 ms
406 23:45:23.916717 Connected to device vid:did:rid of 1ae0:0028:00
407 23:45:23.917018 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
408 23:45:23.917367 Initialized TPM device CR50 revision 0
409 23:45:23.917775 tlcl_send_startup: Startup return code is 0
410 23:45:23.918312 TPM: setup succeeded
411 23:45:23.918644 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
412 23:45:23.918954 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
413 23:45:23.919267 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
414 23:45:23.919482 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
415 23:45:23.919726 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
416 23:45:23.919941 in-header: 03 07 00 00 08 00 00 00
417 23:45:23.920155 in-data: aa e4 47 04 13 02 00 00
418 23:45:23.920365 Chrome EC: UHEPI supported
419 23:45:23.920576 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
420 23:45:23.920853 in-header: 03 a9 00 00 08 00 00 00
421 23:45:23.921085 in-data: 84 60 60 08 00 00 00 00
422 23:45:23.921297 Phase 1
423 23:45:23.921507 FMAP: area GBB found @ 3f5000 (12032 bytes)
424 23:45:23.921749 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
425 23:45:23.921966 VB2:vb2_check_recovery() Recovery was requested manually
426 23:45:23.922212 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
427 23:45:23.922435 Recovery requested (1009000e)
428 23:45:23.922646 TPM: Extending digest for VBOOT: boot mode into PCR 0
429 23:45:23.922861 tlcl_extend: response is 0
430 23:45:23.923075 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
431 23:45:23.923285 tlcl_extend: response is 0
432 23:45:23.923496 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
433 23:45:23.923738 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
434 23:45:23.924001 BS: bootblock times (exec / console): total (unknown) / 148 ms
435 23:45:23.924217
436 23:45:23.924393
437 23:45:23.924546 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
438 23:45:23.924704 ARM64: Exception handlers installed.
439 23:45:23.924858 ARM64: Testing exception
440 23:45:23.925011 ARM64: Done test exception
441 23:45:23.925162 pmic_efuse_setting: Set efuses in 11 msecs
442 23:45:23.925316 pmwrap_interface_init: Select PMIF_VLD_RDY
443 23:45:23.925470 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
444 23:45:23.925645 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
445 23:45:23.926063 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
446 23:45:23.926280 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
447 23:45:23.926445 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
448 23:45:23.926604 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
449 23:45:23.926761 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
450 23:45:23.926943 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
451 23:45:23.927102 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
452 23:45:23.927258 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
453 23:45:23.927413 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
454 23:45:23.927569 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
455 23:45:23.927760 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
456 23:45:23.927918 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
457 23:45:23.928073 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
458 23:45:23.928231 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
459 23:45:23.928387 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
460 23:45:23.928542 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
461 23:45:23.928696 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
462 23:45:23.928888 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
463 23:45:23.929056 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
464 23:45:23.929212 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
465 23:45:23.929366 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
466 23:45:23.929490 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
467 23:45:23.929614 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
468 23:45:23.929738 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
469 23:45:23.929861 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
470 23:45:23.929984 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
471 23:45:23.930122 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
472 23:45:23.930337 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
473 23:45:23.930558 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
474 23:45:23.930731 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
475 23:45:23.930926 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
476 23:45:23.931144 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
477 23:45:23.931362 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
478 23:45:23.931565 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
479 23:45:23.931785 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
480 23:45:23.931975 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
481 23:45:23.932144 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
482 23:45:23.932275 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
483 23:45:23.932413 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
484 23:45:23.932595 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
485 23:45:23.932791 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
486 23:45:23.932987 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
487 23:45:23.933195 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
488 23:45:23.933394 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
489 23:45:23.933564 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
490 23:45:23.933693 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
491 23:45:23.933843 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
492 23:45:23.933969 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
493 23:45:23.934105 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
494 23:45:23.934326 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
495 23:45:23.934471 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
496 23:45:23.934592 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
497 23:45:23.934711 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
498 23:45:23.934839 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
499 23:45:23.934945 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
500 23:45:23.935082 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
501 23:45:23.935189 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
502 23:45:23.935292 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x32
503 23:45:23.935395 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
504 23:45:23.935498 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
505 23:45:23.935601 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
506 23:45:23.935704 [RTC]rtc_get_frequency_meter,154: input=15, output=835
507 23:45:23.935805 [RTC]rtc_get_frequency_meter,154: input=7, output=709
508 23:45:23.935907 [RTC]rtc_get_frequency_meter,154: input=11, output=772
509 23:45:23.936009 [RTC]rtc_get_frequency_meter,154: input=13, output=802
510 23:45:23.936110 [RTC]rtc_get_frequency_meter,154: input=12, output=788
511 23:45:23.936210 [RTC]rtc_get_frequency_meter,154: input=12, output=788
512 23:45:23.936311 [RTC]rtc_get_frequency_meter,154: input=13, output=804
513 23:45:23.936413 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
514 23:45:23.936514 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
515 23:45:23.936836 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
516 23:45:23.936955 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
517 23:45:23.937087 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
518 23:45:23.937194 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
519 23:45:23.937299 ADC[4]: Raw value=903400 ID=7
520 23:45:23.937403 ADC[3]: Raw value=214021 ID=1
521 23:45:23.937505 RAM Code: 0x71
522 23:45:23.937607 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
523 23:45:23.937711 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
524 23:45:23.937814 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
525 23:45:23.937918 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
526 23:45:23.938020 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
527 23:45:23.938123 in-header: 03 07 00 00 08 00 00 00
528 23:45:23.938250 in-data: aa e4 47 04 13 02 00 00
529 23:45:23.938353 Chrome EC: UHEPI supported
530 23:45:23.938456 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
531 23:45:23.938560 in-header: 03 a9 00 00 08 00 00 00
532 23:45:23.938662 in-data: 84 60 60 08 00 00 00 00
533 23:45:23.938763 MRC: failed to locate region type 0.
534 23:45:23.938865 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
535 23:45:23.938967 DRAM-K: Running full calibration
536 23:45:23.939070 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
537 23:45:23.939172 header.status = 0x0
538 23:45:23.939308 header.version = 0x6 (expected: 0x6)
539 23:45:23.939397 header.size = 0xd00 (expected: 0xd00)
540 23:45:23.939483 header.flags = 0x0
541 23:45:23.939570 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
542 23:45:23.939658 read SPI 0x72590 0x1c583: 12497 us, 9290 KB/s, 74.320 Mbps
543 23:45:23.939746 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
544 23:45:23.939833 dram_init: ddr_geometry: 2
545 23:45:23.939919 [EMI] MDL number = 2
546 23:45:23.940005 [EMI] Get MDL freq = 0
547 23:45:23.940092 dram_init: ddr_type: 0
548 23:45:23.940178 is_discrete_lpddr4: 1
549 23:45:23.940265 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
550 23:45:23.940352
551 23:45:23.940439
552 23:45:23.940543 [Bian_co] ETT version 0.0.0.1
553 23:45:23.940634 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
554 23:45:23.940722
555 23:45:23.940809 dramc_set_vcore_voltage set vcore to 650000
556 23:45:23.940895 Read voltage for 800, 4
557 23:45:23.940982 Vio18 = 0
558 23:45:23.941068 Vcore = 650000
559 23:45:23.941153 Vdram = 0
560 23:45:23.941239 Vddq = 0
561 23:45:23.941325 Vmddr = 0
562 23:45:23.941411 dram_init: config_dvfs: 1
563 23:45:23.941497 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
564 23:45:23.941583 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
565 23:45:23.941670 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
566 23:45:23.941757 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
567 23:45:23.941844 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
568 23:45:23.941930 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
569 23:45:23.942017 MEM_TYPE=3, freq_sel=18
570 23:45:23.942103 sv_algorithm_assistance_LP4_1600
571 23:45:23.942197 ============ PULL DRAM RESETB DOWN ============
572 23:45:23.942285 ========== PULL DRAM RESETB DOWN end =========
573 23:45:23.942373 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
574 23:45:23.942459 ===================================
575 23:45:23.942546 LPDDR4 DRAM CONFIGURATION
576 23:45:23.942632 ===================================
577 23:45:23.942718 EX_ROW_EN[0] = 0x0
578 23:45:23.942804 EX_ROW_EN[1] = 0x0
579 23:45:23.942890 LP4Y_EN = 0x0
580 23:45:23.942976 WORK_FSP = 0x0
581 23:45:23.943061 WL = 0x2
582 23:45:23.943147 RL = 0x2
583 23:45:23.943233 BL = 0x2
584 23:45:23.943318 RPST = 0x0
585 23:45:23.943404 RD_PRE = 0x0
586 23:45:23.943489 WR_PRE = 0x1
587 23:45:23.943575 WR_PST = 0x0
588 23:45:23.943659 DBI_WR = 0x0
589 23:45:23.943744 DBI_RD = 0x0
590 23:45:23.943829 OTF = 0x1
591 23:45:23.943930 ===================================
592 23:45:23.944017 ===================================
593 23:45:23.944104 ANA top config
594 23:45:23.944190 ===================================
595 23:45:23.944284 DLL_ASYNC_EN = 0
596 23:45:23.944359 ALL_SLAVE_EN = 1
597 23:45:23.944434 NEW_RANK_MODE = 1
598 23:45:23.944514 DLL_IDLE_MODE = 1
599 23:45:23.944590 LP45_APHY_COMB_EN = 1
600 23:45:23.944665 TX_ODT_DIS = 1
601 23:45:23.944740 NEW_8X_MODE = 1
602 23:45:23.944815 ===================================
603 23:45:23.944892 ===================================
604 23:45:23.944967 data_rate = 1600
605 23:45:23.945043 CKR = 1
606 23:45:23.945118 DQ_P2S_RATIO = 8
607 23:45:23.945193 ===================================
608 23:45:23.945268 CA_P2S_RATIO = 8
609 23:45:23.945344 DQ_CA_OPEN = 0
610 23:45:23.945419 DQ_SEMI_OPEN = 0
611 23:45:23.945494 CA_SEMI_OPEN = 0
612 23:45:23.945568 CA_FULL_RATE = 0
613 23:45:23.945643 DQ_CKDIV4_EN = 1
614 23:45:23.945718 CA_CKDIV4_EN = 1
615 23:45:23.945794 CA_PREDIV_EN = 0
616 23:45:23.945869 PH8_DLY = 0
617 23:45:23.945944 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
618 23:45:23.946019 DQ_AAMCK_DIV = 4
619 23:45:23.946094 CA_AAMCK_DIV = 4
620 23:45:23.946177 CA_ADMCK_DIV = 4
621 23:45:23.946254 DQ_TRACK_CA_EN = 0
622 23:45:23.946330 CA_PICK = 800
623 23:45:23.946405 CA_MCKIO = 800
624 23:45:23.946479 MCKIO_SEMI = 0
625 23:45:23.946554 PLL_FREQ = 3068
626 23:45:23.946629 DQ_UI_PI_RATIO = 32
627 23:45:23.946705 CA_UI_PI_RATIO = 0
628 23:45:23.946780 ===================================
629 23:45:23.946856 ===================================
630 23:45:23.946931 memory_type:LPDDR4
631 23:45:23.947009 GP_NUM : 10
632 23:45:23.947085 SRAM_EN : 1
633 23:45:23.947174 MD32_EN : 0
634 23:45:23.947475 ===================================
635 23:45:23.947563 [ANA_INIT] >>>>>>>>>>>>>>
636 23:45:23.947641 <<<<<< [CONFIGURE PHASE]: ANA_TX
637 23:45:23.947721 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
638 23:45:23.947798 ===================================
639 23:45:23.947875 data_rate = 1600,PCW = 0X7600
640 23:45:23.947951 ===================================
641 23:45:23.948027 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
642 23:45:23.948103 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
643 23:45:23.948180 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
644 23:45:23.948256 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
645 23:45:23.948332 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
646 23:45:23.948408 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
647 23:45:23.948484 [ANA_INIT] flow start
648 23:45:23.948559 [ANA_INIT] PLL >>>>>>>>
649 23:45:23.948634 [ANA_INIT] PLL <<<<<<<<
650 23:45:23.948708 [ANA_INIT] MIDPI >>>>>>>>
651 23:45:23.948784 [ANA_INIT] MIDPI <<<<<<<<
652 23:45:23.948858 [ANA_INIT] DLL >>>>>>>>
653 23:45:23.948933 [ANA_INIT] flow end
654 23:45:23.949008 ============ LP4 DIFF to SE enter ============
655 23:45:23.949084 ============ LP4 DIFF to SE exit ============
656 23:45:23.949160 [ANA_INIT] <<<<<<<<<<<<<
657 23:45:23.949235 [Flow] Enable top DCM control >>>>>
658 23:45:23.949316 [Flow] Enable top DCM control <<<<<
659 23:45:23.949382 Enable DLL master slave shuffle
660 23:45:23.949449 ==============================================================
661 23:45:23.949516 Gating Mode config
662 23:45:23.949583 ==============================================================
663 23:45:23.949650 Config description:
664 23:45:23.949717 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
665 23:45:23.949786 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
666 23:45:23.949853 SELPH_MODE 0: By rank 1: By Phase
667 23:45:23.949920 ==============================================================
668 23:45:23.950000 GAT_TRACK_EN = 1
669 23:45:23.950068 RX_GATING_MODE = 2
670 23:45:23.950135 RX_GATING_TRACK_MODE = 2
671 23:45:23.950212 SELPH_MODE = 1
672 23:45:23.950280 PICG_EARLY_EN = 1
673 23:45:23.950347 VALID_LAT_VALUE = 1
674 23:45:23.950414 ==============================================================
675 23:45:23.950482 Enter into Gating configuration >>>>
676 23:45:23.950549 Exit from Gating configuration <<<<
677 23:45:23.950615 Enter into DVFS_PRE_config >>>>>
678 23:45:23.950682 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
679 23:45:23.950753 Exit from DVFS_PRE_config <<<<<
680 23:45:23.950820 Enter into PICG configuration >>>>
681 23:45:23.950887 Exit from PICG configuration <<<<
682 23:45:23.950954 [RX_INPUT] configuration >>>>>
683 23:45:23.951020 [RX_INPUT] configuration <<<<<
684 23:45:23.951087 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
685 23:45:23.951154 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
686 23:45:23.951221 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
687 23:45:23.951289 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
688 23:45:23.951357 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
689 23:45:23.951424 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
690 23:45:23.951492 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
691 23:45:23.951559 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
692 23:45:23.951625 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
693 23:45:23.951700 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
694 23:45:23.951768 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
695 23:45:23.951835 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
696 23:45:23.951902 ===================================
697 23:45:23.951969 LPDDR4 DRAM CONFIGURATION
698 23:45:23.952040 ===================================
699 23:45:23.952124 EX_ROW_EN[0] = 0x0
700 23:45:23.952191 EX_ROW_EN[1] = 0x0
701 23:45:23.952258 LP4Y_EN = 0x0
702 23:45:23.952324 WORK_FSP = 0x0
703 23:45:23.952391 WL = 0x2
704 23:45:23.952457 RL = 0x2
705 23:45:23.952525 BL = 0x2
706 23:45:23.952591 RPST = 0x0
707 23:45:23.952658 RD_PRE = 0x0
708 23:45:23.952723 WR_PRE = 0x1
709 23:45:23.952789 WR_PST = 0x0
710 23:45:23.952856 DBI_WR = 0x0
711 23:45:23.952923 DBI_RD = 0x0
712 23:45:23.952988 OTF = 0x1
713 23:45:23.953055 ===================================
714 23:45:23.953122 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
715 23:45:23.953189 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
716 23:45:23.953256 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
717 23:45:23.953323 ===================================
718 23:45:23.953390 LPDDR4 DRAM CONFIGURATION
719 23:45:23.953458 ===================================
720 23:45:23.953524 EX_ROW_EN[0] = 0x10
721 23:45:23.953591 EX_ROW_EN[1] = 0x0
722 23:45:23.953667 LP4Y_EN = 0x0
723 23:45:23.953736 WORK_FSP = 0x0
724 23:45:23.953802 WL = 0x2
725 23:45:23.953868 RL = 0x2
726 23:45:23.953934 BL = 0x2
727 23:45:23.954000 RPST = 0x0
728 23:45:23.954065 RD_PRE = 0x0
729 23:45:23.954132 WR_PRE = 0x1
730 23:45:23.954229 WR_PST = 0x0
731 23:45:23.954308 DBI_WR = 0x0
732 23:45:23.954368 DBI_RD = 0x0
733 23:45:23.954427 OTF = 0x1
734 23:45:23.954487 ===================================
735 23:45:23.954548 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
736 23:45:23.954609 nWR fixed to 40
737 23:45:23.954670 [ModeRegInit_LP4] CH0 RK0
738 23:45:23.954730 [ModeRegInit_LP4] CH0 RK1
739 23:45:23.954790 [ModeRegInit_LP4] CH1 RK0
740 23:45:23.954849 [ModeRegInit_LP4] CH1 RK1
741 23:45:23.954917 match AC timing 13
742 23:45:23.954977 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
743 23:45:23.955244 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
744 23:45:23.955319 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
745 23:45:23.955383 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
746 23:45:23.955444 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
747 23:45:23.955506 [EMI DOE] emi_dcm 0
748 23:45:23.955566 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
749 23:45:23.955627 ==
750 23:45:23.955687 Dram Type= 6, Freq= 0, CH_0, rank 0
751 23:45:23.955748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
752 23:45:23.955809 ==
753 23:45:23.955870 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
754 23:45:23.955931 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
755 23:45:23.955992 [CA 0] Center 37 (7~68) winsize 62
756 23:45:23.956053 [CA 1] Center 37 (6~68) winsize 63
757 23:45:23.956113 [CA 2] Center 34 (4~65) winsize 62
758 23:45:23.956174 [CA 3] Center 34 (4~65) winsize 62
759 23:45:23.956235 [CA 4] Center 33 (3~64) winsize 62
760 23:45:23.956295 [CA 5] Center 33 (3~64) winsize 62
761 23:45:23.956355
762 23:45:23.956415 [CmdBusTrainingLP45] Vref(ca) range 1: 32
763 23:45:23.956475
764 23:45:23.956535 [CATrainingPosCal] consider 1 rank data
765 23:45:23.956596 u2DelayCellTimex100 = 270/100 ps
766 23:45:23.956656 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
767 23:45:23.956717 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
768 23:45:23.956789 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
769 23:45:23.956850 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
770 23:45:23.956911 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
771 23:45:23.956971 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
772 23:45:23.957032
773 23:45:23.957091 CA PerBit enable=1, Macro0, CA PI delay=33
774 23:45:23.957151
775 23:45:23.957210 [CBTSetCACLKResult] CA Dly = 33
776 23:45:23.957270 CS Dly: 6 (0~37)
777 23:45:23.957330 ==
778 23:45:23.957390 Dram Type= 6, Freq= 0, CH_0, rank 1
779 23:45:23.957451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
780 23:45:23.957512 ==
781 23:45:23.957572 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
782 23:45:23.957633 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
783 23:45:23.957694 [CA 0] Center 37 (6~68) winsize 63
784 23:45:23.957755 [CA 1] Center 37 (7~68) winsize 62
785 23:45:23.957815 [CA 2] Center 34 (4~65) winsize 62
786 23:45:23.957876 [CA 3] Center 34 (4~65) winsize 62
787 23:45:23.957936 [CA 4] Center 33 (3~64) winsize 62
788 23:45:23.957995 [CA 5] Center 33 (3~64) winsize 62
789 23:45:23.958055
790 23:45:23.958115 [CmdBusTrainingLP45] Vref(ca) range 1: 34
791 23:45:23.958183
792 23:45:23.958243 [CATrainingPosCal] consider 2 rank data
793 23:45:23.958304 u2DelayCellTimex100 = 270/100 ps
794 23:45:23.958363 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
795 23:45:23.958424 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
796 23:45:23.958484 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
797 23:45:23.958543 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
798 23:45:23.958602 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
799 23:45:23.958662 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
800 23:45:23.958722
801 23:45:23.958781 CA PerBit enable=1, Macro0, CA PI delay=33
802 23:45:23.958842
803 23:45:23.958901 [CBTSetCACLKResult] CA Dly = 33
804 23:45:23.958961 CS Dly: 6 (0~38)
805 23:45:23.959021
806 23:45:23.959081 ----->DramcWriteLeveling(PI) begin...
807 23:45:23.959143 ==
808 23:45:23.959204 Dram Type= 6, Freq= 0, CH_0, rank 0
809 23:45:23.959275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
810 23:45:23.959329 ==
811 23:45:23.959384 Write leveling (Byte 0): 33 => 33
812 23:45:23.959439 Write leveling (Byte 1): 28 => 28
813 23:45:23.959493 DramcWriteLeveling(PI) end<-----
814 23:45:23.959548
815 23:45:23.959602 ==
816 23:45:23.959656 Dram Type= 6, Freq= 0, CH_0, rank 0
817 23:45:23.959721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
818 23:45:23.959777 ==
819 23:45:23.959832 [Gating] SW mode calibration
820 23:45:23.959887 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
821 23:45:23.959942 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
822 23:45:23.959997 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
823 23:45:23.960053 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
824 23:45:23.960108 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
825 23:45:23.960163 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
826 23:45:23.960217 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 23:45:23.960272 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 23:45:23.960327 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 23:45:23.960381 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 23:45:23.960436 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 23:45:23.960491 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 23:45:23.960546 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 23:45:23.960601 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
834 23:45:23.960655 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
835 23:45:23.960710 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
836 23:45:23.960765 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
837 23:45:23.960820 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
838 23:45:23.960874 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 23:45:23.960929 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 23:45:23.960983 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
841 23:45:23.961038 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
842 23:45:23.961093 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 23:45:23.961147 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 23:45:23.961202 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 23:45:23.961256 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 23:45:23.961311 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
847 23:45:23.961365 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
848 23:45:23.961419 0 9 8 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
849 23:45:23.961474 0 9 12 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
850 23:45:23.961529 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
851 23:45:23.961773 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
852 23:45:23.961835 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
853 23:45:23.961891 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
854 23:45:23.961946 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
855 23:45:23.962002 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
856 23:45:23.962056 0 10 8 | B1->B0 | 3434 2929 | 1 0 | (1 1) (0 0)
857 23:45:23.962111 0 10 12 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (1 0)
858 23:45:23.962172 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 23:45:23.962228 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 23:45:23.962283 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 23:45:23.962338 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 23:45:23.962392 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 23:45:23.962446 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
864 23:45:23.962501 0 11 8 | B1->B0 | 2727 3939 | 0 0 | (0 0) (0 0)
865 23:45:23.962555 0 11 12 | B1->B0 | 3838 4646 | 0 0 | (1 1) (0 0)
866 23:45:23.962609 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
867 23:45:23.962664 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
868 23:45:23.962718 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
869 23:45:23.962773 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
870 23:45:23.962828 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
871 23:45:23.962882 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
872 23:45:23.962936 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
873 23:45:23.962992 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
874 23:45:23.963046 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
875 23:45:23.963101 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 23:45:23.963155 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 23:45:23.963209 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 23:45:23.963263 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 23:45:23.963328 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 23:45:23.963383 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 23:45:23.963437 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 23:45:23.963492 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 23:45:23.963547 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 23:45:23.963601 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
885 23:45:23.963656 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
886 23:45:23.963710 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
887 23:45:23.963765 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
888 23:45:23.963819 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
889 23:45:23.963873 Total UI for P1: 0, mck2ui 16
890 23:45:23.963929 best dqsien dly found for B0: ( 0, 14, 4)
891 23:45:23.963984 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
892 23:45:23.964039 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
893 23:45:23.964093 Total UI for P1: 0, mck2ui 16
894 23:45:23.964148 best dqsien dly found for B1: ( 0, 14, 10)
895 23:45:23.964203 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
896 23:45:23.964270 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
897 23:45:23.964323
898 23:45:23.964374 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
899 23:45:23.964427 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
900 23:45:23.964478 [Gating] SW calibration Done
901 23:45:23.964530 ==
902 23:45:23.964581 Dram Type= 6, Freq= 0, CH_0, rank 0
903 23:45:23.964634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
904 23:45:23.964686 ==
905 23:45:23.964741 RX Vref Scan: 0
906 23:45:23.964806
907 23:45:23.964858 RX Vref 0 -> 0, step: 1
908 23:45:23.964910
909 23:45:23.964962 RX Delay -130 -> 252, step: 16
910 23:45:23.965014 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
911 23:45:23.965066 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
912 23:45:23.965119 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
913 23:45:23.965170 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
914 23:45:23.965222 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
915 23:45:23.965274 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
916 23:45:23.965327 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
917 23:45:23.965378 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
918 23:45:23.965429 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
919 23:45:23.965481 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
920 23:45:23.965533 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
921 23:45:23.965585 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
922 23:45:23.965637 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
923 23:45:23.965689 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
924 23:45:23.965741 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
925 23:45:23.965792 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
926 23:45:23.965845 ==
927 23:45:23.965897 Dram Type= 6, Freq= 0, CH_0, rank 0
928 23:45:23.965949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
929 23:45:23.966001 ==
930 23:45:23.966053 DQS Delay:
931 23:45:23.966105 DQS0 = 0, DQS1 = 0
932 23:45:23.966157 DQM Delay:
933 23:45:23.966250 DQM0 = 85, DQM1 = 71
934 23:45:23.966302 DQ Delay:
935 23:45:23.966354 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
936 23:45:23.966406 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
937 23:45:23.966458 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
938 23:45:23.966520 DQ12 =69, DQ13 =77, DQ14 =85, DQ15 =77
939 23:45:23.966578
940 23:45:23.966630
941 23:45:23.966681 ==
942 23:45:23.966733 Dram Type= 6, Freq= 0, CH_0, rank 0
943 23:45:23.966785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
944 23:45:23.966838 ==
945 23:45:23.966890
946 23:45:23.966941
947 23:45:23.966992 TX Vref Scan disable
948 23:45:23.967044 == TX Byte 0 ==
949 23:45:23.967095 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
950 23:45:23.967148 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
951 23:45:23.967200 == TX Byte 1 ==
952 23:45:23.967253 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
953 23:45:23.967305 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
954 23:45:23.967357 ==
955 23:45:23.967408 Dram Type= 6, Freq= 0, CH_0, rank 0
956 23:45:23.967461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
957 23:45:23.967513 ==
958 23:45:23.967564 TX Vref=22, minBit 5, minWin=27, winSum=442
959 23:45:23.967804 TX Vref=24, minBit 3, minWin=27, winSum=445
960 23:45:23.967864 TX Vref=26, minBit 3, minWin=27, winSum=445
961 23:45:23.967917 TX Vref=28, minBit 8, minWin=27, winSum=448
962 23:45:23.967970 TX Vref=30, minBit 9, minWin=27, winSum=450
963 23:45:23.968023 TX Vref=32, minBit 9, minWin=27, winSum=446
964 23:45:23.968076 [TxChooseVref] Worse bit 9, Min win 27, Win sum 450, Final Vref 30
965 23:45:23.968128
966 23:45:23.968180 Final TX Range 1 Vref 30
967 23:45:23.968232
968 23:45:23.968283 ==
969 23:45:23.968336 Dram Type= 6, Freq= 0, CH_0, rank 0
970 23:45:23.968388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
971 23:45:23.968441 ==
972 23:45:23.968493
973 23:45:23.968544
974 23:45:23.968596 TX Vref Scan disable
975 23:45:23.968648 == TX Byte 0 ==
976 23:45:23.968700 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
977 23:45:23.968763 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
978 23:45:23.968826 == TX Byte 1 ==
979 23:45:23.968885 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
980 23:45:23.968937 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
981 23:45:23.968989
982 23:45:23.969041 [DATLAT]
983 23:45:23.969093 Freq=800, CH0 RK0
984 23:45:23.969145
985 23:45:23.969197 DATLAT Default: 0xa
986 23:45:23.969249 0, 0xFFFF, sum = 0
987 23:45:23.969303 1, 0xFFFF, sum = 0
988 23:45:23.969356 2, 0xFFFF, sum = 0
989 23:45:23.969409 3, 0xFFFF, sum = 0
990 23:45:23.969462 4, 0xFFFF, sum = 0
991 23:45:23.969515 5, 0xFFFF, sum = 0
992 23:45:23.969568 6, 0xFFFF, sum = 0
993 23:45:23.969620 7, 0xFFFF, sum = 0
994 23:45:23.969683 8, 0xFFFF, sum = 0
995 23:45:23.969736 9, 0x0, sum = 1
996 23:45:23.969789 10, 0x0, sum = 2
997 23:45:23.969842 11, 0x0, sum = 3
998 23:45:23.969896 12, 0x0, sum = 4
999 23:45:23.969948 best_step = 10
1000 23:45:23.970000
1001 23:45:23.970052 ==
1002 23:45:23.970103 Dram Type= 6, Freq= 0, CH_0, rank 0
1003 23:45:23.970155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1004 23:45:23.970254 ==
1005 23:45:23.970307 RX Vref Scan: 1
1006 23:45:23.970359
1007 23:45:23.970411 Set Vref Range= 32 -> 127
1008 23:45:23.970463
1009 23:45:23.970515 RX Vref 32 -> 127, step: 1
1010 23:45:23.970566
1011 23:45:23.970618 RX Delay -111 -> 252, step: 8
1012 23:45:23.970670
1013 23:45:23.970726 Set Vref, RX VrefLevel [Byte0]: 32
1014 23:45:23.970786 [Byte1]: 32
1015 23:45:23.970838
1016 23:45:23.970889 Set Vref, RX VrefLevel [Byte0]: 33
1017 23:45:23.970943 [Byte1]: 33
1018 23:45:23.970995
1019 23:45:23.971047 Set Vref, RX VrefLevel [Byte0]: 34
1020 23:45:23.971099 [Byte1]: 34
1021 23:45:23.971151
1022 23:45:23.971202 Set Vref, RX VrefLevel [Byte0]: 35
1023 23:45:23.971254 [Byte1]: 35
1024 23:45:23.971305
1025 23:45:23.971366 Set Vref, RX VrefLevel [Byte0]: 36
1026 23:45:23.971421 [Byte1]: 36
1027 23:45:23.971474
1028 23:45:23.971525 Set Vref, RX VrefLevel [Byte0]: 37
1029 23:45:23.971577 [Byte1]: 37
1030 23:45:23.971628
1031 23:45:23.971679 Set Vref, RX VrefLevel [Byte0]: 38
1032 23:45:23.971730 [Byte1]: 38
1033 23:45:23.971781
1034 23:45:23.971832 Set Vref, RX VrefLevel [Byte0]: 39
1035 23:45:23.971889 [Byte1]: 39
1036 23:45:23.971941
1037 23:45:23.971992 Set Vref, RX VrefLevel [Byte0]: 40
1038 23:45:23.972043 [Byte1]: 40
1039 23:45:23.972094
1040 23:45:23.972144 Set Vref, RX VrefLevel [Byte0]: 41
1041 23:45:23.972209 [Byte1]: 41
1042 23:45:23.972263
1043 23:45:23.972315 Set Vref, RX VrefLevel [Byte0]: 42
1044 23:45:23.972366 [Byte1]: 42
1045 23:45:23.972417
1046 23:45:23.972468 Set Vref, RX VrefLevel [Byte0]: 43
1047 23:45:23.972519 [Byte1]: 43
1048 23:45:23.972571
1049 23:45:23.972622 Set Vref, RX VrefLevel [Byte0]: 44
1050 23:45:23.972673 [Byte1]: 44
1051 23:45:23.972728
1052 23:45:23.972831 Set Vref, RX VrefLevel [Byte0]: 45
1053 23:45:23.972882 [Byte1]: 45
1054 23:45:23.972933
1055 23:45:23.972983 Set Vref, RX VrefLevel [Byte0]: 46
1056 23:45:23.973035 [Byte1]: 46
1057 23:45:23.973086
1058 23:45:23.973137 Set Vref, RX VrefLevel [Byte0]: 47
1059 23:45:23.973197 [Byte1]: 47
1060 23:45:23.973248
1061 23:45:23.973299 Set Vref, RX VrefLevel [Byte0]: 48
1062 23:45:23.973350 [Byte1]: 48
1063 23:45:23.973402
1064 23:45:23.973453 Set Vref, RX VrefLevel [Byte0]: 49
1065 23:45:23.973504 [Byte1]: 49
1066 23:45:23.973555
1067 23:45:23.973606 Set Vref, RX VrefLevel [Byte0]: 50
1068 23:45:23.973657 [Byte1]: 50
1069 23:45:23.973708
1070 23:45:23.973759 Set Vref, RX VrefLevel [Byte0]: 51
1071 23:45:23.973809 [Byte1]: 51
1072 23:45:23.973860
1073 23:45:23.973910 Set Vref, RX VrefLevel [Byte0]: 52
1074 23:45:23.973961 [Byte1]: 52
1075 23:45:23.974012
1076 23:45:23.974063 Set Vref, RX VrefLevel [Byte0]: 53
1077 23:45:23.974114 [Byte1]: 53
1078 23:45:23.974172
1079 23:45:23.974225 Set Vref, RX VrefLevel [Byte0]: 54
1080 23:45:23.974276 [Byte1]: 54
1081 23:45:23.974327
1082 23:45:23.974377 Set Vref, RX VrefLevel [Byte0]: 55
1083 23:45:23.974429 [Byte1]: 55
1084 23:45:23.974479
1085 23:45:23.974530 Set Vref, RX VrefLevel [Byte0]: 56
1086 23:45:23.974581 [Byte1]: 56
1087 23:45:23.974631
1088 23:45:23.974682 Set Vref, RX VrefLevel [Byte0]: 57
1089 23:45:23.974737 [Byte1]: 57
1090 23:45:23.974817
1091 23:45:23.974905 Set Vref, RX VrefLevel [Byte0]: 58
1092 23:45:23.974966 [Byte1]: 58
1093 23:45:23.975018
1094 23:45:23.975070 Set Vref, RX VrefLevel [Byte0]: 59
1095 23:45:23.975153 [Byte1]: 59
1096 23:45:23.975220
1097 23:45:23.975271 Set Vref, RX VrefLevel [Byte0]: 60
1098 23:45:23.975323 [Byte1]: 60
1099 23:45:23.975386
1100 23:45:23.975441 Set Vref, RX VrefLevel [Byte0]: 61
1101 23:45:23.975493 [Byte1]: 61
1102 23:45:23.975544
1103 23:45:23.975595 Set Vref, RX VrefLevel [Byte0]: 62
1104 23:45:23.975647 [Byte1]: 62
1105 23:45:23.975699
1106 23:45:23.975749 Set Vref, RX VrefLevel [Byte0]: 63
1107 23:45:23.975800 [Byte1]: 63
1108 23:45:23.975851
1109 23:45:23.975901 Set Vref, RX VrefLevel [Byte0]: 64
1110 23:45:23.975952 [Byte1]: 64
1111 23:45:23.976003
1112 23:45:23.976054 Set Vref, RX VrefLevel [Byte0]: 65
1113 23:45:23.976106 [Byte1]: 65
1114 23:45:23.976156
1115 23:45:23.976207 Set Vref, RX VrefLevel [Byte0]: 66
1116 23:45:23.976258 [Byte1]: 66
1117 23:45:23.976309
1118 23:45:23.976361 Set Vref, RX VrefLevel [Byte0]: 67
1119 23:45:23.976412 [Byte1]: 67
1120 23:45:23.976462
1121 23:45:23.976513 Set Vref, RX VrefLevel [Byte0]: 68
1122 23:45:23.976564 [Byte1]: 68
1123 23:45:23.976615
1124 23:45:23.976665 Set Vref, RX VrefLevel [Byte0]: 69
1125 23:45:23.976721 [Byte1]: 69
1126 23:45:23.976779
1127 23:45:23.977029 Set Vref, RX VrefLevel [Byte0]: 70
1128 23:45:23.977092 [Byte1]: 70
1129 23:45:23.977145
1130 23:45:23.977197 Set Vref, RX VrefLevel [Byte0]: 71
1131 23:45:23.977249 [Byte1]: 71
1132 23:45:23.977301
1133 23:45:23.977351 Set Vref, RX VrefLevel [Byte0]: 72
1134 23:45:23.977403 [Byte1]: 72
1135 23:45:23.977455
1136 23:45:23.977506 Set Vref, RX VrefLevel [Byte0]: 73
1137 23:45:23.977557 [Byte1]: 73
1138 23:45:23.977609
1139 23:45:23.977661 Set Vref, RX VrefLevel [Byte0]: 74
1140 23:45:23.977712 [Byte1]: 74
1141 23:45:23.977763
1142 23:45:23.977813 Set Vref, RX VrefLevel [Byte0]: 75
1143 23:45:23.977864 [Byte1]: 75
1144 23:45:23.977915
1145 23:45:23.977966 Set Vref, RX VrefLevel [Byte0]: 76
1146 23:45:23.978017 [Byte1]: 76
1147 23:45:23.978068
1148 23:45:23.978126 Set Vref, RX VrefLevel [Byte0]: 77
1149 23:45:23.978219 [Byte1]: 77
1150 23:45:23.978271
1151 23:45:23.978322 Set Vref, RX VrefLevel [Byte0]: 78
1152 23:45:23.978374 [Byte1]: 78
1153 23:45:23.978444
1154 23:45:23.978496 Final RX Vref Byte 0 = 61 to rank0
1155 23:45:23.978548 Final RX Vref Byte 1 = 61 to rank0
1156 23:45:23.978600 Final RX Vref Byte 0 = 61 to rank1
1157 23:45:23.978652 Final RX Vref Byte 1 = 61 to rank1==
1158 23:45:23.978707 Dram Type= 6, Freq= 0, CH_0, rank 0
1159 23:45:23.978775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1160 23:45:23.978831 ==
1161 23:45:23.978883 DQS Delay:
1162 23:45:23.978934 DQS0 = 0, DQS1 = 0
1163 23:45:23.978986 DQM Delay:
1164 23:45:23.979036 DQM0 = 87, DQM1 = 74
1165 23:45:23.979088 DQ Delay:
1166 23:45:23.979139 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =80
1167 23:45:23.979191 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =100
1168 23:45:23.979242 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1169 23:45:23.979294 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =80
1170 23:45:23.979345
1171 23:45:23.979396
1172 23:45:23.979446 [DQSOSCAuto] RK0, (LSB)MR18= 0x4324, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 393 ps
1173 23:45:23.979510 CH0 RK0: MR19=606, MR18=4324
1174 23:45:23.979563 CH0_RK0: MR19=0x606, MR18=0x4324, DQSOSC=393, MR23=63, INC=95, DEC=63
1175 23:45:23.979615
1176 23:45:23.979666 ----->DramcWriteLeveling(PI) begin...
1177 23:45:23.979727 ==
1178 23:45:23.979781 Dram Type= 6, Freq= 0, CH_0, rank 1
1179 23:45:23.979832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1180 23:45:23.979884 ==
1181 23:45:23.979936 Write leveling (Byte 0): 33 => 33
1182 23:45:23.979987 Write leveling (Byte 1): 31 => 31
1183 23:45:23.980039 DramcWriteLeveling(PI) end<-----
1184 23:45:23.980090
1185 23:45:23.980140 ==
1186 23:45:23.980192 Dram Type= 6, Freq= 0, CH_0, rank 1
1187 23:45:23.980243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1188 23:45:23.980295 ==
1189 23:45:23.980347 [Gating] SW mode calibration
1190 23:45:23.980399 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1191 23:45:23.980451 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1192 23:45:23.980502 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1193 23:45:23.980554 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1194 23:45:23.980605 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1195 23:45:23.980657 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 23:45:23.980712 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 23:45:23.980774 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 23:45:23.980863 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 23:45:23.980915 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 23:45:23.980966 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 23:45:23.981017 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 23:45:23.981068 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 23:45:23.981119 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 23:45:23.981170 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 23:45:23.981221 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 23:45:23.981272 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1207 23:45:23.981323 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 23:45:23.981374 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 23:45:23.981425 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1210 23:45:23.981476 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1211 23:45:23.981527 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 23:45:23.981578 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 23:45:23.981629 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 23:45:23.981680 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 23:45:23.981731 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 23:45:23.981782 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 23:45:23.981833 0 9 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
1218 23:45:23.981884 0 9 8 | B1->B0 | 2323 2d2d | 1 0 | (1 1) (0 0)
1219 23:45:23.981935 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1220 23:45:23.981986 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1221 23:45:23.982038 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1222 23:45:23.982089 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1223 23:45:23.982139 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1224 23:45:23.982238 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1225 23:45:23.982290 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1226 23:45:23.982342 0 10 8 | B1->B0 | 2f2f 2828 | 1 1 | (1 0) (1 1)
1227 23:45:23.982393 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1228 23:45:23.982444 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 23:45:23.982495 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 23:45:23.982547 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 23:45:23.982598 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 23:45:23.982649 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 23:45:23.982700 0 11 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
1234 23:45:23.982765 0 11 8 | B1->B0 | 3030 3c3c | 0 0 | (1 1) (0 0)
1235 23:45:23.982817 0 11 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
1236 23:45:23.983057 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1237 23:45:23.983117 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1238 23:45:23.983170 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1239 23:45:23.983221 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1240 23:45:23.983273 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1241 23:45:23.983324 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1242 23:45:23.983375 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1243 23:45:23.983426 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1244 23:45:23.983478 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1245 23:45:23.983529 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1246 23:45:23.983581 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1247 23:45:23.983632 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1248 23:45:23.983683 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1249 23:45:23.983735 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1250 23:45:23.983786 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1251 23:45:23.983838 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1252 23:45:23.983889 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1253 23:45:23.983940 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1254 23:45:23.983991 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1255 23:45:23.984043 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1256 23:45:23.984094 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1257 23:45:23.984146 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1258 23:45:23.984198 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1259 23:45:23.984249 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1260 23:45:23.984301 Total UI for P1: 0, mck2ui 16
1261 23:45:23.984352 best dqsien dly found for B0: ( 0, 14, 8)
1262 23:45:23.984404 Total UI for P1: 0, mck2ui 16
1263 23:45:23.984456 best dqsien dly found for B1: ( 0, 14, 8)
1264 23:45:23.984507 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1265 23:45:23.984558 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1266 23:45:23.984609
1267 23:45:23.984660 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1268 23:45:23.984716 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1269 23:45:23.984777 [Gating] SW calibration Done
1270 23:45:23.984853 ==
1271 23:45:23.984977 Dram Type= 6, Freq= 0, CH_0, rank 1
1272 23:45:23.985036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1273 23:45:23.985090 ==
1274 23:45:23.985142 RX Vref Scan: 0
1275 23:45:23.985209
1276 23:45:23.985262 RX Vref 0 -> 0, step: 1
1277 23:45:23.985314
1278 23:45:23.985365 RX Delay -130 -> 252, step: 16
1279 23:45:23.985417 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1280 23:45:23.985468 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1281 23:45:23.985519 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1282 23:45:23.985571 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1283 23:45:23.985622 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1284 23:45:23.985673 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1285 23:45:23.985724 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1286 23:45:23.985776 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1287 23:45:23.985827 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1288 23:45:23.985878 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
1289 23:45:23.985929 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1290 23:45:23.985981 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1291 23:45:23.986032 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1292 23:45:23.986083 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1293 23:45:23.986134 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1294 23:45:23.986221 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1295 23:45:23.986286 ==
1296 23:45:23.986338 Dram Type= 6, Freq= 0, CH_0, rank 1
1297 23:45:23.986388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1298 23:45:23.986440 ==
1299 23:45:23.986492 DQS Delay:
1300 23:45:23.986543 DQS0 = 0, DQS1 = 0
1301 23:45:23.986594 DQM Delay:
1302 23:45:23.986645 DQM0 = 85, DQM1 = 77
1303 23:45:23.986696 DQ Delay:
1304 23:45:23.986760 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1305 23:45:23.986858 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1306 23:45:23.986939 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1307 23:45:23.986990 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1308 23:45:23.987041
1309 23:45:23.987092
1310 23:45:23.987143 ==
1311 23:45:23.987194 Dram Type= 6, Freq= 0, CH_0, rank 1
1312 23:45:23.987245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1313 23:45:23.987297 ==
1314 23:45:23.987347
1315 23:45:23.987398
1316 23:45:23.987448 TX Vref Scan disable
1317 23:45:23.987499 == TX Byte 0 ==
1318 23:45:23.987550 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1319 23:45:23.987602 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1320 23:45:23.987653 == TX Byte 1 ==
1321 23:45:23.987704 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1322 23:45:23.987756 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1323 23:45:23.987807 ==
1324 23:45:23.987869 Dram Type= 6, Freq= 0, CH_0, rank 1
1325 23:45:23.987924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1326 23:45:23.987977 ==
1327 23:45:23.988028 TX Vref=22, minBit 9, minWin=27, winSum=449
1328 23:45:23.988080 TX Vref=24, minBit 3, minWin=27, winSum=444
1329 23:45:23.988132 TX Vref=26, minBit 11, minWin=27, winSum=446
1330 23:45:23.988183 TX Vref=28, minBit 9, minWin=27, winSum=450
1331 23:45:23.988235 TX Vref=30, minBit 9, minWin=27, winSum=451
1332 23:45:23.988286 TX Vref=32, minBit 9, minWin=27, winSum=446
1333 23:45:23.988336 [TxChooseVref] Worse bit 9, Min win 27, Win sum 451, Final Vref 30
1334 23:45:23.988388
1335 23:45:23.988438 Final TX Range 1 Vref 30
1336 23:45:23.988489
1337 23:45:23.988539 ==
1338 23:45:23.988590 Dram Type= 6, Freq= 0, CH_0, rank 1
1339 23:45:23.988640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1340 23:45:23.988691 ==
1341 23:45:23.988754
1342 23:45:23.988812
1343 23:45:23.988862 TX Vref Scan disable
1344 23:45:23.988913 == TX Byte 0 ==
1345 23:45:23.988964 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1346 23:45:23.989015 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1347 23:45:23.989065 == TX Byte 1 ==
1348 23:45:23.989116 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1349 23:45:23.989167 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1350 23:45:23.989217
1351 23:45:23.989267 [DATLAT]
1352 23:45:23.989317 Freq=800, CH0 RK1
1353 23:45:23.989368
1354 23:45:23.989418 DATLAT Default: 0xa
1355 23:45:23.989468 0, 0xFFFF, sum = 0
1356 23:45:23.989520 1, 0xFFFF, sum = 0
1357 23:45:23.989571 2, 0xFFFF, sum = 0
1358 23:45:23.989814 3, 0xFFFF, sum = 0
1359 23:45:23.989882 4, 0xFFFF, sum = 0
1360 23:45:23.989971 5, 0xFFFF, sum = 0
1361 23:45:23.990023 6, 0xFFFF, sum = 0
1362 23:45:23.990074 7, 0xFFFF, sum = 0
1363 23:45:23.990126 8, 0xFFFF, sum = 0
1364 23:45:23.990202 9, 0x0, sum = 1
1365 23:45:23.990268 10, 0x0, sum = 2
1366 23:45:23.990319 11, 0x0, sum = 3
1367 23:45:23.990371 12, 0x0, sum = 4
1368 23:45:23.990422 best_step = 10
1369 23:45:23.990472
1370 23:45:23.990523 ==
1371 23:45:23.990574 Dram Type= 6, Freq= 0, CH_0, rank 1
1372 23:45:23.990625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1373 23:45:23.990677 ==
1374 23:45:23.990727 RX Vref Scan: 0
1375 23:45:23.990780
1376 23:45:23.990831 RX Vref 0 -> 0, step: 1
1377 23:45:23.990882
1378 23:45:23.990933 RX Delay -95 -> 252, step: 8
1379 23:45:23.990984 iDelay=209, Bit 0, Center 80 (-31 ~ 192) 224
1380 23:45:23.991035 iDelay=209, Bit 1, Center 88 (-31 ~ 208) 240
1381 23:45:23.991086 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1382 23:45:23.991137 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1383 23:45:23.991187 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1384 23:45:23.991238 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1385 23:45:23.991288 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1386 23:45:23.991339 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1387 23:45:23.991389 iDelay=209, Bit 8, Center 68 (-47 ~ 184) 232
1388 23:45:23.991440 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1389 23:45:23.991490 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
1390 23:45:23.991541 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1391 23:45:23.991592 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
1392 23:45:23.991643 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1393 23:45:23.991694 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1394 23:45:23.991744 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1395 23:45:23.991795 ==
1396 23:45:23.991846 Dram Type= 6, Freq= 0, CH_0, rank 1
1397 23:45:23.991897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1398 23:45:23.991948 ==
1399 23:45:23.991999 DQS Delay:
1400 23:45:23.992049 DQS0 = 0, DQS1 = 0
1401 23:45:23.992100 DQM Delay:
1402 23:45:23.992150 DQM0 = 85, DQM1 = 76
1403 23:45:23.992201 DQ Delay:
1404 23:45:23.992252 DQ0 =80, DQ1 =88, DQ2 =80, DQ3 =84
1405 23:45:23.992303 DQ4 =84, DQ5 =76, DQ6 =96, DQ7 =96
1406 23:45:23.992354 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1407 23:45:23.992404 DQ12 =84, DQ13 =80, DQ14 =88, DQ15 =84
1408 23:45:23.992455
1409 23:45:23.992506
1410 23:45:23.992556 [DQSOSCAuto] RK1, (LSB)MR18= 0x4007, (MSB)MR19= 0x606, tDQSOscB0 = 408 ps tDQSOscB1 = 393 ps
1411 23:45:23.992608 CH0 RK1: MR19=606, MR18=4007
1412 23:45:23.992659 CH0_RK1: MR19=0x606, MR18=0x4007, DQSOSC=393, MR23=63, INC=95, DEC=63
1413 23:45:23.992722 [RxdqsGatingPostProcess] freq 800
1414 23:45:23.992774 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1415 23:45:23.992826 Pre-setting of DQS Precalculation
1416 23:45:23.992877 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1417 23:45:23.992928 ==
1418 23:45:23.992980 Dram Type= 6, Freq= 0, CH_1, rank 0
1419 23:45:23.993031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1420 23:45:23.993083 ==
1421 23:45:23.993134 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1422 23:45:23.993186 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1423 23:45:23.993237 [CA 0] Center 36 (6~67) winsize 62
1424 23:45:23.993288 [CA 1] Center 36 (6~67) winsize 62
1425 23:45:23.993339 [CA 2] Center 34 (4~65) winsize 62
1426 23:45:23.993390 [CA 3] Center 34 (3~65) winsize 63
1427 23:45:23.993440 [CA 4] Center 34 (4~65) winsize 62
1428 23:45:23.993491 [CA 5] Center 34 (3~65) winsize 63
1429 23:45:23.993542
1430 23:45:23.993592 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1431 23:45:23.993643
1432 23:45:23.993694 [CATrainingPosCal] consider 1 rank data
1433 23:45:23.993744 u2DelayCellTimex100 = 270/100 ps
1434 23:45:23.993795 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1435 23:45:23.993846 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1436 23:45:23.993897 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1437 23:45:23.993947 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1438 23:45:23.993998 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1439 23:45:23.994048 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1440 23:45:23.994098
1441 23:45:23.994149 CA PerBit enable=1, Macro0, CA PI delay=34
1442 23:45:23.994204
1443 23:45:23.994255 [CBTSetCACLKResult] CA Dly = 34
1444 23:45:23.994306 CS Dly: 5 (0~36)
1445 23:45:23.994357 ==
1446 23:45:23.994407 Dram Type= 6, Freq= 0, CH_1, rank 1
1447 23:45:23.994458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1448 23:45:23.994509 ==
1449 23:45:23.994559 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1450 23:45:23.994611 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1451 23:45:23.994662 [CA 0] Center 36 (6~67) winsize 62
1452 23:45:23.994713 [CA 1] Center 36 (6~67) winsize 62
1453 23:45:23.994764 [CA 2] Center 34 (4~65) winsize 62
1454 23:45:23.994815 [CA 3] Center 34 (3~65) winsize 63
1455 23:45:23.994865 [CA 4] Center 34 (4~65) winsize 62
1456 23:45:23.994916 [CA 5] Center 34 (3~65) winsize 63
1457 23:45:23.994966
1458 23:45:23.995017 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1459 23:45:23.995068
1460 23:45:23.995118 [CATrainingPosCal] consider 2 rank data
1461 23:45:23.995169 u2DelayCellTimex100 = 270/100 ps
1462 23:45:23.995220 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1463 23:45:23.995270 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1464 23:45:23.995321 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1465 23:45:23.995372 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1466 23:45:23.995422 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1467 23:45:23.995472 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1468 23:45:23.995523
1469 23:45:23.995574 CA PerBit enable=1, Macro0, CA PI delay=34
1470 23:45:23.995625
1471 23:45:23.995675 [CBTSetCACLKResult] CA Dly = 34
1472 23:45:23.995725 CS Dly: 6 (0~38)
1473 23:45:23.995775
1474 23:45:23.995826 ----->DramcWriteLeveling(PI) begin...
1475 23:45:23.995878 ==
1476 23:45:23.995929 Dram Type= 6, Freq= 0, CH_1, rank 0
1477 23:45:23.995980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1478 23:45:23.996031 ==
1479 23:45:23.996083 Write leveling (Byte 0): 27 => 27
1480 23:45:23.996133 Write leveling (Byte 1): 30 => 30
1481 23:45:23.996194 DramcWriteLeveling(PI) end<-----
1482 23:45:23.996245
1483 23:45:23.996295 ==
1484 23:45:23.996352 Dram Type= 6, Freq= 0, CH_1, rank 0
1485 23:45:23.996403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1486 23:45:23.996455 ==
1487 23:45:23.996505 [Gating] SW mode calibration
1488 23:45:23.996749 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1489 23:45:23.996812 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1490 23:45:23.996865 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1491 23:45:23.996917 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1492 23:45:23.996968 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 23:45:23.997020 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 23:45:23.997071 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 23:45:23.997122 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 23:45:23.997173 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 23:45:23.997224 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 23:45:23.997275 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 23:45:23.997326 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 23:45:23.997377 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 23:45:23.997427 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 23:45:23.997479 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 23:45:23.997529 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 23:45:23.997580 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 23:45:23.997630 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 23:45:23.997681 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1507 23:45:23.997732 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1508 23:45:23.997783 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1509 23:45:23.997837 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 23:45:23.997895 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 23:45:23.997953 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 23:45:23.998004 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 23:45:23.998055 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 23:45:23.998105 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 23:45:23.998156 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 23:45:23.998218 0 9 8 | B1->B0 | 2d2d 2f2f | 0 0 | (0 0) (0 0)
1517 23:45:23.998268 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1518 23:45:23.998319 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1519 23:45:23.998370 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1520 23:45:23.998420 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1521 23:45:23.998471 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1522 23:45:23.998521 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1523 23:45:23.998571 0 10 4 | B1->B0 | 3232 3434 | 1 1 | (1 0) (1 0)
1524 23:45:23.998621 0 10 8 | B1->B0 | 2e2e 2424 | 1 1 | (1 0) (1 0)
1525 23:45:23.998672 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 23:45:23.998723 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 23:45:23.998774 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 23:45:23.998825 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 23:45:23.998875 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 23:45:23.998925 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 23:45:23.998976 0 11 4 | B1->B0 | 2424 2c2c | 0 0 | (0 0) (0 0)
1532 23:45:23.999027 0 11 8 | B1->B0 | 3a3a 3a3a | 0 0 | (0 0) (1 1)
1533 23:45:23.999077 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1534 23:45:23.999128 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1535 23:45:23.999188 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1536 23:45:23.999240 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1537 23:45:23.999291 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1538 23:45:23.999341 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1539 23:45:23.999392 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1540 23:45:23.999442 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1541 23:45:23.999493 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1542 23:45:23.999543 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1543 23:45:23.999593 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1544 23:45:23.999643 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1545 23:45:23.999694 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1546 23:45:23.999745 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1547 23:45:23.999794 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1548 23:45:23.999848 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1549 23:45:23.999905 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1550 23:45:23.999955 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1551 23:45:24.000006 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1552 23:45:24.000056 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1553 23:45:24.000107 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1554 23:45:24.000157 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1555 23:45:24.000207 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1556 23:45:24.000258 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1557 23:45:24.000308 Total UI for P1: 0, mck2ui 16
1558 23:45:24.000360 best dqsien dly found for B0: ( 0, 14, 4)
1559 23:45:24.000410 Total UI for P1: 0, mck2ui 16
1560 23:45:24.000462 best dqsien dly found for B1: ( 0, 14, 4)
1561 23:45:24.000513 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1562 23:45:24.000564 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1563 23:45:24.000614
1564 23:45:24.000665 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1565 23:45:24.000716 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1566 23:45:24.000767 [Gating] SW calibration Done
1567 23:45:24.000817 ==
1568 23:45:24.000868 Dram Type= 6, Freq= 0, CH_1, rank 0
1569 23:45:24.000918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1570 23:45:24.000969 ==
1571 23:45:24.001020 RX Vref Scan: 0
1572 23:45:24.001071
1573 23:45:24.001121 RX Vref 0 -> 0, step: 1
1574 23:45:24.001171
1575 23:45:24.001222 RX Delay -130 -> 252, step: 16
1576 23:45:24.001273 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1577 23:45:24.001518 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1578 23:45:24.001578 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1579 23:45:24.001630 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1580 23:45:24.001681 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1581 23:45:24.001732 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1582 23:45:24.001783 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1583 23:45:24.001839 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1584 23:45:24.001899 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1585 23:45:24.002042 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1586 23:45:24.002135 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1587 23:45:24.002231 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1588 23:45:24.002317 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1589 23:45:24.002421 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1590 23:45:24.002521 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1591 23:45:24.002610 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1592 23:45:24.002690 ==
1593 23:45:24.002744 Dram Type= 6, Freq= 0, CH_1, rank 0
1594 23:45:24.002796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1595 23:45:24.002864 ==
1596 23:45:24.002946 DQS Delay:
1597 23:45:24.003025 DQS0 = 0, DQS1 = 0
1598 23:45:24.003105 DQM Delay:
1599 23:45:24.003185 DQM0 = 89, DQM1 = 80
1600 23:45:24.003265 DQ Delay:
1601 23:45:24.003345 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1602 23:45:24.003425 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1603 23:45:24.003504 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1604 23:45:24.003584 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =93
1605 23:45:24.003663
1606 23:45:24.003742
1607 23:45:24.003821 ==
1608 23:45:24.003900 Dram Type= 6, Freq= 0, CH_1, rank 0
1609 23:45:24.003981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1610 23:45:24.004060 ==
1611 23:45:24.004140
1612 23:45:24.004218
1613 23:45:24.004297 TX Vref Scan disable
1614 23:45:24.004377 == TX Byte 0 ==
1615 23:45:24.004457 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1616 23:45:24.004538 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1617 23:45:24.004617 == TX Byte 1 ==
1618 23:45:24.004697 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1619 23:45:24.004777 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1620 23:45:24.004856 ==
1621 23:45:24.004936 Dram Type= 6, Freq= 0, CH_1, rank 0
1622 23:45:24.005016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1623 23:45:24.005095 ==
1624 23:45:24.005175 TX Vref=22, minBit 15, minWin=26, winSum=444
1625 23:45:24.005256 TX Vref=24, minBit 8, minWin=27, winSum=448
1626 23:45:24.005337 TX Vref=26, minBit 8, minWin=27, winSum=449
1627 23:45:24.005417 TX Vref=28, minBit 8, minWin=27, winSum=451
1628 23:45:24.005497 TX Vref=30, minBit 9, minWin=27, winSum=450
1629 23:45:24.005577 TX Vref=32, minBit 9, minWin=27, winSum=450
1630 23:45:24.005657 [TxChooseVref] Worse bit 8, Min win 27, Win sum 451, Final Vref 28
1631 23:45:24.005737
1632 23:45:24.005816 Final TX Range 1 Vref 28
1633 23:45:24.005895
1634 23:45:24.005980 ==
1635 23:45:24.006040 Dram Type= 6, Freq= 0, CH_1, rank 0
1636 23:45:24.006092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1637 23:45:24.006144 ==
1638 23:45:24.006239
1639 23:45:24.006290
1640 23:45:24.006341 TX Vref Scan disable
1641 23:45:24.006393 == TX Byte 0 ==
1642 23:45:24.006444 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1643 23:45:24.006496 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1644 23:45:24.006546 == TX Byte 1 ==
1645 23:45:24.006597 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1646 23:45:24.006647 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1647 23:45:24.006699
1648 23:45:24.006750 [DATLAT]
1649 23:45:24.006801 Freq=800, CH1 RK0
1650 23:45:24.006852
1651 23:45:24.006903 DATLAT Default: 0xa
1652 23:45:24.006954 0, 0xFFFF, sum = 0
1653 23:45:24.007005 1, 0xFFFF, sum = 0
1654 23:45:24.007057 2, 0xFFFF, sum = 0
1655 23:45:24.007108 3, 0xFFFF, sum = 0
1656 23:45:24.007159 4, 0xFFFF, sum = 0
1657 23:45:24.007210 5, 0xFFFF, sum = 0
1658 23:45:24.007261 6, 0xFFFF, sum = 0
1659 23:45:24.007312 7, 0xFFFF, sum = 0
1660 23:45:24.007364 8, 0xFFFF, sum = 0
1661 23:45:24.007414 9, 0x0, sum = 1
1662 23:45:24.007466 10, 0x0, sum = 2
1663 23:45:24.007517 11, 0x0, sum = 3
1664 23:45:24.007568 12, 0x0, sum = 4
1665 23:45:24.007618 best_step = 10
1666 23:45:24.007669
1667 23:45:24.007719 ==
1668 23:45:24.007770 Dram Type= 6, Freq= 0, CH_1, rank 0
1669 23:45:24.007821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1670 23:45:24.007873 ==
1671 23:45:24.007923 RX Vref Scan: 1
1672 23:45:24.007974
1673 23:45:24.008024 Set Vref Range= 32 -> 127
1674 23:45:24.008075
1675 23:45:24.008126 RX Vref 32 -> 127, step: 1
1676 23:45:24.008176
1677 23:45:24.008226 RX Delay -95 -> 252, step: 8
1678 23:45:24.008277
1679 23:45:24.008328 Set Vref, RX VrefLevel [Byte0]: 32
1680 23:45:24.008379 [Byte1]: 32
1681 23:45:24.008429
1682 23:45:24.008480 Set Vref, RX VrefLevel [Byte0]: 33
1683 23:45:24.008530 [Byte1]: 33
1684 23:45:24.008581
1685 23:45:24.008631 Set Vref, RX VrefLevel [Byte0]: 34
1686 23:45:24.008683 [Byte1]: 34
1687 23:45:24.008733
1688 23:45:24.008785 Set Vref, RX VrefLevel [Byte0]: 35
1689 23:45:24.008836 [Byte1]: 35
1690 23:45:24.008886
1691 23:45:24.008936 Set Vref, RX VrefLevel [Byte0]: 36
1692 23:45:24.008987 [Byte1]: 36
1693 23:45:24.009038
1694 23:45:24.009088 Set Vref, RX VrefLevel [Byte0]: 37
1695 23:45:24.009139 [Byte1]: 37
1696 23:45:24.009200
1697 23:45:24.009254 Set Vref, RX VrefLevel [Byte0]: 38
1698 23:45:24.009305 [Byte1]: 38
1699 23:45:24.009357
1700 23:45:24.009407 Set Vref, RX VrefLevel [Byte0]: 39
1701 23:45:24.009458 [Byte1]: 39
1702 23:45:24.009509
1703 23:45:24.009560 Set Vref, RX VrefLevel [Byte0]: 40
1704 23:45:24.009610 [Byte1]: 40
1705 23:45:24.009660
1706 23:45:24.009711 Set Vref, RX VrefLevel [Byte0]: 41
1707 23:45:24.009762 [Byte1]: 41
1708 23:45:24.009813
1709 23:45:24.009863 Set Vref, RX VrefLevel [Byte0]: 42
1710 23:45:24.009914 [Byte1]: 42
1711 23:45:24.009965
1712 23:45:24.010015 Set Vref, RX VrefLevel [Byte0]: 43
1713 23:45:24.010066 [Byte1]: 43
1714 23:45:24.010116
1715 23:45:24.010173 Set Vref, RX VrefLevel [Byte0]: 44
1716 23:45:24.010225 [Byte1]: 44
1717 23:45:24.010276
1718 23:45:24.010327 Set Vref, RX VrefLevel [Byte0]: 45
1719 23:45:24.010378 [Byte1]: 45
1720 23:45:24.010428
1721 23:45:24.010479 Set Vref, RX VrefLevel [Byte0]: 46
1722 23:45:24.010546 [Byte1]: 46
1723 23:45:24.010600
1724 23:45:24.010651 Set Vref, RX VrefLevel [Byte0]: 47
1725 23:45:24.010702 [Byte1]: 47
1726 23:45:24.010753
1727 23:45:24.010804 Set Vref, RX VrefLevel [Byte0]: 48
1728 23:45:24.010856 [Byte1]: 48
1729 23:45:24.010907
1730 23:45:24.010958 Set Vref, RX VrefLevel [Byte0]: 49
1731 23:45:24.011009 [Byte1]: 49
1732 23:45:24.011060
1733 23:45:24.011111 Set Vref, RX VrefLevel [Byte0]: 50
1734 23:45:24.011355 [Byte1]: 50
1735 23:45:24.011464
1736 23:45:24.011569 Set Vref, RX VrefLevel [Byte0]: 51
1737 23:45:24.011673 [Byte1]: 51
1738 23:45:24.011776
1739 23:45:24.011865 Set Vref, RX VrefLevel [Byte0]: 52
1740 23:45:24.011951 [Byte1]: 52
1741 23:45:24.012005
1742 23:45:24.012057 Set Vref, RX VrefLevel [Byte0]: 53
1743 23:45:24.012108 [Byte1]: 53
1744 23:45:24.012159
1745 23:45:24.012210 Set Vref, RX VrefLevel [Byte0]: 54
1746 23:45:24.012261 [Byte1]: 54
1747 23:45:24.012312
1748 23:45:24.012363 Set Vref, RX VrefLevel [Byte0]: 55
1749 23:45:24.012414 [Byte1]: 55
1750 23:45:24.012464
1751 23:45:24.012514 Set Vref, RX VrefLevel [Byte0]: 56
1752 23:45:24.012566 [Byte1]: 56
1753 23:45:24.012616
1754 23:45:24.012666 Set Vref, RX VrefLevel [Byte0]: 57
1755 23:45:24.012717 [Byte1]: 57
1756 23:45:24.012767
1757 23:45:24.012818 Set Vref, RX VrefLevel [Byte0]: 58
1758 23:45:24.012885 [Byte1]: 58
1759 23:45:24.012937
1760 23:45:24.012988 Set Vref, RX VrefLevel [Byte0]: 59
1761 23:45:24.013039 [Byte1]: 59
1762 23:45:24.013089
1763 23:45:24.013140 Set Vref, RX VrefLevel [Byte0]: 60
1764 23:45:24.013191 [Byte1]: 60
1765 23:45:24.013242
1766 23:45:24.013292 Set Vref, RX VrefLevel [Byte0]: 61
1767 23:45:24.013343 [Byte1]: 61
1768 23:45:24.013394
1769 23:45:24.013444 Set Vref, RX VrefLevel [Byte0]: 62
1770 23:45:24.013496 [Byte1]: 62
1771 23:45:24.013547
1772 23:45:24.013598 Set Vref, RX VrefLevel [Byte0]: 63
1773 23:45:24.013649 [Byte1]: 63
1774 23:45:24.013700
1775 23:45:24.013751 Set Vref, RX VrefLevel [Byte0]: 64
1776 23:45:24.013801 [Byte1]: 64
1777 23:45:24.013852
1778 23:45:24.013903 Set Vref, RX VrefLevel [Byte0]: 65
1779 23:45:24.013954 [Byte1]: 65
1780 23:45:24.014004
1781 23:45:24.014055 Set Vref, RX VrefLevel [Byte0]: 66
1782 23:45:24.014107 [Byte1]: 66
1783 23:45:24.014157
1784 23:45:24.014218 Set Vref, RX VrefLevel [Byte0]: 67
1785 23:45:24.014269 [Byte1]: 67
1786 23:45:24.014320
1787 23:45:24.014370 Set Vref, RX VrefLevel [Byte0]: 68
1788 23:45:24.014421 [Byte1]: 68
1789 23:45:24.014472
1790 23:45:24.014521 Set Vref, RX VrefLevel [Byte0]: 69
1791 23:45:24.014572 [Byte1]: 69
1792 23:45:24.014622
1793 23:45:24.014672 Set Vref, RX VrefLevel [Byte0]: 70
1794 23:45:24.014722 [Byte1]: 70
1795 23:45:24.014773
1796 23:45:24.014823 Set Vref, RX VrefLevel [Byte0]: 71
1797 23:45:24.014873 [Byte1]: 71
1798 23:45:24.014923
1799 23:45:24.014974 Set Vref, RX VrefLevel [Byte0]: 72
1800 23:45:24.015025 [Byte1]: 72
1801 23:45:24.015075
1802 23:45:24.015125 Set Vref, RX VrefLevel [Byte0]: 73
1803 23:45:24.015176 [Byte1]: 73
1804 23:45:24.015243
1805 23:45:24.015296 Set Vref, RX VrefLevel [Byte0]: 74
1806 23:45:24.015348 [Byte1]: 74
1807 23:45:24.015398
1808 23:45:24.015449 Set Vref, RX VrefLevel [Byte0]: 75
1809 23:45:24.015499 [Byte1]: 75
1810 23:45:24.015550
1811 23:45:24.015601 Final RX Vref Byte 0 = 57 to rank0
1812 23:45:24.015653 Final RX Vref Byte 1 = 64 to rank0
1813 23:45:24.015720 Final RX Vref Byte 0 = 57 to rank1
1814 23:45:24.015771 Final RX Vref Byte 1 = 64 to rank1==
1815 23:45:24.015822 Dram Type= 6, Freq= 0, CH_1, rank 0
1816 23:45:24.015873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1817 23:45:24.015924 ==
1818 23:45:24.015980 DQS Delay:
1819 23:45:24.016045 DQS0 = 0, DQS1 = 0
1820 23:45:24.016097 DQM Delay:
1821 23:45:24.016147 DQM0 = 86, DQM1 = 79
1822 23:45:24.016198 DQ Delay:
1823 23:45:24.016266 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1824 23:45:24.016319 DQ4 =80, DQ5 =100, DQ6 =96, DQ7 =80
1825 23:45:24.016371 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1826 23:45:24.016422 DQ12 =88, DQ13 =84, DQ14 =88, DQ15 =88
1827 23:45:24.016472
1828 23:45:24.016524
1829 23:45:24.016574 [DQSOSCAuto] RK0, (LSB)MR18= 0x3420, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
1830 23:45:24.016626 CH1 RK0: MR19=606, MR18=3420
1831 23:45:24.016677 CH1_RK0: MR19=0x606, MR18=0x3420, DQSOSC=396, MR23=63, INC=94, DEC=62
1832 23:45:24.016728
1833 23:45:24.016778 ----->DramcWriteLeveling(PI) begin...
1834 23:45:24.016830 ==
1835 23:45:24.016881 Dram Type= 6, Freq= 0, CH_1, rank 1
1836 23:45:24.016932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1837 23:45:24.016983 ==
1838 23:45:24.017033 Write leveling (Byte 0): 26 => 26
1839 23:45:24.017084 Write leveling (Byte 1): 31 => 31
1840 23:45:24.017134 DramcWriteLeveling(PI) end<-----
1841 23:45:24.017185
1842 23:45:24.017235 ==
1843 23:45:24.017285 Dram Type= 6, Freq= 0, CH_1, rank 1
1844 23:45:24.017336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1845 23:45:24.017387 ==
1846 23:45:24.017438 [Gating] SW mode calibration
1847 23:45:24.017488 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1848 23:45:24.017540 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1849 23:45:24.017591 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1850 23:45:24.017642 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1851 23:45:24.017693 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 23:45:24.017745 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 23:45:24.017796 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 23:45:24.017846 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 23:45:24.017897 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 23:45:24.017947 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 23:45:24.018009 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 23:45:24.018080 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 23:45:24.018170 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 23:45:24.018260 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 23:45:24.018312 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 23:45:24.018363 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 23:45:24.018413 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 23:45:24.018464 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 23:45:24.018515 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 23:45:24.018565 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1867 23:45:24.018615 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1868 23:45:24.018858 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 23:45:24.018948 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 23:45:24.019062 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 23:45:24.019153 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 23:45:24.019235 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 23:45:24.019288 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 23:45:24.019340 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 23:45:24.019392 0 9 8 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 0)
1876 23:45:24.019443 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1877 23:45:24.019494 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1878 23:45:24.019545 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1879 23:45:24.019596 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1880 23:45:24.019647 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1881 23:45:24.019698 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
1882 23:45:24.019749 0 10 4 | B1->B0 | 3030 3434 | 1 1 | (1 0) (1 0)
1883 23:45:24.019800 0 10 8 | B1->B0 | 2626 2d2d | 0 1 | (0 0) (1 0)
1884 23:45:24.019851 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 23:45:24.019903 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 23:45:24.019954 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 23:45:24.020005 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 23:45:24.020056 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 23:45:24.020110 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 23:45:24.020189 0 11 4 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
1891 23:45:24.020244 0 11 8 | B1->B0 | 4040 3939 | 0 0 | (0 0) (0 0)
1892 23:45:24.020295 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1893 23:45:24.020347 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1894 23:45:24.020397 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1895 23:45:24.020448 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1896 23:45:24.020499 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1897 23:45:24.020550 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1898 23:45:24.020601 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1899 23:45:24.020652 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1900 23:45:24.020702 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1901 23:45:24.020753 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1902 23:45:24.020804 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1903 23:45:24.020853 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1904 23:45:24.020904 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1905 23:45:24.020963 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1906 23:45:24.021016 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1907 23:45:24.021067 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1908 23:45:24.021118 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1909 23:45:24.021168 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1910 23:45:24.021219 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1911 23:45:24.021270 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1912 23:45:24.021321 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1913 23:45:24.021371 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1914 23:45:24.021422 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1915 23:45:24.021472 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1916 23:45:24.021523 Total UI for P1: 0, mck2ui 16
1917 23:45:24.021574 best dqsien dly found for B0: ( 0, 14, 6)
1918 23:45:24.021626 Total UI for P1: 0, mck2ui 16
1919 23:45:24.021677 best dqsien dly found for B1: ( 0, 14, 4)
1920 23:45:24.021728 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1921 23:45:24.021779 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1922 23:45:24.021830
1923 23:45:24.021881 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1924 23:45:24.021932 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1925 23:45:24.021983 [Gating] SW calibration Done
1926 23:45:24.022033 ==
1927 23:45:24.022089 Dram Type= 6, Freq= 0, CH_1, rank 1
1928 23:45:24.022146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1929 23:45:24.022245 ==
1930 23:45:24.022319 RX Vref Scan: 0
1931 23:45:24.022382
1932 23:45:24.022435 RX Vref 0 -> 0, step: 1
1933 23:45:24.022487
1934 23:45:24.022538 RX Delay -130 -> 252, step: 16
1935 23:45:24.022590 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1936 23:45:24.022641 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1937 23:45:24.022692 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1938 23:45:24.022743 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1939 23:45:24.022795 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1940 23:45:24.022845 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1941 23:45:24.022896 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1942 23:45:24.022947 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1943 23:45:24.022998 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1944 23:45:24.023049 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1945 23:45:24.023100 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1946 23:45:24.023150 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1947 23:45:24.023201 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1948 23:45:24.023252 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1949 23:45:24.023302 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1950 23:45:24.023353 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1951 23:45:24.023403 ==
1952 23:45:24.023455 Dram Type= 6, Freq= 0, CH_1, rank 1
1953 23:45:24.023506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1954 23:45:24.023557 ==
1955 23:45:24.023608 DQS Delay:
1956 23:45:24.023658 DQS0 = 0, DQS1 = 0
1957 23:45:24.023709 DQM Delay:
1958 23:45:24.184138 DQM0 = 87, DQM1 = 79
1959 23:45:24.184354 DQ Delay:
1960 23:45:24.184490 DQ0 =85, DQ1 =77, DQ2 =77, DQ3 =85
1961 23:45:24.184616 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1962 23:45:24.184744 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1963 23:45:24.184862 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1964 23:45:24.184975
1965 23:45:24.185105
1966 23:45:24.185216 ==
1967 23:45:24.185337 Dram Type= 6, Freq= 0, CH_1, rank 1
1968 23:45:24.185684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1969 23:45:24.185828 ==
1970 23:45:24.185977
1971 23:45:24.186123
1972 23:45:24.186280 TX Vref Scan disable
1973 23:45:24.186406 == TX Byte 0 ==
1974 23:45:24.186525 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1975 23:45:24.186601 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1976 23:45:24.186675 == TX Byte 1 ==
1977 23:45:24.186745 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1978 23:45:24.186816 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1979 23:45:24.186886 ==
1980 23:45:24.186957 Dram Type= 6, Freq= 0, CH_1, rank 1
1981 23:45:24.187028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1982 23:45:24.187108 ==
1983 23:45:24.187181 TX Vref=22, minBit 8, minWin=26, winSum=443
1984 23:45:24.187252 TX Vref=24, minBit 8, minWin=27, winSum=448
1985 23:45:24.187323 TX Vref=26, minBit 8, minWin=27, winSum=450
1986 23:45:24.187392 TX Vref=28, minBit 8, minWin=27, winSum=449
1987 23:45:24.187462 TX Vref=30, minBit 8, minWin=27, winSum=449
1988 23:45:24.187532 TX Vref=32, minBit 8, minWin=27, winSum=448
1989 23:45:24.187601 [TxChooseVref] Worse bit 8, Min win 27, Win sum 450, Final Vref 26
1990 23:45:24.187671
1991 23:45:24.187741 Final TX Range 1 Vref 26
1992 23:45:24.187810
1993 23:45:24.187879 ==
1994 23:45:24.187947 Dram Type= 6, Freq= 0, CH_1, rank 1
1995 23:45:24.188017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1996 23:45:24.188087 ==
1997 23:45:24.188161
1998 23:45:24.188255
1999 23:45:24.188326 TX Vref Scan disable
2000 23:45:24.188397 == TX Byte 0 ==
2001 23:45:24.188466 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2002 23:45:24.188536 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2003 23:45:24.188604 == TX Byte 1 ==
2004 23:45:24.188673 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
2005 23:45:24.188743 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2006 23:45:24.188812
2007 23:45:24.188880 [DATLAT]
2008 23:45:24.188949 Freq=800, CH1 RK1
2009 23:45:24.189019
2010 23:45:24.189087 DATLAT Default: 0xa
2011 23:45:24.189155 0, 0xFFFF, sum = 0
2012 23:45:24.189226 1, 0xFFFF, sum = 0
2013 23:45:24.189297 2, 0xFFFF, sum = 0
2014 23:45:24.189376 3, 0xFFFF, sum = 0
2015 23:45:24.189455 4, 0xFFFF, sum = 0
2016 23:45:24.189525 5, 0xFFFF, sum = 0
2017 23:45:24.189595 6, 0xFFFF, sum = 0
2018 23:45:24.189664 7, 0xFFFF, sum = 0
2019 23:45:24.189734 8, 0xFFFF, sum = 0
2020 23:45:24.189808 9, 0x0, sum = 1
2021 23:45:24.189884 10, 0x0, sum = 2
2022 23:45:24.189955 11, 0x0, sum = 3
2023 23:45:24.190025 12, 0x0, sum = 4
2024 23:45:24.190095 best_step = 10
2025 23:45:24.190172
2026 23:45:24.190245 ==
2027 23:45:24.190314 Dram Type= 6, Freq= 0, CH_1, rank 1
2028 23:45:24.190384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2029 23:45:24.190464 ==
2030 23:45:24.190534 RX Vref Scan: 0
2031 23:45:24.190603
2032 23:45:24.190672 RX Vref 0 -> 0, step: 1
2033 23:45:24.190741
2034 23:45:24.190809 RX Delay -95 -> 252, step: 8
2035 23:45:24.190878 iDelay=217, Bit 0, Center 88 (-23 ~ 200) 224
2036 23:45:24.190948 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2037 23:45:24.191016 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
2038 23:45:24.191086 iDelay=217, Bit 3, Center 84 (-23 ~ 192) 216
2039 23:45:24.191155 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2040 23:45:24.191224 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2041 23:45:24.191292 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2042 23:45:24.191378 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2043 23:45:24.191456 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2044 23:45:24.191526 iDelay=217, Bit 9, Center 68 (-47 ~ 184) 232
2045 23:45:24.191595 iDelay=217, Bit 10, Center 84 (-31 ~ 200) 232
2046 23:45:24.191665 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
2047 23:45:24.191734 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
2048 23:45:24.191809 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2049 23:45:24.191881 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2050 23:45:24.191951 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2051 23:45:24.192020 ==
2052 23:45:24.192090 Dram Type= 6, Freq= 0, CH_1, rank 1
2053 23:45:24.192160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2054 23:45:24.192230 ==
2055 23:45:24.192305 DQS Delay:
2056 23:45:24.192374 DQS0 = 0, DQS1 = 0
2057 23:45:24.192444 DQM Delay:
2058 23:45:24.192522 DQM0 = 86, DQM1 = 78
2059 23:45:24.192596 DQ Delay:
2060 23:45:24.192666 DQ0 =88, DQ1 =80, DQ2 =76, DQ3 =84
2061 23:45:24.192736 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2062 23:45:24.192806 DQ8 =68, DQ9 =68, DQ10 =84, DQ11 =68
2063 23:45:24.192875 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
2064 23:45:24.192944
2065 23:45:24.193013
2066 23:45:24.193083 [DQSOSCAuto] RK1, (LSB)MR18= 0x1a12, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
2067 23:45:24.193153 CH1 RK1: MR19=606, MR18=1A12
2068 23:45:24.193224 CH1_RK1: MR19=0x606, MR18=0x1A12, DQSOSC=403, MR23=63, INC=90, DEC=60
2069 23:45:24.193294 [RxdqsGatingPostProcess] freq 800
2070 23:45:24.193363 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2071 23:45:24.193432 Pre-setting of DQS Precalculation
2072 23:45:24.193502 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2073 23:45:24.193572 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2074 23:45:24.193642 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2075 23:45:24.193712
2076 23:45:24.193781
2077 23:45:24.193892 [Calibration Summary] 1600 Mbps
2078 23:45:24.194045 CH 0, Rank 0
2079 23:45:24.194203 SW Impedance : PASS
2080 23:45:24.194353 DUTY Scan : NO K
2081 23:45:24.194505 ZQ Calibration : PASS
2082 23:45:24.194657 Jitter Meter : NO K
2083 23:45:24.194808 CBT Training : PASS
2084 23:45:24.194959 Write leveling : PASS
2085 23:45:24.195111 RX DQS gating : PASS
2086 23:45:24.195255 RX DQ/DQS(RDDQC) : PASS
2087 23:45:24.195391 TX DQ/DQS : PASS
2088 23:45:24.195540 RX DATLAT : PASS
2089 23:45:24.195691 RX DQ/DQS(Engine): PASS
2090 23:45:24.195841 TX OE : NO K
2091 23:45:24.195990 All Pass.
2092 23:45:24.196092
2093 23:45:24.196165 CH 0, Rank 1
2094 23:45:24.196236 SW Impedance : PASS
2095 23:45:24.196307 DUTY Scan : NO K
2096 23:45:24.196392 ZQ Calibration : PASS
2097 23:45:24.196464 Jitter Meter : NO K
2098 23:45:24.196534 CBT Training : PASS
2099 23:45:24.196604 Write leveling : PASS
2100 23:45:24.196674 RX DQS gating : PASS
2101 23:45:24.196744 RX DQ/DQS(RDDQC) : PASS
2102 23:45:24.196813 TX DQ/DQS : PASS
2103 23:45:24.196883 RX DATLAT : PASS
2104 23:45:24.196952 RX DQ/DQS(Engine): PASS
2105 23:45:24.197022 TX OE : NO K
2106 23:45:24.197092 All Pass.
2107 23:45:24.197176
2108 23:45:24.197321 CH 1, Rank 0
2109 23:45:24.197430 SW Impedance : PASS
2110 23:45:24.197543 DUTY Scan : NO K
2111 23:45:24.197654 ZQ Calibration : PASS
2112 23:45:24.197765 Jitter Meter : NO K
2113 23:45:24.197878 CBT Training : PASS
2114 23:45:24.197988 Write leveling : PASS
2115 23:45:24.198097 RX DQS gating : PASS
2116 23:45:24.198438 RX DQ/DQS(RDDQC) : PASS
2117 23:45:24.198567 TX DQ/DQS : PASS
2118 23:45:24.198680 RX DATLAT : PASS
2119 23:45:24.198790 RX DQ/DQS(Engine): PASS
2120 23:45:24.198900 TX OE : NO K
2121 23:45:24.199013 All Pass.
2122 23:45:24.199123
2123 23:45:24.199232 CH 1, Rank 1
2124 23:45:24.199351 SW Impedance : PASS
2125 23:45:24.199476 DUTY Scan : NO K
2126 23:45:24.199574 ZQ Calibration : PASS
2127 23:45:24.199672 Jitter Meter : NO K
2128 23:45:24.199769 CBT Training : PASS
2129 23:45:24.199866 Write leveling : PASS
2130 23:45:24.199963 RX DQS gating : PASS
2131 23:45:24.200060 RX DQ/DQS(RDDQC) : PASS
2132 23:45:24.200157 TX DQ/DQS : PASS
2133 23:45:24.200255 RX DATLAT : PASS
2134 23:45:24.200352 RX DQ/DQS(Engine): PASS
2135 23:45:24.200449 TX OE : NO K
2136 23:45:24.200555 All Pass.
2137 23:45:24.200654
2138 23:45:24.200751 DramC Write-DBI off
2139 23:45:24.200848 PER_BANK_REFRESH: Hybrid Mode
2140 23:45:24.200946 TX_TRACKING: ON
2141 23:45:24.201044 [GetDramInforAfterCalByMRR] Vendor 6.
2142 23:45:24.201142 [GetDramInforAfterCalByMRR] Revision 606.
2143 23:45:24.201240 [GetDramInforAfterCalByMRR] Revision 2 0.
2144 23:45:24.201340 MR0 0x3b3b
2145 23:45:24.201443 MR8 0x5151
2146 23:45:24.201541 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2147 23:45:24.201638
2148 23:45:24.201735 MR0 0x3b3b
2149 23:45:24.201831 MR8 0x5151
2150 23:45:24.201929 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2151 23:45:24.202026
2152 23:45:24.202126 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2153 23:45:24.202218 [FAST_K] Save calibration result to emmc
2154 23:45:24.202282 [FAST_K] Save calibration result to emmc
2155 23:45:24.202345 dram_init: config_dvfs: 1
2156 23:45:24.202408 dramc_set_vcore_voltage set vcore to 662500
2157 23:45:24.202470 Read voltage for 1200, 2
2158 23:45:24.202533 Vio18 = 0
2159 23:45:24.202595 Vcore = 662500
2160 23:45:24.202658 Vdram = 0
2161 23:45:24.202720 Vddq = 0
2162 23:45:24.202782 Vmddr = 0
2163 23:45:24.202844 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2164 23:45:24.202907 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2165 23:45:24.202970 MEM_TYPE=3, freq_sel=15
2166 23:45:24.203032 sv_algorithm_assistance_LP4_1600
2167 23:45:24.203095 ============ PULL DRAM RESETB DOWN ============
2168 23:45:24.203158 ========== PULL DRAM RESETB DOWN end =========
2169 23:45:24.203221 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2170 23:45:24.203283 ===================================
2171 23:45:24.203350 LPDDR4 DRAM CONFIGURATION
2172 23:45:24.203421 ===================================
2173 23:45:24.203484 EX_ROW_EN[0] = 0x0
2174 23:45:24.203546 EX_ROW_EN[1] = 0x0
2175 23:45:24.203609 LP4Y_EN = 0x0
2176 23:45:24.203670 WORK_FSP = 0x0
2177 23:45:24.203742 WL = 0x4
2178 23:45:24.203806 RL = 0x4
2179 23:45:24.203867 BL = 0x2
2180 23:45:24.203929 RPST = 0x0
2181 23:45:24.203990 RD_PRE = 0x0
2182 23:45:24.204052 WR_PRE = 0x1
2183 23:45:24.204113 WR_PST = 0x0
2184 23:45:24.204174 DBI_WR = 0x0
2185 23:45:24.204236 DBI_RD = 0x0
2186 23:45:24.204308 OTF = 0x1
2187 23:45:24.204364 ===================================
2188 23:45:24.204420 ===================================
2189 23:45:24.204476 ANA top config
2190 23:45:24.204531 ===================================
2191 23:45:24.204587 DLL_ASYNC_EN = 0
2192 23:45:24.204643 ALL_SLAVE_EN = 0
2193 23:45:24.204699 NEW_RANK_MODE = 1
2194 23:45:24.204756 DLL_IDLE_MODE = 1
2195 23:45:24.204811 LP45_APHY_COMB_EN = 1
2196 23:45:24.204867 TX_ODT_DIS = 1
2197 23:45:24.204923 NEW_8X_MODE = 1
2198 23:45:24.204979 ===================================
2199 23:45:24.205035 ===================================
2200 23:45:24.205091 data_rate = 2400
2201 23:45:24.205147 CKR = 1
2202 23:45:24.205203 DQ_P2S_RATIO = 8
2203 23:45:24.205259 ===================================
2204 23:45:24.205315 CA_P2S_RATIO = 8
2205 23:45:24.205393 DQ_CA_OPEN = 0
2206 23:45:24.205500 DQ_SEMI_OPEN = 0
2207 23:45:24.205567 CA_SEMI_OPEN = 0
2208 23:45:24.205624 CA_FULL_RATE = 0
2209 23:45:24.205680 DQ_CKDIV4_EN = 0
2210 23:45:24.205735 CA_CKDIV4_EN = 0
2211 23:45:24.205792 CA_PREDIV_EN = 0
2212 23:45:24.205847 PH8_DLY = 17
2213 23:45:24.205903 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2214 23:45:24.205959 DQ_AAMCK_DIV = 4
2215 23:45:24.206015 CA_AAMCK_DIV = 4
2216 23:45:24.206071 CA_ADMCK_DIV = 4
2217 23:45:24.206127 DQ_TRACK_CA_EN = 0
2218 23:45:24.206191 CA_PICK = 1200
2219 23:45:24.206248 CA_MCKIO = 1200
2220 23:45:24.206304 MCKIO_SEMI = 0
2221 23:45:24.206360 PLL_FREQ = 2366
2222 23:45:24.206425 DQ_UI_PI_RATIO = 32
2223 23:45:24.206481 CA_UI_PI_RATIO = 0
2224 23:45:24.206537 ===================================
2225 23:45:24.206594 ===================================
2226 23:45:24.206650 memory_type:LPDDR4
2227 23:45:24.206706 GP_NUM : 10
2228 23:45:24.206771 SRAM_EN : 1
2229 23:45:24.206828 MD32_EN : 0
2230 23:45:24.206884 ===================================
2231 23:45:24.206940 [ANA_INIT] >>>>>>>>>>>>>>
2232 23:45:24.206996 <<<<<< [CONFIGURE PHASE]: ANA_TX
2233 23:45:24.207054 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2234 23:45:24.207111 ===================================
2235 23:45:24.207167 data_rate = 2400,PCW = 0X5b00
2236 23:45:24.207223 ===================================
2237 23:45:24.207279 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2238 23:45:24.207339 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2239 23:45:24.207406 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2240 23:45:24.207464 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2241 23:45:24.207520 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2242 23:45:24.207576 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2243 23:45:24.207632 [ANA_INIT] flow start
2244 23:45:24.207688 [ANA_INIT] PLL >>>>>>>>
2245 23:45:24.207743 [ANA_INIT] PLL <<<<<<<<
2246 23:45:24.207799 [ANA_INIT] MIDPI >>>>>>>>
2247 23:45:24.207855 [ANA_INIT] MIDPI <<<<<<<<
2248 23:45:24.207911 [ANA_INIT] DLL >>>>>>>>
2249 23:45:24.207966 [ANA_INIT] DLL <<<<<<<<
2250 23:45:24.208022 [ANA_INIT] flow end
2251 23:45:24.208079 ============ LP4 DIFF to SE enter ============
2252 23:45:24.208135 ============ LP4 DIFF to SE exit ============
2253 23:45:24.208408 [ANA_INIT] <<<<<<<<<<<<<
2254 23:45:24.208475 [Flow] Enable top DCM control >>>>>
2255 23:45:24.208533 [Flow] Enable top DCM control <<<<<
2256 23:45:24.208590 Enable DLL master slave shuffle
2257 23:45:24.208646 ==============================================================
2258 23:45:24.208771 Gating Mode config
2259 23:45:24.208894 ==============================================================
2260 23:45:24.208995 Config description:
2261 23:45:24.209093 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2262 23:45:24.209185 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2263 23:45:24.209274 SELPH_MODE 0: By rank 1: By Phase
2264 23:45:24.209382 ==============================================================
2265 23:45:24.209509 GAT_TRACK_EN = 1
2266 23:45:24.209654 RX_GATING_MODE = 2
2267 23:45:24.209734 RX_GATING_TRACK_MODE = 2
2268 23:45:24.209814 SELPH_MODE = 1
2269 23:45:24.209894 PICG_EARLY_EN = 1
2270 23:45:24.209974 VALID_LAT_VALUE = 1
2271 23:45:24.210055 ==============================================================
2272 23:45:24.210136 Enter into Gating configuration >>>>
2273 23:45:24.210248 Exit from Gating configuration <<<<
2274 23:45:24.210302 Enter into DVFS_PRE_config >>>>>
2275 23:45:24.210363 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2276 23:45:24.210435 Exit from DVFS_PRE_config <<<<<
2277 23:45:24.210500 Enter into PICG configuration >>>>
2278 23:45:24.210551 Exit from PICG configuration <<<<
2279 23:45:24.210603 [RX_INPUT] configuration >>>>>
2280 23:45:24.210654 [RX_INPUT] configuration <<<<<
2281 23:45:24.210705 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2282 23:45:24.210757 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2283 23:45:24.210815 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2284 23:45:24.210924 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2285 23:45:24.211025 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2286 23:45:24.211079 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2287 23:45:24.211161 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2288 23:45:24.211227 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2289 23:45:24.211278 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2290 23:45:24.211329 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2291 23:45:24.211380 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2292 23:45:24.211432 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2293 23:45:24.211483 ===================================
2294 23:45:24.211534 LPDDR4 DRAM CONFIGURATION
2295 23:45:24.211585 ===================================
2296 23:45:24.211636 EX_ROW_EN[0] = 0x0
2297 23:45:24.211687 EX_ROW_EN[1] = 0x0
2298 23:45:24.211738 LP4Y_EN = 0x0
2299 23:45:24.211788 WORK_FSP = 0x0
2300 23:45:24.211839 WL = 0x4
2301 23:45:24.211889 RL = 0x4
2302 23:45:24.211940 BL = 0x2
2303 23:45:24.211991 RPST = 0x0
2304 23:45:24.212042 RD_PRE = 0x0
2305 23:45:24.212092 WR_PRE = 0x1
2306 23:45:24.212143 WR_PST = 0x0
2307 23:45:24.212193 DBI_WR = 0x0
2308 23:45:24.212244 DBI_RD = 0x0
2309 23:45:24.212294 OTF = 0x1
2310 23:45:24.212346 ===================================
2311 23:45:24.212397 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2312 23:45:24.212448 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2313 23:45:24.212512 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2314 23:45:24.212564 ===================================
2315 23:45:24.212615 LPDDR4 DRAM CONFIGURATION
2316 23:45:24.212666 ===================================
2317 23:45:24.212717 EX_ROW_EN[0] = 0x10
2318 23:45:24.212769 EX_ROW_EN[1] = 0x0
2319 23:45:24.212820 LP4Y_EN = 0x0
2320 23:45:24.212870 WORK_FSP = 0x0
2321 23:45:24.212921 WL = 0x4
2322 23:45:24.212972 RL = 0x4
2323 23:45:24.213023 BL = 0x2
2324 23:45:24.213074 RPST = 0x0
2325 23:45:24.213124 RD_PRE = 0x0
2326 23:45:24.213175 WR_PRE = 0x1
2327 23:45:24.213226 WR_PST = 0x0
2328 23:45:24.213277 DBI_WR = 0x0
2329 23:45:24.213327 DBI_RD = 0x0
2330 23:45:24.213378 OTF = 0x1
2331 23:45:24.213429 ===================================
2332 23:45:24.213480 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2333 23:45:24.213531 ==
2334 23:45:24.213583 Dram Type= 6, Freq= 0, CH_0, rank 0
2335 23:45:24.213644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2336 23:45:24.213695 ==
2337 23:45:24.213747 [Duty_Offset_Calibration]
2338 23:45:24.213797 B0:1 B1:-1 CA:0
2339 23:45:24.213847
2340 23:45:24.213898 [DutyScan_Calibration_Flow] k_type=0
2341 23:45:24.213949
2342 23:45:24.214000 ==CLK 0==
2343 23:45:24.214065 Final CLK duty delay cell = 0
2344 23:45:24.214118 [0] MAX Duty = 5094%(X100), DQS PI = 22
2345 23:45:24.214184 [0] MIN Duty = 4907%(X100), DQS PI = 6
2346 23:45:24.214251 [0] AVG Duty = 5000%(X100)
2347 23:45:24.214301
2348 23:45:24.214352 CH0 CLK Duty spec in!! Max-Min= 187%
2349 23:45:24.214402 [DutyScan_Calibration_Flow] ====Done====
2350 23:45:24.214457
2351 23:45:24.214517 [DutyScan_Calibration_Flow] k_type=1
2352 23:45:24.214644
2353 23:45:24.214695 ==DQS 0 ==
2354 23:45:24.214746 Final DQS duty delay cell = -4
2355 23:45:24.214797 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2356 23:45:24.214847 [-4] MIN Duty = 4875%(X100), DQS PI = 54
2357 23:45:24.214898 [-4] AVG Duty = 4968%(X100)
2358 23:45:24.214948
2359 23:45:24.214998 ==DQS 1 ==
2360 23:45:24.215048 Final DQS duty delay cell = 0
2361 23:45:24.215099 [0] MAX Duty = 5124%(X100), DQS PI = 6
2362 23:45:24.215150 [0] MIN Duty = 5000%(X100), DQS PI = 20
2363 23:45:24.215200 [0] AVG Duty = 5062%(X100)
2364 23:45:24.215249
2365 23:45:24.215300 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2366 23:45:24.215351
2367 23:45:24.215401 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2368 23:45:24.215452 [DutyScan_Calibration_Flow] ====Done====
2369 23:45:24.215523
2370 23:45:24.215576 [DutyScan_Calibration_Flow] k_type=3
2371 23:45:24.215627
2372 23:45:24.215678 ==DQM 0 ==
2373 23:45:24.215729 Final DQM duty delay cell = 0
2374 23:45:24.215782 [0] MAX Duty = 5031%(X100), DQS PI = 16
2375 23:45:24.216040 [0] MIN Duty = 4875%(X100), DQS PI = 6
2376 23:45:24.216100 [0] AVG Duty = 4953%(X100)
2377 23:45:24.216152
2378 23:45:24.216203 ==DQM 1 ==
2379 23:45:24.216254 Final DQM duty delay cell = 4
2380 23:45:24.216305 [4] MAX Duty = 5187%(X100), DQS PI = 14
2381 23:45:24.216356 [4] MIN Duty = 5000%(X100), DQS PI = 22
2382 23:45:24.216407 [4] AVG Duty = 5093%(X100)
2383 23:45:24.216462
2384 23:45:24.216518 CH0 DQM 0 Duty spec in!! Max-Min= 156%
2385 23:45:24.216668
2386 23:45:24.216815 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2387 23:45:24.216872 [DutyScan_Calibration_Flow] ====Done====
2388 23:45:24.216925
2389 23:45:24.216976 [DutyScan_Calibration_Flow] k_type=2
2390 23:45:24.217028
2391 23:45:24.217092 ==DQ 0 ==
2392 23:45:24.217144 Final DQ duty delay cell = -4
2393 23:45:24.217196 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2394 23:45:24.217247 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2395 23:45:24.217310 [-4] AVG Duty = 4969%(X100)
2396 23:45:24.217362
2397 23:45:24.217413 ==DQ 1 ==
2398 23:45:24.217464 Final DQ duty delay cell = 0
2399 23:45:24.217516 [0] MAX Duty = 5125%(X100), DQS PI = 50
2400 23:45:24.217570 [0] MIN Duty = 4969%(X100), DQS PI = 40
2401 23:45:24.217621 [0] AVG Duty = 5047%(X100)
2402 23:45:24.217672
2403 23:45:24.217723 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2404 23:45:24.217774
2405 23:45:24.217824 CH0 DQ 1 Duty spec in!! Max-Min= 156%
2406 23:45:24.217876 [DutyScan_Calibration_Flow] ====Done====
2407 23:45:24.217926 ==
2408 23:45:24.217978 Dram Type= 6, Freq= 0, CH_1, rank 0
2409 23:45:24.218029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2410 23:45:24.218080 ==
2411 23:45:24.218131 [Duty_Offset_Calibration]
2412 23:45:24.218211 B0:-1 B1:1 CA:1
2413 23:45:24.218277
2414 23:45:24.218328 [DutyScan_Calibration_Flow] k_type=0
2415 23:45:24.218379
2416 23:45:24.218429 ==CLK 0==
2417 23:45:24.218481 Final CLK duty delay cell = 0
2418 23:45:24.218534 [0] MAX Duty = 5156%(X100), DQS PI = 22
2419 23:45:24.218585 [0] MIN Duty = 4969%(X100), DQS PI = 62
2420 23:45:24.218635 [0] AVG Duty = 5062%(X100)
2421 23:45:24.218686
2422 23:45:24.218737 CH1 CLK Duty spec in!! Max-Min= 187%
2423 23:45:24.218792 [DutyScan_Calibration_Flow] ====Done====
2424 23:45:24.218842
2425 23:45:24.218893 [DutyScan_Calibration_Flow] k_type=1
2426 23:45:24.218944
2427 23:45:24.218995 ==DQS 0 ==
2428 23:45:24.219046 Final DQS duty delay cell = 0
2429 23:45:24.219097 [0] MAX Duty = 5125%(X100), DQS PI = 48
2430 23:45:24.219148 [0] MIN Duty = 4875%(X100), DQS PI = 6
2431 23:45:24.219199 [0] AVG Duty = 5000%(X100)
2432 23:45:24.219250
2433 23:45:24.219299 ==DQS 1 ==
2434 23:45:24.219350 Final DQS duty delay cell = 0
2435 23:45:24.219401 [0] MAX Duty = 5062%(X100), DQS PI = 12
2436 23:45:24.219452 [0] MIN Duty = 4969%(X100), DQS PI = 56
2437 23:45:24.219507 [0] AVG Duty = 5015%(X100)
2438 23:45:24.219558
2439 23:45:24.219609 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2440 23:45:24.219660
2441 23:45:24.219710 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2442 23:45:24.219761 [DutyScan_Calibration_Flow] ====Done====
2443 23:45:24.219811
2444 23:45:24.219862 [DutyScan_Calibration_Flow] k_type=3
2445 23:45:24.219912
2446 23:45:24.219963 ==DQM 0 ==
2447 23:45:24.220013 Final DQM duty delay cell = -4
2448 23:45:24.220064 [-4] MAX Duty = 5031%(X100), DQS PI = 36
2449 23:45:24.220114 [-4] MIN Duty = 4844%(X100), DQS PI = 6
2450 23:45:24.220165 [-4] AVG Duty = 4937%(X100)
2451 23:45:24.220219
2452 23:45:24.220270 ==DQM 1 ==
2453 23:45:24.220321 Final DQM duty delay cell = 0
2454 23:45:24.220372 [0] MAX Duty = 5156%(X100), DQS PI = 4
2455 23:45:24.220431 [0] MIN Duty = 4969%(X100), DQS PI = 28
2456 23:45:24.220487 [0] AVG Duty = 5062%(X100)
2457 23:45:24.220538
2458 23:45:24.220589 CH1 DQM 0 Duty spec in!! Max-Min= 187%
2459 23:45:24.220641
2460 23:45:24.220692 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2461 23:45:24.220743 [DutyScan_Calibration_Flow] ====Done====
2462 23:45:24.220794
2463 23:45:24.220844 [DutyScan_Calibration_Flow] k_type=2
2464 23:45:24.220894
2465 23:45:24.220945 ==DQ 0 ==
2466 23:45:24.220995 Final DQ duty delay cell = 0
2467 23:45:24.221061 [0] MAX Duty = 5156%(X100), DQS PI = 28
2468 23:45:24.221142 [0] MIN Duty = 4876%(X100), DQS PI = 8
2469 23:45:24.221221 [0] AVG Duty = 5016%(X100)
2470 23:45:24.221299
2471 23:45:24.221355 ==DQ 1 ==
2472 23:45:24.221407 Final DQ duty delay cell = 0
2473 23:45:24.221459 [0] MAX Duty = 5124%(X100), DQS PI = 12
2474 23:45:24.221510 [0] MIN Duty = 4969%(X100), DQS PI = 0
2475 23:45:24.221565 [0] AVG Duty = 5046%(X100)
2476 23:45:24.221616
2477 23:45:24.221667 CH1 DQ 0 Duty spec in!! Max-Min= 280%
2478 23:45:24.221718
2479 23:45:24.221769 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2480 23:45:24.221819 [DutyScan_Calibration_Flow] ====Done====
2481 23:45:24.221869 nWR fixed to 30
2482 23:45:24.221920 [ModeRegInit_LP4] CH0 RK0
2483 23:45:24.221971 [ModeRegInit_LP4] CH0 RK1
2484 23:45:24.222021 [ModeRegInit_LP4] CH1 RK0
2485 23:45:24.222072 [ModeRegInit_LP4] CH1 RK1
2486 23:45:24.222122 match AC timing 7
2487 23:45:24.222200 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2488 23:45:24.222268 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2489 23:45:24.222318 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2490 23:45:24.222369 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2491 23:45:24.222420 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2492 23:45:24.222471 ==
2493 23:45:24.222522 Dram Type= 6, Freq= 0, CH_0, rank 0
2494 23:45:24.222573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2495 23:45:24.222624 ==
2496 23:45:24.222675 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2497 23:45:24.222726 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2498 23:45:24.222777 [CA 0] Center 39 (9~70) winsize 62
2499 23:45:24.222828 [CA 1] Center 39 (9~69) winsize 61
2500 23:45:24.222879 [CA 2] Center 35 (5~66) winsize 62
2501 23:45:24.222929 [CA 3] Center 35 (5~66) winsize 62
2502 23:45:24.222983 [CA 4] Center 33 (4~63) winsize 60
2503 23:45:24.223034 [CA 5] Center 33 (3~63) winsize 61
2504 23:45:24.223084
2505 23:45:24.223135 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2506 23:45:24.223185
2507 23:45:24.223236 [CATrainingPosCal] consider 1 rank data
2508 23:45:24.223287 u2DelayCellTimex100 = 270/100 ps
2509 23:45:24.223337 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2510 23:45:24.223388 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2511 23:45:24.223441 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2512 23:45:24.223493 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2513 23:45:24.223543 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2514 23:45:24.223594 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2515 23:45:24.223644
2516 23:45:24.223703 CA PerBit enable=1, Macro0, CA PI delay=33
2517 23:45:24.223755
2518 23:45:24.223806 [CBTSetCACLKResult] CA Dly = 33
2519 23:45:24.223857 CS Dly: 8 (0~39)
2520 23:45:24.223907 ==
2521 23:45:24.223957 Dram Type= 6, Freq= 0, CH_0, rank 1
2522 23:45:24.224008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2523 23:45:24.224058 ==
2524 23:45:24.224317 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2525 23:45:24.224425 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2526 23:45:24.224530 [CA 0] Center 39 (8~70) winsize 63
2527 23:45:24.224633 [CA 1] Center 39 (9~70) winsize 62
2528 23:45:24.224731 [CA 2] Center 35 (5~66) winsize 62
2529 23:45:24.224812 [CA 3] Center 34 (4~65) winsize 62
2530 23:45:24.224892 [CA 4] Center 33 (3~64) winsize 62
2531 23:45:24.224972 [CA 5] Center 33 (3~63) winsize 61
2532 23:45:24.225051
2533 23:45:24.225138 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2534 23:45:24.225219
2535 23:45:24.225299 [CATrainingPosCal] consider 2 rank data
2536 23:45:24.225379 u2DelayCellTimex100 = 270/100 ps
2537 23:45:24.225459 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2538 23:45:24.225540 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2539 23:45:24.225621 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2540 23:45:24.225702 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2541 23:45:24.225782 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2542 23:45:24.225861 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2543 23:45:24.225940
2544 23:45:24.226020 CA PerBit enable=1, Macro0, CA PI delay=33
2545 23:45:24.226099
2546 23:45:24.226209 [CBTSetCACLKResult] CA Dly = 33
2547 23:45:24.226303 CS Dly: 9 (0~41)
2548 23:45:24.226383
2549 23:45:24.226463 ----->DramcWriteLeveling(PI) begin...
2550 23:45:24.226543 ==
2551 23:45:24.226623 Dram Type= 6, Freq= 0, CH_0, rank 0
2552 23:45:24.226707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2553 23:45:24.226801 ==
2554 23:45:24.226888 Write leveling (Byte 0): 33 => 33
2555 23:45:24.226969 Write leveling (Byte 1): 29 => 29
2556 23:45:24.227049 DramcWriteLeveling(PI) end<-----
2557 23:45:24.227128
2558 23:45:24.227207 ==
2559 23:45:24.227287 Dram Type= 6, Freq= 0, CH_0, rank 0
2560 23:45:24.227367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2561 23:45:24.227447 ==
2562 23:45:24.227527 [Gating] SW mode calibration
2563 23:45:24.227608 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2564 23:45:24.227690 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2565 23:45:24.227770 0 15 0 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
2566 23:45:24.227851 0 15 4 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
2567 23:45:24.227932 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2568 23:45:24.228012 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2569 23:45:24.228092 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2570 23:45:24.228173 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2571 23:45:24.228253 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2572 23:45:24.228333 0 15 28 | B1->B0 | 3434 2c2c | 1 1 | (1 1) (1 0)
2573 23:45:24.228413 1 0 0 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
2574 23:45:24.228493 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2575 23:45:24.228574 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2576 23:45:24.228654 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2577 23:45:24.228741 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2578 23:45:24.228822 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2579 23:45:24.228910 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2580 23:45:24.228991 1 0 28 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
2581 23:45:24.229071 1 1 0 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
2582 23:45:24.229151 1 1 4 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
2583 23:45:24.229232 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2584 23:45:24.229312 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2585 23:45:24.229398 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2586 23:45:24.229454 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2587 23:45:24.229505 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2588 23:45:24.229556 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2589 23:45:24.229607 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2590 23:45:24.229658 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2591 23:45:24.229708 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2592 23:45:24.229759 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2593 23:45:24.229818 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2594 23:45:24.229870 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2595 23:45:24.229921 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2596 23:45:24.229971 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2597 23:45:24.230022 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2598 23:45:24.230073 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2599 23:45:24.230124 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2600 23:45:24.230200 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2601 23:45:24.230267 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2602 23:45:24.230317 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2603 23:45:24.230368 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2604 23:45:24.230418 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2605 23:45:24.230469 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2606 23:45:24.230520 Total UI for P1: 0, mck2ui 16
2607 23:45:24.230571 best dqsien dly found for B0: ( 1, 3, 26)
2608 23:45:24.230622 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2609 23:45:24.230672 Total UI for P1: 0, mck2ui 16
2610 23:45:24.230723 best dqsien dly found for B1: ( 1, 4, 0)
2611 23:45:24.230775 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2612 23:45:24.230829 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2613 23:45:24.230891
2614 23:45:24.230983 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2615 23:45:24.231049 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2616 23:45:24.231100 [Gating] SW calibration Done
2617 23:45:24.231150 ==
2618 23:45:24.231202 Dram Type= 6, Freq= 0, CH_0, rank 0
2619 23:45:24.231253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2620 23:45:24.231304 ==
2621 23:45:24.231354 RX Vref Scan: 0
2622 23:45:24.231405
2623 23:45:24.231456 RX Vref 0 -> 0, step: 1
2624 23:45:24.231506
2625 23:45:24.231557 RX Delay -40 -> 252, step: 8
2626 23:45:24.231608 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2627 23:45:24.231660 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2628 23:45:24.231912 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2629 23:45:24.231974 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2630 23:45:24.232026 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2631 23:45:24.232077 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2632 23:45:24.232128 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2633 23:45:24.232179 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2634 23:45:24.232229 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2635 23:45:24.232280 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2636 23:45:24.232332 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2637 23:45:24.232382 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2638 23:45:24.232433 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2639 23:45:24.232484 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2640 23:45:24.232535 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2641 23:45:24.232586 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2642 23:45:24.232636 ==
2643 23:45:24.232688 Dram Type= 6, Freq= 0, CH_0, rank 0
2644 23:45:24.232739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2645 23:45:24.232790 ==
2646 23:45:24.232844 DQS Delay:
2647 23:45:24.232899 DQS0 = 0, DQS1 = 0
2648 23:45:24.232988 DQM Delay:
2649 23:45:24.233057 DQM0 = 119, DQM1 = 106
2650 23:45:24.233122 DQ Delay:
2651 23:45:24.233174 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2652 23:45:24.233235 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =123
2653 23:45:24.233286 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2654 23:45:24.233336 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2655 23:45:24.233387
2656 23:45:24.233437
2657 23:45:24.233488 ==
2658 23:45:24.233539 Dram Type= 6, Freq= 0, CH_0, rank 0
2659 23:45:24.233590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2660 23:45:24.233641 ==
2661 23:45:24.233691
2662 23:45:24.233742
2663 23:45:24.233792 TX Vref Scan disable
2664 23:45:24.233843 == TX Byte 0 ==
2665 23:45:24.233894 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2666 23:45:24.233945 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2667 23:45:24.233996 == TX Byte 1 ==
2668 23:45:24.234047 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2669 23:45:24.234098 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2670 23:45:24.234148 ==
2671 23:45:24.234248 Dram Type= 6, Freq= 0, CH_0, rank 0
2672 23:45:24.234300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2673 23:45:24.234351 ==
2674 23:45:24.234402 TX Vref=22, minBit 1, minWin=26, winSum=425
2675 23:45:24.234454 TX Vref=24, minBit 0, minWin=26, winSum=429
2676 23:45:24.234506 TX Vref=26, minBit 4, minWin=26, winSum=433
2677 23:45:24.234557 TX Vref=28, minBit 4, minWin=27, winSum=437
2678 23:45:24.234607 TX Vref=30, minBit 14, minWin=26, winSum=436
2679 23:45:24.234658 TX Vref=32, minBit 4, minWin=26, winSum=431
2680 23:45:24.234708 [TxChooseVref] Worse bit 4, Min win 27, Win sum 437, Final Vref 28
2681 23:45:24.234759
2682 23:45:24.234809 Final TX Range 1 Vref 28
2683 23:45:24.234860
2684 23:45:24.234909 ==
2685 23:45:24.234959 Dram Type= 6, Freq= 0, CH_0, rank 0
2686 23:45:24.235010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2687 23:45:24.235060 ==
2688 23:45:24.235111
2689 23:45:24.235160
2690 23:45:24.235210 TX Vref Scan disable
2691 23:45:24.235260 == TX Byte 0 ==
2692 23:45:24.235311 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2693 23:45:24.235362 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2694 23:45:24.235412 == TX Byte 1 ==
2695 23:45:24.235463 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2696 23:45:24.235513 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2697 23:45:24.235564
2698 23:45:24.235615 [DATLAT]
2699 23:45:24.235665 Freq=1200, CH0 RK0
2700 23:45:24.235716
2701 23:45:24.235766 DATLAT Default: 0xd
2702 23:45:24.235817 0, 0xFFFF, sum = 0
2703 23:45:24.235868 1, 0xFFFF, sum = 0
2704 23:45:24.235920 2, 0xFFFF, sum = 0
2705 23:45:24.235971 3, 0xFFFF, sum = 0
2706 23:45:24.236022 4, 0xFFFF, sum = 0
2707 23:45:24.236074 5, 0xFFFF, sum = 0
2708 23:45:24.236125 6, 0xFFFF, sum = 0
2709 23:45:24.236176 7, 0xFFFF, sum = 0
2710 23:45:24.236227 8, 0xFFFF, sum = 0
2711 23:45:24.236278 9, 0xFFFF, sum = 0
2712 23:45:24.236330 10, 0xFFFF, sum = 0
2713 23:45:24.236381 11, 0xFFFF, sum = 0
2714 23:45:24.236432 12, 0x0, sum = 1
2715 23:45:24.236483 13, 0x0, sum = 2
2716 23:45:24.236534 14, 0x0, sum = 3
2717 23:45:24.236585 15, 0x0, sum = 4
2718 23:45:24.236636 best_step = 13
2719 23:45:24.236686
2720 23:45:24.236736 ==
2721 23:45:24.236786 Dram Type= 6, Freq= 0, CH_0, rank 0
2722 23:45:24.236837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2723 23:45:24.236897 ==
2724 23:45:24.236948 RX Vref Scan: 1
2725 23:45:24.236999
2726 23:45:24.237049 Set Vref Range= 32 -> 127
2727 23:45:24.237100
2728 23:45:24.237150 RX Vref 32 -> 127, step: 1
2729 23:45:24.237201
2730 23:45:24.237251 RX Delay -21 -> 252, step: 4
2731 23:45:24.237301
2732 23:45:24.237351 Set Vref, RX VrefLevel [Byte0]: 32
2733 23:45:24.237402 [Byte1]: 32
2734 23:45:24.237452
2735 23:45:24.237503 Set Vref, RX VrefLevel [Byte0]: 33
2736 23:45:24.237553 [Byte1]: 33
2737 23:45:24.237604
2738 23:45:24.237655 Set Vref, RX VrefLevel [Byte0]: 34
2739 23:45:24.237705 [Byte1]: 34
2740 23:45:24.237755
2741 23:45:24.237806 Set Vref, RX VrefLevel [Byte0]: 35
2742 23:45:24.237857 [Byte1]: 35
2743 23:45:24.237907
2744 23:45:24.237957 Set Vref, RX VrefLevel [Byte0]: 36
2745 23:45:24.238008 [Byte1]: 36
2746 23:45:24.238070
2747 23:45:24.238183 Set Vref, RX VrefLevel [Byte0]: 37
2748 23:45:24.238257 [Byte1]: 37
2749 23:45:24.238310
2750 23:45:24.238361 Set Vref, RX VrefLevel [Byte0]: 38
2751 23:45:24.238412 [Byte1]: 38
2752 23:45:24.238463
2753 23:45:24.238514 Set Vref, RX VrefLevel [Byte0]: 39
2754 23:45:24.238565 [Byte1]: 39
2755 23:45:24.238615
2756 23:45:24.238666 Set Vref, RX VrefLevel [Byte0]: 40
2757 23:45:24.238717 [Byte1]: 40
2758 23:45:24.238768
2759 23:45:24.238818 Set Vref, RX VrefLevel [Byte0]: 41
2760 23:45:24.238869 [Byte1]: 41
2761 23:45:24.238919
2762 23:45:24.238970 Set Vref, RX VrefLevel [Byte0]: 42
2763 23:45:24.239020 [Byte1]: 42
2764 23:45:24.239070
2765 23:45:24.239120 Set Vref, RX VrefLevel [Byte0]: 43
2766 23:45:24.239170 [Byte1]: 43
2767 23:45:24.239220
2768 23:45:24.239271 Set Vref, RX VrefLevel [Byte0]: 44
2769 23:45:24.239322 [Byte1]: 44
2770 23:45:24.239371
2771 23:45:24.239422 Set Vref, RX VrefLevel [Byte0]: 45
2772 23:45:24.239472 [Byte1]: 45
2773 23:45:24.239522
2774 23:45:24.239572 Set Vref, RX VrefLevel [Byte0]: 46
2775 23:45:24.239622 [Byte1]: 46
2776 23:45:24.239672
2777 23:45:24.239722 Set Vref, RX VrefLevel [Byte0]: 47
2778 23:45:24.239773 [Byte1]: 47
2779 23:45:24.239824
2780 23:45:24.239874 Set Vref, RX VrefLevel [Byte0]: 48
2781 23:45:24.239924 [Byte1]: 48
2782 23:45:24.239975
2783 23:45:24.240025 Set Vref, RX VrefLevel [Byte0]: 49
2784 23:45:24.240075 [Byte1]: 49
2785 23:45:24.240136
2786 23:45:24.240388 Set Vref, RX VrefLevel [Byte0]: 50
2787 23:45:24.240448 [Byte1]: 50
2788 23:45:24.240502
2789 23:45:24.240553 Set Vref, RX VrefLevel [Byte0]: 51
2790 23:45:24.240605 [Byte1]: 51
2791 23:45:24.240655
2792 23:45:24.240706 Set Vref, RX VrefLevel [Byte0]: 52
2793 23:45:24.240757 [Byte1]: 52
2794 23:45:24.240807
2795 23:45:24.240858 Set Vref, RX VrefLevel [Byte0]: 53
2796 23:45:24.240908 [Byte1]: 53
2797 23:45:24.240959
2798 23:45:24.241010 Set Vref, RX VrefLevel [Byte0]: 54
2799 23:45:24.241061 [Byte1]: 54
2800 23:45:24.241112
2801 23:45:24.241162 Set Vref, RX VrefLevel [Byte0]: 55
2802 23:45:24.241213 [Byte1]: 55
2803 23:45:24.241264
2804 23:45:24.241315 Set Vref, RX VrefLevel [Byte0]: 56
2805 23:45:24.241365 [Byte1]: 56
2806 23:45:24.241416
2807 23:45:24.241466 Set Vref, RX VrefLevel [Byte0]: 57
2808 23:45:24.241517 [Byte1]: 57
2809 23:45:24.241567
2810 23:45:24.241617 Set Vref, RX VrefLevel [Byte0]: 58
2811 23:45:24.241668 [Byte1]: 58
2812 23:45:24.241718
2813 23:45:24.241769 Set Vref, RX VrefLevel [Byte0]: 59
2814 23:45:24.241819 [Byte1]: 59
2815 23:45:24.241870
2816 23:45:24.241920 Set Vref, RX VrefLevel [Byte0]: 60
2817 23:45:24.241971 [Byte1]: 60
2818 23:45:24.242022
2819 23:45:24.242072 Set Vref, RX VrefLevel [Byte0]: 61
2820 23:45:24.242123 [Byte1]: 61
2821 23:45:24.242204
2822 23:45:24.242270 Set Vref, RX VrefLevel [Byte0]: 62
2823 23:45:24.242320 [Byte1]: 62
2824 23:45:24.242370
2825 23:45:24.242421 Set Vref, RX VrefLevel [Byte0]: 63
2826 23:45:24.242475 [Byte1]: 63
2827 23:45:24.242538
2828 23:45:24.242590 Set Vref, RX VrefLevel [Byte0]: 64
2829 23:45:24.242641 [Byte1]: 64
2830 23:45:24.242692
2831 23:45:24.242743 Set Vref, RX VrefLevel [Byte0]: 65
2832 23:45:24.242793 [Byte1]: 65
2833 23:45:24.242844
2834 23:45:24.242894 Set Vref, RX VrefLevel [Byte0]: 66
2835 23:45:24.242945 [Byte1]: 66
2836 23:45:24.242996
2837 23:45:24.243047 Set Vref, RX VrefLevel [Byte0]: 67
2838 23:45:24.243108 [Byte1]: 67
2839 23:45:24.243160
2840 23:45:24.243211 Set Vref, RX VrefLevel [Byte0]: 68
2841 23:45:24.243261 [Byte1]: 68
2842 23:45:24.243311
2843 23:45:24.243361 Set Vref, RX VrefLevel [Byte0]: 69
2844 23:45:24.243412 [Byte1]: 69
2845 23:45:24.243462
2846 23:45:24.243513 Set Vref, RX VrefLevel [Byte0]: 70
2847 23:45:24.243564 [Byte1]: 70
2848 23:45:24.243614
2849 23:45:24.243664 Set Vref, RX VrefLevel [Byte0]: 71
2850 23:45:24.243715 [Byte1]: 71
2851 23:45:24.243765
2852 23:45:24.243816 Set Vref, RX VrefLevel [Byte0]: 72
2853 23:45:24.243866 [Byte1]: 72
2854 23:45:24.243917
2855 23:45:24.243967 Set Vref, RX VrefLevel [Byte0]: 73
2856 23:45:24.244018 [Byte1]: 73
2857 23:45:24.244068
2858 23:45:24.244119 Set Vref, RX VrefLevel [Byte0]: 74
2859 23:45:24.244169 [Byte1]: 74
2860 23:45:24.244219
2861 23:45:24.244269 Set Vref, RX VrefLevel [Byte0]: 75
2862 23:45:24.244319 [Byte1]: 75
2863 23:45:24.244371
2864 23:45:24.244421 Set Vref, RX VrefLevel [Byte0]: 76
2865 23:45:24.244475 [Byte1]: 76
2866 23:45:24.244536
2867 23:45:24.244588 Set Vref, RX VrefLevel [Byte0]: 77
2868 23:45:24.244638 [Byte1]: 77
2869 23:45:24.244688
2870 23:45:24.244739 Set Vref, RX VrefLevel [Byte0]: 78
2871 23:45:24.244790 [Byte1]: 78
2872 23:45:24.244840
2873 23:45:24.244890 Final RX Vref Byte 0 = 57 to rank0
2874 23:45:24.244942 Final RX Vref Byte 1 = 50 to rank0
2875 23:45:24.244993 Final RX Vref Byte 0 = 57 to rank1
2876 23:45:24.245043 Final RX Vref Byte 1 = 50 to rank1==
2877 23:45:24.245094 Dram Type= 6, Freq= 0, CH_0, rank 0
2878 23:45:24.245145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2879 23:45:24.245195 ==
2880 23:45:24.245246 DQS Delay:
2881 23:45:24.245296 DQS0 = 0, DQS1 = 0
2882 23:45:24.245346 DQM Delay:
2883 23:45:24.245403 DQM0 = 118, DQM1 = 107
2884 23:45:24.245454 DQ Delay:
2885 23:45:24.245504 DQ0 =118, DQ1 =120, DQ2 =116, DQ3 =114
2886 23:45:24.245555 DQ4 =120, DQ5 =110, DQ6 =126, DQ7 =126
2887 23:45:24.245606 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =100
2888 23:45:24.245656 DQ12 =112, DQ13 =110, DQ14 =120, DQ15 =116
2889 23:45:24.245706
2890 23:45:24.245756
2891 23:45:24.245807 [DQSOSCAuto] RK0, (LSB)MR18= 0x11fd, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 403 ps
2892 23:45:24.245859 CH0 RK0: MR19=403, MR18=11FD
2893 23:45:24.245910 CH0_RK0: MR19=0x403, MR18=0x11FD, DQSOSC=403, MR23=63, INC=40, DEC=26
2894 23:45:24.245960
2895 23:45:24.246011 ----->DramcWriteLeveling(PI) begin...
2896 23:45:24.246063 ==
2897 23:45:24.246113 Dram Type= 6, Freq= 0, CH_0, rank 1
2898 23:45:24.246174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2899 23:45:24.246259 ==
2900 23:45:24.246309 Write leveling (Byte 0): 33 => 33
2901 23:45:24.246370 Write leveling (Byte 1): 29 => 29
2902 23:45:24.246421 DramcWriteLeveling(PI) end<-----
2903 23:45:24.246472
2904 23:45:24.246523 ==
2905 23:45:24.246577 Dram Type= 6, Freq= 0, CH_0, rank 1
2906 23:45:24.246634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2907 23:45:24.246691 ==
2908 23:45:24.246742 [Gating] SW mode calibration
2909 23:45:24.246794 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2910 23:45:24.246846 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2911 23:45:24.246897 0 15 0 | B1->B0 | 2525 3333 | 0 1 | (0 0) (1 1)
2912 23:45:24.246948 0 15 4 | B1->B0 | 2f2f 3434 | 1 1 | (0 0) (1 1)
2913 23:45:24.246999 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2914 23:45:24.247050 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2915 23:45:24.247107 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2916 23:45:24.247177 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2917 23:45:24.247241 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2918 23:45:24.247292 0 15 28 | B1->B0 | 3434 3333 | 1 0 | (1 0) (1 0)
2919 23:45:24.247342 1 0 0 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
2920 23:45:24.247393 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2921 23:45:24.247443 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2922 23:45:24.247493 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2923 23:45:24.247544 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2924 23:45:24.247594 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2925 23:45:24.247848 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2926 23:45:24.247911 1 0 28 | B1->B0 | 2424 3232 | 0 0 | (0 0) (0 0)
2927 23:45:24.247963 1 1 0 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
2928 23:45:24.248015 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2929 23:45:24.248066 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2930 23:45:24.248118 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2931 23:45:24.248169 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2932 23:45:24.248219 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2933 23:45:24.248270 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2934 23:45:24.248320 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2935 23:45:24.248371 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2936 23:45:24.248421 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2937 23:45:24.248472 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2938 23:45:24.248522 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2939 23:45:24.248574 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2940 23:45:24.248625 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2941 23:45:24.248675 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2942 23:45:24.248726 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2943 23:45:24.248776 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2944 23:45:24.248827 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2945 23:45:24.248878 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2946 23:45:24.248929 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2947 23:45:24.248979 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2948 23:45:24.249030 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2949 23:45:24.249080 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2950 23:45:24.249131 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2951 23:45:24.249186 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2952 23:45:24.249270 Total UI for P1: 0, mck2ui 16
2953 23:45:24.249321 best dqsien dly found for B0: ( 1, 3, 28)
2954 23:45:24.249372 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2955 23:45:24.249423 Total UI for P1: 0, mck2ui 16
2956 23:45:24.249474 best dqsien dly found for B1: ( 1, 4, 0)
2957 23:45:24.249524 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2958 23:45:24.249575 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2959 23:45:24.249626
2960 23:45:24.249676 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2961 23:45:24.249736 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2962 23:45:24.249786 [Gating] SW calibration Done
2963 23:45:24.249836 ==
2964 23:45:24.249887 Dram Type= 6, Freq= 0, CH_0, rank 1
2965 23:45:24.249938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2966 23:45:24.249989 ==
2967 23:45:24.250040 RX Vref Scan: 0
2968 23:45:24.250090
2969 23:45:24.250141 RX Vref 0 -> 0, step: 1
2970 23:45:24.250233
2971 23:45:24.250284 RX Delay -40 -> 252, step: 8
2972 23:45:24.250335 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2973 23:45:24.250386 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2974 23:45:24.250437 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2975 23:45:24.250496 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2976 23:45:24.409664 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2977 23:45:24.409832 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2978 23:45:24.409915 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2979 23:45:24.409990 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2980 23:45:24.410062 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2981 23:45:24.410133 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2982 23:45:24.410217 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2983 23:45:24.410286 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2984 23:45:24.410354 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2985 23:45:24.410421 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2986 23:45:24.410488 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2987 23:45:24.410553 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2988 23:45:24.410619 ==
2989 23:45:24.410697 Dram Type= 6, Freq= 0, CH_0, rank 1
2990 23:45:24.410765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2991 23:45:24.410832 ==
2992 23:45:24.410899 DQS Delay:
2993 23:45:24.410966 DQS0 = 0, DQS1 = 0
2994 23:45:24.411050 DQM Delay:
2995 23:45:24.411157 DQM0 = 117, DQM1 = 107
2996 23:45:24.411270 DQ Delay:
2997 23:45:24.411339 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =115
2998 23:45:24.411407 DQ4 =119, DQ5 =111, DQ6 =127, DQ7 =123
2999 23:45:24.411473 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
3000 23:45:24.411539 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
3001 23:45:24.411610
3002 23:45:24.411704
3003 23:45:24.411772 ==
3004 23:45:24.411838 Dram Type= 6, Freq= 0, CH_0, rank 1
3005 23:45:24.411905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3006 23:45:24.411972 ==
3007 23:45:24.412038
3008 23:45:24.412103
3009 23:45:24.412168 TX Vref Scan disable
3010 23:45:24.412234 == TX Byte 0 ==
3011 23:45:24.412298 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3012 23:45:24.412365 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3013 23:45:24.412430 == TX Byte 1 ==
3014 23:45:24.412495 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3015 23:45:24.412561 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3016 23:45:24.412627 ==
3017 23:45:24.412692 Dram Type= 6, Freq= 0, CH_0, rank 1
3018 23:45:24.412758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3019 23:45:24.412824 ==
3020 23:45:24.412889 TX Vref=22, minBit 0, minWin=26, winSum=422
3021 23:45:24.412956 TX Vref=24, minBit 1, minWin=26, winSum=427
3022 23:45:24.413021 TX Vref=26, minBit 1, minWin=26, winSum=428
3023 23:45:24.413086 TX Vref=28, minBit 2, minWin=26, winSum=432
3024 23:45:24.413151 TX Vref=30, minBit 10, minWin=26, winSum=434
3025 23:45:24.413217 TX Vref=32, minBit 13, minWin=26, winSum=434
3026 23:45:24.413282 [TxChooseVref] Worse bit 10, Min win 26, Win sum 434, Final Vref 30
3027 23:45:24.413347
3028 23:45:24.413413 Final TX Range 1 Vref 30
3029 23:45:24.413478
3030 23:45:24.413543 ==
3031 23:45:24.413617 Dram Type= 6, Freq= 0, CH_0, rank 1
3032 23:45:24.413714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3033 23:45:24.413812 ==
3034 23:45:24.413905
3035 23:45:24.413973
3036 23:45:24.414039 TX Vref Scan disable
3037 23:45:24.414104 == TX Byte 0 ==
3038 23:45:24.414179 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3039 23:45:24.414247 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3040 23:45:24.414315 == TX Byte 1 ==
3041 23:45:24.414584 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3042 23:45:24.414645 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3043 23:45:24.414698
3044 23:45:24.414750 [DATLAT]
3045 23:45:24.414800 Freq=1200, CH0 RK1
3046 23:45:24.414852
3047 23:45:24.414903 DATLAT Default: 0xd
3048 23:45:24.414954 0, 0xFFFF, sum = 0
3049 23:45:24.415007 1, 0xFFFF, sum = 0
3050 23:45:24.415059 2, 0xFFFF, sum = 0
3051 23:45:24.415111 3, 0xFFFF, sum = 0
3052 23:45:24.415162 4, 0xFFFF, sum = 0
3053 23:45:24.415214 5, 0xFFFF, sum = 0
3054 23:45:24.415265 6, 0xFFFF, sum = 0
3055 23:45:24.415316 7, 0xFFFF, sum = 0
3056 23:45:24.415367 8, 0xFFFF, sum = 0
3057 23:45:24.415419 9, 0xFFFF, sum = 0
3058 23:45:24.415471 10, 0xFFFF, sum = 0
3059 23:45:24.415522 11, 0xFFFF, sum = 0
3060 23:45:24.415574 12, 0x0, sum = 1
3061 23:45:24.415626 13, 0x0, sum = 2
3062 23:45:24.415677 14, 0x0, sum = 3
3063 23:45:24.415729 15, 0x0, sum = 4
3064 23:45:24.415801 best_step = 13
3065 23:45:24.415853
3066 23:45:24.415904 ==
3067 23:45:24.415955 Dram Type= 6, Freq= 0, CH_0, rank 1
3068 23:45:24.416007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3069 23:45:24.416059 ==
3070 23:45:24.416110 RX Vref Scan: 0
3071 23:45:24.416162
3072 23:45:24.416213 RX Vref 0 -> 0, step: 1
3073 23:45:24.416264
3074 23:45:24.416314 RX Delay -21 -> 252, step: 4
3075 23:45:24.416365 iDelay=199, Bit 0, Center 114 (51 ~ 178) 128
3076 23:45:24.416416 iDelay=199, Bit 1, Center 118 (47 ~ 190) 144
3077 23:45:24.416468 iDelay=199, Bit 2, Center 110 (43 ~ 178) 136
3078 23:45:24.416519 iDelay=199, Bit 3, Center 114 (43 ~ 186) 144
3079 23:45:24.416570 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3080 23:45:24.416621 iDelay=199, Bit 5, Center 110 (43 ~ 178) 136
3081 23:45:24.416672 iDelay=199, Bit 6, Center 126 (55 ~ 198) 144
3082 23:45:24.416723 iDelay=199, Bit 7, Center 124 (55 ~ 194) 140
3083 23:45:24.416774 iDelay=199, Bit 8, Center 96 (27 ~ 166) 140
3084 23:45:24.416824 iDelay=199, Bit 9, Center 94 (27 ~ 162) 136
3085 23:45:24.416884 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3086 23:45:24.416944 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3087 23:45:24.416995 iDelay=199, Bit 12, Center 112 (47 ~ 178) 132
3088 23:45:24.417047 iDelay=199, Bit 13, Center 114 (47 ~ 182) 136
3089 23:45:24.417099 iDelay=199, Bit 14, Center 118 (55 ~ 182) 128
3090 23:45:24.417150 iDelay=199, Bit 15, Center 116 (51 ~ 182) 132
3091 23:45:24.417201 ==
3092 23:45:24.417253 Dram Type= 6, Freq= 0, CH_0, rank 1
3093 23:45:24.417305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3094 23:45:24.417356 ==
3095 23:45:24.417407 DQS Delay:
3096 23:45:24.417458 DQS0 = 0, DQS1 = 0
3097 23:45:24.417509 DQM Delay:
3098 23:45:24.417561 DQM0 = 116, DQM1 = 107
3099 23:45:24.417611 DQ Delay:
3100 23:45:24.417662 DQ0 =114, DQ1 =118, DQ2 =110, DQ3 =114
3101 23:45:24.417714 DQ4 =116, DQ5 =110, DQ6 =126, DQ7 =124
3102 23:45:24.417765 DQ8 =96, DQ9 =94, DQ10 =110, DQ11 =100
3103 23:45:24.417817 DQ12 =112, DQ13 =114, DQ14 =118, DQ15 =116
3104 23:45:24.417877
3105 23:45:24.417929
3106 23:45:24.417980 [DQSOSCAuto] RK1, (LSB)MR18= 0xfeb, (MSB)MR19= 0x403, tDQSOscB0 = 418 ps tDQSOscB1 = 404 ps
3107 23:45:24.418033 CH0 RK1: MR19=403, MR18=FEB
3108 23:45:24.418085 CH0_RK1: MR19=0x403, MR18=0xFEB, DQSOSC=404, MR23=63, INC=40, DEC=26
3109 23:45:24.418137 [RxdqsGatingPostProcess] freq 1200
3110 23:45:24.418229 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3111 23:45:24.418282 best DQS0 dly(2T, 0.5T) = (0, 11)
3112 23:45:24.418333 best DQS1 dly(2T, 0.5T) = (0, 12)
3113 23:45:24.418384 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3114 23:45:24.418435 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3115 23:45:24.418486 best DQS0 dly(2T, 0.5T) = (0, 11)
3116 23:45:24.418537 best DQS1 dly(2T, 0.5T) = (0, 12)
3117 23:45:24.418588 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3118 23:45:24.418639 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3119 23:45:24.418690 Pre-setting of DQS Precalculation
3120 23:45:24.418742 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3121 23:45:24.418793 ==
3122 23:45:24.418845 Dram Type= 6, Freq= 0, CH_1, rank 0
3123 23:45:24.418897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3124 23:45:24.418948 ==
3125 23:45:24.418999 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3126 23:45:24.419051 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3127 23:45:24.419102 [CA 0] Center 37 (7~67) winsize 61
3128 23:45:24.419154 [CA 1] Center 38 (8~68) winsize 61
3129 23:45:24.419205 [CA 2] Center 34 (4~64) winsize 61
3130 23:45:24.419256 [CA 3] Center 33 (3~64) winsize 62
3131 23:45:24.419306 [CA 4] Center 34 (4~64) winsize 61
3132 23:45:24.419357 [CA 5] Center 33 (3~64) winsize 62
3133 23:45:24.419407
3134 23:45:24.419457 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3135 23:45:24.419509
3136 23:45:24.419560 [CATrainingPosCal] consider 1 rank data
3137 23:45:24.419611 u2DelayCellTimex100 = 270/100 ps
3138 23:45:24.419662 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3139 23:45:24.419713 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3140 23:45:24.419764 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3141 23:45:24.419815 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3142 23:45:24.419866 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3143 23:45:24.419917 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3144 23:45:24.419967
3145 23:45:24.420019 CA PerBit enable=1, Macro0, CA PI delay=33
3146 23:45:24.420070
3147 23:45:24.420120 [CBTSetCACLKResult] CA Dly = 33
3148 23:45:24.420172 CS Dly: 6 (0~37)
3149 23:45:24.420222 ==
3150 23:45:24.420274 Dram Type= 6, Freq= 0, CH_1, rank 1
3151 23:45:24.420326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3152 23:45:24.420377 ==
3153 23:45:24.420428 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3154 23:45:24.420480 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3155 23:45:24.420531 [CA 0] Center 37 (7~67) winsize 61
3156 23:45:24.420582 [CA 1] Center 38 (8~68) winsize 61
3157 23:45:24.420633 [CA 2] Center 34 (4~65) winsize 62
3158 23:45:24.420684 [CA 3] Center 33 (3~64) winsize 62
3159 23:45:24.420735 [CA 4] Center 34 (4~65) winsize 62
3160 23:45:24.420785 [CA 5] Center 33 (3~64) winsize 62
3161 23:45:24.420836
3162 23:45:24.420887 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3163 23:45:24.420938
3164 23:45:24.420988 [CATrainingPosCal] consider 2 rank data
3165 23:45:24.421040 u2DelayCellTimex100 = 270/100 ps
3166 23:45:24.421091 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3167 23:45:24.421141 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3168 23:45:24.421192 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3169 23:45:24.421243 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3170 23:45:24.421294 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3171 23:45:24.421556 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3172 23:45:24.421648
3173 23:45:24.421750 CA PerBit enable=1, Macro0, CA PI delay=33
3174 23:45:24.421845
3175 23:45:24.421937 [CBTSetCACLKResult] CA Dly = 33
3176 23:45:24.422020 CS Dly: 7 (0~40)
3177 23:45:24.422100
3178 23:45:24.422191 ----->DramcWriteLeveling(PI) begin...
3179 23:45:24.422288 ==
3180 23:45:24.422371 Dram Type= 6, Freq= 0, CH_1, rank 0
3181 23:45:24.422453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3182 23:45:24.422535 ==
3183 23:45:24.422616 Write leveling (Byte 0): 24 => 24
3184 23:45:24.422697 Write leveling (Byte 1): 29 => 29
3185 23:45:24.422777 DramcWriteLeveling(PI) end<-----
3186 23:45:24.422857
3187 23:45:24.422936 ==
3188 23:45:24.423017 Dram Type= 6, Freq= 0, CH_1, rank 0
3189 23:45:24.423098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3190 23:45:24.423179 ==
3191 23:45:24.423259 [Gating] SW mode calibration
3192 23:45:24.423341 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3193 23:45:24.423422 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3194 23:45:24.423503 0 15 0 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
3195 23:45:24.423585 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3196 23:45:24.423666 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3197 23:45:24.423755 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3198 23:45:24.423840 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3199 23:45:24.423921 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3200 23:45:24.424002 0 15 24 | B1->B0 | 3434 3131 | 1 0 | (1 0) (0 0)
3201 23:45:24.424083 0 15 28 | B1->B0 | 2626 2424 | 0 0 | (0 0) (1 0)
3202 23:45:24.424163 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3203 23:45:24.424244 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3204 23:45:24.424325 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3205 23:45:24.424406 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3206 23:45:24.424487 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3207 23:45:24.424568 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3208 23:45:24.424649 1 0 24 | B1->B0 | 2a2a 3f3f | 1 0 | (0 0) (0 0)
3209 23:45:24.424762 1 0 28 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
3210 23:45:24.424857 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3211 23:45:24.424938 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3212 23:45:24.425018 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3213 23:45:24.425099 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3214 23:45:24.425179 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3215 23:45:24.425260 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3216 23:45:24.425340 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3217 23:45:24.425421 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3218 23:45:24.425501 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3219 23:45:24.425582 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3220 23:45:24.425663 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3221 23:45:24.425752 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3222 23:45:24.425833 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3223 23:45:24.425914 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3224 23:45:24.425995 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3225 23:45:24.426075 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3226 23:45:24.426156 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3227 23:45:24.426221 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3228 23:45:24.426273 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3229 23:45:24.426325 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3230 23:45:24.426377 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3231 23:45:24.426428 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3232 23:45:24.426479 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3233 23:45:24.426530 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3234 23:45:24.426581 Total UI for P1: 0, mck2ui 16
3235 23:45:24.426633 best dqsien dly found for B0: ( 1, 3, 24)
3236 23:45:24.426684 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3237 23:45:24.426735 Total UI for P1: 0, mck2ui 16
3238 23:45:24.426787 best dqsien dly found for B1: ( 1, 3, 28)
3239 23:45:24.426838 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3240 23:45:24.426889 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3241 23:45:24.426940
3242 23:45:24.426991 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3243 23:45:24.427042 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3244 23:45:24.427094 [Gating] SW calibration Done
3245 23:45:24.427144 ==
3246 23:45:24.427196 Dram Type= 6, Freq= 0, CH_1, rank 0
3247 23:45:24.427248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3248 23:45:24.427300 ==
3249 23:45:24.427351 RX Vref Scan: 0
3250 23:45:24.427402
3251 23:45:24.427453 RX Vref 0 -> 0, step: 1
3252 23:45:24.427505
3253 23:45:24.427556 RX Delay -40 -> 252, step: 8
3254 23:45:24.427606 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3255 23:45:24.427667 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3256 23:45:24.427722 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3257 23:45:24.427800 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3258 23:45:24.427869 iDelay=208, Bit 4, Center 111 (40 ~ 183) 144
3259 23:45:24.427944 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3260 23:45:24.428004 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3261 23:45:24.428057 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3262 23:45:24.428109 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3263 23:45:24.428160 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3264 23:45:24.428251 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3265 23:45:24.428303 iDelay=208, Bit 11, Center 95 (24 ~ 167) 144
3266 23:45:24.428355 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3267 23:45:24.428422 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3268 23:45:24.428490 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3269 23:45:24.428543 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3270 23:45:24.428594 ==
3271 23:45:24.428647 Dram Type= 6, Freq= 0, CH_1, rank 0
3272 23:45:24.428698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3273 23:45:24.428750 ==
3274 23:45:24.428999 DQS Delay:
3275 23:45:24.429058 DQS0 = 0, DQS1 = 0
3276 23:45:24.429110 DQM Delay:
3277 23:45:24.429162 DQM0 = 117, DQM1 = 109
3278 23:45:24.429214 DQ Delay:
3279 23:45:24.429265 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =115
3280 23:45:24.429317 DQ4 =111, DQ5 =131, DQ6 =123, DQ7 =115
3281 23:45:24.429368 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =95
3282 23:45:24.429419 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3283 23:45:24.429470
3284 23:45:24.429521
3285 23:45:24.429571 ==
3286 23:45:24.429623 Dram Type= 6, Freq= 0, CH_1, rank 0
3287 23:45:24.429687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3288 23:45:24.429755 ==
3289 23:45:24.429859
3290 23:45:24.429925
3291 23:45:24.429975 TX Vref Scan disable
3292 23:45:24.430027 == TX Byte 0 ==
3293 23:45:24.430078 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3294 23:45:24.430130 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3295 23:45:24.430218 == TX Byte 1 ==
3296 23:45:24.430271 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3297 23:45:24.430322 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3298 23:45:24.430373 ==
3299 23:45:24.430424 Dram Type= 6, Freq= 0, CH_1, rank 0
3300 23:45:24.430476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3301 23:45:24.430527 ==
3302 23:45:24.430578 TX Vref=22, minBit 10, minWin=25, winSum=417
3303 23:45:24.430630 TX Vref=24, minBit 8, minWin=25, winSum=422
3304 23:45:24.430681 TX Vref=26, minBit 8, minWin=25, winSum=427
3305 23:45:24.430733 TX Vref=28, minBit 10, minWin=25, winSum=431
3306 23:45:24.430784 TX Vref=30, minBit 9, minWin=26, winSum=433
3307 23:45:24.430835 TX Vref=32, minBit 9, minWin=25, winSum=427
3308 23:45:24.430886 [TxChooseVref] Worse bit 9, Min win 26, Win sum 433, Final Vref 30
3309 23:45:24.430937
3310 23:45:24.430988 Final TX Range 1 Vref 30
3311 23:45:24.431039
3312 23:45:24.431090 ==
3313 23:45:24.431141 Dram Type= 6, Freq= 0, CH_1, rank 0
3314 23:45:24.431192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3315 23:45:24.431243 ==
3316 23:45:24.431294
3317 23:45:24.431345
3318 23:45:24.431404 TX Vref Scan disable
3319 23:45:24.431456 == TX Byte 0 ==
3320 23:45:24.431512 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3321 23:45:24.431581 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3322 23:45:24.431646 == TX Byte 1 ==
3323 23:45:24.431712 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3324 23:45:24.431772 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3325 23:45:24.431824
3326 23:45:24.431875 [DATLAT]
3327 23:45:24.431925 Freq=1200, CH1 RK0
3328 23:45:24.431977
3329 23:45:24.432028 DATLAT Default: 0xd
3330 23:45:24.432079 0, 0xFFFF, sum = 0
3331 23:45:24.432131 1, 0xFFFF, sum = 0
3332 23:45:24.432183 2, 0xFFFF, sum = 0
3333 23:45:24.432234 3, 0xFFFF, sum = 0
3334 23:45:24.432286 4, 0xFFFF, sum = 0
3335 23:45:24.432338 5, 0xFFFF, sum = 0
3336 23:45:24.432389 6, 0xFFFF, sum = 0
3337 23:45:24.432441 7, 0xFFFF, sum = 0
3338 23:45:24.432492 8, 0xFFFF, sum = 0
3339 23:45:24.432544 9, 0xFFFF, sum = 0
3340 23:45:24.432594 10, 0xFFFF, sum = 0
3341 23:45:24.432646 11, 0xFFFF, sum = 0
3342 23:45:24.432697 12, 0x0, sum = 1
3343 23:45:24.432748 13, 0x0, sum = 2
3344 23:45:24.432798 14, 0x0, sum = 3
3345 23:45:24.432850 15, 0x0, sum = 4
3346 23:45:24.432901 best_step = 13
3347 23:45:24.432950
3348 23:45:24.433001 ==
3349 23:45:24.433051 Dram Type= 6, Freq= 0, CH_1, rank 0
3350 23:45:24.433103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3351 23:45:24.433154 ==
3352 23:45:24.433204 RX Vref Scan: 1
3353 23:45:24.433254
3354 23:45:24.433305 Set Vref Range= 32 -> 127
3355 23:45:24.433355
3356 23:45:24.433405 RX Vref 32 -> 127, step: 1
3357 23:45:24.433455
3358 23:45:24.433505 RX Delay -21 -> 252, step: 4
3359 23:45:24.433556
3360 23:45:24.433606 Set Vref, RX VrefLevel [Byte0]: 32
3361 23:45:24.433657 [Byte1]: 32
3362 23:45:24.433710
3363 23:45:24.433768 Set Vref, RX VrefLevel [Byte0]: 33
3364 23:45:24.433825 [Byte1]: 33
3365 23:45:24.433906
3366 23:45:24.433956 Set Vref, RX VrefLevel [Byte0]: 34
3367 23:45:24.434007 [Byte1]: 34
3368 23:45:24.434058
3369 23:45:24.434107 Set Vref, RX VrefLevel [Byte0]: 35
3370 23:45:24.434158 [Byte1]: 35
3371 23:45:24.434245
3372 23:45:24.434296 Set Vref, RX VrefLevel [Byte0]: 36
3373 23:45:24.434347 [Byte1]: 36
3374 23:45:24.434397
3375 23:45:24.434448 Set Vref, RX VrefLevel [Byte0]: 37
3376 23:45:24.434500 [Byte1]: 37
3377 23:45:24.434551
3378 23:45:24.434611 Set Vref, RX VrefLevel [Byte0]: 38
3379 23:45:24.434667 [Byte1]: 38
3380 23:45:24.434718
3381 23:45:24.434769 Set Vref, RX VrefLevel [Byte0]: 39
3382 23:45:24.434819 [Byte1]: 39
3383 23:45:24.434869
3384 23:45:24.434932 Set Vref, RX VrefLevel [Byte0]: 40
3385 23:45:24.434986 [Byte1]: 40
3386 23:45:24.435037
3387 23:45:24.435087 Set Vref, RX VrefLevel [Byte0]: 41
3388 23:45:24.435138 [Byte1]: 41
3389 23:45:24.435189
3390 23:45:24.435239 Set Vref, RX VrefLevel [Byte0]: 42
3391 23:45:24.435289 [Byte1]: 42
3392 23:45:24.435339
3393 23:45:24.435390 Set Vref, RX VrefLevel [Byte0]: 43
3394 23:45:24.435441 [Byte1]: 43
3395 23:45:24.435491
3396 23:45:24.435540 Set Vref, RX VrefLevel [Byte0]: 44
3397 23:45:24.435591 [Byte1]: 44
3398 23:45:24.435641
3399 23:45:24.435692 Set Vref, RX VrefLevel [Byte0]: 45
3400 23:45:24.435742 [Byte1]: 45
3401 23:45:24.435792
3402 23:45:24.435843 Set Vref, RX VrefLevel [Byte0]: 46
3403 23:45:24.435893 [Byte1]: 46
3404 23:45:24.435943
3405 23:45:24.435993 Set Vref, RX VrefLevel [Byte0]: 47
3406 23:45:24.436044 [Byte1]: 47
3407 23:45:24.436094
3408 23:45:24.436144 Set Vref, RX VrefLevel [Byte0]: 48
3409 23:45:24.436195 [Byte1]: 48
3410 23:45:24.436245
3411 23:45:24.436295 Set Vref, RX VrefLevel [Byte0]: 49
3412 23:45:24.436346 [Byte1]: 49
3413 23:45:24.436396
3414 23:45:24.436447 Set Vref, RX VrefLevel [Byte0]: 50
3415 23:45:24.436497 [Byte1]: 50
3416 23:45:24.436548
3417 23:45:24.436598 Set Vref, RX VrefLevel [Byte0]: 51
3418 23:45:24.436649 [Byte1]: 51
3419 23:45:24.436699
3420 23:45:24.436750 Set Vref, RX VrefLevel [Byte0]: 52
3421 23:45:24.436801 [Byte1]: 52
3422 23:45:24.436851
3423 23:45:24.436901 Set Vref, RX VrefLevel [Byte0]: 53
3424 23:45:24.436951 [Byte1]: 53
3425 23:45:24.437001
3426 23:45:24.437052 Set Vref, RX VrefLevel [Byte0]: 54
3427 23:45:24.437102 [Byte1]: 54
3428 23:45:24.437152
3429 23:45:24.437202 Set Vref, RX VrefLevel [Byte0]: 55
3430 23:45:24.437253 [Byte1]: 55
3431 23:45:24.437305
3432 23:45:24.437356 Set Vref, RX VrefLevel [Byte0]: 56
3433 23:45:24.437406 [Byte1]: 56
3434 23:45:24.437457
3435 23:45:24.437507 Set Vref, RX VrefLevel [Byte0]: 57
3436 23:45:24.437558 [Byte1]: 57
3437 23:45:24.437617
3438 23:45:24.437668 Set Vref, RX VrefLevel [Byte0]: 58
3439 23:45:24.437718 [Byte1]: 58
3440 23:45:24.437768
3441 23:45:24.437818 Set Vref, RX VrefLevel [Byte0]: 59
3442 23:45:24.438066 [Byte1]: 59
3443 23:45:24.438124
3444 23:45:24.438207 Set Vref, RX VrefLevel [Byte0]: 60
3445 23:45:24.438291 [Byte1]: 60
3446 23:45:24.438380
3447 23:45:24.438487 Set Vref, RX VrefLevel [Byte0]: 61
3448 23:45:24.438544 [Byte1]: 61
3449 23:45:24.438596
3450 23:45:24.438647 Set Vref, RX VrefLevel [Byte0]: 62
3451 23:45:24.438698 [Byte1]: 62
3452 23:45:24.438749
3453 23:45:24.438800 Set Vref, RX VrefLevel [Byte0]: 63
3454 23:45:24.438851 [Byte1]: 63
3455 23:45:24.438902
3456 23:45:24.438952 Set Vref, RX VrefLevel [Byte0]: 64
3457 23:45:24.439003 [Byte1]: 64
3458 23:45:24.439054
3459 23:45:24.439105 Set Vref, RX VrefLevel [Byte0]: 65
3460 23:45:24.439157 [Byte1]: 65
3461 23:45:24.439208
3462 23:45:24.439259 Set Vref, RX VrefLevel [Byte0]: 66
3463 23:45:24.439309 [Byte1]: 66
3464 23:45:24.439368
3465 23:45:24.439420 Set Vref, RX VrefLevel [Byte0]: 67
3466 23:45:24.439470 [Byte1]: 67
3467 23:45:24.439521
3468 23:45:24.439572 Final RX Vref Byte 0 = 49 to rank0
3469 23:45:24.439623 Final RX Vref Byte 1 = 54 to rank0
3470 23:45:24.439674 Final RX Vref Byte 0 = 49 to rank1
3471 23:45:24.439732 Final RX Vref Byte 1 = 54 to rank1==
3472 23:45:24.439783 Dram Type= 6, Freq= 0, CH_1, rank 0
3473 23:45:24.439834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3474 23:45:24.439885 ==
3475 23:45:24.439937 DQS Delay:
3476 23:45:24.439993 DQS0 = 0, DQS1 = 0
3477 23:45:24.440055 DQM Delay:
3478 23:45:24.440107 DQM0 = 116, DQM1 = 110
3479 23:45:24.440158 DQ Delay:
3480 23:45:24.440209 DQ0 =120, DQ1 =112, DQ2 =108, DQ3 =112
3481 23:45:24.440260 DQ4 =114, DQ5 =126, DQ6 =126, DQ7 =112
3482 23:45:24.440311 DQ8 =98, DQ9 =102, DQ10 =112, DQ11 =100
3483 23:45:24.440361 DQ12 =118, DQ13 =118, DQ14 =118, DQ15 =118
3484 23:45:24.440412
3485 23:45:24.440462
3486 23:45:24.440513 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f5, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 409 ps
3487 23:45:24.440565 CH1 RK0: MR19=403, MR18=2F5
3488 23:45:24.440616 CH1_RK0: MR19=0x403, MR18=0x2F5, DQSOSC=409, MR23=63, INC=39, DEC=26
3489 23:45:24.440668
3490 23:45:24.440726 ----->DramcWriteLeveling(PI) begin...
3491 23:45:24.440780 ==
3492 23:45:24.440831 Dram Type= 6, Freq= 0, CH_1, rank 1
3493 23:45:24.440882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3494 23:45:24.440933 ==
3495 23:45:24.440984 Write leveling (Byte 0): 24 => 24
3496 23:45:24.441035 Write leveling (Byte 1): 28 => 28
3497 23:45:24.441085 DramcWriteLeveling(PI) end<-----
3498 23:45:24.441136
3499 23:45:24.441186 ==
3500 23:45:24.441236 Dram Type= 6, Freq= 0, CH_1, rank 1
3501 23:45:24.441288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3502 23:45:24.441343 ==
3503 23:45:24.441409 [Gating] SW mode calibration
3504 23:45:24.441469 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3505 23:45:24.441522 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3506 23:45:24.441574 0 15 0 | B1->B0 | 3434 3030 | 1 1 | (1 1) (0 0)
3507 23:45:24.441625 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3508 23:45:24.441675 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3509 23:45:24.441726 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3510 23:45:24.441777 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3511 23:45:24.441828 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3512 23:45:24.441878 0 15 24 | B1->B0 | 3030 3434 | 1 1 | (1 0) (1 1)
3513 23:45:24.441929 0 15 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3514 23:45:24.441979 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3515 23:45:24.442030 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3516 23:45:24.442080 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3517 23:45:24.442130 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3518 23:45:24.442223 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3519 23:45:24.442275 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3520 23:45:24.442326 1 0 24 | B1->B0 | 3b3a 2828 | 1 1 | (0 0) (0 0)
3521 23:45:24.442377 1 0 28 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3522 23:45:24.442428 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3523 23:45:24.442479 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3524 23:45:24.442529 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3525 23:45:24.442580 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3526 23:45:24.442630 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3527 23:45:24.442680 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3528 23:45:24.442732 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3529 23:45:24.442782 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3530 23:45:24.442832 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3531 23:45:24.442882 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3532 23:45:24.442933 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3533 23:45:24.442983 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3534 23:45:24.443033 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3535 23:45:24.443084 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3536 23:45:24.443135 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3537 23:45:24.443185 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3538 23:45:24.443235 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3539 23:45:24.443286 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3540 23:45:24.443340 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3541 23:45:24.443397 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3542 23:45:24.443447 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3543 23:45:24.443498 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3544 23:45:24.443548 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3545 23:45:24.443599 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3546 23:45:24.443649 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3547 23:45:24.443700 Total UI for P1: 0, mck2ui 16
3548 23:45:24.443751 best dqsien dly found for B0: ( 1, 3, 26)
3549 23:45:24.443802 Total UI for P1: 0, mck2ui 16
3550 23:45:24.443853 best dqsien dly found for B1: ( 1, 3, 26)
3551 23:45:24.444109 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3552 23:45:24.444169 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3553 23:45:24.444221
3554 23:45:24.444272 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3555 23:45:24.444324 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3556 23:45:24.444375 [Gating] SW calibration Done
3557 23:45:24.444425 ==
3558 23:45:24.444486 Dram Type= 6, Freq= 0, CH_1, rank 1
3559 23:45:24.444538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3560 23:45:24.444590 ==
3561 23:45:24.444641 RX Vref Scan: 0
3562 23:45:24.444692
3563 23:45:24.444742 RX Vref 0 -> 0, step: 1
3564 23:45:24.444793
3565 23:45:24.444844 RX Delay -40 -> 252, step: 8
3566 23:45:24.444895 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3567 23:45:24.444945 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3568 23:45:24.444996 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3569 23:45:24.445047 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3570 23:45:24.445097 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3571 23:45:24.445147 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3572 23:45:24.445199 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3573 23:45:24.445250 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3574 23:45:24.445300 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3575 23:45:24.445354 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3576 23:45:24.445447 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3577 23:45:24.445498 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3578 23:45:24.445549 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3579 23:45:24.445600 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3580 23:45:24.445650 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3581 23:45:24.445700 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
3582 23:45:24.445750 ==
3583 23:45:24.445801 Dram Type= 6, Freq= 0, CH_1, rank 1
3584 23:45:24.445852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3585 23:45:24.445903 ==
3586 23:45:24.445954 DQS Delay:
3587 23:45:24.446005 DQS0 = 0, DQS1 = 0
3588 23:45:24.446056 DQM Delay:
3589 23:45:24.446106 DQM0 = 116, DQM1 = 109
3590 23:45:24.446157 DQ Delay:
3591 23:45:24.446248 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3592 23:45:24.446300 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =115
3593 23:45:24.446350 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3594 23:45:24.446401 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =115
3595 23:45:24.446452
3596 23:45:24.446502
3597 23:45:24.446552 ==
3598 23:45:24.446603 Dram Type= 6, Freq= 0, CH_1, rank 1
3599 23:45:24.446655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3600 23:45:24.446706 ==
3601 23:45:24.446757
3602 23:45:24.446806
3603 23:45:24.446857 TX Vref Scan disable
3604 23:45:24.446907 == TX Byte 0 ==
3605 23:45:24.446958 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3606 23:45:24.447009 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3607 23:45:24.447060 == TX Byte 1 ==
3608 23:45:24.447112 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3609 23:45:24.447162 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3610 23:45:24.447213 ==
3611 23:45:24.447264 Dram Type= 6, Freq= 0, CH_1, rank 1
3612 23:45:24.447315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3613 23:45:24.447381 ==
3614 23:45:24.447472 TX Vref=22, minBit 8, minWin=26, winSum=431
3615 23:45:24.447542 TX Vref=24, minBit 9, minWin=25, winSum=429
3616 23:45:24.447635 TX Vref=26, minBit 9, minWin=25, winSum=432
3617 23:45:24.447689 TX Vref=28, minBit 9, minWin=26, winSum=439
3618 23:45:24.447741 TX Vref=30, minBit 2, minWin=27, winSum=437
3619 23:45:24.447793 TX Vref=32, minBit 9, minWin=26, winSum=436
3620 23:45:24.447845 [TxChooseVref] Worse bit 2, Min win 27, Win sum 437, Final Vref 30
3621 23:45:24.447896
3622 23:45:24.447947 Final TX Range 1 Vref 30
3623 23:45:24.447999
3624 23:45:24.448049 ==
3625 23:45:24.448099 Dram Type= 6, Freq= 0, CH_1, rank 1
3626 23:45:24.448150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3627 23:45:24.448201 ==
3628 23:45:24.448252
3629 23:45:24.448303
3630 23:45:24.448353 TX Vref Scan disable
3631 23:45:24.448404 == TX Byte 0 ==
3632 23:45:24.448454 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3633 23:45:24.448506 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3634 23:45:24.448556 == TX Byte 1 ==
3635 23:45:24.448606 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3636 23:45:24.448657 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3637 23:45:24.448707
3638 23:45:24.448758 [DATLAT]
3639 23:45:24.448808 Freq=1200, CH1 RK1
3640 23:45:24.448859
3641 23:45:24.448910 DATLAT Default: 0xd
3642 23:45:24.448960 0, 0xFFFF, sum = 0
3643 23:45:24.449012 1, 0xFFFF, sum = 0
3644 23:45:24.449063 2, 0xFFFF, sum = 0
3645 23:45:24.449114 3, 0xFFFF, sum = 0
3646 23:45:24.449166 4, 0xFFFF, sum = 0
3647 23:45:24.449217 5, 0xFFFF, sum = 0
3648 23:45:24.449268 6, 0xFFFF, sum = 0
3649 23:45:24.449319 7, 0xFFFF, sum = 0
3650 23:45:24.449371 8, 0xFFFF, sum = 0
3651 23:45:24.449422 9, 0xFFFF, sum = 0
3652 23:45:24.449472 10, 0xFFFF, sum = 0
3653 23:45:24.449523 11, 0xFFFF, sum = 0
3654 23:45:24.449575 12, 0x0, sum = 1
3655 23:45:24.449626 13, 0x0, sum = 2
3656 23:45:24.449677 14, 0x0, sum = 3
3657 23:45:24.449728 15, 0x0, sum = 4
3658 23:45:24.449780 best_step = 13
3659 23:45:24.449830
3660 23:45:24.449880 ==
3661 23:45:24.449930 Dram Type= 6, Freq= 0, CH_1, rank 1
3662 23:45:24.449981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3663 23:45:24.450032 ==
3664 23:45:24.450082 RX Vref Scan: 0
3665 23:45:24.450133
3666 23:45:24.450213 RX Vref 0 -> 0, step: 1
3667 23:45:24.450278
3668 23:45:24.450329 RX Delay -21 -> 252, step: 4
3669 23:45:24.450380 iDelay=199, Bit 0, Center 118 (51 ~ 186) 136
3670 23:45:24.450431 iDelay=199, Bit 1, Center 112 (47 ~ 178) 132
3671 23:45:24.450482 iDelay=199, Bit 2, Center 106 (43 ~ 170) 128
3672 23:45:24.450533 iDelay=199, Bit 3, Center 114 (51 ~ 178) 128
3673 23:45:24.450584 iDelay=199, Bit 4, Center 114 (47 ~ 182) 136
3674 23:45:24.450634 iDelay=199, Bit 5, Center 126 (59 ~ 194) 136
3675 23:45:24.450685 iDelay=199, Bit 6, Center 130 (63 ~ 198) 136
3676 23:45:24.450735 iDelay=199, Bit 7, Center 116 (51 ~ 182) 132
3677 23:45:24.450785 iDelay=199, Bit 8, Center 96 (31 ~ 162) 132
3678 23:45:24.450836 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3679 23:45:24.450886 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3680 23:45:24.450936 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3681 23:45:24.450987 iDelay=199, Bit 12, Center 118 (51 ~ 186) 136
3682 23:45:24.451037 iDelay=199, Bit 13, Center 118 (51 ~ 186) 136
3683 23:45:24.451088 iDelay=199, Bit 14, Center 118 (51 ~ 186) 136
3684 23:45:24.451138 iDelay=199, Bit 15, Center 118 (51 ~ 186) 136
3685 23:45:24.451189 ==
3686 23:45:24.451239 Dram Type= 6, Freq= 0, CH_1, rank 1
3687 23:45:24.451300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3688 23:45:24.451353 ==
3689 23:45:24.451404 DQS Delay:
3690 23:45:24.451454 DQS0 = 0, DQS1 = 0
3691 23:45:24.451505 DQM Delay:
3692 23:45:24.451556 DQM0 = 117, DQM1 = 109
3693 23:45:24.451606 DQ Delay:
3694 23:45:24.451854 DQ0 =118, DQ1 =112, DQ2 =106, DQ3 =114
3695 23:45:24.451913 DQ4 =114, DQ5 =126, DQ6 =130, DQ7 =116
3696 23:45:24.451964 DQ8 =96, DQ9 =100, DQ10 =110, DQ11 =100
3697 23:45:24.452016 DQ12 =118, DQ13 =118, DQ14 =118, DQ15 =118
3698 23:45:24.452067
3699 23:45:24.452118
3700 23:45:24.452168 [DQSOSCAuto] RK1, (LSB)MR18= 0xf4ee, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 415 ps
3701 23:45:24.452221 CH1 RK1: MR19=303, MR18=F4EE
3702 23:45:24.452271 CH1_RK1: MR19=0x303, MR18=0xF4EE, DQSOSC=415, MR23=63, INC=38, DEC=25
3703 23:45:24.452322 [RxdqsGatingPostProcess] freq 1200
3704 23:45:24.452373 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3705 23:45:24.452424 best DQS0 dly(2T, 0.5T) = (0, 11)
3706 23:45:24.452474 best DQS1 dly(2T, 0.5T) = (0, 11)
3707 23:45:24.452525 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3708 23:45:24.452576 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3709 23:45:24.452627 best DQS0 dly(2T, 0.5T) = (0, 11)
3710 23:45:24.452683 best DQS1 dly(2T, 0.5T) = (0, 11)
3711 23:45:24.452734 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3712 23:45:24.452785 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3713 23:45:24.452835 Pre-setting of DQS Precalculation
3714 23:45:24.452886 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3715 23:45:24.452937 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3716 23:45:24.452996 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3717 23:45:24.453048
3718 23:45:24.453099
3719 23:45:24.453148 [Calibration Summary] 2400 Mbps
3720 23:45:24.453199 CH 0, Rank 0
3721 23:45:24.453249 SW Impedance : PASS
3722 23:45:24.453300 DUTY Scan : NO K
3723 23:45:24.453350 ZQ Calibration : PASS
3724 23:45:24.453400 Jitter Meter : NO K
3725 23:45:24.453451 CBT Training : PASS
3726 23:45:24.453502 Write leveling : PASS
3727 23:45:24.453552 RX DQS gating : PASS
3728 23:45:24.453602 RX DQ/DQS(RDDQC) : PASS
3729 23:45:24.453652 TX DQ/DQS : PASS
3730 23:45:24.453703 RX DATLAT : PASS
3731 23:45:24.453752 RX DQ/DQS(Engine): PASS
3732 23:45:24.453802 TX OE : NO K
3733 23:45:24.453853 All Pass.
3734 23:45:24.453904
3735 23:45:24.453955 CH 0, Rank 1
3736 23:45:24.454012 SW Impedance : PASS
3737 23:45:24.454065 DUTY Scan : NO K
3738 23:45:24.454115 ZQ Calibration : PASS
3739 23:45:24.454192 Jitter Meter : NO K
3740 23:45:24.454258 CBT Training : PASS
3741 23:45:24.454309 Write leveling : PASS
3742 23:45:24.454359 RX DQS gating : PASS
3743 23:45:24.454409 RX DQ/DQS(RDDQC) : PASS
3744 23:45:24.454459 TX DQ/DQS : PASS
3745 23:45:24.454509 RX DATLAT : PASS
3746 23:45:24.454559 RX DQ/DQS(Engine): PASS
3747 23:45:24.454609 TX OE : NO K
3748 23:45:24.454660 All Pass.
3749 23:45:24.454711
3750 23:45:24.454760 CH 1, Rank 0
3751 23:45:24.454810 SW Impedance : PASS
3752 23:45:24.454861 DUTY Scan : NO K
3753 23:45:24.454911 ZQ Calibration : PASS
3754 23:45:24.454965 Jitter Meter : NO K
3755 23:45:24.455025 CBT Training : PASS
3756 23:45:24.455081 Write leveling : PASS
3757 23:45:24.455131 RX DQS gating : PASS
3758 23:45:24.455182 RX DQ/DQS(RDDQC) : PASS
3759 23:45:24.455232 TX DQ/DQS : PASS
3760 23:45:24.455282 RX DATLAT : PASS
3761 23:45:24.455333 RX DQ/DQS(Engine): PASS
3762 23:45:24.455383 TX OE : NO K
3763 23:45:24.455434 All Pass.
3764 23:45:24.455501
3765 23:45:24.455556 CH 1, Rank 1
3766 23:45:24.455607 SW Impedance : PASS
3767 23:45:24.455658 DUTY Scan : NO K
3768 23:45:24.455709 ZQ Calibration : PASS
3769 23:45:24.455759 Jitter Meter : NO K
3770 23:45:24.455810 CBT Training : PASS
3771 23:45:24.455860 Write leveling : PASS
3772 23:45:24.455910 RX DQS gating : PASS
3773 23:45:24.455961 RX DQ/DQS(RDDQC) : PASS
3774 23:45:24.456011 TX DQ/DQS : PASS
3775 23:45:24.456062 RX DATLAT : PASS
3776 23:45:24.456112 RX DQ/DQS(Engine): PASS
3777 23:45:24.456163 TX OE : NO K
3778 23:45:24.456214 All Pass.
3779 23:45:24.456264
3780 23:45:24.456314 DramC Write-DBI off
3781 23:45:24.456364 PER_BANK_REFRESH: Hybrid Mode
3782 23:45:24.456415 TX_TRACKING: ON
3783 23:45:24.456466 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3784 23:45:24.456518 [FAST_K] Save calibration result to emmc
3785 23:45:24.456568 dramc_set_vcore_voltage set vcore to 650000
3786 23:45:24.456618 Read voltage for 600, 5
3787 23:45:24.456668 Vio18 = 0
3788 23:45:24.456719 Vcore = 650000
3789 23:45:24.456769 Vdram = 0
3790 23:45:24.456819 Vddq = 0
3791 23:45:24.456869 Vmddr = 0
3792 23:45:24.456919 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3793 23:45:24.456970 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3794 23:45:24.457022 MEM_TYPE=3, freq_sel=19
3795 23:45:24.457075 sv_algorithm_assistance_LP4_1600
3796 23:45:24.457130 ============ PULL DRAM RESETB DOWN ============
3797 23:45:24.457181 ========== PULL DRAM RESETB DOWN end =========
3798 23:45:24.457233 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3799 23:45:24.457290 ===================================
3800 23:45:24.457343 LPDDR4 DRAM CONFIGURATION
3801 23:45:24.457394 ===================================
3802 23:45:24.457444 EX_ROW_EN[0] = 0x0
3803 23:45:24.457494 EX_ROW_EN[1] = 0x0
3804 23:45:24.457544 LP4Y_EN = 0x0
3805 23:45:24.457594 WORK_FSP = 0x0
3806 23:45:24.457644 WL = 0x2
3807 23:45:24.457694 RL = 0x2
3808 23:45:24.457743 BL = 0x2
3809 23:45:24.457793 RPST = 0x0
3810 23:45:24.457843 RD_PRE = 0x0
3811 23:45:24.457893 WR_PRE = 0x1
3812 23:45:24.457943 WR_PST = 0x0
3813 23:45:24.457993 DBI_WR = 0x0
3814 23:45:24.458042 DBI_RD = 0x0
3815 23:45:24.458092 OTF = 0x1
3816 23:45:24.458142 ===================================
3817 23:45:24.458242 ===================================
3818 23:45:24.458294 ANA top config
3819 23:45:24.458345 ===================================
3820 23:45:24.458396 DLL_ASYNC_EN = 0
3821 23:45:24.458446 ALL_SLAVE_EN = 1
3822 23:45:24.458496 NEW_RANK_MODE = 1
3823 23:45:24.458547 DLL_IDLE_MODE = 1
3824 23:45:24.458597 LP45_APHY_COMB_EN = 1
3825 23:45:24.458646 TX_ODT_DIS = 1
3826 23:45:24.458697 NEW_8X_MODE = 1
3827 23:45:24.458748 ===================================
3828 23:45:24.458798 ===================================
3829 23:45:24.458848 data_rate = 1200
3830 23:45:24.458899 CKR = 1
3831 23:45:24.458949 DQ_P2S_RATIO = 8
3832 23:45:24.458999 ===================================
3833 23:45:24.459050 CA_P2S_RATIO = 8
3834 23:45:24.459104 DQ_CA_OPEN = 0
3835 23:45:24.459163 DQ_SEMI_OPEN = 0
3836 23:45:24.459214 CA_SEMI_OPEN = 0
3837 23:45:24.459460 CA_FULL_RATE = 0
3838 23:45:24.459524 DQ_CKDIV4_EN = 1
3839 23:45:24.459577 CA_CKDIV4_EN = 1
3840 23:45:24.459628 CA_PREDIV_EN = 0
3841 23:45:24.459680 PH8_DLY = 0
3842 23:45:24.459731 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3843 23:45:24.459782 DQ_AAMCK_DIV = 4
3844 23:45:24.459832 CA_AAMCK_DIV = 4
3845 23:45:24.459883 CA_ADMCK_DIV = 4
3846 23:45:24.459934 DQ_TRACK_CA_EN = 0
3847 23:45:24.459984 CA_PICK = 600
3848 23:45:24.460035 CA_MCKIO = 600
3849 23:45:24.460086 MCKIO_SEMI = 0
3850 23:45:24.460137 PLL_FREQ = 2288
3851 23:45:24.460187 DQ_UI_PI_RATIO = 32
3852 23:45:24.460237 CA_UI_PI_RATIO = 0
3853 23:45:24.460288 ===================================
3854 23:45:24.460339 ===================================
3855 23:45:24.460389 memory_type:LPDDR4
3856 23:45:24.460440 GP_NUM : 10
3857 23:45:24.460490 SRAM_EN : 1
3858 23:45:24.460542 MD32_EN : 0
3859 23:45:24.460593 ===================================
3860 23:45:24.460644 [ANA_INIT] >>>>>>>>>>>>>>
3861 23:45:24.460703 <<<<<< [CONFIGURE PHASE]: ANA_TX
3862 23:45:24.460755 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3863 23:45:24.460806 ===================================
3864 23:45:24.460857 data_rate = 1200,PCW = 0X5800
3865 23:45:24.460907 ===================================
3866 23:45:24.460958 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3867 23:45:24.461009 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3868 23:45:24.461060 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3869 23:45:24.461122 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3870 23:45:24.461188 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3871 23:45:24.461240 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3872 23:45:24.461291 [ANA_INIT] flow start
3873 23:45:24.461342 [ANA_INIT] PLL >>>>>>>>
3874 23:45:24.461392 [ANA_INIT] PLL <<<<<<<<
3875 23:45:24.461442 [ANA_INIT] MIDPI >>>>>>>>
3876 23:45:24.461493 [ANA_INIT] MIDPI <<<<<<<<
3877 23:45:24.461544 [ANA_INIT] DLL >>>>>>>>
3878 23:45:24.461608 [ANA_INIT] flow end
3879 23:45:24.465062 ============ LP4 DIFF to SE enter ============
3880 23:45:24.467601 ============ LP4 DIFF to SE exit ============
3881 23:45:24.470817 [ANA_INIT] <<<<<<<<<<<<<
3882 23:45:24.473850 [Flow] Enable top DCM control >>>>>
3883 23:45:24.477648 [Flow] Enable top DCM control <<<<<
3884 23:45:24.480756 Enable DLL master slave shuffle
3885 23:45:24.487567 ==============================================================
3886 23:45:24.487648 Gating Mode config
3887 23:45:24.494082 ==============================================================
3888 23:45:24.497563 Config description:
3889 23:45:24.504065 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3890 23:45:24.510721 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3891 23:45:24.517464 SELPH_MODE 0: By rank 1: By Phase
3892 23:45:24.523923 ==============================================================
3893 23:45:24.524125 GAT_TRACK_EN = 1
3894 23:45:24.527235 RX_GATING_MODE = 2
3895 23:45:24.530375 RX_GATING_TRACK_MODE = 2
3896 23:45:24.533894 SELPH_MODE = 1
3897 23:45:24.537470 PICG_EARLY_EN = 1
3898 23:45:24.540520 VALID_LAT_VALUE = 1
3899 23:45:24.547349 ==============================================================
3900 23:45:24.551126 Enter into Gating configuration >>>>
3901 23:45:24.554242 Exit from Gating configuration <<<<
3902 23:45:24.557627 Enter into DVFS_PRE_config >>>>>
3903 23:45:24.567206 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3904 23:45:24.570693 Exit from DVFS_PRE_config <<<<<
3905 23:45:24.573641 Enter into PICG configuration >>>>
3906 23:45:24.577031 Exit from PICG configuration <<<<
3907 23:45:24.580363 [RX_INPUT] configuration >>>>>
3908 23:45:24.583513 [RX_INPUT] configuration <<<<<
3909 23:45:24.586792 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3910 23:45:24.594085 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3911 23:45:24.600219 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3912 23:45:24.606870 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3913 23:45:24.610311 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3914 23:45:24.616691 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3915 23:45:24.620154 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3916 23:45:24.626851 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3917 23:45:24.629706 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3918 23:45:24.633196 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3919 23:45:24.636572 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3920 23:45:24.643101 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3921 23:45:24.646902 ===================================
3922 23:45:24.649761 LPDDR4 DRAM CONFIGURATION
3923 23:45:24.650269 ===================================
3924 23:45:24.653408 EX_ROW_EN[0] = 0x0
3925 23:45:24.656220 EX_ROW_EN[1] = 0x0
3926 23:45:24.656678 LP4Y_EN = 0x0
3927 23:45:24.660442 WORK_FSP = 0x0
3928 23:45:24.661008 WL = 0x2
3929 23:45:24.663006 RL = 0x2
3930 23:45:24.663463 BL = 0x2
3931 23:45:24.666539 RPST = 0x0
3932 23:45:24.667149 RD_PRE = 0x0
3933 23:45:24.669955 WR_PRE = 0x1
3934 23:45:24.670590 WR_PST = 0x0
3935 23:45:24.672537 DBI_WR = 0x0
3936 23:45:24.672997 DBI_RD = 0x0
3937 23:45:24.676331 OTF = 0x1
3938 23:45:24.679407 ===================================
3939 23:45:24.682720 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3940 23:45:24.686050 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3941 23:45:24.692647 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3942 23:45:24.695891 ===================================
3943 23:45:24.698891 LPDDR4 DRAM CONFIGURATION
3944 23:45:24.702081 ===================================
3945 23:45:24.702853 EX_ROW_EN[0] = 0x10
3946 23:45:24.705737 EX_ROW_EN[1] = 0x0
3947 23:45:24.706297 LP4Y_EN = 0x0
3948 23:45:24.708651 WORK_FSP = 0x0
3949 23:45:24.709108 WL = 0x2
3950 23:45:24.712332 RL = 0x2
3951 23:45:24.712787 BL = 0x2
3952 23:45:24.715778 RPST = 0x0
3953 23:45:24.716234 RD_PRE = 0x0
3954 23:45:24.718762 WR_PRE = 0x1
3955 23:45:24.719220 WR_PST = 0x0
3956 23:45:24.721840 DBI_WR = 0x0
3957 23:45:24.725397 DBI_RD = 0x0
3958 23:45:24.725856 OTF = 0x1
3959 23:45:24.728487 ===================================
3960 23:45:24.735211 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3961 23:45:24.738488 nWR fixed to 30
3962 23:45:24.742366 [ModeRegInit_LP4] CH0 RK0
3963 23:45:24.742790 [ModeRegInit_LP4] CH0 RK1
3964 23:45:24.745653 [ModeRegInit_LP4] CH1 RK0
3965 23:45:24.748801 [ModeRegInit_LP4] CH1 RK1
3966 23:45:24.749263 match AC timing 17
3967 23:45:24.755657 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3968 23:45:24.759282 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3969 23:45:24.762268 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3970 23:45:24.768725 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3971 23:45:24.772006 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3972 23:45:24.772472 ==
3973 23:45:24.774800 Dram Type= 6, Freq= 0, CH_0, rank 0
3974 23:45:24.778454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3975 23:45:24.778923 ==
3976 23:45:24.785019 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3977 23:45:24.791437 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3978 23:45:24.794951 [CA 0] Center 36 (6~66) winsize 61
3979 23:45:24.798361 [CA 1] Center 36 (6~66) winsize 61
3980 23:45:24.801761 [CA 2] Center 34 (4~65) winsize 62
3981 23:45:24.804560 [CA 3] Center 34 (4~65) winsize 62
3982 23:45:24.807873 [CA 4] Center 33 (3~64) winsize 62
3983 23:45:24.811723 [CA 5] Center 33 (3~64) winsize 62
3984 23:45:24.812237
3985 23:45:24.814519 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3986 23:45:24.814933
3987 23:45:24.817961 [CATrainingPosCal] consider 1 rank data
3988 23:45:24.821358 u2DelayCellTimex100 = 270/100 ps
3989 23:45:24.824474 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3990 23:45:24.827735 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3991 23:45:24.831184 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3992 23:45:24.834692 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3993 23:45:24.841411 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3994 23:45:24.844201 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3995 23:45:24.844624
3996 23:45:24.847596 CA PerBit enable=1, Macro0, CA PI delay=33
3997 23:45:24.848017
3998 23:45:24.851070 [CBTSetCACLKResult] CA Dly = 33
3999 23:45:24.851492 CS Dly: 4 (0~35)
4000 23:45:24.851834 ==
4001 23:45:24.854229 Dram Type= 6, Freq= 0, CH_0, rank 1
4002 23:45:24.861576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4003 23:45:24.862024 ==
4004 23:45:24.864383 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4005 23:45:24.870691 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4006 23:45:24.874360 [CA 0] Center 35 (5~66) winsize 62
4007 23:45:24.877700 [CA 1] Center 36 (6~66) winsize 61
4008 23:45:24.881404 [CA 2] Center 34 (3~65) winsize 63
4009 23:45:24.884021 [CA 3] Center 33 (3~64) winsize 62
4010 23:45:24.887186 [CA 4] Center 33 (3~64) winsize 62
4011 23:45:24.891042 [CA 5] Center 33 (3~64) winsize 62
4012 23:45:24.891459
4013 23:45:24.893616 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4014 23:45:24.894028
4015 23:45:24.896986 [CATrainingPosCal] consider 2 rank data
4016 23:45:24.900760 u2DelayCellTimex100 = 270/100 ps
4017 23:45:24.904405 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4018 23:45:24.910339 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4019 23:45:24.914429 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4020 23:45:24.917650 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4021 23:45:24.920787 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4022 23:45:24.924117 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4023 23:45:24.924673
4024 23:45:24.926902 CA PerBit enable=1, Macro0, CA PI delay=33
4025 23:45:24.927418
4026 23:45:24.929962 [CBTSetCACLKResult] CA Dly = 33
4027 23:45:24.933372 CS Dly: 5 (0~37)
4028 23:45:24.933835
4029 23:45:24.937051 ----->DramcWriteLeveling(PI) begin...
4030 23:45:24.937619 ==
4031 23:45:24.940013 Dram Type= 6, Freq= 0, CH_0, rank 0
4032 23:45:24.943553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4033 23:45:24.944012 ==
4034 23:45:24.946727 Write leveling (Byte 0): 34 => 34
4035 23:45:24.950041 Write leveling (Byte 1): 30 => 30
4036 23:45:24.953490 DramcWriteLeveling(PI) end<-----
4037 23:45:24.954043
4038 23:45:24.954452 ==
4039 23:45:24.957004 Dram Type= 6, Freq= 0, CH_0, rank 0
4040 23:45:24.960236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4041 23:45:24.960811 ==
4042 23:45:24.963330 [Gating] SW mode calibration
4043 23:45:24.970145 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4044 23:45:24.976689 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4045 23:45:24.980122 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4046 23:45:24.983205 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4047 23:45:24.989679 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4048 23:45:24.993271 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4049 23:45:24.996431 0 9 16 | B1->B0 | 3131 2929 | 1 0 | (0 0) (0 0)
4050 23:45:25.002802 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4051 23:45:25.005958 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4052 23:45:25.009692 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4053 23:45:25.016318 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4054 23:45:25.019663 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4055 23:45:25.022663 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4056 23:45:25.029099 0 10 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4057 23:45:25.032966 0 10 16 | B1->B0 | 3636 4545 | 0 0 | (0 0) (0 0)
4058 23:45:25.036355 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4059 23:45:25.042435 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4060 23:45:25.045730 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4061 23:45:25.049072 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4062 23:45:25.056129 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4063 23:45:25.058958 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4064 23:45:25.062477 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4065 23:45:25.069027 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4066 23:45:25.072293 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4067 23:45:25.075512 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 23:45:25.081768 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 23:45:25.085678 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 23:45:25.089095 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 23:45:25.095168 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 23:45:25.098850 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 23:45:25.102478 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 23:45:25.108786 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 23:45:25.111853 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 23:45:25.115238 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4077 23:45:25.121868 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4078 23:45:25.125140 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4079 23:45:25.128339 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4080 23:45:25.134832 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4081 23:45:25.138231 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4082 23:45:25.141147 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4083 23:45:25.144636 Total UI for P1: 0, mck2ui 16
4084 23:45:25.148085 best dqsien dly found for B0: ( 0, 13, 14)
4085 23:45:25.151003 Total UI for P1: 0, mck2ui 16
4086 23:45:25.154243 best dqsien dly found for B1: ( 0, 13, 18)
4087 23:45:25.157845 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4088 23:45:25.163934 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4089 23:45:25.164477
4090 23:45:25.167553 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4091 23:45:25.171231 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4092 23:45:25.173923 [Gating] SW calibration Done
4093 23:45:25.174422 ==
4094 23:45:25.177870 Dram Type= 6, Freq= 0, CH_0, rank 0
4095 23:45:25.180766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4096 23:45:25.181324 ==
4097 23:45:25.184155 RX Vref Scan: 0
4098 23:45:25.184942
4099 23:45:25.185369 RX Vref 0 -> 0, step: 1
4100 23:45:25.185718
4101 23:45:25.187309 RX Delay -230 -> 252, step: 16
4102 23:45:25.190485 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4103 23:45:25.197488 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4104 23:45:25.200589 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4105 23:45:25.203555 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4106 23:45:25.206954 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4107 23:45:25.213862 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4108 23:45:25.216939 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4109 23:45:25.220645 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4110 23:45:25.223326 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4111 23:45:25.229714 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4112 23:45:25.233124 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4113 23:45:25.236697 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4114 23:45:25.240039 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4115 23:45:25.246681 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4116 23:45:25.249767 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4117 23:45:25.252875 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4118 23:45:25.253411 ==
4119 23:45:25.256566 Dram Type= 6, Freq= 0, CH_0, rank 0
4120 23:45:25.259657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4121 23:45:25.260234 ==
4122 23:45:25.262802 DQS Delay:
4123 23:45:25.263261 DQS0 = 0, DQS1 = 0
4124 23:45:25.266710 DQM Delay:
4125 23:45:25.267264 DQM0 = 43, DQM1 = 33
4126 23:45:25.269696 DQ Delay:
4127 23:45:25.270305 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4128 23:45:25.273002 DQ4 =41, DQ5 =41, DQ6 =49, DQ7 =49
4129 23:45:25.275796 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4130 23:45:25.279589 DQ12 =41, DQ13 =33, DQ14 =49, DQ15 =41
4131 23:45:25.280141
4132 23:45:25.283442
4133 23:45:25.283992 ==
4134 23:45:25.286291 Dram Type= 6, Freq= 0, CH_0, rank 0
4135 23:45:25.289685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4136 23:45:25.290303 ==
4137 23:45:25.290682
4138 23:45:25.291022
4139 23:45:25.292787 TX Vref Scan disable
4140 23:45:25.293343 == TX Byte 0 ==
4141 23:45:25.299636 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4142 23:45:25.302415 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4143 23:45:25.302876 == TX Byte 1 ==
4144 23:45:25.309580 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4145 23:45:25.312610 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4146 23:45:25.313072 ==
4147 23:45:25.315721 Dram Type= 6, Freq= 0, CH_0, rank 0
4148 23:45:25.319052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4149 23:45:25.319610 ==
4150 23:45:25.319977
4151 23:45:25.320311
4152 23:45:25.322392 TX Vref Scan disable
4153 23:45:25.325540 == TX Byte 0 ==
4154 23:45:25.329189 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4155 23:45:25.335406 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4156 23:45:25.335984 == TX Byte 1 ==
4157 23:45:25.338554 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4158 23:45:25.345643 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4159 23:45:25.346291
4160 23:45:25.346673 [DATLAT]
4161 23:45:25.347011 Freq=600, CH0 RK0
4162 23:45:25.347343
4163 23:45:25.348545 DATLAT Default: 0x9
4164 23:45:25.351566 0, 0xFFFF, sum = 0
4165 23:45:25.351991 1, 0xFFFF, sum = 0
4166 23:45:25.355125 2, 0xFFFF, sum = 0
4167 23:45:25.355622 3, 0xFFFF, sum = 0
4168 23:45:25.358436 4, 0xFFFF, sum = 0
4169 23:45:25.358861 5, 0xFFFF, sum = 0
4170 23:45:25.361676 6, 0xFFFF, sum = 0
4171 23:45:25.362233 7, 0xFFFF, sum = 0
4172 23:45:25.365004 8, 0x0, sum = 1
4173 23:45:25.365430 9, 0x0, sum = 2
4174 23:45:25.368431 10, 0x0, sum = 3
4175 23:45:25.368971 11, 0x0, sum = 4
4176 23:45:25.369313 best_step = 9
4177 23:45:25.369617
4178 23:45:25.371365 ==
4179 23:45:25.375369 Dram Type= 6, Freq= 0, CH_0, rank 0
4180 23:45:25.380959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4181 23:45:25.381397 ==
4182 23:45:25.381728 RX Vref Scan: 1
4183 23:45:25.382035
4184 23:45:25.382703 RX Vref 0 -> 0, step: 1
4185 23:45:25.383027
4186 23:45:25.384388 RX Delay -195 -> 252, step: 8
4187 23:45:25.384808
4188 23:45:25.388068 Set Vref, RX VrefLevel [Byte0]: 57
4189 23:45:25.391121 [Byte1]: 50
4190 23:45:25.394715
4191 23:45:25.395375 Final RX Vref Byte 0 = 57 to rank0
4192 23:45:25.398070 Final RX Vref Byte 1 = 50 to rank0
4193 23:45:25.401346 Final RX Vref Byte 0 = 57 to rank1
4194 23:45:25.404550 Final RX Vref Byte 1 = 50 to rank1==
4195 23:45:25.407572 Dram Type= 6, Freq= 0, CH_0, rank 0
4196 23:45:25.414239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4197 23:45:25.414984 ==
4198 23:45:25.415490 DQS Delay:
4199 23:45:25.417917 DQS0 = 0, DQS1 = 0
4200 23:45:25.418381 DQM Delay:
4201 23:45:25.418717 DQM0 = 44, DQM1 = 32
4202 23:45:25.421609 DQ Delay:
4203 23:45:25.424211 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4204 23:45:25.427265 DQ4 =44, DQ5 =36, DQ6 =52, DQ7 =52
4205 23:45:25.430867 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =24
4206 23:45:25.434038 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =40
4207 23:45:25.434478
4208 23:45:25.434815
4209 23:45:25.440894 [DQSOSCAuto] RK0, (LSB)MR18= 0x633a, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 391 ps
4210 23:45:25.443670 CH0 RK0: MR19=808, MR18=633A
4211 23:45:25.450510 CH0_RK0: MR19=0x808, MR18=0x633A, DQSOSC=391, MR23=63, INC=171, DEC=114
4212 23:45:25.450944
4213 23:45:25.453946 ----->DramcWriteLeveling(PI) begin...
4214 23:45:25.454516 ==
4215 23:45:25.457303 Dram Type= 6, Freq= 0, CH_0, rank 1
4216 23:45:25.460297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4217 23:45:25.460718 ==
4218 23:45:25.463593 Write leveling (Byte 0): 33 => 33
4219 23:45:25.466938 Write leveling (Byte 1): 33 => 33
4220 23:45:25.470480 DramcWriteLeveling(PI) end<-----
4221 23:45:25.470935
4222 23:45:25.471296 ==
4223 23:45:25.473656 Dram Type= 6, Freq= 0, CH_0, rank 1
4224 23:45:25.477036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4225 23:45:25.480178 ==
4226 23:45:25.480731 [Gating] SW mode calibration
4227 23:45:25.490020 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4228 23:45:25.494091 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4229 23:45:25.497249 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4230 23:45:25.503213 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4231 23:45:25.506789 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4232 23:45:25.509554 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 1)
4233 23:45:25.516084 0 9 16 | B1->B0 | 2f2f 2828 | 0 0 | (0 0) (0 0)
4234 23:45:25.519737 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4235 23:45:25.522702 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4236 23:45:25.529661 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4237 23:45:25.532481 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4238 23:45:25.536104 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4239 23:45:25.542329 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4240 23:45:25.545725 0 10 12 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4241 23:45:25.548914 0 10 16 | B1->B0 | 3a3a 4040 | 0 0 | (0 0) (0 0)
4242 23:45:25.555579 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4243 23:45:25.559115 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4244 23:45:25.562209 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4245 23:45:25.568914 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4246 23:45:25.572450 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4247 23:45:25.575732 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4248 23:45:25.582079 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4249 23:45:25.585566 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4250 23:45:25.588950 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 23:45:25.595819 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 23:45:25.598673 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 23:45:25.601957 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 23:45:25.609475 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 23:45:25.611987 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 23:45:25.615058 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 23:45:25.622007 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 23:45:25.624832 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 23:45:25.628145 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 23:45:25.635143 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 23:45:25.638054 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 23:45:25.641340 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 23:45:25.648136 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 23:45:25.651824 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4265 23:45:25.654646 Total UI for P1: 0, mck2ui 16
4266 23:45:25.658070 best dqsien dly found for B0: ( 0, 13, 10)
4267 23:45:25.660916 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4268 23:45:25.664957 Total UI for P1: 0, mck2ui 16
4269 23:45:25.667769 best dqsien dly found for B1: ( 0, 13, 12)
4270 23:45:25.670951 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4271 23:45:25.677886 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4272 23:45:25.678454
4273 23:45:25.681099 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4274 23:45:25.684641 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4275 23:45:25.688030 [Gating] SW calibration Done
4276 23:45:25.688549 ==
4277 23:45:25.691102 Dram Type= 6, Freq= 0, CH_0, rank 1
4278 23:45:25.694813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4279 23:45:25.695229 ==
4280 23:45:25.697386 RX Vref Scan: 0
4281 23:45:25.697796
4282 23:45:25.698122 RX Vref 0 -> 0, step: 1
4283 23:45:25.698455
4284 23:45:25.700977 RX Delay -230 -> 252, step: 16
4285 23:45:25.703942 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4286 23:45:25.710776 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4287 23:45:25.713966 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4288 23:45:25.717056 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4289 23:45:25.720534 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4290 23:45:25.727064 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4291 23:45:25.730518 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4292 23:45:25.733773 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4293 23:45:25.737266 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4294 23:45:25.743770 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4295 23:45:25.746609 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4296 23:45:25.750739 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4297 23:45:25.753533 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4298 23:45:25.760754 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4299 23:45:25.763310 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4300 23:45:25.766558 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4301 23:45:25.767020 ==
4302 23:45:25.769694 Dram Type= 6, Freq= 0, CH_0, rank 1
4303 23:45:25.773029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4304 23:45:25.776640 ==
4305 23:45:25.777269 DQS Delay:
4306 23:45:25.777647 DQS0 = 0, DQS1 = 0
4307 23:45:25.779789 DQM Delay:
4308 23:45:25.780343 DQM0 = 44, DQM1 = 38
4309 23:45:25.783037 DQ Delay:
4310 23:45:25.783497 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =41
4311 23:45:25.786369 DQ4 =41, DQ5 =41, DQ6 =49, DQ7 =49
4312 23:45:25.789627 DQ8 =33, DQ9 =17, DQ10 =41, DQ11 =33
4313 23:45:25.793216 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =41
4314 23:45:25.794058
4315 23:45:25.796462
4316 23:45:25.797017 ==
4317 23:45:25.799291 Dram Type= 6, Freq= 0, CH_0, rank 1
4318 23:45:25.802955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4319 23:45:25.803413 ==
4320 23:45:25.803777
4321 23:45:25.804109
4322 23:45:25.806494 TX Vref Scan disable
4323 23:45:25.806905 == TX Byte 0 ==
4324 23:45:25.813025 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4325 23:45:25.816029 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4326 23:45:25.816566 == TX Byte 1 ==
4327 23:45:25.822773 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4328 23:45:25.825742 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4329 23:45:25.826159 ==
4330 23:45:25.828980 Dram Type= 6, Freq= 0, CH_0, rank 1
4331 23:45:25.832058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4332 23:45:25.832475 ==
4333 23:45:25.832813
4334 23:45:25.835289
4335 23:45:25.835702 TX Vref Scan disable
4336 23:45:25.838952 == TX Byte 0 ==
4337 23:45:25.841905 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4338 23:45:25.849042 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4339 23:45:25.849459 == TX Byte 1 ==
4340 23:45:25.851939 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4341 23:45:25.858769 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4342 23:45:25.859360
4343 23:45:25.859803 [DATLAT]
4344 23:45:25.860118 Freq=600, CH0 RK1
4345 23:45:25.860413
4346 23:45:25.861836 DATLAT Default: 0x9
4347 23:45:25.866328 0, 0xFFFF, sum = 0
4348 23:45:25.866851 1, 0xFFFF, sum = 0
4349 23:45:25.868348 2, 0xFFFF, sum = 0
4350 23:45:25.868802 3, 0xFFFF, sum = 0
4351 23:45:25.871589 4, 0xFFFF, sum = 0
4352 23:45:25.872012 5, 0xFFFF, sum = 0
4353 23:45:25.875196 6, 0xFFFF, sum = 0
4354 23:45:25.875713 7, 0xFFFF, sum = 0
4355 23:45:25.878471 8, 0x0, sum = 1
4356 23:45:25.878997 9, 0x0, sum = 2
4357 23:45:25.881753 10, 0x0, sum = 3
4358 23:45:25.882293 11, 0x0, sum = 4
4359 23:45:25.882624 best_step = 9
4360 23:45:25.882920
4361 23:45:25.885398 ==
4362 23:45:25.885813 Dram Type= 6, Freq= 0, CH_0, rank 1
4363 23:45:25.892181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4364 23:45:25.892819 ==
4365 23:45:25.893272 RX Vref Scan: 0
4366 23:45:25.893591
4367 23:45:25.894756 RX Vref 0 -> 0, step: 1
4368 23:45:25.895169
4369 23:45:25.898370 RX Delay -195 -> 252, step: 8
4370 23:45:25.904946 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4371 23:45:25.908031 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4372 23:45:25.911584 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4373 23:45:25.915101 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4374 23:45:25.917991 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4375 23:45:25.924512 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4376 23:45:25.928071 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4377 23:45:25.931538 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4378 23:45:25.935270 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4379 23:45:25.941739 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4380 23:45:25.944557 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4381 23:45:25.947995 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4382 23:45:25.951165 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4383 23:45:25.957747 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4384 23:45:25.961247 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4385 23:45:25.964602 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4386 23:45:25.965147 ==
4387 23:45:25.967623 Dram Type= 6, Freq= 0, CH_0, rank 1
4388 23:45:25.971323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4389 23:45:25.974133 ==
4390 23:45:25.974787 DQS Delay:
4391 23:45:25.975122 DQS0 = 0, DQS1 = 0
4392 23:45:25.977679 DQM Delay:
4393 23:45:25.978096 DQM0 = 41, DQM1 = 36
4394 23:45:25.981187 DQ Delay:
4395 23:45:25.981709 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =40
4396 23:45:25.984136 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4397 23:45:25.987853 DQ8 =28, DQ9 =20, DQ10 =40, DQ11 =28
4398 23:45:25.990682 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =44
4399 23:45:25.991098
4400 23:45:25.994469
4401 23:45:26.000701 [DQSOSCAuto] RK1, (LSB)MR18= 0x6115, (MSB)MR19= 0x808, tDQSOscB0 = 405 ps tDQSOscB1 = 391 ps
4402 23:45:26.004013 CH0 RK1: MR19=808, MR18=6115
4403 23:45:26.010659 CH0_RK1: MR19=0x808, MR18=0x6115, DQSOSC=391, MR23=63, INC=171, DEC=114
4404 23:45:26.014132 [RxdqsGatingPostProcess] freq 600
4405 23:45:26.017162 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4406 23:45:26.020423 Pre-setting of DQS Precalculation
4407 23:45:26.027092 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4408 23:45:26.027511 ==
4409 23:45:26.030432 Dram Type= 6, Freq= 0, CH_1, rank 0
4410 23:45:26.033497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4411 23:45:26.033917 ==
4412 23:45:26.040880 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4413 23:45:26.043532 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4414 23:45:26.048286 [CA 0] Center 35 (5~66) winsize 62
4415 23:45:26.051036 [CA 1] Center 35 (5~66) winsize 62
4416 23:45:26.055107 [CA 2] Center 34 (4~65) winsize 62
4417 23:45:26.057748 [CA 3] Center 33 (3~64) winsize 62
4418 23:45:26.061205 [CA 4] Center 34 (4~65) winsize 62
4419 23:45:26.064394 [CA 5] Center 33 (3~64) winsize 62
4420 23:45:26.064908
4421 23:45:26.067849 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4422 23:45:26.068261
4423 23:45:26.070961 [CATrainingPosCal] consider 1 rank data
4424 23:45:26.074398 u2DelayCellTimex100 = 270/100 ps
4425 23:45:26.077546 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4426 23:45:26.084472 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4427 23:45:26.087570 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4428 23:45:26.090728 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4429 23:45:26.094043 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4430 23:45:26.097084 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4431 23:45:26.097512
4432 23:45:26.100483 CA PerBit enable=1, Macro0, CA PI delay=33
4433 23:45:26.100918
4434 23:45:26.104123 [CBTSetCACLKResult] CA Dly = 33
4435 23:45:26.107215 CS Dly: 4 (0~35)
4436 23:45:26.107643 ==
4437 23:45:26.111060 Dram Type= 6, Freq= 0, CH_1, rank 1
4438 23:45:26.114130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4439 23:45:26.114694 ==
4440 23:45:26.120377 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4441 23:45:26.123466 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4442 23:45:26.127981 [CA 0] Center 35 (5~66) winsize 62
4443 23:45:26.131108 [CA 1] Center 36 (6~66) winsize 61
4444 23:45:26.134986 [CA 2] Center 34 (4~65) winsize 62
4445 23:45:26.137763 [CA 3] Center 34 (3~65) winsize 63
4446 23:45:26.141151 [CA 4] Center 34 (4~65) winsize 62
4447 23:45:26.144625 [CA 5] Center 34 (3~65) winsize 63
4448 23:45:26.145040
4449 23:45:26.147494 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4450 23:45:26.147906
4451 23:45:26.151055 [CATrainingPosCal] consider 2 rank data
4452 23:45:26.154214 u2DelayCellTimex100 = 270/100 ps
4453 23:45:26.157648 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4454 23:45:26.164323 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4455 23:45:26.167751 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4456 23:45:26.170758 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4457 23:45:26.173805 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4458 23:45:26.177814 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4459 23:45:26.178268
4460 23:45:26.181029 CA PerBit enable=1, Macro0, CA PI delay=33
4461 23:45:26.181579
4462 23:45:26.184319 [CBTSetCACLKResult] CA Dly = 33
4463 23:45:26.187168 CS Dly: 5 (0~37)
4464 23:45:26.187586
4465 23:45:26.190675 ----->DramcWriteLeveling(PI) begin...
4466 23:45:26.191099 ==
4467 23:45:26.194265 Dram Type= 6, Freq= 0, CH_1, rank 0
4468 23:45:26.197390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4469 23:45:26.197915 ==
4470 23:45:26.200938 Write leveling (Byte 0): 28 => 28
4471 23:45:26.203819 Write leveling (Byte 1): 30 => 30
4472 23:45:26.206918 DramcWriteLeveling(PI) end<-----
4473 23:45:26.207448
4474 23:45:26.207787 ==
4475 23:45:26.210708 Dram Type= 6, Freq= 0, CH_1, rank 0
4476 23:45:26.213929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4477 23:45:26.214380 ==
4478 23:45:26.216732 [Gating] SW mode calibration
4479 23:45:26.223803 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4480 23:45:26.229879 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4481 23:45:26.233778 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4482 23:45:26.236859 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4483 23:45:26.243371 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4484 23:45:26.246803 0 9 12 | B1->B0 | 2f2f 2f2f | 1 1 | (1 0) (1 0)
4485 23:45:26.250424 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4486 23:45:26.257136 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4487 23:45:26.259781 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4488 23:45:26.263449 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4489 23:45:26.269824 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4490 23:45:26.273412 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4491 23:45:26.276591 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4492 23:45:26.283115 0 10 12 | B1->B0 | 2a2a 3636 | 0 0 | (0 0) (1 1)
4493 23:45:26.286805 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4494 23:45:26.289522 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4495 23:45:26.296573 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4496 23:45:26.300105 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4497 23:45:26.302919 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4498 23:45:26.310067 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4499 23:45:26.312805 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4500 23:45:26.316263 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4501 23:45:26.322562 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 23:45:26.326042 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 23:45:26.329125 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 23:45:26.336159 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 23:45:26.339534 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 23:45:26.342695 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 23:45:26.349172 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 23:45:26.352589 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 23:45:26.355526 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 23:45:26.362135 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4511 23:45:26.365771 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4512 23:45:26.369178 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4513 23:45:26.375657 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4514 23:45:26.378789 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4515 23:45:26.382539 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4516 23:45:26.388891 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4517 23:45:26.391732 Total UI for P1: 0, mck2ui 16
4518 23:45:26.395215 best dqsien dly found for B0: ( 0, 13, 8)
4519 23:45:26.398475 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4520 23:45:26.402001 Total UI for P1: 0, mck2ui 16
4521 23:45:26.405105 best dqsien dly found for B1: ( 0, 13, 12)
4522 23:45:26.408613 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4523 23:45:26.411846 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4524 23:45:26.412363
4525 23:45:26.415269 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4526 23:45:26.418669 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4527 23:45:26.421802 [Gating] SW calibration Done
4528 23:45:26.422362 ==
4529 23:45:26.424836 Dram Type= 6, Freq= 0, CH_1, rank 0
4530 23:45:26.431874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4531 23:45:26.432469 ==
4532 23:45:26.432986 RX Vref Scan: 0
4533 23:45:26.433395
4534 23:45:26.434957 RX Vref 0 -> 0, step: 1
4535 23:45:26.435418
4536 23:45:26.437989 RX Delay -230 -> 252, step: 16
4537 23:45:26.441255 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4538 23:45:26.444591 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4539 23:45:26.448029 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4540 23:45:26.454433 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4541 23:45:26.458218 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4542 23:45:26.461277 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4543 23:45:26.464713 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4544 23:45:26.470938 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4545 23:45:26.474608 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4546 23:45:26.477581 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4547 23:45:26.481345 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4548 23:45:26.484378 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4549 23:45:26.490840 iDelay=218, Bit 12, Center 41 (-134 ~ 217) 352
4550 23:45:26.494216 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4551 23:45:26.497403 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4552 23:45:26.504148 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4553 23:45:26.504667 ==
4554 23:45:26.507565 Dram Type= 6, Freq= 0, CH_1, rank 0
4555 23:45:26.510608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4556 23:45:26.511122 ==
4557 23:45:26.511453 DQS Delay:
4558 23:45:26.513888 DQS0 = 0, DQS1 = 0
4559 23:45:26.514450 DQM Delay:
4560 23:45:26.517646 DQM0 = 45, DQM1 = 36
4561 23:45:26.518157 DQ Delay:
4562 23:45:26.521262 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4563 23:45:26.523914 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4564 23:45:26.527017 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4565 23:45:26.530902 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =49
4566 23:45:26.531320
4567 23:45:26.531652
4568 23:45:26.531958 ==
4569 23:45:26.533854 Dram Type= 6, Freq= 0, CH_1, rank 0
4570 23:45:26.537394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4571 23:45:26.537918 ==
4572 23:45:26.538311
4573 23:45:26.540534
4574 23:45:26.540945 TX Vref Scan disable
4575 23:45:26.543623 == TX Byte 0 ==
4576 23:45:26.547164 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4577 23:45:26.550337 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4578 23:45:26.553723 == TX Byte 1 ==
4579 23:45:26.556960 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4580 23:45:26.560197 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4581 23:45:26.560657 ==
4582 23:45:26.563654 Dram Type= 6, Freq= 0, CH_1, rank 0
4583 23:45:26.570473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4584 23:45:26.570938 ==
4585 23:45:26.571318
4586 23:45:26.571623
4587 23:45:26.573156 TX Vref Scan disable
4588 23:45:26.573584 == TX Byte 0 ==
4589 23:45:26.579922 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4590 23:45:26.583050 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4591 23:45:26.583500 == TX Byte 1 ==
4592 23:45:26.590300 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4593 23:45:26.593213 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4594 23:45:26.593729
4595 23:45:26.594062 [DATLAT]
4596 23:45:26.596675 Freq=600, CH1 RK0
4597 23:45:26.597188
4598 23:45:26.597522 DATLAT Default: 0x9
4599 23:45:26.599740 0, 0xFFFF, sum = 0
4600 23:45:26.600274 1, 0xFFFF, sum = 0
4601 23:45:26.603309 2, 0xFFFF, sum = 0
4602 23:45:26.606327 3, 0xFFFF, sum = 0
4603 23:45:26.606840 4, 0xFFFF, sum = 0
4604 23:45:26.609774 5, 0xFFFF, sum = 0
4605 23:45:26.610347 6, 0xFFFF, sum = 0
4606 23:45:26.613480 7, 0xFFFF, sum = 0
4607 23:45:26.613994 8, 0x0, sum = 1
4608 23:45:26.616172 9, 0x0, sum = 2
4609 23:45:26.616763 10, 0x0, sum = 3
4610 23:45:26.617117 11, 0x0, sum = 4
4611 23:45:26.618998 best_step = 9
4612 23:45:26.619458
4613 23:45:26.619808 ==
4614 23:45:26.622284 Dram Type= 6, Freq= 0, CH_1, rank 0
4615 23:45:26.625867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4616 23:45:26.626325 ==
4617 23:45:26.628904 RX Vref Scan: 1
4618 23:45:26.629350
4619 23:45:26.632854 RX Vref 0 -> 0, step: 1
4620 23:45:26.633426
4621 23:45:26.633969 RX Delay -179 -> 252, step: 8
4622 23:45:26.634481
4623 23:45:26.636985 Set Vref, RX VrefLevel [Byte0]: 49
4624 23:45:26.638847 [Byte1]: 54
4625 23:45:26.643565
4626 23:45:26.644079 Final RX Vref Byte 0 = 49 to rank0
4627 23:45:26.647056 Final RX Vref Byte 1 = 54 to rank0
4628 23:45:26.650288 Final RX Vref Byte 0 = 49 to rank1
4629 23:45:26.653249 Final RX Vref Byte 1 = 54 to rank1==
4630 23:45:26.657089 Dram Type= 6, Freq= 0, CH_1, rank 0
4631 23:45:26.663243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4632 23:45:26.663683 ==
4633 23:45:26.664057 DQS Delay:
4634 23:45:26.666499 DQS0 = 0, DQS1 = 0
4635 23:45:26.666913 DQM Delay:
4636 23:45:26.667238 DQM0 = 48, DQM1 = 37
4637 23:45:26.670149 DQ Delay:
4638 23:45:26.673175 DQ0 =56, DQ1 =44, DQ2 =40, DQ3 =44
4639 23:45:26.676741 DQ4 =44, DQ5 =56, DQ6 =56, DQ7 =44
4640 23:45:26.679495 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =24
4641 23:45:26.683144 DQ12 =44, DQ13 =44, DQ14 =48, DQ15 =48
4642 23:45:26.683661
4643 23:45:26.683992
4644 23:45:26.689968 [DQSOSCAuto] RK0, (LSB)MR18= 0x4b30, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 395 ps
4645 23:45:26.693349 CH1 RK0: MR19=808, MR18=4B30
4646 23:45:26.699508 CH1_RK0: MR19=0x808, MR18=0x4B30, DQSOSC=395, MR23=63, INC=168, DEC=112
4647 23:45:26.699927
4648 23:45:26.702649 ----->DramcWriteLeveling(PI) begin...
4649 23:45:26.703068 ==
4650 23:45:26.705942 Dram Type= 6, Freq= 0, CH_1, rank 1
4651 23:45:26.709549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4652 23:45:26.710107 ==
4653 23:45:26.713089 Write leveling (Byte 0): 30 => 30
4654 23:45:26.715756 Write leveling (Byte 1): 30 => 30
4655 23:45:26.719136 DramcWriteLeveling(PI) end<-----
4656 23:45:26.719547
4657 23:45:26.719878 ==
4658 23:45:26.722125 Dram Type= 6, Freq= 0, CH_1, rank 1
4659 23:45:26.729027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4660 23:45:26.729582 ==
4661 23:45:26.729920 [Gating] SW mode calibration
4662 23:45:26.738817 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4663 23:45:26.742027 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4664 23:45:26.749005 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4665 23:45:26.751802 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4666 23:45:26.755210 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4667 23:45:26.762230 0 9 12 | B1->B0 | 3131 3434 | 1 1 | (1 0) (1 0)
4668 23:45:26.764836 0 9 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4669 23:45:26.768522 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4670 23:45:26.774421 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4671 23:45:26.778449 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4672 23:45:26.781284 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4673 23:45:26.788046 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4674 23:45:26.791187 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4675 23:45:26.795043 0 10 12 | B1->B0 | 3737 2e2e | 1 0 | (0 0) (1 1)
4676 23:45:26.801408 0 10 16 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
4677 23:45:26.804739 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4678 23:45:26.808140 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4679 23:45:26.814544 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4680 23:45:26.817561 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4681 23:45:26.820890 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4682 23:45:26.827622 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4683 23:45:26.830985 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4684 23:45:26.834335 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4685 23:45:26.840537 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4686 23:45:26.843763 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4687 23:45:26.847489 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4688 23:45:26.853684 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4689 23:45:26.857570 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4690 23:45:26.860395 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4691 23:45:26.866861 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4692 23:45:26.870082 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4693 23:45:26.873504 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4694 23:45:26.880009 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4695 23:45:26.883591 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4696 23:45:26.886699 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4697 23:45:26.893277 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4698 23:45:26.896792 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4699 23:45:26.899648 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4700 23:45:26.906281 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4701 23:45:26.906854 Total UI for P1: 0, mck2ui 16
4702 23:45:26.913168 best dqsien dly found for B0: ( 0, 13, 12)
4703 23:45:26.913839 Total UI for P1: 0, mck2ui 16
4704 23:45:26.919482 best dqsien dly found for B1: ( 0, 13, 12)
4705 23:45:26.923182 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4706 23:45:26.926103 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4707 23:45:26.926738
4708 23:45:26.929563 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4709 23:45:26.932555 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4710 23:45:26.935971 [Gating] SW calibration Done
4711 23:45:26.936512 ==
4712 23:45:26.938949 Dram Type= 6, Freq= 0, CH_1, rank 1
4713 23:45:26.942542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4714 23:45:26.943076 ==
4715 23:45:26.945895 RX Vref Scan: 0
4716 23:45:26.946443
4717 23:45:26.948913 RX Vref 0 -> 0, step: 1
4718 23:45:26.949328
4719 23:45:26.949653 RX Delay -230 -> 252, step: 16
4720 23:45:26.955718 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4721 23:45:26.959216 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4722 23:45:26.962617 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4723 23:45:26.966322 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4724 23:45:26.972261 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4725 23:45:26.975739 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4726 23:45:26.979129 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4727 23:45:26.981767 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4728 23:45:26.989248 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4729 23:45:26.992416 iDelay=218, Bit 9, Center 33 (-134 ~ 201) 336
4730 23:45:26.995577 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4731 23:45:26.998677 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4732 23:45:27.005166 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4733 23:45:27.008599 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4734 23:45:27.011594 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4735 23:45:27.014929 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4736 23:45:27.015348 ==
4737 23:45:27.018832 Dram Type= 6, Freq= 0, CH_1, rank 1
4738 23:45:27.024978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4739 23:45:27.025558 ==
4740 23:45:27.026055 DQS Delay:
4741 23:45:27.028268 DQS0 = 0, DQS1 = 0
4742 23:45:27.028680 DQM Delay:
4743 23:45:27.029004 DQM0 = 44, DQM1 = 40
4744 23:45:27.031577 DQ Delay:
4745 23:45:27.034926 DQ0 =49, DQ1 =41, DQ2 =25, DQ3 =41
4746 23:45:27.038343 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4747 23:45:27.041954 DQ8 =25, DQ9 =33, DQ10 =33, DQ11 =33
4748 23:45:27.044950 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4749 23:45:27.045382
4750 23:45:27.045708
4751 23:45:27.046006 ==
4752 23:45:27.047956 Dram Type= 6, Freq= 0, CH_1, rank 1
4753 23:45:27.051236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4754 23:45:27.051654 ==
4755 23:45:27.051985
4756 23:45:27.052284
4757 23:45:27.054804 TX Vref Scan disable
4758 23:45:27.057993 == TX Byte 0 ==
4759 23:45:27.061624 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4760 23:45:27.064448 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4761 23:45:27.067663 == TX Byte 1 ==
4762 23:45:27.071233 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4763 23:45:27.074615 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4764 23:45:27.075222 ==
4765 23:45:27.078053 Dram Type= 6, Freq= 0, CH_1, rank 1
4766 23:45:27.081283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4767 23:45:27.084793 ==
4768 23:45:27.085317
4769 23:45:27.085643
4770 23:45:27.085940 TX Vref Scan disable
4771 23:45:27.088124 == TX Byte 0 ==
4772 23:45:27.091632 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4773 23:45:27.098090 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4774 23:45:27.098645 == TX Byte 1 ==
4775 23:45:27.101569 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4776 23:45:27.108325 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4777 23:45:27.108838
4778 23:45:27.109169 [DATLAT]
4779 23:45:27.109470 Freq=600, CH1 RK1
4780 23:45:27.109763
4781 23:45:27.111620 DATLAT Default: 0x9
4782 23:45:27.114600 0, 0xFFFF, sum = 0
4783 23:45:27.115020 1, 0xFFFF, sum = 0
4784 23:45:27.117788 2, 0xFFFF, sum = 0
4785 23:45:27.118230 3, 0xFFFF, sum = 0
4786 23:45:27.121088 4, 0xFFFF, sum = 0
4787 23:45:27.121679 5, 0xFFFF, sum = 0
4788 23:45:27.124359 6, 0xFFFF, sum = 0
4789 23:45:27.124976 7, 0xFFFF, sum = 0
4790 23:45:27.127791 8, 0x0, sum = 1
4791 23:45:27.128212 9, 0x0, sum = 2
4792 23:45:27.130837 10, 0x0, sum = 3
4793 23:45:27.131253 11, 0x0, sum = 4
4794 23:45:27.131583 best_step = 9
4795 23:45:27.131890
4796 23:45:27.134659 ==
4797 23:45:27.137520 Dram Type= 6, Freq= 0, CH_1, rank 1
4798 23:45:27.141110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4799 23:45:27.141641 ==
4800 23:45:27.141976 RX Vref Scan: 0
4801 23:45:27.142331
4802 23:45:27.144134 RX Vref 0 -> 0, step: 1
4803 23:45:27.144646
4804 23:45:27.147933 RX Delay -179 -> 252, step: 8
4805 23:45:27.154491 iDelay=213, Bit 0, Center 48 (-99 ~ 196) 296
4806 23:45:27.157871 iDelay=213, Bit 1, Center 40 (-107 ~ 188) 296
4807 23:45:27.160686 iDelay=213, Bit 2, Center 32 (-115 ~ 180) 296
4808 23:45:27.163563 iDelay=213, Bit 3, Center 40 (-107 ~ 188) 296
4809 23:45:27.170684 iDelay=213, Bit 4, Center 44 (-107 ~ 196) 304
4810 23:45:27.174004 iDelay=213, Bit 5, Center 56 (-91 ~ 204) 296
4811 23:45:27.177146 iDelay=213, Bit 6, Center 60 (-91 ~ 212) 304
4812 23:45:27.180605 iDelay=213, Bit 7, Center 40 (-115 ~ 196) 312
4813 23:45:27.183575 iDelay=213, Bit 8, Center 28 (-123 ~ 180) 304
4814 23:45:27.190383 iDelay=213, Bit 9, Center 24 (-131 ~ 180) 312
4815 23:45:27.193751 iDelay=213, Bit 10, Center 36 (-115 ~ 188) 304
4816 23:45:27.196997 iDelay=213, Bit 11, Center 28 (-123 ~ 180) 304
4817 23:45:27.200314 iDelay=213, Bit 12, Center 48 (-107 ~ 204) 312
4818 23:45:27.206732 iDelay=213, Bit 13, Center 44 (-107 ~ 196) 304
4819 23:45:27.210014 iDelay=213, Bit 14, Center 44 (-107 ~ 196) 304
4820 23:45:27.213751 iDelay=213, Bit 15, Center 48 (-107 ~ 204) 312
4821 23:45:27.214305 ==
4822 23:45:27.217174 Dram Type= 6, Freq= 0, CH_1, rank 1
4823 23:45:27.219756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4824 23:45:27.223219 ==
4825 23:45:27.223632 DQS Delay:
4826 23:45:27.223957 DQS0 = 0, DQS1 = 0
4827 23:45:27.226532 DQM Delay:
4828 23:45:27.227139 DQM0 = 45, DQM1 = 37
4829 23:45:27.229953 DQ Delay:
4830 23:45:27.230518 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4831 23:45:27.233073 DQ4 =44, DQ5 =56, DQ6 =60, DQ7 =40
4832 23:45:27.236647 DQ8 =28, DQ9 =24, DQ10 =36, DQ11 =28
4833 23:45:27.240480 DQ12 =48, DQ13 =44, DQ14 =44, DQ15 =48
4834 23:45:27.242875
4835 23:45:27.243524
4836 23:45:27.249228 [DQSOSCAuto] RK1, (LSB)MR18= 0x3227, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 400 ps
4837 23:45:27.252724 CH1 RK1: MR19=808, MR18=3227
4838 23:45:27.259454 CH1_RK1: MR19=0x808, MR18=0x3227, DQSOSC=400, MR23=63, INC=163, DEC=109
4839 23:45:27.263051 [RxdqsGatingPostProcess] freq 600
4840 23:45:27.265869 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4841 23:45:27.269187 Pre-setting of DQS Precalculation
4842 23:45:27.275519 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4843 23:45:27.282306 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4844 23:45:27.289160 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4845 23:45:27.289805
4846 23:45:27.290141
4847 23:45:27.292283 [Calibration Summary] 1200 Mbps
4848 23:45:27.292842 CH 0, Rank 0
4849 23:45:27.295238 SW Impedance : PASS
4850 23:45:27.298718 DUTY Scan : NO K
4851 23:45:27.299135 ZQ Calibration : PASS
4852 23:45:27.302307 Jitter Meter : NO K
4853 23:45:27.305680 CBT Training : PASS
4854 23:45:27.306120 Write leveling : PASS
4855 23:45:27.308567 RX DQS gating : PASS
4856 23:45:27.311975 RX DQ/DQS(RDDQC) : PASS
4857 23:45:27.312390 TX DQ/DQS : PASS
4858 23:45:27.315565 RX DATLAT : PASS
4859 23:45:27.318760 RX DQ/DQS(Engine): PASS
4860 23:45:27.319257 TX OE : NO K
4861 23:45:27.322045 All Pass.
4862 23:45:27.322592
4863 23:45:27.322923 CH 0, Rank 1
4864 23:45:27.325024 SW Impedance : PASS
4865 23:45:27.325502 DUTY Scan : NO K
4866 23:45:27.328484 ZQ Calibration : PASS
4867 23:45:27.331757 Jitter Meter : NO K
4868 23:45:27.332236 CBT Training : PASS
4869 23:45:27.335070 Write leveling : PASS
4870 23:45:27.338335 RX DQS gating : PASS
4871 23:45:27.338750 RX DQ/DQS(RDDQC) : PASS
4872 23:45:27.341791 TX DQ/DQS : PASS
4873 23:45:27.342247 RX DATLAT : PASS
4874 23:45:27.344691 RX DQ/DQS(Engine): PASS
4875 23:45:27.348218 TX OE : NO K
4876 23:45:27.348787 All Pass.
4877 23:45:27.349494
4878 23:45:27.351568 CH 1, Rank 0
4879 23:45:27.351978 SW Impedance : PASS
4880 23:45:27.354740 DUTY Scan : NO K
4881 23:45:27.355179 ZQ Calibration : PASS
4882 23:45:27.358050 Jitter Meter : NO K
4883 23:45:27.361494 CBT Training : PASS
4884 23:45:27.362008 Write leveling : PASS
4885 23:45:27.364679 RX DQS gating : PASS
4886 23:45:27.367801 RX DQ/DQS(RDDQC) : PASS
4887 23:45:27.368330 TX DQ/DQS : PASS
4888 23:45:27.370906 RX DATLAT : PASS
4889 23:45:27.375381 RX DQ/DQS(Engine): PASS
4890 23:45:27.375797 TX OE : NO K
4891 23:45:27.378105 All Pass.
4892 23:45:27.378566
4893 23:45:27.378888 CH 1, Rank 1
4894 23:45:27.381355 SW Impedance : PASS
4895 23:45:27.381766 DUTY Scan : NO K
4896 23:45:27.384415 ZQ Calibration : PASS
4897 23:45:27.387772 Jitter Meter : NO K
4898 23:45:27.388193 CBT Training : PASS
4899 23:45:27.391402 Write leveling : PASS
4900 23:45:27.394631 RX DQS gating : PASS
4901 23:45:27.395187 RX DQ/DQS(RDDQC) : PASS
4902 23:45:27.397981 TX DQ/DQS : PASS
4903 23:45:27.401440 RX DATLAT : PASS
4904 23:45:27.401852 RX DQ/DQS(Engine): PASS
4905 23:45:27.404348 TX OE : NO K
4906 23:45:27.404763 All Pass.
4907 23:45:27.405102
4908 23:45:27.407421 DramC Write-DBI off
4909 23:45:27.411023 PER_BANK_REFRESH: Hybrid Mode
4910 23:45:27.411436 TX_TRACKING: ON
4911 23:45:27.420610 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4912 23:45:27.424445 [FAST_K] Save calibration result to emmc
4913 23:45:27.427384 dramc_set_vcore_voltage set vcore to 662500
4914 23:45:27.430868 Read voltage for 933, 3
4915 23:45:27.431479 Vio18 = 0
4916 23:45:27.431817 Vcore = 662500
4917 23:45:27.434235 Vdram = 0
4918 23:45:27.434752 Vddq = 0
4919 23:45:27.435081 Vmddr = 0
4920 23:45:27.441073 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4921 23:45:27.444111 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4922 23:45:27.447105 MEM_TYPE=3, freq_sel=17
4923 23:45:27.450857 sv_algorithm_assistance_LP4_1600
4924 23:45:27.454025 ============ PULL DRAM RESETB DOWN ============
4925 23:45:27.457332 ========== PULL DRAM RESETB DOWN end =========
4926 23:45:27.464046 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4927 23:45:27.466917 ===================================
4928 23:45:27.470302 LPDDR4 DRAM CONFIGURATION
4929 23:45:27.470860 ===================================
4930 23:45:27.473655 EX_ROW_EN[0] = 0x0
4931 23:45:27.477095 EX_ROW_EN[1] = 0x0
4932 23:45:27.477682 LP4Y_EN = 0x0
4933 23:45:27.480413 WORK_FSP = 0x0
4934 23:45:27.481077 WL = 0x3
4935 23:45:27.483888 RL = 0x3
4936 23:45:27.484446 BL = 0x2
4937 23:45:27.487293 RPST = 0x0
4938 23:45:27.487770 RD_PRE = 0x0
4939 23:45:27.490033 WR_PRE = 0x1
4940 23:45:27.490621 WR_PST = 0x0
4941 23:45:27.493593 DBI_WR = 0x0
4942 23:45:27.494147 DBI_RD = 0x0
4943 23:45:27.496915 OTF = 0x1
4944 23:45:27.500270 ===================================
4945 23:45:27.503314 ===================================
4946 23:45:27.503776 ANA top config
4947 23:45:27.506788 ===================================
4948 23:45:27.510659 DLL_ASYNC_EN = 0
4949 23:45:27.513514 ALL_SLAVE_EN = 1
4950 23:45:27.516719 NEW_RANK_MODE = 1
4951 23:45:27.517298 DLL_IDLE_MODE = 1
4952 23:45:27.519699 LP45_APHY_COMB_EN = 1
4953 23:45:27.523448 TX_ODT_DIS = 1
4954 23:45:27.526645 NEW_8X_MODE = 1
4955 23:45:27.529569 ===================================
4956 23:45:27.533351 ===================================
4957 23:45:27.536562 data_rate = 1866
4958 23:45:27.539796 CKR = 1
4959 23:45:27.540347 DQ_P2S_RATIO = 8
4960 23:45:27.542991 ===================================
4961 23:45:27.546314 CA_P2S_RATIO = 8
4962 23:45:27.550123 DQ_CA_OPEN = 0
4963 23:45:27.552787 DQ_SEMI_OPEN = 0
4964 23:45:27.556327 CA_SEMI_OPEN = 0
4965 23:45:27.559471 CA_FULL_RATE = 0
4966 23:45:27.560029 DQ_CKDIV4_EN = 1
4967 23:45:27.562681 CA_CKDIV4_EN = 1
4968 23:45:27.566328 CA_PREDIV_EN = 0
4969 23:45:27.569333 PH8_DLY = 0
4970 23:45:27.572533 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4971 23:45:27.575862 DQ_AAMCK_DIV = 4
4972 23:45:27.576325 CA_AAMCK_DIV = 4
4973 23:45:27.579183 CA_ADMCK_DIV = 4
4974 23:45:27.582668 DQ_TRACK_CA_EN = 0
4975 23:45:27.586459 CA_PICK = 933
4976 23:45:27.589266 CA_MCKIO = 933
4977 23:45:27.592082 MCKIO_SEMI = 0
4978 23:45:27.595854 PLL_FREQ = 3732
4979 23:45:27.596376 DQ_UI_PI_RATIO = 32
4980 23:45:27.599118 CA_UI_PI_RATIO = 0
4981 23:45:27.602329 ===================================
4982 23:45:27.605713 ===================================
4983 23:45:27.609423 memory_type:LPDDR4
4984 23:45:27.612269 GP_NUM : 10
4985 23:45:27.612682 SRAM_EN : 1
4986 23:45:27.615562 MD32_EN : 0
4987 23:45:27.618846 ===================================
4988 23:45:27.622300 [ANA_INIT] >>>>>>>>>>>>>>
4989 23:45:27.622746 <<<<<< [CONFIGURE PHASE]: ANA_TX
4990 23:45:27.628944 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4991 23:45:27.632192 ===================================
4992 23:45:27.632608 data_rate = 1866,PCW = 0X8f00
4993 23:45:27.635771 ===================================
4994 23:45:27.638374 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4995 23:45:27.644951 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4996 23:45:27.651798 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4997 23:45:27.654851 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4998 23:45:27.658259 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4999 23:45:27.661713 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5000 23:45:27.664661 [ANA_INIT] flow start
5001 23:45:27.668089 [ANA_INIT] PLL >>>>>>>>
5002 23:45:27.668607 [ANA_INIT] PLL <<<<<<<<
5003 23:45:27.671084 [ANA_INIT] MIDPI >>>>>>>>
5004 23:45:27.674509 [ANA_INIT] MIDPI <<<<<<<<
5005 23:45:27.674938 [ANA_INIT] DLL >>>>>>>>
5006 23:45:27.677596 [ANA_INIT] flow end
5007 23:45:27.681481 ============ LP4 DIFF to SE enter ============
5008 23:45:27.687999 ============ LP4 DIFF to SE exit ============
5009 23:45:27.688539 [ANA_INIT] <<<<<<<<<<<<<
5010 23:45:27.691486 [Flow] Enable top DCM control >>>>>
5011 23:45:27.694705 [Flow] Enable top DCM control <<<<<
5012 23:45:27.697986 Enable DLL master slave shuffle
5013 23:45:27.704610 ==============================================================
5014 23:45:27.705178 Gating Mode config
5015 23:45:27.711154 ==============================================================
5016 23:45:27.714060 Config description:
5017 23:45:27.720766 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5018 23:45:27.727157 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5019 23:45:27.733725 SELPH_MODE 0: By rank 1: By Phase
5020 23:45:27.740980 ==============================================================
5021 23:45:27.743904 GAT_TRACK_EN = 1
5022 23:45:27.744443 RX_GATING_MODE = 2
5023 23:45:27.747459 RX_GATING_TRACK_MODE = 2
5024 23:45:27.750967 SELPH_MODE = 1
5025 23:45:27.753747 PICG_EARLY_EN = 1
5026 23:45:27.757314 VALID_LAT_VALUE = 1
5027 23:45:27.763915 ==============================================================
5028 23:45:27.767201 Enter into Gating configuration >>>>
5029 23:45:27.770282 Exit from Gating configuration <<<<
5030 23:45:27.773856 Enter into DVFS_PRE_config >>>>>
5031 23:45:27.783463 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5032 23:45:27.786844 Exit from DVFS_PRE_config <<<<<
5033 23:45:27.790123 Enter into PICG configuration >>>>
5034 23:45:27.793616 Exit from PICG configuration <<<<
5035 23:45:27.796911 [RX_INPUT] configuration >>>>>
5036 23:45:27.800369 [RX_INPUT] configuration <<<<<
5037 23:45:27.803605 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5038 23:45:27.810016 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5039 23:45:27.816950 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5040 23:45:27.822879 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5041 23:45:27.826452 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5042 23:45:27.832985 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5043 23:45:27.836152 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5044 23:45:27.843150 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5045 23:45:27.846123 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5046 23:45:27.849654 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5047 23:45:27.852798 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5048 23:45:27.859399 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5049 23:45:27.862473 ===================================
5050 23:45:27.865829 LPDDR4 DRAM CONFIGURATION
5051 23:45:27.869229 ===================================
5052 23:45:27.869690 EX_ROW_EN[0] = 0x0
5053 23:45:27.872960 EX_ROW_EN[1] = 0x0
5054 23:45:27.873532 LP4Y_EN = 0x0
5055 23:45:27.876401 WORK_FSP = 0x0
5056 23:45:27.876992 WL = 0x3
5057 23:45:27.879253 RL = 0x3
5058 23:45:27.879710 BL = 0x2
5059 23:45:27.882383 RPST = 0x0
5060 23:45:27.882842 RD_PRE = 0x0
5061 23:45:27.885991 WR_PRE = 0x1
5062 23:45:27.886616 WR_PST = 0x0
5063 23:45:27.889298 DBI_WR = 0x0
5064 23:45:27.892503 DBI_RD = 0x0
5065 23:45:27.893066 OTF = 0x1
5066 23:45:27.895476 ===================================
5067 23:45:27.899026 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5068 23:45:27.902909 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5069 23:45:27.909245 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5070 23:45:27.911890 ===================================
5071 23:45:27.915177 LPDDR4 DRAM CONFIGURATION
5072 23:45:27.918683 ===================================
5073 23:45:27.919098 EX_ROW_EN[0] = 0x10
5074 23:45:27.921987 EX_ROW_EN[1] = 0x0
5075 23:45:27.922431 LP4Y_EN = 0x0
5076 23:45:27.925251 WORK_FSP = 0x0
5077 23:45:27.925665 WL = 0x3
5078 23:45:27.928654 RL = 0x3
5079 23:45:27.929074 BL = 0x2
5080 23:45:27.931961 RPST = 0x0
5081 23:45:27.932376 RD_PRE = 0x0
5082 23:45:27.934864 WR_PRE = 0x1
5083 23:45:27.938848 WR_PST = 0x0
5084 23:45:27.939372 DBI_WR = 0x0
5085 23:45:27.941999 DBI_RD = 0x0
5086 23:45:27.942594 OTF = 0x1
5087 23:45:27.945861 ===================================
5088 23:45:27.951889 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5089 23:45:27.955219 nWR fixed to 30
5090 23:45:27.958351 [ModeRegInit_LP4] CH0 RK0
5091 23:45:27.958768 [ModeRegInit_LP4] CH0 RK1
5092 23:45:27.962047 [ModeRegInit_LP4] CH1 RK0
5093 23:45:27.965859 [ModeRegInit_LP4] CH1 RK1
5094 23:45:27.966432 match AC timing 9
5095 23:45:27.972738 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5096 23:45:27.975481 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5097 23:45:27.979105 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5098 23:45:27.985861 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5099 23:45:27.988515 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5100 23:45:27.988983 ==
5101 23:45:27.991682 Dram Type= 6, Freq= 0, CH_0, rank 0
5102 23:45:27.994690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5103 23:45:27.995155 ==
5104 23:45:28.001763 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5105 23:45:28.008343 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5106 23:45:28.011341 [CA 0] Center 37 (7~68) winsize 62
5107 23:45:28.014707 [CA 1] Center 37 (7~68) winsize 62
5108 23:45:28.017884 [CA 2] Center 34 (4~65) winsize 62
5109 23:45:28.021007 [CA 3] Center 35 (5~65) winsize 61
5110 23:45:28.024377 [CA 4] Center 33 (3~64) winsize 62
5111 23:45:28.027864 [CA 5] Center 33 (3~63) winsize 61
5112 23:45:28.028308
5113 23:45:28.030989 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5114 23:45:28.031412
5115 23:45:28.034751 [CATrainingPosCal] consider 1 rank data
5116 23:45:28.037633 u2DelayCellTimex100 = 270/100 ps
5117 23:45:28.041268 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5118 23:45:28.044935 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5119 23:45:28.047628 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5120 23:45:28.054276 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5121 23:45:28.057413 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5122 23:45:28.060859 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5123 23:45:28.061320
5124 23:45:28.064961 CA PerBit enable=1, Macro0, CA PI delay=33
5125 23:45:28.065528
5126 23:45:28.067584 [CBTSetCACLKResult] CA Dly = 33
5127 23:45:28.068091 CS Dly: 7 (0~38)
5128 23:45:28.068469 ==
5129 23:45:28.070915 Dram Type= 6, Freq= 0, CH_0, rank 1
5130 23:45:28.077652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5131 23:45:28.078288 ==
5132 23:45:28.080675 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5133 23:45:28.086893 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5134 23:45:28.090707 [CA 0] Center 37 (7~68) winsize 62
5135 23:45:28.094217 [CA 1] Center 37 (7~68) winsize 62
5136 23:45:28.097256 [CA 2] Center 34 (4~65) winsize 62
5137 23:45:28.100868 [CA 3] Center 35 (5~65) winsize 61
5138 23:45:28.104634 [CA 4] Center 33 (3~64) winsize 62
5139 23:45:28.106793 [CA 5] Center 33 (3~63) winsize 61
5140 23:45:28.107255
5141 23:45:28.110539 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5142 23:45:28.111118
5143 23:45:28.113470 [CATrainingPosCal] consider 2 rank data
5144 23:45:28.116642 u2DelayCellTimex100 = 270/100 ps
5145 23:45:28.120200 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5146 23:45:28.126471 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5147 23:45:28.130060 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5148 23:45:28.133742 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5149 23:45:28.136395 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5150 23:45:28.139674 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5151 23:45:28.140091
5152 23:45:28.143140 CA PerBit enable=1, Macro0, CA PI delay=33
5153 23:45:28.143555
5154 23:45:28.146417 [CBTSetCACLKResult] CA Dly = 33
5155 23:45:28.149757 CS Dly: 7 (0~39)
5156 23:45:28.150219
5157 23:45:28.153456 ----->DramcWriteLeveling(PI) begin...
5158 23:45:28.153990 ==
5159 23:45:28.156514 Dram Type= 6, Freq= 0, CH_0, rank 0
5160 23:45:28.160126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5161 23:45:28.160608 ==
5162 23:45:28.162687 Write leveling (Byte 0): 32 => 32
5163 23:45:28.166255 Write leveling (Byte 1): 29 => 29
5164 23:45:28.169263 DramcWriteLeveling(PI) end<-----
5165 23:45:28.169683
5166 23:45:28.170013 ==
5167 23:45:28.172569 Dram Type= 6, Freq= 0, CH_0, rank 0
5168 23:45:28.175794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5169 23:45:28.176223 ==
5170 23:45:28.179602 [Gating] SW mode calibration
5171 23:45:28.186657 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5172 23:45:28.192892 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5173 23:45:28.196033 0 14 0 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
5174 23:45:28.199420 0 14 4 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
5175 23:45:28.205876 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5176 23:45:28.210131 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5177 23:45:28.213290 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5178 23:45:28.219106 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5179 23:45:28.222373 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5180 23:45:28.226068 0 14 28 | B1->B0 | 3434 3030 | 1 1 | (1 1) (0 1)
5181 23:45:28.232728 0 15 0 | B1->B0 | 3131 2424 | 1 0 | (1 0) (0 0)
5182 23:45:28.235727 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5183 23:45:28.239454 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5184 23:45:28.245636 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5185 23:45:28.248722 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5186 23:45:28.252529 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5187 23:45:28.258546 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5188 23:45:28.261861 0 15 28 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
5189 23:45:28.265168 1 0 0 | B1->B0 | 3030 4646 | 0 0 | (1 1) (0 0)
5190 23:45:28.271934 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5191 23:45:28.275155 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5192 23:45:28.278371 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5193 23:45:28.285052 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5194 23:45:28.288346 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5195 23:45:28.291801 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5196 23:45:28.298294 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5197 23:45:28.301814 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5198 23:45:28.305277 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 23:45:28.311628 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5200 23:45:28.314994 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 23:45:28.318430 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 23:45:28.324899 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5203 23:45:28.327985 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5204 23:45:28.331098 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5205 23:45:28.338271 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5206 23:45:28.341837 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5207 23:45:28.344522 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5208 23:45:28.350991 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5209 23:45:28.354463 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5210 23:45:28.357915 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5211 23:45:28.364594 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5212 23:45:28.367517 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5213 23:45:28.371348 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5214 23:45:28.374097 Total UI for P1: 0, mck2ui 16
5215 23:45:28.377607 best dqsien dly found for B0: ( 1, 2, 28)
5216 23:45:28.384064 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5217 23:45:28.384580 Total UI for P1: 0, mck2ui 16
5218 23:45:28.390975 best dqsien dly found for B1: ( 1, 3, 0)
5219 23:45:28.394272 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5220 23:45:28.398084 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5221 23:45:28.398529
5222 23:45:28.400480 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5223 23:45:28.404652 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5224 23:45:28.407475 [Gating] SW calibration Done
5225 23:45:28.407889 ==
5226 23:45:28.410367 Dram Type= 6, Freq= 0, CH_0, rank 0
5227 23:45:28.414090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5228 23:45:28.414639 ==
5229 23:45:28.417341 RX Vref Scan: 0
5230 23:45:28.417753
5231 23:45:28.418211 RX Vref 0 -> 0, step: 1
5232 23:45:28.418545
5233 23:45:28.421072 RX Delay -80 -> 252, step: 8
5234 23:45:28.423957 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5235 23:45:28.430332 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5236 23:45:28.433885 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5237 23:45:28.436913 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5238 23:45:28.440000 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5239 23:45:28.443931 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5240 23:45:28.446708 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5241 23:45:28.453592 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5242 23:45:28.456828 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5243 23:45:28.459918 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5244 23:45:28.463019 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5245 23:45:28.469996 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5246 23:45:28.472897 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5247 23:45:28.476473 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5248 23:45:28.479722 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5249 23:45:28.482836 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5250 23:45:28.483268 ==
5251 23:45:28.486611 Dram Type= 6, Freq= 0, CH_0, rank 0
5252 23:45:28.493032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5253 23:45:28.493468 ==
5254 23:45:28.493903 DQS Delay:
5255 23:45:28.496179 DQS0 = 0, DQS1 = 0
5256 23:45:28.496800 DQM Delay:
5257 23:45:28.497233 DQM0 = 96, DQM1 = 85
5258 23:45:28.499677 DQ Delay:
5259 23:45:28.503354 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5260 23:45:28.506071 DQ4 =99, DQ5 =83, DQ6 =107, DQ7 =107
5261 23:45:28.509383 DQ8 =79, DQ9 =79, DQ10 =83, DQ11 =83
5262 23:45:28.513001 DQ12 =87, DQ13 =91, DQ14 =91, DQ15 =91
5263 23:45:28.513522
5264 23:45:28.513978
5265 23:45:28.514445 ==
5266 23:45:28.516075 Dram Type= 6, Freq= 0, CH_0, rank 0
5267 23:45:28.519551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5268 23:45:28.519970 ==
5269 23:45:28.520302
5270 23:45:28.520606
5271 23:45:28.522809 TX Vref Scan disable
5272 23:45:28.525766 == TX Byte 0 ==
5273 23:45:28.529536 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5274 23:45:28.532631 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5275 23:45:28.535838 == TX Byte 1 ==
5276 23:45:28.539190 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5277 23:45:28.542564 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5278 23:45:28.542996 ==
5279 23:45:28.545570 Dram Type= 6, Freq= 0, CH_0, rank 0
5280 23:45:28.552143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5281 23:45:28.552687 ==
5282 23:45:28.553128
5283 23:45:28.553530
5284 23:45:28.553925 TX Vref Scan disable
5285 23:45:28.556603 == TX Byte 0 ==
5286 23:45:28.559428 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5287 23:45:28.565654 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5288 23:45:28.566246 == TX Byte 1 ==
5289 23:45:28.569362 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5290 23:45:28.576424 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5291 23:45:28.576932
5292 23:45:28.577449 [DATLAT]
5293 23:45:28.577860 Freq=933, CH0 RK0
5294 23:45:28.578457
5295 23:45:28.579250 DATLAT Default: 0xd
5296 23:45:28.582145 0, 0xFFFF, sum = 0
5297 23:45:28.582600 1, 0xFFFF, sum = 0
5298 23:45:28.585818 2, 0xFFFF, sum = 0
5299 23:45:28.586393 3, 0xFFFF, sum = 0
5300 23:45:28.589349 4, 0xFFFF, sum = 0
5301 23:45:28.589765 5, 0xFFFF, sum = 0
5302 23:45:28.592275 6, 0xFFFF, sum = 0
5303 23:45:28.592764 7, 0xFFFF, sum = 0
5304 23:45:28.595839 8, 0xFFFF, sum = 0
5305 23:45:28.596361 9, 0xFFFF, sum = 0
5306 23:45:28.598706 10, 0x0, sum = 1
5307 23:45:28.599126 11, 0x0, sum = 2
5308 23:45:28.602510 12, 0x0, sum = 3
5309 23:45:28.602931 13, 0x0, sum = 4
5310 23:45:28.605519 best_step = 11
5311 23:45:28.605929
5312 23:45:28.606301 ==
5313 23:45:28.609147 Dram Type= 6, Freq= 0, CH_0, rank 0
5314 23:45:28.612059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5315 23:45:28.612580 ==
5316 23:45:28.615371 RX Vref Scan: 1
5317 23:45:28.615984
5318 23:45:28.616413 RX Vref 0 -> 0, step: 1
5319 23:45:28.616740
5320 23:45:28.618578 RX Delay -61 -> 252, step: 4
5321 23:45:28.618999
5322 23:45:28.621793 Set Vref, RX VrefLevel [Byte0]: 57
5323 23:45:28.624946 [Byte1]: 50
5324 23:45:28.628722
5325 23:45:28.629135 Final RX Vref Byte 0 = 57 to rank0
5326 23:45:28.632451 Final RX Vref Byte 1 = 50 to rank0
5327 23:45:28.635219 Final RX Vref Byte 0 = 57 to rank1
5328 23:45:28.638724 Final RX Vref Byte 1 = 50 to rank1==
5329 23:45:28.641789 Dram Type= 6, Freq= 0, CH_0, rank 0
5330 23:45:28.648135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5331 23:45:28.648547 ==
5332 23:45:28.648869 DQS Delay:
5333 23:45:28.651813 DQS0 = 0, DQS1 = 0
5334 23:45:28.652221 DQM Delay:
5335 23:45:28.652541 DQM0 = 96, DQM1 = 85
5336 23:45:28.654770 DQ Delay:
5337 23:45:28.658481 DQ0 =96, DQ1 =98, DQ2 =92, DQ3 =94
5338 23:45:28.661363 DQ4 =98, DQ5 =88, DQ6 =104, DQ7 =104
5339 23:45:28.664644 DQ8 =76, DQ9 =74, DQ10 =86, DQ11 =80
5340 23:45:28.668171 DQ12 =90, DQ13 =88, DQ14 =98, DQ15 =92
5341 23:45:28.668560
5342 23:45:28.668796
5343 23:45:28.674515 [DQSOSCAuto] RK0, (LSB)MR18= 0x2a11, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 408 ps
5344 23:45:28.678074 CH0 RK0: MR19=505, MR18=2A11
5345 23:45:28.684933 CH0_RK0: MR19=0x505, MR18=0x2A11, DQSOSC=408, MR23=63, INC=65, DEC=43
5346 23:45:28.685326
5347 23:45:28.688137 ----->DramcWriteLeveling(PI) begin...
5348 23:45:28.688528 ==
5349 23:45:28.690962 Dram Type= 6, Freq= 0, CH_0, rank 1
5350 23:45:28.695088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5351 23:45:28.695483 ==
5352 23:45:28.698129 Write leveling (Byte 0): 33 => 33
5353 23:45:28.701461 Write leveling (Byte 1): 29 => 29
5354 23:45:28.704461 DramcWriteLeveling(PI) end<-----
5355 23:45:28.705000
5356 23:45:28.705362 ==
5357 23:45:28.708055 Dram Type= 6, Freq= 0, CH_0, rank 1
5358 23:45:28.710985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5359 23:45:28.714604 ==
5360 23:45:28.715118 [Gating] SW mode calibration
5361 23:45:28.724352 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5362 23:45:28.727854 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5363 23:45:28.731067 0 14 0 | B1->B0 | 2b2b 3333 | 0 1 | (0 0) (1 1)
5364 23:45:28.737663 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5365 23:45:28.741261 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5366 23:45:28.744528 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5367 23:45:28.750915 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5368 23:45:28.754147 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5369 23:45:28.757348 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5370 23:45:28.763747 0 14 28 | B1->B0 | 3434 2f2f | 0 1 | (0 1) (1 1)
5371 23:45:28.767796 0 15 0 | B1->B0 | 2f2f 2727 | 1 0 | (1 0) (0 0)
5372 23:45:28.770700 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5373 23:45:28.777577 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5374 23:45:28.780305 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5375 23:45:28.784057 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5376 23:45:28.790273 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5377 23:45:28.793453 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5378 23:45:28.797129 0 15 28 | B1->B0 | 2525 3232 | 0 0 | (0 0) (0 0)
5379 23:45:28.803709 1 0 0 | B1->B0 | 3e3e 3e3e | 0 0 | (0 0) (0 0)
5380 23:45:28.807414 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5381 23:45:28.810328 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5382 23:45:28.817055 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5383 23:45:28.820119 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5384 23:45:28.822992 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5385 23:45:28.830040 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5386 23:45:28.833074 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5387 23:45:28.836432 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5388 23:45:28.843321 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 23:45:28.846324 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 23:45:28.849831 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 23:45:28.856790 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 23:45:28.859589 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 23:45:28.862675 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 23:45:28.869713 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 23:45:28.872388 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 23:45:28.875739 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5397 23:45:28.882583 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5398 23:45:28.887147 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5399 23:45:28.889109 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5400 23:45:28.896039 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5401 23:45:28.899015 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5402 23:45:28.902276 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5403 23:45:28.908646 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5404 23:45:28.912673 Total UI for P1: 0, mck2ui 16
5405 23:45:28.915496 best dqsien dly found for B0: ( 1, 2, 28)
5406 23:45:28.918993 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5407 23:45:28.922293 Total UI for P1: 0, mck2ui 16
5408 23:45:28.925827 best dqsien dly found for B1: ( 1, 2, 30)
5409 23:45:28.929140 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5410 23:45:28.931848 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5411 23:45:28.932314
5412 23:45:28.935374 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5413 23:45:28.941642 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5414 23:45:28.942108 [Gating] SW calibration Done
5415 23:45:28.942533 ==
5416 23:45:28.945063 Dram Type= 6, Freq= 0, CH_0, rank 1
5417 23:45:28.951545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5418 23:45:28.952225 ==
5419 23:45:28.952611 RX Vref Scan: 0
5420 23:45:28.952955
5421 23:45:28.955281 RX Vref 0 -> 0, step: 1
5422 23:45:28.955817
5423 23:45:28.958205 RX Delay -80 -> 252, step: 8
5424 23:45:28.961985 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5425 23:45:28.964987 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5426 23:45:28.968487 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5427 23:45:28.971558 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5428 23:45:28.978312 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5429 23:45:28.981536 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5430 23:45:28.984871 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5431 23:45:28.988119 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5432 23:45:28.992100 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5433 23:45:28.994831 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5434 23:45:29.001334 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5435 23:45:29.004546 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5436 23:45:29.007824 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5437 23:45:29.011539 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5438 23:45:29.014548 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5439 23:45:29.021184 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5440 23:45:29.021940 ==
5441 23:45:29.024740 Dram Type= 6, Freq= 0, CH_0, rank 1
5442 23:45:29.027594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5443 23:45:29.028071 ==
5444 23:45:29.028589 DQS Delay:
5445 23:45:29.030620 DQS0 = 0, DQS1 = 0
5446 23:45:29.031090 DQM Delay:
5447 23:45:29.034774 DQM0 = 96, DQM1 = 88
5448 23:45:29.035425 DQ Delay:
5449 23:45:29.038069 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5450 23:45:29.041048 DQ4 =95, DQ5 =87, DQ6 =103, DQ7 =107
5451 23:45:29.043950 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =79
5452 23:45:29.047260 DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =91
5453 23:45:29.047825
5454 23:45:29.048305
5455 23:45:29.048749 ==
5456 23:45:29.050529 Dram Type= 6, Freq= 0, CH_0, rank 1
5457 23:45:29.057388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5458 23:45:29.057963 ==
5459 23:45:29.058519
5460 23:45:29.058975
5461 23:45:29.059413 TX Vref Scan disable
5462 23:45:29.060398 == TX Byte 0 ==
5463 23:45:29.063821 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5464 23:45:29.070608 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5465 23:45:29.071074 == TX Byte 1 ==
5466 23:45:29.073701 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5467 23:45:29.080870 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5468 23:45:29.081392 ==
5469 23:45:29.084071 Dram Type= 6, Freq= 0, CH_0, rank 1
5470 23:45:29.087355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5471 23:45:29.087883 ==
5472 23:45:29.088244
5473 23:45:29.088549
5474 23:45:29.090024 TX Vref Scan disable
5475 23:45:29.090480 == TX Byte 0 ==
5476 23:45:29.097250 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5477 23:45:29.100429 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5478 23:45:29.103738 == TX Byte 1 ==
5479 23:45:29.106899 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5480 23:45:29.110291 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5481 23:45:29.110814
5482 23:45:29.111142 [DATLAT]
5483 23:45:29.113776 Freq=933, CH0 RK1
5484 23:45:29.114335
5485 23:45:29.114669 DATLAT Default: 0xb
5486 23:45:29.116568 0, 0xFFFF, sum = 0
5487 23:45:29.119702 1, 0xFFFF, sum = 0
5488 23:45:29.120123 2, 0xFFFF, sum = 0
5489 23:45:29.123140 3, 0xFFFF, sum = 0
5490 23:45:29.123559 4, 0xFFFF, sum = 0
5491 23:45:29.126660 5, 0xFFFF, sum = 0
5492 23:45:29.127076 6, 0xFFFF, sum = 0
5493 23:45:29.130194 7, 0xFFFF, sum = 0
5494 23:45:29.130717 8, 0xFFFF, sum = 0
5495 23:45:29.133628 9, 0xFFFF, sum = 0
5496 23:45:29.134044 10, 0x0, sum = 1
5497 23:45:29.136378 11, 0x0, sum = 2
5498 23:45:29.136794 12, 0x0, sum = 3
5499 23:45:29.140395 13, 0x0, sum = 4
5500 23:45:29.140932 best_step = 11
5501 23:45:29.141374
5502 23:45:29.141774 ==
5503 23:45:29.143204 Dram Type= 6, Freq= 0, CH_0, rank 1
5504 23:45:29.146454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5505 23:45:29.146885 ==
5506 23:45:29.149845 RX Vref Scan: 0
5507 23:45:29.150496
5508 23:45:29.152933 RX Vref 0 -> 0, step: 1
5509 23:45:29.153402
5510 23:45:29.153738 RX Delay -61 -> 252, step: 4
5511 23:45:29.160903 iDelay=203, Bit 0, Center 92 (3 ~ 182) 180
5512 23:45:29.164268 iDelay=203, Bit 1, Center 98 (3 ~ 194) 192
5513 23:45:29.167632 iDelay=203, Bit 2, Center 90 (-1 ~ 182) 184
5514 23:45:29.170642 iDelay=203, Bit 3, Center 94 (-1 ~ 190) 192
5515 23:45:29.174248 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5516 23:45:29.177239 iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192
5517 23:45:29.184177 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
5518 23:45:29.187656 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5519 23:45:29.191536 iDelay=203, Bit 8, Center 78 (-13 ~ 170) 184
5520 23:45:29.194155 iDelay=203, Bit 9, Center 74 (-17 ~ 166) 184
5521 23:45:29.197479 iDelay=203, Bit 10, Center 86 (-9 ~ 182) 192
5522 23:45:29.204516 iDelay=203, Bit 11, Center 80 (-9 ~ 170) 180
5523 23:45:29.207107 iDelay=203, Bit 12, Center 92 (-1 ~ 186) 188
5524 23:45:29.211383 iDelay=203, Bit 13, Center 94 (-1 ~ 190) 192
5525 23:45:29.214441 iDelay=203, Bit 14, Center 92 (-1 ~ 186) 188
5526 23:45:29.217909 iDelay=203, Bit 15, Center 92 (-1 ~ 186) 188
5527 23:45:29.220432 ==
5528 23:45:29.220894 Dram Type= 6, Freq= 0, CH_0, rank 1
5529 23:45:29.227131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5530 23:45:29.227689 ==
5531 23:45:29.228060 DQS Delay:
5532 23:45:29.230430 DQS0 = 0, DQS1 = 0
5533 23:45:29.230892 DQM Delay:
5534 23:45:29.233679 DQM0 = 95, DQM1 = 86
5535 23:45:29.234285 DQ Delay:
5536 23:45:29.236820 DQ0 =92, DQ1 =98, DQ2 =90, DQ3 =94
5537 23:45:29.240577 DQ4 =96, DQ5 =86, DQ6 =104, DQ7 =104
5538 23:45:29.243719 DQ8 =78, DQ9 =74, DQ10 =86, DQ11 =80
5539 23:45:29.247102 DQ12 =92, DQ13 =94, DQ14 =92, DQ15 =92
5540 23:45:29.247664
5541 23:45:29.248029
5542 23:45:29.253597 [DQSOSCAuto] RK1, (LSB)MR18= 0x28f9, (MSB)MR19= 0x504, tDQSOscB0 = 424 ps tDQSOscB1 = 409 ps
5543 23:45:29.256776 CH0 RK1: MR19=504, MR18=28F9
5544 23:45:29.263582 CH0_RK1: MR19=0x504, MR18=0x28F9, DQSOSC=409, MR23=63, INC=64, DEC=43
5545 23:45:29.266645 [RxdqsGatingPostProcess] freq 933
5546 23:45:29.273307 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5547 23:45:29.276428 best DQS0 dly(2T, 0.5T) = (0, 10)
5548 23:45:29.276852 best DQS1 dly(2T, 0.5T) = (0, 11)
5549 23:45:29.280157 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5550 23:45:29.283143 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5551 23:45:29.286712 best DQS0 dly(2T, 0.5T) = (0, 10)
5552 23:45:29.290329 best DQS1 dly(2T, 0.5T) = (0, 10)
5553 23:45:29.293167 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5554 23:45:29.296761 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5555 23:45:29.299562 Pre-setting of DQS Precalculation
5556 23:45:29.306361 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5557 23:45:29.306880 ==
5558 23:45:29.309756 Dram Type= 6, Freq= 0, CH_1, rank 0
5559 23:45:29.313048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5560 23:45:29.313624 ==
5561 23:45:29.319624 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5562 23:45:29.325851 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5563 23:45:29.329476 [CA 0] Center 36 (6~67) winsize 62
5564 23:45:29.332798 [CA 1] Center 37 (7~68) winsize 62
5565 23:45:29.335940 [CA 2] Center 34 (4~65) winsize 62
5566 23:45:29.339305 [CA 3] Center 33 (3~64) winsize 62
5567 23:45:29.342246 [CA 4] Center 34 (4~65) winsize 62
5568 23:45:29.345605 [CA 5] Center 33 (3~64) winsize 62
5569 23:45:29.346037
5570 23:45:29.349432 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5571 23:45:29.349945
5572 23:45:29.352280 [CATrainingPosCal] consider 1 rank data
5573 23:45:29.355839 u2DelayCellTimex100 = 270/100 ps
5574 23:45:29.359008 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5575 23:45:29.362344 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5576 23:45:29.365381 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5577 23:45:29.369150 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5578 23:45:29.371832 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5579 23:45:29.375285 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5580 23:45:29.375839
5581 23:45:29.381846 CA PerBit enable=1, Macro0, CA PI delay=33
5582 23:45:29.382416
5583 23:45:29.382760 [CBTSetCACLKResult] CA Dly = 33
5584 23:45:29.384972 CS Dly: 6 (0~37)
5585 23:45:29.385392 ==
5586 23:45:29.388236 Dram Type= 6, Freq= 0, CH_1, rank 1
5587 23:45:29.391673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5588 23:45:29.392095 ==
5589 23:45:29.398186 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5590 23:45:29.405292 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5591 23:45:29.408275 [CA 0] Center 36 (6~67) winsize 62
5592 23:45:29.411580 [CA 1] Center 36 (6~67) winsize 62
5593 23:45:29.415106 [CA 2] Center 34 (4~65) winsize 62
5594 23:45:29.418024 [CA 3] Center 34 (3~65) winsize 63
5595 23:45:29.421131 [CA 4] Center 34 (4~65) winsize 62
5596 23:45:29.424486 [CA 5] Center 33 (3~64) winsize 62
5597 23:45:29.425012
5598 23:45:29.427904 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5599 23:45:29.428329
5600 23:45:29.431077 [CATrainingPosCal] consider 2 rank data
5601 23:45:29.434391 u2DelayCellTimex100 = 270/100 ps
5602 23:45:29.437633 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5603 23:45:29.441469 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5604 23:45:29.444422 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5605 23:45:29.447521 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5606 23:45:29.453756 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5607 23:45:29.457659 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5608 23:45:29.458222
5609 23:45:29.460509 CA PerBit enable=1, Macro0, CA PI delay=33
5610 23:45:29.460951
5611 23:45:29.463926 [CBTSetCACLKResult] CA Dly = 33
5612 23:45:29.464348 CS Dly: 7 (0~39)
5613 23:45:29.464681
5614 23:45:29.467366 ----->DramcWriteLeveling(PI) begin...
5615 23:45:29.470303 ==
5616 23:45:29.470731 Dram Type= 6, Freq= 0, CH_1, rank 0
5617 23:45:29.477523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5618 23:45:29.478138 ==
5619 23:45:29.480386 Write leveling (Byte 0): 28 => 28
5620 23:45:29.483936 Write leveling (Byte 1): 29 => 29
5621 23:45:29.487596 DramcWriteLeveling(PI) end<-----
5622 23:45:29.488064
5623 23:45:29.488535 ==
5624 23:45:29.489976 Dram Type= 6, Freq= 0, CH_1, rank 0
5625 23:45:29.493212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5626 23:45:29.493686 ==
5627 23:45:29.496693 [Gating] SW mode calibration
5628 23:45:29.503118 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5629 23:45:29.509927 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5630 23:45:29.513072 0 14 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5631 23:45:29.516663 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5632 23:45:29.522902 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5633 23:45:29.526108 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5634 23:45:29.529145 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5635 23:45:29.536102 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5636 23:45:29.539316 0 14 24 | B1->B0 | 3434 3131 | 0 0 | (0 1) (0 1)
5637 23:45:29.542553 0 14 28 | B1->B0 | 2d2d 2929 | 0 0 | (0 0) (0 0)
5638 23:45:29.549627 0 15 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5639 23:45:29.552715 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5640 23:45:29.555810 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5641 23:45:29.562728 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5642 23:45:29.565617 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5643 23:45:29.568908 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5644 23:45:29.575807 0 15 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5645 23:45:29.579001 0 15 28 | B1->B0 | 3434 3e3e | 0 0 | (0 0) (0 0)
5646 23:45:29.582073 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5647 23:45:29.588902 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5648 23:45:29.592317 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5649 23:45:29.595592 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5650 23:45:29.602073 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5651 23:45:29.605311 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5652 23:45:29.608993 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5653 23:45:29.615149 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5654 23:45:29.618807 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5655 23:45:29.622267 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5656 23:45:29.628357 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5657 23:45:29.632052 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5658 23:45:29.635218 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5659 23:45:29.641793 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5660 23:45:29.644740 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5661 23:45:29.649062 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5662 23:45:29.654902 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5663 23:45:29.658037 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5664 23:45:29.661499 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5665 23:45:29.667758 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5666 23:45:29.671140 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5667 23:45:29.674387 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5668 23:45:29.681031 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5669 23:45:29.684812 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5670 23:45:29.688292 Total UI for P1: 0, mck2ui 16
5671 23:45:29.691009 best dqsien dly found for B0: ( 1, 2, 24)
5672 23:45:29.694294 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5673 23:45:29.701300 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5674 23:45:29.701832 Total UI for P1: 0, mck2ui 16
5675 23:45:29.707358 best dqsien dly found for B1: ( 1, 2, 30)
5676 23:45:29.710641 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5677 23:45:29.714303 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5678 23:45:29.714762
5679 23:45:29.717392 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5680 23:45:29.720782 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5681 23:45:29.724054 [Gating] SW calibration Done
5682 23:45:29.724471 ==
5683 23:45:29.727351 Dram Type= 6, Freq= 0, CH_1, rank 0
5684 23:45:29.730933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5685 23:45:29.731359 ==
5686 23:45:29.733781 RX Vref Scan: 0
5687 23:45:29.734369
5688 23:45:29.734709 RX Vref 0 -> 0, step: 1
5689 23:45:29.735023
5690 23:45:29.737307 RX Delay -80 -> 252, step: 8
5691 23:45:29.740430 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5692 23:45:29.747368 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5693 23:45:29.750409 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5694 23:45:29.753562 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5695 23:45:29.756753 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5696 23:45:29.760198 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5697 23:45:29.763520 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5698 23:45:29.770238 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5699 23:45:29.773750 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5700 23:45:29.776792 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5701 23:45:29.780006 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5702 23:45:29.786741 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5703 23:45:29.790310 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5704 23:45:29.793339 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5705 23:45:29.796431 iDelay=208, Bit 14, Center 95 (-8 ~ 199) 208
5706 23:45:29.800053 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5707 23:45:29.800530 ==
5708 23:45:29.803154 Dram Type= 6, Freq= 0, CH_1, rank 0
5709 23:45:29.809605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5710 23:45:29.810118 ==
5711 23:45:29.810645 DQS Delay:
5712 23:45:29.810974 DQS0 = 0, DQS1 = 0
5713 23:45:29.813160 DQM Delay:
5714 23:45:29.813681 DQM0 = 101, DQM1 = 91
5715 23:45:29.816410 DQ Delay:
5716 23:45:29.819474 DQ0 =103, DQ1 =99, DQ2 =95, DQ3 =95
5717 23:45:29.823421 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =99
5718 23:45:29.826519 DQ8 =79, DQ9 =83, DQ10 =91, DQ11 =79
5719 23:45:29.830089 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =103
5720 23:45:29.830660
5721 23:45:29.830999
5722 23:45:29.831307 ==
5723 23:45:29.832938 Dram Type= 6, Freq= 0, CH_1, rank 0
5724 23:45:29.836334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5725 23:45:29.836858 ==
5726 23:45:29.837196
5727 23:45:29.837501
5728 23:45:29.839540 TX Vref Scan disable
5729 23:45:29.843078 == TX Byte 0 ==
5730 23:45:29.846305 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5731 23:45:29.849591 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5732 23:45:29.852797 == TX Byte 1 ==
5733 23:45:29.855901 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5734 23:45:29.859883 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5735 23:45:29.860304 ==
5736 23:45:29.862950 Dram Type= 6, Freq= 0, CH_1, rank 0
5737 23:45:29.866017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5738 23:45:29.869075 ==
5739 23:45:29.869496
5740 23:45:29.869825
5741 23:45:29.870132 TX Vref Scan disable
5742 23:45:29.873312 == TX Byte 0 ==
5743 23:45:29.876178 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5744 23:45:29.883157 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5745 23:45:29.883700 == TX Byte 1 ==
5746 23:45:29.885960 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5747 23:45:29.892377 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5748 23:45:29.892889
5749 23:45:29.893226 [DATLAT]
5750 23:45:29.893534 Freq=933, CH1 RK0
5751 23:45:29.893832
5752 23:45:29.896034 DATLAT Default: 0xd
5753 23:45:29.898841 0, 0xFFFF, sum = 0
5754 23:45:29.899354 1, 0xFFFF, sum = 0
5755 23:45:29.902023 2, 0xFFFF, sum = 0
5756 23:45:29.902624 3, 0xFFFF, sum = 0
5757 23:45:29.905724 4, 0xFFFF, sum = 0
5758 23:45:29.906145 5, 0xFFFF, sum = 0
5759 23:45:29.908990 6, 0xFFFF, sum = 0
5760 23:45:29.909541 7, 0xFFFF, sum = 0
5761 23:45:29.912374 8, 0xFFFF, sum = 0
5762 23:45:29.912906 9, 0xFFFF, sum = 0
5763 23:45:29.916177 10, 0x0, sum = 1
5764 23:45:29.916711 11, 0x0, sum = 2
5765 23:45:29.918824 12, 0x0, sum = 3
5766 23:45:29.919250 13, 0x0, sum = 4
5767 23:45:29.922500 best_step = 11
5768 23:45:29.923029
5769 23:45:29.923364 ==
5770 23:45:29.926140 Dram Type= 6, Freq= 0, CH_1, rank 0
5771 23:45:29.928959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5772 23:45:29.929488 ==
5773 23:45:29.929825 RX Vref Scan: 1
5774 23:45:29.930138
5775 23:45:29.931968 RX Vref 0 -> 0, step: 1
5776 23:45:29.932385
5777 23:45:29.936036 RX Delay -61 -> 252, step: 4
5778 23:45:29.936558
5779 23:45:29.938369 Set Vref, RX VrefLevel [Byte0]: 49
5780 23:45:29.941857 [Byte1]: 54
5781 23:45:29.945768
5782 23:45:29.946337 Final RX Vref Byte 0 = 49 to rank0
5783 23:45:29.948919 Final RX Vref Byte 1 = 54 to rank0
5784 23:45:29.951941 Final RX Vref Byte 0 = 49 to rank1
5785 23:45:29.955396 Final RX Vref Byte 1 = 54 to rank1==
5786 23:45:29.958714 Dram Type= 6, Freq= 0, CH_1, rank 0
5787 23:45:29.965182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5788 23:45:29.965699 ==
5789 23:45:29.966035 DQS Delay:
5790 23:45:29.966385 DQS0 = 0, DQS1 = 0
5791 23:45:29.968421 DQM Delay:
5792 23:45:29.968837 DQM0 = 101, DQM1 = 93
5793 23:45:29.971975 DQ Delay:
5794 23:45:29.975355 DQ0 =106, DQ1 =96, DQ2 =92, DQ3 =98
5795 23:45:29.978335 DQ4 =98, DQ5 =112, DQ6 =108, DQ7 =98
5796 23:45:29.981952 DQ8 =80, DQ9 =84, DQ10 =94, DQ11 =84
5797 23:45:29.985779 DQ12 =100, DQ13 =98, DQ14 =100, DQ15 =104
5798 23:45:29.986354
5799 23:45:29.986700
5800 23:45:29.991649 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d0d, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 412 ps
5801 23:45:29.994853 CH1 RK0: MR19=505, MR18=1D0D
5802 23:45:30.001677 CH1_RK0: MR19=0x505, MR18=0x1D0D, DQSOSC=412, MR23=63, INC=63, DEC=42
5803 23:45:30.002291
5804 23:45:30.005442 ----->DramcWriteLeveling(PI) begin...
5805 23:45:30.005978 ==
5806 23:45:30.008441 Dram Type= 6, Freq= 0, CH_1, rank 1
5807 23:45:30.011723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5808 23:45:30.012249 ==
5809 23:45:30.015072 Write leveling (Byte 0): 27 => 27
5810 23:45:30.018626 Write leveling (Byte 1): 27 => 27
5811 23:45:30.021544 DramcWriteLeveling(PI) end<-----
5812 23:45:30.022116
5813 23:45:30.022627 ==
5814 23:45:30.024949 Dram Type= 6, Freq= 0, CH_1, rank 1
5815 23:45:30.031413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5816 23:45:30.031881 ==
5817 23:45:30.032252 [Gating] SW mode calibration
5818 23:45:30.041846 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5819 23:45:30.044688 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5820 23:45:30.047500 0 14 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5821 23:45:30.054858 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5822 23:45:30.058394 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5823 23:45:30.063949 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5824 23:45:30.067507 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5825 23:45:30.070899 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5826 23:45:30.074073 0 14 24 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5827 23:45:30.080991 0 14 28 | B1->B0 | 2c2c 3030 | 0 0 | (1 0) (1 0)
5828 23:45:30.084733 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5829 23:45:30.087300 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5830 23:45:30.093775 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5831 23:45:30.098418 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5832 23:45:30.103515 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5833 23:45:30.107069 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5834 23:45:30.110401 0 15 24 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
5835 23:45:30.117375 0 15 28 | B1->B0 | 3f3f 3636 | 0 0 | (0 0) (0 0)
5836 23:45:30.120474 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5837 23:45:30.123874 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5838 23:45:30.129860 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5839 23:45:30.133563 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5840 23:45:30.136757 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5841 23:45:30.143134 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5842 23:45:30.146739 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5843 23:45:30.150096 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5844 23:45:30.156526 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5845 23:45:30.159509 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5846 23:45:30.163097 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5847 23:45:30.169601 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5848 23:45:30.173149 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5849 23:45:30.176642 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5850 23:45:30.183144 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5851 23:45:30.186307 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5852 23:45:30.189415 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5853 23:45:30.196658 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5854 23:45:30.199282 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5855 23:45:30.202722 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5856 23:45:30.206604 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5857 23:45:30.212984 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5858 23:45:30.216130 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5859 23:45:30.219543 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5860 23:45:30.226074 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5861 23:45:30.229911 Total UI for P1: 0, mck2ui 16
5862 23:45:30.232385 best dqsien dly found for B0: ( 1, 2, 28)
5863 23:45:30.235538 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5864 23:45:30.239146 Total UI for P1: 0, mck2ui 16
5865 23:45:30.242494 best dqsien dly found for B1: ( 1, 2, 28)
5866 23:45:30.245823 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5867 23:45:30.249495 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5868 23:45:30.250078
5869 23:45:30.252015 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5870 23:45:30.258771 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5871 23:45:30.259340 [Gating] SW calibration Done
5872 23:45:30.259712 ==
5873 23:45:30.262228 Dram Type= 6, Freq= 0, CH_1, rank 1
5874 23:45:30.268646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5875 23:45:30.269115 ==
5876 23:45:30.269484 RX Vref Scan: 0
5877 23:45:30.269825
5878 23:45:30.271865 RX Vref 0 -> 0, step: 1
5879 23:45:30.272330
5880 23:45:30.275490 RX Delay -80 -> 252, step: 8
5881 23:45:30.278457 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5882 23:45:30.282109 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5883 23:45:30.285391 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5884 23:45:30.288629 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5885 23:45:30.294761 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5886 23:45:30.298524 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5887 23:45:30.301739 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5888 23:45:30.304738 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5889 23:45:30.307910 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5890 23:45:30.315794 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5891 23:45:30.318071 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5892 23:45:30.321353 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5893 23:45:30.324454 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5894 23:45:30.328149 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5895 23:45:30.334729 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5896 23:45:30.337592 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5897 23:45:30.338155 ==
5898 23:45:30.341460 Dram Type= 6, Freq= 0, CH_1, rank 1
5899 23:45:30.344396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5900 23:45:30.345072 ==
5901 23:45:30.345451 DQS Delay:
5902 23:45:30.347440 DQS0 = 0, DQS1 = 0
5903 23:45:30.347904 DQM Delay:
5904 23:45:30.351212 DQM0 = 99, DQM1 = 91
5905 23:45:30.351673 DQ Delay:
5906 23:45:30.354272 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =95
5907 23:45:30.357807 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5908 23:45:30.360750 DQ8 =79, DQ9 =79, DQ10 =95, DQ11 =83
5909 23:45:30.364341 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =99
5910 23:45:30.364897
5911 23:45:30.365266
5912 23:45:30.365605 ==
5913 23:45:30.367352 Dram Type= 6, Freq= 0, CH_1, rank 1
5914 23:45:30.374074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5915 23:45:30.374686 ==
5916 23:45:30.375057
5917 23:45:30.375395
5918 23:45:30.375717 TX Vref Scan disable
5919 23:45:30.377370 == TX Byte 0 ==
5920 23:45:30.380680 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5921 23:45:30.384076 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5922 23:45:30.387279 == TX Byte 1 ==
5923 23:45:30.390877 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5924 23:45:30.397597 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5925 23:45:30.398126 ==
5926 23:45:30.401150 Dram Type= 6, Freq= 0, CH_1, rank 1
5927 23:45:30.404088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5928 23:45:30.404627 ==
5929 23:45:30.405071
5930 23:45:30.405474
5931 23:45:30.407551 TX Vref Scan disable
5932 23:45:30.408077 == TX Byte 0 ==
5933 23:45:30.413827 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5934 23:45:30.417272 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5935 23:45:30.420634 == TX Byte 1 ==
5936 23:45:30.423760 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5937 23:45:30.426995 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5938 23:45:30.427419
5939 23:45:30.427752 [DATLAT]
5940 23:45:30.429947 Freq=933, CH1 RK1
5941 23:45:30.430416
5942 23:45:30.433797 DATLAT Default: 0xb
5943 23:45:30.434256 0, 0xFFFF, sum = 0
5944 23:45:30.436896 1, 0xFFFF, sum = 0
5945 23:45:30.437418 2, 0xFFFF, sum = 0
5946 23:45:30.440132 3, 0xFFFF, sum = 0
5947 23:45:30.440559 4, 0xFFFF, sum = 0
5948 23:45:30.443242 5, 0xFFFF, sum = 0
5949 23:45:30.443774 6, 0xFFFF, sum = 0
5950 23:45:30.446564 7, 0xFFFF, sum = 0
5951 23:45:30.447117 8, 0xFFFF, sum = 0
5952 23:45:30.450509 9, 0xFFFF, sum = 0
5953 23:45:30.451071 10, 0x0, sum = 1
5954 23:45:30.453096 11, 0x0, sum = 2
5955 23:45:30.453664 12, 0x0, sum = 3
5956 23:45:30.456649 13, 0x0, sum = 4
5957 23:45:30.457212 best_step = 11
5958 23:45:30.457579
5959 23:45:30.457921 ==
5960 23:45:30.459570 Dram Type= 6, Freq= 0, CH_1, rank 1
5961 23:45:30.463290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5962 23:45:30.466502 ==
5963 23:45:30.467061 RX Vref Scan: 0
5964 23:45:30.467435
5965 23:45:30.469489 RX Vref 0 -> 0, step: 1
5966 23:45:30.469950
5967 23:45:30.472900 RX Delay -61 -> 252, step: 4
5968 23:45:30.476389 iDelay=207, Bit 0, Center 106 (19 ~ 194) 176
5969 23:45:30.479493 iDelay=207, Bit 1, Center 94 (7 ~ 182) 176
5970 23:45:30.486383 iDelay=207, Bit 2, Center 90 (3 ~ 178) 176
5971 23:45:30.489691 iDelay=207, Bit 3, Center 96 (11 ~ 182) 172
5972 23:45:30.492758 iDelay=207, Bit 4, Center 100 (11 ~ 190) 180
5973 23:45:30.496265 iDelay=207, Bit 5, Center 110 (23 ~ 198) 176
5974 23:45:30.499424 iDelay=207, Bit 6, Center 114 (23 ~ 206) 184
5975 23:45:30.502452 iDelay=207, Bit 7, Center 96 (3 ~ 190) 188
5976 23:45:30.509272 iDelay=207, Bit 8, Center 80 (-13 ~ 174) 188
5977 23:45:30.512513 iDelay=207, Bit 9, Center 82 (-9 ~ 174) 184
5978 23:45:30.516093 iDelay=207, Bit 10, Center 92 (-1 ~ 186) 188
5979 23:45:30.519657 iDelay=207, Bit 11, Center 84 (-5 ~ 174) 180
5980 23:45:30.522505 iDelay=207, Bit 12, Center 100 (7 ~ 194) 188
5981 23:45:30.528834 iDelay=207, Bit 13, Center 98 (7 ~ 190) 184
5982 23:45:30.532073 iDelay=207, Bit 14, Center 98 (7 ~ 190) 184
5983 23:45:30.535663 iDelay=207, Bit 15, Center 102 (11 ~ 194) 184
5984 23:45:30.536176 ==
5985 23:45:30.538836 Dram Type= 6, Freq= 0, CH_1, rank 1
5986 23:45:30.542076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5987 23:45:30.542616 ==
5988 23:45:30.545274 DQS Delay:
5989 23:45:30.545692 DQS0 = 0, DQS1 = 0
5990 23:45:30.548873 DQM Delay:
5991 23:45:30.549390 DQM0 = 100, DQM1 = 92
5992 23:45:30.549730 DQ Delay:
5993 23:45:30.552067 DQ0 =106, DQ1 =94, DQ2 =90, DQ3 =96
5994 23:45:30.555655 DQ4 =100, DQ5 =110, DQ6 =114, DQ7 =96
5995 23:45:30.558667 DQ8 =80, DQ9 =82, DQ10 =92, DQ11 =84
5996 23:45:30.565574 DQ12 =100, DQ13 =98, DQ14 =98, DQ15 =102
5997 23:45:30.566102
5998 23:45:30.566475
5999 23:45:30.571959 [DQSOSCAuto] RK1, (LSB)MR18= 0xa03, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 418 ps
6000 23:45:30.575058 CH1 RK1: MR19=505, MR18=A03
6001 23:45:30.581850 CH1_RK1: MR19=0x505, MR18=0xA03, DQSOSC=418, MR23=63, INC=62, DEC=41
6002 23:45:30.584984 [RxdqsGatingPostProcess] freq 933
6003 23:45:30.588191 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6004 23:45:30.591802 best DQS0 dly(2T, 0.5T) = (0, 10)
6005 23:45:30.594852 best DQS1 dly(2T, 0.5T) = (0, 10)
6006 23:45:30.598512 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6007 23:45:30.601656 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6008 23:45:30.605004 best DQS0 dly(2T, 0.5T) = (0, 10)
6009 23:45:30.608504 best DQS1 dly(2T, 0.5T) = (0, 10)
6010 23:45:30.611851 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6011 23:45:30.614744 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6012 23:45:30.618195 Pre-setting of DQS Precalculation
6013 23:45:30.621591 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6014 23:45:30.627974 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6015 23:45:30.637962 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6016 23:45:30.638571
6017 23:45:30.639107
6018 23:45:30.641607 [Calibration Summary] 1866 Mbps
6019 23:45:30.642275 CH 0, Rank 0
6020 23:45:30.644882 SW Impedance : PASS
6021 23:45:30.645485 DUTY Scan : NO K
6022 23:45:30.647655 ZQ Calibration : PASS
6023 23:45:30.650978 Jitter Meter : NO K
6024 23:45:30.651549 CBT Training : PASS
6025 23:45:30.655256 Write leveling : PASS
6026 23:45:30.658149 RX DQS gating : PASS
6027 23:45:30.658757 RX DQ/DQS(RDDQC) : PASS
6028 23:45:30.661067 TX DQ/DQS : PASS
6029 23:45:30.664419 RX DATLAT : PASS
6030 23:45:30.664890 RX DQ/DQS(Engine): PASS
6031 23:45:30.667581 TX OE : NO K
6032 23:45:30.668007 All Pass.
6033 23:45:30.668439
6034 23:45:30.671019 CH 0, Rank 1
6035 23:45:30.671446 SW Impedance : PASS
6036 23:45:30.674483 DUTY Scan : NO K
6037 23:45:30.674909 ZQ Calibration : PASS
6038 23:45:30.677578 Jitter Meter : NO K
6039 23:45:30.680857 CBT Training : PASS
6040 23:45:30.681397 Write leveling : PASS
6041 23:45:30.684336 RX DQS gating : PASS
6042 23:45:30.687472 RX DQ/DQS(RDDQC) : PASS
6043 23:45:30.687914 TX DQ/DQS : PASS
6044 23:45:30.690795 RX DATLAT : PASS
6045 23:45:30.694150 RX DQ/DQS(Engine): PASS
6046 23:45:30.694608 TX OE : NO K
6047 23:45:30.697719 All Pass.
6048 23:45:30.698338
6049 23:45:30.698783 CH 1, Rank 0
6050 23:45:30.700907 SW Impedance : PASS
6051 23:45:30.701340 DUTY Scan : NO K
6052 23:45:30.703972 ZQ Calibration : PASS
6053 23:45:30.707098 Jitter Meter : NO K
6054 23:45:30.707528 CBT Training : PASS
6055 23:45:30.710602 Write leveling : PASS
6056 23:45:30.713714 RX DQS gating : PASS
6057 23:45:30.714139 RX DQ/DQS(RDDQC) : PASS
6058 23:45:30.717179 TX DQ/DQS : PASS
6059 23:45:30.720592 RX DATLAT : PASS
6060 23:45:30.721118 RX DQ/DQS(Engine): PASS
6061 23:45:30.723799 TX OE : NO K
6062 23:45:30.724233 All Pass.
6063 23:45:30.724661
6064 23:45:30.727239 CH 1, Rank 1
6065 23:45:30.727663 SW Impedance : PASS
6066 23:45:30.730009 DUTY Scan : NO K
6067 23:45:30.733431 ZQ Calibration : PASS
6068 23:45:30.733907 Jitter Meter : NO K
6069 23:45:30.737387 CBT Training : PASS
6070 23:45:30.739978 Write leveling : PASS
6071 23:45:30.740403 RX DQS gating : PASS
6072 23:45:30.743819 RX DQ/DQS(RDDQC) : PASS
6073 23:45:30.744339 TX DQ/DQS : PASS
6074 23:45:30.747331 RX DATLAT : PASS
6075 23:45:30.750321 RX DQ/DQS(Engine): PASS
6076 23:45:30.750939 TX OE : NO K
6077 23:45:30.753270 All Pass.
6078 23:45:30.753846
6079 23:45:30.754271 DramC Write-DBI off
6080 23:45:30.756673 PER_BANK_REFRESH: Hybrid Mode
6081 23:45:30.759969 TX_TRACKING: ON
6082 23:45:30.766728 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6083 23:45:30.769660 [FAST_K] Save calibration result to emmc
6084 23:45:30.776122 dramc_set_vcore_voltage set vcore to 650000
6085 23:45:30.776545 Read voltage for 400, 6
6086 23:45:30.779565 Vio18 = 0
6087 23:45:30.779999 Vcore = 650000
6088 23:45:30.780329 Vdram = 0
6089 23:45:30.780641 Vddq = 0
6090 23:45:30.783057 Vmddr = 0
6091 23:45:30.786743 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6092 23:45:30.792961 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6093 23:45:30.796347 MEM_TYPE=3, freq_sel=20
6094 23:45:30.796769 sv_algorithm_assistance_LP4_800
6095 23:45:30.802963 ============ PULL DRAM RESETB DOWN ============
6096 23:45:30.805721 ========== PULL DRAM RESETB DOWN end =========
6097 23:45:30.809344 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6098 23:45:30.812739 ===================================
6099 23:45:30.815615 LPDDR4 DRAM CONFIGURATION
6100 23:45:30.820890 ===================================
6101 23:45:30.822411 EX_ROW_EN[0] = 0x0
6102 23:45:30.822941 EX_ROW_EN[1] = 0x0
6103 23:45:30.825821 LP4Y_EN = 0x0
6104 23:45:30.826285 WORK_FSP = 0x0
6105 23:45:30.829065 WL = 0x2
6106 23:45:30.829483 RL = 0x2
6107 23:45:30.832560 BL = 0x2
6108 23:45:30.832986 RPST = 0x0
6109 23:45:30.835587 RD_PRE = 0x0
6110 23:45:30.836016 WR_PRE = 0x1
6111 23:45:30.839322 WR_PST = 0x0
6112 23:45:30.842554 DBI_WR = 0x0
6113 23:45:30.842983 DBI_RD = 0x0
6114 23:45:30.845526 OTF = 0x1
6115 23:45:30.849121 ===================================
6116 23:45:30.852128 ===================================
6117 23:45:30.852576 ANA top config
6118 23:45:30.855244 ===================================
6119 23:45:30.858545 DLL_ASYNC_EN = 0
6120 23:45:30.861971 ALL_SLAVE_EN = 1
6121 23:45:30.862507 NEW_RANK_MODE = 1
6122 23:45:30.865380 DLL_IDLE_MODE = 1
6123 23:45:30.868989 LP45_APHY_COMB_EN = 1
6124 23:45:30.872111 TX_ODT_DIS = 1
6125 23:45:30.875212 NEW_8X_MODE = 1
6126 23:45:30.875637 ===================================
6127 23:45:30.878583 ===================================
6128 23:45:30.881654 data_rate = 800
6129 23:45:30.885645 CKR = 1
6130 23:45:30.888633 DQ_P2S_RATIO = 4
6131 23:45:30.891373 ===================================
6132 23:45:30.894664 CA_P2S_RATIO = 4
6133 23:45:30.898418 DQ_CA_OPEN = 0
6134 23:45:30.901507 DQ_SEMI_OPEN = 1
6135 23:45:30.902028 CA_SEMI_OPEN = 1
6136 23:45:30.904832 CA_FULL_RATE = 0
6137 23:45:30.907939 DQ_CKDIV4_EN = 0
6138 23:45:30.911084 CA_CKDIV4_EN = 1
6139 23:45:30.914642 CA_PREDIV_EN = 0
6140 23:45:30.917968 PH8_DLY = 0
6141 23:45:30.918430 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6142 23:45:30.921326 DQ_AAMCK_DIV = 0
6143 23:45:30.924725 CA_AAMCK_DIV = 0
6144 23:45:30.927638 CA_ADMCK_DIV = 4
6145 23:45:30.930764 DQ_TRACK_CA_EN = 0
6146 23:45:30.934031 CA_PICK = 800
6147 23:45:30.937746 CA_MCKIO = 400
6148 23:45:30.938415 MCKIO_SEMI = 400
6149 23:45:30.941055 PLL_FREQ = 3016
6150 23:45:30.944297 DQ_UI_PI_RATIO = 32
6151 23:45:30.947748 CA_UI_PI_RATIO = 32
6152 23:45:30.950565 ===================================
6153 23:45:30.954723 ===================================
6154 23:45:30.957842 memory_type:LPDDR4
6155 23:45:30.958331 GP_NUM : 10
6156 23:45:30.960643 SRAM_EN : 1
6157 23:45:30.964195 MD32_EN : 0
6158 23:45:30.967756 ===================================
6159 23:45:30.968334 [ANA_INIT] >>>>>>>>>>>>>>
6160 23:45:30.970702 <<<<<< [CONFIGURE PHASE]: ANA_TX
6161 23:45:30.974079 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6162 23:45:30.977601 ===================================
6163 23:45:30.980871 data_rate = 800,PCW = 0X7400
6164 23:45:30.984478 ===================================
6165 23:45:30.987503 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6166 23:45:30.993740 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6167 23:45:31.003999 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6168 23:45:31.010590 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6169 23:45:31.014072 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6170 23:45:31.017074 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6171 23:45:31.017658 [ANA_INIT] flow start
6172 23:45:31.020506 [ANA_INIT] PLL >>>>>>>>
6173 23:45:31.023705 [ANA_INIT] PLL <<<<<<<<
6174 23:45:31.024201 [ANA_INIT] MIDPI >>>>>>>>
6175 23:45:31.027334 [ANA_INIT] MIDPI <<<<<<<<
6176 23:45:31.030128 [ANA_INIT] DLL >>>>>>>>
6177 23:45:31.030642 [ANA_INIT] flow end
6178 23:45:31.036423 ============ LP4 DIFF to SE enter ============
6179 23:45:31.039763 ============ LP4 DIFF to SE exit ============
6180 23:45:31.043444 [ANA_INIT] <<<<<<<<<<<<<
6181 23:45:31.046378 [Flow] Enable top DCM control >>>>>
6182 23:45:31.049769 [Flow] Enable top DCM control <<<<<
6183 23:45:31.053489 Enable DLL master slave shuffle
6184 23:45:31.056564 ==============================================================
6185 23:45:31.059950 Gating Mode config
6186 23:45:31.063197 ==============================================================
6187 23:45:31.066624 Config description:
6188 23:45:31.076848 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6189 23:45:31.083024 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6190 23:45:31.086267 SELPH_MODE 0: By rank 1: By Phase
6191 23:45:31.093020 ==============================================================
6192 23:45:31.097295 GAT_TRACK_EN = 0
6193 23:45:31.099504 RX_GATING_MODE = 2
6194 23:45:31.103402 RX_GATING_TRACK_MODE = 2
6195 23:45:31.106601 SELPH_MODE = 1
6196 23:45:31.109786 PICG_EARLY_EN = 1
6197 23:45:31.112650 VALID_LAT_VALUE = 1
6198 23:45:31.116356 ==============================================================
6199 23:45:31.119079 Enter into Gating configuration >>>>
6200 23:45:31.122914 Exit from Gating configuration <<<<
6201 23:45:31.126504 Enter into DVFS_PRE_config >>>>>
6202 23:45:31.138936 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6203 23:45:31.139503 Exit from DVFS_PRE_config <<<<<
6204 23:45:31.142597 Enter into PICG configuration >>>>
6205 23:45:31.145952 Exit from PICG configuration <<<<
6206 23:45:31.149327 [RX_INPUT] configuration >>>>>
6207 23:45:31.152695 [RX_INPUT] configuration <<<<<
6208 23:45:31.158957 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6209 23:45:31.162319 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6210 23:45:31.169157 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6211 23:45:31.175189 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6212 23:45:31.181811 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6213 23:45:31.188772 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6214 23:45:31.192080 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6215 23:45:31.195110 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6216 23:45:31.198580 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6217 23:45:31.204969 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6218 23:45:31.208582 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6219 23:45:31.212037 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6220 23:45:31.215259 ===================================
6221 23:45:31.218615 LPDDR4 DRAM CONFIGURATION
6222 23:45:31.221840 ===================================
6223 23:45:31.225409 EX_ROW_EN[0] = 0x0
6224 23:45:31.225834 EX_ROW_EN[1] = 0x0
6225 23:45:31.227757 LP4Y_EN = 0x0
6226 23:45:31.228203 WORK_FSP = 0x0
6227 23:45:31.231496 WL = 0x2
6228 23:45:31.232006 RL = 0x2
6229 23:45:31.234626 BL = 0x2
6230 23:45:31.235039 RPST = 0x0
6231 23:45:31.238292 RD_PRE = 0x0
6232 23:45:31.238812 WR_PRE = 0x1
6233 23:45:31.241505 WR_PST = 0x0
6234 23:45:31.241920 DBI_WR = 0x0
6235 23:45:31.244577 DBI_RD = 0x0
6236 23:45:31.247887 OTF = 0x1
6237 23:45:31.251154 ===================================
6238 23:45:31.255114 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6239 23:45:31.257519 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6240 23:45:31.261239 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6241 23:45:31.264314 ===================================
6242 23:45:31.267686 LPDDR4 DRAM CONFIGURATION
6243 23:45:31.271123 ===================================
6244 23:45:31.274092 EX_ROW_EN[0] = 0x10
6245 23:45:31.274688 EX_ROW_EN[1] = 0x0
6246 23:45:31.277357 LP4Y_EN = 0x0
6247 23:45:31.277772 WORK_FSP = 0x0
6248 23:45:31.281147 WL = 0x2
6249 23:45:31.281614 RL = 0x2
6250 23:45:31.284390 BL = 0x2
6251 23:45:31.284806 RPST = 0x0
6252 23:45:31.288063 RD_PRE = 0x0
6253 23:45:31.288576 WR_PRE = 0x1
6254 23:45:31.290892 WR_PST = 0x0
6255 23:45:31.291308 DBI_WR = 0x0
6256 23:45:31.294211 DBI_RD = 0x0
6257 23:45:31.297685 OTF = 0x1
6258 23:45:31.300488 ===================================
6259 23:45:31.304098 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6260 23:45:31.309764 nWR fixed to 30
6261 23:45:31.312683 [ModeRegInit_LP4] CH0 RK0
6262 23:45:31.313226 [ModeRegInit_LP4] CH0 RK1
6263 23:45:31.315358 [ModeRegInit_LP4] CH1 RK0
6264 23:45:31.318660 [ModeRegInit_LP4] CH1 RK1
6265 23:45:31.319096 match AC timing 19
6266 23:45:31.325802 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6267 23:45:31.328762 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6268 23:45:31.332154 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6269 23:45:31.338957 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6270 23:45:31.341983 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6271 23:45:31.342482 ==
6272 23:45:31.345710 Dram Type= 6, Freq= 0, CH_0, rank 0
6273 23:45:31.348802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6274 23:45:31.349363 ==
6275 23:45:31.355161 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6276 23:45:31.361921 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6277 23:45:31.364981 [CA 0] Center 36 (8~64) winsize 57
6278 23:45:31.368496 [CA 1] Center 36 (8~64) winsize 57
6279 23:45:31.371869 [CA 2] Center 36 (8~64) winsize 57
6280 23:45:31.374979 [CA 3] Center 36 (8~64) winsize 57
6281 23:45:31.378021 [CA 4] Center 36 (8~64) winsize 57
6282 23:45:31.381442 [CA 5] Center 36 (8~64) winsize 57
6283 23:45:31.381907
6284 23:45:31.384522 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6285 23:45:31.385179
6286 23:45:31.387835 [CATrainingPosCal] consider 1 rank data
6287 23:45:31.391372 u2DelayCellTimex100 = 270/100 ps
6288 23:45:31.394521 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6289 23:45:31.397999 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6290 23:45:31.401402 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6291 23:45:31.404623 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6292 23:45:31.407915 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6293 23:45:31.411728 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6294 23:45:31.412304
6295 23:45:31.417654 CA PerBit enable=1, Macro0, CA PI delay=36
6296 23:45:31.418119
6297 23:45:31.418629 [CBTSetCACLKResult] CA Dly = 36
6298 23:45:31.421176 CS Dly: 1 (0~32)
6299 23:45:31.421594 ==
6300 23:45:31.424942 Dram Type= 6, Freq= 0, CH_0, rank 1
6301 23:45:31.427932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6302 23:45:31.428358 ==
6303 23:45:31.434511 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6304 23:45:31.440854 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6305 23:45:31.444621 [CA 0] Center 36 (8~64) winsize 57
6306 23:45:31.447766 [CA 1] Center 36 (8~64) winsize 57
6307 23:45:31.450840 [CA 2] Center 36 (8~64) winsize 57
6308 23:45:31.454528 [CA 3] Center 36 (8~64) winsize 57
6309 23:45:31.455067 [CA 4] Center 36 (8~64) winsize 57
6310 23:45:31.457767 [CA 5] Center 36 (8~64) winsize 57
6311 23:45:31.458231
6312 23:45:31.464063 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6313 23:45:31.464591
6314 23:45:31.467762 [CATrainingPosCal] consider 2 rank data
6315 23:45:31.470981 u2DelayCellTimex100 = 270/100 ps
6316 23:45:31.473655 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6317 23:45:31.477295 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6318 23:45:31.480393 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6319 23:45:31.483684 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6320 23:45:31.487013 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6321 23:45:31.490344 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6322 23:45:31.490777
6323 23:45:31.493859 CA PerBit enable=1, Macro0, CA PI delay=36
6324 23:45:31.494334
6325 23:45:31.496945 [CBTSetCACLKResult] CA Dly = 36
6326 23:45:31.500460 CS Dly: 1 (0~32)
6327 23:45:31.500897
6328 23:45:31.503989 ----->DramcWriteLeveling(PI) begin...
6329 23:45:31.504556 ==
6330 23:45:31.506947 Dram Type= 6, Freq= 0, CH_0, rank 0
6331 23:45:31.510136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6332 23:45:31.510731 ==
6333 23:45:31.513396 Write leveling (Byte 0): 40 => 8
6334 23:45:31.517096 Write leveling (Byte 1): 32 => 0
6335 23:45:31.520117 DramcWriteLeveling(PI) end<-----
6336 23:45:31.520542
6337 23:45:31.520876 ==
6338 23:45:31.523175 Dram Type= 6, Freq= 0, CH_0, rank 0
6339 23:45:31.526211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6340 23:45:31.526503 ==
6341 23:45:31.529571 [Gating] SW mode calibration
6342 23:45:31.536321 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6343 23:45:31.543216 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6344 23:45:31.546482 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6345 23:45:31.552908 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6346 23:45:31.556344 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6347 23:45:31.560258 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6348 23:45:31.566198 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6349 23:45:31.569571 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6350 23:45:31.572647 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6351 23:45:31.579476 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6352 23:45:31.582653 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6353 23:45:31.586251 Total UI for P1: 0, mck2ui 16
6354 23:45:31.589662 best dqsien dly found for B0: ( 0, 14, 24)
6355 23:45:31.592846 Total UI for P1: 0, mck2ui 16
6356 23:45:31.596462 best dqsien dly found for B1: ( 0, 14, 24)
6357 23:45:31.599730 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6358 23:45:31.602880 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6359 23:45:31.603407
6360 23:45:31.606265 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6361 23:45:31.608953 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6362 23:45:31.612827 [Gating] SW calibration Done
6363 23:45:31.613346 ==
6364 23:45:31.616199 Dram Type= 6, Freq= 0, CH_0, rank 0
6365 23:45:31.619364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6366 23:45:31.622356 ==
6367 23:45:31.622774 RX Vref Scan: 0
6368 23:45:31.623105
6369 23:45:31.626199 RX Vref 0 -> 0, step: 1
6370 23:45:31.626723
6371 23:45:31.629009 RX Delay -410 -> 252, step: 16
6372 23:45:31.632929 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6373 23:45:31.635736 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6374 23:45:31.642026 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6375 23:45:31.645809 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6376 23:45:31.648448 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6377 23:45:31.652184 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6378 23:45:31.658282 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6379 23:45:31.661621 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6380 23:45:31.665036 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6381 23:45:31.668141 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6382 23:45:31.675030 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6383 23:45:31.678124 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6384 23:45:31.681286 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6385 23:45:31.684778 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6386 23:45:31.691905 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6387 23:45:31.695114 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6388 23:45:31.695656 ==
6389 23:45:31.698089 Dram Type= 6, Freq= 0, CH_0, rank 0
6390 23:45:31.701263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6391 23:45:31.701809 ==
6392 23:45:31.704995 DQS Delay:
6393 23:45:31.705533 DQS0 = 43, DQS1 = 59
6394 23:45:31.707997 DQM Delay:
6395 23:45:31.708428 DQM0 = 10, DQM1 = 11
6396 23:45:31.711036 DQ Delay:
6397 23:45:31.711469 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6398 23:45:31.714251 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6399 23:45:31.717989 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6400 23:45:31.720875 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6401 23:45:31.721309
6402 23:45:31.721749
6403 23:45:31.722157 ==
6404 23:45:31.724331 Dram Type= 6, Freq= 0, CH_0, rank 0
6405 23:45:31.731347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6406 23:45:31.731784 ==
6407 23:45:31.732221
6408 23:45:31.732634
6409 23:45:31.733036 TX Vref Scan disable
6410 23:45:31.733909 == TX Byte 0 ==
6411 23:45:31.737456 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6412 23:45:31.740847 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6413 23:45:31.744227 == TX Byte 1 ==
6414 23:45:31.747270 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6415 23:45:31.750762 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6416 23:45:31.754385 ==
6417 23:45:31.757622 Dram Type= 6, Freq= 0, CH_0, rank 0
6418 23:45:31.760651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6419 23:45:31.761166 ==
6420 23:45:31.761498
6421 23:45:31.761802
6422 23:45:31.763784 TX Vref Scan disable
6423 23:45:31.764199 == TX Byte 0 ==
6424 23:45:31.767140 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6425 23:45:31.773744 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6426 23:45:31.774308 == TX Byte 1 ==
6427 23:45:31.777094 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6428 23:45:31.783744 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6429 23:45:31.784264
6430 23:45:31.784595 [DATLAT]
6431 23:45:31.784903 Freq=400, CH0 RK0
6432 23:45:31.787124
6433 23:45:31.787540 DATLAT Default: 0xf
6434 23:45:31.790639 0, 0xFFFF, sum = 0
6435 23:45:31.791069 1, 0xFFFF, sum = 0
6436 23:45:31.793637 2, 0xFFFF, sum = 0
6437 23:45:31.794062 3, 0xFFFF, sum = 0
6438 23:45:31.797484 4, 0xFFFF, sum = 0
6439 23:45:31.798019 5, 0xFFFF, sum = 0
6440 23:45:31.800531 6, 0xFFFF, sum = 0
6441 23:45:31.800989 7, 0xFFFF, sum = 0
6442 23:45:31.803886 8, 0xFFFF, sum = 0
6443 23:45:31.804439 9, 0xFFFF, sum = 0
6444 23:45:31.807094 10, 0xFFFF, sum = 0
6445 23:45:31.807522 11, 0xFFFF, sum = 0
6446 23:45:31.810891 12, 0xFFFF, sum = 0
6447 23:45:31.811420 13, 0x0, sum = 1
6448 23:45:31.814130 14, 0x0, sum = 2
6449 23:45:31.814701 15, 0x0, sum = 3
6450 23:45:31.816852 16, 0x0, sum = 4
6451 23:45:31.817276 best_step = 14
6452 23:45:31.817606
6453 23:45:31.817913 ==
6454 23:45:31.819971 Dram Type= 6, Freq= 0, CH_0, rank 0
6455 23:45:31.826756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6456 23:45:31.827273 ==
6457 23:45:31.827610 RX Vref Scan: 1
6458 23:45:31.827920
6459 23:45:31.830218 RX Vref 0 -> 0, step: 1
6460 23:45:31.830643
6461 23:45:31.833650 RX Delay -359 -> 252, step: 8
6462 23:45:31.834071
6463 23:45:31.836603 Set Vref, RX VrefLevel [Byte0]: 57
6464 23:45:31.839836 [Byte1]: 50
6465 23:45:31.840322
6466 23:45:31.843159 Final RX Vref Byte 0 = 57 to rank0
6467 23:45:31.846445 Final RX Vref Byte 1 = 50 to rank0
6468 23:45:31.849992 Final RX Vref Byte 0 = 57 to rank1
6469 23:45:31.853068 Final RX Vref Byte 1 = 50 to rank1==
6470 23:45:31.856564 Dram Type= 6, Freq= 0, CH_0, rank 0
6471 23:45:31.859911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6472 23:45:31.863423 ==
6473 23:45:31.864008 DQS Delay:
6474 23:45:31.864566 DQS0 = 48, DQS1 = 60
6475 23:45:31.866515 DQM Delay:
6476 23:45:31.866933 DQM0 = 11, DQM1 = 12
6477 23:45:31.869847 DQ Delay:
6478 23:45:31.873075 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6479 23:45:31.873497 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6480 23:45:31.876124 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6481 23:45:31.879589 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6482 23:45:31.880007
6483 23:45:31.882990
6484 23:45:31.889637 [DQSOSCAuto] RK0, (LSB)MR18= 0xbd81, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 386 ps
6485 23:45:31.893110 CH0 RK0: MR19=C0C, MR18=BD81
6486 23:45:31.899561 CH0_RK0: MR19=0xC0C, MR18=0xBD81, DQSOSC=386, MR23=63, INC=396, DEC=264
6487 23:45:31.900000 ==
6488 23:45:31.902851 Dram Type= 6, Freq= 0, CH_0, rank 1
6489 23:45:31.905832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6490 23:45:31.906304 ==
6491 23:45:31.909692 [Gating] SW mode calibration
6492 23:45:31.915710 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6493 23:45:31.922874 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6494 23:45:31.925995 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6495 23:45:31.929091 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6496 23:45:31.935531 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6497 23:45:31.938811 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6498 23:45:31.942307 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6499 23:45:31.948651 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6500 23:45:31.952307 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6501 23:45:31.955272 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6502 23:45:31.961931 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6503 23:45:31.962495 Total UI for P1: 0, mck2ui 16
6504 23:45:31.968627 best dqsien dly found for B0: ( 0, 14, 24)
6505 23:45:31.969135 Total UI for P1: 0, mck2ui 16
6506 23:45:31.975371 best dqsien dly found for B1: ( 0, 14, 24)
6507 23:45:31.978278 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6508 23:45:31.981735 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6509 23:45:31.982202
6510 23:45:31.984896 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6511 23:45:31.988334 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6512 23:45:31.991645 [Gating] SW calibration Done
6513 23:45:31.992095 ==
6514 23:45:31.994978 Dram Type= 6, Freq= 0, CH_0, rank 1
6515 23:45:31.998667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6516 23:45:31.999087 ==
6517 23:45:32.001448 RX Vref Scan: 0
6518 23:45:32.001864
6519 23:45:32.002229 RX Vref 0 -> 0, step: 1
6520 23:45:32.002548
6521 23:45:32.004728 RX Delay -410 -> 252, step: 16
6522 23:45:32.011593 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6523 23:45:32.015104 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6524 23:45:32.018394 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6525 23:45:32.021356 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6526 23:45:32.027807 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6527 23:45:32.031405 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6528 23:45:32.034667 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6529 23:45:32.038220 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6530 23:45:32.044351 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6531 23:45:32.048015 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6532 23:45:32.051430 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6533 23:45:32.057757 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6534 23:45:32.061459 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6535 23:45:32.064281 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6536 23:45:32.067293 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6537 23:45:32.074029 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6538 23:45:32.074495 ==
6539 23:45:32.076935 Dram Type= 6, Freq= 0, CH_0, rank 1
6540 23:45:32.080965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6541 23:45:32.081390 ==
6542 23:45:32.081724 DQS Delay:
6543 23:45:32.083741 DQS0 = 43, DQS1 = 59
6544 23:45:32.084158 DQM Delay:
6545 23:45:32.087021 DQM0 = 10, DQM1 = 16
6546 23:45:32.087439 DQ Delay:
6547 23:45:32.090296 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6548 23:45:32.093592 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6549 23:45:32.097233 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6550 23:45:32.100651 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6551 23:45:32.101095
6552 23:45:32.101421
6553 23:45:32.101720 ==
6554 23:45:32.103401 Dram Type= 6, Freq= 0, CH_0, rank 1
6555 23:45:32.106810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6556 23:45:32.107223 ==
6557 23:45:32.107550
6558 23:45:32.110265
6559 23:45:32.110810 TX Vref Scan disable
6560 23:45:32.113993 == TX Byte 0 ==
6561 23:45:32.116485 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6562 23:45:32.120355 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6563 23:45:32.123160 == TX Byte 1 ==
6564 23:45:32.126804 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6565 23:45:32.129870 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6566 23:45:32.130385 ==
6567 23:45:32.133565 Dram Type= 6, Freq= 0, CH_0, rank 1
6568 23:45:32.136537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6569 23:45:32.139555 ==
6570 23:45:32.139965
6571 23:45:32.140285
6572 23:45:32.140583 TX Vref Scan disable
6573 23:45:32.142791 == TX Byte 0 ==
6574 23:45:32.145972 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6575 23:45:32.149703 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6576 23:45:32.152630 == TX Byte 1 ==
6577 23:45:32.156426 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6578 23:45:32.159304 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6579 23:45:32.159792
6580 23:45:32.162496 [DATLAT]
6581 23:45:32.162907 Freq=400, CH0 RK1
6582 23:45:32.163232
6583 23:45:32.166253 DATLAT Default: 0xe
6584 23:45:32.166669 0, 0xFFFF, sum = 0
6585 23:45:32.169502 1, 0xFFFF, sum = 0
6586 23:45:32.169919 2, 0xFFFF, sum = 0
6587 23:45:32.172785 3, 0xFFFF, sum = 0
6588 23:45:32.173199 4, 0xFFFF, sum = 0
6589 23:45:32.175687 5, 0xFFFF, sum = 0
6590 23:45:32.176102 6, 0xFFFF, sum = 0
6591 23:45:32.179247 7, 0xFFFF, sum = 0
6592 23:45:32.179665 8, 0xFFFF, sum = 0
6593 23:45:32.182827 9, 0xFFFF, sum = 0
6594 23:45:32.183250 10, 0xFFFF, sum = 0
6595 23:45:32.185621 11, 0xFFFF, sum = 0
6596 23:45:32.188797 12, 0xFFFF, sum = 0
6597 23:45:32.189427 13, 0x0, sum = 1
6598 23:45:32.192205 14, 0x0, sum = 2
6599 23:45:32.192624 15, 0x0, sum = 3
6600 23:45:32.192953 16, 0x0, sum = 4
6601 23:45:32.195491 best_step = 14
6602 23:45:32.195897
6603 23:45:32.196220 ==
6604 23:45:32.198750 Dram Type= 6, Freq= 0, CH_0, rank 1
6605 23:45:32.202332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6606 23:45:32.202747 ==
6607 23:45:32.205175 RX Vref Scan: 0
6608 23:45:32.205695
6609 23:45:32.208357 RX Vref 0 -> 0, step: 1
6610 23:45:32.208900
6611 23:45:32.209242 RX Delay -359 -> 252, step: 8
6612 23:45:32.217257 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6613 23:45:32.221170 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6614 23:45:32.223813 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6615 23:45:32.230741 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6616 23:45:32.233739 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6617 23:45:32.237091 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6618 23:45:32.240380 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6619 23:45:32.246857 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6620 23:45:32.249982 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6621 23:45:32.253487 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6622 23:45:32.256716 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6623 23:45:32.263403 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6624 23:45:32.266766 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6625 23:45:32.270388 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6626 23:45:32.273846 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6627 23:45:32.279753 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6628 23:45:32.280271 ==
6629 23:45:32.283210 Dram Type= 6, Freq= 0, CH_0, rank 1
6630 23:45:32.286636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6631 23:45:32.287155 ==
6632 23:45:32.287491 DQS Delay:
6633 23:45:32.290504 DQS0 = 44, DQS1 = 60
6634 23:45:32.290924 DQM Delay:
6635 23:45:32.293247 DQM0 = 8, DQM1 = 14
6636 23:45:32.293761 DQ Delay:
6637 23:45:32.296579 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =8
6638 23:45:32.299844 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6639 23:45:32.303069 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6640 23:45:32.306578 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6641 23:45:32.307098
6642 23:45:32.307428
6643 23:45:32.312902 [DQSOSCAuto] RK1, (LSB)MR18= 0xb744, (MSB)MR19= 0xc0c, tDQSOscB0 = 401 ps tDQSOscB1 = 387 ps
6644 23:45:32.316419 CH0 RK1: MR19=C0C, MR18=B744
6645 23:45:32.322474 CH0_RK1: MR19=0xC0C, MR18=0xB744, DQSOSC=387, MR23=63, INC=394, DEC=262
6646 23:45:32.326183 [RxdqsGatingPostProcess] freq 400
6647 23:45:32.332487 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6648 23:45:32.335661 best DQS0 dly(2T, 0.5T) = (0, 10)
6649 23:45:32.339365 best DQS1 dly(2T, 0.5T) = (0, 10)
6650 23:45:32.342764 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6651 23:45:32.345833 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6652 23:45:32.349117 best DQS0 dly(2T, 0.5T) = (0, 10)
6653 23:45:32.349583 best DQS1 dly(2T, 0.5T) = (0, 10)
6654 23:45:32.352316 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6655 23:45:32.355382 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6656 23:45:32.359122 Pre-setting of DQS Precalculation
6657 23:45:32.365583 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6658 23:45:32.366220 ==
6659 23:45:32.368479 Dram Type= 6, Freq= 0, CH_1, rank 0
6660 23:45:32.372458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6661 23:45:32.372940 ==
6662 23:45:32.378780 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6663 23:45:32.386117 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6664 23:45:32.388473 [CA 0] Center 36 (8~64) winsize 57
6665 23:45:32.392077 [CA 1] Center 36 (8~64) winsize 57
6666 23:45:32.394865 [CA 2] Center 36 (8~64) winsize 57
6667 23:45:32.395491 [CA 3] Center 36 (8~64) winsize 57
6668 23:45:32.398691 [CA 4] Center 36 (8~64) winsize 57
6669 23:45:32.401541 [CA 5] Center 36 (8~64) winsize 57
6670 23:45:32.401991
6671 23:45:32.408487 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6672 23:45:32.409016
6673 23:45:32.411859 [CATrainingPosCal] consider 1 rank data
6674 23:45:32.415487 u2DelayCellTimex100 = 270/100 ps
6675 23:45:32.418471 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6676 23:45:32.422045 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6677 23:45:32.425096 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6678 23:45:32.427944 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6679 23:45:32.431608 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6680 23:45:32.434397 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6681 23:45:32.434820
6682 23:45:32.438140 CA PerBit enable=1, Macro0, CA PI delay=36
6683 23:45:32.438627
6684 23:45:32.441082 [CBTSetCACLKResult] CA Dly = 36
6685 23:45:32.444432 CS Dly: 1 (0~32)
6686 23:45:32.444990 ==
6687 23:45:32.447780 Dram Type= 6, Freq= 0, CH_1, rank 1
6688 23:45:32.450872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6689 23:45:32.451290 ==
6690 23:45:32.457732 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6691 23:45:32.464158 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6692 23:45:32.467262 [CA 0] Center 36 (8~64) winsize 57
6693 23:45:32.470816 [CA 1] Center 36 (8~64) winsize 57
6694 23:45:32.471368 [CA 2] Center 36 (8~64) winsize 57
6695 23:45:32.474111 [CA 3] Center 36 (8~64) winsize 57
6696 23:45:32.477513 [CA 4] Center 36 (8~64) winsize 57
6697 23:45:32.480983 [CA 5] Center 36 (8~64) winsize 57
6698 23:45:32.481438
6699 23:45:32.484121 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6700 23:45:32.487588
6701 23:45:32.490453 [CATrainingPosCal] consider 2 rank data
6702 23:45:32.494069 u2DelayCellTimex100 = 270/100 ps
6703 23:45:32.497259 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6704 23:45:32.500896 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6705 23:45:32.503781 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6706 23:45:32.506880 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6707 23:45:32.510409 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6708 23:45:32.514135 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6709 23:45:32.514739
6710 23:45:32.517102 CA PerBit enable=1, Macro0, CA PI delay=36
6711 23:45:32.517657
6712 23:45:32.520258 [CBTSetCACLKResult] CA Dly = 36
6713 23:45:32.524166 CS Dly: 1 (0~32)
6714 23:45:32.524719
6715 23:45:32.526637 ----->DramcWriteLeveling(PI) begin...
6716 23:45:32.527101 ==
6717 23:45:32.530702 Dram Type= 6, Freq= 0, CH_1, rank 0
6718 23:45:32.533714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6719 23:45:32.534235 ==
6720 23:45:32.537104 Write leveling (Byte 0): 40 => 8
6721 23:45:32.540361 Write leveling (Byte 1): 40 => 8
6722 23:45:32.543372 DramcWriteLeveling(PI) end<-----
6723 23:45:32.543970
6724 23:45:32.544337 ==
6725 23:45:32.546812 Dram Type= 6, Freq= 0, CH_1, rank 0
6726 23:45:32.549993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6727 23:45:32.550602 ==
6728 23:45:32.553003 [Gating] SW mode calibration
6729 23:45:32.559777 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6730 23:45:32.566325 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6731 23:45:32.569870 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6732 23:45:32.576408 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6733 23:45:32.579123 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6734 23:45:32.582724 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6735 23:45:32.589250 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6736 23:45:32.592521 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6737 23:45:32.595808 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6738 23:45:32.602784 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6739 23:45:32.606483 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6740 23:45:32.609283 Total UI for P1: 0, mck2ui 16
6741 23:45:32.612752 best dqsien dly found for B0: ( 0, 14, 24)
6742 23:45:32.615792 Total UI for P1: 0, mck2ui 16
6743 23:45:32.619341 best dqsien dly found for B1: ( 0, 14, 24)
6744 23:45:32.622379 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6745 23:45:32.625872 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6746 23:45:32.626499
6747 23:45:32.628708 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6748 23:45:32.632278 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6749 23:45:32.635293 [Gating] SW calibration Done
6750 23:45:32.635796 ==
6751 23:45:32.638753 Dram Type= 6, Freq= 0, CH_1, rank 0
6752 23:45:32.642202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6753 23:45:32.645354 ==
6754 23:45:32.645911 RX Vref Scan: 0
6755 23:45:32.646450
6756 23:45:32.648842 RX Vref 0 -> 0, step: 1
6757 23:45:32.649312
6758 23:45:32.652064 RX Delay -410 -> 252, step: 16
6759 23:45:32.655505 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6760 23:45:32.658644 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6761 23:45:32.662487 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6762 23:45:32.668775 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6763 23:45:32.672245 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6764 23:45:32.675029 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6765 23:45:32.678272 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6766 23:45:32.684696 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6767 23:45:32.687981 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6768 23:45:32.691821 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6769 23:45:32.698013 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6770 23:45:32.701380 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6771 23:45:32.704847 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6772 23:45:32.708313 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6773 23:45:32.714400 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6774 23:45:32.718294 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6775 23:45:32.718877 ==
6776 23:45:32.721083 Dram Type= 6, Freq= 0, CH_1, rank 0
6777 23:45:32.724319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6778 23:45:32.724736 ==
6779 23:45:32.727984 DQS Delay:
6780 23:45:32.728414 DQS0 = 43, DQS1 = 51
6781 23:45:32.730946 DQM Delay:
6782 23:45:32.731354 DQM0 = 11, DQM1 = 14
6783 23:45:32.731679 DQ Delay:
6784 23:45:32.734739 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6785 23:45:32.737345 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6786 23:45:32.740969 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6787 23:45:32.744190 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6788 23:45:32.744604
6789 23:45:32.744932
6790 23:45:32.745234 ==
6791 23:45:32.747424 Dram Type= 6, Freq= 0, CH_1, rank 0
6792 23:45:32.754283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6793 23:45:32.754872 ==
6794 23:45:32.755208
6795 23:45:32.755510
6796 23:45:32.755798 TX Vref Scan disable
6797 23:45:32.757358 == TX Byte 0 ==
6798 23:45:32.760841 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6799 23:45:32.764200 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6800 23:45:32.767203 == TX Byte 1 ==
6801 23:45:32.770980 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6802 23:45:32.774283 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6803 23:45:32.774822 ==
6804 23:45:32.777328 Dram Type= 6, Freq= 0, CH_1, rank 0
6805 23:45:32.783883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6806 23:45:32.784324 ==
6807 23:45:32.784651
6808 23:45:32.784954
6809 23:45:32.785247 TX Vref Scan disable
6810 23:45:32.787048 == TX Byte 0 ==
6811 23:45:32.790246 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6812 23:45:32.793633 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6813 23:45:32.797125 == TX Byte 1 ==
6814 23:45:32.800235 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6815 23:45:32.804197 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6816 23:45:32.804610
6817 23:45:32.806899 [DATLAT]
6818 23:45:32.807312 Freq=400, CH1 RK0
6819 23:45:32.807644
6820 23:45:32.810266 DATLAT Default: 0xf
6821 23:45:32.810730 0, 0xFFFF, sum = 0
6822 23:45:32.813514 1, 0xFFFF, sum = 0
6823 23:45:32.813930 2, 0xFFFF, sum = 0
6824 23:45:32.817071 3, 0xFFFF, sum = 0
6825 23:45:32.817590 4, 0xFFFF, sum = 0
6826 23:45:32.820748 5, 0xFFFF, sum = 0
6827 23:45:32.821294 6, 0xFFFF, sum = 0
6828 23:45:32.823738 7, 0xFFFF, sum = 0
6829 23:45:32.824158 8, 0xFFFF, sum = 0
6830 23:45:32.826862 9, 0xFFFF, sum = 0
6831 23:45:32.830246 10, 0xFFFF, sum = 0
6832 23:45:32.830803 11, 0xFFFF, sum = 0
6833 23:45:32.834149 12, 0xFFFF, sum = 0
6834 23:45:32.834795 13, 0x0, sum = 1
6835 23:45:32.837380 14, 0x0, sum = 2
6836 23:45:32.837840 15, 0x0, sum = 3
6837 23:45:32.838220 16, 0x0, sum = 4
6838 23:45:32.840375 best_step = 14
6839 23:45:32.840893
6840 23:45:32.841240 ==
6841 23:45:32.843627 Dram Type= 6, Freq= 0, CH_1, rank 0
6842 23:45:32.847011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6843 23:45:32.847426 ==
6844 23:45:32.850341 RX Vref Scan: 1
6845 23:45:32.850751
6846 23:45:32.853755 RX Vref 0 -> 0, step: 1
6847 23:45:32.854311
6848 23:45:32.854650 RX Delay -343 -> 252, step: 8
6849 23:45:32.854961
6850 23:45:32.856732 Set Vref, RX VrefLevel [Byte0]: 49
6851 23:45:32.859848 [Byte1]: 54
6852 23:45:32.865531
6853 23:45:32.866040 Final RX Vref Byte 0 = 49 to rank0
6854 23:45:32.868783 Final RX Vref Byte 1 = 54 to rank0
6855 23:45:32.872766 Final RX Vref Byte 0 = 49 to rank1
6856 23:45:32.875399 Final RX Vref Byte 1 = 54 to rank1==
6857 23:45:32.878605 Dram Type= 6, Freq= 0, CH_1, rank 0
6858 23:45:32.885022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6859 23:45:32.885452 ==
6860 23:45:32.885836 DQS Delay:
6861 23:45:32.888433 DQS0 = 44, DQS1 = 56
6862 23:45:32.888844 DQM Delay:
6863 23:45:32.889170 DQM0 = 7, DQM1 = 11
6864 23:45:32.891587 DQ Delay:
6865 23:45:32.894817 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6866 23:45:32.898158 DQ4 =4, DQ5 =16, DQ6 =16, DQ7 =4
6867 23:45:32.898609 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6868 23:45:32.904724 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
6869 23:45:32.905221
6870 23:45:32.905545
6871 23:45:32.911436 [DQSOSCAuto] RK0, (LSB)MR18= 0x9c72, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 390 ps
6872 23:45:32.914641 CH1 RK0: MR19=C0C, MR18=9C72
6873 23:45:32.921104 CH1_RK0: MR19=0xC0C, MR18=0x9C72, DQSOSC=390, MR23=63, INC=388, DEC=258
6874 23:45:32.921705 ==
6875 23:45:32.924806 Dram Type= 6, Freq= 0, CH_1, rank 1
6876 23:45:32.928229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6877 23:45:32.928795 ==
6878 23:45:32.930953 [Gating] SW mode calibration
6879 23:45:32.937475 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6880 23:45:32.944215 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6881 23:45:32.947908 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6882 23:45:32.951001 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6883 23:45:32.957836 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6884 23:45:32.961071 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6885 23:45:32.964526 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6886 23:45:32.970843 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6887 23:45:32.974330 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6888 23:45:32.977838 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6889 23:45:32.983965 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6890 23:45:32.987037 Total UI for P1: 0, mck2ui 16
6891 23:45:32.990495 best dqsien dly found for B0: ( 0, 14, 24)
6892 23:45:32.994196 Total UI for P1: 0, mck2ui 16
6893 23:45:32.997187 best dqsien dly found for B1: ( 0, 14, 24)
6894 23:45:32.999804 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6895 23:45:33.003103 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6896 23:45:33.003565
6897 23:45:33.007167 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6898 23:45:33.009827 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6899 23:45:33.013453 [Gating] SW calibration Done
6900 23:45:33.014032 ==
6901 23:45:33.017161 Dram Type= 6, Freq= 0, CH_1, rank 1
6902 23:45:33.019834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6903 23:45:33.020296 ==
6904 23:45:33.022930 RX Vref Scan: 0
6905 23:45:33.023404
6906 23:45:33.026837 RX Vref 0 -> 0, step: 1
6907 23:45:33.027636
6908 23:45:33.029829 RX Delay -410 -> 252, step: 16
6909 23:45:33.033244 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6910 23:45:33.036564 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6911 23:45:33.039551 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6912 23:45:33.046284 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6913 23:45:33.049728 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6914 23:45:33.052406 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6915 23:45:33.056351 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6916 23:45:33.062533 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6917 23:45:33.066369 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6918 23:45:33.069569 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6919 23:45:33.072901 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6920 23:45:33.079513 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6921 23:45:33.082715 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6922 23:45:33.085931 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6923 23:45:33.092898 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6924 23:45:33.096085 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6925 23:45:33.096649 ==
6926 23:45:33.098882 Dram Type= 6, Freq= 0, CH_1, rank 1
6927 23:45:33.102377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6928 23:45:33.102836 ==
6929 23:45:33.105755 DQS Delay:
6930 23:45:33.106236 DQS0 = 51, DQS1 = 51
6931 23:45:33.106604 DQM Delay:
6932 23:45:33.109405 DQM0 = 19, DQM1 = 14
6933 23:45:33.109967 DQ Delay:
6934 23:45:33.112451 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6935 23:45:33.115803 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6936 23:45:33.118962 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6937 23:45:33.121973 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6938 23:45:33.122465
6939 23:45:33.122829
6940 23:45:33.123162 ==
6941 23:45:33.125860 Dram Type= 6, Freq= 0, CH_1, rank 1
6942 23:45:33.131836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6943 23:45:33.132301 ==
6944 23:45:33.132665
6945 23:45:33.133002
6946 23:45:33.133326 TX Vref Scan disable
6947 23:45:33.135404 == TX Byte 0 ==
6948 23:45:33.138379 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6949 23:45:33.142152 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6950 23:45:33.144811 == TX Byte 1 ==
6951 23:45:33.148721 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6952 23:45:33.151488 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6953 23:45:33.151980 ==
6954 23:45:33.155167 Dram Type= 6, Freq= 0, CH_1, rank 1
6955 23:45:33.161731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6956 23:45:33.162349 ==
6957 23:45:33.162727
6958 23:45:33.163060
6959 23:45:33.163379 TX Vref Scan disable
6960 23:45:33.164769 == TX Byte 0 ==
6961 23:45:33.168703 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6962 23:45:33.171803 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6963 23:45:33.174682 == TX Byte 1 ==
6964 23:45:33.178332 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6965 23:45:33.181672 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6966 23:45:33.182302
6967 23:45:33.184911 [DATLAT]
6968 23:45:33.185517 Freq=400, CH1 RK1
6969 23:45:33.185896
6970 23:45:33.188212 DATLAT Default: 0xe
6971 23:45:33.188762 0, 0xFFFF, sum = 0
6972 23:45:33.191176 1, 0xFFFF, sum = 0
6973 23:45:33.191638 2, 0xFFFF, sum = 0
6974 23:45:33.195026 3, 0xFFFF, sum = 0
6975 23:45:33.195489 4, 0xFFFF, sum = 0
6976 23:45:33.197763 5, 0xFFFF, sum = 0
6977 23:45:33.198267 6, 0xFFFF, sum = 0
6978 23:45:33.201407 7, 0xFFFF, sum = 0
6979 23:45:33.201971 8, 0xFFFF, sum = 0
6980 23:45:33.204431 9, 0xFFFF, sum = 0
6981 23:45:33.207799 10, 0xFFFF, sum = 0
6982 23:45:33.208262 11, 0xFFFF, sum = 0
6983 23:45:33.211047 12, 0xFFFF, sum = 0
6984 23:45:33.211511 13, 0x0, sum = 1
6985 23:45:33.214411 14, 0x0, sum = 2
6986 23:45:33.214878 15, 0x0, sum = 3
6987 23:45:33.217599 16, 0x0, sum = 4
6988 23:45:33.218021 best_step = 14
6989 23:45:33.218396
6990 23:45:33.218706 ==
6991 23:45:33.221245 Dram Type= 6, Freq= 0, CH_1, rank 1
6992 23:45:33.224413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6993 23:45:33.224848 ==
6994 23:45:33.228040 RX Vref Scan: 0
6995 23:45:33.228456
6996 23:45:33.230690 RX Vref 0 -> 0, step: 1
6997 23:45:33.231108
6998 23:45:33.231436 RX Delay -343 -> 252, step: 8
6999 23:45:33.239784 iDelay=225, Bit 0, Center -32 (-271 ~ 208) 480
7000 23:45:33.243260 iDelay=225, Bit 1, Center -40 (-279 ~ 200) 480
7001 23:45:33.246257 iDelay=225, Bit 2, Center -48 (-287 ~ 192) 480
7002 23:45:33.252736 iDelay=225, Bit 3, Center -36 (-271 ~ 200) 472
7003 23:45:33.256258 iDelay=225, Bit 4, Center -36 (-279 ~ 208) 488
7004 23:45:33.259737 iDelay=225, Bit 5, Center -24 (-263 ~ 216) 480
7005 23:45:33.262548 iDelay=225, Bit 6, Center -24 (-271 ~ 224) 496
7006 23:45:33.269425 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
7007 23:45:33.272435 iDelay=225, Bit 8, Center -56 (-303 ~ 192) 496
7008 23:45:33.276079 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
7009 23:45:33.279061 iDelay=225, Bit 10, Center -44 (-295 ~ 208) 504
7010 23:45:33.286034 iDelay=225, Bit 11, Center -56 (-303 ~ 192) 496
7011 23:45:33.288990 iDelay=225, Bit 12, Center -36 (-287 ~ 216) 504
7012 23:45:33.292456 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
7013 23:45:33.295798 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
7014 23:45:33.302264 iDelay=225, Bit 15, Center -36 (-287 ~ 216) 504
7015 23:45:33.302687 ==
7016 23:45:33.305900 Dram Type= 6, Freq= 0, CH_1, rank 1
7017 23:45:33.308987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7018 23:45:33.309519 ==
7019 23:45:33.309860 DQS Delay:
7020 23:45:33.312275 DQS0 = 48, DQS1 = 56
7021 23:45:33.312690 DQM Delay:
7022 23:45:33.315577 DQM0 = 13, DQM1 = 10
7023 23:45:33.316017 DQ Delay:
7024 23:45:33.318638 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
7025 23:45:33.321967 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
7026 23:45:33.326069 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
7027 23:45:33.329038 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
7028 23:45:33.329455
7029 23:45:33.329784
7030 23:45:33.338409 [DQSOSCAuto] RK1, (LSB)MR18= 0x6b5a, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
7031 23:45:33.338847 CH1 RK1: MR19=C0C, MR18=6B5A
7032 23:45:33.345645 CH1_RK1: MR19=0xC0C, MR18=0x6B5A, DQSOSC=396, MR23=63, INC=376, DEC=251
7033 23:45:33.348617 [RxdqsGatingPostProcess] freq 400
7034 23:45:33.355399 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7035 23:45:33.358369 best DQS0 dly(2T, 0.5T) = (0, 10)
7036 23:45:33.361708 best DQS1 dly(2T, 0.5T) = (0, 10)
7037 23:45:33.364911 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7038 23:45:33.368497 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7039 23:45:33.371421 best DQS0 dly(2T, 0.5T) = (0, 10)
7040 23:45:33.374653 best DQS1 dly(2T, 0.5T) = (0, 10)
7041 23:45:33.377932 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7042 23:45:33.381627 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7043 23:45:33.382044 Pre-setting of DQS Precalculation
7044 23:45:33.388042 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7045 23:45:33.394605 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7046 23:45:33.401567 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7047 23:45:33.401995
7048 23:45:33.402374
7049 23:45:33.404297 [Calibration Summary] 800 Mbps
7050 23:45:33.407896 CH 0, Rank 0
7051 23:45:33.408309 SW Impedance : PASS
7052 23:45:33.410970 DUTY Scan : NO K
7053 23:45:33.414130 ZQ Calibration : PASS
7054 23:45:33.414586 Jitter Meter : NO K
7055 23:45:33.417712 CBT Training : PASS
7056 23:45:33.420978 Write leveling : PASS
7057 23:45:33.421502 RX DQS gating : PASS
7058 23:45:33.424335 RX DQ/DQS(RDDQC) : PASS
7059 23:45:33.427643 TX DQ/DQS : PASS
7060 23:45:33.428067 RX DATLAT : PASS
7061 23:45:33.431112 RX DQ/DQS(Engine): PASS
7062 23:45:33.431525 TX OE : NO K
7063 23:45:33.434116 All Pass.
7064 23:45:33.434572
7065 23:45:33.434900 CH 0, Rank 1
7066 23:45:33.437081 SW Impedance : PASS
7067 23:45:33.440461 DUTY Scan : NO K
7068 23:45:33.440875 ZQ Calibration : PASS
7069 23:45:33.443855 Jitter Meter : NO K
7070 23:45:33.444270 CBT Training : PASS
7071 23:45:33.447129 Write leveling : NO K
7072 23:45:33.450204 RX DQS gating : PASS
7073 23:45:33.450624 RX DQ/DQS(RDDQC) : PASS
7074 23:45:33.454047 TX DQ/DQS : PASS
7075 23:45:33.457259 RX DATLAT : PASS
7076 23:45:33.457771 RX DQ/DQS(Engine): PASS
7077 23:45:33.460237 TX OE : NO K
7078 23:45:33.460656 All Pass.
7079 23:45:33.460987
7080 23:45:33.463666 CH 1, Rank 0
7081 23:45:33.464185 SW Impedance : PASS
7082 23:45:33.466806 DUTY Scan : NO K
7083 23:45:33.470732 ZQ Calibration : PASS
7084 23:45:33.471255 Jitter Meter : NO K
7085 23:45:33.473418 CBT Training : PASS
7086 23:45:33.476919 Write leveling : PASS
7087 23:45:33.477433 RX DQS gating : PASS
7088 23:45:33.480404 RX DQ/DQS(RDDQC) : PASS
7089 23:45:33.483097 TX DQ/DQS : PASS
7090 23:45:33.483535 RX DATLAT : PASS
7091 23:45:33.486548 RX DQ/DQS(Engine): PASS
7092 23:45:33.490535 TX OE : NO K
7093 23:45:33.491053 All Pass.
7094 23:45:33.491386
7095 23:45:33.491697 CH 1, Rank 1
7096 23:45:33.493433 SW Impedance : PASS
7097 23:45:33.496592 DUTY Scan : NO K
7098 23:45:33.497010 ZQ Calibration : PASS
7099 23:45:33.499925 Jitter Meter : NO K
7100 23:45:33.503126 CBT Training : PASS
7101 23:45:33.503539 Write leveling : NO K
7102 23:45:33.506715 RX DQS gating : PASS
7103 23:45:33.507131 RX DQ/DQS(RDDQC) : PASS
7104 23:45:33.510117 TX DQ/DQS : PASS
7105 23:45:33.513357 RX DATLAT : PASS
7106 23:45:33.513873 RX DQ/DQS(Engine): PASS
7107 23:45:33.516802 TX OE : NO K
7108 23:45:33.517318 All Pass.
7109 23:45:33.517659
7110 23:45:33.519628 DramC Write-DBI off
7111 23:45:33.523096 PER_BANK_REFRESH: Hybrid Mode
7112 23:45:33.523515 TX_TRACKING: ON
7113 23:45:33.533659 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7114 23:45:33.536067 [FAST_K] Save calibration result to emmc
7115 23:45:33.539364 dramc_set_vcore_voltage set vcore to 725000
7116 23:45:33.543188 Read voltage for 1600, 0
7117 23:45:33.543730 Vio18 = 0
7118 23:45:33.546064 Vcore = 725000
7119 23:45:33.546516 Vdram = 0
7120 23:45:33.546844 Vddq = 0
7121 23:45:33.547146 Vmddr = 0
7122 23:45:33.552787 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7123 23:45:33.559134 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7124 23:45:33.559656 MEM_TYPE=3, freq_sel=13
7125 23:45:33.562551 sv_algorithm_assistance_LP4_3733
7126 23:45:33.565828 ============ PULL DRAM RESETB DOWN ============
7127 23:45:33.572294 ========== PULL DRAM RESETB DOWN end =========
7128 23:45:33.575756 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7129 23:45:33.578802 ===================================
7130 23:45:33.582441 LPDDR4 DRAM CONFIGURATION
7131 23:45:33.585574 ===================================
7132 23:45:33.586046 EX_ROW_EN[0] = 0x0
7133 23:45:33.588995 EX_ROW_EN[1] = 0x0
7134 23:45:33.592146 LP4Y_EN = 0x0
7135 23:45:33.592562 WORK_FSP = 0x1
7136 23:45:33.595315 WL = 0x5
7137 23:45:33.595730 RL = 0x5
7138 23:45:33.598846 BL = 0x2
7139 23:45:33.599263 RPST = 0x0
7140 23:45:33.602138 RD_PRE = 0x0
7141 23:45:33.602694 WR_PRE = 0x1
7142 23:45:33.605716 WR_PST = 0x1
7143 23:45:33.606267 DBI_WR = 0x0
7144 23:45:33.608662 DBI_RD = 0x0
7145 23:45:33.609076 OTF = 0x1
7146 23:45:33.611510 ===================================
7147 23:45:33.615657 ===================================
7148 23:45:33.618457 ANA top config
7149 23:45:33.621640 ===================================
7150 23:45:33.624916 DLL_ASYNC_EN = 0
7151 23:45:33.625333 ALL_SLAVE_EN = 0
7152 23:45:33.628453 NEW_RANK_MODE = 1
7153 23:45:33.631447 DLL_IDLE_MODE = 1
7154 23:45:33.635182 LP45_APHY_COMB_EN = 1
7155 23:45:33.635699 TX_ODT_DIS = 0
7156 23:45:33.638317 NEW_8X_MODE = 1
7157 23:45:33.641773 ===================================
7158 23:45:33.644859 ===================================
7159 23:45:33.648447 data_rate = 3200
7160 23:45:33.651500 CKR = 1
7161 23:45:33.655009 DQ_P2S_RATIO = 8
7162 23:45:33.658499 ===================================
7163 23:45:33.661922 CA_P2S_RATIO = 8
7164 23:45:33.662514 DQ_CA_OPEN = 0
7165 23:45:33.665370 DQ_SEMI_OPEN = 0
7166 23:45:33.668265 CA_SEMI_OPEN = 0
7167 23:45:33.671843 CA_FULL_RATE = 0
7168 23:45:33.674790 DQ_CKDIV4_EN = 0
7169 23:45:33.677671 CA_CKDIV4_EN = 0
7170 23:45:33.678088 CA_PREDIV_EN = 0
7171 23:45:33.681468 PH8_DLY = 12
7172 23:45:33.684469 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7173 23:45:33.688042 DQ_AAMCK_DIV = 4
7174 23:45:33.690969 CA_AAMCK_DIV = 4
7175 23:45:33.694100 CA_ADMCK_DIV = 4
7176 23:45:33.697533 DQ_TRACK_CA_EN = 0
7177 23:45:33.698057 CA_PICK = 1600
7178 23:45:33.701206 CA_MCKIO = 1600
7179 23:45:33.704016 MCKIO_SEMI = 0
7180 23:45:33.707926 PLL_FREQ = 3068
7181 23:45:33.710704 DQ_UI_PI_RATIO = 32
7182 23:45:33.714094 CA_UI_PI_RATIO = 0
7183 23:45:33.717438 ===================================
7184 23:45:33.720540 ===================================
7185 23:45:33.723788 memory_type:LPDDR4
7186 23:45:33.724250 GP_NUM : 10
7187 23:45:33.727321 SRAM_EN : 1
7188 23:45:33.727868 MD32_EN : 0
7189 23:45:33.730442 ===================================
7190 23:45:33.733794 [ANA_INIT] >>>>>>>>>>>>>>
7191 23:45:33.737497 <<<<<< [CONFIGURE PHASE]: ANA_TX
7192 23:45:33.740363 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7193 23:45:33.744245 ===================================
7194 23:45:33.746905 data_rate = 3200,PCW = 0X7600
7195 23:45:33.751054 ===================================
7196 23:45:33.753444 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7197 23:45:33.759970 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7198 23:45:33.763435 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7199 23:45:33.769997 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7200 23:45:33.773843 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7201 23:45:33.776472 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7202 23:45:33.776937 [ANA_INIT] flow start
7203 23:45:33.779717 [ANA_INIT] PLL >>>>>>>>
7204 23:45:33.783435 [ANA_INIT] PLL <<<<<<<<
7205 23:45:33.784000 [ANA_INIT] MIDPI >>>>>>>>
7206 23:45:33.786312 [ANA_INIT] MIDPI <<<<<<<<
7207 23:45:33.789741 [ANA_INIT] DLL >>>>>>>>
7208 23:45:33.793057 [ANA_INIT] DLL <<<<<<<<
7209 23:45:33.793619 [ANA_INIT] flow end
7210 23:45:33.796562 ============ LP4 DIFF to SE enter ============
7211 23:45:33.802865 ============ LP4 DIFF to SE exit ============
7212 23:45:33.803331 [ANA_INIT] <<<<<<<<<<<<<
7213 23:45:33.806363 [Flow] Enable top DCM control >>>>>
7214 23:45:33.809623 [Flow] Enable top DCM control <<<<<
7215 23:45:33.812810 Enable DLL master slave shuffle
7216 23:45:33.819781 ==============================================================
7217 23:45:33.820337 Gating Mode config
7218 23:45:33.826225 ==============================================================
7219 23:45:33.829700 Config description:
7220 23:45:33.839123 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7221 23:45:33.845735 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7222 23:45:33.849218 SELPH_MODE 0: By rank 1: By Phase
7223 23:45:33.855997 ==============================================================
7224 23:45:33.859329 GAT_TRACK_EN = 1
7225 23:45:33.862338 RX_GATING_MODE = 2
7226 23:45:33.865319 RX_GATING_TRACK_MODE = 2
7227 23:45:33.865801 SELPH_MODE = 1
7228 23:45:33.868653 PICG_EARLY_EN = 1
7229 23:45:33.872341 VALID_LAT_VALUE = 1
7230 23:45:33.878646 ==============================================================
7231 23:45:33.881930 Enter into Gating configuration >>>>
7232 23:45:33.884841 Exit from Gating configuration <<<<
7233 23:45:33.888189 Enter into DVFS_PRE_config >>>>>
7234 23:45:33.898545 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7235 23:45:33.902131 Exit from DVFS_PRE_config <<<<<
7236 23:45:33.904837 Enter into PICG configuration >>>>
7237 23:45:33.908552 Exit from PICG configuration <<<<
7238 23:45:33.911216 [RX_INPUT] configuration >>>>>
7239 23:45:33.915056 [RX_INPUT] configuration <<<<<
7240 23:45:33.918502 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7241 23:45:33.924528 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7242 23:45:33.931290 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7243 23:45:33.938056 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7244 23:45:33.944706 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7245 23:45:33.951148 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7246 23:45:33.954747 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7247 23:45:33.957870 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7248 23:45:33.960904 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7249 23:45:33.967879 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7250 23:45:33.971183 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7251 23:45:33.974518 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7252 23:45:33.977452 ===================================
7253 23:45:33.980668 LPDDR4 DRAM CONFIGURATION
7254 23:45:33.984434 ===================================
7255 23:45:33.985016 EX_ROW_EN[0] = 0x0
7256 23:45:33.987598 EX_ROW_EN[1] = 0x0
7257 23:45:33.990932 LP4Y_EN = 0x0
7258 23:45:33.991392 WORK_FSP = 0x1
7259 23:45:33.994106 WL = 0x5
7260 23:45:33.994618 RL = 0x5
7261 23:45:33.997830 BL = 0x2
7262 23:45:33.998334 RPST = 0x0
7263 23:45:34.000572 RD_PRE = 0x0
7264 23:45:34.001031 WR_PRE = 0x1
7265 23:45:34.004216 WR_PST = 0x1
7266 23:45:34.004771 DBI_WR = 0x0
7267 23:45:34.007110 DBI_RD = 0x0
7268 23:45:34.007625 OTF = 0x1
7269 23:45:34.010741 ===================================
7270 23:45:34.013950 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7271 23:45:34.020445 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7272 23:45:34.023536 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7273 23:45:34.026879 ===================================
7274 23:45:34.030246 LPDDR4 DRAM CONFIGURATION
7275 23:45:34.033610 ===================================
7276 23:45:34.034093 EX_ROW_EN[0] = 0x10
7277 23:45:34.037298 EX_ROW_EN[1] = 0x0
7278 23:45:34.040520 LP4Y_EN = 0x0
7279 23:45:34.040999 WORK_FSP = 0x1
7280 23:45:34.044649 WL = 0x5
7281 23:45:34.045249 RL = 0x5
7282 23:45:34.047118 BL = 0x2
7283 23:45:34.047598 RPST = 0x0
7284 23:45:34.050278 RD_PRE = 0x0
7285 23:45:34.050758 WR_PRE = 0x1
7286 23:45:34.053635 WR_PST = 0x1
7287 23:45:34.054254 DBI_WR = 0x0
7288 23:45:34.056835 DBI_RD = 0x0
7289 23:45:34.057418 OTF = 0x1
7290 23:45:34.060172 ===================================
7291 23:45:34.066972 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7292 23:45:34.067559 ==
7293 23:45:34.070561 Dram Type= 6, Freq= 0, CH_0, rank 0
7294 23:45:34.073199 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7295 23:45:34.076355 ==
7296 23:45:34.076904 [Duty_Offset_Calibration]
7297 23:45:34.079827 B0:1 B1:-1 CA:0
7298 23:45:34.080387
7299 23:45:34.083140 [DutyScan_Calibration_Flow] k_type=0
7300 23:45:34.092334
7301 23:45:34.092938 ==CLK 0==
7302 23:45:34.095504 Final CLK duty delay cell = 0
7303 23:45:34.098706 [0] MAX Duty = 5093%(X100), DQS PI = 20
7304 23:45:34.102112 [0] MIN Duty = 4875%(X100), DQS PI = 10
7305 23:45:34.105809 [0] AVG Duty = 4984%(X100)
7306 23:45:34.106414
7307 23:45:34.108644 CH0 CLK Duty spec in!! Max-Min= 218%
7308 23:45:34.111983 [DutyScan_Calibration_Flow] ====Done====
7309 23:45:34.112566
7310 23:45:34.114930 [DutyScan_Calibration_Flow] k_type=1
7311 23:45:34.131349
7312 23:45:34.131922 ==DQS 0 ==
7313 23:45:34.134632 Final DQS duty delay cell = -4
7314 23:45:34.138370 [-4] MAX Duty = 4969%(X100), DQS PI = 18
7315 23:45:34.141179 [-4] MIN Duty = 4844%(X100), DQS PI = 48
7316 23:45:34.144563 [-4] AVG Duty = 4906%(X100)
7317 23:45:34.145125
7318 23:45:34.145488 ==DQS 1 ==
7319 23:45:34.147778 Final DQS duty delay cell = 0
7320 23:45:34.151688 [0] MAX Duty = 5156%(X100), DQS PI = 0
7321 23:45:34.154491 [0] MIN Duty = 5000%(X100), DQS PI = 18
7322 23:45:34.158360 [0] AVG Duty = 5078%(X100)
7323 23:45:34.158919
7324 23:45:34.160941 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7325 23:45:34.161404
7326 23:45:34.164231 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7327 23:45:34.167732 [DutyScan_Calibration_Flow] ====Done====
7328 23:45:34.168194
7329 23:45:34.170873 [DutyScan_Calibration_Flow] k_type=3
7330 23:45:34.188969
7331 23:45:34.189425 ==DQM 0 ==
7332 23:45:34.192277 Final DQM duty delay cell = 0
7333 23:45:34.195504 [0] MAX Duty = 5093%(X100), DQS PI = 20
7334 23:45:34.198876 [0] MIN Duty = 4875%(X100), DQS PI = 10
7335 23:45:34.202207 [0] AVG Duty = 4984%(X100)
7336 23:45:34.202625
7337 23:45:34.202952 ==DQM 1 ==
7338 23:45:34.205278 Final DQM duty delay cell = 0
7339 23:45:34.208614 [0] MAX Duty = 5000%(X100), DQS PI = 4
7340 23:45:34.211875 [0] MIN Duty = 4813%(X100), DQS PI = 18
7341 23:45:34.215161 [0] AVG Duty = 4906%(X100)
7342 23:45:34.215577
7343 23:45:34.218601 CH0 DQM 0 Duty spec in!! Max-Min= 218%
7344 23:45:34.219019
7345 23:45:34.221594 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7346 23:45:34.224688 [DutyScan_Calibration_Flow] ====Done====
7347 23:45:34.225104
7348 23:45:34.228264 [DutyScan_Calibration_Flow] k_type=2
7349 23:45:34.245212
7350 23:45:34.245627 ==DQ 0 ==
7351 23:45:34.248494 Final DQ duty delay cell = -4
7352 23:45:34.252094 [-4] MAX Duty = 5031%(X100), DQS PI = 26
7353 23:45:34.255057 [-4] MIN Duty = 4876%(X100), DQS PI = 54
7354 23:45:34.258718 [-4] AVG Duty = 4953%(X100)
7355 23:45:34.259243
7356 23:45:34.259573 ==DQ 1 ==
7357 23:45:34.262113 Final DQ duty delay cell = 0
7358 23:45:34.265411 [0] MAX Duty = 5125%(X100), DQS PI = 50
7359 23:45:34.268655 [0] MIN Duty = 4969%(X100), DQS PI = 38
7360 23:45:34.271811 [0] AVG Duty = 5047%(X100)
7361 23:45:34.272269
7362 23:45:34.275061 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7363 23:45:34.275595
7364 23:45:34.278279 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7365 23:45:34.282449 [DutyScan_Calibration_Flow] ====Done====
7366 23:45:34.282969 ==
7367 23:45:34.285307 Dram Type= 6, Freq= 0, CH_1, rank 0
7368 23:45:34.288504 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7369 23:45:34.288930 ==
7370 23:45:34.291330 [Duty_Offset_Calibration]
7371 23:45:34.291902 B0:-1 B1:1 CA:2
7372 23:45:34.292294
7373 23:45:34.294650 [DutyScan_Calibration_Flow] k_type=0
7374 23:45:34.305891
7375 23:45:34.306502 ==CLK 0==
7376 23:45:34.309706 Final CLK duty delay cell = 0
7377 23:45:34.312519 [0] MAX Duty = 5187%(X100), DQS PI = 24
7378 23:45:34.316049 [0] MIN Duty = 4969%(X100), DQS PI = 0
7379 23:45:34.316617 [0] AVG Duty = 5078%(X100)
7380 23:45:34.319066
7381 23:45:34.322313 CH1 CLK Duty spec in!! Max-Min= 218%
7382 23:45:34.325886 [DutyScan_Calibration_Flow] ====Done====
7383 23:45:34.326502
7384 23:45:34.329131 [DutyScan_Calibration_Flow] k_type=1
7385 23:45:34.345396
7386 23:45:34.345938 ==DQS 0 ==
7387 23:45:34.348689 Final DQS duty delay cell = 0
7388 23:45:34.352490 [0] MAX Duty = 5124%(X100), DQS PI = 18
7389 23:45:34.355141 [0] MIN Duty = 4907%(X100), DQS PI = 8
7390 23:45:34.358804 [0] AVG Duty = 5015%(X100)
7391 23:45:34.359344
7392 23:45:34.359699 ==DQS 1 ==
7393 23:45:34.362094 Final DQS duty delay cell = 0
7394 23:45:34.365634 [0] MAX Duty = 5093%(X100), DQS PI = 26
7395 23:45:34.368419 [0] MIN Duty = 4969%(X100), DQS PI = 56
7396 23:45:34.372079 [0] AVG Duty = 5031%(X100)
7397 23:45:34.372635
7398 23:45:34.375371 CH1 DQS 0 Duty spec in!! Max-Min= 217%
7399 23:45:34.375835
7400 23:45:34.378540 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7401 23:45:34.381990 [DutyScan_Calibration_Flow] ====Done====
7402 23:45:34.382610
7403 23:45:34.385184 [DutyScan_Calibration_Flow] k_type=3
7404 23:45:34.402850
7405 23:45:34.403408 ==DQM 0 ==
7406 23:45:34.405681 Final DQM duty delay cell = 0
7407 23:45:34.409338 [0] MAX Duty = 5218%(X100), DQS PI = 18
7408 23:45:34.412407 [0] MIN Duty = 5031%(X100), DQS PI = 6
7409 23:45:34.415585 [0] AVG Duty = 5124%(X100)
7410 23:45:34.416376
7411 23:45:34.416845 ==DQM 1 ==
7412 23:45:34.418559 Final DQM duty delay cell = 0
7413 23:45:34.422580 [0] MAX Duty = 5125%(X100), DQS PI = 0
7414 23:45:34.425563 [0] MIN Duty = 4938%(X100), DQS PI = 34
7415 23:45:34.429028 [0] AVG Duty = 5031%(X100)
7416 23:45:34.429585
7417 23:45:34.432086 CH1 DQM 0 Duty spec in!! Max-Min= 187%
7418 23:45:34.432551
7419 23:45:34.435006 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7420 23:45:34.438415 [DutyScan_Calibration_Flow] ====Done====
7421 23:45:34.438896
7422 23:45:34.441761 [DutyScan_Calibration_Flow] k_type=2
7423 23:45:34.459085
7424 23:45:34.459632 ==DQ 0 ==
7425 23:45:34.462830 Final DQ duty delay cell = 0
7426 23:45:34.465712 [0] MAX Duty = 5156%(X100), DQS PI = 30
7427 23:45:34.469214 [0] MIN Duty = 4906%(X100), DQS PI = 8
7428 23:45:34.469669 [0] AVG Duty = 5031%(X100)
7429 23:45:34.472275
7430 23:45:34.472766 ==DQ 1 ==
7431 23:45:34.475773 Final DQ duty delay cell = 0
7432 23:45:34.478710 [0] MAX Duty = 5156%(X100), DQS PI = 8
7433 23:45:34.482082 [0] MIN Duty = 4969%(X100), DQS PI = 56
7434 23:45:34.482574 [0] AVG Duty = 5062%(X100)
7435 23:45:34.485486
7436 23:45:34.488816 CH1 DQ 0 Duty spec in!! Max-Min= 250%
7437 23:45:34.489353
7438 23:45:34.492195 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7439 23:45:34.495931 [DutyScan_Calibration_Flow] ====Done====
7440 23:45:34.499049 nWR fixed to 30
7441 23:45:34.499489 [ModeRegInit_LP4] CH0 RK0
7442 23:45:34.501621 [ModeRegInit_LP4] CH0 RK1
7443 23:45:34.505224 [ModeRegInit_LP4] CH1 RK0
7444 23:45:34.508697 [ModeRegInit_LP4] CH1 RK1
7445 23:45:34.509109 match AC timing 5
7446 23:45:34.515223 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7447 23:45:34.518627 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7448 23:45:34.522022 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7449 23:45:34.528975 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7450 23:45:34.531579 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7451 23:45:34.531993 [MiockJmeterHQA]
7452 23:45:34.532316
7453 23:45:34.534764 [DramcMiockJmeter] u1RxGatingPI = 0
7454 23:45:34.538269 0 : 4252, 4027
7455 23:45:34.538689 4 : 4257, 4029
7456 23:45:34.541329 8 : 4255, 4029
7457 23:45:34.541746 12 : 4252, 4027
7458 23:45:34.544934 16 : 4253, 4026
7459 23:45:34.545371 20 : 4363, 4137
7460 23:45:34.545725 24 : 4252, 4026
7461 23:45:34.547914 28 : 4252, 4027
7462 23:45:34.548272 32 : 4252, 4027
7463 23:45:34.551469 36 : 4255, 4029
7464 23:45:34.552075 40 : 4252, 4027
7465 23:45:34.554581 44 : 4363, 4140
7466 23:45:34.554996 48 : 4363, 4137
7467 23:45:34.557733 52 : 4249, 4027
7468 23:45:34.558218 56 : 4250, 4026
7469 23:45:34.558587 60 : 4250, 4027
7470 23:45:34.561052 64 : 4249, 4027
7471 23:45:34.561468 68 : 4253, 4029
7472 23:45:34.564246 72 : 4360, 4138
7473 23:45:34.564665 76 : 4250, 4026
7474 23:45:34.567872 80 : 4250, 4027
7475 23:45:34.568290 84 : 4249, 4027
7476 23:45:34.571394 88 : 4253, 4027
7477 23:45:34.571812 92 : 4250, 363
7478 23:45:34.572143 96 : 4250, 0
7479 23:45:34.574303 100 : 4252, 0
7480 23:45:34.574724 104 : 4250, 0
7481 23:45:34.575054 108 : 4361, 0
7482 23:45:34.577874 112 : 4250, 0
7483 23:45:34.578357 116 : 4360, 0
7484 23:45:34.580866 120 : 4250, 0
7485 23:45:34.581302 124 : 4250, 0
7486 23:45:34.581733 128 : 4250, 0
7487 23:45:34.584300 132 : 4361, 0
7488 23:45:34.584735 136 : 4360, 0
7489 23:45:34.587403 140 : 4249, 0
7490 23:45:34.587838 144 : 4250, 0
7491 23:45:34.588264 148 : 4253, 0
7492 23:45:34.590709 152 : 4360, 0
7493 23:45:34.591144 156 : 4360, 0
7494 23:45:34.593932 160 : 4363, 0
7495 23:45:34.594392 164 : 4250, 0
7496 23:45:34.594826 168 : 4249, 0
7497 23:45:34.597550 172 : 4250, 0
7498 23:45:34.597967 176 : 4250, 0
7499 23:45:34.600702 180 : 4249, 0
7500 23:45:34.601169 184 : 4250, 0
7501 23:45:34.601503 188 : 4253, 0
7502 23:45:34.603885 192 : 4250, 0
7503 23:45:34.604307 196 : 4250, 0
7504 23:45:34.607299 200 : 4253, 0
7505 23:45:34.607720 204 : 4361, 0
7506 23:45:34.608051 208 : 4360, 0
7507 23:45:34.610377 212 : 4363, 0
7508 23:45:34.610797 216 : 4250, 0
7509 23:45:34.611134 220 : 4250, 0
7510 23:45:34.613695 224 : 4250, 164
7511 23:45:34.614113 228 : 4250, 3160
7512 23:45:34.617147 232 : 4253, 4029
7513 23:45:34.617567 236 : 4250, 4026
7514 23:45:34.620895 240 : 4250, 4027
7515 23:45:34.621419 244 : 4249, 4027
7516 23:45:34.623554 248 : 4360, 4137
7517 23:45:34.623975 252 : 4250, 4026
7518 23:45:34.627009 256 : 4250, 4027
7519 23:45:34.627436 260 : 4360, 4138
7520 23:45:34.630247 264 : 4250, 4027
7521 23:45:34.630667 268 : 4250, 4026
7522 23:45:34.633644 272 : 4363, 4139
7523 23:45:34.634065 276 : 4250, 4027
7524 23:45:34.637234 280 : 4250, 4027
7525 23:45:34.637760 284 : 4250, 4026
7526 23:45:34.638095 288 : 4253, 4029
7527 23:45:34.640480 292 : 4250, 4027
7528 23:45:34.640900 296 : 4250, 4027
7529 23:45:34.644001 300 : 4360, 4137
7530 23:45:34.644598 304 : 4250, 4026
7531 23:45:34.646987 308 : 4250, 4027
7532 23:45:34.647406 312 : 4360, 4138
7533 23:45:34.650571 316 : 4249, 4027
7534 23:45:34.650992 320 : 4250, 4027
7535 23:45:34.653373 324 : 4363, 4139
7536 23:45:34.653893 328 : 4250, 4027
7537 23:45:34.656729 332 : 4249, 4027
7538 23:45:34.657149 336 : 4250, 3882
7539 23:45:34.660205 340 : 4253, 1890
7540 23:45:34.660753
7541 23:45:34.661202 MIOCK jitter meter ch=0
7542 23:45:34.661519
7543 23:45:34.663325 1T = (340-92) = 248 dly cells
7544 23:45:34.669860 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 262/100 ps
7545 23:45:34.670338 ==
7546 23:45:34.673263 Dram Type= 6, Freq= 0, CH_0, rank 0
7547 23:45:34.676900 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7548 23:45:34.677417 ==
7549 23:45:34.683485 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7550 23:45:34.686902 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7551 23:45:34.689891 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7552 23:45:34.696125 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7553 23:45:34.706380 [CA 0] Center 43 (13~74) winsize 62
7554 23:45:34.709592 [CA 1] Center 43 (13~74) winsize 62
7555 23:45:34.712609 [CA 2] Center 39 (10~69) winsize 60
7556 23:45:34.716253 [CA 3] Center 38 (9~68) winsize 60
7557 23:45:34.719198 [CA 4] Center 37 (8~66) winsize 59
7558 23:45:34.722845 [CA 5] Center 36 (7~66) winsize 60
7559 23:45:34.723408
7560 23:45:34.726117 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7561 23:45:34.726601
7562 23:45:34.732522 [CATrainingPosCal] consider 1 rank data
7563 23:45:34.733105 u2DelayCellTimex100 = 262/100 ps
7564 23:45:34.739286 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7565 23:45:34.742334 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7566 23:45:34.745786 CA2 delay=39 (10~69),Diff = 3 PI (11 cell)
7567 23:45:34.749072 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7568 23:45:34.753122 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7569 23:45:34.755875 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7570 23:45:34.756337
7571 23:45:34.759130 CA PerBit enable=1, Macro0, CA PI delay=36
7572 23:45:34.759752
7573 23:45:34.762610 [CBTSetCACLKResult] CA Dly = 36
7574 23:45:34.765915 CS Dly: 11 (0~42)
7575 23:45:34.768872 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7576 23:45:34.772116 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7577 23:45:34.772581 ==
7578 23:45:34.775752 Dram Type= 6, Freq= 0, CH_0, rank 1
7579 23:45:34.782326 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7580 23:45:34.782994 ==
7581 23:45:34.785233 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7582 23:45:34.792143 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7583 23:45:34.795185 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7584 23:45:34.801777 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7585 23:45:34.809967 [CA 0] Center 42 (12~73) winsize 62
7586 23:45:34.813248 [CA 1] Center 43 (13~73) winsize 61
7587 23:45:34.816397 [CA 2] Center 37 (8~67) winsize 60
7588 23:45:34.819676 [CA 3] Center 37 (7~67) winsize 61
7589 23:45:34.823132 [CA 4] Center 36 (6~66) winsize 61
7590 23:45:34.826615 [CA 5] Center 35 (5~65) winsize 61
7591 23:45:34.827075
7592 23:45:34.829743 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7593 23:45:34.830361
7594 23:45:34.835936 [CATrainingPosCal] consider 2 rank data
7595 23:45:34.836487 u2DelayCellTimex100 = 262/100 ps
7596 23:45:34.842493 CA0 delay=43 (13~73),Diff = 7 PI (26 cell)
7597 23:45:34.846085 CA1 delay=43 (13~73),Diff = 7 PI (26 cell)
7598 23:45:34.849522 CA2 delay=38 (10~67),Diff = 2 PI (7 cell)
7599 23:45:34.852573 CA3 delay=38 (9~67),Diff = 2 PI (7 cell)
7600 23:45:34.856194 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7601 23:45:34.859801 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7602 23:45:34.860260
7603 23:45:34.862843 CA PerBit enable=1, Macro0, CA PI delay=36
7604 23:45:34.863304
7605 23:45:34.865764 [CBTSetCACLKResult] CA Dly = 36
7606 23:45:34.869108 CS Dly: 12 (0~44)
7607 23:45:34.872539 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7608 23:45:34.875808 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7609 23:45:34.876272
7610 23:45:34.878691 ----->DramcWriteLeveling(PI) begin...
7611 23:45:34.879156 ==
7612 23:45:34.882235 Dram Type= 6, Freq= 0, CH_0, rank 0
7613 23:45:34.888830 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7614 23:45:34.889462 ==
7615 23:45:34.891903 Write leveling (Byte 0): 36 => 36
7616 23:45:34.895246 Write leveling (Byte 1): 27 => 27
7617 23:45:34.898482 DramcWriteLeveling(PI) end<-----
7618 23:45:34.898935
7619 23:45:34.899312 ==
7620 23:45:34.902015 Dram Type= 6, Freq= 0, CH_0, rank 0
7621 23:45:34.905313 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7622 23:45:34.905783 ==
7623 23:45:34.908933 [Gating] SW mode calibration
7624 23:45:34.914990 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7625 23:45:34.922264 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7626 23:45:34.925489 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7627 23:45:34.928503 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7628 23:45:34.934785 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7629 23:45:34.938528 1 4 12 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (1 1)
7630 23:45:34.941560 1 4 16 | B1->B0 | 2323 3434 | 0 0 | (0 0) (1 1)
7631 23:45:34.948459 1 4 20 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7632 23:45:34.951399 1 4 24 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
7633 23:45:34.954620 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7634 23:45:34.961489 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7635 23:45:34.964301 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7636 23:45:34.967896 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7637 23:45:34.974477 1 5 12 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 0)
7638 23:45:34.977412 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7639 23:45:34.981031 1 5 20 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
7640 23:45:34.987639 1 5 24 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (0 0)
7641 23:45:34.990801 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7642 23:45:34.993959 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7643 23:45:35.000895 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7644 23:45:35.004227 1 6 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7645 23:45:35.007216 1 6 12 | B1->B0 | 2323 3d3d | 0 1 | (0 0) (0 0)
7646 23:45:35.014070 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7647 23:45:35.017489 1 6 20 | B1->B0 | 2b2b 4646 | 1 0 | (0 0) (0 0)
7648 23:45:35.020533 1 6 24 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
7649 23:45:35.026787 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7650 23:45:35.031102 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7651 23:45:35.033633 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7652 23:45:35.040136 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7653 23:45:35.043852 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7654 23:45:35.047079 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7655 23:45:35.053416 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7656 23:45:35.056989 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7657 23:45:35.060396 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7658 23:45:35.067119 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7659 23:45:35.070131 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7660 23:45:35.073690 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7661 23:45:35.079775 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7662 23:45:35.083350 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7663 23:45:35.086402 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7664 23:45:35.093147 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7665 23:45:35.096431 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7666 23:45:35.100130 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7667 23:45:35.106628 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7668 23:45:35.109939 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7669 23:45:35.112851 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7670 23:45:35.116476 Total UI for P1: 0, mck2ui 16
7671 23:45:35.119835 best dqsien dly found for B0: ( 1, 9, 10)
7672 23:45:35.123189 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7673 23:45:35.129309 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7674 23:45:35.132810 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7675 23:45:35.135638 Total UI for P1: 0, mck2ui 16
7676 23:45:35.139216 best dqsien dly found for B1: ( 1, 9, 18)
7677 23:45:35.142580 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7678 23:45:35.146413 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7679 23:45:35.146994
7680 23:45:35.152588 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7681 23:45:35.155846 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7682 23:45:35.156310 [Gating] SW calibration Done
7683 23:45:35.158768 ==
7684 23:45:35.162561 Dram Type= 6, Freq= 0, CH_0, rank 0
7685 23:45:35.165769 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7686 23:45:35.166389 ==
7687 23:45:35.166761 RX Vref Scan: 0
7688 23:45:35.167100
7689 23:45:35.169233 RX Vref 0 -> 0, step: 1
7690 23:45:35.169841
7691 23:45:35.172931 RX Delay 0 -> 252, step: 8
7692 23:45:35.175335 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7693 23:45:35.178974 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7694 23:45:35.182531 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7695 23:45:35.188909 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7696 23:45:35.192096 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7697 23:45:35.195436 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7698 23:45:35.198499 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7699 23:45:35.202074 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7700 23:45:35.208907 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7701 23:45:35.212430 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7702 23:45:35.215377 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7703 23:45:35.218351 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7704 23:45:35.221820 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7705 23:45:35.228934 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7706 23:45:35.232096 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7707 23:45:35.234940 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7708 23:45:35.235416 ==
7709 23:45:35.238721 Dram Type= 6, Freq= 0, CH_0, rank 0
7710 23:45:35.244970 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7711 23:45:35.245544 ==
7712 23:45:35.246031 DQS Delay:
7713 23:45:35.246518 DQS0 = 0, DQS1 = 0
7714 23:45:35.248022 DQM Delay:
7715 23:45:35.248494 DQM0 = 136, DQM1 = 126
7716 23:45:35.251557 DQ Delay:
7717 23:45:35.254954 DQ0 =135, DQ1 =139, DQ2 =131, DQ3 =131
7718 23:45:35.258157 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =147
7719 23:45:35.261356 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =119
7720 23:45:35.265387 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =131
7721 23:45:35.265938
7722 23:45:35.266337
7723 23:45:35.266671 ==
7724 23:45:35.267623 Dram Type= 6, Freq= 0, CH_0, rank 0
7725 23:45:35.271156 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7726 23:45:35.274769 ==
7727 23:45:35.275221
7728 23:45:35.275572
7729 23:45:35.275900 TX Vref Scan disable
7730 23:45:35.277752 == TX Byte 0 ==
7731 23:45:35.281572 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7732 23:45:35.284539 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7733 23:45:35.287836 == TX Byte 1 ==
7734 23:45:35.291467 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7735 23:45:35.294586 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7736 23:45:35.297663 ==
7737 23:45:35.301293 Dram Type= 6, Freq= 0, CH_0, rank 0
7738 23:45:35.304647 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7739 23:45:35.305107 ==
7740 23:45:35.317406
7741 23:45:35.320816 TX Vref early break, caculate TX vref
7742 23:45:35.323591 TX Vref=16, minBit 4, minWin=22, winSum=374
7743 23:45:35.327213 TX Vref=18, minBit 7, minWin=23, winSum=385
7744 23:45:35.330519 TX Vref=20, minBit 1, minWin=23, winSum=390
7745 23:45:35.333920 TX Vref=22, minBit 1, minWin=24, winSum=399
7746 23:45:35.336657 TX Vref=24, minBit 4, minWin=24, winSum=406
7747 23:45:35.343400 TX Vref=26, minBit 1, minWin=25, winSum=415
7748 23:45:35.346960 TX Vref=28, minBit 0, minWin=24, winSum=417
7749 23:45:35.350285 TX Vref=30, minBit 4, minWin=24, winSum=408
7750 23:45:35.353379 TX Vref=32, minBit 0, minWin=24, winSum=399
7751 23:45:35.356626 TX Vref=34, minBit 4, minWin=23, winSum=388
7752 23:45:35.363356 [TxChooseVref] Worse bit 1, Min win 25, Win sum 415, Final Vref 26
7753 23:45:35.363926
7754 23:45:35.366710 Final TX Range 0 Vref 26
7755 23:45:35.367172
7756 23:45:35.367535 ==
7757 23:45:35.369936 Dram Type= 6, Freq= 0, CH_0, rank 0
7758 23:45:35.373024 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7759 23:45:35.373533 ==
7760 23:45:35.373994
7761 23:45:35.374459
7762 23:45:35.376709 TX Vref Scan disable
7763 23:45:35.383484 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
7764 23:45:35.384073 == TX Byte 0 ==
7765 23:45:35.386150 u2DelayCellOfst[0]=18 cells (5 PI)
7766 23:45:35.389747 u2DelayCellOfst[1]=18 cells (5 PI)
7767 23:45:35.393082 u2DelayCellOfst[2]=14 cells (4 PI)
7768 23:45:35.396417 u2DelayCellOfst[3]=14 cells (4 PI)
7769 23:45:35.399612 u2DelayCellOfst[4]=11 cells (3 PI)
7770 23:45:35.402937 u2DelayCellOfst[5]=0 cells (0 PI)
7771 23:45:35.406138 u2DelayCellOfst[6]=18 cells (5 PI)
7772 23:45:35.409527 u2DelayCellOfst[7]=22 cells (6 PI)
7773 23:45:35.413079 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7774 23:45:35.415754 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7775 23:45:35.419168 == TX Byte 1 ==
7776 23:45:35.422808 u2DelayCellOfst[8]=0 cells (0 PI)
7777 23:45:35.425804 u2DelayCellOfst[9]=0 cells (0 PI)
7778 23:45:35.428913 u2DelayCellOfst[10]=7 cells (2 PI)
7779 23:45:35.432945 u2DelayCellOfst[11]=0 cells (0 PI)
7780 23:45:35.433511 u2DelayCellOfst[12]=11 cells (3 PI)
7781 23:45:35.435491 u2DelayCellOfst[13]=7 cells (2 PI)
7782 23:45:35.439312 u2DelayCellOfst[14]=11 cells (3 PI)
7783 23:45:35.442493 u2DelayCellOfst[15]=7 cells (2 PI)
7784 23:45:35.448736 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7785 23:45:35.452121 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7786 23:45:35.452596 DramC Write-DBI on
7787 23:45:35.455428 ==
7788 23:45:35.458944 Dram Type= 6, Freq= 0, CH_0, rank 0
7789 23:45:35.462219 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7790 23:45:35.462802 ==
7791 23:45:35.463292
7792 23:45:35.463740
7793 23:45:35.465700 TX Vref Scan disable
7794 23:45:35.466316 == TX Byte 0 ==
7795 23:45:35.471661 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7796 23:45:35.472237 == TX Byte 1 ==
7797 23:45:35.475464 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7798 23:45:35.478349 DramC Write-DBI off
7799 23:45:35.478915
7800 23:45:35.479282 [DATLAT]
7801 23:45:35.481628 Freq=1600, CH0 RK0
7802 23:45:35.482085
7803 23:45:35.482501 DATLAT Default: 0xf
7804 23:45:35.484935 0, 0xFFFF, sum = 0
7805 23:45:35.485406 1, 0xFFFF, sum = 0
7806 23:45:35.488322 2, 0xFFFF, sum = 0
7807 23:45:35.491422 3, 0xFFFF, sum = 0
7808 23:45:35.491893 4, 0xFFFF, sum = 0
7809 23:45:35.494668 5, 0xFFFF, sum = 0
7810 23:45:35.495138 6, 0xFFFF, sum = 0
7811 23:45:35.497979 7, 0xFFFF, sum = 0
7812 23:45:35.498510 8, 0xFFFF, sum = 0
7813 23:45:35.501695 9, 0xFFFF, sum = 0
7814 23:45:35.502486 10, 0xFFFF, sum = 0
7815 23:45:35.504446 11, 0xFFFF, sum = 0
7816 23:45:35.504930 12, 0xFFFF, sum = 0
7817 23:45:35.508485 13, 0xFFFF, sum = 0
7818 23:45:35.509057 14, 0x0, sum = 1
7819 23:45:35.511737 15, 0x0, sum = 2
7820 23:45:35.512210 16, 0x0, sum = 3
7821 23:45:35.514603 17, 0x0, sum = 4
7822 23:45:35.515073 best_step = 15
7823 23:45:35.515435
7824 23:45:35.515838 ==
7825 23:45:35.517775 Dram Type= 6, Freq= 0, CH_0, rank 0
7826 23:45:35.524696 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7827 23:45:35.525244 ==
7828 23:45:35.525613 RX Vref Scan: 1
7829 23:45:35.525956
7830 23:45:35.527730 Set Vref Range= 24 -> 127
7831 23:45:35.528258
7832 23:45:35.530742 RX Vref 24 -> 127, step: 1
7833 23:45:35.531204
7834 23:45:35.531564 RX Delay 11 -> 252, step: 4
7835 23:45:35.534429
7836 23:45:35.534999 Set Vref, RX VrefLevel [Byte0]: 24
7837 23:45:35.537839 [Byte1]: 24
7838 23:45:35.541606
7839 23:45:35.542025 Set Vref, RX VrefLevel [Byte0]: 25
7840 23:45:35.545067 [Byte1]: 25
7841 23:45:35.549433
7842 23:45:35.549854 Set Vref, RX VrefLevel [Byte0]: 26
7843 23:45:35.552517 [Byte1]: 26
7844 23:45:35.557353
7845 23:45:35.557884 Set Vref, RX VrefLevel [Byte0]: 27
7846 23:45:35.560362 [Byte1]: 27
7847 23:45:35.564795
7848 23:45:35.565213 Set Vref, RX VrefLevel [Byte0]: 28
7849 23:45:35.567954 [Byte1]: 28
7850 23:45:35.572136
7851 23:45:35.572657 Set Vref, RX VrefLevel [Byte0]: 29
7852 23:45:35.575444 [Byte1]: 29
7853 23:45:35.580039
7854 23:45:35.580556 Set Vref, RX VrefLevel [Byte0]: 30
7855 23:45:35.583244 [Byte1]: 30
7856 23:45:35.587776
7857 23:45:35.588369 Set Vref, RX VrefLevel [Byte0]: 31
7858 23:45:35.590919 [Byte1]: 31
7859 23:45:35.594690
7860 23:45:35.595105 Set Vref, RX VrefLevel [Byte0]: 32
7861 23:45:35.598659 [Byte1]: 32
7862 23:45:35.602851
7863 23:45:35.603360 Set Vref, RX VrefLevel [Byte0]: 33
7864 23:45:35.605844 [Byte1]: 33
7865 23:45:35.610435
7866 23:45:35.610989 Set Vref, RX VrefLevel [Byte0]: 34
7867 23:45:35.613651 [Byte1]: 34
7868 23:45:35.618025
7869 23:45:35.618583 Set Vref, RX VrefLevel [Byte0]: 35
7870 23:45:35.620957 [Byte1]: 35
7871 23:45:35.625570
7872 23:45:35.626021 Set Vref, RX VrefLevel [Byte0]: 36
7873 23:45:35.628587 [Byte1]: 36
7874 23:45:35.633151
7875 23:45:35.633678 Set Vref, RX VrefLevel [Byte0]: 37
7876 23:45:35.636147 [Byte1]: 37
7877 23:45:35.640470
7878 23:45:35.640982 Set Vref, RX VrefLevel [Byte0]: 38
7879 23:45:35.643846 [Byte1]: 38
7880 23:45:35.648067
7881 23:45:35.648476 Set Vref, RX VrefLevel [Byte0]: 39
7882 23:45:35.651581 [Byte1]: 39
7883 23:45:35.655816
7884 23:45:35.656362 Set Vref, RX VrefLevel [Byte0]: 40
7885 23:45:35.658804 [Byte1]: 40
7886 23:45:35.663516
7887 23:45:35.663922 Set Vref, RX VrefLevel [Byte0]: 41
7888 23:45:35.666679 [Byte1]: 41
7889 23:45:35.671415
7890 23:45:35.671925 Set Vref, RX VrefLevel [Byte0]: 42
7891 23:45:35.674271 [Byte1]: 42
7892 23:45:35.678589
7893 23:45:35.679090 Set Vref, RX VrefLevel [Byte0]: 43
7894 23:45:35.681906 [Byte1]: 43
7895 23:45:35.686689
7896 23:45:35.687097 Set Vref, RX VrefLevel [Byte0]: 44
7897 23:45:35.689450 [Byte1]: 44
7898 23:45:35.693904
7899 23:45:35.694426 Set Vref, RX VrefLevel [Byte0]: 45
7900 23:45:35.697180 [Byte1]: 45
7901 23:45:35.701505
7902 23:45:35.702068 Set Vref, RX VrefLevel [Byte0]: 46
7903 23:45:35.708534 [Byte1]: 46
7904 23:45:35.709078
7905 23:45:35.711255 Set Vref, RX VrefLevel [Byte0]: 47
7906 23:45:35.714514 [Byte1]: 47
7907 23:45:35.714933
7908 23:45:35.717570 Set Vref, RX VrefLevel [Byte0]: 48
7909 23:45:35.720970 [Byte1]: 48
7910 23:45:35.724462
7911 23:45:35.724915 Set Vref, RX VrefLevel [Byte0]: 49
7912 23:45:35.727711 [Byte1]: 49
7913 23:45:35.732237
7914 23:45:35.732668 Set Vref, RX VrefLevel [Byte0]: 50
7915 23:45:35.735332 [Byte1]: 50
7916 23:45:35.739936
7917 23:45:35.740443 Set Vref, RX VrefLevel [Byte0]: 51
7918 23:45:35.742951 [Byte1]: 51
7919 23:45:35.746988
7920 23:45:35.747400 Set Vref, RX VrefLevel [Byte0]: 52
7921 23:45:35.750297 [Byte1]: 52
7922 23:45:35.754698
7923 23:45:35.755220 Set Vref, RX VrefLevel [Byte0]: 53
7924 23:45:35.758536 [Byte1]: 53
7925 23:45:35.762900
7926 23:45:35.763418 Set Vref, RX VrefLevel [Byte0]: 54
7927 23:45:35.766125 [Byte1]: 54
7928 23:45:35.770331
7929 23:45:35.770898 Set Vref, RX VrefLevel [Byte0]: 55
7930 23:45:35.773455 [Byte1]: 55
7931 23:45:35.777604
7932 23:45:35.778208 Set Vref, RX VrefLevel [Byte0]: 56
7933 23:45:35.781263 [Byte1]: 56
7934 23:45:35.785755
7935 23:45:35.786362 Set Vref, RX VrefLevel [Byte0]: 57
7936 23:45:35.788358 [Byte1]: 57
7937 23:45:35.793282
7938 23:45:35.793839 Set Vref, RX VrefLevel [Byte0]: 58
7939 23:45:35.796381 [Byte1]: 58
7940 23:45:35.800492
7941 23:45:35.800945 Set Vref, RX VrefLevel [Byte0]: 59
7942 23:45:35.807373 [Byte1]: 59
7943 23:45:35.807832
7944 23:45:35.810584 Set Vref, RX VrefLevel [Byte0]: 60
7945 23:45:35.813826 [Byte1]: 60
7946 23:45:35.814429
7947 23:45:35.816848 Set Vref, RX VrefLevel [Byte0]: 61
7948 23:45:35.820081 [Byte1]: 61
7949 23:45:35.823874
7950 23:45:35.824430 Set Vref, RX VrefLevel [Byte0]: 62
7951 23:45:35.826907 [Byte1]: 62
7952 23:45:35.831665
7953 23:45:35.832324 Set Vref, RX VrefLevel [Byte0]: 63
7954 23:45:35.834236 [Byte1]: 63
7955 23:45:35.838529
7956 23:45:35.839077 Set Vref, RX VrefLevel [Byte0]: 64
7957 23:45:35.841968 [Byte1]: 64
7958 23:45:35.846596
7959 23:45:35.847153 Set Vref, RX VrefLevel [Byte0]: 65
7960 23:45:35.849476 [Byte1]: 65
7961 23:45:35.853626
7962 23:45:35.854077 Set Vref, RX VrefLevel [Byte0]: 66
7963 23:45:35.857243 [Byte1]: 66
7964 23:45:35.861240
7965 23:45:35.861696 Set Vref, RX VrefLevel [Byte0]: 67
7966 23:45:35.864744 [Byte1]: 67
7967 23:45:35.869283
7968 23:45:35.869815 Set Vref, RX VrefLevel [Byte0]: 68
7969 23:45:35.872279 [Byte1]: 68
7970 23:45:35.876612
7971 23:45:35.877124 Set Vref, RX VrefLevel [Byte0]: 69
7972 23:45:35.880022 [Byte1]: 69
7973 23:45:35.884541
7974 23:45:35.885093 Set Vref, RX VrefLevel [Byte0]: 70
7975 23:45:35.887465 [Byte1]: 70
7976 23:45:35.891640
7977 23:45:35.892098 Set Vref, RX VrefLevel [Byte0]: 71
7978 23:45:35.895235 [Byte1]: 71
7979 23:45:35.899270
7980 23:45:35.899728 Set Vref, RX VrefLevel [Byte0]: 72
7981 23:45:35.906568 [Byte1]: 72
7982 23:45:35.907116
7983 23:45:35.909128 Set Vref, RX VrefLevel [Byte0]: 73
7984 23:45:35.912463 [Byte1]: 73
7985 23:45:35.913019
7986 23:45:35.915728 Set Vref, RX VrefLevel [Byte0]: 74
7987 23:45:35.918851 [Byte1]: 74
7988 23:45:35.922244
7989 23:45:35.922706 Set Vref, RX VrefLevel [Byte0]: 75
7990 23:45:35.925949 [Byte1]: 75
7991 23:45:35.929965
7992 23:45:35.930613 Set Vref, RX VrefLevel [Byte0]: 76
7993 23:45:35.933061 [Byte1]: 76
7994 23:45:35.938040
7995 23:45:35.938564 Set Vref, RX VrefLevel [Byte0]: 77
7996 23:45:35.940678 [Byte1]: 77
7997 23:45:35.945094
7998 23:45:35.945507 Set Vref, RX VrefLevel [Byte0]: 78
7999 23:45:35.948560 [Byte1]: 78
8000 23:45:35.952631
8001 23:45:35.953044 Final RX Vref Byte 0 = 64 to rank0
8002 23:45:35.956113 Final RX Vref Byte 1 = 57 to rank0
8003 23:45:35.959710 Final RX Vref Byte 0 = 64 to rank1
8004 23:45:35.963129 Final RX Vref Byte 1 = 57 to rank1==
8005 23:45:35.965935 Dram Type= 6, Freq= 0, CH_0, rank 0
8006 23:45:35.972937 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8007 23:45:35.973455 ==
8008 23:45:35.973799 DQS Delay:
8009 23:45:35.975649 DQS0 = 0, DQS1 = 0
8010 23:45:35.976077 DQM Delay:
8011 23:45:35.976403 DQM0 = 133, DQM1 = 122
8012 23:45:35.979056 DQ Delay:
8013 23:45:35.982548 DQ0 =130, DQ1 =134, DQ2 =132, DQ3 =132
8014 23:45:35.986482 DQ4 =134, DQ5 =122, DQ6 =140, DQ7 =142
8015 23:45:35.989174 DQ8 =114, DQ9 =110, DQ10 =122, DQ11 =118
8016 23:45:35.992493 DQ12 =128, DQ13 =126, DQ14 =132, DQ15 =128
8017 23:45:35.992949
8018 23:45:35.993308
8019 23:45:35.993639
8020 23:45:35.995767 [DramC_TX_OE_Calibration] TA2
8021 23:45:35.998763 Original DQ_B0 (3 6) =30, OEN = 27
8022 23:45:36.002399 Original DQ_B1 (3 6) =30, OEN = 27
8023 23:45:36.005800 24, 0x0, End_B0=24 End_B1=24
8024 23:45:36.008778 25, 0x0, End_B0=25 End_B1=25
8025 23:45:36.009242 26, 0x0, End_B0=26 End_B1=26
8026 23:45:36.012115 27, 0x0, End_B0=27 End_B1=27
8027 23:45:36.015396 28, 0x0, End_B0=28 End_B1=28
8028 23:45:36.018628 29, 0x0, End_B0=29 End_B1=29
8029 23:45:36.019208 30, 0x0, End_B0=30 End_B1=30
8030 23:45:36.022016 31, 0x4141, End_B0=30 End_B1=30
8031 23:45:36.025830 Byte0 end_step=30 best_step=27
8032 23:45:36.028545 Byte1 end_step=30 best_step=27
8033 23:45:36.032042 Byte0 TX OE(2T, 0.5T) = (3, 3)
8034 23:45:36.035380 Byte1 TX OE(2T, 0.5T) = (3, 3)
8035 23:45:36.035845
8036 23:45:36.036214
8037 23:45:36.042496 [DQSOSCAuto] RK0, (LSB)MR18= 0x2112, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 393 ps
8038 23:45:36.045655 CH0 RK0: MR19=303, MR18=2112
8039 23:45:36.051704 CH0_RK0: MR19=0x303, MR18=0x2112, DQSOSC=393, MR23=63, INC=23, DEC=15
8040 23:45:36.052252
8041 23:45:36.054989 ----->DramcWriteLeveling(PI) begin...
8042 23:45:36.055450 ==
8043 23:45:36.058830 Dram Type= 6, Freq= 0, CH_0, rank 1
8044 23:45:36.061645 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8045 23:45:36.062244 ==
8046 23:45:36.065274 Write leveling (Byte 0): 36 => 36
8047 23:45:36.068034 Write leveling (Byte 1): 29 => 29
8048 23:45:36.071577 DramcWriteLeveling(PI) end<-----
8049 23:45:36.072060
8050 23:45:36.072418 ==
8051 23:45:36.075194 Dram Type= 6, Freq= 0, CH_0, rank 1
8052 23:45:36.078416 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8053 23:45:36.081569 ==
8054 23:45:36.082074 [Gating] SW mode calibration
8055 23:45:36.091131 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8056 23:45:36.094531 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8057 23:45:36.098028 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8058 23:45:36.104283 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8059 23:45:36.107989 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8060 23:45:36.110869 1 4 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8061 23:45:36.117969 1 4 16 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
8062 23:45:36.121082 1 4 20 | B1->B0 | 2c2b 3434 | 1 1 | (0 0) (1 1)
8063 23:45:36.124597 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8064 23:45:36.130852 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8065 23:45:36.133838 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8066 23:45:36.137221 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8067 23:45:36.143788 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8068 23:45:36.147040 1 5 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8069 23:45:36.150309 1 5 16 | B1->B0 | 3434 2424 | 1 0 | (1 0) (1 1)
8070 23:45:36.157165 1 5 20 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
8071 23:45:36.160470 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8072 23:45:36.163899 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8073 23:45:36.170128 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8074 23:45:36.173714 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8075 23:45:36.176807 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8076 23:45:36.183421 1 6 12 | B1->B0 | 2323 2c2b | 0 1 | (0 0) (0 0)
8077 23:45:36.186783 1 6 16 | B1->B0 | 2c2c 4444 | 1 0 | (1 1) (0 0)
8078 23:45:36.189930 1 6 20 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
8079 23:45:36.196474 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8080 23:45:36.199716 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8081 23:45:36.206627 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8082 23:45:36.209384 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8083 23:45:36.213378 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8084 23:45:36.219699 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8085 23:45:36.223315 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8086 23:45:36.226323 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8087 23:45:36.232568 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8088 23:45:36.236248 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8089 23:45:36.239400 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8090 23:45:36.245835 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8091 23:45:36.249634 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8092 23:45:36.252482 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8093 23:45:36.258589 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8094 23:45:36.262358 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8095 23:45:36.265785 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8096 23:45:36.272279 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8097 23:45:36.275403 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8098 23:45:36.278553 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8099 23:45:36.285499 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8100 23:45:36.288626 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8101 23:45:36.292178 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8102 23:45:36.294977 Total UI for P1: 0, mck2ui 16
8103 23:45:36.298699 best dqsien dly found for B0: ( 1, 9, 12)
8104 23:45:36.304818 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8105 23:45:36.308325 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8106 23:45:36.311494 Total UI for P1: 0, mck2ui 16
8107 23:45:36.314762 best dqsien dly found for B1: ( 1, 9, 18)
8108 23:45:36.318570 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8109 23:45:36.321733 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8110 23:45:36.322249
8111 23:45:36.325120 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8112 23:45:36.328400 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8113 23:45:36.331049 [Gating] SW calibration Done
8114 23:45:36.331514 ==
8115 23:45:36.334810 Dram Type= 6, Freq= 0, CH_0, rank 1
8116 23:45:36.341086 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8117 23:45:36.341653 ==
8118 23:45:36.342023 RX Vref Scan: 0
8119 23:45:36.342438
8120 23:45:36.344170 RX Vref 0 -> 0, step: 1
8121 23:45:36.344631
8122 23:45:36.347469 RX Delay 0 -> 252, step: 8
8123 23:45:36.350637 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8124 23:45:36.354350 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8125 23:45:36.357930 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8126 23:45:36.360966 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8127 23:45:36.367230 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8128 23:45:36.370543 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8129 23:45:36.374419 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8130 23:45:36.377217 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8131 23:45:36.380878 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8132 23:45:36.387192 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8133 23:45:36.390630 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8134 23:45:36.393484 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8135 23:45:36.397067 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8136 23:45:36.404304 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8137 23:45:36.406744 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8138 23:45:36.410549 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8139 23:45:36.411114 ==
8140 23:45:36.413588 Dram Type= 6, Freq= 0, CH_0, rank 1
8141 23:45:36.417412 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8142 23:45:36.417981 ==
8143 23:45:36.420279 DQS Delay:
8144 23:45:36.420839 DQS0 = 0, DQS1 = 0
8145 23:45:36.423303 DQM Delay:
8146 23:45:36.423766 DQM0 = 132, DQM1 = 128
8147 23:45:36.427137 DQ Delay:
8148 23:45:36.430150 DQ0 =127, DQ1 =135, DQ2 =127, DQ3 =127
8149 23:45:36.433637 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8150 23:45:36.436771 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =127
8151 23:45:36.440121 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =135
8152 23:45:36.440689
8153 23:45:36.441054
8154 23:45:36.441388 ==
8155 23:45:36.442876 Dram Type= 6, Freq= 0, CH_0, rank 1
8156 23:45:36.446600 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8157 23:45:36.447067 ==
8158 23:45:36.449482
8159 23:45:36.449941
8160 23:45:36.450354 TX Vref Scan disable
8161 23:45:36.452748 == TX Byte 0 ==
8162 23:45:36.456181 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8163 23:45:36.459206 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8164 23:45:36.462935 == TX Byte 1 ==
8165 23:45:36.466477 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8166 23:45:36.469240 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8167 23:45:36.469707 ==
8168 23:45:36.473239 Dram Type= 6, Freq= 0, CH_0, rank 1
8169 23:45:36.479133 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8170 23:45:36.479605 ==
8171 23:45:36.492378
8172 23:45:36.494842 TX Vref early break, caculate TX vref
8173 23:45:36.498425 TX Vref=16, minBit 1, minWin=22, winSum=378
8174 23:45:36.501442 TX Vref=18, minBit 3, minWin=22, winSum=387
8175 23:45:36.504826 TX Vref=20, minBit 1, minWin=23, winSum=398
8176 23:45:36.508072 TX Vref=22, minBit 0, minWin=24, winSum=406
8177 23:45:36.511643 TX Vref=24, minBit 1, minWin=24, winSum=410
8178 23:45:36.518052 TX Vref=26, minBit 0, minWin=24, winSum=415
8179 23:45:36.522037 TX Vref=28, minBit 1, minWin=24, winSum=417
8180 23:45:36.524592 TX Vref=30, minBit 0, minWin=24, winSum=403
8181 23:45:36.528288 TX Vref=32, minBit 7, minWin=23, winSum=397
8182 23:45:36.531529 TX Vref=34, minBit 2, minWin=23, winSum=390
8183 23:45:36.537695 [TxChooseVref] Worse bit 1, Min win 24, Win sum 417, Final Vref 28
8184 23:45:36.538207
8185 23:45:36.541898 Final TX Range 0 Vref 28
8186 23:45:36.542517
8187 23:45:36.542883 ==
8188 23:45:36.544494 Dram Type= 6, Freq= 0, CH_0, rank 1
8189 23:45:36.547960 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8190 23:45:36.548424 ==
8191 23:45:36.548789
8192 23:45:36.549123
8193 23:45:36.550791 TX Vref Scan disable
8194 23:45:36.557794 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8195 23:45:36.558296 == TX Byte 0 ==
8196 23:45:36.561362 u2DelayCellOfst[0]=11 cells (3 PI)
8197 23:45:36.564667 u2DelayCellOfst[1]=14 cells (4 PI)
8198 23:45:36.567276 u2DelayCellOfst[2]=11 cells (3 PI)
8199 23:45:36.570757 u2DelayCellOfst[3]=14 cells (4 PI)
8200 23:45:36.574625 u2DelayCellOfst[4]=7 cells (2 PI)
8201 23:45:36.577728 u2DelayCellOfst[5]=0 cells (0 PI)
8202 23:45:36.580909 u2DelayCellOfst[6]=14 cells (4 PI)
8203 23:45:36.583989 u2DelayCellOfst[7]=18 cells (5 PI)
8204 23:45:36.587881 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8205 23:45:36.590821 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8206 23:45:36.594006 == TX Byte 1 ==
8207 23:45:36.597260 u2DelayCellOfst[8]=0 cells (0 PI)
8208 23:45:36.600778 u2DelayCellOfst[9]=3 cells (1 PI)
8209 23:45:36.603534 u2DelayCellOfst[10]=7 cells (2 PI)
8210 23:45:36.606948 u2DelayCellOfst[11]=3 cells (1 PI)
8211 23:45:36.607410 u2DelayCellOfst[12]=14 cells (4 PI)
8212 23:45:36.610557 u2DelayCellOfst[13]=14 cells (4 PI)
8213 23:45:36.614087 u2DelayCellOfst[14]=18 cells (5 PI)
8214 23:45:36.617300 u2DelayCellOfst[15]=11 cells (3 PI)
8215 23:45:36.623348 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8216 23:45:36.626889 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8217 23:45:36.627369 DramC Write-DBI on
8218 23:45:36.630281 ==
8219 23:45:36.633683 Dram Type= 6, Freq= 0, CH_0, rank 1
8220 23:45:36.637293 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8221 23:45:36.637899 ==
8222 23:45:36.638486
8223 23:45:36.638848
8224 23:45:36.640158 TX Vref Scan disable
8225 23:45:36.640620 == TX Byte 0 ==
8226 23:45:36.646816 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8227 23:45:36.647280 == TX Byte 1 ==
8228 23:45:36.650326 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8229 23:45:36.653189 DramC Write-DBI off
8230 23:45:36.653651
8231 23:45:36.654017 [DATLAT]
8232 23:45:36.657273 Freq=1600, CH0 RK1
8233 23:45:36.657838
8234 23:45:36.658247 DATLAT Default: 0xf
8235 23:45:36.660201 0, 0xFFFF, sum = 0
8236 23:45:36.660672 1, 0xFFFF, sum = 0
8237 23:45:36.663445 2, 0xFFFF, sum = 0
8238 23:45:36.663913 3, 0xFFFF, sum = 0
8239 23:45:36.666208 4, 0xFFFF, sum = 0
8240 23:45:36.669710 5, 0xFFFF, sum = 0
8241 23:45:36.670221 6, 0xFFFF, sum = 0
8242 23:45:36.672962 7, 0xFFFF, sum = 0
8243 23:45:36.673429 8, 0xFFFF, sum = 0
8244 23:45:36.676277 9, 0xFFFF, sum = 0
8245 23:45:36.676703 10, 0xFFFF, sum = 0
8246 23:45:36.679922 11, 0xFFFF, sum = 0
8247 23:45:36.680449 12, 0xFFFF, sum = 0
8248 23:45:36.682706 13, 0xFFFF, sum = 0
8249 23:45:36.683138 14, 0x0, sum = 1
8250 23:45:36.686357 15, 0x0, sum = 2
8251 23:45:36.686782 16, 0x0, sum = 3
8252 23:45:36.689857 17, 0x0, sum = 4
8253 23:45:36.690655 best_step = 15
8254 23:45:36.691143
8255 23:45:36.691597 ==
8256 23:45:36.692613 Dram Type= 6, Freq= 0, CH_0, rank 1
8257 23:45:36.699389 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8258 23:45:36.699910 ==
8259 23:45:36.700250 RX Vref Scan: 0
8260 23:45:36.700560
8261 23:45:36.702748 RX Vref 0 -> 0, step: 1
8262 23:45:36.703183
8263 23:45:36.705906 RX Delay 11 -> 252, step: 4
8264 23:45:36.709081 iDelay=195, Bit 0, Center 128 (79 ~ 178) 100
8265 23:45:36.712386 iDelay=195, Bit 1, Center 134 (79 ~ 190) 112
8266 23:45:36.715743 iDelay=195, Bit 2, Center 126 (75 ~ 178) 104
8267 23:45:36.722607 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8268 23:45:36.725576 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
8269 23:45:36.728850 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8270 23:45:36.732248 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8271 23:45:36.735692 iDelay=195, Bit 7, Center 138 (87 ~ 190) 104
8272 23:45:36.742421 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8273 23:45:36.745382 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8274 23:45:36.749026 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8275 23:45:36.752734 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8276 23:45:36.758592 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8277 23:45:36.761946 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8278 23:45:36.765937 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8279 23:45:36.768485 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8280 23:45:36.768945 ==
8281 23:45:36.771656 Dram Type= 6, Freq= 0, CH_0, rank 1
8282 23:45:36.778450 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8283 23:45:36.778889 ==
8284 23:45:36.779329 DQS Delay:
8285 23:45:36.779744 DQS0 = 0, DQS1 = 0
8286 23:45:36.781471 DQM Delay:
8287 23:45:36.781868 DQM0 = 130, DQM1 = 125
8288 23:45:36.785160 DQ Delay:
8289 23:45:36.788865 DQ0 =128, DQ1 =134, DQ2 =126, DQ3 =128
8290 23:45:36.791413 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =138
8291 23:45:36.795277 DQ8 =114, DQ9 =112, DQ10 =126, DQ11 =120
8292 23:45:36.798048 DQ12 =132, DQ13 =132, DQ14 =136, DQ15 =132
8293 23:45:36.798602
8294 23:45:36.799047
8295 23:45:36.799460
8296 23:45:36.801597 [DramC_TX_OE_Calibration] TA2
8297 23:45:36.804796 Original DQ_B0 (3 6) =30, OEN = 27
8298 23:45:36.808019 Original DQ_B1 (3 6) =30, OEN = 27
8299 23:45:36.811542 24, 0x0, End_B0=24 End_B1=24
8300 23:45:36.811966 25, 0x0, End_B0=25 End_B1=25
8301 23:45:36.814906 26, 0x0, End_B0=26 End_B1=26
8302 23:45:36.818017 27, 0x0, End_B0=27 End_B1=27
8303 23:45:36.821507 28, 0x0, End_B0=28 End_B1=28
8304 23:45:36.824660 29, 0x0, End_B0=29 End_B1=29
8305 23:45:36.825082 30, 0x0, End_B0=30 End_B1=30
8306 23:45:36.827492 31, 0x4141, End_B0=30 End_B1=30
8307 23:45:36.831268 Byte0 end_step=30 best_step=27
8308 23:45:36.834132 Byte1 end_step=30 best_step=27
8309 23:45:36.837740 Byte0 TX OE(2T, 0.5T) = (3, 3)
8310 23:45:36.840881 Byte1 TX OE(2T, 0.5T) = (3, 3)
8311 23:45:36.841298
8312 23:45:36.841623
8313 23:45:36.848044 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f03, (MSB)MR19= 0x303, tDQSOscB0 = 408 ps tDQSOscB1 = 394 ps
8314 23:45:36.851055 CH0 RK1: MR19=303, MR18=1F03
8315 23:45:36.858199 CH0_RK1: MR19=0x303, MR18=0x1F03, DQSOSC=394, MR23=63, INC=23, DEC=15
8316 23:45:36.860912 [RxdqsGatingPostProcess] freq 1600
8317 23:45:36.864184 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8318 23:45:36.867351 best DQS0 dly(2T, 0.5T) = (1, 1)
8319 23:45:36.870721 best DQS1 dly(2T, 0.5T) = (1, 1)
8320 23:45:36.873922 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8321 23:45:36.877426 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8322 23:45:36.880905 best DQS0 dly(2T, 0.5T) = (1, 1)
8323 23:45:36.883827 best DQS1 dly(2T, 0.5T) = (1, 1)
8324 23:45:36.887260 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8325 23:45:36.890856 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8326 23:45:36.893834 Pre-setting of DQS Precalculation
8327 23:45:36.897085 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8328 23:45:36.897665 ==
8329 23:45:36.900739 Dram Type= 6, Freq= 0, CH_1, rank 0
8330 23:45:36.906879 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8331 23:45:36.907350 ==
8332 23:45:36.910600 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8333 23:45:36.917106 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8334 23:45:36.920281 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8335 23:45:36.926973 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8336 23:45:36.934271 [CA 0] Center 41 (12~71) winsize 60
8337 23:45:36.937632 [CA 1] Center 42 (12~72) winsize 61
8338 23:45:36.941073 [CA 2] Center 36 (7~66) winsize 60
8339 23:45:36.944056 [CA 3] Center 36 (7~65) winsize 59
8340 23:45:36.947680 [CA 4] Center 37 (8~66) winsize 59
8341 23:45:36.950658 [CA 5] Center 36 (7~66) winsize 60
8342 23:45:36.951072
8343 23:45:36.954007 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8344 23:45:36.954672
8345 23:45:36.960712 [CATrainingPosCal] consider 1 rank data
8346 23:45:36.961254 u2DelayCellTimex100 = 262/100 ps
8347 23:45:36.967297 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8348 23:45:36.970676 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8349 23:45:36.973880 CA2 delay=36 (7~66),Diff = 0 PI (0 cell)
8350 23:45:36.977242 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8351 23:45:36.980580 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8352 23:45:36.983629 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8353 23:45:36.984087
8354 23:45:36.986825 CA PerBit enable=1, Macro0, CA PI delay=36
8355 23:45:36.987284
8356 23:45:36.990299 [CBTSetCACLKResult] CA Dly = 36
8357 23:45:36.993714 CS Dly: 9 (0~40)
8358 23:45:36.996840 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8359 23:45:37.000339 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8360 23:45:37.000755 ==
8361 23:45:37.003523 Dram Type= 6, Freq= 0, CH_1, rank 1
8362 23:45:37.010217 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8363 23:45:37.010801 ==
8364 23:45:37.013274 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8365 23:45:37.019935 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8366 23:45:37.023040 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8367 23:45:37.029387 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8368 23:45:37.037822 [CA 0] Center 42 (13~72) winsize 60
8369 23:45:37.041134 [CA 1] Center 43 (13~73) winsize 61
8370 23:45:37.044360 [CA 2] Center 37 (8~67) winsize 60
8371 23:45:37.047704 [CA 3] Center 37 (8~67) winsize 60
8372 23:45:37.050643 [CA 4] Center 38 (9~67) winsize 59
8373 23:45:37.053745 [CA 5] Center 37 (8~67) winsize 60
8374 23:45:37.054227
8375 23:45:37.056964 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8376 23:45:37.057413
8377 23:45:37.064111 [CATrainingPosCal] consider 2 rank data
8378 23:45:37.064663 u2DelayCellTimex100 = 262/100 ps
8379 23:45:37.070589 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8380 23:45:37.073859 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8381 23:45:37.076827 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8382 23:45:37.080348 CA3 delay=36 (8~65),Diff = 0 PI (0 cell)
8383 23:45:37.083470 CA4 delay=37 (9~66),Diff = 1 PI (3 cell)
8384 23:45:37.086585 CA5 delay=37 (8~66),Diff = 1 PI (3 cell)
8385 23:45:37.087039
8386 23:45:37.090474 CA PerBit enable=1, Macro0, CA PI delay=36
8387 23:45:37.091030
8388 23:45:37.093493 [CBTSetCACLKResult] CA Dly = 36
8389 23:45:37.096490 CS Dly: 10 (0~43)
8390 23:45:37.100211 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8391 23:45:37.103404 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8392 23:45:37.103856
8393 23:45:37.106275 ----->DramcWriteLeveling(PI) begin...
8394 23:45:37.109846 ==
8395 23:45:37.110438 Dram Type= 6, Freq= 0, CH_1, rank 0
8396 23:45:37.116253 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8397 23:45:37.116845 ==
8398 23:45:37.119952 Write leveling (Byte 0): 24 => 24
8399 23:45:37.122911 Write leveling (Byte 1): 26 => 26
8400 23:45:37.126295 DramcWriteLeveling(PI) end<-----
8401 23:45:37.126894
8402 23:45:37.127459 ==
8403 23:45:37.130075 Dram Type= 6, Freq= 0, CH_1, rank 0
8404 23:45:37.132748 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8405 23:45:37.133201 ==
8406 23:45:37.136686 [Gating] SW mode calibration
8407 23:45:37.142448 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8408 23:45:37.149256 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8409 23:45:37.152558 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8410 23:45:37.156171 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8411 23:45:37.162942 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8412 23:45:37.166092 1 4 12 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
8413 23:45:37.169415 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8414 23:45:37.176171 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8415 23:45:37.179510 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8416 23:45:37.182760 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8417 23:45:37.189109 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8418 23:45:37.192179 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8419 23:45:37.195771 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8420 23:45:37.202273 1 5 12 | B1->B0 | 3232 2727 | 0 0 | (1 0) (1 0)
8421 23:45:37.205467 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8422 23:45:37.208923 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8423 23:45:37.215491 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8424 23:45:37.218510 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8425 23:45:37.222584 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8426 23:45:37.228525 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8427 23:45:37.231737 1 6 8 | B1->B0 | 2525 2323 | 0 1 | (0 0) (0 0)
8428 23:45:37.235670 1 6 12 | B1->B0 | 3d3d 4141 | 0 0 | (0 0) (0 0)
8429 23:45:37.241875 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8430 23:45:37.245041 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8431 23:45:37.248675 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8432 23:45:37.254851 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8433 23:45:37.258579 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8434 23:45:37.261401 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8435 23:45:37.268238 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8436 23:45:37.271611 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8437 23:45:37.274975 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8438 23:45:37.278419 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8439 23:45:37.284988 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8440 23:45:37.288189 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8441 23:45:37.291384 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8442 23:45:37.297929 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8443 23:45:37.301258 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8444 23:45:37.304427 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8445 23:45:37.311065 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8446 23:45:37.314331 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8447 23:45:37.317877 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8448 23:45:37.324734 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8449 23:45:37.327717 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8450 23:45:37.330775 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8451 23:45:37.338400 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8452 23:45:37.341645 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8453 23:45:37.344410 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8454 23:45:37.347451 Total UI for P1: 0, mck2ui 16
8455 23:45:37.350767 best dqsien dly found for B0: ( 1, 9, 10)
8456 23:45:37.353849 Total UI for P1: 0, mck2ui 16
8457 23:45:37.357389 best dqsien dly found for B1: ( 1, 9, 12)
8458 23:45:37.360800 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8459 23:45:37.367511 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8460 23:45:37.368076
8461 23:45:37.370627 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8462 23:45:37.373867 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8463 23:45:37.377038 [Gating] SW calibration Done
8464 23:45:37.377601 ==
8465 23:45:37.380512 Dram Type= 6, Freq= 0, CH_1, rank 0
8466 23:45:37.383724 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8467 23:45:37.384196 ==
8468 23:45:37.387186 RX Vref Scan: 0
8469 23:45:37.387749
8470 23:45:37.388118 RX Vref 0 -> 0, step: 1
8471 23:45:37.388461
8472 23:45:37.390068 RX Delay 0 -> 252, step: 8
8473 23:45:37.393851 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8474 23:45:37.400138 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8475 23:45:37.403210 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8476 23:45:37.406746 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8477 23:45:37.410231 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8478 23:45:37.413353 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8479 23:45:37.420127 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8480 23:45:37.423205 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8481 23:45:37.426338 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8482 23:45:37.429924 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8483 23:45:37.433422 iDelay=208, Bit 10, Center 127 (72 ~ 183) 112
8484 23:45:37.439436 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8485 23:45:37.443020 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8486 23:45:37.446237 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8487 23:45:37.449346 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8488 23:45:37.455561 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8489 23:45:37.456032 ==
8490 23:45:37.459387 Dram Type= 6, Freq= 0, CH_1, rank 0
8491 23:45:37.462263 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8492 23:45:37.462747 ==
8493 23:45:37.463117 DQS Delay:
8494 23:45:37.465675 DQS0 = 0, DQS1 = 0
8495 23:45:37.466133 DQM Delay:
8496 23:45:37.468983 DQM0 = 136, DQM1 = 129
8497 23:45:37.469444 DQ Delay:
8498 23:45:37.471980 DQ0 =139, DQ1 =131, DQ2 =127, DQ3 =131
8499 23:45:37.475817 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8500 23:45:37.478868 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =123
8501 23:45:37.485578 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =135
8502 23:45:37.486040
8503 23:45:37.486444
8504 23:45:37.486786 ==
8505 23:45:37.488358 Dram Type= 6, Freq= 0, CH_1, rank 0
8506 23:45:37.492130 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8507 23:45:37.492812 ==
8508 23:45:37.493192
8509 23:45:37.493535
8510 23:45:37.495257 TX Vref Scan disable
8511 23:45:37.495719 == TX Byte 0 ==
8512 23:45:37.502106 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8513 23:45:37.505073 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8514 23:45:37.505653 == TX Byte 1 ==
8515 23:45:37.511832 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8516 23:45:37.515121 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8517 23:45:37.515604 ==
8518 23:45:37.518355 Dram Type= 6, Freq= 0, CH_1, rank 0
8519 23:45:37.521825 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8520 23:45:37.522437 ==
8521 23:45:37.537134
8522 23:45:37.539631 TX Vref early break, caculate TX vref
8523 23:45:37.542883 TX Vref=16, minBit 0, minWin=22, winSum=377
8524 23:45:37.546435 TX Vref=18, minBit 0, minWin=22, winSum=387
8525 23:45:37.549609 TX Vref=20, minBit 5, minWin=22, winSum=397
8526 23:45:37.552649 TX Vref=22, minBit 5, minWin=23, winSum=402
8527 23:45:37.556169 TX Vref=24, minBit 5, minWin=24, winSum=412
8528 23:45:37.562813 TX Vref=26, minBit 0, minWin=25, winSum=421
8529 23:45:37.566470 TX Vref=28, minBit 0, minWin=25, winSum=419
8530 23:45:37.569493 TX Vref=30, minBit 1, minWin=24, winSum=415
8531 23:45:37.572422 TX Vref=32, minBit 0, minWin=24, winSum=405
8532 23:45:37.575956 TX Vref=34, minBit 0, minWin=24, winSum=400
8533 23:45:37.582782 TX Vref=36, minBit 0, minWin=23, winSum=386
8534 23:45:37.585773 [TxChooseVref] Worse bit 0, Min win 25, Win sum 421, Final Vref 26
8535 23:45:37.586284
8536 23:45:37.589132 Final TX Range 0 Vref 26
8537 23:45:37.589687
8538 23:45:37.590052 ==
8539 23:45:37.592383 Dram Type= 6, Freq= 0, CH_1, rank 0
8540 23:45:37.595354 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8541 23:45:37.598387 ==
8542 23:45:37.598847
8543 23:45:37.599206
8544 23:45:37.599538 TX Vref Scan disable
8545 23:45:37.605752 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8546 23:45:37.606255 == TX Byte 0 ==
8547 23:45:37.609202 u2DelayCellOfst[0]=18 cells (5 PI)
8548 23:45:37.612646 u2DelayCellOfst[1]=14 cells (4 PI)
8549 23:45:37.615568 u2DelayCellOfst[2]=0 cells (0 PI)
8550 23:45:37.618561 u2DelayCellOfst[3]=3 cells (1 PI)
8551 23:45:37.622531 u2DelayCellOfst[4]=7 cells (2 PI)
8552 23:45:37.625356 u2DelayCellOfst[5]=18 cells (5 PI)
8553 23:45:37.628623 u2DelayCellOfst[6]=18 cells (5 PI)
8554 23:45:37.631949 u2DelayCellOfst[7]=3 cells (1 PI)
8555 23:45:37.635594 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8556 23:45:37.638509 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8557 23:45:37.642112 == TX Byte 1 ==
8558 23:45:37.645348 u2DelayCellOfst[8]=0 cells (0 PI)
8559 23:45:37.648656 u2DelayCellOfst[9]=3 cells (1 PI)
8560 23:45:37.651913 u2DelayCellOfst[10]=11 cells (3 PI)
8561 23:45:37.654745 u2DelayCellOfst[11]=3 cells (1 PI)
8562 23:45:37.658520 u2DelayCellOfst[12]=14 cells (4 PI)
8563 23:45:37.661339 u2DelayCellOfst[13]=18 cells (5 PI)
8564 23:45:37.664652 u2DelayCellOfst[14]=18 cells (5 PI)
8565 23:45:37.665203 u2DelayCellOfst[15]=18 cells (5 PI)
8566 23:45:37.671552 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8567 23:45:37.674619 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8568 23:45:37.678050 DramC Write-DBI on
8569 23:45:37.678676 ==
8570 23:45:37.681518 Dram Type= 6, Freq= 0, CH_1, rank 0
8571 23:45:37.684459 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8572 23:45:37.685027 ==
8573 23:45:37.685395
8574 23:45:37.685732
8575 23:45:37.688157 TX Vref Scan disable
8576 23:45:37.690682 == TX Byte 0 ==
8577 23:45:37.694280 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8578 23:45:37.694765 == TX Byte 1 ==
8579 23:45:37.700639 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8580 23:45:37.701242 DramC Write-DBI off
8581 23:45:37.701618
8582 23:45:37.701955 [DATLAT]
8583 23:45:37.703738 Freq=1600, CH1 RK0
8584 23:45:37.704196
8585 23:45:37.707100 DATLAT Default: 0xf
8586 23:45:37.707558 0, 0xFFFF, sum = 0
8587 23:45:37.710372 1, 0xFFFF, sum = 0
8588 23:45:37.710838 2, 0xFFFF, sum = 0
8589 23:45:37.714037 3, 0xFFFF, sum = 0
8590 23:45:37.714549 4, 0xFFFF, sum = 0
8591 23:45:37.717188 5, 0xFFFF, sum = 0
8592 23:45:37.717775 6, 0xFFFF, sum = 0
8593 23:45:37.720651 7, 0xFFFF, sum = 0
8594 23:45:37.721146 8, 0xFFFF, sum = 0
8595 23:45:37.723723 9, 0xFFFF, sum = 0
8596 23:45:37.724189 10, 0xFFFF, sum = 0
8597 23:45:37.727000 11, 0xFFFF, sum = 0
8598 23:45:37.727468 12, 0xFFFF, sum = 0
8599 23:45:37.729913 13, 0xFFFF, sum = 0
8600 23:45:37.733871 14, 0x0, sum = 1
8601 23:45:37.734513 15, 0x0, sum = 2
8602 23:45:37.734893 16, 0x0, sum = 3
8603 23:45:37.736594 17, 0x0, sum = 4
8604 23:45:37.737064 best_step = 15
8605 23:45:37.737424
8606 23:45:37.737760 ==
8607 23:45:37.740227 Dram Type= 6, Freq= 0, CH_1, rank 0
8608 23:45:37.746834 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8609 23:45:37.747300 ==
8610 23:45:37.747661 RX Vref Scan: 1
8611 23:45:37.748003
8612 23:45:37.750062 Set Vref Range= 24 -> 127
8613 23:45:37.750564
8614 23:45:37.753119 RX Vref 24 -> 127, step: 1
8615 23:45:37.753578
8616 23:45:37.756599 RX Delay 11 -> 252, step: 4
8617 23:45:37.757032
8618 23:45:37.759845 Set Vref, RX VrefLevel [Byte0]: 24
8619 23:45:37.763187 [Byte1]: 24
8620 23:45:37.763611
8621 23:45:37.766370 Set Vref, RX VrefLevel [Byte0]: 25
8622 23:45:37.769697 [Byte1]: 25
8623 23:45:37.770111
8624 23:45:37.773135 Set Vref, RX VrefLevel [Byte0]: 26
8625 23:45:37.776413 [Byte1]: 26
8626 23:45:37.779662
8627 23:45:37.780079 Set Vref, RX VrefLevel [Byte0]: 27
8628 23:45:37.782896 [Byte1]: 27
8629 23:45:37.787224
8630 23:45:37.787735 Set Vref, RX VrefLevel [Byte0]: 28
8631 23:45:37.790990 [Byte1]: 28
8632 23:45:37.795033
8633 23:45:37.795551 Set Vref, RX VrefLevel [Byte0]: 29
8634 23:45:37.798326 [Byte1]: 29
8635 23:45:37.802663
8636 23:45:37.803075 Set Vref, RX VrefLevel [Byte0]: 30
8637 23:45:37.806073 [Byte1]: 30
8638 23:45:37.810436
8639 23:45:37.810897 Set Vref, RX VrefLevel [Byte0]: 31
8640 23:45:37.813489 [Byte1]: 31
8641 23:45:37.817645
8642 23:45:37.818153 Set Vref, RX VrefLevel [Byte0]: 32
8643 23:45:37.821227 [Byte1]: 32
8644 23:45:37.825655
8645 23:45:37.826219 Set Vref, RX VrefLevel [Byte0]: 33
8646 23:45:37.828673 [Byte1]: 33
8647 23:45:37.832946
8648 23:45:37.833365 Set Vref, RX VrefLevel [Byte0]: 34
8649 23:45:37.836730 [Byte1]: 34
8650 23:45:37.840447
8651 23:45:37.840907 Set Vref, RX VrefLevel [Byte0]: 35
8652 23:45:37.843912 [Byte1]: 35
8653 23:45:37.848290
8654 23:45:37.848753 Set Vref, RX VrefLevel [Byte0]: 36
8655 23:45:37.851954 [Byte1]: 36
8656 23:45:37.855999
8657 23:45:37.856466 Set Vref, RX VrefLevel [Byte0]: 37
8658 23:45:37.859035 [Byte1]: 37
8659 23:45:37.863422
8660 23:45:37.863849 Set Vref, RX VrefLevel [Byte0]: 38
8661 23:45:37.867282 [Byte1]: 38
8662 23:45:37.872076
8663 23:45:37.872627 Set Vref, RX VrefLevel [Byte0]: 39
8664 23:45:37.874764 [Byte1]: 39
8665 23:45:37.879279
8666 23:45:37.879921 Set Vref, RX VrefLevel [Byte0]: 40
8667 23:45:37.882214 [Byte1]: 40
8668 23:45:37.886106
8669 23:45:37.886626 Set Vref, RX VrefLevel [Byte0]: 41
8670 23:45:37.889466 [Byte1]: 41
8671 23:45:37.893859
8672 23:45:37.894345 Set Vref, RX VrefLevel [Byte0]: 42
8673 23:45:37.897522 [Byte1]: 42
8674 23:45:37.901375
8675 23:45:37.901851 Set Vref, RX VrefLevel [Byte0]: 43
8676 23:45:37.905080 [Byte1]: 43
8677 23:45:37.909653
8678 23:45:37.910082 Set Vref, RX VrefLevel [Byte0]: 44
8679 23:45:37.913182 [Byte1]: 44
8680 23:45:37.916587
8681 23:45:37.917017 Set Vref, RX VrefLevel [Byte0]: 45
8682 23:45:37.920402 [Byte1]: 45
8683 23:45:37.924029
8684 23:45:37.924457 Set Vref, RX VrefLevel [Byte0]: 46
8685 23:45:37.928010 [Byte1]: 46
8686 23:45:37.931862
8687 23:45:37.932294 Set Vref, RX VrefLevel [Byte0]: 47
8688 23:45:37.935138 [Byte1]: 47
8689 23:45:37.939309
8690 23:45:37.939736 Set Vref, RX VrefLevel [Byte0]: 48
8691 23:45:37.942709 [Byte1]: 48
8692 23:45:37.947080
8693 23:45:37.947509 Set Vref, RX VrefLevel [Byte0]: 49
8694 23:45:37.950220 [Byte1]: 49
8695 23:45:37.954896
8696 23:45:37.955325 Set Vref, RX VrefLevel [Byte0]: 50
8697 23:45:37.957945 [Byte1]: 50
8698 23:45:37.962696
8699 23:45:37.963130 Set Vref, RX VrefLevel [Byte0]: 51
8700 23:45:37.965530 [Byte1]: 51
8701 23:45:37.970207
8702 23:45:37.970634 Set Vref, RX VrefLevel [Byte0]: 52
8703 23:45:37.973397 [Byte1]: 52
8704 23:45:37.977472
8705 23:45:37.977901 Set Vref, RX VrefLevel [Byte0]: 53
8706 23:45:37.984208 [Byte1]: 53
8707 23:45:37.984637
8708 23:45:37.987565 Set Vref, RX VrefLevel [Byte0]: 54
8709 23:45:37.990688 [Byte1]: 54
8710 23:45:37.991117
8711 23:45:37.993887 Set Vref, RX VrefLevel [Byte0]: 55
8712 23:45:37.996957 [Byte1]: 55
8713 23:45:38.000907
8714 23:45:38.001322 Set Vref, RX VrefLevel [Byte0]: 56
8715 23:45:38.004045 [Byte1]: 56
8716 23:45:38.008330
8717 23:45:38.008740 Set Vref, RX VrefLevel [Byte0]: 57
8718 23:45:38.011444 [Byte1]: 57
8719 23:45:38.015581
8720 23:45:38.015994 Set Vref, RX VrefLevel [Byte0]: 58
8721 23:45:38.018722 [Byte1]: 58
8722 23:45:38.023434
8723 23:45:38.023845 Set Vref, RX VrefLevel [Byte0]: 59
8724 23:45:38.026502 [Byte1]: 59
8725 23:45:38.030925
8726 23:45:38.031337 Set Vref, RX VrefLevel [Byte0]: 60
8727 23:45:38.034326 [Byte1]: 60
8728 23:45:38.038652
8729 23:45:38.039173 Set Vref, RX VrefLevel [Byte0]: 61
8730 23:45:38.041815 [Byte1]: 61
8731 23:45:38.046023
8732 23:45:38.046563 Set Vref, RX VrefLevel [Byte0]: 62
8733 23:45:38.049552 [Byte1]: 62
8734 23:45:38.053713
8735 23:45:38.054130 Set Vref, RX VrefLevel [Byte0]: 63
8736 23:45:38.056764 [Byte1]: 63
8737 23:45:38.061449
8738 23:45:38.061863 Set Vref, RX VrefLevel [Byte0]: 64
8739 23:45:38.064370 [Byte1]: 64
8740 23:45:38.069593
8741 23:45:38.070104 Set Vref, RX VrefLevel [Byte0]: 65
8742 23:45:38.072100 [Byte1]: 65
8743 23:45:38.076687
8744 23:45:38.077115 Set Vref, RX VrefLevel [Byte0]: 66
8745 23:45:38.079688 [Byte1]: 66
8746 23:45:38.084134
8747 23:45:38.084550 Set Vref, RX VrefLevel [Byte0]: 67
8748 23:45:38.087485 [Byte1]: 67
8749 23:45:38.092268
8750 23:45:38.092799 Set Vref, RX VrefLevel [Byte0]: 68
8751 23:45:38.095307 [Byte1]: 68
8752 23:45:38.099420
8753 23:45:38.099840 Set Vref, RX VrefLevel [Byte0]: 69
8754 23:45:38.102575 [Byte1]: 69
8755 23:45:38.107019
8756 23:45:38.107435 Set Vref, RX VrefLevel [Byte0]: 70
8757 23:45:38.110306 [Byte1]: 70
8758 23:45:38.114973
8759 23:45:38.115522 Set Vref, RX VrefLevel [Byte0]: 71
8760 23:45:38.118048 [Byte1]: 71
8761 23:45:38.122461
8762 23:45:38.122878 Set Vref, RX VrefLevel [Byte0]: 72
8763 23:45:38.125764 [Byte1]: 72
8764 23:45:38.129799
8765 23:45:38.130260 Set Vref, RX VrefLevel [Byte0]: 73
8766 23:45:38.133125 [Byte1]: 73
8767 23:45:38.137341
8768 23:45:38.137760 Set Vref, RX VrefLevel [Byte0]: 74
8769 23:45:38.140609 [Byte1]: 74
8770 23:45:38.145847
8771 23:45:38.146399 Set Vref, RX VrefLevel [Byte0]: 75
8772 23:45:38.148305 [Byte1]: 75
8773 23:45:38.152844
8774 23:45:38.153432 Final RX Vref Byte 0 = 54 to rank0
8775 23:45:38.155859 Final RX Vref Byte 1 = 58 to rank0
8776 23:45:38.159054 Final RX Vref Byte 0 = 54 to rank1
8777 23:45:38.163067 Final RX Vref Byte 1 = 58 to rank1==
8778 23:45:38.165614 Dram Type= 6, Freq= 0, CH_1, rank 0
8779 23:45:38.172413 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8780 23:45:38.172835 ==
8781 23:45:38.173167 DQS Delay:
8782 23:45:38.175661 DQS0 = 0, DQS1 = 0
8783 23:45:38.176080 DQM Delay:
8784 23:45:38.179048 DQM0 = 133, DQM1 = 127
8785 23:45:38.179498 DQ Delay:
8786 23:45:38.182099 DQ0 =142, DQ1 =126, DQ2 =124, DQ3 =130
8787 23:45:38.185366 DQ4 =130, DQ5 =146, DQ6 =142, DQ7 =128
8788 23:45:38.189580 DQ8 =114, DQ9 =116, DQ10 =130, DQ11 =116
8789 23:45:38.191959 DQ12 =134, DQ13 =134, DQ14 =136, DQ15 =136
8790 23:45:38.192381
8791 23:45:38.192710
8792 23:45:38.193017
8793 23:45:38.195320 [DramC_TX_OE_Calibration] TA2
8794 23:45:38.198544 Original DQ_B0 (3 6) =30, OEN = 27
8795 23:45:38.201746 Original DQ_B1 (3 6) =30, OEN = 27
8796 23:45:38.205199 24, 0x0, End_B0=24 End_B1=24
8797 23:45:38.208310 25, 0x0, End_B0=25 End_B1=25
8798 23:45:38.208755 26, 0x0, End_B0=26 End_B1=26
8799 23:45:38.212160 27, 0x0, End_B0=27 End_B1=27
8800 23:45:38.215086 28, 0x0, End_B0=28 End_B1=28
8801 23:45:38.218094 29, 0x0, End_B0=29 End_B1=29
8802 23:45:38.222061 30, 0x0, End_B0=30 End_B1=30
8803 23:45:38.222561 31, 0x4545, End_B0=30 End_B1=30
8804 23:45:38.225061 Byte0 end_step=30 best_step=27
8805 23:45:38.227961 Byte1 end_step=30 best_step=27
8806 23:45:38.231292 Byte0 TX OE(2T, 0.5T) = (3, 3)
8807 23:45:38.234648 Byte1 TX OE(2T, 0.5T) = (3, 3)
8808 23:45:38.235076
8809 23:45:38.235510
8810 23:45:38.241162 [DQSOSCAuto] RK0, (LSB)MR18= 0x180d, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
8811 23:45:38.244313 CH1 RK0: MR19=303, MR18=180D
8812 23:45:38.251260 CH1_RK0: MR19=0x303, MR18=0x180D, DQSOSC=397, MR23=63, INC=23, DEC=15
8813 23:45:38.251691
8814 23:45:38.254476 ----->DramcWriteLeveling(PI) begin...
8815 23:45:38.254910 ==
8816 23:45:38.257682 Dram Type= 6, Freq= 0, CH_1, rank 1
8817 23:45:38.261600 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8818 23:45:38.264731 ==
8819 23:45:38.265167 Write leveling (Byte 0): 22 => 22
8820 23:45:38.267641 Write leveling (Byte 1): 27 => 27
8821 23:45:38.271115 DramcWriteLeveling(PI) end<-----
8822 23:45:38.271630
8823 23:45:38.272072 ==
8824 23:45:38.274259 Dram Type= 6, Freq= 0, CH_1, rank 1
8825 23:45:38.281042 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8826 23:45:38.281550 ==
8827 23:45:38.284253 [Gating] SW mode calibration
8828 23:45:38.291637 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8829 23:45:38.294242 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8830 23:45:38.301052 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8831 23:45:38.303920 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8832 23:45:38.307430 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8833 23:45:38.313683 1 4 12 | B1->B0 | 3333 2424 | 1 0 | (1 1) (0 0)
8834 23:45:38.317163 1 4 16 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
8835 23:45:38.320530 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8836 23:45:38.327903 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8837 23:45:38.330230 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8838 23:45:38.334266 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8839 23:45:38.340393 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8840 23:45:38.343848 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8841 23:45:38.346912 1 5 12 | B1->B0 | 2a2a 3434 | 0 0 | (0 0) (0 1)
8842 23:45:38.353782 1 5 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8843 23:45:38.356853 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8844 23:45:38.360261 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8845 23:45:38.366559 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8846 23:45:38.370307 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8847 23:45:38.373383 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8848 23:45:38.379882 1 6 8 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
8849 23:45:38.383639 1 6 12 | B1->B0 | 4646 2323 | 0 0 | (0 0) (0 0)
8850 23:45:38.386577 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8851 23:45:38.392992 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8852 23:45:38.396572 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8853 23:45:38.399760 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8854 23:45:38.405903 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8855 23:45:38.409430 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8856 23:45:38.413148 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8857 23:45:38.419143 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8858 23:45:38.422240 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8859 23:45:38.425868 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8860 23:45:38.432785 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8861 23:45:38.435725 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8862 23:45:38.439087 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8863 23:45:38.445844 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8864 23:45:38.449157 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8865 23:45:38.452471 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8866 23:45:38.459209 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8867 23:45:38.461775 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8868 23:45:38.465709 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8869 23:45:38.472133 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8870 23:45:38.475068 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8871 23:45:38.478730 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8872 23:45:38.484959 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8873 23:45:38.488435 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8874 23:45:38.491964 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8875 23:45:38.494866 Total UI for P1: 0, mck2ui 16
8876 23:45:38.498215 best dqsien dly found for B0: ( 1, 9, 10)
8877 23:45:38.501619 Total UI for P1: 0, mck2ui 16
8878 23:45:38.504599 best dqsien dly found for B1: ( 1, 9, 10)
8879 23:45:38.508105 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8880 23:45:38.512069 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8881 23:45:38.512610
8882 23:45:38.518241 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8883 23:45:38.521353 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8884 23:45:38.524807 [Gating] SW calibration Done
8885 23:45:38.525375 ==
8886 23:45:38.528783 Dram Type= 6, Freq= 0, CH_1, rank 1
8887 23:45:38.531470 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8888 23:45:38.531905 ==
8889 23:45:38.532345 RX Vref Scan: 0
8890 23:45:38.532754
8891 23:45:38.534635 RX Vref 0 -> 0, step: 1
8892 23:45:38.535079
8893 23:45:38.537889 RX Delay 0 -> 252, step: 8
8894 23:45:38.541092 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8895 23:45:38.544335 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8896 23:45:38.550612 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8897 23:45:38.554156 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8898 23:45:38.557444 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8899 23:45:38.561067 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8900 23:45:38.564117 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8901 23:45:38.571098 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8902 23:45:38.573910 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8903 23:45:38.577398 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8904 23:45:38.580328 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8905 23:45:38.584203 iDelay=208, Bit 11, Center 119 (56 ~ 183) 128
8906 23:45:38.590531 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8907 23:45:38.593357 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8908 23:45:38.597633 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8909 23:45:38.600119 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8910 23:45:38.600554 ==
8911 23:45:38.603605 Dram Type= 6, Freq= 0, CH_1, rank 1
8912 23:45:38.610035 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8913 23:45:38.610685 ==
8914 23:45:38.611169 DQS Delay:
8915 23:45:38.613487 DQS0 = 0, DQS1 = 0
8916 23:45:38.613963 DQM Delay:
8917 23:45:38.616943 DQM0 = 137, DQM1 = 129
8918 23:45:38.617535 DQ Delay:
8919 23:45:38.620136 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8920 23:45:38.623084 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8921 23:45:38.626887 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8922 23:45:38.629998 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8923 23:45:38.630611
8924 23:45:38.631100
8925 23:45:38.631546 ==
8926 23:45:38.633129 Dram Type= 6, Freq= 0, CH_1, rank 1
8927 23:45:38.639791 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8928 23:45:38.640372 ==
8929 23:45:38.640865
8930 23:45:38.641312
8931 23:45:38.641746 TX Vref Scan disable
8932 23:45:38.643774 == TX Byte 0 ==
8933 23:45:38.647092 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8934 23:45:38.653531 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8935 23:45:38.654109 == TX Byte 1 ==
8936 23:45:38.656603 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8937 23:45:38.663427 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8938 23:45:38.664017 ==
8939 23:45:38.666660 Dram Type= 6, Freq= 0, CH_1, rank 1
8940 23:45:38.670434 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8941 23:45:38.671013 ==
8942 23:45:38.684232
8943 23:45:38.686981 TX Vref early break, caculate TX vref
8944 23:45:38.691192 TX Vref=16, minBit 5, minWin=21, winSum=379
8945 23:45:38.693812 TX Vref=18, minBit 0, minWin=23, winSum=392
8946 23:45:38.697124 TX Vref=20, minBit 5, minWin=23, winSum=397
8947 23:45:38.700432 TX Vref=22, minBit 6, minWin=23, winSum=407
8948 23:45:38.703477 TX Vref=24, minBit 5, minWin=23, winSum=410
8949 23:45:38.710120 TX Vref=26, minBit 0, minWin=25, winSum=420
8950 23:45:38.714272 TX Vref=28, minBit 0, minWin=24, winSum=417
8951 23:45:38.716901 TX Vref=30, minBit 0, minWin=23, winSum=412
8952 23:45:38.720127 TX Vref=32, minBit 0, minWin=23, winSum=405
8953 23:45:38.723558 TX Vref=34, minBit 0, minWin=22, winSum=399
8954 23:45:38.726666 TX Vref=36, minBit 0, minWin=21, winSum=385
8955 23:45:38.733480 [TxChooseVref] Worse bit 0, Min win 25, Win sum 420, Final Vref 26
8956 23:45:38.733955
8957 23:45:38.736396 Final TX Range 0 Vref 26
8958 23:45:38.736871
8959 23:45:38.737347 ==
8960 23:45:38.740084 Dram Type= 6, Freq= 0, CH_1, rank 1
8961 23:45:38.743217 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8962 23:45:38.743647 ==
8963 23:45:38.746281
8964 23:45:38.746712
8965 23:45:38.747139 TX Vref Scan disable
8966 23:45:38.753351 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8967 23:45:38.753875 == TX Byte 0 ==
8968 23:45:38.756119 u2DelayCellOfst[0]=18 cells (5 PI)
8969 23:45:38.759947 u2DelayCellOfst[1]=11 cells (3 PI)
8970 23:45:38.762836 u2DelayCellOfst[2]=0 cells (0 PI)
8971 23:45:38.766131 u2DelayCellOfst[3]=7 cells (2 PI)
8972 23:45:38.769841 u2DelayCellOfst[4]=7 cells (2 PI)
8973 23:45:38.772779 u2DelayCellOfst[5]=18 cells (5 PI)
8974 23:45:38.776124 u2DelayCellOfst[6]=18 cells (5 PI)
8975 23:45:38.779342 u2DelayCellOfst[7]=3 cells (1 PI)
8976 23:45:38.782837 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8977 23:45:38.785772 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8978 23:45:38.789113 == TX Byte 1 ==
8979 23:45:38.792623 u2DelayCellOfst[8]=0 cells (0 PI)
8980 23:45:38.796019 u2DelayCellOfst[9]=7 cells (2 PI)
8981 23:45:38.799050 u2DelayCellOfst[10]=14 cells (4 PI)
8982 23:45:38.802279 u2DelayCellOfst[11]=7 cells (2 PI)
8983 23:45:38.805246 u2DelayCellOfst[12]=14 cells (4 PI)
8984 23:45:38.808555 u2DelayCellOfst[13]=18 cells (5 PI)
8985 23:45:38.812105 u2DelayCellOfst[14]=18 cells (5 PI)
8986 23:45:38.815090 u2DelayCellOfst[15]=18 cells (5 PI)
8987 23:45:38.818757 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8988 23:45:38.822544 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8989 23:45:38.825559 DramC Write-DBI on
8990 23:45:38.826069 ==
8991 23:45:38.828464 Dram Type= 6, Freq= 0, CH_1, rank 1
8992 23:45:38.832069 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8993 23:45:38.832591 ==
8994 23:45:38.832958
8995 23:45:38.833266
8996 23:45:38.835147 TX Vref Scan disable
8997 23:45:38.835561 == TX Byte 0 ==
8998 23:45:38.841958 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8999 23:45:38.842415 == TX Byte 1 ==
9000 23:45:38.848678 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
9001 23:45:38.849180 DramC Write-DBI off
9002 23:45:38.849508
9003 23:45:38.849809 [DATLAT]
9004 23:45:38.851599 Freq=1600, CH1 RK1
9005 23:45:38.852011
9006 23:45:38.852336 DATLAT Default: 0xf
9007 23:45:38.854899 0, 0xFFFF, sum = 0
9008 23:45:38.858359 1, 0xFFFF, sum = 0
9009 23:45:38.858782 2, 0xFFFF, sum = 0
9010 23:45:38.861848 3, 0xFFFF, sum = 0
9011 23:45:38.862426 4, 0xFFFF, sum = 0
9012 23:45:38.865096 5, 0xFFFF, sum = 0
9013 23:45:38.865532 6, 0xFFFF, sum = 0
9014 23:45:38.868368 7, 0xFFFF, sum = 0
9015 23:45:38.868801 8, 0xFFFF, sum = 0
9016 23:45:38.871683 9, 0xFFFF, sum = 0
9017 23:45:38.872236 10, 0xFFFF, sum = 0
9018 23:45:38.875000 11, 0xFFFF, sum = 0
9019 23:45:38.875452 12, 0xFFFF, sum = 0
9020 23:45:38.879013 13, 0xFFFF, sum = 0
9021 23:45:38.879558 14, 0x0, sum = 1
9022 23:45:38.881568 15, 0x0, sum = 2
9023 23:45:38.882105 16, 0x0, sum = 3
9024 23:45:38.885088 17, 0x0, sum = 4
9025 23:45:38.885634 best_step = 15
9026 23:45:38.886081
9027 23:45:38.886533 ==
9028 23:45:38.887840 Dram Type= 6, Freq= 0, CH_1, rank 1
9029 23:45:38.895008 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9030 23:45:38.895538 ==
9031 23:45:38.895987 RX Vref Scan: 0
9032 23:45:38.896402
9033 23:45:38.897756 RX Vref 0 -> 0, step: 1
9034 23:45:38.898214
9035 23:45:38.901002 RX Delay 11 -> 252, step: 4
9036 23:45:38.904959 iDelay=203, Bit 0, Center 138 (87 ~ 190) 104
9037 23:45:38.908036 iDelay=203, Bit 1, Center 128 (75 ~ 182) 108
9038 23:45:38.911281 iDelay=203, Bit 2, Center 122 (67 ~ 178) 112
9039 23:45:38.918003 iDelay=203, Bit 3, Center 130 (79 ~ 182) 104
9040 23:45:38.921675 iDelay=203, Bit 4, Center 132 (75 ~ 190) 116
9041 23:45:38.924662 iDelay=203, Bit 5, Center 144 (91 ~ 198) 108
9042 23:45:38.927944 iDelay=203, Bit 6, Center 146 (91 ~ 202) 112
9043 23:45:38.930860 iDelay=203, Bit 7, Center 130 (79 ~ 182) 104
9044 23:45:38.937355 iDelay=203, Bit 8, Center 112 (55 ~ 170) 116
9045 23:45:38.940939 iDelay=203, Bit 9, Center 116 (63 ~ 170) 108
9046 23:45:38.944938 iDelay=203, Bit 10, Center 126 (71 ~ 182) 112
9047 23:45:38.947137 iDelay=203, Bit 11, Center 118 (67 ~ 170) 104
9048 23:45:38.954069 iDelay=203, Bit 12, Center 134 (79 ~ 190) 112
9049 23:45:38.957249 iDelay=203, Bit 13, Center 134 (79 ~ 190) 112
9050 23:45:38.960499 iDelay=203, Bit 14, Center 134 (79 ~ 190) 112
9051 23:45:38.964062 iDelay=203, Bit 15, Center 138 (83 ~ 194) 112
9052 23:45:38.964492 ==
9053 23:45:38.967408 Dram Type= 6, Freq= 0, CH_1, rank 1
9054 23:45:38.973955 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9055 23:45:38.974568 ==
9056 23:45:38.975014 DQS Delay:
9057 23:45:38.977334 DQS0 = 0, DQS1 = 0
9058 23:45:38.977758 DQM Delay:
9059 23:45:38.978218 DQM0 = 133, DQM1 = 126
9060 23:45:38.980500 DQ Delay:
9061 23:45:38.984066 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =130
9062 23:45:38.987302 DQ4 =132, DQ5 =144, DQ6 =146, DQ7 =130
9063 23:45:38.990727 DQ8 =112, DQ9 =116, DQ10 =126, DQ11 =118
9064 23:45:38.994451 DQ12 =134, DQ13 =134, DQ14 =134, DQ15 =138
9065 23:45:38.994972
9066 23:45:38.995298
9067 23:45:38.995596
9068 23:45:38.996780 [DramC_TX_OE_Calibration] TA2
9069 23:45:39.000513 Original DQ_B0 (3 6) =30, OEN = 27
9070 23:45:39.004111 Original DQ_B1 (3 6) =30, OEN = 27
9071 23:45:39.006985 24, 0x0, End_B0=24 End_B1=24
9072 23:45:39.007408 25, 0x0, End_B0=25 End_B1=25
9073 23:45:39.010573 26, 0x0, End_B0=26 End_B1=26
9074 23:45:39.013476 27, 0x0, End_B0=27 End_B1=27
9075 23:45:39.016775 28, 0x0, End_B0=28 End_B1=28
9076 23:45:39.019940 29, 0x0, End_B0=29 End_B1=29
9077 23:45:39.020363 30, 0x0, End_B0=30 End_B1=30
9078 23:45:39.023265 31, 0x4141, End_B0=30 End_B1=30
9079 23:45:39.026839 Byte0 end_step=30 best_step=27
9080 23:45:39.029670 Byte1 end_step=30 best_step=27
9081 23:45:39.033101 Byte0 TX OE(2T, 0.5T) = (3, 3)
9082 23:45:39.036697 Byte1 TX OE(2T, 0.5T) = (3, 3)
9083 23:45:39.037219
9084 23:45:39.037548
9085 23:45:39.043140 [DQSOSCAuto] RK1, (LSB)MR18= 0xd08, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
9086 23:45:39.046485 CH1 RK1: MR19=303, MR18=D08
9087 23:45:39.053050 CH1_RK1: MR19=0x303, MR18=0xD08, DQSOSC=403, MR23=63, INC=22, DEC=15
9088 23:45:39.056086 [RxdqsGatingPostProcess] freq 1600
9089 23:45:39.059369 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9090 23:45:39.062794 best DQS0 dly(2T, 0.5T) = (1, 1)
9091 23:45:39.065984 best DQS1 dly(2T, 0.5T) = (1, 1)
9092 23:45:39.069439 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9093 23:45:39.072386 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9094 23:45:39.076992 best DQS0 dly(2T, 0.5T) = (1, 1)
9095 23:45:39.079371 best DQS1 dly(2T, 0.5T) = (1, 1)
9096 23:45:39.082837 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9097 23:45:39.085979 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9098 23:45:39.089048 Pre-setting of DQS Precalculation
9099 23:45:39.092269 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9100 23:45:39.102640 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9101 23:45:39.108900 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9102 23:45:39.109428
9103 23:45:39.109869
9104 23:45:39.112016 [Calibration Summary] 3200 Mbps
9105 23:45:39.112452 CH 0, Rank 0
9106 23:45:39.115620 SW Impedance : PASS
9107 23:45:39.116049 DUTY Scan : NO K
9108 23:45:39.118660 ZQ Calibration : PASS
9109 23:45:39.122265 Jitter Meter : NO K
9110 23:45:39.122699 CBT Training : PASS
9111 23:45:39.125407 Write leveling : PASS
9112 23:45:39.128589 RX DQS gating : PASS
9113 23:45:39.129020 RX DQ/DQS(RDDQC) : PASS
9114 23:45:39.132544 TX DQ/DQS : PASS
9115 23:45:39.135501 RX DATLAT : PASS
9116 23:45:39.135932 RX DQ/DQS(Engine): PASS
9117 23:45:39.138862 TX OE : PASS
9118 23:45:39.139296 All Pass.
9119 23:45:39.139733
9120 23:45:39.142021 CH 0, Rank 1
9121 23:45:39.142483 SW Impedance : PASS
9122 23:45:39.145551 DUTY Scan : NO K
9123 23:45:39.148794 ZQ Calibration : PASS
9124 23:45:39.149225 Jitter Meter : NO K
9125 23:45:39.151595 CBT Training : PASS
9126 23:45:39.155403 Write leveling : PASS
9127 23:45:39.155938 RX DQS gating : PASS
9128 23:45:39.158240 RX DQ/DQS(RDDQC) : PASS
9129 23:45:39.158703 TX DQ/DQS : PASS
9130 23:45:39.162053 RX DATLAT : PASS
9131 23:45:39.164939 RX DQ/DQS(Engine): PASS
9132 23:45:39.165458 TX OE : PASS
9133 23:45:39.168905 All Pass.
9134 23:45:39.169469
9135 23:45:39.169919 CH 1, Rank 0
9136 23:45:39.171431 SW Impedance : PASS
9137 23:45:39.171861 DUTY Scan : NO K
9138 23:45:39.175225 ZQ Calibration : PASS
9139 23:45:39.178114 Jitter Meter : NO K
9140 23:45:39.178575 CBT Training : PASS
9141 23:45:39.181637 Write leveling : PASS
9142 23:45:39.184575 RX DQS gating : PASS
9143 23:45:39.185023 RX DQ/DQS(RDDQC) : PASS
9144 23:45:39.187974 TX DQ/DQS : PASS
9145 23:45:39.191490 RX DATLAT : PASS
9146 23:45:39.192025 RX DQ/DQS(Engine): PASS
9147 23:45:39.194717 TX OE : PASS
9148 23:45:39.195260 All Pass.
9149 23:45:39.195603
9150 23:45:39.197967 CH 1, Rank 1
9151 23:45:39.198419 SW Impedance : PASS
9152 23:45:39.201294 DUTY Scan : NO K
9153 23:45:39.204305 ZQ Calibration : PASS
9154 23:45:39.204726 Jitter Meter : NO K
9155 23:45:39.207826 CBT Training : PASS
9156 23:45:39.211115 Write leveling : PASS
9157 23:45:39.211566 RX DQS gating : PASS
9158 23:45:39.214450 RX DQ/DQS(RDDQC) : PASS
9159 23:45:39.217648 TX DQ/DQS : PASS
9160 23:45:39.218068 RX DATLAT : PASS
9161 23:45:39.221268 RX DQ/DQS(Engine): PASS
9162 23:45:39.224125 TX OE : PASS
9163 23:45:39.224548 All Pass.
9164 23:45:39.224874
9165 23:45:39.225181 DramC Write-DBI on
9166 23:45:39.227978 PER_BANK_REFRESH: Hybrid Mode
9167 23:45:39.230812 TX_TRACKING: ON
9168 23:45:39.237715 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9169 23:45:39.247460 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9170 23:45:39.254426 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9171 23:45:39.257377 [FAST_K] Save calibration result to emmc
9172 23:45:39.260429 sync common calibartion params.
9173 23:45:39.264044 sync cbt_mode0:1, 1:1
9174 23:45:39.264663 dram_init: ddr_geometry: 2
9175 23:45:39.267297 dram_init: ddr_geometry: 2
9176 23:45:39.271050 dram_init: ddr_geometry: 2
9177 23:45:39.271619 0:dram_rank_size:100000000
9178 23:45:39.274134 1:dram_rank_size:100000000
9179 23:45:39.280352 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9180 23:45:39.283352 DFS_SHUFFLE_HW_MODE: ON
9181 23:45:39.286916 dramc_set_vcore_voltage set vcore to 725000
9182 23:45:39.287379 Read voltage for 1600, 0
9183 23:45:39.290349 Vio18 = 0
9184 23:45:39.290813 Vcore = 725000
9185 23:45:39.291176 Vdram = 0
9186 23:45:39.293957 Vddq = 0
9187 23:45:39.294579 Vmddr = 0
9188 23:45:39.296811 switch to 3200 Mbps bootup
9189 23:45:39.297340 [DramcRunTimeConfig]
9190 23:45:39.297710 PHYPLL
9191 23:45:39.300039 DPM_CONTROL_AFTERK: ON
9192 23:45:39.303098 PER_BANK_REFRESH: ON
9193 23:45:39.306584 REFRESH_OVERHEAD_REDUCTION: ON
9194 23:45:39.307130 CMD_PICG_NEW_MODE: OFF
9195 23:45:39.309756 XRTWTW_NEW_MODE: ON
9196 23:45:39.310266 XRTRTR_NEW_MODE: ON
9197 23:45:39.313175 TX_TRACKING: ON
9198 23:45:39.313622 RDSEL_TRACKING: OFF
9199 23:45:39.316339 DQS Precalculation for DVFS: ON
9200 23:45:39.319584 RX_TRACKING: OFF
9201 23:45:39.320012 HW_GATING DBG: ON
9202 23:45:39.322963 ZQCS_ENABLE_LP4: ON
9203 23:45:39.323394 RX_PICG_NEW_MODE: ON
9204 23:45:39.326125 TX_PICG_NEW_MODE: ON
9205 23:45:39.326598 ENABLE_RX_DCM_DPHY: ON
9206 23:45:39.329767 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9207 23:45:39.333534 DUMMY_READ_FOR_TRACKING: OFF
9208 23:45:39.336264 !!! SPM_CONTROL_AFTERK: OFF
9209 23:45:39.339395 !!! SPM could not control APHY
9210 23:45:39.339827 IMPEDANCE_TRACKING: ON
9211 23:45:39.342938 TEMP_SENSOR: ON
9212 23:45:39.343372 HW_SAVE_FOR_SR: OFF
9213 23:45:39.346270 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9214 23:45:39.349227 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9215 23:45:39.352632 Read ODT Tracking: ON
9216 23:45:39.356040 Refresh Rate DeBounce: ON
9217 23:45:39.356464 DFS_NO_QUEUE_FLUSH: ON
9218 23:45:39.358937 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9219 23:45:39.362734 ENABLE_DFS_RUNTIME_MRW: OFF
9220 23:45:39.366059 DDR_RESERVE_NEW_MODE: ON
9221 23:45:39.366530 MR_CBT_SWITCH_FREQ: ON
9222 23:45:39.369314 =========================
9223 23:45:39.388066 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9224 23:45:39.391208 dram_init: ddr_geometry: 2
9225 23:45:39.409982 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9226 23:45:39.412964 dram_init: dram init end (result: 0)
9227 23:45:39.420089 DRAM-K: Full calibration passed in 24619 msecs
9228 23:45:39.423168 MRC: failed to locate region type 0.
9229 23:45:39.423635 DRAM rank0 size:0x100000000,
9230 23:45:39.426145 DRAM rank1 size=0x100000000
9231 23:45:39.436098 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9232 23:45:39.442548 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9233 23:45:39.452469 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9234 23:45:39.459090 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9235 23:45:39.459516 DRAM rank0 size:0x100000000,
9236 23:45:39.462828 DRAM rank1 size=0x100000000
9237 23:45:39.463384 CBMEM:
9238 23:45:39.465330 IMD: root @ 0xfffff000 254 entries.
9239 23:45:39.469216 IMD: root @ 0xffffec00 62 entries.
9240 23:45:39.475553 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9241 23:45:39.478866 WARNING: RO_VPD is uninitialized or empty.
9242 23:45:39.482137 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9243 23:45:39.490128 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9244 23:45:39.502921 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9245 23:45:39.514335 BS: romstage times (exec / console): total (unknown) / 24109 ms
9246 23:45:39.514908
9247 23:45:39.515394
9248 23:45:39.523993 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9249 23:45:39.527062 ARM64: Exception handlers installed.
9250 23:45:39.530777 ARM64: Testing exception
9251 23:45:39.533669 ARM64: Done test exception
9252 23:45:39.534302 Enumerating buses...
9253 23:45:39.537012 Show all devs... Before device enumeration.
9254 23:45:39.540726 Root Device: enabled 1
9255 23:45:39.543795 CPU_CLUSTER: 0: enabled 1
9256 23:45:39.544269 CPU: 00: enabled 1
9257 23:45:39.547053 Compare with tree...
9258 23:45:39.547527 Root Device: enabled 1
9259 23:45:39.550013 CPU_CLUSTER: 0: enabled 1
9260 23:45:39.553565 CPU: 00: enabled 1
9261 23:45:39.554142 Root Device scanning...
9262 23:45:39.556869 scan_static_bus for Root Device
9263 23:45:39.560166 CPU_CLUSTER: 0 enabled
9264 23:45:39.563822 scan_static_bus for Root Device done
9265 23:45:39.566595 scan_bus: bus Root Device finished in 8 msecs
9266 23:45:39.567164 done
9267 23:45:39.573779 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9268 23:45:39.576682 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9269 23:45:39.583240 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9270 23:45:39.586969 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9271 23:45:39.590220 Allocating resources...
9272 23:45:39.593555 Reading resources...
9273 23:45:39.596644 Root Device read_resources bus 0 link: 0
9274 23:45:39.599749 DRAM rank0 size:0x100000000,
9275 23:45:39.600220 DRAM rank1 size=0x100000000
9276 23:45:39.606354 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9277 23:45:39.606903 CPU: 00 missing read_resources
9278 23:45:39.613560 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9279 23:45:39.616489 Root Device read_resources bus 0 link: 0 done
9280 23:45:39.619413 Done reading resources.
9281 23:45:39.622553 Show resources in subtree (Root Device)...After reading.
9282 23:45:39.626005 Root Device child on link 0 CPU_CLUSTER: 0
9283 23:45:39.629591 CPU_CLUSTER: 0 child on link 0 CPU: 00
9284 23:45:39.639243 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9285 23:45:39.639811 CPU: 00
9286 23:45:39.645783 Root Device assign_resources, bus 0 link: 0
9287 23:45:39.648963 CPU_CLUSTER: 0 missing set_resources
9288 23:45:39.652151 Root Device assign_resources, bus 0 link: 0 done
9289 23:45:39.652619 Done setting resources.
9290 23:45:39.659407 Show resources in subtree (Root Device)...After assigning values.
9291 23:45:39.662431 Root Device child on link 0 CPU_CLUSTER: 0
9292 23:45:39.669196 CPU_CLUSTER: 0 child on link 0 CPU: 00
9293 23:45:39.675897 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9294 23:45:39.678739 CPU: 00
9295 23:45:39.679208 Done allocating resources.
9296 23:45:39.685527 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9297 23:45:39.686102 Enabling resources...
9298 23:45:39.688542 done.
9299 23:45:39.692060 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9300 23:45:39.695701 Initializing devices...
9301 23:45:39.696264 Root Device init
9302 23:45:39.698264 init hardware done!
9303 23:45:39.698727 0x00000018: ctrlr->caps
9304 23:45:39.702208 52.000 MHz: ctrlr->f_max
9305 23:45:39.705109 0.400 MHz: ctrlr->f_min
9306 23:45:39.708065 0x40ff8080: ctrlr->voltages
9307 23:45:39.708603 sclk: 390625
9308 23:45:39.709102 Bus Width = 1
9309 23:45:39.711845 sclk: 390625
9310 23:45:39.712307 Bus Width = 1
9311 23:45:39.714796 Early init status = 3
9312 23:45:39.718635 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9313 23:45:39.721758 in-header: 03 fc 00 00 01 00 00 00
9314 23:45:39.725186 in-data: 00
9315 23:45:39.728289 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9316 23:45:39.732503 in-header: 03 fd 00 00 00 00 00 00
9317 23:45:39.736150 in-data:
9318 23:45:39.739086 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9319 23:45:39.742829 in-header: 03 fc 00 00 01 00 00 00
9320 23:45:39.745946 in-data: 00
9321 23:45:39.749340 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9322 23:45:39.754552 in-header: 03 fd 00 00 00 00 00 00
9323 23:45:39.757343 in-data:
9324 23:45:39.760673 [SSUSB] Setting up USB HOST controller...
9325 23:45:39.764921 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9326 23:45:39.767144 [SSUSB] phy power-on done.
9327 23:45:39.770905 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9328 23:45:39.777312 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9329 23:45:39.780576 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9330 23:45:39.787011 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9331 23:45:39.793479 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9332 23:45:39.800237 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9333 23:45:39.806903 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9334 23:45:39.813267 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9335 23:45:39.816544 SPM: binary array size = 0x9dc
9336 23:45:39.819679 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9337 23:45:39.826488 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9338 23:45:39.833254 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9339 23:45:39.840136 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9340 23:45:39.842675 configure_display: Starting display init
9341 23:45:39.877727 anx7625_power_on_init: Init interface.
9342 23:45:39.880885 anx7625_disable_pd_protocol: Disabled PD feature.
9343 23:45:39.884258 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9344 23:45:39.912285 anx7625_start_dp_work: Secure OCM version=00
9345 23:45:39.914890 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9346 23:45:39.930328 sp_tx_get_edid_block: EDID Block = 1
9347 23:45:40.032842 Extracted contents:
9348 23:45:40.035988 header: 00 ff ff ff ff ff ff 00
9349 23:45:40.039385 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9350 23:45:40.042496 version: 01 04
9351 23:45:40.045709 basic params: 95 1f 11 78 0a
9352 23:45:40.049369 chroma info: 76 90 94 55 54 90 27 21 50 54
9353 23:45:40.052199 established: 00 00 00
9354 23:45:40.059064 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9355 23:45:40.062472 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9356 23:45:40.069013 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9357 23:45:40.075550 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9358 23:45:40.082295 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9359 23:45:40.085104 extensions: 00
9360 23:45:40.085583 checksum: fb
9361 23:45:40.086060
9362 23:45:40.091749 Manufacturer: IVO Model 57d Serial Number 0
9363 23:45:40.092330 Made week 0 of 2020
9364 23:45:40.095434 EDID version: 1.4
9365 23:45:40.095908 Digital display
9366 23:45:40.098476 6 bits per primary color channel
9367 23:45:40.101359 DisplayPort interface
9368 23:45:40.101837 Maximum image size: 31 cm x 17 cm
9369 23:45:40.104654 Gamma: 220%
9370 23:45:40.105125 Check DPMS levels
9371 23:45:40.111286 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9372 23:45:40.114705 First detailed timing is preferred timing
9373 23:45:40.117998 Established timings supported:
9374 23:45:40.118512 Standard timings supported:
9375 23:45:40.122094 Detailed timings
9376 23:45:40.124273 Hex of detail: 383680a07038204018303c0035ae10000019
9377 23:45:40.130951 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9378 23:45:40.134255 0780 0798 07c8 0820 hborder 0
9379 23:45:40.137425 0438 043b 0447 0458 vborder 0
9380 23:45:40.141039 -hsync -vsync
9381 23:45:40.141470 Did detailed timing
9382 23:45:40.147780 Hex of detail: 000000000000000000000000000000000000
9383 23:45:40.151240 Manufacturer-specified data, tag 0
9384 23:45:40.154254 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9385 23:45:40.157438 ASCII string: InfoVision
9386 23:45:40.160451 Hex of detail: 000000fe00523134304e574635205248200a
9387 23:45:40.163933 ASCII string: R140NWF5 RH
9388 23:45:40.164362 Checksum
9389 23:45:40.167023 Checksum: 0xfb (valid)
9390 23:45:40.170865 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9391 23:45:40.174255 DSI data_rate: 832800000 bps
9392 23:45:40.180304 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9393 23:45:40.184064 anx7625_parse_edid: pixelclock(138800).
9394 23:45:40.186708 hactive(1920), hsync(48), hfp(24), hbp(88)
9395 23:45:40.190269 vactive(1080), vsync(12), vfp(3), vbp(17)
9396 23:45:40.193322 anx7625_dsi_config: config dsi.
9397 23:45:40.200474 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9398 23:45:40.214519 anx7625_dsi_config: success to config DSI
9399 23:45:40.217660 anx7625_dp_start: MIPI phy setup OK.
9400 23:45:40.221073 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9401 23:45:40.224157 mtk_ddp_mode_set invalid vrefresh 60
9402 23:45:40.228184 main_disp_path_setup
9403 23:45:40.228698 ovl_layer_smi_id_en
9404 23:45:40.230935 ovl_layer_smi_id_en
9405 23:45:40.231396 ccorr_config
9406 23:45:40.231757 aal_config
9407 23:45:40.234629 gamma_config
9408 23:45:40.235182 postmask_config
9409 23:45:40.237463 dither_config
9410 23:45:40.241241 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9411 23:45:40.247932 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9412 23:45:40.251044 Root Device init finished in 551 msecs
9413 23:45:40.254276 CPU_CLUSTER: 0 init
9414 23:45:40.260943 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9415 23:45:40.267249 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9416 23:45:40.267863 APU_MBOX 0x190000b0 = 0x10001
9417 23:45:40.270642 APU_MBOX 0x190001b0 = 0x10001
9418 23:45:40.273843 APU_MBOX 0x190005b0 = 0x10001
9419 23:45:40.277103 APU_MBOX 0x190006b0 = 0x10001
9420 23:45:40.283797 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9421 23:45:40.293945 read SPI 0x539f4 0xe237: 6246 us, 9271 KB/s, 74.168 Mbps
9422 23:45:40.306211 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9423 23:45:40.312506 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9424 23:45:40.324249 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9425 23:45:40.333740 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9426 23:45:40.336833 CPU_CLUSTER: 0 init finished in 81 msecs
9427 23:45:40.340348 Devices initialized
9428 23:45:40.342929 Show all devs... After init.
9429 23:45:40.343396 Root Device: enabled 1
9430 23:45:40.346349 CPU_CLUSTER: 0: enabled 1
9431 23:45:40.349754 CPU: 00: enabled 1
9432 23:45:40.353218 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9433 23:45:40.356269 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9434 23:45:40.359553 ELOG: NV offset 0x57f000 size 0x1000
9435 23:45:40.366782 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9436 23:45:40.373373 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9437 23:45:40.376475 ELOG: Event(17) added with size 13 at 2024-06-04 23:45:40 UTC
9438 23:45:40.382876 out: cmd=0x121: 03 db 21 01 00 00 00 00
9439 23:45:40.386384 in-header: 03 37 00 00 2c 00 00 00
9440 23:45:40.399377 in-data: 05 73 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9441 23:45:40.402590 ELOG: Event(A1) added with size 10 at 2024-06-04 23:45:40 UTC
9442 23:45:40.408975 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9443 23:45:40.416168 ELOG: Event(A0) added with size 9 at 2024-06-04 23:45:40 UTC
9444 23:45:40.418778 elog_add_boot_reason: Logged dev mode boot
9445 23:45:40.425685 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9446 23:45:40.426303 Finalize devices...
9447 23:45:40.429211 Devices finalized
9448 23:45:40.432388 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9449 23:45:40.435345 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9450 23:45:40.438566 in-header: 03 07 00 00 08 00 00 00
9451 23:45:40.442395 in-data: aa e4 47 04 13 02 00 00
9452 23:45:40.445572 Chrome EC: UHEPI supported
9453 23:45:40.452100 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9454 23:45:40.454944 in-header: 03 a9 00 00 08 00 00 00
9455 23:45:40.458786 in-data: 84 60 60 08 00 00 00 00
9456 23:45:40.465148 ELOG: Event(91) added with size 10 at 2024-06-04 23:45:40 UTC
9457 23:45:40.468302 Chrome EC: clear events_b mask to 0x0000000020004000
9458 23:45:40.474643 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9459 23:45:40.479704 in-header: 03 fd 00 00 00 00 00 00
9460 23:45:40.482774 in-data:
9461 23:45:40.486379 BS: BS_WRITE_TABLES entry times (exec / console): 3 / 46 ms
9462 23:45:40.490116 Writing coreboot table at 0xffe64000
9463 23:45:40.496046 0. 000000000010a000-0000000000113fff: RAMSTAGE
9464 23:45:40.499488 1. 0000000040000000-00000000400fffff: RAM
9465 23:45:40.502786 2. 0000000040100000-000000004032afff: RAMSTAGE
9466 23:45:40.506132 3. 000000004032b000-00000000545fffff: RAM
9467 23:45:40.509577 4. 0000000054600000-000000005465ffff: BL31
9468 23:45:40.513265 5. 0000000054660000-00000000ffe63fff: RAM
9469 23:45:40.519914 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9470 23:45:40.522691 7. 0000000100000000-000000023fffffff: RAM
9471 23:45:40.525814 Passing 5 GPIOs to payload:
9472 23:45:40.529793 NAME | PORT | POLARITY | VALUE
9473 23:45:40.536148 EC in RW | 0x000000aa | low | undefined
9474 23:45:40.539251 EC interrupt | 0x00000005 | low | undefined
9475 23:45:40.545607 TPM interrupt | 0x000000ab | high | undefined
9476 23:45:40.548775 SD card detect | 0x00000011 | high | undefined
9477 23:45:40.552280 speaker enable | 0x00000093 | high | undefined
9478 23:45:40.555562 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9479 23:45:40.559393 in-header: 03 f9 00 00 02 00 00 00
9480 23:45:40.563028 in-data: 02 00
9481 23:45:40.566550 ADC[4]: Raw value=900443 ID=7
9482 23:45:40.569278 ADC[3]: Raw value=212912 ID=1
9483 23:45:40.569691 RAM Code: 0x71
9484 23:45:40.572506 ADC[6]: Raw value=75036 ID=0
9485 23:45:40.575925 ADC[5]: Raw value=212912 ID=1
9486 23:45:40.576338 SKU Code: 0x1
9487 23:45:40.582399 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum ad69
9488 23:45:40.582815 coreboot table: 964 bytes.
9489 23:45:40.585814 IMD ROOT 0. 0xfffff000 0x00001000
9490 23:45:40.588790 IMD SMALL 1. 0xffffe000 0x00001000
9491 23:45:40.592460 RO MCACHE 2. 0xffffc000 0x00001104
9492 23:45:40.596036 CONSOLE 3. 0xfff7c000 0x00080000
9493 23:45:40.599427 FMAP 4. 0xfff7b000 0x00000452
9494 23:45:40.602350 TIME STAMP 5. 0xfff7a000 0x00000910
9495 23:45:40.605509 VBOOT WORK 6. 0xfff66000 0x00014000
9496 23:45:40.608794 RAMOOPS 7. 0xffe66000 0x00100000
9497 23:45:40.612570 COREBOOT 8. 0xffe64000 0x00002000
9498 23:45:40.615730 IMD small region:
9499 23:45:40.619185 IMD ROOT 0. 0xffffec00 0x00000400
9500 23:45:40.622232 VPD 1. 0xffffeb80 0x0000006c
9501 23:45:40.626264 MMC STATUS 2. 0xffffeb60 0x00000004
9502 23:45:40.629500 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9503 23:45:40.635551 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9504 23:45:40.677119 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9505 23:45:40.680079 Checking segment from ROM address 0x40100000
9506 23:45:40.684064 Checking segment from ROM address 0x4010001c
9507 23:45:40.690111 Loading segment from ROM address 0x40100000
9508 23:45:40.690748 code (compression=0)
9509 23:45:40.700306 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9510 23:45:40.706713 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9511 23:45:40.707386 it's not compressed!
9512 23:45:40.713409 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9513 23:45:40.719912 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9514 23:45:40.737923 Loading segment from ROM address 0x4010001c
9515 23:45:40.738590 Entry Point 0x80000000
9516 23:45:40.741285 Loaded segments
9517 23:45:40.743849 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9518 23:45:40.750634 Jumping to boot code at 0x80000000(0xffe64000)
9519 23:45:40.757573 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9520 23:45:40.763801 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9521 23:45:40.771682 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9522 23:45:40.775028 Checking segment from ROM address 0x40100000
9523 23:45:40.778598 Checking segment from ROM address 0x4010001c
9524 23:45:40.785012 Loading segment from ROM address 0x40100000
9525 23:45:40.785600 code (compression=1)
9526 23:45:40.791630 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9527 23:45:40.801192 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9528 23:45:40.801767 using LZMA
9529 23:45:40.810304 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9530 23:45:40.816913 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9531 23:45:40.819944 Loading segment from ROM address 0x4010001c
9532 23:45:40.820434 Entry Point 0x54601000
9533 23:45:40.823225 Loaded segments
9534 23:45:40.826703 NOTICE: MT8192 bl31_setup
9535 23:45:40.833685 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9536 23:45:40.837137 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9537 23:45:40.840231 WARNING: region 0:
9538 23:45:40.843870 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9539 23:45:40.844354 WARNING: region 1:
9540 23:45:40.850082 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9541 23:45:40.853330 WARNING: region 2:
9542 23:45:40.857876 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9543 23:45:40.860282 WARNING: region 3:
9544 23:45:40.863511 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9545 23:45:40.867205 WARNING: region 4:
9546 23:45:40.873346 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9547 23:45:40.873931 WARNING: region 5:
9548 23:45:40.877054 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9549 23:45:40.880259 WARNING: region 6:
9550 23:45:40.883585 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9551 23:45:40.887077 WARNING: region 7:
9552 23:45:40.889960 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9553 23:45:40.897474 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9554 23:45:40.900663 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9555 23:45:40.906964 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9556 23:45:40.910194 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9557 23:45:40.913161 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9558 23:45:40.919902 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9559 23:45:40.922760 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9560 23:45:40.926098 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9561 23:45:40.932626 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9562 23:45:40.936289 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9563 23:45:40.942748 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9564 23:45:40.945961 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9565 23:45:40.949204 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9566 23:45:40.956029 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9567 23:45:40.959357 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9568 23:45:40.962700 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9569 23:45:40.969377 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9570 23:45:40.972478 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9571 23:45:40.979424 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9572 23:45:40.982483 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9573 23:45:40.985966 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9574 23:45:40.992791 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9575 23:45:40.996054 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9576 23:45:41.002574 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9577 23:45:41.005392 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9578 23:45:41.008823 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9579 23:45:41.015855 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9580 23:45:41.018582 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9581 23:45:41.025808 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9582 23:45:41.028510 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9583 23:45:41.031846 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9584 23:45:41.038568 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9585 23:45:41.042349 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9586 23:45:41.045594 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9587 23:45:41.051868 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9588 23:45:41.054888 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9589 23:45:41.058428 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9590 23:45:41.061863 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9591 23:45:41.068187 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9592 23:45:41.071664 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9593 23:45:41.074592 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9594 23:45:41.078779 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9595 23:45:41.084891 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9596 23:45:41.088241 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9597 23:45:41.091835 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9598 23:45:41.094764 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9599 23:45:41.101218 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9600 23:45:41.104822 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9601 23:45:41.108026 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9602 23:45:41.114590 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9603 23:45:41.118012 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9604 23:45:41.124451 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9605 23:45:41.127987 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9606 23:45:41.134822 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9607 23:45:41.137636 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9608 23:45:41.144505 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9609 23:45:41.147977 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9610 23:45:41.150862 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9611 23:45:41.157639 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9612 23:45:41.160805 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9613 23:45:41.167481 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9614 23:45:41.170893 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9615 23:45:41.177716 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9616 23:45:41.180728 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9617 23:45:41.187141 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9618 23:45:41.190531 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9619 23:45:41.197256 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9620 23:45:41.200438 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9621 23:45:41.203553 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9622 23:45:41.210100 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9623 23:45:41.214103 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9624 23:45:41.220104 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9625 23:45:41.223358 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9626 23:45:41.230329 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9627 23:45:41.233521 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9628 23:45:41.236762 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9629 23:45:41.243979 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9630 23:45:41.246895 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9631 23:45:41.253193 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9632 23:45:41.256455 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9633 23:45:41.263392 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9634 23:45:41.266698 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9635 23:45:41.273137 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9636 23:45:41.276391 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9637 23:45:41.280201 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9638 23:45:41.286701 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9639 23:45:41.290540 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9640 23:45:41.296701 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9641 23:45:41.300039 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9642 23:45:41.306503 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9643 23:45:41.309656 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9644 23:45:41.313245 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9645 23:45:41.319570 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9646 23:45:41.322728 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9647 23:45:41.329358 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9648 23:45:41.333080 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9649 23:45:41.336942 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9650 23:45:41.343527 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9651 23:45:41.346586 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9652 23:45:41.349671 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9653 23:45:41.353916 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9654 23:45:41.359690 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9655 23:45:41.363096 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9656 23:45:41.369830 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9657 23:45:41.372839 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9658 23:45:41.379140 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9659 23:45:41.382668 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9660 23:45:41.386618 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9661 23:45:41.392367 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9662 23:45:41.395647 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9663 23:45:41.402887 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9664 23:45:41.405596 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9665 23:45:41.409046 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9666 23:45:41.415392 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9667 23:45:41.418854 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9668 23:45:41.425422 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9669 23:45:41.428659 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9670 23:45:41.432176 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9671 23:45:41.438734 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9672 23:45:41.441880 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9673 23:45:41.445368 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9674 23:45:41.448642 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9675 23:45:41.452285 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9676 23:45:41.458708 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9677 23:45:41.462111 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9678 23:45:41.469178 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9679 23:45:41.472001 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9680 23:45:41.475213 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9681 23:45:41.482062 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9682 23:45:41.485387 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9683 23:45:41.492094 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9684 23:45:41.494876 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9685 23:45:41.498300 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9686 23:45:41.505020 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9687 23:45:41.508613 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9688 23:45:41.514826 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9689 23:45:41.517967 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9690 23:45:41.521725 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9691 23:45:41.528015 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9692 23:45:41.530993 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9693 23:45:41.537955 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9694 23:45:41.541374 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9695 23:45:41.544195 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9696 23:45:41.550901 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9697 23:45:41.554201 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9698 23:45:41.561688 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9699 23:45:41.564107 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9700 23:45:41.567632 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9701 23:45:41.574093 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9702 23:45:41.577162 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9703 23:45:41.584443 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9704 23:45:41.587769 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9705 23:45:41.590835 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9706 23:45:41.597463 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9707 23:45:41.601050 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9708 23:45:41.607394 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9709 23:45:41.610555 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9710 23:45:41.613702 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9711 23:45:41.620679 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9712 23:45:41.623802 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9713 23:45:41.630487 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9714 23:45:41.633973 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9715 23:45:41.636938 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9716 23:45:41.643734 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9717 23:45:41.647069 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9718 23:45:41.653469 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9719 23:45:41.656711 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9720 23:45:41.660341 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9721 23:45:41.666682 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9722 23:45:41.669714 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9723 23:45:41.676850 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9724 23:45:41.679484 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9725 23:45:41.682841 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9726 23:45:41.689554 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9727 23:45:41.692838 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9728 23:45:41.696362 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9729 23:45:41.703062 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9730 23:45:41.706492 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9731 23:45:41.712810 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9732 23:45:41.716839 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9733 23:45:41.719757 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9734 23:45:41.725981 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9735 23:45:41.729695 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9736 23:45:41.736074 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9737 23:45:41.739741 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9738 23:45:41.742537 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9739 23:45:41.749600 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9740 23:45:41.752903 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9741 23:45:41.759073 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9742 23:45:41.762798 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9743 23:45:41.769857 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9744 23:45:41.772825 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9745 23:45:41.776271 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9746 23:45:41.782620 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9747 23:45:41.785694 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9748 23:45:41.792460 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9749 23:45:41.795739 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9750 23:45:41.799111 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9751 23:45:41.805727 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9752 23:45:41.809233 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9753 23:45:41.815736 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9754 23:45:41.818800 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9755 23:45:41.825485 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9756 23:45:41.828691 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9757 23:45:41.832158 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9758 23:45:41.838610 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9759 23:45:41.842251 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9760 23:45:41.848749 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9761 23:45:41.852034 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9762 23:45:41.858684 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9763 23:45:41.861958 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9764 23:45:41.865247 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9765 23:45:41.871724 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9766 23:45:41.875159 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9767 23:45:41.881795 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9768 23:45:41.885115 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9769 23:45:41.888511 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9770 23:45:41.894961 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9771 23:45:41.898546 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9772 23:45:41.905230 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9773 23:45:41.908193 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9774 23:45:41.914875 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9775 23:45:41.917863 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9776 23:45:41.920976 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9777 23:45:41.927608 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9778 23:45:41.931072 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9779 23:45:41.937918 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9780 23:45:41.941025 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9781 23:45:41.947644 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9782 23:45:41.950736 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9783 23:45:41.954122 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9784 23:45:41.957265 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9785 23:45:41.960972 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9786 23:45:41.967648 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9787 23:45:41.971289 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9788 23:45:41.974102 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9789 23:45:41.981650 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9790 23:45:41.984159 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9791 23:45:41.991113 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9792 23:45:41.993861 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9793 23:45:41.997245 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9794 23:45:42.003895 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9795 23:45:42.007031 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9796 23:45:42.010285 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9797 23:45:42.016860 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9798 23:45:42.020545 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9799 23:45:42.026899 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9800 23:45:42.030389 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9801 23:45:42.033305 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9802 23:45:42.040072 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9803 23:45:42.043417 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9804 23:45:42.046702 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9805 23:45:42.053572 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9806 23:45:42.057157 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9807 23:45:42.063192 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9808 23:45:42.066479 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9809 23:45:42.070124 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9810 23:45:42.076575 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9811 23:45:42.080088 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9812 23:45:42.083104 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9813 23:45:42.089617 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9814 23:45:42.093111 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9815 23:45:42.099724 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9816 23:45:42.102952 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9817 23:45:42.106767 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9818 23:45:42.113059 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9819 23:45:42.115975 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9820 23:45:42.119824 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9821 23:45:42.126444 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9822 23:45:42.129654 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9823 23:45:42.132712 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9824 23:45:42.136079 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9825 23:45:42.142684 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9826 23:45:42.147073 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9827 23:45:42.149368 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9828 23:45:42.152794 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9829 23:45:42.159187 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9830 23:45:42.163008 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9831 23:45:42.165759 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9832 23:45:42.169182 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9833 23:45:42.176454 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9834 23:45:42.178775 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9835 23:45:42.182522 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9836 23:45:42.188914 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9837 23:45:42.192690 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9838 23:45:42.199097 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9839 23:45:42.202230 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9840 23:45:42.208866 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9841 23:45:42.212124 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9842 23:45:42.215899 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9843 23:45:42.221959 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9844 23:45:42.225689 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9845 23:45:42.231664 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9846 23:45:42.235126 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9847 23:45:42.238760 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9848 23:45:42.245192 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9849 23:45:42.248798 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9850 23:45:42.255407 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9851 23:45:42.258374 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9852 23:45:42.262045 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9853 23:45:42.268440 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9854 23:45:42.271790 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9855 23:45:42.278394 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9856 23:45:42.281235 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9857 23:45:42.288313 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9858 23:45:42.291494 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9859 23:45:42.294762 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9860 23:45:42.301326 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9861 23:45:42.304157 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9862 23:45:42.310963 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9863 23:45:42.314533 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9864 23:45:42.320914 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9865 23:45:42.324072 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9866 23:45:42.327407 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9867 23:45:42.334154 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9868 23:45:42.337912 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9869 23:45:42.344222 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9870 23:45:42.347504 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9871 23:45:42.350713 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9872 23:45:42.357088 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9873 23:45:42.360957 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9874 23:45:42.367665 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9875 23:45:42.370484 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9876 23:45:42.373888 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9877 23:45:42.380171 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9878 23:45:42.383814 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9879 23:45:42.390369 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9880 23:45:42.393798 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9881 23:45:42.400550 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9882 23:45:42.403590 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9883 23:45:42.407052 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9884 23:45:42.413589 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9885 23:45:42.417194 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9886 23:45:42.423540 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9887 23:45:42.426737 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9888 23:45:42.433064 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9889 23:45:42.436662 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9890 23:45:42.439696 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9891 23:45:42.446552 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9892 23:45:42.450007 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9893 23:45:42.456556 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9894 23:45:42.459548 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9895 23:45:42.463180 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9896 23:45:42.469952 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9897 23:45:42.473071 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9898 23:45:42.479837 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9899 23:45:42.482902 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9900 23:45:42.486625 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9901 23:45:42.493078 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9902 23:45:42.496520 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9903 23:45:42.503155 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9904 23:45:42.506531 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9905 23:45:42.512974 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9906 23:45:42.516479 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9907 23:45:42.519451 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9908 23:45:42.526258 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9909 23:45:42.529524 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9910 23:45:42.536225 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9911 23:45:42.539005 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9912 23:45:42.546065 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9913 23:45:42.549182 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9914 23:45:42.552166 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9915 23:45:42.558888 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9916 23:45:42.562345 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9917 23:45:42.569342 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9918 23:45:42.572577 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9919 23:45:42.578946 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9920 23:45:42.582269 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9921 23:45:42.588598 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9922 23:45:42.592714 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9923 23:45:42.595147 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9924 23:45:42.601637 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9925 23:45:42.604876 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9926 23:45:42.611835 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9927 23:45:42.615342 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9928 23:45:42.621694 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9929 23:45:42.625377 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9930 23:45:42.628049 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9931 23:45:42.634766 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9932 23:45:42.638337 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9933 23:45:42.645018 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9934 23:45:42.648330 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9935 23:45:42.655450 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9936 23:45:42.658025 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9937 23:45:42.664855 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9938 23:45:42.668228 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9939 23:45:42.671407 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9940 23:45:42.678337 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9941 23:45:42.681382 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9942 23:45:42.687990 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9943 23:45:42.691136 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9944 23:45:42.698093 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9945 23:45:42.701097 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9946 23:45:42.704945 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9947 23:45:42.711259 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9948 23:45:42.714398 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9949 23:45:42.721226 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9950 23:45:42.724396 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9951 23:45:42.730900 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9952 23:45:42.734269 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9953 23:45:42.741492 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9954 23:45:42.744225 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9955 23:45:42.747752 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9956 23:45:42.754052 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9957 23:45:42.757983 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9958 23:45:42.764487 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9959 23:45:42.767409 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9960 23:45:42.773921 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9961 23:45:42.777577 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9962 23:45:42.783905 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9963 23:45:42.786970 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9964 23:45:42.793934 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9965 23:45:42.797148 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9966 23:45:42.803862 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9967 23:45:42.806950 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9968 23:45:42.810346 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9969 23:45:42.816867 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9970 23:45:42.820542 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9971 23:45:42.826640 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9972 23:45:42.830095 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9973 23:45:42.836668 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9974 23:45:42.840497 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9975 23:45:42.846494 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9976 23:45:42.850276 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9977 23:45:42.856602 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9978 23:45:42.859959 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9979 23:45:42.866636 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9980 23:45:42.869935 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9981 23:45:42.876278 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9982 23:45:42.879856 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9983 23:45:42.886333 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9984 23:45:42.893118 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9985 23:45:42.896175 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9986 23:45:42.903048 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9987 23:45:42.905818 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9988 23:45:42.906261 INFO: [APUAPC] vio 0
9989 23:45:42.913514 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9990 23:45:42.917327 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9991 23:45:42.920113 INFO: [APUAPC] D0_APC_0: 0x400510
9992 23:45:42.923451 INFO: [APUAPC] D0_APC_1: 0x0
9993 23:45:42.926488 INFO: [APUAPC] D0_APC_2: 0x1540
9994 23:45:42.930139 INFO: [APUAPC] D0_APC_3: 0x0
9995 23:45:42.933286 INFO: [APUAPC] D1_APC_0: 0xffffffff
9996 23:45:42.936526 INFO: [APUAPC] D1_APC_1: 0xffffffff
9997 23:45:42.939676 INFO: [APUAPC] D1_APC_2: 0x3fffff
9998 23:45:42.943179 INFO: [APUAPC] D1_APC_3: 0x0
9999 23:45:42.946580 INFO: [APUAPC] D2_APC_0: 0xffffffff
10000 23:45:42.949638 INFO: [APUAPC] D2_APC_1: 0xffffffff
10001 23:45:42.953112 INFO: [APUAPC] D2_APC_2: 0x3fffff
10002 23:45:42.956595 INFO: [APUAPC] D2_APC_3: 0x0
10003 23:45:42.959957 INFO: [APUAPC] D3_APC_0: 0xffffffff
10004 23:45:42.963046 INFO: [APUAPC] D3_APC_1: 0xffffffff
10005 23:45:42.966037 INFO: [APUAPC] D3_APC_2: 0x3fffff
10006 23:45:42.969596 INFO: [APUAPC] D3_APC_3: 0x0
10007 23:45:42.973094 INFO: [APUAPC] D4_APC_0: 0xffffffff
10008 23:45:42.976225 INFO: [APUAPC] D4_APC_1: 0xffffffff
10009 23:45:42.979632 INFO: [APUAPC] D4_APC_2: 0x3fffff
10010 23:45:42.982869 INFO: [APUAPC] D4_APC_3: 0x0
10011 23:45:42.986367 INFO: [APUAPC] D5_APC_0: 0xffffffff
10012 23:45:42.989260 INFO: [APUAPC] D5_APC_1: 0xffffffff
10013 23:45:42.993324 INFO: [APUAPC] D5_APC_2: 0x3fffff
10014 23:45:42.995865 INFO: [APUAPC] D5_APC_3: 0x0
10015 23:45:42.999077 INFO: [APUAPC] D6_APC_0: 0xffffffff
10016 23:45:43.002794 INFO: [APUAPC] D6_APC_1: 0xffffffff
10017 23:45:43.006017 INFO: [APUAPC] D6_APC_2: 0x3fffff
10018 23:45:43.009170 INFO: [APUAPC] D6_APC_3: 0x0
10019 23:45:43.012251 INFO: [APUAPC] D7_APC_0: 0xffffffff
10020 23:45:43.015580 INFO: [APUAPC] D7_APC_1: 0xffffffff
10021 23:45:43.018875 INFO: [APUAPC] D7_APC_2: 0x3fffff
10022 23:45:43.019289 INFO: [APUAPC] D7_APC_3: 0x0
10023 23:45:43.025462 INFO: [APUAPC] D8_APC_0: 0xffffffff
10024 23:45:43.028898 INFO: [APUAPC] D8_APC_1: 0xffffffff
10025 23:45:43.032378 INFO: [APUAPC] D8_APC_2: 0x3fffff
10026 23:45:43.032792 INFO: [APUAPC] D8_APC_3: 0x0
10027 23:45:43.035270 INFO: [APUAPC] D9_APC_0: 0xffffffff
10028 23:45:43.042319 INFO: [APUAPC] D9_APC_1: 0xffffffff
10029 23:45:43.046081 INFO: [APUAPC] D9_APC_2: 0x3fffff
10030 23:45:43.046527 INFO: [APUAPC] D9_APC_3: 0x0
10031 23:45:43.048650 INFO: [APUAPC] D10_APC_0: 0xffffffff
10032 23:45:43.054851 INFO: [APUAPC] D10_APC_1: 0xffffffff
10033 23:45:43.058592 INFO: [APUAPC] D10_APC_2: 0x3fffff
10034 23:45:43.059104 INFO: [APUAPC] D10_APC_3: 0x0
10035 23:45:43.061760 INFO: [APUAPC] D11_APC_0: 0xffffffff
10036 23:45:43.068027 INFO: [APUAPC] D11_APC_1: 0xffffffff
10037 23:45:43.072433 INFO: [APUAPC] D11_APC_2: 0x3fffff
10038 23:45:43.072962 INFO: [APUAPC] D11_APC_3: 0x0
10039 23:45:43.078543 INFO: [APUAPC] D12_APC_0: 0xffffffff
10040 23:45:43.081826 INFO: [APUAPC] D12_APC_1: 0xffffffff
10041 23:45:43.084923 INFO: [APUAPC] D12_APC_2: 0x3fffff
10042 23:45:43.089032 INFO: [APUAPC] D12_APC_3: 0x0
10043 23:45:43.091675 INFO: [APUAPC] D13_APC_0: 0xffffffff
10044 23:45:43.095111 INFO: [APUAPC] D13_APC_1: 0xffffffff
10045 23:45:43.097873 INFO: [APUAPC] D13_APC_2: 0x3fffff
10046 23:45:43.101627 INFO: [APUAPC] D13_APC_3: 0x0
10047 23:45:43.104808 INFO: [APUAPC] D14_APC_0: 0xffffffff
10048 23:45:43.107936 INFO: [APUAPC] D14_APC_1: 0xffffffff
10049 23:45:43.111377 INFO: [APUAPC] D14_APC_2: 0x3fffff
10050 23:45:43.114261 INFO: [APUAPC] D14_APC_3: 0x0
10051 23:45:43.117831 INFO: [APUAPC] D15_APC_0: 0xffffffff
10052 23:45:43.121459 INFO: [APUAPC] D15_APC_1: 0xffffffff
10053 23:45:43.124141 INFO: [APUAPC] D15_APC_2: 0x3fffff
10054 23:45:43.127659 INFO: [APUAPC] D15_APC_3: 0x0
10055 23:45:43.128106 INFO: [APUAPC] APC_CON: 0x4
10056 23:45:43.131086 INFO: [NOCDAPC] D0_APC_0: 0x0
10057 23:45:43.134262 INFO: [NOCDAPC] D0_APC_1: 0x0
10058 23:45:43.138033 INFO: [NOCDAPC] D1_APC_0: 0x0
10059 23:45:43.140787 INFO: [NOCDAPC] D1_APC_1: 0xfff
10060 23:45:43.144412 INFO: [NOCDAPC] D2_APC_0: 0x0
10061 23:45:43.147806 INFO: [NOCDAPC] D2_APC_1: 0xfff
10062 23:45:43.151141 INFO: [NOCDAPC] D3_APC_0: 0x0
10063 23:45:43.154348 INFO: [NOCDAPC] D3_APC_1: 0xfff
10064 23:45:43.157177 INFO: [NOCDAPC] D4_APC_0: 0x0
10065 23:45:43.160714 INFO: [NOCDAPC] D4_APC_1: 0xfff
10066 23:45:43.161131 INFO: [NOCDAPC] D5_APC_0: 0x0
10067 23:45:43.163979 INFO: [NOCDAPC] D5_APC_1: 0xfff
10068 23:45:43.167462 INFO: [NOCDAPC] D6_APC_0: 0x0
10069 23:45:43.171197 INFO: [NOCDAPC] D6_APC_1: 0xfff
10070 23:45:43.174229 INFO: [NOCDAPC] D7_APC_0: 0x0
10071 23:45:43.177425 INFO: [NOCDAPC] D7_APC_1: 0xfff
10072 23:45:43.181417 INFO: [NOCDAPC] D8_APC_0: 0x0
10073 23:45:43.185150 INFO: [NOCDAPC] D8_APC_1: 0xfff
10074 23:45:43.187359 INFO: [NOCDAPC] D9_APC_0: 0x0
10075 23:45:43.190735 INFO: [NOCDAPC] D9_APC_1: 0xfff
10076 23:45:43.194003 INFO: [NOCDAPC] D10_APC_0: 0x0
10077 23:45:43.197526 INFO: [NOCDAPC] D10_APC_1: 0xfff
10078 23:45:43.198089 INFO: [NOCDAPC] D11_APC_0: 0x0
10079 23:45:43.200679 INFO: [NOCDAPC] D11_APC_1: 0xfff
10080 23:45:43.203786 INFO: [NOCDAPC] D12_APC_0: 0x0
10081 23:45:43.207394 INFO: [NOCDAPC] D12_APC_1: 0xfff
10082 23:45:43.210418 INFO: [NOCDAPC] D13_APC_0: 0x0
10083 23:45:43.214055 INFO: [NOCDAPC] D13_APC_1: 0xfff
10084 23:45:43.216945 INFO: [NOCDAPC] D14_APC_0: 0x0
10085 23:45:43.220238 INFO: [NOCDAPC] D14_APC_1: 0xfff
10086 23:45:43.223734 INFO: [NOCDAPC] D15_APC_0: 0x0
10087 23:45:43.227013 INFO: [NOCDAPC] D15_APC_1: 0xfff
10088 23:45:43.230067 INFO: [NOCDAPC] APC_CON: 0x4
10089 23:45:43.233444 INFO: [APUAPC] set_apusys_apc done
10090 23:45:43.236702 INFO: [DEVAPC] devapc_init done
10091 23:45:43.239810 INFO: GICv3 without legacy support detected.
10092 23:45:43.243385 INFO: ARM GICv3 driver initialized in EL3
10093 23:45:43.246539 INFO: Maximum SPI INTID supported: 639
10094 23:45:43.253482 INFO: BL31: Initializing runtime services
10095 23:45:43.256456 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10096 23:45:43.259848 INFO: SPM: enable CPC mode
10097 23:45:43.266440 INFO: mcdi ready for mcusys-off-idle and system suspend
10098 23:45:43.269983 INFO: BL31: Preparing for EL3 exit to normal world
10099 23:45:43.272847 INFO: Entry point address = 0x80000000
10100 23:45:43.276538 INFO: SPSR = 0x8
10101 23:45:43.282088
10102 23:45:43.282703
10103 23:45:43.283065
10104 23:45:43.284912 Starting depthcharge on Spherion...
10105 23:45:43.285386
10106 23:45:43.285747 Wipe memory regions:
10107 23:45:43.286083
10108 23:45:43.288554 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
10109 23:45:43.289077 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
10110 23:45:43.289528 Setting prompt string to ['asurada:']
10111 23:45:43.289980 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
10112 23:45:43.290729 [0x00000040000000, 0x00000054600000)
10113 23:45:43.410842
10114 23:45:43.411392 [0x00000054660000, 0x00000080000000)
10115 23:45:43.671343
10116 23:45:43.671896 [0x000000821a7280, 0x000000ffe64000)
10117 23:45:44.416052
10118 23:45:44.419459 [0x00000100000000, 0x00000240000000)
10119 23:45:46.306530
10120 23:45:46.309735 Initializing XHCI USB controller at 0x11200000.
10121 23:45:47.348121
10122 23:45:47.351335 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10123 23:45:47.351896
10124 23:45:47.352264
10125 23:45:47.353085 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10127 23:45:47.454366 asurada: tftpboot 192.168.201.1 14172980/tftp-deploy-2o3salbj/kernel/image.itb 14172980/tftp-deploy-2o3salbj/kernel/cmdline
10128 23:45:47.455064 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10129 23:45:47.455829 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:22)
10130 23:45:47.460489 tftpboot 192.168.201.1 14172980/tftp-deploy-2o3salbj/kernel/image.itp-deploy-2o3salbj/kernel/cmdline
10131 23:45:47.460937
10132 23:45:47.461293 Waiting for link
10133 23:45:47.618769
10134 23:45:47.619341 R8152: Initializing
10135 23:45:47.619705
10136 23:45:47.622035 Version 6 (ocp_data = 5c30)
10137 23:45:47.622547
10138 23:45:47.625533 R8152: Done initializing
10139 23:45:47.626100
10140 23:45:47.626523 Adding net device
10141 23:45:49.527699
10142 23:45:49.528212 done.
10143 23:45:49.528538
10144 23:45:49.528841 MAC: 00:e0:4c:68:02:81
10145 23:45:49.529134
10146 23:45:49.530814 Sending DHCP discover... done.
10147 23:45:49.531269
10148 23:45:59.240299 Waiting for reply... R8152: Bulk read error 0xffffffbf
10149 23:45:59.240881
10150 23:45:59.243020 Receive failed.
10151 23:45:59.243475
10152 23:45:59.243835 done.
10153 23:45:59.244165
10154 23:45:59.246387 Sending DHCP request... done.
10155 23:45:59.246942
10156 23:45:59.253265 Waiting for reply... done.
10157 23:45:59.253863
10158 23:45:59.254413 My ip is 192.168.201.14
10159 23:45:59.254862
10160 23:45:59.256658 The DHCP server ip is 192.168.201.1
10161 23:45:59.257137
10162 23:45:59.262869 TFTP server IP predefined by user: 192.168.201.1
10163 23:45:59.263437
10164 23:45:59.269627 Bootfile predefined by user: 14172980/tftp-deploy-2o3salbj/kernel/image.itb
10165 23:45:59.270260
10166 23:45:59.272757 Sending tftp read request... done.
10167 23:45:59.273232
10168 23:45:59.279569 Waiting for the transfer...
10169 23:45:59.279998
10170 23:45:59.932293 00000000 ################################################################
10171 23:45:59.932870
10172 23:46:00.594434 00080000 ################################################################
10173 23:46:00.594946
10174 23:46:01.253281 00100000 ################################################################
10175 23:46:01.253812
10176 23:46:01.934154 00180000 ################################################################
10177 23:46:01.934756
10178 23:46:02.608643 00200000 ################################################################
10179 23:46:02.609255
10180 23:46:03.272838 00280000 ################################################################
10181 23:46:03.273375
10182 23:46:03.954579 00300000 ################################################################
10183 23:46:03.955117
10184 23:46:04.640554 00380000 ################################################################
10185 23:46:04.641063
10186 23:46:05.308724 00400000 ################################################################
10187 23:46:05.309261
10188 23:46:05.940171 00480000 ################################################################
10189 23:46:05.940315
10190 23:46:06.573564 00500000 ################################################################
10191 23:46:06.573704
10192 23:46:07.159468 00580000 ################################################################
10193 23:46:07.159604
10194 23:46:07.696180 00600000 ################################################################
10195 23:46:07.696329
10196 23:46:08.260522 00680000 ################################################################
10197 23:46:08.260669
10198 23:46:08.826821 00700000 ################################################################
10199 23:46:08.826967
10200 23:46:09.395060 00780000 ################################################################
10201 23:46:09.395326
10202 23:46:09.933665 00800000 ################################################################
10203 23:46:09.933815
10204 23:46:10.506702 00880000 ################################################################
10205 23:46:10.506854
10206 23:46:11.073669 00900000 ################################################################
10207 23:46:11.073809
10208 23:46:11.632260 00980000 ################################################################
10209 23:46:11.632412
10210 23:46:12.193021 00a00000 ################################################################
10211 23:46:12.193171
10212 23:46:12.734131 00a80000 ################################################################
10213 23:46:12.734317
10214 23:46:13.275900 00b00000 ################################################################
10215 23:46:13.276049
10216 23:46:13.829871 00b80000 ################################################################
10217 23:46:13.830007
10218 23:46:14.403684 00c00000 ################################################################
10219 23:46:14.403828
10220 23:46:14.981957 00c80000 ################################################################
10221 23:46:14.982126
10222 23:46:15.554169 00d00000 ################################################################
10223 23:46:15.554321
10224 23:46:16.119573 00d80000 ################################################################
10225 23:46:16.119722
10226 23:46:16.691424 00e00000 ################################################################
10227 23:46:16.691571
10228 23:46:17.300270 00e80000 ################################################################
10229 23:46:17.300693
10230 23:46:17.845689 00f00000 ################################################################
10231 23:46:17.845843
10232 23:46:18.378309 00f80000 ################################################################
10233 23:46:18.378547
10234 23:46:18.927230 01000000 ################################################################
10235 23:46:18.927386
10236 23:46:19.500042 01080000 ################################################################
10237 23:46:19.500250
10238 23:46:20.063462 01100000 ################################################################
10239 23:46:20.063609
10240 23:46:20.591038 01180000 ################################################################
10241 23:46:20.591183
10242 23:46:21.143249 01200000 ################################################################
10243 23:46:21.143399
10244 23:46:21.687805 01280000 ################################################################
10245 23:46:21.687952
10246 23:46:22.243309 01300000 ################################################################
10247 23:46:22.243456
10248 23:46:22.794477 01380000 ################################################################
10249 23:46:22.794635
10250 23:46:23.346741 01400000 ################################################################
10251 23:46:23.346887
10252 23:46:23.911344 01480000 ################################################################
10253 23:46:23.911497
10254 23:46:24.471472 01500000 ################################################################
10255 23:46:24.471606
10256 23:46:25.026622 01580000 ################################################################
10257 23:46:25.026773
10258 23:46:25.583255 01600000 ################################################################
10259 23:46:25.583397
10260 23:46:26.135719 01680000 ################################################################
10261 23:46:26.135867
10262 23:46:26.681241 01700000 ################################################################
10263 23:46:26.681384
10264 23:46:27.239120 01780000 ################################################################
10265 23:46:27.239260
10266 23:46:27.805264 01800000 ################################################################
10267 23:46:27.805433
10268 23:46:28.384066 01880000 ################################################################
10269 23:46:28.384212
10270 23:46:28.914807 01900000 ################################################################
10271 23:46:28.914957
10272 23:46:29.438907 01980000 ################################################################
10273 23:46:29.439057
10274 23:46:29.973795 01a00000 ################################################################
10275 23:46:29.973943
10276 23:46:30.510981 01a80000 ################################################################
10277 23:46:30.511132
10278 23:46:31.079518 01b00000 ################################################################
10279 23:46:31.079672
10280 23:46:31.659666 01b80000 ################################################################
10281 23:46:31.659816
10282 23:46:32.197839 01c00000 ################################################################
10283 23:46:32.197994
10284 23:46:32.745583 01c80000 ################################################################
10285 23:46:32.745738
10286 23:46:33.272227 01d00000 ################################################################
10287 23:46:33.272400
10288 23:46:33.816383 01d80000 ################################################################
10289 23:46:33.816539
10290 23:46:34.237680 01e00000 ################################################ done.
10291 23:46:34.237825
10292 23:46:34.241207 The bootfile was 31845910 bytes long.
10293 23:46:34.241303
10294 23:46:34.244066 Sending tftp read request... done.
10295 23:46:34.244152
10296 23:46:34.244217 Waiting for the transfer...
10297 23:46:34.244277
10298 23:46:34.247452 00000000 # done.
10299 23:46:34.247579
10300 23:46:34.254061 Command line loaded dynamically from TFTP file: 14172980/tftp-deploy-2o3salbj/kernel/cmdline
10301 23:46:34.254233
10302 23:46:34.276963 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14172980/extract-nfsrootfs-vz806a3u,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10303 23:46:34.277117
10304 23:46:34.277185 Loading FIT.
10305 23:46:34.280110
10306 23:46:34.280194 Image ramdisk-1 has 18735187 bytes.
10307 23:46:34.283530
10308 23:46:34.283616 Image fdt-1 has 47258 bytes.
10309 23:46:34.283681
10310 23:46:34.287072 Image kernel-1 has 13061430 bytes.
10311 23:46:34.287158
10312 23:46:34.296591 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10313 23:46:34.296712
10314 23:46:34.313016 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10315 23:46:34.313168
10316 23:46:34.319857 Choosing best match conf-1 for compat google,spherion-rev2.
10317 23:46:34.323505
10318 23:46:34.327472 Connected to device vid:did:rid of 1ae0:0028:00
10319 23:46:34.335086
10320 23:46:34.338057 tpm_get_response: command 0x17b, return code 0x0
10321 23:46:34.338213
10322 23:46:34.341576 ec_init: CrosEC protocol v3 supported (256, 248)
10323 23:46:34.345472
10324 23:46:34.349321 tpm_cleanup: add release locality here.
10325 23:46:34.349416
10326 23:46:34.349482 Shutting down all USB controllers.
10327 23:46:34.352141
10328 23:46:34.352225 Removing current net device
10329 23:46:34.352291
10330 23:46:34.358913 Exiting depthcharge with code 4 at timestamp: 80511491
10331 23:46:34.359016
10332 23:46:34.362329 LZMA decompressing kernel-1 to 0x821a6718
10333 23:46:34.362415
10334 23:46:34.365021 LZMA decompressing kernel-1 to 0x40000000
10335 23:46:35.974840
10336 23:46:35.974990 jumping to kernel
10337 23:46:35.975544 end: 2.2.4 bootloader-commands (duration 00:00:53) [common]
10338 23:46:35.975645 start: 2.2.5 auto-login-action (timeout 00:03:34) [common]
10339 23:46:35.975721 Setting prompt string to ['Linux version [0-9]']
10340 23:46:35.975788 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10341 23:46:35.975893 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10342 23:46:36.058115
10343 23:46:36.061209 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10344 23:46:36.064779 start: 2.2.5.1 login-action (timeout 00:03:34) [common]
10345 23:46:36.064893 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10346 23:46:36.064968 Setting prompt string to []
10347 23:46:36.065043 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10348 23:46:36.065117 Using line separator: #'\n'#
10349 23:46:36.065176 No login prompt set.
10350 23:46:36.065236 Parsing kernel messages
10351 23:46:36.065291 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10352 23:46:36.065391 [login-action] Waiting for messages, (timeout 00:03:34)
10353 23:46:36.065456 Waiting using forced prompt support (timeout 00:01:47)
10354 23:46:36.084603 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j217067-arm64-gcc-10-defconfig-arm64-chromebook-s48tj) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 4 23:28:43 UTC 2024
10355 23:46:36.087869 [ 0.000000] random: crng init done
10356 23:46:36.094114 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10357 23:46:36.097658 [ 0.000000] efi: UEFI not found.
10358 23:46:36.104749 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10359 23:46:36.111111 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10360 23:46:36.121352 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10361 23:46:36.130680 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10362 23:46:36.137132 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10363 23:46:36.144242 [ 0.000000] printk: bootconsole [mtk8250] enabled
10364 23:46:36.150608 [ 0.000000] NUMA: No NUMA configuration found
10365 23:46:36.157064 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10366 23:46:36.160650 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10367 23:46:36.163521 [ 0.000000] Zone ranges:
10368 23:46:36.170065 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10369 23:46:36.173175 [ 0.000000] DMA32 empty
10370 23:46:36.179918 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10371 23:46:36.183325 [ 0.000000] Movable zone start for each node
10372 23:46:36.187194 [ 0.000000] Early memory node ranges
10373 23:46:36.193408 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10374 23:46:36.199836 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10375 23:46:36.206685 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10376 23:46:36.213002 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10377 23:46:36.219697 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10378 23:46:36.226467 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10379 23:46:36.281706 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10380 23:46:36.288646 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10381 23:46:36.295029 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10382 23:46:36.298441 [ 0.000000] psci: probing for conduit method from DT.
10383 23:46:36.305417 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10384 23:46:36.308502 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10385 23:46:36.315176 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10386 23:46:36.318091 [ 0.000000] psci: SMC Calling Convention v1.2
10387 23:46:36.324764 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10388 23:46:36.328189 [ 0.000000] Detected VIPT I-cache on CPU0
10389 23:46:36.334797 [ 0.000000] CPU features: detected: GIC system register CPU interface
10390 23:46:36.341379 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10391 23:46:36.348221 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10392 23:46:36.354912 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10393 23:46:36.364803 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10394 23:46:36.371182 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10395 23:46:36.374123 [ 0.000000] alternatives: applying boot alternatives
10396 23:46:36.381037 [ 0.000000] Fallback order for Node 0: 0
10397 23:46:36.387591 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10398 23:46:36.390966 [ 0.000000] Policy zone: Normal
10399 23:46:36.413752 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14172980/extract-nfsrootfs-vz806a3u,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10400 23:46:36.423846 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10401 23:46:36.435125 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10402 23:46:36.444709 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10403 23:46:36.451557 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10404 23:46:36.454762 <6>[ 0.000000] software IO TLB: area num 8.
10405 23:46:36.511564 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10406 23:46:36.660391 <6>[ 0.000000] Memory: 7945888K/8385536K available (18112K kernel code, 4120K rwdata, 22504K rodata, 8512K init, 616K bss, 406880K reserved, 32768K cma-reserved)
10407 23:46:36.667005 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10408 23:46:36.673923 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10409 23:46:36.676973 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10410 23:46:36.683500 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10411 23:46:36.690281 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10412 23:46:36.693807 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10413 23:46:36.703536 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10414 23:46:36.709897 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10415 23:46:36.716785 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10416 23:46:36.723384 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10417 23:46:36.726639 <6>[ 0.000000] GICv3: 608 SPIs implemented
10418 23:46:36.729879 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10419 23:46:36.736430 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10420 23:46:36.739703 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10421 23:46:36.746827 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10422 23:46:36.759451 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10423 23:46:36.772715 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10424 23:46:36.779433 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10425 23:46:36.787522 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10426 23:46:36.800714 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10427 23:46:36.807207 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10428 23:46:36.813927 <6>[ 0.009183] Console: colour dummy device 80x25
10429 23:46:36.823765 <6>[ 0.013913] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10430 23:46:36.830017 <6>[ 0.024355] pid_max: default: 32768 minimum: 301
10431 23:46:36.833208 <6>[ 0.029226] LSM: Security Framework initializing
10432 23:46:36.840085 <6>[ 0.034162] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10433 23:46:36.849848 <6>[ 0.041975] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10434 23:46:36.859861 <6>[ 0.051395] cblist_init_generic: Setting adjustable number of callback queues.
10435 23:46:36.862898 <6>[ 0.058840] cblist_init_generic: Setting shift to 3 and lim to 1.
10436 23:46:36.873547 <6>[ 0.065178] cblist_init_generic: Setting adjustable number of callback queues.
10437 23:46:36.880015 <6>[ 0.072605] cblist_init_generic: Setting shift to 3 and lim to 1.
10438 23:46:36.882816 <6>[ 0.079005] rcu: Hierarchical SRCU implementation.
10439 23:46:36.889417 <6>[ 0.084020] rcu: Max phase no-delay instances is 1000.
10440 23:46:36.896047 <6>[ 0.091090] EFI services will not be available.
10441 23:46:36.899316 <6>[ 0.096046] smp: Bringing up secondary CPUs ...
10442 23:46:36.907771 <6>[ 0.101092] Detected VIPT I-cache on CPU1
10443 23:46:36.914468 <6>[ 0.101165] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10444 23:46:36.921376 <6>[ 0.101198] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10445 23:46:36.925194 <6>[ 0.101540] Detected VIPT I-cache on CPU2
10446 23:46:36.934144 <6>[ 0.101598] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10447 23:46:36.940554 <6>[ 0.101617] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10448 23:46:36.944102 <6>[ 0.101877] Detected VIPT I-cache on CPU3
10449 23:46:36.950758 <6>[ 0.101923] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10450 23:46:36.957183 <6>[ 0.101938] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10451 23:46:36.964251 <6>[ 0.102241] CPU features: detected: Spectre-v4
10452 23:46:36.966870 <6>[ 0.102247] CPU features: detected: Spectre-BHB
10453 23:46:36.970527 <6>[ 0.102252] Detected PIPT I-cache on CPU4
10454 23:46:36.980207 <6>[ 0.102311] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10455 23:46:36.986859 <6>[ 0.102327] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10456 23:46:36.990089 <6>[ 0.102619] Detected PIPT I-cache on CPU5
10457 23:46:36.997051 <6>[ 0.102683] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10458 23:46:37.003173 <6>[ 0.102699] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10459 23:46:37.006626 <6>[ 0.102978] Detected PIPT I-cache on CPU6
10460 23:46:37.013176 <6>[ 0.103042] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10461 23:46:37.022970 <6>[ 0.103059] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10462 23:46:37.026740 <6>[ 0.103356] Detected PIPT I-cache on CPU7
10463 23:46:37.033283 <6>[ 0.103421] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10464 23:46:37.039505 <6>[ 0.103437] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10465 23:46:37.042990 <6>[ 0.103484] smp: Brought up 1 node, 8 CPUs
10466 23:46:37.049461 <6>[ 0.244780] SMP: Total of 8 processors activated.
10467 23:46:37.056121 <6>[ 0.249701] CPU features: detected: 32-bit EL0 Support
10468 23:46:37.062633 <6>[ 0.255063] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10469 23:46:37.069401 <6>[ 0.263863] CPU features: detected: Common not Private translations
10470 23:46:37.075677 <6>[ 0.270339] CPU features: detected: CRC32 instructions
10471 23:46:37.082443 <6>[ 0.275724] CPU features: detected: RCpc load-acquire (LDAPR)
10472 23:46:37.085794 <6>[ 0.281684] CPU features: detected: LSE atomic instructions
10473 23:46:37.092316 <6>[ 0.287466] CPU features: detected: Privileged Access Never
10474 23:46:37.098708 <6>[ 0.293245] CPU features: detected: RAS Extension Support
10475 23:46:37.105507 <6>[ 0.298889] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10476 23:46:37.108571 <6>[ 0.306109] CPU: All CPU(s) started at EL2
10477 23:46:37.115159 <6>[ 0.310452] alternatives: applying system-wide alternatives
10478 23:46:37.125524 <6>[ 0.321300] devtmpfs: initialized
10479 23:46:37.141314 <6>[ 0.330244] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10480 23:46:37.148066 <6>[ 0.340203] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10481 23:46:37.155048 <6>[ 0.348224] pinctrl core: initialized pinctrl subsystem
10482 23:46:37.157780 <6>[ 0.354908] DMI not present or invalid.
10483 23:46:37.164123 <6>[ 0.359319] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10484 23:46:37.174394 <6>[ 0.366139] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10485 23:46:37.180573 <6>[ 0.373725] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10486 23:46:37.190611 <6>[ 0.381941] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10487 23:46:37.193678 <6>[ 0.390186] audit: initializing netlink subsys (disabled)
10488 23:46:37.203721 <5>[ 0.395881] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10489 23:46:37.210500 <6>[ 0.396602] thermal_sys: Registered thermal governor 'step_wise'
10490 23:46:37.216987 <6>[ 0.403846] thermal_sys: Registered thermal governor 'power_allocator'
10491 23:46:37.220756 <6>[ 0.410104] cpuidle: using governor menu
10492 23:46:37.226888 <6>[ 0.421060] NET: Registered PF_QIPCRTR protocol family
10493 23:46:37.233855 <6>[ 0.426545] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10494 23:46:37.240060 <6>[ 0.433650] ASID allocator initialised with 32768 entries
10495 23:46:37.243201 <6>[ 0.440256] Serial: AMBA PL011 UART driver
10496 23:46:37.253499 <4>[ 0.449121] Trying to register duplicate clock ID: 134
10497 23:46:37.313253 <6>[ 0.512153] KASLR enabled
10498 23:46:37.327660 <6>[ 0.519916] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10499 23:46:37.334359 <6>[ 0.526930] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10500 23:46:37.340962 <6>[ 0.533420] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10501 23:46:37.347291 <6>[ 0.540423] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10502 23:46:37.353834 <6>[ 0.546910] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10503 23:46:37.360941 <6>[ 0.553916] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10504 23:46:37.366923 <6>[ 0.560403] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10505 23:46:37.373871 <6>[ 0.567404] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10506 23:46:37.376743 <6>[ 0.574921] ACPI: Interpreter disabled.
10507 23:46:37.385959 <6>[ 0.581365] iommu: Default domain type: Translated
10508 23:46:37.392411 <6>[ 0.586476] iommu: DMA domain TLB invalidation policy: strict mode
10509 23:46:37.395746 <5>[ 0.593137] SCSI subsystem initialized
10510 23:46:37.402389 <6>[ 0.597309] usbcore: registered new interface driver usbfs
10511 23:46:37.409033 <6>[ 0.603042] usbcore: registered new interface driver hub
10512 23:46:37.411935 <6>[ 0.608595] usbcore: registered new device driver usb
10513 23:46:37.418951 <6>[ 0.614699] pps_core: LinuxPPS API ver. 1 registered
10514 23:46:37.429270 <6>[ 0.619892] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10515 23:46:37.432443 <6>[ 0.629239] PTP clock support registered
10516 23:46:37.435515 <6>[ 0.633474] EDAC MC: Ver: 3.0.0
10517 23:46:37.443266 <6>[ 0.638648] FPGA manager framework
10518 23:46:37.449547 <6>[ 0.642332] Advanced Linux Sound Architecture Driver Initialized.
10519 23:46:37.453023 <6>[ 0.649109] vgaarb: loaded
10520 23:46:37.459786 <6>[ 0.652279] clocksource: Switched to clocksource arch_sys_counter
10521 23:46:37.462854 <5>[ 0.658724] VFS: Disk quotas dquot_6.6.0
10522 23:46:37.469332 <6>[ 0.662908] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10523 23:46:37.472321 <6>[ 0.670097] pnp: PnP ACPI: disabled
10524 23:46:37.481136 <6>[ 0.676831] NET: Registered PF_INET protocol family
10525 23:46:37.491247 <6>[ 0.682437] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10526 23:46:37.502752 <6>[ 0.694797] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10527 23:46:37.512580 <6>[ 0.703611] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10528 23:46:37.519274 <6>[ 0.711584] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10529 23:46:37.525747 <6>[ 0.720290] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10530 23:46:37.537891 <6>[ 0.730034] TCP: Hash tables configured (established 65536 bind 65536)
10531 23:46:37.544246 <6>[ 0.736898] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10532 23:46:37.550804 <6>[ 0.744094] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10533 23:46:37.557901 <6>[ 0.751804] NET: Registered PF_UNIX/PF_LOCAL protocol family
10534 23:46:37.564236 <6>[ 0.757951] RPC: Registered named UNIX socket transport module.
10535 23:46:37.567214 <6>[ 0.764106] RPC: Registered udp transport module.
10536 23:46:37.573729 <6>[ 0.769038] RPC: Registered tcp transport module.
10537 23:46:37.580553 <6>[ 0.773969] RPC: Registered tcp NFSv4.1 backchannel transport module.
10538 23:46:37.583874 <6>[ 0.780634] PCI: CLS 0 bytes, default 64
10539 23:46:37.587303 <6>[ 0.784929] Unpacking initramfs...
10540 23:46:37.596636 <6>[ 0.788955] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10541 23:46:37.606633 <6>[ 0.797571] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10542 23:46:37.610348 <6>[ 0.806370] kvm [1]: IPA Size Limit: 40 bits
10543 23:46:37.616512 <6>[ 0.810898] kvm [1]: GICv3: no GICV resource entry
10544 23:46:37.620222 <6>[ 0.815920] kvm [1]: disabling GICv2 emulation
10545 23:46:37.626426 <6>[ 0.820607] kvm [1]: GIC system register CPU interface enabled
10546 23:46:37.629732 <6>[ 0.826767] kvm [1]: vgic interrupt IRQ18
10547 23:46:37.636240 <6>[ 0.831122] kvm [1]: VHE mode initialized successfully
10548 23:46:37.643062 <5>[ 0.837502] Initialise system trusted keyrings
10549 23:46:37.649282 <6>[ 0.842297] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10550 23:46:37.656840 <6>[ 0.852509] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10551 23:46:37.663890 <5>[ 0.858930] NFS: Registering the id_resolver key type
10552 23:46:37.667113 <5>[ 0.864229] Key type id_resolver registered
10553 23:46:37.673350 <5>[ 0.868644] Key type id_legacy registered
10554 23:46:37.680096 <6>[ 0.872937] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10555 23:46:37.686546 <6>[ 0.879855] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10556 23:46:37.693373 <6>[ 0.887580] 9p: Installing v9fs 9p2000 file system support
10557 23:46:37.728741 <5>[ 0.924472] Key type asymmetric registered
10558 23:46:37.732173 <5>[ 0.928804] Asymmetric key parser 'x509' registered
10559 23:46:37.742315 <6>[ 0.933947] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10560 23:46:37.745545 <6>[ 0.941558] io scheduler mq-deadline registered
10561 23:46:37.748234 <6>[ 0.946319] io scheduler kyber registered
10562 23:46:37.768270 <6>[ 0.963500] EINJ: ACPI disabled.
10563 23:46:37.801177 <4>[ 0.990233] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10564 23:46:37.810846 <4>[ 1.000885] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10565 23:46:37.826434 <6>[ 1.022215] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10566 23:46:37.834778 <6>[ 1.030439] printk: console [ttyS0] disabled
10567 23:46:37.862806 <6>[ 1.055071] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10568 23:46:37.869552 <6>[ 1.064550] printk: console [ttyS0] enabled
10569 23:46:37.872764 <6>[ 1.064550] printk: console [ttyS0] enabled
10570 23:46:37.879271 <6>[ 1.073445] printk: bootconsole [mtk8250] disabled
10571 23:46:37.882759 <6>[ 1.073445] printk: bootconsole [mtk8250] disabled
10572 23:46:37.889205 <6>[ 1.084766] SuperH (H)SCI(F) driver initialized
10573 23:46:37.892496 <6>[ 1.090055] msm_serial: driver initialized
10574 23:46:37.906774 <6>[ 1.099067] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10575 23:46:37.916544 <6>[ 1.107619] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10576 23:46:37.922833 <6>[ 1.116162] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10577 23:46:37.932907 <6>[ 1.124791] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10578 23:46:37.942950 <6>[ 1.133503] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10579 23:46:37.949069 <6>[ 1.142218] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10580 23:46:37.959090 <6>[ 1.150766] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10581 23:46:37.968782 <6>[ 1.159574] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10582 23:46:37.975299 <6>[ 1.168118] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10583 23:46:37.988084 <6>[ 1.183915] loop: module loaded
10584 23:46:37.994718 <6>[ 1.189913] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10585 23:46:38.017776 <4>[ 1.213523] mtk-pmic-keys: Failed to locate of_node [id: -1]
10586 23:46:38.024801 <6>[ 1.220478] megasas: 07.719.03.00-rc1
10587 23:46:38.034560 <6>[ 1.230372] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10588 23:46:38.044272 <6>[ 1.239666] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10589 23:46:38.060694 <6>[ 1.256210] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10590 23:46:38.120850 <6>[ 1.309779] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10591 23:46:38.423279 <6>[ 1.619036] Freeing initrd memory: 18292K
10592 23:46:38.434788 <6>[ 1.630627] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10593 23:46:38.445990 <6>[ 1.641730] tun: Universal TUN/TAP device driver, 1.6
10594 23:46:38.449272 <6>[ 1.647807] thunder_xcv, ver 1.0
10595 23:46:38.452457 <6>[ 1.651314] thunder_bgx, ver 1.0
10596 23:46:38.456047 <6>[ 1.654810] nicpf, ver 1.0
10597 23:46:38.466361 <6>[ 1.658841] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10598 23:46:38.470042 <6>[ 1.666318] hns3: Copyright (c) 2017 Huawei Corporation.
10599 23:46:38.476449 <6>[ 1.671924] hclge is initializing
10600 23:46:38.479766 <6>[ 1.675505] e1000: Intel(R) PRO/1000 Network Driver
10601 23:46:38.486147 <6>[ 1.680634] e1000: Copyright (c) 1999-2006 Intel Corporation.
10602 23:46:38.489828 <6>[ 1.686649] e1000e: Intel(R) PRO/1000 Network Driver
10603 23:46:38.496367 <6>[ 1.691864] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10604 23:46:38.502922 <6>[ 1.698051] igb: Intel(R) Gigabit Ethernet Network Driver
10605 23:46:38.509619 <6>[ 1.703701] igb: Copyright (c) 2007-2014 Intel Corporation.
10606 23:46:38.516190 <6>[ 1.709537] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10607 23:46:38.522832 <6>[ 1.716055] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10608 23:46:38.526135 <6>[ 1.722521] sky2: driver version 1.30
10609 23:46:38.532528 <6>[ 1.727456] usbcore: registered new device driver r8152-cfgselector
10610 23:46:38.539043 <6>[ 1.733992] usbcore: registered new interface driver r8152
10611 23:46:38.545707 <6>[ 1.739813] VFIO - User Level meta-driver version: 0.3
10612 23:46:38.552701 <6>[ 1.748061] usbcore: registered new interface driver usb-storage
10613 23:46:38.558804 <6>[ 1.754509] usbcore: registered new device driver onboard-usb-hub
10614 23:46:38.568298 <6>[ 1.763682] mt6397-rtc mt6359-rtc: registered as rtc0
10615 23:46:38.577718 <6>[ 1.769144] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-04T23:46:38 UTC (1717544798)
10616 23:46:38.581053 <6>[ 1.778712] i2c_dev: i2c /dev entries driver
10617 23:46:38.598330 <6>[ 1.790533] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10618 23:46:38.604810 <4>[ 1.799260] cpu cpu0: supply cpu not found, using dummy regulator
10619 23:46:38.611462 <4>[ 1.805689] cpu cpu1: supply cpu not found, using dummy regulator
10620 23:46:38.618205 <4>[ 1.812097] cpu cpu2: supply cpu not found, using dummy regulator
10621 23:46:38.624835 <4>[ 1.818504] cpu cpu3: supply cpu not found, using dummy regulator
10622 23:46:38.631496 <4>[ 1.824904] cpu cpu4: supply cpu not found, using dummy regulator
10623 23:46:38.637623 <4>[ 1.831321] cpu cpu5: supply cpu not found, using dummy regulator
10624 23:46:38.644425 <4>[ 1.837717] cpu cpu6: supply cpu not found, using dummy regulator
10625 23:46:38.651058 <4>[ 1.844118] cpu cpu7: supply cpu not found, using dummy regulator
10626 23:46:38.669375 <6>[ 1.864752] cpu cpu0: EM: created perf domain
10627 23:46:38.672208 <6>[ 1.869692] cpu cpu4: EM: created perf domain
10628 23:46:38.679468 <6>[ 1.875339] sdhci: Secure Digital Host Controller Interface driver
10629 23:46:38.686134 <6>[ 1.881781] sdhci: Copyright(c) Pierre Ossman
10630 23:46:38.692734 <6>[ 1.886734] Synopsys Designware Multimedia Card Interface Driver
10631 23:46:38.699550 <6>[ 1.893382] sdhci-pltfm: SDHCI platform and OF driver helper
10632 23:46:38.702677 <6>[ 1.893436] mmc0: CQHCI version 5.10
10633 23:46:38.710051 <6>[ 1.903554] ledtrig-cpu: registered to indicate activity on CPUs
10634 23:46:38.716426 <6>[ 1.910732] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10635 23:46:38.722353 <6>[ 1.917785] usbcore: registered new interface driver usbhid
10636 23:46:38.725832 <6>[ 1.923608] usbhid: USB HID core driver
10637 23:46:38.735653 <6>[ 1.927818] spi_master spi0: will run message pump with realtime priority
10638 23:46:38.776024 <6>[ 1.965094] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10639 23:46:38.794413 <6>[ 1.980032] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10640 23:46:38.797638 <6>[ 1.993623] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x17414
10641 23:46:38.804636 <6>[ 2.000733] cros-ec-spi spi0.0: Chrome EC device registered
10642 23:46:38.811487 <6>[ 2.006733] mmc0: Command Queue Engine enabled
10643 23:46:38.818745 <6>[ 2.011467] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10644 23:46:38.821260 <6>[ 2.019077] mmcblk0: mmc0:0001 DA4128 116 GiB
10645 23:46:38.832808 <6>[ 2.028160] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10646 23:46:38.840362 <6>[ 2.035972] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10647 23:46:38.850106 <6>[ 2.039390] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10648 23:46:38.853359 <6>[ 2.041840] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10649 23:46:38.860091 <6>[ 2.051671] NET: Registered PF_PACKET protocol family
10650 23:46:38.866874 <6>[ 2.056380] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10651 23:46:38.870050 <6>[ 2.061095] 9pnet: Installing 9P2000 support
10652 23:46:38.877158 <5>[ 2.072107] Key type dns_resolver registered
10653 23:46:38.880500 <6>[ 2.077096] registered taskstats version 1
10654 23:46:38.887045 <5>[ 2.081476] Loading compiled-in X.509 certificates
10655 23:46:38.916213 <4>[ 2.105223] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10656 23:46:38.926133 <4>[ 2.115957] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10657 23:46:38.942513 <6>[ 2.138066] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10658 23:46:38.949306 <6>[ 2.144925] xhci-mtk 11200000.usb: xHCI Host Controller
10659 23:46:38.955988 <6>[ 2.150445] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10660 23:46:38.965819 <6>[ 2.158302] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10661 23:46:38.972738 <6>[ 2.167737] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10662 23:46:38.979126 <6>[ 2.173927] xhci-mtk 11200000.usb: xHCI Host Controller
10663 23:46:38.986087 <6>[ 2.179420] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10664 23:46:38.992332 <6>[ 2.187075] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10665 23:46:38.999165 <6>[ 2.194935] hub 1-0:1.0: USB hub found
10666 23:46:39.002509 <6>[ 2.198961] hub 1-0:1.0: 1 port detected
10667 23:46:39.012439 <6>[ 2.203268] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10668 23:46:39.016047 <6>[ 2.211997] hub 2-0:1.0: USB hub found
10669 23:46:39.019114 <6>[ 2.216018] hub 2-0:1.0: 1 port detected
10670 23:46:39.027449 <6>[ 2.223226] mtk-msdc 11f70000.mmc: Got CD GPIO
10671 23:46:39.045623 <6>[ 2.237778] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10672 23:46:39.052104 <6>[ 2.245900] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10673 23:46:39.061851 <4>[ 2.253840] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10674 23:46:39.071674 <6>[ 2.263430] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10675 23:46:39.078125 <6>[ 2.271515] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10676 23:46:39.087969 <6>[ 2.279555] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10677 23:46:39.094574 <6>[ 2.287470] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10678 23:46:39.101857 <6>[ 2.295306] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10679 23:46:39.110850 <6>[ 2.303127] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10680 23:46:39.121191 <6>[ 2.313599] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10681 23:46:39.130781 <6>[ 2.321964] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10682 23:46:39.137622 <6>[ 2.330332] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10683 23:46:39.147399 <6>[ 2.338672] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10684 23:46:39.154294 <6>[ 2.347020] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10685 23:46:39.163950 <6>[ 2.355362] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10686 23:46:39.170432 <6>[ 2.363712] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10687 23:46:39.180707 <6>[ 2.372052] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10688 23:46:39.186811 <6>[ 2.380400] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10689 23:46:39.197032 <6>[ 2.388739] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10690 23:46:39.203977 <6>[ 2.397077] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10691 23:46:39.213558 <6>[ 2.405414] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10692 23:46:39.220156 <6>[ 2.413752] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10693 23:46:39.230367 <6>[ 2.422090] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10694 23:46:39.236658 <6>[ 2.430428] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10695 23:46:39.243401 <6>[ 2.439216] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10696 23:46:39.250785 <6>[ 2.446411] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10697 23:46:39.257236 <6>[ 2.453189] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10698 23:46:39.267794 <6>[ 2.459960] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10699 23:46:39.274551 <6>[ 2.466882] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10700 23:46:39.280615 <6>[ 2.473738] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10701 23:46:39.290556 <6>[ 2.482869] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10702 23:46:39.300304 <6>[ 2.492009] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10703 23:46:39.310589 <6>[ 2.501310] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10704 23:46:39.320103 <6>[ 2.510779] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10705 23:46:39.330284 <6>[ 2.520244] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10706 23:46:39.336609 <6>[ 2.529364] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10707 23:46:39.346679 <6>[ 2.538830] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10708 23:46:39.356785 <6>[ 2.547949] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10709 23:46:39.366388 <6>[ 2.557243] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10710 23:46:39.376095 <6>[ 2.567403] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10711 23:46:39.386084 <6>[ 2.578904] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10712 23:46:39.393006 <6>[ 2.588676] Trying to probe devices needed for running init ...
10713 23:46:39.408049 <6>[ 2.600623] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10714 23:46:39.436416 <6>[ 2.632075] hub 2-1:1.0: USB hub found
10715 23:46:39.439542 <6>[ 2.636538] hub 2-1:1.0: 3 ports detected
10716 23:46:39.448421 <6>[ 2.643855] hub 2-1:1.0: USB hub found
10717 23:46:39.451246 <6>[ 2.648195] hub 2-1:1.0: 3 ports detected
10718 23:46:39.560159 <6>[ 2.752496] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10719 23:46:39.715032 <6>[ 2.910635] hub 1-1:1.0: USB hub found
10720 23:46:39.718367 <6>[ 2.915109] hub 1-1:1.0: 4 ports detected
10721 23:46:39.727042 <6>[ 2.922937] hub 1-1:1.0: USB hub found
10722 23:46:39.730727 <6>[ 2.927255] hub 1-1:1.0: 4 ports detected
10723 23:46:39.800072 <6>[ 2.992804] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10724 23:46:39.908526 <6>[ 3.101022] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10725 23:46:39.945467 <4>[ 3.137589] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10726 23:46:39.954858 <4>[ 3.146748] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10727 23:46:39.989990 <6>[ 3.185647] r8152 2-1.3:1.0 eth0: v1.12.13
10728 23:46:40.059824 <6>[ 3.252588] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10729 23:46:40.192495 <6>[ 3.388557] hub 1-1.4:1.0: USB hub found
10730 23:46:40.196199 <6>[ 3.393229] hub 1-1.4:1.0: 2 ports detected
10731 23:46:40.205656 <6>[ 3.401665] hub 1-1.4:1.0: USB hub found
10732 23:46:40.209007 <6>[ 3.406257] hub 1-1.4:1.0: 2 ports detected
10733 23:46:40.508000 <6>[ 3.700465] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10734 23:46:40.699409 <6>[ 3.892387] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10735 23:46:41.720874 <6>[ 4.916989] r8152 2-1.3:1.0 eth0: carrier on
10736 23:46:44.496264 <5>[ 4.948386] Sending DHCP requests .., OK
10737 23:46:44.503209 <6>[ 7.696667] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10738 23:46:44.506345 <6>[ 7.705011] IP-Config: Complete:
10739 23:46:44.519223 <6>[ 7.708509] device=eth0, hwaddr=00:e0:4c:68:02:81, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10740 23:46:44.526284 <6>[ 7.719221] host=mt8192-asurada-spherion-r0-cbg-9, domain=lava-rack, nis-domain=(none)
10741 23:46:44.535797 <6>[ 7.727840] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10742 23:46:44.539394 <6>[ 7.727849] nameserver0=192.168.201.1
10743 23:46:44.542844 <6>[ 7.740006] clk: Disabling unused clocks
10744 23:46:44.546056 <6>[ 7.745507] ALSA device list:
10745 23:46:44.553179 <6>[ 7.748773] No soundcards found.
10746 23:46:44.560296 <6>[ 7.756210] Freeing unused kernel memory: 8512K
10747 23:46:44.563320 <6>[ 7.761229] Run /init as init process
10748 23:46:44.573058 Loading, please wait...
10749 23:46:44.600388 Starting systemd-udevd version 252.22-1~deb12u1
10750 23:46:44.860818 <6>[ 8.052956] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10751 23:46:44.871030 <6>[ 8.053133] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10752 23:46:44.877494 <6>[ 8.065835] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10753 23:46:44.895911 <6>[ 8.091949] remoteproc remoteproc0: scp is available
10754 23:46:44.902798 <6>[ 8.093439] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10755 23:46:44.909280 <6>[ 8.098817] remoteproc remoteproc0: powering up scp
10756 23:46:44.918970 <6>[ 8.104902] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10757 23:46:44.926090 <4>[ 8.118832] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10758 23:46:44.932738 <4>[ 8.118832] Fallback method does not support PEC.
10759 23:46:44.938811 <6>[ 8.119108] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10760 23:46:44.948885 <4>[ 8.121096] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10761 23:46:44.955420 <4>[ 8.135392] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10762 23:46:44.958765 <6>[ 8.141187] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10763 23:46:44.969413 <3>[ 8.153558] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10764 23:46:44.972824 <6>[ 8.160037] mc: Linux media interface: v0.10
10765 23:46:44.979899 <3>[ 8.161482] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10766 23:46:44.989588 <3>[ 8.161525] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10767 23:46:44.999494 <3>[ 8.185034] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10768 23:46:45.006189 <3>[ 8.190992] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10769 23:46:45.013128 <6>[ 8.192189] videodev: Linux video capture interface: v2.00
10770 23:46:45.019991 <3>[ 8.213895] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10771 23:46:45.029297 <3>[ 8.222075] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10772 23:46:45.035953 <6>[ 8.227033] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10773 23:46:45.042754 <3>[ 8.230165] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10774 23:46:45.052370 <3>[ 8.230172] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10775 23:46:45.059180 <6>[ 8.237042] pci_bus 0000:00: root bus resource [bus 00-ff]
10776 23:46:45.065900 <3>[ 8.245111] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10777 23:46:45.075547 <3>[ 8.245141] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10778 23:46:45.082110 <6>[ 8.253193] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10779 23:46:45.088767 <3>[ 8.258953] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10780 23:46:45.098821 <6>[ 8.260586] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10781 23:46:45.108970 <6>[ 8.267007] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10782 23:46:45.115013 <3>[ 8.275080] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10783 23:46:45.125266 <3>[ 8.275083] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10784 23:46:45.131599 <3>[ 8.275108] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10785 23:46:45.142101 <6>[ 8.281559] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10786 23:46:45.145095 <6>[ 8.282261] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10787 23:46:45.154894 <6>[ 8.290308] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10788 23:46:45.161822 <3>[ 8.290821] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10789 23:46:45.171233 <3>[ 8.290832] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10790 23:46:45.178034 <3>[ 8.290841] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10791 23:46:45.188136 <3>[ 8.290848] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10792 23:46:45.194552 <3>[ 8.290881] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10793 23:46:45.204613 <6>[ 8.293082] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10794 23:46:45.214343 <6>[ 8.293548] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10795 23:46:45.221372 <6>[ 8.299878] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10796 23:46:45.230609 <6>[ 8.303631] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10797 23:46:45.237422 <6>[ 8.306717] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10798 23:46:45.244032 <6>[ 8.309997] remoteproc remoteproc0: remote processor scp is now up
10799 23:46:45.251199 <6>[ 8.318173] pci 0000:00:00.0: supports D1 D2
10800 23:46:45.254306 <6>[ 8.318475] Bluetooth: Core ver 2.22
10801 23:46:45.257003 <6>[ 8.318557] NET: Registered PF_BLUETOOTH protocol family
10802 23:46:45.263513 <6>[ 8.318559] Bluetooth: HCI device and connection manager initialized
10803 23:46:45.270374 <6>[ 8.318581] Bluetooth: HCI socket layer initialized
10804 23:46:45.276781 <6>[ 8.318587] Bluetooth: L2CAP socket layer initialized
10805 23:46:45.280799 <6>[ 8.318603] Bluetooth: SCO socket layer initialized
10806 23:46:45.286692 <6>[ 8.365811] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10807 23:46:45.293778 <6>[ 8.371861] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10808 23:46:45.300021 <6>[ 8.372773] usbcore: registered new interface driver btusb
10809 23:46:45.309824 <6>[ 8.373137] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10810 23:46:45.313100 <6>[ 8.373245] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10811 23:46:45.322911 <6>[ 8.373272] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10812 23:46:45.329965 <6>[ 8.373289] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10813 23:46:45.337051 <6>[ 8.373304] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10814 23:46:45.342989 <6>[ 8.373413] pci 0000:01:00.0: supports D1 D2
10815 23:46:45.349578 <6>[ 8.373414] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10816 23:46:45.359769 <4>[ 8.373613] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10817 23:46:45.366206 <3>[ 8.373622] Bluetooth: hci0: Failed to load firmware file (-2)
10818 23:46:45.369253 <3>[ 8.373624] Bluetooth: hci0: Failed to set up firmware (-2)
10819 23:46:45.382671 <4>[ 8.373629] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10820 23:46:45.389280 <6>[ 8.380360] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10821 23:46:45.399476 <6>[ 8.382077] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10822 23:46:45.406227 <6>[ 8.382164] usbcore: registered new interface driver uvcvideo
10823 23:46:45.412068 <6>[ 8.406741] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10824 23:46:45.422117 <6>[ 8.415272] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10825 23:46:45.428683 <6>[ 8.622262] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10826 23:46:45.438453 <6>[ 8.630264] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10827 23:46:45.445349 <6>[ 8.638266] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10828 23:46:45.452107 <6>[ 8.646266] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10829 23:46:45.458440 <6>[ 8.654266] pci 0000:00:00.0: PCI bridge to [bus 01]
10830 23:46:45.464959 <6>[ 8.659481] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10831 23:46:45.471826 <6>[ 8.667583] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10832 23:46:45.478483 <6>[ 8.674424] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10833 23:46:45.484904 <6>[ 8.681149] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10834 23:46:45.507134 <5>[ 8.700038] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10835 23:46:45.529203 <5>[ 8.721560] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10836 23:46:45.535361 <5>[ 8.729635] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10837 23:46:45.545231 <4>[ 8.738160] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10838 23:46:45.551627 <6>[ 8.747097] cfg80211: failed to load regulatory.db
10839 23:46:45.608234 <6>[ 8.800203] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10840 23:46:45.614140 <6>[ 8.807793] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10841 23:46:45.639372 <6>[ 8.834781] mt7921e 0000:01:00.0: ASIC revision: 79610010
10842 23:46:45.745356 <6>[ 8.938172] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10843 23:46:45.748824 <6>[ 8.938172]
10844 23:46:45.773587 Begin: Loading essential drivers ... done.
10845 23:46:45.776715 Begin: Running /scripts/init-premount ... done.
10846 23:46:45.782905 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10847 23:46:45.792914 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10848 23:46:45.795904 Device /sys/class/net/eth0 found
10849 23:46:45.796325 done.
10850 23:46:45.815981 Begin: Waiting up to 180 secs for any network device to become available ... done.
10851 23:46:45.860763 IP-Config: eth0 hardware address 00:e0:4c:68:02:81 mtu 1500 DHCP
10852 23:46:45.868039 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10853 23:46:45.874033 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10854 23:46:45.881227 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10855 23:46:45.887868 host : mt8192-asurada-spherion-r0-cbg-9
10856 23:46:45.894735 domain : lava-rack
10857 23:46:45.897339 rootserver: 192.168.201.1 rootpath:
10858 23:46:45.900480 filename :
10859 23:46:46.012566 <6>[ 9.205514] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10860 23:46:46.047276 done.
10861 23:46:46.055497 Begin: Running /scripts/nfs-bottom ... done.
10862 23:46:46.070702 Begin: Running /scripts/init-bottom ... done.
10863 23:46:47.456133 <6>[ 10.652629] NET: Registered PF_INET6 protocol family
10864 23:46:47.463663 <6>[ 10.659886] Segment Routing with IPv6
10865 23:46:47.467123 <6>[ 10.663889] In-situ OAM (IOAM) with IPv6
10866 23:46:47.650331 <30>[ 10.819794] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10867 23:46:47.656709 <30>[ 10.852940] systemd[1]: Detected architecture arm64.
10868 23:46:47.667820
10869 23:46:47.670880 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10870 23:46:47.671323
10871 23:46:47.694271 <30>[ 10.890794] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10872 23:46:48.947562 <30>[ 12.140789] systemd[1]: Queued start job for default target graphical.target.
10873 23:46:48.978642 <30>[ 12.171449] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10874 23:46:48.984798 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10875 23:46:49.005014 <30>[ 12.198052] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10876 23:46:49.015147 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10877 23:46:49.033043 <30>[ 12.226409] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10878 23:46:49.043558 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10879 23:46:49.061082 <30>[ 12.253917] systemd[1]: Created slice user.slice - User and Session Slice.
10880 23:46:49.067181 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10881 23:46:49.091751 <30>[ 12.281498] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10882 23:46:49.101602 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10883 23:46:49.123394 <30>[ 12.312843] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10884 23:46:49.129623 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10885 23:46:49.157407 <30>[ 12.340744] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10886 23:46:49.167284 <30>[ 12.360564] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10887 23:46:49.173870 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10888 23:46:49.192127 <30>[ 12.384835] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10889 23:46:49.201514 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10890 23:46:49.215568 <30>[ 12.408637] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10891 23:46:49.225321 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10892 23:46:49.240871 <30>[ 12.437044] systemd[1]: Reached target paths.target - Path Units.
10893 23:46:49.250780 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10894 23:46:49.268120 <30>[ 12.460914] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10895 23:46:49.274153 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10896 23:46:49.288733 <30>[ 12.484565] systemd[1]: Reached target slices.target - Slice Units.
10897 23:46:49.298340 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10898 23:46:49.312956 <30>[ 12.509066] systemd[1]: Reached target swap.target - Swaps.
10899 23:46:49.319582 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10900 23:46:49.339832 <30>[ 12.532993] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10901 23:46:49.349695 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10902 23:46:49.367666 <30>[ 12.561050] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10903 23:46:49.377883 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10904 23:46:49.399349 <30>[ 12.592332] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10905 23:46:49.409103 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10906 23:46:49.425861 <30>[ 12.618290] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10907 23:46:49.434899 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10908 23:46:49.451958 <30>[ 12.645251] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10909 23:46:49.458648 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10910 23:46:49.477554 <30>[ 12.670432] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10911 23:46:49.487620 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10912 23:46:49.508503 <30>[ 12.701414] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10913 23:46:49.518078 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10914 23:46:49.535983 <30>[ 12.729088] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10915 23:46:49.545983 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10916 23:46:49.595865 <30>[ 12.789095] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10917 23:46:49.602241 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10918 23:46:49.614435 <30>[ 12.807922] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10919 23:46:49.621148 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10920 23:46:49.642933 <30>[ 12.836215] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10921 23:46:49.649534 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10922 23:46:49.673736 <30>[ 12.860805] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10923 23:46:49.687900 <30>[ 12.881458] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10924 23:46:49.697958 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10925 23:46:49.751965 <30>[ 12.945331] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10926 23:46:49.758775 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10927 23:46:49.784787 <30>[ 12.978247] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10928 23:46:49.794975 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10929 23:46:49.816930 <30>[ 13.010173] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10930 23:46:49.823365 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10931 23:46:49.833321 <6>[ 13.026266] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10932 23:46:49.849874 <30>[ 13.042768] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10933 23:46:49.859171 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10934 23:46:49.900433 <30>[ 13.093371] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10935 23:46:49.907047 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10936 23:46:49.933242 <30>[ 13.126680] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10937 23:46:49.940108 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10938 23:46:49.943059 <6>[ 13.142214] fuse: init (API version 7.37)
10939 23:46:49.965683 <30>[ 13.159005] systemd[1]: Starting systemd-journald.service - Journal Service...
10940 23:46:49.972620 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10941 23:46:50.048402 <30>[ 13.241587] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10942 23:46:50.054752 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10943 23:46:50.081757 <30>[ 13.271914] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10944 23:46:50.088326 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10945 23:46:50.119526 <30>[ 13.312645] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10946 23:46:50.132754 Startin<3>[ 13.323631] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10947 23:46:50.135692 g [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10948 23:46:50.161327 <3>[ 13.354169] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10949 23:46:50.192053 <30>[ 13.385220] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10950 23:46:50.198368 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10951 23:46:50.220836 <3>[ 13.413770] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10952 23:46:50.238643 <30>[ 13.431676] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10953 23:46:50.245316 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10954 23:46:50.254890 <3>[ 13.447975] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10955 23:46:50.265203 <30>[ 13.457741] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10956 23:46:50.271773 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10957 23:46:50.283993 <3>[ 13.477615] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10958 23:46:50.293958 <30>[ 13.487332] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10959 23:46:50.300999 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10960 23:46:50.314698 <3>[ 13.508143] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10961 23:46:50.325320 <30>[ 13.518384] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10962 23:46:50.334758 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10963 23:46:50.353081 <30>[ 13.546002] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10964 23:46:50.359808 <3>[ 13.553514] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10965 23:46:50.369796 <30>[ 13.554337] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10966 23:46:50.376419 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10967 23:46:50.390389 <3>[ 13.583719] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10968 23:46:50.400626 <30>[ 13.593581] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10969 23:46:50.406921 <30>[ 13.601260] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10970 23:46:50.421459 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m <3>[ 13.613690] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10971 23:46:50.423922 - Load Kernel Module dm_mod.
10972 23:46:50.442089 <30>[ 13.637914] systemd[1]: modprobe@drm.service: Deactivated successfully.
10973 23:46:50.452563 <30>[ 13.645408] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10974 23:46:50.459015 <3>[ 13.645814] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10975 23:46:50.468512 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10976 23:46:50.489522 <30>[ 13.682518] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10977 23:46:50.499814 <30>[ 13.690714] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10978 23:46:50.506103 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10979 23:46:50.524348 <30>[ 13.717211] systemd[1]: Started systemd-journald.service - Journal Service.
10980 23:46:50.530774 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10981 23:46:50.552055 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10982 23:46:50.570590 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10983 23:46:50.590117 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10984 23:46:50.610250 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10985 23:46:50.626829 <4>[ 13.811117] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10986 23:46:50.632877 <3>[ 13.826778] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10987 23:46:50.643104 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10988 23:46:50.662272 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10989 23:46:50.682549 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10990 23:46:50.732096 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10991 23:46:50.755280 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10992 23:46:50.782714 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10993 23:46:50.806558 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10994 23:46:50.851191 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables..<46>[ 14.044449] systemd-journald[312]: Received client request to flush runtime journal.
10995 23:46:50.851787 .
10996 23:46:50.937121 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10997 23:46:51.188324 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10998 23:46:51.207464 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10999 23:46:51.228730 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
11000 23:46:51.638969 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
11001 23:46:52.288770 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
11002 23:46:52.316166 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
11003 23:46:52.368720 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
11004 23:46:52.483180 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
11005 23:46:52.499799 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
11006 23:46:52.519263 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
11007 23:46:52.567856 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
11008 23:46:52.590701 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
11009 23:46:52.831942 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11010 23:46:52.908574 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11011 23:46:52.968369 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11012 23:46:53.275485 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11013 23:46:53.283931 <6>[ 16.481464] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11014 23:46:53.318357 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11015 23:46:53.344856 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11016 23:46:53.443139 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11017 23:46:53.459281 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11018 23:46:53.526201 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11019 23:46:53.551043 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11020 23:46:53.572196 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11021 23:46:53.596310 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11022 23:46:53.662039 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11023 23:46:53.709087 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11024 23:46:53.735841 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11025 23:46:53.770647 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11026 23:46:53.800430 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11027 23:46:53.823633 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11028 23:46:53.833755 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11029 23:46:53.850969 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11030 23:46:53.876414 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11031 23:46:53.903445 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11032 23:46:53.919066 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11033 23:46:53.939439 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11034 23:46:53.959260 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11035 23:46:53.974887 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11036 23:46:53.993632 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11037 23:46:54.010920 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11038 23:46:54.017826 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11039 23:46:54.077173 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11040 23:46:54.111011 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11041 23:46:54.206602 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11042 23:46:54.232553 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11043 23:46:54.308468 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11044 23:46:54.365585 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11045 23:46:54.386927 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11046 23:46:54.412032 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11047 23:46:54.504983 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11048 23:46:54.544040 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11049 23:46:54.589964 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11050 23:46:54.613360 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11051 23:46:54.631317 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11052 23:46:54.696298 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11053 23:46:54.770283 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11054 23:46:54.876029
11055 23:46:54.879049 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11056 23:46:54.879538
11057 23:46:54.882190 debian-bookworm-arm64 login: root (automatic login)
11058 23:46:54.882679
11059 23:46:55.168292 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Tue Jun 4 23:28:43 UTC 2024 aarch64
11060 23:46:55.168801
11061 23:46:55.174853 The programs included with the Debian GNU/Linux system are free software;
11062 23:46:55.181437 the exact distribution terms for each program are described in the
11063 23:46:55.184988 individual files in /usr/share/doc/*/copyright.
11064 23:46:55.185428
11065 23:46:55.191936 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11066 23:46:55.194967 permitted by applicable law.
11067 23:46:55.315335 Matched prompt #10: / #
11069 23:46:55.316579 Setting prompt string to ['/ #']
11070 23:46:55.317115 end: 2.2.5.1 login-action (duration 00:00:19) [common]
11072 23:46:55.318296 end: 2.2.5 auto-login-action (duration 00:00:19) [common]
11073 23:46:55.318835 start: 2.2.6 expect-shell-connection (timeout 00:03:14) [common]
11074 23:46:55.319236 Setting prompt string to ['/ #']
11075 23:46:55.319631 Forcing a shell prompt, looking for ['/ #']
11077 23:46:55.370726 / #
11078 23:46:55.371403 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11079 23:46:55.371948 Waiting using forced prompt support (timeout 00:02:30)
11080 23:46:55.377727
11081 23:46:55.378619 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11082 23:46:55.379243 start: 2.2.7 export-device-env (timeout 00:03:14) [common]
11084 23:46:55.480575 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14172980/extract-nfsrootfs-vz806a3u'
11085 23:46:55.487000 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14172980/extract-nfsrootfs-vz806a3u'
11087 23:46:55.588781 / # export NFS_SERVER_IP='192.168.201.1'
11088 23:46:55.595814 export NFS_SERVER_IP='192.168.201.1'
11089 23:46:55.596772 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11090 23:46:55.597285 end: 2.2 depthcharge-retry (duration 00:01:46) [common]
11091 23:46:55.597839 end: 2 depthcharge-action (duration 00:01:46) [common]
11092 23:46:55.598397 start: 3 lava-test-retry (timeout 00:30:00) [common]
11093 23:46:55.598893 start: 3.1 lava-test-shell (timeout 00:30:00) [common]
11094 23:46:55.599317 Using namespace: common
11096 23:46:55.700479 / # #
11097 23:46:55.701136 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:30:00)
11098 23:46:55.706807 #
11099 23:46:55.707566 Using /lava-14172980
11101 23:46:55.808819 / # export SHELL=/bin/sh
11102 23:46:55.815588 export SHELL=/bin/sh
11104 23:46:55.917283 / # . /lava-14172980/environment
11105 23:46:55.923487 . /lava-14172980/environment
11107 23:46:56.032365 / # /lava-14172980/bin/lava-test-runner /lava-14172980/0
11108 23:46:56.033016 Test shell timeout: 10s (minimum of the action and connection timeout)
11109 23:46:56.038577 /lava-14172980/bin/lava-test-runner /lava-14172980/0
11110 23:46:56.309893 + export TESTRUN_ID=0_lc-compliance
11111 23:46:56.315865 + cd /lava-14172980/0/tests/0_lc-compliance
11112 23:46:56.316300 + cat uuid
11113 23:46:56.328378 + UUID=14172980_1.6.2.3.1
11114 23:46:56.328902 + set +x
11115 23:46:56.334588 <LAVA_SIGNAL_STARTRUN 0_lc-compliance 14172980_1.6.2.3.1>
11116 23:46:56.335292 Received signal: <STARTRUN> 0_lc-compliance 14172980_1.6.2.3.1
11117 23:46:56.335659 Starting test lava.0_lc-compliance (14172980_1.6.2.3.1)
11118 23:46:56.336061 Skipping test definition patterns.
11119 23:46:56.337935 + /usr/bin/lc-compliance-parser.sh
11120 23:46:58.005295 [0:00:21.105228803] [417] [1;32m INFO [1;37mCamera [1;34mcamera_manager.cpp:284 [0mlibcamera v0.0.0+1-01935edb
11121 23:46:58.008656 Using camera /base/soc/usb@11200000-1.4.1:1.0-04f2:b741
11122 23:46:58.023292 [0:00:21.123780133] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11123 23:46:58.078273 [0:00:21.178516494] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11124 23:46:58.103591 [==========] Running 120 tests from 1 test suite.
11125 23:46:58.131800 [0:00:21.232307712] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11126 23:46:58.185647 [0:00:21.286882958] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11127 23:46:58.200273 [----------] Global test environment set-up.
11128 23:46:58.292248 [----------] 120 tests from CaptureTests/SingleStream
11129 23:46:58.382316 [ RUN ] CaptureTests/SingleStream.Capture/Raw_1
11130 23:46:58.459900 <LAVA_SIGNAL_TESTSET START CaptureTests/SingleStream>
11131 23:46:58.460782 Received signal: <TESTSET> START CaptureTests/SingleStream
11132 23:46:58.461209 Starting test_set CaptureTests/SingleStream
11133 23:46:58.463652 Camera needs 4 requests, can't test only 1
11134 23:46:58.556414 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11135 23:46:58.612138 [0:00:21.715034405] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11136 23:46:58.648009
11137 23:46:58.750847 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_1 (55 ms)
11138 23:46:58.870522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_1 RESULT=skip>
11139 23:46:58.871284 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_1 RESULT=skip
11141 23:46:58.906254 [ RUN ] CaptureTests/SingleStream.Capture/Raw_2
11142 23:46:58.965324 Camera needs 4 requests, can't test only 2
11143 23:46:59.054740 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11144 23:46:59.150369
11145 23:46:59.255720 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_2 (53 ms)
11146 23:46:59.303020 [0:00:22.408775555] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11147 23:46:59.364633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_2 RESULT=skip>
11148 23:46:59.365359 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_2 RESULT=skip
11150 23:46:59.383401 [ RUN ] CaptureTests/SingleStream.Capture/Raw_3
11151 23:46:59.445248 Camera needs 4 requests, can't test only 3
11152 23:46:59.537386 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11153 23:46:59.628831
11154 23:46:59.723127 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_3 (54 ms)
11155 23:46:59.832263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_3 RESULT=skip>
11156 23:46:59.833028 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_3 RESULT=skip
11158 23:46:59.850107 [ RUN ] CaptureTests/SingleStream.Capture/Raw_5
11159 23:46:59.912538 [ OK ] CaptureTests/SingleStream.Capture/Raw_5 (428 ms)
11160 23:47:00.023011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_5 RESULT=pass>
11161 23:47:00.023735 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_5 RESULT=pass
11163 23:47:00.042742 [ RUN ] CaptureTests/SingleStream.Capture/Raw_8
11164 23:47:00.106273 [ OK ] CaptureTests/SingleStream.Capture/Raw_8 (693 ms)
11165 23:47:00.216948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_8 RESULT=pass>
11166 23:47:00.217707 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_8 RESULT=pass
11168 23:47:00.236235 [ RUN ] CaptureTests/SingleStream.Capture/Raw_13
11169 23:47:00.550589 [ OK ] CaptureTests/SingleStream.Capture/Raw_13 (1259 ms)
11170 23:47:00.559656 [0:00:23.670188696] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11171 23:47:00.659378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_13 RESULT=pass>
11172 23:47:00.660140 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_13 RESULT=pass
11174 23:47:00.679034 [ RUN ] CaptureTests/SingleStream.Capture/Raw_21
11175 23:47:02.366312 [ OK ] CaptureTests/SingleStream.Capture/Raw_21 (1821 ms)
11176 23:47:02.375827 [0:00:25.492649409] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11177 23:47:02.479875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_21 RESULT=pass>
11178 23:47:02.480612 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_21 RESULT=pass
11180 23:47:02.500905 [ RUN ] CaptureTests/SingleStream.Capture/Raw_34
11181 23:47:05.094197 [ OK ] CaptureTests/SingleStream.Capture/Raw_34 (2734 ms)
11182 23:47:05.103788 [0:00:28.227219406] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11183 23:47:05.211921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_34 RESULT=pass>
11184 23:47:05.212825 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_34 RESULT=pass
11186 23:47:05.231399 [ RUN ] CaptureTests/SingleStream.Capture/Raw_55
11187 23:47:09.291449 [ OK ] CaptureTests/SingleStream.Capture/Raw_55 (4204 ms)
11188 23:47:09.301221 [0:00:32.431340203] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11189 23:47:09.389213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_55 RESULT=pass>
11190 23:47:09.389509 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_55 RESULT=pass
11192 23:47:09.406615 [ RUN ] CaptureTests/SingleStream.Capture/Raw_89
11193 23:47:14.711522 <6>[ 37.914345] vpu: disabling
11194 23:47:14.714475 <6>[ 37.917442] vproc2: disabling
11195 23:47:14.717765 <6>[ 37.920766] vproc1: disabling
11196 23:47:14.721289 <6>[ 37.924077] vaud18: disabling
11197 23:47:14.727605 <6>[ 37.927587] vsram_others: disabling
11198 23:47:14.730838 <6>[ 37.931545] va09: disabling
11199 23:47:14.734095 <6>[ 37.934709] vsram_md: disabling
11200 23:47:14.737825 <6>[ 37.938272] Vgpu: disabling
11201 23:47:15.868727 [ OK ] CaptureTests/SingleStream.Capture/Raw_89 (6582 ms)
11202 23:47:15.878920 [0:00:39.014022218] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11203 23:47:15.933321 [0:00:39.069205341] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11204 23:47:15.965112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_89 RESULT=pass>
11205 23:47:15.965404 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_89 RESULT=pass
11207 23:47:15.987395 [0:00:39.123263394] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11208 23:47:15.990620 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_1
11209 23:47:16.036568 Camera needs 4 requests, can't test only 1
11210 23:47:16.046220 [0:00:39.179697794] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11211 23:47:16.113670 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11212 23:47:16.185721
11213 23:47:16.264346 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_1 (56 ms)
11214 23:47:16.353775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip>
11215 23:47:16.354105 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip
11217 23:47:16.370799 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_2
11218 23:47:16.427160 Camera needs 4 requests, can't test only 2
11219 23:47:16.505190 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11220 23:47:16.580202
11221 23:47:16.656909 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_2 (53 ms)
11222 23:47:16.739234 [0:00:39.875236063] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11223 23:47:16.745923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip>
11224 23:47:16.746217 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip
11226 23:47:16.762688 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_3
11227 23:47:16.814746 Camera needs 4 requests, can't test only 3
11228 23:47:16.892409 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11229 23:47:16.963388
11230 23:47:17.041774 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_3 (56 ms)
11231 23:47:17.131184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip>
11232 23:47:17.131564 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip
11234 23:47:17.147021 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_5
11235 23:47:17.199643 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_5 (695 ms)
11236 23:47:17.288113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass>
11237 23:47:17.288429 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass
11239 23:47:17.304129 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_8
11240 23:47:17.637091 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_8 (906 ms)
11241 23:47:17.650393 [0:00:40.783584738] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11242 23:47:17.729137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass>
11243 23:47:17.729426 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass
11245 23:47:17.743960 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_13
11246 23:47:18.893832 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_13 (1257 ms)
11247 23:47:18.906961 [0:00:42.040785177] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11248 23:47:18.985230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass>
11249 23:47:18.985526 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass
11251 23:47:19.001708 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_21
11252 23:47:20.712040 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_21 (1818 ms)
11253 23:47:20.725088 [0:00:43.859848300] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11254 23:47:20.803475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass>
11255 23:47:20.803774 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass
11257 23:47:20.819560 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_34
11258 23:47:23.442288 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_34 (2730 ms)
11259 23:47:23.455137 [0:00:46.590259478] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11260 23:47:23.534948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass>
11261 23:47:23.535238 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass
11263 23:47:23.552038 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_55
11264 23:47:27.640568 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_55 (4198 ms)
11265 23:47:27.653070 [0:00:50.788860206] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11266 23:47:27.763924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass>
11267 23:47:27.764708 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass
11269 23:47:27.783254 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_89
11270 23:47:34.217694 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_89 (6578 ms)
11271 23:47:34.230697 [0:00:57.367745487] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11272 23:47:34.282465 [0:00:57.422879853] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11273 23:47:34.336780 [0:00:57.477173035] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11274 23:47:34.343109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass>
11275 23:47:34.343796 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass
11277 23:47:34.355525 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_1
11278 23:47:34.393127 [0:00:57.533932386] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11279 23:47:34.417780 Camera needs 4 requests, can't test only 1
11280 23:47:34.511363 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11281 23:47:34.598402
11282 23:47:34.696044 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_1 (56 ms)
11283 23:47:34.805507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip>
11284 23:47:34.806279 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip
11286 23:47:34.826031 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_2
11287 23:47:34.891738 Camera needs 4 requests, can't test only 2
11288 23:47:34.984565 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11289 23:47:35.076590
11290 23:47:35.089097 [0:00:58.229364632] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11291 23:47:35.178661 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_2 (54 ms)
11292 23:47:35.289988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip>
11293 23:47:35.290790 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip
11295 23:47:35.309202 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_3
11296 23:47:35.373581 Camera needs 4 requests, can't test only 3
11297 23:47:35.468482 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11298 23:47:35.560076
11299 23:47:35.660137 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_3 (56 ms)
11300 23:47:35.777281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip>
11301 23:47:35.778058 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip
11303 23:47:35.798235 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_5
11304 23:47:35.866917 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_5 (695 ms)
11305 23:47:35.979999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass>
11306 23:47:35.980908 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass
11308 23:47:35.995824 [0:00:59.136739593] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11309 23:47:36.002410 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_8
11310 23:47:36.066221 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_8 (907 ms)
11311 23:47:36.181213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass>
11312 23:47:36.181994 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass
11314 23:47:36.202911 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_13
11315 23:47:37.243056 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_13 (1255 ms)
11316 23:47:37.256686 [0:01:00.393618611] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11317 23:47:37.365982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass>
11318 23:47:37.366866 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass
11320 23:47:37.387066 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_21
11321 23:47:39.060551 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_21 (1817 ms)
11322 23:47:39.074138 [0:01:02.211798198] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11323 23:47:39.179665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass>
11324 23:47:39.180502 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass
11326 23:47:39.198660 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_34
11327 23:47:41.790233 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_34 (2729 ms)
11328 23:47:41.802936 [0:01:04.941256415] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11329 23:47:41.894878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass>
11330 23:47:41.895277 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass
11332 23:47:41.912939 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_55
11333 23:47:45.987398 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_55 (4198 ms)
11334 23:47:46.000459 [0:01:09.139588531] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11335 23:47:46.079421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass>
11336 23:47:46.079733 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass
11338 23:47:46.095288 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_89
11339 23:47:52.565333 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_89 (6578 ms)
11340 23:47:52.578274 [0:01:15.718181206] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11341 23:47:52.631170 [0:01:15.773909317] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11342 23:47:52.672486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass>
11343 23:47:52.672783 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass
11345 23:47:52.686425 [0:01:15.829737583] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11346 23:47:52.689673 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_1
11347 23:47:52.740067 [0:01:15.882874531] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11348 23:47:52.743128 Camera needs 4 requests, can't test only 1
11349 23:47:52.818028 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11350 23:47:52.897445
11351 23:47:52.988761 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_1 (56 ms)
11352 23:47:53.091507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip>
11353 23:47:53.092573 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip
11355 23:47:53.109876 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_2
11356 23:47:53.171837 Camera needs 4 requests, can't test only 2
11357 23:47:53.251000 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11358 23:47:53.330362
11359 23:47:53.434143 [0:01:16.576992544] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11360 23:47:53.437165 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_2 (55 ms)
11361 23:47:53.534729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip>
11362 23:47:53.535062 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip
11364 23:47:53.551227 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_3
11365 23:47:53.603694 Camera needs 4 requests, can't test only 3
11366 23:47:53.679860 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11367 23:47:53.756786
11368 23:47:53.851343 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_3 (53 ms)
11369 23:47:53.962529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip>
11370 23:47:53.963311 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip
11372 23:47:53.982497 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_5
11373 23:47:54.049948 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_5 (693 ms)
11374 23:47:54.165862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass>
11375 23:47:54.166696 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass
11377 23:47:54.184668 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_8
11378 23:47:54.331440 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_8 (905 ms)
11379 23:47:54.344580 [0:01:17.483923871] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11380 23:47:54.444043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass>
11381 23:47:54.444827 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass
11383 23:47:54.462928 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_13
11384 23:47:55.588848 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_13 (1257 ms)
11385 23:47:55.602147 [0:01:18.741801857] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11386 23:47:55.702111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass>
11387 23:47:55.702908 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass
11389 23:47:55.722152 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_21
11390 23:47:57.405959 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_21 (1817 ms)
11391 23:47:57.419086 [0:01:20.559336933] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11392 23:47:57.522346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass>
11393 23:47:57.523115 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass
11395 23:47:57.544484 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_34
11396 23:48:00.134339 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_34 (2728 ms)
11397 23:48:00.147283 [0:01:23.287548960] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11398 23:48:00.246932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass>
11399 23:48:00.247666 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass
11401 23:48:00.266136 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_55
11402 23:48:04.331794 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_55 (4198 ms)
11403 23:48:04.344565 [0:01:27.485331642] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11404 23:48:04.451681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass>
11405 23:48:04.452474 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass
11407 23:48:04.469927 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_89
11408 23:48:10.909495 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_89 (6578 ms)
11409 23:48:10.922501 [0:01:34.064051464] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11410 23:48:10.974534 [0:01:34.119387481] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11411 23:48:11.031048 [0:01:34.176064574] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11412 23:48:11.034951 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass
11414 23:48:11.037497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass>
11415 23:48:11.049000 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_1
11416 23:48:11.083269 [0:01:34.228178358] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11417 23:48:11.115060 Camera needs 4 requests, can't test only 1
11418 23:48:11.208531 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11419 23:48:11.297328
11420 23:48:11.392753 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_1 (56 ms)
11421 23:48:11.503180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip>
11422 23:48:11.503944 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip
11424 23:48:11.521424 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_2
11425 23:48:11.583513 Camera needs 4 requests, can't test only 2
11426 23:48:11.679577 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11427 23:48:11.773341
11428 23:48:11.870701 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_2 (57 ms)
11429 23:48:11.978865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip>
11430 23:48:11.979691 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip
11432 23:48:11.997370 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_3
11433 23:48:12.058370 Camera needs 4 requests, can't test only 3
11434 23:48:12.153905 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11435 23:48:12.241224
11436 23:48:12.344449 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_3 (52 ms)
11437 23:48:12.456427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip>
11438 23:48:12.457240 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip
11440 23:48:12.478858 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_5
11441 23:48:13.154133 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_5 (2078 ms)
11442 23:48:13.167339 [0:01:36.309476486] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11443 23:48:13.265016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass>
11444 23:48:13.265781 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass
11446 23:48:13.285142 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_8
11447 23:48:15.870906 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_8 (2716 ms)
11448 23:48:15.884186 [0:01:39.025878590] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11449 23:48:15.987056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass>
11450 23:48:15.987808 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass
11452 23:48:16.005743 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_13
11453 23:48:19.632303 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_13 (3761 ms)
11454 23:48:19.645551 [0:01:42.787946184] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11455 23:48:19.751918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass>
11456 23:48:19.752715 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass
11458 23:48:19.772017 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_21
11459 23:48:25.072998 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_21 (5440 ms)
11460 23:48:25.085476 [0:01:48.228867149] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11461 23:48:25.188808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass>
11462 23:48:25.189568 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass
11464 23:48:25.207277 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_34
11465 23:48:33.246338 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_34 (8174 ms)
11466 23:48:33.259105 [0:01:56.403203982] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11467 23:48:33.369540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass>
11468 23:48:33.370275 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass
11470 23:48:33.389359 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_55
11471 23:48:45.827609 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_55 (12582 ms)
11472 23:48:45.840372 [0:02:08.985598687] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11473 23:48:45.949093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass>
11474 23:48:45.949931 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass
11476 23:48:45.968104 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_89
11477 23:49:05.549001 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_89 (19723 ms)
11478 23:49:05.561911 [0:02:28.709875707] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11479 23:49:05.614102 [0:02:28.764756400] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11480 23:49:05.669769 [0:02:28.820666861] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11481 23:49:05.676452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass>
11482 23:49:05.677179 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass
11484 23:49:05.685556 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1
11485 23:49:05.725673 [0:02:28.876834784] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11486 23:49:05.750602 Camera needs 4 requests, can't test only 1
11487 23:49:05.843222 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11488 23:49:05.935938
11489 23:49:06.040064 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1 (56 ms)
11490 23:49:06.151258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip>
11491 23:49:06.152036 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip
11493 23:49:06.168436 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2
11494 23:49:06.230671 Camera needs 4 requests, can't test only 2
11495 23:49:06.323775 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11496 23:49:06.418837
11497 23:49:06.521747 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2 (55 ms)
11498 23:49:06.632557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip>
11499 23:49:06.633344 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip
11501 23:49:06.649096 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3
11502 23:49:06.713902 Camera needs 4 requests, can't test only 3
11503 23:49:06.805262 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11504 23:49:06.894064
11505 23:49:06.992014 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3 (56 ms)
11506 23:49:07.096694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip>
11507 23:49:07.097503 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip
11509 23:49:07.113652 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5
11510 23:49:07.798791 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5 (2078 ms)
11511 23:49:07.808674 [0:02:30.956984785] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11512 23:49:07.915752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass>
11513 23:49:07.916524 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass
11515 23:49:07.932458 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8
11516 23:49:10.510952 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8 (2712 ms)
11517 23:49:10.520634 [0:02:33.669005247] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11518 23:49:10.628530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass>
11519 23:49:10.629347 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass
11521 23:49:10.643740 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13
11522 23:49:14.271714 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13 (3761 ms)
11523 23:49:14.281610 [0:02:37.429860170] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11524 23:49:14.386267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass>
11525 23:49:14.387054 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass
11527 23:49:14.402331 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21
11528 23:49:19.712422 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21 (5441 ms)
11529 23:49:19.722059 [0:02:42.871711402] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11530 23:49:19.825707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass>
11531 23:49:19.826685 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass
11533 23:49:19.842157 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34
11534 23:49:27.886082 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34 (8174 ms)
11535 23:49:27.895862 [0:02:51.045784172] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11536 23:49:27.999695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass>
11537 23:49:28.000440 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass
11539 23:49:28.015417 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55
11540 23:49:40.467140 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55 (12582 ms)
11541 23:49:40.476708 [0:03:03.628570557] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11542 23:49:40.593609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass>
11543 23:49:40.594484 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass
11545 23:49:40.611679 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89
11546 23:50:00.189427 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89 (19724 ms)
11547 23:50:00.198993 [0:03:23.352958174] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11548 23:50:00.251165 [0:03:23.408282174] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11549 23:50:00.306929 [0:03:23.464386174] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11550 23:50:00.313414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass>
11551 23:50:00.314105 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass
11553 23:50:00.328052 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1
11554 23:50:00.361877 [0:03:23.519248174] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11555 23:50:00.390853 Camera needs 4 requests, can't test only 1
11556 23:50:00.490833 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11557 23:50:00.583969
11558 23:50:00.687456 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1 (56 ms)
11559 23:50:00.797865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip>
11560 23:50:00.798689 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip
11562 23:50:00.814708 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2
11563 23:50:00.878111 Camera needs 4 requests, can't test only 2
11564 23:50:00.968225 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11565 23:50:01.058072
11566 23:50:01.158441 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2 (56 ms)
11567 23:50:01.266987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip>
11568 23:50:01.267795 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip
11570 23:50:01.281988 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3
11571 23:50:01.344508 Camera needs 4 requests, can't test only 3
11572 23:50:01.438932 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11573 23:50:01.531100
11574 23:50:01.635469 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3 (54 ms)
11575 23:50:01.751053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip>
11576 23:50:01.751813 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip
11578 23:50:01.767346 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5
11579 23:50:02.434154 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5 (2077 ms)
11580 23:50:02.443946 [0:03:25.597886251] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11581 23:50:02.551339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass>
11582 23:50:02.552101 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass
11584 23:50:02.568391 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8
11585 23:50:05.146639 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8 (2712 ms)
11586 23:50:05.156449 [0:03:28.310825866] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11587 23:50:05.262689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass>
11588 23:50:05.263449 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass
11590 23:50:05.279977 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13
11591 23:50:08.907262 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13 (3760 ms)
11592 23:50:08.916757 [0:03:32.071438559] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11593 23:50:09.030751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass>
11594 23:50:09.031552 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass
11596 23:50:09.047175 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21
11597 23:50:14.347769 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21 (5441 ms)
11598 23:50:14.357240 [0:03:37.512917713] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11599 23:50:14.462374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass>
11600 23:50:14.463113 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass
11602 23:50:14.477553 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34
11603 23:50:22.522604 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34 (8175 ms)
11604 23:50:22.532779 [0:03:45.689019098] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11605 23:50:22.636057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass>
11606 23:50:22.636977 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass
11608 23:50:22.652326 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55
11609 23:50:35.104736 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55 (12583 ms)
11610 23:50:35.113857 [0:03:58.271902330] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11611 23:50:35.220472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass>
11612 23:50:35.221238 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass
11614 23:50:35.236628 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89
11615 23:50:54.825781 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89 (19723 ms)
11616 23:50:54.835441 [0:04:17.995718946] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11617 23:50:54.887341 [0:04:18.050911023] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11618 23:50:54.941787 [0:04:18.104925562] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11619 23:50:54.956009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass>
11620 23:50:54.956769 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass
11622 23:50:54.973231 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1
11623 23:50:54.995432 [0:04:18.158960177] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11624 23:50:55.041261 Camera needs 4 requests, can't test only 1
11625 23:50:55.142691 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11626 23:50:55.238685
11627 23:50:55.347302 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1 (56 ms)
11628 23:50:55.455844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip>
11629 23:50:55.456612 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip
11631 23:50:55.473305 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2
11632 23:50:55.537241 Camera needs 4 requests, can't test only 2
11633 23:50:55.631491 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11634 23:50:55.725098
11635 23:50:55.826496 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2 (54 ms)
11636 23:50:55.938903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip>
11637 23:50:55.939668 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip
11639 23:50:55.956014 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3
11640 23:50:56.024095 Camera needs 4 requests, can't test only 3
11641 23:50:56.125008 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11642 23:50:56.223069
11643 23:50:56.331654 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3 (53 ms)
11644 23:50:56.451621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip>
11645 23:50:56.452390 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip
11647 23:50:56.467906 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5
11648 23:50:57.069172 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5 (2078 ms)
11649 23:50:57.079363 [0:04:20.239569562] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11650 23:50:57.188318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass>
11651 23:50:57.189112 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass
11653 23:50:57.202957 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8
11654 23:50:59.781403 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8 (2712 ms)
11655 23:50:59.791270 [0:04:22.951377100] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11656 23:50:59.899060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass>
11657 23:50:59.899839 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass
11659 23:50:59.914701 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13
11660 23:51:03.542831 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13 (3761 ms)
11661 23:51:03.552512 [0:04:26.713533562] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11662 23:51:03.661585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass>
11663 23:51:03.662352 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass
11665 23:51:03.678570 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21
11666 23:51:08.982223 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21 (5440 ms)
11667 23:51:08.992296 [0:04:32.154046562] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11668 23:51:09.102932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass>
11669 23:51:09.103700 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass
11671 23:51:09.119503 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34
11672 23:51:17.156085 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34 (8174 ms)
11673 23:51:17.165722 [0:04:40.328575255] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11674 23:51:17.273466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass>
11675 23:51:17.274290 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass
11677 23:51:17.288691 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55
11678 23:51:29.737796 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55 (12583 ms)
11679 23:51:29.747981 [0:04:52.911537641] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11680 23:51:29.857812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass>
11681 23:51:29.858623 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass
11683 23:51:29.873693 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89
11684 23:51:49.460450 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89 (19724 ms)
11685 23:51:49.469840 [0:05:12.636136257] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11686 23:51:49.577471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass>
11687 23:51:49.578230 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass
11689 23:51:49.593233 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_1
11690 23:51:49.874395 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_1 (417 ms)
11691 23:51:49.887877 [0:05:13.053933026] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11692 23:51:49.990278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass>
11693 23:51:49.991053 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass
11695 23:51:50.008718 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_2
11696 23:51:50.364439 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_2 (489 ms)
11697 23:51:50.377471 [0:05:13.543598103] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11698 23:51:50.480630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass>
11699 23:51:50.481404 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass
11701 23:51:50.499882 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_3
11702 23:51:50.922575 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_3 (557 ms)
11703 23:51:50.935034 [0:05:14.101538796] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11704 23:51:51.039969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass>
11705 23:51:51.040759 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass
11707 23:51:51.060123 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_5
11708 23:51:51.620044 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_5 (698 ms)
11709 23:51:51.633921 [0:05:14.799603334] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11710 23:51:51.733985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass>
11711 23:51:51.734787 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass
11713 23:51:51.751976 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_8
11714 23:51:52.527517 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_8 (907 ms)
11715 23:51:52.540583 [0:05:15.707181565] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11716 23:51:52.642624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass>
11717 23:51:52.643396 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass
11719 23:51:52.662073 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_13
11720 23:51:53.784429 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_13 (1256 ms)
11721 23:51:53.797855 [0:05:16.964112104] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11722 23:51:53.904094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass>
11723 23:51:53.904866 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass
11725 23:51:53.924157 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_21
11726 23:51:55.601960 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_21 (1817 ms)
11727 23:51:55.615167 [0:05:18.781295642] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11728 23:51:55.725079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass>
11729 23:51:55.725819 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass
11731 23:51:55.746749 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_34
11732 23:51:58.328841 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_34 (2727 ms)
11733 23:51:58.341641 [0:05:21.508930796] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11734 23:51:58.449120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass>
11735 23:51:58.449949 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass
11737 23:51:58.466562 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_55
11738 23:52:02.526492 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_55 (4198 ms)
11739 23:52:02.539134 [0:05:25.707152104] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11740 23:52:02.647186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass>
11741 23:52:02.647943 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass
11743 23:52:02.666273 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_89
11744 23:52:09.103773 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_89 (6577 ms)
11745 23:52:09.116753 [0:05:32.285227797] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11746 23:52:09.220312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass>
11747 23:52:09.221035 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass
11749 23:52:09.240329 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1
11750 23:52:09.524385 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1 (417 ms)
11751 23:52:09.533639 [0:05:32.701892720] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11752 23:52:09.639500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass>
11753 23:52:09.640239 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass
11755 23:52:09.655194 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2
11756 23:52:10.011597 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2 (487 ms)
11757 23:52:10.020868 [0:05:33.189743720] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11758 23:52:10.132116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass>
11759 23:52:10.132923 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass
11761 23:52:10.149837 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3
11762 23:52:10.569401 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3 (557 ms)
11763 23:52:10.579160 [0:05:33.747692643] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11764 23:52:10.688594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass>
11765 23:52:10.689366 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass
11767 23:52:10.704977 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5
11768 23:52:11.267124 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5 (697 ms)
11769 23:52:11.277173 [0:05:34.445744566] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11770 23:52:11.386127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass>
11771 23:52:11.386940 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass
11773 23:52:11.401990 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8
11774 23:52:12.176913 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8 (909 ms)
11775 23:52:12.186627 [0:05:35.355251105] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11776 23:52:12.296920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass>
11777 23:52:12.297858 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass
11779 23:52:12.313929 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13
11780 23:52:13.433689 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13 (1257 ms)
11781 23:52:13.443423 [0:05:36.612621566] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11782 23:52:13.546601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass>
11783 23:52:13.547369 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass
11785 23:52:13.563357 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21
11786 23:52:15.251316 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21 (1817 ms)
11787 23:52:15.260916 [0:05:38.430232259] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11788 23:52:15.360061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass>
11789 23:52:15.360802 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass
11791 23:52:15.374955 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34
11792 23:52:17.981146 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34 (2729 ms)
11793 23:52:17.990533 [0:05:41.160220951] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11794 23:52:18.090983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass>
11795 23:52:18.091729 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass
11797 23:52:18.107493 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55
11798 23:52:22.179086 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55 (4198 ms)
11799 23:52:22.188326 [0:05:45.358005336] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11800 23:52:22.296089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass>
11801 23:52:22.296904 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass
11803 23:52:22.313824 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89
11804 23:52:28.755863 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89 (6578 ms)
11805 23:52:28.765630 [0:05:51.936611490] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11806 23:52:28.871784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass>
11807 23:52:28.872562 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass
11809 23:52:28.888224 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1
11810 23:52:29.174298 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1 (417 ms)
11811 23:52:29.183776 [0:05:52.354619413] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11812 23:52:29.289143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass>
11813 23:52:29.289905 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass
11815 23:52:29.306202 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2
11816 23:52:29.661865 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2 (487 ms)
11817 23:52:29.671989 [0:05:52.842670490] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11818 23:52:29.774642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass>
11819 23:52:29.775401 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass
11821 23:52:29.791172 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3
11822 23:52:30.219908 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3 (557 ms)
11823 23:52:30.229853 [0:05:53.400631644] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11824 23:52:30.335981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass>
11825 23:52:30.336707 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass
11827 23:52:30.352072 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5
11828 23:52:30.918037 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5 (697 ms)
11829 23:52:30.927662 [0:05:54.098027798] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11830 23:52:31.034635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass>
11831 23:52:31.035394 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass
11833 23:52:31.050516 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8
11834 23:52:31.827002 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8 (909 ms)
11835 23:52:31.837249 [0:05:55.007760260] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11836 23:52:31.946252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass>
11837 23:52:31.947025 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass
11839 23:52:31.963305 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13
11840 23:52:33.084365 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13 (1257 ms)
11841 23:52:33.094204 [0:05:56.265629029] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11842 23:52:33.195889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass>
11843 23:52:33.196676 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass
11845 23:52:33.212199 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21
11846 23:52:34.901736 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21 (1817 ms)
11847 23:52:34.911706 [0:05:58.083049183] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11848 23:52:35.020808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass>
11849 23:52:35.021639 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass
11851 23:52:35.038449 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34
11852 23:52:37.629400 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34 (2727 ms)
11853 23:52:37.638985 [0:06:00.810844414] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11854 23:52:37.750105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass>
11855 23:52:37.750897 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass
11857 23:52:37.766537 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55
11858 23:52:41.826489 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55 (4197 ms)
11859 23:52:41.835842 [0:06:05.007974183] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11860 23:52:41.939995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass>
11861 23:52:41.940736 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass
11863 23:52:41.957533 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89
11864 23:52:48.403773 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89 (6578 ms)
11865 23:52:48.413539 [0:06:11.586102645] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11866 23:52:48.520055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass>
11867 23:52:48.520793 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass
11869 23:52:48.536106 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1
11870 23:52:48.821186 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1 (416 ms)
11871 23:52:48.830967 [0:06:12.003441107] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11872 23:52:48.935381 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass
11874 23:52:48.938026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass>
11875 23:52:48.955463 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2
11876 23:52:49.308787 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2 (487 ms)
11877 23:52:49.318051 [0:06:12.491272030] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11878 23:52:49.425706 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass
11880 23:52:49.428582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass>
11881 23:52:49.445125 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3
11882 23:52:49.865721 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3 (557 ms)
11883 23:52:49.875229 [0:06:13.048229184] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11884 23:52:49.987990 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass
11886 23:52:49.990983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass>
11887 23:52:50.007028 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5
11888 23:52:50.562882 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5 (697 ms)
11889 23:52:50.572475 [0:06:13.745567030] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11890 23:52:50.674740 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass
11892 23:52:50.677295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass>
11893 23:52:50.692931 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8
11894 23:52:51.470638 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8 (908 ms)
11895 23:52:51.481206 [0:06:14.653823261] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11896 23:52:51.584817 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass
11898 23:52:51.587535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass>
11899 23:52:51.604862 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13
11900 23:52:52.729266 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13 (1258 ms)
11901 23:52:52.738634 [0:06:15.912082030] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11902 23:52:52.846736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass>
11903 23:52:52.847554 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass
11905 23:52:52.863476 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21
11906 23:52:54.546325 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21 (1817 ms)
11907 23:52:54.556327 [0:06:17.729439953] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11908 23:52:54.657480 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass
11910 23:52:54.660073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass>
11911 23:52:54.678423 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34
11912 23:52:57.274158 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34 (2728 ms)
11913 23:52:57.284047 [0:06:20.458070492] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11914 23:52:57.401663 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass
11916 23:52:57.404971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass>
11917 23:52:57.421986 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55
11918 23:53:01.472516 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55 (4198 ms)
11919 23:53:01.481956 [0:06:24.656238184] [417] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11920 23:53:01.593301 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass
11922 23:53:01.596126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass>
11923 23:53:01.614242 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89
11924 23:53:08.049912 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89 (6578 ms)
11925 23:53:08.151252 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass
11927 23:53:08.153488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass>
11928 23:53:08.169864 [----------] 120 tests from CaptureTests/SingleStream (370109 ms total)
11929 23:53:08.263194
11930 23:53:08.365883 [----------] Global test environment tear-down
11931 23:53:08.463314 [==========] 120 tests from 1 test suite ran. (370110 ms total)
11932 23:53:08.561517 <LAVA_SIGNAL_TESTSET STOP>
11933 23:53:08.562282 Received signal: <TESTSET> STOP
11934 23:53:08.562650 Closing test_set CaptureTests/SingleStream
11935 23:53:08.564741 + set +x
11936 23:53:08.568305 <LAVA_SIGNAL_ENDRUN 0_lc-compliance 14172980_1.6.2.3.1>
11937 23:53:08.568973 Received signal: <ENDRUN> 0_lc-compliance 14172980_1.6.2.3.1
11938 23:53:08.569362 Ending use of test pattern.
11939 23:53:08.569677 Ending test lava.0_lc-compliance (14172980_1.6.2.3.1), duration 372.23
11941 23:53:08.571570 <LAVA_TEST_RUNNER EXIT>
11942 23:53:08.572253 ok: lava_test_shell seems to have completed
11943 23:53:08.581216 Capture/Raw_1:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_13:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_2:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_21:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_3:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_34:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_5:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_55:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_8:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_89:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
11944 23:53:08.582063 end: 3.1 lava-test-shell (duration 00:06:13) [common]
11945 23:53:08.582549 end: 3 lava-test-retry (duration 00:06:13) [common]
11946 23:53:08.582986 start: 4 finalize (timeout 00:10:00) [common]
11947 23:53:08.583420 start: 4.1 power-off (timeout 00:00:30) [common]
11948 23:53:08.584154 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-9', '--port=1', '--command=off']
11949 23:53:08.847936 >> Command sent successfully.
11950 23:53:08.858340 Returned 0 in 0 seconds
11951 23:53:08.959628 end: 4.1 power-off (duration 00:00:00) [common]
11953 23:53:08.961124 start: 4.2 read-feedback (timeout 00:10:00) [common]
11954 23:53:08.962482 Listened to connection for namespace 'common' for up to 1s
11955 23:53:09.962459 Finalising connection for namespace 'common'
11956 23:53:09.963138 Disconnecting from shell: Finalise
11957 23:53:09.963551 / #
11958 23:53:10.064540 end: 4.2 read-feedback (duration 00:00:01) [common]
11959 23:53:10.065242 end: 4 finalize (duration 00:00:01) [common]
11960 23:53:10.065822 Cleaning after the job
11961 23:53:10.066360 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14172980/tftp-deploy-2o3salbj/ramdisk
11962 23:53:10.075695 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14172980/tftp-deploy-2o3salbj/kernel
11963 23:53:10.110042 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14172980/tftp-deploy-2o3salbj/dtb
11964 23:53:10.110448 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14172980/tftp-deploy-2o3salbj/nfsrootfs
11965 23:53:10.158216 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14172980/tftp-deploy-2o3salbj/modules
11966 23:53:10.163696 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14172980
11967 23:53:10.415344 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14172980
11968 23:53:10.415516 Job finished correctly