Boot log: mt8192-asurada-spherion-r0
- Errors: 1
- Kernel Errors: 27
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 26
1 23:43:38.903258 lava-dispatcher, installed at version: 2024.03
2 23:43:38.903481 start: 0 validate
3 23:43:38.903625 Start time: 2024-06-04 23:43:38.903617+00:00 (UTC)
4 23:43:38.903753 Using caching service: 'http://localhost/cache/?uri=%s'
5 23:43:38.903885 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-v4l2%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 23:43:39.164274 Using caching service: 'http://localhost/cache/?uri=%s'
7 23:43:39.164483 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 23:43:39.414553 Using caching service: 'http://localhost/cache/?uri=%s'
9 23:43:39.414728 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 23:43:39.673285 Using caching service: 'http://localhost/cache/?uri=%s'
11 23:43:39.673445 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 23:43:39.933282 validate duration: 1.03
14 23:43:39.933572 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 23:43:39.933688 start: 1.1 download-retry (timeout 00:10:00) [common]
16 23:43:39.933791 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 23:43:39.975641 Not decompressing ramdisk as can be used compressed.
18 23:43:39.975838 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-v4l2/20240313.0/arm64/rootfs.cpio.gz
19 23:43:39.975916 saving as /var/lib/lava/dispatcher/tmp/14172956/tftp-deploy-mv6oeqmu/ramdisk/rootfs.cpio.gz
20 23:43:39.975982 total size: 28105535 (26 MB)
21 23:43:39.977665 progress 0 % (0 MB)
22 23:43:39.985384 progress 5 % (1 MB)
23 23:43:39.992799 progress 10 % (2 MB)
24 23:43:40.000215 progress 15 % (4 MB)
25 23:43:40.007993 progress 20 % (5 MB)
26 23:43:40.015398 progress 25 % (6 MB)
27 23:43:40.022774 progress 30 % (8 MB)
28 23:43:40.030224 progress 35 % (9 MB)
29 23:43:40.037546 progress 40 % (10 MB)
30 23:43:40.044692 progress 45 % (12 MB)
31 23:43:40.051953 progress 50 % (13 MB)
32 23:43:40.059314 progress 55 % (14 MB)
33 23:43:40.066661 progress 60 % (16 MB)
34 23:43:40.074208 progress 65 % (17 MB)
35 23:43:40.081508 progress 70 % (18 MB)
36 23:43:40.088858 progress 75 % (20 MB)
37 23:43:40.096125 progress 80 % (21 MB)
38 23:43:40.103422 progress 85 % (22 MB)
39 23:43:40.110370 progress 90 % (24 MB)
40 23:43:40.117530 progress 95 % (25 MB)
41 23:43:40.124743 progress 100 % (26 MB)
42 23:43:40.124987 26 MB downloaded in 0.15 s (179.89 MB/s)
43 23:43:40.125213 end: 1.1.1 http-download (duration 00:00:00) [common]
45 23:43:40.125449 end: 1.1 download-retry (duration 00:00:00) [common]
46 23:43:40.125534 start: 1.2 download-retry (timeout 00:10:00) [common]
47 23:43:40.125616 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 23:43:40.125752 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 23:43:40.125820 saving as /var/lib/lava/dispatcher/tmp/14172956/tftp-deploy-mv6oeqmu/kernel/Image
50 23:43:40.125881 total size: 54682112 (52 MB)
51 23:43:40.125941 No compression specified
52 23:43:40.127216 progress 0 % (0 MB)
53 23:43:40.141164 progress 5 % (2 MB)
54 23:43:40.155356 progress 10 % (5 MB)
55 23:43:40.169589 progress 15 % (7 MB)
56 23:43:40.183517 progress 20 % (10 MB)
57 23:43:40.198117 progress 25 % (13 MB)
58 23:43:40.212233 progress 30 % (15 MB)
59 23:43:40.226667 progress 35 % (18 MB)
60 23:43:40.241052 progress 40 % (20 MB)
61 23:43:40.254937 progress 45 % (23 MB)
62 23:43:40.269195 progress 50 % (26 MB)
63 23:43:40.283146 progress 55 % (28 MB)
64 23:43:40.298007 progress 60 % (31 MB)
65 23:43:40.312227 progress 65 % (33 MB)
66 23:43:40.326547 progress 70 % (36 MB)
67 23:43:40.344252 progress 75 % (39 MB)
68 23:43:40.359167 progress 80 % (41 MB)
69 23:43:40.373383 progress 85 % (44 MB)
70 23:43:40.387625 progress 90 % (46 MB)
71 23:43:40.401969 progress 95 % (49 MB)
72 23:43:40.416135 progress 100 % (52 MB)
73 23:43:40.416417 52 MB downloaded in 0.29 s (179.49 MB/s)
74 23:43:40.416587 end: 1.2.1 http-download (duration 00:00:00) [common]
76 23:43:40.416828 end: 1.2 download-retry (duration 00:00:00) [common]
77 23:43:40.416916 start: 1.3 download-retry (timeout 00:10:00) [common]
78 23:43:40.417008 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 23:43:40.417146 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 23:43:40.417216 saving as /var/lib/lava/dispatcher/tmp/14172956/tftp-deploy-mv6oeqmu/dtb/mt8192-asurada-spherion-r0.dtb
81 23:43:40.417277 total size: 47258 (0 MB)
82 23:43:40.417339 No compression specified
83 23:43:40.418430 progress 69 % (0 MB)
84 23:43:40.418756 progress 100 % (0 MB)
85 23:43:40.418947 0 MB downloaded in 0.00 s (27.05 MB/s)
86 23:43:40.419122 end: 1.3.1 http-download (duration 00:00:00) [common]
88 23:43:40.419482 end: 1.3 download-retry (duration 00:00:00) [common]
89 23:43:40.419597 start: 1.4 download-retry (timeout 00:10:00) [common]
90 23:43:40.419710 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 23:43:40.419857 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 23:43:40.419952 saving as /var/lib/lava/dispatcher/tmp/14172956/tftp-deploy-mv6oeqmu/modules/modules.tar
93 23:43:40.420042 total size: 8603924 (8 MB)
94 23:43:40.420133 Using unxz to decompress xz
95 23:43:40.424532 progress 0 % (0 MB)
96 23:43:40.444885 progress 5 % (0 MB)
97 23:43:40.470246 progress 10 % (0 MB)
98 23:43:40.496912 progress 15 % (1 MB)
99 23:43:40.522598 progress 20 % (1 MB)
100 23:43:40.549073 progress 25 % (2 MB)
101 23:43:40.574968 progress 30 % (2 MB)
102 23:43:40.599066 progress 35 % (2 MB)
103 23:43:40.625712 progress 40 % (3 MB)
104 23:43:40.650964 progress 45 % (3 MB)
105 23:43:40.675469 progress 50 % (4 MB)
106 23:43:40.700800 progress 55 % (4 MB)
107 23:43:40.726045 progress 60 % (4 MB)
108 23:43:40.750848 progress 65 % (5 MB)
109 23:43:40.778258 progress 70 % (5 MB)
110 23:43:40.804322 progress 75 % (6 MB)
111 23:43:40.830433 progress 80 % (6 MB)
112 23:43:40.855116 progress 85 % (7 MB)
113 23:43:40.879367 progress 90 % (7 MB)
114 23:43:40.908971 progress 95 % (7 MB)
115 23:43:40.937666 progress 100 % (8 MB)
116 23:43:40.943248 8 MB downloaded in 0.52 s (15.68 MB/s)
117 23:43:40.943508 end: 1.4.1 http-download (duration 00:00:01) [common]
119 23:43:40.943763 end: 1.4 download-retry (duration 00:00:01) [common]
120 23:43:40.943860 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 23:43:40.943951 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 23:43:40.944032 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 23:43:40.944135 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 23:43:40.944383 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14172956/lava-overlay-kxj_7x_j
125 23:43:40.944558 makedir: /var/lib/lava/dispatcher/tmp/14172956/lava-overlay-kxj_7x_j/lava-14172956/bin
126 23:43:40.944666 makedir: /var/lib/lava/dispatcher/tmp/14172956/lava-overlay-kxj_7x_j/lava-14172956/tests
127 23:43:40.944764 makedir: /var/lib/lava/dispatcher/tmp/14172956/lava-overlay-kxj_7x_j/lava-14172956/results
128 23:43:40.944884 Creating /var/lib/lava/dispatcher/tmp/14172956/lava-overlay-kxj_7x_j/lava-14172956/bin/lava-add-keys
129 23:43:40.945101 Creating /var/lib/lava/dispatcher/tmp/14172956/lava-overlay-kxj_7x_j/lava-14172956/bin/lava-add-sources
130 23:43:40.945240 Creating /var/lib/lava/dispatcher/tmp/14172956/lava-overlay-kxj_7x_j/lava-14172956/bin/lava-background-process-start
131 23:43:40.945373 Creating /var/lib/lava/dispatcher/tmp/14172956/lava-overlay-kxj_7x_j/lava-14172956/bin/lava-background-process-stop
132 23:43:40.945504 Creating /var/lib/lava/dispatcher/tmp/14172956/lava-overlay-kxj_7x_j/lava-14172956/bin/lava-common-functions
133 23:43:40.945627 Creating /var/lib/lava/dispatcher/tmp/14172956/lava-overlay-kxj_7x_j/lava-14172956/bin/lava-echo-ipv4
134 23:43:40.945753 Creating /var/lib/lava/dispatcher/tmp/14172956/lava-overlay-kxj_7x_j/lava-14172956/bin/lava-install-packages
135 23:43:40.945875 Creating /var/lib/lava/dispatcher/tmp/14172956/lava-overlay-kxj_7x_j/lava-14172956/bin/lava-installed-packages
136 23:43:40.946005 Creating /var/lib/lava/dispatcher/tmp/14172956/lava-overlay-kxj_7x_j/lava-14172956/bin/lava-os-build
137 23:43:40.946161 Creating /var/lib/lava/dispatcher/tmp/14172956/lava-overlay-kxj_7x_j/lava-14172956/bin/lava-probe-channel
138 23:43:40.946315 Creating /var/lib/lava/dispatcher/tmp/14172956/lava-overlay-kxj_7x_j/lava-14172956/bin/lava-probe-ip
139 23:43:40.946471 Creating /var/lib/lava/dispatcher/tmp/14172956/lava-overlay-kxj_7x_j/lava-14172956/bin/lava-target-ip
140 23:43:40.946601 Creating /var/lib/lava/dispatcher/tmp/14172956/lava-overlay-kxj_7x_j/lava-14172956/bin/lava-target-mac
141 23:43:40.946723 Creating /var/lib/lava/dispatcher/tmp/14172956/lava-overlay-kxj_7x_j/lava-14172956/bin/lava-target-storage
142 23:43:40.946845 Creating /var/lib/lava/dispatcher/tmp/14172956/lava-overlay-kxj_7x_j/lava-14172956/bin/lava-test-case
143 23:43:40.946967 Creating /var/lib/lava/dispatcher/tmp/14172956/lava-overlay-kxj_7x_j/lava-14172956/bin/lava-test-event
144 23:43:40.947097 Creating /var/lib/lava/dispatcher/tmp/14172956/lava-overlay-kxj_7x_j/lava-14172956/bin/lava-test-feedback
145 23:43:40.947283 Creating /var/lib/lava/dispatcher/tmp/14172956/lava-overlay-kxj_7x_j/lava-14172956/bin/lava-test-raise
146 23:43:40.947405 Creating /var/lib/lava/dispatcher/tmp/14172956/lava-overlay-kxj_7x_j/lava-14172956/bin/lava-test-reference
147 23:43:40.947528 Creating /var/lib/lava/dispatcher/tmp/14172956/lava-overlay-kxj_7x_j/lava-14172956/bin/lava-test-runner
148 23:43:40.947653 Creating /var/lib/lava/dispatcher/tmp/14172956/lava-overlay-kxj_7x_j/lava-14172956/bin/lava-test-set
149 23:43:40.947775 Creating /var/lib/lava/dispatcher/tmp/14172956/lava-overlay-kxj_7x_j/lava-14172956/bin/lava-test-shell
150 23:43:40.947927 Updating /var/lib/lava/dispatcher/tmp/14172956/lava-overlay-kxj_7x_j/lava-14172956/bin/lava-install-packages (oe)
151 23:43:40.948076 Updating /var/lib/lava/dispatcher/tmp/14172956/lava-overlay-kxj_7x_j/lava-14172956/bin/lava-installed-packages (oe)
152 23:43:40.948206 Creating /var/lib/lava/dispatcher/tmp/14172956/lava-overlay-kxj_7x_j/lava-14172956/environment
153 23:43:40.948310 LAVA metadata
154 23:43:40.948385 - LAVA_JOB_ID=14172956
155 23:43:40.948448 - LAVA_DISPATCHER_IP=192.168.201.1
156 23:43:40.948550 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 23:43:40.948616 skipped lava-vland-overlay
158 23:43:40.948691 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 23:43:40.948774 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 23:43:40.948844 skipped lava-multinode-overlay
161 23:43:40.948914 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 23:43:40.949022 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 23:43:40.949116 Loading test definitions
164 23:43:40.949276 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 23:43:40.949351 Using /lava-14172956 at stage 0
166 23:43:40.949657 uuid=14172956_1.5.2.3.1 testdef=None
167 23:43:40.949745 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 23:43:40.949833 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 23:43:40.950339 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 23:43:40.950561 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 23:43:40.951193 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 23:43:40.951424 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 23:43:40.952016 runner path: /var/lib/lava/dispatcher/tmp/14172956/lava-overlay-kxj_7x_j/lava-14172956/0/tests/0_v4l2-compliance-mtk-vcodec-enc test_uuid 14172956_1.5.2.3.1
176 23:43:40.952171 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 23:43:40.952375 Creating lava-test-runner.conf files
179 23:43:40.952437 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14172956/lava-overlay-kxj_7x_j/lava-14172956/0 for stage 0
180 23:43:40.952529 - 0_v4l2-compliance-mtk-vcodec-enc
181 23:43:40.952627 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 23:43:40.952709 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 23:43:40.960217 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 23:43:40.960352 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 23:43:40.960442 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 23:43:40.960527 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 23:43:40.960611 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 23:43:41.851623 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 23:43:41.851984 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 23:43:41.852095 extracting modules file /var/lib/lava/dispatcher/tmp/14172956/tftp-deploy-mv6oeqmu/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14172956/extract-overlay-ramdisk-nvj7w1cp/ramdisk
191 23:43:42.074364 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 23:43:42.074541 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 23:43:42.074632 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14172956/compress-overlay-mvp9j3af/overlay-1.5.2.4.tar.gz to ramdisk
194 23:43:42.074701 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14172956/compress-overlay-mvp9j3af/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14172956/extract-overlay-ramdisk-nvj7w1cp/ramdisk
195 23:43:42.081469 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 23:43:42.081607 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 23:43:42.081700 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 23:43:42.081791 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 23:43:42.081875 Building ramdisk /var/lib/lava/dispatcher/tmp/14172956/extract-overlay-ramdisk-nvj7w1cp/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14172956/extract-overlay-ramdisk-nvj7w1cp/ramdisk
200 23:43:42.817745 >> 275884 blocks
201 23:43:46.998594 rename /var/lib/lava/dispatcher/tmp/14172956/extract-overlay-ramdisk-nvj7w1cp/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14172956/tftp-deploy-mv6oeqmu/ramdisk/ramdisk.cpio.gz
202 23:43:46.999082 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 23:43:46.999215 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
204 23:43:46.999322 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
205 23:43:46.999428 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14172956/tftp-deploy-mv6oeqmu/kernel/Image']
206 23:44:01.218499 Returned 0 in 14 seconds
207 23:44:01.319133 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14172956/tftp-deploy-mv6oeqmu/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14172956/tftp-deploy-mv6oeqmu/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14172956/tftp-deploy-mv6oeqmu/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14172956/tftp-deploy-mv6oeqmu/kernel/image.itb
208 23:44:01.977386 output: FIT description: Kernel Image image with one or more FDT blobs
209 23:44:01.977745 output: Created: Wed Jun 5 00:44:01 2024
210 23:44:01.977821 output: Image 0 (kernel-1)
211 23:44:01.977884 output: Description:
212 23:44:01.977943 output: Created: Wed Jun 5 00:44:01 2024
213 23:44:01.978003 output: Type: Kernel Image
214 23:44:01.978062 output: Compression: lzma compressed
215 23:44:01.978121 output: Data Size: 13061430 Bytes = 12755.30 KiB = 12.46 MiB
216 23:44:01.978181 output: Architecture: AArch64
217 23:44:01.978238 output: OS: Linux
218 23:44:01.978299 output: Load Address: 0x00000000
219 23:44:01.978358 output: Entry Point: 0x00000000
220 23:44:01.978416 output: Hash algo: crc32
221 23:44:01.978475 output: Hash value: ecfb5096
222 23:44:01.978529 output: Image 1 (fdt-1)
223 23:44:01.978584 output: Description: mt8192-asurada-spherion-r0
224 23:44:01.978637 output: Created: Wed Jun 5 00:44:01 2024
225 23:44:01.978689 output: Type: Flat Device Tree
226 23:44:01.978742 output: Compression: uncompressed
227 23:44:01.978793 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 23:44:01.978846 output: Architecture: AArch64
229 23:44:01.978898 output: Hash algo: crc32
230 23:44:01.978950 output: Hash value: 0f8e4d2e
231 23:44:01.979002 output: Image 2 (ramdisk-1)
232 23:44:01.979053 output: Description: unavailable
233 23:44:01.979104 output: Created: Wed Jun 5 00:44:01 2024
234 23:44:01.979178 output: Type: RAMDisk Image
235 23:44:01.979231 output: Compression: Unknown Compression
236 23:44:01.979283 output: Data Size: 41207787 Bytes = 40241.98 KiB = 39.30 MiB
237 23:44:01.979337 output: Architecture: AArch64
238 23:44:01.979389 output: OS: Linux
239 23:44:01.979441 output: Load Address: unavailable
240 23:44:01.979494 output: Entry Point: unavailable
241 23:44:01.979546 output: Hash algo: crc32
242 23:44:01.979597 output: Hash value: 6c2e2d1f
243 23:44:01.979649 output: Default Configuration: 'conf-1'
244 23:44:01.979701 output: Configuration 0 (conf-1)
245 23:44:01.979752 output: Description: mt8192-asurada-spherion-r0
246 23:44:01.979804 output: Kernel: kernel-1
247 23:44:01.979856 output: Init Ramdisk: ramdisk-1
248 23:44:01.979908 output: FDT: fdt-1
249 23:44:01.979959 output: Loadables: kernel-1
250 23:44:01.980011 output:
251 23:44:01.980208 end: 1.5.8.1 prepare-fit (duration 00:00:15) [common]
252 23:44:01.980301 end: 1.5.8 prepare-kernel (duration 00:00:15) [common]
253 23:44:01.980404 end: 1.5 prepare-tftp-overlay (duration 00:00:21) [common]
254 23:44:01.980491 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:38) [common]
255 23:44:01.980569 No LXC device requested
256 23:44:01.980648 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 23:44:01.980729 start: 1.7 deploy-device-env (timeout 00:09:38) [common]
258 23:44:01.980804 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 23:44:01.980873 Checking files for TFTP limit of 4294967296 bytes.
260 23:44:01.981402 end: 1 tftp-deploy (duration 00:00:22) [common]
261 23:44:01.981507 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 23:44:01.981600 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 23:44:01.981719 substitutions:
264 23:44:01.981786 - {DTB}: 14172956/tftp-deploy-mv6oeqmu/dtb/mt8192-asurada-spherion-r0.dtb
265 23:44:01.981851 - {INITRD}: 14172956/tftp-deploy-mv6oeqmu/ramdisk/ramdisk.cpio.gz
266 23:44:01.981908 - {KERNEL}: 14172956/tftp-deploy-mv6oeqmu/kernel/Image
267 23:44:01.981965 - {LAVA_MAC}: None
268 23:44:01.982019 - {PRESEED_CONFIG}: None
269 23:44:01.982074 - {PRESEED_LOCAL}: None
270 23:44:01.982127 - {RAMDISK}: 14172956/tftp-deploy-mv6oeqmu/ramdisk/ramdisk.cpio.gz
271 23:44:01.982181 - {ROOT_PART}: None
272 23:44:01.982235 - {ROOT}: None
273 23:44:01.982288 - {SERVER_IP}: 192.168.201.1
274 23:44:01.982342 - {TEE}: None
275 23:44:01.982395 Parsed boot commands:
276 23:44:01.982448 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 23:44:01.982617 Parsed boot commands: tftpboot 192.168.201.1 14172956/tftp-deploy-mv6oeqmu/kernel/image.itb 14172956/tftp-deploy-mv6oeqmu/kernel/cmdline
278 23:44:01.982705 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 23:44:01.982794 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 23:44:01.982882 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 23:44:01.982970 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 23:44:01.983053 Not connected, no need to disconnect.
283 23:44:01.983131 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 23:44:01.983209 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 23:44:01.983276 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-3'
286 23:44:01.986833 Setting prompt string to ['lava-test: # ']
287 23:44:01.987192 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 23:44:01.987298 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 23:44:01.987395 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 23:44:01.987528 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 23:44:01.987757 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-3', '--port=1', '--command=reboot']
292 23:44:07.128719 >> Command sent successfully.
293 23:44:07.131522 Returned 0 in 5 seconds
294 23:44:07.231877 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 23:44:07.232188 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 23:44:07.232298 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 23:44:07.232394 Setting prompt string to 'Starting depthcharge on Spherion...'
299 23:44:07.232474 Changing prompt to 'Starting depthcharge on Spherion...'
300 23:44:07.232545 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 23:44:07.232948 [Enter `^Ec?' for help]
302 23:44:07.405726
303 23:44:07.405868
304 23:44:07.405934 F0: 102B 0000
305 23:44:07.405998
306 23:44:07.406057 F3: 1001 0000 [0200]
307 23:44:07.406116
308 23:44:07.409623 F3: 1001 0000
309 23:44:07.409736
310 23:44:07.409802 F7: 102D 0000
311 23:44:07.409863
312 23:44:07.409921 F1: 0000 0000
313 23:44:07.409978
314 23:44:07.413421 V0: 0000 0000 [0001]
315 23:44:07.413505
316 23:44:07.413570 00: 0007 8000
317 23:44:07.413636
318 23:44:07.416882 01: 0000 0000
319 23:44:07.416969
320 23:44:07.417057 BP: 0C00 0209 [0000]
321 23:44:07.417146
322 23:44:07.417203 G0: 1182 0000
323 23:44:07.420822
324 23:44:07.420905 EC: 0000 0021 [4000]
325 23:44:07.420971
326 23:44:07.424427 S7: 0000 0000 [0000]
327 23:44:07.424524
328 23:44:07.424588 CC: 0000 0000 [0001]
329 23:44:07.424649
330 23:44:07.427713 T0: 0000 0040 [010F]
331 23:44:07.427797
332 23:44:07.427861 Jump to BL
333 23:44:07.427922
334 23:44:07.452640
335 23:44:07.452758
336 23:44:07.460933 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
337 23:44:07.464095 ARM64: Exception handlers installed.
338 23:44:07.467602 ARM64: Testing exception
339 23:44:07.471378 ARM64: Done test exception
340 23:44:07.478762 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
341 23:44:07.485743 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
342 23:44:07.492561 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
343 23:44:07.503302 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
344 23:44:07.510398 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
345 23:44:07.520006 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
346 23:44:07.530429 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
347 23:44:07.537731 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
348 23:44:07.555431 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
349 23:44:07.558399 WDT: Last reset was cold boot
350 23:44:07.561569 SPI1(PAD0) initialized at 2873684 Hz
351 23:44:07.565053 SPI5(PAD0) initialized at 992727 Hz
352 23:44:07.568767 VBOOT: Loading verstage.
353 23:44:07.575080 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
354 23:44:07.578401 FMAP: Found "FLASH" version 1.1 at 0x20000.
355 23:44:07.581954 FMAP: base = 0x0 size = 0x800000 #areas = 25
356 23:44:07.585231 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
357 23:44:07.592638 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
358 23:44:07.599447 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
359 23:44:07.610349 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
360 23:44:07.610437
361 23:44:07.610503
362 23:44:07.620419 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
363 23:44:07.623838 ARM64: Exception handlers installed.
364 23:44:07.627235 ARM64: Testing exception
365 23:44:07.627349 ARM64: Done test exception
366 23:44:07.634137 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
367 23:44:07.637268 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
368 23:44:07.652577 Probing TPM: . done!
369 23:44:07.652662 TPM ready after 0 ms
370 23:44:07.659417 Connected to device vid:did:rid of 1ae0:0028:00
371 23:44:07.666518 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
372 23:44:07.725264 Initialized TPM device CR50 revision 0
373 23:44:07.736466 tlcl_send_startup: Startup return code is 0
374 23:44:07.736557 TPM: setup succeeded
375 23:44:07.747051 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
376 23:44:07.756340 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
377 23:44:07.767851 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
378 23:44:07.778161 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
379 23:44:07.781711 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
380 23:44:07.786161 in-header: 03 07 00 00 08 00 00 00
381 23:44:07.789807 in-data: aa e4 47 04 13 02 00 00
382 23:44:07.793504 Chrome EC: UHEPI supported
383 23:44:07.800839 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
384 23:44:07.804920 in-header: 03 ad 00 00 08 00 00 00
385 23:44:07.808571 in-data: 00 20 20 08 00 00 00 00
386 23:44:07.808654 Phase 1
387 23:44:07.812130 FMAP: area GBB found @ 3f5000 (12032 bytes)
388 23:44:07.819413 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
389 23:44:07.822796 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
390 23:44:07.826557 Recovery requested (1009000e)
391 23:44:07.835566 TPM: Extending digest for VBOOT: boot mode into PCR 0
392 23:44:07.840794 tlcl_extend: response is 0
393 23:44:07.849881 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
394 23:44:07.855764 tlcl_extend: response is 0
395 23:44:07.862843 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
396 23:44:07.882338 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
397 23:44:07.889475 BS: bootblock times (exec / console): total (unknown) / 148 ms
398 23:44:07.889594
399 23:44:07.889694
400 23:44:07.900315 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
401 23:44:07.903857 ARM64: Exception handlers installed.
402 23:44:07.903981 ARM64: Testing exception
403 23:44:07.906513 ARM64: Done test exception
404 23:44:07.927730 pmic_efuse_setting: Set efuses in 11 msecs
405 23:44:07.931552 pmwrap_interface_init: Select PMIF_VLD_RDY
406 23:44:07.938250 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
407 23:44:07.942033 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
408 23:44:07.944984 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
409 23:44:07.952271 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
410 23:44:07.956867 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
411 23:44:07.960068 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
412 23:44:07.967797 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
413 23:44:07.971037 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
414 23:44:07.974824 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
415 23:44:07.978491 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
416 23:44:07.986681 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
417 23:44:07.990521 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
418 23:44:07.994198 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
419 23:44:08.001144 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
420 23:44:08.005066 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
421 23:44:08.012444 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
422 23:44:08.016109 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
423 23:44:08.022837 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
424 23:44:08.030254 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
425 23:44:08.033704 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
426 23:44:08.041482 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
427 23:44:08.045917 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
428 23:44:08.052824 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
429 23:44:08.056543 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
430 23:44:08.060199 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
431 23:44:08.068091 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
432 23:44:08.071813 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
433 23:44:08.078319 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
434 23:44:08.082667 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
435 23:44:08.086010 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
436 23:44:08.093489 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
437 23:44:08.096520 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
438 23:44:08.100485 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
439 23:44:08.108044 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
440 23:44:08.111470 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
441 23:44:08.119319 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
442 23:44:08.122583 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
443 23:44:08.126141 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
444 23:44:08.130268 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
445 23:44:08.137693 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
446 23:44:08.141292 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
447 23:44:08.145117 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
448 23:44:08.148215 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
449 23:44:08.152254 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
450 23:44:08.155796 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
451 23:44:08.163824 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
452 23:44:08.167702 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
453 23:44:08.170797 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
454 23:44:08.174899 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
455 23:44:08.178606 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
456 23:44:08.182669 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
457 23:44:08.189610 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
458 23:44:08.200482 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
459 23:44:08.204361 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
460 23:44:08.211405 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
461 23:44:08.219003 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
462 23:44:08.225854 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
463 23:44:08.229913 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
464 23:44:08.233443 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 23:44:08.241036 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x12
466 23:44:08.244732 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
467 23:44:08.252811 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
468 23:44:08.256408 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
469 23:44:08.265530 [RTC]rtc_get_frequency_meter,154: input=15, output=789
470 23:44:08.275398 [RTC]rtc_get_frequency_meter,154: input=23, output=979
471 23:44:08.284432 [RTC]rtc_get_frequency_meter,154: input=19, output=884
472 23:44:08.294232 [RTC]rtc_get_frequency_meter,154: input=17, output=837
473 23:44:08.303471 [RTC]rtc_get_frequency_meter,154: input=16, output=813
474 23:44:08.313402 [RTC]rtc_get_frequency_meter,154: input=15, output=790
475 23:44:08.322779 [RTC]rtc_get_frequency_meter,154: input=16, output=812
476 23:44:08.326285 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
477 23:44:08.330334 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
478 23:44:08.333975 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
479 23:44:08.341891 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
480 23:44:08.345586 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
481 23:44:08.349018 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
482 23:44:08.352868 ADC[4]: Raw value=900959 ID=7
483 23:44:08.352996 ADC[3]: Raw value=213336 ID=1
484 23:44:08.356206 RAM Code: 0x71
485 23:44:08.360328 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
486 23:44:08.363944 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
487 23:44:08.375265 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
488 23:44:08.379394 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
489 23:44:08.382280 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
490 23:44:08.386319 in-header: 03 07 00 00 08 00 00 00
491 23:44:08.390647 in-data: aa e4 47 04 13 02 00 00
492 23:44:08.394437 Chrome EC: UHEPI supported
493 23:44:08.401426 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
494 23:44:08.405225 in-header: 03 ed 00 00 08 00 00 00
495 23:44:08.405323 in-data: 80 20 60 08 00 00 00 00
496 23:44:08.409300 MRC: failed to locate region type 0.
497 23:44:08.416236 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
498 23:44:08.420364 DRAM-K: Running full calibration
499 23:44:08.427547 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
500 23:44:08.427665 header.status = 0x0
501 23:44:08.431591 header.version = 0x6 (expected: 0x6)
502 23:44:08.434967 header.size = 0xd00 (expected: 0xd00)
503 23:44:08.435055 header.flags = 0x0
504 23:44:08.442114 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
505 23:44:08.460529 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
506 23:44:08.468239 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
507 23:44:08.471831 dram_init: ddr_geometry: 2
508 23:44:08.471918 [EMI] MDL number = 2
509 23:44:08.475147 [EMI] Get MDL freq = 0
510 23:44:08.475225 dram_init: ddr_type: 0
511 23:44:08.478956 is_discrete_lpddr4: 1
512 23:44:08.482856 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
513 23:44:08.482972
514 23:44:08.483065
515 23:44:08.483158 [Bian_co] ETT version 0.0.0.1
516 23:44:08.489629 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
517 23:44:08.489716
518 23:44:08.494060 dramc_set_vcore_voltage set vcore to 650000
519 23:44:08.494141 Read voltage for 800, 4
520 23:44:08.497333 Vio18 = 0
521 23:44:08.497423 Vcore = 650000
522 23:44:08.497512 Vdram = 0
523 23:44:08.500942 Vddq = 0
524 23:44:08.501030 Vmddr = 0
525 23:44:08.501114 dram_init: config_dvfs: 1
526 23:44:08.507643 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
527 23:44:08.511384 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
528 23:44:08.515425 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
529 23:44:08.519030 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
530 23:44:08.522095 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
531 23:44:08.528833 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
532 23:44:08.528926 MEM_TYPE=3, freq_sel=18
533 23:44:08.532128 sv_algorithm_assistance_LP4_1600
534 23:44:08.535858 ============ PULL DRAM RESETB DOWN ============
535 23:44:08.542856 ========== PULL DRAM RESETB DOWN end =========
536 23:44:08.545688 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
537 23:44:08.548851 ===================================
538 23:44:08.552436 LPDDR4 DRAM CONFIGURATION
539 23:44:08.555613 ===================================
540 23:44:08.555729 EX_ROW_EN[0] = 0x0
541 23:44:08.559596 EX_ROW_EN[1] = 0x0
542 23:44:08.559723 LP4Y_EN = 0x0
543 23:44:08.562346 WORK_FSP = 0x0
544 23:44:08.562425 WL = 0x2
545 23:44:08.565834 RL = 0x2
546 23:44:08.565907 BL = 0x2
547 23:44:08.569113 RPST = 0x0
548 23:44:08.572447 RD_PRE = 0x0
549 23:44:08.572547 WR_PRE = 0x1
550 23:44:08.576112 WR_PST = 0x0
551 23:44:08.576203 DBI_WR = 0x0
552 23:44:08.579004 DBI_RD = 0x0
553 23:44:08.579084 OTF = 0x1
554 23:44:08.582525 ===================================
555 23:44:08.586051 ===================================
556 23:44:08.586165 ANA top config
557 23:44:08.589170 ===================================
558 23:44:08.593045 DLL_ASYNC_EN = 0
559 23:44:08.595833 ALL_SLAVE_EN = 1
560 23:44:08.599224 NEW_RANK_MODE = 1
561 23:44:08.603002 DLL_IDLE_MODE = 1
562 23:44:08.603082 LP45_APHY_COMB_EN = 1
563 23:44:08.605926 TX_ODT_DIS = 1
564 23:44:08.609424 NEW_8X_MODE = 1
565 23:44:08.612710 ===================================
566 23:44:08.616139 ===================================
567 23:44:08.619886 data_rate = 1600
568 23:44:08.622996 CKR = 1
569 23:44:08.623079 DQ_P2S_RATIO = 8
570 23:44:08.626545 ===================================
571 23:44:08.629842 CA_P2S_RATIO = 8
572 23:44:08.632841 DQ_CA_OPEN = 0
573 23:44:08.636423 DQ_SEMI_OPEN = 0
574 23:44:08.639492 CA_SEMI_OPEN = 0
575 23:44:08.639611 CA_FULL_RATE = 0
576 23:44:08.643365 DQ_CKDIV4_EN = 1
577 23:44:08.646553 CA_CKDIV4_EN = 1
578 23:44:08.649972 CA_PREDIV_EN = 0
579 23:44:08.653091 PH8_DLY = 0
580 23:44:08.653194 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
581 23:44:08.656242 DQ_AAMCK_DIV = 4
582 23:44:08.659573 CA_AAMCK_DIV = 4
583 23:44:08.663639 CA_ADMCK_DIV = 4
584 23:44:08.666531 DQ_TRACK_CA_EN = 0
585 23:44:08.669619 CA_PICK = 800
586 23:44:08.672834 CA_MCKIO = 800
587 23:44:08.672912 MCKIO_SEMI = 0
588 23:44:08.676375 PLL_FREQ = 3068
589 23:44:08.680776 DQ_UI_PI_RATIO = 32
590 23:44:08.684175 CA_UI_PI_RATIO = 0
591 23:44:08.687590 ===================================
592 23:44:08.691709 ===================================
593 23:44:08.691785 memory_type:LPDDR4
594 23:44:08.695480 GP_NUM : 10
595 23:44:08.695559 SRAM_EN : 1
596 23:44:08.698874 MD32_EN : 0
597 23:44:08.702491 ===================================
598 23:44:08.702574 [ANA_INIT] >>>>>>>>>>>>>>
599 23:44:08.706465 <<<<<< [CONFIGURE PHASE]: ANA_TX
600 23:44:08.710400 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
601 23:44:08.714333 ===================================
602 23:44:08.717328 data_rate = 1600,PCW = 0X7600
603 23:44:08.720763 ===================================
604 23:44:08.724607 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
605 23:44:08.727274 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
606 23:44:08.733915 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 23:44:08.737836 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
608 23:44:08.740743 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
609 23:44:08.744306 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
610 23:44:08.747625 [ANA_INIT] flow start
611 23:44:08.751114 [ANA_INIT] PLL >>>>>>>>
612 23:44:08.751187 [ANA_INIT] PLL <<<<<<<<
613 23:44:08.754019 [ANA_INIT] MIDPI >>>>>>>>
614 23:44:08.757441 [ANA_INIT] MIDPI <<<<<<<<
615 23:44:08.757512 [ANA_INIT] DLL >>>>>>>>
616 23:44:08.760718 [ANA_INIT] flow end
617 23:44:08.764183 ============ LP4 DIFF to SE enter ============
618 23:44:08.767557 ============ LP4 DIFF to SE exit ============
619 23:44:08.770847 [ANA_INIT] <<<<<<<<<<<<<
620 23:44:08.774244 [Flow] Enable top DCM control >>>>>
621 23:44:08.777504 [Flow] Enable top DCM control <<<<<
622 23:44:08.780996 Enable DLL master slave shuffle
623 23:44:08.787728 ==============================================================
624 23:44:08.787808 Gating Mode config
625 23:44:08.794123 ==============================================================
626 23:44:08.794200 Config description:
627 23:44:08.804389 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
628 23:44:08.811268 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
629 23:44:08.817837 SELPH_MODE 0: By rank 1: By Phase
630 23:44:08.821241 ==============================================================
631 23:44:08.825188 GAT_TRACK_EN = 1
632 23:44:08.828077 RX_GATING_MODE = 2
633 23:44:08.831406 RX_GATING_TRACK_MODE = 2
634 23:44:08.835068 SELPH_MODE = 1
635 23:44:08.838272 PICG_EARLY_EN = 1
636 23:44:08.841296 VALID_LAT_VALUE = 1
637 23:44:08.844808 ==============================================================
638 23:44:08.848387 Enter into Gating configuration >>>>
639 23:44:08.851478 Exit from Gating configuration <<<<
640 23:44:08.854781 Enter into DVFS_PRE_config >>>>>
641 23:44:08.868701 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
642 23:44:08.868816 Exit from DVFS_PRE_config <<<<<
643 23:44:08.871584 Enter into PICG configuration >>>>
644 23:44:08.875426 Exit from PICG configuration <<<<
645 23:44:08.878302 [RX_INPUT] configuration >>>>>
646 23:44:08.881441 [RX_INPUT] configuration <<<<<
647 23:44:08.888271 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
648 23:44:08.891929 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
649 23:44:08.899360 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
650 23:44:08.905831 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
651 23:44:08.909456 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
652 23:44:08.916294 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
653 23:44:08.919644 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
654 23:44:08.926401 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
655 23:44:08.929445 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
656 23:44:08.932792 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
657 23:44:08.936126 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
658 23:44:08.943148 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
659 23:44:08.946304 ===================================
660 23:44:08.946380 LPDDR4 DRAM CONFIGURATION
661 23:44:08.949826 ===================================
662 23:44:08.953012 EX_ROW_EN[0] = 0x0
663 23:44:08.956179 EX_ROW_EN[1] = 0x0
664 23:44:08.956288 LP4Y_EN = 0x0
665 23:44:08.959772 WORK_FSP = 0x0
666 23:44:08.959851 WL = 0x2
667 23:44:08.963084 RL = 0x2
668 23:44:08.963167 BL = 0x2
669 23:44:08.966851 RPST = 0x0
670 23:44:08.966925 RD_PRE = 0x0
671 23:44:08.969993 WR_PRE = 0x1
672 23:44:08.970067 WR_PST = 0x0
673 23:44:08.973142 DBI_WR = 0x0
674 23:44:08.973216 DBI_RD = 0x0
675 23:44:08.976525 OTF = 0x1
676 23:44:08.980128 ===================================
677 23:44:08.982994 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
678 23:44:08.986559 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
679 23:44:08.990123 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
680 23:44:08.993182 ===================================
681 23:44:08.996508 LPDDR4 DRAM CONFIGURATION
682 23:44:09.000339 ===================================
683 23:44:09.003347 EX_ROW_EN[0] = 0x10
684 23:44:09.003428 EX_ROW_EN[1] = 0x0
685 23:44:09.006570 LP4Y_EN = 0x0
686 23:44:09.006655 WORK_FSP = 0x0
687 23:44:09.010271 WL = 0x2
688 23:44:09.010349 RL = 0x2
689 23:44:09.013571 BL = 0x2
690 23:44:09.013650 RPST = 0x0
691 23:44:09.016811 RD_PRE = 0x0
692 23:44:09.016908 WR_PRE = 0x1
693 23:44:09.020138 WR_PST = 0x0
694 23:44:09.020214 DBI_WR = 0x0
695 23:44:09.023052 DBI_RD = 0x0
696 23:44:09.026807 OTF = 0x1
697 23:44:09.029775 ===================================
698 23:44:09.033014 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
699 23:44:09.038351 nWR fixed to 40
700 23:44:09.042046 [ModeRegInit_LP4] CH0 RK0
701 23:44:09.042152 [ModeRegInit_LP4] CH0 RK1
702 23:44:09.044951 [ModeRegInit_LP4] CH1 RK0
703 23:44:09.048516 [ModeRegInit_LP4] CH1 RK1
704 23:44:09.048588 match AC timing 13
705 23:44:09.054997 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
706 23:44:09.058408 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
707 23:44:09.062169 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
708 23:44:09.068493 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
709 23:44:09.071948 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
710 23:44:09.072020 [EMI DOE] emi_dcm 0
711 23:44:09.078958 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
712 23:44:09.079039 ==
713 23:44:09.082108 Dram Type= 6, Freq= 0, CH_0, rank 0
714 23:44:09.085589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
715 23:44:09.085664 ==
716 23:44:09.092238 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
717 23:44:09.095344 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
718 23:44:09.105778 [CA 0] Center 37 (7~68) winsize 62
719 23:44:09.109436 [CA 1] Center 37 (6~68) winsize 63
720 23:44:09.112475 [CA 2] Center 35 (5~66) winsize 62
721 23:44:09.115901 [CA 3] Center 35 (4~66) winsize 63
722 23:44:09.119212 [CA 4] Center 34 (3~65) winsize 63
723 23:44:09.122938 [CA 5] Center 33 (3~64) winsize 62
724 23:44:09.123020
725 23:44:09.125633 [CmdBusTrainingLP45] Vref(ca) range 1: 34
726 23:44:09.125714
727 23:44:09.129227 [CATrainingPosCal] consider 1 rank data
728 23:44:09.132369 u2DelayCellTimex100 = 270/100 ps
729 23:44:09.136192 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
730 23:44:09.139454 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
731 23:44:09.142474 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
732 23:44:09.149218 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
733 23:44:09.152672 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
734 23:44:09.155905 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
735 23:44:09.155978
736 23:44:09.159193 CA PerBit enable=1, Macro0, CA PI delay=33
737 23:44:09.159274
738 23:44:09.162585 [CBTSetCACLKResult] CA Dly = 33
739 23:44:09.162657 CS Dly: 5 (0~36)
740 23:44:09.162718 ==
741 23:44:09.166160 Dram Type= 6, Freq= 0, CH_0, rank 1
742 23:44:09.173176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
743 23:44:09.173249 ==
744 23:44:09.176011 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
745 23:44:09.182508 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
746 23:44:09.192533 [CA 0] Center 37 (6~68) winsize 63
747 23:44:09.195565 [CA 1] Center 37 (7~68) winsize 62
748 23:44:09.198949 [CA 2] Center 35 (5~66) winsize 62
749 23:44:09.202713 [CA 3] Center 35 (4~66) winsize 63
750 23:44:09.205478 [CA 4] Center 34 (4~65) winsize 62
751 23:44:09.208955 [CA 5] Center 33 (3~64) winsize 62
752 23:44:09.209053
753 23:44:09.212518 [CmdBusTrainingLP45] Vref(ca) range 1: 34
754 23:44:09.212596
755 23:44:09.215880 [CATrainingPosCal] consider 2 rank data
756 23:44:09.218949 u2DelayCellTimex100 = 270/100 ps
757 23:44:09.222193 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
758 23:44:09.225676 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
759 23:44:09.228971 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
760 23:44:09.236030 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
761 23:44:09.239591 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
762 23:44:09.242439 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
763 23:44:09.242523
764 23:44:09.246169 CA PerBit enable=1, Macro0, CA PI delay=33
765 23:44:09.246272
766 23:44:09.249394 [CBTSetCACLKResult] CA Dly = 33
767 23:44:09.249469 CS Dly: 5 (0~37)
768 23:44:09.249536
769 23:44:09.252784 ----->DramcWriteLeveling(PI) begin...
770 23:44:09.252861 ==
771 23:44:09.256022 Dram Type= 6, Freq= 0, CH_0, rank 0
772 23:44:09.263595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
773 23:44:09.263672 ==
774 23:44:09.263736 Write leveling (Byte 0): 28 => 28
775 23:44:09.266964 Write leveling (Byte 1): 27 => 27
776 23:44:09.270463 DramcWriteLeveling(PI) end<-----
777 23:44:09.270545
778 23:44:09.270609 ==
779 23:44:09.274449 Dram Type= 6, Freq= 0, CH_0, rank 0
780 23:44:09.278082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 23:44:09.278171 ==
782 23:44:09.281185 [Gating] SW mode calibration
783 23:44:09.288105 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
784 23:44:09.295373 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
785 23:44:09.298533 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
786 23:44:09.302018 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 23:44:09.305602 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
788 23:44:09.312116 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
789 23:44:09.315330 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 23:44:09.318954 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 23:44:09.325768 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 23:44:09.328958 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 23:44:09.332419 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 23:44:09.338844 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 23:44:09.342522 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 23:44:09.345563 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 23:44:09.352291 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 23:44:09.355782 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 23:44:09.359629 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 23:44:09.362641 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 23:44:09.369372 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 23:44:09.372586 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 23:44:09.376094 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
804 23:44:09.382599 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
805 23:44:09.385770 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 23:44:09.389267 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 23:44:09.396172 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 23:44:09.399647 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 23:44:09.402617 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 23:44:09.409557 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 23:44:09.412589 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 23:44:09.416159 0 9 12 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
813 23:44:09.419415 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 23:44:09.426481 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 23:44:09.429445 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 23:44:09.433024 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 23:44:09.439567 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 23:44:09.443227 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 23:44:09.446169 0 10 8 | B1->B0 | 3434 3131 | 1 0 | (1 0) (1 0)
820 23:44:09.452937 0 10 12 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
821 23:44:09.456228 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 23:44:09.459782 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 23:44:09.466126 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 23:44:09.469538 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 23:44:09.472980 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 23:44:09.479725 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 23:44:09.483470 0 11 8 | B1->B0 | 2424 2c2c | 0 0 | (0 0) (0 0)
828 23:44:09.486960 0 11 12 | B1->B0 | 3636 4444 | 0 0 | (0 0) (0 0)
829 23:44:09.489987 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 23:44:09.496910 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 23:44:09.500012 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 23:44:09.503620 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 23:44:09.510315 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 23:44:09.513162 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 23:44:09.516795 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
836 23:44:09.523911 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 23:44:09.526907 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 23:44:09.530164 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 23:44:09.536962 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 23:44:09.540280 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 23:44:09.543192 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 23:44:09.550376 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 23:44:09.553527 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 23:44:09.557076 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 23:44:09.559907 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 23:44:09.567129 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 23:44:09.569942 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 23:44:09.573385 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 23:44:09.580042 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 23:44:09.583412 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 23:44:09.587059 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 23:44:09.593689 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
853 23:44:09.593772 Total UI for P1: 0, mck2ui 16
854 23:44:09.600241 best dqsien dly found for B0: ( 0, 14, 10)
855 23:44:09.603720 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
856 23:44:09.606864 Total UI for P1: 0, mck2ui 16
857 23:44:09.610275 best dqsien dly found for B1: ( 0, 14, 12)
858 23:44:09.614088 best DQS0 dly(MCK, UI, PI) = (0, 14, 10)
859 23:44:09.616794 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
860 23:44:09.616898
861 23:44:09.620312 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 10)
862 23:44:09.623445 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
863 23:44:09.626821 [Gating] SW calibration Done
864 23:44:09.626899 ==
865 23:44:09.630202 Dram Type= 6, Freq= 0, CH_0, rank 0
866 23:44:09.633730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 23:44:09.633816 ==
868 23:44:09.637183 RX Vref Scan: 0
869 23:44:09.637263
870 23:44:09.640504 RX Vref 0 -> 0, step: 1
871 23:44:09.640584
872 23:44:09.640668 RX Delay -130 -> 252, step: 16
873 23:44:09.647031 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
874 23:44:09.651051 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
875 23:44:09.654325 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
876 23:44:09.657346 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
877 23:44:09.660687 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
878 23:44:09.667483 iDelay=206, Bit 5, Center 69 (-50 ~ 189) 240
879 23:44:09.670662 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
880 23:44:09.673788 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
881 23:44:09.677384 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
882 23:44:09.680957 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
883 23:44:09.687269 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
884 23:44:09.690646 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
885 23:44:09.694083 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
886 23:44:09.697386 iDelay=206, Bit 13, Center 77 (-34 ~ 189) 224
887 23:44:09.700529 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
888 23:44:09.707985 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
889 23:44:09.708096 ==
890 23:44:09.711182 Dram Type= 6, Freq= 0, CH_0, rank 0
891 23:44:09.714242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 23:44:09.714327 ==
893 23:44:09.714391 DQS Delay:
894 23:44:09.717658 DQS0 = 0, DQS1 = 0
895 23:44:09.717767 DQM Delay:
896 23:44:09.720925 DQM0 = 85, DQM1 = 78
897 23:44:09.721039 DQ Delay:
898 23:44:09.724406 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
899 23:44:09.727748 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
900 23:44:09.731327 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
901 23:44:09.734213 DQ12 =85, DQ13 =77, DQ14 =85, DQ15 =93
902 23:44:09.734304
903 23:44:09.734389
904 23:44:09.734469 ==
905 23:44:09.737777 Dram Type= 6, Freq= 0, CH_0, rank 0
906 23:44:09.741149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 23:44:09.741232 ==
908 23:44:09.741339
909 23:44:09.741430
910 23:44:09.745044 TX Vref Scan disable
911 23:44:09.748110 == TX Byte 0 ==
912 23:44:09.751312 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
913 23:44:09.755319 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
914 23:44:09.755435 == TX Byte 1 ==
915 23:44:09.761674 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
916 23:44:09.764979 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
917 23:44:09.765065 ==
918 23:44:09.768121 Dram Type= 6, Freq= 0, CH_0, rank 0
919 23:44:09.771488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 23:44:09.771567 ==
921 23:44:09.786103 TX Vref=22, minBit 0, minWin=27, winSum=435
922 23:44:09.789636 TX Vref=24, minBit 13, minWin=26, winSum=435
923 23:44:09.792548 TX Vref=26, minBit 5, minWin=27, winSum=442
924 23:44:09.795808 TX Vref=28, minBit 13, minWin=26, winSum=444
925 23:44:09.799786 TX Vref=30, minBit 10, minWin=27, winSum=452
926 23:44:09.806414 TX Vref=32, minBit 8, minWin=27, winSum=445
927 23:44:09.809476 [TxChooseVref] Worse bit 10, Min win 27, Win sum 452, Final Vref 30
928 23:44:09.809558
929 23:44:09.813073 Final TX Range 1 Vref 30
930 23:44:09.813164
931 23:44:09.813230 ==
932 23:44:09.816013 Dram Type= 6, Freq= 0, CH_0, rank 0
933 23:44:09.819241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 23:44:09.819323 ==
935 23:44:09.819390
936 23:44:09.822579
937 23:44:09.822659 TX Vref Scan disable
938 23:44:09.826356 == TX Byte 0 ==
939 23:44:09.829909 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
940 23:44:09.832896 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
941 23:44:09.836318 == TX Byte 1 ==
942 23:44:09.839944 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
943 23:44:09.842895 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
944 23:44:09.842978
945 23:44:09.846102 [DATLAT]
946 23:44:09.846178 Freq=800, CH0 RK0
947 23:44:09.846257
948 23:44:09.849469 DATLAT Default: 0xa
949 23:44:09.849545 0, 0xFFFF, sum = 0
950 23:44:09.853168 1, 0xFFFF, sum = 0
951 23:44:09.853246 2, 0xFFFF, sum = 0
952 23:44:09.856586 3, 0xFFFF, sum = 0
953 23:44:09.856676 4, 0xFFFF, sum = 0
954 23:44:09.859721 5, 0xFFFF, sum = 0
955 23:44:09.859798 6, 0xFFFF, sum = 0
956 23:44:09.863137 7, 0xFFFF, sum = 0
957 23:44:09.863215 8, 0xFFFF, sum = 0
958 23:44:09.866466 9, 0x0, sum = 1
959 23:44:09.866552 10, 0x0, sum = 2
960 23:44:09.869549 11, 0x0, sum = 3
961 23:44:09.869635 12, 0x0, sum = 4
962 23:44:09.872882 best_step = 10
963 23:44:09.872960
964 23:44:09.873035 ==
965 23:44:09.876607 Dram Type= 6, Freq= 0, CH_0, rank 0
966 23:44:09.879932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 23:44:09.880036 ==
968 23:44:09.883570 RX Vref Scan: 1
969 23:44:09.883652
970 23:44:09.883746 Set Vref Range= 32 -> 127
971 23:44:09.883806
972 23:44:09.886416 RX Vref 32 -> 127, step: 1
973 23:44:09.886488
974 23:44:09.889984 RX Delay -95 -> 252, step: 8
975 23:44:09.890054
976 23:44:09.893387 Set Vref, RX VrefLevel [Byte0]: 32
977 23:44:09.896839 [Byte1]: 32
978 23:44:09.896921
979 23:44:09.901084 Set Vref, RX VrefLevel [Byte0]: 33
980 23:44:09.904337 [Byte1]: 33
981 23:44:09.904413
982 23:44:09.907212 Set Vref, RX VrefLevel [Byte0]: 34
983 23:44:09.910306 [Byte1]: 34
984 23:44:09.914152
985 23:44:09.914231 Set Vref, RX VrefLevel [Byte0]: 35
986 23:44:09.917191 [Byte1]: 35
987 23:44:09.921512
988 23:44:09.921592 Set Vref, RX VrefLevel [Byte0]: 36
989 23:44:09.924820 [Byte1]: 36
990 23:44:09.929409
991 23:44:09.929486 Set Vref, RX VrefLevel [Byte0]: 37
992 23:44:09.933017 [Byte1]: 37
993 23:44:09.937471
994 23:44:09.937554 Set Vref, RX VrefLevel [Byte0]: 38
995 23:44:09.940200 [Byte1]: 38
996 23:44:09.944914
997 23:44:09.945023 Set Vref, RX VrefLevel [Byte0]: 39
998 23:44:09.948602 [Byte1]: 39
999 23:44:09.952407
1000 23:44:09.952483 Set Vref, RX VrefLevel [Byte0]: 40
1001 23:44:09.955764 [Byte1]: 40
1002 23:44:09.960219
1003 23:44:09.960295 Set Vref, RX VrefLevel [Byte0]: 41
1004 23:44:09.963062 [Byte1]: 41
1005 23:44:09.967036
1006 23:44:09.967118 Set Vref, RX VrefLevel [Byte0]: 42
1007 23:44:09.970698 [Byte1]: 42
1008 23:44:09.974580
1009 23:44:09.974656 Set Vref, RX VrefLevel [Byte0]: 43
1010 23:44:09.978090 [Byte1]: 43
1011 23:44:09.982510
1012 23:44:09.982595 Set Vref, RX VrefLevel [Byte0]: 44
1013 23:44:09.985860 [Byte1]: 44
1014 23:44:09.990046
1015 23:44:09.990129 Set Vref, RX VrefLevel [Byte0]: 45
1016 23:44:09.992943 [Byte1]: 45
1017 23:44:09.997653
1018 23:44:09.997742 Set Vref, RX VrefLevel [Byte0]: 46
1019 23:44:10.001275 [Byte1]: 46
1020 23:44:10.005197
1021 23:44:10.005277 Set Vref, RX VrefLevel [Byte0]: 47
1022 23:44:10.008796 [Byte1]: 47
1023 23:44:10.012584
1024 23:44:10.012665 Set Vref, RX VrefLevel [Byte0]: 48
1025 23:44:10.015912 [Byte1]: 48
1026 23:44:10.020306
1027 23:44:10.020385 Set Vref, RX VrefLevel [Byte0]: 49
1028 23:44:10.023978 [Byte1]: 49
1029 23:44:10.028019
1030 23:44:10.028099 Set Vref, RX VrefLevel [Byte0]: 50
1031 23:44:10.031340 [Byte1]: 50
1032 23:44:10.035787
1033 23:44:10.035862 Set Vref, RX VrefLevel [Byte0]: 51
1034 23:44:10.039014 [Byte1]: 51
1035 23:44:10.043170
1036 23:44:10.043249 Set Vref, RX VrefLevel [Byte0]: 52
1037 23:44:10.046230 [Byte1]: 52
1038 23:44:10.050860
1039 23:44:10.050933 Set Vref, RX VrefLevel [Byte0]: 53
1040 23:44:10.054294 [Byte1]: 53
1041 23:44:10.058353
1042 23:44:10.058434 Set Vref, RX VrefLevel [Byte0]: 54
1043 23:44:10.061772 [Byte1]: 54
1044 23:44:10.065847
1045 23:44:10.065928 Set Vref, RX VrefLevel [Byte0]: 55
1046 23:44:10.069617 [Byte1]: 55
1047 23:44:10.073566
1048 23:44:10.073647 Set Vref, RX VrefLevel [Byte0]: 56
1049 23:44:10.077118 [Byte1]: 56
1050 23:44:10.081551
1051 23:44:10.081632 Set Vref, RX VrefLevel [Byte0]: 57
1052 23:44:10.084739 [Byte1]: 57
1053 23:44:10.088914
1054 23:44:10.089004 Set Vref, RX VrefLevel [Byte0]: 58
1055 23:44:10.091943 [Byte1]: 58
1056 23:44:10.096251
1057 23:44:10.096332 Set Vref, RX VrefLevel [Byte0]: 59
1058 23:44:10.099821 [Byte1]: 59
1059 23:44:10.103705
1060 23:44:10.103785 Set Vref, RX VrefLevel [Byte0]: 60
1061 23:44:10.107208 [Byte1]: 60
1062 23:44:10.111327
1063 23:44:10.111407 Set Vref, RX VrefLevel [Byte0]: 61
1064 23:44:10.114837 [Byte1]: 61
1065 23:44:10.119345
1066 23:44:10.119425 Set Vref, RX VrefLevel [Byte0]: 62
1067 23:44:10.122758 [Byte1]: 62
1068 23:44:10.126523
1069 23:44:10.126600 Set Vref, RX VrefLevel [Byte0]: 63
1070 23:44:10.129900 [Byte1]: 63
1071 23:44:10.134712
1072 23:44:10.134787 Set Vref, RX VrefLevel [Byte0]: 64
1073 23:44:10.137665 [Byte1]: 64
1074 23:44:10.141900
1075 23:44:10.141970 Set Vref, RX VrefLevel [Byte0]: 65
1076 23:44:10.145211 [Byte1]: 65
1077 23:44:10.149195
1078 23:44:10.149290 Set Vref, RX VrefLevel [Byte0]: 66
1079 23:44:10.152879 [Byte1]: 66
1080 23:44:10.156933
1081 23:44:10.157031 Set Vref, RX VrefLevel [Byte0]: 67
1082 23:44:10.160137 [Byte1]: 67
1083 23:44:10.164423
1084 23:44:10.164528 Set Vref, RX VrefLevel [Byte0]: 68
1085 23:44:10.168199 [Byte1]: 68
1086 23:44:10.172120
1087 23:44:10.172202 Set Vref, RX VrefLevel [Byte0]: 69
1088 23:44:10.175608 [Byte1]: 69
1089 23:44:10.179706
1090 23:44:10.179785 Set Vref, RX VrefLevel [Byte0]: 70
1091 23:44:10.183114 [Byte1]: 70
1092 23:44:10.187326
1093 23:44:10.187405 Set Vref, RX VrefLevel [Byte0]: 71
1094 23:44:10.190704 [Byte1]: 71
1095 23:44:10.195064
1096 23:44:10.195149 Set Vref, RX VrefLevel [Byte0]: 72
1097 23:44:10.198154 [Byte1]: 72
1098 23:44:10.203378
1099 23:44:10.203552 Set Vref, RX VrefLevel [Byte0]: 73
1100 23:44:10.206087 [Byte1]: 73
1101 23:44:10.210173
1102 23:44:10.210341 Set Vref, RX VrefLevel [Byte0]: 74
1103 23:44:10.213495 [Byte1]: 74
1104 23:44:10.218005
1105 23:44:10.218183 Set Vref, RX VrefLevel [Byte0]: 75
1106 23:44:10.221539 [Byte1]: 75
1107 23:44:10.225737
1108 23:44:10.225957 Set Vref, RX VrefLevel [Byte0]: 76
1109 23:44:10.229011 [Byte1]: 76
1110 23:44:10.233595
1111 23:44:10.233818 Final RX Vref Byte 0 = 58 to rank0
1112 23:44:10.236448 Final RX Vref Byte 1 = 58 to rank0
1113 23:44:10.240400 Final RX Vref Byte 0 = 58 to rank1
1114 23:44:10.243800 Final RX Vref Byte 1 = 58 to rank1==
1115 23:44:10.247153 Dram Type= 6, Freq= 0, CH_0, rank 0
1116 23:44:10.250576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1117 23:44:10.253477 ==
1118 23:44:10.253975 DQS Delay:
1119 23:44:10.254381 DQS0 = 0, DQS1 = 0
1120 23:44:10.257030 DQM Delay:
1121 23:44:10.257502 DQM0 = 86, DQM1 = 78
1122 23:44:10.260282 DQ Delay:
1123 23:44:10.260835 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =84
1124 23:44:10.263687 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =92
1125 23:44:10.266727 DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =76
1126 23:44:10.270434 DQ12 =84, DQ13 =80, DQ14 =88, DQ15 =88
1127 23:44:10.270983
1128 23:44:10.273614
1129 23:44:10.280249 [DQSOSCAuto] RK0, (LSB)MR18= 0x270e, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 400 ps
1130 23:44:10.283654 CH0 RK0: MR19=606, MR18=270E
1131 23:44:10.290538 CH0_RK0: MR19=0x606, MR18=0x270E, DQSOSC=400, MR23=63, INC=92, DEC=61
1132 23:44:10.290985
1133 23:44:10.293704 ----->DramcWriteLeveling(PI) begin...
1134 23:44:10.294122 ==
1135 23:44:10.297456 Dram Type= 6, Freq= 0, CH_0, rank 1
1136 23:44:10.300687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1137 23:44:10.301210 ==
1138 23:44:10.304104 Write leveling (Byte 0): 31 => 31
1139 23:44:10.307111 Write leveling (Byte 1): 30 => 30
1140 23:44:10.310533 DramcWriteLeveling(PI) end<-----
1141 23:44:10.310980
1142 23:44:10.311306 ==
1143 23:44:10.313824 Dram Type= 6, Freq= 0, CH_0, rank 1
1144 23:44:10.317389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1145 23:44:10.317839 ==
1146 23:44:10.320577 [Gating] SW mode calibration
1147 23:44:10.327424 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1148 23:44:10.330683 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1149 23:44:10.337279 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1150 23:44:10.381573 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1151 23:44:10.382154 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1152 23:44:10.382675 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1153 23:44:10.383547 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 23:44:10.384079 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 23:44:10.384562 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 23:44:10.385062 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 23:44:10.385551 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 23:44:10.386006 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 23:44:10.386500 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 23:44:10.390925 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 23:44:10.394193 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 23:44:10.394484 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 23:44:10.397653 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 23:44:10.401060 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 23:44:10.407701 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1166 23:44:10.411064 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1167 23:44:10.414472 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1168 23:44:10.420755 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 23:44:10.424304 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 23:44:10.427180 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 23:44:10.434228 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 23:44:10.437426 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 23:44:10.440877 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 23:44:10.447535 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 23:44:10.451312 0 9 8 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
1176 23:44:10.454253 0 9 12 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
1177 23:44:10.461254 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1178 23:44:10.464155 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 23:44:10.468003 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 23:44:10.471177 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 23:44:10.478084 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 23:44:10.480929 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
1183 23:44:10.484145 0 10 8 | B1->B0 | 3131 2626 | 0 0 | (0 1) (0 0)
1184 23:44:10.491046 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1185 23:44:10.494646 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 23:44:10.497956 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 23:44:10.504464 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 23:44:10.507768 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 23:44:10.511414 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 23:44:10.515070 0 11 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 1)
1191 23:44:10.522991 0 11 8 | B1->B0 | 2b2a 4141 | 1 0 | (0 0) (0 0)
1192 23:44:10.527087 0 11 12 | B1->B0 | 3c3c 4646 | 0 0 | (1 1) (0 0)
1193 23:44:10.530075 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 23:44:10.533474 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 23:44:10.537113 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 23:44:10.543715 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 23:44:10.547500 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 23:44:10.551095 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 23:44:10.557136 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1200 23:44:10.560697 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1201 23:44:10.563789 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 23:44:10.571094 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 23:44:10.574343 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 23:44:10.577758 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 23:44:10.580765 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 23:44:10.587897 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 23:44:10.590638 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 23:44:10.594158 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 23:44:10.600855 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 23:44:10.604243 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 23:44:10.607926 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 23:44:10.614412 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 23:44:10.617892 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 23:44:10.621137 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1215 23:44:10.627955 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1216 23:44:10.628036 Total UI for P1: 0, mck2ui 16
1217 23:44:10.631395 best dqsien dly found for B0: ( 0, 14, 4)
1218 23:44:10.637750 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1219 23:44:10.641506 Total UI for P1: 0, mck2ui 16
1220 23:44:10.644561 best dqsien dly found for B1: ( 0, 14, 8)
1221 23:44:10.647968 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1222 23:44:10.651685 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1223 23:44:10.651765
1224 23:44:10.654372 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1225 23:44:10.657927 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1226 23:44:10.661199 [Gating] SW calibration Done
1227 23:44:10.661274 ==
1228 23:44:10.664785 Dram Type= 6, Freq= 0, CH_0, rank 1
1229 23:44:10.668372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1230 23:44:10.668447 ==
1231 23:44:10.671117 RX Vref Scan: 0
1232 23:44:10.671187
1233 23:44:10.671250 RX Vref 0 -> 0, step: 1
1234 23:44:10.671308
1235 23:44:10.674821 RX Delay -130 -> 252, step: 16
1236 23:44:10.678075 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1237 23:44:10.684719 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1238 23:44:10.688160 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1239 23:44:10.691156 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1240 23:44:10.694642 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1241 23:44:10.697878 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1242 23:44:10.704869 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1243 23:44:10.708449 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1244 23:44:10.711563 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1245 23:44:10.715211 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1246 23:44:10.718121 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1247 23:44:10.724894 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1248 23:44:10.728634 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1249 23:44:10.731546 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1250 23:44:10.735548 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1251 23:44:10.738450 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1252 23:44:10.741910 ==
1253 23:44:10.741991 Dram Type= 6, Freq= 0, CH_0, rank 1
1254 23:44:10.748630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1255 23:44:10.748741 ==
1256 23:44:10.748838 DQS Delay:
1257 23:44:10.752044 DQS0 = 0, DQS1 = 0
1258 23:44:10.752125 DQM Delay:
1259 23:44:10.755137 DQM0 = 87, DQM1 = 76
1260 23:44:10.755243 DQ Delay:
1261 23:44:10.758777 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1262 23:44:10.761617 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =101
1263 23:44:10.765008 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1264 23:44:10.768316 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1265 23:44:10.768425
1266 23:44:10.768517
1267 23:44:10.768614 ==
1268 23:44:10.771842 Dram Type= 6, Freq= 0, CH_0, rank 1
1269 23:44:10.775450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1270 23:44:10.775560 ==
1271 23:44:10.775658
1272 23:44:10.775747
1273 23:44:10.778415 TX Vref Scan disable
1274 23:44:10.781781 == TX Byte 0 ==
1275 23:44:10.785343 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1276 23:44:10.788878 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1277 23:44:10.789052 == TX Byte 1 ==
1278 23:44:10.795262 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1279 23:44:10.799076 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1280 23:44:10.799181 ==
1281 23:44:10.802240 Dram Type= 6, Freq= 0, CH_0, rank 1
1282 23:44:10.805945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1283 23:44:10.806028 ==
1284 23:44:10.820056 TX Vref=22, minBit 5, minWin=27, winSum=445
1285 23:44:10.822887 TX Vref=24, minBit 9, minWin=27, winSum=450
1286 23:44:10.826349 TX Vref=26, minBit 9, minWin=27, winSum=452
1287 23:44:10.829830 TX Vref=28, minBit 4, minWin=28, winSum=454
1288 23:44:10.833340 TX Vref=30, minBit 4, minWin=28, winSum=456
1289 23:44:10.836867 TX Vref=32, minBit 3, minWin=28, winSum=455
1290 23:44:10.843242 [TxChooseVref] Worse bit 4, Min win 28, Win sum 456, Final Vref 30
1291 23:44:10.843344
1292 23:44:10.846608 Final TX Range 1 Vref 30
1293 23:44:10.846681
1294 23:44:10.846741 ==
1295 23:44:10.849678 Dram Type= 6, Freq= 0, CH_0, rank 1
1296 23:44:10.853344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1297 23:44:10.853420 ==
1298 23:44:10.853481
1299 23:44:10.853537
1300 23:44:10.856631 TX Vref Scan disable
1301 23:44:10.859994 == TX Byte 0 ==
1302 23:44:10.863542 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1303 23:44:10.866817 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1304 23:44:10.870137 == TX Byte 1 ==
1305 23:44:10.873703 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1306 23:44:10.876775 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1307 23:44:10.876842
1308 23:44:10.880155 [DATLAT]
1309 23:44:10.880224 Freq=800, CH0 RK1
1310 23:44:10.880283
1311 23:44:10.883447 DATLAT Default: 0xa
1312 23:44:10.883526 0, 0xFFFF, sum = 0
1313 23:44:10.886796 1, 0xFFFF, sum = 0
1314 23:44:10.886880 2, 0xFFFF, sum = 0
1315 23:44:10.889851 3, 0xFFFF, sum = 0
1316 23:44:10.889931 4, 0xFFFF, sum = 0
1317 23:44:10.893173 5, 0xFFFF, sum = 0
1318 23:44:10.893253 6, 0xFFFF, sum = 0
1319 23:44:10.896684 7, 0xFFFF, sum = 0
1320 23:44:10.896764 8, 0xFFFF, sum = 0
1321 23:44:10.899912 9, 0x0, sum = 1
1322 23:44:10.900013 10, 0x0, sum = 2
1323 23:44:10.903356 11, 0x0, sum = 3
1324 23:44:10.903436 12, 0x0, sum = 4
1325 23:44:10.906675 best_step = 10
1326 23:44:10.906774
1327 23:44:10.906861 ==
1328 23:44:10.910297 Dram Type= 6, Freq= 0, CH_0, rank 1
1329 23:44:10.913778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1330 23:44:10.913862 ==
1331 23:44:10.913924 RX Vref Scan: 0
1332 23:44:10.916789
1333 23:44:10.916889 RX Vref 0 -> 0, step: 1
1334 23:44:10.916983
1335 23:44:10.920249 RX Delay -95 -> 252, step: 8
1336 23:44:10.923448 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1337 23:44:10.930192 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1338 23:44:10.933694 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1339 23:44:10.937079 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1340 23:44:10.940891 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1341 23:44:10.943794 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1342 23:44:10.950838 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1343 23:44:10.953709 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1344 23:44:10.956811 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1345 23:44:10.960376 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1346 23:44:10.963821 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1347 23:44:10.970762 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1348 23:44:10.974017 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1349 23:44:10.977258 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1350 23:44:10.980645 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1351 23:44:10.984366 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1352 23:44:10.984447 ==
1353 23:44:10.987212 Dram Type= 6, Freq= 0, CH_0, rank 1
1354 23:44:10.994127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1355 23:44:10.994208 ==
1356 23:44:10.994271 DQS Delay:
1357 23:44:10.997446 DQS0 = 0, DQS1 = 0
1358 23:44:10.997527 DQM Delay:
1359 23:44:10.997589 DQM0 = 87, DQM1 = 78
1360 23:44:11.000721 DQ Delay:
1361 23:44:11.003903 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1362 23:44:11.007181 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1363 23:44:11.010974 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1364 23:44:11.014037 DQ12 =84, DQ13 =80, DQ14 =88, DQ15 =88
1365 23:44:11.014118
1366 23:44:11.014180
1367 23:44:11.020881 [DQSOSCAuto] RK1, (LSB)MR18= 0x321d, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
1368 23:44:11.024363 CH0 RK1: MR19=606, MR18=321D
1369 23:44:11.031159 CH0_RK1: MR19=0x606, MR18=0x321D, DQSOSC=397, MR23=63, INC=93, DEC=62
1370 23:44:11.033843 [RxdqsGatingPostProcess] freq 800
1371 23:44:11.037253 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1372 23:44:11.040839 Pre-setting of DQS Precalculation
1373 23:44:11.047395 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1374 23:44:11.047475 ==
1375 23:44:11.050777 Dram Type= 6, Freq= 0, CH_1, rank 0
1376 23:44:11.054032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1377 23:44:11.054112 ==
1378 23:44:11.060785 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1379 23:44:11.063857 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1380 23:44:11.074318 [CA 0] Center 36 (6~66) winsize 61
1381 23:44:11.077631 [CA 1] Center 36 (6~67) winsize 62
1382 23:44:11.080951 [CA 2] Center 34 (5~64) winsize 60
1383 23:44:11.084634 [CA 3] Center 33 (3~64) winsize 62
1384 23:44:11.087981 [CA 4] Center 34 (4~65) winsize 62
1385 23:44:11.091127 [CA 5] Center 33 (3~64) winsize 62
1386 23:44:11.091196
1387 23:44:11.094256 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1388 23:44:11.094328
1389 23:44:11.097741 [CATrainingPosCal] consider 1 rank data
1390 23:44:11.101121 u2DelayCellTimex100 = 270/100 ps
1391 23:44:11.104855 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1392 23:44:11.107884 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1393 23:44:11.111334 CA2 delay=34 (5~64),Diff = 1 PI (7 cell)
1394 23:44:11.118087 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1395 23:44:11.121546 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1396 23:44:11.124844 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1397 23:44:11.124955
1398 23:44:11.127949 CA PerBit enable=1, Macro0, CA PI delay=33
1399 23:44:11.128030
1400 23:44:11.131876 [CBTSetCACLKResult] CA Dly = 33
1401 23:44:11.131957 CS Dly: 5 (0~36)
1402 23:44:11.132021 ==
1403 23:44:11.134895 Dram Type= 6, Freq= 0, CH_1, rank 1
1404 23:44:11.141502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1405 23:44:11.141583 ==
1406 23:44:11.145299 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1407 23:44:11.151502 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1408 23:44:11.160201 [CA 0] Center 36 (6~66) winsize 61
1409 23:44:11.164060 [CA 1] Center 36 (6~66) winsize 61
1410 23:44:11.167219 [CA 2] Center 34 (4~65) winsize 62
1411 23:44:11.170568 [CA 3] Center 33 (3~64) winsize 62
1412 23:44:11.173805 [CA 4] Center 34 (4~65) winsize 62
1413 23:44:11.177588 [CA 5] Center 33 (3~64) winsize 62
1414 23:44:11.177669
1415 23:44:11.181160 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1416 23:44:11.181264
1417 23:44:11.184906 [CATrainingPosCal] consider 2 rank data
1418 23:44:11.188901 u2DelayCellTimex100 = 270/100 ps
1419 23:44:11.192745 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1420 23:44:11.196619 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1421 23:44:11.199894 CA2 delay=34 (5~64),Diff = 1 PI (7 cell)
1422 23:44:11.203380 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1423 23:44:11.207362 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1424 23:44:11.211564 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1425 23:44:11.211646
1426 23:44:11.215138 CA PerBit enable=1, Macro0, CA PI delay=33
1427 23:44:11.215222
1428 23:44:11.218384 [CBTSetCACLKResult] CA Dly = 33
1429 23:44:11.218490 CS Dly: 5 (0~37)
1430 23:44:11.218581
1431 23:44:11.221647 ----->DramcWriteLeveling(PI) begin...
1432 23:44:11.221729 ==
1433 23:44:11.225117 Dram Type= 6, Freq= 0, CH_1, rank 0
1434 23:44:11.228169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1435 23:44:11.228251 ==
1436 23:44:11.231721 Write leveling (Byte 0): 28 => 28
1437 23:44:11.234955 Write leveling (Byte 1): 29 => 29
1438 23:44:11.238409 DramcWriteLeveling(PI) end<-----
1439 23:44:11.238489
1440 23:44:11.238553 ==
1441 23:44:11.241719 Dram Type= 6, Freq= 0, CH_1, rank 0
1442 23:44:11.244934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1443 23:44:11.248305 ==
1444 23:44:11.248386 [Gating] SW mode calibration
1445 23:44:11.255315 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1446 23:44:11.261782 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1447 23:44:11.265171 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1448 23:44:11.271951 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1449 23:44:11.275210 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1450 23:44:11.278874 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 23:44:11.285256 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 23:44:11.288805 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 23:44:11.291879 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 23:44:11.295292 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 23:44:11.301917 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 23:44:11.305390 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 23:44:11.308927 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 23:44:11.315590 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 23:44:11.318571 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 23:44:11.322442 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 23:44:11.328564 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 23:44:11.332567 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 23:44:11.335308 0 8 0 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1464 23:44:11.342192 0 8 4 | B1->B0 | 2424 2323 | 0 0 | (0 1) (0 1)
1465 23:44:11.345303 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1466 23:44:11.348856 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 23:44:11.355539 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 23:44:11.358863 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 23:44:11.362549 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 23:44:11.365877 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 23:44:11.372189 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 23:44:11.375556 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 23:44:11.379153 0 9 8 | B1->B0 | 2424 2727 | 0 1 | (0 0) (1 1)
1474 23:44:11.385818 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1475 23:44:11.389320 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1476 23:44:11.392514 0 9 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1477 23:44:11.399282 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 23:44:11.402669 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 23:44:11.406039 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 23:44:11.412800 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 23:44:11.415954 0 10 8 | B1->B0 | 2c2c 3030 | 0 0 | (1 0) (1 0)
1482 23:44:11.419593 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 23:44:11.423134 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 23:44:11.429505 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 23:44:11.433199 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 23:44:11.436194 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 23:44:11.443016 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 23:44:11.446110 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 23:44:11.449720 0 11 8 | B1->B0 | 3535 3131 | 0 1 | (0 0) (0 0)
1490 23:44:11.456240 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1491 23:44:11.459822 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1492 23:44:11.462663 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 23:44:11.469411 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 23:44:11.472746 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 23:44:11.476314 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 23:44:11.482901 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1497 23:44:11.486185 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 23:44:11.489492 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1499 23:44:11.493149 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 23:44:11.499560 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 23:44:11.503092 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 23:44:11.506623 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 23:44:11.513352 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 23:44:11.516753 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 23:44:11.519905 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 23:44:11.526766 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 23:44:11.529898 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 23:44:11.533661 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 23:44:11.540063 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 23:44:11.543172 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 23:44:11.547055 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 23:44:11.550386 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1513 23:44:11.557595 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1514 23:44:11.560506 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1515 23:44:11.563630 Total UI for P1: 0, mck2ui 16
1516 23:44:11.566911 best dqsien dly found for B0: ( 0, 14, 8)
1517 23:44:11.570538 Total UI for P1: 0, mck2ui 16
1518 23:44:11.573660 best dqsien dly found for B1: ( 0, 14, 6)
1519 23:44:11.577240 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1520 23:44:11.580251 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1521 23:44:11.580331
1522 23:44:11.583560 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1523 23:44:11.587115 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1524 23:44:11.590533 [Gating] SW calibration Done
1525 23:44:11.590612 ==
1526 23:44:11.594098 Dram Type= 6, Freq= 0, CH_1, rank 0
1527 23:44:11.597552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1528 23:44:11.597632 ==
1529 23:44:11.600821 RX Vref Scan: 0
1530 23:44:11.600900
1531 23:44:11.604194 RX Vref 0 -> 0, step: 1
1532 23:44:11.604273
1533 23:44:11.604336 RX Delay -130 -> 252, step: 16
1534 23:44:11.610936 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1535 23:44:11.614335 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1536 23:44:11.617209 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1537 23:44:11.620435 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1538 23:44:11.623786 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1539 23:44:11.630590 iDelay=206, Bit 5, Center 85 (-34 ~ 205) 240
1540 23:44:11.633814 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1541 23:44:11.637600 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1542 23:44:11.640818 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1543 23:44:11.643830 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1544 23:44:11.650946 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1545 23:44:11.654048 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1546 23:44:11.657228 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1547 23:44:11.660814 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1548 23:44:11.664027 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1549 23:44:11.670817 iDelay=206, Bit 15, Center 77 (-50 ~ 205) 256
1550 23:44:11.670898 ==
1551 23:44:11.674454 Dram Type= 6, Freq= 0, CH_1, rank 0
1552 23:44:11.677694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1553 23:44:11.677774 ==
1554 23:44:11.677837 DQS Delay:
1555 23:44:11.681093 DQS0 = 0, DQS1 = 0
1556 23:44:11.681173 DQM Delay:
1557 23:44:11.684193 DQM0 = 82, DQM1 = 75
1558 23:44:11.684272 DQ Delay:
1559 23:44:11.687433 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1560 23:44:11.690813 DQ4 =85, DQ5 =85, DQ6 =93, DQ7 =77
1561 23:44:11.694874 DQ8 =69, DQ9 =61, DQ10 =69, DQ11 =69
1562 23:44:11.697524 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =77
1563 23:44:11.697604
1564 23:44:11.697667
1565 23:44:11.697724 ==
1566 23:44:11.700851 Dram Type= 6, Freq= 0, CH_1, rank 0
1567 23:44:11.704309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1568 23:44:11.704389 ==
1569 23:44:11.704451
1570 23:44:11.704509
1571 23:44:11.707857 TX Vref Scan disable
1572 23:44:11.711264 == TX Byte 0 ==
1573 23:44:11.714796 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1574 23:44:11.718341 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1575 23:44:11.721138 == TX Byte 1 ==
1576 23:44:11.724596 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1577 23:44:11.728153 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1578 23:44:11.728232 ==
1579 23:44:11.731388 Dram Type= 6, Freq= 0, CH_1, rank 0
1580 23:44:11.734982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1581 23:44:11.735062 ==
1582 23:44:11.748852 TX Vref=22, minBit 10, minWin=26, winSum=439
1583 23:44:11.752566 TX Vref=24, minBit 10, minWin=26, winSum=444
1584 23:44:11.755423 TX Vref=26, minBit 1, minWin=27, winSum=447
1585 23:44:11.758905 TX Vref=28, minBit 0, minWin=28, winSum=454
1586 23:44:11.762764 TX Vref=30, minBit 0, minWin=28, winSum=455
1587 23:44:11.766295 TX Vref=32, minBit 1, minWin=28, winSum=454
1588 23:44:11.773224 [TxChooseVref] Worse bit 0, Min win 28, Win sum 455, Final Vref 30
1589 23:44:11.773307
1590 23:44:11.776495 Final TX Range 1 Vref 30
1591 23:44:11.776575
1592 23:44:11.776638 ==
1593 23:44:11.779770 Dram Type= 6, Freq= 0, CH_1, rank 0
1594 23:44:11.782727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1595 23:44:11.782809 ==
1596 23:44:11.782872
1597 23:44:11.782930
1598 23:44:11.786297 TX Vref Scan disable
1599 23:44:11.789731 == TX Byte 0 ==
1600 23:44:11.792916 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1601 23:44:11.796349 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1602 23:44:11.799784 == TX Byte 1 ==
1603 23:44:11.803094 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1604 23:44:11.806123 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1605 23:44:11.806204
1606 23:44:11.809499 [DATLAT]
1607 23:44:11.809579 Freq=800, CH1 RK0
1608 23:44:11.809642
1609 23:44:11.812808 DATLAT Default: 0xa
1610 23:44:11.812888 0, 0xFFFF, sum = 0
1611 23:44:11.816198 1, 0xFFFF, sum = 0
1612 23:44:11.816280 2, 0xFFFF, sum = 0
1613 23:44:11.820022 3, 0xFFFF, sum = 0
1614 23:44:11.820103 4, 0xFFFF, sum = 0
1615 23:44:11.823081 5, 0xFFFF, sum = 0
1616 23:44:11.823162 6, 0xFFFF, sum = 0
1617 23:44:11.826262 7, 0xFFFF, sum = 0
1618 23:44:11.826343 8, 0xFFFF, sum = 0
1619 23:44:11.830085 9, 0x0, sum = 1
1620 23:44:11.830166 10, 0x0, sum = 2
1621 23:44:11.833489 11, 0x0, sum = 3
1622 23:44:11.833570 12, 0x0, sum = 4
1623 23:44:11.836752 best_step = 10
1624 23:44:11.836832
1625 23:44:11.836894 ==
1626 23:44:11.839718 Dram Type= 6, Freq= 0, CH_1, rank 0
1627 23:44:11.842975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1628 23:44:11.843055 ==
1629 23:44:11.843118 RX Vref Scan: 1
1630 23:44:11.843177
1631 23:44:11.846821 Set Vref Range= 32 -> 127
1632 23:44:11.846901
1633 23:44:11.850040 RX Vref 32 -> 127, step: 1
1634 23:44:11.850120
1635 23:44:11.853364 RX Delay -95 -> 252, step: 8
1636 23:44:11.853444
1637 23:44:11.856855 Set Vref, RX VrefLevel [Byte0]: 32
1638 23:44:11.859817 [Byte1]: 32
1639 23:44:11.859898
1640 23:44:11.863319 Set Vref, RX VrefLevel [Byte0]: 33
1641 23:44:11.866563 [Byte1]: 33
1642 23:44:11.866644
1643 23:44:11.870130 Set Vref, RX VrefLevel [Byte0]: 34
1644 23:44:11.873343 [Byte1]: 34
1645 23:44:11.877197
1646 23:44:11.877277 Set Vref, RX VrefLevel [Byte0]: 35
1647 23:44:11.880162 [Byte1]: 35
1648 23:44:11.884483
1649 23:44:11.884563 Set Vref, RX VrefLevel [Byte0]: 36
1650 23:44:11.888032 [Byte1]: 36
1651 23:44:11.892151
1652 23:44:11.892231 Set Vref, RX VrefLevel [Byte0]: 37
1653 23:44:11.895379 [Byte1]: 37
1654 23:44:11.899570
1655 23:44:11.899650 Set Vref, RX VrefLevel [Byte0]: 38
1656 23:44:11.902953 [Byte1]: 38
1657 23:44:11.907666
1658 23:44:11.907747 Set Vref, RX VrefLevel [Byte0]: 39
1659 23:44:11.910563 [Byte1]: 39
1660 23:44:11.914908
1661 23:44:11.914988 Set Vref, RX VrefLevel [Byte0]: 40
1662 23:44:11.918147 [Byte1]: 40
1663 23:44:11.922912
1664 23:44:11.922993 Set Vref, RX VrefLevel [Byte0]: 41
1665 23:44:11.925643 [Byte1]: 41
1666 23:44:11.930491
1667 23:44:11.930572 Set Vref, RX VrefLevel [Byte0]: 42
1668 23:44:11.933293 [Byte1]: 42
1669 23:44:11.938100
1670 23:44:11.938180 Set Vref, RX VrefLevel [Byte0]: 43
1671 23:44:11.941005 [Byte1]: 43
1672 23:44:11.945637
1673 23:44:11.945717 Set Vref, RX VrefLevel [Byte0]: 44
1674 23:44:11.948535 [Byte1]: 44
1675 23:44:11.953154
1676 23:44:11.953234 Set Vref, RX VrefLevel [Byte0]: 45
1677 23:44:11.956504 [Byte1]: 45
1678 23:44:11.960416
1679 23:44:11.960522 Set Vref, RX VrefLevel [Byte0]: 46
1680 23:44:11.963807 [Byte1]: 46
1681 23:44:11.968458
1682 23:44:11.968542 Set Vref, RX VrefLevel [Byte0]: 47
1683 23:44:11.971435 [Byte1]: 47
1684 23:44:11.975431
1685 23:44:11.975511 Set Vref, RX VrefLevel [Byte0]: 48
1686 23:44:11.978986 [Byte1]: 48
1687 23:44:11.983464
1688 23:44:11.983544 Set Vref, RX VrefLevel [Byte0]: 49
1689 23:44:11.986602 [Byte1]: 49
1690 23:44:11.990840
1691 23:44:11.990919 Set Vref, RX VrefLevel [Byte0]: 50
1692 23:44:11.994475 [Byte1]: 50
1693 23:44:11.998622
1694 23:44:11.998702 Set Vref, RX VrefLevel [Byte0]: 51
1695 23:44:12.001581 [Byte1]: 51
1696 23:44:12.006332
1697 23:44:12.006405 Set Vref, RX VrefLevel [Byte0]: 52
1698 23:44:12.009227 [Byte1]: 52
1699 23:44:12.013744
1700 23:44:12.013825 Set Vref, RX VrefLevel [Byte0]: 53
1701 23:44:12.017274 [Byte1]: 53
1702 23:44:12.021207
1703 23:44:12.021307 Set Vref, RX VrefLevel [Byte0]: 54
1704 23:44:12.024838 [Byte1]: 54
1705 23:44:12.028871
1706 23:44:12.028986 Set Vref, RX VrefLevel [Byte0]: 55
1707 23:44:12.032175 [Byte1]: 55
1708 23:44:12.036570
1709 23:44:12.036676 Set Vref, RX VrefLevel [Byte0]: 56
1710 23:44:12.039564 [Byte1]: 56
1711 23:44:12.044224
1712 23:44:12.044303 Set Vref, RX VrefLevel [Byte0]: 57
1713 23:44:12.047119 [Byte1]: 57
1714 23:44:12.051417
1715 23:44:12.051497 Set Vref, RX VrefLevel [Byte0]: 58
1716 23:44:12.054897 [Byte1]: 58
1717 23:44:12.059229
1718 23:44:12.059335 Set Vref, RX VrefLevel [Byte0]: 59
1719 23:44:12.062529 [Byte1]: 59
1720 23:44:12.066679
1721 23:44:12.066758 Set Vref, RX VrefLevel [Byte0]: 60
1722 23:44:12.069990 [Byte1]: 60
1723 23:44:12.074395
1724 23:44:12.074475 Set Vref, RX VrefLevel [Byte0]: 61
1725 23:44:12.077903 [Byte1]: 61
1726 23:44:12.082543
1727 23:44:12.082623 Set Vref, RX VrefLevel [Byte0]: 62
1728 23:44:12.085394 [Byte1]: 62
1729 23:44:12.089678
1730 23:44:12.089758 Set Vref, RX VrefLevel [Byte0]: 63
1731 23:44:12.092778 [Byte1]: 63
1732 23:44:12.097397
1733 23:44:12.097477 Set Vref, RX VrefLevel [Byte0]: 64
1734 23:44:12.100641 [Byte1]: 64
1735 23:44:12.104858
1736 23:44:12.104938 Set Vref, RX VrefLevel [Byte0]: 65
1737 23:44:12.108026 [Byte1]: 65
1738 23:44:12.112202
1739 23:44:12.112282 Set Vref, RX VrefLevel [Byte0]: 66
1740 23:44:12.115963 [Byte1]: 66
1741 23:44:12.119793
1742 23:44:12.119873 Set Vref, RX VrefLevel [Byte0]: 67
1743 23:44:12.123270 [Byte1]: 67
1744 23:44:12.127394
1745 23:44:12.127475 Set Vref, RX VrefLevel [Byte0]: 68
1746 23:44:12.131167 [Byte1]: 68
1747 23:44:12.135010
1748 23:44:12.135090 Set Vref, RX VrefLevel [Byte0]: 69
1749 23:44:12.138265 [Byte1]: 69
1750 23:44:12.142757
1751 23:44:12.142836 Set Vref, RX VrefLevel [Byte0]: 70
1752 23:44:12.146526 [Byte1]: 70
1753 23:44:12.150171
1754 23:44:12.150251 Set Vref, RX VrefLevel [Byte0]: 71
1755 23:44:12.153551 [Byte1]: 71
1756 23:44:12.158045
1757 23:44:12.158124 Set Vref, RX VrefLevel [Byte0]: 72
1758 23:44:12.161137 [Byte1]: 72
1759 23:44:12.165687
1760 23:44:12.165768 Set Vref, RX VrefLevel [Byte0]: 73
1761 23:44:12.168818 [Byte1]: 73
1762 23:44:12.173299
1763 23:44:12.173379 Set Vref, RX VrefLevel [Byte0]: 74
1764 23:44:12.176534 [Byte1]: 74
1765 23:44:12.180428
1766 23:44:12.180508 Set Vref, RX VrefLevel [Byte0]: 75
1767 23:44:12.183793 [Byte1]: 75
1768 23:44:12.188461
1769 23:44:12.188541 Set Vref, RX VrefLevel [Byte0]: 76
1770 23:44:12.191508 [Byte1]: 76
1771 23:44:12.196087
1772 23:44:12.196169 Set Vref, RX VrefLevel [Byte0]: 77
1773 23:44:12.199050 [Byte1]: 77
1774 23:44:12.203450
1775 23:44:12.203531 Set Vref, RX VrefLevel [Byte0]: 78
1776 23:44:12.207231 [Byte1]: 78
1777 23:44:12.211242
1778 23:44:12.211323 Final RX Vref Byte 0 = 64 to rank0
1779 23:44:12.214868 Final RX Vref Byte 1 = 59 to rank0
1780 23:44:12.218012 Final RX Vref Byte 0 = 64 to rank1
1781 23:44:12.221245 Final RX Vref Byte 1 = 59 to rank1==
1782 23:44:12.224748 Dram Type= 6, Freq= 0, CH_1, rank 0
1783 23:44:12.228097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1784 23:44:12.231626 ==
1785 23:44:12.231707 DQS Delay:
1786 23:44:12.231771 DQS0 = 0, DQS1 = 0
1787 23:44:12.234558 DQM Delay:
1788 23:44:12.234638 DQM0 = 83, DQM1 = 73
1789 23:44:12.238899 DQ Delay:
1790 23:44:12.238982 DQ0 =92, DQ1 =76, DQ2 =72, DQ3 =84
1791 23:44:12.241369 DQ4 =80, DQ5 =92, DQ6 =96, DQ7 =76
1792 23:44:12.244775 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =72
1793 23:44:12.248721 DQ12 =84, DQ13 =80, DQ14 =80, DQ15 =76
1794 23:44:12.248829
1795 23:44:12.248924
1796 23:44:12.258242 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c02, (MSB)MR19= 0x606, tDQSOscB0 = 409 ps tDQSOscB1 = 398 ps
1797 23:44:12.261598 CH1 RK0: MR19=606, MR18=2C02
1798 23:44:12.265347 CH1_RK0: MR19=0x606, MR18=0x2C02, DQSOSC=398, MR23=63, INC=93, DEC=62
1799 23:44:12.268505
1800 23:44:12.272119 ----->DramcWriteLeveling(PI) begin...
1801 23:44:12.272201 ==
1802 23:44:12.274947 Dram Type= 6, Freq= 0, CH_1, rank 1
1803 23:44:12.278449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1804 23:44:12.278539 ==
1805 23:44:12.281735 Write leveling (Byte 0): 27 => 27
1806 23:44:12.285103 Write leveling (Byte 1): 27 => 27
1807 23:44:12.288567 DramcWriteLeveling(PI) end<-----
1808 23:44:12.288672
1809 23:44:12.288770 ==
1810 23:44:12.291769 Dram Type= 6, Freq= 0, CH_1, rank 1
1811 23:44:12.295134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1812 23:44:12.295230 ==
1813 23:44:12.299005 [Gating] SW mode calibration
1814 23:44:12.305581 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1815 23:44:12.308569 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1816 23:44:12.315299 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1817 23:44:12.318526 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1818 23:44:12.322105 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1819 23:44:12.328625 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 23:44:12.332125 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 23:44:12.335595 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 23:44:12.342041 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 23:44:12.345417 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 23:44:12.348894 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 23:44:12.355472 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 23:44:12.359012 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 23:44:12.362291 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 23:44:12.365749 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 23:44:12.372097 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 23:44:12.375494 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 23:44:12.379168 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 23:44:12.385690 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 23:44:12.389268 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1834 23:44:12.392775 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1835 23:44:12.399189 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 23:44:12.402515 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 23:44:12.406264 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 23:44:12.413083 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 23:44:12.415790 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 23:44:12.419272 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 23:44:12.422781 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1842 23:44:12.429430 0 9 8 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
1843 23:44:12.432777 0 9 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1844 23:44:12.436160 0 9 16 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
1845 23:44:12.443045 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1846 23:44:12.446482 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1847 23:44:12.449444 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1848 23:44:12.456402 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1849 23:44:12.459621 0 10 4 | B1->B0 | 3030 2f2f | 0 0 | (1 0) (0 1)
1850 23:44:12.463190 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 23:44:12.469918 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 23:44:12.472771 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 23:44:12.476198 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 23:44:12.482766 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 23:44:12.486137 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 23:44:12.489852 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 23:44:12.493425 0 11 4 | B1->B0 | 2d2d 3332 | 0 1 | (0 0) (0 0)
1858 23:44:12.500079 0 11 8 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
1859 23:44:12.503101 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1860 23:44:12.506398 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1861 23:44:12.513441 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1862 23:44:12.516930 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1863 23:44:12.520150 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1864 23:44:12.527007 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1865 23:44:12.530090 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1866 23:44:12.533125 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 23:44:12.539784 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 23:44:12.543259 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 23:44:12.546887 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 23:44:12.550072 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 23:44:12.556854 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 23:44:12.560598 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 23:44:12.563885 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 23:44:12.570052 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 23:44:12.573513 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 23:44:12.576905 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 23:44:12.583131 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 23:44:12.586631 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 23:44:12.590440 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 23:44:12.596767 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1881 23:44:12.599797 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1882 23:44:12.603287 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1883 23:44:12.606524 Total UI for P1: 0, mck2ui 16
1884 23:44:12.610055 best dqsien dly found for B0: ( 0, 14, 2)
1885 23:44:12.613850 Total UI for P1: 0, mck2ui 16
1886 23:44:12.616941 best dqsien dly found for B1: ( 0, 14, 6)
1887 23:44:12.620381 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1888 23:44:12.623561 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1889 23:44:12.623641
1890 23:44:12.626960 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1891 23:44:12.633840 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1892 23:44:12.633921 [Gating] SW calibration Done
1893 23:44:12.633984 ==
1894 23:44:12.637087 Dram Type= 6, Freq= 0, CH_1, rank 1
1895 23:44:12.644252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1896 23:44:12.644347 ==
1897 23:44:12.644410 RX Vref Scan: 0
1898 23:44:12.644468
1899 23:44:12.647180 RX Vref 0 -> 0, step: 1
1900 23:44:12.647260
1901 23:44:12.650577 RX Delay -130 -> 252, step: 16
1902 23:44:12.653769 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1903 23:44:12.657192 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1904 23:44:12.660382 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1905 23:44:12.664137 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1906 23:44:12.670300 iDelay=206, Bit 4, Center 77 (-34 ~ 189) 224
1907 23:44:12.673891 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1908 23:44:12.676935 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1909 23:44:12.680592 iDelay=206, Bit 7, Center 69 (-50 ~ 189) 240
1910 23:44:12.683786 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1911 23:44:12.690644 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1912 23:44:12.694121 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1913 23:44:12.697271 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1914 23:44:12.700459 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1915 23:44:12.703707 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1916 23:44:12.710587 iDelay=206, Bit 14, Center 77 (-50 ~ 205) 256
1917 23:44:12.714049 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1918 23:44:12.714129 ==
1919 23:44:12.717520 Dram Type= 6, Freq= 0, CH_1, rank 1
1920 23:44:12.720460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1921 23:44:12.720540 ==
1922 23:44:12.724055 DQS Delay:
1923 23:44:12.724134 DQS0 = 0, DQS1 = 0
1924 23:44:12.724197 DQM Delay:
1925 23:44:12.727252 DQM0 = 79, DQM1 = 76
1926 23:44:12.727332 DQ Delay:
1927 23:44:12.731070 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =77
1928 23:44:12.734109 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =69
1929 23:44:12.737631 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1930 23:44:12.740859 DQ12 =85, DQ13 =85, DQ14 =77, DQ15 =85
1931 23:44:12.740963
1932 23:44:12.741061
1933 23:44:12.741150 ==
1934 23:44:12.744594 Dram Type= 6, Freq= 0, CH_1, rank 1
1935 23:44:12.748017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1936 23:44:12.751294 ==
1937 23:44:12.751373
1938 23:44:12.751436
1939 23:44:12.751493 TX Vref Scan disable
1940 23:44:12.754638 == TX Byte 0 ==
1941 23:44:12.757952 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1942 23:44:12.760774 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1943 23:44:12.764306 == TX Byte 1 ==
1944 23:44:12.767731 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1945 23:44:12.770919 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1946 23:44:12.771000 ==
1947 23:44:12.774413 Dram Type= 6, Freq= 0, CH_1, rank 1
1948 23:44:12.781203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1949 23:44:12.781283 ==
1950 23:44:12.792867 TX Vref=22, minBit 15, minWin=26, winSum=439
1951 23:44:12.796479 TX Vref=24, minBit 1, minWin=27, winSum=441
1952 23:44:12.799921 TX Vref=26, minBit 9, minWin=27, winSum=445
1953 23:44:12.803065 TX Vref=28, minBit 1, minWin=27, winSum=448
1954 23:44:12.806174 TX Vref=30, minBit 0, minWin=28, winSum=451
1955 23:44:12.810114 TX Vref=32, minBit 0, minWin=28, winSum=453
1956 23:44:12.816636 [TxChooseVref] Worse bit 0, Min win 28, Win sum 453, Final Vref 32
1957 23:44:12.816748
1958 23:44:12.820018 Final TX Range 1 Vref 32
1959 23:44:12.820130
1960 23:44:12.820226 ==
1961 23:44:12.823241 Dram Type= 6, Freq= 0, CH_1, rank 1
1962 23:44:12.826663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1963 23:44:12.826755 ==
1964 23:44:12.826845
1965 23:44:12.826936
1966 23:44:12.829553 TX Vref Scan disable
1967 23:44:12.833235 == TX Byte 0 ==
1968 23:44:12.836735 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1969 23:44:12.839810 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1970 23:44:12.843280 == TX Byte 1 ==
1971 23:44:12.846563 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1972 23:44:12.849993 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1973 23:44:12.850106
1974 23:44:12.853413 [DATLAT]
1975 23:44:12.853492 Freq=800, CH1 RK1
1976 23:44:12.853555
1977 23:44:12.856919 DATLAT Default: 0xa
1978 23:44:12.857053 0, 0xFFFF, sum = 0
1979 23:44:12.859972 1, 0xFFFF, sum = 0
1980 23:44:12.860074 2, 0xFFFF, sum = 0
1981 23:44:12.863342 3, 0xFFFF, sum = 0
1982 23:44:12.863451 4, 0xFFFF, sum = 0
1983 23:44:12.866561 5, 0xFFFF, sum = 0
1984 23:44:12.866673 6, 0xFFFF, sum = 0
1985 23:44:12.869766 7, 0xFFFF, sum = 0
1986 23:44:12.869846 8, 0xFFFF, sum = 0
1987 23:44:12.873327 9, 0x0, sum = 1
1988 23:44:12.873429 10, 0x0, sum = 2
1989 23:44:12.876913 11, 0x0, sum = 3
1990 23:44:12.877001 12, 0x0, sum = 4
1991 23:44:12.880322 best_step = 10
1992 23:44:12.880401
1993 23:44:12.880463 ==
1994 23:44:12.883218 Dram Type= 6, Freq= 0, CH_1, rank 1
1995 23:44:12.886898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1996 23:44:12.887010 ==
1997 23:44:12.887106 RX Vref Scan: 0
1998 23:44:12.890249
1999 23:44:12.890356 RX Vref 0 -> 0, step: 1
2000 23:44:12.890448
2001 23:44:12.893858 RX Delay -95 -> 252, step: 8
2002 23:44:12.896734 iDelay=201, Bit 0, Center 84 (-31 ~ 200) 232
2003 23:44:12.903560 iDelay=201, Bit 1, Center 76 (-39 ~ 192) 232
2004 23:44:12.907027 iDelay=201, Bit 2, Center 68 (-47 ~ 184) 232
2005 23:44:12.910238 iDelay=201, Bit 3, Center 76 (-39 ~ 192) 232
2006 23:44:12.913837 iDelay=201, Bit 4, Center 80 (-31 ~ 192) 224
2007 23:44:12.917017 iDelay=201, Bit 5, Center 88 (-23 ~ 200) 224
2008 23:44:12.923803 iDelay=201, Bit 6, Center 88 (-23 ~ 200) 224
2009 23:44:12.927470 iDelay=201, Bit 7, Center 72 (-39 ~ 184) 224
2010 23:44:12.930366 iDelay=201, Bit 8, Center 68 (-47 ~ 184) 232
2011 23:44:12.933860 iDelay=201, Bit 9, Center 64 (-47 ~ 176) 224
2012 23:44:12.937356 iDelay=201, Bit 10, Center 76 (-39 ~ 192) 232
2013 23:44:12.940490 iDelay=201, Bit 11, Center 68 (-47 ~ 184) 232
2014 23:44:12.947120 iDelay=201, Bit 12, Center 80 (-31 ~ 192) 224
2015 23:44:12.950372 iDelay=201, Bit 13, Center 84 (-31 ~ 200) 232
2016 23:44:12.954100 iDelay=201, Bit 14, Center 84 (-31 ~ 200) 232
2017 23:44:12.957266 iDelay=201, Bit 15, Center 84 (-31 ~ 200) 232
2018 23:44:12.957347 ==
2019 23:44:12.960522 Dram Type= 6, Freq= 0, CH_1, rank 1
2020 23:44:12.967617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2021 23:44:12.967699 ==
2022 23:44:12.967762 DQS Delay:
2023 23:44:12.970624 DQS0 = 0, DQS1 = 0
2024 23:44:12.970705 DQM Delay:
2025 23:44:12.970767 DQM0 = 79, DQM1 = 76
2026 23:44:12.974085 DQ Delay:
2027 23:44:12.977526 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
2028 23:44:12.981243 DQ4 =80, DQ5 =88, DQ6 =88, DQ7 =72
2029 23:44:12.983853 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
2030 23:44:12.987397 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
2031 23:44:12.987478
2032 23:44:12.987540
2033 23:44:12.993734 [DQSOSCAuto] RK1, (LSB)MR18= 0x202c, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 401 ps
2034 23:44:12.997554 CH1 RK1: MR19=606, MR18=202C
2035 23:44:13.004270 CH1_RK1: MR19=0x606, MR18=0x202C, DQSOSC=398, MR23=63, INC=93, DEC=62
2036 23:44:13.007442 [RxdqsGatingPostProcess] freq 800
2037 23:44:13.011078 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2038 23:44:13.014113 Pre-setting of DQS Precalculation
2039 23:44:13.020918 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2040 23:44:13.027175 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2041 23:44:13.034156 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2042 23:44:13.034257
2043 23:44:13.034322
2044 23:44:13.037288 [Calibration Summary] 1600 Mbps
2045 23:44:13.037368 CH 0, Rank 0
2046 23:44:13.040564 SW Impedance : PASS
2047 23:44:13.044333 DUTY Scan : NO K
2048 23:44:13.044413 ZQ Calibration : PASS
2049 23:44:13.047496 Jitter Meter : NO K
2050 23:44:13.051032 CBT Training : PASS
2051 23:44:13.051110 Write leveling : PASS
2052 23:44:13.053890 RX DQS gating : PASS
2053 23:44:13.053971 RX DQ/DQS(RDDQC) : PASS
2054 23:44:13.057457 TX DQ/DQS : PASS
2055 23:44:13.060689 RX DATLAT : PASS
2056 23:44:13.060789 RX DQ/DQS(Engine): PASS
2057 23:44:13.064309 TX OE : NO K
2058 23:44:13.064391 All Pass.
2059 23:44:13.064454
2060 23:44:13.067736 CH 0, Rank 1
2061 23:44:13.067816 SW Impedance : PASS
2062 23:44:13.071283 DUTY Scan : NO K
2063 23:44:13.074195 ZQ Calibration : PASS
2064 23:44:13.074276 Jitter Meter : NO K
2065 23:44:13.077816 CBT Training : PASS
2066 23:44:13.081250 Write leveling : PASS
2067 23:44:13.081336 RX DQS gating : PASS
2068 23:44:13.084753 RX DQ/DQS(RDDQC) : PASS
2069 23:44:13.084847 TX DQ/DQS : PASS
2070 23:44:13.087717 RX DATLAT : PASS
2071 23:44:13.091204 RX DQ/DQS(Engine): PASS
2072 23:44:13.091304 TX OE : NO K
2073 23:44:13.094563 All Pass.
2074 23:44:13.094671
2075 23:44:13.094757 CH 1, Rank 0
2076 23:44:13.097511 SW Impedance : PASS
2077 23:44:13.097620 DUTY Scan : NO K
2078 23:44:13.101885 ZQ Calibration : PASS
2079 23:44:13.104824 Jitter Meter : NO K
2080 23:44:13.105009 CBT Training : PASS
2081 23:44:13.107862 Write leveling : PASS
2082 23:44:13.111690 RX DQS gating : PASS
2083 23:44:13.111840 RX DQ/DQS(RDDQC) : PASS
2084 23:44:13.114493 TX DQ/DQS : PASS
2085 23:44:13.117881 RX DATLAT : PASS
2086 23:44:13.118050 RX DQ/DQS(Engine): PASS
2087 23:44:13.121297 TX OE : NO K
2088 23:44:13.121494 All Pass.
2089 23:44:13.121646
2090 23:44:13.124587 CH 1, Rank 1
2091 23:44:13.124834 SW Impedance : PASS
2092 23:44:13.128459 DUTY Scan : NO K
2093 23:44:13.128748 ZQ Calibration : PASS
2094 23:44:13.131239 Jitter Meter : NO K
2095 23:44:13.134934 CBT Training : PASS
2096 23:44:13.135313 Write leveling : PASS
2097 23:44:13.138208 RX DQS gating : PASS
2098 23:44:13.141582 RX DQ/DQS(RDDQC) : PASS
2099 23:44:13.141963 TX DQ/DQS : PASS
2100 23:44:13.144862 RX DATLAT : PASS
2101 23:44:13.148547 RX DQ/DQS(Engine): PASS
2102 23:44:13.148930 TX OE : NO K
2103 23:44:13.151870 All Pass.
2104 23:44:13.152255
2105 23:44:13.152558 DramC Write-DBI off
2106 23:44:13.154942 PER_BANK_REFRESH: Hybrid Mode
2107 23:44:13.155320 TX_TRACKING: ON
2108 23:44:13.158430 [GetDramInforAfterCalByMRR] Vendor 6.
2109 23:44:13.161589 [GetDramInforAfterCalByMRR] Revision 606.
2110 23:44:13.168081 [GetDramInforAfterCalByMRR] Revision 2 0.
2111 23:44:13.168496 MR0 0x3b3b
2112 23:44:13.168825 MR8 0x5151
2113 23:44:13.171575 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2114 23:44:13.171976
2115 23:44:13.174998 MR0 0x3b3b
2116 23:44:13.175471 MR8 0x5151
2117 23:44:13.178475 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2118 23:44:13.178859
2119 23:44:13.188411 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2120 23:44:13.191559 [FAST_K] Save calibration result to emmc
2121 23:44:13.195329 [FAST_K] Save calibration result to emmc
2122 23:44:13.198859 dram_init: config_dvfs: 1
2123 23:44:13.202017 dramc_set_vcore_voltage set vcore to 662500
2124 23:44:13.202401 Read voltage for 1200, 2
2125 23:44:13.205557 Vio18 = 0
2126 23:44:13.206050 Vcore = 662500
2127 23:44:13.206366 Vdram = 0
2128 23:44:13.208463 Vddq = 0
2129 23:44:13.208839 Vmddr = 0
2130 23:44:13.211760 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2131 23:44:13.218854 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2132 23:44:13.221682 MEM_TYPE=3, freq_sel=15
2133 23:44:13.225169 sv_algorithm_assistance_LP4_1600
2134 23:44:13.228726 ============ PULL DRAM RESETB DOWN ============
2135 23:44:13.232126 ========== PULL DRAM RESETB DOWN end =========
2136 23:44:13.235391 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2137 23:44:13.238552 ===================================
2138 23:44:13.242241 LPDDR4 DRAM CONFIGURATION
2139 23:44:13.245370 ===================================
2140 23:44:13.249288 EX_ROW_EN[0] = 0x0
2141 23:44:13.249693 EX_ROW_EN[1] = 0x0
2142 23:44:13.252269 LP4Y_EN = 0x0
2143 23:44:13.252729 WORK_FSP = 0x0
2144 23:44:13.255443 WL = 0x4
2145 23:44:13.255968 RL = 0x4
2146 23:44:13.258815 BL = 0x2
2147 23:44:13.259348 RPST = 0x0
2148 23:44:13.262876 RD_PRE = 0x0
2149 23:44:13.263385 WR_PRE = 0x1
2150 23:44:13.265370 WR_PST = 0x0
2151 23:44:13.265916 DBI_WR = 0x0
2152 23:44:13.268845 DBI_RD = 0x0
2153 23:44:13.269373 OTF = 0x1
2154 23:44:13.275729 ===================================
2155 23:44:13.276126 ===================================
2156 23:44:13.279195 ANA top config
2157 23:44:13.282187 ===================================
2158 23:44:13.285632 DLL_ASYNC_EN = 0
2159 23:44:13.286122 ALL_SLAVE_EN = 0
2160 23:44:13.289138 NEW_RANK_MODE = 1
2161 23:44:13.292041 DLL_IDLE_MODE = 1
2162 23:44:13.295775 LP45_APHY_COMB_EN = 1
2163 23:44:13.296206 TX_ODT_DIS = 1
2164 23:44:13.299122 NEW_8X_MODE = 1
2165 23:44:13.302715 ===================================
2166 23:44:13.305900 ===================================
2167 23:44:13.309294 data_rate = 2400
2168 23:44:13.312692 CKR = 1
2169 23:44:13.315890 DQ_P2S_RATIO = 8
2170 23:44:13.319684 ===================================
2171 23:44:13.322332 CA_P2S_RATIO = 8
2172 23:44:13.322739 DQ_CA_OPEN = 0
2173 23:44:13.325834 DQ_SEMI_OPEN = 0
2174 23:44:13.329098 CA_SEMI_OPEN = 0
2175 23:44:13.332679 CA_FULL_RATE = 0
2176 23:44:13.335811 DQ_CKDIV4_EN = 0
2177 23:44:13.339297 CA_CKDIV4_EN = 0
2178 23:44:13.339679 CA_PREDIV_EN = 0
2179 23:44:13.342359 PH8_DLY = 17
2180 23:44:13.345949 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2181 23:44:13.349365 DQ_AAMCK_DIV = 4
2182 23:44:13.352608 CA_AAMCK_DIV = 4
2183 23:44:13.353158 CA_ADMCK_DIV = 4
2184 23:44:13.355681 DQ_TRACK_CA_EN = 0
2185 23:44:13.359163 CA_PICK = 1200
2186 23:44:13.362700 CA_MCKIO = 1200
2187 23:44:13.366100 MCKIO_SEMI = 0
2188 23:44:13.369639 PLL_FREQ = 2366
2189 23:44:13.373317 DQ_UI_PI_RATIO = 32
2190 23:44:13.373702 CA_UI_PI_RATIO = 0
2191 23:44:13.376030 ===================================
2192 23:44:13.379322 ===================================
2193 23:44:13.382635 memory_type:LPDDR4
2194 23:44:13.386371 GP_NUM : 10
2195 23:44:13.386853 SRAM_EN : 1
2196 23:44:13.389458 MD32_EN : 0
2197 23:44:13.392955 ===================================
2198 23:44:13.396609 [ANA_INIT] >>>>>>>>>>>>>>
2199 23:44:13.400024 <<<<<< [CONFIGURE PHASE]: ANA_TX
2200 23:44:13.402556 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2201 23:44:13.406091 ===================================
2202 23:44:13.406473 data_rate = 2400,PCW = 0X5b00
2203 23:44:13.409312 ===================================
2204 23:44:13.413389 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2205 23:44:13.419470 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2206 23:44:13.426245 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2207 23:44:13.429989 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2208 23:44:13.432801 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2209 23:44:13.435971 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2210 23:44:13.439724 [ANA_INIT] flow start
2211 23:44:13.440106 [ANA_INIT] PLL >>>>>>>>
2212 23:44:13.443088 [ANA_INIT] PLL <<<<<<<<
2213 23:44:13.446623 [ANA_INIT] MIDPI >>>>>>>>
2214 23:44:13.447282 [ANA_INIT] MIDPI <<<<<<<<
2215 23:44:13.449611 [ANA_INIT] DLL >>>>>>>>
2216 23:44:13.453466 [ANA_INIT] DLL <<<<<<<<
2217 23:44:13.453901 [ANA_INIT] flow end
2218 23:44:13.459805 ============ LP4 DIFF to SE enter ============
2219 23:44:13.463324 ============ LP4 DIFF to SE exit ============
2220 23:44:13.463710 [ANA_INIT] <<<<<<<<<<<<<
2221 23:44:13.466579 [Flow] Enable top DCM control >>>>>
2222 23:44:13.470030 [Flow] Enable top DCM control <<<<<
2223 23:44:13.473561 Enable DLL master slave shuffle
2224 23:44:13.479856 ==============================================================
2225 23:44:13.480243 Gating Mode config
2226 23:44:13.486507 ==============================================================
2227 23:44:13.490282 Config description:
2228 23:44:13.500025 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2229 23:44:13.506607 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2230 23:44:13.510151 SELPH_MODE 0: By rank 1: By Phase
2231 23:44:13.517067 ==============================================================
2232 23:44:13.520506 GAT_TRACK_EN = 1
2233 23:44:13.520933 RX_GATING_MODE = 2
2234 23:44:13.523525 RX_GATING_TRACK_MODE = 2
2235 23:44:13.526967 SELPH_MODE = 1
2236 23:44:13.530255 PICG_EARLY_EN = 1
2237 23:44:13.533933 VALID_LAT_VALUE = 1
2238 23:44:13.540758 ==============================================================
2239 23:44:13.543794 Enter into Gating configuration >>>>
2240 23:44:13.547143 Exit from Gating configuration <<<<
2241 23:44:13.550594 Enter into DVFS_PRE_config >>>>>
2242 23:44:13.560121 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2243 23:44:13.563450 Exit from DVFS_PRE_config <<<<<
2244 23:44:13.566878 Enter into PICG configuration >>>>
2245 23:44:13.570119 Exit from PICG configuration <<<<
2246 23:44:13.570199 [RX_INPUT] configuration >>>>>
2247 23:44:13.573711 [RX_INPUT] configuration <<<<<
2248 23:44:13.580602 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2249 23:44:13.584155 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2250 23:44:13.590872 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2251 23:44:13.597395 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2252 23:44:13.604257 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2253 23:44:13.610637 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2254 23:44:13.613913 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2255 23:44:13.617198 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2256 23:44:13.620715 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2257 23:44:13.627074 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2258 23:44:13.630717 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2259 23:44:13.634323 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2260 23:44:13.637327 ===================================
2261 23:44:13.640827 LPDDR4 DRAM CONFIGURATION
2262 23:44:13.644105 ===================================
2263 23:44:13.647362 EX_ROW_EN[0] = 0x0
2264 23:44:13.647443 EX_ROW_EN[1] = 0x0
2265 23:44:13.651095 LP4Y_EN = 0x0
2266 23:44:13.651175 WORK_FSP = 0x0
2267 23:44:13.654466 WL = 0x4
2268 23:44:13.654552 RL = 0x4
2269 23:44:13.657954 BL = 0x2
2270 23:44:13.658039 RPST = 0x0
2271 23:44:13.660980 RD_PRE = 0x0
2272 23:44:13.661108 WR_PRE = 0x1
2273 23:44:13.664437 WR_PST = 0x0
2274 23:44:13.664946 DBI_WR = 0x0
2275 23:44:13.667969 DBI_RD = 0x0
2276 23:44:13.668492 OTF = 0x1
2277 23:44:13.671024 ===================================
2278 23:44:13.674748 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2279 23:44:13.681562 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2280 23:44:13.684930 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2281 23:44:13.687991 ===================================
2282 23:44:13.691320 LPDDR4 DRAM CONFIGURATION
2283 23:44:13.695362 ===================================
2284 23:44:13.695872 EX_ROW_EN[0] = 0x10
2285 23:44:13.698630 EX_ROW_EN[1] = 0x0
2286 23:44:13.699039 LP4Y_EN = 0x0
2287 23:44:13.701527 WORK_FSP = 0x0
2288 23:44:13.701997 WL = 0x4
2289 23:44:13.704628 RL = 0x4
2290 23:44:13.705255 BL = 0x2
2291 23:44:13.708327 RPST = 0x0
2292 23:44:13.708738 RD_PRE = 0x0
2293 23:44:13.711783 WR_PRE = 0x1
2294 23:44:13.712188 WR_PST = 0x0
2295 23:44:13.715273 DBI_WR = 0x0
2296 23:44:13.718790 DBI_RD = 0x0
2297 23:44:13.719195 OTF = 0x1
2298 23:44:13.722076 ===================================
2299 23:44:13.728341 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2300 23:44:13.728752 ==
2301 23:44:13.731705 Dram Type= 6, Freq= 0, CH_0, rank 0
2302 23:44:13.735477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2303 23:44:13.735771 ==
2304 23:44:13.738181 [Duty_Offset_Calibration]
2305 23:44:13.738425 B0:2 B1:-1 CA:1
2306 23:44:13.738597
2307 23:44:13.742065 [DutyScan_Calibration_Flow] k_type=0
2308 23:44:13.751423
2309 23:44:13.751574 ==CLK 0==
2310 23:44:13.754732 Final CLK duty delay cell = -4
2311 23:44:13.758235 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2312 23:44:13.761530 [-4] MIN Duty = 4875%(X100), DQS PI = 30
2313 23:44:13.764922 [-4] AVG Duty = 4953%(X100)
2314 23:44:13.765031
2315 23:44:13.767864 CH0 CLK Duty spec in!! Max-Min= 156%
2316 23:44:13.771658 [DutyScan_Calibration_Flow] ====Done====
2317 23:44:13.771758
2318 23:44:13.774526 [DutyScan_Calibration_Flow] k_type=1
2319 23:44:13.790185
2320 23:44:13.790268 ==DQS 0 ==
2321 23:44:13.793907 Final DQS duty delay cell = 0
2322 23:44:13.796843 [0] MAX Duty = 5125%(X100), DQS PI = 48
2323 23:44:13.800220 [0] MIN Duty = 4969%(X100), DQS PI = 12
2324 23:44:13.800303 [0] AVG Duty = 5047%(X100)
2325 23:44:13.803640
2326 23:44:13.803720 ==DQS 1 ==
2327 23:44:13.807022 Final DQS duty delay cell = -4
2328 23:44:13.810540 [-4] MAX Duty = 5124%(X100), DQS PI = 6
2329 23:44:13.813365 [-4] MIN Duty = 5000%(X100), DQS PI = 44
2330 23:44:13.816741 [-4] AVG Duty = 5062%(X100)
2331 23:44:13.816820
2332 23:44:13.820149 CH0 DQS 0 Duty spec in!! Max-Min= 156%
2333 23:44:13.820228
2334 23:44:13.823743 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2335 23:44:13.827263 [DutyScan_Calibration_Flow] ====Done====
2336 23:44:13.827344
2337 23:44:13.830469 [DutyScan_Calibration_Flow] k_type=3
2338 23:44:13.847145
2339 23:44:13.847227 ==DQM 0 ==
2340 23:44:13.850598 Final DQM duty delay cell = 0
2341 23:44:13.853895 [0] MAX Duty = 5000%(X100), DQS PI = 54
2342 23:44:13.857323 [0] MIN Duty = 4875%(X100), DQS PI = 4
2343 23:44:13.857404 [0] AVG Duty = 4937%(X100)
2344 23:44:13.857468
2345 23:44:13.860889 ==DQM 1 ==
2346 23:44:13.863893 Final DQM duty delay cell = 0
2347 23:44:13.867087 [0] MAX Duty = 5124%(X100), DQS PI = 62
2348 23:44:13.870708 [0] MIN Duty = 4969%(X100), DQS PI = 8
2349 23:44:13.870789 [0] AVG Duty = 5046%(X100)
2350 23:44:13.870852
2351 23:44:13.877113 CH0 DQM 0 Duty spec in!! Max-Min= 125%
2352 23:44:13.877192
2353 23:44:13.880708 CH0 DQM 1 Duty spec in!! Max-Min= 155%
2354 23:44:13.883902 [DutyScan_Calibration_Flow] ====Done====
2355 23:44:13.883983
2356 23:44:13.887280 [DutyScan_Calibration_Flow] k_type=2
2357 23:44:13.902767
2358 23:44:13.902848 ==DQ 0 ==
2359 23:44:13.905978 Final DQ duty delay cell = -4
2360 23:44:13.909319 [-4] MAX Duty = 5031%(X100), DQS PI = 38
2361 23:44:13.912864 [-4] MIN Duty = 4844%(X100), DQS PI = 18
2362 23:44:13.916623 [-4] AVG Duty = 4937%(X100)
2363 23:44:13.916703
2364 23:44:13.916766 ==DQ 1 ==
2365 23:44:13.919562 Final DQ duty delay cell = 0
2366 23:44:13.922784 [0] MAX Duty = 5031%(X100), DQS PI = 18
2367 23:44:13.926025 [0] MIN Duty = 4907%(X100), DQS PI = 46
2368 23:44:13.926110 [0] AVG Duty = 4969%(X100)
2369 23:44:13.926174
2370 23:44:13.929603 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2371 23:44:13.933012
2372 23:44:13.933106 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2373 23:44:13.939798 [DutyScan_Calibration_Flow] ====Done====
2374 23:44:13.939880 ==
2375 23:44:13.943317 Dram Type= 6, Freq= 0, CH_1, rank 0
2376 23:44:13.946740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2377 23:44:13.946822 ==
2378 23:44:13.949611 [Duty_Offset_Calibration]
2379 23:44:13.949693 B0:1 B1:1 CA:2
2380 23:44:13.949756
2381 23:44:13.953139 [DutyScan_Calibration_Flow] k_type=0
2382 23:44:13.962922
2383 23:44:13.963003 ==CLK 0==
2384 23:44:13.966272 Final CLK duty delay cell = 0
2385 23:44:13.969952 [0] MAX Duty = 5125%(X100), DQS PI = 24
2386 23:44:13.973297 [0] MIN Duty = 4938%(X100), DQS PI = 40
2387 23:44:13.976574 [0] AVG Duty = 5031%(X100)
2388 23:44:13.976655
2389 23:44:13.979822 CH1 CLK Duty spec in!! Max-Min= 187%
2390 23:44:13.982906 [DutyScan_Calibration_Flow] ====Done====
2391 23:44:13.982987
2392 23:44:13.986032 [DutyScan_Calibration_Flow] k_type=1
2393 23:44:14.002211
2394 23:44:14.002295 ==DQS 0 ==
2395 23:44:14.005947 Final DQS duty delay cell = 0
2396 23:44:14.008934 [0] MAX Duty = 5031%(X100), DQS PI = 18
2397 23:44:14.012694 [0] MIN Duty = 4813%(X100), DQS PI = 48
2398 23:44:14.012774 [0] AVG Duty = 4922%(X100)
2399 23:44:14.016228
2400 23:44:14.016312 ==DQS 1 ==
2401 23:44:14.019140 Final DQS duty delay cell = 0
2402 23:44:14.022507 [0] MAX Duty = 5062%(X100), DQS PI = 36
2403 23:44:14.026003 [0] MIN Duty = 4875%(X100), DQS PI = 16
2404 23:44:14.026085 [0] AVG Duty = 4968%(X100)
2405 23:44:14.029290
2406 23:44:14.032809 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2407 23:44:14.032892
2408 23:44:14.035980 CH1 DQS 1 Duty spec in!! Max-Min= 187%
2409 23:44:14.039463 [DutyScan_Calibration_Flow] ====Done====
2410 23:44:14.039544
2411 23:44:14.042918 [DutyScan_Calibration_Flow] k_type=3
2412 23:44:14.058980
2413 23:44:14.059061 ==DQM 0 ==
2414 23:44:14.061995 Final DQM duty delay cell = 0
2415 23:44:14.065526 [0] MAX Duty = 5093%(X100), DQS PI = 16
2416 23:44:14.069032 [0] MIN Duty = 4875%(X100), DQS PI = 48
2417 23:44:14.069113 [0] AVG Duty = 4984%(X100)
2418 23:44:14.072337
2419 23:44:14.072417 ==DQM 1 ==
2420 23:44:14.075844 Final DQM duty delay cell = 0
2421 23:44:14.079142 [0] MAX Duty = 5156%(X100), DQS PI = 62
2422 23:44:14.082492 [0] MIN Duty = 4938%(X100), DQS PI = 22
2423 23:44:14.082573 [0] AVG Duty = 5047%(X100)
2424 23:44:14.085698
2425 23:44:14.088907 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2426 23:44:14.089015
2427 23:44:14.092356 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2428 23:44:14.095912 [DutyScan_Calibration_Flow] ====Done====
2429 23:44:14.095996
2430 23:44:14.099541 [DutyScan_Calibration_Flow] k_type=2
2431 23:44:14.115533
2432 23:44:14.115616 ==DQ 0 ==
2433 23:44:14.119066 Final DQ duty delay cell = 0
2434 23:44:14.122146 [0] MAX Duty = 5124%(X100), DQS PI = 18
2435 23:44:14.125626 [0] MIN Duty = 4938%(X100), DQS PI = 50
2436 23:44:14.125712 [0] AVG Duty = 5031%(X100)
2437 23:44:14.125776
2438 23:44:14.128946 ==DQ 1 ==
2439 23:44:14.132522 Final DQ duty delay cell = 0
2440 23:44:14.135484 [0] MAX Duty = 5093%(X100), DQS PI = 8
2441 23:44:14.138967 [0] MIN Duty = 5031%(X100), DQS PI = 2
2442 23:44:14.139049 [0] AVG Duty = 5062%(X100)
2443 23:44:14.139113
2444 23:44:14.142488 CH1 DQ 0 Duty spec in!! Max-Min= 186%
2445 23:44:14.142569
2446 23:44:14.145779 CH1 DQ 1 Duty spec in!! Max-Min= 62%
2447 23:44:14.149408 [DutyScan_Calibration_Flow] ====Done====
2448 23:44:14.154603 nWR fixed to 30
2449 23:44:14.157961 [ModeRegInit_LP4] CH0 RK0
2450 23:44:14.158042 [ModeRegInit_LP4] CH0 RK1
2451 23:44:14.161305 [ModeRegInit_LP4] CH1 RK0
2452 23:44:14.164378 [ModeRegInit_LP4] CH1 RK1
2453 23:44:14.164488 match AC timing 7
2454 23:44:14.171096 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2455 23:44:14.174471 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2456 23:44:14.177855 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2457 23:44:14.184380 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2458 23:44:14.187760 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2459 23:44:14.187859 ==
2460 23:44:14.191436 Dram Type= 6, Freq= 0, CH_0, rank 0
2461 23:44:14.194523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2462 23:44:14.194608 ==
2463 23:44:14.201351 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2464 23:44:14.207714 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2465 23:44:14.215782 [CA 0] Center 40 (10~71) winsize 62
2466 23:44:14.218684 [CA 1] Center 39 (9~70) winsize 62
2467 23:44:14.221985 [CA 2] Center 36 (6~67) winsize 62
2468 23:44:14.225413 [CA 3] Center 36 (5~67) winsize 63
2469 23:44:14.228626 [CA 4] Center 35 (5~65) winsize 61
2470 23:44:14.232094 [CA 5] Center 34 (4~64) winsize 61
2471 23:44:14.232175
2472 23:44:14.235287 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2473 23:44:14.235368
2474 23:44:14.238704 [CATrainingPosCal] consider 1 rank data
2475 23:44:14.242058 u2DelayCellTimex100 = 270/100 ps
2476 23:44:14.245885 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2477 23:44:14.248852 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2478 23:44:14.255705 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2479 23:44:14.258955 CA3 delay=36 (5~67),Diff = 2 PI (9 cell)
2480 23:44:14.262364 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2481 23:44:14.265501 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2482 23:44:14.265582
2483 23:44:14.268900 CA PerBit enable=1, Macro0, CA PI delay=34
2484 23:44:14.268988
2485 23:44:14.272228 [CBTSetCACLKResult] CA Dly = 34
2486 23:44:14.272309 CS Dly: 7 (0~38)
2487 23:44:14.272374 ==
2488 23:44:14.275892 Dram Type= 6, Freq= 0, CH_0, rank 1
2489 23:44:14.282455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2490 23:44:14.282563 ==
2491 23:44:14.285395 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2492 23:44:14.292178 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2493 23:44:14.301540 [CA 0] Center 39 (9~70) winsize 62
2494 23:44:14.304559 [CA 1] Center 40 (10~70) winsize 61
2495 23:44:14.308102 [CA 2] Center 36 (6~67) winsize 62
2496 23:44:14.311466 [CA 3] Center 35 (5~66) winsize 62
2497 23:44:14.314920 [CA 4] Center 34 (4~65) winsize 62
2498 23:44:14.317949 [CA 5] Center 34 (4~64) winsize 61
2499 23:44:14.318056
2500 23:44:14.321172 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2501 23:44:14.321253
2502 23:44:14.324919 [CATrainingPosCal] consider 2 rank data
2503 23:44:14.328204 u2DelayCellTimex100 = 270/100 ps
2504 23:44:14.331674 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2505 23:44:14.334784 CA1 delay=40 (10~70),Diff = 6 PI (28 cell)
2506 23:44:14.341334 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2507 23:44:14.344896 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2508 23:44:14.348231 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2509 23:44:14.351744 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2510 23:44:14.351827
2511 23:44:14.354419 CA PerBit enable=1, Macro0, CA PI delay=34
2512 23:44:14.354500
2513 23:44:14.358273 [CBTSetCACLKResult] CA Dly = 34
2514 23:44:14.358355 CS Dly: 8 (0~41)
2515 23:44:14.358419
2516 23:44:14.361219 ----->DramcWriteLeveling(PI) begin...
2517 23:44:14.365074 ==
2518 23:44:14.367975 Dram Type= 6, Freq= 0, CH_0, rank 0
2519 23:44:14.371625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2520 23:44:14.371708 ==
2521 23:44:14.375056 Write leveling (Byte 0): 31 => 31
2522 23:44:14.378155 Write leveling (Byte 1): 29 => 29
2523 23:44:14.381362 DramcWriteLeveling(PI) end<-----
2524 23:44:14.381446
2525 23:44:14.381510 ==
2526 23:44:14.384770 Dram Type= 6, Freq= 0, CH_0, rank 0
2527 23:44:14.388224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2528 23:44:14.388332 ==
2529 23:44:14.391820 [Gating] SW mode calibration
2530 23:44:14.398216 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2531 23:44:14.401837 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2532 23:44:14.408784 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2533 23:44:14.411513 0 15 4 | B1->B0 | 2424 3030 | 0 1 | (0 0) (1 1)
2534 23:44:14.415147 0 15 8 | B1->B0 | 3433 3434 | 1 1 | (1 1) (1 1)
2535 23:44:14.421502 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2536 23:44:14.424964 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2537 23:44:14.428698 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2538 23:44:14.435366 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2539 23:44:14.438752 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2540 23:44:14.442218 1 0 0 | B1->B0 | 3434 3131 | 1 1 | (1 0) (1 0)
2541 23:44:14.445283 1 0 4 | B1->B0 | 2626 2323 | 0 0 | (1 0) (1 0)
2542 23:44:14.452242 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2543 23:44:14.455194 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2544 23:44:14.458835 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2545 23:44:14.465629 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2546 23:44:14.469120 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2547 23:44:14.472906 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2548 23:44:14.478774 1 1 0 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
2549 23:44:14.482621 1 1 4 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
2550 23:44:14.485478 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2551 23:44:14.492311 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2552 23:44:14.495705 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2553 23:44:14.498998 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2554 23:44:14.502542 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2555 23:44:14.509229 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2556 23:44:14.512768 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2557 23:44:14.515835 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2558 23:44:14.523002 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2559 23:44:14.526339 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 23:44:14.529322 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 23:44:14.536211 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 23:44:14.539287 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 23:44:14.542735 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 23:44:14.549957 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 23:44:14.553038 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 23:44:14.556157 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 23:44:14.559437 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 23:44:14.566467 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 23:44:14.569535 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 23:44:14.573238 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 23:44:14.579567 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 23:44:14.583044 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2573 23:44:14.586528 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2574 23:44:14.589541 Total UI for P1: 0, mck2ui 16
2575 23:44:14.592920 best dqsien dly found for B0: ( 1, 4, 0)
2576 23:44:14.599755 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2577 23:44:14.599837 Total UI for P1: 0, mck2ui 16
2578 23:44:14.606287 best dqsien dly found for B1: ( 1, 4, 2)
2579 23:44:14.610067 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2580 23:44:14.613227 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2581 23:44:14.613308
2582 23:44:14.616497 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2583 23:44:14.620055 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2584 23:44:14.622964 [Gating] SW calibration Done
2585 23:44:14.623044 ==
2586 23:44:14.626596 Dram Type= 6, Freq= 0, CH_0, rank 0
2587 23:44:14.629948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2588 23:44:14.630030 ==
2589 23:44:14.630094 RX Vref Scan: 0
2590 23:44:14.633200
2591 23:44:14.633283 RX Vref 0 -> 0, step: 1
2592 23:44:14.633346
2593 23:44:14.636510 RX Delay -40 -> 252, step: 8
2594 23:44:14.640088 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2595 23:44:14.643437 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2596 23:44:14.649739 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2597 23:44:14.653600 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2598 23:44:14.656687 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2599 23:44:14.659776 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2600 23:44:14.663199 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2601 23:44:14.666809 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2602 23:44:14.673523 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2603 23:44:14.677173 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2604 23:44:14.680229 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2605 23:44:14.683632 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2606 23:44:14.686882 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2607 23:44:14.693340 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2608 23:44:14.697323 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2609 23:44:14.700198 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2610 23:44:14.700279 ==
2611 23:44:14.703759 Dram Type= 6, Freq= 0, CH_0, rank 0
2612 23:44:14.706763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2613 23:44:14.706848 ==
2614 23:44:14.710435 DQS Delay:
2615 23:44:14.710516 DQS0 = 0, DQS1 = 0
2616 23:44:14.713909 DQM Delay:
2617 23:44:14.713990 DQM0 = 116, DQM1 = 107
2618 23:44:14.714053 DQ Delay:
2619 23:44:14.717218 DQ0 =115, DQ1 =115, DQ2 =115, DQ3 =111
2620 23:44:14.723760 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
2621 23:44:14.727731 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2622 23:44:14.730697 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2623 23:44:14.730779
2624 23:44:14.730843
2625 23:44:14.730903 ==
2626 23:44:14.734095 Dram Type= 6, Freq= 0, CH_0, rank 0
2627 23:44:14.737345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2628 23:44:14.737426 ==
2629 23:44:14.737490
2630 23:44:14.737550
2631 23:44:14.740778 TX Vref Scan disable
2632 23:44:14.740859 == TX Byte 0 ==
2633 23:44:14.747398 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2634 23:44:14.752260 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2635 23:44:14.752342 == TX Byte 1 ==
2636 23:44:14.757265 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2637 23:44:14.760733 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2638 23:44:14.760815 ==
2639 23:44:14.763978 Dram Type= 6, Freq= 0, CH_0, rank 0
2640 23:44:14.767509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2641 23:44:14.767591 ==
2642 23:44:14.780262 TX Vref=22, minBit 1, minWin=25, winSum=418
2643 23:44:14.783534 TX Vref=24, minBit 5, minWin=25, winSum=425
2644 23:44:14.787163 TX Vref=26, minBit 12, minWin=25, winSum=429
2645 23:44:14.790575 TX Vref=28, minBit 0, minWin=26, winSum=433
2646 23:44:14.794128 TX Vref=30, minBit 1, minWin=26, winSum=435
2647 23:44:14.796928 TX Vref=32, minBit 1, minWin=26, winSum=436
2648 23:44:14.803516 [TxChooseVref] Worse bit 1, Min win 26, Win sum 436, Final Vref 32
2649 23:44:14.803597
2650 23:44:14.806958 Final TX Range 1 Vref 32
2651 23:44:14.807077
2652 23:44:14.807141 ==
2653 23:44:14.810727 Dram Type= 6, Freq= 0, CH_0, rank 0
2654 23:44:14.813549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2655 23:44:14.813631 ==
2656 23:44:14.813694
2657 23:44:14.813777
2658 23:44:14.817179 TX Vref Scan disable
2659 23:44:14.820629 == TX Byte 0 ==
2660 23:44:14.823792 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2661 23:44:14.827617 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2662 23:44:14.830658 == TX Byte 1 ==
2663 23:44:14.834046 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2664 23:44:14.837445 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2665 23:44:14.837527
2666 23:44:14.841071 [DATLAT]
2667 23:44:14.841152 Freq=1200, CH0 RK0
2668 23:44:14.841216
2669 23:44:14.843811 DATLAT Default: 0xd
2670 23:44:14.843892 0, 0xFFFF, sum = 0
2671 23:44:14.847509 1, 0xFFFF, sum = 0
2672 23:44:14.847591 2, 0xFFFF, sum = 0
2673 23:44:14.850765 3, 0xFFFF, sum = 0
2674 23:44:14.850848 4, 0xFFFF, sum = 0
2675 23:44:14.854490 5, 0xFFFF, sum = 0
2676 23:44:14.854575 6, 0xFFFF, sum = 0
2677 23:44:14.857849 7, 0xFFFF, sum = 0
2678 23:44:14.857931 8, 0xFFFF, sum = 0
2679 23:44:14.860898 9, 0xFFFF, sum = 0
2680 23:44:14.860987 10, 0xFFFF, sum = 0
2681 23:44:14.863985 11, 0xFFFF, sum = 0
2682 23:44:14.864067 12, 0x0, sum = 1
2683 23:44:14.868121 13, 0x0, sum = 2
2684 23:44:14.868203 14, 0x0, sum = 3
2685 23:44:14.870778 15, 0x0, sum = 4
2686 23:44:14.870859 best_step = 13
2687 23:44:14.870923
2688 23:44:14.870981 ==
2689 23:44:14.874462 Dram Type= 6, Freq= 0, CH_0, rank 0
2690 23:44:14.877921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2691 23:44:14.881006 ==
2692 23:44:14.881101 RX Vref Scan: 1
2693 23:44:14.881165
2694 23:44:14.884927 Set Vref Range= 32 -> 127
2695 23:44:14.885055
2696 23:44:14.888814 RX Vref 32 -> 127, step: 1
2697 23:44:14.888928
2698 23:44:14.889047 RX Delay -21 -> 252, step: 4
2699 23:44:14.889109
2700 23:44:14.891044 Set Vref, RX VrefLevel [Byte0]: 32
2701 23:44:14.894581 [Byte1]: 32
2702 23:44:14.898678
2703 23:44:14.898790 Set Vref, RX VrefLevel [Byte0]: 33
2704 23:44:14.901719 [Byte1]: 33
2705 23:44:14.906513
2706 23:44:14.906594 Set Vref, RX VrefLevel [Byte0]: 34
2707 23:44:14.909801 [Byte1]: 34
2708 23:44:14.914430
2709 23:44:14.914511 Set Vref, RX VrefLevel [Byte0]: 35
2710 23:44:14.918008 [Byte1]: 35
2711 23:44:14.922161
2712 23:44:14.922241 Set Vref, RX VrefLevel [Byte0]: 36
2713 23:44:14.925766 [Byte1]: 36
2714 23:44:14.930331
2715 23:44:14.930412 Set Vref, RX VrefLevel [Byte0]: 37
2716 23:44:14.933398 [Byte1]: 37
2717 23:44:14.937914
2718 23:44:14.937994 Set Vref, RX VrefLevel [Byte0]: 38
2719 23:44:14.941669 [Byte1]: 38
2720 23:44:14.945935
2721 23:44:14.946016 Set Vref, RX VrefLevel [Byte0]: 39
2722 23:44:14.949386 [Byte1]: 39
2723 23:44:14.953828
2724 23:44:14.953934 Set Vref, RX VrefLevel [Byte0]: 40
2725 23:44:14.957568 [Byte1]: 40
2726 23:44:14.961697
2727 23:44:14.961778 Set Vref, RX VrefLevel [Byte0]: 41
2728 23:44:14.964935 [Byte1]: 41
2729 23:44:14.969747
2730 23:44:14.969829 Set Vref, RX VrefLevel [Byte0]: 42
2731 23:44:14.973128 [Byte1]: 42
2732 23:44:14.977603
2733 23:44:14.977684 Set Vref, RX VrefLevel [Byte0]: 43
2734 23:44:14.981028 [Byte1]: 43
2735 23:44:14.985597
2736 23:44:14.985679 Set Vref, RX VrefLevel [Byte0]: 44
2737 23:44:14.988730 [Byte1]: 44
2738 23:44:14.993790
2739 23:44:14.993886 Set Vref, RX VrefLevel [Byte0]: 45
2740 23:44:14.996673 [Byte1]: 45
2741 23:44:15.001537
2742 23:44:15.001617 Set Vref, RX VrefLevel [Byte0]: 46
2743 23:44:15.005400 [Byte1]: 46
2744 23:44:15.009683
2745 23:44:15.009763 Set Vref, RX VrefLevel [Byte0]: 47
2746 23:44:15.013014 [Byte1]: 47
2747 23:44:15.017177
2748 23:44:15.017256 Set Vref, RX VrefLevel [Byte0]: 48
2749 23:44:15.020701 [Byte1]: 48
2750 23:44:15.025276
2751 23:44:15.028287 Set Vref, RX VrefLevel [Byte0]: 49
2752 23:44:15.028371 [Byte1]: 49
2753 23:44:15.033125
2754 23:44:15.033207 Set Vref, RX VrefLevel [Byte0]: 50
2755 23:44:15.036828 [Byte1]: 50
2756 23:44:15.041314
2757 23:44:15.041399 Set Vref, RX VrefLevel [Byte0]: 51
2758 23:44:15.044678 [Byte1]: 51
2759 23:44:15.049553
2760 23:44:15.049632 Set Vref, RX VrefLevel [Byte0]: 52
2761 23:44:15.052403 [Byte1]: 52
2762 23:44:15.057053
2763 23:44:15.057132 Set Vref, RX VrefLevel [Byte0]: 53
2764 23:44:15.060533 [Byte1]: 53
2765 23:44:15.064644
2766 23:44:15.064724 Set Vref, RX VrefLevel [Byte0]: 54
2767 23:44:15.068265 [Byte1]: 54
2768 23:44:15.072971
2769 23:44:15.073093 Set Vref, RX VrefLevel [Byte0]: 55
2770 23:44:15.076060 [Byte1]: 55
2771 23:44:15.080678
2772 23:44:15.080758 Set Vref, RX VrefLevel [Byte0]: 56
2773 23:44:15.083862 [Byte1]: 56
2774 23:44:15.088905
2775 23:44:15.089045 Set Vref, RX VrefLevel [Byte0]: 57
2776 23:44:15.092058 [Byte1]: 57
2777 23:44:15.096671
2778 23:44:15.096750 Set Vref, RX VrefLevel [Byte0]: 58
2779 23:44:15.099858 [Byte1]: 58
2780 23:44:15.104485
2781 23:44:15.104564 Set Vref, RX VrefLevel [Byte0]: 59
2782 23:44:15.107878 [Byte1]: 59
2783 23:44:15.112697
2784 23:44:15.112784 Set Vref, RX VrefLevel [Byte0]: 60
2785 23:44:15.115740 [Byte1]: 60
2786 23:44:15.120384
2787 23:44:15.120463 Set Vref, RX VrefLevel [Byte0]: 61
2788 23:44:15.123530 [Byte1]: 61
2789 23:44:15.128362
2790 23:44:15.128442 Set Vref, RX VrefLevel [Byte0]: 62
2791 23:44:15.131785 [Byte1]: 62
2792 23:44:15.136033
2793 23:44:15.136113 Set Vref, RX VrefLevel [Byte0]: 63
2794 23:44:15.140686 [Byte1]: 63
2795 23:44:15.144148
2796 23:44:15.144227 Set Vref, RX VrefLevel [Byte0]: 64
2797 23:44:15.147586 [Byte1]: 64
2798 23:44:15.152134
2799 23:44:15.152214 Set Vref, RX VrefLevel [Byte0]: 65
2800 23:44:15.155813 [Byte1]: 65
2801 23:44:15.160453
2802 23:44:15.160532 Set Vref, RX VrefLevel [Byte0]: 66
2803 23:44:15.163412 [Byte1]: 66
2804 23:44:15.167795
2805 23:44:15.167875 Set Vref, RX VrefLevel [Byte0]: 67
2806 23:44:15.171485 [Byte1]: 67
2807 23:44:15.175745
2808 23:44:15.175846 Set Vref, RX VrefLevel [Byte0]: 68
2809 23:44:15.179308 [Byte1]: 68
2810 23:44:15.183733
2811 23:44:15.183812 Final RX Vref Byte 0 = 54 to rank0
2812 23:44:15.187288 Final RX Vref Byte 1 = 51 to rank0
2813 23:44:15.190837 Final RX Vref Byte 0 = 54 to rank1
2814 23:44:15.194186 Final RX Vref Byte 1 = 51 to rank1==
2815 23:44:15.197134 Dram Type= 6, Freq= 0, CH_0, rank 0
2816 23:44:15.200793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2817 23:44:15.204285 ==
2818 23:44:15.204355 DQS Delay:
2819 23:44:15.204415 DQS0 = 0, DQS1 = 0
2820 23:44:15.207476 DQM Delay:
2821 23:44:15.207543 DQM0 = 114, DQM1 = 104
2822 23:44:15.210636 DQ Delay:
2823 23:44:15.214616 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =112
2824 23:44:15.217905 DQ4 =116, DQ5 =108, DQ6 =120, DQ7 =122
2825 23:44:15.221183 DQ8 =92, DQ9 =90, DQ10 =104, DQ11 =96
2826 23:44:15.224512 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
2827 23:44:15.224662
2828 23:44:15.224751
2829 23:44:15.231256 [DQSOSCAuto] RK0, (LSB)MR18= 0xfeed, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 410 ps
2830 23:44:15.234819 CH0 RK0: MR19=303, MR18=FEED
2831 23:44:15.240968 CH0_RK0: MR19=0x303, MR18=0xFEED, DQSOSC=410, MR23=63, INC=39, DEC=26
2832 23:44:15.241177
2833 23:44:15.244451 ----->DramcWriteLeveling(PI) begin...
2834 23:44:15.244602 ==
2835 23:44:15.248107 Dram Type= 6, Freq= 0, CH_0, rank 1
2836 23:44:15.250986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2837 23:44:15.251156 ==
2838 23:44:15.254598 Write leveling (Byte 0): 29 => 29
2839 23:44:15.257570 Write leveling (Byte 1): 29 => 29
2840 23:44:15.261709 DramcWriteLeveling(PI) end<-----
2841 23:44:15.261943
2842 23:44:15.262129 ==
2843 23:44:15.264739 Dram Type= 6, Freq= 0, CH_0, rank 1
2844 23:44:15.268069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2845 23:44:15.271693 ==
2846 23:44:15.272072 [Gating] SW mode calibration
2847 23:44:15.277992 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2848 23:44:15.284679 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2849 23:44:15.288085 0 15 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
2850 23:44:15.294987 0 15 4 | B1->B0 | 2a2a 3434 | 1 1 | (1 1) (1 1)
2851 23:44:15.298473 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2852 23:44:15.301760 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2853 23:44:15.305288 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2854 23:44:15.311798 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2855 23:44:15.315005 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2856 23:44:15.318246 0 15 28 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 0)
2857 23:44:15.325258 1 0 0 | B1->B0 | 2c2c 2424 | 0 0 | (0 0) (1 1)
2858 23:44:15.328632 1 0 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
2859 23:44:15.331755 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2860 23:44:15.338732 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2861 23:44:15.342010 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2862 23:44:15.345075 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2863 23:44:15.351718 1 0 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
2864 23:44:15.355382 1 0 28 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
2865 23:44:15.358482 1 1 0 | B1->B0 | 2f2f 3a3a | 0 1 | (0 0) (0 0)
2866 23:44:15.365343 1 1 4 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
2867 23:44:15.368673 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2868 23:44:15.372100 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2869 23:44:15.375678 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2870 23:44:15.381793 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2871 23:44:15.385607 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2872 23:44:15.388807 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2873 23:44:15.395400 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2874 23:44:15.398584 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2875 23:44:15.401890 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 23:44:15.408713 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 23:44:15.412377 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 23:44:15.415488 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 23:44:15.422489 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 23:44:15.425317 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 23:44:15.428870 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 23:44:15.435688 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 23:44:15.438855 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 23:44:15.442288 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 23:44:15.445813 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 23:44:15.452020 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 23:44:15.456258 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2888 23:44:15.459051 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2889 23:44:15.465718 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2890 23:44:15.468602 Total UI for P1: 0, mck2ui 16
2891 23:44:15.472017 best dqsien dly found for B0: ( 1, 3, 26)
2892 23:44:15.475520 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2893 23:44:15.479183 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2894 23:44:15.482472 Total UI for P1: 0, mck2ui 16
2895 23:44:15.485733 best dqsien dly found for B1: ( 1, 4, 2)
2896 23:44:15.489224 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2897 23:44:15.492557 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2898 23:44:15.493209
2899 23:44:15.495619 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2900 23:44:15.502415 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2901 23:44:15.502830 [Gating] SW calibration Done
2902 23:44:15.503160 ==
2903 23:44:15.506270 Dram Type= 6, Freq= 0, CH_0, rank 1
2904 23:44:15.512855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2905 23:44:15.513332 ==
2906 23:44:15.513669 RX Vref Scan: 0
2907 23:44:15.513983
2908 23:44:15.516336 RX Vref 0 -> 0, step: 1
2909 23:44:15.516746
2910 23:44:15.519329 RX Delay -40 -> 252, step: 8
2911 23:44:15.522298 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2912 23:44:15.525916 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2913 23:44:15.529087 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2914 23:44:15.532856 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2915 23:44:15.539151 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2916 23:44:15.543170 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2917 23:44:15.546186 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2918 23:44:15.550243 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2919 23:44:15.552553 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2920 23:44:15.559774 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2921 23:44:15.562952 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2922 23:44:15.566481 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2923 23:44:15.569284 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2924 23:44:15.573125 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2925 23:44:15.579637 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2926 23:44:15.583203 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2927 23:44:15.583622 ==
2928 23:44:15.586664 Dram Type= 6, Freq= 0, CH_0, rank 1
2929 23:44:15.589923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2930 23:44:15.590342 ==
2931 23:44:15.590669 DQS Delay:
2932 23:44:15.593100 DQS0 = 0, DQS1 = 0
2933 23:44:15.593519 DQM Delay:
2934 23:44:15.597071 DQM0 = 115, DQM1 = 105
2935 23:44:15.597487 DQ Delay:
2936 23:44:15.600094 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
2937 23:44:15.603258 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2938 23:44:15.606368 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
2939 23:44:15.609606 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2940 23:44:15.610024
2941 23:44:15.610353
2942 23:44:15.612861 ==
2943 23:44:15.616356 Dram Type= 6, Freq= 0, CH_0, rank 1
2944 23:44:15.620001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2945 23:44:15.620418 ==
2946 23:44:15.620746
2947 23:44:15.621081
2948 23:44:15.623446 TX Vref Scan disable
2949 23:44:15.623856 == TX Byte 0 ==
2950 23:44:15.626293 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2951 23:44:15.633257 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2952 23:44:15.633676 == TX Byte 1 ==
2953 23:44:15.637007 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2954 23:44:15.643681 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2955 23:44:15.644188 ==
2956 23:44:15.647031 Dram Type= 6, Freq= 0, CH_0, rank 1
2957 23:44:15.650305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2958 23:44:15.650718 ==
2959 23:44:15.662019 TX Vref=22, minBit 4, minWin=25, winSum=427
2960 23:44:15.665410 TX Vref=24, minBit 5, minWin=26, winSum=435
2961 23:44:15.668145 TX Vref=26, minBit 0, minWin=26, winSum=431
2962 23:44:15.671819 TX Vref=28, minBit 14, minWin=26, winSum=437
2963 23:44:15.674877 TX Vref=30, minBit 0, minWin=27, winSum=441
2964 23:44:15.678329 TX Vref=32, minBit 12, minWin=26, winSum=440
2965 23:44:15.684928 [TxChooseVref] Worse bit 0, Min win 27, Win sum 441, Final Vref 30
2966 23:44:15.685413
2967 23:44:15.688297 Final TX Range 1 Vref 30
2968 23:44:15.688707
2969 23:44:15.689073 ==
2970 23:44:15.691735 Dram Type= 6, Freq= 0, CH_0, rank 1
2971 23:44:15.695151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2972 23:44:15.695577 ==
2973 23:44:15.695901
2974 23:44:15.696200
2975 23:44:15.698544 TX Vref Scan disable
2976 23:44:15.701759 == TX Byte 0 ==
2977 23:44:15.705117 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2978 23:44:15.708274 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2979 23:44:15.711739 == TX Byte 1 ==
2980 23:44:15.715167 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2981 23:44:15.718743 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2982 23:44:15.719292
2983 23:44:15.722236 [DATLAT]
2984 23:44:15.722775 Freq=1200, CH0 RK1
2985 23:44:15.723123
2986 23:44:15.725365 DATLAT Default: 0xd
2987 23:44:15.725939 0, 0xFFFF, sum = 0
2988 23:44:15.728605 1, 0xFFFF, sum = 0
2989 23:44:15.729064 2, 0xFFFF, sum = 0
2990 23:44:15.732199 3, 0xFFFF, sum = 0
2991 23:44:15.732688 4, 0xFFFF, sum = 0
2992 23:44:15.735113 5, 0xFFFF, sum = 0
2993 23:44:15.735531 6, 0xFFFF, sum = 0
2994 23:44:15.738503 7, 0xFFFF, sum = 0
2995 23:44:15.738920 8, 0xFFFF, sum = 0
2996 23:44:15.742590 9, 0xFFFF, sum = 0
2997 23:44:15.743011 10, 0xFFFF, sum = 0
2998 23:44:15.745340 11, 0xFFFF, sum = 0
2999 23:44:15.745759 12, 0x0, sum = 1
3000 23:44:15.748946 13, 0x0, sum = 2
3001 23:44:15.749408 14, 0x0, sum = 3
3002 23:44:15.752010 15, 0x0, sum = 4
3003 23:44:15.752526 best_step = 13
3004 23:44:15.752858
3005 23:44:15.753214 ==
3006 23:44:15.755135 Dram Type= 6, Freq= 0, CH_0, rank 1
3007 23:44:15.762148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3008 23:44:15.762565 ==
3009 23:44:15.762890 RX Vref Scan: 0
3010 23:44:15.763196
3011 23:44:15.765309 RX Vref 0 -> 0, step: 1
3012 23:44:15.765720
3013 23:44:15.769096 RX Delay -21 -> 252, step: 4
3014 23:44:15.772591 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3015 23:44:15.775486 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3016 23:44:15.782044 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3017 23:44:15.785489 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3018 23:44:15.789220 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3019 23:44:15.792360 iDelay=195, Bit 5, Center 104 (35 ~ 174) 140
3020 23:44:15.796060 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3021 23:44:15.799276 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
3022 23:44:15.805712 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3023 23:44:15.809289 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3024 23:44:15.812858 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3025 23:44:15.816022 iDelay=195, Bit 11, Center 96 (31 ~ 162) 132
3026 23:44:15.819496 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3027 23:44:15.826171 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3028 23:44:15.829079 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3029 23:44:15.832581 iDelay=195, Bit 15, Center 114 (47 ~ 182) 136
3030 23:44:15.833093 ==
3031 23:44:15.835863 Dram Type= 6, Freq= 0, CH_0, rank 1
3032 23:44:15.839455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3033 23:44:15.839873 ==
3034 23:44:15.842720 DQS Delay:
3035 23:44:15.843133 DQS0 = 0, DQS1 = 0
3036 23:44:15.843462 DQM Delay:
3037 23:44:15.846029 DQM0 = 114, DQM1 = 104
3038 23:44:15.846441 DQ Delay:
3039 23:44:15.849068 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3040 23:44:15.852727 DQ4 =112, DQ5 =104, DQ6 =122, DQ7 =122
3041 23:44:15.855970 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =96
3042 23:44:15.862425 DQ12 =110, DQ13 =110, DQ14 =116, DQ15 =114
3043 23:44:15.862839
3044 23:44:15.863166
3045 23:44:15.869331 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f2, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 409 ps
3046 23:44:15.872259 CH0 RK1: MR19=403, MR18=2F2
3047 23:44:15.879508 CH0_RK1: MR19=0x403, MR18=0x2F2, DQSOSC=409, MR23=63, INC=39, DEC=26
3048 23:44:15.882957 [RxdqsGatingPostProcess] freq 1200
3049 23:44:15.885869 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3050 23:44:15.889888 best DQS0 dly(2T, 0.5T) = (0, 12)
3051 23:44:15.892672 best DQS1 dly(2T, 0.5T) = (0, 12)
3052 23:44:15.896214 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3053 23:44:15.899466 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3054 23:44:15.903442 best DQS0 dly(2T, 0.5T) = (0, 11)
3055 23:44:15.906591 best DQS1 dly(2T, 0.5T) = (0, 12)
3056 23:44:15.910136 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3057 23:44:15.912829 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3058 23:44:15.916139 Pre-setting of DQS Precalculation
3059 23:44:15.919492 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3060 23:44:15.919907 ==
3061 23:44:15.923192 Dram Type= 6, Freq= 0, CH_1, rank 0
3062 23:44:15.926328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3063 23:44:15.926765 ==
3064 23:44:15.932856 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3065 23:44:15.940030 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3066 23:44:15.947124 [CA 0] Center 38 (9~68) winsize 60
3067 23:44:15.950715 [CA 1] Center 38 (8~68) winsize 61
3068 23:44:15.953972 [CA 2] Center 35 (5~65) winsize 61
3069 23:44:15.957592 [CA 3] Center 34 (3~65) winsize 63
3070 23:44:15.960606 [CA 4] Center 34 (4~65) winsize 62
3071 23:44:15.964075 [CA 5] Center 34 (4~64) winsize 61
3072 23:44:15.964489
3073 23:44:15.967546 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3074 23:44:15.967962
3075 23:44:15.970590 [CATrainingPosCal] consider 1 rank data
3076 23:44:15.973945 u2DelayCellTimex100 = 270/100 ps
3077 23:44:15.977280 CA0 delay=38 (9~68),Diff = 4 PI (19 cell)
3078 23:44:15.980844 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3079 23:44:15.984513 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3080 23:44:15.990869 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
3081 23:44:15.994263 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3082 23:44:15.997606 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3083 23:44:15.998018
3084 23:44:16.001381 CA PerBit enable=1, Macro0, CA PI delay=34
3085 23:44:16.001796
3086 23:44:16.003941 [CBTSetCACLKResult] CA Dly = 34
3087 23:44:16.004354 CS Dly: 6 (0~37)
3088 23:44:16.004681 ==
3089 23:44:16.007862 Dram Type= 6, Freq= 0, CH_1, rank 1
3090 23:44:16.011427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3091 23:44:16.014501 ==
3092 23:44:16.018161 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3093 23:44:16.024517 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3094 23:44:16.032713 [CA 0] Center 38 (8~68) winsize 61
3095 23:44:16.036370 [CA 1] Center 38 (8~68) winsize 61
3096 23:44:16.039520 [CA 2] Center 34 (4~65) winsize 62
3097 23:44:16.042944 [CA 3] Center 34 (4~65) winsize 62
3098 23:44:16.046143 [CA 4] Center 34 (4~65) winsize 62
3099 23:44:16.049210 [CA 5] Center 33 (3~64) winsize 62
3100 23:44:16.049629
3101 23:44:16.052585 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3102 23:44:16.053040
3103 23:44:16.056127 [CATrainingPosCal] consider 2 rank data
3104 23:44:16.059290 u2DelayCellTimex100 = 270/100 ps
3105 23:44:16.062882 CA0 delay=38 (9~68),Diff = 4 PI (19 cell)
3106 23:44:16.066213 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3107 23:44:16.069470 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3108 23:44:16.076385 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3109 23:44:16.079521 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3110 23:44:16.082749 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3111 23:44:16.083163
3112 23:44:16.086624 CA PerBit enable=1, Macro0, CA PI delay=34
3113 23:44:16.087041
3114 23:44:16.089546 [CBTSetCACLKResult] CA Dly = 34
3115 23:44:16.090061 CS Dly: 7 (0~40)
3116 23:44:16.090549
3117 23:44:16.093121 ----->DramcWriteLeveling(PI) begin...
3118 23:44:16.093557 ==
3119 23:44:16.096491 Dram Type= 6, Freq= 0, CH_1, rank 0
3120 23:44:16.103304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3121 23:44:16.104124 ==
3122 23:44:16.106455 Write leveling (Byte 0): 26 => 26
3123 23:44:16.110072 Write leveling (Byte 1): 30 => 30
3124 23:44:16.110727 DramcWriteLeveling(PI) end<-----
3125 23:44:16.111328
3126 23:44:16.113453 ==
3127 23:44:16.114096 Dram Type= 6, Freq= 0, CH_1, rank 0
3128 23:44:16.120128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3129 23:44:16.120940 ==
3130 23:44:16.123594 [Gating] SW mode calibration
3131 23:44:16.130162 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3132 23:44:16.133332 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3133 23:44:16.139611 0 15 0 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
3134 23:44:16.143345 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
3135 23:44:16.146177 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3136 23:44:16.153493 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3137 23:44:16.156800 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3138 23:44:16.159861 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3139 23:44:16.163255 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3140 23:44:16.169583 0 15 28 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 0)
3141 23:44:16.173132 1 0 0 | B1->B0 | 2828 2b2b | 0 0 | (1 0) (1 0)
3142 23:44:16.176339 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3143 23:44:16.183099 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3144 23:44:16.186755 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3145 23:44:16.190044 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3146 23:44:16.196600 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3147 23:44:16.199959 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3148 23:44:16.203086 1 0 28 | B1->B0 | 2c2c 2727 | 0 0 | (0 0) (0 0)
3149 23:44:16.210228 1 1 0 | B1->B0 | 3f3f 2f2f | 0 1 | (1 1) (0 0)
3150 23:44:16.213401 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3151 23:44:16.216845 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3152 23:44:16.219988 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3153 23:44:16.227419 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3154 23:44:16.230066 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3155 23:44:16.233918 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3156 23:44:16.240645 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3157 23:44:16.244141 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3158 23:44:16.247154 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 23:44:16.253885 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 23:44:16.256927 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 23:44:16.260865 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 23:44:16.267227 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 23:44:16.270953 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 23:44:16.274477 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 23:44:16.277462 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 23:44:16.284181 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 23:44:16.288240 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 23:44:16.291089 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 23:44:16.297885 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 23:44:16.300799 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 23:44:16.304645 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 23:44:16.310972 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3173 23:44:16.314585 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3174 23:44:16.318137 Total UI for P1: 0, mck2ui 16
3175 23:44:16.321593 best dqsien dly found for B0: ( 1, 3, 28)
3176 23:44:16.324396 Total UI for P1: 0, mck2ui 16
3177 23:44:16.328054 best dqsien dly found for B1: ( 1, 3, 28)
3178 23:44:16.331448 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3179 23:44:16.334359 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3180 23:44:16.334812
3181 23:44:16.338199 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3182 23:44:16.341592 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3183 23:44:16.344616 [Gating] SW calibration Done
3184 23:44:16.345059 ==
3185 23:44:16.347894 Dram Type= 6, Freq= 0, CH_1, rank 0
3186 23:44:16.351641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3187 23:44:16.352236 ==
3188 23:44:16.354584 RX Vref Scan: 0
3189 23:44:16.355147
3190 23:44:16.355587 RX Vref 0 -> 0, step: 1
3191 23:44:16.358151
3192 23:44:16.358638 RX Delay -40 -> 252, step: 8
3193 23:44:16.365096 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3194 23:44:16.367958 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3195 23:44:16.371327 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3196 23:44:16.374763 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3197 23:44:16.378283 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3198 23:44:16.381337 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3199 23:44:16.388199 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3200 23:44:16.391826 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3201 23:44:16.395270 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3202 23:44:16.398461 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3203 23:44:16.401817 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3204 23:44:16.408239 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3205 23:44:16.412011 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3206 23:44:16.415410 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3207 23:44:16.418779 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3208 23:44:16.422005 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3209 23:44:16.425674 ==
3210 23:44:16.426086 Dram Type= 6, Freq= 0, CH_1, rank 0
3211 23:44:16.431647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3212 23:44:16.432066 ==
3213 23:44:16.432394 DQS Delay:
3214 23:44:16.435483 DQS0 = 0, DQS1 = 0
3215 23:44:16.435895 DQM Delay:
3216 23:44:16.438431 DQM0 = 115, DQM1 = 108
3217 23:44:16.438845 DQ Delay:
3218 23:44:16.441740 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3219 23:44:16.445080 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =111
3220 23:44:16.448534 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
3221 23:44:16.452123 DQ12 =119, DQ13 =115, DQ14 =111, DQ15 =111
3222 23:44:16.452535
3223 23:44:16.452856
3224 23:44:16.453370 ==
3225 23:44:16.455247 Dram Type= 6, Freq= 0, CH_1, rank 0
3226 23:44:16.458887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3227 23:44:16.461809 ==
3228 23:44:16.462220
3229 23:44:16.462674
3230 23:44:16.463001 TX Vref Scan disable
3231 23:44:16.465747 == TX Byte 0 ==
3232 23:44:16.468921 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3233 23:44:16.472341 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3234 23:44:16.475781 == TX Byte 1 ==
3235 23:44:16.478946 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3236 23:44:16.481980 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3237 23:44:16.482464 ==
3238 23:44:16.485263 Dram Type= 6, Freq= 0, CH_1, rank 0
3239 23:44:16.491842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3240 23:44:16.492426 ==
3241 23:44:16.503084 TX Vref=22, minBit 1, minWin=25, winSum=411
3242 23:44:16.506162 TX Vref=24, minBit 4, minWin=25, winSum=416
3243 23:44:16.509843 TX Vref=26, minBit 0, minWin=26, winSum=418
3244 23:44:16.512924 TX Vref=28, minBit 1, minWin=26, winSum=427
3245 23:44:16.516113 TX Vref=30, minBit 1, minWin=26, winSum=430
3246 23:44:16.519734 TX Vref=32, minBit 15, minWin=25, winSum=429
3247 23:44:16.526552 [TxChooseVref] Worse bit 1, Min win 26, Win sum 430, Final Vref 30
3248 23:44:16.526971
3249 23:44:16.529835 Final TX Range 1 Vref 30
3250 23:44:16.530248
3251 23:44:16.530578 ==
3252 23:44:16.533403 Dram Type= 6, Freq= 0, CH_1, rank 0
3253 23:44:16.536819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3254 23:44:16.537316 ==
3255 23:44:16.537657
3256 23:44:16.537963
3257 23:44:16.540022 TX Vref Scan disable
3258 23:44:16.543430 == TX Byte 0 ==
3259 23:44:16.546543 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3260 23:44:16.549679 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3261 23:44:16.553210 == TX Byte 1 ==
3262 23:44:16.556859 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3263 23:44:16.559684 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3264 23:44:16.560098
3265 23:44:16.563453 [DATLAT]
3266 23:44:16.563864 Freq=1200, CH1 RK0
3267 23:44:16.564190
3268 23:44:16.566509 DATLAT Default: 0xd
3269 23:44:16.566922 0, 0xFFFF, sum = 0
3270 23:44:16.570280 1, 0xFFFF, sum = 0
3271 23:44:16.570702 2, 0xFFFF, sum = 0
3272 23:44:16.573378 3, 0xFFFF, sum = 0
3273 23:44:16.573797 4, 0xFFFF, sum = 0
3274 23:44:16.576679 5, 0xFFFF, sum = 0
3275 23:44:16.577139 6, 0xFFFF, sum = 0
3276 23:44:16.579814 7, 0xFFFF, sum = 0
3277 23:44:16.580232 8, 0xFFFF, sum = 0
3278 23:44:16.583211 9, 0xFFFF, sum = 0
3279 23:44:16.583629 10, 0xFFFF, sum = 0
3280 23:44:16.586871 11, 0xFFFF, sum = 0
3281 23:44:16.587315 12, 0x0, sum = 1
3282 23:44:16.589955 13, 0x0, sum = 2
3283 23:44:16.590375 14, 0x0, sum = 3
3284 23:44:16.593337 15, 0x0, sum = 4
3285 23:44:16.593759 best_step = 13
3286 23:44:16.594080
3287 23:44:16.594382 ==
3288 23:44:16.596530 Dram Type= 6, Freq= 0, CH_1, rank 0
3289 23:44:16.603575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3290 23:44:16.604078 ==
3291 23:44:16.604590 RX Vref Scan: 1
3292 23:44:16.605094
3293 23:44:16.606814 Set Vref Range= 32 -> 127
3294 23:44:16.607496
3295 23:44:16.610184 RX Vref 32 -> 127, step: 1
3296 23:44:16.610754
3297 23:44:16.611273 RX Delay -21 -> 252, step: 4
3298 23:44:16.611798
3299 23:44:16.613638 Set Vref, RX VrefLevel [Byte0]: 32
3300 23:44:16.616887 [Byte1]: 32
3301 23:44:16.621436
3302 23:44:16.622002 Set Vref, RX VrefLevel [Byte0]: 33
3303 23:44:16.624382 [Byte1]: 33
3304 23:44:16.628788
3305 23:44:16.629110 Set Vref, RX VrefLevel [Byte0]: 34
3306 23:44:16.632761 [Byte1]: 34
3307 23:44:16.637118
3308 23:44:16.637338 Set Vref, RX VrefLevel [Byte0]: 35
3309 23:44:16.640643 [Byte1]: 35
3310 23:44:16.645078
3311 23:44:16.645292 Set Vref, RX VrefLevel [Byte0]: 36
3312 23:44:16.648562 [Byte1]: 36
3313 23:44:16.652706
3314 23:44:16.652902 Set Vref, RX VrefLevel [Byte0]: 37
3315 23:44:16.655888 [Byte1]: 37
3316 23:44:16.660743
3317 23:44:16.660895 Set Vref, RX VrefLevel [Byte0]: 38
3318 23:44:16.664397 [Byte1]: 38
3319 23:44:16.668869
3320 23:44:16.668966 Set Vref, RX VrefLevel [Byte0]: 39
3321 23:44:16.672218 [Byte1]: 39
3322 23:44:16.676337
3323 23:44:16.676442 Set Vref, RX VrefLevel [Byte0]: 40
3324 23:44:16.679836 [Byte1]: 40
3325 23:44:16.684592
3326 23:44:16.684776 Set Vref, RX VrefLevel [Byte0]: 41
3327 23:44:16.687431 [Byte1]: 41
3328 23:44:16.691951
3329 23:44:16.692059 Set Vref, RX VrefLevel [Byte0]: 42
3330 23:44:16.695338 [Byte1]: 42
3331 23:44:16.700124
3332 23:44:16.700238 Set Vref, RX VrefLevel [Byte0]: 43
3333 23:44:16.703317 [Byte1]: 43
3334 23:44:16.708161
3335 23:44:16.708268 Set Vref, RX VrefLevel [Byte0]: 44
3336 23:44:16.711677 [Byte1]: 44
3337 23:44:16.715880
3338 23:44:16.715960 Set Vref, RX VrefLevel [Byte0]: 45
3339 23:44:16.719288 [Byte1]: 45
3340 23:44:16.724068
3341 23:44:16.724148 Set Vref, RX VrefLevel [Byte0]: 46
3342 23:44:16.727298 [Byte1]: 46
3343 23:44:16.731696
3344 23:44:16.731776 Set Vref, RX VrefLevel [Byte0]: 47
3345 23:44:16.735128 [Byte1]: 47
3346 23:44:16.739723
3347 23:44:16.739812 Set Vref, RX VrefLevel [Byte0]: 48
3348 23:44:16.742883 [Byte1]: 48
3349 23:44:16.747473
3350 23:44:16.747552 Set Vref, RX VrefLevel [Byte0]: 49
3351 23:44:16.751023 [Byte1]: 49
3352 23:44:16.755453
3353 23:44:16.755534 Set Vref, RX VrefLevel [Byte0]: 50
3354 23:44:16.758573 [Byte1]: 50
3355 23:44:16.763994
3356 23:44:16.764079 Set Vref, RX VrefLevel [Byte0]: 51
3357 23:44:16.766947 [Byte1]: 51
3358 23:44:16.771791
3359 23:44:16.771958 Set Vref, RX VrefLevel [Byte0]: 52
3360 23:44:16.775003 [Byte1]: 52
3361 23:44:16.779159
3362 23:44:16.782724 Set Vref, RX VrefLevel [Byte0]: 53
3363 23:44:16.782832 [Byte1]: 53
3364 23:44:16.787179
3365 23:44:16.787303 Set Vref, RX VrefLevel [Byte0]: 54
3366 23:44:16.790812 [Byte1]: 54
3367 23:44:16.795395
3368 23:44:16.795556 Set Vref, RX VrefLevel [Byte0]: 55
3369 23:44:16.798735 [Byte1]: 55
3370 23:44:16.803336
3371 23:44:16.803529 Set Vref, RX VrefLevel [Byte0]: 56
3372 23:44:16.806335 [Byte1]: 56
3373 23:44:16.811581
3374 23:44:16.811820 Set Vref, RX VrefLevel [Byte0]: 57
3375 23:44:16.814441 [Byte1]: 57
3376 23:44:16.819561
3377 23:44:16.820047 Set Vref, RX VrefLevel [Byte0]: 58
3378 23:44:16.822919 [Byte1]: 58
3379 23:44:16.827226
3380 23:44:16.827668 Set Vref, RX VrefLevel [Byte0]: 59
3381 23:44:16.830344 [Byte1]: 59
3382 23:44:16.834949
3383 23:44:16.835381 Set Vref, RX VrefLevel [Byte0]: 60
3384 23:44:16.838900 [Byte1]: 60
3385 23:44:16.843155
3386 23:44:16.843571 Set Vref, RX VrefLevel [Byte0]: 61
3387 23:44:16.849483 [Byte1]: 61
3388 23:44:16.849899
3389 23:44:16.853170 Set Vref, RX VrefLevel [Byte0]: 62
3390 23:44:16.856580 [Byte1]: 62
3391 23:44:16.857037
3392 23:44:16.859880 Set Vref, RX VrefLevel [Byte0]: 63
3393 23:44:16.863292 [Byte1]: 63
3394 23:44:16.866594
3395 23:44:16.867009 Set Vref, RX VrefLevel [Byte0]: 64
3396 23:44:16.870211 [Byte1]: 64
3397 23:44:16.875292
3398 23:44:16.875781 Set Vref, RX VrefLevel [Byte0]: 65
3399 23:44:16.878252 [Byte1]: 65
3400 23:44:16.882562
3401 23:44:16.883221 Set Vref, RX VrefLevel [Byte0]: 66
3402 23:44:16.885985 [Byte1]: 66
3403 23:44:16.890636
3404 23:44:16.891205 Set Vref, RX VrefLevel [Byte0]: 67
3405 23:44:16.894062 [Byte1]: 67
3406 23:44:16.898652
3407 23:44:16.899070 Set Vref, RX VrefLevel [Byte0]: 68
3408 23:44:16.901855 [Byte1]: 68
3409 23:44:16.906757
3410 23:44:16.907171 Set Vref, RX VrefLevel [Byte0]: 69
3411 23:44:16.910184 [Byte1]: 69
3412 23:44:16.914341
3413 23:44:16.914753 Set Vref, RX VrefLevel [Byte0]: 70
3414 23:44:16.917829 [Byte1]: 70
3415 23:44:16.922354
3416 23:44:16.922789 Set Vref, RX VrefLevel [Byte0]: 71
3417 23:44:16.925575 [Byte1]: 71
3418 23:44:16.930159
3419 23:44:16.930582 Final RX Vref Byte 0 = 58 to rank0
3420 23:44:16.933773 Final RX Vref Byte 1 = 52 to rank0
3421 23:44:16.936684 Final RX Vref Byte 0 = 58 to rank1
3422 23:44:16.940063 Final RX Vref Byte 1 = 52 to rank1==
3423 23:44:16.943378 Dram Type= 6, Freq= 0, CH_1, rank 0
3424 23:44:16.946700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3425 23:44:16.950217 ==
3426 23:44:16.950708 DQS Delay:
3427 23:44:16.951118 DQS0 = 0, DQS1 = 0
3428 23:44:16.954226 DQM Delay:
3429 23:44:16.954705 DQM0 = 116, DQM1 = 109
3430 23:44:16.957162 DQ Delay:
3431 23:44:16.960324 DQ0 =118, DQ1 =112, DQ2 =106, DQ3 =114
3432 23:44:16.963800 DQ4 =116, DQ5 =126, DQ6 =126, DQ7 =114
3433 23:44:16.967125 DQ8 =98, DQ9 =98, DQ10 =112, DQ11 =104
3434 23:44:16.970550 DQ12 =116, DQ13 =118, DQ14 =118, DQ15 =114
3435 23:44:16.971194
3436 23:44:16.971747
3437 23:44:16.977402 [DQSOSCAuto] RK0, (LSB)MR18= 0xfde1, (MSB)MR19= 0x303, tDQSOscB0 = 422 ps tDQSOscB1 = 411 ps
3438 23:44:16.980909 CH1 RK0: MR19=303, MR18=FDE1
3439 23:44:16.987272 CH1_RK0: MR19=0x303, MR18=0xFDE1, DQSOSC=411, MR23=63, INC=38, DEC=25
3440 23:44:16.987844
3441 23:44:16.990900 ----->DramcWriteLeveling(PI) begin...
3442 23:44:16.991639 ==
3443 23:44:16.994423 Dram Type= 6, Freq= 0, CH_1, rank 1
3444 23:44:16.997241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3445 23:44:16.997843 ==
3446 23:44:17.000495 Write leveling (Byte 0): 25 => 25
3447 23:44:17.004224 Write leveling (Byte 1): 29 => 29
3448 23:44:17.007450 DramcWriteLeveling(PI) end<-----
3449 23:44:17.008027
3450 23:44:17.008552 ==
3451 23:44:17.010540 Dram Type= 6, Freq= 0, CH_1, rank 1
3452 23:44:17.014108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3453 23:44:17.017123 ==
3454 23:44:17.017234 [Gating] SW mode calibration
3455 23:44:17.023701 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3456 23:44:17.030441 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3457 23:44:17.033961 0 15 0 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
3458 23:44:17.040357 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3459 23:44:17.043998 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3460 23:44:17.047316 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3461 23:44:17.050838 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3462 23:44:17.057241 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3463 23:44:17.060989 0 15 24 | B1->B0 | 3434 2f2f | 0 0 | (0 0) (0 1)
3464 23:44:17.063961 0 15 28 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
3465 23:44:17.071241 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3466 23:44:17.073923 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3467 23:44:17.077745 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3468 23:44:17.083851 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3469 23:44:17.087540 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3470 23:44:17.090471 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3471 23:44:17.097002 1 0 24 | B1->B0 | 2525 3c3c | 0 0 | (0 0) (0 0)
3472 23:44:17.100773 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3473 23:44:17.104284 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3474 23:44:17.110683 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3475 23:44:17.114215 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3476 23:44:17.117088 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3477 23:44:17.124047 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3478 23:44:17.127124 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3479 23:44:17.130203 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3480 23:44:17.137133 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3481 23:44:17.140385 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 23:44:17.144059 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 23:44:17.150541 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 23:44:17.153518 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 23:44:17.157509 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 23:44:17.160932 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 23:44:17.167361 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 23:44:17.170661 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 23:44:17.174014 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3490 23:44:17.180522 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 23:44:17.183997 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 23:44:17.187051 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 23:44:17.194496 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 23:44:17.197792 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3495 23:44:17.200553 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3496 23:44:17.207005 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3497 23:44:17.210760 Total UI for P1: 0, mck2ui 16
3498 23:44:17.214093 best dqsien dly found for B0: ( 1, 3, 22)
3499 23:44:17.216901 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3500 23:44:17.220689 Total UI for P1: 0, mck2ui 16
3501 23:44:17.223983 best dqsien dly found for B1: ( 1, 3, 28)
3502 23:44:17.227560 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3503 23:44:17.230953 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3504 23:44:17.231465
3505 23:44:17.233955 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3506 23:44:17.237548 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3507 23:44:17.241132 [Gating] SW calibration Done
3508 23:44:17.241561 ==
3509 23:44:17.243878 Dram Type= 6, Freq= 0, CH_1, rank 1
3510 23:44:17.247626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3511 23:44:17.251143 ==
3512 23:44:17.251818 RX Vref Scan: 0
3513 23:44:17.252319
3514 23:44:17.254161 RX Vref 0 -> 0, step: 1
3515 23:44:17.254579
3516 23:44:17.254943 RX Delay -40 -> 252, step: 8
3517 23:44:17.261264 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
3518 23:44:17.264216 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3519 23:44:17.267610 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3520 23:44:17.270886 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3521 23:44:17.273819 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3522 23:44:17.280796 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3523 23:44:17.284464 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3524 23:44:17.287417 iDelay=200, Bit 7, Center 107 (40 ~ 175) 136
3525 23:44:17.290835 iDelay=200, Bit 8, Center 99 (24 ~ 175) 152
3526 23:44:17.294009 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3527 23:44:17.300857 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3528 23:44:17.304292 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3529 23:44:17.307653 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3530 23:44:17.310826 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3531 23:44:17.314423 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3532 23:44:17.320941 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3533 23:44:17.321414 ==
3534 23:44:17.324235 Dram Type= 6, Freq= 0, CH_1, rank 1
3535 23:44:17.327893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3536 23:44:17.328562 ==
3537 23:44:17.329046 DQS Delay:
3538 23:44:17.331015 DQS0 = 0, DQS1 = 0
3539 23:44:17.331549 DQM Delay:
3540 23:44:17.334331 DQM0 = 112, DQM1 = 110
3541 23:44:17.334760 DQ Delay:
3542 23:44:17.337809 DQ0 =111, DQ1 =111, DQ2 =103, DQ3 =111
3543 23:44:17.340891 DQ4 =111, DQ5 =127, DQ6 =119, DQ7 =107
3544 23:44:17.344262 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =103
3545 23:44:17.347920 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =119
3546 23:44:17.348336
3547 23:44:17.348658
3548 23:44:17.351270 ==
3549 23:44:17.351752 Dram Type= 6, Freq= 0, CH_1, rank 1
3550 23:44:17.357643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3551 23:44:17.358062 ==
3552 23:44:17.358390
3553 23:44:17.358836
3554 23:44:17.360722 TX Vref Scan disable
3555 23:44:17.361281 == TX Byte 0 ==
3556 23:44:17.363957 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3557 23:44:17.370666 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3558 23:44:17.371081 == TX Byte 1 ==
3559 23:44:17.374004 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3560 23:44:17.380502 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3561 23:44:17.380918 ==
3562 23:44:17.384395 Dram Type= 6, Freq= 0, CH_1, rank 1
3563 23:44:17.387475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3564 23:44:17.387893 ==
3565 23:44:17.399224 TX Vref=22, minBit 1, minWin=25, winSum=419
3566 23:44:17.403030 TX Vref=24, minBit 1, minWin=25, winSum=422
3567 23:44:17.406274 TX Vref=26, minBit 1, minWin=25, winSum=425
3568 23:44:17.409303 TX Vref=28, minBit 9, minWin=26, winSum=430
3569 23:44:17.413048 TX Vref=30, minBit 4, minWin=26, winSum=434
3570 23:44:17.415985 TX Vref=32, minBit 1, minWin=26, winSum=434
3571 23:44:17.422883 [TxChooseVref] Worse bit 4, Min win 26, Win sum 434, Final Vref 30
3572 23:44:17.423301
3573 23:44:17.426245 Final TX Range 1 Vref 30
3574 23:44:17.426666
3575 23:44:17.426990 ==
3576 23:44:17.429824 Dram Type= 6, Freq= 0, CH_1, rank 1
3577 23:44:17.432709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3578 23:44:17.433164 ==
3579 23:44:17.433496
3580 23:44:17.435884
3581 23:44:17.436372 TX Vref Scan disable
3582 23:44:17.439009 == TX Byte 0 ==
3583 23:44:17.442804 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3584 23:44:17.446212 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3585 23:44:17.449492 == TX Byte 1 ==
3586 23:44:17.452609 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3587 23:44:17.455910 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3588 23:44:17.456363
3589 23:44:17.459637 [DATLAT]
3590 23:44:17.460175 Freq=1200, CH1 RK1
3591 23:44:17.460576
3592 23:44:17.463077 DATLAT Default: 0xd
3593 23:44:17.463587 0, 0xFFFF, sum = 0
3594 23:44:17.466264 1, 0xFFFF, sum = 0
3595 23:44:17.466683 2, 0xFFFF, sum = 0
3596 23:44:17.469489 3, 0xFFFF, sum = 0
3597 23:44:17.469910 4, 0xFFFF, sum = 0
3598 23:44:17.472841 5, 0xFFFF, sum = 0
3599 23:44:17.473303 6, 0xFFFF, sum = 0
3600 23:44:17.475893 7, 0xFFFF, sum = 0
3601 23:44:17.476309 8, 0xFFFF, sum = 0
3602 23:44:17.479415 9, 0xFFFF, sum = 0
3603 23:44:17.482744 10, 0xFFFF, sum = 0
3604 23:44:17.483161 11, 0xFFFF, sum = 0
3605 23:44:17.485955 12, 0x0, sum = 1
3606 23:44:17.486375 13, 0x0, sum = 2
3607 23:44:17.486706 14, 0x0, sum = 3
3608 23:44:17.489078 15, 0x0, sum = 4
3609 23:44:17.489498 best_step = 13
3610 23:44:17.489821
3611 23:44:17.493215 ==
3612 23:44:17.493628 Dram Type= 6, Freq= 0, CH_1, rank 1
3613 23:44:17.499013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3614 23:44:17.499490 ==
3615 23:44:17.499823 RX Vref Scan: 0
3616 23:44:17.500126
3617 23:44:17.502897 RX Vref 0 -> 0, step: 1
3618 23:44:17.503307
3619 23:44:17.506398 RX Delay -21 -> 252, step: 4
3620 23:44:17.509133 iDelay=191, Bit 0, Center 114 (47 ~ 182) 136
3621 23:44:17.512943 iDelay=191, Bit 1, Center 108 (43 ~ 174) 132
3622 23:44:17.519800 iDelay=191, Bit 2, Center 104 (39 ~ 170) 132
3623 23:44:17.522463 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3624 23:44:17.526233 iDelay=191, Bit 4, Center 114 (47 ~ 182) 136
3625 23:44:17.529158 iDelay=191, Bit 5, Center 124 (59 ~ 190) 132
3626 23:44:17.532606 iDelay=191, Bit 6, Center 120 (51 ~ 190) 140
3627 23:44:17.539205 iDelay=191, Bit 7, Center 110 (47 ~ 174) 128
3628 23:44:17.542662 iDelay=191, Bit 8, Center 98 (31 ~ 166) 136
3629 23:44:17.546066 iDelay=191, Bit 9, Center 98 (35 ~ 162) 128
3630 23:44:17.549953 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3631 23:44:17.553034 iDelay=191, Bit 11, Center 102 (35 ~ 170) 136
3632 23:44:17.559497 iDelay=191, Bit 12, Center 114 (51 ~ 178) 128
3633 23:44:17.563195 iDelay=191, Bit 13, Center 118 (51 ~ 186) 136
3634 23:44:17.566588 iDelay=191, Bit 14, Center 118 (55 ~ 182) 128
3635 23:44:17.569890 iDelay=191, Bit 15, Center 116 (51 ~ 182) 132
3636 23:44:17.570304 ==
3637 23:44:17.572840 Dram Type= 6, Freq= 0, CH_1, rank 1
3638 23:44:17.576319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3639 23:44:17.579575 ==
3640 23:44:17.579990 DQS Delay:
3641 23:44:17.580314 DQS0 = 0, DQS1 = 0
3642 23:44:17.583144 DQM Delay:
3643 23:44:17.583555 DQM0 = 113, DQM1 = 109
3644 23:44:17.587096 DQ Delay:
3645 23:44:17.589650 DQ0 =114, DQ1 =108, DQ2 =104, DQ3 =112
3646 23:44:17.593124 DQ4 =114, DQ5 =124, DQ6 =120, DQ7 =110
3647 23:44:17.596588 DQ8 =98, DQ9 =98, DQ10 =110, DQ11 =102
3648 23:44:17.599797 DQ12 =114, DQ13 =118, DQ14 =118, DQ15 =116
3649 23:44:17.600211
3650 23:44:17.600535
3651 23:44:17.606457 [DQSOSCAuto] RK1, (LSB)MR18= 0xf6fe, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 414 ps
3652 23:44:17.610179 CH1 RK1: MR19=303, MR18=F6FE
3653 23:44:17.616686 CH1_RK1: MR19=0x303, MR18=0xF6FE, DQSOSC=410, MR23=63, INC=39, DEC=26
3654 23:44:17.619661 [RxdqsGatingPostProcess] freq 1200
3655 23:44:17.626643 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3656 23:44:17.627059 best DQS0 dly(2T, 0.5T) = (0, 11)
3657 23:44:17.629883 best DQS1 dly(2T, 0.5T) = (0, 11)
3658 23:44:17.632940 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3659 23:44:17.636523 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3660 23:44:17.639881 best DQS0 dly(2T, 0.5T) = (0, 11)
3661 23:44:17.643372 best DQS1 dly(2T, 0.5T) = (0, 11)
3662 23:44:17.647122 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3663 23:44:17.649964 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3664 23:44:17.653175 Pre-setting of DQS Precalculation
3665 23:44:17.656145 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3666 23:44:17.666246 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3667 23:44:17.672817 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3668 23:44:17.673424
3669 23:44:17.673888
3670 23:44:17.676555 [Calibration Summary] 2400 Mbps
3671 23:44:17.677035 CH 0, Rank 0
3672 23:44:17.680426 SW Impedance : PASS
3673 23:44:17.680840 DUTY Scan : NO K
3674 23:44:17.683231 ZQ Calibration : PASS
3675 23:44:17.686384 Jitter Meter : NO K
3676 23:44:17.686890 CBT Training : PASS
3677 23:44:17.689570 Write leveling : PASS
3678 23:44:17.693199 RX DQS gating : PASS
3679 23:44:17.693618 RX DQ/DQS(RDDQC) : PASS
3680 23:44:17.696534 TX DQ/DQS : PASS
3681 23:44:17.699626 RX DATLAT : PASS
3682 23:44:17.700234 RX DQ/DQS(Engine): PASS
3683 23:44:17.703034 TX OE : NO K
3684 23:44:17.703580 All Pass.
3685 23:44:17.704114
3686 23:44:17.706674 CH 0, Rank 1
3687 23:44:17.707126 SW Impedance : PASS
3688 23:44:17.709969 DUTY Scan : NO K
3689 23:44:17.713037 ZQ Calibration : PASS
3690 23:44:17.713443 Jitter Meter : NO K
3691 23:44:17.716441 CBT Training : PASS
3692 23:44:17.717061 Write leveling : PASS
3693 23:44:17.720133 RX DQS gating : PASS
3694 23:44:17.722981 RX DQ/DQS(RDDQC) : PASS
3695 23:44:17.723390 TX DQ/DQS : PASS
3696 23:44:17.726225 RX DATLAT : PASS
3697 23:44:17.729707 RX DQ/DQS(Engine): PASS
3698 23:44:17.730118 TX OE : NO K
3699 23:44:17.733316 All Pass.
3700 23:44:17.733739
3701 23:44:17.734307 CH 1, Rank 0
3702 23:44:17.736171 SW Impedance : PASS
3703 23:44:17.736709 DUTY Scan : NO K
3704 23:44:17.739652 ZQ Calibration : PASS
3705 23:44:17.742899 Jitter Meter : NO K
3706 23:44:17.743309 CBT Training : PASS
3707 23:44:17.746717 Write leveling : PASS
3708 23:44:17.749220 RX DQS gating : PASS
3709 23:44:17.749692 RX DQ/DQS(RDDQC) : PASS
3710 23:44:17.752574 TX DQ/DQS : PASS
3711 23:44:17.756441 RX DATLAT : PASS
3712 23:44:17.756884 RX DQ/DQS(Engine): PASS
3713 23:44:17.759406 TX OE : NO K
3714 23:44:17.759818 All Pass.
3715 23:44:17.760141
3716 23:44:17.762804 CH 1, Rank 1
3717 23:44:17.763213 SW Impedance : PASS
3718 23:44:17.766372 DUTY Scan : NO K
3719 23:44:17.766785 ZQ Calibration : PASS
3720 23:44:17.769681 Jitter Meter : NO K
3721 23:44:17.772849 CBT Training : PASS
3722 23:44:17.773338 Write leveling : PASS
3723 23:44:17.776340 RX DQS gating : PASS
3724 23:44:17.779189 RX DQ/DQS(RDDQC) : PASS
3725 23:44:17.779725 TX DQ/DQS : PASS
3726 23:44:17.782707 RX DATLAT : PASS
3727 23:44:17.786321 RX DQ/DQS(Engine): PASS
3728 23:44:17.786883 TX OE : NO K
3729 23:44:17.789292 All Pass.
3730 23:44:17.789890
3731 23:44:17.790394 DramC Write-DBI off
3732 23:44:17.792967 PER_BANK_REFRESH: Hybrid Mode
3733 23:44:17.793421 TX_TRACKING: ON
3734 23:44:17.802631 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3735 23:44:17.806114 [FAST_K] Save calibration result to emmc
3736 23:44:17.808891 dramc_set_vcore_voltage set vcore to 650000
3737 23:44:17.812352 Read voltage for 600, 5
3738 23:44:17.812460 Vio18 = 0
3739 23:44:17.815572 Vcore = 650000
3740 23:44:17.815652 Vdram = 0
3741 23:44:17.815715 Vddq = 0
3742 23:44:17.818935 Vmddr = 0
3743 23:44:17.822222 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3744 23:44:17.829103 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3745 23:44:17.829184 MEM_TYPE=3, freq_sel=19
3746 23:44:17.832328 sv_algorithm_assistance_LP4_1600
3747 23:44:17.838872 ============ PULL DRAM RESETB DOWN ============
3748 23:44:17.842298 ========== PULL DRAM RESETB DOWN end =========
3749 23:44:17.845832 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3750 23:44:17.849224 ===================================
3751 23:44:17.852565 LPDDR4 DRAM CONFIGURATION
3752 23:44:17.855620 ===================================
3753 23:44:17.855800 EX_ROW_EN[0] = 0x0
3754 23:44:17.859173 EX_ROW_EN[1] = 0x0
3755 23:44:17.862488 LP4Y_EN = 0x0
3756 23:44:17.862672 WORK_FSP = 0x0
3757 23:44:17.866142 WL = 0x2
3758 23:44:17.866277 RL = 0x2
3759 23:44:17.869004 BL = 0x2
3760 23:44:17.869153 RPST = 0x0
3761 23:44:17.872233 RD_PRE = 0x0
3762 23:44:17.872382 WR_PRE = 0x1
3763 23:44:17.876224 WR_PST = 0x0
3764 23:44:17.876395 DBI_WR = 0x0
3765 23:44:17.879492 DBI_RD = 0x0
3766 23:44:17.879688 OTF = 0x1
3767 23:44:17.882337 ===================================
3768 23:44:17.885909 ===================================
3769 23:44:17.889396 ANA top config
3770 23:44:17.893059 ===================================
3771 23:44:17.893491 DLL_ASYNC_EN = 0
3772 23:44:17.895993 ALL_SLAVE_EN = 1
3773 23:44:17.899335 NEW_RANK_MODE = 1
3774 23:44:17.902894 DLL_IDLE_MODE = 1
3775 23:44:17.903306 LP45_APHY_COMB_EN = 1
3776 23:44:17.906032 TX_ODT_DIS = 1
3777 23:44:17.909254 NEW_8X_MODE = 1
3778 23:44:17.912922 ===================================
3779 23:44:17.916027 ===================================
3780 23:44:17.919394 data_rate = 1200
3781 23:44:17.922378 CKR = 1
3782 23:44:17.922459 DQ_P2S_RATIO = 8
3783 23:44:17.925691 ===================================
3784 23:44:17.929239 CA_P2S_RATIO = 8
3785 23:44:17.932901 DQ_CA_OPEN = 0
3786 23:44:17.935901 DQ_SEMI_OPEN = 0
3787 23:44:17.939519 CA_SEMI_OPEN = 0
3788 23:44:17.942503 CA_FULL_RATE = 0
3789 23:44:17.942621 DQ_CKDIV4_EN = 1
3790 23:44:17.946457 CA_CKDIV4_EN = 1
3791 23:44:17.949592 CA_PREDIV_EN = 0
3792 23:44:17.953105 PH8_DLY = 0
3793 23:44:17.956482 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3794 23:44:17.956568 DQ_AAMCK_DIV = 4
3795 23:44:17.959452 CA_AAMCK_DIV = 4
3796 23:44:17.962759 CA_ADMCK_DIV = 4
3797 23:44:17.966320 DQ_TRACK_CA_EN = 0
3798 23:44:17.969352 CA_PICK = 600
3799 23:44:17.972735 CA_MCKIO = 600
3800 23:44:17.976181 MCKIO_SEMI = 0
3801 23:44:17.976359 PLL_FREQ = 2288
3802 23:44:17.979494 DQ_UI_PI_RATIO = 32
3803 23:44:17.982980 CA_UI_PI_RATIO = 0
3804 23:44:17.986231 ===================================
3805 23:44:17.989437 ===================================
3806 23:44:17.992859 memory_type:LPDDR4
3807 23:44:17.993098 GP_NUM : 10
3808 23:44:17.995712 SRAM_EN : 1
3809 23:44:17.999141 MD32_EN : 0
3810 23:44:18.002631 ===================================
3811 23:44:18.002713 [ANA_INIT] >>>>>>>>>>>>>>
3812 23:44:18.006046 <<<<<< [CONFIGURE PHASE]: ANA_TX
3813 23:44:18.009340 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3814 23:44:18.012991 ===================================
3815 23:44:18.015987 data_rate = 1200,PCW = 0X5800
3816 23:44:18.019623 ===================================
3817 23:44:18.022876 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3818 23:44:18.029835 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3819 23:44:18.033045 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3820 23:44:18.039501 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3821 23:44:18.042796 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3822 23:44:18.046764 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3823 23:44:18.046979 [ANA_INIT] flow start
3824 23:44:18.049912 [ANA_INIT] PLL >>>>>>>>
3825 23:44:18.053100 [ANA_INIT] PLL <<<<<<<<
3826 23:44:18.053249 [ANA_INIT] MIDPI >>>>>>>>
3827 23:44:18.056635 [ANA_INIT] MIDPI <<<<<<<<
3828 23:44:18.059812 [ANA_INIT] DLL >>>>>>>>
3829 23:44:18.060008 [ANA_INIT] flow end
3830 23:44:18.066940 ============ LP4 DIFF to SE enter ============
3831 23:44:18.070544 ============ LP4 DIFF to SE exit ============
3832 23:44:18.073485 [ANA_INIT] <<<<<<<<<<<<<
3833 23:44:18.076593 [Flow] Enable top DCM control >>>>>
3834 23:44:18.080090 [Flow] Enable top DCM control <<<<<
3835 23:44:18.080472 Enable DLL master slave shuffle
3836 23:44:18.087087 ==============================================================
3837 23:44:18.090134 Gating Mode config
3838 23:44:18.093634 ==============================================================
3839 23:44:18.097212 Config description:
3840 23:44:18.107109 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3841 23:44:18.113476 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3842 23:44:18.117034 SELPH_MODE 0: By rank 1: By Phase
3843 23:44:18.123726 ==============================================================
3844 23:44:18.127118 GAT_TRACK_EN = 1
3845 23:44:18.130435 RX_GATING_MODE = 2
3846 23:44:18.130894 RX_GATING_TRACK_MODE = 2
3847 23:44:18.133512 SELPH_MODE = 1
3848 23:44:18.136785 PICG_EARLY_EN = 1
3849 23:44:18.140086 VALID_LAT_VALUE = 1
3850 23:44:18.146665 ==============================================================
3851 23:44:18.150063 Enter into Gating configuration >>>>
3852 23:44:18.153260 Exit from Gating configuration <<<<
3853 23:44:18.156839 Enter into DVFS_PRE_config >>>>>
3854 23:44:18.166735 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3855 23:44:18.169645 Exit from DVFS_PRE_config <<<<<
3856 23:44:18.173383 Enter into PICG configuration >>>>
3857 23:44:18.177127 Exit from PICG configuration <<<<
3858 23:44:18.179910 [RX_INPUT] configuration >>>>>
3859 23:44:18.183003 [RX_INPUT] configuration <<<<<
3860 23:44:18.186285 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3861 23:44:18.193050 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3862 23:44:18.200265 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3863 23:44:18.206719 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3864 23:44:18.210192 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3865 23:44:18.216611 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3866 23:44:18.219941 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3867 23:44:18.226363 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3868 23:44:18.229618 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3869 23:44:18.233453 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3870 23:44:18.236610 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3871 23:44:18.243270 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3872 23:44:18.246359 ===================================
3873 23:44:18.246813 LPDDR4 DRAM CONFIGURATION
3874 23:44:18.250278 ===================================
3875 23:44:18.253593 EX_ROW_EN[0] = 0x0
3876 23:44:18.256285 EX_ROW_EN[1] = 0x0
3877 23:44:18.256695 LP4Y_EN = 0x0
3878 23:44:18.259709 WORK_FSP = 0x0
3879 23:44:18.260120 WL = 0x2
3880 23:44:18.263349 RL = 0x2
3881 23:44:18.263813 BL = 0x2
3882 23:44:18.267243 RPST = 0x0
3883 23:44:18.267753 RD_PRE = 0x0
3884 23:44:18.269807 WR_PRE = 0x1
3885 23:44:18.270230 WR_PST = 0x0
3886 23:44:18.273058 DBI_WR = 0x0
3887 23:44:18.273470 DBI_RD = 0x0
3888 23:44:18.276552 OTF = 0x1
3889 23:44:18.280159 ===================================
3890 23:44:18.283242 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3891 23:44:18.287171 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3892 23:44:18.293409 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3893 23:44:18.296552 ===================================
3894 23:44:18.296961 LPDDR4 DRAM CONFIGURATION
3895 23:44:18.300555 ===================================
3896 23:44:18.302957 EX_ROW_EN[0] = 0x10
3897 23:44:18.303411 EX_ROW_EN[1] = 0x0
3898 23:44:18.306465 LP4Y_EN = 0x0
3899 23:44:18.306913 WORK_FSP = 0x0
3900 23:44:18.310151 WL = 0x2
3901 23:44:18.313539 RL = 0x2
3902 23:44:18.313988 BL = 0x2
3903 23:44:18.317622 RPST = 0x0
3904 23:44:18.318037 RD_PRE = 0x0
3905 23:44:18.320067 WR_PRE = 0x1
3906 23:44:18.320494 WR_PST = 0x0
3907 23:44:18.323387 DBI_WR = 0x0
3908 23:44:18.323797 DBI_RD = 0x0
3909 23:44:18.326978 OTF = 0x1
3910 23:44:18.329812 ===================================
3911 23:44:18.333351 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3912 23:44:18.339454 nWR fixed to 30
3913 23:44:18.342696 [ModeRegInit_LP4] CH0 RK0
3914 23:44:18.343121 [ModeRegInit_LP4] CH0 RK1
3915 23:44:18.345564 [ModeRegInit_LP4] CH1 RK0
3916 23:44:18.349032 [ModeRegInit_LP4] CH1 RK1
3917 23:44:18.349444 match AC timing 17
3918 23:44:18.355592 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3919 23:44:18.359150 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3920 23:44:18.362500 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3921 23:44:18.368970 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3922 23:44:18.372667 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3923 23:44:18.373118 ==
3924 23:44:18.375580 Dram Type= 6, Freq= 0, CH_0, rank 0
3925 23:44:18.378947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3926 23:44:18.379382 ==
3927 23:44:18.385846 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3928 23:44:18.392268 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3929 23:44:18.395311 [CA 0] Center 36 (6~66) winsize 61
3930 23:44:18.399320 [CA 1] Center 36 (6~66) winsize 61
3931 23:44:18.402483 [CA 2] Center 34 (4~65) winsize 62
3932 23:44:18.405562 [CA 3] Center 34 (4~65) winsize 62
3933 23:44:18.409446 [CA 4] Center 33 (3~64) winsize 62
3934 23:44:18.412597 [CA 5] Center 33 (3~64) winsize 62
3935 23:44:18.413042
3936 23:44:18.415487 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3937 23:44:18.415899
3938 23:44:18.419307 [CATrainingPosCal] consider 1 rank data
3939 23:44:18.422623 u2DelayCellTimex100 = 270/100 ps
3940 23:44:18.425546 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3941 23:44:18.429523 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3942 23:44:18.432287 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3943 23:44:18.436029 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3944 23:44:18.439268 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3945 23:44:18.442620 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3946 23:44:18.443183
3947 23:44:18.445940 CA PerBit enable=1, Macro0, CA PI delay=33
3948 23:44:18.446348
3949 23:44:18.449112 [CBTSetCACLKResult] CA Dly = 33
3950 23:44:18.452876 CS Dly: 4 (0~35)
3951 23:44:18.453331 ==
3952 23:44:18.455789 Dram Type= 6, Freq= 0, CH_0, rank 1
3953 23:44:18.459090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3954 23:44:18.459501 ==
3955 23:44:18.466216 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3956 23:44:18.472718 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3957 23:44:18.476392 [CA 0] Center 36 (6~66) winsize 61
3958 23:44:18.479765 [CA 1] Center 36 (6~66) winsize 61
3959 23:44:18.483273 [CA 2] Center 34 (4~65) winsize 62
3960 23:44:18.486304 [CA 3] Center 34 (4~64) winsize 61
3961 23:44:18.489382 [CA 4] Center 33 (3~64) winsize 62
3962 23:44:18.489795 [CA 5] Center 33 (3~64) winsize 62
3963 23:44:18.492761
3964 23:44:18.495789 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3965 23:44:18.496197
3966 23:44:18.499723 [CATrainingPosCal] consider 2 rank data
3967 23:44:18.502823 u2DelayCellTimex100 = 270/100 ps
3968 23:44:18.506338 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3969 23:44:18.509796 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3970 23:44:18.513217 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3971 23:44:18.516292 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
3972 23:44:18.519269 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3973 23:44:18.522899 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3974 23:44:18.523333
3975 23:44:18.526087 CA PerBit enable=1, Macro0, CA PI delay=33
3976 23:44:18.526660
3977 23:44:18.529421 [CBTSetCACLKResult] CA Dly = 33
3978 23:44:18.533099 CS Dly: 4 (0~36)
3979 23:44:18.533611
3980 23:44:18.536360 ----->DramcWriteLeveling(PI) begin...
3981 23:44:18.536909 ==
3982 23:44:18.539584 Dram Type= 6, Freq= 0, CH_0, rank 0
3983 23:44:18.542895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3984 23:44:18.543420 ==
3985 23:44:18.546599 Write leveling (Byte 0): 30 => 30
3986 23:44:18.549389 Write leveling (Byte 1): 30 => 30
3987 23:44:18.552957 DramcWriteLeveling(PI) end<-----
3988 23:44:18.553444
3989 23:44:18.553770 ==
3990 23:44:18.556303 Dram Type= 6, Freq= 0, CH_0, rank 0
3991 23:44:18.559445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3992 23:44:18.559963 ==
3993 23:44:18.563076 [Gating] SW mode calibration
3994 23:44:18.569416 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3995 23:44:18.576496 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3996 23:44:18.579641 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3997 23:44:18.583222 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3998 23:44:18.589698 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3999 23:44:18.593414 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4000 23:44:18.596233 0 9 16 | B1->B0 | 2f2f 2b2b | 1 0 | (1 0) (0 0)
4001 23:44:18.603373 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4002 23:44:18.606369 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4003 23:44:18.609872 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4004 23:44:18.616730 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4005 23:44:18.619698 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4006 23:44:18.622966 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4007 23:44:18.629423 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4008 23:44:18.632915 0 10 16 | B1->B0 | 2c2c 3d3d | 0 0 | (0 0) (0 0)
4009 23:44:18.636562 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4010 23:44:18.640378 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4011 23:44:18.647231 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4012 23:44:18.649885 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4013 23:44:18.653780 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4014 23:44:18.659692 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4015 23:44:18.663169 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4016 23:44:18.666696 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4017 23:44:18.673221 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 23:44:18.676316 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 23:44:18.679880 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 23:44:18.686692 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 23:44:18.689583 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 23:44:18.693181 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 23:44:18.699935 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 23:44:18.703123 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 23:44:18.706172 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 23:44:18.713149 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 23:44:18.716664 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 23:44:18.719689 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 23:44:18.726850 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 23:44:18.729574 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 23:44:18.733300 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4032 23:44:18.739657 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4033 23:44:18.740086 Total UI for P1: 0, mck2ui 16
4034 23:44:18.742946 best dqsien dly found for B0: ( 0, 13, 12)
4035 23:44:18.746443 Total UI for P1: 0, mck2ui 16
4036 23:44:18.749544 best dqsien dly found for B1: ( 0, 13, 12)
4037 23:44:18.752880 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4038 23:44:18.759546 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4039 23:44:18.759968
4040 23:44:18.763119 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4041 23:44:18.766562 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4042 23:44:18.769489 [Gating] SW calibration Done
4043 23:44:18.770026 ==
4044 23:44:18.772479 Dram Type= 6, Freq= 0, CH_0, rank 0
4045 23:44:18.776040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4046 23:44:18.776381 ==
4047 23:44:18.779774 RX Vref Scan: 0
4048 23:44:18.779992
4049 23:44:18.780210 RX Vref 0 -> 0, step: 1
4050 23:44:18.780396
4051 23:44:18.782828 RX Delay -230 -> 252, step: 16
4052 23:44:18.786244 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4053 23:44:18.792314 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4054 23:44:18.795893 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4055 23:44:18.799002 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4056 23:44:18.802313 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4057 23:44:18.805733 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4058 23:44:18.812706 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4059 23:44:18.815564 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4060 23:44:18.819081 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4061 23:44:18.822573 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4062 23:44:18.829164 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4063 23:44:18.832520 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4064 23:44:18.835825 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4065 23:44:18.839244 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4066 23:44:18.845531 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4067 23:44:18.849277 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4068 23:44:18.849407 ==
4069 23:44:18.852221 Dram Type= 6, Freq= 0, CH_0, rank 0
4070 23:44:18.855845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4071 23:44:18.855949 ==
4072 23:44:18.856030 DQS Delay:
4073 23:44:18.859200 DQS0 = 0, DQS1 = 0
4074 23:44:18.859297 DQM Delay:
4075 23:44:18.862521 DQM0 = 40, DQM1 = 31
4076 23:44:18.862618 DQ Delay:
4077 23:44:18.865783 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4078 23:44:18.868835 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4079 23:44:18.872750 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4080 23:44:18.875422 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =41
4081 23:44:18.875532
4082 23:44:18.875627
4083 23:44:18.875718 ==
4084 23:44:18.879070 Dram Type= 6, Freq= 0, CH_0, rank 0
4085 23:44:18.882317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4086 23:44:18.885730 ==
4087 23:44:18.885833
4088 23:44:18.885899
4089 23:44:18.885956 TX Vref Scan disable
4090 23:44:18.888706 == TX Byte 0 ==
4091 23:44:18.892282 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4092 23:44:18.895604 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4093 23:44:18.899294 == TX Byte 1 ==
4094 23:44:18.902259 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4095 23:44:18.905560 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4096 23:44:18.909188 ==
4097 23:44:18.912502 Dram Type= 6, Freq= 0, CH_0, rank 0
4098 23:44:18.915836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4099 23:44:18.915940 ==
4100 23:44:18.916042
4101 23:44:18.916103
4102 23:44:18.918965 TX Vref Scan disable
4103 23:44:18.919049 == TX Byte 0 ==
4104 23:44:18.925563 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4105 23:44:18.928969 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4106 23:44:18.929100 == TX Byte 1 ==
4107 23:44:18.935649 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4108 23:44:18.938903 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4109 23:44:18.938996
4110 23:44:18.939061 [DATLAT]
4111 23:44:18.942774 Freq=600, CH0 RK0
4112 23:44:18.942877
4113 23:44:18.942942 DATLAT Default: 0x9
4114 23:44:18.945655 0, 0xFFFF, sum = 0
4115 23:44:18.945741 1, 0xFFFF, sum = 0
4116 23:44:18.949132 2, 0xFFFF, sum = 0
4117 23:44:18.949222 3, 0xFFFF, sum = 0
4118 23:44:18.952573 4, 0xFFFF, sum = 0
4119 23:44:18.952662 5, 0xFFFF, sum = 0
4120 23:44:18.955879 6, 0xFFFF, sum = 0
4121 23:44:18.955984 7, 0xFFFF, sum = 0
4122 23:44:18.959381 8, 0x0, sum = 1
4123 23:44:18.959474 9, 0x0, sum = 2
4124 23:44:18.962410 10, 0x0, sum = 3
4125 23:44:18.962496 11, 0x0, sum = 4
4126 23:44:18.965893 best_step = 9
4127 23:44:18.965974
4128 23:44:18.966037 ==
4129 23:44:18.969024 Dram Type= 6, Freq= 0, CH_0, rank 0
4130 23:44:18.972455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4131 23:44:18.972537 ==
4132 23:44:18.975811 RX Vref Scan: 1
4133 23:44:18.975892
4134 23:44:18.975956 RX Vref 0 -> 0, step: 1
4135 23:44:18.976020
4136 23:44:18.978903 RX Delay -195 -> 252, step: 8
4137 23:44:18.979037
4138 23:44:18.982555 Set Vref, RX VrefLevel [Byte0]: 54
4139 23:44:18.985854 [Byte1]: 51
4140 23:44:18.989333
4141 23:44:18.989437 Final RX Vref Byte 0 = 54 to rank0
4142 23:44:18.992758 Final RX Vref Byte 1 = 51 to rank0
4143 23:44:18.996353 Final RX Vref Byte 0 = 54 to rank1
4144 23:44:18.999366 Final RX Vref Byte 1 = 51 to rank1==
4145 23:44:19.002951 Dram Type= 6, Freq= 0, CH_0, rank 0
4146 23:44:19.006194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4147 23:44:19.009281 ==
4148 23:44:19.009363 DQS Delay:
4149 23:44:19.009427 DQS0 = 0, DQS1 = 0
4150 23:44:19.012845 DQM Delay:
4151 23:44:19.012927 DQM0 = 42, DQM1 = 33
4152 23:44:19.016154 DQ Delay:
4153 23:44:19.019597 DQ0 =44, DQ1 =40, DQ2 =40, DQ3 =40
4154 23:44:19.019679 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4155 23:44:19.023144 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4156 23:44:19.026126 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4157 23:44:19.029580
4158 23:44:19.029663
4159 23:44:19.036053 [DQSOSCAuto] RK0, (LSB)MR18= 0x4625, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
4160 23:44:19.039812 CH0 RK0: MR19=808, MR18=4625
4161 23:44:19.046197 CH0_RK0: MR19=0x808, MR18=0x4625, DQSOSC=396, MR23=63, INC=167, DEC=111
4162 23:44:19.046289
4163 23:44:19.049699 ----->DramcWriteLeveling(PI) begin...
4164 23:44:19.049810 ==
4165 23:44:19.052915 Dram Type= 6, Freq= 0, CH_0, rank 1
4166 23:44:19.056622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4167 23:44:19.056721 ==
4168 23:44:19.059970 Write leveling (Byte 0): 33 => 33
4169 23:44:19.063035 Write leveling (Byte 1): 29 => 29
4170 23:44:19.065918 DramcWriteLeveling(PI) end<-----
4171 23:44:19.066003
4172 23:44:19.066068 ==
4173 23:44:19.069574 Dram Type= 6, Freq= 0, CH_0, rank 1
4174 23:44:19.073049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4175 23:44:19.073133 ==
4176 23:44:19.075909 [Gating] SW mode calibration
4177 23:44:19.082762 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4178 23:44:19.089545 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4179 23:44:19.092536 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4180 23:44:19.096180 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4181 23:44:19.102748 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4182 23:44:19.105943 0 9 12 | B1->B0 | 3434 3232 | 1 1 | (1 0) (0 0)
4183 23:44:19.109438 0 9 16 | B1->B0 | 3030 2323 | 1 0 | (1 0) (0 0)
4184 23:44:19.116585 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4185 23:44:19.119334 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4186 23:44:19.122916 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4187 23:44:19.129806 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4188 23:44:19.132458 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4189 23:44:19.136263 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4190 23:44:19.142868 0 10 12 | B1->B0 | 2323 3838 | 0 0 | (0 0) (0 0)
4191 23:44:19.146345 0 10 16 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
4192 23:44:19.149246 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4193 23:44:19.152855 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4194 23:44:19.159379 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4195 23:44:19.162675 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4196 23:44:19.165830 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4197 23:44:19.172537 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4198 23:44:19.176005 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4199 23:44:19.179259 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4200 23:44:19.185975 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4201 23:44:19.189671 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 23:44:19.192852 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 23:44:19.199468 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 23:44:19.202795 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 23:44:19.206449 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 23:44:19.212845 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 23:44:19.215990 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 23:44:19.219663 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 23:44:19.226391 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 23:44:19.229877 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 23:44:19.232708 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 23:44:19.236033 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 23:44:19.243120 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 23:44:19.246143 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4215 23:44:19.249581 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4216 23:44:19.253251 Total UI for P1: 0, mck2ui 16
4217 23:44:19.256171 best dqsien dly found for B0: ( 0, 13, 12)
4218 23:44:19.263189 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4219 23:44:19.263301 Total UI for P1: 0, mck2ui 16
4220 23:44:19.269805 best dqsien dly found for B1: ( 0, 13, 14)
4221 23:44:19.273084 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4222 23:44:19.276287 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4223 23:44:19.276368
4224 23:44:19.280031 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4225 23:44:19.283156 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4226 23:44:19.286350 [Gating] SW calibration Done
4227 23:44:19.286431 ==
4228 23:44:19.289840 Dram Type= 6, Freq= 0, CH_0, rank 1
4229 23:44:19.292695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4230 23:44:19.292776 ==
4231 23:44:19.296661 RX Vref Scan: 0
4232 23:44:19.296748
4233 23:44:19.296829 RX Vref 0 -> 0, step: 1
4234 23:44:19.299844
4235 23:44:19.299944 RX Delay -230 -> 252, step: 16
4236 23:44:19.306151 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4237 23:44:19.309734 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4238 23:44:19.312686 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4239 23:44:19.316130 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4240 23:44:19.319679 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4241 23:44:19.326557 iDelay=218, Bit 5, Center 33 (-118 ~ 185) 304
4242 23:44:19.329930 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4243 23:44:19.332784 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4244 23:44:19.336242 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4245 23:44:19.342724 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4246 23:44:19.346404 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4247 23:44:19.349840 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4248 23:44:19.352759 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4249 23:44:19.359389 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4250 23:44:19.363019 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4251 23:44:19.366208 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4252 23:44:19.366311 ==
4253 23:44:19.369858 Dram Type= 6, Freq= 0, CH_0, rank 1
4254 23:44:19.372660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4255 23:44:19.372751 ==
4256 23:44:19.376223 DQS Delay:
4257 23:44:19.376318 DQS0 = 0, DQS1 = 0
4258 23:44:19.379746 DQM Delay:
4259 23:44:19.379843 DQM0 = 42, DQM1 = 35
4260 23:44:19.379911 DQ Delay:
4261 23:44:19.382682 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4262 23:44:19.386128 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4263 23:44:19.389524 DQ8 =25, DQ9 =17, DQ10 =41, DQ11 =25
4264 23:44:19.392856 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4265 23:44:19.393062
4266 23:44:19.393171
4267 23:44:19.393257 ==
4268 23:44:19.396325 Dram Type= 6, Freq= 0, CH_0, rank 1
4269 23:44:19.402788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4270 23:44:19.402937 ==
4271 23:44:19.403007
4272 23:44:19.403068
4273 23:44:19.403125 TX Vref Scan disable
4274 23:44:19.406702 == TX Byte 0 ==
4275 23:44:19.409898 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4276 23:44:19.416745 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4277 23:44:19.416900 == TX Byte 1 ==
4278 23:44:19.420400 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4279 23:44:19.423535 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4280 23:44:19.427233 ==
4281 23:44:19.430237 Dram Type= 6, Freq= 0, CH_0, rank 1
4282 23:44:19.433587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4283 23:44:19.433692 ==
4284 23:44:19.433760
4285 23:44:19.433819
4286 23:44:19.436816 TX Vref Scan disable
4287 23:44:19.436937 == TX Byte 0 ==
4288 23:44:19.444139 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4289 23:44:19.447017 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4290 23:44:19.447125 == TX Byte 1 ==
4291 23:44:19.453918 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4292 23:44:19.456785 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4293 23:44:19.456896
4294 23:44:19.456962 [DATLAT]
4295 23:44:19.460098 Freq=600, CH0 RK1
4296 23:44:19.460219
4297 23:44:19.460311 DATLAT Default: 0x9
4298 23:44:19.463557 0, 0xFFFF, sum = 0
4299 23:44:19.463659 1, 0xFFFF, sum = 0
4300 23:44:19.466659 2, 0xFFFF, sum = 0
4301 23:44:19.470106 3, 0xFFFF, sum = 0
4302 23:44:19.470223 4, 0xFFFF, sum = 0
4303 23:44:19.473765 5, 0xFFFF, sum = 0
4304 23:44:19.473862 6, 0xFFFF, sum = 0
4305 23:44:19.476899 7, 0xFFFF, sum = 0
4306 23:44:19.477055 8, 0x0, sum = 1
4307 23:44:19.477124 9, 0x0, sum = 2
4308 23:44:19.480351 10, 0x0, sum = 3
4309 23:44:19.480449 11, 0x0, sum = 4
4310 23:44:19.483889 best_step = 9
4311 23:44:19.483979
4312 23:44:19.484041 ==
4313 23:44:19.486435 Dram Type= 6, Freq= 0, CH_0, rank 1
4314 23:44:19.489821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4315 23:44:19.489959 ==
4316 23:44:19.492946 RX Vref Scan: 0
4317 23:44:19.493081
4318 23:44:19.493145 RX Vref 0 -> 0, step: 1
4319 23:44:19.493202
4320 23:44:19.496503 RX Delay -195 -> 252, step: 8
4321 23:44:19.504125 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4322 23:44:19.507342 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4323 23:44:19.510653 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4324 23:44:19.514158 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4325 23:44:19.520873 iDelay=205, Bit 4, Center 36 (-115 ~ 188) 304
4326 23:44:19.523997 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4327 23:44:19.527902 iDelay=205, Bit 6, Center 52 (-99 ~ 204) 304
4328 23:44:19.530839 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4329 23:44:19.534763 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4330 23:44:19.541307 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4331 23:44:19.544121 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4332 23:44:19.547345 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4333 23:44:19.550823 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4334 23:44:19.557751 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4335 23:44:19.560680 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4336 23:44:19.564062 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4337 23:44:19.564160 ==
4338 23:44:19.567386 Dram Type= 6, Freq= 0, CH_0, rank 1
4339 23:44:19.570774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4340 23:44:19.570901 ==
4341 23:44:19.573919 DQS Delay:
4342 23:44:19.574034 DQS0 = 0, DQS1 = 0
4343 23:44:19.577640 DQM Delay:
4344 23:44:19.577743 DQM0 = 40, DQM1 = 32
4345 23:44:19.577824 DQ Delay:
4346 23:44:19.580946 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =40
4347 23:44:19.584325 DQ4 =36, DQ5 =28, DQ6 =52, DQ7 =48
4348 23:44:19.587722 DQ8 =20, DQ9 =24, DQ10 =32, DQ11 =24
4349 23:44:19.591331 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =40
4350 23:44:19.591465
4351 23:44:19.591560
4352 23:44:19.600766 [DQSOSCAuto] RK1, (LSB)MR18= 0x4a2b, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 395 ps
4353 23:44:19.604139 CH0 RK1: MR19=808, MR18=4A2B
4354 23:44:19.607570 CH0_RK1: MR19=0x808, MR18=0x4A2B, DQSOSC=395, MR23=63, INC=168, DEC=112
4355 23:44:19.610784 [RxdqsGatingPostProcess] freq 600
4356 23:44:19.617567 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4357 23:44:19.620802 Pre-setting of DQS Precalculation
4358 23:44:19.624657 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4359 23:44:19.624792 ==
4360 23:44:19.627637 Dram Type= 6, Freq= 0, CH_1, rank 0
4361 23:44:19.634273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4362 23:44:19.634402 ==
4363 23:44:19.637528 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4364 23:44:19.644419 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4365 23:44:19.647791 [CA 0] Center 35 (5~66) winsize 62
4366 23:44:19.651114 [CA 1] Center 35 (5~66) winsize 62
4367 23:44:19.654172 [CA 2] Center 33 (3~64) winsize 62
4368 23:44:19.657574 [CA 3] Center 33 (2~64) winsize 63
4369 23:44:19.660942 [CA 4] Center 34 (3~65) winsize 63
4370 23:44:19.664247 [CA 5] Center 33 (2~64) winsize 63
4371 23:44:19.664329
4372 23:44:19.667654 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4373 23:44:19.667734
4374 23:44:19.671100 [CATrainingPosCal] consider 1 rank data
4375 23:44:19.674045 u2DelayCellTimex100 = 270/100 ps
4376 23:44:19.677693 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4377 23:44:19.681127 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4378 23:44:19.687597 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4379 23:44:19.690874 CA3 delay=33 (2~64),Diff = 0 PI (0 cell)
4380 23:44:19.694423 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4381 23:44:19.697960 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4382 23:44:19.698056
4383 23:44:19.700926 CA PerBit enable=1, Macro0, CA PI delay=33
4384 23:44:19.701037
4385 23:44:19.704388 [CBTSetCACLKResult] CA Dly = 33
4386 23:44:19.704473 CS Dly: 5 (0~36)
4387 23:44:19.704537 ==
4388 23:44:19.707721 Dram Type= 6, Freq= 0, CH_1, rank 1
4389 23:44:19.714305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4390 23:44:19.714425 ==
4391 23:44:19.718018 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4392 23:44:19.724106 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4393 23:44:19.727817 [CA 0] Center 35 (5~66) winsize 62
4394 23:44:19.731089 [CA 1] Center 35 (5~66) winsize 62
4395 23:44:19.734284 [CA 2] Center 34 (3~65) winsize 63
4396 23:44:19.737570 [CA 3] Center 33 (3~64) winsize 62
4397 23:44:19.741333 [CA 4] Center 34 (3~65) winsize 63
4398 23:44:19.744407 [CA 5] Center 33 (2~64) winsize 63
4399 23:44:19.744504
4400 23:44:19.747804 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4401 23:44:19.747899
4402 23:44:19.751051 [CATrainingPosCal] consider 2 rank data
4403 23:44:19.754497 u2DelayCellTimex100 = 270/100 ps
4404 23:44:19.757774 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4405 23:44:19.760826 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4406 23:44:19.767734 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4407 23:44:19.771160 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4408 23:44:19.774142 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4409 23:44:19.778106 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4410 23:44:19.778201
4411 23:44:19.780947 CA PerBit enable=1, Macro0, CA PI delay=33
4412 23:44:19.781072
4413 23:44:19.784443 [CBTSetCACLKResult] CA Dly = 33
4414 23:44:19.784529 CS Dly: 5 (0~36)
4415 23:44:19.784594
4416 23:44:19.787704 ----->DramcWriteLeveling(PI) begin...
4417 23:44:19.791377 ==
4418 23:44:19.791469 Dram Type= 6, Freq= 0, CH_1, rank 0
4419 23:44:19.797562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4420 23:44:19.797669 ==
4421 23:44:19.800808 Write leveling (Byte 0): 31 => 31
4422 23:44:19.804767 Write leveling (Byte 1): 32 => 32
4423 23:44:19.807581 DramcWriteLeveling(PI) end<-----
4424 23:44:19.807677
4425 23:44:19.807742 ==
4426 23:44:19.811362 Dram Type= 6, Freq= 0, CH_1, rank 0
4427 23:44:19.814718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4428 23:44:19.814810 ==
4429 23:44:19.818005 [Gating] SW mode calibration
4430 23:44:19.824336 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4431 23:44:19.827686 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4432 23:44:19.834691 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4433 23:44:19.837652 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4434 23:44:19.841005 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4435 23:44:19.847730 0 9 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
4436 23:44:19.850873 0 9 16 | B1->B0 | 2e2e 2626 | 0 0 | (1 1) (1 0)
4437 23:44:19.854580 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4438 23:44:19.861120 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4439 23:44:19.864398 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4440 23:44:19.867812 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4441 23:44:19.874557 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4442 23:44:19.877387 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4443 23:44:19.881136 0 10 12 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (0 0)
4444 23:44:19.887582 0 10 16 | B1->B0 | 3b3b 4343 | 0 0 | (0 0) (0 0)
4445 23:44:19.891396 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4446 23:44:19.894915 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4447 23:44:19.897508 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4448 23:44:19.904393 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4449 23:44:19.908152 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4450 23:44:19.911523 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4451 23:44:19.917853 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4452 23:44:19.921150 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4453 23:44:19.924890 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 23:44:19.931102 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 23:44:19.934612 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 23:44:19.937908 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 23:44:19.944473 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 23:44:19.947782 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 23:44:19.951073 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 23:44:19.957987 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 23:44:19.960916 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 23:44:19.964912 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 23:44:19.971659 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 23:44:19.974470 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 23:44:19.977802 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 23:44:19.981204 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 23:44:19.987975 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4468 23:44:19.991812 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4469 23:44:19.994338 Total UI for P1: 0, mck2ui 16
4470 23:44:19.998086 best dqsien dly found for B0: ( 0, 13, 12)
4471 23:44:20.001174 Total UI for P1: 0, mck2ui 16
4472 23:44:20.004637 best dqsien dly found for B1: ( 0, 13, 12)
4473 23:44:20.007776 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4474 23:44:20.011155 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4475 23:44:20.011265
4476 23:44:20.014637 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4477 23:44:20.017956 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4478 23:44:20.021591 [Gating] SW calibration Done
4479 23:44:20.021698 ==
4480 23:44:20.024790 Dram Type= 6, Freq= 0, CH_1, rank 0
4481 23:44:20.031120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4482 23:44:20.031246 ==
4483 23:44:20.031315 RX Vref Scan: 0
4484 23:44:20.031376
4485 23:44:20.035244 RX Vref 0 -> 0, step: 1
4486 23:44:20.035341
4487 23:44:20.038048 RX Delay -230 -> 252, step: 16
4488 23:44:20.041588 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4489 23:44:20.044451 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4490 23:44:20.047924 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4491 23:44:20.055041 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4492 23:44:20.057868 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4493 23:44:20.061146 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4494 23:44:20.064704 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4495 23:44:20.068334 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4496 23:44:20.074720 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4497 23:44:20.078139 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4498 23:44:20.081143 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4499 23:44:20.084700 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4500 23:44:20.091796 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4501 23:44:20.094575 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4502 23:44:20.098295 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4503 23:44:20.101708 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4504 23:44:20.101808 ==
4505 23:44:20.104766 Dram Type= 6, Freq= 0, CH_1, rank 0
4506 23:44:20.111742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4507 23:44:20.111878 ==
4508 23:44:20.111973 DQS Delay:
4509 23:44:20.112060 DQS0 = 0, DQS1 = 0
4510 23:44:20.115169 DQM Delay:
4511 23:44:20.115257 DQM0 = 40, DQM1 = 34
4512 23:44:20.118088 DQ Delay:
4513 23:44:20.121254 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =41
4514 23:44:20.124916 DQ4 =41, DQ5 =49, DQ6 =57, DQ7 =33
4515 23:44:20.125082 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =33
4516 23:44:20.131587 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =33
4517 23:44:20.131768
4518 23:44:20.131841
4519 23:44:20.131901 ==
4520 23:44:20.135035 Dram Type= 6, Freq= 0, CH_1, rank 0
4521 23:44:20.138417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4522 23:44:20.138566 ==
4523 23:44:20.138697
4524 23:44:20.138843
4525 23:44:20.141342 TX Vref Scan disable
4526 23:44:20.141427 == TX Byte 0 ==
4527 23:44:20.147768 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4528 23:44:20.151826 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4529 23:44:20.151942 == TX Byte 1 ==
4530 23:44:20.158398 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4531 23:44:20.161457 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4532 23:44:20.161558 ==
4533 23:44:20.165015 Dram Type= 6, Freq= 0, CH_1, rank 0
4534 23:44:20.168550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4535 23:44:20.168640 ==
4536 23:44:20.168705
4537 23:44:20.168764
4538 23:44:20.171673 TX Vref Scan disable
4539 23:44:20.174859 == TX Byte 0 ==
4540 23:44:20.177976 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4541 23:44:20.181742 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4542 23:44:20.185199 == TX Byte 1 ==
4543 23:44:20.188302 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4544 23:44:20.191501 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4545 23:44:20.191596
4546 23:44:20.194915 [DATLAT]
4547 23:44:20.195010 Freq=600, CH1 RK0
4548 23:44:20.195075
4549 23:44:20.198552 DATLAT Default: 0x9
4550 23:44:20.198641 0, 0xFFFF, sum = 0
4551 23:44:20.202002 1, 0xFFFF, sum = 0
4552 23:44:20.202116 2, 0xFFFF, sum = 0
4553 23:44:20.204713 3, 0xFFFF, sum = 0
4554 23:44:20.204799 4, 0xFFFF, sum = 0
4555 23:44:20.208445 5, 0xFFFF, sum = 0
4556 23:44:20.208577 6, 0xFFFF, sum = 0
4557 23:44:20.211315 7, 0xFFFF, sum = 0
4558 23:44:20.211410 8, 0x0, sum = 1
4559 23:44:20.214965 9, 0x0, sum = 2
4560 23:44:20.215088 10, 0x0, sum = 3
4561 23:44:20.218427 11, 0x0, sum = 4
4562 23:44:20.218521 best_step = 9
4563 23:44:20.218587
4564 23:44:20.218646 ==
4565 23:44:20.222163 Dram Type= 6, Freq= 0, CH_1, rank 0
4566 23:44:20.224682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4567 23:44:20.229282 ==
4568 23:44:20.229399 RX Vref Scan: 1
4569 23:44:20.229473
4570 23:44:20.231784 RX Vref 0 -> 0, step: 1
4571 23:44:20.231897
4572 23:44:20.235198 RX Delay -195 -> 252, step: 8
4573 23:44:20.235295
4574 23:44:20.235393 Set Vref, RX VrefLevel [Byte0]: 58
4575 23:44:20.238193 [Byte1]: 52
4576 23:44:20.243310
4577 23:44:20.243459 Final RX Vref Byte 0 = 58 to rank0
4578 23:44:20.246769 Final RX Vref Byte 1 = 52 to rank0
4579 23:44:20.249943 Final RX Vref Byte 0 = 58 to rank1
4580 23:44:20.253308 Final RX Vref Byte 1 = 52 to rank1==
4581 23:44:20.256516 Dram Type= 6, Freq= 0, CH_1, rank 0
4582 23:44:20.263153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4583 23:44:20.263283 ==
4584 23:44:20.263351 DQS Delay:
4585 23:44:20.263410 DQS0 = 0, DQS1 = 0
4586 23:44:20.266857 DQM Delay:
4587 23:44:20.266969 DQM0 = 40, DQM1 = 32
4588 23:44:20.269897 DQ Delay:
4589 23:44:20.273499 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4590 23:44:20.273600 DQ4 =36, DQ5 =48, DQ6 =52, DQ7 =36
4591 23:44:20.276710 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =24
4592 23:44:20.280242 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4593 23:44:20.283586
4594 23:44:20.283675
4595 23:44:20.290072 [DQSOSCAuto] RK0, (LSB)MR18= 0x3e04, (MSB)MR19= 0x808, tDQSOscB0 = 409 ps tDQSOscB1 = 398 ps
4596 23:44:20.293442 CH1 RK0: MR19=808, MR18=3E04
4597 23:44:20.299803 CH1_RK0: MR19=0x808, MR18=0x3E04, DQSOSC=398, MR23=63, INC=165, DEC=110
4598 23:44:20.299921
4599 23:44:20.303519 ----->DramcWriteLeveling(PI) begin...
4600 23:44:20.303609 ==
4601 23:44:20.306807 Dram Type= 6, Freq= 0, CH_1, rank 1
4602 23:44:20.309947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4603 23:44:20.310044 ==
4604 23:44:20.313508 Write leveling (Byte 0): 30 => 30
4605 23:44:20.317126 Write leveling (Byte 1): 30 => 30
4606 23:44:20.319968 DramcWriteLeveling(PI) end<-----
4607 23:44:20.320053
4608 23:44:20.320118 ==
4609 23:44:20.323830 Dram Type= 6, Freq= 0, CH_1, rank 1
4610 23:44:20.326788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4611 23:44:20.326879 ==
4612 23:44:20.330093 [Gating] SW mode calibration
4613 23:44:20.336536 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4614 23:44:20.343631 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4615 23:44:20.347159 0 9 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4616 23:44:20.350185 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4617 23:44:20.356634 0 9 8 | B1->B0 | 3535 3333 | 0 0 | (0 0) (0 0)
4618 23:44:20.360212 0 9 12 | B1->B0 | 2f2f 2a2a | 0 1 | (0 0) (1 0)
4619 23:44:20.363605 0 9 16 | B1->B0 | 2323 2323 | 1 0 | (1 1) (0 0)
4620 23:44:20.370441 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4621 23:44:20.373453 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4622 23:44:20.376877 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4623 23:44:20.383858 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4624 23:44:20.386764 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4625 23:44:20.389964 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4626 23:44:20.396608 0 10 12 | B1->B0 | 2f2f 4141 | 1 0 | (0 0) (0 0)
4627 23:44:20.400089 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4628 23:44:20.403596 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4629 23:44:20.406989 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4630 23:44:20.413405 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4631 23:44:20.416816 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4632 23:44:20.419909 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4633 23:44:20.426622 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4634 23:44:20.430125 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4635 23:44:20.433398 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 23:44:20.440378 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 23:44:20.443786 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 23:44:20.446776 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 23:44:20.453574 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 23:44:20.456606 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 23:44:20.459840 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 23:44:20.466846 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 23:44:20.469925 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 23:44:20.473335 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 23:44:20.479956 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 23:44:20.483351 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 23:44:20.487100 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 23:44:20.493515 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 23:44:20.496748 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 23:44:20.499855 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4651 23:44:20.503268 Total UI for P1: 0, mck2ui 16
4652 23:44:20.506835 best dqsien dly found for B0: ( 0, 13, 10)
4653 23:44:20.510507 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4654 23:44:20.513492 Total UI for P1: 0, mck2ui 16
4655 23:44:20.517082 best dqsien dly found for B1: ( 0, 13, 14)
4656 23:44:20.520332 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4657 23:44:20.527130 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4658 23:44:20.527305
4659 23:44:20.530321 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4660 23:44:20.533777 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4661 23:44:20.536569 [Gating] SW calibration Done
4662 23:44:20.536719 ==
4663 23:44:20.540372 Dram Type= 6, Freq= 0, CH_1, rank 1
4664 23:44:20.543251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4665 23:44:20.543396 ==
4666 23:44:20.543510 RX Vref Scan: 0
4667 23:44:20.546529
4668 23:44:20.546651 RX Vref 0 -> 0, step: 1
4669 23:44:20.546746
4670 23:44:20.550104 RX Delay -230 -> 252, step: 16
4671 23:44:20.553260 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4672 23:44:20.560405 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4673 23:44:20.563721 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4674 23:44:20.566659 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4675 23:44:20.570268 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4676 23:44:20.573838 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4677 23:44:20.580227 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4678 23:44:20.583395 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4679 23:44:20.586950 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4680 23:44:20.590147 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4681 23:44:20.593248 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4682 23:44:20.600077 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4683 23:44:20.603493 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4684 23:44:20.606488 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4685 23:44:20.610026 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4686 23:44:20.616844 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4687 23:44:20.616957 ==
4688 23:44:20.620337 Dram Type= 6, Freq= 0, CH_1, rank 1
4689 23:44:20.623381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4690 23:44:20.623471 ==
4691 23:44:20.623535 DQS Delay:
4692 23:44:20.626765 DQS0 = 0, DQS1 = 0
4693 23:44:20.626849 DQM Delay:
4694 23:44:20.629986 DQM0 = 37, DQM1 = 34
4695 23:44:20.630072 DQ Delay:
4696 23:44:20.633625 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =33
4697 23:44:20.636635 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4698 23:44:20.640187 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4699 23:44:20.643661 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41
4700 23:44:20.643804
4701 23:44:20.643899
4702 23:44:20.644013 ==
4703 23:44:20.646780 Dram Type= 6, Freq= 0, CH_1, rank 1
4704 23:44:20.650433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4705 23:44:20.650586 ==
4706 23:44:20.653758
4707 23:44:20.653868
4708 23:44:20.653974 TX Vref Scan disable
4709 23:44:20.656576 == TX Byte 0 ==
4710 23:44:20.660606 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4711 23:44:20.663266 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4712 23:44:20.666761 == TX Byte 1 ==
4713 23:44:20.670024 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4714 23:44:20.673674 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4715 23:44:20.673791 ==
4716 23:44:20.676569 Dram Type= 6, Freq= 0, CH_1, rank 1
4717 23:44:20.683349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4718 23:44:20.683507 ==
4719 23:44:20.683605
4720 23:44:20.683693
4721 23:44:20.683811 TX Vref Scan disable
4722 23:44:20.688343 == TX Byte 0 ==
4723 23:44:20.691605 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4724 23:44:20.694881 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4725 23:44:20.697737 == TX Byte 1 ==
4726 23:44:20.701406 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4727 23:44:20.704730 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4728 23:44:20.707876
4729 23:44:20.708000 [DATLAT]
4730 23:44:20.708094 Freq=600, CH1 RK1
4731 23:44:20.708186
4732 23:44:20.711669 DATLAT Default: 0x9
4733 23:44:20.711808 0, 0xFFFF, sum = 0
4734 23:44:20.714635 1, 0xFFFF, sum = 0
4735 23:44:20.714745 2, 0xFFFF, sum = 0
4736 23:44:20.718245 3, 0xFFFF, sum = 0
4737 23:44:20.721722 4, 0xFFFF, sum = 0
4738 23:44:20.722010 5, 0xFFFF, sum = 0
4739 23:44:20.724613 6, 0xFFFF, sum = 0
4740 23:44:20.724720 7, 0xFFFF, sum = 0
4741 23:44:20.727537 8, 0x0, sum = 1
4742 23:44:20.727651 9, 0x0, sum = 2
4743 23:44:20.727780 10, 0x0, sum = 3
4744 23:44:20.731475 11, 0x0, sum = 4
4745 23:44:20.731588 best_step = 9
4746 23:44:20.731679
4747 23:44:20.731805 ==
4748 23:44:20.734560 Dram Type= 6, Freq= 0, CH_1, rank 1
4749 23:44:20.741070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4750 23:44:20.741210 ==
4751 23:44:20.741310 RX Vref Scan: 0
4752 23:44:20.741395
4753 23:44:20.744819 RX Vref 0 -> 0, step: 1
4754 23:44:20.744925
4755 23:44:20.748137 RX Delay -195 -> 252, step: 8
4756 23:44:20.750953 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4757 23:44:20.757707 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4758 23:44:20.760936 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4759 23:44:20.764835 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4760 23:44:20.767974 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4761 23:44:20.770843 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4762 23:44:20.777936 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4763 23:44:20.781104 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4764 23:44:20.784329 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4765 23:44:20.787828 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4766 23:44:20.794900 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4767 23:44:20.798012 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4768 23:44:20.801309 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4769 23:44:20.805016 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4770 23:44:20.808110 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4771 23:44:20.814994 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4772 23:44:20.815158 ==
4773 23:44:20.818319 Dram Type= 6, Freq= 0, CH_1, rank 1
4774 23:44:20.821203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4775 23:44:20.821317 ==
4776 23:44:20.821434 DQS Delay:
4777 23:44:20.824638 DQS0 = 0, DQS1 = 0
4778 23:44:20.824747 DQM Delay:
4779 23:44:20.827678 DQM0 = 37, DQM1 = 32
4780 23:44:20.827788 DQ Delay:
4781 23:44:20.831078 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4782 23:44:20.835052 DQ4 =40, DQ5 =48, DQ6 =48, DQ7 =32
4783 23:44:20.837809 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =24
4784 23:44:20.841641 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4785 23:44:20.841775
4786 23:44:20.841898
4787 23:44:20.848323 [DQSOSCAuto] RK1, (LSB)MR18= 0x3543, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 399 ps
4788 23:44:20.851489 CH1 RK1: MR19=808, MR18=3543
4789 23:44:20.857955 CH1_RK1: MR19=0x808, MR18=0x3543, DQSOSC=397, MR23=63, INC=166, DEC=110
4790 23:44:20.861459 [RxdqsGatingPostProcess] freq 600
4791 23:44:20.868454 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4792 23:44:20.871707 Pre-setting of DQS Precalculation
4793 23:44:20.874615 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4794 23:44:20.881894 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4795 23:44:20.888074 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4796 23:44:20.888205
4797 23:44:20.888297
4798 23:44:20.891683 [Calibration Summary] 1200 Mbps
4799 23:44:20.895063 CH 0, Rank 0
4800 23:44:20.895190 SW Impedance : PASS
4801 23:44:20.898208 DUTY Scan : NO K
4802 23:44:20.901646 ZQ Calibration : PASS
4803 23:44:20.901762 Jitter Meter : NO K
4804 23:44:20.905123 CBT Training : PASS
4805 23:44:20.908066 Write leveling : PASS
4806 23:44:20.908195 RX DQS gating : PASS
4807 23:44:20.911442 RX DQ/DQS(RDDQC) : PASS
4808 23:44:20.911561 TX DQ/DQS : PASS
4809 23:44:20.915286 RX DATLAT : PASS
4810 23:44:20.918183 RX DQ/DQS(Engine): PASS
4811 23:44:20.918306 TX OE : NO K
4812 23:44:20.921421 All Pass.
4813 23:44:20.921532
4814 23:44:20.921628 CH 0, Rank 1
4815 23:44:20.924697 SW Impedance : PASS
4816 23:44:20.924803 DUTY Scan : NO K
4817 23:44:20.928104 ZQ Calibration : PASS
4818 23:44:20.931435 Jitter Meter : NO K
4819 23:44:20.931554 CBT Training : PASS
4820 23:44:20.935159 Write leveling : PASS
4821 23:44:20.938072 RX DQS gating : PASS
4822 23:44:20.938183 RX DQ/DQS(RDDQC) : PASS
4823 23:44:20.941660 TX DQ/DQS : PASS
4824 23:44:20.944903 RX DATLAT : PASS
4825 23:44:20.945083 RX DQ/DQS(Engine): PASS
4826 23:44:20.948587 TX OE : NO K
4827 23:44:20.948708 All Pass.
4828 23:44:20.948795
4829 23:44:20.951253 CH 1, Rank 0
4830 23:44:20.951361 SW Impedance : PASS
4831 23:44:20.954830 DUTY Scan : NO K
4832 23:44:20.954945 ZQ Calibration : PASS
4833 23:44:20.958210 Jitter Meter : NO K
4834 23:44:20.961463 CBT Training : PASS
4835 23:44:20.961575 Write leveling : PASS
4836 23:44:20.965161 RX DQS gating : PASS
4837 23:44:20.968575 RX DQ/DQS(RDDQC) : PASS
4838 23:44:20.968691 TX DQ/DQS : PASS
4839 23:44:20.971768 RX DATLAT : PASS
4840 23:44:20.975028 RX DQ/DQS(Engine): PASS
4841 23:44:20.975144 TX OE : NO K
4842 23:44:20.978138 All Pass.
4843 23:44:20.978316
4844 23:44:20.978410 CH 1, Rank 1
4845 23:44:20.981832 SW Impedance : PASS
4846 23:44:20.981944 DUTY Scan : NO K
4847 23:44:20.984647 ZQ Calibration : PASS
4848 23:44:20.988890 Jitter Meter : NO K
4849 23:44:20.989046 CBT Training : PASS
4850 23:44:20.992703 Write leveling : PASS
4851 23:44:20.994655 RX DQS gating : PASS
4852 23:44:20.994769 RX DQ/DQS(RDDQC) : PASS
4853 23:44:20.998292 TX DQ/DQS : PASS
4854 23:44:20.998409 RX DATLAT : PASS
4855 23:44:21.001515 RX DQ/DQS(Engine): PASS
4856 23:44:21.004879 TX OE : NO K
4857 23:44:21.005011 All Pass.
4858 23:44:21.005119
4859 23:44:21.008539 DramC Write-DBI off
4860 23:44:21.008650 PER_BANK_REFRESH: Hybrid Mode
4861 23:44:21.011750 TX_TRACKING: ON
4862 23:44:21.018336 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4863 23:44:21.024674 [FAST_K] Save calibration result to emmc
4864 23:44:21.028341 dramc_set_vcore_voltage set vcore to 662500
4865 23:44:21.028478 Read voltage for 933, 3
4866 23:44:21.031370 Vio18 = 0
4867 23:44:21.031481 Vcore = 662500
4868 23:44:21.031574 Vdram = 0
4869 23:44:21.034770 Vddq = 0
4870 23:44:21.034896 Vmddr = 0
4871 23:44:21.038416 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4872 23:44:21.044656 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4873 23:44:21.048131 MEM_TYPE=3, freq_sel=17
4874 23:44:21.051542 sv_algorithm_assistance_LP4_1600
4875 23:44:21.054902 ============ PULL DRAM RESETB DOWN ============
4876 23:44:21.057939 ========== PULL DRAM RESETB DOWN end =========
4877 23:44:21.061521 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4878 23:44:21.064883 ===================================
4879 23:44:21.068132 LPDDR4 DRAM CONFIGURATION
4880 23:44:21.071569 ===================================
4881 23:44:21.075049 EX_ROW_EN[0] = 0x0
4882 23:44:21.075163 EX_ROW_EN[1] = 0x0
4883 23:44:21.077994 LP4Y_EN = 0x0
4884 23:44:21.078105 WORK_FSP = 0x0
4885 23:44:21.081448 WL = 0x3
4886 23:44:21.081568 RL = 0x3
4887 23:44:21.084830 BL = 0x2
4888 23:44:21.084937 RPST = 0x0
4889 23:44:21.088134 RD_PRE = 0x0
4890 23:44:21.088259 WR_PRE = 0x1
4891 23:44:21.091263 WR_PST = 0x0
4892 23:44:21.095207 DBI_WR = 0x0
4893 23:44:21.095323 DBI_RD = 0x0
4894 23:44:21.097946 OTF = 0x1
4895 23:44:21.101586 ===================================
4896 23:44:21.104905 ===================================
4897 23:44:21.105055 ANA top config
4898 23:44:21.107849 ===================================
4899 23:44:21.111332 DLL_ASYNC_EN = 0
4900 23:44:21.114483 ALL_SLAVE_EN = 1
4901 23:44:21.114579 NEW_RANK_MODE = 1
4902 23:44:21.118154 DLL_IDLE_MODE = 1
4903 23:44:21.121341 LP45_APHY_COMB_EN = 1
4904 23:44:21.124410 TX_ODT_DIS = 1
4905 23:44:21.124540 NEW_8X_MODE = 1
4906 23:44:21.128194 ===================================
4907 23:44:21.131631 ===================================
4908 23:44:21.134996 data_rate = 1866
4909 23:44:21.137839 CKR = 1
4910 23:44:21.141158 DQ_P2S_RATIO = 8
4911 23:44:21.144913 ===================================
4912 23:44:21.148313 CA_P2S_RATIO = 8
4913 23:44:21.151378 DQ_CA_OPEN = 0
4914 23:44:21.151507 DQ_SEMI_OPEN = 0
4915 23:44:21.154722 CA_SEMI_OPEN = 0
4916 23:44:21.158259 CA_FULL_RATE = 0
4917 23:44:21.161912 DQ_CKDIV4_EN = 1
4918 23:44:21.164490 CA_CKDIV4_EN = 1
4919 23:44:21.168117 CA_PREDIV_EN = 0
4920 23:44:21.168239 PH8_DLY = 0
4921 23:44:21.171511 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4922 23:44:21.174954 DQ_AAMCK_DIV = 4
4923 23:44:21.177879 CA_AAMCK_DIV = 4
4924 23:44:21.181398 CA_ADMCK_DIV = 4
4925 23:44:21.181507 DQ_TRACK_CA_EN = 0
4926 23:44:21.184892 CA_PICK = 933
4927 23:44:21.188114 CA_MCKIO = 933
4928 23:44:21.191604 MCKIO_SEMI = 0
4929 23:44:21.195091 PLL_FREQ = 3732
4930 23:44:21.197850 DQ_UI_PI_RATIO = 32
4931 23:44:21.201457 CA_UI_PI_RATIO = 0
4932 23:44:21.204893 ===================================
4933 23:44:21.208157 ===================================
4934 23:44:21.208274 memory_type:LPDDR4
4935 23:44:21.211291 GP_NUM : 10
4936 23:44:21.214614 SRAM_EN : 1
4937 23:44:21.214728 MD32_EN : 0
4938 23:44:21.217878 ===================================
4939 23:44:21.221171 [ANA_INIT] >>>>>>>>>>>>>>
4940 23:44:21.224761 <<<<<< [CONFIGURE PHASE]: ANA_TX
4941 23:44:21.227760 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4942 23:44:21.231112 ===================================
4943 23:44:21.234810 data_rate = 1866,PCW = 0X8f00
4944 23:44:21.237965 ===================================
4945 23:44:21.241084 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4946 23:44:21.244767 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4947 23:44:21.251488 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4948 23:44:21.254766 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4949 23:44:21.257987 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4950 23:44:21.261288 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4951 23:44:21.264667 [ANA_INIT] flow start
4952 23:44:21.268082 [ANA_INIT] PLL >>>>>>>>
4953 23:44:21.268218 [ANA_INIT] PLL <<<<<<<<
4954 23:44:21.271543 [ANA_INIT] MIDPI >>>>>>>>
4955 23:44:21.274709 [ANA_INIT] MIDPI <<<<<<<<
4956 23:44:21.274837 [ANA_INIT] DLL >>>>>>>>
4957 23:44:21.278121 [ANA_INIT] flow end
4958 23:44:21.281593 ============ LP4 DIFF to SE enter ============
4959 23:44:21.284635 ============ LP4 DIFF to SE exit ============
4960 23:44:21.287928 [ANA_INIT] <<<<<<<<<<<<<
4961 23:44:21.291294 [Flow] Enable top DCM control >>>>>
4962 23:44:21.294481 [Flow] Enable top DCM control <<<<<
4963 23:44:21.297976 Enable DLL master slave shuffle
4964 23:44:21.304887 ==============================================================
4965 23:44:21.305106 Gating Mode config
4966 23:44:21.311686 ==============================================================
4967 23:44:21.311857 Config description:
4968 23:44:21.321183 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4969 23:44:21.327845 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4970 23:44:21.334696 SELPH_MODE 0: By rank 1: By Phase
4971 23:44:21.337856 ==============================================================
4972 23:44:21.341106 GAT_TRACK_EN = 1
4973 23:44:21.344484 RX_GATING_MODE = 2
4974 23:44:21.347756 RX_GATING_TRACK_MODE = 2
4975 23:44:21.351488 SELPH_MODE = 1
4976 23:44:21.354848 PICG_EARLY_EN = 1
4977 23:44:21.357802 VALID_LAT_VALUE = 1
4978 23:44:21.364891 ==============================================================
4979 23:44:21.368207 Enter into Gating configuration >>>>
4980 23:44:21.371674 Exit from Gating configuration <<<<
4981 23:44:21.371786 Enter into DVFS_PRE_config >>>>>
4982 23:44:21.384399 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4983 23:44:21.388113 Exit from DVFS_PRE_config <<<<<
4984 23:44:21.391288 Enter into PICG configuration >>>>
4985 23:44:21.394632 Exit from PICG configuration <<<<
4986 23:44:21.394744 [RX_INPUT] configuration >>>>>
4987 23:44:21.398270 [RX_INPUT] configuration <<<<<
4988 23:44:21.404477 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4989 23:44:21.408324 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4990 23:44:21.414564 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4991 23:44:21.421367 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4992 23:44:21.428082 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4993 23:44:21.434958 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4994 23:44:21.438297 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4995 23:44:21.441611 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4996 23:44:21.444832 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4997 23:44:21.451360 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4998 23:44:21.454913 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4999 23:44:21.458332 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5000 23:44:21.461225 ===================================
5001 23:44:21.464505 LPDDR4 DRAM CONFIGURATION
5002 23:44:21.467860 ===================================
5003 23:44:21.471737 EX_ROW_EN[0] = 0x0
5004 23:44:21.471850 EX_ROW_EN[1] = 0x0
5005 23:44:21.474446 LP4Y_EN = 0x0
5006 23:44:21.474530 WORK_FSP = 0x0
5007 23:44:21.477752 WL = 0x3
5008 23:44:21.477839 RL = 0x3
5009 23:44:21.481271 BL = 0x2
5010 23:44:21.481364 RPST = 0x0
5011 23:44:21.484708 RD_PRE = 0x0
5012 23:44:21.484796 WR_PRE = 0x1
5013 23:44:21.487468 WR_PST = 0x0
5014 23:44:21.487557 DBI_WR = 0x0
5015 23:44:21.491141 DBI_RD = 0x0
5016 23:44:21.491230 OTF = 0x1
5017 23:44:21.494937 ===================================
5018 23:44:21.501104 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5019 23:44:21.504240 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5020 23:44:21.507738 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5021 23:44:21.511246 ===================================
5022 23:44:21.514823 LPDDR4 DRAM CONFIGURATION
5023 23:44:21.517831 ===================================
5024 23:44:21.521034 EX_ROW_EN[0] = 0x10
5025 23:44:21.521130 EX_ROW_EN[1] = 0x0
5026 23:44:21.524802 LP4Y_EN = 0x0
5027 23:44:21.524911 WORK_FSP = 0x0
5028 23:44:21.528064 WL = 0x3
5029 23:44:21.528156 RL = 0x3
5030 23:44:21.530881 BL = 0x2
5031 23:44:21.530967 RPST = 0x0
5032 23:44:21.534796 RD_PRE = 0x0
5033 23:44:21.534912 WR_PRE = 0x1
5034 23:44:21.537746 WR_PST = 0x0
5035 23:44:21.537831 DBI_WR = 0x0
5036 23:44:21.541309 DBI_RD = 0x0
5037 23:44:21.541393 OTF = 0x1
5038 23:44:21.544294 ===================================
5039 23:44:21.551335 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5040 23:44:21.555083 nWR fixed to 30
5041 23:44:21.558690 [ModeRegInit_LP4] CH0 RK0
5042 23:44:21.558791 [ModeRegInit_LP4] CH0 RK1
5043 23:44:21.562378 [ModeRegInit_LP4] CH1 RK0
5044 23:44:21.565247 [ModeRegInit_LP4] CH1 RK1
5045 23:44:21.565365 match AC timing 9
5046 23:44:21.571920 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5047 23:44:21.575675 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5048 23:44:21.578614 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5049 23:44:21.585551 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5050 23:44:21.588748 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5051 23:44:21.588873 ==
5052 23:44:21.592202 Dram Type= 6, Freq= 0, CH_0, rank 0
5053 23:44:21.595347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5054 23:44:21.595440 ==
5055 23:44:21.602337 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5056 23:44:21.608943 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5057 23:44:21.612085 [CA 0] Center 38 (8~69) winsize 62
5058 23:44:21.615414 [CA 1] Center 38 (7~69) winsize 63
5059 23:44:21.618789 [CA 2] Center 35 (5~66) winsize 62
5060 23:44:21.622255 [CA 3] Center 35 (4~66) winsize 63
5061 23:44:21.625816 [CA 4] Center 34 (4~64) winsize 61
5062 23:44:21.628546 [CA 5] Center 34 (4~64) winsize 61
5063 23:44:21.628647
5064 23:44:21.632084 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5065 23:44:21.632183
5066 23:44:21.635216 [CATrainingPosCal] consider 1 rank data
5067 23:44:21.638560 u2DelayCellTimex100 = 270/100 ps
5068 23:44:21.641912 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5069 23:44:21.644877 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5070 23:44:21.648249 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5071 23:44:21.652435 CA3 delay=35 (4~66),Diff = 1 PI (6 cell)
5072 23:44:21.655119 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5073 23:44:21.658916 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5074 23:44:21.659054
5075 23:44:21.665612 CA PerBit enable=1, Macro0, CA PI delay=34
5076 23:44:21.665785
5077 23:44:21.665883 [CBTSetCACLKResult] CA Dly = 34
5078 23:44:21.668858 CS Dly: 6 (0~37)
5079 23:44:21.668993 ==
5080 23:44:21.672105 Dram Type= 6, Freq= 0, CH_0, rank 1
5081 23:44:21.675688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5082 23:44:21.675819 ==
5083 23:44:21.681960 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5084 23:44:21.688457 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5085 23:44:21.691790 [CA 0] Center 38 (7~69) winsize 63
5086 23:44:21.694830 [CA 1] Center 38 (7~69) winsize 63
5087 23:44:21.698263 [CA 2] Center 35 (5~66) winsize 62
5088 23:44:21.701533 [CA 3] Center 35 (4~66) winsize 63
5089 23:44:21.705007 [CA 4] Center 34 (4~65) winsize 62
5090 23:44:21.708252 [CA 5] Center 33 (3~64) winsize 62
5091 23:44:21.708371
5092 23:44:21.711974 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5093 23:44:21.712081
5094 23:44:21.715019 [CATrainingPosCal] consider 2 rank data
5095 23:44:21.718833 u2DelayCellTimex100 = 270/100 ps
5096 23:44:21.722054 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5097 23:44:21.725388 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5098 23:44:21.728341 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5099 23:44:21.731902 CA3 delay=35 (4~66),Diff = 1 PI (6 cell)
5100 23:44:21.734990 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5101 23:44:21.738482 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5102 23:44:21.738628
5103 23:44:21.745176 CA PerBit enable=1, Macro0, CA PI delay=34
5104 23:44:21.745281
5105 23:44:21.745348 [CBTSetCACLKResult] CA Dly = 34
5106 23:44:21.748640 CS Dly: 7 (0~39)
5107 23:44:21.748752
5108 23:44:21.751598 ----->DramcWriteLeveling(PI) begin...
5109 23:44:21.751695 ==
5110 23:44:21.755233 Dram Type= 6, Freq= 0, CH_0, rank 0
5111 23:44:21.758753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5112 23:44:21.758864 ==
5113 23:44:21.761937 Write leveling (Byte 0): 32 => 32
5114 23:44:21.764909 Write leveling (Byte 1): 27 => 27
5115 23:44:21.768509 DramcWriteLeveling(PI) end<-----
5116 23:44:21.768623
5117 23:44:21.768690 ==
5118 23:44:21.771904 Dram Type= 6, Freq= 0, CH_0, rank 0
5119 23:44:21.775203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5120 23:44:21.778289 ==
5121 23:44:21.778399 [Gating] SW mode calibration
5122 23:44:21.785434 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5123 23:44:21.791828 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5124 23:44:21.795102 0 14 0 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
5125 23:44:21.802014 0 14 4 | B1->B0 | 2c2c 3434 | 1 1 | (0 0) (1 1)
5126 23:44:21.805377 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5127 23:44:21.808325 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5128 23:44:21.814804 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5129 23:44:21.818039 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5130 23:44:21.821507 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5131 23:44:21.828700 0 14 28 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
5132 23:44:21.831649 0 15 0 | B1->B0 | 3434 2a2a | 1 0 | (1 0) (0 0)
5133 23:44:21.834967 0 15 4 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
5134 23:44:21.841653 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5135 23:44:21.845247 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5136 23:44:21.847966 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5137 23:44:21.854865 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5138 23:44:21.858397 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5139 23:44:21.861597 0 15 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5140 23:44:21.868065 1 0 0 | B1->B0 | 2e2e 3f3f | 1 0 | (0 0) (0 0)
5141 23:44:21.871670 1 0 4 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
5142 23:44:21.874644 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5143 23:44:21.878372 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5144 23:44:21.884775 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5145 23:44:21.888285 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5146 23:44:21.891581 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5147 23:44:21.898263 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5148 23:44:21.901685 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5149 23:44:21.905203 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5150 23:44:21.911621 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 23:44:21.914645 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 23:44:21.918159 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 23:44:21.925282 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 23:44:21.928185 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 23:44:21.931726 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 23:44:21.938524 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 23:44:21.942099 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5158 23:44:21.944643 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5159 23:44:21.951587 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5160 23:44:21.954801 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 23:44:21.958603 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 23:44:21.961787 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 23:44:21.968186 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5164 23:44:21.971807 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5165 23:44:21.975174 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5166 23:44:21.978458 Total UI for P1: 0, mck2ui 16
5167 23:44:21.981699 best dqsien dly found for B0: ( 1, 2, 30)
5168 23:44:21.988297 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5169 23:44:21.988414 Total UI for P1: 0, mck2ui 16
5170 23:44:21.995239 best dqsien dly found for B1: ( 1, 3, 2)
5171 23:44:21.998342 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5172 23:44:22.001914 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5173 23:44:22.002012
5174 23:44:22.004857 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5175 23:44:22.008081 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5176 23:44:22.011624 [Gating] SW calibration Done
5177 23:44:22.011721 ==
5178 23:44:22.014925 Dram Type= 6, Freq= 0, CH_0, rank 0
5179 23:44:22.018138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5180 23:44:22.018233 ==
5181 23:44:22.021508 RX Vref Scan: 0
5182 23:44:22.021595
5183 23:44:22.021683 RX Vref 0 -> 0, step: 1
5184 23:44:22.021772
5185 23:44:22.024755 RX Delay -80 -> 252, step: 8
5186 23:44:22.028247 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5187 23:44:22.035222 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5188 23:44:22.038600 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5189 23:44:22.041562 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5190 23:44:22.045094 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5191 23:44:22.048558 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5192 23:44:22.052053 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5193 23:44:22.055278 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5194 23:44:22.061901 iDelay=208, Bit 8, Center 75 (-16 ~ 167) 184
5195 23:44:22.065321 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5196 23:44:22.068340 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5197 23:44:22.071909 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5198 23:44:22.075059 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5199 23:44:22.078754 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5200 23:44:22.085540 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5201 23:44:22.088667 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5202 23:44:22.088822 ==
5203 23:44:22.091756 Dram Type= 6, Freq= 0, CH_0, rank 0
5204 23:44:22.095304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5205 23:44:22.095461 ==
5206 23:44:22.095577 DQS Delay:
5207 23:44:22.098724 DQS0 = 0, DQS1 = 0
5208 23:44:22.098872 DQM Delay:
5209 23:44:22.101919 DQM0 = 97, DQM1 = 87
5210 23:44:22.102058 DQ Delay:
5211 23:44:22.105347 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =95
5212 23:44:22.108747 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =103
5213 23:44:22.111872 DQ8 =75, DQ9 =75, DQ10 =87, DQ11 =79
5214 23:44:22.115028 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =95
5215 23:44:22.115190
5216 23:44:22.115311
5217 23:44:22.115429 ==
5218 23:44:22.118759 Dram Type= 6, Freq= 0, CH_0, rank 0
5219 23:44:22.124775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5220 23:44:22.124959 ==
5221 23:44:22.125127
5222 23:44:22.125241
5223 23:44:22.125360 TX Vref Scan disable
5224 23:44:22.128390 == TX Byte 0 ==
5225 23:44:22.132274 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5226 23:44:22.134871 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5227 23:44:22.138588 == TX Byte 1 ==
5228 23:44:22.141887 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5229 23:44:22.144835 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5230 23:44:22.148225 ==
5231 23:44:22.151957 Dram Type= 6, Freq= 0, CH_0, rank 0
5232 23:44:22.155452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5233 23:44:22.155607 ==
5234 23:44:22.155714
5235 23:44:22.155818
5236 23:44:22.158397 TX Vref Scan disable
5237 23:44:22.158521 == TX Byte 0 ==
5238 23:44:22.164828 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5239 23:44:22.168585 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5240 23:44:22.168759 == TX Byte 1 ==
5241 23:44:22.175110 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5242 23:44:22.178364 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5243 23:44:22.178558
5244 23:44:22.178678 [DATLAT]
5245 23:44:22.181711 Freq=933, CH0 RK0
5246 23:44:22.181852
5247 23:44:22.181966 DATLAT Default: 0xd
5248 23:44:22.185184 0, 0xFFFF, sum = 0
5249 23:44:22.185346 1, 0xFFFF, sum = 0
5250 23:44:22.188813 2, 0xFFFF, sum = 0
5251 23:44:22.188947 3, 0xFFFF, sum = 0
5252 23:44:22.191706 4, 0xFFFF, sum = 0
5253 23:44:22.191845 5, 0xFFFF, sum = 0
5254 23:44:22.195448 6, 0xFFFF, sum = 0
5255 23:44:22.195590 7, 0xFFFF, sum = 0
5256 23:44:22.198483 8, 0xFFFF, sum = 0
5257 23:44:22.198619 9, 0xFFFF, sum = 0
5258 23:44:22.202227 10, 0x0, sum = 1
5259 23:44:22.202373 11, 0x0, sum = 2
5260 23:44:22.205142 12, 0x0, sum = 3
5261 23:44:22.205276 13, 0x0, sum = 4
5262 23:44:22.208612 best_step = 11
5263 23:44:22.208756
5264 23:44:22.208878 ==
5265 23:44:22.211995 Dram Type= 6, Freq= 0, CH_0, rank 0
5266 23:44:22.215210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5267 23:44:22.215366 ==
5268 23:44:22.218656 RX Vref Scan: 1
5269 23:44:22.218806
5270 23:44:22.218932 RX Vref 0 -> 0, step: 1
5271 23:44:22.219045
5272 23:44:22.222190 RX Delay -61 -> 252, step: 4
5273 23:44:22.222331
5274 23:44:22.225675 Set Vref, RX VrefLevel [Byte0]: 54
5275 23:44:22.228290 [Byte1]: 51
5276 23:44:22.232388
5277 23:44:22.232567 Final RX Vref Byte 0 = 54 to rank0
5278 23:44:22.236038 Final RX Vref Byte 1 = 51 to rank0
5279 23:44:22.239060 Final RX Vref Byte 0 = 54 to rank1
5280 23:44:22.242714 Final RX Vref Byte 1 = 51 to rank1==
5281 23:44:22.246004 Dram Type= 6, Freq= 0, CH_0, rank 0
5282 23:44:22.252255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5283 23:44:22.252438 ==
5284 23:44:22.252549 DQS Delay:
5285 23:44:22.252657 DQS0 = 0, DQS1 = 0
5286 23:44:22.255884 DQM Delay:
5287 23:44:22.256031 DQM0 = 96, DQM1 = 88
5288 23:44:22.259170 DQ Delay:
5289 23:44:22.262498 DQ0 =98, DQ1 =98, DQ2 =92, DQ3 =94
5290 23:44:22.266211 DQ4 =98, DQ5 =88, DQ6 =104, DQ7 =102
5291 23:44:22.266370 DQ8 =78, DQ9 =76, DQ10 =90, DQ11 =80
5292 23:44:22.272424 DQ12 =96, DQ13 =92, DQ14 =98, DQ15 =98
5293 23:44:22.272602
5294 23:44:22.272716
5295 23:44:22.279215 [DQSOSCAuto] RK0, (LSB)MR18= 0x1500, (MSB)MR19= 0x505, tDQSOscB0 = 422 ps tDQSOscB1 = 415 ps
5296 23:44:22.282617 CH0 RK0: MR19=505, MR18=1500
5297 23:44:22.289044 CH0_RK0: MR19=0x505, MR18=0x1500, DQSOSC=415, MR23=63, INC=62, DEC=41
5298 23:44:22.289237
5299 23:44:22.292652 ----->DramcWriteLeveling(PI) begin...
5300 23:44:22.292786 ==
5301 23:44:22.296196 Dram Type= 6, Freq= 0, CH_0, rank 1
5302 23:44:22.299600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5303 23:44:22.299756 ==
5304 23:44:22.302418 Write leveling (Byte 0): 30 => 30
5305 23:44:22.306156 Write leveling (Byte 1): 29 => 29
5306 23:44:22.308948 DramcWriteLeveling(PI) end<-----
5307 23:44:22.309068
5308 23:44:22.309136 ==
5309 23:44:22.312305 Dram Type= 6, Freq= 0, CH_0, rank 1
5310 23:44:22.315658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5311 23:44:22.315792 ==
5312 23:44:22.319140 [Gating] SW mode calibration
5313 23:44:22.326024 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5314 23:44:22.332483 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5315 23:44:22.336306 0 14 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
5316 23:44:22.339285 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5317 23:44:22.345731 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5318 23:44:22.349239 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5319 23:44:22.352588 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5320 23:44:22.359551 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5321 23:44:22.362435 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
5322 23:44:22.365716 0 14 28 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 0)
5323 23:44:22.372478 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
5324 23:44:22.376148 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5325 23:44:22.379543 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5326 23:44:22.385848 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5327 23:44:22.389667 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5328 23:44:22.393015 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5329 23:44:22.399387 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5330 23:44:22.402327 0 15 28 | B1->B0 | 2828 3838 | 0 0 | (0 0) (0 0)
5331 23:44:22.405750 1 0 0 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
5332 23:44:22.409228 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5333 23:44:22.415768 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5334 23:44:22.419479 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5335 23:44:22.422438 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5336 23:44:22.429270 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5337 23:44:22.432938 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5338 23:44:22.436195 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5339 23:44:22.442899 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5340 23:44:22.446054 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5341 23:44:22.449550 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5342 23:44:22.455935 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 23:44:22.459209 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 23:44:22.462531 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 23:44:22.469236 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 23:44:22.472827 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5347 23:44:22.475858 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5348 23:44:22.482545 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5349 23:44:22.485971 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5350 23:44:22.489345 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5351 23:44:22.496304 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5352 23:44:22.499105 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 23:44:22.502514 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5354 23:44:22.506123 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5355 23:44:22.512531 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5356 23:44:22.515763 Total UI for P1: 0, mck2ui 16
5357 23:44:22.518937 best dqsien dly found for B0: ( 1, 2, 26)
5358 23:44:22.522788 Total UI for P1: 0, mck2ui 16
5359 23:44:22.525957 best dqsien dly found for B1: ( 1, 2, 30)
5360 23:44:22.529529 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5361 23:44:22.532250 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5362 23:44:22.532366
5363 23:44:22.535924 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5364 23:44:22.539422 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5365 23:44:22.542960 [Gating] SW calibration Done
5366 23:44:22.543068 ==
5367 23:44:22.545660 Dram Type= 6, Freq= 0, CH_0, rank 1
5368 23:44:22.549381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5369 23:44:22.549497 ==
5370 23:44:22.552874 RX Vref Scan: 0
5371 23:44:22.552999
5372 23:44:22.553083 RX Vref 0 -> 0, step: 1
5373 23:44:22.555755
5374 23:44:22.555841 RX Delay -80 -> 252, step: 8
5375 23:44:22.559435 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5376 23:44:22.565962 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5377 23:44:22.569083 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5378 23:44:22.572651 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5379 23:44:22.575737 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5380 23:44:22.578831 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5381 23:44:22.582448 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5382 23:44:22.588988 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5383 23:44:22.592482 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5384 23:44:22.596429 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5385 23:44:22.598903 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5386 23:44:22.602594 iDelay=208, Bit 11, Center 75 (-16 ~ 167) 184
5387 23:44:22.605670 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5388 23:44:22.612652 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5389 23:44:22.615791 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5390 23:44:22.619082 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5391 23:44:22.619270 ==
5392 23:44:22.622502 Dram Type= 6, Freq= 0, CH_0, rank 1
5393 23:44:22.625693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5394 23:44:22.625845 ==
5395 23:44:22.629510 DQS Delay:
5396 23:44:22.629654 DQS0 = 0, DQS1 = 0
5397 23:44:22.629777 DQM Delay:
5398 23:44:22.632629 DQM0 = 98, DQM1 = 87
5399 23:44:22.632754 DQ Delay:
5400 23:44:22.635708 DQ0 =99, DQ1 =99, DQ2 =95, DQ3 =95
5401 23:44:22.638918 DQ4 =95, DQ5 =87, DQ6 =107, DQ7 =107
5402 23:44:22.642570 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =75
5403 23:44:22.646152 DQ12 =91, DQ13 =95, DQ14 =99, DQ15 =95
5404 23:44:22.646313
5405 23:44:22.646436
5406 23:44:22.646533 ==
5407 23:44:22.649646 Dram Type= 6, Freq= 0, CH_0, rank 1
5408 23:44:22.655884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5409 23:44:22.656091 ==
5410 23:44:22.656207
5411 23:44:22.656319
5412 23:44:22.656435 TX Vref Scan disable
5413 23:44:22.659717 == TX Byte 0 ==
5414 23:44:22.663245 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5415 23:44:22.669479 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5416 23:44:22.669674 == TX Byte 1 ==
5417 23:44:22.673238 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5418 23:44:22.676557 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5419 23:44:22.680029 ==
5420 23:44:22.682786 Dram Type= 6, Freq= 0, CH_0, rank 1
5421 23:44:22.686520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5422 23:44:22.686664 ==
5423 23:44:22.686827
5424 23:44:22.686919
5425 23:44:22.689654 TX Vref Scan disable
5426 23:44:22.689785 == TX Byte 0 ==
5427 23:44:22.696056 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5428 23:44:22.699296 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5429 23:44:22.699437 == TX Byte 1 ==
5430 23:44:22.706161 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5431 23:44:22.709601 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5432 23:44:22.709737
5433 23:44:22.709867 [DATLAT]
5434 23:44:22.712724 Freq=933, CH0 RK1
5435 23:44:22.712846
5436 23:44:22.712965 DATLAT Default: 0xb
5437 23:44:22.716554 0, 0xFFFF, sum = 0
5438 23:44:22.716675 1, 0xFFFF, sum = 0
5439 23:44:22.719410 2, 0xFFFF, sum = 0
5440 23:44:22.719521 3, 0xFFFF, sum = 0
5441 23:44:22.722861 4, 0xFFFF, sum = 0
5442 23:44:22.722978 5, 0xFFFF, sum = 0
5443 23:44:22.726447 6, 0xFFFF, sum = 0
5444 23:44:22.726583 7, 0xFFFF, sum = 0
5445 23:44:22.729391 8, 0xFFFF, sum = 0
5446 23:44:22.732826 9, 0xFFFF, sum = 0
5447 23:44:22.732953 10, 0x0, sum = 1
5448 23:44:22.733112 11, 0x0, sum = 2
5449 23:44:22.736377 12, 0x0, sum = 3
5450 23:44:22.736489 13, 0x0, sum = 4
5451 23:44:22.739433 best_step = 11
5452 23:44:22.739547
5453 23:44:22.739639 ==
5454 23:44:22.742870 Dram Type= 6, Freq= 0, CH_0, rank 1
5455 23:44:22.745870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5456 23:44:22.746003 ==
5457 23:44:22.749815 RX Vref Scan: 0
5458 23:44:22.749949
5459 23:44:22.750043 RX Vref 0 -> 0, step: 1
5460 23:44:22.750132
5461 23:44:22.752628 RX Delay -61 -> 252, step: 4
5462 23:44:22.760365 iDelay=199, Bit 0, Center 96 (3 ~ 190) 188
5463 23:44:22.763635 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5464 23:44:22.767380 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5465 23:44:22.770304 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5466 23:44:22.773387 iDelay=199, Bit 4, Center 94 (3 ~ 186) 184
5467 23:44:22.776759 iDelay=199, Bit 5, Center 84 (-9 ~ 178) 188
5468 23:44:22.783341 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5469 23:44:22.786954 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5470 23:44:22.790278 iDelay=199, Bit 8, Center 82 (-5 ~ 170) 176
5471 23:44:22.793774 iDelay=199, Bit 9, Center 80 (-9 ~ 170) 180
5472 23:44:22.796816 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5473 23:44:22.799997 iDelay=199, Bit 11, Center 80 (-5 ~ 166) 172
5474 23:44:22.806864 iDelay=199, Bit 12, Center 90 (-1 ~ 182) 184
5475 23:44:22.810301 iDelay=199, Bit 13, Center 94 (7 ~ 182) 176
5476 23:44:22.813355 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5477 23:44:22.816793 iDelay=199, Bit 15, Center 96 (11 ~ 182) 172
5478 23:44:22.816877 ==
5479 23:44:22.820270 Dram Type= 6, Freq= 0, CH_0, rank 1
5480 23:44:22.823666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5481 23:44:22.826902 ==
5482 23:44:22.826983 DQS Delay:
5483 23:44:22.827046 DQS0 = 0, DQS1 = 0
5484 23:44:22.830462 DQM Delay:
5485 23:44:22.830542 DQM0 = 95, DQM1 = 88
5486 23:44:22.833626 DQ Delay:
5487 23:44:22.836542 DQ0 =96, DQ1 =96, DQ2 =92, DQ3 =94
5488 23:44:22.840041 DQ4 =94, DQ5 =84, DQ6 =106, DQ7 =102
5489 23:44:22.843487 DQ8 =82, DQ9 =80, DQ10 =88, DQ11 =80
5490 23:44:22.846685 DQ12 =90, DQ13 =94, DQ14 =100, DQ15 =96
5491 23:44:22.846766
5492 23:44:22.846829
5493 23:44:22.853714 [DQSOSCAuto] RK1, (LSB)MR18= 0x1604, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 414 ps
5494 23:44:22.856895 CH0 RK1: MR19=505, MR18=1604
5495 23:44:22.863522 CH0_RK1: MR19=0x505, MR18=0x1604, DQSOSC=414, MR23=63, INC=63, DEC=42
5496 23:44:22.867101 [RxdqsGatingPostProcess] freq 933
5497 23:44:22.869894 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5498 23:44:22.873100 best DQS0 dly(2T, 0.5T) = (0, 10)
5499 23:44:22.876854 best DQS1 dly(2T, 0.5T) = (0, 11)
5500 23:44:22.879698 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5501 23:44:22.883020 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5502 23:44:22.886437 best DQS0 dly(2T, 0.5T) = (0, 10)
5503 23:44:22.890252 best DQS1 dly(2T, 0.5T) = (0, 10)
5504 23:44:22.893098 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5505 23:44:22.896659 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5506 23:44:22.900195 Pre-setting of DQS Precalculation
5507 23:44:22.903058 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5508 23:44:22.903140 ==
5509 23:44:22.906659 Dram Type= 6, Freq= 0, CH_1, rank 0
5510 23:44:22.913131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5511 23:44:22.913215 ==
5512 23:44:22.916741 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5513 23:44:22.923344 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5514 23:44:22.926417 [CA 0] Center 37 (7~67) winsize 61
5515 23:44:22.929770 [CA 1] Center 36 (6~67) winsize 62
5516 23:44:22.933031 [CA 2] Center 34 (4~64) winsize 61
5517 23:44:22.936426 [CA 3] Center 33 (3~64) winsize 62
5518 23:44:22.940382 [CA 4] Center 34 (4~64) winsize 61
5519 23:44:22.943194 [CA 5] Center 33 (3~64) winsize 62
5520 23:44:22.943276
5521 23:44:22.946780 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5522 23:44:22.946861
5523 23:44:22.950099 [CATrainingPosCal] consider 1 rank data
5524 23:44:22.952934 u2DelayCellTimex100 = 270/100 ps
5525 23:44:22.956544 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5526 23:44:22.960080 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5527 23:44:22.963193 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5528 23:44:22.969875 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5529 23:44:22.973488 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5530 23:44:22.976227 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5531 23:44:22.976310
5532 23:44:22.979685 CA PerBit enable=1, Macro0, CA PI delay=33
5533 23:44:22.979769
5534 23:44:22.983232 [CBTSetCACLKResult] CA Dly = 33
5535 23:44:22.983313 CS Dly: 4 (0~35)
5536 23:44:22.983376 ==
5537 23:44:22.986435 Dram Type= 6, Freq= 0, CH_1, rank 1
5538 23:44:22.993554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5539 23:44:22.993636 ==
5540 23:44:22.996654 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5541 23:44:23.003207 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5542 23:44:23.006776 [CA 0] Center 36 (6~67) winsize 62
5543 23:44:23.009833 [CA 1] Center 36 (6~67) winsize 62
5544 23:44:23.013168 [CA 2] Center 33 (3~64) winsize 62
5545 23:44:23.016428 [CA 3] Center 33 (3~64) winsize 62
5546 23:44:23.019754 [CA 4] Center 34 (4~65) winsize 62
5547 23:44:23.023153 [CA 5] Center 33 (3~63) winsize 61
5548 23:44:23.023233
5549 23:44:23.026267 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5550 23:44:23.026347
5551 23:44:23.029616 [CATrainingPosCal] consider 2 rank data
5552 23:44:23.033064 u2DelayCellTimex100 = 270/100 ps
5553 23:44:23.036339 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5554 23:44:23.039939 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5555 23:44:23.043264 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5556 23:44:23.046627 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5557 23:44:23.053585 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5558 23:44:23.056571 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5559 23:44:23.056653
5560 23:44:23.059839 CA PerBit enable=1, Macro0, CA PI delay=33
5561 23:44:23.059919
5562 23:44:23.063124 [CBTSetCACLKResult] CA Dly = 33
5563 23:44:23.063207 CS Dly: 5 (0~37)
5564 23:44:23.063270
5565 23:44:23.066666 ----->DramcWriteLeveling(PI) begin...
5566 23:44:23.066749 ==
5567 23:44:23.070213 Dram Type= 6, Freq= 0, CH_1, rank 0
5568 23:44:23.076443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5569 23:44:23.076525 ==
5570 23:44:23.080112 Write leveling (Byte 0): 25 => 25
5571 23:44:23.080192 Write leveling (Byte 1): 31 => 31
5572 23:44:23.083383 DramcWriteLeveling(PI) end<-----
5573 23:44:23.083577
5574 23:44:23.083672 ==
5575 23:44:23.086544 Dram Type= 6, Freq= 0, CH_1, rank 0
5576 23:44:23.093395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5577 23:44:23.093478 ==
5578 23:44:23.097086 [Gating] SW mode calibration
5579 23:44:23.103224 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5580 23:44:23.106859 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5581 23:44:23.113811 0 14 0 | B1->B0 | 2e2e 3434 | 0 0 | (0 0) (0 0)
5582 23:44:23.117266 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5583 23:44:23.119903 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5584 23:44:23.126645 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5585 23:44:23.130002 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5586 23:44:23.133548 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5587 23:44:23.137081 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5588 23:44:23.143879 0 14 28 | B1->B0 | 2f2f 2f2f | 1 1 | (1 0) (1 0)
5589 23:44:23.146883 0 15 0 | B1->B0 | 2525 2424 | 0 0 | (0 0) (0 0)
5590 23:44:23.150539 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5591 23:44:23.156651 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5592 23:44:23.160118 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5593 23:44:23.163873 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5594 23:44:23.170295 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5595 23:44:23.174071 0 15 24 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
5596 23:44:23.176680 0 15 28 | B1->B0 | 2828 2d2d | 0 0 | (0 0) (0 0)
5597 23:44:23.183534 1 0 0 | B1->B0 | 4545 4242 | 0 0 | (0 0) (0 0)
5598 23:44:23.187043 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5599 23:44:23.190426 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5600 23:44:23.197109 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5601 23:44:23.200370 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5602 23:44:23.203370 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5603 23:44:23.210377 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5604 23:44:23.213550 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5605 23:44:23.216918 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5606 23:44:23.220454 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 23:44:23.226762 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 23:44:23.230526 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 23:44:23.233872 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 23:44:23.240269 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 23:44:23.243511 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 23:44:23.247201 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 23:44:23.253915 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5614 23:44:23.257093 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 23:44:23.260478 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 23:44:23.267029 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 23:44:23.270332 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 23:44:23.273594 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 23:44:23.280227 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5620 23:44:23.283745 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5621 23:44:23.287032 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5622 23:44:23.290338 Total UI for P1: 0, mck2ui 16
5623 23:44:23.293233 best dqsien dly found for B0: ( 1, 2, 28)
5624 23:44:23.296896 Total UI for P1: 0, mck2ui 16
5625 23:44:23.300046 best dqsien dly found for B1: ( 1, 2, 26)
5626 23:44:23.303646 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5627 23:44:23.306652 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5628 23:44:23.306733
5629 23:44:23.310228 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5630 23:44:23.316515 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5631 23:44:23.316600 [Gating] SW calibration Done
5632 23:44:23.319930 ==
5633 23:44:23.320037 Dram Type= 6, Freq= 0, CH_1, rank 0
5634 23:44:23.326876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5635 23:44:23.326960 ==
5636 23:44:23.327024 RX Vref Scan: 0
5637 23:44:23.327083
5638 23:44:23.330131 RX Vref 0 -> 0, step: 1
5639 23:44:23.330212
5640 23:44:23.332921 RX Delay -80 -> 252, step: 8
5641 23:44:23.336401 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5642 23:44:23.339543 iDelay=200, Bit 1, Center 91 (0 ~ 183) 184
5643 23:44:23.342835 iDelay=200, Bit 2, Center 83 (-8 ~ 175) 184
5644 23:44:23.349827 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5645 23:44:23.352944 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5646 23:44:23.356085 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5647 23:44:23.359778 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5648 23:44:23.363208 iDelay=200, Bit 7, Center 95 (0 ~ 191) 192
5649 23:44:23.366120 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5650 23:44:23.372639 iDelay=200, Bit 9, Center 75 (-24 ~ 175) 200
5651 23:44:23.376487 iDelay=200, Bit 10, Center 91 (-8 ~ 191) 200
5652 23:44:23.379479 iDelay=200, Bit 11, Center 83 (-16 ~ 183) 200
5653 23:44:23.382905 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5654 23:44:23.386386 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5655 23:44:23.389245 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5656 23:44:23.396155 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5657 23:44:23.396236 ==
5658 23:44:23.399256 Dram Type= 6, Freq= 0, CH_1, rank 0
5659 23:44:23.402734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5660 23:44:23.402815 ==
5661 23:44:23.402879 DQS Delay:
5662 23:44:23.405906 DQS0 = 0, DQS1 = 0
5663 23:44:23.405986 DQM Delay:
5664 23:44:23.409527 DQM0 = 96, DQM1 = 88
5665 23:44:23.409607 DQ Delay:
5666 23:44:23.412804 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =95
5667 23:44:23.416257 DQ4 =95, DQ5 =103, DQ6 =107, DQ7 =95
5668 23:44:23.419359 DQ8 =79, DQ9 =75, DQ10 =91, DQ11 =83
5669 23:44:23.422368 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5670 23:44:23.422451
5671 23:44:23.422514
5672 23:44:23.422573 ==
5673 23:44:23.426263 Dram Type= 6, Freq= 0, CH_1, rank 0
5674 23:44:23.429201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5675 23:44:23.432867 ==
5676 23:44:23.432948
5677 23:44:23.433052
5678 23:44:23.433111 TX Vref Scan disable
5679 23:44:23.436481 == TX Byte 0 ==
5680 23:44:23.439605 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5681 23:44:23.442843 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5682 23:44:23.445700 == TX Byte 1 ==
5683 23:44:23.449005 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5684 23:44:23.452745 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5685 23:44:23.452845 ==
5686 23:44:23.456110 Dram Type= 6, Freq= 0, CH_1, rank 0
5687 23:44:23.462531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5688 23:44:23.462612 ==
5689 23:44:23.462675
5690 23:44:23.462734
5691 23:44:23.462790 TX Vref Scan disable
5692 23:44:23.467366 == TX Byte 0 ==
5693 23:44:23.470726 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5694 23:44:23.473595 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5695 23:44:23.477526 == TX Byte 1 ==
5696 23:44:23.480735 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5697 23:44:23.483558 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5698 23:44:23.486994
5699 23:44:23.487075 [DATLAT]
5700 23:44:23.487138 Freq=933, CH1 RK0
5701 23:44:23.487197
5702 23:44:23.490455 DATLAT Default: 0xd
5703 23:44:23.490534 0, 0xFFFF, sum = 0
5704 23:44:23.494119 1, 0xFFFF, sum = 0
5705 23:44:23.494201 2, 0xFFFF, sum = 0
5706 23:44:23.497082 3, 0xFFFF, sum = 0
5707 23:44:23.497164 4, 0xFFFF, sum = 0
5708 23:44:23.500689 5, 0xFFFF, sum = 0
5709 23:44:23.500771 6, 0xFFFF, sum = 0
5710 23:44:23.504090 7, 0xFFFF, sum = 0
5711 23:44:23.507559 8, 0xFFFF, sum = 0
5712 23:44:23.507641 9, 0xFFFF, sum = 0
5713 23:44:23.507705 10, 0x0, sum = 1
5714 23:44:23.510470 11, 0x0, sum = 2
5715 23:44:23.510551 12, 0x0, sum = 3
5716 23:44:23.514310 13, 0x0, sum = 4
5717 23:44:23.514393 best_step = 11
5718 23:44:23.514456
5719 23:44:23.514515 ==
5720 23:44:23.516953 Dram Type= 6, Freq= 0, CH_1, rank 0
5721 23:44:23.523788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5722 23:44:23.523872 ==
5723 23:44:23.523950 RX Vref Scan: 1
5724 23:44:23.524029
5725 23:44:23.527107 RX Vref 0 -> 0, step: 1
5726 23:44:23.527187
5727 23:44:23.530553 RX Delay -69 -> 252, step: 4
5728 23:44:23.530633
5729 23:44:23.533845 Set Vref, RX VrefLevel [Byte0]: 58
5730 23:44:23.537154 [Byte1]: 52
5731 23:44:23.537234
5732 23:44:23.540850 Final RX Vref Byte 0 = 58 to rank0
5733 23:44:23.543645 Final RX Vref Byte 1 = 52 to rank0
5734 23:44:23.547074 Final RX Vref Byte 0 = 58 to rank1
5735 23:44:23.550646 Final RX Vref Byte 1 = 52 to rank1==
5736 23:44:23.553802 Dram Type= 6, Freq= 0, CH_1, rank 0
5737 23:44:23.557076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5738 23:44:23.557157 ==
5739 23:44:23.560470 DQS Delay:
5740 23:44:23.560550 DQS0 = 0, DQS1 = 0
5741 23:44:23.563750 DQM Delay:
5742 23:44:23.563863 DQM0 = 98, DQM1 = 91
5743 23:44:23.563988 DQ Delay:
5744 23:44:23.566658 DQ0 =102, DQ1 =92, DQ2 =88, DQ3 =98
5745 23:44:23.570464 DQ4 =98, DQ5 =108, DQ6 =106, DQ7 =94
5746 23:44:23.573591 DQ8 =80, DQ9 =80, DQ10 =90, DQ11 =86
5747 23:44:23.576799 DQ12 =98, DQ13 =98, DQ14 =98, DQ15 =98
5748 23:44:23.576882
5749 23:44:23.577007
5750 23:44:23.586821 [DQSOSCAuto] RK0, (LSB)MR18= 0x17f5, (MSB)MR19= 0x504, tDQSOscB0 = 425 ps tDQSOscB1 = 414 ps
5751 23:44:23.590743 CH1 RK0: MR19=504, MR18=17F5
5752 23:44:23.593461 CH1_RK0: MR19=0x504, MR18=0x17F5, DQSOSC=414, MR23=63, INC=63, DEC=42
5753 23:44:23.597141
5754 23:44:23.600115 ----->DramcWriteLeveling(PI) begin...
5755 23:44:23.600199 ==
5756 23:44:23.603571 Dram Type= 6, Freq= 0, CH_1, rank 1
5757 23:44:23.607249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5758 23:44:23.607330 ==
5759 23:44:23.610242 Write leveling (Byte 0): 24 => 24
5760 23:44:23.614236 Write leveling (Byte 1): 25 => 25
5761 23:44:23.616814 DramcWriteLeveling(PI) end<-----
5762 23:44:23.616895
5763 23:44:23.616958 ==
5764 23:44:23.620328 Dram Type= 6, Freq= 0, CH_1, rank 1
5765 23:44:23.623645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5766 23:44:23.623726 ==
5767 23:44:23.626785 [Gating] SW mode calibration
5768 23:44:23.633679 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5769 23:44:23.640604 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5770 23:44:23.643895 0 14 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5771 23:44:23.647344 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5772 23:44:23.650850 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5773 23:44:23.657379 0 14 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5774 23:44:23.660664 0 14 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5775 23:44:23.663916 0 14 20 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
5776 23:44:23.670344 0 14 24 | B1->B0 | 3333 2f2f | 1 0 | (1 1) (0 0)
5777 23:44:23.673776 0 14 28 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
5778 23:44:23.676875 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5779 23:44:23.683852 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5780 23:44:23.686824 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5781 23:44:23.690546 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5782 23:44:23.696883 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5783 23:44:23.700024 0 15 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5784 23:44:23.703381 0 15 24 | B1->B0 | 2626 3939 | 0 0 | (0 0) (1 1)
5785 23:44:23.710342 0 15 28 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
5786 23:44:23.713293 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5787 23:44:23.716995 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5788 23:44:23.723257 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5789 23:44:23.726516 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5790 23:44:23.730183 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5791 23:44:23.736435 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5792 23:44:23.739944 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5793 23:44:23.743459 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5794 23:44:23.750334 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5795 23:44:23.753459 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5796 23:44:23.756323 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5797 23:44:23.763186 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 23:44:23.766146 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 23:44:23.769686 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 23:44:23.776610 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5801 23:44:23.780181 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5802 23:44:23.783761 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5803 23:44:23.789662 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5804 23:44:23.793564 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5805 23:44:23.796637 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 23:44:23.799721 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 23:44:23.806676 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 23:44:23.809923 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5809 23:44:23.812964 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5810 23:44:23.816870 Total UI for P1: 0, mck2ui 16
5811 23:44:23.819877 best dqsien dly found for B0: ( 1, 2, 24)
5812 23:44:23.823134 Total UI for P1: 0, mck2ui 16
5813 23:44:23.826659 best dqsien dly found for B1: ( 1, 2, 24)
5814 23:44:23.830055 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5815 23:44:23.833102 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5816 23:44:23.833196
5817 23:44:23.839725 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5818 23:44:23.843211 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5819 23:44:23.846847 [Gating] SW calibration Done
5820 23:44:23.846929 ==
5821 23:44:23.850140 Dram Type= 6, Freq= 0, CH_1, rank 1
5822 23:44:23.853311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5823 23:44:23.853411 ==
5824 23:44:23.853508 RX Vref Scan: 0
5825 23:44:23.853583
5826 23:44:23.856374 RX Vref 0 -> 0, step: 1
5827 23:44:23.856491
5828 23:44:23.860066 RX Delay -80 -> 252, step: 8
5829 23:44:23.863331 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5830 23:44:23.866976 iDelay=200, Bit 1, Center 91 (-8 ~ 191) 200
5831 23:44:23.870249 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5832 23:44:23.876805 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5833 23:44:23.880360 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5834 23:44:23.883764 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5835 23:44:23.886655 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5836 23:44:23.890110 iDelay=200, Bit 7, Center 91 (0 ~ 183) 184
5837 23:44:23.893365 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5838 23:44:23.896640 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5839 23:44:23.903264 iDelay=200, Bit 10, Center 91 (-8 ~ 191) 200
5840 23:44:23.906734 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5841 23:44:23.910245 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5842 23:44:23.913733 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5843 23:44:23.917168 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5844 23:44:23.920644 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5845 23:44:23.923717 ==
5846 23:44:23.926770 Dram Type= 6, Freq= 0, CH_1, rank 1
5847 23:44:23.930383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5848 23:44:23.930468 ==
5849 23:44:23.930532 DQS Delay:
5850 23:44:23.933958 DQS0 = 0, DQS1 = 0
5851 23:44:23.934039 DQM Delay:
5852 23:44:23.936629 DQM0 = 95, DQM1 = 89
5853 23:44:23.936709 DQ Delay:
5854 23:44:23.940180 DQ0 =95, DQ1 =91, DQ2 =87, DQ3 =95
5855 23:44:23.943762 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =91
5856 23:44:23.947235 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5857 23:44:23.949926 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5858 23:44:23.950007
5859 23:44:23.950071
5860 23:44:23.950149 ==
5861 23:44:23.953735 Dram Type= 6, Freq= 0, CH_1, rank 1
5862 23:44:23.957133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5863 23:44:23.957215 ==
5864 23:44:23.957278
5865 23:44:23.957337
5866 23:44:23.960550 TX Vref Scan disable
5867 23:44:23.963903 == TX Byte 0 ==
5868 23:44:23.967496 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5869 23:44:23.970287 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5870 23:44:23.973548 == TX Byte 1 ==
5871 23:44:23.976928 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5872 23:44:23.980207 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5873 23:44:23.980287 ==
5874 23:44:23.983846 Dram Type= 6, Freq= 0, CH_1, rank 1
5875 23:44:23.987442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5876 23:44:23.990204 ==
5877 23:44:23.990284
5878 23:44:23.990346
5879 23:44:23.990405 TX Vref Scan disable
5880 23:44:23.993680 == TX Byte 0 ==
5881 23:44:23.996891 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5882 23:44:24.000306 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5883 23:44:24.003524 == TX Byte 1 ==
5884 23:44:24.007261 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5885 23:44:24.014194 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5886 23:44:24.014282
5887 23:44:24.014346 [DATLAT]
5888 23:44:24.014405 Freq=933, CH1 RK1
5889 23:44:24.014463
5890 23:44:24.017260 DATLAT Default: 0xb
5891 23:44:24.017341 0, 0xFFFF, sum = 0
5892 23:44:24.020580 1, 0xFFFF, sum = 0
5893 23:44:24.020662 2, 0xFFFF, sum = 0
5894 23:44:24.023502 3, 0xFFFF, sum = 0
5895 23:44:24.023588 4, 0xFFFF, sum = 0
5896 23:44:24.027338 5, 0xFFFF, sum = 0
5897 23:44:24.030341 6, 0xFFFF, sum = 0
5898 23:44:24.030444 7, 0xFFFF, sum = 0
5899 23:44:24.033428 8, 0xFFFF, sum = 0
5900 23:44:24.033511 9, 0xFFFF, sum = 0
5901 23:44:24.037320 10, 0x0, sum = 1
5902 23:44:24.037402 11, 0x0, sum = 2
5903 23:44:24.037467 12, 0x0, sum = 3
5904 23:44:24.040415 13, 0x0, sum = 4
5905 23:44:24.040498 best_step = 11
5906 23:44:24.040561
5907 23:44:24.040620 ==
5908 23:44:24.043913 Dram Type= 6, Freq= 0, CH_1, rank 1
5909 23:44:24.050655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5910 23:44:24.050743 ==
5911 23:44:24.050808 RX Vref Scan: 0
5912 23:44:24.050867
5913 23:44:24.053647 RX Vref 0 -> 0, step: 1
5914 23:44:24.053728
5915 23:44:24.057190 RX Delay -61 -> 252, step: 4
5916 23:44:24.060586 iDelay=199, Bit 0, Center 98 (7 ~ 190) 184
5917 23:44:24.067189 iDelay=199, Bit 1, Center 90 (-1 ~ 182) 184
5918 23:44:24.070211 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5919 23:44:24.074081 iDelay=199, Bit 3, Center 92 (-1 ~ 186) 188
5920 23:44:24.077020 iDelay=199, Bit 4, Center 94 (3 ~ 186) 184
5921 23:44:24.080389 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5922 23:44:24.083691 iDelay=199, Bit 6, Center 104 (15 ~ 194) 180
5923 23:44:24.087362 iDelay=199, Bit 7, Center 90 (-1 ~ 182) 184
5924 23:44:24.093933 iDelay=199, Bit 8, Center 82 (-9 ~ 174) 184
5925 23:44:24.097536 iDelay=199, Bit 9, Center 80 (-9 ~ 170) 180
5926 23:44:24.100312 iDelay=199, Bit 10, Center 94 (3 ~ 186) 184
5927 23:44:24.103847 iDelay=199, Bit 11, Center 84 (-5 ~ 174) 180
5928 23:44:24.107085 iDelay=199, Bit 12, Center 98 (11 ~ 186) 176
5929 23:44:24.114134 iDelay=199, Bit 13, Center 98 (7 ~ 190) 184
5930 23:44:24.117157 iDelay=199, Bit 14, Center 102 (15 ~ 190) 176
5931 23:44:24.120754 iDelay=199, Bit 15, Center 98 (7 ~ 190) 184
5932 23:44:24.120837 ==
5933 23:44:24.123980 Dram Type= 6, Freq= 0, CH_1, rank 1
5934 23:44:24.127155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5935 23:44:24.127236 ==
5936 23:44:24.130664 DQS Delay:
5937 23:44:24.130745 DQS0 = 0, DQS1 = 0
5938 23:44:24.130808 DQM Delay:
5939 23:44:24.133516 DQM0 = 95, DQM1 = 92
5940 23:44:24.133597 DQ Delay:
5941 23:44:24.137102 DQ0 =98, DQ1 =90, DQ2 =86, DQ3 =92
5942 23:44:24.140231 DQ4 =94, DQ5 =106, DQ6 =104, DQ7 =90
5943 23:44:24.143939 DQ8 =82, DQ9 =80, DQ10 =94, DQ11 =84
5944 23:44:24.147186 DQ12 =98, DQ13 =98, DQ14 =102, DQ15 =98
5945 23:44:24.147266
5946 23:44:24.147329
5947 23:44:24.156853 [DQSOSCAuto] RK1, (LSB)MR18= 0xb14, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 418 ps
5948 23:44:24.160549 CH1 RK1: MR19=505, MR18=B14
5949 23:44:24.163319 CH1_RK1: MR19=0x505, MR18=0xB14, DQSOSC=415, MR23=63, INC=62, DEC=41
5950 23:44:24.166798 [RxdqsGatingPostProcess] freq 933
5951 23:44:24.173489 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5952 23:44:24.176829 best DQS0 dly(2T, 0.5T) = (0, 10)
5953 23:44:24.180306 best DQS1 dly(2T, 0.5T) = (0, 10)
5954 23:44:24.183424 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5955 23:44:24.186904 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5956 23:44:24.190400 best DQS0 dly(2T, 0.5T) = (0, 10)
5957 23:44:24.194097 best DQS1 dly(2T, 0.5T) = (0, 10)
5958 23:44:24.196876 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5959 23:44:24.200513 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5960 23:44:24.200631 Pre-setting of DQS Precalculation
5961 23:44:24.207016 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5962 23:44:24.213677 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5963 23:44:24.220221 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5964 23:44:24.220318
5965 23:44:24.220382
5966 23:44:24.223691 [Calibration Summary] 1866 Mbps
5967 23:44:24.226934 CH 0, Rank 0
5968 23:44:24.227016 SW Impedance : PASS
5969 23:44:24.230274 DUTY Scan : NO K
5970 23:44:24.233573 ZQ Calibration : PASS
5971 23:44:24.233655 Jitter Meter : NO K
5972 23:44:24.237298 CBT Training : PASS
5973 23:44:24.237379 Write leveling : PASS
5974 23:44:24.240269 RX DQS gating : PASS
5975 23:44:24.243730 RX DQ/DQS(RDDQC) : PASS
5976 23:44:24.243811 TX DQ/DQS : PASS
5977 23:44:24.247334 RX DATLAT : PASS
5978 23:44:24.250872 RX DQ/DQS(Engine): PASS
5979 23:44:24.250953 TX OE : NO K
5980 23:44:24.253622 All Pass.
5981 23:44:24.253702
5982 23:44:24.253765 CH 0, Rank 1
5983 23:44:24.257088 SW Impedance : PASS
5984 23:44:24.257213 DUTY Scan : NO K
5985 23:44:24.260282 ZQ Calibration : PASS
5986 23:44:24.263657 Jitter Meter : NO K
5987 23:44:24.263737 CBT Training : PASS
5988 23:44:24.267210 Write leveling : PASS
5989 23:44:24.270205 RX DQS gating : PASS
5990 23:44:24.270285 RX DQ/DQS(RDDQC) : PASS
5991 23:44:24.274055 TX DQ/DQS : PASS
5992 23:44:24.274136 RX DATLAT : PASS
5993 23:44:24.276954 RX DQ/DQS(Engine): PASS
5994 23:44:24.280898 TX OE : NO K
5995 23:44:24.281009 All Pass.
5996 23:44:24.281088
5997 23:44:24.281148 CH 1, Rank 0
5998 23:44:24.283462 SW Impedance : PASS
5999 23:44:24.287069 DUTY Scan : NO K
6000 23:44:24.287150 ZQ Calibration : PASS
6001 23:44:24.290162 Jitter Meter : NO K
6002 23:44:24.293419 CBT Training : PASS
6003 23:44:24.293499 Write leveling : PASS
6004 23:44:24.296760 RX DQS gating : PASS
6005 23:44:24.300311 RX DQ/DQS(RDDQC) : PASS
6006 23:44:24.300392 TX DQ/DQS : PASS
6007 23:44:24.303680 RX DATLAT : PASS
6008 23:44:24.306635 RX DQ/DQS(Engine): PASS
6009 23:44:24.306715 TX OE : NO K
6010 23:44:24.309930 All Pass.
6011 23:44:24.310010
6012 23:44:24.310073 CH 1, Rank 1
6013 23:44:24.313510 SW Impedance : PASS
6014 23:44:24.313590 DUTY Scan : NO K
6015 23:44:24.316949 ZQ Calibration : PASS
6016 23:44:24.320129 Jitter Meter : NO K
6017 23:44:24.320209 CBT Training : PASS
6018 23:44:24.323497 Write leveling : PASS
6019 23:44:24.323577 RX DQS gating : PASS
6020 23:44:24.327195 RX DQ/DQS(RDDQC) : PASS
6021 23:44:24.330359 TX DQ/DQS : PASS
6022 23:44:24.330440 RX DATLAT : PASS
6023 23:44:24.333433 RX DQ/DQS(Engine): PASS
6024 23:44:24.336801 TX OE : NO K
6025 23:44:24.336882 All Pass.
6026 23:44:24.336984
6027 23:44:24.340236 DramC Write-DBI off
6028 23:44:24.340316 PER_BANK_REFRESH: Hybrid Mode
6029 23:44:24.343127 TX_TRACKING: ON
6030 23:44:24.353277 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6031 23:44:24.356695 [FAST_K] Save calibration result to emmc
6032 23:44:24.359808 dramc_set_vcore_voltage set vcore to 650000
6033 23:44:24.359889 Read voltage for 400, 6
6034 23:44:24.363688 Vio18 = 0
6035 23:44:24.363769 Vcore = 650000
6036 23:44:24.363832 Vdram = 0
6037 23:44:24.366889 Vddq = 0
6038 23:44:24.366969 Vmddr = 0
6039 23:44:24.370161 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6040 23:44:24.376575 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6041 23:44:24.379931 MEM_TYPE=3, freq_sel=20
6042 23:44:24.383392 sv_algorithm_assistance_LP4_800
6043 23:44:24.386647 ============ PULL DRAM RESETB DOWN ============
6044 23:44:24.389903 ========== PULL DRAM RESETB DOWN end =========
6045 23:44:24.396523 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6046 23:44:24.396606 ===================================
6047 23:44:24.399914 LPDDR4 DRAM CONFIGURATION
6048 23:44:24.403736 ===================================
6049 23:44:24.406509 EX_ROW_EN[0] = 0x0
6050 23:44:24.406592 EX_ROW_EN[1] = 0x0
6051 23:44:24.409956 LP4Y_EN = 0x0
6052 23:44:24.410036 WORK_FSP = 0x0
6053 23:44:24.413697 WL = 0x2
6054 23:44:24.413777 RL = 0x2
6055 23:44:24.416558 BL = 0x2
6056 23:44:24.416639 RPST = 0x0
6057 23:44:24.420062 RD_PRE = 0x0
6058 23:44:24.420133 WR_PRE = 0x1
6059 23:44:24.423224 WR_PST = 0x0
6060 23:44:24.426982 DBI_WR = 0x0
6061 23:44:24.427062 DBI_RD = 0x0
6062 23:44:24.429918 OTF = 0x1
6063 23:44:24.433527 ===================================
6064 23:44:24.436514 ===================================
6065 23:44:24.436595 ANA top config
6066 23:44:24.439926 ===================================
6067 23:44:24.443324 DLL_ASYNC_EN = 0
6068 23:44:24.443404 ALL_SLAVE_EN = 1
6069 23:44:24.446822 NEW_RANK_MODE = 1
6070 23:44:24.449974 DLL_IDLE_MODE = 1
6071 23:44:24.453661 LP45_APHY_COMB_EN = 1
6072 23:44:24.456525 TX_ODT_DIS = 1
6073 23:44:24.456605 NEW_8X_MODE = 1
6074 23:44:24.460006 ===================================
6075 23:44:24.463652 ===================================
6076 23:44:24.466710 data_rate = 800
6077 23:44:24.470306 CKR = 1
6078 23:44:24.473301 DQ_P2S_RATIO = 4
6079 23:44:24.476836 ===================================
6080 23:44:24.480365 CA_P2S_RATIO = 4
6081 23:44:24.480448 DQ_CA_OPEN = 0
6082 23:44:24.483306 DQ_SEMI_OPEN = 1
6083 23:44:24.487073 CA_SEMI_OPEN = 1
6084 23:44:24.490407 CA_FULL_RATE = 0
6085 23:44:24.493450 DQ_CKDIV4_EN = 0
6086 23:44:24.497150 CA_CKDIV4_EN = 1
6087 23:44:24.497233 CA_PREDIV_EN = 0
6088 23:44:24.499884 PH8_DLY = 0
6089 23:44:24.503876 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6090 23:44:24.506831 DQ_AAMCK_DIV = 0
6091 23:44:24.510066 CA_AAMCK_DIV = 0
6092 23:44:24.513599 CA_ADMCK_DIV = 4
6093 23:44:24.513683 DQ_TRACK_CA_EN = 0
6094 23:44:24.516910 CA_PICK = 800
6095 23:44:24.520219 CA_MCKIO = 400
6096 23:44:24.523908 MCKIO_SEMI = 400
6097 23:44:24.526689 PLL_FREQ = 3016
6098 23:44:24.529878 DQ_UI_PI_RATIO = 32
6099 23:44:24.533513 CA_UI_PI_RATIO = 32
6100 23:44:24.537160 ===================================
6101 23:44:24.539956 ===================================
6102 23:44:24.540036 memory_type:LPDDR4
6103 23:44:24.543395 GP_NUM : 10
6104 23:44:24.546682 SRAM_EN : 1
6105 23:44:24.546762 MD32_EN : 0
6106 23:44:24.549926 ===================================
6107 23:44:24.553318 [ANA_INIT] >>>>>>>>>>>>>>
6108 23:44:24.557160 <<<<<< [CONFIGURE PHASE]: ANA_TX
6109 23:44:24.560120 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6110 23:44:24.563775 ===================================
6111 23:44:24.566831 data_rate = 800,PCW = 0X7400
6112 23:44:24.570043 ===================================
6113 23:44:24.573250 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6114 23:44:24.576825 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6115 23:44:24.590264 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6116 23:44:24.593656 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6117 23:44:24.596901 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6118 23:44:24.600114 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6119 23:44:24.603672 [ANA_INIT] flow start
6120 23:44:24.603753 [ANA_INIT] PLL >>>>>>>>
6121 23:44:24.606772 [ANA_INIT] PLL <<<<<<<<
6122 23:44:24.610271 [ANA_INIT] MIDPI >>>>>>>>
6123 23:44:24.610351 [ANA_INIT] MIDPI <<<<<<<<
6124 23:44:24.613398 [ANA_INIT] DLL >>>>>>>>
6125 23:44:24.617010 [ANA_INIT] flow end
6126 23:44:24.620511 ============ LP4 DIFF to SE enter ============
6127 23:44:24.623637 ============ LP4 DIFF to SE exit ============
6128 23:44:24.627330 [ANA_INIT] <<<<<<<<<<<<<
6129 23:44:24.630424 [Flow] Enable top DCM control >>>>>
6130 23:44:24.633732 [Flow] Enable top DCM control <<<<<
6131 23:44:24.637248 Enable DLL master slave shuffle
6132 23:44:24.640558 ==============================================================
6133 23:44:24.643745 Gating Mode config
6134 23:44:24.650108 ==============================================================
6135 23:44:24.650189 Config description:
6136 23:44:24.660413 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6137 23:44:24.666888 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6138 23:44:24.670612 SELPH_MODE 0: By rank 1: By Phase
6139 23:44:24.676830 ==============================================================
6140 23:44:24.680149 GAT_TRACK_EN = 0
6141 23:44:24.684009 RX_GATING_MODE = 2
6142 23:44:24.687262 RX_GATING_TRACK_MODE = 2
6143 23:44:24.690165 SELPH_MODE = 1
6144 23:44:24.693623 PICG_EARLY_EN = 1
6145 23:44:24.696770 VALID_LAT_VALUE = 1
6146 23:44:24.700108 ==============================================================
6147 23:44:24.703308 Enter into Gating configuration >>>>
6148 23:44:24.706779 Exit from Gating configuration <<<<
6149 23:44:24.710006 Enter into DVFS_PRE_config >>>>>
6150 23:44:24.720431 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6151 23:44:24.723492 Exit from DVFS_PRE_config <<<<<
6152 23:44:24.726901 Enter into PICG configuration >>>>
6153 23:44:24.730388 Exit from PICG configuration <<<<
6154 23:44:24.733213 [RX_INPUT] configuration >>>>>
6155 23:44:24.736506 [RX_INPUT] configuration <<<<<
6156 23:44:24.743514 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6157 23:44:24.746743 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6158 23:44:24.753418 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6159 23:44:24.759971 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6160 23:44:24.766792 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6161 23:44:24.773559 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6162 23:44:24.776755 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6163 23:44:24.780604 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6164 23:44:24.783804 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6165 23:44:24.787177 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6166 23:44:24.793790 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6167 23:44:24.797584 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6168 23:44:24.800781 ===================================
6169 23:44:24.803696 LPDDR4 DRAM CONFIGURATION
6170 23:44:24.806816 ===================================
6171 23:44:24.806897 EX_ROW_EN[0] = 0x0
6172 23:44:24.810155 EX_ROW_EN[1] = 0x0
6173 23:44:24.810236 LP4Y_EN = 0x0
6174 23:44:24.813923 WORK_FSP = 0x0
6175 23:44:24.814003 WL = 0x2
6176 23:44:24.817081 RL = 0x2
6177 23:44:24.817161 BL = 0x2
6178 23:44:24.820182 RPST = 0x0
6179 23:44:24.820263 RD_PRE = 0x0
6180 23:44:24.823801 WR_PRE = 0x1
6181 23:44:24.823881 WR_PST = 0x0
6182 23:44:24.827078 DBI_WR = 0x0
6183 23:44:24.830623 DBI_RD = 0x0
6184 23:44:24.830704 OTF = 0x1
6185 23:44:24.833760 ===================================
6186 23:44:24.837081 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6187 23:44:24.840126 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6188 23:44:24.846999 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6189 23:44:24.850302 ===================================
6190 23:44:24.850412 LPDDR4 DRAM CONFIGURATION
6191 23:44:24.853789 ===================================
6192 23:44:24.856925 EX_ROW_EN[0] = 0x10
6193 23:44:24.860328 EX_ROW_EN[1] = 0x0
6194 23:44:24.860434 LP4Y_EN = 0x0
6195 23:44:24.863622 WORK_FSP = 0x0
6196 23:44:24.863702 WL = 0x2
6197 23:44:24.866827 RL = 0x2
6198 23:44:24.866921 BL = 0x2
6199 23:44:24.870414 RPST = 0x0
6200 23:44:24.870520 RD_PRE = 0x0
6201 23:44:24.873737 WR_PRE = 0x1
6202 23:44:24.873817 WR_PST = 0x0
6203 23:44:24.876992 DBI_WR = 0x0
6204 23:44:24.877077 DBI_RD = 0x0
6205 23:44:24.880503 OTF = 0x1
6206 23:44:24.883508 ===================================
6207 23:44:24.890427 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6208 23:44:24.893755 nWR fixed to 30
6209 23:44:24.897161 [ModeRegInit_LP4] CH0 RK0
6210 23:44:24.897246 [ModeRegInit_LP4] CH0 RK1
6211 23:44:24.899955 [ModeRegInit_LP4] CH1 RK0
6212 23:44:24.903348 [ModeRegInit_LP4] CH1 RK1
6213 23:44:24.903429 match AC timing 19
6214 23:44:24.910088 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6215 23:44:24.913767 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6216 23:44:24.917229 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6217 23:44:24.923872 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6218 23:44:24.926786 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6219 23:44:24.926886 ==
6220 23:44:24.930352 Dram Type= 6, Freq= 0, CH_0, rank 0
6221 23:44:24.933773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6222 23:44:24.933862 ==
6223 23:44:24.940372 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6224 23:44:24.946994 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6225 23:44:24.950265 [CA 0] Center 36 (8~64) winsize 57
6226 23:44:24.953689 [CA 1] Center 36 (8~64) winsize 57
6227 23:44:24.953770 [CA 2] Center 36 (8~64) winsize 57
6228 23:44:24.956791 [CA 3] Center 36 (8~64) winsize 57
6229 23:44:24.960025 [CA 4] Center 36 (8~64) winsize 57
6230 23:44:24.963431 [CA 5] Center 36 (8~64) winsize 57
6231 23:44:24.963512
6232 23:44:24.966907 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6233 23:44:24.966988
6234 23:44:24.970232 [CATrainingPosCal] consider 1 rank data
6235 23:44:24.973415 u2DelayCellTimex100 = 270/100 ps
6236 23:44:24.976885 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6237 23:44:24.983787 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6238 23:44:24.986610 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6239 23:44:24.990741 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6240 23:44:24.993461 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6241 23:44:24.997217 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6242 23:44:24.997323
6243 23:44:25.000357 CA PerBit enable=1, Macro0, CA PI delay=36
6244 23:44:25.000442
6245 23:44:25.003675 [CBTSetCACLKResult] CA Dly = 36
6246 23:44:25.003757 CS Dly: 1 (0~32)
6247 23:44:25.006729 ==
6248 23:44:25.009918 Dram Type= 6, Freq= 0, CH_0, rank 1
6249 23:44:25.013379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6250 23:44:25.013465 ==
6251 23:44:25.016472 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6252 23:44:25.023251 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6253 23:44:25.026553 [CA 0] Center 36 (8~64) winsize 57
6254 23:44:25.029991 [CA 1] Center 36 (8~64) winsize 57
6255 23:44:25.033425 [CA 2] Center 36 (8~64) winsize 57
6256 23:44:25.036815 [CA 3] Center 36 (8~64) winsize 57
6257 23:44:25.039824 [CA 4] Center 36 (8~64) winsize 57
6258 23:44:25.043447 [CA 5] Center 36 (8~64) winsize 57
6259 23:44:25.043528
6260 23:44:25.047616 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6261 23:44:25.047698
6262 23:44:25.049946 [CATrainingPosCal] consider 2 rank data
6263 23:44:25.053563 u2DelayCellTimex100 = 270/100 ps
6264 23:44:25.057222 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6265 23:44:25.060087 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6266 23:44:25.063639 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6267 23:44:25.066839 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6268 23:44:25.070076 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6269 23:44:25.076551 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6270 23:44:25.076699
6271 23:44:25.080596 CA PerBit enable=1, Macro0, CA PI delay=36
6272 23:44:25.080677
6273 23:44:25.083296 [CBTSetCACLKResult] CA Dly = 36
6274 23:44:25.083376 CS Dly: 1 (0~32)
6275 23:44:25.083439
6276 23:44:25.087104 ----->DramcWriteLeveling(PI) begin...
6277 23:44:25.087185 ==
6278 23:44:25.090217 Dram Type= 6, Freq= 0, CH_0, rank 0
6279 23:44:25.093443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6280 23:44:25.096709 ==
6281 23:44:25.096790 Write leveling (Byte 0): 40 => 8
6282 23:44:25.100370 Write leveling (Byte 1): 32 => 0
6283 23:44:25.103609 DramcWriteLeveling(PI) end<-----
6284 23:44:25.103709
6285 23:44:25.103788 ==
6286 23:44:25.106947 Dram Type= 6, Freq= 0, CH_0, rank 0
6287 23:44:25.113839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6288 23:44:25.113937 ==
6289 23:44:25.114020 [Gating] SW mode calibration
6290 23:44:25.123793 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6291 23:44:25.126720 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6292 23:44:25.130499 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6293 23:44:25.136495 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6294 23:44:25.140075 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6295 23:44:25.143412 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6296 23:44:25.150170 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6297 23:44:25.153280 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6298 23:44:25.157174 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6299 23:44:25.163577 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6300 23:44:25.166518 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6301 23:44:25.170162 Total UI for P1: 0, mck2ui 16
6302 23:44:25.173446 best dqsien dly found for B0: ( 0, 14, 24)
6303 23:44:25.176557 Total UI for P1: 0, mck2ui 16
6304 23:44:25.179913 best dqsien dly found for B1: ( 0, 14, 24)
6305 23:44:25.183352 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6306 23:44:25.186941 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6307 23:44:25.187022
6308 23:44:25.189730 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6309 23:44:25.193551 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6310 23:44:25.196924 [Gating] SW calibration Done
6311 23:44:25.197024 ==
6312 23:44:25.199792 Dram Type= 6, Freq= 0, CH_0, rank 0
6313 23:44:25.203649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6314 23:44:25.206285 ==
6315 23:44:25.206366 RX Vref Scan: 0
6316 23:44:25.206429
6317 23:44:25.209835 RX Vref 0 -> 0, step: 1
6318 23:44:25.209915
6319 23:44:25.213120 RX Delay -410 -> 252, step: 16
6320 23:44:25.216892 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6321 23:44:25.219634 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6322 23:44:25.222817 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6323 23:44:25.230203 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6324 23:44:25.232924 iDelay=230, Bit 4, Center -19 (-266 ~ 229) 496
6325 23:44:25.236187 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6326 23:44:25.239573 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6327 23:44:25.246162 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6328 23:44:25.249756 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6329 23:44:25.252822 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6330 23:44:25.256406 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6331 23:44:25.263533 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6332 23:44:25.266081 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6333 23:44:25.269332 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6334 23:44:25.276524 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6335 23:44:25.279565 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6336 23:44:25.279646 ==
6337 23:44:25.283171 Dram Type= 6, Freq= 0, CH_0, rank 0
6338 23:44:25.286394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6339 23:44:25.286475 ==
6340 23:44:25.289555 DQS Delay:
6341 23:44:25.289634 DQS0 = 35, DQS1 = 51
6342 23:44:25.289697 DQM Delay:
6343 23:44:25.292703 DQM0 = 8, DQM1 = 10
6344 23:44:25.292783 DQ Delay:
6345 23:44:25.296120 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6346 23:44:25.299240 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6347 23:44:25.302852 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6348 23:44:25.305901 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6349 23:44:25.305981
6350 23:44:25.306044
6351 23:44:25.306102 ==
6352 23:44:25.309329 Dram Type= 6, Freq= 0, CH_0, rank 0
6353 23:44:25.312525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6354 23:44:25.312604 ==
6355 23:44:25.312667
6356 23:44:25.316109
6357 23:44:25.316187 TX Vref Scan disable
6358 23:44:25.319454 == TX Byte 0 ==
6359 23:44:25.322584 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6360 23:44:25.326358 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6361 23:44:25.329626 == TX Byte 1 ==
6362 23:44:25.332793 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6363 23:44:25.336032 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6364 23:44:25.336113 ==
6365 23:44:25.339149 Dram Type= 6, Freq= 0, CH_0, rank 0
6366 23:44:25.342968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6367 23:44:25.346024 ==
6368 23:44:25.346102
6369 23:44:25.346164
6370 23:44:25.346222 TX Vref Scan disable
6371 23:44:25.349720 == TX Byte 0 ==
6372 23:44:25.352822 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6373 23:44:25.356213 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6374 23:44:25.359414 == TX Byte 1 ==
6375 23:44:25.362878 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6376 23:44:25.365985 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6377 23:44:25.366065
6378 23:44:25.369480 [DATLAT]
6379 23:44:25.369560 Freq=400, CH0 RK0
6380 23:44:25.369623
6381 23:44:25.372805 DATLAT Default: 0xf
6382 23:44:25.372884 0, 0xFFFF, sum = 0
6383 23:44:25.376178 1, 0xFFFF, sum = 0
6384 23:44:25.376259 2, 0xFFFF, sum = 0
6385 23:44:25.379260 3, 0xFFFF, sum = 0
6386 23:44:25.379340 4, 0xFFFF, sum = 0
6387 23:44:25.383152 5, 0xFFFF, sum = 0
6388 23:44:25.383233 6, 0xFFFF, sum = 0
6389 23:44:25.386470 7, 0xFFFF, sum = 0
6390 23:44:25.386551 8, 0xFFFF, sum = 0
6391 23:44:25.389874 9, 0xFFFF, sum = 0
6392 23:44:25.389954 10, 0xFFFF, sum = 0
6393 23:44:25.392661 11, 0xFFFF, sum = 0
6394 23:44:25.392743 12, 0xFFFF, sum = 0
6395 23:44:25.396572 13, 0x0, sum = 1
6396 23:44:25.396669 14, 0x0, sum = 2
6397 23:44:25.399278 15, 0x0, sum = 3
6398 23:44:25.399360 16, 0x0, sum = 4
6399 23:44:25.402603 best_step = 14
6400 23:44:25.402683
6401 23:44:25.402746 ==
6402 23:44:25.406040 Dram Type= 6, Freq= 0, CH_0, rank 0
6403 23:44:25.409328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6404 23:44:25.409409 ==
6405 23:44:25.413046 RX Vref Scan: 1
6406 23:44:25.413127
6407 23:44:25.413190 RX Vref 0 -> 0, step: 1
6408 23:44:25.413250
6409 23:44:25.416019 RX Delay -343 -> 252, step: 8
6410 23:44:25.416099
6411 23:44:25.419431 Set Vref, RX VrefLevel [Byte0]: 54
6412 23:44:25.422824 [Byte1]: 51
6413 23:44:25.427218
6414 23:44:25.427298 Final RX Vref Byte 0 = 54 to rank0
6415 23:44:25.430442 Final RX Vref Byte 1 = 51 to rank0
6416 23:44:25.433817 Final RX Vref Byte 0 = 54 to rank1
6417 23:44:25.438891 Final RX Vref Byte 1 = 51 to rank1==
6418 23:44:25.440673 Dram Type= 6, Freq= 0, CH_0, rank 0
6419 23:44:25.447413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6420 23:44:25.447517 ==
6421 23:44:25.447583 DQS Delay:
6422 23:44:25.450427 DQS0 = 44, DQS1 = 60
6423 23:44:25.450530 DQM Delay:
6424 23:44:25.450617 DQM0 = 11, DQM1 = 16
6425 23:44:25.453687 DQ Delay:
6426 23:44:25.457065 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =8
6427 23:44:25.457167 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6428 23:44:25.460290 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =12
6429 23:44:25.463954 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =28
6430 23:44:25.464054
6431 23:44:25.466848
6432 23:44:25.473490 [DQSOSCAuto] RK0, (LSB)MR18= 0x804e, (MSB)MR19= 0xc0c, tDQSOscB0 = 400 ps tDQSOscB1 = 393 ps
6433 23:44:25.476829 CH0 RK0: MR19=C0C, MR18=804E
6434 23:44:25.483890 CH0_RK0: MR19=0xC0C, MR18=0x804E, DQSOSC=393, MR23=63, INC=382, DEC=254
6435 23:44:25.483973 ==
6436 23:44:25.487103 Dram Type= 6, Freq= 0, CH_0, rank 1
6437 23:44:25.490809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6438 23:44:25.490904 ==
6439 23:44:25.493637 [Gating] SW mode calibration
6440 23:44:25.500615 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6441 23:44:25.503816 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6442 23:44:25.510848 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6443 23:44:25.514049 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6444 23:44:25.517244 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6445 23:44:25.523810 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6446 23:44:25.527515 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6447 23:44:25.531044 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6448 23:44:25.537563 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6449 23:44:25.540435 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6450 23:44:25.543738 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6451 23:44:25.547147 Total UI for P1: 0, mck2ui 16
6452 23:44:25.550668 best dqsien dly found for B0: ( 0, 14, 24)
6453 23:44:25.553935 Total UI for P1: 0, mck2ui 16
6454 23:44:25.557372 best dqsien dly found for B1: ( 0, 14, 24)
6455 23:44:25.560777 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6456 23:44:25.563907 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6457 23:44:25.563988
6458 23:44:25.567192 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6459 23:44:25.574341 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6460 23:44:25.574483 [Gating] SW calibration Done
6461 23:44:25.577440 ==
6462 23:44:25.577537 Dram Type= 6, Freq= 0, CH_0, rank 1
6463 23:44:25.583950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6464 23:44:25.584048 ==
6465 23:44:25.584126 RX Vref Scan: 0
6466 23:44:25.584215
6467 23:44:25.587279 RX Vref 0 -> 0, step: 1
6468 23:44:25.587360
6469 23:44:25.590510 RX Delay -410 -> 252, step: 16
6470 23:44:25.594025 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6471 23:44:25.597867 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6472 23:44:25.603927 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6473 23:44:25.607284 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6474 23:44:25.610738 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6475 23:44:25.614166 iDelay=230, Bit 5, Center -43 (-282 ~ 197) 480
6476 23:44:25.620576 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6477 23:44:25.624245 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6478 23:44:25.627307 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6479 23:44:25.630754 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6480 23:44:25.637399 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6481 23:44:25.640818 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6482 23:44:25.644237 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6483 23:44:25.647944 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6484 23:44:25.653954 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6485 23:44:25.657502 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6486 23:44:25.657582 ==
6487 23:44:25.660801 Dram Type= 6, Freq= 0, CH_0, rank 1
6488 23:44:25.664429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6489 23:44:25.664511 ==
6490 23:44:25.667677 DQS Delay:
6491 23:44:25.667758 DQS0 = 43, DQS1 = 51
6492 23:44:25.667821 DQM Delay:
6493 23:44:25.670938 DQM0 = 11, DQM1 = 10
6494 23:44:25.671018 DQ Delay:
6495 23:44:25.673942 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6496 23:44:25.677931 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6497 23:44:25.681340 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6498 23:44:25.684524 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6499 23:44:25.684605
6500 23:44:25.684668
6501 23:44:25.684726 ==
6502 23:44:25.687660 Dram Type= 6, Freq= 0, CH_0, rank 1
6503 23:44:25.690995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6504 23:44:25.691077 ==
6505 23:44:25.694042
6506 23:44:25.694121
6507 23:44:25.694184 TX Vref Scan disable
6508 23:44:25.697364 == TX Byte 0 ==
6509 23:44:25.700899 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6510 23:44:25.704256 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6511 23:44:25.707450 == TX Byte 1 ==
6512 23:44:25.711468 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6513 23:44:25.714368 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6514 23:44:25.714488 ==
6515 23:44:25.717625 Dram Type= 6, Freq= 0, CH_0, rank 1
6516 23:44:25.720793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6517 23:44:25.724109 ==
6518 23:44:25.724189
6519 23:44:25.724251
6520 23:44:25.724310 TX Vref Scan disable
6521 23:44:25.727351 == TX Byte 0 ==
6522 23:44:25.730989 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6523 23:44:25.733873 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6524 23:44:25.737668 == TX Byte 1 ==
6525 23:44:25.740857 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6526 23:44:25.744288 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6527 23:44:25.744369
6528 23:44:25.744433 [DATLAT]
6529 23:44:25.747387 Freq=400, CH0 RK1
6530 23:44:25.747467
6531 23:44:25.747530 DATLAT Default: 0xe
6532 23:44:25.750685 0, 0xFFFF, sum = 0
6533 23:44:25.754154 1, 0xFFFF, sum = 0
6534 23:44:25.754237 2, 0xFFFF, sum = 0
6535 23:44:25.757406 3, 0xFFFF, sum = 0
6536 23:44:25.757491 4, 0xFFFF, sum = 0
6537 23:44:25.761548 5, 0xFFFF, sum = 0
6538 23:44:25.761629 6, 0xFFFF, sum = 0
6539 23:44:25.763846 7, 0xFFFF, sum = 0
6540 23:44:25.763928 8, 0xFFFF, sum = 0
6541 23:44:25.767372 9, 0xFFFF, sum = 0
6542 23:44:25.767469 10, 0xFFFF, sum = 0
6543 23:44:25.770705 11, 0xFFFF, sum = 0
6544 23:44:25.770787 12, 0xFFFF, sum = 0
6545 23:44:25.773948 13, 0x0, sum = 1
6546 23:44:25.774045 14, 0x0, sum = 2
6547 23:44:25.777407 15, 0x0, sum = 3
6548 23:44:25.777489 16, 0x0, sum = 4
6549 23:44:25.780500 best_step = 14
6550 23:44:25.780581
6551 23:44:25.780644 ==
6552 23:44:25.784062 Dram Type= 6, Freq= 0, CH_0, rank 1
6553 23:44:25.787267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6554 23:44:25.787365 ==
6555 23:44:25.787443 RX Vref Scan: 0
6556 23:44:25.790642
6557 23:44:25.790721 RX Vref 0 -> 0, step: 1
6558 23:44:25.790784
6559 23:44:25.793983 RX Delay -343 -> 252, step: 8
6560 23:44:25.801593 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6561 23:44:25.805117 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6562 23:44:25.808367 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6563 23:44:25.811376 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6564 23:44:25.818694 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6565 23:44:25.821708 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6566 23:44:25.824770 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6567 23:44:25.828110 iDelay=217, Bit 7, Center -24 (-263 ~ 216) 480
6568 23:44:25.835088 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6569 23:44:25.838442 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6570 23:44:25.841773 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6571 23:44:25.844774 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6572 23:44:25.851666 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6573 23:44:25.854620 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6574 23:44:25.858581 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6575 23:44:25.864635 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6576 23:44:25.864717 ==
6577 23:44:25.868030 Dram Type= 6, Freq= 0, CH_0, rank 1
6578 23:44:25.871548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6579 23:44:25.871630 ==
6580 23:44:25.871695 DQS Delay:
6581 23:44:25.874971 DQS0 = 48, DQS1 = 60
6582 23:44:25.875051 DQM Delay:
6583 23:44:25.878003 DQM0 = 13, DQM1 = 13
6584 23:44:25.878083 DQ Delay:
6585 23:44:25.881865 DQ0 =16, DQ1 =16, DQ2 =8, DQ3 =12
6586 23:44:25.884445 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =24
6587 23:44:25.887728 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6588 23:44:25.891036 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =24
6589 23:44:25.891116
6590 23:44:25.891178
6591 23:44:25.897685 [DQSOSCAuto] RK1, (LSB)MR18= 0x8e62, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 392 ps
6592 23:44:25.900985 CH0 RK1: MR19=C0C, MR18=8E62
6593 23:44:25.908263 CH0_RK1: MR19=0xC0C, MR18=0x8E62, DQSOSC=392, MR23=63, INC=384, DEC=256
6594 23:44:25.911104 [RxdqsGatingPostProcess] freq 400
6595 23:44:25.917398 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6596 23:44:25.920947 best DQS0 dly(2T, 0.5T) = (0, 10)
6597 23:44:25.921094 best DQS1 dly(2T, 0.5T) = (0, 10)
6598 23:44:25.924475 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6599 23:44:25.927783 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6600 23:44:25.931303 best DQS0 dly(2T, 0.5T) = (0, 10)
6601 23:44:25.934592 best DQS1 dly(2T, 0.5T) = (0, 10)
6602 23:44:25.937892 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6603 23:44:25.940785 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6604 23:44:25.944273 Pre-setting of DQS Precalculation
6605 23:44:25.951072 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6606 23:44:25.951154 ==
6607 23:44:25.954235 Dram Type= 6, Freq= 0, CH_1, rank 0
6608 23:44:25.957659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6609 23:44:25.957741 ==
6610 23:44:25.964129 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6611 23:44:25.967874 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6612 23:44:25.970924 [CA 0] Center 36 (8~64) winsize 57
6613 23:44:25.974551 [CA 1] Center 36 (8~64) winsize 57
6614 23:44:25.978201 [CA 2] Center 36 (8~64) winsize 57
6615 23:44:25.980961 [CA 3] Center 36 (8~64) winsize 57
6616 23:44:25.984682 [CA 4] Center 36 (8~64) winsize 57
6617 23:44:25.987898 [CA 5] Center 36 (8~64) winsize 57
6618 23:44:25.987978
6619 23:44:25.991436 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6620 23:44:25.991525
6621 23:44:25.994166 [CATrainingPosCal] consider 1 rank data
6622 23:44:25.997530 u2DelayCellTimex100 = 270/100 ps
6623 23:44:26.001165 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6624 23:44:26.004078 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6625 23:44:26.007772 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6626 23:44:26.010826 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6627 23:44:26.017765 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6628 23:44:26.021031 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6629 23:44:26.021116
6630 23:44:26.024659 CA PerBit enable=1, Macro0, CA PI delay=36
6631 23:44:26.024740
6632 23:44:26.027569 [CBTSetCACLKResult] CA Dly = 36
6633 23:44:26.027651 CS Dly: 1 (0~32)
6634 23:44:26.027715 ==
6635 23:44:26.031198 Dram Type= 6, Freq= 0, CH_1, rank 1
6636 23:44:26.034285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6637 23:44:26.037834 ==
6638 23:44:26.041210 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6639 23:44:26.047673 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6640 23:44:26.051254 [CA 0] Center 36 (8~64) winsize 57
6641 23:44:26.054522 [CA 1] Center 36 (8~64) winsize 57
6642 23:44:26.057494 [CA 2] Center 36 (8~64) winsize 57
6643 23:44:26.061536 [CA 3] Center 36 (8~64) winsize 57
6644 23:44:26.064397 [CA 4] Center 36 (8~64) winsize 57
6645 23:44:26.067849 [CA 5] Center 36 (8~64) winsize 57
6646 23:44:26.067954
6647 23:44:26.071255 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6648 23:44:26.071355
6649 23:44:26.074137 [CATrainingPosCal] consider 2 rank data
6650 23:44:26.077741 u2DelayCellTimex100 = 270/100 ps
6651 23:44:26.080964 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6652 23:44:26.084423 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6653 23:44:26.087412 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6654 23:44:26.091025 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6655 23:44:26.094272 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6656 23:44:26.097872 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6657 23:44:26.097953
6658 23:44:26.100663 CA PerBit enable=1, Macro0, CA PI delay=36
6659 23:44:26.100774
6660 23:44:26.104619 [CBTSetCACLKResult] CA Dly = 36
6661 23:44:26.107665 CS Dly: 1 (0~32)
6662 23:44:26.107746
6663 23:44:26.110874 ----->DramcWriteLeveling(PI) begin...
6664 23:44:26.110957 ==
6665 23:44:26.114374 Dram Type= 6, Freq= 0, CH_1, rank 0
6666 23:44:26.117360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6667 23:44:26.117459 ==
6668 23:44:26.120822 Write leveling (Byte 0): 40 => 8
6669 23:44:26.124325 Write leveling (Byte 1): 40 => 8
6670 23:44:26.127651 DramcWriteLeveling(PI) end<-----
6671 23:44:26.127737
6672 23:44:26.127822 ==
6673 23:44:26.130870 Dram Type= 6, Freq= 0, CH_1, rank 0
6674 23:44:26.134114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6675 23:44:26.134198 ==
6676 23:44:26.137671 [Gating] SW mode calibration
6677 23:44:26.144092 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6678 23:44:26.151316 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6679 23:44:26.154199 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6680 23:44:26.157646 0 11 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6681 23:44:26.164275 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6682 23:44:26.167532 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6683 23:44:26.171032 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6684 23:44:26.178108 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6685 23:44:26.180823 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6686 23:44:26.184272 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6687 23:44:26.190857 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6688 23:44:26.193877 Total UI for P1: 0, mck2ui 16
6689 23:44:26.197696 best dqsien dly found for B0: ( 0, 14, 24)
6690 23:44:26.197806 Total UI for P1: 0, mck2ui 16
6691 23:44:26.204533 best dqsien dly found for B1: ( 0, 14, 24)
6692 23:44:26.207314 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6693 23:44:26.210891 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6694 23:44:26.210996
6695 23:44:26.214068 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6696 23:44:26.217982 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6697 23:44:26.221345 [Gating] SW calibration Done
6698 23:44:26.221428 ==
6699 23:44:26.224389 Dram Type= 6, Freq= 0, CH_1, rank 0
6700 23:44:26.227552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6701 23:44:26.227663 ==
6702 23:44:26.231393 RX Vref Scan: 0
6703 23:44:26.231475
6704 23:44:26.231540 RX Vref 0 -> 0, step: 1
6705 23:44:26.231600
6706 23:44:26.234028 RX Delay -410 -> 252, step: 16
6707 23:44:26.240957 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6708 23:44:26.244212 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6709 23:44:26.247456 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6710 23:44:26.250846 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6711 23:44:26.257553 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6712 23:44:26.260798 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6713 23:44:26.264827 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6714 23:44:26.267875 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6715 23:44:26.270828 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6716 23:44:26.277823 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6717 23:44:26.281226 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6718 23:44:26.284727 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6719 23:44:26.291526 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6720 23:44:26.294196 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6721 23:44:26.298070 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6722 23:44:26.301160 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6723 23:44:26.301241 ==
6724 23:44:26.304278 Dram Type= 6, Freq= 0, CH_1, rank 0
6725 23:44:26.310883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6726 23:44:26.310968 ==
6727 23:44:26.311033 DQS Delay:
6728 23:44:26.314832 DQS0 = 51, DQS1 = 59
6729 23:44:26.314916 DQM Delay:
6730 23:44:26.314981 DQM0 = 18, DQM1 = 16
6731 23:44:26.317901 DQ Delay:
6732 23:44:26.321285 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6733 23:44:26.324098 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6734 23:44:26.328012 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6735 23:44:26.330833 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6736 23:44:26.330940
6737 23:44:26.331033
6738 23:44:26.331126 ==
6739 23:44:26.334378 Dram Type= 6, Freq= 0, CH_1, rank 0
6740 23:44:26.337562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6741 23:44:26.337643 ==
6742 23:44:26.337708
6743 23:44:26.337768
6744 23:44:26.341332 TX Vref Scan disable
6745 23:44:26.341412 == TX Byte 0 ==
6746 23:44:26.347504 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6747 23:44:26.350860 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6748 23:44:26.350965 == TX Byte 1 ==
6749 23:44:26.354226 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6750 23:44:26.360909 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6751 23:44:26.361049 ==
6752 23:44:26.364436 Dram Type= 6, Freq= 0, CH_1, rank 0
6753 23:44:26.368104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6754 23:44:26.368186 ==
6755 23:44:26.368250
6756 23:44:26.368309
6757 23:44:26.371335 TX Vref Scan disable
6758 23:44:26.371419 == TX Byte 0 ==
6759 23:44:26.378121 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6760 23:44:26.381576 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6761 23:44:26.381657 == TX Byte 1 ==
6762 23:44:26.384723 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6763 23:44:26.391088 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6764 23:44:26.391168
6765 23:44:26.391231 [DATLAT]
6766 23:44:26.391290 Freq=400, CH1 RK0
6767 23:44:26.394383
6768 23:44:26.394456 DATLAT Default: 0xf
6769 23:44:26.397788 0, 0xFFFF, sum = 0
6770 23:44:26.397865 1, 0xFFFF, sum = 0
6771 23:44:26.401075 2, 0xFFFF, sum = 0
6772 23:44:26.401148 3, 0xFFFF, sum = 0
6773 23:44:26.404574 4, 0xFFFF, sum = 0
6774 23:44:26.404654 5, 0xFFFF, sum = 0
6775 23:44:26.407770 6, 0xFFFF, sum = 0
6776 23:44:26.407846 7, 0xFFFF, sum = 0
6777 23:44:26.411046 8, 0xFFFF, sum = 0
6778 23:44:26.411121 9, 0xFFFF, sum = 0
6779 23:44:26.414065 10, 0xFFFF, sum = 0
6780 23:44:26.414142 11, 0xFFFF, sum = 0
6781 23:44:26.417617 12, 0xFFFF, sum = 0
6782 23:44:26.417693 13, 0x0, sum = 1
6783 23:44:26.420849 14, 0x0, sum = 2
6784 23:44:26.420952 15, 0x0, sum = 3
6785 23:44:26.424042 16, 0x0, sum = 4
6786 23:44:26.424118 best_step = 14
6787 23:44:26.424183
6788 23:44:26.424242 ==
6789 23:44:26.427446 Dram Type= 6, Freq= 0, CH_1, rank 0
6790 23:44:26.434041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6791 23:44:26.434124 ==
6792 23:44:26.434187 RX Vref Scan: 1
6793 23:44:26.434261
6794 23:44:26.437627 RX Vref 0 -> 0, step: 1
6795 23:44:26.437701
6796 23:44:26.441198 RX Delay -359 -> 252, step: 8
6797 23:44:26.441278
6798 23:44:26.444039 Set Vref, RX VrefLevel [Byte0]: 58
6799 23:44:26.447580 [Byte1]: 52
6800 23:44:26.447655
6801 23:44:26.451022 Final RX Vref Byte 0 = 58 to rank0
6802 23:44:26.454309 Final RX Vref Byte 1 = 52 to rank0
6803 23:44:26.457430 Final RX Vref Byte 0 = 58 to rank1
6804 23:44:26.460737 Final RX Vref Byte 1 = 52 to rank1==
6805 23:44:26.464098 Dram Type= 6, Freq= 0, CH_1, rank 0
6806 23:44:26.467378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6807 23:44:26.470739 ==
6808 23:44:26.470834 DQS Delay:
6809 23:44:26.470905 DQS0 = 48, DQS1 = 60
6810 23:44:26.474115 DQM Delay:
6811 23:44:26.474189 DQM0 = 12, DQM1 = 13
6812 23:44:26.477586 DQ Delay:
6813 23:44:26.477659 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6814 23:44:26.480771 DQ4 =8, DQ5 =20, DQ6 =24, DQ7 =8
6815 23:44:26.483928 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6816 23:44:26.487532 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6817 23:44:26.487639
6818 23:44:26.487728
6819 23:44:26.497927 [DQSOSCAuto] RK0, (LSB)MR18= 0x8932, (MSB)MR19= 0xc0c, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
6820 23:44:26.500928 CH1 RK0: MR19=C0C, MR18=8932
6821 23:44:26.503975 CH1_RK0: MR19=0xC0C, MR18=0x8932, DQSOSC=392, MR23=63, INC=384, DEC=256
6822 23:44:26.507951 ==
6823 23:44:26.510666 Dram Type= 6, Freq= 0, CH_1, rank 1
6824 23:44:26.513876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6825 23:44:26.513950 ==
6826 23:44:26.517180 [Gating] SW mode calibration
6827 23:44:26.524427 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6828 23:44:26.526917 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6829 23:44:26.534033 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6830 23:44:26.537189 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6831 23:44:26.540652 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6832 23:44:26.546891 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6833 23:44:26.550327 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6834 23:44:26.553637 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6835 23:44:26.560870 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6836 23:44:26.563788 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6837 23:44:26.567076 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6838 23:44:26.570474 Total UI for P1: 0, mck2ui 16
6839 23:44:26.573601 best dqsien dly found for B0: ( 0, 14, 24)
6840 23:44:26.577003 Total UI for P1: 0, mck2ui 16
6841 23:44:26.580578 best dqsien dly found for B1: ( 0, 14, 24)
6842 23:44:26.583795 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6843 23:44:26.587176 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6844 23:44:26.587258
6845 23:44:26.593475 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6846 23:44:26.597360 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6847 23:44:26.597442 [Gating] SW calibration Done
6848 23:44:26.600375 ==
6849 23:44:26.603683 Dram Type= 6, Freq= 0, CH_1, rank 1
6850 23:44:26.606984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6851 23:44:26.607061 ==
6852 23:44:26.607122 RX Vref Scan: 0
6853 23:44:26.607181
6854 23:44:26.610428 RX Vref 0 -> 0, step: 1
6855 23:44:26.610497
6856 23:44:26.613815 RX Delay -410 -> 252, step: 16
6857 23:44:26.617645 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6858 23:44:26.620244 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6859 23:44:26.627553 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6860 23:44:26.630735 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6861 23:44:26.633933 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6862 23:44:26.637531 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6863 23:44:26.643998 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6864 23:44:26.647476 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6865 23:44:26.650628 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6866 23:44:26.653725 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6867 23:44:26.661042 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6868 23:44:26.663826 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6869 23:44:26.667310 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6870 23:44:26.670719 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6871 23:44:26.676961 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6872 23:44:26.680579 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6873 23:44:26.680678 ==
6874 23:44:26.683615 Dram Type= 6, Freq= 0, CH_1, rank 1
6875 23:44:26.687499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6876 23:44:26.687576 ==
6877 23:44:26.690290 DQS Delay:
6878 23:44:26.690402 DQS0 = 43, DQS1 = 59
6879 23:44:26.693823 DQM Delay:
6880 23:44:26.693924 DQM0 = 10, DQM1 = 20
6881 23:44:26.694013 DQ Delay:
6882 23:44:26.697152 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6883 23:44:26.700330 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6884 23:44:26.703743 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6885 23:44:26.707425 DQ12 =24, DQ13 =32, DQ14 =32, DQ15 =32
6886 23:44:26.707532
6887 23:44:26.707638
6888 23:44:26.707724 ==
6889 23:44:26.710478 Dram Type= 6, Freq= 0, CH_1, rank 1
6890 23:44:26.714084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6891 23:44:26.717257 ==
6892 23:44:26.717337
6893 23:44:26.717398
6894 23:44:26.717455 TX Vref Scan disable
6895 23:44:26.720805 == TX Byte 0 ==
6896 23:44:26.724054 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6897 23:44:26.727475 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6898 23:44:26.730671 == TX Byte 1 ==
6899 23:44:26.734377 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6900 23:44:26.737426 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6901 23:44:26.737505 ==
6902 23:44:26.740906 Dram Type= 6, Freq= 0, CH_1, rank 1
6903 23:44:26.743520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6904 23:44:26.747122 ==
6905 23:44:26.747208
6906 23:44:26.747276
6907 23:44:26.747334 TX Vref Scan disable
6908 23:44:26.750459 == TX Byte 0 ==
6909 23:44:26.754322 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6910 23:44:26.756951 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6911 23:44:26.760261 == TX Byte 1 ==
6912 23:44:26.763677 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6913 23:44:26.767163 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6914 23:44:26.767277
6915 23:44:26.767367 [DATLAT]
6916 23:44:26.770411 Freq=400, CH1 RK1
6917 23:44:26.770497
6918 23:44:26.773523 DATLAT Default: 0xe
6919 23:44:26.773601 0, 0xFFFF, sum = 0
6920 23:44:26.776964 1, 0xFFFF, sum = 0
6921 23:44:26.777078 2, 0xFFFF, sum = 0
6922 23:44:26.780416 3, 0xFFFF, sum = 0
6923 23:44:26.780496 4, 0xFFFF, sum = 0
6924 23:44:26.784189 5, 0xFFFF, sum = 0
6925 23:44:26.784287 6, 0xFFFF, sum = 0
6926 23:44:26.787304 7, 0xFFFF, sum = 0
6927 23:44:26.787403 8, 0xFFFF, sum = 0
6928 23:44:26.790923 9, 0xFFFF, sum = 0
6929 23:44:26.791035 10, 0xFFFF, sum = 0
6930 23:44:26.794372 11, 0xFFFF, sum = 0
6931 23:44:26.794445 12, 0xFFFF, sum = 0
6932 23:44:26.797057 13, 0x0, sum = 1
6933 23:44:26.797126 14, 0x0, sum = 2
6934 23:44:26.801118 15, 0x0, sum = 3
6935 23:44:26.801194 16, 0x0, sum = 4
6936 23:44:26.804022 best_step = 14
6937 23:44:26.804091
6938 23:44:26.804162 ==
6939 23:44:26.807801 Dram Type= 6, Freq= 0, CH_1, rank 1
6940 23:44:26.810910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6941 23:44:26.810991 ==
6942 23:44:26.811052 RX Vref Scan: 0
6943 23:44:26.814520
6944 23:44:26.814593 RX Vref 0 -> 0, step: 1
6945 23:44:26.814653
6946 23:44:26.817717 RX Delay -359 -> 252, step: 8
6947 23:44:26.824919 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6948 23:44:26.827963 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6949 23:44:26.831287 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
6950 23:44:26.834549 iDelay=217, Bit 3, Center -40 (-279 ~ 200) 480
6951 23:44:26.841657 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6952 23:44:26.844662 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6953 23:44:26.848091 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6954 23:44:26.851710 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
6955 23:44:26.858033 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6956 23:44:26.861756 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6957 23:44:26.865061 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6958 23:44:26.868239 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6959 23:44:26.874832 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6960 23:44:26.878404 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6961 23:44:26.881507 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6962 23:44:26.884651 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6963 23:44:26.887945 ==
6964 23:44:26.891515 Dram Type= 6, Freq= 0, CH_1, rank 1
6965 23:44:26.894566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6966 23:44:26.894642 ==
6967 23:44:26.894713 DQS Delay:
6968 23:44:26.898203 DQS0 = 52, DQS1 = 56
6969 23:44:26.898301 DQM Delay:
6970 23:44:26.901839 DQM0 = 13, DQM1 = 8
6971 23:44:26.901911 DQ Delay:
6972 23:44:26.904619 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6973 23:44:26.908103 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6974 23:44:26.912031 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6975 23:44:26.915014 DQ12 =12, DQ13 =16, DQ14 =16, DQ15 =16
6976 23:44:26.915098
6977 23:44:26.915160
6978 23:44:26.921661 [DQSOSCAuto] RK1, (LSB)MR18= 0x788d, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 394 ps
6979 23:44:26.925091 CH1 RK1: MR19=C0C, MR18=788D
6980 23:44:26.931480 CH1_RK1: MR19=0xC0C, MR18=0x788D, DQSOSC=392, MR23=63, INC=384, DEC=256
6981 23:44:26.934941 [RxdqsGatingPostProcess] freq 400
6982 23:44:26.937990 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6983 23:44:26.941214 best DQS0 dly(2T, 0.5T) = (0, 10)
6984 23:44:26.944535 best DQS1 dly(2T, 0.5T) = (0, 10)
6985 23:44:26.947995 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6986 23:44:26.951372 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6987 23:44:26.954807 best DQS0 dly(2T, 0.5T) = (0, 10)
6988 23:44:26.958010 best DQS1 dly(2T, 0.5T) = (0, 10)
6989 23:44:26.961429 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6990 23:44:26.965123 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6991 23:44:26.968490 Pre-setting of DQS Precalculation
6992 23:44:26.971653 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6993 23:44:26.978411 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6994 23:44:26.988498 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6995 23:44:26.988576
6996 23:44:26.988707
6997 23:44:26.991523 [Calibration Summary] 800 Mbps
6998 23:44:26.991605 CH 0, Rank 0
6999 23:44:26.994886 SW Impedance : PASS
7000 23:44:26.994964 DUTY Scan : NO K
7001 23:44:26.998092 ZQ Calibration : PASS
7002 23:44:27.001463 Jitter Meter : NO K
7003 23:44:27.001537 CBT Training : PASS
7004 23:44:27.004700 Write leveling : PASS
7005 23:44:27.004770 RX DQS gating : PASS
7006 23:44:27.008386 RX DQ/DQS(RDDQC) : PASS
7007 23:44:27.011669 TX DQ/DQS : PASS
7008 23:44:27.011737 RX DATLAT : PASS
7009 23:44:27.015219 RX DQ/DQS(Engine): PASS
7010 23:44:27.018682 TX OE : NO K
7011 23:44:27.018750 All Pass.
7012 23:44:27.018808
7013 23:44:27.018864 CH 0, Rank 1
7014 23:44:27.021949 SW Impedance : PASS
7015 23:44:27.024872 DUTY Scan : NO K
7016 23:44:27.024938 ZQ Calibration : PASS
7017 23:44:27.028428 Jitter Meter : NO K
7018 23:44:27.031933 CBT Training : PASS
7019 23:44:27.032017 Write leveling : NO K
7020 23:44:27.034654 RX DQS gating : PASS
7021 23:44:27.038424 RX DQ/DQS(RDDQC) : PASS
7022 23:44:27.038490 TX DQ/DQS : PASS
7023 23:44:27.041521 RX DATLAT : PASS
7024 23:44:27.041585 RX DQ/DQS(Engine): PASS
7025 23:44:27.044746 TX OE : NO K
7026 23:44:27.044819 All Pass.
7027 23:44:27.044879
7028 23:44:27.047983 CH 1, Rank 0
7029 23:44:27.048048 SW Impedance : PASS
7030 23:44:27.051699 DUTY Scan : NO K
7031 23:44:27.055008 ZQ Calibration : PASS
7032 23:44:27.055090 Jitter Meter : NO K
7033 23:44:27.058353 CBT Training : PASS
7034 23:44:27.061946 Write leveling : PASS
7035 23:44:27.062026 RX DQS gating : PASS
7036 23:44:27.065247 RX DQ/DQS(RDDQC) : PASS
7037 23:44:27.067885 TX DQ/DQS : PASS
7038 23:44:27.067965 RX DATLAT : PASS
7039 23:44:27.071848 RX DQ/DQS(Engine): PASS
7040 23:44:27.074604 TX OE : NO K
7041 23:44:27.074684 All Pass.
7042 23:44:27.074747
7043 23:44:27.074806 CH 1, Rank 1
7044 23:44:27.078556 SW Impedance : PASS
7045 23:44:27.081698 DUTY Scan : NO K
7046 23:44:27.081777 ZQ Calibration : PASS
7047 23:44:27.085122 Jitter Meter : NO K
7048 23:44:27.085202 CBT Training : PASS
7049 23:44:27.088452 Write leveling : NO K
7050 23:44:27.091494 RX DQS gating : PASS
7051 23:44:27.091574 RX DQ/DQS(RDDQC) : PASS
7052 23:44:27.094895 TX DQ/DQS : PASS
7053 23:44:27.098554 RX DATLAT : PASS
7054 23:44:27.098634 RX DQ/DQS(Engine): PASS
7055 23:44:27.101862 TX OE : NO K
7056 23:44:27.101943 All Pass.
7057 23:44:27.102005
7058 23:44:27.105282 DramC Write-DBI off
7059 23:44:27.108134 PER_BANK_REFRESH: Hybrid Mode
7060 23:44:27.108221 TX_TRACKING: ON
7061 23:44:27.118751 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7062 23:44:27.121586 [FAST_K] Save calibration result to emmc
7063 23:44:27.125228 dramc_set_vcore_voltage set vcore to 725000
7064 23:44:27.128703 Read voltage for 1600, 0
7065 23:44:27.128774 Vio18 = 0
7066 23:44:27.128838 Vcore = 725000
7067 23:44:27.131426 Vdram = 0
7068 23:44:27.131493 Vddq = 0
7069 23:44:27.131559 Vmddr = 0
7070 23:44:27.138125 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7071 23:44:27.141785 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7072 23:44:27.145115 MEM_TYPE=3, freq_sel=13
7073 23:44:27.148493 sv_algorithm_assistance_LP4_3733
7074 23:44:27.151473 ============ PULL DRAM RESETB DOWN ============
7075 23:44:27.155468 ========== PULL DRAM RESETB DOWN end =========
7076 23:44:27.162220 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7077 23:44:27.164914 ===================================
7078 23:44:27.165021 LPDDR4 DRAM CONFIGURATION
7079 23:44:27.168228 ===================================
7080 23:44:27.171631 EX_ROW_EN[0] = 0x0
7081 23:44:27.175202 EX_ROW_EN[1] = 0x0
7082 23:44:27.175298 LP4Y_EN = 0x0
7083 23:44:27.178740 WORK_FSP = 0x1
7084 23:44:27.178813 WL = 0x5
7085 23:44:27.181713 RL = 0x5
7086 23:44:27.181785 BL = 0x2
7087 23:44:27.185660 RPST = 0x0
7088 23:44:27.185730 RD_PRE = 0x0
7089 23:44:27.188517 WR_PRE = 0x1
7090 23:44:27.188601 WR_PST = 0x1
7091 23:44:27.192092 DBI_WR = 0x0
7092 23:44:27.192172 DBI_RD = 0x0
7093 23:44:27.195257 OTF = 0x1
7094 23:44:27.198520 ===================================
7095 23:44:27.201765 ===================================
7096 23:44:27.201846 ANA top config
7097 23:44:27.205120 ===================================
7098 23:44:27.208371 DLL_ASYNC_EN = 0
7099 23:44:27.211851 ALL_SLAVE_EN = 0
7100 23:44:27.215209 NEW_RANK_MODE = 1
7101 23:44:27.215292 DLL_IDLE_MODE = 1
7102 23:44:27.218345 LP45_APHY_COMB_EN = 1
7103 23:44:27.221637 TX_ODT_DIS = 0
7104 23:44:27.225433 NEW_8X_MODE = 1
7105 23:44:27.228443 ===================================
7106 23:44:27.232367 ===================================
7107 23:44:27.232449 data_rate = 3200
7108 23:44:27.235309 CKR = 1
7109 23:44:27.238632 DQ_P2S_RATIO = 8
7110 23:44:27.242190 ===================================
7111 23:44:27.244891 CA_P2S_RATIO = 8
7112 23:44:27.248240 DQ_CA_OPEN = 0
7113 23:44:27.251780 DQ_SEMI_OPEN = 0
7114 23:44:27.251888 CA_SEMI_OPEN = 0
7115 23:44:27.254922 CA_FULL_RATE = 0
7116 23:44:27.258269 DQ_CKDIV4_EN = 0
7117 23:44:27.261768 CA_CKDIV4_EN = 0
7118 23:44:27.265337 CA_PREDIV_EN = 0
7119 23:44:27.268373 PH8_DLY = 12
7120 23:44:27.268455 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7121 23:44:27.271492 DQ_AAMCK_DIV = 4
7122 23:44:27.275143 CA_AAMCK_DIV = 4
7123 23:44:27.278409 CA_ADMCK_DIV = 4
7124 23:44:27.282116 DQ_TRACK_CA_EN = 0
7125 23:44:27.285412 CA_PICK = 1600
7126 23:44:27.288397 CA_MCKIO = 1600
7127 23:44:27.288478 MCKIO_SEMI = 0
7128 23:44:27.291511 PLL_FREQ = 3068
7129 23:44:27.295333 DQ_UI_PI_RATIO = 32
7130 23:44:27.298415 CA_UI_PI_RATIO = 0
7131 23:44:27.301871 ===================================
7132 23:44:27.304938 ===================================
7133 23:44:27.308784 memory_type:LPDDR4
7134 23:44:27.308865 GP_NUM : 10
7135 23:44:27.311871 SRAM_EN : 1
7136 23:44:27.311951 MD32_EN : 0
7137 23:44:27.315192 ===================================
7138 23:44:27.318314 [ANA_INIT] >>>>>>>>>>>>>>
7139 23:44:27.322270 <<<<<< [CONFIGURE PHASE]: ANA_TX
7140 23:44:27.325006 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7141 23:44:27.329083 ===================================
7142 23:44:27.331983 data_rate = 3200,PCW = 0X7600
7143 23:44:27.335010 ===================================
7144 23:44:27.338768 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7145 23:44:27.345648 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7146 23:44:27.348732 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7147 23:44:27.355543 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7148 23:44:27.358372 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7149 23:44:27.362082 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7150 23:44:27.362166 [ANA_INIT] flow start
7151 23:44:27.364868 [ANA_INIT] PLL >>>>>>>>
7152 23:44:27.368451 [ANA_INIT] PLL <<<<<<<<
7153 23:44:27.368588 [ANA_INIT] MIDPI >>>>>>>>
7154 23:44:27.371904 [ANA_INIT] MIDPI <<<<<<<<
7155 23:44:27.375337 [ANA_INIT] DLL >>>>>>>>
7156 23:44:27.375418 [ANA_INIT] DLL <<<<<<<<
7157 23:44:27.378723 [ANA_INIT] flow end
7158 23:44:27.381548 ============ LP4 DIFF to SE enter ============
7159 23:44:27.386089 ============ LP4 DIFF to SE exit ============
7160 23:44:27.388582 [ANA_INIT] <<<<<<<<<<<<<
7161 23:44:27.391837 [Flow] Enable top DCM control >>>>>
7162 23:44:27.395173 [Flow] Enable top DCM control <<<<<
7163 23:44:27.398727 Enable DLL master slave shuffle
7164 23:44:27.405056 ==============================================================
7165 23:44:27.405138 Gating Mode config
7166 23:44:27.411644 ==============================================================
7167 23:44:27.411728 Config description:
7168 23:44:27.422307 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7169 23:44:27.428513 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7170 23:44:27.435607 SELPH_MODE 0: By rank 1: By Phase
7171 23:44:27.438761 ==============================================================
7172 23:44:27.441732 GAT_TRACK_EN = 1
7173 23:44:27.445859 RX_GATING_MODE = 2
7174 23:44:27.448959 RX_GATING_TRACK_MODE = 2
7175 23:44:27.452669 SELPH_MODE = 1
7176 23:44:27.455349 PICG_EARLY_EN = 1
7177 23:44:27.458694 VALID_LAT_VALUE = 1
7178 23:44:27.462105 ==============================================================
7179 23:44:27.465532 Enter into Gating configuration >>>>
7180 23:44:27.468839 Exit from Gating configuration <<<<
7181 23:44:27.471901 Enter into DVFS_PRE_config >>>>>
7182 23:44:27.485834 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7183 23:44:27.488962 Exit from DVFS_PRE_config <<<<<
7184 23:44:27.492370 Enter into PICG configuration >>>>
7185 23:44:27.492476 Exit from PICG configuration <<<<
7186 23:44:27.495291 [RX_INPUT] configuration >>>>>
7187 23:44:27.498825 [RX_INPUT] configuration <<<<<
7188 23:44:27.505142 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7189 23:44:27.508403 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7190 23:44:27.515110 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7191 23:44:27.521912 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7192 23:44:27.528767 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7193 23:44:27.535096 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7194 23:44:27.538860 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7195 23:44:27.541994 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7196 23:44:27.545269 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7197 23:44:27.551937 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7198 23:44:27.555060 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7199 23:44:27.558475 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7200 23:44:27.562475 ===================================
7201 23:44:27.565288 LPDDR4 DRAM CONFIGURATION
7202 23:44:27.569076 ===================================
7203 23:44:27.569158 EX_ROW_EN[0] = 0x0
7204 23:44:27.572293 EX_ROW_EN[1] = 0x0
7205 23:44:27.575539 LP4Y_EN = 0x0
7206 23:44:27.575619 WORK_FSP = 0x1
7207 23:44:27.578646 WL = 0x5
7208 23:44:27.578727 RL = 0x5
7209 23:44:27.581976 BL = 0x2
7210 23:44:27.582057 RPST = 0x0
7211 23:44:27.585376 RD_PRE = 0x0
7212 23:44:27.585457 WR_PRE = 0x1
7213 23:44:27.588443 WR_PST = 0x1
7214 23:44:27.588541 DBI_WR = 0x0
7215 23:44:27.591993 DBI_RD = 0x0
7216 23:44:27.592075 OTF = 0x1
7217 23:44:27.595416 ===================================
7218 23:44:27.598519 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7219 23:44:27.605180 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7220 23:44:27.608585 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7221 23:44:27.612141 ===================================
7222 23:44:27.615275 LPDDR4 DRAM CONFIGURATION
7223 23:44:27.619051 ===================================
7224 23:44:27.619131 EX_ROW_EN[0] = 0x10
7225 23:44:27.621899 EX_ROW_EN[1] = 0x0
7226 23:44:27.621997 LP4Y_EN = 0x0
7227 23:44:27.625696 WORK_FSP = 0x1
7228 23:44:27.625788 WL = 0x5
7229 23:44:27.628708 RL = 0x5
7230 23:44:27.632174 BL = 0x2
7231 23:44:27.632245 RPST = 0x0
7232 23:44:27.635718 RD_PRE = 0x0
7233 23:44:27.635813 WR_PRE = 0x1
7234 23:44:27.638897 WR_PST = 0x1
7235 23:44:27.638971 DBI_WR = 0x0
7236 23:44:27.641878 DBI_RD = 0x0
7237 23:44:27.641951 OTF = 0x1
7238 23:44:27.645482 ===================================
7239 23:44:27.652074 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7240 23:44:27.652179 ==
7241 23:44:27.655168 Dram Type= 6, Freq= 0, CH_0, rank 0
7242 23:44:27.658704 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7243 23:44:27.658791 ==
7244 23:44:27.661837 [Duty_Offset_Calibration]
7245 23:44:27.665448 B0:2 B1:-1 CA:1
7246 23:44:27.665530
7247 23:44:27.668636 [DutyScan_Calibration_Flow] k_type=0
7248 23:44:27.675939
7249 23:44:27.676025 ==CLK 0==
7250 23:44:27.679317 Final CLK duty delay cell = -4
7251 23:44:27.682634 [-4] MAX Duty = 5031%(X100), DQS PI = 22
7252 23:44:27.686003 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7253 23:44:27.689665 [-4] AVG Duty = 4937%(X100)
7254 23:44:27.689750
7255 23:44:27.692746 CH0 CLK Duty spec in!! Max-Min= 187%
7256 23:44:27.695892 [DutyScan_Calibration_Flow] ====Done====
7257 23:44:27.695976
7258 23:44:27.699480 [DutyScan_Calibration_Flow] k_type=1
7259 23:44:27.715713
7260 23:44:27.715866 ==DQS 0 ==
7261 23:44:27.719119 Final DQS duty delay cell = 0
7262 23:44:27.722503 [0] MAX Duty = 5125%(X100), DQS PI = 20
7263 23:44:27.725864 [0] MIN Duty = 5000%(X100), DQS PI = 14
7264 23:44:27.725962 [0] AVG Duty = 5062%(X100)
7265 23:44:27.729104
7266 23:44:27.729185 ==DQS 1 ==
7267 23:44:27.732387 Final DQS duty delay cell = -4
7268 23:44:27.735718 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7269 23:44:27.739057 [-4] MIN Duty = 5031%(X100), DQS PI = 6
7270 23:44:27.742173 [-4] AVG Duty = 5062%(X100)
7271 23:44:27.742257
7272 23:44:27.745751 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7273 23:44:27.745833
7274 23:44:27.748907 CH0 DQS 1 Duty spec in!! Max-Min= 62%
7275 23:44:27.751940 [DutyScan_Calibration_Flow] ====Done====
7276 23:44:27.752022
7277 23:44:27.755799 [DutyScan_Calibration_Flow] k_type=3
7278 23:44:27.773299
7279 23:44:27.773427 ==DQM 0 ==
7280 23:44:27.776351 Final DQM duty delay cell = 0
7281 23:44:27.779901 [0] MAX Duty = 5000%(X100), DQS PI = 20
7282 23:44:27.782784 [0] MIN Duty = 4875%(X100), DQS PI = 4
7283 23:44:27.782901 [0] AVG Duty = 4937%(X100)
7284 23:44:27.786276
7285 23:44:27.786369 ==DQM 1 ==
7286 23:44:27.790075 Final DQM duty delay cell = 0
7287 23:44:27.792839 [0] MAX Duty = 5218%(X100), DQS PI = 58
7288 23:44:27.796531 [0] MIN Duty = 4969%(X100), DQS PI = 18
7289 23:44:27.796636 [0] AVG Duty = 5093%(X100)
7290 23:44:27.799509
7291 23:44:27.803022 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7292 23:44:27.803130
7293 23:44:27.806585 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7294 23:44:27.809496 [DutyScan_Calibration_Flow] ====Done====
7295 23:44:27.809584
7296 23:44:27.812920 [DutyScan_Calibration_Flow] k_type=2
7297 23:44:27.829927
7298 23:44:27.830080 ==DQ 0 ==
7299 23:44:27.833633 Final DQ duty delay cell = 0
7300 23:44:27.836895 [0] MAX Duty = 5156%(X100), DQS PI = 0
7301 23:44:27.840335 [0] MIN Duty = 5031%(X100), DQS PI = 4
7302 23:44:27.840435 [0] AVG Duty = 5093%(X100)
7303 23:44:27.840499
7304 23:44:27.843458 ==DQ 1 ==
7305 23:44:27.846911 Final DQ duty delay cell = 0
7306 23:44:27.850077 [0] MAX Duty = 5000%(X100), DQS PI = 0
7307 23:44:27.853475 [0] MIN Duty = 4907%(X100), DQS PI = 18
7308 23:44:27.853588 [0] AVG Duty = 4953%(X100)
7309 23:44:27.853667
7310 23:44:27.856895 CH0 DQ 0 Duty spec in!! Max-Min= 125%
7311 23:44:27.857031
7312 23:44:27.859899 CH0 DQ 1 Duty spec in!! Max-Min= 93%
7313 23:44:27.867190 [DutyScan_Calibration_Flow] ====Done====
7314 23:44:27.867335 ==
7315 23:44:27.870693 Dram Type= 6, Freq= 0, CH_1, rank 0
7316 23:44:27.873874 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7317 23:44:27.873998 ==
7318 23:44:27.877124 [Duty_Offset_Calibration]
7319 23:44:27.877232 B0:1 B1:1 CA:2
7320 23:44:27.877297
7321 23:44:27.880914 [DutyScan_Calibration_Flow] k_type=0
7322 23:44:27.890337
7323 23:44:27.890465 ==CLK 0==
7324 23:44:27.893437 Final CLK duty delay cell = 0
7325 23:44:27.896833 [0] MAX Duty = 5156%(X100), DQS PI = 24
7326 23:44:27.900342 [0] MIN Duty = 4938%(X100), DQS PI = 48
7327 23:44:27.900444 [0] AVG Duty = 5047%(X100)
7328 23:44:27.903324
7329 23:44:27.903419 CH1 CLK Duty spec in!! Max-Min= 218%
7330 23:44:27.910211 [DutyScan_Calibration_Flow] ====Done====
7331 23:44:27.910354
7332 23:44:27.913312 [DutyScan_Calibration_Flow] k_type=1
7333 23:44:27.929571
7334 23:44:27.929726 ==DQS 0 ==
7335 23:44:27.932930 Final DQS duty delay cell = 0
7336 23:44:27.936499 [0] MAX Duty = 5062%(X100), DQS PI = 22
7337 23:44:27.939889 [0] MIN Duty = 4813%(X100), DQS PI = 52
7338 23:44:27.940029 [0] AVG Duty = 4937%(X100)
7339 23:44:27.943119
7340 23:44:27.943252 ==DQS 1 ==
7341 23:44:27.946633 Final DQS duty delay cell = 0
7342 23:44:27.949940 [0] MAX Duty = 5031%(X100), DQS PI = 34
7343 23:44:27.953324 [0] MIN Duty = 4938%(X100), DQS PI = 14
7344 23:44:27.953457 [0] AVG Duty = 4984%(X100)
7345 23:44:27.956285
7346 23:44:27.959888 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7347 23:44:27.960020
7348 23:44:27.963159 CH1 DQS 1 Duty spec in!! Max-Min= 93%
7349 23:44:27.966319 [DutyScan_Calibration_Flow] ====Done====
7350 23:44:27.966450
7351 23:44:27.969889 [DutyScan_Calibration_Flow] k_type=3
7352 23:44:27.986381
7353 23:44:27.986579 ==DQM 0 ==
7354 23:44:27.989699 Final DQM duty delay cell = 0
7355 23:44:27.993159 [0] MAX Duty = 5156%(X100), DQS PI = 20
7356 23:44:27.996365 [0] MIN Duty = 4844%(X100), DQS PI = 50
7357 23:44:28.000261 [0] AVG Duty = 5000%(X100)
7358 23:44:28.000401
7359 23:44:28.000519 ==DQM 1 ==
7360 23:44:28.003481 Final DQM duty delay cell = 0
7361 23:44:28.006512 [0] MAX Duty = 5156%(X100), DQS PI = 60
7362 23:44:28.009679 [0] MIN Duty = 4875%(X100), DQS PI = 20
7363 23:44:28.013188 [0] AVG Duty = 5015%(X100)
7364 23:44:28.013330
7365 23:44:28.016787 CH1 DQM 0 Duty spec in!! Max-Min= 312%
7366 23:44:28.016923
7367 23:44:28.019783 CH1 DQM 1 Duty spec in!! Max-Min= 281%
7368 23:44:28.023663 [DutyScan_Calibration_Flow] ====Done====
7369 23:44:28.023809
7370 23:44:28.026506 [DutyScan_Calibration_Flow] k_type=2
7371 23:44:28.043644
7372 23:44:28.043861 ==DQ 0 ==
7373 23:44:28.046703 Final DQ duty delay cell = 0
7374 23:44:28.050311 [0] MAX Duty = 5156%(X100), DQS PI = 20
7375 23:44:28.053603 [0] MIN Duty = 4907%(X100), DQS PI = 52
7376 23:44:28.053750 [0] AVG Duty = 5031%(X100)
7377 23:44:28.056530
7378 23:44:28.056673 ==DQ 1 ==
7379 23:44:28.060174 Final DQ duty delay cell = 0
7380 23:44:28.063319 [0] MAX Duty = 5093%(X100), DQS PI = 6
7381 23:44:28.067020 [0] MIN Duty = 5031%(X100), DQS PI = 0
7382 23:44:28.067168 [0] AVG Duty = 5062%(X100)
7383 23:44:28.067291
7384 23:44:28.070110 CH1 DQ 0 Duty spec in!! Max-Min= 249%
7385 23:44:28.070253
7386 23:44:28.073520 CH1 DQ 1 Duty spec in!! Max-Min= 62%
7387 23:44:28.080287 [DutyScan_Calibration_Flow] ====Done====
7388 23:44:28.083813 nWR fixed to 30
7389 23:44:28.083977 [ModeRegInit_LP4] CH0 RK0
7390 23:44:28.087235 [ModeRegInit_LP4] CH0 RK1
7391 23:44:28.090011 [ModeRegInit_LP4] CH1 RK0
7392 23:44:28.090167 [ModeRegInit_LP4] CH1 RK1
7393 23:44:28.093685 match AC timing 5
7394 23:44:28.096948 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7395 23:44:28.100500 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7396 23:44:28.106898 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7397 23:44:28.110175 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7398 23:44:28.116806 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7399 23:44:28.116985 [MiockJmeterHQA]
7400 23:44:28.117145
7401 23:44:28.120467 [DramcMiockJmeter] u1RxGatingPI = 0
7402 23:44:28.123799 0 : 4253, 4027
7403 23:44:28.123944 4 : 4368, 4140
7404 23:44:28.124075 8 : 4258, 4029
7405 23:44:28.127156 12 : 4252, 4027
7406 23:44:28.127294 16 : 4363, 4138
7407 23:44:28.130190 20 : 4253, 4026
7408 23:44:28.130329 24 : 4255, 4030
7409 23:44:28.133378 28 : 4252, 4027
7410 23:44:28.133517 32 : 4363, 4137
7411 23:44:28.133649 36 : 4363, 4137
7412 23:44:28.136948 40 : 4253, 4026
7413 23:44:28.137131 44 : 4253, 4027
7414 23:44:28.140062 48 : 4253, 4026
7415 23:44:28.140204 52 : 4253, 4026
7416 23:44:28.143253 56 : 4254, 4029
7417 23:44:28.143392 60 : 4363, 4137
7418 23:44:28.143525 64 : 4252, 4027
7419 23:44:28.147253 68 : 4250, 4026
7420 23:44:28.147394 72 : 4250, 4026
7421 23:44:28.150224 76 : 4252, 4030
7422 23:44:28.150368 80 : 4250, 4026
7423 23:44:28.153757 84 : 4361, 4137
7424 23:44:28.153894 88 : 4361, 4138
7425 23:44:28.157020 92 : 4250, 4026
7426 23:44:28.157162 96 : 4250, 3550
7427 23:44:28.157283 100 : 4250, 0
7428 23:44:28.160049 104 : 4253, 0
7429 23:44:28.160187 108 : 4250, 0
7430 23:44:28.163543 112 : 4249, 0
7431 23:44:28.163695 116 : 4252, 0
7432 23:44:28.163824 120 : 4361, 0
7433 23:44:28.166616 124 : 4360, 0
7434 23:44:28.166760 128 : 4363, 0
7435 23:44:28.166888 132 : 4250, 0
7436 23:44:28.170234 136 : 4250, 0
7437 23:44:28.170381 140 : 4250, 0
7438 23:44:28.173340 144 : 4252, 0
7439 23:44:28.173450 148 : 4250, 0
7440 23:44:28.173553 152 : 4250, 0
7441 23:44:28.176775 156 : 4252, 0
7442 23:44:28.176866 160 : 4250, 0
7443 23:44:28.179992 164 : 4249, 0
7444 23:44:28.180074 168 : 4252, 0
7445 23:44:28.180138 172 : 4250, 0
7446 23:44:28.183468 176 : 4360, 0
7447 23:44:28.183558 180 : 4361, 0
7448 23:44:28.186887 184 : 4250, 0
7449 23:44:28.186973 188 : 4250, 0
7450 23:44:28.187039 192 : 4363, 0
7451 23:44:28.190366 196 : 4250, 0
7452 23:44:28.190482 200 : 4250, 0
7453 23:44:28.190564 204 : 4250, 0
7454 23:44:28.193823 208 : 4253, 0
7455 23:44:28.193908 212 : 4250, 52
7456 23:44:28.196995 216 : 4250, 3423
7457 23:44:28.197094 220 : 4360, 4137
7458 23:44:28.200419 224 : 4250, 4026
7459 23:44:28.200503 228 : 4250, 4027
7460 23:44:28.203837 232 : 4363, 4140
7461 23:44:28.203955 236 : 4250, 4027
7462 23:44:28.207080 240 : 4250, 4027
7463 23:44:28.207166 244 : 4250, 4027
7464 23:44:28.207231 248 : 4252, 4030
7465 23:44:28.210036 252 : 4250, 4027
7466 23:44:28.210141 256 : 4250, 4026
7467 23:44:28.213681 260 : 4361, 4137
7468 23:44:28.213765 264 : 4250, 4027
7469 23:44:28.217012 268 : 4250, 4027
7470 23:44:28.217095 272 : 4360, 4137
7471 23:44:28.220154 276 : 4250, 4026
7472 23:44:28.220237 280 : 4250, 4027
7473 23:44:28.223450 284 : 4363, 4140
7474 23:44:28.223548 288 : 4250, 4027
7475 23:44:28.226812 292 : 4250, 4026
7476 23:44:28.226896 296 : 4252, 4027
7477 23:44:28.230050 300 : 4252, 4029
7478 23:44:28.230134 304 : 4250, 4027
7479 23:44:28.230198 308 : 4250, 4026
7480 23:44:28.233589 312 : 4361, 4137
7481 23:44:28.233672 316 : 4250, 4027
7482 23:44:28.236817 320 : 4250, 4027
7483 23:44:28.236900 324 : 4360, 4137
7484 23:44:28.240240 328 : 4250, 4026
7485 23:44:28.240323 332 : 4250, 3142
7486 23:44:28.243558 336 : 4363, 270
7487 23:44:28.243641
7488 23:44:28.243705 MIOCK jitter meter ch=0
7489 23:44:28.243764
7490 23:44:28.246777 1T = (336-100) = 236 dly cells
7491 23:44:28.253469 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7492 23:44:28.253564 ==
7493 23:44:28.257032 Dram Type= 6, Freq= 0, CH_0, rank 0
7494 23:44:28.260125 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7495 23:44:28.260211 ==
7496 23:44:28.266863 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7497 23:44:28.270498 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7498 23:44:28.273815 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7499 23:44:28.280429 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7500 23:44:28.289667 [CA 0] Center 44 (14~75) winsize 62
7501 23:44:28.293481 [CA 1] Center 43 (13~74) winsize 62
7502 23:44:28.296847 [CA 2] Center 39 (10~68) winsize 59
7503 23:44:28.299869 [CA 3] Center 39 (10~68) winsize 59
7504 23:44:28.303106 [CA 4] Center 37 (7~67) winsize 61
7505 23:44:28.306462 [CA 5] Center 37 (7~67) winsize 61
7506 23:44:28.306590
7507 23:44:28.309757 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7508 23:44:28.309889
7509 23:44:28.313078 [CATrainingPosCal] consider 1 rank data
7510 23:44:28.316463 u2DelayCellTimex100 = 275/100 ps
7511 23:44:28.319719 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7512 23:44:28.326617 CA1 delay=43 (13~74),Diff = 6 PI (21 cell)
7513 23:44:28.329738 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7514 23:44:28.332913 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7515 23:44:28.336532 CA4 delay=37 (7~67),Diff = 0 PI (0 cell)
7516 23:44:28.339779 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7517 23:44:28.339910
7518 23:44:28.342989 CA PerBit enable=1, Macro0, CA PI delay=37
7519 23:44:28.343116
7520 23:44:28.346661 [CBTSetCACLKResult] CA Dly = 37
7521 23:44:28.349794 CS Dly: 11 (0~42)
7522 23:44:28.353594 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7523 23:44:28.356421 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7524 23:44:28.356502 ==
7525 23:44:28.359903 Dram Type= 6, Freq= 0, CH_0, rank 1
7526 23:44:28.363133 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7527 23:44:28.366470 ==
7528 23:44:28.369780 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7529 23:44:28.372969 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7530 23:44:28.379747 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7531 23:44:28.383684 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7532 23:44:28.393942 [CA 0] Center 44 (14~75) winsize 62
7533 23:44:28.396916 [CA 1] Center 44 (14~75) winsize 62
7534 23:44:28.400506 [CA 2] Center 40 (11~69) winsize 59
7535 23:44:28.404310 [CA 3] Center 39 (10~69) winsize 60
7536 23:44:28.407013 [CA 4] Center 38 (9~67) winsize 59
7537 23:44:28.410526 [CA 5] Center 37 (7~67) winsize 61
7538 23:44:28.410609
7539 23:44:28.413964 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7540 23:44:28.414045
7541 23:44:28.417192 [CATrainingPosCal] consider 2 rank data
7542 23:44:28.420725 u2DelayCellTimex100 = 275/100 ps
7543 23:44:28.424119 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7544 23:44:28.430546 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7545 23:44:28.434127 CA2 delay=39 (11~68),Diff = 2 PI (7 cell)
7546 23:44:28.437279 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7547 23:44:28.440917 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
7548 23:44:28.443723 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7549 23:44:28.443804
7550 23:44:28.447260 CA PerBit enable=1, Macro0, CA PI delay=37
7551 23:44:28.447341
7552 23:44:28.450702 [CBTSetCACLKResult] CA Dly = 37
7553 23:44:28.454443 CS Dly: 12 (0~44)
7554 23:44:28.458155 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7555 23:44:28.460980 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7556 23:44:28.461074
7557 23:44:28.464363 ----->DramcWriteLeveling(PI) begin...
7558 23:44:28.464447 ==
7559 23:44:28.467815 Dram Type= 6, Freq= 0, CH_0, rank 0
7560 23:44:28.471065 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7561 23:44:28.471146 ==
7562 23:44:28.474406 Write leveling (Byte 0): 32 => 32
7563 23:44:28.477314 Write leveling (Byte 1): 27 => 27
7564 23:44:28.481147 DramcWriteLeveling(PI) end<-----
7565 23:44:28.481266
7566 23:44:28.481329 ==
7567 23:44:28.484489 Dram Type= 6, Freq= 0, CH_0, rank 0
7568 23:44:28.487374 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7569 23:44:28.491300 ==
7570 23:44:28.491382 [Gating] SW mode calibration
7571 23:44:28.500760 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7572 23:44:28.504440 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7573 23:44:28.507574 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7574 23:44:28.514486 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7575 23:44:28.517672 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7576 23:44:28.521112 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7577 23:44:28.527481 1 4 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7578 23:44:28.531160 1 4 20 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
7579 23:44:28.534652 1 4 24 | B1->B0 | 3433 3434 | 1 1 | (0 0) (1 1)
7580 23:44:28.540808 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7581 23:44:28.544200 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7582 23:44:28.547893 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7583 23:44:28.550896 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7584 23:44:28.558002 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7585 23:44:28.561499 1 5 16 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
7586 23:44:28.564907 1 5 20 | B1->B0 | 3434 2626 | 1 0 | (1 0) (1 0)
7587 23:44:28.570902 1 5 24 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
7588 23:44:28.574425 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7589 23:44:28.577826 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7590 23:44:28.584707 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7591 23:44:28.587829 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7592 23:44:28.591175 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7593 23:44:28.597543 1 6 16 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
7594 23:44:28.600866 1 6 20 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
7595 23:44:28.604260 1 6 24 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
7596 23:44:28.611135 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7597 23:44:28.614376 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7598 23:44:28.618006 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7599 23:44:28.624380 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7600 23:44:28.628239 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7601 23:44:28.631336 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7602 23:44:28.634629 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7603 23:44:28.641205 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7604 23:44:28.644748 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7605 23:44:28.647827 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7606 23:44:28.654278 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7607 23:44:28.657611 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7608 23:44:28.661380 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7609 23:44:28.668196 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7610 23:44:28.671284 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7611 23:44:28.674799 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7612 23:44:28.681390 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7613 23:44:28.684854 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7614 23:44:28.688274 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7615 23:44:28.694333 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7616 23:44:28.697674 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7617 23:44:28.701078 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7618 23:44:28.707991 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7619 23:44:28.708076 Total UI for P1: 0, mck2ui 16
7620 23:44:28.714696 best dqsien dly found for B0: ( 1, 9, 14)
7621 23:44:28.717710 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7622 23:44:28.721612 Total UI for P1: 0, mck2ui 16
7623 23:44:28.724803 best dqsien dly found for B1: ( 1, 9, 20)
7624 23:44:28.728334 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7625 23:44:28.731041 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7626 23:44:28.731127
7627 23:44:28.734263 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7628 23:44:28.738105 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7629 23:44:28.741567 [Gating] SW calibration Done
7630 23:44:28.741648 ==
7631 23:44:28.744708 Dram Type= 6, Freq= 0, CH_0, rank 0
7632 23:44:28.748094 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7633 23:44:28.748175 ==
7634 23:44:28.751449 RX Vref Scan: 0
7635 23:44:28.751530
7636 23:44:28.754832 RX Vref 0 -> 0, step: 1
7637 23:44:28.754912
7638 23:44:28.754975 RX Delay 0 -> 252, step: 8
7639 23:44:28.760833 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7640 23:44:28.764198 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7641 23:44:28.767899 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7642 23:44:28.770830 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7643 23:44:28.774287 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7644 23:44:28.780985 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7645 23:44:28.784360 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7646 23:44:28.788108 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7647 23:44:28.791225 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7648 23:44:28.794325 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7649 23:44:28.801244 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7650 23:44:28.804496 iDelay=200, Bit 11, Center 119 (72 ~ 167) 96
7651 23:44:28.807957 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7652 23:44:28.811215 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7653 23:44:28.814490 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7654 23:44:28.820830 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7655 23:44:28.820913 ==
7656 23:44:28.824090 Dram Type= 6, Freq= 0, CH_0, rank 0
7657 23:44:28.827970 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7658 23:44:28.828052 ==
7659 23:44:28.828117 DQS Delay:
7660 23:44:28.831303 DQS0 = 0, DQS1 = 0
7661 23:44:28.831384 DQM Delay:
7662 23:44:28.834476 DQM0 = 132, DQM1 = 124
7663 23:44:28.834557 DQ Delay:
7664 23:44:28.837618 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7665 23:44:28.841135 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7666 23:44:28.844290 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =119
7667 23:44:28.847560 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7668 23:44:28.847748
7669 23:44:28.847843
7670 23:44:28.851192 ==
7671 23:44:28.854229 Dram Type= 6, Freq= 0, CH_0, rank 0
7672 23:44:28.857455 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7673 23:44:28.857554 ==
7674 23:44:28.857618
7675 23:44:28.857677
7676 23:44:28.861379 TX Vref Scan disable
7677 23:44:28.861458 == TX Byte 0 ==
7678 23:44:28.864157 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7679 23:44:28.871139 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7680 23:44:28.871223 == TX Byte 1 ==
7681 23:44:28.874091 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7682 23:44:28.881450 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7683 23:44:28.881531 ==
7684 23:44:28.884265 Dram Type= 6, Freq= 0, CH_0, rank 0
7685 23:44:28.887592 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7686 23:44:28.887674 ==
7687 23:44:28.901593
7688 23:44:28.904850 TX Vref early break, caculate TX vref
7689 23:44:28.907803 TX Vref=16, minBit 7, minWin=21, winSum=358
7690 23:44:28.911212 TX Vref=18, minBit 0, minWin=22, winSum=370
7691 23:44:28.914374 TX Vref=20, minBit 4, minWin=23, winSum=381
7692 23:44:28.917700 TX Vref=22, minBit 4, minWin=23, winSum=390
7693 23:44:28.921501 TX Vref=24, minBit 1, minWin=24, winSum=399
7694 23:44:28.928041 TX Vref=26, minBit 3, minWin=25, winSum=412
7695 23:44:28.931528 TX Vref=28, minBit 0, minWin=25, winSum=419
7696 23:44:28.934732 TX Vref=30, minBit 3, minWin=25, winSum=414
7697 23:44:28.937863 TX Vref=32, minBit 4, minWin=24, winSum=411
7698 23:44:28.941164 TX Vref=34, minBit 0, minWin=24, winSum=394
7699 23:44:28.947764 [TxChooseVref] Worse bit 0, Min win 25, Win sum 419, Final Vref 28
7700 23:44:28.947847
7701 23:44:28.951064 Final TX Range 0 Vref 28
7702 23:44:28.951147
7703 23:44:28.951209 ==
7704 23:44:28.954680 Dram Type= 6, Freq= 0, CH_0, rank 0
7705 23:44:28.957943 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7706 23:44:28.958026 ==
7707 23:44:28.958089
7708 23:44:28.958147
7709 23:44:28.961311 TX Vref Scan disable
7710 23:44:28.968220 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7711 23:44:28.968304 == TX Byte 0 ==
7712 23:44:28.971227 u2DelayCellOfst[0]=17 cells (5 PI)
7713 23:44:28.974584 u2DelayCellOfst[1]=21 cells (6 PI)
7714 23:44:28.978080 u2DelayCellOfst[2]=14 cells (4 PI)
7715 23:44:28.981287 u2DelayCellOfst[3]=17 cells (5 PI)
7716 23:44:28.984769 u2DelayCellOfst[4]=10 cells (3 PI)
7717 23:44:28.987679 u2DelayCellOfst[5]=0 cells (0 PI)
7718 23:44:28.991283 u2DelayCellOfst[6]=21 cells (6 PI)
7719 23:44:28.991364 u2DelayCellOfst[7]=21 cells (6 PI)
7720 23:44:28.997633 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7721 23:44:29.000866 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7722 23:44:29.000966 == TX Byte 1 ==
7723 23:44:29.004347 u2DelayCellOfst[8]=0 cells (0 PI)
7724 23:44:29.007998 u2DelayCellOfst[9]=0 cells (0 PI)
7725 23:44:29.011221 u2DelayCellOfst[10]=7 cells (2 PI)
7726 23:44:29.014274 u2DelayCellOfst[11]=0 cells (0 PI)
7727 23:44:29.017746 u2DelayCellOfst[12]=10 cells (3 PI)
7728 23:44:29.021042 u2DelayCellOfst[13]=10 cells (3 PI)
7729 23:44:29.024572 u2DelayCellOfst[14]=17 cells (5 PI)
7730 23:44:29.028047 u2DelayCellOfst[15]=10 cells (3 PI)
7731 23:44:29.031045 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7732 23:44:29.037678 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7733 23:44:29.037760 DramC Write-DBI on
7734 23:44:29.037824 ==
7735 23:44:29.041016 Dram Type= 6, Freq= 0, CH_0, rank 0
7736 23:44:29.044454 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7737 23:44:29.044535 ==
7738 23:44:29.044598
7739 23:44:29.044657
7740 23:44:29.047728 TX Vref Scan disable
7741 23:44:29.051040 == TX Byte 0 ==
7742 23:44:29.054630 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
7743 23:44:29.058245 == TX Byte 1 ==
7744 23:44:29.061290 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7745 23:44:29.061373 DramC Write-DBI off
7746 23:44:29.061436
7747 23:44:29.064855 [DATLAT]
7748 23:44:29.064935 Freq=1600, CH0 RK0
7749 23:44:29.065040
7750 23:44:29.068538 DATLAT Default: 0xf
7751 23:44:29.068619 0, 0xFFFF, sum = 0
7752 23:44:29.071875 1, 0xFFFF, sum = 0
7753 23:44:29.071958 2, 0xFFFF, sum = 0
7754 23:44:29.074741 3, 0xFFFF, sum = 0
7755 23:44:29.074823 4, 0xFFFF, sum = 0
7756 23:44:29.078421 5, 0xFFFF, sum = 0
7757 23:44:29.078503 6, 0xFFFF, sum = 0
7758 23:44:29.082181 7, 0xFFFF, sum = 0
7759 23:44:29.082263 8, 0xFFFF, sum = 0
7760 23:44:29.085149 9, 0xFFFF, sum = 0
7761 23:44:29.085230 10, 0xFFFF, sum = 0
7762 23:44:29.088096 11, 0xFFFF, sum = 0
7763 23:44:29.091871 12, 0xFFFF, sum = 0
7764 23:44:29.091953 13, 0xFFFF, sum = 0
7765 23:44:29.095021 14, 0x0, sum = 1
7766 23:44:29.095102 15, 0x0, sum = 2
7767 23:44:29.095165 16, 0x0, sum = 3
7768 23:44:29.098160 17, 0x0, sum = 4
7769 23:44:29.098241 best_step = 15
7770 23:44:29.098304
7771 23:44:29.101569 ==
7772 23:44:29.101649 Dram Type= 6, Freq= 0, CH_0, rank 0
7773 23:44:29.108159 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7774 23:44:29.108243 ==
7775 23:44:29.108307 RX Vref Scan: 1
7776 23:44:29.108366
7777 23:44:29.112140 Set Vref Range= 24 -> 127
7778 23:44:29.112223
7779 23:44:29.114992 RX Vref 24 -> 127, step: 1
7780 23:44:29.115074
7781 23:44:29.118169 RX Delay 11 -> 252, step: 4
7782 23:44:29.118251
7783 23:44:29.121344 Set Vref, RX VrefLevel [Byte0]: 24
7784 23:44:29.124790 [Byte1]: 24
7785 23:44:29.124871
7786 23:44:29.127710 Set Vref, RX VrefLevel [Byte0]: 25
7787 23:44:29.131141 [Byte1]: 25
7788 23:44:29.131224
7789 23:44:29.134519 Set Vref, RX VrefLevel [Byte0]: 26
7790 23:44:29.138227 [Byte1]: 26
7791 23:44:29.141393
7792 23:44:29.141474 Set Vref, RX VrefLevel [Byte0]: 27
7793 23:44:29.144629 [Byte1]: 27
7794 23:44:29.148825
7795 23:44:29.148906 Set Vref, RX VrefLevel [Byte0]: 28
7796 23:44:29.152083 [Byte1]: 28
7797 23:44:29.156558
7798 23:44:29.156639 Set Vref, RX VrefLevel [Byte0]: 29
7799 23:44:29.159711 [Byte1]: 29
7800 23:44:29.163916
7801 23:44:29.164000 Set Vref, RX VrefLevel [Byte0]: 30
7802 23:44:29.167779 [Byte1]: 30
7803 23:44:29.171908
7804 23:44:29.171988 Set Vref, RX VrefLevel [Byte0]: 31
7805 23:44:29.175077 [Byte1]: 31
7806 23:44:29.179674
7807 23:44:29.179754 Set Vref, RX VrefLevel [Byte0]: 32
7808 23:44:29.183400 [Byte1]: 32
7809 23:44:29.187146
7810 23:44:29.187226 Set Vref, RX VrefLevel [Byte0]: 33
7811 23:44:29.190300 [Byte1]: 33
7812 23:44:29.194704
7813 23:44:29.194783 Set Vref, RX VrefLevel [Byte0]: 34
7814 23:44:29.197678 [Byte1]: 34
7815 23:44:29.202149
7816 23:44:29.202230 Set Vref, RX VrefLevel [Byte0]: 35
7817 23:44:29.205823 [Byte1]: 35
7818 23:44:29.209567
7819 23:44:29.209647 Set Vref, RX VrefLevel [Byte0]: 36
7820 23:44:29.213116 [Byte1]: 36
7821 23:44:29.217889
7822 23:44:29.217970 Set Vref, RX VrefLevel [Byte0]: 37
7823 23:44:29.220967 [Byte1]: 37
7824 23:44:29.225090
7825 23:44:29.225198 Set Vref, RX VrefLevel [Byte0]: 38
7826 23:44:29.228967 [Byte1]: 38
7827 23:44:29.232585
7828 23:44:29.232664 Set Vref, RX VrefLevel [Byte0]: 39
7829 23:44:29.236208 [Byte1]: 39
7830 23:44:29.240599
7831 23:44:29.240679 Set Vref, RX VrefLevel [Byte0]: 40
7832 23:44:29.243700 [Byte1]: 40
7833 23:44:29.248083
7834 23:44:29.248163 Set Vref, RX VrefLevel [Byte0]: 41
7835 23:44:29.251100 [Byte1]: 41
7836 23:44:29.255364
7837 23:44:29.255444 Set Vref, RX VrefLevel [Byte0]: 42
7838 23:44:29.258994 [Byte1]: 42
7839 23:44:29.263336
7840 23:44:29.263418 Set Vref, RX VrefLevel [Byte0]: 43
7841 23:44:29.266232 [Byte1]: 43
7842 23:44:29.270644
7843 23:44:29.270725 Set Vref, RX VrefLevel [Byte0]: 44
7844 23:44:29.274382 [Byte1]: 44
7845 23:44:29.278100
7846 23:44:29.278180 Set Vref, RX VrefLevel [Byte0]: 45
7847 23:44:29.281929 [Byte1]: 45
7848 23:44:29.286801
7849 23:44:29.286910 Set Vref, RX VrefLevel [Byte0]: 46
7850 23:44:29.289505 [Byte1]: 46
7851 23:44:29.293427
7852 23:44:29.293508 Set Vref, RX VrefLevel [Byte0]: 47
7853 23:44:29.298384 [Byte1]: 47
7854 23:44:29.301300
7855 23:44:29.301436 Set Vref, RX VrefLevel [Byte0]: 48
7856 23:44:29.304720 [Byte1]: 48
7857 23:44:29.308662
7858 23:44:29.308808 Set Vref, RX VrefLevel [Byte0]: 49
7859 23:44:29.312042 [Byte1]: 49
7860 23:44:29.317134
7861 23:44:29.317279 Set Vref, RX VrefLevel [Byte0]: 50
7862 23:44:29.319744 [Byte1]: 50
7863 23:44:29.323919
7864 23:44:29.324037 Set Vref, RX VrefLevel [Byte0]: 51
7865 23:44:29.327586 [Byte1]: 51
7866 23:44:29.331359
7867 23:44:29.331489 Set Vref, RX VrefLevel [Byte0]: 52
7868 23:44:29.334906 [Byte1]: 52
7869 23:44:29.339421
7870 23:44:29.339501 Set Vref, RX VrefLevel [Byte0]: 53
7871 23:44:29.342878 [Byte1]: 53
7872 23:44:29.347025
7873 23:44:29.347105 Set Vref, RX VrefLevel [Byte0]: 54
7874 23:44:29.350227 [Byte1]: 54
7875 23:44:29.354294
7876 23:44:29.354374 Set Vref, RX VrefLevel [Byte0]: 55
7877 23:44:29.357780 [Byte1]: 55
7878 23:44:29.362006
7879 23:44:29.362087 Set Vref, RX VrefLevel [Byte0]: 56
7880 23:44:29.365655 [Byte1]: 56
7881 23:44:29.369637
7882 23:44:29.369718 Set Vref, RX VrefLevel [Byte0]: 57
7883 23:44:29.372701 [Byte1]: 57
7884 23:44:29.377136
7885 23:44:29.377216 Set Vref, RX VrefLevel [Byte0]: 58
7886 23:44:29.380906 [Byte1]: 58
7887 23:44:29.384797
7888 23:44:29.384878 Set Vref, RX VrefLevel [Byte0]: 59
7889 23:44:29.388353 [Byte1]: 59
7890 23:44:29.392484
7891 23:44:29.392564 Set Vref, RX VrefLevel [Byte0]: 60
7892 23:44:29.396357 [Byte1]: 60
7893 23:44:29.400174
7894 23:44:29.400255 Set Vref, RX VrefLevel [Byte0]: 61
7895 23:44:29.403310 [Byte1]: 61
7896 23:44:29.408159
7897 23:44:29.408239 Set Vref, RX VrefLevel [Byte0]: 62
7898 23:44:29.410861 [Byte1]: 62
7899 23:44:29.415105
7900 23:44:29.415185 Set Vref, RX VrefLevel [Byte0]: 63
7901 23:44:29.418797 [Byte1]: 63
7902 23:44:29.422643
7903 23:44:29.422723 Set Vref, RX VrefLevel [Byte0]: 64
7904 23:44:29.426010 [Byte1]: 64
7905 23:44:29.430296
7906 23:44:29.430376 Set Vref, RX VrefLevel [Byte0]: 65
7907 23:44:29.433614 [Byte1]: 65
7908 23:44:29.438379
7909 23:44:29.438459 Set Vref, RX VrefLevel [Byte0]: 66
7910 23:44:29.441728 [Byte1]: 66
7911 23:44:29.445857
7912 23:44:29.445937 Set Vref, RX VrefLevel [Byte0]: 67
7913 23:44:29.449358 [Byte1]: 67
7914 23:44:29.453478
7915 23:44:29.453558 Set Vref, RX VrefLevel [Byte0]: 68
7916 23:44:29.456764 [Byte1]: 68
7917 23:44:29.461152
7918 23:44:29.461233 Set Vref, RX VrefLevel [Byte0]: 69
7919 23:44:29.464347 [Byte1]: 69
7920 23:44:29.468707
7921 23:44:29.468787 Set Vref, RX VrefLevel [Byte0]: 70
7922 23:44:29.471973 [Byte1]: 70
7923 23:44:29.476086
7924 23:44:29.476165 Set Vref, RX VrefLevel [Byte0]: 71
7925 23:44:29.479387 [Byte1]: 71
7926 23:44:29.483792
7927 23:44:29.483872 Set Vref, RX VrefLevel [Byte0]: 72
7928 23:44:29.486974 [Byte1]: 72
7929 23:44:29.491298
7930 23:44:29.491379 Set Vref, RX VrefLevel [Byte0]: 73
7931 23:44:29.494722 [Byte1]: 73
7932 23:44:29.499025
7933 23:44:29.499107 Set Vref, RX VrefLevel [Byte0]: 74
7934 23:44:29.502976 [Byte1]: 74
7935 23:44:29.506628
7936 23:44:29.506708 Set Vref, RX VrefLevel [Byte0]: 75
7937 23:44:29.509697 [Byte1]: 75
7938 23:44:29.514644
7939 23:44:29.514770 Set Vref, RX VrefLevel [Byte0]: 76
7940 23:44:29.517646 [Byte1]: 76
7941 23:44:29.522241
7942 23:44:29.522321 Set Vref, RX VrefLevel [Byte0]: 77
7943 23:44:29.525540 [Byte1]: 77
7944 23:44:29.529917
7945 23:44:29.529997 Final RX Vref Byte 0 = 58 to rank0
7946 23:44:29.532743 Final RX Vref Byte 1 = 62 to rank0
7947 23:44:29.536120 Final RX Vref Byte 0 = 58 to rank1
7948 23:44:29.539767 Final RX Vref Byte 1 = 62 to rank1==
7949 23:44:29.543035 Dram Type= 6, Freq= 0, CH_0, rank 0
7950 23:44:29.549512 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7951 23:44:29.549627 ==
7952 23:44:29.549690 DQS Delay:
7953 23:44:29.549749 DQS0 = 0, DQS1 = 0
7954 23:44:29.552709 DQM Delay:
7955 23:44:29.552789 DQM0 = 128, DQM1 = 121
7956 23:44:29.556499 DQ Delay:
7957 23:44:29.559403 DQ0 =128, DQ1 =132, DQ2 =124, DQ3 =124
7958 23:44:29.563365 DQ4 =132, DQ5 =116, DQ6 =136, DQ7 =136
7959 23:44:29.566197 DQ8 =110, DQ9 =108, DQ10 =122, DQ11 =116
7960 23:44:29.569984 DQ12 =128, DQ13 =126, DQ14 =132, DQ15 =132
7961 23:44:29.570066
7962 23:44:29.570129
7963 23:44:29.570187
7964 23:44:29.573255 [DramC_TX_OE_Calibration] TA2
7965 23:44:29.576219 Original DQ_B0 (3 6) =30, OEN = 27
7966 23:44:29.579360 Original DQ_B1 (3 6) =30, OEN = 27
7967 23:44:29.582927 24, 0x0, End_B0=24 End_B1=24
7968 23:44:29.583009 25, 0x0, End_B0=25 End_B1=25
7969 23:44:29.586068 26, 0x0, End_B0=26 End_B1=26
7970 23:44:29.589791 27, 0x0, End_B0=27 End_B1=27
7971 23:44:29.592642 28, 0x0, End_B0=28 End_B1=28
7972 23:44:29.592751 29, 0x0, End_B0=29 End_B1=29
7973 23:44:29.596746 30, 0x0, End_B0=30 End_B1=30
7974 23:44:29.599715 31, 0x4141, End_B0=30 End_B1=30
7975 23:44:29.602620 Byte0 end_step=30 best_step=27
7976 23:44:29.606275 Byte1 end_step=30 best_step=27
7977 23:44:29.609495 Byte0 TX OE(2T, 0.5T) = (3, 3)
7978 23:44:29.609577 Byte1 TX OE(2T, 0.5T) = (3, 3)
7979 23:44:29.609641
7980 23:44:29.609700
7981 23:44:29.619323 [DQSOSCAuto] RK0, (LSB)MR18= 0x1206, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 400 ps
7982 23:44:29.622993 CH0 RK0: MR19=303, MR18=1206
7983 23:44:29.629985 CH0_RK0: MR19=0x303, MR18=0x1206, DQSOSC=400, MR23=63, INC=23, DEC=15
7984 23:44:29.630081
7985 23:44:29.633271 ----->DramcWriteLeveling(PI) begin...
7986 23:44:29.633354 ==
7987 23:44:29.636966 Dram Type= 6, Freq= 0, CH_0, rank 1
7988 23:44:29.639520 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7989 23:44:29.639602 ==
7990 23:44:29.643069 Write leveling (Byte 0): 32 => 32
7991 23:44:29.646174 Write leveling (Byte 1): 27 => 27
7992 23:44:29.649294 DramcWriteLeveling(PI) end<-----
7993 23:44:29.649383
7994 23:44:29.649447 ==
7995 23:44:29.652953 Dram Type= 6, Freq= 0, CH_0, rank 1
7996 23:44:29.656303 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7997 23:44:29.656385 ==
7998 23:44:29.659487 [Gating] SW mode calibration
7999 23:44:29.666084 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8000 23:44:29.672843 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8001 23:44:29.676175 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8002 23:44:29.679646 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8003 23:44:29.686863 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8004 23:44:29.689616 1 4 12 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
8005 23:44:29.693155 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8006 23:44:29.696765 1 4 20 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
8007 23:44:29.703053 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8008 23:44:29.706479 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8009 23:44:29.709534 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8010 23:44:29.716384 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8011 23:44:29.719848 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8012 23:44:29.723500 1 5 12 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 0)
8013 23:44:29.729705 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8014 23:44:29.732791 1 5 20 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
8015 23:44:29.736281 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8016 23:44:29.742738 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8017 23:44:29.746436 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8018 23:44:29.749446 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8019 23:44:29.756300 1 6 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
8020 23:44:29.759439 1 6 12 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
8021 23:44:29.763178 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8022 23:44:29.769346 1 6 20 | B1->B0 | 3737 4646 | 1 0 | (0 0) (0 0)
8023 23:44:29.772916 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8024 23:44:29.776020 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8025 23:44:29.783241 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8026 23:44:29.786296 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8027 23:44:29.789664 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8028 23:44:29.796281 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8029 23:44:29.799341 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8030 23:44:29.803174 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8031 23:44:29.809509 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8032 23:44:29.812759 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8033 23:44:29.817176 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8034 23:44:29.819765 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8035 23:44:29.826722 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8036 23:44:29.829518 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8037 23:44:29.832608 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8038 23:44:29.839495 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8039 23:44:29.842453 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8040 23:44:29.846190 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8041 23:44:29.852883 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8042 23:44:29.856413 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8043 23:44:29.859430 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8044 23:44:29.866472 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8045 23:44:29.869722 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8046 23:44:29.872734 Total UI for P1: 0, mck2ui 16
8047 23:44:29.876255 best dqsien dly found for B0: ( 1, 9, 10)
8048 23:44:29.880076 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8049 23:44:29.886469 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8050 23:44:29.889350 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8051 23:44:29.893062 Total UI for P1: 0, mck2ui 16
8052 23:44:29.896799 best dqsien dly found for B1: ( 1, 9, 20)
8053 23:44:29.899835 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8054 23:44:29.903441 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8055 23:44:29.903531
8056 23:44:29.906328 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8057 23:44:29.910364 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8058 23:44:29.912865 [Gating] SW calibration Done
8059 23:44:29.912988 ==
8060 23:44:29.916252 Dram Type= 6, Freq= 0, CH_0, rank 1
8061 23:44:29.919834 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8062 23:44:29.919930 ==
8063 23:44:29.923213 RX Vref Scan: 0
8064 23:44:29.923304
8065 23:44:29.926408 RX Vref 0 -> 0, step: 1
8066 23:44:29.926502
8067 23:44:29.926572 RX Delay 0 -> 252, step: 8
8068 23:44:29.932898 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8069 23:44:29.936222 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8070 23:44:29.940311 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
8071 23:44:29.943390 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8072 23:44:29.946792 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8073 23:44:29.950250 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8074 23:44:29.956389 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8075 23:44:29.959808 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8076 23:44:29.963149 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8077 23:44:29.966780 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8078 23:44:29.969658 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8079 23:44:29.976352 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8080 23:44:29.979477 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8081 23:44:29.983187 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8082 23:44:29.986617 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8083 23:44:29.993721 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8084 23:44:29.993844 ==
8085 23:44:29.996382 Dram Type= 6, Freq= 0, CH_0, rank 1
8086 23:44:29.999987 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8087 23:44:30.000072 ==
8088 23:44:30.000136 DQS Delay:
8089 23:44:30.003843 DQS0 = 0, DQS1 = 0
8090 23:44:30.003925 DQM Delay:
8091 23:44:30.006546 DQM0 = 131, DQM1 = 124
8092 23:44:30.006626 DQ Delay:
8093 23:44:30.010493 DQ0 =131, DQ1 =131, DQ2 =131, DQ3 =131
8094 23:44:30.013792 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
8095 23:44:30.016753 DQ8 =115, DQ9 =115, DQ10 =123, DQ11 =119
8096 23:44:30.019807 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =131
8097 23:44:30.019882
8098 23:44:30.019943
8099 23:44:30.020031 ==
8100 23:44:30.023904 Dram Type= 6, Freq= 0, CH_0, rank 1
8101 23:44:30.030095 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8102 23:44:30.030174 ==
8103 23:44:30.030236
8104 23:44:30.030293
8105 23:44:30.030353 TX Vref Scan disable
8106 23:44:30.033291 == TX Byte 0 ==
8107 23:44:30.036919 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8108 23:44:30.043769 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8109 23:44:30.043854 == TX Byte 1 ==
8110 23:44:30.046818 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8111 23:44:30.053807 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8112 23:44:30.053889 ==
8113 23:44:30.056846 Dram Type= 6, Freq= 0, CH_0, rank 1
8114 23:44:30.061712 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8115 23:44:30.061799 ==
8116 23:44:30.072926
8117 23:44:30.076200 TX Vref early break, caculate TX vref
8118 23:44:30.079314 TX Vref=16, minBit 3, minWin=22, winSum=372
8119 23:44:30.082994 TX Vref=18, minBit 9, minWin=22, winSum=381
8120 23:44:30.085917 TX Vref=20, minBit 7, minWin=23, winSum=393
8121 23:44:30.089315 TX Vref=22, minBit 0, minWin=24, winSum=396
8122 23:44:30.092828 TX Vref=24, minBit 9, minWin=24, winSum=404
8123 23:44:30.099860 TX Vref=26, minBit 3, minWin=25, winSum=414
8124 23:44:30.102973 TX Vref=28, minBit 1, minWin=26, winSum=426
8125 23:44:30.106093 TX Vref=30, minBit 0, minWin=26, winSum=422
8126 23:44:30.110026 TX Vref=32, minBit 0, minWin=25, winSum=410
8127 23:44:30.112791 TX Vref=34, minBit 1, minWin=24, winSum=400
8128 23:44:30.119269 [TxChooseVref] Worse bit 1, Min win 26, Win sum 426, Final Vref 28
8129 23:44:30.119387
8130 23:44:30.122786 Final TX Range 0 Vref 28
8131 23:44:30.122895
8132 23:44:30.122993 ==
8133 23:44:30.126170 Dram Type= 6, Freq= 0, CH_0, rank 1
8134 23:44:30.129492 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8135 23:44:30.129579 ==
8136 23:44:30.129643
8137 23:44:30.129711
8138 23:44:30.132762 TX Vref Scan disable
8139 23:44:30.139842 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8140 23:44:30.139994 == TX Byte 0 ==
8141 23:44:30.142678 u2DelayCellOfst[0]=10 cells (3 PI)
8142 23:44:30.146296 u2DelayCellOfst[1]=17 cells (5 PI)
8143 23:44:30.149910 u2DelayCellOfst[2]=10 cells (3 PI)
8144 23:44:30.153158 u2DelayCellOfst[3]=10 cells (3 PI)
8145 23:44:30.156060 u2DelayCellOfst[4]=7 cells (2 PI)
8146 23:44:30.159388 u2DelayCellOfst[5]=0 cells (0 PI)
8147 23:44:30.159500 u2DelayCellOfst[6]=17 cells (5 PI)
8148 23:44:30.162931 u2DelayCellOfst[7]=14 cells (4 PI)
8149 23:44:30.170124 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8150 23:44:30.173201 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8151 23:44:30.173313 == TX Byte 1 ==
8152 23:44:30.176073 u2DelayCellOfst[8]=0 cells (0 PI)
8153 23:44:30.180191 u2DelayCellOfst[9]=0 cells (0 PI)
8154 23:44:30.182921 u2DelayCellOfst[10]=7 cells (2 PI)
8155 23:44:30.186666 u2DelayCellOfst[11]=0 cells (0 PI)
8156 23:44:30.189717 u2DelayCellOfst[12]=14 cells (4 PI)
8157 23:44:30.192945 u2DelayCellOfst[13]=10 cells (3 PI)
8158 23:44:30.196370 u2DelayCellOfst[14]=14 cells (4 PI)
8159 23:44:30.199579 u2DelayCellOfst[15]=10 cells (3 PI)
8160 23:44:30.203178 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8161 23:44:30.206421 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8162 23:44:30.209456 DramC Write-DBI on
8163 23:44:30.209541 ==
8164 23:44:30.213012 Dram Type= 6, Freq= 0, CH_0, rank 1
8165 23:44:30.216496 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8166 23:44:30.216588 ==
8167 23:44:30.216659
8168 23:44:30.219776
8169 23:44:30.219860 TX Vref Scan disable
8170 23:44:30.222970 == TX Byte 0 ==
8171 23:44:30.226337 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
8172 23:44:30.230066 == TX Byte 1 ==
8173 23:44:30.233349 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8174 23:44:30.233444 DramC Write-DBI off
8175 23:44:30.233529
8176 23:44:30.236165 [DATLAT]
8177 23:44:30.236251 Freq=1600, CH0 RK1
8178 23:44:30.236335
8179 23:44:30.239341 DATLAT Default: 0xf
8180 23:44:30.239442 0, 0xFFFF, sum = 0
8181 23:44:30.242745 1, 0xFFFF, sum = 0
8182 23:44:30.242859 2, 0xFFFF, sum = 0
8183 23:44:30.246066 3, 0xFFFF, sum = 0
8184 23:44:30.246180 4, 0xFFFF, sum = 0
8185 23:44:30.249570 5, 0xFFFF, sum = 0
8186 23:44:30.249660 6, 0xFFFF, sum = 0
8187 23:44:30.252575 7, 0xFFFF, sum = 0
8188 23:44:30.252663 8, 0xFFFF, sum = 0
8189 23:44:30.256268 9, 0xFFFF, sum = 0
8190 23:44:30.259538 10, 0xFFFF, sum = 0
8191 23:44:30.259645 11, 0xFFFF, sum = 0
8192 23:44:30.262697 12, 0xFFFF, sum = 0
8193 23:44:30.262794 13, 0xFFFF, sum = 0
8194 23:44:30.266055 14, 0x0, sum = 1
8195 23:44:30.266221 15, 0x0, sum = 2
8196 23:44:30.269256 16, 0x0, sum = 3
8197 23:44:30.269406 17, 0x0, sum = 4
8198 23:44:30.269540 best_step = 15
8199 23:44:30.269663
8200 23:44:30.272706 ==
8201 23:44:30.276267 Dram Type= 6, Freq= 0, CH_0, rank 1
8202 23:44:30.279650 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8203 23:44:30.279810 ==
8204 23:44:30.279938 RX Vref Scan: 0
8205 23:44:30.280067
8206 23:44:30.282979 RX Vref 0 -> 0, step: 1
8207 23:44:30.283119
8208 23:44:30.286264 RX Delay 11 -> 252, step: 4
8209 23:44:30.289687 iDelay=191, Bit 0, Center 126 (71 ~ 182) 112
8210 23:44:30.292826 iDelay=191, Bit 1, Center 130 (75 ~ 186) 112
8211 23:44:30.299688 iDelay=191, Bit 2, Center 124 (71 ~ 178) 108
8212 23:44:30.303052 iDelay=191, Bit 3, Center 126 (71 ~ 182) 112
8213 23:44:30.306502 iDelay=191, Bit 4, Center 126 (75 ~ 178) 104
8214 23:44:30.309314 iDelay=191, Bit 5, Center 116 (63 ~ 170) 108
8215 23:44:30.312900 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8216 23:44:30.319798 iDelay=191, Bit 7, Center 136 (83 ~ 190) 108
8217 23:44:30.322916 iDelay=191, Bit 8, Center 112 (59 ~ 166) 108
8218 23:44:30.327199 iDelay=191, Bit 9, Center 110 (55 ~ 166) 112
8219 23:44:30.329311 iDelay=191, Bit 10, Center 122 (67 ~ 178) 112
8220 23:44:30.332692 iDelay=191, Bit 11, Center 116 (63 ~ 170) 108
8221 23:44:30.339764 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8222 23:44:30.342794 iDelay=191, Bit 13, Center 126 (71 ~ 182) 112
8223 23:44:30.346313 iDelay=191, Bit 14, Center 134 (79 ~ 190) 112
8224 23:44:30.349514 iDelay=191, Bit 15, Center 130 (75 ~ 186) 112
8225 23:44:30.349661 ==
8226 23:44:30.352711 Dram Type= 6, Freq= 0, CH_0, rank 1
8227 23:44:30.359425 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8228 23:44:30.359618 ==
8229 23:44:30.359745 DQS Delay:
8230 23:44:30.359868 DQS0 = 0, DQS1 = 0
8231 23:44:30.362847 DQM Delay:
8232 23:44:30.362999 DQM0 = 127, DQM1 = 122
8233 23:44:30.366076 DQ Delay:
8234 23:44:30.369855 DQ0 =126, DQ1 =130, DQ2 =124, DQ3 =126
8235 23:44:30.372748 DQ4 =126, DQ5 =116, DQ6 =134, DQ7 =136
8236 23:44:30.376276 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
8237 23:44:30.379862 DQ12 =126, DQ13 =126, DQ14 =134, DQ15 =130
8238 23:44:30.380012
8239 23:44:30.380144
8240 23:44:30.380270
8241 23:44:30.382867 [DramC_TX_OE_Calibration] TA2
8242 23:44:30.385868 Original DQ_B0 (3 6) =30, OEN = 27
8243 23:44:30.389591 Original DQ_B1 (3 6) =30, OEN = 27
8244 23:44:30.392485 24, 0x0, End_B0=24 End_B1=24
8245 23:44:30.392618 25, 0x0, End_B0=25 End_B1=25
8246 23:44:30.396420 26, 0x0, End_B0=26 End_B1=26
8247 23:44:30.399835 27, 0x0, End_B0=27 End_B1=27
8248 23:44:30.402543 28, 0x0, End_B0=28 End_B1=28
8249 23:44:30.402678 29, 0x0, End_B0=29 End_B1=29
8250 23:44:30.405994 30, 0x0, End_B0=30 End_B1=30
8251 23:44:30.409176 31, 0x4141, End_B0=30 End_B1=30
8252 23:44:30.412680 Byte0 end_step=30 best_step=27
8253 23:44:30.415900 Byte1 end_step=30 best_step=27
8254 23:44:30.419615 Byte0 TX OE(2T, 0.5T) = (3, 3)
8255 23:44:30.419758 Byte1 TX OE(2T, 0.5T) = (3, 3)
8256 23:44:30.419883
8257 23:44:30.422621
8258 23:44:30.429234 [DQSOSCAuto] RK1, (LSB)MR18= 0x160b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 398 ps
8259 23:44:30.432711 CH0 RK1: MR19=303, MR18=160B
8260 23:44:30.441021 CH0_RK1: MR19=0x303, MR18=0x160B, DQSOSC=398, MR23=63, INC=23, DEC=15
8261 23:44:30.442743 [RxdqsGatingPostProcess] freq 1600
8262 23:44:30.446308 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8263 23:44:30.449563 best DQS0 dly(2T, 0.5T) = (1, 1)
8264 23:44:30.452979 best DQS1 dly(2T, 0.5T) = (1, 1)
8265 23:44:30.456235 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8266 23:44:30.459753 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8267 23:44:30.462999 best DQS0 dly(2T, 0.5T) = (1, 1)
8268 23:44:30.466127 best DQS1 dly(2T, 0.5T) = (1, 1)
8269 23:44:30.469735 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8270 23:44:30.469829 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8271 23:44:30.473264 Pre-setting of DQS Precalculation
8272 23:44:30.479397 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8273 23:44:30.479506 ==
8274 23:44:30.483295 Dram Type= 6, Freq= 0, CH_1, rank 0
8275 23:44:30.486269 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8276 23:44:30.486362 ==
8277 23:44:30.492779 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8278 23:44:30.496662 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8279 23:44:30.499645 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8280 23:44:30.506645 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8281 23:44:30.515657 [CA 0] Center 42 (14~71) winsize 58
8282 23:44:30.518720 [CA 1] Center 42 (13~71) winsize 59
8283 23:44:30.521887 [CA 2] Center 37 (8~66) winsize 59
8284 23:44:30.525781 [CA 3] Center 36 (7~66) winsize 60
8285 23:44:30.528779 [CA 4] Center 36 (7~66) winsize 60
8286 23:44:30.532138 [CA 5] Center 36 (7~66) winsize 60
8287 23:44:30.532232
8288 23:44:30.535939 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8289 23:44:30.536034
8290 23:44:30.538951 [CATrainingPosCal] consider 1 rank data
8291 23:44:30.542927 u2DelayCellTimex100 = 275/100 ps
8292 23:44:30.545731 CA0 delay=42 (14~71),Diff = 6 PI (21 cell)
8293 23:44:30.551938 CA1 delay=42 (13~71),Diff = 6 PI (21 cell)
8294 23:44:30.556094 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8295 23:44:30.559352 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8296 23:44:30.562448 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
8297 23:44:30.565894 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8298 23:44:30.565998
8299 23:44:30.569255 CA PerBit enable=1, Macro0, CA PI delay=36
8300 23:44:30.569349
8301 23:44:30.572950 [CBTSetCACLKResult] CA Dly = 36
8302 23:44:30.573084 CS Dly: 8 (0~39)
8303 23:44:30.579054 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8304 23:44:30.582320 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8305 23:44:30.582420 ==
8306 23:44:30.585630 Dram Type= 6, Freq= 0, CH_1, rank 1
8307 23:44:30.590182 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8308 23:44:30.590295 ==
8309 23:44:30.595427 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8310 23:44:30.598993 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8311 23:44:30.602502 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8312 23:44:30.609253 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8313 23:44:30.618290 [CA 0] Center 43 (14~72) winsize 59
8314 23:44:30.621693 [CA 1] Center 43 (15~72) winsize 58
8315 23:44:30.625734 [CA 2] Center 38 (9~67) winsize 59
8316 23:44:30.628454 [CA 3] Center 37 (8~66) winsize 59
8317 23:44:30.631842 [CA 4] Center 38 (9~67) winsize 59
8318 23:44:30.635090 [CA 5] Center 36 (7~66) winsize 60
8319 23:44:30.635173
8320 23:44:30.638738 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8321 23:44:30.638822
8322 23:44:30.641863 [CATrainingPosCal] consider 2 rank data
8323 23:44:30.645505 u2DelayCellTimex100 = 275/100 ps
8324 23:44:30.649273 CA0 delay=42 (14~71),Diff = 6 PI (21 cell)
8325 23:44:30.655720 CA1 delay=43 (15~71),Diff = 7 PI (24 cell)
8326 23:44:30.659059 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8327 23:44:30.662089 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8328 23:44:30.665379 CA4 delay=37 (9~66),Diff = 1 PI (3 cell)
8329 23:44:30.668614 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8330 23:44:30.668698
8331 23:44:30.671826 CA PerBit enable=1, Macro0, CA PI delay=36
8332 23:44:30.671911
8333 23:44:30.675131 [CBTSetCACLKResult] CA Dly = 36
8334 23:44:30.675205 CS Dly: 10 (0~44)
8335 23:44:30.682265 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8336 23:44:30.685105 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8337 23:44:30.685181
8338 23:44:30.688495 ----->DramcWriteLeveling(PI) begin...
8339 23:44:30.688579 ==
8340 23:44:30.691970 Dram Type= 6, Freq= 0, CH_1, rank 0
8341 23:44:30.695582 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8342 23:44:30.695671 ==
8343 23:44:30.698794 Write leveling (Byte 0): 24 => 24
8344 23:44:30.702522 Write leveling (Byte 1): 28 => 28
8345 23:44:30.705642 DramcWriteLeveling(PI) end<-----
8346 23:44:30.705717
8347 23:44:30.705778 ==
8348 23:44:30.709089 Dram Type= 6, Freq= 0, CH_1, rank 0
8349 23:44:30.712046 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8350 23:44:30.715295 ==
8351 23:44:30.715365 [Gating] SW mode calibration
8352 23:44:30.725097 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8353 23:44:30.728720 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8354 23:44:30.732343 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8355 23:44:30.738812 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8356 23:44:30.741749 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8357 23:44:30.745716 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8358 23:44:30.751756 1 4 16 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
8359 23:44:30.755071 1 4 20 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
8360 23:44:30.758715 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8361 23:44:30.765518 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8362 23:44:30.768812 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8363 23:44:30.771912 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8364 23:44:30.778468 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8365 23:44:30.781747 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8366 23:44:30.785442 1 5 16 | B1->B0 | 2828 3333 | 1 1 | (1 0) (1 0)
8367 23:44:30.792048 1 5 20 | B1->B0 | 2323 2424 | 0 0 | (1 0) (0 0)
8368 23:44:30.795344 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8369 23:44:30.798868 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8370 23:44:30.805646 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8371 23:44:30.809127 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8372 23:44:30.811627 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8373 23:44:30.815177 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8374 23:44:30.821873 1 6 16 | B1->B0 | 3434 2b2b | 0 0 | (0 0) (0 0)
8375 23:44:30.825580 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8376 23:44:30.828769 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8377 23:44:30.835162 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8378 23:44:30.838864 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8379 23:44:30.842187 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8380 23:44:30.848718 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8381 23:44:30.851643 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8382 23:44:30.855092 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8383 23:44:30.861657 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8384 23:44:30.865558 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8385 23:44:30.868803 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8386 23:44:30.875362 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8387 23:44:30.878359 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8388 23:44:30.883030 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8389 23:44:30.888405 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8390 23:44:30.892189 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8391 23:44:30.895503 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8392 23:44:30.898733 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8393 23:44:30.905302 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8394 23:44:30.908539 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8395 23:44:30.911907 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 23:44:30.919113 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8397 23:44:30.922076 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 23:44:30.925363 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8399 23:44:30.932004 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8400 23:44:30.935381 Total UI for P1: 0, mck2ui 16
8401 23:44:30.938627 best dqsien dly found for B0: ( 1, 9, 16)
8402 23:44:30.938723 Total UI for P1: 0, mck2ui 16
8403 23:44:30.945758 best dqsien dly found for B1: ( 1, 9, 16)
8404 23:44:30.948590 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8405 23:44:30.951793 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8406 23:44:30.951897
8407 23:44:30.955274 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8408 23:44:30.958952 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8409 23:44:30.962283 [Gating] SW calibration Done
8410 23:44:30.962393 ==
8411 23:44:30.965257 Dram Type= 6, Freq= 0, CH_1, rank 0
8412 23:44:30.968764 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8413 23:44:30.968864 ==
8414 23:44:30.971985 RX Vref Scan: 0
8415 23:44:30.972076
8416 23:44:30.972140 RX Vref 0 -> 0, step: 1
8417 23:44:30.972199
8418 23:44:30.975207 RX Delay 0 -> 252, step: 8
8419 23:44:30.978453 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8420 23:44:30.985265 iDelay=208, Bit 1, Center 127 (72 ~ 183) 112
8421 23:44:30.988858 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8422 23:44:30.991927 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8423 23:44:30.995709 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8424 23:44:30.998391 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8425 23:44:31.005267 iDelay=208, Bit 6, Center 143 (96 ~ 191) 96
8426 23:44:31.008407 iDelay=208, Bit 7, Center 127 (72 ~ 183) 112
8427 23:44:31.011928 iDelay=208, Bit 8, Center 111 (56 ~ 167) 112
8428 23:44:31.015101 iDelay=208, Bit 9, Center 115 (64 ~ 167) 104
8429 23:44:31.018925 iDelay=208, Bit 10, Center 127 (72 ~ 183) 112
8430 23:44:31.025584 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8431 23:44:31.028698 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8432 23:44:31.031841 iDelay=208, Bit 13, Center 135 (80 ~ 191) 112
8433 23:44:31.035101 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8434 23:44:31.038174 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8435 23:44:31.041662 ==
8436 23:44:31.041758 Dram Type= 6, Freq= 0, CH_1, rank 0
8437 23:44:31.048687 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8438 23:44:31.048807 ==
8439 23:44:31.048881 DQS Delay:
8440 23:44:31.051667 DQS0 = 0, DQS1 = 0
8441 23:44:31.051755 DQM Delay:
8442 23:44:31.055330 DQM0 = 134, DQM1 = 127
8443 23:44:31.055420 DQ Delay:
8444 23:44:31.058694 DQ0 =139, DQ1 =127, DQ2 =123, DQ3 =135
8445 23:44:31.061745 DQ4 =135, DQ5 =147, DQ6 =143, DQ7 =127
8446 23:44:31.065493 DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =123
8447 23:44:31.068914 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8448 23:44:31.069039
8449 23:44:31.069104
8450 23:44:31.069164 ==
8451 23:44:31.071978 Dram Type= 6, Freq= 0, CH_1, rank 0
8452 23:44:31.078232 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8453 23:44:31.078315 ==
8454 23:44:31.078380
8455 23:44:31.078439
8456 23:44:31.078496 TX Vref Scan disable
8457 23:44:31.081757 == TX Byte 0 ==
8458 23:44:31.085170 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8459 23:44:31.091905 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8460 23:44:31.092003 == TX Byte 1 ==
8461 23:44:31.094930 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8462 23:44:31.101311 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8463 23:44:31.102258 ==
8464 23:44:31.105277 Dram Type= 6, Freq= 0, CH_1, rank 0
8465 23:44:31.108830 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8466 23:44:31.108920 ==
8467 23:44:31.121764
8468 23:44:31.125806 TX Vref early break, caculate TX vref
8469 23:44:31.128833 TX Vref=16, minBit 8, minWin=21, winSum=361
8470 23:44:31.131800 TX Vref=18, minBit 8, minWin=21, winSum=371
8471 23:44:31.135260 TX Vref=20, minBit 5, minWin=23, winSum=387
8472 23:44:31.138813 TX Vref=22, minBit 8, minWin=23, winSum=392
8473 23:44:31.141866 TX Vref=24, minBit 5, minWin=24, winSum=403
8474 23:44:31.145816 TX Vref=26, minBit 5, minWin=24, winSum=409
8475 23:44:31.152106 TX Vref=28, minBit 5, minWin=25, winSum=419
8476 23:44:31.155294 TX Vref=30, minBit 11, minWin=24, winSum=417
8477 23:44:31.158848 TX Vref=32, minBit 8, minWin=24, winSum=411
8478 23:44:31.162365 TX Vref=34, minBit 0, minWin=24, winSum=398
8479 23:44:31.165200 TX Vref=36, minBit 0, minWin=23, winSum=385
8480 23:44:31.172294 [TxChooseVref] Worse bit 5, Min win 25, Win sum 419, Final Vref 28
8481 23:44:31.172395
8482 23:44:31.175593 Final TX Range 0 Vref 28
8483 23:44:31.175676
8484 23:44:31.175740 ==
8485 23:44:31.178725 Dram Type= 6, Freq= 0, CH_1, rank 0
8486 23:44:31.182348 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8487 23:44:31.182439 ==
8488 23:44:31.182504
8489 23:44:31.182563
8490 23:44:31.185856 TX Vref Scan disable
8491 23:44:31.192641 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8492 23:44:31.192726 == TX Byte 0 ==
8493 23:44:31.195860 u2DelayCellOfst[0]=17 cells (5 PI)
8494 23:44:31.198703 u2DelayCellOfst[1]=10 cells (3 PI)
8495 23:44:31.202903 u2DelayCellOfst[2]=0 cells (0 PI)
8496 23:44:31.205692 u2DelayCellOfst[3]=7 cells (2 PI)
8497 23:44:31.208721 u2DelayCellOfst[4]=7 cells (2 PI)
8498 23:44:31.212061 u2DelayCellOfst[5]=17 cells (5 PI)
8499 23:44:31.215875 u2DelayCellOfst[6]=17 cells (5 PI)
8500 23:44:31.215976 u2DelayCellOfst[7]=7 cells (2 PI)
8501 23:44:31.222578 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8502 23:44:31.225646 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8503 23:44:31.225739 == TX Byte 1 ==
8504 23:44:31.229404 u2DelayCellOfst[8]=0 cells (0 PI)
8505 23:44:31.232405 u2DelayCellOfst[9]=3 cells (1 PI)
8506 23:44:31.235973 u2DelayCellOfst[10]=10 cells (3 PI)
8507 23:44:31.238955 u2DelayCellOfst[11]=7 cells (2 PI)
8508 23:44:31.242359 u2DelayCellOfst[12]=14 cells (4 PI)
8509 23:44:31.245528 u2DelayCellOfst[13]=14 cells (4 PI)
8510 23:44:31.248958 u2DelayCellOfst[14]=17 cells (5 PI)
8511 23:44:31.252676 u2DelayCellOfst[15]=17 cells (5 PI)
8512 23:44:31.256642 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8513 23:44:31.262392 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8514 23:44:31.262516 DramC Write-DBI on
8515 23:44:31.262586 ==
8516 23:44:31.265646 Dram Type= 6, Freq= 0, CH_1, rank 0
8517 23:44:31.268760 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8518 23:44:31.268861 ==
8519 23:44:31.268929
8520 23:44:31.272223
8521 23:44:31.272306 TX Vref Scan disable
8522 23:44:31.275410 == TX Byte 0 ==
8523 23:44:31.278938 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8524 23:44:31.282505 == TX Byte 1 ==
8525 23:44:31.285649 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8526 23:44:31.285732 DramC Write-DBI off
8527 23:44:31.285796
8528 23:44:31.288924 [DATLAT]
8529 23:44:31.289017 Freq=1600, CH1 RK0
8530 23:44:31.289098
8531 23:44:31.292507 DATLAT Default: 0xf
8532 23:44:31.292590 0, 0xFFFF, sum = 0
8533 23:44:31.296143 1, 0xFFFF, sum = 0
8534 23:44:31.296228 2, 0xFFFF, sum = 0
8535 23:44:31.299150 3, 0xFFFF, sum = 0
8536 23:44:31.299234 4, 0xFFFF, sum = 0
8537 23:44:31.302612 5, 0xFFFF, sum = 0
8538 23:44:31.302697 6, 0xFFFF, sum = 0
8539 23:44:31.305815 7, 0xFFFF, sum = 0
8540 23:44:31.305900 8, 0xFFFF, sum = 0
8541 23:44:31.309008 9, 0xFFFF, sum = 0
8542 23:44:31.309106 10, 0xFFFF, sum = 0
8543 23:44:31.313245 11, 0xFFFF, sum = 0
8544 23:44:31.316255 12, 0xFFFF, sum = 0
8545 23:44:31.316340 13, 0xFFFF, sum = 0
8546 23:44:31.319256 14, 0x0, sum = 1
8547 23:44:31.319340 15, 0x0, sum = 2
8548 23:44:31.319406 16, 0x0, sum = 3
8549 23:44:31.322276 17, 0x0, sum = 4
8550 23:44:31.322360 best_step = 15
8551 23:44:31.322424
8552 23:44:31.326481 ==
8553 23:44:31.326564 Dram Type= 6, Freq= 0, CH_1, rank 0
8554 23:44:31.332519 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8555 23:44:31.332606 ==
8556 23:44:31.332670 RX Vref Scan: 1
8557 23:44:31.332730
8558 23:44:31.335970 Set Vref Range= 24 -> 127
8559 23:44:31.336053
8560 23:44:31.339225 RX Vref 24 -> 127, step: 1
8561 23:44:31.339309
8562 23:44:31.342505 RX Delay 11 -> 252, step: 4
8563 23:44:31.342587
8564 23:44:31.345837 Set Vref, RX VrefLevel [Byte0]: 24
8565 23:44:31.349637 [Byte1]: 24
8566 23:44:31.349721
8567 23:44:31.352538 Set Vref, RX VrefLevel [Byte0]: 25
8568 23:44:31.355522 [Byte1]: 25
8569 23:44:31.355605
8570 23:44:31.359443 Set Vref, RX VrefLevel [Byte0]: 26
8571 23:44:31.362319 [Byte1]: 26
8572 23:44:31.362404
8573 23:44:31.365960 Set Vref, RX VrefLevel [Byte0]: 27
8574 23:44:31.369275 [Byte1]: 27
8575 23:44:31.373117
8576 23:44:31.373200 Set Vref, RX VrefLevel [Byte0]: 28
8577 23:44:31.377163 [Byte1]: 28
8578 23:44:31.380732
8579 23:44:31.380836 Set Vref, RX VrefLevel [Byte0]: 29
8580 23:44:31.384247 [Byte1]: 29
8581 23:44:31.388199
8582 23:44:31.388288 Set Vref, RX VrefLevel [Byte0]: 30
8583 23:44:31.391931 [Byte1]: 30
8584 23:44:31.395756
8585 23:44:31.395840 Set Vref, RX VrefLevel [Byte0]: 31
8586 23:44:31.399171 [Byte1]: 31
8587 23:44:31.403511
8588 23:44:31.403598 Set Vref, RX VrefLevel [Byte0]: 32
8589 23:44:31.406798 [Byte1]: 32
8590 23:44:31.411183
8591 23:44:31.411268 Set Vref, RX VrefLevel [Byte0]: 33
8592 23:44:31.414855 [Byte1]: 33
8593 23:44:31.419767
8594 23:44:31.419858 Set Vref, RX VrefLevel [Byte0]: 34
8595 23:44:31.422125 [Byte1]: 34
8596 23:44:31.427174
8597 23:44:31.427276 Set Vref, RX VrefLevel [Byte0]: 35
8598 23:44:31.430380 [Byte1]: 35
8599 23:44:31.434454
8600 23:44:31.434541 Set Vref, RX VrefLevel [Byte0]: 36
8601 23:44:31.437449 [Byte1]: 36
8602 23:44:31.442928
8603 23:44:31.443023 Set Vref, RX VrefLevel [Byte0]: 37
8604 23:44:31.444724 [Byte1]: 37
8605 23:44:31.449079
8606 23:44:31.449166 Set Vref, RX VrefLevel [Byte0]: 38
8607 23:44:31.452955 [Byte1]: 38
8608 23:44:31.456960
8609 23:44:31.457108 Set Vref, RX VrefLevel [Byte0]: 39
8610 23:44:31.460487 [Byte1]: 39
8611 23:44:31.464890
8612 23:44:31.465034 Set Vref, RX VrefLevel [Byte0]: 40
8613 23:44:31.468222 [Byte1]: 40
8614 23:44:31.472098
8615 23:44:31.472187 Set Vref, RX VrefLevel [Byte0]: 41
8616 23:44:31.475526 [Byte1]: 41
8617 23:44:31.480073
8618 23:44:31.480150 Set Vref, RX VrefLevel [Byte0]: 42
8619 23:44:31.482971 [Byte1]: 42
8620 23:44:31.487115
8621 23:44:31.487190 Set Vref, RX VrefLevel [Byte0]: 43
8622 23:44:31.490814 [Byte1]: 43
8623 23:44:31.495330
8624 23:44:31.495444 Set Vref, RX VrefLevel [Byte0]: 44
8625 23:44:31.498119 [Byte1]: 44
8626 23:44:31.502788
8627 23:44:31.502893 Set Vref, RX VrefLevel [Byte0]: 45
8628 23:44:31.505931 [Byte1]: 45
8629 23:44:31.510231
8630 23:44:31.510334 Set Vref, RX VrefLevel [Byte0]: 46
8631 23:44:31.513437 [Byte1]: 46
8632 23:44:31.518465
8633 23:44:31.518573 Set Vref, RX VrefLevel [Byte0]: 47
8634 23:44:31.521774 [Byte1]: 47
8635 23:44:31.525257
8636 23:44:31.525386 Set Vref, RX VrefLevel [Byte0]: 48
8637 23:44:31.529169 [Byte1]: 48
8638 23:44:31.533184
8639 23:44:31.533276 Set Vref, RX VrefLevel [Byte0]: 49
8640 23:44:31.536511 [Byte1]: 49
8641 23:44:31.541493
8642 23:44:31.541585 Set Vref, RX VrefLevel [Byte0]: 50
8643 23:44:31.543698 [Byte1]: 50
8644 23:44:31.548475
8645 23:44:31.548567 Set Vref, RX VrefLevel [Byte0]: 51
8646 23:44:31.552046 [Byte1]: 51
8647 23:44:31.555782
8648 23:44:31.555963 Set Vref, RX VrefLevel [Byte0]: 52
8649 23:44:31.558939 [Byte1]: 52
8650 23:44:31.563802
8651 23:44:31.563927 Set Vref, RX VrefLevel [Byte0]: 53
8652 23:44:31.566975 [Byte1]: 53
8653 23:44:31.571054
8654 23:44:31.571167 Set Vref, RX VrefLevel [Byte0]: 54
8655 23:44:31.575056 [Byte1]: 54
8656 23:44:31.579028
8657 23:44:31.579132 Set Vref, RX VrefLevel [Byte0]: 55
8658 23:44:31.581941 [Byte1]: 55
8659 23:44:31.586232
8660 23:44:31.586335 Set Vref, RX VrefLevel [Byte0]: 56
8661 23:44:31.589768 [Byte1]: 56
8662 23:44:31.593847
8663 23:44:31.593993 Set Vref, RX VrefLevel [Byte0]: 57
8664 23:44:31.597013 [Byte1]: 57
8665 23:44:31.601246
8666 23:44:31.601386 Set Vref, RX VrefLevel [Byte0]: 58
8667 23:44:31.604624 [Byte1]: 58
8668 23:44:31.608987
8669 23:44:31.609155 Set Vref, RX VrefLevel [Byte0]: 59
8670 23:44:31.612262 [Byte1]: 59
8671 23:44:31.616785
8672 23:44:31.616925 Set Vref, RX VrefLevel [Byte0]: 60
8673 23:44:31.619809 [Byte1]: 60
8674 23:44:31.624785
8675 23:44:31.624878 Set Vref, RX VrefLevel [Byte0]: 61
8676 23:44:31.628006 [Byte1]: 61
8677 23:44:31.632070
8678 23:44:31.632157 Set Vref, RX VrefLevel [Byte0]: 62
8679 23:44:31.635774 [Byte1]: 62
8680 23:44:31.639995
8681 23:44:31.640100 Set Vref, RX VrefLevel [Byte0]: 63
8682 23:44:31.643050 [Byte1]: 63
8683 23:44:31.647320
8684 23:44:31.647428 Set Vref, RX VrefLevel [Byte0]: 64
8685 23:44:31.650927 [Byte1]: 64
8686 23:44:31.654851
8687 23:44:31.654949 Set Vref, RX VrefLevel [Byte0]: 65
8688 23:44:31.658692 [Byte1]: 65
8689 23:44:31.662256
8690 23:44:31.662343 Set Vref, RX VrefLevel [Byte0]: 66
8691 23:44:31.665982 [Byte1]: 66
8692 23:44:31.670388
8693 23:44:31.670480 Set Vref, RX VrefLevel [Byte0]: 67
8694 23:44:31.673330 [Byte1]: 67
8695 23:44:31.677854
8696 23:44:31.677941 Set Vref, RX VrefLevel [Byte0]: 68
8697 23:44:31.680793 [Byte1]: 68
8698 23:44:31.685393
8699 23:44:31.685479 Set Vref, RX VrefLevel [Byte0]: 69
8700 23:44:31.689238 [Byte1]: 69
8701 23:44:31.693179
8702 23:44:31.693263 Set Vref, RX VrefLevel [Byte0]: 70
8703 23:44:31.696304 [Byte1]: 70
8704 23:44:31.700581
8705 23:44:31.700666 Set Vref, RX VrefLevel [Byte0]: 71
8706 23:44:31.704280 [Byte1]: 71
8707 23:44:31.709090
8708 23:44:31.709178 Set Vref, RX VrefLevel [Byte0]: 72
8709 23:44:31.712000 [Byte1]: 72
8710 23:44:31.715683
8711 23:44:31.715771 Set Vref, RX VrefLevel [Byte0]: 73
8712 23:44:31.719052 [Byte1]: 73
8713 23:44:31.723495
8714 23:44:31.723590 Set Vref, RX VrefLevel [Byte0]: 74
8715 23:44:31.726812 [Byte1]: 74
8716 23:44:31.730713
8717 23:44:31.730816 Set Vref, RX VrefLevel [Byte0]: 75
8718 23:44:31.734110 [Byte1]: 75
8719 23:44:31.738611
8720 23:44:31.738707 Final RX Vref Byte 0 = 57 to rank0
8721 23:44:31.741920 Final RX Vref Byte 1 = 56 to rank0
8722 23:44:31.745253 Final RX Vref Byte 0 = 57 to rank1
8723 23:44:31.748888 Final RX Vref Byte 1 = 56 to rank1==
8724 23:44:31.751963 Dram Type= 6, Freq= 0, CH_1, rank 0
8725 23:44:31.755486 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8726 23:44:31.758765 ==
8727 23:44:31.758849 DQS Delay:
8728 23:44:31.758912 DQS0 = 0, DQS1 = 0
8729 23:44:31.762793 DQM Delay:
8730 23:44:31.762878 DQM0 = 130, DQM1 = 124
8731 23:44:31.765537 DQ Delay:
8732 23:44:31.768677 DQ0 =134, DQ1 =124, DQ2 =118, DQ3 =128
8733 23:44:31.771910 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =126
8734 23:44:31.775608 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =118
8735 23:44:31.778563 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =132
8736 23:44:31.778649
8737 23:44:31.778712
8738 23:44:31.778771
8739 23:44:31.782019 [DramC_TX_OE_Calibration] TA2
8740 23:44:31.785785 Original DQ_B0 (3 6) =30, OEN = 27
8741 23:44:31.789638 Original DQ_B1 (3 6) =30, OEN = 27
8742 23:44:31.789720 24, 0x0, End_B0=24 End_B1=24
8743 23:44:31.792328 25, 0x0, End_B0=25 End_B1=25
8744 23:44:31.795668 26, 0x0, End_B0=26 End_B1=26
8745 23:44:31.798725 27, 0x0, End_B0=27 End_B1=27
8746 23:44:31.802671 28, 0x0, End_B0=28 End_B1=28
8747 23:44:31.802753 29, 0x0, End_B0=29 End_B1=29
8748 23:44:31.806209 30, 0x0, End_B0=30 End_B1=30
8749 23:44:31.809232 31, 0x4141, End_B0=30 End_B1=30
8750 23:44:31.812322 Byte0 end_step=30 best_step=27
8751 23:44:31.815637 Byte1 end_step=30 best_step=27
8752 23:44:31.815718 Byte0 TX OE(2T, 0.5T) = (3, 3)
8753 23:44:31.819156 Byte1 TX OE(2T, 0.5T) = (3, 3)
8754 23:44:31.819243
8755 23:44:31.819308
8756 23:44:31.829212 [DQSOSCAuto] RK0, (LSB)MR18= 0x13fe, (MSB)MR19= 0x302, tDQSOscB0 = 411 ps tDQSOscB1 = 400 ps
8757 23:44:31.832557 CH1 RK0: MR19=302, MR18=13FE
8758 23:44:31.835741 CH1_RK0: MR19=0x302, MR18=0x13FE, DQSOSC=400, MR23=63, INC=23, DEC=15
8759 23:44:31.839090
8760 23:44:31.842319 ----->DramcWriteLeveling(PI) begin...
8761 23:44:31.842404 ==
8762 23:44:31.845785 Dram Type= 6, Freq= 0, CH_1, rank 1
8763 23:44:31.848962 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8764 23:44:31.849082 ==
8765 23:44:31.852346 Write leveling (Byte 0): 24 => 24
8766 23:44:31.855764 Write leveling (Byte 1): 26 => 26
8767 23:44:31.858683 DramcWriteLeveling(PI) end<-----
8768 23:44:31.858768
8769 23:44:31.858831 ==
8770 23:44:31.862308 Dram Type= 6, Freq= 0, CH_1, rank 1
8771 23:44:31.865466 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8772 23:44:31.865548 ==
8773 23:44:31.868713 [Gating] SW mode calibration
8774 23:44:31.875515 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8775 23:44:31.882423 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8776 23:44:31.885641 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8777 23:44:31.889718 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8778 23:44:31.896301 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8779 23:44:31.898867 1 4 12 | B1->B0 | 2c2c 3434 | 1 1 | (1 1) (1 1)
8780 23:44:31.903030 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8781 23:44:31.905633 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8782 23:44:31.912109 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8783 23:44:31.915979 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8784 23:44:31.919496 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8785 23:44:31.925911 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8786 23:44:31.928887 1 5 8 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
8787 23:44:31.932150 1 5 12 | B1->B0 | 2d2d 2525 | 1 0 | (1 0) (1 0)
8788 23:44:31.939259 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8789 23:44:31.942343 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8790 23:44:31.945526 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8791 23:44:31.952120 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8792 23:44:31.955331 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8793 23:44:31.958598 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8794 23:44:31.965455 1 6 8 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
8795 23:44:31.969198 1 6 12 | B1->B0 | 3f3f 4646 | 1 0 | (0 0) (0 0)
8796 23:44:31.972129 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8797 23:44:31.979779 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8798 23:44:31.982388 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8799 23:44:31.985964 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8800 23:44:31.988771 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8801 23:44:31.996229 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8802 23:44:31.998777 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8803 23:44:32.002361 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8804 23:44:32.009143 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8805 23:44:32.012294 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 23:44:32.015449 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 23:44:32.022271 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 23:44:32.025358 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 23:44:32.028955 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8810 23:44:32.036025 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 23:44:32.038667 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8812 23:44:32.042427 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8813 23:44:32.049310 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8814 23:44:32.052679 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8815 23:44:32.055989 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8816 23:44:32.062410 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8817 23:44:32.065452 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8818 23:44:32.068959 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8819 23:44:32.075731 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8820 23:44:32.075862 Total UI for P1: 0, mck2ui 16
8821 23:44:32.081974 best dqsien dly found for B0: ( 1, 9, 6)
8822 23:44:32.085449 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8823 23:44:32.088528 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8824 23:44:32.092005 Total UI for P1: 0, mck2ui 16
8825 23:44:32.095408 best dqsien dly found for B1: ( 1, 9, 12)
8826 23:44:32.098770 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8827 23:44:32.102656 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8828 23:44:32.102760
8829 23:44:32.105363 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8830 23:44:32.111933 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8831 23:44:32.112049 [Gating] SW calibration Done
8832 23:44:32.112116 ==
8833 23:44:32.115235 Dram Type= 6, Freq= 0, CH_1, rank 1
8834 23:44:32.122015 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8835 23:44:32.122137 ==
8836 23:44:32.122206 RX Vref Scan: 0
8837 23:44:32.122267
8838 23:44:32.124878 RX Vref 0 -> 0, step: 1
8839 23:44:32.125017
8840 23:44:32.129452 RX Delay 0 -> 252, step: 8
8841 23:44:32.131893 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8842 23:44:32.135171 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8843 23:44:32.139449 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8844 23:44:32.145142 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8845 23:44:32.148326 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8846 23:44:32.151918 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8847 23:44:32.155656 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8848 23:44:32.158784 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8849 23:44:32.162166 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8850 23:44:32.168848 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8851 23:44:32.171836 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8852 23:44:32.175385 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8853 23:44:32.178550 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8854 23:44:32.182063 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8855 23:44:32.188635 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8856 23:44:32.192098 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8857 23:44:32.192196 ==
8858 23:44:32.195386 Dram Type= 6, Freq= 0, CH_1, rank 1
8859 23:44:32.198610 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8860 23:44:32.198707 ==
8861 23:44:32.202029 DQS Delay:
8862 23:44:32.202121 DQS0 = 0, DQS1 = 0
8863 23:44:32.202186 DQM Delay:
8864 23:44:32.205044 DQM0 = 133, DQM1 = 128
8865 23:44:32.205133 DQ Delay:
8866 23:44:32.209171 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =135
8867 23:44:32.212026 DQ4 =135, DQ5 =147, DQ6 =143, DQ7 =127
8868 23:44:32.215875 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8869 23:44:32.222062 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =139
8870 23:44:32.222186
8871 23:44:32.222254
8872 23:44:32.222314 ==
8873 23:44:32.225118 Dram Type= 6, Freq= 0, CH_1, rank 1
8874 23:44:32.229471 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8875 23:44:32.229571 ==
8876 23:44:32.229638
8877 23:44:32.229698
8878 23:44:32.232540 TX Vref Scan disable
8879 23:44:32.232622 == TX Byte 0 ==
8880 23:44:32.239234 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8881 23:44:32.242209 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8882 23:44:32.242304 == TX Byte 1 ==
8883 23:44:32.248926 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8884 23:44:32.252866 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8885 23:44:32.252969 ==
8886 23:44:32.255482 Dram Type= 6, Freq= 0, CH_1, rank 1
8887 23:44:32.259366 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8888 23:44:32.259460 ==
8889 23:44:32.274234
8890 23:44:32.277081 TX Vref early break, caculate TX vref
8891 23:44:32.279996 TX Vref=16, minBit 0, minWin=23, winSum=384
8892 23:44:32.283211 TX Vref=18, minBit 0, minWin=24, winSum=390
8893 23:44:32.286828 TX Vref=20, minBit 0, minWin=24, winSum=401
8894 23:44:32.289926 TX Vref=22, minBit 5, minWin=24, winSum=408
8895 23:44:32.294002 TX Vref=24, minBit 5, minWin=25, winSum=420
8896 23:44:32.300111 TX Vref=26, minBit 6, minWin=25, winSum=424
8897 23:44:32.303175 TX Vref=28, minBit 0, minWin=26, winSum=430
8898 23:44:32.306574 TX Vref=30, minBit 5, minWin=25, winSum=426
8899 23:44:32.311520 TX Vref=32, minBit 0, minWin=24, winSum=420
8900 23:44:32.313801 TX Vref=34, minBit 0, minWin=24, winSum=418
8901 23:44:32.316725 TX Vref=36, minBit 0, minWin=24, winSum=403
8902 23:44:32.323254 [TxChooseVref] Worse bit 0, Min win 26, Win sum 430, Final Vref 28
8903 23:44:32.323338
8904 23:44:32.326817 Final TX Range 0 Vref 28
8905 23:44:32.326899
8906 23:44:32.326962 ==
8907 23:44:32.329779 Dram Type= 6, Freq= 0, CH_1, rank 1
8908 23:44:32.332941 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8909 23:44:32.333058 ==
8910 23:44:32.333122
8911 23:44:32.333182
8912 23:44:32.336781 TX Vref Scan disable
8913 23:44:32.343555 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8914 23:44:32.343637 == TX Byte 0 ==
8915 23:44:32.347418 u2DelayCellOfst[0]=17 cells (5 PI)
8916 23:44:32.349885 u2DelayCellOfst[1]=14 cells (4 PI)
8917 23:44:32.353261 u2DelayCellOfst[2]=0 cells (0 PI)
8918 23:44:32.357394 u2DelayCellOfst[3]=7 cells (2 PI)
8919 23:44:32.360338 u2DelayCellOfst[4]=7 cells (2 PI)
8920 23:44:32.363065 u2DelayCellOfst[5]=21 cells (6 PI)
8921 23:44:32.366989 u2DelayCellOfst[6]=17 cells (5 PI)
8922 23:44:32.369920 u2DelayCellOfst[7]=3 cells (1 PI)
8923 23:44:32.373945 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8924 23:44:32.376886 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8925 23:44:32.379926 == TX Byte 1 ==
8926 23:44:32.380007 u2DelayCellOfst[8]=0 cells (0 PI)
8927 23:44:32.383750 u2DelayCellOfst[9]=3 cells (1 PI)
8928 23:44:32.386481 u2DelayCellOfst[10]=10 cells (3 PI)
8929 23:44:32.390639 u2DelayCellOfst[11]=3 cells (1 PI)
8930 23:44:32.393010 u2DelayCellOfst[12]=14 cells (4 PI)
8931 23:44:32.396859 u2DelayCellOfst[13]=14 cells (4 PI)
8932 23:44:32.399972 u2DelayCellOfst[14]=17 cells (5 PI)
8933 23:44:32.403397 u2DelayCellOfst[15]=14 cells (4 PI)
8934 23:44:32.406491 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8935 23:44:32.413391 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8936 23:44:32.413477 DramC Write-DBI on
8937 23:44:32.413541 ==
8938 23:44:32.416819 Dram Type= 6, Freq= 0, CH_1, rank 1
8939 23:44:32.420017 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8940 23:44:32.420100 ==
8941 23:44:32.423395
8942 23:44:32.423475
8943 23:44:32.423539 TX Vref Scan disable
8944 23:44:32.426996 == TX Byte 0 ==
8945 23:44:32.431048 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8946 23:44:32.433605 == TX Byte 1 ==
8947 23:44:32.436824 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8948 23:44:32.436922 DramC Write-DBI off
8949 23:44:32.436992
8950 23:44:32.440349 [DATLAT]
8951 23:44:32.440429 Freq=1600, CH1 RK1
8952 23:44:32.440493
8953 23:44:32.443446 DATLAT Default: 0xf
8954 23:44:32.443526 0, 0xFFFF, sum = 0
8955 23:44:32.447854 1, 0xFFFF, sum = 0
8956 23:44:32.447937 2, 0xFFFF, sum = 0
8957 23:44:32.451282 3, 0xFFFF, sum = 0
8958 23:44:32.451364 4, 0xFFFF, sum = 0
8959 23:44:32.453389 5, 0xFFFF, sum = 0
8960 23:44:32.453470 6, 0xFFFF, sum = 0
8961 23:44:32.456765 7, 0xFFFF, sum = 0
8962 23:44:32.456847 8, 0xFFFF, sum = 0
8963 23:44:32.460063 9, 0xFFFF, sum = 0
8964 23:44:32.463500 10, 0xFFFF, sum = 0
8965 23:44:32.463585 11, 0xFFFF, sum = 0
8966 23:44:32.467343 12, 0xFFFF, sum = 0
8967 23:44:32.467427 13, 0xFFFF, sum = 0
8968 23:44:32.470019 14, 0x0, sum = 1
8969 23:44:32.470101 15, 0x0, sum = 2
8970 23:44:32.473849 16, 0x0, sum = 3
8971 23:44:32.473933 17, 0x0, sum = 4
8972 23:44:32.473998 best_step = 15
8973 23:44:32.474058
8974 23:44:32.476789 ==
8975 23:44:32.480382 Dram Type= 6, Freq= 0, CH_1, rank 1
8976 23:44:32.483721 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8977 23:44:32.483808 ==
8978 23:44:32.483872 RX Vref Scan: 0
8979 23:44:32.483931
8980 23:44:32.486701 RX Vref 0 -> 0, step: 1
8981 23:44:32.486784
8982 23:44:32.490461 RX Delay 11 -> 252, step: 4
8983 23:44:32.493316 iDelay=195, Bit 0, Center 132 (83 ~ 182) 100
8984 23:44:32.496743 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
8985 23:44:32.503580 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
8986 23:44:32.506799 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
8987 23:44:32.510390 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
8988 23:44:32.513607 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
8989 23:44:32.517411 iDelay=195, Bit 6, Center 138 (87 ~ 190) 104
8990 23:44:32.523443 iDelay=195, Bit 7, Center 126 (75 ~ 178) 104
8991 23:44:32.526798 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8992 23:44:32.530247 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8993 23:44:32.533963 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8994 23:44:32.536661 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8995 23:44:32.543445 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8996 23:44:32.546721 iDelay=195, Bit 13, Center 134 (83 ~ 186) 104
8997 23:44:32.550698 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8998 23:44:32.554091 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
8999 23:44:32.554173 ==
9000 23:44:32.556946 Dram Type= 6, Freq= 0, CH_1, rank 1
9001 23:44:32.563426 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9002 23:44:32.563509 ==
9003 23:44:32.563573 DQS Delay:
9004 23:44:32.563632 DQS0 = 0, DQS1 = 0
9005 23:44:32.567314 DQM Delay:
9006 23:44:32.567407 DQM0 = 129, DQM1 = 126
9007 23:44:32.570145 DQ Delay:
9008 23:44:32.573353 DQ0 =132, DQ1 =124, DQ2 =118, DQ3 =126
9009 23:44:32.577093 DQ4 =130, DQ5 =144, DQ6 =138, DQ7 =126
9010 23:44:32.580452 DQ8 =114, DQ9 =112, DQ10 =126, DQ11 =120
9011 23:44:32.583694 DQ12 =132, DQ13 =134, DQ14 =136, DQ15 =136
9012 23:44:32.583790
9013 23:44:32.583855
9014 23:44:32.583914
9015 23:44:32.586585 [DramC_TX_OE_Calibration] TA2
9016 23:44:32.590066 Original DQ_B0 (3 6) =30, OEN = 27
9017 23:44:32.593493 Original DQ_B1 (3 6) =30, OEN = 27
9018 23:44:32.596582 24, 0x0, End_B0=24 End_B1=24
9019 23:44:32.596678 25, 0x0, End_B0=25 End_B1=25
9020 23:44:32.600501 26, 0x0, End_B0=26 End_B1=26
9021 23:44:32.603358 27, 0x0, End_B0=27 End_B1=27
9022 23:44:32.606805 28, 0x0, End_B0=28 End_B1=28
9023 23:44:32.606901 29, 0x0, End_B0=29 End_B1=29
9024 23:44:32.610766 30, 0x0, End_B0=30 End_B1=30
9025 23:44:32.613877 31, 0x4141, End_B0=30 End_B1=30
9026 23:44:32.617088 Byte0 end_step=30 best_step=27
9027 23:44:32.619820 Byte1 end_step=30 best_step=27
9028 23:44:32.623280 Byte0 TX OE(2T, 0.5T) = (3, 3)
9029 23:44:32.623374 Byte1 TX OE(2T, 0.5T) = (3, 3)
9030 23:44:32.626751
9031 23:44:32.626851
9032 23:44:32.633525 [DQSOSCAuto] RK1, (LSB)MR18= 0xd13, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 403 ps
9033 23:44:32.637110 CH1 RK1: MR19=303, MR18=D13
9034 23:44:32.643339 CH1_RK1: MR19=0x303, MR18=0xD13, DQSOSC=400, MR23=63, INC=23, DEC=15
9035 23:44:32.643448 [RxdqsGatingPostProcess] freq 1600
9036 23:44:32.650460 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9037 23:44:32.653216 best DQS0 dly(2T, 0.5T) = (1, 1)
9038 23:44:32.656643 best DQS1 dly(2T, 0.5T) = (1, 1)
9039 23:44:32.661667 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9040 23:44:32.663128 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9041 23:44:32.666797 best DQS0 dly(2T, 0.5T) = (1, 1)
9042 23:44:32.670540 best DQS1 dly(2T, 0.5T) = (1, 1)
9043 23:44:32.673286 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9044 23:44:32.676856 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9045 23:44:32.676943 Pre-setting of DQS Precalculation
9046 23:44:32.683113 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9047 23:44:32.689889 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9048 23:44:32.696749 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9049 23:44:32.696901
9050 23:44:32.697066
9051 23:44:32.699915 [Calibration Summary] 3200 Mbps
9052 23:44:32.703348 CH 0, Rank 0
9053 23:44:32.703486 SW Impedance : PASS
9054 23:44:32.706643 DUTY Scan : NO K
9055 23:44:32.709705 ZQ Calibration : PASS
9056 23:44:32.709843 Jitter Meter : NO K
9057 23:44:32.712936 CBT Training : PASS
9058 23:44:32.713069 Write leveling : PASS
9059 23:44:32.717092 RX DQS gating : PASS
9060 23:44:32.719855 RX DQ/DQS(RDDQC) : PASS
9061 23:44:32.720001 TX DQ/DQS : PASS
9062 23:44:32.722898 RX DATLAT : PASS
9063 23:44:32.727515 RX DQ/DQS(Engine): PASS
9064 23:44:32.727672 TX OE : PASS
9065 23:44:32.729869 All Pass.
9066 23:44:32.730013
9067 23:44:32.730141 CH 0, Rank 1
9068 23:44:32.733134 SW Impedance : PASS
9069 23:44:32.733273 DUTY Scan : NO K
9070 23:44:32.737191 ZQ Calibration : PASS
9071 23:44:32.740037 Jitter Meter : NO K
9072 23:44:32.740188 CBT Training : PASS
9073 23:44:32.743530 Write leveling : PASS
9074 23:44:32.746585 RX DQS gating : PASS
9075 23:44:32.746717 RX DQ/DQS(RDDQC) : PASS
9076 23:44:32.750308 TX DQ/DQS : PASS
9077 23:44:32.750434 RX DATLAT : PASS
9078 23:44:32.753304 RX DQ/DQS(Engine): PASS
9079 23:44:32.756492 TX OE : PASS
9080 23:44:32.756620 All Pass.
9081 23:44:32.756738
9082 23:44:32.756850 CH 1, Rank 0
9083 23:44:32.759700 SW Impedance : PASS
9084 23:44:32.763023 DUTY Scan : NO K
9085 23:44:32.763158 ZQ Calibration : PASS
9086 23:44:32.766390 Jitter Meter : NO K
9087 23:44:32.770054 CBT Training : PASS
9088 23:44:32.770182 Write leveling : PASS
9089 23:44:32.774055 RX DQS gating : PASS
9090 23:44:32.776250 RX DQ/DQS(RDDQC) : PASS
9091 23:44:32.776385 TX DQ/DQS : PASS
9092 23:44:32.780301 RX DATLAT : PASS
9093 23:44:32.782999 RX DQ/DQS(Engine): PASS
9094 23:44:32.783130 TX OE : PASS
9095 23:44:32.786717 All Pass.
9096 23:44:32.786845
9097 23:44:32.786966 CH 1, Rank 1
9098 23:44:32.790250 SW Impedance : PASS
9099 23:44:32.790378 DUTY Scan : NO K
9100 23:44:32.793306 ZQ Calibration : PASS
9101 23:44:32.796309 Jitter Meter : NO K
9102 23:44:32.796436 CBT Training : PASS
9103 23:44:32.799803 Write leveling : PASS
9104 23:44:32.799932 RX DQS gating : PASS
9105 23:44:32.803281 RX DQ/DQS(RDDQC) : PASS
9106 23:44:32.806738 TX DQ/DQS : PASS
9107 23:44:32.806870 RX DATLAT : PASS
9108 23:44:32.809587 RX DQ/DQS(Engine): PASS
9109 23:44:32.813133 TX OE : PASS
9110 23:44:32.813273 All Pass.
9111 23:44:32.813394
9112 23:44:32.816256 DramC Write-DBI on
9113 23:44:32.816385 PER_BANK_REFRESH: Hybrid Mode
9114 23:44:32.819896 TX_TRACKING: ON
9115 23:44:32.829788 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9116 23:44:32.836908 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9117 23:44:32.843273 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9118 23:44:32.846482 [FAST_K] Save calibration result to emmc
9119 23:44:32.850302 sync common calibartion params.
9120 23:44:32.853335 sync cbt_mode0:1, 1:1
9121 23:44:32.853415 dram_init: ddr_geometry: 2
9122 23:44:32.856934 dram_init: ddr_geometry: 2
9123 23:44:32.860557 dram_init: ddr_geometry: 2
9124 23:44:32.863082 0:dram_rank_size:100000000
9125 23:44:32.863195 1:dram_rank_size:100000000
9126 23:44:32.869898 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9127 23:44:32.873203 DFS_SHUFFLE_HW_MODE: ON
9128 23:44:32.876959 dramc_set_vcore_voltage set vcore to 725000
9129 23:44:32.877053 Read voltage for 1600, 0
9130 23:44:32.879738 Vio18 = 0
9131 23:44:32.879819 Vcore = 725000
9132 23:44:32.879882 Vdram = 0
9133 23:44:32.883217 Vddq = 0
9134 23:44:32.883298 Vmddr = 0
9135 23:44:32.887035 switch to 3200 Mbps bootup
9136 23:44:32.887117 [DramcRunTimeConfig]
9137 23:44:32.887180 PHYPLL
9138 23:44:32.889736 DPM_CONTROL_AFTERK: ON
9139 23:44:32.893327 PER_BANK_REFRESH: ON
9140 23:44:32.893410 REFRESH_OVERHEAD_REDUCTION: ON
9141 23:44:32.896547 CMD_PICG_NEW_MODE: OFF
9142 23:44:32.900536 XRTWTW_NEW_MODE: ON
9143 23:44:32.900618 XRTRTR_NEW_MODE: ON
9144 23:44:32.903649 TX_TRACKING: ON
9145 23:44:32.903730 RDSEL_TRACKING: OFF
9146 23:44:32.907132 DQS Precalculation for DVFS: ON
9147 23:44:32.907212 RX_TRACKING: OFF
9148 23:44:32.909962 HW_GATING DBG: ON
9149 23:44:32.910042 ZQCS_ENABLE_LP4: ON
9150 23:44:32.913654 RX_PICG_NEW_MODE: ON
9151 23:44:32.916899 TX_PICG_NEW_MODE: ON
9152 23:44:32.917012 ENABLE_RX_DCM_DPHY: ON
9153 23:44:32.920122 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9154 23:44:32.923178 DUMMY_READ_FOR_TRACKING: OFF
9155 23:44:32.926561 !!! SPM_CONTROL_AFTERK: OFF
9156 23:44:32.926653 !!! SPM could not control APHY
9157 23:44:32.929943 IMPEDANCE_TRACKING: ON
9158 23:44:32.933592 TEMP_SENSOR: ON
9159 23:44:32.933673 HW_SAVE_FOR_SR: OFF
9160 23:44:32.936295 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9161 23:44:32.939758 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9162 23:44:32.943812 Read ODT Tracking: ON
9163 23:44:32.943882 Refresh Rate DeBounce: ON
9164 23:44:32.946737 DFS_NO_QUEUE_FLUSH: ON
9165 23:44:32.950741 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9166 23:44:32.953339 ENABLE_DFS_RUNTIME_MRW: OFF
9167 23:44:32.953406 DDR_RESERVE_NEW_MODE: ON
9168 23:44:32.957402 MR_CBT_SWITCH_FREQ: ON
9169 23:44:32.959992 =========================
9170 23:44:32.977822 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9171 23:44:32.981120 dram_init: ddr_geometry: 2
9172 23:44:32.999458 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9173 23:44:33.002924 dram_init: dram init end (result: 0)
9174 23:44:33.009239 DRAM-K: Full calibration passed in 24577 msecs
9175 23:44:33.012605 MRC: failed to locate region type 0.
9176 23:44:33.012689 DRAM rank0 size:0x100000000,
9177 23:44:33.016042 DRAM rank1 size=0x100000000
9178 23:44:33.026173 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9179 23:44:33.032708 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9180 23:44:33.038962 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9181 23:44:33.046213 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9182 23:44:33.049539 DRAM rank0 size:0x100000000,
9183 23:44:33.052420 DRAM rank1 size=0x100000000
9184 23:44:33.052504 CBMEM:
9185 23:44:33.055829 IMD: root @ 0xfffff000 254 entries.
9186 23:44:33.059042 IMD: root @ 0xffffec00 62 entries.
9187 23:44:33.062364 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9188 23:44:33.065816 WARNING: RO_VPD is uninitialized or empty.
9189 23:44:33.072300 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9190 23:44:33.079903 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9191 23:44:33.092182 read SPI 0x42894 0xe01e: 6223 us, 9219 KB/s, 73.752 Mbps
9192 23:44:33.103917 BS: romstage times (exec / console): total (unknown) / 24081 ms
9193 23:44:33.104039
9194 23:44:33.104106
9195 23:44:33.113658 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9196 23:44:33.116775 ARM64: Exception handlers installed.
9197 23:44:33.120087 ARM64: Testing exception
9198 23:44:33.123359 ARM64: Done test exception
9199 23:44:33.123442 Enumerating buses...
9200 23:44:33.127054 Show all devs... Before device enumeration.
9201 23:44:33.130283 Root Device: enabled 1
9202 23:44:33.133845 CPU_CLUSTER: 0: enabled 1
9203 23:44:33.133928 CPU: 00: enabled 1
9204 23:44:33.137324 Compare with tree...
9205 23:44:33.137405 Root Device: enabled 1
9206 23:44:33.140120 CPU_CLUSTER: 0: enabled 1
9207 23:44:33.143482 CPU: 00: enabled 1
9208 23:44:33.143563 Root Device scanning...
9209 23:44:33.146654 scan_static_bus for Root Device
9210 23:44:33.150350 CPU_CLUSTER: 0 enabled
9211 23:44:33.153737 scan_static_bus for Root Device done
9212 23:44:33.156687 scan_bus: bus Root Device finished in 8 msecs
9213 23:44:33.156777 done
9214 23:44:33.163771 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9215 23:44:33.166778 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9216 23:44:33.173281 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9217 23:44:33.177908 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9218 23:44:33.180672 Allocating resources...
9219 23:44:33.180756 Reading resources...
9220 23:44:33.186602 Root Device read_resources bus 0 link: 0
9221 23:44:33.186688 DRAM rank0 size:0x100000000,
9222 23:44:33.190067 DRAM rank1 size=0x100000000
9223 23:44:33.193185 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9224 23:44:33.196590 CPU: 00 missing read_resources
9225 23:44:33.199622 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9226 23:44:33.206651 Root Device read_resources bus 0 link: 0 done
9227 23:44:33.206740 Done reading resources.
9228 23:44:33.213206 Show resources in subtree (Root Device)...After reading.
9229 23:44:33.216879 Root Device child on link 0 CPU_CLUSTER: 0
9230 23:44:33.219724 CPU_CLUSTER: 0 child on link 0 CPU: 00
9231 23:44:33.230015 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9232 23:44:33.230138 CPU: 00
9233 23:44:33.233636 Root Device assign_resources, bus 0 link: 0
9234 23:44:33.236389 CPU_CLUSTER: 0 missing set_resources
9235 23:44:33.240076 Root Device assign_resources, bus 0 link: 0 done
9236 23:44:33.243076 Done setting resources.
9237 23:44:33.249662 Show resources in subtree (Root Device)...After assigning values.
9238 23:44:33.253655 Root Device child on link 0 CPU_CLUSTER: 0
9239 23:44:33.256678 CPU_CLUSTER: 0 child on link 0 CPU: 00
9240 23:44:33.266183 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9241 23:44:33.266297 CPU: 00
9242 23:44:33.269828 Done allocating resources.
9243 23:44:33.272852 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9244 23:44:33.276366 Enabling resources...
9245 23:44:33.276483 done.
9246 23:44:33.283938 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9247 23:44:33.284032 Initializing devices...
9248 23:44:33.288037 Root Device init
9249 23:44:33.288121 init hardware done!
9250 23:44:33.290488 0x00000018: ctrlr->caps
9251 23:44:33.293468 52.000 MHz: ctrlr->f_max
9252 23:44:33.293556 0.400 MHz: ctrlr->f_min
9253 23:44:33.296890 0x40ff8080: ctrlr->voltages
9254 23:44:33.297002 sclk: 390625
9255 23:44:33.299846 Bus Width = 1
9256 23:44:33.299927 sclk: 390625
9257 23:44:33.299989 Bus Width = 1
9258 23:44:33.303803 Early init status = 3
9259 23:44:33.306762 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9260 23:44:33.312131 in-header: 03 fc 00 00 01 00 00 00
9261 23:44:33.315895 in-data: 00
9262 23:44:33.318728 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9263 23:44:33.324239 in-header: 03 fd 00 00 00 00 00 00
9264 23:44:33.327524 in-data:
9265 23:44:33.330906 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9266 23:44:33.335068 in-header: 03 fc 00 00 01 00 00 00
9267 23:44:33.338498 in-data: 00
9268 23:44:33.342063 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9269 23:44:33.347439 in-header: 03 fd 00 00 00 00 00 00
9270 23:44:33.351073 in-data:
9271 23:44:33.354022 [SSUSB] Setting up USB HOST controller...
9272 23:44:33.357571 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9273 23:44:33.360597 [SSUSB] phy power-on done.
9274 23:44:33.364067 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9275 23:44:33.370990 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9276 23:44:33.374188 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9277 23:44:33.380772 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9278 23:44:33.388511 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9279 23:44:33.394113 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9280 23:44:33.401248 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9281 23:44:33.407397 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9282 23:44:33.407498 SPM: binary array size = 0x9dc
9283 23:44:33.414400 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9284 23:44:33.421119 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9285 23:44:33.427469 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9286 23:44:33.430822 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9287 23:44:33.433852 configure_display: Starting display init
9288 23:44:33.470719 anx7625_power_on_init: Init interface.
9289 23:44:33.474008 anx7625_disable_pd_protocol: Disabled PD feature.
9290 23:44:33.477991 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9291 23:44:33.505897 anx7625_start_dp_work: Secure OCM version=00
9292 23:44:33.508686 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9293 23:44:33.523061 sp_tx_get_edid_block: EDID Block = 1
9294 23:44:33.625924 Extracted contents:
9295 23:44:33.629176 header: 00 ff ff ff ff ff ff 00
9296 23:44:33.632246 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9297 23:44:33.635888 version: 01 04
9298 23:44:33.639177 basic params: 95 1f 11 78 0a
9299 23:44:33.642504 chroma info: 76 90 94 55 54 90 27 21 50 54
9300 23:44:33.645860 established: 00 00 00
9301 23:44:33.649794 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9302 23:44:33.656297 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9303 23:44:33.662522 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9304 23:44:33.669234 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9305 23:44:33.675825 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9306 23:44:33.679627 extensions: 00
9307 23:44:33.679725 checksum: fb
9308 23:44:33.679789
9309 23:44:33.682283 Manufacturer: IVO Model 57d Serial Number 0
9310 23:44:33.686061 Made week 0 of 2020
9311 23:44:33.686143 EDID version: 1.4
9312 23:44:33.689336 Digital display
9313 23:44:33.692756 6 bits per primary color channel
9314 23:44:33.692843 DisplayPort interface
9315 23:44:33.696727 Maximum image size: 31 cm x 17 cm
9316 23:44:33.696810 Gamma: 220%
9317 23:44:33.699284 Check DPMS levels
9318 23:44:33.702860 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9319 23:44:33.706109 First detailed timing is preferred timing
9320 23:44:33.709192 Established timings supported:
9321 23:44:33.712572 Standard timings supported:
9322 23:44:33.712656 Detailed timings
9323 23:44:33.719414 Hex of detail: 383680a07038204018303c0035ae10000019
9324 23:44:33.722829 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9325 23:44:33.725960 0780 0798 07c8 0820 hborder 0
9326 23:44:33.732468 0438 043b 0447 0458 vborder 0
9327 23:44:33.732573 -hsync -vsync
9328 23:44:33.736234 Did detailed timing
9329 23:44:33.739141 Hex of detail: 000000000000000000000000000000000000
9330 23:44:33.742291 Manufacturer-specified data, tag 0
9331 23:44:33.749123 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9332 23:44:33.749232 ASCII string: InfoVision
9333 23:44:33.755926 Hex of detail: 000000fe00523134304e574635205248200a
9334 23:44:33.756037 ASCII string: R140NWF5 RH
9335 23:44:33.758953 Checksum
9336 23:44:33.759037 Checksum: 0xfb (valid)
9337 23:44:33.765714 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9338 23:44:33.765814 DSI data_rate: 832800000 bps
9339 23:44:33.773442 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9340 23:44:33.776699 anx7625_parse_edid: pixelclock(138800).
9341 23:44:33.780334 hactive(1920), hsync(48), hfp(24), hbp(88)
9342 23:44:33.783776 vactive(1080), vsync(12), vfp(3), vbp(17)
9343 23:44:33.786858 anx7625_dsi_config: config dsi.
9344 23:44:33.793742 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9345 23:44:33.807917 anx7625_dsi_config: success to config DSI
9346 23:44:33.810889 anx7625_dp_start: MIPI phy setup OK.
9347 23:44:33.815335 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9348 23:44:33.817766 mtk_ddp_mode_set invalid vrefresh 60
9349 23:44:33.821556 main_disp_path_setup
9350 23:44:33.821646 ovl_layer_smi_id_en
9351 23:44:33.824922 ovl_layer_smi_id_en
9352 23:44:33.825046 ccorr_config
9353 23:44:33.825144 aal_config
9354 23:44:33.828601 gamma_config
9355 23:44:33.828683 postmask_config
9356 23:44:33.831061 dither_config
9357 23:44:33.834732 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9358 23:44:33.841671 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9359 23:44:33.845113 Root Device init finished in 555 msecs
9360 23:44:33.845207 CPU_CLUSTER: 0 init
9361 23:44:33.854265 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9362 23:44:33.857997 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9363 23:44:33.861331 APU_MBOX 0x190000b0 = 0x10001
9364 23:44:33.864524 APU_MBOX 0x190001b0 = 0x10001
9365 23:44:33.869180 APU_MBOX 0x190005b0 = 0x10001
9366 23:44:33.871033 APU_MBOX 0x190006b0 = 0x10001
9367 23:44:33.874443 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9368 23:44:33.887021 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9369 23:44:33.899162 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9370 23:44:33.905899 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9371 23:44:33.917543 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9372 23:44:33.927090 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9373 23:44:33.930285 CPU_CLUSTER: 0 init finished in 81 msecs
9374 23:44:33.933675 Devices initialized
9375 23:44:33.938432 Show all devs... After init.
9376 23:44:33.938529 Root Device: enabled 1
9377 23:44:33.940007 CPU_CLUSTER: 0: enabled 1
9378 23:44:33.943453 CPU: 00: enabled 1
9379 23:44:33.946631 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9380 23:44:33.950475 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9381 23:44:33.953606 ELOG: NV offset 0x57f000 size 0x1000
9382 23:44:33.960598 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9383 23:44:33.966907 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9384 23:44:33.970196 ELOG: Event(17) added with size 13 at 2024-06-04 23:44:35 UTC
9385 23:44:33.973271 out: cmd=0x121: 03 db 21 01 00 00 00 00
9386 23:44:33.977746 in-header: 03 d5 00 00 2c 00 00 00
9387 23:44:33.991039 in-data: 8a 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9388 23:44:33.998131 ELOG: Event(A1) added with size 10 at 2024-06-04 23:44:35 UTC
9389 23:44:34.004820 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9390 23:44:34.011022 ELOG: Event(A0) added with size 9 at 2024-06-04 23:44:35 UTC
9391 23:44:34.014457 elog_add_boot_reason: Logged dev mode boot
9392 23:44:34.018282 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9393 23:44:34.021430 Finalize devices...
9394 23:44:34.021519 Devices finalized
9395 23:44:34.028473 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9396 23:44:34.031369 Writing coreboot table at 0xffe64000
9397 23:44:34.034457 0. 000000000010a000-0000000000113fff: RAMSTAGE
9398 23:44:34.038072 1. 0000000040000000-00000000400fffff: RAM
9399 23:44:34.041324 2. 0000000040100000-000000004032afff: RAMSTAGE
9400 23:44:34.048204 3. 000000004032b000-00000000545fffff: RAM
9401 23:44:34.051102 4. 0000000054600000-000000005465ffff: BL31
9402 23:44:34.054444 5. 0000000054660000-00000000ffe63fff: RAM
9403 23:44:34.057900 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9404 23:44:34.065338 7. 0000000100000000-000000023fffffff: RAM
9405 23:44:34.065449 Passing 5 GPIOs to payload:
9406 23:44:34.071171 NAME | PORT | POLARITY | VALUE
9407 23:44:34.074588 EC in RW | 0x000000aa | low | undefined
9408 23:44:34.080959 EC interrupt | 0x00000005 | low | undefined
9409 23:44:34.084583 TPM interrupt | 0x000000ab | high | undefined
9410 23:44:34.087810 SD card detect | 0x00000011 | high | undefined
9411 23:44:34.094643 speaker enable | 0x00000093 | high | undefined
9412 23:44:34.098578 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9413 23:44:34.101280 in-header: 03 f9 00 00 02 00 00 00
9414 23:44:34.101371 in-data: 02 00
9415 23:44:34.104380 ADC[4]: Raw value=899114 ID=7
9416 23:44:34.108369 ADC[3]: Raw value=213336 ID=1
9417 23:44:34.108456 RAM Code: 0x71
9418 23:44:34.111111 ADC[6]: Raw value=74557 ID=0
9419 23:44:34.114910 ADC[5]: Raw value=212229 ID=1
9420 23:44:34.114997 SKU Code: 0x1
9421 23:44:34.121641 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 6bbf
9422 23:44:34.124511 coreboot table: 964 bytes.
9423 23:44:34.128744 IMD ROOT 0. 0xfffff000 0x00001000
9424 23:44:34.131555 IMD SMALL 1. 0xffffe000 0x00001000
9425 23:44:34.134458 RO MCACHE 2. 0xffffc000 0x00001104
9426 23:44:34.137899 CONSOLE 3. 0xfff7c000 0x00080000
9427 23:44:34.141394 FMAP 4. 0xfff7b000 0x00000452
9428 23:44:34.144798 TIME STAMP 5. 0xfff7a000 0x00000910
9429 23:44:34.148197 VBOOT WORK 6. 0xfff66000 0x00014000
9430 23:44:34.151704 RAMOOPS 7. 0xffe66000 0x00100000
9431 23:44:34.154399 COREBOOT 8. 0xffe64000 0x00002000
9432 23:44:34.154484 IMD small region:
9433 23:44:34.157647 IMD ROOT 0. 0xffffec00 0x00000400
9434 23:44:34.161695 VPD 1. 0xffffeb80 0x0000006c
9435 23:44:34.164248 MMC STATUS 2. 0xffffeb60 0x00000004
9436 23:44:34.171379 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9437 23:44:34.171493 Probing TPM: done!
9438 23:44:34.178645 Connected to device vid:did:rid of 1ae0:0028:00
9439 23:44:34.185413 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9440 23:44:34.188151 Initialized TPM device CR50 revision 0
9441 23:44:34.191808 Checking cr50 for pending updates
9442 23:44:34.197566 Reading cr50 TPM mode
9443 23:44:34.206220 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9444 23:44:34.212537 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9445 23:44:34.252815 read SPI 0x3990ec 0x4f1b0: 34846 us, 9298 KB/s, 74.384 Mbps
9446 23:44:34.256313 Checking segment from ROM address 0x40100000
9447 23:44:34.259157 Checking segment from ROM address 0x4010001c
9448 23:44:34.266308 Loading segment from ROM address 0x40100000
9449 23:44:34.266423 code (compression=0)
9450 23:44:34.273234 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9451 23:44:34.283571 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9452 23:44:34.283714 it's not compressed!
9453 23:44:34.289294 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9454 23:44:34.292640 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9455 23:44:34.313229 Loading segment from ROM address 0x4010001c
9456 23:44:34.313377 Entry Point 0x80000000
9457 23:44:34.316443 Loaded segments
9458 23:44:34.319568 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9459 23:44:34.326488 Jumping to boot code at 0x80000000(0xffe64000)
9460 23:44:34.333458 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9461 23:44:34.339677 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9462 23:44:34.347650 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9463 23:44:34.351450 Checking segment from ROM address 0x40100000
9464 23:44:34.354659 Checking segment from ROM address 0x4010001c
9465 23:44:34.360677 Loading segment from ROM address 0x40100000
9466 23:44:34.360778 code (compression=1)
9467 23:44:34.367338 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9468 23:44:34.377680 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9469 23:44:34.377835 using LZMA
9470 23:44:34.386262 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9471 23:44:34.392618 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9472 23:44:34.396136 Loading segment from ROM address 0x4010001c
9473 23:44:34.396225 Entry Point 0x54601000
9474 23:44:34.399341 Loaded segments
9475 23:44:34.402710 NOTICE: MT8192 bl31_setup
9476 23:44:34.409815 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9477 23:44:34.412727 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9478 23:44:34.416349 WARNING: region 0:
9479 23:44:34.419687 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9480 23:44:34.419775 WARNING: region 1:
9481 23:44:34.426139 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9482 23:44:34.426236 WARNING: region 2:
9483 23:44:34.432732 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9484 23:44:34.436218 WARNING: region 3:
9485 23:44:34.439769 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9486 23:44:34.443027 WARNING: region 4:
9487 23:44:34.446164 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9488 23:44:34.449584 WARNING: region 5:
9489 23:44:34.453545 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9490 23:44:34.456533 WARNING: region 6:
9491 23:44:34.460448 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9492 23:44:34.460553 WARNING: region 7:
9493 23:44:34.466645 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9494 23:44:34.473348 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9495 23:44:34.476678 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9496 23:44:34.480019 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9497 23:44:34.486500 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9498 23:44:34.489713 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9499 23:44:34.493355 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9500 23:44:34.499836 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9501 23:44:34.503552 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9502 23:44:34.506331 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9503 23:44:34.513167 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9504 23:44:34.516482 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9505 23:44:34.519611 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9506 23:44:34.526920 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9507 23:44:34.530531 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9508 23:44:34.536662 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9509 23:44:34.539891 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9510 23:44:34.543565 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9511 23:44:34.550336 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9512 23:44:34.553154 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9513 23:44:34.556831 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9514 23:44:34.563276 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9515 23:44:34.566749 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9516 23:44:34.573537 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9517 23:44:34.576707 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9518 23:44:34.581082 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9519 23:44:34.586980 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9520 23:44:34.590292 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9521 23:44:34.593999 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9522 23:44:34.601114 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9523 23:44:34.604162 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9524 23:44:34.611206 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9525 23:44:34.613699 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9526 23:44:34.617372 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9527 23:44:34.620687 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9528 23:44:34.627491 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9529 23:44:34.631094 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9530 23:44:34.633819 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9531 23:44:34.637014 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9532 23:44:34.643663 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9533 23:44:34.647027 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9534 23:44:34.650960 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9535 23:44:34.653731 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9536 23:44:34.660737 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9537 23:44:34.663960 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9538 23:44:34.667792 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9539 23:44:34.670941 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9540 23:44:34.677528 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9541 23:44:34.681130 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9542 23:44:34.684311 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9543 23:44:34.691314 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9544 23:44:34.694365 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9545 23:44:34.700918 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9546 23:44:34.704194 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9547 23:44:34.708094 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9548 23:44:34.714799 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9549 23:44:34.718038 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9550 23:44:34.724678 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9551 23:44:34.727784 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9552 23:44:34.731007 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9553 23:44:34.738371 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9554 23:44:34.741174 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9555 23:44:34.747938 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9556 23:44:34.751159 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9557 23:44:34.757909 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9558 23:44:34.761127 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9559 23:44:34.764765 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9560 23:44:34.771351 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9561 23:44:34.774737 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9562 23:44:34.781696 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9563 23:44:34.784608 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9564 23:44:34.791649 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9565 23:44:34.795186 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9566 23:44:34.798375 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9567 23:44:34.805131 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9568 23:44:34.808548 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9569 23:44:34.814803 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9570 23:44:34.818836 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9571 23:44:34.825100 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9572 23:44:34.828634 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9573 23:44:34.831526 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9574 23:44:34.838377 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9575 23:44:34.842051 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9576 23:44:34.848811 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9577 23:44:34.852122 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9578 23:44:34.855161 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9579 23:44:34.862176 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9580 23:44:34.865207 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9581 23:44:34.871762 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9582 23:44:34.875343 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9583 23:44:34.881821 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9584 23:44:34.885527 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9585 23:44:34.888694 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9586 23:44:34.895772 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9587 23:44:34.899336 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9588 23:44:34.905720 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9589 23:44:34.908873 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9590 23:44:34.912157 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9591 23:44:34.919232 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9592 23:44:34.922209 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9593 23:44:34.926134 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9594 23:44:34.929573 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9595 23:44:34.935870 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9596 23:44:34.939199 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9597 23:44:34.945890 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9598 23:44:34.949192 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9599 23:44:34.953319 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9600 23:44:34.958998 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9601 23:44:34.962751 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9602 23:44:34.969258 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9603 23:44:34.973342 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9604 23:44:34.975904 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9605 23:44:34.982904 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9606 23:44:34.986709 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9607 23:44:34.989754 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9608 23:44:34.996012 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9609 23:44:34.999486 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9610 23:44:35.003159 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9611 23:44:35.010127 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9612 23:44:35.012920 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9613 23:44:35.016473 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9614 23:44:35.020241 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9615 23:44:35.026403 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9616 23:44:35.030011 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9617 23:44:35.032917 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9618 23:44:35.040661 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9619 23:44:35.043641 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9620 23:44:35.047085 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9621 23:44:35.053254 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9622 23:44:35.056528 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9623 23:44:35.060386 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9624 23:44:35.066672 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9625 23:44:35.070588 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9626 23:44:35.073408 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9627 23:44:35.080447 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9628 23:44:35.084157 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9629 23:44:35.090738 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9630 23:44:35.093445 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9631 23:44:35.096866 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9632 23:44:35.103689 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9633 23:44:35.107440 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9634 23:44:35.114026 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9635 23:44:35.117592 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9636 23:44:35.120376 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9637 23:44:35.126964 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9638 23:44:35.130420 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9639 23:44:35.133885 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9640 23:44:35.140580 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9641 23:44:35.144568 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9642 23:44:35.150563 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9643 23:44:35.153993 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9644 23:44:35.157476 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9645 23:44:35.164200 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9646 23:44:35.167990 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9647 23:44:35.170890 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9648 23:44:35.177873 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9649 23:44:35.181221 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9650 23:44:35.188125 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9651 23:44:35.191178 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9652 23:44:35.194754 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9653 23:44:35.200815 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9654 23:44:35.204193 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9655 23:44:35.207657 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9656 23:44:35.214501 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9657 23:44:35.217854 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9658 23:44:35.224502 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9659 23:44:35.227531 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9660 23:44:35.230932 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9661 23:44:35.238477 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9662 23:44:35.241290 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9663 23:44:35.247552 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9664 23:44:35.251173 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9665 23:44:35.254585 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9666 23:44:35.260835 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9667 23:44:35.264260 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9668 23:44:35.268132 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9669 23:44:35.274208 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9670 23:44:35.277748 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9671 23:44:35.284500 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9672 23:44:35.288086 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9673 23:44:35.291158 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9674 23:44:35.298062 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9675 23:44:35.301084 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9676 23:44:35.304853 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9677 23:44:35.310887 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9678 23:44:35.314844 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9679 23:44:35.321084 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9680 23:44:35.324773 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9681 23:44:35.327653 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9682 23:44:35.334299 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9683 23:44:35.338011 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9684 23:44:35.344259 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9685 23:44:35.347713 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9686 23:44:35.354379 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9687 23:44:35.357734 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9688 23:44:35.361110 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9689 23:44:35.368060 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9690 23:44:35.370935 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9691 23:44:35.377780 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9692 23:44:35.380955 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9693 23:44:35.384384 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9694 23:44:35.390963 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9695 23:44:35.394746 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9696 23:44:35.401479 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9697 23:44:35.404356 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9698 23:44:35.408406 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9699 23:44:35.414831 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9700 23:44:35.418293 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9701 23:44:35.424490 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9702 23:44:35.427780 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9703 23:44:35.430774 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9704 23:44:35.437588 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9705 23:44:35.442480 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9706 23:44:35.447620 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9707 23:44:35.450792 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9708 23:44:35.454350 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9709 23:44:35.461282 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9710 23:44:35.464648 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9711 23:44:35.470991 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9712 23:44:35.474728 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9713 23:44:35.481599 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9714 23:44:35.485097 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9715 23:44:35.487758 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9716 23:44:35.494868 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9717 23:44:35.497722 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9718 23:44:35.504830 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9719 23:44:35.507488 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9720 23:44:35.511445 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9721 23:44:35.517905 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9722 23:44:35.521473 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9723 23:44:35.524846 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9724 23:44:35.531086 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9725 23:44:35.534450 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9726 23:44:35.537819 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9727 23:44:35.541191 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9728 23:44:35.548024 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9729 23:44:35.551361 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9730 23:44:35.554807 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9731 23:44:35.561070 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9732 23:44:35.564616 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9733 23:44:35.568563 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9734 23:44:35.575227 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9735 23:44:35.578020 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9736 23:44:35.584827 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9737 23:44:35.588068 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9738 23:44:35.591463 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9739 23:44:35.597986 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9740 23:44:35.601783 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9741 23:44:35.605140 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9742 23:44:35.611275 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9743 23:44:35.614653 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9744 23:44:35.618686 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9745 23:44:35.624783 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9746 23:44:35.628623 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9747 23:44:35.631642 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9748 23:44:35.638713 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9749 23:44:35.641707 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9750 23:44:35.648801 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9751 23:44:35.651748 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9752 23:44:35.655060 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9753 23:44:35.658455 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9754 23:44:35.665236 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9755 23:44:35.668945 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9756 23:44:35.675714 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9757 23:44:35.678322 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9758 23:44:35.682036 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9759 23:44:35.689292 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9760 23:44:35.692167 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9761 23:44:35.695099 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9762 23:44:35.701995 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9763 23:44:35.705525 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9764 23:44:35.708913 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9765 23:44:35.711741 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9766 23:44:35.715747 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9767 23:44:35.722359 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9768 23:44:35.725329 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9769 23:44:35.729039 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9770 23:44:35.731810 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9771 23:44:35.738487 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9772 23:44:35.742056 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9773 23:44:35.745742 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9774 23:44:35.752093 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9775 23:44:35.755536 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9776 23:44:35.758394 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9777 23:44:35.765140 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9778 23:44:35.768697 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9779 23:44:35.771732 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9780 23:44:35.779010 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9781 23:44:35.782584 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9782 23:44:35.788736 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9783 23:44:35.792361 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9784 23:44:35.795515 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9785 23:44:35.801957 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9786 23:44:35.805314 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9787 23:44:35.812051 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9788 23:44:35.815094 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9789 23:44:35.822487 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9790 23:44:35.825211 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9791 23:44:35.828503 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9792 23:44:35.835115 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9793 23:44:35.838540 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9794 23:44:35.845701 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9795 23:44:35.848386 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9796 23:44:35.852030 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9797 23:44:35.858765 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9798 23:44:35.862323 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9799 23:44:35.865452 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9800 23:44:35.872449 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9801 23:44:35.875616 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9802 23:44:35.881726 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9803 23:44:35.885725 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9804 23:44:35.892203 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9805 23:44:35.896430 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9806 23:44:35.898683 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9807 23:44:35.905678 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9808 23:44:35.909302 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9809 23:44:35.912190 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9810 23:44:35.919071 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9811 23:44:35.922005 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9812 23:44:35.928962 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9813 23:44:35.932159 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9814 23:44:35.939356 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9815 23:44:35.942867 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9816 23:44:35.945431 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9817 23:44:35.952795 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9818 23:44:35.956557 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9819 23:44:35.962221 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9820 23:44:35.965572 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9821 23:44:35.969172 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9822 23:44:35.975646 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9823 23:44:35.979322 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9824 23:44:35.982429 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9825 23:44:35.988874 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9826 23:44:35.992323 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9827 23:44:35.999999 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9828 23:44:36.002634 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9829 23:44:36.005663 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9830 23:44:36.012541 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9831 23:44:36.015904 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9832 23:44:36.022462 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9833 23:44:36.025608 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9834 23:44:36.029228 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9835 23:44:36.036677 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9836 23:44:36.039340 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9837 23:44:36.046402 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9838 23:44:36.048843 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9839 23:44:36.052467 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9840 23:44:36.059375 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9841 23:44:36.063004 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9842 23:44:36.068725 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9843 23:44:36.072190 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9844 23:44:36.079400 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9845 23:44:36.082880 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9846 23:44:36.085685 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9847 23:44:36.092283 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9848 23:44:36.096136 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9849 23:44:36.102041 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9850 23:44:36.105993 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9851 23:44:36.109415 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9852 23:44:36.115449 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9853 23:44:36.119195 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9854 23:44:36.125633 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9855 23:44:36.128759 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9856 23:44:36.135888 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9857 23:44:36.139162 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9858 23:44:36.142324 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9859 23:44:36.149205 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9860 23:44:36.152516 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9861 23:44:36.159005 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9862 23:44:36.162741 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9863 23:44:36.165570 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9864 23:44:36.172302 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9865 23:44:36.175679 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9866 23:44:36.182575 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9867 23:44:36.185549 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9868 23:44:36.192938 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9869 23:44:36.195820 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9870 23:44:36.202706 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9871 23:44:36.206000 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9872 23:44:36.209875 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9873 23:44:36.216079 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9874 23:44:36.220065 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9875 23:44:36.225805 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9876 23:44:36.228938 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9877 23:44:36.235829 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9878 23:44:36.239449 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9879 23:44:36.242271 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9880 23:44:36.249706 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9881 23:44:36.252728 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9882 23:44:36.259700 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9883 23:44:36.262652 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9884 23:44:36.269364 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9885 23:44:36.272950 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9886 23:44:36.275657 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9887 23:44:36.282400 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9888 23:44:36.286312 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9889 23:44:36.292689 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9890 23:44:36.296121 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9891 23:44:36.302849 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9892 23:44:36.305762 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9893 23:44:36.309316 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9894 23:44:36.316391 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9895 23:44:36.319101 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9896 23:44:36.328102 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9897 23:44:36.328898 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9898 23:44:36.332073 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9899 23:44:36.339291 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9900 23:44:36.342502 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9901 23:44:36.349185 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9902 23:44:36.352300 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9903 23:44:36.359007 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9904 23:44:36.362456 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9905 23:44:36.369043 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9906 23:44:36.372274 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9907 23:44:36.379646 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9908 23:44:36.382425 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9909 23:44:36.389707 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9910 23:44:36.392732 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9911 23:44:36.395939 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9912 23:44:36.402971 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9913 23:44:36.406212 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9914 23:44:36.412937 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9915 23:44:36.416165 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9916 23:44:36.422852 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9917 23:44:36.426077 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9918 23:44:36.433134 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9919 23:44:36.436485 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9920 23:44:36.443615 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9921 23:44:36.445926 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9922 23:44:36.452700 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9923 23:44:36.456706 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9924 23:44:36.462992 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9925 23:44:36.466848 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9926 23:44:36.472422 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9927 23:44:36.476224 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9928 23:44:36.482842 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9929 23:44:36.482951 INFO: [APUAPC] vio 0
9930 23:44:36.488951 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9931 23:44:36.492878 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9932 23:44:36.496406 INFO: [APUAPC] D0_APC_0: 0x400510
9933 23:44:36.499665 INFO: [APUAPC] D0_APC_1: 0x0
9934 23:44:36.502667 INFO: [APUAPC] D0_APC_2: 0x1540
9935 23:44:36.505935 INFO: [APUAPC] D0_APC_3: 0x0
9936 23:44:36.509386 INFO: [APUAPC] D1_APC_0: 0xffffffff
9937 23:44:36.513322 INFO: [APUAPC] D1_APC_1: 0xffffffff
9938 23:44:36.516084 INFO: [APUAPC] D1_APC_2: 0x3fffff
9939 23:44:36.519665 INFO: [APUAPC] D1_APC_3: 0x0
9940 23:44:36.523082 INFO: [APUAPC] D2_APC_0: 0xffffffff
9941 23:44:36.526228 INFO: [APUAPC] D2_APC_1: 0xffffffff
9942 23:44:36.529359 INFO: [APUAPC] D2_APC_2: 0x3fffff
9943 23:44:36.529447 INFO: [APUAPC] D2_APC_3: 0x0
9944 23:44:36.532903 INFO: [APUAPC] D3_APC_0: 0xffffffff
9945 23:44:36.540668 INFO: [APUAPC] D3_APC_1: 0xffffffff
9946 23:44:36.542833 INFO: [APUAPC] D3_APC_2: 0x3fffff
9947 23:44:36.542922 INFO: [APUAPC] D3_APC_3: 0x0
9948 23:44:36.546113 INFO: [APUAPC] D4_APC_0: 0xffffffff
9949 23:44:36.550186 INFO: [APUAPC] D4_APC_1: 0xffffffff
9950 23:44:36.552711 INFO: [APUAPC] D4_APC_2: 0x3fffff
9951 23:44:36.556537 INFO: [APUAPC] D4_APC_3: 0x0
9952 23:44:36.560241 INFO: [APUAPC] D5_APC_0: 0xffffffff
9953 23:44:36.563048 INFO: [APUAPC] D5_APC_1: 0xffffffff
9954 23:44:36.566327 INFO: [APUAPC] D5_APC_2: 0x3fffff
9955 23:44:36.569359 INFO: [APUAPC] D5_APC_3: 0x0
9956 23:44:36.573034 INFO: [APUAPC] D6_APC_0: 0xffffffff
9957 23:44:36.576130 INFO: [APUAPC] D6_APC_1: 0xffffffff
9958 23:44:36.579335 INFO: [APUAPC] D6_APC_2: 0x3fffff
9959 23:44:36.583391 INFO: [APUAPC] D6_APC_3: 0x0
9960 23:44:36.586581 INFO: [APUAPC] D7_APC_0: 0xffffffff
9961 23:44:36.589770 INFO: [APUAPC] D7_APC_1: 0xffffffff
9962 23:44:36.592730 INFO: [APUAPC] D7_APC_2: 0x3fffff
9963 23:44:36.596505 INFO: [APUAPC] D7_APC_3: 0x0
9964 23:44:36.599873 INFO: [APUAPC] D8_APC_0: 0xffffffff
9965 23:44:36.603067 INFO: [APUAPC] D8_APC_1: 0xffffffff
9966 23:44:36.606812 INFO: [APUAPC] D8_APC_2: 0x3fffff
9967 23:44:36.610059 INFO: [APUAPC] D8_APC_3: 0x0
9968 23:44:36.613027 INFO: [APUAPC] D9_APC_0: 0xffffffff
9969 23:44:36.616065 INFO: [APUAPC] D9_APC_1: 0xffffffff
9970 23:44:36.619658 INFO: [APUAPC] D9_APC_2: 0x3fffff
9971 23:44:36.623322 INFO: [APUAPC] D9_APC_3: 0x0
9972 23:44:36.626381 INFO: [APUAPC] D10_APC_0: 0xffffffff
9973 23:44:36.629256 INFO: [APUAPC] D10_APC_1: 0xffffffff
9974 23:44:36.632971 INFO: [APUAPC] D10_APC_2: 0x3fffff
9975 23:44:36.636259 INFO: [APUAPC] D10_APC_3: 0x0
9976 23:44:36.639816 INFO: [APUAPC] D11_APC_0: 0xffffffff
9977 23:44:36.643067 INFO: [APUAPC] D11_APC_1: 0xffffffff
9978 23:44:36.646227 INFO: [APUAPC] D11_APC_2: 0x3fffff
9979 23:44:36.649808 INFO: [APUAPC] D11_APC_3: 0x0
9980 23:44:36.652949 INFO: [APUAPC] D12_APC_0: 0xffffffff
9981 23:44:36.656214 INFO: [APUAPC] D12_APC_1: 0xffffffff
9982 23:44:36.659297 INFO: [APUAPC] D12_APC_2: 0x3fffff
9983 23:44:36.662885 INFO: [APUAPC] D12_APC_3: 0x0
9984 23:44:36.666300 INFO: [APUAPC] D13_APC_0: 0xffffffff
9985 23:44:36.669433 INFO: [APUAPC] D13_APC_1: 0xffffffff
9986 23:44:36.672541 INFO: [APUAPC] D13_APC_2: 0x3fffff
9987 23:44:36.676196 INFO: [APUAPC] D13_APC_3: 0x0
9988 23:44:36.679725 INFO: [APUAPC] D14_APC_0: 0xffffffff
9989 23:44:36.682792 INFO: [APUAPC] D14_APC_1: 0xffffffff
9990 23:44:36.685876 INFO: [APUAPC] D14_APC_2: 0x3fffff
9991 23:44:36.689541 INFO: [APUAPC] D14_APC_3: 0x0
9992 23:44:36.692648 INFO: [APUAPC] D15_APC_0: 0xffffffff
9993 23:44:36.696420 INFO: [APUAPC] D15_APC_1: 0xffffffff
9994 23:44:36.699881 INFO: [APUAPC] D15_APC_2: 0x3fffff
9995 23:44:36.703323 INFO: [APUAPC] D15_APC_3: 0x0
9996 23:44:36.706395 INFO: [APUAPC] APC_CON: 0x4
9997 23:44:36.709550 INFO: [NOCDAPC] D0_APC_0: 0x0
9998 23:44:36.709637 INFO: [NOCDAPC] D0_APC_1: 0x0
9999 23:44:36.712734 INFO: [NOCDAPC] D1_APC_0: 0x0
10000 23:44:36.716201 INFO: [NOCDAPC] D1_APC_1: 0xfff
10001 23:44:36.719422 INFO: [NOCDAPC] D2_APC_0: 0x0
10002 23:44:36.722729 INFO: [NOCDAPC] D2_APC_1: 0xfff
10003 23:44:36.726840 INFO: [NOCDAPC] D3_APC_0: 0x0
10004 23:44:36.729650 INFO: [NOCDAPC] D3_APC_1: 0xfff
10005 23:44:36.732714 INFO: [NOCDAPC] D4_APC_0: 0x0
10006 23:44:36.736117 INFO: [NOCDAPC] D4_APC_1: 0xfff
10007 23:44:36.740319 INFO: [NOCDAPC] D5_APC_0: 0x0
10008 23:44:36.740416 INFO: [NOCDAPC] D5_APC_1: 0xfff
10009 23:44:36.742709 INFO: [NOCDAPC] D6_APC_0: 0x0
10010 23:44:36.746289 INFO: [NOCDAPC] D6_APC_1: 0xfff
10011 23:44:36.749882 INFO: [NOCDAPC] D7_APC_0: 0x0
10012 23:44:36.753058 INFO: [NOCDAPC] D7_APC_1: 0xfff
10013 23:44:36.756398 INFO: [NOCDAPC] D8_APC_0: 0x0
10014 23:44:36.759894 INFO: [NOCDAPC] D8_APC_1: 0xfff
10015 23:44:36.763236 INFO: [NOCDAPC] D9_APC_0: 0x0
10016 23:44:36.766739 INFO: [NOCDAPC] D9_APC_1: 0xfff
10017 23:44:36.769485 INFO: [NOCDAPC] D10_APC_0: 0x0
10018 23:44:36.769577 INFO: [NOCDAPC] D10_APC_1: 0xfff
10019 23:44:36.773440 INFO: [NOCDAPC] D11_APC_0: 0x0
10020 23:44:36.776422 INFO: [NOCDAPC] D11_APC_1: 0xfff
10021 23:44:36.779856 INFO: [NOCDAPC] D12_APC_0: 0x0
10022 23:44:36.783657 INFO: [NOCDAPC] D12_APC_1: 0xfff
10023 23:44:36.786603 INFO: [NOCDAPC] D13_APC_0: 0x0
10024 23:44:36.789566 INFO: [NOCDAPC] D13_APC_1: 0xfff
10025 23:44:36.793003 INFO: [NOCDAPC] D14_APC_0: 0x0
10026 23:44:36.796175 INFO: [NOCDAPC] D14_APC_1: 0xfff
10027 23:44:36.799848 INFO: [NOCDAPC] D15_APC_0: 0x0
10028 23:44:36.802833 INFO: [NOCDAPC] D15_APC_1: 0xfff
10029 23:44:36.806390 INFO: [NOCDAPC] APC_CON: 0x4
10030 23:44:36.810598 INFO: [APUAPC] set_apusys_apc done
10031 23:44:36.812696 INFO: [DEVAPC] devapc_init done
10032 23:44:36.816121 INFO: GICv3 without legacy support detected.
10033 23:44:36.819420 INFO: ARM GICv3 driver initialized in EL3
10034 23:44:36.823705 INFO: Maximum SPI INTID supported: 639
10035 23:44:36.826155 INFO: BL31: Initializing runtime services
10036 23:44:36.832560 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10037 23:44:36.836064 INFO: SPM: enable CPC mode
10038 23:44:36.842736 INFO: mcdi ready for mcusys-off-idle and system suspend
10039 23:44:36.845865 INFO: BL31: Preparing for EL3 exit to normal world
10040 23:44:36.849724 INFO: Entry point address = 0x80000000
10041 23:44:36.852325 INFO: SPSR = 0x8
10042 23:44:36.857063
10043 23:44:36.857168
10044 23:44:36.857233
10045 23:44:36.860414 Starting depthcharge on Spherion...
10046 23:44:36.860564
10047 23:44:36.860676 Wipe memory regions:
10048 23:44:36.860787
10049 23:44:36.861502 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10050 23:44:36.861606 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10051 23:44:36.861688 Setting prompt string to ['asurada:']
10052 23:44:36.861764 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10053 23:44:36.864170 [0x00000040000000, 0x00000054600000)
10054 23:44:36.986547
10055 23:44:36.986712 [0x00000054660000, 0x00000080000000)
10056 23:44:37.246733
10057 23:44:37.246889 [0x000000821a7280, 0x000000ffe64000)
10058 23:44:37.991585
10059 23:44:37.991747 [0x00000100000000, 0x00000240000000)
10060 23:44:39.881851
10061 23:44:39.885706 Initializing XHCI USB controller at 0x11200000.
10062 23:44:40.923408
10063 23:44:40.926650 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10064 23:44:40.926734
10065 23:44:40.926794
10066 23:44:40.927066 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10068 23:44:41.027400 asurada: tftpboot 192.168.201.1 14172956/tftp-deploy-mv6oeqmu/kernel/image.itb 14172956/tftp-deploy-mv6oeqmu/kernel/cmdline
10069 23:44:41.027578 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10070 23:44:41.027668 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10071 23:44:41.032497 tftpboot 192.168.201.1 14172956/tftp-deploy-mv6oeqmu/kernel/image.ittp-deploy-mv6oeqmu/kernel/cmdline
10072 23:44:41.032581
10073 23:44:41.032644 Waiting for link
10074 23:44:41.192851
10075 23:44:41.193062 R8152: Initializing
10076 23:44:41.193130
10077 23:44:41.196183 Version 6 (ocp_data = 5c30)
10078 23:44:41.196253
10079 23:44:41.199489 R8152: Done initializing
10080 23:44:41.199562
10081 23:44:41.199623 Adding net device
10082 23:44:43.133463
10083 23:44:43.133690 done.
10084 23:44:43.133826
10085 23:44:43.133951 MAC: 00:24:32:30:78:52
10086 23:44:43.134079
10087 23:44:43.136261 Sending DHCP discover... done.
10088 23:44:43.136398
10089 23:44:43.139659 Waiting for reply... done.
10090 23:44:43.139798
10091 23:44:43.143161 Sending DHCP request... done.
10092 23:44:43.143305
10093 23:44:43.206554 Waiting for reply... done.
10094 23:44:43.206751
10095 23:44:43.206913 My ip is 192.168.201.14
10096 23:44:43.207047
10097 23:44:43.208327 The DHCP server ip is 192.168.201.1
10098 23:44:43.208442
10099 23:44:43.214763 TFTP server IP predefined by user: 192.168.201.1
10100 23:44:43.214892
10101 23:44:43.221644 Bootfile predefined by user: 14172956/tftp-deploy-mv6oeqmu/kernel/image.itb
10102 23:44:43.221776
10103 23:44:43.221866 Sending tftp read request... done.
10104 23:44:43.225066
10105 23:44:43.228847 Waiting for the transfer...
10106 23:44:43.228969
10107 23:44:43.747088 00000000 ################################################################
10108 23:44:43.747251
10109 23:44:44.277010 00080000 ################################################################
10110 23:44:44.277168
10111 23:44:44.828878 00100000 ################################################################
10112 23:44:44.829066
10113 23:44:45.379344 00180000 ################################################################
10114 23:44:45.379496
10115 23:44:45.968686 00200000 ################################################################
10116 23:44:45.968834
10117 23:44:46.549634 00280000 ################################################################
10118 23:44:46.549814
10119 23:44:47.223279 00300000 ################################################################
10120 23:44:47.223783
10121 23:44:47.906598 00380000 ################################################################
10122 23:44:47.907089
10123 23:44:48.600512 00400000 ################################################################
10124 23:44:48.601363
10125 23:44:49.286910 00480000 ################################################################
10126 23:44:49.287727
10127 23:44:49.943909 00500000 ################################################################
10128 23:44:49.944416
10129 23:44:50.608248 00580000 ################################################################
10130 23:44:50.608787
10131 23:44:51.293866 00600000 ################################################################
10132 23:44:51.294254
10133 23:44:51.942590 00680000 ################################################################
10134 23:44:51.942816
10135 23:44:52.598949 00700000 ################################################################
10136 23:44:52.599443
10137 23:44:53.286726 00780000 ################################################################
10138 23:44:53.287256
10139 23:44:53.979059 00800000 ################################################################
10140 23:44:53.979571
10141 23:44:54.686460 00880000 ################################################################
10142 23:44:54.686964
10143 23:44:55.394812 00900000 ################################################################
10144 23:44:55.395322
10145 23:44:56.112464 00980000 ################################################################
10146 23:44:56.113047
10147 23:44:56.832290 00a00000 ################################################################
10148 23:44:56.832809
10149 23:44:57.535223 00a80000 ################################################################
10150 23:44:57.535725
10151 23:44:58.201259 00b00000 ################################################################
10152 23:44:58.201761
10153 23:44:58.823289 00b80000 ################################################################
10154 23:44:58.823429
10155 23:44:59.363160 00c00000 ################################################################
10156 23:44:59.363300
10157 23:44:59.925361 00c80000 ################################################################
10158 23:44:59.925491
10159 23:45:00.539376 00d00000 ################################################################
10160 23:45:00.539508
10161 23:45:01.079569 00d80000 ################################################################
10162 23:45:01.079714
10163 23:45:01.642242 00e00000 ################################################################
10164 23:45:01.642393
10165 23:45:02.180507 00e80000 ################################################################
10166 23:45:02.180638
10167 23:45:02.711280 00f00000 ################################################################
10168 23:45:02.711430
10169 23:45:03.241501 00f80000 ################################################################
10170 23:45:03.241648
10171 23:45:03.764550 01000000 ################################################################
10172 23:45:03.764746
10173 23:45:04.298150 01080000 ################################################################
10174 23:45:04.298296
10175 23:45:04.826024 01100000 ################################################################
10176 23:45:04.826184
10177 23:45:05.376595 01180000 ################################################################
10178 23:45:05.376751
10179 23:45:05.907944 01200000 ################################################################
10180 23:45:05.908100
10181 23:45:06.455968 01280000 ################################################################
10182 23:45:06.456108
10183 23:45:07.003876 01300000 ################################################################
10184 23:45:07.004029
10185 23:45:07.540586 01380000 ################################################################
10186 23:45:07.540756
10187 23:45:08.090179 01400000 ################################################################
10188 23:45:08.090373
10189 23:45:08.624065 01480000 ################################################################
10190 23:45:08.624250
10191 23:45:09.185607 01500000 ################################################################
10192 23:45:09.185797
10193 23:45:09.718353 01580000 ################################################################
10194 23:45:09.718506
10195 23:45:10.302753 01600000 ################################################################
10196 23:45:10.302931
10197 23:45:10.901360 01680000 ################################################################
10198 23:45:10.901512
10199 23:45:11.498006 01700000 ################################################################
10200 23:45:11.498166
10201 23:45:12.055806 01780000 ################################################################
10202 23:45:12.055963
10203 23:45:12.614663 01800000 ################################################################
10204 23:45:12.614821
10205 23:45:13.184085 01880000 ################################################################
10206 23:45:13.184244
10207 23:45:13.764472 01900000 ################################################################
10208 23:45:13.764631
10209 23:45:14.339591 01980000 ################################################################
10210 23:45:14.339728
10211 23:45:14.926303 01a00000 ################################################################
10212 23:45:14.926509
10213 23:45:15.498762 01a80000 ################################################################
10214 23:45:15.498916
10215 23:45:16.076022 01b00000 ################################################################
10216 23:45:16.076156
10217 23:45:16.662856 01b80000 ################################################################
10218 23:45:16.662997
10219 23:45:17.251977 01c00000 ################################################################
10220 23:45:17.252133
10221 23:45:17.843010 01c80000 ################################################################
10222 23:45:17.843163
10223 23:45:18.450599 01d00000 ################################################################
10224 23:45:18.450752
10225 23:45:19.048894 01d80000 ################################################################
10226 23:45:19.049086
10227 23:45:19.653732 01e00000 ################################################################
10228 23:45:19.653892
10229 23:45:20.245755 01e80000 ################################################################
10230 23:45:20.245907
10231 23:45:20.855066 01f00000 ################################################################
10232 23:45:20.855216
10233 23:45:21.454176 01f80000 ################################################################
10234 23:45:21.454329
10235 23:45:22.062506 02000000 ################################################################
10236 23:45:22.062663
10237 23:45:22.654430 02080000 ################################################################
10238 23:45:22.654584
10239 23:45:23.242878 02100000 ################################################################
10240 23:45:23.243022
10241 23:45:23.881152 02180000 ################################################################
10242 23:45:23.881667
10243 23:45:24.599440 02200000 ################################################################
10244 23:45:24.599955
10245 23:45:25.253656 02280000 ################################################################
10246 23:45:25.254146
10247 23:45:25.928781 02300000 ################################################################
10248 23:45:25.929377
10249 23:45:26.573461 02380000 ################################################################
10250 23:45:26.573607
10251 23:45:27.260528 02400000 ################################################################
10252 23:45:27.260861
10253 23:45:27.967684 02480000 ################################################################
10254 23:45:27.968202
10255 23:45:28.600232 02500000 ################################################################
10256 23:45:28.600398
10257 23:45:29.254817 02580000 ################################################################
10258 23:45:29.255371
10259 23:45:29.903180 02600000 ################################################################
10260 23:45:29.903454
10261 23:45:30.567019 02680000 ################################################################
10262 23:45:30.567507
10263 23:45:31.215219 02700000 ################################################################
10264 23:45:31.215389
10265 23:45:31.830901 02780000 ################################################################
10266 23:45:31.831421
10267 23:45:32.538060 02800000 ################################################################
10268 23:45:32.538578
10269 23:45:33.268476 02880000 ################################################################
10270 23:45:33.269252
10271 23:45:33.894598 02900000 ################################################################
10272 23:45:33.894734
10273 23:45:34.432327 02980000 ################################################################
10274 23:45:34.432466
10275 23:45:34.974341 02a00000 ################################################################
10276 23:45:34.974473
10277 23:45:35.505546 02a80000 ################################################################
10278 23:45:35.505682
10279 23:45:36.032145 02b00000 ################################################################
10280 23:45:36.032282
10281 23:45:36.551668 02b80000 ################################################################
10282 23:45:36.551808
10283 23:45:37.086941 02c00000 ################################################################
10284 23:45:37.087077
10285 23:45:37.625428 02c80000 ################################################################
10286 23:45:37.625568
10287 23:45:38.146566 02d00000 ################################################################
10288 23:45:38.146714
10289 23:45:38.692169 02d80000 ################################################################
10290 23:45:38.692310
10291 23:45:39.213569 02e00000 ################################################################
10292 23:45:39.213709
10293 23:45:39.748386 02e80000 ################################################################
10294 23:45:39.748535
10295 23:45:40.293775 02f00000 ################################################################
10296 23:45:40.293953
10297 23:45:40.821335 02f80000 ################################################################
10298 23:45:40.821484
10299 23:45:41.341842 03000000 ################################################################
10300 23:45:41.342053
10301 23:45:41.860143 03080000 ################################################################
10302 23:45:41.860287
10303 23:45:42.389664 03100000 ################################################################
10304 23:45:42.389817
10305 23:45:42.905237 03180000 ################################################################
10306 23:45:42.905404
10307 23:45:43.436752 03200000 ################################################################
10308 23:45:43.436895
10309 23:45:43.971048 03280000 ################################################################
10310 23:45:43.971194
10311 23:45:44.504278 03300000 ################################################################
10312 23:45:44.504428
10313 23:45:44.835633 03380000 ####################################### done.
10314 23:45:44.835773
10315 23:45:44.839026 The bootfile was 54318510 bytes long.
10316 23:45:44.839107
10317 23:45:44.842286 Sending tftp read request... done.
10318 23:45:44.842362
10319 23:45:44.842452 Waiting for the transfer...
10320 23:45:44.842556
10321 23:45:44.845643 00000000 # done.
10322 23:45:44.845724
10323 23:45:44.852537 Command line loaded dynamically from TFTP file: 14172956/tftp-deploy-mv6oeqmu/kernel/cmdline
10324 23:45:44.852628
10325 23:45:44.865521 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10326 23:45:44.865616
10327 23:45:44.868680 Loading FIT.
10328 23:45:44.868763
10329 23:45:44.872096 Image ramdisk-1 has 41207787 bytes.
10330 23:45:44.872177
10331 23:45:44.872242 Image fdt-1 has 47258 bytes.
10332 23:45:44.872301
10333 23:45:44.875331 Image kernel-1 has 13061430 bytes.
10334 23:45:44.875412
10335 23:45:44.885220 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10336 23:45:44.885311
10337 23:45:44.901988 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10338 23:45:44.902140
10339 23:45:44.908595 Choosing best match conf-1 for compat google,spherion-rev2.
10340 23:45:44.912541
10341 23:45:44.917718 Connected to device vid:did:rid of 1ae0:0028:00
10342 23:45:44.925734
10343 23:45:44.929304 tpm_get_response: command 0x17b, return code 0x0
10344 23:45:44.929390
10345 23:45:44.932207 ec_init: CrosEC protocol v3 supported (256, 248)
10346 23:45:44.936465
10347 23:45:44.939514 tpm_cleanup: add release locality here.
10348 23:45:44.939596
10349 23:45:44.939660 Shutting down all USB controllers.
10350 23:45:44.943218
10351 23:45:44.943301 Removing current net device
10352 23:45:44.943365
10353 23:45:44.949936 Exiting depthcharge with code 4 at timestamp: 97493661
10354 23:45:44.950020
10355 23:45:44.953207 LZMA decompressing kernel-1 to 0x821a6718
10356 23:45:44.953288
10357 23:45:44.956281 LZMA decompressing kernel-1 to 0x40000000
10358 23:45:46.566455
10359 23:45:46.566602 jumping to kernel
10360 23:45:46.567119 end: 2.2.4 bootloader-commands (duration 00:01:10) [common]
10361 23:45:46.567215 start: 2.2.5 auto-login-action (timeout 00:03:15) [common]
10362 23:45:46.567291 Setting prompt string to ['Linux version [0-9]']
10363 23:45:46.567422 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10364 23:45:46.567552 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10365 23:45:46.648666
10366 23:45:46.651879 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10367 23:45:46.655261 start: 2.2.5.1 login-action (timeout 00:03:15) [common]
10368 23:45:46.655366 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10369 23:45:46.655438 Setting prompt string to []
10370 23:45:46.655515 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10371 23:45:46.655589 Using line separator: #'\n'#
10372 23:45:46.655646 No login prompt set.
10373 23:45:46.655740 Parsing kernel messages
10374 23:45:46.655825 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10375 23:45:46.655927 [login-action] Waiting for messages, (timeout 00:03:15)
10376 23:45:46.656023 Waiting using forced prompt support (timeout 00:01:38)
10377 23:45:46.674822 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j217067-arm64-gcc-10-defconfig-arm64-chromebook-s48tj) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 4 23:28:43 UTC 2024
10378 23:45:46.678529 [ 0.000000] random: crng init done
10379 23:45:46.685236 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10380 23:45:46.688286 [ 0.000000] efi: UEFI not found.
10381 23:45:46.694986 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10382 23:45:46.701601 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10383 23:45:46.711968 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10384 23:45:46.721366 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10385 23:45:46.728332 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10386 23:45:46.731416 [ 0.000000] printk: bootconsole [mtk8250] enabled
10387 23:45:46.740696 [ 0.000000] NUMA: No NUMA configuration found
10388 23:45:46.747175 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10389 23:45:46.753518 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10390 23:45:46.753609 [ 0.000000] Zone ranges:
10391 23:45:46.760925 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10392 23:45:46.764418 [ 0.000000] DMA32 empty
10393 23:45:46.770491 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10394 23:45:46.773962 [ 0.000000] Movable zone start for each node
10395 23:45:46.776873 [ 0.000000] Early memory node ranges
10396 23:45:46.784035 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10397 23:45:46.790507 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10398 23:45:46.796981 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10399 23:45:46.803490 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10400 23:45:46.810427 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10401 23:45:46.817286 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10402 23:45:46.873362 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10403 23:45:46.879602 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10404 23:45:46.886862 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10405 23:45:46.889684 [ 0.000000] psci: probing for conduit method from DT.
10406 23:45:46.896267 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10407 23:45:46.899727 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10408 23:45:46.906935 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10409 23:45:46.909718 [ 0.000000] psci: SMC Calling Convention v1.2
10410 23:45:46.916603 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10411 23:45:46.920332 [ 0.000000] Detected VIPT I-cache on CPU0
10412 23:45:46.926645 [ 0.000000] CPU features: detected: GIC system register CPU interface
10413 23:45:46.933378 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10414 23:45:46.939817 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10415 23:45:46.946527 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10416 23:45:46.953192 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10417 23:45:46.959791 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10418 23:45:46.966210 [ 0.000000] alternatives: applying boot alternatives
10419 23:45:46.969816 [ 0.000000] Fallback order for Node 0: 0
10420 23:45:46.979700 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10421 23:45:46.979854 [ 0.000000] Policy zone: Normal
10422 23:45:46.995972 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10423 23:45:47.006005 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10424 23:45:47.017461 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10425 23:45:47.027614 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10426 23:45:47.034274 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10427 23:45:47.037625 <6>[ 0.000000] software IO TLB: area num 8.
10428 23:45:47.094376 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10429 23:45:47.244097 <6>[ 0.000000] Memory: 7923944K/8385536K available (18112K kernel code, 4120K rwdata, 22504K rodata, 8512K init, 616K bss, 428824K reserved, 32768K cma-reserved)
10430 23:45:47.251037 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10431 23:45:47.257764 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10432 23:45:47.260783 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10433 23:45:47.267814 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10434 23:45:47.274258 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10435 23:45:47.277666 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10436 23:45:47.287198 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10437 23:45:47.293884 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10438 23:45:47.297612 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10439 23:45:47.305572 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10440 23:45:47.308908 <6>[ 0.000000] GICv3: 608 SPIs implemented
10441 23:45:47.315575 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10442 23:45:47.318514 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10443 23:45:47.322377 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10444 23:45:47.331940 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10445 23:45:47.341987 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10446 23:45:47.355027 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10447 23:45:47.361530 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10448 23:45:47.370981 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10449 23:45:47.383859 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10450 23:45:47.390608 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10451 23:45:47.397294 <6>[ 0.009178] Console: colour dummy device 80x25
10452 23:45:47.407277 <6>[ 0.013906] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10453 23:45:47.413885 <6>[ 0.024412] pid_max: default: 32768 minimum: 301
10454 23:45:47.417163 <6>[ 0.029314] LSM: Security Framework initializing
10455 23:45:47.423879 <6>[ 0.034251] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10456 23:45:47.434040 <6>[ 0.042067] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10457 23:45:47.440318 <6>[ 0.051484] cblist_init_generic: Setting adjustable number of callback queues.
10458 23:45:47.446973 <6>[ 0.058929] cblist_init_generic: Setting shift to 3 and lim to 1.
10459 23:45:47.457165 <6>[ 0.065268] cblist_init_generic: Setting adjustable number of callback queues.
10460 23:45:47.463912 <6>[ 0.072742] cblist_init_generic: Setting shift to 3 and lim to 1.
10461 23:45:47.467178 <6>[ 0.079141] rcu: Hierarchical SRCU implementation.
10462 23:45:47.473692 <6>[ 0.084188] rcu: Max phase no-delay instances is 1000.
10463 23:45:47.480456 <6>[ 0.091213] EFI services will not be available.
10464 23:45:47.484142 <6>[ 0.096196] smp: Bringing up secondary CPUs ...
10465 23:45:47.491590 <6>[ 0.101244] Detected VIPT I-cache on CPU1
10466 23:45:47.498595 <6>[ 0.101315] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10467 23:45:47.505270 <6>[ 0.101347] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10468 23:45:47.508763 <6>[ 0.101688] Detected VIPT I-cache on CPU2
10469 23:45:47.515271 <6>[ 0.101742] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10470 23:45:47.521970 <6>[ 0.101760] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10471 23:45:47.528048 <6>[ 0.102022] Detected VIPT I-cache on CPU3
10472 23:45:47.535342 <6>[ 0.102071] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10473 23:45:47.541407 <6>[ 0.102087] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10474 23:45:47.545068 <6>[ 0.102390] CPU features: detected: Spectre-v4
10475 23:45:47.551629 <6>[ 0.102396] CPU features: detected: Spectre-BHB
10476 23:45:47.555133 <6>[ 0.102403] Detected PIPT I-cache on CPU4
10477 23:45:47.562051 <6>[ 0.102464] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10478 23:45:47.568509 <6>[ 0.102480] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10479 23:45:47.571736 <6>[ 0.102774] Detected PIPT I-cache on CPU5
10480 23:45:47.581740 <6>[ 0.102835] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10481 23:45:47.588387 <6>[ 0.102851] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10482 23:45:47.591585 <6>[ 0.103129] Detected PIPT I-cache on CPU6
10483 23:45:47.598972 <6>[ 0.103196] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10484 23:45:47.605426 <6>[ 0.103213] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10485 23:45:47.608495 <6>[ 0.103509] Detected PIPT I-cache on CPU7
10486 23:45:47.618299 <6>[ 0.103574] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10487 23:45:47.624795 <6>[ 0.103590] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10488 23:45:47.628273 <6>[ 0.103638] smp: Brought up 1 node, 8 CPUs
10489 23:45:47.631616 <6>[ 0.244938] SMP: Total of 8 processors activated.
10490 23:45:47.638546 <6>[ 0.249859] CPU features: detected: 32-bit EL0 Support
10491 23:45:47.648351 <6>[ 0.255253] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10492 23:45:47.655039 <6>[ 0.264050] CPU features: detected: Common not Private translations
10493 23:45:47.658473 <6>[ 0.270528] CPU features: detected: CRC32 instructions
10494 23:45:47.664963 <6>[ 0.275882] CPU features: detected: RCpc load-acquire (LDAPR)
10495 23:45:47.671645 <6>[ 0.281877] CPU features: detected: LSE atomic instructions
10496 23:45:47.675068 <6>[ 0.287658] CPU features: detected: Privileged Access Never
10497 23:45:47.681490 <6>[ 0.293445] CPU features: detected: RAS Extension Support
10498 23:45:47.688119 <6>[ 0.299056] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10499 23:45:47.694459 <6>[ 0.306322] CPU: All CPU(s) started at EL2
10500 23:45:47.698105 <6>[ 0.310640] alternatives: applying system-wide alternatives
10501 23:45:47.709661 <6>[ 0.321489] devtmpfs: initialized
10502 23:45:47.721535 <6>[ 0.330300] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10503 23:45:47.731978 <6>[ 0.340257] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10504 23:45:47.738251 <6>[ 0.348270] pinctrl core: initialized pinctrl subsystem
10505 23:45:47.741341 <6>[ 0.354949] DMI not present or invalid.
10506 23:45:47.748154 <6>[ 0.359355] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10507 23:45:47.758548 <6>[ 0.366198] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10508 23:45:47.764788 <6>[ 0.373784] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10509 23:45:47.775036 <6>[ 0.382003] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10510 23:45:47.778146 <6>[ 0.390247] audit: initializing netlink subsys (disabled)
10511 23:45:47.788084 <5>[ 0.395941] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10512 23:45:47.794708 <6>[ 0.396651] thermal_sys: Registered thermal governor 'step_wise'
10513 23:45:47.801451 <6>[ 0.403904] thermal_sys: Registered thermal governor 'power_allocator'
10514 23:45:47.805145 <6>[ 0.410163] cpuidle: using governor menu
10515 23:45:47.808093 <6>[ 0.421120] NET: Registered PF_QIPCRTR protocol family
10516 23:45:47.817938 <6>[ 0.426601] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10517 23:45:47.821417 <6>[ 0.433700] ASID allocator initialised with 32768 entries
10518 23:45:47.827954 <6>[ 0.440292] Serial: AMBA PL011 UART driver
10519 23:45:47.837166 <4>[ 0.449132] Trying to register duplicate clock ID: 134
10520 23:45:47.894934 <6>[ 0.510358] KASLR enabled
10521 23:45:47.909791 <6>[ 0.518006] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10522 23:45:47.915834 <6>[ 0.525022] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10523 23:45:47.922714 <6>[ 0.531507] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10524 23:45:47.929404 <6>[ 0.538513] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10525 23:45:47.935807 <6>[ 0.545001] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10526 23:45:47.943075 <6>[ 0.552002] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10527 23:45:47.949445 <6>[ 0.558487] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10528 23:45:47.955949 <6>[ 0.565491] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10529 23:45:47.959147 <6>[ 0.572949] ACPI: Interpreter disabled.
10530 23:45:47.967217 <6>[ 0.579385] iommu: Default domain type: Translated
10531 23:45:47.974350 <6>[ 0.584500] iommu: DMA domain TLB invalidation policy: strict mode
10532 23:45:47.977707 <5>[ 0.591160] SCSI subsystem initialized
10533 23:45:47.983905 <6>[ 0.595407] usbcore: registered new interface driver usbfs
10534 23:45:47.990573 <6>[ 0.601137] usbcore: registered new interface driver hub
10535 23:45:47.994197 <6>[ 0.606691] usbcore: registered new device driver usb
10536 23:45:48.000968 <6>[ 0.612797] pps_core: LinuxPPS API ver. 1 registered
10537 23:45:48.010769 <6>[ 0.617991] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10538 23:45:48.014404 <6>[ 0.627337] PTP clock support registered
10539 23:45:48.017909 <6>[ 0.631575] EDAC MC: Ver: 3.0.0
10540 23:45:48.024881 <6>[ 0.636764] FPGA manager framework
10541 23:45:48.027972 <6>[ 0.640440] Advanced Linux Sound Architecture Driver Initialized.
10542 23:45:48.031803 <6>[ 0.647212] vgaarb: loaded
10543 23:45:48.038389 <6>[ 0.650365] clocksource: Switched to clocksource arch_sys_counter
10544 23:45:48.045449 <5>[ 0.656807] VFS: Disk quotas dquot_6.6.0
10545 23:45:48.051947 <6>[ 0.660992] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10546 23:45:48.055607 <6>[ 0.668167] pnp: PnP ACPI: disabled
10547 23:45:48.062819 <6>[ 0.674839] NET: Registered PF_INET protocol family
10548 23:45:48.072715 <6>[ 0.680432] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10549 23:45:48.083975 <6>[ 0.692760] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10550 23:45:48.094401 <6>[ 0.701567] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10551 23:45:48.100845 <6>[ 0.709533] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10552 23:45:48.107850 <6>[ 0.718188] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10553 23:45:48.119521 <6>[ 0.727940] TCP: Hash tables configured (established 65536 bind 65536)
10554 23:45:48.126285 <6>[ 0.734810] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10555 23:45:48.132548 <6>[ 0.742006] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10556 23:45:48.139079 <6>[ 0.749711] NET: Registered PF_UNIX/PF_LOCAL protocol family
10557 23:45:48.145834 <6>[ 0.755854] RPC: Registered named UNIX socket transport module.
10558 23:45:48.149627 <6>[ 0.762010] RPC: Registered udp transport module.
10559 23:45:48.155637 <6>[ 0.766944] RPC: Registered tcp transport module.
10560 23:45:48.162593 <6>[ 0.771874] RPC: Registered tcp NFSv4.1 backchannel transport module.
10561 23:45:48.165577 <6>[ 0.778542] PCI: CLS 0 bytes, default 64
10562 23:45:48.168941 <6>[ 0.782868] Unpacking initramfs...
10563 23:45:48.186303 <6>[ 0.794887] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10564 23:45:48.195951 <6>[ 0.803507] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10565 23:45:48.199325 <6>[ 0.812322] kvm [1]: IPA Size Limit: 40 bits
10566 23:45:48.206164 <6>[ 0.816848] kvm [1]: GICv3: no GICV resource entry
10567 23:45:48.209711 <6>[ 0.821869] kvm [1]: disabling GICv2 emulation
10568 23:45:48.216439 <6>[ 0.826555] kvm [1]: GIC system register CPU interface enabled
10569 23:45:48.223023 <6>[ 0.834422] kvm [1]: vgic interrupt IRQ18
10570 23:45:48.226497 <6>[ 0.838796] kvm [1]: VHE mode initialized successfully
10571 23:45:48.233339 <5>[ 0.845144] Initialise system trusted keyrings
10572 23:45:48.240500 <6>[ 0.849964] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10573 23:45:48.248193 <6>[ 0.859949] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10574 23:45:48.254773 <5>[ 0.866323] NFS: Registering the id_resolver key type
10575 23:45:48.258099 <5>[ 0.871622] Key type id_resolver registered
10576 23:45:48.264862 <5>[ 0.876034] Key type id_legacy registered
10577 23:45:48.271196 <6>[ 0.880314] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10578 23:45:48.278574 <6>[ 0.887232] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10579 23:45:48.284672 <6>[ 0.894941] 9p: Installing v9fs 9p2000 file system support
10580 23:45:48.320799 <5>[ 0.932768] Key type asymmetric registered
10581 23:45:48.324166 <5>[ 0.937096] Asymmetric key parser 'x509' registered
10582 23:45:48.334514 <6>[ 0.942232] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10583 23:45:48.337263 <6>[ 0.949848] io scheduler mq-deadline registered
10584 23:45:48.341154 <6>[ 0.954633] io scheduler kyber registered
10585 23:45:48.359517 <6>[ 0.971528] EINJ: ACPI disabled.
10586 23:45:48.392172 <4>[ 0.997622] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10587 23:45:48.402868 <4>[ 1.008249] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10588 23:45:48.416531 <6>[ 1.028840] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10589 23:45:48.424627 <6>[ 1.036829] printk: console [ttyS0] disabled
10590 23:45:48.452483 <6>[ 1.061451] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10591 23:45:48.459135 <6>[ 1.070923] printk: console [ttyS0] enabled
10592 23:45:48.463102 <6>[ 1.070923] printk: console [ttyS0] enabled
10593 23:45:48.469487 <6>[ 1.079820] printk: bootconsole [mtk8250] disabled
10594 23:45:48.472599 <6>[ 1.079820] printk: bootconsole [mtk8250] disabled
10595 23:45:48.479161 <6>[ 1.090828] SuperH (H)SCI(F) driver initialized
10596 23:45:48.482750 <6>[ 1.096110] msm_serial: driver initialized
10597 23:45:48.496142 <6>[ 1.105017] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10598 23:45:48.506172 <6>[ 1.113561] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10599 23:45:48.513233 <6>[ 1.122103] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10600 23:45:48.522922 <6>[ 1.130731] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10601 23:45:48.529614 <6>[ 1.139437] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10602 23:45:48.539435 <6>[ 1.148151] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10603 23:45:48.549540 <6>[ 1.156690] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10604 23:45:48.556602 <6>[ 1.165492] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10605 23:45:48.566335 <6>[ 1.174036] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10606 23:45:48.577247 <6>[ 1.189469] loop: module loaded
10607 23:45:48.583840 <6>[ 1.195366] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10608 23:45:48.606485 <4>[ 1.218663] mtk-pmic-keys: Failed to locate of_node [id: -1]
10609 23:45:48.614060 <6>[ 1.225588] megasas: 07.719.03.00-rc1
10610 23:45:48.623009 <6>[ 1.235340] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10611 23:45:48.633892 <6>[ 1.245742] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10612 23:45:48.650257 <6>[ 1.262463] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10613 23:45:48.707056 <6>[ 1.312323] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10614 23:45:49.896529 <6>[ 2.508876] Freeing initrd memory: 40240K
10615 23:45:49.908431 <6>[ 2.520438] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10616 23:45:49.919402 <6>[ 2.531396] tun: Universal TUN/TAP device driver, 1.6
10617 23:45:49.922408 <6>[ 2.537457] thunder_xcv, ver 1.0
10618 23:45:49.926219 <6>[ 2.540963] thunder_bgx, ver 1.0
10619 23:45:49.929369 <6>[ 2.544466] nicpf, ver 1.0
10620 23:45:49.939450 <6>[ 2.548482] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10621 23:45:49.942634 <6>[ 2.555958] hns3: Copyright (c) 2017 Huawei Corporation.
10622 23:45:49.946688 <6>[ 2.561548] hclge is initializing
10623 23:45:49.952893 <6>[ 2.565123] e1000: Intel(R) PRO/1000 Network Driver
10624 23:45:49.959669 <6>[ 2.570253] e1000: Copyright (c) 1999-2006 Intel Corporation.
10625 23:45:49.963086 <6>[ 2.576265] e1000e: Intel(R) PRO/1000 Network Driver
10626 23:45:49.969769 <6>[ 2.581481] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10627 23:45:49.975683 <6>[ 2.587665] igb: Intel(R) Gigabit Ethernet Network Driver
10628 23:45:49.982482 <6>[ 2.593314] igb: Copyright (c) 2007-2014 Intel Corporation.
10629 23:45:49.989460 <6>[ 2.599152] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10630 23:45:49.995817 <6>[ 2.605670] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10631 23:45:49.999223 <6>[ 2.612131] sky2: driver version 1.30
10632 23:45:50.005638 <6>[ 2.617059] usbcore: registered new device driver r8152-cfgselector
10633 23:45:50.012552 <6>[ 2.623598] usbcore: registered new interface driver r8152
10634 23:45:50.019541 <6>[ 2.629420] VFIO - User Level meta-driver version: 0.3
10635 23:45:50.025818 <6>[ 2.637656] usbcore: registered new interface driver usb-storage
10636 23:45:50.032200 <6>[ 2.644102] usbcore: registered new device driver onboard-usb-hub
10637 23:45:50.041205 <6>[ 2.653258] mt6397-rtc mt6359-rtc: registered as rtc0
10638 23:45:50.050919 <6>[ 2.658721] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-04T23:45:51 UTC (1717544751)
10639 23:45:50.054159 <6>[ 2.668284] i2c_dev: i2c /dev entries driver
10640 23:45:50.071893 <6>[ 2.680199] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10641 23:45:50.077807 <4>[ 2.688957] cpu cpu0: supply cpu not found, using dummy regulator
10642 23:45:50.084826 <4>[ 2.695382] cpu cpu1: supply cpu not found, using dummy regulator
10643 23:45:50.091021 <4>[ 2.701786] cpu cpu2: supply cpu not found, using dummy regulator
10644 23:45:50.097601 <4>[ 2.708192] cpu cpu3: supply cpu not found, using dummy regulator
10645 23:45:50.104288 <4>[ 2.714603] cpu cpu4: supply cpu not found, using dummy regulator
10646 23:45:50.111079 <4>[ 2.720997] cpu cpu5: supply cpu not found, using dummy regulator
10647 23:45:50.117417 <4>[ 2.727397] cpu cpu6: supply cpu not found, using dummy regulator
10648 23:45:50.124234 <4>[ 2.733792] cpu cpu7: supply cpu not found, using dummy regulator
10649 23:45:50.142998 <6>[ 2.755449] cpu cpu0: EM: created perf domain
10650 23:45:50.146667 <6>[ 2.760396] cpu cpu4: EM: created perf domain
10651 23:45:50.154138 <6>[ 2.766023] sdhci: Secure Digital Host Controller Interface driver
10652 23:45:50.160380 <6>[ 2.772456] sdhci: Copyright(c) Pierre Ossman
10653 23:45:50.166958 <6>[ 2.777415] Synopsys Designware Multimedia Card Interface Driver
10654 23:45:50.173906 <6>[ 2.784055] sdhci-pltfm: SDHCI platform and OF driver helper
10655 23:45:50.176951 <6>[ 2.784105] mmc0: CQHCI version 5.10
10656 23:45:50.183929 <6>[ 2.794108] ledtrig-cpu: registered to indicate activity on CPUs
10657 23:45:50.190757 <6>[ 2.801172] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10658 23:45:50.197165 <6>[ 2.808230] usbcore: registered new interface driver usbhid
10659 23:45:50.200257 <6>[ 2.814052] usbhid: USB HID core driver
10660 23:45:50.207193 <6>[ 2.818244] spi_master spi0: will run message pump with realtime priority
10661 23:45:50.247927 <6>[ 2.853652] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10662 23:45:50.266689 <6>[ 2.868779] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10663 23:45:50.273475 <6>[ 2.883637] cros-ec-spi spi0.0: Chrome EC device registered
10664 23:45:50.276897 <6>[ 2.885516] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x15414
10665 23:45:50.287341 <6>[ 2.899542] mmc0: Command Queue Engine enabled
10666 23:45:50.294326 <6>[ 2.904271] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10667 23:45:50.300816 <6>[ 2.912098] mmcblk0: mmc0:0001 DA4128 116 GiB
10668 23:45:50.309158 <6>[ 2.920790] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10669 23:45:50.318854 <6>[ 2.924324] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10670 23:45:50.325441 <6>[ 2.928020] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10671 23:45:50.328632 <6>[ 2.937332] NET: Registered PF_PACKET protocol family
10672 23:45:50.335454 <6>[ 2.941986] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10673 23:45:50.339320 <6>[ 2.946621] 9pnet: Installing 9P2000 support
10674 23:45:50.345179 <6>[ 2.952411] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10675 23:45:50.348675 <5>[ 2.956328] Key type dns_resolver registered
10676 23:45:50.355449 <6>[ 2.967785] registered taskstats version 1
10677 23:45:50.359060 <5>[ 2.972169] Loading compiled-in X.509 certificates
10678 23:45:50.389260 <4>[ 2.994904] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10679 23:45:50.399233 <4>[ 3.005773] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10680 23:45:50.417374 <6>[ 3.029547] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10681 23:45:50.424222 <6>[ 3.036598] xhci-mtk 11200000.usb: xHCI Host Controller
10682 23:45:50.431024 <6>[ 3.042102] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10683 23:45:50.441195 <6>[ 3.049944] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10684 23:45:50.447611 <6>[ 3.059369] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10685 23:45:50.454628 <6>[ 3.065441] xhci-mtk 11200000.usb: xHCI Host Controller
10686 23:45:50.461264 <6>[ 3.070921] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10687 23:45:50.467747 <6>[ 3.078573] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10688 23:45:50.474660 <6>[ 3.086211] hub 1-0:1.0: USB hub found
10689 23:45:50.478080 <6>[ 3.090222] hub 1-0:1.0: 1 port detected
10690 23:45:50.484057 <6>[ 3.094496] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10691 23:45:50.491347 <6>[ 3.103012] hub 2-0:1.0: USB hub found
10692 23:45:50.494174 <6>[ 3.107019] hub 2-0:1.0: 1 port detected
10693 23:45:50.501937 <6>[ 3.114013] mtk-msdc 11f70000.mmc: Got CD GPIO
10694 23:45:50.514603 <6>[ 3.123385] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10695 23:45:50.521451 <6>[ 3.131409] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10696 23:45:50.531471 <4>[ 3.139330] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10697 23:45:50.540857 <6>[ 3.148865] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10698 23:45:50.547740 <6>[ 3.156942] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10699 23:45:50.554318 <6>[ 3.164930] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10700 23:45:50.564698 <6>[ 3.172850] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10701 23:45:50.571055 <6>[ 3.180667] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10702 23:45:50.581872 <6>[ 3.188483] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10703 23:45:50.590950 <6>[ 3.198691] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10704 23:45:50.597945 <6>[ 3.207052] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10705 23:45:50.607795 <6>[ 3.215396] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10706 23:45:50.614389 <6>[ 3.223735] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10707 23:45:50.624235 <6>[ 3.232073] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10708 23:45:50.631068 <6>[ 3.240411] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10709 23:45:50.640627 <6>[ 3.248752] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10710 23:45:50.647514 <6>[ 3.257090] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10711 23:45:50.657011 <6>[ 3.265427] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10712 23:45:50.664006 <6>[ 3.273766] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10713 23:45:50.673645 <6>[ 3.282104] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10714 23:45:50.680520 <6>[ 3.290444] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10715 23:45:50.690649 <6>[ 3.298784] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10716 23:45:50.697664 <6>[ 3.307122] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10717 23:45:50.707112 <6>[ 3.315460] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10718 23:45:50.713857 <6>[ 3.324200] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10719 23:45:50.720185 <6>[ 3.331359] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10720 23:45:50.726732 <6>[ 3.338125] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10721 23:45:50.733726 <6>[ 3.344879] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10722 23:45:50.740299 <6>[ 3.351811] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10723 23:45:50.750156 <6>[ 3.358662] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10724 23:45:50.760668 <6>[ 3.367799] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10725 23:45:50.771194 <6>[ 3.376919] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10726 23:45:50.777106 <6>[ 3.386213] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10727 23:45:50.787072 <6>[ 3.395680] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10728 23:45:50.796547 <6>[ 3.405148] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10729 23:45:50.806543 <6>[ 3.414267] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10730 23:45:50.816531 <6>[ 3.423733] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10731 23:45:50.823166 <6>[ 3.432851] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10732 23:45:50.836878 <6>[ 3.442145] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10733 23:45:50.846785 <6>[ 3.452305] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10734 23:45:50.856483 <6>[ 3.464302] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10735 23:45:50.905760 <6>[ 3.514633] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10736 23:45:51.060723 <6>[ 3.672748] hub 1-1:1.0: USB hub found
10737 23:45:51.064220 <6>[ 3.677258] hub 1-1:1.0: 4 ports detected
10738 23:45:51.073523 <6>[ 3.685566] hub 1-1:1.0: USB hub found
10739 23:45:51.076912 <6>[ 3.689909] hub 1-1:1.0: 4 ports detected
10740 23:45:51.185579 <6>[ 3.794971] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10741 23:45:51.212033 <6>[ 3.824579] hub 2-1:1.0: USB hub found
10742 23:45:51.215567 <6>[ 3.829111] hub 2-1:1.0: 3 ports detected
10743 23:45:51.225681 <6>[ 3.837510] hub 2-1:1.0: USB hub found
10744 23:45:51.228669 <6>[ 3.841987] hub 2-1:1.0: 3 ports detected
10745 23:45:51.401788 <6>[ 4.010663] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10746 23:45:51.533371 <6>[ 4.145658] hub 1-1.4:1.0: USB hub found
10747 23:45:51.536385 <6>[ 4.150178] hub 1-1.4:1.0: 2 ports detected
10748 23:45:51.546242 <6>[ 4.158224] hub 1-1.4:1.0: USB hub found
10749 23:45:51.549155 <6>[ 4.162850] hub 1-1.4:1.0: 2 ports detected
10750 23:45:51.617752 <6>[ 4.226771] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10751 23:45:51.726224 <6>[ 4.335230] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10752 23:45:51.761616 <4>[ 4.370488] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10753 23:45:51.771461 <4>[ 4.379612] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10754 23:45:51.807704 <6>[ 4.419986] r8152 2-1.3:1.0 eth0: v1.12.13
10755 23:45:51.845947 <6>[ 4.454658] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10756 23:45:52.037665 <6>[ 4.646730] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10757 23:45:53.419876 <6>[ 6.032425] r8152 2-1.3:1.0 eth0: carrier on
10758 23:45:56.173879 <5>[ 6.058415] Sending DHCP requests .., OK
10759 23:45:56.180112 <6>[ 8.790717] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10760 23:45:56.183361 <6>[ 8.799007] IP-Config: Complete:
10761 23:45:56.197160 <6>[ 8.802500] device=eth0, hwaddr=00:24:32:30:78:52, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10762 23:45:56.203951 <6>[ 8.813214] host=mt8192-asurada-spherion-r0-cbg-3, domain=lava-rack, nis-domain=(none)
10763 23:45:56.210245 <6>[ 8.821836] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10764 23:45:56.216927 <6>[ 8.821845] nameserver0=192.168.201.1
10765 23:45:56.220261 <6>[ 8.833967] clk: Disabling unused clocks
10766 23:45:56.223449 <6>[ 8.839326] ALSA device list:
10767 23:45:56.226806 <6>[ 8.842619] No soundcards found.
10768 23:45:56.237711 <6>[ 8.850224] Freeing unused kernel memory: 8512K
10769 23:45:56.240495 <6>[ 8.855202] Run /init as init process
10770 23:45:56.274906 <6>[ 8.887234] NET: Registered PF_INET6 protocol family
10771 23:45:56.281587 <6>[ 8.894102] Segment Routing with IPv6
10772 23:45:56.284430 <6>[ 8.898060] In-situ OAM (IOAM) with IPv6
10773 23:45:56.327756 <30>[ 8.913832] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10774 23:45:56.333834 <30>[ 8.946872] systemd[1]: Detected architecture arm64.
10775 23:45:56.333918
10776 23:45:56.340572 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10777 23:45:56.340653
10778 23:45:56.354053 <30>[ 8.966775] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10779 23:45:56.480810 <30>[ 9.090264] systemd[1]: Queued start job for default target graphical.target.
10780 23:45:56.534255 <30>[ 9.143949] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10781 23:45:56.540692 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10782 23:45:56.561380 <30>[ 9.171249] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10783 23:45:56.571657 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10784 23:45:56.590470 <30>[ 9.200346] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10785 23:45:56.600836 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10786 23:45:56.618977 <30>[ 9.228112] systemd[1]: Created slice user.slice - User and Session Slice.
10787 23:45:56.625240 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10788 23:45:56.648907 <30>[ 9.255384] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10789 23:45:56.659063 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10790 23:45:56.676481 <30>[ 9.282804] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10791 23:45:56.683113 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10792 23:45:56.711076 <30>[ 9.310794] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10793 23:45:56.720956 <30>[ 9.330613] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10794 23:45:56.727827 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10795 23:45:56.745310 <30>[ 9.355108] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10796 23:45:56.752071 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10797 23:45:56.773671 <30>[ 9.383171] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10798 23:45:56.783602 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10799 23:45:56.798017 <30>[ 9.411221] systemd[1]: Reached target paths.target - Path Units.
10800 23:45:56.808388 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10801 23:45:56.825615 <30>[ 9.435109] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10802 23:45:56.832429 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10803 23:45:56.845856 <30>[ 9.458646] systemd[1]: Reached target slices.target - Slice Units.
10804 23:45:56.855505 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10805 23:45:56.870377 <30>[ 9.483178] systemd[1]: Reached target swap.target - Swaps.
10806 23:45:56.876656 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10807 23:45:56.897582 <30>[ 9.507187] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10808 23:45:56.907716 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10809 23:45:56.926194 <30>[ 9.535610] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10810 23:45:56.935873 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10811 23:45:56.955678 <30>[ 9.564893] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10812 23:45:56.965267 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10813 23:45:56.981723 <30>[ 9.591338] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10814 23:45:56.991640 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10815 23:45:57.009342 <30>[ 9.619264] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10816 23:45:57.016098 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10817 23:45:57.034041 <30>[ 9.643337] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10818 23:45:57.043986 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10819 23:45:57.061970 <30>[ 9.671367] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10820 23:45:57.071783 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10821 23:45:57.090256 <30>[ 9.699769] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10822 23:45:57.099723 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10823 23:45:57.141391 <30>[ 9.750767] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10824 23:45:57.148272 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10825 23:45:57.169448 <30>[ 9.778920] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10826 23:45:57.176071 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10827 23:45:57.196884 <30>[ 9.806701] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10828 23:45:57.203436 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10829 23:45:57.228079 <30>[ 9.831125] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10830 23:45:57.241580 <30>[ 9.851271] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10831 23:45:57.251816 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10832 23:45:57.301655 <30>[ 9.911128] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10833 23:45:57.307705 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10834 23:45:57.333915 <30>[ 9.943924] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10835 23:45:57.347174 Starting [0;1;39mmodpr<6>[ 9.955060] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10836 23:45:57.350526 obe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10837 23:45:57.374750 <30>[ 9.984281] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10838 23:45:57.381324 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10839 23:45:57.441775 <30>[ 10.051346] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10840 23:45:57.448587 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10841 23:45:57.474311 <30>[ 10.083818] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10842 23:45:57.480459 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10843 23:45:57.534271 <30>[ 10.143521] systemd[1]: Starting systemd-journald.service - Journal Service...
10844 23:45:57.540269 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10845 23:45:57.563352 <30>[ 10.173376] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10846 23:45:57.570273 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10847 23:45:57.595324 <30>[ 10.201586] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10848 23:45:57.601778 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10849 23:45:57.626293 <30>[ 10.235906] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10850 23:45:57.636211 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10851 23:45:57.656928 <30>[ 10.266860] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10852 23:45:57.663866 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10853 23:45:57.693137 <30>[ 10.302502] systemd[1]: Started systemd-journald.service - Journal Service.
10854 23:45:57.699524 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10855 23:45:57.721354 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10856 23:45:57.738216 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10857 23:45:57.758040 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10858 23:45:57.778008 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10859 23:45:57.799436 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10860 23:45:57.818435 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10861 23:45:57.839745 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10862 23:45:57.864365 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10863 23:45:57.887738 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10864 23:45:57.907045 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10865 23:45:57.930626 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10866 23:45:57.951523 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10867 23:45:57.958128 See 'systemctl status systemd-remount-fs.service' for details.
10868 23:45:57.967867 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10869 23:45:57.991749 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10870 23:45:58.045712 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10871 23:45:58.071168 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10872 23:45:58.082430 <46>[ 10.691811] systemd-journald[191]: Received client request to flush runtime journal.
10873 23:45:58.096368 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10874 23:45:58.118861 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10875 23:45:58.142326 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10876 23:45:58.171285 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10877 23:45:58.190581 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10878 23:45:58.210715 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10879 23:45:58.230467 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10880 23:45:58.250523 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10881 23:45:58.309548 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10882 23:45:58.336273 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10883 23:45:58.357539 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10884 23:45:58.376858 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10885 23:45:58.426028 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10886 23:45:58.452526 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10887 23:45:58.472763 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10888 23:45:58.529324 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10889 23:45:58.557851 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10890 23:45:58.586151 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10891 23:45:58.628174 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10892 23:45:58.690545 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10893 23:45:58.711099 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10894 23:45:58.718257 <46>[ 11.331042] systemd-journald[191]: Time jumped backwards, rotating.
10895 23:45:58.818840 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10896 23:45:58.838067 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10897 23:45:58.858213 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10898 23:45:58.878814 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10899 23:45:58.898321 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10900 23:45:58.919192 [[0;32m OK [0m] Listening on [0;1;39mdbus.s<3>[ 11.529560] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10901 23:45:58.929134 ocket[…- D-Bu<3>[ 11.538277] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10902 23:45:58.938759 s System Message<3>[ 11.547901] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10903 23:45:58.938840 Bus Socket.
10904 23:45:58.948884 <3>[ 11.558700] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10905 23:45:58.955960 <6>[ 11.562789] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10906 23:45:58.962170 <6>[ 11.566581] mc: Linux media interface: v0.10
10907 23:45:58.968886 <3>[ 11.566858] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10908 23:45:58.975963 <6>[ 11.569490] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10909 23:45:58.985775 <6>[ 11.574462] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10910 23:45:58.992429 <3>[ 11.578957] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10911 23:45:59.002373 <3>[ 11.578961] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10912 23:45:59.005167 <6>[ 11.582983] remoteproc remoteproc0: scp is available
10913 23:45:59.012202 <6>[ 11.583077] remoteproc remoteproc0: powering up scp
10914 23:45:59.018948 <6>[ 11.583083] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10915 23:45:59.025488 <6>[ 11.583119] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10916 23:45:59.035285 <6>[ 11.587050] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10917 23:45:59.041859 <3>[ 11.594349] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10918 23:45:59.048738 <6>[ 11.625326] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10919 23:45:59.058756 <3>[ 11.631786] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10920 23:45:59.064971 <4>[ 11.632793] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10921 23:45:59.072212 <4>[ 11.636410] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10922 23:45:59.079176 <6>[ 11.638493] videodev: Linux video capture interface: v2.00
10923 23:45:59.085516 <3>[ 11.645367] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10924 23:45:59.095856 <4>[ 11.664918] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10925 23:45:59.099174 <4>[ 11.664918] Fallback method does not support PEC.
10926 23:45:59.109102 <3>[ 11.668468] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10927 23:45:59.115542 <3>[ 11.693252] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10928 23:45:59.126577 <3>[ 11.696675] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10929 23:45:59.133317 <3>[ 11.696783] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10930 23:45:59.139636 <6>[ 11.704400] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10931 23:45:59.149640 <6>[ 11.704447] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10932 23:45:59.156469 <6>[ 11.704456] remoteproc remoteproc0: remote processor scp is now up
10933 23:45:59.166229 <6>[ 11.711192] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10934 23:45:59.172939 <3>[ 11.718390] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10935 23:45:59.183411 <3>[ 11.718394] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10936 23:45:59.190939 <6>[ 11.726850] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10937 23:45:59.198118 <6>[ 11.727596] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10938 23:45:59.205410 <6>[ 11.727601] pci_bus 0000:00: root bus resource [bus 00-ff]
10939 23:45:59.212114 <6>[ 11.727605] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10940 23:45:59.222281 <6>[ 11.727608] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10941 23:45:59.225907 <6>[ 11.727638] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10942 23:45:59.232551 <6>[ 11.727650] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10943 23:45:59.239627 <6>[ 11.727720] pci 0000:00:00.0: supports D1 D2
10944 23:45:59.246620 <6>[ 11.727722] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10945 23:45:59.253794 <6>[ 11.728715] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10946 23:45:59.260614 <6>[ 11.728793] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10947 23:45:59.267010 <6>[ 11.728818] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10948 23:45:59.273934 <6>[ 11.728836] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10949 23:45:59.283463 <6>[ 11.728851] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10950 23:45:59.286949 <6>[ 11.728960] pci 0000:01:00.0: supports D1 D2
10951 23:45:59.293696 <6>[ 11.728962] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10952 23:45:59.303655 <3>[ 11.735240] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10953 23:45:59.310265 <3>[ 11.735243] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10954 23:45:59.316741 <3>[ 11.735266] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10955 23:45:59.326613 <3>[ 11.742311] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10956 23:45:59.333604 <6>[ 11.742436] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10957 23:45:59.340536 <6>[ 11.742496] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10958 23:45:59.350507 <6>[ 11.742501] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10959 23:45:59.356953 <6>[ 11.742514] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10960 23:45:59.367230 <6>[ 11.742527] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10961 23:45:59.373683 <6>[ 11.742540] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10962 23:45:59.380603 <6>[ 11.742553] pci 0000:00:00.0: PCI bridge to [bus 01]
10963 23:45:59.387469 <6>[ 11.742560] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10964 23:45:59.394350 <6>[ 11.742724] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10965 23:45:59.401216 <3>[ 11.743432] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10966 23:45:59.407853 <6>[ 11.743650] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10967 23:45:59.414902 <6>[ 11.744125] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10968 23:45:59.424853 <6>[ 11.746406] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10969 23:45:59.428736 <6>[ 11.775346] Bluetooth: Core ver 2.22
10970 23:45:59.435801 <5>[ 11.776588] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10971 23:45:59.442102 <6>[ 11.777859] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10972 23:45:59.452880 <6>[ 11.782392] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10973 23:45:59.459204 <5>[ 11.789637] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10974 23:45:59.465950 <6>[ 11.791925] NET: Registered PF_BLUETOOTH protocol family
10975 23:45:59.472104 <5>[ 11.800201] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10976 23:45:59.479143 <6>[ 11.800711] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10977 23:45:59.492264 <6>[ 11.802222] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10978 23:45:59.498738 <6>[ 11.802373] usbcore: registered new interface driver uvcvideo
10979 23:45:59.505619 <6>[ 11.809512] Bluetooth: HCI device and connection manager initialized
10980 23:45:59.512153 <3>[ 11.812487] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10981 23:45:59.522017 <3>[ 11.813291] power_supply sbs-5-000b: driver failed to report `current_avg' property: -6
10982 23:45:59.532011 <4>[ 11.815919] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10983 23:45:59.535426 <6>[ 11.822023] Bluetooth: HCI socket layer initialized
10984 23:45:59.545477 <3>[ 11.823475] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10985 23:45:59.551960 <3>[ 11.824312] power_supply sbs-5-000b: driver failed to report `status' property: -6
10986 23:45:59.558553 <6>[ 11.828800] cfg80211: failed to load regulatory.db
10987 23:45:59.561948 <6>[ 11.838699] Bluetooth: L2CAP socket layer initialized
10988 23:45:59.571978 <3>[ 11.844738] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10989 23:45:59.578419 <6>[ 11.853124] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10990 23:45:59.581781 <6>[ 11.857021] Bluetooth: SCO socket layer initialized
10991 23:45:59.591832 <3>[ 11.866527] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10992 23:45:59.598588 <6>[ 11.929481] usbcore: registered new interface driver btusb
10993 23:45:59.608198 <4>[ 11.930331] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10994 23:45:59.614869 <3>[ 11.930351] Bluetooth: hci0: Failed to load firmware file (-2)
10995 23:45:59.621140 <3>[ 11.930353] Bluetooth: hci0: Failed to set up firmware (-2)
10996 23:45:59.631109 <4>[ 11.930371] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10997 23:45:59.638207 <6>[ 11.940032] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10998 23:45:59.648441 <3>[ 11.957637] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10999 23:45:59.651588 <6>[ 11.960618] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11000 23:45:59.660911 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11001 23:45:59.678139 <6>[ 12.291313] mt7921e 0000:01:00.0: ASIC revision: 79610010
11002 23:45:59.717919 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11003 23:45:59.737471 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11004 23:45:59.761713 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11005 23:45:59.782874 <6>[ 12.392898] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
11006 23:45:59.785966 <6>[ 12.392898]
11007 23:45:59.796258 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11008 23:45:59.813731 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11009 23:45:59.833246 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11010 23:45:59.884123 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11011 23:45:59.904453 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11012 23:45:59.921485 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11013 23:45:59.938330 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11014 23:45:59.958384 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11015 23:46:00.017635 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11016 23:46:00.042218 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11017 23:46:00.052689 <6>[ 12.662271] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
11018 23:46:00.067178 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11019 23:46:00.087585 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11020 23:46:00.142755 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11021 23:46:00.167615 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11022 23:46:00.186487 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11023 23:46:00.201716 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11024 23:46:00.221458 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11025 23:46:00.286508 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11026 23:46:00.310198 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11027 23:46:00.331674 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11028 23:46:00.363584 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11029 23:46:00.405958
11030 23:46:00.409405 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11031 23:46:00.409504
11032 23:46:00.413048 debian-bookworm-arm64 login: root (automatic login)
11033 23:46:00.413132
11034 23:46:00.425409 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Tue Jun 4 23:28:43 UTC 2024 aarch64
11035 23:46:00.425494
11036 23:46:00.432487 The programs included with the Debian GNU/Linux system are free software;
11037 23:46:00.438792 the exact distribution terms for each program are described in the
11038 23:46:00.442110 individual files in /usr/share/doc/*/copyright.
11039 23:46:00.442194
11040 23:46:00.448552 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11041 23:46:00.451846 permitted by applicable law.
11042 23:46:00.452231 Matched prompt #10: / #
11044 23:46:00.452457 Setting prompt string to ['/ #']
11045 23:46:00.452568 end: 2.2.5.1 login-action (duration 00:00:14) [common]
11047 23:46:00.452883 end: 2.2.5 auto-login-action (duration 00:00:14) [common]
11048 23:46:00.453057 start: 2.2.6 expect-shell-connection (timeout 00:03:02) [common]
11049 23:46:00.453153 Setting prompt string to ['/ #']
11050 23:46:00.453226 Forcing a shell prompt, looking for ['/ #']
11052 23:46:00.503514 / #
11053 23:46:00.503630 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11054 23:46:00.503714 Waiting using forced prompt support (timeout 00:02:30)
11055 23:46:00.508757
11056 23:46:00.509064 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11057 23:46:00.509179 start: 2.2.7 export-device-env (timeout 00:03:01) [common]
11058 23:46:00.509288 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11059 23:46:00.509390 end: 2.2 depthcharge-retry (duration 00:01:59) [common]
11060 23:46:00.509487 end: 2 depthcharge-action (duration 00:01:59) [common]
11061 23:46:00.509588 start: 3 lava-test-retry (timeout 00:07:39) [common]
11062 23:46:00.509690 start: 3.1 lava-test-shell (timeout 00:07:39) [common]
11063 23:46:00.509801 Using namespace: common
11065 23:46:00.610220 / # #
11066 23:46:00.610376 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11067 23:46:00.615866 #
11068 23:46:00.616135 Using /lava-14172956
11070 23:46:00.716478 / # export SHELL=/bin/sh
11071 23:46:00.721722 export SHELL=/bin/sh
11073 23:46:00.822297 / # . /lava-14172956/environment
11074 23:46:00.827977 . /lava-14172956/environment
11076 23:46:00.928522 / # /lava-14172956/bin/lava-test-runner /lava-14172956/0
11077 23:46:00.928703 Test shell timeout: 10s (minimum of the action and connection timeout)
11078 23:46:00.929162 /lava-14172956/bin/lava-test-runner /lava-14172956/0<6>[ 13.538811] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11079 23:46:00.933735
11080 23:46:00.977172 + export TESTRUN_ID=0_v4l2-compliance-mtk-vcodec-enc
11081 23:46:00.977297 + cd /lava-14172956/0/tests/0_v4l2-compliance-mtk-vcodec-enc
11082 23:46:00.977388 + cat uuid
11083 23:46:00.977468 + UUID=14172956_1.5.2.3.1
11084 23:46:00.977547 + set +x
11085 23:46:00.977643 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-mtk-vcodec-enc 14172956_1.5.2.3.1>
11086 23:46:00.977925 Received signal: <STARTRUN> 0_v4l2-compliance-mtk-vcodec-enc 14172956_1.5.2.3.1
11087 23:46:00.978025 Starting test lava.0_v4l2-compliance-mtk-vcodec-enc (14172956_1.5.2.3.1)
11088 23:46:00.978147 Skipping test definition patterns.
11089 23:46:00.978291 + /usr/bin/v4l2-parser.sh -d mtk-vcodec-enc
11090 23:46:00.984405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
11091 23:46:00.984489 device: /dev/video2
11092 23:46:00.984762 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
11094 23:46:00.996871 <4>[ 13.606680] use of bytesused == 0 is deprecated and will be removed in the future,
11095 23:46:00.999932 <4>[ 13.614548] use the actual size instead.
11096 23:46:01.024236 v4l2-compliance 1.27.0-1, 64 bits, 64-bit time_t
11097 23:46:01.041493 v4l2-compliance SHA: a18611d8960f 2024-03-08 13:09:54
11098 23:46:01.048524
11099 23:46:01.060902 Compliance test for mtk-vcodec-enc device /dev/video2:
11100 23:46:01.066253
11101 23:46:01.075902 Driver Info:
11102 23:46:01.084931 Driver name : mtk-vcodec-enc
11103 23:46:01.100032 Card type : MT8192 video encoder
11104 23:46:01.110008 Bus info : platform:17020000.vcodec
11105 23:46:01.116701 Driver version : 6.1.92
11106 23:46:01.127142 Capabilities : 0x84204000
11107 23:46:01.139722 Video Memory-to-Memory Multiplanar
11108 23:46:01.150312 Streaming
11109 23:46:01.162343 Extended Pix Format
11110 23:46:01.174563 Device Capabilities
11111 23:46:01.186491 Device Caps : 0x04204000
11112 23:46:01.197120 Video Memory-to-Memory Multiplanar
11113 23:46:01.211053 Streaming
11114 23:46:01.220810 Extended Pix Format
11115 23:46:01.230520 Detected Stateful Encoder
11116 23:46:01.241498
11117 23:46:01.252008 Required ioctls:
11118 23:46:01.271297 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11119 23:46:01.271385 test VIDIOC_QUERYCAP: OK
11120 23:46:01.271625 Received signal: <TESTSET> START Required-ioctls
11121 23:46:01.271696 Starting test_set Required-ioctls
11122 23:46:01.295813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11123 23:46:01.296114 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11125 23:46:01.298600 test invalid ioctls: OK
11126 23:46:01.320948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11127 23:46:01.321079
11128 23:46:01.321314 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11130 23:46:01.332567 Allow for multiple opens:
11131 23:46:01.342276 <LAVA_SIGNAL_TESTSET STOP>
11132 23:46:01.342530 Received signal: <TESTSET> STOP
11133 23:46:01.342604 Closing test_set Required-ioctls
11134 23:46:01.352365 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11135 23:46:01.352617 Received signal: <TESTSET> START Allow-for-multiple-opens
11136 23:46:01.352684 Starting test_set Allow-for-multiple-opens
11137 23:46:01.355722 test second /dev/video2 open: OK
11138 23:46:01.382244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video2-open RESULT=pass>
11139 23:46:01.382529 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video2-open RESULT=pass
11141 23:46:01.385128 test VIDIOC_QUERYCAP: OK
11142 23:46:01.410290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11143 23:46:01.410595 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11145 23:46:01.413582 test VIDIOC_G/S_PRIORITY: OK
11146 23:46:01.435096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11147 23:46:01.435433 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11149 23:46:01.438337 test for unlimited opens: OK
11150 23:46:01.459889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11151 23:46:01.460032
11152 23:46:01.460300 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11154 23:46:01.471146 Debug ioctls:
11155 23:46:01.477302 <LAVA_SIGNAL_TESTSET STOP>
11156 23:46:01.477563 Received signal: <TESTSET> STOP
11157 23:46:01.477632 Closing test_set Allow-for-multiple-opens
11158 23:46:01.487077 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11159 23:46:01.487357 Received signal: <TESTSET> START Debug-ioctls
11160 23:46:01.487458 Starting test_set Debug-ioctls
11161 23:46:01.489929 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11162 23:46:01.516249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11163 23:46:01.516529 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11165 23:46:01.522257 test VIDIOC_LOG_STATUS: OK (Not Supported)
11166 23:46:01.540166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11167 23:46:01.540268
11168 23:46:01.540507 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11170 23:46:01.550717 Input ioctls:
11171 23:46:01.557107 <LAVA_SIGNAL_TESTSET STOP>
11172 23:46:01.557364 Received signal: <TESTSET> STOP
11173 23:46:01.557433 Closing test_set Debug-ioctls
11174 23:46:01.566024 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11175 23:46:01.566277 Received signal: <TESTSET> START Input-ioctls
11176 23:46:01.566347 Starting test_set Input-ioctls
11177 23:46:01.569422 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11178 23:46:01.595696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11179 23:46:01.595973 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11181 23:46:01.598372 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11182 23:46:01.617992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11183 23:46:01.618259 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11185 23:46:01.624805 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11186 23:46:01.642264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11187 23:46:01.642536 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11189 23:46:01.646429 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11190 23:46:01.667221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11191 23:46:01.667493 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11193 23:46:01.670352 test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
11194 23:46:01.695720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11195 23:46:01.695999 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11197 23:46:01.698802 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11198 23:46:01.723410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11199 23:46:01.723689 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11201 23:46:01.726883 Inputs: 0 Audio Inputs: 0 Tuners: 0
11202 23:46:01.734888
11203 23:46:01.756474 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11204 23:46:01.779795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11205 23:46:01.780087 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11207 23:46:01.786510 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11208 23:46:01.803512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11209 23:46:01.803778 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11211 23:46:01.806928 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11212 23:46:01.827575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11213 23:46:01.827847 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11215 23:46:01.834258 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11216 23:46:01.851081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11217 23:46:01.851361 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11219 23:46:01.857783 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11220 23:46:01.877368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11221 23:46:01.877512
11222 23:46:01.877781 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11224 23:46:01.902471 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11225 23:46:01.923777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11226 23:46:01.924087 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11228 23:46:01.930524 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11229 23:46:01.951549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11230 23:46:01.951834 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11232 23:46:01.954922 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11233 23:46:01.975725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11234 23:46:01.976008 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11236 23:46:01.979080 test VIDIOC_G/S_EDID: OK (Not Supported)
11237 23:46:02.000581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11238 23:46:02.000706
11239 23:46:02.000986 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11241 23:46:02.011667 Control ioctls:
11242 23:46:02.018409 <LAVA_SIGNAL_TESTSET STOP>
11243 23:46:02.018664 Received signal: <TESTSET> STOP
11244 23:46:02.018738 Closing test_set Input-ioctls
11245 23:46:02.027829 <LAVA_SIGNAL_TESTSET START Control-ioctls>
11246 23:46:02.028085 Received signal: <TESTSET> START Control-ioctls
11247 23:46:02.028158 Starting test_set Control-ioctls
11248 23:46:02.030925 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11249 23:46:02.055126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11250 23:46:02.055216 test VIDIOC_QUERYCTRL: OK
11251 23:46:02.055470 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11253 23:46:02.075826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11254 23:46:02.076110 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11256 23:46:02.079305 test VIDIOC_G/S_CTRL: OK
11257 23:46:02.101568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11258 23:46:02.101828 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11260 23:46:02.104723 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11261 23:46:02.125180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11262 23:46:02.125443 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11264 23:46:02.131933 fail: v4l2-test-controls.cpp(1167): node->codec_mask & STATEFUL_ENCODER
11265 23:46:02.138191 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: FAIL
11266 23:46:02.163795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail>
11267 23:46:02.164063 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail
11269 23:46:02.166555 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11270 23:46:02.186448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11271 23:46:02.186711 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11273 23:46:02.189684 Standard Controls: 16 Private Controls: 0
11274 23:46:02.196925
11275 23:46:02.207373 Format ioctls:
11276 23:46:02.213424 <LAVA_SIGNAL_TESTSET STOP>
11277 23:46:02.213678 Received signal: <TESTSET> STOP
11278 23:46:02.213753 Closing test_set Control-ioctls
11279 23:46:02.223595 <LAVA_SIGNAL_TESTSET START Format-ioctls>
11280 23:46:02.223851 Received signal: <TESTSET> START Format-ioctls
11281 23:46:02.223926 Starting test_set Format-ioctls
11282 23:46:02.226565 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11283 23:46:02.252178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11284 23:46:02.252440 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11286 23:46:02.255362 test VIDIOC_G/S_PARM: OK
11287 23:46:02.275565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11288 23:46:02.275832 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11290 23:46:02.279089 test VIDIOC_G_FBUF: OK (Not Supported)
11291 23:46:02.299927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11292 23:46:02.300189 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11294 23:46:02.303161 test VIDIOC_G_FMT: OK
11295 23:46:02.323349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11296 23:46:02.323607 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11298 23:46:02.326082 test VIDIOC_TRY_FMT: OK
11299 23:46:02.348013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11300 23:46:02.348274 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11302 23:46:02.355058 fail: v4l2-test-formats.cpp(924): sel.r.width != fmt.g_width()
11303 23:46:02.358984 test VIDIOC_S_FMT: FAIL
11304 23:46:02.383779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail>
11305 23:46:02.384073 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail
11307 23:46:02.387177 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11308 23:46:02.409580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11309 23:46:02.409846 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11311 23:46:02.412624 test Cropping: OK
11312 23:46:02.433866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11313 23:46:02.434129 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11315 23:46:02.437619 test Composing: OK (Not Supported)
11316 23:46:02.459575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11317 23:46:02.459834 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11319 23:46:02.462905 test Scaling: OK (Not Supported)
11320 23:46:02.486411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11321 23:46:02.486497
11322 23:46:02.486751 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11324 23:46:02.498645 Codec ioctls:
11325 23:46:02.504261 <LAVA_SIGNAL_TESTSET STOP>
11326 23:46:02.504516 Received signal: <TESTSET> STOP
11327 23:46:02.504589 Closing test_set Format-ioctls
11328 23:46:02.513547 <LAVA_SIGNAL_TESTSET START Codec-ioctls>
11329 23:46:02.513801 Received signal: <TESTSET> START Codec-ioctls
11330 23:46:02.513876 Starting test_set Codec-ioctls
11331 23:46:02.516710 test VIDIOC_(TRY_)ENCODER_CMD: OK
11332 23:46:02.543405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11333 23:46:02.543663 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11335 23:46:02.549330 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11336 23:46:02.566735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11337 23:46:02.566991 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11339 23:46:02.573683 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11340 23:46:02.599384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11341 23:46:02.599470
11342 23:46:02.599725 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11344 23:46:02.611649 Buffer ioctls:
11345 23:46:02.620570 <LAVA_SIGNAL_TESTSET STOP>
11346 23:46:02.620827 Received signal: <TESTSET> STOP
11347 23:46:02.620925 Closing test_set Codec-ioctls
11348 23:46:02.631401 <LAVA_SIGNAL_TESTSET START Buffer-ioctls>
11349 23:46:02.631657 Received signal: <TESTSET> START Buffer-ioctls
11350 23:46:02.631732 Starting test_set Buffer-ioctls
11351 23:46:02.634712 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11352 23:46:02.659796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11353 23:46:02.660052 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11355 23:46:02.663463 test CREATE_BUFS maximum buffers: OK
11356 23:46:02.682569 Received signal: <TESTCASE> TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass
11358 23:46:02.685900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass>
11359 23:46:02.685984 test VIDIOC_EXPBUF: OK
11360 23:46:02.705507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11361 23:46:02.705763 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11363 23:46:02.708700 test Requests: OK (Not Supported)
11364 23:46:02.728682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11365 23:46:02.728767
11366 23:46:02.728997 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11368 23:46:02.738964 Test input 0:
11369 23:46:02.748105
11370 23:46:02.758936 Streaming ioctls:
11371 23:46:02.766826 <LAVA_SIGNAL_TESTSET STOP>
11372 23:46:02.767085 Received signal: <TESTSET> STOP
11373 23:46:02.767159 Closing test_set Buffer-ioctls
11374 23:46:02.776293 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11375 23:46:02.776550 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11376 23:46:02.776625 Starting test_set Streaming-ioctls_Test-input-0
11377 23:46:02.779884 test read/write: OK (Not Supported)
11378 23:46:02.802162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11379 23:46:02.802417 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11381 23:46:02.808905 fail: v4l2-test-buffers.cpp(2829): node->streamon(q.g_type())
11382 23:46:02.819083 fail: v4l2-test-buffers.cpp(2876): testBlockingDQBuf(node, q)
11383 23:46:02.826073 test blocking wait: FAIL
11384 23:46:02.850358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=fail>
11385 23:46:02.850618 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=fail
11387 23:46:02.856805 fail: v4l2-test-buffers.cpp(1461): node->streamon(q.g_type())
11388 23:46:02.861211 test MMAP (select): FAIL
11389 23:46:02.886875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11390 23:46:02.887140 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11392 23:46:02.893217 fail: v4l2-test-buffers.cpp(1461): node->streamon(q.g_type())
11393 23:46:02.896392 test MMAP (epoll): FAIL
11394 23:46:02.921062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11395 23:46:02.921319 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11397 23:46:02.927839 fail: v4l2-test-buffers.cpp(1633): ret && ret != ENOTTY (got 22)
11398 23:46:02.936161 fail: v4l2-test-buffers.cpp(1764): setupUserPtr(node, q)
11399 23:46:02.943775 test USERPTR (select): FAIL
11400 23:46:02.972540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=fail>
11401 23:46:02.972826 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=fail
11403 23:46:02.979106 test DMABUF: Cannot test, specify --expbuf-device
11404 23:46:02.982732
11405 23:46:03.005922 Total for mtk-vcodec-enc device /dev/video2: 51, Succeeded: 45, Failed: 6, Warnings: 0
11406 23:46:03.009551 <LAVA_TEST_RUNNER EXIT>
11407 23:46:03.009808 ok: lava_test_shell seems to have completed
11408 23:46:03.009888 Marking unfinished test run as failed
11410 23:46:03.010839 CREATE_BUFS-maximum-buffers:
result: pass
set: Buffer-ioctls
Composing:
result: pass
set: Format-ioctls
Cropping:
result: pass
set: Format-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls
Scaling:
result: pass
set: Format-ioctls
USERPTR-select:
result: fail
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls
VIDIOC_G_FMT:
result: pass
set: Format-ioctls
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls
VIDIOC_S_FMT:
result: fail
set: Format-ioctls
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: fail
set: Control-ioctls
blocking-wait:
result: fail
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video2-open:
result: pass
set: Allow-for-multiple-opens
11411 23:46:03.010974 end: 3.1 lava-test-shell (duration 00:00:03) [common]
11412 23:46:03.011072 end: 3 lava-test-retry (duration 00:00:03) [common]
11413 23:46:03.011174 start: 4 finalize (timeout 00:07:37) [common]
11414 23:46:03.011276 start: 4.1 power-off (timeout 00:00:30) [common]
11415 23:46:03.011537 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-3', '--port=1', '--command=off']
11416 23:46:03.087113 >> Command sent successfully.
11417 23:46:03.089637 Returned 0 in 0 seconds
11418 23:46:03.190434 end: 4.1 power-off (duration 00:00:00) [common]
11420 23:46:03.192017 start: 4.2 read-feedback (timeout 00:07:37) [common]
11421 23:46:03.193075 Listened to connection for namespace 'common' for up to 1s
11422 23:46:04.193069 Finalising connection for namespace 'common'
11423 23:46:04.193244 Disconnecting from shell: Finalise
11424 23:46:04.193320 / #
11425 23:46:04.293875 end: 4.2 read-feedback (duration 00:00:01) [common]
11426 23:46:04.294538 end: 4 finalize (duration 00:00:01) [common]
11427 23:46:04.295076 Cleaning after the job
11428 23:46:04.295554 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14172956/tftp-deploy-mv6oeqmu/ramdisk
11429 23:46:04.314857 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14172956/tftp-deploy-mv6oeqmu/kernel
11430 23:46:04.345416 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14172956/tftp-deploy-mv6oeqmu/dtb
11431 23:46:04.345732 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14172956/tftp-deploy-mv6oeqmu/modules
11432 23:46:04.353160 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14172956
11433 23:46:04.416331 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14172956
11434 23:46:04.416516 Job finished correctly