Boot log: mt8192-asurada-spherion-r0
- Errors: 1
- Kernel Errors: 29
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
1 23:44:30.014095 lava-dispatcher, installed at version: 2024.03
2 23:44:30.014327 start: 0 validate
3 23:44:30.014504 Start time: 2024-06-04 23:44:30.014495+00:00 (UTC)
4 23:44:30.014674 Using caching service: 'http://localhost/cache/?uri=%s'
5 23:44:30.014872 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-v4l2%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 23:44:30.277942 Using caching service: 'http://localhost/cache/?uri=%s'
7 23:44:30.278191 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 23:44:30.527974 Using caching service: 'http://localhost/cache/?uri=%s'
9 23:44:30.528192 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 23:44:30.786439 Using caching service: 'http://localhost/cache/?uri=%s'
11 23:44:30.786673 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 23:44:31.038008 validate duration: 1.02
14 23:44:31.038453 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 23:44:31.038641 start: 1.1 download-retry (timeout 00:10:00) [common]
16 23:44:31.038809 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 23:44:31.039014 Not decompressing ramdisk as can be used compressed.
18 23:44:31.039153 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-v4l2/20240313.0/arm64/rootfs.cpio.gz
19 23:44:31.039272 saving as /var/lib/lava/dispatcher/tmp/14172972/tftp-deploy-6oanwx39/ramdisk/rootfs.cpio.gz
20 23:44:31.039391 total size: 28105535 (26 MB)
21 23:44:31.041038 progress 0 % (0 MB)
22 23:44:31.051498 progress 5 % (1 MB)
23 23:44:31.062450 progress 10 % (2 MB)
24 23:44:31.072852 progress 15 % (4 MB)
25 23:44:31.080384 progress 20 % (5 MB)
26 23:44:31.087766 progress 25 % (6 MB)
27 23:44:31.094953 progress 30 % (8 MB)
28 23:44:31.102190 progress 35 % (9 MB)
29 23:44:31.109615 progress 40 % (10 MB)
30 23:44:31.117060 progress 45 % (12 MB)
31 23:44:31.124353 progress 50 % (13 MB)
32 23:44:31.131566 progress 55 % (14 MB)
33 23:44:31.138810 progress 60 % (16 MB)
34 23:44:31.146057 progress 65 % (17 MB)
35 23:44:31.153398 progress 70 % (18 MB)
36 23:44:31.160714 progress 75 % (20 MB)
37 23:44:31.168352 progress 80 % (21 MB)
38 23:44:31.176065 progress 85 % (22 MB)
39 23:44:31.183324 progress 90 % (24 MB)
40 23:44:31.190897 progress 95 % (25 MB)
41 23:44:31.198426 progress 100 % (26 MB)
42 23:44:31.198645 26 MB downloaded in 0.16 s (168.30 MB/s)
43 23:44:31.198804 end: 1.1.1 http-download (duration 00:00:00) [common]
45 23:44:31.199077 end: 1.1 download-retry (duration 00:00:00) [common]
46 23:44:31.199164 start: 1.2 download-retry (timeout 00:10:00) [common]
47 23:44:31.199249 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 23:44:31.199373 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 23:44:31.199442 saving as /var/lib/lava/dispatcher/tmp/14172972/tftp-deploy-6oanwx39/kernel/Image
50 23:44:31.199507 total size: 54682112 (52 MB)
51 23:44:31.199569 No compression specified
52 23:44:31.200675 progress 0 % (0 MB)
53 23:44:31.215277 progress 5 % (2 MB)
54 23:44:31.229671 progress 10 % (5 MB)
55 23:44:31.244056 progress 15 % (7 MB)
56 23:44:31.258525 progress 20 % (10 MB)
57 23:44:31.273249 progress 25 % (13 MB)
58 23:44:31.288792 progress 30 % (15 MB)
59 23:44:31.306147 progress 35 % (18 MB)
60 23:44:31.322513 progress 40 % (20 MB)
61 23:44:31.339606 progress 45 % (23 MB)
62 23:44:31.355657 progress 50 % (26 MB)
63 23:44:31.370807 progress 55 % (28 MB)
64 23:44:31.384813 progress 60 % (31 MB)
65 23:44:31.398722 progress 65 % (33 MB)
66 23:44:31.412915 progress 70 % (36 MB)
67 23:44:31.427730 progress 75 % (39 MB)
68 23:44:31.442449 progress 80 % (41 MB)
69 23:44:31.456775 progress 85 % (44 MB)
70 23:44:31.471132 progress 90 % (46 MB)
71 23:44:31.485336 progress 95 % (49 MB)
72 23:44:31.499262 progress 100 % (52 MB)
73 23:44:31.499517 52 MB downloaded in 0.30 s (173.83 MB/s)
74 23:44:31.499670 end: 1.2.1 http-download (duration 00:00:00) [common]
76 23:44:31.499927 end: 1.2 download-retry (duration 00:00:00) [common]
77 23:44:31.500045 start: 1.3 download-retry (timeout 00:10:00) [common]
78 23:44:31.500133 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 23:44:31.500283 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 23:44:31.500387 saving as /var/lib/lava/dispatcher/tmp/14172972/tftp-deploy-6oanwx39/dtb/mt8192-asurada-spherion-r0.dtb
81 23:44:31.500479 total size: 47258 (0 MB)
82 23:44:31.500577 No compression specified
83 23:44:31.502274 progress 69 % (0 MB)
84 23:44:31.502611 progress 100 % (0 MB)
85 23:44:31.502801 0 MB downloaded in 0.00 s (19.44 MB/s)
86 23:44:31.502973 end: 1.3.1 http-download (duration 00:00:00) [common]
88 23:44:31.503330 end: 1.3 download-retry (duration 00:00:00) [common]
89 23:44:31.503445 start: 1.4 download-retry (timeout 00:10:00) [common]
90 23:44:31.503573 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 23:44:31.503721 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 23:44:31.503817 saving as /var/lib/lava/dispatcher/tmp/14172972/tftp-deploy-6oanwx39/modules/modules.tar
93 23:44:31.503907 total size: 8603924 (8 MB)
94 23:44:31.503997 Using unxz to decompress xz
95 23:44:31.508098 progress 0 % (0 MB)
96 23:44:31.531622 progress 5 % (0 MB)
97 23:44:31.558290 progress 10 % (0 MB)
98 23:44:31.587302 progress 15 % (1 MB)
99 23:44:31.617078 progress 20 % (1 MB)
100 23:44:31.646292 progress 25 % (2 MB)
101 23:44:31.674257 progress 30 % (2 MB)
102 23:44:31.698129 progress 35 % (2 MB)
103 23:44:31.726625 progress 40 % (3 MB)
104 23:44:31.751639 progress 45 % (3 MB)
105 23:44:31.776753 progress 50 % (4 MB)
106 23:44:31.802443 progress 55 % (4 MB)
107 23:44:31.827988 progress 60 % (4 MB)
108 23:44:31.854894 progress 65 % (5 MB)
109 23:44:31.882866 progress 70 % (5 MB)
110 23:44:31.911972 progress 75 % (6 MB)
111 23:44:31.941173 progress 80 % (6 MB)
112 23:44:31.970459 progress 85 % (7 MB)
113 23:44:32.003074 progress 90 % (7 MB)
114 23:44:32.037855 progress 95 % (7 MB)
115 23:44:32.068191 progress 100 % (8 MB)
116 23:44:32.074095 8 MB downloaded in 0.57 s (14.39 MB/s)
117 23:44:32.074465 end: 1.4.1 http-download (duration 00:00:01) [common]
119 23:44:32.074931 end: 1.4 download-retry (duration 00:00:01) [common]
120 23:44:32.075087 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 23:44:32.075243 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 23:44:32.075386 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 23:44:32.075533 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 23:44:32.075866 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14172972/lava-overlay-9uh_xggz
125 23:44:32.076084 makedir: /var/lib/lava/dispatcher/tmp/14172972/lava-overlay-9uh_xggz/lava-14172972/bin
126 23:44:32.076260 makedir: /var/lib/lava/dispatcher/tmp/14172972/lava-overlay-9uh_xggz/lava-14172972/tests
127 23:44:32.076418 makedir: /var/lib/lava/dispatcher/tmp/14172972/lava-overlay-9uh_xggz/lava-14172972/results
128 23:44:32.076612 Creating /var/lib/lava/dispatcher/tmp/14172972/lava-overlay-9uh_xggz/lava-14172972/bin/lava-add-keys
129 23:44:32.076843 Creating /var/lib/lava/dispatcher/tmp/14172972/lava-overlay-9uh_xggz/lava-14172972/bin/lava-add-sources
130 23:44:32.077054 Creating /var/lib/lava/dispatcher/tmp/14172972/lava-overlay-9uh_xggz/lava-14172972/bin/lava-background-process-start
131 23:44:32.077269 Creating /var/lib/lava/dispatcher/tmp/14172972/lava-overlay-9uh_xggz/lava-14172972/bin/lava-background-process-stop
132 23:44:32.077473 Creating /var/lib/lava/dispatcher/tmp/14172972/lava-overlay-9uh_xggz/lava-14172972/bin/lava-common-functions
133 23:44:32.077676 Creating /var/lib/lava/dispatcher/tmp/14172972/lava-overlay-9uh_xggz/lava-14172972/bin/lava-echo-ipv4
134 23:44:32.077884 Creating /var/lib/lava/dispatcher/tmp/14172972/lava-overlay-9uh_xggz/lava-14172972/bin/lava-install-packages
135 23:44:32.078086 Creating /var/lib/lava/dispatcher/tmp/14172972/lava-overlay-9uh_xggz/lava-14172972/bin/lava-installed-packages
136 23:44:32.078293 Creating /var/lib/lava/dispatcher/tmp/14172972/lava-overlay-9uh_xggz/lava-14172972/bin/lava-os-build
137 23:44:32.078496 Creating /var/lib/lava/dispatcher/tmp/14172972/lava-overlay-9uh_xggz/lava-14172972/bin/lava-probe-channel
138 23:44:32.078700 Creating /var/lib/lava/dispatcher/tmp/14172972/lava-overlay-9uh_xggz/lava-14172972/bin/lava-probe-ip
139 23:44:32.078903 Creating /var/lib/lava/dispatcher/tmp/14172972/lava-overlay-9uh_xggz/lava-14172972/bin/lava-target-ip
140 23:44:32.079108 Creating /var/lib/lava/dispatcher/tmp/14172972/lava-overlay-9uh_xggz/lava-14172972/bin/lava-target-mac
141 23:44:32.079311 Creating /var/lib/lava/dispatcher/tmp/14172972/lava-overlay-9uh_xggz/lava-14172972/bin/lava-target-storage
142 23:44:32.079524 Creating /var/lib/lava/dispatcher/tmp/14172972/lava-overlay-9uh_xggz/lava-14172972/bin/lava-test-case
143 23:44:32.079729 Creating /var/lib/lava/dispatcher/tmp/14172972/lava-overlay-9uh_xggz/lava-14172972/bin/lava-test-event
144 23:44:32.079932 Creating /var/lib/lava/dispatcher/tmp/14172972/lava-overlay-9uh_xggz/lava-14172972/bin/lava-test-feedback
145 23:44:32.080139 Creating /var/lib/lava/dispatcher/tmp/14172972/lava-overlay-9uh_xggz/lava-14172972/bin/lava-test-raise
146 23:44:32.080339 Creating /var/lib/lava/dispatcher/tmp/14172972/lava-overlay-9uh_xggz/lava-14172972/bin/lava-test-reference
147 23:44:32.080547 Creating /var/lib/lava/dispatcher/tmp/14172972/lava-overlay-9uh_xggz/lava-14172972/bin/lava-test-runner
148 23:44:32.080771 Creating /var/lib/lava/dispatcher/tmp/14172972/lava-overlay-9uh_xggz/lava-14172972/bin/lava-test-set
149 23:44:32.080978 Creating /var/lib/lava/dispatcher/tmp/14172972/lava-overlay-9uh_xggz/lava-14172972/bin/lava-test-shell
150 23:44:32.081188 Updating /var/lib/lava/dispatcher/tmp/14172972/lava-overlay-9uh_xggz/lava-14172972/bin/lava-install-packages (oe)
151 23:44:32.081426 Updating /var/lib/lava/dispatcher/tmp/14172972/lava-overlay-9uh_xggz/lava-14172972/bin/lava-installed-packages (oe)
152 23:44:32.081624 Creating /var/lib/lava/dispatcher/tmp/14172972/lava-overlay-9uh_xggz/lava-14172972/environment
153 23:44:32.081786 LAVA metadata
154 23:44:32.081911 - LAVA_JOB_ID=14172972
155 23:44:32.082033 - LAVA_DISPATCHER_IP=192.168.201.1
156 23:44:32.082210 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 23:44:32.082330 skipped lava-vland-overlay
158 23:44:32.082465 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 23:44:32.082613 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 23:44:32.082755 skipped lava-multinode-overlay
161 23:44:32.082887 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 23:44:32.083037 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 23:44:32.083166 Loading test definitions
164 23:44:32.083329 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 23:44:32.083455 Using /lava-14172972 at stage 0
166 23:44:32.083900 uuid=14172972_1.5.2.3.1 testdef=None
167 23:44:32.084022 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 23:44:32.084146 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 23:44:32.084886 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 23:44:32.085242 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 23:44:32.086135 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 23:44:32.086518 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 23:44:32.087403 runner path: /var/lib/lava/dispatcher/tmp/14172972/lava-overlay-9uh_xggz/lava-14172972/0/tests/0_v4l2-compliance-uvc test_uuid 14172972_1.5.2.3.1
176 23:44:32.087614 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 23:44:32.087958 Creating lava-test-runner.conf files
179 23:44:32.088051 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14172972/lava-overlay-9uh_xggz/lava-14172972/0 for stage 0
180 23:44:32.088172 - 0_v4l2-compliance-uvc
181 23:44:32.088301 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 23:44:32.088420 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 23:44:32.095911 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 23:44:32.096048 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 23:44:32.096139 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 23:44:32.096226 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 23:44:32.096312 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 23:44:33.075112 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 23:44:33.075670 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 23:44:33.075865 extracting modules file /var/lib/lava/dispatcher/tmp/14172972/tftp-deploy-6oanwx39/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14172972/extract-overlay-ramdisk-ocev7j28/ramdisk
191 23:44:33.385296 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 23:44:33.385472 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 23:44:33.385563 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14172972/compress-overlay-2ljunc0c/overlay-1.5.2.4.tar.gz to ramdisk
194 23:44:33.385634 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14172972/compress-overlay-2ljunc0c/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14172972/extract-overlay-ramdisk-ocev7j28/ramdisk
195 23:44:33.393999 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 23:44:33.394120 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 23:44:33.394221 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 23:44:33.394319 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 23:44:33.394436 Building ramdisk /var/lib/lava/dispatcher/tmp/14172972/extract-overlay-ramdisk-ocev7j28/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14172972/extract-overlay-ramdisk-ocev7j28/ramdisk
200 23:44:34.089681 >> 275883 blocks
201 23:44:38.319009 rename /var/lib/lava/dispatcher/tmp/14172972/extract-overlay-ramdisk-ocev7j28/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14172972/tftp-deploy-6oanwx39/ramdisk/ramdisk.cpio.gz
202 23:44:38.319481 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 23:44:38.319660 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
204 23:44:38.319758 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
205 23:44:38.319868 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14172972/tftp-deploy-6oanwx39/kernel/Image']
206 23:44:53.064215 Returned 0 in 14 seconds
207 23:44:53.164860 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14172972/tftp-deploy-6oanwx39/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14172972/tftp-deploy-6oanwx39/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14172972/tftp-deploy-6oanwx39/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14172972/tftp-deploy-6oanwx39/kernel/image.itb
208 23:44:53.842178 output: FIT description: Kernel Image image with one or more FDT blobs
209 23:44:53.842582 output: Created: Wed Jun 5 00:44:53 2024
210 23:44:53.842686 output: Image 0 (kernel-1)
211 23:44:53.842782 output: Description:
212 23:44:53.842873 output: Created: Wed Jun 5 00:44:53 2024
213 23:44:53.842964 output: Type: Kernel Image
214 23:44:53.843056 output: Compression: lzma compressed
215 23:44:53.843150 output: Data Size: 13061430 Bytes = 12755.30 KiB = 12.46 MiB
216 23:44:53.843244 output: Architecture: AArch64
217 23:44:53.843334 output: OS: Linux
218 23:44:53.843425 output: Load Address: 0x00000000
219 23:44:53.843513 output: Entry Point: 0x00000000
220 23:44:53.843604 output: Hash algo: crc32
221 23:44:53.843691 output: Hash value: ecfb5096
222 23:44:53.843777 output: Image 1 (fdt-1)
223 23:44:53.843861 output: Description: mt8192-asurada-spherion-r0
224 23:44:53.843948 output: Created: Wed Jun 5 00:44:53 2024
225 23:44:53.844032 output: Type: Flat Device Tree
226 23:44:53.844116 output: Compression: uncompressed
227 23:44:53.844200 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 23:44:53.844284 output: Architecture: AArch64
229 23:44:53.844367 output: Hash algo: crc32
230 23:44:53.844451 output: Hash value: 0f8e4d2e
231 23:44:53.844535 output: Image 2 (ramdisk-1)
232 23:44:53.844630 output: Description: unavailable
233 23:44:53.844714 output: Created: Wed Jun 5 00:44:53 2024
234 23:44:53.844798 output: Type: RAMDisk Image
235 23:44:53.844882 output: Compression: Unknown Compression
236 23:44:53.844966 output: Data Size: 41208553 Bytes = 40242.73 KiB = 39.30 MiB
237 23:44:53.845051 output: Architecture: AArch64
238 23:44:53.845134 output: OS: Linux
239 23:44:53.845218 output: Load Address: unavailable
240 23:44:53.845301 output: Entry Point: unavailable
241 23:44:53.845385 output: Hash algo: crc32
242 23:44:53.845468 output: Hash value: cc561909
243 23:44:53.845552 output: Default Configuration: 'conf-1'
244 23:44:53.845635 output: Configuration 0 (conf-1)
245 23:44:53.845718 output: Description: mt8192-asurada-spherion-r0
246 23:44:53.845802 output: Kernel: kernel-1
247 23:44:53.845885 output: Init Ramdisk: ramdisk-1
248 23:44:53.845969 output: FDT: fdt-1
249 23:44:53.846052 output: Loadables: kernel-1
250 23:44:53.846135 output:
251 23:44:53.846381 end: 1.5.8.1 prepare-fit (duration 00:00:16) [common]
252 23:44:53.846509 end: 1.5.8 prepare-kernel (duration 00:00:16) [common]
253 23:44:53.846648 end: 1.5 prepare-tftp-overlay (duration 00:00:22) [common]
254 23:44:53.846778 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:37) [common]
255 23:44:53.846884 No LXC device requested
256 23:44:53.846997 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 23:44:53.847115 start: 1.7 deploy-device-env (timeout 00:09:37) [common]
258 23:44:53.847225 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 23:44:53.847330 Checking files for TFTP limit of 4294967296 bytes.
260 23:44:53.847992 end: 1 tftp-deploy (duration 00:00:23) [common]
261 23:44:53.848125 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 23:44:53.848253 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 23:44:53.848423 substitutions:
264 23:44:53.848517 - {DTB}: 14172972/tftp-deploy-6oanwx39/dtb/mt8192-asurada-spherion-r0.dtb
265 23:44:53.848608 - {INITRD}: 14172972/tftp-deploy-6oanwx39/ramdisk/ramdisk.cpio.gz
266 23:44:53.848671 - {KERNEL}: 14172972/tftp-deploy-6oanwx39/kernel/Image
267 23:44:53.848731 - {LAVA_MAC}: None
268 23:44:53.848790 - {PRESEED_CONFIG}: None
269 23:44:53.848848 - {PRESEED_LOCAL}: None
270 23:44:53.848904 - {RAMDISK}: 14172972/tftp-deploy-6oanwx39/ramdisk/ramdisk.cpio.gz
271 23:44:53.848961 - {ROOT_PART}: None
272 23:44:53.849017 - {ROOT}: None
273 23:44:53.849073 - {SERVER_IP}: 192.168.201.1
274 23:44:53.849128 - {TEE}: None
275 23:44:53.849184 Parsed boot commands:
276 23:44:53.849239 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 23:44:53.849421 Parsed boot commands: tftpboot 192.168.201.1 14172972/tftp-deploy-6oanwx39/kernel/image.itb 14172972/tftp-deploy-6oanwx39/kernel/cmdline
278 23:44:53.849513 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 23:44:53.849602 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 23:44:53.849698 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 23:44:53.849788 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 23:44:53.849866 Not connected, no need to disconnect.
283 23:44:53.849943 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 23:44:53.850025 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 23:44:53.850093 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
286 23:44:53.854127 Setting prompt string to ['lava-test: # ']
287 23:44:53.854649 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 23:44:53.854824 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 23:44:53.854993 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 23:44:53.855156 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 23:44:53.855519 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-8', '--port=1', '--command=reboot']
292 23:44:58.995906 >> Command sent successfully.
293 23:44:58.998599 Returned 0 in 5 seconds
294 23:44:59.098988 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 23:44:59.099315 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 23:44:59.099411 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 23:44:59.099501 Setting prompt string to 'Starting depthcharge on Spherion...'
299 23:44:59.099569 Changing prompt to 'Starting depthcharge on Spherion...'
300 23:44:59.099638 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 23:44:59.100024 [Enter `^Ec?' for help]
302 23:44:59.271255
303 23:44:59.271402
304 23:44:59.271474 F0: 102B 0000
305 23:44:59.271539
306 23:44:59.271604 F3: 1001 0000 [0200]
307 23:44:59.274644
308 23:44:59.274735 F3: 1001 0000
309 23:44:59.274805
310 23:44:59.274869 F7: 102D 0000
311 23:44:59.274930
312 23:44:59.278082 F1: 0000 0000
313 23:44:59.278168
314 23:44:59.278235 V0: 0000 0000 [0001]
315 23:44:59.278298
316 23:44:59.280766 00: 0007 8000
317 23:44:59.280856
318 23:44:59.280923 01: 0000 0000
319 23:44:59.280987
320 23:44:59.284597 BP: 0C00 0209 [0000]
321 23:44:59.284683
322 23:44:59.284750 G0: 1182 0000
323 23:44:59.284814
324 23:44:59.287805 EC: 0000 0021 [4000]
325 23:44:59.287890
326 23:44:59.287958 S7: 0000 0000 [0000]
327 23:44:59.288021
328 23:44:59.291674 CC: 0000 0000 [0001]
329 23:44:59.291812
330 23:44:59.291928 T0: 0000 0040 [010F]
331 23:44:59.292042
332 23:44:59.292150 Jump to BL
333 23:44:59.292258
334 23:44:59.318151
335 23:44:59.318304
336 23:44:59.326125 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
337 23:44:59.329604 ARM64: Exception handlers installed.
338 23:44:59.333155 ARM64: Testing exception
339 23:44:59.336201 ARM64: Done test exception
340 23:44:59.343169 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
341 23:44:59.353658 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
342 23:44:59.359966 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
343 23:44:59.369969 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
344 23:44:59.376572 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
345 23:44:59.383220 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
346 23:44:59.395179 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
347 23:44:59.401790 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
348 23:44:59.421152 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
349 23:44:59.424343 WDT: Last reset was cold boot
350 23:44:59.427598 SPI1(PAD0) initialized at 2873684 Hz
351 23:44:59.430707 SPI5(PAD0) initialized at 992727 Hz
352 23:44:59.434174 VBOOT: Loading verstage.
353 23:44:59.440913 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
354 23:44:59.444430 FMAP: Found "FLASH" version 1.1 at 0x20000.
355 23:44:59.447512 FMAP: base = 0x0 size = 0x800000 #areas = 25
356 23:44:59.450707 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
357 23:44:59.458603 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
358 23:44:59.465419 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
359 23:44:59.476255 read SPI 0x96554 0xa1eb: 4595 us, 9020 KB/s, 72.160 Mbps
360 23:44:59.476342
361 23:44:59.476410
362 23:44:59.486089 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
363 23:44:59.489572 ARM64: Exception handlers installed.
364 23:44:59.492879 ARM64: Testing exception
365 23:44:59.492982 ARM64: Done test exception
366 23:44:59.499441 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
367 23:44:59.502652 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
368 23:44:59.517179 Probing TPM: . done!
369 23:44:59.517272 TPM ready after 0 ms
370 23:44:59.523809 Connected to device vid:did:rid of 1ae0:0028:00
371 23:44:59.530905 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
372 23:44:59.572327 Initialized TPM device CR50 revision 0
373 23:44:59.582818 tlcl_send_startup: Startup return code is 0
374 23:44:59.582987 TPM: setup succeeded
375 23:44:59.594149 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
376 23:44:59.602702 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
377 23:44:59.614571 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
378 23:44:59.623704 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
379 23:44:59.626913 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
380 23:44:59.630811 in-header: 03 07 00 00 08 00 00 00
381 23:44:59.634719 in-data: aa e4 47 04 13 02 00 00
382 23:44:59.637983 Chrome EC: UHEPI supported
383 23:44:59.645386 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
384 23:44:59.648784 in-header: 03 9d 00 00 08 00 00 00
385 23:44:59.652383 in-data: 10 20 20 08 00 00 00 00
386 23:44:59.652517 Phase 1
387 23:44:59.656175 FMAP: area GBB found @ 3f5000 (12032 bytes)
388 23:44:59.663667 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
389 23:44:59.671074 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
390 23:44:59.671202 Recovery requested (1009000e)
391 23:44:59.679890 TPM: Extending digest for VBOOT: boot mode into PCR 0
392 23:44:59.685119 tlcl_extend: response is 0
393 23:44:59.693433 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
394 23:44:59.698762 tlcl_extend: response is 0
395 23:44:59.705448 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
396 23:44:59.726287 read SPI 0x210d4 0x2173b: 15144 us, 9047 KB/s, 72.376 Mbps
397 23:44:59.733617 BS: bootblock times (exec / console): total (unknown) / 148 ms
398 23:44:59.733764
399 23:44:59.733868
400 23:44:59.741371 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
401 23:44:59.745229 ARM64: Exception handlers installed.
402 23:44:59.748749 ARM64: Testing exception
403 23:44:59.752182 ARM64: Done test exception
404 23:44:59.772136 pmic_efuse_setting: Set efuses in 11 msecs
405 23:44:59.775570 pmwrap_interface_init: Select PMIF_VLD_RDY
406 23:44:59.779112 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
407 23:44:59.786315 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
408 23:44:59.790191 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
409 23:44:59.794021 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
410 23:44:59.801300 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
411 23:44:59.805154 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
412 23:44:59.808892 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
413 23:44:59.815924 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
414 23:44:59.819487 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
415 23:44:59.822538 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
416 23:44:59.829226 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
417 23:44:59.832595 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
418 23:44:59.835781 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
419 23:44:59.843151 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
420 23:44:59.849600 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
421 23:44:59.856322 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
422 23:44:59.859637 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
423 23:44:59.866391 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
424 23:44:59.873549 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
425 23:44:59.876973 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
426 23:44:59.884114 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
427 23:44:59.887967 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
428 23:44:59.894711 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
429 23:44:59.898113 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
430 23:44:59.905128 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
431 23:44:59.912125 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
432 23:44:59.915626 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
433 23:44:59.919391 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
434 23:44:59.926230 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
435 23:44:59.929874 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
436 23:44:59.936482 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
437 23:44:59.940369 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
438 23:44:59.943803 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
439 23:44:59.951645 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
440 23:44:59.955523 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
441 23:44:59.959656 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
442 23:44:59.966330 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
443 23:44:59.969018 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
444 23:44:59.976070 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
445 23:44:59.979026 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
446 23:44:59.982550 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
447 23:44:59.989168 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
448 23:44:59.992529 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
449 23:44:59.996037 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
450 23:45:00.002079 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
451 23:45:00.005678 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
452 23:45:00.009118 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
453 23:45:00.012428 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
454 23:45:00.018930 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
455 23:45:00.022388 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
456 23:45:00.025674 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
457 23:45:00.035436 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
458 23:45:00.042176 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
459 23:45:00.049242 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
460 23:45:00.055663 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
461 23:45:00.065860 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
462 23:45:00.069082 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
463 23:45:00.072566 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
464 23:45:00.078577 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 23:45:00.085439 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x7
466 23:45:00.088669 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
467 23:45:00.095849 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
468 23:45:00.099282 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
469 23:45:00.108716 [RTC]rtc_get_frequency_meter,154: input=15, output=793
470 23:45:00.112085 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
471 23:45:00.118753 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
472 23:45:00.122101 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
473 23:45:00.125504 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
474 23:45:00.128272 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
475 23:45:00.131877 ADC[4]: Raw value=896670 ID=7
476 23:45:00.135366 ADC[3]: Raw value=213440 ID=1
477 23:45:00.138864 RAM Code: 0x71
478 23:45:00.142184 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
479 23:45:00.145038 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
480 23:45:00.155424 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
481 23:45:00.162422 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
482 23:45:00.165674 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
483 23:45:00.168720 in-header: 03 07 00 00 08 00 00 00
484 23:45:00.172309 in-data: aa e4 47 04 13 02 00 00
485 23:45:00.175749 Chrome EC: UHEPI supported
486 23:45:00.183163 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
487 23:45:00.186526 in-header: 03 d5 00 00 08 00 00 00
488 23:45:00.186662 in-data: 98 20 60 08 00 00 00 00
489 23:45:00.190244 MRC: failed to locate region type 0.
490 23:45:00.197891 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
491 23:45:00.201178 DRAM-K: Running full calibration
492 23:45:00.208563 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
493 23:45:00.208696 header.status = 0x0
494 23:45:00.212379 header.version = 0x6 (expected: 0x6)
495 23:45:00.215873 header.size = 0xd00 (expected: 0xd00)
496 23:45:00.216004 header.flags = 0x0
497 23:45:00.222898 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
498 23:45:00.241830 read SPI 0x72590 0x1c583: 12503 us, 9285 KB/s, 74.280 Mbps
499 23:45:00.249376 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
500 23:45:00.249524 dram_init: ddr_geometry: 2
501 23:45:00.253212 [EMI] MDL number = 2
502 23:45:00.256404 [EMI] Get MDL freq = 0
503 23:45:00.256539 dram_init: ddr_type: 0
504 23:45:00.260385 is_discrete_lpddr4: 1
505 23:45:00.260499 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
506 23:45:00.264435
507 23:45:00.264523
508 23:45:00.264603 [Bian_co] ETT version 0.0.0.1
509 23:45:00.271144 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
510 23:45:00.271236
511 23:45:00.275374 dramc_set_vcore_voltage set vcore to 650000
512 23:45:00.275467 Read voltage for 800, 4
513 23:45:00.278551 Vio18 = 0
514 23:45:00.278695 Vcore = 650000
515 23:45:00.278821 Vdram = 0
516 23:45:00.278943 Vddq = 0
517 23:45:00.282456 Vmddr = 0
518 23:45:00.282615 dram_init: config_dvfs: 1
519 23:45:00.289618 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
520 23:45:00.293363 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
521 23:45:00.297039 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
522 23:45:00.301137 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
523 23:45:00.304243 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
524 23:45:00.307313 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
525 23:45:00.310820 MEM_TYPE=3, freq_sel=18
526 23:45:00.314135 sv_algorithm_assistance_LP4_1600
527 23:45:00.317508 ============ PULL DRAM RESETB DOWN ============
528 23:45:00.320938 ========== PULL DRAM RESETB DOWN end =========
529 23:45:00.327277 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
530 23:45:00.331251 ===================================
531 23:45:00.334078 LPDDR4 DRAM CONFIGURATION
532 23:45:00.334230 ===================================
533 23:45:00.337457 EX_ROW_EN[0] = 0x0
534 23:45:00.341045 EX_ROW_EN[1] = 0x0
535 23:45:00.341226 LP4Y_EN = 0x0
536 23:45:00.344383 WORK_FSP = 0x0
537 23:45:00.344532 WL = 0x2
538 23:45:00.347627 RL = 0x2
539 23:45:00.347772 BL = 0x2
540 23:45:00.350736 RPST = 0x0
541 23:45:00.350890 RD_PRE = 0x0
542 23:45:00.354319 WR_PRE = 0x1
543 23:45:00.354464 WR_PST = 0x0
544 23:45:00.357373 DBI_WR = 0x0
545 23:45:00.357522 DBI_RD = 0x0
546 23:45:00.361032 OTF = 0x1
547 23:45:00.364152 ===================================
548 23:45:00.367523 ===================================
549 23:45:00.367696 ANA top config
550 23:45:00.370899 ===================================
551 23:45:00.374189 DLL_ASYNC_EN = 0
552 23:45:00.377724 ALL_SLAVE_EN = 1
553 23:45:00.380807 NEW_RANK_MODE = 1
554 23:45:00.380968 DLL_IDLE_MODE = 1
555 23:45:00.384213 LP45_APHY_COMB_EN = 1
556 23:45:00.387467 TX_ODT_DIS = 1
557 23:45:00.390672 NEW_8X_MODE = 1
558 23:45:00.394559 ===================================
559 23:45:00.397740 ===================================
560 23:45:00.401024 data_rate = 1600
561 23:45:00.401175 CKR = 1
562 23:45:00.404285 DQ_P2S_RATIO = 8
563 23:45:00.407767 ===================================
564 23:45:00.410958 CA_P2S_RATIO = 8
565 23:45:00.414165 DQ_CA_OPEN = 0
566 23:45:00.417537 DQ_SEMI_OPEN = 0
567 23:45:00.417682 CA_SEMI_OPEN = 0
568 23:45:00.421039 CA_FULL_RATE = 0
569 23:45:00.424518 DQ_CKDIV4_EN = 1
570 23:45:00.427885 CA_CKDIV4_EN = 1
571 23:45:00.430851 CA_PREDIV_EN = 0
572 23:45:00.434240 PH8_DLY = 0
573 23:45:00.434382 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
574 23:45:00.437544 DQ_AAMCK_DIV = 4
575 23:45:00.441138 CA_AAMCK_DIV = 4
576 23:45:00.444536 CA_ADMCK_DIV = 4
577 23:45:00.447882 DQ_TRACK_CA_EN = 0
578 23:45:00.451334 CA_PICK = 800
579 23:45:00.451483 CA_MCKIO = 800
580 23:45:00.454204 MCKIO_SEMI = 0
581 23:45:00.457697 PLL_FREQ = 3068
582 23:45:00.461192 DQ_UI_PI_RATIO = 32
583 23:45:00.464223 CA_UI_PI_RATIO = 0
584 23:45:00.468025 ===================================
585 23:45:00.471068 ===================================
586 23:45:00.474238 memory_type:LPDDR4
587 23:45:00.474384 GP_NUM : 10
588 23:45:00.477441 SRAM_EN : 1
589 23:45:00.477578 MD32_EN : 0
590 23:45:00.480891 ===================================
591 23:45:00.484403 [ANA_INIT] >>>>>>>>>>>>>>
592 23:45:00.487836 <<<<<< [CONFIGURE PHASE]: ANA_TX
593 23:45:00.490777 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
594 23:45:00.494187 ===================================
595 23:45:00.497401 data_rate = 1600,PCW = 0X7600
596 23:45:00.500628 ===================================
597 23:45:00.504010 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
598 23:45:00.510699 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
599 23:45:00.514183 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
600 23:45:00.520887 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
601 23:45:00.524358 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
602 23:45:00.528046 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
603 23:45:00.528198 [ANA_INIT] flow start
604 23:45:00.531332 [ANA_INIT] PLL >>>>>>>>
605 23:45:00.531476 [ANA_INIT] PLL <<<<<<<<
606 23:45:00.535237 [ANA_INIT] MIDPI >>>>>>>>
607 23:45:00.539173 [ANA_INIT] MIDPI <<<<<<<<
608 23:45:00.539318 [ANA_INIT] DLL >>>>>>>>
609 23:45:00.542600 [ANA_INIT] flow end
610 23:45:00.546108 ============ LP4 DIFF to SE enter ============
611 23:45:00.550079 ============ LP4 DIFF to SE exit ============
612 23:45:00.553496 [ANA_INIT] <<<<<<<<<<<<<
613 23:45:00.557118 [Flow] Enable top DCM control >>>>>
614 23:45:00.560566 [Flow] Enable top DCM control <<<<<
615 23:45:00.560745 Enable DLL master slave shuffle
616 23:45:00.568004 ==============================================================
617 23:45:00.568164 Gating Mode config
618 23:45:00.575446 ==============================================================
619 23:45:00.575590 Config description:
620 23:45:00.586405 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
621 23:45:00.593673 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
622 23:45:00.597431 SELPH_MODE 0: By rank 1: By Phase
623 23:45:00.604778 ==============================================================
624 23:45:00.604934 GAT_TRACK_EN = 1
625 23:45:00.608466 RX_GATING_MODE = 2
626 23:45:00.612136 RX_GATING_TRACK_MODE = 2
627 23:45:00.616128 SELPH_MODE = 1
628 23:45:00.619888 PICG_EARLY_EN = 1
629 23:45:00.623257 VALID_LAT_VALUE = 1
630 23:45:00.626771 ==============================================================
631 23:45:00.630896 Enter into Gating configuration >>>>
632 23:45:00.633889 Exit from Gating configuration <<<<
633 23:45:00.637680 Enter into DVFS_PRE_config >>>>>
634 23:45:00.649435 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
635 23:45:00.649625 Exit from DVFS_PRE_config <<<<<
636 23:45:00.652752 Enter into PICG configuration >>>>
637 23:45:00.656836 Exit from PICG configuration <<<<
638 23:45:00.660679 [RX_INPUT] configuration >>>>>
639 23:45:00.664494 [RX_INPUT] configuration <<<<<
640 23:45:00.667952 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
641 23:45:00.671903 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
642 23:45:00.679023 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
643 23:45:00.686654 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
644 23:45:00.690101 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
645 23:45:00.697047 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
646 23:45:00.700793 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
647 23:45:00.704458 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
648 23:45:00.708959 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
649 23:45:00.715769 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
650 23:45:00.719303 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
651 23:45:00.723302 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
652 23:45:00.726961 ===================================
653 23:45:00.727064 LPDDR4 DRAM CONFIGURATION
654 23:45:00.730842 ===================================
655 23:45:00.734590 EX_ROW_EN[0] = 0x0
656 23:45:00.734708 EX_ROW_EN[1] = 0x0
657 23:45:00.738154 LP4Y_EN = 0x0
658 23:45:00.738242 WORK_FSP = 0x0
659 23:45:00.741815 WL = 0x2
660 23:45:00.741904 RL = 0x2
661 23:45:00.745554 BL = 0x2
662 23:45:00.745650 RPST = 0x0
663 23:45:00.748991 RD_PRE = 0x0
664 23:45:00.749097 WR_PRE = 0x1
665 23:45:00.752921 WR_PST = 0x0
666 23:45:00.753009 DBI_WR = 0x0
667 23:45:00.756856 DBI_RD = 0x0
668 23:45:00.756973 OTF = 0x1
669 23:45:00.760839 ===================================
670 23:45:00.764197 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
671 23:45:00.767557 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
672 23:45:00.771476 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
673 23:45:00.774989 ===================================
674 23:45:00.778788 LPDDR4 DRAM CONFIGURATION
675 23:45:00.782115 ===================================
676 23:45:00.782200 EX_ROW_EN[0] = 0x10
677 23:45:00.785827 EX_ROW_EN[1] = 0x0
678 23:45:00.785921 LP4Y_EN = 0x0
679 23:45:00.789115 WORK_FSP = 0x0
680 23:45:00.789202 WL = 0x2
681 23:45:00.793018 RL = 0x2
682 23:45:00.793095 BL = 0x2
683 23:45:00.796532 RPST = 0x0
684 23:45:00.796618 RD_PRE = 0x0
685 23:45:00.800822 WR_PRE = 0x1
686 23:45:00.800919 WR_PST = 0x0
687 23:45:00.804077 DBI_WR = 0x0
688 23:45:00.804162 DBI_RD = 0x0
689 23:45:00.807789 OTF = 0x1
690 23:45:00.807882 ===================================
691 23:45:00.815007 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
692 23:45:00.820046 nWR fixed to 40
693 23:45:00.820138 [ModeRegInit_LP4] CH0 RK0
694 23:45:00.823291 [ModeRegInit_LP4] CH0 RK1
695 23:45:00.827203 [ModeRegInit_LP4] CH1 RK0
696 23:45:00.827297 [ModeRegInit_LP4] CH1 RK1
697 23:45:00.830872 match AC timing 13
698 23:45:00.834691 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
699 23:45:00.838402 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
700 23:45:00.842454 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
701 23:45:00.849878 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
702 23:45:00.853576 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
703 23:45:00.853719 [EMI DOE] emi_dcm 0
704 23:45:00.857885 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
705 23:45:00.857985 ==
706 23:45:00.861249 Dram Type= 6, Freq= 0, CH_0, rank 0
707 23:45:00.865098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
708 23:45:00.865200 ==
709 23:45:00.872308 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
710 23:45:00.879117 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
711 23:45:00.886877 [CA 0] Center 38 (7~69) winsize 63
712 23:45:00.890069 [CA 1] Center 38 (7~69) winsize 63
713 23:45:00.893424 [CA 2] Center 35 (5~66) winsize 62
714 23:45:00.896956 [CA 3] Center 35 (5~66) winsize 62
715 23:45:00.900161 [CA 4] Center 34 (4~65) winsize 62
716 23:45:00.903297 [CA 5] Center 34 (3~65) winsize 63
717 23:45:00.903426
718 23:45:00.906616 [CmdBusTrainingLP45] Vref(ca) range 1: 34
719 23:45:00.906732
720 23:45:00.909893 [CATrainingPosCal] consider 1 rank data
721 23:45:00.913821 u2DelayCellTimex100 = 270/100 ps
722 23:45:00.916550 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
723 23:45:00.919906 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
724 23:45:00.926512 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
725 23:45:00.929926 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
726 23:45:00.933036 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
727 23:45:00.936950 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
728 23:45:00.937046
729 23:45:00.939974 CA PerBit enable=1, Macro0, CA PI delay=34
730 23:45:00.940054
731 23:45:00.943164 [CBTSetCACLKResult] CA Dly = 34
732 23:45:00.943256 CS Dly: 6 (0~37)
733 23:45:00.946777 ==
734 23:45:00.946871 Dram Type= 6, Freq= 0, CH_0, rank 1
735 23:45:00.953487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
736 23:45:00.953588 ==
737 23:45:00.956368 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
738 23:45:00.962894 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
739 23:45:00.973259 [CA 0] Center 38 (7~69) winsize 63
740 23:45:00.976098 [CA 1] Center 38 (7~69) winsize 63
741 23:45:00.979474 [CA 2] Center 35 (5~66) winsize 62
742 23:45:00.982877 [CA 3] Center 35 (5~66) winsize 62
743 23:45:00.986328 [CA 4] Center 34 (4~65) winsize 62
744 23:45:00.989840 [CA 5] Center 34 (4~65) winsize 62
745 23:45:00.989930
746 23:45:00.993109 [CmdBusTrainingLP45] Vref(ca) range 1: 32
747 23:45:00.993228
748 23:45:00.996199 [CATrainingPosCal] consider 2 rank data
749 23:45:00.999697 u2DelayCellTimex100 = 270/100 ps
750 23:45:01.003440 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
751 23:45:01.006261 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
752 23:45:01.012923 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
753 23:45:01.016182 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
754 23:45:01.019423 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
755 23:45:01.023310 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
756 23:45:01.023403
757 23:45:01.026281 CA PerBit enable=1, Macro0, CA PI delay=34
758 23:45:01.026402
759 23:45:01.029720 [CBTSetCACLKResult] CA Dly = 34
760 23:45:01.029843 CS Dly: 6 (0~38)
761 23:45:01.029948
762 23:45:01.032942 ----->DramcWriteLeveling(PI) begin...
763 23:45:01.036093 ==
764 23:45:01.039389 Dram Type= 6, Freq= 0, CH_0, rank 0
765 23:45:01.043075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
766 23:45:01.043192 ==
767 23:45:01.046077 Write leveling (Byte 0): 31 => 31
768 23:45:01.049447 Write leveling (Byte 1): 30 => 30
769 23:45:01.053205 DramcWriteLeveling(PI) end<-----
770 23:45:01.053296
771 23:45:01.053365 ==
772 23:45:01.056577 Dram Type= 6, Freq= 0, CH_0, rank 0
773 23:45:01.059572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 23:45:01.059686 ==
775 23:45:01.062972 [Gating] SW mode calibration
776 23:45:01.069677 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
777 23:45:01.073498 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
778 23:45:01.079653 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
779 23:45:01.082803 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
780 23:45:01.086108 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
781 23:45:01.093073 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
782 23:45:01.096857 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
783 23:45:01.099700 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
784 23:45:01.106477 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
785 23:45:01.109905 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
786 23:45:01.113088 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 23:45:01.119664 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 23:45:01.123855 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 23:45:01.127439 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 23:45:01.131376 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 23:45:01.135380 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 23:45:01.141848 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 23:45:01.144952 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 23:45:01.148463 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 23:45:01.152437 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 23:45:01.158807 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
797 23:45:01.162244 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
798 23:45:01.165953 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 23:45:01.172529 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 23:45:01.175882 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 23:45:01.179116 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 23:45:01.185855 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 23:45:01.188990 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 23:45:01.192132 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 23:45:01.198726 0 9 12 | B1->B0 | 2c2c 3030 | 0 1 | (0 0) (1 1)
806 23:45:01.202459 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
807 23:45:01.205885 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
808 23:45:01.212446 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
809 23:45:01.215917 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
810 23:45:01.219259 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
811 23:45:01.222069 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 23:45:01.229184 0 10 8 | B1->B0 | 3434 3131 | 0 1 | (0 0) (1 0)
813 23:45:01.232661 0 10 12 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (0 0)
814 23:45:01.235376 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 23:45:01.242208 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 23:45:01.245628 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 23:45:01.248863 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 23:45:01.255585 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 23:45:01.258758 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 23:45:01.262065 0 11 8 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
821 23:45:01.268674 0 11 12 | B1->B0 | 3030 4040 | 0 0 | (0 0) (0 0)
822 23:45:01.272172 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
823 23:45:01.275326 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
824 23:45:01.282222 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
825 23:45:01.285614 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
826 23:45:01.288990 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
827 23:45:01.295330 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 23:45:01.298998 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
829 23:45:01.302011 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
830 23:45:01.308843 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
831 23:45:01.311816 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
832 23:45:01.315225 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
833 23:45:01.322117 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
834 23:45:01.325278 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 23:45:01.328537 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 23:45:01.335222 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 23:45:01.338432 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 23:45:01.341829 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 23:45:01.345149 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 23:45:01.351828 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 23:45:01.355131 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 23:45:01.359093 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 23:45:01.365604 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 23:45:01.368869 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
845 23:45:01.372370 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
846 23:45:01.378728 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
847 23:45:01.378877 Total UI for P1: 0, mck2ui 16
848 23:45:01.385220 best dqsien dly found for B0: ( 0, 14, 10)
849 23:45:01.385374 Total UI for P1: 0, mck2ui 16
850 23:45:01.391950 best dqsien dly found for B1: ( 0, 14, 14)
851 23:45:01.395332 best DQS0 dly(MCK, UI, PI) = (0, 14, 10)
852 23:45:01.398785 best DQS1 dly(MCK, UI, PI) = (0, 14, 14)
853 23:45:01.398883
854 23:45:01.402163 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 10)
855 23:45:01.405473 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 14)
856 23:45:01.408621 [Gating] SW calibration Done
857 23:45:01.408707 ==
858 23:45:01.411942 Dram Type= 6, Freq= 0, CH_0, rank 0
859 23:45:01.415104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
860 23:45:01.415192 ==
861 23:45:01.418555 RX Vref Scan: 0
862 23:45:01.418647
863 23:45:01.418715 RX Vref 0 -> 0, step: 1
864 23:45:01.418818
865 23:45:01.422198 RX Delay -130 -> 252, step: 16
866 23:45:01.425574 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
867 23:45:01.432149 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
868 23:45:01.435480 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
869 23:45:01.438752 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
870 23:45:01.442221 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
871 23:45:01.445483 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
872 23:45:01.452324 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
873 23:45:01.455118 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
874 23:45:01.458544 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
875 23:45:01.462279 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
876 23:45:01.465159 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
877 23:45:01.471916 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
878 23:45:01.475268 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
879 23:45:01.478671 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
880 23:45:01.481803 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
881 23:45:01.485281 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
882 23:45:01.488933 ==
883 23:45:01.492094 Dram Type= 6, Freq= 0, CH_0, rank 0
884 23:45:01.495403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
885 23:45:01.495536 ==
886 23:45:01.495654 DQS Delay:
887 23:45:01.498717 DQS0 = 0, DQS1 = 0
888 23:45:01.498845 DQM Delay:
889 23:45:01.502271 DQM0 = 81, DQM1 = 70
890 23:45:01.502409 DQ Delay:
891 23:45:01.505647 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =77
892 23:45:01.508544 DQ4 =85, DQ5 =61, DQ6 =85, DQ7 =93
893 23:45:01.511880 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
894 23:45:01.515011 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
895 23:45:01.515141
896 23:45:01.515259
897 23:45:01.515369 ==
898 23:45:01.518748 Dram Type= 6, Freq= 0, CH_0, rank 0
899 23:45:01.522439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
900 23:45:01.522574 ==
901 23:45:01.522684
902 23:45:01.522791
903 23:45:01.525930 TX Vref Scan disable
904 23:45:01.526057 == TX Byte 0 ==
905 23:45:01.532265 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
906 23:45:01.535716 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
907 23:45:01.535826 == TX Byte 1 ==
908 23:45:01.542289 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
909 23:45:01.546048 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
910 23:45:01.546184 ==
911 23:45:01.549394 Dram Type= 6, Freq= 0, CH_0, rank 0
912 23:45:01.552213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
913 23:45:01.552307 ==
914 23:45:01.566646 TX Vref=22, minBit 1, minWin=26, winSum=430
915 23:45:01.569935 TX Vref=24, minBit 14, minWin=26, winSum=436
916 23:45:01.573198 TX Vref=26, minBit 14, minWin=26, winSum=439
917 23:45:01.576142 TX Vref=28, minBit 9, minWin=27, winSum=443
918 23:45:01.579635 TX Vref=30, minBit 2, minWin=27, winSum=442
919 23:45:01.586110 TX Vref=32, minBit 2, minWin=27, winSum=440
920 23:45:01.589788 [TxChooseVref] Worse bit 9, Min win 27, Win sum 443, Final Vref 28
921 23:45:01.589887
922 23:45:01.592706 Final TX Range 1 Vref 28
923 23:45:01.592800
924 23:45:01.592869 ==
925 23:45:01.596417 Dram Type= 6, Freq= 0, CH_0, rank 0
926 23:45:01.599597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
927 23:45:01.599689 ==
928 23:45:01.602981
929 23:45:01.603067
930 23:45:01.603134 TX Vref Scan disable
931 23:45:01.606309 == TX Byte 0 ==
932 23:45:01.609715 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
933 23:45:01.616747 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
934 23:45:01.616840 == TX Byte 1 ==
935 23:45:01.620181 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
936 23:45:01.623454 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
937 23:45:01.626748
938 23:45:01.626834 [DATLAT]
939 23:45:01.626901 Freq=800, CH0 RK0
940 23:45:01.626965
941 23:45:01.630091 DATLAT Default: 0xa
942 23:45:01.630176 0, 0xFFFF, sum = 0
943 23:45:01.633157 1, 0xFFFF, sum = 0
944 23:45:01.633292 2, 0xFFFF, sum = 0
945 23:45:01.636332 3, 0xFFFF, sum = 0
946 23:45:01.636460 4, 0xFFFF, sum = 0
947 23:45:01.639557 5, 0xFFFF, sum = 0
948 23:45:01.643259 6, 0xFFFF, sum = 0
949 23:45:01.643390 7, 0xFFFF, sum = 0
950 23:45:01.646271 8, 0xFFFF, sum = 0
951 23:45:01.646411 9, 0x0, sum = 1
952 23:45:01.646531 10, 0x0, sum = 2
953 23:45:01.650015 11, 0x0, sum = 3
954 23:45:01.650166 12, 0x0, sum = 4
955 23:45:01.653222 best_step = 10
956 23:45:01.653358
957 23:45:01.653476 ==
958 23:45:01.656235 Dram Type= 6, Freq= 0, CH_0, rank 0
959 23:45:01.659912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
960 23:45:01.660067 ==
961 23:45:01.663231 RX Vref Scan: 1
962 23:45:01.663357
963 23:45:01.663473 Set Vref Range= 32 -> 127
964 23:45:01.663587
965 23:45:01.666582 RX Vref 32 -> 127, step: 1
966 23:45:01.666717
967 23:45:01.669788 RX Delay -111 -> 252, step: 8
968 23:45:01.669921
969 23:45:01.673107 Set Vref, RX VrefLevel [Byte0]: 32
970 23:45:01.676551 [Byte1]: 32
971 23:45:01.676650
972 23:45:01.679991 Set Vref, RX VrefLevel [Byte0]: 33
973 23:45:01.683096 [Byte1]: 33
974 23:45:01.687010
975 23:45:01.687121 Set Vref, RX VrefLevel [Byte0]: 34
976 23:45:01.690115 [Byte1]: 34
977 23:45:01.694473
978 23:45:01.694565 Set Vref, RX VrefLevel [Byte0]: 35
979 23:45:01.697613 [Byte1]: 35
980 23:45:01.702087
981 23:45:01.702236 Set Vref, RX VrefLevel [Byte0]: 36
982 23:45:01.705428 [Byte1]: 36
983 23:45:01.709770
984 23:45:01.709930 Set Vref, RX VrefLevel [Byte0]: 37
985 23:45:01.713092 [Byte1]: 37
986 23:45:01.717561
987 23:45:01.717692 Set Vref, RX VrefLevel [Byte0]: 38
988 23:45:01.720916 [Byte1]: 38
989 23:45:01.724938
990 23:45:01.725039 Set Vref, RX VrefLevel [Byte0]: 39
991 23:45:01.728938 [Byte1]: 39
992 23:45:01.732677
993 23:45:01.732780 Set Vref, RX VrefLevel [Byte0]: 40
994 23:45:01.736332 [Byte1]: 40
995 23:45:01.740521
996 23:45:01.740682 Set Vref, RX VrefLevel [Byte0]: 41
997 23:45:01.743573 [Byte1]: 41
998 23:45:01.748044
999 23:45:01.748183 Set Vref, RX VrefLevel [Byte0]: 42
1000 23:45:01.751453 [Byte1]: 42
1001 23:45:01.756071
1002 23:45:01.756215 Set Vref, RX VrefLevel [Byte0]: 43
1003 23:45:01.758956 [Byte1]: 43
1004 23:45:01.763291
1005 23:45:01.763404 Set Vref, RX VrefLevel [Byte0]: 44
1006 23:45:01.766440 [Byte1]: 44
1007 23:45:01.771259
1008 23:45:01.771420 Set Vref, RX VrefLevel [Byte0]: 45
1009 23:45:01.774528 [Byte1]: 45
1010 23:45:01.778927
1011 23:45:01.779028 Set Vref, RX VrefLevel [Byte0]: 46
1012 23:45:01.782102 [Byte1]: 46
1013 23:45:01.786681
1014 23:45:01.786776 Set Vref, RX VrefLevel [Byte0]: 47
1015 23:45:01.789964 [Byte1]: 47
1016 23:45:01.794117
1017 23:45:01.794278 Set Vref, RX VrefLevel [Byte0]: 48
1018 23:45:01.797812 [Byte1]: 48
1019 23:45:01.801855
1020 23:45:01.802002 Set Vref, RX VrefLevel [Byte0]: 49
1021 23:45:01.805108 [Byte1]: 49
1022 23:45:01.809523
1023 23:45:01.809674 Set Vref, RX VrefLevel [Byte0]: 50
1024 23:45:01.812965 [Byte1]: 50
1025 23:45:01.817360
1026 23:45:01.817504 Set Vref, RX VrefLevel [Byte0]: 51
1027 23:45:01.820656 [Byte1]: 51
1028 23:45:01.824701
1029 23:45:01.824849 Set Vref, RX VrefLevel [Byte0]: 52
1030 23:45:01.828039 [Byte1]: 52
1031 23:45:01.832525
1032 23:45:01.832687 Set Vref, RX VrefLevel [Byte0]: 53
1033 23:45:01.835864 [Byte1]: 53
1034 23:45:01.840126
1035 23:45:01.840248 Set Vref, RX VrefLevel [Byte0]: 54
1036 23:45:01.843131 [Byte1]: 54
1037 23:45:01.847480
1038 23:45:01.847610 Set Vref, RX VrefLevel [Byte0]: 55
1039 23:45:01.851204 [Byte1]: 55
1040 23:45:01.854917
1041 23:45:01.855045 Set Vref, RX VrefLevel [Byte0]: 56
1042 23:45:01.858306 [Byte1]: 56
1043 23:45:01.862825
1044 23:45:01.862911 Set Vref, RX VrefLevel [Byte0]: 57
1045 23:45:01.866130 [Byte1]: 57
1046 23:45:01.870497
1047 23:45:01.870609 Set Vref, RX VrefLevel [Byte0]: 58
1048 23:45:01.873532 [Byte1]: 58
1049 23:45:01.878235
1050 23:45:01.878320 Set Vref, RX VrefLevel [Byte0]: 59
1051 23:45:01.881518 [Byte1]: 59
1052 23:45:01.885662
1053 23:45:01.885745 Set Vref, RX VrefLevel [Byte0]: 60
1054 23:45:01.888986 [Byte1]: 60
1055 23:45:01.893384
1056 23:45:01.893467 Set Vref, RX VrefLevel [Byte0]: 61
1057 23:45:01.896547 [Byte1]: 61
1058 23:45:01.900864
1059 23:45:01.900959 Set Vref, RX VrefLevel [Byte0]: 62
1060 23:45:01.904413 [Byte1]: 62
1061 23:45:01.908898
1062 23:45:01.908990 Set Vref, RX VrefLevel [Byte0]: 63
1063 23:45:01.911968 [Byte1]: 63
1064 23:45:01.916534
1065 23:45:01.916638 Set Vref, RX VrefLevel [Byte0]: 64
1066 23:45:01.919677 [Byte1]: 64
1067 23:45:01.924242
1068 23:45:01.924328 Set Vref, RX VrefLevel [Byte0]: 65
1069 23:45:01.927153 [Byte1]: 65
1070 23:45:01.931487
1071 23:45:01.931581 Set Vref, RX VrefLevel [Byte0]: 66
1072 23:45:01.934835 [Byte1]: 66
1073 23:45:01.939139
1074 23:45:01.939222 Set Vref, RX VrefLevel [Byte0]: 67
1075 23:45:01.942430 [Byte1]: 67
1076 23:45:01.947041
1077 23:45:01.947120 Set Vref, RX VrefLevel [Byte0]: 68
1078 23:45:01.950373 [Byte1]: 68
1079 23:45:01.954744
1080 23:45:01.954886 Set Vref, RX VrefLevel [Byte0]: 69
1081 23:45:01.957985 [Byte1]: 69
1082 23:45:01.961936
1083 23:45:01.962081 Set Vref, RX VrefLevel [Byte0]: 70
1084 23:45:01.965621 [Byte1]: 70
1085 23:45:01.970052
1086 23:45:01.970197 Set Vref, RX VrefLevel [Byte0]: 71
1087 23:45:01.973369 [Byte1]: 71
1088 23:45:01.977131
1089 23:45:01.977267 Set Vref, RX VrefLevel [Byte0]: 72
1090 23:45:01.980603 [Byte1]: 72
1091 23:45:01.985010
1092 23:45:01.985167 Set Vref, RX VrefLevel [Byte0]: 73
1093 23:45:01.988328 [Byte1]: 73
1094 23:45:01.992537
1095 23:45:01.992680 Set Vref, RX VrefLevel [Byte0]: 74
1096 23:45:01.996466 [Byte1]: 74
1097 23:45:02.000242
1098 23:45:02.000380 Set Vref, RX VrefLevel [Byte0]: 75
1099 23:45:02.003593 [Byte1]: 75
1100 23:45:02.007856
1101 23:45:02.007983 Set Vref, RX VrefLevel [Byte0]: 76
1102 23:45:02.011424 [Byte1]: 76
1103 23:45:02.015490
1104 23:45:02.015588 Set Vref, RX VrefLevel [Byte0]: 77
1105 23:45:02.018839 [Byte1]: 77
1106 23:45:02.023182
1107 23:45:02.023294 Set Vref, RX VrefLevel [Byte0]: 78
1108 23:45:02.026611 [Byte1]: 78
1109 23:45:02.030865
1110 23:45:02.030992 Final RX Vref Byte 0 = 61 to rank0
1111 23:45:02.034165 Final RX Vref Byte 1 = 58 to rank0
1112 23:45:02.037448 Final RX Vref Byte 0 = 61 to rank1
1113 23:45:02.040695 Final RX Vref Byte 1 = 58 to rank1==
1114 23:45:02.044139 Dram Type= 6, Freq= 0, CH_0, rank 0
1115 23:45:02.051267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1116 23:45:02.051403 ==
1117 23:45:02.051473 DQS Delay:
1118 23:45:02.051538 DQS0 = 0, DQS1 = 0
1119 23:45:02.054083 DQM Delay:
1120 23:45:02.054163 DQM0 = 81, DQM1 = 68
1121 23:45:02.057324 DQ Delay:
1122 23:45:02.060612 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1123 23:45:02.064478 DQ4 =80, DQ5 =68, DQ6 =88, DQ7 =92
1124 23:45:02.067492 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1125 23:45:02.070509 DQ12 =76, DQ13 =72, DQ14 =76, DQ15 =76
1126 23:45:02.070626
1127 23:45:02.070695
1128 23:45:02.077676 [DQSOSCAuto] RK0, (LSB)MR18= 0x2322, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 401 ps
1129 23:45:02.080581 CH0 RK0: MR19=606, MR18=2322
1130 23:45:02.087332 CH0_RK0: MR19=0x606, MR18=0x2322, DQSOSC=401, MR23=63, INC=91, DEC=61
1131 23:45:02.087455
1132 23:45:02.090623 ----->DramcWriteLeveling(PI) begin...
1133 23:45:02.090702 ==
1134 23:45:02.094075 Dram Type= 6, Freq= 0, CH_0, rank 1
1135 23:45:02.097373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1136 23:45:02.097478 ==
1137 23:45:02.100647 Write leveling (Byte 0): 31 => 31
1138 23:45:02.103895 Write leveling (Byte 1): 30 => 30
1139 23:45:02.107613 DramcWriteLeveling(PI) end<-----
1140 23:45:02.107732
1141 23:45:02.107825 ==
1142 23:45:02.110808 Dram Type= 6, Freq= 0, CH_0, rank 1
1143 23:45:02.113878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1144 23:45:02.114004 ==
1145 23:45:02.117735 [Gating] SW mode calibration
1146 23:45:02.124328 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1147 23:45:02.130736 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1148 23:45:02.134176 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1149 23:45:02.137219 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1150 23:45:02.143883 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1151 23:45:02.147198 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1152 23:45:02.150623 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 23:45:02.157341 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 23:45:02.160687 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 23:45:02.164116 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 23:45:02.171032 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 23:45:02.174233 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 23:45:02.177895 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 23:45:02.184458 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 23:45:02.187840 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 23:45:02.191045 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 23:45:02.238013 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 23:45:02.238160 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 23:45:02.238484 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 23:45:02.238753 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1166 23:45:02.238823 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1167 23:45:02.238908 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 23:45:02.239389 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 23:45:02.239676 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 23:45:02.239977 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 23:45:02.240095 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 23:45:02.240191 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 23:45:02.272992 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 23:45:02.273524 0 9 8 | B1->B0 | 2525 3030 | 0 1 | (0 0) (1 1)
1175 23:45:02.273869 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1176 23:45:02.273991 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1177 23:45:02.274116 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1178 23:45:02.274248 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 23:45:02.274682 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 23:45:02.277331 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 23:45:02.280724 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
1182 23:45:02.284097 0 10 8 | B1->B0 | 3333 2929 | 0 0 | (0 0) (0 0)
1183 23:45:02.287545 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1184 23:45:02.294141 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 23:45:02.297395 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 23:45:02.300716 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 23:45:02.304085 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 23:45:02.310672 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 23:45:02.313933 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 23:45:02.317408 0 11 8 | B1->B0 | 3333 4242 | 0 0 | (0 0) (0 0)
1191 23:45:02.323863 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1192 23:45:02.327503 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1193 23:45:02.330457 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 23:45:02.337607 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 23:45:02.341165 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 23:45:02.344247 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 23:45:02.351026 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 23:45:02.354167 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1199 23:45:02.357577 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1200 23:45:02.361219 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 23:45:02.368276 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 23:45:02.372049 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 23:45:02.375465 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 23:45:02.378986 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 23:45:02.385412 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 23:45:02.388800 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 23:45:02.392948 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 23:45:02.396294 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 23:45:02.403033 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 23:45:02.406333 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 23:45:02.409782 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 23:45:02.416349 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 23:45:02.419793 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1214 23:45:02.423108 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1215 23:45:02.429808 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1216 23:45:02.433059 Total UI for P1: 0, mck2ui 16
1217 23:45:02.436428 best dqsien dly found for B0: ( 0, 14, 6)
1218 23:45:02.436528 Total UI for P1: 0, mck2ui 16
1219 23:45:02.443198 best dqsien dly found for B1: ( 0, 14, 8)
1220 23:45:02.446317 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1221 23:45:02.449723 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1222 23:45:02.449827
1223 23:45:02.453046 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1224 23:45:02.456060 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1225 23:45:02.459608 [Gating] SW calibration Done
1226 23:45:02.459677 ==
1227 23:45:02.462942 Dram Type= 6, Freq= 0, CH_0, rank 1
1228 23:45:02.466753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1229 23:45:02.466831 ==
1230 23:45:02.469825 RX Vref Scan: 0
1231 23:45:02.469942
1232 23:45:02.470072 RX Vref 0 -> 0, step: 1
1233 23:45:02.470197
1234 23:45:02.472822 RX Delay -130 -> 252, step: 16
1235 23:45:02.476636 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1236 23:45:02.483270 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1237 23:45:02.486575 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1238 23:45:02.489962 iDelay=206, Bit 3, Center 77 (-50 ~ 205) 256
1239 23:45:02.493063 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1240 23:45:02.496351 iDelay=206, Bit 5, Center 61 (-66 ~ 189) 256
1241 23:45:02.499896 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1242 23:45:02.506597 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1243 23:45:02.510028 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1244 23:45:02.512899 iDelay=206, Bit 9, Center 53 (-66 ~ 173) 240
1245 23:45:02.516751 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1246 23:45:02.519959 iDelay=206, Bit 11, Center 61 (-66 ~ 189) 256
1247 23:45:02.526715 iDelay=206, Bit 12, Center 77 (-50 ~ 205) 256
1248 23:45:02.530077 iDelay=206, Bit 13, Center 77 (-50 ~ 205) 256
1249 23:45:02.533439 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1250 23:45:02.536732 iDelay=206, Bit 15, Center 77 (-50 ~ 205) 256
1251 23:45:02.536863 ==
1252 23:45:02.540370 Dram Type= 6, Freq= 0, CH_0, rank 1
1253 23:45:02.546558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1254 23:45:02.546683 ==
1255 23:45:02.546805 DQS Delay:
1256 23:45:02.549486 DQS0 = 0, DQS1 = 0
1257 23:45:02.549604 DQM Delay:
1258 23:45:02.549722 DQM0 = 79, DQM1 = 70
1259 23:45:02.553193 DQ Delay:
1260 23:45:02.556490 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =77
1261 23:45:02.559859 DQ4 =85, DQ5 =61, DQ6 =85, DQ7 =85
1262 23:45:02.563197 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1263 23:45:02.566350 DQ12 =77, DQ13 =77, DQ14 =85, DQ15 =77
1264 23:45:02.566473
1265 23:45:02.566593
1266 23:45:02.566702 ==
1267 23:45:02.569981 Dram Type= 6, Freq= 0, CH_0, rank 1
1268 23:45:02.572978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1269 23:45:02.573128 ==
1270 23:45:02.573252
1271 23:45:02.573363
1272 23:45:02.576341 TX Vref Scan disable
1273 23:45:02.576458 == TX Byte 0 ==
1274 23:45:02.583561 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1275 23:45:02.586450 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1276 23:45:02.586531 == TX Byte 1 ==
1277 23:45:02.593351 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1278 23:45:02.596666 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1279 23:45:02.596769 ==
1280 23:45:02.600199 Dram Type= 6, Freq= 0, CH_0, rank 1
1281 23:45:02.603320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1282 23:45:02.603420 ==
1283 23:45:02.616957 TX Vref=22, minBit 9, minWin=26, winSum=433
1284 23:45:02.620280 TX Vref=24, minBit 1, minWin=27, winSum=437
1285 23:45:02.623981 TX Vref=26, minBit 1, minWin=27, winSum=442
1286 23:45:02.626818 TX Vref=28, minBit 1, minWin=27, winSum=441
1287 23:45:02.630251 TX Vref=30, minBit 9, minWin=27, winSum=447
1288 23:45:02.637051 TX Vref=32, minBit 15, minWin=26, winSum=442
1289 23:45:02.640709 [TxChooseVref] Worse bit 9, Min win 27, Win sum 447, Final Vref 30
1290 23:45:02.640842
1291 23:45:02.644037 Final TX Range 1 Vref 30
1292 23:45:02.644132
1293 23:45:02.644210 ==
1294 23:45:02.647352 Dram Type= 6, Freq= 0, CH_0, rank 1
1295 23:45:02.650100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1296 23:45:02.650220 ==
1297 23:45:02.653496
1298 23:45:02.653589
1299 23:45:02.653652 TX Vref Scan disable
1300 23:45:02.656989 == TX Byte 0 ==
1301 23:45:02.660374 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1302 23:45:02.663719 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1303 23:45:02.667021 == TX Byte 1 ==
1304 23:45:02.670415 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1305 23:45:02.673738 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1306 23:45:02.676992
1307 23:45:02.677107 [DATLAT]
1308 23:45:02.677173 Freq=800, CH0 RK1
1309 23:45:02.677235
1310 23:45:02.680233 DATLAT Default: 0xa
1311 23:45:02.680342 0, 0xFFFF, sum = 0
1312 23:45:02.683840 1, 0xFFFF, sum = 0
1313 23:45:02.683969 2, 0xFFFF, sum = 0
1314 23:45:02.686780 3, 0xFFFF, sum = 0
1315 23:45:02.690425 4, 0xFFFF, sum = 0
1316 23:45:02.690569 5, 0xFFFF, sum = 0
1317 23:45:02.693351 6, 0xFFFF, sum = 0
1318 23:45:02.693472 7, 0xFFFF, sum = 0
1319 23:45:02.696994 8, 0xFFFF, sum = 0
1320 23:45:02.697102 9, 0x0, sum = 1
1321 23:45:02.697195 10, 0x0, sum = 2
1322 23:45:02.700142 11, 0x0, sum = 3
1323 23:45:02.700249 12, 0x0, sum = 4
1324 23:45:02.703423 best_step = 10
1325 23:45:02.703540
1326 23:45:02.703653 ==
1327 23:45:02.707404 Dram Type= 6, Freq= 0, CH_0, rank 1
1328 23:45:02.710260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1329 23:45:02.710379 ==
1330 23:45:02.716675 RX Vref Scan: 0
1331 23:45:02.716834
1332 23:45:02.716978 RX Vref 0 -> 0, step: 1
1333 23:45:02.717087
1334 23:45:02.717392 RX Delay -111 -> 252, step: 8
1335 23:45:02.723948 iDelay=209, Bit 0, Center 76 (-39 ~ 192) 232
1336 23:45:02.727112 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1337 23:45:02.730543 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1338 23:45:02.733882 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1339 23:45:02.737184 iDelay=209, Bit 4, Center 76 (-39 ~ 192) 232
1340 23:45:02.744081 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1341 23:45:02.746912 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
1342 23:45:02.750371 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1343 23:45:02.753594 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
1344 23:45:02.757570 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1345 23:45:02.763983 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1346 23:45:02.766994 iDelay=209, Bit 11, Center 60 (-55 ~ 176) 232
1347 23:45:02.770499 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
1348 23:45:02.773795 iDelay=209, Bit 13, Center 72 (-47 ~ 192) 240
1349 23:45:02.780098 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1350 23:45:02.784050 iDelay=209, Bit 15, Center 76 (-39 ~ 192) 232
1351 23:45:02.784141 ==
1352 23:45:02.786724 Dram Type= 6, Freq= 0, CH_0, rank 1
1353 23:45:02.790815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1354 23:45:02.790897 ==
1355 23:45:02.790962 DQS Delay:
1356 23:45:02.794192 DQS0 = 0, DQS1 = 0
1357 23:45:02.794274 DQM Delay:
1358 23:45:02.797066 DQM0 = 78, DQM1 = 69
1359 23:45:02.797149 DQ Delay:
1360 23:45:02.800431 DQ0 =76, DQ1 =84, DQ2 =76, DQ3 =72
1361 23:45:02.803620 DQ4 =76, DQ5 =64, DQ6 =88, DQ7 =92
1362 23:45:02.807081 DQ8 =60, DQ9 =56, DQ10 =72, DQ11 =60
1363 23:45:02.810350 DQ12 =80, DQ13 =72, DQ14 =80, DQ15 =76
1364 23:45:02.810435
1365 23:45:02.810500
1366 23:45:02.820530 [DQSOSCAuto] RK1, (LSB)MR18= 0x4620, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 392 ps
1367 23:45:02.820624 CH0 RK1: MR19=606, MR18=4620
1368 23:45:02.827185 CH0_RK1: MR19=0x606, MR18=0x4620, DQSOSC=392, MR23=63, INC=96, DEC=64
1369 23:45:02.829964 [RxdqsGatingPostProcess] freq 800
1370 23:45:02.837010 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1371 23:45:02.839799 Pre-setting of DQS Precalculation
1372 23:45:02.843657 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1373 23:45:02.843741 ==
1374 23:45:02.846914 Dram Type= 6, Freq= 0, CH_1, rank 0
1375 23:45:02.850141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1376 23:45:02.853061 ==
1377 23:45:02.856436 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1378 23:45:02.863120 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1379 23:45:02.872448 [CA 0] Center 36 (6~66) winsize 61
1380 23:45:02.875401 [CA 1] Center 36 (6~67) winsize 62
1381 23:45:02.879020 [CA 2] Center 34 (4~64) winsize 61
1382 23:45:02.882320 [CA 3] Center 34 (4~64) winsize 61
1383 23:45:02.885513 [CA 4] Center 34 (4~64) winsize 61
1384 23:45:02.888842 [CA 5] Center 34 (4~64) winsize 61
1385 23:45:02.888918
1386 23:45:02.892151 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1387 23:45:02.892249
1388 23:45:02.895597 [CATrainingPosCal] consider 1 rank data
1389 23:45:02.898903 u2DelayCellTimex100 = 270/100 ps
1390 23:45:02.902249 CA0 delay=36 (6~66),Diff = 2 PI (14 cell)
1391 23:45:02.905589 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1392 23:45:02.912395 CA2 delay=34 (4~64),Diff = 0 PI (0 cell)
1393 23:45:02.915812 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1394 23:45:02.918605 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
1395 23:45:02.922087 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1396 23:45:02.922165
1397 23:45:02.925485 CA PerBit enable=1, Macro0, CA PI delay=34
1398 23:45:02.925561
1399 23:45:02.928827 [CBTSetCACLKResult] CA Dly = 34
1400 23:45:02.928953 CS Dly: 5 (0~36)
1401 23:45:02.929066 ==
1402 23:45:02.932227 Dram Type= 6, Freq= 0, CH_1, rank 1
1403 23:45:02.938748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1404 23:45:02.938879 ==
1405 23:45:02.942042 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1406 23:45:02.948216 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1407 23:45:02.958034 [CA 0] Center 37 (7~67) winsize 61
1408 23:45:02.961469 [CA 1] Center 36 (6~67) winsize 62
1409 23:45:02.964742 [CA 2] Center 35 (5~65) winsize 61
1410 23:45:02.968098 [CA 3] Center 33 (3~64) winsize 62
1411 23:45:02.971422 [CA 4] Center 34 (4~65) winsize 62
1412 23:45:02.974693 [CA 5] Center 33 (3~64) winsize 62
1413 23:45:02.974804
1414 23:45:02.978020 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1415 23:45:02.978105
1416 23:45:02.981517 [CATrainingPosCal] consider 2 rank data
1417 23:45:02.984554 u2DelayCellTimex100 = 270/100 ps
1418 23:45:02.988356 CA0 delay=36 (7~66),Diff = 2 PI (14 cell)
1419 23:45:02.995094 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1420 23:45:02.998267 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1421 23:45:03.001027 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1422 23:45:03.004967 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
1423 23:45:03.008235 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1424 23:45:03.008342
1425 23:45:03.011683 CA PerBit enable=1, Macro0, CA PI delay=34
1426 23:45:03.011791
1427 23:45:03.014915 [CBTSetCACLKResult] CA Dly = 34
1428 23:45:03.014998 CS Dly: 6 (0~38)
1429 23:45:03.015068
1430 23:45:03.021382 ----->DramcWriteLeveling(PI) begin...
1431 23:45:03.021513 ==
1432 23:45:03.025001 Dram Type= 6, Freq= 0, CH_1, rank 0
1433 23:45:03.028963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1434 23:45:03.029075 ==
1435 23:45:03.029219 Write leveling (Byte 0): 28 => 28
1436 23:45:03.032880 Write leveling (Byte 1): 28 => 28
1437 23:45:03.036497 DramcWriteLeveling(PI) end<-----
1438 23:45:03.036639
1439 23:45:03.036748 ==
1440 23:45:03.040400 Dram Type= 6, Freq= 0, CH_1, rank 0
1441 23:45:03.044059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1442 23:45:03.044183 ==
1443 23:45:03.048328 [Gating] SW mode calibration
1444 23:45:03.055642 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1445 23:45:03.058800 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1446 23:45:03.065507 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1447 23:45:03.069030 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1448 23:45:03.072352 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1449 23:45:03.079018 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 23:45:03.082372 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 23:45:03.085650 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 23:45:03.089301 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 23:45:03.095516 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 23:45:03.098861 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 23:45:03.102132 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 23:45:03.108847 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 23:45:03.112161 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 23:45:03.115530 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 23:45:03.122234 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 23:45:03.125726 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 23:45:03.128917 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 23:45:03.135411 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 23:45:03.138733 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1464 23:45:03.142002 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1465 23:45:03.148828 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 23:45:03.152584 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 23:45:03.155922 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 23:45:03.162082 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 23:45:03.165732 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 23:45:03.168976 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 23:45:03.172500 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 23:45:03.179137 0 9 8 | B1->B0 | 2a2a 2929 | 1 0 | (1 1) (0 0)
1473 23:45:03.181914 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1474 23:45:03.185833 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1475 23:45:03.192159 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1476 23:45:03.195474 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1477 23:45:03.199208 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 23:45:03.205450 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 23:45:03.208891 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 23:45:03.212184 0 10 8 | B1->B0 | 2929 2d2d | 0 0 | (0 0) (0 1)
1481 23:45:03.218963 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 23:45:03.222355 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 23:45:03.225788 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 23:45:03.232719 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 23:45:03.235891 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 23:45:03.238888 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 23:45:03.246044 0 11 4 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
1488 23:45:03.249208 0 11 8 | B1->B0 | 3838 3737 | 0 1 | (0 0) (0 0)
1489 23:45:03.252533 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1490 23:45:03.255636 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1491 23:45:03.262237 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1492 23:45:03.266052 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 23:45:03.268799 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 23:45:03.275810 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 23:45:03.279142 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1496 23:45:03.282813 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1497 23:45:03.289064 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1498 23:45:03.292177 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 23:45:03.295331 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 23:45:03.302514 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 23:45:03.305725 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 23:45:03.308645 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 23:45:03.315468 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 23:45:03.318854 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 23:45:03.322191 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 23:45:03.328993 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 23:45:03.332436 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 23:45:03.335635 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 23:45:03.342082 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 23:45:03.345724 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 23:45:03.348921 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 23:45:03.355270 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1513 23:45:03.355390 Total UI for P1: 0, mck2ui 16
1514 23:45:03.362216 best dqsien dly found for B0: ( 0, 14, 6)
1515 23:45:03.362334 Total UI for P1: 0, mck2ui 16
1516 23:45:03.365519 best dqsien dly found for B1: ( 0, 14, 6)
1517 23:45:03.371979 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1518 23:45:03.375346 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1519 23:45:03.375432
1520 23:45:03.378609 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1521 23:45:03.381979 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1522 23:45:03.385369 [Gating] SW calibration Done
1523 23:45:03.385492 ==
1524 23:45:03.388523 Dram Type= 6, Freq= 0, CH_1, rank 0
1525 23:45:03.392085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1526 23:45:03.392170 ==
1527 23:45:03.392236 RX Vref Scan: 0
1528 23:45:03.395537
1529 23:45:03.395621 RX Vref 0 -> 0, step: 1
1530 23:45:03.395687
1531 23:45:03.398397 RX Delay -130 -> 252, step: 16
1532 23:45:03.401728 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1533 23:45:03.408652 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1534 23:45:03.412022 iDelay=222, Bit 2, Center 61 (-66 ~ 189) 256
1535 23:45:03.415430 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1536 23:45:03.418584 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1537 23:45:03.421930 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1538 23:45:03.425070 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1539 23:45:03.432012 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1540 23:45:03.435112 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1541 23:45:03.438553 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1542 23:45:03.442084 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1543 23:45:03.445512 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1544 23:45:03.452071 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1545 23:45:03.455311 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1546 23:45:03.458477 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1547 23:45:03.461895 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1548 23:45:03.461969 ==
1549 23:45:03.465376 Dram Type= 6, Freq= 0, CH_1, rank 0
1550 23:45:03.471725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1551 23:45:03.471818 ==
1552 23:45:03.471884 DQS Delay:
1553 23:45:03.475581 DQS0 = 0, DQS1 = 0
1554 23:45:03.475690 DQM Delay:
1555 23:45:03.475784 DQM0 = 80, DQM1 = 71
1556 23:45:03.478488 DQ Delay:
1557 23:45:03.481841 DQ0 =85, DQ1 =77, DQ2 =61, DQ3 =77
1558 23:45:03.485122 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1559 23:45:03.488554 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
1560 23:45:03.491762 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1561 23:45:03.491848
1562 23:45:03.491916
1563 23:45:03.491978 ==
1564 23:45:03.495502 Dram Type= 6, Freq= 0, CH_1, rank 0
1565 23:45:03.498734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1566 23:45:03.498861 ==
1567 23:45:03.498977
1568 23:45:03.499085
1569 23:45:03.502195 TX Vref Scan disable
1570 23:45:03.502317 == TX Byte 0 ==
1571 23:45:03.508226 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1572 23:45:03.511972 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1573 23:45:03.512078 == TX Byte 1 ==
1574 23:45:03.518493 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1575 23:45:03.521908 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1576 23:45:03.522014 ==
1577 23:45:03.524913 Dram Type= 6, Freq= 0, CH_1, rank 0
1578 23:45:03.528445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1579 23:45:03.528552 ==
1580 23:45:03.542446 TX Vref=22, minBit 0, minWin=27, winSum=438
1581 23:45:03.545766 TX Vref=24, minBit 1, minWin=27, winSum=443
1582 23:45:03.549238 TX Vref=26, minBit 1, minWin=26, winSum=443
1583 23:45:03.552023 TX Vref=28, minBit 1, minWin=27, winSum=446
1584 23:45:03.555467 TX Vref=30, minBit 5, minWin=27, winSum=447
1585 23:45:03.559004 TX Vref=32, minBit 6, minWin=27, winSum=449
1586 23:45:03.565911 [TxChooseVref] Worse bit 6, Min win 27, Win sum 449, Final Vref 32
1587 23:45:03.566019
1588 23:45:03.569205 Final TX Range 1 Vref 32
1589 23:45:03.569321
1590 23:45:03.569414 ==
1591 23:45:03.572498 Dram Type= 6, Freq= 0, CH_1, rank 0
1592 23:45:03.575663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1593 23:45:03.575777 ==
1594 23:45:03.575869
1595 23:45:03.579242
1596 23:45:03.579346 TX Vref Scan disable
1597 23:45:03.582057 == TX Byte 0 ==
1598 23:45:03.585914 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1599 23:45:03.588599 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1600 23:45:03.592014 == TX Byte 1 ==
1601 23:45:03.595246 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1602 23:45:03.602194 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1603 23:45:03.602320
1604 23:45:03.602416 [DATLAT]
1605 23:45:03.602516 Freq=800, CH1 RK0
1606 23:45:03.602607
1607 23:45:03.606080 DATLAT Default: 0xa
1608 23:45:03.606173 0, 0xFFFF, sum = 0
1609 23:45:03.609483 1, 0xFFFF, sum = 0
1610 23:45:03.609566 2, 0xFFFF, sum = 0
1611 23:45:03.612770 3, 0xFFFF, sum = 0
1612 23:45:03.612901 4, 0xFFFF, sum = 0
1613 23:45:03.616082 5, 0xFFFF, sum = 0
1614 23:45:03.616208 6, 0xFFFF, sum = 0
1615 23:45:03.619450 7, 0xFFFF, sum = 0
1616 23:45:03.619563 8, 0xFFFF, sum = 0
1617 23:45:03.622712 9, 0x0, sum = 1
1618 23:45:03.622824 10, 0x0, sum = 2
1619 23:45:03.625937 11, 0x0, sum = 3
1620 23:45:03.626049 12, 0x0, sum = 4
1621 23:45:03.629633 best_step = 10
1622 23:45:03.629732
1623 23:45:03.629831 ==
1624 23:45:03.632874 Dram Type= 6, Freq= 0, CH_1, rank 0
1625 23:45:03.636111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1626 23:45:03.636218 ==
1627 23:45:03.639329 RX Vref Scan: 1
1628 23:45:03.639431
1629 23:45:03.639531 Set Vref Range= 32 -> 127
1630 23:45:03.639623
1631 23:45:03.642644 RX Vref 32 -> 127, step: 1
1632 23:45:03.642746
1633 23:45:03.646333 RX Delay -111 -> 252, step: 8
1634 23:45:03.646441
1635 23:45:03.649352 Set Vref, RX VrefLevel [Byte0]: 32
1636 23:45:03.652721 [Byte1]: 32
1637 23:45:03.652821
1638 23:45:03.655966 Set Vref, RX VrefLevel [Byte0]: 33
1639 23:45:03.659210 [Byte1]: 33
1640 23:45:03.662741
1641 23:45:03.662844 Set Vref, RX VrefLevel [Byte0]: 34
1642 23:45:03.666208 [Byte1]: 34
1643 23:45:03.670289
1644 23:45:03.670397 Set Vref, RX VrefLevel [Byte0]: 35
1645 23:45:03.673631 [Byte1]: 35
1646 23:45:03.678214
1647 23:45:03.678302 Set Vref, RX VrefLevel [Byte0]: 36
1648 23:45:03.681573 [Byte1]: 36
1649 23:45:03.685982
1650 23:45:03.686123 Set Vref, RX VrefLevel [Byte0]: 37
1651 23:45:03.689017 [Byte1]: 37
1652 23:45:03.693075
1653 23:45:03.693191 Set Vref, RX VrefLevel [Byte0]: 38
1654 23:45:03.696448 [Byte1]: 38
1655 23:45:03.700907
1656 23:45:03.700988 Set Vref, RX VrefLevel [Byte0]: 39
1657 23:45:03.704093 [Byte1]: 39
1658 23:45:03.708576
1659 23:45:03.708717 Set Vref, RX VrefLevel [Byte0]: 40
1660 23:45:03.711807 [Byte1]: 40
1661 23:45:03.716269
1662 23:45:03.716384 Set Vref, RX VrefLevel [Byte0]: 41
1663 23:45:03.719648 [Byte1]: 41
1664 23:45:03.724070
1665 23:45:03.724179 Set Vref, RX VrefLevel [Byte0]: 42
1666 23:45:03.727423 [Byte1]: 42
1667 23:45:03.731255
1668 23:45:03.731336 Set Vref, RX VrefLevel [Byte0]: 43
1669 23:45:03.735084 [Byte1]: 43
1670 23:45:03.739355
1671 23:45:03.739470 Set Vref, RX VrefLevel [Byte0]: 44
1672 23:45:03.742672 [Byte1]: 44
1673 23:45:03.747137
1674 23:45:03.747244 Set Vref, RX VrefLevel [Byte0]: 45
1675 23:45:03.750140 [Byte1]: 45
1676 23:45:03.754484
1677 23:45:03.754645 Set Vref, RX VrefLevel [Byte0]: 46
1678 23:45:03.757646 [Byte1]: 46
1679 23:45:03.762138
1680 23:45:03.762250 Set Vref, RX VrefLevel [Byte0]: 47
1681 23:45:03.765204 [Byte1]: 47
1682 23:45:03.769849
1683 23:45:03.769980 Set Vref, RX VrefLevel [Byte0]: 48
1684 23:45:03.772928 [Byte1]: 48
1685 23:45:03.777626
1686 23:45:03.777750 Set Vref, RX VrefLevel [Byte0]: 49
1687 23:45:03.780472 [Byte1]: 49
1688 23:45:03.785024
1689 23:45:03.785134 Set Vref, RX VrefLevel [Byte0]: 50
1690 23:45:03.788389 [Byte1]: 50
1691 23:45:03.792755
1692 23:45:03.792868 Set Vref, RX VrefLevel [Byte0]: 51
1693 23:45:03.796029 [Byte1]: 51
1694 23:45:03.800505
1695 23:45:03.800620 Set Vref, RX VrefLevel [Byte0]: 52
1696 23:45:03.803802 [Byte1]: 52
1697 23:45:03.808065
1698 23:45:03.808185 Set Vref, RX VrefLevel [Byte0]: 53
1699 23:45:03.811381 [Byte1]: 53
1700 23:45:03.815741
1701 23:45:03.815827 Set Vref, RX VrefLevel [Byte0]: 54
1702 23:45:03.819116 [Byte1]: 54
1703 23:45:03.823063
1704 23:45:03.826415 Set Vref, RX VrefLevel [Byte0]: 55
1705 23:45:03.829748 [Byte1]: 55
1706 23:45:03.829839
1707 23:45:03.833087 Set Vref, RX VrefLevel [Byte0]: 56
1708 23:45:03.836633 [Byte1]: 56
1709 23:45:03.836710
1710 23:45:03.839889 Set Vref, RX VrefLevel [Byte0]: 57
1711 23:45:03.843265 [Byte1]: 57
1712 23:45:03.843343
1713 23:45:03.846652 Set Vref, RX VrefLevel [Byte0]: 58
1714 23:45:03.849567 [Byte1]: 58
1715 23:45:03.853889
1716 23:45:03.853970 Set Vref, RX VrefLevel [Byte0]: 59
1717 23:45:03.857151 [Byte1]: 59
1718 23:45:03.861471
1719 23:45:03.861567 Set Vref, RX VrefLevel [Byte0]: 60
1720 23:45:03.865122 [Byte1]: 60
1721 23:45:03.869085
1722 23:45:03.869201 Set Vref, RX VrefLevel [Byte0]: 61
1723 23:45:03.872269 [Byte1]: 61
1724 23:45:03.876865
1725 23:45:03.876961 Set Vref, RX VrefLevel [Byte0]: 62
1726 23:45:03.879900 [Byte1]: 62
1727 23:45:03.884329
1728 23:45:03.884442 Set Vref, RX VrefLevel [Byte0]: 63
1729 23:45:03.887814 [Byte1]: 63
1730 23:45:03.892268
1731 23:45:03.892372 Set Vref, RX VrefLevel [Byte0]: 64
1732 23:45:03.895565 [Byte1]: 64
1733 23:45:03.900075
1734 23:45:03.900205 Set Vref, RX VrefLevel [Byte0]: 65
1735 23:45:03.903129 [Byte1]: 65
1736 23:45:03.907631
1737 23:45:03.907746 Set Vref, RX VrefLevel [Byte0]: 66
1738 23:45:03.910921 [Byte1]: 66
1739 23:45:03.915230
1740 23:45:03.915339 Set Vref, RX VrefLevel [Byte0]: 67
1741 23:45:03.918380 [Byte1]: 67
1742 23:45:03.922903
1743 23:45:03.923016 Set Vref, RX VrefLevel [Byte0]: 68
1744 23:45:03.926297 [Byte1]: 68
1745 23:45:03.930152
1746 23:45:03.930236 Set Vref, RX VrefLevel [Byte0]: 69
1747 23:45:03.933947 [Byte1]: 69
1748 23:45:03.937941
1749 23:45:03.938057 Set Vref, RX VrefLevel [Byte0]: 70
1750 23:45:03.941090 [Byte1]: 70
1751 23:45:03.945848
1752 23:45:03.945934 Set Vref, RX VrefLevel [Byte0]: 71
1753 23:45:03.949217 [Byte1]: 71
1754 23:45:03.953137
1755 23:45:03.953215 Set Vref, RX VrefLevel [Byte0]: 72
1756 23:45:03.956512 [Byte1]: 72
1757 23:45:03.960892
1758 23:45:03.960980 Set Vref, RX VrefLevel [Byte0]: 73
1759 23:45:03.964067 [Byte1]: 73
1760 23:45:03.968482
1761 23:45:03.968577 Final RX Vref Byte 0 = 60 to rank0
1762 23:45:03.971890 Final RX Vref Byte 1 = 55 to rank0
1763 23:45:03.975148 Final RX Vref Byte 0 = 60 to rank1
1764 23:45:03.978831 Final RX Vref Byte 1 = 55 to rank1==
1765 23:45:03.981764 Dram Type= 6, Freq= 0, CH_1, rank 0
1766 23:45:03.988320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1767 23:45:03.988442 ==
1768 23:45:03.988542 DQS Delay:
1769 23:45:03.988649 DQS0 = 0, DQS1 = 0
1770 23:45:03.992085 DQM Delay:
1771 23:45:03.992196 DQM0 = 81, DQM1 = 71
1772 23:45:03.995040 DQ Delay:
1773 23:45:03.998300 DQ0 =88, DQ1 =76, DQ2 =68, DQ3 =76
1774 23:45:04.002032 DQ4 =76, DQ5 =92, DQ6 =92, DQ7 =80
1775 23:45:04.002150 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =68
1776 23:45:04.008307 DQ12 =80, DQ13 =76, DQ14 =76, DQ15 =76
1777 23:45:04.008422
1778 23:45:04.008521
1779 23:45:04.014910 [DQSOSCAuto] RK0, (LSB)MR18= 0xe19, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 406 ps
1780 23:45:04.018321 CH1 RK0: MR19=606, MR18=E19
1781 23:45:04.024751 CH1_RK0: MR19=0x606, MR18=0xE19, DQSOSC=403, MR23=63, INC=90, DEC=60
1782 23:45:04.024885
1783 23:45:04.028106 ----->DramcWriteLeveling(PI) begin...
1784 23:45:04.028234 ==
1785 23:45:04.031425 Dram Type= 6, Freq= 0, CH_1, rank 1
1786 23:45:04.034632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1787 23:45:04.034762 ==
1788 23:45:04.038091 Write leveling (Byte 0): 26 => 26
1789 23:45:04.041452 Write leveling (Byte 1): 27 => 27
1790 23:45:04.044468 DramcWriteLeveling(PI) end<-----
1791 23:45:04.044602
1792 23:45:04.044718 ==
1793 23:45:04.048106 Dram Type= 6, Freq= 0, CH_1, rank 1
1794 23:45:04.051392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1795 23:45:04.051512 ==
1796 23:45:04.054765 [Gating] SW mode calibration
1797 23:45:04.061515 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1798 23:45:04.068280 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1799 23:45:04.071378 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1800 23:45:04.074681 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1801 23:45:04.081390 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1802 23:45:04.084485 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1803 23:45:04.088085 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1804 23:45:04.094592 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1805 23:45:04.098312 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 23:45:04.101587 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 23:45:04.107857 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 23:45:04.111479 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 23:45:04.114787 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 23:45:04.121591 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 23:45:04.124624 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 23:45:04.128110 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 23:45:04.134636 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 23:45:04.138033 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 23:45:04.141420 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 23:45:04.144676 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1817 23:45:04.151199 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 23:45:04.155008 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 23:45:04.158305 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 23:45:04.164904 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 23:45:04.168278 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 23:45:04.171594 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 23:45:04.178116 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 23:45:04.181460 0 9 4 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (1 1)
1825 23:45:04.184765 0 9 8 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1826 23:45:04.191284 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1827 23:45:04.194620 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1828 23:45:04.197947 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1829 23:45:04.204304 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1830 23:45:04.207789 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1831 23:45:04.211198 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1832 23:45:04.217632 0 10 4 | B1->B0 | 3333 3030 | 1 0 | (1 0) (0 1)
1833 23:45:04.221246 0 10 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1834 23:45:04.224617 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 23:45:04.231324 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 23:45:04.234722 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 23:45:04.237885 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 23:45:04.244471 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 23:45:04.248158 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 23:45:04.251369 0 11 4 | B1->B0 | 2c2b 3f3e | 1 1 | (0 0) (0 0)
1841 23:45:04.254661 0 11 8 | B1->B0 | 3f3f 4646 | 1 0 | (0 0) (0 0)
1842 23:45:04.261601 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1843 23:45:04.264925 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1844 23:45:04.268135 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1845 23:45:04.274932 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1846 23:45:04.278279 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1847 23:45:04.281588 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1848 23:45:04.288213 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1849 23:45:04.291609 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1850 23:45:04.294930 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1851 23:45:04.301416 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1852 23:45:04.304874 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1853 23:45:04.308234 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 23:45:04.314872 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 23:45:04.318255 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 23:45:04.321617 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 23:45:04.324888 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 23:45:04.331529 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 23:45:04.335306 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 23:45:04.338713 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 23:45:04.344900 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 23:45:04.348616 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 23:45:04.351696 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 23:45:04.358216 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1865 23:45:04.361490 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1866 23:45:04.365083 Total UI for P1: 0, mck2ui 16
1867 23:45:04.368457 best dqsien dly found for B0: ( 0, 14, 4)
1868 23:45:04.371791 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1869 23:45:04.375149 Total UI for P1: 0, mck2ui 16
1870 23:45:04.378367 best dqsien dly found for B1: ( 0, 14, 8)
1871 23:45:04.381583 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1872 23:45:04.384909 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1873 23:45:04.385030
1874 23:45:04.391585 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1875 23:45:04.394991 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1876 23:45:04.395140 [Gating] SW calibration Done
1877 23:45:04.398232 ==
1878 23:45:04.398343 Dram Type= 6, Freq= 0, CH_1, rank 1
1879 23:45:04.405063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1880 23:45:04.405163 ==
1881 23:45:04.405292 RX Vref Scan: 0
1882 23:45:04.405412
1883 23:45:04.408344 RX Vref 0 -> 0, step: 1
1884 23:45:04.408475
1885 23:45:04.411517 RX Delay -130 -> 252, step: 16
1886 23:45:04.415127 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1887 23:45:04.418077 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1888 23:45:04.421640 iDelay=222, Bit 2, Center 61 (-66 ~ 189) 256
1889 23:45:04.428355 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1890 23:45:04.431495 iDelay=222, Bit 4, Center 69 (-50 ~ 189) 240
1891 23:45:04.434495 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1892 23:45:04.437941 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1893 23:45:04.441246 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1894 23:45:04.448282 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1895 23:45:04.451425 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1896 23:45:04.454842 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1897 23:45:04.458068 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1898 23:45:04.461358 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1899 23:45:04.468361 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1900 23:45:04.471379 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1901 23:45:04.474792 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1902 23:45:04.474929 ==
1903 23:45:04.477954 Dram Type= 6, Freq= 0, CH_1, rank 1
1904 23:45:04.481241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1905 23:45:04.484868 ==
1906 23:45:04.485005 DQS Delay:
1907 23:45:04.485107 DQS0 = 0, DQS1 = 0
1908 23:45:04.488109 DQM Delay:
1909 23:45:04.488234 DQM0 = 77, DQM1 = 71
1910 23:45:04.491431 DQ Delay:
1911 23:45:04.491566 DQ0 =85, DQ1 =69, DQ2 =61, DQ3 =77
1912 23:45:04.494665 DQ4 =69, DQ5 =85, DQ6 =93, DQ7 =77
1913 23:45:04.498106 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =61
1914 23:45:04.501400 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1915 23:45:04.501533
1916 23:45:04.501656
1917 23:45:04.504659 ==
1918 23:45:04.507997 Dram Type= 6, Freq= 0, CH_1, rank 1
1919 23:45:04.511366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1920 23:45:04.511485 ==
1921 23:45:04.511583
1922 23:45:04.511675
1923 23:45:04.514678 TX Vref Scan disable
1924 23:45:04.514768 == TX Byte 0 ==
1925 23:45:04.518090 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1926 23:45:04.524446 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1927 23:45:04.524582 == TX Byte 1 ==
1928 23:45:04.527873 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1929 23:45:04.534915 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1930 23:45:04.535049 ==
1931 23:45:04.538211 Dram Type= 6, Freq= 0, CH_1, rank 1
1932 23:45:04.541317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1933 23:45:04.541458 ==
1934 23:45:04.554500 TX Vref=22, minBit 1, minWin=27, winSum=454
1935 23:45:04.557717 TX Vref=24, minBit 5, minWin=28, winSum=457
1936 23:45:04.561058 TX Vref=26, minBit 1, minWin=28, winSum=458
1937 23:45:04.564451 TX Vref=28, minBit 13, minWin=28, winSum=465
1938 23:45:04.567897 TX Vref=30, minBit 5, minWin=27, winSum=462
1939 23:45:04.574398 TX Vref=32, minBit 1, minWin=28, winSum=463
1940 23:45:04.577701 [TxChooseVref] Worse bit 13, Min win 28, Win sum 465, Final Vref 28
1941 23:45:04.577832
1942 23:45:04.581112 Final TX Range 1 Vref 28
1943 23:45:04.581226
1944 23:45:04.581294 ==
1945 23:45:04.584353 Dram Type= 6, Freq= 0, CH_1, rank 1
1946 23:45:04.587896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1947 23:45:04.588015 ==
1948 23:45:04.590766
1949 23:45:04.590871
1950 23:45:04.590951 TX Vref Scan disable
1951 23:45:04.594362 == TX Byte 0 ==
1952 23:45:04.597636 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1953 23:45:04.604144 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1954 23:45:04.604278 == TX Byte 1 ==
1955 23:45:04.608184 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1956 23:45:04.611523 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1957 23:45:04.614307
1958 23:45:04.614395 [DATLAT]
1959 23:45:04.614461 Freq=800, CH1 RK1
1960 23:45:04.614524
1961 23:45:04.618245 DATLAT Default: 0xa
1962 23:45:04.618335 0, 0xFFFF, sum = 0
1963 23:45:04.621053 1, 0xFFFF, sum = 0
1964 23:45:04.621146 2, 0xFFFF, sum = 0
1965 23:45:04.624287 3, 0xFFFF, sum = 0
1966 23:45:04.624401 4, 0xFFFF, sum = 0
1967 23:45:04.627604 5, 0xFFFF, sum = 0
1968 23:45:04.631413 6, 0xFFFF, sum = 0
1969 23:45:04.631503 7, 0xFFFF, sum = 0
1970 23:45:04.634507 8, 0xFFFF, sum = 0
1971 23:45:04.634597 9, 0x0, sum = 1
1972 23:45:04.634666 10, 0x0, sum = 2
1973 23:45:04.637919 11, 0x0, sum = 3
1974 23:45:04.638006 12, 0x0, sum = 4
1975 23:45:04.641154 best_step = 10
1976 23:45:04.641263
1977 23:45:04.641334 ==
1978 23:45:04.644451 Dram Type= 6, Freq= 0, CH_1, rank 1
1979 23:45:04.647723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1980 23:45:04.647847 ==
1981 23:45:04.650948 RX Vref Scan: 0
1982 23:45:04.651075
1983 23:45:04.651169 RX Vref 0 -> 0, step: 1
1984 23:45:04.651247
1985 23:45:04.654533 RX Delay -111 -> 252, step: 8
1986 23:45:04.661406 iDelay=209, Bit 0, Center 84 (-39 ~ 208) 248
1987 23:45:04.664743 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
1988 23:45:04.668092 iDelay=209, Bit 2, Center 68 (-55 ~ 192) 248
1989 23:45:04.671621 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1990 23:45:04.674780 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
1991 23:45:04.681334 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
1992 23:45:04.684540 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
1993 23:45:04.688034 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
1994 23:45:04.691205 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
1995 23:45:04.694545 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
1996 23:45:04.701593 iDelay=209, Bit 10, Center 76 (-47 ~ 200) 248
1997 23:45:04.704573 iDelay=209, Bit 11, Center 68 (-55 ~ 192) 248
1998 23:45:04.708023 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
1999 23:45:04.711370 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2000 23:45:04.714605 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
2001 23:45:04.721088 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2002 23:45:04.721175 ==
2003 23:45:04.724450 Dram Type= 6, Freq= 0, CH_1, rank 1
2004 23:45:04.727855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2005 23:45:04.727941 ==
2006 23:45:04.728008 DQS Delay:
2007 23:45:04.731301 DQS0 = 0, DQS1 = 0
2008 23:45:04.731385 DQM Delay:
2009 23:45:04.734768 DQM0 = 78, DQM1 = 74
2010 23:45:04.734853 DQ Delay:
2011 23:45:04.738215 DQ0 =84, DQ1 =72, DQ2 =68, DQ3 =72
2012 23:45:04.741370 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2013 23:45:04.744498 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =68
2014 23:45:04.747822 DQ12 =84, DQ13 =80, DQ14 =80, DQ15 =80
2015 23:45:04.747908
2016 23:45:04.747974
2017 23:45:04.754587 [DQSOSCAuto] RK1, (LSB)MR18= 0x253d, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 400 ps
2018 23:45:04.757757 CH1 RK1: MR19=606, MR18=253D
2019 23:45:04.764443 CH1_RK1: MR19=0x606, MR18=0x253D, DQSOSC=394, MR23=63, INC=95, DEC=63
2020 23:45:04.768043 [RxdqsGatingPostProcess] freq 800
2021 23:45:04.774997 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2022 23:45:04.778193 Pre-setting of DQS Precalculation
2023 23:45:04.781421 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2024 23:45:04.788197 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2025 23:45:04.794622 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2026 23:45:04.794707
2027 23:45:04.794773
2028 23:45:04.798160 [Calibration Summary] 1600 Mbps
2029 23:45:04.801546 CH 0, Rank 0
2030 23:45:04.801630 SW Impedance : PASS
2031 23:45:04.804624 DUTY Scan : NO K
2032 23:45:04.807885 ZQ Calibration : PASS
2033 23:45:04.807971 Jitter Meter : NO K
2034 23:45:04.811135 CBT Training : PASS
2035 23:45:04.814591 Write leveling : PASS
2036 23:45:04.814675 RX DQS gating : PASS
2037 23:45:04.817965 RX DQ/DQS(RDDQC) : PASS
2038 23:45:04.818049 TX DQ/DQS : PASS
2039 23:45:04.821461 RX DATLAT : PASS
2040 23:45:04.824689 RX DQ/DQS(Engine): PASS
2041 23:45:04.824775 TX OE : NO K
2042 23:45:04.828182 All Pass.
2043 23:45:04.828266
2044 23:45:04.828331 CH 0, Rank 1
2045 23:45:04.831197 SW Impedance : PASS
2046 23:45:04.831282 DUTY Scan : NO K
2047 23:45:04.834417 ZQ Calibration : PASS
2048 23:45:04.838096 Jitter Meter : NO K
2049 23:45:04.838181 CBT Training : PASS
2050 23:45:04.841381 Write leveling : PASS
2051 23:45:04.844816 RX DQS gating : PASS
2052 23:45:04.844924 RX DQ/DQS(RDDQC) : PASS
2053 23:45:04.848009 TX DQ/DQS : PASS
2054 23:45:04.851591 RX DATLAT : PASS
2055 23:45:04.851682 RX DQ/DQS(Engine): PASS
2056 23:45:04.854572 TX OE : NO K
2057 23:45:04.854658 All Pass.
2058 23:45:04.854724
2059 23:45:04.858122 CH 1, Rank 0
2060 23:45:04.858214 SW Impedance : PASS
2061 23:45:04.861611 DUTY Scan : NO K
2062 23:45:04.865111 ZQ Calibration : PASS
2063 23:45:04.865201 Jitter Meter : NO K
2064 23:45:04.867772 CBT Training : PASS
2065 23:45:04.867876 Write leveling : PASS
2066 23:45:04.871134 RX DQS gating : PASS
2067 23:45:04.874631 RX DQ/DQS(RDDQC) : PASS
2068 23:45:04.874713 TX DQ/DQS : PASS
2069 23:45:04.878011 RX DATLAT : PASS
2070 23:45:04.881339 RX DQ/DQS(Engine): PASS
2071 23:45:04.881415 TX OE : NO K
2072 23:45:04.884551 All Pass.
2073 23:45:04.884637
2074 23:45:04.884706 CH 1, Rank 1
2075 23:45:04.888048 SW Impedance : PASS
2076 23:45:04.888131 DUTY Scan : NO K
2077 23:45:04.891590 ZQ Calibration : PASS
2078 23:45:04.894856 Jitter Meter : NO K
2079 23:45:04.894941 CBT Training : PASS
2080 23:45:04.898131 Write leveling : PASS
2081 23:45:04.901696 RX DQS gating : PASS
2082 23:45:04.901781 RX DQ/DQS(RDDQC) : PASS
2083 23:45:04.904863 TX DQ/DQS : PASS
2084 23:45:04.904948 RX DATLAT : PASS
2085 23:45:04.908167 RX DQ/DQS(Engine): PASS
2086 23:45:04.911230 TX OE : NO K
2087 23:45:04.911316 All Pass.
2088 23:45:04.911386
2089 23:45:04.914701 DramC Write-DBI off
2090 23:45:04.918169 PER_BANK_REFRESH: Hybrid Mode
2091 23:45:04.918254 TX_TRACKING: ON
2092 23:45:04.921113 [GetDramInforAfterCalByMRR] Vendor 6.
2093 23:45:04.924903 [GetDramInforAfterCalByMRR] Revision 606.
2094 23:45:04.928161 [GetDramInforAfterCalByMRR] Revision 2 0.
2095 23:45:04.928247 MR0 0x3b3b
2096 23:45:04.931399 MR8 0x5151
2097 23:45:04.934638 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2098 23:45:04.934723
2099 23:45:04.934788 MR0 0x3b3b
2100 23:45:04.937728 MR8 0x5151
2101 23:45:04.941171 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2102 23:45:04.941254
2103 23:45:04.947986 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2104 23:45:04.951353 [FAST_K] Save calibration result to emmc
2105 23:45:04.957884 [FAST_K] Save calibration result to emmc
2106 23:45:04.957972 dram_init: config_dvfs: 1
2107 23:45:04.961066 dramc_set_vcore_voltage set vcore to 662500
2108 23:45:04.964502 Read voltage for 1200, 2
2109 23:45:04.964596 Vio18 = 0
2110 23:45:04.967868 Vcore = 662500
2111 23:45:04.967951 Vdram = 0
2112 23:45:04.968017 Vddq = 0
2113 23:45:04.971200 Vmddr = 0
2114 23:45:04.974489 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2115 23:45:04.981273 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2116 23:45:04.981359 MEM_TYPE=3, freq_sel=15
2117 23:45:04.984612 sv_algorithm_assistance_LP4_1600
2118 23:45:04.991147 ============ PULL DRAM RESETB DOWN ============
2119 23:45:04.994964 ========== PULL DRAM RESETB DOWN end =========
2120 23:45:04.998311 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2121 23:45:05.001233 ===================================
2122 23:45:05.004761 LPDDR4 DRAM CONFIGURATION
2123 23:45:05.008027 ===================================
2124 23:45:05.008137 EX_ROW_EN[0] = 0x0
2125 23:45:05.011378 EX_ROW_EN[1] = 0x0
2126 23:45:05.014556 LP4Y_EN = 0x0
2127 23:45:05.014661 WORK_FSP = 0x0
2128 23:45:05.018045 WL = 0x4
2129 23:45:05.018133 RL = 0x4
2130 23:45:05.021319 BL = 0x2
2131 23:45:05.021426 RPST = 0x0
2132 23:45:05.024687 RD_PRE = 0x0
2133 23:45:05.024763 WR_PRE = 0x1
2134 23:45:05.028159 WR_PST = 0x0
2135 23:45:05.028261 DBI_WR = 0x0
2136 23:45:05.031275 DBI_RD = 0x0
2137 23:45:05.031375 OTF = 0x1
2138 23:45:05.034615 ===================================
2139 23:45:05.037984 ===================================
2140 23:45:05.041327 ANA top config
2141 23:45:05.044759 ===================================
2142 23:45:05.044868 DLL_ASYNC_EN = 0
2143 23:45:05.047863 ALL_SLAVE_EN = 0
2144 23:45:05.051043 NEW_RANK_MODE = 1
2145 23:45:05.054790 DLL_IDLE_MODE = 1
2146 23:45:05.054872 LP45_APHY_COMB_EN = 1
2147 23:45:05.057739 TX_ODT_DIS = 1
2148 23:45:05.061352 NEW_8X_MODE = 1
2149 23:45:05.064589 ===================================
2150 23:45:05.067834 ===================================
2151 23:45:05.071234 data_rate = 2400
2152 23:45:05.074966 CKR = 1
2153 23:45:05.077798 DQ_P2S_RATIO = 8
2154 23:45:05.081182 ===================================
2155 23:45:05.081285 CA_P2S_RATIO = 8
2156 23:45:05.084531 DQ_CA_OPEN = 0
2157 23:45:05.087994 DQ_SEMI_OPEN = 0
2158 23:45:05.091441 CA_SEMI_OPEN = 0
2159 23:45:05.094497 CA_FULL_RATE = 0
2160 23:45:05.094578 DQ_CKDIV4_EN = 0
2161 23:45:05.097846 CA_CKDIV4_EN = 0
2162 23:45:05.101074 CA_PREDIV_EN = 0
2163 23:45:05.104449 PH8_DLY = 17
2164 23:45:05.107707 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2165 23:45:05.111075 DQ_AAMCK_DIV = 4
2166 23:45:05.111153 CA_AAMCK_DIV = 4
2167 23:45:05.114488 CA_ADMCK_DIV = 4
2168 23:45:05.117700 DQ_TRACK_CA_EN = 0
2169 23:45:05.121173 CA_PICK = 1200
2170 23:45:05.124409 CA_MCKIO = 1200
2171 23:45:05.128269 MCKIO_SEMI = 0
2172 23:45:05.131533 PLL_FREQ = 2366
2173 23:45:05.134404 DQ_UI_PI_RATIO = 32
2174 23:45:05.134510 CA_UI_PI_RATIO = 0
2175 23:45:05.138183 ===================================
2176 23:45:05.141436 ===================================
2177 23:45:05.144710 memory_type:LPDDR4
2178 23:45:05.148024 GP_NUM : 10
2179 23:45:05.148139 SRAM_EN : 1
2180 23:45:05.151481 MD32_EN : 0
2181 23:45:05.154748 ===================================
2182 23:45:05.157570 [ANA_INIT] >>>>>>>>>>>>>>
2183 23:45:05.157668 <<<<<< [CONFIGURE PHASE]: ANA_TX
2184 23:45:05.164550 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2185 23:45:05.168127 ===================================
2186 23:45:05.168225 data_rate = 2400,PCW = 0X5b00
2187 23:45:05.171031 ===================================
2188 23:45:05.174571 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2189 23:45:05.181486 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2190 23:45:05.188004 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2191 23:45:05.191386 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2192 23:45:05.194715 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2193 23:45:05.197597 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2194 23:45:05.201421 [ANA_INIT] flow start
2195 23:45:05.201529 [ANA_INIT] PLL >>>>>>>>
2196 23:45:05.204654 [ANA_INIT] PLL <<<<<<<<
2197 23:45:05.208055 [ANA_INIT] MIDPI >>>>>>>>
2198 23:45:05.208144 [ANA_INIT] MIDPI <<<<<<<<
2199 23:45:05.211351 [ANA_INIT] DLL >>>>>>>>
2200 23:45:05.214759 [ANA_INIT] DLL <<<<<<<<
2201 23:45:05.214840 [ANA_INIT] flow end
2202 23:45:05.220855 ============ LP4 DIFF to SE enter ============
2203 23:45:05.224723 ============ LP4 DIFF to SE exit ============
2204 23:45:05.227857 [ANA_INIT] <<<<<<<<<<<<<
2205 23:45:05.230875 [Flow] Enable top DCM control >>>>>
2206 23:45:05.234255 [Flow] Enable top DCM control <<<<<
2207 23:45:05.234371 Enable DLL master slave shuffle
2208 23:45:05.241235 ==============================================================
2209 23:45:05.244391 Gating Mode config
2210 23:45:05.247756 ==============================================================
2211 23:45:05.251129 Config description:
2212 23:45:05.261106 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2213 23:45:05.268000 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2214 23:45:05.271113 SELPH_MODE 0: By rank 1: By Phase
2215 23:45:05.277648 ==============================================================
2216 23:45:05.281094 GAT_TRACK_EN = 1
2217 23:45:05.284491 RX_GATING_MODE = 2
2218 23:45:05.287772 RX_GATING_TRACK_MODE = 2
2219 23:45:05.287858 SELPH_MODE = 1
2220 23:45:05.291043 PICG_EARLY_EN = 1
2221 23:45:05.294343 VALID_LAT_VALUE = 1
2222 23:45:05.301294 ==============================================================
2223 23:45:05.304266 Enter into Gating configuration >>>>
2224 23:45:05.307763 Exit from Gating configuration <<<<
2225 23:45:05.311040 Enter into DVFS_PRE_config >>>>>
2226 23:45:05.321068 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2227 23:45:05.324395 Exit from DVFS_PRE_config <<<<<
2228 23:45:05.327791 Enter into PICG configuration >>>>
2229 23:45:05.331124 Exit from PICG configuration <<<<
2230 23:45:05.334474 [RX_INPUT] configuration >>>>>
2231 23:45:05.337897 [RX_INPUT] configuration <<<<<
2232 23:45:05.341163 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2233 23:45:05.347583 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2234 23:45:05.354304 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2235 23:45:05.361256 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2236 23:45:05.364472 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2237 23:45:05.371208 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2238 23:45:05.374487 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2239 23:45:05.380894 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2240 23:45:05.384333 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2241 23:45:05.387696 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2242 23:45:05.391158 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2243 23:45:05.397798 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2244 23:45:05.401283 ===================================
2245 23:45:05.401369 LPDDR4 DRAM CONFIGURATION
2246 23:45:05.404248 ===================================
2247 23:45:05.407962 EX_ROW_EN[0] = 0x0
2248 23:45:05.411251 EX_ROW_EN[1] = 0x0
2249 23:45:05.411335 LP4Y_EN = 0x0
2250 23:45:05.414376 WORK_FSP = 0x0
2251 23:45:05.414464 WL = 0x4
2252 23:45:05.418105 RL = 0x4
2253 23:45:05.418190 BL = 0x2
2254 23:45:05.421135 RPST = 0x0
2255 23:45:05.421219 RD_PRE = 0x0
2256 23:45:05.424548 WR_PRE = 0x1
2257 23:45:05.424643 WR_PST = 0x0
2258 23:45:05.427816 DBI_WR = 0x0
2259 23:45:05.427900 DBI_RD = 0x0
2260 23:45:05.431012 OTF = 0x1
2261 23:45:05.434432 ===================================
2262 23:45:05.437705 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2263 23:45:05.441157 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2264 23:45:05.447576 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2265 23:45:05.451028 ===================================
2266 23:45:05.451113 LPDDR4 DRAM CONFIGURATION
2267 23:45:05.454190 ===================================
2268 23:45:05.457472 EX_ROW_EN[0] = 0x10
2269 23:45:05.460816 EX_ROW_EN[1] = 0x0
2270 23:45:05.460900 LP4Y_EN = 0x0
2271 23:45:05.464149 WORK_FSP = 0x0
2272 23:45:05.464233 WL = 0x4
2273 23:45:05.467502 RL = 0x4
2274 23:45:05.467587 BL = 0x2
2275 23:45:05.470937 RPST = 0x0
2276 23:45:05.471053 RD_PRE = 0x0
2277 23:45:05.474315 WR_PRE = 0x1
2278 23:45:05.474399 WR_PST = 0x0
2279 23:45:05.477499 DBI_WR = 0x0
2280 23:45:05.477584 DBI_RD = 0x0
2281 23:45:05.481036 OTF = 0x1
2282 23:45:05.484310 ===================================
2283 23:45:05.491006 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2284 23:45:05.491096 ==
2285 23:45:05.494398 Dram Type= 6, Freq= 0, CH_0, rank 0
2286 23:45:05.497857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2287 23:45:05.497944 ==
2288 23:45:05.500648 [Duty_Offset_Calibration]
2289 23:45:05.500732 B0:2 B1:0 CA:3
2290 23:45:05.500797
2291 23:45:05.504016 [DutyScan_Calibration_Flow] k_type=0
2292 23:45:05.514125
2293 23:45:05.514226 ==CLK 0==
2294 23:45:05.517592 Final CLK duty delay cell = 0
2295 23:45:05.520804 [0] MAX Duty = 5062%(X100), DQS PI = 28
2296 23:45:05.523905 [0] MIN Duty = 4906%(X100), DQS PI = 54
2297 23:45:05.523989 [0] AVG Duty = 4984%(X100)
2298 23:45:05.527423
2299 23:45:05.530403 CH0 CLK Duty spec in!! Max-Min= 156%
2300 23:45:05.533711 [DutyScan_Calibration_Flow] ====Done====
2301 23:45:05.533795
2302 23:45:05.537381 [DutyScan_Calibration_Flow] k_type=1
2303 23:45:05.552521
2304 23:45:05.552630 ==DQS 0 ==
2305 23:45:05.555758 Final DQS duty delay cell = 0
2306 23:45:05.559002 [0] MAX Duty = 5062%(X100), DQS PI = 14
2307 23:45:05.562235 [0] MIN Duty = 4907%(X100), DQS PI = 2
2308 23:45:05.562338 [0] AVG Duty = 4984%(X100)
2309 23:45:05.566083
2310 23:45:05.566158 ==DQS 1 ==
2311 23:45:05.569337 Final DQS duty delay cell = -4
2312 23:45:05.572777 [-4] MAX Duty = 4969%(X100), DQS PI = 24
2313 23:45:05.576189 [-4] MIN Duty = 4875%(X100), DQS PI = 14
2314 23:45:05.579373 [-4] AVG Duty = 4922%(X100)
2315 23:45:05.579482
2316 23:45:05.582561 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2317 23:45:05.582662
2318 23:45:05.585804 CH0 DQS 1 Duty spec in!! Max-Min= 94%
2319 23:45:05.588884 [DutyScan_Calibration_Flow] ====Done====
2320 23:45:05.588962
2321 23:45:05.592449 [DutyScan_Calibration_Flow] k_type=3
2322 23:45:05.609710
2323 23:45:05.609808 ==DQM 0 ==
2324 23:45:05.613083 Final DQM duty delay cell = 0
2325 23:45:05.616959 [0] MAX Duty = 5124%(X100), DQS PI = 28
2326 23:45:05.620161 [0] MIN Duty = 4876%(X100), DQS PI = 48
2327 23:45:05.623150 [0] AVG Duty = 5000%(X100)
2328 23:45:05.623234
2329 23:45:05.623300 ==DQM 1 ==
2330 23:45:05.626816 Final DQM duty delay cell = 4
2331 23:45:05.629982 [4] MAX Duty = 5124%(X100), DQS PI = 50
2332 23:45:05.633169 [4] MIN Duty = 5000%(X100), DQS PI = 16
2333 23:45:05.636510 [4] AVG Duty = 5062%(X100)
2334 23:45:05.636618
2335 23:45:05.639672 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2336 23:45:05.639792
2337 23:45:05.643090 CH0 DQM 1 Duty spec in!! Max-Min= 124%
2338 23:45:05.646827 [DutyScan_Calibration_Flow] ====Done====
2339 23:45:05.646939
2340 23:45:05.649811 [DutyScan_Calibration_Flow] k_type=2
2341 23:45:05.665121
2342 23:45:05.665244 ==DQ 0 ==
2343 23:45:05.668526 Final DQ duty delay cell = -4
2344 23:45:05.671337 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2345 23:45:05.674633 [-4] MIN Duty = 4907%(X100), DQS PI = 44
2346 23:45:05.678089 [-4] AVG Duty = 4969%(X100)
2347 23:45:05.678207
2348 23:45:05.678303 ==DQ 1 ==
2349 23:45:05.681289 Final DQ duty delay cell = -4
2350 23:45:05.684610 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2351 23:45:05.688417 [-4] MIN Duty = 4876%(X100), DQS PI = 20
2352 23:45:05.691624 [-4] AVG Duty = 4938%(X100)
2353 23:45:05.691752
2354 23:45:05.694475 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2355 23:45:05.694601
2356 23:45:05.698311 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2357 23:45:05.701698 [DutyScan_Calibration_Flow] ====Done====
2358 23:45:05.701825 ==
2359 23:45:05.705050 Dram Type= 6, Freq= 0, CH_1, rank 0
2360 23:45:05.708148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2361 23:45:05.708278 ==
2362 23:45:05.711571 [Duty_Offset_Calibration]
2363 23:45:05.711694 B0:1 B1:-2 CA:0
2364 23:45:05.711806
2365 23:45:05.714870 [DutyScan_Calibration_Flow] k_type=0
2366 23:45:05.725468
2367 23:45:05.725592 ==CLK 0==
2368 23:45:05.728674 Final CLK duty delay cell = 0
2369 23:45:05.732020 [0] MAX Duty = 5031%(X100), DQS PI = 16
2370 23:45:05.735721 [0] MIN Duty = 4844%(X100), DQS PI = 58
2371 23:45:05.735822 [0] AVG Duty = 4937%(X100)
2372 23:45:05.739214
2373 23:45:05.742032 CH1 CLK Duty spec in!! Max-Min= 187%
2374 23:45:05.745883 [DutyScan_Calibration_Flow] ====Done====
2375 23:45:05.745975
2376 23:45:05.748574 [DutyScan_Calibration_Flow] k_type=1
2377 23:45:05.763888
2378 23:45:05.763980 ==DQS 0 ==
2379 23:45:05.768020 Final DQS duty delay cell = -4
2380 23:45:05.770774 [-4] MAX Duty = 5000%(X100), DQS PI = 24
2381 23:45:05.773981 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2382 23:45:05.777527 [-4] AVG Duty = 4953%(X100)
2383 23:45:05.777633
2384 23:45:05.777721 ==DQS 1 ==
2385 23:45:05.780936 Final DQS duty delay cell = 0
2386 23:45:05.784323 [0] MAX Duty = 5093%(X100), DQS PI = 2
2387 23:45:05.787646 [0] MIN Duty = 4875%(X100), DQS PI = 26
2388 23:45:05.790753 [0] AVG Duty = 4984%(X100)
2389 23:45:05.790840
2390 23:45:05.793947 CH1 DQS 0 Duty spec in!! Max-Min= 93%
2391 23:45:05.794036
2392 23:45:05.797305 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2393 23:45:05.800668 [DutyScan_Calibration_Flow] ====Done====
2394 23:45:05.800755
2395 23:45:05.804098 [DutyScan_Calibration_Flow] k_type=3
2396 23:45:05.820465
2397 23:45:05.820611 ==DQM 0 ==
2398 23:45:05.824072 Final DQM duty delay cell = 0
2399 23:45:05.827171 [0] MAX Duty = 5000%(X100), DQS PI = 22
2400 23:45:05.830580 [0] MIN Duty = 4876%(X100), DQS PI = 4
2401 23:45:05.830692 [0] AVG Duty = 4938%(X100)
2402 23:45:05.833757
2403 23:45:05.833869 ==DQM 1 ==
2404 23:45:05.837302 Final DQM duty delay cell = 0
2405 23:45:05.840749 [0] MAX Duty = 5031%(X100), DQS PI = 36
2406 23:45:05.843881 [0] MIN Duty = 4907%(X100), DQS PI = 0
2407 23:45:05.843995 [0] AVG Duty = 4969%(X100)
2408 23:45:05.847118
2409 23:45:05.850789 CH1 DQM 0 Duty spec in!! Max-Min= 124%
2410 23:45:05.850902
2411 23:45:05.854003 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2412 23:45:05.857381 [DutyScan_Calibration_Flow] ====Done====
2413 23:45:05.857490
2414 23:45:05.860675 [DutyScan_Calibration_Flow] k_type=2
2415 23:45:05.876999
2416 23:45:05.877121 ==DQ 0 ==
2417 23:45:05.880163 Final DQ duty delay cell = 0
2418 23:45:05.883328 [0] MAX Duty = 5062%(X100), DQS PI = 12
2419 23:45:05.886834 [0] MIN Duty = 4938%(X100), DQS PI = 54
2420 23:45:05.886946 [0] AVG Duty = 5000%(X100)
2421 23:45:05.887052
2422 23:45:05.890147 ==DQ 1 ==
2423 23:45:05.893345 Final DQ duty delay cell = 0
2424 23:45:05.896958 [0] MAX Duty = 5125%(X100), DQS PI = 36
2425 23:45:05.900055 [0] MIN Duty = 5000%(X100), DQS PI = 24
2426 23:45:05.900177 [0] AVG Duty = 5062%(X100)
2427 23:45:05.900286
2428 23:45:05.903916 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2429 23:45:05.906791
2430 23:45:05.910145 CH1 DQ 1 Duty spec in!! Max-Min= 125%
2431 23:45:05.913380 [DutyScan_Calibration_Flow] ====Done====
2432 23:45:05.917360 nWR fixed to 30
2433 23:45:05.917480 [ModeRegInit_LP4] CH0 RK0
2434 23:45:05.920165 [ModeRegInit_LP4] CH0 RK1
2435 23:45:05.923423 [ModeRegInit_LP4] CH1 RK0
2436 23:45:05.923538 [ModeRegInit_LP4] CH1 RK1
2437 23:45:05.927160 match AC timing 7
2438 23:45:05.930052 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2439 23:45:05.933835 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2440 23:45:05.940343 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2441 23:45:05.943838 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2442 23:45:05.950534 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2443 23:45:05.950659 ==
2444 23:45:05.953706 Dram Type= 6, Freq= 0, CH_0, rank 0
2445 23:45:05.956987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2446 23:45:05.957105 ==
2447 23:45:05.963491 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2448 23:45:05.966905 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2449 23:45:05.976848 [CA 0] Center 40 (10~71) winsize 62
2450 23:45:05.980238 [CA 1] Center 40 (10~70) winsize 61
2451 23:45:05.983630 [CA 2] Center 36 (6~66) winsize 61
2452 23:45:05.986833 [CA 3] Center 35 (5~66) winsize 62
2453 23:45:05.990221 [CA 4] Center 34 (4~65) winsize 62
2454 23:45:05.993497 [CA 5] Center 33 (3~64) winsize 62
2455 23:45:05.993614
2456 23:45:05.996868 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2457 23:45:05.996982
2458 23:45:06.000082 [CATrainingPosCal] consider 1 rank data
2459 23:45:06.003916 u2DelayCellTimex100 = 270/100 ps
2460 23:45:06.007211 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2461 23:45:06.013456 CA1 delay=40 (10~70),Diff = 7 PI (33 cell)
2462 23:45:06.017353 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2463 23:45:06.020128 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2464 23:45:06.023548 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2465 23:45:06.026840 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2466 23:45:06.026951
2467 23:45:06.030123 CA PerBit enable=1, Macro0, CA PI delay=33
2468 23:45:06.030237
2469 23:45:06.034011 [CBTSetCACLKResult] CA Dly = 33
2470 23:45:06.034126 CS Dly: 7 (0~38)
2471 23:45:06.037374 ==
2472 23:45:06.040163 Dram Type= 6, Freq= 0, CH_0, rank 1
2473 23:45:06.043975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2474 23:45:06.044089 ==
2475 23:45:06.047199 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2476 23:45:06.053881 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2477 23:45:06.063128 [CA 0] Center 40 (10~70) winsize 61
2478 23:45:06.066708 [CA 1] Center 40 (10~70) winsize 61
2479 23:45:06.069693 [CA 2] Center 35 (5~66) winsize 62
2480 23:45:06.073013 [CA 3] Center 35 (5~66) winsize 62
2481 23:45:06.076468 [CA 4] Center 34 (4~65) winsize 62
2482 23:45:06.079818 [CA 5] Center 33 (3~64) winsize 62
2483 23:45:06.079926
2484 23:45:06.083431 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2485 23:45:06.083545
2486 23:45:06.086620 [CATrainingPosCal] consider 2 rank data
2487 23:45:06.089983 u2DelayCellTimex100 = 270/100 ps
2488 23:45:06.093475 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2489 23:45:06.099857 CA1 delay=40 (10~70),Diff = 7 PI (33 cell)
2490 23:45:06.103171 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2491 23:45:06.106449 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2492 23:45:06.110202 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2493 23:45:06.113389 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2494 23:45:06.113505
2495 23:45:06.116694 CA PerBit enable=1, Macro0, CA PI delay=33
2496 23:45:06.116802
2497 23:45:06.119870 [CBTSetCACLKResult] CA Dly = 33
2498 23:45:06.119977 CS Dly: 8 (0~40)
2499 23:45:06.123007
2500 23:45:06.126742 ----->DramcWriteLeveling(PI) begin...
2501 23:45:06.126856 ==
2502 23:45:06.130093 Dram Type= 6, Freq= 0, CH_0, rank 0
2503 23:45:06.132829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2504 23:45:06.132943 ==
2505 23:45:06.136467 Write leveling (Byte 0): 33 => 33
2506 23:45:06.139920 Write leveling (Byte 1): 28 => 28
2507 23:45:06.143179 DramcWriteLeveling(PI) end<-----
2508 23:45:06.143323
2509 23:45:06.143419 ==
2510 23:45:06.146626 Dram Type= 6, Freq= 0, CH_0, rank 0
2511 23:45:06.149913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2512 23:45:06.150017 ==
2513 23:45:06.153269 [Gating] SW mode calibration
2514 23:45:06.159793 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2515 23:45:06.166491 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2516 23:45:06.169945 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2517 23:45:06.173288 0 15 4 | B1->B0 | 2424 3333 | 1 0 | (0 0) (0 0)
2518 23:45:06.179302 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2519 23:45:06.182940 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2520 23:45:06.186339 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2521 23:45:06.192734 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2522 23:45:06.196085 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2523 23:45:06.199254 0 15 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2524 23:45:06.206249 1 0 0 | B1->B0 | 3232 2b2b | 1 0 | (1 0) (1 0)
2525 23:45:06.209631 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2526 23:45:06.212460 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2527 23:45:06.219088 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2528 23:45:06.222495 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2529 23:45:06.225820 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2530 23:45:06.232313 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2531 23:45:06.236002 1 0 28 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
2532 23:45:06.239285 1 1 0 | B1->B0 | 2727 3131 | 0 1 | (0 0) (0 0)
2533 23:45:06.242586 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2534 23:45:06.249229 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2535 23:45:06.252410 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2536 23:45:06.255776 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2537 23:45:06.262309 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2538 23:45:06.265595 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2539 23:45:06.269041 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2540 23:45:06.275829 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2541 23:45:06.279146 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2542 23:45:06.282456 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2543 23:45:06.289048 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2544 23:45:06.292385 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 23:45:06.295830 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 23:45:06.302440 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 23:45:06.305942 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 23:45:06.309520 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 23:45:06.315812 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 23:45:06.318853 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 23:45:06.322168 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 23:45:06.328743 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 23:45:06.332078 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 23:45:06.335416 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 23:45:06.342515 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2556 23:45:06.346009 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2557 23:45:06.349566 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2558 23:45:06.352121 Total UI for P1: 0, mck2ui 16
2559 23:45:06.355891 best dqsien dly found for B0: ( 1, 3, 30)
2560 23:45:06.359081 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2561 23:45:06.362141 Total UI for P1: 0, mck2ui 16
2562 23:45:06.365343 best dqsien dly found for B1: ( 1, 4, 2)
2563 23:45:06.368694 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2564 23:45:06.375437 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2565 23:45:06.375525
2566 23:45:06.378778 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2567 23:45:06.382150 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2568 23:45:06.385542 [Gating] SW calibration Done
2569 23:45:06.385613 ==
2570 23:45:06.388825 Dram Type= 6, Freq= 0, CH_0, rank 0
2571 23:45:06.391998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2572 23:45:06.392071 ==
2573 23:45:06.392136 RX Vref Scan: 0
2574 23:45:06.392223
2575 23:45:06.395319 RX Vref 0 -> 0, step: 1
2576 23:45:06.395426
2577 23:45:06.398621 RX Delay -40 -> 252, step: 8
2578 23:45:06.402008 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2579 23:45:06.405425 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2580 23:45:06.411908 iDelay=200, Bit 2, Center 111 (32 ~ 191) 160
2581 23:45:06.415617 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2582 23:45:06.418668 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2583 23:45:06.422075 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2584 23:45:06.425413 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2585 23:45:06.432007 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2586 23:45:06.435579 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2587 23:45:06.438997 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2588 23:45:06.441981 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2589 23:45:06.445321 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2590 23:45:06.448685 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2591 23:45:06.455429 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2592 23:45:06.458684 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2593 23:45:06.461899 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2594 23:45:06.461975 ==
2595 23:45:06.465488 Dram Type= 6, Freq= 0, CH_0, rank 0
2596 23:45:06.468929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2597 23:45:06.469006 ==
2598 23:45:06.471887 DQS Delay:
2599 23:45:06.471968 DQS0 = 0, DQS1 = 0
2600 23:45:06.475123 DQM Delay:
2601 23:45:06.475229 DQM0 = 112, DQM1 = 102
2602 23:45:06.478682 DQ Delay:
2603 23:45:06.482059 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2604 23:45:06.485553 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2605 23:45:06.488780 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
2606 23:45:06.492152 DQ12 =111, DQ13 =111, DQ14 =115, DQ15 =111
2607 23:45:06.492272
2608 23:45:06.492368
2609 23:45:06.492467 ==
2610 23:45:06.495360 Dram Type= 6, Freq= 0, CH_0, rank 0
2611 23:45:06.498586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2612 23:45:06.498692 ==
2613 23:45:06.498800
2614 23:45:06.498889
2615 23:45:06.501902 TX Vref Scan disable
2616 23:45:06.505843 == TX Byte 0 ==
2617 23:45:06.508983 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2618 23:45:06.512310 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2619 23:45:06.515532 == TX Byte 1 ==
2620 23:45:06.518920 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2621 23:45:06.522275 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2622 23:45:06.522391 ==
2623 23:45:06.525564 Dram Type= 6, Freq= 0, CH_0, rank 0
2624 23:45:06.528974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2625 23:45:06.529085 ==
2626 23:45:06.542283 TX Vref=22, minBit 0, minWin=25, winSum=414
2627 23:45:06.545329 TX Vref=24, minBit 9, minWin=25, winSum=422
2628 23:45:06.548838 TX Vref=26, minBit 7, minWin=25, winSum=427
2629 23:45:06.552090 TX Vref=28, minBit 7, minWin=26, winSum=428
2630 23:45:06.555409 TX Vref=30, minBit 10, minWin=26, winSum=433
2631 23:45:06.559393 TX Vref=32, minBit 8, minWin=25, winSum=427
2632 23:45:06.565541 [TxChooseVref] Worse bit 10, Min win 26, Win sum 433, Final Vref 30
2633 23:45:06.565622
2634 23:45:06.569213 Final TX Range 1 Vref 30
2635 23:45:06.569289
2636 23:45:06.569351 ==
2637 23:45:06.572413 Dram Type= 6, Freq= 0, CH_0, rank 0
2638 23:45:06.575863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2639 23:45:06.575995 ==
2640 23:45:06.579225
2641 23:45:06.579340
2642 23:45:06.579433 TX Vref Scan disable
2643 23:45:06.582071 == TX Byte 0 ==
2644 23:45:06.585646 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2645 23:45:06.588678 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2646 23:45:06.592250 == TX Byte 1 ==
2647 23:45:06.595160 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2648 23:45:06.602216 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2649 23:45:06.602298
2650 23:45:06.602367 [DATLAT]
2651 23:45:06.602428 Freq=1200, CH0 RK0
2652 23:45:06.602487
2653 23:45:06.605052 DATLAT Default: 0xd
2654 23:45:06.605123 0, 0xFFFF, sum = 0
2655 23:45:06.608880 1, 0xFFFF, sum = 0
2656 23:45:06.612328 2, 0xFFFF, sum = 0
2657 23:45:06.612402 3, 0xFFFF, sum = 0
2658 23:45:06.615092 4, 0xFFFF, sum = 0
2659 23:45:06.615164 5, 0xFFFF, sum = 0
2660 23:45:06.618321 6, 0xFFFF, sum = 0
2661 23:45:06.618395 7, 0xFFFF, sum = 0
2662 23:45:06.622038 8, 0xFFFF, sum = 0
2663 23:45:06.622115 9, 0xFFFF, sum = 0
2664 23:45:06.625405 10, 0xFFFF, sum = 0
2665 23:45:06.625477 11, 0xFFFF, sum = 0
2666 23:45:06.628838 12, 0x0, sum = 1
2667 23:45:06.628940 13, 0x0, sum = 2
2668 23:45:06.631691 14, 0x0, sum = 3
2669 23:45:06.631784 15, 0x0, sum = 4
2670 23:45:06.634996 best_step = 13
2671 23:45:06.635068
2672 23:45:06.635128 ==
2673 23:45:06.638422 Dram Type= 6, Freq= 0, CH_0, rank 0
2674 23:45:06.641903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2675 23:45:06.641979 ==
2676 23:45:06.642041 RX Vref Scan: 1
2677 23:45:06.644909
2678 23:45:06.644990 Set Vref Range= 32 -> 127
2679 23:45:06.645054
2680 23:45:06.648378 RX Vref 32 -> 127, step: 1
2681 23:45:06.648450
2682 23:45:06.652047 RX Delay -37 -> 252, step: 4
2683 23:45:06.652130
2684 23:45:06.654905 Set Vref, RX VrefLevel [Byte0]: 32
2685 23:45:06.658133 [Byte1]: 32
2686 23:45:06.658238
2687 23:45:06.661859 Set Vref, RX VrefLevel [Byte0]: 33
2688 23:45:06.665260 [Byte1]: 33
2689 23:45:06.668537
2690 23:45:06.668626 Set Vref, RX VrefLevel [Byte0]: 34
2691 23:45:06.671919 [Byte1]: 34
2692 23:45:06.676626
2693 23:45:06.676709 Set Vref, RX VrefLevel [Byte0]: 35
2694 23:45:06.679996 [Byte1]: 35
2695 23:45:06.685192
2696 23:45:06.685318 Set Vref, RX VrefLevel [Byte0]: 36
2697 23:45:06.687937 [Byte1]: 36
2698 23:45:06.692990
2699 23:45:06.693112 Set Vref, RX VrefLevel [Byte0]: 37
2700 23:45:06.696029 [Byte1]: 37
2701 23:45:06.700731
2702 23:45:06.700861 Set Vref, RX VrefLevel [Byte0]: 38
2703 23:45:06.704461 [Byte1]: 38
2704 23:45:06.708856
2705 23:45:06.708980 Set Vref, RX VrefLevel [Byte0]: 39
2706 23:45:06.711844 [Byte1]: 39
2707 23:45:06.716844
2708 23:45:06.716971 Set Vref, RX VrefLevel [Byte0]: 40
2709 23:45:06.720254 [Byte1]: 40
2710 23:45:06.725107
2711 23:45:06.725235 Set Vref, RX VrefLevel [Byte0]: 41
2712 23:45:06.727880 [Byte1]: 41
2713 23:45:06.732987
2714 23:45:06.733112 Set Vref, RX VrefLevel [Byte0]: 42
2715 23:45:06.735820 [Byte1]: 42
2716 23:45:06.740728
2717 23:45:06.740851 Set Vref, RX VrefLevel [Byte0]: 43
2718 23:45:06.744089 [Byte1]: 43
2719 23:45:06.748875
2720 23:45:06.748997 Set Vref, RX VrefLevel [Byte0]: 44
2721 23:45:06.751941 [Byte1]: 44
2722 23:45:06.756854
2723 23:45:06.756983 Set Vref, RX VrefLevel [Byte0]: 45
2724 23:45:06.760371 [Byte1]: 45
2725 23:45:06.765020
2726 23:45:06.765147 Set Vref, RX VrefLevel [Byte0]: 46
2727 23:45:06.767951 [Byte1]: 46
2728 23:45:06.773112
2729 23:45:06.773231 Set Vref, RX VrefLevel [Byte0]: 47
2730 23:45:06.775941 [Byte1]: 47
2731 23:45:06.780838
2732 23:45:06.780922 Set Vref, RX VrefLevel [Byte0]: 48
2733 23:45:06.784079 [Byte1]: 48
2734 23:45:06.788637
2735 23:45:06.788710 Set Vref, RX VrefLevel [Byte0]: 49
2736 23:45:06.791816 [Byte1]: 49
2737 23:45:06.796994
2738 23:45:06.797104 Set Vref, RX VrefLevel [Byte0]: 50
2739 23:45:06.800146 [Byte1]: 50
2740 23:45:06.804964
2741 23:45:06.805054 Set Vref, RX VrefLevel [Byte0]: 51
2742 23:45:06.808235 [Byte1]: 51
2743 23:45:06.812652
2744 23:45:06.812753 Set Vref, RX VrefLevel [Byte0]: 52
2745 23:45:06.816112 [Byte1]: 52
2746 23:45:06.820782
2747 23:45:06.820869 Set Vref, RX VrefLevel [Byte0]: 53
2748 23:45:06.824019 [Byte1]: 53
2749 23:45:06.828840
2750 23:45:06.828948 Set Vref, RX VrefLevel [Byte0]: 54
2751 23:45:06.832195 [Byte1]: 54
2752 23:45:06.836715
2753 23:45:06.836792 Set Vref, RX VrefLevel [Byte0]: 55
2754 23:45:06.840033 [Byte1]: 55
2755 23:45:06.844969
2756 23:45:06.845044 Set Vref, RX VrefLevel [Byte0]: 56
2757 23:45:06.848321 [Byte1]: 56
2758 23:45:06.852799
2759 23:45:06.852902 Set Vref, RX VrefLevel [Byte0]: 57
2760 23:45:06.856090 [Byte1]: 57
2761 23:45:06.860907
2762 23:45:06.860986 Set Vref, RX VrefLevel [Byte0]: 58
2763 23:45:06.863912 [Byte1]: 58
2764 23:45:06.868693
2765 23:45:06.868776 Set Vref, RX VrefLevel [Byte0]: 59
2766 23:45:06.872083 [Byte1]: 59
2767 23:45:06.877003
2768 23:45:06.877085 Set Vref, RX VrefLevel [Byte0]: 60
2769 23:45:06.879948 [Byte1]: 60
2770 23:45:06.884985
2771 23:45:06.885062 Set Vref, RX VrefLevel [Byte0]: 61
2772 23:45:06.888264 [Byte1]: 61
2773 23:45:06.892765
2774 23:45:06.892844 Set Vref, RX VrefLevel [Byte0]: 62
2775 23:45:06.896048 [Byte1]: 62
2776 23:45:06.901099
2777 23:45:06.901198 Set Vref, RX VrefLevel [Byte0]: 63
2778 23:45:06.904297 [Byte1]: 63
2779 23:45:06.909152
2780 23:45:06.909232 Set Vref, RX VrefLevel [Byte0]: 64
2781 23:45:06.912102 [Byte1]: 64
2782 23:45:06.916986
2783 23:45:06.917064 Set Vref, RX VrefLevel [Byte0]: 65
2784 23:45:06.920340 [Byte1]: 65
2785 23:45:06.925306
2786 23:45:06.925380 Set Vref, RX VrefLevel [Byte0]: 66
2787 23:45:06.928374 [Byte1]: 66
2788 23:45:06.933100
2789 23:45:06.933177 Set Vref, RX VrefLevel [Byte0]: 67
2790 23:45:06.935859 [Byte1]: 67
2791 23:45:06.940606
2792 23:45:06.940684 Set Vref, RX VrefLevel [Byte0]: 68
2793 23:45:06.944214 [Byte1]: 68
2794 23:45:06.949059
2795 23:45:06.949141 Set Vref, RX VrefLevel [Byte0]: 69
2796 23:45:06.951814 [Byte1]: 69
2797 23:45:06.956867
2798 23:45:06.956941 Set Vref, RX VrefLevel [Byte0]: 70
2799 23:45:06.960349 [Byte1]: 70
2800 23:45:06.964625
2801 23:45:06.964701 Set Vref, RX VrefLevel [Byte0]: 71
2802 23:45:06.967934 [Byte1]: 71
2803 23:45:06.972989
2804 23:45:06.973072 Set Vref, RX VrefLevel [Byte0]: 72
2805 23:45:06.975960 [Byte1]: 72
2806 23:45:06.980945
2807 23:45:06.981040 Set Vref, RX VrefLevel [Byte0]: 73
2808 23:45:06.984371 [Byte1]: 73
2809 23:45:06.988900
2810 23:45:06.988988 Set Vref, RX VrefLevel [Byte0]: 74
2811 23:45:06.992026 [Byte1]: 74
2812 23:45:06.996912
2813 23:45:06.997042 Set Vref, RX VrefLevel [Byte0]: 75
2814 23:45:07.000247 [Byte1]: 75
2815 23:45:07.004692
2816 23:45:07.004778 Final RX Vref Byte 0 = 62 to rank0
2817 23:45:07.007996 Final RX Vref Byte 1 = 47 to rank0
2818 23:45:07.011680 Final RX Vref Byte 0 = 62 to rank1
2819 23:45:07.015034 Final RX Vref Byte 1 = 47 to rank1==
2820 23:45:07.018417 Dram Type= 6, Freq= 0, CH_0, rank 0
2821 23:45:07.025093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2822 23:45:07.025187 ==
2823 23:45:07.025281 DQS Delay:
2824 23:45:07.025339 DQS0 = 0, DQS1 = 0
2825 23:45:07.027919 DQM Delay:
2826 23:45:07.028013 DQM0 = 112, DQM1 = 98
2827 23:45:07.031763 DQ Delay:
2828 23:45:07.035090 DQ0 =112, DQ1 =112, DQ2 =110, DQ3 =108
2829 23:45:07.038313 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2830 23:45:07.041447 DQ8 =90, DQ9 =82, DQ10 =100, DQ11 =90
2831 23:45:07.044770 DQ12 =104, DQ13 =104, DQ14 =112, DQ15 =106
2832 23:45:07.044848
2833 23:45:07.044910
2834 23:45:07.051391 [DQSOSCAuto] RK0, (LSB)MR18= 0xfcfc, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 411 ps
2835 23:45:07.054829 CH0 RK0: MR19=303, MR18=FCFC
2836 23:45:07.061573 CH0_RK0: MR19=0x303, MR18=0xFCFC, DQSOSC=411, MR23=63, INC=38, DEC=25
2837 23:45:07.061660
2838 23:45:07.064885 ----->DramcWriteLeveling(PI) begin...
2839 23:45:07.064961 ==
2840 23:45:07.067830 Dram Type= 6, Freq= 0, CH_0, rank 1
2841 23:45:07.071596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2842 23:45:07.071713 ==
2843 23:45:07.074818 Write leveling (Byte 0): 32 => 32
2844 23:45:07.077917 Write leveling (Byte 1): 30 => 30
2845 23:45:07.081581 DramcWriteLeveling(PI) end<-----
2846 23:45:07.081689
2847 23:45:07.081790 ==
2848 23:45:07.084959 Dram Type= 6, Freq= 0, CH_0, rank 1
2849 23:45:07.091434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2850 23:45:07.091542 ==
2851 23:45:07.091623 [Gating] SW mode calibration
2852 23:45:07.101195 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2853 23:45:07.104555 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2854 23:45:07.108234 0 15 0 | B1->B0 | 2c2c 3434 | 1 1 | (0 0) (1 1)
2855 23:45:07.114727 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2856 23:45:07.118111 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2857 23:45:07.121534 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2858 23:45:07.128261 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2859 23:45:07.131624 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2860 23:45:07.134542 0 15 24 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
2861 23:45:07.141116 0 15 28 | B1->B0 | 3434 2626 | 1 0 | (1 1) (1 0)
2862 23:45:07.144476 1 0 0 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
2863 23:45:07.148287 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2864 23:45:07.154437 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2865 23:45:07.158074 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2866 23:45:07.161153 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2867 23:45:07.167955 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2868 23:45:07.171231 1 0 24 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
2869 23:45:07.174577 1 0 28 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
2870 23:45:07.181329 1 1 0 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
2871 23:45:07.184689 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2872 23:45:07.187917 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2873 23:45:07.194502 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2874 23:45:07.197697 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2875 23:45:07.201053 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2876 23:45:07.204499 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2877 23:45:07.211014 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2878 23:45:07.214492 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2879 23:45:07.217717 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 23:45:07.224906 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 23:45:07.227640 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 23:45:07.230919 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 23:45:07.237697 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 23:45:07.241007 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 23:45:07.244525 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 23:45:07.250967 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 23:45:07.254356 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 23:45:07.257600 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 23:45:07.264328 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 23:45:07.267718 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 23:45:07.271073 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 23:45:07.277828 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2893 23:45:07.280972 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2894 23:45:07.284264 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2895 23:45:07.287544 Total UI for P1: 0, mck2ui 16
2896 23:45:07.291126 best dqsien dly found for B0: ( 1, 3, 26)
2897 23:45:07.297567 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2898 23:45:07.297657 Total UI for P1: 0, mck2ui 16
2899 23:45:07.300946 best dqsien dly found for B1: ( 1, 4, 0)
2900 23:45:07.307916 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2901 23:45:07.310932 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2902 23:45:07.311034
2903 23:45:07.314121 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2904 23:45:07.317592 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2905 23:45:07.321085 [Gating] SW calibration Done
2906 23:45:07.321206 ==
2907 23:45:07.324738 Dram Type= 6, Freq= 0, CH_0, rank 1
2908 23:45:07.328003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2909 23:45:07.328133 ==
2910 23:45:07.328247 RX Vref Scan: 0
2911 23:45:07.328361
2912 23:45:07.331254 RX Vref 0 -> 0, step: 1
2913 23:45:07.331386
2914 23:45:07.334679 RX Delay -40 -> 252, step: 8
2915 23:45:07.338078 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2916 23:45:07.340986 iDelay=200, Bit 1, Center 111 (32 ~ 191) 160
2917 23:45:07.347530 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2918 23:45:07.351380 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2919 23:45:07.354037 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2920 23:45:07.357503 iDelay=200, Bit 5, Center 99 (32 ~ 167) 136
2921 23:45:07.360750 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2922 23:45:07.367342 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2923 23:45:07.371216 iDelay=200, Bit 8, Center 87 (16 ~ 159) 144
2924 23:45:07.374392 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2925 23:45:07.377855 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2926 23:45:07.381235 iDelay=200, Bit 11, Center 91 (16 ~ 167) 152
2927 23:45:07.384315 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2928 23:45:07.391016 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2929 23:45:07.393893 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2930 23:45:07.397311 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2931 23:45:07.397414 ==
2932 23:45:07.400792 Dram Type= 6, Freq= 0, CH_0, rank 1
2933 23:45:07.403910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2934 23:45:07.407280 ==
2935 23:45:07.407355 DQS Delay:
2936 23:45:07.407417 DQS0 = 0, DQS1 = 0
2937 23:45:07.410621 DQM Delay:
2938 23:45:07.410696 DQM0 = 112, DQM1 = 100
2939 23:45:07.413832 DQ Delay:
2940 23:45:07.417541 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2941 23:45:07.420502 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2942 23:45:07.423822 DQ8 =87, DQ9 =83, DQ10 =103, DQ11 =91
2943 23:45:07.427313 DQ12 =107, DQ13 =107, DQ14 =111, DQ15 =111
2944 23:45:07.427389
2945 23:45:07.427455
2946 23:45:07.427516 ==
2947 23:45:07.430702 Dram Type= 6, Freq= 0, CH_0, rank 1
2948 23:45:07.433996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2949 23:45:07.434123 ==
2950 23:45:07.434244
2951 23:45:07.434355
2952 23:45:07.437507 TX Vref Scan disable
2953 23:45:07.440730 == TX Byte 0 ==
2954 23:45:07.444036 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2955 23:45:07.447625 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2956 23:45:07.450757 == TX Byte 1 ==
2957 23:45:07.453967 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2958 23:45:07.457460 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2959 23:45:07.457537 ==
2960 23:45:07.460752 Dram Type= 6, Freq= 0, CH_0, rank 1
2961 23:45:07.467337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2962 23:45:07.467440 ==
2963 23:45:07.477632 TX Vref=22, minBit 1, minWin=25, winSum=426
2964 23:45:07.481055 TX Vref=24, minBit 5, minWin=26, winSum=431
2965 23:45:07.484356 TX Vref=26, minBit 1, minWin=26, winSum=435
2966 23:45:07.487729 TX Vref=28, minBit 1, minWin=27, winSum=440
2967 23:45:07.491196 TX Vref=30, minBit 1, minWin=27, winSum=444
2968 23:45:07.494318 TX Vref=32, minBit 10, minWin=26, winSum=439
2969 23:45:07.501090 [TxChooseVref] Worse bit 1, Min win 27, Win sum 444, Final Vref 30
2970 23:45:07.501195
2971 23:45:07.504169 Final TX Range 1 Vref 30
2972 23:45:07.504301
2973 23:45:07.504409 ==
2974 23:45:07.507830 Dram Type= 6, Freq= 0, CH_0, rank 1
2975 23:45:07.511068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2976 23:45:07.511190 ==
2977 23:45:07.511287
2978 23:45:07.514201
2979 23:45:07.514282 TX Vref Scan disable
2980 23:45:07.517526 == TX Byte 0 ==
2981 23:45:07.520907 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2982 23:45:07.524247 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2983 23:45:07.527468 == TX Byte 1 ==
2984 23:45:07.530936 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2985 23:45:07.534223 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2986 23:45:07.534336
2987 23:45:07.537657 [DATLAT]
2988 23:45:07.537767 Freq=1200, CH0 RK1
2989 23:45:07.537866
2990 23:45:07.540968 DATLAT Default: 0xd
2991 23:45:07.541083 0, 0xFFFF, sum = 0
2992 23:45:07.544539 1, 0xFFFF, sum = 0
2993 23:45:07.544661 2, 0xFFFF, sum = 0
2994 23:45:07.547463 3, 0xFFFF, sum = 0
2995 23:45:07.547577 4, 0xFFFF, sum = 0
2996 23:45:07.551221 5, 0xFFFF, sum = 0
2997 23:45:07.551337 6, 0xFFFF, sum = 0
2998 23:45:07.554558 7, 0xFFFF, sum = 0
2999 23:45:07.554670 8, 0xFFFF, sum = 0
3000 23:45:07.557892 9, 0xFFFF, sum = 0
3001 23:45:07.561144 10, 0xFFFF, sum = 0
3002 23:45:07.561258 11, 0xFFFF, sum = 0
3003 23:45:07.564491 12, 0x0, sum = 1
3004 23:45:07.564614 13, 0x0, sum = 2
3005 23:45:07.564718 14, 0x0, sum = 3
3006 23:45:07.567743 15, 0x0, sum = 4
3007 23:45:07.567858 best_step = 13
3008 23:45:07.567954
3009 23:45:07.571140 ==
3010 23:45:07.571246 Dram Type= 6, Freq= 0, CH_0, rank 1
3011 23:45:07.577982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3012 23:45:07.578101 ==
3013 23:45:07.578197 RX Vref Scan: 0
3014 23:45:07.578291
3015 23:45:07.580995 RX Vref 0 -> 0, step: 1
3016 23:45:07.581107
3017 23:45:07.584256 RX Delay -37 -> 252, step: 4
3018 23:45:07.587660 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3019 23:45:07.594436 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3020 23:45:07.597678 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3021 23:45:07.600909 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3022 23:45:07.604093 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3023 23:45:07.607391 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3024 23:45:07.614458 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3025 23:45:07.617255 iDelay=195, Bit 7, Center 120 (47 ~ 194) 148
3026 23:45:07.620571 iDelay=195, Bit 8, Center 88 (19 ~ 158) 140
3027 23:45:07.623913 iDelay=195, Bit 9, Center 80 (11 ~ 150) 140
3028 23:45:07.627603 iDelay=195, Bit 10, Center 100 (31 ~ 170) 140
3029 23:45:07.630963 iDelay=195, Bit 11, Center 90 (23 ~ 158) 136
3030 23:45:07.637565 iDelay=195, Bit 12, Center 108 (39 ~ 178) 140
3031 23:45:07.640989 iDelay=195, Bit 13, Center 106 (35 ~ 178) 144
3032 23:45:07.644122 iDelay=195, Bit 14, Center 112 (47 ~ 178) 132
3033 23:45:07.647542 iDelay=195, Bit 15, Center 108 (39 ~ 178) 140
3034 23:45:07.647655 ==
3035 23:45:07.650827 Dram Type= 6, Freq= 0, CH_0, rank 1
3036 23:45:07.657359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3037 23:45:07.657444 ==
3038 23:45:07.657509 DQS Delay:
3039 23:45:07.657578 DQS0 = 0, DQS1 = 0
3040 23:45:07.660916 DQM Delay:
3041 23:45:07.661048 DQM0 = 111, DQM1 = 99
3042 23:45:07.664120 DQ Delay:
3043 23:45:07.667476 DQ0 =108, DQ1 =112, DQ2 =110, DQ3 =108
3044 23:45:07.670814 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =120
3045 23:45:07.674063 DQ8 =88, DQ9 =80, DQ10 =100, DQ11 =90
3046 23:45:07.677371 DQ12 =108, DQ13 =106, DQ14 =112, DQ15 =108
3047 23:45:07.677499
3048 23:45:07.677607
3049 23:45:07.683965 [DQSOSCAuto] RK1, (LSB)MR18= 0x13fb, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 402 ps
3050 23:45:07.687624 CH0 RK1: MR19=403, MR18=13FB
3051 23:45:07.694311 CH0_RK1: MR19=0x403, MR18=0x13FB, DQSOSC=402, MR23=63, INC=40, DEC=27
3052 23:45:07.697234 [RxdqsGatingPostProcess] freq 1200
3053 23:45:07.703853 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3054 23:45:07.707110 best DQS0 dly(2T, 0.5T) = (0, 11)
3055 23:45:07.710684 best DQS1 dly(2T, 0.5T) = (0, 12)
3056 23:45:07.714018 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3057 23:45:07.714100 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3058 23:45:07.717414 best DQS0 dly(2T, 0.5T) = (0, 11)
3059 23:45:07.720897 best DQS1 dly(2T, 0.5T) = (0, 12)
3060 23:45:07.723690 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3061 23:45:07.727413 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3062 23:45:07.730447 Pre-setting of DQS Precalculation
3063 23:45:07.737444 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3064 23:45:07.737527 ==
3065 23:45:07.740728 Dram Type= 6, Freq= 0, CH_1, rank 0
3066 23:45:07.743522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3067 23:45:07.743595 ==
3068 23:45:07.750180 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3069 23:45:07.753580 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3070 23:45:07.763365 [CA 0] Center 37 (7~67) winsize 61
3071 23:45:07.767187 [CA 1] Center 37 (7~68) winsize 62
3072 23:45:07.770382 [CA 2] Center 34 (4~64) winsize 61
3073 23:45:07.773271 [CA 3] Center 34 (4~64) winsize 61
3074 23:45:07.776691 [CA 4] Center 34 (4~64) winsize 61
3075 23:45:07.780048 [CA 5] Center 33 (3~63) winsize 61
3076 23:45:07.780124
3077 23:45:07.783343 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3078 23:45:07.783413
3079 23:45:07.786729 [CATrainingPosCal] consider 1 rank data
3080 23:45:07.789966 u2DelayCellTimex100 = 270/100 ps
3081 23:45:07.793328 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3082 23:45:07.800133 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3083 23:45:07.803530 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3084 23:45:07.806812 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3085 23:45:07.810039 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3086 23:45:07.813337 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3087 23:45:07.813409
3088 23:45:07.816966 CA PerBit enable=1, Macro0, CA PI delay=33
3089 23:45:07.817046
3090 23:45:07.820150 [CBTSetCACLKResult] CA Dly = 33
3091 23:45:07.820231 CS Dly: 6 (0~37)
3092 23:45:07.823467 ==
3093 23:45:07.823537 Dram Type= 6, Freq= 0, CH_1, rank 1
3094 23:45:07.830311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3095 23:45:07.830424 ==
3096 23:45:07.833589 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3097 23:45:07.839836 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3098 23:45:07.848826 [CA 0] Center 37 (7~67) winsize 61
3099 23:45:07.852523 [CA 1] Center 37 (7~68) winsize 62
3100 23:45:07.855845 [CA 2] Center 34 (4~65) winsize 62
3101 23:45:07.859362 [CA 3] Center 33 (3~64) winsize 62
3102 23:45:07.862608 [CA 4] Center 34 (4~65) winsize 62
3103 23:45:07.865572 [CA 5] Center 33 (3~63) winsize 61
3104 23:45:07.865677
3105 23:45:07.868894 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3106 23:45:07.868997
3107 23:45:07.872569 [CATrainingPosCal] consider 2 rank data
3108 23:45:07.875883 u2DelayCellTimex100 = 270/100 ps
3109 23:45:07.879236 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3110 23:45:07.882258 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3111 23:45:07.889359 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3112 23:45:07.892585 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3113 23:45:07.895893 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3114 23:45:07.899209 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3115 23:45:07.899287
3116 23:45:07.902554 CA PerBit enable=1, Macro0, CA PI delay=33
3117 23:45:07.902630
3118 23:45:07.905946 [CBTSetCACLKResult] CA Dly = 33
3119 23:45:07.906015 CS Dly: 7 (0~39)
3120 23:45:07.906082
3121 23:45:07.909272 ----->DramcWriteLeveling(PI) begin...
3122 23:45:07.912141 ==
3123 23:45:07.912212 Dram Type= 6, Freq= 0, CH_1, rank 0
3124 23:45:07.918896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3125 23:45:07.918981 ==
3126 23:45:07.922229 Write leveling (Byte 0): 25 => 25
3127 23:45:07.925740 Write leveling (Byte 1): 29 => 29
3128 23:45:07.929048 DramcWriteLeveling(PI) end<-----
3129 23:45:07.929127
3130 23:45:07.929191 ==
3131 23:45:07.932440 Dram Type= 6, Freq= 0, CH_1, rank 0
3132 23:45:07.935969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3133 23:45:07.936071 ==
3134 23:45:07.939240 [Gating] SW mode calibration
3135 23:45:07.945813 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3136 23:45:07.949066 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3137 23:45:07.955912 0 15 0 | B1->B0 | 3030 2f2e | 1 1 | (1 1) (0 0)
3138 23:45:07.959060 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3139 23:45:07.962512 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3140 23:45:07.969260 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3141 23:45:07.972364 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3142 23:45:07.975596 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3143 23:45:07.982337 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3144 23:45:07.986249 0 15 28 | B1->B0 | 2626 2d2d | 1 1 | (1 1) (1 0)
3145 23:45:07.989378 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3146 23:45:07.995636 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3147 23:45:07.999191 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3148 23:45:08.002433 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3149 23:45:08.009250 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3150 23:45:08.012642 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3151 23:45:08.015425 1 0 24 | B1->B0 | 2626 2424 | 0 0 | (0 0) (0 0)
3152 23:45:08.022741 1 0 28 | B1->B0 | 3f3f 3f3f | 0 0 | (0 0) (0 0)
3153 23:45:08.025415 1 1 0 | B1->B0 | 4646 4444 | 0 1 | (0 0) (0 0)
3154 23:45:08.029189 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3155 23:45:08.035644 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3156 23:45:08.038994 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3157 23:45:08.042021 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3158 23:45:08.045844 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3159 23:45:08.052514 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3160 23:45:08.055819 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3161 23:45:08.058963 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3162 23:45:08.065826 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 23:45:08.068688 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 23:45:08.072260 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 23:45:08.078858 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 23:45:08.082415 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 23:45:08.085646 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 23:45:08.092281 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 23:45:08.095434 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 23:45:08.099227 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 23:45:08.105650 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 23:45:08.109051 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 23:45:08.112395 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 23:45:08.118995 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 23:45:08.122249 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 23:45:08.125654 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3177 23:45:08.132339 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3178 23:45:08.132461 Total UI for P1: 0, mck2ui 16
3179 23:45:08.135468 best dqsien dly found for B1: ( 1, 3, 28)
3180 23:45:08.142532 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3181 23:45:08.145322 Total UI for P1: 0, mck2ui 16
3182 23:45:08.148787 best dqsien dly found for B0: ( 1, 3, 30)
3183 23:45:08.152088 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3184 23:45:08.155497 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3185 23:45:08.155604
3186 23:45:08.158876 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3187 23:45:08.162089 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3188 23:45:08.165337 [Gating] SW calibration Done
3189 23:45:08.165448 ==
3190 23:45:08.168870 Dram Type= 6, Freq= 0, CH_1, rank 0
3191 23:45:08.172157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3192 23:45:08.172269 ==
3193 23:45:08.175479 RX Vref Scan: 0
3194 23:45:08.175563
3195 23:45:08.178637 RX Vref 0 -> 0, step: 1
3196 23:45:08.178715
3197 23:45:08.178780 RX Delay -40 -> 252, step: 8
3198 23:45:08.185572 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3199 23:45:08.188948 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3200 23:45:08.192230 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3201 23:45:08.195384 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3202 23:45:08.198790 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3203 23:45:08.205261 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3204 23:45:08.208703 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3205 23:45:08.212320 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3206 23:45:08.215706 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3207 23:45:08.218879 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3208 23:45:08.222241 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3209 23:45:08.228863 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3210 23:45:08.232127 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3211 23:45:08.235511 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3212 23:45:08.238740 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3213 23:45:08.245371 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3214 23:45:08.245462 ==
3215 23:45:08.248514 Dram Type= 6, Freq= 0, CH_1, rank 0
3216 23:45:08.251863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3217 23:45:08.251938 ==
3218 23:45:08.252026 DQS Delay:
3219 23:45:08.255217 DQS0 = 0, DQS1 = 0
3220 23:45:08.255325 DQM Delay:
3221 23:45:08.258538 DQM0 = 114, DQM1 = 105
3222 23:45:08.258638 DQ Delay:
3223 23:45:08.261809 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3224 23:45:08.265247 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3225 23:45:08.268619 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =103
3226 23:45:08.272010 DQ12 =115, DQ13 =111, DQ14 =111, DQ15 =111
3227 23:45:08.272118
3228 23:45:08.272208
3229 23:45:08.275119 ==
3230 23:45:08.275206 Dram Type= 6, Freq= 0, CH_1, rank 0
3231 23:45:08.281589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3232 23:45:08.281697 ==
3233 23:45:08.281805
3234 23:45:08.281896
3235 23:45:08.284856 TX Vref Scan disable
3236 23:45:08.284928 == TX Byte 0 ==
3237 23:45:08.288242 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3238 23:45:08.295138 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3239 23:45:08.295229 == TX Byte 1 ==
3240 23:45:08.298155 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3241 23:45:08.305010 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3242 23:45:08.305098 ==
3243 23:45:08.308056 Dram Type= 6, Freq= 0, CH_1, rank 0
3244 23:45:08.311697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3245 23:45:08.311785 ==
3246 23:45:08.323725 TX Vref=22, minBit 11, minWin=24, winSum=410
3247 23:45:08.326979 TX Vref=24, minBit 8, minWin=24, winSum=414
3248 23:45:08.330151 TX Vref=26, minBit 8, minWin=25, winSum=424
3249 23:45:08.333398 TX Vref=28, minBit 9, minWin=25, winSum=427
3250 23:45:08.336630 TX Vref=30, minBit 9, minWin=25, winSum=426
3251 23:45:08.343974 TX Vref=32, minBit 1, minWin=26, winSum=426
3252 23:45:08.347100 [TxChooseVref] Worse bit 1, Min win 26, Win sum 426, Final Vref 32
3253 23:45:08.347183
3254 23:45:08.350198 Final TX Range 1 Vref 32
3255 23:45:08.350277
3256 23:45:08.350346 ==
3257 23:45:08.353510 Dram Type= 6, Freq= 0, CH_1, rank 0
3258 23:45:08.356863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3259 23:45:08.356943 ==
3260 23:45:08.360108
3261 23:45:08.360190
3262 23:45:08.360252 TX Vref Scan disable
3263 23:45:08.363476 == TX Byte 0 ==
3264 23:45:08.367022 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3265 23:45:08.373639 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3266 23:45:08.373752 == TX Byte 1 ==
3267 23:45:08.376950 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3268 23:45:08.383713 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3269 23:45:08.383801
3270 23:45:08.383888 [DATLAT]
3271 23:45:08.383969 Freq=1200, CH1 RK0
3272 23:45:08.384049
3273 23:45:08.386652 DATLAT Default: 0xd
3274 23:45:08.386740 0, 0xFFFF, sum = 0
3275 23:45:08.390089 1, 0xFFFF, sum = 0
3276 23:45:08.390176 2, 0xFFFF, sum = 0
3277 23:45:08.393435 3, 0xFFFF, sum = 0
3278 23:45:08.396745 4, 0xFFFF, sum = 0
3279 23:45:08.396832 5, 0xFFFF, sum = 0
3280 23:45:08.399880 6, 0xFFFF, sum = 0
3281 23:45:08.399958 7, 0xFFFF, sum = 0
3282 23:45:08.403417 8, 0xFFFF, sum = 0
3283 23:45:08.403504 9, 0xFFFF, sum = 0
3284 23:45:08.406692 10, 0xFFFF, sum = 0
3285 23:45:08.406780 11, 0xFFFF, sum = 0
3286 23:45:08.410196 12, 0x0, sum = 1
3287 23:45:08.410284 13, 0x0, sum = 2
3288 23:45:08.413563 14, 0x0, sum = 3
3289 23:45:08.413650 15, 0x0, sum = 4
3290 23:45:08.413735 best_step = 13
3291 23:45:08.416904
3292 23:45:08.416989 ==
3293 23:45:08.420215 Dram Type= 6, Freq= 0, CH_1, rank 0
3294 23:45:08.423671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3295 23:45:08.423757 ==
3296 23:45:08.423821 RX Vref Scan: 1
3297 23:45:08.423881
3298 23:45:08.427106 Set Vref Range= 32 -> 127
3299 23:45:08.427188
3300 23:45:08.430388 RX Vref 32 -> 127, step: 1
3301 23:45:08.430472
3302 23:45:08.433641 RX Delay -21 -> 252, step: 4
3303 23:45:08.433725
3304 23:45:08.436710 Set Vref, RX VrefLevel [Byte0]: 32
3305 23:45:08.440088 [Byte1]: 32
3306 23:45:08.440172
3307 23:45:08.443359 Set Vref, RX VrefLevel [Byte0]: 33
3308 23:45:08.446912 [Byte1]: 33
3309 23:45:08.446994
3310 23:45:08.450243 Set Vref, RX VrefLevel [Byte0]: 34
3311 23:45:08.453336 [Byte1]: 34
3312 23:45:08.457648
3313 23:45:08.457771 Set Vref, RX VrefLevel [Byte0]: 35
3314 23:45:08.460868 [Byte1]: 35
3315 23:45:08.465956
3316 23:45:08.466081 Set Vref, RX VrefLevel [Byte0]: 36
3317 23:45:08.469363 [Byte1]: 36
3318 23:45:08.473874
3319 23:45:08.473995 Set Vref, RX VrefLevel [Byte0]: 37
3320 23:45:08.477238 [Byte1]: 37
3321 23:45:08.481685
3322 23:45:08.481805 Set Vref, RX VrefLevel [Byte0]: 38
3323 23:45:08.485043 [Byte1]: 38
3324 23:45:08.489342
3325 23:45:08.489419 Set Vref, RX VrefLevel [Byte0]: 39
3326 23:45:08.492919 [Byte1]: 39
3327 23:45:08.497179
3328 23:45:08.497261 Set Vref, RX VrefLevel [Byte0]: 40
3329 23:45:08.501035 [Byte1]: 40
3330 23:45:08.505481
3331 23:45:08.505564 Set Vref, RX VrefLevel [Byte0]: 41
3332 23:45:08.508736 [Byte1]: 41
3333 23:45:08.513322
3334 23:45:08.513406 Set Vref, RX VrefLevel [Byte0]: 42
3335 23:45:08.516401 [Byte1]: 42
3336 23:45:08.520980
3337 23:45:08.521064 Set Vref, RX VrefLevel [Byte0]: 43
3338 23:45:08.524324 [Byte1]: 43
3339 23:45:08.529114
3340 23:45:08.529200 Set Vref, RX VrefLevel [Byte0]: 44
3341 23:45:08.532458 [Byte1]: 44
3342 23:45:08.537024
3343 23:45:08.537107 Set Vref, RX VrefLevel [Byte0]: 45
3344 23:45:08.540406 [Byte1]: 45
3345 23:45:08.545066
3346 23:45:08.545148 Set Vref, RX VrefLevel [Byte0]: 46
3347 23:45:08.548528 [Byte1]: 46
3348 23:45:08.552956
3349 23:45:08.553038 Set Vref, RX VrefLevel [Byte0]: 47
3350 23:45:08.556098 [Byte1]: 47
3351 23:45:08.560828
3352 23:45:08.560954 Set Vref, RX VrefLevel [Byte0]: 48
3353 23:45:08.564047 [Byte1]: 48
3354 23:45:08.568904
3355 23:45:08.569031 Set Vref, RX VrefLevel [Byte0]: 49
3356 23:45:08.572088 [Byte1]: 49
3357 23:45:08.576645
3358 23:45:08.576775 Set Vref, RX VrefLevel [Byte0]: 50
3359 23:45:08.579974 [Byte1]: 50
3360 23:45:08.584467
3361 23:45:08.584595 Set Vref, RX VrefLevel [Byte0]: 51
3362 23:45:08.587875 [Byte1]: 51
3363 23:45:08.592288
3364 23:45:08.592412 Set Vref, RX VrefLevel [Byte0]: 52
3365 23:45:08.595701 [Byte1]: 52
3366 23:45:08.600400
3367 23:45:08.600521 Set Vref, RX VrefLevel [Byte0]: 53
3368 23:45:08.603988 [Byte1]: 53
3369 23:45:08.608441
3370 23:45:08.611195 Set Vref, RX VrefLevel [Byte0]: 54
3371 23:45:08.614584 [Byte1]: 54
3372 23:45:08.614705
3373 23:45:08.617824 Set Vref, RX VrefLevel [Byte0]: 55
3374 23:45:08.621396 [Byte1]: 55
3375 23:45:08.621514
3376 23:45:08.624984 Set Vref, RX VrefLevel [Byte0]: 56
3377 23:45:08.627842 [Byte1]: 56
3378 23:45:08.631991
3379 23:45:08.632116 Set Vref, RX VrefLevel [Byte0]: 57
3380 23:45:08.635288 [Byte1]: 57
3381 23:45:08.639747
3382 23:45:08.639841 Set Vref, RX VrefLevel [Byte0]: 58
3383 23:45:08.643068 [Byte1]: 58
3384 23:45:08.648008
3385 23:45:08.648131 Set Vref, RX VrefLevel [Byte0]: 59
3386 23:45:08.651335 [Byte1]: 59
3387 23:45:08.655760
3388 23:45:08.655886 Set Vref, RX VrefLevel [Byte0]: 60
3389 23:45:08.658968 [Byte1]: 60
3390 23:45:08.663934
3391 23:45:08.664061 Set Vref, RX VrefLevel [Byte0]: 61
3392 23:45:08.667231 [Byte1]: 61
3393 23:45:08.671366
3394 23:45:08.671491 Set Vref, RX VrefLevel [Byte0]: 62
3395 23:45:08.674987 [Byte1]: 62
3396 23:45:08.679507
3397 23:45:08.679635 Set Vref, RX VrefLevel [Byte0]: 63
3398 23:45:08.682807 [Byte1]: 63
3399 23:45:08.687276
3400 23:45:08.687403 Set Vref, RX VrefLevel [Byte0]: 64
3401 23:45:08.690638 [Byte1]: 64
3402 23:45:08.695200
3403 23:45:08.695324 Set Vref, RX VrefLevel [Byte0]: 65
3404 23:45:08.698455 [Byte1]: 65
3405 23:45:08.703382
3406 23:45:08.703506 Set Vref, RX VrefLevel [Byte0]: 66
3407 23:45:08.706565 [Byte1]: 66
3408 23:45:08.711100
3409 23:45:08.711206 Set Vref, RX VrefLevel [Byte0]: 67
3410 23:45:08.714575 [Byte1]: 67
3411 23:45:08.719330
3412 23:45:08.719406 Set Vref, RX VrefLevel [Byte0]: 68
3413 23:45:08.722577 [Byte1]: 68
3414 23:45:08.726944
3415 23:45:08.727016 Set Vref, RX VrefLevel [Byte0]: 69
3416 23:45:08.730519 [Byte1]: 69
3417 23:45:08.735300
3418 23:45:08.735376 Final RX Vref Byte 0 = 56 to rank0
3419 23:45:08.738575 Final RX Vref Byte 1 = 48 to rank0
3420 23:45:08.741863 Final RX Vref Byte 0 = 56 to rank1
3421 23:45:08.745138 Final RX Vref Byte 1 = 48 to rank1==
3422 23:45:08.748474 Dram Type= 6, Freq= 0, CH_1, rank 0
3423 23:45:08.754938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3424 23:45:08.755043 ==
3425 23:45:08.755149 DQS Delay:
3426 23:45:08.755239 DQS0 = 0, DQS1 = 0
3427 23:45:08.758403 DQM Delay:
3428 23:45:08.758523 DQM0 = 114, DQM1 = 105
3429 23:45:08.761566 DQ Delay:
3430 23:45:08.764997 DQ0 =118, DQ1 =108, DQ2 =106, DQ3 =112
3431 23:45:08.768147 DQ4 =110, DQ5 =122, DQ6 =124, DQ7 =112
3432 23:45:08.771832 DQ8 =94, DQ9 =98, DQ10 =104, DQ11 =102
3433 23:45:08.775283 DQ12 =112, DQ13 =110, DQ14 =114, DQ15 =110
3434 23:45:08.775394
3435 23:45:08.775501
3436 23:45:08.781622 [DQSOSCAuto] RK0, (LSB)MR18= 0xf0f7, (MSB)MR19= 0x303, tDQSOscB0 = 413 ps tDQSOscB1 = 416 ps
3437 23:45:08.784863 CH1 RK0: MR19=303, MR18=F0F7
3438 23:45:08.791528 CH1_RK0: MR19=0x303, MR18=0xF0F7, DQSOSC=413, MR23=63, INC=38, DEC=25
3439 23:45:08.791632
3440 23:45:08.794831 ----->DramcWriteLeveling(PI) begin...
3441 23:45:08.794947 ==
3442 23:45:08.798322 Dram Type= 6, Freq= 0, CH_1, rank 1
3443 23:45:08.801665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3444 23:45:08.804954 ==
3445 23:45:08.805052 Write leveling (Byte 0): 25 => 25
3446 23:45:08.808375 Write leveling (Byte 1): 27 => 27
3447 23:45:08.811645 DramcWriteLeveling(PI) end<-----
3448 23:45:08.811761
3449 23:45:08.811851 ==
3450 23:45:08.814896 Dram Type= 6, Freq= 0, CH_1, rank 1
3451 23:45:08.821434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3452 23:45:08.821564 ==
3453 23:45:08.821658 [Gating] SW mode calibration
3454 23:45:08.831598 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3455 23:45:08.835338 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3456 23:45:08.838389 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3457 23:45:08.845003 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3458 23:45:08.848247 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3459 23:45:08.851668 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3460 23:45:08.858501 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3461 23:45:08.861525 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3462 23:45:08.865173 0 15 24 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
3463 23:45:08.871593 0 15 28 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
3464 23:45:08.874830 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3465 23:45:08.878511 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3466 23:45:08.885052 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3467 23:45:08.888339 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3468 23:45:08.891803 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3469 23:45:08.898559 1 0 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3470 23:45:08.901694 1 0 24 | B1->B0 | 2d2d 4545 | 1 0 | (0 0) (0 0)
3471 23:45:08.905011 1 0 28 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
3472 23:45:08.911957 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3473 23:45:08.915210 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3474 23:45:08.918089 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3475 23:45:08.925089 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3476 23:45:08.927899 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3477 23:45:08.931671 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3478 23:45:08.937996 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3479 23:45:08.941170 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3480 23:45:08.944359 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 23:45:08.951227 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 23:45:08.954431 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 23:45:08.957728 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 23:45:08.964451 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 23:45:08.967604 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 23:45:08.970669 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 23:45:08.977728 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 23:45:08.980953 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 23:45:08.984226 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3490 23:45:08.990645 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 23:45:08.994314 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 23:45:08.997163 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 23:45:09.003717 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 23:45:09.007064 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3495 23:45:09.010563 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3496 23:45:09.014005 Total UI for P1: 0, mck2ui 16
3497 23:45:09.017110 best dqsien dly found for B0: ( 1, 3, 24)
3498 23:45:09.020585 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3499 23:45:09.024017 Total UI for P1: 0, mck2ui 16
3500 23:45:09.027214 best dqsien dly found for B1: ( 1, 3, 26)
3501 23:45:09.033631 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3502 23:45:09.036726 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3503 23:45:09.036836
3504 23:45:09.040019 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3505 23:45:09.043376 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3506 23:45:09.046674 [Gating] SW calibration Done
3507 23:45:09.046752 ==
3508 23:45:09.049912 Dram Type= 6, Freq= 0, CH_1, rank 1
3509 23:45:09.053147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3510 23:45:09.053225 ==
3511 23:45:09.056946 RX Vref Scan: 0
3512 23:45:09.057031
3513 23:45:09.057095 RX Vref 0 -> 0, step: 1
3514 23:45:09.057154
3515 23:45:09.060122 RX Delay -40 -> 252, step: 8
3516 23:45:09.062931 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3517 23:45:09.069633 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3518 23:45:09.072956 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3519 23:45:09.076598 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3520 23:45:09.079633 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3521 23:45:09.082954 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3522 23:45:09.089558 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3523 23:45:09.092860 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3524 23:45:09.096081 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3525 23:45:09.099677 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3526 23:45:09.102836 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3527 23:45:09.109110 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3528 23:45:09.112421 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3529 23:45:09.115876 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3530 23:45:09.119112 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3531 23:45:09.125857 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3532 23:45:09.125940 ==
3533 23:45:09.129154 Dram Type= 6, Freq= 0, CH_1, rank 1
3534 23:45:09.132417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3535 23:45:09.132524 ==
3536 23:45:09.132632 DQS Delay:
3537 23:45:09.135675 DQS0 = 0, DQS1 = 0
3538 23:45:09.135785 DQM Delay:
3539 23:45:09.138978 DQM0 = 110, DQM1 = 107
3540 23:45:09.139085 DQ Delay:
3541 23:45:09.142112 DQ0 =115, DQ1 =107, DQ2 =99, DQ3 =107
3542 23:45:09.145669 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =111
3543 23:45:09.149052 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =99
3544 23:45:09.152454 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =115
3545 23:45:09.152530
3546 23:45:09.152601
3547 23:45:09.152660 ==
3548 23:45:09.155457 Dram Type= 6, Freq= 0, CH_1, rank 1
3549 23:45:09.161931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3550 23:45:09.162014 ==
3551 23:45:09.162100
3552 23:45:09.162168
3553 23:45:09.162227 TX Vref Scan disable
3554 23:45:09.165794 == TX Byte 0 ==
3555 23:45:09.169234 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3556 23:45:09.175857 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3557 23:45:09.175956 == TX Byte 1 ==
3558 23:45:09.178882 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3559 23:45:09.185854 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3560 23:45:09.185939 ==
3561 23:45:09.188964 Dram Type= 6, Freq= 0, CH_1, rank 1
3562 23:45:09.192054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3563 23:45:09.192138 ==
3564 23:45:09.203719 TX Vref=22, minBit 9, minWin=25, winSum=417
3565 23:45:09.206813 TX Vref=24, minBit 9, minWin=25, winSum=425
3566 23:45:09.210417 TX Vref=26, minBit 8, minWin=26, winSum=429
3567 23:45:09.213277 TX Vref=28, minBit 1, minWin=26, winSum=434
3568 23:45:09.216608 TX Vref=30, minBit 9, minWin=26, winSum=434
3569 23:45:09.223253 TX Vref=32, minBit 8, minWin=26, winSum=430
3570 23:45:09.226578 [TxChooseVref] Worse bit 1, Min win 26, Win sum 434, Final Vref 28
3571 23:45:09.226698
3572 23:45:09.229819 Final TX Range 1 Vref 28
3573 23:45:09.229944
3574 23:45:09.230053 ==
3575 23:45:09.233482 Dram Type= 6, Freq= 0, CH_1, rank 1
3576 23:45:09.236487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3577 23:45:09.239761 ==
3578 23:45:09.239882
3579 23:45:09.239993
3580 23:45:09.240101 TX Vref Scan disable
3581 23:45:09.243380 == TX Byte 0 ==
3582 23:45:09.246656 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3583 23:45:09.253299 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3584 23:45:09.253386 == TX Byte 1 ==
3585 23:45:09.256659 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3586 23:45:09.263013 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3587 23:45:09.263141
3588 23:45:09.263254 [DATLAT]
3589 23:45:09.263362 Freq=1200, CH1 RK1
3590 23:45:09.263474
3591 23:45:09.266280 DATLAT Default: 0xd
3592 23:45:09.266403 0, 0xFFFF, sum = 0
3593 23:45:09.269702 1, 0xFFFF, sum = 0
3594 23:45:09.273127 2, 0xFFFF, sum = 0
3595 23:45:09.273252 3, 0xFFFF, sum = 0
3596 23:45:09.276443 4, 0xFFFF, sum = 0
3597 23:45:09.276578 5, 0xFFFF, sum = 0
3598 23:45:09.279654 6, 0xFFFF, sum = 0
3599 23:45:09.279781 7, 0xFFFF, sum = 0
3600 23:45:09.283329 8, 0xFFFF, sum = 0
3601 23:45:09.283457 9, 0xFFFF, sum = 0
3602 23:45:09.286608 10, 0xFFFF, sum = 0
3603 23:45:09.286731 11, 0xFFFF, sum = 0
3604 23:45:09.289856 12, 0x0, sum = 1
3605 23:45:09.289982 13, 0x0, sum = 2
3606 23:45:09.292959 14, 0x0, sum = 3
3607 23:45:09.293078 15, 0x0, sum = 4
3608 23:45:09.296459 best_step = 13
3609 23:45:09.296580
3610 23:45:09.296650 ==
3611 23:45:09.299785 Dram Type= 6, Freq= 0, CH_1, rank 1
3612 23:45:09.303139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3613 23:45:09.303266 ==
3614 23:45:09.303379 RX Vref Scan: 0
3615 23:45:09.306409
3616 23:45:09.306514 RX Vref 0 -> 0, step: 1
3617 23:45:09.306607
3618 23:45:09.309709 RX Delay -21 -> 252, step: 4
3619 23:45:09.315965 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3620 23:45:09.319660 iDelay=195, Bit 1, Center 110 (43 ~ 178) 136
3621 23:45:09.322976 iDelay=195, Bit 2, Center 100 (31 ~ 170) 140
3622 23:45:09.325904 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3623 23:45:09.329901 iDelay=195, Bit 4, Center 108 (39 ~ 178) 140
3624 23:45:09.332596 iDelay=195, Bit 5, Center 120 (47 ~ 194) 148
3625 23:45:09.339294 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3626 23:45:09.343029 iDelay=195, Bit 7, Center 108 (39 ~ 178) 140
3627 23:45:09.346594 iDelay=195, Bit 8, Center 94 (31 ~ 158) 128
3628 23:45:09.349457 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3629 23:45:09.352677 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3630 23:45:09.359141 iDelay=195, Bit 11, Center 100 (35 ~ 166) 132
3631 23:45:09.362832 iDelay=195, Bit 12, Center 118 (55 ~ 182) 128
3632 23:45:09.366091 iDelay=195, Bit 13, Center 116 (51 ~ 182) 132
3633 23:45:09.369208 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3634 23:45:09.375957 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3635 23:45:09.376065 ==
3636 23:45:09.379305 Dram Type= 6, Freq= 0, CH_1, rank 1
3637 23:45:09.382457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3638 23:45:09.382561 ==
3639 23:45:09.382657 DQS Delay:
3640 23:45:09.385975 DQS0 = 0, DQS1 = 0
3641 23:45:09.386079 DQM Delay:
3642 23:45:09.388994 DQM0 = 111, DQM1 = 109
3643 23:45:09.389097 DQ Delay:
3644 23:45:09.392342 DQ0 =114, DQ1 =110, DQ2 =100, DQ3 =108
3645 23:45:09.395558 DQ4 =108, DQ5 =120, DQ6 =122, DQ7 =108
3646 23:45:09.398923 DQ8 =94, DQ9 =100, DQ10 =110, DQ11 =100
3647 23:45:09.402355 DQ12 =118, DQ13 =116, DQ14 =118, DQ15 =116
3648 23:45:09.402460
3649 23:45:09.402550
3650 23:45:09.412232 [DQSOSCAuto] RK1, (LSB)MR18= 0xf707, (MSB)MR19= 0x304, tDQSOscB0 = 407 ps tDQSOscB1 = 413 ps
3651 23:45:09.416108 CH1 RK1: MR19=304, MR18=F707
3652 23:45:09.419511 CH1_RK1: MR19=0x304, MR18=0xF707, DQSOSC=407, MR23=63, INC=39, DEC=26
3653 23:45:09.422412 [RxdqsGatingPostProcess] freq 1200
3654 23:45:09.429323 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3655 23:45:09.432151 best DQS0 dly(2T, 0.5T) = (0, 11)
3656 23:45:09.435528 best DQS1 dly(2T, 0.5T) = (0, 11)
3657 23:45:09.438851 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3658 23:45:09.442322 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3659 23:45:09.445716 best DQS0 dly(2T, 0.5T) = (0, 11)
3660 23:45:09.448865 best DQS1 dly(2T, 0.5T) = (0, 11)
3661 23:45:09.452619 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3662 23:45:09.455357 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3663 23:45:09.458949 Pre-setting of DQS Precalculation
3664 23:45:09.462243 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3665 23:45:09.468761 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3666 23:45:09.475416 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3667 23:45:09.478910
3668 23:45:09.479032
3669 23:45:09.479133 [Calibration Summary] 2400 Mbps
3670 23:45:09.482214 CH 0, Rank 0
3671 23:45:09.482329 SW Impedance : PASS
3672 23:45:09.485602 DUTY Scan : NO K
3673 23:45:09.488871 ZQ Calibration : PASS
3674 23:45:09.488982 Jitter Meter : NO K
3675 23:45:09.491878 CBT Training : PASS
3676 23:45:09.495380 Write leveling : PASS
3677 23:45:09.495492 RX DQS gating : PASS
3678 23:45:09.498873 RX DQ/DQS(RDDQC) : PASS
3679 23:45:09.502192 TX DQ/DQS : PASS
3680 23:45:09.502300 RX DATLAT : PASS
3681 23:45:09.505611 RX DQ/DQS(Engine): PASS
3682 23:45:09.508801 TX OE : NO K
3683 23:45:09.508886 All Pass.
3684 23:45:09.508972
3685 23:45:09.509036 CH 0, Rank 1
3686 23:45:09.512250 SW Impedance : PASS
3687 23:45:09.515506 DUTY Scan : NO K
3688 23:45:09.515623 ZQ Calibration : PASS
3689 23:45:09.518330 Jitter Meter : NO K
3690 23:45:09.522281 CBT Training : PASS
3691 23:45:09.522383 Write leveling : PASS
3692 23:45:09.525080 RX DQS gating : PASS
3693 23:45:09.525154 RX DQ/DQS(RDDQC) : PASS
3694 23:45:09.528370 TX DQ/DQS : PASS
3695 23:45:09.531844 RX DATLAT : PASS
3696 23:45:09.531949 RX DQ/DQS(Engine): PASS
3697 23:45:09.534976 TX OE : NO K
3698 23:45:09.535080 All Pass.
3699 23:45:09.535146
3700 23:45:09.538270 CH 1, Rank 0
3701 23:45:09.538381 SW Impedance : PASS
3702 23:45:09.541670 DUTY Scan : NO K
3703 23:45:09.545124 ZQ Calibration : PASS
3704 23:45:09.545201 Jitter Meter : NO K
3705 23:45:09.548294 CBT Training : PASS
3706 23:45:09.551705 Write leveling : PASS
3707 23:45:09.551809 RX DQS gating : PASS
3708 23:45:09.555014 RX DQ/DQS(RDDQC) : PASS
3709 23:45:09.558402 TX DQ/DQS : PASS
3710 23:45:09.558488 RX DATLAT : PASS
3711 23:45:09.561758 RX DQ/DQS(Engine): PASS
3712 23:45:09.565120 TX OE : NO K
3713 23:45:09.565195 All Pass.
3714 23:45:09.565257
3715 23:45:09.565322 CH 1, Rank 1
3716 23:45:09.568482 SW Impedance : PASS
3717 23:45:09.571537 DUTY Scan : NO K
3718 23:45:09.571637 ZQ Calibration : PASS
3719 23:45:09.574628 Jitter Meter : NO K
3720 23:45:09.577928 CBT Training : PASS
3721 23:45:09.578032 Write leveling : PASS
3722 23:45:09.581572 RX DQS gating : PASS
3723 23:45:09.584513 RX DQ/DQS(RDDQC) : PASS
3724 23:45:09.584619 TX DQ/DQS : PASS
3725 23:45:09.588318 RX DATLAT : PASS
3726 23:45:09.588414 RX DQ/DQS(Engine): PASS
3727 23:45:09.591259 TX OE : NO K
3728 23:45:09.591379 All Pass.
3729 23:45:09.591485
3730 23:45:09.594641 DramC Write-DBI off
3731 23:45:09.597903 PER_BANK_REFRESH: Hybrid Mode
3732 23:45:09.597987 TX_TRACKING: ON
3733 23:45:09.608177 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3734 23:45:09.611467 [FAST_K] Save calibration result to emmc
3735 23:45:09.614589 dramc_set_vcore_voltage set vcore to 650000
3736 23:45:09.617800 Read voltage for 600, 5
3737 23:45:09.617884 Vio18 = 0
3738 23:45:09.621105 Vcore = 650000
3739 23:45:09.621188 Vdram = 0
3740 23:45:09.621253 Vddq = 0
3741 23:45:09.621313 Vmddr = 0
3742 23:45:09.627720 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3743 23:45:09.631162 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3744 23:45:09.634332 MEM_TYPE=3, freq_sel=19
3745 23:45:09.638050 sv_algorithm_assistance_LP4_1600
3746 23:45:09.641054 ============ PULL DRAM RESETB DOWN ============
3747 23:45:09.647675 ========== PULL DRAM RESETB DOWN end =========
3748 23:45:09.651042 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3749 23:45:09.654337 ===================================
3750 23:45:09.657712 LPDDR4 DRAM CONFIGURATION
3751 23:45:09.661051 ===================================
3752 23:45:09.661149 EX_ROW_EN[0] = 0x0
3753 23:45:09.664250 EX_ROW_EN[1] = 0x0
3754 23:45:09.664345 LP4Y_EN = 0x0
3755 23:45:09.667659 WORK_FSP = 0x0
3756 23:45:09.667731 WL = 0x2
3757 23:45:09.671136 RL = 0x2
3758 23:45:09.671217 BL = 0x2
3759 23:45:09.674352 RPST = 0x0
3760 23:45:09.677623 RD_PRE = 0x0
3761 23:45:09.677703 WR_PRE = 0x1
3762 23:45:09.680651 WR_PST = 0x0
3763 23:45:09.680727 DBI_WR = 0x0
3764 23:45:09.684018 DBI_RD = 0x0
3765 23:45:09.684101 OTF = 0x1
3766 23:45:09.687478 ===================================
3767 23:45:09.690944 ===================================
3768 23:45:09.694163 ANA top config
3769 23:45:09.697349 ===================================
3770 23:45:09.697435 DLL_ASYNC_EN = 0
3771 23:45:09.700620 ALL_SLAVE_EN = 1
3772 23:45:09.703925 NEW_RANK_MODE = 1
3773 23:45:09.707067 DLL_IDLE_MODE = 1
3774 23:45:09.707170 LP45_APHY_COMB_EN = 1
3775 23:45:09.710444 TX_ODT_DIS = 1
3776 23:45:09.714022 NEW_8X_MODE = 1
3777 23:45:09.716932 ===================================
3778 23:45:09.720083 ===================================
3779 23:45:09.723669 data_rate = 1200
3780 23:45:09.726819 CKR = 1
3781 23:45:09.730016 DQ_P2S_RATIO = 8
3782 23:45:09.733562 ===================================
3783 23:45:09.733670 CA_P2S_RATIO = 8
3784 23:45:09.736944 DQ_CA_OPEN = 0
3785 23:45:09.739978 DQ_SEMI_OPEN = 0
3786 23:45:09.743222 CA_SEMI_OPEN = 0
3787 23:45:09.746878 CA_FULL_RATE = 0
3788 23:45:09.749895 DQ_CKDIV4_EN = 1
3789 23:45:09.749979 CA_CKDIV4_EN = 1
3790 23:45:09.753113 CA_PREDIV_EN = 0
3791 23:45:09.756549 PH8_DLY = 0
3792 23:45:09.759872 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3793 23:45:09.763287 DQ_AAMCK_DIV = 4
3794 23:45:09.766637 CA_AAMCK_DIV = 4
3795 23:45:09.766723 CA_ADMCK_DIV = 4
3796 23:45:09.770016 DQ_TRACK_CA_EN = 0
3797 23:45:09.773449 CA_PICK = 600
3798 23:45:09.776231 CA_MCKIO = 600
3799 23:45:09.779593 MCKIO_SEMI = 0
3800 23:45:09.783282 PLL_FREQ = 2288
3801 23:45:09.786490 DQ_UI_PI_RATIO = 32
3802 23:45:09.786567 CA_UI_PI_RATIO = 0
3803 23:45:09.789775 ===================================
3804 23:45:09.793221 ===================================
3805 23:45:09.796455 memory_type:LPDDR4
3806 23:45:09.799856 GP_NUM : 10
3807 23:45:09.799932 SRAM_EN : 1
3808 23:45:09.803110 MD32_EN : 0
3809 23:45:09.806560 ===================================
3810 23:45:09.809860 [ANA_INIT] >>>>>>>>>>>>>>
3811 23:45:09.812635 <<<<<< [CONFIGURE PHASE]: ANA_TX
3812 23:45:09.816500 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3813 23:45:09.819305 ===================================
3814 23:45:09.819418 data_rate = 1200,PCW = 0X5800
3815 23:45:09.822657 ===================================
3816 23:45:09.830032 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3817 23:45:09.832928 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3818 23:45:09.839317 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3819 23:45:09.842677 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3820 23:45:09.845909 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3821 23:45:09.849097 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3822 23:45:09.858126 [ANA_INIT] flow start
3823 23:45:09.858321 [ANA_INIT] PLL >>>>>>>>
3824 23:45:09.858454 [ANA_INIT] PLL <<<<<<<<
3825 23:45:09.859281 [ANA_INIT] MIDPI >>>>>>>>
3826 23:45:09.862687 [ANA_INIT] MIDPI <<<<<<<<
3827 23:45:09.862847 [ANA_INIT] DLL >>>>>>>>
3828 23:45:09.865974 [ANA_INIT] flow end
3829 23:45:09.869437 ============ LP4 DIFF to SE enter ============
3830 23:45:09.876022 ============ LP4 DIFF to SE exit ============
3831 23:45:09.876224 [ANA_INIT] <<<<<<<<<<<<<
3832 23:45:09.878832 [Flow] Enable top DCM control >>>>>
3833 23:45:09.882198 [Flow] Enable top DCM control <<<<<
3834 23:45:09.885429 Enable DLL master slave shuffle
3835 23:45:09.891990 ==============================================================
3836 23:45:09.892144 Gating Mode config
3837 23:45:09.898468 ==============================================================
3838 23:45:09.901800 Config description:
3839 23:45:09.908530 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3840 23:45:09.918735 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3841 23:45:09.922117 SELPH_MODE 0: By rank 1: By Phase
3842 23:45:09.928238 ==============================================================
3843 23:45:09.931984 GAT_TRACK_EN = 1
3844 23:45:09.932118 RX_GATING_MODE = 2
3845 23:45:09.935140 RX_GATING_TRACK_MODE = 2
3846 23:45:09.946806 SELPH_MODE = 1
3847 23:45:09.946936 PICG_EARLY_EN = 1
3848 23:45:09.947015 VALID_LAT_VALUE = 1
3849 23:45:09.951370 ==============================================================
3850 23:45:09.955287 Enter into Gating configuration >>>>
3851 23:45:09.958342 Exit from Gating configuration <<<<
3852 23:45:09.961423 Enter into DVFS_PRE_config >>>>>
3853 23:45:09.971449 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3854 23:45:09.974873 Exit from DVFS_PRE_config <<<<<
3855 23:45:09.977962 Enter into PICG configuration >>>>
3856 23:45:09.981689 Exit from PICG configuration <<<<
3857 23:45:09.984516 [RX_INPUT] configuration >>>>>
3858 23:45:09.987823 [RX_INPUT] configuration <<<<<
3859 23:45:09.991187 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3860 23:45:09.998519 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3861 23:45:10.004750 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3862 23:45:10.011506 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3863 23:45:10.014747 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3864 23:45:10.021081 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3865 23:45:10.024306 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3866 23:45:10.030918 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3867 23:45:10.034101 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3868 23:45:10.037587 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3869 23:45:10.041139 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3870 23:45:10.047730 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3871 23:45:10.051083 ===================================
3872 23:45:10.054296 LPDDR4 DRAM CONFIGURATION
3873 23:45:10.057451 ===================================
3874 23:45:10.057585 EX_ROW_EN[0] = 0x0
3875 23:45:10.060904 EX_ROW_EN[1] = 0x0
3876 23:45:10.061001 LP4Y_EN = 0x0
3877 23:45:10.064335 WORK_FSP = 0x0
3878 23:45:10.064420 WL = 0x2
3879 23:45:10.067104 RL = 0x2
3880 23:45:10.067188 BL = 0x2
3881 23:45:10.070958 RPST = 0x0
3882 23:45:10.071043 RD_PRE = 0x0
3883 23:45:10.074174 WR_PRE = 0x1
3884 23:45:10.074258 WR_PST = 0x0
3885 23:45:10.077483 DBI_WR = 0x0
3886 23:45:10.077570 DBI_RD = 0x0
3887 23:45:10.080355 OTF = 0x1
3888 23:45:10.083992 ===================================
3889 23:45:10.087116 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3890 23:45:10.090409 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3891 23:45:10.097046 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3892 23:45:10.100424 ===================================
3893 23:45:10.100511 LPDDR4 DRAM CONFIGURATION
3894 23:45:10.103656 ===================================
3895 23:45:10.107251 EX_ROW_EN[0] = 0x10
3896 23:45:10.110682 EX_ROW_EN[1] = 0x0
3897 23:45:10.110769 LP4Y_EN = 0x0
3898 23:45:10.113880 WORK_FSP = 0x0
3899 23:45:10.113965 WL = 0x2
3900 23:45:10.116776 RL = 0x2
3901 23:45:10.116862 BL = 0x2
3902 23:45:10.120052 RPST = 0x0
3903 23:45:10.120136 RD_PRE = 0x0
3904 23:45:10.123979 WR_PRE = 0x1
3905 23:45:10.124063 WR_PST = 0x0
3906 23:45:10.126804 DBI_WR = 0x0
3907 23:45:10.126888 DBI_RD = 0x0
3908 23:45:10.130020 OTF = 0x1
3909 23:45:10.133291 ===================================
3910 23:45:10.140390 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3911 23:45:10.143568 nWR fixed to 30
3912 23:45:10.147090 [ModeRegInit_LP4] CH0 RK0
3913 23:45:10.147175 [ModeRegInit_LP4] CH0 RK1
3914 23:45:10.150025 [ModeRegInit_LP4] CH1 RK0
3915 23:45:10.153252 [ModeRegInit_LP4] CH1 RK1
3916 23:45:10.153381 match AC timing 17
3917 23:45:10.160269 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3918 23:45:10.163660 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3919 23:45:10.166876 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3920 23:45:10.173391 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3921 23:45:10.176749 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3922 23:45:10.176880 ==
3923 23:45:10.179531 Dram Type= 6, Freq= 0, CH_0, rank 0
3924 23:45:10.182864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3925 23:45:10.182990 ==
3926 23:45:10.190055 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3927 23:45:10.196207 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3928 23:45:10.199583 [CA 0] Center 37 (7~67) winsize 61
3929 23:45:10.203194 [CA 1] Center 36 (6~67) winsize 62
3930 23:45:10.206240 [CA 2] Center 35 (5~65) winsize 61
3931 23:45:10.209892 [CA 3] Center 35 (5~65) winsize 61
3932 23:45:10.213310 [CA 4] Center 34 (4~65) winsize 62
3933 23:45:10.216451 [CA 5] Center 34 (4~64) winsize 61
3934 23:45:10.216563
3935 23:45:10.219659 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3936 23:45:10.219783
3937 23:45:10.223406 [CATrainingPosCal] consider 1 rank data
3938 23:45:10.226494 u2DelayCellTimex100 = 270/100 ps
3939 23:45:10.229359 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3940 23:45:10.232608 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
3941 23:45:10.236075 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3942 23:45:10.239481 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3943 23:45:10.242743 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3944 23:45:10.249381 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3945 23:45:10.249466
3946 23:45:10.252508 CA PerBit enable=1, Macro0, CA PI delay=34
3947 23:45:10.252614
3948 23:45:10.256055 [CBTSetCACLKResult] CA Dly = 34
3949 23:45:10.256139 CS Dly: 4 (0~35)
3950 23:45:10.256204 ==
3951 23:45:10.259181 Dram Type= 6, Freq= 0, CH_0, rank 1
3952 23:45:10.262370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3953 23:45:10.266027 ==
3954 23:45:10.269319 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3955 23:45:10.275906 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3956 23:45:10.279313 [CA 0] Center 37 (7~67) winsize 61
3957 23:45:10.282636 [CA 1] Center 37 (7~67) winsize 61
3958 23:45:10.285874 [CA 2] Center 35 (5~65) winsize 61
3959 23:45:10.289148 [CA 3] Center 35 (5~65) winsize 61
3960 23:45:10.292449 [CA 4] Center 34 (4~65) winsize 62
3961 23:45:10.295846 [CA 5] Center 34 (3~65) winsize 63
3962 23:45:10.295923
3963 23:45:10.299278 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3964 23:45:10.299361
3965 23:45:10.302608 [CATrainingPosCal] consider 2 rank data
3966 23:45:10.305460 u2DelayCellTimex100 = 270/100 ps
3967 23:45:10.309112 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3968 23:45:10.312550 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
3969 23:45:10.315860 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3970 23:45:10.322408 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3971 23:45:10.325546 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3972 23:45:10.328658 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3973 23:45:10.328742
3974 23:45:10.332180 CA PerBit enable=1, Macro0, CA PI delay=34
3975 23:45:10.332258
3976 23:45:10.335403 [CBTSetCACLKResult] CA Dly = 34
3977 23:45:10.335511 CS Dly: 5 (0~37)
3978 23:45:10.335607
3979 23:45:10.338883 ----->DramcWriteLeveling(PI) begin...
3980 23:45:10.338958 ==
3981 23:45:10.342129 Dram Type= 6, Freq= 0, CH_0, rank 0
3982 23:45:10.348555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3983 23:45:10.348667 ==
3984 23:45:10.352219 Write leveling (Byte 0): 31 => 31
3985 23:45:10.355552 Write leveling (Byte 1): 30 => 30
3986 23:45:10.355637 DramcWriteLeveling(PI) end<-----
3987 23:45:10.358881
3988 23:45:10.358964 ==
3989 23:45:10.362330 Dram Type= 6, Freq= 0, CH_0, rank 0
3990 23:45:10.365299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3991 23:45:10.365399 ==
3992 23:45:10.368721 [Gating] SW mode calibration
3993 23:45:10.375295 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3994 23:45:10.378586 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3995 23:45:10.385310 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3996 23:45:10.388492 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3997 23:45:10.391768 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3998 23:45:10.398437 0 9 12 | B1->B0 | 3434 3131 | 0 0 | (0 0) (1 0)
3999 23:45:10.401948 0 9 16 | B1->B0 | 3030 2e2e | 0 0 | (0 0) (0 0)
4000 23:45:10.405145 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4001 23:45:10.411715 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4002 23:45:10.415130 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4003 23:45:10.418407 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4004 23:45:10.424679 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4005 23:45:10.428093 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4006 23:45:10.431401 0 10 12 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
4007 23:45:10.437984 0 10 16 | B1->B0 | 3636 3939 | 0 0 | (0 0) (1 1)
4008 23:45:10.441289 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4009 23:45:10.444669 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4010 23:45:10.451342 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4011 23:45:10.454908 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4012 23:45:10.458728 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4013 23:45:10.464999 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4014 23:45:10.467828 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4015 23:45:10.471250 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4016 23:45:10.477963 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 23:45:10.481312 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 23:45:10.484964 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 23:45:10.491469 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 23:45:10.494806 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 23:45:10.498153 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 23:45:10.504445 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 23:45:10.507727 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 23:45:10.511160 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 23:45:10.517732 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 23:45:10.521129 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 23:45:10.524449 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 23:45:10.530904 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 23:45:10.534337 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 23:45:10.537485 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 23:45:10.544053 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4032 23:45:10.547246 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4033 23:45:10.550557 Total UI for P1: 0, mck2ui 16
4034 23:45:10.553923 best dqsien dly found for B0: ( 0, 13, 16)
4035 23:45:10.557236 Total UI for P1: 0, mck2ui 16
4036 23:45:10.560703 best dqsien dly found for B1: ( 0, 13, 16)
4037 23:45:10.564048 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4038 23:45:10.567026 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4039 23:45:10.567114
4040 23:45:10.570777 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4041 23:45:10.573944 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4042 23:45:10.576901 [Gating] SW calibration Done
4043 23:45:10.577006 ==
4044 23:45:10.580700 Dram Type= 6, Freq= 0, CH_0, rank 0
4045 23:45:10.583969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4046 23:45:10.586978 ==
4047 23:45:10.587065 RX Vref Scan: 0
4048 23:45:10.587131
4049 23:45:10.590382 RX Vref 0 -> 0, step: 1
4050 23:45:10.590465
4051 23:45:10.593577 RX Delay -230 -> 252, step: 16
4052 23:45:10.596993 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4053 23:45:10.600171 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4054 23:45:10.603609 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4055 23:45:10.607026 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4056 23:45:10.613709 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4057 23:45:10.617037 iDelay=218, Bit 5, Center 17 (-150 ~ 185) 336
4058 23:45:10.620385 iDelay=218, Bit 6, Center 41 (-134 ~ 217) 352
4059 23:45:10.623784 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4060 23:45:10.630337 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4061 23:45:10.633550 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4062 23:45:10.636905 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4063 23:45:10.640354 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4064 23:45:10.646576 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4065 23:45:10.650266 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4066 23:45:10.653592 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4067 23:45:10.657028 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4068 23:45:10.657116 ==
4069 23:45:10.660399 Dram Type= 6, Freq= 0, CH_0, rank 0
4070 23:45:10.666839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4071 23:45:10.666925 ==
4072 23:45:10.666993 DQS Delay:
4073 23:45:10.670082 DQS0 = 0, DQS1 = 0
4074 23:45:10.670168 DQM Delay:
4075 23:45:10.670254 DQM0 = 34, DQM1 = 29
4076 23:45:10.673725 DQ Delay:
4077 23:45:10.677039 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4078 23:45:10.680333 DQ4 =33, DQ5 =17, DQ6 =41, DQ7 =49
4079 23:45:10.683762 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4080 23:45:10.686839 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4081 23:45:10.686925
4082 23:45:10.687011
4083 23:45:10.687092 ==
4084 23:45:10.690340 Dram Type= 6, Freq= 0, CH_0, rank 0
4085 23:45:10.693310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4086 23:45:10.693396 ==
4087 23:45:10.693481
4088 23:45:10.693563
4089 23:45:10.696996 TX Vref Scan disable
4090 23:45:10.697078 == TX Byte 0 ==
4091 23:45:10.703457 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4092 23:45:10.706476 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4093 23:45:10.706560 == TX Byte 1 ==
4094 23:45:10.713222 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4095 23:45:10.716472 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4096 23:45:10.716590 ==
4097 23:45:10.720065 Dram Type= 6, Freq= 0, CH_0, rank 0
4098 23:45:10.723410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4099 23:45:10.723491 ==
4100 23:45:10.726752
4101 23:45:10.726825
4102 23:45:10.726886 TX Vref Scan disable
4103 23:45:10.730157 == TX Byte 0 ==
4104 23:45:10.733524 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4105 23:45:10.739910 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4106 23:45:10.739997 == TX Byte 1 ==
4107 23:45:10.743204 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4108 23:45:10.749711 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4109 23:45:10.749796
4110 23:45:10.749861 [DATLAT]
4111 23:45:10.749922 Freq=600, CH0 RK0
4112 23:45:10.749982
4113 23:45:10.753003 DATLAT Default: 0x9
4114 23:45:10.753087 0, 0xFFFF, sum = 0
4115 23:45:10.756150 1, 0xFFFF, sum = 0
4116 23:45:10.759853 2, 0xFFFF, sum = 0
4117 23:45:10.759938 3, 0xFFFF, sum = 0
4118 23:45:10.763184 4, 0xFFFF, sum = 0
4119 23:45:10.763272 5, 0xFFFF, sum = 0
4120 23:45:10.766101 6, 0xFFFF, sum = 0
4121 23:45:10.766186 7, 0xFFFF, sum = 0
4122 23:45:10.769453 8, 0x0, sum = 1
4123 23:45:10.769538 9, 0x0, sum = 2
4124 23:45:10.769606 10, 0x0, sum = 3
4125 23:45:10.772739 11, 0x0, sum = 4
4126 23:45:10.772824 best_step = 9
4127 23:45:10.772889
4128 23:45:10.772949 ==
4129 23:45:10.776485 Dram Type= 6, Freq= 0, CH_0, rank 0
4130 23:45:10.782981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4131 23:45:10.783099 ==
4132 23:45:10.783194 RX Vref Scan: 1
4133 23:45:10.783294
4134 23:45:10.786291 RX Vref 0 -> 0, step: 1
4135 23:45:10.786374
4136 23:45:10.789657 RX Delay -195 -> 252, step: 8
4137 23:45:10.789740
4138 23:45:10.793078 Set Vref, RX VrefLevel [Byte0]: 62
4139 23:45:10.795960 [Byte1]: 47
4140 23:45:10.796042
4141 23:45:10.799548 Final RX Vref Byte 0 = 62 to rank0
4142 23:45:10.802407 Final RX Vref Byte 1 = 47 to rank0
4143 23:45:10.805703 Final RX Vref Byte 0 = 62 to rank1
4144 23:45:10.809397 Final RX Vref Byte 1 = 47 to rank1==
4145 23:45:10.812732 Dram Type= 6, Freq= 0, CH_0, rank 0
4146 23:45:10.815969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4147 23:45:10.816072 ==
4148 23:45:10.819207 DQS Delay:
4149 23:45:10.819307 DQS0 = 0, DQS1 = 0
4150 23:45:10.822534 DQM Delay:
4151 23:45:10.822635 DQM0 = 35, DQM1 = 29
4152 23:45:10.822734 DQ Delay:
4153 23:45:10.826104 DQ0 =36, DQ1 =36, DQ2 =32, DQ3 =32
4154 23:45:10.829515 DQ4 =36, DQ5 =24, DQ6 =40, DQ7 =48
4155 23:45:10.832313 DQ8 =20, DQ9 =16, DQ10 =32, DQ11 =24
4156 23:45:10.835825 DQ12 =32, DQ13 =32, DQ14 =40, DQ15 =36
4157 23:45:10.835904
4158 23:45:10.835967
4159 23:45:10.845775 [DQSOSCAuto] RK0, (LSB)MR18= 0x4443, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 396 ps
4160 23:45:10.849206 CH0 RK0: MR19=808, MR18=4443
4161 23:45:10.855749 CH0_RK0: MR19=0x808, MR18=0x4443, DQSOSC=396, MR23=63, INC=167, DEC=111
4162 23:45:10.855845
4163 23:45:10.859198 ----->DramcWriteLeveling(PI) begin...
4164 23:45:10.859286 ==
4165 23:45:10.862734 Dram Type= 6, Freq= 0, CH_0, rank 1
4166 23:45:10.865983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4167 23:45:10.866072 ==
4168 23:45:10.869168 Write leveling (Byte 0): 32 => 32
4169 23:45:10.872441 Write leveling (Byte 1): 30 => 30
4170 23:45:10.875869 DramcWriteLeveling(PI) end<-----
4171 23:45:10.875958
4172 23:45:10.876043 ==
4173 23:45:10.879243 Dram Type= 6, Freq= 0, CH_0, rank 1
4174 23:45:10.882445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4175 23:45:10.882532 ==
4176 23:45:10.885571 [Gating] SW mode calibration
4177 23:45:10.892184 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4178 23:45:10.899034 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4179 23:45:10.902317 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4180 23:45:10.905656 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4181 23:45:10.911911 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4182 23:45:10.915558 0 9 12 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)
4183 23:45:10.918842 0 9 16 | B1->B0 | 2f2f 2323 | 1 0 | (0 0) (0 0)
4184 23:45:10.924943 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4185 23:45:10.928715 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4186 23:45:10.931766 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4187 23:45:10.938609 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4188 23:45:10.941718 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4189 23:45:10.945181 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4190 23:45:10.951529 0 10 12 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
4191 23:45:10.955119 0 10 16 | B1->B0 | 3939 4444 | 0 0 | (1 1) (0 0)
4192 23:45:10.958200 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4193 23:45:10.965329 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4194 23:45:10.968527 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4195 23:45:10.971535 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4196 23:45:10.978311 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4197 23:45:10.981495 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4198 23:45:10.984880 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4199 23:45:10.991729 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 23:45:10.995112 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 23:45:10.998466 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 23:45:11.005190 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 23:45:11.008456 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 23:45:11.011985 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 23:45:11.018044 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 23:45:11.021211 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 23:45:11.024465 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 23:45:11.031226 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 23:45:11.034411 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 23:45:11.037898 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 23:45:11.044516 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 23:45:11.048112 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 23:45:11.051494 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 23:45:11.054781 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4215 23:45:11.057934 Total UI for P1: 0, mck2ui 16
4216 23:45:11.060996 best dqsien dly found for B0: ( 0, 13, 10)
4217 23:45:11.067759 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4218 23:45:11.070938 Total UI for P1: 0, mck2ui 16
4219 23:45:11.074481 best dqsien dly found for B1: ( 0, 13, 12)
4220 23:45:11.077788 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4221 23:45:11.080854 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4222 23:45:11.080985
4223 23:45:11.084142 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4224 23:45:11.087551 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4225 23:45:11.090935 [Gating] SW calibration Done
4226 23:45:11.091010 ==
4227 23:45:11.094368 Dram Type= 6, Freq= 0, CH_0, rank 1
4228 23:45:11.097383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4229 23:45:11.097468 ==
4230 23:45:11.101106 RX Vref Scan: 0
4231 23:45:11.101206
4232 23:45:11.104495 RX Vref 0 -> 0, step: 1
4233 23:45:11.104583
4234 23:45:11.104646 RX Delay -230 -> 252, step: 16
4235 23:45:11.111137 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4236 23:45:11.114074 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4237 23:45:11.117297 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4238 23:45:11.120612 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4239 23:45:11.127304 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4240 23:45:11.130593 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4241 23:45:11.133720 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4242 23:45:11.137189 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4243 23:45:11.143764 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4244 23:45:11.147116 iDelay=218, Bit 9, Center 9 (-150 ~ 169) 320
4245 23:45:11.150719 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4246 23:45:11.153715 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4247 23:45:11.157121 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4248 23:45:11.163754 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4249 23:45:11.167005 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4250 23:45:11.170349 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4251 23:45:11.170439 ==
4252 23:45:11.173592 Dram Type= 6, Freq= 0, CH_0, rank 1
4253 23:45:11.180305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4254 23:45:11.180401 ==
4255 23:45:11.180468 DQS Delay:
4256 23:45:11.180531 DQS0 = 0, DQS1 = 0
4257 23:45:11.183673 DQM Delay:
4258 23:45:11.183757 DQM0 = 36, DQM1 = 29
4259 23:45:11.187000 DQ Delay:
4260 23:45:11.189981 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4261 23:45:11.193562 DQ4 =33, DQ5 =25, DQ6 =49, DQ7 =49
4262 23:45:11.196798 DQ8 =25, DQ9 =9, DQ10 =33, DQ11 =25
4263 23:45:11.200185 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4264 23:45:11.200289
4265 23:45:11.200356
4266 23:45:11.200422 ==
4267 23:45:11.203435 Dram Type= 6, Freq= 0, CH_0, rank 1
4268 23:45:11.206512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4269 23:45:11.206600 ==
4270 23:45:11.206665
4271 23:45:11.206726
4272 23:45:11.209866 TX Vref Scan disable
4273 23:45:11.209953 == TX Byte 0 ==
4274 23:45:11.216518 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4275 23:45:11.219868 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4276 23:45:11.219957 == TX Byte 1 ==
4277 23:45:11.226457 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4278 23:45:11.229806 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4279 23:45:11.229893 ==
4280 23:45:11.233266 Dram Type= 6, Freq= 0, CH_0, rank 1
4281 23:45:11.236534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4282 23:45:11.236635 ==
4283 23:45:11.236702
4284 23:45:11.239862
4285 23:45:11.239945 TX Vref Scan disable
4286 23:45:11.243225 == TX Byte 0 ==
4287 23:45:11.246939 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4288 23:45:11.249950 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4289 23:45:11.253284 == TX Byte 1 ==
4290 23:45:11.256804 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4291 23:45:11.260334 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4292 23:45:11.263700
4293 23:45:11.263789 [DATLAT]
4294 23:45:11.263855 Freq=600, CH0 RK1
4295 23:45:11.263917
4296 23:45:11.266965 DATLAT Default: 0x9
4297 23:45:11.267051 0, 0xFFFF, sum = 0
4298 23:45:11.270277 1, 0xFFFF, sum = 0
4299 23:45:11.270412 2, 0xFFFF, sum = 0
4300 23:45:11.273596 3, 0xFFFF, sum = 0
4301 23:45:11.273718 4, 0xFFFF, sum = 0
4302 23:45:11.276735 5, 0xFFFF, sum = 0
4303 23:45:11.280145 6, 0xFFFF, sum = 0
4304 23:45:11.280235 7, 0xFFFF, sum = 0
4305 23:45:11.280302 8, 0x0, sum = 1
4306 23:45:11.283134 9, 0x0, sum = 2
4307 23:45:11.283220 10, 0x0, sum = 3
4308 23:45:11.286852 11, 0x0, sum = 4
4309 23:45:11.286939 best_step = 9
4310 23:45:11.287005
4311 23:45:11.287066 ==
4312 23:45:11.289768 Dram Type= 6, Freq= 0, CH_0, rank 1
4313 23:45:11.296542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4314 23:45:11.296637 ==
4315 23:45:11.296713 RX Vref Scan: 0
4316 23:45:11.296776
4317 23:45:11.300212 RX Vref 0 -> 0, step: 1
4318 23:45:11.300319
4319 23:45:11.303092 RX Delay -195 -> 252, step: 8
4320 23:45:11.306349 iDelay=205, Bit 0, Center 28 (-131 ~ 188) 320
4321 23:45:11.313174 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4322 23:45:11.316148 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4323 23:45:11.319948 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4324 23:45:11.322752 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4325 23:45:11.329405 iDelay=205, Bit 5, Center 20 (-139 ~ 180) 320
4326 23:45:11.332710 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4327 23:45:11.335988 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4328 23:45:11.339333 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4329 23:45:11.342680 iDelay=205, Bit 9, Center 12 (-139 ~ 164) 304
4330 23:45:11.349350 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4331 23:45:11.352716 iDelay=205, Bit 11, Center 16 (-139 ~ 172) 312
4332 23:45:11.356194 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4333 23:45:11.359328 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4334 23:45:11.365881 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4335 23:45:11.369231 iDelay=205, Bit 15, Center 32 (-123 ~ 188) 312
4336 23:45:11.369343 ==
4337 23:45:11.372318 Dram Type= 6, Freq= 0, CH_0, rank 1
4338 23:45:11.375982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4339 23:45:11.376070 ==
4340 23:45:11.378982 DQS Delay:
4341 23:45:11.379073 DQS0 = 0, DQS1 = 0
4342 23:45:11.382293 DQM Delay:
4343 23:45:11.382405 DQM0 = 32, DQM1 = 27
4344 23:45:11.382505 DQ Delay:
4345 23:45:11.385731 DQ0 =28, DQ1 =32, DQ2 =32, DQ3 =28
4346 23:45:11.388980 DQ4 =32, DQ5 =20, DQ6 =44, DQ7 =44
4347 23:45:11.392572 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =16
4348 23:45:11.395614 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =32
4349 23:45:11.395743
4350 23:45:11.395861
4351 23:45:11.405572 [DQSOSCAuto] RK1, (LSB)MR18= 0x6a38, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 389 ps
4352 23:45:11.408710 CH0 RK1: MR19=808, MR18=6A38
4353 23:45:11.415194 CH0_RK1: MR19=0x808, MR18=0x6A38, DQSOSC=389, MR23=63, INC=173, DEC=115
4354 23:45:11.415322 [RxdqsGatingPostProcess] freq 600
4355 23:45:11.422139 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4356 23:45:11.425178 Pre-setting of DQS Precalculation
4357 23:45:11.428602 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4358 23:45:11.432082 ==
4359 23:45:11.432200 Dram Type= 6, Freq= 0, CH_1, rank 0
4360 23:45:11.438596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4361 23:45:11.438713 ==
4362 23:45:11.442027 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4363 23:45:11.448725 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4364 23:45:11.452578 [CA 0] Center 36 (6~66) winsize 61
4365 23:45:11.455861 [CA 1] Center 35 (5~66) winsize 62
4366 23:45:11.459252 [CA 2] Center 34 (4~65) winsize 62
4367 23:45:11.462116 [CA 3] Center 34 (4~65) winsize 62
4368 23:45:11.465386 [CA 4] Center 34 (4~65) winsize 62
4369 23:45:11.469060 [CA 5] Center 33 (3~64) winsize 62
4370 23:45:11.469175
4371 23:45:11.472199 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4372 23:45:11.472310
4373 23:45:11.475306 [CATrainingPosCal] consider 1 rank data
4374 23:45:11.478743 u2DelayCellTimex100 = 270/100 ps
4375 23:45:11.481965 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4376 23:45:11.489046 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4377 23:45:11.492440 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4378 23:45:11.495746 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4379 23:45:11.498902 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4380 23:45:11.502073 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4381 23:45:11.502188
4382 23:45:11.505361 CA PerBit enable=1, Macro0, CA PI delay=33
4383 23:45:11.505475
4384 23:45:11.508633 [CBTSetCACLKResult] CA Dly = 33
4385 23:45:11.508746 CS Dly: 5 (0~36)
4386 23:45:11.511890 ==
4387 23:45:11.511998 Dram Type= 6, Freq= 0, CH_1, rank 1
4388 23:45:11.519086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4389 23:45:11.519204 ==
4390 23:45:11.521848 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4391 23:45:11.528474 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4392 23:45:11.532493 [CA 0] Center 36 (6~66) winsize 61
4393 23:45:11.535685 [CA 1] Center 36 (5~67) winsize 63
4394 23:45:11.538966 [CA 2] Center 34 (4~65) winsize 62
4395 23:45:11.542630 [CA 3] Center 34 (3~65) winsize 63
4396 23:45:11.545780 [CA 4] Center 34 (4~65) winsize 62
4397 23:45:11.548854 [CA 5] Center 33 (3~64) winsize 62
4398 23:45:11.548970
4399 23:45:11.552345 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4400 23:45:11.552456
4401 23:45:11.555469 [CATrainingPosCal] consider 2 rank data
4402 23:45:11.558816 u2DelayCellTimex100 = 270/100 ps
4403 23:45:11.562294 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4404 23:45:11.565725 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4405 23:45:11.572356 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4406 23:45:11.575619 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4407 23:45:11.579125 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4408 23:45:11.582455 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4409 23:45:11.582542
4410 23:45:11.585555 CA PerBit enable=1, Macro0, CA PI delay=33
4411 23:45:11.585639
4412 23:45:11.588835 [CBTSetCACLKResult] CA Dly = 33
4413 23:45:11.588912 CS Dly: 5 (0~36)
4414 23:45:11.588975
4415 23:45:11.592342 ----->DramcWriteLeveling(PI) begin...
4416 23:45:11.595798 ==
4417 23:45:11.598623 Dram Type= 6, Freq= 0, CH_1, rank 0
4418 23:45:11.602403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4419 23:45:11.602491 ==
4420 23:45:11.605510 Write leveling (Byte 0): 29 => 29
4421 23:45:11.608644 Write leveling (Byte 1): 33 => 33
4422 23:45:11.611958 DramcWriteLeveling(PI) end<-----
4423 23:45:11.612075
4424 23:45:11.612174 ==
4425 23:45:11.615193 Dram Type= 6, Freq= 0, CH_1, rank 0
4426 23:45:11.619045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4427 23:45:11.619162 ==
4428 23:45:11.621896 [Gating] SW mode calibration
4429 23:45:11.628581 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4430 23:45:11.635245 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4431 23:45:11.638773 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4432 23:45:11.642060 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4433 23:45:11.648418 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4434 23:45:11.652037 0 9 12 | B1->B0 | 3232 3333 | 0 0 | (0 0) (0 1)
4435 23:45:11.655056 0 9 16 | B1->B0 | 2828 2626 | 0 0 | (1 1) (1 1)
4436 23:45:11.661603 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4437 23:45:11.665148 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4438 23:45:11.668277 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4439 23:45:11.674851 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4440 23:45:11.678271 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4441 23:45:11.681655 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4442 23:45:11.688089 0 10 12 | B1->B0 | 2d2d 2d2c | 1 1 | (0 0) (1 1)
4443 23:45:11.691739 0 10 16 | B1->B0 | 4141 4242 | 0 0 | (0 0) (0 0)
4444 23:45:11.695259 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4445 23:45:11.698184 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4446 23:45:11.704608 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4447 23:45:11.707955 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4448 23:45:11.711179 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4449 23:45:11.717963 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4450 23:45:11.721607 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4451 23:45:11.724885 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4452 23:45:11.731427 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 23:45:11.734702 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 23:45:11.738162 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 23:45:11.744708 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 23:45:11.747963 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 23:45:11.751354 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 23:45:11.758009 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 23:45:11.761303 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 23:45:11.764566 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 23:45:11.770821 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 23:45:11.774322 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 23:45:11.777614 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 23:45:11.784244 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 23:45:11.787583 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 23:45:11.790897 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4467 23:45:11.797490 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4468 23:45:11.797627 Total UI for P1: 0, mck2ui 16
4469 23:45:11.804497 best dqsien dly found for B0: ( 0, 13, 12)
4470 23:45:11.804645 Total UI for P1: 0, mck2ui 16
4471 23:45:11.810921 best dqsien dly found for B1: ( 0, 13, 14)
4472 23:45:11.814151 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4473 23:45:11.817352 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4474 23:45:11.817439
4475 23:45:11.820768 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4476 23:45:11.824404 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4477 23:45:11.827327 [Gating] SW calibration Done
4478 23:45:11.827412 ==
4479 23:45:11.830959 Dram Type= 6, Freq= 0, CH_1, rank 0
4480 23:45:11.834151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4481 23:45:11.834240 ==
4482 23:45:11.837507 RX Vref Scan: 0
4483 23:45:11.837593
4484 23:45:11.837659 RX Vref 0 -> 0, step: 1
4485 23:45:11.837721
4486 23:45:11.840871 RX Delay -230 -> 252, step: 16
4487 23:45:11.847149 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4488 23:45:11.850714 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4489 23:45:11.853920 iDelay=218, Bit 2, Center 25 (-150 ~ 201) 352
4490 23:45:11.857091 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4491 23:45:11.860599 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4492 23:45:11.867248 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4493 23:45:11.870477 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4494 23:45:11.873727 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4495 23:45:11.877063 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4496 23:45:11.883660 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4497 23:45:11.887151 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4498 23:45:11.890389 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4499 23:45:11.893802 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4500 23:45:11.900420 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4501 23:45:11.903592 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4502 23:45:11.906893 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4503 23:45:11.907016 ==
4504 23:45:11.910103 Dram Type= 6, Freq= 0, CH_1, rank 0
4505 23:45:11.913339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4506 23:45:11.916459 ==
4507 23:45:11.916586 DQS Delay:
4508 23:45:11.916687 DQS0 = 0, DQS1 = 0
4509 23:45:11.920097 DQM Delay:
4510 23:45:11.920217 DQM0 = 38, DQM1 = 28
4511 23:45:11.923378 DQ Delay:
4512 23:45:11.923495 DQ0 =49, DQ1 =33, DQ2 =25, DQ3 =33
4513 23:45:11.926524 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4514 23:45:11.929935 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4515 23:45:11.933392 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4516 23:45:11.933504
4517 23:45:11.933600
4518 23:45:11.936740 ==
4519 23:45:11.940108 Dram Type= 6, Freq= 0, CH_1, rank 0
4520 23:45:11.943469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4521 23:45:11.943554 ==
4522 23:45:11.943646
4523 23:45:11.943726
4524 23:45:11.946214 TX Vref Scan disable
4525 23:45:11.946327 == TX Byte 0 ==
4526 23:45:11.952932 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4527 23:45:11.956542 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4528 23:45:11.956672 == TX Byte 1 ==
4529 23:45:11.963159 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4530 23:45:11.966541 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4531 23:45:11.966657 ==
4532 23:45:11.969939 Dram Type= 6, Freq= 0, CH_1, rank 0
4533 23:45:11.972684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4534 23:45:11.972797 ==
4535 23:45:11.972894
4536 23:45:11.972990
4537 23:45:11.975926 TX Vref Scan disable
4538 23:45:11.979224 == TX Byte 0 ==
4539 23:45:11.982524 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4540 23:45:11.989353 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4541 23:45:11.989472 == TX Byte 1 ==
4542 23:45:11.992605 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4543 23:45:11.999257 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4544 23:45:11.999382
4545 23:45:11.999487 [DATLAT]
4546 23:45:11.999585 Freq=600, CH1 RK0
4547 23:45:11.999681
4548 23:45:12.002689 DATLAT Default: 0x9
4549 23:45:12.002800 0, 0xFFFF, sum = 0
4550 23:45:12.005823 1, 0xFFFF, sum = 0
4551 23:45:12.009414 2, 0xFFFF, sum = 0
4552 23:45:12.009533 3, 0xFFFF, sum = 0
4553 23:45:12.012684 4, 0xFFFF, sum = 0
4554 23:45:12.012799 5, 0xFFFF, sum = 0
4555 23:45:12.015989 6, 0xFFFF, sum = 0
4556 23:45:12.016103 7, 0xFFFF, sum = 0
4557 23:45:12.019477 8, 0x0, sum = 1
4558 23:45:12.019596 9, 0x0, sum = 2
4559 23:45:12.019696 10, 0x0, sum = 3
4560 23:45:12.022614 11, 0x0, sum = 4
4561 23:45:12.022729 best_step = 9
4562 23:45:12.022828
4563 23:45:12.022925 ==
4564 23:45:12.025973 Dram Type= 6, Freq= 0, CH_1, rank 0
4565 23:45:12.032669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4566 23:45:12.032791 ==
4567 23:45:12.032895 RX Vref Scan: 1
4568 23:45:12.032988
4569 23:45:12.035706 RX Vref 0 -> 0, step: 1
4570 23:45:12.035819
4571 23:45:12.039087 RX Delay -195 -> 252, step: 8
4572 23:45:12.039201
4573 23:45:12.042347 Set Vref, RX VrefLevel [Byte0]: 56
4574 23:45:12.045514 [Byte1]: 48
4575 23:45:12.045622
4576 23:45:12.049351 Final RX Vref Byte 0 = 56 to rank0
4577 23:45:12.052485 Final RX Vref Byte 1 = 48 to rank0
4578 23:45:12.055741 Final RX Vref Byte 0 = 56 to rank1
4579 23:45:12.058891 Final RX Vref Byte 1 = 48 to rank1==
4580 23:45:12.061971 Dram Type= 6, Freq= 0, CH_1, rank 0
4581 23:45:12.065696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4582 23:45:12.065810 ==
4583 23:45:12.068612 DQS Delay:
4584 23:45:12.068728 DQS0 = 0, DQS1 = 0
4585 23:45:12.071936 DQM Delay:
4586 23:45:12.072044 DQM0 = 39, DQM1 = 29
4587 23:45:12.072144 DQ Delay:
4588 23:45:12.075332 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =36
4589 23:45:12.078691 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =36
4590 23:45:12.082023 DQ8 =16, DQ9 =20, DQ10 =28, DQ11 =20
4591 23:45:12.085341 DQ12 =40, DQ13 =36, DQ14 =40, DQ15 =36
4592 23:45:12.085455
4593 23:45:12.085550
4594 23:45:12.095288 [DQSOSCAuto] RK0, (LSB)MR18= 0x2836, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 402 ps
4595 23:45:12.098675 CH1 RK0: MR19=808, MR18=2836
4596 23:45:12.105251 CH1_RK0: MR19=0x808, MR18=0x2836, DQSOSC=399, MR23=63, INC=164, DEC=109
4597 23:45:12.105376
4598 23:45:12.108567 ----->DramcWriteLeveling(PI) begin...
4599 23:45:12.108686 ==
4600 23:45:12.112052 Dram Type= 6, Freq= 0, CH_1, rank 1
4601 23:45:12.115405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4602 23:45:12.115522 ==
4603 23:45:12.118422 Write leveling (Byte 0): 27 => 27
4604 23:45:12.122138 Write leveling (Byte 1): 32 => 32
4605 23:45:12.125029 DramcWriteLeveling(PI) end<-----
4606 23:45:12.125144
4607 23:45:12.125241 ==
4608 23:45:12.128278 Dram Type= 6, Freq= 0, CH_1, rank 1
4609 23:45:12.131583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4610 23:45:12.131695 ==
4611 23:45:12.135022 [Gating] SW mode calibration
4612 23:45:12.141434 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4613 23:45:12.148087 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4614 23:45:12.151471 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4615 23:45:12.154909 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4616 23:45:12.161427 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4617 23:45:12.164695 0 9 12 | B1->B0 | 3232 3030 | 0 0 | (0 0) (1 1)
4618 23:45:12.168291 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4619 23:45:12.174873 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4620 23:45:12.178228 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4621 23:45:12.181487 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4622 23:45:12.188312 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4623 23:45:12.191499 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4624 23:45:12.194838 0 10 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
4625 23:45:12.201487 0 10 12 | B1->B0 | 3333 3939 | 0 0 | (0 0) (0 0)
4626 23:45:12.204666 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4627 23:45:12.207961 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4628 23:45:12.214708 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4629 23:45:12.217856 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4630 23:45:12.220935 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4631 23:45:12.227564 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4632 23:45:12.230943 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4633 23:45:12.234241 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4634 23:45:12.241030 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 23:45:12.244352 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 23:45:12.247780 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 23:45:12.254281 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 23:45:12.257283 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 23:45:12.260929 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 23:45:12.267334 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 23:45:12.270529 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 23:45:12.274154 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 23:45:12.280624 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 23:45:12.283936 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 23:45:12.287422 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 23:45:12.294081 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 23:45:12.297369 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 23:45:12.300297 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 23:45:12.306935 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 23:45:12.310189 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4651 23:45:12.313561 Total UI for P1: 0, mck2ui 16
4652 23:45:12.316806 best dqsien dly found for B0: ( 0, 13, 14)
4653 23:45:12.320241 Total UI for P1: 0, mck2ui 16
4654 23:45:12.323468 best dqsien dly found for B1: ( 0, 13, 14)
4655 23:45:12.327296 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4656 23:45:12.330184 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4657 23:45:12.330316
4658 23:45:12.333727 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4659 23:45:12.337021 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4660 23:45:12.340390 [Gating] SW calibration Done
4661 23:45:12.340510 ==
4662 23:45:12.343384 Dram Type= 6, Freq= 0, CH_1, rank 1
4663 23:45:12.346905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4664 23:45:12.347020 ==
4665 23:45:12.350296 RX Vref Scan: 0
4666 23:45:12.350403
4667 23:45:12.353646 RX Vref 0 -> 0, step: 1
4668 23:45:12.353754
4669 23:45:12.357131 RX Delay -230 -> 252, step: 16
4670 23:45:12.360459 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4671 23:45:12.363613 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4672 23:45:12.366441 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4673 23:45:12.369743 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4674 23:45:12.376797 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4675 23:45:12.379661 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4676 23:45:12.383018 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4677 23:45:12.386551 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4678 23:45:12.393267 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4679 23:45:12.396604 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4680 23:45:12.399976 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4681 23:45:12.403297 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4682 23:45:12.409471 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4683 23:45:12.412649 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4684 23:45:12.416013 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4685 23:45:12.419246 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4686 23:45:12.419358 ==
4687 23:45:12.422631 Dram Type= 6, Freq= 0, CH_1, rank 1
4688 23:45:12.429440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4689 23:45:12.429558 ==
4690 23:45:12.429659 DQS Delay:
4691 23:45:12.432601 DQS0 = 0, DQS1 = 0
4692 23:45:12.432714 DQM Delay:
4693 23:45:12.436187 DQM0 = 35, DQM1 = 29
4694 23:45:12.436300 DQ Delay:
4695 23:45:12.439203 DQ0 =33, DQ1 =33, DQ2 =17, DQ3 =33
4696 23:45:12.442656 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4697 23:45:12.445976 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4698 23:45:12.449005 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4699 23:45:12.449121
4700 23:45:12.449218
4701 23:45:12.449312 ==
4702 23:45:12.452670 Dram Type= 6, Freq= 0, CH_1, rank 1
4703 23:45:12.455706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4704 23:45:12.455822 ==
4705 23:45:12.455920
4706 23:45:12.456013
4707 23:45:12.458983 TX Vref Scan disable
4708 23:45:12.462324 == TX Byte 0 ==
4709 23:45:12.465565 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4710 23:45:12.469420 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4711 23:45:12.472808 == TX Byte 1 ==
4712 23:45:12.475841 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4713 23:45:12.479167 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4714 23:45:12.479282 ==
4715 23:45:12.482495 Dram Type= 6, Freq= 0, CH_1, rank 1
4716 23:45:12.486008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4717 23:45:12.489034 ==
4718 23:45:12.489147
4719 23:45:12.489242
4720 23:45:12.489333 TX Vref Scan disable
4721 23:45:12.493158 == TX Byte 0 ==
4722 23:45:12.496334 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4723 23:45:12.503061 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4724 23:45:12.503174 == TX Byte 1 ==
4725 23:45:12.506329 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4726 23:45:12.513055 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4727 23:45:12.513175
4728 23:45:12.513273 [DATLAT]
4729 23:45:12.513367 Freq=600, CH1 RK1
4730 23:45:12.513462
4731 23:45:12.516198 DATLAT Default: 0x9
4732 23:45:12.516310 0, 0xFFFF, sum = 0
4733 23:45:12.519582 1, 0xFFFF, sum = 0
4734 23:45:12.519700 2, 0xFFFF, sum = 0
4735 23:45:12.522930 3, 0xFFFF, sum = 0
4736 23:45:12.526242 4, 0xFFFF, sum = 0
4737 23:45:12.526355 5, 0xFFFF, sum = 0
4738 23:45:12.529556 6, 0xFFFF, sum = 0
4739 23:45:12.529668 7, 0xFFFF, sum = 0
4740 23:45:12.529765 8, 0x0, sum = 1
4741 23:45:12.532910 9, 0x0, sum = 2
4742 23:45:12.533028 10, 0x0, sum = 3
4743 23:45:12.536272 11, 0x0, sum = 4
4744 23:45:12.536383 best_step = 9
4745 23:45:12.536471
4746 23:45:12.536562 ==
4747 23:45:12.539515 Dram Type= 6, Freq= 0, CH_1, rank 1
4748 23:45:12.546071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4749 23:45:12.546191 ==
4750 23:45:12.546288 RX Vref Scan: 0
4751 23:45:12.546381
4752 23:45:12.549330 RX Vref 0 -> 0, step: 1
4753 23:45:12.549441
4754 23:45:12.552682 RX Delay -195 -> 252, step: 8
4755 23:45:12.556368 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4756 23:45:12.562486 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4757 23:45:12.565890 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4758 23:45:12.569198 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4759 23:45:12.572599 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4760 23:45:12.579278 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4761 23:45:12.582647 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4762 23:45:12.585723 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4763 23:45:12.589395 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4764 23:45:12.592763 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4765 23:45:12.599431 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4766 23:45:12.602515 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4767 23:45:12.605850 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4768 23:45:12.609042 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4769 23:45:12.615523 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4770 23:45:12.619237 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4771 23:45:12.619352 ==
4772 23:45:12.622500 Dram Type= 6, Freq= 0, CH_1, rank 1
4773 23:45:12.625826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4774 23:45:12.625943 ==
4775 23:45:12.628647 DQS Delay:
4776 23:45:12.628761 DQS0 = 0, DQS1 = 0
4777 23:45:12.632538 DQM Delay:
4778 23:45:12.632669 DQM0 = 36, DQM1 = 30
4779 23:45:12.632771 DQ Delay:
4780 23:45:12.635846 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4781 23:45:12.638730 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =32
4782 23:45:12.642005 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =20
4783 23:45:12.645304 DQ12 =36, DQ13 =36, DQ14 =40, DQ15 =36
4784 23:45:12.645424
4785 23:45:12.645521
4786 23:45:12.655655 [DQSOSCAuto] RK1, (LSB)MR18= 0x3756, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 399 ps
4787 23:45:12.658706 CH1 RK1: MR19=808, MR18=3756
4788 23:45:12.665183 CH1_RK1: MR19=0x808, MR18=0x3756, DQSOSC=393, MR23=63, INC=169, DEC=113
4789 23:45:12.665319 [RxdqsGatingPostProcess] freq 600
4790 23:45:12.671745 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4791 23:45:12.675048 Pre-setting of DQS Precalculation
4792 23:45:12.678408 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4793 23:45:12.688405 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4794 23:45:12.694899 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4795 23:45:12.695036
4796 23:45:12.695148
4797 23:45:12.698061 [Calibration Summary] 1200 Mbps
4798 23:45:12.698188 CH 0, Rank 0
4799 23:45:12.701825 SW Impedance : PASS
4800 23:45:12.701954 DUTY Scan : NO K
4801 23:45:12.704659 ZQ Calibration : PASS
4802 23:45:12.708427 Jitter Meter : NO K
4803 23:45:12.708551 CBT Training : PASS
4804 23:45:12.711882 Write leveling : PASS
4805 23:45:12.714752 RX DQS gating : PASS
4806 23:45:12.714845 RX DQ/DQS(RDDQC) : PASS
4807 23:45:12.718203 TX DQ/DQS : PASS
4808 23:45:12.721360 RX DATLAT : PASS
4809 23:45:12.721509 RX DQ/DQS(Engine): PASS
4810 23:45:12.724780 TX OE : NO K
4811 23:45:12.724898 All Pass.
4812 23:45:12.725014
4813 23:45:12.728452 CH 0, Rank 1
4814 23:45:12.728584 SW Impedance : PASS
4815 23:45:12.731263 DUTY Scan : NO K
4816 23:45:12.734595 ZQ Calibration : PASS
4817 23:45:12.734680 Jitter Meter : NO K
4818 23:45:12.737776 CBT Training : PASS
4819 23:45:12.741153 Write leveling : PASS
4820 23:45:12.741273 RX DQS gating : PASS
4821 23:45:12.744404 RX DQ/DQS(RDDQC) : PASS
4822 23:45:12.747833 TX DQ/DQS : PASS
4823 23:45:12.747966 RX DATLAT : PASS
4824 23:45:12.751190 RX DQ/DQS(Engine): PASS
4825 23:45:12.751308 TX OE : NO K
4826 23:45:12.754538 All Pass.
4827 23:45:12.754661
4828 23:45:12.754780 CH 1, Rank 0
4829 23:45:12.757853 SW Impedance : PASS
4830 23:45:12.757980 DUTY Scan : NO K
4831 23:45:12.761229 ZQ Calibration : PASS
4832 23:45:12.764471 Jitter Meter : NO K
4833 23:45:12.764586 CBT Training : PASS
4834 23:45:12.767559 Write leveling : PASS
4835 23:45:12.771101 RX DQS gating : PASS
4836 23:45:12.771216 RX DQ/DQS(RDDQC) : PASS
4837 23:45:12.774627 TX DQ/DQS : PASS
4838 23:45:12.777620 RX DATLAT : PASS
4839 23:45:12.777749 RX DQ/DQS(Engine): PASS
4840 23:45:12.780919 TX OE : NO K
4841 23:45:12.781013 All Pass.
4842 23:45:12.781081
4843 23:45:12.784214 CH 1, Rank 1
4844 23:45:12.784294 SW Impedance : PASS
4845 23:45:12.787466 DUTY Scan : NO K
4846 23:45:12.790873 ZQ Calibration : PASS
4847 23:45:12.790954 Jitter Meter : NO K
4848 23:45:12.794150 CBT Training : PASS
4849 23:45:12.797944 Write leveling : PASS
4850 23:45:12.798041 RX DQS gating : PASS
4851 23:45:12.801123 RX DQ/DQS(RDDQC) : PASS
4852 23:45:12.801300 TX DQ/DQS : PASS
4853 23:45:12.804402 RX DATLAT : PASS
4854 23:45:12.807982 RX DQ/DQS(Engine): PASS
4855 23:45:12.808074 TX OE : NO K
4856 23:45:12.811215 All Pass.
4857 23:45:12.811328
4858 23:45:12.811423 DramC Write-DBI off
4859 23:45:12.814727 PER_BANK_REFRESH: Hybrid Mode
4860 23:45:12.817690 TX_TRACKING: ON
4861 23:45:12.824251 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4862 23:45:12.827262 [FAST_K] Save calibration result to emmc
4863 23:45:12.834114 dramc_set_vcore_voltage set vcore to 662500
4864 23:45:12.834213 Read voltage for 933, 3
4865 23:45:12.834280 Vio18 = 0
4866 23:45:12.837552 Vcore = 662500
4867 23:45:12.837653 Vdram = 0
4868 23:45:12.837720 Vddq = 0
4869 23:45:12.840361 Vmddr = 0
4870 23:45:12.843945 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4871 23:45:12.850464 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4872 23:45:12.853984 MEM_TYPE=3, freq_sel=17
4873 23:45:12.854067 sv_algorithm_assistance_LP4_1600
4874 23:45:12.860514 ============ PULL DRAM RESETB DOWN ============
4875 23:45:12.864014 ========== PULL DRAM RESETB DOWN end =========
4876 23:45:12.867226 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4877 23:45:12.870556 ===================================
4878 23:45:12.873828 LPDDR4 DRAM CONFIGURATION
4879 23:45:12.877049 ===================================
4880 23:45:12.880554 EX_ROW_EN[0] = 0x0
4881 23:45:12.880682 EX_ROW_EN[1] = 0x0
4882 23:45:12.883615 LP4Y_EN = 0x0
4883 23:45:12.883719 WORK_FSP = 0x0
4884 23:45:12.886675 WL = 0x3
4885 23:45:12.886776 RL = 0x3
4886 23:45:12.890599 BL = 0x2
4887 23:45:12.890685 RPST = 0x0
4888 23:45:12.893502 RD_PRE = 0x0
4889 23:45:12.893583 WR_PRE = 0x1
4890 23:45:12.896690 WR_PST = 0x0
4891 23:45:12.896801 DBI_WR = 0x0
4892 23:45:12.900262 DBI_RD = 0x0
4893 23:45:12.903695 OTF = 0x1
4894 23:45:12.906974 ===================================
4895 23:45:12.907053 ===================================
4896 23:45:12.910178 ANA top config
4897 23:45:12.913566 ===================================
4898 23:45:12.916787 DLL_ASYNC_EN = 0
4899 23:45:12.916898 ALL_SLAVE_EN = 1
4900 23:45:12.920190 NEW_RANK_MODE = 1
4901 23:45:12.923453 DLL_IDLE_MODE = 1
4902 23:45:12.926867 LP45_APHY_COMB_EN = 1
4903 23:45:12.930167 TX_ODT_DIS = 1
4904 23:45:12.930266 NEW_8X_MODE = 1
4905 23:45:12.933503 ===================================
4906 23:45:12.936601 ===================================
4907 23:45:12.940121 data_rate = 1866
4908 23:45:12.943277 CKR = 1
4909 23:45:12.946479 DQ_P2S_RATIO = 8
4910 23:45:12.949916 ===================================
4911 23:45:12.953289 CA_P2S_RATIO = 8
4912 23:45:12.956704 DQ_CA_OPEN = 0
4913 23:45:12.956786 DQ_SEMI_OPEN = 0
4914 23:45:12.959890 CA_SEMI_OPEN = 0
4915 23:45:12.963178 CA_FULL_RATE = 0
4916 23:45:12.966530 DQ_CKDIV4_EN = 1
4917 23:45:12.969645 CA_CKDIV4_EN = 1
4918 23:45:12.973092 CA_PREDIV_EN = 0
4919 23:45:12.973176 PH8_DLY = 0
4920 23:45:12.976414 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4921 23:45:12.979675 DQ_AAMCK_DIV = 4
4922 23:45:12.983263 CA_AAMCK_DIV = 4
4923 23:45:12.986356 CA_ADMCK_DIV = 4
4924 23:45:12.989652 DQ_TRACK_CA_EN = 0
4925 23:45:12.989776 CA_PICK = 933
4926 23:45:12.993223 CA_MCKIO = 933
4927 23:45:12.996399 MCKIO_SEMI = 0
4928 23:45:12.999682 PLL_FREQ = 3732
4929 23:45:13.003079 DQ_UI_PI_RATIO = 32
4930 23:45:13.006318 CA_UI_PI_RATIO = 0
4931 23:45:13.009449 ===================================
4932 23:45:13.012731 ===================================
4933 23:45:13.012845 memory_type:LPDDR4
4934 23:45:13.015973 GP_NUM : 10
4935 23:45:13.019323 SRAM_EN : 1
4936 23:45:13.019471 MD32_EN : 0
4937 23:45:13.022984 ===================================
4938 23:45:13.026304 [ANA_INIT] >>>>>>>>>>>>>>
4939 23:45:13.029566 <<<<<< [CONFIGURE PHASE]: ANA_TX
4940 23:45:13.032845 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4941 23:45:13.036330 ===================================
4942 23:45:13.039640 data_rate = 1866,PCW = 0X8f00
4943 23:45:13.042835 ===================================
4944 23:45:13.045981 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4945 23:45:13.048989 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4946 23:45:13.055910 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4947 23:45:13.059114 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4948 23:45:13.065622 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4949 23:45:13.069044 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4950 23:45:13.069162 [ANA_INIT] flow start
4951 23:45:13.072356 [ANA_INIT] PLL >>>>>>>>
4952 23:45:13.075464 [ANA_INIT] PLL <<<<<<<<
4953 23:45:13.075573 [ANA_INIT] MIDPI >>>>>>>>
4954 23:45:13.078880 [ANA_INIT] MIDPI <<<<<<<<
4955 23:45:13.082571 [ANA_INIT] DLL >>>>>>>>
4956 23:45:13.082683 [ANA_INIT] flow end
4957 23:45:13.085397 ============ LP4 DIFF to SE enter ============
4958 23:45:13.092062 ============ LP4 DIFF to SE exit ============
4959 23:45:13.092184 [ANA_INIT] <<<<<<<<<<<<<
4960 23:45:13.095794 [Flow] Enable top DCM control >>>>>
4961 23:45:13.098971 [Flow] Enable top DCM control <<<<<
4962 23:45:13.102242 Enable DLL master slave shuffle
4963 23:45:13.108450 ==============================================================
4964 23:45:13.112432 Gating Mode config
4965 23:45:13.115297 ==============================================================
4966 23:45:13.118618 Config description:
4967 23:45:13.128806 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4968 23:45:13.135296 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4969 23:45:13.138549 SELPH_MODE 0: By rank 1: By Phase
4970 23:45:13.145360 ==============================================================
4971 23:45:13.148201 GAT_TRACK_EN = 1
4972 23:45:13.151573 RX_GATING_MODE = 2
4973 23:45:13.155265 RX_GATING_TRACK_MODE = 2
4974 23:45:13.155391 SELPH_MODE = 1
4975 23:45:13.158706 PICG_EARLY_EN = 1
4976 23:45:13.161837 VALID_LAT_VALUE = 1
4977 23:45:13.168319 ==============================================================
4978 23:45:13.171333 Enter into Gating configuration >>>>
4979 23:45:13.175111 Exit from Gating configuration <<<<
4980 23:45:13.178354 Enter into DVFS_PRE_config >>>>>
4981 23:45:13.188067 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4982 23:45:13.191370 Exit from DVFS_PRE_config <<<<<
4983 23:45:13.195024 Enter into PICG configuration >>>>
4984 23:45:13.197985 Exit from PICG configuration <<<<
4985 23:45:13.201180 [RX_INPUT] configuration >>>>>
4986 23:45:13.204752 [RX_INPUT] configuration <<<<<
4987 23:45:13.208091 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4988 23:45:13.214733 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4989 23:45:13.221338 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4990 23:45:13.227396 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4991 23:45:13.234054 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4992 23:45:13.241138 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4993 23:45:13.243938 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4994 23:45:13.247291 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4995 23:45:13.251099 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4996 23:45:13.254124 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4997 23:45:13.260496 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4998 23:45:13.263885 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4999 23:45:13.267209 ===================================
5000 23:45:13.270443 LPDDR4 DRAM CONFIGURATION
5001 23:45:13.273761 ===================================
5002 23:45:13.273843 EX_ROW_EN[0] = 0x0
5003 23:45:13.277380 EX_ROW_EN[1] = 0x0
5004 23:45:13.277466 LP4Y_EN = 0x0
5005 23:45:13.280525 WORK_FSP = 0x0
5006 23:45:13.280639 WL = 0x3
5007 23:45:13.284096 RL = 0x3
5008 23:45:13.287339 BL = 0x2
5009 23:45:13.287453 RPST = 0x0
5010 23:45:13.290840 RD_PRE = 0x0
5011 23:45:13.290919 WR_PRE = 0x1
5012 23:45:13.294079 WR_PST = 0x0
5013 23:45:13.294160 DBI_WR = 0x0
5014 23:45:13.296873 DBI_RD = 0x0
5015 23:45:13.296979 OTF = 0x1
5016 23:45:13.300604 ===================================
5017 23:45:13.303743 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5018 23:45:13.310086 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5019 23:45:13.313708 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5020 23:45:13.317065 ===================================
5021 23:45:13.320396 LPDDR4 DRAM CONFIGURATION
5022 23:45:13.323257 ===================================
5023 23:45:13.323373 EX_ROW_EN[0] = 0x10
5024 23:45:13.327220 EX_ROW_EN[1] = 0x0
5025 23:45:13.327334 LP4Y_EN = 0x0
5026 23:45:13.329817 WORK_FSP = 0x0
5027 23:45:13.333502 WL = 0x3
5028 23:45:13.333613 RL = 0x3
5029 23:45:13.336553 BL = 0x2
5030 23:45:13.336688 RPST = 0x0
5031 23:45:13.340199 RD_PRE = 0x0
5032 23:45:13.340306 WR_PRE = 0x1
5033 23:45:13.343231 WR_PST = 0x0
5034 23:45:13.343302 DBI_WR = 0x0
5035 23:45:13.346485 DBI_RD = 0x0
5036 23:45:13.346586 OTF = 0x1
5037 23:45:13.349947 ===================================
5038 23:45:13.356781 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5039 23:45:13.360437 nWR fixed to 30
5040 23:45:13.363693 [ModeRegInit_LP4] CH0 RK0
5041 23:45:13.363777 [ModeRegInit_LP4] CH0 RK1
5042 23:45:13.367229 [ModeRegInit_LP4] CH1 RK0
5043 23:45:13.370503 [ModeRegInit_LP4] CH1 RK1
5044 23:45:13.370582 match AC timing 9
5045 23:45:13.377138 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5046 23:45:13.380423 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5047 23:45:13.383903 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5048 23:45:13.390373 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5049 23:45:13.393682 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5050 23:45:13.393800 ==
5051 23:45:13.396918 Dram Type= 6, Freq= 0, CH_0, rank 0
5052 23:45:13.400061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5053 23:45:13.400179 ==
5054 23:45:13.407130 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5055 23:45:13.413396 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5056 23:45:13.416912 [CA 0] Center 38 (8~69) winsize 62
5057 23:45:13.419968 [CA 1] Center 38 (8~69) winsize 62
5058 23:45:13.423372 [CA 2] Center 35 (5~66) winsize 62
5059 23:45:13.426634 [CA 3] Center 35 (5~65) winsize 61
5060 23:45:13.430002 [CA 4] Center 34 (3~65) winsize 63
5061 23:45:13.433269 [CA 5] Center 33 (3~64) winsize 62
5062 23:45:13.433349
5063 23:45:13.436651 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5064 23:45:13.436733
5065 23:45:13.439712 [CATrainingPosCal] consider 1 rank data
5066 23:45:13.442908 u2DelayCellTimex100 = 270/100 ps
5067 23:45:13.446562 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5068 23:45:13.449943 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5069 23:45:13.453155 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5070 23:45:13.456598 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5071 23:45:13.463362 CA4 delay=34 (3~65),Diff = 1 PI (6 cell)
5072 23:45:13.466503 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5073 23:45:13.466648
5074 23:45:13.469805 CA PerBit enable=1, Macro0, CA PI delay=33
5075 23:45:13.469935
5076 23:45:13.473206 [CBTSetCACLKResult] CA Dly = 33
5077 23:45:13.473318 CS Dly: 7 (0~38)
5078 23:45:13.473443 ==
5079 23:45:13.476475 Dram Type= 6, Freq= 0, CH_0, rank 1
5080 23:45:13.483296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5081 23:45:13.483437 ==
5082 23:45:13.486061 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5083 23:45:13.492756 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5084 23:45:13.496138 [CA 0] Center 38 (8~69) winsize 62
5085 23:45:13.499452 [CA 1] Center 38 (8~69) winsize 62
5086 23:45:13.502734 [CA 2] Center 35 (5~66) winsize 62
5087 23:45:13.506272 [CA 3] Center 35 (5~66) winsize 62
5088 23:45:13.509281 [CA 4] Center 34 (4~64) winsize 61
5089 23:45:13.512505 [CA 5] Center 33 (3~64) winsize 62
5090 23:45:13.512636
5091 23:45:13.515964 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5092 23:45:13.516081
5093 23:45:13.519134 [CATrainingPosCal] consider 2 rank data
5094 23:45:13.522562 u2DelayCellTimex100 = 270/100 ps
5095 23:45:13.526190 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5096 23:45:13.529284 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5097 23:45:13.532415 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5098 23:45:13.539427 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5099 23:45:13.542775 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5100 23:45:13.546029 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5101 23:45:13.546152
5102 23:45:13.549191 CA PerBit enable=1, Macro0, CA PI delay=33
5103 23:45:13.549309
5104 23:45:13.552386 [CBTSetCACLKResult] CA Dly = 33
5105 23:45:13.552504 CS Dly: 7 (0~39)
5106 23:45:13.552614
5107 23:45:13.555784 ----->DramcWriteLeveling(PI) begin...
5108 23:45:13.559183 ==
5109 23:45:13.559302 Dram Type= 6, Freq= 0, CH_0, rank 0
5110 23:45:13.565800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5111 23:45:13.565935 ==
5112 23:45:13.568973 Write leveling (Byte 0): 31 => 31
5113 23:45:13.572349 Write leveling (Byte 1): 30 => 30
5114 23:45:13.575705 DramcWriteLeveling(PI) end<-----
5115 23:45:13.575827
5116 23:45:13.575928 ==
5117 23:45:13.579172 Dram Type= 6, Freq= 0, CH_0, rank 0
5118 23:45:13.582550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5119 23:45:13.582684 ==
5120 23:45:13.585707 [Gating] SW mode calibration
5121 23:45:13.592463 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5122 23:45:13.599160 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5123 23:45:13.601978 0 14 0 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
5124 23:45:13.605311 0 14 4 | B1->B0 | 3232 3434 | 1 1 | (0 0) (1 1)
5125 23:45:13.612085 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5126 23:45:13.615357 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5127 23:45:13.618536 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5128 23:45:13.625321 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5129 23:45:13.628573 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5130 23:45:13.632124 0 14 28 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
5131 23:45:13.638555 0 15 0 | B1->B0 | 3333 2e2e | 1 0 | (1 0) (0 1)
5132 23:45:13.641933 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
5133 23:45:13.645057 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5134 23:45:13.651632 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5135 23:45:13.655150 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5136 23:45:13.658114 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5137 23:45:13.664910 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5138 23:45:13.668202 0 15 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5139 23:45:13.671342 1 0 0 | B1->B0 | 2626 3a3a | 0 0 | (0 0) (0 0)
5140 23:45:13.678282 1 0 4 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
5141 23:45:13.681556 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5142 23:45:13.685043 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5143 23:45:13.688296 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5144 23:45:13.694562 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5145 23:45:13.697794 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5146 23:45:13.704540 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5147 23:45:13.707838 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5148 23:45:13.711197 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5149 23:45:13.714560 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5150 23:45:13.721274 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 23:45:13.724596 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 23:45:13.727837 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 23:45:13.734270 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 23:45:13.737529 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 23:45:13.740896 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 23:45:13.747443 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 23:45:13.750525 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5158 23:45:13.757281 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5159 23:45:13.760322 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5160 23:45:13.763987 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 23:45:13.767025 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 23:45:13.773952 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5163 23:45:13.777325 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5164 23:45:13.780337 Total UI for P1: 0, mck2ui 16
5165 23:45:13.783508 best dqsien dly found for B0: ( 1, 2, 28)
5166 23:45:13.787066 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5167 23:45:13.790470 Total UI for P1: 0, mck2ui 16
5168 23:45:13.793531 best dqsien dly found for B1: ( 1, 3, 2)
5169 23:45:13.797048 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5170 23:45:13.800231 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5171 23:45:13.803687
5172 23:45:13.807023 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5173 23:45:13.810118 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5174 23:45:13.813335 [Gating] SW calibration Done
5175 23:45:13.813422 ==
5176 23:45:13.816579 Dram Type= 6, Freq= 0, CH_0, rank 0
5177 23:45:13.819934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5178 23:45:13.820040 ==
5179 23:45:13.820132 RX Vref Scan: 0
5180 23:45:13.823239
5181 23:45:13.823322 RX Vref 0 -> 0, step: 1
5182 23:45:13.823386
5183 23:45:13.826589 RX Delay -80 -> 252, step: 8
5184 23:45:13.830059 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5185 23:45:13.833368 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5186 23:45:13.839710 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5187 23:45:13.843208 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5188 23:45:13.846414 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5189 23:45:13.850051 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5190 23:45:13.853073 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5191 23:45:13.856276 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5192 23:45:13.862852 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5193 23:45:13.866008 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5194 23:45:13.869451 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5195 23:45:13.872909 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5196 23:45:13.879465 iDelay=208, Bit 12, Center 87 (-16 ~ 191) 208
5197 23:45:13.883136 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5198 23:45:13.885732 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5199 23:45:13.889425 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5200 23:45:13.889514 ==
5201 23:45:13.892392 Dram Type= 6, Freq= 0, CH_0, rank 0
5202 23:45:13.899097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5203 23:45:13.899226 ==
5204 23:45:13.899324 DQS Delay:
5205 23:45:13.899419 DQS0 = 0, DQS1 = 0
5206 23:45:13.902729 DQM Delay:
5207 23:45:13.902839 DQM0 = 94, DQM1 = 82
5208 23:45:13.905655 DQ Delay:
5209 23:45:13.909025 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5210 23:45:13.912354 DQ4 =95, DQ5 =79, DQ6 =103, DQ7 =107
5211 23:45:13.915655 DQ8 =75, DQ9 =67, DQ10 =83, DQ11 =75
5212 23:45:13.918877 DQ12 =87, DQ13 =87, DQ14 =91, DQ15 =91
5213 23:45:13.918991
5214 23:45:13.919094
5215 23:45:13.919193 ==
5216 23:45:13.922437 Dram Type= 6, Freq= 0, CH_0, rank 0
5217 23:45:13.925718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5218 23:45:13.925805 ==
5219 23:45:13.925871
5220 23:45:13.925931
5221 23:45:13.929041 TX Vref Scan disable
5222 23:45:13.929120 == TX Byte 0 ==
5223 23:45:13.935782 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5224 23:45:13.938538 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5225 23:45:13.938642 == TX Byte 1 ==
5226 23:45:13.945286 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5227 23:45:13.948503 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5228 23:45:13.948618 ==
5229 23:45:13.951696 Dram Type= 6, Freq= 0, CH_0, rank 0
5230 23:45:13.955149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5231 23:45:13.958288 ==
5232 23:45:13.958369
5233 23:45:13.958452
5234 23:45:13.958544 TX Vref Scan disable
5235 23:45:13.961887 == TX Byte 0 ==
5236 23:45:13.965190 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5237 23:45:13.971839 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5238 23:45:13.971964 == TX Byte 1 ==
5239 23:45:13.975310 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5240 23:45:13.982023 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5241 23:45:13.982126
5242 23:45:13.982194 [DATLAT]
5243 23:45:13.982277 Freq=933, CH0 RK0
5244 23:45:13.982381
5245 23:45:13.985337 DATLAT Default: 0xd
5246 23:45:13.985431 0, 0xFFFF, sum = 0
5247 23:45:13.988734 1, 0xFFFF, sum = 0
5248 23:45:13.991519 2, 0xFFFF, sum = 0
5249 23:45:13.991630 3, 0xFFFF, sum = 0
5250 23:45:13.994715 4, 0xFFFF, sum = 0
5251 23:45:13.994859 5, 0xFFFF, sum = 0
5252 23:45:13.998186 6, 0xFFFF, sum = 0
5253 23:45:13.998312 7, 0xFFFF, sum = 0
5254 23:45:14.001390 8, 0xFFFF, sum = 0
5255 23:45:14.001475 9, 0xFFFF, sum = 0
5256 23:45:14.004979 10, 0x0, sum = 1
5257 23:45:14.005093 11, 0x0, sum = 2
5258 23:45:14.008009 12, 0x0, sum = 3
5259 23:45:14.008089 13, 0x0, sum = 4
5260 23:45:14.008157 best_step = 11
5261 23:45:14.011354
5262 23:45:14.011474 ==
5263 23:45:14.014797 Dram Type= 6, Freq= 0, CH_0, rank 0
5264 23:45:14.017670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5265 23:45:14.017766 ==
5266 23:45:14.017832 RX Vref Scan: 1
5267 23:45:14.017892
5268 23:45:14.021007 RX Vref 0 -> 0, step: 1
5269 23:45:14.021084
5270 23:45:14.024353 RX Delay -77 -> 252, step: 4
5271 23:45:14.024466
5272 23:45:14.027592 Set Vref, RX VrefLevel [Byte0]: 62
5273 23:45:14.030984 [Byte1]: 47
5274 23:45:14.034403
5275 23:45:14.034488 Final RX Vref Byte 0 = 62 to rank0
5276 23:45:14.037692 Final RX Vref Byte 1 = 47 to rank0
5277 23:45:14.040913 Final RX Vref Byte 0 = 62 to rank1
5278 23:45:14.044358 Final RX Vref Byte 1 = 47 to rank1==
5279 23:45:14.047695 Dram Type= 6, Freq= 0, CH_0, rank 0
5280 23:45:14.054440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5281 23:45:14.054597 ==
5282 23:45:14.054693 DQS Delay:
5283 23:45:14.057792 DQS0 = 0, DQS1 = 0
5284 23:45:14.057898 DQM Delay:
5285 23:45:14.057999 DQM0 = 95, DQM1 = 82
5286 23:45:14.061133 DQ Delay:
5287 23:45:14.064289 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =92
5288 23:45:14.067362 DQ4 =96, DQ5 =84, DQ6 =102, DQ7 =106
5289 23:45:14.070847 DQ8 =74, DQ9 =70, DQ10 =82, DQ11 =76
5290 23:45:14.073946 DQ12 =86, DQ13 =86, DQ14 =94, DQ15 =90
5291 23:45:14.074068
5292 23:45:14.074171
5293 23:45:14.080852 [DQSOSCAuto] RK0, (LSB)MR18= 0x1312, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 415 ps
5294 23:45:14.084079 CH0 RK0: MR19=505, MR18=1312
5295 23:45:14.090559 CH0_RK0: MR19=0x505, MR18=0x1312, DQSOSC=415, MR23=63, INC=62, DEC=41
5296 23:45:14.090693
5297 23:45:14.093706 ----->DramcWriteLeveling(PI) begin...
5298 23:45:14.093823 ==
5299 23:45:14.096907 Dram Type= 6, Freq= 0, CH_0, rank 1
5300 23:45:14.100481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5301 23:45:14.100594 ==
5302 23:45:14.103637 Write leveling (Byte 0): 28 => 28
5303 23:45:14.106994 Write leveling (Byte 1): 28 => 28
5304 23:45:14.110318 DramcWriteLeveling(PI) end<-----
5305 23:45:14.110407
5306 23:45:14.110488 ==
5307 23:45:14.113541 Dram Type= 6, Freq= 0, CH_0, rank 1
5308 23:45:14.117020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5309 23:45:14.120284 ==
5310 23:45:14.120410 [Gating] SW mode calibration
5311 23:45:14.129973 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5312 23:45:14.133300 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5313 23:45:14.136626 0 14 0 | B1->B0 | 2626 3434 | 1 1 | (0 0) (1 1)
5314 23:45:14.143371 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5315 23:45:14.146762 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5316 23:45:14.149640 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5317 23:45:14.156392 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5318 23:45:14.159924 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5319 23:45:14.163128 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5320 23:45:14.169595 0 14 28 | B1->B0 | 3232 2e2e | 1 0 | (1 0) (1 1)
5321 23:45:14.173024 0 15 0 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
5322 23:45:14.176577 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5323 23:45:14.182951 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5324 23:45:14.186289 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5325 23:45:14.189740 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5326 23:45:14.196357 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5327 23:45:14.199610 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5328 23:45:14.202792 0 15 28 | B1->B0 | 2727 3636 | 0 0 | (0 0) (0 0)
5329 23:45:14.209502 1 0 0 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
5330 23:45:14.212576 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5331 23:45:14.216235 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5332 23:45:14.222652 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5333 23:45:14.226037 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5334 23:45:14.229268 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5335 23:45:14.236102 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5336 23:45:14.239329 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5337 23:45:14.242650 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5338 23:45:14.249304 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5339 23:45:14.252662 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5340 23:45:14.255925 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5341 23:45:14.262652 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5342 23:45:14.265537 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 23:45:14.269326 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 23:45:14.275772 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 23:45:14.279053 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 23:45:14.282317 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5347 23:45:14.288987 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5348 23:45:14.292232 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5349 23:45:14.295679 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5350 23:45:14.302514 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5351 23:45:14.305797 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5352 23:45:14.309202 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5353 23:45:14.315515 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5354 23:45:14.315612 Total UI for P1: 0, mck2ui 16
5355 23:45:14.318898 best dqsien dly found for B0: ( 1, 2, 28)
5356 23:45:14.322290 Total UI for P1: 0, mck2ui 16
5357 23:45:14.325336 best dqsien dly found for B1: ( 1, 2, 30)
5358 23:45:14.328920 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5359 23:45:14.335256 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5360 23:45:14.335385
5361 23:45:14.338972 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5362 23:45:14.342070 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5363 23:45:14.345200 [Gating] SW calibration Done
5364 23:45:14.345293 ==
5365 23:45:14.348860 Dram Type= 6, Freq= 0, CH_0, rank 1
5366 23:45:14.352173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5367 23:45:14.352282 ==
5368 23:45:14.355411 RX Vref Scan: 0
5369 23:45:14.355512
5370 23:45:14.355586 RX Vref 0 -> 0, step: 1
5371 23:45:14.355646
5372 23:45:14.358912 RX Delay -80 -> 252, step: 8
5373 23:45:14.362169 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5374 23:45:14.365597 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5375 23:45:14.372224 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5376 23:45:14.374978 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5377 23:45:14.378726 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5378 23:45:14.382012 iDelay=208, Bit 5, Center 75 (-24 ~ 175) 200
5379 23:45:14.384924 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5380 23:45:14.391605 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5381 23:45:14.395354 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5382 23:45:14.398452 iDelay=208, Bit 9, Center 67 (-24 ~ 159) 184
5383 23:45:14.401820 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5384 23:45:14.405114 iDelay=208, Bit 11, Center 71 (-24 ~ 167) 192
5385 23:45:14.411750 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5386 23:45:14.415096 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5387 23:45:14.418574 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5388 23:45:14.421440 iDelay=208, Bit 15, Center 87 (-8 ~ 183) 192
5389 23:45:14.421554 ==
5390 23:45:14.424841 Dram Type= 6, Freq= 0, CH_0, rank 1
5391 23:45:14.431248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5392 23:45:14.431393 ==
5393 23:45:14.431514 DQS Delay:
5394 23:45:14.431629 DQS0 = 0, DQS1 = 0
5395 23:45:14.434922 DQM Delay:
5396 23:45:14.435053 DQM0 = 91, DQM1 = 80
5397 23:45:14.437943 DQ Delay:
5398 23:45:14.441412 DQ0 =91, DQ1 =91, DQ2 =91, DQ3 =87
5399 23:45:14.444695 DQ4 =91, DQ5 =75, DQ6 =103, DQ7 =103
5400 23:45:14.447913 DQ8 =71, DQ9 =67, DQ10 =83, DQ11 =71
5401 23:45:14.451029 DQ12 =87, DQ13 =87, DQ14 =91, DQ15 =87
5402 23:45:14.451136
5403 23:45:14.451246
5404 23:45:14.451337 ==
5405 23:45:14.454395 Dram Type= 6, Freq= 0, CH_0, rank 1
5406 23:45:14.458024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5407 23:45:14.458140 ==
5408 23:45:14.458241
5409 23:45:14.458353
5410 23:45:14.461401 TX Vref Scan disable
5411 23:45:14.461531 == TX Byte 0 ==
5412 23:45:14.468187 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5413 23:45:14.471069 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5414 23:45:14.471194 == TX Byte 1 ==
5415 23:45:14.477903 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5416 23:45:14.480939 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5417 23:45:14.481065 ==
5418 23:45:14.484263 Dram Type= 6, Freq= 0, CH_0, rank 1
5419 23:45:14.487527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5420 23:45:14.487618 ==
5421 23:45:14.487686
5422 23:45:14.490858
5423 23:45:14.490942 TX Vref Scan disable
5424 23:45:14.494491 == TX Byte 0 ==
5425 23:45:14.497515 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5426 23:45:14.501118 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5427 23:45:14.504163 == TX Byte 1 ==
5428 23:45:14.507468 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5429 23:45:14.510931 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5430 23:45:14.514278
5431 23:45:14.514371 [DATLAT]
5432 23:45:14.514438 Freq=933, CH0 RK1
5433 23:45:14.514499
5434 23:45:14.517641 DATLAT Default: 0xb
5435 23:45:14.517733 0, 0xFFFF, sum = 0
5436 23:45:14.520955 1, 0xFFFF, sum = 0
5437 23:45:14.521044 2, 0xFFFF, sum = 0
5438 23:45:14.524139 3, 0xFFFF, sum = 0
5439 23:45:14.527629 4, 0xFFFF, sum = 0
5440 23:45:14.527720 5, 0xFFFF, sum = 0
5441 23:45:14.530570 6, 0xFFFF, sum = 0
5442 23:45:14.530659 7, 0xFFFF, sum = 0
5443 23:45:14.534343 8, 0xFFFF, sum = 0
5444 23:45:14.534433 9, 0xFFFF, sum = 0
5445 23:45:14.537508 10, 0x0, sum = 1
5446 23:45:14.537602 11, 0x0, sum = 2
5447 23:45:14.540374 12, 0x0, sum = 3
5448 23:45:14.540462 13, 0x0, sum = 4
5449 23:45:14.540529 best_step = 11
5450 23:45:14.540616
5451 23:45:14.544097 ==
5452 23:45:14.547167 Dram Type= 6, Freq= 0, CH_0, rank 1
5453 23:45:14.550771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5454 23:45:14.550867 ==
5455 23:45:14.550934 RX Vref Scan: 0
5456 23:45:14.550996
5457 23:45:14.554090 RX Vref 0 -> 0, step: 1
5458 23:45:14.554202
5459 23:45:14.557403 RX Delay -69 -> 252, step: 4
5460 23:45:14.560371 iDelay=199, Bit 0, Center 90 (-1 ~ 182) 184
5461 23:45:14.566999 iDelay=199, Bit 1, Center 92 (-1 ~ 186) 188
5462 23:45:14.570393 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5463 23:45:14.573765 iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196
5464 23:45:14.577161 iDelay=199, Bit 4, Center 90 (-5 ~ 186) 192
5465 23:45:14.580596 iDelay=199, Bit 5, Center 80 (-13 ~ 174) 188
5466 23:45:14.583966 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5467 23:45:14.590448 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5468 23:45:14.593734 iDelay=199, Bit 8, Center 76 (-13 ~ 166) 180
5469 23:45:14.597103 iDelay=199, Bit 9, Center 66 (-21 ~ 154) 176
5470 23:45:14.600508 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5471 23:45:14.606880 iDelay=199, Bit 11, Center 76 (-13 ~ 166) 180
5472 23:45:14.610193 iDelay=199, Bit 12, Center 90 (-1 ~ 182) 184
5473 23:45:14.613391 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5474 23:45:14.616687 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5475 23:45:14.619990 iDelay=199, Bit 15, Center 90 (-1 ~ 182) 184
5476 23:45:14.620080 ==
5477 23:45:14.623365 Dram Type= 6, Freq= 0, CH_0, rank 1
5478 23:45:14.629966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5479 23:45:14.630057 ==
5480 23:45:14.630145 DQS Delay:
5481 23:45:14.633608 DQS0 = 0, DQS1 = 0
5482 23:45:14.633697 DQM Delay:
5483 23:45:14.633785 DQM0 = 92, DQM1 = 83
5484 23:45:14.636782 DQ Delay:
5485 23:45:14.640087 DQ0 =90, DQ1 =92, DQ2 =88, DQ3 =88
5486 23:45:14.643292 DQ4 =90, DQ5 =80, DQ6 =106, DQ7 =104
5487 23:45:14.646920 DQ8 =76, DQ9 =66, DQ10 =86, DQ11 =76
5488 23:45:14.649925 DQ12 =90, DQ13 =90, DQ14 =96, DQ15 =90
5489 23:45:14.650015
5490 23:45:14.650102
5491 23:45:14.656627 [DQSOSCAuto] RK1, (LSB)MR18= 0x3213, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 406 ps
5492 23:45:14.660224 CH0 RK1: MR19=505, MR18=3213
5493 23:45:14.666857 CH0_RK1: MR19=0x505, MR18=0x3213, DQSOSC=406, MR23=63, INC=65, DEC=43
5494 23:45:14.670239 [RxdqsGatingPostProcess] freq 933
5495 23:45:14.673103 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5496 23:45:14.676552 best DQS0 dly(2T, 0.5T) = (0, 10)
5497 23:45:14.679736 best DQS1 dly(2T, 0.5T) = (0, 11)
5498 23:45:14.682979 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5499 23:45:14.686311 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5500 23:45:14.689499 best DQS0 dly(2T, 0.5T) = (0, 10)
5501 23:45:14.692853 best DQS1 dly(2T, 0.5T) = (0, 10)
5502 23:45:14.696528 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5503 23:45:14.699394 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5504 23:45:14.702805 Pre-setting of DQS Precalculation
5505 23:45:14.706043 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5506 23:45:14.709533 ==
5507 23:45:14.712967 Dram Type= 6, Freq= 0, CH_1, rank 0
5508 23:45:14.716443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5509 23:45:14.716554 ==
5510 23:45:14.719565 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5511 23:45:14.726093 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5512 23:45:14.729958 [CA 0] Center 36 (7~66) winsize 60
5513 23:45:14.732778 [CA 1] Center 37 (7~67) winsize 61
5514 23:45:14.736791 [CA 2] Center 34 (5~64) winsize 60
5515 23:45:14.739915 [CA 3] Center 34 (4~64) winsize 61
5516 23:45:14.743284 [CA 4] Center 34 (5~64) winsize 60
5517 23:45:14.746083 [CA 5] Center 33 (4~63) winsize 60
5518 23:45:14.746213
5519 23:45:14.749457 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5520 23:45:14.749542
5521 23:45:14.753206 [CATrainingPosCal] consider 1 rank data
5522 23:45:14.756095 u2DelayCellTimex100 = 270/100 ps
5523 23:45:14.759960 CA0 delay=36 (7~66),Diff = 3 PI (18 cell)
5524 23:45:14.766108 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5525 23:45:14.769376 CA2 delay=34 (5~64),Diff = 1 PI (6 cell)
5526 23:45:14.772581 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5527 23:45:14.776014 CA4 delay=34 (5~64),Diff = 1 PI (6 cell)
5528 23:45:14.779524 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5529 23:45:14.779636
5530 23:45:14.782640 CA PerBit enable=1, Macro0, CA PI delay=33
5531 23:45:14.782746
5532 23:45:14.786223 [CBTSetCACLKResult] CA Dly = 33
5533 23:45:14.786343 CS Dly: 5 (0~36)
5534 23:45:14.789409 ==
5535 23:45:14.792514 Dram Type= 6, Freq= 0, CH_1, rank 1
5536 23:45:14.796277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5537 23:45:14.796415 ==
5538 23:45:14.799652 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5539 23:45:14.805893 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5540 23:45:14.809814 [CA 0] Center 37 (8~66) winsize 59
5541 23:45:14.813136 [CA 1] Center 37 (7~68) winsize 62
5542 23:45:14.816444 [CA 2] Center 35 (5~65) winsize 61
5543 23:45:14.819730 [CA 3] Center 34 (4~64) winsize 61
5544 23:45:14.822902 [CA 4] Center 34 (4~65) winsize 62
5545 23:45:14.826340 [CA 5] Center 33 (3~64) winsize 62
5546 23:45:14.826471
5547 23:45:14.829687 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5548 23:45:14.829816
5549 23:45:14.833259 [CATrainingPosCal] consider 2 rank data
5550 23:45:14.836158 u2DelayCellTimex100 = 270/100 ps
5551 23:45:14.839390 CA0 delay=37 (8~66),Diff = 4 PI (24 cell)
5552 23:45:14.845977 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5553 23:45:14.849554 CA2 delay=34 (5~64),Diff = 1 PI (6 cell)
5554 23:45:14.852778 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5555 23:45:14.856107 CA4 delay=34 (5~64),Diff = 1 PI (6 cell)
5556 23:45:14.859339 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5557 23:45:14.859418
5558 23:45:14.862703 CA PerBit enable=1, Macro0, CA PI delay=33
5559 23:45:14.862780
5560 23:45:14.866085 [CBTSetCACLKResult] CA Dly = 33
5561 23:45:14.866173 CS Dly: 6 (0~39)
5562 23:45:14.869523
5563 23:45:14.872719 ----->DramcWriteLeveling(PI) begin...
5564 23:45:14.872831 ==
5565 23:45:14.876045 Dram Type= 6, Freq= 0, CH_1, rank 0
5566 23:45:14.879499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5567 23:45:14.879583 ==
5568 23:45:14.882710 Write leveling (Byte 0): 27 => 27
5569 23:45:14.886038 Write leveling (Byte 1): 28 => 28
5570 23:45:14.889246 DramcWriteLeveling(PI) end<-----
5571 23:45:14.889329
5572 23:45:14.889392 ==
5573 23:45:14.892509 Dram Type= 6, Freq= 0, CH_1, rank 0
5574 23:45:14.895949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5575 23:45:14.896031 ==
5576 23:45:14.899087 [Gating] SW mode calibration
5577 23:45:14.905969 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5578 23:45:14.912178 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5579 23:45:14.915600 0 14 0 | B1->B0 | 3333 3030 | 0 1 | (0 0) (1 1)
5580 23:45:14.918935 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5581 23:45:14.925715 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5582 23:45:14.929018 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5583 23:45:14.932091 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5584 23:45:14.938745 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5585 23:45:14.941946 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5586 23:45:14.945236 0 14 28 | B1->B0 | 2f2f 2f2f | 1 1 | (1 0) (1 0)
5587 23:45:14.952092 0 15 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5588 23:45:14.955611 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5589 23:45:14.958574 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5590 23:45:14.965208 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5591 23:45:14.968180 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5592 23:45:14.971638 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5593 23:45:14.978357 0 15 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5594 23:45:14.981479 0 15 28 | B1->B0 | 3434 3130 | 0 1 | (0 0) (0 0)
5595 23:45:14.985080 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5596 23:45:14.991478 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5597 23:45:14.994789 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5598 23:45:14.998318 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5599 23:45:15.004937 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5600 23:45:15.008386 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5601 23:45:15.011317 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5602 23:45:15.017839 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5603 23:45:15.021314 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5604 23:45:15.024529 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5605 23:45:15.031163 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5606 23:45:15.034933 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 23:45:15.038159 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 23:45:15.044417 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 23:45:15.047953 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 23:45:15.051334 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 23:45:15.057391 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 23:45:15.060762 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 23:45:15.064454 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5614 23:45:15.070937 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 23:45:15.074172 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 23:45:15.077652 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 23:45:15.084029 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 23:45:15.087357 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5619 23:45:15.090638 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5620 23:45:15.094457 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5621 23:45:15.097200 Total UI for P1: 0, mck2ui 16
5622 23:45:15.100686 best dqsien dly found for B0: ( 1, 2, 30)
5623 23:45:15.103947 Total UI for P1: 0, mck2ui 16
5624 23:45:15.107342 best dqsien dly found for B1: ( 1, 2, 30)
5625 23:45:15.110501 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5626 23:45:15.117150 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5627 23:45:15.117246
5628 23:45:15.120469 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5629 23:45:15.123738 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5630 23:45:15.127138 [Gating] SW calibration Done
5631 23:45:15.127246 ==
5632 23:45:15.130467 Dram Type= 6, Freq= 0, CH_1, rank 0
5633 23:45:15.133808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5634 23:45:15.133913 ==
5635 23:45:15.137058 RX Vref Scan: 0
5636 23:45:15.137160
5637 23:45:15.137263 RX Vref 0 -> 0, step: 1
5638 23:45:15.137352
5639 23:45:15.140380 RX Delay -80 -> 252, step: 8
5640 23:45:15.143664 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5641 23:45:15.147044 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5642 23:45:15.153342 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5643 23:45:15.156838 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5644 23:45:15.160160 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5645 23:45:15.163589 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5646 23:45:15.166863 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5647 23:45:15.173668 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5648 23:45:15.176678 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5649 23:45:15.180074 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5650 23:45:15.183208 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5651 23:45:15.186813 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5652 23:45:15.193274 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5653 23:45:15.196535 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5654 23:45:15.199900 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5655 23:45:15.203040 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5656 23:45:15.203162 ==
5657 23:45:15.206680 Dram Type= 6, Freq= 0, CH_1, rank 0
5658 23:45:15.210087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5659 23:45:15.210202 ==
5660 23:45:15.213158 DQS Delay:
5661 23:45:15.213240 DQS0 = 0, DQS1 = 0
5662 23:45:15.216738 DQM Delay:
5663 23:45:15.216841 DQM0 = 94, DQM1 = 89
5664 23:45:15.216942 DQ Delay:
5665 23:45:15.219951 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =87
5666 23:45:15.223093 DQ4 =91, DQ5 =107, DQ6 =103, DQ7 =91
5667 23:45:15.226563 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5668 23:45:15.230014 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5669 23:45:15.230115
5670 23:45:15.232909
5671 23:45:15.232993 ==
5672 23:45:15.236129 Dram Type= 6, Freq= 0, CH_1, rank 0
5673 23:45:15.239450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5674 23:45:15.239535 ==
5675 23:45:15.239603
5676 23:45:15.239681
5677 23:45:15.242759 TX Vref Scan disable
5678 23:45:15.242870 == TX Byte 0 ==
5679 23:45:15.249377 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5680 23:45:15.252718 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5681 23:45:15.252811 == TX Byte 1 ==
5682 23:45:15.259274 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5683 23:45:15.262746 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5684 23:45:15.262853 ==
5685 23:45:15.265968 Dram Type= 6, Freq= 0, CH_1, rank 0
5686 23:45:15.269400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5687 23:45:15.269518 ==
5688 23:45:15.269618
5689 23:45:15.269710
5690 23:45:15.272714 TX Vref Scan disable
5691 23:45:15.276022 == TX Byte 0 ==
5692 23:45:15.279521 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5693 23:45:15.283001 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5694 23:45:15.286108 == TX Byte 1 ==
5695 23:45:15.289336 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5696 23:45:15.292519 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5697 23:45:15.292623
5698 23:45:15.295955 [DATLAT]
5699 23:45:15.296066 Freq=933, CH1 RK0
5700 23:45:15.296169
5701 23:45:15.299414 DATLAT Default: 0xd
5702 23:45:15.299527 0, 0xFFFF, sum = 0
5703 23:45:15.302698 1, 0xFFFF, sum = 0
5704 23:45:15.302811 2, 0xFFFF, sum = 0
5705 23:45:15.306018 3, 0xFFFF, sum = 0
5706 23:45:15.306136 4, 0xFFFF, sum = 0
5707 23:45:15.309287 5, 0xFFFF, sum = 0
5708 23:45:15.309400 6, 0xFFFF, sum = 0
5709 23:45:15.312436 7, 0xFFFF, sum = 0
5710 23:45:15.312564 8, 0xFFFF, sum = 0
5711 23:45:15.315704 9, 0xFFFF, sum = 0
5712 23:45:15.315820 10, 0x0, sum = 1
5713 23:45:15.319055 11, 0x0, sum = 2
5714 23:45:15.319174 12, 0x0, sum = 3
5715 23:45:15.322171 13, 0x0, sum = 4
5716 23:45:15.322288 best_step = 11
5717 23:45:15.322396
5718 23:45:15.322490 ==
5719 23:45:15.325491 Dram Type= 6, Freq= 0, CH_1, rank 0
5720 23:45:15.332528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5721 23:45:15.332637 ==
5722 23:45:15.332705 RX Vref Scan: 1
5723 23:45:15.332767
5724 23:45:15.335604 RX Vref 0 -> 0, step: 1
5725 23:45:15.335718
5726 23:45:15.338961 RX Delay -61 -> 252, step: 4
5727 23:45:15.339070
5728 23:45:15.342351 Set Vref, RX VrefLevel [Byte0]: 56
5729 23:45:15.345704 [Byte1]: 48
5730 23:45:15.345818
5731 23:45:15.348731 Final RX Vref Byte 0 = 56 to rank0
5732 23:45:15.352106 Final RX Vref Byte 1 = 48 to rank0
5733 23:45:15.355583 Final RX Vref Byte 0 = 56 to rank1
5734 23:45:15.358886 Final RX Vref Byte 1 = 48 to rank1==
5735 23:45:15.362190 Dram Type= 6, Freq= 0, CH_1, rank 0
5736 23:45:15.365542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5737 23:45:15.365632 ==
5738 23:45:15.368927 DQS Delay:
5739 23:45:15.369014 DQS0 = 0, DQS1 = 0
5740 23:45:15.369082 DQM Delay:
5741 23:45:15.371810 DQM0 = 95, DQM1 = 86
5742 23:45:15.371886 DQ Delay:
5743 23:45:15.375086 DQ0 =100, DQ1 =92, DQ2 =84, DQ3 =92
5744 23:45:15.378435 DQ4 =92, DQ5 =104, DQ6 =108, DQ7 =92
5745 23:45:15.381977 DQ8 =74, DQ9 =78, DQ10 =88, DQ11 =80
5746 23:45:15.385165 DQ12 =96, DQ13 =92, DQ14 =92, DQ15 =94
5747 23:45:15.385283
5748 23:45:15.385388
5749 23:45:15.395187 [DQSOSCAuto] RK0, (LSB)MR18= 0x40d, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 420 ps
5750 23:45:15.398444 CH1 RK0: MR19=505, MR18=40D
5751 23:45:15.402001 CH1_RK0: MR19=0x505, MR18=0x40D, DQSOSC=417, MR23=63, INC=62, DEC=41
5752 23:45:15.402117
5753 23:45:15.405263 ----->DramcWriteLeveling(PI) begin...
5754 23:45:15.408574 ==
5755 23:45:15.411964 Dram Type= 6, Freq= 0, CH_1, rank 1
5756 23:45:15.415295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5757 23:45:15.415444 ==
5758 23:45:15.418622 Write leveling (Byte 0): 25 => 25
5759 23:45:15.421721 Write leveling (Byte 1): 30 => 30
5760 23:45:15.424983 DramcWriteLeveling(PI) end<-----
5761 23:45:15.425132
5762 23:45:15.425249 ==
5763 23:45:15.428144 Dram Type= 6, Freq= 0, CH_1, rank 1
5764 23:45:15.431579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5765 23:45:15.431719 ==
5766 23:45:15.434905 [Gating] SW mode calibration
5767 23:45:15.441640 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5768 23:45:15.448215 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5769 23:45:15.451751 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5770 23:45:15.455090 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5771 23:45:15.461594 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5772 23:45:15.464877 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5773 23:45:15.467871 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5774 23:45:15.475030 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5775 23:45:15.478017 0 14 24 | B1->B0 | 3333 3131 | 0 0 | (0 0) (0 1)
5776 23:45:15.481028 0 14 28 | B1->B0 | 2525 2323 | 1 0 | (1 0) (1 0)
5777 23:45:15.487734 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5778 23:45:15.491180 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5779 23:45:15.494480 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5780 23:45:15.501261 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5781 23:45:15.504592 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5782 23:45:15.507792 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5783 23:45:15.514669 0 15 24 | B1->B0 | 2828 3636 | 0 0 | (0 0) (0 0)
5784 23:45:15.518089 0 15 28 | B1->B0 | 3c3c 4646 | 1 0 | (0 0) (0 0)
5785 23:45:15.520901 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5786 23:45:15.524335 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5787 23:45:15.530994 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5788 23:45:15.534171 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5789 23:45:15.537614 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5790 23:45:15.544406 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5791 23:45:15.547756 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5792 23:45:15.550583 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5793 23:45:15.557367 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5794 23:45:15.560760 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5795 23:45:15.564262 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5796 23:45:15.570541 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5797 23:45:15.573885 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 23:45:15.577168 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 23:45:15.583925 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 23:45:15.587282 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5801 23:45:15.590764 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5802 23:45:15.597335 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5803 23:45:15.600709 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5804 23:45:15.604075 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5805 23:45:15.610415 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 23:45:15.613752 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 23:45:15.616966 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5808 23:45:15.620682 Total UI for P1: 0, mck2ui 16
5809 23:45:15.624087 best dqsien dly found for B0: ( 1, 2, 22)
5810 23:45:15.630156 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5811 23:45:15.633633 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5812 23:45:15.637109 Total UI for P1: 0, mck2ui 16
5813 23:45:15.640451 best dqsien dly found for B1: ( 1, 2, 26)
5814 23:45:15.643790 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5815 23:45:15.646900 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5816 23:45:15.647015
5817 23:45:15.650130 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5818 23:45:15.653645 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5819 23:45:15.656828 [Gating] SW calibration Done
5820 23:45:15.656908 ==
5821 23:45:15.660161 Dram Type= 6, Freq= 0, CH_1, rank 1
5822 23:45:15.663491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5823 23:45:15.666803 ==
5824 23:45:15.666882 RX Vref Scan: 0
5825 23:45:15.666974
5826 23:45:15.670043 RX Vref 0 -> 0, step: 1
5827 23:45:15.670145
5828 23:45:15.673363 RX Delay -80 -> 252, step: 8
5829 23:45:15.676579 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5830 23:45:15.680129 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5831 23:45:15.683293 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5832 23:45:15.686593 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5833 23:45:15.690017 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5834 23:45:15.696360 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5835 23:45:15.699785 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5836 23:45:15.703121 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5837 23:45:15.706579 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5838 23:45:15.709906 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5839 23:45:15.716477 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5840 23:45:15.719866 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5841 23:45:15.723262 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5842 23:45:15.726346 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5843 23:45:15.729917 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5844 23:45:15.736250 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5845 23:45:15.736335 ==
5846 23:45:15.739530 Dram Type= 6, Freq= 0, CH_1, rank 1
5847 23:45:15.742906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5848 23:45:15.743010 ==
5849 23:45:15.743081 DQS Delay:
5850 23:45:15.746317 DQS0 = 0, DQS1 = 0
5851 23:45:15.746396 DQM Delay:
5852 23:45:15.749505 DQM0 = 95, DQM1 = 87
5853 23:45:15.749582 DQ Delay:
5854 23:45:15.752919 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5855 23:45:15.756371 DQ4 =91, DQ5 =107, DQ6 =107, DQ7 =91
5856 23:45:15.759467 DQ8 =75, DQ9 =75, DQ10 =95, DQ11 =79
5857 23:45:15.762712 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =91
5858 23:45:15.762797
5859 23:45:15.762862
5860 23:45:15.762923 ==
5861 23:45:15.766313 Dram Type= 6, Freq= 0, CH_1, rank 1
5862 23:45:15.769587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5863 23:45:15.769676 ==
5864 23:45:15.769764
5865 23:45:15.769846
5866 23:45:15.773040 TX Vref Scan disable
5867 23:45:15.775920 == TX Byte 0 ==
5868 23:45:15.779724 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5869 23:45:15.783073 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5870 23:45:15.786127 == TX Byte 1 ==
5871 23:45:15.789572 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5872 23:45:15.792922 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5873 23:45:15.793008 ==
5874 23:45:15.796277 Dram Type= 6, Freq= 0, CH_1, rank 1
5875 23:45:15.802804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5876 23:45:15.802891 ==
5877 23:45:15.802957
5878 23:45:15.803018
5879 23:45:15.803075 TX Vref Scan disable
5880 23:45:15.806447 == TX Byte 0 ==
5881 23:45:15.810042 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5882 23:45:15.816828 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5883 23:45:15.816915 == TX Byte 1 ==
5884 23:45:15.820029 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5885 23:45:15.826372 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5886 23:45:15.826512
5887 23:45:15.826629 [DATLAT]
5888 23:45:15.826744 Freq=933, CH1 RK1
5889 23:45:15.826857
5890 23:45:15.829605 DATLAT Default: 0xb
5891 23:45:15.829732 0, 0xFFFF, sum = 0
5892 23:45:15.832841 1, 0xFFFF, sum = 0
5893 23:45:15.836402 2, 0xFFFF, sum = 0
5894 23:45:15.836530 3, 0xFFFF, sum = 0
5895 23:45:15.839727 4, 0xFFFF, sum = 0
5896 23:45:15.839839 5, 0xFFFF, sum = 0
5897 23:45:15.843231 6, 0xFFFF, sum = 0
5898 23:45:15.843343 7, 0xFFFF, sum = 0
5899 23:45:15.846060 8, 0xFFFF, sum = 0
5900 23:45:15.846136 9, 0xFFFF, sum = 0
5901 23:45:15.849458 10, 0x0, sum = 1
5902 23:45:15.849539 11, 0x0, sum = 2
5903 23:45:15.852737 12, 0x0, sum = 3
5904 23:45:15.852810 13, 0x0, sum = 4
5905 23:45:15.852893 best_step = 11
5906 23:45:15.856143
5907 23:45:15.856239 ==
5908 23:45:15.859313 Dram Type= 6, Freq= 0, CH_1, rank 1
5909 23:45:15.862970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5910 23:45:15.863065 ==
5911 23:45:15.863130 RX Vref Scan: 0
5912 23:45:15.863189
5913 23:45:15.865978 RX Vref 0 -> 0, step: 1
5914 23:45:15.866053
5915 23:45:15.869177 RX Delay -69 -> 252, step: 4
5916 23:45:15.875695 iDelay=203, Bit 0, Center 98 (3 ~ 194) 192
5917 23:45:15.879086 iDelay=203, Bit 1, Center 88 (-5 ~ 182) 188
5918 23:45:15.882471 iDelay=203, Bit 2, Center 84 (-9 ~ 178) 188
5919 23:45:15.885777 iDelay=203, Bit 3, Center 90 (-5 ~ 186) 192
5920 23:45:15.889289 iDelay=203, Bit 4, Center 88 (-9 ~ 186) 196
5921 23:45:15.892841 iDelay=203, Bit 5, Center 102 (7 ~ 198) 192
5922 23:45:15.899052 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
5923 23:45:15.902395 iDelay=203, Bit 7, Center 90 (-5 ~ 186) 192
5924 23:45:15.905714 iDelay=203, Bit 8, Center 76 (-17 ~ 170) 188
5925 23:45:15.909065 iDelay=203, Bit 9, Center 82 (-13 ~ 178) 192
5926 23:45:15.912265 iDelay=203, Bit 10, Center 92 (-1 ~ 186) 188
5927 23:45:15.919037 iDelay=203, Bit 11, Center 84 (-9 ~ 178) 188
5928 23:45:15.922452 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188
5929 23:45:15.925786 iDelay=203, Bit 13, Center 96 (3 ~ 190) 188
5930 23:45:15.929020 iDelay=203, Bit 14, Center 92 (-1 ~ 186) 188
5931 23:45:15.932089 iDelay=203, Bit 15, Center 94 (-1 ~ 190) 192
5932 23:45:15.932211 ==
5933 23:45:15.935368 Dram Type= 6, Freq= 0, CH_1, rank 1
5934 23:45:15.941754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5935 23:45:15.941884 ==
5936 23:45:15.942001 DQS Delay:
5937 23:45:15.945410 DQS0 = 0, DQS1 = 0
5938 23:45:15.945532 DQM Delay:
5939 23:45:15.948748 DQM0 = 93, DQM1 = 89
5940 23:45:15.948877 DQ Delay:
5941 23:45:15.952081 DQ0 =98, DQ1 =88, DQ2 =84, DQ3 =90
5942 23:45:15.955388 DQ4 =88, DQ5 =102, DQ6 =104, DQ7 =90
5943 23:45:15.958931 DQ8 =76, DQ9 =82, DQ10 =92, DQ11 =84
5944 23:45:15.961678 DQ12 =96, DQ13 =96, DQ14 =92, DQ15 =94
5945 23:45:15.961805
5946 23:45:15.961921
5947 23:45:15.968548 [DQSOSCAuto] RK1, (LSB)MR18= 0xd21, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 417 ps
5948 23:45:15.971748 CH1 RK1: MR19=505, MR18=D21
5949 23:45:15.978396 CH1_RK1: MR19=0x505, MR18=0xD21, DQSOSC=411, MR23=63, INC=64, DEC=42
5950 23:45:15.981573 [RxdqsGatingPostProcess] freq 933
5951 23:45:15.984822 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5952 23:45:15.988294 best DQS0 dly(2T, 0.5T) = (0, 10)
5953 23:45:15.991602 best DQS1 dly(2T, 0.5T) = (0, 10)
5954 23:45:15.995065 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5955 23:45:15.997911 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5956 23:45:16.001974 best DQS0 dly(2T, 0.5T) = (0, 10)
5957 23:45:16.004866 best DQS1 dly(2T, 0.5T) = (0, 10)
5958 23:45:16.007927 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5959 23:45:16.011007 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5960 23:45:16.014479 Pre-setting of DQS Precalculation
5961 23:45:16.021009 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5962 23:45:16.027885 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5963 23:45:16.034480 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5964 23:45:16.034572
5965 23:45:16.034638
5966 23:45:16.037670 [Calibration Summary] 1866 Mbps
5967 23:45:16.037747 CH 0, Rank 0
5968 23:45:16.041306 SW Impedance : PASS
5969 23:45:16.044482 DUTY Scan : NO K
5970 23:45:16.044591 ZQ Calibration : PASS
5971 23:45:16.047799 Jitter Meter : NO K
5972 23:45:16.047874 CBT Training : PASS
5973 23:45:16.050983 Write leveling : PASS
5974 23:45:16.054122 RX DQS gating : PASS
5975 23:45:16.054198 RX DQ/DQS(RDDQC) : PASS
5976 23:45:16.057418 TX DQ/DQS : PASS
5977 23:45:16.060776 RX DATLAT : PASS
5978 23:45:16.060856 RX DQ/DQS(Engine): PASS
5979 23:45:16.064103 TX OE : NO K
5980 23:45:16.064206 All Pass.
5981 23:45:16.064299
5982 23:45:16.067514 CH 0, Rank 1
5983 23:45:16.067620 SW Impedance : PASS
5984 23:45:16.070941 DUTY Scan : NO K
5985 23:45:16.074040 ZQ Calibration : PASS
5986 23:45:16.074138 Jitter Meter : NO K
5987 23:45:16.077417 CBT Training : PASS
5988 23:45:16.080741 Write leveling : PASS
5989 23:45:16.080865 RX DQS gating : PASS
5990 23:45:16.084278 RX DQ/DQS(RDDQC) : PASS
5991 23:45:16.087445 TX DQ/DQS : PASS
5992 23:45:16.087579 RX DATLAT : PASS
5993 23:45:16.090600 RX DQ/DQS(Engine): PASS
5994 23:45:16.093978 TX OE : NO K
5995 23:45:16.094105 All Pass.
5996 23:45:16.094218
5997 23:45:16.094329 CH 1, Rank 0
5998 23:45:16.097354 SW Impedance : PASS
5999 23:45:16.100233 DUTY Scan : NO K
6000 23:45:16.100356 ZQ Calibration : PASS
6001 23:45:16.104145 Jitter Meter : NO K
6002 23:45:16.107424 CBT Training : PASS
6003 23:45:16.107547 Write leveling : PASS
6004 23:45:16.110309 RX DQS gating : PASS
6005 23:45:16.110435 RX DQ/DQS(RDDQC) : PASS
6006 23:45:16.113567 TX DQ/DQS : PASS
6007 23:45:16.117076 RX DATLAT : PASS
6008 23:45:16.117198 RX DQ/DQS(Engine): PASS
6009 23:45:16.120728 TX OE : NO K
6010 23:45:16.120813 All Pass.
6011 23:45:16.120878
6012 23:45:16.123882 CH 1, Rank 1
6013 23:45:16.123992 SW Impedance : PASS
6014 23:45:16.127165 DUTY Scan : NO K
6015 23:45:16.130228 ZQ Calibration : PASS
6016 23:45:16.130354 Jitter Meter : NO K
6017 23:45:16.133345 CBT Training : PASS
6018 23:45:16.136615 Write leveling : PASS
6019 23:45:16.136743 RX DQS gating : PASS
6020 23:45:16.139937 RX DQ/DQS(RDDQC) : PASS
6021 23:45:16.143682 TX DQ/DQS : PASS
6022 23:45:16.143812 RX DATLAT : PASS
6023 23:45:16.146450 RX DQ/DQS(Engine): PASS
6024 23:45:16.150073 TX OE : NO K
6025 23:45:16.150184 All Pass.
6026 23:45:16.150279
6027 23:45:16.153491 DramC Write-DBI off
6028 23:45:16.153592 PER_BANK_REFRESH: Hybrid Mode
6029 23:45:16.156647 TX_TRACKING: ON
6030 23:45:16.163463 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6031 23:45:16.169581 [FAST_K] Save calibration result to emmc
6032 23:45:16.172901 dramc_set_vcore_voltage set vcore to 650000
6033 23:45:16.172998 Read voltage for 400, 6
6034 23:45:16.176121 Vio18 = 0
6035 23:45:16.176247 Vcore = 650000
6036 23:45:16.176359 Vdram = 0
6037 23:45:16.179539 Vddq = 0
6038 23:45:16.179665 Vmddr = 0
6039 23:45:16.183117 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6040 23:45:16.189684 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6041 23:45:16.196423 MEM_TYPE=3, freq_sel=20
6042 23:45:16.196725 sv_algorithm_assistance_LP4_800
6043 23:45:16.199594 ============ PULL DRAM RESETB DOWN ============
6044 23:45:16.202902 ========== PULL DRAM RESETB DOWN end =========
6045 23:45:16.209315 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6046 23:45:16.212607 ===================================
6047 23:45:16.212683 LPDDR4 DRAM CONFIGURATION
6048 23:45:16.216075 ===================================
6049 23:45:16.219492 EX_ROW_EN[0] = 0x0
6050 23:45:16.219593 EX_ROW_EN[1] = 0x0
6051 23:45:16.222845 LP4Y_EN = 0x0
6052 23:45:16.222955 WORK_FSP = 0x0
6053 23:45:16.225938 WL = 0x2
6054 23:45:16.229641 RL = 0x2
6055 23:45:16.229746 BL = 0x2
6056 23:45:16.232757 RPST = 0x0
6057 23:45:16.232835 RD_PRE = 0x0
6058 23:45:16.236119 WR_PRE = 0x1
6059 23:45:16.236216 WR_PST = 0x0
6060 23:45:16.239125 DBI_WR = 0x0
6061 23:45:16.239200 DBI_RD = 0x0
6062 23:45:16.242809 OTF = 0x1
6063 23:45:16.245704 ===================================
6064 23:45:16.249040 ===================================
6065 23:45:16.249143 ANA top config
6066 23:45:16.252755 ===================================
6067 23:45:16.255795 DLL_ASYNC_EN = 0
6068 23:45:16.259032 ALL_SLAVE_EN = 1
6069 23:45:16.259111 NEW_RANK_MODE = 1
6070 23:45:16.262380 DLL_IDLE_MODE = 1
6071 23:45:16.265478 LP45_APHY_COMB_EN = 1
6072 23:45:16.269022 TX_ODT_DIS = 1
6073 23:45:16.272421 NEW_8X_MODE = 1
6074 23:45:16.275725 ===================================
6075 23:45:16.275829 ===================================
6076 23:45:16.279139 data_rate = 800
6077 23:45:16.282327 CKR = 1
6078 23:45:16.285709 DQ_P2S_RATIO = 4
6079 23:45:16.289136 ===================================
6080 23:45:16.291949 CA_P2S_RATIO = 4
6081 23:45:16.295652 DQ_CA_OPEN = 0
6082 23:45:16.298818 DQ_SEMI_OPEN = 1
6083 23:45:16.298927 CA_SEMI_OPEN = 1
6084 23:45:16.302082 CA_FULL_RATE = 0
6085 23:45:16.305366 DQ_CKDIV4_EN = 0
6086 23:45:16.308583 CA_CKDIV4_EN = 1
6087 23:45:16.311887 CA_PREDIV_EN = 0
6088 23:45:16.315332 PH8_DLY = 0
6089 23:45:16.315442 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6090 23:45:16.318687 DQ_AAMCK_DIV = 0
6091 23:45:16.321598 CA_AAMCK_DIV = 0
6092 23:45:16.325339 CA_ADMCK_DIV = 4
6093 23:45:16.328184 DQ_TRACK_CA_EN = 0
6094 23:45:16.332172 CA_PICK = 800
6095 23:45:16.335223 CA_MCKIO = 400
6096 23:45:16.335331 MCKIO_SEMI = 400
6097 23:45:16.338466 PLL_FREQ = 3016
6098 23:45:16.341454 DQ_UI_PI_RATIO = 32
6099 23:45:16.344860 CA_UI_PI_RATIO = 32
6100 23:45:16.348254 ===================================
6101 23:45:16.351442 ===================================
6102 23:45:16.354820 memory_type:LPDDR4
6103 23:45:16.354929 GP_NUM : 10
6104 23:45:16.358172 SRAM_EN : 1
6105 23:45:16.361278 MD32_EN : 0
6106 23:45:16.364862 ===================================
6107 23:45:16.364948 [ANA_INIT] >>>>>>>>>>>>>>
6108 23:45:16.368193 <<<<<< [CONFIGURE PHASE]: ANA_TX
6109 23:45:16.371507 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6110 23:45:16.374722 ===================================
6111 23:45:16.377774 data_rate = 800,PCW = 0X7400
6112 23:45:16.381169 ===================================
6113 23:45:16.384435 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6114 23:45:16.391051 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6115 23:45:16.401088 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6116 23:45:16.407693 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6117 23:45:16.411007 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6118 23:45:16.414334 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6119 23:45:16.414414 [ANA_INIT] flow start
6120 23:45:16.417696 [ANA_INIT] PLL >>>>>>>>
6121 23:45:16.421105 [ANA_INIT] PLL <<<<<<<<
6122 23:45:16.421186 [ANA_INIT] MIDPI >>>>>>>>
6123 23:45:16.424471 [ANA_INIT] MIDPI <<<<<<<<
6124 23:45:16.427408 [ANA_INIT] DLL >>>>>>>>
6125 23:45:16.427486 [ANA_INIT] flow end
6126 23:45:16.434176 ============ LP4 DIFF to SE enter ============
6127 23:45:16.437473 ============ LP4 DIFF to SE exit ============
6128 23:45:16.440833 [ANA_INIT] <<<<<<<<<<<<<
6129 23:45:16.444316 [Flow] Enable top DCM control >>>>>
6130 23:45:16.447759 [Flow] Enable top DCM control <<<<<
6131 23:45:16.447842 Enable DLL master slave shuffle
6132 23:45:16.454309 ==============================================================
6133 23:45:16.457461 Gating Mode config
6134 23:45:16.461075 ==============================================================
6135 23:45:16.463865 Config description:
6136 23:45:16.473814 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6137 23:45:16.480542 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6138 23:45:16.483704 SELPH_MODE 0: By rank 1: By Phase
6139 23:45:16.490752 ==============================================================
6140 23:45:16.494011 GAT_TRACK_EN = 0
6141 23:45:16.497377 RX_GATING_MODE = 2
6142 23:45:16.500801 RX_GATING_TRACK_MODE = 2
6143 23:45:16.503629 SELPH_MODE = 1
6144 23:45:16.503711 PICG_EARLY_EN = 1
6145 23:45:16.507328 VALID_LAT_VALUE = 1
6146 23:45:16.514050 ==============================================================
6147 23:45:16.517061 Enter into Gating configuration >>>>
6148 23:45:16.520187 Exit from Gating configuration <<<<
6149 23:45:16.523629 Enter into DVFS_PRE_config >>>>>
6150 23:45:16.533715 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6151 23:45:16.537107 Exit from DVFS_PRE_config <<<<<
6152 23:45:16.540472 Enter into PICG configuration >>>>
6153 23:45:16.543724 Exit from PICG configuration <<<<
6154 23:45:16.547184 [RX_INPUT] configuration >>>>>
6155 23:45:16.550465 [RX_INPUT] configuration <<<<<
6156 23:45:16.553593 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6157 23:45:16.560418 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6158 23:45:16.566832 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6159 23:45:16.573805 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6160 23:45:16.580027 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6161 23:45:16.583229 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6162 23:45:16.589803 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6163 23:45:16.593286 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6164 23:45:16.596683 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6165 23:45:16.599909 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6166 23:45:16.606372 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6167 23:45:16.610221 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6168 23:45:16.613020 ===================================
6169 23:45:16.616431 LPDDR4 DRAM CONFIGURATION
6170 23:45:16.619814 ===================================
6171 23:45:16.619934 EX_ROW_EN[0] = 0x0
6172 23:45:16.623054 EX_ROW_EN[1] = 0x0
6173 23:45:16.623138 LP4Y_EN = 0x0
6174 23:45:16.626275 WORK_FSP = 0x0
6175 23:45:16.626360 WL = 0x2
6176 23:45:16.629574 RL = 0x2
6177 23:45:16.632955 BL = 0x2
6178 23:45:16.633034 RPST = 0x0
6179 23:45:16.636332 RD_PRE = 0x0
6180 23:45:16.636405 WR_PRE = 0x1
6181 23:45:16.639639 WR_PST = 0x0
6182 23:45:16.639741 DBI_WR = 0x0
6183 23:45:16.643006 DBI_RD = 0x0
6184 23:45:16.643082 OTF = 0x1
6185 23:45:16.646367 ===================================
6186 23:45:16.649838 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6187 23:45:16.656165 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6188 23:45:16.659768 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6189 23:45:16.663201 ===================================
6190 23:45:16.666017 LPDDR4 DRAM CONFIGURATION
6191 23:45:16.669418 ===================================
6192 23:45:16.669523 EX_ROW_EN[0] = 0x10
6193 23:45:16.672702 EX_ROW_EN[1] = 0x0
6194 23:45:16.672802 LP4Y_EN = 0x0
6195 23:45:16.675802 WORK_FSP = 0x0
6196 23:45:16.675881 WL = 0x2
6197 23:45:16.679340 RL = 0x2
6198 23:45:16.679449 BL = 0x2
6199 23:45:16.682966 RPST = 0x0
6200 23:45:16.686000 RD_PRE = 0x0
6201 23:45:16.686101 WR_PRE = 0x1
6202 23:45:16.689222 WR_PST = 0x0
6203 23:45:16.689305 DBI_WR = 0x0
6204 23:45:16.692641 DBI_RD = 0x0
6205 23:45:16.692725 OTF = 0x1
6206 23:45:16.696090 ===================================
6207 23:45:16.702375 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6208 23:45:16.706264 nWR fixed to 30
6209 23:45:16.709642 [ModeRegInit_LP4] CH0 RK0
6210 23:45:16.709723 [ModeRegInit_LP4] CH0 RK1
6211 23:45:16.713272 [ModeRegInit_LP4] CH1 RK0
6212 23:45:16.716217 [ModeRegInit_LP4] CH1 RK1
6213 23:45:16.716322 match AC timing 19
6214 23:45:16.722899 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6215 23:45:16.726211 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6216 23:45:16.729574 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6217 23:45:16.736124 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6218 23:45:16.739628 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6219 23:45:16.739708 ==
6220 23:45:16.742902 Dram Type= 6, Freq= 0, CH_0, rank 0
6221 23:45:16.746350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6222 23:45:16.746437 ==
6223 23:45:16.752614 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6224 23:45:16.759319 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6225 23:45:16.762553 [CA 0] Center 36 (8~64) winsize 57
6226 23:45:16.765973 [CA 1] Center 36 (8~64) winsize 57
6227 23:45:16.769180 [CA 2] Center 36 (8~64) winsize 57
6228 23:45:16.772584 [CA 3] Center 36 (8~64) winsize 57
6229 23:45:16.772670 [CA 4] Center 36 (8~64) winsize 57
6230 23:45:16.776055 [CA 5] Center 36 (8~64) winsize 57
6231 23:45:16.776139
6232 23:45:16.782431 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6233 23:45:16.782519
6234 23:45:16.786183 [CATrainingPosCal] consider 1 rank data
6235 23:45:16.789003 u2DelayCellTimex100 = 270/100 ps
6236 23:45:16.792377 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6237 23:45:16.796021 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6238 23:45:16.798906 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6239 23:45:16.802412 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6240 23:45:16.805997 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6241 23:45:16.809497 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6242 23:45:16.809580
6243 23:45:16.812491 CA PerBit enable=1, Macro0, CA PI delay=36
6244 23:45:16.812573
6245 23:45:16.815565 [CBTSetCACLKResult] CA Dly = 36
6246 23:45:16.819676 CS Dly: 1 (0~32)
6247 23:45:16.819772 ==
6248 23:45:16.822618 Dram Type= 6, Freq= 0, CH_0, rank 1
6249 23:45:16.825591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6250 23:45:16.825669 ==
6251 23:45:16.832218 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6252 23:45:16.835557 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6253 23:45:16.838821 [CA 0] Center 36 (8~64) winsize 57
6254 23:45:16.842147 [CA 1] Center 36 (8~64) winsize 57
6255 23:45:16.845677 [CA 2] Center 36 (8~64) winsize 57
6256 23:45:16.848928 [CA 3] Center 36 (8~64) winsize 57
6257 23:45:16.852301 [CA 4] Center 36 (8~64) winsize 57
6258 23:45:16.855627 [CA 5] Center 36 (8~64) winsize 57
6259 23:45:16.855702
6260 23:45:16.859053 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6261 23:45:16.859129
6262 23:45:16.862397 [CATrainingPosCal] consider 2 rank data
6263 23:45:16.865217 u2DelayCellTimex100 = 270/100 ps
6264 23:45:16.868787 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6265 23:45:16.872456 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6266 23:45:16.878643 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6267 23:45:16.882099 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6268 23:45:16.885277 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6269 23:45:16.889004 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6270 23:45:16.889089
6271 23:45:16.892261 CA PerBit enable=1, Macro0, CA PI delay=36
6272 23:45:16.892340
6273 23:45:16.895561 [CBTSetCACLKResult] CA Dly = 36
6274 23:45:16.895636 CS Dly: 1 (0~32)
6275 23:45:16.895709
6276 23:45:16.898816 ----->DramcWriteLeveling(PI) begin...
6277 23:45:16.902404 ==
6278 23:45:16.902495 Dram Type= 6, Freq= 0, CH_0, rank 0
6279 23:45:16.908904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6280 23:45:16.908992 ==
6281 23:45:16.911934 Write leveling (Byte 0): 40 => 8
6282 23:45:16.915280 Write leveling (Byte 1): 40 => 8
6283 23:45:16.915389 DramcWriteLeveling(PI) end<-----
6284 23:45:16.918923
6285 23:45:16.919008 ==
6286 23:45:16.922138 Dram Type= 6, Freq= 0, CH_0, rank 0
6287 23:45:16.925175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6288 23:45:16.925261 ==
6289 23:45:16.928810 [Gating] SW mode calibration
6290 23:45:16.934935 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6291 23:45:16.938481 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6292 23:45:16.945058 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6293 23:45:16.948752 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6294 23:45:16.951531 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6295 23:45:16.958351 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6296 23:45:16.961771 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6297 23:45:16.965038 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6298 23:45:16.971805 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6299 23:45:16.975095 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6300 23:45:16.978448 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6301 23:45:16.981671 Total UI for P1: 0, mck2ui 16
6302 23:45:16.985048 best dqsien dly found for B0: ( 0, 14, 24)
6303 23:45:16.988351 Total UI for P1: 0, mck2ui 16
6304 23:45:16.991505 best dqsien dly found for B1: ( 0, 14, 24)
6305 23:45:16.994730 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6306 23:45:17.001524 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6307 23:45:17.001665
6308 23:45:17.004819 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6309 23:45:17.008181 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6310 23:45:17.011523 [Gating] SW calibration Done
6311 23:45:17.011658 ==
6312 23:45:17.014822 Dram Type= 6, Freq= 0, CH_0, rank 0
6313 23:45:17.018009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6314 23:45:17.018112 ==
6315 23:45:17.021159 RX Vref Scan: 0
6316 23:45:17.021235
6317 23:45:17.021297 RX Vref 0 -> 0, step: 1
6318 23:45:17.021364
6319 23:45:17.024669 RX Delay -410 -> 252, step: 16
6320 23:45:17.027624 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6321 23:45:17.034842 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6322 23:45:17.037680 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6323 23:45:17.040806 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6324 23:45:17.044322 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6325 23:45:17.051233 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6326 23:45:17.054487 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6327 23:45:17.057379 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6328 23:45:17.061138 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6329 23:45:17.067471 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6330 23:45:17.070715 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6331 23:45:17.074099 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6332 23:45:17.080694 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6333 23:45:17.084197 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6334 23:45:17.087348 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6335 23:45:17.090738 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6336 23:45:17.090823 ==
6337 23:45:17.094026 Dram Type= 6, Freq= 0, CH_0, rank 0
6338 23:45:17.100434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6339 23:45:17.100548 ==
6340 23:45:17.100654 DQS Delay:
6341 23:45:17.103974 DQS0 = 59, DQS1 = 59
6342 23:45:17.104085 DQM Delay:
6343 23:45:17.107243 DQM0 = 18, DQM1 = 10
6344 23:45:17.107354 DQ Delay:
6345 23:45:17.110705 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6346 23:45:17.113586 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6347 23:45:17.116892 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6348 23:45:17.120226 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6349 23:45:17.120339
6350 23:45:17.120436
6351 23:45:17.120536 ==
6352 23:45:17.123566 Dram Type= 6, Freq= 0, CH_0, rank 0
6353 23:45:17.126867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6354 23:45:17.126981 ==
6355 23:45:17.127081
6356 23:45:17.127173
6357 23:45:17.130508 TX Vref Scan disable
6358 23:45:17.130619 == TX Byte 0 ==
6359 23:45:17.137234 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6360 23:45:17.140612 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6361 23:45:17.140722 == TX Byte 1 ==
6362 23:45:17.147224 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6363 23:45:17.150362 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6364 23:45:17.150480 ==
6365 23:45:17.153639 Dram Type= 6, Freq= 0, CH_0, rank 0
6366 23:45:17.156950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6367 23:45:17.157028 ==
6368 23:45:17.157099
6369 23:45:17.157178
6370 23:45:17.160034 TX Vref Scan disable
6371 23:45:17.160109 == TX Byte 0 ==
6372 23:45:17.166586 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6373 23:45:17.170085 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6374 23:45:17.170201 == TX Byte 1 ==
6375 23:45:17.176815 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6376 23:45:17.180097 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6377 23:45:17.180185
6378 23:45:17.180249 [DATLAT]
6379 23:45:17.183407 Freq=400, CH0 RK0
6380 23:45:17.183481
6381 23:45:17.183543 DATLAT Default: 0xf
6382 23:45:17.186276 0, 0xFFFF, sum = 0
6383 23:45:17.186354 1, 0xFFFF, sum = 0
6384 23:45:17.190056 2, 0xFFFF, sum = 0
6385 23:45:17.190151 3, 0xFFFF, sum = 0
6386 23:45:17.192857 4, 0xFFFF, sum = 0
6387 23:45:17.192938 5, 0xFFFF, sum = 0
6388 23:45:17.196164 6, 0xFFFF, sum = 0
6389 23:45:17.199790 7, 0xFFFF, sum = 0
6390 23:45:17.199907 8, 0xFFFF, sum = 0
6391 23:45:17.202966 9, 0xFFFF, sum = 0
6392 23:45:17.203084 10, 0xFFFF, sum = 0
6393 23:45:17.206377 11, 0xFFFF, sum = 0
6394 23:45:17.206488 12, 0xFFFF, sum = 0
6395 23:45:17.209634 13, 0x0, sum = 1
6396 23:45:17.209717 14, 0x0, sum = 2
6397 23:45:17.213212 15, 0x0, sum = 3
6398 23:45:17.213291 16, 0x0, sum = 4
6399 23:45:17.216495 best_step = 14
6400 23:45:17.216599
6401 23:45:17.216672 ==
6402 23:45:17.219356 Dram Type= 6, Freq= 0, CH_0, rank 0
6403 23:45:17.222644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6404 23:45:17.222757 ==
6405 23:45:17.222851 RX Vref Scan: 1
6406 23:45:17.222946
6407 23:45:17.226027 RX Vref 0 -> 0, step: 1
6408 23:45:17.226140
6409 23:45:17.229389 RX Delay -359 -> 252, step: 8
6410 23:45:17.229501
6411 23:45:17.232724 Set Vref, RX VrefLevel [Byte0]: 62
6412 23:45:17.235871 [Byte1]: 47
6413 23:45:17.240001
6414 23:45:17.240115 Final RX Vref Byte 0 = 62 to rank0
6415 23:45:17.243221 Final RX Vref Byte 1 = 47 to rank0
6416 23:45:17.246577 Final RX Vref Byte 0 = 62 to rank1
6417 23:45:17.250269 Final RX Vref Byte 1 = 47 to rank1==
6418 23:45:17.253242 Dram Type= 6, Freq= 0, CH_0, rank 0
6419 23:45:17.260234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6420 23:45:17.260354 ==
6421 23:45:17.260452 DQS Delay:
6422 23:45:17.263418 DQS0 = 60, DQS1 = 68
6423 23:45:17.263534 DQM Delay:
6424 23:45:17.263632 DQM0 = 14, DQM1 = 13
6425 23:45:17.266821 DQ Delay:
6426 23:45:17.270201 DQ0 =12, DQ1 =16, DQ2 =12, DQ3 =12
6427 23:45:17.273161 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6428 23:45:17.273279 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6429 23:45:17.279838 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =20
6430 23:45:17.279953
6431 23:45:17.280053
6432 23:45:17.286531 [DQSOSCAuto] RK0, (LSB)MR18= 0x8381, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6433 23:45:17.289858 CH0 RK0: MR19=C0C, MR18=8381
6434 23:45:17.296513 CH0_RK0: MR19=0xC0C, MR18=0x8381, DQSOSC=393, MR23=63, INC=382, DEC=254
6435 23:45:17.296622 ==
6436 23:45:17.299890 Dram Type= 6, Freq= 0, CH_0, rank 1
6437 23:45:17.303189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6438 23:45:17.303276 ==
6439 23:45:17.306302 [Gating] SW mode calibration
6440 23:45:17.312702 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6441 23:45:17.319624 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6442 23:45:17.322964 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6443 23:45:17.326232 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6444 23:45:17.333076 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6445 23:45:17.336368 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6446 23:45:17.339841 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6447 23:45:17.346147 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6448 23:45:17.349250 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6449 23:45:17.352622 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6450 23:45:17.359286 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6451 23:45:17.359399 Total UI for P1: 0, mck2ui 16
6452 23:45:17.366098 best dqsien dly found for B0: ( 0, 14, 24)
6453 23:45:17.366211 Total UI for P1: 0, mck2ui 16
6454 23:45:17.372329 best dqsien dly found for B1: ( 0, 14, 24)
6455 23:45:17.375924 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6456 23:45:17.379034 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6457 23:45:17.379150
6458 23:45:17.382515 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6459 23:45:17.385571 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6460 23:45:17.389165 [Gating] SW calibration Done
6461 23:45:17.389277 ==
6462 23:45:17.392542 Dram Type= 6, Freq= 0, CH_0, rank 1
6463 23:45:17.395929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6464 23:45:17.396017 ==
6465 23:45:17.398683 RX Vref Scan: 0
6466 23:45:17.398783
6467 23:45:17.398876 RX Vref 0 -> 0, step: 1
6468 23:45:17.398966
6469 23:45:17.402735 RX Delay -410 -> 252, step: 16
6470 23:45:17.408728 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6471 23:45:17.412297 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6472 23:45:17.415337 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6473 23:45:17.418690 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6474 23:45:17.425423 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6475 23:45:17.428934 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6476 23:45:17.432214 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6477 23:45:17.435078 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6478 23:45:17.441791 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6479 23:45:17.445265 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6480 23:45:17.448807 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6481 23:45:17.452045 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6482 23:45:17.458517 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6483 23:45:17.461902 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6484 23:45:17.465212 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6485 23:45:17.471519 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6486 23:45:17.471600 ==
6487 23:45:17.474815 Dram Type= 6, Freq= 0, CH_0, rank 1
6488 23:45:17.478435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6489 23:45:17.478515 ==
6490 23:45:17.478585 DQS Delay:
6491 23:45:17.481636 DQS0 = 59, DQS1 = 59
6492 23:45:17.481705 DQM Delay:
6493 23:45:17.485001 DQM0 = 16, DQM1 = 10
6494 23:45:17.485076 DQ Delay:
6495 23:45:17.488366 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6496 23:45:17.491883 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6497 23:45:17.495034 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6498 23:45:17.497964 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6499 23:45:17.498094
6500 23:45:17.498209
6501 23:45:17.498324 ==
6502 23:45:17.501642 Dram Type= 6, Freq= 0, CH_0, rank 1
6503 23:45:17.505085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6504 23:45:17.505214 ==
6505 23:45:17.505332
6506 23:45:17.505444
6507 23:45:17.507953 TX Vref Scan disable
6508 23:45:17.511624 == TX Byte 0 ==
6509 23:45:17.514587 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6510 23:45:17.518125 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6511 23:45:17.518239 == TX Byte 1 ==
6512 23:45:17.524815 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6513 23:45:17.528151 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6514 23:45:17.528238 ==
6515 23:45:17.531536 Dram Type= 6, Freq= 0, CH_0, rank 1
6516 23:45:17.534393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6517 23:45:17.534478 ==
6518 23:45:17.534544
6519 23:45:17.537877
6520 23:45:17.537961 TX Vref Scan disable
6521 23:45:17.541332 == TX Byte 0 ==
6522 23:45:17.544570 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6523 23:45:17.547966 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6524 23:45:17.551312 == TX Byte 1 ==
6525 23:45:17.554705 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6526 23:45:17.558011 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6527 23:45:17.558097
6528 23:45:17.558164 [DATLAT]
6529 23:45:17.560816 Freq=400, CH0 RK1
6530 23:45:17.560900
6531 23:45:17.564422 DATLAT Default: 0xe
6532 23:45:17.564546 0, 0xFFFF, sum = 0
6533 23:45:17.567656 1, 0xFFFF, sum = 0
6534 23:45:17.567781 2, 0xFFFF, sum = 0
6535 23:45:17.570598 3, 0xFFFF, sum = 0
6536 23:45:17.570709 4, 0xFFFF, sum = 0
6537 23:45:17.574202 5, 0xFFFF, sum = 0
6538 23:45:17.574307 6, 0xFFFF, sum = 0
6539 23:45:17.577132 7, 0xFFFF, sum = 0
6540 23:45:17.577219 8, 0xFFFF, sum = 0
6541 23:45:17.580489 9, 0xFFFF, sum = 0
6542 23:45:17.580605 10, 0xFFFF, sum = 0
6543 23:45:17.583861 11, 0xFFFF, sum = 0
6544 23:45:17.583947 12, 0xFFFF, sum = 0
6545 23:45:17.587033 13, 0x0, sum = 1
6546 23:45:17.587135 14, 0x0, sum = 2
6547 23:45:17.590484 15, 0x0, sum = 3
6548 23:45:17.590605 16, 0x0, sum = 4
6549 23:45:17.593767 best_step = 14
6550 23:45:17.593900
6551 23:45:17.594015 ==
6552 23:45:17.596999 Dram Type= 6, Freq= 0, CH_0, rank 1
6553 23:45:17.600419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6554 23:45:17.600543 ==
6555 23:45:17.603751 RX Vref Scan: 0
6556 23:45:17.603857
6557 23:45:17.603952 RX Vref 0 -> 0, step: 1
6558 23:45:17.604041
6559 23:45:17.606864 RX Delay -359 -> 252, step: 8
6560 23:45:17.615143 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6561 23:45:17.618427 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6562 23:45:17.621654 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6563 23:45:17.625278 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6564 23:45:17.631879 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6565 23:45:17.635326 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6566 23:45:17.638111 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6567 23:45:17.641395 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6568 23:45:17.648265 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6569 23:45:17.651585 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6570 23:45:17.654991 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6571 23:45:17.661260 iDelay=217, Bit 11, Center -64 (-311 ~ 184) 496
6572 23:45:17.664554 iDelay=217, Bit 12, Center -48 (-295 ~ 200) 496
6573 23:45:17.668032 iDelay=217, Bit 13, Center -48 (-295 ~ 200) 496
6574 23:45:17.671298 iDelay=217, Bit 14, Center -48 (-295 ~ 200) 496
6575 23:45:17.678187 iDelay=217, Bit 15, Center -48 (-295 ~ 200) 496
6576 23:45:17.678279 ==
6577 23:45:17.681247 Dram Type= 6, Freq= 0, CH_0, rank 1
6578 23:45:17.684496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6579 23:45:17.684603 ==
6580 23:45:17.684673 DQS Delay:
6581 23:45:17.687873 DQS0 = 60, DQS1 = 72
6582 23:45:17.687965 DQM Delay:
6583 23:45:17.691392 DQM0 = 11, DQM1 = 16
6584 23:45:17.691521 DQ Delay:
6585 23:45:17.694529 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6586 23:45:17.697581 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6587 23:45:17.701108 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =8
6588 23:45:17.704271 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6589 23:45:17.704384
6590 23:45:17.704485
6591 23:45:17.710825 [DQSOSCAuto] RK1, (LSB)MR18= 0xcb80, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 384 ps
6592 23:45:17.714054 CH0 RK1: MR19=C0C, MR18=CB80
6593 23:45:17.720658 CH0_RK1: MR19=0xC0C, MR18=0xCB80, DQSOSC=384, MR23=63, INC=400, DEC=267
6594 23:45:17.724378 [RxdqsGatingPostProcess] freq 400
6595 23:45:17.730929 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6596 23:45:17.733968 best DQS0 dly(2T, 0.5T) = (0, 10)
6597 23:45:17.737679 best DQS1 dly(2T, 0.5T) = (0, 10)
6598 23:45:17.740531 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6599 23:45:17.740632 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6600 23:45:17.743940 best DQS0 dly(2T, 0.5T) = (0, 10)
6601 23:45:17.747277 best DQS1 dly(2T, 0.5T) = (0, 10)
6602 23:45:17.750859 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6603 23:45:17.753582 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6604 23:45:17.757106 Pre-setting of DQS Precalculation
6605 23:45:17.763787 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6606 23:45:17.763923 ==
6607 23:45:17.767209 Dram Type= 6, Freq= 0, CH_1, rank 0
6608 23:45:17.770579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6609 23:45:17.770711 ==
6610 23:45:17.776841 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6611 23:45:17.783247 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6612 23:45:17.786992 [CA 0] Center 36 (8~64) winsize 57
6613 23:45:17.787104 [CA 1] Center 36 (8~64) winsize 57
6614 23:45:17.790155 [CA 2] Center 36 (8~64) winsize 57
6615 23:45:17.793525 [CA 3] Center 36 (8~64) winsize 57
6616 23:45:17.796885 [CA 4] Center 36 (8~64) winsize 57
6617 23:45:17.800168 [CA 5] Center 36 (8~64) winsize 57
6618 23:45:17.800253
6619 23:45:17.803221 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6620 23:45:17.803332
6621 23:45:17.810369 [CATrainingPosCal] consider 1 rank data
6622 23:45:17.810461 u2DelayCellTimex100 = 270/100 ps
6623 23:45:17.816856 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6624 23:45:17.820244 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6625 23:45:17.823333 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6626 23:45:17.826418 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6627 23:45:17.829607 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6628 23:45:17.833442 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6629 23:45:17.833589
6630 23:45:17.836289 CA PerBit enable=1, Macro0, CA PI delay=36
6631 23:45:17.836412
6632 23:45:17.839961 [CBTSetCACLKResult] CA Dly = 36
6633 23:45:17.843219 CS Dly: 1 (0~32)
6634 23:45:17.843375 ==
6635 23:45:17.846201 Dram Type= 6, Freq= 0, CH_1, rank 1
6636 23:45:17.849356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6637 23:45:17.849498 ==
6638 23:45:17.856327 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6639 23:45:17.859699 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6640 23:45:17.862997 [CA 0] Center 36 (8~64) winsize 57
6641 23:45:17.865909 [CA 1] Center 36 (8~64) winsize 57
6642 23:45:17.869374 [CA 2] Center 36 (8~64) winsize 57
6643 23:45:17.872524 [CA 3] Center 36 (8~64) winsize 57
6644 23:45:17.875953 [CA 4] Center 36 (8~64) winsize 57
6645 23:45:17.879286 [CA 5] Center 36 (8~64) winsize 57
6646 23:45:17.879357
6647 23:45:17.882700 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6648 23:45:17.882773
6649 23:45:17.886034 [CATrainingPosCal] consider 2 rank data
6650 23:45:17.889260 u2DelayCellTimex100 = 270/100 ps
6651 23:45:17.892552 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6652 23:45:17.895801 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6653 23:45:17.902225 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6654 23:45:17.905553 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6655 23:45:17.908822 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6656 23:45:17.912455 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6657 23:45:17.912562
6658 23:45:17.915788 CA PerBit enable=1, Macro0, CA PI delay=36
6659 23:45:17.915890
6660 23:45:17.918942 [CBTSetCACLKResult] CA Dly = 36
6661 23:45:17.919043 CS Dly: 1 (0~32)
6662 23:45:17.919146
6663 23:45:17.921962 ----->DramcWriteLeveling(PI) begin...
6664 23:45:17.925444 ==
6665 23:45:17.928786 Dram Type= 6, Freq= 0, CH_1, rank 0
6666 23:45:17.932369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6667 23:45:17.932475 ==
6668 23:45:17.935553 Write leveling (Byte 0): 40 => 8
6669 23:45:17.938919 Write leveling (Byte 1): 40 => 8
6670 23:45:17.941995 DramcWriteLeveling(PI) end<-----
6671 23:45:17.942080
6672 23:45:17.942165 ==
6673 23:45:17.945528 Dram Type= 6, Freq= 0, CH_1, rank 0
6674 23:45:17.949282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6675 23:45:17.949363 ==
6676 23:45:17.951891 [Gating] SW mode calibration
6677 23:45:17.958973 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6678 23:45:17.962266 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6679 23:45:17.969092 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6680 23:45:17.971960 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6681 23:45:17.975271 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6682 23:45:17.981959 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6683 23:45:17.985359 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6684 23:45:17.988783 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6685 23:45:17.995214 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6686 23:45:17.998553 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6687 23:45:18.001863 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6688 23:45:18.005026 Total UI for P1: 0, mck2ui 16
6689 23:45:18.008857 best dqsien dly found for B0: ( 0, 14, 24)
6690 23:45:18.012149 Total UI for P1: 0, mck2ui 16
6691 23:45:18.014985 best dqsien dly found for B1: ( 0, 14, 24)
6692 23:45:18.018619 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6693 23:45:18.021777 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6694 23:45:18.025104
6695 23:45:18.028352 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6696 23:45:18.031612 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6697 23:45:18.035092 [Gating] SW calibration Done
6698 23:45:18.035216 ==
6699 23:45:18.038173 Dram Type= 6, Freq= 0, CH_1, rank 0
6700 23:45:18.041820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6701 23:45:18.041937 ==
6702 23:45:18.042002 RX Vref Scan: 0
6703 23:45:18.042093
6704 23:45:18.045112 RX Vref 0 -> 0, step: 1
6705 23:45:18.045227
6706 23:45:18.048168 RX Delay -410 -> 252, step: 16
6707 23:45:18.051521 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6708 23:45:18.058386 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6709 23:45:18.061524 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6710 23:45:18.064678 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6711 23:45:18.067999 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6712 23:45:18.074861 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6713 23:45:18.078035 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6714 23:45:18.081407 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6715 23:45:18.084815 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6716 23:45:18.091648 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6717 23:45:18.095022 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6718 23:45:18.098298 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6719 23:45:18.101718 iDelay=230, Bit 12, Center -35 (-298 ~ 229) 528
6720 23:45:18.108117 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6721 23:45:18.111396 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6722 23:45:18.114556 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6723 23:45:18.114641 ==
6724 23:45:18.118261 Dram Type= 6, Freq= 0, CH_1, rank 0
6725 23:45:18.124726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6726 23:45:18.124815 ==
6727 23:45:18.124882 DQS Delay:
6728 23:45:18.127816 DQS0 = 51, DQS1 = 67
6729 23:45:18.127904 DQM Delay:
6730 23:45:18.127970 DQM0 = 13, DQM1 = 18
6731 23:45:18.131218 DQ Delay:
6732 23:45:18.134353 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6733 23:45:18.134439 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6734 23:45:18.137841 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6735 23:45:18.141242 DQ12 =32, DQ13 =24, DQ14 =24, DQ15 =24
6736 23:45:18.141327
6737 23:45:18.144422
6738 23:45:18.144505 ==
6739 23:45:18.147809 Dram Type= 6, Freq= 0, CH_1, rank 0
6740 23:45:18.151374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6741 23:45:18.151506 ==
6742 23:45:18.151622
6743 23:45:18.151735
6744 23:45:18.154401 TX Vref Scan disable
6745 23:45:18.154528 == TX Byte 0 ==
6746 23:45:18.157657 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6747 23:45:18.164462 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6748 23:45:18.164581 == TX Byte 1 ==
6749 23:45:18.167838 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6750 23:45:18.174157 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6751 23:45:18.174239 ==
6752 23:45:18.177741 Dram Type= 6, Freq= 0, CH_1, rank 0
6753 23:45:18.181119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6754 23:45:18.181203 ==
6755 23:45:18.181299
6756 23:45:18.181390
6757 23:45:18.184624 TX Vref Scan disable
6758 23:45:18.184719 == TX Byte 0 ==
6759 23:45:18.187813 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6760 23:45:18.194099 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6761 23:45:18.194216 == TX Byte 1 ==
6762 23:45:18.197426 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6763 23:45:18.204120 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6764 23:45:18.204239
6765 23:45:18.204340 [DATLAT]
6766 23:45:18.204442 Freq=400, CH1 RK0
6767 23:45:18.207371
6768 23:45:18.207472 DATLAT Default: 0xf
6769 23:45:18.210787 0, 0xFFFF, sum = 0
6770 23:45:18.210891 1, 0xFFFF, sum = 0
6771 23:45:18.214088 2, 0xFFFF, sum = 0
6772 23:45:18.214193 3, 0xFFFF, sum = 0
6773 23:45:18.217506 4, 0xFFFF, sum = 0
6774 23:45:18.217612 5, 0xFFFF, sum = 0
6775 23:45:18.220696 6, 0xFFFF, sum = 0
6776 23:45:18.220804 7, 0xFFFF, sum = 0
6777 23:45:18.223812 8, 0xFFFF, sum = 0
6778 23:45:18.223918 9, 0xFFFF, sum = 0
6779 23:45:18.227063 10, 0xFFFF, sum = 0
6780 23:45:18.227194 11, 0xFFFF, sum = 0
6781 23:45:18.230729 12, 0xFFFF, sum = 0
6782 23:45:18.230858 13, 0x0, sum = 1
6783 23:45:18.233809 14, 0x0, sum = 2
6784 23:45:18.233897 15, 0x0, sum = 3
6785 23:45:18.237092 16, 0x0, sum = 4
6786 23:45:18.237172 best_step = 14
6787 23:45:18.237255
6788 23:45:18.237339 ==
6789 23:45:18.240877 Dram Type= 6, Freq= 0, CH_1, rank 0
6790 23:45:18.246912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6791 23:45:18.246997 ==
6792 23:45:18.247091 RX Vref Scan: 1
6793 23:45:18.247192
6794 23:45:18.250381 RX Vref 0 -> 0, step: 1
6795 23:45:18.250466
6796 23:45:18.253726 RX Delay -375 -> 252, step: 8
6797 23:45:18.253817
6798 23:45:18.257243 Set Vref, RX VrefLevel [Byte0]: 56
6799 23:45:18.260501 [Byte1]: 48
6800 23:45:18.260614
6801 23:45:18.263691 Final RX Vref Byte 0 = 56 to rank0
6802 23:45:18.266959 Final RX Vref Byte 1 = 48 to rank0
6803 23:45:18.270295 Final RX Vref Byte 0 = 56 to rank1
6804 23:45:18.273646 Final RX Vref Byte 1 = 48 to rank1==
6805 23:45:18.277139 Dram Type= 6, Freq= 0, CH_1, rank 0
6806 23:45:18.280309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6807 23:45:18.283568 ==
6808 23:45:18.283690 DQS Delay:
6809 23:45:18.283793 DQS0 = 56, DQS1 = 68
6810 23:45:18.286850 DQM Delay:
6811 23:45:18.286950 DQM0 = 12, DQM1 = 14
6812 23:45:18.290452 DQ Delay:
6813 23:45:18.290565 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
6814 23:45:18.293547 DQ4 =12, DQ5 =20, DQ6 =24, DQ7 =8
6815 23:45:18.296836 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6816 23:45:18.300214 DQ12 =24, DQ13 =24, DQ14 =20, DQ15 =20
6817 23:45:18.300339
6818 23:45:18.300454
6819 23:45:18.310129 [DQSOSCAuto] RK0, (LSB)MR18= 0x5e73, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 397 ps
6820 23:45:18.313579 CH1 RK0: MR19=C0C, MR18=5E73
6821 23:45:18.320348 CH1_RK0: MR19=0xC0C, MR18=0x5E73, DQSOSC=395, MR23=63, INC=378, DEC=252
6822 23:45:18.320495 ==
6823 23:45:18.323614 Dram Type= 6, Freq= 0, CH_1, rank 1
6824 23:45:18.326881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6825 23:45:18.327001 ==
6826 23:45:18.329964 [Gating] SW mode calibration
6827 23:45:18.336710 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6828 23:45:18.340360 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6829 23:45:18.346618 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6830 23:45:18.350013 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6831 23:45:18.353455 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6832 23:45:18.359956 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6833 23:45:18.363321 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6834 23:45:18.366542 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6835 23:45:18.373502 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6836 23:45:18.376339 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6837 23:45:18.379659 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6838 23:45:18.383022 Total UI for P1: 0, mck2ui 16
6839 23:45:18.386419 best dqsien dly found for B0: ( 0, 14, 24)
6840 23:45:18.389489 Total UI for P1: 0, mck2ui 16
6841 23:45:18.392890 best dqsien dly found for B1: ( 0, 14, 24)
6842 23:45:18.396095 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6843 23:45:18.402927 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6844 23:45:18.403050
6845 23:45:18.406319 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6846 23:45:18.409541 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6847 23:45:18.412913 [Gating] SW calibration Done
6848 23:45:18.413015 ==
6849 23:45:18.416420 Dram Type= 6, Freq= 0, CH_1, rank 1
6850 23:45:18.419127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6851 23:45:18.419238 ==
6852 23:45:18.422611 RX Vref Scan: 0
6853 23:45:18.422715
6854 23:45:18.422811 RX Vref 0 -> 0, step: 1
6855 23:45:18.422910
6856 23:45:18.426192 RX Delay -410 -> 252, step: 16
6857 23:45:18.429493 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6858 23:45:18.435913 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6859 23:45:18.439135 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6860 23:45:18.442913 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6861 23:45:18.445859 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6862 23:45:18.452532 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6863 23:45:18.455714 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6864 23:45:18.459122 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6865 23:45:18.462390 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6866 23:45:18.469259 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6867 23:45:18.472232 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6868 23:45:18.475921 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6869 23:45:18.481835 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6870 23:45:18.485329 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6871 23:45:18.488856 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6872 23:45:18.492076 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6873 23:45:18.492188 ==
6874 23:45:18.495312 Dram Type= 6, Freq= 0, CH_1, rank 1
6875 23:45:18.501987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6876 23:45:18.502110 ==
6877 23:45:18.502204 DQS Delay:
6878 23:45:18.505286 DQS0 = 59, DQS1 = 59
6879 23:45:18.505402 DQM Delay:
6880 23:45:18.508541 DQM0 = 19, DQM1 = 12
6881 23:45:18.508661 DQ Delay:
6882 23:45:18.511955 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6883 23:45:18.515039 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6884 23:45:18.518463 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6885 23:45:18.521772 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6886 23:45:18.521878
6887 23:45:18.521968
6888 23:45:18.522060 ==
6889 23:45:18.525239 Dram Type= 6, Freq= 0, CH_1, rank 1
6890 23:45:18.528552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6891 23:45:18.528665 ==
6892 23:45:18.528771
6893 23:45:18.528860
6894 23:45:18.531849 TX Vref Scan disable
6895 23:45:18.531950 == TX Byte 0 ==
6896 23:45:18.538093 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6897 23:45:18.541991 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6898 23:45:18.542070 == TX Byte 1 ==
6899 23:45:18.548326 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6900 23:45:18.551555 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6901 23:45:18.551648 ==
6902 23:45:18.555052 Dram Type= 6, Freq= 0, CH_1, rank 1
6903 23:45:18.558056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6904 23:45:18.558170 ==
6905 23:45:18.558238
6906 23:45:18.558300
6907 23:45:18.561752 TX Vref Scan disable
6908 23:45:18.561836 == TX Byte 0 ==
6909 23:45:18.568207 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6910 23:45:18.571467 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6911 23:45:18.571552 == TX Byte 1 ==
6912 23:45:18.578095 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6913 23:45:18.581361 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6914 23:45:18.581485
6915 23:45:18.581581 [DATLAT]
6916 23:45:18.584550 Freq=400, CH1 RK1
6917 23:45:18.584643
6918 23:45:18.584709 DATLAT Default: 0xe
6919 23:45:18.587932 0, 0xFFFF, sum = 0
6920 23:45:18.588017 1, 0xFFFF, sum = 0
6921 23:45:18.591287 2, 0xFFFF, sum = 0
6922 23:45:18.591372 3, 0xFFFF, sum = 0
6923 23:45:18.594606 4, 0xFFFF, sum = 0
6924 23:45:18.594718 5, 0xFFFF, sum = 0
6925 23:45:18.597899 6, 0xFFFF, sum = 0
6926 23:45:18.601103 7, 0xFFFF, sum = 0
6927 23:45:18.601189 8, 0xFFFF, sum = 0
6928 23:45:18.604418 9, 0xFFFF, sum = 0
6929 23:45:18.604502 10, 0xFFFF, sum = 0
6930 23:45:18.608184 11, 0xFFFF, sum = 0
6931 23:45:18.608270 12, 0xFFFF, sum = 0
6932 23:45:18.610983 13, 0x0, sum = 1
6933 23:45:18.611068 14, 0x0, sum = 2
6934 23:45:18.614264 15, 0x0, sum = 3
6935 23:45:18.614349 16, 0x0, sum = 4
6936 23:45:18.614416 best_step = 14
6937 23:45:18.617955
6938 23:45:18.618045 ==
6939 23:45:18.621227 Dram Type= 6, Freq= 0, CH_1, rank 1
6940 23:45:18.624586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6941 23:45:18.624671 ==
6942 23:45:18.624737 RX Vref Scan: 0
6943 23:45:18.624798
6944 23:45:18.627387 RX Vref 0 -> 0, step: 1
6945 23:45:18.627470
6946 23:45:18.630882 RX Delay -359 -> 252, step: 8
6947 23:45:18.638038 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6948 23:45:18.641453 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
6949 23:45:18.644927 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
6950 23:45:18.648257 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6951 23:45:18.654769 iDelay=217, Bit 4, Center -48 (-303 ~ 208) 512
6952 23:45:18.658003 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
6953 23:45:18.661244 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6954 23:45:18.664609 iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504
6955 23:45:18.671247 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
6956 23:45:18.674784 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
6957 23:45:18.677887 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
6958 23:45:18.681235 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6959 23:45:18.687800 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6960 23:45:18.691027 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6961 23:45:18.694453 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
6962 23:45:18.701168 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
6963 23:45:18.701255 ==
6964 23:45:18.704579 Dram Type= 6, Freq= 0, CH_1, rank 1
6965 23:45:18.707505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6966 23:45:18.707592 ==
6967 23:45:18.707660 DQS Delay:
6968 23:45:18.710580 DQS0 = 60, DQS1 = 64
6969 23:45:18.710663 DQM Delay:
6970 23:45:18.713969 DQM0 = 12, DQM1 = 10
6971 23:45:18.714083 DQ Delay:
6972 23:45:18.717440 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6973 23:45:18.720810 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6974 23:45:18.724461 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6975 23:45:18.727487 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6976 23:45:18.727572
6977 23:45:18.727638
6978 23:45:18.734469 [DQSOSCAuto] RK1, (LSB)MR18= 0x7fad, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 393 ps
6979 23:45:18.737356 CH1 RK1: MR19=C0C, MR18=7FAD
6980 23:45:18.743961 CH1_RK1: MR19=0xC0C, MR18=0x7FAD, DQSOSC=388, MR23=63, INC=392, DEC=261
6981 23:45:18.747366 [RxdqsGatingPostProcess] freq 400
6982 23:45:18.753640 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6983 23:45:18.756882 best DQS0 dly(2T, 0.5T) = (0, 10)
6984 23:45:18.760600 best DQS1 dly(2T, 0.5T) = (0, 10)
6985 23:45:18.763993 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6986 23:45:18.767072 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6987 23:45:18.767198 best DQS0 dly(2T, 0.5T) = (0, 10)
6988 23:45:18.770242 best DQS1 dly(2T, 0.5T) = (0, 10)
6989 23:45:18.773716 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6990 23:45:18.776922 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6991 23:45:18.780323 Pre-setting of DQS Precalculation
6992 23:45:18.786645 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6993 23:45:18.793159 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6994 23:45:18.799751 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6995 23:45:18.799865
6996 23:45:18.799932
6997 23:45:18.803200 [Calibration Summary] 800 Mbps
6998 23:45:18.803358 CH 0, Rank 0
6999 23:45:18.806411 SW Impedance : PASS
7000 23:45:18.809866 DUTY Scan : NO K
7001 23:45:18.809967 ZQ Calibration : PASS
7002 23:45:18.813071 Jitter Meter : NO K
7003 23:45:18.816264 CBT Training : PASS
7004 23:45:18.816463 Write leveling : PASS
7005 23:45:18.819538 RX DQS gating : PASS
7006 23:45:18.823065 RX DQ/DQS(RDDQC) : PASS
7007 23:45:18.823149 TX DQ/DQS : PASS
7008 23:45:18.826426 RX DATLAT : PASS
7009 23:45:18.829574 RX DQ/DQS(Engine): PASS
7010 23:45:18.829659 TX OE : NO K
7011 23:45:18.833438 All Pass.
7012 23:45:18.833522
7013 23:45:18.833589 CH 0, Rank 1
7014 23:45:18.836421 SW Impedance : PASS
7015 23:45:18.836493 DUTY Scan : NO K
7016 23:45:18.839838 ZQ Calibration : PASS
7017 23:45:18.842685 Jitter Meter : NO K
7018 23:45:18.842768 CBT Training : PASS
7019 23:45:18.846053 Write leveling : NO K
7020 23:45:18.849299 RX DQS gating : PASS
7021 23:45:18.849384 RX DQ/DQS(RDDQC) : PASS
7022 23:45:18.852674 TX DQ/DQS : PASS
7023 23:45:18.855980 RX DATLAT : PASS
7024 23:45:18.856063 RX DQ/DQS(Engine): PASS
7025 23:45:18.859453 TX OE : NO K
7026 23:45:18.859541 All Pass.
7027 23:45:18.859619
7028 23:45:18.862742 CH 1, Rank 0
7029 23:45:18.862827 SW Impedance : PASS
7030 23:45:18.865779 DUTY Scan : NO K
7031 23:45:18.865866 ZQ Calibration : PASS
7032 23:45:18.869082 Jitter Meter : NO K
7033 23:45:18.872741 CBT Training : PASS
7034 23:45:18.872854 Write leveling : PASS
7035 23:45:18.875860 RX DQS gating : PASS
7036 23:45:18.879249 RX DQ/DQS(RDDQC) : PASS
7037 23:45:18.879334 TX DQ/DQS : PASS
7038 23:45:18.882573 RX DATLAT : PASS
7039 23:45:18.885877 RX DQ/DQS(Engine): PASS
7040 23:45:18.885990 TX OE : NO K
7041 23:45:18.889075 All Pass.
7042 23:45:18.889173
7043 23:45:18.889240 CH 1, Rank 1
7044 23:45:18.892309 SW Impedance : PASS
7045 23:45:18.892427 DUTY Scan : NO K
7046 23:45:18.895651 ZQ Calibration : PASS
7047 23:45:18.899187 Jitter Meter : NO K
7048 23:45:18.899263 CBT Training : PASS
7049 23:45:18.902197 Write leveling : NO K
7050 23:45:18.905669 RX DQS gating : PASS
7051 23:45:18.905777 RX DQ/DQS(RDDQC) : PASS
7052 23:45:18.909248 TX DQ/DQS : PASS
7053 23:45:18.912605 RX DATLAT : PASS
7054 23:45:18.912720 RX DQ/DQS(Engine): PASS
7055 23:45:18.915595 TX OE : NO K
7056 23:45:18.915713 All Pass.
7057 23:45:18.915813
7058 23:45:18.919428 DramC Write-DBI off
7059 23:45:18.922543 PER_BANK_REFRESH: Hybrid Mode
7060 23:45:18.922644 TX_TRACKING: ON
7061 23:45:18.932569 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7062 23:45:18.935569 [FAST_K] Save calibration result to emmc
7063 23:45:18.938963 dramc_set_vcore_voltage set vcore to 725000
7064 23:45:18.942259 Read voltage for 1600, 0
7065 23:45:18.942344 Vio18 = 0
7066 23:45:18.942419 Vcore = 725000
7067 23:45:18.945540 Vdram = 0
7068 23:45:18.945650 Vddq = 0
7069 23:45:18.945746 Vmddr = 0
7070 23:45:18.952357 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7071 23:45:18.955936 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7072 23:45:18.958963 MEM_TYPE=3, freq_sel=13
7073 23:45:18.962265 sv_algorithm_assistance_LP4_3733
7074 23:45:18.965835 ============ PULL DRAM RESETB DOWN ============
7075 23:45:18.969190 ========== PULL DRAM RESETB DOWN end =========
7076 23:45:18.975090 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7077 23:45:18.978898 ===================================
7078 23:45:18.979013 LPDDR4 DRAM CONFIGURATION
7079 23:45:18.982092 ===================================
7080 23:45:18.985319 EX_ROW_EN[0] = 0x0
7081 23:45:18.988446 EX_ROW_EN[1] = 0x0
7082 23:45:18.988565 LP4Y_EN = 0x0
7083 23:45:18.991905 WORK_FSP = 0x1
7084 23:45:18.991997 WL = 0x5
7085 23:45:18.995428 RL = 0x5
7086 23:45:18.995515 BL = 0x2
7087 23:45:18.998762 RPST = 0x0
7088 23:45:18.998849 RD_PRE = 0x0
7089 23:45:19.001956 WR_PRE = 0x1
7090 23:45:19.002041 WR_PST = 0x1
7091 23:45:19.005038 DBI_WR = 0x0
7092 23:45:19.005123 DBI_RD = 0x0
7093 23:45:19.008430 OTF = 0x1
7094 23:45:19.011951 ===================================
7095 23:45:19.015337 ===================================
7096 23:45:19.015465 ANA top config
7097 23:45:19.018837 ===================================
7098 23:45:19.021607 DLL_ASYNC_EN = 0
7099 23:45:19.025149 ALL_SLAVE_EN = 0
7100 23:45:19.028418 NEW_RANK_MODE = 1
7101 23:45:19.028548 DLL_IDLE_MODE = 1
7102 23:45:19.031646 LP45_APHY_COMB_EN = 1
7103 23:45:19.035129 TX_ODT_DIS = 0
7104 23:45:19.038494 NEW_8X_MODE = 1
7105 23:45:19.041711 ===================================
7106 23:45:19.044700 ===================================
7107 23:45:19.048176 data_rate = 3200
7108 23:45:19.048302 CKR = 1
7109 23:45:19.051415 DQ_P2S_RATIO = 8
7110 23:45:19.054748 ===================================
7111 23:45:19.058180 CA_P2S_RATIO = 8
7112 23:45:19.061480 DQ_CA_OPEN = 0
7113 23:45:19.064922 DQ_SEMI_OPEN = 0
7114 23:45:19.068208 CA_SEMI_OPEN = 0
7115 23:45:19.068333 CA_FULL_RATE = 0
7116 23:45:19.071601 DQ_CKDIV4_EN = 0
7117 23:45:19.074833 CA_CKDIV4_EN = 0
7118 23:45:19.077991 CA_PREDIV_EN = 0
7119 23:45:19.081307 PH8_DLY = 12
7120 23:45:19.084593 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7121 23:45:19.084718 DQ_AAMCK_DIV = 4
7122 23:45:19.088207 CA_AAMCK_DIV = 4
7123 23:45:19.091317 CA_ADMCK_DIV = 4
7124 23:45:19.094743 DQ_TRACK_CA_EN = 0
7125 23:45:19.098053 CA_PICK = 1600
7126 23:45:19.101429 CA_MCKIO = 1600
7127 23:45:19.104252 MCKIO_SEMI = 0
7128 23:45:19.107516 PLL_FREQ = 3068
7129 23:45:19.107597 DQ_UI_PI_RATIO = 32
7130 23:45:19.111296 CA_UI_PI_RATIO = 0
7131 23:45:19.114559 ===================================
7132 23:45:19.117830 ===================================
7133 23:45:19.121252 memory_type:LPDDR4
7134 23:45:19.124502 GP_NUM : 10
7135 23:45:19.124625 SRAM_EN : 1
7136 23:45:19.128023 MD32_EN : 0
7137 23:45:19.131361 ===================================
7138 23:45:19.131444 [ANA_INIT] >>>>>>>>>>>>>>
7139 23:45:19.134343 <<<<<< [CONFIGURE PHASE]: ANA_TX
7140 23:45:19.137840 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7141 23:45:19.140917 ===================================
7142 23:45:19.144233 data_rate = 3200,PCW = 0X7600
7143 23:45:19.147622 ===================================
7144 23:45:19.150829 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7145 23:45:19.157314 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7146 23:45:19.164107 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7147 23:45:19.167457 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7148 23:45:19.170839 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7149 23:45:19.174206 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7150 23:45:19.177210 [ANA_INIT] flow start
7151 23:45:19.177296 [ANA_INIT] PLL >>>>>>>>
7152 23:45:19.180485 [ANA_INIT] PLL <<<<<<<<
7153 23:45:19.184062 [ANA_INIT] MIDPI >>>>>>>>
7154 23:45:19.184144 [ANA_INIT] MIDPI <<<<<<<<
7155 23:45:19.187471 [ANA_INIT] DLL >>>>>>>>
7156 23:45:19.190804 [ANA_INIT] DLL <<<<<<<<
7157 23:45:19.190885 [ANA_INIT] flow end
7158 23:45:19.197533 ============ LP4 DIFF to SE enter ============
7159 23:45:19.200547 ============ LP4 DIFF to SE exit ============
7160 23:45:19.204064 [ANA_INIT] <<<<<<<<<<<<<
7161 23:45:19.207420 [Flow] Enable top DCM control >>>>>
7162 23:45:19.210754 [Flow] Enable top DCM control <<<<<
7163 23:45:19.210860 Enable DLL master slave shuffle
7164 23:45:19.216941 ==============================================================
7165 23:45:19.220951 Gating Mode config
7166 23:45:19.223549 ==============================================================
7167 23:45:19.226975 Config description:
7168 23:45:19.237329 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7169 23:45:19.243550 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7170 23:45:19.247126 SELPH_MODE 0: By rank 1: By Phase
7171 23:45:19.253524 ==============================================================
7172 23:45:19.256801 GAT_TRACK_EN = 1
7173 23:45:19.260147 RX_GATING_MODE = 2
7174 23:45:19.263988 RX_GATING_TRACK_MODE = 2
7175 23:45:19.267334 SELPH_MODE = 1
7176 23:45:19.267415 PICG_EARLY_EN = 1
7177 23:45:19.270017 VALID_LAT_VALUE = 1
7178 23:45:19.276941 ==============================================================
7179 23:45:19.280355 Enter into Gating configuration >>>>
7180 23:45:19.283573 Exit from Gating configuration <<<<
7181 23:45:19.286911 Enter into DVFS_PRE_config >>>>>
7182 23:45:19.296761 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7183 23:45:19.300144 Exit from DVFS_PRE_config <<<<<
7184 23:45:19.303796 Enter into PICG configuration >>>>
7185 23:45:19.306790 Exit from PICG configuration <<<<
7186 23:45:19.310099 [RX_INPUT] configuration >>>>>
7187 23:45:19.313549 [RX_INPUT] configuration <<<<<
7188 23:45:19.317041 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7189 23:45:19.323196 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7190 23:45:19.330328 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7191 23:45:19.336624 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7192 23:45:19.343434 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7193 23:45:19.346798 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7194 23:45:19.353121 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7195 23:45:19.356254 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7196 23:45:19.359757 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7197 23:45:19.363071 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7198 23:45:19.369537 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7199 23:45:19.372951 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7200 23:45:19.376407 ===================================
7201 23:45:19.379632 LPDDR4 DRAM CONFIGURATION
7202 23:45:19.383045 ===================================
7203 23:45:19.383130 EX_ROW_EN[0] = 0x0
7204 23:45:19.386452 EX_ROW_EN[1] = 0x0
7205 23:45:19.386535 LP4Y_EN = 0x0
7206 23:45:19.389281 WORK_FSP = 0x1
7207 23:45:19.389365 WL = 0x5
7208 23:45:19.393175 RL = 0x5
7209 23:45:19.393260 BL = 0x2
7210 23:45:19.396298 RPST = 0x0
7211 23:45:19.399682 RD_PRE = 0x0
7212 23:45:19.399764 WR_PRE = 0x1
7213 23:45:19.402951 WR_PST = 0x1
7214 23:45:19.403033 DBI_WR = 0x0
7215 23:45:19.406218 DBI_RD = 0x0
7216 23:45:19.406300 OTF = 0x1
7217 23:45:19.409536 ===================================
7218 23:45:19.412565 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7219 23:45:19.419474 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7220 23:45:19.422743 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7221 23:45:19.425877 ===================================
7222 23:45:19.429297 LPDDR4 DRAM CONFIGURATION
7223 23:45:19.432528 ===================================
7224 23:45:19.432620 EX_ROW_EN[0] = 0x10
7225 23:45:19.435927 EX_ROW_EN[1] = 0x0
7226 23:45:19.436009 LP4Y_EN = 0x0
7227 23:45:19.439304 WORK_FSP = 0x1
7228 23:45:19.439387 WL = 0x5
7229 23:45:19.442554 RL = 0x5
7230 23:45:19.442637 BL = 0x2
7231 23:45:19.445923 RPST = 0x0
7232 23:45:19.446006 RD_PRE = 0x0
7233 23:45:19.449360 WR_PRE = 0x1
7234 23:45:19.452657 WR_PST = 0x1
7235 23:45:19.452739 DBI_WR = 0x0
7236 23:45:19.455919 DBI_RD = 0x0
7237 23:45:19.456002 OTF = 0x1
7238 23:45:19.459138 ===================================
7239 23:45:19.465704 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7240 23:45:19.465790 ==
7241 23:45:19.469257 Dram Type= 6, Freq= 0, CH_0, rank 0
7242 23:45:19.472553 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7243 23:45:19.472644 ==
7244 23:45:19.475756 [Duty_Offset_Calibration]
7245 23:45:19.475838 B0:2 B1:0 CA:3
7246 23:45:19.479123
7247 23:45:19.481958 [DutyScan_Calibration_Flow] k_type=0
7248 23:45:19.490384
7249 23:45:19.490466 ==CLK 0==
7250 23:45:19.493748 Final CLK duty delay cell = 0
7251 23:45:19.497112 [0] MAX Duty = 5031%(X100), DQS PI = 12
7252 23:45:19.500397 [0] MIN Duty = 4907%(X100), DQS PI = 6
7253 23:45:19.500503 [0] AVG Duty = 4969%(X100)
7254 23:45:19.503629
7255 23:45:19.506866 CH0 CLK Duty spec in!! Max-Min= 124%
7256 23:45:19.510212 [DutyScan_Calibration_Flow] ====Done====
7257 23:45:19.510294
7258 23:45:19.513538 [DutyScan_Calibration_Flow] k_type=1
7259 23:45:19.530374
7260 23:45:19.530458 ==DQS 0 ==
7261 23:45:19.533045 Final DQS duty delay cell = 0
7262 23:45:19.536939 [0] MAX Duty = 5094%(X100), DQS PI = 30
7263 23:45:19.540220 [0] MIN Duty = 4875%(X100), DQS PI = 48
7264 23:45:19.543126 [0] AVG Duty = 4984%(X100)
7265 23:45:19.543208
7266 23:45:19.543272 ==DQS 1 ==
7267 23:45:19.546480 Final DQS duty delay cell = 0
7268 23:45:19.549982 [0] MAX Duty = 5156%(X100), DQS PI = 32
7269 23:45:19.553131 [0] MIN Duty = 5031%(X100), DQS PI = 14
7270 23:45:19.556476 [0] AVG Duty = 5093%(X100)
7271 23:45:19.556603
7272 23:45:19.559779 CH0 DQS 0 Duty spec in!! Max-Min= 219%
7273 23:45:19.559861
7274 23:45:19.562863 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7275 23:45:19.566790 [DutyScan_Calibration_Flow] ====Done====
7276 23:45:19.566872
7277 23:45:19.570025 [DutyScan_Calibration_Flow] k_type=3
7278 23:45:19.587971
7279 23:45:19.588057 ==DQM 0 ==
7280 23:45:19.591387 Final DQM duty delay cell = 0
7281 23:45:19.594709 [0] MAX Duty = 5156%(X100), DQS PI = 30
7282 23:45:19.597992 [0] MIN Duty = 4844%(X100), DQS PI = 48
7283 23:45:19.600977 [0] AVG Duty = 5000%(X100)
7284 23:45:19.601059
7285 23:45:19.601124 ==DQM 1 ==
7286 23:45:19.604723 Final DQM duty delay cell = 4
7287 23:45:19.608004 [4] MAX Duty = 5187%(X100), DQS PI = 62
7288 23:45:19.611407 [4] MIN Duty = 5000%(X100), DQS PI = 14
7289 23:45:19.614291 [4] AVG Duty = 5093%(X100)
7290 23:45:19.614372
7291 23:45:19.617626 CH0 DQM 0 Duty spec in!! Max-Min= 312%
7292 23:45:19.617707
7293 23:45:19.620922 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7294 23:45:19.624377 [DutyScan_Calibration_Flow] ====Done====
7295 23:45:19.624483
7296 23:45:19.627523 [DutyScan_Calibration_Flow] k_type=2
7297 23:45:19.644351
7298 23:45:19.644484 ==DQ 0 ==
7299 23:45:19.647200 Final DQ duty delay cell = -4
7300 23:45:19.650535 [-4] MAX Duty = 5000%(X100), DQS PI = 20
7301 23:45:19.654413 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7302 23:45:19.657716 [-4] AVG Duty = 4938%(X100)
7303 23:45:19.657797
7304 23:45:19.657861 ==DQ 1 ==
7305 23:45:19.660452 Final DQ duty delay cell = 0
7306 23:45:19.664206 [0] MAX Duty = 5156%(X100), DQS PI = 58
7307 23:45:19.667407 [0] MIN Duty = 5000%(X100), DQS PI = 16
7308 23:45:19.670887 [0] AVG Duty = 5078%(X100)
7309 23:45:19.670968
7310 23:45:19.674070 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7311 23:45:19.674151
7312 23:45:19.677175 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7313 23:45:19.680461 [DutyScan_Calibration_Flow] ====Done====
7314 23:45:19.680584 ==
7315 23:45:19.683896 Dram Type= 6, Freq= 0, CH_1, rank 0
7316 23:45:19.687424 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7317 23:45:19.687508 ==
7318 23:45:19.690815 [Duty_Offset_Calibration]
7319 23:45:19.690921 B0:1 B1:-2 CA:0
7320 23:45:19.691012
7321 23:45:19.693690 [DutyScan_Calibration_Flow] k_type=0
7322 23:45:19.704414
7323 23:45:19.704521 ==CLK 0==
7324 23:45:19.707770 Final CLK duty delay cell = 0
7325 23:45:19.711170 [0] MAX Duty = 5062%(X100), DQS PI = 20
7326 23:45:19.714411 [0] MIN Duty = 4844%(X100), DQS PI = 4
7327 23:45:19.714492 [0] AVG Duty = 4953%(X100)
7328 23:45:19.717927
7329 23:45:19.721273 CH1 CLK Duty spec in!! Max-Min= 218%
7330 23:45:19.724533 [DutyScan_Calibration_Flow] ====Done====
7331 23:45:19.724662
7332 23:45:19.727975 [DutyScan_Calibration_Flow] k_type=1
7333 23:45:19.743494
7334 23:45:19.743577 ==DQS 0 ==
7335 23:45:19.746445 Final DQS duty delay cell = -4
7336 23:45:19.750177 [-4] MAX Duty = 4969%(X100), DQS PI = 24
7337 23:45:19.753324 [-4] MIN Duty = 4813%(X100), DQS PI = 54
7338 23:45:19.756562 [-4] AVG Duty = 4891%(X100)
7339 23:45:19.756669
7340 23:45:19.756735 ==DQS 1 ==
7341 23:45:19.760089 Final DQS duty delay cell = 0
7342 23:45:19.763333 [0] MAX Duty = 5093%(X100), DQS PI = 0
7343 23:45:19.766572 [0] MIN Duty = 4844%(X100), DQS PI = 24
7344 23:45:19.769858 [0] AVG Duty = 4968%(X100)
7345 23:45:19.769958
7346 23:45:19.773133 CH1 DQS 0 Duty spec in!! Max-Min= 156%
7347 23:45:19.773208
7348 23:45:19.776226 CH1 DQS 1 Duty spec in!! Max-Min= 249%
7349 23:45:19.779722 [DutyScan_Calibration_Flow] ====Done====
7350 23:45:19.779828
7351 23:45:19.782878 [DutyScan_Calibration_Flow] k_type=3
7352 23:45:19.800256
7353 23:45:19.800345 ==DQM 0 ==
7354 23:45:19.803670 Final DQM duty delay cell = 0
7355 23:45:19.807093 [0] MAX Duty = 5062%(X100), DQS PI = 24
7356 23:45:19.810459 [0] MIN Duty = 4813%(X100), DQS PI = 54
7357 23:45:19.813971 [0] AVG Duty = 4937%(X100)
7358 23:45:19.814053
7359 23:45:19.814118 ==DQM 1 ==
7360 23:45:19.816754 Final DQM duty delay cell = 0
7361 23:45:19.819988 [0] MAX Duty = 5062%(X100), DQS PI = 34
7362 23:45:19.823297 [0] MIN Duty = 4875%(X100), DQS PI = 24
7363 23:45:19.826860 [0] AVG Duty = 4968%(X100)
7364 23:45:19.826941
7365 23:45:19.830328 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7366 23:45:19.830410
7367 23:45:19.833159 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7368 23:45:19.836496 [DutyScan_Calibration_Flow] ====Done====
7369 23:45:19.836582
7370 23:45:19.839849 [DutyScan_Calibration_Flow] k_type=2
7371 23:45:19.857234
7372 23:45:19.857321 ==DQ 0 ==
7373 23:45:19.860930 Final DQ duty delay cell = 0
7374 23:45:19.863776 [0] MAX Duty = 5093%(X100), DQS PI = 22
7375 23:45:19.867352 [0] MIN Duty = 4907%(X100), DQS PI = 60
7376 23:45:19.867434 [0] AVG Duty = 5000%(X100)
7377 23:45:19.870622
7378 23:45:19.870703 ==DQ 1 ==
7379 23:45:19.873805 Final DQ duty delay cell = 0
7380 23:45:19.877115 [0] MAX Duty = 5125%(X100), DQS PI = 34
7381 23:45:19.880492 [0] MIN Duty = 4938%(X100), DQS PI = 24
7382 23:45:19.880584 [0] AVG Duty = 5031%(X100)
7383 23:45:19.883609
7384 23:45:19.886929 CH1 DQ 0 Duty spec in!! Max-Min= 186%
7385 23:45:19.887012
7386 23:45:19.890551 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7387 23:45:19.893548 [DutyScan_Calibration_Flow] ====Done====
7388 23:45:19.896860 nWR fixed to 30
7389 23:45:19.896989 [ModeRegInit_LP4] CH0 RK0
7390 23:45:19.900025 [ModeRegInit_LP4] CH0 RK1
7391 23:45:19.903854 [ModeRegInit_LP4] CH1 RK0
7392 23:45:19.906754 [ModeRegInit_LP4] CH1 RK1
7393 23:45:19.906881 match AC timing 5
7394 23:45:19.913325 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7395 23:45:19.916688 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7396 23:45:19.920072 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7397 23:45:19.926879 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7398 23:45:19.929773 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7399 23:45:19.929899 [MiockJmeterHQA]
7400 23:45:19.930014
7401 23:45:19.933109 [DramcMiockJmeter] u1RxGatingPI = 0
7402 23:45:19.936420 0 : 4255, 4029
7403 23:45:19.936531 4 : 4366, 4139
7404 23:45:19.939786 8 : 4255, 4029
7405 23:45:19.939862 12 : 4365, 4140
7406 23:45:19.939926 16 : 4258, 4029
7407 23:45:19.943134 20 : 4255, 4029
7408 23:45:19.943222 24 : 4254, 4029
7409 23:45:19.946498 28 : 4257, 4032
7410 23:45:19.946585 32 : 4365, 4139
7411 23:45:19.949894 36 : 4255, 4029
7412 23:45:19.950007 40 : 4363, 4140
7413 23:45:19.953001 44 : 4365, 4140
7414 23:45:19.953098 48 : 4250, 4026
7415 23:45:19.953166 52 : 4252, 4029
7416 23:45:19.956426 56 : 4253, 4029
7417 23:45:19.956593 60 : 4366, 4140
7418 23:45:19.959680 64 : 4252, 4029
7419 23:45:19.959782 68 : 4250, 4027
7420 23:45:19.963217 72 : 4255, 4029
7421 23:45:19.963323 76 : 4252, 4029
7422 23:45:19.966231 80 : 4255, 4029
7423 23:45:19.966321 84 : 4366, 4140
7424 23:45:19.966390 88 : 4253, 4029
7425 23:45:19.969854 92 : 4255, 4029
7426 23:45:19.969940 96 : 4255, 4029
7427 23:45:19.972621 100 : 4255, 4029
7428 23:45:19.972708 104 : 4368, 3371
7429 23:45:19.975894 108 : 4366, 0
7430 23:45:19.975979 112 : 4365, 0
7431 23:45:19.976046 116 : 4252, 0
7432 23:45:19.979691 120 : 4255, 0
7433 23:45:19.979776 124 : 4363, 0
7434 23:45:19.982637 128 : 4255, 0
7435 23:45:19.982748 132 : 4255, 0
7436 23:45:19.982844 136 : 4252, 0
7437 23:45:19.985975 140 : 4255, 0
7438 23:45:19.986060 144 : 4366, 0
7439 23:45:19.989655 148 : 4252, 0
7440 23:45:19.989740 152 : 4253, 0
7441 23:45:19.989806 156 : 4254, 0
7442 23:45:19.992428 160 : 4252, 0
7443 23:45:19.992542 164 : 4253, 0
7444 23:45:19.995804 168 : 4255, 0
7445 23:45:19.995891 172 : 4253, 0
7446 23:45:19.995959 176 : 4252, 0
7447 23:45:19.998986 180 : 4253, 0
7448 23:45:19.999071 184 : 4253, 0
7449 23:45:20.002591 188 : 4252, 0
7450 23:45:20.002676 192 : 4255, 0
7451 23:45:20.002741 196 : 4363, 0
7452 23:45:20.005946 200 : 4252, 0
7453 23:45:20.006030 204 : 4253, 0
7454 23:45:20.006096 208 : 4252, 0
7455 23:45:20.009275 212 : 4252, 0
7456 23:45:20.009358 216 : 4363, 0
7457 23:45:20.012484 220 : 4252, 0
7458 23:45:20.012599 224 : 4363, 0
7459 23:45:20.012668 228 : 4368, 0
7460 23:45:20.015617 232 : 4253, 0
7461 23:45:20.015702 236 : 4363, 1009
7462 23:45:20.019064 240 : 4253, 4029
7463 23:45:20.019178 244 : 4255, 4029
7464 23:45:20.022454 248 : 4255, 4029
7465 23:45:20.022542 252 : 4363, 4139
7466 23:45:20.025717 256 : 4253, 4029
7467 23:45:20.025803 260 : 4255, 4029
7468 23:45:20.029127 264 : 4366, 4140
7469 23:45:20.029211 268 : 4363, 4139
7470 23:45:20.032450 272 : 4250, 4027
7471 23:45:20.032575 276 : 4252, 4029
7472 23:45:20.032659 280 : 4365, 4140
7473 23:45:20.035843 284 : 4366, 4140
7474 23:45:20.035929 288 : 4365, 4140
7475 23:45:20.039215 292 : 4253, 4029
7476 23:45:20.039299 296 : 4255, 4029
7477 23:45:20.042365 300 : 4255, 4029
7478 23:45:20.042476 304 : 4363, 4140
7479 23:45:20.045852 308 : 4253, 4029
7480 23:45:20.045962 312 : 4254, 4029
7481 23:45:20.048610 316 : 4255, 4029
7482 23:45:20.048694 320 : 4366, 4140
7483 23:45:20.051989 324 : 4363, 4140
7484 23:45:20.052074 328 : 4250, 4027
7485 23:45:20.055364 332 : 4365, 4142
7486 23:45:20.055447 336 : 4366, 4139
7487 23:45:20.058699 340 : 4250, 4026
7488 23:45:20.058784 344 : 4253, 4029
7489 23:45:20.058856 348 : 4257, 4032
7490 23:45:20.061962 352 : 4366, 4108
7491 23:45:20.062046 356 : 4252, 2822
7492 23:45:20.065227 360 : 4253, 0
7493 23:45:20.065326
7494 23:45:20.068925 MIOCK jitter meter ch=0
7495 23:45:20.069039
7496 23:45:20.069104 1T = (360-108) = 252 dly cells
7497 23:45:20.075446 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7498 23:45:20.075529 ==
7499 23:45:20.078530 Dram Type= 6, Freq= 0, CH_0, rank 0
7500 23:45:20.081811 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7501 23:45:20.085312 ==
7502 23:45:20.088613 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7503 23:45:20.091687 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7504 23:45:20.098675 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7505 23:45:20.105080 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7506 23:45:20.112089 [CA 0] Center 44 (14~75) winsize 62
7507 23:45:20.115561 [CA 1] Center 43 (13~74) winsize 62
7508 23:45:20.119057 [CA 2] Center 39 (10~69) winsize 60
7509 23:45:20.122102 [CA 3] Center 39 (10~68) winsize 59
7510 23:45:20.125246 [CA 4] Center 37 (8~67) winsize 60
7511 23:45:20.128777 [CA 5] Center 37 (7~67) winsize 61
7512 23:45:20.128876
7513 23:45:20.132005 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7514 23:45:20.132102
7515 23:45:20.138785 [CATrainingPosCal] consider 1 rank data
7516 23:45:20.138899 u2DelayCellTimex100 = 258/100 ps
7517 23:45:20.145501 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7518 23:45:20.148968 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7519 23:45:20.151877 CA2 delay=39 (10~69),Diff = 2 PI (7 cell)
7520 23:45:20.154962 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7521 23:45:20.158294 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7522 23:45:20.162020 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7523 23:45:20.162142
7524 23:45:20.165433 CA PerBit enable=1, Macro0, CA PI delay=37
7525 23:45:20.165559
7526 23:45:20.168306 [CBTSetCACLKResult] CA Dly = 37
7527 23:45:20.171768 CS Dly: 11 (0~42)
7528 23:45:20.174906 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7529 23:45:20.178618 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7530 23:45:20.178748 ==
7531 23:45:20.181659 Dram Type= 6, Freq= 0, CH_0, rank 1
7532 23:45:20.188744 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7533 23:45:20.188891 ==
7534 23:45:20.191966 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7535 23:45:20.195227 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7536 23:45:20.201884 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7537 23:45:20.208376 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7538 23:45:20.215906 [CA 0] Center 44 (13~75) winsize 63
7539 23:45:20.219204 [CA 1] Center 43 (13~74) winsize 62
7540 23:45:20.222591 [CA 2] Center 39 (10~69) winsize 60
7541 23:45:20.226136 [CA 3] Center 39 (10~68) winsize 59
7542 23:45:20.229295 [CA 4] Center 37 (8~67) winsize 60
7543 23:45:20.232553 [CA 5] Center 36 (7~66) winsize 60
7544 23:45:20.232639
7545 23:45:20.235665 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7546 23:45:20.235765
7547 23:45:20.242341 [CATrainingPosCal] consider 2 rank data
7548 23:45:20.242447 u2DelayCellTimex100 = 258/100 ps
7549 23:45:20.249010 CA0 delay=44 (14~75),Diff = 8 PI (30 cell)
7550 23:45:20.252399 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7551 23:45:20.255773 CA2 delay=39 (10~69),Diff = 3 PI (11 cell)
7552 23:45:20.259022 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7553 23:45:20.262688 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
7554 23:45:20.265882 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7555 23:45:20.266008
7556 23:45:20.269265 CA PerBit enable=1, Macro0, CA PI delay=36
7557 23:45:20.269388
7558 23:45:20.272461 [CBTSetCACLKResult] CA Dly = 36
7559 23:45:20.275945 CS Dly: 11 (0~43)
7560 23:45:20.279342 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7561 23:45:20.282585 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7562 23:45:20.282669
7563 23:45:20.285932 ----->DramcWriteLeveling(PI) begin...
7564 23:45:20.286017 ==
7565 23:45:20.289340 Dram Type= 6, Freq= 0, CH_0, rank 0
7566 23:45:20.295701 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7567 23:45:20.295788 ==
7568 23:45:20.299224 Write leveling (Byte 0): 36 => 36
7569 23:45:20.302166 Write leveling (Byte 1): 30 => 30
7570 23:45:20.302250 DramcWriteLeveling(PI) end<-----
7571 23:45:20.302315
7572 23:45:20.305449 ==
7573 23:45:20.308929 Dram Type= 6, Freq= 0, CH_0, rank 0
7574 23:45:20.312072 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7575 23:45:20.312157 ==
7576 23:45:20.315456 [Gating] SW mode calibration
7577 23:45:20.322206 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7578 23:45:20.325640 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7579 23:45:20.331963 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7580 23:45:20.335346 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7581 23:45:20.338752 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7582 23:45:20.345240 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7583 23:45:20.348832 1 4 16 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (0 0)
7584 23:45:20.351751 1 4 20 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7585 23:45:20.358381 1 4 24 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
7586 23:45:20.361689 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7587 23:45:20.365035 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7588 23:45:20.371764 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7589 23:45:20.374944 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7590 23:45:20.378302 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7591 23:45:20.384919 1 5 16 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 0)
7592 23:45:20.388300 1 5 20 | B1->B0 | 3333 2323 | 1 0 | (1 1) (0 0)
7593 23:45:20.391705 1 5 24 | B1->B0 | 2b2b 2323 | 1 0 | (0 0) (0 0)
7594 23:45:20.398413 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7595 23:45:20.401660 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7596 23:45:20.404743 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7597 23:45:20.411463 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7598 23:45:20.414768 1 6 12 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7599 23:45:20.418475 1 6 16 | B1->B0 | 2323 3f3f | 0 0 | (0 0) (1 1)
7600 23:45:20.424732 1 6 20 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
7601 23:45:20.428539 1 6 24 | B1->B0 | 4242 4646 | 1 0 | (0 0) (0 0)
7602 23:45:20.431803 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7603 23:45:20.438112 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7604 23:45:20.441344 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7605 23:45:20.444744 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7606 23:45:20.451368 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7607 23:45:20.454819 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7608 23:45:20.458421 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7609 23:45:20.461475 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7610 23:45:20.468080 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7611 23:45:20.471404 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7612 23:45:20.474680 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7613 23:45:20.481316 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7614 23:45:20.484823 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7615 23:45:20.488157 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7616 23:45:20.494849 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7617 23:45:20.497665 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7618 23:45:20.501128 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7619 23:45:20.507819 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7620 23:45:20.510967 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7621 23:45:20.514273 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 23:45:20.521080 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7623 23:45:20.524291 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7624 23:45:20.527679 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7625 23:45:20.534252 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7626 23:45:20.537609 Total UI for P1: 0, mck2ui 16
7627 23:45:20.540989 best dqsien dly found for B0: ( 1, 9, 16)
7628 23:45:20.544405 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7629 23:45:20.547803 Total UI for P1: 0, mck2ui 16
7630 23:45:20.550617 best dqsien dly found for B1: ( 1, 9, 24)
7631 23:45:20.553996 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
7632 23:45:20.557272 best DQS1 dly(MCK, UI, PI) = (1, 9, 24)
7633 23:45:20.557370
7634 23:45:20.560534 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
7635 23:45:20.563978 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 24)
7636 23:45:20.567376 [Gating] SW calibration Done
7637 23:45:20.567476 ==
7638 23:45:20.570525 Dram Type= 6, Freq= 0, CH_0, rank 0
7639 23:45:20.577340 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7640 23:45:20.577434 ==
7641 23:45:20.577502 RX Vref Scan: 0
7642 23:45:20.577565
7643 23:45:20.580573 RX Vref 0 -> 0, step: 1
7644 23:45:20.580658
7645 23:45:20.583859 RX Delay 0 -> 252, step: 8
7646 23:45:20.587063 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
7647 23:45:20.590534 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
7648 23:45:20.593535 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7649 23:45:20.597020 iDelay=200, Bit 3, Center 123 (72 ~ 175) 104
7650 23:45:20.603596 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
7651 23:45:20.607027 iDelay=200, Bit 5, Center 111 (56 ~ 167) 112
7652 23:45:20.610258 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
7653 23:45:20.613391 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
7654 23:45:20.616699 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7655 23:45:20.623561 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7656 23:45:20.626968 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7657 23:45:20.630120 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
7658 23:45:20.633154 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
7659 23:45:20.640068 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7660 23:45:20.643211 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7661 23:45:20.646563 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7662 23:45:20.646681 ==
7663 23:45:20.650284 Dram Type= 6, Freq= 0, CH_0, rank 0
7664 23:45:20.653319 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7665 23:45:20.653407 ==
7666 23:45:20.656577 DQS Delay:
7667 23:45:20.656661 DQS0 = 0, DQS1 = 0
7668 23:45:20.660052 DQM Delay:
7669 23:45:20.660140 DQM0 = 129, DQM1 = 123
7670 23:45:20.660207 DQ Delay:
7671 23:45:20.663439 DQ0 =131, DQ1 =131, DQ2 =127, DQ3 =123
7672 23:45:20.666838 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =143
7673 23:45:20.673640 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =115
7674 23:45:20.676401 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
7675 23:45:20.676513
7676 23:45:20.676606
7677 23:45:20.676687 ==
7678 23:45:20.680065 Dram Type= 6, Freq= 0, CH_0, rank 0
7679 23:45:20.683042 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7680 23:45:20.683122 ==
7681 23:45:20.683203
7682 23:45:20.683265
7683 23:45:20.686388 TX Vref Scan disable
7684 23:45:20.689846 == TX Byte 0 ==
7685 23:45:20.692962 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
7686 23:45:20.696363 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7687 23:45:20.699517 == TX Byte 1 ==
7688 23:45:20.703126 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7689 23:45:20.706670 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7690 23:45:20.706776 ==
7691 23:45:20.709603 Dram Type= 6, Freq= 0, CH_0, rank 0
7692 23:45:20.712981 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7693 23:45:20.716212 ==
7694 23:45:20.727893
7695 23:45:20.731385 TX Vref early break, caculate TX vref
7696 23:45:20.734546 TX Vref=16, minBit 11, minWin=22, winSum=372
7697 23:45:20.738323 TX Vref=18, minBit 0, minWin=23, winSum=378
7698 23:45:20.741241 TX Vref=20, minBit 8, minWin=23, winSum=391
7699 23:45:20.744446 TX Vref=22, minBit 4, minWin=24, winSum=402
7700 23:45:20.747954 TX Vref=24, minBit 4, minWin=24, winSum=404
7701 23:45:20.754628 TX Vref=26, minBit 2, minWin=25, winSum=413
7702 23:45:20.757907 TX Vref=28, minBit 4, minWin=25, winSum=416
7703 23:45:20.761268 TX Vref=30, minBit 3, minWin=25, winSum=412
7704 23:45:20.764482 TX Vref=32, minBit 4, minWin=24, winSum=400
7705 23:45:20.767991 TX Vref=34, minBit 9, minWin=23, winSum=391
7706 23:45:20.774646 [TxChooseVref] Worse bit 4, Min win 25, Win sum 416, Final Vref 28
7707 23:45:20.774780
7708 23:45:20.778034 Final TX Range 0 Vref 28
7709 23:45:20.778127
7710 23:45:20.778194 ==
7711 23:45:20.780861 Dram Type= 6, Freq= 0, CH_0, rank 0
7712 23:45:20.784242 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7713 23:45:20.784344 ==
7714 23:45:20.784414
7715 23:45:20.784476
7716 23:45:20.787719 TX Vref Scan disable
7717 23:45:20.794174 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7718 23:45:20.794325 == TX Byte 0 ==
7719 23:45:20.797572 u2DelayCellOfst[0]=15 cells (4 PI)
7720 23:45:20.800706 u2DelayCellOfst[1]=18 cells (5 PI)
7721 23:45:20.804099 u2DelayCellOfst[2]=15 cells (4 PI)
7722 23:45:20.807372 u2DelayCellOfst[3]=15 cells (4 PI)
7723 23:45:20.810647 u2DelayCellOfst[4]=11 cells (3 PI)
7724 23:45:20.814243 u2DelayCellOfst[5]=0 cells (0 PI)
7725 23:45:20.817750 u2DelayCellOfst[6]=18 cells (5 PI)
7726 23:45:20.821050 u2DelayCellOfst[7]=18 cells (5 PI)
7727 23:45:20.824278 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7728 23:45:20.827605 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7729 23:45:20.831083 == TX Byte 1 ==
7730 23:45:20.834350 u2DelayCellOfst[8]=0 cells (0 PI)
7731 23:45:20.834447 u2DelayCellOfst[9]=0 cells (0 PI)
7732 23:45:20.837338 u2DelayCellOfst[10]=3 cells (1 PI)
7733 23:45:20.840464 u2DelayCellOfst[11]=0 cells (0 PI)
7734 23:45:20.843825 u2DelayCellOfst[12]=11 cells (3 PI)
7735 23:45:20.847227 u2DelayCellOfst[13]=11 cells (3 PI)
7736 23:45:20.850570 u2DelayCellOfst[14]=15 cells (4 PI)
7737 23:45:20.853899 u2DelayCellOfst[15]=7 cells (2 PI)
7738 23:45:20.857353 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7739 23:45:20.863652 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7740 23:45:20.863758 DramC Write-DBI on
7741 23:45:20.863827 ==
7742 23:45:20.867228 Dram Type= 6, Freq= 0, CH_0, rank 0
7743 23:45:20.873692 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7744 23:45:20.873837 ==
7745 23:45:20.873952
7746 23:45:20.874044
7747 23:45:20.874149 TX Vref Scan disable
7748 23:45:20.877474 == TX Byte 0 ==
7749 23:45:20.880861 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
7750 23:45:20.884230 == TX Byte 1 ==
7751 23:45:20.887550 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7752 23:45:20.891079 DramC Write-DBI off
7753 23:45:20.891163
7754 23:45:20.891228 [DATLAT]
7755 23:45:20.891289 Freq=1600, CH0 RK0
7756 23:45:20.891350
7757 23:45:20.894299 DATLAT Default: 0xf
7758 23:45:20.894409 0, 0xFFFF, sum = 0
7759 23:45:20.897490 1, 0xFFFF, sum = 0
7760 23:45:20.900899 2, 0xFFFF, sum = 0
7761 23:45:20.900998 3, 0xFFFF, sum = 0
7762 23:45:20.904334 4, 0xFFFF, sum = 0
7763 23:45:20.904458 5, 0xFFFF, sum = 0
7764 23:45:20.907478 6, 0xFFFF, sum = 0
7765 23:45:20.907600 7, 0xFFFF, sum = 0
7766 23:45:20.910953 8, 0xFFFF, sum = 0
7767 23:45:20.911067 9, 0xFFFF, sum = 0
7768 23:45:20.914307 10, 0xFFFF, sum = 0
7769 23:45:20.914422 11, 0xFFFF, sum = 0
7770 23:45:20.917171 12, 0xFFFF, sum = 0
7771 23:45:20.917276 13, 0xFFFF, sum = 0
7772 23:45:20.920776 14, 0x0, sum = 1
7773 23:45:20.920855 15, 0x0, sum = 2
7774 23:45:20.923862 16, 0x0, sum = 3
7775 23:45:20.923969 17, 0x0, sum = 4
7776 23:45:20.927190 best_step = 15
7777 23:45:20.927281
7778 23:45:20.927357 ==
7779 23:45:20.930964 Dram Type= 6, Freq= 0, CH_0, rank 0
7780 23:45:20.933657 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7781 23:45:20.933736 ==
7782 23:45:20.937082 RX Vref Scan: 1
7783 23:45:20.937192
7784 23:45:20.937298 Set Vref Range= 24 -> 127
7785 23:45:20.937362
7786 23:45:20.940411 RX Vref 24 -> 127, step: 1
7787 23:45:20.940512
7788 23:45:20.944086 RX Delay 11 -> 252, step: 4
7789 23:45:20.944194
7790 23:45:20.947509 Set Vref, RX VrefLevel [Byte0]: 24
7791 23:45:20.950914 [Byte1]: 24
7792 23:45:20.950996
7793 23:45:20.954153 Set Vref, RX VrefLevel [Byte0]: 25
7794 23:45:20.956925 [Byte1]: 25
7795 23:45:20.960248
7796 23:45:20.960368 Set Vref, RX VrefLevel [Byte0]: 26
7797 23:45:20.963649 [Byte1]: 26
7798 23:45:20.968137
7799 23:45:20.968252 Set Vref, RX VrefLevel [Byte0]: 27
7800 23:45:20.971311 [Byte1]: 27
7801 23:45:20.975429
7802 23:45:20.975539 Set Vref, RX VrefLevel [Byte0]: 28
7803 23:45:20.979064 [Byte1]: 28
7804 23:45:20.983209
7805 23:45:20.983312 Set Vref, RX VrefLevel [Byte0]: 29
7806 23:45:20.986571 [Byte1]: 29
7807 23:45:20.991080
7808 23:45:20.991180 Set Vref, RX VrefLevel [Byte0]: 30
7809 23:45:20.994328 [Byte1]: 30
7810 23:45:20.998245
7811 23:45:20.998357 Set Vref, RX VrefLevel [Byte0]: 31
7812 23:45:21.001754 [Byte1]: 31
7813 23:45:21.006076
7814 23:45:21.006194 Set Vref, RX VrefLevel [Byte0]: 32
7815 23:45:21.009332 [Byte1]: 32
7816 23:45:21.014046
7817 23:45:21.014170 Set Vref, RX VrefLevel [Byte0]: 33
7818 23:45:21.017026 [Byte1]: 33
7819 23:45:21.021600
7820 23:45:21.021677 Set Vref, RX VrefLevel [Byte0]: 34
7821 23:45:21.024765 [Byte1]: 34
7822 23:45:21.029039
7823 23:45:21.029144 Set Vref, RX VrefLevel [Byte0]: 35
7824 23:45:21.032368 [Byte1]: 35
7825 23:45:21.036618
7826 23:45:21.036700 Set Vref, RX VrefLevel [Byte0]: 36
7827 23:45:21.039572 [Byte1]: 36
7828 23:45:21.044067
7829 23:45:21.044158 Set Vref, RX VrefLevel [Byte0]: 37
7830 23:45:21.047355 [Byte1]: 37
7831 23:45:21.051817
7832 23:45:21.051904 Set Vref, RX VrefLevel [Byte0]: 38
7833 23:45:21.055267 [Byte1]: 38
7834 23:45:21.059715
7835 23:45:21.059804 Set Vref, RX VrefLevel [Byte0]: 39
7836 23:45:21.062502 [Byte1]: 39
7837 23:45:21.067073
7838 23:45:21.067185 Set Vref, RX VrefLevel [Byte0]: 40
7839 23:45:21.070003 [Byte1]: 40
7840 23:45:21.074424
7841 23:45:21.074532 Set Vref, RX VrefLevel [Byte0]: 41
7842 23:45:21.077841 [Byte1]: 41
7843 23:45:21.082358
7844 23:45:21.082481 Set Vref, RX VrefLevel [Byte0]: 42
7845 23:45:21.085677 [Byte1]: 42
7846 23:45:21.089897
7847 23:45:21.089998 Set Vref, RX VrefLevel [Byte0]: 43
7848 23:45:21.093207 [Byte1]: 43
7849 23:45:21.097606
7850 23:45:21.097698 Set Vref, RX VrefLevel [Byte0]: 44
7851 23:45:21.101115 [Byte1]: 44
7852 23:45:21.105098
7853 23:45:21.105182 Set Vref, RX VrefLevel [Byte0]: 45
7854 23:45:21.108281 [Byte1]: 45
7855 23:45:21.112928
7856 23:45:21.113046 Set Vref, RX VrefLevel [Byte0]: 46
7857 23:45:21.116136 [Byte1]: 46
7858 23:45:21.120413
7859 23:45:21.120530 Set Vref, RX VrefLevel [Byte0]: 47
7860 23:45:21.123908 [Byte1]: 47
7861 23:45:21.128145
7862 23:45:21.128236 Set Vref, RX VrefLevel [Byte0]: 48
7863 23:45:21.131340 [Byte1]: 48
7864 23:45:21.135682
7865 23:45:21.135776 Set Vref, RX VrefLevel [Byte0]: 49
7866 23:45:21.138788 [Byte1]: 49
7867 23:45:21.142994
7868 23:45:21.143080 Set Vref, RX VrefLevel [Byte0]: 50
7869 23:45:21.146290 [Byte1]: 50
7870 23:45:21.150724
7871 23:45:21.150821 Set Vref, RX VrefLevel [Byte0]: 51
7872 23:45:21.154107 [Byte1]: 51
7873 23:45:21.158475
7874 23:45:21.158558 Set Vref, RX VrefLevel [Byte0]: 52
7875 23:45:21.161944 [Byte1]: 52
7876 23:45:21.166081
7877 23:45:21.166176 Set Vref, RX VrefLevel [Byte0]: 53
7878 23:45:21.169283 [Byte1]: 53
7879 23:45:21.173755
7880 23:45:21.173864 Set Vref, RX VrefLevel [Byte0]: 54
7881 23:45:21.177031 [Byte1]: 54
7882 23:45:21.181579
7883 23:45:21.181662 Set Vref, RX VrefLevel [Byte0]: 55
7884 23:45:21.184714 [Byte1]: 55
7885 23:45:21.188849
7886 23:45:21.188931 Set Vref, RX VrefLevel [Byte0]: 56
7887 23:45:21.192191 [Byte1]: 56
7888 23:45:21.196471
7889 23:45:21.196594 Set Vref, RX VrefLevel [Byte0]: 57
7890 23:45:21.199770 [Byte1]: 57
7891 23:45:21.204170
7892 23:45:21.204254 Set Vref, RX VrefLevel [Byte0]: 58
7893 23:45:21.207609 [Byte1]: 58
7894 23:45:21.211595
7895 23:45:21.211684 Set Vref, RX VrefLevel [Byte0]: 59
7896 23:45:21.214960 [Byte1]: 59
7897 23:45:21.219404
7898 23:45:21.219491 Set Vref, RX VrefLevel [Byte0]: 60
7899 23:45:21.222592 [Byte1]: 60
7900 23:45:21.227320
7901 23:45:21.227406 Set Vref, RX VrefLevel [Byte0]: 61
7902 23:45:21.229943 [Byte1]: 61
7903 23:45:21.234515
7904 23:45:21.234630 Set Vref, RX VrefLevel [Byte0]: 62
7905 23:45:21.237831 [Byte1]: 62
7906 23:45:21.242173
7907 23:45:21.242287 Set Vref, RX VrefLevel [Byte0]: 63
7908 23:45:21.245572 [Byte1]: 63
7909 23:45:21.249951
7910 23:45:21.250063 Set Vref, RX VrefLevel [Byte0]: 64
7911 23:45:21.253192 [Byte1]: 64
7912 23:45:21.257332
7913 23:45:21.257440 Set Vref, RX VrefLevel [Byte0]: 65
7914 23:45:21.260843 [Byte1]: 65
7915 23:45:21.265006
7916 23:45:21.265131 Set Vref, RX VrefLevel [Byte0]: 66
7917 23:45:21.268420 [Byte1]: 66
7918 23:45:21.272305
7919 23:45:21.272387 Set Vref, RX VrefLevel [Byte0]: 67
7920 23:45:21.275738 [Byte1]: 67
7921 23:45:21.280273
7922 23:45:21.280351 Set Vref, RX VrefLevel [Byte0]: 68
7923 23:45:21.283632 [Byte1]: 68
7924 23:45:21.287613
7925 23:45:21.287747 Set Vref, RX VrefLevel [Byte0]: 69
7926 23:45:21.290970 [Byte1]: 69
7927 23:45:21.295126
7928 23:45:21.295259 Set Vref, RX VrefLevel [Byte0]: 70
7929 23:45:21.298619 [Byte1]: 70
7930 23:45:21.302875
7931 23:45:21.302994 Set Vref, RX VrefLevel [Byte0]: 71
7932 23:45:21.306448 [Byte1]: 71
7933 23:45:21.310517
7934 23:45:21.310644 Set Vref, RX VrefLevel [Byte0]: 72
7935 23:45:21.314055 [Byte1]: 72
7936 23:45:21.318183
7937 23:45:21.318311 Set Vref, RX VrefLevel [Byte0]: 73
7938 23:45:21.321631 [Byte1]: 73
7939 23:45:21.325699
7940 23:45:21.325831 Set Vref, RX VrefLevel [Byte0]: 74
7941 23:45:21.329256 [Byte1]: 74
7942 23:45:21.333322
7943 23:45:21.333454 Set Vref, RX VrefLevel [Byte0]: 75
7944 23:45:21.336876 [Byte1]: 75
7945 23:45:21.340946
7946 23:45:21.341034 Set Vref, RX VrefLevel [Byte0]: 76
7947 23:45:21.344355 [Byte1]: 76
7948 23:45:21.348688
7949 23:45:21.348778 Set Vref, RX VrefLevel [Byte0]: 77
7950 23:45:21.352170 [Byte1]: 77
7951 23:45:21.356422
7952 23:45:21.356548 Final RX Vref Byte 0 = 62 to rank0
7953 23:45:21.359943 Final RX Vref Byte 1 = 59 to rank0
7954 23:45:21.362727 Final RX Vref Byte 0 = 62 to rank1
7955 23:45:21.366254 Final RX Vref Byte 1 = 59 to rank1==
7956 23:45:21.369483 Dram Type= 6, Freq= 0, CH_0, rank 0
7957 23:45:21.375948 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7958 23:45:21.376068 ==
7959 23:45:21.376176 DQS Delay:
7960 23:45:21.379128 DQS0 = 0, DQS1 = 0
7961 23:45:21.379249 DQM Delay:
7962 23:45:21.379350 DQM0 = 126, DQM1 = 120
7963 23:45:21.382618 DQ Delay:
7964 23:45:21.385995 DQ0 =126, DQ1 =128, DQ2 =126, DQ3 =122
7965 23:45:21.389579 DQ4 =126, DQ5 =112, DQ6 =132, DQ7 =138
7966 23:45:21.392851 DQ8 =112, DQ9 =108, DQ10 =120, DQ11 =114
7967 23:45:21.396210 DQ12 =124, DQ13 =124, DQ14 =130, DQ15 =128
7968 23:45:21.396332
7969 23:45:21.396426
7970 23:45:21.396520
7971 23:45:21.399411 [DramC_TX_OE_Calibration] TA2
7972 23:45:21.402248 Original DQ_B0 (3 6) =30, OEN = 27
7973 23:45:21.405797 Original DQ_B1 (3 6) =30, OEN = 27
7974 23:45:21.409002 24, 0x0, End_B0=24 End_B1=24
7975 23:45:21.409084 25, 0x0, End_B0=25 End_B1=25
7976 23:45:21.412647 26, 0x0, End_B0=26 End_B1=26
7977 23:45:21.415417 27, 0x0, End_B0=27 End_B1=27
7978 23:45:21.418942 28, 0x0, End_B0=28 End_B1=28
7979 23:45:21.422554 29, 0x0, End_B0=29 End_B1=29
7980 23:45:21.422644 30, 0x0, End_B0=30 End_B1=30
7981 23:45:21.425333 31, 0x5151, End_B0=30 End_B1=30
7982 23:45:21.428638 Byte0 end_step=30 best_step=27
7983 23:45:21.432117 Byte1 end_step=30 best_step=27
7984 23:45:21.435367 Byte0 TX OE(2T, 0.5T) = (3, 3)
7985 23:45:21.438971 Byte1 TX OE(2T, 0.5T) = (3, 3)
7986 23:45:21.439059
7987 23:45:21.439126
7988 23:45:21.445303 [DQSOSCAuto] RK0, (LSB)MR18= 0x1515, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
7989 23:45:21.448737 CH0 RK0: MR19=303, MR18=1515
7990 23:45:21.455444 CH0_RK0: MR19=0x303, MR18=0x1515, DQSOSC=399, MR23=63, INC=23, DEC=15
7991 23:45:21.455607
7992 23:45:21.458581 ----->DramcWriteLeveling(PI) begin...
7993 23:45:21.458712 ==
7994 23:45:21.461996 Dram Type= 6, Freq= 0, CH_0, rank 1
7995 23:45:21.465301 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7996 23:45:21.465428 ==
7997 23:45:21.468421 Write leveling (Byte 0): 32 => 32
7998 23:45:21.472000 Write leveling (Byte 1): 28 => 28
7999 23:45:21.475338 DramcWriteLeveling(PI) end<-----
8000 23:45:21.475445
8001 23:45:21.475549 ==
8002 23:45:21.478246 Dram Type= 6, Freq= 0, CH_0, rank 1
8003 23:45:21.481607 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8004 23:45:21.485099 ==
8005 23:45:21.485200 [Gating] SW mode calibration
8006 23:45:21.494968 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8007 23:45:21.498576 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8008 23:45:21.501331 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8009 23:45:21.508364 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8010 23:45:21.511551 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8011 23:45:21.514850 1 4 12 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
8012 23:45:21.521200 1 4 16 | B1->B0 | 2929 3434 | 1 1 | (1 1) (1 1)
8013 23:45:21.524454 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8014 23:45:21.527981 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8015 23:45:21.534564 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8016 23:45:21.537993 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8017 23:45:21.540967 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8018 23:45:21.547851 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8019 23:45:21.551171 1 5 12 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 0)
8020 23:45:21.554303 1 5 16 | B1->B0 | 3333 2323 | 0 0 | (0 0) (0 0)
8021 23:45:21.561390 1 5 20 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
8022 23:45:21.564755 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8023 23:45:21.567871 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8024 23:45:21.574389 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8025 23:45:21.577826 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8026 23:45:21.580791 1 6 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8027 23:45:21.587662 1 6 12 | B1->B0 | 2323 4242 | 0 1 | (0 0) (0 0)
8028 23:45:21.590977 1 6 16 | B1->B0 | 3333 4646 | 0 0 | (1 1) (0 0)
8029 23:45:21.594163 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8030 23:45:21.600697 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8031 23:45:21.604052 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8032 23:45:21.607571 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8033 23:45:21.613959 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8034 23:45:21.617736 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8035 23:45:21.620415 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8036 23:45:21.627437 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8037 23:45:21.630928 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8038 23:45:21.634116 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8039 23:45:21.640379 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8040 23:45:21.643716 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8041 23:45:21.647185 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8042 23:45:21.653898 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8043 23:45:21.656824 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8044 23:45:21.660450 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8045 23:45:21.666723 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8046 23:45:21.669947 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8047 23:45:21.673776 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8048 23:45:21.680336 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8049 23:45:21.683409 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8050 23:45:21.686849 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8051 23:45:21.693289 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8052 23:45:21.693404 Total UI for P1: 0, mck2ui 16
8053 23:45:21.696857 best dqsien dly found for B0: ( 1, 9, 8)
8054 23:45:21.703627 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8055 23:45:21.706801 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8056 23:45:21.710189 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8057 23:45:21.713191 Total UI for P1: 0, mck2ui 16
8058 23:45:21.716473 best dqsien dly found for B1: ( 1, 9, 18)
8059 23:45:21.720167 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8060 23:45:21.726229 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8061 23:45:21.726347
8062 23:45:21.729888 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8063 23:45:21.733349 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8064 23:45:21.736114 [Gating] SW calibration Done
8065 23:45:21.736214 ==
8066 23:45:21.739765 Dram Type= 6, Freq= 0, CH_0, rank 1
8067 23:45:21.743140 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8068 23:45:21.743226 ==
8069 23:45:21.746605 RX Vref Scan: 0
8070 23:45:21.746685
8071 23:45:21.746758 RX Vref 0 -> 0, step: 1
8072 23:45:21.746826
8073 23:45:21.749562 RX Delay 0 -> 252, step: 8
8074 23:45:21.752916 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8075 23:45:21.756325 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8076 23:45:21.762818 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8077 23:45:21.766240 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8078 23:45:21.769513 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8079 23:45:21.772784 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
8080 23:45:21.776498 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8081 23:45:21.782911 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8082 23:45:21.786467 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8083 23:45:21.789793 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8084 23:45:21.792581 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8085 23:45:21.796148 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8086 23:45:21.802587 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8087 23:45:21.806057 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
8088 23:45:21.809321 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8089 23:45:21.812279 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8090 23:45:21.812401 ==
8091 23:45:21.815694 Dram Type= 6, Freq= 0, CH_0, rank 1
8092 23:45:21.822577 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8093 23:45:21.822697 ==
8094 23:45:21.822767 DQS Delay:
8095 23:45:21.825711 DQS0 = 0, DQS1 = 0
8096 23:45:21.825833 DQM Delay:
8097 23:45:21.828997 DQM0 = 128, DQM1 = 121
8098 23:45:21.829085 DQ Delay:
8099 23:45:21.832564 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
8100 23:45:21.835467 DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =139
8101 23:45:21.839133 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
8102 23:45:21.842078 DQ12 =127, DQ13 =127, DQ14 =131, DQ15 =127
8103 23:45:21.842170
8104 23:45:21.842237
8105 23:45:21.842298 ==
8106 23:45:21.845691 Dram Type= 6, Freq= 0, CH_0, rank 1
8107 23:45:21.852018 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8108 23:45:21.852123 ==
8109 23:45:21.852200
8110 23:45:21.852261
8111 23:45:21.852323 TX Vref Scan disable
8112 23:45:21.855563 == TX Byte 0 ==
8113 23:45:21.859159 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8114 23:45:21.865783 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
8115 23:45:21.865888 == TX Byte 1 ==
8116 23:45:21.868763 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8117 23:45:21.875504 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8118 23:45:21.875630 ==
8119 23:45:21.879077 Dram Type= 6, Freq= 0, CH_0, rank 1
8120 23:45:21.882049 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8121 23:45:21.882141 ==
8122 23:45:21.894918
8123 23:45:21.898388 TX Vref early break, caculate TX vref
8124 23:45:21.901473 TX Vref=16, minBit 0, minWin=22, winSum=366
8125 23:45:21.905063 TX Vref=18, minBit 8, minWin=22, winSum=373
8126 23:45:21.908277 TX Vref=20, minBit 8, minWin=22, winSum=377
8127 23:45:21.911446 TX Vref=22, minBit 8, minWin=23, winSum=389
8128 23:45:21.914939 TX Vref=24, minBit 8, minWin=24, winSum=402
8129 23:45:21.921152 TX Vref=26, minBit 8, minWin=24, winSum=410
8130 23:45:21.924423 TX Vref=28, minBit 7, minWin=24, winSum=407
8131 23:45:21.927934 TX Vref=30, minBit 8, minWin=24, winSum=406
8132 23:45:21.931418 TX Vref=32, minBit 8, minWin=24, winSum=403
8133 23:45:21.934665 TX Vref=34, minBit 8, minWin=22, winSum=383
8134 23:45:21.941341 [TxChooseVref] Worse bit 8, Min win 24, Win sum 410, Final Vref 26
8135 23:45:21.941457
8136 23:45:21.944651 Final TX Range 0 Vref 26
8137 23:45:21.944764
8138 23:45:21.944858 ==
8139 23:45:21.947932 Dram Type= 6, Freq= 0, CH_0, rank 1
8140 23:45:21.951359 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8141 23:45:21.951450 ==
8142 23:45:21.951516
8143 23:45:21.951577
8144 23:45:21.954857 TX Vref Scan disable
8145 23:45:21.961261 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8146 23:45:21.961354 == TX Byte 0 ==
8147 23:45:21.964768 u2DelayCellOfst[0]=11 cells (3 PI)
8148 23:45:21.968149 u2DelayCellOfst[1]=18 cells (5 PI)
8149 23:45:21.971031 u2DelayCellOfst[2]=11 cells (3 PI)
8150 23:45:21.974419 u2DelayCellOfst[3]=7 cells (2 PI)
8151 23:45:21.977904 u2DelayCellOfst[4]=7 cells (2 PI)
8152 23:45:21.980931 u2DelayCellOfst[5]=0 cells (0 PI)
8153 23:45:21.984188 u2DelayCellOfst[6]=18 cells (5 PI)
8154 23:45:21.984295 u2DelayCellOfst[7]=15 cells (4 PI)
8155 23:45:21.991143 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
8156 23:45:21.994433 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
8157 23:45:21.997783 == TX Byte 1 ==
8158 23:45:21.997933 u2DelayCellOfst[8]=0 cells (0 PI)
8159 23:45:22.000974 u2DelayCellOfst[9]=0 cells (0 PI)
8160 23:45:22.004326 u2DelayCellOfst[10]=7 cells (2 PI)
8161 23:45:22.007737 u2DelayCellOfst[11]=7 cells (2 PI)
8162 23:45:22.011137 u2DelayCellOfst[12]=15 cells (4 PI)
8163 23:45:22.014456 u2DelayCellOfst[13]=11 cells (3 PI)
8164 23:45:22.017809 u2DelayCellOfst[14]=15 cells (4 PI)
8165 23:45:22.021111 u2DelayCellOfst[15]=11 cells (3 PI)
8166 23:45:22.023996 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8167 23:45:22.031007 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8168 23:45:22.031119 DramC Write-DBI on
8169 23:45:22.031218 ==
8170 23:45:22.034274 Dram Type= 6, Freq= 0, CH_0, rank 1
8171 23:45:22.037542 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8172 23:45:22.040720 ==
8173 23:45:22.040822
8174 23:45:22.040891
8175 23:45:22.040953 TX Vref Scan disable
8176 23:45:22.044443 == TX Byte 0 ==
8177 23:45:22.047309 Update DQM dly =732 (2 ,6, 28) DQM OEN =(3 ,3)
8178 23:45:22.050899 == TX Byte 1 ==
8179 23:45:22.053904 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8180 23:45:22.057167 DramC Write-DBI off
8181 23:45:22.057257
8182 23:45:22.057324 [DATLAT]
8183 23:45:22.057386 Freq=1600, CH0 RK1
8184 23:45:22.057446
8185 23:45:22.060946 DATLAT Default: 0xf
8186 23:45:22.061034 0, 0xFFFF, sum = 0
8187 23:45:22.063931 1, 0xFFFF, sum = 0
8188 23:45:22.067431 2, 0xFFFF, sum = 0
8189 23:45:22.067519 3, 0xFFFF, sum = 0
8190 23:45:22.070903 4, 0xFFFF, sum = 0
8191 23:45:22.070993 5, 0xFFFF, sum = 0
8192 23:45:22.074305 6, 0xFFFF, sum = 0
8193 23:45:22.074394 7, 0xFFFF, sum = 0
8194 23:45:22.077271 8, 0xFFFF, sum = 0
8195 23:45:22.077360 9, 0xFFFF, sum = 0
8196 23:45:22.080691 10, 0xFFFF, sum = 0
8197 23:45:22.080782 11, 0xFFFF, sum = 0
8198 23:45:22.084172 12, 0xFFFF, sum = 0
8199 23:45:22.084263 13, 0xCFFF, sum = 0
8200 23:45:22.087187 14, 0x0, sum = 1
8201 23:45:22.087278 15, 0x0, sum = 2
8202 23:45:22.090563 16, 0x0, sum = 3
8203 23:45:22.090651 17, 0x0, sum = 4
8204 23:45:22.094002 best_step = 15
8205 23:45:22.094092
8206 23:45:22.094158 ==
8207 23:45:22.097339 Dram Type= 6, Freq= 0, CH_0, rank 1
8208 23:45:22.100440 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8209 23:45:22.100532 ==
8210 23:45:22.103525 RX Vref Scan: 0
8211 23:45:22.103635
8212 23:45:22.103729 RX Vref 0 -> 0, step: 1
8213 23:45:22.103819
8214 23:45:22.106886 RX Delay 3 -> 252, step: 4
8215 23:45:22.110637 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8216 23:45:22.117021 iDelay=191, Bit 1, Center 126 (71 ~ 182) 112
8217 23:45:22.120173 iDelay=191, Bit 2, Center 120 (67 ~ 174) 108
8218 23:45:22.123727 iDelay=191, Bit 3, Center 120 (63 ~ 178) 116
8219 23:45:22.126522 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8220 23:45:22.133487 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8221 23:45:22.137082 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8222 23:45:22.140165 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8223 23:45:22.143301 iDelay=191, Bit 8, Center 112 (55 ~ 170) 116
8224 23:45:22.146588 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8225 23:45:22.153118 iDelay=191, Bit 10, Center 118 (59 ~ 178) 120
8226 23:45:22.156621 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8227 23:45:22.159837 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8228 23:45:22.163455 iDelay=191, Bit 13, Center 122 (67 ~ 178) 112
8229 23:45:22.166714 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8230 23:45:22.173461 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8231 23:45:22.173640 ==
8232 23:45:22.176228 Dram Type= 6, Freq= 0, CH_0, rank 1
8233 23:45:22.180258 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8234 23:45:22.180408 ==
8235 23:45:22.180528 DQS Delay:
8236 23:45:22.183074 DQS0 = 0, DQS1 = 0
8237 23:45:22.183209 DQM Delay:
8238 23:45:22.186569 DQM0 = 124, DQM1 = 118
8239 23:45:22.186698 DQ Delay:
8240 23:45:22.189831 DQ0 =124, DQ1 =126, DQ2 =120, DQ3 =120
8241 23:45:22.193177 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8242 23:45:22.196465 DQ8 =112, DQ9 =104, DQ10 =118, DQ11 =112
8243 23:45:22.199688 DQ12 =124, DQ13 =122, DQ14 =128, DQ15 =124
8244 23:45:22.199802
8245 23:45:22.203113
8246 23:45:22.203216
8247 23:45:22.203308 [DramC_TX_OE_Calibration] TA2
8248 23:45:22.206623 Original DQ_B0 (3 6) =30, OEN = 27
8249 23:45:22.209793 Original DQ_B1 (3 6) =30, OEN = 27
8250 23:45:22.212779 24, 0x0, End_B0=24 End_B1=24
8251 23:45:22.216275 25, 0x0, End_B0=25 End_B1=25
8252 23:45:22.220068 26, 0x0, End_B0=26 End_B1=26
8253 23:45:22.220206 27, 0x0, End_B0=27 End_B1=27
8254 23:45:22.222941 28, 0x0, End_B0=28 End_B1=28
8255 23:45:22.226202 29, 0x0, End_B0=29 End_B1=29
8256 23:45:22.229625 30, 0x0, End_B0=30 End_B1=30
8257 23:45:22.232967 31, 0x4141, End_B0=30 End_B1=30
8258 23:45:22.233124 Byte0 end_step=30 best_step=27
8259 23:45:22.236263 Byte1 end_step=30 best_step=27
8260 23:45:22.239182 Byte0 TX OE(2T, 0.5T) = (3, 3)
8261 23:45:22.242554 Byte1 TX OE(2T, 0.5T) = (3, 3)
8262 23:45:22.242687
8263 23:45:22.242784
8264 23:45:22.249574 [DQSOSCAuto] RK1, (LSB)MR18= 0x220f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 392 ps
8265 23:45:22.253111 CH0 RK1: MR19=303, MR18=220F
8266 23:45:22.259265 CH0_RK1: MR19=0x303, MR18=0x220F, DQSOSC=392, MR23=63, INC=24, DEC=16
8267 23:45:22.262781 [RxdqsGatingPostProcess] freq 1600
8268 23:45:22.269143 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8269 23:45:22.272696 best DQS0 dly(2T, 0.5T) = (1, 1)
8270 23:45:22.272840 best DQS1 dly(2T, 0.5T) = (1, 1)
8271 23:45:22.275830 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8272 23:45:22.279558 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8273 23:45:22.282806 best DQS0 dly(2T, 0.5T) = (1, 1)
8274 23:45:22.285669 best DQS1 dly(2T, 0.5T) = (1, 1)
8275 23:45:22.289246 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8276 23:45:22.292830 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8277 23:45:22.295823 Pre-setting of DQS Precalculation
8278 23:45:22.299076 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8279 23:45:22.302370 ==
8280 23:45:22.305976 Dram Type= 6, Freq= 0, CH_1, rank 0
8281 23:45:22.309371 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8282 23:45:22.309498 ==
8283 23:45:22.312371 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8284 23:45:22.319021 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8285 23:45:22.322649 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8286 23:45:22.328937 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8287 23:45:22.337283 [CA 0] Center 41 (12~71) winsize 60
8288 23:45:22.340513 [CA 1] Center 42 (12~72) winsize 61
8289 23:45:22.344077 [CA 2] Center 38 (9~67) winsize 59
8290 23:45:22.347630 [CA 3] Center 37 (8~66) winsize 59
8291 23:45:22.350512 [CA 4] Center 37 (8~67) winsize 60
8292 23:45:22.354091 [CA 5] Center 36 (7~66) winsize 60
8293 23:45:22.354201
8294 23:45:22.356932 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8295 23:45:22.357021
8296 23:45:22.360434 [CATrainingPosCal] consider 1 rank data
8297 23:45:22.363565 u2DelayCellTimex100 = 258/100 ps
8298 23:45:22.367181 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8299 23:45:22.373651 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8300 23:45:22.377042 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8301 23:45:22.380319 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8302 23:45:22.384035 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8303 23:45:22.386967 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8304 23:45:22.387118
8305 23:45:22.390283 CA PerBit enable=1, Macro0, CA PI delay=36
8306 23:45:22.390417
8307 23:45:22.393337 [CBTSetCACLKResult] CA Dly = 36
8308 23:45:22.396784 CS Dly: 9 (0~40)
8309 23:45:22.400226 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8310 23:45:22.403673 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8311 23:45:22.403818 ==
8312 23:45:22.406990 Dram Type= 6, Freq= 0, CH_1, rank 1
8313 23:45:22.409812 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8314 23:45:22.413315 ==
8315 23:45:22.416999 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8316 23:45:22.419971 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8317 23:45:22.426834 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8318 23:45:22.430201 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8319 23:45:22.440503 [CA 0] Center 41 (12~71) winsize 60
8320 23:45:22.443444 [CA 1] Center 42 (12~72) winsize 61
8321 23:45:22.446729 [CA 2] Center 37 (8~67) winsize 60
8322 23:45:22.450296 [CA 3] Center 36 (7~66) winsize 60
8323 23:45:22.453854 [CA 4] Center 37 (7~67) winsize 61
8324 23:45:22.456695 [CA 5] Center 36 (6~66) winsize 61
8325 23:45:22.456807
8326 23:45:22.460216 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8327 23:45:22.460326
8328 23:45:22.463804 [CATrainingPosCal] consider 2 rank data
8329 23:45:22.466617 u2DelayCellTimex100 = 258/100 ps
8330 23:45:22.473132 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8331 23:45:22.477132 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8332 23:45:22.479863 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8333 23:45:22.483215 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8334 23:45:22.486481 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8335 23:45:22.489626 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8336 23:45:22.489738
8337 23:45:22.493240 CA PerBit enable=1, Macro0, CA PI delay=36
8338 23:45:22.493337
8339 23:45:22.496655 [CBTSetCACLKResult] CA Dly = 36
8340 23:45:22.499675 CS Dly: 10 (0~43)
8341 23:45:22.503059 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8342 23:45:22.506545 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8343 23:45:22.506666
8344 23:45:22.509436 ----->DramcWriteLeveling(PI) begin...
8345 23:45:22.509576 ==
8346 23:45:22.512898 Dram Type= 6, Freq= 0, CH_1, rank 0
8347 23:45:22.519863 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8348 23:45:22.519960 ==
8349 23:45:22.522903 Write leveling (Byte 0): 24 => 24
8350 23:45:22.526351 Write leveling (Byte 1): 28 => 28
8351 23:45:22.526447 DramcWriteLeveling(PI) end<-----
8352 23:45:22.526534
8353 23:45:22.529721 ==
8354 23:45:22.532595 Dram Type= 6, Freq= 0, CH_1, rank 0
8355 23:45:22.535868 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8356 23:45:22.536002 ==
8357 23:45:22.539456 [Gating] SW mode calibration
8358 23:45:22.545948 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8359 23:45:22.549315 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8360 23:45:22.555845 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8361 23:45:22.559263 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8362 23:45:22.562239 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8363 23:45:22.569156 1 4 12 | B1->B0 | 2525 2424 | 0 0 | (0 0) (0 0)
8364 23:45:22.572541 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
8365 23:45:22.575416 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8366 23:45:22.582654 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8367 23:45:22.586004 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8368 23:45:22.588796 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8369 23:45:22.595326 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8370 23:45:22.598644 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8371 23:45:22.602344 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8372 23:45:22.608895 1 5 16 | B1->B0 | 2626 2727 | 0 0 | (0 1) (1 0)
8373 23:45:22.612301 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8374 23:45:22.615523 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8375 23:45:22.622105 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8376 23:45:22.625584 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8377 23:45:22.628998 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8378 23:45:22.635326 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8379 23:45:22.638564 1 6 12 | B1->B0 | 3434 2626 | 0 1 | (0 0) (0 0)
8380 23:45:22.642039 1 6 16 | B1->B0 | 4343 4140 | 0 1 | (0 0) (1 1)
8381 23:45:22.648668 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8382 23:45:22.651919 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8383 23:45:22.655158 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8384 23:45:22.662201 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8385 23:45:22.665497 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8386 23:45:22.668483 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8387 23:45:22.675111 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8388 23:45:22.678474 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8389 23:45:22.682039 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8390 23:45:22.685440 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8391 23:45:22.691715 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8392 23:45:22.695269 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8393 23:45:22.698676 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8394 23:45:22.705010 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8395 23:45:22.708351 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 23:45:22.711722 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8397 23:45:22.718712 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 23:45:22.721660 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 23:45:22.725052 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 23:45:22.731858 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 23:45:22.735210 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 23:45:22.738075 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 23:45:22.744879 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 23:45:22.748356 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8405 23:45:22.751780 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8406 23:45:22.755014 Total UI for P1: 0, mck2ui 16
8407 23:45:22.758173 best dqsien dly found for B0: ( 1, 9, 16)
8408 23:45:22.761624 Total UI for P1: 0, mck2ui 16
8409 23:45:22.764847 best dqsien dly found for B1: ( 1, 9, 16)
8410 23:45:22.768240 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8411 23:45:22.771647 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8412 23:45:22.771735
8413 23:45:22.777977 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8414 23:45:22.781190 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8415 23:45:22.784520 [Gating] SW calibration Done
8416 23:45:22.784673 ==
8417 23:45:22.787956 Dram Type= 6, Freq= 0, CH_1, rank 0
8418 23:45:22.791385 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8419 23:45:22.791514 ==
8420 23:45:22.791628 RX Vref Scan: 0
8421 23:45:22.794654
8422 23:45:22.794779 RX Vref 0 -> 0, step: 1
8423 23:45:22.794884
8424 23:45:22.797628 RX Delay 0 -> 252, step: 8
8425 23:45:22.800926 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8426 23:45:22.804289 iDelay=200, Bit 1, Center 127 (64 ~ 191) 128
8427 23:45:22.811010 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8428 23:45:22.814252 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8429 23:45:22.817500 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8430 23:45:22.821013 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8431 23:45:22.824465 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8432 23:45:22.831031 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8433 23:45:22.834340 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8434 23:45:22.837702 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8435 23:45:22.840629 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8436 23:45:22.844092 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8437 23:45:22.850852 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8438 23:45:22.854236 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8439 23:45:22.857562 iDelay=200, Bit 14, Center 131 (80 ~ 183) 104
8440 23:45:22.860381 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8441 23:45:22.860483 ==
8442 23:45:22.864314 Dram Type= 6, Freq= 0, CH_1, rank 0
8443 23:45:22.870462 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8444 23:45:22.870588 ==
8445 23:45:22.870685 DQS Delay:
8446 23:45:22.873967 DQS0 = 0, DQS1 = 0
8447 23:45:22.874058 DQM Delay:
8448 23:45:22.876864 DQM0 = 131, DQM1 = 125
8449 23:45:22.876975 DQ Delay:
8450 23:45:22.880791 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8451 23:45:22.883965 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =127
8452 23:45:22.886812 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8453 23:45:22.890379 DQ12 =135, DQ13 =135, DQ14 =131, DQ15 =135
8454 23:45:22.890493
8455 23:45:22.890591
8456 23:45:22.890680 ==
8457 23:45:22.893554 Dram Type= 6, Freq= 0, CH_1, rank 0
8458 23:45:22.899796 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8459 23:45:22.899879 ==
8460 23:45:22.899947
8461 23:45:22.900006
8462 23:45:22.900063 TX Vref Scan disable
8463 23:45:22.903488 == TX Byte 0 ==
8464 23:45:22.906680 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8465 23:45:22.913313 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8466 23:45:22.913419 == TX Byte 1 ==
8467 23:45:22.917005 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8468 23:45:22.923831 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8469 23:45:22.923935 ==
8470 23:45:22.926665 Dram Type= 6, Freq= 0, CH_1, rank 0
8471 23:45:22.930085 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8472 23:45:22.930161 ==
8473 23:45:22.942412
8474 23:45:22.945888 TX Vref early break, caculate TX vref
8475 23:45:22.949120 TX Vref=16, minBit 13, minWin=21, winSum=362
8476 23:45:22.952442 TX Vref=18, minBit 5, minWin=22, winSum=373
8477 23:45:22.955706 TX Vref=20, minBit 10, minWin=22, winSum=382
8478 23:45:22.959178 TX Vref=22, minBit 9, minWin=23, winSum=395
8479 23:45:22.962507 TX Vref=24, minBit 5, minWin=24, winSum=402
8480 23:45:22.969083 TX Vref=26, minBit 1, minWin=25, winSum=413
8481 23:45:22.972348 TX Vref=28, minBit 0, minWin=25, winSum=417
8482 23:45:22.975596 TX Vref=30, minBit 0, minWin=24, winSum=406
8483 23:45:22.979069 TX Vref=32, minBit 0, minWin=23, winSum=402
8484 23:45:22.982356 TX Vref=34, minBit 0, minWin=23, winSum=392
8485 23:45:22.989282 [TxChooseVref] Worse bit 0, Min win 25, Win sum 417, Final Vref 28
8486 23:45:22.989360
8487 23:45:22.992473 Final TX Range 0 Vref 28
8488 23:45:22.992580
8489 23:45:22.992644 ==
8490 23:45:22.995524 Dram Type= 6, Freq= 0, CH_1, rank 0
8491 23:45:22.998736 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8492 23:45:22.998817 ==
8493 23:45:22.998885
8494 23:45:22.998946
8495 23:45:23.001981 TX Vref Scan disable
8496 23:45:23.008671 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8497 23:45:23.008748 == TX Byte 0 ==
8498 23:45:23.011972 u2DelayCellOfst[0]=22 cells (6 PI)
8499 23:45:23.015533 u2DelayCellOfst[1]=15 cells (4 PI)
8500 23:45:23.018647 u2DelayCellOfst[2]=0 cells (0 PI)
8501 23:45:23.021933 u2DelayCellOfst[3]=7 cells (2 PI)
8502 23:45:23.025180 u2DelayCellOfst[4]=7 cells (2 PI)
8503 23:45:23.028972 u2DelayCellOfst[5]=26 cells (7 PI)
8504 23:45:23.032097 u2DelayCellOfst[6]=26 cells (7 PI)
8505 23:45:23.035316 u2DelayCellOfst[7]=7 cells (2 PI)
8506 23:45:23.038504 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8507 23:45:23.041926 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8508 23:45:23.045043 == TX Byte 1 ==
8509 23:45:23.048704 u2DelayCellOfst[8]=0 cells (0 PI)
8510 23:45:23.048782 u2DelayCellOfst[9]=7 cells (2 PI)
8511 23:45:23.051597 u2DelayCellOfst[10]=15 cells (4 PI)
8512 23:45:23.055204 u2DelayCellOfst[11]=7 cells (2 PI)
8513 23:45:23.058418 u2DelayCellOfst[12]=18 cells (5 PI)
8514 23:45:23.061732 u2DelayCellOfst[13]=22 cells (6 PI)
8515 23:45:23.065119 u2DelayCellOfst[14]=22 cells (6 PI)
8516 23:45:23.068418 u2DelayCellOfst[15]=22 cells (6 PI)
8517 23:45:23.071840 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8518 23:45:23.078315 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8519 23:45:23.078442 DramC Write-DBI on
8520 23:45:23.078535 ==
8521 23:45:23.081837 Dram Type= 6, Freq= 0, CH_1, rank 0
8522 23:45:23.088007 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8523 23:45:23.088108 ==
8524 23:45:23.088205
8525 23:45:23.088292
8526 23:45:23.088386 TX Vref Scan disable
8527 23:45:23.091863 == TX Byte 0 ==
8528 23:45:23.095281 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8529 23:45:23.098549 == TX Byte 1 ==
8530 23:45:23.101842 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8531 23:45:23.105329 DramC Write-DBI off
8532 23:45:23.105433
8533 23:45:23.105524 [DATLAT]
8534 23:45:23.105611 Freq=1600, CH1 RK0
8535 23:45:23.105702
8536 23:45:23.108379 DATLAT Default: 0xf
8537 23:45:23.108493 0, 0xFFFF, sum = 0
8538 23:45:23.112020 1, 0xFFFF, sum = 0
8539 23:45:23.115463 2, 0xFFFF, sum = 0
8540 23:45:23.115561 3, 0xFFFF, sum = 0
8541 23:45:23.118317 4, 0xFFFF, sum = 0
8542 23:45:23.118414 5, 0xFFFF, sum = 0
8543 23:45:23.121941 6, 0xFFFF, sum = 0
8544 23:45:23.122044 7, 0xFFFF, sum = 0
8545 23:45:23.125279 8, 0xFFFF, sum = 0
8546 23:45:23.125426 9, 0xFFFF, sum = 0
8547 23:45:23.128512 10, 0xFFFF, sum = 0
8548 23:45:23.128633 11, 0xFFFF, sum = 0
8549 23:45:23.131689 12, 0xFFFF, sum = 0
8550 23:45:23.131773 13, 0x8FFF, sum = 0
8551 23:45:23.134794 14, 0x0, sum = 1
8552 23:45:23.134879 15, 0x0, sum = 2
8553 23:45:23.138467 16, 0x0, sum = 3
8554 23:45:23.138552 17, 0x0, sum = 4
8555 23:45:23.141717 best_step = 15
8556 23:45:23.141801
8557 23:45:23.141884 ==
8558 23:45:23.145161 Dram Type= 6, Freq= 0, CH_1, rank 0
8559 23:45:23.148486 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8560 23:45:23.148630 ==
8561 23:45:23.151785 RX Vref Scan: 1
8562 23:45:23.151868
8563 23:45:23.151952 Set Vref Range= 24 -> 127
8564 23:45:23.152032
8565 23:45:23.154915 RX Vref 24 -> 127, step: 1
8566 23:45:23.154991
8567 23:45:23.158198 RX Delay 11 -> 252, step: 4
8568 23:45:23.158281
8569 23:45:23.162144 Set Vref, RX VrefLevel [Byte0]: 24
8570 23:45:23.165050 [Byte1]: 24
8571 23:45:23.165134
8572 23:45:23.168467 Set Vref, RX VrefLevel [Byte0]: 25
8573 23:45:23.171777 [Byte1]: 25
8574 23:45:23.174817
8575 23:45:23.174901 Set Vref, RX VrefLevel [Byte0]: 26
8576 23:45:23.178098 [Byte1]: 26
8577 23:45:23.182555
8578 23:45:23.182635 Set Vref, RX VrefLevel [Byte0]: 27
8579 23:45:23.185993 [Byte1]: 27
8580 23:45:23.190070
8581 23:45:23.190153 Set Vref, RX VrefLevel [Byte0]: 28
8582 23:45:23.193669 [Byte1]: 28
8583 23:45:23.197705
8584 23:45:23.197791 Set Vref, RX VrefLevel [Byte0]: 29
8585 23:45:23.201105 [Byte1]: 29
8586 23:45:23.205211
8587 23:45:23.205309 Set Vref, RX VrefLevel [Byte0]: 30
8588 23:45:23.208765 [Byte1]: 30
8589 23:45:23.212656
8590 23:45:23.212775 Set Vref, RX VrefLevel [Byte0]: 31
8591 23:45:23.216296 [Byte1]: 31
8592 23:45:23.220444
8593 23:45:23.220524 Set Vref, RX VrefLevel [Byte0]: 32
8594 23:45:23.223685 [Byte1]: 32
8595 23:45:23.228089
8596 23:45:23.228164 Set Vref, RX VrefLevel [Byte0]: 33
8597 23:45:23.231500 [Byte1]: 33
8598 23:45:23.235972
8599 23:45:23.236075 Set Vref, RX VrefLevel [Byte0]: 34
8600 23:45:23.239123 [Byte1]: 34
8601 23:45:23.243521
8602 23:45:23.243644 Set Vref, RX VrefLevel [Byte0]: 35
8603 23:45:23.246716 [Byte1]: 35
8604 23:45:23.250765
8605 23:45:23.250920 Set Vref, RX VrefLevel [Byte0]: 36
8606 23:45:23.254207 [Byte1]: 36
8607 23:45:23.258689
8608 23:45:23.258940 Set Vref, RX VrefLevel [Byte0]: 37
8609 23:45:23.261814 [Byte1]: 37
8610 23:45:23.265993
8611 23:45:23.266127 Set Vref, RX VrefLevel [Byte0]: 38
8612 23:45:23.269561 [Byte1]: 38
8613 23:45:23.273593
8614 23:45:23.273680 Set Vref, RX VrefLevel [Byte0]: 39
8615 23:45:23.277157 [Byte1]: 39
8616 23:45:23.281189
8617 23:45:23.281275 Set Vref, RX VrefLevel [Byte0]: 40
8618 23:45:23.284820 [Byte1]: 40
8619 23:45:23.289070
8620 23:45:23.289151 Set Vref, RX VrefLevel [Byte0]: 41
8621 23:45:23.292476 [Byte1]: 41
8622 23:45:23.296535
8623 23:45:23.296678 Set Vref, RX VrefLevel [Byte0]: 42
8624 23:45:23.299595 [Byte1]: 42
8625 23:45:23.304047
8626 23:45:23.304179 Set Vref, RX VrefLevel [Byte0]: 43
8627 23:45:23.307502 [Byte1]: 43
8628 23:45:23.311477
8629 23:45:23.311605 Set Vref, RX VrefLevel [Byte0]: 44
8630 23:45:23.315109 [Byte1]: 44
8631 23:45:23.319190
8632 23:45:23.319321 Set Vref, RX VrefLevel [Byte0]: 45
8633 23:45:23.322385 [Byte1]: 45
8634 23:45:23.327051
8635 23:45:23.327175 Set Vref, RX VrefLevel [Byte0]: 46
8636 23:45:23.330251 [Byte1]: 46
8637 23:45:23.334721
8638 23:45:23.334813 Set Vref, RX VrefLevel [Byte0]: 47
8639 23:45:23.338102 [Byte1]: 47
8640 23:45:23.341990
8641 23:45:23.342074 Set Vref, RX VrefLevel [Byte0]: 48
8642 23:45:23.345601 [Byte1]: 48
8643 23:45:23.349944
8644 23:45:23.350034 Set Vref, RX VrefLevel [Byte0]: 49
8645 23:45:23.353074 [Byte1]: 49
8646 23:45:23.357611
8647 23:45:23.357740 Set Vref, RX VrefLevel [Byte0]: 50
8648 23:45:23.360767 [Byte1]: 50
8649 23:45:23.365459
8650 23:45:23.365592 Set Vref, RX VrefLevel [Byte0]: 51
8651 23:45:23.368496 [Byte1]: 51
8652 23:45:23.372624
8653 23:45:23.372753 Set Vref, RX VrefLevel [Byte0]: 52
8654 23:45:23.375774 [Byte1]: 52
8655 23:45:23.380254
8656 23:45:23.380366 Set Vref, RX VrefLevel [Byte0]: 53
8657 23:45:23.383797 [Byte1]: 53
8658 23:45:23.388211
8659 23:45:23.388327 Set Vref, RX VrefLevel [Byte0]: 54
8660 23:45:23.391677 [Byte1]: 54
8661 23:45:23.395320
8662 23:45:23.395452 Set Vref, RX VrefLevel [Byte0]: 55
8663 23:45:23.398544 [Byte1]: 55
8664 23:45:23.403082
8665 23:45:23.403210 Set Vref, RX VrefLevel [Byte0]: 56
8666 23:45:23.406447 [Byte1]: 56
8667 23:45:23.411046
8668 23:45:23.411163 Set Vref, RX VrefLevel [Byte0]: 57
8669 23:45:23.413901 [Byte1]: 57
8670 23:45:23.418438
8671 23:45:23.418522 Set Vref, RX VrefLevel [Byte0]: 58
8672 23:45:23.421729 [Byte1]: 58
8673 23:45:23.426229
8674 23:45:23.426313 Set Vref, RX VrefLevel [Byte0]: 59
8675 23:45:23.429630 [Byte1]: 59
8676 23:45:23.433741
8677 23:45:23.433825 Set Vref, RX VrefLevel [Byte0]: 60
8678 23:45:23.436772 [Byte1]: 60
8679 23:45:23.441121
8680 23:45:23.441262 Set Vref, RX VrefLevel [Byte0]: 61
8681 23:45:23.444448 [Byte1]: 61
8682 23:45:23.448964
8683 23:45:23.449049 Set Vref, RX VrefLevel [Byte0]: 62
8684 23:45:23.452169 [Byte1]: 62
8685 23:45:23.456168
8686 23:45:23.456267 Set Vref, RX VrefLevel [Byte0]: 63
8687 23:45:23.459906 [Byte1]: 63
8688 23:45:23.464453
8689 23:45:23.464569 Set Vref, RX VrefLevel [Byte0]: 64
8690 23:45:23.467053 [Byte1]: 64
8691 23:45:23.471594
8692 23:45:23.471681 Set Vref, RX VrefLevel [Byte0]: 65
8693 23:45:23.474900 [Byte1]: 65
8694 23:45:23.479021
8695 23:45:23.479142 Set Vref, RX VrefLevel [Byte0]: 66
8696 23:45:23.482663 [Byte1]: 66
8697 23:45:23.487113
8698 23:45:23.487223 Set Vref, RX VrefLevel [Byte0]: 67
8699 23:45:23.489966 [Byte1]: 67
8700 23:45:23.494636
8701 23:45:23.494754 Set Vref, RX VrefLevel [Byte0]: 68
8702 23:45:23.497472 [Byte1]: 68
8703 23:45:23.502221
8704 23:45:23.502329 Set Vref, RX VrefLevel [Byte0]: 69
8705 23:45:23.505722 [Byte1]: 69
8706 23:45:23.509811
8707 23:45:23.509937 Set Vref, RX VrefLevel [Byte0]: 70
8708 23:45:23.513219 [Byte1]: 70
8709 23:45:23.517313
8710 23:45:23.517397 Set Vref, RX VrefLevel [Byte0]: 71
8711 23:45:23.520822 [Byte1]: 71
8712 23:45:23.524690
8713 23:45:23.524806 Set Vref, RX VrefLevel [Byte0]: 72
8714 23:45:23.528258 [Byte1]: 72
8715 23:45:23.532979
8716 23:45:23.533089 Final RX Vref Byte 0 = 59 to rank0
8717 23:45:23.535661 Final RX Vref Byte 1 = 54 to rank0
8718 23:45:23.539080 Final RX Vref Byte 0 = 59 to rank1
8719 23:45:23.542342 Final RX Vref Byte 1 = 54 to rank1==
8720 23:45:23.545527 Dram Type= 6, Freq= 0, CH_1, rank 0
8721 23:45:23.552611 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8722 23:45:23.552716 ==
8723 23:45:23.552787 DQS Delay:
8724 23:45:23.552850 DQS0 = 0, DQS1 = 0
8725 23:45:23.555626 DQM Delay:
8726 23:45:23.555703 DQM0 = 131, DQM1 = 123
8727 23:45:23.559077 DQ Delay:
8728 23:45:23.562365 DQ0 =138, DQ1 =126, DQ2 =120, DQ3 =130
8729 23:45:23.565400 DQ4 =128, DQ5 =142, DQ6 =142, DQ7 =128
8730 23:45:23.568827 DQ8 =110, DQ9 =114, DQ10 =122, DQ11 =114
8731 23:45:23.572272 DQ12 =132, DQ13 =130, DQ14 =132, DQ15 =132
8732 23:45:23.572359
8733 23:45:23.572464
8734 23:45:23.572575
8735 23:45:23.575669 [DramC_TX_OE_Calibration] TA2
8736 23:45:23.579161 Original DQ_B0 (3 6) =30, OEN = 27
8737 23:45:23.582308 Original DQ_B1 (3 6) =30, OEN = 27
8738 23:45:23.585453 24, 0x0, End_B0=24 End_B1=24
8739 23:45:23.585576 25, 0x0, End_B0=25 End_B1=25
8740 23:45:23.588427 26, 0x0, End_B0=26 End_B1=26
8741 23:45:23.592273 27, 0x0, End_B0=27 End_B1=27
8742 23:45:23.595595 28, 0x0, End_B0=28 End_B1=28
8743 23:45:23.598390 29, 0x0, End_B0=29 End_B1=29
8744 23:45:23.598507 30, 0x0, End_B0=30 End_B1=30
8745 23:45:23.601900 31, 0x4141, End_B0=30 End_B1=30
8746 23:45:23.605041 Byte0 end_step=30 best_step=27
8747 23:45:23.608384 Byte1 end_step=30 best_step=27
8748 23:45:23.611844 Byte0 TX OE(2T, 0.5T) = (3, 3)
8749 23:45:23.615274 Byte1 TX OE(2T, 0.5T) = (3, 3)
8750 23:45:23.615404
8751 23:45:23.615505
8752 23:45:23.621702 [DQSOSCAuto] RK0, (LSB)MR18= 0x80d, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 405 ps
8753 23:45:23.625200 CH1 RK0: MR19=303, MR18=80D
8754 23:45:23.631450 CH1_RK0: MR19=0x303, MR18=0x80D, DQSOSC=403, MR23=63, INC=22, DEC=15
8755 23:45:23.631572
8756 23:45:23.635004 ----->DramcWriteLeveling(PI) begin...
8757 23:45:23.635118 ==
8758 23:45:23.638463 Dram Type= 6, Freq= 0, CH_1, rank 1
8759 23:45:23.641834 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8760 23:45:23.641955 ==
8761 23:45:23.645242 Write leveling (Byte 0): 24 => 24
8762 23:45:23.648138 Write leveling (Byte 1): 28 => 28
8763 23:45:23.651987 DramcWriteLeveling(PI) end<-----
8764 23:45:23.652120
8765 23:45:23.652233 ==
8766 23:45:23.655146 Dram Type= 6, Freq= 0, CH_1, rank 1
8767 23:45:23.658444 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8768 23:45:23.658564 ==
8769 23:45:23.661957 [Gating] SW mode calibration
8770 23:45:23.668497 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8771 23:45:23.674722 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8772 23:45:23.678127 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8773 23:45:23.681765 1 4 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
8774 23:45:23.688142 1 4 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
8775 23:45:23.691365 1 4 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8776 23:45:23.698234 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8777 23:45:23.701554 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8778 23:45:23.704809 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8779 23:45:23.708097 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8780 23:45:23.714833 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8781 23:45:23.717509 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8782 23:45:23.721039 1 5 8 | B1->B0 | 3333 2727 | 0 0 | (0 0) (1 0)
8783 23:45:23.727580 1 5 12 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
8784 23:45:23.731161 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8785 23:45:23.734498 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8786 23:45:23.740933 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8787 23:45:23.744368 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8788 23:45:23.747678 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8789 23:45:23.754245 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8790 23:45:23.757438 1 6 8 | B1->B0 | 2929 4444 | 0 0 | (0 0) (0 0)
8791 23:45:23.760903 1 6 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8792 23:45:23.767202 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8793 23:45:23.770404 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8794 23:45:23.774257 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8795 23:45:23.780385 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8796 23:45:23.783568 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8797 23:45:23.787171 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8798 23:45:23.793676 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8799 23:45:23.797241 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8800 23:45:23.800341 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8801 23:45:23.806879 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8802 23:45:23.810480 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8803 23:45:23.813867 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8804 23:45:23.820223 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8805 23:45:23.823664 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 23:45:23.826387 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 23:45:23.833191 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 23:45:23.836687 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 23:45:23.839884 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8810 23:45:23.846385 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 23:45:23.849669 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8812 23:45:23.853104 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8813 23:45:23.859803 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8814 23:45:23.863271 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8815 23:45:23.866069 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8816 23:45:23.869832 Total UI for P1: 0, mck2ui 16
8817 23:45:23.873138 best dqsien dly found for B0: ( 1, 9, 8)
8818 23:45:23.876242 Total UI for P1: 0, mck2ui 16
8819 23:45:23.879852 best dqsien dly found for B1: ( 1, 9, 8)
8820 23:45:23.883001 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8821 23:45:23.885906 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8822 23:45:23.889273
8823 23:45:23.892587 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8824 23:45:23.896207 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8825 23:45:23.899143 [Gating] SW calibration Done
8826 23:45:23.899221 ==
8827 23:45:23.902647 Dram Type= 6, Freq= 0, CH_1, rank 1
8828 23:45:23.905798 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8829 23:45:23.905905 ==
8830 23:45:23.905998 RX Vref Scan: 0
8831 23:45:23.906087
8832 23:45:23.909375 RX Vref 0 -> 0, step: 1
8833 23:45:23.909449
8834 23:45:23.912318 RX Delay 0 -> 252, step: 8
8835 23:45:23.915936 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8836 23:45:23.918906 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8837 23:45:23.925885 iDelay=200, Bit 2, Center 115 (56 ~ 175) 120
8838 23:45:23.929072 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8839 23:45:23.932466 iDelay=200, Bit 4, Center 123 (64 ~ 183) 120
8840 23:45:23.935958 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8841 23:45:23.939325 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8842 23:45:23.945364 iDelay=200, Bit 7, Center 127 (64 ~ 191) 128
8843 23:45:23.948836 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8844 23:45:23.952257 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8845 23:45:23.955594 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8846 23:45:23.958529 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8847 23:45:23.965244 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8848 23:45:23.968640 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8849 23:45:23.972059 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8850 23:45:23.975229 iDelay=200, Bit 15, Center 135 (72 ~ 199) 128
8851 23:45:23.975325 ==
8852 23:45:23.978452 Dram Type= 6, Freq= 0, CH_1, rank 1
8853 23:45:23.984985 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8854 23:45:23.985073 ==
8855 23:45:23.985168 DQS Delay:
8856 23:45:23.988081 DQS0 = 0, DQS1 = 0
8857 23:45:23.988171 DQM Delay:
8858 23:45:23.991832 DQM0 = 128, DQM1 = 127
8859 23:45:23.991936 DQ Delay:
8860 23:45:23.995028 DQ0 =131, DQ1 =127, DQ2 =115, DQ3 =123
8861 23:45:23.997897 DQ4 =123, DQ5 =139, DQ6 =139, DQ7 =127
8862 23:45:24.001794 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8863 23:45:24.004819 DQ12 =131, DQ13 =139, DQ14 =131, DQ15 =135
8864 23:45:24.004955
8865 23:45:24.005066
8866 23:45:24.005188 ==
8867 23:45:24.007942 Dram Type= 6, Freq= 0, CH_1, rank 1
8868 23:45:24.014650 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8869 23:45:24.014785 ==
8870 23:45:24.014899
8871 23:45:24.015013
8872 23:45:24.015126 TX Vref Scan disable
8873 23:45:24.018490 == TX Byte 0 ==
8874 23:45:24.021771 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8875 23:45:24.028326 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8876 23:45:24.028446 == TX Byte 1 ==
8877 23:45:24.031473 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8878 23:45:24.035093 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8879 23:45:24.038134 ==
8880 23:45:24.041488 Dram Type= 6, Freq= 0, CH_1, rank 1
8881 23:45:24.044893 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8882 23:45:24.044978 ==
8883 23:45:24.057638
8884 23:45:24.060521 TX Vref early break, caculate TX vref
8885 23:45:24.063956 TX Vref=16, minBit 0, minWin=23, winSum=383
8886 23:45:24.067448 TX Vref=18, minBit 0, minWin=23, winSum=391
8887 23:45:24.070825 TX Vref=20, minBit 0, minWin=24, winSum=401
8888 23:45:24.074092 TX Vref=22, minBit 5, minWin=24, winSum=405
8889 23:45:24.077488 TX Vref=24, minBit 0, minWin=25, winSum=421
8890 23:45:24.084027 TX Vref=26, minBit 0, minWin=25, winSum=422
8891 23:45:24.087516 TX Vref=28, minBit 0, minWin=25, winSum=423
8892 23:45:24.090334 TX Vref=30, minBit 0, minWin=25, winSum=425
8893 23:45:24.094006 TX Vref=32, minBit 1, minWin=24, winSum=411
8894 23:45:24.097280 TX Vref=34, minBit 0, minWin=23, winSum=400
8895 23:45:24.103839 [TxChooseVref] Worse bit 0, Min win 25, Win sum 425, Final Vref 30
8896 23:45:24.103986
8897 23:45:24.107261 Final TX Range 0 Vref 30
8898 23:45:24.107400
8899 23:45:24.107513 ==
8900 23:45:24.110491 Dram Type= 6, Freq= 0, CH_1, rank 1
8901 23:45:24.113747 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8902 23:45:24.113880 ==
8903 23:45:24.113996
8904 23:45:24.114122
8905 23:45:24.117287 TX Vref Scan disable
8906 23:45:24.123437 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8907 23:45:24.123573 == TX Byte 0 ==
8908 23:45:24.127179 u2DelayCellOfst[0]=18 cells (5 PI)
8909 23:45:24.130406 u2DelayCellOfst[1]=15 cells (4 PI)
8910 23:45:24.133945 u2DelayCellOfst[2]=0 cells (0 PI)
8911 23:45:24.137087 u2DelayCellOfst[3]=7 cells (2 PI)
8912 23:45:24.140658 u2DelayCellOfst[4]=11 cells (3 PI)
8913 23:45:24.143356 u2DelayCellOfst[5]=26 cells (7 PI)
8914 23:45:24.146918 u2DelayCellOfst[6]=22 cells (6 PI)
8915 23:45:24.150077 u2DelayCellOfst[7]=7 cells (2 PI)
8916 23:45:24.153253 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8917 23:45:24.156705 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8918 23:45:24.160238 == TX Byte 1 ==
8919 23:45:24.163008 u2DelayCellOfst[8]=0 cells (0 PI)
8920 23:45:24.163144 u2DelayCellOfst[9]=7 cells (2 PI)
8921 23:45:24.166585 u2DelayCellOfst[10]=15 cells (4 PI)
8922 23:45:24.169823 u2DelayCellOfst[11]=7 cells (2 PI)
8923 23:45:24.173316 u2DelayCellOfst[12]=18 cells (5 PI)
8924 23:45:24.176679 u2DelayCellOfst[13]=18 cells (5 PI)
8925 23:45:24.179563 u2DelayCellOfst[14]=22 cells (6 PI)
8926 23:45:24.182974 u2DelayCellOfst[15]=18 cells (5 PI)
8927 23:45:24.186139 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8928 23:45:24.193310 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8929 23:45:24.193436 DramC Write-DBI on
8930 23:45:24.193535 ==
8931 23:45:24.196069 Dram Type= 6, Freq= 0, CH_1, rank 1
8932 23:45:24.202887 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8933 23:45:24.203029 ==
8934 23:45:24.203147
8935 23:45:24.203267
8936 23:45:24.203385 TX Vref Scan disable
8937 23:45:24.206875 == TX Byte 0 ==
8938 23:45:24.210124 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8939 23:45:24.213610 == TX Byte 1 ==
8940 23:45:24.216342 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8941 23:45:24.219669 DramC Write-DBI off
8942 23:45:24.219807
8943 23:45:24.219932 [DATLAT]
8944 23:45:24.220047 Freq=1600, CH1 RK1
8945 23:45:24.220164
8946 23:45:24.222968 DATLAT Default: 0xf
8947 23:45:24.226324 0, 0xFFFF, sum = 0
8948 23:45:24.226462 1, 0xFFFF, sum = 0
8949 23:45:24.229583 2, 0xFFFF, sum = 0
8950 23:45:24.229724 3, 0xFFFF, sum = 0
8951 23:45:24.232814 4, 0xFFFF, sum = 0
8952 23:45:24.232924 5, 0xFFFF, sum = 0
8953 23:45:24.236163 6, 0xFFFF, sum = 0
8954 23:45:24.236275 7, 0xFFFF, sum = 0
8955 23:45:24.239865 8, 0xFFFF, sum = 0
8956 23:45:24.239970 9, 0xFFFF, sum = 0
8957 23:45:24.243201 10, 0xFFFF, sum = 0
8958 23:45:24.243281 11, 0xFFFF, sum = 0
8959 23:45:24.246537 12, 0xFFFF, sum = 0
8960 23:45:24.246620 13, 0x8FFF, sum = 0
8961 23:45:24.249381 14, 0x0, sum = 1
8962 23:45:24.249498 15, 0x0, sum = 2
8963 23:45:24.252884 16, 0x0, sum = 3
8964 23:45:24.253009 17, 0x0, sum = 4
8965 23:45:24.256882 best_step = 15
8966 23:45:24.257018
8967 23:45:24.257135 ==
8968 23:45:24.259418 Dram Type= 6, Freq= 0, CH_1, rank 1
8969 23:45:24.262997 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8970 23:45:24.263126 ==
8971 23:45:24.266365 RX Vref Scan: 0
8972 23:45:24.266487
8973 23:45:24.266597 RX Vref 0 -> 0, step: 1
8974 23:45:24.266708
8975 23:45:24.269302 RX Delay 11 -> 252, step: 4
8976 23:45:24.276010 iDelay=195, Bit 0, Center 134 (79 ~ 190) 112
8977 23:45:24.279599 iDelay=195, Bit 1, Center 126 (75 ~ 178) 104
8978 23:45:24.282986 iDelay=195, Bit 2, Center 114 (59 ~ 170) 112
8979 23:45:24.285944 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8980 23:45:24.289688 iDelay=195, Bit 4, Center 124 (67 ~ 182) 116
8981 23:45:24.295937 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8982 23:45:24.299418 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8983 23:45:24.302385 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8984 23:45:24.306412 iDelay=195, Bit 8, Center 108 (51 ~ 166) 116
8985 23:45:24.309023 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8986 23:45:24.316007 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8987 23:45:24.319540 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8988 23:45:24.322695 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8989 23:45:24.326003 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8990 23:45:24.329076 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
8991 23:45:24.335858 iDelay=195, Bit 15, Center 134 (79 ~ 190) 112
8992 23:45:24.335970 ==
8993 23:45:24.339200 Dram Type= 6, Freq= 0, CH_1, rank 1
8994 23:45:24.342367 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8995 23:45:24.342456 ==
8996 23:45:24.342545 DQS Delay:
8997 23:45:24.345890 DQS0 = 0, DQS1 = 0
8998 23:45:24.345976 DQM Delay:
8999 23:45:24.349462 DQM0 = 128, DQM1 = 124
9000 23:45:24.349548 DQ Delay:
9001 23:45:24.352135 DQ0 =134, DQ1 =126, DQ2 =114, DQ3 =124
9002 23:45:24.355715 DQ4 =124, DQ5 =138, DQ6 =138, DQ7 =126
9003 23:45:24.359208 DQ8 =108, DQ9 =112, DQ10 =128, DQ11 =120
9004 23:45:24.362081 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =134
9005 23:45:24.362162
9006 23:45:24.365624
9007 23:45:24.365710
9008 23:45:24.365798 [DramC_TX_OE_Calibration] TA2
9009 23:45:24.368889 Original DQ_B0 (3 6) =30, OEN = 27
9010 23:45:24.372433 Original DQ_B1 (3 6) =30, OEN = 27
9011 23:45:24.375507 24, 0x0, End_B0=24 End_B1=24
9012 23:45:24.378926 25, 0x0, End_B0=25 End_B1=25
9013 23:45:24.382353 26, 0x0, End_B0=26 End_B1=26
9014 23:45:24.382454 27, 0x0, End_B0=27 End_B1=27
9015 23:45:24.385344 28, 0x0, End_B0=28 End_B1=28
9016 23:45:24.388777 29, 0x0, End_B0=29 End_B1=29
9017 23:45:24.392237 30, 0x0, End_B0=30 End_B1=30
9018 23:45:24.395562 31, 0x4141, End_B0=30 End_B1=30
9019 23:45:24.395699 Byte0 end_step=30 best_step=27
9020 23:45:24.399049 Byte1 end_step=30 best_step=27
9021 23:45:24.402423 Byte0 TX OE(2T, 0.5T) = (3, 3)
9022 23:45:24.405289 Byte1 TX OE(2T, 0.5T) = (3, 3)
9023 23:45:24.405401
9024 23:45:24.405495
9025 23:45:24.412188 [DQSOSCAuto] RK1, (LSB)MR18= 0x131f, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 400 ps
9026 23:45:24.415092 CH1 RK1: MR19=303, MR18=131F
9027 23:45:24.421625 CH1_RK1: MR19=0x303, MR18=0x131F, DQSOSC=394, MR23=63, INC=23, DEC=15
9028 23:45:24.425212 [RxdqsGatingPostProcess] freq 1600
9029 23:45:24.431560 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9030 23:45:24.434994 best DQS0 dly(2T, 0.5T) = (1, 1)
9031 23:45:24.438554 best DQS1 dly(2T, 0.5T) = (1, 1)
9032 23:45:24.441822 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9033 23:45:24.441897 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9034 23:45:24.444940 best DQS0 dly(2T, 0.5T) = (1, 1)
9035 23:45:24.448609 best DQS1 dly(2T, 0.5T) = (1, 1)
9036 23:45:24.451375 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9037 23:45:24.454643 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9038 23:45:24.458079 Pre-setting of DQS Precalculation
9039 23:45:24.465215 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9040 23:45:24.471271 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9041 23:45:24.477979 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9042 23:45:24.478100
9043 23:45:24.478211
9044 23:45:24.481265 [Calibration Summary] 3200 Mbps
9045 23:45:24.481378 CH 0, Rank 0
9046 23:45:24.484661 SW Impedance : PASS
9047 23:45:24.488087 DUTY Scan : NO K
9048 23:45:24.488223 ZQ Calibration : PASS
9049 23:45:24.491347 Jitter Meter : NO K
9050 23:45:24.494916 CBT Training : PASS
9051 23:45:24.495078 Write leveling : PASS
9052 23:45:24.498047 RX DQS gating : PASS
9053 23:45:24.500963 RX DQ/DQS(RDDQC) : PASS
9054 23:45:24.501115 TX DQ/DQS : PASS
9055 23:45:24.504512 RX DATLAT : PASS
9056 23:45:24.504644 RX DQ/DQS(Engine): PASS
9057 23:45:24.508024 TX OE : PASS
9058 23:45:24.508148 All Pass.
9059 23:45:24.508243
9060 23:45:24.510982 CH 0, Rank 1
9061 23:45:24.514617 SW Impedance : PASS
9062 23:45:24.514744 DUTY Scan : NO K
9063 23:45:24.517529 ZQ Calibration : PASS
9064 23:45:24.517649 Jitter Meter : NO K
9065 23:45:24.520990 CBT Training : PASS
9066 23:45:24.524012 Write leveling : PASS
9067 23:45:24.524141 RX DQS gating : PASS
9068 23:45:24.527576 RX DQ/DQS(RDDQC) : PASS
9069 23:45:24.530905 TX DQ/DQS : PASS
9070 23:45:24.531033 RX DATLAT : PASS
9071 23:45:24.534335 RX DQ/DQS(Engine): PASS
9072 23:45:24.537483 TX OE : PASS
9073 23:45:24.537621 All Pass.
9074 23:45:24.537727
9075 23:45:24.537824 CH 1, Rank 0
9076 23:45:24.540988 SW Impedance : PASS
9077 23:45:24.543996 DUTY Scan : NO K
9078 23:45:24.544129 ZQ Calibration : PASS
9079 23:45:24.547520 Jitter Meter : NO K
9080 23:45:24.550803 CBT Training : PASS
9081 23:45:24.550940 Write leveling : PASS
9082 23:45:24.553988 RX DQS gating : PASS
9083 23:45:24.557571 RX DQ/DQS(RDDQC) : PASS
9084 23:45:24.557710 TX DQ/DQS : PASS
9085 23:45:24.560477 RX DATLAT : PASS
9086 23:45:24.563869 RX DQ/DQS(Engine): PASS
9087 23:45:24.563991 TX OE : PASS
9088 23:45:24.564107 All Pass.
9089 23:45:24.567113
9090 23:45:24.567249 CH 1, Rank 1
9091 23:45:24.570920 SW Impedance : PASS
9092 23:45:24.571012 DUTY Scan : NO K
9093 23:45:24.574278 ZQ Calibration : PASS
9094 23:45:24.574384 Jitter Meter : NO K
9095 23:45:24.577051 CBT Training : PASS
9096 23:45:24.580508 Write leveling : PASS
9097 23:45:24.580658 RX DQS gating : PASS
9098 23:45:24.584081 RX DQ/DQS(RDDQC) : PASS
9099 23:45:24.587499 TX DQ/DQS : PASS
9100 23:45:24.587604 RX DATLAT : PASS
9101 23:45:24.590866 RX DQ/DQS(Engine): PASS
9102 23:45:24.593969 TX OE : PASS
9103 23:45:24.594059 All Pass.
9104 23:45:24.594145
9105 23:45:24.597030 DramC Write-DBI on
9106 23:45:24.597203 PER_BANK_REFRESH: Hybrid Mode
9107 23:45:24.600445 TX_TRACKING: ON
9108 23:45:24.610438 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9109 23:45:24.617001 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9110 23:45:24.623370 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9111 23:45:24.626954 [FAST_K] Save calibration result to emmc
9112 23:45:24.629847 sync common calibartion params.
9113 23:45:24.633407 sync cbt_mode0:1, 1:1
9114 23:45:24.633529 dram_init: ddr_geometry: 2
9115 23:45:24.636890 dram_init: ddr_geometry: 2
9116 23:45:24.640317 dram_init: ddr_geometry: 2
9117 23:45:24.643619 0:dram_rank_size:100000000
9118 23:45:24.643752 1:dram_rank_size:100000000
9119 23:45:24.650128 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9120 23:45:24.653497 DFS_SHUFFLE_HW_MODE: ON
9121 23:45:24.656614 dramc_set_vcore_voltage set vcore to 725000
9122 23:45:24.660187 Read voltage for 1600, 0
9123 23:45:24.660315 Vio18 = 0
9124 23:45:24.660444 Vcore = 725000
9125 23:45:24.663389 Vdram = 0
9126 23:45:24.663510 Vddq = 0
9127 23:45:24.663610 Vmddr = 0
9128 23:45:24.666909 switch to 3200 Mbps bootup
9129 23:45:24.667024 [DramcRunTimeConfig]
9130 23:45:24.669895 PHYPLL
9131 23:45:24.670071 DPM_CONTROL_AFTERK: ON
9132 23:45:24.673296 PER_BANK_REFRESH: ON
9133 23:45:24.676572 REFRESH_OVERHEAD_REDUCTION: ON
9134 23:45:24.676705 CMD_PICG_NEW_MODE: OFF
9135 23:45:24.680117 XRTWTW_NEW_MODE: ON
9136 23:45:24.680212 XRTRTR_NEW_MODE: ON
9137 23:45:24.682850 TX_TRACKING: ON
9138 23:45:24.682932 RDSEL_TRACKING: OFF
9139 23:45:24.686378 DQS Precalculation for DVFS: ON
9140 23:45:24.689989 RX_TRACKING: OFF
9141 23:45:24.690080 HW_GATING DBG: ON
9142 23:45:24.693356 ZQCS_ENABLE_LP4: ON
9143 23:45:24.693447 RX_PICG_NEW_MODE: ON
9144 23:45:24.696665 TX_PICG_NEW_MODE: ON
9145 23:45:24.696752 ENABLE_RX_DCM_DPHY: ON
9146 23:45:24.699504 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9147 23:45:24.703270 DUMMY_READ_FOR_TRACKING: OFF
9148 23:45:24.706480 !!! SPM_CONTROL_AFTERK: OFF
9149 23:45:24.709572 !!! SPM could not control APHY
9150 23:45:24.709722 IMPEDANCE_TRACKING: ON
9151 23:45:24.712879 TEMP_SENSOR: ON
9152 23:45:24.712992 HW_SAVE_FOR_SR: OFF
9153 23:45:24.716116 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9154 23:45:24.719561 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9155 23:45:24.722841 Read ODT Tracking: ON
9156 23:45:24.726284 Refresh Rate DeBounce: ON
9157 23:45:24.726415 DFS_NO_QUEUE_FLUSH: ON
9158 23:45:24.729739 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9159 23:45:24.732534 ENABLE_DFS_RUNTIME_MRW: OFF
9160 23:45:24.735918 DDR_RESERVE_NEW_MODE: ON
9161 23:45:24.735999 MR_CBT_SWITCH_FREQ: ON
9162 23:45:24.739262 =========================
9163 23:45:24.758523 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9164 23:45:24.761498 dram_init: ddr_geometry: 2
9165 23:45:24.779666 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9166 23:45:24.783498 dram_init: dram init end (result: 0)
9167 23:45:24.789847 DRAM-K: Full calibration passed in 24577 msecs
9168 23:45:24.793025 MRC: failed to locate region type 0.
9169 23:45:24.793123 DRAM rank0 size:0x100000000,
9170 23:45:24.796313 DRAM rank1 size=0x100000000
9171 23:45:24.806507 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9172 23:45:24.812678 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9173 23:45:24.819247 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9174 23:45:24.826047 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9175 23:45:24.829484 DRAM rank0 size:0x100000000,
9176 23:45:24.832812 DRAM rank1 size=0x100000000
9177 23:45:24.832950 CBMEM:
9178 23:45:24.836012 IMD: root @ 0xfffff000 254 entries.
9179 23:45:24.839483 IMD: root @ 0xffffec00 62 entries.
9180 23:45:24.842974 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9181 23:45:24.846206 WARNING: RO_VPD is uninitialized or empty.
9182 23:45:24.852911 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9183 23:45:24.859703 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9184 23:45:24.872359 read SPI 0x42894 0xe01e: 6227 us, 9213 KB/s, 73.704 Mbps
9185 23:45:24.883872 BS: romstage times (exec / console): total (unknown) / 24041 ms
9186 23:45:24.884006
9187 23:45:24.884100
9188 23:45:24.893838 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9189 23:45:24.897032 ARM64: Exception handlers installed.
9190 23:45:24.900732 ARM64: Testing exception
9191 23:45:24.904202 ARM64: Done test exception
9192 23:45:24.904308 Enumerating buses...
9193 23:45:24.906943 Show all devs... Before device enumeration.
9194 23:45:24.910341 Root Device: enabled 1
9195 23:45:24.913734 CPU_CLUSTER: 0: enabled 1
9196 23:45:24.913818 CPU: 00: enabled 1
9197 23:45:24.917149 Compare with tree...
9198 23:45:24.917231 Root Device: enabled 1
9199 23:45:24.920494 CPU_CLUSTER: 0: enabled 1
9200 23:45:24.923789 CPU: 00: enabled 1
9201 23:45:24.923872 Root Device scanning...
9202 23:45:24.927215 scan_static_bus for Root Device
9203 23:45:24.930311 CPU_CLUSTER: 0 enabled
9204 23:45:24.933522 scan_static_bus for Root Device done
9205 23:45:24.937220 scan_bus: bus Root Device finished in 8 msecs
9206 23:45:24.937349 done
9207 23:45:24.943841 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9208 23:45:24.947176 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9209 23:45:24.953880 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9210 23:45:24.957316 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9211 23:45:24.960119 Allocating resources...
9212 23:45:24.963634 Reading resources...
9213 23:45:24.966748 Root Device read_resources bus 0 link: 0
9214 23:45:24.966856 DRAM rank0 size:0x100000000,
9215 23:45:24.970121 DRAM rank1 size=0x100000000
9216 23:45:24.973609 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9217 23:45:24.977031 CPU: 00 missing read_resources
9218 23:45:24.980173 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9219 23:45:24.986724 Root Device read_resources bus 0 link: 0 done
9220 23:45:24.986809 Done reading resources.
9221 23:45:24.993195 Show resources in subtree (Root Device)...After reading.
9222 23:45:24.996582 Root Device child on link 0 CPU_CLUSTER: 0
9223 23:45:25.000154 CPU_CLUSTER: 0 child on link 0 CPU: 00
9224 23:45:25.010275 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9225 23:45:25.010439 CPU: 00
9226 23:45:25.013688 Root Device assign_resources, bus 0 link: 0
9227 23:45:25.016578 CPU_CLUSTER: 0 missing set_resources
9228 23:45:25.022893 Root Device assign_resources, bus 0 link: 0 done
9229 23:45:25.023010 Done setting resources.
9230 23:45:25.029908 Show resources in subtree (Root Device)...After assigning values.
9231 23:45:25.033328 Root Device child on link 0 CPU_CLUSTER: 0
9232 23:45:25.036701 CPU_CLUSTER: 0 child on link 0 CPU: 00
9233 23:45:25.046437 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9234 23:45:25.046530 CPU: 00
9235 23:45:25.049878 Done allocating resources.
9236 23:45:25.052939 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9237 23:45:25.056592 Enabling resources...
9238 23:45:25.056714 done.
9239 23:45:25.063285 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9240 23:45:25.063407 Initializing devices...
9241 23:45:25.066257 Root Device init
9242 23:45:25.066383 init hardware done!
9243 23:45:25.069555 0x00000018: ctrlr->caps
9244 23:45:25.072866 52.000 MHz: ctrlr->f_max
9245 23:45:25.072995 0.400 MHz: ctrlr->f_min
9246 23:45:25.076699 0x40ff8080: ctrlr->voltages
9247 23:45:25.076832 sclk: 390625
9248 23:45:25.079697 Bus Width = 1
9249 23:45:25.079818 sclk: 390625
9250 23:45:25.083299 Bus Width = 1
9251 23:45:25.083421 Early init status = 3
9252 23:45:25.089827 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9253 23:45:25.093178 in-header: 03 fc 00 00 01 00 00 00
9254 23:45:25.093300 in-data: 00
9255 23:45:25.099753 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9256 23:45:25.102835 in-header: 03 fd 00 00 00 00 00 00
9257 23:45:25.106046 in-data:
9258 23:45:25.109662 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9259 23:45:25.113066 in-header: 03 fc 00 00 01 00 00 00
9260 23:45:25.116227 in-data: 00
9261 23:45:25.119627 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9262 23:45:25.124215 in-header: 03 fd 00 00 00 00 00 00
9263 23:45:25.127634 in-data:
9264 23:45:25.130295 [SSUSB] Setting up USB HOST controller...
9265 23:45:25.133826 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9266 23:45:25.137043 [SSUSB] phy power-on done.
9267 23:45:25.140441 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9268 23:45:25.147064 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9269 23:45:25.150482 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9270 23:45:25.157370 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9271 23:45:25.163937 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9272 23:45:25.170492 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9273 23:45:25.177313 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9274 23:45:25.183845 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9275 23:45:25.187000 SPM: binary array size = 0x9dc
9276 23:45:25.189962 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9277 23:45:25.196724 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9278 23:45:25.203533 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9279 23:45:25.210092 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9280 23:45:25.213300 configure_display: Starting display init
9281 23:45:25.247760 anx7625_power_on_init: Init interface.
9282 23:45:25.250995 anx7625_disable_pd_protocol: Disabled PD feature.
9283 23:45:25.253704 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9284 23:45:25.281532 anx7625_start_dp_work: Secure OCM version=00
9285 23:45:25.285310 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9286 23:45:25.299977 sp_tx_get_edid_block: EDID Block = 1
9287 23:45:25.402365 Extracted contents:
9288 23:45:25.405552 header: 00 ff ff ff ff ff ff 00
9289 23:45:25.408791 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9290 23:45:25.412394 version: 01 04
9291 23:45:25.415530 basic params: 95 1f 11 78 0a
9292 23:45:25.418598 chroma info: 76 90 94 55 54 90 27 21 50 54
9293 23:45:25.421993 established: 00 00 00
9294 23:45:25.428481 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9295 23:45:25.432239 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9296 23:45:25.438519 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9297 23:45:25.445259 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9298 23:45:25.451903 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9299 23:45:25.455204 extensions: 00
9300 23:45:25.455316 checksum: fb
9301 23:45:25.455412
9302 23:45:25.458557 Manufacturer: IVO Model 57d Serial Number 0
9303 23:45:25.461548 Made week 0 of 2020
9304 23:45:25.464823 EDID version: 1.4
9305 23:45:25.464923 Digital display
9306 23:45:25.468211 6 bits per primary color channel
9307 23:45:25.468296 DisplayPort interface
9308 23:45:25.471528 Maximum image size: 31 cm x 17 cm
9309 23:45:25.474967 Gamma: 220%
9310 23:45:25.475047 Check DPMS levels
9311 23:45:25.481777 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9312 23:45:25.484532 First detailed timing is preferred timing
9313 23:45:25.484640 Established timings supported:
9314 23:45:25.487779 Standard timings supported:
9315 23:45:25.491658 Detailed timings
9316 23:45:25.494468 Hex of detail: 383680a07038204018303c0035ae10000019
9317 23:45:25.501356 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9318 23:45:25.504305 0780 0798 07c8 0820 hborder 0
9319 23:45:25.508012 0438 043b 0447 0458 vborder 0
9320 23:45:25.511100 -hsync -vsync
9321 23:45:25.511184 Did detailed timing
9322 23:45:25.517885 Hex of detail: 000000000000000000000000000000000000
9323 23:45:25.520971 Manufacturer-specified data, tag 0
9324 23:45:25.524161 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9325 23:45:25.527838 ASCII string: InfoVision
9326 23:45:25.530869 Hex of detail: 000000fe00523134304e574635205248200a
9327 23:45:25.534210 ASCII string: R140NWF5 RH
9328 23:45:25.534321 Checksum
9329 23:45:25.537699 Checksum: 0xfb (valid)
9330 23:45:25.541162 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9331 23:45:25.544297 DSI data_rate: 832800000 bps
9332 23:45:25.550875 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9333 23:45:25.554292 anx7625_parse_edid: pixelclock(138800).
9334 23:45:25.557619 hactive(1920), hsync(48), hfp(24), hbp(88)
9335 23:45:25.560760 vactive(1080), vsync(12), vfp(3), vbp(17)
9336 23:45:25.564160 anx7625_dsi_config: config dsi.
9337 23:45:25.570433 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9338 23:45:25.584552 anx7625_dsi_config: success to config DSI
9339 23:45:25.587925 anx7625_dp_start: MIPI phy setup OK.
9340 23:45:25.590869 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9341 23:45:25.594216 mtk_ddp_mode_set invalid vrefresh 60
9342 23:45:25.597393 main_disp_path_setup
9343 23:45:25.597529 ovl_layer_smi_id_en
9344 23:45:25.600789 ovl_layer_smi_id_en
9345 23:45:25.600912 ccorr_config
9346 23:45:25.601022 aal_config
9347 23:45:25.604337 gamma_config
9348 23:45:25.604479 postmask_config
9349 23:45:25.607655 dither_config
9350 23:45:25.611046 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9351 23:45:25.617728 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9352 23:45:25.620826 Root Device init finished in 551 msecs
9353 23:45:25.624236 CPU_CLUSTER: 0 init
9354 23:45:25.630856 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9355 23:45:25.634203 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9356 23:45:25.637453 APU_MBOX 0x190000b0 = 0x10001
9357 23:45:25.641003 APU_MBOX 0x190001b0 = 0x10001
9358 23:45:25.643786 APU_MBOX 0x190005b0 = 0x10001
9359 23:45:25.647195 APU_MBOX 0x190006b0 = 0x10001
9360 23:45:25.650569 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9361 23:45:25.663603 read SPI 0x539f4 0xe237: 6251 us, 9264 KB/s, 74.112 Mbps
9362 23:45:25.676099 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9363 23:45:25.682182 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9364 23:45:25.693970 read SPI 0x61c74 0xe8ef: 6412 us, 9299 KB/s, 74.392 Mbps
9365 23:45:25.703058 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9366 23:45:25.706450 CPU_CLUSTER: 0 init finished in 81 msecs
9367 23:45:25.709703 Devices initialized
9368 23:45:25.713102 Show all devs... After init.
9369 23:45:25.713230 Root Device: enabled 1
9370 23:45:25.716241 CPU_CLUSTER: 0: enabled 1
9371 23:45:25.720135 CPU: 00: enabled 1
9372 23:45:25.723312 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9373 23:45:25.726427 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9374 23:45:25.729577 ELOG: NV offset 0x57f000 size 0x1000
9375 23:45:25.736070 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9376 23:45:25.742900 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9377 23:45:25.745887 ELOG: Event(17) added with size 13 at 2024-06-04 23:45:25 UTC
9378 23:45:25.752425 out: cmd=0x121: 03 db 21 01 00 00 00 00
9379 23:45:25.755792 in-header: 03 5b 00 00 2c 00 00 00
9380 23:45:25.765665 in-data: 03 69 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9381 23:45:25.772733 ELOG: Event(A1) added with size 10 at 2024-06-04 23:45:25 UTC
9382 23:45:25.778995 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9383 23:45:25.785741 ELOG: Event(A0) added with size 9 at 2024-06-04 23:45:25 UTC
9384 23:45:25.788972 elog_add_boot_reason: Logged dev mode boot
9385 23:45:25.795705 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9386 23:45:25.795822 Finalize devices...
9387 23:45:25.799118 Devices finalized
9388 23:45:25.802058 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9389 23:45:25.805320 Writing coreboot table at 0xffe64000
9390 23:45:25.808667 0. 000000000010a000-0000000000113fff: RAMSTAGE
9391 23:45:25.815411 1. 0000000040000000-00000000400fffff: RAM
9392 23:45:25.818794 2. 0000000040100000-000000004032afff: RAMSTAGE
9393 23:45:25.822271 3. 000000004032b000-00000000545fffff: RAM
9394 23:45:25.825593 4. 0000000054600000-000000005465ffff: BL31
9395 23:45:25.828656 5. 0000000054660000-00000000ffe63fff: RAM
9396 23:45:25.835310 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9397 23:45:25.838508 7. 0000000100000000-000000023fffffff: RAM
9398 23:45:25.841987 Passing 5 GPIOs to payload:
9399 23:45:25.845418 NAME | PORT | POLARITY | VALUE
9400 23:45:25.851802 EC in RW | 0x000000aa | low | undefined
9401 23:45:25.855451 EC interrupt | 0x00000005 | low | undefined
9402 23:45:25.858374 TPM interrupt | 0x000000ab | high | undefined
9403 23:45:25.865009 SD card detect | 0x00000011 | high | undefined
9404 23:45:25.868224 speaker enable | 0x00000093 | high | undefined
9405 23:45:25.871616 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9406 23:45:25.875067 in-header: 03 f9 00 00 02 00 00 00
9407 23:45:25.878106 in-data: 02 00
9408 23:45:25.881394 ADC[4]: Raw value=896300 ID=7
9409 23:45:25.881520 ADC[3]: Raw value=213440 ID=1
9410 23:45:25.885110 RAM Code: 0x71
9411 23:45:25.888081 ADC[6]: Raw value=74352 ID=0
9412 23:45:25.888188 ADC[5]: Raw value=211960 ID=1
9413 23:45:25.891365 SKU Code: 0x1
9414 23:45:25.898162 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 7b2b
9415 23:45:25.898275 coreboot table: 964 bytes.
9416 23:45:25.901594 IMD ROOT 0. 0xfffff000 0x00001000
9417 23:45:25.904457 IMD SMALL 1. 0xffffe000 0x00001000
9418 23:45:25.907758 RO MCACHE 2. 0xffffc000 0x00001104
9419 23:45:25.911105 CONSOLE 3. 0xfff7c000 0x00080000
9420 23:45:25.914555 FMAP 4. 0xfff7b000 0x00000452
9421 23:45:25.917853 TIME STAMP 5. 0xfff7a000 0x00000910
9422 23:45:25.921221 VBOOT WORK 6. 0xfff66000 0x00014000
9423 23:45:25.924210 RAMOOPS 7. 0xffe66000 0x00100000
9424 23:45:25.927542 COREBOOT 8. 0xffe64000 0x00002000
9425 23:45:25.930870 IMD small region:
9426 23:45:25.934248 IMD ROOT 0. 0xffffec00 0x00000400
9427 23:45:25.937515 VPD 1. 0xffffeb80 0x0000006c
9428 23:45:25.940861 MMC STATUS 2. 0xffffeb60 0x00000004
9429 23:45:25.944214 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9430 23:45:25.947605 Probing TPM: done!
9431 23:45:25.951536 Connected to device vid:did:rid of 1ae0:0028:00
9432 23:45:25.961829 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9433 23:45:25.965185 Initialized TPM device CR50 revision 0
9434 23:45:25.969007 Checking cr50 for pending updates
9435 23:45:25.972666 Reading cr50 TPM mode
9436 23:45:25.981212 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9437 23:45:25.987785 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9438 23:45:26.028487 read SPI 0x3990ec 0x4f1b0: 34859 us, 9295 KB/s, 74.360 Mbps
9439 23:45:26.031862 Checking segment from ROM address 0x40100000
9440 23:45:26.034693 Checking segment from ROM address 0x4010001c
9441 23:45:26.041975 Loading segment from ROM address 0x40100000
9442 23:45:26.042063 code (compression=0)
9443 23:45:26.048113 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9444 23:45:26.058150 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9445 23:45:26.058237 it's not compressed!
9446 23:45:26.064944 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9447 23:45:26.067958 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9448 23:45:26.088416 Loading segment from ROM address 0x4010001c
9449 23:45:26.088570 Entry Point 0x80000000
9450 23:45:26.091849 Loaded segments
9451 23:45:26.095179 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9452 23:45:26.101954 Jumping to boot code at 0x80000000(0xffe64000)
9453 23:45:26.108542 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9454 23:45:26.115308 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9455 23:45:26.123315 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9456 23:45:26.126590 Checking segment from ROM address 0x40100000
9457 23:45:26.129928 Checking segment from ROM address 0x4010001c
9458 23:45:26.136696 Loading segment from ROM address 0x40100000
9459 23:45:26.136812 code (compression=1)
9460 23:45:26.142961 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9461 23:45:26.153036 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9462 23:45:26.153127 using LZMA
9463 23:45:26.161495 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9464 23:45:26.168291 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9465 23:45:26.171113 Loading segment from ROM address 0x4010001c
9466 23:45:26.171232 Entry Point 0x54601000
9467 23:45:26.174424 Loaded segments
9468 23:45:26.178232 NOTICE: MT8192 bl31_setup
9469 23:45:26.184874 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9470 23:45:26.188414 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9471 23:45:26.191829 WARNING: region 0:
9472 23:45:26.195065 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9473 23:45:26.195150 WARNING: region 1:
9474 23:45:26.201903 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9475 23:45:26.205250 WARNING: region 2:
9476 23:45:26.208046 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9477 23:45:26.211985 WARNING: region 3:
9478 23:45:26.215077 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9479 23:45:26.218076 WARNING: region 4:
9480 23:45:26.224522 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9481 23:45:26.224621 WARNING: region 5:
9482 23:45:26.228130 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9483 23:45:26.231607 WARNING: region 6:
9484 23:45:26.234671 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9485 23:45:26.238025 WARNING: region 7:
9486 23:45:26.241144 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9487 23:45:26.248145 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9488 23:45:26.251602 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9489 23:45:26.254945 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9490 23:45:26.261084 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9491 23:45:26.264495 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9492 23:45:26.267915 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9493 23:45:26.274611 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9494 23:45:26.278077 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9495 23:45:26.284528 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9496 23:45:26.287862 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9497 23:45:26.290961 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9498 23:45:26.297772 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9499 23:45:26.301314 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9500 23:45:26.304810 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9501 23:45:26.311324 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9502 23:45:26.314713 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9503 23:45:26.321154 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9504 23:45:26.324871 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9505 23:45:26.327955 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9506 23:45:26.334651 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9507 23:45:26.337647 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9508 23:45:26.341229 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9509 23:45:26.347622 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9510 23:45:26.351132 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9511 23:45:26.358031 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9512 23:45:26.361454 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9513 23:45:26.367714 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9514 23:45:26.371182 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9515 23:45:26.374513 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9516 23:45:26.381272 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9517 23:45:26.384561 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9518 23:45:26.388045 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9519 23:45:26.394344 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9520 23:45:26.397966 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9521 23:45:26.401333 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9522 23:45:26.404423 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9523 23:45:26.411455 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9524 23:45:26.414571 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9525 23:45:26.418514 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9526 23:45:26.421393 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9527 23:45:26.428058 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9528 23:45:26.431283 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9529 23:45:26.434716 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9530 23:45:26.438058 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9531 23:45:26.444607 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9532 23:45:26.447904 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9533 23:45:26.451244 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9534 23:45:26.454466 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9535 23:45:26.460846 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9536 23:45:26.464396 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9537 23:45:26.471275 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9538 23:45:26.474399 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9539 23:45:26.481283 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9540 23:45:26.484532 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9541 23:45:26.487915 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9542 23:45:26.494664 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9543 23:45:26.498119 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9544 23:45:26.504369 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9545 23:45:26.507658 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9546 23:45:26.514223 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9547 23:45:26.517692 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9548 23:45:26.520978 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9549 23:45:26.527819 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9550 23:45:26.531220 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9551 23:45:26.537712 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9552 23:45:26.541218 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9553 23:45:26.547662 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9554 23:45:26.551188 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9555 23:45:26.557853 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9556 23:45:26.560783 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9557 23:45:26.564403 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9558 23:45:26.571077 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9559 23:45:26.574168 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9560 23:45:26.581042 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9561 23:45:26.583984 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9562 23:45:26.590644 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9563 23:45:26.594494 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9564 23:45:26.597877 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9565 23:45:26.604121 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9566 23:45:26.607407 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9567 23:45:26.614020 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9568 23:45:26.617423 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9569 23:45:26.623993 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9570 23:45:26.627710 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9571 23:45:26.631187 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9572 23:45:26.637318 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9573 23:45:26.640791 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9574 23:45:26.647354 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9575 23:45:26.650926 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9576 23:45:26.657168 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9577 23:45:26.660728 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9578 23:45:26.664176 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9579 23:45:26.670826 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9580 23:45:26.674051 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9581 23:45:26.680875 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9582 23:45:26.684473 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9583 23:45:26.687772 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9584 23:45:26.694065 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9585 23:45:26.697560 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9586 23:45:26.701023 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9587 23:45:26.704349 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9588 23:45:26.711005 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9589 23:45:26.714401 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9590 23:45:26.721145 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9591 23:45:26.724369 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9592 23:45:26.727784 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9593 23:45:26.734332 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9594 23:45:26.737756 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9595 23:45:26.744401 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9596 23:45:26.747885 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9597 23:45:26.751187 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9598 23:45:26.757484 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9599 23:45:26.760733 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9600 23:45:26.767714 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9601 23:45:26.770904 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9602 23:45:26.774176 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9603 23:45:26.780674 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9604 23:45:26.784435 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9605 23:45:26.787527 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9606 23:45:26.794015 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9607 23:45:26.797429 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9608 23:45:26.800751 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9609 23:45:26.803964 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9610 23:45:26.810620 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9611 23:45:26.814038 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9612 23:45:26.817401 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9613 23:45:26.823885 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9614 23:45:26.827268 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9615 23:45:26.833889 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9616 23:45:26.837130 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9617 23:45:26.840520 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9618 23:45:26.847251 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9619 23:45:26.850559 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9620 23:45:26.853993 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9621 23:45:26.860747 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9622 23:45:26.864043 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9623 23:45:26.870828 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9624 23:45:26.874301 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9625 23:45:26.877535 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9626 23:45:26.884142 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9627 23:45:26.887185 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9628 23:45:26.893863 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9629 23:45:26.897248 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9630 23:45:26.900482 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9631 23:45:26.907136 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9632 23:45:26.910768 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9633 23:45:26.914426 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9634 23:45:26.920758 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9635 23:45:26.924036 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9636 23:45:26.930530 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9637 23:45:26.934114 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9638 23:45:26.937284 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9639 23:45:26.943911 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9640 23:45:26.947403 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9641 23:45:26.954105 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9642 23:45:26.957482 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9643 23:45:26.960898 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9644 23:45:26.967607 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9645 23:45:26.970379 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9646 23:45:26.973931 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9647 23:45:26.980465 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9648 23:45:26.983658 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9649 23:45:26.990493 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9650 23:45:26.994062 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9651 23:45:26.997234 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9652 23:45:27.003933 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9653 23:45:27.007355 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9654 23:45:27.013957 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9655 23:45:27.017411 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9656 23:45:27.020510 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9657 23:45:27.027163 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9658 23:45:27.030409 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9659 23:45:27.037076 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9660 23:45:27.040307 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9661 23:45:27.043331 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9662 23:45:27.050272 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9663 23:45:27.053839 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9664 23:45:27.060038 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9665 23:45:27.063308 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9666 23:45:27.066682 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9667 23:45:27.073361 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9668 23:45:27.076790 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9669 23:45:27.080140 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9670 23:45:27.086740 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9671 23:45:27.090143 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9672 23:45:27.096899 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9673 23:45:27.100055 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9674 23:45:27.103058 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9675 23:45:27.109896 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9676 23:45:27.113254 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9677 23:45:27.119590 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9678 23:45:27.122828 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9679 23:45:27.129495 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9680 23:45:27.132878 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9681 23:45:27.136199 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9682 23:45:27.142923 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9683 23:45:27.146126 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9684 23:45:27.152820 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9685 23:45:27.156178 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9686 23:45:27.162308 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9687 23:45:27.165842 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9688 23:45:27.169370 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9689 23:45:27.176091 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9690 23:45:27.178949 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9691 23:45:27.185721 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9692 23:45:27.188956 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9693 23:45:27.195745 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9694 23:45:27.199131 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9695 23:45:27.202516 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9696 23:45:27.208895 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9697 23:45:27.212127 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9698 23:45:27.219050 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9699 23:45:27.221766 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9700 23:45:27.228544 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9701 23:45:27.231846 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9702 23:45:27.235206 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9703 23:45:27.241965 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9704 23:45:27.245309 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9705 23:45:27.251636 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9706 23:45:27.255115 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9707 23:45:27.261623 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9708 23:45:27.264747 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9709 23:45:27.268361 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9710 23:45:27.274673 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9711 23:45:27.278231 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9712 23:45:27.284677 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9713 23:45:27.288150 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9714 23:45:27.294611 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9715 23:45:27.298035 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9716 23:45:27.301384 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9717 23:45:27.304743 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9718 23:45:27.308062 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9719 23:45:27.314598 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9720 23:45:27.317962 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9721 23:45:27.321117 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9722 23:45:27.327844 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9723 23:45:27.331310 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9724 23:45:27.337996 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9725 23:45:27.340900 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9726 23:45:27.344211 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9727 23:45:27.351044 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9728 23:45:27.354518 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9729 23:45:27.357804 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9730 23:45:27.364414 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9731 23:45:27.367680 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9732 23:45:27.370740 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9733 23:45:27.377408 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9734 23:45:27.380855 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9735 23:45:27.387591 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9736 23:45:27.391002 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9737 23:45:27.393732 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9738 23:45:27.400541 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9739 23:45:27.403834 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9740 23:45:27.407254 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9741 23:45:27.413792 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9742 23:45:27.417547 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9743 23:45:27.423682 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9744 23:45:27.427027 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9745 23:45:27.430817 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9746 23:45:27.437099 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9747 23:45:27.440864 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9748 23:45:27.443698 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9749 23:45:27.450439 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9750 23:45:27.453757 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9751 23:45:27.457194 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9752 23:45:27.464045 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9753 23:45:27.467152 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9754 23:45:27.473663 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9755 23:45:27.477214 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9756 23:45:27.480646 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9757 23:45:27.484011 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9758 23:45:27.487283 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9759 23:45:27.493991 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9760 23:45:27.496884 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9761 23:45:27.500235 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9762 23:45:27.503804 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9763 23:45:27.510485 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9764 23:45:27.513676 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9765 23:45:27.516883 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9766 23:45:27.520074 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9767 23:45:27.526734 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9768 23:45:27.530191 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9769 23:45:27.533498 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9770 23:45:27.540148 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9771 23:45:27.543335 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9772 23:45:27.550256 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9773 23:45:27.553257 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9774 23:45:27.560259 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9775 23:45:27.563516 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9776 23:45:27.566892 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9777 23:45:27.573545 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9778 23:45:27.576871 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9779 23:45:27.583097 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9780 23:45:27.586240 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9781 23:45:27.589610 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9782 23:45:27.596779 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9783 23:45:27.599486 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9784 23:45:27.606166 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9785 23:45:27.609532 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9786 23:45:27.612876 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9787 23:45:27.619819 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9788 23:45:27.623094 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9789 23:45:27.629317 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9790 23:45:27.632686 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9791 23:45:27.639683 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9792 23:45:27.643164 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9793 23:45:27.646049 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9794 23:45:27.652564 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9795 23:45:27.656406 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9796 23:45:27.662437 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9797 23:45:27.666316 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9798 23:45:27.669338 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9799 23:45:27.675803 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9800 23:45:27.679223 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9801 23:45:27.685825 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9802 23:45:27.689052 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9803 23:45:27.692516 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9804 23:45:27.699004 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9805 23:45:27.702337 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9806 23:45:27.709135 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9807 23:45:27.712533 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9808 23:45:27.715873 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9809 23:45:27.722035 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9810 23:45:27.725521 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9811 23:45:27.732061 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9812 23:45:27.735258 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9813 23:45:27.742279 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9814 23:45:27.745536 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9815 23:45:27.748792 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9816 23:45:27.755446 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9817 23:45:27.758787 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9818 23:45:27.765032 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9819 23:45:27.768322 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9820 23:45:27.772009 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9821 23:45:27.778299 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9822 23:45:27.781598 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9823 23:45:27.788485 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9824 23:45:27.791814 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9825 23:45:27.795274 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9826 23:45:27.801945 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9827 23:45:27.805273 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9828 23:45:27.811439 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9829 23:45:27.814763 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9830 23:45:27.821617 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9831 23:45:27.825061 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9832 23:45:27.828288 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9833 23:45:27.835157 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9834 23:45:27.838524 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9835 23:45:27.845299 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9836 23:45:27.848856 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9837 23:45:27.851571 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9838 23:45:27.858358 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9839 23:45:27.862108 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9840 23:45:27.868459 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9841 23:45:27.871596 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9842 23:45:27.874963 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9843 23:45:27.881672 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9844 23:45:27.885005 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9845 23:45:27.892008 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9846 23:45:27.894795 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9847 23:45:27.901600 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9848 23:45:27.904851 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9849 23:45:27.908043 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9850 23:45:27.914964 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9851 23:45:27.918068 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9852 23:45:27.924958 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9853 23:45:27.928287 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9854 23:45:27.934556 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9855 23:45:27.937888 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9856 23:45:27.944607 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9857 23:45:27.947927 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9858 23:45:27.951276 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9859 23:45:27.957440 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9860 23:45:27.961483 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9861 23:45:27.967491 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9862 23:45:27.971147 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9863 23:45:27.977260 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9864 23:45:27.980757 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9865 23:45:27.987450 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9866 23:45:27.990989 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9867 23:45:27.994468 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9868 23:45:28.000855 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9869 23:45:28.003991 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9870 23:45:28.010901 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9871 23:45:28.013705 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9872 23:45:28.020574 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9873 23:45:28.024017 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9874 23:45:28.026973 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9875 23:45:28.033652 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9876 23:45:28.037042 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9877 23:45:28.043755 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9878 23:45:28.047027 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9879 23:45:28.053815 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9880 23:45:28.057157 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9881 23:45:28.063808 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9882 23:45:28.067124 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9883 23:45:28.069950 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9884 23:45:28.076540 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9885 23:45:28.079811 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9886 23:45:28.086333 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9887 23:45:28.090191 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9888 23:45:28.096680 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9889 23:45:28.099880 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9890 23:45:28.103569 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9891 23:45:28.109632 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9892 23:45:28.113016 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9893 23:45:28.119440 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9894 23:45:28.122788 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9895 23:45:28.129585 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9896 23:45:28.133064 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9897 23:45:28.139425 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9898 23:45:28.142963 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9899 23:45:28.149538 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9900 23:45:28.152884 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9901 23:45:28.159725 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9902 23:45:28.162553 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9903 23:45:28.169370 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9904 23:45:28.172643 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9905 23:45:28.179589 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9906 23:45:28.182342 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9907 23:45:28.188879 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9908 23:45:28.192461 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9909 23:45:28.199018 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9910 23:45:28.202413 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9911 23:45:28.208628 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9912 23:45:28.212477 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9913 23:45:28.218702 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9914 23:45:28.222525 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9915 23:45:28.229211 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9916 23:45:28.231893 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9917 23:45:28.238442 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9918 23:45:28.241758 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9919 23:45:28.248672 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9920 23:45:28.252166 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9921 23:45:28.255541 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9922 23:45:28.258809 INFO: [APUAPC] vio 0
9923 23:45:28.265108 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9924 23:45:28.268372 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9925 23:45:28.271918 INFO: [APUAPC] D0_APC_0: 0x400510
9926 23:45:28.275189 INFO: [APUAPC] D0_APC_1: 0x0
9927 23:45:28.278621 INFO: [APUAPC] D0_APC_2: 0x1540
9928 23:45:28.282056 INFO: [APUAPC] D0_APC_3: 0x0
9929 23:45:28.284887 INFO: [APUAPC] D1_APC_0: 0xffffffff
9930 23:45:28.288058 INFO: [APUAPC] D1_APC_1: 0xffffffff
9931 23:45:28.291798 INFO: [APUAPC] D1_APC_2: 0x3fffff
9932 23:45:28.295086 INFO: [APUAPC] D1_APC_3: 0x0
9933 23:45:28.298306 INFO: [APUAPC] D2_APC_0: 0xffffffff
9934 23:45:28.301307 INFO: [APUAPC] D2_APC_1: 0xffffffff
9935 23:45:28.304618 INFO: [APUAPC] D2_APC_2: 0x3fffff
9936 23:45:28.308461 INFO: [APUAPC] D2_APC_3: 0x0
9937 23:45:28.311793 INFO: [APUAPC] D3_APC_0: 0xffffffff
9938 23:45:28.314628 INFO: [APUAPC] D3_APC_1: 0xffffffff
9939 23:45:28.318329 INFO: [APUAPC] D3_APC_2: 0x3fffff
9940 23:45:28.321408 INFO: [APUAPC] D3_APC_3: 0x0
9941 23:45:28.324946 INFO: [APUAPC] D4_APC_0: 0xffffffff
9942 23:45:28.328363 INFO: [APUAPC] D4_APC_1: 0xffffffff
9943 23:45:28.331546 INFO: [APUAPC] D4_APC_2: 0x3fffff
9944 23:45:28.331623 INFO: [APUAPC] D4_APC_3: 0x0
9945 23:45:28.334836 INFO: [APUAPC] D5_APC_0: 0xffffffff
9946 23:45:28.338117 INFO: [APUAPC] D5_APC_1: 0xffffffff
9947 23:45:28.341146 INFO: [APUAPC] D5_APC_2: 0x3fffff
9948 23:45:28.344362 INFO: [APUAPC] D5_APC_3: 0x0
9949 23:45:28.348016 INFO: [APUAPC] D6_APC_0: 0xffffffff
9950 23:45:28.351397 INFO: [APUAPC] D6_APC_1: 0xffffffff
9951 23:45:28.354709 INFO: [APUAPC] D6_APC_2: 0x3fffff
9952 23:45:28.357904 INFO: [APUAPC] D6_APC_3: 0x0
9953 23:45:28.361147 INFO: [APUAPC] D7_APC_0: 0xffffffff
9954 23:45:28.364290 INFO: [APUAPC] D7_APC_1: 0xffffffff
9955 23:45:28.368063 INFO: [APUAPC] D7_APC_2: 0x3fffff
9956 23:45:28.370814 INFO: [APUAPC] D7_APC_3: 0x0
9957 23:45:28.374191 INFO: [APUAPC] D8_APC_0: 0xffffffff
9958 23:45:28.377557 INFO: [APUAPC] D8_APC_1: 0xffffffff
9959 23:45:28.381119 INFO: [APUAPC] D8_APC_2: 0x3fffff
9960 23:45:28.384435 INFO: [APUAPC] D8_APC_3: 0x0
9961 23:45:28.387803 INFO: [APUAPC] D9_APC_0: 0xffffffff
9962 23:45:28.391312 INFO: [APUAPC] D9_APC_1: 0xffffffff
9963 23:45:28.394582 INFO: [APUAPC] D9_APC_2: 0x3fffff
9964 23:45:28.397758 INFO: [APUAPC] D9_APC_3: 0x0
9965 23:45:28.401146 INFO: [APUAPC] D10_APC_0: 0xffffffff
9966 23:45:28.404552 INFO: [APUAPC] D10_APC_1: 0xffffffff
9967 23:45:28.407727 INFO: [APUAPC] D10_APC_2: 0x3fffff
9968 23:45:28.410791 INFO: [APUAPC] D10_APC_3: 0x0
9969 23:45:28.414134 INFO: [APUAPC] D11_APC_0: 0xffffffff
9970 23:45:28.417486 INFO: [APUAPC] D11_APC_1: 0xffffffff
9971 23:45:28.420906 INFO: [APUAPC] D11_APC_2: 0x3fffff
9972 23:45:28.424151 INFO: [APUAPC] D11_APC_3: 0x0
9973 23:45:28.427462 INFO: [APUAPC] D12_APC_0: 0xffffffff
9974 23:45:28.431025 INFO: [APUAPC] D12_APC_1: 0xffffffff
9975 23:45:28.433833 INFO: [APUAPC] D12_APC_2: 0x3fffff
9976 23:45:28.437120 INFO: [APUAPC] D12_APC_3: 0x0
9977 23:45:28.440508 INFO: [APUAPC] D13_APC_0: 0xffffffff
9978 23:45:28.443965 INFO: [APUAPC] D13_APC_1: 0xffffffff
9979 23:45:28.447126 INFO: [APUAPC] D13_APC_2: 0x3fffff
9980 23:45:28.450682 INFO: [APUAPC] D13_APC_3: 0x0
9981 23:45:28.453637 INFO: [APUAPC] D14_APC_0: 0xffffffff
9982 23:45:28.457034 INFO: [APUAPC] D14_APC_1: 0xffffffff
9983 23:45:28.460351 INFO: [APUAPC] D14_APC_2: 0x3fffff
9984 23:45:28.463906 INFO: [APUAPC] D14_APC_3: 0x0
9985 23:45:28.466871 INFO: [APUAPC] D15_APC_0: 0xffffffff
9986 23:45:28.470270 INFO: [APUAPC] D15_APC_1: 0xffffffff
9987 23:45:28.473626 INFO: [APUAPC] D15_APC_2: 0x3fffff
9988 23:45:28.477104 INFO: [APUAPC] D15_APC_3: 0x0
9989 23:45:28.480345 INFO: [APUAPC] APC_CON: 0x4
9990 23:45:28.483300 INFO: [NOCDAPC] D0_APC_0: 0x0
9991 23:45:28.487090 INFO: [NOCDAPC] D0_APC_1: 0x0
9992 23:45:28.490389 INFO: [NOCDAPC] D1_APC_0: 0x0
9993 23:45:28.493839 INFO: [NOCDAPC] D1_APC_1: 0xfff
9994 23:45:28.496622 INFO: [NOCDAPC] D2_APC_0: 0x0
9995 23:45:28.500105 INFO: [NOCDAPC] D2_APC_1: 0xfff
9996 23:45:28.500200 INFO: [NOCDAPC] D3_APC_0: 0x0
9997 23:45:28.503264 INFO: [NOCDAPC] D3_APC_1: 0xfff
9998 23:45:28.506620 INFO: [NOCDAPC] D4_APC_0: 0x0
9999 23:45:28.509903 INFO: [NOCDAPC] D4_APC_1: 0xfff
10000 23:45:28.513283 INFO: [NOCDAPC] D5_APC_0: 0x0
10001 23:45:28.516682 INFO: [NOCDAPC] D5_APC_1: 0xfff
10002 23:45:28.519875 INFO: [NOCDAPC] D6_APC_0: 0x0
10003 23:45:28.523235 INFO: [NOCDAPC] D6_APC_1: 0xfff
10004 23:45:28.526530 INFO: [NOCDAPC] D7_APC_0: 0x0
10005 23:45:28.529978 INFO: [NOCDAPC] D7_APC_1: 0xfff
10006 23:45:28.533365 INFO: [NOCDAPC] D8_APC_0: 0x0
10007 23:45:28.533446 INFO: [NOCDAPC] D8_APC_1: 0xfff
10008 23:45:28.536881 INFO: [NOCDAPC] D9_APC_0: 0x0
10009 23:45:28.540241 INFO: [NOCDAPC] D9_APC_1: 0xfff
10010 23:45:28.543316 INFO: [NOCDAPC] D10_APC_0: 0x0
10011 23:45:28.546771 INFO: [NOCDAPC] D10_APC_1: 0xfff
10012 23:45:28.549602 INFO: [NOCDAPC] D11_APC_0: 0x0
10013 23:45:28.552924 INFO: [NOCDAPC] D11_APC_1: 0xfff
10014 23:45:28.556286 INFO: [NOCDAPC] D12_APC_0: 0x0
10015 23:45:28.559571 INFO: [NOCDAPC] D12_APC_1: 0xfff
10016 23:45:28.562972 INFO: [NOCDAPC] D13_APC_0: 0x0
10017 23:45:28.566352 INFO: [NOCDAPC] D13_APC_1: 0xfff
10018 23:45:28.569823 INFO: [NOCDAPC] D14_APC_0: 0x0
10019 23:45:28.573209 INFO: [NOCDAPC] D14_APC_1: 0xfff
10020 23:45:28.576481 INFO: [NOCDAPC] D15_APC_0: 0x0
10021 23:45:28.579779 INFO: [NOCDAPC] D15_APC_1: 0xfff
10022 23:45:28.579884 INFO: [NOCDAPC] APC_CON: 0x4
10023 23:45:28.582607 INFO: [APUAPC] set_apusys_apc done
10024 23:45:28.586029 INFO: [DEVAPC] devapc_init done
10025 23:45:28.592954 INFO: GICv3 without legacy support detected.
10026 23:45:28.596307 INFO: ARM GICv3 driver initialized in EL3
10027 23:45:28.599559 INFO: Maximum SPI INTID supported: 639
10028 23:45:28.602798 INFO: BL31: Initializing runtime services
10029 23:45:28.609497 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10030 23:45:28.612603 INFO: SPM: enable CPC mode
10031 23:45:28.616296 INFO: mcdi ready for mcusys-off-idle and system suspend
10032 23:45:28.622942 INFO: BL31: Preparing for EL3 exit to normal world
10033 23:45:28.625834 INFO: Entry point address = 0x80000000
10034 23:45:28.625913 INFO: SPSR = 0x8
10035 23:45:28.633142
10036 23:45:28.633245
10037 23:45:28.633346
10038 23:45:28.636431 Starting depthcharge on Spherion...
10039 23:45:28.636531
10040 23:45:28.636643 Wipe memory regions:
10041 23:45:28.636733
10042 23:45:28.637590 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10043 23:45:28.637721 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10044 23:45:28.637837 Setting prompt string to ['asurada:']
10045 23:45:28.637946 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10046 23:45:28.639396 [0x00000040000000, 0x00000054600000)
10047 23:45:28.761960
10048 23:45:28.762091 [0x00000054660000, 0x00000080000000)
10049 23:45:29.022656
10050 23:45:29.022832 [0x000000821a7280, 0x000000ffe64000)
10051 23:45:29.767291
10052 23:45:29.767449 [0x00000100000000, 0x00000240000000)
10053 23:45:31.657100
10054 23:45:31.660045 Initializing XHCI USB controller at 0x11200000.
10055 23:45:32.697664
10056 23:45:32.701108 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10057 23:45:32.701250
10058 23:45:32.701346
10059 23:45:32.701670 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10061 23:45:32.802052 asurada: tftpboot 192.168.201.1 14172972/tftp-deploy-6oanwx39/kernel/image.itb 14172972/tftp-deploy-6oanwx39/kernel/cmdline
10062 23:45:32.802238 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10063 23:45:32.802368 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10064 23:45:32.806646 tftpboot 192.168.201.1 14172972/tftp-deploy-6oanwx39/kernel/image.ittp-deploy-6oanwx39/kernel/cmdline
10065 23:45:32.806760
10066 23:45:32.806828 Waiting for link
10067 23:45:32.967070
10068 23:45:32.967252 R8152: Initializing
10069 23:45:32.967355
10070 23:45:32.969969 Version 6 (ocp_data = 5c30)
10071 23:45:32.970077
10072 23:45:32.973279 R8152: Done initializing
10073 23:45:32.973387
10074 23:45:32.973482 Adding net device
10075 23:45:34.877268
10076 23:45:34.877406 done.
10077 23:45:34.877474
10078 23:45:34.877535 MAC: 00:24:32:30:78:ff
10079 23:45:34.877595
10080 23:45:34.880423 Sending DHCP discover... done.
10081 23:45:34.880504
10082 23:45:38.057057 Waiting for reply... done.
10083 23:45:38.057200
10084 23:45:38.057271 Sending DHCP request... done.
10085 23:45:38.059901
10086 23:45:38.071189 Waiting for reply... done.
10087 23:45:38.071385
10088 23:45:38.071504 My ip is 192.168.201.21
10089 23:45:38.071614
10090 23:45:38.074608 The DHCP server ip is 192.168.201.1
10091 23:45:38.074758
10092 23:45:38.081005 TFTP server IP predefined by user: 192.168.201.1
10093 23:45:38.081147
10094 23:45:38.087819 Bootfile predefined by user: 14172972/tftp-deploy-6oanwx39/kernel/image.itb
10095 23:45:38.087973
10096 23:45:38.090912 Sending tftp read request... done.
10097 23:45:38.091027
10098 23:45:38.094901 Waiting for the transfer...
10099 23:45:38.095011
10100 23:45:38.718194 00000000 ################################################################
10101 23:45:38.718334
10102 23:45:39.352150 00080000 ################################################################
10103 23:45:39.352351
10104 23:45:39.992553 00100000 ################################################################
10105 23:45:39.992726
10106 23:45:40.652356 00180000 ################################################################
10107 23:45:40.652548
10108 23:45:41.318875 00200000 ################################################################
10109 23:45:41.319057
10110 23:45:41.956275 00280000 ################################################################
10111 23:45:41.956447
10112 23:45:42.586388 00300000 ################################################################
10113 23:45:42.586530
10114 23:45:43.218284 00380000 ################################################################
10115 23:45:43.218445
10116 23:45:43.855988 00400000 ################################################################
10117 23:45:43.856160
10118 23:45:44.493342 00480000 ################################################################
10119 23:45:44.493539
10120 23:45:45.119427 00500000 ################################################################
10121 23:45:45.119600
10122 23:45:45.750180 00580000 ################################################################
10123 23:45:45.750348
10124 23:45:46.384068 00600000 ################################################################
10125 23:45:46.384202
10126 23:45:47.020062 00680000 ################################################################
10127 23:45:47.020203
10128 23:45:47.677121 00700000 ################################################################
10129 23:45:47.677257
10130 23:45:48.313181 00780000 ################################################################
10131 23:45:48.313410
10132 23:45:48.943928 00800000 ################################################################
10133 23:45:48.944162
10134 23:45:49.561933 00880000 ################################################################
10135 23:45:49.562087
10136 23:45:50.178861 00900000 ################################################################
10137 23:45:50.179064
10138 23:45:50.789784 00980000 ################################################################
10139 23:45:50.789970
10140 23:45:51.411857 00a00000 ################################################################
10141 23:45:51.412046
10142 23:45:52.029600 00a80000 ################################################################
10143 23:45:52.029792
10144 23:45:52.654775 00b00000 ################################################################
10145 23:45:52.654955
10146 23:45:53.280434 00b80000 ################################################################
10147 23:45:53.280677
10148 23:45:53.905961 00c00000 ################################################################
10149 23:45:53.906118
10150 23:45:54.531084 00c80000 ################################################################
10151 23:45:54.531274
10152 23:45:55.161585 00d00000 ################################################################
10153 23:45:55.161800
10154 23:45:55.786845 00d80000 ################################################################
10155 23:45:55.787113
10156 23:45:56.413096 00e00000 ################################################################
10157 23:45:56.413264
10158 23:45:57.026682 00e80000 ################################################################
10159 23:45:57.026871
10160 23:45:57.645139 00f00000 ################################################################
10161 23:45:57.645297
10162 23:45:58.206542 00f80000 ################################################################
10163 23:45:58.206682
10164 23:45:58.739991 01000000 ################################################################
10165 23:45:58.740166
10166 23:45:59.263110 01080000 ################################################################
10167 23:45:59.263254
10168 23:45:59.792017 01100000 ################################################################
10169 23:45:59.792171
10170 23:46:00.316918 01180000 ################################################################
10171 23:46:00.317053
10172 23:46:00.847704 01200000 ################################################################
10173 23:46:00.847897
10174 23:46:01.377118 01280000 ################################################################
10175 23:46:01.377340
10176 23:46:01.901415 01300000 ################################################################
10177 23:46:01.901607
10178 23:46:02.423714 01380000 ################################################################
10179 23:46:02.423927
10180 23:46:02.962882 01400000 ################################################################
10181 23:46:02.963068
10182 23:46:03.498043 01480000 ################################################################
10183 23:46:03.498219
10184 23:46:04.026531 01500000 ################################################################
10185 23:46:04.026684
10186 23:46:04.557057 01580000 ################################################################
10187 23:46:04.557275
10188 23:46:05.089456 01600000 ################################################################
10189 23:46:05.089686
10190 23:46:05.614743 01680000 ################################################################
10191 23:46:05.614880
10192 23:46:06.175889 01700000 ################################################################
10193 23:46:06.176098
10194 23:46:06.728026 01780000 ################################################################
10195 23:46:06.728158
10196 23:46:07.273100 01800000 ################################################################
10197 23:46:07.273230
10198 23:46:07.809726 01880000 ################################################################
10199 23:46:07.809884
10200 23:46:08.338869 01900000 ################################################################
10201 23:46:08.339004
10202 23:46:08.866478 01980000 ################################################################
10203 23:46:08.866672
10204 23:46:09.405767 01a00000 ################################################################
10205 23:46:09.405980
10206 23:46:09.944564 01a80000 ################################################################
10207 23:46:09.944710
10208 23:46:10.477938 01b00000 ################################################################
10209 23:46:10.478069
10210 23:46:11.007636 01b80000 ################################################################
10211 23:46:11.007773
10212 23:46:11.578338 01c00000 ################################################################
10213 23:46:11.578482
10214 23:46:12.132745 01c80000 ################################################################
10215 23:46:12.132882
10216 23:46:12.674516 01d00000 ################################################################
10217 23:46:12.674668
10218 23:46:13.210173 01d80000 ################################################################
10219 23:46:13.210368
10220 23:46:13.752984 01e00000 ################################################################
10221 23:46:13.753114
10222 23:46:14.319965 01e80000 ################################################################
10223 23:46:14.320124
10224 23:46:14.895888 01f00000 ################################################################
10225 23:46:14.896076
10226 23:46:15.456969 01f80000 ################################################################
10227 23:46:15.457159
10228 23:46:16.011061 02000000 ################################################################
10229 23:46:16.011253
10230 23:46:16.555036 02080000 ################################################################
10231 23:46:16.555241
10232 23:46:17.098268 02100000 ################################################################
10233 23:46:17.098401
10234 23:46:17.642112 02180000 ################################################################
10235 23:46:17.642253
10236 23:46:18.191750 02200000 ################################################################
10237 23:46:18.191884
10238 23:46:18.716236 02280000 ################################################################
10239 23:46:18.716401
10240 23:46:19.276737 02300000 ################################################################
10241 23:46:19.276921
10242 23:46:19.929368 02380000 ################################################################
10243 23:46:19.929519
10244 23:46:20.553415 02400000 ################################################################
10245 23:46:20.553553
10246 23:46:21.103938 02480000 ################################################################
10247 23:46:21.104156
10248 23:46:21.647360 02500000 ################################################################
10249 23:46:21.647520
10250 23:46:22.188415 02580000 ################################################################
10251 23:46:22.188613
10252 23:46:22.739821 02600000 ################################################################
10253 23:46:22.739979
10254 23:46:23.291161 02680000 ################################################################
10255 23:46:23.291357
10256 23:46:23.847886 02700000 ################################################################
10257 23:46:23.848026
10258 23:46:24.419001 02780000 ################################################################
10259 23:46:24.419170
10260 23:46:24.966270 02800000 ################################################################
10261 23:46:24.966414
10262 23:46:25.509231 02880000 ################################################################
10263 23:46:25.509369
10264 23:46:26.102130 02900000 ################################################################
10265 23:46:26.102286
10266 23:46:26.684927 02980000 ################################################################
10267 23:46:26.685067
10268 23:46:27.297661 02a00000 ################################################################
10269 23:46:27.297823
10270 23:46:27.935889 02a80000 ################################################################
10271 23:46:27.936071
10272 23:46:28.576230 02b00000 ################################################################
10273 23:46:28.576374
10274 23:46:29.233969 02b80000 ################################################################
10275 23:46:29.234111
10276 23:46:29.886139 02c00000 ################################################################
10277 23:46:29.886283
10278 23:46:30.496501 02c80000 ################################################################
10279 23:46:30.496746
10280 23:46:31.089872 02d00000 ################################################################
10281 23:46:31.090049
10282 23:46:31.659615 02d80000 ################################################################
10283 23:46:31.659826
10284 23:46:32.216170 02e00000 ################################################################
10285 23:46:32.216342
10286 23:46:32.762526 02e80000 ################################################################
10287 23:46:32.762759
10288 23:46:33.307815 02f00000 ################################################################
10289 23:46:33.308010
10290 23:46:33.853281 02f80000 ################################################################
10291 23:46:33.853495
10292 23:46:34.403000 03000000 ################################################################
10293 23:46:34.403184
10294 23:46:34.934944 03080000 ################################################################
10295 23:46:34.935143
10296 23:46:35.470250 03100000 ################################################################
10297 23:46:35.470458
10298 23:46:36.006469 03180000 ################################################################
10299 23:46:36.006679
10300 23:46:36.528763 03200000 ################################################################
10301 23:46:36.528976
10302 23:46:37.052355 03280000 ################################################################
10303 23:46:37.052500
10304 23:46:37.576632 03300000 ################################################################
10305 23:46:37.576806
10306 23:46:37.893739 03380000 ####################################### done.
10307 23:46:37.893896
10308 23:46:37.896755 The bootfile was 54319278 bytes long.
10309 23:46:37.896907
10310 23:46:37.900120 Sending tftp read request... done.
10311 23:46:37.900213
10312 23:46:37.900280 Waiting for the transfer...
10313 23:46:37.900341
10314 23:46:37.903577 00000000 # done.
10315 23:46:37.903674
10316 23:46:37.909949 Command line loaded dynamically from TFTP file: 14172972/tftp-deploy-6oanwx39/kernel/cmdline
10317 23:46:37.910043
10318 23:46:37.923605 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10319 23:46:37.923744
10320 23:46:37.926409 Loading FIT.
10321 23:46:37.926521
10322 23:46:37.929862 Image ramdisk-1 has 41208553 bytes.
10323 23:46:37.929951
10324 23:46:37.933180 Image fdt-1 has 47258 bytes.
10325 23:46:37.933265
10326 23:46:37.933331 Image kernel-1 has 13061430 bytes.
10327 23:46:37.936718
10328 23:46:37.943316 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10329 23:46:37.943442
10330 23:46:37.962900 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10331 23:46:37.963041
10332 23:46:37.966237 Choosing best match conf-1 for compat google,spherion-rev2.
10333 23:46:37.971003
10334 23:46:37.975798 Connected to device vid:did:rid of 1ae0:0028:00
10335 23:46:37.983587
10336 23:46:37.986908 tpm_get_response: command 0x17b, return code 0x0
10337 23:46:37.986992
10338 23:46:37.990222 ec_init: CrosEC protocol v3 supported (256, 248)
10339 23:46:37.994084
10340 23:46:37.997520 tpm_cleanup: add release locality here.
10341 23:46:37.997616
10342 23:46:37.997685 Shutting down all USB controllers.
10343 23:46:38.000867
10344 23:46:38.000946 Removing current net device
10345 23:46:38.001009
10346 23:46:38.007319 Exiting depthcharge with code 4 at timestamp: 98685598
10347 23:46:38.007409
10348 23:46:38.010670 LZMA decompressing kernel-1 to 0x821a6718
10349 23:46:38.010765
10350 23:46:38.014405 LZMA decompressing kernel-1 to 0x40000000
10351 23:46:39.624077
10352 23:46:39.624284 jumping to kernel
10353 23:46:39.625140 end: 2.2.4 bootloader-commands (duration 00:01:11) [common]
10354 23:46:39.625305 start: 2.2.5 auto-login-action (timeout 00:03:14) [common]
10355 23:46:39.625436 Setting prompt string to ['Linux version [0-9]']
10356 23:46:39.625565 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10357 23:46:39.625690 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10358 23:46:39.706914
10359 23:46:39.710295 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10360 23:46:39.713977 start: 2.2.5.1 login-action (timeout 00:03:14) [common]
10361 23:46:39.714134 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10362 23:46:39.714262 Setting prompt string to []
10363 23:46:39.714393 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10364 23:46:39.714528 Using line separator: #'\n'#
10365 23:46:39.714637 No login prompt set.
10366 23:46:39.714749 Parsing kernel messages
10367 23:46:39.714857 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10368 23:46:39.715054 [login-action] Waiting for messages, (timeout 00:03:14)
10369 23:46:39.715176 Waiting using forced prompt support (timeout 00:01:37)
10370 23:46:39.733606 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j217067-arm64-gcc-10-defconfig-arm64-chromebook-s48tj) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 4 23:28:43 UTC 2024
10371 23:46:39.736944 [ 0.000000] random: crng init done
10372 23:46:39.743427 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10373 23:46:39.746606 [ 0.000000] efi: UEFI not found.
10374 23:46:39.753343 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10375 23:46:39.759637 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10376 23:46:39.769723 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10377 23:46:39.779818 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10378 23:46:39.786419 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10379 23:46:39.792663 [ 0.000000] printk: bootconsole [mtk8250] enabled
10380 23:46:39.799223 [ 0.000000] NUMA: No NUMA configuration found
10381 23:46:39.806182 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10382 23:46:39.808904 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10383 23:46:39.812385 [ 0.000000] Zone ranges:
10384 23:46:39.819230 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10385 23:46:39.822074 [ 0.000000] DMA32 empty
10386 23:46:39.828818 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10387 23:46:39.832196 [ 0.000000] Movable zone start for each node
10388 23:46:39.835423 [ 0.000000] Early memory node ranges
10389 23:46:39.842146 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10390 23:46:39.848782 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10391 23:46:39.855529 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10392 23:46:39.861915 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10393 23:46:39.868725 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10394 23:46:39.875192 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10395 23:46:39.931629 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10396 23:46:39.937805 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10397 23:46:39.944538 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10398 23:46:39.947809 [ 0.000000] psci: probing for conduit method from DT.
10399 23:46:39.954634 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10400 23:46:39.958023 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10401 23:46:39.964368 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10402 23:46:39.968186 [ 0.000000] psci: SMC Calling Convention v1.2
10403 23:46:39.974786 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10404 23:46:39.977973 [ 0.000000] Detected VIPT I-cache on CPU0
10405 23:46:39.984691 [ 0.000000] CPU features: detected: GIC system register CPU interface
10406 23:46:39.990986 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10407 23:46:39.997829 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10408 23:46:40.004341 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10409 23:46:40.010770 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10410 23:46:40.017652 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10411 23:46:40.024326 [ 0.000000] alternatives: applying boot alternatives
10412 23:46:40.031201 [ 0.000000] Fallback order for Node 0: 0
10413 23:46:40.037491 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10414 23:46:40.040822 [ 0.000000] Policy zone: Normal
10415 23:46:40.053687 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10416 23:46:40.064043 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10417 23:46:40.075823 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10418 23:46:40.085679 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10419 23:46:40.092394 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10420 23:46:40.095871 <6>[ 0.000000] software IO TLB: area num 8.
10421 23:46:40.152577 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10422 23:46:40.301944 <6>[ 0.000000] Memory: 7923944K/8385536K available (18112K kernel code, 4120K rwdata, 22504K rodata, 8512K init, 616K bss, 428824K reserved, 32768K cma-reserved)
10423 23:46:40.308632 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10424 23:46:40.314974 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10425 23:46:40.318476 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10426 23:46:40.325276 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10427 23:46:40.331275 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10428 23:46:40.334799 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10429 23:46:40.344824 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10430 23:46:40.351681 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10431 23:46:40.358030 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10432 23:46:40.364669 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10433 23:46:40.368055 <6>[ 0.000000] GICv3: 608 SPIs implemented
10434 23:46:40.370935 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10435 23:46:40.377754 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10436 23:46:40.380969 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10437 23:46:40.387776 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10438 23:46:40.400828 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10439 23:46:40.414033 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10440 23:46:40.420391 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10441 23:46:40.428406 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10442 23:46:40.441585 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10443 23:46:40.448148 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10444 23:46:40.454969 <6>[ 0.009175] Console: colour dummy device 80x25
10445 23:46:40.464910 <6>[ 0.013932] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10446 23:46:40.471412 <6>[ 0.024438] pid_max: default: 32768 minimum: 301
10447 23:46:40.474883 <6>[ 0.029309] LSM: Security Framework initializing
10448 23:46:40.481601 <6>[ 0.034246] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10449 23:46:40.491219 <6>[ 0.042107] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10450 23:46:40.501052 <6>[ 0.051594] cblist_init_generic: Setting adjustable number of callback queues.
10451 23:46:40.504682 <6>[ 0.059083] cblist_init_generic: Setting shift to 3 and lim to 1.
10452 23:46:40.514612 <6>[ 0.065462] cblist_init_generic: Setting adjustable number of callback queues.
10453 23:46:40.521007 <6>[ 0.072935] cblist_init_generic: Setting shift to 3 and lim to 1.
10454 23:46:40.524131 <6>[ 0.079336] rcu: Hierarchical SRCU implementation.
10455 23:46:40.530800 <6>[ 0.084381] rcu: Max phase no-delay instances is 1000.
10456 23:46:40.537460 <6>[ 0.091401] EFI services will not be available.
10457 23:46:40.540735 <6>[ 0.096383] smp: Bringing up secondary CPUs ...
10458 23:46:40.549889 <6>[ 0.101461] Detected VIPT I-cache on CPU1
10459 23:46:40.555993 <6>[ 0.101535] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10460 23:46:40.562945 <6>[ 0.101566] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10461 23:46:40.566136 <6>[ 0.101904] Detected VIPT I-cache on CPU2
10462 23:46:40.572823 <6>[ 0.101958] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10463 23:46:40.582464 <6>[ 0.101977] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10464 23:46:40.585818 <6>[ 0.102234] Detected VIPT I-cache on CPU3
10465 23:46:40.592618 <6>[ 0.102280] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10466 23:46:40.599294 <6>[ 0.102295] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10467 23:46:40.602492 <6>[ 0.102595] CPU features: detected: Spectre-v4
10468 23:46:40.609189 <6>[ 0.102601] CPU features: detected: Spectre-BHB
10469 23:46:40.612207 <6>[ 0.102606] Detected PIPT I-cache on CPU4
10470 23:46:40.618923 <6>[ 0.102665] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10471 23:46:40.625440 <6>[ 0.102682] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10472 23:46:40.632362 <6>[ 0.102970] Detected PIPT I-cache on CPU5
10473 23:46:40.638961 <6>[ 0.103031] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10474 23:46:40.645562 <6>[ 0.103047] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10475 23:46:40.648932 <6>[ 0.103329] Detected PIPT I-cache on CPU6
10476 23:46:40.655575 <6>[ 0.103392] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10477 23:46:40.661880 <6>[ 0.103408] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10478 23:46:40.668677 <6>[ 0.103702] Detected PIPT I-cache on CPU7
10479 23:46:40.675127 <6>[ 0.103765] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10480 23:46:40.682074 <6>[ 0.103781] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10481 23:46:40.684931 <6>[ 0.103828] smp: Brought up 1 node, 8 CPUs
10482 23:46:40.691704 <6>[ 0.245166] SMP: Total of 8 processors activated.
10483 23:46:40.695004 <6>[ 0.250087] CPU features: detected: 32-bit EL0 Support
10484 23:46:40.705116 <6>[ 0.255450] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10485 23:46:40.711737 <6>[ 0.264251] CPU features: detected: Common not Private translations
10486 23:46:40.718110 <6>[ 0.270727] CPU features: detected: CRC32 instructions
10487 23:46:40.721558 <6>[ 0.276084] CPU features: detected: RCpc load-acquire (LDAPR)
10488 23:46:40.728265 <6>[ 0.282044] CPU features: detected: LSE atomic instructions
10489 23:46:40.734782 <6>[ 0.287825] CPU features: detected: Privileged Access Never
10490 23:46:40.741621 <6>[ 0.293605] CPU features: detected: RAS Extension Support
10491 23:46:40.747868 <6>[ 0.299249] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10492 23:46:40.751241 <6>[ 0.306468] CPU: All CPU(s) started at EL2
10493 23:46:40.757893 <6>[ 0.310784] alternatives: applying system-wide alternatives
10494 23:46:40.767270 <6>[ 0.321607] devtmpfs: initialized
10495 23:46:40.779289 <6>[ 0.330406] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10496 23:46:40.789150 <6>[ 0.340367] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10497 23:46:40.796139 <6>[ 0.348402] pinctrl core: initialized pinctrl subsystem
10498 23:46:40.799392 <6>[ 0.355085] DMI not present or invalid.
10499 23:46:40.805602 <6>[ 0.359404] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10500 23:46:40.815656 <6>[ 0.366274] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10501 23:46:40.822320 <6>[ 0.373864] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10502 23:46:40.831829 <6>[ 0.382081] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10503 23:46:40.835547 <6>[ 0.390322] audit: initializing netlink subsys (disabled)
10504 23:46:40.844909 <5>[ 0.396017] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10505 23:46:40.851829 <6>[ 0.396735] thermal_sys: Registered thermal governor 'step_wise'
10506 23:46:40.858397 <6>[ 0.403983] thermal_sys: Registered thermal governor 'power_allocator'
10507 23:46:40.861830 <6>[ 0.410239] cpuidle: using governor menu
10508 23:46:40.868019 <6>[ 0.421197] NET: Registered PF_QIPCRTR protocol family
10509 23:46:40.874700 <6>[ 0.426680] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10510 23:46:40.881675 <6>[ 0.433785] ASID allocator initialised with 32768 entries
10511 23:46:40.884486 <6>[ 0.440352] Serial: AMBA PL011 UART driver
10512 23:46:40.895055 <4>[ 0.449203] Trying to register duplicate clock ID: 134
10513 23:46:40.952658 <6>[ 0.510428] KASLR enabled
10514 23:46:40.967114 <6>[ 0.518104] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10515 23:46:40.973451 <6>[ 0.525116] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10516 23:46:40.980105 <6>[ 0.531605] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10517 23:46:40.986898 <6>[ 0.538612] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10518 23:46:40.993135 <6>[ 0.545098] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10519 23:46:41.000019 <6>[ 0.552104] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10520 23:46:41.006398 <6>[ 0.558590] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10521 23:46:41.013298 <6>[ 0.565592] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10522 23:46:41.016192 <6>[ 0.573037] ACPI: Interpreter disabled.
10523 23:46:41.025122 <6>[ 0.579467] iommu: Default domain type: Translated
10524 23:46:41.031858 <6>[ 0.584581] iommu: DMA domain TLB invalidation policy: strict mode
10525 23:46:41.035195 <5>[ 0.591244] SCSI subsystem initialized
10526 23:46:41.041949 <6>[ 0.595497] usbcore: registered new interface driver usbfs
10527 23:46:41.047960 <6>[ 0.601227] usbcore: registered new interface driver hub
10528 23:46:41.051297 <6>[ 0.606778] usbcore: registered new device driver usb
10529 23:46:41.058724 <6>[ 0.612889] pps_core: LinuxPPS API ver. 1 registered
10530 23:46:41.068768 <6>[ 0.618080] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10531 23:46:41.071834 <6>[ 0.627423] PTP clock support registered
10532 23:46:41.074975 <6>[ 0.631665] EDAC MC: Ver: 3.0.0
10533 23:46:41.082486 <6>[ 0.636849] FPGA manager framework
10534 23:46:41.089384 <6>[ 0.640529] Advanced Linux Sound Architecture Driver Initialized.
10535 23:46:41.092214 <6>[ 0.647302] vgaarb: loaded
10536 23:46:41.099090 <6>[ 0.650455] clocksource: Switched to clocksource arch_sys_counter
10537 23:46:41.102440 <5>[ 0.656906] VFS: Disk quotas dquot_6.6.0
10538 23:46:41.109463 <6>[ 0.661087] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10539 23:46:41.112373 <6>[ 0.668278] pnp: PnP ACPI: disabled
10540 23:46:41.120493 <6>[ 0.674945] NET: Registered PF_INET protocol family
10541 23:46:41.130179 <6>[ 0.680536] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10542 23:46:41.141593 <6>[ 0.692853] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10543 23:46:41.151401 <6>[ 0.701667] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10544 23:46:41.158316 <6>[ 0.709638] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10545 23:46:41.168156 <6>[ 0.718339] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10546 23:46:41.174742 <6>[ 0.728058] TCP: Hash tables configured (established 65536 bind 65536)
10547 23:46:41.181428 <6>[ 0.734930] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10548 23:46:41.191149 <6>[ 0.742127] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10549 23:46:41.197786 <6>[ 0.749834] NET: Registered PF_UNIX/PF_LOCAL protocol family
10550 23:46:41.201167 <6>[ 0.755978] RPC: Registered named UNIX socket transport module.
10551 23:46:41.207987 <6>[ 0.762131] RPC: Registered udp transport module.
10552 23:46:41.210804 <6>[ 0.767063] RPC: Registered tcp transport module.
10553 23:46:41.220934 <6>[ 0.771994] RPC: Registered tcp NFSv4.1 backchannel transport module.
10554 23:46:41.224138 <6>[ 0.778661] PCI: CLS 0 bytes, default 64
10555 23:46:41.227212 <6>[ 0.783009] Unpacking initramfs...
10556 23:46:41.244056 <6>[ 0.794926] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10557 23:46:41.253491 <6>[ 0.803545] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10558 23:46:41.256928 <6>[ 0.812350] kvm [1]: IPA Size Limit: 40 bits
10559 23:46:41.263481 <6>[ 0.816876] kvm [1]: GICv3: no GICV resource entry
10560 23:46:41.266730 <6>[ 0.821895] kvm [1]: disabling GICv2 emulation
10561 23:46:41.273368 <6>[ 0.826580] kvm [1]: GIC system register CPU interface enabled
10562 23:46:41.277064 <6>[ 0.832735] kvm [1]: vgic interrupt IRQ18
10563 23:46:41.283719 <6>[ 0.837092] kvm [1]: VHE mode initialized successfully
10564 23:46:41.289819 <5>[ 0.843528] Initialise system trusted keyrings
10565 23:46:41.296699 <6>[ 0.848329] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10566 23:46:41.304283 <6>[ 0.858516] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10567 23:46:41.310548 <5>[ 0.864889] NFS: Registering the id_resolver key type
10568 23:46:41.313916 <5>[ 0.870189] Key type id_resolver registered
10569 23:46:41.320604 <5>[ 0.874604] Key type id_legacy registered
10570 23:46:41.327337 <6>[ 0.878877] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10571 23:46:41.334225 <6>[ 0.885796] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10572 23:46:41.340163 <6>[ 0.893500] 9p: Installing v9fs 9p2000 file system support
10573 23:46:41.376588 <5>[ 0.931045] Key type asymmetric registered
10574 23:46:41.380195 <5>[ 0.935378] Asymmetric key parser 'x509' registered
10575 23:46:41.389636 <6>[ 0.940536] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10576 23:46:41.393400 <6>[ 0.948151] io scheduler mq-deadline registered
10577 23:46:41.396192 <6>[ 0.952922] io scheduler kyber registered
10578 23:46:41.415727 <6>[ 0.969934] EINJ: ACPI disabled.
10579 23:46:41.448129 <4>[ 0.995848] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10580 23:46:41.457935 <4>[ 1.006469] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10581 23:46:41.472762 <6>[ 1.027267] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10582 23:46:41.480522 <6>[ 1.035182] printk: console [ttyS0] disabled
10583 23:46:41.508784 <6>[ 1.059804] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10584 23:46:41.515383 <6>[ 1.069276] printk: console [ttyS0] enabled
10585 23:46:41.518698 <6>[ 1.069276] printk: console [ttyS0] enabled
10586 23:46:41.525424 <6>[ 1.078174] printk: bootconsole [mtk8250] disabled
10587 23:46:41.528862 <6>[ 1.078174] printk: bootconsole [mtk8250] disabled
10588 23:46:41.535610 <6>[ 1.089184] SuperH (H)SCI(F) driver initialized
10589 23:46:41.538306 <6>[ 1.094454] msm_serial: driver initialized
10590 23:46:41.552260 <6>[ 1.103318] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10591 23:46:41.562462 <6>[ 1.111863] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10592 23:46:41.568704 <6>[ 1.120405] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10593 23:46:41.579109 <6>[ 1.129034] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10594 23:46:41.588721 <6>[ 1.137741] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10595 23:46:41.595159 <6>[ 1.146459] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10596 23:46:41.604991 <6>[ 1.154999] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10597 23:46:41.611791 <6>[ 1.163787] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10598 23:46:41.621962 <6>[ 1.172329] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10599 23:46:41.633342 <6>[ 1.187984] loop: module loaded
10600 23:46:41.639910 <6>[ 1.193917] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10601 23:46:41.662629 <4>[ 1.217268] mtk-pmic-keys: Failed to locate of_node [id: -1]
10602 23:46:41.669611 <6>[ 1.224086] megasas: 07.719.03.00-rc1
10603 23:46:41.679197 <6>[ 1.233681] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10604 23:46:41.691516 <6>[ 1.245841] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10605 23:46:41.708116 <6>[ 1.262484] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10606 23:46:41.764337 <6>[ 1.312333] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10607 23:46:42.952023 <6>[ 2.506816] Freeing initrd memory: 40240K
10608 23:46:42.964213 <6>[ 2.518691] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10609 23:46:42.975365 <6>[ 2.529798] tun: Universal TUN/TAP device driver, 1.6
10610 23:46:42.978845 <6>[ 2.535880] thunder_xcv, ver 1.0
10611 23:46:42.982175 <6>[ 2.539386] thunder_bgx, ver 1.0
10612 23:46:42.985218 <6>[ 2.542879] nicpf, ver 1.0
10613 23:46:42.995875 <6>[ 2.546898] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10614 23:46:42.999034 <6>[ 2.554375] hns3: Copyright (c) 2017 Huawei Corporation.
10615 23:46:43.005680 <6>[ 2.559964] hclge is initializing
10616 23:46:43.009109 <6>[ 2.563548] e1000: Intel(R) PRO/1000 Network Driver
10617 23:46:43.015772 <6>[ 2.568677] e1000: Copyright (c) 1999-2006 Intel Corporation.
10618 23:46:43.018567 <6>[ 2.574690] e1000e: Intel(R) PRO/1000 Network Driver
10619 23:46:43.025335 <6>[ 2.579906] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10620 23:46:43.031939 <6>[ 2.586097] igb: Intel(R) Gigabit Ethernet Network Driver
10621 23:46:43.038620 <6>[ 2.591746] igb: Copyright (c) 2007-2014 Intel Corporation.
10622 23:46:43.045079 <6>[ 2.597582] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10623 23:46:43.051810 <6>[ 2.604100] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10624 23:46:43.055155 <6>[ 2.610585] sky2: driver version 1.30
10625 23:46:43.062125 <6>[ 2.615511] usbcore: registered new device driver r8152-cfgselector
10626 23:46:43.068414 <6>[ 2.622045] usbcore: registered new interface driver r8152
10627 23:46:43.074843 <6>[ 2.627865] VFIO - User Level meta-driver version: 0.3
10628 23:46:43.081385 <6>[ 2.636101] usbcore: registered new interface driver usb-storage
10629 23:46:43.088072 <6>[ 2.642556] usbcore: registered new device driver onboard-usb-hub
10630 23:46:43.097466 <6>[ 2.651705] mt6397-rtc mt6359-rtc: registered as rtc0
10631 23:46:43.107029 <6>[ 2.657167] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-04T23:46:43 UTC (1717544803)
10632 23:46:43.110281 <6>[ 2.666739] i2c_dev: i2c /dev entries driver
10633 23:46:43.127300 <6>[ 2.678425] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10634 23:46:43.133542 <4>[ 2.687155] cpu cpu0: supply cpu not found, using dummy regulator
10635 23:46:43.140081 <4>[ 2.693599] cpu cpu1: supply cpu not found, using dummy regulator
10636 23:46:43.146898 <4>[ 2.700016] cpu cpu2: supply cpu not found, using dummy regulator
10637 23:46:43.153751 <4>[ 2.706416] cpu cpu3: supply cpu not found, using dummy regulator
10638 23:46:43.160117 <4>[ 2.712809] cpu cpu4: supply cpu not found, using dummy regulator
10639 23:46:43.166609 <4>[ 2.719206] cpu cpu5: supply cpu not found, using dummy regulator
10640 23:46:43.173153 <4>[ 2.725620] cpu cpu6: supply cpu not found, using dummy regulator
10641 23:46:43.179968 <4>[ 2.732018] cpu cpu7: supply cpu not found, using dummy regulator
10642 23:46:43.199236 <6>[ 2.753664] cpu cpu0: EM: created perf domain
10643 23:46:43.202396 <6>[ 2.758605] cpu cpu4: EM: created perf domain
10644 23:46:43.209447 <6>[ 2.764230] sdhci: Secure Digital Host Controller Interface driver
10645 23:46:43.216398 <6>[ 2.770664] sdhci: Copyright(c) Pierre Ossman
10646 23:46:43.222717 <6>[ 2.775623] Synopsys Designware Multimedia Card Interface Driver
10647 23:46:43.229458 <6>[ 2.782253] sdhci-pltfm: SDHCI platform and OF driver helper
10648 23:46:43.232914 <6>[ 2.782294] mmc0: CQHCI version 5.10
10649 23:46:43.239109 <6>[ 2.792205] ledtrig-cpu: registered to indicate activity on CPUs
10650 23:46:43.246052 <6>[ 2.799311] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10651 23:46:43.252814 <6>[ 2.806361] usbcore: registered new interface driver usbhid
10652 23:46:43.256216 <6>[ 2.812183] usbhid: USB HID core driver
10653 23:46:43.262757 <6>[ 2.816372] spi_master spi0: will run message pump with realtime priority
10654 23:46:43.308238 <6>[ 2.856308] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10655 23:46:43.326923 <6>[ 2.871607] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10656 23:46:43.334385 <6>[ 2.886396] cros-ec-spi spi0.0: Chrome EC device registered
10657 23:46:43.337265 <6>[ 2.887553] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x16014
10658 23:46:43.348988 <6>[ 2.903454] mmc0: Command Queue Engine enabled
10659 23:46:43.359023 <6>[ 2.905770] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10660 23:46:43.365123 <6>[ 2.908205] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10661 23:46:43.368431 <6>[ 2.918499] NET: Registered PF_PACKET protocol family
10662 23:46:43.375273 <6>[ 2.924588] mmcblk0: mmc0:0001 DA4128 116 GiB
10663 23:46:43.378562 <6>[ 2.929463] 9pnet: Installing 9P2000 support
10664 23:46:43.381880 <5>[ 2.938641] Key type dns_resolver registered
10665 23:46:43.388453 <6>[ 2.940447] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10666 23:46:43.395615 <6>[ 2.943726] registered taskstats version 1
10667 23:46:43.398511 <6>[ 2.950535] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10668 23:46:43.405155 <5>[ 2.953472] Loading compiled-in X.509 certificates
10669 23:46:43.408579 <6>[ 2.959321] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10670 23:46:43.414976 <6>[ 2.969761] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10671 23:46:43.432659 <4>[ 2.980573] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10672 23:46:43.442251 <4>[ 2.991246] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10673 23:46:43.456750 <6>[ 3.011037] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10674 23:46:43.463384 <6>[ 3.017880] xhci-mtk 11200000.usb: xHCI Host Controller
10675 23:46:43.469910 <6>[ 3.023434] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10676 23:46:43.480294 <6>[ 3.031301] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10677 23:46:43.486703 <6>[ 3.040741] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10678 23:46:43.493198 <6>[ 3.046947] xhci-mtk 11200000.usb: xHCI Host Controller
10679 23:46:43.499911 <6>[ 3.052453] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10680 23:46:43.506670 <6>[ 3.060116] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10681 23:46:43.513195 <6>[ 3.067955] hub 1-0:1.0: USB hub found
10682 23:46:43.516591 <6>[ 3.071989] hub 1-0:1.0: 1 port detected
10683 23:46:43.526305 <6>[ 3.076293] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10684 23:46:43.529903 <6>[ 3.085077] hub 2-0:1.0: USB hub found
10685 23:46:43.533349 <6>[ 3.089105] hub 2-0:1.0: 1 port detected
10686 23:46:43.542088 <6>[ 3.096792] mtk-msdc 11f70000.mmc: Got CD GPIO
10687 23:46:43.553922 <6>[ 3.105059] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10688 23:46:43.560228 <6>[ 3.113088] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10689 23:46:43.570187 <4>[ 3.121008] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10690 23:46:43.580203 <6>[ 3.130577] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10691 23:46:43.586992 <6>[ 3.138655] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10692 23:46:43.593743 <6>[ 3.146676] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10693 23:46:43.603194 <6>[ 3.154599] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10694 23:46:43.610291 <6>[ 3.162425] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10695 23:46:43.620251 <6>[ 3.170245] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10696 23:46:43.630088 <6>[ 3.180612] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10697 23:46:43.636789 <6>[ 3.188982] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10698 23:46:43.646483 <6>[ 3.197332] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10699 23:46:43.653260 <6>[ 3.205670] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10700 23:46:43.662935 <6>[ 3.214009] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10701 23:46:43.669835 <6>[ 3.222347] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10702 23:46:43.679696 <6>[ 3.230684] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10703 23:46:43.686547 <6>[ 3.239021] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10704 23:46:43.696261 <6>[ 3.247365] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10705 23:46:43.703004 <6>[ 3.255704] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10706 23:46:43.712978 <6>[ 3.264044] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10707 23:46:43.719420 <6>[ 3.272381] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10708 23:46:43.729654 <6>[ 3.280719] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10709 23:46:43.738976 <6>[ 3.289058] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10710 23:46:43.745840 <6>[ 3.297395] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10711 23:46:43.752414 <6>[ 3.306112] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10712 23:46:43.759067 <6>[ 3.313259] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10713 23:46:43.765917 <6>[ 3.320037] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10714 23:46:43.775607 <6>[ 3.326808] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10715 23:46:43.782218 <6>[ 3.333744] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10716 23:46:43.788865 <6>[ 3.340592] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10717 23:46:43.798497 <6>[ 3.349723] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10718 23:46:43.808738 <6>[ 3.358843] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10719 23:46:43.818291 <6>[ 3.368140] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10720 23:46:43.828289 <6>[ 3.377607] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10721 23:46:43.835246 <6>[ 3.387074] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10722 23:46:43.844578 <6>[ 3.396193] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10723 23:46:43.854879 <6>[ 3.405659] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10724 23:46:43.864778 <6>[ 3.414778] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10725 23:46:43.874471 <6>[ 3.424071] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10726 23:46:43.884575 <6>[ 3.434240] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10727 23:46:43.894860 <6>[ 3.446053] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10728 23:46:43.947355 <6>[ 3.498704] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10729 23:46:44.101919 <6>[ 3.656530] hub 1-1:1.0: USB hub found
10730 23:46:44.105206 <6>[ 3.661008] hub 1-1:1.0: 4 ports detected
10731 23:46:44.115264 <6>[ 3.670043] hub 1-1:1.0: USB hub found
10732 23:46:44.118734 <6>[ 3.674372] hub 1-1:1.0: 4 ports detected
10733 23:46:44.227461 <6>[ 3.779089] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10734 23:46:44.253794 <6>[ 3.808454] hub 2-1:1.0: USB hub found
10735 23:46:44.257178 <6>[ 3.812948] hub 2-1:1.0: 3 ports detected
10736 23:46:44.266180 <6>[ 3.821086] hub 2-1:1.0: USB hub found
10737 23:46:44.269514 <6>[ 3.825549] hub 2-1:1.0: 3 ports detected
10738 23:46:44.443390 <6>[ 3.994754] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10739 23:46:44.575889 <6>[ 4.130274] hub 1-1.4:1.0: USB hub found
10740 23:46:44.578706 <6>[ 4.134913] hub 1-1.4:1.0: 2 ports detected
10741 23:46:44.588318 <6>[ 4.142854] hub 1-1.4:1.0: USB hub found
10742 23:46:44.591647 <6>[ 4.147433] hub 1-1.4:1.0: 2 ports detected
10743 23:46:44.659564 <6>[ 4.210894] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10744 23:46:44.768031 <6>[ 4.319403] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10745 23:46:44.804033 <4>[ 4.355455] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10746 23:46:44.813673 <4>[ 4.364547] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10747 23:46:44.849541 <6>[ 4.404449] r8152 2-1.3:1.0 eth0: v1.12.13
10748 23:46:44.887491 <6>[ 4.438772] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10749 23:46:45.083285 <6>[ 4.634785] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10750 23:46:46.475109 <6>[ 6.029997] r8152 2-1.3:1.0 eth0: carrier on
10751 23:46:48.831565 <5>[ 6.058527] Sending DHCP requests .., OK
10752 23:46:48.838329 <6>[ 8.390980] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.21
10753 23:46:48.841705 <6>[ 8.399277] IP-Config: Complete:
10754 23:46:48.854818 <6>[ 8.402778] device=eth0, hwaddr=00:24:32:30:78:ff, ipaddr=192.168.201.21, mask=255.255.255.0, gw=192.168.201.1
10755 23:46:48.861148 <6>[ 8.413496] host=mt8192-asurada-spherion-r0-cbg-8, domain=lava-rack, nis-domain=(none)
10756 23:46:48.867942 <6>[ 8.422116] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10757 23:46:48.874308 <6>[ 8.422125] nameserver0=192.168.201.1
10758 23:46:48.877983 <6>[ 8.434266] clk: Disabling unused clocks
10759 23:46:48.881440 <6>[ 8.439800] ALSA device list:
10760 23:46:48.887488 <6>[ 8.443080] No soundcards found.
10761 23:46:48.896092 <6>[ 8.451017] Freeing unused kernel memory: 8512K
10762 23:46:48.899350 <6>[ 8.455938] Run /init as init process
10763 23:46:48.930196 <6>[ 8.485281] NET: Registered PF_INET6 protocol family
10764 23:46:48.936909 <6>[ 8.492090] Segment Routing with IPv6
10765 23:46:48.939965 <6>[ 8.496049] In-situ OAM (IOAM) with IPv6
10766 23:46:48.984039 <30>[ 8.512650] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10767 23:46:48.990665 <30>[ 8.545727] systemd[1]: Detected architecture arm64.
10768 23:46:48.990794
10769 23:46:48.997299 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10770 23:46:48.997423
10771 23:46:49.015792 <30>[ 8.570853] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10772 23:46:49.153488 <30>[ 8.705623] systemd[1]: Queued start job for default target graphical.target.
10773 23:46:49.188699 <30>[ 8.740740] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10774 23:46:49.195460 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10775 23:46:49.215450 <30>[ 8.767475] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10776 23:46:49.225366 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10777 23:46:49.244733 <30>[ 8.796554] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10778 23:46:49.254342 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10779 23:46:49.272603 <30>[ 8.824345] systemd[1]: Created slice user.slice - User and Session Slice.
10780 23:46:49.278644 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10781 23:46:49.302897 <30>[ 8.851604] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10782 23:46:49.309925 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10783 23:46:49.330287 <30>[ 8.879004] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10784 23:46:49.337336 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10785 23:46:49.364693 <30>[ 8.906878] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10786 23:46:49.375046 <30>[ 8.926701] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10787 23:46:49.381356 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10788 23:46:49.399056 <30>[ 8.951171] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10789 23:46:49.409199 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10790 23:46:49.427522 <30>[ 8.979238] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10791 23:46:49.437398 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10792 23:46:49.451878 <30>[ 9.007220] systemd[1]: Reached target paths.target - Path Units.
10793 23:46:49.462027 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10794 23:46:49.479293 <30>[ 9.031176] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10795 23:46:49.486027 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10796 23:46:49.499754 <30>[ 9.054740] systemd[1]: Reached target slices.target - Slice Units.
10797 23:46:49.509733 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10798 23:46:49.524141 <30>[ 9.079252] systemd[1]: Reached target swap.target - Swaps.
10799 23:46:49.530317 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10800 23:46:49.551064 <30>[ 9.103159] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10801 23:46:49.560874 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10802 23:46:49.579318 <30>[ 9.131248] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10803 23:46:49.588910 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10804 23:46:49.608745 <30>[ 9.160874] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10805 23:46:49.618759 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10806 23:46:49.635136 <30>[ 9.187359] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10807 23:46:49.645348 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10808 23:46:49.664210 <30>[ 9.216055] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10809 23:46:49.670646 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10810 23:46:49.691662 <30>[ 9.243514] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10811 23:46:49.701547 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10812 23:46:49.720205 <30>[ 9.272138] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10813 23:46:49.730140 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10814 23:46:49.748043 <30>[ 9.299919] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10815 23:46:49.757740 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10816 23:46:49.815081 <30>[ 9.366943] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10817 23:46:49.821310 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10818 23:46:49.842700 <30>[ 9.394885] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10819 23:46:49.849314 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10820 23:46:49.871138 <30>[ 9.423068] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10821 23:46:49.877883 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10822 23:46:49.901823 <30>[ 9.447146] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10823 23:46:49.947025 <30>[ 9.499036] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10824 23:46:49.956868 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10825 23:46:49.980009 <30>[ 9.531927] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10826 23:46:49.986318 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10827 23:46:50.011735 <30>[ 9.564010] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10828 23:46:50.025313 Starting [0;1;39mmodpr<6>[ 9.575211] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10829 23:46:50.028494 obe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10830 23:46:50.083124 <30>[ 9.635226] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10831 23:46:50.089747 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10832 23:46:50.115789 <30>[ 9.667646] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10833 23:46:50.125556 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10834 23:46:50.148039 <30>[ 9.699950] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10835 23:46:50.154507 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10836 23:46:50.222924 <30>[ 9.775183] systemd[1]: Starting systemd-journald.service - Journal Service...
10837 23:46:50.229895 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10838 23:46:50.250206 <30>[ 9.802152] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10839 23:46:50.256649 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10840 23:46:50.284663 <30>[ 9.833407] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10841 23:46:50.291053 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10842 23:46:50.319047 <30>[ 9.871148] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10843 23:46:50.329155 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10844 23:46:50.351719 <30>[ 9.903894] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10845 23:46:50.358577 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10846 23:46:50.387028 <30>[ 9.939144] systemd[1]: Started systemd-journald.service - Journal Service.
10847 23:46:50.393712 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10848 23:46:50.412903 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10849 23:46:50.431679 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10850 23:46:50.451666 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10851 23:46:50.472203 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10852 23:46:50.496386 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10853 23:46:50.517198 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10854 23:46:50.537612 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10855 23:46:50.557732 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10856 23:46:50.577564 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10857 23:46:50.600410 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10858 23:46:50.625584 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10859 23:46:50.646106 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10860 23:46:50.653132 See 'systemctl status systemd-remount-fs.service' for details.
10861 23:46:50.672723 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10862 23:46:50.693736 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10863 23:46:50.751811 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10864 23:46:50.777026 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10865 23:46:50.794524 <46>[ 10.346583] systemd-journald[180]: Received client request to flush runtime journal.
10866 23:46:50.840397 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10867 23:46:50.864892 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10868 23:46:50.887163 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10869 23:46:50.908575 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10870 23:46:50.928835 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10871 23:46:50.948962 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10872 23:46:50.968041 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10873 23:46:50.988289 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10874 23:46:51.039988 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10875 23:46:51.067660 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10876 23:46:51.087747 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10877 23:46:51.107431 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10878 23:46:51.155485 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10879 23:46:51.180838 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10880 23:46:51.202805 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10881 23:46:51.255158 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10882 23:46:51.282442 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10883 23:46:51.305054 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10884 23:46:51.358091 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10885 23:46:51.395247 <46>[ 10.950760] systemd-journald[180]: Time jumped backwards, rotating.
10886 23:46:51.405937 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10887 23:46:51.436699 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10888 23:46:51.535783 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10889 23:46:51.556594 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10890 23:46:51.586167 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Se<3>[ 11.138197] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10891 23:46:51.586330 t.
10892 23:46:51.596076 <3>[ 11.146797] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10893 23:46:51.602286 <3>[ 11.155676] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10894 23:46:51.613052 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10895 23:46:51.623059 <3>[ 11.174387] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10896 23:46:51.629898 <3>[ 11.182864] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10897 23:46:51.639619 <3>[ 11.190975] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10898 23:46:51.646036 <6>[ 11.197827] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10899 23:46:51.652945 <3>[ 11.199422] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10900 23:46:51.662669 <6>[ 11.201610] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10901 23:46:51.669156 <6>[ 11.208425] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10902 23:46:51.679486 <3>[ 11.214781] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10903 23:46:51.682260 <6>[ 11.216311] mc: Linux media interface: v0.10
10904 23:46:51.689035 <6>[ 11.218160] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10905 23:46:51.699243 <6>[ 11.222457] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10906 23:46:51.706396 <3>[ 11.223323] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10907 23:46:51.713440 <6>[ 11.230964] remoteproc remoteproc0: scp is available
10908 23:46:51.719684 <4>[ 11.241254] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10909 23:46:51.726768 <6>[ 11.243565] remoteproc remoteproc0: powering up scp
10910 23:46:51.732996 <4>[ 11.245752] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10911 23:46:51.739681 <4>[ 11.245752] Fallback method does not support PEC.
10912 23:46:51.746360 <3>[ 11.246061] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10913 23:46:51.757324 <3>[ 11.246097] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10914 23:46:51.764477 <3>[ 11.246107] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10915 23:46:51.771057 <3>[ 11.247993] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10916 23:46:51.780654 <3>[ 11.248052] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10917 23:46:51.787332 <3>[ 11.248063] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10918 23:46:51.794737 <3>[ 11.248081] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10919 23:46:51.804608 <3>[ 11.248094] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10920 23:46:51.810790 <3>[ 11.248215] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10921 23:46:51.821224 <4>[ 11.251379] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10922 23:46:51.827966 <6>[ 11.260790] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10923 23:46:51.835113 <3>[ 11.268554] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10924 23:46:51.841904 <6>[ 11.275091] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10925 23:46:51.851611 <3>[ 11.317145] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10926 23:46:51.861564 <3>[ 11.319629] power_supply sbs-5-000b: driver failed to report `capacity_error_margin' property: -6
10927 23:46:51.871218 <6>[ 11.328772] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10928 23:46:51.878007 <3>[ 11.357811] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10929 23:46:51.884435 <6>[ 11.359848] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10930 23:46:51.891073 <6>[ 11.359853] pci_bus 0000:00: root bus resource [bus 00-ff]
10931 23:46:51.898130 <6>[ 11.359857] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10932 23:46:51.907639 <6>[ 11.359859] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10933 23:46:51.914367 <6>[ 11.359885] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10934 23:46:51.920946 <6>[ 11.359898] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10935 23:46:51.927789 <6>[ 11.359962] pci 0000:00:00.0: supports D1 D2
10936 23:46:51.934235 <6>[ 11.359964] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10937 23:46:51.940915 <6>[ 11.360834] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10938 23:46:51.947537 <6>[ 11.360914] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10939 23:46:51.957289 <6>[ 11.360939] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10940 23:46:51.963953 <6>[ 11.360954] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10941 23:46:51.970745 <6>[ 11.360969] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10942 23:46:51.973831 <6>[ 11.361071] pci 0000:01:00.0: supports D1 D2
10943 23:46:51.983608 <6>[ 11.361072] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10944 23:46:51.990519 <6>[ 11.364972] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10945 23:46:52.000430 <6>[ 11.373889] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10946 23:46:52.007156 <6>[ 11.374690] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10947 23:46:52.016794 <6>[ 11.374722] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10948 23:46:52.023940 <6>[ 11.374731] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10949 23:46:52.030326 <6>[ 11.374754] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10950 23:46:52.041181 <6>[ 11.374773] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10951 23:46:52.047343 <6>[ 11.374790] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10952 23:46:52.054139 <6>[ 11.374809] pci 0000:00:00.0: PCI bridge to [bus 01]
10953 23:46:52.060678 <6>[ 11.374821] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10954 23:46:52.067414 <6>[ 11.375032] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10955 23:46:52.074150 <6>[ 11.376229] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10956 23:46:52.081102 <6>[ 11.380224] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10957 23:46:52.087450 <3>[ 11.393036] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10958 23:46:52.094167 <6>[ 11.403498] videodev: Linux video capture interface: v2.00
10959 23:46:52.101189 <5>[ 11.441889] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10960 23:46:52.107609 <6>[ 11.447463] Bluetooth: Core ver 2.22
10961 23:46:52.114327 <6>[ 11.452524] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10962 23:46:52.121173 <6>[ 11.452526] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10963 23:46:52.127557 <6>[ 11.459646] NET: Registered PF_BLUETOOTH protocol family
10964 23:46:52.134300 <6>[ 11.460871] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10965 23:46:52.144021 <6>[ 11.463156] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10966 23:46:52.150796 <6>[ 11.469471] remoteproc remoteproc0: remote processor scp is now up
10967 23:46:52.157079 <5>[ 11.470491] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10968 23:46:52.163749 <5>[ 11.470732] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10969 23:46:52.173739 <4>[ 11.470791] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10970 23:46:52.180754 <6>[ 11.470796] cfg80211: failed to load regulatory.db
10971 23:46:52.186982 <6>[ 11.475723] Bluetooth: HCI device and connection manager initialized
10972 23:46:52.193731 <6>[ 11.510285] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10973 23:46:52.196886 <6>[ 11.516570] Bluetooth: HCI socket layer initialized
10974 23:46:52.204163 <6>[ 11.516581] Bluetooth: L2CAP socket layer initialized
10975 23:46:52.214239 <6>[ 11.525351] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10976 23:46:52.221087 <6>[ 11.531544] Bluetooth: SCO socket layer initialized
10977 23:46:52.227822 <6>[ 11.544932] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10978 23:46:52.234460 <6>[ 11.552590] usbcore: registered new interface driver uvcvideo
10979 23:46:52.237976 <6>[ 11.569594] usbcore: registered new interface driver btusb
10980 23:46:52.251000 <4>[ 11.570502] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10981 23:46:52.253849 <3>[ 11.570525] Bluetooth: hci0: Failed to load firmware file (-2)
10982 23:46:52.260530 <3>[ 11.570529] Bluetooth: hci0: Failed to set up firmware (-2)
10983 23:46:52.270683 <4>[ 11.570534] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10984 23:46:52.280735 <6>[ 11.572475] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10985 23:46:52.286933 <6>[ 11.572583] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10986 23:46:52.290790 <6>[ 11.590510] mt7921e 0000:01:00.0: ASIC revision: 79610010
10987 23:46:52.300539 <3>[ 11.595584] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10988 23:46:52.310273 <3>[ 11.613969] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10989 23:46:52.316832 <3>[ 11.622677] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10990 23:46:52.326719 <3>[ 11.662486] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10991 23:46:52.333241 <6>[ 11.741276] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10992 23:46:52.336507 <6>[ 11.741276]
10993 23:46:52.346707 <3>[ 11.770901] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10994 23:46:52.353140 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10995 23:46:52.371733 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10996 23:46:52.391355 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10997 23:46:52.443794 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10998 23:46:52.462864 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10999 23:46:52.482772 <6>[ 12.034851] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
11000 23:46:52.488991 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11001 23:46:52.514568 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11002 23:46:52.531503 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11003 23:46:52.564197 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11004 23:46:52.617735 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11005 23:46:52.638884 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11006 23:46:52.659296 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11007 23:46:52.676200 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11008 23:46:52.695477 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11009 23:46:52.740589 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11010 23:46:52.764850 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11011 23:46:52.788539 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11012 23:46:52.809360 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11013 23:46:52.859819 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11014 23:46:52.878176 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11015 23:46:52.895098 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11016 23:46:52.910728 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11017 23:46:52.930911 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11018 23:46:53.004285 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11019 23:46:53.029497 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11020 23:46:53.053032 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11021 23:46:53.093073 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11022 23:46:53.136263
11023 23:46:53.139573 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11024 23:46:53.139752
11025 23:46:53.142843 debian-bookworm-arm64 login: root (automatic login)
11026 23:46:53.143012
11027 23:46:53.158246 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Tue Jun 4 23:28:43 UTC 2024 aarch64
11028 23:46:53.158446
11029 23:46:53.165341 The programs included with the Debian GNU/Linux system are free software;
11030 23:46:53.171513 the exact distribution terms for each program are described in the
11031 23:46:53.174900 individual files in /usr/share/doc/*/copyright.
11032 23:46:53.175065
11033 23:46:53.181510 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11034 23:46:53.184788 permitted by applicable law.
11035 23:46:53.185354 Matched prompt #10: / #
11037 23:46:53.185586 Setting prompt string to ['/ #']
11038 23:46:53.185685 end: 2.2.5.1 login-action (duration 00:00:13) [common]
11040 23:46:53.185895 end: 2.2.5 auto-login-action (duration 00:00:14) [common]
11041 23:46:53.185984 start: 2.2.6 expect-shell-connection (timeout 00:03:01) [common]
11042 23:46:53.186059 Setting prompt string to ['/ #']
11043 23:46:53.186130 Forcing a shell prompt, looking for ['/ #']
11045 23:46:53.236342 / #
11046 23:46:53.236529 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11047 23:46:53.236625 Waiting using forced prompt support (timeout 00:02:30)
11048 23:46:53.241371
11049 23:46:53.241686 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11050 23:46:53.241801 start: 2.2.7 export-device-env (timeout 00:03:01) [common]
11051 23:46:53.241906 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11052 23:46:53.242016 end: 2.2 depthcharge-retry (duration 00:01:59) [common]
11053 23:46:53.242103 end: 2 depthcharge-action (duration 00:01:59) [common]
11054 23:46:53.242191 start: 3 lava-test-retry (timeout 00:07:38) [common]
11055 23:46:53.242276 start: 3.1 lava-test-shell (timeout 00:07:38) [common]
11056 23:46:53.242355 Using namespace: common
11058 23:46:53.342679 / # #
11059 23:46:53.342902 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11060 23:46:53.348163 #
11061 23:46:53.348505 Using /lava-14172972
11063 23:46:53.448980 / # export SHELL=/bin/sh
11064 23:46:53.449185 <6>[ 12.918777] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11065 23:46:53.454523 export SHELL=/bin/sh
11067 23:46:53.555073 / # . /lava-14172972/environment
11068 23:46:53.559762 . /lava-14172972/environment
11070 23:46:53.660360 / # /lava-14172972/bin/lava-test-runner /lava-14172972/0
11071 23:46:53.660620 Test shell timeout: 10s (minimum of the action and connection timeout)
11072 23:46:53.666008 /lava-14172972/bin/lava-test-runner /lava-14172972/0
11073 23:46:53.688236 + export TESTRUN_ID=0_v4l2-compliance-uvc
11074 23:46:53.691236 + cd /lava-14172972/0/tests/0_v4l2-compliance-uvc
11075 23:46:53.691359 + cat uuid
11076 23:46:53.694912 + UUID=14172972_1.5.2.3.1
11077 23:46:53.694999 + set +x
11078 23:46:53.701545 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-uvc 14172972_1.5.2.3.1>
11079 23:46:53.701915 Received signal: <STARTRUN> 0_v4l2-compliance-uvc 14172972_1.5.2.3.1
11080 23:46:53.702048 Starting test lava.0_v4l2-compliance-uvc (14172972_1.5.2.3.1)
11081 23:46:53.702192 Skipping test definition patterns.
11082 23:46:53.704797 + /usr/bin/v4l2-parser.sh -d uvcvideo
11083 23:46:53.711458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
11084 23:46:53.711598 device: /dev/video0
11085 23:46:53.711872 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
11087 23:47:00.201224 v4l2-compliance 1.27.0-1, 64 bits, 64-bit time_t
11088 23:47:00.213628 v4l2-compliance SHA: a18611d8960f 2024-03-08 13:09:54
11089 23:47:00.221492
11090 23:47:00.235833 Compliance test for uvcvideo device /dev/video0:
11091 23:47:00.247778
11092 23:47:00.259187 Driver Info:
11093 23:47:00.269747 Driver name : uvcvideo
11094 23:47:00.284306 Card type : HD User Facing: HD User Facing
11095 23:47:00.295285 Bus info : usb-11200000.usb-1.4.1
11096 23:47:00.302016 Driver version : 6.1.92
11097 23:47:00.313268 Capabilities : 0x84a00001
11098 23:47:00.325066 Metadata Capture
11099 23:47:00.334306 Streaming
11100 23:47:00.348458 Extended Pix Format
11101 23:47:00.361206 Device Capabilities
11102 23:47:00.374177 Device Caps : 0x04200001
11103 23:47:00.388741 Streaming
11104 23:47:00.399087 Extended Pix Format
11105 23:47:00.410135 Media Driver Info:
11106 23:47:00.420751 Driver name : uvcvideo
11107 23:47:00.435829 Model : HD User Facing: HD User Facing
11108 23:47:00.442903 Serial : 200901010001
11109 23:47:00.459061 Bus info : usb-11200000.usb-1.4.1
11110 23:47:00.465950 Media version : 6.1.92
11111 23:47:00.479277 Hardware revision: 0x00009758 (38744)
11112 23:47:00.487427 Driver version : 6.1.92
11113 23:47:00.500803 Interface Info:
11114 23:47:00.516804 <LAVA_SIGNAL_TESTSET START Interface-Info>
11115 23:47:00.516984 ID : 0x03000002
11116 23:47:00.517283 Received signal: <TESTSET> START Interface-Info
11117 23:47:00.517373 Starting test_set Interface-Info
11118 23:47:00.529004 Type : V4L Video
11119 23:47:00.538174 Entity Info:
11120 23:47:00.544714 <LAVA_SIGNAL_TESTSET STOP>
11121 23:47:00.545078 Received signal: <TESTSET> STOP
11122 23:47:00.545168 Closing test_set Interface-Info
11123 23:47:00.554944 <LAVA_SIGNAL_TESTSET START Entity-Info>
11124 23:47:00.555277 Received signal: <TESTSET> START Entity-Info
11125 23:47:00.555382 Starting test_set Entity-Info
11126 23:47:00.558234 ID : 0x00000001 (1)
11127 23:47:00.572140 Name : HD User Facing: HD User Facing
11128 23:47:00.580161 Function : V4L2 I/O
11129 23:47:00.590335 Flags : default
11130 23:47:00.601130 Pad 0x01000007 : 0: Sink
11131 23:47:00.621860 Link 0x02000013: from remote pad 0x100000a of entity 'Realtek Extended Controls Unit' (Video Pixel Formatter): Data, Enabled, Immutable
11132 23:47:00.622136
11133 23:47:00.633513 Required ioctls:
11134 23:47:00.644891 <LAVA_SIGNAL_TESTSET STOP>
11135 23:47:00.645227 Received signal: <TESTSET> STOP
11136 23:47:00.645307 Closing test_set Entity-Info
11137 23:47:00.654509 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11138 23:47:00.654891 Received signal: <TESTSET> START Required-ioctls
11139 23:47:00.655018 Starting test_set Required-ioctls
11140 23:47:00.657882 test MC information (see 'Media Driver Info' above): OK
11141 23:47:00.687879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass>
11142 23:47:00.688246 Received signal: <TESTCASE> TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass
11144 23:47:00.691314 test VIDIOC_QUERYCAP: OK
11145 23:47:00.709504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11146 23:47:00.709900 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11148 23:47:00.712712 test invalid ioctls: OK
11149 23:47:00.733620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11150 23:47:00.733812
11151 23:47:00.734113 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11153 23:47:00.744734 Allow for multiple opens:
11154 23:47:00.752124 <LAVA_SIGNAL_TESTSET STOP>
11155 23:47:00.752511 Received signal: <TESTSET> STOP
11156 23:47:00.752648 Closing test_set Required-ioctls
11157 23:47:00.761711 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11158 23:47:00.762018 Received signal: <TESTSET> START Allow-for-multiple-opens
11159 23:47:00.762098 Starting test_set Allow-for-multiple-opens
11160 23:47:00.764946 test second /dev/video0 open: OK
11161 23:47:00.785204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video0-open RESULT=pass>
11162 23:47:00.785598 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video0-open RESULT=pass
11164 23:47:00.788448 test VIDIOC_QUERYCAP: OK
11165 23:47:00.814652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11166 23:47:00.815045 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11168 23:47:00.817886 test VIDIOC_G/S_PRIORITY: OK
11169 23:47:00.839758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11170 23:47:00.840152 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11172 23:47:00.843541 test for unlimited opens: OK
11173 23:47:00.868352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11174 23:47:00.868574
11175 23:47:00.868895 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11177 23:47:00.880439 Debug ioctls:
11178 23:47:00.890244 <LAVA_SIGNAL_TESTSET STOP>
11179 23:47:00.890623 Received signal: <TESTSET> STOP
11180 23:47:00.890747 Closing test_set Allow-for-multiple-opens
11181 23:47:00.901542 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11182 23:47:00.901920 Received signal: <TESTSET> START Debug-ioctls
11183 23:47:00.902051 Starting test_set Debug-ioctls
11184 23:47:00.904938 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11185 23:47:00.924804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11186 23:47:00.925197 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11188 23:47:00.931207 test VIDIOC_LOG_STATUS: OK (Not Supported)
11189 23:47:00.949333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11190 23:47:00.949470
11191 23:47:00.949714 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11193 23:47:00.960279 Input ioctls:
11194 23:47:00.966844 <LAVA_SIGNAL_TESTSET STOP>
11195 23:47:00.967195 Received signal: <TESTSET> STOP
11196 23:47:00.967313 Closing test_set Debug-ioctls
11197 23:47:00.976133 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11198 23:47:00.976463 Received signal: <TESTSET> START Input-ioctls
11199 23:47:00.976580 Starting test_set Input-ioctls
11200 23:47:00.979544 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11201 23:47:01.004524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11202 23:47:01.004866 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11204 23:47:01.007869 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11205 23:47:01.027788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11206 23:47:01.028130 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11208 23:47:01.034280 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11209 23:47:01.056063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11210 23:47:01.056462 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11212 23:47:01.062604 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11213 23:47:01.081024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11214 23:47:01.081428 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11216 23:47:01.084256 test VIDIOC_G/S/ENUMINPUT: OK
11217 23:47:01.112120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11218 23:47:01.112453 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11220 23:47:01.115617 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11221 23:47:01.137246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11222 23:47:01.137563 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11224 23:47:01.140251 Inputs: 1 Audio Inputs: 0 Tuners: 0
11225 23:47:01.148589
11226 23:47:01.168477 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11227 23:47:01.189283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11228 23:47:01.189714 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11230 23:47:01.195697 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11231 23:47:01.213164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11232 23:47:01.213573 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11234 23:47:01.219654 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11235 23:47:01.237547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11236 23:47:01.237869 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11238 23:47:01.243874 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11239 23:47:01.263453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11240 23:47:01.263824 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11242 23:47:01.269797 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11243 23:47:01.290989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11244 23:47:01.291145
11245 23:47:01.291394 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11247 23:47:01.310470 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11248 23:47:01.331397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11249 23:47:01.331727 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11251 23:47:01.337767 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11252 23:47:01.359589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11253 23:47:01.359917 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11255 23:47:01.362682 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11256 23:47:01.383773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11257 23:47:01.384103 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11259 23:47:01.387071 test VIDIOC_G/S_EDID: OK (Not Supported)
11260 23:47:01.407093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11261 23:47:01.407267
11262 23:47:01.407554 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11264 23:47:01.418323 Control ioctls (Input 0):
11265 23:47:01.424527 <LAVA_SIGNAL_TESTSET STOP>
11266 23:47:01.424894 Received signal: <TESTSET> STOP
11267 23:47:01.425024 Closing test_set Input-ioctls
11268 23:47:01.433694 <LAVA_SIGNAL_TESTSET START Control-ioctls-Input-0>
11269 23:47:01.434059 Received signal: <TESTSET> START Control-ioctls-Input-0
11270 23:47:01.434186 Starting test_set Control-ioctls-Input-0
11271 23:47:01.436840 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11272 23:47:01.459996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11273 23:47:01.460148 test VIDIOC_QUERYCTRL: OK
11274 23:47:01.460398 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11276 23:47:01.480913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11277 23:47:01.481225 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11279 23:47:01.484407 test VIDIOC_G/S_CTRL: OK
11280 23:47:01.503918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11281 23:47:01.504239 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11283 23:47:01.507274 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11284 23:47:01.530372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11285 23:47:01.530680 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11287 23:47:01.537126 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
11288 23:47:01.563660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass>
11289 23:47:01.563975 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass
11291 23:47:01.566382 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11292 23:47:01.587865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11293 23:47:01.588193 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11295 23:47:01.591272 Standard Controls: 16 Private Controls: 0
11296 23:47:01.599234
11297 23:47:01.613210 Format ioctls (Input 0):
11298 23:47:01.621151 <LAVA_SIGNAL_TESTSET STOP>
11299 23:47:01.621532 Received signal: <TESTSET> STOP
11300 23:47:01.621656 Closing test_set Control-ioctls-Input-0
11301 23:47:01.630248 <LAVA_SIGNAL_TESTSET START Format-ioctls-Input-0>
11302 23:47:01.630615 Received signal: <TESTSET> START Format-ioctls-Input-0
11303 23:47:01.630752 Starting test_set Format-ioctls-Input-0
11304 23:47:01.633725 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11305 23:47:01.659587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11306 23:47:01.659962 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11308 23:47:01.662964 test VIDIOC_G/S_PARM: OK
11309 23:47:01.682244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11310 23:47:01.682619 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11312 23:47:01.685516 test VIDIOC_G_FBUF: OK (Not Supported)
11313 23:47:01.707395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11314 23:47:01.707762 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11316 23:47:01.710101 test VIDIOC_G_FMT: OK
11317 23:47:01.731877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11318 23:47:01.732236 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11320 23:47:01.735132 test VIDIOC_TRY_FMT: OK
11321 23:47:01.754929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11322 23:47:01.755307 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11324 23:47:01.761685 warn: v4l2-test-formats.cpp(1046): Could not set fmt2
11325 23:47:01.767351 test VIDIOC_S_FMT: OK
11326 23:47:01.793440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass>
11327 23:47:01.793811 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass
11329 23:47:01.796730 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11330 23:47:01.816199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11331 23:47:01.816579 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11333 23:47:01.819366 test Cropping: OK (Not Supported)
11334 23:47:01.835678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11335 23:47:01.836045 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11337 23:47:01.839073 test Composing: OK (Not Supported)
11338 23:47:01.863394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11339 23:47:01.863770 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11341 23:47:01.866079 test Scaling: OK (Not Supported)
11342 23:47:01.886641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11343 23:47:01.886828
11344 23:47:01.887112 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11346 23:47:01.897812 Codec ioctls (Input 0):
11347 23:47:01.906218 <LAVA_SIGNAL_TESTSET STOP>
11348 23:47:01.906573 Received signal: <TESTSET> STOP
11349 23:47:01.906683 Closing test_set Format-ioctls-Input-0
11350 23:47:01.917072 <LAVA_SIGNAL_TESTSET START Codec-ioctls-Input-0>
11351 23:47:01.917427 Received signal: <TESTSET> START Codec-ioctls-Input-0
11352 23:47:01.917539 Starting test_set Codec-ioctls-Input-0
11353 23:47:01.920256 test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
11354 23:47:01.941896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11355 23:47:01.942267 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11357 23:47:01.948671 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11358 23:47:01.972218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11359 23:47:01.972603 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11361 23:47:01.978752 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11362 23:47:01.999252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11363 23:47:01.999442
11364 23:47:01.999729 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11366 23:47:02.015386 Buffer ioctls (Input 0):
11367 23:47:02.021908 <LAVA_SIGNAL_TESTSET STOP>
11368 23:47:02.022258 Received signal: <TESTSET> STOP
11369 23:47:02.022374 Closing test_set Codec-ioctls-Input-0
11370 23:47:02.031268 <LAVA_SIGNAL_TESTSET START Buffer-ioctls-Input-0>
11371 23:47:02.031606 Received signal: <TESTSET> START Buffer-ioctls-Input-0
11372 23:47:02.031716 Starting test_set Buffer-ioctls-Input-0
11373 23:47:02.034233 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11374 23:47:02.059581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11375 23:47:02.059939 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11377 23:47:02.063167 test CREATE_BUFS maximum buffers: OK
11378 23:47:02.081453 Received signal: <TESTCASE> TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass
11380 23:47:02.084732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass>
11381 23:47:02.084856 test VIDIOC_EXPBUF: OK
11382 23:47:02.107589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11383 23:47:02.107945 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11385 23:47:02.111153 test Requests: OK (Not Supported)
11386 23:47:02.132278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11387 23:47:02.132469
11388 23:47:02.132768 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11390 23:47:02.143500 Test input 0:
11391 23:47:02.153561
11392 23:47:02.164406 Streaming ioctls:
11393 23:47:02.176384 <LAVA_SIGNAL_TESTSET STOP>
11394 23:47:02.176766 Received signal: <TESTSET> STOP
11395 23:47:02.176879 Closing test_set Buffer-ioctls-Input-0
11396 23:47:02.186604 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11397 23:47:02.186960 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11398 23:47:02.187069 Starting test_set Streaming-ioctls_Test-input-0
11399 23:47:02.189706 test read/write: OK (Not Supported)
11400 23:47:02.210942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11401 23:47:02.211309 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11403 23:47:02.213706 test blocking wait: OK
11404 23:47:02.234928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=pass>
11405 23:47:02.235277 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=pass
11407 23:47:02.241213 fail: v4l2-test-buffers.cpp(1377): node->streamon(q.g_type()) != EINVAL
11408 23:47:02.246898 test MMAP (no poll): FAIL
11409 23:47:02.272757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-no-poll RESULT=fail>
11410 23:47:02.273123 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-no-poll RESULT=fail
11412 23:47:02.279452 fail: v4l2-test-buffers.cpp(1377): node->streamon(q.g_type()) != EINVAL
11413 23:47:02.283193 test MMAP (select): FAIL
11414 23:47:02.307452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11415 23:47:02.307827 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11417 23:47:02.313763 fail: v4l2-test-buffers.cpp(1377): node->streamon(q.g_type()) != EINVAL
11418 23:47:02.318196 test MMAP (epoll): FAIL
11419 23:47:02.343120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11420 23:47:02.343311
11421 23:47:02.343600 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11423 23:47:02.356098
11424 23:47:02.545931
11425 23:47:02.554070 test USERPTR (no poll): OK
11426 23:47:02.583325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-no-poll RESULT=pass>
11427 23:47:02.583504
11428 23:47:02.583788 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-no-poll RESULT=pass
11430 23:47:02.599947
11431 23:47:02.783626
11432 23:47:02.790539 test USERPTR (select): OK
11433 23:47:02.820283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=pass>
11434 23:47:02.820661 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=pass
11436 23:47:02.827022 test DMABUF: Cannot test, specify --expbuf-device
11437 23:47:02.830427
11438 23:47:02.847723 Total for uvcvideo device /dev/video0: 54, Succeeded: 51, Failed: 3, Warnings: 3
11439 23:47:02.856372 <LAVA_TEST_RUNNER EXIT>
11440 23:47:02.856725 ok: lava_test_shell seems to have completed
11441 23:47:02.856818 Marking unfinished test run as failed
11443 23:47:02.857843 CREATE_BUFS-maximum-buffers:
result: pass
set: Buffer-ioctls-Input-0
Composing:
result: pass
set: Format-ioctls-Input-0
Cropping:
result: pass
set: Format-ioctls-Input-0
MC-information-see-Media-Driver-Info-above:
result: pass
set: Required-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-no-poll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls-Input-0
Scaling:
result: pass
set: Format-ioctls-Input-0
USERPTR-no-poll:
result: pass
set: Streaming-ioctls_Test-input-0
USERPTR-select:
result: pass
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls-Input-0
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls-Input-0
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls-Input-0
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_S_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: pass
set: Control-ioctls-Input-0
blocking-wait:
result: pass
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video0-open:
result: pass
set: Allow-for-multiple-opens
11444 23:47:02.858030 end: 3.1 lava-test-shell (duration 00:00:10) [common]
11445 23:47:02.858168 end: 3 lava-test-retry (duration 00:00:10) [common]
11446 23:47:02.858300 start: 4 finalize (timeout 00:07:28) [common]
11447 23:47:02.858438 start: 4.1 power-off (timeout 00:00:30) [common]
11448 23:47:02.858736 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-8', '--port=1', '--command=off']
11449 23:47:02.942046 >> Command sent successfully.
11450 23:47:02.944993 Returned 0 in 0 seconds
11451 23:47:03.045464 end: 4.1 power-off (duration 00:00:00) [common]
11453 23:47:03.045962 start: 4.2 read-feedback (timeout 00:07:28) [common]
11454 23:47:03.046343 Listened to connection for namespace 'common' for up to 1s
11455 23:47:04.047231 Finalising connection for namespace 'common'
11456 23:47:04.047489 Disconnecting from shell: Finalise
11457 23:47:04.047621 / #
11458 23:47:04.148016 end: 4.2 read-feedback (duration 00:00:01) [common]
11459 23:47:04.148272 end: 4 finalize (duration 00:00:01) [common]
11460 23:47:04.148448 Cleaning after the job
11461 23:47:04.148624 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14172972/tftp-deploy-6oanwx39/ramdisk
11462 23:47:04.154852 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14172972/tftp-deploy-6oanwx39/kernel
11463 23:47:04.172176 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14172972/tftp-deploy-6oanwx39/dtb
11464 23:47:04.172460 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14172972/tftp-deploy-6oanwx39/modules
11465 23:47:04.180069 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14172972
11466 23:47:04.258473 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14172972
11467 23:47:04.258668 Job finished correctly