Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 22
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
1 00:21:06.516584 lava-dispatcher, installed at version: 2024.03
2 00:21:06.516807 start: 0 validate
3 00:21:06.516947 Start time: 2024-06-21 00:21:06.516940+00:00 (UTC)
4 00:21:06.517076 Using caching service: 'http://localhost/cache/?uri=%s'
5 00:21:06.517214 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 00:21:06.775042 Using caching service: 'http://localhost/cache/?uri=%s'
7 00:21:06.775305 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.94-cip23%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 00:21:33.776732 Using caching service: 'http://localhost/cache/?uri=%s'
9 00:21:33.777416 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.94-cip23%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 00:21:34.037006 Using caching service: 'http://localhost/cache/?uri=%s'
11 00:21:34.037235 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.94-cip23%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 00:21:35.797376 validate duration: 29.28
14 00:21:35.798787 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 00:21:35.799347 start: 1.1 download-retry (timeout 00:10:00) [common]
16 00:21:35.799829 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 00:21:35.800417 Not decompressing ramdisk as can be used compressed.
18 00:21:35.800850 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 00:21:35.801195 saving as /var/lib/lava/dispatcher/tmp/14479190/tftp-deploy-i9ftv1sc/ramdisk/rootfs.cpio.gz
20 00:21:35.801571 total size: 8181887 (7 MB)
21 00:21:36.064001 progress 0 % (0 MB)
22 00:21:36.069051 progress 5 % (0 MB)
23 00:21:36.072871 progress 10 % (0 MB)
24 00:21:36.076586 progress 15 % (1 MB)
25 00:21:36.079830 progress 20 % (1 MB)
26 00:21:36.082929 progress 25 % (1 MB)
27 00:21:36.085635 progress 30 % (2 MB)
28 00:21:36.088393 progress 35 % (2 MB)
29 00:21:36.090771 progress 40 % (3 MB)
30 00:21:36.093248 progress 45 % (3 MB)
31 00:21:36.095439 progress 50 % (3 MB)
32 00:21:36.097760 progress 55 % (4 MB)
33 00:21:36.100002 progress 60 % (4 MB)
34 00:21:36.102407 progress 65 % (5 MB)
35 00:21:36.104675 progress 70 % (5 MB)
36 00:21:36.107169 progress 75 % (5 MB)
37 00:21:36.109311 progress 80 % (6 MB)
38 00:21:36.111496 progress 85 % (6 MB)
39 00:21:36.113564 progress 90 % (7 MB)
40 00:21:36.115774 progress 95 % (7 MB)
41 00:21:36.117818 progress 100 % (7 MB)
42 00:21:36.118014 7 MB downloaded in 0.32 s (24.66 MB/s)
43 00:21:36.118167 end: 1.1.1 http-download (duration 00:00:00) [common]
45 00:21:36.118404 end: 1.1 download-retry (duration 00:00:00) [common]
46 00:21:36.118488 start: 1.2 download-retry (timeout 00:10:00) [common]
47 00:21:36.118584 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 00:21:36.118720 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.94-cip23/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 00:21:36.118790 saving as /var/lib/lava/dispatcher/tmp/14479190/tftp-deploy-i9ftv1sc/kernel/Image
50 00:21:36.118849 total size: 54813184 (52 MB)
51 00:21:36.118909 No compression specified
52 00:21:36.119974 progress 0 % (0 MB)
53 00:21:36.134115 progress 5 % (2 MB)
54 00:21:36.148410 progress 10 % (5 MB)
55 00:21:36.162563 progress 15 % (7 MB)
56 00:21:36.176784 progress 20 % (10 MB)
57 00:21:36.191061 progress 25 % (13 MB)
58 00:21:36.205482 progress 30 % (15 MB)
59 00:21:36.219733 progress 35 % (18 MB)
60 00:21:36.238194 progress 40 % (20 MB)
61 00:21:36.260509 progress 45 % (23 MB)
62 00:21:36.276513 progress 50 % (26 MB)
63 00:21:36.290642 progress 55 % (28 MB)
64 00:21:36.304960 progress 60 % (31 MB)
65 00:21:36.319770 progress 65 % (34 MB)
66 00:21:36.334201 progress 70 % (36 MB)
67 00:21:36.348849 progress 75 % (39 MB)
68 00:21:36.363098 progress 80 % (41 MB)
69 00:21:36.377794 progress 85 % (44 MB)
70 00:21:36.392127 progress 90 % (47 MB)
71 00:21:36.406502 progress 95 % (49 MB)
72 00:21:36.420365 progress 100 % (52 MB)
73 00:21:36.420631 52 MB downloaded in 0.30 s (173.22 MB/s)
74 00:21:36.420794 end: 1.2.1 http-download (duration 00:00:00) [common]
76 00:21:36.421032 end: 1.2 download-retry (duration 00:00:00) [common]
77 00:21:36.421119 start: 1.3 download-retry (timeout 00:09:59) [common]
78 00:21:36.421204 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 00:21:36.421353 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.94-cip23/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 00:21:36.421425 saving as /var/lib/lava/dispatcher/tmp/14479190/tftp-deploy-i9ftv1sc/dtb/mt8192-asurada-spherion-r0.dtb
81 00:21:36.421487 total size: 47258 (0 MB)
82 00:21:36.421548 No compression specified
83 00:21:36.422652 progress 69 % (0 MB)
84 00:21:36.422935 progress 100 % (0 MB)
85 00:21:36.423092 0 MB downloaded in 0.00 s (28.11 MB/s)
86 00:21:36.423219 end: 1.3.1 http-download (duration 00:00:00) [common]
88 00:21:36.423441 end: 1.3 download-retry (duration 00:00:00) [common]
89 00:21:36.423527 start: 1.4 download-retry (timeout 00:09:59) [common]
90 00:21:36.423610 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 00:21:36.423727 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.94-cip23/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 00:21:36.423796 saving as /var/lib/lava/dispatcher/tmp/14479190/tftp-deploy-i9ftv1sc/modules/modules.tar
93 00:21:36.423857 total size: 8618924 (8 MB)
94 00:21:36.423918 Using unxz to decompress xz
95 00:21:36.428114 progress 0 % (0 MB)
96 00:21:36.448024 progress 5 % (0 MB)
97 00:21:36.473343 progress 10 % (0 MB)
98 00:21:36.499297 progress 15 % (1 MB)
99 00:21:36.525684 progress 20 % (1 MB)
100 00:21:36.552579 progress 25 % (2 MB)
101 00:21:36.579641 progress 30 % (2 MB)
102 00:21:36.606507 progress 35 % (2 MB)
103 00:21:36.632085 progress 40 % (3 MB)
104 00:21:36.657923 progress 45 % (3 MB)
105 00:21:36.683602 progress 50 % (4 MB)
106 00:21:36.709170 progress 55 % (4 MB)
107 00:21:36.736276 progress 60 % (4 MB)
108 00:21:36.761508 progress 65 % (5 MB)
109 00:21:36.790663 progress 70 % (5 MB)
110 00:21:36.816500 progress 75 % (6 MB)
111 00:21:36.840616 progress 80 % (6 MB)
112 00:21:36.864917 progress 85 % (7 MB)
113 00:21:36.890421 progress 90 % (7 MB)
114 00:21:36.920883 progress 95 % (7 MB)
115 00:21:36.952902 progress 100 % (8 MB)
116 00:21:36.957859 8 MB downloaded in 0.53 s (15.39 MB/s)
117 00:21:36.958125 end: 1.4.1 http-download (duration 00:00:01) [common]
119 00:21:36.958418 end: 1.4 download-retry (duration 00:00:01) [common]
120 00:21:36.958528 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 00:21:36.958636 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 00:21:36.958733 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 00:21:36.958843 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 00:21:36.959098 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14479190/lava-overlay-eizhqc4r
125 00:21:36.959277 makedir: /var/lib/lava/dispatcher/tmp/14479190/lava-overlay-eizhqc4r/lava-14479190/bin
126 00:21:36.959424 makedir: /var/lib/lava/dispatcher/tmp/14479190/lava-overlay-eizhqc4r/lava-14479190/tests
127 00:21:36.959565 makedir: /var/lib/lava/dispatcher/tmp/14479190/lava-overlay-eizhqc4r/lava-14479190/results
128 00:21:36.959724 Creating /var/lib/lava/dispatcher/tmp/14479190/lava-overlay-eizhqc4r/lava-14479190/bin/lava-add-keys
129 00:21:36.959917 Creating /var/lib/lava/dispatcher/tmp/14479190/lava-overlay-eizhqc4r/lava-14479190/bin/lava-add-sources
130 00:21:36.960092 Creating /var/lib/lava/dispatcher/tmp/14479190/lava-overlay-eizhqc4r/lava-14479190/bin/lava-background-process-start
131 00:21:36.960271 Creating /var/lib/lava/dispatcher/tmp/14479190/lava-overlay-eizhqc4r/lava-14479190/bin/lava-background-process-stop
132 00:21:36.960440 Creating /var/lib/lava/dispatcher/tmp/14479190/lava-overlay-eizhqc4r/lava-14479190/bin/lava-common-functions
133 00:21:36.960584 Creating /var/lib/lava/dispatcher/tmp/14479190/lava-overlay-eizhqc4r/lava-14479190/bin/lava-echo-ipv4
134 00:21:36.960756 Creating /var/lib/lava/dispatcher/tmp/14479190/lava-overlay-eizhqc4r/lava-14479190/bin/lava-install-packages
135 00:21:36.960926 Creating /var/lib/lava/dispatcher/tmp/14479190/lava-overlay-eizhqc4r/lava-14479190/bin/lava-installed-packages
136 00:21:36.961099 Creating /var/lib/lava/dispatcher/tmp/14479190/lava-overlay-eizhqc4r/lava-14479190/bin/lava-os-build
137 00:21:36.961295 Creating /var/lib/lava/dispatcher/tmp/14479190/lava-overlay-eizhqc4r/lava-14479190/bin/lava-probe-channel
138 00:21:36.961465 Creating /var/lib/lava/dispatcher/tmp/14479190/lava-overlay-eizhqc4r/lava-14479190/bin/lava-probe-ip
139 00:21:36.961633 Creating /var/lib/lava/dispatcher/tmp/14479190/lava-overlay-eizhqc4r/lava-14479190/bin/lava-target-ip
140 00:21:36.961799 Creating /var/lib/lava/dispatcher/tmp/14479190/lava-overlay-eizhqc4r/lava-14479190/bin/lava-target-mac
141 00:21:36.961940 Creating /var/lib/lava/dispatcher/tmp/14479190/lava-overlay-eizhqc4r/lava-14479190/bin/lava-target-storage
142 00:21:36.962089 Creating /var/lib/lava/dispatcher/tmp/14479190/lava-overlay-eizhqc4r/lava-14479190/bin/lava-test-case
143 00:21:36.962270 Creating /var/lib/lava/dispatcher/tmp/14479190/lava-overlay-eizhqc4r/lava-14479190/bin/lava-test-event
144 00:21:36.962439 Creating /var/lib/lava/dispatcher/tmp/14479190/lava-overlay-eizhqc4r/lava-14479190/bin/lava-test-feedback
145 00:21:36.962609 Creating /var/lib/lava/dispatcher/tmp/14479190/lava-overlay-eizhqc4r/lava-14479190/bin/lava-test-raise
146 00:21:36.962784 Creating /var/lib/lava/dispatcher/tmp/14479190/lava-overlay-eizhqc4r/lava-14479190/bin/lava-test-reference
147 00:21:36.962927 Creating /var/lib/lava/dispatcher/tmp/14479190/lava-overlay-eizhqc4r/lava-14479190/bin/lava-test-runner
148 00:21:36.963069 Creating /var/lib/lava/dispatcher/tmp/14479190/lava-overlay-eizhqc4r/lava-14479190/bin/lava-test-set
149 00:21:36.963213 Creating /var/lib/lava/dispatcher/tmp/14479190/lava-overlay-eizhqc4r/lava-14479190/bin/lava-test-shell
150 00:21:36.963362 Updating /var/lib/lava/dispatcher/tmp/14479190/lava-overlay-eizhqc4r/lava-14479190/bin/lava-install-packages (oe)
151 00:21:36.963554 Updating /var/lib/lava/dispatcher/tmp/14479190/lava-overlay-eizhqc4r/lava-14479190/bin/lava-installed-packages (oe)
152 00:21:36.963694 Creating /var/lib/lava/dispatcher/tmp/14479190/lava-overlay-eizhqc4r/lava-14479190/environment
153 00:21:36.963844 LAVA metadata
154 00:21:36.963952 - LAVA_JOB_ID=14479190
155 00:21:36.964056 - LAVA_DISPATCHER_IP=192.168.201.1
156 00:21:36.964214 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 00:21:36.964319 skipped lava-vland-overlay
158 00:21:36.964437 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 00:21:36.964567 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 00:21:36.964667 skipped lava-multinode-overlay
161 00:21:36.964784 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 00:21:36.964921 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 00:21:36.965035 Loading test definitions
164 00:21:36.965177 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 00:21:36.965295 Using /lava-14479190 at stage 0
166 00:21:36.965753 uuid=14479190_1.5.2.3.1 testdef=None
167 00:21:36.965883 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 00:21:36.966012 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 00:21:36.966827 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 00:21:36.967204 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 00:21:36.968090 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 00:21:36.968373 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 00:21:36.969011 runner path: /var/lib/lava/dispatcher/tmp/14479190/lava-overlay-eizhqc4r/lava-14479190/0/tests/0_dmesg test_uuid 14479190_1.5.2.3.1
176 00:21:36.969188 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 00:21:36.969548 Creating lava-test-runner.conf files
179 00:21:36.969651 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14479190/lava-overlay-eizhqc4r/lava-14479190/0 for stage 0
180 00:21:36.969788 - 0_dmesg
181 00:21:36.969926 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 00:21:36.970052 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 00:21:36.978010 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 00:21:36.978143 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 00:21:36.978260 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 00:21:36.978385 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 00:21:36.978476 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 00:21:37.225403 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
189 00:21:37.225795 start: 1.5.4 extract-modules (timeout 00:09:59) [common]
190 00:21:37.225911 extracting modules file /var/lib/lava/dispatcher/tmp/14479190/tftp-deploy-i9ftv1sc/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14479190/extract-overlay-ramdisk-1r4o5ume/ramdisk
191 00:21:37.449322 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 00:21:37.449489 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 00:21:37.449588 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14479190/compress-overlay-ve78_yfx/overlay-1.5.2.4.tar.gz to ramdisk
194 00:21:37.449661 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14479190/compress-overlay-ve78_yfx/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14479190/extract-overlay-ramdisk-1r4o5ume/ramdisk
195 00:21:37.456331 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 00:21:37.456446 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 00:21:37.456537 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 00:21:37.456628 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 00:21:37.456722 Building ramdisk /var/lib/lava/dispatcher/tmp/14479190/extract-overlay-ramdisk-1r4o5ume/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14479190/extract-overlay-ramdisk-1r4o5ume/ramdisk
200 00:21:37.816619 >> 145269 blocks
201 00:21:40.176197 rename /var/lib/lava/dispatcher/tmp/14479190/extract-overlay-ramdisk-1r4o5ume/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14479190/tftp-deploy-i9ftv1sc/ramdisk/ramdisk.cpio.gz
202 00:21:40.176638 end: 1.5.7 compress-ramdisk (duration 00:00:03) [common]
203 00:21:40.176767 start: 1.5.8 prepare-kernel (timeout 00:09:56) [common]
204 00:21:40.176867 start: 1.5.8.1 prepare-fit (timeout 00:09:56) [common]
205 00:21:40.177131 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14479190/tftp-deploy-i9ftv1sc/kernel/Image']
206 00:21:54.884205 Returned 0 in 14 seconds
207 00:21:54.984806 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14479190/tftp-deploy-i9ftv1sc/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14479190/tftp-deploy-i9ftv1sc/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14479190/tftp-deploy-i9ftv1sc/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14479190/tftp-deploy-i9ftv1sc/kernel/image.itb
208 00:21:55.378398 output: FIT description: Kernel Image image with one or more FDT blobs
209 00:21:55.378764 output: Created: Fri Jun 21 01:21:55 2024
210 00:21:55.378837 output: Image 0 (kernel-1)
211 00:21:55.378901 output: Description:
212 00:21:55.378965 output: Created: Fri Jun 21 01:21:55 2024
213 00:21:55.379026 output: Type: Kernel Image
214 00:21:55.379084 output: Compression: lzma compressed
215 00:21:55.379141 output: Data Size: 13124896 Bytes = 12817.28 KiB = 12.52 MiB
216 00:21:55.379203 output: Architecture: AArch64
217 00:21:55.379264 output: OS: Linux
218 00:21:55.379323 output: Load Address: 0x00000000
219 00:21:55.379381 output: Entry Point: 0x00000000
220 00:21:55.379435 output: Hash algo: crc32
221 00:21:55.379491 output: Hash value: ab2f7826
222 00:21:55.379550 output: Image 1 (fdt-1)
223 00:21:55.379602 output: Description: mt8192-asurada-spherion-r0
224 00:21:55.379657 output: Created: Fri Jun 21 01:21:55 2024
225 00:21:55.379712 output: Type: Flat Device Tree
226 00:21:55.379764 output: Compression: uncompressed
227 00:21:55.379816 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 00:21:55.379869 output: Architecture: AArch64
229 00:21:55.379921 output: Hash algo: crc32
230 00:21:55.379973 output: Hash value: 0f8e4d2e
231 00:21:55.380025 output: Image 2 (ramdisk-1)
232 00:21:55.380077 output: Description: unavailable
233 00:21:55.380129 output: Created: Fri Jun 21 01:21:55 2024
234 00:21:55.380181 output: Type: RAMDisk Image
235 00:21:55.380233 output: Compression: Unknown Compression
236 00:21:55.380285 output: Data Size: 21374203 Bytes = 20873.25 KiB = 20.38 MiB
237 00:21:55.380338 output: Architecture: AArch64
238 00:21:55.380390 output: OS: Linux
239 00:21:55.380441 output: Load Address: unavailable
240 00:21:55.380493 output: Entry Point: unavailable
241 00:21:55.380545 output: Hash algo: crc32
242 00:21:55.380597 output: Hash value: f557bbe8
243 00:21:55.380649 output: Default Configuration: 'conf-1'
244 00:21:55.380701 output: Configuration 0 (conf-1)
245 00:21:55.380752 output: Description: mt8192-asurada-spherion-r0
246 00:21:55.380804 output: Kernel: kernel-1
247 00:21:55.380856 output: Init Ramdisk: ramdisk-1
248 00:21:55.380921 output: FDT: fdt-1
249 00:21:55.380974 output: Loadables: kernel-1
250 00:21:55.381027 output:
251 00:21:55.381229 end: 1.5.8.1 prepare-fit (duration 00:00:15) [common]
252 00:21:55.381344 end: 1.5.8 prepare-kernel (duration 00:00:15) [common]
253 00:21:55.381448 end: 1.5 prepare-tftp-overlay (duration 00:00:18) [common]
254 00:21:55.381538 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:40) [common]
255 00:21:55.381618 No LXC device requested
256 00:21:55.381698 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 00:21:55.381780 start: 1.7 deploy-device-env (timeout 00:09:40) [common]
258 00:21:55.381855 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 00:21:55.381921 Checking files for TFTP limit of 4294967296 bytes.
260 00:21:55.382430 end: 1 tftp-deploy (duration 00:00:20) [common]
261 00:21:55.382539 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 00:21:55.382631 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 00:21:55.382754 substitutions:
264 00:21:55.382820 - {DTB}: 14479190/tftp-deploy-i9ftv1sc/dtb/mt8192-asurada-spherion-r0.dtb
265 00:21:55.382881 - {INITRD}: 14479190/tftp-deploy-i9ftv1sc/ramdisk/ramdisk.cpio.gz
266 00:21:55.382940 - {KERNEL}: 14479190/tftp-deploy-i9ftv1sc/kernel/Image
267 00:21:55.382997 - {LAVA_MAC}: None
268 00:21:55.383053 - {PRESEED_CONFIG}: None
269 00:21:55.383107 - {PRESEED_LOCAL}: None
270 00:21:55.383163 - {RAMDISK}: 14479190/tftp-deploy-i9ftv1sc/ramdisk/ramdisk.cpio.gz
271 00:21:55.383217 - {ROOT_PART}: None
272 00:21:55.383272 - {ROOT}: None
273 00:21:55.383326 - {SERVER_IP}: 192.168.201.1
274 00:21:55.383379 - {TEE}: None
275 00:21:55.383432 Parsed boot commands:
276 00:21:55.383486 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 00:21:55.383659 Parsed boot commands: tftpboot 192.168.201.1 14479190/tftp-deploy-i9ftv1sc/kernel/image.itb 14479190/tftp-deploy-i9ftv1sc/kernel/cmdline
278 00:21:55.383760 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 00:21:55.383844 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 00:21:55.383935 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 00:21:55.384019 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 00:21:55.384088 Not connected, no need to disconnect.
283 00:21:55.384161 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 00:21:55.384240 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 00:21:55.384306 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-2'
286 00:21:55.388000 Setting prompt string to ['lava-test: # ']
287 00:21:55.388371 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 00:21:55.388472 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 00:21:55.388568 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 00:21:55.388656 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 00:21:55.388834 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-2']
292 00:22:09.357416 Returned 0 in 13 seconds
293 00:22:09.458449 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
295 00:22:09.458787 end: 2.2.2 reset-device (duration 00:00:14) [common]
296 00:22:09.458892 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
297 00:22:09.458979 Setting prompt string to 'Starting depthcharge on Spherion...'
298 00:22:09.459047 Changing prompt to 'Starting depthcharge on Spherion...'
299 00:22:09.459115 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
300 00:22:09.459576 [Enter `^Ec?' for help]
301 00:22:09.459663
302 00:22:09.459729
303 00:22:09.459789 F0: 102B 0000
304 00:22:09.459852
305 00:22:09.459924 F3: 1001 0000 [0200]
306 00:22:09.459985
307 00:22:09.460052 F3: 1001 0000
308 00:22:09.460113
309 00:22:09.460169 F7: 102D 0000
310 00:22:09.460244
311 00:22:09.460329 F1: 0000 0000
312 00:22:09.460398
313 00:22:09.460453 V0: 0000 0000 [0001]
314 00:22:09.460506
315 00:22:09.460560 00: 0007 8000
316 00:22:09.460617
317 00:22:09.460671 01: 0000 0000
318 00:22:09.460725
319 00:22:09.460778 BP: 0C00 0209 [0000]
320 00:22:09.460830
321 00:22:09.460883 G0: 1182 0000
322 00:22:09.460936
323 00:22:09.460988 EC: 0000 0021 [4000]
324 00:22:09.461041
325 00:22:09.461093 S7: 0000 0000 [0000]
326 00:22:09.461146
327 00:22:09.461198 CC: 0000 0000 [0001]
328 00:22:09.461251
329 00:22:09.461321 T0: 0000 0040 [010F]
330 00:22:09.461379
331 00:22:09.461456 Jump to BL
332 00:22:09.461511
333 00:22:09.461564
334 00:22:09.461617
335 00:22:09.461671 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
336 00:22:09.461746 ARM64: Exception handlers installed.
337 00:22:09.461802 ARM64: Testing exception
338 00:22:09.461855 ARM64: Done test exception
339 00:22:09.461908 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
340 00:22:09.461993 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
341 00:22:09.462052 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
342 00:22:09.462106 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
343 00:22:09.462161 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
344 00:22:09.462216 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
345 00:22:09.462270 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
346 00:22:09.462324 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
347 00:22:09.462378 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
348 00:22:09.462432 WDT: Last reset was cold boot
349 00:22:09.462485 SPI1(PAD0) initialized at 2873684 Hz
350 00:22:09.462539 SPI5(PAD0) initialized at 992727 Hz
351 00:22:09.462592 VBOOT: Loading verstage.
352 00:22:09.462646 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
353 00:22:09.462699 FMAP: Found "FLASH" version 1.1 at 0x20000.
354 00:22:09.462753 FMAP: base = 0x0 size = 0x800000 #areas = 25
355 00:22:09.462806 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
356 00:22:09.462871 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
357 00:22:09.462963 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
358 00:22:09.463023 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
359 00:22:09.463078
360 00:22:09.463131
361 00:22:09.463185 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
362 00:22:09.463239 ARM64: Exception handlers installed.
363 00:22:09.463292 ARM64: Testing exception
364 00:22:09.463344 ARM64: Done test exception
365 00:22:09.463397 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
366 00:22:09.463451 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
367 00:22:09.463504 Probing TPM: . done!
368 00:22:09.463556 TPM ready after 0 ms
369 00:22:09.463608 Connected to device vid:did:rid of 1ae0:0028:00
370 00:22:09.463662 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
371 00:22:09.463716 Initialized TPM device CR50 revision 0
372 00:22:09.463800 tlcl_send_startup: Startup return code is 0
373 00:22:09.463887 TPM: setup succeeded
374 00:22:09.463974 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
375 00:22:09.464074 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
376 00:22:09.464170 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
377 00:22:09.464256 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 00:22:09.464340 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
379 00:22:09.464425 in-header: 03 07 00 00 08 00 00 00
380 00:22:09.464516 in-data: aa e4 47 04 13 02 00 00
381 00:22:09.464600 Chrome EC: UHEPI supported
382 00:22:09.464684 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
383 00:22:09.464769 in-header: 03 a9 00 00 08 00 00 00
384 00:22:09.464853 in-data: 84 60 60 08 00 00 00 00
385 00:22:09.464961 Phase 1
386 00:22:09.465046 FMAP: area GBB found @ 3f5000 (12032 bytes)
387 00:22:09.465132 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
388 00:22:09.465226 VB2:vb2_check_recovery() Recovery was requested manually
389 00:22:09.465318 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
390 00:22:09.465387 Recovery requested (1009000e)
391 00:22:09.465451 TPM: Extending digest for VBOOT: boot mode into PCR 0
392 00:22:09.465507 tlcl_extend: response is 0
393 00:22:09.465561 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
394 00:22:09.465615 tlcl_extend: response is 0
395 00:22:09.465668 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
396 00:22:09.465722 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
397 00:22:09.465775 BS: bootblock times (exec / console): total (unknown) / 148 ms
398 00:22:09.465846
399 00:22:09.465901
400 00:22:09.465954 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
401 00:22:09.466008 ARM64: Exception handlers installed.
402 00:22:09.466107 ARM64: Testing exception
403 00:22:09.466166 ARM64: Done test exception
404 00:22:09.466219 pmic_efuse_setting: Set efuses in 11 msecs
405 00:22:09.466273 pmwrap_interface_init: Select PMIF_VLD_RDY
406 00:22:09.466335 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
407 00:22:09.466393 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
408 00:22:09.466660 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
409 00:22:09.466753 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
410 00:22:09.466839 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
411 00:22:09.466931 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
412 00:22:09.467019 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
413 00:22:09.467104 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
414 00:22:09.467188 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
415 00:22:09.467281 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
416 00:22:09.467366 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
417 00:22:09.467459 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
418 00:22:09.467550 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
419 00:22:09.467637 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
420 00:22:09.467724 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
421 00:22:09.467822 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
422 00:22:09.467913 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
423 00:22:09.468000 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
424 00:22:09.468104 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
425 00:22:09.468189 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
426 00:22:09.468278 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
427 00:22:09.468371 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
428 00:22:09.468445 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
429 00:22:09.468502 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
430 00:22:09.468555 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
431 00:22:09.468609 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
432 00:22:09.468679 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
433 00:22:09.468734 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
434 00:22:09.468787 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
435 00:22:09.468848 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
436 00:22:09.468905 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
437 00:22:09.468999 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
438 00:22:09.469087 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
439 00:22:09.469176 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
440 00:22:09.469282 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
441 00:22:09.469369 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
442 00:22:09.469483 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
443 00:22:09.469579 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
444 00:22:09.469665 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
445 00:22:09.469759 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
446 00:22:09.469853 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
447 00:22:09.469943 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
448 00:22:09.470017 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
449 00:22:09.470094 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
450 00:22:09.470180 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
451 00:22:09.470265 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
452 00:22:09.470359 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
453 00:22:09.470462 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
454 00:22:09.470562 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
455 00:22:09.470660 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
456 00:22:09.470754 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
457 00:22:09.470847 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
458 00:22:09.470938 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
459 00:22:09.471024 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
460 00:22:09.471109 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
461 00:22:09.471195 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
462 00:22:09.471280 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
463 00:22:09.471364 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
464 00:22:09.471449 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 00:22:09.471533 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x32
466 00:22:09.471618 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
467 00:22:09.471702 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
468 00:22:09.471798 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
469 00:22:09.471882 [RTC]rtc_get_frequency_meter,154: input=15, output=853
470 00:22:09.471967 [RTC]rtc_get_frequency_meter,154: input=7, output=726
471 00:22:09.472051 [RTC]rtc_get_frequency_meter,154: input=11, output=790
472 00:22:09.472135 [RTC]rtc_get_frequency_meter,154: input=13, output=822
473 00:22:09.472220 [RTC]rtc_get_frequency_meter,154: input=12, output=806
474 00:22:09.472303 [RTC]rtc_get_frequency_meter,154: input=11, output=790
475 00:22:09.472387 [RTC]rtc_get_frequency_meter,154: input=12, output=806
476 00:22:09.472471 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
477 00:22:09.472575 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
478 00:22:09.472873 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
479 00:22:09.472964 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
480 00:22:09.473050 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
481 00:22:09.473134 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
482 00:22:09.473219 ADC[4]: Raw value=904064 ID=7
483 00:22:09.473308 ADC[3]: Raw value=213916 ID=1
484 00:22:09.473365 RAM Code: 0x71
485 00:22:09.473419 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
486 00:22:09.473477 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
487 00:22:09.473531 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
488 00:22:09.473586 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
489 00:22:09.473640 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
490 00:22:09.473694 in-header: 03 07 00 00 08 00 00 00
491 00:22:09.473747 in-data: aa e4 47 04 13 02 00 00
492 00:22:09.473800 Chrome EC: UHEPI supported
493 00:22:09.473853 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
494 00:22:09.473906 in-header: 03 a9 00 00 08 00 00 00
495 00:22:09.473959 in-data: 84 60 60 08 00 00 00 00
496 00:22:09.474012 MRC: failed to locate region type 0.
497 00:22:09.474079 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
498 00:22:09.474134 DRAM-K: Running full calibration
499 00:22:09.474187 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
500 00:22:09.474241 header.status = 0x0
501 00:22:09.474295 header.version = 0x6 (expected: 0x6)
502 00:22:09.474349 header.size = 0xd00 (expected: 0xd00)
503 00:22:09.474401 header.flags = 0x0
504 00:22:09.474454 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
505 00:22:09.474508 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
506 00:22:09.474573 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
507 00:22:09.474628 dram_init: ddr_geometry: 2
508 00:22:09.474681 [EMI] MDL number = 2
509 00:22:09.474734 [EMI] Get MDL freq = 0
510 00:22:09.474786 dram_init: ddr_type: 0
511 00:22:09.474839 is_discrete_lpddr4: 1
512 00:22:09.474892 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
513 00:22:09.474945
514 00:22:09.474998
515 00:22:09.475050 [Bian_co] ETT version 0.0.0.1
516 00:22:09.475104 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
517 00:22:09.475157
518 00:22:09.475210 dramc_set_vcore_voltage set vcore to 650000
519 00:22:09.475262 Read voltage for 800, 4
520 00:22:09.475315 Vio18 = 0
521 00:22:09.475368 Vcore = 650000
522 00:22:09.475425 Vdram = 0
523 00:22:09.475491 Vddq = 0
524 00:22:09.475552 Vmddr = 0
525 00:22:09.475607 dram_init: config_dvfs: 1
526 00:22:09.475660 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
527 00:22:09.475713 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
528 00:22:09.475767 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
529 00:22:09.475820 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
530 00:22:09.475873 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
531 00:22:09.475968 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
532 00:22:09.476030 MEM_TYPE=3, freq_sel=18
533 00:22:09.476084 sv_algorithm_assistance_LP4_1600
534 00:22:09.476137 ============ PULL DRAM RESETB DOWN ============
535 00:22:09.476192 ========== PULL DRAM RESETB DOWN end =========
536 00:22:09.476245 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
537 00:22:09.476298 ===================================
538 00:22:09.476351 LPDDR4 DRAM CONFIGURATION
539 00:22:09.476404 ===================================
540 00:22:09.476457 EX_ROW_EN[0] = 0x0
541 00:22:09.476510 EX_ROW_EN[1] = 0x0
542 00:22:09.476563 LP4Y_EN = 0x0
543 00:22:09.476625 WORK_FSP = 0x0
544 00:22:09.476711 WL = 0x2
545 00:22:09.476794 RL = 0x2
546 00:22:09.476877 BL = 0x2
547 00:22:09.476960 RPST = 0x0
548 00:22:09.477042 RD_PRE = 0x0
549 00:22:09.477125 WR_PRE = 0x1
550 00:22:09.477213 WR_PST = 0x0
551 00:22:09.477310 DBI_WR = 0x0
552 00:22:09.477394 DBI_RD = 0x0
553 00:22:09.477477 OTF = 0x1
554 00:22:09.477551 ===================================
555 00:22:09.477607 ===================================
556 00:22:09.477660 ANA top config
557 00:22:09.477714 ===================================
558 00:22:09.477767 DLL_ASYNC_EN = 0
559 00:22:09.477819 ALL_SLAVE_EN = 1
560 00:22:09.477872 NEW_RANK_MODE = 1
561 00:22:09.477929 DLL_IDLE_MODE = 1
562 00:22:09.477982 LP45_APHY_COMB_EN = 1
563 00:22:09.478034 TX_ODT_DIS = 1
564 00:22:09.478087 NEW_8X_MODE = 1
565 00:22:09.478140 ===================================
566 00:22:09.478204 ===================================
567 00:22:09.478258 data_rate = 1600
568 00:22:09.478311 CKR = 1
569 00:22:09.478363 DQ_P2S_RATIO = 8
570 00:22:09.478416 ===================================
571 00:22:09.478468 CA_P2S_RATIO = 8
572 00:22:09.478520 DQ_CA_OPEN = 0
573 00:22:09.478574 DQ_SEMI_OPEN = 0
574 00:22:09.478626 CA_SEMI_OPEN = 0
575 00:22:09.478679 CA_FULL_RATE = 0
576 00:22:09.478731 DQ_CKDIV4_EN = 1
577 00:22:09.478784 CA_CKDIV4_EN = 1
578 00:22:09.478837 CA_PREDIV_EN = 0
579 00:22:09.478889 PH8_DLY = 0
580 00:22:09.478941 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
581 00:22:09.479041 DQ_AAMCK_DIV = 4
582 00:22:09.479099 CA_AAMCK_DIV = 4
583 00:22:09.479152 CA_ADMCK_DIV = 4
584 00:22:09.479206 DQ_TRACK_CA_EN = 0
585 00:22:09.479259 CA_PICK = 800
586 00:22:09.479312 CA_MCKIO = 800
587 00:22:09.479365 MCKIO_SEMI = 0
588 00:22:09.479418 PLL_FREQ = 3068
589 00:22:09.479470 DQ_UI_PI_RATIO = 32
590 00:22:09.479523 CA_UI_PI_RATIO = 0
591 00:22:09.479576 ===================================
592 00:22:09.479629 ===================================
593 00:22:09.479685 memory_type:LPDDR4
594 00:22:09.479785 GP_NUM : 10
595 00:22:09.479889 SRAM_EN : 1
596 00:22:09.479990 MD32_EN : 0
597 00:22:09.480314 ===================================
598 00:22:09.480408 [ANA_INIT] >>>>>>>>>>>>>>
599 00:22:09.480496 <<<<<< [CONFIGURE PHASE]: ANA_TX
600 00:22:09.480586 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
601 00:22:09.480672 ===================================
602 00:22:09.480758 data_rate = 1600,PCW = 0X7600
603 00:22:09.480843 ===================================
604 00:22:09.480927 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
605 00:22:09.481013 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
606 00:22:09.481098 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 00:22:09.481183 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
608 00:22:09.481281 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
609 00:22:09.481340 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
610 00:22:09.481395 [ANA_INIT] flow start
611 00:22:09.481449 [ANA_INIT] PLL >>>>>>>>
612 00:22:09.481503 [ANA_INIT] PLL <<<<<<<<
613 00:22:09.481556 [ANA_INIT] MIDPI >>>>>>>>
614 00:22:09.481608 [ANA_INIT] MIDPI <<<<<<<<
615 00:22:09.481673 [ANA_INIT] DLL >>>>>>>>
616 00:22:09.481727 [ANA_INIT] flow end
617 00:22:09.481780 ============ LP4 DIFF to SE enter ============
618 00:22:09.481834 ============ LP4 DIFF to SE exit ============
619 00:22:09.481886 [ANA_INIT] <<<<<<<<<<<<<
620 00:22:09.481939 [Flow] Enable top DCM control >>>>>
621 00:22:09.481999 [Flow] Enable top DCM control <<<<<
622 00:22:09.482052 Enable DLL master slave shuffle
623 00:22:09.482105 ==============================================================
624 00:22:09.482158 Gating Mode config
625 00:22:09.482211 ==============================================================
626 00:22:09.482265 Config description:
627 00:22:09.482318 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
628 00:22:09.482372 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
629 00:22:09.482426 SELPH_MODE 0: By rank 1: By Phase
630 00:22:09.482480 ==============================================================
631 00:22:09.482533 GAT_TRACK_EN = 1
632 00:22:09.482606 RX_GATING_MODE = 2
633 00:22:09.482665 RX_GATING_TRACK_MODE = 2
634 00:22:09.482718 SELPH_MODE = 1
635 00:22:09.482771 PICG_EARLY_EN = 1
636 00:22:09.482824 VALID_LAT_VALUE = 1
637 00:22:09.482877 ==============================================================
638 00:22:09.482930 Enter into Gating configuration >>>>
639 00:22:09.482983 Exit from Gating configuration <<<<
640 00:22:09.483036 Enter into DVFS_PRE_config >>>>>
641 00:22:09.483090 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
642 00:22:09.483147 Exit from DVFS_PRE_config <<<<<
643 00:22:09.483206 Enter into PICG configuration >>>>
644 00:22:09.483259 Exit from PICG configuration <<<<
645 00:22:09.483312 [RX_INPUT] configuration >>>>>
646 00:22:09.483364 [RX_INPUT] configuration <<<<<
647 00:22:09.483417 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
648 00:22:09.483471 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
649 00:22:09.483532 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
650 00:22:09.483589 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
651 00:22:09.483645 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
652 00:22:09.483698 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
653 00:22:09.483752 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
654 00:22:09.483805 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
655 00:22:09.483858 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
656 00:22:09.483911 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
657 00:22:09.483964 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
658 00:22:09.484030 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
659 00:22:09.484084 ===================================
660 00:22:09.484138 LPDDR4 DRAM CONFIGURATION
661 00:22:09.484191 ===================================
662 00:22:09.484243 EX_ROW_EN[0] = 0x0
663 00:22:09.484296 EX_ROW_EN[1] = 0x0
664 00:22:09.484349 LP4Y_EN = 0x0
665 00:22:09.484401 WORK_FSP = 0x0
666 00:22:09.484454 WL = 0x2
667 00:22:09.484519 RL = 0x2
668 00:22:09.484583 BL = 0x2
669 00:22:09.484636 RPST = 0x0
670 00:22:09.484688 RD_PRE = 0x0
671 00:22:09.484741 WR_PRE = 0x1
672 00:22:09.484794 WR_PST = 0x0
673 00:22:09.484846 DBI_WR = 0x0
674 00:22:09.484899 DBI_RD = 0x0
675 00:22:09.484950 OTF = 0x1
676 00:22:09.485003 ===================================
677 00:22:09.485056 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
678 00:22:09.485108 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
679 00:22:09.485161 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
680 00:22:09.485214 ===================================
681 00:22:09.485282 LPDDR4 DRAM CONFIGURATION
682 00:22:09.485341 ===================================
683 00:22:09.485394 EX_ROW_EN[0] = 0x10
684 00:22:09.485448 EX_ROW_EN[1] = 0x0
685 00:22:09.485501 LP4Y_EN = 0x0
686 00:22:09.485557 WORK_FSP = 0x0
687 00:22:09.485624 WL = 0x2
688 00:22:09.485677 RL = 0x2
689 00:22:09.485729 BL = 0x2
690 00:22:09.485781 RPST = 0x0
691 00:22:09.485833 RD_PRE = 0x0
692 00:22:09.485893 WR_PRE = 0x1
693 00:22:09.485945 WR_PST = 0x0
694 00:22:09.486010 DBI_WR = 0x0
695 00:22:09.486087 DBI_RD = 0x0
696 00:22:09.486142 OTF = 0x1
697 00:22:09.486196 ===================================
698 00:22:09.486249 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
699 00:22:09.486303 nWR fixed to 40
700 00:22:09.486357 [ModeRegInit_LP4] CH0 RK0
701 00:22:09.486409 [ModeRegInit_LP4] CH0 RK1
702 00:22:09.486462 [ModeRegInit_LP4] CH1 RK0
703 00:22:09.486514 [ModeRegInit_LP4] CH1 RK1
704 00:22:09.486577 match AC timing 13
705 00:22:09.486629 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
706 00:22:09.486891 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
707 00:22:09.486951 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
708 00:22:09.487006 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
709 00:22:09.487060 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
710 00:22:09.487114 [EMI DOE] emi_dcm 0
711 00:22:09.487168 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
712 00:22:09.487220 ==
713 00:22:09.487274 Dram Type= 6, Freq= 0, CH_0, rank 0
714 00:22:09.487327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
715 00:22:09.487379 ==
716 00:22:09.487432 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
717 00:22:09.487485 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
718 00:22:09.487538 [CA 0] Center 38 (7~69) winsize 63
719 00:22:09.487590 [CA 1] Center 37 (6~68) winsize 63
720 00:22:09.487642 [CA 2] Center 34 (4~65) winsize 62
721 00:22:09.487695 [CA 3] Center 34 (4~65) winsize 62
722 00:22:09.487747 [CA 4] Center 33 (3~64) winsize 62
723 00:22:09.487800 [CA 5] Center 33 (3~64) winsize 62
724 00:22:09.487877
725 00:22:09.487980 [CmdBusTrainingLP45] Vref(ca) range 1: 34
726 00:22:09.488070
727 00:22:09.488147 [CATrainingPosCal] consider 1 rank data
728 00:22:09.488226 u2DelayCellTimex100 = 270/100 ps
729 00:22:09.488321 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
730 00:22:09.488417 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
731 00:22:09.488511 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
732 00:22:09.488605 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
733 00:22:09.488679 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
734 00:22:09.488773 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
735 00:22:09.488867
736 00:22:09.488960 CA PerBit enable=1, Macro0, CA PI delay=33
737 00:22:09.489053
738 00:22:09.489149 [CBTSetCACLKResult] CA Dly = 33
739 00:22:09.489243 CS Dly: 5 (0~36)
740 00:22:09.489346 ==
741 00:22:09.489452 Dram Type= 6, Freq= 0, CH_0, rank 1
742 00:22:09.489546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
743 00:22:09.489641 ==
744 00:22:09.489734 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
745 00:22:09.489837 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
746 00:22:09.489937 [CA 0] Center 38 (7~69) winsize 63
747 00:22:09.490015 [CA 1] Center 37 (7~68) winsize 62
748 00:22:09.490109 [CA 2] Center 35 (4~66) winsize 63
749 00:22:09.490181 [CA 3] Center 35 (4~66) winsize 63
750 00:22:09.490238 [CA 4] Center 34 (3~65) winsize 63
751 00:22:09.490294 [CA 5] Center 33 (3~64) winsize 62
752 00:22:09.490349
753 00:22:09.490402 [CmdBusTrainingLP45] Vref(ca) range 1: 34
754 00:22:09.490456
755 00:22:09.490509 [CATrainingPosCal] consider 2 rank data
756 00:22:09.490563 u2DelayCellTimex100 = 270/100 ps
757 00:22:09.490617 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
758 00:22:09.490670 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
759 00:22:09.490723 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
760 00:22:09.490777 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
761 00:22:09.490830 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
762 00:22:09.490883 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
763 00:22:09.490936
764 00:22:09.490989 CA PerBit enable=1, Macro0, CA PI delay=33
765 00:22:09.491054
766 00:22:09.491107 [CBTSetCACLKResult] CA Dly = 33
767 00:22:09.491161 CS Dly: 6 (0~38)
768 00:22:09.491214
769 00:22:09.491266 ----->DramcWriteLeveling(PI) begin...
770 00:22:09.491320 ==
771 00:22:09.491373 Dram Type= 6, Freq= 0, CH_0, rank 0
772 00:22:09.491431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
773 00:22:09.491499 ==
774 00:22:09.491552 Write leveling (Byte 0): 34 => 34
775 00:22:09.491604 Write leveling (Byte 1): 27 => 27
776 00:22:09.491673 DramcWriteLeveling(PI) end<-----
777 00:22:09.491762
778 00:22:09.491853 ==
779 00:22:09.491945 Dram Type= 6, Freq= 0, CH_0, rank 0
780 00:22:09.492039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 00:22:09.492132 ==
782 00:22:09.492224 [Gating] SW mode calibration
783 00:22:09.492317 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
784 00:22:09.492412 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
785 00:22:09.492506 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
786 00:22:09.492612 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
787 00:22:09.492707 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
788 00:22:09.492801 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
789 00:22:09.492894 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 00:22:09.492987 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 00:22:09.493079 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 00:22:09.493171 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 00:22:09.493276 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 00:22:09.493364 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 00:22:09.493449 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 00:22:09.493538 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 00:22:09.493637 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 00:22:09.493721 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 00:22:09.493805 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 00:22:09.493889 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 00:22:09.493973 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 00:22:09.494057 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
803 00:22:09.494141 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
804 00:22:09.494225 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 00:22:09.494309 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 00:22:09.494393 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 00:22:09.494477 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 00:22:09.494570 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 00:22:09.494654 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 00:22:09.494738 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 00:22:09.494822 0 9 8 | B1->B0 | 2322 3131 | 1 0 | (0 0) (0 0)
812 00:22:09.494906 0 9 12 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
813 00:22:09.494990 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 00:22:09.495288 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 00:22:09.495384 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 00:22:09.495478 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 00:22:09.495569 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 00:22:09.495661 0 10 4 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
819 00:22:09.495753 0 10 8 | B1->B0 | 3030 2424 | 0 0 | (0 0) (0 0)
820 00:22:09.495846 0 10 12 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
821 00:22:09.495940 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 00:22:09.496033 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 00:22:09.496126 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 00:22:09.496219 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 00:22:09.496311 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 00:22:09.496404 0 11 4 | B1->B0 | 2323 3030 | 0 1 | (0 0) (0 0)
827 00:22:09.496508 0 11 8 | B1->B0 | 2828 4444 | 1 0 | (0 0) (0 0)
828 00:22:09.496601 0 11 12 | B1->B0 | 3e3e 4646 | 1 0 | (0 0) (0 0)
829 00:22:09.496693 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 00:22:09.496786 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 00:22:09.496879 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 00:22:09.496971 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 00:22:09.497063 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 00:22:09.497156 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
835 00:22:09.497248 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
836 00:22:09.497352 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 00:22:09.497456 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 00:22:09.497558 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 00:22:09.497651 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 00:22:09.497743 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 00:22:09.497835 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 00:22:09.497938 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 00:22:09.498031 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 00:22:09.498123 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 00:22:09.498215 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 00:22:09.498309 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 00:22:09.498401 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 00:22:09.498493 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 00:22:09.498585 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 00:22:09.498678 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
851 00:22:09.498771 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
852 00:22:09.498864 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
853 00:22:09.498956 Total UI for P1: 0, mck2ui 16
854 00:22:09.499050 best dqsien dly found for B0: ( 0, 14, 6)
855 00:22:09.499143 Total UI for P1: 0, mck2ui 16
856 00:22:09.499236 best dqsien dly found for B1: ( 0, 14, 6)
857 00:22:09.499328 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
858 00:22:09.499421 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
859 00:22:09.499513
860 00:22:09.499624 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
861 00:22:09.499718 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
862 00:22:09.499810 [Gating] SW calibration Done
863 00:22:09.499912 ==
864 00:22:09.500006 Dram Type= 6, Freq= 0, CH_0, rank 0
865 00:22:09.500099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
866 00:22:09.500191 ==
867 00:22:09.500284 RX Vref Scan: 0
868 00:22:09.500376
869 00:22:09.500468 RX Vref 0 -> 0, step: 1
870 00:22:09.500560
871 00:22:09.500652 RX Delay -130 -> 252, step: 16
872 00:22:09.500744 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
873 00:22:09.500837 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
874 00:22:09.500929 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
875 00:22:09.501020 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
876 00:22:09.501123 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
877 00:22:09.501214 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
878 00:22:09.501317 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
879 00:22:09.501410 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
880 00:22:09.501503 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
881 00:22:09.501595 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
882 00:22:09.501697 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
883 00:22:09.501798 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
884 00:22:09.501891 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
885 00:22:09.501984 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
886 00:22:09.502076 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
887 00:22:09.502168 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
888 00:22:09.502260 ==
889 00:22:09.502356 Dram Type= 6, Freq= 0, CH_0, rank 0
890 00:22:09.502447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
891 00:22:09.502532 ==
892 00:22:09.502615 DQS Delay:
893 00:22:09.502698 DQS0 = 0, DQS1 = 0
894 00:22:09.502781 DQM Delay:
895 00:22:09.502864 DQM0 = 88, DQM1 = 75
896 00:22:09.502947 DQ Delay:
897 00:22:09.503030 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
898 00:22:09.503113 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
899 00:22:09.503197 DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =69
900 00:22:09.503280 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
901 00:22:09.503363
902 00:22:09.503445
903 00:22:09.503527 ==
904 00:22:09.503610 Dram Type= 6, Freq= 0, CH_0, rank 0
905 00:22:09.503694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
906 00:22:09.503778 ==
907 00:22:09.503860
908 00:22:09.503942
909 00:22:09.504025 TX Vref Scan disable
910 00:22:09.504108 == TX Byte 0 ==
911 00:22:09.504191 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
912 00:22:09.504275 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
913 00:22:09.504358 == TX Byte 1 ==
914 00:22:09.504441 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
915 00:22:09.504535 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
916 00:22:09.504619 ==
917 00:22:09.504702 Dram Type= 6, Freq= 0, CH_0, rank 0
918 00:22:09.504786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
919 00:22:09.504869 ==
920 00:22:09.504953 TX Vref=22, minBit 0, minWin=27, winSum=439
921 00:22:09.505037 TX Vref=24, minBit 4, minWin=27, winSum=446
922 00:22:09.505329 TX Vref=26, minBit 7, minWin=27, winSum=449
923 00:22:09.505422 TX Vref=28, minBit 1, minWin=27, winSum=450
924 00:22:09.505508 TX Vref=30, minBit 1, minWin=27, winSum=453
925 00:22:09.505593 TX Vref=32, minBit 2, minWin=27, winSum=450
926 00:22:09.505679 [TxChooseVref] Worse bit 1, Min win 27, Win sum 453, Final Vref 30
927 00:22:09.505763
928 00:22:09.505847 Final TX Range 1 Vref 30
929 00:22:09.505932
930 00:22:09.506023 ==
931 00:22:09.506115 Dram Type= 6, Freq= 0, CH_0, rank 0
932 00:22:09.506220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
933 00:22:09.506321 ==
934 00:22:09.506414
935 00:22:09.506515
936 00:22:09.506609 TX Vref Scan disable
937 00:22:09.506713 == TX Byte 0 ==
938 00:22:09.506811 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
939 00:22:09.506910 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
940 00:22:09.506997 == TX Byte 1 ==
941 00:22:09.507083 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
942 00:22:09.507169 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
943 00:22:09.507257
944 00:22:09.507341 [DATLAT]
945 00:22:09.507424 Freq=800, CH0 RK0
946 00:22:09.507507
947 00:22:09.507589 DATLAT Default: 0xa
948 00:22:09.507672 0, 0xFFFF, sum = 0
949 00:22:09.507757 1, 0xFFFF, sum = 0
950 00:22:09.507854 2, 0xFFFF, sum = 0
951 00:22:09.507940 3, 0xFFFF, sum = 0
952 00:22:09.508025 4, 0xFFFF, sum = 0
953 00:22:09.508118 5, 0xFFFF, sum = 0
954 00:22:09.508203 6, 0xFFFF, sum = 0
955 00:22:09.508287 7, 0xFFFF, sum = 0
956 00:22:09.508372 8, 0xFFFF, sum = 0
957 00:22:09.508457 9, 0x0, sum = 1
958 00:22:09.508551 10, 0x0, sum = 2
959 00:22:09.508637 11, 0x0, sum = 3
960 00:22:09.508721 12, 0x0, sum = 4
961 00:22:09.508806 best_step = 10
962 00:22:09.508888
963 00:22:09.508970 ==
964 00:22:09.509054 Dram Type= 6, Freq= 0, CH_0, rank 0
965 00:22:09.509137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
966 00:22:09.509221 ==
967 00:22:09.509322 RX Vref Scan: 1
968 00:22:09.509406
969 00:22:09.509499 Set Vref Range= 32 -> 127
970 00:22:09.509582
971 00:22:09.509665 RX Vref 32 -> 127, step: 1
972 00:22:09.509751
973 00:22:09.509836 RX Delay -111 -> 252, step: 8
974 00:22:09.509921
975 00:22:09.509992 Set Vref, RX VrefLevel [Byte0]: 32
976 00:22:09.510047 [Byte1]: 32
977 00:22:09.510101
978 00:22:09.510153 Set Vref, RX VrefLevel [Byte0]: 33
979 00:22:09.510206 [Byte1]: 33
980 00:22:09.510258
981 00:22:09.510311 Set Vref, RX VrefLevel [Byte0]: 34
982 00:22:09.510363 [Byte1]: 34
983 00:22:09.510415
984 00:22:09.510472 Set Vref, RX VrefLevel [Byte0]: 35
985 00:22:09.510527 [Byte1]: 35
986 00:22:09.510580
987 00:22:09.510632 Set Vref, RX VrefLevel [Byte0]: 36
988 00:22:09.510685 [Byte1]: 36
989 00:22:09.510737
990 00:22:09.510789 Set Vref, RX VrefLevel [Byte0]: 37
991 00:22:09.510852 [Byte1]: 37
992 00:22:09.510906
993 00:22:09.510959 Set Vref, RX VrefLevel [Byte0]: 38
994 00:22:09.511011 [Byte1]: 38
995 00:22:09.511063
996 00:22:09.511115 Set Vref, RX VrefLevel [Byte0]: 39
997 00:22:09.511168 [Byte1]: 39
998 00:22:09.511220
999 00:22:09.511272 Set Vref, RX VrefLevel [Byte0]: 40
1000 00:22:09.511325 [Byte1]: 40
1001 00:22:09.511377
1002 00:22:09.511439 Set Vref, RX VrefLevel [Byte0]: 41
1003 00:22:09.511515 [Byte1]: 41
1004 00:22:09.511572
1005 00:22:09.511624 Set Vref, RX VrefLevel [Byte0]: 42
1006 00:22:09.511677 [Byte1]: 42
1007 00:22:09.511728
1008 00:22:09.511780 Set Vref, RX VrefLevel [Byte0]: 43
1009 00:22:09.511833 [Byte1]: 43
1010 00:22:09.511885
1011 00:22:09.511943 Set Vref, RX VrefLevel [Byte0]: 44
1012 00:22:09.511998 [Byte1]: 44
1013 00:22:09.512089
1014 00:22:09.512173 Set Vref, RX VrefLevel [Byte0]: 45
1015 00:22:09.512265 [Byte1]: 45
1016 00:22:09.512348
1017 00:22:09.512436 Set Vref, RX VrefLevel [Byte0]: 46
1018 00:22:09.512509 [Byte1]: 46
1019 00:22:09.512607
1020 00:22:09.512702 Set Vref, RX VrefLevel [Byte0]: 47
1021 00:22:09.512787 [Byte1]: 47
1022 00:22:09.512870
1023 00:22:09.512953 Set Vref, RX VrefLevel [Byte0]: 48
1024 00:22:09.513037 [Byte1]: 48
1025 00:22:09.513127
1026 00:22:09.513212 Set Vref, RX VrefLevel [Byte0]: 49
1027 00:22:09.513302 [Byte1]: 49
1028 00:22:09.513359
1029 00:22:09.513417 Set Vref, RX VrefLevel [Byte0]: 50
1030 00:22:09.513479 [Byte1]: 50
1031 00:22:09.513533
1032 00:22:09.513585 Set Vref, RX VrefLevel [Byte0]: 51
1033 00:22:09.513639 [Byte1]: 51
1034 00:22:09.513692
1035 00:22:09.513745 Set Vref, RX VrefLevel [Byte0]: 52
1036 00:22:09.513797 [Byte1]: 52
1037 00:22:09.513849
1038 00:22:09.513901 Set Vref, RX VrefLevel [Byte0]: 53
1039 00:22:09.513953 [Byte1]: 53
1040 00:22:09.514006
1041 00:22:09.514058 Set Vref, RX VrefLevel [Byte0]: 54
1042 00:22:09.514111 [Byte1]: 54
1043 00:22:09.514178
1044 00:22:09.514256 Set Vref, RX VrefLevel [Byte0]: 55
1045 00:22:09.514331 [Byte1]: 55
1046 00:22:09.514423
1047 00:22:09.514513 Set Vref, RX VrefLevel [Byte0]: 56
1048 00:22:09.514605 [Byte1]: 56
1049 00:22:09.514695
1050 00:22:09.514786 Set Vref, RX VrefLevel [Byte0]: 57
1051 00:22:09.514878 [Byte1]: 57
1052 00:22:09.514969
1053 00:22:09.515059 Set Vref, RX VrefLevel [Byte0]: 58
1054 00:22:09.515150 [Byte1]: 58
1055 00:22:09.515248
1056 00:22:09.515343 Set Vref, RX VrefLevel [Byte0]: 59
1057 00:22:09.515442 [Byte1]: 59
1058 00:22:09.515525
1059 00:22:09.515608 Set Vref, RX VrefLevel [Byte0]: 60
1060 00:22:09.515691 [Byte1]: 60
1061 00:22:09.515773
1062 00:22:09.515855 Set Vref, RX VrefLevel [Byte0]: 61
1063 00:22:09.515937 [Byte1]: 61
1064 00:22:09.516019
1065 00:22:09.516103 Set Vref, RX VrefLevel [Byte0]: 62
1066 00:22:09.516193 [Byte1]: 62
1067 00:22:09.516284
1068 00:22:09.516375 Set Vref, RX VrefLevel [Byte0]: 63
1069 00:22:09.516466 [Byte1]: 63
1070 00:22:09.516558
1071 00:22:09.516648 Set Vref, RX VrefLevel [Byte0]: 64
1072 00:22:09.516751 [Byte1]: 64
1073 00:22:09.516848
1074 00:22:09.516935 Set Vref, RX VrefLevel [Byte0]: 65
1075 00:22:09.517020 [Byte1]: 65
1076 00:22:09.517103
1077 00:22:09.517185 Set Vref, RX VrefLevel [Byte0]: 66
1078 00:22:09.517277 [Byte1]: 66
1079 00:22:09.517361
1080 00:22:09.517477 Set Vref, RX VrefLevel [Byte0]: 67
1081 00:22:09.517563 [Byte1]: 67
1082 00:22:09.517645
1083 00:22:09.517727 Set Vref, RX VrefLevel [Byte0]: 68
1084 00:22:09.517810 [Byte1]: 68
1085 00:22:09.517892
1086 00:22:09.517974 Set Vref, RX VrefLevel [Byte0]: 69
1087 00:22:09.518056 [Byte1]: 69
1088 00:22:09.518138
1089 00:22:09.518220 Set Vref, RX VrefLevel [Byte0]: 70
1090 00:22:09.518518 [Byte1]: 70
1091 00:22:09.518610
1092 00:22:09.518695 Set Vref, RX VrefLevel [Byte0]: 71
1093 00:22:09.518778 [Byte1]: 71
1094 00:22:09.518860
1095 00:22:09.518943 Set Vref, RX VrefLevel [Byte0]: 72
1096 00:22:09.519027 [Byte1]: 72
1097 00:22:09.519109
1098 00:22:09.519191 Set Vref, RX VrefLevel [Byte0]: 73
1099 00:22:09.519273 [Byte1]: 73
1100 00:22:09.519354
1101 00:22:09.519455 Final RX Vref Byte 0 = 55 to rank0
1102 00:22:09.519548 Final RX Vref Byte 1 = 59 to rank0
1103 00:22:09.519626 Final RX Vref Byte 0 = 55 to rank1
1104 00:22:09.519701 Final RX Vref Byte 1 = 59 to rank1==
1105 00:22:09.519774 Dram Type= 6, Freq= 0, CH_0, rank 0
1106 00:22:09.519865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1107 00:22:09.519957 ==
1108 00:22:09.520048 DQS Delay:
1109 00:22:09.520139 DQS0 = 0, DQS1 = 0
1110 00:22:09.520231 DQM Delay:
1111 00:22:09.520322 DQM0 = 88, DQM1 = 76
1112 00:22:09.520422 DQ Delay:
1113 00:22:09.520514 DQ0 =88, DQ1 =88, DQ2 =88, DQ3 =84
1114 00:22:09.520608 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1115 00:22:09.520701 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =72
1116 00:22:09.520793 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1117 00:22:09.520885
1118 00:22:09.520957
1119 00:22:09.521030 [DQSOSCAuto] RK0, (LSB)MR18= 0x3932, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 395 ps
1120 00:22:09.521123 CH0 RK0: MR19=606, MR18=3932
1121 00:22:09.521215 CH0_RK0: MR19=0x606, MR18=0x3932, DQSOSC=395, MR23=63, INC=94, DEC=63
1122 00:22:09.521318
1123 00:22:09.521416 ----->DramcWriteLeveling(PI) begin...
1124 00:22:09.521518 ==
1125 00:22:09.521611 Dram Type= 6, Freq= 0, CH_0, rank 1
1126 00:22:09.521703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1127 00:22:09.521796 ==
1128 00:22:09.521888 Write leveling (Byte 0): 31 => 31
1129 00:22:09.521980 Write leveling (Byte 1): 27 => 27
1130 00:22:09.522071 DramcWriteLeveling(PI) end<-----
1131 00:22:09.522162
1132 00:22:09.522252 ==
1133 00:22:09.522344 Dram Type= 6, Freq= 0, CH_0, rank 1
1134 00:22:09.522435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1135 00:22:09.522527 ==
1136 00:22:09.522618 [Gating] SW mode calibration
1137 00:22:09.522710 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1138 00:22:09.522802 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1139 00:22:09.522902 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1140 00:22:09.523001 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1141 00:22:09.523094 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1142 00:22:09.523180 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1143 00:22:09.523265 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1144 00:22:09.523348 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1145 00:22:09.523451 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1146 00:22:09.523545 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1147 00:22:09.523636 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1148 00:22:09.523728 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1149 00:22:09.523819 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1150 00:22:09.523910 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1151 00:22:09.524001 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1152 00:22:09.524091 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 00:22:09.524193 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 00:22:09.524285 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 00:22:09.524376 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1156 00:22:09.524467 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1157 00:22:09.524557 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1158 00:22:09.524648 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 00:22:09.524739 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 00:22:09.524830 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 00:22:09.524921 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 00:22:09.525011 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 00:22:09.525102 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 00:22:09.525193 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 00:22:09.525291 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
1166 00:22:09.525383 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1167 00:22:09.525487 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1168 00:22:09.525579 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1169 00:22:09.525670 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1170 00:22:09.525762 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1171 00:22:09.525852 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1172 00:22:09.525943 0 10 4 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 1)
1173 00:22:09.526034 0 10 8 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
1174 00:22:09.526124 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 00:22:09.526215 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 00:22:09.526306 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 00:22:09.526396 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 00:22:09.526486 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 00:22:09.526576 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 00:22:09.526667 0 11 4 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
1181 00:22:09.526757 0 11 8 | B1->B0 | 3434 4545 | 0 0 | (0 0) (0 0)
1182 00:22:09.526848 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1183 00:22:09.526938 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1184 00:22:09.527029 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1185 00:22:09.527119 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1186 00:22:09.527210 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1187 00:22:09.527300 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1188 00:22:09.527390 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1189 00:22:09.527496 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1190 00:22:09.527598 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1191 00:22:09.527907 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1192 00:22:09.528003 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1193 00:22:09.528097 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1194 00:22:09.528190 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1195 00:22:09.528283 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1196 00:22:09.528376 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1197 00:22:09.528468 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1198 00:22:09.528561 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 00:22:09.528652 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 00:22:09.528744 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 00:22:09.528836 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 00:22:09.528928 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 00:22:09.529019 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 00:22:09.529110 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 00:22:09.529202 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1206 00:22:09.529305 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1207 00:22:09.529408 Total UI for P1: 0, mck2ui 16
1208 00:22:09.529499 best dqsien dly found for B0: ( 0, 14, 8)
1209 00:22:09.529591 Total UI for P1: 0, mck2ui 16
1210 00:22:09.529683 best dqsien dly found for B1: ( 0, 14, 8)
1211 00:22:09.529778 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1212 00:22:09.529871 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1213 00:22:09.529963
1214 00:22:09.530055 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1215 00:22:09.530146 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1216 00:22:09.530238 [Gating] SW calibration Done
1217 00:22:09.530331 ==
1218 00:22:09.530423 Dram Type= 6, Freq= 0, CH_0, rank 1
1219 00:22:09.530514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1220 00:22:09.530606 ==
1221 00:22:09.530708 RX Vref Scan: 0
1222 00:22:09.530800
1223 00:22:09.530891 RX Vref 0 -> 0, step: 1
1224 00:22:09.530983
1225 00:22:09.531074 RX Delay -130 -> 252, step: 16
1226 00:22:09.531165 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1227 00:22:09.531257 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1228 00:22:09.531348 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1229 00:22:09.531456 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1230 00:22:09.531548 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1231 00:22:09.531639 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1232 00:22:09.531731 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1233 00:22:09.531822 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1234 00:22:09.531913 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1235 00:22:09.532004 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1236 00:22:09.532096 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1237 00:22:09.532187 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1238 00:22:09.532278 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1239 00:22:09.532368 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1240 00:22:09.532459 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1241 00:22:09.532550 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1242 00:22:09.532641 ==
1243 00:22:09.532732 Dram Type= 6, Freq= 0, CH_0, rank 1
1244 00:22:09.532823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1245 00:22:09.532918 ==
1246 00:22:09.533009 DQS Delay:
1247 00:22:09.533100 DQS0 = 0, DQS1 = 0
1248 00:22:09.533191 DQM Delay:
1249 00:22:09.533292 DQM0 = 86, DQM1 = 77
1250 00:22:09.533384 DQ Delay:
1251 00:22:09.533498 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1252 00:22:09.533592 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1253 00:22:09.533681 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1254 00:22:09.533795 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1255 00:22:09.533907
1256 00:22:09.534015
1257 00:22:09.534123 ==
1258 00:22:09.534225 Dram Type= 6, Freq= 0, CH_0, rank 1
1259 00:22:09.534319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1260 00:22:09.534386 ==
1261 00:22:09.534442
1262 00:22:09.534495
1263 00:22:09.534548 TX Vref Scan disable
1264 00:22:09.534602 == TX Byte 0 ==
1265 00:22:09.534655 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1266 00:22:09.534709 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1267 00:22:09.534761 == TX Byte 1 ==
1268 00:22:09.534814 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1269 00:22:09.534866 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1270 00:22:09.534919 ==
1271 00:22:09.534972 Dram Type= 6, Freq= 0, CH_0, rank 1
1272 00:22:09.535025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1273 00:22:09.535078 ==
1274 00:22:09.535130 TX Vref=22, minBit 0, minWin=27, winSum=438
1275 00:22:09.535184 TX Vref=24, minBit 1, minWin=27, winSum=443
1276 00:22:09.535236 TX Vref=26, minBit 1, minWin=27, winSum=449
1277 00:22:09.535289 TX Vref=28, minBit 2, minWin=27, winSum=451
1278 00:22:09.535341 TX Vref=30, minBit 2, minWin=27, winSum=451
1279 00:22:09.535398 TX Vref=32, minBit 1, minWin=27, winSum=450
1280 00:22:09.535457 [TxChooseVref] Worse bit 2, Min win 27, Win sum 451, Final Vref 28
1281 00:22:09.535523
1282 00:22:09.535597 Final TX Range 1 Vref 28
1283 00:22:09.535671
1284 00:22:09.535744 ==
1285 00:22:09.535817 Dram Type= 6, Freq= 0, CH_0, rank 1
1286 00:22:09.535890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1287 00:22:09.535968 ==
1288 00:22:09.536059
1289 00:22:09.536150
1290 00:22:09.536242 TX Vref Scan disable
1291 00:22:09.536334 == TX Byte 0 ==
1292 00:22:09.536426 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1293 00:22:09.536517 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1294 00:22:09.536607 == TX Byte 1 ==
1295 00:22:09.536695 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1296 00:22:09.536785 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1297 00:22:09.536876
1298 00:22:09.536968 [DATLAT]
1299 00:22:09.537055 Freq=800, CH0 RK1
1300 00:22:09.537140
1301 00:22:09.537232 DATLAT Default: 0xa
1302 00:22:09.537326 0, 0xFFFF, sum = 0
1303 00:22:09.537412 1, 0xFFFF, sum = 0
1304 00:22:09.537510 2, 0xFFFF, sum = 0
1305 00:22:09.537596 3, 0xFFFF, sum = 0
1306 00:22:09.537685 4, 0xFFFF, sum = 0
1307 00:22:09.537772 5, 0xFFFF, sum = 0
1308 00:22:09.537865 6, 0xFFFF, sum = 0
1309 00:22:09.537951 7, 0xFFFF, sum = 0
1310 00:22:09.538036 8, 0xFFFF, sum = 0
1311 00:22:09.538121 9, 0x0, sum = 1
1312 00:22:09.538207 10, 0x0, sum = 2
1313 00:22:09.538293 11, 0x0, sum = 3
1314 00:22:09.538379 12, 0x0, sum = 4
1315 00:22:09.538465 best_step = 10
1316 00:22:09.538548
1317 00:22:09.538631 ==
1318 00:22:09.538715 Dram Type= 6, Freq= 0, CH_0, rank 1
1319 00:22:09.538799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1320 00:22:09.538884 ==
1321 00:22:09.538966 RX Vref Scan: 0
1322 00:22:09.539051
1323 00:22:09.539137 RX Vref 0 -> 0, step: 1
1324 00:22:09.539220
1325 00:22:09.539303 RX Delay -95 -> 252, step: 8
1326 00:22:09.539387 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1327 00:22:09.539695 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1328 00:22:09.539791 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1329 00:22:09.539879 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1330 00:22:09.539965 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1331 00:22:09.540050 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1332 00:22:09.540133 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1333 00:22:09.540224 iDelay=209, Bit 7, Center 92 (-15 ~ 200) 216
1334 00:22:09.540309 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1335 00:22:09.540393 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1336 00:22:09.540478 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1337 00:22:09.540561 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
1338 00:22:09.540644 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1339 00:22:09.540726 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1340 00:22:09.540824 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1341 00:22:09.540906 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1342 00:22:09.540989 ==
1343 00:22:09.541073 Dram Type= 6, Freq= 0, CH_0, rank 1
1344 00:22:09.541155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1345 00:22:09.541238 ==
1346 00:22:09.541334 DQS Delay:
1347 00:22:09.541419 DQS0 = 0, DQS1 = 0
1348 00:22:09.541501 DQM Delay:
1349 00:22:09.541584 DQM0 = 85, DQM1 = 76
1350 00:22:09.541668 DQ Delay:
1351 00:22:09.541751 DQ0 =84, DQ1 =88, DQ2 =80, DQ3 =80
1352 00:22:09.541834 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =92
1353 00:22:09.541917 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =72
1354 00:22:09.541999 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1355 00:22:09.542081
1356 00:22:09.542164
1357 00:22:09.542245 [DQSOSCAuto] RK1, (LSB)MR18= 0x302d, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
1358 00:22:09.542330 CH0 RK1: MR19=606, MR18=302D
1359 00:22:09.542413 CH0_RK1: MR19=0x606, MR18=0x302D, DQSOSC=397, MR23=63, INC=93, DEC=62
1360 00:22:09.542500 [RxdqsGatingPostProcess] freq 800
1361 00:22:09.542582 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1362 00:22:09.542670 Pre-setting of DQS Precalculation
1363 00:22:09.542761 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1364 00:22:09.542845 ==
1365 00:22:09.542927 Dram Type= 6, Freq= 0, CH_1, rank 0
1366 00:22:09.543010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1367 00:22:09.543094 ==
1368 00:22:09.543177 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1369 00:22:09.543260 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1370 00:22:09.543344 [CA 0] Center 37 (6~68) winsize 63
1371 00:22:09.543424 [CA 1] Center 37 (6~68) winsize 63
1372 00:22:09.543502 [CA 2] Center 34 (4~65) winsize 62
1373 00:22:09.543579 [CA 3] Center 34 (4~65) winsize 62
1374 00:22:09.543656 [CA 4] Center 34 (4~65) winsize 62
1375 00:22:09.543733 [CA 5] Center 33 (3~64) winsize 62
1376 00:22:09.543812
1377 00:22:09.543904 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1378 00:22:09.543990
1379 00:22:09.544071 [CATrainingPosCal] consider 1 rank data
1380 00:22:09.544155 u2DelayCellTimex100 = 270/100 ps
1381 00:22:09.544237 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1382 00:22:09.544320 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1383 00:22:09.544402 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1384 00:22:09.544484 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1385 00:22:09.544564 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1386 00:22:09.544647 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1387 00:22:09.544746
1388 00:22:09.544832 CA PerBit enable=1, Macro0, CA PI delay=33
1389 00:22:09.544921
1390 00:22:09.545015 [CBTSetCACLKResult] CA Dly = 33
1391 00:22:09.545107 CS Dly: 5 (0~36)
1392 00:22:09.545202 ==
1393 00:22:09.545352 Dram Type= 6, Freq= 0, CH_1, rank 1
1394 00:22:09.545442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1395 00:22:09.545508 ==
1396 00:22:09.545569 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1397 00:22:09.545629 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1398 00:22:09.545686 [CA 0] Center 36 (6~67) winsize 62
1399 00:22:09.545742 [CA 1] Center 37 (6~68) winsize 63
1400 00:22:09.545797 [CA 2] Center 34 (4~65) winsize 62
1401 00:22:09.545851 [CA 3] Center 34 (3~65) winsize 63
1402 00:22:09.545906 [CA 4] Center 34 (4~65) winsize 62
1403 00:22:09.545960 [CA 5] Center 33 (3~64) winsize 62
1404 00:22:09.546014
1405 00:22:09.546068 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1406 00:22:09.546122
1407 00:22:09.546175 [CATrainingPosCal] consider 2 rank data
1408 00:22:09.546230 u2DelayCellTimex100 = 270/100 ps
1409 00:22:09.546283 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1410 00:22:09.546337 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1411 00:22:09.546390 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1412 00:22:09.546444 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1413 00:22:09.546499 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1414 00:22:09.546552 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1415 00:22:09.546606
1416 00:22:09.546659 CA PerBit enable=1, Macro0, CA PI delay=33
1417 00:22:09.546712
1418 00:22:09.546787 [CBTSetCACLKResult] CA Dly = 33
1419 00:22:09.546874 CS Dly: 5 (0~37)
1420 00:22:09.546938
1421 00:22:09.546993 ----->DramcWriteLeveling(PI) begin...
1422 00:22:09.547048 ==
1423 00:22:09.547102 Dram Type= 6, Freq= 0, CH_1, rank 0
1424 00:22:09.547156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1425 00:22:09.547210 ==
1426 00:22:09.547264 Write leveling (Byte 0): 27 => 27
1427 00:22:09.547318 Write leveling (Byte 1): 28 => 28
1428 00:22:09.547371 DramcWriteLeveling(PI) end<-----
1429 00:22:09.547423
1430 00:22:09.547476 ==
1431 00:22:09.547529 Dram Type= 6, Freq= 0, CH_1, rank 0
1432 00:22:09.547582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1433 00:22:09.547636 ==
1434 00:22:09.547689 [Gating] SW mode calibration
1435 00:22:09.547742 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1436 00:22:09.547797 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1437 00:22:09.547850 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1438 00:22:09.547903 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1439 00:22:09.547955 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1440 00:22:09.548008 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1441 00:22:09.548062 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1442 00:22:09.548115 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1443 00:22:09.548168 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1444 00:22:09.548439 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1445 00:22:09.548501 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1446 00:22:09.548556 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1447 00:22:09.548611 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1448 00:22:09.548665 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1449 00:22:09.548718 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 00:22:09.548771 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 00:22:09.548825 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 00:22:09.548878 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 00:22:09.548931 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1454 00:22:09.548984 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1455 00:22:09.549037 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 00:22:09.549090 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 00:22:09.549143 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 00:22:09.549196 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 00:22:09.549248 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 00:22:09.549317 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 00:22:09.549371 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 00:22:09.549424 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1463 00:22:09.549477 0 9 8 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
1464 00:22:09.549529 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1465 00:22:09.549583 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1466 00:22:09.549636 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1467 00:22:09.549689 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1468 00:22:09.549742 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1469 00:22:09.549794 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1470 00:22:09.549847 0 10 4 | B1->B0 | 3333 3030 | 0 0 | (0 0) (0 0)
1471 00:22:09.549900 0 10 8 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
1472 00:22:09.549953 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 00:22:09.550006 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 00:22:09.550059 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 00:22:09.550112 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 00:22:09.550165 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 00:22:09.550217 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 00:22:09.550269 0 11 4 | B1->B0 | 2626 3030 | 0 1 | (0 0) (0 0)
1479 00:22:09.550322 0 11 8 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
1480 00:22:09.550375 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1481 00:22:09.550427 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1482 00:22:09.550480 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1483 00:22:09.550533 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1484 00:22:09.550587 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1485 00:22:09.550640 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1486 00:22:09.550693 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1487 00:22:09.550747 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1488 00:22:09.550799 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1489 00:22:09.550852 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1490 00:22:09.550905 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1491 00:22:09.550958 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1492 00:22:09.551010 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1493 00:22:09.551063 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1494 00:22:09.551116 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1495 00:22:09.551169 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1496 00:22:09.551222 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1497 00:22:09.551274 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 00:22:09.551328 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 00:22:09.551381 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 00:22:09.551433 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 00:22:09.551486 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 00:22:09.551538 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1503 00:22:09.551591 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1504 00:22:09.551644 Total UI for P1: 0, mck2ui 16
1505 00:22:09.551697 best dqsien dly found for B0: ( 0, 14, 4)
1506 00:22:09.551750 Total UI for P1: 0, mck2ui 16
1507 00:22:09.551803 best dqsien dly found for B1: ( 0, 14, 4)
1508 00:22:09.551856 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1509 00:22:09.551908 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1510 00:22:09.551961
1511 00:22:09.552014 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1512 00:22:09.552067 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1513 00:22:09.552120 [Gating] SW calibration Done
1514 00:22:09.552172 ==
1515 00:22:09.552226 Dram Type= 6, Freq= 0, CH_1, rank 0
1516 00:22:09.552279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1517 00:22:09.552332 ==
1518 00:22:09.552385 RX Vref Scan: 0
1519 00:22:09.552438
1520 00:22:09.552492 RX Vref 0 -> 0, step: 1
1521 00:22:09.552545
1522 00:22:09.552597 RX Delay -130 -> 252, step: 16
1523 00:22:09.552649 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1524 00:22:09.552703 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1525 00:22:09.552755 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1526 00:22:09.552808 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1527 00:22:09.552860 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1528 00:22:09.552913 iDelay=222, Bit 5, Center 93 (-18 ~ 205) 224
1529 00:22:09.552966 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1530 00:22:09.553019 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1531 00:22:09.553071 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1532 00:22:09.553124 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1533 00:22:09.553177 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1534 00:22:09.553437 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1535 00:22:09.553498 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1536 00:22:09.553553 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1537 00:22:09.553606 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1538 00:22:09.553659 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1539 00:22:09.553711 ==
1540 00:22:09.553764 Dram Type= 6, Freq= 0, CH_1, rank 0
1541 00:22:09.553817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1542 00:22:09.553871 ==
1543 00:22:09.553924 DQS Delay:
1544 00:22:09.553977 DQS0 = 0, DQS1 = 0
1545 00:22:09.554030 DQM Delay:
1546 00:22:09.554083 DQM0 = 83, DQM1 = 78
1547 00:22:09.554136 DQ Delay:
1548 00:22:09.554188 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1549 00:22:09.554241 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77
1550 00:22:09.554294 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1551 00:22:09.554348 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1552 00:22:09.554400
1553 00:22:09.554452
1554 00:22:09.554505 ==
1555 00:22:09.554557 Dram Type= 6, Freq= 0, CH_1, rank 0
1556 00:22:09.554611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1557 00:22:09.554664 ==
1558 00:22:09.554716
1559 00:22:09.554768
1560 00:22:09.554821 TX Vref Scan disable
1561 00:22:09.554874 == TX Byte 0 ==
1562 00:22:09.554927 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1563 00:22:09.554980 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1564 00:22:09.555033 == TX Byte 1 ==
1565 00:22:09.555085 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1566 00:22:09.555138 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1567 00:22:09.555190 ==
1568 00:22:09.555243 Dram Type= 6, Freq= 0, CH_1, rank 0
1569 00:22:09.555296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1570 00:22:09.555349 ==
1571 00:22:09.555402 TX Vref=22, minBit 4, minWin=27, winSum=444
1572 00:22:09.555455 TX Vref=24, minBit 1, minWin=27, winSum=448
1573 00:22:09.555508 TX Vref=26, minBit 4, minWin=27, winSum=456
1574 00:22:09.555561 TX Vref=28, minBit 1, minWin=27, winSum=454
1575 00:22:09.555614 TX Vref=30, minBit 1, minWin=27, winSum=454
1576 00:22:09.555668 TX Vref=32, minBit 0, minWin=27, winSum=453
1577 00:22:09.555721 [TxChooseVref] Worse bit 4, Min win 27, Win sum 456, Final Vref 26
1578 00:22:09.555774
1579 00:22:09.555827 Final TX Range 1 Vref 26
1580 00:22:09.555881
1581 00:22:09.555934 ==
1582 00:22:09.555986 Dram Type= 6, Freq= 0, CH_1, rank 0
1583 00:22:09.556039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1584 00:22:09.556092 ==
1585 00:22:09.556144
1586 00:22:09.556197
1587 00:22:09.556249 TX Vref Scan disable
1588 00:22:09.556301 == TX Byte 0 ==
1589 00:22:09.556354 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1590 00:22:09.556407 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1591 00:22:09.556460 == TX Byte 1 ==
1592 00:22:09.556512 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1593 00:22:09.556565 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1594 00:22:09.556617
1595 00:22:09.556670 [DATLAT]
1596 00:22:09.556722 Freq=800, CH1 RK0
1597 00:22:09.556774
1598 00:22:09.556827 DATLAT Default: 0xa
1599 00:22:09.556879 0, 0xFFFF, sum = 0
1600 00:22:09.556934 1, 0xFFFF, sum = 0
1601 00:22:09.556988 2, 0xFFFF, sum = 0
1602 00:22:09.557042 3, 0xFFFF, sum = 0
1603 00:22:09.557096 4, 0xFFFF, sum = 0
1604 00:22:09.557149 5, 0xFFFF, sum = 0
1605 00:22:09.557202 6, 0xFFFF, sum = 0
1606 00:22:09.557268 7, 0xFFFF, sum = 0
1607 00:22:09.557325 8, 0xFFFF, sum = 0
1608 00:22:09.557379 9, 0x0, sum = 1
1609 00:22:09.557432 10, 0x0, sum = 2
1610 00:22:09.557486 11, 0x0, sum = 3
1611 00:22:09.557539 12, 0x0, sum = 4
1612 00:22:09.557593 best_step = 10
1613 00:22:09.557645
1614 00:22:09.557697 ==
1615 00:22:09.557750 Dram Type= 6, Freq= 0, CH_1, rank 0
1616 00:22:09.557803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1617 00:22:09.557856 ==
1618 00:22:09.557908 RX Vref Scan: 1
1619 00:22:09.557961
1620 00:22:09.558013 Set Vref Range= 32 -> 127
1621 00:22:09.558066
1622 00:22:09.558118 RX Vref 32 -> 127, step: 1
1623 00:22:09.558171
1624 00:22:09.558223 RX Delay -95 -> 252, step: 8
1625 00:22:09.558275
1626 00:22:09.558327 Set Vref, RX VrefLevel [Byte0]: 32
1627 00:22:09.558380 [Byte1]: 32
1628 00:22:09.558432
1629 00:22:09.558484 Set Vref, RX VrefLevel [Byte0]: 33
1630 00:22:09.558536 [Byte1]: 33
1631 00:22:09.558589
1632 00:22:09.558641 Set Vref, RX VrefLevel [Byte0]: 34
1633 00:22:09.558694 [Byte1]: 34
1634 00:22:09.558746
1635 00:22:09.558798 Set Vref, RX VrefLevel [Byte0]: 35
1636 00:22:09.558851 [Byte1]: 35
1637 00:22:09.558903
1638 00:22:09.558956 Set Vref, RX VrefLevel [Byte0]: 36
1639 00:22:09.559007 [Byte1]: 36
1640 00:22:09.559060
1641 00:22:09.559112 Set Vref, RX VrefLevel [Byte0]: 37
1642 00:22:09.559165 [Byte1]: 37
1643 00:22:09.559217
1644 00:22:09.559269 Set Vref, RX VrefLevel [Byte0]: 38
1645 00:22:09.559322 [Byte1]: 38
1646 00:22:09.559375
1647 00:22:09.559428 Set Vref, RX VrefLevel [Byte0]: 39
1648 00:22:09.559480 [Byte1]: 39
1649 00:22:09.559532
1650 00:22:09.559584 Set Vref, RX VrefLevel [Byte0]: 40
1651 00:22:09.559640 [Byte1]: 40
1652 00:22:09.559692
1653 00:22:09.559745 Set Vref, RX VrefLevel [Byte0]: 41
1654 00:22:09.559797 [Byte1]: 41
1655 00:22:09.559850
1656 00:22:09.559902 Set Vref, RX VrefLevel [Byte0]: 42
1657 00:22:09.559954 [Byte1]: 42
1658 00:22:09.560006
1659 00:22:09.560058 Set Vref, RX VrefLevel [Byte0]: 43
1660 00:22:09.560111 [Byte1]: 43
1661 00:22:09.560163
1662 00:22:09.560215 Set Vref, RX VrefLevel [Byte0]: 44
1663 00:22:09.560268 [Byte1]: 44
1664 00:22:09.560320
1665 00:22:09.560372 Set Vref, RX VrefLevel [Byte0]: 45
1666 00:22:09.560424 [Byte1]: 45
1667 00:22:09.560476
1668 00:22:09.560528 Set Vref, RX VrefLevel [Byte0]: 46
1669 00:22:09.560580 [Byte1]: 46
1670 00:22:09.560633
1671 00:22:09.560685 Set Vref, RX VrefLevel [Byte0]: 47
1672 00:22:09.560737 [Byte1]: 47
1673 00:22:09.560789
1674 00:22:09.560842 Set Vref, RX VrefLevel [Byte0]: 48
1675 00:22:09.560894 [Byte1]: 48
1676 00:22:09.560947
1677 00:22:09.560998 Set Vref, RX VrefLevel [Byte0]: 49
1678 00:22:09.561051 [Byte1]: 49
1679 00:22:09.561103
1680 00:22:09.561155 Set Vref, RX VrefLevel [Byte0]: 50
1681 00:22:09.561207 [Byte1]: 50
1682 00:22:09.561264
1683 00:22:09.561317 Set Vref, RX VrefLevel [Byte0]: 51
1684 00:22:09.561369 [Byte1]: 51
1685 00:22:09.561422
1686 00:22:09.561475 Set Vref, RX VrefLevel [Byte0]: 52
1687 00:22:09.561527 [Byte1]: 52
1688 00:22:09.561581
1689 00:22:09.561634 Set Vref, RX VrefLevel [Byte0]: 53
1690 00:22:09.561687 [Byte1]: 53
1691 00:22:09.561739
1692 00:22:09.561792 Set Vref, RX VrefLevel [Byte0]: 54
1693 00:22:09.561844 [Byte1]: 54
1694 00:22:09.561896
1695 00:22:09.561948 Set Vref, RX VrefLevel [Byte0]: 55
1696 00:22:09.562000 [Byte1]: 55
1697 00:22:09.562052
1698 00:22:09.562318 Set Vref, RX VrefLevel [Byte0]: 56
1699 00:22:09.562378 [Byte1]: 56
1700 00:22:09.562433
1701 00:22:09.562486 Set Vref, RX VrefLevel [Byte0]: 57
1702 00:22:09.562540 [Byte1]: 57
1703 00:22:09.562593
1704 00:22:09.562646 Set Vref, RX VrefLevel [Byte0]: 58
1705 00:22:09.562699 [Byte1]: 58
1706 00:22:09.562753
1707 00:22:09.562805 Set Vref, RX VrefLevel [Byte0]: 59
1708 00:22:09.562858 [Byte1]: 59
1709 00:22:09.562911
1710 00:22:09.562963 Set Vref, RX VrefLevel [Byte0]: 60
1711 00:22:09.563017 [Byte1]: 60
1712 00:22:09.563069
1713 00:22:09.563121 Set Vref, RX VrefLevel [Byte0]: 61
1714 00:22:09.563173 [Byte1]: 61
1715 00:22:09.563226
1716 00:22:09.563278 Set Vref, RX VrefLevel [Byte0]: 62
1717 00:22:09.563331 [Byte1]: 62
1718 00:22:09.563383
1719 00:22:09.563435 Set Vref, RX VrefLevel [Byte0]: 63
1720 00:22:09.563488 [Byte1]: 63
1721 00:22:09.563540
1722 00:22:09.563592 Set Vref, RX VrefLevel [Byte0]: 64
1723 00:22:09.563645 [Byte1]: 64
1724 00:22:09.563697
1725 00:22:09.563749 Set Vref, RX VrefLevel [Byte0]: 65
1726 00:22:09.563802 [Byte1]: 65
1727 00:22:09.563854
1728 00:22:09.563906 Set Vref, RX VrefLevel [Byte0]: 66
1729 00:22:09.563959 [Byte1]: 66
1730 00:22:09.564013
1731 00:22:09.564066 Set Vref, RX VrefLevel [Byte0]: 67
1732 00:22:09.564118 [Byte1]: 67
1733 00:22:09.564170
1734 00:22:09.564222 Set Vref, RX VrefLevel [Byte0]: 68
1735 00:22:09.564274 [Byte1]: 68
1736 00:22:09.564327
1737 00:22:09.564379 Set Vref, RX VrefLevel [Byte0]: 69
1738 00:22:09.564431 [Byte1]: 69
1739 00:22:09.564483
1740 00:22:09.564535 Set Vref, RX VrefLevel [Byte0]: 70
1741 00:22:09.564588 [Byte1]: 70
1742 00:22:09.564641
1743 00:22:09.564693 Set Vref, RX VrefLevel [Byte0]: 71
1744 00:22:09.564746 [Byte1]: 71
1745 00:22:09.564799
1746 00:22:09.564851 Set Vref, RX VrefLevel [Byte0]: 72
1747 00:22:09.564903 [Byte1]: 72
1748 00:22:09.564956
1749 00:22:09.565008 Set Vref, RX VrefLevel [Byte0]: 73
1750 00:22:09.565060 [Byte1]: 73
1751 00:22:09.565113
1752 00:22:09.565165 Set Vref, RX VrefLevel [Byte0]: 74
1753 00:22:09.565218 [Byte1]: 74
1754 00:22:09.565280
1755 00:22:09.565334 Set Vref, RX VrefLevel [Byte0]: 75
1756 00:22:09.565387 [Byte1]: 75
1757 00:22:09.565439
1758 00:22:09.565491 Final RX Vref Byte 0 = 59 to rank0
1759 00:22:09.565544 Final RX Vref Byte 1 = 53 to rank0
1760 00:22:09.565597 Final RX Vref Byte 0 = 59 to rank1
1761 00:22:09.565651 Final RX Vref Byte 1 = 53 to rank1==
1762 00:22:09.565704 Dram Type= 6, Freq= 0, CH_1, rank 0
1763 00:22:09.565756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1764 00:22:09.565809 ==
1765 00:22:09.565863 DQS Delay:
1766 00:22:09.565916 DQS0 = 0, DQS1 = 0
1767 00:22:09.565968 DQM Delay:
1768 00:22:09.566021 DQM0 = 86, DQM1 = 80
1769 00:22:09.566074 DQ Delay:
1770 00:22:09.566127 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1771 00:22:09.566180 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =80
1772 00:22:09.566233 DQ8 =64, DQ9 =72, DQ10 =80, DQ11 =76
1773 00:22:09.566286 DQ12 =88, DQ13 =88, DQ14 =84, DQ15 =88
1774 00:22:09.566339
1775 00:22:09.566392
1776 00:22:09.566444 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a2e, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 403 ps
1777 00:22:09.566498 CH1 RK0: MR19=606, MR18=1A2E
1778 00:22:09.566551 CH1_RK0: MR19=0x606, MR18=0x1A2E, DQSOSC=398, MR23=63, INC=93, DEC=62
1779 00:22:09.566604
1780 00:22:09.566657 ----->DramcWriteLeveling(PI) begin...
1781 00:22:09.566710 ==
1782 00:22:09.566763 Dram Type= 6, Freq= 0, CH_1, rank 1
1783 00:22:09.566816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1784 00:22:09.566869 ==
1785 00:22:09.566921 Write leveling (Byte 0): 26 => 26
1786 00:22:09.566975 Write leveling (Byte 1): 27 => 27
1787 00:22:09.567028 DramcWriteLeveling(PI) end<-----
1788 00:22:09.567080
1789 00:22:09.567132 ==
1790 00:22:09.567184 Dram Type= 6, Freq= 0, CH_1, rank 1
1791 00:22:09.567237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1792 00:22:09.567290 ==
1793 00:22:09.567342 [Gating] SW mode calibration
1794 00:22:09.567395 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1795 00:22:09.567448 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1796 00:22:09.567502 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1797 00:22:09.567555 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1798 00:22:09.567607 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1799 00:22:09.567660 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1800 00:22:09.567713 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1801 00:22:09.567766 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1802 00:22:09.567818 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1803 00:22:09.567874 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1804 00:22:09.567927 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1805 00:22:09.567980 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 00:22:09.568033 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 00:22:09.568085 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 00:22:09.568138 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 00:22:09.568192 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 00:22:09.568245 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 00:22:09.568297 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 00:22:09.568351 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1813 00:22:09.568404 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1814 00:22:09.568456 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 00:22:09.568509 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 00:22:09.568562 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 00:22:09.568615 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 00:22:09.568668 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 00:22:09.568721 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 00:22:09.568773 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 00:22:09.568826 0 9 4 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
1822 00:22:09.568879 0 9 8 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
1823 00:22:09.568932 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1824 00:22:09.569195 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1825 00:22:09.569255 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1826 00:22:09.569337 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1827 00:22:09.569445 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1828 00:22:09.569553 0 10 0 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
1829 00:22:09.569659 0 10 4 | B1->B0 | 3333 2323 | 1 1 | (1 1) (1 0)
1830 00:22:09.569762 0 10 8 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
1831 00:22:09.569855 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 00:22:09.569930 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 00:22:09.569988 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 00:22:09.570042 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 00:22:09.570095 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 00:22:09.570147 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 00:22:09.570200 0 11 4 | B1->B0 | 2929 3a3a | 0 0 | (0 0) (0 0)
1838 00:22:09.570253 0 11 8 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
1839 00:22:09.570305 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1840 00:22:09.570358 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1841 00:22:09.570416 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1842 00:22:09.570472 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1843 00:22:09.570525 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1844 00:22:09.570578 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1845 00:22:09.570631 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1846 00:22:09.570687 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1847 00:22:09.570740 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1848 00:22:09.570793 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1849 00:22:09.570844 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1850 00:22:09.570897 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1851 00:22:09.570950 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1852 00:22:09.571003 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1853 00:22:09.571055 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 00:22:09.571107 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 00:22:09.571160 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 00:22:09.571212 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 00:22:09.571264 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 00:22:09.571317 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 00:22:09.571369 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 00:22:09.571422 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1861 00:22:09.571475 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1862 00:22:09.571528 Total UI for P1: 0, mck2ui 16
1863 00:22:09.571581 best dqsien dly found for B0: ( 0, 14, 0)
1864 00:22:09.571635 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1865 00:22:09.571688 Total UI for P1: 0, mck2ui 16
1866 00:22:09.571740 best dqsien dly found for B1: ( 0, 14, 4)
1867 00:22:09.571793 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1868 00:22:09.571846 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1869 00:22:09.571899
1870 00:22:09.571951 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1871 00:22:09.572005 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1872 00:22:09.572057 [Gating] SW calibration Done
1873 00:22:09.572109 ==
1874 00:22:09.572162 Dram Type= 6, Freq= 0, CH_1, rank 1
1875 00:22:09.572215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1876 00:22:09.572268 ==
1877 00:22:09.572321 RX Vref Scan: 0
1878 00:22:09.572375
1879 00:22:09.572427 RX Vref 0 -> 0, step: 1
1880 00:22:09.572480
1881 00:22:09.572532 RX Delay -130 -> 252, step: 16
1882 00:22:09.572585 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1883 00:22:09.572638 iDelay=206, Bit 1, Center 77 (-50 ~ 205) 256
1884 00:22:09.572691 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1885 00:22:09.572743 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1886 00:22:09.572796 iDelay=206, Bit 4, Center 77 (-50 ~ 205) 256
1887 00:22:09.572849 iDelay=206, Bit 5, Center 85 (-34 ~ 205) 240
1888 00:22:09.572901 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1889 00:22:09.572954 iDelay=206, Bit 7, Center 77 (-50 ~ 205) 256
1890 00:22:09.573007 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1891 00:22:09.573059 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1892 00:22:09.573111 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1893 00:22:09.573164 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1894 00:22:09.573216 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1895 00:22:09.573289 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1896 00:22:09.573348 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1897 00:22:09.573401 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1898 00:22:09.573454 ==
1899 00:22:09.573507 Dram Type= 6, Freq= 0, CH_1, rank 1
1900 00:22:09.573560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1901 00:22:09.573619 ==
1902 00:22:09.573673 DQS Delay:
1903 00:22:09.573725 DQS0 = 0, DQS1 = 0
1904 00:22:09.573779 DQM Delay:
1905 00:22:09.573832 DQM0 = 79, DQM1 = 79
1906 00:22:09.573885 DQ Delay:
1907 00:22:09.573938 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1908 00:22:09.573991 DQ4 =77, DQ5 =85, DQ6 =85, DQ7 =77
1909 00:22:09.574043 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1910 00:22:09.574096 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1911 00:22:09.574149
1912 00:22:09.574202
1913 00:22:09.574255 ==
1914 00:22:09.574307 Dram Type= 6, Freq= 0, CH_1, rank 1
1915 00:22:09.574361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1916 00:22:09.574414 ==
1917 00:22:09.574467
1918 00:22:09.779623
1919 00:22:09.779764 TX Vref Scan disable
1920 00:22:09.779835 == TX Byte 0 ==
1921 00:22:09.779894 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1922 00:22:09.779953 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1923 00:22:09.780009 == TX Byte 1 ==
1924 00:22:09.780065 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1925 00:22:09.780120 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1926 00:22:09.780173 ==
1927 00:22:09.780228 Dram Type= 6, Freq= 0, CH_1, rank 1
1928 00:22:09.780281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1929 00:22:09.780335 ==
1930 00:22:09.780388 TX Vref=22, minBit 1, minWin=27, winSum=448
1931 00:22:09.780658 TX Vref=24, minBit 1, minWin=27, winSum=450
1932 00:22:09.780741 TX Vref=26, minBit 1, minWin=27, winSum=453
1933 00:22:09.780864 TX Vref=28, minBit 1, minWin=27, winSum=455
1934 00:22:09.780959 TX Vref=30, minBit 0, minWin=28, winSum=455
1935 00:22:09.781031 TX Vref=32, minBit 5, minWin=27, winSum=454
1936 00:22:09.781087 [TxChooseVref] Worse bit 0, Min win 28, Win sum 455, Final Vref 30
1937 00:22:09.781142
1938 00:22:09.781196 Final TX Range 1 Vref 30
1939 00:22:09.781249
1940 00:22:09.781357 ==
1941 00:22:09.781440 Dram Type= 6, Freq= 0, CH_1, rank 1
1942 00:22:09.781522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1943 00:22:09.781603 ==
1944 00:22:09.781684
1945 00:22:09.781764
1946 00:22:09.781844 TX Vref Scan disable
1947 00:22:09.781924 == TX Byte 0 ==
1948 00:22:09.782005 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1949 00:22:09.782088 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1950 00:22:09.782151 == TX Byte 1 ==
1951 00:22:09.782203 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1952 00:22:09.782256 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1953 00:22:09.782309
1954 00:22:09.782361 [DATLAT]
1955 00:22:09.782413 Freq=800, CH1 RK1
1956 00:22:09.782465
1957 00:22:09.782517 DATLAT Default: 0xa
1958 00:22:09.782569 0, 0xFFFF, sum = 0
1959 00:22:09.782643 1, 0xFFFF, sum = 0
1960 00:22:09.782710 2, 0xFFFF, sum = 0
1961 00:22:09.782763 3, 0xFFFF, sum = 0
1962 00:22:09.782815 4, 0xFFFF, sum = 0
1963 00:22:09.782868 5, 0xFFFF, sum = 0
1964 00:22:09.782920 6, 0xFFFF, sum = 0
1965 00:22:09.782973 7, 0xFFFF, sum = 0
1966 00:22:09.783043 8, 0xFFFF, sum = 0
1967 00:22:09.783109 9, 0x0, sum = 1
1968 00:22:09.783160 10, 0x0, sum = 2
1969 00:22:09.783212 11, 0x0, sum = 3
1970 00:22:09.783265 12, 0x0, sum = 4
1971 00:22:09.783317 best_step = 10
1972 00:22:09.783369
1973 00:22:09.783420 ==
1974 00:22:09.783472 Dram Type= 6, Freq= 0, CH_1, rank 1
1975 00:22:09.783523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1976 00:22:09.783575 ==
1977 00:22:09.783626 RX Vref Scan: 0
1978 00:22:09.783677
1979 00:22:09.783728 RX Vref 0 -> 0, step: 1
1980 00:22:09.783779
1981 00:22:09.783830 RX Delay -95 -> 252, step: 8
1982 00:22:09.783882 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
1983 00:22:09.783958 iDelay=209, Bit 1, Center 80 (-39 ~ 200) 240
1984 00:22:09.784023 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1985 00:22:09.784075 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1986 00:22:09.784127 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1987 00:22:09.784178 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
1988 00:22:09.784229 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1989 00:22:09.784280 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
1990 00:22:09.784332 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1991 00:22:09.784390 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
1992 00:22:09.784448 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1993 00:22:09.784500 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1994 00:22:09.784552 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
1995 00:22:09.784603 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
1996 00:22:09.784655 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1997 00:22:09.784707 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1998 00:22:09.784758 ==
1999 00:22:09.784810 Dram Type= 6, Freq= 0, CH_1, rank 1
2000 00:22:09.784862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2001 00:22:09.784932 ==
2002 00:22:09.784997 DQS Delay:
2003 00:22:09.785048 DQS0 = 0, DQS1 = 0
2004 00:22:09.785100 DQM Delay:
2005 00:22:09.785151 DQM0 = 85, DQM1 = 81
2006 00:22:09.785203 DQ Delay:
2007 00:22:09.785254 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =80
2008 00:22:09.785348 DQ4 =84, DQ5 =96, DQ6 =92, DQ7 =84
2009 00:22:09.785400 DQ8 =68, DQ9 =72, DQ10 =80, DQ11 =76
2010 00:22:09.785452 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
2011 00:22:09.785504
2012 00:22:09.785555
2013 00:22:09.785606 [DQSOSCAuto] RK1, (LSB)MR18= 0x2643, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 400 ps
2014 00:22:09.785660 CH1 RK1: MR19=606, MR18=2643
2015 00:22:09.785712 CH1_RK1: MR19=0x606, MR18=0x2643, DQSOSC=393, MR23=63, INC=95, DEC=63
2016 00:22:09.785765 [RxdqsGatingPostProcess] freq 800
2017 00:22:09.785818 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2018 00:22:09.785870 Pre-setting of DQS Precalculation
2019 00:22:09.785922 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2020 00:22:09.785974 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2021 00:22:09.786027 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2022 00:22:09.786079
2023 00:22:09.786131
2024 00:22:09.786182 [Calibration Summary] 1600 Mbps
2025 00:22:09.786234 CH 0, Rank 0
2026 00:22:09.786286 SW Impedance : PASS
2027 00:22:09.786338 DUTY Scan : NO K
2028 00:22:09.786390 ZQ Calibration : PASS
2029 00:22:09.786442 Jitter Meter : NO K
2030 00:22:09.786494 CBT Training : PASS
2031 00:22:09.786546 Write leveling : PASS
2032 00:22:09.786598 RX DQS gating : PASS
2033 00:22:09.786649 RX DQ/DQS(RDDQC) : PASS
2034 00:22:09.786700 TX DQ/DQS : PASS
2035 00:22:09.786753 RX DATLAT : PASS
2036 00:22:09.786805 RX DQ/DQS(Engine): PASS
2037 00:22:09.786856 TX OE : NO K
2038 00:22:09.786908 All Pass.
2039 00:22:09.786960
2040 00:22:09.787012 CH 0, Rank 1
2041 00:22:09.787064 SW Impedance : PASS
2042 00:22:09.787116 DUTY Scan : NO K
2043 00:22:09.787168 ZQ Calibration : PASS
2044 00:22:09.787219 Jitter Meter : NO K
2045 00:22:09.787271 CBT Training : PASS
2046 00:22:09.787323 Write leveling : PASS
2047 00:22:09.787375 RX DQS gating : PASS
2048 00:22:09.787426 RX DQ/DQS(RDDQC) : PASS
2049 00:22:09.787478 TX DQ/DQS : PASS
2050 00:22:09.787531 RX DATLAT : PASS
2051 00:22:09.787582 RX DQ/DQS(Engine): PASS
2052 00:22:09.787634 TX OE : NO K
2053 00:22:09.787686 All Pass.
2054 00:22:09.787737
2055 00:22:09.787789 CH 1, Rank 0
2056 00:22:09.787840 SW Impedance : PASS
2057 00:22:09.787950 DUTY Scan : NO K
2058 00:22:09.788002 ZQ Calibration : PASS
2059 00:22:09.788054 Jitter Meter : NO K
2060 00:22:09.788119 CBT Training : PASS
2061 00:22:09.788172 Write leveling : PASS
2062 00:22:09.788225 RX DQS gating : PASS
2063 00:22:09.788278 RX DQ/DQS(RDDQC) : PASS
2064 00:22:09.788331 TX DQ/DQS : PASS
2065 00:22:09.788385 RX DATLAT : PASS
2066 00:22:09.788439 RX DQ/DQS(Engine): PASS
2067 00:22:09.788506 TX OE : NO K
2068 00:22:09.788611 All Pass.
2069 00:22:09.788683
2070 00:22:09.788751 CH 1, Rank 1
2071 00:22:09.788804 SW Impedance : PASS
2072 00:22:09.788856 DUTY Scan : NO K
2073 00:22:09.788909 ZQ Calibration : PASS
2074 00:22:09.788961 Jitter Meter : NO K
2075 00:22:09.789013 CBT Training : PASS
2076 00:22:09.789066 Write leveling : PASS
2077 00:22:09.789118 RX DQS gating : PASS
2078 00:22:09.789170 RX DQ/DQS(RDDQC) : PASS
2079 00:22:09.789222 TX DQ/DQS : PASS
2080 00:22:09.789300 RX DATLAT : PASS
2081 00:22:09.789384 RX DQ/DQS(Engine): PASS
2082 00:22:09.789451 TX OE : NO K
2083 00:22:09.789719 All Pass.
2084 00:22:09.789778
2085 00:22:09.789837 DramC Write-DBI off
2086 00:22:09.789906 PER_BANK_REFRESH: Hybrid Mode
2087 00:22:09.789960 TX_TRACKING: ON
2088 00:22:09.790013 [GetDramInforAfterCalByMRR] Vendor 6.
2089 00:22:09.790067 [GetDramInforAfterCalByMRR] Revision 606.
2090 00:22:09.790121 [GetDramInforAfterCalByMRR] Revision 2 0.
2091 00:22:09.790177 MR0 0x3b3b
2092 00:22:09.790300 MR8 0x5151
2093 00:22:09.790386 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2094 00:22:09.790468
2095 00:22:09.790549 MR0 0x3b3b
2096 00:22:09.790630 MR8 0x5151
2097 00:22:09.790711 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2098 00:22:09.790792
2099 00:22:09.790874 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2100 00:22:09.790957 [FAST_K] Save calibration result to emmc
2101 00:22:09.791039 [FAST_K] Save calibration result to emmc
2102 00:22:09.791123 dram_init: config_dvfs: 1
2103 00:22:09.791206 dramc_set_vcore_voltage set vcore to 662500
2104 00:22:09.791289 Read voltage for 1200, 2
2105 00:22:09.791409 Vio18 = 0
2106 00:22:09.791490 Vcore = 662500
2107 00:22:09.791571 Vdram = 0
2108 00:22:09.791651 Vddq = 0
2109 00:22:09.791731 Vmddr = 0
2110 00:22:09.791813 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2111 00:22:09.791895 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2112 00:22:09.791977 MEM_TYPE=3, freq_sel=15
2113 00:22:09.792058 sv_algorithm_assistance_LP4_1600
2114 00:22:09.792155 ============ PULL DRAM RESETB DOWN ============
2115 00:22:09.792240 ========== PULL DRAM RESETB DOWN end =========
2116 00:22:09.792341 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2117 00:22:09.792422 ===================================
2118 00:22:09.792504 LPDDR4 DRAM CONFIGURATION
2119 00:22:09.792585 ===================================
2120 00:22:09.792666 EX_ROW_EN[0] = 0x0
2121 00:22:09.792748 EX_ROW_EN[1] = 0x0
2122 00:22:09.792828 LP4Y_EN = 0x0
2123 00:22:09.792909 WORK_FSP = 0x0
2124 00:22:09.792990 WL = 0x4
2125 00:22:09.793070 RL = 0x4
2126 00:22:09.793151 BL = 0x2
2127 00:22:09.793232 RPST = 0x0
2128 00:22:09.793382 RD_PRE = 0x0
2129 00:22:09.793465 WR_PRE = 0x1
2130 00:22:09.793546 WR_PST = 0x0
2131 00:22:09.793627 DBI_WR = 0x0
2132 00:22:09.793708 DBI_RD = 0x0
2133 00:22:09.793789 OTF = 0x1
2134 00:22:09.793870 ===================================
2135 00:22:09.793952 ===================================
2136 00:22:09.794033 ANA top config
2137 00:22:09.794114 ===================================
2138 00:22:09.794196 DLL_ASYNC_EN = 0
2139 00:22:09.794276 ALL_SLAVE_EN = 0
2140 00:22:09.794353 NEW_RANK_MODE = 1
2141 00:22:09.794408 DLL_IDLE_MODE = 1
2142 00:22:09.794461 LP45_APHY_COMB_EN = 1
2143 00:22:09.794514 TX_ODT_DIS = 1
2144 00:22:09.794566 NEW_8X_MODE = 1
2145 00:22:09.794619 ===================================
2146 00:22:09.794672 ===================================
2147 00:22:09.794725 data_rate = 2400
2148 00:22:09.794777 CKR = 1
2149 00:22:09.794829 DQ_P2S_RATIO = 8
2150 00:22:09.794906 ===================================
2151 00:22:09.794962 CA_P2S_RATIO = 8
2152 00:22:09.795015 DQ_CA_OPEN = 0
2153 00:22:09.795067 DQ_SEMI_OPEN = 0
2154 00:22:09.795167 CA_SEMI_OPEN = 0
2155 00:22:09.795353 CA_FULL_RATE = 0
2156 00:22:09.795456 DQ_CKDIV4_EN = 0
2157 00:22:09.795540 CA_CKDIV4_EN = 0
2158 00:22:09.795596 CA_PREDIV_EN = 0
2159 00:22:09.795652 PH8_DLY = 17
2160 00:22:09.795718 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2161 00:22:09.795774 DQ_AAMCK_DIV = 4
2162 00:22:09.795827 CA_AAMCK_DIV = 4
2163 00:22:09.795880 CA_ADMCK_DIV = 4
2164 00:22:09.795931 DQ_TRACK_CA_EN = 0
2165 00:22:09.795984 CA_PICK = 1200
2166 00:22:09.796036 CA_MCKIO = 1200
2167 00:22:09.796089 MCKIO_SEMI = 0
2168 00:22:09.796160 PLL_FREQ = 2366
2169 00:22:09.796214 DQ_UI_PI_RATIO = 32
2170 00:22:09.796266 CA_UI_PI_RATIO = 0
2171 00:22:09.796319 ===================================
2172 00:22:09.796371 ===================================
2173 00:22:09.796423 memory_type:LPDDR4
2174 00:22:09.796475 GP_NUM : 10
2175 00:22:09.796527 SRAM_EN : 1
2176 00:22:09.796580 MD32_EN : 0
2177 00:22:09.796631 ===================================
2178 00:22:09.796684 [ANA_INIT] >>>>>>>>>>>>>>
2179 00:22:09.796736 <<<<<< [CONFIGURE PHASE]: ANA_TX
2180 00:22:09.796789 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2181 00:22:09.796841 ===================================
2182 00:22:09.796893 data_rate = 2400,PCW = 0X5b00
2183 00:22:09.796945 ===================================
2184 00:22:09.796997 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2185 00:22:09.797050 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2186 00:22:09.797102 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2187 00:22:09.797155 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2188 00:22:09.797207 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2189 00:22:09.797284 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2190 00:22:09.797353 [ANA_INIT] flow start
2191 00:22:09.797406 [ANA_INIT] PLL >>>>>>>>
2192 00:22:09.797458 [ANA_INIT] PLL <<<<<<<<
2193 00:22:09.797510 [ANA_INIT] MIDPI >>>>>>>>
2194 00:22:09.797562 [ANA_INIT] MIDPI <<<<<<<<
2195 00:22:09.797614 [ANA_INIT] DLL >>>>>>>>
2196 00:22:09.797670 [ANA_INIT] DLL <<<<<<<<
2197 00:22:09.797723 [ANA_INIT] flow end
2198 00:22:09.797775 ============ LP4 DIFF to SE enter ============
2199 00:22:09.797827 ============ LP4 DIFF to SE exit ============
2200 00:22:09.797880 [ANA_INIT] <<<<<<<<<<<<<
2201 00:22:09.797932 [Flow] Enable top DCM control >>>>>
2202 00:22:09.797984 [Flow] Enable top DCM control <<<<<
2203 00:22:09.798036 Enable DLL master slave shuffle
2204 00:22:09.798088 ==============================================================
2205 00:22:09.798140 Gating Mode config
2206 00:22:09.798192 ==============================================================
2207 00:22:09.798245 Config description:
2208 00:22:09.798297 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2209 00:22:09.798587 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2210 00:22:09.798695 SELPH_MODE 0: By rank 1: By Phase
2211 00:22:09.798817 ==============================================================
2212 00:22:09.798924 GAT_TRACK_EN = 1
2213 00:22:09.799058 RX_GATING_MODE = 2
2214 00:22:09.799148 RX_GATING_TRACK_MODE = 2
2215 00:22:09.799234 SELPH_MODE = 1
2216 00:22:09.799316 PICG_EARLY_EN = 1
2217 00:22:09.799397 VALID_LAT_VALUE = 1
2218 00:22:09.799479 ==============================================================
2219 00:22:09.799562 Enter into Gating configuration >>>>
2220 00:22:09.799643 Exit from Gating configuration <<<<
2221 00:22:09.799724 Enter into DVFS_PRE_config >>>>>
2222 00:22:09.799808 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2223 00:22:09.799891 Exit from DVFS_PRE_config <<<<<
2224 00:22:09.799972 Enter into PICG configuration >>>>
2225 00:22:09.800053 Exit from PICG configuration <<<<
2226 00:22:09.800135 [RX_INPUT] configuration >>>>>
2227 00:22:09.800203 [RX_INPUT] configuration <<<<<
2228 00:22:09.800257 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2229 00:22:09.800317 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2230 00:22:09.800375 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2231 00:22:09.800428 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2232 00:22:09.800482 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2233 00:22:09.800534 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2234 00:22:09.800587 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2235 00:22:09.800639 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2236 00:22:09.800696 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2237 00:22:09.800752 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2238 00:22:09.800834 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2239 00:22:09.800920 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2240 00:22:09.801006 ===================================
2241 00:22:09.801088 LPDDR4 DRAM CONFIGURATION
2242 00:22:09.801178 ===================================
2243 00:22:09.801297 EX_ROW_EN[0] = 0x0
2244 00:22:09.801399 EX_ROW_EN[1] = 0x0
2245 00:22:09.801481 LP4Y_EN = 0x0
2246 00:22:09.801562 WORK_FSP = 0x0
2247 00:22:09.801643 WL = 0x4
2248 00:22:09.801724 RL = 0x4
2249 00:22:09.801807 BL = 0x2
2250 00:22:09.801863 RPST = 0x0
2251 00:22:09.801916 RD_PRE = 0x0
2252 00:22:09.801978 WR_PRE = 0x1
2253 00:22:09.802031 WR_PST = 0x0
2254 00:22:09.802083 DBI_WR = 0x0
2255 00:22:09.802135 DBI_RD = 0x0
2256 00:22:09.802187 OTF = 0x1
2257 00:22:09.802239 ===================================
2258 00:22:09.802292 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2259 00:22:09.802345 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2260 00:22:09.802397 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2261 00:22:09.802449 ===================================
2262 00:22:09.802502 LPDDR4 DRAM CONFIGURATION
2263 00:22:09.802554 ===================================
2264 00:22:09.802607 EX_ROW_EN[0] = 0x10
2265 00:22:09.802659 EX_ROW_EN[1] = 0x0
2266 00:22:09.802711 LP4Y_EN = 0x0
2267 00:22:09.802763 WORK_FSP = 0x0
2268 00:22:09.802830 WL = 0x4
2269 00:22:09.802896 RL = 0x4
2270 00:22:09.802948 BL = 0x2
2271 00:22:09.802999 RPST = 0x0
2272 00:22:09.803051 RD_PRE = 0x0
2273 00:22:09.803103 WR_PRE = 0x1
2274 00:22:09.803154 WR_PST = 0x0
2275 00:22:09.803206 DBI_WR = 0x0
2276 00:22:09.803256 DBI_RD = 0x0
2277 00:22:09.803308 OTF = 0x1
2278 00:22:09.803360 ===================================
2279 00:22:09.803412 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2280 00:22:09.803464 ==
2281 00:22:09.803517 Dram Type= 6, Freq= 0, CH_0, rank 0
2282 00:22:09.803569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2283 00:22:09.803622 ==
2284 00:22:09.803674 [Duty_Offset_Calibration]
2285 00:22:09.803726 B0:2 B1:0 CA:4
2286 00:22:09.803778
2287 00:22:09.803830 [DutyScan_Calibration_Flow] k_type=0
2288 00:22:09.803882
2289 00:22:09.803934 ==CLK 0==
2290 00:22:09.803986 Final CLK duty delay cell = 0
2291 00:22:09.804038 [0] MAX Duty = 5156%(X100), DQS PI = 14
2292 00:22:09.804099 [0] MIN Duty = 4969%(X100), DQS PI = 8
2293 00:22:09.804154 [0] AVG Duty = 5062%(X100)
2294 00:22:09.804206
2295 00:22:09.804258 CH0 CLK Duty spec in!! Max-Min= 187%
2296 00:22:09.804309 [DutyScan_Calibration_Flow] ====Done====
2297 00:22:09.804368
2298 00:22:09.804420 [DutyScan_Calibration_Flow] k_type=1
2299 00:22:09.804473
2300 00:22:09.804524 ==DQS 0 ==
2301 00:22:09.804576 Final DQS duty delay cell = 0
2302 00:22:09.804628 [0] MAX Duty = 5156%(X100), DQS PI = 18
2303 00:22:09.804680 [0] MIN Duty = 5093%(X100), DQS PI = 0
2304 00:22:09.804732 [0] AVG Duty = 5124%(X100)
2305 00:22:09.804784
2306 00:22:09.804835 ==DQS 1 ==
2307 00:22:09.804886 Final DQS duty delay cell = 0
2308 00:22:09.804938 [0] MAX Duty = 5093%(X100), DQS PI = 4
2309 00:22:09.804989 [0] MIN Duty = 4969%(X100), DQS PI = 14
2310 00:22:09.805041 [0] AVG Duty = 5031%(X100)
2311 00:22:09.805092
2312 00:22:09.805143 CH0 DQS 0 Duty spec in!! Max-Min= 63%
2313 00:22:09.805194
2314 00:22:09.805246 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2315 00:22:09.805342 [DutyScan_Calibration_Flow] ====Done====
2316 00:22:09.805394
2317 00:22:09.805446 [DutyScan_Calibration_Flow] k_type=3
2318 00:22:09.805497
2319 00:22:09.805548 ==DQM 0 ==
2320 00:22:09.805600 Final DQM duty delay cell = 0
2321 00:22:09.805653 [0] MAX Duty = 5093%(X100), DQS PI = 20
2322 00:22:09.805705 [0] MIN Duty = 4844%(X100), DQS PI = 50
2323 00:22:09.805761 [0] AVG Duty = 4968%(X100)
2324 00:22:09.805833
2325 00:22:09.805994 ==DQM 1 ==
2326 00:22:09.806098 Final DQM duty delay cell = 0
2327 00:22:09.806179 [0] MAX Duty = 4969%(X100), DQS PI = 4
2328 00:22:09.806243 [0] MIN Duty = 4875%(X100), DQS PI = 12
2329 00:22:09.806331 [0] AVG Duty = 4922%(X100)
2330 00:22:09.806400
2331 00:22:09.806487 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2332 00:22:09.806582
2333 00:22:09.806668 CH0 DQM 1 Duty spec in!! Max-Min= 94%
2334 00:22:09.806751 [DutyScan_Calibration_Flow] ====Done====
2335 00:22:09.806832
2336 00:22:09.806914 [DutyScan_Calibration_Flow] k_type=2
2337 00:22:09.806999
2338 00:22:09.807088 ==DQ 0 ==
2339 00:22:09.807173 Final DQ duty delay cell = 0
2340 00:22:09.807491 [0] MAX Duty = 5125%(X100), DQS PI = 18
2341 00:22:09.807584 [0] MIN Duty = 4938%(X100), DQS PI = 58
2342 00:22:09.807669 [0] AVG Duty = 5031%(X100)
2343 00:22:09.807751
2344 00:22:09.807834 ==DQ 1 ==
2345 00:22:09.807917 Final DQ duty delay cell = 0
2346 00:22:09.808013 [0] MAX Duty = 5125%(X100), DQS PI = 4
2347 00:22:09.808094 [0] MIN Duty = 4938%(X100), DQS PI = 14
2348 00:22:09.808175 [0] AVG Duty = 5031%(X100)
2349 00:22:09.808255
2350 00:22:09.808336 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2351 00:22:09.808416
2352 00:22:09.808497 CH0 DQ 1 Duty spec in!! Max-Min= 187%
2353 00:22:09.808581 [DutyScan_Calibration_Flow] ====Done====
2354 00:22:09.808644 ==
2355 00:22:09.808697 Dram Type= 6, Freq= 0, CH_1, rank 0
2356 00:22:09.808786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2357 00:22:09.808869 ==
2358 00:22:09.808950 [Duty_Offset_Calibration]
2359 00:22:09.809031 B0:0 B1:-1 CA:3
2360 00:22:09.809111
2361 00:22:09.809195 [DutyScan_Calibration_Flow] k_type=0
2362 00:22:09.809322
2363 00:22:09.809378 ==CLK 0==
2364 00:22:09.809432 Final CLK duty delay cell = -4
2365 00:22:09.809484 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2366 00:22:09.809537 [-4] MIN Duty = 4876%(X100), DQS PI = 36
2367 00:22:09.809589 [-4] AVG Duty = 4938%(X100)
2368 00:22:09.809641
2369 00:22:09.809692 CH1 CLK Duty spec in!! Max-Min= 124%
2370 00:22:09.809745 [DutyScan_Calibration_Flow] ====Done====
2371 00:22:09.809797
2372 00:22:09.809849 [DutyScan_Calibration_Flow] k_type=1
2373 00:22:09.809900
2374 00:22:09.809952 ==DQS 0 ==
2375 00:22:09.810004 Final DQS duty delay cell = 0
2376 00:22:09.810056 [0] MAX Duty = 5156%(X100), DQS PI = 18
2377 00:22:09.810108 [0] MIN Duty = 4876%(X100), DQS PI = 38
2378 00:22:09.810159 [0] AVG Duty = 5016%(X100)
2379 00:22:09.810211
2380 00:22:09.810263 ==DQS 1 ==
2381 00:22:09.810316 Final DQS duty delay cell = 0
2382 00:22:09.810368 [0] MAX Duty = 5156%(X100), DQS PI = 8
2383 00:22:09.810420 [0] MIN Duty = 5000%(X100), DQS PI = 26
2384 00:22:09.810472 [0] AVG Duty = 5078%(X100)
2385 00:22:09.810523
2386 00:22:09.810574 CH1 DQS 0 Duty spec in!! Max-Min= 280%
2387 00:22:09.810626
2388 00:22:09.810699 CH1 DQS 1 Duty spec in!! Max-Min= 156%
2389 00:22:09.810892 [DutyScan_Calibration_Flow] ====Done====
2390 00:22:09.810990
2391 00:22:09.811047 [DutyScan_Calibration_Flow] k_type=3
2392 00:22:09.811100
2393 00:22:09.811152 ==DQM 0 ==
2394 00:22:09.811205 Final DQM duty delay cell = 0
2395 00:22:09.811258 [0] MAX Duty = 5031%(X100), DQS PI = 28
2396 00:22:09.811310 [0] MIN Duty = 4782%(X100), DQS PI = 38
2397 00:22:09.811362 [0] AVG Duty = 4906%(X100)
2398 00:22:09.811413
2399 00:22:09.811465 ==DQM 1 ==
2400 00:22:09.811517 Final DQM duty delay cell = 0
2401 00:22:09.811568 [0] MAX Duty = 5000%(X100), DQS PI = 34
2402 00:22:09.811621 [0] MIN Duty = 4813%(X100), DQS PI = 62
2403 00:22:09.811672 [0] AVG Duty = 4906%(X100)
2404 00:22:09.811724
2405 00:22:09.811775 CH1 DQM 0 Duty spec in!! Max-Min= 249%
2406 00:22:09.811827
2407 00:22:09.811878 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2408 00:22:09.811930 [DutyScan_Calibration_Flow] ====Done====
2409 00:22:09.811982
2410 00:22:09.812033 [DutyScan_Calibration_Flow] k_type=2
2411 00:22:09.812085
2412 00:22:09.812139 ==DQ 0 ==
2413 00:22:09.812228 Final DQ duty delay cell = -4
2414 00:22:09.812315 [-4] MAX Duty = 5000%(X100), DQS PI = 14
2415 00:22:09.812383 [-4] MIN Duty = 4844%(X100), DQS PI = 36
2416 00:22:09.812437 [-4] AVG Duty = 4922%(X100)
2417 00:22:09.812489
2418 00:22:09.812541 ==DQ 1 ==
2419 00:22:09.812593 Final DQ duty delay cell = 0
2420 00:22:09.812645 [0] MAX Duty = 5031%(X100), DQS PI = 34
2421 00:22:09.812697 [0] MIN Duty = 4844%(X100), DQS PI = 62
2422 00:22:09.812750 [0] AVG Duty = 4937%(X100)
2423 00:22:09.812828
2424 00:22:09.812915 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2425 00:22:09.812996
2426 00:22:09.813077 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2427 00:22:09.813158 [DutyScan_Calibration_Flow] ====Done====
2428 00:22:09.813238 nWR fixed to 30
2429 00:22:09.813344 [ModeRegInit_LP4] CH0 RK0
2430 00:22:09.813398 [ModeRegInit_LP4] CH0 RK1
2431 00:22:09.813450 [ModeRegInit_LP4] CH1 RK0
2432 00:22:09.813503 [ModeRegInit_LP4] CH1 RK1
2433 00:22:09.813555 match AC timing 7
2434 00:22:09.813607 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2435 00:22:09.813660 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2436 00:22:09.813712 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2437 00:22:09.813764 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2438 00:22:09.813816 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2439 00:22:09.813867 ==
2440 00:22:09.813920 Dram Type= 6, Freq= 0, CH_0, rank 0
2441 00:22:09.813972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2442 00:22:09.814024 ==
2443 00:22:09.814075 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2444 00:22:09.814127 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2445 00:22:09.814180 [CA 0] Center 39 (9~70) winsize 62
2446 00:22:09.814232 [CA 1] Center 39 (9~69) winsize 61
2447 00:22:09.814283 [CA 2] Center 35 (5~66) winsize 62
2448 00:22:09.814335 [CA 3] Center 35 (5~66) winsize 62
2449 00:22:09.814386 [CA 4] Center 33 (3~64) winsize 62
2450 00:22:09.814438 [CA 5] Center 33 (3~63) winsize 61
2451 00:22:09.814490
2452 00:22:09.814541 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2453 00:22:09.814592
2454 00:22:09.814643 [CATrainingPosCal] consider 1 rank data
2455 00:22:09.814695 u2DelayCellTimex100 = 270/100 ps
2456 00:22:09.814747 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2457 00:22:09.814798 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2458 00:22:09.814850 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2459 00:22:09.814902 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2460 00:22:09.814953 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2461 00:22:09.815005 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2462 00:22:09.815057
2463 00:22:09.815109 CA PerBit enable=1, Macro0, CA PI delay=33
2464 00:22:09.815161
2465 00:22:09.815212 [CBTSetCACLKResult] CA Dly = 33
2466 00:22:09.815264 CS Dly: 7 (0~38)
2467 00:22:09.815315 ==
2468 00:22:09.815367 Dram Type= 6, Freq= 0, CH_0, rank 1
2469 00:22:09.815419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2470 00:22:09.815471 ==
2471 00:22:09.815523 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2472 00:22:09.815575 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2473 00:22:09.815627 [CA 0] Center 39 (9~70) winsize 62
2474 00:22:09.815679 [CA 1] Center 39 (9~70) winsize 62
2475 00:22:09.815730 [CA 2] Center 35 (5~66) winsize 62
2476 00:22:09.815782 [CA 3] Center 35 (5~66) winsize 62
2477 00:22:09.815834 [CA 4] Center 34 (4~65) winsize 62
2478 00:22:09.815885 [CA 5] Center 33 (3~64) winsize 62
2479 00:22:09.815936
2480 00:22:09.815988 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2481 00:22:09.816040
2482 00:22:09.816094 [CATrainingPosCal] consider 2 rank data
2483 00:22:09.816146 u2DelayCellTimex100 = 270/100 ps
2484 00:22:09.816416 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2485 00:22:09.816514 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2486 00:22:09.816567 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2487 00:22:09.816619 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2488 00:22:09.816706 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2489 00:22:09.816758 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2490 00:22:09.816810
2491 00:22:09.816861 CA PerBit enable=1, Macro0, CA PI delay=33
2492 00:22:09.816913
2493 00:22:09.816965 [CBTSetCACLKResult] CA Dly = 33
2494 00:22:09.817016 CS Dly: 8 (0~41)
2495 00:22:09.817067
2496 00:22:09.817118 ----->DramcWriteLeveling(PI) begin...
2497 00:22:09.817171 ==
2498 00:22:09.817222 Dram Type= 6, Freq= 0, CH_0, rank 0
2499 00:22:09.817328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2500 00:22:09.817384 ==
2501 00:22:09.817436 Write leveling (Byte 0): 32 => 32
2502 00:22:09.817488 Write leveling (Byte 1): 26 => 26
2503 00:22:09.817541 DramcWriteLeveling(PI) end<-----
2504 00:22:09.817594
2505 00:22:09.817645 ==
2506 00:22:09.817697 Dram Type= 6, Freq= 0, CH_0, rank 0
2507 00:22:09.817748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2508 00:22:09.817800 ==
2509 00:22:09.817851 [Gating] SW mode calibration
2510 00:22:09.817903 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2511 00:22:09.817956 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2512 00:22:09.818008 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2513 00:22:09.818065 0 15 4 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
2514 00:22:09.818118 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2515 00:22:09.818171 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2516 00:22:09.818235 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2517 00:22:09.818467 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2518 00:22:09.818569 0 15 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
2519 00:22:09.818641 0 15 28 | B1->B0 | 3434 2929 | 1 0 | (1 1) (0 1)
2520 00:22:09.818699 1 0 0 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
2521 00:22:09.818752 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2522 00:22:09.818805 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2523 00:22:09.818870 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2524 00:22:09.819075 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2525 00:22:09.819181 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2526 00:22:09.819241 1 0 24 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (0 0)
2527 00:22:09.819295 1 0 28 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
2528 00:22:09.819347 1 1 0 | B1->B0 | 2c2c 4646 | 1 0 | (0 0) (0 0)
2529 00:22:09.819399 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2530 00:22:09.819452 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2531 00:22:09.819507 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2532 00:22:09.819560 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2533 00:22:09.819612 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2534 00:22:09.819665 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2535 00:22:09.819717 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2536 00:22:09.819769 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2537 00:22:09.819821 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2538 00:22:09.819874 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2539 00:22:09.819925 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2540 00:22:09.819977 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2541 00:22:09.820028 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2542 00:22:09.820080 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2543 00:22:09.820132 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2544 00:22:09.820184 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 00:22:09.820235 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 00:22:09.820287 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 00:22:09.820339 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 00:22:09.820391 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 00:22:09.820442 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 00:22:09.820494 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 00:22:09.820546 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
2552 00:22:09.820620 Total UI for P1: 0, mck2ui 16
2553 00:22:09.820700 best dqsien dly found for B0: ( 1, 3, 26)
2554 00:22:09.820766 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2555 00:22:09.820818 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2556 00:22:09.820870 Total UI for P1: 0, mck2ui 16
2557 00:22:09.820922 best dqsien dly found for B1: ( 1, 4, 0)
2558 00:22:09.820980 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2559 00:22:09.821068 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2560 00:22:09.821150
2561 00:22:09.821231 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2562 00:22:09.821335 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2563 00:22:09.821389 [Gating] SW calibration Done
2564 00:22:09.821441 ==
2565 00:22:09.821494 Dram Type= 6, Freq= 0, CH_0, rank 0
2566 00:22:09.821546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2567 00:22:09.821599 ==
2568 00:22:09.821651 RX Vref Scan: 0
2569 00:22:09.821702
2570 00:22:09.821753 RX Vref 0 -> 0, step: 1
2571 00:22:09.821805
2572 00:22:09.821856 RX Delay -40 -> 252, step: 8
2573 00:22:09.821908 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2574 00:22:09.821961 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2575 00:22:09.822013 iDelay=200, Bit 2, Center 115 (48 ~ 183) 136
2576 00:22:09.822066 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2577 00:22:09.822117 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
2578 00:22:09.822169 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2579 00:22:09.822221 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2580 00:22:09.822272 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
2581 00:22:09.822324 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2582 00:22:09.822375 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2583 00:22:09.822427 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2584 00:22:09.822478 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2585 00:22:09.822779 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
2586 00:22:09.822870 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2587 00:22:09.822924 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2588 00:22:09.823007 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2589 00:22:09.823059 ==
2590 00:22:09.823112 Dram Type= 6, Freq= 0, CH_0, rank 0
2591 00:22:09.823226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2592 00:22:09.823380 ==
2593 00:22:09.823516 DQS Delay:
2594 00:22:09.823676 DQS0 = 0, DQS1 = 0
2595 00:22:09.823796 DQM Delay:
2596 00:22:09.823901 DQM0 = 119, DQM1 = 106
2597 00:22:09.824009 DQ Delay:
2598 00:22:09.824099 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2599 00:22:09.824154 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =123
2600 00:22:09.824207 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =103
2601 00:22:09.824259 DQ12 =115, DQ13 =111, DQ14 =119, DQ15 =111
2602 00:22:09.824311
2603 00:22:09.824362
2604 00:22:09.824413 ==
2605 00:22:09.824489 Dram Type= 6, Freq= 0, CH_0, rank 0
2606 00:22:09.824545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2607 00:22:09.824597 ==
2608 00:22:09.824649
2609 00:22:09.824701
2610 00:22:09.824753 TX Vref Scan disable
2611 00:22:09.824805 == TX Byte 0 ==
2612 00:22:09.824856 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2613 00:22:09.824909 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2614 00:22:09.824961 == TX Byte 1 ==
2615 00:22:09.825014 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2616 00:22:09.825066 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2617 00:22:09.825117 ==
2618 00:22:09.825170 Dram Type= 6, Freq= 0, CH_0, rank 0
2619 00:22:09.825222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2620 00:22:09.825334 ==
2621 00:22:09.825419 TX Vref=22, minBit 5, minWin=25, winSum=417
2622 00:22:09.825501 TX Vref=24, minBit 8, minWin=25, winSum=419
2623 00:22:09.825583 TX Vref=26, minBit 1, minWin=26, winSum=426
2624 00:22:09.825665 TX Vref=28, minBit 4, minWin=25, winSum=427
2625 00:22:09.825746 TX Vref=30, minBit 5, minWin=26, winSum=432
2626 00:22:09.825827 TX Vref=32, minBit 4, minWin=26, winSum=428
2627 00:22:09.825909 [TxChooseVref] Worse bit 5, Min win 26, Win sum 432, Final Vref 30
2628 00:22:09.825990
2629 00:22:09.826073 Final TX Range 1 Vref 30
2630 00:22:09.826155
2631 00:22:09.826268 ==
2632 00:22:09.826349 Dram Type= 6, Freq= 0, CH_0, rank 0
2633 00:22:09.826430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2634 00:22:09.826511 ==
2635 00:22:09.826591
2636 00:22:09.826670
2637 00:22:09.826750 TX Vref Scan disable
2638 00:22:09.826831 == TX Byte 0 ==
2639 00:22:09.826912 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2640 00:22:09.826993 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2641 00:22:09.827081 == TX Byte 1 ==
2642 00:22:09.827167 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2643 00:22:09.827291 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2644 00:22:09.827374
2645 00:22:09.827456 [DATLAT]
2646 00:22:09.827540 Freq=1200, CH0 RK0
2647 00:22:09.827624
2648 00:22:09.827713 DATLAT Default: 0xd
2649 00:22:09.827797 0, 0xFFFF, sum = 0
2650 00:22:09.827880 1, 0xFFFF, sum = 0
2651 00:22:09.827962 2, 0xFFFF, sum = 0
2652 00:22:09.828044 3, 0xFFFF, sum = 0
2653 00:22:09.828127 4, 0xFFFF, sum = 0
2654 00:22:09.828209 5, 0xFFFF, sum = 0
2655 00:22:09.828291 6, 0xFFFF, sum = 0
2656 00:22:09.828373 7, 0xFFFF, sum = 0
2657 00:22:09.828457 8, 0xFFFF, sum = 0
2658 00:22:09.828539 9, 0xFFFF, sum = 0
2659 00:22:09.828622 10, 0xFFFF, sum = 0
2660 00:22:09.828704 11, 0xFFFF, sum = 0
2661 00:22:09.828787 12, 0x0, sum = 1
2662 00:22:09.828869 13, 0x0, sum = 2
2663 00:22:09.828951 14, 0x0, sum = 3
2664 00:22:09.829034 15, 0x0, sum = 4
2665 00:22:09.829116 best_step = 13
2666 00:22:09.829196
2667 00:22:09.829301 ==
2668 00:22:09.829397 Dram Type= 6, Freq= 0, CH_0, rank 0
2669 00:22:09.829478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2670 00:22:09.829559 ==
2671 00:22:09.829640 RX Vref Scan: 1
2672 00:22:09.829720
2673 00:22:09.829801 Set Vref Range= 32 -> 127
2674 00:22:09.829871
2675 00:22:09.829924 RX Vref 32 -> 127, step: 1
2676 00:22:09.829980
2677 00:22:09.830032 RX Delay -21 -> 252, step: 4
2678 00:22:09.830084
2679 00:22:09.830136 Set Vref, RX VrefLevel [Byte0]: 32
2680 00:22:09.830191 [Byte1]: 32
2681 00:22:09.830243
2682 00:22:09.830295 Set Vref, RX VrefLevel [Byte0]: 33
2683 00:22:09.830347 [Byte1]: 33
2684 00:22:09.830399
2685 00:22:09.830455 Set Vref, RX VrefLevel [Byte0]: 34
2686 00:22:09.830508 [Byte1]: 34
2687 00:22:09.830560
2688 00:22:09.830611 Set Vref, RX VrefLevel [Byte0]: 35
2689 00:22:09.830663 [Byte1]: 35
2690 00:22:09.830755
2691 00:22:09.830808 Set Vref, RX VrefLevel [Byte0]: 36
2692 00:22:09.830860 [Byte1]: 36
2693 00:22:09.830912
2694 00:22:09.830963 Set Vref, RX VrefLevel [Byte0]: 37
2695 00:22:09.831016 [Byte1]: 37
2696 00:22:09.831067
2697 00:22:09.831119 Set Vref, RX VrefLevel [Byte0]: 38
2698 00:22:09.831170 [Byte1]: 38
2699 00:22:09.831221
2700 00:22:09.831272 Set Vref, RX VrefLevel [Byte0]: 39
2701 00:22:09.831325 [Byte1]: 39
2702 00:22:09.831377
2703 00:22:09.831428 Set Vref, RX VrefLevel [Byte0]: 40
2704 00:22:09.831480 [Byte1]: 40
2705 00:22:09.831532
2706 00:22:09.831596 Set Vref, RX VrefLevel [Byte0]: 41
2707 00:22:09.831649 [Byte1]: 41
2708 00:22:09.831725
2709 00:22:09.831826 Set Vref, RX VrefLevel [Byte0]: 42
2710 00:22:09.831915 [Byte1]: 42
2711 00:22:09.832007
2712 00:22:09.832103 Set Vref, RX VrefLevel [Byte0]: 43
2713 00:22:09.832190 [Byte1]: 43
2714 00:22:09.832277
2715 00:22:09.832361 Set Vref, RX VrefLevel [Byte0]: 44
2716 00:22:09.832459 [Byte1]: 44
2717 00:22:09.832646
2718 00:22:09.832747 Set Vref, RX VrefLevel [Byte0]: 45
2719 00:22:09.832835 [Byte1]: 45
2720 00:22:09.832920
2721 00:22:09.833003 Set Vref, RX VrefLevel [Byte0]: 46
2722 00:22:09.833084 [Byte1]: 46
2723 00:22:09.833182
2724 00:22:09.833275 Set Vref, RX VrefLevel [Byte0]: 47
2725 00:22:09.833373 [Byte1]: 47
2726 00:22:09.833454
2727 00:22:09.833536 Set Vref, RX VrefLevel [Byte0]: 48
2728 00:22:09.833593 [Byte1]: 48
2729 00:22:09.833646
2730 00:22:09.833698 Set Vref, RX VrefLevel [Byte0]: 49
2731 00:22:09.833750 [Byte1]: 49
2732 00:22:09.833802
2733 00:22:09.833854 Set Vref, RX VrefLevel [Byte0]: 50
2734 00:22:09.833906 [Byte1]: 50
2735 00:22:09.833957
2736 00:22:09.834009 Set Vref, RX VrefLevel [Byte0]: 51
2737 00:22:09.834060 [Byte1]: 51
2738 00:22:09.834111
2739 00:22:09.834163 Set Vref, RX VrefLevel [Byte0]: 52
2740 00:22:09.834215 [Byte1]: 52
2741 00:22:09.834266
2742 00:22:09.834318 Set Vref, RX VrefLevel [Byte0]: 53
2743 00:22:09.834371 [Byte1]: 53
2744 00:22:09.834422
2745 00:22:09.834489 Set Vref, RX VrefLevel [Byte0]: 54
2746 00:22:09.834555 [Byte1]: 54
2747 00:22:09.834607
2748 00:22:09.834658 Set Vref, RX VrefLevel [Byte0]: 55
2749 00:22:09.834733 [Byte1]: 55
2750 00:22:09.834800
2751 00:22:09.835112 Set Vref, RX VrefLevel [Byte0]: 56
2752 00:22:09.835207 [Byte1]: 56
2753 00:22:09.835306
2754 00:22:09.835411 Set Vref, RX VrefLevel [Byte0]: 57
2755 00:22:09.835518 [Byte1]: 57
2756 00:22:09.835630
2757 00:22:09.835743 Set Vref, RX VrefLevel [Byte0]: 58
2758 00:22:09.835833 [Byte1]: 58
2759 00:22:09.835932
2760 00:22:09.835986 Set Vref, RX VrefLevel [Byte0]: 59
2761 00:22:09.836039 [Byte1]: 59
2762 00:22:09.836091
2763 00:22:09.836143 Set Vref, RX VrefLevel [Byte0]: 60
2764 00:22:09.836195 [Byte1]: 60
2765 00:22:09.836246
2766 00:22:09.836298 Set Vref, RX VrefLevel [Byte0]: 61
2767 00:22:09.836349 [Byte1]: 61
2768 00:22:09.836401
2769 00:22:09.836452 Set Vref, RX VrefLevel [Byte0]: 62
2770 00:22:09.836504 [Byte1]: 62
2771 00:22:09.836556
2772 00:22:09.836607 Set Vref, RX VrefLevel [Byte0]: 63
2773 00:22:09.836659 [Byte1]: 63
2774 00:22:09.836711
2775 00:22:09.836762 Set Vref, RX VrefLevel [Byte0]: 64
2776 00:22:09.836813 [Byte1]: 64
2777 00:22:09.836864
2778 00:22:09.836916 Set Vref, RX VrefLevel [Byte0]: 65
2779 00:22:09.837000 [Byte1]: 65
2780 00:22:09.837080
2781 00:22:09.837161 Set Vref, RX VrefLevel [Byte0]: 66
2782 00:22:09.837242 [Byte1]: 66
2783 00:22:09.837366
2784 00:22:09.837447 Set Vref, RX VrefLevel [Byte0]: 67
2785 00:22:09.837529 [Byte1]: 67
2786 00:22:09.837605
2787 00:22:09.837659 Set Vref, RX VrefLevel [Byte0]: 68
2788 00:22:09.837711 [Byte1]: 68
2789 00:22:09.837762
2790 00:22:09.837817 Final RX Vref Byte 0 = 55 to rank0
2791 00:22:09.837903 Final RX Vref Byte 1 = 48 to rank0
2792 00:22:09.837956 Final RX Vref Byte 0 = 55 to rank1
2793 00:22:09.838099 Final RX Vref Byte 1 = 48 to rank1==
2794 00:22:09.838310 Dram Type= 6, Freq= 0, CH_0, rank 0
2795 00:22:09.838410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2796 00:22:09.838472 ==
2797 00:22:09.838529 DQS Delay:
2798 00:22:09.838582 DQS0 = 0, DQS1 = 0
2799 00:22:09.838635 DQM Delay:
2800 00:22:09.838691 DQM0 = 119, DQM1 = 105
2801 00:22:09.838743 DQ Delay:
2802 00:22:09.838795 DQ0 =120, DQ1 =118, DQ2 =116, DQ3 =116
2803 00:22:09.838848 DQ4 =122, DQ5 =114, DQ6 =126, DQ7 =122
2804 00:22:09.838900 DQ8 =94, DQ9 =92, DQ10 =104, DQ11 =100
2805 00:22:09.838952 DQ12 =114, DQ13 =108, DQ14 =116, DQ15 =114
2806 00:22:09.839004
2807 00:22:09.839056
2808 00:22:09.839107 [DQSOSCAuto] RK0, (LSB)MR18= 0x2fd, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 409 ps
2809 00:22:09.839160 CH0 RK0: MR19=403, MR18=2FD
2810 00:22:09.839212 CH0_RK0: MR19=0x403, MR18=0x2FD, DQSOSC=409, MR23=63, INC=39, DEC=26
2811 00:22:09.839265
2812 00:22:09.839316 ----->DramcWriteLeveling(PI) begin...
2813 00:22:09.839369 ==
2814 00:22:09.839421 Dram Type= 6, Freq= 0, CH_0, rank 1
2815 00:22:09.839472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2816 00:22:09.839525 ==
2817 00:22:09.839579 Write leveling (Byte 0): 32 => 32
2818 00:22:09.839631 Write leveling (Byte 1): 25 => 25
2819 00:22:09.839744 DramcWriteLeveling(PI) end<-----
2820 00:22:09.839899
2821 00:22:09.840029 ==
2822 00:22:09.840135 Dram Type= 6, Freq= 0, CH_0, rank 1
2823 00:22:09.840202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2824 00:22:09.840256 ==
2825 00:22:09.840309 [Gating] SW mode calibration
2826 00:22:09.840363 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2827 00:22:09.840417 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2828 00:22:09.840471 0 15 0 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
2829 00:22:09.840523 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2830 00:22:09.840576 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2831 00:22:09.840628 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2832 00:22:09.840681 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2833 00:22:09.840733 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2834 00:22:09.840785 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2835 00:22:09.840837 0 15 28 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 0)
2836 00:22:09.840889 1 0 0 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
2837 00:22:09.840941 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2838 00:22:09.840992 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2839 00:22:09.841044 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2840 00:22:09.841096 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2841 00:22:09.841148 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2842 00:22:09.841199 1 0 24 | B1->B0 | 2323 3332 | 0 1 | (0 0) (0 0)
2843 00:22:09.841251 1 0 28 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
2844 00:22:09.841373 1 1 0 | B1->B0 | 4444 4646 | 0 0 | (1 1) (0 0)
2845 00:22:09.841426 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2846 00:22:09.841478 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2847 00:22:09.841529 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2848 00:22:09.841581 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2849 00:22:09.841633 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2850 00:22:09.841684 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2851 00:22:09.841736 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2852 00:22:09.841788 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2853 00:22:09.841839 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2854 00:22:09.841891 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2855 00:22:09.841943 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2856 00:22:09.841994 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2857 00:22:09.842046 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2858 00:22:09.842098 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2859 00:22:09.842150 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2860 00:22:09.842206 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2861 00:22:09.842273 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2862 00:22:09.842336 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2863 00:22:09.842449 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2864 00:22:09.842586 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2865 00:22:09.842685 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2866 00:22:09.842968 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2867 00:22:09.843163 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
2868 00:22:09.843267 Total UI for P1: 0, mck2ui 16
2869 00:22:09.843353 best dqsien dly found for B0: ( 1, 3, 24)
2870 00:22:09.843438 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2871 00:22:09.843521 Total UI for P1: 0, mck2ui 16
2872 00:22:09.843618 best dqsien dly found for B1: ( 1, 3, 30)
2873 00:22:09.843700 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2874 00:22:09.843781 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2875 00:22:09.843862
2876 00:22:09.844017 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2877 00:22:09.844149 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2878 00:22:09.844247 [Gating] SW calibration Done
2879 00:22:09.844331 ==
2880 00:22:09.844414 Dram Type= 6, Freq= 0, CH_0, rank 1
2881 00:22:09.844496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2882 00:22:09.844577 ==
2883 00:22:09.844659 RX Vref Scan: 0
2884 00:22:09.844739
2885 00:22:09.844820 RX Vref 0 -> 0, step: 1
2886 00:22:09.844900
2887 00:22:09.844982 RX Delay -40 -> 252, step: 8
2888 00:22:09.845073 iDelay=200, Bit 0, Center 115 (48 ~ 183) 136
2889 00:22:09.845155 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2890 00:22:09.845236 iDelay=200, Bit 2, Center 115 (48 ~ 183) 136
2891 00:22:09.845337 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2892 00:22:09.845406 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
2893 00:22:09.845459 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2894 00:22:09.845512 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2895 00:22:09.845563 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2896 00:22:09.845617 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2897 00:22:09.845669 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2898 00:22:09.845721 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2899 00:22:09.845773 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2900 00:22:09.845839 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2901 00:22:09.845892 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2902 00:22:09.845944 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2903 00:22:09.845996 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2904 00:22:09.846047 ==
2905 00:22:09.846100 Dram Type= 6, Freq= 0, CH_0, rank 1
2906 00:22:09.846152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2907 00:22:09.846204 ==
2908 00:22:09.846256 DQS Delay:
2909 00:22:09.846307 DQS0 = 0, DQS1 = 0
2910 00:22:09.846359 DQM Delay:
2911 00:22:09.846410 DQM0 = 119, DQM1 = 107
2912 00:22:09.846461 DQ Delay:
2913 00:22:09.846516 DQ0 =115, DQ1 =119, DQ2 =115, DQ3 =115
2914 00:22:09.846568 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2915 00:22:09.846625 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2916 00:22:09.846715 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =115
2917 00:22:09.846857
2918 00:22:09.846956
2919 00:22:09.847017 ==
2920 00:22:09.847101 Dram Type= 6, Freq= 0, CH_0, rank 1
2921 00:22:09.847186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2922 00:22:09.847268 ==
2923 00:22:09.847349
2924 00:22:09.847429
2925 00:22:09.847509 TX Vref Scan disable
2926 00:22:09.847590 == TX Byte 0 ==
2927 00:22:09.847671 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2928 00:22:09.847753 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2929 00:22:09.847834 == TX Byte 1 ==
2930 00:22:09.847915 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2931 00:22:09.847996 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2932 00:22:09.848076 ==
2933 00:22:09.848157 Dram Type= 6, Freq= 0, CH_0, rank 1
2934 00:22:09.848238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2935 00:22:09.848319 ==
2936 00:22:09.848401 TX Vref=22, minBit 2, minWin=26, winSum=418
2937 00:22:09.987997 TX Vref=24, minBit 10, minWin=25, winSum=422
2938 00:22:09.988140 TX Vref=26, minBit 1, minWin=25, winSum=422
2939 00:22:09.988212 TX Vref=28, minBit 2, minWin=26, winSum=431
2940 00:22:09.988272 TX Vref=30, minBit 2, minWin=26, winSum=428
2941 00:22:09.988330 TX Vref=32, minBit 1, minWin=26, winSum=427
2942 00:22:09.988387 [TxChooseVref] Worse bit 2, Min win 26, Win sum 431, Final Vref 28
2943 00:22:09.988443
2944 00:22:09.988498 Final TX Range 1 Vref 28
2945 00:22:09.988553
2946 00:22:09.988606 ==
2947 00:22:09.988660 Dram Type= 6, Freq= 0, CH_0, rank 1
2948 00:22:09.988714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2949 00:22:09.988768 ==
2950 00:22:09.988821
2951 00:22:09.988874
2952 00:22:09.989121 TX Vref Scan disable
2953 00:22:09.989222 == TX Byte 0 ==
2954 00:22:09.989320 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2955 00:22:09.989378 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2956 00:22:09.989433 == TX Byte 1 ==
2957 00:22:09.989487 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2958 00:22:09.989554 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2959 00:22:09.989608
2960 00:22:09.989692 [DATLAT]
2961 00:22:09.989758 Freq=1200, CH0 RK1
2962 00:22:09.989827
2963 00:22:09.989880 DATLAT Default: 0xd
2964 00:22:09.989934 0, 0xFFFF, sum = 0
2965 00:22:09.989989 1, 0xFFFF, sum = 0
2966 00:22:09.990044 2, 0xFFFF, sum = 0
2967 00:22:09.990125 3, 0xFFFF, sum = 0
2968 00:22:09.990210 4, 0xFFFF, sum = 0
2969 00:22:09.990264 5, 0xFFFF, sum = 0
2970 00:22:09.990318 6, 0xFFFF, sum = 0
2971 00:22:09.990372 7, 0xFFFF, sum = 0
2972 00:22:09.990426 8, 0xFFFF, sum = 0
2973 00:22:09.990480 9, 0xFFFF, sum = 0
2974 00:22:09.990546 10, 0xFFFF, sum = 0
2975 00:22:09.990621 11, 0xFFFF, sum = 0
2976 00:22:09.990675 12, 0x0, sum = 1
2977 00:22:09.990758 13, 0x0, sum = 2
2978 00:22:09.990827 14, 0x0, sum = 3
2979 00:22:09.990881 15, 0x0, sum = 4
2980 00:22:09.990935 best_step = 13
2981 00:22:09.991016
2982 00:22:09.991082 ==
2983 00:22:09.991134 Dram Type= 6, Freq= 0, CH_0, rank 1
2984 00:22:09.991186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2985 00:22:09.991268 ==
2986 00:22:09.991320 RX Vref Scan: 0
2987 00:22:09.991371
2988 00:22:09.991423 RX Vref 0 -> 0, step: 1
2989 00:22:09.991475
2990 00:22:09.991527 RX Delay -21 -> 252, step: 4
2991 00:22:09.991593 iDelay=195, Bit 0, Center 114 (51 ~ 178) 128
2992 00:22:09.991647 iDelay=195, Bit 1, Center 118 (51 ~ 186) 136
2993 00:22:09.991713 iDelay=195, Bit 2, Center 114 (51 ~ 178) 128
2994 00:22:09.991765 iDelay=195, Bit 3, Center 114 (51 ~ 178) 128
2995 00:22:09.991832 iDelay=195, Bit 4, Center 122 (59 ~ 186) 128
2996 00:22:09.991899 iDelay=195, Bit 5, Center 110 (47 ~ 174) 128
2997 00:22:09.991950 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
2998 00:22:09.992002 iDelay=195, Bit 7, Center 124 (59 ~ 190) 132
2999 00:22:09.992053 iDelay=195, Bit 8, Center 96 (27 ~ 166) 140
3000 00:22:09.992122 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3001 00:22:09.992187 iDelay=195, Bit 10, Center 108 (43 ~ 174) 132
3002 00:22:09.992239 iDelay=195, Bit 11, Center 98 (31 ~ 166) 136
3003 00:22:09.992291 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3004 00:22:09.992592 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3005 00:22:09.992655 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3006 00:22:09.992715 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3007 00:22:09.992770 ==
3008 00:22:09.992828 Dram Type= 6, Freq= 0, CH_0, rank 1
3009 00:22:09.992883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3010 00:22:09.992938 ==
3011 00:22:09.993015 DQS Delay:
3012 00:22:09.993098 DQS0 = 0, DQS1 = 0
3013 00:22:09.993184 DQM Delay:
3014 00:22:09.993277 DQM0 = 118, DQM1 = 106
3015 00:22:09.993348 DQ Delay:
3016 00:22:09.993401 DQ0 =114, DQ1 =118, DQ2 =114, DQ3 =114
3017 00:22:09.993454 DQ4 =122, DQ5 =110, DQ6 =128, DQ7 =124
3018 00:22:09.993507 DQ8 =96, DQ9 =92, DQ10 =108, DQ11 =98
3019 00:22:09.993559 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =114
3020 00:22:09.993611
3021 00:22:09.993663
3022 00:22:09.993721 [DQSOSCAuto] RK1, (LSB)MR18= 0xfe, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
3023 00:22:09.993777 CH0 RK1: MR19=403, MR18=FE
3024 00:22:09.993829 CH0_RK1: MR19=0x403, MR18=0xFE, DQSOSC=410, MR23=63, INC=39, DEC=26
3025 00:22:09.993891 [RxdqsGatingPostProcess] freq 1200
3026 00:22:09.993952 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3027 00:22:09.994005 best DQS0 dly(2T, 0.5T) = (0, 11)
3028 00:22:09.994058 best DQS1 dly(2T, 0.5T) = (0, 12)
3029 00:22:09.994111 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3030 00:22:09.994163 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3031 00:22:09.994215 best DQS0 dly(2T, 0.5T) = (0, 11)
3032 00:22:09.994267 best DQS1 dly(2T, 0.5T) = (0, 11)
3033 00:22:09.994319 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3034 00:22:09.994371 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3035 00:22:09.994423 Pre-setting of DQS Precalculation
3036 00:22:09.994474 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3037 00:22:09.994543 ==
3038 00:22:09.994614 Dram Type= 6, Freq= 0, CH_1, rank 0
3039 00:22:09.994667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3040 00:22:09.994738 ==
3041 00:22:09.994825 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3042 00:22:09.994909 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3043 00:22:09.994990 [CA 0] Center 38 (8~68) winsize 61
3044 00:22:09.995072 [CA 1] Center 38 (8~68) winsize 61
3045 00:22:09.995152 [CA 2] Center 35 (6~65) winsize 60
3046 00:22:09.995234 [CA 3] Center 34 (4~64) winsize 61
3047 00:22:09.995315 [CA 4] Center 34 (4~65) winsize 62
3048 00:22:09.995396 [CA 5] Center 33 (3~64) winsize 62
3049 00:22:09.995477
3050 00:22:09.995558 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3051 00:22:09.995639
3052 00:22:09.995721 [CATrainingPosCal] consider 1 rank data
3053 00:22:09.995802 u2DelayCellTimex100 = 270/100 ps
3054 00:22:09.995883 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3055 00:22:09.995965 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3056 00:22:09.996046 CA2 delay=35 (6~65),Diff = 2 PI (9 cell)
3057 00:22:09.996128 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3058 00:22:09.996209 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3059 00:22:09.996290 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3060 00:22:09.996370
3061 00:22:09.996455 CA PerBit enable=1, Macro0, CA PI delay=33
3062 00:22:09.996538
3063 00:22:09.996619 [CBTSetCACLKResult] CA Dly = 33
3064 00:22:09.996700 CS Dly: 4 (0~35)
3065 00:22:09.996771 ==
3066 00:22:09.996826 Dram Type= 6, Freq= 0, CH_1, rank 1
3067 00:22:09.996879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3068 00:22:09.996933 ==
3069 00:22:09.996985 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3070 00:22:09.997089 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3071 00:22:09.997178 [CA 0] Center 37 (7~68) winsize 62
3072 00:22:09.997283 [CA 1] Center 38 (8~68) winsize 61
3073 00:22:09.997374 [CA 2] Center 35 (5~65) winsize 61
3074 00:22:09.997457 [CA 3] Center 33 (3~64) winsize 62
3075 00:22:09.997539 [CA 4] Center 34 (4~64) winsize 61
3076 00:22:09.997622 [CA 5] Center 33 (3~63) winsize 61
3077 00:22:09.997706
3078 00:22:09.997799 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3079 00:22:09.997883
3080 00:22:09.997942 [CATrainingPosCal] consider 2 rank data
3081 00:22:09.998015 u2DelayCellTimex100 = 270/100 ps
3082 00:22:09.998073 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3083 00:22:09.998127 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3084 00:22:09.998180 CA2 delay=35 (6~65),Diff = 2 PI (9 cell)
3085 00:22:09.998240 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3086 00:22:09.998301 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3087 00:22:09.998384 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3088 00:22:09.998464
3089 00:22:09.998550 CA PerBit enable=1, Macro0, CA PI delay=33
3090 00:22:09.998632
3091 00:22:09.998713 [CBTSetCACLKResult] CA Dly = 33
3092 00:22:09.998799 CS Dly: 5 (0~38)
3093 00:22:09.998880
3094 00:22:09.998961 ----->DramcWriteLeveling(PI) begin...
3095 00:22:09.999045 ==
3096 00:22:09.999147 Dram Type= 6, Freq= 0, CH_1, rank 0
3097 00:22:09.999245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3098 00:22:09.999327 ==
3099 00:22:09.999412 Write leveling (Byte 0): 26 => 26
3100 00:22:09.999495 Write leveling (Byte 1): 28 => 28
3101 00:22:09.999576 DramcWriteLeveling(PI) end<-----
3102 00:22:09.999657
3103 00:22:09.999737 ==
3104 00:22:09.999819 Dram Type= 6, Freq= 0, CH_1, rank 0
3105 00:22:09.999901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3106 00:22:09.999984 ==
3107 00:22:10.000069 [Gating] SW mode calibration
3108 00:22:10.000155 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3109 00:22:10.000239 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3110 00:22:10.000325 0 15 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
3111 00:22:10.000407 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3112 00:22:10.000490 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3113 00:22:10.000546 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3114 00:22:10.000599 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3115 00:22:10.000651 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3116 00:22:10.000704 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 0)
3117 00:22:10.000756 0 15 28 | B1->B0 | 2929 2424 | 0 0 | (0 1) (1 0)
3118 00:22:10.000808 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3119 00:22:10.000885 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3120 00:22:10.000967 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3121 00:22:10.001049 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3122 00:22:10.001370 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3123 00:22:10.001434 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3124 00:22:10.001490 1 0 24 | B1->B0 | 2626 2d2d | 0 1 | (0 0) (0 0)
3125 00:22:10.001557 1 0 28 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
3126 00:22:10.001618 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3127 00:22:10.001672 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3128 00:22:10.001725 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3129 00:22:10.001777 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3130 00:22:10.001831 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3131 00:22:10.001890 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3132 00:22:10.001943 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3133 00:22:10.001995 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3134 00:22:10.002048 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3135 00:22:10.002100 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3136 00:22:10.002186 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3137 00:22:10.002268 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3138 00:22:10.002350 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3139 00:22:10.002435 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3140 00:22:10.002517 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3141 00:22:10.002599 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3142 00:22:10.002681 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3143 00:22:10.002765 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3144 00:22:10.002847 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3145 00:22:10.002928 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3146 00:22:10.003010 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3147 00:22:10.003109 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 00:22:10.003206 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3149 00:22:10.003314 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3150 00:22:10.003414 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3151 00:22:10.003497 Total UI for P1: 0, mck2ui 16
3152 00:22:10.003580 best dqsien dly found for B0: ( 1, 3, 26)
3153 00:22:10.003662 Total UI for P1: 0, mck2ui 16
3154 00:22:10.003744 best dqsien dly found for B1: ( 1, 3, 28)
3155 00:22:10.003826 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3156 00:22:10.003908 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3157 00:22:10.003988
3158 00:22:10.004070 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3159 00:22:10.004152 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3160 00:22:10.004234 [Gating] SW calibration Done
3161 00:22:10.004315 ==
3162 00:22:10.004397 Dram Type= 6, Freq= 0, CH_1, rank 0
3163 00:22:10.004479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3164 00:22:10.004560 ==
3165 00:22:10.004643 RX Vref Scan: 0
3166 00:22:10.004700
3167 00:22:10.004752 RX Vref 0 -> 0, step: 1
3168 00:22:10.004805
3169 00:22:10.004857 RX Delay -40 -> 252, step: 8
3170 00:22:10.004931 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3171 00:22:10.005015 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3172 00:22:10.005097 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3173 00:22:10.005184 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3174 00:22:10.005293 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3175 00:22:10.005364 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3176 00:22:10.005417 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3177 00:22:10.005470 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3178 00:22:10.005522 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3179 00:22:10.005575 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3180 00:22:10.005628 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3181 00:22:10.005680 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3182 00:22:10.005733 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3183 00:22:10.005786 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3184 00:22:10.005838 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3185 00:22:10.005890 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3186 00:22:10.005941 ==
3187 00:22:10.005993 Dram Type= 6, Freq= 0, CH_1, rank 0
3188 00:22:10.006046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3189 00:22:10.006099 ==
3190 00:22:10.006152 DQS Delay:
3191 00:22:10.006204 DQS0 = 0, DQS1 = 0
3192 00:22:10.006256 DQM Delay:
3193 00:22:10.006309 DQM0 = 116, DQM1 = 112
3194 00:22:10.006361 DQ Delay:
3195 00:22:10.006413 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =119
3196 00:22:10.006466 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =115
3197 00:22:10.006518 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3198 00:22:10.006571 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3199 00:22:10.006623
3200 00:22:10.006674
3201 00:22:10.006726 ==
3202 00:22:10.006778 Dram Type= 6, Freq= 0, CH_1, rank 0
3203 00:22:10.006830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3204 00:22:10.006883 ==
3205 00:22:10.006935
3206 00:22:10.006987
3207 00:22:10.007038 TX Vref Scan disable
3208 00:22:10.007090 == TX Byte 0 ==
3209 00:22:10.007141 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3210 00:22:10.007194 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3211 00:22:10.007246 == TX Byte 1 ==
3212 00:22:10.007299 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3213 00:22:10.007355 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3214 00:22:10.007408 ==
3215 00:22:10.007460 Dram Type= 6, Freq= 0, CH_1, rank 0
3216 00:22:10.007513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3217 00:22:10.007566 ==
3218 00:22:10.007618 TX Vref=22, minBit 8, minWin=25, winSum=416
3219 00:22:10.007670 TX Vref=24, minBit 8, minWin=25, winSum=417
3220 00:22:10.007723 TX Vref=26, minBit 9, minWin=25, winSum=424
3221 00:22:10.007775 TX Vref=28, minBit 9, minWin=25, winSum=425
3222 00:22:10.007828 TX Vref=30, minBit 9, minWin=25, winSum=426
3223 00:22:10.007880 TX Vref=32, minBit 2, minWin=26, winSum=429
3224 00:22:10.007932 [TxChooseVref] Worse bit 2, Min win 26, Win sum 429, Final Vref 32
3225 00:22:10.007986
3226 00:22:10.008038 Final TX Range 1 Vref 32
3227 00:22:10.008090
3228 00:22:10.008141 ==
3229 00:22:10.008193 Dram Type= 6, Freq= 0, CH_1, rank 0
3230 00:22:10.008245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3231 00:22:10.008297 ==
3232 00:22:10.008349
3233 00:22:10.008401
3234 00:22:10.008452 TX Vref Scan disable
3235 00:22:10.008504 == TX Byte 0 ==
3236 00:22:10.008556 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3237 00:22:10.008821 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3238 00:22:10.008881 == TX Byte 1 ==
3239 00:22:10.008936 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3240 00:22:10.008989 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3241 00:22:10.009043
3242 00:22:10.009095 [DATLAT]
3243 00:22:10.009147 Freq=1200, CH1 RK0
3244 00:22:10.009199
3245 00:22:10.009251 DATLAT Default: 0xd
3246 00:22:10.009359 0, 0xFFFF, sum = 0
3247 00:22:10.009414 1, 0xFFFF, sum = 0
3248 00:22:10.009467 2, 0xFFFF, sum = 0
3249 00:22:10.009520 3, 0xFFFF, sum = 0
3250 00:22:10.009573 4, 0xFFFF, sum = 0
3251 00:22:10.009626 5, 0xFFFF, sum = 0
3252 00:22:10.009680 6, 0xFFFF, sum = 0
3253 00:22:10.009733 7, 0xFFFF, sum = 0
3254 00:22:10.009786 8, 0xFFFF, sum = 0
3255 00:22:10.009839 9, 0xFFFF, sum = 0
3256 00:22:10.009893 10, 0xFFFF, sum = 0
3257 00:22:10.009946 11, 0xFFFF, sum = 0
3258 00:22:10.009999 12, 0x0, sum = 1
3259 00:22:10.010052 13, 0x0, sum = 2
3260 00:22:10.010105 14, 0x0, sum = 3
3261 00:22:10.010158 15, 0x0, sum = 4
3262 00:22:10.010211 best_step = 13
3263 00:22:10.010263
3264 00:22:10.010315 ==
3265 00:22:10.010367 Dram Type= 6, Freq= 0, CH_1, rank 0
3266 00:22:10.010419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3267 00:22:10.010471 ==
3268 00:22:10.010523 RX Vref Scan: 1
3269 00:22:10.010575
3270 00:22:10.010627 Set Vref Range= 32 -> 127
3271 00:22:10.010679
3272 00:22:10.010730 RX Vref 32 -> 127, step: 1
3273 00:22:10.010782
3274 00:22:10.010834 RX Delay -13 -> 252, step: 4
3275 00:22:10.010885
3276 00:22:10.010937 Set Vref, RX VrefLevel [Byte0]: 32
3277 00:22:10.010989 [Byte1]: 32
3278 00:22:10.011041
3279 00:22:10.011093 Set Vref, RX VrefLevel [Byte0]: 33
3280 00:22:10.011145 [Byte1]: 33
3281 00:22:10.011197
3282 00:22:10.011256 Set Vref, RX VrefLevel [Byte0]: 34
3283 00:22:10.011309 [Byte1]: 34
3284 00:22:10.011360
3285 00:22:10.011412 Set Vref, RX VrefLevel [Byte0]: 35
3286 00:22:10.011465 [Byte1]: 35
3287 00:22:10.011522
3288 00:22:10.011574 Set Vref, RX VrefLevel [Byte0]: 36
3289 00:22:10.011626 [Byte1]: 36
3290 00:22:10.011677
3291 00:22:10.011728 Set Vref, RX VrefLevel [Byte0]: 37
3292 00:22:10.011781 [Byte1]: 37
3293 00:22:10.011832
3294 00:22:10.011884 Set Vref, RX VrefLevel [Byte0]: 38
3295 00:22:10.011935 [Byte1]: 38
3296 00:22:10.011987
3297 00:22:10.012037 Set Vref, RX VrefLevel [Byte0]: 39
3298 00:22:10.012088 [Byte1]: 39
3299 00:22:10.012140
3300 00:22:10.012191 Set Vref, RX VrefLevel [Byte0]: 40
3301 00:22:10.012243 [Byte1]: 40
3302 00:22:10.012294
3303 00:22:10.012353 Set Vref, RX VrefLevel [Byte0]: 41
3304 00:22:10.012408 [Byte1]: 41
3305 00:22:10.012460
3306 00:22:10.012511 Set Vref, RX VrefLevel [Byte0]: 42
3307 00:22:10.012562 [Byte1]: 42
3308 00:22:10.012614
3309 00:22:10.012666 Set Vref, RX VrefLevel [Byte0]: 43
3310 00:22:10.012717 [Byte1]: 43
3311 00:22:10.012768
3312 00:22:10.012820 Set Vref, RX VrefLevel [Byte0]: 44
3313 00:22:10.012871 [Byte1]: 44
3314 00:22:10.012923
3315 00:22:10.012974 Set Vref, RX VrefLevel [Byte0]: 45
3316 00:22:10.013025 [Byte1]: 45
3317 00:22:10.013077
3318 00:22:10.013129 Set Vref, RX VrefLevel [Byte0]: 46
3319 00:22:10.013180 [Byte1]: 46
3320 00:22:10.013231
3321 00:22:10.013329 Set Vref, RX VrefLevel [Byte0]: 47
3322 00:22:10.013382 [Byte1]: 47
3323 00:22:10.013434
3324 00:22:10.013485 Set Vref, RX VrefLevel [Byte0]: 48
3325 00:22:10.013537 [Byte1]: 48
3326 00:22:10.013589
3327 00:22:10.013640 Set Vref, RX VrefLevel [Byte0]: 49
3328 00:22:10.013692 [Byte1]: 49
3329 00:22:10.013744
3330 00:22:10.013795 Set Vref, RX VrefLevel [Byte0]: 50
3331 00:22:10.013847 [Byte1]: 50
3332 00:22:10.013899
3333 00:22:10.013950 Set Vref, RX VrefLevel [Byte0]: 51
3334 00:22:10.014002 [Byte1]: 51
3335 00:22:10.014053
3336 00:22:10.014104 Set Vref, RX VrefLevel [Byte0]: 52
3337 00:22:10.014158 [Byte1]: 52
3338 00:22:10.014210
3339 00:22:10.014261 Set Vref, RX VrefLevel [Byte0]: 53
3340 00:22:10.014313 [Byte1]: 53
3341 00:22:10.014398
3342 00:22:10.014565 Set Vref, RX VrefLevel [Byte0]: 54
3343 00:22:10.014636 [Byte1]: 54
3344 00:22:10.014704
3345 00:22:10.014770 Set Vref, RX VrefLevel [Byte0]: 55
3346 00:22:10.014822 [Byte1]: 55
3347 00:22:10.014873
3348 00:22:10.014925 Set Vref, RX VrefLevel [Byte0]: 56
3349 00:22:10.014977 [Byte1]: 56
3350 00:22:10.015028
3351 00:22:10.015080 Set Vref, RX VrefLevel [Byte0]: 57
3352 00:22:10.015132 [Byte1]: 57
3353 00:22:10.015183
3354 00:22:10.015234 Set Vref, RX VrefLevel [Byte0]: 58
3355 00:22:10.015285 [Byte1]: 58
3356 00:22:10.015336
3357 00:22:10.015388 Set Vref, RX VrefLevel [Byte0]: 59
3358 00:22:10.015439 [Byte1]: 59
3359 00:22:10.015490
3360 00:22:10.015542 Set Vref, RX VrefLevel [Byte0]: 60
3361 00:22:10.015593 [Byte1]: 60
3362 00:22:10.015644
3363 00:22:10.015711 Set Vref, RX VrefLevel [Byte0]: 61
3364 00:22:10.015776 [Byte1]: 61
3365 00:22:10.015828
3366 00:22:10.015895 Set Vref, RX VrefLevel [Byte0]: 62
3367 00:22:10.015966 [Byte1]: 62
3368 00:22:10.016018
3369 00:22:10.016070 Set Vref, RX VrefLevel [Byte0]: 63
3370 00:22:10.016122 [Byte1]: 63
3371 00:22:10.016173
3372 00:22:10.016225 Set Vref, RX VrefLevel [Byte0]: 64
3373 00:22:10.016276 [Byte1]: 64
3374 00:22:10.016328
3375 00:22:10.016380 Set Vref, RX VrefLevel [Byte0]: 65
3376 00:22:10.016477 [Byte1]: 65
3377 00:22:10.016529
3378 00:22:10.016585 Final RX Vref Byte 0 = 50 to rank0
3379 00:22:10.016639 Final RX Vref Byte 1 = 50 to rank0
3380 00:22:10.016694 Final RX Vref Byte 0 = 50 to rank1
3381 00:22:10.016752 Final RX Vref Byte 1 = 50 to rank1==
3382 00:22:10.016846 Dram Type= 6, Freq= 0, CH_1, rank 0
3383 00:22:10.016931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3384 00:22:10.017013 ==
3385 00:22:10.017095 DQS Delay:
3386 00:22:10.017178 DQS0 = 0, DQS1 = 0
3387 00:22:10.017281 DQM Delay:
3388 00:22:10.017353 DQM0 = 114, DQM1 = 112
3389 00:22:10.017405 DQ Delay:
3390 00:22:10.017481 DQ0 =120, DQ1 =110, DQ2 =104, DQ3 =114
3391 00:22:10.017535 DQ4 =110, DQ5 =122, DQ6 =126, DQ7 =110
3392 00:22:10.017588 DQ8 =98, DQ9 =102, DQ10 =112, DQ11 =106
3393 00:22:10.017641 DQ12 =120, DQ13 =120, DQ14 =118, DQ15 =120
3394 00:22:10.017700
3395 00:22:10.017757
3396 00:22:10.017810 [DQSOSCAuto] RK0, (LSB)MR18= 0xf603, (MSB)MR19= 0x304, tDQSOscB0 = 408 ps tDQSOscB1 = 414 ps
3397 00:22:10.017864 CH1 RK0: MR19=304, MR18=F603
3398 00:22:10.017916 CH1_RK0: MR19=0x304, MR18=0xF603, DQSOSC=408, MR23=63, INC=39, DEC=26
3399 00:22:10.017969
3400 00:22:10.018024 ----->DramcWriteLeveling(PI) begin...
3401 00:22:10.018079 ==
3402 00:22:10.018131 Dram Type= 6, Freq= 0, CH_1, rank 1
3403 00:22:10.018414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3404 00:22:10.018479 ==
3405 00:22:10.018533 Write leveling (Byte 0): 25 => 25
3406 00:22:10.018591 Write leveling (Byte 1): 27 => 27
3407 00:22:10.018644 DramcWriteLeveling(PI) end<-----
3408 00:22:10.018696
3409 00:22:10.018747 ==
3410 00:22:10.018800 Dram Type= 6, Freq= 0, CH_1, rank 1
3411 00:22:10.018852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3412 00:22:10.018904 ==
3413 00:22:10.018961 [Gating] SW mode calibration
3414 00:22:10.019014 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3415 00:22:10.019067 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3416 00:22:10.019120 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3417 00:22:10.019172 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3418 00:22:10.019224 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3419 00:22:10.019277 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3420 00:22:10.019329 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3421 00:22:10.019381 0 15 20 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
3422 00:22:10.019433 0 15 24 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
3423 00:22:10.019510 0 15 28 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
3424 00:22:10.019594 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3425 00:22:10.019676 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3426 00:22:10.019758 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3427 00:22:10.019849 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3428 00:22:10.019935 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3429 00:22:10.020020 1 0 20 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
3430 00:22:10.020102 1 0 24 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
3431 00:22:10.020184 1 0 28 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
3432 00:22:10.020268 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3433 00:22:10.020333 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3434 00:22:10.020386 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3435 00:22:10.020438 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3436 00:22:10.020494 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3437 00:22:10.020559 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3438 00:22:10.020644 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3439 00:22:10.020725 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3440 00:22:10.020809 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3441 00:22:10.020894 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3442 00:22:10.020978 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3443 00:22:10.021060 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3444 00:22:10.021143 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3445 00:22:10.021227 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3446 00:22:10.021357 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3447 00:22:10.021443 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3448 00:22:10.021526 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3449 00:22:10.021608 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3450 00:22:10.021693 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3451 00:22:10.021776 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3452 00:22:10.021859 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3453 00:22:10.021943 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3454 00:22:10.022028 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3455 00:22:10.022110 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3456 00:22:10.022194 Total UI for P1: 0, mck2ui 16
3457 00:22:10.022278 best dqsien dly found for B0: ( 1, 3, 24)
3458 00:22:10.022360 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3459 00:22:10.022443 Total UI for P1: 0, mck2ui 16
3460 00:22:10.022522 best dqsien dly found for B1: ( 1, 3, 26)
3461 00:22:10.022577 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3462 00:22:10.022653 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3463 00:22:10.022737
3464 00:22:10.022820 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3465 00:22:10.022905 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3466 00:22:10.022989 [Gating] SW calibration Done
3467 00:22:10.023070 ==
3468 00:22:10.023153 Dram Type= 6, Freq= 0, CH_1, rank 1
3469 00:22:10.023235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3470 00:22:10.023319 ==
3471 00:22:10.023404 RX Vref Scan: 0
3472 00:22:10.023490
3473 00:22:10.023573 RX Vref 0 -> 0, step: 1
3474 00:22:10.023654
3475 00:22:10.023738 RX Delay -40 -> 252, step: 8
3476 00:22:10.023816 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3477 00:22:10.023871 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3478 00:22:10.023923 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3479 00:22:10.023975 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3480 00:22:10.024040 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3481 00:22:10.024142 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3482 00:22:10.024238 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3483 00:22:10.024319 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3484 00:22:10.024400 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3485 00:22:10.024486 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3486 00:22:10.024569 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3487 00:22:10.024651 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3488 00:22:10.024735 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3489 00:22:10.024823 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3490 00:22:10.024905 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3491 00:22:10.024987 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3492 00:22:10.025066 ==
3493 00:22:10.025147 Dram Type= 6, Freq= 0, CH_1, rank 1
3494 00:22:10.025230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3495 00:22:10.025353 ==
3496 00:22:10.025408 DQS Delay:
3497 00:22:10.025475 DQS0 = 0, DQS1 = 0
3498 00:22:10.025526 DQM Delay:
3499 00:22:10.025579 DQM0 = 115, DQM1 = 111
3500 00:22:10.025631 DQ Delay:
3501 00:22:10.025683 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3502 00:22:10.025735 DQ4 =115, DQ5 =127, DQ6 =119, DQ7 =111
3503 00:22:10.025787 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =107
3504 00:22:10.026057 DQ12 =123, DQ13 =119, DQ14 =115, DQ15 =119
3505 00:22:10.026123
3506 00:22:10.026178
3507 00:22:10.026230 ==
3508 00:22:10.026312 Dram Type= 6, Freq= 0, CH_1, rank 1
3509 00:22:10.026394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3510 00:22:10.026491 ==
3511 00:22:10.026598
3512 00:22:10.026680
3513 00:22:10.026763 TX Vref Scan disable
3514 00:22:10.026847 == TX Byte 0 ==
3515 00:22:10.026928 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3516 00:22:10.027010 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3517 00:22:10.027094 == TX Byte 1 ==
3518 00:22:10.027178 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3519 00:22:10.027261 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3520 00:22:10.027345 ==
3521 00:22:10.027428 Dram Type= 6, Freq= 0, CH_1, rank 1
3522 00:22:10.027512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3523 00:22:10.027596 ==
3524 00:22:10.027694 TX Vref=22, minBit 3, minWin=25, winSum=419
3525 00:22:10.027791 TX Vref=24, minBit 2, minWin=25, winSum=420
3526 00:22:10.027875 TX Vref=26, minBit 9, minWin=25, winSum=423
3527 00:22:10.027957 TX Vref=28, minBit 3, minWin=26, winSum=432
3528 00:22:10.028041 TX Vref=30, minBit 3, minWin=26, winSum=430
3529 00:22:10.028125 TX Vref=32, minBit 8, minWin=26, winSum=434
3530 00:22:10.028210 [TxChooseVref] Worse bit 8, Min win 26, Win sum 434, Final Vref 32
3531 00:22:10.028294
3532 00:22:10.028369 Final TX Range 1 Vref 32
3533 00:22:10.028424
3534 00:22:10.028482 ==
3535 00:22:10.028535 Dram Type= 6, Freq= 0, CH_1, rank 1
3536 00:22:10.028609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3537 00:22:10.028700 ==
3538 00:22:10.028787
3539 00:22:10.028867
3540 00:22:10.028950 TX Vref Scan disable
3541 00:22:10.029033 == TX Byte 0 ==
3542 00:22:10.029115 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3543 00:22:10.029199 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3544 00:22:10.029325 == TX Byte 1 ==
3545 00:22:10.029381 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3546 00:22:10.029435 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3547 00:22:10.029513
3548 00:22:10.029598 [DATLAT]
3549 00:22:10.029690 Freq=1200, CH1 RK1
3550 00:22:10.029773
3551 00:22:10.029858 DATLAT Default: 0xd
3552 00:22:10.029942 0, 0xFFFF, sum = 0
3553 00:22:10.030026 1, 0xFFFF, sum = 0
3554 00:22:10.030112 2, 0xFFFF, sum = 0
3555 00:22:10.030198 3, 0xFFFF, sum = 0
3556 00:22:10.030283 4, 0xFFFF, sum = 0
3557 00:22:10.030366 5, 0xFFFF, sum = 0
3558 00:22:10.030449 6, 0xFFFF, sum = 0
3559 00:22:10.030531 7, 0xFFFF, sum = 0
3560 00:22:10.030613 8, 0xFFFF, sum = 0
3561 00:22:10.030696 9, 0xFFFF, sum = 0
3562 00:22:10.030778 10, 0xFFFF, sum = 0
3563 00:22:10.030861 11, 0xFFFF, sum = 0
3564 00:22:10.030944 12, 0x0, sum = 1
3565 00:22:10.031067 13, 0x0, sum = 2
3566 00:22:10.031150 14, 0x0, sum = 3
3567 00:22:10.031232 15, 0x0, sum = 4
3568 00:22:10.031315 best_step = 13
3569 00:22:10.031395
3570 00:22:10.031475 ==
3571 00:22:10.031556 Dram Type= 6, Freq= 0, CH_1, rank 1
3572 00:22:10.031644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3573 00:22:10.031732 ==
3574 00:22:10.031816 RX Vref Scan: 0
3575 00:22:10.031898
3576 00:22:10.031981 RX Vref 0 -> 0, step: 1
3577 00:22:10.032063
3578 00:22:10.032147 RX Delay -13 -> 252, step: 4
3579 00:22:10.032230 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3580 00:22:10.032313 iDelay=195, Bit 1, Center 110 (43 ~ 178) 136
3581 00:22:10.032394 iDelay=195, Bit 2, Center 106 (39 ~ 174) 136
3582 00:22:10.032453 iDelay=195, Bit 3, Center 114 (47 ~ 182) 136
3583 00:22:10.032540 iDelay=195, Bit 4, Center 114 (47 ~ 182) 136
3584 00:22:10.032621 iDelay=195, Bit 5, Center 124 (55 ~ 194) 140
3585 00:22:10.032702 iDelay=195, Bit 6, Center 122 (55 ~ 190) 136
3586 00:22:10.032783 iDelay=195, Bit 7, Center 112 (43 ~ 182) 140
3587 00:22:10.032869 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3588 00:22:10.032954 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3589 00:22:10.033035 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3590 00:22:10.033116 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3591 00:22:10.033197 iDelay=195, Bit 12, Center 118 (55 ~ 182) 128
3592 00:22:10.033322 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3593 00:22:10.033377 iDelay=195, Bit 14, Center 116 (55 ~ 178) 124
3594 00:22:10.033429 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3595 00:22:10.033482 ==
3596 00:22:10.033561 Dram Type= 6, Freq= 0, CH_1, rank 1
3597 00:22:10.033630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3598 00:22:10.033685 ==
3599 00:22:10.033741 DQS Delay:
3600 00:22:10.033793 DQS0 = 0, DQS1 = 0
3601 00:22:10.033844 DQM Delay:
3602 00:22:10.033895 DQM0 = 115, DQM1 = 111
3603 00:22:10.033947 DQ Delay:
3604 00:22:10.034026 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114
3605 00:22:10.034110 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =112
3606 00:22:10.034191 DQ8 =98, DQ9 =102, DQ10 =114, DQ11 =106
3607 00:22:10.034274 DQ12 =118, DQ13 =118, DQ14 =116, DQ15 =120
3608 00:22:10.034356
3609 00:22:10.034438
3610 00:22:10.034520 [DQSOSCAuto] RK1, (LSB)MR18= 0xfa0c, (MSB)MR19= 0x304, tDQSOscB0 = 405 ps tDQSOscB1 = 412 ps
3611 00:22:10.034603 CH1 RK1: MR19=304, MR18=FA0C
3612 00:22:10.034762 CH1_RK1: MR19=0x304, MR18=0xFA0C, DQSOSC=405, MR23=63, INC=39, DEC=26
3613 00:22:10.034846 [RxdqsGatingPostProcess] freq 1200
3614 00:22:10.034929 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3615 00:22:10.035011 best DQS0 dly(2T, 0.5T) = (0, 11)
3616 00:22:10.035095 best DQS1 dly(2T, 0.5T) = (0, 11)
3617 00:22:10.035178 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3618 00:22:10.035259 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3619 00:22:10.035340 best DQS0 dly(2T, 0.5T) = (0, 11)
3620 00:22:10.035421 best DQS1 dly(2T, 0.5T) = (0, 11)
3621 00:22:10.035501 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3622 00:22:10.035582 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3623 00:22:10.035663 Pre-setting of DQS Precalculation
3624 00:22:10.035744 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3625 00:22:10.035826 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3626 00:22:10.035909 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3627 00:22:10.035989
3628 00:22:10.036069
3629 00:22:10.036149 [Calibration Summary] 2400 Mbps
3630 00:22:10.036230 CH 0, Rank 0
3631 00:22:10.036310 SW Impedance : PASS
3632 00:22:10.036391 DUTY Scan : NO K
3633 00:22:10.036472 ZQ Calibration : PASS
3634 00:22:10.036552 Jitter Meter : NO K
3635 00:22:10.036633 CBT Training : PASS
3636 00:22:10.036714 Write leveling : PASS
3637 00:22:10.036794 RX DQS gating : PASS
3638 00:22:10.036877 RX DQ/DQS(RDDQC) : PASS
3639 00:22:10.036958 TX DQ/DQS : PASS
3640 00:22:10.037039 RX DATLAT : PASS
3641 00:22:10.037119 RX DQ/DQS(Engine): PASS
3642 00:22:10.037200 TX OE : NO K
3643 00:22:10.037307 All Pass.
3644 00:22:10.037402
3645 00:22:10.037483 CH 0, Rank 1
3646 00:22:10.037563 SW Impedance : PASS
3647 00:22:10.037647 DUTY Scan : NO K
3648 00:22:10.037944 ZQ Calibration : PASS
3649 00:22:10.038012 Jitter Meter : NO K
3650 00:22:10.038071 CBT Training : PASS
3651 00:22:10.038133 Write leveling : PASS
3652 00:22:10.038187 RX DQS gating : PASS
3653 00:22:10.038239 RX DQ/DQS(RDDQC) : PASS
3654 00:22:10.038292 TX DQ/DQS : PASS
3655 00:22:10.038350 RX DATLAT : PASS
3656 00:22:10.038403 RX DQ/DQS(Engine): PASS
3657 00:22:10.038455 TX OE : NO K
3658 00:22:10.038506 All Pass.
3659 00:22:10.038558
3660 00:22:10.038610 CH 1, Rank 0
3661 00:22:10.038668 SW Impedance : PASS
3662 00:22:10.038721 DUTY Scan : NO K
3663 00:22:10.038773 ZQ Calibration : PASS
3664 00:22:10.038825 Jitter Meter : NO K
3665 00:22:10.038878 CBT Training : PASS
3666 00:22:10.038930 Write leveling : PASS
3667 00:22:10.038987 RX DQS gating : PASS
3668 00:22:10.039039 RX DQ/DQS(RDDQC) : PASS
3669 00:22:10.039090 TX DQ/DQS : PASS
3670 00:22:10.039144 RX DATLAT : PASS
3671 00:22:10.039226 RX DQ/DQS(Engine): PASS
3672 00:22:10.039307 TX OE : NO K
3673 00:22:10.039388 All Pass.
3674 00:22:10.039478
3675 00:22:10.039561 CH 1, Rank 1
3676 00:22:10.039641 SW Impedance : PASS
3677 00:22:10.039722 DUTY Scan : NO K
3678 00:22:10.039802 ZQ Calibration : PASS
3679 00:22:10.039882 Jitter Meter : NO K
3680 00:22:10.039980 CBT Training : PASS
3681 00:22:10.040063 Write leveling : PASS
3682 00:22:10.040153 RX DQS gating : PASS
3683 00:22:10.040254 RX DQ/DQS(RDDQC) : PASS
3684 00:22:10.040349 TX DQ/DQS : PASS
3685 00:22:10.040430 RX DATLAT : PASS
3686 00:22:10.040509 RX DQ/DQS(Engine): PASS
3687 00:22:10.040563 TX OE : NO K
3688 00:22:10.040616 All Pass.
3689 00:22:10.040668
3690 00:22:10.040737 DramC Write-DBI off
3691 00:22:10.040822 PER_BANK_REFRESH: Hybrid Mode
3692 00:22:10.040906 TX_TRACKING: ON
3693 00:22:10.040991 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3694 00:22:10.041074 [FAST_K] Save calibration result to emmc
3695 00:22:10.041171 dramc_set_vcore_voltage set vcore to 650000
3696 00:22:10.041254 Read voltage for 600, 5
3697 00:22:10.041338 Vio18 = 0
3698 00:22:10.041391 Vcore = 650000
3699 00:22:10.041443 Vdram = 0
3700 00:22:10.041495 Vddq = 0
3701 00:22:10.041547 Vmddr = 0
3702 00:22:10.041598 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3703 00:22:10.041657 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3704 00:22:10.041710 MEM_TYPE=3, freq_sel=19
3705 00:22:10.041762 sv_algorithm_assistance_LP4_1600
3706 00:22:10.041814 ============ PULL DRAM RESETB DOWN ============
3707 00:22:10.041866 ========== PULL DRAM RESETB DOWN end =========
3708 00:22:10.041918 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3709 00:22:10.041976 ===================================
3710 00:22:10.042033 LPDDR4 DRAM CONFIGURATION
3711 00:22:10.042085 ===================================
3712 00:22:10.042138 EX_ROW_EN[0] = 0x0
3713 00:22:10.042190 EX_ROW_EN[1] = 0x0
3714 00:22:10.042242 LP4Y_EN = 0x0
3715 00:22:10.042298 WORK_FSP = 0x0
3716 00:22:10.042350 WL = 0x2
3717 00:22:10.042401 RL = 0x2
3718 00:22:10.042452 BL = 0x2
3719 00:22:10.042503 RPST = 0x0
3720 00:22:10.042554 RD_PRE = 0x0
3721 00:22:10.042606 WR_PRE = 0x1
3722 00:22:10.042662 WR_PST = 0x0
3723 00:22:10.042713 DBI_WR = 0x0
3724 00:22:10.042764 DBI_RD = 0x0
3725 00:22:10.042815 OTF = 0x1
3726 00:22:10.042867 ===================================
3727 00:22:10.042919 ===================================
3728 00:22:10.043002 ANA top config
3729 00:22:10.043083 ===================================
3730 00:22:10.043164 DLL_ASYNC_EN = 0
3731 00:22:10.043245 ALL_SLAVE_EN = 1
3732 00:22:10.043329 NEW_RANK_MODE = 1
3733 00:22:10.043411 DLL_IDLE_MODE = 1
3734 00:22:10.043491 LP45_APHY_COMB_EN = 1
3735 00:22:10.043572 TX_ODT_DIS = 1
3736 00:22:10.043655 NEW_8X_MODE = 1
3737 00:22:10.043737 ===================================
3738 00:22:10.043820 ===================================
3739 00:22:10.043901 data_rate = 1200
3740 00:22:10.043987 CKR = 1
3741 00:22:10.044068 DQ_P2S_RATIO = 8
3742 00:22:10.044149 ===================================
3743 00:22:10.044230 CA_P2S_RATIO = 8
3744 00:22:10.044311 DQ_CA_OPEN = 0
3745 00:22:10.044391 DQ_SEMI_OPEN = 0
3746 00:22:10.044472 CA_SEMI_OPEN = 0
3747 00:22:10.044553 CA_FULL_RATE = 0
3748 00:22:10.044641 DQ_CKDIV4_EN = 1
3749 00:22:10.044735 CA_CKDIV4_EN = 1
3750 00:22:10.044819 CA_PREDIV_EN = 0
3751 00:22:10.044903 PH8_DLY = 0
3752 00:22:10.044985 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3753 00:22:10.045065 DQ_AAMCK_DIV = 4
3754 00:22:10.045146 CA_AAMCK_DIV = 4
3755 00:22:10.045227 CA_ADMCK_DIV = 4
3756 00:22:10.045350 DQ_TRACK_CA_EN = 0
3757 00:22:10.045431 CA_PICK = 600
3758 00:22:10.045513 CA_MCKIO = 600
3759 00:22:10.045594 MCKIO_SEMI = 0
3760 00:22:10.045708 PLL_FREQ = 2288
3761 00:22:10.045803 DQ_UI_PI_RATIO = 32
3762 00:22:10.045887 CA_UI_PI_RATIO = 0
3763 00:22:10.045968 ===================================
3764 00:22:10.046052 ===================================
3765 00:22:10.046115 memory_type:LPDDR4
3766 00:22:10.046168 GP_NUM : 10
3767 00:22:10.046232 SRAM_EN : 1
3768 00:22:10.046288 MD32_EN : 0
3769 00:22:10.046341 ===================================
3770 00:22:10.046394 [ANA_INIT] >>>>>>>>>>>>>>
3771 00:22:10.046446 <<<<<< [CONFIGURE PHASE]: ANA_TX
3772 00:22:10.046499 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3773 00:22:10.046551 ===================================
3774 00:22:10.046603 data_rate = 1200,PCW = 0X5800
3775 00:22:10.046655 ===================================
3776 00:22:10.046707 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3777 00:22:10.046761 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3778 00:22:10.046813 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3779 00:22:10.046865 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3780 00:22:10.046918 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3781 00:22:10.046970 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3782 00:22:10.047022 [ANA_INIT] flow start
3783 00:22:10.047073 [ANA_INIT] PLL >>>>>>>>
3784 00:22:10.047125 [ANA_INIT] PLL <<<<<<<<
3785 00:22:10.047177 [ANA_INIT] MIDPI >>>>>>>>
3786 00:22:10.047229 [ANA_INIT] MIDPI <<<<<<<<
3787 00:22:10.047280 [ANA_INIT] DLL >>>>>>>>
3788 00:22:10.047331 [ANA_INIT] flow end
3789 00:22:10.047596 ============ LP4 DIFF to SE enter ============
3790 00:22:10.047656 ============ LP4 DIFF to SE exit ============
3791 00:22:10.047710 [ANA_INIT] <<<<<<<<<<<<<
3792 00:22:10.047762 [Flow] Enable top DCM control >>>>>
3793 00:22:10.047821 [Flow] Enable top DCM control <<<<<
3794 00:22:10.047874 Enable DLL master slave shuffle
3795 00:22:10.047926 ==============================================================
3796 00:22:10.047988 Gating Mode config
3797 00:22:10.048049 ==============================================================
3798 00:22:10.048102 Config description:
3799 00:22:10.048159 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3800 00:22:10.048213 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3801 00:22:10.048295 SELPH_MODE 0: By rank 1: By Phase
3802 00:22:10.048422 ==============================================================
3803 00:22:10.048505 GAT_TRACK_EN = 1
3804 00:22:10.048589 RX_GATING_MODE = 2
3805 00:22:10.048671 RX_GATING_TRACK_MODE = 2
3806 00:22:10.048752 SELPH_MODE = 1
3807 00:22:10.048835 PICG_EARLY_EN = 1
3808 00:22:10.048917 VALID_LAT_VALUE = 1
3809 00:22:10.048999 ==============================================================
3810 00:22:10.049081 Enter into Gating configuration >>>>
3811 00:22:10.049163 Exit from Gating configuration <<<<
3812 00:22:10.049278 Enter into DVFS_PRE_config >>>>>
3813 00:22:10.049352 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3814 00:22:10.049407 Exit from DVFS_PRE_config <<<<<
3815 00:22:10.049461 Enter into PICG configuration >>>>
3816 00:22:10.049513 Exit from PICG configuration <<<<
3817 00:22:10.049575 [RX_INPUT] configuration >>>>>
3818 00:22:10.049628 [RX_INPUT] configuration <<<<<
3819 00:22:10.049680 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3820 00:22:10.049750 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3821 00:22:10.054689 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3822 00:22:10.061368 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3823 00:22:10.064249 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3824 00:22:10.070810 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3825 00:22:10.074254 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3826 00:22:10.080769 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3827 00:22:10.084205 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3828 00:22:10.087568 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3829 00:22:10.090794 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3830 00:22:10.097095 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3831 00:22:10.100790 ===================================
3832 00:22:10.103887 LPDDR4 DRAM CONFIGURATION
3833 00:22:10.107093 ===================================
3834 00:22:10.107235 EX_ROW_EN[0] = 0x0
3835 00:22:10.110456 EX_ROW_EN[1] = 0x0
3836 00:22:10.110589 LP4Y_EN = 0x0
3837 00:22:10.113617 WORK_FSP = 0x0
3838 00:22:10.113738 WL = 0x2
3839 00:22:10.117009 RL = 0x2
3840 00:22:10.117140 BL = 0x2
3841 00:22:10.120547 RPST = 0x0
3842 00:22:10.120651 RD_PRE = 0x0
3843 00:22:10.123399 WR_PRE = 0x1
3844 00:22:10.123545 WR_PST = 0x0
3845 00:22:10.126540 DBI_WR = 0x0
3846 00:22:10.130204 DBI_RD = 0x0
3847 00:22:10.130319 OTF = 0x1
3848 00:22:10.133326 ===================================
3849 00:22:10.137060 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3850 00:22:10.139862 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3851 00:22:10.146615 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3852 00:22:10.149772 ===================================
3853 00:22:10.153109 LPDDR4 DRAM CONFIGURATION
3854 00:22:10.156318 ===================================
3855 00:22:10.156613 EX_ROW_EN[0] = 0x10
3856 00:22:10.159507 EX_ROW_EN[1] = 0x0
3857 00:22:10.159706 LP4Y_EN = 0x0
3858 00:22:10.162802 WORK_FSP = 0x0
3859 00:22:10.163022 WL = 0x2
3860 00:22:10.166724 RL = 0x2
3861 00:22:10.166927 BL = 0x2
3862 00:22:10.169884 RPST = 0x0
3863 00:22:10.170106 RD_PRE = 0x0
3864 00:22:10.172803 WR_PRE = 0x1
3865 00:22:10.176461 WR_PST = 0x0
3866 00:22:10.176662 DBI_WR = 0x0
3867 00:22:10.179744 DBI_RD = 0x0
3868 00:22:10.179934 OTF = 0x1
3869 00:22:10.182569 ===================================
3870 00:22:10.189541 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3871 00:22:10.193123 nWR fixed to 30
3872 00:22:10.196561 [ModeRegInit_LP4] CH0 RK0
3873 00:22:10.196755 [ModeRegInit_LP4] CH0 RK1
3874 00:22:10.200093 [ModeRegInit_LP4] CH1 RK0
3875 00:22:10.202891 [ModeRegInit_LP4] CH1 RK1
3876 00:22:10.203051 match AC timing 17
3877 00:22:10.209162 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3878 00:22:10.212694 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3879 00:22:10.215801 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3880 00:22:10.222993 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3881 00:22:10.226388 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3882 00:22:10.226534 ==
3883 00:22:10.229162 Dram Type= 6, Freq= 0, CH_0, rank 0
3884 00:22:10.232561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3885 00:22:10.235530 ==
3886 00:22:10.239459 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3887 00:22:10.245795 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3888 00:22:10.249176 [CA 0] Center 36 (6~67) winsize 62
3889 00:22:10.252063 [CA 1] Center 36 (6~67) winsize 62
3890 00:22:10.255829 [CA 2] Center 34 (4~65) winsize 62
3891 00:22:10.258775 [CA 3] Center 34 (3~65) winsize 63
3892 00:22:10.262386 [CA 4] Center 33 (3~64) winsize 62
3893 00:22:10.265393 [CA 5] Center 33 (2~64) winsize 63
3894 00:22:10.265564
3895 00:22:10.268627 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3896 00:22:10.268788
3897 00:22:10.271807 [CATrainingPosCal] consider 1 rank data
3898 00:22:10.275618 u2DelayCellTimex100 = 270/100 ps
3899 00:22:10.278777 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3900 00:22:10.281628 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3901 00:22:10.284952 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3902 00:22:10.291818 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3903 00:22:10.295085 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3904 00:22:10.298119 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
3905 00:22:10.298296
3906 00:22:10.301920 CA PerBit enable=1, Macro0, CA PI delay=33
3907 00:22:10.302091
3908 00:22:10.304930 [CBTSetCACLKResult] CA Dly = 33
3909 00:22:10.305068 CS Dly: 4 (0~35)
3910 00:22:10.307878 ==
3911 00:22:10.308013 Dram Type= 6, Freq= 0, CH_0, rank 1
3912 00:22:10.314672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3913 00:22:10.314869 ==
3914 00:22:10.318465 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3915 00:22:10.324890 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3916 00:22:10.328726 [CA 0] Center 36 (6~67) winsize 62
3917 00:22:10.331572 [CA 1] Center 36 (6~67) winsize 62
3918 00:22:10.334849 [CA 2] Center 34 (4~65) winsize 62
3919 00:22:10.338600 [CA 3] Center 34 (4~65) winsize 62
3920 00:22:10.341413 [CA 4] Center 34 (3~65) winsize 63
3921 00:22:10.344999 [CA 5] Center 33 (3~64) winsize 62
3922 00:22:10.345162
3923 00:22:10.348089 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3924 00:22:10.348235
3925 00:22:10.351718 [CATrainingPosCal] consider 2 rank data
3926 00:22:10.354778 u2DelayCellTimex100 = 270/100 ps
3927 00:22:10.357999 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3928 00:22:10.364924 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3929 00:22:10.367939 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3930 00:22:10.371644 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3931 00:22:10.374511 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3932 00:22:10.378104 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3933 00:22:10.378285
3934 00:22:10.380989 CA PerBit enable=1, Macro0, CA PI delay=33
3935 00:22:10.381131
3936 00:22:10.384480 [CBTSetCACLKResult] CA Dly = 33
3937 00:22:10.388063 CS Dly: 5 (0~38)
3938 00:22:10.388238
3939 00:22:10.391200 ----->DramcWriteLeveling(PI) begin...
3940 00:22:10.391378 ==
3941 00:22:10.394326 Dram Type= 6, Freq= 0, CH_0, rank 0
3942 00:22:10.397637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3943 00:22:10.397814 ==
3944 00:22:10.400950 Write leveling (Byte 0): 33 => 33
3945 00:22:10.404336 Write leveling (Byte 1): 29 => 29
3946 00:22:10.407444 DramcWriteLeveling(PI) end<-----
3947 00:22:10.407613
3948 00:22:10.407721 ==
3949 00:22:10.410828 Dram Type= 6, Freq= 0, CH_0, rank 0
3950 00:22:10.414379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3951 00:22:10.414550 ==
3952 00:22:10.417489 [Gating] SW mode calibration
3953 00:22:10.424198 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3954 00:22:10.430840 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3955 00:22:10.434143 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3956 00:22:10.437267 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3957 00:22:10.443906 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3958 00:22:10.447283 0 9 12 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
3959 00:22:10.450456 0 9 16 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
3960 00:22:10.457017 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3961 00:22:10.460565 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3962 00:22:10.463453 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3963 00:22:10.469909 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3964 00:22:10.473706 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3965 00:22:10.476432 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3966 00:22:10.483304 0 10 12 | B1->B0 | 2929 3030 | 0 0 | (0 0) (0 0)
3967 00:22:10.486546 0 10 16 | B1->B0 | 3c3c 4242 | 0 0 | (0 0) (0 0)
3968 00:22:10.489636 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3969 00:22:10.496648 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3970 00:22:10.499636 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3971 00:22:10.503007 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3972 00:22:10.509847 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3973 00:22:10.513648 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3974 00:22:10.516041 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3975 00:22:10.523225 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3976 00:22:10.526246 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3977 00:22:10.529189 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3978 00:22:10.536309 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3979 00:22:10.539151 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3980 00:22:10.542347 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3981 00:22:10.549314 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3982 00:22:10.552114 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3983 00:22:10.555596 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3984 00:22:10.562347 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3985 00:22:10.565910 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3986 00:22:10.569372 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3987 00:22:10.575731 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3988 00:22:10.579198 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3989 00:22:10.582334 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3990 00:22:10.588815 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3991 00:22:10.592202 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3992 00:22:10.595528 Total UI for P1: 0, mck2ui 16
3993 00:22:10.598776 best dqsien dly found for B0: ( 0, 13, 12)
3994 00:22:10.602027 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3995 00:22:10.605096 Total UI for P1: 0, mck2ui 16
3996 00:22:10.608515 best dqsien dly found for B1: ( 0, 13, 16)
3997 00:22:10.611827 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
3998 00:22:10.618583 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
3999 00:22:10.618741
4000 00:22:10.621851 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4001 00:22:10.625466 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4002 00:22:10.628563 [Gating] SW calibration Done
4003 00:22:10.628688 ==
4004 00:22:10.631956 Dram Type= 6, Freq= 0, CH_0, rank 0
4005 00:22:10.635189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4006 00:22:10.635314 ==
4007 00:22:10.638333 RX Vref Scan: 0
4008 00:22:10.638453
4009 00:22:10.638553 RX Vref 0 -> 0, step: 1
4010 00:22:10.638644
4011 00:22:10.641497 RX Delay -230 -> 252, step: 16
4012 00:22:10.645329 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4013 00:22:10.651210 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4014 00:22:10.654475 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4015 00:22:10.658111 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4016 00:22:10.661631 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4017 00:22:10.668009 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4018 00:22:10.671334 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4019 00:22:10.674553 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4020 00:22:10.677698 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4021 00:22:10.681017 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4022 00:22:10.687806 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4023 00:22:10.690791 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4024 00:22:10.694416 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4025 00:22:10.697395 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4026 00:22:10.704271 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4027 00:22:10.707597 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4028 00:22:10.707720 ==
4029 00:22:10.710886 Dram Type= 6, Freq= 0, CH_0, rank 0
4030 00:22:10.714112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4031 00:22:10.714197 ==
4032 00:22:10.717224 DQS Delay:
4033 00:22:10.717319 DQS0 = 0, DQS1 = 0
4034 00:22:10.720980 DQM Delay:
4035 00:22:10.721082 DQM0 = 45, DQM1 = 35
4036 00:22:10.721173 DQ Delay:
4037 00:22:10.723895 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4038 00:22:10.727273 DQ4 =49, DQ5 =33, DQ6 =57, DQ7 =57
4039 00:22:10.731144 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4040 00:22:10.733831 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4041 00:22:10.733926
4042 00:22:10.733991
4043 00:22:10.737560 ==
4044 00:22:10.740425 Dram Type= 6, Freq= 0, CH_0, rank 0
4045 00:22:10.743822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4046 00:22:10.743922 ==
4047 00:22:10.743990
4048 00:22:10.744049
4049 00:22:10.747486 TX Vref Scan disable
4050 00:22:10.747573 == TX Byte 0 ==
4051 00:22:10.754090 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4052 00:22:10.757217 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4053 00:22:10.757361 == TX Byte 1 ==
4054 00:22:10.763891 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4055 00:22:10.766866 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4056 00:22:10.766972 ==
4057 00:22:10.770380 Dram Type= 6, Freq= 0, CH_0, rank 0
4058 00:22:10.773943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4059 00:22:10.774048 ==
4060 00:22:10.774117
4061 00:22:10.774177
4062 00:22:10.776907 TX Vref Scan disable
4063 00:22:10.780291 == TX Byte 0 ==
4064 00:22:10.783553 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4065 00:22:10.786830 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4066 00:22:10.790143 == TX Byte 1 ==
4067 00:22:10.793526 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4068 00:22:10.796468 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4069 00:22:10.800032
4070 00:22:10.800130 [DATLAT]
4071 00:22:10.800196 Freq=600, CH0 RK0
4072 00:22:10.800256
4073 00:22:10.803499 DATLAT Default: 0x9
4074 00:22:10.803680 0, 0xFFFF, sum = 0
4075 00:22:10.806377 1, 0xFFFF, sum = 0
4076 00:22:10.806465 2, 0xFFFF, sum = 0
4077 00:22:10.809872 3, 0xFFFF, sum = 0
4078 00:22:10.809963 4, 0xFFFF, sum = 0
4079 00:22:10.813585 5, 0xFFFF, sum = 0
4080 00:22:10.816515 6, 0xFFFF, sum = 0
4081 00:22:10.816615 7, 0xFFFF, sum = 0
4082 00:22:10.816682 8, 0x0, sum = 1
4083 00:22:10.819691 9, 0x0, sum = 2
4084 00:22:10.819780 10, 0x0, sum = 3
4085 00:22:10.823175 11, 0x0, sum = 4
4086 00:22:10.823267 best_step = 9
4087 00:22:10.823331
4088 00:22:10.823389 ==
4089 00:22:10.826332 Dram Type= 6, Freq= 0, CH_0, rank 0
4090 00:22:10.833471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4091 00:22:10.833587 ==
4092 00:22:10.833654 RX Vref Scan: 1
4093 00:22:10.833714
4094 00:22:10.836737 RX Vref 0 -> 0, step: 1
4095 00:22:10.836825
4096 00:22:10.839663 RX Delay -179 -> 252, step: 8
4097 00:22:10.839751
4098 00:22:10.842853 Set Vref, RX VrefLevel [Byte0]: 55
4099 00:22:10.846313 [Byte1]: 48
4100 00:22:10.846408
4101 00:22:10.849598 Final RX Vref Byte 0 = 55 to rank0
4102 00:22:10.853193 Final RX Vref Byte 1 = 48 to rank0
4103 00:22:10.855858 Final RX Vref Byte 0 = 55 to rank1
4104 00:22:10.859375 Final RX Vref Byte 1 = 48 to rank1==
4105 00:22:10.862413 Dram Type= 6, Freq= 0, CH_0, rank 0
4106 00:22:10.865761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4107 00:22:10.865869 ==
4108 00:22:10.869187 DQS Delay:
4109 00:22:10.869299 DQS0 = 0, DQS1 = 0
4110 00:22:10.872721 DQM Delay:
4111 00:22:10.872810 DQM0 = 44, DQM1 = 37
4112 00:22:10.872875 DQ Delay:
4113 00:22:10.875994 DQ0 =48, DQ1 =44, DQ2 =40, DQ3 =40
4114 00:22:10.879431 DQ4 =48, DQ5 =36, DQ6 =52, DQ7 =48
4115 00:22:10.882115 DQ8 =28, DQ9 =24, DQ10 =40, DQ11 =32
4116 00:22:10.885678 DQ12 =44, DQ13 =40, DQ14 =48, DQ15 =44
4117 00:22:10.885773
4118 00:22:10.888853
4119 00:22:10.895225 [DQSOSCAuto] RK0, (LSB)MR18= 0x534a, (MSB)MR19= 0x808, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
4120 00:22:10.898684 CH0 RK0: MR19=808, MR18=534A
4121 00:22:10.905286 CH0_RK0: MR19=0x808, MR18=0x534A, DQSOSC=394, MR23=63, INC=168, DEC=112
4122 00:22:10.905415
4123 00:22:10.908719 ----->DramcWriteLeveling(PI) begin...
4124 00:22:10.908810 ==
4125 00:22:10.912365 Dram Type= 6, Freq= 0, CH_0, rank 1
4126 00:22:10.915313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4127 00:22:10.915402 ==
4128 00:22:10.918687 Write leveling (Byte 0): 34 => 34
4129 00:22:10.921870 Write leveling (Byte 1): 30 => 30
4130 00:22:10.925139 DramcWriteLeveling(PI) end<-----
4131 00:22:10.925279
4132 00:22:10.925363 ==
4133 00:22:10.928406 Dram Type= 6, Freq= 0, CH_0, rank 1
4134 00:22:10.931972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4135 00:22:10.932140 ==
4136 00:22:10.935352 [Gating] SW mode calibration
4137 00:22:10.942038 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4138 00:22:10.948593 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4139 00:22:10.951827 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4140 00:22:10.958178 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4141 00:22:10.961231 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4142 00:22:10.964598 0 9 12 | B1->B0 | 3333 3030 | 1 0 | (1 1) (0 0)
4143 00:22:10.971226 0 9 16 | B1->B0 | 2f2f 2424 | 0 0 | (0 0) (0 0)
4144 00:22:10.975169 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4145 00:22:10.978054 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4146 00:22:10.984582 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4147 00:22:10.987986 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4148 00:22:10.990859 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4149 00:22:10.997590 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4150 00:22:11.000701 0 10 12 | B1->B0 | 2424 3333 | 0 1 | (0 0) (0 0)
4151 00:22:11.004098 0 10 16 | B1->B0 | 3c3c 4545 | 1 0 | (0 0) (0 0)
4152 00:22:11.011063 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4153 00:22:11.014529 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4154 00:22:11.017537 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4155 00:22:11.024377 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4156 00:22:11.027733 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4157 00:22:11.030908 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4158 00:22:11.037303 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4159 00:22:11.040364 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4160 00:22:11.043745 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4161 00:22:11.050227 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4162 00:22:11.053810 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4163 00:22:11.057128 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4164 00:22:11.063565 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4165 00:22:11.066973 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4166 00:22:11.070024 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4167 00:22:11.076583 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4168 00:22:11.080018 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4169 00:22:11.083374 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4170 00:22:11.090203 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4171 00:22:11.093196 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4172 00:22:11.096892 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4173 00:22:11.103002 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4174 00:22:11.106140 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4175 00:22:11.109979 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4176 00:22:11.113617 Total UI for P1: 0, mck2ui 16
4177 00:22:11.116673 best dqsien dly found for B0: ( 0, 13, 12)
4178 00:22:11.119631 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4179 00:22:11.123197 Total UI for P1: 0, mck2ui 16
4180 00:22:11.126067 best dqsien dly found for B1: ( 0, 13, 14)
4181 00:22:11.132521 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4182 00:22:11.135917 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4183 00:22:11.136018
4184 00:22:11.139231 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4185 00:22:11.142437 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4186 00:22:11.146212 [Gating] SW calibration Done
4187 00:22:11.146302 ==
4188 00:22:11.149710 Dram Type= 6, Freq= 0, CH_0, rank 1
4189 00:22:11.152773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4190 00:22:11.152871 ==
4191 00:22:11.155666 RX Vref Scan: 0
4192 00:22:11.155749
4193 00:22:11.155814 RX Vref 0 -> 0, step: 1
4194 00:22:11.155875
4195 00:22:11.158977 RX Delay -230 -> 252, step: 16
4196 00:22:11.165801 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4197 00:22:11.169116 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4198 00:22:11.172496 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4199 00:22:11.175480 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4200 00:22:11.179055 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4201 00:22:11.185485 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4202 00:22:11.188979 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4203 00:22:11.192435 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4204 00:22:11.195218 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4205 00:22:11.201969 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4206 00:22:11.204896 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4207 00:22:11.208400 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4208 00:22:11.211594 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4209 00:22:11.218589 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4210 00:22:11.221739 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4211 00:22:11.224718 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4212 00:22:11.224820 ==
4213 00:22:11.228175 Dram Type= 6, Freq= 0, CH_0, rank 1
4214 00:22:11.234834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4215 00:22:11.234944 ==
4216 00:22:11.235014 DQS Delay:
4217 00:22:11.235076 DQS0 = 0, DQS1 = 0
4218 00:22:11.238364 DQM Delay:
4219 00:22:11.238458 DQM0 = 49, DQM1 = 38
4220 00:22:11.241059 DQ Delay:
4221 00:22:11.244582 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4222 00:22:11.248077 DQ4 =49, DQ5 =33, DQ6 =57, DQ7 =57
4223 00:22:11.251317 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =25
4224 00:22:11.254574 DQ12 =41, DQ13 =41, DQ14 =57, DQ15 =49
4225 00:22:11.254664
4226 00:22:11.254729
4227 00:22:11.254790 ==
4228 00:22:11.257960 Dram Type= 6, Freq= 0, CH_0, rank 1
4229 00:22:11.260874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4230 00:22:11.260959 ==
4231 00:22:11.261025
4232 00:22:11.261085
4233 00:22:11.264343 TX Vref Scan disable
4234 00:22:11.264426 == TX Byte 0 ==
4235 00:22:11.271173 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4236 00:22:11.274019 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4237 00:22:11.277510 == TX Byte 1 ==
4238 00:22:11.280752 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4239 00:22:11.283661 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4240 00:22:11.283750 ==
4241 00:22:11.287105 Dram Type= 6, Freq= 0, CH_0, rank 1
4242 00:22:11.290342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4243 00:22:11.293751 ==
4244 00:22:11.293850
4245 00:22:11.293918
4246 00:22:11.293979 TX Vref Scan disable
4247 00:22:11.297809 == TX Byte 0 ==
4248 00:22:11.300956 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4249 00:22:11.307604 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4250 00:22:11.307716 == TX Byte 1 ==
4251 00:22:11.310943 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4252 00:22:11.317407 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4253 00:22:11.317552
4254 00:22:11.317633 [DATLAT]
4255 00:22:11.317703 Freq=600, CH0 RK1
4256 00:22:11.317770
4257 00:22:11.321208 DATLAT Default: 0x9
4258 00:22:11.321336 0, 0xFFFF, sum = 0
4259 00:22:11.324174 1, 0xFFFF, sum = 0
4260 00:22:11.327528 2, 0xFFFF, sum = 0
4261 00:22:11.327667 3, 0xFFFF, sum = 0
4262 00:22:11.330757 4, 0xFFFF, sum = 0
4263 00:22:11.330853 5, 0xFFFF, sum = 0
4264 00:22:11.334110 6, 0xFFFF, sum = 0
4265 00:22:11.334198 7, 0xFFFF, sum = 0
4266 00:22:11.337592 8, 0x0, sum = 1
4267 00:22:11.337670 9, 0x0, sum = 2
4268 00:22:11.341029 10, 0x0, sum = 3
4269 00:22:11.341105 11, 0x0, sum = 4
4270 00:22:11.341175 best_step = 9
4271 00:22:11.341235
4272 00:22:11.343971 ==
4273 00:22:11.344056 Dram Type= 6, Freq= 0, CH_0, rank 1
4274 00:22:11.350858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4275 00:22:11.350959 ==
4276 00:22:11.351026 RX Vref Scan: 0
4277 00:22:11.351096
4278 00:22:11.353647 RX Vref 0 -> 0, step: 1
4279 00:22:11.353733
4280 00:22:11.357077 RX Delay -179 -> 252, step: 8
4281 00:22:11.363953 iDelay=197, Bit 0, Center 40 (-107 ~ 188) 296
4282 00:22:11.367081 iDelay=197, Bit 1, Center 48 (-99 ~ 196) 296
4283 00:22:11.370175 iDelay=197, Bit 2, Center 40 (-107 ~ 188) 296
4284 00:22:11.373747 iDelay=197, Bit 3, Center 40 (-107 ~ 188) 296
4285 00:22:11.376906 iDelay=197, Bit 4, Center 48 (-99 ~ 196) 296
4286 00:22:11.383300 iDelay=197, Bit 5, Center 32 (-115 ~ 180) 296
4287 00:22:11.386817 iDelay=197, Bit 6, Center 52 (-91 ~ 196) 288
4288 00:22:11.390254 iDelay=197, Bit 7, Center 52 (-91 ~ 196) 288
4289 00:22:11.393513 iDelay=197, Bit 8, Center 28 (-123 ~ 180) 304
4290 00:22:11.396928 iDelay=197, Bit 9, Center 24 (-131 ~ 180) 312
4291 00:22:11.403346 iDelay=197, Bit 10, Center 36 (-115 ~ 188) 304
4292 00:22:11.407035 iDelay=197, Bit 11, Center 32 (-115 ~ 180) 296
4293 00:22:11.410252 iDelay=197, Bit 12, Center 40 (-107 ~ 188) 296
4294 00:22:11.413290 iDelay=197, Bit 13, Center 40 (-107 ~ 188) 296
4295 00:22:11.420003 iDelay=197, Bit 14, Center 48 (-99 ~ 196) 296
4296 00:22:11.422782 iDelay=197, Bit 15, Center 44 (-107 ~ 196) 304
4297 00:22:11.422873 ==
4298 00:22:11.426423 Dram Type= 6, Freq= 0, CH_0, rank 1
4299 00:22:11.429703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4300 00:22:11.429790 ==
4301 00:22:11.433035 DQS Delay:
4302 00:22:11.433111 DQS0 = 0, DQS1 = 0
4303 00:22:11.436476 DQM Delay:
4304 00:22:11.436567 DQM0 = 44, DQM1 = 36
4305 00:22:11.436639 DQ Delay:
4306 00:22:11.439846 DQ0 =40, DQ1 =48, DQ2 =40, DQ3 =40
4307 00:22:11.443094 DQ4 =48, DQ5 =32, DQ6 =52, DQ7 =52
4308 00:22:11.446314 DQ8 =28, DQ9 =24, DQ10 =36, DQ11 =32
4309 00:22:11.449632 DQ12 =40, DQ13 =40, DQ14 =48, DQ15 =44
4310 00:22:11.449740
4311 00:22:11.449811
4312 00:22:11.459671 [DQSOSCAuto] RK1, (LSB)MR18= 0x4b46, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
4313 00:22:11.462630 CH0 RK1: MR19=808, MR18=4B46
4314 00:22:11.469805 CH0_RK1: MR19=0x808, MR18=0x4B46, DQSOSC=395, MR23=63, INC=168, DEC=112
4315 00:22:11.469950 [RxdqsGatingPostProcess] freq 600
4316 00:22:11.475995 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4317 00:22:11.478978 Pre-setting of DQS Precalculation
4318 00:22:11.482824 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4319 00:22:11.485674 ==
4320 00:22:11.489431 Dram Type= 6, Freq= 0, CH_1, rank 0
4321 00:22:11.492583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4322 00:22:11.492701 ==
4323 00:22:11.495688 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4324 00:22:11.502085 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4325 00:22:11.506399 [CA 0] Center 35 (5~66) winsize 62
4326 00:22:11.509824 [CA 1] Center 35 (5~66) winsize 62
4327 00:22:11.513340 [CA 2] Center 35 (5~65) winsize 61
4328 00:22:11.516005 [CA 3] Center 34 (3~65) winsize 63
4329 00:22:11.519870 [CA 4] Center 34 (4~65) winsize 62
4330 00:22:11.523002 [CA 5] Center 34 (3~65) winsize 63
4331 00:22:11.523110
4332 00:22:11.526024 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4333 00:22:11.526113
4334 00:22:11.529230 [CATrainingPosCal] consider 1 rank data
4335 00:22:11.532810 u2DelayCellTimex100 = 270/100 ps
4336 00:22:11.535952 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4337 00:22:11.542282 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4338 00:22:11.545852 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4339 00:22:11.549195 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
4340 00:22:11.552470 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4341 00:22:11.556143 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4342 00:22:11.556229
4343 00:22:11.558980 CA PerBit enable=1, Macro0, CA PI delay=34
4344 00:22:11.559062
4345 00:22:11.562486 [CBTSetCACLKResult] CA Dly = 34
4346 00:22:11.562569 CS Dly: 5 (0~36)
4347 00:22:11.565755 ==
4348 00:22:11.569162 Dram Type= 6, Freq= 0, CH_1, rank 1
4349 00:22:11.572554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4350 00:22:11.572639 ==
4351 00:22:11.578921 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4352 00:22:11.582280 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4353 00:22:11.586102 [CA 0] Center 35 (5~66) winsize 62
4354 00:22:11.589345 [CA 1] Center 35 (5~66) winsize 62
4355 00:22:11.592547 [CA 2] Center 34 (4~65) winsize 62
4356 00:22:11.596004 [CA 3] Center 34 (3~65) winsize 63
4357 00:22:11.599816 [CA 4] Center 34 (3~65) winsize 63
4358 00:22:11.602435 [CA 5] Center 33 (3~64) winsize 62
4359 00:22:11.602548
4360 00:22:11.606235 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4361 00:22:11.606325
4362 00:22:11.608953 [CATrainingPosCal] consider 2 rank data
4363 00:22:11.612593 u2DelayCellTimex100 = 270/100 ps
4364 00:22:11.616130 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4365 00:22:11.622756 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4366 00:22:11.625684 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
4367 00:22:11.629221 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4368 00:22:11.632331 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4369 00:22:11.635368 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4370 00:22:11.635458
4371 00:22:11.638869 CA PerBit enable=1, Macro0, CA PI delay=33
4372 00:22:11.638957
4373 00:22:11.641969 [CBTSetCACLKResult] CA Dly = 33
4374 00:22:11.645441 CS Dly: 4 (0~35)
4375 00:22:11.645527
4376 00:22:11.648887 ----->DramcWriteLeveling(PI) begin...
4377 00:22:11.648973 ==
4378 00:22:11.652268 Dram Type= 6, Freq= 0, CH_1, rank 0
4379 00:22:11.655261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4380 00:22:11.655382 ==
4381 00:22:11.658787 Write leveling (Byte 0): 28 => 28
4382 00:22:11.662125 Write leveling (Byte 1): 30 => 30
4383 00:22:11.664944 DramcWriteLeveling(PI) end<-----
4384 00:22:11.665043
4385 00:22:11.665118 ==
4386 00:22:11.668632 Dram Type= 6, Freq= 0, CH_1, rank 0
4387 00:22:11.671679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4388 00:22:11.671762 ==
4389 00:22:11.675012 [Gating] SW mode calibration
4390 00:22:11.681587 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4391 00:22:11.688369 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4392 00:22:11.691810 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4393 00:22:11.694758 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4394 00:22:11.701890 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4395 00:22:11.705206 0 9 12 | B1->B0 | 2f2f 2f2f | 1 0 | (1 1) (1 0)
4396 00:22:11.708611 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4397 00:22:11.714715 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4398 00:22:11.717858 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4399 00:22:11.721189 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4400 00:22:11.727743 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4401 00:22:11.731365 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4402 00:22:11.734763 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4403 00:22:11.741087 0 10 12 | B1->B0 | 3636 3c3c | 0 0 | (1 1) (0 0)
4404 00:22:11.744354 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4405 00:22:11.751338 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4406 00:22:11.754443 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4407 00:22:11.757436 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4408 00:22:11.764531 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4409 00:22:11.767428 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4410 00:22:11.770654 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4411 00:22:11.777475 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4412 00:22:11.780558 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4413 00:22:11.783791 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4414 00:22:11.790336 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4415 00:22:11.794019 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4416 00:22:11.797390 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4417 00:22:11.800531 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4418 00:22:11.806955 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4419 00:22:11.810153 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4420 00:22:11.813392 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4421 00:22:11.820187 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4422 00:22:11.823184 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4423 00:22:11.827092 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4424 00:22:11.833380 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4425 00:22:11.836410 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4426 00:22:11.839794 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4427 00:22:11.846548 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4428 00:22:11.849826 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4429 00:22:11.853129 Total UI for P1: 0, mck2ui 16
4430 00:22:11.856230 best dqsien dly found for B0: ( 0, 13, 12)
4431 00:22:11.859673 Total UI for P1: 0, mck2ui 16
4432 00:22:11.862965 best dqsien dly found for B1: ( 0, 13, 12)
4433 00:22:11.866362 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4434 00:22:11.869284 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4435 00:22:11.869377
4436 00:22:11.872720 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4437 00:22:11.879595 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4438 00:22:11.879745 [Gating] SW calibration Done
4439 00:22:11.883057 ==
4440 00:22:11.885856 Dram Type= 6, Freq= 0, CH_1, rank 0
4441 00:22:11.889123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4442 00:22:11.889238 ==
4443 00:22:11.889326 RX Vref Scan: 0
4444 00:22:11.889389
4445 00:22:11.892386 RX Vref 0 -> 0, step: 1
4446 00:22:11.892470
4447 00:22:11.895960 RX Delay -230 -> 252, step: 16
4448 00:22:11.899112 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4449 00:22:11.902848 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4450 00:22:11.909247 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4451 00:22:11.912661 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4452 00:22:11.915416 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4453 00:22:11.919190 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4454 00:22:11.925965 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4455 00:22:11.928676 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4456 00:22:11.932014 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4457 00:22:11.935160 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4458 00:22:11.941671 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4459 00:22:11.945169 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4460 00:22:11.948386 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4461 00:22:11.951859 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4462 00:22:11.958136 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4463 00:22:11.962001 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4464 00:22:11.962101 ==
4465 00:22:11.965130 Dram Type= 6, Freq= 0, CH_1, rank 0
4466 00:22:11.968365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4467 00:22:11.968458 ==
4468 00:22:11.971947 DQS Delay:
4469 00:22:11.972035 DQS0 = 0, DQS1 = 0
4470 00:22:11.972102 DQM Delay:
4471 00:22:11.974853 DQM0 = 41, DQM1 = 37
4472 00:22:11.974944 DQ Delay:
4473 00:22:11.978322 DQ0 =49, DQ1 =33, DQ2 =25, DQ3 =41
4474 00:22:11.981440 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =33
4475 00:22:11.984677 DQ8 =17, DQ9 =25, DQ10 =41, DQ11 =33
4476 00:22:11.988236 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41
4477 00:22:11.988333
4478 00:22:11.988400
4479 00:22:11.988460 ==
4480 00:22:11.991508 Dram Type= 6, Freq= 0, CH_1, rank 0
4481 00:22:11.998059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4482 00:22:11.998183 ==
4483 00:22:11.998252
4484 00:22:11.998315
4485 00:22:11.998373 TX Vref Scan disable
4486 00:22:12.001860 == TX Byte 0 ==
4487 00:22:12.004705 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4488 00:22:12.011310 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4489 00:22:12.011425 == TX Byte 1 ==
4490 00:22:12.014881 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4491 00:22:12.021154 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4492 00:22:12.021305 ==
4493 00:22:12.024628 Dram Type= 6, Freq= 0, CH_1, rank 0
4494 00:22:12.028062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4495 00:22:12.028164 ==
4496 00:22:12.028233
4497 00:22:12.028293
4498 00:22:12.031536 TX Vref Scan disable
4499 00:22:12.034327 == TX Byte 0 ==
4500 00:22:12.037615 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4501 00:22:12.041088 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4502 00:22:12.044343 == TX Byte 1 ==
4503 00:22:12.047559 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4504 00:22:12.051030 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4505 00:22:12.051127
4506 00:22:12.054375 [DATLAT]
4507 00:22:12.054468 Freq=600, CH1 RK0
4508 00:22:12.054534
4509 00:22:12.057798 DATLAT Default: 0x9
4510 00:22:12.057895 0, 0xFFFF, sum = 0
4511 00:22:12.060785 1, 0xFFFF, sum = 0
4512 00:22:12.060881 2, 0xFFFF, sum = 0
4513 00:22:12.064254 3, 0xFFFF, sum = 0
4514 00:22:12.064357 4, 0xFFFF, sum = 0
4515 00:22:12.067610 5, 0xFFFF, sum = 0
4516 00:22:12.067711 6, 0xFFFF, sum = 0
4517 00:22:12.070777 7, 0xFFFF, sum = 0
4518 00:22:12.070879 8, 0x0, sum = 1
4519 00:22:12.073943 9, 0x0, sum = 2
4520 00:22:12.074045 10, 0x0, sum = 3
4521 00:22:12.077469 11, 0x0, sum = 4
4522 00:22:12.077576 best_step = 9
4523 00:22:12.077642
4524 00:22:12.077702 ==
4525 00:22:12.080506 Dram Type= 6, Freq= 0, CH_1, rank 0
4526 00:22:12.083903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4527 00:22:12.084004 ==
4528 00:22:12.087499 RX Vref Scan: 1
4529 00:22:12.087599
4530 00:22:12.090599 RX Vref 0 -> 0, step: 1
4531 00:22:12.090701
4532 00:22:12.090767 RX Delay -195 -> 252, step: 8
4533 00:22:12.094043
4534 00:22:12.094153 Set Vref, RX VrefLevel [Byte0]: 50
4535 00:22:12.097496 [Byte1]: 50
4536 00:22:12.102021
4537 00:22:12.102134 Final RX Vref Byte 0 = 50 to rank0
4538 00:22:12.105554 Final RX Vref Byte 1 = 50 to rank0
4539 00:22:12.108715 Final RX Vref Byte 0 = 50 to rank1
4540 00:22:12.111760 Final RX Vref Byte 1 = 50 to rank1==
4541 00:22:12.115390 Dram Type= 6, Freq= 0, CH_1, rank 0
4542 00:22:12.121972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4543 00:22:12.122097 ==
4544 00:22:12.122171 DQS Delay:
4545 00:22:12.125032 DQS0 = 0, DQS1 = 0
4546 00:22:12.125129 DQM Delay:
4547 00:22:12.125196 DQM0 = 41, DQM1 = 35
4548 00:22:12.128542 DQ Delay:
4549 00:22:12.132297 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4550 00:22:12.135112 DQ4 =36, DQ5 =48, DQ6 =52, DQ7 =36
4551 00:22:12.138169 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =28
4552 00:22:12.142104 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =40
4553 00:22:12.142228
4554 00:22:12.142310
4555 00:22:12.148255 [DQSOSCAuto] RK0, (LSB)MR18= 0x314c, (MSB)MR19= 0x808, tDQSOscB0 = 395 ps tDQSOscB1 = 400 ps
4556 00:22:12.151701 CH1 RK0: MR19=808, MR18=314C
4557 00:22:12.158060 CH1_RK0: MR19=0x808, MR18=0x314C, DQSOSC=395, MR23=63, INC=168, DEC=112
4558 00:22:12.158223
4559 00:22:12.161673 ----->DramcWriteLeveling(PI) begin...
4560 00:22:12.161768 ==
4561 00:22:12.165386 Dram Type= 6, Freq= 0, CH_1, rank 1
4562 00:22:12.167644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4563 00:22:12.167747 ==
4564 00:22:12.171117 Write leveling (Byte 0): 29 => 29
4565 00:22:12.174767 Write leveling (Byte 1): 29 => 29
4566 00:22:12.177977 DramcWriteLeveling(PI) end<-----
4567 00:22:12.178069
4568 00:22:12.178134 ==
4569 00:22:12.181204 Dram Type= 6, Freq= 0, CH_1, rank 1
4570 00:22:12.187395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4571 00:22:12.187512 ==
4572 00:22:12.187592 [Gating] SW mode calibration
4573 00:22:12.197355 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4574 00:22:12.200643 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4575 00:22:12.204251 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4576 00:22:12.210970 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4577 00:22:12.214017 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4578 00:22:12.217596 0 9 12 | B1->B0 | 3131 2a2a | 0 0 | (0 0) (0 0)
4579 00:22:12.223826 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4580 00:22:12.227263 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4581 00:22:12.230770 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4582 00:22:12.237231 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4583 00:22:12.240228 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4584 00:22:12.244066 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4585 00:22:12.250190 0 10 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
4586 00:22:12.253430 0 10 12 | B1->B0 | 3131 3c3c | 1 0 | (0 0) (0 0)
4587 00:22:12.256827 0 10 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
4588 00:22:12.263354 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4589 00:22:12.266852 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4590 00:22:12.270200 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4591 00:22:12.276860 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4592 00:22:12.279975 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4593 00:22:12.282934 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4594 00:22:12.289782 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4595 00:22:12.293134 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4596 00:22:12.296179 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4597 00:22:12.303167 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4598 00:22:12.306191 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4599 00:22:12.309599 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4600 00:22:12.316254 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4601 00:22:12.319265 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4602 00:22:12.322794 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4603 00:22:12.329457 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4604 00:22:12.332568 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4605 00:22:12.335919 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4606 00:22:12.342614 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4607 00:22:12.345516 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4608 00:22:12.348847 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4609 00:22:12.355593 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4610 00:22:12.358792 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4611 00:22:12.362203 Total UI for P1: 0, mck2ui 16
4612 00:22:12.365267 best dqsien dly found for B0: ( 0, 13, 10)
4613 00:22:12.368969 Total UI for P1: 0, mck2ui 16
4614 00:22:12.371826 best dqsien dly found for B1: ( 0, 13, 10)
4615 00:22:12.375156 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4616 00:22:12.378802 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4617 00:22:12.378899
4618 00:22:12.381885 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4619 00:22:12.388556 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4620 00:22:12.388667 [Gating] SW calibration Done
4621 00:22:12.391676 ==
4622 00:22:12.391768 Dram Type= 6, Freq= 0, CH_1, rank 1
4623 00:22:12.398497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4624 00:22:12.398611 ==
4625 00:22:12.398680 RX Vref Scan: 0
4626 00:22:12.398739
4627 00:22:12.402198 RX Vref 0 -> 0, step: 1
4628 00:22:12.402283
4629 00:22:12.404873 RX Delay -230 -> 252, step: 16
4630 00:22:12.408237 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4631 00:22:12.411731 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4632 00:22:12.418330 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4633 00:22:12.421470 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4634 00:22:12.424663 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4635 00:22:12.427956 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4636 00:22:12.434523 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4637 00:22:12.437963 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4638 00:22:12.441287 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4639 00:22:12.444834 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4640 00:22:12.447956 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4641 00:22:12.454471 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4642 00:22:12.457889 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4643 00:22:12.461403 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4644 00:22:12.467462 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4645 00:22:12.470660 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4646 00:22:12.470755 ==
4647 00:22:12.473956 Dram Type= 6, Freq= 0, CH_1, rank 1
4648 00:22:12.478110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4649 00:22:12.478198 ==
4650 00:22:12.480896 DQS Delay:
4651 00:22:12.481012 DQS0 = 0, DQS1 = 0
4652 00:22:12.481107 DQM Delay:
4653 00:22:12.483915 DQM0 = 42, DQM1 = 38
4654 00:22:12.484017 DQ Delay:
4655 00:22:12.487259 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4656 00:22:12.490877 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4657 00:22:12.493745 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4658 00:22:12.497203 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4659 00:22:12.497323
4660 00:22:12.497392
4661 00:22:12.497453 ==
4662 00:22:12.500521 Dram Type= 6, Freq= 0, CH_1, rank 1
4663 00:22:12.507060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4664 00:22:12.507158 ==
4665 00:22:12.507227
4666 00:22:12.507287
4667 00:22:12.507347 TX Vref Scan disable
4668 00:22:12.510461 == TX Byte 0 ==
4669 00:22:12.513920 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4670 00:22:12.520823 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4671 00:22:12.520920 == TX Byte 1 ==
4672 00:22:12.523897 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4673 00:22:12.530204 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4674 00:22:12.530307 ==
4675 00:22:12.533911 Dram Type= 6, Freq= 0, CH_1, rank 1
4676 00:22:12.537061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4677 00:22:12.537149 ==
4678 00:22:12.537214
4679 00:22:12.537305
4680 00:22:12.540522 TX Vref Scan disable
4681 00:22:12.543324 == TX Byte 0 ==
4682 00:22:12.547242 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4683 00:22:12.550155 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4684 00:22:12.553566 == TX Byte 1 ==
4685 00:22:12.556715 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4686 00:22:12.559986 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4687 00:22:12.560076
4688 00:22:12.560141 [DATLAT]
4689 00:22:12.563497 Freq=600, CH1 RK1
4690 00:22:12.563580
4691 00:22:12.566880 DATLAT Default: 0x9
4692 00:22:12.566962 0, 0xFFFF, sum = 0
4693 00:22:12.569743 1, 0xFFFF, sum = 0
4694 00:22:12.569826 2, 0xFFFF, sum = 0
4695 00:22:12.573190 3, 0xFFFF, sum = 0
4696 00:22:12.573315 4, 0xFFFF, sum = 0
4697 00:22:12.576802 5, 0xFFFF, sum = 0
4698 00:22:12.576885 6, 0xFFFF, sum = 0
4699 00:22:12.579792 7, 0xFFFF, sum = 0
4700 00:22:12.579876 8, 0x0, sum = 1
4701 00:22:12.582998 9, 0x0, sum = 2
4702 00:22:12.583108 10, 0x0, sum = 3
4703 00:22:12.586186 11, 0x0, sum = 4
4704 00:22:12.586272 best_step = 9
4705 00:22:12.586335
4706 00:22:12.586393 ==
4707 00:22:12.589713 Dram Type= 6, Freq= 0, CH_1, rank 1
4708 00:22:12.592998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4709 00:22:12.593107 ==
4710 00:22:12.596422 RX Vref Scan: 0
4711 00:22:12.596510
4712 00:22:12.599371 RX Vref 0 -> 0, step: 1
4713 00:22:12.599454
4714 00:22:12.599517 RX Delay -179 -> 252, step: 8
4715 00:22:12.607522 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4716 00:22:12.610653 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4717 00:22:12.614400 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4718 00:22:12.617485 iDelay=205, Bit 3, Center 36 (-123 ~ 196) 320
4719 00:22:12.623746 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4720 00:22:12.627048 iDelay=205, Bit 5, Center 44 (-115 ~ 204) 320
4721 00:22:12.630593 iDelay=205, Bit 6, Center 40 (-115 ~ 196) 312
4722 00:22:12.633933 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4723 00:22:12.640713 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4724 00:22:12.643565 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4725 00:22:12.647035 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4726 00:22:12.650580 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4727 00:22:12.656841 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4728 00:22:12.659965 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4729 00:22:12.663730 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4730 00:22:12.666390 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4731 00:22:12.666504 ==
4732 00:22:12.670596 Dram Type= 6, Freq= 0, CH_1, rank 1
4733 00:22:12.676560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4734 00:22:12.676683 ==
4735 00:22:12.676782 DQS Delay:
4736 00:22:12.680105 DQS0 = 0, DQS1 = 0
4737 00:22:12.680214 DQM Delay:
4738 00:22:12.683161 DQM0 = 36, DQM1 = 34
4739 00:22:12.683269 DQ Delay:
4740 00:22:12.686314 DQ0 =40, DQ1 =36, DQ2 =24, DQ3 =36
4741 00:22:12.690019 DQ4 =36, DQ5 =44, DQ6 =40, DQ7 =32
4742 00:22:12.692899 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =24
4743 00:22:12.696185 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =40
4744 00:22:12.696297
4745 00:22:12.696389
4746 00:22:12.702765 [DQSOSCAuto] RK1, (LSB)MR18= 0x4064, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 397 ps
4747 00:22:12.705876 CH1 RK1: MR19=808, MR18=4064
4748 00:22:12.712553 CH1_RK1: MR19=0x808, MR18=0x4064, DQSOSC=391, MR23=63, INC=171, DEC=114
4749 00:22:12.716062 [RxdqsGatingPostProcess] freq 600
4750 00:22:12.722647 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4751 00:22:12.725824 Pre-setting of DQS Precalculation
4752 00:22:12.729474 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4753 00:22:12.735705 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4754 00:22:12.742365 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4755 00:22:12.742467
4756 00:22:12.742535
4757 00:22:12.745711 [Calibration Summary] 1200 Mbps
4758 00:22:12.749011 CH 0, Rank 0
4759 00:22:12.749093 SW Impedance : PASS
4760 00:22:12.752140 DUTY Scan : NO K
4761 00:22:12.755780 ZQ Calibration : PASS
4762 00:22:12.755864 Jitter Meter : NO K
4763 00:22:12.758648 CBT Training : PASS
4764 00:22:12.762298 Write leveling : PASS
4765 00:22:12.762382 RX DQS gating : PASS
4766 00:22:12.765650 RX DQ/DQS(RDDQC) : PASS
4767 00:22:12.769126 TX DQ/DQS : PASS
4768 00:22:12.769224 RX DATLAT : PASS
4769 00:22:12.772120 RX DQ/DQS(Engine): PASS
4770 00:22:12.775422 TX OE : NO K
4771 00:22:12.775506 All Pass.
4772 00:22:12.775571
4773 00:22:12.775631 CH 0, Rank 1
4774 00:22:12.778965 SW Impedance : PASS
4775 00:22:12.781944 DUTY Scan : NO K
4776 00:22:12.782030 ZQ Calibration : PASS
4777 00:22:12.785141 Jitter Meter : NO K
4778 00:22:12.788176 CBT Training : PASS
4779 00:22:12.788306 Write leveling : PASS
4780 00:22:12.791986 RX DQS gating : PASS
4781 00:22:12.792094 RX DQ/DQS(RDDQC) : PASS
4782 00:22:12.795289 TX DQ/DQS : PASS
4783 00:22:12.798354 RX DATLAT : PASS
4784 00:22:12.798436 RX DQ/DQS(Engine): PASS
4785 00:22:12.801680 TX OE : NO K
4786 00:22:12.801767 All Pass.
4787 00:22:12.801837
4788 00:22:12.805077 CH 1, Rank 0
4789 00:22:12.805185 SW Impedance : PASS
4790 00:22:12.808024 DUTY Scan : NO K
4791 00:22:12.811317 ZQ Calibration : PASS
4792 00:22:12.811405 Jitter Meter : NO K
4793 00:22:12.814917 CBT Training : PASS
4794 00:22:12.817799 Write leveling : PASS
4795 00:22:12.817884 RX DQS gating : PASS
4796 00:22:12.821156 RX DQ/DQS(RDDQC) : PASS
4797 00:22:12.824546 TX DQ/DQS : PASS
4798 00:22:12.824663 RX DATLAT : PASS
4799 00:22:12.828017 RX DQ/DQS(Engine): PASS
4800 00:22:12.831504 TX OE : NO K
4801 00:22:12.831593 All Pass.
4802 00:22:12.831657
4803 00:22:12.831717 CH 1, Rank 1
4804 00:22:12.834734 SW Impedance : PASS
4805 00:22:12.838017 DUTY Scan : NO K
4806 00:22:12.838104 ZQ Calibration : PASS
4807 00:22:12.841211 Jitter Meter : NO K
4808 00:22:12.844644 CBT Training : PASS
4809 00:22:12.844732 Write leveling : PASS
4810 00:22:12.848401 RX DQS gating : PASS
4811 00:22:12.851163 RX DQ/DQS(RDDQC) : PASS
4812 00:22:12.851248 TX DQ/DQS : PASS
4813 00:22:12.854647 RX DATLAT : PASS
4814 00:22:12.854731 RX DQ/DQS(Engine): PASS
4815 00:22:12.858477 TX OE : NO K
4816 00:22:12.858567 All Pass.
4817 00:22:12.858633
4818 00:22:12.861216 DramC Write-DBI off
4819 00:22:12.864465 PER_BANK_REFRESH: Hybrid Mode
4820 00:22:12.864551 TX_TRACKING: ON
4821 00:22:12.874353 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4822 00:22:12.877695 [FAST_K] Save calibration result to emmc
4823 00:22:12.880835 dramc_set_vcore_voltage set vcore to 662500
4824 00:22:12.884144 Read voltage for 933, 3
4825 00:22:12.884266 Vio18 = 0
4826 00:22:12.887732 Vcore = 662500
4827 00:22:12.887820 Vdram = 0
4828 00:22:12.887885 Vddq = 0
4829 00:22:12.887944 Vmddr = 0
4830 00:22:12.894457 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4831 00:22:12.900496 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4832 00:22:12.900613 MEM_TYPE=3, freq_sel=17
4833 00:22:12.903915 sv_algorithm_assistance_LP4_1600
4834 00:22:12.907127 ============ PULL DRAM RESETB DOWN ============
4835 00:22:12.913497 ========== PULL DRAM RESETB DOWN end =========
4836 00:22:12.916859 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4837 00:22:12.920219 ===================================
4838 00:22:12.923565 LPDDR4 DRAM CONFIGURATION
4839 00:22:12.926836 ===================================
4840 00:22:12.926930 EX_ROW_EN[0] = 0x0
4841 00:22:12.930286 EX_ROW_EN[1] = 0x0
4842 00:22:12.933478 LP4Y_EN = 0x0
4843 00:22:12.933572 WORK_FSP = 0x0
4844 00:22:12.937059 WL = 0x3
4845 00:22:12.937143 RL = 0x3
4846 00:22:12.940405 BL = 0x2
4847 00:22:12.940491 RPST = 0x0
4848 00:22:12.943166 RD_PRE = 0x0
4849 00:22:12.943249 WR_PRE = 0x1
4850 00:22:12.946527 WR_PST = 0x0
4851 00:22:12.946613 DBI_WR = 0x0
4852 00:22:12.949597 DBI_RD = 0x0
4853 00:22:12.949683 OTF = 0x1
4854 00:22:12.953210 ===================================
4855 00:22:12.956470 ===================================
4856 00:22:12.959953 ANA top config
4857 00:22:12.963074 ===================================
4858 00:22:12.966051 DLL_ASYNC_EN = 0
4859 00:22:12.966138 ALL_SLAVE_EN = 1
4860 00:22:12.969426 NEW_RANK_MODE = 1
4861 00:22:12.973034 DLL_IDLE_MODE = 1
4862 00:22:12.976184 LP45_APHY_COMB_EN = 1
4863 00:22:12.976272 TX_ODT_DIS = 1
4864 00:22:12.979675 NEW_8X_MODE = 1
4865 00:22:12.983218 ===================================
4866 00:22:12.986019 ===================================
4867 00:22:12.989301 data_rate = 1866
4868 00:22:12.992625 CKR = 1
4869 00:22:12.995763 DQ_P2S_RATIO = 8
4870 00:22:12.998884 ===================================
4871 00:22:13.002375 CA_P2S_RATIO = 8
4872 00:22:13.005747 DQ_CA_OPEN = 0
4873 00:22:13.005842 DQ_SEMI_OPEN = 0
4874 00:22:13.008932 CA_SEMI_OPEN = 0
4875 00:22:13.012491 CA_FULL_RATE = 0
4876 00:22:13.015974 DQ_CKDIV4_EN = 1
4877 00:22:13.019371 CA_CKDIV4_EN = 1
4878 00:22:13.022084 CA_PREDIV_EN = 0
4879 00:22:13.022171 PH8_DLY = 0
4880 00:22:13.025566 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4881 00:22:13.028758 DQ_AAMCK_DIV = 4
4882 00:22:13.031984 CA_AAMCK_DIV = 4
4883 00:22:13.035737 CA_ADMCK_DIV = 4
4884 00:22:13.039087 DQ_TRACK_CA_EN = 0
4885 00:22:13.039177 CA_PICK = 933
4886 00:22:13.041842 CA_MCKIO = 933
4887 00:22:13.045114 MCKIO_SEMI = 0
4888 00:22:13.049081 PLL_FREQ = 3732
4889 00:22:13.051800 DQ_UI_PI_RATIO = 32
4890 00:22:13.055092 CA_UI_PI_RATIO = 0
4891 00:22:13.058552 ===================================
4892 00:22:13.061943 ===================================
4893 00:22:13.064938 memory_type:LPDDR4
4894 00:22:13.065025 GP_NUM : 10
4895 00:22:13.068240 SRAM_EN : 1
4896 00:22:13.068323 MD32_EN : 0
4897 00:22:13.071660 ===================================
4898 00:22:13.075189 [ANA_INIT] >>>>>>>>>>>>>>
4899 00:22:13.078112 <<<<<< [CONFIGURE PHASE]: ANA_TX
4900 00:22:13.081443 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4901 00:22:13.084786 ===================================
4902 00:22:13.087967 data_rate = 1866,PCW = 0X8f00
4903 00:22:13.091337 ===================================
4904 00:22:13.094896 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4905 00:22:13.101296 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4906 00:22:13.104682 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4907 00:22:13.111328 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4908 00:22:13.114273 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4909 00:22:13.117963 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4910 00:22:13.118084 [ANA_INIT] flow start
4911 00:22:13.120826 [ANA_INIT] PLL >>>>>>>>
4912 00:22:13.124276 [ANA_INIT] PLL <<<<<<<<
4913 00:22:13.124395 [ANA_INIT] MIDPI >>>>>>>>
4914 00:22:13.127588 [ANA_INIT] MIDPI <<<<<<<<
4915 00:22:13.131017 [ANA_INIT] DLL >>>>>>>>
4916 00:22:13.131133 [ANA_INIT] flow end
4917 00:22:13.137501 ============ LP4 DIFF to SE enter ============
4918 00:22:13.140906 ============ LP4 DIFF to SE exit ============
4919 00:22:13.144018 [ANA_INIT] <<<<<<<<<<<<<
4920 00:22:13.147524 [Flow] Enable top DCM control >>>>>
4921 00:22:13.150914 [Flow] Enable top DCM control <<<<<
4922 00:22:13.154283 Enable DLL master slave shuffle
4923 00:22:13.157227 ==============================================================
4924 00:22:13.160729 Gating Mode config
4925 00:22:13.163839 ==============================================================
4926 00:22:13.167087 Config description:
4927 00:22:13.176859 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4928 00:22:13.183714 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4929 00:22:13.187166 SELPH_MODE 0: By rank 1: By Phase
4930 00:22:13.193461 ==============================================================
4931 00:22:13.196896 GAT_TRACK_EN = 1
4932 00:22:13.200454 RX_GATING_MODE = 2
4933 00:22:13.203149 RX_GATING_TRACK_MODE = 2
4934 00:22:13.206443 SELPH_MODE = 1
4935 00:22:13.209829 PICG_EARLY_EN = 1
4936 00:22:13.212908 VALID_LAT_VALUE = 1
4937 00:22:13.216878 ==============================================================
4938 00:22:13.219830 Enter into Gating configuration >>>>
4939 00:22:13.223399 Exit from Gating configuration <<<<
4940 00:22:13.226393 Enter into DVFS_PRE_config >>>>>
4941 00:22:13.239489 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4942 00:22:13.239624 Exit from DVFS_PRE_config <<<<<
4943 00:22:13.243038 Enter into PICG configuration >>>>
4944 00:22:13.246251 Exit from PICG configuration <<<<
4945 00:22:13.249055 [RX_INPUT] configuration >>>>>
4946 00:22:13.252571 [RX_INPUT] configuration <<<<<
4947 00:22:13.259353 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4948 00:22:13.262562 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4949 00:22:13.269158 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4950 00:22:13.275804 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4951 00:22:13.281940 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4952 00:22:13.289170 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4953 00:22:13.291798 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4954 00:22:13.295580 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4955 00:22:13.301701 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4956 00:22:13.305184 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4957 00:22:13.308440 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4958 00:22:13.312108 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4959 00:22:13.315574 ===================================
4960 00:22:13.318363 LPDDR4 DRAM CONFIGURATION
4961 00:22:13.321748 ===================================
4962 00:22:13.324970 EX_ROW_EN[0] = 0x0
4963 00:22:13.325080 EX_ROW_EN[1] = 0x0
4964 00:22:13.328302 LP4Y_EN = 0x0
4965 00:22:13.328388 WORK_FSP = 0x0
4966 00:22:13.331909 WL = 0x3
4967 00:22:13.332017 RL = 0x3
4968 00:22:13.335101 BL = 0x2
4969 00:22:13.335185 RPST = 0x0
4970 00:22:13.338607 RD_PRE = 0x0
4971 00:22:13.341270 WR_PRE = 0x1
4972 00:22:13.341370 WR_PST = 0x0
4973 00:22:13.344828 DBI_WR = 0x0
4974 00:22:13.344912 DBI_RD = 0x0
4975 00:22:13.348254 OTF = 0x1
4976 00:22:13.351442 ===================================
4977 00:22:13.354851 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4978 00:22:13.358198 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4979 00:22:13.361579 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4980 00:22:13.364837 ===================================
4981 00:22:13.367882 LPDDR4 DRAM CONFIGURATION
4982 00:22:13.371254 ===================================
4983 00:22:13.374305 EX_ROW_EN[0] = 0x10
4984 00:22:13.374387 EX_ROW_EN[1] = 0x0
4985 00:22:13.377681 LP4Y_EN = 0x0
4986 00:22:13.377760 WORK_FSP = 0x0
4987 00:22:13.381105 WL = 0x3
4988 00:22:13.384045 RL = 0x3
4989 00:22:13.384129 BL = 0x2
4990 00:22:13.387798 RPST = 0x0
4991 00:22:13.387906 RD_PRE = 0x0
4992 00:22:13.390913 WR_PRE = 0x1
4993 00:22:13.391022 WR_PST = 0x0
4994 00:22:13.394271 DBI_WR = 0x0
4995 00:22:13.394351 DBI_RD = 0x0
4996 00:22:13.397361 OTF = 0x1
4997 00:22:13.401005 ===================================
4998 00:22:13.407450 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4999 00:22:13.410318 nWR fixed to 30
5000 00:22:13.410413 [ModeRegInit_LP4] CH0 RK0
5001 00:22:13.413877 [ModeRegInit_LP4] CH0 RK1
5002 00:22:13.417493 [ModeRegInit_LP4] CH1 RK0
5003 00:22:13.420434 [ModeRegInit_LP4] CH1 RK1
5004 00:22:13.420551 match AC timing 9
5005 00:22:13.423482 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5006 00:22:13.430432 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5007 00:22:13.433197 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5008 00:22:13.439773 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5009 00:22:13.443076 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5010 00:22:13.443200 ==
5011 00:22:13.446415 Dram Type= 6, Freq= 0, CH_0, rank 0
5012 00:22:13.450000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5013 00:22:13.450114 ==
5014 00:22:13.456813 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5015 00:22:13.463065 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5016 00:22:13.467050 [CA 0] Center 38 (7~69) winsize 63
5017 00:22:13.469847 [CA 1] Center 37 (7~68) winsize 62
5018 00:22:13.473104 [CA 2] Center 34 (4~65) winsize 62
5019 00:22:13.476449 [CA 3] Center 34 (4~65) winsize 62
5020 00:22:13.479840 [CA 4] Center 33 (2~64) winsize 63
5021 00:22:13.482769 [CA 5] Center 32 (2~63) winsize 62
5022 00:22:13.482847
5023 00:22:13.486082 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5024 00:22:13.486163
5025 00:22:13.489782 [CATrainingPosCal] consider 1 rank data
5026 00:22:13.493007 u2DelayCellTimex100 = 270/100 ps
5027 00:22:13.495961 CA0 delay=38 (7~69),Diff = 6 PI (37 cell)
5028 00:22:13.499417 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5029 00:22:13.503009 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5030 00:22:13.506016 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5031 00:22:13.509322 CA4 delay=33 (2~64),Diff = 1 PI (6 cell)
5032 00:22:13.516359 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5033 00:22:13.516498
5034 00:22:13.519403 CA PerBit enable=1, Macro0, CA PI delay=32
5035 00:22:13.519484
5036 00:22:13.522593 [CBTSetCACLKResult] CA Dly = 32
5037 00:22:13.522694 CS Dly: 6 (0~37)
5038 00:22:13.522785 ==
5039 00:22:13.525565 Dram Type= 6, Freq= 0, CH_0, rank 1
5040 00:22:13.529206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5041 00:22:13.532230 ==
5042 00:22:13.535836 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5043 00:22:13.542304 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5044 00:22:13.545429 [CA 0] Center 38 (8~68) winsize 61
5045 00:22:13.548717 [CA 1] Center 37 (7~68) winsize 62
5046 00:22:13.552060 [CA 2] Center 35 (5~65) winsize 61
5047 00:22:13.555538 [CA 3] Center 34 (4~65) winsize 62
5048 00:22:13.558778 [CA 4] Center 33 (3~64) winsize 62
5049 00:22:13.562052 [CA 5] Center 32 (2~63) winsize 62
5050 00:22:13.562160
5051 00:22:13.565396 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5052 00:22:13.565501
5053 00:22:13.568766 [CATrainingPosCal] consider 2 rank data
5054 00:22:13.572289 u2DelayCellTimex100 = 270/100 ps
5055 00:22:13.575060 CA0 delay=38 (8~68),Diff = 6 PI (37 cell)
5056 00:22:13.578320 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5057 00:22:13.584793 CA2 delay=35 (5~65),Diff = 3 PI (18 cell)
5058 00:22:13.588031 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5059 00:22:13.591248 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5060 00:22:13.595161 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5061 00:22:13.595283
5062 00:22:13.598379 CA PerBit enable=1, Macro0, CA PI delay=32
5063 00:22:13.598498
5064 00:22:13.601461 [CBTSetCACLKResult] CA Dly = 32
5065 00:22:13.601566 CS Dly: 7 (0~39)
5066 00:22:13.604515
5067 00:22:13.608307 ----->DramcWriteLeveling(PI) begin...
5068 00:22:13.608425 ==
5069 00:22:13.611729 Dram Type= 6, Freq= 0, CH_0, rank 0
5070 00:22:13.614582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5071 00:22:13.614695 ==
5072 00:22:13.617662 Write leveling (Byte 0): 31 => 31
5073 00:22:13.620778 Write leveling (Byte 1): 29 => 29
5074 00:22:13.624396 DramcWriteLeveling(PI) end<-----
5075 00:22:13.624511
5076 00:22:13.624608 ==
5077 00:22:13.627969 Dram Type= 6, Freq= 0, CH_0, rank 0
5078 00:22:13.630822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5079 00:22:13.630939 ==
5080 00:22:13.634514 [Gating] SW mode calibration
5081 00:22:13.640571 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5082 00:22:13.647284 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5083 00:22:13.650575 0 14 0 | B1->B0 | 2423 3434 | 1 0 | (0 0) (0 0)
5084 00:22:13.653834 0 14 4 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
5085 00:22:13.660626 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5086 00:22:13.664217 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5087 00:22:13.667515 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5088 00:22:13.673803 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5089 00:22:13.678369 0 14 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
5090 00:22:13.680608 0 14 28 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 0)
5091 00:22:13.687451 0 15 0 | B1->B0 | 2f2f 2424 | 0 0 | (0 0) (0 0)
5092 00:22:13.690231 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5093 00:22:13.693656 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5094 00:22:13.700483 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5095 00:22:13.704071 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5096 00:22:13.706758 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5097 00:22:13.713253 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5098 00:22:13.716615 0 15 28 | B1->B0 | 2323 3737 | 0 1 | (0 0) (1 1)
5099 00:22:13.720417 1 0 0 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
5100 00:22:13.726517 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5101 00:22:13.729860 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5102 00:22:13.733486 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5103 00:22:13.739555 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5104 00:22:13.743183 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5105 00:22:13.746625 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5106 00:22:13.753072 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5107 00:22:13.756144 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5108 00:22:13.759185 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5109 00:22:13.766002 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5110 00:22:13.769251 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5111 00:22:13.772141 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5112 00:22:13.778916 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5113 00:22:13.782558 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5114 00:22:13.785346 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5115 00:22:13.791917 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5116 00:22:13.795614 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5117 00:22:13.798886 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5118 00:22:13.805755 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5119 00:22:13.808575 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5120 00:22:13.812204 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5121 00:22:13.818313 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5122 00:22:13.822011 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5123 00:22:13.825617 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5124 00:22:13.828363 Total UI for P1: 0, mck2ui 16
5125 00:22:13.831711 best dqsien dly found for B0: ( 1, 2, 26)
5126 00:22:13.838163 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5127 00:22:13.841966 Total UI for P1: 0, mck2ui 16
5128 00:22:13.844618 best dqsien dly found for B1: ( 1, 2, 30)
5129 00:22:13.848393 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5130 00:22:13.851859 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5131 00:22:13.851994
5132 00:22:13.855594 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5133 00:22:13.858233 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5134 00:22:13.861912 [Gating] SW calibration Done
5135 00:22:13.862032 ==
5136 00:22:13.864792 Dram Type= 6, Freq= 0, CH_0, rank 0
5137 00:22:13.868164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5138 00:22:13.868287 ==
5139 00:22:13.871468 RX Vref Scan: 0
5140 00:22:13.871580
5141 00:22:13.874982 RX Vref 0 -> 0, step: 1
5142 00:22:13.875107
5143 00:22:13.875205 RX Delay -80 -> 252, step: 8
5144 00:22:13.881549 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5145 00:22:13.884819 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5146 00:22:13.887933 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5147 00:22:13.891918 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5148 00:22:13.894733 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5149 00:22:13.897713 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5150 00:22:13.904268 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5151 00:22:13.907550 iDelay=208, Bit 7, Center 107 (16 ~ 199) 184
5152 00:22:13.910805 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5153 00:22:13.914044 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5154 00:22:13.917514 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5155 00:22:13.923830 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5156 00:22:13.927267 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5157 00:22:13.930660 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5158 00:22:13.934369 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5159 00:22:13.936787 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5160 00:22:13.940153 ==
5161 00:22:13.943583 Dram Type= 6, Freq= 0, CH_0, rank 0
5162 00:22:13.947261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5163 00:22:13.947388 ==
5164 00:22:13.947490 DQS Delay:
5165 00:22:13.950295 DQS0 = 0, DQS1 = 0
5166 00:22:13.950423 DQM Delay:
5167 00:22:13.953298 DQM0 = 101, DQM1 = 87
5168 00:22:13.953415 DQ Delay:
5169 00:22:13.956638 DQ0 =103, DQ1 =103, DQ2 =99, DQ3 =95
5170 00:22:13.960274 DQ4 =103, DQ5 =91, DQ6 =111, DQ7 =107
5171 00:22:13.963182 DQ8 =79, DQ9 =71, DQ10 =87, DQ11 =79
5172 00:22:13.966499 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5173 00:22:13.966618
5174 00:22:13.966715
5175 00:22:13.966806 ==
5176 00:22:13.970003 Dram Type= 6, Freq= 0, CH_0, rank 0
5177 00:22:13.973202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5178 00:22:13.976593 ==
5179 00:22:13.976709
5180 00:22:13.976804
5181 00:22:13.976894 TX Vref Scan disable
5182 00:22:13.979789 == TX Byte 0 ==
5183 00:22:13.983296 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5184 00:22:13.986276 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5185 00:22:13.989617 == TX Byte 1 ==
5186 00:22:13.993425 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5187 00:22:13.996561 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5188 00:22:13.999665 ==
5189 00:22:14.002923 Dram Type= 6, Freq= 0, CH_0, rank 0
5190 00:22:14.006326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5191 00:22:14.006457 ==
5192 00:22:14.006556
5193 00:22:14.006649
5194 00:22:14.009559 TX Vref Scan disable
5195 00:22:14.009669 == TX Byte 0 ==
5196 00:22:14.015986 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5197 00:22:14.019497 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5198 00:22:14.019638 == TX Byte 1 ==
5199 00:22:14.025926 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5200 00:22:14.029089 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5201 00:22:14.029222
5202 00:22:14.029359 [DATLAT]
5203 00:22:14.032520 Freq=933, CH0 RK0
5204 00:22:14.032630
5205 00:22:14.032723 DATLAT Default: 0xd
5206 00:22:14.035917 0, 0xFFFF, sum = 0
5207 00:22:14.039492 1, 0xFFFF, sum = 0
5208 00:22:14.039609 2, 0xFFFF, sum = 0
5209 00:22:14.042220 3, 0xFFFF, sum = 0
5210 00:22:14.042329 4, 0xFFFF, sum = 0
5211 00:22:14.045432 5, 0xFFFF, sum = 0
5212 00:22:14.045543 6, 0xFFFF, sum = 0
5213 00:22:14.048641 7, 0xFFFF, sum = 0
5214 00:22:14.048753 8, 0xFFFF, sum = 0
5215 00:22:14.052138 9, 0xFFFF, sum = 0
5216 00:22:14.052249 10, 0x0, sum = 1
5217 00:22:14.055254 11, 0x0, sum = 2
5218 00:22:14.055373 12, 0x0, sum = 3
5219 00:22:14.059064 13, 0x0, sum = 4
5220 00:22:14.059181 best_step = 11
5221 00:22:14.059280
5222 00:22:14.059375 ==
5223 00:22:14.062224 Dram Type= 6, Freq= 0, CH_0, rank 0
5224 00:22:14.065211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5225 00:22:14.065367 ==
5226 00:22:14.068729 RX Vref Scan: 1
5227 00:22:14.068835
5228 00:22:14.071738 RX Vref 0 -> 0, step: 1
5229 00:22:14.071854
5230 00:22:14.071951 RX Delay -69 -> 252, step: 4
5231 00:22:14.074932
5232 00:22:14.075047 Set Vref, RX VrefLevel [Byte0]: 55
5233 00:22:14.078685 [Byte1]: 48
5234 00:22:14.083294
5235 00:22:14.083433 Final RX Vref Byte 0 = 55 to rank0
5236 00:22:14.086854 Final RX Vref Byte 1 = 48 to rank0
5237 00:22:14.090194 Final RX Vref Byte 0 = 55 to rank1
5238 00:22:14.093726 Final RX Vref Byte 1 = 48 to rank1==
5239 00:22:14.096786 Dram Type= 6, Freq= 0, CH_0, rank 0
5240 00:22:14.102982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5241 00:22:14.103142 ==
5242 00:22:14.103247 DQS Delay:
5243 00:22:14.106778 DQS0 = 0, DQS1 = 0
5244 00:22:14.106887 DQM Delay:
5245 00:22:14.106979 DQM0 = 102, DQM1 = 90
5246 00:22:14.109821 DQ Delay:
5247 00:22:14.113286 DQ0 =104, DQ1 =102, DQ2 =98, DQ3 =100
5248 00:22:14.116553 DQ4 =104, DQ5 =96, DQ6 =112, DQ7 =106
5249 00:22:14.119759 DQ8 =78, DQ9 =76, DQ10 =94, DQ11 =86
5250 00:22:14.122911 DQ12 =98, DQ13 =94, DQ14 =98, DQ15 =98
5251 00:22:14.123027
5252 00:22:14.123121
5253 00:22:14.129758 [DQSOSCAuto] RK0, (LSB)MR18= 0x201a, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 411 ps
5254 00:22:14.133398 CH0 RK0: MR19=505, MR18=201A
5255 00:22:14.139534 CH0_RK0: MR19=0x505, MR18=0x201A, DQSOSC=411, MR23=63, INC=64, DEC=42
5256 00:22:14.139686
5257 00:22:14.142926 ----->DramcWriteLeveling(PI) begin...
5258 00:22:14.143047 ==
5259 00:22:14.145994 Dram Type= 6, Freq= 0, CH_0, rank 1
5260 00:22:14.149063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5261 00:22:14.152986 ==
5262 00:22:14.153099 Write leveling (Byte 0): 31 => 31
5263 00:22:14.156655 Write leveling (Byte 1): 25 => 25
5264 00:22:14.159475 DramcWriteLeveling(PI) end<-----
5265 00:22:14.159590
5266 00:22:14.159689 ==
5267 00:22:14.162876 Dram Type= 6, Freq= 0, CH_0, rank 1
5268 00:22:14.169095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5269 00:22:14.169220 ==
5270 00:22:14.172572 [Gating] SW mode calibration
5271 00:22:14.179175 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5272 00:22:14.182767 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5273 00:22:14.189223 0 14 0 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
5274 00:22:14.192506 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5275 00:22:14.195552 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5276 00:22:14.202239 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5277 00:22:14.205482 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5278 00:22:14.208653 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5279 00:22:14.215693 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5280 00:22:14.219002 0 14 28 | B1->B0 | 3434 2a2a | 1 0 | (1 0) (0 0)
5281 00:22:14.221807 0 15 0 | B1->B0 | 2a2a 2424 | 0 0 | (0 0) (1 1)
5282 00:22:14.228695 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5283 00:22:14.231705 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5284 00:22:14.235120 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5285 00:22:14.241723 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5286 00:22:14.245229 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5287 00:22:14.248305 0 15 24 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
5288 00:22:14.255170 0 15 28 | B1->B0 | 2e2e 3a3a | 1 0 | (0 0) (0 0)
5289 00:22:14.258845 1 0 0 | B1->B0 | 4141 4646 | 1 0 | (0 0) (0 0)
5290 00:22:14.261914 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5291 00:22:14.268543 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5292 00:22:14.271564 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5293 00:22:14.274817 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5294 00:22:14.281562 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5295 00:22:14.284411 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5296 00:22:14.288052 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5297 00:22:14.294278 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5298 00:22:14.297524 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5299 00:22:14.301239 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5300 00:22:14.307834 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5301 00:22:14.311132 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5302 00:22:14.314652 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5303 00:22:14.320707 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5304 00:22:14.323891 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5305 00:22:14.327340 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5306 00:22:14.334147 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5307 00:22:14.337240 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5308 00:22:14.340590 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5309 00:22:14.347084 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5310 00:22:14.350494 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5311 00:22:14.353919 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5312 00:22:14.360123 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5313 00:22:14.360267 Total UI for P1: 0, mck2ui 16
5314 00:22:14.366948 best dqsien dly found for B0: ( 1, 2, 26)
5315 00:22:14.370099 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5316 00:22:14.373393 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5317 00:22:14.376773 Total UI for P1: 0, mck2ui 16
5318 00:22:14.379854 best dqsien dly found for B1: ( 1, 3, 0)
5319 00:22:14.383368 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5320 00:22:14.386486 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5321 00:22:14.386615
5322 00:22:14.393020 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5323 00:22:14.396576 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5324 00:22:14.396699 [Gating] SW calibration Done
5325 00:22:14.400276 ==
5326 00:22:14.403360 Dram Type= 6, Freq= 0, CH_0, rank 1
5327 00:22:14.406205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5328 00:22:14.406321 ==
5329 00:22:14.406415 RX Vref Scan: 0
5330 00:22:14.406515
5331 00:22:14.409522 RX Vref 0 -> 0, step: 1
5332 00:22:14.409604
5333 00:22:14.412850 RX Delay -80 -> 252, step: 8
5334 00:22:14.415970 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5335 00:22:14.420071 iDelay=200, Bit 1, Center 103 (8 ~ 199) 192
5336 00:22:14.422921 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5337 00:22:14.429130 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5338 00:22:14.432828 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5339 00:22:14.436179 iDelay=200, Bit 5, Center 91 (0 ~ 183) 184
5340 00:22:14.439543 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5341 00:22:14.442386 iDelay=200, Bit 7, Center 107 (16 ~ 199) 184
5342 00:22:14.449386 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5343 00:22:14.452933 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5344 00:22:14.455432 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5345 00:22:14.459086 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5346 00:22:14.462343 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5347 00:22:14.465767 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5348 00:22:14.472031 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5349 00:22:14.475255 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5350 00:22:14.475355 ==
5351 00:22:14.478587 Dram Type= 6, Freq= 0, CH_0, rank 1
5352 00:22:14.482324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5353 00:22:14.482443 ==
5354 00:22:14.485705 DQS Delay:
5355 00:22:14.485790 DQS0 = 0, DQS1 = 0
5356 00:22:14.485853 DQM Delay:
5357 00:22:14.488385 DQM0 = 100, DQM1 = 89
5358 00:22:14.488466 DQ Delay:
5359 00:22:14.491743 DQ0 =99, DQ1 =103, DQ2 =95, DQ3 =95
5360 00:22:14.495420 DQ4 =103, DQ5 =91, DQ6 =107, DQ7 =107
5361 00:22:14.498657 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5362 00:22:14.501688 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5363 00:22:14.501777
5364 00:22:14.501841
5365 00:22:14.505036 ==
5366 00:22:14.505198 Dram Type= 6, Freq= 0, CH_0, rank 1
5367 00:22:14.511872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5368 00:22:14.511961 ==
5369 00:22:14.512026
5370 00:22:14.512085
5371 00:22:14.515185 TX Vref Scan disable
5372 00:22:14.515267 == TX Byte 0 ==
5373 00:22:14.518194 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5374 00:22:14.524837 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5375 00:22:14.524941 == TX Byte 1 ==
5376 00:22:14.531422 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5377 00:22:14.534499 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5378 00:22:14.534606 ==
5379 00:22:14.537960 Dram Type= 6, Freq= 0, CH_0, rank 1
5380 00:22:14.541159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5381 00:22:14.541249 ==
5382 00:22:14.541341
5383 00:22:14.541431
5384 00:22:14.544247 TX Vref Scan disable
5385 00:22:14.547715 == TX Byte 0 ==
5386 00:22:14.551245 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5387 00:22:14.554112 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5388 00:22:14.557753 == TX Byte 1 ==
5389 00:22:14.560642 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5390 00:22:14.564068 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5391 00:22:14.564165
5392 00:22:14.568002 [DATLAT]
5393 00:22:14.568083 Freq=933, CH0 RK1
5394 00:22:14.568148
5395 00:22:14.570668 DATLAT Default: 0xb
5396 00:22:14.570752 0, 0xFFFF, sum = 0
5397 00:22:14.574259 1, 0xFFFF, sum = 0
5398 00:22:14.574343 2, 0xFFFF, sum = 0
5399 00:22:14.577593 3, 0xFFFF, sum = 0
5400 00:22:14.577697 4, 0xFFFF, sum = 0
5401 00:22:14.580830 5, 0xFFFF, sum = 0
5402 00:22:14.580917 6, 0xFFFF, sum = 0
5403 00:22:14.584256 7, 0xFFFF, sum = 0
5404 00:22:14.587091 8, 0xFFFF, sum = 0
5405 00:22:14.587178 9, 0xFFFF, sum = 0
5406 00:22:14.590681 10, 0x0, sum = 1
5407 00:22:14.590768 11, 0x0, sum = 2
5408 00:22:14.590833 12, 0x0, sum = 3
5409 00:22:14.593939 13, 0x0, sum = 4
5410 00:22:14.594035 best_step = 11
5411 00:22:14.594190
5412 00:22:14.596836 ==
5413 00:22:14.596918 Dram Type= 6, Freq= 0, CH_0, rank 1
5414 00:22:14.603805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5415 00:22:14.603942 ==
5416 00:22:14.604014 RX Vref Scan: 0
5417 00:22:14.604106
5418 00:22:14.606901 RX Vref 0 -> 0, step: 1
5419 00:22:14.606979
5420 00:22:14.610890 RX Delay -61 -> 252, step: 4
5421 00:22:14.613250 iDelay=195, Bit 0, Center 100 (19 ~ 182) 164
5422 00:22:14.620704 iDelay=195, Bit 1, Center 102 (15 ~ 190) 176
5423 00:22:14.623298 iDelay=195, Bit 2, Center 96 (11 ~ 182) 172
5424 00:22:14.626507 iDelay=195, Bit 3, Center 98 (11 ~ 186) 176
5425 00:22:14.629889 iDelay=195, Bit 4, Center 102 (15 ~ 190) 176
5426 00:22:14.633464 iDelay=195, Bit 5, Center 92 (7 ~ 178) 172
5427 00:22:14.640195 iDelay=195, Bit 6, Center 110 (27 ~ 194) 168
5428 00:22:14.643176 iDelay=195, Bit 7, Center 108 (23 ~ 194) 172
5429 00:22:14.646710 iDelay=195, Bit 8, Center 80 (-5 ~ 166) 172
5430 00:22:14.650200 iDelay=195, Bit 9, Center 78 (-9 ~ 166) 176
5431 00:22:14.653181 iDelay=195, Bit 10, Center 94 (11 ~ 178) 168
5432 00:22:14.659721 iDelay=195, Bit 11, Center 84 (-1 ~ 170) 172
5433 00:22:14.663170 iDelay=195, Bit 12, Center 96 (11 ~ 182) 172
5434 00:22:14.666519 iDelay=195, Bit 13, Center 94 (11 ~ 178) 168
5435 00:22:14.669806 iDelay=195, Bit 14, Center 100 (15 ~ 186) 172
5436 00:22:14.672809 iDelay=195, Bit 15, Center 96 (11 ~ 182) 172
5437 00:22:14.672913 ==
5438 00:22:14.676580 Dram Type= 6, Freq= 0, CH_0, rank 1
5439 00:22:14.683152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5440 00:22:14.683266 ==
5441 00:22:14.683337 DQS Delay:
5442 00:22:14.686268 DQS0 = 0, DQS1 = 0
5443 00:22:14.686358 DQM Delay:
5444 00:22:14.689424 DQM0 = 101, DQM1 = 90
5445 00:22:14.689520 DQ Delay:
5446 00:22:14.692817 DQ0 =100, DQ1 =102, DQ2 =96, DQ3 =98
5447 00:22:14.696057 DQ4 =102, DQ5 =92, DQ6 =110, DQ7 =108
5448 00:22:14.699024 DQ8 =80, DQ9 =78, DQ10 =94, DQ11 =84
5449 00:22:14.702806 DQ12 =96, DQ13 =94, DQ14 =100, DQ15 =96
5450 00:22:14.702918
5451 00:22:14.703003
5452 00:22:14.712341 [DQSOSCAuto] RK1, (LSB)MR18= 0x1511, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 415 ps
5453 00:22:14.712479 CH0 RK1: MR19=505, MR18=1511
5454 00:22:14.718863 CH0_RK1: MR19=0x505, MR18=0x1511, DQSOSC=415, MR23=63, INC=62, DEC=41
5455 00:22:14.721934 [RxdqsGatingPostProcess] freq 933
5456 00:22:14.729030 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5457 00:22:14.732262 best DQS0 dly(2T, 0.5T) = (0, 10)
5458 00:22:14.735164 best DQS1 dly(2T, 0.5T) = (0, 10)
5459 00:22:14.738839 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5460 00:22:14.741809 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5461 00:22:14.741903 best DQS0 dly(2T, 0.5T) = (0, 10)
5462 00:22:14.745243 best DQS1 dly(2T, 0.5T) = (0, 11)
5463 00:22:14.748575 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5464 00:22:14.752232 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5465 00:22:14.755261 Pre-setting of DQS Precalculation
5466 00:22:14.761716 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5467 00:22:14.761843 ==
5468 00:22:14.765157 Dram Type= 6, Freq= 0, CH_1, rank 0
5469 00:22:14.768622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5470 00:22:14.768714 ==
5471 00:22:14.775052 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5472 00:22:14.781773 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5473 00:22:14.785200 [CA 0] Center 36 (6~66) winsize 61
5474 00:22:14.788069 [CA 1] Center 36 (6~67) winsize 62
5475 00:22:14.791330 [CA 2] Center 34 (4~65) winsize 62
5476 00:22:14.795030 [CA 3] Center 33 (3~64) winsize 62
5477 00:22:14.797952 [CA 4] Center 34 (4~64) winsize 61
5478 00:22:14.801326 [CA 5] Center 33 (3~64) winsize 62
5479 00:22:14.801433
5480 00:22:14.804523 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5481 00:22:14.804615
5482 00:22:14.808352 [CATrainingPosCal] consider 1 rank data
5483 00:22:14.811185 u2DelayCellTimex100 = 270/100 ps
5484 00:22:14.814736 CA0 delay=36 (6~66),Diff = 3 PI (18 cell)
5485 00:22:14.818181 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5486 00:22:14.821112 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5487 00:22:14.824636 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5488 00:22:14.828020 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5489 00:22:14.831207 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5490 00:22:14.834328
5491 00:22:14.837495 CA PerBit enable=1, Macro0, CA PI delay=33
5492 00:22:14.837588
5493 00:22:14.840768 [CBTSetCACLKResult] CA Dly = 33
5494 00:22:14.840850 CS Dly: 5 (0~36)
5495 00:22:14.840913 ==
5496 00:22:14.844565 Dram Type= 6, Freq= 0, CH_1, rank 1
5497 00:22:14.847216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5498 00:22:14.847313 ==
5499 00:22:14.853823 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5500 00:22:14.861012 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5501 00:22:14.863892 [CA 0] Center 36 (6~67) winsize 62
5502 00:22:14.867228 [CA 1] Center 36 (6~67) winsize 62
5503 00:22:14.870889 [CA 2] Center 34 (4~65) winsize 62
5504 00:22:14.873821 [CA 3] Center 33 (3~64) winsize 62
5505 00:22:14.877595 [CA 4] Center 33 (3~64) winsize 62
5506 00:22:14.880359 [CA 5] Center 33 (3~64) winsize 62
5507 00:22:14.880443
5508 00:22:14.883674 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5509 00:22:14.883768
5510 00:22:14.887236 [CATrainingPosCal] consider 2 rank data
5511 00:22:14.890604 u2DelayCellTimex100 = 270/100 ps
5512 00:22:14.893355 CA0 delay=36 (6~66),Diff = 3 PI (18 cell)
5513 00:22:14.896677 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5514 00:22:14.900147 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5515 00:22:14.907070 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5516 00:22:14.910018 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5517 00:22:14.913552 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5518 00:22:14.913649
5519 00:22:14.916673 CA PerBit enable=1, Macro0, CA PI delay=33
5520 00:22:14.916764
5521 00:22:14.919784 [CBTSetCACLKResult] CA Dly = 33
5522 00:22:14.919871 CS Dly: 5 (0~37)
5523 00:22:14.919935
5524 00:22:14.923393 ----->DramcWriteLeveling(PI) begin...
5525 00:22:14.923468 ==
5526 00:22:14.926611 Dram Type= 6, Freq= 0, CH_1, rank 0
5527 00:22:14.933143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5528 00:22:14.933245 ==
5529 00:22:14.936025 Write leveling (Byte 0): 27 => 27
5530 00:22:14.939967 Write leveling (Byte 1): 30 => 30
5531 00:22:14.943273 DramcWriteLeveling(PI) end<-----
5532 00:22:14.943352
5533 00:22:14.943421 ==
5534 00:22:14.946530 Dram Type= 6, Freq= 0, CH_1, rank 0
5535 00:22:14.949772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5536 00:22:14.949849 ==
5537 00:22:14.952757 [Gating] SW mode calibration
5538 00:22:14.959630 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5539 00:22:14.965759 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5540 00:22:14.969224 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5541 00:22:14.972839 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5542 00:22:14.979061 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5543 00:22:14.982856 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5544 00:22:14.986076 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5545 00:22:14.992743 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5546 00:22:14.995621 0 14 24 | B1->B0 | 3131 3434 | 1 1 | (1 0) (1 1)
5547 00:22:14.999322 0 14 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5548 00:22:15.005801 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
5549 00:22:15.009109 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5550 00:22:15.012311 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5551 00:22:15.019223 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5552 00:22:15.021762 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5553 00:22:15.025429 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5554 00:22:15.032057 0 15 24 | B1->B0 | 2828 2f2f | 0 1 | (0 0) (0 0)
5555 00:22:15.035594 0 15 28 | B1->B0 | 3b3b 4242 | 1 0 | (0 0) (0 0)
5556 00:22:15.038452 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5557 00:22:15.045016 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5558 00:22:15.048179 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5559 00:22:15.051498 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5560 00:22:15.058356 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5561 00:22:15.061937 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5562 00:22:15.064965 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5563 00:22:15.071336 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5564 00:22:15.074583 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5565 00:22:15.078062 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5566 00:22:15.084392 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5567 00:22:15.087816 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5568 00:22:15.091393 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5569 00:22:15.097751 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5570 00:22:15.100962 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5571 00:22:15.104560 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5572 00:22:15.110783 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5573 00:22:15.114330 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5574 00:22:15.117292 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5575 00:22:15.124382 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5576 00:22:15.127507 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5577 00:22:15.130657 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5578 00:22:15.137263 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5579 00:22:15.140503 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5580 00:22:15.143965 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5581 00:22:15.147239 Total UI for P1: 0, mck2ui 16
5582 00:22:15.150364 best dqsien dly found for B0: ( 1, 2, 28)
5583 00:22:15.153607 Total UI for P1: 0, mck2ui 16
5584 00:22:15.156896 best dqsien dly found for B1: ( 1, 2, 28)
5585 00:22:15.160693 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5586 00:22:15.163505 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5587 00:22:15.163612
5588 00:22:15.170213 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5589 00:22:15.173682 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5590 00:22:15.173792 [Gating] SW calibration Done
5591 00:22:15.177079 ==
5592 00:22:15.180542 Dram Type= 6, Freq= 0, CH_1, rank 0
5593 00:22:15.183194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5594 00:22:15.183305 ==
5595 00:22:15.183425 RX Vref Scan: 0
5596 00:22:15.183542
5597 00:22:15.186878 RX Vref 0 -> 0, step: 1
5598 00:22:15.186982
5599 00:22:15.189928 RX Delay -80 -> 252, step: 8
5600 00:22:15.193232 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5601 00:22:15.196707 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5602 00:22:15.200182 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5603 00:22:15.203673 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5604 00:22:15.209814 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5605 00:22:15.213117 iDelay=208, Bit 5, Center 107 (16 ~ 199) 184
5606 00:22:15.216612 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5607 00:22:15.219686 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5608 00:22:15.223141 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5609 00:22:15.229787 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5610 00:22:15.233150 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5611 00:22:15.236400 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5612 00:22:15.239530 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5613 00:22:15.243219 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5614 00:22:15.249341 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5615 00:22:15.252807 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5616 00:22:15.252917 ==
5617 00:22:15.256259 Dram Type= 6, Freq= 0, CH_1, rank 0
5618 00:22:15.259365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5619 00:22:15.259471 ==
5620 00:22:15.259564 DQS Delay:
5621 00:22:15.262859 DQS0 = 0, DQS1 = 0
5622 00:22:15.262965 DQM Delay:
5623 00:22:15.266064 DQM0 = 99, DQM1 = 96
5624 00:22:15.266170 DQ Delay:
5625 00:22:15.269159 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =99
5626 00:22:15.272679 DQ4 =95, DQ5 =107, DQ6 =111, DQ7 =95
5627 00:22:15.276317 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =91
5628 00:22:15.279051 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5629 00:22:15.279156
5630 00:22:15.279244
5631 00:22:15.282543 ==
5632 00:22:15.282646 Dram Type= 6, Freq= 0, CH_1, rank 0
5633 00:22:15.289137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5634 00:22:15.289248 ==
5635 00:22:15.289383
5636 00:22:15.289469
5637 00:22:15.292623 TX Vref Scan disable
5638 00:22:15.292725 == TX Byte 0 ==
5639 00:22:15.295816 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5640 00:22:15.302317 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5641 00:22:15.302445 == TX Byte 1 ==
5642 00:22:15.305423 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5643 00:22:15.312338 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5644 00:22:15.312452 ==
5645 00:22:15.315492 Dram Type= 6, Freq= 0, CH_1, rank 0
5646 00:22:15.318606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5647 00:22:15.318714 ==
5648 00:22:15.318845
5649 00:22:15.318932
5650 00:22:15.322209 TX Vref Scan disable
5651 00:22:15.325160 == TX Byte 0 ==
5652 00:22:15.328338 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5653 00:22:15.331697 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5654 00:22:15.335191 == TX Byte 1 ==
5655 00:22:15.338646 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5656 00:22:15.342005 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5657 00:22:15.342112
5658 00:22:15.345232 [DATLAT]
5659 00:22:15.345374 Freq=933, CH1 RK0
5660 00:22:15.345466
5661 00:22:15.348158 DATLAT Default: 0xd
5662 00:22:15.348259 0, 0xFFFF, sum = 0
5663 00:22:15.351372 1, 0xFFFF, sum = 0
5664 00:22:15.351477 2, 0xFFFF, sum = 0
5665 00:22:15.355222 3, 0xFFFF, sum = 0
5666 00:22:15.355328 4, 0xFFFF, sum = 0
5667 00:22:15.358091 5, 0xFFFF, sum = 0
5668 00:22:15.358193 6, 0xFFFF, sum = 0
5669 00:22:15.361593 7, 0xFFFF, sum = 0
5670 00:22:15.361713 8, 0xFFFF, sum = 0
5671 00:22:15.364923 9, 0xFFFF, sum = 0
5672 00:22:15.365026 10, 0x0, sum = 1
5673 00:22:15.368028 11, 0x0, sum = 2
5674 00:22:15.368130 12, 0x0, sum = 3
5675 00:22:15.371255 13, 0x0, sum = 4
5676 00:22:15.371360 best_step = 11
5677 00:22:15.371450
5678 00:22:15.371536 ==
5679 00:22:15.375273 Dram Type= 6, Freq= 0, CH_1, rank 0
5680 00:22:15.381466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5681 00:22:15.381584 ==
5682 00:22:15.381679 RX Vref Scan: 1
5683 00:22:15.381769
5684 00:22:15.384291 RX Vref 0 -> 0, step: 1
5685 00:22:15.384394
5686 00:22:15.387937 RX Delay -53 -> 252, step: 4
5687 00:22:15.388060
5688 00:22:15.391100 Set Vref, RX VrefLevel [Byte0]: 50
5689 00:22:15.394104 [Byte1]: 50
5690 00:22:15.394210
5691 00:22:15.397665 Final RX Vref Byte 0 = 50 to rank0
5692 00:22:15.401431 Final RX Vref Byte 1 = 50 to rank0
5693 00:22:15.404371 Final RX Vref Byte 0 = 50 to rank1
5694 00:22:15.407658 Final RX Vref Byte 1 = 50 to rank1==
5695 00:22:15.410923 Dram Type= 6, Freq= 0, CH_1, rank 0
5696 00:22:15.414116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5697 00:22:15.414225 ==
5698 00:22:15.417205 DQS Delay:
5699 00:22:15.417348 DQS0 = 0, DQS1 = 0
5700 00:22:15.420730 DQM Delay:
5701 00:22:15.420836 DQM0 = 99, DQM1 = 95
5702 00:22:15.420927 DQ Delay:
5703 00:22:15.424320 DQ0 =104, DQ1 =94, DQ2 =88, DQ3 =100
5704 00:22:15.427072 DQ4 =94, DQ5 =108, DQ6 =110, DQ7 =94
5705 00:22:15.430599 DQ8 =80, DQ9 =86, DQ10 =94, DQ11 =88
5706 00:22:15.436908 DQ12 =104, DQ13 =104, DQ14 =100, DQ15 =104
5707 00:22:15.437030
5708 00:22:15.437125
5709 00:22:15.443556 [DQSOSCAuto] RK0, (LSB)MR18= 0x919, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 419 ps
5710 00:22:15.446991 CH1 RK0: MR19=505, MR18=919
5711 00:22:15.453539 CH1_RK0: MR19=0x505, MR18=0x919, DQSOSC=413, MR23=63, INC=63, DEC=42
5712 00:22:15.453662
5713 00:22:15.457057 ----->DramcWriteLeveling(PI) begin...
5714 00:22:15.457165 ==
5715 00:22:15.460131 Dram Type= 6, Freq= 0, CH_1, rank 1
5716 00:22:15.463817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5717 00:22:15.463926 ==
5718 00:22:15.466587 Write leveling (Byte 0): 27 => 27
5719 00:22:15.470186 Write leveling (Byte 1): 27 => 27
5720 00:22:15.473271 DramcWriteLeveling(PI) end<-----
5721 00:22:15.473390
5722 00:22:15.473483 ==
5723 00:22:15.476395 Dram Type= 6, Freq= 0, CH_1, rank 1
5724 00:22:15.480155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5725 00:22:15.480259 ==
5726 00:22:15.482999 [Gating] SW mode calibration
5727 00:22:15.489587 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5728 00:22:15.496556 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5729 00:22:15.499439 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5730 00:22:15.506073 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5731 00:22:15.509412 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5732 00:22:15.512933 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5733 00:22:15.519855 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5734 00:22:15.523433 0 14 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5735 00:22:15.526008 0 14 24 | B1->B0 | 3434 3030 | 1 0 | (1 1) (1 0)
5736 00:22:15.533023 0 14 28 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
5737 00:22:15.536599 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5738 00:22:15.539272 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5739 00:22:15.546114 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5740 00:22:15.549597 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5741 00:22:15.552679 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5742 00:22:15.559132 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5743 00:22:15.562477 0 15 24 | B1->B0 | 2b2b 3434 | 0 0 | (0 0) (0 0)
5744 00:22:15.565673 0 15 28 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
5745 00:22:15.572235 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5746 00:22:15.575631 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5747 00:22:15.578884 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5748 00:22:15.585532 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5749 00:22:15.588727 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5750 00:22:15.592347 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5751 00:22:15.598657 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5752 00:22:15.601940 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5753 00:22:15.605234 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5754 00:22:15.612059 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5755 00:22:15.614886 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5756 00:22:15.618314 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5757 00:22:15.625092 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5758 00:22:15.628223 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5759 00:22:15.631215 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5760 00:22:15.638237 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5761 00:22:15.641048 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5762 00:22:15.644389 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5763 00:22:15.651474 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5764 00:22:15.654523 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5765 00:22:15.657478 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5766 00:22:15.664221 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5767 00:22:15.667616 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5768 00:22:15.671223 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5769 00:22:15.674027 Total UI for P1: 0, mck2ui 16
5770 00:22:15.677571 best dqsien dly found for B0: ( 1, 2, 24)
5771 00:22:15.683900 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5772 00:22:15.683995 Total UI for P1: 0, mck2ui 16
5773 00:22:15.690716 best dqsien dly found for B1: ( 1, 2, 26)
5774 00:22:15.694070 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5775 00:22:15.697935 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5776 00:22:15.698027
5777 00:22:15.701223 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5778 00:22:15.703855 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5779 00:22:15.707262 [Gating] SW calibration Done
5780 00:22:15.707350 ==
5781 00:22:15.710499 Dram Type= 6, Freq= 0, CH_1, rank 1
5782 00:22:15.713692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5783 00:22:15.713780 ==
5784 00:22:15.717267 RX Vref Scan: 0
5785 00:22:15.717367
5786 00:22:15.717431 RX Vref 0 -> 0, step: 1
5787 00:22:15.720484
5788 00:22:15.720566 RX Delay -80 -> 252, step: 8
5789 00:22:15.726532 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5790 00:22:15.730428 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5791 00:22:15.733379 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5792 00:22:15.736528 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5793 00:22:15.740258 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5794 00:22:15.743532 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5795 00:22:15.750326 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5796 00:22:15.753133 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5797 00:22:15.756274 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5798 00:22:15.759635 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5799 00:22:15.762999 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5800 00:22:15.766479 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5801 00:22:15.772926 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5802 00:22:15.776110 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5803 00:22:15.779598 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5804 00:22:15.782590 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5805 00:22:15.782677 ==
5806 00:22:15.786138 Dram Type= 6, Freq= 0, CH_1, rank 1
5807 00:22:15.792996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5808 00:22:15.793155 ==
5809 00:22:15.793249 DQS Delay:
5810 00:22:15.796318 DQS0 = 0, DQS1 = 0
5811 00:22:15.796401 DQM Delay:
5812 00:22:15.796464 DQM0 = 97, DQM1 = 94
5813 00:22:15.799555 DQ Delay:
5814 00:22:15.803033 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =95
5815 00:22:15.805928 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5816 00:22:15.809219 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5817 00:22:15.812108 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5818 00:22:15.812211
5819 00:22:15.812301
5820 00:22:15.812387 ==
5821 00:22:15.815409 Dram Type= 6, Freq= 0, CH_1, rank 1
5822 00:22:15.819058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5823 00:22:15.819150 ==
5824 00:22:15.819215
5825 00:22:15.819324
5826 00:22:15.822047 TX Vref Scan disable
5827 00:22:15.825869 == TX Byte 0 ==
5828 00:22:15.828491 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5829 00:22:15.832134 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5830 00:22:15.835626 == TX Byte 1 ==
5831 00:22:15.838849 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5832 00:22:15.841732 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5833 00:22:15.841820 ==
5834 00:22:15.845516 Dram Type= 6, Freq= 0, CH_1, rank 1
5835 00:22:15.851642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5836 00:22:15.851762 ==
5837 00:22:15.851857
5838 00:22:15.851946
5839 00:22:15.852038 TX Vref Scan disable
5840 00:22:15.855824 == TX Byte 0 ==
5841 00:22:15.859624 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5842 00:22:15.865775 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5843 00:22:15.865895 == TX Byte 1 ==
5844 00:22:15.869227 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5845 00:22:15.875794 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5846 00:22:15.875910
5847 00:22:15.876009 [DATLAT]
5848 00:22:15.876101 Freq=933, CH1 RK1
5849 00:22:15.876192
5850 00:22:15.878930 DATLAT Default: 0xb
5851 00:22:15.879040 0, 0xFFFF, sum = 0
5852 00:22:15.882388 1, 0xFFFF, sum = 0
5853 00:22:15.885813 2, 0xFFFF, sum = 0
5854 00:22:15.885926 3, 0xFFFF, sum = 0
5855 00:22:15.889214 4, 0xFFFF, sum = 0
5856 00:22:15.889312 5, 0xFFFF, sum = 0
5857 00:22:15.892468 6, 0xFFFF, sum = 0
5858 00:22:15.892569 7, 0xFFFF, sum = 0
5859 00:22:15.895752 8, 0xFFFF, sum = 0
5860 00:22:15.895871 9, 0xFFFF, sum = 0
5861 00:22:15.899510 10, 0x0, sum = 1
5862 00:22:15.899627 11, 0x0, sum = 2
5863 00:22:15.902301 12, 0x0, sum = 3
5864 00:22:15.902392 13, 0x0, sum = 4
5865 00:22:15.902459 best_step = 11
5866 00:22:15.905510
5867 00:22:15.905594 ==
5868 00:22:15.908650 Dram Type= 6, Freq= 0, CH_1, rank 1
5869 00:22:15.912195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5870 00:22:15.912281 ==
5871 00:22:15.912346 RX Vref Scan: 0
5872 00:22:15.912406
5873 00:22:15.915751 RX Vref 0 -> 0, step: 1
5874 00:22:15.915835
5875 00:22:15.918817 RX Delay -53 -> 252, step: 4
5876 00:22:15.925231 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5877 00:22:15.928457 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
5878 00:22:15.932261 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5879 00:22:15.935088 iDelay=199, Bit 3, Center 96 (3 ~ 190) 188
5880 00:22:15.938697 iDelay=199, Bit 4, Center 98 (7 ~ 190) 184
5881 00:22:15.941739 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5882 00:22:15.948484 iDelay=199, Bit 6, Center 104 (15 ~ 194) 180
5883 00:22:15.951710 iDelay=199, Bit 7, Center 94 (3 ~ 186) 184
5884 00:22:15.954870 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5885 00:22:15.958530 iDelay=199, Bit 9, Center 84 (-5 ~ 174) 180
5886 00:22:15.961589 iDelay=199, Bit 10, Center 92 (-1 ~ 186) 188
5887 00:22:15.968471 iDelay=199, Bit 11, Center 86 (-5 ~ 178) 184
5888 00:22:15.971338 iDelay=199, Bit 12, Center 100 (11 ~ 190) 180
5889 00:22:15.974613 iDelay=199, Bit 13, Center 100 (11 ~ 190) 180
5890 00:22:15.978381 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5891 00:22:15.981229 iDelay=199, Bit 15, Center 102 (11 ~ 194) 184
5892 00:22:15.984877 ==
5893 00:22:15.984955 Dram Type= 6, Freq= 0, CH_1, rank 1
5894 00:22:15.991291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5895 00:22:15.991407 ==
5896 00:22:15.991502 DQS Delay:
5897 00:22:15.994708 DQS0 = 0, DQS1 = 0
5898 00:22:15.994820 DQM Delay:
5899 00:22:15.998189 DQM0 = 97, DQM1 = 92
5900 00:22:15.998361 DQ Delay:
5901 00:22:16.000952 DQ0 =102, DQ1 =94, DQ2 =86, DQ3 =96
5902 00:22:16.004736 DQ4 =98, DQ5 =106, DQ6 =104, DQ7 =94
5903 00:22:16.007526 DQ8 =80, DQ9 =84, DQ10 =92, DQ11 =86
5904 00:22:16.010812 DQ12 =100, DQ13 =100, DQ14 =98, DQ15 =102
5905 00:22:16.010897
5906 00:22:16.010962
5907 00:22:16.020836 [DQSOSCAuto] RK1, (LSB)MR18= 0x132a, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 415 ps
5908 00:22:16.020934 CH1 RK1: MR19=505, MR18=132A
5909 00:22:16.027792 CH1_RK1: MR19=0x505, MR18=0x132A, DQSOSC=408, MR23=63, INC=65, DEC=43
5910 00:22:16.030551 [RxdqsGatingPostProcess] freq 933
5911 00:22:16.037198 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5912 00:22:16.040602 best DQS0 dly(2T, 0.5T) = (0, 10)
5913 00:22:16.043723 best DQS1 dly(2T, 0.5T) = (0, 10)
5914 00:22:16.047099 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5915 00:22:16.050379 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5916 00:22:16.054126 best DQS0 dly(2T, 0.5T) = (0, 10)
5917 00:22:16.054212 best DQS1 dly(2T, 0.5T) = (0, 10)
5918 00:22:16.056865 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5919 00:22:16.060003 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5920 00:22:16.063873 Pre-setting of DQS Precalculation
5921 00:22:16.070352 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5922 00:22:16.076854 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5923 00:22:16.083819 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5924 00:22:16.083921
5925 00:22:16.083985
5926 00:22:16.087257 [Calibration Summary] 1866 Mbps
5927 00:22:16.090005 CH 0, Rank 0
5928 00:22:16.090090 SW Impedance : PASS
5929 00:22:16.093463 DUTY Scan : NO K
5930 00:22:16.093548 ZQ Calibration : PASS
5931 00:22:16.096624 Jitter Meter : NO K
5932 00:22:16.100320 CBT Training : PASS
5933 00:22:16.100429 Write leveling : PASS
5934 00:22:16.103352 RX DQS gating : PASS
5935 00:22:16.106612 RX DQ/DQS(RDDQC) : PASS
5936 00:22:16.106729 TX DQ/DQS : PASS
5937 00:22:16.110125 RX DATLAT : PASS
5938 00:22:16.112946 RX DQ/DQS(Engine): PASS
5939 00:22:16.113085 TX OE : NO K
5940 00:22:16.116940 All Pass.
5941 00:22:16.117053
5942 00:22:16.117148 CH 0, Rank 1
5943 00:22:16.120130 SW Impedance : PASS
5944 00:22:16.120238 DUTY Scan : NO K
5945 00:22:16.123390 ZQ Calibration : PASS
5946 00:22:16.126874 Jitter Meter : NO K
5947 00:22:16.126954 CBT Training : PASS
5948 00:22:16.130055 Write leveling : PASS
5949 00:22:16.133150 RX DQS gating : PASS
5950 00:22:16.133251 RX DQ/DQS(RDDQC) : PASS
5951 00:22:16.136049 TX DQ/DQS : PASS
5952 00:22:16.139508 RX DATLAT : PASS
5953 00:22:16.139634 RX DQ/DQS(Engine): PASS
5954 00:22:16.142579 TX OE : NO K
5955 00:22:16.142685 All Pass.
5956 00:22:16.142774
5957 00:22:16.146072 CH 1, Rank 0
5958 00:22:16.146174 SW Impedance : PASS
5959 00:22:16.149418 DUTY Scan : NO K
5960 00:22:16.152696 ZQ Calibration : PASS
5961 00:22:16.152807 Jitter Meter : NO K
5962 00:22:16.156253 CBT Training : PASS
5963 00:22:16.159087 Write leveling : PASS
5964 00:22:16.159209 RX DQS gating : PASS
5965 00:22:16.162914 RX DQ/DQS(RDDQC) : PASS
5966 00:22:16.165815 TX DQ/DQS : PASS
5967 00:22:16.165896 RX DATLAT : PASS
5968 00:22:16.169154 RX DQ/DQS(Engine): PASS
5969 00:22:16.169254 TX OE : NO K
5970 00:22:16.172803 All Pass.
5971 00:22:16.172902
5972 00:22:16.172993 CH 1, Rank 1
5973 00:22:16.175818 SW Impedance : PASS
5974 00:22:16.175925 DUTY Scan : NO K
5975 00:22:16.179464 ZQ Calibration : PASS
5976 00:22:16.182555 Jitter Meter : NO K
5977 00:22:16.182635 CBT Training : PASS
5978 00:22:16.185676 Write leveling : PASS
5979 00:22:16.188884 RX DQS gating : PASS
5980 00:22:16.188992 RX DQ/DQS(RDDQC) : PASS
5981 00:22:16.192705 TX DQ/DQS : PASS
5982 00:22:16.195471 RX DATLAT : PASS
5983 00:22:16.195573 RX DQ/DQS(Engine): PASS
5984 00:22:16.199040 TX OE : NO K
5985 00:22:16.199144 All Pass.
5986 00:22:16.199266
5987 00:22:16.202536 DramC Write-DBI off
5988 00:22:16.205213 PER_BANK_REFRESH: Hybrid Mode
5989 00:22:16.205348 TX_TRACKING: ON
5990 00:22:16.215051 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5991 00:22:16.218845 [FAST_K] Save calibration result to emmc
5992 00:22:16.221658 dramc_set_vcore_voltage set vcore to 650000
5993 00:22:16.225146 Read voltage for 400, 6
5994 00:22:16.225252 Vio18 = 0
5995 00:22:16.228092 Vcore = 650000
5996 00:22:16.228198 Vdram = 0
5997 00:22:16.228288 Vddq = 0
5998 00:22:16.228363 Vmddr = 0
5999 00:22:16.234877 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6000 00:22:16.241614 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6001 00:22:16.241714 MEM_TYPE=3, freq_sel=20
6002 00:22:16.245029 sv_algorithm_assistance_LP4_800
6003 00:22:16.248522 ============ PULL DRAM RESETB DOWN ============
6004 00:22:16.254639 ========== PULL DRAM RESETB DOWN end =========
6005 00:22:16.258242 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6006 00:22:16.261133 ===================================
6007 00:22:16.264883 LPDDR4 DRAM CONFIGURATION
6008 00:22:16.267778 ===================================
6009 00:22:16.267860 EX_ROW_EN[0] = 0x0
6010 00:22:16.271416 EX_ROW_EN[1] = 0x0
6011 00:22:16.271499 LP4Y_EN = 0x0
6012 00:22:16.274363 WORK_FSP = 0x0
6013 00:22:16.277547 WL = 0x2
6014 00:22:16.277624 RL = 0x2
6015 00:22:16.280974 BL = 0x2
6016 00:22:16.281077 RPST = 0x0
6017 00:22:16.284250 RD_PRE = 0x0
6018 00:22:16.284349 WR_PRE = 0x1
6019 00:22:16.287742 WR_PST = 0x0
6020 00:22:16.287814 DBI_WR = 0x0
6021 00:22:16.291007 DBI_RD = 0x0
6022 00:22:16.291097 OTF = 0x1
6023 00:22:16.294191 ===================================
6024 00:22:16.297266 ===================================
6025 00:22:16.300612 ANA top config
6026 00:22:16.304100 ===================================
6027 00:22:16.304268 DLL_ASYNC_EN = 0
6028 00:22:16.307078 ALL_SLAVE_EN = 1
6029 00:22:16.310417 NEW_RANK_MODE = 1
6030 00:22:16.313825 DLL_IDLE_MODE = 1
6031 00:22:16.317203 LP45_APHY_COMB_EN = 1
6032 00:22:16.317352 TX_ODT_DIS = 1
6033 00:22:16.320539 NEW_8X_MODE = 1
6034 00:22:16.323866 ===================================
6035 00:22:16.327242 ===================================
6036 00:22:16.330324 data_rate = 800
6037 00:22:16.333941 CKR = 1
6038 00:22:16.337484 DQ_P2S_RATIO = 4
6039 00:22:16.340473 ===================================
6040 00:22:16.343547 CA_P2S_RATIO = 4
6041 00:22:16.343658 DQ_CA_OPEN = 0
6042 00:22:16.347065 DQ_SEMI_OPEN = 1
6043 00:22:16.350355 CA_SEMI_OPEN = 1
6044 00:22:16.353159 CA_FULL_RATE = 0
6045 00:22:16.356489 DQ_CKDIV4_EN = 0
6046 00:22:16.360884 CA_CKDIV4_EN = 1
6047 00:22:16.360993 CA_PREDIV_EN = 0
6048 00:22:16.363154 PH8_DLY = 0
6049 00:22:16.366671 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6050 00:22:16.369623 DQ_AAMCK_DIV = 0
6051 00:22:16.373324 CA_AAMCK_DIV = 0
6052 00:22:16.376470 CA_ADMCK_DIV = 4
6053 00:22:16.376569 DQ_TRACK_CA_EN = 0
6054 00:22:16.379926 CA_PICK = 800
6055 00:22:16.382995 CA_MCKIO = 400
6056 00:22:16.386257 MCKIO_SEMI = 400
6057 00:22:16.389906 PLL_FREQ = 3016
6058 00:22:16.392677 DQ_UI_PI_RATIO = 32
6059 00:22:16.396191 CA_UI_PI_RATIO = 32
6060 00:22:16.399658 ===================================
6061 00:22:16.402515 ===================================
6062 00:22:16.405936 memory_type:LPDDR4
6063 00:22:16.406024 GP_NUM : 10
6064 00:22:16.409136 SRAM_EN : 1
6065 00:22:16.409247 MD32_EN : 0
6066 00:22:16.412663 ===================================
6067 00:22:16.416535 [ANA_INIT] >>>>>>>>>>>>>>
6068 00:22:16.419064 <<<<<< [CONFIGURE PHASE]: ANA_TX
6069 00:22:16.422667 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6070 00:22:16.426041 ===================================
6071 00:22:16.429186 data_rate = 800,PCW = 0X7400
6072 00:22:16.432450 ===================================
6073 00:22:16.435736 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6074 00:22:16.439174 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6075 00:22:16.452035 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6076 00:22:16.455453 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6077 00:22:16.458727 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6078 00:22:16.462025 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6079 00:22:16.465229 [ANA_INIT] flow start
6080 00:22:16.468378 [ANA_INIT] PLL >>>>>>>>
6081 00:22:16.468461 [ANA_INIT] PLL <<<<<<<<
6082 00:22:16.471769 [ANA_INIT] MIDPI >>>>>>>>
6083 00:22:16.475056 [ANA_INIT] MIDPI <<<<<<<<
6084 00:22:16.478614 [ANA_INIT] DLL >>>>>>>>
6085 00:22:16.478731 [ANA_INIT] flow end
6086 00:22:16.481526 ============ LP4 DIFF to SE enter ============
6087 00:22:16.488273 ============ LP4 DIFF to SE exit ============
6088 00:22:16.488394 [ANA_INIT] <<<<<<<<<<<<<
6089 00:22:16.491762 [Flow] Enable top DCM control >>>>>
6090 00:22:16.495044 [Flow] Enable top DCM control <<<<<
6091 00:22:16.498353 Enable DLL master slave shuffle
6092 00:22:16.504953 ==============================================================
6093 00:22:16.505089 Gating Mode config
6094 00:22:16.511207 ==============================================================
6095 00:22:16.514561 Config description:
6096 00:22:16.524398 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6097 00:22:16.530943 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6098 00:22:16.534259 SELPH_MODE 0: By rank 1: By Phase
6099 00:22:16.541623 ==============================================================
6100 00:22:16.544167 GAT_TRACK_EN = 0
6101 00:22:16.547349 RX_GATING_MODE = 2
6102 00:22:16.551172 RX_GATING_TRACK_MODE = 2
6103 00:22:16.554115 SELPH_MODE = 1
6104 00:22:16.554222 PICG_EARLY_EN = 1
6105 00:22:16.557250 VALID_LAT_VALUE = 1
6106 00:22:16.564467 ==============================================================
6107 00:22:16.566914 Enter into Gating configuration >>>>
6108 00:22:16.570210 Exit from Gating configuration <<<<
6109 00:22:16.573635 Enter into DVFS_PRE_config >>>>>
6110 00:22:16.584187 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6111 00:22:16.586758 Exit from DVFS_PRE_config <<<<<
6112 00:22:16.589981 Enter into PICG configuration >>>>
6113 00:22:16.593357 Exit from PICG configuration <<<<
6114 00:22:16.596793 [RX_INPUT] configuration >>>>>
6115 00:22:16.600457 [RX_INPUT] configuration <<<<<
6116 00:22:16.606695 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6117 00:22:16.610141 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6118 00:22:16.616776 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6119 00:22:16.623217 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6120 00:22:16.630036 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6121 00:22:16.636294 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6122 00:22:16.639928 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6123 00:22:16.643153 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6124 00:22:16.646359 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6125 00:22:16.653120 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6126 00:22:16.656395 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6127 00:22:16.660058 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6128 00:22:16.663339 ===================================
6129 00:22:16.666249 LPDDR4 DRAM CONFIGURATION
6130 00:22:16.669356 ===================================
6131 00:22:16.669444 EX_ROW_EN[0] = 0x0
6132 00:22:16.672491 EX_ROW_EN[1] = 0x0
6133 00:22:16.675926 LP4Y_EN = 0x0
6134 00:22:16.676029 WORK_FSP = 0x0
6135 00:22:16.679028 WL = 0x2
6136 00:22:16.679130 RL = 0x2
6137 00:22:16.683018 BL = 0x2
6138 00:22:16.683127 RPST = 0x0
6139 00:22:16.685681 RD_PRE = 0x0
6140 00:22:16.685754 WR_PRE = 0x1
6141 00:22:16.688993 WR_PST = 0x0
6142 00:22:16.689101 DBI_WR = 0x0
6143 00:22:16.692427 DBI_RD = 0x0
6144 00:22:16.692528 OTF = 0x1
6145 00:22:16.695668 ===================================
6146 00:22:16.702079 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6147 00:22:16.705673 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6148 00:22:16.709009 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6149 00:22:16.712636 ===================================
6150 00:22:16.715844 LPDDR4 DRAM CONFIGURATION
6151 00:22:16.719085 ===================================
6152 00:22:16.721987 EX_ROW_EN[0] = 0x10
6153 00:22:16.722071 EX_ROW_EN[1] = 0x0
6154 00:22:16.725426 LP4Y_EN = 0x0
6155 00:22:16.725508 WORK_FSP = 0x0
6156 00:22:16.728795 WL = 0x2
6157 00:22:16.728903 RL = 0x2
6158 00:22:16.731714 BL = 0x2
6159 00:22:16.731796 RPST = 0x0
6160 00:22:16.735135 RD_PRE = 0x0
6161 00:22:16.735218 WR_PRE = 0x1
6162 00:22:16.738497 WR_PST = 0x0
6163 00:22:16.738588 DBI_WR = 0x0
6164 00:22:16.741560 DBI_RD = 0x0
6165 00:22:16.741644 OTF = 0x1
6166 00:22:16.745254 ===================================
6167 00:22:16.751481 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6168 00:22:16.756158 nWR fixed to 30
6169 00:22:16.759998 [ModeRegInit_LP4] CH0 RK0
6170 00:22:16.760105 [ModeRegInit_LP4] CH0 RK1
6171 00:22:16.763549 [ModeRegInit_LP4] CH1 RK0
6172 00:22:16.766255 [ModeRegInit_LP4] CH1 RK1
6173 00:22:16.766338 match AC timing 19
6174 00:22:16.773061 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6175 00:22:16.776595 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6176 00:22:16.779691 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6177 00:22:16.786133 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6178 00:22:16.789611 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6179 00:22:16.789703 ==
6180 00:22:16.792768 Dram Type= 6, Freq= 0, CH_0, rank 0
6181 00:22:16.796065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6182 00:22:16.796170 ==
6183 00:22:16.802939 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6184 00:22:16.809564 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6185 00:22:16.812566 [CA 0] Center 36 (8~64) winsize 57
6186 00:22:16.815965 [CA 1] Center 36 (8~64) winsize 57
6187 00:22:16.819417 [CA 2] Center 36 (8~64) winsize 57
6188 00:22:16.822725 [CA 3] Center 36 (8~64) winsize 57
6189 00:22:16.826074 [CA 4] Center 36 (8~64) winsize 57
6190 00:22:16.826163 [CA 5] Center 36 (8~64) winsize 57
6191 00:22:16.829026
6192 00:22:16.832503 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6193 00:22:16.832610
6194 00:22:16.836314 [CATrainingPosCal] consider 1 rank data
6195 00:22:16.839486 u2DelayCellTimex100 = 270/100 ps
6196 00:22:16.842256 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6197 00:22:16.845770 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6198 00:22:16.849228 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6199 00:22:16.852156 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6200 00:22:16.855485 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6201 00:22:16.858727 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6202 00:22:16.858828
6203 00:22:16.862044 CA PerBit enable=1, Macro0, CA PI delay=36
6204 00:22:16.865589
6205 00:22:16.865671 [CBTSetCACLKResult] CA Dly = 36
6206 00:22:16.868474 CS Dly: 1 (0~32)
6207 00:22:16.868559 ==
6208 00:22:16.872052 Dram Type= 6, Freq= 0, CH_0, rank 1
6209 00:22:16.875081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6210 00:22:16.875190 ==
6211 00:22:16.881928 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6212 00:22:16.888337 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6213 00:22:16.892232 [CA 0] Center 36 (8~64) winsize 57
6214 00:22:16.894923 [CA 1] Center 36 (8~64) winsize 57
6215 00:22:16.898382 [CA 2] Center 36 (8~64) winsize 57
6216 00:22:16.898488 [CA 3] Center 36 (8~64) winsize 57
6217 00:22:16.901950 [CA 4] Center 36 (8~64) winsize 57
6218 00:22:16.904760 [CA 5] Center 36 (8~64) winsize 57
6219 00:22:16.904872
6220 00:22:16.911654 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6221 00:22:16.911772
6222 00:22:16.915533 [CATrainingPosCal] consider 2 rank data
6223 00:22:16.918372 u2DelayCellTimex100 = 270/100 ps
6224 00:22:16.921523 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6225 00:22:16.924750 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6226 00:22:16.927814 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6227 00:22:16.931610 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6228 00:22:16.934493 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6229 00:22:16.938036 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6230 00:22:16.938114
6231 00:22:16.941627 CA PerBit enable=1, Macro0, CA PI delay=36
6232 00:22:16.941745
6233 00:22:16.944382 [CBTSetCACLKResult] CA Dly = 36
6234 00:22:16.947683 CS Dly: 1 (0~32)
6235 00:22:16.947790
6236 00:22:16.951294 ----->DramcWriteLeveling(PI) begin...
6237 00:22:16.951404 ==
6238 00:22:16.954216 Dram Type= 6, Freq= 0, CH_0, rank 0
6239 00:22:16.957606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6240 00:22:16.957689 ==
6241 00:22:16.960739 Write leveling (Byte 0): 40 => 8
6242 00:22:16.964304 Write leveling (Byte 1): 40 => 8
6243 00:22:16.967350 DramcWriteLeveling(PI) end<-----
6244 00:22:16.967461
6245 00:22:16.967551 ==
6246 00:22:16.970628 Dram Type= 6, Freq= 0, CH_0, rank 0
6247 00:22:16.974642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6248 00:22:16.974861 ==
6249 00:22:16.977183 [Gating] SW mode calibration
6250 00:22:16.983918 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6251 00:22:16.990723 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6252 00:22:16.993830 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6253 00:22:17.000308 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6254 00:22:17.003697 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6255 00:22:17.006784 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6256 00:22:17.013738 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6257 00:22:17.017107 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6258 00:22:17.020151 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6259 00:22:17.026775 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6260 00:22:17.030334 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6261 00:22:17.033043 Total UI for P1: 0, mck2ui 16
6262 00:22:17.036818 best dqsien dly found for B0: ( 0, 14, 24)
6263 00:22:17.040200 Total UI for P1: 0, mck2ui 16
6264 00:22:17.043068 best dqsien dly found for B1: ( 0, 14, 24)
6265 00:22:17.046510 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6266 00:22:17.049830 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6267 00:22:17.049920
6268 00:22:17.053028 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6269 00:22:17.056304 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6270 00:22:17.059757 [Gating] SW calibration Done
6271 00:22:17.059858 ==
6272 00:22:17.063075 Dram Type= 6, Freq= 0, CH_0, rank 0
6273 00:22:17.066520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6274 00:22:17.069518 ==
6275 00:22:17.069623 RX Vref Scan: 0
6276 00:22:17.069730
6277 00:22:17.072936 RX Vref 0 -> 0, step: 1
6278 00:22:17.073041
6279 00:22:17.076218 RX Delay -410 -> 252, step: 16
6280 00:22:17.079595 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6281 00:22:17.083017 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6282 00:22:17.089655 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6283 00:22:17.092558 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6284 00:22:17.095792 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6285 00:22:17.099128 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6286 00:22:17.106139 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6287 00:22:17.108811 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6288 00:22:17.112124 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6289 00:22:17.115767 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6290 00:22:17.122105 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6291 00:22:17.125178 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6292 00:22:17.128926 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6293 00:22:17.131860 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6294 00:22:17.138838 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6295 00:22:17.141742 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6296 00:22:17.141887 ==
6297 00:22:17.145036 Dram Type= 6, Freq= 0, CH_0, rank 0
6298 00:22:17.148233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6299 00:22:17.148399 ==
6300 00:22:17.151695 DQS Delay:
6301 00:22:17.151880 DQS0 = 35, DQS1 = 59
6302 00:22:17.155340 DQM Delay:
6303 00:22:17.155492 DQM0 = 6, DQM1 = 17
6304 00:22:17.158194 DQ Delay:
6305 00:22:17.158330 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6306 00:22:17.161902 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6307 00:22:17.165192 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =16
6308 00:22:17.168115 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6309 00:22:17.168237
6310 00:22:17.168306
6311 00:22:17.168366 ==
6312 00:22:17.171529 Dram Type= 6, Freq= 0, CH_0, rank 0
6313 00:22:17.178003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6314 00:22:17.178137 ==
6315 00:22:17.178206
6316 00:22:17.178267
6317 00:22:17.178323 TX Vref Scan disable
6318 00:22:17.181442 == TX Byte 0 ==
6319 00:22:17.184762 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6320 00:22:17.187814 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6321 00:22:17.191236 == TX Byte 1 ==
6322 00:22:17.194193 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6323 00:22:17.197601 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6324 00:22:17.201045 ==
6325 00:22:17.204506 Dram Type= 6, Freq= 0, CH_0, rank 0
6326 00:22:17.207673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6327 00:22:17.207824 ==
6328 00:22:17.207961
6329 00:22:17.208083
6330 00:22:17.211287 TX Vref Scan disable
6331 00:22:17.211448 == TX Byte 0 ==
6332 00:22:17.214299 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6333 00:22:17.220839 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6334 00:22:17.221014 == TX Byte 1 ==
6335 00:22:17.224316 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6336 00:22:17.230585 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6337 00:22:17.230759
6338 00:22:17.230867 [DATLAT]
6339 00:22:17.230962 Freq=400, CH0 RK0
6340 00:22:17.231055
6341 00:22:17.233784 DATLAT Default: 0xf
6342 00:22:17.237129 0, 0xFFFF, sum = 0
6343 00:22:17.237288 1, 0xFFFF, sum = 0
6344 00:22:17.240433 2, 0xFFFF, sum = 0
6345 00:22:17.240588 3, 0xFFFF, sum = 0
6346 00:22:17.243838 4, 0xFFFF, sum = 0
6347 00:22:17.243957 5, 0xFFFF, sum = 0
6348 00:22:17.247752 6, 0xFFFF, sum = 0
6349 00:22:17.247891 7, 0xFFFF, sum = 0
6350 00:22:17.250790 8, 0xFFFF, sum = 0
6351 00:22:17.250882 9, 0xFFFF, sum = 0
6352 00:22:17.253968 10, 0xFFFF, sum = 0
6353 00:22:17.254054 11, 0xFFFF, sum = 0
6354 00:22:17.257187 12, 0xFFFF, sum = 0
6355 00:22:17.257283 13, 0x0, sum = 1
6356 00:22:17.260460 14, 0x0, sum = 2
6357 00:22:17.260543 15, 0x0, sum = 3
6358 00:22:17.263752 16, 0x0, sum = 4
6359 00:22:17.263845 best_step = 14
6360 00:22:17.263916
6361 00:22:17.263976 ==
6362 00:22:17.267368 Dram Type= 6, Freq= 0, CH_0, rank 0
6363 00:22:17.273655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6364 00:22:17.273772 ==
6365 00:22:17.273875 RX Vref Scan: 1
6366 00:22:17.273965
6367 00:22:17.276621 RX Vref 0 -> 0, step: 1
6368 00:22:17.276730
6369 00:22:17.280424 RX Delay -359 -> 252, step: 8
6370 00:22:17.280536
6371 00:22:17.283358 Set Vref, RX VrefLevel [Byte0]: 55
6372 00:22:17.286576 [Byte1]: 48
6373 00:22:17.289935
6374 00:22:17.290070 Final RX Vref Byte 0 = 55 to rank0
6375 00:22:17.293285 Final RX Vref Byte 1 = 48 to rank0
6376 00:22:17.296434 Final RX Vref Byte 0 = 55 to rank1
6377 00:22:17.299799 Final RX Vref Byte 1 = 48 to rank1==
6378 00:22:17.303041 Dram Type= 6, Freq= 0, CH_0, rank 0
6379 00:22:17.309399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6380 00:22:17.309545 ==
6381 00:22:17.309639 DQS Delay:
6382 00:22:17.312666 DQS0 = 44, DQS1 = 60
6383 00:22:17.312749 DQM Delay:
6384 00:22:17.312813 DQM0 = 10, DQM1 = 17
6385 00:22:17.316150 DQ Delay:
6386 00:22:17.319424 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =4
6387 00:22:17.322813 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6388 00:22:17.326133 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =12
6389 00:22:17.329681 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =24
6390 00:22:17.329766
6391 00:22:17.329830
6392 00:22:17.336675 [DQSOSCAuto] RK0, (LSB)MR18= 0x9c90, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 390 ps
6393 00:22:17.339001 CH0 RK0: MR19=C0C, MR18=9C90
6394 00:22:17.345878 CH0_RK0: MR19=0xC0C, MR18=0x9C90, DQSOSC=390, MR23=63, INC=388, DEC=258
6395 00:22:17.346069 ==
6396 00:22:17.349305 Dram Type= 6, Freq= 0, CH_0, rank 1
6397 00:22:17.352307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6398 00:22:17.352450 ==
6399 00:22:17.355764 [Gating] SW mode calibration
6400 00:22:17.362621 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6401 00:22:17.369245 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6402 00:22:17.372168 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6403 00:22:17.375565 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6404 00:22:17.382517 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6405 00:22:17.386196 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6406 00:22:17.388635 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6407 00:22:17.395520 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6408 00:22:17.398761 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6409 00:22:17.402191 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6410 00:22:17.408898 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6411 00:22:17.411791 Total UI for P1: 0, mck2ui 16
6412 00:22:17.415341 best dqsien dly found for B0: ( 0, 14, 24)
6413 00:22:17.418303 Total UI for P1: 0, mck2ui 16
6414 00:22:17.421865 best dqsien dly found for B1: ( 0, 14, 24)
6415 00:22:17.424766 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6416 00:22:17.428070 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6417 00:22:17.428230
6418 00:22:17.431164 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6419 00:22:17.434988 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6420 00:22:17.438507 [Gating] SW calibration Done
6421 00:22:17.438595 ==
6422 00:22:17.441056 Dram Type= 6, Freq= 0, CH_0, rank 1
6423 00:22:17.444678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6424 00:22:17.444767 ==
6425 00:22:17.448093 RX Vref Scan: 0
6426 00:22:17.448180
6427 00:22:17.451785 RX Vref 0 -> 0, step: 1
6428 00:22:17.451868
6429 00:22:17.454857 RX Delay -410 -> 252, step: 16
6430 00:22:17.458031 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6431 00:22:17.461148 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6432 00:22:17.464492 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6433 00:22:17.471314 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6434 00:22:17.474013 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6435 00:22:17.477332 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6436 00:22:17.480824 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6437 00:22:17.487228 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6438 00:22:17.490815 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6439 00:22:17.494457 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6440 00:22:17.497247 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6441 00:22:17.503946 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6442 00:22:17.507592 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6443 00:22:17.510247 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6444 00:22:17.517195 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6445 00:22:17.520278 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6446 00:22:17.520370 ==
6447 00:22:17.523393 Dram Type= 6, Freq= 0, CH_0, rank 1
6448 00:22:17.527027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6449 00:22:17.527115 ==
6450 00:22:17.530414 DQS Delay:
6451 00:22:17.530524 DQS0 = 35, DQS1 = 59
6452 00:22:17.533194 DQM Delay:
6453 00:22:17.533334 DQM0 = 6, DQM1 = 17
6454 00:22:17.533413 DQ Delay:
6455 00:22:17.536595 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6456 00:22:17.540068 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6457 00:22:17.543418 DQ8 =8, DQ9 =0, DQ10 =24, DQ11 =8
6458 00:22:17.546799 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6459 00:22:17.546889
6460 00:22:17.546954
6461 00:22:17.547013 ==
6462 00:22:17.549535 Dram Type= 6, Freq= 0, CH_0, rank 1
6463 00:22:17.556396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6464 00:22:17.556504 ==
6465 00:22:17.556574
6466 00:22:17.556635
6467 00:22:17.556693 TX Vref Scan disable
6468 00:22:17.559668 == TX Byte 0 ==
6469 00:22:17.562908 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6470 00:22:17.566171 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6471 00:22:17.569920 == TX Byte 1 ==
6472 00:22:17.572727 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6473 00:22:17.576678 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6474 00:22:17.576890 ==
6475 00:22:17.579673 Dram Type= 6, Freq= 0, CH_0, rank 1
6476 00:22:17.585786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6477 00:22:17.585978 ==
6478 00:22:17.586132
6479 00:22:17.586279
6480 00:22:17.586422 TX Vref Scan disable
6481 00:22:17.589358 == TX Byte 0 ==
6482 00:22:17.592561 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6483 00:22:17.596725 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6484 00:22:17.599304 == TX Byte 1 ==
6485 00:22:17.602660 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6486 00:22:17.605999 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6487 00:22:17.606180
6488 00:22:17.609149 [DATLAT]
6489 00:22:17.609324 Freq=400, CH0 RK1
6490 00:22:17.609474
6491 00:22:17.612634 DATLAT Default: 0xe
6492 00:22:17.612795 0, 0xFFFF, sum = 0
6493 00:22:17.616235 1, 0xFFFF, sum = 0
6494 00:22:17.616401 2, 0xFFFF, sum = 0
6495 00:22:17.619307 3, 0xFFFF, sum = 0
6496 00:22:17.619473 4, 0xFFFF, sum = 0
6497 00:22:17.622211 5, 0xFFFF, sum = 0
6498 00:22:17.622375 6, 0xFFFF, sum = 0
6499 00:22:17.625719 7, 0xFFFF, sum = 0
6500 00:22:17.625882 8, 0xFFFF, sum = 0
6501 00:22:17.628898 9, 0xFFFF, sum = 0
6502 00:22:17.632230 10, 0xFFFF, sum = 0
6503 00:22:17.632403 11, 0xFFFF, sum = 0
6504 00:22:17.635332 12, 0xFFFF, sum = 0
6505 00:22:17.635499 13, 0x0, sum = 1
6506 00:22:17.638867 14, 0x0, sum = 2
6507 00:22:17.639022 15, 0x0, sum = 3
6508 00:22:17.641990 16, 0x0, sum = 4
6509 00:22:17.642134 best_step = 14
6510 00:22:17.642264
6511 00:22:17.642388 ==
6512 00:22:17.645497 Dram Type= 6, Freq= 0, CH_0, rank 1
6513 00:22:17.648677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6514 00:22:17.648836 ==
6515 00:22:17.652015 RX Vref Scan: 0
6516 00:22:17.652125
6517 00:22:17.655307 RX Vref 0 -> 0, step: 1
6518 00:22:17.655415
6519 00:22:17.658912 RX Delay -359 -> 252, step: 8
6520 00:22:17.662000 iDelay=209, Bit 0, Center -36 (-271 ~ 200) 472
6521 00:22:17.668203 iDelay=209, Bit 1, Center -32 (-271 ~ 208) 480
6522 00:22:17.671793 iDelay=209, Bit 2, Center -40 (-279 ~ 200) 480
6523 00:22:17.675137 iDelay=209, Bit 3, Center -40 (-279 ~ 200) 480
6524 00:22:17.681521 iDelay=209, Bit 4, Center -32 (-271 ~ 208) 480
6525 00:22:17.684851 iDelay=209, Bit 5, Center -44 (-279 ~ 192) 472
6526 00:22:17.688228 iDelay=209, Bit 6, Center -28 (-263 ~ 208) 472
6527 00:22:17.691458 iDelay=209, Bit 7, Center -28 (-263 ~ 208) 472
6528 00:22:17.697686 iDelay=209, Bit 8, Center -52 (-295 ~ 192) 488
6529 00:22:17.701013 iDelay=209, Bit 9, Center -60 (-303 ~ 184) 488
6530 00:22:17.704426 iDelay=209, Bit 10, Center -44 (-287 ~ 200) 488
6531 00:22:17.707634 iDelay=209, Bit 11, Center -48 (-287 ~ 192) 480
6532 00:22:17.714461 iDelay=209, Bit 12, Center -44 (-287 ~ 200) 488
6533 00:22:17.717615 iDelay=209, Bit 13, Center -40 (-279 ~ 200) 480
6534 00:22:17.720930 iDelay=209, Bit 14, Center -36 (-279 ~ 208) 488
6535 00:22:17.724699 iDelay=209, Bit 15, Center -40 (-279 ~ 200) 480
6536 00:22:17.727496 ==
6537 00:22:17.731135 Dram Type= 6, Freq= 0, CH_0, rank 1
6538 00:22:17.734426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6539 00:22:17.734555 ==
6540 00:22:17.734629 DQS Delay:
6541 00:22:17.737329 DQS0 = 44, DQS1 = 60
6542 00:22:17.737474 DQM Delay:
6543 00:22:17.740581 DQM0 = 9, DQM1 = 14
6544 00:22:17.740690 DQ Delay:
6545 00:22:17.744368 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =4
6546 00:22:17.747231 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6547 00:22:17.750957 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =12
6548 00:22:17.753706 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =20
6549 00:22:17.753850
6550 00:22:17.753948
6551 00:22:17.760551 [DQSOSCAuto] RK1, (LSB)MR18= 0x928b, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 391 ps
6552 00:22:17.764085 CH0 RK1: MR19=C0C, MR18=928B
6553 00:22:17.770395 CH0_RK1: MR19=0xC0C, MR18=0x928B, DQSOSC=391, MR23=63, INC=386, DEC=257
6554 00:22:17.773744 [RxdqsGatingPostProcess] freq 400
6555 00:22:17.780004 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6556 00:22:17.783444 best DQS0 dly(2T, 0.5T) = (0, 10)
6557 00:22:17.783581 best DQS1 dly(2T, 0.5T) = (0, 10)
6558 00:22:17.786754 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6559 00:22:17.790366 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6560 00:22:17.793244 best DQS0 dly(2T, 0.5T) = (0, 10)
6561 00:22:17.796819 best DQS1 dly(2T, 0.5T) = (0, 10)
6562 00:22:17.799630 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6563 00:22:17.803100 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6564 00:22:17.806716 Pre-setting of DQS Precalculation
6565 00:22:17.813098 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6566 00:22:17.813234 ==
6567 00:22:17.816424 Dram Type= 6, Freq= 0, CH_1, rank 0
6568 00:22:17.819517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6569 00:22:17.819641 ==
6570 00:22:17.826170 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6571 00:22:17.832868 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6572 00:22:17.833000 [CA 0] Center 36 (8~64) winsize 57
6573 00:22:17.836229 [CA 1] Center 36 (8~64) winsize 57
6574 00:22:17.839569 [CA 2] Center 36 (8~64) winsize 57
6575 00:22:17.842517 [CA 3] Center 36 (8~64) winsize 57
6576 00:22:17.845921 [CA 4] Center 36 (8~64) winsize 57
6577 00:22:17.849220 [CA 5] Center 36 (8~64) winsize 57
6578 00:22:17.849333
6579 00:22:17.852630 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6580 00:22:17.852759
6581 00:22:17.855913 [CATrainingPosCal] consider 1 rank data
6582 00:22:17.859175 u2DelayCellTimex100 = 270/100 ps
6583 00:22:17.862635 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6584 00:22:17.869582 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6585 00:22:17.872589 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6586 00:22:17.875755 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6587 00:22:17.879125 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6588 00:22:17.882097 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6589 00:22:17.882206
6590 00:22:17.885704 CA PerBit enable=1, Macro0, CA PI delay=36
6591 00:22:17.885802
6592 00:22:17.888861 [CBTSetCACLKResult] CA Dly = 36
6593 00:22:17.892196 CS Dly: 1 (0~32)
6594 00:22:17.892320 ==
6595 00:22:17.895429 Dram Type= 6, Freq= 0, CH_1, rank 1
6596 00:22:17.898737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6597 00:22:17.898873 ==
6598 00:22:17.905566 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6599 00:22:17.908537 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6600 00:22:17.911721 [CA 0] Center 36 (8~64) winsize 57
6601 00:22:17.915384 [CA 1] Center 36 (8~64) winsize 57
6602 00:22:17.918883 [CA 2] Center 36 (8~64) winsize 57
6603 00:22:17.921617 [CA 3] Center 36 (8~64) winsize 57
6604 00:22:17.924960 [CA 4] Center 36 (8~64) winsize 57
6605 00:22:17.928104 [CA 5] Center 36 (8~64) winsize 57
6606 00:22:17.928215
6607 00:22:17.931812 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6608 00:22:17.931922
6609 00:22:17.935296 [CATrainingPosCal] consider 2 rank data
6610 00:22:17.938094 u2DelayCellTimex100 = 270/100 ps
6611 00:22:17.941620 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6612 00:22:17.947802 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6613 00:22:17.951182 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6614 00:22:17.954456 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6615 00:22:17.958260 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6616 00:22:17.961476 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6617 00:22:17.961557
6618 00:22:17.964689 CA PerBit enable=1, Macro0, CA PI delay=36
6619 00:22:17.964789
6620 00:22:17.967822 [CBTSetCACLKResult] CA Dly = 36
6621 00:22:17.971225 CS Dly: 1 (0~32)
6622 00:22:17.971322
6623 00:22:17.974316 ----->DramcWriteLeveling(PI) begin...
6624 00:22:17.974414 ==
6625 00:22:17.977302 Dram Type= 6, Freq= 0, CH_1, rank 0
6626 00:22:17.981111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6627 00:22:17.981245 ==
6628 00:22:17.984303 Write leveling (Byte 0): 40 => 8
6629 00:22:17.987820 Write leveling (Byte 1): 40 => 8
6630 00:22:17.990899 DramcWriteLeveling(PI) end<-----
6631 00:22:17.990981
6632 00:22:17.991049 ==
6633 00:22:17.994381 Dram Type= 6, Freq= 0, CH_1, rank 0
6634 00:22:17.997919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6635 00:22:17.998003 ==
6636 00:22:18.000850 [Gating] SW mode calibration
6637 00:22:18.007279 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6638 00:22:18.013967 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6639 00:22:18.017313 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6640 00:22:18.020916 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6641 00:22:18.027161 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6642 00:22:18.030303 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6643 00:22:18.034039 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6644 00:22:18.040393 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6645 00:22:18.043235 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6646 00:22:18.046900 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6647 00:22:18.053650 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6648 00:22:18.056483 Total UI for P1: 0, mck2ui 16
6649 00:22:18.060150 best dqsien dly found for B0: ( 0, 14, 24)
6650 00:22:18.060300 Total UI for P1: 0, mck2ui 16
6651 00:22:18.066844 best dqsien dly found for B1: ( 0, 14, 24)
6652 00:22:18.069806 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6653 00:22:18.073436 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6654 00:22:18.073679
6655 00:22:18.076298 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6656 00:22:18.079561 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6657 00:22:18.082970 [Gating] SW calibration Done
6658 00:22:18.083150 ==
6659 00:22:18.086494 Dram Type= 6, Freq= 0, CH_1, rank 0
6660 00:22:18.089540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6661 00:22:18.089650 ==
6662 00:22:18.093222 RX Vref Scan: 0
6663 00:22:18.093375
6664 00:22:18.096120 RX Vref 0 -> 0, step: 1
6665 00:22:18.096218
6666 00:22:18.096284 RX Delay -410 -> 252, step: 16
6667 00:22:18.102791 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6668 00:22:18.106000 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6669 00:22:18.109374 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6670 00:22:18.116176 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6671 00:22:18.119183 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6672 00:22:18.122914 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6673 00:22:18.126095 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6674 00:22:18.132498 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6675 00:22:18.135835 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6676 00:22:18.139483 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6677 00:22:18.142236 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6678 00:22:18.149271 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6679 00:22:18.152363 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6680 00:22:18.155349 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6681 00:22:18.158810 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6682 00:22:18.165643 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6683 00:22:18.165757 ==
6684 00:22:18.168853 Dram Type= 6, Freq= 0, CH_1, rank 0
6685 00:22:18.171794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6686 00:22:18.171882 ==
6687 00:22:18.175271 DQS Delay:
6688 00:22:18.175356 DQS0 = 35, DQS1 = 51
6689 00:22:18.175421 DQM Delay:
6690 00:22:18.178497 DQM0 = 6, DQM1 = 13
6691 00:22:18.178583 DQ Delay:
6692 00:22:18.182362 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6693 00:22:18.185125 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6694 00:22:18.188318 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6695 00:22:18.191997 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6696 00:22:18.192091
6697 00:22:18.192157
6698 00:22:18.192221 ==
6699 00:22:18.195137 Dram Type= 6, Freq= 0, CH_1, rank 0
6700 00:22:18.198225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6701 00:22:18.198325 ==
6702 00:22:18.201691
6703 00:22:18.201777
6704 00:22:18.201842 TX Vref Scan disable
6705 00:22:18.205508 == TX Byte 0 ==
6706 00:22:18.208271 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6707 00:22:18.211909 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6708 00:22:18.215158 == TX Byte 1 ==
6709 00:22:18.218163 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6710 00:22:18.221562 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6711 00:22:18.221707 ==
6712 00:22:18.225117 Dram Type= 6, Freq= 0, CH_1, rank 0
6713 00:22:18.228175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6714 00:22:18.232057 ==
6715 00:22:18.232199
6716 00:22:18.232266
6717 00:22:18.232327 TX Vref Scan disable
6718 00:22:18.234797 == TX Byte 0 ==
6719 00:22:18.237988 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6720 00:22:18.241253 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6721 00:22:18.244774 == TX Byte 1 ==
6722 00:22:18.247779 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6723 00:22:18.251046 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6724 00:22:18.251190
6725 00:22:18.254386 [DATLAT]
6726 00:22:18.254510 Freq=400, CH1 RK0
6727 00:22:18.254580
6728 00:22:18.257772 DATLAT Default: 0xf
6729 00:22:18.257859 0, 0xFFFF, sum = 0
6730 00:22:18.261205 1, 0xFFFF, sum = 0
6731 00:22:18.261309 2, 0xFFFF, sum = 0
6732 00:22:18.264270 3, 0xFFFF, sum = 0
6733 00:22:18.264355 4, 0xFFFF, sum = 0
6734 00:22:18.267742 5, 0xFFFF, sum = 0
6735 00:22:18.267827 6, 0xFFFF, sum = 0
6736 00:22:18.270857 7, 0xFFFF, sum = 0
6737 00:22:18.270942 8, 0xFFFF, sum = 0
6738 00:22:18.274187 9, 0xFFFF, sum = 0
6739 00:22:18.274272 10, 0xFFFF, sum = 0
6740 00:22:18.277255 11, 0xFFFF, sum = 0
6741 00:22:18.281086 12, 0xFFFF, sum = 0
6742 00:22:18.281171 13, 0x0, sum = 1
6743 00:22:18.284269 14, 0x0, sum = 2
6744 00:22:18.284354 15, 0x0, sum = 3
6745 00:22:18.284420 16, 0x0, sum = 4
6746 00:22:18.287508 best_step = 14
6747 00:22:18.287592
6748 00:22:18.287657 ==
6749 00:22:18.290611 Dram Type= 6, Freq= 0, CH_1, rank 0
6750 00:22:18.293861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6751 00:22:18.293946 ==
6752 00:22:18.297187 RX Vref Scan: 1
6753 00:22:18.297299
6754 00:22:18.300872 RX Vref 0 -> 0, step: 1
6755 00:22:18.300982
6756 00:22:18.301079 RX Delay -343 -> 252, step: 8
6757 00:22:18.301168
6758 00:22:18.303962 Set Vref, RX VrefLevel [Byte0]: 50
6759 00:22:18.307182 [Byte1]: 50
6760 00:22:18.312433
6761 00:22:18.312527 Final RX Vref Byte 0 = 50 to rank0
6762 00:22:18.315837 Final RX Vref Byte 1 = 50 to rank0
6763 00:22:18.318910 Final RX Vref Byte 0 = 50 to rank1
6764 00:22:18.322279 Final RX Vref Byte 1 = 50 to rank1==
6765 00:22:18.325563 Dram Type= 6, Freq= 0, CH_1, rank 0
6766 00:22:18.332016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6767 00:22:18.332131 ==
6768 00:22:18.332232 DQS Delay:
6769 00:22:18.335725 DQS0 = 44, DQS1 = 56
6770 00:22:18.335831 DQM Delay:
6771 00:22:18.335926 DQM0 = 11, DQM1 = 14
6772 00:22:18.339075 DQ Delay:
6773 00:22:18.342450 DQ0 =20, DQ1 =4, DQ2 =0, DQ3 =12
6774 00:22:18.345595 DQ4 =8, DQ5 =20, DQ6 =24, DQ7 =4
6775 00:22:18.345701 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =4
6776 00:22:18.348773 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =20
6777 00:22:18.352222
6778 00:22:18.352298
6779 00:22:18.358403 [DQSOSCAuto] RK0, (LSB)MR18= 0x6b93, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 396 ps
6780 00:22:18.362422 CH1 RK0: MR19=C0C, MR18=6B93
6781 00:22:18.368478 CH1_RK0: MR19=0xC0C, MR18=0x6B93, DQSOSC=391, MR23=63, INC=386, DEC=257
6782 00:22:18.368563 ==
6783 00:22:18.372034 Dram Type= 6, Freq= 0, CH_1, rank 1
6784 00:22:18.374928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6785 00:22:18.375030 ==
6786 00:22:18.378371 [Gating] SW mode calibration
6787 00:22:18.385028 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6788 00:22:18.391512 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6789 00:22:18.394694 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6790 00:22:18.398252 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6791 00:22:18.405154 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6792 00:22:18.408178 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6793 00:22:18.411704 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6794 00:22:18.418107 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6795 00:22:18.421543 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6796 00:22:18.424973 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6797 00:22:18.431559 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6798 00:22:18.431760 Total UI for P1: 0, mck2ui 16
6799 00:22:18.437844 best dqsien dly found for B0: ( 0, 14, 24)
6800 00:22:18.438022 Total UI for P1: 0, mck2ui 16
6801 00:22:18.444625 best dqsien dly found for B1: ( 0, 14, 24)
6802 00:22:18.447447 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6803 00:22:18.451048 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6804 00:22:18.451131
6805 00:22:18.454218 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6806 00:22:18.457351 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6807 00:22:18.460615 [Gating] SW calibration Done
6808 00:22:18.460697 ==
6809 00:22:18.464285 Dram Type= 6, Freq= 0, CH_1, rank 1
6810 00:22:18.467586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6811 00:22:18.467671 ==
6812 00:22:18.470956 RX Vref Scan: 0
6813 00:22:18.471061
6814 00:22:18.474234 RX Vref 0 -> 0, step: 1
6815 00:22:18.474341
6816 00:22:18.474435 RX Delay -410 -> 252, step: 16
6817 00:22:18.480809 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6818 00:22:18.483732 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6819 00:22:18.487292 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6820 00:22:18.493708 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6821 00:22:18.497224 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6822 00:22:18.500093 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6823 00:22:18.503589 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6824 00:22:18.510026 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6825 00:22:18.513946 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6826 00:22:18.517017 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6827 00:22:18.520704 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6828 00:22:18.527104 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6829 00:22:18.530191 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6830 00:22:18.533098 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6831 00:22:18.536585 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6832 00:22:18.543295 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6833 00:22:18.543377 ==
6834 00:22:18.546289 Dram Type= 6, Freq= 0, CH_1, rank 1
6835 00:22:18.549861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6836 00:22:18.549966 ==
6837 00:22:18.550033 DQS Delay:
6838 00:22:18.553038 DQS0 = 43, DQS1 = 51
6839 00:22:18.553144 DQM Delay:
6840 00:22:18.556665 DQM0 = 9, DQM1 = 13
6841 00:22:18.556766 DQ Delay:
6842 00:22:18.559450 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6843 00:22:18.563197 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6844 00:22:18.566029 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6845 00:22:18.570074 DQ12 =16, DQ13 =24, DQ14 =16, DQ15 =24
6846 00:22:18.570185
6847 00:22:18.570255
6848 00:22:18.570315 ==
6849 00:22:18.573271 Dram Type= 6, Freq= 0, CH_1, rank 1
6850 00:22:18.576435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6851 00:22:18.576574 ==
6852 00:22:18.576674
6853 00:22:18.576763
6854 00:22:18.579600 TX Vref Scan disable
6855 00:22:18.582980 == TX Byte 0 ==
6856 00:22:18.586035 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6857 00:22:18.590072 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6858 00:22:18.592612 == TX Byte 1 ==
6859 00:22:18.596236 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6860 00:22:18.599219 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6861 00:22:18.599421 ==
6862 00:22:18.602973 Dram Type= 6, Freq= 0, CH_1, rank 1
6863 00:22:18.605815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6864 00:22:18.605989 ==
6865 00:22:18.609376
6866 00:22:18.609515
6867 00:22:18.609586 TX Vref Scan disable
6868 00:22:18.612582 == TX Byte 0 ==
6869 00:22:18.615906 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6870 00:22:18.618878 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6871 00:22:18.622338 == TX Byte 1 ==
6872 00:22:18.625736 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6873 00:22:18.628897 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6874 00:22:18.629066
6875 00:22:18.629174 [DATLAT]
6876 00:22:18.632268 Freq=400, CH1 RK1
6877 00:22:18.632421
6878 00:22:18.635399 DATLAT Default: 0xe
6879 00:22:18.635601 0, 0xFFFF, sum = 0
6880 00:22:18.638646 1, 0xFFFF, sum = 0
6881 00:22:18.638776 2, 0xFFFF, sum = 0
6882 00:22:18.642338 3, 0xFFFF, sum = 0
6883 00:22:18.642497 4, 0xFFFF, sum = 0
6884 00:22:18.645381 5, 0xFFFF, sum = 0
6885 00:22:18.645487 6, 0xFFFF, sum = 0
6886 00:22:18.648895 7, 0xFFFF, sum = 0
6887 00:22:18.649014 8, 0xFFFF, sum = 0
6888 00:22:18.652033 9, 0xFFFF, sum = 0
6889 00:22:18.652146 10, 0xFFFF, sum = 0
6890 00:22:18.655434 11, 0xFFFF, sum = 0
6891 00:22:18.655549 12, 0xFFFF, sum = 0
6892 00:22:18.658566 13, 0x0, sum = 1
6893 00:22:18.658679 14, 0x0, sum = 2
6894 00:22:18.661985 15, 0x0, sum = 3
6895 00:22:18.662071 16, 0x0, sum = 4
6896 00:22:18.665006 best_step = 14
6897 00:22:18.665117
6898 00:22:18.665210 ==
6899 00:22:18.668530 Dram Type= 6, Freq= 0, CH_1, rank 1
6900 00:22:18.671975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6901 00:22:18.672100 ==
6902 00:22:18.674985 RX Vref Scan: 0
6903 00:22:18.675071
6904 00:22:18.675137 RX Vref 0 -> 0, step: 1
6905 00:22:18.675198
6906 00:22:18.678656 RX Delay -343 -> 252, step: 8
6907 00:22:18.686394 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6908 00:22:18.690039 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6909 00:22:18.693023 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6910 00:22:18.699510 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6911 00:22:18.703222 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6912 00:22:18.706195 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6913 00:22:18.709869 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6914 00:22:18.716326 iDelay=217, Bit 7, Center -36 (-279 ~ 208) 488
6915 00:22:18.719194 iDelay=217, Bit 8, Center -56 (-295 ~ 184) 480
6916 00:22:18.722708 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6917 00:22:18.726342 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6918 00:22:18.732429 iDelay=217, Bit 11, Center -48 (-287 ~ 192) 480
6919 00:22:18.736252 iDelay=217, Bit 12, Center -32 (-271 ~ 208) 480
6920 00:22:18.739064 iDelay=217, Bit 13, Center -32 (-271 ~ 208) 480
6921 00:22:18.742606 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6922 00:22:18.749094 iDelay=217, Bit 15, Center -32 (-279 ~ 216) 496
6923 00:22:18.749215 ==
6924 00:22:18.752773 Dram Type= 6, Freq= 0, CH_1, rank 1
6925 00:22:18.755681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6926 00:22:18.755788 ==
6927 00:22:18.755887 DQS Delay:
6928 00:22:18.758841 DQS0 = 48, DQS1 = 56
6929 00:22:18.758915 DQM Delay:
6930 00:22:18.762148 DQM0 = 12, DQM1 = 15
6931 00:22:18.762242 DQ Delay:
6932 00:22:18.766001 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6933 00:22:18.768965 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =12
6934 00:22:18.772170 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6935 00:22:18.775153 DQ12 =24, DQ13 =24, DQ14 =20, DQ15 =24
6936 00:22:18.775243
6937 00:22:18.775325
6938 00:22:18.785168 [DQSOSCAuto] RK1, (LSB)MR18= 0x80b8, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 393 ps
6939 00:22:18.785313 CH1 RK1: MR19=C0C, MR18=80B8
6940 00:22:18.791807 CH1_RK1: MR19=0xC0C, MR18=0x80B8, DQSOSC=386, MR23=63, INC=396, DEC=264
6941 00:22:18.795078 [RxdqsGatingPostProcess] freq 400
6942 00:22:18.801532 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6943 00:22:18.805141 best DQS0 dly(2T, 0.5T) = (0, 10)
6944 00:22:18.808220 best DQS1 dly(2T, 0.5T) = (0, 10)
6945 00:22:18.812031 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6946 00:22:18.814909 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6947 00:22:18.818487 best DQS0 dly(2T, 0.5T) = (0, 10)
6948 00:22:18.821373 best DQS1 dly(2T, 0.5T) = (0, 10)
6949 00:22:18.824733 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6950 00:22:18.828445 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6951 00:22:18.828527 Pre-setting of DQS Precalculation
6952 00:22:18.834662 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6953 00:22:18.841416 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6954 00:22:18.847857 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6955 00:22:18.847945
6956 00:22:18.848050
6957 00:22:18.851428 [Calibration Summary] 800 Mbps
6958 00:22:18.854322 CH 0, Rank 0
6959 00:22:18.854403 SW Impedance : PASS
6960 00:22:18.857927 DUTY Scan : NO K
6961 00:22:18.861136 ZQ Calibration : PASS
6962 00:22:18.861217 Jitter Meter : NO K
6963 00:22:18.864483 CBT Training : PASS
6964 00:22:18.867734 Write leveling : PASS
6965 00:22:18.867839 RX DQS gating : PASS
6966 00:22:18.870761 RX DQ/DQS(RDDQC) : PASS
6967 00:22:18.874296 TX DQ/DQS : PASS
6968 00:22:18.874369 RX DATLAT : PASS
6969 00:22:18.877439 RX DQ/DQS(Engine): PASS
6970 00:22:18.880944 TX OE : NO K
6971 00:22:18.881043 All Pass.
6972 00:22:18.881131
6973 00:22:18.881215 CH 0, Rank 1
6974 00:22:18.884186 SW Impedance : PASS
6975 00:22:18.887666 DUTY Scan : NO K
6976 00:22:18.887739 ZQ Calibration : PASS
6977 00:22:18.890500 Jitter Meter : NO K
6978 00:22:18.890569 CBT Training : PASS
6979 00:22:18.894124 Write leveling : NO K
6980 00:22:18.897283 RX DQS gating : PASS
6981 00:22:18.897364 RX DQ/DQS(RDDQC) : PASS
6982 00:22:18.900718 TX DQ/DQS : PASS
6983 00:22:18.903963 RX DATLAT : PASS
6984 00:22:18.904043 RX DQ/DQS(Engine): PASS
6985 00:22:18.907321 TX OE : NO K
6986 00:22:18.907645 All Pass.
6987 00:22:18.907896
6988 00:22:18.910618 CH 1, Rank 0
6989 00:22:18.910941 SW Impedance : PASS
6990 00:22:18.914442 DUTY Scan : NO K
6991 00:22:18.917425 ZQ Calibration : PASS
6992 00:22:18.917758 Jitter Meter : NO K
6993 00:22:18.921046 CBT Training : PASS
6994 00:22:18.923796 Write leveling : PASS
6995 00:22:18.924118 RX DQS gating : PASS
6996 00:22:18.927311 RX DQ/DQS(RDDQC) : PASS
6997 00:22:18.930235 TX DQ/DQS : PASS
6998 00:22:18.930566 RX DATLAT : PASS
6999 00:22:18.933693 RX DQ/DQS(Engine): PASS
7000 00:22:18.937340 TX OE : NO K
7001 00:22:18.937676 All Pass.
7002 00:22:18.937935
7003 00:22:18.938183 CH 1, Rank 1
7004 00:22:18.940524 SW Impedance : PASS
7005 00:22:18.943363 DUTY Scan : NO K
7006 00:22:18.943606 ZQ Calibration : PASS
7007 00:22:18.946841 Jitter Meter : NO K
7008 00:22:18.950321 CBT Training : PASS
7009 00:22:18.950518 Write leveling : NO K
7010 00:22:18.953184 RX DQS gating : PASS
7011 00:22:18.956608 RX DQ/DQS(RDDQC) : PASS
7012 00:22:18.956785 TX DQ/DQS : PASS
7013 00:22:18.959943 RX DATLAT : PASS
7014 00:22:18.962977 RX DQ/DQS(Engine): PASS
7015 00:22:18.963112 TX OE : NO K
7016 00:22:18.963238 All Pass.
7017 00:22:18.966576
7018 00:22:18.966703 DramC Write-DBI off
7019 00:22:18.969558 PER_BANK_REFRESH: Hybrid Mode
7020 00:22:18.969720 TX_TRACKING: ON
7021 00:22:18.979214 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7022 00:22:18.982993 [FAST_K] Save calibration result to emmc
7023 00:22:18.986057 dramc_set_vcore_voltage set vcore to 725000
7024 00:22:18.989538 Read voltage for 1600, 0
7025 00:22:18.989677 Vio18 = 0
7026 00:22:18.992794 Vcore = 725000
7027 00:22:18.992933 Vdram = 0
7028 00:22:18.993043 Vddq = 0
7029 00:22:18.996066 Vmddr = 0
7030 00:22:18.999429 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7031 00:22:19.005747 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7032 00:22:19.005907 MEM_TYPE=3, freq_sel=13
7033 00:22:19.009117 sv_algorithm_assistance_LP4_3733
7034 00:22:19.015689 ============ PULL DRAM RESETB DOWN ============
7035 00:22:19.018666 ========== PULL DRAM RESETB DOWN end =========
7036 00:22:19.022114 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7037 00:22:19.025122 ===================================
7038 00:22:19.028762 LPDDR4 DRAM CONFIGURATION
7039 00:22:19.032388 ===================================
7040 00:22:19.035592 EX_ROW_EN[0] = 0x0
7041 00:22:19.035686 EX_ROW_EN[1] = 0x0
7042 00:22:19.038526 LP4Y_EN = 0x0
7043 00:22:19.038649 WORK_FSP = 0x1
7044 00:22:19.042240 WL = 0x5
7045 00:22:19.042339 RL = 0x5
7046 00:22:19.045252 BL = 0x2
7047 00:22:19.045358 RPST = 0x0
7048 00:22:19.048885 RD_PRE = 0x0
7049 00:22:19.048980 WR_PRE = 0x1
7050 00:22:19.052028 WR_PST = 0x1
7051 00:22:19.052125 DBI_WR = 0x0
7052 00:22:19.055450 DBI_RD = 0x0
7053 00:22:19.055547 OTF = 0x1
7054 00:22:19.058317 ===================================
7055 00:22:19.062001 ===================================
7056 00:22:19.065043 ANA top config
7057 00:22:19.068505 ===================================
7058 00:22:19.071594 DLL_ASYNC_EN = 0
7059 00:22:19.071682 ALL_SLAVE_EN = 0
7060 00:22:19.075126 NEW_RANK_MODE = 1
7061 00:22:19.078206 DLL_IDLE_MODE = 1
7062 00:22:19.081769 LP45_APHY_COMB_EN = 1
7063 00:22:19.084705 TX_ODT_DIS = 0
7064 00:22:19.084797 NEW_8X_MODE = 1
7065 00:22:19.088223 ===================================
7066 00:22:19.091270 ===================================
7067 00:22:19.094818 data_rate = 3200
7068 00:22:19.098159 CKR = 1
7069 00:22:19.101426 DQ_P2S_RATIO = 8
7070 00:22:19.104467 ===================================
7071 00:22:19.107956 CA_P2S_RATIO = 8
7072 00:22:19.111569 DQ_CA_OPEN = 0
7073 00:22:19.111658 DQ_SEMI_OPEN = 0
7074 00:22:19.114401 CA_SEMI_OPEN = 0
7075 00:22:19.118022 CA_FULL_RATE = 0
7076 00:22:19.121199 DQ_CKDIV4_EN = 0
7077 00:22:19.124891 CA_CKDIV4_EN = 0
7078 00:22:19.127559 CA_PREDIV_EN = 0
7079 00:22:19.127650 PH8_DLY = 12
7080 00:22:19.131178 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7081 00:22:19.134681 DQ_AAMCK_DIV = 4
7082 00:22:19.137478 CA_AAMCK_DIV = 4
7083 00:22:19.140938 CA_ADMCK_DIV = 4
7084 00:22:19.144489 DQ_TRACK_CA_EN = 0
7085 00:22:19.144579 CA_PICK = 1600
7086 00:22:19.147550 CA_MCKIO = 1600
7087 00:22:19.151001 MCKIO_SEMI = 0
7088 00:22:19.154275 PLL_FREQ = 3068
7089 00:22:19.157756 DQ_UI_PI_RATIO = 32
7090 00:22:19.160623 CA_UI_PI_RATIO = 0
7091 00:22:19.164408 ===================================
7092 00:22:19.167736 ===================================
7093 00:22:19.170605 memory_type:LPDDR4
7094 00:22:19.170689 GP_NUM : 10
7095 00:22:19.174129 SRAM_EN : 1
7096 00:22:19.174223 MD32_EN : 0
7097 00:22:19.177091 ===================================
7098 00:22:19.180849 [ANA_INIT] >>>>>>>>>>>>>>
7099 00:22:19.183862 <<<<<< [CONFIGURE PHASE]: ANA_TX
7100 00:22:19.187414 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7101 00:22:19.190364 ===================================
7102 00:22:19.193414 data_rate = 3200,PCW = 0X7600
7103 00:22:19.196952 ===================================
7104 00:22:19.200180 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7105 00:22:19.207136 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7106 00:22:19.210728 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7107 00:22:19.217077 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7108 00:22:19.220215 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7109 00:22:19.223558 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7110 00:22:19.223923 [ANA_INIT] flow start
7111 00:22:19.227179 [ANA_INIT] PLL >>>>>>>>
7112 00:22:19.230438 [ANA_INIT] PLL <<<<<<<<
7113 00:22:19.230802 [ANA_INIT] MIDPI >>>>>>>>
7114 00:22:19.233555 [ANA_INIT] MIDPI <<<<<<<<
7115 00:22:19.237004 [ANA_INIT] DLL >>>>>>>>
7116 00:22:19.240495 [ANA_INIT] DLL <<<<<<<<
7117 00:22:19.240854 [ANA_INIT] flow end
7118 00:22:19.243404 ============ LP4 DIFF to SE enter ============
7119 00:22:19.250011 ============ LP4 DIFF to SE exit ============
7120 00:22:19.250377 [ANA_INIT] <<<<<<<<<<<<<
7121 00:22:19.253510 [Flow] Enable top DCM control >>>>>
7122 00:22:19.256588 [Flow] Enable top DCM control <<<<<
7123 00:22:19.259591 Enable DLL master slave shuffle
7124 00:22:19.266738 ==============================================================
7125 00:22:19.267087 Gating Mode config
7126 00:22:19.273317 ==============================================================
7127 00:22:19.276133 Config description:
7128 00:22:19.286254 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7129 00:22:19.293352 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7130 00:22:19.296142 SELPH_MODE 0: By rank 1: By Phase
7131 00:22:19.302741 ==============================================================
7132 00:22:19.305737 GAT_TRACK_EN = 1
7133 00:22:19.309111 RX_GATING_MODE = 2
7134 00:22:19.312644 RX_GATING_TRACK_MODE = 2
7135 00:22:19.313003 SELPH_MODE = 1
7136 00:22:19.315696 PICG_EARLY_EN = 1
7137 00:22:19.319148 VALID_LAT_VALUE = 1
7138 00:22:19.325323 ==============================================================
7139 00:22:19.328679 Enter into Gating configuration >>>>
7140 00:22:19.332081 Exit from Gating configuration <<<<
7141 00:22:19.335633 Enter into DVFS_PRE_config >>>>>
7142 00:22:19.345355 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7143 00:22:19.348636 Exit from DVFS_PRE_config <<<<<
7144 00:22:19.351898 Enter into PICG configuration >>>>
7145 00:22:19.354979 Exit from PICG configuration <<<<
7146 00:22:19.358003 [RX_INPUT] configuration >>>>>
7147 00:22:19.361545 [RX_INPUT] configuration <<<<<
7148 00:22:19.368271 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7149 00:22:19.371453 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7150 00:22:19.378451 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7151 00:22:19.385057 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7152 00:22:19.391072 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7153 00:22:19.397951 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7154 00:22:19.401067 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7155 00:22:19.404636 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7156 00:22:19.407907 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7157 00:22:19.414692 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7158 00:22:19.417483 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7159 00:22:19.420835 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7160 00:22:19.424491 ===================================
7161 00:22:19.427396 LPDDR4 DRAM CONFIGURATION
7162 00:22:19.430757 ===================================
7163 00:22:19.434084 EX_ROW_EN[0] = 0x0
7164 00:22:19.434440 EX_ROW_EN[1] = 0x0
7165 00:22:19.437099 LP4Y_EN = 0x0
7166 00:22:19.437501 WORK_FSP = 0x1
7167 00:22:19.440815 WL = 0x5
7168 00:22:19.441168 RL = 0x5
7169 00:22:19.444139 BL = 0x2
7170 00:22:19.444489 RPST = 0x0
7171 00:22:19.447386 RD_PRE = 0x0
7172 00:22:19.447738 WR_PRE = 0x1
7173 00:22:19.450590 WR_PST = 0x1
7174 00:22:19.451086 DBI_WR = 0x0
7175 00:22:19.453820 DBI_RD = 0x0
7176 00:22:19.454172 OTF = 0x1
7177 00:22:19.457045 ===================================
7178 00:22:19.464203 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7179 00:22:19.466861 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7180 00:22:19.470503 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7181 00:22:19.473407 ===================================
7182 00:22:19.477162 LPDDR4 DRAM CONFIGURATION
7183 00:22:19.479917 ===================================
7184 00:22:19.483730 EX_ROW_EN[0] = 0x10
7185 00:22:19.484241 EX_ROW_EN[1] = 0x0
7186 00:22:19.486525 LP4Y_EN = 0x0
7187 00:22:19.486991 WORK_FSP = 0x1
7188 00:22:19.489871 WL = 0x5
7189 00:22:19.490300 RL = 0x5
7190 00:22:19.493039 BL = 0x2
7191 00:22:19.493462 RPST = 0x0
7192 00:22:19.496468 RD_PRE = 0x0
7193 00:22:19.497105 WR_PRE = 0x1
7194 00:22:19.499911 WR_PST = 0x1
7195 00:22:19.500352 DBI_WR = 0x0
7196 00:22:19.502917 DBI_RD = 0x0
7197 00:22:19.506114 OTF = 0x1
7198 00:22:19.509989 ===================================
7199 00:22:19.512792 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7200 00:22:19.513138 ==
7201 00:22:19.516383 Dram Type= 6, Freq= 0, CH_0, rank 0
7202 00:22:19.522662 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7203 00:22:19.523009 ==
7204 00:22:19.526036 [Duty_Offset_Calibration]
7205 00:22:19.526382 B0:2 B1:0 CA:4
7206 00:22:19.526650
7207 00:22:19.529220 [DutyScan_Calibration_Flow] k_type=0
7208 00:22:19.538245
7209 00:22:19.538587 ==CLK 0==
7210 00:22:19.541401 Final CLK duty delay cell = -4
7211 00:22:19.545007 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7212 00:22:19.548488 [-4] MIN Duty = 4813%(X100), DQS PI = 8
7213 00:22:19.551350 [-4] AVG Duty = 4922%(X100)
7214 00:22:19.551738
7215 00:22:19.554835 CH0 CLK Duty spec in!! Max-Min= 218%
7216 00:22:19.558252 [DutyScan_Calibration_Flow] ====Done====
7217 00:22:19.558598
7218 00:22:19.561534 [DutyScan_Calibration_Flow] k_type=1
7219 00:22:19.578283
7220 00:22:19.578395 ==DQS 0 ==
7221 00:22:19.581710 Final DQS duty delay cell = 0
7222 00:22:19.584676 [0] MAX Duty = 5218%(X100), DQS PI = 38
7223 00:22:19.588166 [0] MIN Duty = 5093%(X100), DQS PI = 6
7224 00:22:19.591310 [0] AVG Duty = 5155%(X100)
7225 00:22:19.591417
7226 00:22:19.591508 ==DQS 1 ==
7227 00:22:19.594894 Final DQS duty delay cell = 0
7228 00:22:19.598146 [0] MAX Duty = 5125%(X100), DQS PI = 4
7229 00:22:19.601964 [0] MIN Duty = 4969%(X100), DQS PI = 8
7230 00:22:19.604732 [0] AVG Duty = 5047%(X100)
7231 00:22:19.604817
7232 00:22:19.607973 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7233 00:22:19.608073
7234 00:22:19.611344 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7235 00:22:19.614867 [DutyScan_Calibration_Flow] ====Done====
7236 00:22:19.614949
7237 00:22:19.618096 [DutyScan_Calibration_Flow] k_type=3
7238 00:22:19.635545
7239 00:22:19.635628 ==DQM 0 ==
7240 00:22:19.638387 Final DQM duty delay cell = 0
7241 00:22:19.642130 [0] MAX Duty = 5124%(X100), DQS PI = 22
7242 00:22:19.645006 [0] MIN Duty = 4875%(X100), DQS PI = 54
7243 00:22:19.648386 [0] AVG Duty = 4999%(X100)
7244 00:22:19.648474
7245 00:22:19.648564 ==DQM 1 ==
7246 00:22:19.652038 Final DQM duty delay cell = 0
7247 00:22:19.654837 [0] MAX Duty = 4969%(X100), DQS PI = 0
7248 00:22:19.658372 [0] MIN Duty = 4844%(X100), DQS PI = 14
7249 00:22:19.661902 [0] AVG Duty = 4906%(X100)
7250 00:22:19.662013
7251 00:22:19.664708 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7252 00:22:19.664819
7253 00:22:19.668421 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7254 00:22:19.671567 [DutyScan_Calibration_Flow] ====Done====
7255 00:22:19.671650
7256 00:22:19.675129 [DutyScan_Calibration_Flow] k_type=2
7257 00:22:19.692740
7258 00:22:19.693097 ==DQ 0 ==
7259 00:22:19.696325 Final DQ duty delay cell = 0
7260 00:22:19.699471 [0] MAX Duty = 5124%(X100), DQS PI = 20
7261 00:22:19.702772 [0] MIN Duty = 4938%(X100), DQS PI = 10
7262 00:22:19.706128 [0] AVG Duty = 5031%(X100)
7263 00:22:19.706516
7264 00:22:19.706910 ==DQ 1 ==
7265 00:22:19.709197 Final DQ duty delay cell = 0
7266 00:22:19.712211 [0] MAX Duty = 5187%(X100), DQS PI = 2
7267 00:22:19.715926 [0] MIN Duty = 4907%(X100), DQS PI = 32
7268 00:22:19.716318 [0] AVG Duty = 5047%(X100)
7269 00:22:19.719234
7270 00:22:19.722081 CH0 DQ 0 Duty spec in!! Max-Min= 186%
7271 00:22:19.722587
7272 00:22:19.732865 CH0 DQ 1 Duty spec in!! Max-Min= 280%
7273 00:22:19.733421 [DutyScan_Calibration_Flow] ====Done====
7274 00:22:19.733890 ==
7275 00:22:19.734323 Dram Type= 6, Freq= 0, CH_1, rank 0
7276 00:22:19.735164 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7277 00:22:19.735607 ==
7278 00:22:19.738558 [Duty_Offset_Calibration]
7279 00:22:19.739147 B0:0 B1:-1 CA:3
7280 00:22:19.739651
7281 00:22:19.742043 [DutyScan_Calibration_Flow] k_type=0
7282 00:22:19.752962
7283 00:22:19.753396 ==CLK 0==
7284 00:22:19.756574 Final CLK duty delay cell = 0
7285 00:22:19.759830 [0] MAX Duty = 5187%(X100), DQS PI = 4
7286 00:22:19.762688 [0] MIN Duty = 5000%(X100), DQS PI = 54
7287 00:22:19.766336 [0] AVG Duty = 5093%(X100)
7288 00:22:19.766712
7289 00:22:19.769093 CH1 CLK Duty spec in!! Max-Min= 187%
7290 00:22:19.772446 [DutyScan_Calibration_Flow] ====Done====
7291 00:22:19.772823
7292 00:22:19.776079 [DutyScan_Calibration_Flow] k_type=1
7293 00:22:19.791680
7294 00:22:19.792050 ==DQS 0 ==
7295 00:22:19.795128 Final DQS duty delay cell = 0
7296 00:22:19.798710 [0] MAX Duty = 5250%(X100), DQS PI = 30
7297 00:22:19.801769 [0] MIN Duty = 4907%(X100), DQS PI = 56
7298 00:22:19.805205 [0] AVG Duty = 5078%(X100)
7299 00:22:19.805615
7300 00:22:19.805926 ==DQS 1 ==
7301 00:22:19.808028 Final DQS duty delay cell = -4
7302 00:22:19.811575 [-4] MAX Duty = 5000%(X100), DQS PI = 30
7303 00:22:19.814631 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7304 00:22:19.818550 [-4] AVG Duty = 4922%(X100)
7305 00:22:19.818929
7306 00:22:19.821656 CH1 DQS 0 Duty spec in!! Max-Min= 343%
7307 00:22:19.822032
7308 00:22:19.824981 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7309 00:22:19.828163 [DutyScan_Calibration_Flow] ====Done====
7310 00:22:19.828538
7311 00:22:19.831262 [DutyScan_Calibration_Flow] k_type=3
7312 00:22:19.849368
7313 00:22:19.849749 ==DQM 0 ==
7314 00:22:19.852473 Final DQM duty delay cell = 0
7315 00:22:19.855996 [0] MAX Duty = 5062%(X100), DQS PI = 32
7316 00:22:19.859150 [0] MIN Duty = 4782%(X100), DQS PI = 40
7317 00:22:19.862487 [0] AVG Duty = 4922%(X100)
7318 00:22:19.862866
7319 00:22:19.863160 ==DQM 1 ==
7320 00:22:19.865675 Final DQM duty delay cell = 0
7321 00:22:19.868964 [0] MAX Duty = 4969%(X100), DQS PI = 30
7322 00:22:19.872035 [0] MIN Duty = 4844%(X100), DQS PI = 0
7323 00:22:19.875799 [0] AVG Duty = 4906%(X100)
7324 00:22:19.876175
7325 00:22:19.878537 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7326 00:22:19.878617
7327 00:22:19.881633 CH1 DQM 1 Duty spec in!! Max-Min= 125%
7328 00:22:19.885088 [DutyScan_Calibration_Flow] ====Done====
7329 00:22:19.885167
7330 00:22:19.888839 [DutyScan_Calibration_Flow] k_type=2
7331 00:22:19.904820
7332 00:22:19.904906 ==DQ 0 ==
7333 00:22:19.908388 Final DQ duty delay cell = -4
7334 00:22:19.911940 [-4] MAX Duty = 4969%(X100), DQS PI = 32
7335 00:22:19.914926 [-4] MIN Duty = 4813%(X100), DQS PI = 38
7336 00:22:19.918025 [-4] AVG Duty = 4891%(X100)
7337 00:22:19.918136
7338 00:22:19.918220 ==DQ 1 ==
7339 00:22:19.921671 Final DQ duty delay cell = 0
7340 00:22:19.924747 [0] MAX Duty = 5031%(X100), DQS PI = 30
7341 00:22:19.928197 [0] MIN Duty = 4844%(X100), DQS PI = 58
7342 00:22:19.931437 [0] AVG Duty = 4937%(X100)
7343 00:22:19.931517
7344 00:22:19.934603 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7345 00:22:19.934702
7346 00:22:19.938216 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7347 00:22:19.941214 [DutyScan_Calibration_Flow] ====Done====
7348 00:22:19.944470 nWR fixed to 30
7349 00:22:19.948055 [ModeRegInit_LP4] CH0 RK0
7350 00:22:19.948140 [ModeRegInit_LP4] CH0 RK1
7351 00:22:19.951191 [ModeRegInit_LP4] CH1 RK0
7352 00:22:19.954546 [ModeRegInit_LP4] CH1 RK1
7353 00:22:19.954934 match AC timing 5
7354 00:22:19.961698 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7355 00:22:19.964985 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7356 00:22:19.967932 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7357 00:22:19.974526 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7358 00:22:19.978027 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7359 00:22:19.978377 [MiockJmeterHQA]
7360 00:22:19.980739
7361 00:22:19.981067 [DramcMiockJmeter] u1RxGatingPI = 0
7362 00:22:19.984061 0 : 4252, 4027
7363 00:22:19.984434 4 : 4363, 4138
7364 00:22:19.987561 8 : 4252, 4027
7365 00:22:19.987995 12 : 4363, 4137
7366 00:22:19.990711 16 : 4253, 4026
7367 00:22:19.991091 20 : 4252, 4027
7368 00:22:19.994366 24 : 4252, 4027
7369 00:22:19.994782 28 : 4255, 4029
7370 00:22:19.995085 32 : 4363, 4138
7371 00:22:19.997625 36 : 4253, 4026
7372 00:22:19.998013 40 : 4252, 4027
7373 00:22:20.000688 44 : 4250, 4027
7374 00:22:20.001072 48 : 4255, 4029
7375 00:22:20.004070 52 : 4363, 4140
7376 00:22:20.004455 56 : 4360, 4137
7377 00:22:20.007384 60 : 4363, 4140
7378 00:22:20.007793 64 : 4250, 4027
7379 00:22:20.008112 68 : 4250, 4026
7380 00:22:20.010811 72 : 4250, 4027
7381 00:22:20.011200 76 : 4250, 4027
7382 00:22:20.013923 80 : 4253, 4029
7383 00:22:20.014309 84 : 4360, 4137
7384 00:22:20.017105 88 : 4250, 4026
7385 00:22:20.017673 92 : 4250, 4027
7386 00:22:20.020594 96 : 4250, 2847
7387 00:22:20.020981 100 : 4252, 0
7388 00:22:20.021323 104 : 4250, 0
7389 00:22:20.023683 108 : 4249, 0
7390 00:22:20.024066 112 : 4252, 0
7391 00:22:20.027160 116 : 4360, 0
7392 00:22:20.027518 120 : 4361, 0
7393 00:22:20.027800 124 : 4362, 0
7394 00:22:20.030284 128 : 4250, 0
7395 00:22:20.030642 132 : 4250, 0
7396 00:22:20.033194 136 : 4250, 0
7397 00:22:20.033602 140 : 4250, 0
7398 00:22:20.033886 144 : 4250, 0
7399 00:22:20.036694 148 : 4250, 0
7400 00:22:20.037069 152 : 4253, 0
7401 00:22:20.037391 156 : 4250, 0
7402 00:22:20.040278 160 : 4250, 0
7403 00:22:20.040740 164 : 4253, 0
7404 00:22:20.043584 168 : 4360, 0
7405 00:22:20.043944 172 : 4361, 0
7406 00:22:20.044227 176 : 4363, 0
7407 00:22:20.046831 180 : 4250, 0
7408 00:22:20.047189 184 : 4250, 0
7409 00:22:20.049821 188 : 4250, 0
7410 00:22:20.050185 192 : 4250, 0
7411 00:22:20.050467 196 : 4250, 0
7412 00:22:20.053305 200 : 4249, 0
7413 00:22:20.053664 204 : 4253, 0
7414 00:22:20.056308 208 : 4250, 0
7415 00:22:20.056665 212 : 4360, 0
7416 00:22:20.056944 216 : 4250, 0
7417 00:22:20.059962 220 : 4360, 662
7418 00:22:20.060319 224 : 4361, 4106
7419 00:22:20.063022 228 : 4250, 4027
7420 00:22:20.063103 232 : 4249, 4027
7421 00:22:20.066154 236 : 4250, 4026
7422 00:22:20.066236 240 : 4252, 4029
7423 00:22:20.069779 244 : 4250, 4026
7424 00:22:20.069861 248 : 4250, 4027
7425 00:22:20.072942 252 : 4360, 4137
7426 00:22:20.073029 256 : 4250, 4027
7427 00:22:20.076102 260 : 4250, 4026
7428 00:22:20.076189 264 : 4361, 4138
7429 00:22:20.076258 268 : 4250, 4027
7430 00:22:20.079465 272 : 4250, 4026
7431 00:22:20.079559 276 : 4363, 4140
7432 00:22:20.082734 280 : 4250, 4027
7433 00:22:20.082828 284 : 4250, 4027
7434 00:22:20.086313 288 : 4250, 4026
7435 00:22:20.086414 292 : 4253, 4029
7436 00:22:20.089132 296 : 4250, 4026
7437 00:22:20.089240 300 : 4252, 4029
7438 00:22:20.092489 304 : 4360, 4137
7439 00:22:20.092598 308 : 4249, 4027
7440 00:22:20.095853 312 : 4250, 4027
7441 00:22:20.096051 316 : 4361, 4138
7442 00:22:20.099578 320 : 4250, 4027
7443 00:22:20.099716 324 : 4250, 4026
7444 00:22:20.102529 328 : 4363, 4140
7445 00:22:20.102675 332 : 4250, 3935
7446 00:22:20.102784 336 : 4250, 1358
7447 00:22:20.102898
7448 00:22:20.105508 MIOCK jitter meter ch=0
7449 00:22:20.105736
7450 00:22:20.109187 1T = (336-100) = 236 dly cells
7451 00:22:20.115893 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7452 00:22:20.116093 ==
7453 00:22:20.119215 Dram Type= 6, Freq= 0, CH_0, rank 0
7454 00:22:20.122579 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7455 00:22:20.122834 ==
7456 00:22:20.129632 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7457 00:22:20.132593 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7458 00:22:20.136190 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7459 00:22:20.142590 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7460 00:22:20.152386 [CA 0] Center 43 (13~74) winsize 62
7461 00:22:20.155085 [CA 1] Center 42 (12~73) winsize 62
7462 00:22:20.158477 [CA 2] Center 37 (8~67) winsize 60
7463 00:22:20.161481 [CA 3] Center 37 (8~67) winsize 60
7464 00:22:20.165124 [CA 4] Center 36 (6~66) winsize 61
7465 00:22:20.168222 [CA 5] Center 35 (5~66) winsize 62
7466 00:22:20.168602
7467 00:22:20.171655 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7468 00:22:20.172009
7469 00:22:20.178556 [CATrainingPosCal] consider 1 rank data
7470 00:22:20.179029 u2DelayCellTimex100 = 275/100 ps
7471 00:22:20.184877 CA0 delay=43 (13~74),Diff = 8 PI (28 cell)
7472 00:22:20.188139 CA1 delay=42 (12~73),Diff = 7 PI (24 cell)
7473 00:22:20.191587 CA2 delay=37 (8~67),Diff = 2 PI (7 cell)
7474 00:22:20.194328 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7475 00:22:20.198010 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7476 00:22:20.200925 CA5 delay=35 (5~66),Diff = 0 PI (0 cell)
7477 00:22:20.201385
7478 00:22:20.204286 CA PerBit enable=1, Macro0, CA PI delay=35
7479 00:22:20.204700
7480 00:22:20.207725 [CBTSetCACLKResult] CA Dly = 35
7481 00:22:20.210780 CS Dly: 11 (0~42)
7482 00:22:20.214452 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7483 00:22:20.217617 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7484 00:22:20.218151 ==
7485 00:22:20.220866 Dram Type= 6, Freq= 0, CH_0, rank 1
7486 00:22:20.227127 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7487 00:22:20.227521 ==
7488 00:22:20.230418 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7489 00:22:20.237345 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7490 00:22:20.240426 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7491 00:22:20.247153 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7492 00:22:20.255541 [CA 0] Center 43 (13~74) winsize 62
7493 00:22:20.258484 [CA 1] Center 43 (13~74) winsize 62
7494 00:22:20.261690 [CA 2] Center 38 (9~68) winsize 60
7495 00:22:20.264863 [CA 3] Center 38 (9~68) winsize 60
7496 00:22:20.268480 [CA 4] Center 36 (6~67) winsize 62
7497 00:22:20.271844 [CA 5] Center 36 (6~66) winsize 61
7498 00:22:20.272176
7499 00:22:20.274821 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7500 00:22:20.275216
7501 00:22:20.278558 [CATrainingPosCal] consider 2 rank data
7502 00:22:20.281530 u2DelayCellTimex100 = 275/100 ps
7503 00:22:20.288196 CA0 delay=43 (13~74),Diff = 7 PI (24 cell)
7504 00:22:20.291289 CA1 delay=43 (13~73),Diff = 7 PI (24 cell)
7505 00:22:20.294585 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
7506 00:22:20.297925 CA3 delay=38 (9~67),Diff = 2 PI (7 cell)
7507 00:22:20.301051 CA4 delay=36 (6~66),Diff = 0 PI (0 cell)
7508 00:22:20.304723 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7509 00:22:20.305225
7510 00:22:20.307930 CA PerBit enable=1, Macro0, CA PI delay=36
7511 00:22:20.308303
7512 00:22:20.311066 [CBTSetCACLKResult] CA Dly = 36
7513 00:22:20.314547 CS Dly: 12 (0~44)
7514 00:22:20.317940 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7515 00:22:20.321380 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7516 00:22:20.321757
7517 00:22:20.324621 ----->DramcWriteLeveling(PI) begin...
7518 00:22:20.325006 ==
7519 00:22:20.327824 Dram Type= 6, Freq= 0, CH_0, rank 0
7520 00:22:20.334408 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7521 00:22:20.334783 ==
7522 00:22:20.337368 Write leveling (Byte 0): 34 => 34
7523 00:22:20.340551 Write leveling (Byte 1): 27 => 27
7524 00:22:20.344344 DramcWriteLeveling(PI) end<-----
7525 00:22:20.344720
7526 00:22:20.345017 ==
7527 00:22:20.347193 Dram Type= 6, Freq= 0, CH_0, rank 0
7528 00:22:20.350777 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7529 00:22:20.351154 ==
7530 00:22:20.353923 [Gating] SW mode calibration
7531 00:22:20.360435 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7532 00:22:20.366989 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7533 00:22:20.370252 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7534 00:22:20.374041 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7535 00:22:20.377142 1 4 8 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
7536 00:22:20.383915 1 4 12 | B1->B0 | 2323 2f2e | 0 1 | (0 0) (0 0)
7537 00:22:20.386849 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7538 00:22:20.393523 1 4 20 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
7539 00:22:20.397024 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7540 00:22:20.399997 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7541 00:22:20.406790 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7542 00:22:20.409866 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7543 00:22:20.413123 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
7544 00:22:20.419729 1 5 12 | B1->B0 | 3434 2929 | 1 0 | (1 1) (0 1)
7545 00:22:20.423189 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7546 00:22:20.426656 1 5 20 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (0 0)
7547 00:22:20.429726 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7548 00:22:20.436880 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7549 00:22:20.439923 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7550 00:22:20.443271 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7551 00:22:20.449817 1 6 8 | B1->B0 | 2323 3231 | 0 1 | (0 0) (0 0)
7552 00:22:20.453090 1 6 12 | B1->B0 | 2323 3f3f | 0 0 | (0 0) (0 0)
7553 00:22:20.456475 1 6 16 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
7554 00:22:20.462718 1 6 20 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
7555 00:22:20.466487 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7556 00:22:20.469202 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7557 00:22:20.476277 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7558 00:22:20.479675 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7559 00:22:20.482656 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7560 00:22:20.489779 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7561 00:22:20.492279 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7562 00:22:20.495895 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7563 00:22:20.502679 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7564 00:22:20.505611 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7565 00:22:20.512095 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7566 00:22:20.515341 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7567 00:22:20.518966 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7568 00:22:20.525424 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7569 00:22:20.528494 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7570 00:22:20.531669 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7571 00:22:20.535496 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7572 00:22:20.541865 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7573 00:22:20.545544 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7574 00:22:20.548540 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7575 00:22:20.554951 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7576 00:22:20.558448 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7577 00:22:20.561775 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7578 00:22:20.565208 Total UI for P1: 0, mck2ui 16
7579 00:22:20.568284 best dqsien dly found for B0: ( 1, 9, 10)
7580 00:22:20.574832 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7581 00:22:20.577968 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7582 00:22:20.581439 Total UI for P1: 0, mck2ui 16
7583 00:22:20.584470 best dqsien dly found for B1: ( 1, 9, 18)
7584 00:22:20.587867 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7585 00:22:20.591399 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7586 00:22:20.591814
7587 00:22:20.594639 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7588 00:22:20.601303 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7589 00:22:20.601909 [Gating] SW calibration Done
7590 00:22:20.604584 ==
7591 00:22:20.605146 Dram Type= 6, Freq= 0, CH_0, rank 0
7592 00:22:20.611393 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7593 00:22:20.611838 ==
7594 00:22:20.612408 RX Vref Scan: 0
7595 00:22:20.612745
7596 00:22:20.614402 RX Vref 0 -> 0, step: 1
7597 00:22:20.614817
7598 00:22:20.617797 RX Delay 0 -> 252, step: 8
7599 00:22:20.621166 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
7600 00:22:20.624218 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7601 00:22:20.627390 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7602 00:22:20.634208 iDelay=192, Bit 3, Center 127 (72 ~ 183) 112
7603 00:22:20.637777 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7604 00:22:20.640837 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7605 00:22:20.644304 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7606 00:22:20.647427 iDelay=192, Bit 7, Center 135 (80 ~ 191) 112
7607 00:22:20.654001 iDelay=192, Bit 8, Center 115 (64 ~ 167) 104
7608 00:22:20.657478 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7609 00:22:20.660983 iDelay=192, Bit 10, Center 123 (72 ~ 175) 104
7610 00:22:20.663730 iDelay=192, Bit 11, Center 119 (64 ~ 175) 112
7611 00:22:20.667619 iDelay=192, Bit 12, Center 131 (72 ~ 191) 120
7612 00:22:20.673610 iDelay=192, Bit 13, Center 131 (80 ~ 183) 104
7613 00:22:20.677313 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7614 00:22:20.680819 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7615 00:22:20.681407 ==
7616 00:22:20.683714 Dram Type= 6, Freq= 0, CH_0, rank 0
7617 00:22:20.687232 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7618 00:22:20.690337 ==
7619 00:22:20.690872 DQS Delay:
7620 00:22:20.691382 DQS0 = 0, DQS1 = 0
7621 00:22:20.693895 DQM Delay:
7622 00:22:20.694439 DQM0 = 131, DQM1 = 125
7623 00:22:20.697025 DQ Delay:
7624 00:22:20.700328 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7625 00:22:20.703607 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =135
7626 00:22:20.706921 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =119
7627 00:22:20.710150 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7628 00:22:20.710665
7629 00:22:20.711144
7630 00:22:20.711643 ==
7631 00:22:20.713833 Dram Type= 6, Freq= 0, CH_0, rank 0
7632 00:22:20.716726 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7633 00:22:20.719773 ==
7634 00:22:20.720233
7635 00:22:20.720754
7636 00:22:20.721240 TX Vref Scan disable
7637 00:22:20.723227 == TX Byte 0 ==
7638 00:22:20.726683 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7639 00:22:20.730140 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7640 00:22:20.733142 == TX Byte 1 ==
7641 00:22:20.736488 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7642 00:22:20.739904 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7643 00:22:20.743434 ==
7644 00:22:20.746208 Dram Type= 6, Freq= 0, CH_0, rank 0
7645 00:22:20.749163 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7646 00:22:20.749697 ==
7647 00:22:20.763316
7648 00:22:20.766666 TX Vref early break, caculate TX vref
7649 00:22:20.770435 TX Vref=16, minBit 1, minWin=22, winSum=370
7650 00:22:20.773597 TX Vref=18, minBit 1, minWin=23, winSum=383
7651 00:22:20.776555 TX Vref=20, minBit 1, minWin=24, winSum=394
7652 00:22:20.779891 TX Vref=22, minBit 8, minWin=24, winSum=402
7653 00:22:20.783618 TX Vref=24, minBit 1, minWin=23, winSum=406
7654 00:22:20.790141 TX Vref=26, minBit 0, minWin=25, winSum=415
7655 00:22:20.792976 TX Vref=28, minBit 1, minWin=25, winSum=418
7656 00:22:20.796810 TX Vref=30, minBit 0, minWin=25, winSum=418
7657 00:22:20.799535 TX Vref=32, minBit 0, minWin=25, winSum=413
7658 00:22:20.802870 TX Vref=34, minBit 0, minWin=24, winSum=400
7659 00:22:20.810121 TX Vref=36, minBit 2, minWin=23, winSum=388
7660 00:22:20.813393 [TxChooseVref] Worse bit 1, Min win 25, Win sum 418, Final Vref 28
7661 00:22:20.813820
7662 00:22:20.816295 Final TX Range 0 Vref 28
7663 00:22:20.816702
7664 00:22:20.817057 ==
7665 00:22:20.819686 Dram Type= 6, Freq= 0, CH_0, rank 0
7666 00:22:20.822747 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7667 00:22:20.823225 ==
7668 00:22:20.826404
7669 00:22:20.826780
7670 00:22:20.827082 TX Vref Scan disable
7671 00:22:20.833001 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7672 00:22:20.833491 == TX Byte 0 ==
7673 00:22:20.835923 u2DelayCellOfst[0]=10 cells (3 PI)
7674 00:22:20.839484 u2DelayCellOfst[1]=14 cells (4 PI)
7675 00:22:20.842698 u2DelayCellOfst[2]=7 cells (2 PI)
7676 00:22:20.846108 u2DelayCellOfst[3]=7 cells (2 PI)
7677 00:22:20.849555 u2DelayCellOfst[4]=7 cells (2 PI)
7678 00:22:20.853040 u2DelayCellOfst[5]=0 cells (0 PI)
7679 00:22:20.855668 u2DelayCellOfst[6]=14 cells (4 PI)
7680 00:22:20.858973 u2DelayCellOfst[7]=14 cells (4 PI)
7681 00:22:20.862328 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7682 00:22:20.865902 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7683 00:22:20.869093 == TX Byte 1 ==
7684 00:22:20.872576 u2DelayCellOfst[8]=0 cells (0 PI)
7685 00:22:20.875531 u2DelayCellOfst[9]=0 cells (0 PI)
7686 00:22:20.879207 u2DelayCellOfst[10]=7 cells (2 PI)
7687 00:22:20.882152 u2DelayCellOfst[11]=0 cells (0 PI)
7688 00:22:20.882579 u2DelayCellOfst[12]=7 cells (2 PI)
7689 00:22:20.885604 u2DelayCellOfst[13]=10 cells (3 PI)
7690 00:22:20.888870 u2DelayCellOfst[14]=14 cells (4 PI)
7691 00:22:20.892086 u2DelayCellOfst[15]=10 cells (3 PI)
7692 00:22:20.898658 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7693 00:22:20.902166 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7694 00:22:20.902600 DramC Write-DBI on
7695 00:22:20.905067 ==
7696 00:22:20.909011 Dram Type= 6, Freq= 0, CH_0, rank 0
7697 00:22:20.911865 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7698 00:22:20.912328 ==
7699 00:22:20.912729
7700 00:22:20.913433
7701 00:22:20.915419 TX Vref Scan disable
7702 00:22:20.915986 == TX Byte 0 ==
7703 00:22:20.922384 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
7704 00:22:20.922797 == TX Byte 1 ==
7705 00:22:20.924977 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7706 00:22:20.928440 DramC Write-DBI off
7707 00:22:20.928850
7708 00:22:20.929170 [DATLAT]
7709 00:22:20.932014 Freq=1600, CH0 RK0
7710 00:22:20.932431
7711 00:22:20.932756 DATLAT Default: 0xf
7712 00:22:20.934911 0, 0xFFFF, sum = 0
7713 00:22:20.935330 1, 0xFFFF, sum = 0
7714 00:22:20.938465 2, 0xFFFF, sum = 0
7715 00:22:20.938897 3, 0xFFFF, sum = 0
7716 00:22:20.941650 4, 0xFFFF, sum = 0
7717 00:22:20.945206 5, 0xFFFF, sum = 0
7718 00:22:20.945731 6, 0xFFFF, sum = 0
7719 00:22:20.948088 7, 0xFFFF, sum = 0
7720 00:22:20.948515 8, 0xFFFF, sum = 0
7721 00:22:20.951846 9, 0xFFFF, sum = 0
7722 00:22:20.952281 10, 0xFFFF, sum = 0
7723 00:22:20.954824 11, 0xFFFF, sum = 0
7724 00:22:20.955241 12, 0xFFFF, sum = 0
7725 00:22:20.958302 13, 0xFFFF, sum = 0
7726 00:22:20.958726 14, 0x0, sum = 1
7727 00:22:20.961834 15, 0x0, sum = 2
7728 00:22:20.962281 16, 0x0, sum = 3
7729 00:22:20.964803 17, 0x0, sum = 4
7730 00:22:20.965223 best_step = 15
7731 00:22:20.965595
7732 00:22:20.965901 ==
7733 00:22:20.968014 Dram Type= 6, Freq= 0, CH_0, rank 0
7734 00:22:20.971612 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7735 00:22:20.974968 ==
7736 00:22:20.975380 RX Vref Scan: 1
7737 00:22:20.975705
7738 00:22:20.978098 Set Vref Range= 24 -> 127
7739 00:22:20.978511
7740 00:22:20.981284 RX Vref 24 -> 127, step: 1
7741 00:22:20.981708
7742 00:22:20.982033 RX Delay 11 -> 252, step: 4
7743 00:22:20.982357
7744 00:22:20.984578 Set Vref, RX VrefLevel [Byte0]: 24
7745 00:22:20.987716 [Byte1]: 24
7746 00:22:20.991710
7747 00:22:20.992115 Set Vref, RX VrefLevel [Byte0]: 25
7748 00:22:20.995123 [Byte1]: 25
7749 00:22:20.999402
7750 00:22:20.999807 Set Vref, RX VrefLevel [Byte0]: 26
7751 00:22:21.003029 [Byte1]: 26
7752 00:22:21.007115
7753 00:22:21.007522 Set Vref, RX VrefLevel [Byte0]: 27
7754 00:22:21.010586 [Byte1]: 27
7755 00:22:21.014740
7756 00:22:21.015156 Set Vref, RX VrefLevel [Byte0]: 28
7757 00:22:21.018186 [Byte1]: 28
7758 00:22:21.022113
7759 00:22:21.022521 Set Vref, RX VrefLevel [Byte0]: 29
7760 00:22:21.025553 [Byte1]: 29
7761 00:22:21.030591
7762 00:22:21.030998 Set Vref, RX VrefLevel [Byte0]: 30
7763 00:22:21.033343 [Byte1]: 30
7764 00:22:21.037392
7765 00:22:21.037812 Set Vref, RX VrefLevel [Byte0]: 31
7766 00:22:21.041034 [Byte1]: 31
7767 00:22:21.045346
7768 00:22:21.045767 Set Vref, RX VrefLevel [Byte0]: 32
7769 00:22:21.048168 [Byte1]: 32
7770 00:22:21.052969
7771 00:22:21.053437 Set Vref, RX VrefLevel [Byte0]: 33
7772 00:22:21.056141 [Byte1]: 33
7773 00:22:21.060550
7774 00:22:21.060962 Set Vref, RX VrefLevel [Byte0]: 34
7775 00:22:21.063456 [Byte1]: 34
7776 00:22:21.067497
7777 00:22:21.067577 Set Vref, RX VrefLevel [Byte0]: 35
7778 00:22:21.071230 [Byte1]: 35
7779 00:22:21.075616
7780 00:22:21.075696 Set Vref, RX VrefLevel [Byte0]: 36
7781 00:22:21.078859 [Byte1]: 36
7782 00:22:21.082798
7783 00:22:21.082878 Set Vref, RX VrefLevel [Byte0]: 37
7784 00:22:21.086332 [Byte1]: 37
7785 00:22:21.090784
7786 00:22:21.091256 Set Vref, RX VrefLevel [Byte0]: 38
7787 00:22:21.094090 [Byte1]: 38
7788 00:22:21.098343
7789 00:22:21.098752 Set Vref, RX VrefLevel [Byte0]: 39
7790 00:22:21.101891 [Byte1]: 39
7791 00:22:21.106243
7792 00:22:21.106656 Set Vref, RX VrefLevel [Byte0]: 40
7793 00:22:21.109604 [Byte1]: 40
7794 00:22:21.113575
7795 00:22:21.113990 Set Vref, RX VrefLevel [Byte0]: 41
7796 00:22:21.117088 [Byte1]: 41
7797 00:22:21.121684
7798 00:22:21.122192 Set Vref, RX VrefLevel [Byte0]: 42
7799 00:22:21.124581 [Byte1]: 42
7800 00:22:21.128804
7801 00:22:21.129469 Set Vref, RX VrefLevel [Byte0]: 43
7802 00:22:21.132041 [Byte1]: 43
7803 00:22:21.136806
7804 00:22:21.137389 Set Vref, RX VrefLevel [Byte0]: 44
7805 00:22:21.139530 [Byte1]: 44
7806 00:22:21.143834
7807 00:22:21.144441 Set Vref, RX VrefLevel [Byte0]: 45
7808 00:22:21.147407 [Byte1]: 45
7809 00:22:21.151768
7810 00:22:21.152179 Set Vref, RX VrefLevel [Byte0]: 46
7811 00:22:21.154684 [Byte1]: 46
7812 00:22:21.159658
7813 00:22:21.160072 Set Vref, RX VrefLevel [Byte0]: 47
7814 00:22:21.162662 [Byte1]: 47
7815 00:22:21.166716
7816 00:22:21.167225 Set Vref, RX VrefLevel [Byte0]: 48
7817 00:22:21.170228 [Byte1]: 48
7818 00:22:21.174329
7819 00:22:21.174944 Set Vref, RX VrefLevel [Byte0]: 49
7820 00:22:21.177478 [Byte1]: 49
7821 00:22:21.182313
7822 00:22:21.182726 Set Vref, RX VrefLevel [Byte0]: 50
7823 00:22:21.185063 [Byte1]: 50
7824 00:22:21.190035
7825 00:22:21.190601 Set Vref, RX VrefLevel [Byte0]: 51
7826 00:22:21.193041 [Byte1]: 51
7827 00:22:21.197818
7828 00:22:21.198229 Set Vref, RX VrefLevel [Byte0]: 52
7829 00:22:21.200864 [Byte1]: 52
7830 00:22:21.204808
7831 00:22:21.205219 Set Vref, RX VrefLevel [Byte0]: 53
7832 00:22:21.208231 [Byte1]: 53
7833 00:22:21.212535
7834 00:22:21.212950 Set Vref, RX VrefLevel [Byte0]: 54
7835 00:22:21.216233 [Byte1]: 54
7836 00:22:21.219844
7837 00:22:21.220397 Set Vref, RX VrefLevel [Byte0]: 55
7838 00:22:21.223686 [Byte1]: 55
7839 00:22:21.227664
7840 00:22:21.228079 Set Vref, RX VrefLevel [Byte0]: 56
7841 00:22:21.231072 [Byte1]: 56
7842 00:22:21.235627
7843 00:22:21.236104 Set Vref, RX VrefLevel [Byte0]: 57
7844 00:22:21.238639 [Byte1]: 57
7845 00:22:21.243078
7846 00:22:21.243490 Set Vref, RX VrefLevel [Byte0]: 58
7847 00:22:21.246535 [Byte1]: 58
7848 00:22:21.250722
7849 00:22:21.251177 Set Vref, RX VrefLevel [Byte0]: 59
7850 00:22:21.254006 [Byte1]: 59
7851 00:22:21.258469
7852 00:22:21.258885 Set Vref, RX VrefLevel [Byte0]: 60
7853 00:22:21.261889 [Byte1]: 60
7854 00:22:21.265851
7855 00:22:21.266396 Set Vref, RX VrefLevel [Byte0]: 61
7856 00:22:21.268851 [Byte1]: 61
7857 00:22:21.273754
7858 00:22:21.274196 Set Vref, RX VrefLevel [Byte0]: 62
7859 00:22:21.276819 [Byte1]: 62
7860 00:22:21.280986
7861 00:22:21.281438 Set Vref, RX VrefLevel [Byte0]: 63
7862 00:22:21.284636 [Byte1]: 63
7863 00:22:21.288646
7864 00:22:21.289069 Set Vref, RX VrefLevel [Byte0]: 64
7865 00:22:21.292138 [Byte1]: 64
7866 00:22:21.296317
7867 00:22:21.296728 Set Vref, RX VrefLevel [Byte0]: 65
7868 00:22:21.299904 [Byte1]: 65
7869 00:22:21.304191
7870 00:22:21.304608 Set Vref, RX VrefLevel [Byte0]: 66
7871 00:22:21.307211 [Byte1]: 66
7872 00:22:21.311755
7873 00:22:21.312164 Set Vref, RX VrefLevel [Byte0]: 67
7874 00:22:21.314816 [Byte1]: 67
7875 00:22:21.319406
7876 00:22:21.319816 Set Vref, RX VrefLevel [Byte0]: 68
7877 00:22:21.322709 [Byte1]: 68
7878 00:22:21.326903
7879 00:22:21.327442 Set Vref, RX VrefLevel [Byte0]: 69
7880 00:22:21.330221 [Byte1]: 69
7881 00:22:21.334448
7882 00:22:21.334860 Set Vref, RX VrefLevel [Byte0]: 70
7883 00:22:21.337661 [Byte1]: 70
7884 00:22:21.341743
7885 00:22:21.342156 Set Vref, RX VrefLevel [Byte0]: 71
7886 00:22:21.345346 [Byte1]: 71
7887 00:22:21.349906
7888 00:22:21.350352 Set Vref, RX VrefLevel [Byte0]: 72
7889 00:22:21.352954 [Byte1]: 72
7890 00:22:21.357376
7891 00:22:21.357801 Set Vref, RX VrefLevel [Byte0]: 73
7892 00:22:21.360533 [Byte1]: 73
7893 00:22:21.364902
7894 00:22:21.365519 Set Vref, RX VrefLevel [Byte0]: 74
7895 00:22:21.367924 [Byte1]: 74
7896 00:22:21.372629
7897 00:22:21.373170 Set Vref, RX VrefLevel [Byte0]: 75
7898 00:22:21.375507 [Byte1]: 75
7899 00:22:21.380346
7900 00:22:21.380880 Final RX Vref Byte 0 = 55 to rank0
7901 00:22:21.383421 Final RX Vref Byte 1 = 60 to rank0
7902 00:22:21.386403 Final RX Vref Byte 0 = 55 to rank1
7903 00:22:21.390071 Final RX Vref Byte 1 = 60 to rank1==
7904 00:22:21.393649 Dram Type= 6, Freq= 0, CH_0, rank 0
7905 00:22:21.400027 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7906 00:22:21.400444 ==
7907 00:22:21.400768 DQS Delay:
7908 00:22:21.403006 DQS0 = 0, DQS1 = 0
7909 00:22:21.403435 DQM Delay:
7910 00:22:21.403763 DQM0 = 128, DQM1 = 124
7911 00:22:21.406657 DQ Delay:
7912 00:22:21.409735 DQ0 =130, DQ1 =130, DQ2 =126, DQ3 =124
7913 00:22:21.413140 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =134
7914 00:22:21.416485 DQ8 =114, DQ9 =112, DQ10 =126, DQ11 =120
7915 00:22:21.419427 DQ12 =130, DQ13 =128, DQ14 =134, DQ15 =130
7916 00:22:21.419843
7917 00:22:21.420167
7918 00:22:21.420470
7919 00:22:21.423108 [DramC_TX_OE_Calibration] TA2
7920 00:22:21.426457 Original DQ_B0 (3 6) =30, OEN = 27
7921 00:22:21.429704 Original DQ_B1 (3 6) =30, OEN = 27
7922 00:22:21.432620 24, 0x0, End_B0=24 End_B1=24
7923 00:22:21.436045 25, 0x0, End_B0=25 End_B1=25
7924 00:22:21.436543 26, 0x0, End_B0=26 End_B1=26
7925 00:22:21.439126 27, 0x0, End_B0=27 End_B1=27
7926 00:22:21.442360 28, 0x0, End_B0=28 End_B1=28
7927 00:22:21.445910 29, 0x0, End_B0=29 End_B1=29
7928 00:22:21.446350 30, 0x0, End_B0=30 End_B1=30
7929 00:22:21.448823 31, 0x4545, End_B0=30 End_B1=30
7930 00:22:21.452459 Byte0 end_step=30 best_step=27
7931 00:22:21.455856 Byte1 end_step=30 best_step=27
7932 00:22:21.459017 Byte0 TX OE(2T, 0.5T) = (3, 3)
7933 00:22:21.461933 Byte1 TX OE(2T, 0.5T) = (3, 3)
7934 00:22:21.462346
7935 00:22:21.462667
7936 00:22:21.468622 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a17, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
7937 00:22:21.471791 CH0 RK0: MR19=303, MR18=1A17
7938 00:22:21.477988 CH0_RK0: MR19=0x303, MR18=0x1A17, DQSOSC=396, MR23=63, INC=23, DEC=15
7939 00:22:21.478068
7940 00:22:21.481254 ----->DramcWriteLeveling(PI) begin...
7941 00:22:21.481373 ==
7942 00:22:21.484987 Dram Type= 6, Freq= 0, CH_0, rank 1
7943 00:22:21.488002 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7944 00:22:21.488089 ==
7945 00:22:21.491568 Write leveling (Byte 0): 35 => 35
7946 00:22:21.495140 Write leveling (Byte 1): 28 => 28
7947 00:22:21.498113 DramcWriteLeveling(PI) end<-----
7948 00:22:21.498213
7949 00:22:21.498290 ==
7950 00:22:21.501485 Dram Type= 6, Freq= 0, CH_0, rank 1
7951 00:22:21.508004 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7952 00:22:21.508148 ==
7953 00:22:21.508242 [Gating] SW mode calibration
7954 00:22:21.517582 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7955 00:22:21.521130 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7956 00:22:21.527893 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7957 00:22:21.531159 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7958 00:22:21.534751 1 4 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7959 00:22:21.541182 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7960 00:22:21.543962 1 4 16 | B1->B0 | 2a29 3434 | 1 1 | (0 0) (1 1)
7961 00:22:21.547388 1 4 20 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
7962 00:22:21.554221 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7963 00:22:21.557457 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7964 00:22:21.560973 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7965 00:22:21.567557 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7966 00:22:21.570797 1 5 8 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
7967 00:22:21.574184 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7968 00:22:21.580471 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7969 00:22:21.584137 1 5 20 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
7970 00:22:21.587119 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7971 00:22:21.594308 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7972 00:22:21.597337 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7973 00:22:21.600319 1 6 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
7974 00:22:21.607380 1 6 8 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (0 0)
7975 00:22:21.610328 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7976 00:22:21.614008 1 6 16 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
7977 00:22:21.620499 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7978 00:22:21.623722 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7979 00:22:21.626984 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7980 00:22:21.633690 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7981 00:22:21.637024 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7982 00:22:21.639880 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7983 00:22:21.646668 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7984 00:22:21.649522 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7985 00:22:21.653144 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7986 00:22:21.659638 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7987 00:22:21.663089 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7988 00:22:21.666106 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7989 00:22:21.672560 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7990 00:22:21.675811 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7991 00:22:21.678969 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7992 00:22:21.686185 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7993 00:22:21.689504 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7994 00:22:21.692649 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7995 00:22:21.699558 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7996 00:22:21.702205 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7997 00:22:21.705911 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7998 00:22:21.712095 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7999 00:22:21.715269 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8000 00:22:21.718804 Total UI for P1: 0, mck2ui 16
8001 00:22:21.722429 best dqsien dly found for B0: ( 1, 9, 8)
8002 00:22:21.725595 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8003 00:22:21.732082 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8004 00:22:21.735123 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8005 00:22:21.738763 Total UI for P1: 0, mck2ui 16
8006 00:22:21.741931 best dqsien dly found for B1: ( 1, 9, 18)
8007 00:22:21.745077 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8008 00:22:21.748428 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8009 00:22:21.748895
8010 00:22:21.751926 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8011 00:22:21.755004 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8012 00:22:21.758809 [Gating] SW calibration Done
8013 00:22:21.759230 ==
8014 00:22:21.761753 Dram Type= 6, Freq= 0, CH_0, rank 1
8015 00:22:21.764820 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8016 00:22:21.768304 ==
8017 00:22:21.768952 RX Vref Scan: 0
8018 00:22:21.769490
8019 00:22:21.771821 RX Vref 0 -> 0, step: 1
8020 00:22:21.772238
8021 00:22:21.774849 RX Delay 0 -> 252, step: 8
8022 00:22:21.778410 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8023 00:22:21.781440 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8024 00:22:21.784925 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
8025 00:22:21.788224 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8026 00:22:21.794841 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8027 00:22:21.797966 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8028 00:22:21.801110 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8029 00:22:21.804690 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8030 00:22:21.807682 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8031 00:22:21.814698 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8032 00:22:21.817607 iDelay=200, Bit 10, Center 127 (64 ~ 191) 128
8033 00:22:21.821198 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8034 00:22:21.824748 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8035 00:22:21.827807 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8036 00:22:21.834235 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8037 00:22:21.837855 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8038 00:22:21.838270 ==
8039 00:22:21.840635 Dram Type= 6, Freq= 0, CH_0, rank 1
8040 00:22:21.844220 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8041 00:22:21.844639 ==
8042 00:22:21.847947 DQS Delay:
8043 00:22:21.848360 DQS0 = 0, DQS1 = 0
8044 00:22:21.851283 DQM Delay:
8045 00:22:21.851696 DQM0 = 131, DQM1 = 124
8046 00:22:21.852022 DQ Delay:
8047 00:22:21.854144 DQ0 =127, DQ1 =135, DQ2 =131, DQ3 =127
8048 00:22:21.857728 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
8049 00:22:21.864256 DQ8 =115, DQ9 =111, DQ10 =127, DQ11 =119
8050 00:22:21.867686 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
8051 00:22:21.868101
8052 00:22:21.868422
8053 00:22:21.868720 ==
8054 00:22:21.870906 Dram Type= 6, Freq= 0, CH_0, rank 1
8055 00:22:21.873878 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8056 00:22:21.874292 ==
8057 00:22:21.874613
8058 00:22:21.874912
8059 00:22:21.877088 TX Vref Scan disable
8060 00:22:21.880391 == TX Byte 0 ==
8061 00:22:21.883989 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8062 00:22:21.887060 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8063 00:22:21.890483 == TX Byte 1 ==
8064 00:22:21.893820 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8065 00:22:21.897319 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8066 00:22:21.897739 ==
8067 00:22:21.900610 Dram Type= 6, Freq= 0, CH_0, rank 1
8068 00:22:21.906776 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8069 00:22:21.907191 ==
8070 00:22:21.919030
8071 00:22:21.922253 TX Vref early break, caculate TX vref
8072 00:22:21.925734 TX Vref=16, minBit 9, minWin=22, winSum=383
8073 00:22:21.928770 TX Vref=18, minBit 9, minWin=23, winSum=389
8074 00:22:21.932445 TX Vref=20, minBit 3, minWin=24, winSum=398
8075 00:22:21.935404 TX Vref=22, minBit 2, minWin=24, winSum=407
8076 00:22:21.938430 TX Vref=24, minBit 3, minWin=25, winSum=416
8077 00:22:21.945439 TX Vref=26, minBit 3, minWin=25, winSum=419
8078 00:22:21.948398 TX Vref=28, minBit 4, minWin=25, winSum=422
8079 00:22:21.951950 TX Vref=30, minBit 1, minWin=25, winSum=417
8080 00:22:21.955156 TX Vref=32, minBit 8, minWin=24, winSum=407
8081 00:22:21.958703 TX Vref=34, minBit 0, minWin=24, winSum=398
8082 00:22:21.965740 [TxChooseVref] Worse bit 4, Min win 25, Win sum 422, Final Vref 28
8083 00:22:21.966196
8084 00:22:21.968150 Final TX Range 0 Vref 28
8085 00:22:21.968621
8086 00:22:21.968951 ==
8087 00:22:21.971748 Dram Type= 6, Freq= 0, CH_0, rank 1
8088 00:22:21.974958 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8089 00:22:21.975503 ==
8090 00:22:21.975970
8091 00:22:21.976413
8092 00:22:21.978200 TX Vref Scan disable
8093 00:22:21.984678 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8094 00:22:21.985314 == TX Byte 0 ==
8095 00:22:21.988129 u2DelayCellOfst[0]=14 cells (4 PI)
8096 00:22:21.990996 u2DelayCellOfst[1]=17 cells (5 PI)
8097 00:22:21.994554 u2DelayCellOfst[2]=10 cells (3 PI)
8098 00:22:21.997910 u2DelayCellOfst[3]=10 cells (3 PI)
8099 00:22:22.000879 u2DelayCellOfst[4]=10 cells (3 PI)
8100 00:22:22.004562 u2DelayCellOfst[5]=0 cells (0 PI)
8101 00:22:22.007495 u2DelayCellOfst[6]=17 cells (5 PI)
8102 00:22:22.010879 u2DelayCellOfst[7]=17 cells (5 PI)
8103 00:22:22.014300 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8104 00:22:22.017546 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8105 00:22:22.021133 == TX Byte 1 ==
8106 00:22:22.024663 u2DelayCellOfst[8]=0 cells (0 PI)
8107 00:22:22.027405 u2DelayCellOfst[9]=0 cells (0 PI)
8108 00:22:22.031017 u2DelayCellOfst[10]=7 cells (2 PI)
8109 00:22:22.034111 u2DelayCellOfst[11]=3 cells (1 PI)
8110 00:22:22.037724 u2DelayCellOfst[12]=10 cells (3 PI)
8111 00:22:22.038141 u2DelayCellOfst[13]=10 cells (3 PI)
8112 00:22:22.040684 u2DelayCellOfst[14]=14 cells (4 PI)
8113 00:22:22.044186 u2DelayCellOfst[15]=10 cells (3 PI)
8114 00:22:22.050864 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8115 00:22:22.053858 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8116 00:22:22.056876 DramC Write-DBI on
8117 00:22:22.057560 ==
8118 00:22:22.060441 Dram Type= 6, Freq= 0, CH_0, rank 1
8119 00:22:22.063503 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8120 00:22:22.064101 ==
8121 00:22:22.064661
8122 00:22:22.065175
8123 00:22:22.067061 TX Vref Scan disable
8124 00:22:22.067614 == TX Byte 0 ==
8125 00:22:22.073737 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8126 00:22:22.074255 == TX Byte 1 ==
8127 00:22:22.077206 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8128 00:22:22.080394 DramC Write-DBI off
8129 00:22:22.080872
8130 00:22:22.081379 [DATLAT]
8131 00:22:22.083551 Freq=1600, CH0 RK1
8132 00:22:22.084081
8133 00:22:22.084546 DATLAT Default: 0xf
8134 00:22:22.087045 0, 0xFFFF, sum = 0
8135 00:22:22.089965 1, 0xFFFF, sum = 0
8136 00:22:22.090615 2, 0xFFFF, sum = 0
8137 00:22:22.092986 3, 0xFFFF, sum = 0
8138 00:22:22.093693 4, 0xFFFF, sum = 0
8139 00:22:22.096694 5, 0xFFFF, sum = 0
8140 00:22:22.097297 6, 0xFFFF, sum = 0
8141 00:22:22.099943 7, 0xFFFF, sum = 0
8142 00:22:22.100494 8, 0xFFFF, sum = 0
8143 00:22:22.102881 9, 0xFFFF, sum = 0
8144 00:22:22.103444 10, 0xFFFF, sum = 0
8145 00:22:22.106399 11, 0xFFFF, sum = 0
8146 00:22:22.106995 12, 0xFFFF, sum = 0
8147 00:22:22.109888 13, 0xFFFF, sum = 0
8148 00:22:22.110536 14, 0x0, sum = 1
8149 00:22:22.113350 15, 0x0, sum = 2
8150 00:22:22.113841 16, 0x0, sum = 3
8151 00:22:22.116215 17, 0x0, sum = 4
8152 00:22:22.116839 best_step = 15
8153 00:22:22.117393
8154 00:22:22.117793 ==
8155 00:22:22.119448 Dram Type= 6, Freq= 0, CH_0, rank 1
8156 00:22:22.126469 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8157 00:22:22.126887 ==
8158 00:22:22.127214 RX Vref Scan: 0
8159 00:22:22.127519
8160 00:22:22.129734 RX Vref 0 -> 0, step: 1
8161 00:22:22.130147
8162 00:22:22.132761 RX Delay 11 -> 252, step: 4
8163 00:22:22.136170 iDelay=187, Bit 0, Center 126 (79 ~ 174) 96
8164 00:22:22.139582 iDelay=187, Bit 1, Center 132 (79 ~ 186) 108
8165 00:22:22.142777 iDelay=187, Bit 2, Center 126 (75 ~ 178) 104
8166 00:22:22.149370 iDelay=187, Bit 3, Center 126 (75 ~ 178) 104
8167 00:22:22.152439 iDelay=187, Bit 4, Center 132 (83 ~ 182) 100
8168 00:22:22.156013 iDelay=187, Bit 5, Center 120 (67 ~ 174) 108
8169 00:22:22.158878 iDelay=187, Bit 6, Center 138 (91 ~ 186) 96
8170 00:22:22.162728 iDelay=187, Bit 7, Center 134 (83 ~ 186) 104
8171 00:22:22.169086 iDelay=187, Bit 8, Center 114 (63 ~ 166) 104
8172 00:22:22.172691 iDelay=187, Bit 9, Center 110 (59 ~ 162) 104
8173 00:22:22.175731 iDelay=187, Bit 10, Center 126 (71 ~ 182) 112
8174 00:22:22.179171 iDelay=187, Bit 11, Center 118 (67 ~ 170) 104
8175 00:22:22.185352 iDelay=187, Bit 12, Center 128 (75 ~ 182) 108
8176 00:22:22.188890 iDelay=187, Bit 13, Center 130 (79 ~ 182) 104
8177 00:22:22.191973 iDelay=187, Bit 14, Center 134 (83 ~ 186) 104
8178 00:22:22.195187 iDelay=187, Bit 15, Center 132 (79 ~ 186) 108
8179 00:22:22.195268 ==
8180 00:22:22.198679 Dram Type= 6, Freq= 0, CH_0, rank 1
8181 00:22:22.205349 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8182 00:22:22.205928 ==
8183 00:22:22.206269 DQS Delay:
8184 00:22:22.206581 DQS0 = 0, DQS1 = 0
8185 00:22:22.208844 DQM Delay:
8186 00:22:22.209297 DQM0 = 129, DQM1 = 124
8187 00:22:22.211772 DQ Delay:
8188 00:22:22.215016 DQ0 =126, DQ1 =132, DQ2 =126, DQ3 =126
8189 00:22:22.218433 DQ4 =132, DQ5 =120, DQ6 =138, DQ7 =134
8190 00:22:22.221553 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =118
8191 00:22:22.225194 DQ12 =128, DQ13 =130, DQ14 =134, DQ15 =132
8192 00:22:22.225715
8193 00:22:22.226046
8194 00:22:22.226352
8195 00:22:22.228069 [DramC_TX_OE_Calibration] TA2
8196 00:22:22.231446 Original DQ_B0 (3 6) =30, OEN = 27
8197 00:22:22.234818 Original DQ_B1 (3 6) =30, OEN = 27
8198 00:22:22.238309 24, 0x0, End_B0=24 End_B1=24
8199 00:22:22.238730 25, 0x0, End_B0=25 End_B1=25
8200 00:22:22.241347 26, 0x0, End_B0=26 End_B1=26
8201 00:22:22.244695 27, 0x0, End_B0=27 End_B1=27
8202 00:22:22.248167 28, 0x0, End_B0=28 End_B1=28
8203 00:22:22.251780 29, 0x0, End_B0=29 End_B1=29
8204 00:22:22.252448 30, 0x0, End_B0=30 End_B1=30
8205 00:22:22.254639 31, 0x4141, End_B0=30 End_B1=30
8206 00:22:22.258260 Byte0 end_step=30 best_step=27
8207 00:22:22.261053 Byte1 end_step=30 best_step=27
8208 00:22:22.264505 Byte0 TX OE(2T, 0.5T) = (3, 3)
8209 00:22:22.267404 Byte1 TX OE(2T, 0.5T) = (3, 3)
8210 00:22:22.267504
8211 00:22:22.267580
8212 00:22:22.274130 [DQSOSCAuto] RK1, (LSB)MR18= 0x1615, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
8213 00:22:22.277617 CH0 RK1: MR19=303, MR18=1615
8214 00:22:22.284107 CH0_RK1: MR19=0x303, MR18=0x1615, DQSOSC=398, MR23=63, INC=23, DEC=15
8215 00:22:22.287555 [RxdqsGatingPostProcess] freq 1600
8216 00:22:22.294086 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8217 00:22:22.294167 best DQS0 dly(2T, 0.5T) = (1, 1)
8218 00:22:22.297633 best DQS1 dly(2T, 0.5T) = (1, 1)
8219 00:22:22.300165 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8220 00:22:22.303967 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8221 00:22:22.306841 best DQS0 dly(2T, 0.5T) = (1, 1)
8222 00:22:22.310647 best DQS1 dly(2T, 0.5T) = (1, 1)
8223 00:22:22.313414 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8224 00:22:22.316993 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8225 00:22:22.320578 Pre-setting of DQS Precalculation
8226 00:22:22.323683 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8227 00:22:22.323770 ==
8228 00:22:22.326776 Dram Type= 6, Freq= 0, CH_1, rank 0
8229 00:22:22.333302 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8230 00:22:22.333384 ==
8231 00:22:22.336693 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8232 00:22:22.343162 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8233 00:22:22.346461 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8234 00:22:22.353157 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8235 00:22:22.360886 [CA 0] Center 42 (13~72) winsize 60
8236 00:22:22.364580 [CA 1] Center 42 (13~72) winsize 60
8237 00:22:22.367515 [CA 2] Center 39 (9~69) winsize 61
8238 00:22:22.371130 [CA 3] Center 38 (8~68) winsize 61
8239 00:22:22.374163 [CA 4] Center 38 (8~69) winsize 62
8240 00:22:22.378038 [CA 5] Center 37 (8~67) winsize 60
8241 00:22:22.378119
8242 00:22:22.380619 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8243 00:22:22.380700
8244 00:22:22.387381 [CATrainingPosCal] consider 1 rank data
8245 00:22:22.387467 u2DelayCellTimex100 = 275/100 ps
8246 00:22:22.394091 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8247 00:22:22.397187 CA1 delay=42 (13~72),Diff = 5 PI (17 cell)
8248 00:22:22.400433 CA2 delay=39 (9~69),Diff = 2 PI (7 cell)
8249 00:22:22.403667 CA3 delay=38 (8~68),Diff = 1 PI (3 cell)
8250 00:22:22.407037 CA4 delay=38 (8~69),Diff = 1 PI (3 cell)
8251 00:22:22.410029 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8252 00:22:22.410162
8253 00:22:22.413656 CA PerBit enable=1, Macro0, CA PI delay=37
8254 00:22:22.413805
8255 00:22:22.416778 [CBTSetCACLKResult] CA Dly = 37
8256 00:22:22.420282 CS Dly: 8 (0~39)
8257 00:22:22.423229 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8258 00:22:22.426931 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8259 00:22:22.427130 ==
8260 00:22:22.430166 Dram Type= 6, Freq= 0, CH_1, rank 1
8261 00:22:22.436778 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8262 00:22:22.437222 ==
8263 00:22:22.440231 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8264 00:22:22.446494 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8265 00:22:22.449929 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8266 00:22:22.456369 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8267 00:22:22.464778 [CA 0] Center 42 (12~72) winsize 61
8268 00:22:22.468163 [CA 1] Center 43 (13~73) winsize 61
8269 00:22:22.470707 [CA 2] Center 38 (9~68) winsize 60
8270 00:22:22.474472 [CA 3] Center 37 (7~67) winsize 61
8271 00:22:22.477570 [CA 4] Center 38 (8~68) winsize 61
8272 00:22:22.480941 [CA 5] Center 37 (7~67) winsize 61
8273 00:22:22.481091
8274 00:22:22.484193 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8275 00:22:22.484323
8276 00:22:22.490895 [CATrainingPosCal] consider 2 rank data
8277 00:22:22.490976 u2DelayCellTimex100 = 275/100 ps
8278 00:22:22.497501 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8279 00:22:22.500450 CA1 delay=42 (13~72),Diff = 5 PI (17 cell)
8280 00:22:22.503985 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8281 00:22:22.507210 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8282 00:22:22.510273 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
8283 00:22:22.513546 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8284 00:22:22.513633
8285 00:22:22.517138 CA PerBit enable=1, Macro0, CA PI delay=37
8286 00:22:22.517225
8287 00:22:22.520128 [CBTSetCACLKResult] CA Dly = 37
8288 00:22:22.523560 CS Dly: 9 (0~42)
8289 00:22:22.527237 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8290 00:22:22.530136 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8291 00:22:22.530246
8292 00:22:22.533842 ----->DramcWriteLeveling(PI) begin...
8293 00:22:22.533964 ==
8294 00:22:22.536630 Dram Type= 6, Freq= 0, CH_1, rank 0
8295 00:22:22.543629 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8296 00:22:22.543764 ==
8297 00:22:22.546714 Write leveling (Byte 0): 25 => 25
8298 00:22:22.550291 Write leveling (Byte 1): 24 => 24
8299 00:22:22.550427 DramcWriteLeveling(PI) end<-----
8300 00:22:22.550529
8301 00:22:22.553280 ==
8302 00:22:22.556806 Dram Type= 6, Freq= 0, CH_1, rank 0
8303 00:22:22.560078 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8304 00:22:22.560183 ==
8305 00:22:22.563300 [Gating] SW mode calibration
8306 00:22:22.569974 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8307 00:22:22.572985 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8308 00:22:22.579633 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8309 00:22:22.582743 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8310 00:22:22.586570 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8311 00:22:22.592986 1 4 12 | B1->B0 | 2424 3434 | 0 0 | (0 0) (0 0)
8312 00:22:22.596215 1 4 16 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
8313 00:22:22.599739 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8314 00:22:22.606284 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8315 00:22:22.609791 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8316 00:22:22.612946 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8317 00:22:22.619936 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8318 00:22:22.623049 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8319 00:22:22.626202 1 5 12 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (1 0)
8320 00:22:22.632616 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8321 00:22:22.636306 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8322 00:22:22.639155 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8323 00:22:22.646041 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8324 00:22:22.648880 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8325 00:22:22.652523 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8326 00:22:22.659059 1 6 8 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
8327 00:22:22.662578 1 6 12 | B1->B0 | 3636 4545 | 0 0 | (0 0) (0 0)
8328 00:22:22.665449 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8329 00:22:22.672119 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8330 00:22:22.675310 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8331 00:22:22.678907 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8332 00:22:22.685535 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8333 00:22:22.688897 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8334 00:22:22.692306 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8335 00:22:22.698554 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8336 00:22:22.702297 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8337 00:22:22.705336 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8338 00:22:22.711711 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8339 00:22:22.715404 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8340 00:22:22.718431 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8341 00:22:22.725004 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8342 00:22:22.728593 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8343 00:22:22.731496 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8344 00:22:22.737988 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8345 00:22:22.741369 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8346 00:22:22.744517 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8347 00:22:22.751571 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8348 00:22:22.754638 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8349 00:22:22.757691 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8350 00:22:22.764273 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8351 00:22:22.767787 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8352 00:22:22.774625 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8353 00:22:22.775042 Total UI for P1: 0, mck2ui 16
8354 00:22:22.777474 best dqsien dly found for B0: ( 1, 9, 10)
8355 00:22:22.780928 Total UI for P1: 0, mck2ui 16
8356 00:22:22.784429 best dqsien dly found for B1: ( 1, 9, 12)
8357 00:22:22.787614 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8358 00:22:22.794026 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8359 00:22:22.794441
8360 00:22:22.797506 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8361 00:22:22.801063 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8362 00:22:22.803930 [Gating] SW calibration Done
8363 00:22:22.804345 ==
8364 00:22:22.807672 Dram Type= 6, Freq= 0, CH_1, rank 0
8365 00:22:22.810430 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8366 00:22:22.810867 ==
8367 00:22:22.813670 RX Vref Scan: 0
8368 00:22:22.814087
8369 00:22:22.814413 RX Vref 0 -> 0, step: 1
8370 00:22:22.814715
8371 00:22:22.817201 RX Delay 0 -> 252, step: 8
8372 00:22:22.820118 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8373 00:22:22.827349 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8374 00:22:22.830237 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8375 00:22:22.833654 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8376 00:22:22.836837 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8377 00:22:22.840340 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8378 00:22:22.846854 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8379 00:22:22.850388 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8380 00:22:22.853396 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8381 00:22:22.856409 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8382 00:22:22.859834 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8383 00:22:22.866352 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8384 00:22:22.869810 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8385 00:22:22.873354 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8386 00:22:22.876258 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8387 00:22:22.883109 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8388 00:22:22.883338 ==
8389 00:22:22.885921 Dram Type= 6, Freq= 0, CH_1, rank 0
8390 00:22:22.889586 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8391 00:22:22.889811 ==
8392 00:22:22.890001 DQS Delay:
8393 00:22:22.892320 DQS0 = 0, DQS1 = 0
8394 00:22:22.892543 DQM Delay:
8395 00:22:22.896192 DQM0 = 135, DQM1 = 131
8396 00:22:22.896416 DQ Delay:
8397 00:22:22.899521 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8398 00:22:22.902254 DQ4 =131, DQ5 =143, DQ6 =147, DQ7 =131
8399 00:22:22.905617 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =127
8400 00:22:22.908756 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =139
8401 00:22:22.908866
8402 00:22:22.908957
8403 00:22:22.912203 ==
8404 00:22:22.915973 Dram Type= 6, Freq= 0, CH_1, rank 0
8405 00:22:22.918955 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8406 00:22:22.919052 ==
8407 00:22:22.919149
8408 00:22:22.919208
8409 00:22:22.921996 TX Vref Scan disable
8410 00:22:22.922077 == TX Byte 0 ==
8411 00:22:22.929192 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8412 00:22:22.932401 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8413 00:22:22.933079 == TX Byte 1 ==
8414 00:22:22.939051 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8415 00:22:22.942511 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8416 00:22:22.943070 ==
8417 00:22:22.945558 Dram Type= 6, Freq= 0, CH_1, rank 0
8418 00:22:22.949114 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8419 00:22:22.949579 ==
8420 00:22:22.961859
8421 00:22:22.964933 TX Vref early break, caculate TX vref
8422 00:22:22.968602 TX Vref=16, minBit 5, minWin=22, winSum=368
8423 00:22:22.971650 TX Vref=18, minBit 8, minWin=22, winSum=379
8424 00:22:22.975118 TX Vref=20, minBit 3, minWin=23, winSum=392
8425 00:22:22.978156 TX Vref=22, minBit 6, minWin=24, winSum=403
8426 00:22:22.981386 TX Vref=24, minBit 1, minWin=25, winSum=411
8427 00:22:22.987879 TX Vref=26, minBit 1, minWin=25, winSum=413
8428 00:22:22.991539 TX Vref=28, minBit 7, minWin=25, winSum=422
8429 00:22:22.994479 TX Vref=30, minBit 0, minWin=24, winSum=418
8430 00:22:22.998103 TX Vref=32, minBit 0, minWin=25, winSum=411
8431 00:22:23.001377 TX Vref=34, minBit 9, minWin=23, winSum=396
8432 00:22:23.007797 [TxChooseVref] Worse bit 7, Min win 25, Win sum 422, Final Vref 28
8433 00:22:23.007919
8434 00:22:23.011411 Final TX Range 0 Vref 28
8435 00:22:23.011544
8436 00:22:23.011658 ==
8437 00:22:23.014294 Dram Type= 6, Freq= 0, CH_1, rank 0
8438 00:22:23.017903 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8439 00:22:23.018018 ==
8440 00:22:23.018142
8441 00:22:23.018251
8442 00:22:23.021021 TX Vref Scan disable
8443 00:22:23.027416 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8444 00:22:23.027547 == TX Byte 0 ==
8445 00:22:23.031208 u2DelayCellOfst[0]=14 cells (4 PI)
8446 00:22:23.034205 u2DelayCellOfst[1]=10 cells (3 PI)
8447 00:22:23.037572 u2DelayCellOfst[2]=0 cells (0 PI)
8448 00:22:23.040681 u2DelayCellOfst[3]=7 cells (2 PI)
8449 00:22:23.044332 u2DelayCellOfst[4]=7 cells (2 PI)
8450 00:22:23.047566 u2DelayCellOfst[5]=14 cells (4 PI)
8451 00:22:23.051147 u2DelayCellOfst[6]=14 cells (4 PI)
8452 00:22:23.054491 u2DelayCellOfst[7]=7 cells (2 PI)
8453 00:22:23.057492 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8454 00:22:23.060823 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8455 00:22:23.064191 == TX Byte 1 ==
8456 00:22:23.067316 u2DelayCellOfst[8]=0 cells (0 PI)
8457 00:22:23.070771 u2DelayCellOfst[9]=3 cells (1 PI)
8458 00:22:23.074211 u2DelayCellOfst[10]=14 cells (4 PI)
8459 00:22:23.074893 u2DelayCellOfst[11]=7 cells (2 PI)
8460 00:22:23.077177 u2DelayCellOfst[12]=14 cells (4 PI)
8461 00:22:23.080847 u2DelayCellOfst[13]=17 cells (5 PI)
8462 00:22:23.084037 u2DelayCellOfst[14]=21 cells (6 PI)
8463 00:22:23.087219 u2DelayCellOfst[15]=17 cells (5 PI)
8464 00:22:23.093572 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8465 00:22:23.097201 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8466 00:22:23.097647 DramC Write-DBI on
8467 00:22:23.100160 ==
8468 00:22:23.100571 Dram Type= 6, Freq= 0, CH_1, rank 0
8469 00:22:23.106926 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8470 00:22:23.107341 ==
8471 00:22:23.107667
8472 00:22:23.107964
8473 00:22:23.109869 TX Vref Scan disable
8474 00:22:23.110277 == TX Byte 0 ==
8475 00:22:23.116653 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8476 00:22:23.117063 == TX Byte 1 ==
8477 00:22:23.119704 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8478 00:22:23.123112 DramC Write-DBI off
8479 00:22:23.123522
8480 00:22:23.123841 [DATLAT]
8481 00:22:23.126515 Freq=1600, CH1 RK0
8482 00:22:23.126974
8483 00:22:23.127306 DATLAT Default: 0xf
8484 00:22:23.129660 0, 0xFFFF, sum = 0
8485 00:22:23.130079 1, 0xFFFF, sum = 0
8486 00:22:23.133125 2, 0xFFFF, sum = 0
8487 00:22:23.133591 3, 0xFFFF, sum = 0
8488 00:22:23.136087 4, 0xFFFF, sum = 0
8489 00:22:23.139853 5, 0xFFFF, sum = 0
8490 00:22:23.140268 6, 0xFFFF, sum = 0
8491 00:22:23.143381 7, 0xFFFF, sum = 0
8492 00:22:23.143795 8, 0xFFFF, sum = 0
8493 00:22:23.146474 9, 0xFFFF, sum = 0
8494 00:22:23.146888 10, 0xFFFF, sum = 0
8495 00:22:23.149391 11, 0xFFFF, sum = 0
8496 00:22:23.149835 12, 0xFFFF, sum = 0
8497 00:22:23.153078 13, 0xFFFF, sum = 0
8498 00:22:23.153560 14, 0x0, sum = 1
8499 00:22:23.156125 15, 0x0, sum = 2
8500 00:22:23.156540 16, 0x0, sum = 3
8501 00:22:23.159535 17, 0x0, sum = 4
8502 00:22:23.160181 best_step = 15
8503 00:22:23.160850
8504 00:22:23.161459 ==
8505 00:22:23.162521 Dram Type= 6, Freq= 0, CH_1, rank 0
8506 00:22:23.166079 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8507 00:22:23.169733 ==
8508 00:22:23.170340 RX Vref Scan: 1
8509 00:22:23.170930
8510 00:22:23.172422 Set Vref Range= 24 -> 127
8511 00:22:23.172978
8512 00:22:23.176142 RX Vref 24 -> 127, step: 1
8513 00:22:23.176748
8514 00:22:23.177330 RX Delay 19 -> 252, step: 4
8515 00:22:23.177788
8516 00:22:23.178977 Set Vref, RX VrefLevel [Byte0]: 24
8517 00:22:23.182567 [Byte1]: 24
8518 00:22:23.186515
8519 00:22:23.186921 Set Vref, RX VrefLevel [Byte0]: 25
8520 00:22:23.189461 [Byte1]: 25
8521 00:22:23.193936
8522 00:22:23.194382 Set Vref, RX VrefLevel [Byte0]: 26
8523 00:22:23.197466 [Byte1]: 26
8524 00:22:23.201228
8525 00:22:23.201966 Set Vref, RX VrefLevel [Byte0]: 27
8526 00:22:23.204747 [Byte1]: 27
8527 00:22:23.209136
8528 00:22:23.209607 Set Vref, RX VrefLevel [Byte0]: 28
8529 00:22:23.212637 [Byte1]: 28
8530 00:22:23.216956
8531 00:22:23.217572 Set Vref, RX VrefLevel [Byte0]: 29
8532 00:22:23.220071 [Byte1]: 29
8533 00:22:23.224098
8534 00:22:23.224663 Set Vref, RX VrefLevel [Byte0]: 30
8535 00:22:23.227860 [Byte1]: 30
8536 00:22:23.231750
8537 00:22:23.232153 Set Vref, RX VrefLevel [Byte0]: 31
8538 00:22:23.235011 [Byte1]: 31
8539 00:22:23.239902
8540 00:22:23.240539 Set Vref, RX VrefLevel [Byte0]: 32
8541 00:22:23.242758 [Byte1]: 32
8542 00:22:23.246834
8543 00:22:23.247450 Set Vref, RX VrefLevel [Byte0]: 33
8544 00:22:23.250513 [Byte1]: 33
8545 00:22:23.254254
8546 00:22:23.254659 Set Vref, RX VrefLevel [Byte0]: 34
8547 00:22:23.258089 [Byte1]: 34
8548 00:22:23.262192
8549 00:22:23.262600 Set Vref, RX VrefLevel [Byte0]: 35
8550 00:22:23.265912 [Byte1]: 35
8551 00:22:23.269800
8552 00:22:23.270206 Set Vref, RX VrefLevel [Byte0]: 36
8553 00:22:23.273374 [Byte1]: 36
8554 00:22:23.277433
8555 00:22:23.277843 Set Vref, RX VrefLevel [Byte0]: 37
8556 00:22:23.280825 [Byte1]: 37
8557 00:22:23.284501
8558 00:22:23.284911 Set Vref, RX VrefLevel [Byte0]: 38
8559 00:22:23.288268 [Byte1]: 38
8560 00:22:23.292298
8561 00:22:23.292909 Set Vref, RX VrefLevel [Byte0]: 39
8562 00:22:23.296150 [Byte1]: 39
8563 00:22:23.299983
8564 00:22:23.300487 Set Vref, RX VrefLevel [Byte0]: 40
8565 00:22:23.303258 [Byte1]: 40
8566 00:22:23.307592
8567 00:22:23.307994 Set Vref, RX VrefLevel [Byte0]: 41
8568 00:22:23.311241 [Byte1]: 41
8569 00:22:23.315621
8570 00:22:23.316249 Set Vref, RX VrefLevel [Byte0]: 42
8571 00:22:23.318360 [Byte1]: 42
8572 00:22:23.322639
8573 00:22:23.323266 Set Vref, RX VrefLevel [Byte0]: 43
8574 00:22:23.326076 [Byte1]: 43
8575 00:22:23.330353
8576 00:22:23.330948 Set Vref, RX VrefLevel [Byte0]: 44
8577 00:22:23.333326 [Byte1]: 44
8578 00:22:23.337836
8579 00:22:23.338368 Set Vref, RX VrefLevel [Byte0]: 45
8580 00:22:23.341255 [Byte1]: 45
8581 00:22:23.345493
8582 00:22:23.345903 Set Vref, RX VrefLevel [Byte0]: 46
8583 00:22:23.348971 [Byte1]: 46
8584 00:22:23.353141
8585 00:22:23.353649 Set Vref, RX VrefLevel [Byte0]: 47
8586 00:22:23.356316 [Byte1]: 47
8587 00:22:23.360437
8588 00:22:23.360971 Set Vref, RX VrefLevel [Byte0]: 48
8589 00:22:23.364119 [Byte1]: 48
8590 00:22:23.368238
8591 00:22:23.368765 Set Vref, RX VrefLevel [Byte0]: 49
8592 00:22:23.371362 [Byte1]: 49
8593 00:22:23.375822
8594 00:22:23.376407 Set Vref, RX VrefLevel [Byte0]: 50
8595 00:22:23.379296 [Byte1]: 50
8596 00:22:23.383207
8597 00:22:23.383610 Set Vref, RX VrefLevel [Byte0]: 51
8598 00:22:23.387020 [Byte1]: 51
8599 00:22:23.390895
8600 00:22:23.391454 Set Vref, RX VrefLevel [Byte0]: 52
8601 00:22:23.394482 [Byte1]: 52
8602 00:22:23.398470
8603 00:22:23.399022 Set Vref, RX VrefLevel [Byte0]: 53
8604 00:22:23.401465 [Byte1]: 53
8605 00:22:23.405851
8606 00:22:23.406484 Set Vref, RX VrefLevel [Byte0]: 54
8607 00:22:23.409301 [Byte1]: 54
8608 00:22:23.413848
8609 00:22:23.414338 Set Vref, RX VrefLevel [Byte0]: 55
8610 00:22:23.416515 [Byte1]: 55
8611 00:22:23.420956
8612 00:22:23.421541 Set Vref, RX VrefLevel [Byte0]: 56
8613 00:22:23.424267 [Byte1]: 56
8614 00:22:23.428703
8615 00:22:23.429123 Set Vref, RX VrefLevel [Byte0]: 57
8616 00:22:23.431946 [Byte1]: 57
8617 00:22:23.436090
8618 00:22:23.436520 Set Vref, RX VrefLevel [Byte0]: 58
8619 00:22:23.439711 [Byte1]: 58
8620 00:22:23.443841
8621 00:22:23.444254 Set Vref, RX VrefLevel [Byte0]: 59
8622 00:22:23.447304 [Byte1]: 59
8623 00:22:23.451089
8624 00:22:23.451576 Set Vref, RX VrefLevel [Byte0]: 60
8625 00:22:23.454760 [Byte1]: 60
8626 00:22:23.459196
8627 00:22:23.459795 Set Vref, RX VrefLevel [Byte0]: 61
8628 00:22:23.462206 [Byte1]: 61
8629 00:22:23.466418
8630 00:22:23.467002 Set Vref, RX VrefLevel [Byte0]: 62
8631 00:22:23.469691 [Byte1]: 62
8632 00:22:23.473847
8633 00:22:23.473957 Set Vref, RX VrefLevel [Byte0]: 63
8634 00:22:23.476995 [Byte1]: 63
8635 00:22:23.481768
8636 00:22:23.481857 Set Vref, RX VrefLevel [Byte0]: 64
8637 00:22:23.484685 [Byte1]: 64
8638 00:22:23.488864
8639 00:22:23.488970 Set Vref, RX VrefLevel [Byte0]: 65
8640 00:22:23.491940 [Byte1]: 65
8641 00:22:23.496616
8642 00:22:23.496695 Set Vref, RX VrefLevel [Byte0]: 66
8643 00:22:23.499677 [Byte1]: 66
8644 00:22:23.503843
8645 00:22:23.503922 Set Vref, RX VrefLevel [Byte0]: 67
8646 00:22:23.507654 [Byte1]: 67
8647 00:22:23.511616
8648 00:22:23.511696 Set Vref, RX VrefLevel [Byte0]: 68
8649 00:22:23.514775 [Byte1]: 68
8650 00:22:23.519303
8651 00:22:23.519383 Set Vref, RX VrefLevel [Byte0]: 69
8652 00:22:23.522548 [Byte1]: 69
8653 00:22:23.526724
8654 00:22:23.526805 Set Vref, RX VrefLevel [Byte0]: 70
8655 00:22:23.530212 [Byte1]: 70
8656 00:22:23.534294
8657 00:22:23.534374 Set Vref, RX VrefLevel [Byte0]: 71
8658 00:22:23.537941 [Byte1]: 71
8659 00:22:23.542137
8660 00:22:23.542223 Set Vref, RX VrefLevel [Byte0]: 72
8661 00:22:23.545453 [Byte1]: 72
8662 00:22:23.549656
8663 00:22:23.550067 Final RX Vref Byte 0 = 58 to rank0
8664 00:22:23.553461 Final RX Vref Byte 1 = 54 to rank0
8665 00:22:23.556872 Final RX Vref Byte 0 = 58 to rank1
8666 00:22:23.559717 Final RX Vref Byte 1 = 54 to rank1==
8667 00:22:23.563103 Dram Type= 6, Freq= 0, CH_1, rank 0
8668 00:22:23.569702 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8669 00:22:23.570143 ==
8670 00:22:23.570482 DQS Delay:
8671 00:22:23.573228 DQS0 = 0, DQS1 = 0
8672 00:22:23.573691 DQM Delay:
8673 00:22:23.574020 DQM0 = 132, DQM1 = 128
8674 00:22:23.576040 DQ Delay:
8675 00:22:23.579663 DQ0 =138, DQ1 =130, DQ2 =118, DQ3 =132
8676 00:22:23.582749 DQ4 =130, DQ5 =142, DQ6 =146, DQ7 =126
8677 00:22:23.586300 DQ8 =112, DQ9 =114, DQ10 =130, DQ11 =122
8678 00:22:23.589411 DQ12 =138, DQ13 =136, DQ14 =136, DQ15 =138
8679 00:22:23.589825
8680 00:22:23.590222
8681 00:22:23.590599
8682 00:22:23.592787 [DramC_TX_OE_Calibration] TA2
8683 00:22:23.595761 Original DQ_B0 (3 6) =30, OEN = 27
8684 00:22:23.599317 Original DQ_B1 (3 6) =30, OEN = 27
8685 00:22:23.602079 24, 0x0, End_B0=24 End_B1=24
8686 00:22:23.605791 25, 0x0, End_B0=25 End_B1=25
8687 00:22:23.606209 26, 0x0, End_B0=26 End_B1=26
8688 00:22:23.608707 27, 0x0, End_B0=27 End_B1=27
8689 00:22:23.612477 28, 0x0, End_B0=28 End_B1=28
8690 00:22:23.615424 29, 0x0, End_B0=29 End_B1=29
8691 00:22:23.618687 30, 0x0, End_B0=30 End_B1=30
8692 00:22:23.619108 31, 0x4141, End_B0=30 End_B1=30
8693 00:22:23.621935 Byte0 end_step=30 best_step=27
8694 00:22:23.625793 Byte1 end_step=30 best_step=27
8695 00:22:23.628857 Byte0 TX OE(2T, 0.5T) = (3, 3)
8696 00:22:23.633213 Byte1 TX OE(2T, 0.5T) = (3, 3)
8697 00:22:23.634036
8698 00:22:23.634595
8699 00:22:23.638653 [DQSOSCAuto] RK0, (LSB)MR18= 0xc16, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 403 ps
8700 00:22:23.641935 CH1 RK0: MR19=303, MR18=C16
8701 00:22:23.648559 CH1_RK0: MR19=0x303, MR18=0xC16, DQSOSC=398, MR23=63, INC=23, DEC=15
8702 00:22:23.648975
8703 00:22:23.651601 ----->DramcWriteLeveling(PI) begin...
8704 00:22:23.652021 ==
8705 00:22:23.654884 Dram Type= 6, Freq= 0, CH_1, rank 1
8706 00:22:23.658224 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8707 00:22:23.658666 ==
8708 00:22:23.661580 Write leveling (Byte 0): 23 => 23
8709 00:22:23.665038 Write leveling (Byte 1): 26 => 26
8710 00:22:23.668048 DramcWriteLeveling(PI) end<-----
8711 00:22:23.668582
8712 00:22:23.668939 ==
8713 00:22:23.671700 Dram Type= 6, Freq= 0, CH_1, rank 1
8714 00:22:23.677858 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8715 00:22:23.678300 ==
8716 00:22:23.678648 [Gating] SW mode calibration
8717 00:22:23.688435 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8718 00:22:23.691008 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8719 00:22:23.694738 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8720 00:22:23.701358 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8721 00:22:23.704660 1 4 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
8722 00:22:23.711210 1 4 12 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
8723 00:22:23.714304 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8724 00:22:23.717809 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8725 00:22:23.724101 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8726 00:22:23.727087 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8727 00:22:23.730200 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8728 00:22:23.737196 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8729 00:22:23.740119 1 5 8 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
8730 00:22:23.743632 1 5 12 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
8731 00:22:23.749868 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8732 00:22:23.753649 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8733 00:22:23.756934 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8734 00:22:23.763185 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8735 00:22:23.766567 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8736 00:22:23.769754 1 6 4 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
8737 00:22:23.773196 1 6 8 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8738 00:22:23.780105 1 6 12 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
8739 00:22:23.783327 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8740 00:22:23.786613 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8741 00:22:23.793229 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8742 00:22:23.796659 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8743 00:22:23.800300 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8744 00:22:23.806370 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8745 00:22:23.809808 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8746 00:22:23.815825 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8747 00:22:23.819467 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8748 00:22:23.822649 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8749 00:22:23.829101 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8750 00:22:23.832664 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8751 00:22:23.835794 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8752 00:22:23.842355 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8753 00:22:23.845615 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8754 00:22:23.849092 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8755 00:22:23.855444 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8756 00:22:23.859106 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8757 00:22:23.862481 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8758 00:22:23.868470 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8759 00:22:23.872069 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8760 00:22:23.875172 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8761 00:22:23.881536 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8762 00:22:23.884782 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8763 00:22:23.888551 Total UI for P1: 0, mck2ui 16
8764 00:22:23.891867 best dqsien dly found for B0: ( 1, 9, 6)
8765 00:22:23.894965 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8766 00:22:23.898055 Total UI for P1: 0, mck2ui 16
8767 00:22:23.901840 best dqsien dly found for B1: ( 1, 9, 10)
8768 00:22:23.904813 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8769 00:22:23.908162 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8770 00:22:23.908235
8771 00:22:23.911120 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8772 00:22:23.918138 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8773 00:22:23.918221 [Gating] SW calibration Done
8774 00:22:23.921295 ==
8775 00:22:23.924793 Dram Type= 6, Freq= 0, CH_1, rank 1
8776 00:22:23.927944 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8777 00:22:23.928026 ==
8778 00:22:23.928089 RX Vref Scan: 0
8779 00:22:23.928148
8780 00:22:23.931394 RX Vref 0 -> 0, step: 1
8781 00:22:23.931474
8782 00:22:23.934354 RX Delay 0 -> 252, step: 8
8783 00:22:23.937941 iDelay=200, Bit 0, Center 139 (80 ~ 199) 120
8784 00:22:23.941034 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8785 00:22:23.944179 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8786 00:22:23.950878 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8787 00:22:23.954610 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8788 00:22:23.958127 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8789 00:22:23.960972 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8790 00:22:23.964422 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8791 00:22:23.970763 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8792 00:22:23.974369 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8793 00:22:23.977890 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8794 00:22:23.981140 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8795 00:22:23.987419 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8796 00:22:23.990976 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8797 00:22:23.993804 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8798 00:22:23.997531 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8799 00:22:23.997987 ==
8800 00:22:24.000983 Dram Type= 6, Freq= 0, CH_1, rank 1
8801 00:22:24.007432 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8802 00:22:24.007851 ==
8803 00:22:24.008194 DQS Delay:
8804 00:22:24.010568 DQS0 = 0, DQS1 = 0
8805 00:22:24.011076 DQM Delay:
8806 00:22:24.011454 DQM0 = 134, DQM1 = 130
8807 00:22:24.013620 DQ Delay:
8808 00:22:24.017074 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =131
8809 00:22:24.020531 DQ4 =131, DQ5 =143, DQ6 =143, DQ7 =131
8810 00:22:24.023694 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8811 00:22:24.027146 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8812 00:22:24.027561
8813 00:22:24.027964
8814 00:22:24.028428 ==
8815 00:22:24.030789 Dram Type= 6, Freq= 0, CH_1, rank 1
8816 00:22:24.037207 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8817 00:22:24.037722 ==
8818 00:22:24.038053
8819 00:22:24.038360
8820 00:22:24.038653 TX Vref Scan disable
8821 00:22:24.040263 == TX Byte 0 ==
8822 00:22:24.043294 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8823 00:22:24.049924 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8824 00:22:24.050483 == TX Byte 1 ==
8825 00:22:24.053674 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8826 00:22:24.060247 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8827 00:22:24.060643 ==
8828 00:22:24.063264 Dram Type= 6, Freq= 0, CH_1, rank 1
8829 00:22:24.066266 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8830 00:22:24.066682 ==
8831 00:22:24.079184
8832 00:22:24.082279 TX Vref early break, caculate TX vref
8833 00:22:24.085688 TX Vref=16, minBit 9, minWin=22, winSum=379
8834 00:22:24.089124 TX Vref=18, minBit 9, minWin=22, winSum=389
8835 00:22:24.092070 TX Vref=20, minBit 9, minWin=22, winSum=392
8836 00:22:24.095647 TX Vref=22, minBit 9, minWin=23, winSum=402
8837 00:22:24.098801 TX Vref=24, minBit 9, minWin=24, winSum=413
8838 00:22:24.105210 TX Vref=26, minBit 9, minWin=24, winSum=417
8839 00:22:24.108528 TX Vref=28, minBit 9, minWin=24, winSum=423
8840 00:22:24.111781 TX Vref=30, minBit 8, minWin=25, winSum=423
8841 00:22:24.115376 TX Vref=32, minBit 0, minWin=24, winSum=409
8842 00:22:24.118599 TX Vref=34, minBit 9, minWin=23, winSum=400
8843 00:22:24.125494 [TxChooseVref] Worse bit 8, Min win 25, Win sum 423, Final Vref 30
8844 00:22:24.125993
8845 00:22:24.128542 Final TX Range 0 Vref 30
8846 00:22:24.128948
8847 00:22:24.129303 ==
8848 00:22:24.132139 Dram Type= 6, Freq= 0, CH_1, rank 1
8849 00:22:24.135005 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8850 00:22:24.135415 ==
8851 00:22:24.135755
8852 00:22:24.136053
8853 00:22:24.138458 TX Vref Scan disable
8854 00:22:24.144835 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8855 00:22:24.145241 == TX Byte 0 ==
8856 00:22:24.148174 u2DelayCellOfst[0]=14 cells (4 PI)
8857 00:22:24.151409 u2DelayCellOfst[1]=10 cells (3 PI)
8858 00:22:24.154753 u2DelayCellOfst[2]=0 cells (0 PI)
8859 00:22:24.158382 u2DelayCellOfst[3]=7 cells (2 PI)
8860 00:22:24.161404 u2DelayCellOfst[4]=10 cells (3 PI)
8861 00:22:24.164653 u2DelayCellOfst[5]=14 cells (4 PI)
8862 00:22:24.167926 u2DelayCellOfst[6]=17 cells (5 PI)
8863 00:22:24.171343 u2DelayCellOfst[7]=7 cells (2 PI)
8864 00:22:24.174639 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8865 00:22:24.177735 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8866 00:22:24.181351 == TX Byte 1 ==
8867 00:22:24.184393 u2DelayCellOfst[8]=0 cells (0 PI)
8868 00:22:24.187718 u2DelayCellOfst[9]=3 cells (1 PI)
8869 00:22:24.191271 u2DelayCellOfst[10]=10 cells (3 PI)
8870 00:22:24.191989 u2DelayCellOfst[11]=7 cells (2 PI)
8871 00:22:24.194539 u2DelayCellOfst[12]=14 cells (4 PI)
8872 00:22:24.197434 u2DelayCellOfst[13]=14 cells (4 PI)
8873 00:22:24.200972 u2DelayCellOfst[14]=17 cells (5 PI)
8874 00:22:24.204014 u2DelayCellOfst[15]=17 cells (5 PI)
8875 00:22:24.210491 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8876 00:22:24.214044 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8877 00:22:24.214451 DramC Write-DBI on
8878 00:22:24.217568 ==
8879 00:22:24.220347 Dram Type= 6, Freq= 0, CH_1, rank 1
8880 00:22:24.223734 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8881 00:22:24.224168 ==
8882 00:22:24.224494
8883 00:22:24.224844
8884 00:22:24.227566 TX Vref Scan disable
8885 00:22:24.228013 == TX Byte 0 ==
8886 00:22:24.233793 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8887 00:22:24.234367 == TX Byte 1 ==
8888 00:22:24.236739 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8889 00:22:24.240354 DramC Write-DBI off
8890 00:22:24.240812
8891 00:22:24.241371 [DATLAT]
8892 00:22:24.243499 Freq=1600, CH1 RK1
8893 00:22:24.243919
8894 00:22:24.244354 DATLAT Default: 0xf
8895 00:22:24.246881 0, 0xFFFF, sum = 0
8896 00:22:24.247306 1, 0xFFFF, sum = 0
8897 00:22:24.250464 2, 0xFFFF, sum = 0
8898 00:22:24.250904 3, 0xFFFF, sum = 0
8899 00:22:24.253353 4, 0xFFFF, sum = 0
8900 00:22:24.256730 5, 0xFFFF, sum = 0
8901 00:22:24.257154 6, 0xFFFF, sum = 0
8902 00:22:24.259719 7, 0xFFFF, sum = 0
8903 00:22:24.260204 8, 0xFFFF, sum = 0
8904 00:22:24.263655 9, 0xFFFF, sum = 0
8905 00:22:24.264125 10, 0xFFFF, sum = 0
8906 00:22:24.266537 11, 0xFFFF, sum = 0
8907 00:22:24.267092 12, 0xFFFF, sum = 0
8908 00:22:24.270434 13, 0xFFFF, sum = 0
8909 00:22:24.270874 14, 0x0, sum = 1
8910 00:22:24.272839 15, 0x0, sum = 2
8911 00:22:24.273300 16, 0x0, sum = 3
8912 00:22:24.276528 17, 0x0, sum = 4
8913 00:22:24.276960 best_step = 15
8914 00:22:24.277476
8915 00:22:24.277897 ==
8916 00:22:24.279566 Dram Type= 6, Freq= 0, CH_1, rank 1
8917 00:22:24.286654 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8918 00:22:24.287079 ==
8919 00:22:24.287503 RX Vref Scan: 0
8920 00:22:24.287905
8921 00:22:24.289546 RX Vref 0 -> 0, step: 1
8922 00:22:24.290012
8923 00:22:24.292961 RX Delay 19 -> 252, step: 4
8924 00:22:24.296612 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
8925 00:22:24.299432 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
8926 00:22:24.302904 iDelay=195, Bit 2, Center 120 (67 ~ 174) 108
8927 00:22:24.309628 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8928 00:22:24.312468 iDelay=195, Bit 4, Center 128 (71 ~ 186) 116
8929 00:22:24.316191 iDelay=195, Bit 5, Center 142 (91 ~ 194) 104
8930 00:22:24.319165 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8931 00:22:24.322198 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8932 00:22:24.328834 iDelay=195, Bit 8, Center 112 (59 ~ 166) 108
8933 00:22:24.332178 iDelay=195, Bit 9, Center 116 (63 ~ 170) 108
8934 00:22:24.335797 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
8935 00:22:24.339121 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8936 00:22:24.345317 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
8937 00:22:24.348692 iDelay=195, Bit 13, Center 134 (83 ~ 186) 104
8938 00:22:24.352278 iDelay=195, Bit 14, Center 132 (83 ~ 182) 100
8939 00:22:24.355433 iDelay=195, Bit 15, Center 138 (83 ~ 194) 112
8940 00:22:24.355887 ==
8941 00:22:24.358946 Dram Type= 6, Freq= 0, CH_1, rank 1
8942 00:22:24.365812 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8943 00:22:24.366242 ==
8944 00:22:24.366582 DQS Delay:
8945 00:22:24.366893 DQS0 = 0, DQS1 = 0
8946 00:22:24.368583 DQM Delay:
8947 00:22:24.368988 DQM0 = 130, DQM1 = 127
8948 00:22:24.372103 DQ Delay:
8949 00:22:24.375658 DQ0 =134, DQ1 =130, DQ2 =120, DQ3 =128
8950 00:22:24.378729 DQ4 =128, DQ5 =142, DQ6 =138, DQ7 =126
8951 00:22:24.382206 DQ8 =112, DQ9 =116, DQ10 =130, DQ11 =120
8952 00:22:24.385245 DQ12 =138, DQ13 =134, DQ14 =132, DQ15 =138
8953 00:22:24.385736
8954 00:22:24.386168
8955 00:22:24.386669
8956 00:22:24.388648 [DramC_TX_OE_Calibration] TA2
8957 00:22:24.391827 Original DQ_B0 (3 6) =30, OEN = 27
8958 00:22:24.395229 Original DQ_B1 (3 6) =30, OEN = 27
8959 00:22:24.398830 24, 0x0, End_B0=24 End_B1=24
8960 00:22:24.399241 25, 0x0, End_B0=25 End_B1=25
8961 00:22:24.401833 26, 0x0, End_B0=26 End_B1=26
8962 00:22:24.405101 27, 0x0, End_B0=27 End_B1=27
8963 00:22:24.408164 28, 0x0, End_B0=28 End_B1=28
8964 00:22:24.412123 29, 0x0, End_B0=29 End_B1=29
8965 00:22:24.412780 30, 0x0, End_B0=30 End_B1=30
8966 00:22:24.415039 31, 0x4141, End_B0=30 End_B1=30
8967 00:22:24.418664 Byte0 end_step=30 best_step=27
8968 00:22:24.421732 Byte1 end_step=30 best_step=27
8969 00:22:24.425294 Byte0 TX OE(2T, 0.5T) = (3, 3)
8970 00:22:24.428201 Byte1 TX OE(2T, 0.5T) = (3, 3)
8971 00:22:24.428676
8972 00:22:24.429044
8973 00:22:24.434864 [DQSOSCAuto] RK1, (LSB)MR18= 0x111f, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 401 ps
8974 00:22:24.438430 CH1 RK1: MR19=303, MR18=111F
8975 00:22:24.444936 CH1_RK1: MR19=0x303, MR18=0x111F, DQSOSC=394, MR23=63, INC=23, DEC=15
8976 00:22:24.447849 [RxdqsGatingPostProcess] freq 1600
8977 00:22:24.451088 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8978 00:22:24.454665 best DQS0 dly(2T, 0.5T) = (1, 1)
8979 00:22:24.458117 best DQS1 dly(2T, 0.5T) = (1, 1)
8980 00:22:24.460976 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8981 00:22:24.464694 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8982 00:22:24.467694 best DQS0 dly(2T, 0.5T) = (1, 1)
8983 00:22:24.471420 best DQS1 dly(2T, 0.5T) = (1, 1)
8984 00:22:24.474389 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8985 00:22:24.477864 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8986 00:22:24.480816 Pre-setting of DQS Precalculation
8987 00:22:24.484418 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8988 00:22:24.494060 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8989 00:22:24.500706 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8990 00:22:24.501300
8991 00:22:24.501714
8992 00:22:24.503735 [Calibration Summary] 3200 Mbps
8993 00:22:24.504301 CH 0, Rank 0
8994 00:22:24.507044 SW Impedance : PASS
8995 00:22:24.507545 DUTY Scan : NO K
8996 00:22:24.510847 ZQ Calibration : PASS
8997 00:22:24.513676 Jitter Meter : NO K
8998 00:22:24.514105 CBT Training : PASS
8999 00:22:24.517323 Write leveling : PASS
9000 00:22:24.520279 RX DQS gating : PASS
9001 00:22:24.520707 RX DQ/DQS(RDDQC) : PASS
9002 00:22:24.523684 TX DQ/DQS : PASS
9003 00:22:24.527240 RX DATLAT : PASS
9004 00:22:24.527747 RX DQ/DQS(Engine): PASS
9005 00:22:24.530360 TX OE : PASS
9006 00:22:24.530774 All Pass.
9007 00:22:24.531094
9008 00:22:24.533878 CH 0, Rank 1
9009 00:22:24.534288 SW Impedance : PASS
9010 00:22:24.536731 DUTY Scan : NO K
9011 00:22:24.540436 ZQ Calibration : PASS
9012 00:22:24.540844 Jitter Meter : NO K
9013 00:22:24.543583 CBT Training : PASS
9014 00:22:24.546813 Write leveling : PASS
9015 00:22:24.547221 RX DQS gating : PASS
9016 00:22:24.550156 RX DQ/DQS(RDDQC) : PASS
9017 00:22:24.550564 TX DQ/DQS : PASS
9018 00:22:24.553346 RX DATLAT : PASS
9019 00:22:24.556944 RX DQ/DQS(Engine): PASS
9020 00:22:24.557401 TX OE : PASS
9021 00:22:24.560237 All Pass.
9022 00:22:24.560644
9023 00:22:24.560962 CH 1, Rank 0
9024 00:22:24.563144 SW Impedance : PASS
9025 00:22:24.563552 DUTY Scan : NO K
9026 00:22:24.566546 ZQ Calibration : PASS
9027 00:22:24.570167 Jitter Meter : NO K
9028 00:22:24.570577 CBT Training : PASS
9029 00:22:24.573088 Write leveling : PASS
9030 00:22:24.576128 RX DQS gating : PASS
9031 00:22:24.576603 RX DQ/DQS(RDDQC) : PASS
9032 00:22:24.579779 TX DQ/DQS : PASS
9033 00:22:24.583411 RX DATLAT : PASS
9034 00:22:24.583837 RX DQ/DQS(Engine): PASS
9035 00:22:24.586443 TX OE : PASS
9036 00:22:24.586880 All Pass.
9037 00:22:24.587238
9038 00:22:24.589377 CH 1, Rank 1
9039 00:22:24.589944 SW Impedance : PASS
9040 00:22:24.592947 DUTY Scan : NO K
9041 00:22:24.595922 ZQ Calibration : PASS
9042 00:22:24.596339 Jitter Meter : NO K
9043 00:22:24.599091 CBT Training : PASS
9044 00:22:24.602686 Write leveling : PASS
9045 00:22:24.603096 RX DQS gating : PASS
9046 00:22:24.606302 RX DQ/DQS(RDDQC) : PASS
9047 00:22:24.609392 TX DQ/DQS : PASS
9048 00:22:24.609806 RX DATLAT : PASS
9049 00:22:24.612448 RX DQ/DQS(Engine): PASS
9050 00:22:24.616145 TX OE : PASS
9051 00:22:24.616557 All Pass.
9052 00:22:24.616881
9053 00:22:24.617185 DramC Write-DBI on
9054 00:22:24.619784 PER_BANK_REFRESH: Hybrid Mode
9055 00:22:24.623010 TX_TRACKING: ON
9056 00:22:24.628683 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9057 00:22:24.638862 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9058 00:22:24.645288 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9059 00:22:24.648872 [FAST_K] Save calibration result to emmc
9060 00:22:24.652460 sync common calibartion params.
9061 00:22:24.655358 sync cbt_mode0:1, 1:1
9062 00:22:24.655974 dram_init: ddr_geometry: 2
9063 00:22:24.658535 dram_init: ddr_geometry: 2
9064 00:22:24.662116 dram_init: ddr_geometry: 2
9065 00:22:24.664871 0:dram_rank_size:100000000
9066 00:22:24.664956 1:dram_rank_size:100000000
9067 00:22:24.671298 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9068 00:22:24.674415 DFS_SHUFFLE_HW_MODE: ON
9069 00:22:24.678337 dramc_set_vcore_voltage set vcore to 725000
9070 00:22:24.678413 Read voltage for 1600, 0
9071 00:22:24.681496 Vio18 = 0
9072 00:22:24.681579 Vcore = 725000
9073 00:22:24.681644 Vdram = 0
9074 00:22:24.684585 Vddq = 0
9075 00:22:24.684667 Vmddr = 0
9076 00:22:24.687611 switch to 3200 Mbps bootup
9077 00:22:24.687719 [DramcRunTimeConfig]
9078 00:22:24.691353 PHYPLL
9079 00:22:24.691465 DPM_CONTROL_AFTERK: ON
9080 00:22:24.694452 PER_BANK_REFRESH: ON
9081 00:22:24.697744 REFRESH_OVERHEAD_REDUCTION: ON
9082 00:22:24.697844 CMD_PICG_NEW_MODE: OFF
9083 00:22:24.701322 XRTWTW_NEW_MODE: ON
9084 00:22:24.701431 XRTRTR_NEW_MODE: ON
9085 00:22:24.704553 TX_TRACKING: ON
9086 00:22:24.704651 RDSEL_TRACKING: OFF
9087 00:22:24.707753 DQS Precalculation for DVFS: ON
9088 00:22:24.710915 RX_TRACKING: OFF
9089 00:22:24.710997 HW_GATING DBG: ON
9090 00:22:24.714400 ZQCS_ENABLE_LP4: ON
9091 00:22:24.714482 RX_PICG_NEW_MODE: ON
9092 00:22:24.717427 TX_PICG_NEW_MODE: ON
9093 00:22:24.717511 ENABLE_RX_DCM_DPHY: ON
9094 00:22:24.721123 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9095 00:22:24.724400 DUMMY_READ_FOR_TRACKING: OFF
9096 00:22:24.727944 !!! SPM_CONTROL_AFTERK: OFF
9097 00:22:24.730960 !!! SPM could not control APHY
9098 00:22:24.731043 IMPEDANCE_TRACKING: ON
9099 00:22:24.734000 TEMP_SENSOR: ON
9100 00:22:24.734111 HW_SAVE_FOR_SR: OFF
9101 00:22:24.737245 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9102 00:22:24.740737 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9103 00:22:24.743777 Read ODT Tracking: ON
9104 00:22:24.747382 Refresh Rate DeBounce: ON
9105 00:22:24.747491 DFS_NO_QUEUE_FLUSH: ON
9106 00:22:24.750632 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9107 00:22:24.753860 ENABLE_DFS_RUNTIME_MRW: OFF
9108 00:22:24.757133 DDR_RESERVE_NEW_MODE: ON
9109 00:22:24.757241 MR_CBT_SWITCH_FREQ: ON
9110 00:22:24.760776 =========================
9111 00:22:24.779335 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9112 00:22:24.782597 dram_init: ddr_geometry: 2
9113 00:22:24.801143 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9114 00:22:24.804710 dram_init: dram init end (result: 0)
9115 00:22:24.811080 DRAM-K: Full calibration passed in 24411 msecs
9116 00:22:24.814636 MRC: failed to locate region type 0.
9117 00:22:24.815050 DRAM rank0 size:0x100000000,
9118 00:22:24.817382 DRAM rank1 size=0x100000000
9119 00:22:24.827744 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9120 00:22:24.834449 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9121 00:22:24.844016 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9122 00:22:24.850640 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9123 00:22:24.851101 DRAM rank0 size:0x100000000,
9124 00:22:24.854171 DRAM rank1 size=0x100000000
9125 00:22:24.854615 CBMEM:
9126 00:22:24.856847 IMD: root @ 0xfffff000 254 entries.
9127 00:22:24.860277 IMD: root @ 0xffffec00 62 entries.
9128 00:22:24.863660 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9129 00:22:24.870392 WARNING: RO_VPD is uninitialized or empty.
9130 00:22:24.873779 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9131 00:22:24.881293 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9132 00:22:24.893971 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9133 00:22:24.905566 BS: romstage times (exec / console): total (unknown) / 23939 ms
9134 00:22:24.906040
9135 00:22:24.906402
9136 00:22:24.915244 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9137 00:22:24.918989 ARM64: Exception handlers installed.
9138 00:22:24.922301 ARM64: Testing exception
9139 00:22:24.925546 ARM64: Done test exception
9140 00:22:24.925955 Enumerating buses...
9141 00:22:24.928680 Show all devs... Before device enumeration.
9142 00:22:24.931756 Root Device: enabled 1
9143 00:22:24.935590 CPU_CLUSTER: 0: enabled 1
9144 00:22:24.936091 CPU: 00: enabled 1
9145 00:22:24.938696 Compare with tree...
9146 00:22:24.939216 Root Device: enabled 1
9147 00:22:24.941567 CPU_CLUSTER: 0: enabled 1
9148 00:22:24.944958 CPU: 00: enabled 1
9149 00:22:24.945401 Root Device scanning...
9150 00:22:24.948699 scan_static_bus for Root Device
9151 00:22:24.951434 CPU_CLUSTER: 0 enabled
9152 00:22:24.954952 scan_static_bus for Root Device done
9153 00:22:24.958582 scan_bus: bus Root Device finished in 8 msecs
9154 00:22:24.958999 done
9155 00:22:24.965056 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9156 00:22:24.967726 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9157 00:22:24.974324 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9158 00:22:24.981138 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9159 00:22:24.981675 Allocating resources...
9160 00:22:24.984188 Reading resources...
9161 00:22:24.987655 Root Device read_resources bus 0 link: 0
9162 00:22:24.991180 DRAM rank0 size:0x100000000,
9163 00:22:24.991721 DRAM rank1 size=0x100000000
9164 00:22:24.997897 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9165 00:22:24.998500 CPU: 00 missing read_resources
9166 00:22:25.004403 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9167 00:22:25.007683 Root Device read_resources bus 0 link: 0 done
9168 00:22:25.011000 Done reading resources.
9169 00:22:25.014126 Show resources in subtree (Root Device)...After reading.
9170 00:22:25.017175 Root Device child on link 0 CPU_CLUSTER: 0
9171 00:22:25.020759 CPU_CLUSTER: 0 child on link 0 CPU: 00
9172 00:22:25.030416 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9173 00:22:25.030840 CPU: 00
9174 00:22:25.036763 Root Device assign_resources, bus 0 link: 0
9175 00:22:25.040496 CPU_CLUSTER: 0 missing set_resources
9176 00:22:25.043674 Root Device assign_resources, bus 0 link: 0 done
9177 00:22:25.047032 Done setting resources.
9178 00:22:25.050206 Show resources in subtree (Root Device)...After assigning values.
9179 00:22:25.056666 Root Device child on link 0 CPU_CLUSTER: 0
9180 00:22:25.059835 CPU_CLUSTER: 0 child on link 0 CPU: 00
9181 00:22:25.066718 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9182 00:22:25.069828 CPU: 00
9183 00:22:25.070304 Done allocating resources.
9184 00:22:25.076268 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9185 00:22:25.079787 Enabling resources...
9186 00:22:25.080342 done.
9187 00:22:25.083065 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9188 00:22:25.086337 Initializing devices...
9189 00:22:25.086765 Root Device init
9190 00:22:25.089371 init hardware done!
9191 00:22:25.092916 0x00000018: ctrlr->caps
9192 00:22:25.093385 52.000 MHz: ctrlr->f_max
9193 00:22:25.095981 0.400 MHz: ctrlr->f_min
9194 00:22:25.099280 0x40ff8080: ctrlr->voltages
9195 00:22:25.099758 sclk: 390625
9196 00:22:25.100120 Bus Width = 1
9197 00:22:25.102925 sclk: 390625
9198 00:22:25.103333 Bus Width = 1
9199 00:22:25.105917 Early init status = 3
9200 00:22:25.109359 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9201 00:22:25.113405 in-header: 03 fc 00 00 01 00 00 00
9202 00:22:25.116590 in-data: 00
9203 00:22:25.119905 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9204 00:22:25.124250 in-header: 03 fd 00 00 00 00 00 00
9205 00:22:25.127491 in-data:
9206 00:22:25.130976 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9207 00:22:25.134494 in-header: 03 fc 00 00 01 00 00 00
9208 00:22:25.137838 in-data: 00
9209 00:22:25.141091 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9210 00:22:25.145735 in-header: 03 fd 00 00 00 00 00 00
9211 00:22:25.148738 in-data:
9212 00:22:25.152338 [SSUSB] Setting up USB HOST controller...
9213 00:22:25.155213 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9214 00:22:25.158894 [SSUSB] phy power-on done.
9215 00:22:25.162523 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9216 00:22:25.168629 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9217 00:22:25.171928 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9218 00:22:25.178890 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9219 00:22:25.185233 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9220 00:22:25.191763 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9221 00:22:25.198616 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9222 00:22:25.205176 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9223 00:22:25.208281 SPM: binary array size = 0x9dc
9224 00:22:25.211450 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9225 00:22:25.217973 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9226 00:22:25.225340 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9227 00:22:25.231705 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9228 00:22:25.234725 configure_display: Starting display init
9229 00:22:25.268756 anx7625_power_on_init: Init interface.
9230 00:22:25.272370 anx7625_disable_pd_protocol: Disabled PD feature.
9231 00:22:25.275616 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9232 00:22:25.303266 anx7625_start_dp_work: Secure OCM version=00
9233 00:22:25.306667 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9234 00:22:25.321472 sp_tx_get_edid_block: EDID Block = 1
9235 00:22:25.424307 Extracted contents:
9236 00:22:25.427330 header: 00 ff ff ff ff ff ff 00
9237 00:22:25.430549 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9238 00:22:25.434069 version: 01 04
9239 00:22:25.437240 basic params: 95 1f 11 78 0a
9240 00:22:25.440190 chroma info: 76 90 94 55 54 90 27 21 50 54
9241 00:22:25.443602 established: 00 00 00
9242 00:22:25.450068 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9243 00:22:25.456831 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9244 00:22:25.460375 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9245 00:22:25.466968 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9246 00:22:25.473038 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9247 00:22:25.476708 extensions: 00
9248 00:22:25.477127 checksum: fb
9249 00:22:25.477595
9250 00:22:25.483158 Manufacturer: IVO Model 57d Serial Number 0
9251 00:22:25.483684 Made week 0 of 2020
9252 00:22:25.486353 EDID version: 1.4
9253 00:22:25.486897 Digital display
9254 00:22:25.489708 6 bits per primary color channel
9255 00:22:25.490134 DisplayPort interface
9256 00:22:25.493229 Maximum image size: 31 cm x 17 cm
9257 00:22:25.496192 Gamma: 220%
9258 00:22:25.496610 Check DPMS levels
9259 00:22:25.502831 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9260 00:22:25.506416 First detailed timing is preferred timing
9261 00:22:25.506986 Established timings supported:
9262 00:22:25.509585 Standard timings supported:
9263 00:22:25.512972 Detailed timings
9264 00:22:25.516492 Hex of detail: 383680a07038204018303c0035ae10000019
9265 00:22:25.523050 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9266 00:22:25.526501 0780 0798 07c8 0820 hborder 0
9267 00:22:25.529707 0438 043b 0447 0458 vborder 0
9268 00:22:25.532959 -hsync -vsync
9269 00:22:25.533470 Did detailed timing
9270 00:22:25.539344 Hex of detail: 000000000000000000000000000000000000
9271 00:22:25.542870 Manufacturer-specified data, tag 0
9272 00:22:25.546033 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9273 00:22:25.549322 ASCII string: InfoVision
9274 00:22:25.552391 Hex of detail: 000000fe00523134304e574635205248200a
9275 00:22:25.555876 ASCII string: R140NWF5 RH
9276 00:22:25.556420 Checksum
9277 00:22:25.559522 Checksum: 0xfb (valid)
9278 00:22:25.562436 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9279 00:22:25.565996 DSI data_rate: 832800000 bps
9280 00:22:25.572571 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9281 00:22:25.575698 anx7625_parse_edid: pixelclock(138800).
9282 00:22:25.579120 hactive(1920), hsync(48), hfp(24), hbp(88)
9283 00:22:25.582373 vactive(1080), vsync(12), vfp(3), vbp(17)
9284 00:22:25.585650 anx7625_dsi_config: config dsi.
9285 00:22:25.592249 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9286 00:22:25.605477 anx7625_dsi_config: success to config DSI
9287 00:22:25.609215 anx7625_dp_start: MIPI phy setup OK.
9288 00:22:25.612245 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9289 00:22:25.615255 mtk_ddp_mode_set invalid vrefresh 60
9290 00:22:25.618771 main_disp_path_setup
9291 00:22:25.618861 ovl_layer_smi_id_en
9292 00:22:25.621994 ovl_layer_smi_id_en
9293 00:22:25.622074 ccorr_config
9294 00:22:25.622135 aal_config
9295 00:22:25.625539 gamma_config
9296 00:22:25.625617 postmask_config
9297 00:22:25.628809 dither_config
9298 00:22:25.632285 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9299 00:22:25.638507 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9300 00:22:25.641892 Root Device init finished in 551 msecs
9301 00:22:25.645452 CPU_CLUSTER: 0 init
9302 00:22:25.651547 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9303 00:22:25.658348 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9304 00:22:25.658755 APU_MBOX 0x190000b0 = 0x10001
9305 00:22:25.661858 APU_MBOX 0x190001b0 = 0x10001
9306 00:22:25.665004 APU_MBOX 0x190005b0 = 0x10001
9307 00:22:25.668630 APU_MBOX 0x190006b0 = 0x10001
9308 00:22:25.675152 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9309 00:22:25.684722 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9310 00:22:25.697234 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9311 00:22:25.703922 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9312 00:22:25.715660 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9313 00:22:25.724746 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9314 00:22:25.728005 CPU_CLUSTER: 0 init finished in 81 msecs
9315 00:22:25.731129 Devices initialized
9316 00:22:25.734789 Show all devs... After init.
9317 00:22:25.735195 Root Device: enabled 1
9318 00:22:25.737770 CPU_CLUSTER: 0: enabled 1
9319 00:22:25.741022 CPU: 00: enabled 1
9320 00:22:25.744375 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9321 00:22:25.747625 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9322 00:22:25.750876 ELOG: NV offset 0x57f000 size 0x1000
9323 00:22:25.757888 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9324 00:22:25.764180 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9325 00:22:25.767759 ELOG: Event(17) added with size 13 at 2024-06-21 00:22:25 UTC
9326 00:22:25.774552 out: cmd=0x121: 03 db 21 01 00 00 00 00
9327 00:22:25.777573 in-header: 03 03 00 00 2c 00 00 00
9328 00:22:25.787814 in-data: 3a 72 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9329 00:22:25.794437 ELOG: Event(A1) added with size 10 at 2024-06-21 00:22:25 UTC
9330 00:22:25.801125 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9331 00:22:25.807005 ELOG: Event(A0) added with size 9 at 2024-06-21 00:22:25 UTC
9332 00:22:25.810841 elog_add_boot_reason: Logged dev mode boot
9333 00:22:25.817156 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9334 00:22:25.817645 Finalize devices...
9335 00:22:25.820156 Devices finalized
9336 00:22:25.823853 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9337 00:22:25.827420 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9338 00:22:25.830257 in-header: 03 07 00 00 08 00 00 00
9339 00:22:25.833465 in-data: aa e4 47 04 13 02 00 00
9340 00:22:25.837157 Chrome EC: UHEPI supported
9341 00:22:25.843297 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9342 00:22:25.847033 in-header: 03 a9 00 00 08 00 00 00
9343 00:22:25.850231 in-data: 84 60 60 08 00 00 00 00
9344 00:22:25.856852 ELOG: Event(91) added with size 10 at 2024-06-21 00:22:26 UTC
9345 00:22:25.859888 Chrome EC: clear events_b mask to 0x0000000020004000
9346 00:22:25.866530 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9347 00:22:25.870114 in-header: 03 fd 00 00 00 00 00 00
9348 00:22:25.873363 in-data:
9349 00:22:25.876826 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9350 00:22:25.879913 Writing coreboot table at 0xffe64000
9351 00:22:25.886555 0. 000000000010a000-0000000000113fff: RAMSTAGE
9352 00:22:25.890168 1. 0000000040000000-00000000400fffff: RAM
9353 00:22:25.893222 2. 0000000040100000-000000004032afff: RAMSTAGE
9354 00:22:25.896739 3. 000000004032b000-00000000545fffff: RAM
9355 00:22:25.899737 4. 0000000054600000-000000005465ffff: BL31
9356 00:22:25.906219 5. 0000000054660000-00000000ffe63fff: RAM
9357 00:22:25.909745 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9358 00:22:25.913118 7. 0000000100000000-000000023fffffff: RAM
9359 00:22:25.916296 Passing 5 GPIOs to payload:
9360 00:22:25.919593 NAME | PORT | POLARITY | VALUE
9361 00:22:25.926163 EC in RW | 0x000000aa | low | undefined
9362 00:22:25.929854 EC interrupt | 0x00000005 | low | undefined
9363 00:22:25.936357 TPM interrupt | 0x000000ab | high | undefined
9364 00:22:25.939401 SD card detect | 0x00000011 | high | undefined
9365 00:22:25.946062 speaker enable | 0x00000093 | high | undefined
9366 00:22:25.949369 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9367 00:22:25.952918 in-header: 03 f9 00 00 02 00 00 00
9368 00:22:25.953429 in-data: 02 00
9369 00:22:25.955670 ADC[4]: Raw value=902586 ID=7
9370 00:22:25.959275 ADC[3]: Raw value=213177 ID=1
9371 00:22:25.959684 RAM Code: 0x71
9372 00:22:25.962135 ADC[6]: Raw value=74630 ID=0
9373 00:22:25.966015 ADC[5]: Raw value=213546 ID=1
9374 00:22:25.966427 SKU Code: 0x1
9375 00:22:25.972167 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum e31f
9376 00:22:25.975548 coreboot table: 964 bytes.
9377 00:22:25.979070 IMD ROOT 0. 0xfffff000 0x00001000
9378 00:22:25.982369 IMD SMALL 1. 0xffffe000 0x00001000
9379 00:22:25.985779 RO MCACHE 2. 0xffffc000 0x00001104
9380 00:22:25.988873 CONSOLE 3. 0xfff7c000 0x00080000
9381 00:22:25.991948 FMAP 4. 0xfff7b000 0x00000452
9382 00:22:25.995109 TIME STAMP 5. 0xfff7a000 0x00000910
9383 00:22:25.998118 VBOOT WORK 6. 0xfff66000 0x00014000
9384 00:22:26.001780 RAMOOPS 7. 0xffe66000 0x00100000
9385 00:22:26.004590 COREBOOT 8. 0xffe64000 0x00002000
9386 00:22:26.004679 IMD small region:
9387 00:22:26.008336 IMD ROOT 0. 0xffffec00 0x00000400
9388 00:22:26.011234 VPD 1. 0xffffeb80 0x0000006c
9389 00:22:26.014700 MMC STATUS 2. 0xffffeb60 0x00000004
9390 00:22:26.020880 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9391 00:22:26.028045 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9392 00:22:26.066996 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9393 00:22:26.070065 Checking segment from ROM address 0x40100000
9394 00:22:26.076729 Checking segment from ROM address 0x4010001c
9395 00:22:26.080223 Loading segment from ROM address 0x40100000
9396 00:22:26.080321 code (compression=0)
9397 00:22:26.089644 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9398 00:22:26.096762 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9399 00:22:26.099977 it's not compressed!
9400 00:22:26.103133 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9401 00:22:26.109585 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9402 00:22:26.127468 Loading segment from ROM address 0x4010001c
9403 00:22:26.127548 Entry Point 0x80000000
9404 00:22:26.131017 Loaded segments
9405 00:22:26.134292 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9406 00:22:26.140644 Jumping to boot code at 0x80000000(0xffe64000)
9407 00:22:26.147210 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9408 00:22:26.153203 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9409 00:22:26.161609 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9410 00:22:26.165206 Checking segment from ROM address 0x40100000
9411 00:22:26.168191 Checking segment from ROM address 0x4010001c
9412 00:22:26.174805 Loading segment from ROM address 0x40100000
9413 00:22:26.174924 code (compression=1)
9414 00:22:26.181379 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9415 00:22:26.191175 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9416 00:22:26.191255 using LZMA
9417 00:22:26.200395 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9418 00:22:26.206768 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9419 00:22:26.209926 Loading segment from ROM address 0x4010001c
9420 00:22:26.213131 Entry Point 0x54601000
9421 00:22:26.213245 Loaded segments
9422 00:22:26.216431 NOTICE: MT8192 bl31_setup
9423 00:22:26.223599 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9424 00:22:26.227022 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9425 00:22:26.230102 WARNING: region 0:
9426 00:22:26.233727 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9427 00:22:26.233864 WARNING: region 1:
9428 00:22:26.240213 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9429 00:22:26.243619 WARNING: region 2:
9430 00:22:26.247082 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9431 00:22:26.250041 WARNING: region 3:
9432 00:22:26.256733 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9433 00:22:26.257227 WARNING: region 4:
9434 00:22:26.263331 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9435 00:22:26.263741 WARNING: region 5:
9436 00:22:26.269940 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9437 00:22:26.270347 WARNING: region 6:
9438 00:22:26.273045 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9439 00:22:26.276466 WARNING: region 7:
9440 00:22:26.279860 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9441 00:22:26.286651 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9442 00:22:26.289744 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9443 00:22:26.296273 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9444 00:22:26.299773 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9445 00:22:26.303123 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9446 00:22:26.309597 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9447 00:22:26.312863 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9448 00:22:26.316308 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9449 00:22:26.322928 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9450 00:22:26.326186 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9451 00:22:26.332861 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9452 00:22:26.335987 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9453 00:22:26.339497 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9454 00:22:26.345731 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9455 00:22:26.349234 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9456 00:22:26.355609 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9457 00:22:26.359032 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9458 00:22:26.362307 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9459 00:22:26.368774 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9460 00:22:26.372295 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9461 00:22:26.378663 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9462 00:22:26.382188 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9463 00:22:26.385665 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9464 00:22:26.391909 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9465 00:22:26.395119 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9466 00:22:26.402160 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9467 00:22:26.405062 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9468 00:22:26.408679 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9469 00:22:26.415216 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9470 00:22:26.418775 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9471 00:22:26.424666 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9472 00:22:26.428304 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9473 00:22:26.431576 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9474 00:22:26.437992 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9475 00:22:26.441601 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9476 00:22:26.444348 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9477 00:22:26.448000 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9478 00:22:26.454506 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9479 00:22:26.457853 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9480 00:22:26.461190 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9481 00:22:26.464745 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9482 00:22:26.470570 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9483 00:22:26.474082 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9484 00:22:26.477139 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9485 00:22:26.483875 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9486 00:22:26.487731 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9487 00:22:26.490398 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9488 00:22:26.493889 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9489 00:22:26.500320 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9490 00:22:26.503575 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9491 00:22:26.510112 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9492 00:22:26.513425 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9493 00:22:26.520287 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9494 00:22:26.523649 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9495 00:22:26.526741 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9496 00:22:26.533490 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9497 00:22:26.536719 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9498 00:22:26.543211 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9499 00:22:26.546335 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9500 00:22:26.553595 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9501 00:22:26.556421 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9502 00:22:26.562995 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9503 00:22:26.566419 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9504 00:22:26.572490 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9505 00:22:26.576288 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9506 00:22:26.579114 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9507 00:22:26.586078 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9508 00:22:26.589092 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9509 00:22:26.595341 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9510 00:22:26.599192 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9511 00:22:26.605079 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9512 00:22:26.608292 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9513 00:22:26.615123 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9514 00:22:26.618380 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9515 00:22:26.621762 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9516 00:22:26.628396 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9517 00:22:26.632176 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9518 00:22:26.638136 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9519 00:22:26.641358 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9520 00:22:26.648329 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9521 00:22:26.651593 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9522 00:22:26.658229 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9523 00:22:26.661224 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9524 00:22:26.667894 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9525 00:22:26.671464 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9526 00:22:26.674965 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9527 00:22:26.681273 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9528 00:22:26.684140 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9529 00:22:26.690704 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9530 00:22:26.694141 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9531 00:22:26.700666 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9532 00:22:26.704281 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9533 00:22:26.710916 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9534 00:22:26.713835 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9535 00:22:26.717550 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9536 00:22:26.723653 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9537 00:22:26.727510 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9538 00:22:26.730803 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9539 00:22:26.737465 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9540 00:22:26.740451 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9541 00:22:26.743908 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9542 00:22:26.750337 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9543 00:22:26.753936 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9544 00:22:26.760185 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9545 00:22:26.763610 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9546 00:22:26.766623 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9547 00:22:26.773286 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9548 00:22:26.776822 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9549 00:22:26.783173 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9550 00:22:26.786432 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9551 00:22:26.789733 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9552 00:22:26.796267 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9553 00:22:26.799825 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9554 00:22:26.806143 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9555 00:22:26.809731 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9556 00:22:26.812709 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9557 00:22:26.819342 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9558 00:22:26.822830 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9559 00:22:26.825804 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9560 00:22:26.832408 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9561 00:22:26.836011 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9562 00:22:26.839372 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9563 00:22:26.842831 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9564 00:22:26.849381 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9565 00:22:26.852304 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9566 00:22:26.855614 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9567 00:22:26.862464 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9568 00:22:26.865858 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9569 00:22:26.872470 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9570 00:22:26.875375 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9571 00:22:26.879312 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9572 00:22:26.885742 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9573 00:22:26.888648 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9574 00:22:26.895341 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9575 00:22:26.898853 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9576 00:22:26.902232 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9577 00:22:26.908538 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9578 00:22:26.911636 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9579 00:22:26.918347 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9580 00:22:26.921948 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9581 00:22:26.925016 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9582 00:22:26.931456 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9583 00:22:26.935004 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9584 00:22:26.941378 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9585 00:22:26.944558 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9586 00:22:26.948074 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9587 00:22:26.954333 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9588 00:22:26.957894 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9589 00:22:26.964286 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9590 00:22:26.967495 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9591 00:22:26.974143 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9592 00:22:26.977351 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9593 00:22:26.981046 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9594 00:22:26.987328 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9595 00:22:26.991046 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9596 00:22:26.994007 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9597 00:22:27.000483 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9598 00:22:27.003720 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9599 00:22:27.010612 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9600 00:22:27.014156 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9601 00:22:27.020499 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9602 00:22:27.023553 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9603 00:22:27.027327 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9604 00:22:27.033315 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9605 00:22:27.036908 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9606 00:22:27.040252 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9607 00:22:27.046709 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9608 00:22:27.050176 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9609 00:22:27.056976 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9610 00:22:27.059948 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9611 00:22:27.066759 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9612 00:22:27.069752 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9613 00:22:27.073145 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9614 00:22:27.079645 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9615 00:22:27.082991 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9616 00:22:27.086572 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9617 00:22:27.093136 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9618 00:22:27.096164 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9619 00:22:27.102617 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9620 00:22:27.106297 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9621 00:22:27.109158 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9622 00:22:27.115975 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9623 00:22:27.119314 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9624 00:22:27.125915 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9625 00:22:27.128879 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9626 00:22:27.135591 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9627 00:22:27.139378 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9628 00:22:27.142050 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9629 00:22:27.149092 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9630 00:22:27.152036 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9631 00:22:27.158895 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9632 00:22:27.162269 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9633 00:22:27.168817 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9634 00:22:27.171729 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9635 00:22:27.175468 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9636 00:22:27.181929 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9637 00:22:27.185043 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9638 00:22:27.191821 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9639 00:22:27.194730 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9640 00:22:27.201392 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9641 00:22:27.204903 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9642 00:22:27.208332 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9643 00:22:27.214992 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9644 00:22:27.218036 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9645 00:22:27.224340 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9646 00:22:27.227888 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9647 00:22:27.234116 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9648 00:22:27.237551 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9649 00:22:27.241215 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9650 00:22:27.247611 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9651 00:22:27.251221 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9652 00:22:27.257668 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9653 00:22:27.260834 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9654 00:22:27.267894 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9655 00:22:27.270663 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9656 00:22:27.274107 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9657 00:22:27.280403 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9658 00:22:27.283972 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9659 00:22:27.290381 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9660 00:22:27.293763 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9661 00:22:27.300502 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9662 00:22:27.303501 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9663 00:22:27.307067 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9664 00:22:27.313117 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9665 00:22:27.316832 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9666 00:22:27.323534 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9667 00:22:27.326585 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9668 00:22:27.333170 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9669 00:22:27.336563 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9670 00:22:27.339919 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9671 00:22:27.343136 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9672 00:22:27.349750 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9673 00:22:27.353025 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9674 00:22:27.356750 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9675 00:22:27.359507 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9676 00:22:27.366110 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9677 00:22:27.369296 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9678 00:22:27.376395 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9679 00:22:27.379425 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9680 00:22:27.382336 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9681 00:22:27.389058 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9682 00:22:27.392554 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9683 00:22:27.399236 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9684 00:22:27.402135 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9685 00:22:27.405661 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9686 00:22:27.412233 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9687 00:22:27.415761 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9688 00:22:27.419088 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9689 00:22:27.425418 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9690 00:22:27.428415 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9691 00:22:27.431964 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9692 00:22:27.438520 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9693 00:22:27.442097 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9694 00:22:27.448285 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9695 00:22:27.451654 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9696 00:22:27.454967 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9697 00:22:27.462054 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9698 00:22:27.464620 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9699 00:22:27.468327 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9700 00:22:27.474856 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9701 00:22:27.478094 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9702 00:22:27.485083 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9703 00:22:27.487892 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9704 00:22:27.491421 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9705 00:22:27.497845 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9706 00:22:27.501168 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9707 00:22:27.507582 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9708 00:22:27.511143 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9709 00:22:27.514421 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9710 00:22:27.517442 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9711 00:22:27.524397 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9712 00:22:27.527621 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9713 00:22:27.530623 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9714 00:22:27.534203 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9715 00:22:27.540998 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9716 00:22:27.543962 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9717 00:22:27.547451 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9718 00:22:27.550412 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9719 00:22:27.556941 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9720 00:22:27.560257 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9721 00:22:27.563938 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9722 00:22:27.570441 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9723 00:22:27.573499 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9724 00:22:27.577033 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9725 00:22:27.583325 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9726 00:22:27.586813 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9727 00:22:27.593440 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9728 00:22:27.596747 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9729 00:22:27.602935 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9730 00:22:27.606167 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9731 00:22:27.609592 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9732 00:22:27.616260 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9733 00:22:27.619656 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9734 00:22:27.626218 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9735 00:22:27.630001 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9736 00:22:27.635996 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9737 00:22:27.639184 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9738 00:22:27.642664 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9739 00:22:27.649281 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9740 00:22:27.652455 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9741 00:22:27.659519 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9742 00:22:27.662550 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9743 00:22:27.666112 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9744 00:22:27.672694 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9745 00:22:27.675868 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9746 00:22:27.682436 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9747 00:22:27.685914 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9748 00:22:27.692592 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9749 00:22:27.695492 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9750 00:22:27.699010 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9751 00:22:27.705463 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9752 00:22:27.708456 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9753 00:22:27.715324 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9754 00:22:27.718471 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9755 00:22:27.722061 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9756 00:22:27.728434 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9757 00:22:27.731394 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9758 00:22:27.738482 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9759 00:22:27.741387 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9760 00:22:27.748052 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9761 00:22:27.751482 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9762 00:22:27.754482 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9763 00:22:27.761181 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9764 00:22:27.764637 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9765 00:22:27.771296 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9766 00:22:27.774245 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9767 00:22:27.778051 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9768 00:22:27.784457 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9769 00:22:27.787431 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9770 00:22:27.794531 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9771 00:22:27.797567 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9772 00:22:27.804364 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9773 00:22:27.807205 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9774 00:22:27.810871 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9775 00:22:27.817706 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9776 00:22:27.820715 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9777 00:22:27.827130 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9778 00:22:27.830592 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9779 00:22:27.833812 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9780 00:22:27.840922 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9781 00:22:27.843759 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9782 00:22:27.850650 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9783 00:22:27.853716 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9784 00:22:27.860265 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9785 00:22:27.863598 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9786 00:22:27.866820 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9787 00:22:27.873918 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9788 00:22:27.876807 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9789 00:22:27.883478 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9790 00:22:27.886365 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9791 00:22:27.892968 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9792 00:22:27.896502 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9793 00:22:27.899594 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9794 00:22:27.906183 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9795 00:22:27.909703 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9796 00:22:27.916382 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9797 00:22:27.919283 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9798 00:22:27.926256 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9799 00:22:27.929103 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9800 00:22:27.935777 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9801 00:22:27.939241 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9802 00:22:27.942364 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9803 00:22:27.948893 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9804 00:22:27.952227 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9805 00:22:27.958846 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9806 00:22:27.962159 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9807 00:22:27.968573 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9808 00:22:27.971853 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9809 00:22:27.978531 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9810 00:22:27.982140 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9811 00:22:27.985173 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9812 00:22:27.991739 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9813 00:22:27.994874 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9814 00:22:28.001507 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9815 00:22:28.005066 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9816 00:22:28.011877 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9817 00:22:28.014598 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9818 00:22:28.018201 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9819 00:22:28.024627 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9820 00:22:28.028225 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9821 00:22:28.034347 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9822 00:22:28.037820 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9823 00:22:28.044616 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9824 00:22:28.047988 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9825 00:22:28.054276 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9826 00:22:28.057791 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9827 00:22:28.063881 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9828 00:22:28.067653 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9829 00:22:28.071099 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9830 00:22:28.077156 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9831 00:22:28.080848 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9832 00:22:28.087666 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9833 00:22:28.090461 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9834 00:22:28.097163 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9835 00:22:28.100475 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9836 00:22:28.107391 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9837 00:22:28.110380 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9838 00:22:28.114078 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9839 00:22:28.119911 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9840 00:22:28.123520 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9841 00:22:28.129807 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9842 00:22:28.133253 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9843 00:22:28.139696 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9844 00:22:28.143235 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9845 00:22:28.146339 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9846 00:22:28.152866 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9847 00:22:28.156403 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9848 00:22:28.163018 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9849 00:22:28.166538 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9850 00:22:28.172893 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9851 00:22:28.176266 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9852 00:22:28.183005 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9853 00:22:28.186059 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9854 00:22:28.192613 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9855 00:22:28.196387 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9856 00:22:28.202447 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9857 00:22:28.206209 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9858 00:22:28.212289 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9859 00:22:28.215777 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9860 00:22:28.222586 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9861 00:22:28.225680 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9862 00:22:28.232180 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9863 00:22:28.235607 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9864 00:22:28.242071 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9865 00:22:28.245559 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9866 00:22:28.251623 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9867 00:22:28.255339 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9868 00:22:28.261877 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9869 00:22:28.265186 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9870 00:22:28.271214 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9871 00:22:28.277933 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9872 00:22:28.281712 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9873 00:22:28.288063 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9874 00:22:28.291415 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9875 00:22:28.294506 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9876 00:22:28.298038 INFO: [APUAPC] vio 0
9877 00:22:28.301165 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9878 00:22:28.307592 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9879 00:22:28.311029 INFO: [APUAPC] D0_APC_0: 0x400510
9880 00:22:28.314155 INFO: [APUAPC] D0_APC_1: 0x0
9881 00:22:28.317586 INFO: [APUAPC] D0_APC_2: 0x1540
9882 00:22:28.321097 INFO: [APUAPC] D0_APC_3: 0x0
9883 00:22:28.324403 INFO: [APUAPC] D1_APC_0: 0xffffffff
9884 00:22:28.327160 INFO: [APUAPC] D1_APC_1: 0xffffffff
9885 00:22:28.330796 INFO: [APUAPC] D1_APC_2: 0x3fffff
9886 00:22:28.330896 INFO: [APUAPC] D1_APC_3: 0x0
9887 00:22:28.337236 INFO: [APUAPC] D2_APC_0: 0xffffffff
9888 00:22:28.340570 INFO: [APUAPC] D2_APC_1: 0xffffffff
9889 00:22:28.343980 INFO: [APUAPC] D2_APC_2: 0x3fffff
9890 00:22:28.344085 INFO: [APUAPC] D2_APC_3: 0x0
9891 00:22:28.347083 INFO: [APUAPC] D3_APC_0: 0xffffffff
9892 00:22:28.353632 INFO: [APUAPC] D3_APC_1: 0xffffffff
9893 00:22:28.357128 INFO: [APUAPC] D3_APC_2: 0x3fffff
9894 00:22:28.357220 INFO: [APUAPC] D3_APC_3: 0x0
9895 00:22:28.360857 INFO: [APUAPC] D4_APC_0: 0xffffffff
9896 00:22:28.363731 INFO: [APUAPC] D4_APC_1: 0xffffffff
9897 00:22:28.366853 INFO: [APUAPC] D4_APC_2: 0x3fffff
9898 00:22:28.370390 INFO: [APUAPC] D4_APC_3: 0x0
9899 00:22:28.373898 INFO: [APUAPC] D5_APC_0: 0xffffffff
9900 00:22:28.376639 INFO: [APUAPC] D5_APC_1: 0xffffffff
9901 00:22:28.380060 INFO: [APUAPC] D5_APC_2: 0x3fffff
9902 00:22:28.383842 INFO: [APUAPC] D5_APC_3: 0x0
9903 00:22:28.386779 INFO: [APUAPC] D6_APC_0: 0xffffffff
9904 00:22:28.390246 INFO: [APUAPC] D6_APC_1: 0xffffffff
9905 00:22:28.394012 INFO: [APUAPC] D6_APC_2: 0x3fffff
9906 00:22:28.396492 INFO: [APUAPC] D6_APC_3: 0x0
9907 00:22:28.400292 INFO: [APUAPC] D7_APC_0: 0xffffffff
9908 00:22:28.403463 INFO: [APUAPC] D7_APC_1: 0xffffffff
9909 00:22:28.406630 INFO: [APUAPC] D7_APC_2: 0x3fffff
9910 00:22:28.409763 INFO: [APUAPC] D7_APC_3: 0x0
9911 00:22:28.413204 INFO: [APUAPC] D8_APC_0: 0xffffffff
9912 00:22:28.416603 INFO: [APUAPC] D8_APC_1: 0xffffffff
9913 00:22:28.419598 INFO: [APUAPC] D8_APC_2: 0x3fffff
9914 00:22:28.422979 INFO: [APUAPC] D8_APC_3: 0x0
9915 00:22:28.426533 INFO: [APUAPC] D9_APC_0: 0xffffffff
9916 00:22:28.429427 INFO: [APUAPC] D9_APC_1: 0xffffffff
9917 00:22:28.433288 INFO: [APUAPC] D9_APC_2: 0x3fffff
9918 00:22:28.436211 INFO: [APUAPC] D9_APC_3: 0x0
9919 00:22:28.439669 INFO: [APUAPC] D10_APC_0: 0xffffffff
9920 00:22:28.443190 INFO: [APUAPC] D10_APC_1: 0xffffffff
9921 00:22:28.446314 INFO: [APUAPC] D10_APC_2: 0x3fffff
9922 00:22:28.449420 INFO: [APUAPC] D10_APC_3: 0x0
9923 00:22:28.452401 INFO: [APUAPC] D11_APC_0: 0xffffffff
9924 00:22:28.456703 INFO: [APUAPC] D11_APC_1: 0xffffffff
9925 00:22:28.459631 INFO: [APUAPC] D11_APC_2: 0x3fffff
9926 00:22:28.463397 INFO: [APUAPC] D11_APC_3: 0x0
9927 00:22:28.465888 INFO: [APUAPC] D12_APC_0: 0xffffffff
9928 00:22:28.468941 INFO: [APUAPC] D12_APC_1: 0xffffffff
9929 00:22:28.472400 INFO: [APUAPC] D12_APC_2: 0x3fffff
9930 00:22:28.475500 INFO: [APUAPC] D12_APC_3: 0x0
9931 00:22:28.478990 INFO: [APUAPC] D13_APC_0: 0xffffffff
9932 00:22:28.482332 INFO: [APUAPC] D13_APC_1: 0xffffffff
9933 00:22:28.485884 INFO: [APUAPC] D13_APC_2: 0x3fffff
9934 00:22:28.488958 INFO: [APUAPC] D13_APC_3: 0x0
9935 00:22:28.492447 INFO: [APUAPC] D14_APC_0: 0xffffffff
9936 00:22:28.495451 INFO: [APUAPC] D14_APC_1: 0xffffffff
9937 00:22:28.499258 INFO: [APUAPC] D14_APC_2: 0x3fffff
9938 00:22:28.502011 INFO: [APUAPC] D14_APC_3: 0x0
9939 00:22:28.505447 INFO: [APUAPC] D15_APC_0: 0xffffffff
9940 00:22:28.508639 INFO: [APUAPC] D15_APC_1: 0xffffffff
9941 00:22:28.515202 INFO: [APUAPC] D15_APC_2: 0x3fffff
9942 00:22:28.515284 INFO: [APUAPC] D15_APC_3: 0x0
9943 00:22:28.518873 INFO: [APUAPC] APC_CON: 0x4
9944 00:22:28.521664 INFO: [NOCDAPC] D0_APC_0: 0x0
9945 00:22:28.525129 INFO: [NOCDAPC] D0_APC_1: 0x0
9946 00:22:28.528172 INFO: [NOCDAPC] D1_APC_0: 0x0
9947 00:22:28.531881 INFO: [NOCDAPC] D1_APC_1: 0xfff
9948 00:22:28.534696 INFO: [NOCDAPC] D2_APC_0: 0x0
9949 00:22:28.538295 INFO: [NOCDAPC] D2_APC_1: 0xfff
9950 00:22:28.541409 INFO: [NOCDAPC] D3_APC_0: 0x0
9951 00:22:28.544867 INFO: [NOCDAPC] D3_APC_1: 0xfff
9952 00:22:28.544939 INFO: [NOCDAPC] D4_APC_0: 0x0
9953 00:22:28.548396 INFO: [NOCDAPC] D4_APC_1: 0xfff
9954 00:22:28.551465 INFO: [NOCDAPC] D5_APC_0: 0x0
9955 00:22:28.554522 INFO: [NOCDAPC] D5_APC_1: 0xfff
9956 00:22:28.557938 INFO: [NOCDAPC] D6_APC_0: 0x0
9957 00:22:28.561388 INFO: [NOCDAPC] D6_APC_1: 0xfff
9958 00:22:28.565016 INFO: [NOCDAPC] D7_APC_0: 0x0
9959 00:22:28.568499 INFO: [NOCDAPC] D7_APC_1: 0xfff
9960 00:22:28.571529 INFO: [NOCDAPC] D8_APC_0: 0x0
9961 00:22:28.574371 INFO: [NOCDAPC] D8_APC_1: 0xfff
9962 00:22:28.577675 INFO: [NOCDAPC] D9_APC_0: 0x0
9963 00:22:28.577756 INFO: [NOCDAPC] D9_APC_1: 0xfff
9964 00:22:28.581040 INFO: [NOCDAPC] D10_APC_0: 0x0
9965 00:22:28.584506 INFO: [NOCDAPC] D10_APC_1: 0xfff
9966 00:22:28.587928 INFO: [NOCDAPC] D11_APC_0: 0x0
9967 00:22:28.591175 INFO: [NOCDAPC] D11_APC_1: 0xfff
9968 00:22:28.594272 INFO: [NOCDAPC] D12_APC_0: 0x0
9969 00:22:28.597844 INFO: [NOCDAPC] D12_APC_1: 0xfff
9970 00:22:28.600763 INFO: [NOCDAPC] D13_APC_0: 0x0
9971 00:22:28.604360 INFO: [NOCDAPC] D13_APC_1: 0xfff
9972 00:22:28.607500 INFO: [NOCDAPC] D14_APC_0: 0x0
9973 00:22:28.610857 INFO: [NOCDAPC] D14_APC_1: 0xfff
9974 00:22:28.614305 INFO: [NOCDAPC] D15_APC_0: 0x0
9975 00:22:28.617242 INFO: [NOCDAPC] D15_APC_1: 0xfff
9976 00:22:28.620839 INFO: [NOCDAPC] APC_CON: 0x4
9977 00:22:28.624016 INFO: [APUAPC] set_apusys_apc done
9978 00:22:28.627187 INFO: [DEVAPC] devapc_init done
9979 00:22:28.630667 INFO: GICv3 without legacy support detected.
9980 00:22:28.633753 INFO: ARM GICv3 driver initialized in EL3
9981 00:22:28.637153 INFO: Maximum SPI INTID supported: 639
9982 00:22:28.640145 INFO: BL31: Initializing runtime services
9983 00:22:28.646829 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9984 00:22:28.650122 INFO: SPM: enable CPC mode
9985 00:22:28.657333 INFO: mcdi ready for mcusys-off-idle and system suspend
9986 00:22:28.660053 INFO: BL31: Preparing for EL3 exit to normal world
9987 00:22:28.663570 INFO: Entry point address = 0x80000000
9988 00:22:28.666629 INFO: SPSR = 0x8
9989 00:22:28.671390
9990 00:22:28.671470
9991 00:22:28.671549
9992 00:22:28.674918 Starting depthcharge on Spherion...
9993 00:22:28.675017
9994 00:22:28.675109 Wipe memory regions:
9995 00:22:28.675196
9996 00:22:28.675912 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
9997 00:22:28.676044 start: 2.2.4 bootloader-commands (timeout 00:04:27) [common]
9998 00:22:28.676153 Setting prompt string to ['asurada:']
9999 00:22:28.676260 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:27)
10000 00:22:28.678419 [0x00000040000000, 0x00000054600000)
10001 00:22:28.800704
10002 00:22:28.800859 [0x00000054660000, 0x00000080000000)
10003 00:22:29.061064
10004 00:22:29.061239 [0x000000821a7280, 0x000000ffe64000)
10005 00:22:29.805439
10006 00:22:29.805588 [0x00000100000000, 0x00000240000000)
10007 00:22:31.694825
10008 00:22:31.697776 Initializing XHCI USB controller at 0x11200000.
10009 00:22:32.736842
10010 00:22:32.740372 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10011 00:22:32.740873
10012 00:22:32.741233
10013 00:22:32.742107 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10015 00:22:32.843344 asurada: tftpboot 192.168.201.1 14479190/tftp-deploy-i9ftv1sc/kernel/image.itb 14479190/tftp-deploy-i9ftv1sc/kernel/cmdline
10016 00:22:32.843963 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10017 00:22:32.844392 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:23)
10018 00:22:32.849177 tftpboot 192.168.201.1 14479190/tftp-deploy-i9ftv1sc/kernel/image.ittp-deploy-i9ftv1sc/kernel/cmdline
10019 00:22:32.849769
10020 00:22:32.850164 Waiting for link
10021 00:22:33.006991
10022 00:22:33.007505 R8152: Initializing
10023 00:22:33.007871
10024 00:22:33.010263 Version 6 (ocp_data = 5c30)
10025 00:22:33.010697
10026 00:22:33.013646 R8152: Done initializing
10027 00:22:33.014063
10028 00:22:33.014393 Adding net device
10029 00:22:35.056539
10030 00:22:35.056674 done.
10031 00:22:35.056743
10032 00:22:35.056804 MAC: 00:24:32:30:7c:7b
10033 00:22:35.056877
10034 00:22:35.060007 Sending DHCP discover... done.
10035 00:22:35.060090
10036 00:22:35.063489 Waiting for reply... done.
10037 00:22:35.063625
10038 00:22:35.066645 Sending DHCP request... done.
10039 00:22:35.066747
10040 00:22:35.075743 Waiting for reply... done.
10041 00:22:35.075826
10042 00:22:35.075889 My ip is 192.168.201.14
10043 00:22:35.075950
10044 00:22:35.079002 The DHCP server ip is 192.168.201.1
10045 00:22:35.079084
10046 00:22:35.085647 TFTP server IP predefined by user: 192.168.201.1
10047 00:22:35.085729
10048 00:22:35.091816 Bootfile predefined by user: 14479190/tftp-deploy-i9ftv1sc/kernel/image.itb
10049 00:22:35.091898
10050 00:22:35.095563 Sending tftp read request... done.
10051 00:22:35.095645
10052 00:22:35.099325 Waiting for the transfer...
10053 00:22:35.099407
10054 00:22:35.633502 00000000 ################################################################
10055 00:22:35.633633
10056 00:22:36.162948 00080000 ################################################################
10057 00:22:36.163111
10058 00:22:36.689282 00100000 ################################################################
10059 00:22:36.689416
10060 00:22:37.222544 00180000 ################################################################
10061 00:22:37.222678
10062 00:22:37.748795 00200000 ################################################################
10063 00:22:37.748930
10064 00:22:38.282098 00280000 ################################################################
10065 00:22:38.282232
10066 00:22:38.810114 00300000 ################################################################
10067 00:22:38.810251
10068 00:22:39.362498 00380000 ################################################################
10069 00:22:39.362649
10070 00:22:39.924896 00400000 ################################################################
10071 00:22:39.925058
10072 00:22:40.626331 00480000 ################################################################
10073 00:22:40.626536
10074 00:22:41.047087 00500000 ################################################################
10075 00:22:41.047243
10076 00:22:41.596596 00580000 ################################################################
10077 00:22:41.596765
10078 00:22:42.145639 00600000 ################################################################
10079 00:22:42.145778
10080 00:22:42.696980 00680000 ################################################################
10081 00:22:42.697154
10082 00:22:43.252223 00700000 ################################################################
10083 00:22:43.252372
10084 00:22:43.788468 00780000 ################################################################
10085 00:22:43.788618
10086 00:22:44.334961 00800000 ################################################################
10087 00:22:44.335098
10088 00:22:44.898233 00880000 ################################################################
10089 00:22:44.898447
10090 00:22:45.443127 00900000 ################################################################
10091 00:22:45.443274
10092 00:22:46.000121 00980000 ################################################################
10093 00:22:46.000268
10094 00:22:46.542941 00a00000 ################################################################
10095 00:22:46.543084
10096 00:22:47.087980 00a80000 ################################################################
10097 00:22:47.088142
10098 00:22:47.633512 00b00000 ################################################################
10099 00:22:47.633680
10100 00:22:48.185707 00b80000 ################################################################
10101 00:22:48.185881
10102 00:22:48.728566 00c00000 ################################################################
10103 00:22:48.728712
10104 00:22:49.265580 00c80000 ################################################################
10105 00:22:49.265722
10106 00:22:49.813234 00d00000 ################################################################
10107 00:22:49.813495
10108 00:22:50.355035 00d80000 ################################################################
10109 00:22:50.355183
10110 00:22:50.884817 00e00000 ################################################################
10111 00:22:50.884987
10112 00:22:51.418794 00e80000 ################################################################
10113 00:22:51.418959
10114 00:22:51.942060 00f00000 ################################################################
10115 00:22:51.942202
10116 00:22:52.461448 00f80000 ################################################################
10117 00:22:52.461598
10118 00:22:52.982543 01000000 ################################################################
10119 00:22:52.982690
10120 00:22:53.507418 01080000 ################################################################
10121 00:22:53.507576
10122 00:22:54.045472 01100000 ################################################################
10123 00:22:54.045621
10124 00:22:54.577922 01180000 ################################################################
10125 00:22:54.578059
10126 00:22:55.109023 01200000 ################################################################
10127 00:22:55.109171
10128 00:22:55.633697 01280000 ################################################################
10129 00:22:55.633837
10130 00:22:56.154474 01300000 ################################################################
10131 00:22:56.154609
10132 00:22:56.684051 01380000 ################################################################
10133 00:22:56.684203
10134 00:22:57.229415 01400000 ################################################################
10135 00:22:57.229564
10136 00:22:57.749221 01480000 ################################################################
10137 00:22:57.749407
10138 00:22:58.292754 01500000 ################################################################
10139 00:22:58.292955
10140 00:22:58.826745 01580000 ################################################################
10141 00:22:58.826890
10142 00:22:59.363384 01600000 ################################################################
10143 00:22:59.363525
10144 00:22:59.930064 01680000 ################################################################
10145 00:22:59.930215
10146 00:23:00.488777 01700000 ################################################################
10147 00:23:00.488979
10148 00:23:01.036090 01780000 ################################################################
10149 00:23:01.036248
10150 00:23:01.565472 01800000 ################################################################
10151 00:23:01.565639
10152 00:23:02.105837 01880000 ################################################################
10153 00:23:02.105986
10154 00:23:02.672946 01900000 ################################################################
10155 00:23:02.673077
10156 00:23:03.230746 01980000 ################################################################
10157 00:23:03.230880
10158 00:23:03.778870 01a00000 ################################################################
10159 00:23:03.779010
10160 00:23:04.321017 01a80000 ################################################################
10161 00:23:04.321169
10162 00:23:04.855966 01b00000 ################################################################
10163 00:23:04.856121
10164 00:23:05.404897 01b80000 ################################################################
10165 00:23:05.405031
10166 00:23:05.957572 01c00000 ################################################################
10167 00:23:05.957702
10168 00:23:06.513857 01c80000 ################################################################
10169 00:23:06.514350
10170 00:23:07.164622 01d00000 ################################################################
10171 00:23:07.164796
10172 00:23:07.722151 01d80000 ################################################################
10173 00:23:07.722728
10174 00:23:08.279921 01e00000 ################################################################
10175 00:23:08.280080
10176 00:23:08.816431 01e80000 ################################################################
10177 00:23:08.816564
10178 00:23:09.363067 01f00000 ################################################################
10179 00:23:09.363208
10180 00:23:09.905662 01f80000 ################################################################
10181 00:23:09.905798
10182 00:23:10.449955 02000000 ################################################################
10183 00:23:10.450100
10184 00:23:10.942868 02080000 ########################################################## done.
10185 00:23:10.943012
10186 00:23:10.946539 The bootfile was 34548390 bytes long.
10187 00:23:10.946637
10188 00:23:10.946702 Sending tftp read request... done.
10189 00:23:10.949824
10190 00:23:10.949899 Waiting for the transfer...
10191 00:23:10.949960
10192 00:23:10.952810 00000000 # done.
10193 00:23:10.952881
10194 00:23:10.959349 Command line loaded dynamically from TFTP file: 14479190/tftp-deploy-i9ftv1sc/kernel/cmdline
10195 00:23:10.959430
10196 00:23:10.972654 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10197 00:23:10.972748
10198 00:23:10.975725 Loading FIT.
10199 00:23:10.975828
10200 00:23:10.979236 Image ramdisk-1 has 21374203 bytes.
10201 00:23:10.979345
10202 00:23:10.979440 Image fdt-1 has 47258 bytes.
10203 00:23:10.979528
10204 00:23:10.982734 Image kernel-1 has 13124896 bytes.
10205 00:23:10.982833
10206 00:23:10.992605 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10207 00:23:10.993285
10208 00:23:11.009130 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10209 00:23:11.009659
10210 00:23:11.015492 Choosing best match conf-1 for compat google,spherion-rev2.
10211 00:23:11.019937
10212 00:23:11.024715 Connected to device vid:did:rid of 1ae0:0028:00
10213 00:23:11.031390
10214 00:23:11.034966 tpm_get_response: command 0x17b, return code 0x0
10215 00:23:11.035399
10216 00:23:11.037790 ec_init: CrosEC protocol v3 supported (256, 248)
10217 00:23:11.042071
10218 00:23:11.045186 tpm_cleanup: add release locality here.
10219 00:23:11.045647
10220 00:23:11.045970 Shutting down all USB controllers.
10221 00:23:11.048922
10222 00:23:11.049632 Removing current net device
10223 00:23:11.050234
10224 00:23:11.056826 Exiting depthcharge with code 4 at timestamp: 71608412
10225 00:23:11.057479
10226 00:23:11.061065 LZMA decompressing kernel-1 to 0x821a6718
10227 00:23:11.061712
10228 00:23:11.062121 LZMA decompressing kernel-1 to 0x40000000
10229 00:23:12.677910
10230 00:23:12.678060 jumping to kernel
10231 00:23:12.678933 end: 2.2.4 bootloader-commands (duration 00:00:44) [common]
10232 00:23:12.679072 start: 2.2.5 auto-login-action (timeout 00:03:43) [common]
10233 00:23:12.679181 Setting prompt string to ['Linux version [0-9]']
10234 00:23:12.679279 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10235 00:23:12.679376 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10236 00:23:12.759792
10237 00:23:12.763459 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10238 00:23:12.766626 start: 2.2.5.1 login-action (timeout 00:03:43) [common]
10239 00:23:12.766718 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10240 00:23:12.766787 Setting prompt string to []
10241 00:23:12.766863 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10242 00:23:12.766934 Using line separator: #'\n'#
10243 00:23:12.766992 No login prompt set.
10244 00:23:12.767052 Parsing kernel messages
10245 00:23:12.767106 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10246 00:23:12.767203 [login-action] Waiting for messages, (timeout 00:03:43)
10247 00:23:12.767267 Waiting using forced prompt support (timeout 00:01:51)
10248 00:23:12.786066 [ 0.000000] Linux version 6.1.94-cip23 (KernelCI@build-j239242-arm64-gcc-10-defconfig-arm64-chromebook-c5lwc) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Jun 21 00:04:56 UTC 2024
10249 00:23:12.789520 [ 0.000000] random: crng init done
10250 00:23:12.796155 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10251 00:23:12.799092 [ 0.000000] efi: UEFI not found.
10252 00:23:12.805813 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10253 00:23:12.815498 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10254 00:23:12.825348 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10255 00:23:12.832058 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10256 00:23:12.838973 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10257 00:23:12.845488 [ 0.000000] printk: bootconsole [mtk8250] enabled
10258 00:23:12.851996 [ 0.000000] NUMA: No NUMA configuration found
10259 00:23:12.858418 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10260 00:23:12.864990 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10261 00:23:12.865070 [ 0.000000] Zone ranges:
10262 00:23:12.871758 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10263 00:23:12.874824 [ 0.000000] DMA32 empty
10264 00:23:12.881663 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10265 00:23:12.885065 [ 0.000000] Movable zone start for each node
10266 00:23:12.888040 [ 0.000000] Early memory node ranges
10267 00:23:12.895331 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10268 00:23:12.901146 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10269 00:23:12.907910 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10270 00:23:12.914417 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10271 00:23:12.921034 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10272 00:23:12.927921 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10273 00:23:12.984237 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10274 00:23:12.990751 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10275 00:23:12.997646 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10276 00:23:13.001244 [ 0.000000] psci: probing for conduit method from DT.
10277 00:23:13.007389 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10278 00:23:13.010886 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10279 00:23:13.017499 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10280 00:23:13.020623 [ 0.000000] psci: SMC Calling Convention v1.2
10281 00:23:13.027520 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10282 00:23:13.030982 [ 0.000000] Detected VIPT I-cache on CPU0
10283 00:23:13.037741 [ 0.000000] CPU features: detected: GIC system register CPU interface
10284 00:23:13.043701 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10285 00:23:13.050701 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10286 00:23:13.057130 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10287 00:23:13.063958 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10288 00:23:13.073942 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10289 00:23:13.076870 [ 0.000000] alternatives: applying boot alternatives
10290 00:23:13.083542 [ 0.000000] Fallback order for Node 0: 0
10291 00:23:13.090190 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10292 00:23:13.093467 [ 0.000000] Policy zone: Normal
10293 00:23:13.106961 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10294 00:23:13.116498 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10295 00:23:13.128950 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10296 00:23:13.138636 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10297 00:23:13.145312 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10298 00:23:13.148350 <6>[ 0.000000] software IO TLB: area num 8.
10299 00:23:13.205305 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10300 00:23:13.355370 <6>[ 0.000000] Memory: 7943188K/8385536K available (18112K kernel code, 4120K rwdata, 22648K rodata, 8512K init, 616K bss, 409580K reserved, 32768K cma-reserved)
10301 00:23:13.361650 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10302 00:23:13.368172 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10303 00:23:13.371684 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10304 00:23:13.378352 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10305 00:23:13.384785 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10306 00:23:13.388330 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10307 00:23:13.397646 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10308 00:23:13.404735 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10309 00:23:13.411147 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10310 00:23:13.417584 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10311 00:23:13.420877 <6>[ 0.000000] GICv3: 608 SPIs implemented
10312 00:23:13.424059 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10313 00:23:13.430896 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10314 00:23:13.434311 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10315 00:23:13.441047 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10316 00:23:13.453631 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10317 00:23:13.467102 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10318 00:23:13.473609 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10319 00:23:13.481582 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10320 00:23:13.494774 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10321 00:23:13.501043 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10322 00:23:13.507964 <6>[ 0.009175] Console: colour dummy device 80x25
10323 00:23:13.517799 <6>[ 0.013894] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10324 00:23:13.524671 <6>[ 0.024335] pid_max: default: 32768 minimum: 301
10325 00:23:13.528061 <6>[ 0.029207] LSM: Security Framework initializing
10326 00:23:13.534683 <6>[ 0.034145] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10327 00:23:13.544619 <6>[ 0.041959] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10328 00:23:13.554541 <6>[ 0.051368] cblist_init_generic: Setting adjustable number of callback queues.
10329 00:23:13.557434 <6>[ 0.058811] cblist_init_generic: Setting shift to 3 and lim to 1.
10330 00:23:13.567625 <6>[ 0.065150] cblist_init_generic: Setting adjustable number of callback queues.
10331 00:23:13.574176 <6>[ 0.072576] cblist_init_generic: Setting shift to 3 and lim to 1.
10332 00:23:13.577436 <6>[ 0.079016] rcu: Hierarchical SRCU implementation.
10333 00:23:13.584110 <6>[ 0.084032] rcu: Max phase no-delay instances is 1000.
10334 00:23:13.590656 <6>[ 0.091060] EFI services will not be available.
10335 00:23:13.593618 <6>[ 0.096017] smp: Bringing up secondary CPUs ...
10336 00:23:13.602172 <6>[ 0.101071] Detected VIPT I-cache on CPU1
10337 00:23:13.609307 <6>[ 0.101141] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10338 00:23:13.615714 <6>[ 0.101172] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10339 00:23:13.619351 <6>[ 0.101503] Detected VIPT I-cache on CPU2
10340 00:23:13.625817 <6>[ 0.101552] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10341 00:23:13.635676 <6>[ 0.101568] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10342 00:23:13.639173 <6>[ 0.101823] Detected VIPT I-cache on CPU3
10343 00:23:13.645567 <6>[ 0.101869] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10344 00:23:13.652018 <6>[ 0.101883] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10345 00:23:13.655305 <6>[ 0.102187] CPU features: detected: Spectre-v4
10346 00:23:13.661994 <6>[ 0.102194] CPU features: detected: Spectre-BHB
10347 00:23:13.665056 <6>[ 0.102199] Detected PIPT I-cache on CPU4
10348 00:23:13.671344 <6>[ 0.102259] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10349 00:23:13.678322 <6>[ 0.102276] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10350 00:23:13.684797 <6>[ 0.102572] Detected PIPT I-cache on CPU5
10351 00:23:13.691535 <6>[ 0.102637] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10352 00:23:13.698044 <6>[ 0.102653] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10353 00:23:13.701217 <6>[ 0.102934] Detected PIPT I-cache on CPU6
10354 00:23:13.707607 <6>[ 0.102999] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10355 00:23:13.717312 <6>[ 0.103016] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10356 00:23:13.721119 <6>[ 0.103311] Detected PIPT I-cache on CPU7
10357 00:23:13.727326 <6>[ 0.103378] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10358 00:23:13.734062 <6>[ 0.103394] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10359 00:23:13.737461 <6>[ 0.103442] smp: Brought up 1 node, 8 CPUs
10360 00:23:13.743798 <6>[ 0.244887] SMP: Total of 8 processors activated.
10361 00:23:13.750546 <6>[ 0.249808] CPU features: detected: 32-bit EL0 Support
10362 00:23:13.757027 <6>[ 0.255172] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10363 00:23:13.763469 <6>[ 0.263973] CPU features: detected: Common not Private translations
10364 00:23:13.770268 <6>[ 0.270449] CPU features: detected: CRC32 instructions
10365 00:23:13.776882 <6>[ 0.275800] CPU features: detected: RCpc load-acquire (LDAPR)
10366 00:23:13.779866 <6>[ 0.281761] CPU features: detected: LSE atomic instructions
10367 00:23:13.786411 <6>[ 0.287542] CPU features: detected: Privileged Access Never
10368 00:23:13.793356 <6>[ 0.293322] CPU features: detected: RAS Extension Support
10369 00:23:13.799828 <6>[ 0.298965] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10370 00:23:13.802876 <6>[ 0.306185] CPU: All CPU(s) started at EL2
10371 00:23:13.809492 <6>[ 0.310529] alternatives: applying system-wide alternatives
10372 00:23:13.820158 <6>[ 0.321432] devtmpfs: initialized
10373 00:23:13.835475 <6>[ 0.330348] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10374 00:23:13.842134 <6>[ 0.340311] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10375 00:23:13.848764 <6>[ 0.348327] pinctrl core: initialized pinctrl subsystem
10376 00:23:13.852128 <6>[ 0.355128] DMI not present or invalid.
10377 00:23:13.858547 <6>[ 0.359540] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10378 00:23:13.868573 <6>[ 0.366316] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10379 00:23:13.875534 <6>[ 0.373905] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10380 00:23:13.885180 <6>[ 0.382129] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10381 00:23:13.888467 <6>[ 0.390371] audit: initializing netlink subsys (disabled)
10382 00:23:13.898202 <5>[ 0.396063] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10383 00:23:13.904965 <6>[ 0.396819] thermal_sys: Registered thermal governor 'step_wise'
10384 00:23:13.911493 <6>[ 0.404030] thermal_sys: Registered thermal governor 'power_allocator'
10385 00:23:13.914478 <6>[ 0.410284] cpuidle: using governor menu
10386 00:23:13.921236 <6>[ 0.421244] NET: Registered PF_QIPCRTR protocol family
10387 00:23:13.928131 <6>[ 0.426719] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10388 00:23:13.934504 <6>[ 0.433825] ASID allocator initialised with 32768 entries
10389 00:23:13.938010 <6>[ 0.440455] Serial: AMBA PL011 UART driver
10390 00:23:13.948608 <4>[ 0.449662] Trying to register duplicate clock ID: 134
10391 00:23:14.008500 <6>[ 0.513371] KASLR enabled
10392 00:23:14.022533 <6>[ 0.521094] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10393 00:23:14.029273 <6>[ 0.528108] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10394 00:23:14.035918 <6>[ 0.534598] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10395 00:23:14.042233 <6>[ 0.541603] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10396 00:23:14.048954 <6>[ 0.548090] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10397 00:23:14.055427 <6>[ 0.555093] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10398 00:23:14.062070 <6>[ 0.561580] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10399 00:23:14.069140 <6>[ 0.568582] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10400 00:23:14.072067 <6>[ 0.576048] ACPI: Interpreter disabled.
10401 00:23:14.081196 <6>[ 0.582554] iommu: Default domain type: Translated
10402 00:23:14.087534 <6>[ 0.587706] iommu: DMA domain TLB invalidation policy: strict mode
10403 00:23:14.090715 <5>[ 0.594368] SCSI subsystem initialized
10404 00:23:14.097903 <6>[ 0.598620] usbcore: registered new interface driver usbfs
10405 00:23:14.103969 <6>[ 0.604352] usbcore: registered new interface driver hub
10406 00:23:14.107285 <6>[ 0.609903] usbcore: registered new device driver usb
10407 00:23:14.114557 <6>[ 0.616068] pps_core: LinuxPPS API ver. 1 registered
10408 00:23:14.124471 <6>[ 0.621262] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10409 00:23:14.127798 <6>[ 0.630607] PTP clock support registered
10410 00:23:14.131058 <6>[ 0.634850] EDAC MC: Ver: 3.0.0
10411 00:23:14.138356 <6>[ 0.640090] FPGA manager framework
10412 00:23:14.145089 <6>[ 0.643769] Advanced Linux Sound Architecture Driver Initialized.
10413 00:23:14.148861 <6>[ 0.650543] vgaarb: loaded
10414 00:23:14.154998 <6>[ 0.653684] clocksource: Switched to clocksource arch_sys_counter
10415 00:23:14.158599 <5>[ 0.660128] VFS: Disk quotas dquot_6.6.0
10416 00:23:14.165209 <6>[ 0.664312] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10417 00:23:14.168266 <6>[ 0.671504] pnp: PnP ACPI: disabled
10418 00:23:14.177202 <6>[ 0.678212] NET: Registered PF_INET protocol family
10419 00:23:14.186740 <6>[ 0.683801] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10420 00:23:14.197800 <6>[ 0.696130] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10421 00:23:14.208154 <6>[ 0.704946] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10422 00:23:14.214485 <6>[ 0.712917] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10423 00:23:14.224418 <6>[ 0.721617] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10424 00:23:14.230829 <6>[ 0.731368] TCP: Hash tables configured (established 65536 bind 65536)
10425 00:23:14.237475 <6>[ 0.738238] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10426 00:23:14.247505 <6>[ 0.745437] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10427 00:23:14.254152 <6>[ 0.753144] NET: Registered PF_UNIX/PF_LOCAL protocol family
10428 00:23:14.260381 <6>[ 0.759285] RPC: Registered named UNIX socket transport module.
10429 00:23:14.263913 <6>[ 0.765441] RPC: Registered udp transport module.
10430 00:23:14.270497 <6>[ 0.770374] RPC: Registered tcp transport module.
10431 00:23:14.277169 <6>[ 0.775306] RPC: Registered tcp NFSv4.1 backchannel transport module.
10432 00:23:14.280230 <6>[ 0.781973] PCI: CLS 0 bytes, default 64
10433 00:23:14.283555 <6>[ 0.786288] Unpacking initramfs...
10434 00:23:14.300016 <6>[ 0.798255] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10435 00:23:14.309757 <6>[ 0.806892] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10436 00:23:14.313190 <6>[ 0.815738] kvm [1]: IPA Size Limit: 40 bits
10437 00:23:14.319477 <6>[ 0.820266] kvm [1]: GICv3: no GICV resource entry
10438 00:23:14.322977 <6>[ 0.825287] kvm [1]: disabling GICv2 emulation
10439 00:23:14.330019 <6>[ 0.829973] kvm [1]: GIC system register CPU interface enabled
10440 00:23:14.332728 <6>[ 0.836132] kvm [1]: vgic interrupt IRQ18
10441 00:23:14.339764 <6>[ 0.840485] kvm [1]: VHE mode initialized successfully
10442 00:23:14.346068 <5>[ 0.846975] Initialise system trusted keyrings
10443 00:23:14.352483 <6>[ 0.851757] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10444 00:23:14.359921 <6>[ 0.861757] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10445 00:23:14.366880 <5>[ 0.868130] NFS: Registering the id_resolver key type
10446 00:23:14.370278 <5>[ 0.873431] Key type id_resolver registered
10447 00:23:14.376497 <5>[ 0.877844] Key type id_legacy registered
10448 00:23:14.383485 <6>[ 0.882122] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10449 00:23:14.390091 <6>[ 0.889044] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10450 00:23:14.396204 <6>[ 0.896744] 9p: Installing v9fs 9p2000 file system support
10451 00:23:14.432774 <5>[ 0.934397] Key type asymmetric registered
10452 00:23:14.436055 <5>[ 0.938727] Asymmetric key parser 'x509' registered
10453 00:23:14.446490 <6>[ 0.943857] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10454 00:23:14.449447 <6>[ 0.951475] io scheduler mq-deadline registered
10455 00:23:14.453010 <6>[ 0.956234] io scheduler kyber registered
10456 00:23:14.471847 <6>[ 0.973722] EINJ: ACPI disabled.
10457 00:23:14.505103 <4>[ 1.000251] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10458 00:23:14.515233 <4>[ 1.010880] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10459 00:23:14.530807 <6>[ 1.032119] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10460 00:23:14.538396 <6>[ 1.040147] printk: console [ttyS0] disabled
10461 00:23:14.566490 <6>[ 1.064775] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10462 00:23:14.573208 <6>[ 1.074248] printk: console [ttyS0] enabled
10463 00:23:14.576509 <6>[ 1.074248] printk: console [ttyS0] enabled
10464 00:23:14.582977 <6>[ 1.083142] printk: bootconsole [mtk8250] disabled
10465 00:23:14.586502 <6>[ 1.083142] printk: bootconsole [mtk8250] disabled
10466 00:23:14.593060 <6>[ 1.094207] SuperH (H)SCI(F) driver initialized
10467 00:23:14.596300 <6>[ 1.099493] msm_serial: driver initialized
10468 00:23:14.610091 <6>[ 1.108531] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10469 00:23:14.620206 <6>[ 1.117076] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10470 00:23:14.626851 <6>[ 1.125618] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10471 00:23:14.637130 <6>[ 1.134248] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10472 00:23:14.646512 <6>[ 1.142956] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10473 00:23:14.653049 <6>[ 1.151675] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10474 00:23:14.663236 <6>[ 1.160216] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10475 00:23:14.669767 <6>[ 1.169016] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10476 00:23:14.679623 <6>[ 1.177560] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10477 00:23:14.691615 <6>[ 1.193377] loop: module loaded
10478 00:23:14.698029 <6>[ 1.199448] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10479 00:23:14.721088 <4>[ 1.222916] mtk-pmic-keys: Failed to locate of_node [id: -1]
10480 00:23:14.728565 <6>[ 1.230010] megasas: 07.719.03.00-rc1
10481 00:23:14.737879 <6>[ 1.239859] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10482 00:23:14.747716 <6>[ 1.249063] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10483 00:23:14.764393 <6>[ 1.265720] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10484 00:23:14.820346 <6>[ 1.315646] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10485 00:23:15.193164 <6>[ 1.694629] Freeing initrd memory: 20868K
10486 00:23:15.208843 <6>[ 1.710371] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10487 00:23:15.219733 <6>[ 1.721350] tun: Universal TUN/TAP device driver, 1.6
10488 00:23:15.222803 <6>[ 1.727438] thunder_xcv, ver 1.0
10489 00:23:15.226462 <6>[ 1.730945] thunder_bgx, ver 1.0
10490 00:23:15.230127 <6>[ 1.734439] nicpf, ver 1.0
10491 00:23:15.239909 <6>[ 1.738486] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10492 00:23:15.243648 <6>[ 1.745962] hns3: Copyright (c) 2017 Huawei Corporation.
10493 00:23:15.250026 <6>[ 1.751547] hclge is initializing
10494 00:23:15.253106 <6>[ 1.755127] e1000: Intel(R) PRO/1000 Network Driver
10495 00:23:15.259848 <6>[ 1.760256] e1000: Copyright (c) 1999-2006 Intel Corporation.
10496 00:23:15.263295 <6>[ 1.766269] e1000e: Intel(R) PRO/1000 Network Driver
10497 00:23:15.269955 <6>[ 1.771483] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10498 00:23:15.276659 <6>[ 1.777669] igb: Intel(R) Gigabit Ethernet Network Driver
10499 00:23:15.283066 <6>[ 1.783324] igb: Copyright (c) 2007-2014 Intel Corporation.
10500 00:23:15.289674 <6>[ 1.789164] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10501 00:23:15.296829 <6>[ 1.795681] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10502 00:23:15.299531 <6>[ 1.802148] sky2: driver version 1.30
10503 00:23:15.306614 <6>[ 1.807136] usbcore: registered new device driver r8152-cfgselector
10504 00:23:15.313290 <6>[ 1.813677] usbcore: registered new interface driver r8152
10505 00:23:15.319680 <6>[ 1.819493] VFIO - User Level meta-driver version: 0.3
10506 00:23:15.326440 <6>[ 1.827808] usbcore: registered new interface driver usb-storage
10507 00:23:15.332514 <6>[ 1.834252] usbcore: registered new device driver onboard-usb-hub
10508 00:23:15.341727 <6>[ 1.843464] mt6397-rtc mt6359-rtc: registered as rtc0
10509 00:23:15.351830 <6>[ 1.848935] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-21T00:23:15 UTC (1718929395)
10510 00:23:15.355302 <6>[ 1.858541] i2c_dev: i2c /dev entries driver
10511 00:23:15.369083 <4>[ 1.870670] cpu cpu0: supply cpu not found, using dummy regulator
10512 00:23:15.375696 <4>[ 1.877092] cpu cpu1: supply cpu not found, using dummy regulator
10513 00:23:15.382284 <4>[ 1.883499] cpu cpu2: supply cpu not found, using dummy regulator
10514 00:23:15.388682 <4>[ 1.889900] cpu cpu3: supply cpu not found, using dummy regulator
10515 00:23:15.395342 <4>[ 1.896316] cpu cpu4: supply cpu not found, using dummy regulator
10516 00:23:15.401952 <4>[ 1.902714] cpu cpu5: supply cpu not found, using dummy regulator
10517 00:23:15.408474 <4>[ 1.909112] cpu cpu6: supply cpu not found, using dummy regulator
10518 00:23:15.415396 <4>[ 1.915508] cpu cpu7: supply cpu not found, using dummy regulator
10519 00:23:15.434673 <6>[ 1.936137] cpu cpu0: EM: created perf domain
10520 00:23:15.437695 <6>[ 1.941011] cpu cpu4: EM: created perf domain
10521 00:23:15.444759 <6>[ 1.946622] sdhci: Secure Digital Host Controller Interface driver
10522 00:23:15.451628 <6>[ 1.953053] sdhci: Copyright(c) Pierre Ossman
10523 00:23:15.458512 <6>[ 1.958011] Synopsys Designware Multimedia Card Interface Driver
10524 00:23:15.461469 <6>[ 1.964624] mmc0: CQHCI version 5.10
10525 00:23:15.468206 <6>[ 1.964672] sdhci-pltfm: SDHCI platform and OF driver helper
10526 00:23:15.474758 <6>[ 1.975356] ledtrig-cpu: registered to indicate activity on CPUs
10527 00:23:15.481443 <6>[ 1.982331] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10528 00:23:15.488288 <6>[ 1.989393] usbcore: registered new interface driver usbhid
10529 00:23:15.491413 <6>[ 1.995215] usbhid: USB HID core driver
10530 00:23:15.497987 <6>[ 1.999424] spi_master spi0: will run message pump with realtime priority
10531 00:23:15.547088 <6>[ 2.042202] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10532 00:23:15.566711 <6>[ 2.057889] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10533 00:23:15.569795 <6>[ 2.065051] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x15414
10534 00:23:15.576967 <6>[ 2.073460] cros-ec-spi spi0.0: Chrome EC device registered
10535 00:23:15.580165 <6>[ 2.083343] mmc0: Command Queue Engine enabled
10536 00:23:15.586909 <6>[ 2.088089] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10537 00:23:15.594543 <6>[ 2.096212] mmcblk0: mmc0:0001 DA4128 116 GiB
10538 00:23:15.604757 <6>[ 2.097827] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10539 00:23:15.611525 <6>[ 2.105081] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10540 00:23:15.614449 <6>[ 2.111299] NET: Registered PF_PACKET protocol family
10541 00:23:15.621207 <6>[ 2.117545] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10542 00:23:15.624356 <6>[ 2.121503] 9pnet: Installing 9P2000 support
10543 00:23:15.630798 <6>[ 2.127395] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10544 00:23:15.634190 <5>[ 2.131209] Key type dns_resolver registered
10545 00:23:15.640722 <6>[ 2.137025] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10546 00:23:15.643773 <6>[ 2.141356] registered taskstats version 1
10547 00:23:15.650442 <5>[ 2.151806] Loading compiled-in X.509 certificates
10548 00:23:15.678277 <4>[ 2.173301] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10549 00:23:15.688488 <4>[ 2.184053] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10550 00:23:15.702156 <6>[ 2.203821] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10551 00:23:15.709033 <6>[ 2.210770] xhci-mtk 11200000.usb: xHCI Host Controller
10552 00:23:15.715592 <6>[ 2.216281] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10553 00:23:15.725798 <6>[ 2.224161] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10554 00:23:15.732505 <6>[ 2.233597] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10555 00:23:15.738791 <6>[ 2.239688] xhci-mtk 11200000.usb: xHCI Host Controller
10556 00:23:15.745917 <6>[ 2.245176] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10557 00:23:15.752573 <6>[ 2.252923] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10558 00:23:15.759281 <6>[ 2.260795] hub 1-0:1.0: USB hub found
10559 00:23:15.762300 <6>[ 2.264822] hub 1-0:1.0: 1 port detected
10560 00:23:15.772384 <6>[ 2.269117] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10561 00:23:15.775353 <6>[ 2.277830] hub 2-0:1.0: USB hub found
10562 00:23:15.778544 <6>[ 2.281850] hub 2-0:1.0: 1 port detected
10563 00:23:15.786766 <6>[ 2.288536] mtk-msdc 11f70000.mmc: Got CD GPIO
10564 00:23:15.800736 <6>[ 2.299034] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10565 00:23:15.810632 <6>[ 2.307448] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10566 00:23:15.817535 <6>[ 2.315788] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10567 00:23:15.827627 <6>[ 2.324135] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10568 00:23:15.834096 <6>[ 2.332475] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10569 00:23:15.843864 <6>[ 2.340812] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10570 00:23:15.850669 <6>[ 2.349151] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10571 00:23:15.860599 <6>[ 2.357488] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10572 00:23:15.867221 <6>[ 2.365826] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10573 00:23:15.877122 <6>[ 2.374164] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10574 00:23:15.883819 <6>[ 2.382501] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10575 00:23:15.893592 <6>[ 2.390847] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10576 00:23:15.900259 <6>[ 2.399185] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10577 00:23:15.910121 <6>[ 2.407523] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10578 00:23:15.917083 <6>[ 2.415861] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10579 00:23:15.922934 <6>[ 2.424585] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10580 00:23:15.930340 <6>[ 2.431749] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10581 00:23:15.937248 <6>[ 2.438527] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10582 00:23:15.947185 <6>[ 2.445310] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10583 00:23:15.953675 <6>[ 2.452256] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10584 00:23:15.960597 <6>[ 2.459124] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10585 00:23:15.970319 <6>[ 2.468255] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10586 00:23:15.979893 <6>[ 2.477374] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10587 00:23:15.989997 <6>[ 2.486668] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10588 00:23:15.999788 <6>[ 2.496135] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10589 00:23:16.010009 <6>[ 2.505614] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10590 00:23:16.016324 <6>[ 2.514733] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10591 00:23:16.026083 <6>[ 2.524200] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10592 00:23:16.036153 <6>[ 2.533325] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10593 00:23:16.046133 <6>[ 2.542630] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10594 00:23:16.055800 <6>[ 2.552791] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10595 00:23:16.066289 <6>[ 2.564789] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10596 00:23:16.191179 <6>[ 2.689973] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10597 00:23:16.345487 <6>[ 2.847203] hub 1-1:1.0: USB hub found
10598 00:23:16.348777 <6>[ 2.851655] hub 1-1:1.0: 4 ports detected
10599 00:23:16.359449 <6>[ 2.861249] hub 1-1:1.0: USB hub found
10600 00:23:16.362520 <6>[ 2.865561] hub 1-1:1.0: 4 ports detected
10601 00:23:16.472042 <6>[ 2.970320] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10602 00:23:16.500481 <6>[ 3.001311] hub 2-1:1.0: USB hub found
10603 00:23:16.503093 <6>[ 3.005885] hub 2-1:1.0: 3 ports detected
10604 00:23:16.514999 <6>[ 3.016621] hub 2-1:1.0: USB hub found
10605 00:23:16.518390 <6>[ 3.021054] hub 2-1:1.0: 3 ports detected
10606 00:23:16.683468 <6>[ 3.182006] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10607 00:23:16.815667 <6>[ 3.317219] hub 1-1.4:1.0: USB hub found
10608 00:23:16.818703 <6>[ 3.321795] hub 1-1.4:1.0: 2 ports detected
10609 00:23:16.833578 <6>[ 3.335071] hub 1-1.4:1.0: USB hub found
10610 00:23:16.836910 <6>[ 3.339654] hub 1-1.4:1.0: 2 ports detected
10611 00:23:16.900208 <6>[ 3.398215] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10612 00:23:17.008230 <6>[ 3.506643] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10613 00:23:17.044964 <4>[ 3.543412] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10614 00:23:17.055160 <4>[ 3.552548] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10615 00:23:17.089766 <6>[ 3.591557] r8152 2-1.3:1.0 eth0: v1.12.13
10616 00:23:17.143614 <6>[ 3.641956] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10617 00:23:17.335536 <6>[ 3.833994] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10618 00:23:18.736692 <6>[ 5.238765] r8152 2-1.3:1.0 eth0: carrier on
10619 00:23:21.655801 <5>[ 5.269747] Sending DHCP requests .., OK
10620 00:23:21.662284 <6>[ 8.162141] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10621 00:23:21.665181 <6>[ 8.170426] IP-Config: Complete:
10622 00:23:21.678726 <6>[ 8.173912] device=eth0, hwaddr=00:24:32:30:7c:7b, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10623 00:23:21.685584 <6>[ 8.184612] host=mt8192-asurada-spherion-r0-cbg-2, domain=lava-rack, nis-domain=(none)
10624 00:23:21.691988 <6>[ 8.193223] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10625 00:23:21.698386 <6>[ 8.193230] nameserver0=192.168.201.1
10626 00:23:21.701818 <6>[ 8.205315] clk: Disabling unused clocks
10627 00:23:21.705084 <6>[ 8.210546] ALSA device list:
10628 00:23:21.711592 <6>[ 8.213857] No soundcards found.
10629 00:23:21.719256 <6>[ 8.221155] Freeing unused kernel memory: 8512K
10630 00:23:21.722162 <6>[ 8.226168] Run /init as init process
10631 00:23:21.746946 Starting syslogd: OK
10632 00:23:21.750485 Starting klogd: OK
10633 00:23:21.758352 Running sysctl: OK
10634 00:23:21.768482 Populating /dev using udev: <30>[ 8.270527] udevd[196]: starting version 3.2.9
10635 00:23:21.777089 <27>[ 8.279137] udevd[196]: specified user 'tss' unknown
10636 00:23:21.783587 <27>[ 8.284541] udevd[196]: specified group 'tss' unknown
10637 00:23:21.786662 <30>[ 8.291149] udevd[197]: starting eudev-3.2.9
10638 00:23:21.810904 <27>[ 8.312714] udevd[197]: specified user 'tss' unknown
10639 00:23:21.817102 <27>[ 8.318133] udevd[197]: specified group 'tss' unknown
10640 00:23:21.926238 <6>[ 8.425502] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10641 00:23:21.932958 <6>[ 8.434206] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10642 00:23:21.968972 <6>[ 8.468013] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10643 00:23:21.979091 <3>[ 8.470416] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10644 00:23:21.985712 <6>[ 8.485010] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10645 00:23:21.995128 <3>[ 8.485630] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10646 00:23:21.998858 <6>[ 8.486285] mc: Linux media interface: v0.10
10647 00:23:22.005483 <6>[ 8.503122] videodev: Linux video capture interface: v2.00
10648 00:23:22.012160 <3>[ 8.506413] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10649 00:23:22.022025 <6>[ 8.507342] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10650 00:23:22.028670 <6>[ 8.512397] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10651 00:23:22.035162 <6>[ 8.514377] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10652 00:23:22.041833 <6>[ 8.528832] remoteproc remoteproc0: scp is available
10653 00:23:22.048450 <3>[ 8.529506] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10654 00:23:22.058429 <3>[ 8.529531] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10655 00:23:22.064916 <3>[ 8.529537] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10656 00:23:22.074514 <3>[ 8.529547] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10657 00:23:22.081130 <3>[ 8.529552] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10658 00:23:22.091366 <3>[ 8.529595] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10659 00:23:22.097967 <3>[ 8.529637] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10660 00:23:22.107774 <3>[ 8.529640] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10661 00:23:22.114328 <3>[ 8.529643] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10662 00:23:22.124382 <3>[ 8.529686] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10663 00:23:22.130657 <3>[ 8.529690] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10664 00:23:22.140461 <3>[ 8.529693] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10665 00:23:22.147063 <3>[ 8.529698] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10666 00:23:22.153685 <3>[ 8.529701] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10667 00:23:22.164279 <3>[ 8.529727] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10668 00:23:22.170364 <6>[ 8.536248] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10669 00:23:22.180105 <4>[ 8.536415] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10670 00:23:22.187128 <6>[ 8.544104] remoteproc remoteproc0: powering up scp
10671 00:23:22.193430 <6>[ 8.550081] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10672 00:23:22.203348 <6>[ 8.557358] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10673 00:23:22.209988 <6>[ 8.565383] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10674 00:23:22.216765 <6>[ 8.573526] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10675 00:23:22.223093 <6>[ 8.582776] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10676 00:23:22.229713 <4>[ 8.591637] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10677 00:23:22.239676 <6>[ 8.597761] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10678 00:23:22.246155 <6>[ 8.597765] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10679 00:23:22.256313 <4>[ 8.604701] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10680 00:23:22.259501 <4>[ 8.604701] Fallback method does not support PEC.
10681 00:23:22.266741 <4>[ 8.612443] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10682 00:23:22.275935 <6>[ 8.613938] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10683 00:23:22.282811 <6>[ 8.626035] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10684 00:23:22.289412 <6>[ 8.719070] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10685 00:23:22.299265 <6>[ 8.719118] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10686 00:23:22.305853 <6>[ 8.719128] remoteproc remoteproc0: remote processor scp is now up
10687 00:23:22.312560 <6>[ 8.722964] pci_bus 0000:00: root bus resource [bus 00-ff]
10688 00:23:22.319022 <6>[ 8.736698] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10689 00:23:22.328786 <6>[ 8.738051] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10690 00:23:22.338641 <6>[ 8.738398] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10691 00:23:22.345813 <6>[ 8.738930] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10692 00:23:22.355911 <6>[ 8.739730] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10693 00:23:22.362637 <6>[ 8.741945] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10694 00:23:22.365425 <6>[ 8.777160] Bluetooth: Core ver 2.22
10695 00:23:22.375535 <6>[ 8.784202] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10696 00:23:22.381722 <6>[ 8.791305] NET: Registered PF_BLUETOOTH protocol family
10697 00:23:22.388283 <6>[ 8.792434] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10698 00:23:22.401783 <6>[ 8.793632] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10699 00:23:22.408332 <6>[ 8.793924] usbcore: registered new interface driver uvcvideo
10700 00:23:22.414993 <6>[ 8.797840] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10701 00:23:22.421447 <6>[ 8.806263] Bluetooth: HCI device and connection manager initialized
10702 00:23:22.427710 <6>[ 8.812678] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10703 00:23:22.434598 <6>[ 8.813359] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10704 00:23:22.441251 <6>[ 8.818409] Bluetooth: HCI socket layer initialized
10705 00:23:22.444249 <6>[ 8.827781] pci 0000:00:00.0: supports D1 D2
10706 00:23:22.450905 <6>[ 8.834800] Bluetooth: L2CAP socket layer initialized
10707 00:23:22.457759 <6>[ 8.844893] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10708 00:23:22.460727 <6>[ 8.853917] Bluetooth: SCO socket layer initialized
10709 00:23:22.471012 <6>[ 8.863244] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10710 00:23:22.474099 <6>[ 8.909740] usbcore: registered new interface driver btusb
10711 00:23:22.487301 <4>[ 8.910678] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10712 00:23:22.490704 <3>[ 8.910690] Bluetooth: hci0: Failed to load firmware file (-2)
10713 00:23:22.497450 <3>[ 8.910694] Bluetooth: hci0: Failed to set up firmware (-2)
10714 00:23:22.507123 <4>[ 8.910699] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10715 00:23:22.513885 <6>[ 8.915314] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10716 00:23:22.523938 <6>[ 9.022048] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10717 00:23:22.530385 <6>[ 9.029555] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10718 00:23:22.537210 <6>[ 9.037047] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10719 00:23:22.540775 <6>[ 9.044634] pci 0000:01:00.0: supports D1 D2
10720 00:23:22.547306 <6>[ 9.049169] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10721 00:23:22.564646 <3>[ 9.063945] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10722 00:23:22.571240 <6>[ 9.065847] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10723 00:23:22.581434 <6>[ 9.079672] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10724 00:23:22.588719 <6>[ 9.087756] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10725 00:23:22.595643 <6>[ 9.095753] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10726 00:23:22.604983 <3>[ 9.097343] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10727 00:23:22.611567 <6>[ 9.103754] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10728 00:23:22.621800 <6>[ 9.103767] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10729 00:23:22.625223 <6>[ 9.128524] pci 0000:00:00.0: PCI bridge to [bus 01]
10730 00:23:22.634894 <6>[ 9.133740] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10731 00:23:22.641758 <6>[ 9.141944] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10732 00:23:22.648261 <6>[ 9.148830] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10733 00:23:22.654777 <6>[ 9.155613] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10734 00:23:22.677832 <5>[ 9.176873] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10735 00:23:22.710015 <5>[ 9.209238] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10736 00:23:22.716566 <5>[ 9.217222] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10737 00:23:22.727041 <4>[ 9.225945] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10738 00:23:22.733217 <6>[ 9.234982] cfg80211: failed to load regulatory.db
10739 00:23:22.792521 <6>[ 9.291771] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10740 00:23:22.799388 <6>[ 9.299479] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10741 00:23:22.823955 <6>[ 9.326379] mt7921e 0000:01:00.0: ASIC revision: 79610010
10742 00:23:22.928601 <6>[ 9.427444] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10743 00:23:22.931516 <6>[ 9.427444]
10744 00:23:22.931609 done
10745 00:23:22.941473 Saving random seed: OK
10746 00:23:22.952658 Starting network: ip: RTNETLINK answers: File exists
10747 00:23:22.956420 FAIL
10748 00:23:22.994947 Starting dropbear sshd: <6>[ 9.497441] NET: Registered PF_INET6 protocol family
10749 00:23:23.001568 <6>[ 9.504061] Segment Routing with IPv6
10750 00:23:23.004965 <6>[ 9.508143] In-situ OAM (IOAM) with IPv6
10751 00:23:23.008632 OK
10752 00:23:23.017415 /bin/sh: can't access tty; job control turned off
10753 00:23:23.017754 Matched prompt #10: / #
10755 00:23:23.017957 Setting prompt string to ['/ #']
10756 00:23:23.018047 end: 2.2.5.1 login-action (duration 00:00:10) [common]
10758 00:23:23.018235 end: 2.2.5 auto-login-action (duration 00:00:10) [common]
10759 00:23:23.018317 start: 2.2.6 expect-shell-connection (timeout 00:03:32) [common]
10760 00:23:23.018386 Setting prompt string to ['/ #']
10761 00:23:23.018446 Forcing a shell prompt, looking for ['/ #']
10763 00:23:23.068677 / #
10764 00:23:23.068835 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10765 00:23:23.068917 Waiting using forced prompt support (timeout 00:02:30)
10766 00:23:23.074179
10767 00:23:23.074465 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10768 00:23:23.074563 start: 2.2.7 export-device-env (timeout 00:03:32) [common]
10769 00:23:23.074655 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10770 00:23:23.074740 end: 2.2 depthcharge-retry (duration 00:01:28) [common]
10771 00:23:23.074824 end: 2 depthcharge-action (duration 00:01:28) [common]
10772 00:23:23.074911 start: 3 lava-test-retry (timeout 00:01:00) [common]
10773 00:23:23.074993 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10774 00:23:23.075069 Using namespace: common
10776 00:23:23.175455 / # #
10777 00:23:23.175629 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10778 00:23:23.181004 #
10779 00:23:23.181313 Using /lava-14479190
10781 00:23:23.281704 / # export SHELL=/bin/sh
10782 00:23:23.281952 <6>[ 9.699169] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10783 00:23:23.287545 export SHELL=/bin/sh
10785 00:23:23.388070 / # . /lava-14479190/environment
10786 00:23:23.393467 . /lava-14479190/environment
10788 00:23:23.494067 / # /lava-14479190/bin/lava-test-runner /lava-14479190/0
10789 00:23:23.494226 Test shell timeout: 10s (minimum of the action and connection timeout)
10790 00:23:23.499906 /lava-14479190/bin/lava-test-runner /lava-14479190/0
10791 00:23:23.517084 + export 'TESTRUN_ID=0_dmesg'
10792 00:23:23.523676 + c<8>[ 10.025379] <LAVA_SIGNAL_STARTRUN 0_dmesg 14479190_1.5.2.3.1>
10793 00:23:23.523944 Received signal: <STARTRUN> 0_dmesg 14479190_1.5.2.3.1
10794 00:23:23.524017 Starting test lava.0_dmesg (14479190_1.5.2.3.1)
10795 00:23:23.524116 Skipping test definition patterns.
10796 00:23:23.527193 d /lava-14479190/0/tests/0_dmesg
10797 00:23:23.527277 + cat uuid
10798 00:23:23.530500 + UUID=14479190_1.5.2.3.1
10799 00:23:23.530585 + set +x
10800 00:23:23.536851 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
10801 00:23:23.546836 <8>[ 10.045162] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
10802 00:23:23.547099 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
10804 00:23:23.565728 <8>[ 10.064878] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
10805 00:23:23.565991 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
10807 00:23:23.588856 <8>[ 10.088168] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
10808 00:23:23.589115 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
10810 00:23:23.592514 + set +x
10811 00:23:23.595551 <8>[ 10.098144] <LAVA_SIGNAL_ENDRUN 0_dmesg 14479190_1.5.2.3.1>
10812 00:23:23.595834 Received signal: <ENDRUN> 0_dmesg 14479190_1.5.2.3.1
10813 00:23:23.595954 Ending use of test pattern.
10814 00:23:23.596017 Ending test lava.0_dmesg (14479190_1.5.2.3.1), duration 0.07
10816 00:23:23.599889 <LAVA_TEST_RUNNER EXIT>
10817 00:23:23.600140 ok: lava_test_shell seems to have completed
10818 00:23:23.600244 alert: pass
crit: pass
emerg: pass
10819 00:23:23.600331 end: 3.1 lava-test-shell (duration 00:00:01) [common]
10820 00:23:23.600413 end: 3 lava-test-retry (duration 00:00:01) [common]
10821 00:23:23.600538 start: 4 finalize (timeout 00:08:12) [common]
10822 00:23:23.600630 start: 4.1 power-off (timeout 00:00:30) [common]
10823 00:23:23.600803 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-2', '--port=1', '--command=off']
10824 00:23:23.804399 >> Command sent successfully.
10825 00:23:23.806659 Returned 0 in 0 seconds
10826 00:23:23.907056 end: 4.1 power-off (duration 00:00:00) [common]
10828 00:23:23.907377 start: 4.2 read-feedback (timeout 00:08:12) [common]
10829 00:23:23.907635 Listened to connection for namespace 'common' for up to 1s
10830 00:23:24.908677 Finalising connection for namespace 'common'
10831 00:23:24.908849 Disconnecting from shell: Finalise
10832 00:23:24.908929 / #
10833 00:23:25.009293 end: 4.2 read-feedback (duration 00:00:01) [common]
10834 00:23:25.009491 end: 4 finalize (duration 00:00:01) [common]
10835 00:23:25.009602 Cleaning after the job
10836 00:23:25.009697 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14479190/tftp-deploy-i9ftv1sc/ramdisk
10837 00:23:25.012029 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14479190/tftp-deploy-i9ftv1sc/kernel
10838 00:23:25.019498 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14479190/tftp-deploy-i9ftv1sc/dtb
10839 00:23:25.019671 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14479190/tftp-deploy-i9ftv1sc/modules
10840 00:23:25.025069 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14479190
10841 00:23:25.065083 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14479190
10842 00:23:25.065262 Job finished correctly