Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 33
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 26
1 00:23:46.526841 lava-dispatcher, installed at version: 2024.03
2 00:23:46.527045 start: 0 validate
3 00:23:46.527182 Start time: 2024-06-21 00:23:46.527174+00:00 (UTC)
4 00:23:46.527312 Using caching service: 'http://localhost/cache/?uri=%s'
5 00:23:46.527440 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 00:23:46.791293 Using caching service: 'http://localhost/cache/?uri=%s'
7 00:23:46.791461 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.94-cip23%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 00:23:47.042536 Using caching service: 'http://localhost/cache/?uri=%s'
9 00:23:47.042766 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.94-cip23%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 00:23:47.302393 Using caching service: 'http://localhost/cache/?uri=%s'
11 00:23:47.303005 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 00:23:47.562660 Using caching service: 'http://localhost/cache/?uri=%s'
13 00:23:47.563370 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.94-cip23%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 00:23:47.828069 validate duration: 1.30
16 00:23:47.828422 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 00:23:47.828558 start: 1.1 download-retry (timeout 00:10:00) [common]
18 00:23:47.828673 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 00:23:47.828821 Not decompressing ramdisk as can be used compressed.
20 00:23:47.828932 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/initrd.cpio.gz
21 00:23:47.829023 saving as /var/lib/lava/dispatcher/tmp/14479200/tftp-deploy-krd9ty9v/ramdisk/initrd.cpio.gz
22 00:23:47.829114 total size: 5628182 (5 MB)
23 00:23:47.830716 progress 0 % (0 MB)
24 00:23:47.832480 progress 5 % (0 MB)
25 00:23:47.834085 progress 10 % (0 MB)
26 00:23:47.835647 progress 15 % (0 MB)
27 00:23:47.837172 progress 20 % (1 MB)
28 00:23:47.838575 progress 25 % (1 MB)
29 00:23:47.840127 progress 30 % (1 MB)
30 00:23:47.841673 progress 35 % (1 MB)
31 00:23:47.843041 progress 40 % (2 MB)
32 00:23:47.844515 progress 45 % (2 MB)
33 00:23:47.845926 progress 50 % (2 MB)
34 00:23:47.847408 progress 55 % (2 MB)
35 00:23:47.848883 progress 60 % (3 MB)
36 00:23:47.850264 progress 65 % (3 MB)
37 00:23:47.851749 progress 70 % (3 MB)
38 00:23:47.853075 progress 75 % (4 MB)
39 00:23:47.854611 progress 80 % (4 MB)
40 00:23:47.855931 progress 85 % (4 MB)
41 00:23:47.857449 progress 90 % (4 MB)
42 00:23:47.858933 progress 95 % (5 MB)
43 00:23:47.860268 progress 100 % (5 MB)
44 00:23:47.860468 5 MB downloaded in 0.03 s (171.19 MB/s)
45 00:23:47.860616 end: 1.1.1 http-download (duration 00:00:00) [common]
47 00:23:47.860843 end: 1.1 download-retry (duration 00:00:00) [common]
48 00:23:47.860926 start: 1.2 download-retry (timeout 00:10:00) [common]
49 00:23:47.861081 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 00:23:47.861209 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.94-cip23/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 00:23:47.861304 saving as /var/lib/lava/dispatcher/tmp/14479200/tftp-deploy-krd9ty9v/kernel/Image
52 00:23:47.861396 total size: 54813184 (52 MB)
53 00:23:47.861456 No compression specified
54 00:23:47.862706 progress 0 % (0 MB)
55 00:23:47.876483 progress 5 % (2 MB)
56 00:23:47.890133 progress 10 % (5 MB)
57 00:23:47.903679 progress 15 % (7 MB)
58 00:23:47.917865 progress 20 % (10 MB)
59 00:23:47.931958 progress 25 % (13 MB)
60 00:23:47.945838 progress 30 % (15 MB)
61 00:23:47.959915 progress 35 % (18 MB)
62 00:23:47.973915 progress 40 % (20 MB)
63 00:23:47.987600 progress 45 % (23 MB)
64 00:23:48.001526 progress 50 % (26 MB)
65 00:23:48.015518 progress 55 % (28 MB)
66 00:23:48.029392 progress 60 % (31 MB)
67 00:23:48.043260 progress 65 % (34 MB)
68 00:23:48.056920 progress 70 % (36 MB)
69 00:23:48.070918 progress 75 % (39 MB)
70 00:23:48.084968 progress 80 % (41 MB)
71 00:23:48.098473 progress 85 % (44 MB)
72 00:23:48.112028 progress 90 % (47 MB)
73 00:23:48.125565 progress 95 % (49 MB)
74 00:23:48.138735 progress 100 % (52 MB)
75 00:23:48.138951 52 MB downloaded in 0.28 s (188.34 MB/s)
76 00:23:48.139097 end: 1.2.1 http-download (duration 00:00:00) [common]
78 00:23:48.139326 end: 1.2 download-retry (duration 00:00:00) [common]
79 00:23:48.139409 start: 1.3 download-retry (timeout 00:10:00) [common]
80 00:23:48.139490 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 00:23:48.139621 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.94-cip23/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 00:23:48.139687 saving as /var/lib/lava/dispatcher/tmp/14479200/tftp-deploy-krd9ty9v/dtb/mt8192-asurada-spherion-r0.dtb
83 00:23:48.139744 total size: 47258 (0 MB)
84 00:23:48.139801 No compression specified
85 00:23:48.140831 progress 69 % (0 MB)
86 00:23:48.141090 progress 100 % (0 MB)
87 00:23:48.141238 0 MB downloaded in 0.00 s (30.21 MB/s)
88 00:23:48.141415 end: 1.3.1 http-download (duration 00:00:00) [common]
90 00:23:48.141629 end: 1.3 download-retry (duration 00:00:00) [common]
91 00:23:48.141711 start: 1.4 download-retry (timeout 00:10:00) [common]
92 00:23:48.141792 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 00:23:48.141898 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/full.rootfs.tar.xz
94 00:23:48.141963 saving as /var/lib/lava/dispatcher/tmp/14479200/tftp-deploy-krd9ty9v/nfsrootfs/full.rootfs.tar
95 00:23:48.142022 total size: 107552908 (102 MB)
96 00:23:48.142081 Using unxz to decompress xz
97 00:23:48.146151 progress 0 % (0 MB)
98 00:23:48.417567 progress 5 % (5 MB)
99 00:23:48.729379 progress 10 % (10 MB)
100 00:23:49.032510 progress 15 % (15 MB)
101 00:23:49.344907 progress 20 % (20 MB)
102 00:23:49.600475 progress 25 % (25 MB)
103 00:23:49.889475 progress 30 % (30 MB)
104 00:23:50.193641 progress 35 % (35 MB)
105 00:23:50.355844 progress 40 % (41 MB)
106 00:23:50.546382 progress 45 % (46 MB)
107 00:23:50.842828 progress 50 % (51 MB)
108 00:23:51.145046 progress 55 % (56 MB)
109 00:23:51.466763 progress 60 % (61 MB)
110 00:23:51.784511 progress 65 % (66 MB)
111 00:23:52.096989 progress 70 % (71 MB)
112 00:23:52.426305 progress 75 % (76 MB)
113 00:23:52.719856 progress 80 % (82 MB)
114 00:23:53.022718 progress 85 % (87 MB)
115 00:23:53.326733 progress 90 % (92 MB)
116 00:23:53.633967 progress 95 % (97 MB)
117 00:23:53.952673 progress 100 % (102 MB)
118 00:23:53.957656 102 MB downloaded in 5.82 s (17.64 MB/s)
119 00:23:53.957959 end: 1.4.1 http-download (duration 00:00:06) [common]
121 00:23:53.958357 end: 1.4 download-retry (duration 00:00:06) [common]
122 00:23:53.958475 start: 1.5 download-retry (timeout 00:09:54) [common]
123 00:23:53.958588 start: 1.5.1 http-download (timeout 00:09:54) [common]
124 00:23:53.958765 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.94-cip23/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 00:23:53.958858 saving as /var/lib/lava/dispatcher/tmp/14479200/tftp-deploy-krd9ty9v/modules/modules.tar
126 00:23:53.958945 total size: 8618924 (8 MB)
127 00:23:53.959036 Using unxz to decompress xz
128 00:23:53.963496 progress 0 % (0 MB)
129 00:23:53.982881 progress 5 % (0 MB)
130 00:23:54.006566 progress 10 % (0 MB)
131 00:23:54.031273 progress 15 % (1 MB)
132 00:23:54.055431 progress 20 % (1 MB)
133 00:23:54.080098 progress 25 % (2 MB)
134 00:23:54.104145 progress 30 % (2 MB)
135 00:23:54.128702 progress 35 % (2 MB)
136 00:23:54.152550 progress 40 % (3 MB)
137 00:23:54.176426 progress 45 % (3 MB)
138 00:23:54.199596 progress 50 % (4 MB)
139 00:23:54.223695 progress 55 % (4 MB)
140 00:23:54.247738 progress 60 % (4 MB)
141 00:23:54.270805 progress 65 % (5 MB)
142 00:23:54.298067 progress 70 % (5 MB)
143 00:23:54.322246 progress 75 % (6 MB)
144 00:23:54.345381 progress 80 % (6 MB)
145 00:23:54.368389 progress 85 % (7 MB)
146 00:23:54.391514 progress 90 % (7 MB)
147 00:23:54.418674 progress 95 % (7 MB)
148 00:23:54.448814 progress 100 % (8 MB)
149 00:23:54.453449 8 MB downloaded in 0.49 s (16.62 MB/s)
150 00:23:54.453709 end: 1.5.1 http-download (duration 00:00:00) [common]
152 00:23:54.453987 end: 1.5 download-retry (duration 00:00:00) [common]
153 00:23:54.454082 start: 1.6 prepare-tftp-overlay (timeout 00:09:53) [common]
154 00:23:54.454180 start: 1.6.1 extract-nfsrootfs (timeout 00:09:53) [common]
155 00:23:56.495975 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14479200/extract-nfsrootfs-ini16oba
156 00:23:56.496174 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 00:23:56.496277 start: 1.6.2 lava-overlay (timeout 00:09:51) [common]
158 00:23:56.496435 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14479200/lava-overlay-9lsgrl46
159 00:23:56.496561 makedir: /var/lib/lava/dispatcher/tmp/14479200/lava-overlay-9lsgrl46/lava-14479200/bin
160 00:23:56.496661 makedir: /var/lib/lava/dispatcher/tmp/14479200/lava-overlay-9lsgrl46/lava-14479200/tests
161 00:23:56.496758 makedir: /var/lib/lava/dispatcher/tmp/14479200/lava-overlay-9lsgrl46/lava-14479200/results
162 00:23:56.496856 Creating /var/lib/lava/dispatcher/tmp/14479200/lava-overlay-9lsgrl46/lava-14479200/bin/lava-add-keys
163 00:23:56.496995 Creating /var/lib/lava/dispatcher/tmp/14479200/lava-overlay-9lsgrl46/lava-14479200/bin/lava-add-sources
164 00:23:56.497120 Creating /var/lib/lava/dispatcher/tmp/14479200/lava-overlay-9lsgrl46/lava-14479200/bin/lava-background-process-start
165 00:23:56.497244 Creating /var/lib/lava/dispatcher/tmp/14479200/lava-overlay-9lsgrl46/lava-14479200/bin/lava-background-process-stop
166 00:23:56.497474 Creating /var/lib/lava/dispatcher/tmp/14479200/lava-overlay-9lsgrl46/lava-14479200/bin/lava-common-functions
167 00:23:56.497597 Creating /var/lib/lava/dispatcher/tmp/14479200/lava-overlay-9lsgrl46/lava-14479200/bin/lava-echo-ipv4
168 00:23:56.497719 Creating /var/lib/lava/dispatcher/tmp/14479200/lava-overlay-9lsgrl46/lava-14479200/bin/lava-install-packages
169 00:23:56.497841 Creating /var/lib/lava/dispatcher/tmp/14479200/lava-overlay-9lsgrl46/lava-14479200/bin/lava-installed-packages
170 00:23:56.497961 Creating /var/lib/lava/dispatcher/tmp/14479200/lava-overlay-9lsgrl46/lava-14479200/bin/lava-os-build
171 00:23:56.498082 Creating /var/lib/lava/dispatcher/tmp/14479200/lava-overlay-9lsgrl46/lava-14479200/bin/lava-probe-channel
172 00:23:56.498223 Creating /var/lib/lava/dispatcher/tmp/14479200/lava-overlay-9lsgrl46/lava-14479200/bin/lava-probe-ip
173 00:23:56.498385 Creating /var/lib/lava/dispatcher/tmp/14479200/lava-overlay-9lsgrl46/lava-14479200/bin/lava-target-ip
174 00:23:56.498504 Creating /var/lib/lava/dispatcher/tmp/14479200/lava-overlay-9lsgrl46/lava-14479200/bin/lava-target-mac
175 00:23:56.498623 Creating /var/lib/lava/dispatcher/tmp/14479200/lava-overlay-9lsgrl46/lava-14479200/bin/lava-target-storage
176 00:23:56.498745 Creating /var/lib/lava/dispatcher/tmp/14479200/lava-overlay-9lsgrl46/lava-14479200/bin/lava-test-case
177 00:23:56.498866 Creating /var/lib/lava/dispatcher/tmp/14479200/lava-overlay-9lsgrl46/lava-14479200/bin/lava-test-event
178 00:23:56.498984 Creating /var/lib/lava/dispatcher/tmp/14479200/lava-overlay-9lsgrl46/lava-14479200/bin/lava-test-feedback
179 00:23:56.499103 Creating /var/lib/lava/dispatcher/tmp/14479200/lava-overlay-9lsgrl46/lava-14479200/bin/lava-test-raise
180 00:23:56.499222 Creating /var/lib/lava/dispatcher/tmp/14479200/lava-overlay-9lsgrl46/lava-14479200/bin/lava-test-reference
181 00:23:56.499343 Creating /var/lib/lava/dispatcher/tmp/14479200/lava-overlay-9lsgrl46/lava-14479200/bin/lava-test-runner
182 00:23:56.499463 Creating /var/lib/lava/dispatcher/tmp/14479200/lava-overlay-9lsgrl46/lava-14479200/bin/lava-test-set
183 00:23:56.499583 Creating /var/lib/lava/dispatcher/tmp/14479200/lava-overlay-9lsgrl46/lava-14479200/bin/lava-test-shell
184 00:23:56.499705 Updating /var/lib/lava/dispatcher/tmp/14479200/lava-overlay-9lsgrl46/lava-14479200/bin/lava-install-packages (oe)
185 00:23:56.499851 Updating /var/lib/lava/dispatcher/tmp/14479200/lava-overlay-9lsgrl46/lava-14479200/bin/lava-installed-packages (oe)
186 00:23:56.499968 Creating /var/lib/lava/dispatcher/tmp/14479200/lava-overlay-9lsgrl46/lava-14479200/environment
187 00:23:56.500060 LAVA metadata
188 00:23:56.500125 - LAVA_JOB_ID=14479200
189 00:23:56.500186 - LAVA_DISPATCHER_IP=192.168.201.1
190 00:23:56.500281 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:51) [common]
191 00:23:56.500346 skipped lava-vland-overlay
192 00:23:56.500417 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 00:23:56.500494 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:51) [common]
194 00:23:56.500554 skipped lava-multinode-overlay
195 00:23:56.500623 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 00:23:56.500698 start: 1.6.2.3 test-definition (timeout 00:09:51) [common]
197 00:23:56.500768 Loading test definitions
198 00:23:56.500853 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:51) [common]
199 00:23:56.500923 Using /lava-14479200 at stage 0
200 00:23:56.501225 uuid=14479200_1.6.2.3.1 testdef=None
201 00:23:56.501347 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 00:23:56.501429 start: 1.6.2.3.2 test-overlay (timeout 00:09:51) [common]
203 00:23:56.501955 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 00:23:56.502170 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:51) [common]
206 00:23:56.502784 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 00:23:56.503008 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:51) [common]
209 00:23:56.503600 runner path: /var/lib/lava/dispatcher/tmp/14479200/lava-overlay-9lsgrl46/lava-14479200/0/tests/0_dmesg test_uuid 14479200_1.6.2.3.1
210 00:23:56.503754 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 00:23:56.503954 Creating lava-test-runner.conf files
213 00:23:56.504032 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14479200/lava-overlay-9lsgrl46/lava-14479200/0 for stage 0
214 00:23:56.504193 - 0_dmesg
215 00:23:56.504291 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
216 00:23:56.504373 start: 1.6.2.4 compress-overlay (timeout 00:09:51) [common]
217 00:23:56.510299 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
218 00:23:56.510398 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:51) [common]
219 00:23:56.510481 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
220 00:23:56.510564 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
221 00:23:56.510645 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:51) [common]
222 00:23:56.674109 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
223 00:23:56.674489 start: 1.6.4 extract-modules (timeout 00:09:51) [common]
224 00:23:56.674602 extracting modules file /var/lib/lava/dispatcher/tmp/14479200/tftp-deploy-krd9ty9v/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14479200/extract-nfsrootfs-ini16oba
225 00:23:56.886204 extracting modules file /var/lib/lava/dispatcher/tmp/14479200/tftp-deploy-krd9ty9v/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14479200/extract-overlay-ramdisk-revp62gj/ramdisk
226 00:23:57.108686 end: 1.6.4 extract-modules (duration 00:00:00) [common]
227 00:23:57.108851 start: 1.6.5 apply-overlay-tftp (timeout 00:09:51) [common]
228 00:23:57.108944 [common] Applying overlay to NFS
229 00:23:57.109017 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14479200/compress-overlay-m8na4dd3/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14479200/extract-nfsrootfs-ini16oba
230 00:23:57.115484 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
231 00:23:57.115592 start: 1.6.6 configure-preseed-file (timeout 00:09:51) [common]
232 00:23:57.115682 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
233 00:23:57.115773 start: 1.6.7 compress-ramdisk (timeout 00:09:51) [common]
234 00:23:57.115854 Building ramdisk /var/lib/lava/dispatcher/tmp/14479200/extract-overlay-ramdisk-revp62gj/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14479200/extract-overlay-ramdisk-revp62gj/ramdisk
235 00:23:57.456610 >> 130487 blocks
236 00:23:59.459851 rename /var/lib/lava/dispatcher/tmp/14479200/extract-overlay-ramdisk-revp62gj/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14479200/tftp-deploy-krd9ty9v/ramdisk/ramdisk.cpio.gz
237 00:23:59.460326 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
238 00:23:59.460454 start: 1.6.8 prepare-kernel (timeout 00:09:48) [common]
239 00:23:59.460555 start: 1.6.8.1 prepare-fit (timeout 00:09:48) [common]
240 00:23:59.460657 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14479200/tftp-deploy-krd9ty9v/kernel/Image']
241 00:24:12.404696 Returned 0 in 12 seconds
242 00:24:12.505330 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14479200/tftp-deploy-krd9ty9v/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14479200/tftp-deploy-krd9ty9v/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14479200/tftp-deploy-krd9ty9v/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14479200/tftp-deploy-krd9ty9v/kernel/image.itb
243 00:24:12.862802 output: FIT description: Kernel Image image with one or more FDT blobs
244 00:24:12.863196 output: Created: Fri Jun 21 01:24:12 2024
245 00:24:12.863298 output: Image 0 (kernel-1)
246 00:24:12.863390 output: Description:
247 00:24:12.863487 output: Created: Fri Jun 21 01:24:12 2024
248 00:24:12.863576 output: Type: Kernel Image
249 00:24:12.863664 output: Compression: lzma compressed
250 00:24:12.863752 output: Data Size: 13124896 Bytes = 12817.28 KiB = 12.52 MiB
251 00:24:12.863842 output: Architecture: AArch64
252 00:24:12.863933 output: OS: Linux
253 00:24:12.864021 output: Load Address: 0x00000000
254 00:24:12.864104 output: Entry Point: 0x00000000
255 00:24:12.864186 output: Hash algo: crc32
256 00:24:12.864271 output: Hash value: ab2f7826
257 00:24:12.864353 output: Image 1 (fdt-1)
258 00:24:12.864435 output: Description: mt8192-asurada-spherion-r0
259 00:24:12.864517 output: Created: Fri Jun 21 01:24:12 2024
260 00:24:12.864599 output: Type: Flat Device Tree
261 00:24:12.864680 output: Compression: uncompressed
262 00:24:12.864761 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
263 00:24:12.864841 output: Architecture: AArch64
264 00:24:12.864922 output: Hash algo: crc32
265 00:24:12.865002 output: Hash value: 0f8e4d2e
266 00:24:12.865083 output: Image 2 (ramdisk-1)
267 00:24:12.865164 output: Description: unavailable
268 00:24:12.865244 output: Created: Fri Jun 21 01:24:12 2024
269 00:24:12.865312 output: Type: RAMDisk Image
270 00:24:12.865365 output: Compression: Unknown Compression
271 00:24:12.865418 output: Data Size: 18739174 Bytes = 18299.97 KiB = 17.87 MiB
272 00:24:12.865490 output: Architecture: AArch64
273 00:24:12.865586 output: OS: Linux
274 00:24:12.865673 output: Load Address: unavailable
275 00:24:12.865755 output: Entry Point: unavailable
276 00:24:12.865836 output: Hash algo: crc32
277 00:24:12.865917 output: Hash value: ed103b29
278 00:24:12.865999 output: Default Configuration: 'conf-1'
279 00:24:12.866098 output: Configuration 0 (conf-1)
280 00:24:12.866241 output: Description: mt8192-asurada-spherion-r0
281 00:24:12.866348 output: Kernel: kernel-1
282 00:24:12.866500 output: Init Ramdisk: ramdisk-1
283 00:24:12.866578 output: FDT: fdt-1
284 00:24:12.866631 output: Loadables: kernel-1
285 00:24:12.866684 output:
286 00:24:12.866887 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
287 00:24:12.866983 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
288 00:24:12.867093 end: 1.6 prepare-tftp-overlay (duration 00:00:18) [common]
289 00:24:12.867183 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:35) [common]
290 00:24:12.867261 No LXC device requested
291 00:24:12.867338 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
292 00:24:12.867423 start: 1.8 deploy-device-env (timeout 00:09:35) [common]
293 00:24:12.867499 end: 1.8 deploy-device-env (duration 00:00:00) [common]
294 00:24:12.867566 Checking files for TFTP limit of 4294967296 bytes.
295 00:24:12.868055 end: 1 tftp-deploy (duration 00:00:25) [common]
296 00:24:12.868161 start: 2 depthcharge-action (timeout 00:05:00) [common]
297 00:24:12.868252 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
298 00:24:12.868374 substitutions:
299 00:24:12.868441 - {DTB}: 14479200/tftp-deploy-krd9ty9v/dtb/mt8192-asurada-spherion-r0.dtb
300 00:24:12.868501 - {INITRD}: 14479200/tftp-deploy-krd9ty9v/ramdisk/ramdisk.cpio.gz
301 00:24:12.868559 - {KERNEL}: 14479200/tftp-deploy-krd9ty9v/kernel/Image
302 00:24:12.868614 - {LAVA_MAC}: None
303 00:24:12.868669 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14479200/extract-nfsrootfs-ini16oba
304 00:24:12.868724 - {NFS_SERVER_IP}: 192.168.201.1
305 00:24:12.868777 - {PRESEED_CONFIG}: None
306 00:24:12.868831 - {PRESEED_LOCAL}: None
307 00:24:12.868886 - {RAMDISK}: 14479200/tftp-deploy-krd9ty9v/ramdisk/ramdisk.cpio.gz
308 00:24:12.868939 - {ROOT_PART}: None
309 00:24:12.868993 - {ROOT}: None
310 00:24:12.869046 - {SERVER_IP}: 192.168.201.1
311 00:24:12.869098 - {TEE}: None
312 00:24:12.869151 Parsed boot commands:
313 00:24:12.869204 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
314 00:24:12.869456 Parsed boot commands: tftpboot 192.168.201.1 14479200/tftp-deploy-krd9ty9v/kernel/image.itb 14479200/tftp-deploy-krd9ty9v/kernel/cmdline
315 00:24:12.869542 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
316 00:24:12.869625 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
317 00:24:12.869719 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
318 00:24:12.869800 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
319 00:24:12.869867 Not connected, no need to disconnect.
320 00:24:12.869938 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
321 00:24:12.870016 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
322 00:24:12.870082 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-2'
323 00:24:12.873779 Setting prompt string to ['lava-test: # ']
324 00:24:12.874153 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
325 00:24:12.874255 end: 2.2.1 reset-connection (duration 00:00:00) [common]
326 00:24:12.874351 start: 2.2.2 reset-device (timeout 00:05:00) [common]
327 00:24:12.874442 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
328 00:24:12.874682 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-2']
329 00:24:26.764198 Returned 0 in 13 seconds
330 00:24:26.864850 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
332 00:24:26.865170 end: 2.2.2 reset-device (duration 00:00:14) [common]
333 00:24:26.865271 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
334 00:24:26.865431 Setting prompt string to 'Starting depthcharge on Spherion...'
335 00:24:26.865496 Changing prompt to 'Starting depthcharge on Spherion...'
336 00:24:26.865565 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
337 00:24:26.865969 [Enter `^Ec?' for help]
338 00:24:26.866050
339 00:24:26.866116
340 00:24:26.866177 F0: 102B 0000
341 00:24:26.866236
342 00:24:26.866295 F3: 1001 0000 [0200]
343 00:24:26.866352
344 00:24:26.866410 F3: 1001 0000
345 00:24:26.866466
346 00:24:26.866520 F7: 102D 0000
347 00:24:26.866573
348 00:24:26.866626 F1: 0000 0000
349 00:24:26.866679
350 00:24:26.866731 V0: 0000 0000 [0001]
351 00:24:26.866784
352 00:24:26.866835 00: 0007 8000
353 00:24:26.866892
354 00:24:26.866944 01: 0000 0000
355 00:24:26.866998
356 00:24:26.867051 BP: 0C00 0209 [0000]
357 00:24:26.867103
358 00:24:26.867155 G0: 1182 0000
359 00:24:26.867208
360 00:24:26.867260 EC: 0000 0021 [4000]
361 00:24:26.867311
362 00:24:26.867363 S7: 0000 0000 [0000]
363 00:24:26.867415
364 00:24:26.867467 CC: 0000 0000 [0001]
365 00:24:26.867520
366 00:24:26.867572 T0: 0000 0040 [010F]
367 00:24:26.867624
368 00:24:26.867676 Jump to BL
369 00:24:26.867728
370 00:24:26.867780
371 00:24:26.867833
372 00:24:26.867885 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
373 00:24:26.867941 ARM64: Exception handlers installed.
374 00:24:26.867994 ARM64: Testing exception
375 00:24:26.868046 ARM64: Done test exception
376 00:24:26.868099 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
377 00:24:26.868152 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
378 00:24:26.868205 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
379 00:24:26.868258 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
380 00:24:26.868311 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
381 00:24:26.868364 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
382 00:24:26.868416 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
383 00:24:26.868469 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
384 00:24:26.868522 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
385 00:24:26.868575 WDT: Last reset was cold boot
386 00:24:26.868627 SPI1(PAD0) initialized at 2873684 Hz
387 00:24:26.868680 SPI5(PAD0) initialized at 992727 Hz
388 00:24:26.868732 VBOOT: Loading verstage.
389 00:24:26.868784 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
390 00:24:26.868837 FMAP: Found "FLASH" version 1.1 at 0x20000.
391 00:24:26.868890 FMAP: base = 0x0 size = 0x800000 #areas = 25
392 00:24:26.868943 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
393 00:24:26.868995 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
394 00:24:26.869048 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
395 00:24:26.869100 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
396 00:24:26.869153
397 00:24:26.869204
398 00:24:26.869261 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
399 00:24:26.869351 ARM64: Exception handlers installed.
400 00:24:26.869403 ARM64: Testing exception
401 00:24:26.869455 ARM64: Done test exception
402 00:24:26.869507 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
403 00:24:26.869560 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
404 00:24:26.869612 Probing TPM: . done!
405 00:24:26.869664 TPM ready after 0 ms
406 00:24:26.869716 Connected to device vid:did:rid of 1ae0:0028:00
407 00:24:26.869769 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
408 00:24:26.869822 Initialized TPM device CR50 revision 0
409 00:24:26.869875 tlcl_send_startup: Startup return code is 0
410 00:24:26.869927 TPM: setup succeeded
411 00:24:26.869980 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
412 00:24:26.870033 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
413 00:24:26.870085 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
414 00:24:26.870138 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
415 00:24:26.870190 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
416 00:24:26.870242 in-header: 03 07 00 00 08 00 00 00
417 00:24:26.870294 in-data: aa e4 47 04 13 02 00 00
418 00:24:26.870346 Chrome EC: UHEPI supported
419 00:24:26.870397 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
420 00:24:26.870449 in-header: 03 a9 00 00 08 00 00 00
421 00:24:26.870501 in-data: 84 60 60 08 00 00 00 00
422 00:24:26.870552 Phase 1
423 00:24:26.870604 FMAP: area GBB found @ 3f5000 (12032 bytes)
424 00:24:26.870656 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
425 00:24:26.870709 VB2:vb2_check_recovery() Recovery was requested manually
426 00:24:26.870761 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
427 00:24:26.870813 Recovery requested (1009000e)
428 00:24:26.870865 TPM: Extending digest for VBOOT: boot mode into PCR 0
429 00:24:26.870918 tlcl_extend: response is 0
430 00:24:26.870970 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
431 00:24:26.871022 tlcl_extend: response is 0
432 00:24:26.871074 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
433 00:24:26.871127 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
434 00:24:26.871179 BS: bootblock times (exec / console): total (unknown) / 148 ms
435 00:24:26.871231
436 00:24:26.871283
437 00:24:26.871335 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
438 00:24:26.871388 ARM64: Exception handlers installed.
439 00:24:26.871440 ARM64: Testing exception
440 00:24:26.871492 ARM64: Done test exception
441 00:24:26.871544 pmic_efuse_setting: Set efuses in 11 msecs
442 00:24:26.871596 pmwrap_interface_init: Select PMIF_VLD_RDY
443 00:24:26.871648 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
444 00:24:26.871700 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
445 00:24:26.871942 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
446 00:24:26.872006 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
447 00:24:26.872060 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
448 00:24:26.872113 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
449 00:24:26.872166 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
450 00:24:26.872219 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
451 00:24:26.872271 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
452 00:24:26.872323 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
453 00:24:26.872376 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
454 00:24:26.872429 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
455 00:24:26.872481 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
456 00:24:26.872533 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
457 00:24:26.872585 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
458 00:24:26.872638 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
459 00:24:26.872690 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
460 00:24:26.872742 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
461 00:24:26.872794 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
462 00:24:26.872846 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
463 00:24:26.872898 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
464 00:24:26.872950 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
465 00:24:26.873002 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
466 00:24:26.873054 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
467 00:24:26.873106 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
468 00:24:26.873159 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
469 00:24:26.873211 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
470 00:24:26.873287 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
471 00:24:26.873354 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
472 00:24:26.873407 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
473 00:24:26.873459 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
474 00:24:26.873511 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
475 00:24:26.873563 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
476 00:24:26.873616 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
477 00:24:26.873668 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
478 00:24:26.873734 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
479 00:24:26.873788 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
480 00:24:26.873840 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
481 00:24:26.873892 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
482 00:24:26.873944 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
483 00:24:26.873997 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
484 00:24:26.874049 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
485 00:24:26.874101 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
486 00:24:26.874153 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
487 00:24:26.874205 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
488 00:24:26.874257 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
489 00:24:26.874309 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
490 00:24:26.874361 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
491 00:24:26.874413 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
492 00:24:26.874465 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
493 00:24:26.874516 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
494 00:24:26.874568 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
495 00:24:26.874621 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
496 00:24:26.874674 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
497 00:24:26.874725 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
498 00:24:26.874778 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
499 00:24:26.874831 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
500 00:24:26.874883 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
501 00:24:26.874935 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
502 00:24:26.874987 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x32
503 00:24:26.875040 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
504 00:24:26.875092 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
505 00:24:26.875144 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
506 00:24:26.875197 [RTC]rtc_get_frequency_meter,154: input=15, output=855
507 00:24:26.875249 [RTC]rtc_get_frequency_meter,154: input=7, output=726
508 00:24:26.875301 [RTC]rtc_get_frequency_meter,154: input=11, output=790
509 00:24:26.875353 [RTC]rtc_get_frequency_meter,154: input=13, output=821
510 00:24:26.875405 [RTC]rtc_get_frequency_meter,154: input=12, output=805
511 00:24:26.875457 [RTC]rtc_get_frequency_meter,154: input=11, output=790
512 00:24:26.875509 [RTC]rtc_get_frequency_meter,154: input=12, output=805
513 00:24:26.875561 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
514 00:24:26.875613 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
515 00:24:26.875850 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
516 00:24:26.875911 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
517 00:24:26.875964 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
518 00:24:26.876017 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
519 00:24:26.876069 ADC[4]: Raw value=903694 ID=7
520 00:24:26.876121 ADC[3]: Raw value=213916 ID=1
521 00:24:26.876173 RAM Code: 0x71
522 00:24:26.876224 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
523 00:24:26.876277 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
524 00:24:26.876330 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
525 00:24:26.876383 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
526 00:24:26.876435 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
527 00:24:26.876488 in-header: 03 07 00 00 08 00 00 00
528 00:24:26.876540 in-data: aa e4 47 04 13 02 00 00
529 00:24:26.876592 Chrome EC: UHEPI supported
530 00:24:26.876644 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
531 00:24:26.876696 in-header: 03 a9 00 00 08 00 00 00
532 00:24:26.876748 in-data: 84 60 60 08 00 00 00 00
533 00:24:26.876801 MRC: failed to locate region type 0.
534 00:24:26.876853 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
535 00:24:26.876906 DRAM-K: Running full calibration
536 00:24:26.876958 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
537 00:24:26.877011 header.status = 0x0
538 00:24:26.877062 header.version = 0x6 (expected: 0x6)
539 00:24:26.877115 header.size = 0xd00 (expected: 0xd00)
540 00:24:26.877166 header.flags = 0x0
541 00:24:26.877218 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
542 00:24:26.877295 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
543 00:24:26.877363 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
544 00:24:26.877415 dram_init: ddr_geometry: 2
545 00:24:26.877467 [EMI] MDL number = 2
546 00:24:26.877519 [EMI] Get MDL freq = 0
547 00:24:26.877571 dram_init: ddr_type: 0
548 00:24:26.877622 is_discrete_lpddr4: 1
549 00:24:26.877674 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
550 00:24:26.877725
551 00:24:26.877777
552 00:24:26.877829 [Bian_co] ETT version 0.0.0.1
553 00:24:26.877882 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
554 00:24:26.877934
555 00:24:26.877985 dramc_set_vcore_voltage set vcore to 650000
556 00:24:26.878038 Read voltage for 800, 4
557 00:24:26.878089 Vio18 = 0
558 00:24:26.878141 Vcore = 650000
559 00:24:26.878193 Vdram = 0
560 00:24:26.878245 Vddq = 0
561 00:24:26.878296 Vmddr = 0
562 00:24:26.878347 dram_init: config_dvfs: 1
563 00:24:26.878399 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
564 00:24:26.878451 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
565 00:24:26.878503 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
566 00:24:26.878555 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
567 00:24:26.878607 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
568 00:24:26.878659 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
569 00:24:26.878711 MEM_TYPE=3, freq_sel=18
570 00:24:26.878762 sv_algorithm_assistance_LP4_1600
571 00:24:26.878815 ============ PULL DRAM RESETB DOWN ============
572 00:24:26.878869 ========== PULL DRAM RESETB DOWN end =========
573 00:24:26.878921 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
574 00:24:26.878973 ===================================
575 00:24:26.879026 LPDDR4 DRAM CONFIGURATION
576 00:24:26.879078 ===================================
577 00:24:26.879129 EX_ROW_EN[0] = 0x0
578 00:24:26.879181 EX_ROW_EN[1] = 0x0
579 00:24:26.879233 LP4Y_EN = 0x0
580 00:24:26.879284 WORK_FSP = 0x0
581 00:24:26.879336 WL = 0x2
582 00:24:26.879388 RL = 0x2
583 00:24:26.879439 BL = 0x2
584 00:24:26.879491 RPST = 0x0
585 00:24:26.879543 RD_PRE = 0x0
586 00:24:26.879595 WR_PRE = 0x1
587 00:24:26.879646 WR_PST = 0x0
588 00:24:26.879698 DBI_WR = 0x0
589 00:24:26.879750 DBI_RD = 0x0
590 00:24:26.879801 OTF = 0x1
591 00:24:26.879853 ===================================
592 00:24:26.879905 ===================================
593 00:24:26.879957 ANA top config
594 00:24:26.880009 ===================================
595 00:24:26.880060 DLL_ASYNC_EN = 0
596 00:24:26.880112 ALL_SLAVE_EN = 1
597 00:24:26.880165 NEW_RANK_MODE = 1
598 00:24:26.880217 DLL_IDLE_MODE = 1
599 00:24:26.880269 LP45_APHY_COMB_EN = 1
600 00:24:26.880321 TX_ODT_DIS = 1
601 00:24:26.880373 NEW_8X_MODE = 1
602 00:24:26.880425 ===================================
603 00:24:26.880477 ===================================
604 00:24:26.880528 data_rate = 1600
605 00:24:26.880580 CKR = 1
606 00:24:26.880632 DQ_P2S_RATIO = 8
607 00:24:26.880684 ===================================
608 00:24:26.880735 CA_P2S_RATIO = 8
609 00:24:26.880787 DQ_CA_OPEN = 0
610 00:24:26.880838 DQ_SEMI_OPEN = 0
611 00:24:26.880890 CA_SEMI_OPEN = 0
612 00:24:26.880941 CA_FULL_RATE = 0
613 00:24:26.880993 DQ_CKDIV4_EN = 1
614 00:24:26.881044 CA_CKDIV4_EN = 1
615 00:24:26.881096 CA_PREDIV_EN = 0
616 00:24:26.881147 PH8_DLY = 0
617 00:24:26.881198 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
618 00:24:26.881250 DQ_AAMCK_DIV = 4
619 00:24:26.881344 CA_AAMCK_DIV = 4
620 00:24:26.881396 CA_ADMCK_DIV = 4
621 00:24:26.881447 DQ_TRACK_CA_EN = 0
622 00:24:26.881499 CA_PICK = 800
623 00:24:26.881551 CA_MCKIO = 800
624 00:24:26.881603 MCKIO_SEMI = 0
625 00:24:26.881654 PLL_FREQ = 3068
626 00:24:26.881706 DQ_UI_PI_RATIO = 32
627 00:24:26.881758 CA_UI_PI_RATIO = 0
628 00:24:26.881810 ===================================
629 00:24:26.881862 ===================================
630 00:24:26.881914 memory_type:LPDDR4
631 00:24:26.881965 GP_NUM : 10
632 00:24:26.882017 SRAM_EN : 1
633 00:24:26.882069 MD32_EN : 0
634 00:24:26.882322 ===================================
635 00:24:26.882382 [ANA_INIT] >>>>>>>>>>>>>>
636 00:24:26.882436 <<<<<< [CONFIGURE PHASE]: ANA_TX
637 00:24:26.882490 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
638 00:24:26.882543 ===================================
639 00:24:26.882595 data_rate = 1600,PCW = 0X7600
640 00:24:26.882647 ===================================
641 00:24:26.882699 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
642 00:24:26.882752 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
643 00:24:26.882805 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
644 00:24:26.882857 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
645 00:24:26.882910 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
646 00:24:26.882962 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
647 00:24:26.883015 [ANA_INIT] flow start
648 00:24:26.883067 [ANA_INIT] PLL >>>>>>>>
649 00:24:26.883119 [ANA_INIT] PLL <<<<<<<<
650 00:24:26.883170 [ANA_INIT] MIDPI >>>>>>>>
651 00:24:26.883222 [ANA_INIT] MIDPI <<<<<<<<
652 00:24:26.883273 [ANA_INIT] DLL >>>>>>>>
653 00:24:26.883325 [ANA_INIT] flow end
654 00:24:26.883377 ============ LP4 DIFF to SE enter ============
655 00:24:26.883430 ============ LP4 DIFF to SE exit ============
656 00:24:26.883482 [ANA_INIT] <<<<<<<<<<<<<
657 00:24:26.883534 [Flow] Enable top DCM control >>>>>
658 00:24:26.883586 [Flow] Enable top DCM control <<<<<
659 00:24:26.883638 Enable DLL master slave shuffle
660 00:24:26.883691 ==============================================================
661 00:24:26.883743 Gating Mode config
662 00:24:26.883795 ==============================================================
663 00:24:26.883855 Config description:
664 00:24:26.883910 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
665 00:24:26.883963 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
666 00:24:26.884016 SELPH_MODE 0: By rank 1: By Phase
667 00:24:26.884069 ==============================================================
668 00:24:26.884121 GAT_TRACK_EN = 1
669 00:24:26.884174 RX_GATING_MODE = 2
670 00:24:26.884226 RX_GATING_TRACK_MODE = 2
671 00:24:26.884279 SELPH_MODE = 1
672 00:24:26.884330 PICG_EARLY_EN = 1
673 00:24:26.884383 VALID_LAT_VALUE = 1
674 00:24:26.884434 ==============================================================
675 00:24:26.884487 Enter into Gating configuration >>>>
676 00:24:26.884539 Exit from Gating configuration <<<<
677 00:24:26.884591 Enter into DVFS_PRE_config >>>>>
678 00:24:26.884643 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
679 00:24:26.884698 Exit from DVFS_PRE_config <<<<<
680 00:24:26.884749 Enter into PICG configuration >>>>
681 00:24:26.884801 Exit from PICG configuration <<<<
682 00:24:26.884852 [RX_INPUT] configuration >>>>>
683 00:24:26.884904 [RX_INPUT] configuration <<<<<
684 00:24:26.884955 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
685 00:24:26.885008 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
686 00:24:26.885060 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
687 00:24:26.885112 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
688 00:24:26.885165 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
689 00:24:26.885217 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
690 00:24:26.885280 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
691 00:24:26.885372 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
692 00:24:26.885424 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
693 00:24:26.885477 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
694 00:24:26.885528 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
695 00:24:26.885580 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
696 00:24:26.885632 ===================================
697 00:24:26.885684 LPDDR4 DRAM CONFIGURATION
698 00:24:26.885737 ===================================
699 00:24:26.885788 EX_ROW_EN[0] = 0x0
700 00:24:26.885840 EX_ROW_EN[1] = 0x0
701 00:24:26.885892 LP4Y_EN = 0x0
702 00:24:26.885944 WORK_FSP = 0x0
703 00:24:26.885996 WL = 0x2
704 00:24:26.886047 RL = 0x2
705 00:24:26.886099 BL = 0x2
706 00:24:26.886151 RPST = 0x0
707 00:24:26.886202 RD_PRE = 0x0
708 00:24:26.886254 WR_PRE = 0x1
709 00:24:26.886306 WR_PST = 0x0
710 00:24:26.886357 DBI_WR = 0x0
711 00:24:26.886409 DBI_RD = 0x0
712 00:24:26.886461 OTF = 0x1
713 00:24:26.886513 ===================================
714 00:24:26.886565 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
715 00:24:26.886617 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
716 00:24:26.886669 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
717 00:24:26.886721 ===================================
718 00:24:26.886773 LPDDR4 DRAM CONFIGURATION
719 00:24:26.886825 ===================================
720 00:24:26.886877 EX_ROW_EN[0] = 0x10
721 00:24:26.886929 EX_ROW_EN[1] = 0x0
722 00:24:26.886981 LP4Y_EN = 0x0
723 00:24:26.887032 WORK_FSP = 0x0
724 00:24:26.887084 WL = 0x2
725 00:24:26.887136 RL = 0x2
726 00:24:26.887188 BL = 0x2
727 00:24:26.887239 RPST = 0x0
728 00:24:26.887290 RD_PRE = 0x0
729 00:24:26.887342 WR_PRE = 0x1
730 00:24:26.887393 WR_PST = 0x0
731 00:24:26.887445 DBI_WR = 0x0
732 00:24:26.887496 DBI_RD = 0x0
733 00:24:26.887548 OTF = 0x1
734 00:24:26.887599 ===================================
735 00:24:26.887651 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
736 00:24:26.887704 nWR fixed to 40
737 00:24:26.887756 [ModeRegInit_LP4] CH0 RK0
738 00:24:26.887808 [ModeRegInit_LP4] CH0 RK1
739 00:24:26.887874 [ModeRegInit_LP4] CH1 RK0
740 00:24:26.887950 [ModeRegInit_LP4] CH1 RK1
741 00:24:26.888024 match AC timing 13
742 00:24:26.888078 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
743 00:24:26.888324 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
744 00:24:26.888383 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
745 00:24:26.888438 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
746 00:24:26.888492 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
747 00:24:26.888544 [EMI DOE] emi_dcm 0
748 00:24:26.888597 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
749 00:24:26.888649 ==
750 00:24:26.888702 Dram Type= 6, Freq= 0, CH_0, rank 0
751 00:24:26.888754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
752 00:24:26.888807 ==
753 00:24:26.888860 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
754 00:24:26.888913 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
755 00:24:26.888965 [CA 0] Center 38 (7~69) winsize 63
756 00:24:26.889019 [CA 1] Center 37 (6~68) winsize 63
757 00:24:26.889071 [CA 2] Center 34 (4~65) winsize 62
758 00:24:26.889123 [CA 3] Center 34 (4~65) winsize 62
759 00:24:26.889175 [CA 4] Center 33 (3~64) winsize 62
760 00:24:26.889227 [CA 5] Center 33 (3~64) winsize 62
761 00:24:26.889312
762 00:24:26.889379 [CmdBusTrainingLP45] Vref(ca) range 1: 34
763 00:24:26.889432
764 00:24:26.889484 [CATrainingPosCal] consider 1 rank data
765 00:24:26.889536 u2DelayCellTimex100 = 270/100 ps
766 00:24:26.889589 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
767 00:24:26.889641 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
768 00:24:26.889694 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
769 00:24:26.889745 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
770 00:24:26.889797 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
771 00:24:26.889849 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
772 00:24:26.889901
773 00:24:26.889952 CA PerBit enable=1, Macro0, CA PI delay=33
774 00:24:26.890004
775 00:24:26.890056 [CBTSetCACLKResult] CA Dly = 33
776 00:24:26.890108 CS Dly: 5 (0~36)
777 00:24:26.890159 ==
778 00:24:26.890211 Dram Type= 6, Freq= 0, CH_0, rank 1
779 00:24:26.890263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
780 00:24:26.890316 ==
781 00:24:26.890367 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
782 00:24:26.890420 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
783 00:24:26.890472 [CA 0] Center 38 (7~69) winsize 63
784 00:24:26.890525 [CA 1] Center 37 (7~68) winsize 62
785 00:24:26.890576 [CA 2] Center 35 (4~66) winsize 63
786 00:24:26.890628 [CA 3] Center 35 (4~66) winsize 63
787 00:24:26.890680 [CA 4] Center 34 (3~65) winsize 63
788 00:24:26.890732 [CA 5] Center 33 (3~64) winsize 62
789 00:24:26.890784
790 00:24:26.890835 [CmdBusTrainingLP45] Vref(ca) range 1: 34
791 00:24:26.890886
792 00:24:26.890938 [CATrainingPosCal] consider 2 rank data
793 00:24:26.890990 u2DelayCellTimex100 = 270/100 ps
794 00:24:26.891042 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
795 00:24:26.891094 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
796 00:24:26.891146 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
797 00:24:26.891198 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
798 00:24:26.891250 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
799 00:24:26.891301 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
800 00:24:26.891353
801 00:24:26.891404 CA PerBit enable=1, Macro0, CA PI delay=33
802 00:24:26.891456
803 00:24:26.891507 [CBTSetCACLKResult] CA Dly = 33
804 00:24:26.891559 CS Dly: 6 (0~38)
805 00:24:26.891610
806 00:24:26.891662 ----->DramcWriteLeveling(PI) begin...
807 00:24:26.891715 ==
808 00:24:26.891768 Dram Type= 6, Freq= 0, CH_0, rank 0
809 00:24:26.891820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
810 00:24:26.891872 ==
811 00:24:26.891923 Write leveling (Byte 0): 32 => 32
812 00:24:26.892018 Write leveling (Byte 1): 30 => 30
813 00:24:26.892119 DramcWriteLeveling(PI) end<-----
814 00:24:26.892175
815 00:24:26.892228 ==
816 00:24:26.892280 Dram Type= 6, Freq= 0, CH_0, rank 0
817 00:24:26.892333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
818 00:24:26.892388 ==
819 00:24:26.892441 [Gating] SW mode calibration
820 00:24:26.892493 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
821 00:24:26.892546 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
822 00:24:26.892599 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
823 00:24:26.892652 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
824 00:24:26.892705 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
825 00:24:26.892757 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 00:24:26.892810 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 00:24:26.892863 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 00:24:26.892916 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 00:24:26.892968 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 00:24:26.893021 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 00:24:26.893073 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 00:24:26.893126 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 00:24:26.893178 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
834 00:24:26.893230 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
835 00:24:26.893309 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
836 00:24:26.893376 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
837 00:24:26.893428 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
838 00:24:26.893481 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 00:24:26.893533 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
840 00:24:26.893585 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
841 00:24:26.893637 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
842 00:24:26.893690 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 00:24:26.893742 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 00:24:26.893794 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 00:24:26.893846 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 00:24:26.893902 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
847 00:24:26.893957 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
848 00:24:26.894013 0 9 8 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
849 00:24:26.894065 0 9 12 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
850 00:24:26.894117 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
851 00:24:26.894361 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
852 00:24:26.894425 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
853 00:24:26.894479 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
854 00:24:26.894531 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
855 00:24:26.894584 0 10 4 | B1->B0 | 3434 3232 | 1 0 | (1 1) (1 0)
856 00:24:26.894636 0 10 8 | B1->B0 | 3131 2424 | 1 0 | (1 0) (0 0)
857 00:24:26.894689 0 10 12 | B1->B0 | 2828 2323 | 0 0 | (1 1) (0 0)
858 00:24:26.894741 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 00:24:26.894794 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 00:24:26.894846 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 00:24:26.894898 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 00:24:26.894950 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 00:24:26.895003 0 11 4 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (1 1)
864 00:24:26.895055 0 11 8 | B1->B0 | 2828 4242 | 0 1 | (0 0) (0 0)
865 00:24:26.895107 0 11 12 | B1->B0 | 3c3c 4646 | 0 0 | (1 1) (0 0)
866 00:24:26.895159 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
867 00:24:26.895211 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
868 00:24:26.895263 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
869 00:24:26.895315 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
870 00:24:26.895367 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
871 00:24:26.895419 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
872 00:24:26.895471 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
873 00:24:26.895523 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
874 00:24:26.895575 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
875 00:24:26.895627 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 00:24:26.895679 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 00:24:26.895731 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 00:24:26.895783 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 00:24:26.895835 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 00:24:26.895886 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 00:24:26.895938 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 00:24:26.895989 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 00:24:26.896041 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 00:24:26.896093 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
885 00:24:26.896144 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
886 00:24:26.896196 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
887 00:24:26.896248 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
888 00:24:26.896300 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
889 00:24:26.896352 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
890 00:24:26.896403 Total UI for P1: 0, mck2ui 16
891 00:24:26.896456 best dqsien dly found for B0: ( 0, 14, 8)
892 00:24:26.896508 Total UI for P1: 0, mck2ui 16
893 00:24:26.896561 best dqsien dly found for B1: ( 0, 14, 8)
894 00:24:26.896613 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
895 00:24:26.896666 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
896 00:24:26.896718
897 00:24:26.896770 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
898 00:24:26.896822 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
899 00:24:26.896874 [Gating] SW calibration Done
900 00:24:26.896926 ==
901 00:24:26.896978 Dram Type= 6, Freq= 0, CH_0, rank 0
902 00:24:26.897030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
903 00:24:26.897082 ==
904 00:24:26.897134 RX Vref Scan: 0
905 00:24:26.897186
906 00:24:26.897237 RX Vref 0 -> 0, step: 1
907 00:24:26.897333
908 00:24:26.897386 RX Delay -130 -> 252, step: 16
909 00:24:26.897439 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
910 00:24:26.897492 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
911 00:24:26.897544 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
912 00:24:26.897596 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
913 00:24:26.897648 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
914 00:24:26.897700 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
915 00:24:26.897752 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
916 00:24:26.897803 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
917 00:24:26.897856 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
918 00:24:26.897907 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
919 00:24:26.897959 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
920 00:24:26.898011 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
921 00:24:26.898063 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
922 00:24:26.898115 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
923 00:24:26.898167 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
924 00:24:26.898219 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
925 00:24:26.898271 ==
926 00:24:26.898323 Dram Type= 6, Freq= 0, CH_0, rank 0
927 00:24:26.898375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
928 00:24:26.898427 ==
929 00:24:26.898479 DQS Delay:
930 00:24:26.898531 DQS0 = 0, DQS1 = 0
931 00:24:26.898583 DQM Delay:
932 00:24:26.898634 DQM0 = 87, DQM1 = 75
933 00:24:26.898686 DQ Delay:
934 00:24:26.898737 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
935 00:24:26.898789 DQ4 =93, DQ5 =69, DQ6 =101, DQ7 =93
936 00:24:26.898841 DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =69
937 00:24:26.898893 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
938 00:24:26.898945
939 00:24:26.899000
940 00:24:26.899051 ==
941 00:24:26.899102 Dram Type= 6, Freq= 0, CH_0, rank 0
942 00:24:26.899154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
943 00:24:26.899207 ==
944 00:24:26.899258
945 00:24:26.899309
946 00:24:26.899360 TX Vref Scan disable
947 00:24:26.899411 == TX Byte 0 ==
948 00:24:26.899463 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
949 00:24:26.899515 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
950 00:24:26.899567 == TX Byte 1 ==
951 00:24:26.899619 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
952 00:24:26.899670 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
953 00:24:26.899723 ==
954 00:24:26.899774 Dram Type= 6, Freq= 0, CH_0, rank 0
955 00:24:26.899825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
956 00:24:26.899877 ==
957 00:24:26.899928 TX Vref=22, minBit 1, minWin=26, winSum=437
958 00:24:26.899980 TX Vref=24, minBit 5, minWin=26, winSum=441
959 00:24:26.900220 TX Vref=26, minBit 1, minWin=27, winSum=447
960 00:24:26.900279 TX Vref=28, minBit 2, minWin=27, winSum=451
961 00:24:26.900332 TX Vref=30, minBit 2, minWin=27, winSum=454
962 00:24:26.900384 TX Vref=32, minBit 1, minWin=27, winSum=450
963 00:24:26.900437 [TxChooseVref] Worse bit 2, Min win 27, Win sum 454, Final Vref 30
964 00:24:26.900489
965 00:24:26.900541 Final TX Range 1 Vref 30
966 00:24:26.900593
967 00:24:26.900648 ==
968 00:24:26.900739 Dram Type= 6, Freq= 0, CH_0, rank 0
969 00:24:26.900790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
970 00:24:26.900842 ==
971 00:24:26.900893
972 00:24:26.900944
973 00:24:26.900995 TX Vref Scan disable
974 00:24:26.901046 == TX Byte 0 ==
975 00:24:26.901098 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
976 00:24:26.901150 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
977 00:24:26.901202 == TX Byte 1 ==
978 00:24:26.901253 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
979 00:24:26.901348 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
980 00:24:26.901401
981 00:24:26.901452 [DATLAT]
982 00:24:26.901504 Freq=800, CH0 RK0
983 00:24:26.901555
984 00:24:26.901607 DATLAT Default: 0xa
985 00:24:26.901658 0, 0xFFFF, sum = 0
986 00:24:26.901712 1, 0xFFFF, sum = 0
987 00:24:26.901765 2, 0xFFFF, sum = 0
988 00:24:26.901818 3, 0xFFFF, sum = 0
989 00:24:26.901870 4, 0xFFFF, sum = 0
990 00:24:26.901922 5, 0xFFFF, sum = 0
991 00:24:26.901974 6, 0xFFFF, sum = 0
992 00:24:26.902027 7, 0xFFFF, sum = 0
993 00:24:26.902080 8, 0xFFFF, sum = 0
994 00:24:26.902132 9, 0x0, sum = 1
995 00:24:26.902185 10, 0x0, sum = 2
996 00:24:26.902238 11, 0x0, sum = 3
997 00:24:26.902290 12, 0x0, sum = 4
998 00:24:26.902343 best_step = 10
999 00:24:26.902394
1000 00:24:26.902445 ==
1001 00:24:26.902497 Dram Type= 6, Freq= 0, CH_0, rank 0
1002 00:24:26.902549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1003 00:24:26.902602 ==
1004 00:24:26.902653 RX Vref Scan: 1
1005 00:24:26.902704
1006 00:24:26.902756 Set Vref Range= 32 -> 127
1007 00:24:26.902807
1008 00:24:26.902860 RX Vref 32 -> 127, step: 1
1009 00:24:26.902912
1010 00:24:26.902963 RX Delay -111 -> 252, step: 8
1011 00:24:26.903015
1012 00:24:26.903066 Set Vref, RX VrefLevel [Byte0]: 32
1013 00:24:26.903118 [Byte1]: 32
1014 00:24:26.903169
1015 00:24:26.903221 Set Vref, RX VrefLevel [Byte0]: 33
1016 00:24:26.903272 [Byte1]: 33
1017 00:24:26.903325
1018 00:24:26.903377 Set Vref, RX VrefLevel [Byte0]: 34
1019 00:24:26.903429 [Byte1]: 34
1020 00:24:26.903480
1021 00:24:26.903531 Set Vref, RX VrefLevel [Byte0]: 35
1022 00:24:26.903583 [Byte1]: 35
1023 00:24:26.903635
1024 00:24:26.903686 Set Vref, RX VrefLevel [Byte0]: 36
1025 00:24:26.903743 [Byte1]: 36
1026 00:24:26.903798
1027 00:24:26.903850 Set Vref, RX VrefLevel [Byte0]: 37
1028 00:24:26.903901 [Byte1]: 37
1029 00:24:26.903953
1030 00:24:26.904005 Set Vref, RX VrefLevel [Byte0]: 38
1031 00:24:26.904056 [Byte1]: 38
1032 00:24:26.904108
1033 00:24:26.904158 Set Vref, RX VrefLevel [Byte0]: 39
1034 00:24:26.904210 [Byte1]: 39
1035 00:24:26.904260
1036 00:24:26.904311 Set Vref, RX VrefLevel [Byte0]: 40
1037 00:24:26.904362 [Byte1]: 40
1038 00:24:26.904412
1039 00:24:26.904463 Set Vref, RX VrefLevel [Byte0]: 41
1040 00:24:26.904514 [Byte1]: 41
1041 00:24:26.904565
1042 00:24:26.904615 Set Vref, RX VrefLevel [Byte0]: 42
1043 00:24:26.904666 [Byte1]: 42
1044 00:24:26.904717
1045 00:24:26.904768 Set Vref, RX VrefLevel [Byte0]: 43
1046 00:24:26.904819 [Byte1]: 43
1047 00:24:26.904869
1048 00:24:26.904920 Set Vref, RX VrefLevel [Byte0]: 44
1049 00:24:26.904971 [Byte1]: 44
1050 00:24:26.905021
1051 00:24:26.905072 Set Vref, RX VrefLevel [Byte0]: 45
1052 00:24:26.905123 [Byte1]: 45
1053 00:24:26.905175
1054 00:24:26.905225 Set Vref, RX VrefLevel [Byte0]: 46
1055 00:24:26.905303 [Byte1]: 46
1056 00:24:26.905370
1057 00:24:26.905421 Set Vref, RX VrefLevel [Byte0]: 47
1058 00:24:26.905471 [Byte1]: 47
1059 00:24:26.905522
1060 00:24:26.905572 Set Vref, RX VrefLevel [Byte0]: 48
1061 00:24:26.905623 [Byte1]: 48
1062 00:24:26.905674
1063 00:24:26.905724 Set Vref, RX VrefLevel [Byte0]: 49
1064 00:24:26.905775 [Byte1]: 49
1065 00:24:26.905826
1066 00:24:26.905877 Set Vref, RX VrefLevel [Byte0]: 50
1067 00:24:26.905928 [Byte1]: 50
1068 00:24:26.905978
1069 00:24:26.906029 Set Vref, RX VrefLevel [Byte0]: 51
1070 00:24:26.906080 [Byte1]: 51
1071 00:24:26.906131
1072 00:24:26.906181 Set Vref, RX VrefLevel [Byte0]: 52
1073 00:24:26.906232 [Byte1]: 52
1074 00:24:26.906283
1075 00:24:26.906334 Set Vref, RX VrefLevel [Byte0]: 53
1076 00:24:26.906385 [Byte1]: 53
1077 00:24:26.906436
1078 00:24:26.906486 Set Vref, RX VrefLevel [Byte0]: 54
1079 00:24:26.906537 [Byte1]: 54
1080 00:24:26.906588
1081 00:24:26.906639 Set Vref, RX VrefLevel [Byte0]: 55
1082 00:24:26.906690 [Byte1]: 55
1083 00:24:26.906740
1084 00:24:26.906791 Set Vref, RX VrefLevel [Byte0]: 56
1085 00:24:26.906842 [Byte1]: 56
1086 00:24:26.906893
1087 00:24:26.906944 Set Vref, RX VrefLevel [Byte0]: 57
1088 00:24:26.906996 [Byte1]: 57
1089 00:24:26.907047
1090 00:24:26.907097 Set Vref, RX VrefLevel [Byte0]: 58
1091 00:24:26.907149 [Byte1]: 58
1092 00:24:26.907200
1093 00:24:26.907251 Set Vref, RX VrefLevel [Byte0]: 59
1094 00:24:26.907301 [Byte1]: 59
1095 00:24:26.907353
1096 00:24:26.907403 Set Vref, RX VrefLevel [Byte0]: 60
1097 00:24:26.907455 [Byte1]: 60
1098 00:24:26.907505
1099 00:24:26.907555 Set Vref, RX VrefLevel [Byte0]: 61
1100 00:24:26.907606 [Byte1]: 61
1101 00:24:26.907657
1102 00:24:26.907707 Set Vref, RX VrefLevel [Byte0]: 62
1103 00:24:26.907758 [Byte1]: 62
1104 00:24:26.907809
1105 00:24:26.907860 Set Vref, RX VrefLevel [Byte0]: 63
1106 00:24:26.907912 [Byte1]: 63
1107 00:24:26.907963
1108 00:24:26.908013 Set Vref, RX VrefLevel [Byte0]: 64
1109 00:24:26.908064 [Byte1]: 64
1110 00:24:26.908116
1111 00:24:26.908166 Set Vref, RX VrefLevel [Byte0]: 65
1112 00:24:26.908217 [Byte1]: 65
1113 00:24:26.908268
1114 00:24:26.908319 Set Vref, RX VrefLevel [Byte0]: 66
1115 00:24:26.908369 [Byte1]: 66
1116 00:24:26.908420
1117 00:24:26.908471 Set Vref, RX VrefLevel [Byte0]: 67
1118 00:24:26.908522 [Byte1]: 67
1119 00:24:26.908573
1120 00:24:26.908623 Set Vref, RX VrefLevel [Byte0]: 68
1121 00:24:26.908674 [Byte1]: 68
1122 00:24:26.908725
1123 00:24:26.908775 Set Vref, RX VrefLevel [Byte0]: 69
1124 00:24:26.908826 [Byte1]: 69
1125 00:24:26.908877
1126 00:24:26.908927 Set Vref, RX VrefLevel [Byte0]: 70
1127 00:24:26.909166 [Byte1]: 70
1128 00:24:26.909225
1129 00:24:26.909339 Set Vref, RX VrefLevel [Byte0]: 71
1130 00:24:26.909406 [Byte1]: 71
1131 00:24:26.909458
1132 00:24:26.909508 Set Vref, RX VrefLevel [Byte0]: 72
1133 00:24:26.909560 [Byte1]: 72
1134 00:24:26.909610
1135 00:24:26.909661 Set Vref, RX VrefLevel [Byte0]: 73
1136 00:24:26.909712 [Byte1]: 73
1137 00:24:26.909764
1138 00:24:26.909820 Final RX Vref Byte 0 = 54 to rank0
1139 00:24:26.909873 Final RX Vref Byte 1 = 62 to rank0
1140 00:24:26.909924 Final RX Vref Byte 0 = 54 to rank1
1141 00:24:26.909975 Final RX Vref Byte 1 = 62 to rank1==
1142 00:24:26.910027 Dram Type= 6, Freq= 0, CH_0, rank 0
1143 00:24:26.910078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1144 00:24:26.910130 ==
1145 00:24:26.910181 DQS Delay:
1146 00:24:26.910232 DQS0 = 0, DQS1 = 0
1147 00:24:26.910283 DQM Delay:
1148 00:24:26.910334 DQM0 = 88, DQM1 = 76
1149 00:24:26.910385 DQ Delay:
1150 00:24:26.910436 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =88
1151 00:24:26.910488 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1152 00:24:26.910539 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =72
1153 00:24:26.910590 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1154 00:24:26.910642
1155 00:24:26.910692
1156 00:24:26.910743 [DQSOSCAuto] RK0, (LSB)MR18= 0x3730, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 395 ps
1157 00:24:26.910795 CH0 RK0: MR19=606, MR18=3730
1158 00:24:26.910847 CH0_RK0: MR19=0x606, MR18=0x3730, DQSOSC=395, MR23=63, INC=94, DEC=63
1159 00:24:26.910899
1160 00:24:26.910950 ----->DramcWriteLeveling(PI) begin...
1161 00:24:26.911002 ==
1162 00:24:26.911053 Dram Type= 6, Freq= 0, CH_0, rank 1
1163 00:24:26.911104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1164 00:24:26.911155 ==
1165 00:24:26.911206 Write leveling (Byte 0): 34 => 34
1166 00:24:26.911257 Write leveling (Byte 1): 28 => 28
1167 00:24:26.911307 DramcWriteLeveling(PI) end<-----
1168 00:24:26.911359
1169 00:24:26.911409 ==
1170 00:24:26.911460 Dram Type= 6, Freq= 0, CH_0, rank 1
1171 00:24:26.911511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1172 00:24:26.911563 ==
1173 00:24:26.911614 [Gating] SW mode calibration
1174 00:24:26.911665 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1175 00:24:26.911717 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1176 00:24:26.911768 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1177 00:24:26.911828 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1178 00:24:26.911882 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1179 00:24:26.911933 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 00:24:26.911985 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 00:24:26.912036 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 00:24:26.912087 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 00:24:26.912138 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 00:24:26.912189 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 00:24:26.912240 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 00:24:26.912291 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 00:24:26.912342 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 00:24:26.912394 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 00:24:26.912445 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 00:24:26.912496 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 00:24:26.912556 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 00:24:26.912610 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 00:24:26.912661 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1194 00:24:26.912713 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1195 00:24:26.912764 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 00:24:26.912816 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 00:24:26.912867 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 00:24:26.912918 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 00:24:26.912970 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 00:24:26.913021 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 00:24:26.913072 0 9 4 | B1->B0 | 2323 2525 | 0 1 | (0 0) (1 1)
1202 00:24:26.913123 0 9 8 | B1->B0 | 2323 3434 | 1 1 | (1 1) (1 1)
1203 00:24:26.913174 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1204 00:24:26.913225 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1205 00:24:26.913304 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1206 00:24:26.913370 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1207 00:24:26.913421 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1208 00:24:26.913473 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1209 00:24:26.913525 0 10 4 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
1210 00:24:26.913576 0 10 8 | B1->B0 | 3030 2323 | 0 0 | (1 0) (1 0)
1211 00:24:26.913628 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 00:24:26.913679 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 00:24:26.913731 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 00:24:26.913782 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 00:24:26.913833 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 00:24:26.913883 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 00:24:26.913934 0 11 4 | B1->B0 | 2323 3030 | 0 0 | (0 0) (1 1)
1218 00:24:26.913986 0 11 8 | B1->B0 | 3131 4545 | 0 0 | (1 1) (0 0)
1219 00:24:26.914037 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1220 00:24:26.914088 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1221 00:24:26.914140 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1222 00:24:26.914190 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1223 00:24:26.914241 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1224 00:24:26.914292 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1225 00:24:26.914344 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1226 00:24:26.914395 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1227 00:24:26.914447 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1228 00:24:26.914687 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1229 00:24:26.914751 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1230 00:24:26.914803 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1231 00:24:26.914855 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1232 00:24:26.914907 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1233 00:24:26.914958 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1234 00:24:26.915010 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1235 00:24:26.915060 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1236 00:24:26.915111 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1237 00:24:26.915163 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1238 00:24:26.915214 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1239 00:24:26.915266 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1240 00:24:26.915318 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1241 00:24:26.915370 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
1242 00:24:26.915421 Total UI for P1: 0, mck2ui 16
1243 00:24:26.915472 best dqsien dly found for B0: ( 0, 14, 2)
1244 00:24:26.915523 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1245 00:24:26.915575 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1246 00:24:26.915626 Total UI for P1: 0, mck2ui 16
1247 00:24:26.915677 best dqsien dly found for B1: ( 0, 14, 8)
1248 00:24:26.915728 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1249 00:24:26.915779 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1250 00:24:26.915830
1251 00:24:26.915881 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1252 00:24:26.915931 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1253 00:24:26.915983 [Gating] SW calibration Done
1254 00:24:26.916035 ==
1255 00:24:26.916086 Dram Type= 6, Freq= 0, CH_0, rank 1
1256 00:24:26.916137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1257 00:24:26.916188 ==
1258 00:24:26.916240 RX Vref Scan: 0
1259 00:24:26.916291
1260 00:24:26.916342 RX Vref 0 -> 0, step: 1
1261 00:24:26.916393
1262 00:24:26.916444 RX Delay -130 -> 252, step: 16
1263 00:24:26.916495 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1264 00:24:26.916547 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1265 00:24:26.916597 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1266 00:24:26.916648 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1267 00:24:26.916699 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1268 00:24:26.916750 iDelay=206, Bit 5, Center 69 (-50 ~ 189) 240
1269 00:24:26.916801 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1270 00:24:26.916852 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1271 00:24:26.916903 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1272 00:24:26.916954 iDelay=206, Bit 9, Center 53 (-66 ~ 173) 240
1273 00:24:26.917004 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1274 00:24:26.917055 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1275 00:24:26.917107 iDelay=206, Bit 12, Center 77 (-34 ~ 189) 224
1276 00:24:26.917158 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1277 00:24:26.917209 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1278 00:24:26.917267 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1279 00:24:26.917354 ==
1280 00:24:26.917406 Dram Type= 6, Freq= 0, CH_0, rank 1
1281 00:24:26.917457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1282 00:24:26.917508 ==
1283 00:24:26.917558 DQS Delay:
1284 00:24:26.917609 DQS0 = 0, DQS1 = 0
1285 00:24:26.917660 DQM Delay:
1286 00:24:26.917711 DQM0 = 84, DQM1 = 76
1287 00:24:26.917762 DQ Delay:
1288 00:24:26.917812 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1289 00:24:26.917863 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1290 00:24:26.917914 DQ8 =69, DQ9 =53, DQ10 =85, DQ11 =69
1291 00:24:26.917965 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1292 00:24:26.918016
1293 00:24:26.918066
1294 00:24:26.918117 ==
1295 00:24:26.918167 Dram Type= 6, Freq= 0, CH_0, rank 1
1296 00:24:26.918219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1297 00:24:26.918270 ==
1298 00:24:26.918321
1299 00:24:26.918371
1300 00:24:26.918422 TX Vref Scan disable
1301 00:24:26.918473 == TX Byte 0 ==
1302 00:24:26.918526 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1303 00:24:26.918578 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1304 00:24:26.918630 == TX Byte 1 ==
1305 00:24:26.918681 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1306 00:24:26.918733 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1307 00:24:26.918784 ==
1308 00:24:26.918835 Dram Type= 6, Freq= 0, CH_0, rank 1
1309 00:24:26.918887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1310 00:24:26.918938 ==
1311 00:24:26.918989 TX Vref=22, minBit 1, minWin=27, winSum=444
1312 00:24:26.919040 TX Vref=24, minBit 2, minWin=27, winSum=445
1313 00:24:26.919091 TX Vref=26, minBit 1, minWin=27, winSum=450
1314 00:24:26.919143 TX Vref=28, minBit 5, minWin=27, winSum=452
1315 00:24:26.919194 TX Vref=30, minBit 5, minWin=27, winSum=449
1316 00:24:26.919245 TX Vref=32, minBit 4, minWin=27, winSum=447
1317 00:24:26.919296 [TxChooseVref] Worse bit 5, Min win 27, Win sum 452, Final Vref 28
1318 00:24:26.919348
1319 00:24:26.919398 Final TX Range 1 Vref 28
1320 00:24:26.919450
1321 00:24:26.919500 ==
1322 00:24:26.919551 Dram Type= 6, Freq= 0, CH_0, rank 1
1323 00:24:26.919602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1324 00:24:26.919654 ==
1325 00:24:26.919705
1326 00:24:26.919756
1327 00:24:26.919807 TX Vref Scan disable
1328 00:24:26.919857 == TX Byte 0 ==
1329 00:24:26.919908 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1330 00:24:26.919959 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1331 00:24:26.920010 == TX Byte 1 ==
1332 00:24:26.920060 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1333 00:24:26.920111 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1334 00:24:26.920161
1335 00:24:26.920211 [DATLAT]
1336 00:24:26.920261 Freq=800, CH0 RK1
1337 00:24:26.920312
1338 00:24:26.920362 DATLAT Default: 0xa
1339 00:24:26.920412 0, 0xFFFF, sum = 0
1340 00:24:26.920464 1, 0xFFFF, sum = 0
1341 00:24:26.920515 2, 0xFFFF, sum = 0
1342 00:24:26.920567 3, 0xFFFF, sum = 0
1343 00:24:26.920618 4, 0xFFFF, sum = 0
1344 00:24:26.920670 5, 0xFFFF, sum = 0
1345 00:24:26.920721 6, 0xFFFF, sum = 0
1346 00:24:26.920772 7, 0xFFFF, sum = 0
1347 00:24:26.920823 8, 0xFFFF, sum = 0
1348 00:24:26.920875 9, 0x0, sum = 1
1349 00:24:26.920926 10, 0x0, sum = 2
1350 00:24:26.920977 11, 0x0, sum = 3
1351 00:24:26.921029 12, 0x0, sum = 4
1352 00:24:26.921080 best_step = 10
1353 00:24:26.921130
1354 00:24:26.921180 ==
1355 00:24:26.921231 Dram Type= 6, Freq= 0, CH_0, rank 1
1356 00:24:26.921304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1357 00:24:26.921369 ==
1358 00:24:26.921419 RX Vref Scan: 0
1359 00:24:26.921469
1360 00:24:26.921520 RX Vref 0 -> 0, step: 1
1361 00:24:26.921570
1362 00:24:26.921620 RX Delay -111 -> 252, step: 8
1363 00:24:26.921671 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1364 00:24:26.921925 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1365 00:24:26.922001 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1366 00:24:26.922055 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1367 00:24:26.922107 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1368 00:24:26.922159 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1369 00:24:26.922211 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1370 00:24:26.922262 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1371 00:24:26.922314 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1372 00:24:26.922366 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1373 00:24:26.922433 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1374 00:24:26.922485 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
1375 00:24:26.922536 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1376 00:24:26.922587 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1377 00:24:26.922637 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1378 00:24:26.922688 iDelay=209, Bit 15, Center 84 (-23 ~ 192) 216
1379 00:24:26.922738 ==
1380 00:24:26.922788 Dram Type= 6, Freq= 0, CH_0, rank 1
1381 00:24:26.922839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1382 00:24:26.922890 ==
1383 00:24:26.922940 DQS Delay:
1384 00:24:26.922990 DQS0 = 0, DQS1 = 0
1385 00:24:26.923040 DQM Delay:
1386 00:24:26.923091 DQM0 = 86, DQM1 = 77
1387 00:24:26.923141 DQ Delay:
1388 00:24:26.923192 DQ0 =84, DQ1 =88, DQ2 =80, DQ3 =80
1389 00:24:26.923274 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1390 00:24:26.923325 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =72
1391 00:24:26.923375 DQ12 =84, DQ13 =80, DQ14 =88, DQ15 =84
1392 00:24:26.923426
1393 00:24:26.923476
1394 00:24:26.923526 [DQSOSCAuto] RK1, (LSB)MR18= 0x312d, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
1395 00:24:26.923578 CH0 RK1: MR19=606, MR18=312D
1396 00:24:26.923629 CH0_RK1: MR19=0x606, MR18=0x312D, DQSOSC=397, MR23=63, INC=93, DEC=62
1397 00:24:26.923679 [RxdqsGatingPostProcess] freq 800
1398 00:24:26.923730 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1399 00:24:26.923798 Pre-setting of DQS Precalculation
1400 00:24:26.923864 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1401 00:24:26.923915 ==
1402 00:24:26.923965 Dram Type= 6, Freq= 0, CH_1, rank 0
1403 00:24:26.924016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1404 00:24:26.924066 ==
1405 00:24:26.924116 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1406 00:24:26.924167 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1407 00:24:26.924219 [CA 0] Center 36 (6~67) winsize 62
1408 00:24:26.924269 [CA 1] Center 36 (6~67) winsize 62
1409 00:24:26.924319 [CA 2] Center 35 (5~65) winsize 61
1410 00:24:26.924370 [CA 3] Center 34 (4~65) winsize 62
1411 00:24:26.924421 [CA 4] Center 34 (4~65) winsize 62
1412 00:24:26.924471 [CA 5] Center 34 (3~65) winsize 63
1413 00:24:26.924521
1414 00:24:26.924571 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1415 00:24:26.924622
1416 00:24:26.924672 [CATrainingPosCal] consider 1 rank data
1417 00:24:26.924722 u2DelayCellTimex100 = 270/100 ps
1418 00:24:26.924773 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1419 00:24:26.924824 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1420 00:24:26.924874 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1421 00:24:26.924924 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1422 00:24:26.924975 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1423 00:24:26.925025 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1424 00:24:26.925076
1425 00:24:26.925126 CA PerBit enable=1, Macro0, CA PI delay=34
1426 00:24:26.925176
1427 00:24:26.925226 [CBTSetCACLKResult] CA Dly = 34
1428 00:24:26.925316 CS Dly: 4 (0~35)
1429 00:24:26.925367 ==
1430 00:24:26.925417 Dram Type= 6, Freq= 0, CH_1, rank 1
1431 00:24:26.925467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1432 00:24:26.925518 ==
1433 00:24:26.925569 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1434 00:24:26.925619 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1435 00:24:26.925670 [CA 0] Center 36 (6~67) winsize 62
1436 00:24:26.925721 [CA 1] Center 37 (6~68) winsize 63
1437 00:24:26.925771 [CA 2] Center 34 (4~65) winsize 62
1438 00:24:26.925822 [CA 3] Center 34 (3~65) winsize 63
1439 00:24:26.925872 [CA 4] Center 34 (3~65) winsize 63
1440 00:24:26.925922 [CA 5] Center 33 (3~64) winsize 62
1441 00:24:26.925972
1442 00:24:26.926025 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1443 00:24:26.926075
1444 00:24:26.926125 [CATrainingPosCal] consider 2 rank data
1445 00:24:26.926176 u2DelayCellTimex100 = 270/100 ps
1446 00:24:26.926227 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1447 00:24:26.926296 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1448 00:24:26.926351 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1449 00:24:26.926402 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1450 00:24:26.926454 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1451 00:24:26.926505 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1452 00:24:26.926556
1453 00:24:26.926607 CA PerBit enable=1, Macro0, CA PI delay=33
1454 00:24:26.926658
1455 00:24:26.926708 [CBTSetCACLKResult] CA Dly = 33
1456 00:24:26.926758 CS Dly: 5 (0~37)
1457 00:24:26.926808
1458 00:24:26.926859 ----->DramcWriteLeveling(PI) begin...
1459 00:24:26.926911 ==
1460 00:24:26.926961 Dram Type= 6, Freq= 0, CH_1, rank 0
1461 00:24:26.927012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1462 00:24:26.927063 ==
1463 00:24:26.927113 Write leveling (Byte 0): 26 => 26
1464 00:24:26.927163 Write leveling (Byte 1): 27 => 27
1465 00:24:26.927214 DramcWriteLeveling(PI) end<-----
1466 00:24:26.927264
1467 00:24:26.927314 ==
1468 00:24:26.927364 Dram Type= 6, Freq= 0, CH_1, rank 0
1469 00:24:26.927414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1470 00:24:26.927465 ==
1471 00:24:26.927515 [Gating] SW mode calibration
1472 00:24:26.927565 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1473 00:24:26.927616 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1474 00:24:26.927668 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1475 00:24:26.927718 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1476 00:24:26.927769 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 00:24:26.927819 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 00:24:26.927870 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 00:24:26.927921 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 00:24:26.927971 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 00:24:26.928211 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 00:24:26.928269 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 00:24:26.928321 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 00:24:26.928371 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 00:24:26.928422 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 00:24:26.928473 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 00:24:26.928523 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 00:24:26.928575 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 00:24:26.928626 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 00:24:26.928677 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1491 00:24:26.928728 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1492 00:24:26.928779 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 00:24:26.928829 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 00:24:26.928880 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 00:24:26.928931 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 00:24:26.928981 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 00:24:26.929032 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 00:24:26.929082 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 00:24:26.929133 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 00:24:26.929184 0 9 8 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
1501 00:24:26.929234 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1502 00:24:26.929323 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1503 00:24:26.929374 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1504 00:24:26.929424 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1505 00:24:26.929474 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1506 00:24:26.929525 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1507 00:24:26.929575 0 10 4 | B1->B0 | 3434 3030 | 0 0 | (0 0) (0 1)
1508 00:24:26.929625 0 10 8 | B1->B0 | 2a2a 2323 | 0 0 | (1 1) (0 0)
1509 00:24:26.929675 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 00:24:26.929725 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 00:24:26.929776 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 00:24:26.929827 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 00:24:26.929877 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 00:24:26.929927 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 00:24:26.929977 0 11 4 | B1->B0 | 2525 2c2c | 0 0 | (0 0) (0 0)
1516 00:24:26.930028 0 11 8 | B1->B0 | 3f3f 4343 | 0 0 | (0 0) (0 0)
1517 00:24:26.930078 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1518 00:24:26.930129 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1519 00:24:26.930179 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1520 00:24:26.930230 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1521 00:24:26.930281 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1522 00:24:26.930331 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1523 00:24:26.930382 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1524 00:24:26.930433 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1525 00:24:26.930483 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1526 00:24:26.930533 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1527 00:24:26.930584 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1528 00:24:26.930634 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1529 00:24:26.930685 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1530 00:24:26.930735 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1531 00:24:26.930785 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1532 00:24:26.930835 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1533 00:24:26.930885 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1534 00:24:26.930935 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1535 00:24:26.930986 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1536 00:24:26.931037 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1537 00:24:26.931087 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1538 00:24:26.931137 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1539 00:24:26.931188 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1540 00:24:26.931239 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1541 00:24:26.931290 Total UI for P1: 0, mck2ui 16
1542 00:24:26.931341 best dqsien dly found for B0: ( 0, 14, 4)
1543 00:24:26.931392 Total UI for P1: 0, mck2ui 16
1544 00:24:26.931443 best dqsien dly found for B1: ( 0, 14, 4)
1545 00:24:26.931493 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1546 00:24:26.931544 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1547 00:24:26.931594
1548 00:24:26.931645 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1549 00:24:26.931695 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1550 00:24:26.931746 [Gating] SW calibration Done
1551 00:24:26.931796 ==
1552 00:24:26.931847 Dram Type= 6, Freq= 0, CH_1, rank 0
1553 00:24:26.931897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1554 00:24:26.931949 ==
1555 00:24:26.931999 RX Vref Scan: 0
1556 00:24:26.932049
1557 00:24:26.932099 RX Vref 0 -> 0, step: 1
1558 00:24:26.932149
1559 00:24:26.932200 RX Delay -130 -> 252, step: 16
1560 00:24:26.932250 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1561 00:24:26.932301 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1562 00:24:26.932351 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1563 00:24:26.932402 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1564 00:24:26.932453 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1565 00:24:26.932503 iDelay=222, Bit 5, Center 93 (-18 ~ 205) 224
1566 00:24:26.932554 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1567 00:24:26.932607 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1568 00:24:26.932657 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1569 00:24:26.932707 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1570 00:24:26.932758 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1571 00:24:26.932999 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1572 00:24:26.933059 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1573 00:24:26.933112 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1574 00:24:26.933163 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1575 00:24:26.933214 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1576 00:24:26.933273 ==
1577 00:24:26.933361 Dram Type= 6, Freq= 0, CH_1, rank 0
1578 00:24:26.933412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1579 00:24:26.933464 ==
1580 00:24:26.933514 DQS Delay:
1581 00:24:26.933565 DQS0 = 0, DQS1 = 0
1582 00:24:26.933615 DQM Delay:
1583 00:24:26.933666 DQM0 = 87, DQM1 = 86
1584 00:24:26.933716 DQ Delay:
1585 00:24:26.933766 DQ0 =93, DQ1 =85, DQ2 =69, DQ3 =85
1586 00:24:26.933817 DQ4 =85, DQ5 =93, DQ6 =101, DQ7 =85
1587 00:24:26.933868 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
1588 00:24:26.933919 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1589 00:24:26.933969
1590 00:24:26.934019
1591 00:24:26.934069 ==
1592 00:24:26.934120 Dram Type= 6, Freq= 0, CH_1, rank 0
1593 00:24:26.934170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1594 00:24:26.934221 ==
1595 00:24:26.934271
1596 00:24:26.934321
1597 00:24:26.934371 TX Vref Scan disable
1598 00:24:26.934422 == TX Byte 0 ==
1599 00:24:26.934474 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1600 00:24:26.934525 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1601 00:24:26.934575 == TX Byte 1 ==
1602 00:24:26.934626 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1603 00:24:26.934676 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1604 00:24:26.934727 ==
1605 00:24:26.934778 Dram Type= 6, Freq= 0, CH_1, rank 0
1606 00:24:26.934829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1607 00:24:26.934880 ==
1608 00:24:26.934930 TX Vref=22, minBit 3, minWin=27, winSum=444
1609 00:24:26.934982 TX Vref=24, minBit 2, minWin=27, winSum=447
1610 00:24:26.935032 TX Vref=26, minBit 5, minWin=27, winSum=453
1611 00:24:26.935084 TX Vref=28, minBit 0, minWin=28, winSum=457
1612 00:24:26.935135 TX Vref=30, minBit 5, minWin=27, winSum=455
1613 00:24:26.935185 TX Vref=32, minBit 5, minWin=27, winSum=456
1614 00:24:26.935237 [TxChooseVref] Worse bit 0, Min win 28, Win sum 457, Final Vref 28
1615 00:24:26.935288
1616 00:24:26.935338 Final TX Range 1 Vref 28
1617 00:24:26.935389
1618 00:24:26.935439 ==
1619 00:24:26.935490 Dram Type= 6, Freq= 0, CH_1, rank 0
1620 00:24:26.935540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1621 00:24:26.935591 ==
1622 00:24:26.935641
1623 00:24:26.935691
1624 00:24:26.935740 TX Vref Scan disable
1625 00:24:26.935791 == TX Byte 0 ==
1626 00:24:26.935842 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1627 00:24:26.935893 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1628 00:24:26.935943 == TX Byte 1 ==
1629 00:24:26.935994 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1630 00:24:26.936044 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1631 00:24:26.936095
1632 00:24:26.936145 [DATLAT]
1633 00:24:26.936195 Freq=800, CH1 RK0
1634 00:24:26.936245
1635 00:24:26.936295 DATLAT Default: 0xa
1636 00:24:26.936346 0, 0xFFFF, sum = 0
1637 00:24:26.936398 1, 0xFFFF, sum = 0
1638 00:24:26.936450 2, 0xFFFF, sum = 0
1639 00:24:26.936501 3, 0xFFFF, sum = 0
1640 00:24:26.936552 4, 0xFFFF, sum = 0
1641 00:24:26.936603 5, 0xFFFF, sum = 0
1642 00:24:26.936654 6, 0xFFFF, sum = 0
1643 00:24:26.936705 7, 0xFFFF, sum = 0
1644 00:24:26.936756 8, 0xFFFF, sum = 0
1645 00:24:26.936807 9, 0x0, sum = 1
1646 00:24:26.936859 10, 0x0, sum = 2
1647 00:24:26.936910 11, 0x0, sum = 3
1648 00:24:26.936961 12, 0x0, sum = 4
1649 00:24:26.937012 best_step = 10
1650 00:24:26.937063
1651 00:24:26.937113 ==
1652 00:24:26.937163 Dram Type= 6, Freq= 0, CH_1, rank 0
1653 00:24:26.937214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1654 00:24:26.937268 ==
1655 00:24:26.937353 RX Vref Scan: 1
1656 00:24:26.937403
1657 00:24:26.937453 Set Vref Range= 32 -> 127
1658 00:24:26.937503
1659 00:24:26.937553 RX Vref 32 -> 127, step: 1
1660 00:24:26.937603
1661 00:24:26.937653 RX Delay -95 -> 252, step: 8
1662 00:24:26.937703
1663 00:24:26.937754 Set Vref, RX VrefLevel [Byte0]: 32
1664 00:24:26.937812 [Byte1]: 32
1665 00:24:26.937868
1666 00:24:26.937918 Set Vref, RX VrefLevel [Byte0]: 33
1667 00:24:26.937969 [Byte1]: 33
1668 00:24:26.938020
1669 00:24:26.938069 Set Vref, RX VrefLevel [Byte0]: 34
1670 00:24:26.938120 [Byte1]: 34
1671 00:24:26.938171
1672 00:24:26.938221 Set Vref, RX VrefLevel [Byte0]: 35
1673 00:24:26.938271 [Byte1]: 35
1674 00:24:26.938321
1675 00:24:26.938371 Set Vref, RX VrefLevel [Byte0]: 36
1676 00:24:26.938421 [Byte1]: 36
1677 00:24:26.938471
1678 00:24:26.938521 Set Vref, RX VrefLevel [Byte0]: 37
1679 00:24:26.938571 [Byte1]: 37
1680 00:24:26.938621
1681 00:24:26.938670 Set Vref, RX VrefLevel [Byte0]: 38
1682 00:24:26.938720 [Byte1]: 38
1683 00:24:26.938771
1684 00:24:26.938821 Set Vref, RX VrefLevel [Byte0]: 39
1685 00:24:26.938872 [Byte1]: 39
1686 00:24:26.938922
1687 00:24:26.938972 Set Vref, RX VrefLevel [Byte0]: 40
1688 00:24:26.939023 [Byte1]: 40
1689 00:24:26.939073
1690 00:24:26.939124 Set Vref, RX VrefLevel [Byte0]: 41
1691 00:24:26.939173 [Byte1]: 41
1692 00:24:26.939224
1693 00:24:26.939273 Set Vref, RX VrefLevel [Byte0]: 42
1694 00:24:26.939323 [Byte1]: 42
1695 00:24:26.939375
1696 00:24:26.939426 Set Vref, RX VrefLevel [Byte0]: 43
1697 00:24:26.939476 [Byte1]: 43
1698 00:24:26.939526
1699 00:24:26.939577 Set Vref, RX VrefLevel [Byte0]: 44
1700 00:24:26.939627 [Byte1]: 44
1701 00:24:26.939677
1702 00:24:26.939727 Set Vref, RX VrefLevel [Byte0]: 45
1703 00:24:26.939777 [Byte1]: 45
1704 00:24:26.939827
1705 00:24:26.939877 Set Vref, RX VrefLevel [Byte0]: 46
1706 00:24:26.939927 [Byte1]: 46
1707 00:24:26.939977
1708 00:24:26.940027 Set Vref, RX VrefLevel [Byte0]: 47
1709 00:24:26.940077 [Byte1]: 47
1710 00:24:26.940127
1711 00:24:26.940177 Set Vref, RX VrefLevel [Byte0]: 48
1712 00:24:26.940227 [Byte1]: 48
1713 00:24:26.940277
1714 00:24:26.940327 Set Vref, RX VrefLevel [Byte0]: 49
1715 00:24:26.940377 [Byte1]: 49
1716 00:24:26.940428
1717 00:24:26.940477 Set Vref, RX VrefLevel [Byte0]: 50
1718 00:24:26.940527 [Byte1]: 50
1719 00:24:26.940576
1720 00:24:26.940626 Set Vref, RX VrefLevel [Byte0]: 51
1721 00:24:26.940676 [Byte1]: 51
1722 00:24:26.940726
1723 00:24:26.940776 Set Vref, RX VrefLevel [Byte0]: 52
1724 00:24:26.940826 [Byte1]: 52
1725 00:24:26.940877
1726 00:24:26.940927 Set Vref, RX VrefLevel [Byte0]: 53
1727 00:24:26.940977 [Byte1]: 53
1728 00:24:26.941027
1729 00:24:26.941077 Set Vref, RX VrefLevel [Byte0]: 54
1730 00:24:26.941128 [Byte1]: 54
1731 00:24:26.941178
1732 00:24:26.941228 Set Vref, RX VrefLevel [Byte0]: 55
1733 00:24:26.941313 [Byte1]: 55
1734 00:24:26.941379
1735 00:24:26.941617 Set Vref, RX VrefLevel [Byte0]: 56
1736 00:24:26.941675 [Byte1]: 56
1737 00:24:26.941727
1738 00:24:26.941795 Set Vref, RX VrefLevel [Byte0]: 57
1739 00:24:26.941865 [Byte1]: 57
1740 00:24:26.941931
1741 00:24:26.941981 Set Vref, RX VrefLevel [Byte0]: 58
1742 00:24:26.942032 [Byte1]: 58
1743 00:24:26.942083
1744 00:24:26.942134 Set Vref, RX VrefLevel [Byte0]: 59
1745 00:24:26.942184 [Byte1]: 59
1746 00:24:26.942235
1747 00:24:26.942285 Set Vref, RX VrefLevel [Byte0]: 60
1748 00:24:26.942336 [Byte1]: 60
1749 00:24:26.942387
1750 00:24:26.942437 Set Vref, RX VrefLevel [Byte0]: 61
1751 00:24:26.942488 [Byte1]: 61
1752 00:24:26.942538
1753 00:24:26.942588 Set Vref, RX VrefLevel [Byte0]: 62
1754 00:24:26.942638 [Byte1]: 62
1755 00:24:26.942688
1756 00:24:26.942737 Set Vref, RX VrefLevel [Byte0]: 63
1757 00:24:26.942788 [Byte1]: 63
1758 00:24:26.942838
1759 00:24:26.942889 Set Vref, RX VrefLevel [Byte0]: 64
1760 00:24:26.942939 [Byte1]: 64
1761 00:24:26.942990
1762 00:24:26.943040 Set Vref, RX VrefLevel [Byte0]: 65
1763 00:24:26.943090 [Byte1]: 65
1764 00:24:26.943140
1765 00:24:26.943190 Set Vref, RX VrefLevel [Byte0]: 66
1766 00:24:26.943241 [Byte1]: 66
1767 00:24:26.943297
1768 00:24:26.943349 Set Vref, RX VrefLevel [Byte0]: 67
1769 00:24:26.943399 [Byte1]: 67
1770 00:24:26.943449
1771 00:24:26.943499 Set Vref, RX VrefLevel [Byte0]: 68
1772 00:24:26.943549 [Byte1]: 68
1773 00:24:26.943599
1774 00:24:26.943650 Set Vref, RX VrefLevel [Byte0]: 69
1775 00:24:26.943700 [Byte1]: 69
1776 00:24:26.943751
1777 00:24:26.943811 Set Vref, RX VrefLevel [Byte0]: 70
1778 00:24:26.943879 [Byte1]: 70
1779 00:24:26.943965
1780 00:24:26.944020 Set Vref, RX VrefLevel [Byte0]: 71
1781 00:24:26.944071 [Byte1]: 71
1782 00:24:26.944123
1783 00:24:26.944173 Set Vref, RX VrefLevel [Byte0]: 72
1784 00:24:26.944224 [Byte1]: 72
1785 00:24:26.944274
1786 00:24:26.944325 Final RX Vref Byte 0 = 56 to rank0
1787 00:24:26.944376 Final RX Vref Byte 1 = 54 to rank0
1788 00:24:26.944427 Final RX Vref Byte 0 = 56 to rank1
1789 00:24:26.944477 Final RX Vref Byte 1 = 54 to rank1==
1790 00:24:26.944528 Dram Type= 6, Freq= 0, CH_1, rank 0
1791 00:24:26.944578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1792 00:24:26.944629 ==
1793 00:24:26.944680 DQS Delay:
1794 00:24:26.944730 DQS0 = 0, DQS1 = 0
1795 00:24:26.944780 DQM Delay:
1796 00:24:26.944830 DQM0 = 85, DQM1 = 79
1797 00:24:26.944880 DQ Delay:
1798 00:24:26.944930 DQ0 =92, DQ1 =80, DQ2 =72, DQ3 =84
1799 00:24:26.944981 DQ4 =80, DQ5 =96, DQ6 =96, DQ7 =80
1800 00:24:26.945032 DQ8 =64, DQ9 =72, DQ10 =76, DQ11 =76
1801 00:24:26.945082 DQ12 =88, DQ13 =88, DQ14 =84, DQ15 =88
1802 00:24:26.945133
1803 00:24:26.945182
1804 00:24:26.945232 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a2e, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 403 ps
1805 00:24:26.945317 CH1 RK0: MR19=606, MR18=1A2E
1806 00:24:26.945383 CH1_RK0: MR19=0x606, MR18=0x1A2E, DQSOSC=398, MR23=63, INC=93, DEC=62
1807 00:24:26.945434
1808 00:24:26.945485 ----->DramcWriteLeveling(PI) begin...
1809 00:24:26.945537 ==
1810 00:24:26.945588 Dram Type= 6, Freq= 0, CH_1, rank 1
1811 00:24:26.945638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1812 00:24:26.945689 ==
1813 00:24:26.945739 Write leveling (Byte 0): 26 => 26
1814 00:24:26.945793 Write leveling (Byte 1): 28 => 28
1815 00:24:26.945883 DramcWriteLeveling(PI) end<-----
1816 00:24:26.945942
1817 00:24:26.945993 ==
1818 00:24:26.946045 Dram Type= 6, Freq= 0, CH_1, rank 1
1819 00:24:26.946096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1820 00:24:26.946147 ==
1821 00:24:26.946198 [Gating] SW mode calibration
1822 00:24:26.946249 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1823 00:24:26.946300 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1824 00:24:26.946351 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1825 00:24:26.946402 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1826 00:24:26.946453 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 00:24:26.946504 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 00:24:26.946555 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 00:24:26.946606 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 00:24:26.946656 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 00:24:26.946707 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 00:24:26.946757 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 00:24:26.946808 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 00:24:26.946858 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 00:24:26.946908 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 00:24:26.946958 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 00:24:26.947009 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 00:24:26.947059 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 00:24:26.947109 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 00:24:26.947159 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1841 00:24:26.947210 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1842 00:24:26.947260 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1843 00:24:26.947310 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 00:24:26.947361 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 00:24:26.947412 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 00:24:26.947463 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 00:24:26.947513 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 00:24:26.947564 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 00:24:26.947614 0 9 4 | B1->B0 | 2323 2626 | 1 0 | (1 1) (0 0)
1850 00:24:26.947664 0 9 8 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
1851 00:24:26.947714 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1852 00:24:26.947765 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1853 00:24:26.947816 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1854 00:24:26.947866 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1855 00:24:26.947916 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1856 00:24:26.948157 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1857 00:24:26.948214 0 10 4 | B1->B0 | 3434 2c2c | 1 1 | (1 0) (1 0)
1858 00:24:26.948266 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1859 00:24:26.948317 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 00:24:26.948369 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 00:24:26.948419 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 00:24:26.948470 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 00:24:26.948520 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 00:24:26.948571 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 00:24:26.948622 0 11 4 | B1->B0 | 2929 3e3e | 0 0 | (0 0) (1 1)
1866 00:24:26.948673 0 11 8 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
1867 00:24:26.948724 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1868 00:24:26.948774 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1869 00:24:26.948825 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1870 00:24:26.948876 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1871 00:24:26.948926 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1872 00:24:26.948977 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1873 00:24:26.949028 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1874 00:24:26.949079 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1875 00:24:26.949129 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 00:24:26.949180 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 00:24:26.949231 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 00:24:26.949295 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 00:24:26.949385 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 00:24:26.949436 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 00:24:26.949487 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 00:24:26.949538 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 00:24:26.949589 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1884 00:24:26.949640 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1885 00:24:26.949690 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1886 00:24:26.949741 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1887 00:24:26.949809 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1888 00:24:26.949868 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1889 00:24:26.949920 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1890 00:24:26.949971 Total UI for P1: 0, mck2ui 16
1891 00:24:26.950021 best dqsien dly found for B0: ( 0, 14, 0)
1892 00:24:26.950073 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1893 00:24:26.950123 Total UI for P1: 0, mck2ui 16
1894 00:24:26.950174 best dqsien dly found for B1: ( 0, 14, 4)
1895 00:24:26.950225 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1896 00:24:26.950276 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1897 00:24:26.950327
1898 00:24:26.950378 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1899 00:24:26.950428 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1900 00:24:26.950479 [Gating] SW calibration Done
1901 00:24:26.950529 ==
1902 00:24:26.950580 Dram Type= 6, Freq= 0, CH_1, rank 1
1903 00:24:26.950630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1904 00:24:26.950681 ==
1905 00:24:26.950732 RX Vref Scan: 0
1906 00:24:26.950782
1907 00:24:26.950832 RX Vref 0 -> 0, step: 1
1908 00:24:26.950882
1909 00:24:26.950932 RX Delay -130 -> 252, step: 16
1910 00:24:26.950983 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1911 00:24:26.951034 iDelay=206, Bit 1, Center 77 (-50 ~ 205) 256
1912 00:24:26.951084 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1913 00:24:26.951134 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1914 00:24:26.951185 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1915 00:24:26.951236 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1916 00:24:26.951286 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1917 00:24:26.951337 iDelay=206, Bit 7, Center 77 (-50 ~ 205) 256
1918 00:24:26.951387 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1919 00:24:26.951438 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1920 00:24:26.951488 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1921 00:24:26.951538 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1922 00:24:26.951589 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1923 00:24:26.951640 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1924 00:24:26.951690 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1925 00:24:26.951741 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1926 00:24:26.951792 ==
1927 00:24:26.951842 Dram Type= 6, Freq= 0, CH_1, rank 1
1928 00:24:26.951893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1929 00:24:26.951944 ==
1930 00:24:26.951994 DQS Delay:
1931 00:24:26.952044 DQS0 = 0, DQS1 = 0
1932 00:24:26.952095 DQM Delay:
1933 00:24:26.952144 DQM0 = 81, DQM1 = 79
1934 00:24:26.952194 DQ Delay:
1935 00:24:26.952245 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1936 00:24:26.952296 DQ4 =85, DQ5 =93, DQ6 =85, DQ7 =77
1937 00:24:26.952346 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1938 00:24:26.952396 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1939 00:24:26.952446
1940 00:24:26.952496
1941 00:24:26.952547 ==
1942 00:24:26.952597 Dram Type= 6, Freq= 0, CH_1, rank 1
1943 00:24:26.952647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1944 00:24:26.952698 ==
1945 00:24:26.952749
1946 00:24:26.952798
1947 00:24:26.952848 TX Vref Scan disable
1948 00:24:26.952899 == TX Byte 0 ==
1949 00:24:26.952949 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1950 00:24:26.953001 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1951 00:24:26.953051 == TX Byte 1 ==
1952 00:24:26.953101 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1953 00:24:26.953152 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1954 00:24:27.278969 ==
1955 00:24:27.279106 Dram Type= 6, Freq= 0, CH_1, rank 1
1956 00:24:27.279171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1957 00:24:27.279229 ==
1958 00:24:27.279284 TX Vref=22, minBit 1, minWin=27, winSum=447
1959 00:24:27.279339 TX Vref=24, minBit 1, minWin=27, winSum=448
1960 00:24:27.279392 TX Vref=26, minBit 4, minWin=27, winSum=452
1961 00:24:27.279445 TX Vref=28, minBit 5, minWin=27, winSum=453
1962 00:24:27.279496 TX Vref=30, minBit 0, minWin=28, winSum=457
1963 00:24:27.279546 TX Vref=32, minBit 4, minWin=27, winSum=454
1964 00:24:27.279818 [TxChooseVref] Worse bit 0, Min win 28, Win sum 457, Final Vref 30
1965 00:24:27.279895
1966 00:24:27.279964 Final TX Range 1 Vref 30
1967 00:24:27.280018
1968 00:24:27.280070 ==
1969 00:24:27.280122 Dram Type= 6, Freq= 0, CH_1, rank 1
1970 00:24:27.280190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1971 00:24:27.280257 ==
1972 00:24:27.280308
1973 00:24:27.280358
1974 00:24:27.280408 TX Vref Scan disable
1975 00:24:27.280458 == TX Byte 0 ==
1976 00:24:27.280509 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1977 00:24:27.280560 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1978 00:24:27.280610 == TX Byte 1 ==
1979 00:24:27.280661 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1980 00:24:27.280712 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1981 00:24:27.280763
1982 00:24:27.280813 [DATLAT]
1983 00:24:27.280863 Freq=800, CH1 RK1
1984 00:24:27.280914
1985 00:24:27.280964 DATLAT Default: 0xa
1986 00:24:27.281015 0, 0xFFFF, sum = 0
1987 00:24:27.281066 1, 0xFFFF, sum = 0
1988 00:24:27.281118 2, 0xFFFF, sum = 0
1989 00:24:27.281169 3, 0xFFFF, sum = 0
1990 00:24:27.281264 4, 0xFFFF, sum = 0
1991 00:24:27.281321 5, 0xFFFF, sum = 0
1992 00:24:27.281391 6, 0xFFFF, sum = 0
1993 00:24:27.281443 7, 0xFFFF, sum = 0
1994 00:24:27.281495 8, 0xFFFF, sum = 0
1995 00:24:27.281546 9, 0x0, sum = 1
1996 00:24:27.281599 10, 0x0, sum = 2
1997 00:24:27.281651 11, 0x0, sum = 3
1998 00:24:27.281703 12, 0x0, sum = 4
1999 00:24:27.281770 best_step = 10
2000 00:24:27.281822
2001 00:24:27.281889 ==
2002 00:24:27.281957 Dram Type= 6, Freq= 0, CH_1, rank 1
2003 00:24:27.282022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2004 00:24:27.282073 ==
2005 00:24:27.282139 RX Vref Scan: 0
2006 00:24:27.282205
2007 00:24:27.282285 RX Vref 0 -> 0, step: 1
2008 00:24:27.282336
2009 00:24:27.282386 RX Delay -95 -> 252, step: 8
2010 00:24:27.282437 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
2011 00:24:27.282487 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
2012 00:24:27.282538 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
2013 00:24:27.282588 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
2014 00:24:27.282657 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
2015 00:24:27.282721 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
2016 00:24:27.282771 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2017 00:24:27.282825 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
2018 00:24:27.282876 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2019 00:24:27.282927 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2020 00:24:27.282977 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
2021 00:24:27.283027 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
2022 00:24:27.283078 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
2023 00:24:27.283128 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
2024 00:24:27.283179 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2025 00:24:27.283229 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2026 00:24:27.283280 ==
2027 00:24:27.283330 Dram Type= 6, Freq= 0, CH_1, rank 1
2028 00:24:27.283381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2029 00:24:27.283431 ==
2030 00:24:27.283482 DQS Delay:
2031 00:24:27.283533 DQS0 = 0, DQS1 = 0
2032 00:24:27.283583 DQM Delay:
2033 00:24:27.283633 DQM0 = 86, DQM1 = 81
2034 00:24:27.283684 DQ Delay:
2035 00:24:27.283734 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =84
2036 00:24:27.283785 DQ4 =84, DQ5 =96, DQ6 =92, DQ7 =84
2037 00:24:27.283836 DQ8 =68, DQ9 =72, DQ10 =80, DQ11 =72
2038 00:24:27.283887 DQ12 =88, DQ13 =92, DQ14 =88, DQ15 =88
2039 00:24:27.283938
2040 00:24:27.283988
2041 00:24:27.284038 [DQSOSCAuto] RK1, (LSB)MR18= 0x213e, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 401 ps
2042 00:24:27.284090 CH1 RK1: MR19=606, MR18=213E
2043 00:24:27.284142 CH1_RK1: MR19=0x606, MR18=0x213E, DQSOSC=394, MR23=63, INC=95, DEC=63
2044 00:24:27.284193 [RxdqsGatingPostProcess] freq 800
2045 00:24:27.284244 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2046 00:24:27.284296 Pre-setting of DQS Precalculation
2047 00:24:27.284347 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2048 00:24:27.284398 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2049 00:24:27.284463 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2050 00:24:27.284514
2051 00:24:27.284563
2052 00:24:27.284612 [Calibration Summary] 1600 Mbps
2053 00:24:27.284662 CH 0, Rank 0
2054 00:24:27.284711 SW Impedance : PASS
2055 00:24:27.284777 DUTY Scan : NO K
2056 00:24:27.284841 ZQ Calibration : PASS
2057 00:24:27.284891 Jitter Meter : NO K
2058 00:24:27.284941 CBT Training : PASS
2059 00:24:27.284991 Write leveling : PASS
2060 00:24:27.285041 RX DQS gating : PASS
2061 00:24:27.285091 RX DQ/DQS(RDDQC) : PASS
2062 00:24:27.285141 TX DQ/DQS : PASS
2063 00:24:27.285191 RX DATLAT : PASS
2064 00:24:27.285241 RX DQ/DQS(Engine): PASS
2065 00:24:27.285344 TX OE : NO K
2066 00:24:27.285395 All Pass.
2067 00:24:27.285444
2068 00:24:27.285494 CH 0, Rank 1
2069 00:24:27.285544 SW Impedance : PASS
2070 00:24:27.285595 DUTY Scan : NO K
2071 00:24:27.285644 ZQ Calibration : PASS
2072 00:24:27.285695 Jitter Meter : NO K
2073 00:24:27.285745 CBT Training : PASS
2074 00:24:27.285795 Write leveling : PASS
2075 00:24:27.285845 RX DQS gating : PASS
2076 00:24:27.285895 RX DQ/DQS(RDDQC) : PASS
2077 00:24:27.285945 TX DQ/DQS : PASS
2078 00:24:27.285996 RX DATLAT : PASS
2079 00:24:27.286046 RX DQ/DQS(Engine): PASS
2080 00:24:27.286096 TX OE : NO K
2081 00:24:27.286147 All Pass.
2082 00:24:27.286212
2083 00:24:27.286276 CH 1, Rank 0
2084 00:24:27.286326 SW Impedance : PASS
2085 00:24:27.286376 DUTY Scan : NO K
2086 00:24:27.286427 ZQ Calibration : PASS
2087 00:24:27.286477 Jitter Meter : NO K
2088 00:24:27.286528 CBT Training : PASS
2089 00:24:27.286577 Write leveling : PASS
2090 00:24:27.286628 RX DQS gating : PASS
2091 00:24:27.286678 RX DQ/DQS(RDDQC) : PASS
2092 00:24:27.286728 TX DQ/DQS : PASS
2093 00:24:27.286778 RX DATLAT : PASS
2094 00:24:27.286829 RX DQ/DQS(Engine): PASS
2095 00:24:27.286879 TX OE : NO K
2096 00:24:27.286930 All Pass.
2097 00:24:27.286980
2098 00:24:27.287030 CH 1, Rank 1
2099 00:24:27.287079 SW Impedance : PASS
2100 00:24:27.287129 DUTY Scan : NO K
2101 00:24:27.287180 ZQ Calibration : PASS
2102 00:24:27.287229 Jitter Meter : NO K
2103 00:24:27.287280 CBT Training : PASS
2104 00:24:27.287330 Write leveling : PASS
2105 00:24:27.287380 RX DQS gating : PASS
2106 00:24:27.287430 RX DQ/DQS(RDDQC) : PASS
2107 00:24:27.287480 TX DQ/DQS : PASS
2108 00:24:27.287530 RX DATLAT : PASS
2109 00:24:27.287581 RX DQ/DQS(Engine): PASS
2110 00:24:27.287630 TX OE : NO K
2111 00:24:27.287681 All Pass.
2112 00:24:27.287731
2113 00:24:27.287781 DramC Write-DBI off
2114 00:24:27.287831 PER_BANK_REFRESH: Hybrid Mode
2115 00:24:27.287881 TX_TRACKING: ON
2116 00:24:27.287932 [GetDramInforAfterCalByMRR] Vendor 6.
2117 00:24:27.287982 [GetDramInforAfterCalByMRR] Revision 606.
2118 00:24:27.288033 [GetDramInforAfterCalByMRR] Revision 2 0.
2119 00:24:27.288082 MR0 0x3b3b
2120 00:24:27.288351 MR8 0x5151
2121 00:24:27.288411 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2122 00:24:27.288464
2123 00:24:27.288516 MR0 0x3b3b
2124 00:24:27.288567 MR8 0x5151
2125 00:24:27.288619 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2126 00:24:27.288670
2127 00:24:27.288721 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2128 00:24:27.288773 [FAST_K] Save calibration result to emmc
2129 00:24:27.288825 [FAST_K] Save calibration result to emmc
2130 00:24:27.288877 dram_init: config_dvfs: 1
2131 00:24:27.288927 dramc_set_vcore_voltage set vcore to 662500
2132 00:24:27.288979 Read voltage for 1200, 2
2133 00:24:27.289030 Vio18 = 0
2134 00:24:27.289081 Vcore = 662500
2135 00:24:27.289132 Vdram = 0
2136 00:24:27.289183 Vddq = 0
2137 00:24:27.289233 Vmddr = 0
2138 00:24:27.289322 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2139 00:24:27.289387 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2140 00:24:27.289438 MEM_TYPE=3, freq_sel=15
2141 00:24:27.289488 sv_algorithm_assistance_LP4_1600
2142 00:24:27.289539 ============ PULL DRAM RESETB DOWN ============
2143 00:24:27.289590 ========== PULL DRAM RESETB DOWN end =========
2144 00:24:27.289641 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2145 00:24:27.289692 ===================================
2146 00:24:27.289742 LPDDR4 DRAM CONFIGURATION
2147 00:24:27.289793 ===================================
2148 00:24:27.289843 EX_ROW_EN[0] = 0x0
2149 00:24:27.289894 EX_ROW_EN[1] = 0x0
2150 00:24:27.289944 LP4Y_EN = 0x0
2151 00:24:27.289995 WORK_FSP = 0x0
2152 00:24:27.290045 WL = 0x4
2153 00:24:27.290095 RL = 0x4
2154 00:24:27.290144 BL = 0x2
2155 00:24:27.290194 RPST = 0x0
2156 00:24:27.290244 RD_PRE = 0x0
2157 00:24:27.290294 WR_PRE = 0x1
2158 00:24:27.290344 WR_PST = 0x0
2159 00:24:27.290394 DBI_WR = 0x0
2160 00:24:27.290444 DBI_RD = 0x0
2161 00:24:27.290494 OTF = 0x1
2162 00:24:27.290544 ===================================
2163 00:24:27.290595 ===================================
2164 00:24:27.290645 ANA top config
2165 00:24:27.290695 ===================================
2166 00:24:27.290745 DLL_ASYNC_EN = 0
2167 00:24:27.290795 ALL_SLAVE_EN = 0
2168 00:24:27.290845 NEW_RANK_MODE = 1
2169 00:24:27.290897 DLL_IDLE_MODE = 1
2170 00:24:27.290947 LP45_APHY_COMB_EN = 1
2171 00:24:27.290997 TX_ODT_DIS = 1
2172 00:24:27.291048 NEW_8X_MODE = 1
2173 00:24:27.291114 ===================================
2174 00:24:27.291166 ===================================
2175 00:24:27.291229 data_rate = 2400
2176 00:24:27.291279 CKR = 1
2177 00:24:27.291330 DQ_P2S_RATIO = 8
2178 00:24:27.291380 ===================================
2179 00:24:27.291430 CA_P2S_RATIO = 8
2180 00:24:27.291480 DQ_CA_OPEN = 0
2181 00:24:27.291530 DQ_SEMI_OPEN = 0
2182 00:24:27.291579 CA_SEMI_OPEN = 0
2183 00:24:27.291629 CA_FULL_RATE = 0
2184 00:24:27.291679 DQ_CKDIV4_EN = 0
2185 00:24:27.291730 CA_CKDIV4_EN = 0
2186 00:24:27.291780 CA_PREDIV_EN = 0
2187 00:24:27.291830 PH8_DLY = 17
2188 00:24:27.291881 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2189 00:24:27.291931 DQ_AAMCK_DIV = 4
2190 00:24:27.291981 CA_AAMCK_DIV = 4
2191 00:24:27.292032 CA_ADMCK_DIV = 4
2192 00:24:27.292082 DQ_TRACK_CA_EN = 0
2193 00:24:27.292132 CA_PICK = 1200
2194 00:24:27.292183 CA_MCKIO = 1200
2195 00:24:27.292233 MCKIO_SEMI = 0
2196 00:24:27.292283 PLL_FREQ = 2366
2197 00:24:27.292333 DQ_UI_PI_RATIO = 32
2198 00:24:27.292400 CA_UI_PI_RATIO = 0
2199 00:24:27.292451 ===================================
2200 00:24:27.292503 ===================================
2201 00:24:27.292555 memory_type:LPDDR4
2202 00:24:27.292606 GP_NUM : 10
2203 00:24:27.292700 SRAM_EN : 1
2204 00:24:27.292792 MD32_EN : 0
2205 00:24:27.292849 ===================================
2206 00:24:27.292902 [ANA_INIT] >>>>>>>>>>>>>>
2207 00:24:27.292954 <<<<<< [CONFIGURE PHASE]: ANA_TX
2208 00:24:27.293006 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2209 00:24:27.293058 ===================================
2210 00:24:27.293110 data_rate = 2400,PCW = 0X5b00
2211 00:24:27.293162 ===================================
2212 00:24:27.293214 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2213 00:24:27.293289 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2214 00:24:27.293357 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2215 00:24:27.293410 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2216 00:24:27.293462 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2217 00:24:27.293513 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2218 00:24:27.293564 [ANA_INIT] flow start
2219 00:24:27.293616 [ANA_INIT] PLL >>>>>>>>
2220 00:24:27.293667 [ANA_INIT] PLL <<<<<<<<
2221 00:24:27.293718 [ANA_INIT] MIDPI >>>>>>>>
2222 00:24:27.293769 [ANA_INIT] MIDPI <<<<<<<<
2223 00:24:27.293820 [ANA_INIT] DLL >>>>>>>>
2224 00:24:27.293870 [ANA_INIT] DLL <<<<<<<<
2225 00:24:27.293922 [ANA_INIT] flow end
2226 00:24:27.293973 ============ LP4 DIFF to SE enter ============
2227 00:24:27.294025 ============ LP4 DIFF to SE exit ============
2228 00:24:27.294076 [ANA_INIT] <<<<<<<<<<<<<
2229 00:24:27.294127 [Flow] Enable top DCM control >>>>>
2230 00:24:27.294194 [Flow] Enable top DCM control <<<<<
2231 00:24:27.294248 Enable DLL master slave shuffle
2232 00:24:27.294300 ==============================================================
2233 00:24:27.294352 Gating Mode config
2234 00:24:27.294404 ==============================================================
2235 00:24:27.294455 Config description:
2236 00:24:27.294506 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2237 00:24:27.294559 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2238 00:24:27.294611 SELPH_MODE 0: By rank 1: By Phase
2239 00:24:27.294663 ==============================================================
2240 00:24:27.294714 GAT_TRACK_EN = 1
2241 00:24:27.294958 RX_GATING_MODE = 2
2242 00:24:27.295034 RX_GATING_TRACK_MODE = 2
2243 00:24:27.295088 SELPH_MODE = 1
2244 00:24:27.295141 PICG_EARLY_EN = 1
2245 00:24:27.295194 VALID_LAT_VALUE = 1
2246 00:24:27.295247 ==============================================================
2247 00:24:27.295301 Enter into Gating configuration >>>>
2248 00:24:27.295354 Exit from Gating configuration <<<<
2249 00:24:27.295407 Enter into DVFS_PRE_config >>>>>
2250 00:24:27.295474 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2251 00:24:27.295526 Exit from DVFS_PRE_config <<<<<
2252 00:24:27.295578 Enter into PICG configuration >>>>
2253 00:24:27.295629 Exit from PICG configuration <<<<
2254 00:24:27.295680 [RX_INPUT] configuration >>>>>
2255 00:24:27.295732 [RX_INPUT] configuration <<<<<
2256 00:24:27.295783 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2257 00:24:27.295835 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2258 00:24:27.295886 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2259 00:24:27.295938 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2260 00:24:27.295990 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2261 00:24:27.296042 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2262 00:24:27.296093 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2263 00:24:27.296162 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2264 00:24:27.296228 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2265 00:24:27.296280 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2266 00:24:27.296331 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2267 00:24:27.296383 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2268 00:24:27.296434 ===================================
2269 00:24:27.296486 LPDDR4 DRAM CONFIGURATION
2270 00:24:27.296537 ===================================
2271 00:24:27.296589 EX_ROW_EN[0] = 0x0
2272 00:24:27.296640 EX_ROW_EN[1] = 0x0
2273 00:24:27.296691 LP4Y_EN = 0x0
2274 00:24:27.296742 WORK_FSP = 0x0
2275 00:24:27.296794 WL = 0x4
2276 00:24:27.296845 RL = 0x4
2277 00:24:27.296896 BL = 0x2
2278 00:24:27.296947 RPST = 0x0
2279 00:24:27.296998 RD_PRE = 0x0
2280 00:24:27.297050 WR_PRE = 0x1
2281 00:24:27.297101 WR_PST = 0x0
2282 00:24:27.297152 DBI_WR = 0x0
2283 00:24:27.297203 DBI_RD = 0x0
2284 00:24:27.297254 OTF = 0x1
2285 00:24:27.297345 ===================================
2286 00:24:27.297397 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2287 00:24:27.297448 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2288 00:24:27.297499 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2289 00:24:27.297550 ===================================
2290 00:24:27.297601 LPDDR4 DRAM CONFIGURATION
2291 00:24:27.297653 ===================================
2292 00:24:27.297717 EX_ROW_EN[0] = 0x10
2293 00:24:27.297767 EX_ROW_EN[1] = 0x0
2294 00:24:27.297817 LP4Y_EN = 0x0
2295 00:24:27.297867 WORK_FSP = 0x0
2296 00:24:27.297917 WL = 0x4
2297 00:24:27.297967 RL = 0x4
2298 00:24:27.298017 BL = 0x2
2299 00:24:27.298067 RPST = 0x0
2300 00:24:27.298132 RD_PRE = 0x0
2301 00:24:27.298210 WR_PRE = 0x1
2302 00:24:27.298261 WR_PST = 0x0
2303 00:24:27.298312 DBI_WR = 0x0
2304 00:24:27.298363 DBI_RD = 0x0
2305 00:24:27.298413 OTF = 0x1
2306 00:24:27.298463 ===================================
2307 00:24:27.298514 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2308 00:24:27.298566 ==
2309 00:24:27.298616 Dram Type= 6, Freq= 0, CH_0, rank 0
2310 00:24:27.298667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2311 00:24:27.298718 ==
2312 00:24:27.298769 [Duty_Offset_Calibration]
2313 00:24:27.298819 B0:2 B1:0 CA:4
2314 00:24:27.298870
2315 00:24:27.298919 [DutyScan_Calibration_Flow] k_type=0
2316 00:24:27.298970
2317 00:24:27.299020 ==CLK 0==
2318 00:24:27.299071 Final CLK duty delay cell = 0
2319 00:24:27.299122 [0] MAX Duty = 5156%(X100), DQS PI = 14
2320 00:24:27.299173 [0] MIN Duty = 4969%(X100), DQS PI = 8
2321 00:24:27.299223 [0] AVG Duty = 5062%(X100)
2322 00:24:27.299273
2323 00:24:27.299323 CH0 CLK Duty spec in!! Max-Min= 187%
2324 00:24:27.299374 [DutyScan_Calibration_Flow] ====Done====
2325 00:24:27.299424
2326 00:24:27.299474 [DutyScan_Calibration_Flow] k_type=1
2327 00:24:27.299524
2328 00:24:27.299574 ==DQS 0 ==
2329 00:24:27.299640 Final DQS duty delay cell = 0
2330 00:24:27.299704 [0] MAX Duty = 5156%(X100), DQS PI = 18
2331 00:24:27.299754 [0] MIN Duty = 5093%(X100), DQS PI = 0
2332 00:24:27.299804 [0] AVG Duty = 5124%(X100)
2333 00:24:27.299854
2334 00:24:27.299903 ==DQS 1 ==
2335 00:24:27.299953 Final DQS duty delay cell = 0
2336 00:24:27.300004 [0] MAX Duty = 5125%(X100), DQS PI = 6
2337 00:24:27.300053 [0] MIN Duty = 5000%(X100), DQS PI = 0
2338 00:24:27.300103 [0] AVG Duty = 5062%(X100)
2339 00:24:27.300172
2340 00:24:27.300224 CH0 DQS 0 Duty spec in!! Max-Min= 63%
2341 00:24:27.300287
2342 00:24:27.300337 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2343 00:24:27.300387 [DutyScan_Calibration_Flow] ====Done====
2344 00:24:27.300437
2345 00:24:27.300487 [DutyScan_Calibration_Flow] k_type=3
2346 00:24:27.300536
2347 00:24:27.300586 ==DQM 0 ==
2348 00:24:27.300635 Final DQM duty delay cell = 0
2349 00:24:27.300686 [0] MAX Duty = 5062%(X100), DQS PI = 18
2350 00:24:27.300736 [0] MIN Duty = 4844%(X100), DQS PI = 50
2351 00:24:27.300786 [0] AVG Duty = 4953%(X100)
2352 00:24:27.300836
2353 00:24:27.300885 ==DQM 1 ==
2354 00:24:27.300935 Final DQM duty delay cell = 0
2355 00:24:27.300985 [0] MAX Duty = 4969%(X100), DQS PI = 2
2356 00:24:27.301035 [0] MIN Duty = 4875%(X100), DQS PI = 18
2357 00:24:27.301085 [0] AVG Duty = 4922%(X100)
2358 00:24:27.301150
2359 00:24:27.301200 CH0 DQM 0 Duty spec in!! Max-Min= 218%
2360 00:24:27.301275
2361 00:24:27.301355 CH0 DQM 1 Duty spec in!! Max-Min= 94%
2362 00:24:27.301405 [DutyScan_Calibration_Flow] ====Done====
2363 00:24:27.301454
2364 00:24:27.301504 [DutyScan_Calibration_Flow] k_type=2
2365 00:24:27.301554
2366 00:24:27.301603 ==DQ 0 ==
2367 00:24:27.301653 Final DQ duty delay cell = 0
2368 00:24:27.301703 [0] MAX Duty = 5156%(X100), DQS PI = 18
2369 00:24:27.301753 [0] MIN Duty = 4969%(X100), DQS PI = 58
2370 00:24:27.301802 [0] AVG Duty = 5062%(X100)
2371 00:24:27.301851
2372 00:24:27.301900 ==DQ 1 ==
2373 00:24:27.301950 Final DQ duty delay cell = 0
2374 00:24:27.302001 [0] MAX Duty = 5125%(X100), DQS PI = 4
2375 00:24:27.302051 [0] MIN Duty = 4938%(X100), DQS PI = 16
2376 00:24:27.302293 [0] AVG Duty = 5031%(X100)
2377 00:24:27.302372
2378 00:24:27.302424 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2379 00:24:27.302476
2380 00:24:27.302526 CH0 DQ 1 Duty spec in!! Max-Min= 187%
2381 00:24:27.302578 [DutyScan_Calibration_Flow] ====Done====
2382 00:24:27.302629 ==
2383 00:24:27.302680 Dram Type= 6, Freq= 0, CH_1, rank 0
2384 00:24:27.302731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2385 00:24:27.302783 ==
2386 00:24:27.302834 [Duty_Offset_Calibration]
2387 00:24:27.302884 B0:0 B1:-1 CA:3
2388 00:24:27.302935
2389 00:24:27.302985 [DutyScan_Calibration_Flow] k_type=0
2390 00:24:27.303036
2391 00:24:27.303087 ==CLK 0==
2392 00:24:27.303138 Final CLK duty delay cell = 0
2393 00:24:27.303189 [0] MAX Duty = 5156%(X100), DQS PI = 0
2394 00:24:27.303240 [0] MIN Duty = 5000%(X100), DQS PI = 36
2395 00:24:27.303291 [0] AVG Duty = 5078%(X100)
2396 00:24:27.303341
2397 00:24:27.303392 CH1 CLK Duty spec in!! Max-Min= 156%
2398 00:24:27.303443 [DutyScan_Calibration_Flow] ====Done====
2399 00:24:27.303493
2400 00:24:27.303544 [DutyScan_Calibration_Flow] k_type=1
2401 00:24:27.303595
2402 00:24:27.303645 ==DQS 0 ==
2403 00:24:27.303696 Final DQS duty delay cell = 0
2404 00:24:27.303747 [0] MAX Duty = 5187%(X100), DQS PI = 18
2405 00:24:27.303798 [0] MIN Duty = 4907%(X100), DQS PI = 38
2406 00:24:27.303848 [0] AVG Duty = 5047%(X100)
2407 00:24:27.303899
2408 00:24:27.303949 ==DQS 1 ==
2409 00:24:27.304000 Final DQS duty delay cell = -4
2410 00:24:27.304051 [-4] MAX Duty = 5000%(X100), DQS PI = 32
2411 00:24:27.304102 [-4] MIN Duty = 4875%(X100), DQS PI = 2
2412 00:24:27.304153 [-4] AVG Duty = 4937%(X100)
2413 00:24:27.304210
2414 00:24:27.304261 CH1 DQS 0 Duty spec in!! Max-Min= 280%
2415 00:24:27.304312
2416 00:24:27.304362 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2417 00:24:27.304415 [DutyScan_Calibration_Flow] ====Done====
2418 00:24:27.304466
2419 00:24:27.304516 [DutyScan_Calibration_Flow] k_type=3
2420 00:24:27.304567
2421 00:24:27.304618 ==DQM 0 ==
2422 00:24:27.304669 Final DQM duty delay cell = 0
2423 00:24:27.304720 [0] MAX Duty = 5031%(X100), DQS PI = 28
2424 00:24:27.304772 [0] MIN Duty = 4782%(X100), DQS PI = 38
2425 00:24:27.304822 [0] AVG Duty = 4906%(X100)
2426 00:24:27.304873
2427 00:24:27.304923 ==DQM 1 ==
2428 00:24:27.304973 Final DQM duty delay cell = 0
2429 00:24:27.305024 [0] MAX Duty = 5000%(X100), DQS PI = 34
2430 00:24:27.305075 [0] MIN Duty = 4813%(X100), DQS PI = 0
2431 00:24:27.305125 [0] AVG Duty = 4906%(X100)
2432 00:24:27.305175
2433 00:24:27.305226 CH1 DQM 0 Duty spec in!! Max-Min= 249%
2434 00:24:27.305285
2435 00:24:27.305349 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2436 00:24:27.305399 [DutyScan_Calibration_Flow] ====Done====
2437 00:24:27.305475
2438 00:24:27.305524 [DutyScan_Calibration_Flow] k_type=2
2439 00:24:27.305574
2440 00:24:27.305624 ==DQ 0 ==
2441 00:24:27.305673 Final DQ duty delay cell = -4
2442 00:24:27.305724 [-4] MAX Duty = 5031%(X100), DQS PI = 30
2443 00:24:27.305774 [-4] MIN Duty = 4844%(X100), DQS PI = 36
2444 00:24:27.305823 [-4] AVG Duty = 4937%(X100)
2445 00:24:27.305872
2446 00:24:27.305922 ==DQ 1 ==
2447 00:24:27.305971 Final DQ duty delay cell = 4
2448 00:24:27.306021 [4] MAX Duty = 5156%(X100), DQS PI = 10
2449 00:24:27.306071 [4] MIN Duty = 5031%(X100), DQS PI = 62
2450 00:24:27.306121 [4] AVG Duty = 5093%(X100)
2451 00:24:27.306264
2452 00:24:27.306388 CH1 DQ 0 Duty spec in!! Max-Min= 187%
2453 00:24:27.306455
2454 00:24:27.306505 CH1 DQ 1 Duty spec in!! Max-Min= 125%
2455 00:24:27.306555 [DutyScan_Calibration_Flow] ====Done====
2456 00:24:27.306605 nWR fixed to 30
2457 00:24:27.306656 [ModeRegInit_LP4] CH0 RK0
2458 00:24:27.306705 [ModeRegInit_LP4] CH0 RK1
2459 00:24:27.306756 [ModeRegInit_LP4] CH1 RK0
2460 00:24:27.306806 [ModeRegInit_LP4] CH1 RK1
2461 00:24:27.306856 match AC timing 7
2462 00:24:27.306906 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2463 00:24:27.306956 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2464 00:24:27.307006 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2465 00:24:27.307056 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2466 00:24:27.307106 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2467 00:24:27.307156 ==
2468 00:24:27.307206 Dram Type= 6, Freq= 0, CH_0, rank 0
2469 00:24:27.307256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2470 00:24:27.307306 ==
2471 00:24:27.307355 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2472 00:24:27.307406 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2473 00:24:27.307456 [CA 0] Center 39 (9~70) winsize 62
2474 00:24:27.307520 [CA 1] Center 39 (9~69) winsize 61
2475 00:24:27.307583 [CA 2] Center 35 (5~66) winsize 62
2476 00:24:27.307633 [CA 3] Center 35 (5~66) winsize 62
2477 00:24:27.307682 [CA 4] Center 33 (3~64) winsize 62
2478 00:24:27.307732 [CA 5] Center 33 (3~64) winsize 62
2479 00:24:27.307781
2480 00:24:27.307831 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2481 00:24:27.307880
2482 00:24:27.307929 [CATrainingPosCal] consider 1 rank data
2483 00:24:27.307978 u2DelayCellTimex100 = 270/100 ps
2484 00:24:27.308028 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2485 00:24:27.308078 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2486 00:24:27.308141 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2487 00:24:27.308228 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2488 00:24:27.308306 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2489 00:24:27.308370 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2490 00:24:27.308419
2491 00:24:27.308468 CA PerBit enable=1, Macro0, CA PI delay=33
2492 00:24:27.308518
2493 00:24:27.308567 [CBTSetCACLKResult] CA Dly = 33
2494 00:24:27.308617 CS Dly: 7 (0~38)
2495 00:24:27.308666 ==
2496 00:24:27.308716 Dram Type= 6, Freq= 0, CH_0, rank 1
2497 00:24:27.308766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2498 00:24:27.308817 ==
2499 00:24:27.308867 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2500 00:24:27.308917 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2501 00:24:27.308967 [CA 0] Center 39 (9~70) winsize 62
2502 00:24:27.309017 [CA 1] Center 39 (9~70) winsize 62
2503 00:24:27.309067 [CA 2] Center 35 (5~66) winsize 62
2504 00:24:27.309116 [CA 3] Center 35 (5~66) winsize 62
2505 00:24:27.309165 [CA 4] Center 34 (3~65) winsize 63
2506 00:24:27.309215 [CA 5] Center 33 (3~63) winsize 61
2507 00:24:27.309270
2508 00:24:27.309356 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2509 00:24:27.309406
2510 00:24:27.309455 [CATrainingPosCal] consider 2 rank data
2511 00:24:27.309505 u2DelayCellTimex100 = 270/100 ps
2512 00:24:27.309555 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2513 00:24:27.309605 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2514 00:24:27.309655 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2515 00:24:27.309704 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2516 00:24:27.309754 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2517 00:24:27.309997 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2518 00:24:27.310083
2519 00:24:27.310134 CA PerBit enable=1, Macro0, CA PI delay=33
2520 00:24:27.310185
2521 00:24:27.310235 [CBTSetCACLKResult] CA Dly = 33
2522 00:24:27.310284 CS Dly: 8 (0~41)
2523 00:24:27.310334
2524 00:24:27.310382 ----->DramcWriteLeveling(PI) begin...
2525 00:24:27.310434 ==
2526 00:24:27.310484 Dram Type= 6, Freq= 0, CH_0, rank 0
2527 00:24:27.310533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2528 00:24:27.310583 ==
2529 00:24:27.310633 Write leveling (Byte 0): 31 => 31
2530 00:24:27.310698 Write leveling (Byte 1): 25 => 25
2531 00:24:27.310761 DramcWriteLeveling(PI) end<-----
2532 00:24:27.310810
2533 00:24:27.310859 ==
2534 00:24:27.310909 Dram Type= 6, Freq= 0, CH_0, rank 0
2535 00:24:27.310959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2536 00:24:27.311009 ==
2537 00:24:27.311058 [Gating] SW mode calibration
2538 00:24:27.311109 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2539 00:24:27.311160 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2540 00:24:27.311210 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2541 00:24:27.311260 0 15 4 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
2542 00:24:27.311310 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2543 00:24:27.311360 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2544 00:24:27.311410 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2545 00:24:27.311461 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2546 00:24:27.311510 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2547 00:24:27.311560 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
2548 00:24:27.311610 1 0 0 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
2549 00:24:27.311660 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2550 00:24:27.311710 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2551 00:24:27.311759 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2552 00:24:27.311809 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2553 00:24:27.311859 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2554 00:24:27.311908 1 0 24 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
2555 00:24:27.311958 1 0 28 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
2556 00:24:27.312007 1 1 0 | B1->B0 | 3838 4646 | 1 0 | (0 0) (0 0)
2557 00:24:27.312057 1 1 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
2558 00:24:27.312106 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2559 00:24:27.312155 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2560 00:24:27.312223 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2561 00:24:27.312287 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2562 00:24:27.312365 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2563 00:24:27.312415 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2564 00:24:27.312465 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2565 00:24:27.312515 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2566 00:24:27.312564 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 00:24:27.312614 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 00:24:27.312664 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 00:24:27.312714 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 00:24:27.312763 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 00:24:27.312813 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 00:24:27.312864 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 00:24:27.312914 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 00:24:27.312964 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2575 00:24:27.313014 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2576 00:24:27.313064 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2577 00:24:27.313114 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2578 00:24:27.313163 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2579 00:24:27.313213 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2580 00:24:27.313271 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2581 00:24:27.313379 Total UI for P1: 0, mck2ui 16
2582 00:24:27.313429 best dqsien dly found for B0: ( 1, 3, 28)
2583 00:24:27.313479 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2584 00:24:27.313529 Total UI for P1: 0, mck2ui 16
2585 00:24:27.313579 best dqsien dly found for B1: ( 1, 4, 0)
2586 00:24:27.313629 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2587 00:24:27.313679 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2588 00:24:27.313729
2589 00:24:27.313779 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2590 00:24:27.313829 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2591 00:24:27.313878 [Gating] SW calibration Done
2592 00:24:27.313928 ==
2593 00:24:27.313978 Dram Type= 6, Freq= 0, CH_0, rank 0
2594 00:24:27.314027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2595 00:24:27.314078 ==
2596 00:24:27.314127 RX Vref Scan: 0
2597 00:24:27.314205
2598 00:24:27.314255 RX Vref 0 -> 0, step: 1
2599 00:24:27.314305
2600 00:24:27.314354 RX Delay -40 -> 252, step: 8
2601 00:24:27.314403 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2602 00:24:27.314454 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2603 00:24:27.314504 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2604 00:24:27.314554 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2605 00:24:27.314603 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
2606 00:24:27.314653 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2607 00:24:27.314703 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2608 00:24:27.314754 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
2609 00:24:27.314804 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2610 00:24:27.314854 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2611 00:24:27.314904 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2612 00:24:27.314954 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2613 00:24:27.315035 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2614 00:24:27.315085 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2615 00:24:27.315135 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2616 00:24:27.315185 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2617 00:24:27.315235 ==
2618 00:24:27.315284 Dram Type= 6, Freq= 0, CH_0, rank 0
2619 00:24:27.315525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2620 00:24:27.315635 ==
2621 00:24:27.315687 DQS Delay:
2622 00:24:27.315738 DQS0 = 0, DQS1 = 0
2623 00:24:27.315789 DQM Delay:
2624 00:24:27.315839 DQM0 = 119, DQM1 = 107
2625 00:24:27.315890 DQ Delay:
2626 00:24:27.315941 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2627 00:24:27.315992 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =123
2628 00:24:27.316043 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =103
2629 00:24:27.316093 DQ12 =119, DQ13 =111, DQ14 =119, DQ15 =111
2630 00:24:27.316144
2631 00:24:27.316206
2632 00:24:27.316268 ==
2633 00:24:27.316325 Dram Type= 6, Freq= 0, CH_0, rank 0
2634 00:24:27.316399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2635 00:24:27.316474 ==
2636 00:24:27.316526
2637 00:24:27.316578
2638 00:24:27.316628 TX Vref Scan disable
2639 00:24:27.316692 == TX Byte 0 ==
2640 00:24:27.316742 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2641 00:24:27.316792 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2642 00:24:27.316856 == TX Byte 1 ==
2643 00:24:27.316906 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2644 00:24:27.316957 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2645 00:24:27.317008 ==
2646 00:24:27.317059 Dram Type= 6, Freq= 0, CH_0, rank 0
2647 00:24:27.317110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2648 00:24:27.317162 ==
2649 00:24:27.317213 TX Vref=22, minBit 1, minWin=25, winSum=408
2650 00:24:27.317293 TX Vref=24, minBit 10, minWin=25, winSum=420
2651 00:24:27.317386 TX Vref=26, minBit 4, minWin=25, winSum=423
2652 00:24:27.317451 TX Vref=28, minBit 1, minWin=26, winSum=429
2653 00:24:27.317501 TX Vref=30, minBit 4, minWin=26, winSum=428
2654 00:24:27.317551 TX Vref=32, minBit 4, minWin=26, winSum=428
2655 00:24:27.317601 [TxChooseVref] Worse bit 1, Min win 26, Win sum 429, Final Vref 28
2656 00:24:27.317651
2657 00:24:27.317700 Final TX Range 1 Vref 28
2658 00:24:27.317749
2659 00:24:27.317798 ==
2660 00:24:27.317848 Dram Type= 6, Freq= 0, CH_0, rank 0
2661 00:24:27.317898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2662 00:24:27.317948 ==
2663 00:24:27.317998
2664 00:24:27.318062
2665 00:24:27.318113 TX Vref Scan disable
2666 00:24:27.318163 == TX Byte 0 ==
2667 00:24:27.318227 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2668 00:24:27.318291 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2669 00:24:27.318359 == TX Byte 1 ==
2670 00:24:27.318423 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2671 00:24:27.318474 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2672 00:24:27.318525
2673 00:24:27.318575 [DATLAT]
2674 00:24:27.318639 Freq=1200, CH0 RK0
2675 00:24:27.318688
2676 00:24:27.318738 DATLAT Default: 0xd
2677 00:24:27.318788 0, 0xFFFF, sum = 0
2678 00:24:27.318839 1, 0xFFFF, sum = 0
2679 00:24:27.318889 2, 0xFFFF, sum = 0
2680 00:24:27.318939 3, 0xFFFF, sum = 0
2681 00:24:27.318989 4, 0xFFFF, sum = 0
2682 00:24:27.319039 5, 0xFFFF, sum = 0
2683 00:24:27.319105 6, 0xFFFF, sum = 0
2684 00:24:27.319170 7, 0xFFFF, sum = 0
2685 00:24:27.319220 8, 0xFFFF, sum = 0
2686 00:24:27.319271 9, 0xFFFF, sum = 0
2687 00:24:27.319320 10, 0xFFFF, sum = 0
2688 00:24:27.319371 11, 0xFFFF, sum = 0
2689 00:24:27.319421 12, 0x0, sum = 1
2690 00:24:27.319472 13, 0x0, sum = 2
2691 00:24:27.319522 14, 0x0, sum = 3
2692 00:24:27.319572 15, 0x0, sum = 4
2693 00:24:27.319622 best_step = 13
2694 00:24:27.319672
2695 00:24:27.319721 ==
2696 00:24:27.319770 Dram Type= 6, Freq= 0, CH_0, rank 0
2697 00:24:27.319819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2698 00:24:27.319869 ==
2699 00:24:27.319917 RX Vref Scan: 1
2700 00:24:27.319967
2701 00:24:27.320016 Set Vref Range= 32 -> 127
2702 00:24:27.320065
2703 00:24:27.320114 RX Vref 32 -> 127, step: 1
2704 00:24:27.320163
2705 00:24:27.320212 RX Delay -21 -> 252, step: 4
2706 00:24:27.320277
2707 00:24:27.320357 Set Vref, RX VrefLevel [Byte0]: 32
2708 00:24:27.320420 [Byte1]: 32
2709 00:24:27.320470
2710 00:24:27.320519 Set Vref, RX VrefLevel [Byte0]: 33
2711 00:24:27.320568 [Byte1]: 33
2712 00:24:27.320617
2713 00:24:27.320666 Set Vref, RX VrefLevel [Byte0]: 34
2714 00:24:27.320716 [Byte1]: 34
2715 00:24:27.320765
2716 00:24:27.320815 Set Vref, RX VrefLevel [Byte0]: 35
2717 00:24:27.320864 [Byte1]: 35
2718 00:24:27.320913
2719 00:24:27.320963 Set Vref, RX VrefLevel [Byte0]: 36
2720 00:24:27.321012 [Byte1]: 36
2721 00:24:27.321089
2722 00:24:27.321139 Set Vref, RX VrefLevel [Byte0]: 37
2723 00:24:27.321188 [Byte1]: 37
2724 00:24:27.321238
2725 00:24:27.321343 Set Vref, RX VrefLevel [Byte0]: 38
2726 00:24:27.321394 [Byte1]: 38
2727 00:24:27.321443
2728 00:24:27.321493 Set Vref, RX VrefLevel [Byte0]: 39
2729 00:24:27.321542 [Byte1]: 39
2730 00:24:27.321591
2731 00:24:27.321641 Set Vref, RX VrefLevel [Byte0]: 40
2732 00:24:27.321690 [Byte1]: 40
2733 00:24:27.321740
2734 00:24:27.321789 Set Vref, RX VrefLevel [Byte0]: 41
2735 00:24:27.321839 [Byte1]: 41
2736 00:24:27.321888
2737 00:24:27.321937 Set Vref, RX VrefLevel [Byte0]: 42
2738 00:24:27.321987 [Byte1]: 42
2739 00:24:27.322035
2740 00:24:27.322084 Set Vref, RX VrefLevel [Byte0]: 43
2741 00:24:27.322133 [Byte1]: 43
2742 00:24:27.322183
2743 00:24:27.322232 Set Vref, RX VrefLevel [Byte0]: 44
2744 00:24:27.322284 [Byte1]: 44
2745 00:24:27.322334
2746 00:24:27.322384 Set Vref, RX VrefLevel [Byte0]: 45
2747 00:24:27.322434 [Byte1]: 45
2748 00:24:27.322483
2749 00:24:27.322533 Set Vref, RX VrefLevel [Byte0]: 46
2750 00:24:27.322582 [Byte1]: 46
2751 00:24:27.322632
2752 00:24:27.322681 Set Vref, RX VrefLevel [Byte0]: 47
2753 00:24:27.322731 [Byte1]: 47
2754 00:24:27.322780
2755 00:24:27.322829 Set Vref, RX VrefLevel [Byte0]: 48
2756 00:24:27.322879 [Byte1]: 48
2757 00:24:27.322928
2758 00:24:27.322977 Set Vref, RX VrefLevel [Byte0]: 49
2759 00:24:27.323026 [Byte1]: 49
2760 00:24:27.323076
2761 00:24:27.323125 Set Vref, RX VrefLevel [Byte0]: 50
2762 00:24:27.323174 [Byte1]: 50
2763 00:24:27.323224
2764 00:24:27.323273 Set Vref, RX VrefLevel [Byte0]: 51
2765 00:24:27.323322 [Byte1]: 51
2766 00:24:27.323372
2767 00:24:27.323421 Set Vref, RX VrefLevel [Byte0]: 52
2768 00:24:27.323470 [Byte1]: 52
2769 00:24:27.323520
2770 00:24:27.323569 Set Vref, RX VrefLevel [Byte0]: 53
2771 00:24:27.323619 [Byte1]: 53
2772 00:24:27.323668
2773 00:24:27.323718 Set Vref, RX VrefLevel [Byte0]: 54
2774 00:24:27.323767 [Byte1]: 54
2775 00:24:27.323832
2776 00:24:27.323895 Set Vref, RX VrefLevel [Byte0]: 55
2777 00:24:27.323945 [Byte1]: 55
2778 00:24:27.323995
2779 00:24:27.324044 Set Vref, RX VrefLevel [Byte0]: 56
2780 00:24:27.324094 [Byte1]: 56
2781 00:24:27.324143
2782 00:24:27.324192 Set Vref, RX VrefLevel [Byte0]: 57
2783 00:24:27.324242 [Byte1]: 57
2784 00:24:27.324291
2785 00:24:27.324351 Set Vref, RX VrefLevel [Byte0]: 58
2786 00:24:27.324401 [Byte1]: 58
2787 00:24:27.324451
2788 00:24:27.324691 Set Vref, RX VrefLevel [Byte0]: 59
2789 00:24:27.324779 [Byte1]: 59
2790 00:24:27.324830
2791 00:24:27.324880 Set Vref, RX VrefLevel [Byte0]: 60
2792 00:24:27.324929 [Byte1]: 60
2793 00:24:27.324979
2794 00:24:27.325028 Set Vref, RX VrefLevel [Byte0]: 61
2795 00:24:27.325077 [Byte1]: 61
2796 00:24:27.325127
2797 00:24:27.325176 Set Vref, RX VrefLevel [Byte0]: 62
2798 00:24:27.325226 [Byte1]: 62
2799 00:24:27.325317
2800 00:24:27.325395 Set Vref, RX VrefLevel [Byte0]: 63
2801 00:24:27.325445 [Byte1]: 63
2802 00:24:27.325495
2803 00:24:27.325544 Set Vref, RX VrefLevel [Byte0]: 64
2804 00:24:27.325594 [Byte1]: 64
2805 00:24:27.325643
2806 00:24:27.325692 Set Vref, RX VrefLevel [Byte0]: 65
2807 00:24:27.325742 [Byte1]: 65
2808 00:24:27.325791
2809 00:24:27.325840 Set Vref, RX VrefLevel [Byte0]: 66
2810 00:24:27.325890 [Byte1]: 66
2811 00:24:27.325940
2812 00:24:27.325988 Set Vref, RX VrefLevel [Byte0]: 67
2813 00:24:27.326038 [Byte1]: 67
2814 00:24:27.326088
2815 00:24:27.326137 Final RX Vref Byte 0 = 57 to rank0
2816 00:24:27.326187 Final RX Vref Byte 1 = 50 to rank0
2817 00:24:27.326236 Final RX Vref Byte 0 = 57 to rank1
2818 00:24:27.326301 Final RX Vref Byte 1 = 50 to rank1==
2819 00:24:27.326365 Dram Type= 6, Freq= 0, CH_0, rank 0
2820 00:24:27.326416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2821 00:24:27.326465 ==
2822 00:24:27.326530 DQS Delay:
2823 00:24:27.326593 DQS0 = 0, DQS1 = 0
2824 00:24:27.326659 DQM Delay:
2825 00:24:27.326722 DQM0 = 119, DQM1 = 106
2826 00:24:27.326771 DQ Delay:
2827 00:24:27.326820 DQ0 =120, DQ1 =116, DQ2 =116, DQ3 =114
2828 00:24:27.326882 DQ4 =122, DQ5 =114, DQ6 =128, DQ7 =122
2829 00:24:27.326936 DQ8 =96, DQ9 =90, DQ10 =106, DQ11 =100
2830 00:24:27.326986 DQ12 =116, DQ13 =110, DQ14 =116, DQ15 =114
2831 00:24:27.327036
2832 00:24:27.327085
2833 00:24:27.327151 [DQSOSCAuto] RK0, (LSB)MR18= 0x1fd, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 409 ps
2834 00:24:27.327214 CH0 RK0: MR19=403, MR18=1FD
2835 00:24:27.327264 CH0_RK0: MR19=0x403, MR18=0x1FD, DQSOSC=409, MR23=63, INC=39, DEC=26
2836 00:24:27.327314
2837 00:24:27.327363 ----->DramcWriteLeveling(PI) begin...
2838 00:24:27.327413 ==
2839 00:24:27.327463 Dram Type= 6, Freq= 0, CH_0, rank 1
2840 00:24:27.327512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2841 00:24:27.327563 ==
2842 00:24:27.327612 Write leveling (Byte 0): 31 => 31
2843 00:24:27.327661 Write leveling (Byte 1): 26 => 26
2844 00:24:27.327711 DramcWriteLeveling(PI) end<-----
2845 00:24:27.327760
2846 00:24:27.327809 ==
2847 00:24:27.327858 Dram Type= 6, Freq= 0, CH_0, rank 1
2848 00:24:27.327907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2849 00:24:27.327957 ==
2850 00:24:27.328007 [Gating] SW mode calibration
2851 00:24:27.328056 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2852 00:24:27.328106 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2853 00:24:27.328156 0 15 0 | B1->B0 | 2524 3434 | 1 1 | (0 0) (1 1)
2854 00:24:27.328206 0 15 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
2855 00:24:27.328256 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2856 00:24:27.328306 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2857 00:24:27.328371 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2858 00:24:27.328423 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2859 00:24:27.328474 0 15 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
2860 00:24:27.328525 0 15 28 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 0)
2861 00:24:27.328588 1 0 0 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
2862 00:24:27.328638 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2863 00:24:27.328687 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2864 00:24:27.328737 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2865 00:24:27.328787 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2866 00:24:27.328837 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2867 00:24:27.328886 1 0 24 | B1->B0 | 2323 3534 | 0 1 | (0 0) (0 0)
2868 00:24:27.328936 1 0 28 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
2869 00:24:27.328985 1 1 0 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
2870 00:24:27.329035 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2871 00:24:27.329085 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2872 00:24:27.329150 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2873 00:24:27.329200 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2874 00:24:27.329251 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2875 00:24:27.329306 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2876 00:24:27.329369 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2877 00:24:27.329419 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2878 00:24:27.329468 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 00:24:27.329519 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 00:24:27.329568 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 00:24:27.329617 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 00:24:27.329667 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 00:24:27.329717 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 00:24:27.329766 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 00:24:27.329816 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 00:24:27.329866 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 00:24:27.329915 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 00:24:27.329964 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 00:24:27.330013 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 00:24:27.330063 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 00:24:27.330113 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2892 00:24:27.330163 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2893 00:24:27.330212 Total UI for P1: 0, mck2ui 16
2894 00:24:27.330262 best dqsien dly found for B0: ( 1, 3, 24)
2895 00:24:27.330312 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2896 00:24:27.330362 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2897 00:24:27.330604 Total UI for P1: 0, mck2ui 16
2898 00:24:27.330665 best dqsien dly found for B1: ( 1, 3, 30)
2899 00:24:27.330717 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2900 00:24:27.330767 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2901 00:24:27.330818
2902 00:24:27.330868 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2903 00:24:27.330918 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2904 00:24:27.330969 [Gating] SW calibration Done
2905 00:24:27.331019 ==
2906 00:24:27.331070 Dram Type= 6, Freq= 0, CH_0, rank 1
2907 00:24:27.331121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2908 00:24:27.331172 ==
2909 00:24:27.331223 RX Vref Scan: 0
2910 00:24:27.331273
2911 00:24:27.331323 RX Vref 0 -> 0, step: 1
2912 00:24:27.331374
2913 00:24:27.331424 RX Delay -40 -> 252, step: 8
2914 00:24:27.331475 iDelay=200, Bit 0, Center 115 (48 ~ 183) 136
2915 00:24:27.331526 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2916 00:24:27.331577 iDelay=200, Bit 2, Center 115 (48 ~ 183) 136
2917 00:24:27.331628 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2918 00:24:27.331678 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
2919 00:24:27.331729 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2920 00:24:27.331779 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2921 00:24:27.331830 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2922 00:24:27.331880 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2923 00:24:27.331930 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2924 00:24:27.331980 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2925 00:24:27.332031 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2926 00:24:27.332080 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2927 00:24:27.332131 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2928 00:24:27.332181 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2929 00:24:27.332233 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2930 00:24:27.332284 ==
2931 00:24:27.332334 Dram Type= 6, Freq= 0, CH_0, rank 1
2932 00:24:27.332397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2933 00:24:27.332447 ==
2934 00:24:27.332497 DQS Delay:
2935 00:24:27.332562 DQS0 = 0, DQS1 = 0
2936 00:24:27.332629 DQM Delay:
2937 00:24:27.332694 DQM0 = 119, DQM1 = 107
2938 00:24:27.332744 DQ Delay:
2939 00:24:27.332794 DQ0 =115, DQ1 =119, DQ2 =115, DQ3 =115
2940 00:24:27.332857 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2941 00:24:27.332907 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2942 00:24:27.332969 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =115
2943 00:24:27.333019
2944 00:24:27.333070
2945 00:24:27.333120 ==
2946 00:24:27.333169 Dram Type= 6, Freq= 0, CH_0, rank 1
2947 00:24:27.333220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2948 00:24:27.333279 ==
2949 00:24:27.333331
2950 00:24:27.333381
2951 00:24:27.333431 TX Vref Scan disable
2952 00:24:27.333481 == TX Byte 0 ==
2953 00:24:27.333531 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2954 00:24:27.333582 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2955 00:24:27.333633 == TX Byte 1 ==
2956 00:24:27.333684 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2957 00:24:27.333735 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2958 00:24:27.333786 ==
2959 00:24:27.333836 Dram Type= 6, Freq= 0, CH_0, rank 1
2960 00:24:27.333887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2961 00:24:27.333938 ==
2962 00:24:27.333988 TX Vref=22, minBit 13, minWin=24, winSum=418
2963 00:24:27.334040 TX Vref=24, minBit 1, minWin=25, winSum=415
2964 00:24:27.334091 TX Vref=26, minBit 2, minWin=25, winSum=424
2965 00:24:27.334142 TX Vref=28, minBit 1, minWin=26, winSum=423
2966 00:24:27.334193 TX Vref=30, minBit 0, minWin=26, winSum=428
2967 00:24:27.334244 TX Vref=32, minBit 0, minWin=26, winSum=424
2968 00:24:27.334295 [TxChooseVref] Worse bit 0, Min win 26, Win sum 428, Final Vref 30
2969 00:24:27.334346
2970 00:24:27.442023 Final TX Range 1 Vref 30
2971 00:24:27.442144
2972 00:24:27.442208 ==
2973 00:24:27.442266 Dram Type= 6, Freq= 0, CH_0, rank 1
2974 00:24:27.442322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2975 00:24:27.442377 ==
2976 00:24:27.442430
2977 00:24:27.442482
2978 00:24:27.442534 TX Vref Scan disable
2979 00:24:27.442585 == TX Byte 0 ==
2980 00:24:27.442638 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2981 00:24:27.442690 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2982 00:24:27.442741 == TX Byte 1 ==
2983 00:24:27.442793 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2984 00:24:27.442845 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2985 00:24:27.442897
2986 00:24:27.442948 [DATLAT]
2987 00:24:27.442999 Freq=1200, CH0 RK1
2988 00:24:27.443051
2989 00:24:27.443101 DATLAT Default: 0xd
2990 00:24:27.443151 0, 0xFFFF, sum = 0
2991 00:24:27.443203 1, 0xFFFF, sum = 0
2992 00:24:27.443255 2, 0xFFFF, sum = 0
2993 00:24:27.443306 3, 0xFFFF, sum = 0
2994 00:24:27.443358 4, 0xFFFF, sum = 0
2995 00:24:27.443409 5, 0xFFFF, sum = 0
2996 00:24:27.443461 6, 0xFFFF, sum = 0
2997 00:24:27.443512 7, 0xFFFF, sum = 0
2998 00:24:27.443563 8, 0xFFFF, sum = 0
2999 00:24:27.443614 9, 0xFFFF, sum = 0
3000 00:24:27.443666 10, 0xFFFF, sum = 0
3001 00:24:27.443718 11, 0xFFFF, sum = 0
3002 00:24:27.443769 12, 0x0, sum = 1
3003 00:24:27.443821 13, 0x0, sum = 2
3004 00:24:27.443872 14, 0x0, sum = 3
3005 00:24:27.443924 15, 0x0, sum = 4
3006 00:24:27.443975 best_step = 13
3007 00:24:27.444026
3008 00:24:27.444076 ==
3009 00:24:27.444126 Dram Type= 6, Freq= 0, CH_0, rank 1
3010 00:24:27.444177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3011 00:24:27.444227 ==
3012 00:24:27.444278 RX Vref Scan: 0
3013 00:24:27.444328
3014 00:24:27.444379 RX Vref 0 -> 0, step: 1
3015 00:24:27.444429
3016 00:24:27.444479 RX Delay -21 -> 252, step: 4
3017 00:24:27.444529 iDelay=195, Bit 0, Center 116 (51 ~ 182) 132
3018 00:24:27.444580 iDelay=195, Bit 1, Center 118 (51 ~ 186) 136
3019 00:24:27.444631 iDelay=195, Bit 2, Center 114 (51 ~ 178) 128
3020 00:24:27.444681 iDelay=195, Bit 3, Center 114 (51 ~ 178) 128
3021 00:24:27.444732 iDelay=195, Bit 4, Center 120 (59 ~ 182) 124
3022 00:24:27.444782 iDelay=195, Bit 5, Center 112 (47 ~ 178) 132
3023 00:24:27.444832 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3024 00:24:27.444883 iDelay=195, Bit 7, Center 122 (55 ~ 190) 136
3025 00:24:27.444933 iDelay=195, Bit 8, Center 96 (27 ~ 166) 140
3026 00:24:27.444984 iDelay=195, Bit 9, Center 94 (27 ~ 162) 136
3027 00:24:27.445034 iDelay=195, Bit 10, Center 108 (43 ~ 174) 132
3028 00:24:27.445085 iDelay=195, Bit 11, Center 98 (31 ~ 166) 136
3029 00:24:27.445135 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3030 00:24:27.445186 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
3031 00:24:27.445236 iDelay=195, Bit 14, Center 120 (55 ~ 186) 132
3032 00:24:27.445293 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3033 00:24:27.445345 ==
3034 00:24:27.445395 Dram Type= 6, Freq= 0, CH_0, rank 1
3035 00:24:27.445446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3036 00:24:27.445497 ==
3037 00:24:27.445547 DQS Delay:
3038 00:24:27.445598 DQS0 = 0, DQS1 = 0
3039 00:24:27.445855 DQM Delay:
3040 00:24:27.445914 DQM0 = 118, DQM1 = 107
3041 00:24:27.445966 DQ Delay:
3042 00:24:27.446017 DQ0 =116, DQ1 =118, DQ2 =114, DQ3 =114
3043 00:24:27.446068 DQ4 =120, DQ5 =112, DQ6 =128, DQ7 =122
3044 00:24:27.446118 DQ8 =96, DQ9 =94, DQ10 =108, DQ11 =98
3045 00:24:27.446169 DQ12 =112, DQ13 =112, DQ14 =120, DQ15 =116
3046 00:24:27.446219
3047 00:24:27.446268
3048 00:24:27.446318 [DQSOSCAuto] RK1, (LSB)MR18= 0x1ff, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 409 ps
3049 00:24:27.446369 CH0 RK1: MR19=403, MR18=1FF
3050 00:24:27.446420 CH0_RK1: MR19=0x403, MR18=0x1FF, DQSOSC=409, MR23=63, INC=39, DEC=26
3051 00:24:27.446471 [RxdqsGatingPostProcess] freq 1200
3052 00:24:27.446522 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3053 00:24:27.446573 best DQS0 dly(2T, 0.5T) = (0, 11)
3054 00:24:27.446624 best DQS1 dly(2T, 0.5T) = (0, 12)
3055 00:24:27.446674 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3056 00:24:27.446725 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3057 00:24:27.446775 best DQS0 dly(2T, 0.5T) = (0, 11)
3058 00:24:27.446825 best DQS1 dly(2T, 0.5T) = (0, 11)
3059 00:24:27.446875 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3060 00:24:27.446926 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3061 00:24:27.446976 Pre-setting of DQS Precalculation
3062 00:24:27.447026 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3063 00:24:27.447077 ==
3064 00:24:27.447127 Dram Type= 6, Freq= 0, CH_1, rank 0
3065 00:24:27.447178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3066 00:24:27.447228 ==
3067 00:24:27.447278 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3068 00:24:27.447329 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3069 00:24:27.447379 [CA 0] Center 38 (8~68) winsize 61
3070 00:24:27.447430 [CA 1] Center 37 (7~68) winsize 62
3071 00:24:27.447480 [CA 2] Center 35 (6~65) winsize 60
3072 00:24:27.447531 [CA 3] Center 34 (4~64) winsize 61
3073 00:24:27.447581 [CA 4] Center 35 (5~65) winsize 61
3074 00:24:27.447631 [CA 5] Center 33 (3~63) winsize 61
3075 00:24:27.447681
3076 00:24:27.447731 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3077 00:24:27.447782
3078 00:24:27.447831 [CATrainingPosCal] consider 1 rank data
3079 00:24:27.447881 u2DelayCellTimex100 = 270/100 ps
3080 00:24:27.447933 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3081 00:24:27.447983 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3082 00:24:27.448034 CA2 delay=35 (6~65),Diff = 2 PI (9 cell)
3083 00:24:27.448084 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3084 00:24:27.448134 CA4 delay=35 (5~65),Diff = 2 PI (9 cell)
3085 00:24:27.448185 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3086 00:24:27.448235
3087 00:24:27.448285 CA PerBit enable=1, Macro0, CA PI delay=33
3088 00:24:27.448336
3089 00:24:27.448386 [CBTSetCACLKResult] CA Dly = 33
3090 00:24:27.448468 CS Dly: 5 (0~36)
3091 00:24:27.448519 ==
3092 00:24:27.448569 Dram Type= 6, Freq= 0, CH_1, rank 1
3093 00:24:27.448620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3094 00:24:27.448671 ==
3095 00:24:27.448722 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3096 00:24:27.448773 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3097 00:24:27.448825 [CA 0] Center 37 (7~68) winsize 62
3098 00:24:27.448875 [CA 1] Center 38 (8~68) winsize 61
3099 00:24:27.448926 [CA 2] Center 34 (4~65) winsize 62
3100 00:24:27.448977 [CA 3] Center 33 (3~64) winsize 62
3101 00:24:27.449027 [CA 4] Center 34 (4~64) winsize 61
3102 00:24:27.449094 [CA 5] Center 33 (3~63) winsize 61
3103 00:24:27.449146
3104 00:24:27.449197 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3105 00:24:27.449249
3106 00:24:27.449321 [CATrainingPosCal] consider 2 rank data
3107 00:24:27.449371 u2DelayCellTimex100 = 270/100 ps
3108 00:24:27.449422 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3109 00:24:27.449472 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3110 00:24:27.449523 CA2 delay=35 (6~65),Diff = 2 PI (9 cell)
3111 00:24:27.449573 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3112 00:24:27.449624 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3113 00:24:27.449674 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3114 00:24:27.449725
3115 00:24:27.449776 CA PerBit enable=1, Macro0, CA PI delay=33
3116 00:24:27.449826
3117 00:24:27.449877 [CBTSetCACLKResult] CA Dly = 33
3118 00:24:27.449927 CS Dly: 6 (0~39)
3119 00:24:27.449978
3120 00:24:27.450028 ----->DramcWriteLeveling(PI) begin...
3121 00:24:27.450080 ==
3122 00:24:27.450130 Dram Type= 6, Freq= 0, CH_1, rank 0
3123 00:24:27.450182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3124 00:24:27.450233 ==
3125 00:24:27.450284 Write leveling (Byte 0): 24 => 24
3126 00:24:27.450334 Write leveling (Byte 1): 26 => 26
3127 00:24:27.450385 DramcWriteLeveling(PI) end<-----
3128 00:24:27.450436
3129 00:24:27.450486 ==
3130 00:24:27.450537 Dram Type= 6, Freq= 0, CH_1, rank 0
3131 00:24:27.450619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3132 00:24:27.450670 ==
3133 00:24:27.450720 [Gating] SW mode calibration
3134 00:24:27.450772 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3135 00:24:27.450823 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3136 00:24:27.450875 0 15 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
3137 00:24:27.450926 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3138 00:24:27.450977 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3139 00:24:27.451028 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3140 00:24:27.451079 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3141 00:24:27.451129 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3142 00:24:27.451180 0 15 24 | B1->B0 | 3434 3232 | 0 1 | (0 1) (1 0)
3143 00:24:27.451231 0 15 28 | B1->B0 | 2828 2727 | 1 0 | (0 0) (0 0)
3144 00:24:27.451282 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3145 00:24:27.451333 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3146 00:24:27.451384 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3147 00:24:27.451435 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3148 00:24:27.451486 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3149 00:24:27.451537 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3150 00:24:27.451589 1 0 24 | B1->B0 | 2525 2d2d | 0 0 | (0 0) (0 0)
3151 00:24:27.451640 1 0 28 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
3152 00:24:27.451691 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3153 00:24:27.451939 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3154 00:24:27.452053 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3155 00:24:27.452120 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3156 00:24:27.452172 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3157 00:24:27.452223 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3158 00:24:27.452274 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3159 00:24:27.452325 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3160 00:24:27.452376 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 00:24:27.452427 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 00:24:27.452479 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 00:24:27.452530 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 00:24:27.452584 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 00:24:27.452636 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 00:24:27.452687 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 00:24:27.452738 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 00:24:27.452789 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 00:24:27.452840 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 00:24:27.452892 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 00:24:27.452943 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 00:24:27.452993 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 00:24:27.453044 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 00:24:27.453095 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3175 00:24:27.453146 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3176 00:24:27.453197 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3177 00:24:27.453248 Total UI for P1: 0, mck2ui 16
3178 00:24:27.453335 best dqsien dly found for B0: ( 1, 3, 26)
3179 00:24:27.453387 Total UI for P1: 0, mck2ui 16
3180 00:24:27.453438 best dqsien dly found for B1: ( 1, 3, 26)
3181 00:24:27.453489 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3182 00:24:27.453541 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3183 00:24:27.453591
3184 00:24:27.453642 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3185 00:24:27.453693 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3186 00:24:27.453744 [Gating] SW calibration Done
3187 00:24:27.453794 ==
3188 00:24:27.453845 Dram Type= 6, Freq= 0, CH_1, rank 0
3189 00:24:27.453896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3190 00:24:27.453948 ==
3191 00:24:27.453998 RX Vref Scan: 0
3192 00:24:27.454049
3193 00:24:27.454100 RX Vref 0 -> 0, step: 1
3194 00:24:27.454151
3195 00:24:27.454202 RX Delay -40 -> 252, step: 8
3196 00:24:27.454253 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3197 00:24:27.454304 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3198 00:24:27.454355 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3199 00:24:27.454406 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3200 00:24:27.454457 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3201 00:24:27.454507 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3202 00:24:27.454558 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3203 00:24:27.454609 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3204 00:24:27.454660 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3205 00:24:27.454711 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3206 00:24:27.454762 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3207 00:24:27.454813 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3208 00:24:27.454864 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3209 00:24:27.454915 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3210 00:24:27.454965 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3211 00:24:27.455016 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3212 00:24:27.455067 ==
3213 00:24:27.455117 Dram Type= 6, Freq= 0, CH_1, rank 0
3214 00:24:27.455168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3215 00:24:27.455219 ==
3216 00:24:27.455269 DQS Delay:
3217 00:24:27.455319 DQS0 = 0, DQS1 = 0
3218 00:24:27.455370 DQM Delay:
3219 00:24:27.455420 DQM0 = 118, DQM1 = 114
3220 00:24:27.455471 DQ Delay:
3221 00:24:27.455521 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3222 00:24:27.455572 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3223 00:24:27.455623 DQ8 =103, DQ9 =103, DQ10 =115, DQ11 =111
3224 00:24:27.455673 DQ12 =123, DQ13 =123, DQ14 =119, DQ15 =119
3225 00:24:27.455724
3226 00:24:27.455774
3227 00:24:27.455824 ==
3228 00:24:27.455874 Dram Type= 6, Freq= 0, CH_1, rank 0
3229 00:24:27.455924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3230 00:24:27.455975 ==
3231 00:24:27.456026
3232 00:24:27.456076
3233 00:24:27.456126 TX Vref Scan disable
3234 00:24:27.456177 == TX Byte 0 ==
3235 00:24:27.456228 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3236 00:24:27.456279 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3237 00:24:27.456330 == TX Byte 1 ==
3238 00:24:27.456381 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3239 00:24:27.456432 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3240 00:24:27.456483 ==
3241 00:24:27.456533 Dram Type= 6, Freq= 0, CH_1, rank 0
3242 00:24:27.456584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3243 00:24:27.456635 ==
3244 00:24:27.456686 TX Vref=22, minBit 8, minWin=24, winSum=406
3245 00:24:27.456738 TX Vref=24, minBit 3, minWin=24, winSum=410
3246 00:24:27.456789 TX Vref=26, minBit 11, minWin=24, winSum=416
3247 00:24:27.456840 TX Vref=28, minBit 2, minWin=25, winSum=423
3248 00:24:27.456891 TX Vref=30, minBit 9, minWin=25, winSum=423
3249 00:24:27.456942 TX Vref=32, minBit 11, minWin=24, winSum=423
3250 00:24:27.456993 [TxChooseVref] Worse bit 2, Min win 25, Win sum 423, Final Vref 28
3251 00:24:27.457044
3252 00:24:27.457097 Final TX Range 1 Vref 28
3253 00:24:27.457148
3254 00:24:27.457198 ==
3255 00:24:27.457249 Dram Type= 6, Freq= 0, CH_1, rank 0
3256 00:24:27.457328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3257 00:24:27.457393 ==
3258 00:24:27.457444
3259 00:24:27.457494
3260 00:24:27.457544 TX Vref Scan disable
3261 00:24:27.457595 == TX Byte 0 ==
3262 00:24:27.457646 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3263 00:24:27.457697 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3264 00:24:27.457748 == TX Byte 1 ==
3265 00:24:27.457798 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3266 00:24:27.457849 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3267 00:24:27.457900
3268 00:24:27.457950 [DATLAT]
3269 00:24:27.458001 Freq=1200, CH1 RK0
3270 00:24:27.458051
3271 00:24:27.458102 DATLAT Default: 0xd
3272 00:24:27.458152 0, 0xFFFF, sum = 0
3273 00:24:27.458204 1, 0xFFFF, sum = 0
3274 00:24:27.458449 2, 0xFFFF, sum = 0
3275 00:24:27.458508 3, 0xFFFF, sum = 0
3276 00:24:27.458562 4, 0xFFFF, sum = 0
3277 00:24:27.458614 5, 0xFFFF, sum = 0
3278 00:24:27.458666 6, 0xFFFF, sum = 0
3279 00:24:27.458718 7, 0xFFFF, sum = 0
3280 00:24:27.458769 8, 0xFFFF, sum = 0
3281 00:24:27.458821 9, 0xFFFF, sum = 0
3282 00:24:27.458874 10, 0xFFFF, sum = 0
3283 00:24:27.458926 11, 0xFFFF, sum = 0
3284 00:24:27.458978 12, 0x0, sum = 1
3285 00:24:27.459030 13, 0x0, sum = 2
3286 00:24:27.459082 14, 0x0, sum = 3
3287 00:24:27.459133 15, 0x0, sum = 4
3288 00:24:27.459186 best_step = 13
3289 00:24:27.459237
3290 00:24:27.459287 ==
3291 00:24:27.459337 Dram Type= 6, Freq= 0, CH_1, rank 0
3292 00:24:27.459389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3293 00:24:27.459440 ==
3294 00:24:27.459491 RX Vref Scan: 1
3295 00:24:27.459542
3296 00:24:27.459592 Set Vref Range= 32 -> 127
3297 00:24:27.459643
3298 00:24:27.459693 RX Vref 32 -> 127, step: 1
3299 00:24:27.459744
3300 00:24:27.459795 RX Delay -13 -> 252, step: 4
3301 00:24:27.459845
3302 00:24:27.459896 Set Vref, RX VrefLevel [Byte0]: 32
3303 00:24:27.459947 [Byte1]: 32
3304 00:24:27.459998
3305 00:24:27.460049 Set Vref, RX VrefLevel [Byte0]: 33
3306 00:24:27.460099 [Byte1]: 33
3307 00:24:27.460150
3308 00:24:27.460200 Set Vref, RX VrefLevel [Byte0]: 34
3309 00:24:27.460251 [Byte1]: 34
3310 00:24:27.460301
3311 00:24:27.460352 Set Vref, RX VrefLevel [Byte0]: 35
3312 00:24:27.460402 [Byte1]: 35
3313 00:24:27.460453
3314 00:24:27.460504 Set Vref, RX VrefLevel [Byte0]: 36
3315 00:24:27.460555 [Byte1]: 36
3316 00:24:27.460606
3317 00:24:27.460656 Set Vref, RX VrefLevel [Byte0]: 37
3318 00:24:27.460707 [Byte1]: 37
3319 00:24:27.460757
3320 00:24:27.460807 Set Vref, RX VrefLevel [Byte0]: 38
3321 00:24:27.460858 [Byte1]: 38
3322 00:24:27.460908
3323 00:24:27.460959 Set Vref, RX VrefLevel [Byte0]: 39
3324 00:24:27.461010 [Byte1]: 39
3325 00:24:27.461061
3326 00:24:27.461111 Set Vref, RX VrefLevel [Byte0]: 40
3327 00:24:27.461162 [Byte1]: 40
3328 00:24:27.461212
3329 00:24:27.461270 Set Vref, RX VrefLevel [Byte0]: 41
3330 00:24:27.461360 [Byte1]: 41
3331 00:24:27.461411
3332 00:24:27.461461 Set Vref, RX VrefLevel [Byte0]: 42
3333 00:24:27.461512 [Byte1]: 42
3334 00:24:27.461562
3335 00:24:27.461612 Set Vref, RX VrefLevel [Byte0]: 43
3336 00:24:27.461662 [Byte1]: 43
3337 00:24:27.461712
3338 00:24:27.461762 Set Vref, RX VrefLevel [Byte0]: 44
3339 00:24:27.461812 [Byte1]: 44
3340 00:24:27.461862
3341 00:24:27.461912 Set Vref, RX VrefLevel [Byte0]: 45
3342 00:24:27.461962 [Byte1]: 45
3343 00:24:27.462012
3344 00:24:27.462062 Set Vref, RX VrefLevel [Byte0]: 46
3345 00:24:27.462112 [Byte1]: 46
3346 00:24:27.462162
3347 00:24:27.462212 Set Vref, RX VrefLevel [Byte0]: 47
3348 00:24:27.462262 [Byte1]: 47
3349 00:24:27.462312
3350 00:24:27.462362 Set Vref, RX VrefLevel [Byte0]: 48
3351 00:24:27.462412 [Byte1]: 48
3352 00:24:27.462462
3353 00:24:27.462511 Set Vref, RX VrefLevel [Byte0]: 49
3354 00:24:27.462561 [Byte1]: 49
3355 00:24:27.462611
3356 00:24:27.462661 Set Vref, RX VrefLevel [Byte0]: 50
3357 00:24:27.462711 [Byte1]: 50
3358 00:24:27.462761
3359 00:24:27.462811 Set Vref, RX VrefLevel [Byte0]: 51
3360 00:24:27.462860 [Byte1]: 51
3361 00:24:27.462910
3362 00:24:27.462960 Set Vref, RX VrefLevel [Byte0]: 52
3363 00:24:27.463010 [Byte1]: 52
3364 00:24:27.463060
3365 00:24:27.463110 Set Vref, RX VrefLevel [Byte0]: 53
3366 00:24:27.463160 [Byte1]: 53
3367 00:24:27.463210
3368 00:24:27.463260 Set Vref, RX VrefLevel [Byte0]: 54
3369 00:24:27.463310 [Byte1]: 54
3370 00:24:27.463360
3371 00:24:27.463409 Set Vref, RX VrefLevel [Byte0]: 55
3372 00:24:27.463459 [Byte1]: 55
3373 00:24:27.463510
3374 00:24:27.463560 Set Vref, RX VrefLevel [Byte0]: 56
3375 00:24:27.463610 [Byte1]: 56
3376 00:24:27.463660
3377 00:24:27.463709 Set Vref, RX VrefLevel [Byte0]: 57
3378 00:24:27.463759 [Byte1]: 57
3379 00:24:27.463809
3380 00:24:27.463859 Set Vref, RX VrefLevel [Byte0]: 58
3381 00:24:27.463908 [Byte1]: 58
3382 00:24:27.463958
3383 00:24:27.464008 Set Vref, RX VrefLevel [Byte0]: 59
3384 00:24:27.464057 [Byte1]: 59
3385 00:24:27.464107
3386 00:24:27.464157 Set Vref, RX VrefLevel [Byte0]: 60
3387 00:24:27.464207 [Byte1]: 60
3388 00:24:27.464257
3389 00:24:27.464308 Set Vref, RX VrefLevel [Byte0]: 61
3390 00:24:27.464357 [Byte1]: 61
3391 00:24:27.464407
3392 00:24:27.464456 Set Vref, RX VrefLevel [Byte0]: 62
3393 00:24:27.464506 [Byte1]: 62
3394 00:24:27.464556
3395 00:24:27.464606 Set Vref, RX VrefLevel [Byte0]: 63
3396 00:24:27.464656 [Byte1]: 63
3397 00:24:27.464707
3398 00:24:27.464756 Set Vref, RX VrefLevel [Byte0]: 64
3399 00:24:27.464807 [Byte1]: 64
3400 00:24:27.464857
3401 00:24:27.464906 Set Vref, RX VrefLevel [Byte0]: 65
3402 00:24:27.464956 [Byte1]: 65
3403 00:24:27.465006
3404 00:24:27.465057 Set Vref, RX VrefLevel [Byte0]: 66
3405 00:24:27.465107 [Byte1]: 66
3406 00:24:27.465157
3407 00:24:27.465207 Set Vref, RX VrefLevel [Byte0]: 67
3408 00:24:27.465260 [Byte1]: 67
3409 00:24:27.465350
3410 00:24:27.465399 Final RX Vref Byte 0 = 49 to rank0
3411 00:24:27.465451 Final RX Vref Byte 1 = 52 to rank0
3412 00:24:27.465501 Final RX Vref Byte 0 = 49 to rank1
3413 00:24:27.465551 Final RX Vref Byte 1 = 52 to rank1==
3414 00:24:27.465601 Dram Type= 6, Freq= 0, CH_1, rank 0
3415 00:24:27.465653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3416 00:24:27.465704 ==
3417 00:24:27.465755 DQS Delay:
3418 00:24:27.465805 DQS0 = 0, DQS1 = 0
3419 00:24:27.465855 DQM Delay:
3420 00:24:27.465905 DQM0 = 117, DQM1 = 115
3421 00:24:27.465956 DQ Delay:
3422 00:24:27.466006 DQ0 =122, DQ1 =114, DQ2 =106, DQ3 =118
3423 00:24:27.466057 DQ4 =112, DQ5 =124, DQ6 =128, DQ7 =112
3424 00:24:27.466107 DQ8 =100, DQ9 =104, DQ10 =116, DQ11 =110
3425 00:24:27.466158 DQ12 =124, DQ13 =122, DQ14 =122, DQ15 =124
3426 00:24:27.466208
3427 00:24:27.466258
3428 00:24:27.466308 [DQSOSCAuto] RK0, (LSB)MR18= 0xf300, (MSB)MR19= 0x304, tDQSOscB0 = 410 ps tDQSOscB1 = 415 ps
3429 00:24:27.466360 CH1 RK0: MR19=304, MR18=F300
3430 00:24:27.466410 CH1_RK0: MR19=0x304, MR18=0xF300, DQSOSC=410, MR23=63, INC=39, DEC=26
3431 00:24:27.466461
3432 00:24:27.466511 ----->DramcWriteLeveling(PI) begin...
3433 00:24:27.466562 ==
3434 00:24:27.466612 Dram Type= 6, Freq= 0, CH_1, rank 1
3435 00:24:27.466662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3436 00:24:27.466712 ==
3437 00:24:27.466763 Write leveling (Byte 0): 24 => 24
3438 00:24:27.467007 Write leveling (Byte 1): 28 => 28
3439 00:24:27.467064 DramcWriteLeveling(PI) end<-----
3440 00:24:27.467116
3441 00:24:27.467167 ==
3442 00:24:27.467217 Dram Type= 6, Freq= 0, CH_1, rank 1
3443 00:24:27.467268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3444 00:24:27.467318 ==
3445 00:24:27.467369 [Gating] SW mode calibration
3446 00:24:27.467419 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3447 00:24:27.467470 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3448 00:24:27.467521 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3449 00:24:27.467572 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3450 00:24:27.467623 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3451 00:24:27.467673 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3452 00:24:27.467723 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3453 00:24:27.467774 0 15 20 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
3454 00:24:27.467825 0 15 24 | B1->B0 | 3434 2727 | 1 0 | (1 1) (0 1)
3455 00:24:27.467876 0 15 28 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
3456 00:24:27.467927 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3457 00:24:27.467977 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3458 00:24:27.468027 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3459 00:24:27.468078 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3460 00:24:27.468129 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3461 00:24:27.468179 1 0 20 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
3462 00:24:27.468230 1 0 24 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
3463 00:24:27.468280 1 0 28 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
3464 00:24:27.468330 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3465 00:24:27.468380 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3466 00:24:27.468448 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3467 00:24:27.468501 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3468 00:24:27.468552 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3469 00:24:27.468603 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3470 00:24:27.468654 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3471 00:24:27.468705 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3472 00:24:27.468756 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 00:24:27.468806 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 00:24:27.468857 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 00:24:27.468908 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 00:24:27.468958 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 00:24:27.469008 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 00:24:27.469059 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 00:24:27.469110 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 00:24:27.469161 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 00:24:27.469211 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 00:24:27.469269 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 00:24:27.469354 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 00:24:27.469405 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 00:24:27.469456 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3486 00:24:27.469506 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3487 00:24:27.469558 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3488 00:24:27.469609 Total UI for P1: 0, mck2ui 16
3489 00:24:27.469661 best dqsien dly found for B0: ( 1, 3, 22)
3490 00:24:27.469711 Total UI for P1: 0, mck2ui 16
3491 00:24:27.469762 best dqsien dly found for B1: ( 1, 3, 24)
3492 00:24:27.469813 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3493 00:24:27.469864 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3494 00:24:27.469915
3495 00:24:27.469965 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3496 00:24:27.470016 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3497 00:24:27.470066 [Gating] SW calibration Done
3498 00:24:27.470117 ==
3499 00:24:27.470167 Dram Type= 6, Freq= 0, CH_1, rank 1
3500 00:24:27.470218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3501 00:24:27.470269 ==
3502 00:24:27.470319 RX Vref Scan: 0
3503 00:24:27.470369
3504 00:24:27.470427 RX Vref 0 -> 0, step: 1
3505 00:24:27.470515
3506 00:24:27.470573 RX Delay -40 -> 252, step: 8
3507 00:24:27.470625 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3508 00:24:27.470676 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3509 00:24:27.470728 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3510 00:24:27.470778 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3511 00:24:27.470829 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3512 00:24:27.470880 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3513 00:24:27.470931 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3514 00:24:27.470981 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3515 00:24:27.471032 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3516 00:24:27.471082 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3517 00:24:27.471132 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3518 00:24:27.471183 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3519 00:24:27.471234 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3520 00:24:27.471285 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3521 00:24:27.471336 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3522 00:24:27.471387 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3523 00:24:27.471437 ==
3524 00:24:27.471488 Dram Type= 6, Freq= 0, CH_1, rank 1
3525 00:24:27.471540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3526 00:24:27.471591 ==
3527 00:24:27.471641 DQS Delay:
3528 00:24:27.471692 DQS0 = 0, DQS1 = 0
3529 00:24:27.471742 DQM Delay:
3530 00:24:27.471792 DQM0 = 116, DQM1 = 114
3531 00:24:27.471842 DQ Delay:
3532 00:24:27.471892 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3533 00:24:27.471942 DQ4 =119, DQ5 =127, DQ6 =123, DQ7 =111
3534 00:24:27.471993 DQ8 =103, DQ9 =99, DQ10 =115, DQ11 =107
3535 00:24:27.472043 DQ12 =127, DQ13 =123, DQ14 =115, DQ15 =123
3536 00:24:27.472093
3537 00:24:27.472143
3538 00:24:27.472193 ==
3539 00:24:27.472243 Dram Type= 6, Freq= 0, CH_1, rank 1
3540 00:24:27.472294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3541 00:24:27.472345 ==
3542 00:24:27.472395
3543 00:24:27.472445
3544 00:24:27.472494 TX Vref Scan disable
3545 00:24:27.472737 == TX Byte 0 ==
3546 00:24:27.472795 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3547 00:24:27.472847 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3548 00:24:27.472898 == TX Byte 1 ==
3549 00:24:27.472949 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3550 00:24:27.473000 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3551 00:24:27.473051 ==
3552 00:24:27.473102 Dram Type= 6, Freq= 0, CH_1, rank 1
3553 00:24:27.473152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3554 00:24:27.473204 ==
3555 00:24:27.473255 TX Vref=22, minBit 1, minWin=25, winSum=416
3556 00:24:27.473315 TX Vref=24, minBit 7, minWin=25, winSum=421
3557 00:24:27.473366 TX Vref=26, minBit 1, minWin=26, winSum=421
3558 00:24:27.473417 TX Vref=28, minBit 2, minWin=26, winSum=429
3559 00:24:27.473468 TX Vref=30, minBit 7, minWin=26, winSum=431
3560 00:24:27.473519 TX Vref=32, minBit 2, minWin=26, winSum=429
3561 00:24:27.473570 [TxChooseVref] Worse bit 7, Min win 26, Win sum 431, Final Vref 30
3562 00:24:27.473621
3563 00:24:27.473671 Final TX Range 1 Vref 30
3564 00:24:27.473722
3565 00:24:27.473772 ==
3566 00:24:27.473822 Dram Type= 6, Freq= 0, CH_1, rank 1
3567 00:24:27.473873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3568 00:24:27.473925 ==
3569 00:24:27.473975
3570 00:24:27.474025
3571 00:24:27.474074 TX Vref Scan disable
3572 00:24:27.474124 == TX Byte 0 ==
3573 00:24:27.474175 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3574 00:24:27.474226 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3575 00:24:27.474277 == TX Byte 1 ==
3576 00:24:27.474327 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3577 00:24:27.474378 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3578 00:24:27.474428
3579 00:24:27.474487 [DATLAT]
3580 00:24:27.474540 Freq=1200, CH1 RK1
3581 00:24:27.474591
3582 00:24:27.474641 DATLAT Default: 0xd
3583 00:24:27.474691 0, 0xFFFF, sum = 0
3584 00:24:27.474743 1, 0xFFFF, sum = 0
3585 00:24:27.474794 2, 0xFFFF, sum = 0
3586 00:24:27.474845 3, 0xFFFF, sum = 0
3587 00:24:27.474896 4, 0xFFFF, sum = 0
3588 00:24:27.474948 5, 0xFFFF, sum = 0
3589 00:24:27.474998 6, 0xFFFF, sum = 0
3590 00:24:27.475049 7, 0xFFFF, sum = 0
3591 00:24:27.475101 8, 0xFFFF, sum = 0
3592 00:24:27.475152 9, 0xFFFF, sum = 0
3593 00:24:27.475204 10, 0xFFFF, sum = 0
3594 00:24:27.475255 11, 0xFFFF, sum = 0
3595 00:24:27.475307 12, 0x0, sum = 1
3596 00:24:27.475358 13, 0x0, sum = 2
3597 00:24:27.475410 14, 0x0, sum = 3
3598 00:24:27.475461 15, 0x0, sum = 4
3599 00:24:27.475512 best_step = 13
3600 00:24:27.475562
3601 00:24:27.475612 ==
3602 00:24:27.475662 Dram Type= 6, Freq= 0, CH_1, rank 1
3603 00:24:27.475712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3604 00:24:27.475763 ==
3605 00:24:27.475814 RX Vref Scan: 0
3606 00:24:27.475865
3607 00:24:27.475915 RX Vref 0 -> 0, step: 1
3608 00:24:27.475965
3609 00:24:27.476015 RX Delay -13 -> 252, step: 4
3610 00:24:27.476066 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3611 00:24:27.476117 iDelay=195, Bit 1, Center 112 (47 ~ 178) 132
3612 00:24:27.476168 iDelay=195, Bit 2, Center 108 (43 ~ 174) 132
3613 00:24:27.476219 iDelay=195, Bit 3, Center 116 (51 ~ 182) 132
3614 00:24:27.476270 iDelay=195, Bit 4, Center 116 (51 ~ 182) 132
3615 00:24:27.476321 iDelay=195, Bit 5, Center 124 (55 ~ 194) 140
3616 00:24:27.476372 iDelay=195, Bit 6, Center 124 (59 ~ 190) 132
3617 00:24:27.476422 iDelay=195, Bit 7, Center 112 (47 ~ 178) 132
3618 00:24:27.476473 iDelay=195, Bit 8, Center 102 (43 ~ 162) 120
3619 00:24:27.476523 iDelay=195, Bit 9, Center 104 (43 ~ 166) 124
3620 00:24:27.476574 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3621 00:24:27.476625 iDelay=195, Bit 11, Center 108 (47 ~ 170) 124
3622 00:24:27.476676 iDelay=195, Bit 12, Center 122 (63 ~ 182) 120
3623 00:24:27.476726 iDelay=195, Bit 13, Center 120 (59 ~ 182) 124
3624 00:24:27.476777 iDelay=195, Bit 14, Center 118 (59 ~ 178) 120
3625 00:24:27.476827 iDelay=195, Bit 15, Center 124 (63 ~ 186) 124
3626 00:24:27.476877 ==
3627 00:24:27.476928 Dram Type= 6, Freq= 0, CH_1, rank 1
3628 00:24:27.476978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3629 00:24:27.477028 ==
3630 00:24:27.477079 DQS Delay:
3631 00:24:27.477129 DQS0 = 0, DQS1 = 0
3632 00:24:27.477179 DQM Delay:
3633 00:24:27.477229 DQM0 = 116, DQM1 = 114
3634 00:24:27.477321 DQ Delay:
3635 00:24:27.477401 DQ0 =118, DQ1 =112, DQ2 =108, DQ3 =116
3636 00:24:27.477452 DQ4 =116, DQ5 =124, DQ6 =124, DQ7 =112
3637 00:24:27.477502 DQ8 =102, DQ9 =104, DQ10 =116, DQ11 =108
3638 00:24:27.477553 DQ12 =122, DQ13 =120, DQ14 =118, DQ15 =124
3639 00:24:27.477603
3640 00:24:27.477653
3641 00:24:27.477703 [DQSOSCAuto] RK1, (LSB)MR18= 0xf709, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
3642 00:24:27.477755 CH1 RK1: MR19=304, MR18=F709
3643 00:24:27.477805 CH1_RK1: MR19=0x304, MR18=0xF709, DQSOSC=406, MR23=63, INC=39, DEC=26
3644 00:24:27.477856 [RxdqsGatingPostProcess] freq 1200
3645 00:24:27.477906 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3646 00:24:27.477957 best DQS0 dly(2T, 0.5T) = (0, 11)
3647 00:24:27.478007 best DQS1 dly(2T, 0.5T) = (0, 11)
3648 00:24:27.478059 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3649 00:24:27.478109 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3650 00:24:27.478159 best DQS0 dly(2T, 0.5T) = (0, 11)
3651 00:24:27.478210 best DQS1 dly(2T, 0.5T) = (0, 11)
3652 00:24:27.478260 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3653 00:24:27.478310 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3654 00:24:27.478360 Pre-setting of DQS Precalculation
3655 00:24:27.478411 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3656 00:24:27.478462 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3657 00:24:27.478514 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3658 00:24:27.478565
3659 00:24:27.478615
3660 00:24:27.478665 [Calibration Summary] 2400 Mbps
3661 00:24:27.478715 CH 0, Rank 0
3662 00:24:27.478765 SW Impedance : PASS
3663 00:24:27.478815 DUTY Scan : NO K
3664 00:24:27.478866 ZQ Calibration : PASS
3665 00:24:27.478917 Jitter Meter : NO K
3666 00:24:27.478968 CBT Training : PASS
3667 00:24:27.479018 Write leveling : PASS
3668 00:24:27.479068 RX DQS gating : PASS
3669 00:24:27.479118 RX DQ/DQS(RDDQC) : PASS
3670 00:24:27.479169 TX DQ/DQS : PASS
3671 00:24:27.479219 RX DATLAT : PASS
3672 00:24:27.479270 RX DQ/DQS(Engine): PASS
3673 00:24:27.479320 TX OE : NO K
3674 00:24:27.479371 All Pass.
3675 00:24:27.479422
3676 00:24:27.479472 CH 0, Rank 1
3677 00:24:27.479522 SW Impedance : PASS
3678 00:24:27.479572 DUTY Scan : NO K
3679 00:24:27.479623 ZQ Calibration : PASS
3680 00:24:27.479673 Jitter Meter : NO K
3681 00:24:27.479723 CBT Training : PASS
3682 00:24:27.479773 Write leveling : PASS
3683 00:24:27.479823 RX DQS gating : PASS
3684 00:24:27.480067 RX DQ/DQS(RDDQC) : PASS
3685 00:24:27.480127 TX DQ/DQS : PASS
3686 00:24:27.480178 RX DATLAT : PASS
3687 00:24:27.480229 RX DQ/DQS(Engine): PASS
3688 00:24:27.480280 TX OE : NO K
3689 00:24:27.480332 All Pass.
3690 00:24:27.480383
3691 00:24:27.480433 CH 1, Rank 0
3692 00:24:27.480483 SW Impedance : PASS
3693 00:24:27.480534 DUTY Scan : NO K
3694 00:24:27.480585 ZQ Calibration : PASS
3695 00:24:27.480635 Jitter Meter : NO K
3696 00:24:27.480686 CBT Training : PASS
3697 00:24:27.480736 Write leveling : PASS
3698 00:24:27.480786 RX DQS gating : PASS
3699 00:24:27.480837 RX DQ/DQS(RDDQC) : PASS
3700 00:24:27.480887 TX DQ/DQS : PASS
3701 00:24:27.480938 RX DATLAT : PASS
3702 00:24:27.480988 RX DQ/DQS(Engine): PASS
3703 00:24:27.481038 TX OE : NO K
3704 00:24:27.481089 All Pass.
3705 00:24:27.481139
3706 00:24:27.481189 CH 1, Rank 1
3707 00:24:27.481239 SW Impedance : PASS
3708 00:24:27.481335 DUTY Scan : NO K
3709 00:24:27.481386 ZQ Calibration : PASS
3710 00:24:27.481436 Jitter Meter : NO K
3711 00:24:27.481487 CBT Training : PASS
3712 00:24:27.481538 Write leveling : PASS
3713 00:24:27.481588 RX DQS gating : PASS
3714 00:24:27.481638 RX DQ/DQS(RDDQC) : PASS
3715 00:24:27.481688 TX DQ/DQS : PASS
3716 00:24:27.481739 RX DATLAT : PASS
3717 00:24:27.481789 RX DQ/DQS(Engine): PASS
3718 00:24:27.481839 TX OE : NO K
3719 00:24:27.481889 All Pass.
3720 00:24:27.481940
3721 00:24:27.481990 DramC Write-DBI off
3722 00:24:27.482041 PER_BANK_REFRESH: Hybrid Mode
3723 00:24:27.482091 TX_TRACKING: ON
3724 00:24:27.482142 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3725 00:24:27.482193 [FAST_K] Save calibration result to emmc
3726 00:24:27.482244 dramc_set_vcore_voltage set vcore to 650000
3727 00:24:27.482295 Read voltage for 600, 5
3728 00:24:27.482345 Vio18 = 0
3729 00:24:27.482395 Vcore = 650000
3730 00:24:27.482445 Vdram = 0
3731 00:24:27.482496 Vddq = 0
3732 00:24:27.482547 Vmddr = 0
3733 00:24:27.482597 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3734 00:24:27.482648 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3735 00:24:27.482699 MEM_TYPE=3, freq_sel=19
3736 00:24:27.482749 sv_algorithm_assistance_LP4_1600
3737 00:24:27.482799 ============ PULL DRAM RESETB DOWN ============
3738 00:24:27.482850 ========== PULL DRAM RESETB DOWN end =========
3739 00:24:27.482902 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3740 00:24:27.482953 ===================================
3741 00:24:27.483003 LPDDR4 DRAM CONFIGURATION
3742 00:24:27.483053 ===================================
3743 00:24:27.483103 EX_ROW_EN[0] = 0x0
3744 00:24:27.483154 EX_ROW_EN[1] = 0x0
3745 00:24:27.483204 LP4Y_EN = 0x0
3746 00:24:27.483254 WORK_FSP = 0x0
3747 00:24:27.483304 WL = 0x2
3748 00:24:27.483355 RL = 0x2
3749 00:24:27.483404 BL = 0x2
3750 00:24:27.483455 RPST = 0x0
3751 00:24:27.483505 RD_PRE = 0x0
3752 00:24:27.483555 WR_PRE = 0x1
3753 00:24:27.483606 WR_PST = 0x0
3754 00:24:27.483656 DBI_WR = 0x0
3755 00:24:27.483706 DBI_RD = 0x0
3756 00:24:27.483756 OTF = 0x1
3757 00:24:27.483807 ===================================
3758 00:24:27.483856 ===================================
3759 00:24:27.483907 ANA top config
3760 00:24:27.483957 ===================================
3761 00:24:27.484007 DLL_ASYNC_EN = 0
3762 00:24:27.484057 ALL_SLAVE_EN = 1
3763 00:24:27.484107 NEW_RANK_MODE = 1
3764 00:24:27.484158 DLL_IDLE_MODE = 1
3765 00:24:27.484208 LP45_APHY_COMB_EN = 1
3766 00:24:27.484258 TX_ODT_DIS = 1
3767 00:24:27.484308 NEW_8X_MODE = 1
3768 00:24:27.484359 ===================================
3769 00:24:27.484410 ===================================
3770 00:24:27.484460 data_rate = 1200
3771 00:24:27.484510 CKR = 1
3772 00:24:27.484561 DQ_P2S_RATIO = 8
3773 00:24:27.484612 ===================================
3774 00:24:27.484663 CA_P2S_RATIO = 8
3775 00:24:27.484713 DQ_CA_OPEN = 0
3776 00:24:27.484764 DQ_SEMI_OPEN = 0
3777 00:24:27.484814 CA_SEMI_OPEN = 0
3778 00:24:27.484864 CA_FULL_RATE = 0
3779 00:24:27.484914 DQ_CKDIV4_EN = 1
3780 00:24:27.484964 CA_CKDIV4_EN = 1
3781 00:24:27.485014 CA_PREDIV_EN = 0
3782 00:24:27.485064 PH8_DLY = 0
3783 00:24:27.485115 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3784 00:24:27.485165 DQ_AAMCK_DIV = 4
3785 00:24:27.485216 CA_AAMCK_DIV = 4
3786 00:24:27.485269 CA_ADMCK_DIV = 4
3787 00:24:27.485358 DQ_TRACK_CA_EN = 0
3788 00:24:27.485408 CA_PICK = 600
3789 00:24:27.485458 CA_MCKIO = 600
3790 00:24:27.485508 MCKIO_SEMI = 0
3791 00:24:27.485559 PLL_FREQ = 2288
3792 00:24:27.485609 DQ_UI_PI_RATIO = 32
3793 00:24:27.485659 CA_UI_PI_RATIO = 0
3794 00:24:27.485709 ===================================
3795 00:24:27.485760 ===================================
3796 00:24:27.485810 memory_type:LPDDR4
3797 00:24:27.485860 GP_NUM : 10
3798 00:24:27.485910 SRAM_EN : 1
3799 00:24:27.485960 MD32_EN : 0
3800 00:24:27.486011 ===================================
3801 00:24:27.486061 [ANA_INIT] >>>>>>>>>>>>>>
3802 00:24:27.486112 <<<<<< [CONFIGURE PHASE]: ANA_TX
3803 00:24:27.486163 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3804 00:24:27.486213 ===================================
3805 00:24:27.486264 data_rate = 1200,PCW = 0X5800
3806 00:24:27.486315 ===================================
3807 00:24:27.486366 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3808 00:24:27.486416 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3809 00:24:27.486468 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3810 00:24:27.486519 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3811 00:24:27.486570 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3812 00:24:27.486621 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3813 00:24:27.486672 [ANA_INIT] flow start
3814 00:24:27.486722 [ANA_INIT] PLL >>>>>>>>
3815 00:24:27.486773 [ANA_INIT] PLL <<<<<<<<
3816 00:24:27.486823 [ANA_INIT] MIDPI >>>>>>>>
3817 00:24:27.486874 [ANA_INIT] MIDPI <<<<<<<<
3818 00:24:27.486924 [ANA_INIT] DLL >>>>>>>>
3819 00:24:27.486974 [ANA_INIT] flow end
3820 00:24:27.487025 ============ LP4 DIFF to SE enter ============
3821 00:24:27.487075 ============ LP4 DIFF to SE exit ============
3822 00:24:27.487126 [ANA_INIT] <<<<<<<<<<<<<
3823 00:24:27.487366 [Flow] Enable top DCM control >>>>>
3824 00:24:27.487424 [Flow] Enable top DCM control <<<<<
3825 00:24:27.487477 Enable DLL master slave shuffle
3826 00:24:27.487528 ==============================================================
3827 00:24:27.487579 Gating Mode config
3828 00:24:27.487630 ==============================================================
3829 00:24:27.487681 Config description:
3830 00:24:27.487731 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3831 00:24:27.487783 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3832 00:24:27.487833 SELPH_MODE 0: By rank 1: By Phase
3833 00:24:27.487884 ==============================================================
3834 00:24:27.487935 GAT_TRACK_EN = 1
3835 00:24:27.487986 RX_GATING_MODE = 2
3836 00:24:27.488036 RX_GATING_TRACK_MODE = 2
3837 00:24:27.488086 SELPH_MODE = 1
3838 00:24:27.488136 PICG_EARLY_EN = 1
3839 00:24:27.488187 VALID_LAT_VALUE = 1
3840 00:24:27.488237 ==============================================================
3841 00:24:27.488288 Enter into Gating configuration >>>>
3842 00:24:27.488338 Exit from Gating configuration <<<<
3843 00:24:27.488388 Enter into DVFS_PRE_config >>>>>
3844 00:24:27.488439 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3845 00:24:27.488492 Exit from DVFS_PRE_config <<<<<
3846 00:24:27.488542 Enter into PICG configuration >>>>
3847 00:24:27.488593 Exit from PICG configuration <<<<
3848 00:24:27.488644 [RX_INPUT] configuration >>>>>
3849 00:24:27.488694 [RX_INPUT] configuration <<<<<
3850 00:24:27.488745 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3851 00:24:27.488796 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3852 00:24:27.488847 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3853 00:24:27.488897 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3854 00:24:27.488948 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3855 00:24:27.488999 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3856 00:24:27.489049 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3857 00:24:27.489111 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3858 00:24:27.491468 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3859 00:24:27.498148 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3860 00:24:27.501982 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3861 00:24:27.504869 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3862 00:24:27.507797 ===================================
3863 00:24:27.511078 LPDDR4 DRAM CONFIGURATION
3864 00:24:27.514580 ===================================
3865 00:24:27.517692 EX_ROW_EN[0] = 0x0
3866 00:24:27.517771 EX_ROW_EN[1] = 0x0
3867 00:24:27.521041 LP4Y_EN = 0x0
3868 00:24:27.521119 WORK_FSP = 0x0
3869 00:24:27.524259 WL = 0x2
3870 00:24:27.524339 RL = 0x2
3871 00:24:27.527699 BL = 0x2
3872 00:24:27.527778 RPST = 0x0
3873 00:24:27.531459 RD_PRE = 0x0
3874 00:24:27.531539 WR_PRE = 0x1
3875 00:24:27.534496 WR_PST = 0x0
3876 00:24:27.534594 DBI_WR = 0x0
3877 00:24:27.538142 DBI_RD = 0x0
3878 00:24:27.538223 OTF = 0x1
3879 00:24:27.540814 ===================================
3880 00:24:27.547535 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3881 00:24:27.550698 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3882 00:24:27.554087 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3883 00:24:27.557215 ===================================
3884 00:24:27.560492 LPDDR4 DRAM CONFIGURATION
3885 00:24:27.563869 ===================================
3886 00:24:27.567564 EX_ROW_EN[0] = 0x10
3887 00:24:27.567644 EX_ROW_EN[1] = 0x0
3888 00:24:27.570524 LP4Y_EN = 0x0
3889 00:24:27.570606 WORK_FSP = 0x0
3890 00:24:27.573897 WL = 0x2
3891 00:24:27.573976 RL = 0x2
3892 00:24:27.577471 BL = 0x2
3893 00:24:27.577551 RPST = 0x0
3894 00:24:27.580286 RD_PRE = 0x0
3895 00:24:27.580366 WR_PRE = 0x1
3896 00:24:27.584148 WR_PST = 0x0
3897 00:24:27.584228 DBI_WR = 0x0
3898 00:24:27.586931 DBI_RD = 0x0
3899 00:24:27.587011 OTF = 0x1
3900 00:24:27.590606 ===================================
3901 00:24:27.597017 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3902 00:24:27.602031 nWR fixed to 30
3903 00:24:27.605054 [ModeRegInit_LP4] CH0 RK0
3904 00:24:27.605134 [ModeRegInit_LP4] CH0 RK1
3905 00:24:27.608749 [ModeRegInit_LP4] CH1 RK0
3906 00:24:27.611870 [ModeRegInit_LP4] CH1 RK1
3907 00:24:27.611951 match AC timing 17
3908 00:24:27.618031 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3909 00:24:27.621836 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3910 00:24:27.624629 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3911 00:24:27.631687 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3912 00:24:27.634763 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3913 00:24:27.634846 ==
3914 00:24:27.638038 Dram Type= 6, Freq= 0, CH_0, rank 0
3915 00:24:27.641385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3916 00:24:27.641469 ==
3917 00:24:27.648489 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3918 00:24:27.654368 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3919 00:24:27.657625 [CA 0] Center 36 (6~67) winsize 62
3920 00:24:27.660935 [CA 1] Center 36 (6~67) winsize 62
3921 00:24:27.664054 [CA 2] Center 34 (4~65) winsize 62
3922 00:24:27.667452 [CA 3] Center 34 (4~65) winsize 62
3923 00:24:27.670481 [CA 4] Center 33 (3~64) winsize 62
3924 00:24:27.673686 [CA 5] Center 33 (3~64) winsize 62
3925 00:24:27.673768
3926 00:24:27.677439 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3927 00:24:27.677520
3928 00:24:27.680724 [CATrainingPosCal] consider 1 rank data
3929 00:24:27.684109 u2DelayCellTimex100 = 270/100 ps
3930 00:24:27.687912 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3931 00:24:27.690500 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3932 00:24:27.696821 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3933 00:24:27.700522 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3934 00:24:27.703427 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3935 00:24:27.707159 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3936 00:24:27.707240
3937 00:24:27.710038 CA PerBit enable=1, Macro0, CA PI delay=33
3938 00:24:27.710119
3939 00:24:27.713665 [CBTSetCACLKResult] CA Dly = 33
3940 00:24:27.713745 CS Dly: 5 (0~36)
3941 00:24:27.716743 ==
3942 00:24:27.716851 Dram Type= 6, Freq= 0, CH_0, rank 1
3943 00:24:27.723633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3944 00:24:27.723723 ==
3945 00:24:27.726664 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3946 00:24:27.733417 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3947 00:24:27.737130 [CA 0] Center 36 (6~67) winsize 62
3948 00:24:27.740216 [CA 1] Center 36 (6~67) winsize 62
3949 00:24:27.743898 [CA 2] Center 34 (4~65) winsize 62
3950 00:24:27.746895 [CA 3] Center 34 (4~65) winsize 62
3951 00:24:27.750553 [CA 4] Center 34 (3~65) winsize 63
3952 00:24:27.753739 [CA 5] Center 33 (3~64) winsize 62
3953 00:24:27.753820
3954 00:24:27.757183 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3955 00:24:27.757300
3956 00:24:27.760092 [CATrainingPosCal] consider 2 rank data
3957 00:24:27.763400 u2DelayCellTimex100 = 270/100 ps
3958 00:24:27.766865 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3959 00:24:27.773456 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3960 00:24:27.776354 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3961 00:24:27.779630 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3962 00:24:27.783237 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3963 00:24:27.786385 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3964 00:24:27.786466
3965 00:24:27.789765 CA PerBit enable=1, Macro0, CA PI delay=33
3966 00:24:27.789846
3967 00:24:27.793028 [CBTSetCACLKResult] CA Dly = 33
3968 00:24:27.796312 CS Dly: 6 (0~38)
3969 00:24:27.796416
3970 00:24:27.799621 ----->DramcWriteLeveling(PI) begin...
3971 00:24:27.799704 ==
3972 00:24:27.803279 Dram Type= 6, Freq= 0, CH_0, rank 0
3973 00:24:27.806418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3974 00:24:27.806502 ==
3975 00:24:27.809980 Write leveling (Byte 0): 32 => 32
3976 00:24:27.812958 Write leveling (Byte 1): 29 => 29
3977 00:24:27.816005 DramcWriteLeveling(PI) end<-----
3978 00:24:27.816088
3979 00:24:27.816152 ==
3980 00:24:27.820108 Dram Type= 6, Freq= 0, CH_0, rank 0
3981 00:24:27.822548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3982 00:24:27.822633 ==
3983 00:24:27.826342 [Gating] SW mode calibration
3984 00:24:27.832678 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3985 00:24:27.839049 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3986 00:24:27.842763 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3987 00:24:27.848946 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3988 00:24:27.851948 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3989 00:24:27.855746 0 9 12 | B1->B0 | 3333 3232 | 0 0 | (0 0) (0 0)
3990 00:24:27.861986 0 9 16 | B1->B0 | 2d2d 2424 | 1 0 | (1 0) (0 0)
3991 00:24:27.865602 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3992 00:24:27.869522 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3993 00:24:27.875235 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3994 00:24:27.878504 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3995 00:24:27.881763 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3996 00:24:27.888785 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3997 00:24:27.891701 0 10 12 | B1->B0 | 2727 2c2c | 0 0 | (0 0) (0 0)
3998 00:24:27.895105 0 10 16 | B1->B0 | 3737 3e3e | 1 0 | (0 0) (0 0)
3999 00:24:27.901621 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4000 00:24:27.904739 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4001 00:24:27.908099 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4002 00:24:27.915002 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4003 00:24:27.917743 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4004 00:24:27.921250 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4005 00:24:27.927858 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4006 00:24:27.931030 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4007 00:24:27.935090 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 00:24:27.940835 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 00:24:27.944213 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 00:24:27.947750 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 00:24:27.954285 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 00:24:27.957823 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 00:24:27.960535 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 00:24:27.967653 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 00:24:27.970533 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 00:24:27.973842 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 00:24:27.980161 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 00:24:27.983505 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 00:24:27.987215 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 00:24:27.993622 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 00:24:27.996701 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4022 00:24:28.000446 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4023 00:24:28.003783 Total UI for P1: 0, mck2ui 16
4024 00:24:28.006685 best dqsien dly found for B0: ( 0, 13, 12)
4025 00:24:28.013793 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4026 00:24:28.013875 Total UI for P1: 0, mck2ui 16
4027 00:24:28.019869 best dqsien dly found for B1: ( 0, 13, 16)
4028 00:24:28.023357 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4029 00:24:28.026944 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4030 00:24:28.027026
4031 00:24:28.030147 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4032 00:24:28.033738 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4033 00:24:28.036473 [Gating] SW calibration Done
4034 00:24:28.036555 ==
4035 00:24:28.039727 Dram Type= 6, Freq= 0, CH_0, rank 0
4036 00:24:28.043825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4037 00:24:28.043909 ==
4038 00:24:28.046569 RX Vref Scan: 0
4039 00:24:28.046650
4040 00:24:28.046715 RX Vref 0 -> 0, step: 1
4041 00:24:28.046774
4042 00:24:28.050044 RX Delay -230 -> 252, step: 16
4043 00:24:28.056456 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4044 00:24:28.059851 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4045 00:24:28.063200 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4046 00:24:28.066622 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4047 00:24:28.069804 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4048 00:24:28.076427 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4049 00:24:28.079425 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4050 00:24:28.083151 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4051 00:24:28.086459 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4052 00:24:28.092794 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4053 00:24:28.096114 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4054 00:24:28.099218 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4055 00:24:28.102851 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4056 00:24:28.109643 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4057 00:24:28.112446 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4058 00:24:28.115876 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4059 00:24:28.115959 ==
4060 00:24:28.119578 Dram Type= 6, Freq= 0, CH_0, rank 0
4061 00:24:28.122394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4062 00:24:28.126681 ==
4063 00:24:28.126763 DQS Delay:
4064 00:24:28.126828 DQS0 = 0, DQS1 = 0
4065 00:24:28.129178 DQM Delay:
4066 00:24:28.129320 DQM0 = 46, DQM1 = 36
4067 00:24:28.132646 DQ Delay:
4068 00:24:28.132727 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4069 00:24:28.135799 DQ4 =41, DQ5 =41, DQ6 =65, DQ7 =57
4070 00:24:28.139017 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4071 00:24:28.142289 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4072 00:24:28.145807
4073 00:24:28.145890
4074 00:24:28.145954 ==
4075 00:24:28.148479 Dram Type= 6, Freq= 0, CH_0, rank 0
4076 00:24:28.151927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4077 00:24:28.152009 ==
4078 00:24:28.152072
4079 00:24:28.152131
4080 00:24:28.155244 TX Vref Scan disable
4081 00:24:28.155326 == TX Byte 0 ==
4082 00:24:28.161661 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4083 00:24:28.165452 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4084 00:24:28.165532 == TX Byte 1 ==
4085 00:24:28.171637 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4086 00:24:28.174887 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4087 00:24:28.174970 ==
4088 00:24:28.178390 Dram Type= 6, Freq= 0, CH_0, rank 0
4089 00:24:28.181465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4090 00:24:28.181548 ==
4091 00:24:28.185392
4092 00:24:28.185473
4093 00:24:28.185536 TX Vref Scan disable
4094 00:24:28.188790 == TX Byte 0 ==
4095 00:24:28.191631 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4096 00:24:28.198629 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4097 00:24:28.198713 == TX Byte 1 ==
4098 00:24:28.201788 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4099 00:24:28.208082 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4100 00:24:28.208164
4101 00:24:28.208228 [DATLAT]
4102 00:24:28.208288 Freq=600, CH0 RK0
4103 00:24:28.208347
4104 00:24:28.211751 DATLAT Default: 0x9
4105 00:24:28.214598 0, 0xFFFF, sum = 0
4106 00:24:28.214681 1, 0xFFFF, sum = 0
4107 00:24:28.218068 2, 0xFFFF, sum = 0
4108 00:24:28.218150 3, 0xFFFF, sum = 0
4109 00:24:28.221982 4, 0xFFFF, sum = 0
4110 00:24:28.222065 5, 0xFFFF, sum = 0
4111 00:24:28.225038 6, 0xFFFF, sum = 0
4112 00:24:28.225121 7, 0xFFFF, sum = 0
4113 00:24:28.228544 8, 0x0, sum = 1
4114 00:24:28.228627 9, 0x0, sum = 2
4115 00:24:28.231187 10, 0x0, sum = 3
4116 00:24:28.231270 11, 0x0, sum = 4
4117 00:24:28.231335 best_step = 9
4118 00:24:28.231395
4119 00:24:28.234699 ==
4120 00:24:28.234781 Dram Type= 6, Freq= 0, CH_0, rank 0
4121 00:24:28.240968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4122 00:24:28.241051 ==
4123 00:24:28.241114 RX Vref Scan: 1
4124 00:24:28.241174
4125 00:24:28.244549 RX Vref 0 -> 0, step: 1
4126 00:24:28.244630
4127 00:24:28.247885 RX Delay -179 -> 252, step: 8
4128 00:24:28.247966
4129 00:24:28.251183 Set Vref, RX VrefLevel [Byte0]: 57
4130 00:24:28.254295 [Byte1]: 50
4131 00:24:28.254376
4132 00:24:28.257589 Final RX Vref Byte 0 = 57 to rank0
4133 00:24:28.260977 Final RX Vref Byte 1 = 50 to rank0
4134 00:24:28.264048 Final RX Vref Byte 0 = 57 to rank1
4135 00:24:28.268264 Final RX Vref Byte 1 = 50 to rank1==
4136 00:24:28.270873 Dram Type= 6, Freq= 0, CH_0, rank 0
4137 00:24:28.273795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4138 00:24:28.277703 ==
4139 00:24:28.277784 DQS Delay:
4140 00:24:28.277848 DQS0 = 0, DQS1 = 0
4141 00:24:28.280404 DQM Delay:
4142 00:24:28.280485 DQM0 = 44, DQM1 = 36
4143 00:24:28.283804 DQ Delay:
4144 00:24:28.286945 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4145 00:24:28.287027 DQ4 =48, DQ5 =36, DQ6 =56, DQ7 =48
4146 00:24:28.290648 DQ8 =28, DQ9 =24, DQ10 =36, DQ11 =32
4147 00:24:28.297135 DQ12 =44, DQ13 =40, DQ14 =44, DQ15 =44
4148 00:24:28.297218
4149 00:24:28.297322
4150 00:24:28.304392 [DQSOSCAuto] RK0, (LSB)MR18= 0x5148, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 394 ps
4151 00:24:28.306832 CH0 RK0: MR19=808, MR18=5148
4152 00:24:28.314005 CH0_RK0: MR19=0x808, MR18=0x5148, DQSOSC=394, MR23=63, INC=168, DEC=112
4153 00:24:28.314087
4154 00:24:28.316874 ----->DramcWriteLeveling(PI) begin...
4155 00:24:28.316957 ==
4156 00:24:28.320259 Dram Type= 6, Freq= 0, CH_0, rank 1
4157 00:24:28.323732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4158 00:24:28.323816 ==
4159 00:24:28.326660 Write leveling (Byte 0): 32 => 32
4160 00:24:28.330461 Write leveling (Byte 1): 31 => 31
4161 00:24:28.334067 DramcWriteLeveling(PI) end<-----
4162 00:24:28.334149
4163 00:24:28.334214 ==
4164 00:24:28.337024 Dram Type= 6, Freq= 0, CH_0, rank 1
4165 00:24:28.340104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4166 00:24:28.340187 ==
4167 00:24:28.343127 [Gating] SW mode calibration
4168 00:24:28.349926 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4169 00:24:28.356930 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4170 00:24:28.360035 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4171 00:24:28.366437 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4172 00:24:28.369784 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4173 00:24:28.372986 0 9 12 | B1->B0 | 3333 3030 | 0 0 | (0 1) (1 1)
4174 00:24:28.379452 0 9 16 | B1->B0 | 3030 2727 | 0 0 | (1 1) (0 0)
4175 00:24:28.382746 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4176 00:24:28.386970 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4177 00:24:28.392738 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4178 00:24:28.396785 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4179 00:24:28.399824 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4180 00:24:28.406388 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4181 00:24:28.409251 0 10 12 | B1->B0 | 2424 3535 | 0 0 | (0 0) (1 1)
4182 00:24:28.412774 0 10 16 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
4183 00:24:28.419234 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4184 00:24:28.422861 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4185 00:24:28.425884 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4186 00:24:28.432534 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4187 00:24:28.435660 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4188 00:24:28.438815 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4189 00:24:28.445879 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4190 00:24:28.448866 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4191 00:24:28.452234 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 00:24:28.458718 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 00:24:28.462039 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 00:24:28.465292 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 00:24:28.471952 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 00:24:28.475430 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 00:24:28.479165 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 00:24:28.484948 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 00:24:28.488656 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 00:24:28.492066 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 00:24:28.498427 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 00:24:28.501423 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 00:24:28.504802 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 00:24:28.511867 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 00:24:28.514712 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4206 00:24:28.518129 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4207 00:24:28.522122 Total UI for P1: 0, mck2ui 16
4208 00:24:28.525792 best dqsien dly found for B0: ( 0, 13, 12)
4209 00:24:28.531304 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4210 00:24:28.531395 Total UI for P1: 0, mck2ui 16
4211 00:24:28.538012 best dqsien dly found for B1: ( 0, 13, 16)
4212 00:24:28.541109 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4213 00:24:28.545165 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4214 00:24:28.545251
4215 00:24:28.547625 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4216 00:24:28.550779 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4217 00:24:28.554953 [Gating] SW calibration Done
4218 00:24:28.555039 ==
4219 00:24:28.557440 Dram Type= 6, Freq= 0, CH_0, rank 1
4220 00:24:28.560787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4221 00:24:28.560873 ==
4222 00:24:28.564175 RX Vref Scan: 0
4223 00:24:28.564258
4224 00:24:28.564323 RX Vref 0 -> 0, step: 1
4225 00:24:28.567412
4226 00:24:28.567497 RX Delay -230 -> 252, step: 16
4227 00:24:28.574375 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4228 00:24:28.577139 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4229 00:24:28.580575 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4230 00:24:28.583764 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4231 00:24:28.590537 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4232 00:24:28.593572 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4233 00:24:28.596896 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4234 00:24:28.600103 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4235 00:24:28.606956 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4236 00:24:28.610277 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4237 00:24:28.613530 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4238 00:24:28.616715 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4239 00:24:28.620516 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4240 00:24:28.626556 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4241 00:24:28.629541 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4242 00:24:28.633020 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4243 00:24:28.633102 ==
4244 00:24:28.636487 Dram Type= 6, Freq= 0, CH_0, rank 1
4245 00:24:28.643145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4246 00:24:28.643229 ==
4247 00:24:28.643292 DQS Delay:
4248 00:24:28.646290 DQS0 = 0, DQS1 = 0
4249 00:24:28.646371 DQM Delay:
4250 00:24:28.646435 DQM0 = 48, DQM1 = 36
4251 00:24:28.649628 DQ Delay:
4252 00:24:28.652581 DQ0 =41, DQ1 =49, DQ2 =49, DQ3 =49
4253 00:24:28.656151 DQ4 =49, DQ5 =33, DQ6 =57, DQ7 =57
4254 00:24:28.659509 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =25
4255 00:24:28.662948 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4256 00:24:28.663028
4257 00:24:28.663090
4258 00:24:28.663148 ==
4259 00:24:28.666207 Dram Type= 6, Freq= 0, CH_0, rank 1
4260 00:24:28.669142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4261 00:24:28.669249 ==
4262 00:24:28.669361
4263 00:24:28.669421
4264 00:24:28.672499 TX Vref Scan disable
4265 00:24:28.675949 == TX Byte 0 ==
4266 00:24:28.679275 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4267 00:24:28.682725 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4268 00:24:28.685770 == TX Byte 1 ==
4269 00:24:28.689171 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4270 00:24:28.692466 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4271 00:24:28.692570 ==
4272 00:24:28.695979 Dram Type= 6, Freq= 0, CH_0, rank 1
4273 00:24:28.702515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4274 00:24:28.702602 ==
4275 00:24:28.702666
4276 00:24:28.702725
4277 00:24:28.702780 TX Vref Scan disable
4278 00:24:28.706290 == TX Byte 0 ==
4279 00:24:28.709590 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4280 00:24:28.716506 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4281 00:24:28.716592 == TX Byte 1 ==
4282 00:24:28.719576 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4283 00:24:28.726470 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4284 00:24:28.726577
4285 00:24:28.726648 [DATLAT]
4286 00:24:28.726717 Freq=600, CH0 RK1
4287 00:24:28.726796
4288 00:24:28.729376 DATLAT Default: 0x9
4289 00:24:28.732533 0, 0xFFFF, sum = 0
4290 00:24:28.732620 1, 0xFFFF, sum = 0
4291 00:24:28.736037 2, 0xFFFF, sum = 0
4292 00:24:28.736123 3, 0xFFFF, sum = 0
4293 00:24:28.739262 4, 0xFFFF, sum = 0
4294 00:24:28.739353 5, 0xFFFF, sum = 0
4295 00:24:28.742759 6, 0xFFFF, sum = 0
4296 00:24:28.742843 7, 0xFFFF, sum = 0
4297 00:24:28.746601 8, 0x0, sum = 1
4298 00:24:28.746684 9, 0x0, sum = 2
4299 00:24:28.746750 10, 0x0, sum = 3
4300 00:24:28.749097 11, 0x0, sum = 4
4301 00:24:28.749179 best_step = 9
4302 00:24:28.749241
4303 00:24:28.749343 ==
4304 00:24:28.752529 Dram Type= 6, Freq= 0, CH_0, rank 1
4305 00:24:28.759428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4306 00:24:28.759523 ==
4307 00:24:28.759590 RX Vref Scan: 0
4308 00:24:28.759649
4309 00:24:28.762552 RX Vref 0 -> 0, step: 1
4310 00:24:28.762639
4311 00:24:28.765799 RX Delay -179 -> 252, step: 8
4312 00:24:28.772386 iDelay=205, Bit 0, Center 44 (-99 ~ 188) 288
4313 00:24:28.775638 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4314 00:24:28.779251 iDelay=205, Bit 2, Center 40 (-107 ~ 188) 296
4315 00:24:28.781950 iDelay=205, Bit 3, Center 40 (-107 ~ 188) 296
4316 00:24:28.785337 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4317 00:24:28.792035 iDelay=205, Bit 5, Center 32 (-115 ~ 180) 296
4318 00:24:28.795160 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4319 00:24:28.798493 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4320 00:24:28.801456 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4321 00:24:28.808328 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4322 00:24:28.811587 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4323 00:24:28.815052 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4324 00:24:28.818327 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4325 00:24:28.825289 iDelay=205, Bit 13, Center 40 (-107 ~ 188) 296
4326 00:24:28.828214 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4327 00:24:28.831434 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4328 00:24:28.831515 ==
4329 00:24:28.835115 Dram Type= 6, Freq= 0, CH_0, rank 1
4330 00:24:28.838565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4331 00:24:28.838647 ==
4332 00:24:28.841279 DQS Delay:
4333 00:24:28.841373 DQS0 = 0, DQS1 = 0
4334 00:24:28.844589 DQM Delay:
4335 00:24:28.844669 DQM0 = 44, DQM1 = 36
4336 00:24:28.844731 DQ Delay:
4337 00:24:28.848315 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4338 00:24:28.851305 DQ4 =48, DQ5 =32, DQ6 =56, DQ7 =48
4339 00:24:28.854824 DQ8 =28, DQ9 =24, DQ10 =36, DQ11 =28
4340 00:24:28.858273 DQ12 =40, DQ13 =40, DQ14 =48, DQ15 =44
4341 00:24:28.858378
4342 00:24:28.858468
4343 00:24:28.867862 [DQSOSCAuto] RK1, (LSB)MR18= 0x4743, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 396 ps
4344 00:24:28.871808 CH0 RK1: MR19=808, MR18=4743
4345 00:24:28.878059 CH0_RK1: MR19=0x808, MR18=0x4743, DQSOSC=396, MR23=63, INC=167, DEC=111
4346 00:24:28.881010 [RxdqsGatingPostProcess] freq 600
4347 00:24:28.884508 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4348 00:24:28.888223 Pre-setting of DQS Precalculation
4349 00:24:28.894185 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4350 00:24:28.894296 ==
4351 00:24:28.897676 Dram Type= 6, Freq= 0, CH_1, rank 0
4352 00:24:28.901145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4353 00:24:28.901287 ==
4354 00:24:28.907639 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4355 00:24:28.910707 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4356 00:24:28.915207 [CA 0] Center 35 (5~66) winsize 62
4357 00:24:28.917838 [CA 1] Center 35 (5~66) winsize 62
4358 00:24:28.921596 [CA 2] Center 34 (4~65) winsize 62
4359 00:24:28.924627 [CA 3] Center 34 (4~65) winsize 62
4360 00:24:28.928334 [CA 4] Center 34 (4~65) winsize 62
4361 00:24:28.931455 [CA 5] Center 34 (3~65) winsize 63
4362 00:24:28.931540
4363 00:24:28.934501 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4364 00:24:28.934588
4365 00:24:28.937663 [CATrainingPosCal] consider 1 rank data
4366 00:24:28.941957 u2DelayCellTimex100 = 270/100 ps
4367 00:24:28.944552 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4368 00:24:28.951394 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4369 00:24:28.954327 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4370 00:24:28.958100 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4371 00:24:28.961246 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4372 00:24:28.964212 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4373 00:24:28.964301
4374 00:24:28.967190 CA PerBit enable=1, Macro0, CA PI delay=34
4375 00:24:28.967273
4376 00:24:28.970762 [CBTSetCACLKResult] CA Dly = 34
4377 00:24:28.974037 CS Dly: 5 (0~36)
4378 00:24:28.974121 ==
4379 00:24:28.977064 Dram Type= 6, Freq= 0, CH_1, rank 1
4380 00:24:28.980577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4381 00:24:28.980668 ==
4382 00:24:28.987582 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4383 00:24:28.990585 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4384 00:24:28.995132 [CA 0] Center 35 (5~66) winsize 62
4385 00:24:28.998180 [CA 1] Center 35 (5~66) winsize 62
4386 00:24:29.001589 [CA 2] Center 34 (4~65) winsize 62
4387 00:24:29.004616 [CA 3] Center 34 (3~65) winsize 63
4388 00:24:29.008383 [CA 4] Center 34 (4~65) winsize 62
4389 00:24:29.011275 [CA 5] Center 33 (3~64) winsize 62
4390 00:24:29.011356
4391 00:24:29.014270 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4392 00:24:29.014353
4393 00:24:29.017919 [CATrainingPosCal] consider 2 rank data
4394 00:24:29.021216 u2DelayCellTimex100 = 270/100 ps
4395 00:24:29.024227 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4396 00:24:29.030853 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4397 00:24:29.034817 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4398 00:24:29.037512 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4399 00:24:29.041216 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4400 00:24:29.044416 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4401 00:24:29.044517
4402 00:24:29.047697 CA PerBit enable=1, Macro0, CA PI delay=33
4403 00:24:29.047767
4404 00:24:29.050826 [CBTSetCACLKResult] CA Dly = 33
4405 00:24:29.053669 CS Dly: 5 (0~37)
4406 00:24:29.053750
4407 00:24:29.057274 ----->DramcWriteLeveling(PI) begin...
4408 00:24:29.057370 ==
4409 00:24:29.060490 Dram Type= 6, Freq= 0, CH_1, rank 0
4410 00:24:29.063907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4411 00:24:29.063995 ==
4412 00:24:29.066740 Write leveling (Byte 0): 28 => 28
4413 00:24:29.070114 Write leveling (Byte 1): 29 => 29
4414 00:24:29.073485 DramcWriteLeveling(PI) end<-----
4415 00:24:29.073570
4416 00:24:29.073633 ==
4417 00:24:29.077394 Dram Type= 6, Freq= 0, CH_1, rank 0
4418 00:24:29.079946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4419 00:24:29.080027 ==
4420 00:24:29.083579 [Gating] SW mode calibration
4421 00:24:29.089971 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4422 00:24:29.096656 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4423 00:24:29.099783 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4424 00:24:29.106571 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4425 00:24:29.110146 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4426 00:24:29.113151 0 9 12 | B1->B0 | 2f2f 2f2f | 1 0 | (1 0) (0 1)
4427 00:24:29.119762 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4428 00:24:29.122785 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4429 00:24:29.126180 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4430 00:24:29.132866 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4431 00:24:29.136210 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4432 00:24:29.139455 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4433 00:24:29.146167 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4434 00:24:29.150170 0 10 12 | B1->B0 | 3535 3b3a | 0 1 | (0 0) (1 1)
4435 00:24:29.152710 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4436 00:24:29.156153 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4437 00:24:29.163032 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4438 00:24:29.165906 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4439 00:24:29.169318 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4440 00:24:29.175786 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4441 00:24:29.178964 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4442 00:24:29.182134 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 00:24:29.188811 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 00:24:29.192184 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 00:24:29.195481 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 00:24:29.202296 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 00:24:29.205227 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 00:24:29.211931 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 00:24:29.215207 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 00:24:29.218707 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 00:24:29.225660 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 00:24:29.228472 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 00:24:29.231697 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 00:24:29.238367 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 00:24:29.241435 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 00:24:29.244866 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 00:24:29.251544 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4458 00:24:29.254937 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4459 00:24:29.258480 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4460 00:24:29.261527 Total UI for P1: 0, mck2ui 16
4461 00:24:29.265051 best dqsien dly found for B0: ( 0, 13, 10)
4462 00:24:29.268048 Total UI for P1: 0, mck2ui 16
4463 00:24:29.271257 best dqsien dly found for B1: ( 0, 13, 14)
4464 00:24:29.274477 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4465 00:24:29.278571 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4466 00:24:29.278663
4467 00:24:29.280894 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4468 00:24:29.287671 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4469 00:24:29.287757 [Gating] SW calibration Done
4470 00:24:29.291025 ==
4471 00:24:29.294208 Dram Type= 6, Freq= 0, CH_1, rank 0
4472 00:24:29.297711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4473 00:24:29.297805 ==
4474 00:24:29.297873 RX Vref Scan: 0
4475 00:24:29.297936
4476 00:24:29.301151 RX Vref 0 -> 0, step: 1
4477 00:24:29.301235
4478 00:24:29.304265 RX Delay -230 -> 252, step: 16
4479 00:24:29.307620 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4480 00:24:29.310720 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4481 00:24:29.317587 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4482 00:24:29.320395 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4483 00:24:29.323743 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4484 00:24:29.327024 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4485 00:24:29.333892 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4486 00:24:29.336793 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4487 00:24:29.340693 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4488 00:24:29.343991 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4489 00:24:29.350344 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4490 00:24:29.353714 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4491 00:24:29.356613 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4492 00:24:29.360535 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4493 00:24:29.366497 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4494 00:24:29.370111 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4495 00:24:29.370208 ==
4496 00:24:29.373045 Dram Type= 6, Freq= 0, CH_1, rank 0
4497 00:24:29.376609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4498 00:24:29.376696 ==
4499 00:24:29.379538 DQS Delay:
4500 00:24:29.379621 DQS0 = 0, DQS1 = 0
4501 00:24:29.379686 DQM Delay:
4502 00:24:29.382926 DQM0 = 44, DQM1 = 38
4503 00:24:29.383007 DQ Delay:
4504 00:24:29.386414 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4505 00:24:29.389632 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =41
4506 00:24:29.393164 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4507 00:24:29.396125 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41
4508 00:24:29.396407
4509 00:24:29.396510
4510 00:24:29.396600 ==
4511 00:24:29.399408 Dram Type= 6, Freq= 0, CH_1, rank 0
4512 00:24:29.406227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4513 00:24:29.406318 ==
4514 00:24:29.406384
4515 00:24:29.406481
4516 00:24:29.406538 TX Vref Scan disable
4517 00:24:29.409862 == TX Byte 0 ==
4518 00:24:29.413135 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4519 00:24:29.419756 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4520 00:24:29.419840 == TX Byte 1 ==
4521 00:24:29.422831 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4522 00:24:29.429887 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4523 00:24:29.429981 ==
4524 00:24:29.434084 Dram Type= 6, Freq= 0, CH_1, rank 0
4525 00:24:29.436046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4526 00:24:29.436132 ==
4527 00:24:29.436200
4528 00:24:29.436260
4529 00:24:29.439260 TX Vref Scan disable
4530 00:24:29.442606 == TX Byte 0 ==
4531 00:24:29.446112 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4532 00:24:29.449783 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4533 00:24:29.452508 == TX Byte 1 ==
4534 00:24:29.455718 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4535 00:24:29.458917 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4536 00:24:29.459015
4537 00:24:29.462230 [DATLAT]
4538 00:24:29.462313 Freq=600, CH1 RK0
4539 00:24:29.462378
4540 00:24:29.465848 DATLAT Default: 0x9
4541 00:24:29.465931 0, 0xFFFF, sum = 0
4542 00:24:29.468989 1, 0xFFFF, sum = 0
4543 00:24:29.469073 2, 0xFFFF, sum = 0
4544 00:24:29.472783 3, 0xFFFF, sum = 0
4545 00:24:29.472869 4, 0xFFFF, sum = 0
4546 00:24:29.475402 5, 0xFFFF, sum = 0
4547 00:24:29.475499 6, 0xFFFF, sum = 0
4548 00:24:29.478923 7, 0xFFFF, sum = 0
4549 00:24:29.479024 8, 0x0, sum = 1
4550 00:24:29.482560 9, 0x0, sum = 2
4551 00:24:29.482648 10, 0x0, sum = 3
4552 00:24:29.486247 11, 0x0, sum = 4
4553 00:24:29.486339 best_step = 9
4554 00:24:29.486404
4555 00:24:29.486464 ==
4556 00:24:29.488830 Dram Type= 6, Freq= 0, CH_1, rank 0
4557 00:24:29.492022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4558 00:24:29.495495 ==
4559 00:24:29.495592 RX Vref Scan: 1
4560 00:24:29.495658
4561 00:24:29.498438 RX Vref 0 -> 0, step: 1
4562 00:24:29.498538
4563 00:24:29.502174 RX Delay -179 -> 252, step: 8
4564 00:24:29.502260
4565 00:24:29.505142 Set Vref, RX VrefLevel [Byte0]: 49
4566 00:24:29.508393 [Byte1]: 52
4567 00:24:29.508505
4568 00:24:29.512161 Final RX Vref Byte 0 = 49 to rank0
4569 00:24:29.515179 Final RX Vref Byte 1 = 52 to rank0
4570 00:24:29.518327 Final RX Vref Byte 0 = 49 to rank1
4571 00:24:29.521806 Final RX Vref Byte 1 = 52 to rank1==
4572 00:24:29.525036 Dram Type= 6, Freq= 0, CH_1, rank 0
4573 00:24:29.528295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4574 00:24:29.528433 ==
4575 00:24:29.531799 DQS Delay:
4576 00:24:29.531938 DQS0 = 0, DQS1 = 0
4577 00:24:29.532056 DQM Delay:
4578 00:24:29.535057 DQM0 = 44, DQM1 = 36
4579 00:24:29.535185 DQ Delay:
4580 00:24:29.537937 DQ0 =52, DQ1 =40, DQ2 =32, DQ3 =48
4581 00:24:29.541704 DQ4 =40, DQ5 =52, DQ6 =52, DQ7 =40
4582 00:24:29.544688 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =32
4583 00:24:29.548547 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =44
4584 00:24:29.548665
4585 00:24:29.548767
4586 00:24:29.558110 [DQSOSCAuto] RK0, (LSB)MR18= 0x344e, (MSB)MR19= 0x808, tDQSOscB0 = 395 ps tDQSOscB1 = 400 ps
4587 00:24:29.561189 CH1 RK0: MR19=808, MR18=344E
4588 00:24:29.564702 CH1_RK0: MR19=0x808, MR18=0x344E, DQSOSC=395, MR23=63, INC=168, DEC=112
4589 00:24:29.564780
4590 00:24:29.567988 ----->DramcWriteLeveling(PI) begin...
4591 00:24:29.571069 ==
4592 00:24:29.574745 Dram Type= 6, Freq= 0, CH_1, rank 1
4593 00:24:29.577744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4594 00:24:29.577828 ==
4595 00:24:29.581721 Write leveling (Byte 0): 29 => 29
4596 00:24:29.584505 Write leveling (Byte 1): 29 => 29
4597 00:24:29.587447 DramcWriteLeveling(PI) end<-----
4598 00:24:29.587532
4599 00:24:29.587596 ==
4600 00:24:29.590748 Dram Type= 6, Freq= 0, CH_1, rank 1
4601 00:24:29.593847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4602 00:24:29.593932 ==
4603 00:24:29.597438 [Gating] SW mode calibration
4604 00:24:29.604049 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4605 00:24:29.610846 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4606 00:24:29.613575 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4607 00:24:29.616983 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4608 00:24:29.623571 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4609 00:24:29.627617 0 9 12 | B1->B0 | 3030 2a2a | 0 0 | (0 0) (0 0)
4610 00:24:29.630410 0 9 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4611 00:24:29.636874 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4612 00:24:29.640336 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4613 00:24:29.643620 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4614 00:24:29.650094 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4615 00:24:29.653473 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4616 00:24:29.656490 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4617 00:24:29.663402 0 10 12 | B1->B0 | 3636 4343 | 0 0 | (0 0) (0 0)
4618 00:24:29.666482 0 10 16 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
4619 00:24:29.669682 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4620 00:24:29.676361 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4621 00:24:29.679504 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4622 00:24:29.682962 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4623 00:24:29.689752 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4624 00:24:29.693034 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4625 00:24:29.695870 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4626 00:24:29.702490 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 00:24:29.706586 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 00:24:29.709448 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 00:24:29.715903 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 00:24:29.719108 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 00:24:29.722538 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 00:24:29.728742 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 00:24:29.732360 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 00:24:29.735453 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 00:24:29.741734 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 00:24:29.745452 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 00:24:29.748834 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 00:24:29.755345 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 00:24:29.758387 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 00:24:29.761675 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 00:24:29.768378 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4642 00:24:29.771650 Total UI for P1: 0, mck2ui 16
4643 00:24:29.774461 best dqsien dly found for B1: ( 0, 13, 10)
4644 00:24:29.778679 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4645 00:24:29.781678 Total UI for P1: 0, mck2ui 16
4646 00:24:29.784717 best dqsien dly found for B0: ( 0, 13, 12)
4647 00:24:29.787958 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4648 00:24:29.791347 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4649 00:24:29.791444
4650 00:24:29.797809 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4651 00:24:29.800866 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4652 00:24:29.800953 [Gating] SW calibration Done
4653 00:24:29.804102 ==
4654 00:24:29.807444 Dram Type= 6, Freq= 0, CH_1, rank 1
4655 00:24:29.810607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4656 00:24:29.810692 ==
4657 00:24:29.810757 RX Vref Scan: 0
4658 00:24:29.810817
4659 00:24:29.813734 RX Vref 0 -> 0, step: 1
4660 00:24:29.813817
4661 00:24:29.817801 RX Delay -230 -> 252, step: 16
4662 00:24:29.821013 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4663 00:24:29.827385 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4664 00:24:29.830684 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4665 00:24:29.833742 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4666 00:24:29.837395 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4667 00:24:29.840106 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4668 00:24:29.846996 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4669 00:24:29.850018 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4670 00:24:29.853443 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4671 00:24:29.856809 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4672 00:24:29.863630 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4673 00:24:29.866968 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4674 00:24:29.869897 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4675 00:24:29.874137 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4676 00:24:29.880731 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4677 00:24:29.883169 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4678 00:24:29.883252 ==
4679 00:24:29.886290 Dram Type= 6, Freq= 0, CH_1, rank 1
4680 00:24:29.890151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4681 00:24:29.890236 ==
4682 00:24:29.893033 DQS Delay:
4683 00:24:29.893115 DQS0 = 0, DQS1 = 0
4684 00:24:29.896127 DQM Delay:
4685 00:24:29.896210 DQM0 = 40, DQM1 = 39
4686 00:24:29.896275 DQ Delay:
4687 00:24:29.899539 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4688 00:24:29.902692 DQ4 =41, DQ5 =49, DQ6 =57, DQ7 =33
4689 00:24:29.905987 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4690 00:24:29.909489 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4691 00:24:29.909602
4692 00:24:29.909682
4693 00:24:29.912488 ==
4694 00:24:29.916087 Dram Type= 6, Freq= 0, CH_1, rank 1
4695 00:24:29.919056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4696 00:24:29.919140 ==
4697 00:24:29.919205
4698 00:24:29.919264
4699 00:24:29.922876 TX Vref Scan disable
4700 00:24:29.922958 == TX Byte 0 ==
4701 00:24:29.929371 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4702 00:24:29.932206 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4703 00:24:29.932290 == TX Byte 1 ==
4704 00:24:29.938968 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4705 00:24:29.942638 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4706 00:24:29.942723 ==
4707 00:24:29.945607 Dram Type= 6, Freq= 0, CH_1, rank 1
4708 00:24:29.948839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4709 00:24:29.948923 ==
4710 00:24:29.948988
4711 00:24:29.949047
4712 00:24:29.951929 TX Vref Scan disable
4713 00:24:29.955830 == TX Byte 0 ==
4714 00:24:29.958921 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4715 00:24:29.962189 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4716 00:24:29.965076 == TX Byte 1 ==
4717 00:24:29.968503 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4718 00:24:29.972005 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4719 00:24:29.972098
4720 00:24:29.975377 [DATLAT]
4721 00:24:29.975491 Freq=600, CH1 RK1
4722 00:24:29.975586
4723 00:24:29.978286 DATLAT Default: 0x9
4724 00:24:29.978370 0, 0xFFFF, sum = 0
4725 00:24:29.981655 1, 0xFFFF, sum = 0
4726 00:24:29.981752 2, 0xFFFF, sum = 0
4727 00:24:29.985563 3, 0xFFFF, sum = 0
4728 00:24:29.985649 4, 0xFFFF, sum = 0
4729 00:24:29.988436 5, 0xFFFF, sum = 0
4730 00:24:29.988520 6, 0xFFFF, sum = 0
4731 00:24:29.991597 7, 0xFFFF, sum = 0
4732 00:24:29.991681 8, 0x0, sum = 1
4733 00:24:29.995066 9, 0x0, sum = 2
4734 00:24:29.995151 10, 0x0, sum = 3
4735 00:24:29.998345 11, 0x0, sum = 4
4736 00:24:29.998431 best_step = 9
4737 00:24:29.998496
4738 00:24:29.998556 ==
4739 00:24:30.001638 Dram Type= 6, Freq= 0, CH_1, rank 1
4740 00:24:30.008376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4741 00:24:30.008463 ==
4742 00:24:30.008527 RX Vref Scan: 0
4743 00:24:30.008587
4744 00:24:30.011721 RX Vref 0 -> 0, step: 1
4745 00:24:30.011805
4746 00:24:30.015524 RX Delay -179 -> 252, step: 8
4747 00:24:30.017891 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4748 00:24:30.024439 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4749 00:24:30.028018 iDelay=205, Bit 2, Center 28 (-123 ~ 180) 304
4750 00:24:30.031167 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4751 00:24:30.034548 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4752 00:24:30.041058 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4753 00:24:30.044425 iDelay=205, Bit 6, Center 48 (-99 ~ 196) 296
4754 00:24:30.047795 iDelay=205, Bit 7, Center 36 (-115 ~ 188) 304
4755 00:24:30.050879 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4756 00:24:30.054477 iDelay=205, Bit 9, Center 28 (-123 ~ 180) 304
4757 00:24:30.061522 iDelay=205, Bit 10, Center 44 (-107 ~ 196) 304
4758 00:24:30.063883 iDelay=205, Bit 11, Center 32 (-123 ~ 188) 312
4759 00:24:30.067125 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4760 00:24:30.073762 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4761 00:24:30.077217 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4762 00:24:30.080589 iDelay=205, Bit 15, Center 48 (-107 ~ 204) 312
4763 00:24:30.080668 ==
4764 00:24:30.084008 Dram Type= 6, Freq= 0, CH_1, rank 1
4765 00:24:30.087135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4766 00:24:30.087217 ==
4767 00:24:30.090602 DQS Delay:
4768 00:24:30.090678 DQS0 = 0, DQS1 = 0
4769 00:24:30.093601 DQM Delay:
4770 00:24:30.093679 DQM0 = 40, DQM1 = 38
4771 00:24:30.097394 DQ Delay:
4772 00:24:30.097469 DQ0 =44, DQ1 =40, DQ2 =28, DQ3 =40
4773 00:24:30.100081 DQ4 =40, DQ5 =48, DQ6 =48, DQ7 =36
4774 00:24:30.103347 DQ8 =24, DQ9 =28, DQ10 =44, DQ11 =32
4775 00:24:30.106548 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =48
4776 00:24:30.106631
4777 00:24:30.109799
4778 00:24:30.116791 [DQSOSCAuto] RK1, (LSB)MR18= 0x3f64, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 397 ps
4779 00:24:30.120003 CH1 RK1: MR19=808, MR18=3F64
4780 00:24:30.126529 CH1_RK1: MR19=0x808, MR18=0x3F64, DQSOSC=391, MR23=63, INC=171, DEC=114
4781 00:24:30.129891 [RxdqsGatingPostProcess] freq 600
4782 00:24:30.132911 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4783 00:24:30.136887 Pre-setting of DQS Precalculation
4784 00:24:30.143299 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4785 00:24:30.149603 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4786 00:24:30.156001 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4787 00:24:30.156094
4788 00:24:30.156160
4789 00:24:30.159592 [Calibration Summary] 1200 Mbps
4790 00:24:30.159676 CH 0, Rank 0
4791 00:24:30.162889 SW Impedance : PASS
4792 00:24:30.165836 DUTY Scan : NO K
4793 00:24:30.165920 ZQ Calibration : PASS
4794 00:24:30.169511 Jitter Meter : NO K
4795 00:24:30.172502 CBT Training : PASS
4796 00:24:30.172585 Write leveling : PASS
4797 00:24:30.175731 RX DQS gating : PASS
4798 00:24:30.179105 RX DQ/DQS(RDDQC) : PASS
4799 00:24:30.179190 TX DQ/DQS : PASS
4800 00:24:30.183023 RX DATLAT : PASS
4801 00:24:30.185709 RX DQ/DQS(Engine): PASS
4802 00:24:30.185794 TX OE : NO K
4803 00:24:30.185860 All Pass.
4804 00:24:30.188846
4805 00:24:30.188928 CH 0, Rank 1
4806 00:24:30.192295 SW Impedance : PASS
4807 00:24:30.192378 DUTY Scan : NO K
4808 00:24:30.195727 ZQ Calibration : PASS
4809 00:24:30.195811 Jitter Meter : NO K
4810 00:24:30.199550 CBT Training : PASS
4811 00:24:30.202314 Write leveling : PASS
4812 00:24:30.202400 RX DQS gating : PASS
4813 00:24:30.205798 RX DQ/DQS(RDDQC) : PASS
4814 00:24:30.209120 TX DQ/DQS : PASS
4815 00:24:30.209204 RX DATLAT : PASS
4816 00:24:30.212694 RX DQ/DQS(Engine): PASS
4817 00:24:30.215345 TX OE : NO K
4818 00:24:30.215430 All Pass.
4819 00:24:30.215495
4820 00:24:30.215555 CH 1, Rank 0
4821 00:24:30.219034 SW Impedance : PASS
4822 00:24:30.222305 DUTY Scan : NO K
4823 00:24:30.222389 ZQ Calibration : PASS
4824 00:24:30.225207 Jitter Meter : NO K
4825 00:24:30.228957 CBT Training : PASS
4826 00:24:30.229041 Write leveling : PASS
4827 00:24:30.232318 RX DQS gating : PASS
4828 00:24:30.235855 RX DQ/DQS(RDDQC) : PASS
4829 00:24:30.235944 TX DQ/DQS : PASS
4830 00:24:30.239064 RX DATLAT : PASS
4831 00:24:30.241831 RX DQ/DQS(Engine): PASS
4832 00:24:30.241914 TX OE : NO K
4833 00:24:30.245435 All Pass.
4834 00:24:30.245517
4835 00:24:30.245581 CH 1, Rank 1
4836 00:24:30.248332 SW Impedance : PASS
4837 00:24:30.248414 DUTY Scan : NO K
4838 00:24:30.251523 ZQ Calibration : PASS
4839 00:24:30.255269 Jitter Meter : NO K
4840 00:24:30.255352 CBT Training : PASS
4841 00:24:30.258234 Write leveling : PASS
4842 00:24:30.262009 RX DQS gating : PASS
4843 00:24:30.262125 RX DQ/DQS(RDDQC) : PASS
4844 00:24:30.264905 TX DQ/DQS : PASS
4845 00:24:30.268233 RX DATLAT : PASS
4846 00:24:30.268318 RX DQ/DQS(Engine): PASS
4847 00:24:30.271381 TX OE : NO K
4848 00:24:30.271467 All Pass.
4849 00:24:30.271532
4850 00:24:30.274426 DramC Write-DBI off
4851 00:24:30.277839 PER_BANK_REFRESH: Hybrid Mode
4852 00:24:30.277925 TX_TRACKING: ON
4853 00:24:30.287871 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4854 00:24:30.290741 [FAST_K] Save calibration result to emmc
4855 00:24:30.293958 dramc_set_vcore_voltage set vcore to 662500
4856 00:24:30.298264 Read voltage for 933, 3
4857 00:24:30.298415 Vio18 = 0
4858 00:24:30.298508 Vcore = 662500
4859 00:24:30.300953 Vdram = 0
4860 00:24:30.301062 Vddq = 0
4861 00:24:30.301154 Vmddr = 0
4862 00:24:30.307570 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4863 00:24:30.311275 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4864 00:24:30.313873 MEM_TYPE=3, freq_sel=17
4865 00:24:30.317801 sv_algorithm_assistance_LP4_1600
4866 00:24:30.320667 ============ PULL DRAM RESETB DOWN ============
4867 00:24:30.323865 ========== PULL DRAM RESETB DOWN end =========
4868 00:24:30.330598 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4869 00:24:30.334027 ===================================
4870 00:24:30.337243 LPDDR4 DRAM CONFIGURATION
4871 00:24:30.340553 ===================================
4872 00:24:30.340636 EX_ROW_EN[0] = 0x0
4873 00:24:30.343815 EX_ROW_EN[1] = 0x0
4874 00:24:30.343898 LP4Y_EN = 0x0
4875 00:24:30.347100 WORK_FSP = 0x0
4876 00:24:30.347183 WL = 0x3
4877 00:24:30.350168 RL = 0x3
4878 00:24:30.350250 BL = 0x2
4879 00:24:30.353423 RPST = 0x0
4880 00:24:30.353531 RD_PRE = 0x0
4881 00:24:30.357435 WR_PRE = 0x1
4882 00:24:30.357517 WR_PST = 0x0
4883 00:24:30.360096 DBI_WR = 0x0
4884 00:24:30.363685 DBI_RD = 0x0
4885 00:24:30.363760 OTF = 0x1
4886 00:24:30.366588 ===================================
4887 00:24:30.370265 ===================================
4888 00:24:30.370347 ANA top config
4889 00:24:30.373887 ===================================
4890 00:24:30.376507 DLL_ASYNC_EN = 0
4891 00:24:30.380250 ALL_SLAVE_EN = 1
4892 00:24:30.383337 NEW_RANK_MODE = 1
4893 00:24:30.386433 DLL_IDLE_MODE = 1
4894 00:24:30.386516 LP45_APHY_COMB_EN = 1
4895 00:24:30.390141 TX_ODT_DIS = 1
4896 00:24:30.393005 NEW_8X_MODE = 1
4897 00:24:30.396284 ===================================
4898 00:24:30.399718 ===================================
4899 00:24:30.402710 data_rate = 1866
4900 00:24:30.406301 CKR = 1
4901 00:24:30.410180 DQ_P2S_RATIO = 8
4902 00:24:30.412944 ===================================
4903 00:24:30.413053 CA_P2S_RATIO = 8
4904 00:24:30.415900 DQ_CA_OPEN = 0
4905 00:24:30.420818 DQ_SEMI_OPEN = 0
4906 00:24:30.422707 CA_SEMI_OPEN = 0
4907 00:24:30.425952 CA_FULL_RATE = 0
4908 00:24:30.429211 DQ_CKDIV4_EN = 1
4909 00:24:30.429347 CA_CKDIV4_EN = 1
4910 00:24:30.432386 CA_PREDIV_EN = 0
4911 00:24:30.435525 PH8_DLY = 0
4912 00:24:30.438916 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4913 00:24:30.442370 DQ_AAMCK_DIV = 4
4914 00:24:30.445477 CA_AAMCK_DIV = 4
4915 00:24:30.445559 CA_ADMCK_DIV = 4
4916 00:24:30.448578 DQ_TRACK_CA_EN = 0
4917 00:24:30.451866 CA_PICK = 933
4918 00:24:30.455423 CA_MCKIO = 933
4919 00:24:30.458977 MCKIO_SEMI = 0
4920 00:24:30.462110 PLL_FREQ = 3732
4921 00:24:30.465529 DQ_UI_PI_RATIO = 32
4922 00:24:30.465611 CA_UI_PI_RATIO = 0
4923 00:24:30.468852 ===================================
4924 00:24:30.471779 ===================================
4925 00:24:30.475289 memory_type:LPDDR4
4926 00:24:30.478488 GP_NUM : 10
4927 00:24:30.478571 SRAM_EN : 1
4928 00:24:30.481727 MD32_EN : 0
4929 00:24:30.485142 ===================================
4930 00:24:30.488523 [ANA_INIT] >>>>>>>>>>>>>>
4931 00:24:30.492388 <<<<<< [CONFIGURE PHASE]: ANA_TX
4932 00:24:30.494926 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4933 00:24:30.498751 ===================================
4934 00:24:30.501942 data_rate = 1866,PCW = 0X8f00
4935 00:24:30.504870 ===================================
4936 00:24:30.508008 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4937 00:24:30.511760 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4938 00:24:30.518299 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4939 00:24:30.521827 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4940 00:24:30.524736 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4941 00:24:30.527813 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4942 00:24:30.531453 [ANA_INIT] flow start
4943 00:24:30.534521 [ANA_INIT] PLL >>>>>>>>
4944 00:24:30.534606 [ANA_INIT] PLL <<<<<<<<
4945 00:24:30.538200 [ANA_INIT] MIDPI >>>>>>>>
4946 00:24:30.541724 [ANA_INIT] MIDPI <<<<<<<<
4947 00:24:30.544312 [ANA_INIT] DLL >>>>>>>>
4948 00:24:30.544394 [ANA_INIT] flow end
4949 00:24:30.547769 ============ LP4 DIFF to SE enter ============
4950 00:24:30.554273 ============ LP4 DIFF to SE exit ============
4951 00:24:30.554356 [ANA_INIT] <<<<<<<<<<<<<
4952 00:24:30.558001 [Flow] Enable top DCM control >>>>>
4953 00:24:30.560679 [Flow] Enable top DCM control <<<<<
4954 00:24:30.564867 Enable DLL master slave shuffle
4955 00:24:30.571933 ==============================================================
4956 00:24:30.572017 Gating Mode config
4957 00:24:30.577892 ==============================================================
4958 00:24:30.580660 Config description:
4959 00:24:30.590492 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4960 00:24:30.597251 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4961 00:24:30.600374 SELPH_MODE 0: By rank 1: By Phase
4962 00:24:30.606852 ==============================================================
4963 00:24:30.610419 GAT_TRACK_EN = 1
4964 00:24:30.613598 RX_GATING_MODE = 2
4965 00:24:30.616822 RX_GATING_TRACK_MODE = 2
4966 00:24:30.616904 SELPH_MODE = 1
4967 00:24:30.620429 PICG_EARLY_EN = 1
4968 00:24:30.623679 VALID_LAT_VALUE = 1
4969 00:24:30.630215 ==============================================================
4970 00:24:30.633198 Enter into Gating configuration >>>>
4971 00:24:30.636418 Exit from Gating configuration <<<<
4972 00:24:30.639852 Enter into DVFS_PRE_config >>>>>
4973 00:24:30.650171 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4974 00:24:30.653021 Exit from DVFS_PRE_config <<<<<
4975 00:24:30.656236 Enter into PICG configuration >>>>
4976 00:24:30.659685 Exit from PICG configuration <<<<
4977 00:24:30.662645 [RX_INPUT] configuration >>>>>
4978 00:24:30.666273 [RX_INPUT] configuration <<<<<
4979 00:24:30.669489 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4980 00:24:30.675962 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4981 00:24:30.682672 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4982 00:24:30.690042 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4983 00:24:30.695895 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4984 00:24:30.702262 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4985 00:24:30.705712 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4986 00:24:30.709110 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4987 00:24:30.712402 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4988 00:24:30.718825 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4989 00:24:30.722362 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4990 00:24:30.725067 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4991 00:24:30.728820 ===================================
4992 00:24:30.732093 LPDDR4 DRAM CONFIGURATION
4993 00:24:30.735290 ===================================
4994 00:24:30.735398 EX_ROW_EN[0] = 0x0
4995 00:24:30.738570 EX_ROW_EN[1] = 0x0
4996 00:24:30.741769 LP4Y_EN = 0x0
4997 00:24:30.741851 WORK_FSP = 0x0
4998 00:24:30.745476 WL = 0x3
4999 00:24:30.745558 RL = 0x3
5000 00:24:30.748247 BL = 0x2
5001 00:24:30.748329 RPST = 0x0
5002 00:24:30.752104 RD_PRE = 0x0
5003 00:24:30.752186 WR_PRE = 0x1
5004 00:24:30.755380 WR_PST = 0x0
5005 00:24:30.755462 DBI_WR = 0x0
5006 00:24:30.758117 DBI_RD = 0x0
5007 00:24:30.758199 OTF = 0x1
5008 00:24:30.761769 ===================================
5009 00:24:30.768338 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5010 00:24:30.771239 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5011 00:24:30.774754 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5012 00:24:30.777835 ===================================
5013 00:24:30.781113 LPDDR4 DRAM CONFIGURATION
5014 00:24:30.784708 ===================================
5015 00:24:30.787754 EX_ROW_EN[0] = 0x10
5016 00:24:30.787882 EX_ROW_EN[1] = 0x0
5017 00:24:30.791478 LP4Y_EN = 0x0
5018 00:24:30.791583 WORK_FSP = 0x0
5019 00:24:30.794757 WL = 0x3
5020 00:24:30.794851 RL = 0x3
5021 00:24:30.798102 BL = 0x2
5022 00:24:30.798185 RPST = 0x0
5023 00:24:30.801094 RD_PRE = 0x0
5024 00:24:30.801178 WR_PRE = 0x1
5025 00:24:30.803995 WR_PST = 0x0
5026 00:24:30.804078 DBI_WR = 0x0
5027 00:24:30.807587 DBI_RD = 0x0
5028 00:24:30.807669 OTF = 0x1
5029 00:24:30.810633 ===================================
5030 00:24:30.817661 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5031 00:24:30.822463 nWR fixed to 30
5032 00:24:30.825511 [ModeRegInit_LP4] CH0 RK0
5033 00:24:30.825595 [ModeRegInit_LP4] CH0 RK1
5034 00:24:30.829299 [ModeRegInit_LP4] CH1 RK0
5035 00:24:30.831924 [ModeRegInit_LP4] CH1 RK1
5036 00:24:30.832008 match AC timing 9
5037 00:24:30.838707 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5038 00:24:30.842067 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5039 00:24:30.845534 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5040 00:24:30.852077 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5041 00:24:30.855660 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5042 00:24:30.855744 ==
5043 00:24:30.858382 Dram Type= 6, Freq= 0, CH_0, rank 0
5044 00:24:30.861545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5045 00:24:30.865166 ==
5046 00:24:30.868640 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5047 00:24:30.874688 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5048 00:24:30.878003 [CA 0] Center 38 (7~69) winsize 63
5049 00:24:30.881419 [CA 1] Center 37 (7~68) winsize 62
5050 00:24:30.884724 [CA 2] Center 35 (5~65) winsize 61
5051 00:24:30.888224 [CA 3] Center 34 (4~65) winsize 62
5052 00:24:30.891791 [CA 4] Center 33 (3~64) winsize 62
5053 00:24:30.894502 [CA 5] Center 33 (3~63) winsize 61
5054 00:24:30.894622
5055 00:24:30.897969 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5056 00:24:30.898051
5057 00:24:30.901032 [CATrainingPosCal] consider 1 rank data
5058 00:24:30.904782 u2DelayCellTimex100 = 270/100 ps
5059 00:24:30.908039 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5060 00:24:30.911347 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5061 00:24:30.914449 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5062 00:24:30.921121 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5063 00:24:30.924300 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5064 00:24:30.927921 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5065 00:24:30.928003
5066 00:24:30.930867 CA PerBit enable=1, Macro0, CA PI delay=33
5067 00:24:30.931001
5068 00:24:30.934073 [CBTSetCACLKResult] CA Dly = 33
5069 00:24:30.934157 CS Dly: 6 (0~37)
5070 00:24:30.934221 ==
5071 00:24:30.937725 Dram Type= 6, Freq= 0, CH_0, rank 1
5072 00:24:30.943883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5073 00:24:30.943967 ==
5074 00:24:30.947169 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5075 00:24:30.953589 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5076 00:24:30.957469 [CA 0] Center 38 (8~69) winsize 62
5077 00:24:30.960870 [CA 1] Center 38 (7~69) winsize 63
5078 00:24:30.964022 [CA 2] Center 35 (5~65) winsize 61
5079 00:24:30.967486 [CA 3] Center 34 (4~65) winsize 62
5080 00:24:30.970619 [CA 4] Center 33 (3~64) winsize 62
5081 00:24:30.973560 [CA 5] Center 32 (2~63) winsize 62
5082 00:24:30.973642
5083 00:24:30.977147 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5084 00:24:30.977229
5085 00:24:30.980372 [CATrainingPosCal] consider 2 rank data
5086 00:24:30.983436 u2DelayCellTimex100 = 270/100 ps
5087 00:24:30.986838 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5088 00:24:30.993852 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5089 00:24:30.996760 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5090 00:24:31.000215 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5091 00:24:31.003549 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5092 00:24:31.006742 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5093 00:24:31.006824
5094 00:24:31.010427 CA PerBit enable=1, Macro0, CA PI delay=33
5095 00:24:31.010509
5096 00:24:31.013491 [CBTSetCACLKResult] CA Dly = 33
5097 00:24:31.016541 CS Dly: 7 (0~39)
5098 00:24:31.016624
5099 00:24:31.020233 ----->DramcWriteLeveling(PI) begin...
5100 00:24:31.020316 ==
5101 00:24:31.023590 Dram Type= 6, Freq= 0, CH_0, rank 0
5102 00:24:31.026834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5103 00:24:31.026917 ==
5104 00:24:31.030059 Write leveling (Byte 0): 33 => 33
5105 00:24:31.033653 Write leveling (Byte 1): 25 => 25
5106 00:24:31.036913 DramcWriteLeveling(PI) end<-----
5107 00:24:31.036994
5108 00:24:31.037063 ==
5109 00:24:31.039625 Dram Type= 6, Freq= 0, CH_0, rank 0
5110 00:24:31.042928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5111 00:24:31.043011 ==
5112 00:24:31.046461 [Gating] SW mode calibration
5113 00:24:31.053269 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5114 00:24:31.059854 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5115 00:24:31.062765 0 14 0 | B1->B0 | 2323 3333 | 0 1 | (0 0) (0 0)
5116 00:24:31.066493 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5117 00:24:31.073106 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5118 00:24:31.076070 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5119 00:24:31.079465 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5120 00:24:31.085873 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5121 00:24:31.089854 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5122 00:24:31.092569 0 14 28 | B1->B0 | 3434 2d2d | 1 0 | (1 0) (0 0)
5123 00:24:31.098936 0 15 0 | B1->B0 | 3030 2525 | 1 0 | (1 1) (0 0)
5124 00:24:31.102440 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5125 00:24:31.105748 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5126 00:24:31.112371 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5127 00:24:31.115841 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5128 00:24:31.118901 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5129 00:24:31.125175 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5130 00:24:31.128722 0 15 28 | B1->B0 | 2323 3737 | 0 0 | (0 0) (1 1)
5131 00:24:31.131915 1 0 0 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
5132 00:24:31.138640 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5133 00:24:31.142342 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5134 00:24:31.145612 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5135 00:24:31.151680 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5136 00:24:31.155095 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5137 00:24:31.161467 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5138 00:24:31.165496 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5139 00:24:31.168658 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 00:24:31.174870 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5141 00:24:31.178102 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 00:24:31.181197 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 00:24:31.188055 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 00:24:31.191297 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 00:24:31.194395 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 00:24:31.201107 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 00:24:31.204708 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 00:24:31.207852 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 00:24:31.211295 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5150 00:24:31.217755 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 00:24:31.220832 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 00:24:31.227685 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 00:24:31.230943 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 00:24:31.234181 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5155 00:24:31.240565 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5156 00:24:31.240646 Total UI for P1: 0, mck2ui 16
5157 00:24:31.243837 best dqsien dly found for B0: ( 1, 2, 28)
5158 00:24:31.250628 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5159 00:24:31.253644 Total UI for P1: 0, mck2ui 16
5160 00:24:31.257057 best dqsien dly found for B1: ( 1, 2, 30)
5161 00:24:31.260946 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5162 00:24:31.263558 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5163 00:24:31.263640
5164 00:24:31.267423 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5165 00:24:31.270581 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5166 00:24:31.273454 [Gating] SW calibration Done
5167 00:24:31.273535 ==
5168 00:24:31.276981 Dram Type= 6, Freq= 0, CH_0, rank 0
5169 00:24:31.280105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5170 00:24:31.283576 ==
5171 00:24:31.283657 RX Vref Scan: 0
5172 00:24:31.283721
5173 00:24:31.286724 RX Vref 0 -> 0, step: 1
5174 00:24:31.286805
5175 00:24:31.290244 RX Delay -80 -> 252, step: 8
5176 00:24:31.293251 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5177 00:24:31.296334 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5178 00:24:31.299985 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5179 00:24:31.303214 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5180 00:24:31.306766 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5181 00:24:31.313051 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5182 00:24:31.316351 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5183 00:24:31.323111 iDelay=208, Bit 7, Center 107 (16 ~ 199) 184
5184 00:24:31.323198 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5185 00:24:31.326042 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5186 00:24:31.332742 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5187 00:24:31.336075 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5188 00:24:31.339087 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5189 00:24:31.342595 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5190 00:24:31.345780 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5191 00:24:31.352382 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5192 00:24:31.352464 ==
5193 00:24:31.355765 Dram Type= 6, Freq= 0, CH_0, rank 0
5194 00:24:31.358954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5195 00:24:31.359070 ==
5196 00:24:31.359174 DQS Delay:
5197 00:24:31.362744 DQS0 = 0, DQS1 = 0
5198 00:24:31.362829 DQM Delay:
5199 00:24:31.365416 DQM0 = 101, DQM1 = 87
5200 00:24:31.365501 DQ Delay:
5201 00:24:31.368934 DQ0 =103, DQ1 =103, DQ2 =95, DQ3 =99
5202 00:24:31.372182 DQ4 =103, DQ5 =91, DQ6 =111, DQ7 =107
5203 00:24:31.375559 DQ8 =79, DQ9 =71, DQ10 =87, DQ11 =83
5204 00:24:31.379052 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5205 00:24:31.379137
5206 00:24:31.379237
5207 00:24:31.379318 ==
5208 00:24:31.382348 Dram Type= 6, Freq= 0, CH_0, rank 0
5209 00:24:31.385279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5210 00:24:31.388885 ==
5211 00:24:31.388969
5212 00:24:31.389053
5213 00:24:31.389151 TX Vref Scan disable
5214 00:24:31.392184 == TX Byte 0 ==
5215 00:24:31.395232 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5216 00:24:31.401847 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5217 00:24:31.401933 == TX Byte 1 ==
5218 00:24:31.405077 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5219 00:24:31.411737 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5220 00:24:31.411822 ==
5221 00:24:31.415102 Dram Type= 6, Freq= 0, CH_0, rank 0
5222 00:24:31.418623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5223 00:24:31.418707 ==
5224 00:24:31.418792
5225 00:24:31.418872
5226 00:24:31.421702 TX Vref Scan disable
5227 00:24:31.424995 == TX Byte 0 ==
5228 00:24:31.428436 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5229 00:24:31.431556 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5230 00:24:31.434978 == TX Byte 1 ==
5231 00:24:31.438445 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5232 00:24:31.441480 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5233 00:24:31.441564
5234 00:24:31.441649 [DATLAT]
5235 00:24:31.444767 Freq=933, CH0 RK0
5236 00:24:31.444852
5237 00:24:31.447920 DATLAT Default: 0xd
5238 00:24:31.448004 0, 0xFFFF, sum = 0
5239 00:24:31.451497 1, 0xFFFF, sum = 0
5240 00:24:31.451578 2, 0xFFFF, sum = 0
5241 00:24:31.454716 3, 0xFFFF, sum = 0
5242 00:24:31.454801 4, 0xFFFF, sum = 0
5243 00:24:31.458523 5, 0xFFFF, sum = 0
5244 00:24:31.458608 6, 0xFFFF, sum = 0
5245 00:24:31.461410 7, 0xFFFF, sum = 0
5246 00:24:31.461496 8, 0xFFFF, sum = 0
5247 00:24:31.464668 9, 0xFFFF, sum = 0
5248 00:24:31.464780 10, 0x0, sum = 1
5249 00:24:31.467900 11, 0x0, sum = 2
5250 00:24:31.467983 12, 0x0, sum = 3
5251 00:24:31.471256 13, 0x0, sum = 4
5252 00:24:31.471340 best_step = 11
5253 00:24:31.471403
5254 00:24:31.471462 ==
5255 00:24:31.474557 Dram Type= 6, Freq= 0, CH_0, rank 0
5256 00:24:31.477848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5257 00:24:31.481154 ==
5258 00:24:31.481281 RX Vref Scan: 1
5259 00:24:31.481368
5260 00:24:31.484195 RX Vref 0 -> 0, step: 1
5261 00:24:31.484291
5262 00:24:31.487499 RX Delay -69 -> 252, step: 4
5263 00:24:31.487595
5264 00:24:31.487683 Set Vref, RX VrefLevel [Byte0]: 57
5265 00:24:31.490772 [Byte1]: 50
5266 00:24:31.496017
5267 00:24:31.496100 Final RX Vref Byte 0 = 57 to rank0
5268 00:24:31.499564 Final RX Vref Byte 1 = 50 to rank0
5269 00:24:31.502556 Final RX Vref Byte 0 = 57 to rank1
5270 00:24:31.506061 Final RX Vref Byte 1 = 50 to rank1==
5271 00:24:31.509131 Dram Type= 6, Freq= 0, CH_0, rank 0
5272 00:24:31.515621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5273 00:24:31.515728 ==
5274 00:24:31.515795 DQS Delay:
5275 00:24:31.519117 DQS0 = 0, DQS1 = 0
5276 00:24:31.519228 DQM Delay:
5277 00:24:31.519322 DQM0 = 103, DQM1 = 90
5278 00:24:31.522385 DQ Delay:
5279 00:24:31.525471 DQ0 =104, DQ1 =102, DQ2 =98, DQ3 =100
5280 00:24:31.528870 DQ4 =104, DQ5 =96, DQ6 =114, DQ7 =108
5281 00:24:31.532058 DQ8 =82, DQ9 =76, DQ10 =94, DQ11 =86
5282 00:24:31.535798 DQ12 =96, DQ13 =92, DQ14 =96, DQ15 =98
5283 00:24:31.535887
5284 00:24:31.535953
5285 00:24:31.541900 [DQSOSCAuto] RK0, (LSB)MR18= 0x201b, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 411 ps
5286 00:24:31.545549 CH0 RK0: MR19=505, MR18=201B
5287 00:24:31.552216 CH0_RK0: MR19=0x505, MR18=0x201B, DQSOSC=411, MR23=63, INC=64, DEC=42
5288 00:24:31.552319
5289 00:24:31.554927 ----->DramcWriteLeveling(PI) begin...
5290 00:24:31.555015 ==
5291 00:24:31.558445 Dram Type= 6, Freq= 0, CH_0, rank 1
5292 00:24:31.561718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5293 00:24:31.564994 ==
5294 00:24:31.565079 Write leveling (Byte 0): 31 => 31
5295 00:24:31.568463 Write leveling (Byte 1): 28 => 28
5296 00:24:31.571910 DramcWriteLeveling(PI) end<-----
5297 00:24:31.571993
5298 00:24:31.572057 ==
5299 00:24:31.574830 Dram Type= 6, Freq= 0, CH_0, rank 1
5300 00:24:31.581211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5301 00:24:31.581306 ==
5302 00:24:31.585078 [Gating] SW mode calibration
5303 00:24:31.591276 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5304 00:24:31.594513 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5305 00:24:31.601364 0 14 0 | B1->B0 | 2f2e 3434 | 1 1 | (1 1) (1 1)
5306 00:24:31.604531 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5307 00:24:31.608170 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5308 00:24:31.614187 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5309 00:24:31.617464 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5310 00:24:31.621507 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5311 00:24:31.627666 0 14 24 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
5312 00:24:31.631200 0 14 28 | B1->B0 | 3434 2b2b | 0 0 | (0 0) (0 0)
5313 00:24:31.634092 0 15 0 | B1->B0 | 3030 2525 | 0 0 | (1 1) (0 0)
5314 00:24:31.640678 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5315 00:24:31.644296 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5316 00:24:31.647359 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5317 00:24:31.654255 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5318 00:24:31.657469 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5319 00:24:31.660440 0 15 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 1)
5320 00:24:31.667634 0 15 28 | B1->B0 | 2525 4040 | 0 0 | (1 1) (0 0)
5321 00:24:31.670803 1 0 0 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
5322 00:24:31.673875 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5323 00:24:31.680660 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5324 00:24:31.684537 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5325 00:24:31.687501 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5326 00:24:31.693785 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5327 00:24:31.696950 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5328 00:24:31.699961 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5329 00:24:31.706713 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 00:24:31.710231 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 00:24:31.713598 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 00:24:31.719851 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 00:24:31.723055 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 00:24:31.726566 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 00:24:31.733008 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 00:24:31.736974 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 00:24:31.739671 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5338 00:24:31.746228 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5339 00:24:31.749666 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5340 00:24:31.752948 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5341 00:24:31.759376 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5342 00:24:31.763170 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 00:24:31.766182 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 00:24:31.772680 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5345 00:24:31.775757 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5346 00:24:31.779432 Total UI for P1: 0, mck2ui 16
5347 00:24:31.782648 best dqsien dly found for B0: ( 1, 2, 28)
5348 00:24:31.785713 Total UI for P1: 0, mck2ui 16
5349 00:24:31.788925 best dqsien dly found for B1: ( 1, 2, 30)
5350 00:24:31.792431 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5351 00:24:31.795584 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5352 00:24:31.795703
5353 00:24:31.799071 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5354 00:24:31.802147 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5355 00:24:31.805651 [Gating] SW calibration Done
5356 00:24:31.805739 ==
5357 00:24:31.808992 Dram Type= 6, Freq= 0, CH_0, rank 1
5358 00:24:31.815490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5359 00:24:31.815584 ==
5360 00:24:31.815650 RX Vref Scan: 0
5361 00:24:31.815709
5362 00:24:31.818874 RX Vref 0 -> 0, step: 1
5363 00:24:31.818957
5364 00:24:31.822219 RX Delay -80 -> 252, step: 8
5365 00:24:31.825088 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5366 00:24:31.828581 iDelay=200, Bit 1, Center 103 (8 ~ 199) 192
5367 00:24:31.831951 iDelay=200, Bit 2, Center 95 (8 ~ 183) 176
5368 00:24:31.835638 iDelay=200, Bit 3, Center 99 (8 ~ 191) 184
5369 00:24:31.838582 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5370 00:24:31.845208 iDelay=200, Bit 5, Center 91 (0 ~ 183) 184
5371 00:24:31.848431 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5372 00:24:31.852228 iDelay=200, Bit 7, Center 107 (16 ~ 199) 184
5373 00:24:31.855156 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5374 00:24:31.858694 iDelay=200, Bit 9, Center 75 (-16 ~ 167) 184
5375 00:24:31.865099 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5376 00:24:31.868299 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5377 00:24:31.871581 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5378 00:24:31.875474 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5379 00:24:31.878074 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5380 00:24:31.884620 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5381 00:24:31.884741 ==
5382 00:24:31.888259 Dram Type= 6, Freq= 0, CH_0, rank 1
5383 00:24:31.891003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5384 00:24:31.891092 ==
5385 00:24:31.891158 DQS Delay:
5386 00:24:31.894742 DQS0 = 0, DQS1 = 0
5387 00:24:31.894825 DQM Delay:
5388 00:24:31.898057 DQM0 = 100, DQM1 = 88
5389 00:24:31.898138 DQ Delay:
5390 00:24:31.901199 DQ0 =99, DQ1 =103, DQ2 =95, DQ3 =99
5391 00:24:31.904380 DQ4 =103, DQ5 =91, DQ6 =107, DQ7 =107
5392 00:24:31.907879 DQ8 =79, DQ9 =75, DQ10 =91, DQ11 =83
5393 00:24:31.911007 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5394 00:24:31.911088
5395 00:24:31.911151
5396 00:24:31.911209 ==
5397 00:24:31.914692 Dram Type= 6, Freq= 0, CH_0, rank 1
5398 00:24:31.917691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5399 00:24:31.921692 ==
5400 00:24:31.921772
5401 00:24:31.921835
5402 00:24:31.921893 TX Vref Scan disable
5403 00:24:31.924619 == TX Byte 0 ==
5404 00:24:31.927688 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5405 00:24:31.931477 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5406 00:24:31.934214 == TX Byte 1 ==
5407 00:24:31.938050 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5408 00:24:31.941675 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5409 00:24:31.944544 ==
5410 00:24:31.944632 Dram Type= 6, Freq= 0, CH_0, rank 1
5411 00:24:31.951156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5412 00:24:31.951255 ==
5413 00:24:31.951321
5414 00:24:31.951380
5415 00:24:31.954180 TX Vref Scan disable
5416 00:24:31.954265 == TX Byte 0 ==
5417 00:24:31.960468 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5418 00:24:31.964006 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5419 00:24:31.964130 == TX Byte 1 ==
5420 00:24:31.971521 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5421 00:24:31.973891 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5422 00:24:31.974007
5423 00:24:31.974069 [DATLAT]
5424 00:24:31.977218 Freq=933, CH0 RK1
5425 00:24:31.977342
5426 00:24:31.977406 DATLAT Default: 0xb
5427 00:24:31.980177 0, 0xFFFF, sum = 0
5428 00:24:31.980260 1, 0xFFFF, sum = 0
5429 00:24:31.984776 2, 0xFFFF, sum = 0
5430 00:24:31.984860 3, 0xFFFF, sum = 0
5431 00:24:31.986902 4, 0xFFFF, sum = 0
5432 00:24:31.986985 5, 0xFFFF, sum = 0
5433 00:24:31.990260 6, 0xFFFF, sum = 0
5434 00:24:31.993954 7, 0xFFFF, sum = 0
5435 00:24:31.994037 8, 0xFFFF, sum = 0
5436 00:24:31.996875 9, 0xFFFF, sum = 0
5437 00:24:31.996958 10, 0x0, sum = 1
5438 00:24:32.000240 11, 0x0, sum = 2
5439 00:24:32.000323 12, 0x0, sum = 3
5440 00:24:32.000390 13, 0x0, sum = 4
5441 00:24:32.003284 best_step = 11
5442 00:24:32.003368
5443 00:24:32.003432 ==
5444 00:24:32.007119 Dram Type= 6, Freq= 0, CH_0, rank 1
5445 00:24:32.009893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5446 00:24:32.010005 ==
5447 00:24:32.013154 RX Vref Scan: 0
5448 00:24:32.013241
5449 00:24:32.017002 RX Vref 0 -> 0, step: 1
5450 00:24:32.017084
5451 00:24:32.017148 RX Delay -61 -> 252, step: 4
5452 00:24:32.024149 iDelay=195, Bit 0, Center 98 (15 ~ 182) 168
5453 00:24:32.027750 iDelay=195, Bit 1, Center 102 (15 ~ 190) 176
5454 00:24:32.030816 iDelay=195, Bit 2, Center 96 (11 ~ 182) 172
5455 00:24:32.034408 iDelay=195, Bit 3, Center 98 (11 ~ 186) 176
5456 00:24:32.037711 iDelay=195, Bit 4, Center 104 (19 ~ 190) 172
5457 00:24:32.044146 iDelay=195, Bit 5, Center 92 (7 ~ 178) 172
5458 00:24:32.047191 iDelay=195, Bit 6, Center 110 (27 ~ 194) 168
5459 00:24:32.050712 iDelay=195, Bit 7, Center 108 (23 ~ 194) 172
5460 00:24:32.054204 iDelay=195, Bit 8, Center 82 (-5 ~ 170) 176
5461 00:24:32.057096 iDelay=195, Bit 9, Center 78 (-9 ~ 166) 176
5462 00:24:32.064008 iDelay=195, Bit 10, Center 94 (11 ~ 178) 168
5463 00:24:32.067087 iDelay=195, Bit 11, Center 84 (-1 ~ 170) 172
5464 00:24:32.070190 iDelay=195, Bit 12, Center 96 (15 ~ 178) 164
5465 00:24:32.073995 iDelay=195, Bit 13, Center 94 (11 ~ 178) 168
5466 00:24:32.077600 iDelay=195, Bit 14, Center 98 (11 ~ 186) 176
5467 00:24:32.083895 iDelay=195, Bit 15, Center 96 (11 ~ 182) 172
5468 00:24:32.084015 ==
5469 00:24:32.087060 Dram Type= 6, Freq= 0, CH_0, rank 1
5470 00:24:32.090363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5471 00:24:32.090458 ==
5472 00:24:32.090526 DQS Delay:
5473 00:24:32.093696 DQS0 = 0, DQS1 = 0
5474 00:24:32.093781 DQM Delay:
5475 00:24:32.096840 DQM0 = 101, DQM1 = 90
5476 00:24:32.096926 DQ Delay:
5477 00:24:32.100384 DQ0 =98, DQ1 =102, DQ2 =96, DQ3 =98
5478 00:24:32.103824 DQ4 =104, DQ5 =92, DQ6 =110, DQ7 =108
5479 00:24:32.106429 DQ8 =82, DQ9 =78, DQ10 =94, DQ11 =84
5480 00:24:32.110109 DQ12 =96, DQ13 =94, DQ14 =98, DQ15 =96
5481 00:24:32.110219
5482 00:24:32.110307
5483 00:24:32.120037 [DQSOSCAuto] RK1, (LSB)MR18= 0x1411, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 415 ps
5484 00:24:32.120176 CH0 RK1: MR19=505, MR18=1411
5485 00:24:32.126583 CH0_RK1: MR19=0x505, MR18=0x1411, DQSOSC=415, MR23=63, INC=62, DEC=41
5486 00:24:32.130054 [RxdqsGatingPostProcess] freq 933
5487 00:24:32.135996 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5488 00:24:32.139612 best DQS0 dly(2T, 0.5T) = (0, 10)
5489 00:24:32.143618 best DQS1 dly(2T, 0.5T) = (0, 10)
5490 00:24:32.146203 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5491 00:24:32.149616 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5492 00:24:32.152921 best DQS0 dly(2T, 0.5T) = (0, 10)
5493 00:24:32.153009 best DQS1 dly(2T, 0.5T) = (0, 10)
5494 00:24:32.156900 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5495 00:24:32.159582 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5496 00:24:32.163124 Pre-setting of DQS Precalculation
5497 00:24:32.169532 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5498 00:24:32.169640 ==
5499 00:24:32.172729 Dram Type= 6, Freq= 0, CH_1, rank 0
5500 00:24:32.176023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5501 00:24:32.176113 ==
5502 00:24:32.182510 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5503 00:24:32.189376 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5504 00:24:32.193214 [CA 0] Center 36 (6~67) winsize 62
5505 00:24:32.195864 [CA 1] Center 36 (6~67) winsize 62
5506 00:24:32.199331 [CA 2] Center 34 (4~65) winsize 62
5507 00:24:32.202571 [CA 3] Center 34 (4~65) winsize 62
5508 00:24:32.205597 [CA 4] Center 34 (4~65) winsize 62
5509 00:24:32.209172 [CA 5] Center 33 (3~64) winsize 62
5510 00:24:32.209320
5511 00:24:32.212283 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5512 00:24:32.212365
5513 00:24:32.215646 [CATrainingPosCal] consider 1 rank data
5514 00:24:32.218632 u2DelayCellTimex100 = 270/100 ps
5515 00:24:32.221902 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5516 00:24:32.225509 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5517 00:24:32.228650 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5518 00:24:32.231968 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5519 00:24:32.235096 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5520 00:24:32.241805 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5521 00:24:32.241887
5522 00:24:32.245672 CA PerBit enable=1, Macro0, CA PI delay=33
5523 00:24:32.245755
5524 00:24:32.248459 [CBTSetCACLKResult] CA Dly = 33
5525 00:24:32.248541 CS Dly: 5 (0~36)
5526 00:24:32.248606 ==
5527 00:24:32.251705 Dram Type= 6, Freq= 0, CH_1, rank 1
5528 00:24:32.255401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5529 00:24:32.258341 ==
5530 00:24:32.261526 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5531 00:24:32.269035 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5532 00:24:32.271433 [CA 0] Center 36 (6~67) winsize 62
5533 00:24:32.274999 [CA 1] Center 36 (6~67) winsize 62
5534 00:24:32.278370 [CA 2] Center 34 (4~65) winsize 62
5535 00:24:32.281403 [CA 3] Center 33 (3~64) winsize 62
5536 00:24:32.284602 [CA 4] Center 34 (4~64) winsize 61
5537 00:24:32.287788 [CA 5] Center 33 (3~64) winsize 62
5538 00:24:32.287942
5539 00:24:32.291266 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5540 00:24:32.291421
5541 00:24:32.294553 [CATrainingPosCal] consider 2 rank data
5542 00:24:32.298462 u2DelayCellTimex100 = 270/100 ps
5543 00:24:32.300883 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5544 00:24:32.304563 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5545 00:24:32.311183 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5546 00:24:32.314220 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5547 00:24:32.317917 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5548 00:24:32.320922 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5549 00:24:32.321030
5550 00:24:32.324355 CA PerBit enable=1, Macro0, CA PI delay=33
5551 00:24:32.324451
5552 00:24:32.327684 [CBTSetCACLKResult] CA Dly = 33
5553 00:24:32.327778 CS Dly: 6 (0~38)
5554 00:24:32.327865
5555 00:24:32.330768 ----->DramcWriteLeveling(PI) begin...
5556 00:24:32.334156 ==
5557 00:24:32.337525 Dram Type= 6, Freq= 0, CH_1, rank 0
5558 00:24:32.340825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5559 00:24:32.340912 ==
5560 00:24:32.343930 Write leveling (Byte 0): 26 => 26
5561 00:24:32.347633 Write leveling (Byte 1): 25 => 25
5562 00:24:32.350243 DramcWriteLeveling(PI) end<-----
5563 00:24:32.350332
5564 00:24:32.350445 ==
5565 00:24:32.354229 Dram Type= 6, Freq= 0, CH_1, rank 0
5566 00:24:32.357243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5567 00:24:32.357381 ==
5568 00:24:32.360364 [Gating] SW mode calibration
5569 00:24:32.367020 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5570 00:24:32.373217 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5571 00:24:32.376935 0 14 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5572 00:24:32.379952 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5573 00:24:32.386676 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5574 00:24:32.390364 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5575 00:24:32.393103 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5576 00:24:32.399976 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5577 00:24:32.402831 0 14 24 | B1->B0 | 3434 3232 | 0 1 | (0 0) (1 0)
5578 00:24:32.406393 0 14 28 | B1->B0 | 2f2f 2727 | 0 0 | (1 0) (0 0)
5579 00:24:32.412988 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5580 00:24:32.416367 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5581 00:24:32.419331 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5582 00:24:32.426680 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5583 00:24:32.429335 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5584 00:24:32.432941 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5585 00:24:32.439249 0 15 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5586 00:24:32.442652 0 15 28 | B1->B0 | 3636 3f3f | 0 0 | (0 0) (0 0)
5587 00:24:32.445686 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5588 00:24:32.452806 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5589 00:24:32.455645 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5590 00:24:32.458934 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5591 00:24:32.466154 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5592 00:24:32.469091 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5593 00:24:32.472242 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5594 00:24:32.478585 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5595 00:24:32.482390 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 00:24:32.485380 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 00:24:32.492069 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 00:24:32.495577 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 00:24:32.499336 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 00:24:32.505578 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 00:24:32.508397 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 00:24:32.511590 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 00:24:32.518427 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5604 00:24:32.521526 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5605 00:24:32.524993 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5606 00:24:32.531451 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 00:24:32.534910 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 00:24:32.538095 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 00:24:32.544405 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5610 00:24:32.548072 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5611 00:24:32.551214 Total UI for P1: 0, mck2ui 16
5612 00:24:32.554745 best dqsien dly found for B0: ( 1, 2, 24)
5613 00:24:32.557686 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5614 00:24:32.561175 Total UI for P1: 0, mck2ui 16
5615 00:24:32.564961 best dqsien dly found for B1: ( 1, 2, 26)
5616 00:24:32.568388 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5617 00:24:32.574606 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5618 00:24:32.574710
5619 00:24:32.577723 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5620 00:24:32.580746 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5621 00:24:32.583729 [Gating] SW calibration Done
5622 00:24:32.583832 ==
5623 00:24:32.587901 Dram Type= 6, Freq= 0, CH_1, rank 0
5624 00:24:32.590879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5625 00:24:32.591002 ==
5626 00:24:32.593956 RX Vref Scan: 0
5627 00:24:32.594042
5628 00:24:32.594127 RX Vref 0 -> 0, step: 1
5629 00:24:32.594208
5630 00:24:32.597408 RX Delay -80 -> 252, step: 8
5631 00:24:32.600527 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5632 00:24:32.603921 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5633 00:24:32.610274 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5634 00:24:32.614109 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5635 00:24:32.617168 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5636 00:24:32.620637 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5637 00:24:32.623198 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5638 00:24:32.630183 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5639 00:24:32.633597 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5640 00:24:32.636779 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5641 00:24:32.640180 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5642 00:24:32.643097 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5643 00:24:32.646458 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5644 00:24:32.653143 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5645 00:24:32.656403 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5646 00:24:32.660284 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5647 00:24:32.660381 ==
5648 00:24:32.662807 Dram Type= 6, Freq= 0, CH_1, rank 0
5649 00:24:32.666383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5650 00:24:32.666517 ==
5651 00:24:32.669669 DQS Delay:
5652 00:24:32.669756 DQS0 = 0, DQS1 = 0
5653 00:24:32.672817 DQM Delay:
5654 00:24:32.672934 DQM0 = 98, DQM1 = 94
5655 00:24:32.673029 DQ Delay:
5656 00:24:32.676374 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =99
5657 00:24:32.679575 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =95
5658 00:24:32.682747 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5659 00:24:32.689455 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =99
5660 00:24:32.689557
5661 00:24:32.689622
5662 00:24:32.689682 ==
5663 00:24:32.692844 Dram Type= 6, Freq= 0, CH_1, rank 0
5664 00:24:32.696084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5665 00:24:32.696173 ==
5666 00:24:32.696238
5667 00:24:32.696298
5668 00:24:32.699485 TX Vref Scan disable
5669 00:24:32.699570 == TX Byte 0 ==
5670 00:24:32.706586 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5671 00:24:32.709001 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5672 00:24:32.709122 == TX Byte 1 ==
5673 00:24:32.715530 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5674 00:24:32.718982 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5675 00:24:32.719124 ==
5676 00:24:32.721995 Dram Type= 6, Freq= 0, CH_1, rank 0
5677 00:24:32.725515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5678 00:24:32.728749 ==
5679 00:24:32.728836
5680 00:24:32.728922
5681 00:24:32.729011 TX Vref Scan disable
5682 00:24:32.732737 == TX Byte 0 ==
5683 00:24:32.735692 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5684 00:24:32.741877 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5685 00:24:32.741980 == TX Byte 1 ==
5686 00:24:32.745639 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5687 00:24:32.752017 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5688 00:24:32.752116
5689 00:24:32.752183 [DATLAT]
5690 00:24:32.752243 Freq=933, CH1 RK0
5691 00:24:32.752303
5692 00:24:32.755343 DATLAT Default: 0xd
5693 00:24:32.755428 0, 0xFFFF, sum = 0
5694 00:24:32.758479 1, 0xFFFF, sum = 0
5695 00:24:32.761490 2, 0xFFFF, sum = 0
5696 00:24:32.761577 3, 0xFFFF, sum = 0
5697 00:24:32.765925 4, 0xFFFF, sum = 0
5698 00:24:32.766013 5, 0xFFFF, sum = 0
5699 00:24:32.768652 6, 0xFFFF, sum = 0
5700 00:24:32.768736 7, 0xFFFF, sum = 0
5701 00:24:32.771561 8, 0xFFFF, sum = 0
5702 00:24:32.771647 9, 0xFFFF, sum = 0
5703 00:24:32.775095 10, 0x0, sum = 1
5704 00:24:32.775180 11, 0x0, sum = 2
5705 00:24:32.778017 12, 0x0, sum = 3
5706 00:24:32.778102 13, 0x0, sum = 4
5707 00:24:32.781637 best_step = 11
5708 00:24:32.781722
5709 00:24:32.781786 ==
5710 00:24:32.784645 Dram Type= 6, Freq= 0, CH_1, rank 0
5711 00:24:32.787910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5712 00:24:32.787995 ==
5713 00:24:32.788060 RX Vref Scan: 1
5714 00:24:32.788120
5715 00:24:32.791545 RX Vref 0 -> 0, step: 1
5716 00:24:32.791629
5717 00:24:32.794684 RX Delay -61 -> 252, step: 4
5718 00:24:32.794767
5719 00:24:32.797974 Set Vref, RX VrefLevel [Byte0]: 49
5720 00:24:32.800948 [Byte1]: 52
5721 00:24:32.804648
5722 00:24:32.804742 Final RX Vref Byte 0 = 49 to rank0
5723 00:24:32.808089 Final RX Vref Byte 1 = 52 to rank0
5724 00:24:32.811517 Final RX Vref Byte 0 = 49 to rank1
5725 00:24:32.814518 Final RX Vref Byte 1 = 52 to rank1==
5726 00:24:32.817926 Dram Type= 6, Freq= 0, CH_1, rank 0
5727 00:24:32.824697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5728 00:24:32.824797 ==
5729 00:24:32.824864 DQS Delay:
5730 00:24:32.827860 DQS0 = 0, DQS1 = 0
5731 00:24:32.827944 DQM Delay:
5732 00:24:32.828009 DQM0 = 98, DQM1 = 94
5733 00:24:32.831048 DQ Delay:
5734 00:24:32.834192 DQ0 =104, DQ1 =92, DQ2 =88, DQ3 =98
5735 00:24:32.838032 DQ4 =96, DQ5 =106, DQ6 =110, DQ7 =92
5736 00:24:32.841371 DQ8 =80, DQ9 =86, DQ10 =90, DQ11 =88
5737 00:24:32.844445 DQ12 =106, DQ13 =106, DQ14 =98, DQ15 =102
5738 00:24:32.844538
5739 00:24:32.844624
5740 00:24:32.850851 [DQSOSCAuto] RK0, (LSB)MR18= 0xa1a, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 418 ps
5741 00:24:32.854254 CH1 RK0: MR19=505, MR18=A1A
5742 00:24:32.860412 CH1_RK0: MR19=0x505, MR18=0xA1A, DQSOSC=413, MR23=63, INC=63, DEC=42
5743 00:24:32.860522
5744 00:24:32.864323 ----->DramcWriteLeveling(PI) begin...
5745 00:24:32.864414 ==
5746 00:24:32.867591 Dram Type= 6, Freq= 0, CH_1, rank 1
5747 00:24:32.870521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5748 00:24:32.870609 ==
5749 00:24:32.873675 Write leveling (Byte 0): 26 => 26
5750 00:24:32.876863 Write leveling (Byte 1): 27 => 27
5751 00:24:32.880065 DramcWriteLeveling(PI) end<-----
5752 00:24:32.880153
5753 00:24:32.880238 ==
5754 00:24:32.883505 Dram Type= 6, Freq= 0, CH_1, rank 1
5755 00:24:32.890361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5756 00:24:32.890456 ==
5757 00:24:32.890543 [Gating] SW mode calibration
5758 00:24:32.900426 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5759 00:24:32.903709 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5760 00:24:32.910379 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5761 00:24:32.913378 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5762 00:24:32.916514 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5763 00:24:32.923327 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5764 00:24:32.926670 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5765 00:24:32.929827 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5766 00:24:32.936019 0 14 24 | B1->B0 | 3333 2f2f | 0 0 | (0 0) (0 1)
5767 00:24:32.939529 0 14 28 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
5768 00:24:32.942779 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5769 00:24:32.949215 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5770 00:24:32.952474 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5771 00:24:32.955951 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5772 00:24:32.963012 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5773 00:24:32.966461 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5774 00:24:32.969273 0 15 24 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
5775 00:24:32.975986 0 15 28 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
5776 00:24:32.978899 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5777 00:24:32.982608 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5778 00:24:32.989280 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5779 00:24:32.992083 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5780 00:24:32.995639 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5781 00:24:33.002107 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5782 00:24:33.005616 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5783 00:24:33.008510 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 00:24:33.015174 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5785 00:24:33.018766 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 00:24:33.021834 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 00:24:33.028286 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 00:24:33.031775 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 00:24:33.035023 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 00:24:33.041422 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 00:24:33.044450 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5792 00:24:33.047981 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5793 00:24:33.054481 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5794 00:24:33.057931 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5795 00:24:33.061552 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5796 00:24:33.067476 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5797 00:24:33.070681 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 00:24:33.074436 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5799 00:24:33.080895 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5800 00:24:33.081002 Total UI for P1: 0, mck2ui 16
5801 00:24:33.087301 best dqsien dly found for B0: ( 1, 2, 24)
5802 00:24:33.090688 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5803 00:24:33.093993 Total UI for P1: 0, mck2ui 16
5804 00:24:33.097440 best dqsien dly found for B1: ( 1, 2, 26)
5805 00:24:33.100404 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5806 00:24:33.103580 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5807 00:24:33.103679
5808 00:24:33.107563 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5809 00:24:33.110186 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5810 00:24:33.114073 [Gating] SW calibration Done
5811 00:24:33.114166 ==
5812 00:24:33.117029 Dram Type= 6, Freq= 0, CH_1, rank 1
5813 00:24:33.123966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5814 00:24:33.124076 ==
5815 00:24:33.124147 RX Vref Scan: 0
5816 00:24:33.124208
5817 00:24:33.126772 RX Vref 0 -> 0, step: 1
5818 00:24:33.126855
5819 00:24:33.129897 RX Delay -80 -> 252, step: 8
5820 00:24:33.133572 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5821 00:24:33.136813 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5822 00:24:33.140139 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5823 00:24:33.143267 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5824 00:24:33.150409 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5825 00:24:33.152919 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5826 00:24:33.156489 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5827 00:24:33.159695 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5828 00:24:33.162928 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5829 00:24:33.169510 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5830 00:24:33.172852 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5831 00:24:33.176387 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5832 00:24:33.179514 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5833 00:24:33.182511 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5834 00:24:33.189251 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5835 00:24:33.192885 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5836 00:24:33.192984 ==
5837 00:24:33.196261 Dram Type= 6, Freq= 0, CH_1, rank 1
5838 00:24:33.199064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5839 00:24:33.199153 ==
5840 00:24:33.199218 DQS Delay:
5841 00:24:33.202211 DQS0 = 0, DQS1 = 0
5842 00:24:33.202294 DQM Delay:
5843 00:24:33.205435 DQM0 = 95, DQM1 = 94
5844 00:24:33.205526 DQ Delay:
5845 00:24:33.208717 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =95
5846 00:24:33.212208 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =91
5847 00:24:33.215414 DQ8 =79, DQ9 =83, DQ10 =95, DQ11 =87
5848 00:24:33.219015 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5849 00:24:33.219106
5850 00:24:33.219172
5851 00:24:33.219231 ==
5852 00:24:33.222956 Dram Type= 6, Freq= 0, CH_1, rank 1
5853 00:24:33.228703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5854 00:24:33.228799 ==
5855 00:24:33.228866
5856 00:24:33.228926
5857 00:24:33.228985 TX Vref Scan disable
5858 00:24:33.233043 == TX Byte 0 ==
5859 00:24:33.235727 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5860 00:24:33.242269 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5861 00:24:33.242395 == TX Byte 1 ==
5862 00:24:33.245469 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5863 00:24:33.252064 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5864 00:24:33.252161 ==
5865 00:24:33.255352 Dram Type= 6, Freq= 0, CH_1, rank 1
5866 00:24:33.258851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5867 00:24:33.258943 ==
5868 00:24:33.259008
5869 00:24:33.259068
5870 00:24:33.262025 TX Vref Scan disable
5871 00:24:33.262109 == TX Byte 0 ==
5872 00:24:33.268825 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5873 00:24:33.272061 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5874 00:24:33.275017 == TX Byte 1 ==
5875 00:24:33.278988 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5876 00:24:33.281815 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5877 00:24:33.281914
5878 00:24:33.281979 [DATLAT]
5879 00:24:33.285563 Freq=933, CH1 RK1
5880 00:24:33.285649
5881 00:24:33.288262 DATLAT Default: 0xb
5882 00:24:33.288346 0, 0xFFFF, sum = 0
5883 00:24:33.291482 1, 0xFFFF, sum = 0
5884 00:24:33.291569 2, 0xFFFF, sum = 0
5885 00:24:33.294919 3, 0xFFFF, sum = 0
5886 00:24:33.295006 4, 0xFFFF, sum = 0
5887 00:24:33.298034 5, 0xFFFF, sum = 0
5888 00:24:33.298124 6, 0xFFFF, sum = 0
5889 00:24:33.301591 7, 0xFFFF, sum = 0
5890 00:24:33.301713 8, 0xFFFF, sum = 0
5891 00:24:33.304713 9, 0xFFFF, sum = 0
5892 00:24:33.304801 10, 0x0, sum = 1
5893 00:24:33.307979 11, 0x0, sum = 2
5894 00:24:33.308068 12, 0x0, sum = 3
5895 00:24:33.311178 13, 0x0, sum = 4
5896 00:24:33.311266 best_step = 11
5897 00:24:33.311331
5898 00:24:33.311391 ==
5899 00:24:33.314733 Dram Type= 6, Freq= 0, CH_1, rank 1
5900 00:24:33.318193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5901 00:24:33.321727 ==
5902 00:24:33.321816 RX Vref Scan: 0
5903 00:24:33.321881
5904 00:24:33.324615 RX Vref 0 -> 0, step: 1
5905 00:24:33.324698
5906 00:24:33.327657 RX Delay -61 -> 252, step: 4
5907 00:24:33.330891 iDelay=199, Bit 0, Center 100 (11 ~ 190) 180
5908 00:24:33.334473 iDelay=199, Bit 1, Center 92 (-1 ~ 186) 188
5909 00:24:33.340732 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5910 00:24:33.344420 iDelay=199, Bit 3, Center 96 (7 ~ 186) 180
5911 00:24:33.347873 iDelay=199, Bit 4, Center 98 (7 ~ 190) 184
5912 00:24:33.350654 iDelay=199, Bit 5, Center 104 (11 ~ 198) 188
5913 00:24:33.354332 iDelay=199, Bit 6, Center 104 (15 ~ 194) 180
5914 00:24:33.357485 iDelay=199, Bit 7, Center 94 (3 ~ 186) 184
5915 00:24:33.364183 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5916 00:24:33.367227 iDelay=199, Bit 9, Center 82 (-5 ~ 170) 176
5917 00:24:33.371027 iDelay=199, Bit 10, Center 96 (7 ~ 186) 180
5918 00:24:33.373708 iDelay=199, Bit 11, Center 88 (-1 ~ 178) 180
5919 00:24:33.377718 iDelay=199, Bit 12, Center 102 (15 ~ 190) 176
5920 00:24:33.383932 iDelay=199, Bit 13, Center 100 (11 ~ 190) 180
5921 00:24:33.387025 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5922 00:24:33.390581 iDelay=199, Bit 15, Center 102 (11 ~ 194) 184
5923 00:24:33.390673 ==
5924 00:24:33.393436 Dram Type= 6, Freq= 0, CH_1, rank 1
5925 00:24:33.397074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5926 00:24:33.397162 ==
5927 00:24:33.399967 DQS Delay:
5928 00:24:33.400078 DQS0 = 0, DQS1 = 0
5929 00:24:33.403386 DQM Delay:
5930 00:24:33.403472 DQM0 = 96, DQM1 = 94
5931 00:24:33.407059 DQ Delay:
5932 00:24:33.407152 DQ0 =100, DQ1 =92, DQ2 =86, DQ3 =96
5933 00:24:33.410246 DQ4 =98, DQ5 =104, DQ6 =104, DQ7 =94
5934 00:24:33.413081 DQ8 =84, DQ9 =82, DQ10 =96, DQ11 =88
5935 00:24:33.419682 DQ12 =102, DQ13 =100, DQ14 =100, DQ15 =102
5936 00:24:33.419782
5937 00:24:33.419848
5938 00:24:33.427016 [DQSOSCAuto] RK1, (LSB)MR18= 0xc24, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 418 ps
5939 00:24:33.429929 CH1 RK1: MR19=505, MR18=C24
5940 00:24:33.436678 CH1_RK1: MR19=0x505, MR18=0xC24, DQSOSC=410, MR23=63, INC=64, DEC=42
5941 00:24:33.440408 [RxdqsGatingPostProcess] freq 933
5942 00:24:33.443500 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5943 00:24:33.446802 best DQS0 dly(2T, 0.5T) = (0, 10)
5944 00:24:33.449815 best DQS1 dly(2T, 0.5T) = (0, 10)
5945 00:24:33.453223 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5946 00:24:33.456864 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5947 00:24:33.460201 best DQS0 dly(2T, 0.5T) = (0, 10)
5948 00:24:33.462854 best DQS1 dly(2T, 0.5T) = (0, 10)
5949 00:24:33.466098 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5950 00:24:33.469994 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5951 00:24:33.472691 Pre-setting of DQS Precalculation
5952 00:24:33.476614 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5953 00:24:33.486219 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5954 00:24:33.493194 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5955 00:24:33.493350
5956 00:24:33.493417
5957 00:24:33.496015 [Calibration Summary] 1866 Mbps
5958 00:24:33.496099 CH 0, Rank 0
5959 00:24:33.499452 SW Impedance : PASS
5960 00:24:33.499537 DUTY Scan : NO K
5961 00:24:33.503031 ZQ Calibration : PASS
5962 00:24:33.506099 Jitter Meter : NO K
5963 00:24:33.506195 CBT Training : PASS
5964 00:24:33.509045 Write leveling : PASS
5965 00:24:33.512614 RX DQS gating : PASS
5966 00:24:33.512705 RX DQ/DQS(RDDQC) : PASS
5967 00:24:33.515989 TX DQ/DQS : PASS
5968 00:24:33.518972 RX DATLAT : PASS
5969 00:24:33.519059 RX DQ/DQS(Engine): PASS
5970 00:24:33.522666 TX OE : NO K
5971 00:24:33.522752 All Pass.
5972 00:24:33.522818
5973 00:24:33.526018 CH 0, Rank 1
5974 00:24:33.526103 SW Impedance : PASS
5975 00:24:33.528853 DUTY Scan : NO K
5976 00:24:33.532343 ZQ Calibration : PASS
5977 00:24:33.532432 Jitter Meter : NO K
5978 00:24:33.535903 CBT Training : PASS
5979 00:24:33.538884 Write leveling : PASS
5980 00:24:33.538974 RX DQS gating : PASS
5981 00:24:33.542398 RX DQ/DQS(RDDQC) : PASS
5982 00:24:33.545515 TX DQ/DQS : PASS
5983 00:24:33.545605 RX DATLAT : PASS
5984 00:24:33.548660 RX DQ/DQS(Engine): PASS
5985 00:24:33.548747 TX OE : NO K
5986 00:24:33.551848 All Pass.
5987 00:24:33.551932
5988 00:24:33.551996 CH 1, Rank 0
5989 00:24:33.555270 SW Impedance : PASS
5990 00:24:33.555353 DUTY Scan : NO K
5991 00:24:33.558512 ZQ Calibration : PASS
5992 00:24:33.561922 Jitter Meter : NO K
5993 00:24:33.562007 CBT Training : PASS
5994 00:24:33.565414 Write leveling : PASS
5995 00:24:33.568491 RX DQS gating : PASS
5996 00:24:33.568577 RX DQ/DQS(RDDQC) : PASS
5997 00:24:33.572444 TX DQ/DQS : PASS
5998 00:24:33.575155 RX DATLAT : PASS
5999 00:24:33.575241 RX DQ/DQS(Engine): PASS
6000 00:24:33.578254 TX OE : NO K
6001 00:24:33.578339 All Pass.
6002 00:24:33.578403
6003 00:24:33.581627 CH 1, Rank 1
6004 00:24:33.581711 SW Impedance : PASS
6005 00:24:33.585071 DUTY Scan : NO K
6006 00:24:33.588362 ZQ Calibration : PASS
6007 00:24:33.588447 Jitter Meter : NO K
6008 00:24:33.591466 CBT Training : PASS
6009 00:24:33.595213 Write leveling : PASS
6010 00:24:33.595304 RX DQS gating : PASS
6011 00:24:33.598259 RX DQ/DQS(RDDQC) : PASS
6012 00:24:33.601518 TX DQ/DQS : PASS
6013 00:24:33.601605 RX DATLAT : PASS
6014 00:24:33.604947 RX DQ/DQS(Engine): PASS
6015 00:24:33.608000 TX OE : NO K
6016 00:24:33.608092 All Pass.
6017 00:24:33.608180
6018 00:24:33.608259 DramC Write-DBI off
6019 00:24:33.611706 PER_BANK_REFRESH: Hybrid Mode
6020 00:24:33.615650 TX_TRACKING: ON
6021 00:24:33.621597 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6022 00:24:33.625068 [FAST_K] Save calibration result to emmc
6023 00:24:33.631072 dramc_set_vcore_voltage set vcore to 650000
6024 00:24:33.631214 Read voltage for 400, 6
6025 00:24:33.634471 Vio18 = 0
6026 00:24:33.634579 Vcore = 650000
6027 00:24:33.634648 Vdram = 0
6028 00:24:33.637566 Vddq = 0
6029 00:24:33.637730 Vmddr = 0
6030 00:24:33.641353 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6031 00:24:33.648209 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6032 00:24:33.651125 MEM_TYPE=3, freq_sel=20
6033 00:24:33.654246 sv_algorithm_assistance_LP4_800
6034 00:24:33.657588 ============ PULL DRAM RESETB DOWN ============
6035 00:24:33.660857 ========== PULL DRAM RESETB DOWN end =========
6036 00:24:33.663861 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6037 00:24:33.667484 ===================================
6038 00:24:33.670471 LPDDR4 DRAM CONFIGURATION
6039 00:24:33.673745 ===================================
6040 00:24:33.677031 EX_ROW_EN[0] = 0x0
6041 00:24:33.677158 EX_ROW_EN[1] = 0x0
6042 00:24:33.681054 LP4Y_EN = 0x0
6043 00:24:33.681144 WORK_FSP = 0x0
6044 00:24:33.683857 WL = 0x2
6045 00:24:33.683942 RL = 0x2
6046 00:24:33.687291 BL = 0x2
6047 00:24:33.690764 RPST = 0x0
6048 00:24:33.690888 RD_PRE = 0x0
6049 00:24:33.693946 WR_PRE = 0x1
6050 00:24:33.694101 WR_PST = 0x0
6051 00:24:33.697136 DBI_WR = 0x0
6052 00:24:33.697253 DBI_RD = 0x0
6053 00:24:33.700443 OTF = 0x1
6054 00:24:33.703652 ===================================
6055 00:24:33.706980 ===================================
6056 00:24:33.707107 ANA top config
6057 00:24:33.710261 ===================================
6058 00:24:33.713972 DLL_ASYNC_EN = 0
6059 00:24:33.716691 ALL_SLAVE_EN = 1
6060 00:24:33.716807 NEW_RANK_MODE = 1
6061 00:24:33.720138 DLL_IDLE_MODE = 1
6062 00:24:33.723437 LP45_APHY_COMB_EN = 1
6063 00:24:33.726557 TX_ODT_DIS = 1
6064 00:24:33.730313 NEW_8X_MODE = 1
6065 00:24:33.733667 ===================================
6066 00:24:33.736340 ===================================
6067 00:24:33.736495 data_rate = 800
6068 00:24:33.739923 CKR = 1
6069 00:24:33.743466 DQ_P2S_RATIO = 4
6070 00:24:33.746591 ===================================
6071 00:24:33.749964 CA_P2S_RATIO = 4
6072 00:24:33.753233 DQ_CA_OPEN = 0
6073 00:24:33.756167 DQ_SEMI_OPEN = 1
6074 00:24:33.756304 CA_SEMI_OPEN = 1
6075 00:24:33.759554 CA_FULL_RATE = 0
6076 00:24:33.762977 DQ_CKDIV4_EN = 0
6077 00:24:33.765971 CA_CKDIV4_EN = 1
6078 00:24:33.769614 CA_PREDIV_EN = 0
6079 00:24:33.772545 PH8_DLY = 0
6080 00:24:33.772677 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6081 00:24:33.776452 DQ_AAMCK_DIV = 0
6082 00:24:33.779433 CA_AAMCK_DIV = 0
6083 00:24:33.782834 CA_ADMCK_DIV = 4
6084 00:24:33.785746 DQ_TRACK_CA_EN = 0
6085 00:24:33.789853 CA_PICK = 800
6086 00:24:33.792242 CA_MCKIO = 400
6087 00:24:33.795882 MCKIO_SEMI = 400
6088 00:24:33.796009 PLL_FREQ = 3016
6089 00:24:33.799430 DQ_UI_PI_RATIO = 32
6090 00:24:33.802288 CA_UI_PI_RATIO = 32
6091 00:24:33.805550 ===================================
6092 00:24:33.809221 ===================================
6093 00:24:33.812228 memory_type:LPDDR4
6094 00:24:33.815444 GP_NUM : 10
6095 00:24:33.815581 SRAM_EN : 1
6096 00:24:33.819388 MD32_EN : 0
6097 00:24:33.822223 ===================================
6098 00:24:33.822339 [ANA_INIT] >>>>>>>>>>>>>>
6099 00:24:33.825448 <<<<<< [CONFIGURE PHASE]: ANA_TX
6100 00:24:33.828883 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6101 00:24:33.832235 ===================================
6102 00:24:33.835375 data_rate = 800,PCW = 0X7400
6103 00:24:33.838583 ===================================
6104 00:24:33.842269 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6105 00:24:33.848790 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6106 00:24:33.858979 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6107 00:24:33.865384 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6108 00:24:33.868455 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6109 00:24:33.872192 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6110 00:24:33.872290 [ANA_INIT] flow start
6111 00:24:33.875094 [ANA_INIT] PLL >>>>>>>>
6112 00:24:33.878430 [ANA_INIT] PLL <<<<<<<<
6113 00:24:33.878529 [ANA_INIT] MIDPI >>>>>>>>
6114 00:24:33.882268 [ANA_INIT] MIDPI <<<<<<<<
6115 00:24:33.885239 [ANA_INIT] DLL >>>>>>>>
6116 00:24:33.885365 [ANA_INIT] flow end
6117 00:24:33.891562 ============ LP4 DIFF to SE enter ============
6118 00:24:33.894954 ============ LP4 DIFF to SE exit ============
6119 00:24:33.898082 [ANA_INIT] <<<<<<<<<<<<<
6120 00:24:33.901566 [Flow] Enable top DCM control >>>>>
6121 00:24:33.904823 [Flow] Enable top DCM control <<<<<
6122 00:24:33.908479 Enable DLL master slave shuffle
6123 00:24:33.911518 ==============================================================
6124 00:24:33.914940 Gating Mode config
6125 00:24:33.918165 ==============================================================
6126 00:24:33.921668 Config description:
6127 00:24:33.931108 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6128 00:24:33.937969 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6129 00:24:33.941176 SELPH_MODE 0: By rank 1: By Phase
6130 00:24:33.948054 ==============================================================
6131 00:24:33.950830 GAT_TRACK_EN = 0
6132 00:24:33.954200 RX_GATING_MODE = 2
6133 00:24:33.957723 RX_GATING_TRACK_MODE = 2
6134 00:24:33.961031 SELPH_MODE = 1
6135 00:24:33.964576 PICG_EARLY_EN = 1
6136 00:24:33.967707 VALID_LAT_VALUE = 1
6137 00:24:33.970885 ==============================================================
6138 00:24:33.974327 Enter into Gating configuration >>>>
6139 00:24:33.977400 Exit from Gating configuration <<<<
6140 00:24:33.980639 Enter into DVFS_PRE_config >>>>>
6141 00:24:33.993834 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6142 00:24:33.994044 Exit from DVFS_PRE_config <<<<<
6143 00:24:33.997467 Enter into PICG configuration >>>>
6144 00:24:34.000477 Exit from PICG configuration <<<<
6145 00:24:34.004102 [RX_INPUT] configuration >>>>>
6146 00:24:34.007229 [RX_INPUT] configuration <<<<<
6147 00:24:34.013315 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6148 00:24:34.016957 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6149 00:24:34.023486 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6150 00:24:34.030153 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6151 00:24:34.036627 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6152 00:24:34.043612 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6153 00:24:34.046446 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6154 00:24:34.049725 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6155 00:24:34.053032 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6156 00:24:34.059887 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6157 00:24:34.063271 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6158 00:24:34.066341 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6159 00:24:34.069798 ===================================
6160 00:24:34.072911 LPDDR4 DRAM CONFIGURATION
6161 00:24:34.075985 ===================================
6162 00:24:34.079331 EX_ROW_EN[0] = 0x0
6163 00:24:34.079489 EX_ROW_EN[1] = 0x0
6164 00:24:34.082765 LP4Y_EN = 0x0
6165 00:24:34.082909 WORK_FSP = 0x0
6166 00:24:34.086215 WL = 0x2
6167 00:24:34.086362 RL = 0x2
6168 00:24:34.089539 BL = 0x2
6169 00:24:34.089675 RPST = 0x0
6170 00:24:34.093103 RD_PRE = 0x0
6171 00:24:34.093253 WR_PRE = 0x1
6172 00:24:34.096082 WR_PST = 0x0
6173 00:24:34.099241 DBI_WR = 0x0
6174 00:24:34.099395 DBI_RD = 0x0
6175 00:24:34.102375 OTF = 0x1
6176 00:24:34.105913 ===================================
6177 00:24:34.109162 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6178 00:24:34.112180 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6179 00:24:34.116101 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6180 00:24:34.119211 ===================================
6181 00:24:34.122371 LPDDR4 DRAM CONFIGURATION
6182 00:24:34.125673 ===================================
6183 00:24:34.129023 EX_ROW_EN[0] = 0x10
6184 00:24:34.129170 EX_ROW_EN[1] = 0x0
6185 00:24:34.132349 LP4Y_EN = 0x0
6186 00:24:34.132471 WORK_FSP = 0x0
6187 00:24:34.135726 WL = 0x2
6188 00:24:34.135861 RL = 0x2
6189 00:24:34.139272 BL = 0x2
6190 00:24:34.139420 RPST = 0x0
6191 00:24:34.142352 RD_PRE = 0x0
6192 00:24:34.145163 WR_PRE = 0x1
6193 00:24:34.145347 WR_PST = 0x0
6194 00:24:34.149087 DBI_WR = 0x0
6195 00:24:34.149243 DBI_RD = 0x0
6196 00:24:34.152370 OTF = 0x1
6197 00:24:34.155736 ===================================
6198 00:24:34.158422 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6199 00:24:34.163890 nWR fixed to 30
6200 00:24:34.167384 [ModeRegInit_LP4] CH0 RK0
6201 00:24:34.167548 [ModeRegInit_LP4] CH0 RK1
6202 00:24:34.170758 [ModeRegInit_LP4] CH1 RK0
6203 00:24:34.174305 [ModeRegInit_LP4] CH1 RK1
6204 00:24:34.174463 match AC timing 19
6205 00:24:34.180833 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6206 00:24:34.184229 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6207 00:24:34.187205 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6208 00:24:34.193488 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6209 00:24:34.196879 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6210 00:24:34.196982 ==
6211 00:24:34.200154 Dram Type= 6, Freq= 0, CH_0, rank 0
6212 00:24:34.203991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6213 00:24:34.204086 ==
6214 00:24:34.210121 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6215 00:24:34.216827 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6216 00:24:34.219891 [CA 0] Center 36 (8~64) winsize 57
6217 00:24:34.223589 [CA 1] Center 36 (8~64) winsize 57
6218 00:24:34.226496 [CA 2] Center 36 (8~64) winsize 57
6219 00:24:34.229697 [CA 3] Center 36 (8~64) winsize 57
6220 00:24:34.233285 [CA 4] Center 36 (8~64) winsize 57
6221 00:24:34.236427 [CA 5] Center 36 (8~64) winsize 57
6222 00:24:34.236523
6223 00:24:34.240155 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6224 00:24:34.240244
6225 00:24:34.243174 [CATrainingPosCal] consider 1 rank data
6226 00:24:34.246382 u2DelayCellTimex100 = 270/100 ps
6227 00:24:34.249816 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6228 00:24:34.252834 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6229 00:24:34.256581 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6230 00:24:34.260124 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6231 00:24:34.263212 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6232 00:24:34.265998 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6233 00:24:34.266087
6234 00:24:34.272848 CA PerBit enable=1, Macro0, CA PI delay=36
6235 00:24:34.272952
6236 00:24:34.273021 [CBTSetCACLKResult] CA Dly = 36
6237 00:24:34.276147 CS Dly: 1 (0~32)
6238 00:24:34.276232 ==
6239 00:24:34.279341 Dram Type= 6, Freq= 0, CH_0, rank 1
6240 00:24:34.282511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6241 00:24:34.282598 ==
6242 00:24:34.288902 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6243 00:24:34.295690 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6244 00:24:34.299080 [CA 0] Center 36 (8~64) winsize 57
6245 00:24:34.302413 [CA 1] Center 36 (8~64) winsize 57
6246 00:24:34.305606 [CA 2] Center 36 (8~64) winsize 57
6247 00:24:34.309113 [CA 3] Center 36 (8~64) winsize 57
6248 00:24:34.309209 [CA 4] Center 36 (8~64) winsize 57
6249 00:24:34.312370 [CA 5] Center 36 (8~64) winsize 57
6250 00:24:34.312459
6251 00:24:34.318680 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6252 00:24:34.318784
6253 00:24:34.322490 [CATrainingPosCal] consider 2 rank data
6254 00:24:34.325175 u2DelayCellTimex100 = 270/100 ps
6255 00:24:34.328878 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6256 00:24:34.332757 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6257 00:24:34.335430 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6258 00:24:34.338333 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6259 00:24:34.342209 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6260 00:24:34.345156 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6261 00:24:34.345251
6262 00:24:34.348530 CA PerBit enable=1, Macro0, CA PI delay=36
6263 00:24:34.348621
6264 00:24:34.351755 [CBTSetCACLKResult] CA Dly = 36
6265 00:24:34.355049 CS Dly: 1 (0~32)
6266 00:24:34.355154
6267 00:24:34.358284 ----->DramcWriteLeveling(PI) begin...
6268 00:24:34.358373 ==
6269 00:24:34.361893 Dram Type= 6, Freq= 0, CH_0, rank 0
6270 00:24:34.364609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6271 00:24:34.364696 ==
6272 00:24:34.368269 Write leveling (Byte 0): 40 => 8
6273 00:24:34.371748 Write leveling (Byte 1): 40 => 8
6274 00:24:34.374995 DramcWriteLeveling(PI) end<-----
6275 00:24:34.375088
6276 00:24:34.375153 ==
6277 00:24:34.378025 Dram Type= 6, Freq= 0, CH_0, rank 0
6278 00:24:34.381671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6279 00:24:34.381760 ==
6280 00:24:34.384718 [Gating] SW mode calibration
6281 00:24:34.391284 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6282 00:24:34.397716 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6283 00:24:34.401218 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6284 00:24:34.407532 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6285 00:24:34.410804 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6286 00:24:34.414432 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6287 00:24:34.420833 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6288 00:24:34.424590 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6289 00:24:34.427690 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6290 00:24:34.433539 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6291 00:24:34.437179 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6292 00:24:34.440423 Total UI for P1: 0, mck2ui 16
6293 00:24:34.444111 best dqsien dly found for B0: ( 0, 14, 24)
6294 00:24:34.447171 Total UI for P1: 0, mck2ui 16
6295 00:24:34.450391 best dqsien dly found for B1: ( 0, 14, 24)
6296 00:24:34.453503 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6297 00:24:34.456679 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6298 00:24:34.456772
6299 00:24:34.459961 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6300 00:24:34.466658 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6301 00:24:34.466764 [Gating] SW calibration Done
6302 00:24:34.469584 ==
6303 00:24:34.469670 Dram Type= 6, Freq= 0, CH_0, rank 0
6304 00:24:34.476803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6305 00:24:34.476910 ==
6306 00:24:34.476977 RX Vref Scan: 0
6307 00:24:34.477038
6308 00:24:34.479788 RX Vref 0 -> 0, step: 1
6309 00:24:34.479872
6310 00:24:34.483273 RX Delay -410 -> 252, step: 16
6311 00:24:34.486786 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6312 00:24:34.489908 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6313 00:24:34.496384 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6314 00:24:34.499580 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6315 00:24:34.503015 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6316 00:24:34.506487 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6317 00:24:34.512807 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6318 00:24:34.516563 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6319 00:24:34.520363 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6320 00:24:34.522683 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6321 00:24:34.529223 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6322 00:24:34.533031 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6323 00:24:34.536161 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6324 00:24:34.542785 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6325 00:24:34.545881 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6326 00:24:34.549127 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6327 00:24:34.549220 ==
6328 00:24:34.552303 Dram Type= 6, Freq= 0, CH_0, rank 0
6329 00:24:34.558951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6330 00:24:34.559073 ==
6331 00:24:34.559145 DQS Delay:
6332 00:24:34.562429 DQS0 = 35, DQS1 = 51
6333 00:24:34.562519 DQM Delay:
6334 00:24:34.562584 DQM0 = 5, DQM1 = 10
6335 00:24:34.565367 DQ Delay:
6336 00:24:34.565454 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6337 00:24:34.568565 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6338 00:24:34.572212 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6339 00:24:34.575665 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6340 00:24:34.575757
6341 00:24:34.575822
6342 00:24:34.578819 ==
6343 00:24:34.578908 Dram Type= 6, Freq= 0, CH_0, rank 0
6344 00:24:34.585537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6345 00:24:34.585640 ==
6346 00:24:34.585706
6347 00:24:34.585766
6348 00:24:34.589367 TX Vref Scan disable
6349 00:24:34.589453 == TX Byte 0 ==
6350 00:24:34.592073 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6351 00:24:34.598590 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6352 00:24:34.598694 == TX Byte 1 ==
6353 00:24:34.601608 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6354 00:24:34.608412 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6355 00:24:34.608528 ==
6356 00:24:34.611243 Dram Type= 6, Freq= 0, CH_0, rank 0
6357 00:24:34.614779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6358 00:24:34.614869 ==
6359 00:24:34.614934
6360 00:24:34.614993
6361 00:24:34.617979 TX Vref Scan disable
6362 00:24:34.618063 == TX Byte 0 ==
6363 00:24:34.621461 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6364 00:24:34.628391 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6365 00:24:34.628500 == TX Byte 1 ==
6366 00:24:34.631419 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6367 00:24:34.638185 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6368 00:24:34.638305
6369 00:24:34.638373 [DATLAT]
6370 00:24:34.638432 Freq=400, CH0 RK0
6371 00:24:34.641330
6372 00:24:34.641415 DATLAT Default: 0xf
6373 00:24:34.644398 0, 0xFFFF, sum = 0
6374 00:24:34.644482 1, 0xFFFF, sum = 0
6375 00:24:34.647843 2, 0xFFFF, sum = 0
6376 00:24:34.647929 3, 0xFFFF, sum = 0
6377 00:24:34.651167 4, 0xFFFF, sum = 0
6378 00:24:34.651250 5, 0xFFFF, sum = 0
6379 00:24:34.654123 6, 0xFFFF, sum = 0
6380 00:24:34.654208 7, 0xFFFF, sum = 0
6381 00:24:34.657510 8, 0xFFFF, sum = 0
6382 00:24:34.657598 9, 0xFFFF, sum = 0
6383 00:24:34.660761 10, 0xFFFF, sum = 0
6384 00:24:34.660856 11, 0xFFFF, sum = 0
6385 00:24:34.664154 12, 0xFFFF, sum = 0
6386 00:24:34.664244 13, 0x0, sum = 1
6387 00:24:34.667261 14, 0x0, sum = 2
6388 00:24:34.667347 15, 0x0, sum = 3
6389 00:24:34.671272 16, 0x0, sum = 4
6390 00:24:34.671358 best_step = 14
6391 00:24:34.671422
6392 00:24:34.671482 ==
6393 00:24:34.673960 Dram Type= 6, Freq= 0, CH_0, rank 0
6394 00:24:34.680560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6395 00:24:34.680652 ==
6396 00:24:34.680717 RX Vref Scan: 1
6397 00:24:34.680777
6398 00:24:34.683619 RX Vref 0 -> 0, step: 1
6399 00:24:34.683709
6400 00:24:34.686924 RX Delay -343 -> 252, step: 8
6401 00:24:34.687008
6402 00:24:34.690398 Set Vref, RX VrefLevel [Byte0]: 57
6403 00:24:34.693518 [Byte1]: 50
6404 00:24:34.697012
6405 00:24:34.697104 Final RX Vref Byte 0 = 57 to rank0
6406 00:24:34.700520 Final RX Vref Byte 1 = 50 to rank0
6407 00:24:34.703999 Final RX Vref Byte 0 = 57 to rank1
6408 00:24:34.707226 Final RX Vref Byte 1 = 50 to rank1==
6409 00:24:34.710619 Dram Type= 6, Freq= 0, CH_0, rank 0
6410 00:24:34.717083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6411 00:24:34.717218 ==
6412 00:24:34.717356 DQS Delay:
6413 00:24:34.720240 DQS0 = 44, DQS1 = 60
6414 00:24:34.720348 DQM Delay:
6415 00:24:34.720441 DQM0 = 10, DQM1 = 17
6416 00:24:34.723630 DQ Delay:
6417 00:24:34.727299 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =4
6418 00:24:34.730087 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6419 00:24:34.730204 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =12
6420 00:24:34.737155 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =24
6421 00:24:34.737333
6422 00:24:34.737432
6423 00:24:34.743653 [DQSOSCAuto] RK0, (LSB)MR18= 0x9c90, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 390 ps
6424 00:24:34.747152 CH0 RK0: MR19=C0C, MR18=9C90
6425 00:24:34.753543 CH0_RK0: MR19=0xC0C, MR18=0x9C90, DQSOSC=390, MR23=63, INC=388, DEC=258
6426 00:24:34.753696 ==
6427 00:24:34.756777 Dram Type= 6, Freq= 0, CH_0, rank 1
6428 00:24:34.759844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6429 00:24:34.759958 ==
6430 00:24:34.763243 [Gating] SW mode calibration
6431 00:24:34.770048 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6432 00:24:34.776531 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6433 00:24:34.779858 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6434 00:24:34.783193 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6435 00:24:34.789575 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6436 00:24:34.792974 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6437 00:24:34.796466 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6438 00:24:34.802532 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6439 00:24:34.805962 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6440 00:24:34.809223 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6441 00:24:34.816163 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6442 00:24:34.819585 Total UI for P1: 0, mck2ui 16
6443 00:24:34.822868 best dqsien dly found for B0: ( 0, 14, 24)
6444 00:24:34.822989 Total UI for P1: 0, mck2ui 16
6445 00:24:34.828983 best dqsien dly found for B1: ( 0, 14, 24)
6446 00:24:34.832493 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6447 00:24:34.835934 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6448 00:24:34.836054
6449 00:24:34.839270 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6450 00:24:34.842778 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6451 00:24:34.845846 [Gating] SW calibration Done
6452 00:24:34.845960 ==
6453 00:24:34.849146 Dram Type= 6, Freq= 0, CH_0, rank 1
6454 00:24:34.852422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6455 00:24:34.852518 ==
6456 00:24:34.855450 RX Vref Scan: 0
6457 00:24:34.855534
6458 00:24:34.858854 RX Vref 0 -> 0, step: 1
6459 00:24:34.858948
6460 00:24:34.859013 RX Delay -410 -> 252, step: 16
6461 00:24:34.865566 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6462 00:24:34.868722 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6463 00:24:34.872195 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6464 00:24:34.878911 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6465 00:24:34.882357 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6466 00:24:34.885498 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6467 00:24:34.888533 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6468 00:24:34.895444 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6469 00:24:34.898640 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6470 00:24:34.901853 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6471 00:24:34.905561 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6472 00:24:34.912209 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6473 00:24:34.915148 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6474 00:24:34.918290 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6475 00:24:34.921653 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6476 00:24:34.928423 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6477 00:24:34.928539 ==
6478 00:24:34.931604 Dram Type= 6, Freq= 0, CH_0, rank 1
6479 00:24:34.934665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6480 00:24:34.934757 ==
6481 00:24:34.934822 DQS Delay:
6482 00:24:34.938034 DQS0 = 35, DQS1 = 59
6483 00:24:34.938120 DQM Delay:
6484 00:24:34.941682 DQM0 = 6, DQM1 = 17
6485 00:24:34.941768 DQ Delay:
6486 00:24:34.944932 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6487 00:24:34.948278 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6488 00:24:34.951504 DQ8 =8, DQ9 =0, DQ10 =24, DQ11 =8
6489 00:24:34.954683 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6490 00:24:34.954774
6491 00:24:34.954837
6492 00:24:34.954896 ==
6493 00:24:34.957886 Dram Type= 6, Freq= 0, CH_0, rank 1
6494 00:24:34.961315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6495 00:24:34.961414 ==
6496 00:24:34.961480
6497 00:24:34.961539
6498 00:24:34.964577 TX Vref Scan disable
6499 00:24:34.968206 == TX Byte 0 ==
6500 00:24:34.971398 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6501 00:24:34.974767 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6502 00:24:34.977811 == TX Byte 1 ==
6503 00:24:34.981300 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6504 00:24:34.984999 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6505 00:24:34.985100 ==
6506 00:24:34.987670 Dram Type= 6, Freq= 0, CH_0, rank 1
6507 00:24:34.991037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6508 00:24:34.991130 ==
6509 00:24:34.991196
6510 00:24:34.994285
6511 00:24:34.994373 TX Vref Scan disable
6512 00:24:34.997863 == TX Byte 0 ==
6513 00:24:35.000958 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6514 00:24:35.004325 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6515 00:24:35.007409 == TX Byte 1 ==
6516 00:24:35.010815 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6517 00:24:35.014137 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6518 00:24:35.014242
6519 00:24:35.014310 [DATLAT]
6520 00:24:35.017500 Freq=400, CH0 RK1
6521 00:24:35.017587
6522 00:24:35.020718 DATLAT Default: 0xe
6523 00:24:35.020811 0, 0xFFFF, sum = 0
6524 00:24:35.023839 1, 0xFFFF, sum = 0
6525 00:24:35.023928 2, 0xFFFF, sum = 0
6526 00:24:35.027165 3, 0xFFFF, sum = 0
6527 00:24:35.027255 4, 0xFFFF, sum = 0
6528 00:24:35.030401 5, 0xFFFF, sum = 0
6529 00:24:35.030488 6, 0xFFFF, sum = 0
6530 00:24:35.033839 7, 0xFFFF, sum = 0
6531 00:24:35.033929 8, 0xFFFF, sum = 0
6532 00:24:35.036864 9, 0xFFFF, sum = 0
6533 00:24:35.036953 10, 0xFFFF, sum = 0
6534 00:24:35.040246 11, 0xFFFF, sum = 0
6535 00:24:35.040338 12, 0xFFFF, sum = 0
6536 00:24:35.043449 13, 0x0, sum = 1
6537 00:24:35.043537 14, 0x0, sum = 2
6538 00:24:35.047194 15, 0x0, sum = 3
6539 00:24:35.047282 16, 0x0, sum = 4
6540 00:24:35.050524 best_step = 14
6541 00:24:35.050610
6542 00:24:35.050676 ==
6543 00:24:35.053184 Dram Type= 6, Freq= 0, CH_0, rank 1
6544 00:24:35.056788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6545 00:24:35.056878 ==
6546 00:24:35.060212 RX Vref Scan: 0
6547 00:24:35.060309
6548 00:24:35.060375 RX Vref 0 -> 0, step: 1
6549 00:24:35.060435
6550 00:24:35.063151 RX Delay -359 -> 252, step: 8
6551 00:24:35.071568 iDelay=217, Bit 0, Center -36 (-271 ~ 200) 472
6552 00:24:35.074707 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6553 00:24:35.077781 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6554 00:24:35.084675 iDelay=217, Bit 3, Center -40 (-279 ~ 200) 480
6555 00:24:35.087981 iDelay=217, Bit 4, Center -32 (-271 ~ 208) 480
6556 00:24:35.091274 iDelay=217, Bit 5, Center -40 (-279 ~ 200) 480
6557 00:24:35.094525 iDelay=217, Bit 6, Center -24 (-263 ~ 216) 480
6558 00:24:35.101581 iDelay=217, Bit 7, Center -28 (-263 ~ 208) 472
6559 00:24:35.104350 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6560 00:24:35.107672 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6561 00:24:35.111360 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6562 00:24:35.117493 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6563 00:24:35.121058 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6564 00:24:35.123837 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6565 00:24:35.131076 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6566 00:24:35.134347 iDelay=217, Bit 15, Center -40 (-279 ~ 200) 480
6567 00:24:35.134449 ==
6568 00:24:35.137280 Dram Type= 6, Freq= 0, CH_0, rank 1
6569 00:24:35.140736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6570 00:24:35.140860 ==
6571 00:24:35.143850 DQS Delay:
6572 00:24:35.143978 DQS0 = 40, DQS1 = 60
6573 00:24:35.144075 DQM Delay:
6574 00:24:35.147139 DQM0 = 6, DQM1 = 14
6575 00:24:35.147244 DQ Delay:
6576 00:24:35.150282 DQ0 =4, DQ1 =8, DQ2 =0, DQ3 =0
6577 00:24:35.153847 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =12
6578 00:24:35.157240 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6579 00:24:35.160422 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =20
6580 00:24:35.160518
6581 00:24:35.160601
6582 00:24:35.169966 [DQSOSCAuto] RK1, (LSB)MR18= 0x8780, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
6583 00:24:35.170094 CH0 RK1: MR19=C0C, MR18=8780
6584 00:24:35.176849 CH0_RK1: MR19=0xC0C, MR18=0x8780, DQSOSC=392, MR23=63, INC=384, DEC=256
6585 00:24:35.180334 [RxdqsGatingPostProcess] freq 400
6586 00:24:35.186870 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6587 00:24:35.189808 best DQS0 dly(2T, 0.5T) = (0, 10)
6588 00:24:35.193451 best DQS1 dly(2T, 0.5T) = (0, 10)
6589 00:24:35.196672 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6590 00:24:35.199706 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6591 00:24:35.202968 best DQS0 dly(2T, 0.5T) = (0, 10)
6592 00:24:35.203060 best DQS1 dly(2T, 0.5T) = (0, 10)
6593 00:24:35.206551 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6594 00:24:35.209671 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6595 00:24:35.213317 Pre-setting of DQS Precalculation
6596 00:24:35.220287 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6597 00:24:35.220396 ==
6598 00:24:35.222786 Dram Type= 6, Freq= 0, CH_1, rank 0
6599 00:24:35.226417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6600 00:24:35.226530 ==
6601 00:24:35.232530 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6602 00:24:35.239692 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6603 00:24:35.242679 [CA 0] Center 36 (8~64) winsize 57
6604 00:24:35.245946 [CA 1] Center 36 (8~64) winsize 57
6605 00:24:35.249299 [CA 2] Center 36 (8~64) winsize 57
6606 00:24:35.252332 [CA 3] Center 36 (8~64) winsize 57
6607 00:24:35.252424 [CA 4] Center 36 (8~64) winsize 57
6608 00:24:35.255728 [CA 5] Center 36 (8~64) winsize 57
6609 00:24:35.255814
6610 00:24:35.262618 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6611 00:24:35.262721
6612 00:24:35.265399 [CATrainingPosCal] consider 1 rank data
6613 00:24:35.268590 u2DelayCellTimex100 = 270/100 ps
6614 00:24:35.271826 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6615 00:24:35.275431 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6616 00:24:35.278751 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6617 00:24:35.282089 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6618 00:24:35.284947 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6619 00:24:35.288487 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6620 00:24:35.288577
6621 00:24:35.291754 CA PerBit enable=1, Macro0, CA PI delay=36
6622 00:24:35.294903
6623 00:24:35.294989 [CBTSetCACLKResult] CA Dly = 36
6624 00:24:35.298404 CS Dly: 1 (0~32)
6625 00:24:35.298487 ==
6626 00:24:35.301798 Dram Type= 6, Freq= 0, CH_1, rank 1
6627 00:24:35.305163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6628 00:24:35.305291 ==
6629 00:24:35.311874 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6630 00:24:35.318483 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6631 00:24:35.321309 [CA 0] Center 36 (8~64) winsize 57
6632 00:24:35.324785 [CA 1] Center 36 (8~64) winsize 57
6633 00:24:35.328378 [CA 2] Center 36 (8~64) winsize 57
6634 00:24:35.328466 [CA 3] Center 36 (8~64) winsize 57
6635 00:24:35.331272 [CA 4] Center 36 (8~64) winsize 57
6636 00:24:35.334749 [CA 5] Center 36 (8~64) winsize 57
6637 00:24:35.334835
6638 00:24:35.341125 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6639 00:24:35.341231
6640 00:24:35.344389 [CATrainingPosCal] consider 2 rank data
6641 00:24:35.347889 u2DelayCellTimex100 = 270/100 ps
6642 00:24:35.351133 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6643 00:24:35.354550 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6644 00:24:35.358159 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6645 00:24:35.361234 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6646 00:24:35.364298 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6647 00:24:35.367646 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6648 00:24:35.367736
6649 00:24:35.370988 CA PerBit enable=1, Macro0, CA PI delay=36
6650 00:24:35.371092
6651 00:24:35.374652 [CBTSetCACLKResult] CA Dly = 36
6652 00:24:35.377895 CS Dly: 1 (0~32)
6653 00:24:35.377981
6654 00:24:35.380759 ----->DramcWriteLeveling(PI) begin...
6655 00:24:35.380843 ==
6656 00:24:35.384027 Dram Type= 6, Freq= 0, CH_1, rank 0
6657 00:24:35.387519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6658 00:24:35.387607 ==
6659 00:24:35.390995 Write leveling (Byte 0): 40 => 8
6660 00:24:35.394201 Write leveling (Byte 1): 40 => 8
6661 00:24:35.397665 DramcWriteLeveling(PI) end<-----
6662 00:24:35.397752
6663 00:24:35.397816 ==
6664 00:24:35.400774 Dram Type= 6, Freq= 0, CH_1, rank 0
6665 00:24:35.404058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6666 00:24:35.404145 ==
6667 00:24:35.407052 [Gating] SW mode calibration
6668 00:24:35.414395 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6669 00:24:35.420911 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6670 00:24:35.423636 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6671 00:24:35.430257 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6672 00:24:35.433792 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6673 00:24:35.436858 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6674 00:24:35.443570 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6675 00:24:35.446741 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6676 00:24:35.450209 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6677 00:24:35.456640 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6678 00:24:35.460501 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6679 00:24:35.462991 Total UI for P1: 0, mck2ui 16
6680 00:24:35.466368 best dqsien dly found for B0: ( 0, 14, 24)
6681 00:24:35.469635 Total UI for P1: 0, mck2ui 16
6682 00:24:35.472977 best dqsien dly found for B1: ( 0, 14, 24)
6683 00:24:35.476147 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6684 00:24:35.479600 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6685 00:24:35.479687
6686 00:24:35.483145 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6687 00:24:35.486137 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6688 00:24:35.489472 [Gating] SW calibration Done
6689 00:24:35.489557 ==
6690 00:24:35.492931 Dram Type= 6, Freq= 0, CH_1, rank 0
6691 00:24:35.499635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6692 00:24:35.499737 ==
6693 00:24:35.499804 RX Vref Scan: 0
6694 00:24:35.499863
6695 00:24:35.502493 RX Vref 0 -> 0, step: 1
6696 00:24:35.502575
6697 00:24:35.505764 RX Delay -410 -> 252, step: 16
6698 00:24:35.509255 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6699 00:24:35.512838 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6700 00:24:35.516283 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6701 00:24:35.522256 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6702 00:24:35.526276 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6703 00:24:35.529180 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6704 00:24:35.535448 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6705 00:24:35.538833 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6706 00:24:35.542383 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6707 00:24:35.545409 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6708 00:24:35.552507 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6709 00:24:35.555487 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6710 00:24:35.558741 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6711 00:24:35.561930 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6712 00:24:35.568434 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6713 00:24:35.571637 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6714 00:24:35.571753 ==
6715 00:24:35.575000 Dram Type= 6, Freq= 0, CH_1, rank 0
6716 00:24:35.578793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6717 00:24:35.578882 ==
6718 00:24:35.581663 DQS Delay:
6719 00:24:35.581745 DQS0 = 35, DQS1 = 51
6720 00:24:35.585037 DQM Delay:
6721 00:24:35.585119 DQM0 = 6, DQM1 = 13
6722 00:24:35.585182 DQ Delay:
6723 00:24:35.588277 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6724 00:24:35.591722 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6725 00:24:35.594963 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6726 00:24:35.598283 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6727 00:24:35.598367
6728 00:24:35.598431
6729 00:24:35.598489 ==
6730 00:24:35.601539 Dram Type= 6, Freq= 0, CH_1, rank 0
6731 00:24:35.607878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6732 00:24:35.607974 ==
6733 00:24:35.608039
6734 00:24:35.608097
6735 00:24:35.608152 TX Vref Scan disable
6736 00:24:35.611264 == TX Byte 0 ==
6737 00:24:35.614656 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6738 00:24:35.618137 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6739 00:24:35.621104 == TX Byte 1 ==
6740 00:24:35.624516 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6741 00:24:35.628320 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6742 00:24:35.628408 ==
6743 00:24:35.631160 Dram Type= 6, Freq= 0, CH_1, rank 0
6744 00:24:35.638344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6745 00:24:35.638469 ==
6746 00:24:35.638538
6747 00:24:35.638598
6748 00:24:35.641047 TX Vref Scan disable
6749 00:24:35.641136 == TX Byte 0 ==
6750 00:24:35.645156 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6751 00:24:35.647924 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6752 00:24:35.650901 == TX Byte 1 ==
6753 00:24:35.654610 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6754 00:24:35.657413 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6755 00:24:35.660867
6756 00:24:35.660954 [DATLAT]
6757 00:24:35.661017 Freq=400, CH1 RK0
6758 00:24:35.661076
6759 00:24:35.664377 DATLAT Default: 0xf
6760 00:24:35.664461 0, 0xFFFF, sum = 0
6761 00:24:35.667562 1, 0xFFFF, sum = 0
6762 00:24:35.667647 2, 0xFFFF, sum = 0
6763 00:24:35.670659 3, 0xFFFF, sum = 0
6764 00:24:35.674492 4, 0xFFFF, sum = 0
6765 00:24:35.674581 5, 0xFFFF, sum = 0
6766 00:24:35.677312 6, 0xFFFF, sum = 0
6767 00:24:35.677397 7, 0xFFFF, sum = 0
6768 00:24:35.680821 8, 0xFFFF, sum = 0
6769 00:24:35.680907 9, 0xFFFF, sum = 0
6770 00:24:35.684004 10, 0xFFFF, sum = 0
6771 00:24:35.684089 11, 0xFFFF, sum = 0
6772 00:24:35.687128 12, 0xFFFF, sum = 0
6773 00:24:35.687212 13, 0x0, sum = 1
6774 00:24:35.690663 14, 0x0, sum = 2
6775 00:24:35.690749 15, 0x0, sum = 3
6776 00:24:35.694165 16, 0x0, sum = 4
6777 00:24:35.694251 best_step = 14
6778 00:24:35.694316
6779 00:24:35.694375 ==
6780 00:24:35.697397 Dram Type= 6, Freq= 0, CH_1, rank 0
6781 00:24:35.700263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6782 00:24:35.703695 ==
6783 00:24:35.703780 RX Vref Scan: 1
6784 00:24:35.703843
6785 00:24:35.707030 RX Vref 0 -> 0, step: 1
6786 00:24:35.707113
6787 00:24:35.710455 RX Delay -343 -> 252, step: 8
6788 00:24:35.710543
6789 00:24:35.713763 Set Vref, RX VrefLevel [Byte0]: 49
6790 00:24:35.717196 [Byte1]: 52
6791 00:24:35.717343
6792 00:24:35.720277 Final RX Vref Byte 0 = 49 to rank0
6793 00:24:35.723727 Final RX Vref Byte 1 = 52 to rank0
6794 00:24:35.726993 Final RX Vref Byte 0 = 49 to rank1
6795 00:24:35.730508 Final RX Vref Byte 1 = 52 to rank1==
6796 00:24:35.733185 Dram Type= 6, Freq= 0, CH_1, rank 0
6797 00:24:35.737046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6798 00:24:35.737137 ==
6799 00:24:35.740428 DQS Delay:
6800 00:24:35.740513 DQS0 = 44, DQS1 = 52
6801 00:24:35.743195 DQM Delay:
6802 00:24:35.743277 DQM0 = 10, DQM1 = 11
6803 00:24:35.746720 DQ Delay:
6804 00:24:35.746804 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =12
6805 00:24:35.750540 DQ4 =8, DQ5 =16, DQ6 =20, DQ7 =4
6806 00:24:35.753631 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6807 00:24:35.756523 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =16
6808 00:24:35.756608
6809 00:24:35.756670
6810 00:24:35.766398 [DQSOSCAuto] RK0, (LSB)MR18= 0x7198, (MSB)MR19= 0xc0c, tDQSOscB0 = 390 ps tDQSOscB1 = 395 ps
6811 00:24:35.769686 CH1 RK0: MR19=C0C, MR18=7198
6812 00:24:35.776213 CH1_RK0: MR19=0xC0C, MR18=0x7198, DQSOSC=390, MR23=63, INC=388, DEC=258
6813 00:24:35.776319 ==
6814 00:24:35.779657 Dram Type= 6, Freq= 0, CH_1, rank 1
6815 00:24:35.782697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6816 00:24:35.782786 ==
6817 00:24:35.786317 [Gating] SW mode calibration
6818 00:24:35.793010 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6819 00:24:35.799544 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6820 00:24:35.802682 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6821 00:24:35.806079 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6822 00:24:35.812529 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6823 00:24:35.815708 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6824 00:24:35.819000 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6825 00:24:35.825606 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6826 00:24:35.828838 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6827 00:24:35.832220 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6828 00:24:35.839102 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6829 00:24:35.839221 Total UI for P1: 0, mck2ui 16
6830 00:24:35.842444 best dqsien dly found for B0: ( 0, 14, 24)
6831 00:24:35.845076 Total UI for P1: 0, mck2ui 16
6832 00:24:35.848918 best dqsien dly found for B1: ( 0, 14, 24)
6833 00:24:35.855304 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6834 00:24:35.858373 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6835 00:24:35.858470
6836 00:24:35.861555 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6837 00:24:35.864842 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6838 00:24:35.868573 [Gating] SW calibration Done
6839 00:24:35.868662 ==
6840 00:24:35.871316 Dram Type= 6, Freq= 0, CH_1, rank 1
6841 00:24:35.874812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6842 00:24:35.874900 ==
6843 00:24:35.878038 RX Vref Scan: 0
6844 00:24:35.878121
6845 00:24:35.878186 RX Vref 0 -> 0, step: 1
6846 00:24:35.878245
6847 00:24:35.881407 RX Delay -410 -> 252, step: 16
6848 00:24:35.887921 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6849 00:24:35.891484 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6850 00:24:35.894517 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6851 00:24:35.898054 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6852 00:24:35.904478 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6853 00:24:35.907755 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6854 00:24:35.911007 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6855 00:24:35.914257 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6856 00:24:35.921483 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6857 00:24:35.924325 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6858 00:24:35.927551 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6859 00:24:35.934066 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6860 00:24:35.937666 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6861 00:24:35.940608 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6862 00:24:35.944176 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6863 00:24:35.950434 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6864 00:24:35.950533 ==
6865 00:24:35.954169 Dram Type= 6, Freq= 0, CH_1, rank 1
6866 00:24:35.957045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6867 00:24:35.957129 ==
6868 00:24:35.957193 DQS Delay:
6869 00:24:35.960734 DQS0 = 43, DQS1 = 51
6870 00:24:35.960818 DQM Delay:
6871 00:24:35.963818 DQM0 = 9, DQM1 = 14
6872 00:24:35.963901 DQ Delay:
6873 00:24:35.967301 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6874 00:24:35.970612 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6875 00:24:35.973691 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6876 00:24:35.976783 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6877 00:24:35.976868
6878 00:24:35.976932
6879 00:24:35.976991 ==
6880 00:24:35.979944 Dram Type= 6, Freq= 0, CH_1, rank 1
6881 00:24:35.983438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6882 00:24:35.983528 ==
6883 00:24:35.983593
6884 00:24:35.983653
6885 00:24:35.986712 TX Vref Scan disable
6886 00:24:35.990075 == TX Byte 0 ==
6887 00:24:35.993159 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6888 00:24:35.996803 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6889 00:24:35.999993 == TX Byte 1 ==
6890 00:24:36.003165 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6891 00:24:36.006142 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6892 00:24:36.006234 ==
6893 00:24:36.009969 Dram Type= 6, Freq= 0, CH_1, rank 1
6894 00:24:36.012943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6895 00:24:36.013037 ==
6896 00:24:36.016402
6897 00:24:36.016488
6898 00:24:36.016552 TX Vref Scan disable
6899 00:24:36.019928 == TX Byte 0 ==
6900 00:24:36.022798 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6901 00:24:36.026373 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6902 00:24:36.029521 == TX Byte 1 ==
6903 00:24:36.032824 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6904 00:24:36.036353 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6905 00:24:36.036442
6906 00:24:36.036508 [DATLAT]
6907 00:24:36.039498 Freq=400, CH1 RK1
6908 00:24:36.039582
6909 00:24:36.042882 DATLAT Default: 0xe
6910 00:24:36.042965 0, 0xFFFF, sum = 0
6911 00:24:36.045884 1, 0xFFFF, sum = 0
6912 00:24:36.045968 2, 0xFFFF, sum = 0
6913 00:24:36.049115 3, 0xFFFF, sum = 0
6914 00:24:36.049201 4, 0xFFFF, sum = 0
6915 00:24:36.052506 5, 0xFFFF, sum = 0
6916 00:24:36.052591 6, 0xFFFF, sum = 0
6917 00:24:36.055702 7, 0xFFFF, sum = 0
6918 00:24:36.055786 8, 0xFFFF, sum = 0
6919 00:24:36.059693 9, 0xFFFF, sum = 0
6920 00:24:36.059778 10, 0xFFFF, sum = 0
6921 00:24:36.062878 11, 0xFFFF, sum = 0
6922 00:24:36.062963 12, 0xFFFF, sum = 0
6923 00:24:36.065933 13, 0x0, sum = 1
6924 00:24:36.066018 14, 0x0, sum = 2
6925 00:24:36.068942 15, 0x0, sum = 3
6926 00:24:36.069026 16, 0x0, sum = 4
6927 00:24:36.072628 best_step = 14
6928 00:24:36.072711
6929 00:24:36.072775 ==
6930 00:24:36.075419 Dram Type= 6, Freq= 0, CH_1, rank 1
6931 00:24:36.078722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6932 00:24:36.078810 ==
6933 00:24:36.082680 RX Vref Scan: 0
6934 00:24:36.082766
6935 00:24:36.082830 RX Vref 0 -> 0, step: 1
6936 00:24:36.082890
6937 00:24:36.085610 RX Delay -343 -> 252, step: 8
6938 00:24:36.093885 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6939 00:24:36.096854 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6940 00:24:36.100174 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6941 00:24:36.106893 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6942 00:24:36.110413 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6943 00:24:36.113439 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6944 00:24:36.116850 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6945 00:24:36.123256 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6946 00:24:36.126703 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6947 00:24:36.130221 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6948 00:24:36.132978 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6949 00:24:36.140485 iDelay=217, Bit 11, Center -48 (-287 ~ 192) 480
6950 00:24:36.143071 iDelay=217, Bit 12, Center -32 (-271 ~ 208) 480
6951 00:24:36.146931 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6952 00:24:36.149418 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6953 00:24:36.156154 iDelay=217, Bit 15, Center -32 (-279 ~ 216) 496
6954 00:24:36.156260 ==
6955 00:24:36.159579 Dram Type= 6, Freq= 0, CH_1, rank 1
6956 00:24:36.163130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6957 00:24:36.163217 ==
6958 00:24:36.163280 DQS Delay:
6959 00:24:36.166068 DQS0 = 48, DQS1 = 52
6960 00:24:36.166150 DQM Delay:
6961 00:24:36.169573 DQM0 = 12, DQM1 = 11
6962 00:24:36.169656 DQ Delay:
6963 00:24:36.173134 DQ0 =16, DQ1 =12, DQ2 =0, DQ3 =12
6964 00:24:36.176231 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =8
6965 00:24:36.179559 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6966 00:24:36.182426 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
6967 00:24:36.182526
6968 00:24:36.182630
6969 00:24:36.192604 [DQSOSCAuto] RK1, (LSB)MR18= 0x7db5, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 394 ps
6970 00:24:36.192781 CH1 RK1: MR19=C0C, MR18=7DB5
6971 00:24:36.198868 CH1_RK1: MR19=0xC0C, MR18=0x7DB5, DQSOSC=387, MR23=63, INC=394, DEC=262
6972 00:24:36.202154 [RxdqsGatingPostProcess] freq 400
6973 00:24:36.209201 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6974 00:24:36.211958 best DQS0 dly(2T, 0.5T) = (0, 10)
6975 00:24:36.215678 best DQS1 dly(2T, 0.5T) = (0, 10)
6976 00:24:36.219087 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6977 00:24:36.222215 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6978 00:24:36.225334 best DQS0 dly(2T, 0.5T) = (0, 10)
6979 00:24:36.228573 best DQS1 dly(2T, 0.5T) = (0, 10)
6980 00:24:36.231943 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6981 00:24:36.235086 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6982 00:24:36.235174 Pre-setting of DQS Precalculation
6983 00:24:36.241792 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6984 00:24:36.248827 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6985 00:24:36.254944 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6986 00:24:36.255054
6987 00:24:36.255120
6988 00:24:36.258509 [Calibration Summary] 800 Mbps
6989 00:24:36.261365 CH 0, Rank 0
6990 00:24:36.261451 SW Impedance : PASS
6991 00:24:36.264680 DUTY Scan : NO K
6992 00:24:36.267898 ZQ Calibration : PASS
6993 00:24:36.267983 Jitter Meter : NO K
6994 00:24:36.271886 CBT Training : PASS
6995 00:24:36.274939 Write leveling : PASS
6996 00:24:36.275025 RX DQS gating : PASS
6997 00:24:36.278175 RX DQ/DQS(RDDQC) : PASS
6998 00:24:36.281119 TX DQ/DQS : PASS
6999 00:24:36.281203 RX DATLAT : PASS
7000 00:24:36.284526 RX DQ/DQS(Engine): PASS
7001 00:24:36.287918 TX OE : NO K
7002 00:24:36.288005 All Pass.
7003 00:24:36.288070
7004 00:24:36.288129 CH 0, Rank 1
7005 00:24:36.291406 SW Impedance : PASS
7006 00:24:36.294487 DUTY Scan : NO K
7007 00:24:36.294573 ZQ Calibration : PASS
7008 00:24:36.297790 Jitter Meter : NO K
7009 00:24:36.300934 CBT Training : PASS
7010 00:24:36.301052 Write leveling : NO K
7011 00:24:36.304352 RX DQS gating : PASS
7012 00:24:36.304435 RX DQ/DQS(RDDQC) : PASS
7013 00:24:36.307564 TX DQ/DQS : PASS
7014 00:24:36.310691 RX DATLAT : PASS
7015 00:24:36.310785 RX DQ/DQS(Engine): PASS
7016 00:24:36.313867 TX OE : NO K
7017 00:24:36.313952 All Pass.
7018 00:24:36.314016
7019 00:24:36.317423 CH 1, Rank 0
7020 00:24:36.317509 SW Impedance : PASS
7021 00:24:36.320671 DUTY Scan : NO K
7022 00:24:36.324207 ZQ Calibration : PASS
7023 00:24:36.324298 Jitter Meter : NO K
7024 00:24:36.327369 CBT Training : PASS
7025 00:24:36.330737 Write leveling : PASS
7026 00:24:36.330828 RX DQS gating : PASS
7027 00:24:36.333663 RX DQ/DQS(RDDQC) : PASS
7028 00:24:36.337151 TX DQ/DQS : PASS
7029 00:24:36.337291 RX DATLAT : PASS
7030 00:24:36.340542 RX DQ/DQS(Engine): PASS
7031 00:24:36.343806 TX OE : NO K
7032 00:24:36.343898 All Pass.
7033 00:24:36.343964
7034 00:24:36.344023 CH 1, Rank 1
7035 00:24:36.347054 SW Impedance : PASS
7036 00:24:36.350793 DUTY Scan : NO K
7037 00:24:36.350881 ZQ Calibration : PASS
7038 00:24:36.353653 Jitter Meter : NO K
7039 00:24:36.356571 CBT Training : PASS
7040 00:24:36.356676 Write leveling : NO K
7041 00:24:36.359838 RX DQS gating : PASS
7042 00:24:36.363691 RX DQ/DQS(RDDQC) : PASS
7043 00:24:36.363825 TX DQ/DQS : PASS
7044 00:24:36.366720 RX DATLAT : PASS
7045 00:24:36.369928 RX DQ/DQS(Engine): PASS
7046 00:24:36.370038 TX OE : NO K
7047 00:24:36.373446 All Pass.
7048 00:24:36.373606
7049 00:24:36.373691 DramC Write-DBI off
7050 00:24:36.376631 PER_BANK_REFRESH: Hybrid Mode
7051 00:24:36.376715 TX_TRACKING: ON
7052 00:24:36.386701 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7053 00:24:36.389733 [FAST_K] Save calibration result to emmc
7054 00:24:36.392884 dramc_set_vcore_voltage set vcore to 725000
7055 00:24:36.396888 Read voltage for 1600, 0
7056 00:24:36.396985 Vio18 = 0
7057 00:24:36.399695 Vcore = 725000
7058 00:24:36.399779 Vdram = 0
7059 00:24:36.399843 Vddq = 0
7060 00:24:36.403066 Vmddr = 0
7061 00:24:36.406667 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7062 00:24:36.413042 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7063 00:24:36.413154 MEM_TYPE=3, freq_sel=13
7064 00:24:36.415805 sv_algorithm_assistance_LP4_3733
7065 00:24:36.422673 ============ PULL DRAM RESETB DOWN ============
7066 00:24:36.425601 ========== PULL DRAM RESETB DOWN end =========
7067 00:24:36.428899 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7068 00:24:36.432503 ===================================
7069 00:24:36.435969 LPDDR4 DRAM CONFIGURATION
7070 00:24:36.439356 ===================================
7071 00:24:36.442348 EX_ROW_EN[0] = 0x0
7072 00:24:36.442443 EX_ROW_EN[1] = 0x0
7073 00:24:36.445349 LP4Y_EN = 0x0
7074 00:24:36.445438 WORK_FSP = 0x1
7075 00:24:36.449084 WL = 0x5
7076 00:24:36.449208 RL = 0x5
7077 00:24:36.452011 BL = 0x2
7078 00:24:36.452123 RPST = 0x0
7079 00:24:36.455515 RD_PRE = 0x0
7080 00:24:36.455629 WR_PRE = 0x1
7081 00:24:36.458846 WR_PST = 0x1
7082 00:24:36.461944 DBI_WR = 0x0
7083 00:24:36.462033 DBI_RD = 0x0
7084 00:24:36.464963 OTF = 0x1
7085 00:24:36.468657 ===================================
7086 00:24:36.471833 ===================================
7087 00:24:36.471923 ANA top config
7088 00:24:36.474842 ===================================
7089 00:24:36.478407 DLL_ASYNC_EN = 0
7090 00:24:36.481719 ALL_SLAVE_EN = 0
7091 00:24:36.481810 NEW_RANK_MODE = 1
7092 00:24:36.484794 DLL_IDLE_MODE = 1
7093 00:24:36.488381 LP45_APHY_COMB_EN = 1
7094 00:24:36.491414 TX_ODT_DIS = 0
7095 00:24:36.494590 NEW_8X_MODE = 1
7096 00:24:36.498176 ===================================
7097 00:24:36.501263 ===================================
7098 00:24:36.501362 data_rate = 3200
7099 00:24:36.504505 CKR = 1
7100 00:24:36.507549 DQ_P2S_RATIO = 8
7101 00:24:36.510828 ===================================
7102 00:24:36.514121 CA_P2S_RATIO = 8
7103 00:24:36.517657 DQ_CA_OPEN = 0
7104 00:24:36.520912 DQ_SEMI_OPEN = 0
7105 00:24:36.520999 CA_SEMI_OPEN = 0
7106 00:24:36.524482 CA_FULL_RATE = 0
7107 00:24:36.527273 DQ_CKDIV4_EN = 0
7108 00:24:36.530752 CA_CKDIV4_EN = 0
7109 00:24:36.534178 CA_PREDIV_EN = 0
7110 00:24:36.537283 PH8_DLY = 12
7111 00:24:36.537383 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7112 00:24:36.540825 DQ_AAMCK_DIV = 4
7113 00:24:36.544121 CA_AAMCK_DIV = 4
7114 00:24:36.547398 CA_ADMCK_DIV = 4
7115 00:24:36.550770 DQ_TRACK_CA_EN = 0
7116 00:24:36.554091 CA_PICK = 1600
7117 00:24:36.557190 CA_MCKIO = 1600
7118 00:24:36.557314 MCKIO_SEMI = 0
7119 00:24:36.560645 PLL_FREQ = 3068
7120 00:24:36.563733 DQ_UI_PI_RATIO = 32
7121 00:24:36.567215 CA_UI_PI_RATIO = 0
7122 00:24:36.570596 ===================================
7123 00:24:36.573888 ===================================
7124 00:24:36.577086 memory_type:LPDDR4
7125 00:24:36.577174 GP_NUM : 10
7126 00:24:36.580488 SRAM_EN : 1
7127 00:24:36.583742 MD32_EN : 0
7128 00:24:36.587246 ===================================
7129 00:24:36.587337 [ANA_INIT] >>>>>>>>>>>>>>
7130 00:24:36.590153 <<<<<< [CONFIGURE PHASE]: ANA_TX
7131 00:24:36.593360 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7132 00:24:36.596724 ===================================
7133 00:24:36.600394 data_rate = 3200,PCW = 0X7600
7134 00:24:36.603411 ===================================
7135 00:24:36.606309 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7136 00:24:36.613150 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7137 00:24:36.619926 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7138 00:24:36.623185 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7139 00:24:36.626558 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7140 00:24:36.629514 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7141 00:24:36.633055 [ANA_INIT] flow start
7142 00:24:36.633146 [ANA_INIT] PLL >>>>>>>>
7143 00:24:36.636479 [ANA_INIT] PLL <<<<<<<<
7144 00:24:36.639541 [ANA_INIT] MIDPI >>>>>>>>
7145 00:24:36.639632 [ANA_INIT] MIDPI <<<<<<<<
7146 00:24:36.643025 [ANA_INIT] DLL >>>>>>>>
7147 00:24:36.646220 [ANA_INIT] DLL <<<<<<<<
7148 00:24:36.646306 [ANA_INIT] flow end
7149 00:24:36.653105 ============ LP4 DIFF to SE enter ============
7150 00:24:36.656162 ============ LP4 DIFF to SE exit ============
7151 00:24:36.659363 [ANA_INIT] <<<<<<<<<<<<<
7152 00:24:36.662692 [Flow] Enable top DCM control >>>>>
7153 00:24:36.665681 [Flow] Enable top DCM control <<<<<
7154 00:24:36.665772 Enable DLL master slave shuffle
7155 00:24:36.672778 ==============================================================
7156 00:24:36.675922 Gating Mode config
7157 00:24:36.679043 ==============================================================
7158 00:24:36.683254 Config description:
7159 00:24:36.692640 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7160 00:24:36.699555 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7161 00:24:36.702705 SELPH_MODE 0: By rank 1: By Phase
7162 00:24:36.708895 ==============================================================
7163 00:24:36.712126 GAT_TRACK_EN = 1
7164 00:24:36.715228 RX_GATING_MODE = 2
7165 00:24:36.718933 RX_GATING_TRACK_MODE = 2
7166 00:24:36.722504 SELPH_MODE = 1
7167 00:24:36.725239 PICG_EARLY_EN = 1
7168 00:24:36.728705 VALID_LAT_VALUE = 1
7169 00:24:36.731632 ==============================================================
7170 00:24:36.734850 Enter into Gating configuration >>>>
7171 00:24:36.738540 Exit from Gating configuration <<<<
7172 00:24:36.741516 Enter into DVFS_PRE_config >>>>>
7173 00:24:36.754858 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7174 00:24:36.754986 Exit from DVFS_PRE_config <<<<<
7175 00:24:36.757787 Enter into PICG configuration >>>>
7176 00:24:36.761484 Exit from PICG configuration <<<<
7177 00:24:36.764656 [RX_INPUT] configuration >>>>>
7178 00:24:36.768024 [RX_INPUT] configuration <<<<<
7179 00:24:36.774614 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7180 00:24:36.778216 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7181 00:24:36.784139 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7182 00:24:36.791283 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7183 00:24:36.797410 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7184 00:24:36.803919 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7185 00:24:36.807446 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7186 00:24:36.810725 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7187 00:24:36.817505 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7188 00:24:36.820756 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7189 00:24:36.823500 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7190 00:24:36.826768 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7191 00:24:36.830183 ===================================
7192 00:24:36.833444 LPDDR4 DRAM CONFIGURATION
7193 00:24:36.836952 ===================================
7194 00:24:36.840513 EX_ROW_EN[0] = 0x0
7195 00:24:36.840606 EX_ROW_EN[1] = 0x0
7196 00:24:36.843603 LP4Y_EN = 0x0
7197 00:24:36.843714 WORK_FSP = 0x1
7198 00:24:36.847071 WL = 0x5
7199 00:24:36.847158 RL = 0x5
7200 00:24:36.850168 BL = 0x2
7201 00:24:36.850251 RPST = 0x0
7202 00:24:36.853587 RD_PRE = 0x0
7203 00:24:36.857039 WR_PRE = 0x1
7204 00:24:36.857123 WR_PST = 0x1
7205 00:24:36.859916 DBI_WR = 0x0
7206 00:24:36.859997 DBI_RD = 0x0
7207 00:24:36.863197 OTF = 0x1
7208 00:24:36.866837 ===================================
7209 00:24:36.870249 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7210 00:24:36.873149 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7211 00:24:36.876398 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7212 00:24:36.880137 ===================================
7213 00:24:36.882931 LPDDR4 DRAM CONFIGURATION
7214 00:24:36.886374 ===================================
7215 00:24:36.889896 EX_ROW_EN[0] = 0x10
7216 00:24:36.889982 EX_ROW_EN[1] = 0x0
7217 00:24:36.892843 LP4Y_EN = 0x0
7218 00:24:36.892925 WORK_FSP = 0x1
7219 00:24:36.896702 WL = 0x5
7220 00:24:36.896786 RL = 0x5
7221 00:24:36.899359 BL = 0x2
7222 00:24:36.902788 RPST = 0x0
7223 00:24:36.902872 RD_PRE = 0x0
7224 00:24:36.905994 WR_PRE = 0x1
7225 00:24:36.906075 WR_PST = 0x1
7226 00:24:36.909672 DBI_WR = 0x0
7227 00:24:36.909756 DBI_RD = 0x0
7228 00:24:36.912785 OTF = 0x1
7229 00:24:36.916081 ===================================
7230 00:24:36.922617 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7231 00:24:36.922726 ==
7232 00:24:36.925530 Dram Type= 6, Freq= 0, CH_0, rank 0
7233 00:24:36.929107 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7234 00:24:36.929192 ==
7235 00:24:36.932103 [Duty_Offset_Calibration]
7236 00:24:36.932188 B0:2 B1:0 CA:4
7237 00:24:36.932253
7238 00:24:36.935437 [DutyScan_Calibration_Flow] k_type=0
7239 00:24:36.945272
7240 00:24:36.945397 ==CLK 0==
7241 00:24:36.948458 Final CLK duty delay cell = -4
7242 00:24:36.951723 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7243 00:24:36.954861 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7244 00:24:36.958167 [-4] AVG Duty = 4937%(X100)
7245 00:24:36.958256
7246 00:24:36.961502 CH0 CLK Duty spec in!! Max-Min= 187%
7247 00:24:36.964806 [DutyScan_Calibration_Flow] ====Done====
7248 00:24:36.964891
7249 00:24:36.968214 [DutyScan_Calibration_Flow] k_type=1
7250 00:24:36.985467
7251 00:24:36.985618 ==DQS 0 ==
7252 00:24:36.988856 Final DQS duty delay cell = 0
7253 00:24:36.991899 [0] MAX Duty = 5218%(X100), DQS PI = 38
7254 00:24:36.995370 [0] MIN Duty = 5093%(X100), DQS PI = 6
7255 00:24:36.998761 [0] AVG Duty = 5155%(X100)
7256 00:24:36.998849
7257 00:24:36.998913 ==DQS 1 ==
7258 00:24:37.001753 Final DQS duty delay cell = 0
7259 00:24:37.005553 [0] MAX Duty = 5156%(X100), DQS PI = 2
7260 00:24:37.008374 [0] MIN Duty = 4969%(X100), DQS PI = 12
7261 00:24:37.011415 [0] AVG Duty = 5062%(X100)
7262 00:24:37.011580
7263 00:24:37.014826 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7264 00:24:37.014918
7265 00:24:37.018779 CH0 DQS 1 Duty spec in!! Max-Min= 187%
7266 00:24:37.021496 [DutyScan_Calibration_Flow] ====Done====
7267 00:24:37.021582
7268 00:24:37.024756 [DutyScan_Calibration_Flow] k_type=3
7269 00:24:37.042373
7270 00:24:37.042528 ==DQM 0 ==
7271 00:24:37.046358 Final DQM duty delay cell = 0
7272 00:24:37.048852 [0] MAX Duty = 5124%(X100), DQS PI = 22
7273 00:24:37.052284 [0] MIN Duty = 4844%(X100), DQS PI = 56
7274 00:24:37.055658 [0] AVG Duty = 4984%(X100)
7275 00:24:37.055752
7276 00:24:37.055816 ==DQM 1 ==
7277 00:24:37.059182 Final DQM duty delay cell = 0
7278 00:24:37.062165 [0] MAX Duty = 4969%(X100), DQS PI = 0
7279 00:24:37.065598 [0] MIN Duty = 4844%(X100), DQS PI = 16
7280 00:24:37.068807 [0] AVG Duty = 4906%(X100)
7281 00:24:37.068896
7282 00:24:37.072843 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7283 00:24:37.072929
7284 00:24:37.075653 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7285 00:24:37.078807 [DutyScan_Calibration_Flow] ====Done====
7286 00:24:37.078892
7287 00:24:37.081742 [DutyScan_Calibration_Flow] k_type=2
7288 00:24:37.099889
7289 00:24:37.100045 ==DQ 0 ==
7290 00:24:37.102941 Final DQ duty delay cell = 0
7291 00:24:37.106210 [0] MAX Duty = 5156%(X100), DQS PI = 22
7292 00:24:37.109641 [0] MIN Duty = 4938%(X100), DQS PI = 12
7293 00:24:37.109728 [0] AVG Duty = 5047%(X100)
7294 00:24:37.113030
7295 00:24:37.113118 ==DQ 1 ==
7296 00:24:37.116349 Final DQ duty delay cell = 0
7297 00:24:37.119435 [0] MAX Duty = 5187%(X100), DQS PI = 2
7298 00:24:37.123079 [0] MIN Duty = 4907%(X100), DQS PI = 34
7299 00:24:37.123167 [0] AVG Duty = 5047%(X100)
7300 00:24:37.125926
7301 00:24:37.128958 CH0 DQ 0 Duty spec in!! Max-Min= 218%
7302 00:24:37.129043
7303 00:24:37.132425 CH0 DQ 1 Duty spec in!! Max-Min= 280%
7304 00:24:37.135839 [DutyScan_Calibration_Flow] ====Done====
7305 00:24:37.135922 ==
7306 00:24:37.139186 Dram Type= 6, Freq= 0, CH_1, rank 0
7307 00:24:37.142331 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7308 00:24:37.142418 ==
7309 00:24:37.146053 [Duty_Offset_Calibration]
7310 00:24:37.146136 B0:0 B1:-1 CA:3
7311 00:24:37.146200
7312 00:24:37.148756 [DutyScan_Calibration_Flow] k_type=0
7313 00:24:37.160102
7314 00:24:37.160236 ==CLK 0==
7315 00:24:37.163426 Final CLK duty delay cell = 0
7316 00:24:37.166588 [0] MAX Duty = 5187%(X100), DQS PI = 26
7317 00:24:37.169757 [0] MIN Duty = 5000%(X100), DQS PI = 54
7318 00:24:37.173116 [0] AVG Duty = 5093%(X100)
7319 00:24:37.173202
7320 00:24:37.176378 CH1 CLK Duty spec in!! Max-Min= 187%
7321 00:24:37.179467 [DutyScan_Calibration_Flow] ====Done====
7322 00:24:37.179578
7323 00:24:37.182917 [DutyScan_Calibration_Flow] k_type=1
7324 00:24:37.198869
7325 00:24:37.199018 ==DQS 0 ==
7326 00:24:37.202202 Final DQS duty delay cell = 0
7327 00:24:37.205865 [0] MAX Duty = 5218%(X100), DQS PI = 28
7328 00:24:37.208952 [0] MIN Duty = 4907%(X100), DQS PI = 42
7329 00:24:37.212277 [0] AVG Duty = 5062%(X100)
7330 00:24:37.212374
7331 00:24:37.212440 ==DQS 1 ==
7332 00:24:37.215195 Final DQS duty delay cell = -4
7333 00:24:37.219002 [-4] MAX Duty = 5000%(X100), DQS PI = 30
7334 00:24:37.221980 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7335 00:24:37.225418 [-4] AVG Duty = 4906%(X100)
7336 00:24:37.225503
7337 00:24:37.228332 CH1 DQS 0 Duty spec in!! Max-Min= 311%
7338 00:24:37.228413
7339 00:24:37.231931 CH1 DQS 1 Duty spec in!! Max-Min= 187%
7340 00:24:37.234948 [DutyScan_Calibration_Flow] ====Done====
7341 00:24:37.235034
7342 00:24:37.238149 [DutyScan_Calibration_Flow] k_type=3
7343 00:24:37.256160
7344 00:24:37.256316 ==DQM 0 ==
7345 00:24:37.259952 Final DQM duty delay cell = 0
7346 00:24:37.262617 [0] MAX Duty = 5062%(X100), DQS PI = 30
7347 00:24:37.265546 [0] MIN Duty = 4782%(X100), DQS PI = 38
7348 00:24:37.269167 [0] AVG Duty = 4922%(X100)
7349 00:24:37.269267
7350 00:24:37.269362 ==DQM 1 ==
7351 00:24:37.272626 Final DQM duty delay cell = 0
7352 00:24:37.275530 [0] MAX Duty = 5000%(X100), DQS PI = 32
7353 00:24:37.278804 [0] MIN Duty = 4813%(X100), DQS PI = 0
7354 00:24:37.282091 [0] AVG Duty = 4906%(X100)
7355 00:24:37.282181
7356 00:24:37.285918 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7357 00:24:37.286006
7358 00:24:37.288961 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7359 00:24:37.291989 [DutyScan_Calibration_Flow] ====Done====
7360 00:24:37.292076
7361 00:24:37.295596 [DutyScan_Calibration_Flow] k_type=2
7362 00:24:37.312948
7363 00:24:37.313101 ==DQ 0 ==
7364 00:24:37.315691 Final DQ duty delay cell = -4
7365 00:24:37.318516 [-4] MAX Duty = 4938%(X100), DQS PI = 16
7366 00:24:37.322242 [-4] MIN Duty = 4813%(X100), DQS PI = 38
7367 00:24:37.325164 [-4] AVG Duty = 4875%(X100)
7368 00:24:37.325249
7369 00:24:37.325350 ==DQ 1 ==
7370 00:24:37.328553 Final DQ duty delay cell = 0
7371 00:24:37.332033 [0] MAX Duty = 5031%(X100), DQS PI = 48
7372 00:24:37.335412 [0] MIN Duty = 4875%(X100), DQS PI = 0
7373 00:24:37.338600 [0] AVG Duty = 4953%(X100)
7374 00:24:37.338688
7375 00:24:37.341962 CH1 DQ 0 Duty spec in!! Max-Min= 125%
7376 00:24:37.342049
7377 00:24:37.345281 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7378 00:24:37.348296 [DutyScan_Calibration_Flow] ====Done====
7379 00:24:37.351672 nWR fixed to 30
7380 00:24:37.355286 [ModeRegInit_LP4] CH0 RK0
7381 00:24:37.355373 [ModeRegInit_LP4] CH0 RK1
7382 00:24:37.358178 [ModeRegInit_LP4] CH1 RK0
7383 00:24:37.361418 [ModeRegInit_LP4] CH1 RK1
7384 00:24:37.361502 match AC timing 5
7385 00:24:37.368170 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7386 00:24:37.371793 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7387 00:24:37.374476 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7388 00:24:37.381424 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7389 00:24:37.384353 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7390 00:24:37.384446 [MiockJmeterHQA]
7391 00:24:37.387671
7392 00:24:37.387753 [DramcMiockJmeter] u1RxGatingPI = 0
7393 00:24:37.391473 0 : 4252, 4027
7394 00:24:37.391559 4 : 4363, 4137
7395 00:24:37.394472 8 : 4253, 4026
7396 00:24:37.394556 12 : 4253, 4026
7397 00:24:37.397805 16 : 4252, 4027
7398 00:24:37.397888 20 : 4252, 4027
7399 00:24:37.401187 24 : 4254, 4029
7400 00:24:37.401331 28 : 4252, 4026
7401 00:24:37.401398 32 : 4253, 4027
7402 00:24:37.404454 36 : 4365, 4140
7403 00:24:37.404537 40 : 4252, 4027
7404 00:24:37.407854 44 : 4255, 4029
7405 00:24:37.407938 48 : 4254, 4029
7406 00:24:37.410677 52 : 4363, 4138
7407 00:24:37.410761 56 : 4252, 4027
7408 00:24:37.414071 60 : 4363, 4140
7409 00:24:37.414191 64 : 4253, 4029
7410 00:24:37.414278 68 : 4250, 4026
7411 00:24:37.417667 72 : 4250, 4027
7412 00:24:37.417752 76 : 4252, 4029
7413 00:24:37.420955 80 : 4250, 4026
7414 00:24:37.421039 84 : 4250, 4027
7415 00:24:37.424531 88 : 4363, 4140
7416 00:24:37.424616 92 : 4252, 4027
7417 00:24:37.427568 96 : 4252, 2858
7418 00:24:37.427651 100 : 4250, 0
7419 00:24:37.427717 104 : 4249, 0
7420 00:24:37.430595 108 : 4250, 0
7421 00:24:37.430680 112 : 4252, 0
7422 00:24:37.430744 116 : 4252, 0
7423 00:24:37.433904 120 : 4361, 0
7424 00:24:37.433987 124 : 4361, 0
7425 00:24:37.437214 128 : 4250, 0
7426 00:24:37.437333 132 : 4250, 0
7427 00:24:37.437398 136 : 4250, 0
7428 00:24:37.440404 140 : 4250, 0
7429 00:24:37.440522 144 : 4252, 0
7430 00:24:37.443841 148 : 4250, 0
7431 00:24:37.443926 152 : 4250, 0
7432 00:24:37.443991 156 : 4252, 0
7433 00:24:37.447156 160 : 4253, 0
7434 00:24:37.447241 164 : 4250, 0
7435 00:24:37.450574 168 : 4253, 0
7436 00:24:37.450674 172 : 4361, 0
7437 00:24:37.450741 176 : 4360, 0
7438 00:24:37.453660 180 : 4250, 0
7439 00:24:37.453743 184 : 4250, 0
7440 00:24:37.457050 188 : 4360, 0
7441 00:24:37.457133 192 : 4250, 0
7442 00:24:37.457198 196 : 4249, 0
7443 00:24:37.460750 200 : 4250, 0
7444 00:24:37.460834 204 : 4250, 0
7445 00:24:37.463740 208 : 4252, 0
7446 00:24:37.463823 212 : 4360, 0
7447 00:24:37.463888 216 : 4250, 0
7448 00:24:37.466669 220 : 4249, 623
7449 00:24:37.466752 224 : 4360, 4125
7450 00:24:37.470317 228 : 4252, 4029
7451 00:24:37.470401 232 : 4250, 4027
7452 00:24:37.473571 236 : 4363, 4140
7453 00:24:37.473654 240 : 4360, 4137
7454 00:24:37.476560 244 : 4250, 4027
7455 00:24:37.476670 248 : 4250, 4027
7456 00:24:37.480132 252 : 4252, 4029
7457 00:24:37.480243 256 : 4250, 4026
7458 00:24:37.480337 260 : 4250, 4027
7459 00:24:37.483673 264 : 4252, 4030
7460 00:24:37.483758 268 : 4252, 4029
7461 00:24:37.486751 272 : 4250, 4026
7462 00:24:37.486835 276 : 4363, 4140
7463 00:24:37.489932 280 : 4360, 4138
7464 00:24:37.490015 284 : 4250, 4027
7465 00:24:37.493635 288 : 4361, 4137
7466 00:24:37.493721 292 : 4250, 4026
7467 00:24:37.496496 296 : 4250, 4027
7468 00:24:37.496579 300 : 4250, 4027
7469 00:24:37.499921 304 : 4252, 4030
7470 00:24:37.500006 308 : 4249, 4027
7471 00:24:37.503524 312 : 4249, 4027
7472 00:24:37.503608 316 : 4250, 4027
7473 00:24:37.506270 320 : 4252, 4030
7474 00:24:37.506355 324 : 4250, 4026
7475 00:24:37.506420 328 : 4363, 4140
7476 00:24:37.509995 332 : 4363, 3965
7477 00:24:37.510081 336 : 4248, 1815
7478 00:24:37.510146
7479 00:24:37.512952 MIOCK jitter meter ch=0
7480 00:24:37.513040
7481 00:24:37.516102 1T = (336-100) = 236 dly cells
7482 00:24:37.522965 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7483 00:24:37.523103 ==
7484 00:24:37.525834 Dram Type= 6, Freq= 0, CH_0, rank 0
7485 00:24:37.529215 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7486 00:24:37.529340 ==
7487 00:24:37.536059 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7488 00:24:37.539414 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7489 00:24:37.542740 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7490 00:24:37.549411 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7491 00:24:37.558772 [CA 0] Center 43 (13~74) winsize 62
7492 00:24:37.561762 [CA 1] Center 42 (12~73) winsize 62
7493 00:24:37.565095 [CA 2] Center 37 (8~67) winsize 60
7494 00:24:37.568552 [CA 3] Center 37 (8~67) winsize 60
7495 00:24:37.571676 [CA 4] Center 36 (6~66) winsize 61
7496 00:24:37.575070 [CA 5] Center 35 (5~66) winsize 62
7497 00:24:37.575187
7498 00:24:37.578652 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7499 00:24:37.578757
7500 00:24:37.581614 [CATrainingPosCal] consider 1 rank data
7501 00:24:37.585133 u2DelayCellTimex100 = 275/100 ps
7502 00:24:37.591615 CA0 delay=43 (13~74),Diff = 8 PI (28 cell)
7503 00:24:37.594924 CA1 delay=42 (12~73),Diff = 7 PI (24 cell)
7504 00:24:37.598392 CA2 delay=37 (8~67),Diff = 2 PI (7 cell)
7505 00:24:37.601565 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7506 00:24:37.604690 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7507 00:24:37.608299 CA5 delay=35 (5~66),Diff = 0 PI (0 cell)
7508 00:24:37.608423
7509 00:24:37.611656 CA PerBit enable=1, Macro0, CA PI delay=35
7510 00:24:37.611746
7511 00:24:37.615056 [CBTSetCACLKResult] CA Dly = 35
7512 00:24:37.617861 CS Dly: 10 (0~41)
7513 00:24:37.621193 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7514 00:24:37.624853 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7515 00:24:37.624948 ==
7516 00:24:37.627922 Dram Type= 6, Freq= 0, CH_0, rank 1
7517 00:24:37.634372 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7518 00:24:37.634498 ==
7519 00:24:37.637558 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7520 00:24:37.644377 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7521 00:24:37.647505 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7522 00:24:37.654418 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7523 00:24:37.662040 [CA 0] Center 44 (14~75) winsize 62
7524 00:24:37.665270 [CA 1] Center 44 (14~74) winsize 61
7525 00:24:37.668549 [CA 2] Center 39 (10~69) winsize 60
7526 00:24:37.672143 [CA 3] Center 38 (9~68) winsize 60
7527 00:24:37.675348 [CA 4] Center 37 (7~67) winsize 61
7528 00:24:37.678799 [CA 5] Center 36 (7~66) winsize 60
7529 00:24:37.678889
7530 00:24:37.681813 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7531 00:24:37.681899
7532 00:24:37.688347 [CATrainingPosCal] consider 2 rank data
7533 00:24:37.688445 u2DelayCellTimex100 = 275/100 ps
7534 00:24:37.695046 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7535 00:24:37.698392 CA1 delay=43 (14~73),Diff = 7 PI (24 cell)
7536 00:24:37.701832 CA2 delay=38 (10~67),Diff = 2 PI (7 cell)
7537 00:24:37.705406 CA3 delay=38 (9~67),Diff = 2 PI (7 cell)
7538 00:24:37.708493 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7539 00:24:37.711994 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7540 00:24:37.712082
7541 00:24:37.715323 CA PerBit enable=1, Macro0, CA PI delay=36
7542 00:24:37.715413
7543 00:24:37.718436 [CBTSetCACLKResult] CA Dly = 36
7544 00:24:37.721692 CS Dly: 11 (0~44)
7545 00:24:37.724487 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7546 00:24:37.727871 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7547 00:24:37.727961
7548 00:24:37.731250 ----->DramcWriteLeveling(PI) begin...
7549 00:24:37.731337 ==
7550 00:24:37.734944 Dram Type= 6, Freq= 0, CH_0, rank 0
7551 00:24:37.741119 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7552 00:24:37.741253 ==
7553 00:24:37.744506 Write leveling (Byte 0): 36 => 36
7554 00:24:37.747850 Write leveling (Byte 1): 25 => 25
7555 00:24:37.747954 DramcWriteLeveling(PI) end<-----
7556 00:24:37.751119
7557 00:24:37.751205 ==
7558 00:24:37.754533 Dram Type= 6, Freq= 0, CH_0, rank 0
7559 00:24:37.757817 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7560 00:24:37.757904 ==
7561 00:24:37.760901 [Gating] SW mode calibration
7562 00:24:37.767858 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7563 00:24:37.774274 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7564 00:24:37.777572 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7565 00:24:37.780752 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7566 00:24:37.787165 1 4 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
7567 00:24:37.790560 1 4 12 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (0 0)
7568 00:24:37.793719 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7569 00:24:37.800803 1 4 20 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
7570 00:24:37.803951 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7571 00:24:37.807094 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7572 00:24:37.813427 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7573 00:24:37.816976 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7574 00:24:37.820251 1 5 8 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
7575 00:24:37.826766 1 5 12 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 0)
7576 00:24:37.830261 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7577 00:24:37.833049 1 5 20 | B1->B0 | 3131 2323 | 0 0 | (0 0) (0 0)
7578 00:24:37.840232 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7579 00:24:37.843177 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7580 00:24:37.846223 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7581 00:24:37.853121 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7582 00:24:37.856738 1 6 8 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (0 0)
7583 00:24:37.859597 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7584 00:24:37.866327 1 6 16 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
7585 00:24:37.869718 1 6 20 | B1->B0 | 4141 4646 | 0 0 | (1 1) (0 0)
7586 00:24:37.873093 1 6 24 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7587 00:24:37.879188 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7588 00:24:37.882640 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7589 00:24:37.885738 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7590 00:24:37.892859 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7591 00:24:37.895741 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7592 00:24:37.899046 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7593 00:24:37.906274 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7594 00:24:37.908848 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7595 00:24:37.912187 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7596 00:24:37.919011 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7597 00:24:37.921885 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7598 00:24:37.925336 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7599 00:24:37.932602 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7600 00:24:37.935203 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7601 00:24:37.938693 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7602 00:24:37.945592 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7603 00:24:37.948687 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7604 00:24:37.951606 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7605 00:24:37.958370 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7606 00:24:37.961569 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7607 00:24:37.964709 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7608 00:24:37.967938 Total UI for P1: 0, mck2ui 16
7609 00:24:37.971295 best dqsien dly found for B0: ( 1, 9, 6)
7610 00:24:37.978005 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7611 00:24:37.981211 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7612 00:24:37.984728 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7613 00:24:37.991286 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7614 00:24:37.991396 Total UI for P1: 0, mck2ui 16
7615 00:24:37.997929 best dqsien dly found for B1: ( 1, 9, 22)
7616 00:24:38.001306 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
7617 00:24:38.004161 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7618 00:24:38.004247
7619 00:24:38.007638 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
7620 00:24:38.011027 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7621 00:24:38.014318 [Gating] SW calibration Done
7622 00:24:38.014414 ==
7623 00:24:38.017538 Dram Type= 6, Freq= 0, CH_0, rank 0
7624 00:24:38.021015 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7625 00:24:38.021103 ==
7626 00:24:38.024329 RX Vref Scan: 0
7627 00:24:38.024413
7628 00:24:38.024477 RX Vref 0 -> 0, step: 1
7629 00:24:38.024535
7630 00:24:38.027871 RX Delay 0 -> 252, step: 8
7631 00:24:38.030755 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
7632 00:24:38.037834 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7633 00:24:38.040729 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7634 00:24:38.044031 iDelay=192, Bit 3, Center 127 (72 ~ 183) 112
7635 00:24:38.047474 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7636 00:24:38.050629 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7637 00:24:38.057220 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7638 00:24:38.060261 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7639 00:24:38.063601 iDelay=192, Bit 8, Center 119 (64 ~ 175) 112
7640 00:24:38.066966 iDelay=192, Bit 9, Center 115 (64 ~ 167) 104
7641 00:24:38.073244 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7642 00:24:38.076960 iDelay=192, Bit 11, Center 123 (72 ~ 175) 104
7643 00:24:38.080009 iDelay=192, Bit 12, Center 135 (80 ~ 191) 112
7644 00:24:38.083462 iDelay=192, Bit 13, Center 131 (80 ~ 183) 104
7645 00:24:38.086920 iDelay=192, Bit 14, Center 139 (88 ~ 191) 104
7646 00:24:38.093505 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7647 00:24:38.093629 ==
7648 00:24:38.096509 Dram Type= 6, Freq= 0, CH_0, rank 0
7649 00:24:38.100167 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7650 00:24:38.100254 ==
7651 00:24:38.100318 DQS Delay:
7652 00:24:38.103483 DQS0 = 0, DQS1 = 0
7653 00:24:38.103653 DQM Delay:
7654 00:24:38.106584 DQM0 = 131, DQM1 = 128
7655 00:24:38.106668 DQ Delay:
7656 00:24:38.109524 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7657 00:24:38.113125 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7658 00:24:38.116443 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =123
7659 00:24:38.119667 DQ12 =135, DQ13 =131, DQ14 =139, DQ15 =135
7660 00:24:38.123435
7661 00:24:38.123526
7662 00:24:38.123591 ==
7663 00:24:38.126436 Dram Type= 6, Freq= 0, CH_0, rank 0
7664 00:24:38.129231 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7665 00:24:38.129357 ==
7666 00:24:38.129422
7667 00:24:38.129481
7668 00:24:38.132749 TX Vref Scan disable
7669 00:24:38.132832 == TX Byte 0 ==
7670 00:24:38.139163 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7671 00:24:38.142657 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7672 00:24:38.142755 == TX Byte 1 ==
7673 00:24:38.149183 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7674 00:24:38.152482 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7675 00:24:38.152575 ==
7676 00:24:38.155918 Dram Type= 6, Freq= 0, CH_0, rank 0
7677 00:24:38.159221 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7678 00:24:38.159308 ==
7679 00:24:38.174260
7680 00:24:38.177566 TX Vref early break, caculate TX vref
7681 00:24:38.181076 TX Vref=16, minBit 1, minWin=22, winSum=362
7682 00:24:38.183864 TX Vref=18, minBit 8, minWin=22, winSum=379
7683 00:24:38.187575 TX Vref=20, minBit 1, minWin=23, winSum=387
7684 00:24:38.190869 TX Vref=22, minBit 1, minWin=24, winSum=396
7685 00:24:38.194098 TX Vref=24, minBit 1, minWin=24, winSum=410
7686 00:24:38.200455 TX Vref=26, minBit 1, minWin=25, winSum=414
7687 00:24:38.204004 TX Vref=28, minBit 2, minWin=25, winSum=415
7688 00:24:38.206866 TX Vref=30, minBit 9, minWin=24, winSum=411
7689 00:24:38.210401 TX Vref=32, minBit 4, minWin=24, winSum=403
7690 00:24:38.213677 TX Vref=34, minBit 6, minWin=23, winSum=392
7691 00:24:38.220178 [TxChooseVref] Worse bit 2, Min win 25, Win sum 415, Final Vref 28
7692 00:24:38.220289
7693 00:24:38.223327 Final TX Range 0 Vref 28
7694 00:24:38.223413
7695 00:24:38.223477 ==
7696 00:24:38.226961 Dram Type= 6, Freq= 0, CH_0, rank 0
7697 00:24:38.230404 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7698 00:24:38.230498 ==
7699 00:24:38.230564
7700 00:24:38.230623
7701 00:24:38.233961 TX Vref Scan disable
7702 00:24:38.239765 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7703 00:24:38.239863 == TX Byte 0 ==
7704 00:24:38.243520 u2DelayCellOfst[0]=14 cells (4 PI)
7705 00:24:38.246490 u2DelayCellOfst[1]=17 cells (5 PI)
7706 00:24:38.249602 u2DelayCellOfst[2]=14 cells (4 PI)
7707 00:24:38.253484 u2DelayCellOfst[3]=14 cells (4 PI)
7708 00:24:38.256824 u2DelayCellOfst[4]=10 cells (3 PI)
7709 00:24:38.259803 u2DelayCellOfst[5]=0 cells (0 PI)
7710 00:24:38.262907 u2DelayCellOfst[6]=17 cells (5 PI)
7711 00:24:38.266156 u2DelayCellOfst[7]=21 cells (6 PI)
7712 00:24:38.269588 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7713 00:24:38.272775 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7714 00:24:38.276236 == TX Byte 1 ==
7715 00:24:38.279505 u2DelayCellOfst[8]=0 cells (0 PI)
7716 00:24:38.282725 u2DelayCellOfst[9]=0 cells (0 PI)
7717 00:24:38.286168 u2DelayCellOfst[10]=3 cells (1 PI)
7718 00:24:38.289384 u2DelayCellOfst[11]=0 cells (0 PI)
7719 00:24:38.289473 u2DelayCellOfst[12]=7 cells (2 PI)
7720 00:24:38.292770 u2DelayCellOfst[13]=7 cells (2 PI)
7721 00:24:38.296585 u2DelayCellOfst[14]=14 cells (4 PI)
7722 00:24:38.299348 u2DelayCellOfst[15]=10 cells (3 PI)
7723 00:24:38.305846 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7724 00:24:38.309413 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7725 00:24:38.309506 DramC Write-DBI on
7726 00:24:38.312834 ==
7727 00:24:38.315506 Dram Type= 6, Freq= 0, CH_0, rank 0
7728 00:24:38.319042 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7729 00:24:38.319132 ==
7730 00:24:38.319196
7731 00:24:38.319255
7732 00:24:38.322410 TX Vref Scan disable
7733 00:24:38.322492 == TX Byte 0 ==
7734 00:24:38.328779 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7735 00:24:38.328869 == TX Byte 1 ==
7736 00:24:38.332027 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7737 00:24:38.335427 DramC Write-DBI off
7738 00:24:38.335513
7739 00:24:38.335578 [DATLAT]
7740 00:24:38.338646 Freq=1600, CH0 RK0
7741 00:24:38.338730
7742 00:24:38.338794 DATLAT Default: 0xf
7743 00:24:38.342078 0, 0xFFFF, sum = 0
7744 00:24:38.342164 1, 0xFFFF, sum = 0
7745 00:24:38.345459 2, 0xFFFF, sum = 0
7746 00:24:38.345547 3, 0xFFFF, sum = 0
7747 00:24:38.348875 4, 0xFFFF, sum = 0
7748 00:24:38.351834 5, 0xFFFF, sum = 0
7749 00:24:38.351970 6, 0xFFFF, sum = 0
7750 00:24:38.355411 7, 0xFFFF, sum = 0
7751 00:24:38.355495 8, 0xFFFF, sum = 0
7752 00:24:38.358509 9, 0xFFFF, sum = 0
7753 00:24:38.358595 10, 0xFFFF, sum = 0
7754 00:24:38.361533 11, 0xFFFF, sum = 0
7755 00:24:38.361650 12, 0xFFFF, sum = 0
7756 00:24:38.365201 13, 0xFFFF, sum = 0
7757 00:24:38.365335 14, 0x0, sum = 1
7758 00:24:38.368794 15, 0x0, sum = 2
7759 00:24:38.368879 16, 0x0, sum = 3
7760 00:24:38.371490 17, 0x0, sum = 4
7761 00:24:38.371574 best_step = 15
7762 00:24:38.371638
7763 00:24:38.371697 ==
7764 00:24:38.374843 Dram Type= 6, Freq= 0, CH_0, rank 0
7765 00:24:38.381375 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7766 00:24:38.381478 ==
7767 00:24:38.381544 RX Vref Scan: 1
7768 00:24:38.381603
7769 00:24:38.385376 Set Vref Range= 24 -> 127
7770 00:24:38.385462
7771 00:24:38.388155 RX Vref 24 -> 127, step: 1
7772 00:24:38.388238
7773 00:24:38.388302 RX Delay 19 -> 252, step: 4
7774 00:24:38.388361
7775 00:24:38.392020 Set Vref, RX VrefLevel [Byte0]: 24
7776 00:24:38.395032 [Byte1]: 24
7777 00:24:38.398658
7778 00:24:38.398745 Set Vref, RX VrefLevel [Byte0]: 25
7779 00:24:38.402547 [Byte1]: 25
7780 00:24:38.406720
7781 00:24:38.406807 Set Vref, RX VrefLevel [Byte0]: 26
7782 00:24:38.409394 [Byte1]: 26
7783 00:24:38.413729
7784 00:24:38.413858 Set Vref, RX VrefLevel [Byte0]: 27
7785 00:24:38.417151 [Byte1]: 27
7786 00:24:38.421307
7787 00:24:38.421400 Set Vref, RX VrefLevel [Byte0]: 28
7788 00:24:38.424690 [Byte1]: 28
7789 00:24:38.429146
7790 00:24:38.429235 Set Vref, RX VrefLevel [Byte0]: 29
7791 00:24:38.432586 [Byte1]: 29
7792 00:24:38.436830
7793 00:24:38.436919 Set Vref, RX VrefLevel [Byte0]: 30
7794 00:24:38.439829 [Byte1]: 30
7795 00:24:38.444205
7796 00:24:38.444298 Set Vref, RX VrefLevel [Byte0]: 31
7797 00:24:38.447541 [Byte1]: 31
7798 00:24:38.451660
7799 00:24:38.451755 Set Vref, RX VrefLevel [Byte0]: 32
7800 00:24:38.454803 [Byte1]: 32
7801 00:24:38.459210
7802 00:24:38.459300 Set Vref, RX VrefLevel [Byte0]: 33
7803 00:24:38.462424 [Byte1]: 33
7804 00:24:38.466747
7805 00:24:38.466834 Set Vref, RX VrefLevel [Byte0]: 34
7806 00:24:38.470071 [Byte1]: 34
7807 00:24:38.474374
7808 00:24:38.474464 Set Vref, RX VrefLevel [Byte0]: 35
7809 00:24:38.477777 [Byte1]: 35
7810 00:24:38.482244
7811 00:24:38.482339 Set Vref, RX VrefLevel [Byte0]: 36
7812 00:24:38.485600 [Byte1]: 36
7813 00:24:38.489521
7814 00:24:38.489607 Set Vref, RX VrefLevel [Byte0]: 37
7815 00:24:38.492846 [Byte1]: 37
7816 00:24:38.497516
7817 00:24:38.497609 Set Vref, RX VrefLevel [Byte0]: 38
7818 00:24:38.500654 [Byte1]: 38
7819 00:24:38.504683
7820 00:24:38.504774 Set Vref, RX VrefLevel [Byte0]: 39
7821 00:24:38.508099 [Byte1]: 39
7822 00:24:38.512456
7823 00:24:38.512543 Set Vref, RX VrefLevel [Byte0]: 40
7824 00:24:38.515685 [Byte1]: 40
7825 00:24:38.519899
7826 00:24:38.519995 Set Vref, RX VrefLevel [Byte0]: 41
7827 00:24:38.523304 [Byte1]: 41
7828 00:24:38.527411
7829 00:24:38.527501 Set Vref, RX VrefLevel [Byte0]: 42
7830 00:24:38.531065 [Byte1]: 42
7831 00:24:38.535566
7832 00:24:38.535657 Set Vref, RX VrefLevel [Byte0]: 43
7833 00:24:38.538336 [Byte1]: 43
7834 00:24:38.542831
7835 00:24:38.542920 Set Vref, RX VrefLevel [Byte0]: 44
7836 00:24:38.545961 [Byte1]: 44
7837 00:24:38.550551
7838 00:24:38.550643 Set Vref, RX VrefLevel [Byte0]: 45
7839 00:24:38.553932 [Byte1]: 45
7840 00:24:38.557734
7841 00:24:38.557824 Set Vref, RX VrefLevel [Byte0]: 46
7842 00:24:38.560998 [Byte1]: 46
7843 00:24:38.565423
7844 00:24:38.565514 Set Vref, RX VrefLevel [Byte0]: 47
7845 00:24:38.568613 [Byte1]: 47
7846 00:24:38.572778
7847 00:24:38.572868 Set Vref, RX VrefLevel [Byte0]: 48
7848 00:24:38.576441 [Byte1]: 48
7849 00:24:38.581015
7850 00:24:38.581105 Set Vref, RX VrefLevel [Byte0]: 49
7851 00:24:38.583949 [Byte1]: 49
7852 00:24:38.588026
7853 00:24:38.588131 Set Vref, RX VrefLevel [Byte0]: 50
7854 00:24:38.591421 [Byte1]: 50
7855 00:24:38.595474
7856 00:24:38.595562 Set Vref, RX VrefLevel [Byte0]: 51
7857 00:24:38.599899 [Byte1]: 51
7858 00:24:38.603160
7859 00:24:38.603247 Set Vref, RX VrefLevel [Byte0]: 52
7860 00:24:38.606536 [Byte1]: 52
7861 00:24:38.610566
7862 00:24:38.610658 Set Vref, RX VrefLevel [Byte0]: 53
7863 00:24:38.614027 [Byte1]: 53
7864 00:24:38.618414
7865 00:24:38.618512 Set Vref, RX VrefLevel [Byte0]: 54
7866 00:24:38.621598 [Byte1]: 54
7867 00:24:38.626008
7868 00:24:38.626102 Set Vref, RX VrefLevel [Byte0]: 55
7869 00:24:38.629463 [Byte1]: 55
7870 00:24:38.633556
7871 00:24:38.633645 Set Vref, RX VrefLevel [Byte0]: 56
7872 00:24:38.636587 [Byte1]: 56
7873 00:24:38.641432
7874 00:24:38.641531 Set Vref, RX VrefLevel [Byte0]: 57
7875 00:24:38.644118 [Byte1]: 57
7876 00:24:38.648604
7877 00:24:38.648698 Set Vref, RX VrefLevel [Byte0]: 58
7878 00:24:38.652104 [Byte1]: 58
7879 00:24:38.656057
7880 00:24:38.656146 Set Vref, RX VrefLevel [Byte0]: 59
7881 00:24:38.659396 [Byte1]: 59
7882 00:24:38.664022
7883 00:24:38.664117 Set Vref, RX VrefLevel [Byte0]: 60
7884 00:24:38.667013 [Byte1]: 60
7885 00:24:38.671415
7886 00:24:38.671509 Set Vref, RX VrefLevel [Byte0]: 61
7887 00:24:38.674832 [Byte1]: 61
7888 00:24:38.678694
7889 00:24:38.678809 Set Vref, RX VrefLevel [Byte0]: 62
7890 00:24:38.682077 [Byte1]: 62
7891 00:24:38.686420
7892 00:24:38.686512 Set Vref, RX VrefLevel [Byte0]: 63
7893 00:24:38.689572 [Byte1]: 63
7894 00:24:38.693909
7895 00:24:38.694008 Set Vref, RX VrefLevel [Byte0]: 64
7896 00:24:38.697369 [Byte1]: 64
7897 00:24:38.701905
7898 00:24:38.702001 Set Vref, RX VrefLevel [Byte0]: 65
7899 00:24:38.705414 [Byte1]: 65
7900 00:24:38.709114
7901 00:24:38.709231 Set Vref, RX VrefLevel [Byte0]: 66
7902 00:24:38.712874 [Byte1]: 66
7903 00:24:38.717220
7904 00:24:38.717375 Set Vref, RX VrefLevel [Byte0]: 67
7905 00:24:38.719762 [Byte1]: 67
7906 00:24:38.724376
7907 00:24:38.724531 Set Vref, RX VrefLevel [Byte0]: 68
7908 00:24:38.727575 [Byte1]: 68
7909 00:24:38.732088
7910 00:24:38.732189 Set Vref, RX VrefLevel [Byte0]: 69
7911 00:24:38.735222 [Byte1]: 69
7912 00:24:38.739516
7913 00:24:38.739612 Set Vref, RX VrefLevel [Byte0]: 70
7914 00:24:38.742981 [Byte1]: 70
7915 00:24:38.746793
7916 00:24:38.746891 Set Vref, RX VrefLevel [Byte0]: 71
7917 00:24:38.750442 [Byte1]: 71
7918 00:24:38.754914
7919 00:24:38.757795 Set Vref, RX VrefLevel [Byte0]: 72
7920 00:24:38.761035 [Byte1]: 72
7921 00:24:38.761127
7922 00:24:38.764474 Set Vref, RX VrefLevel [Byte0]: 73
7923 00:24:38.767694 [Byte1]: 73
7924 00:24:38.767784
7925 00:24:38.771173 Set Vref, RX VrefLevel [Byte0]: 74
7926 00:24:38.774139 [Byte1]: 74
7927 00:24:38.774261
7928 00:24:38.777926 Final RX Vref Byte 0 = 55 to rank0
7929 00:24:38.780832 Final RX Vref Byte 1 = 57 to rank0
7930 00:24:38.784228 Final RX Vref Byte 0 = 55 to rank1
7931 00:24:38.787397 Final RX Vref Byte 1 = 57 to rank1==
7932 00:24:38.790686 Dram Type= 6, Freq= 0, CH_0, rank 0
7933 00:24:38.797183 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7934 00:24:38.797329 ==
7935 00:24:38.797426 DQS Delay:
7936 00:24:38.797514 DQS0 = 0, DQS1 = 0
7937 00:24:38.800582 DQM Delay:
7938 00:24:38.800687 DQM0 = 128, DQM1 = 124
7939 00:24:38.803862 DQ Delay:
7940 00:24:38.807630 DQ0 =132, DQ1 =130, DQ2 =124, DQ3 =124
7941 00:24:38.810083 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =134
7942 00:24:38.813777 DQ8 =112, DQ9 =110, DQ10 =126, DQ11 =120
7943 00:24:38.817394 DQ12 =130, DQ13 =130, DQ14 =134, DQ15 =132
7944 00:24:38.817525
7945 00:24:38.817621
7946 00:24:38.817692
7947 00:24:38.820179 [DramC_TX_OE_Calibration] TA2
7948 00:24:38.823593 Original DQ_B0 (3 6) =30, OEN = 27
7949 00:24:38.826921 Original DQ_B1 (3 6) =30, OEN = 27
7950 00:24:38.830234 24, 0x0, End_B0=24 End_B1=24
7951 00:24:38.830353 25, 0x0, End_B0=25 End_B1=25
7952 00:24:38.833207 26, 0x0, End_B0=26 End_B1=26
7953 00:24:38.836579 27, 0x0, End_B0=27 End_B1=27
7954 00:24:38.839791 28, 0x0, End_B0=28 End_B1=28
7955 00:24:38.843307 29, 0x0, End_B0=29 End_B1=29
7956 00:24:38.843429 30, 0x0, End_B0=30 End_B1=30
7957 00:24:38.846533 31, 0x4141, End_B0=30 End_B1=30
7958 00:24:38.850190 Byte0 end_step=30 best_step=27
7959 00:24:38.853002 Byte1 end_step=30 best_step=27
7960 00:24:38.856487 Byte0 TX OE(2T, 0.5T) = (3, 3)
7961 00:24:38.860060 Byte1 TX OE(2T, 0.5T) = (3, 3)
7962 00:24:38.860148
7963 00:24:38.860211
7964 00:24:38.866570 [DQSOSCAuto] RK0, (LSB)MR18= 0x1614, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
7965 00:24:38.869684 CH0 RK0: MR19=303, MR18=1614
7966 00:24:38.876259 CH0_RK0: MR19=0x303, MR18=0x1614, DQSOSC=398, MR23=63, INC=23, DEC=15
7967 00:24:38.876371
7968 00:24:38.879095 ----->DramcWriteLeveling(PI) begin...
7969 00:24:38.879183 ==
7970 00:24:38.883271 Dram Type= 6, Freq= 0, CH_0, rank 1
7971 00:24:38.886078 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7972 00:24:38.886166 ==
7973 00:24:38.889142 Write leveling (Byte 0): 36 => 36
7974 00:24:38.892546 Write leveling (Byte 1): 26 => 26
7975 00:24:38.895883 DramcWriteLeveling(PI) end<-----
7976 00:24:38.895971
7977 00:24:38.896036 ==
7978 00:24:38.899268 Dram Type= 6, Freq= 0, CH_0, rank 1
7979 00:24:38.905649 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7980 00:24:38.905748 ==
7981 00:24:38.905816 [Gating] SW mode calibration
7982 00:24:38.915680 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7983 00:24:38.918698 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7984 00:24:38.925658 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7985 00:24:38.928641 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7986 00:24:38.931791 1 4 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
7987 00:24:38.938360 1 4 12 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
7988 00:24:38.941929 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7989 00:24:38.945113 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7990 00:24:38.951423 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7991 00:24:38.954846 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7992 00:24:38.958083 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7993 00:24:38.964926 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7994 00:24:38.968332 1 5 8 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
7995 00:24:38.971178 1 5 12 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 0)
7996 00:24:38.977729 1 5 16 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
7997 00:24:38.981386 1 5 20 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
7998 00:24:38.984933 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7999 00:24:38.991456 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8000 00:24:38.994224 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8001 00:24:38.997548 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8002 00:24:39.004391 1 6 8 | B1->B0 | 2323 4141 | 0 0 | (0 0) (0 0)
8003 00:24:39.007671 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8004 00:24:39.010881 1 6 16 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
8005 00:24:39.017194 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8006 00:24:39.020654 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8007 00:24:39.023685 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8008 00:24:39.030899 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8009 00:24:39.033468 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8010 00:24:39.037145 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8011 00:24:39.043529 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8012 00:24:39.046633 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8013 00:24:39.050477 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8014 00:24:39.056974 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8015 00:24:39.059911 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8016 00:24:39.063365 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8017 00:24:39.069838 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8018 00:24:39.073025 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8019 00:24:39.076506 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8020 00:24:39.083468 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8021 00:24:39.086666 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8022 00:24:39.089537 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8023 00:24:39.096196 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8024 00:24:39.100001 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8025 00:24:39.103079 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8026 00:24:39.109472 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8027 00:24:39.112650 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8028 00:24:39.116485 Total UI for P1: 0, mck2ui 16
8029 00:24:39.119275 best dqsien dly found for B0: ( 1, 9, 6)
8030 00:24:39.122869 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8031 00:24:39.129851 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8032 00:24:39.132760 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8033 00:24:39.136655 Total UI for P1: 0, mck2ui 16
8034 00:24:39.139228 best dqsien dly found for B1: ( 1, 9, 18)
8035 00:24:39.142360 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8036 00:24:39.145550 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8037 00:24:39.145644
8038 00:24:39.148883 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8039 00:24:39.152533 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8040 00:24:39.155775 [Gating] SW calibration Done
8041 00:24:39.155863 ==
8042 00:24:39.159209 Dram Type= 6, Freq= 0, CH_0, rank 1
8043 00:24:39.165699 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8044 00:24:39.165794 ==
8045 00:24:39.165861 RX Vref Scan: 0
8046 00:24:39.165920
8047 00:24:39.168744 RX Vref 0 -> 0, step: 1
8048 00:24:39.168827
8049 00:24:39.172077 RX Delay 0 -> 252, step: 8
8050 00:24:39.175663 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8051 00:24:39.178962 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8052 00:24:39.181974 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
8053 00:24:39.185046 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8054 00:24:39.191674 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8055 00:24:39.194834 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8056 00:24:39.198476 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8057 00:24:39.201811 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8058 00:24:39.205147 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8059 00:24:39.212007 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8060 00:24:39.214621 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8061 00:24:39.218399 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8062 00:24:39.221389 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8063 00:24:39.228146 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8064 00:24:39.231168 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8065 00:24:39.234527 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8066 00:24:39.234610 ==
8067 00:24:39.237996 Dram Type= 6, Freq= 0, CH_0, rank 1
8068 00:24:39.241212 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8069 00:24:39.244922 ==
8070 00:24:39.245003 DQS Delay:
8071 00:24:39.245066 DQS0 = 0, DQS1 = 0
8072 00:24:39.247750 DQM Delay:
8073 00:24:39.247831 DQM0 = 132, DQM1 = 125
8074 00:24:39.251302 DQ Delay:
8075 00:24:39.254328 DQ0 =131, DQ1 =135, DQ2 =131, DQ3 =127
8076 00:24:39.257426 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
8077 00:24:39.260683 DQ8 =115, DQ9 =111, DQ10 =131, DQ11 =119
8078 00:24:39.264552 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
8079 00:24:39.264633
8080 00:24:39.264696
8081 00:24:39.264755 ==
8082 00:24:39.267688 Dram Type= 6, Freq= 0, CH_0, rank 1
8083 00:24:39.271078 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8084 00:24:39.271160 ==
8085 00:24:39.274071
8086 00:24:39.274152
8087 00:24:39.274215 TX Vref Scan disable
8088 00:24:39.277489 == TX Byte 0 ==
8089 00:24:39.280384 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8090 00:24:39.283722 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8091 00:24:39.286953 == TX Byte 1 ==
8092 00:24:39.290664 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8093 00:24:39.293764 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8094 00:24:39.296977 ==
8095 00:24:39.297057 Dram Type= 6, Freq= 0, CH_0, rank 1
8096 00:24:39.303409 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8097 00:24:39.303491 ==
8098 00:24:39.316741
8099 00:24:39.320042 TX Vref early break, caculate TX vref
8100 00:24:39.323576 TX Vref=16, minBit 2, minWin=23, winSum=379
8101 00:24:39.326858 TX Vref=18, minBit 8, minWin=23, winSum=387
8102 00:24:39.329952 TX Vref=20, minBit 2, minWin=24, winSum=398
8103 00:24:39.333412 TX Vref=22, minBit 9, minWin=24, winSum=406
8104 00:24:39.336445 TX Vref=24, minBit 1, minWin=25, winSum=409
8105 00:24:39.343225 TX Vref=26, minBit 1, minWin=25, winSum=415
8106 00:24:39.346139 TX Vref=28, minBit 1, minWin=25, winSum=417
8107 00:24:39.349418 TX Vref=30, minBit 1, minWin=25, winSum=415
8108 00:24:39.352691 TX Vref=32, minBit 0, minWin=25, winSum=408
8109 00:24:39.356092 TX Vref=34, minBit 0, minWin=24, winSum=395
8110 00:24:39.362770 [TxChooseVref] Worse bit 1, Min win 25, Win sum 417, Final Vref 28
8111 00:24:39.362859
8112 00:24:39.366035 Final TX Range 0 Vref 28
8113 00:24:39.366116
8114 00:24:39.366179 ==
8115 00:24:39.369341 Dram Type= 6, Freq= 0, CH_0, rank 1
8116 00:24:39.372486 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8117 00:24:39.372567 ==
8118 00:24:39.372630
8119 00:24:39.372688
8120 00:24:39.376183 TX Vref Scan disable
8121 00:24:39.382724 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8122 00:24:39.382805 == TX Byte 0 ==
8123 00:24:39.386048 u2DelayCellOfst[0]=10 cells (3 PI)
8124 00:24:39.389486 u2DelayCellOfst[1]=14 cells (4 PI)
8125 00:24:39.392287 u2DelayCellOfst[2]=7 cells (2 PI)
8126 00:24:39.396411 u2DelayCellOfst[3]=10 cells (3 PI)
8127 00:24:39.399219 u2DelayCellOfst[4]=7 cells (2 PI)
8128 00:24:39.402118 u2DelayCellOfst[5]=0 cells (0 PI)
8129 00:24:39.405519 u2DelayCellOfst[6]=14 cells (4 PI)
8130 00:24:39.408772 u2DelayCellOfst[7]=14 cells (4 PI)
8131 00:24:39.412111 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8132 00:24:39.415659 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8133 00:24:39.419139 == TX Byte 1 ==
8134 00:24:39.421853 u2DelayCellOfst[8]=0 cells (0 PI)
8135 00:24:39.425453 u2DelayCellOfst[9]=0 cells (0 PI)
8136 00:24:39.428898 u2DelayCellOfst[10]=7 cells (2 PI)
8137 00:24:39.431903 u2DelayCellOfst[11]=0 cells (0 PI)
8138 00:24:39.431985 u2DelayCellOfst[12]=10 cells (3 PI)
8139 00:24:39.435212 u2DelayCellOfst[13]=10 cells (3 PI)
8140 00:24:39.438850 u2DelayCellOfst[14]=14 cells (4 PI)
8141 00:24:39.441615 u2DelayCellOfst[15]=10 cells (3 PI)
8142 00:24:39.448174 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8143 00:24:39.451421 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8144 00:24:39.455003 DramC Write-DBI on
8145 00:24:39.455083 ==
8146 00:24:39.458202 Dram Type= 6, Freq= 0, CH_0, rank 1
8147 00:24:39.461844 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8148 00:24:39.461925 ==
8149 00:24:39.461988
8150 00:24:39.462046
8151 00:24:39.465441 TX Vref Scan disable
8152 00:24:39.465521 == TX Byte 0 ==
8153 00:24:39.471355 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8154 00:24:39.471436 == TX Byte 1 ==
8155 00:24:39.478070 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8156 00:24:39.478151 DramC Write-DBI off
8157 00:24:39.478214
8158 00:24:39.478272 [DATLAT]
8159 00:24:39.481144 Freq=1600, CH0 RK1
8160 00:24:39.481225
8161 00:24:39.481331 DATLAT Default: 0xf
8162 00:24:39.484115 0, 0xFFFF, sum = 0
8163 00:24:39.487403 1, 0xFFFF, sum = 0
8164 00:24:39.487485 2, 0xFFFF, sum = 0
8165 00:24:39.490798 3, 0xFFFF, sum = 0
8166 00:24:39.490879 4, 0xFFFF, sum = 0
8167 00:24:39.493968 5, 0xFFFF, sum = 0
8168 00:24:39.494050 6, 0xFFFF, sum = 0
8169 00:24:39.497543 7, 0xFFFF, sum = 0
8170 00:24:39.497624 8, 0xFFFF, sum = 0
8171 00:24:39.500776 9, 0xFFFF, sum = 0
8172 00:24:39.500857 10, 0xFFFF, sum = 0
8173 00:24:39.503792 11, 0xFFFF, sum = 0
8174 00:24:39.503873 12, 0xFFFF, sum = 0
8175 00:24:39.507376 13, 0xFFFF, sum = 0
8176 00:24:39.507457 14, 0x0, sum = 1
8177 00:24:39.510503 15, 0x0, sum = 2
8178 00:24:39.510584 16, 0x0, sum = 3
8179 00:24:39.513765 17, 0x0, sum = 4
8180 00:24:39.513846 best_step = 15
8181 00:24:39.513909
8182 00:24:39.513966 ==
8183 00:24:39.517115 Dram Type= 6, Freq= 0, CH_0, rank 1
8184 00:24:39.523817 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8185 00:24:39.523899 ==
8186 00:24:39.523963 RX Vref Scan: 0
8187 00:24:39.524022
8188 00:24:39.527319 RX Vref 0 -> 0, step: 1
8189 00:24:39.527400
8190 00:24:39.530621 RX Delay 11 -> 252, step: 4
8191 00:24:39.533310 iDelay=191, Bit 0, Center 126 (79 ~ 174) 96
8192 00:24:39.536940 iDelay=191, Bit 1, Center 130 (79 ~ 182) 104
8193 00:24:39.543506 iDelay=191, Bit 2, Center 124 (75 ~ 174) 100
8194 00:24:39.546768 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
8195 00:24:39.549918 iDelay=191, Bit 4, Center 132 (83 ~ 182) 100
8196 00:24:39.553509 iDelay=191, Bit 5, Center 120 (67 ~ 174) 108
8197 00:24:39.556959 iDelay=191, Bit 6, Center 136 (87 ~ 186) 100
8198 00:24:39.563360 iDelay=191, Bit 7, Center 134 (83 ~ 186) 104
8199 00:24:39.566722 iDelay=191, Bit 8, Center 114 (63 ~ 166) 104
8200 00:24:39.570397 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8201 00:24:39.573311 iDelay=191, Bit 10, Center 126 (75 ~ 178) 104
8202 00:24:39.576490 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8203 00:24:39.583230 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8204 00:24:39.586897 iDelay=191, Bit 13, Center 130 (79 ~ 182) 104
8205 00:24:39.590334 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8206 00:24:39.592821 iDelay=191, Bit 15, Center 130 (79 ~ 182) 104
8207 00:24:39.592901 ==
8208 00:24:39.596480 Dram Type= 6, Freq= 0, CH_0, rank 1
8209 00:24:39.603042 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8210 00:24:39.603124 ==
8211 00:24:39.603187 DQS Delay:
8212 00:24:39.606038 DQS0 = 0, DQS1 = 0
8213 00:24:39.606118 DQM Delay:
8214 00:24:39.609794 DQM0 = 128, DQM1 = 124
8215 00:24:39.609875 DQ Delay:
8216 00:24:39.612590 DQ0 =126, DQ1 =130, DQ2 =124, DQ3 =126
8217 00:24:39.615884 DQ4 =132, DQ5 =120, DQ6 =136, DQ7 =134
8218 00:24:39.619108 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =118
8219 00:24:39.622605 DQ12 =128, DQ13 =130, DQ14 =136, DQ15 =130
8220 00:24:39.622687
8221 00:24:39.622750
8222 00:24:39.622809
8223 00:24:39.625780 [DramC_TX_OE_Calibration] TA2
8224 00:24:39.629168 Original DQ_B0 (3 6) =30, OEN = 27
8225 00:24:39.632283 Original DQ_B1 (3 6) =30, OEN = 27
8226 00:24:39.635856 24, 0x0, End_B0=24 End_B1=24
8227 00:24:39.639067 25, 0x0, End_B0=25 End_B1=25
8228 00:24:39.639151 26, 0x0, End_B0=26 End_B1=26
8229 00:24:39.642295 27, 0x0, End_B0=27 End_B1=27
8230 00:24:39.645812 28, 0x0, End_B0=28 End_B1=28
8231 00:24:39.649137 29, 0x0, End_B0=29 End_B1=29
8232 00:24:39.649234 30, 0x0, End_B0=30 End_B1=30
8233 00:24:39.652221 31, 0x4141, End_B0=30 End_B1=30
8234 00:24:39.655674 Byte0 end_step=30 best_step=27
8235 00:24:39.658653 Byte1 end_step=30 best_step=27
8236 00:24:39.662038 Byte0 TX OE(2T, 0.5T) = (3, 3)
8237 00:24:39.665437 Byte1 TX OE(2T, 0.5T) = (3, 3)
8238 00:24:39.665517
8239 00:24:39.665579
8240 00:24:39.671923 [DQSOSCAuto] RK1, (LSB)MR18= 0x1815, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 397 ps
8241 00:24:39.675535 CH0 RK1: MR19=303, MR18=1815
8242 00:24:39.681694 CH0_RK1: MR19=0x303, MR18=0x1815, DQSOSC=397, MR23=63, INC=23, DEC=15
8243 00:24:39.684936 [RxdqsGatingPostProcess] freq 1600
8244 00:24:39.691382 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8245 00:24:39.694757 best DQS0 dly(2T, 0.5T) = (1, 1)
8246 00:24:39.694838 best DQS1 dly(2T, 0.5T) = (1, 1)
8247 00:24:39.697976 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8248 00:24:39.701831 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8249 00:24:39.705180 best DQS0 dly(2T, 0.5T) = (1, 1)
8250 00:24:39.708450 best DQS1 dly(2T, 0.5T) = (1, 1)
8251 00:24:39.711847 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8252 00:24:39.715177 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8253 00:24:39.718047 Pre-setting of DQS Precalculation
8254 00:24:39.721585 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8255 00:24:39.724541 ==
8256 00:24:39.728206 Dram Type= 6, Freq= 0, CH_1, rank 0
8257 00:24:39.730939 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8258 00:24:39.731021 ==
8259 00:24:39.737659 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8260 00:24:39.740909 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8261 00:24:39.744110 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8262 00:24:39.750933 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8263 00:24:39.759465 [CA 0] Center 42 (13~72) winsize 60
8264 00:24:39.762557 [CA 1] Center 43 (13~73) winsize 61
8265 00:24:39.765798 [CA 2] Center 39 (9~69) winsize 61
8266 00:24:39.769163 [CA 3] Center 38 (8~68) winsize 61
8267 00:24:39.772581 [CA 4] Center 38 (8~69) winsize 62
8268 00:24:39.775863 [CA 5] Center 37 (8~67) winsize 60
8269 00:24:39.775944
8270 00:24:39.779357 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8271 00:24:39.779437
8272 00:24:39.785603 [CATrainingPosCal] consider 1 rank data
8273 00:24:39.785684 u2DelayCellTimex100 = 275/100 ps
8274 00:24:39.792184 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8275 00:24:39.795768 CA1 delay=43 (13~73),Diff = 6 PI (21 cell)
8276 00:24:39.798517 CA2 delay=39 (9~69),Diff = 2 PI (7 cell)
8277 00:24:39.802060 CA3 delay=38 (8~68),Diff = 1 PI (3 cell)
8278 00:24:39.805318 CA4 delay=38 (8~69),Diff = 1 PI (3 cell)
8279 00:24:39.808508 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8280 00:24:39.808592
8281 00:24:39.811589 CA PerBit enable=1, Macro0, CA PI delay=37
8282 00:24:39.811671
8283 00:24:39.815081 [CBTSetCACLKResult] CA Dly = 37
8284 00:24:39.818440 CS Dly: 8 (0~39)
8285 00:24:39.822234 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8286 00:24:39.825586 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8287 00:24:39.825718 ==
8288 00:24:39.827864 Dram Type= 6, Freq= 0, CH_1, rank 1
8289 00:24:39.834624 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8290 00:24:39.834719 ==
8291 00:24:39.838003 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8292 00:24:39.844894 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8293 00:24:39.847880 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8294 00:24:39.854644 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8295 00:24:39.862557 [CA 0] Center 42 (12~72) winsize 61
8296 00:24:39.865520 [CA 1] Center 42 (12~72) winsize 61
8297 00:24:39.868952 [CA 2] Center 38 (8~68) winsize 61
8298 00:24:39.872384 [CA 3] Center 37 (8~67) winsize 60
8299 00:24:39.875835 [CA 4] Center 37 (8~67) winsize 60
8300 00:24:39.878554 [CA 5] Center 37 (7~67) winsize 61
8301 00:24:39.878700
8302 00:24:39.882446 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8303 00:24:39.882551
8304 00:24:39.888942 [CATrainingPosCal] consider 2 rank data
8305 00:24:39.889031 u2DelayCellTimex100 = 275/100 ps
8306 00:24:39.895608 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8307 00:24:39.898514 CA1 delay=42 (13~72),Diff = 5 PI (17 cell)
8308 00:24:39.901710 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8309 00:24:39.905185 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8310 00:24:39.909043 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8311 00:24:39.911880 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8312 00:24:39.911990
8313 00:24:39.915310 CA PerBit enable=1, Macro0, CA PI delay=37
8314 00:24:39.915452
8315 00:24:39.918642 [CBTSetCACLKResult] CA Dly = 37
8316 00:24:39.922404 CS Dly: 10 (0~43)
8317 00:24:39.925417 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8318 00:24:39.928008 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8319 00:24:39.928097
8320 00:24:39.932326 ----->DramcWriteLeveling(PI) begin...
8321 00:24:39.932411 ==
8322 00:24:39.934868 Dram Type= 6, Freq= 0, CH_1, rank 0
8323 00:24:39.941414 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8324 00:24:39.941515 ==
8325 00:24:39.944849 Write leveling (Byte 0): 23 => 23
8326 00:24:39.948271 Write leveling (Byte 1): 27 => 27
8327 00:24:39.948387 DramcWriteLeveling(PI) end<-----
8328 00:24:39.951424
8329 00:24:39.951509 ==
8330 00:24:39.954438 Dram Type= 6, Freq= 0, CH_1, rank 0
8331 00:24:39.957739 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8332 00:24:39.957834 ==
8333 00:24:39.961625 [Gating] SW mode calibration
8334 00:24:39.968030 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8335 00:24:39.971182 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8336 00:24:39.977895 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8337 00:24:39.981280 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8338 00:24:39.984686 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8339 00:24:39.990955 1 4 12 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
8340 00:24:39.994625 1 4 16 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
8341 00:24:39.997749 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8342 00:24:40.004333 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8343 00:24:40.007903 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8344 00:24:40.011005 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8345 00:24:40.017251 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8346 00:24:40.020775 1 5 8 | B1->B0 | 3434 3131 | 1 0 | (1 0) (0 1)
8347 00:24:40.024055 1 5 12 | B1->B0 | 3333 2424 | 0 0 | (0 1) (0 0)
8348 00:24:40.030535 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8349 00:24:40.033849 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8350 00:24:40.037408 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8351 00:24:40.043795 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8352 00:24:40.047120 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8353 00:24:40.050255 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8354 00:24:40.057015 1 6 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
8355 00:24:40.060545 1 6 12 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
8356 00:24:40.063550 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8357 00:24:40.070367 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8358 00:24:40.073249 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8359 00:24:40.076813 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8360 00:24:40.083115 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8361 00:24:40.086400 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8362 00:24:40.089898 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8363 00:24:40.096487 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8364 00:24:40.099976 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8365 00:24:40.102853 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8366 00:24:40.109616 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8367 00:24:40.112794 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8368 00:24:40.116295 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8369 00:24:40.122701 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8370 00:24:40.126595 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8371 00:24:40.129383 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8372 00:24:40.136310 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8373 00:24:40.139407 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8374 00:24:40.142987 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8375 00:24:40.149357 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8376 00:24:40.152753 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8377 00:24:40.155523 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8378 00:24:40.162232 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8379 00:24:40.165693 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8380 00:24:40.172022 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8381 00:24:40.172121 Total UI for P1: 0, mck2ui 16
8382 00:24:40.175538 best dqsien dly found for B0: ( 1, 9, 10)
8383 00:24:40.181810 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8384 00:24:40.185513 Total UI for P1: 0, mck2ui 16
8385 00:24:40.188788 best dqsien dly found for B1: ( 1, 9, 14)
8386 00:24:40.191811 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8387 00:24:40.195665 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8388 00:24:40.195748
8389 00:24:40.198421 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8390 00:24:40.201711 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8391 00:24:40.205543 [Gating] SW calibration Done
8392 00:24:40.205626 ==
8393 00:24:40.208491 Dram Type= 6, Freq= 0, CH_1, rank 0
8394 00:24:40.211690 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8395 00:24:40.214987 ==
8396 00:24:40.215072 RX Vref Scan: 0
8397 00:24:40.215158
8398 00:24:40.218217 RX Vref 0 -> 0, step: 1
8399 00:24:40.218305
8400 00:24:40.218391 RX Delay 0 -> 252, step: 8
8401 00:24:40.225032 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8402 00:24:40.228007 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8403 00:24:40.231676 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8404 00:24:40.234490 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8405 00:24:40.241140 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8406 00:24:40.244217 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8407 00:24:40.247863 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8408 00:24:40.250872 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8409 00:24:40.254225 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8410 00:24:40.261441 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8411 00:24:40.264823 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8412 00:24:40.267852 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8413 00:24:40.270858 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8414 00:24:40.274165 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8415 00:24:40.281095 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8416 00:24:40.284209 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8417 00:24:40.284300 ==
8418 00:24:40.287555 Dram Type= 6, Freq= 0, CH_1, rank 0
8419 00:24:40.290508 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8420 00:24:40.290595 ==
8421 00:24:40.294035 DQS Delay:
8422 00:24:40.294122 DQS0 = 0, DQS1 = 0
8423 00:24:40.297434 DQM Delay:
8424 00:24:40.297519 DQM0 = 135, DQM1 = 130
8425 00:24:40.297605 DQ Delay:
8426 00:24:40.300329 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8427 00:24:40.306986 DQ4 =131, DQ5 =143, DQ6 =147, DQ7 =131
8428 00:24:40.310341 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =127
8429 00:24:40.313744 DQ12 =139, DQ13 =143, DQ14 =135, DQ15 =135
8430 00:24:40.313829
8431 00:24:40.313913
8432 00:24:40.313993 ==
8433 00:24:40.316994 Dram Type= 6, Freq= 0, CH_1, rank 0
8434 00:24:40.320310 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8435 00:24:40.320395 ==
8436 00:24:40.320460
8437 00:24:40.320520
8438 00:24:40.323437 TX Vref Scan disable
8439 00:24:40.326781 == TX Byte 0 ==
8440 00:24:40.330150 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8441 00:24:40.333552 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8442 00:24:40.336937 == TX Byte 1 ==
8443 00:24:40.340135 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8444 00:24:40.343472 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8445 00:24:40.343553 ==
8446 00:24:40.346160 Dram Type= 6, Freq= 0, CH_1, rank 0
8447 00:24:40.352878 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8448 00:24:40.352964 ==
8449 00:24:40.366214
8450 00:24:40.369985 TX Vref early break, caculate TX vref
8451 00:24:40.372403 TX Vref=16, minBit 9, minWin=21, winSum=368
8452 00:24:40.375757 TX Vref=18, minBit 8, minWin=22, winSum=379
8453 00:24:40.379097 TX Vref=20, minBit 8, minWin=23, winSum=391
8454 00:24:40.382475 TX Vref=22, minBit 8, minWin=23, winSum=399
8455 00:24:40.385513 TX Vref=24, minBit 8, minWin=24, winSum=407
8456 00:24:40.392504 TX Vref=26, minBit 8, minWin=25, winSum=415
8457 00:24:40.395800 TX Vref=28, minBit 9, minWin=25, winSum=417
8458 00:24:40.399375 TX Vref=30, minBit 9, minWin=24, winSum=417
8459 00:24:40.402440 TX Vref=32, minBit 9, minWin=24, winSum=406
8460 00:24:40.405572 TX Vref=34, minBit 11, minWin=23, winSum=399
8461 00:24:40.408839 TX Vref=36, minBit 0, minWin=23, winSum=387
8462 00:24:40.415526 [TxChooseVref] Worse bit 9, Min win 25, Win sum 417, Final Vref 28
8463 00:24:40.415613
8464 00:24:40.419072 Final TX Range 0 Vref 28
8465 00:24:40.419157
8466 00:24:40.419221 ==
8467 00:24:40.421892 Dram Type= 6, Freq= 0, CH_1, rank 0
8468 00:24:40.425663 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8469 00:24:40.425747 ==
8470 00:24:40.428465
8471 00:24:40.428545
8472 00:24:40.428608 TX Vref Scan disable
8473 00:24:40.435138 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8474 00:24:40.435220 == TX Byte 0 ==
8475 00:24:40.438572 u2DelayCellOfst[0]=10 cells (3 PI)
8476 00:24:40.442111 u2DelayCellOfst[1]=7 cells (2 PI)
8477 00:24:40.445464 u2DelayCellOfst[2]=0 cells (0 PI)
8478 00:24:40.448426 u2DelayCellOfst[3]=3 cells (1 PI)
8479 00:24:40.451670 u2DelayCellOfst[4]=7 cells (2 PI)
8480 00:24:40.455179 u2DelayCellOfst[5]=14 cells (4 PI)
8481 00:24:40.458194 u2DelayCellOfst[6]=14 cells (4 PI)
8482 00:24:40.461645 u2DelayCellOfst[7]=3 cells (1 PI)
8483 00:24:40.465000 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8484 00:24:40.468280 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8485 00:24:40.471676 == TX Byte 1 ==
8486 00:24:40.474406 u2DelayCellOfst[8]=0 cells (0 PI)
8487 00:24:40.477780 u2DelayCellOfst[9]=3 cells (1 PI)
8488 00:24:40.481633 u2DelayCellOfst[10]=10 cells (3 PI)
8489 00:24:40.484583 u2DelayCellOfst[11]=3 cells (1 PI)
8490 00:24:40.487514 u2DelayCellOfst[12]=14 cells (4 PI)
8491 00:24:40.490942 u2DelayCellOfst[13]=14 cells (4 PI)
8492 00:24:40.494049 u2DelayCellOfst[14]=17 cells (5 PI)
8493 00:24:40.498088 u2DelayCellOfst[15]=17 cells (5 PI)
8494 00:24:40.500886 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8495 00:24:40.504406 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8496 00:24:40.507630 DramC Write-DBI on
8497 00:24:40.507721 ==
8498 00:24:40.510936 Dram Type= 6, Freq= 0, CH_1, rank 0
8499 00:24:40.514000 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8500 00:24:40.514089 ==
8501 00:24:40.514174
8502 00:24:40.514255
8503 00:24:40.517427 TX Vref Scan disable
8504 00:24:40.517539 == TX Byte 0 ==
8505 00:24:40.524000 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8506 00:24:40.524120 == TX Byte 1 ==
8507 00:24:40.527702 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8508 00:24:40.530464 DramC Write-DBI off
8509 00:24:40.530571
8510 00:24:40.530666 [DATLAT]
8511 00:24:40.534132 Freq=1600, CH1 RK0
8512 00:24:40.534240
8513 00:24:40.534334 DATLAT Default: 0xf
8514 00:24:40.537349 0, 0xFFFF, sum = 0
8515 00:24:40.540547 1, 0xFFFF, sum = 0
8516 00:24:40.540660 2, 0xFFFF, sum = 0
8517 00:24:40.544189 3, 0xFFFF, sum = 0
8518 00:24:40.544297 4, 0xFFFF, sum = 0
8519 00:24:40.546962 5, 0xFFFF, sum = 0
8520 00:24:40.547070 6, 0xFFFF, sum = 0
8521 00:24:40.550376 7, 0xFFFF, sum = 0
8522 00:24:40.550486 8, 0xFFFF, sum = 0
8523 00:24:40.553701 9, 0xFFFF, sum = 0
8524 00:24:40.553811 10, 0xFFFF, sum = 0
8525 00:24:40.557039 11, 0xFFFF, sum = 0
8526 00:24:40.557146 12, 0xFFFF, sum = 0
8527 00:24:40.560553 13, 0xFFFF, sum = 0
8528 00:24:40.560661 14, 0x0, sum = 1
8529 00:24:40.563988 15, 0x0, sum = 2
8530 00:24:40.564096 16, 0x0, sum = 3
8531 00:24:40.566662 17, 0x0, sum = 4
8532 00:24:40.566771 best_step = 15
8533 00:24:40.566864
8534 00:24:40.566954 ==
8535 00:24:40.570133 Dram Type= 6, Freq= 0, CH_1, rank 0
8536 00:24:40.576947 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8537 00:24:40.577055 ==
8538 00:24:40.577148 RX Vref Scan: 1
8539 00:24:40.577238
8540 00:24:40.580118 Set Vref Range= 24 -> 127
8541 00:24:40.580220
8542 00:24:40.583008 RX Vref 24 -> 127, step: 1
8543 00:24:40.583113
8544 00:24:40.586597 RX Delay 19 -> 252, step: 4
8545 00:24:40.586702
8546 00:24:40.589929 Set Vref, RX VrefLevel [Byte0]: 24
8547 00:24:40.590032 [Byte1]: 24
8548 00:24:40.594117
8549 00:24:40.594221 Set Vref, RX VrefLevel [Byte0]: 25
8550 00:24:40.597907 [Byte1]: 25
8551 00:24:40.601570
8552 00:24:40.601675 Set Vref, RX VrefLevel [Byte0]: 26
8553 00:24:40.605422 [Byte1]: 26
8554 00:24:40.609748
8555 00:24:40.609856 Set Vref, RX VrefLevel [Byte0]: 27
8556 00:24:40.612709 [Byte1]: 27
8557 00:24:40.616994
8558 00:24:40.617101 Set Vref, RX VrefLevel [Byte0]: 28
8559 00:24:40.620127 [Byte1]: 28
8560 00:24:40.624579
8561 00:24:40.624674 Set Vref, RX VrefLevel [Byte0]: 29
8562 00:24:40.627656 [Byte1]: 29
8563 00:24:40.632025
8564 00:24:40.632111 Set Vref, RX VrefLevel [Byte0]: 30
8565 00:24:40.635745 [Byte1]: 30
8566 00:24:40.639948
8567 00:24:40.640035 Set Vref, RX VrefLevel [Byte0]: 31
8568 00:24:40.642878 [Byte1]: 31
8569 00:24:40.647439
8570 00:24:40.647527 Set Vref, RX VrefLevel [Byte0]: 32
8571 00:24:40.650841 [Byte1]: 32
8572 00:24:40.654861
8573 00:24:40.654946 Set Vref, RX VrefLevel [Byte0]: 33
8574 00:24:40.658090 [Byte1]: 33
8575 00:24:40.662401
8576 00:24:40.662487 Set Vref, RX VrefLevel [Byte0]: 34
8577 00:24:40.665835 [Byte1]: 34
8578 00:24:40.669698
8579 00:24:40.669792 Set Vref, RX VrefLevel [Byte0]: 35
8580 00:24:40.672998 [Byte1]: 35
8581 00:24:40.677430
8582 00:24:40.677515 Set Vref, RX VrefLevel [Byte0]: 36
8583 00:24:40.680764 [Byte1]: 36
8584 00:24:40.684862
8585 00:24:40.684945 Set Vref, RX VrefLevel [Byte0]: 37
8586 00:24:40.688069 [Byte1]: 37
8587 00:24:40.692696
8588 00:24:40.692785 Set Vref, RX VrefLevel [Byte0]: 38
8589 00:24:40.695977 [Byte1]: 38
8590 00:24:40.700157
8591 00:24:40.700240 Set Vref, RX VrefLevel [Byte0]: 39
8592 00:24:40.703783 [Byte1]: 39
8593 00:24:40.707938
8594 00:24:40.708022 Set Vref, RX VrefLevel [Byte0]: 40
8595 00:24:40.710884 [Byte1]: 40
8596 00:24:40.715320
8597 00:24:40.715405 Set Vref, RX VrefLevel [Byte0]: 41
8598 00:24:40.719406 [Byte1]: 41
8599 00:24:40.723055
8600 00:24:40.723143 Set Vref, RX VrefLevel [Byte0]: 42
8601 00:24:40.726424 [Byte1]: 42
8602 00:24:40.730722
8603 00:24:40.730830 Set Vref, RX VrefLevel [Byte0]: 43
8604 00:24:40.734089 [Byte1]: 43
8605 00:24:40.738187
8606 00:24:40.738299 Set Vref, RX VrefLevel [Byte0]: 44
8607 00:24:40.741293 [Byte1]: 44
8608 00:24:40.745695
8609 00:24:40.745804 Set Vref, RX VrefLevel [Byte0]: 45
8610 00:24:40.749126 [Byte1]: 45
8611 00:24:40.753475
8612 00:24:40.753581 Set Vref, RX VrefLevel [Byte0]: 46
8613 00:24:40.756804 [Byte1]: 46
8614 00:24:40.760776
8615 00:24:40.760882 Set Vref, RX VrefLevel [Byte0]: 47
8616 00:24:40.763988 [Byte1]: 47
8617 00:24:40.768527
8618 00:24:40.768636 Set Vref, RX VrefLevel [Byte0]: 48
8619 00:24:40.772105 [Byte1]: 48
8620 00:24:40.775764
8621 00:24:40.775871 Set Vref, RX VrefLevel [Byte0]: 49
8622 00:24:40.779116 [Byte1]: 49
8623 00:24:40.783571
8624 00:24:40.783679 Set Vref, RX VrefLevel [Byte0]: 50
8625 00:24:40.786769 [Byte1]: 50
8626 00:24:40.791139
8627 00:24:40.791247 Set Vref, RX VrefLevel [Byte0]: 51
8628 00:24:40.794531 [Byte1]: 51
8629 00:24:40.798766
8630 00:24:40.798877 Set Vref, RX VrefLevel [Byte0]: 52
8631 00:24:40.801703 [Byte1]: 52
8632 00:24:40.806166
8633 00:24:40.806274 Set Vref, RX VrefLevel [Byte0]: 53
8634 00:24:40.809738 [Byte1]: 53
8635 00:24:40.814070
8636 00:24:40.814179 Set Vref, RX VrefLevel [Byte0]: 54
8637 00:24:40.817186 [Byte1]: 54
8638 00:24:40.821451
8639 00:24:40.821567 Set Vref, RX VrefLevel [Byte0]: 55
8640 00:24:40.825057 [Byte1]: 55
8641 00:24:40.828828
8642 00:24:40.828936 Set Vref, RX VrefLevel [Byte0]: 56
8643 00:24:40.831991 [Byte1]: 56
8644 00:24:40.836661
8645 00:24:40.836771 Set Vref, RX VrefLevel [Byte0]: 57
8646 00:24:40.840160 [Byte1]: 57
8647 00:24:40.844050
8648 00:24:40.844159 Set Vref, RX VrefLevel [Byte0]: 58
8649 00:24:40.847466 [Byte1]: 58
8650 00:24:40.851350
8651 00:24:40.851463 Set Vref, RX VrefLevel [Byte0]: 59
8652 00:24:40.854935 [Byte1]: 59
8653 00:24:40.859582
8654 00:24:40.859670 Set Vref, RX VrefLevel [Byte0]: 60
8655 00:24:40.862478 [Byte1]: 60
8656 00:24:40.867156
8657 00:24:40.867242 Set Vref, RX VrefLevel [Byte0]: 61
8658 00:24:40.870173 [Byte1]: 61
8659 00:24:40.874277
8660 00:24:40.874363 Set Vref, RX VrefLevel [Byte0]: 62
8661 00:24:40.877483 [Byte1]: 62
8662 00:24:40.881925
8663 00:24:40.882010 Set Vref, RX VrefLevel [Byte0]: 63
8664 00:24:40.885041 [Byte1]: 63
8665 00:24:40.889559
8666 00:24:40.889646 Set Vref, RX VrefLevel [Byte0]: 64
8667 00:24:40.892934 [Byte1]: 64
8668 00:24:40.896991
8669 00:24:40.897078 Set Vref, RX VrefLevel [Byte0]: 65
8670 00:24:40.900099 [Byte1]: 65
8671 00:24:40.904675
8672 00:24:40.904761 Set Vref, RX VrefLevel [Byte0]: 66
8673 00:24:40.908193 [Byte1]: 66
8674 00:24:40.912290
8675 00:24:40.912400 Set Vref, RX VrefLevel [Byte0]: 67
8676 00:24:40.915543 [Byte1]: 67
8677 00:24:40.919913
8678 00:24:40.920004 Set Vref, RX VrefLevel [Byte0]: 68
8679 00:24:40.923213 [Byte1]: 68
8680 00:24:40.927113
8681 00:24:40.927200 Set Vref, RX VrefLevel [Byte0]: 69
8682 00:24:40.930812 [Byte1]: 69
8683 00:24:40.934889
8684 00:24:40.934976 Set Vref, RX VrefLevel [Byte0]: 70
8685 00:24:40.938433 [Byte1]: 70
8686 00:24:40.942884
8687 00:24:40.942970 Set Vref, RX VrefLevel [Byte0]: 71
8688 00:24:40.945797 [Byte1]: 71
8689 00:24:40.950079
8690 00:24:40.950165 Final RX Vref Byte 0 = 62 to rank0
8691 00:24:40.953251 Final RX Vref Byte 1 = 55 to rank0
8692 00:24:40.956383 Final RX Vref Byte 0 = 62 to rank1
8693 00:24:40.960726 Final RX Vref Byte 1 = 55 to rank1==
8694 00:24:40.962961 Dram Type= 6, Freq= 0, CH_1, rank 0
8695 00:24:40.970160 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8696 00:24:40.970264 ==
8697 00:24:40.970351 DQS Delay:
8698 00:24:40.973370 DQS0 = 0, DQS1 = 0
8699 00:24:40.973455 DQM Delay:
8700 00:24:40.973541 DQM0 = 134, DQM1 = 128
8701 00:24:40.976267 DQ Delay:
8702 00:24:40.980192 DQ0 =138, DQ1 =132, DQ2 =120, DQ3 =132
8703 00:24:40.983423 DQ4 =130, DQ5 =144, DQ6 =146, DQ7 =130
8704 00:24:40.986784 DQ8 =112, DQ9 =114, DQ10 =128, DQ11 =122
8705 00:24:40.989729 DQ12 =138, DQ13 =136, DQ14 =136, DQ15 =140
8706 00:24:40.989815
8707 00:24:40.989900
8708 00:24:40.989980
8709 00:24:40.992847 [DramC_TX_OE_Calibration] TA2
8710 00:24:40.996422 Original DQ_B0 (3 6) =30, OEN = 27
8711 00:24:41.000012 Original DQ_B1 (3 6) =30, OEN = 27
8712 00:24:41.003059 24, 0x0, End_B0=24 End_B1=24
8713 00:24:41.006391 25, 0x0, End_B0=25 End_B1=25
8714 00:24:41.006479 26, 0x0, End_B0=26 End_B1=26
8715 00:24:41.009225 27, 0x0, End_B0=27 End_B1=27
8716 00:24:41.012556 28, 0x0, End_B0=28 End_B1=28
8717 00:24:41.015961 29, 0x0, End_B0=29 End_B1=29
8718 00:24:41.016048 30, 0x0, End_B0=30 End_B1=30
8719 00:24:41.019302 31, 0x4141, End_B0=30 End_B1=30
8720 00:24:41.022659 Byte0 end_step=30 best_step=27
8721 00:24:41.025761 Byte1 end_step=30 best_step=27
8722 00:24:41.029067 Byte0 TX OE(2T, 0.5T) = (3, 3)
8723 00:24:41.032509 Byte1 TX OE(2T, 0.5T) = (3, 3)
8724 00:24:41.032592
8725 00:24:41.032656
8726 00:24:41.038876 [DQSOSCAuto] RK0, (LSB)MR18= 0xf19, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 402 ps
8727 00:24:41.042226 CH1 RK0: MR19=303, MR18=F19
8728 00:24:41.048970 CH1_RK0: MR19=0x303, MR18=0xF19, DQSOSC=397, MR23=63, INC=23, DEC=15
8729 00:24:41.049055
8730 00:24:41.052301 ----->DramcWriteLeveling(PI) begin...
8731 00:24:41.052385 ==
8732 00:24:41.055388 Dram Type= 6, Freq= 0, CH_1, rank 1
8733 00:24:41.058657 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8734 00:24:41.058740 ==
8735 00:24:41.061897 Write leveling (Byte 0): 24 => 24
8736 00:24:41.065378 Write leveling (Byte 1): 26 => 26
8737 00:24:41.068637 DramcWriteLeveling(PI) end<-----
8738 00:24:41.068718
8739 00:24:41.068781 ==
8740 00:24:41.071827 Dram Type= 6, Freq= 0, CH_1, rank 1
8741 00:24:41.075280 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8742 00:24:41.078507 ==
8743 00:24:41.078617 [Gating] SW mode calibration
8744 00:24:41.088409 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8745 00:24:41.091686 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8746 00:24:41.094683 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8747 00:24:41.101206 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8748 00:24:41.104908 1 4 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8749 00:24:41.107875 1 4 12 | B1->B0 | 2424 3434 | 1 1 | (0 0) (1 1)
8750 00:24:41.114689 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8751 00:24:41.117602 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8752 00:24:41.124200 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8753 00:24:41.127425 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8754 00:24:41.130841 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8755 00:24:41.137587 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8756 00:24:41.140742 1 5 8 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8757 00:24:41.143962 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8758 00:24:41.150742 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8759 00:24:41.153969 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8760 00:24:41.157462 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8761 00:24:41.164145 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8762 00:24:41.167288 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8763 00:24:41.170503 1 6 4 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
8764 00:24:41.177205 1 6 8 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8765 00:24:41.180696 1 6 12 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
8766 00:24:41.183739 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8767 00:24:41.190481 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8768 00:24:41.193968 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8769 00:24:41.196847 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8770 00:24:41.203414 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8771 00:24:41.206985 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8772 00:24:41.210016 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8773 00:24:41.216625 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8774 00:24:41.220008 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8775 00:24:41.223380 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8776 00:24:41.229733 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8777 00:24:41.232926 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8778 00:24:41.236949 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8779 00:24:41.243221 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8780 00:24:41.246023 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8781 00:24:41.249471 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8782 00:24:41.256358 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8783 00:24:41.259104 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8784 00:24:41.262792 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8785 00:24:41.269079 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8786 00:24:41.272782 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8787 00:24:41.275521 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8788 00:24:41.282296 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8789 00:24:41.285337 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8790 00:24:41.288950 Total UI for P1: 0, mck2ui 16
8791 00:24:41.292418 best dqsien dly found for B0: ( 1, 9, 6)
8792 00:24:41.295520 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8793 00:24:41.298763 Total UI for P1: 0, mck2ui 16
8794 00:24:41.301893 best dqsien dly found for B1: ( 1, 9, 12)
8795 00:24:41.305428 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8796 00:24:41.309056 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8797 00:24:41.309157
8798 00:24:41.315198 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8799 00:24:41.318149 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8800 00:24:41.318258 [Gating] SW calibration Done
8801 00:24:41.321567 ==
8802 00:24:41.324992 Dram Type= 6, Freq= 0, CH_1, rank 1
8803 00:24:41.328597 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8804 00:24:41.328705 ==
8805 00:24:41.328798 RX Vref Scan: 0
8806 00:24:41.328886
8807 00:24:41.331429 RX Vref 0 -> 0, step: 1
8808 00:24:41.331534
8809 00:24:41.335158 RX Delay 0 -> 252, step: 8
8810 00:24:41.338770 iDelay=200, Bit 0, Center 139 (80 ~ 199) 120
8811 00:24:41.341578 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8812 00:24:41.345078 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8813 00:24:41.351374 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8814 00:24:41.354784 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8815 00:24:41.358075 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8816 00:24:41.361438 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8817 00:24:41.367844 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8818 00:24:41.371013 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8819 00:24:41.374408 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8820 00:24:41.377901 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8821 00:24:41.381117 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8822 00:24:41.387535 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8823 00:24:41.390834 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8824 00:24:41.394033 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8825 00:24:41.397361 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8826 00:24:41.397464 ==
8827 00:24:41.400824 Dram Type= 6, Freq= 0, CH_1, rank 1
8828 00:24:41.407188 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8829 00:24:41.407298 ==
8830 00:24:41.407390 DQS Delay:
8831 00:24:41.410487 DQS0 = 0, DQS1 = 0
8832 00:24:41.410588 DQM Delay:
8833 00:24:41.414356 DQM0 = 132, DQM1 = 130
8834 00:24:41.414457 DQ Delay:
8835 00:24:41.417085 DQ0 =139, DQ1 =131, DQ2 =119, DQ3 =127
8836 00:24:41.420184 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131
8837 00:24:41.423957 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =123
8838 00:24:41.427656 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8839 00:24:41.427763
8840 00:24:41.427853
8841 00:24:41.427937 ==
8842 00:24:41.430575 Dram Type= 6, Freq= 0, CH_1, rank 1
8843 00:24:41.436897 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8844 00:24:41.437003 ==
8845 00:24:41.437091
8846 00:24:41.437173
8847 00:24:41.437254 TX Vref Scan disable
8848 00:24:41.440377 == TX Byte 0 ==
8849 00:24:41.443370 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8850 00:24:41.450013 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8851 00:24:41.450121 == TX Byte 1 ==
8852 00:24:41.454091 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8853 00:24:41.459870 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8854 00:24:41.459978 ==
8855 00:24:41.463457 Dram Type= 6, Freq= 0, CH_1, rank 1
8856 00:24:41.466591 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8857 00:24:41.466694 ==
8858 00:24:41.480048
8859 00:24:41.483588 TX Vref early break, caculate TX vref
8860 00:24:41.486819 TX Vref=16, minBit 9, minWin=22, winSum=381
8861 00:24:41.490457 TX Vref=18, minBit 9, minWin=22, winSum=387
8862 00:24:41.493274 TX Vref=20, minBit 9, minWin=22, winSum=391
8863 00:24:41.496736 TX Vref=22, minBit 9, minWin=23, winSum=396
8864 00:24:41.500127 TX Vref=24, minBit 9, minWin=24, winSum=410
8865 00:24:41.506380 TX Vref=26, minBit 9, minWin=24, winSum=415
8866 00:24:41.510052 TX Vref=28, minBit 8, minWin=25, winSum=421
8867 00:24:41.513068 TX Vref=30, minBit 9, minWin=24, winSum=418
8868 00:24:41.516431 TX Vref=32, minBit 8, minWin=24, winSum=409
8869 00:24:41.519615 TX Vref=34, minBit 0, minWin=24, winSum=404
8870 00:24:41.525907 TX Vref=36, minBit 8, minWin=23, winSum=393
8871 00:24:41.529629 [TxChooseVref] Worse bit 8, Min win 25, Win sum 421, Final Vref 28
8872 00:24:41.529716
8873 00:24:41.532806 Final TX Range 0 Vref 28
8874 00:24:41.532888
8875 00:24:41.532953 ==
8876 00:24:41.536371 Dram Type= 6, Freq= 0, CH_1, rank 1
8877 00:24:41.539211 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8878 00:24:41.542456 ==
8879 00:24:41.542539
8880 00:24:41.542604
8881 00:24:41.542663 TX Vref Scan disable
8882 00:24:41.549342 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8883 00:24:41.549428 == TX Byte 0 ==
8884 00:24:41.552952 u2DelayCellOfst[0]=14 cells (4 PI)
8885 00:24:41.556118 u2DelayCellOfst[1]=10 cells (3 PI)
8886 00:24:41.559065 u2DelayCellOfst[2]=0 cells (0 PI)
8887 00:24:41.562554 u2DelayCellOfst[3]=7 cells (2 PI)
8888 00:24:41.565847 u2DelayCellOfst[4]=7 cells (2 PI)
8889 00:24:41.569212 u2DelayCellOfst[5]=14 cells (4 PI)
8890 00:24:41.572428 u2DelayCellOfst[6]=14 cells (4 PI)
8891 00:24:41.576173 u2DelayCellOfst[7]=3 cells (1 PI)
8892 00:24:41.579612 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8893 00:24:41.582437 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8894 00:24:41.585707 == TX Byte 1 ==
8895 00:24:41.588985 u2DelayCellOfst[8]=0 cells (0 PI)
8896 00:24:41.592310 u2DelayCellOfst[9]=3 cells (1 PI)
8897 00:24:41.595649 u2DelayCellOfst[10]=10 cells (3 PI)
8898 00:24:41.599075 u2DelayCellOfst[11]=3 cells (1 PI)
8899 00:24:41.602198 u2DelayCellOfst[12]=14 cells (4 PI)
8900 00:24:41.602282 u2DelayCellOfst[13]=14 cells (4 PI)
8901 00:24:41.605535 u2DelayCellOfst[14]=17 cells (5 PI)
8902 00:24:41.609204 u2DelayCellOfst[15]=14 cells (4 PI)
8903 00:24:41.615725 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8904 00:24:41.619062 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8905 00:24:41.619149 DramC Write-DBI on
8906 00:24:41.622112 ==
8907 00:24:41.625639 Dram Type= 6, Freq= 0, CH_1, rank 1
8908 00:24:41.628405 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8909 00:24:41.628490 ==
8910 00:24:41.628555
8911 00:24:41.628620
8912 00:24:41.632323 TX Vref Scan disable
8913 00:24:41.632406 == TX Byte 0 ==
8914 00:24:41.638551 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8915 00:24:41.638638 == TX Byte 1 ==
8916 00:24:41.641976 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8917 00:24:41.645082 DramC Write-DBI off
8918 00:24:41.645165
8919 00:24:41.645229 [DATLAT]
8920 00:24:41.648826 Freq=1600, CH1 RK1
8921 00:24:41.648909
8922 00:24:41.648974 DATLAT Default: 0xf
8923 00:24:41.651494 0, 0xFFFF, sum = 0
8924 00:24:41.651579 1, 0xFFFF, sum = 0
8925 00:24:41.655113 2, 0xFFFF, sum = 0
8926 00:24:41.655199 3, 0xFFFF, sum = 0
8927 00:24:41.658622 4, 0xFFFF, sum = 0
8928 00:24:41.661456 5, 0xFFFF, sum = 0
8929 00:24:41.661540 6, 0xFFFF, sum = 0
8930 00:24:41.664854 7, 0xFFFF, sum = 0
8931 00:24:41.664938 8, 0xFFFF, sum = 0
8932 00:24:41.668478 9, 0xFFFF, sum = 0
8933 00:24:41.668562 10, 0xFFFF, sum = 0
8934 00:24:41.671458 11, 0xFFFF, sum = 0
8935 00:24:41.671541 12, 0xFFFF, sum = 0
8936 00:24:41.674551 13, 0xFFFF, sum = 0
8937 00:24:41.674634 14, 0x0, sum = 1
8938 00:24:41.678117 15, 0x0, sum = 2
8939 00:24:41.678201 16, 0x0, sum = 3
8940 00:24:41.681375 17, 0x0, sum = 4
8941 00:24:41.681459 best_step = 15
8942 00:24:41.681524
8943 00:24:41.681583 ==
8944 00:24:41.684708 Dram Type= 6, Freq= 0, CH_1, rank 1
8945 00:24:41.688143 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8946 00:24:41.691478 ==
8947 00:24:41.691560 RX Vref Scan: 0
8948 00:24:41.691625
8949 00:24:41.694761 RX Vref 0 -> 0, step: 1
8950 00:24:41.694843
8951 00:24:41.698031 RX Delay 11 -> 252, step: 4
8952 00:24:41.700987 iDelay=195, Bit 0, Center 136 (83 ~ 190) 108
8953 00:24:41.704531 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
8954 00:24:41.707956 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
8955 00:24:41.714457 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8956 00:24:41.717564 iDelay=195, Bit 4, Center 128 (75 ~ 182) 108
8957 00:24:41.721185 iDelay=195, Bit 5, Center 142 (91 ~ 194) 104
8958 00:24:41.724072 iDelay=195, Bit 6, Center 138 (87 ~ 190) 104
8959 00:24:41.727513 iDelay=195, Bit 7, Center 128 (75 ~ 182) 108
8960 00:24:41.734018 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8961 00:24:41.737416 iDelay=195, Bit 9, Center 116 (63 ~ 170) 108
8962 00:24:41.740493 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8963 00:24:41.744058 iDelay=195, Bit 11, Center 122 (67 ~ 178) 112
8964 00:24:41.750937 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
8965 00:24:41.754047 iDelay=195, Bit 13, Center 134 (83 ~ 186) 104
8966 00:24:41.757449 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
8967 00:24:41.760316 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
8968 00:24:41.760400 ==
8969 00:24:41.763606 Dram Type= 6, Freq= 0, CH_1, rank 1
8970 00:24:41.770782 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8971 00:24:41.770872 ==
8972 00:24:41.770938 DQS Delay:
8973 00:24:41.770998 DQS0 = 0, DQS1 = 0
8974 00:24:41.773534 DQM Delay:
8975 00:24:41.773616 DQM0 = 131, DQM1 = 127
8976 00:24:41.777058 DQ Delay:
8977 00:24:41.780602 DQ0 =136, DQ1 =130, DQ2 =118, DQ3 =128
8978 00:24:41.783732 DQ4 =128, DQ5 =142, DQ6 =138, DQ7 =128
8979 00:24:41.786946 DQ8 =114, DQ9 =116, DQ10 =128, DQ11 =122
8980 00:24:41.790030 DQ12 =136, DQ13 =134, DQ14 =132, DQ15 =136
8981 00:24:41.790115
8982 00:24:41.790179
8983 00:24:41.790239
8984 00:24:41.793550 [DramC_TX_OE_Calibration] TA2
8985 00:24:41.796953 Original DQ_B0 (3 6) =30, OEN = 27
8986 00:24:41.800342 Original DQ_B1 (3 6) =30, OEN = 27
8987 00:24:41.803330 24, 0x0, End_B0=24 End_B1=24
8988 00:24:41.803416 25, 0x0, End_B0=25 End_B1=25
8989 00:24:41.806861 26, 0x0, End_B0=26 End_B1=26
8990 00:24:41.809804 27, 0x0, End_B0=27 End_B1=27
8991 00:24:41.813219 28, 0x0, End_B0=28 End_B1=28
8992 00:24:41.816657 29, 0x0, End_B0=29 End_B1=29
8993 00:24:41.816742 30, 0x0, End_B0=30 End_B1=30
8994 00:24:41.819967 31, 0x4141, End_B0=30 End_B1=30
8995 00:24:41.823475 Byte0 end_step=30 best_step=27
8996 00:24:41.826555 Byte1 end_step=30 best_step=27
8997 00:24:41.829903 Byte0 TX OE(2T, 0.5T) = (3, 3)
8998 00:24:41.833380 Byte1 TX OE(2T, 0.5T) = (3, 3)
8999 00:24:41.833462
9000 00:24:41.833526
9001 00:24:41.839831 [DQSOSCAuto] RK1, (LSB)MR18= 0x101d, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 401 ps
9002 00:24:41.843121 CH1 RK1: MR19=303, MR18=101D
9003 00:24:41.849866 CH1_RK1: MR19=0x303, MR18=0x101D, DQSOSC=395, MR23=63, INC=23, DEC=15
9004 00:24:41.852861 [RxdqsGatingPostProcess] freq 1600
9005 00:24:41.856260 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9006 00:24:41.859666 best DQS0 dly(2T, 0.5T) = (1, 1)
9007 00:24:41.862772 best DQS1 dly(2T, 0.5T) = (1, 1)
9008 00:24:41.866338 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9009 00:24:41.869182 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9010 00:24:41.872455 best DQS0 dly(2T, 0.5T) = (1, 1)
9011 00:24:41.875793 best DQS1 dly(2T, 0.5T) = (1, 1)
9012 00:24:41.879363 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9013 00:24:41.882442 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9014 00:24:41.886633 Pre-setting of DQS Precalculation
9015 00:24:41.889378 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9016 00:24:41.895897 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9017 00:24:41.905544 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9018 00:24:41.905640
9019 00:24:41.905705
9020 00:24:41.908747 [Calibration Summary] 3200 Mbps
9021 00:24:41.908830 CH 0, Rank 0
9022 00:24:41.912078 SW Impedance : PASS
9023 00:24:41.912162 DUTY Scan : NO K
9024 00:24:41.915426 ZQ Calibration : PASS
9025 00:24:41.919004 Jitter Meter : NO K
9026 00:24:41.919089 CBT Training : PASS
9027 00:24:41.921880 Write leveling : PASS
9028 00:24:41.925849 RX DQS gating : PASS
9029 00:24:41.925937 RX DQ/DQS(RDDQC) : PASS
9030 00:24:41.928648 TX DQ/DQS : PASS
9031 00:24:41.931922 RX DATLAT : PASS
9032 00:24:41.932005 RX DQ/DQS(Engine): PASS
9033 00:24:41.935058 TX OE : PASS
9034 00:24:41.935141 All Pass.
9035 00:24:41.935205
9036 00:24:41.938557 CH 0, Rank 1
9037 00:24:41.938640 SW Impedance : PASS
9038 00:24:41.941540 DUTY Scan : NO K
9039 00:24:41.944939 ZQ Calibration : PASS
9040 00:24:41.945024 Jitter Meter : NO K
9041 00:24:41.948202 CBT Training : PASS
9042 00:24:41.948284 Write leveling : PASS
9043 00:24:41.951701 RX DQS gating : PASS
9044 00:24:41.954934 RX DQ/DQS(RDDQC) : PASS
9045 00:24:41.955019 TX DQ/DQS : PASS
9046 00:24:41.958505 RX DATLAT : PASS
9047 00:24:41.961531 RX DQ/DQS(Engine): PASS
9048 00:24:41.961614 TX OE : PASS
9049 00:24:41.964862 All Pass.
9050 00:24:41.964946
9051 00:24:41.965033 CH 1, Rank 0
9052 00:24:41.968152 SW Impedance : PASS
9053 00:24:41.968236 DUTY Scan : NO K
9054 00:24:41.971469 ZQ Calibration : PASS
9055 00:24:41.974692 Jitter Meter : NO K
9056 00:24:41.974775 CBT Training : PASS
9057 00:24:41.978189 Write leveling : PASS
9058 00:24:41.981455 RX DQS gating : PASS
9059 00:24:41.981538 RX DQ/DQS(RDDQC) : PASS
9060 00:24:41.985267 TX DQ/DQS : PASS
9061 00:24:41.988239 RX DATLAT : PASS
9062 00:24:41.988322 RX DQ/DQS(Engine): PASS
9063 00:24:41.991068 TX OE : PASS
9064 00:24:41.991151 All Pass.
9065 00:24:41.991214
9066 00:24:41.994468 CH 1, Rank 1
9067 00:24:41.994549 SW Impedance : PASS
9068 00:24:41.997414 DUTY Scan : NO K
9069 00:24:42.000916 ZQ Calibration : PASS
9070 00:24:42.000999 Jitter Meter : NO K
9071 00:24:42.003971 CBT Training : PASS
9072 00:24:42.007808 Write leveling : PASS
9073 00:24:42.007891 RX DQS gating : PASS
9074 00:24:42.010976 RX DQ/DQS(RDDQC) : PASS
9075 00:24:42.014117 TX DQ/DQS : PASS
9076 00:24:42.014199 RX DATLAT : PASS
9077 00:24:42.017253 RX DQ/DQS(Engine): PASS
9078 00:24:42.020809 TX OE : PASS
9079 00:24:42.020895 All Pass.
9080 00:24:42.020959
9081 00:24:42.021018 DramC Write-DBI on
9082 00:24:42.024247 PER_BANK_REFRESH: Hybrid Mode
9083 00:24:42.027433 TX_TRACKING: ON
9084 00:24:42.034194 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9085 00:24:42.043811 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9086 00:24:42.050686 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9087 00:24:42.054099 [FAST_K] Save calibration result to emmc
9088 00:24:42.057099 sync common calibartion params.
9089 00:24:42.060688 sync cbt_mode0:1, 1:1
9090 00:24:42.060772 dram_init: ddr_geometry: 2
9091 00:24:42.063822 dram_init: ddr_geometry: 2
9092 00:24:42.067014 dram_init: ddr_geometry: 2
9093 00:24:42.070555 0:dram_rank_size:100000000
9094 00:24:42.070639 1:dram_rank_size:100000000
9095 00:24:42.076743 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9096 00:24:42.079962 DFS_SHUFFLE_HW_MODE: ON
9097 00:24:42.083446 dramc_set_vcore_voltage set vcore to 725000
9098 00:24:42.083555 Read voltage for 1600, 0
9099 00:24:42.086690 Vio18 = 0
9100 00:24:42.086796 Vcore = 725000
9101 00:24:42.086889 Vdram = 0
9102 00:24:42.090321 Vddq = 0
9103 00:24:42.090428 Vmddr = 0
9104 00:24:42.093211 switch to 3200 Mbps bootup
9105 00:24:42.093324 [DramcRunTimeConfig]
9106 00:24:42.093418 PHYPLL
9107 00:24:42.096571 DPM_CONTROL_AFTERK: ON
9108 00:24:42.100076 PER_BANK_REFRESH: ON
9109 00:24:42.103078 REFRESH_OVERHEAD_REDUCTION: ON
9110 00:24:42.103187 CMD_PICG_NEW_MODE: OFF
9111 00:24:42.106663 XRTWTW_NEW_MODE: ON
9112 00:24:42.106771 XRTRTR_NEW_MODE: ON
9113 00:24:42.109901 TX_TRACKING: ON
9114 00:24:42.110008 RDSEL_TRACKING: OFF
9115 00:24:42.113212 DQS Precalculation for DVFS: ON
9116 00:24:42.116354 RX_TRACKING: OFF
9117 00:24:42.116461 HW_GATING DBG: ON
9118 00:24:42.119597 ZQCS_ENABLE_LP4: ON
9119 00:24:42.119703 RX_PICG_NEW_MODE: ON
9120 00:24:42.122993 TX_PICG_NEW_MODE: ON
9121 00:24:42.123108 ENABLE_RX_DCM_DPHY: ON
9122 00:24:42.126306 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9123 00:24:42.129696 DUMMY_READ_FOR_TRACKING: OFF
9124 00:24:42.132790 !!! SPM_CONTROL_AFTERK: OFF
9125 00:24:42.136008 !!! SPM could not control APHY
9126 00:24:42.136115 IMPEDANCE_TRACKING: ON
9127 00:24:42.139413 TEMP_SENSOR: ON
9128 00:24:42.139519 HW_SAVE_FOR_SR: OFF
9129 00:24:42.142892 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9130 00:24:42.145871 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9131 00:24:42.149146 Read ODT Tracking: ON
9132 00:24:42.152678 Refresh Rate DeBounce: ON
9133 00:24:42.152785 DFS_NO_QUEUE_FLUSH: ON
9134 00:24:42.155849 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9135 00:24:42.159021 ENABLE_DFS_RUNTIME_MRW: OFF
9136 00:24:42.162376 DDR_RESERVE_NEW_MODE: ON
9137 00:24:42.162481 MR_CBT_SWITCH_FREQ: ON
9138 00:24:42.166081 =========================
9139 00:24:42.185013 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9140 00:24:42.187878 dram_init: ddr_geometry: 2
9141 00:24:42.206078 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9142 00:24:42.209454 dram_init: dram init end (result: 0)
9143 00:24:42.216281 DRAM-K: Full calibration passed in 24394 msecs
9144 00:24:42.219699 MRC: failed to locate region type 0.
9145 00:24:42.219814 DRAM rank0 size:0x100000000,
9146 00:24:42.222574 DRAM rank1 size=0x100000000
9147 00:24:42.232392 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9148 00:24:42.239065 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9149 00:24:42.248908 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9150 00:24:42.255791 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9151 00:24:42.255930 DRAM rank0 size:0x100000000,
9152 00:24:42.258815 DRAM rank1 size=0x100000000
9153 00:24:42.258928 CBMEM:
9154 00:24:42.261861 IMD: root @ 0xfffff000 254 entries.
9155 00:24:42.265430 IMD: root @ 0xffffec00 62 entries.
9156 00:24:42.272337 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9157 00:24:42.275833 WARNING: RO_VPD is uninitialized or empty.
9158 00:24:42.278591 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9159 00:24:42.286461 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9160 00:24:42.299374 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9161 00:24:42.310114 BS: romstage times (exec / console): total (unknown) / 23926 ms
9162 00:24:42.310261
9163 00:24:42.310358
9164 00:24:42.320311 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9165 00:24:42.323956 ARM64: Exception handlers installed.
9166 00:24:42.326570 ARM64: Testing exception
9167 00:24:42.329857 ARM64: Done test exception
9168 00:24:42.329971 Enumerating buses...
9169 00:24:42.333250 Show all devs... Before device enumeration.
9170 00:24:42.336914 Root Device: enabled 1
9171 00:24:42.340033 CPU_CLUSTER: 0: enabled 1
9172 00:24:42.340143 CPU: 00: enabled 1
9173 00:24:42.342956 Compare with tree...
9174 00:24:42.343064 Root Device: enabled 1
9175 00:24:42.346370 CPU_CLUSTER: 0: enabled 1
9176 00:24:42.350111 CPU: 00: enabled 1
9177 00:24:42.350220 Root Device scanning...
9178 00:24:42.353000 scan_static_bus for Root Device
9179 00:24:42.356706 CPU_CLUSTER: 0 enabled
9180 00:24:42.359444 scan_static_bus for Root Device done
9181 00:24:42.363158 scan_bus: bus Root Device finished in 8 msecs
9182 00:24:42.363282 done
9183 00:24:42.369404 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9184 00:24:42.372614 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9185 00:24:42.380039 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9186 00:24:42.385685 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9187 00:24:42.385793 Allocating resources...
9188 00:24:42.389129 Reading resources...
9189 00:24:42.392445 Root Device read_resources bus 0 link: 0
9190 00:24:42.395699 DRAM rank0 size:0x100000000,
9191 00:24:42.395821 DRAM rank1 size=0x100000000
9192 00:24:42.402403 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9193 00:24:42.405703 CPU: 00 missing read_resources
9194 00:24:42.408811 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9195 00:24:42.412978 Root Device read_resources bus 0 link: 0 done
9196 00:24:42.415449 Done reading resources.
9197 00:24:42.418994 Show resources in subtree (Root Device)...After reading.
9198 00:24:42.422210 Root Device child on link 0 CPU_CLUSTER: 0
9199 00:24:42.425484 CPU_CLUSTER: 0 child on link 0 CPU: 00
9200 00:24:42.435356 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9201 00:24:42.435475 CPU: 00
9202 00:24:42.442029 Root Device assign_resources, bus 0 link: 0
9203 00:24:42.445300 CPU_CLUSTER: 0 missing set_resources
9204 00:24:42.448872 Root Device assign_resources, bus 0 link: 0 done
9205 00:24:42.451908 Done setting resources.
9206 00:24:42.455380 Show resources in subtree (Root Device)...After assigning values.
9207 00:24:42.461721 Root Device child on link 0 CPU_CLUSTER: 0
9208 00:24:42.464815 CPU_CLUSTER: 0 child on link 0 CPU: 00
9209 00:24:42.471795 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9210 00:24:42.475248 CPU: 00
9211 00:24:42.475343 Done allocating resources.
9212 00:24:42.481531 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9213 00:24:42.484844 Enabling resources...
9214 00:24:42.484936 done.
9215 00:24:42.487777 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9216 00:24:42.491109 Initializing devices...
9217 00:24:42.491198 Root Device init
9218 00:24:42.494500 init hardware done!
9219 00:24:42.497824 0x00000018: ctrlr->caps
9220 00:24:42.497931 52.000 MHz: ctrlr->f_max
9221 00:24:42.501154 0.400 MHz: ctrlr->f_min
9222 00:24:42.504551 0x40ff8080: ctrlr->voltages
9223 00:24:42.504640 sclk: 390625
9224 00:24:42.504706 Bus Width = 1
9225 00:24:42.507523 sclk: 390625
9226 00:24:42.507607 Bus Width = 1
9227 00:24:42.510826 Early init status = 3
9228 00:24:42.514630 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9229 00:24:42.518369 in-header: 03 fc 00 00 01 00 00 00
9230 00:24:42.521215 in-data: 00
9231 00:24:42.524813 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9232 00:24:42.529921 in-header: 03 fd 00 00 00 00 00 00
9233 00:24:42.533093 in-data:
9234 00:24:42.535904 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9235 00:24:42.539371 in-header: 03 fc 00 00 01 00 00 00
9236 00:24:42.543054 in-data: 00
9237 00:24:42.545922 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9238 00:24:42.550710 in-header: 03 fd 00 00 00 00 00 00
9239 00:24:42.554477 in-data:
9240 00:24:42.557496 [SSUSB] Setting up USB HOST controller...
9241 00:24:42.560731 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9242 00:24:42.563772 [SSUSB] phy power-on done.
9243 00:24:42.567746 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9244 00:24:42.574184 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9245 00:24:42.576789 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9246 00:24:42.583560 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9247 00:24:42.589915 read SPI 0x50eb0 0x2ad3: 1173 us, 9346 KB/s, 74.768 Mbps
9248 00:24:42.596649 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9249 00:24:42.603754 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9250 00:24:42.609808 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9251 00:24:42.613024 SPM: binary array size = 0x9dc
9252 00:24:42.620001 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9253 00:24:42.623313 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9254 00:24:42.629552 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9255 00:24:42.636679 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9256 00:24:42.639683 configure_display: Starting display init
9257 00:24:42.673905 anx7625_power_on_init: Init interface.
9258 00:24:42.677132 anx7625_disable_pd_protocol: Disabled PD feature.
9259 00:24:42.680515 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9260 00:24:42.708464 anx7625_start_dp_work: Secure OCM version=00
9261 00:24:42.711955 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9262 00:24:42.726887 sp_tx_get_edid_block: EDID Block = 1
9263 00:24:42.829125 Extracted contents:
9264 00:24:42.832506 header: 00 ff ff ff ff ff ff 00
9265 00:24:42.835972 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9266 00:24:42.839441 version: 01 04
9267 00:24:42.842331 basic params: 95 1f 11 78 0a
9268 00:24:42.845767 chroma info: 76 90 94 55 54 90 27 21 50 54
9269 00:24:42.849160 established: 00 00 00
9270 00:24:42.855474 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9271 00:24:42.858770 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9272 00:24:42.865237 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9273 00:24:42.872181 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9274 00:24:42.878337 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9275 00:24:42.881654 extensions: 00
9276 00:24:42.881756 checksum: fb
9277 00:24:42.881846
9278 00:24:42.888476 Manufacturer: IVO Model 57d Serial Number 0
9279 00:24:42.888580 Made week 0 of 2020
9280 00:24:42.892187 EDID version: 1.4
9281 00:24:42.892275 Digital display
9282 00:24:42.894917 6 bits per primary color channel
9283 00:24:42.898702 DisplayPort interface
9284 00:24:42.898783 Maximum image size: 31 cm x 17 cm
9285 00:24:42.901525 Gamma: 220%
9286 00:24:42.901606 Check DPMS levels
9287 00:24:42.908158 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9288 00:24:42.911733 First detailed timing is preferred timing
9289 00:24:42.914785 Established timings supported:
9290 00:24:42.914865 Standard timings supported:
9291 00:24:42.918400 Detailed timings
9292 00:24:42.921189 Hex of detail: 383680a07038204018303c0035ae10000019
9293 00:24:42.927859 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9294 00:24:42.931351 0780 0798 07c8 0820 hborder 0
9295 00:24:42.934475 0438 043b 0447 0458 vborder 0
9296 00:24:42.937896 -hsync -vsync
9297 00:24:42.937977 Did detailed timing
9298 00:24:42.944428 Hex of detail: 000000000000000000000000000000000000
9299 00:24:42.947656 Manufacturer-specified data, tag 0
9300 00:24:42.950991 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9301 00:24:42.954384 ASCII string: InfoVision
9302 00:24:42.957310 Hex of detail: 000000fe00523134304e574635205248200a
9303 00:24:42.961395 ASCII string: R140NWF5 RH
9304 00:24:42.961476 Checksum
9305 00:24:42.964492 Checksum: 0xfb (valid)
9306 00:24:42.967430 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9307 00:24:42.970770 DSI data_rate: 832800000 bps
9308 00:24:42.977046 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9309 00:24:42.980575 anx7625_parse_edid: pixelclock(138800).
9310 00:24:42.983711 hactive(1920), hsync(48), hfp(24), hbp(88)
9311 00:24:42.987522 vactive(1080), vsync(12), vfp(3), vbp(17)
9312 00:24:42.990198 anx7625_dsi_config: config dsi.
9313 00:24:42.996955 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9314 00:24:43.011120 anx7625_dsi_config: success to config DSI
9315 00:24:43.014313 anx7625_dp_start: MIPI phy setup OK.
9316 00:24:43.017790 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9317 00:24:43.021108 mtk_ddp_mode_set invalid vrefresh 60
9318 00:24:43.024377 main_disp_path_setup
9319 00:24:43.024461 ovl_layer_smi_id_en
9320 00:24:43.027352 ovl_layer_smi_id_en
9321 00:24:43.027433 ccorr_config
9322 00:24:43.027497 aal_config
9323 00:24:43.031120 gamma_config
9324 00:24:43.031200 postmask_config
9325 00:24:43.034264 dither_config
9326 00:24:43.037507 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9327 00:24:43.043902 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9328 00:24:43.047517 Root Device init finished in 551 msecs
9329 00:24:43.051055 CPU_CLUSTER: 0 init
9330 00:24:43.057244 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9331 00:24:43.063808 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9332 00:24:43.063894 APU_MBOX 0x190000b0 = 0x10001
9333 00:24:43.067070 APU_MBOX 0x190001b0 = 0x10001
9334 00:24:43.070677 APU_MBOX 0x190005b0 = 0x10001
9335 00:24:43.073958 APU_MBOX 0x190006b0 = 0x10001
9336 00:24:43.080715 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9337 00:24:43.090321 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9338 00:24:43.102809 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9339 00:24:43.108961 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9340 00:24:43.120789 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9341 00:24:43.130137 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9342 00:24:43.133013 CPU_CLUSTER: 0 init finished in 81 msecs
9343 00:24:43.136326 Devices initialized
9344 00:24:43.139938 Show all devs... After init.
9345 00:24:43.140020 Root Device: enabled 1
9346 00:24:43.143012 CPU_CLUSTER: 0: enabled 1
9347 00:24:43.146460 CPU: 00: enabled 1
9348 00:24:43.149691 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9349 00:24:43.152919 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9350 00:24:43.156179 ELOG: NV offset 0x57f000 size 0x1000
9351 00:24:43.162772 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9352 00:24:43.169426 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9353 00:24:43.173261 ELOG: Event(17) added with size 13 at 2024-06-21 00:24:43 UTC
9354 00:24:43.179147 out: cmd=0x121: 03 db 21 01 00 00 00 00
9355 00:24:43.183032 in-header: 03 3f 00 00 2c 00 00 00
9356 00:24:43.192541 in-data: ff 71 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9357 00:24:43.199489 ELOG: Event(A1) added with size 10 at 2024-06-21 00:24:43 UTC
9358 00:24:43.206021 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9359 00:24:43.212309 ELOG: Event(A0) added with size 9 at 2024-06-21 00:24:43 UTC
9360 00:24:43.215777 elog_add_boot_reason: Logged dev mode boot
9361 00:24:43.222178 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9362 00:24:43.222261 Finalize devices...
9363 00:24:43.225887 Devices finalized
9364 00:24:43.228850 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9365 00:24:43.232074 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9366 00:24:43.235533 in-header: 03 07 00 00 08 00 00 00
9367 00:24:43.238947 in-data: aa e4 47 04 13 02 00 00
9368 00:24:43.242357 Chrome EC: UHEPI supported
9369 00:24:43.248687 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9370 00:24:43.251861 in-header: 03 a9 00 00 08 00 00 00
9371 00:24:43.255973 in-data: 84 60 60 08 00 00 00 00
9372 00:24:43.261946 ELOG: Event(91) added with size 10 at 2024-06-21 00:24:43 UTC
9373 00:24:43.265412 Chrome EC: clear events_b mask to 0x0000000020004000
9374 00:24:43.271742 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9375 00:24:43.275854 in-header: 03 fd 00 00 00 00 00 00
9376 00:24:43.279014 in-data:
9377 00:24:43.282239 BS: BS_WRITE_TABLES entry times (exec / console): 3 / 46 ms
9378 00:24:43.285833 Writing coreboot table at 0xffe64000
9379 00:24:43.292285 0. 000000000010a000-0000000000113fff: RAMSTAGE
9380 00:24:43.295874 1. 0000000040000000-00000000400fffff: RAM
9381 00:24:43.299187 2. 0000000040100000-000000004032afff: RAMSTAGE
9382 00:24:43.302031 3. 000000004032b000-00000000545fffff: RAM
9383 00:24:43.305977 4. 0000000054600000-000000005465ffff: BL31
9384 00:24:43.308871 5. 0000000054660000-00000000ffe63fff: RAM
9385 00:24:43.315589 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9386 00:24:43.318794 7. 0000000100000000-000000023fffffff: RAM
9387 00:24:43.321885 Passing 5 GPIOs to payload:
9388 00:24:43.325418 NAME | PORT | POLARITY | VALUE
9389 00:24:43.331876 EC in RW | 0x000000aa | low | undefined
9390 00:24:43.335089 EC interrupt | 0x00000005 | low | undefined
9391 00:24:43.341511 TPM interrupt | 0x000000ab | high | undefined
9392 00:24:43.344978 SD card detect | 0x00000011 | high | undefined
9393 00:24:43.351251 speaker enable | 0x00000093 | high | undefined
9394 00:24:43.354475 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9395 00:24:43.357788 in-header: 03 f9 00 00 02 00 00 00
9396 00:24:43.357871 in-data: 02 00
9397 00:24:43.361798 ADC[4]: Raw value=902586 ID=7
9398 00:24:43.364559 ADC[3]: Raw value=213546 ID=1
9399 00:24:43.364642 RAM Code: 0x71
9400 00:24:43.367831 ADC[6]: Raw value=74630 ID=0
9401 00:24:43.371537 ADC[5]: Raw value=213546 ID=1
9402 00:24:43.371620 SKU Code: 0x1
9403 00:24:43.377997 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum af3b
9404 00:24:43.381506 coreboot table: 964 bytes.
9405 00:24:43.384560 IMD ROOT 0. 0xfffff000 0x00001000
9406 00:24:43.387828 IMD SMALL 1. 0xffffe000 0x00001000
9407 00:24:43.391304 RO MCACHE 2. 0xffffc000 0x00001104
9408 00:24:43.394405 CONSOLE 3. 0xfff7c000 0x00080000
9409 00:24:43.397597 FMAP 4. 0xfff7b000 0x00000452
9410 00:24:43.400837 TIME STAMP 5. 0xfff7a000 0x00000910
9411 00:24:43.404031 VBOOT WORK 6. 0xfff66000 0x00014000
9412 00:24:43.404139 RAMOOPS 7. 0xffe66000 0x00100000
9413 00:24:43.407912 COREBOOT 8. 0xffe64000 0x00002000
9414 00:24:43.410918 IMD small region:
9415 00:24:43.414100 IMD ROOT 0. 0xffffec00 0x00000400
9416 00:24:43.417581 VPD 1. 0xffffeb80 0x0000006c
9417 00:24:43.420927 MMC STATUS 2. 0xffffeb60 0x00000004
9418 00:24:43.427040 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9419 00:24:43.433567 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9420 00:24:43.473151 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9421 00:24:43.476252 Checking segment from ROM address 0x40100000
9422 00:24:43.482566 Checking segment from ROM address 0x4010001c
9423 00:24:43.485943 Loading segment from ROM address 0x40100000
9424 00:24:43.486055 code (compression=0)
9425 00:24:43.496009 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9426 00:24:43.502518 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9427 00:24:43.502631 it's not compressed!
9428 00:24:43.509126 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9429 00:24:43.515627 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9430 00:24:43.533486 Loading segment from ROM address 0x4010001c
9431 00:24:43.533627 Entry Point 0x80000000
9432 00:24:43.536467 Loaded segments
9433 00:24:43.540083 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9434 00:24:43.546175 Jumping to boot code at 0x80000000(0xffe64000)
9435 00:24:43.552744 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9436 00:24:43.559588 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9437 00:24:43.567556 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9438 00:24:43.570698 Checking segment from ROM address 0x40100000
9439 00:24:43.574034 Checking segment from ROM address 0x4010001c
9440 00:24:43.580666 Loading segment from ROM address 0x40100000
9441 00:24:43.580778 code (compression=1)
9442 00:24:43.587819 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9443 00:24:43.597423 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9444 00:24:43.597544 using LZMA
9445 00:24:43.606259 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9446 00:24:43.612214 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9447 00:24:43.616099 Loading segment from ROM address 0x4010001c
9448 00:24:43.618930 Entry Point 0x54601000
9449 00:24:43.619039 Loaded segments
9450 00:24:43.622816 NOTICE: MT8192 bl31_setup
9451 00:24:43.629539 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9452 00:24:43.632724 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9453 00:24:43.636104 WARNING: region 0:
9454 00:24:43.639573 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9455 00:24:43.639660 WARNING: region 1:
9456 00:24:43.646408 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9457 00:24:43.649045 WARNING: region 2:
9458 00:24:43.653075 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9459 00:24:43.656047 WARNING: region 3:
9460 00:24:43.662492 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9461 00:24:43.662579 WARNING: region 4:
9462 00:24:43.669001 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9463 00:24:43.669112 WARNING: region 5:
9464 00:24:43.672275 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9465 00:24:43.675516 WARNING: region 6:
9466 00:24:43.679127 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9467 00:24:43.681796 WARNING: region 7:
9468 00:24:43.685174 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9469 00:24:43.691928 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9470 00:24:43.695180 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9471 00:24:43.701872 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9472 00:24:43.705104 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9473 00:24:43.708305 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9474 00:24:43.715231 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9475 00:24:43.718433 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9476 00:24:43.722079 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9477 00:24:43.728727 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9478 00:24:43.731549 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9479 00:24:43.738318 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9480 00:24:43.741578 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9481 00:24:43.744993 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9482 00:24:43.751289 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9483 00:24:43.754462 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9484 00:24:43.761280 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9485 00:24:43.764686 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9486 00:24:43.767848 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9487 00:24:43.774395 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9488 00:24:43.777521 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9489 00:24:43.784630 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9490 00:24:43.787866 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9491 00:24:43.790814 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9492 00:24:43.797291 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9493 00:24:43.800770 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9494 00:24:43.807476 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9495 00:24:43.810763 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9496 00:24:43.814301 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9497 00:24:43.820901 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9498 00:24:43.823625 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9499 00:24:43.830208 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9500 00:24:43.833531 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9501 00:24:43.836973 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9502 00:24:43.843649 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9503 00:24:43.846992 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9504 00:24:43.850121 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9505 00:24:43.853690 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9506 00:24:43.859678 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9507 00:24:43.863399 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9508 00:24:43.866993 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9509 00:24:43.869788 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9510 00:24:43.876351 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9511 00:24:43.879907 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9512 00:24:43.883239 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9513 00:24:43.889459 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9514 00:24:43.892730 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9515 00:24:43.896291 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9516 00:24:43.899179 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9517 00:24:43.905819 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9518 00:24:43.909112 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9519 00:24:43.915998 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9520 00:24:43.919051 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9521 00:24:43.925979 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9522 00:24:43.929497 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9523 00:24:43.932622 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9524 00:24:43.939290 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9525 00:24:43.942160 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9526 00:24:43.948675 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9527 00:24:43.951691 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9528 00:24:43.958570 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9529 00:24:43.961503 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9530 00:24:43.968381 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9531 00:24:43.971843 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9532 00:24:43.978007 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9533 00:24:43.981433 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9534 00:24:43.984929 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9535 00:24:43.991777 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9536 00:24:43.994554 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9537 00:24:44.001879 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9538 00:24:44.004638 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9539 00:24:44.011041 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9540 00:24:44.014426 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9541 00:24:44.020854 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9542 00:24:44.024748 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9543 00:24:44.027634 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9544 00:24:44.034489 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9545 00:24:44.037574 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9546 00:24:44.044373 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9547 00:24:44.047708 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9548 00:24:44.053893 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9549 00:24:44.057483 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9550 00:24:44.063777 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9551 00:24:44.067285 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9552 00:24:44.073816 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9553 00:24:44.077497 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9554 00:24:44.080256 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9555 00:24:44.086872 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9556 00:24:44.090043 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9557 00:24:44.097186 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9558 00:24:44.100269 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9559 00:24:44.106629 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9560 00:24:44.110094 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9561 00:24:44.116618 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9562 00:24:44.119503 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9563 00:24:44.126289 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9564 00:24:44.130056 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9565 00:24:44.133150 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9566 00:24:44.136199 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9567 00:24:44.142897 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9568 00:24:44.146014 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9569 00:24:44.149499 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9570 00:24:44.155921 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9571 00:24:44.159155 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9572 00:24:44.166175 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9573 00:24:44.169484 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9574 00:24:44.172391 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9575 00:24:44.179165 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9576 00:24:44.182330 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9577 00:24:44.189021 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9578 00:24:44.192338 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9579 00:24:44.195559 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9580 00:24:44.202397 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9581 00:24:44.205758 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9582 00:24:44.212065 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9583 00:24:44.215334 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9584 00:24:44.218464 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9585 00:24:44.225178 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9586 00:24:44.228466 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9587 00:24:44.231916 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9588 00:24:44.238544 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9589 00:24:44.241947 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9590 00:24:44.244952 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9591 00:24:44.248475 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9592 00:24:44.254506 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9593 00:24:44.257855 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9594 00:24:44.264503 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9595 00:24:44.268322 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9596 00:24:44.271615 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9597 00:24:44.277862 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9598 00:24:44.281375 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9599 00:24:44.284415 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9600 00:24:44.290960 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9601 00:24:44.294166 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9602 00:24:44.301037 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9603 00:24:44.304368 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9604 00:24:44.310927 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9605 00:24:44.314013 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9606 00:24:44.317402 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9607 00:24:44.324122 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9608 00:24:44.327335 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9609 00:24:44.334080 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9610 00:24:44.336997 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9611 00:24:44.340166 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9612 00:24:44.347400 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9613 00:24:44.350278 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9614 00:24:44.356531 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9615 00:24:44.360309 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9616 00:24:44.363225 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9617 00:24:44.370049 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9618 00:24:44.373436 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9619 00:24:44.379712 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9620 00:24:44.383204 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9621 00:24:44.386678 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9622 00:24:44.393474 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9623 00:24:44.396404 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9624 00:24:44.403008 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9625 00:24:44.406059 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9626 00:24:44.409619 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9627 00:24:44.416154 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9628 00:24:44.419583 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9629 00:24:44.426464 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9630 00:24:44.429829 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9631 00:24:44.432510 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9632 00:24:44.439256 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9633 00:24:44.442619 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9634 00:24:44.448918 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9635 00:24:44.452528 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9636 00:24:44.455757 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9637 00:24:44.462469 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9638 00:24:44.466122 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9639 00:24:44.472336 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9640 00:24:44.475191 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9641 00:24:44.478848 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9642 00:24:44.485394 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9643 00:24:44.488805 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9644 00:24:44.495424 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9645 00:24:44.498304 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9646 00:24:44.502280 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9647 00:24:44.507950 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9648 00:24:44.511499 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9649 00:24:44.517941 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9650 00:24:44.521525 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9651 00:24:44.524824 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9652 00:24:44.531550 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9653 00:24:44.534554 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9654 00:24:44.541181 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9655 00:24:44.544857 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9656 00:24:44.548137 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9657 00:24:44.554475 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9658 00:24:44.558017 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9659 00:24:44.564710 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9660 00:24:44.568204 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9661 00:24:44.574290 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9662 00:24:44.577653 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9663 00:24:44.581351 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9664 00:24:44.587478 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9665 00:24:44.590873 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9666 00:24:44.597474 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9667 00:24:44.600388 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9668 00:24:44.607162 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9669 00:24:44.610157 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9670 00:24:44.613478 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9671 00:24:44.620240 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9672 00:24:44.623948 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9673 00:24:44.630282 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9674 00:24:44.633459 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9675 00:24:44.640176 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9676 00:24:44.643676 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9677 00:24:44.646622 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9678 00:24:44.653411 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9679 00:24:44.656284 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9680 00:24:44.663126 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9681 00:24:44.666667 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9682 00:24:44.672989 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9683 00:24:44.676153 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9684 00:24:44.679568 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9685 00:24:44.686258 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9686 00:24:44.689516 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9687 00:24:44.695844 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9688 00:24:44.699378 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9689 00:24:44.705991 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9690 00:24:44.709272 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9691 00:24:44.712467 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9692 00:24:44.719646 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9693 00:24:44.722825 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9694 00:24:44.729217 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9695 00:24:44.732174 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9696 00:24:44.739014 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9697 00:24:44.742615 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9698 00:24:44.745612 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9699 00:24:44.748681 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9700 00:24:44.755136 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9701 00:24:44.758476 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9702 00:24:44.761759 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9703 00:24:44.768456 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9704 00:24:44.771654 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9705 00:24:44.775237 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9706 00:24:44.782318 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9707 00:24:44.784785 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9708 00:24:44.788411 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9709 00:24:44.795236 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9710 00:24:44.798545 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9711 00:24:44.804890 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9712 00:24:44.807961 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9713 00:24:44.811285 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9714 00:24:44.817760 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9715 00:24:44.821486 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9716 00:24:44.824469 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9717 00:24:44.831584 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9718 00:24:44.834387 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9719 00:24:44.841113 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9720 00:24:44.844532 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9721 00:24:44.848107 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9722 00:24:44.854232 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9723 00:24:44.857670 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9724 00:24:44.860520 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9725 00:24:44.867621 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9726 00:24:44.870642 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9727 00:24:44.874257 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9728 00:24:44.880512 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9729 00:24:44.883719 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9730 00:24:44.890524 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9731 00:24:44.893946 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9732 00:24:44.897250 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9733 00:24:44.903878 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9734 00:24:44.906836 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9735 00:24:44.913073 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9736 00:24:44.917039 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9737 00:24:44.920190 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9738 00:24:44.926389 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9739 00:24:44.929576 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9740 00:24:44.933419 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9741 00:24:44.936387 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9742 00:24:44.940055 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9743 00:24:44.946224 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9744 00:24:44.949703 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9745 00:24:44.953078 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9746 00:24:44.956196 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9747 00:24:44.962801 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9748 00:24:44.966480 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9749 00:24:44.969681 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9750 00:24:44.975934 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9751 00:24:44.979449 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9752 00:24:44.982560 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9753 00:24:44.989310 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9754 00:24:44.992430 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9755 00:24:44.999548 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9756 00:24:45.002828 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9757 00:24:45.008986 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9758 00:24:45.012476 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9759 00:24:45.015700 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9760 00:24:45.022168 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9761 00:24:45.025422 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9762 00:24:45.032005 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9763 00:24:45.035027 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9764 00:24:45.041705 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9765 00:24:45.045641 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9766 00:24:45.048586 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9767 00:24:45.055146 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9768 00:24:45.058227 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9769 00:24:45.064888 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9770 00:24:45.068613 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9771 00:24:45.071918 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9772 00:24:45.078305 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9773 00:24:45.081440 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9774 00:24:45.088081 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9775 00:24:45.091057 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9776 00:24:45.098027 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9777 00:24:45.101160 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9778 00:24:45.104714 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9779 00:24:45.110865 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9780 00:24:45.114176 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9781 00:24:45.120580 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9782 00:24:45.124294 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9783 00:24:45.127873 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9784 00:24:45.134173 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9785 00:24:45.137386 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9786 00:24:45.144468 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9787 00:24:45.147198 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9788 00:24:45.154005 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9789 00:24:45.156977 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9790 00:24:45.161219 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9791 00:24:45.166924 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9792 00:24:45.170205 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9793 00:24:45.176750 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9794 00:24:45.180327 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9795 00:24:45.186978 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9796 00:24:45.190056 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9797 00:24:45.193930 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9798 00:24:45.199990 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9799 00:24:45.203460 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9800 00:24:45.209999 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9801 00:24:45.212954 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9802 00:24:45.216403 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9803 00:24:45.222864 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9804 00:24:45.227457 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9805 00:24:45.233103 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9806 00:24:45.240122 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9807 00:24:45.242686 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9808 00:24:45.246135 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9809 00:24:45.249695 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9810 00:24:45.255776 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9811 00:24:45.259085 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9812 00:24:45.265678 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9813 00:24:45.269136 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9814 00:24:45.272303 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9815 00:24:45.278775 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9816 00:24:45.282101 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9817 00:24:45.288757 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9818 00:24:45.291979 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9819 00:24:45.298470 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9820 00:24:45.302412 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9821 00:24:45.308516 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9822 00:24:45.311706 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9823 00:24:45.314876 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9824 00:24:45.321891 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9825 00:24:45.324834 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9826 00:24:45.331474 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9827 00:24:45.334734 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9828 00:24:45.341497 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9829 00:24:45.344737 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9830 00:24:45.348129 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9831 00:24:45.354557 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9832 00:24:45.358112 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9833 00:24:45.364575 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9834 00:24:45.367711 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9835 00:24:45.374447 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9836 00:24:45.377672 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9837 00:24:45.384936 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9838 00:24:45.387300 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9839 00:24:45.390531 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9840 00:24:45.397075 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9841 00:24:45.400679 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9842 00:24:45.407002 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9843 00:24:45.410504 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9844 00:24:45.417393 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9845 00:24:45.420253 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9846 00:24:45.427085 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9847 00:24:45.430569 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9848 00:24:45.433406 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9849 00:24:45.440293 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9850 00:24:45.443464 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9851 00:24:45.449933 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9852 00:24:45.453502 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9853 00:24:45.459789 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9854 00:24:45.463364 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9855 00:24:45.470120 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9856 00:24:45.472849 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9857 00:24:45.479591 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9858 00:24:45.482915 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9859 00:24:45.486039 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9860 00:24:45.493088 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9861 00:24:45.496145 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9862 00:24:45.502475 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9863 00:24:45.505972 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9864 00:24:45.512941 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9865 00:24:45.515776 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9866 00:24:45.522708 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9867 00:24:45.525630 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9868 00:24:45.529003 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9869 00:24:45.535942 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9870 00:24:45.538780 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9871 00:24:45.545631 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9872 00:24:45.549180 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9873 00:24:45.555507 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9874 00:24:45.559083 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9875 00:24:45.565525 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9876 00:24:45.568968 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9877 00:24:45.575517 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9878 00:24:45.578471 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9879 00:24:45.582115 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9880 00:24:45.588411 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9881 00:24:45.592157 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9882 00:24:45.598313 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9883 00:24:45.601492 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9884 00:24:45.608428 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9885 00:24:45.611861 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9886 00:24:45.617997 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9887 00:24:45.621248 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9888 00:24:45.627866 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9889 00:24:45.631288 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9890 00:24:45.638037 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9891 00:24:45.641009 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9892 00:24:45.647869 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9893 00:24:45.651314 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9894 00:24:45.657738 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9895 00:24:45.660658 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9896 00:24:45.667338 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9897 00:24:45.673876 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9898 00:24:45.677471 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9899 00:24:45.684018 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9900 00:24:45.687057 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9901 00:24:45.693840 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9902 00:24:45.696904 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9903 00:24:45.700529 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9904 00:24:45.703855 INFO: [APUAPC] vio 0
9905 00:24:45.710060 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9906 00:24:45.713723 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9907 00:24:45.717124 INFO: [APUAPC] D0_APC_0: 0x400510
9908 00:24:45.720382 INFO: [APUAPC] D0_APC_1: 0x0
9909 00:24:45.723864 INFO: [APUAPC] D0_APC_2: 0x1540
9910 00:24:45.726892 INFO: [APUAPC] D0_APC_3: 0x0
9911 00:24:45.730092 INFO: [APUAPC] D1_APC_0: 0xffffffff
9912 00:24:45.733231 INFO: [APUAPC] D1_APC_1: 0xffffffff
9913 00:24:45.736944 INFO: [APUAPC] D1_APC_2: 0x3fffff
9914 00:24:45.737031 INFO: [APUAPC] D1_APC_3: 0x0
9915 00:24:45.743246 INFO: [APUAPC] D2_APC_0: 0xffffffff
9916 00:24:45.746463 INFO: [APUAPC] D2_APC_1: 0xffffffff
9917 00:24:45.750047 INFO: [APUAPC] D2_APC_2: 0x3fffff
9918 00:24:45.750164 INFO: [APUAPC] D2_APC_3: 0x0
9919 00:24:45.752936 INFO: [APUAPC] D3_APC_0: 0xffffffff
9920 00:24:45.760147 INFO: [APUAPC] D3_APC_1: 0xffffffff
9921 00:24:45.762913 INFO: [APUAPC] D3_APC_2: 0x3fffff
9922 00:24:45.762996 INFO: [APUAPC] D3_APC_3: 0x0
9923 00:24:45.766043 INFO: [APUAPC] D4_APC_0: 0xffffffff
9924 00:24:45.772623 INFO: [APUAPC] D4_APC_1: 0xffffffff
9925 00:24:45.775729 INFO: [APUAPC] D4_APC_2: 0x3fffff
9926 00:24:45.775812 INFO: [APUAPC] D4_APC_3: 0x0
9927 00:24:45.779629 INFO: [APUAPC] D5_APC_0: 0xffffffff
9928 00:24:45.782635 INFO: [APUAPC] D5_APC_1: 0xffffffff
9929 00:24:45.785856 INFO: [APUAPC] D5_APC_2: 0x3fffff
9930 00:24:45.789540 INFO: [APUAPC] D5_APC_3: 0x0
9931 00:24:45.792454 INFO: [APUAPC] D6_APC_0: 0xffffffff
9932 00:24:45.795867 INFO: [APUAPC] D6_APC_1: 0xffffffff
9933 00:24:45.799452 INFO: [APUAPC] D6_APC_2: 0x3fffff
9934 00:24:45.802500 INFO: [APUAPC] D6_APC_3: 0x0
9935 00:24:45.805464 INFO: [APUAPC] D7_APC_0: 0xffffffff
9936 00:24:45.808849 INFO: [APUAPC] D7_APC_1: 0xffffffff
9937 00:24:45.812250 INFO: [APUAPC] D7_APC_2: 0x3fffff
9938 00:24:45.815476 INFO: [APUAPC] D7_APC_3: 0x0
9939 00:24:45.819011 INFO: [APUAPC] D8_APC_0: 0xffffffff
9940 00:24:45.822044 INFO: [APUAPC] D8_APC_1: 0xffffffff
9941 00:24:45.825512 INFO: [APUAPC] D8_APC_2: 0x3fffff
9942 00:24:45.828955 INFO: [APUAPC] D8_APC_3: 0x0
9943 00:24:45.832290 INFO: [APUAPC] D9_APC_0: 0xffffffff
9944 00:24:45.835368 INFO: [APUAPC] D9_APC_1: 0xffffffff
9945 00:24:45.838386 INFO: [APUAPC] D9_APC_2: 0x3fffff
9946 00:24:45.841989 INFO: [APUAPC] D9_APC_3: 0x0
9947 00:24:45.845239 INFO: [APUAPC] D10_APC_0: 0xffffffff
9948 00:24:45.848396 INFO: [APUAPC] D10_APC_1: 0xffffffff
9949 00:24:45.851716 INFO: [APUAPC] D10_APC_2: 0x3fffff
9950 00:24:45.855035 INFO: [APUAPC] D10_APC_3: 0x0
9951 00:24:45.858221 INFO: [APUAPC] D11_APC_0: 0xffffffff
9952 00:24:45.861524 INFO: [APUAPC] D11_APC_1: 0xffffffff
9953 00:24:45.864826 INFO: [APUAPC] D11_APC_2: 0x3fffff
9954 00:24:45.868370 INFO: [APUAPC] D11_APC_3: 0x0
9955 00:24:45.871744 INFO: [APUAPC] D12_APC_0: 0xffffffff
9956 00:24:45.875155 INFO: [APUAPC] D12_APC_1: 0xffffffff
9957 00:24:45.878857 INFO: [APUAPC] D12_APC_2: 0x3fffff
9958 00:24:45.881660 INFO: [APUAPC] D12_APC_3: 0x0
9959 00:24:45.884847 INFO: [APUAPC] D13_APC_0: 0xffffffff
9960 00:24:45.888304 INFO: [APUAPC] D13_APC_1: 0xffffffff
9961 00:24:45.891566 INFO: [APUAPC] D13_APC_2: 0x3fffff
9962 00:24:45.894490 INFO: [APUAPC] D13_APC_3: 0x0
9963 00:24:45.898059 INFO: [APUAPC] D14_APC_0: 0xffffffff
9964 00:24:45.901460 INFO: [APUAPC] D14_APC_1: 0xffffffff
9965 00:24:45.904894 INFO: [APUAPC] D14_APC_2: 0x3fffff
9966 00:24:45.908064 INFO: [APUAPC] D14_APC_3: 0x0
9967 00:24:45.911229 INFO: [APUAPC] D15_APC_0: 0xffffffff
9968 00:24:45.917527 INFO: [APUAPC] D15_APC_1: 0xffffffff
9969 00:24:45.921162 INFO: [APUAPC] D15_APC_2: 0x3fffff
9970 00:24:45.921250 INFO: [APUAPC] D15_APC_3: 0x0
9971 00:24:45.924117 INFO: [APUAPC] APC_CON: 0x4
9972 00:24:45.927909 INFO: [NOCDAPC] D0_APC_0: 0x0
9973 00:24:45.931133 INFO: [NOCDAPC] D0_APC_1: 0x0
9974 00:24:45.934378 INFO: [NOCDAPC] D1_APC_0: 0x0
9975 00:24:45.937665 INFO: [NOCDAPC] D1_APC_1: 0xfff
9976 00:24:45.940836 INFO: [NOCDAPC] D2_APC_0: 0x0
9977 00:24:45.944153 INFO: [NOCDAPC] D2_APC_1: 0xfff
9978 00:24:45.947343 INFO: [NOCDAPC] D3_APC_0: 0x0
9979 00:24:45.950777 INFO: [NOCDAPC] D3_APC_1: 0xfff
9980 00:24:45.950860 INFO: [NOCDAPC] D4_APC_0: 0x0
9981 00:24:45.953832 INFO: [NOCDAPC] D4_APC_1: 0xfff
9982 00:24:45.957734 INFO: [NOCDAPC] D5_APC_0: 0x0
9983 00:24:45.960304 INFO: [NOCDAPC] D5_APC_1: 0xfff
9984 00:24:45.963604 INFO: [NOCDAPC] D6_APC_0: 0x0
9985 00:24:45.966953 INFO: [NOCDAPC] D6_APC_1: 0xfff
9986 00:24:45.970368 INFO: [NOCDAPC] D7_APC_0: 0x0
9987 00:24:45.973960 INFO: [NOCDAPC] D7_APC_1: 0xfff
9988 00:24:45.977004 INFO: [NOCDAPC] D8_APC_0: 0x0
9989 00:24:45.980658 INFO: [NOCDAPC] D8_APC_1: 0xfff
9990 00:24:45.984076 INFO: [NOCDAPC] D9_APC_0: 0x0
9991 00:24:45.987656 INFO: [NOCDAPC] D9_APC_1: 0xfff
9992 00:24:45.987737 INFO: [NOCDAPC] D10_APC_0: 0x0
9993 00:24:45.990461 INFO: [NOCDAPC] D10_APC_1: 0xfff
9994 00:24:45.993462 INFO: [NOCDAPC] D11_APC_0: 0x0
9995 00:24:45.996565 INFO: [NOCDAPC] D11_APC_1: 0xfff
9996 00:24:46.000002 INFO: [NOCDAPC] D12_APC_0: 0x0
9997 00:24:46.003294 INFO: [NOCDAPC] D12_APC_1: 0xfff
9998 00:24:46.006678 INFO: [NOCDAPC] D13_APC_0: 0x0
9999 00:24:46.009766 INFO: [NOCDAPC] D13_APC_1: 0xfff
10000 00:24:46.013413 INFO: [NOCDAPC] D14_APC_0: 0x0
10001 00:24:46.016548 INFO: [NOCDAPC] D14_APC_1: 0xfff
10002 00:24:46.019601 INFO: [NOCDAPC] D15_APC_0: 0x0
10003 00:24:46.023467 INFO: [NOCDAPC] D15_APC_1: 0xfff
10004 00:24:46.026367 INFO: [NOCDAPC] APC_CON: 0x4
10005 00:24:46.030360 INFO: [APUAPC] set_apusys_apc done
10006 00:24:46.033377 INFO: [DEVAPC] devapc_init done
10007 00:24:46.036484 INFO: GICv3 without legacy support detected.
10008 00:24:46.039654 INFO: ARM GICv3 driver initialized in EL3
10009 00:24:46.042868 INFO: Maximum SPI INTID supported: 639
10010 00:24:46.046139 INFO: BL31: Initializing runtime services
10011 00:24:46.052943 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10012 00:24:46.055989 INFO: SPM: enable CPC mode
10013 00:24:46.062641 INFO: mcdi ready for mcusys-off-idle and system suspend
10014 00:24:46.066056 INFO: BL31: Preparing for EL3 exit to normal world
10015 00:24:46.069497 INFO: Entry point address = 0x80000000
10016 00:24:46.072185 INFO: SPSR = 0x8
10017 00:24:46.077464
10018 00:24:46.077614
10019 00:24:46.077720
10020 00:24:46.080802 Starting depthcharge on Spherion...
10021 00:24:46.080947
10022 00:24:46.081041 Wipe memory regions:
10023 00:24:46.081129
10024 00:24:46.081887 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
10025 00:24:46.082063 start: 2.2.4 bootloader-commands (timeout 00:04:27) [common]
10026 00:24:46.082191 Setting prompt string to ['asurada:']
10027 00:24:46.082318 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:27)
10028 00:24:46.084449 [0x00000040000000, 0x00000054600000)
10029 00:24:46.206358
10030 00:24:46.206563 [0x00000054660000, 0x00000080000000)
10031 00:24:46.466483
10032 00:24:46.466649 [0x000000821a7280, 0x000000ffe64000)
10033 00:24:47.210220
10034 00:24:47.210402 [0x00000100000000, 0x00000240000000)
10035 00:24:49.097710
10036 00:24:49.100950 Initializing XHCI USB controller at 0x11200000.
10037 00:24:50.138861
10038 00:24:50.142136 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10039 00:24:50.142230
10040 00:24:50.142293
10041 00:24:50.142576 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10043 00:24:50.242944 asurada: tftpboot 192.168.201.1 14479200/tftp-deploy-krd9ty9v/kernel/image.itb 14479200/tftp-deploy-krd9ty9v/kernel/cmdline
10044 00:24:50.243091 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10045 00:24:50.243194 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:23)
10046 00:24:50.247626 tftpboot 192.168.201.1 14479200/tftp-deploy-krd9ty9v/kernel/image.itp-deploy-krd9ty9v/kernel/cmdline
10047 00:24:50.247730
10048 00:24:50.247837 Waiting for link
10049 00:24:50.405471
10050 00:24:50.405621 R8152: Initializing
10051 00:24:50.405689
10052 00:24:50.408841 Version 6 (ocp_data = 5c30)
10053 00:24:50.408980
10054 00:24:50.412234 R8152: Done initializing
10055 00:24:50.412317
10056 00:24:50.412380 Adding net device
10057 00:24:52.286728
10058 00:24:52.286869 done.
10059 00:24:52.286934
10060 00:24:52.286993 MAC: 00:24:32:30:7c:7b
10061 00:24:52.287050
10062 00:24:52.289347 Sending DHCP discover... done.
10063 00:24:52.289429
10064 00:24:57.990088 Waiting for reply... done.
10065 00:24:57.990249
10066 00:24:57.990343 Sending DHCP request... done.
10067 00:24:57.993271
10068 00:24:57.993376 Waiting for reply... done.
10069 00:24:57.993440
10070 00:24:57.996915 My ip is 192.168.201.14
10071 00:24:57.997029
10072 00:24:57.999805 The DHCP server ip is 192.168.201.1
10073 00:24:57.999911
10074 00:24:58.003399 TFTP server IP predefined by user: 192.168.201.1
10075 00:24:58.003536
10076 00:24:58.010041 Bootfile predefined by user: 14479200/tftp-deploy-krd9ty9v/kernel/image.itb
10077 00:24:58.010187
10078 00:24:58.013450 Sending tftp read request... done.
10079 00:24:58.013539
10080 00:24:58.016668 Waiting for the transfer...
10081 00:24:58.016779
10082 00:24:58.543289 00000000 ################################################################
10083 00:24:58.543424
10084 00:24:59.077424 00080000 ################################################################
10085 00:24:59.077558
10086 00:24:59.600710 00100000 ################################################################
10087 00:24:59.600857
10088 00:25:00.160722 00180000 ################################################################
10089 00:25:00.160860
10090 00:25:00.761663 00200000 ################################################################
10091 00:25:00.761808
10092 00:25:01.386029 00280000 ################################################################
10093 00:25:01.386519
10094 00:25:01.979346 00300000 ################################################################
10095 00:25:01.979480
10096 00:25:02.593879 00380000 ################################################################
10097 00:25:02.594014
10098 00:25:03.207952 00400000 ################################################################
10099 00:25:03.208436
10100 00:25:03.837947 00480000 ################################################################
10101 00:25:03.838205
10102 00:25:04.489056 00500000 ################################################################
10103 00:25:04.489706
10104 00:25:05.142711 00580000 ################################################################
10105 00:25:05.143276
10106 00:25:05.804467 00600000 ################################################################
10107 00:25:05.804982
10108 00:25:06.390120 00680000 ################################################################
10109 00:25:06.390269
10110 00:25:07.030646 00700000 ################################################################
10111 00:25:07.031195
10112 00:25:07.690222 00780000 ################################################################
10113 00:25:07.690740
10114 00:25:08.363928 00800000 ################################################################
10115 00:25:08.364442
10116 00:25:09.007660 00880000 ################################################################
10117 00:25:09.008167
10118 00:25:09.649320 00900000 ################################################################
10119 00:25:09.649840
10120 00:25:10.305712 00980000 ################################################################
10121 00:25:10.306219
10122 00:25:10.940971 00a00000 ################################################################
10123 00:25:10.941119
10124 00:25:11.465603 00a80000 ################################################################
10125 00:25:11.465742
10126 00:25:11.998789 00b00000 ################################################################
10127 00:25:11.998928
10128 00:25:12.518103 00b80000 ################################################################
10129 00:25:12.518248
10130 00:25:13.033417 00c00000 ################################################################
10131 00:25:13.033562
10132 00:25:13.556293 00c80000 ################################################################
10133 00:25:13.556452
10134 00:25:14.073645 00d00000 ################################################################
10135 00:25:14.073774
10136 00:25:14.588767 00d80000 ################################################################
10137 00:25:14.588909
10138 00:25:15.108689 00e00000 ################################################################
10139 00:25:15.108827
10140 00:25:15.619505 00e80000 ################################################################
10141 00:25:15.619645
10142 00:25:16.134163 00f00000 ################################################################
10143 00:25:16.134307
10144 00:25:16.648655 00f80000 ################################################################
10145 00:25:16.648787
10146 00:25:17.165167 01000000 ################################################################
10147 00:25:17.165319
10148 00:25:17.682961 01080000 ################################################################
10149 00:25:17.683103
10150 00:25:18.197407 01100000 ################################################################
10151 00:25:18.197548
10152 00:25:18.713628 01180000 ################################################################
10153 00:25:18.713766
10154 00:25:19.249803 01200000 ################################################################
10155 00:25:19.249944
10156 00:25:19.805044 01280000 ################################################################
10157 00:25:19.805190
10158 00:25:20.341351 01300000 ################################################################
10159 00:25:20.341497
10160 00:25:20.866945 01380000 ################################################################
10161 00:25:20.867088
10162 00:25:21.395340 01400000 ################################################################
10163 00:25:21.395480
10164 00:25:21.925664 01480000 ################################################################
10165 00:25:21.925803
10166 00:25:22.471213 01500000 ################################################################
10167 00:25:22.471350
10168 00:25:23.025365 01580000 ################################################################
10169 00:25:23.025504
10170 00:25:23.573573 01600000 ################################################################
10171 00:25:23.573712
10172 00:25:24.092064 01680000 ################################################################
10173 00:25:24.092200
10174 00:25:24.603342 01700000 ################################################################
10175 00:25:24.603489
10176 00:25:25.114828 01780000 ################################################################
10177 00:25:25.114991
10178 00:25:25.632948 01800000 ################################################################
10179 00:25:25.633091
10180 00:25:26.156838 01880000 ################################################################
10181 00:25:26.156979
10182 00:25:26.685162 01900000 ################################################################
10183 00:25:26.685359
10184 00:25:27.209786 01980000 ################################################################
10185 00:25:27.209919
10186 00:25:27.833219 01a00000 ################################################################
10187 00:25:27.833743
10188 00:25:28.491701 01a80000 ################################################################
10189 00:25:28.492211
10190 00:25:29.156585 01b00000 ################################################################
10191 00:25:29.157081
10192 00:25:29.776180 01b80000 ################################################################
10193 00:25:29.776311
10194 00:25:30.358227 01c00000 ################################################################
10195 00:25:30.358360
10196 00:25:30.930678 01c80000 ################################################################
10197 00:25:30.931235
10198 00:25:31.555590 01d00000 ################################################################
10199 00:25:31.555727
10200 00:25:32.122410 01d80000 ################################################################
10201 00:25:32.122551
10202 00:25:32.617478 01e00000 ######################################################## done.
10203 00:25:32.617927
10204 00:25:32.621398 The bootfile was 31913362 bytes long.
10205 00:25:32.621786
10206 00:25:32.624675 Sending tftp read request... done.
10207 00:25:32.625195
10208 00:25:32.628066 Waiting for the transfer...
10209 00:25:32.628467
10210 00:25:32.628862 00000000 # done.
10211 00:25:32.629365
10212 00:25:32.634188 Command line loaded dynamically from TFTP file: 14479200/tftp-deploy-krd9ty9v/kernel/cmdline
10213 00:25:32.637525
10214 00:25:32.657370 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14479200/extract-nfsrootfs-ini16oba,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10215 00:25:32.657607
10216 00:25:32.660751 Loading FIT.
10217 00:25:32.660968
10218 00:25:32.664049 Image ramdisk-1 has 18739174 bytes.
10219 00:25:32.664269
10220 00:25:32.664487 Image fdt-1 has 47258 bytes.
10221 00:25:32.664693
10222 00:25:32.666967 Image kernel-1 has 13124896 bytes.
10223 00:25:32.667186
10224 00:25:32.676999 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10225 00:25:32.677219
10226 00:25:32.693619 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10227 00:25:32.693850
10228 00:25:32.699926 Choosing best match conf-1 for compat google,spherion-rev2.
10229 00:25:32.704169
10230 00:25:32.708953 Connected to device vid:did:rid of 1ae0:0028:00
10231 00:25:32.716826
10232 00:25:32.720291 tpm_get_response: command 0x17b, return code 0x0
10233 00:25:32.720505
10234 00:25:32.723176 ec_init: CrosEC protocol v3 supported (256, 248)
10235 00:25:32.727509
10236 00:25:32.730713 tpm_cleanup: add release locality here.
10237 00:25:32.730926
10238 00:25:32.731092 Shutting down all USB controllers.
10239 00:25:32.731248
10240 00:25:32.733991 Removing current net device
10241 00:25:32.734202
10242 00:25:32.741453 Exiting depthcharge with code 4 at timestamp: 75871560
10243 00:25:32.741790
10244 00:25:32.744093 LZMA decompressing kernel-1 to 0x821a6718
10245 00:25:32.744387
10246 00:25:32.747628 LZMA decompressing kernel-1 to 0x40000000
10247 00:25:34.364512
10248 00:25:34.365130 jumping to kernel
10249 00:25:34.366903 end: 2.2.4 bootloader-commands (duration 00:00:48) [common]
10250 00:25:34.367424 start: 2.2.5 auto-login-action (timeout 00:03:39) [common]
10251 00:25:34.367826 Setting prompt string to ['Linux version [0-9]']
10252 00:25:34.368194 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10253 00:25:34.368558 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10254 00:25:34.447557
10255 00:25:34.451068 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10256 00:25:34.454510 start: 2.2.5.1 login-action (timeout 00:03:38) [common]
10257 00:25:34.455039 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10258 00:25:34.455438 Setting prompt string to []
10259 00:25:34.455844 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10260 00:25:34.456239 Using line separator: #'\n'#
10261 00:25:34.456570 No login prompt set.
10262 00:25:34.456907 Parsing kernel messages
10263 00:25:34.457416 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10264 00:25:34.458005 [login-action] Waiting for messages, (timeout 00:03:38)
10265 00:25:34.458383 Waiting using forced prompt support (timeout 00:01:49)
10266 00:25:34.474021 [ 0.000000] Linux version 6.1.94-cip23 (KernelCI@build-j239242-arm64-gcc-10-defconfig-arm64-chromebook-c5lwc) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Jun 21 00:04:56 UTC 2024
10267 00:25:34.477541 [ 0.000000] random: crng init done
10268 00:25:34.483950 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10269 00:25:34.487004 [ 0.000000] efi: UEFI not found.
10270 00:25:34.494195 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10271 00:25:34.500482 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10272 00:25:34.510703 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10273 00:25:34.519939 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10274 00:25:34.526650 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10275 00:25:34.532935 [ 0.000000] printk: bootconsole [mtk8250] enabled
10276 00:25:34.539929 [ 0.000000] NUMA: No NUMA configuration found
10277 00:25:34.546320 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10278 00:25:34.550224 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10279 00:25:34.553907 [ 0.000000] Zone ranges:
10280 00:25:34.559981 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10281 00:25:34.563610 [ 0.000000] DMA32 empty
10282 00:25:34.569823 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10283 00:25:34.572709 [ 0.000000] Movable zone start for each node
10284 00:25:34.576022 [ 0.000000] Early memory node ranges
10285 00:25:34.583030 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10286 00:25:34.589342 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10287 00:25:34.596065 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10288 00:25:34.602835 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10289 00:25:34.609434 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10290 00:25:34.616134 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10291 00:25:34.671807 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10292 00:25:34.678583 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10293 00:25:34.684743 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10294 00:25:34.688333 [ 0.000000] psci: probing for conduit method from DT.
10295 00:25:34.694686 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10296 00:25:34.698462 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10297 00:25:34.704838 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10298 00:25:34.707948 [ 0.000000] psci: SMC Calling Convention v1.2
10299 00:25:34.714822 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10300 00:25:34.718377 [ 0.000000] Detected VIPT I-cache on CPU0
10301 00:25:34.724983 [ 0.000000] CPU features: detected: GIC system register CPU interface
10302 00:25:34.731416 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10303 00:25:34.738166 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10304 00:25:34.744726 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10305 00:25:34.753880 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10306 00:25:34.760889 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10307 00:25:34.763866 [ 0.000000] alternatives: applying boot alternatives
10308 00:25:34.771132 [ 0.000000] Fallback order for Node 0: 0
10309 00:25:34.777771 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10310 00:25:34.781031 [ 0.000000] Policy zone: Normal
10311 00:25:34.803636 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14479200/extract-nfsrootfs-ini16oba,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10312 00:25:34.813336 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10313 00:25:34.825376 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10314 00:25:34.834898 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10315 00:25:34.841786 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10316 00:25:34.845369 <6>[ 0.000000] software IO TLB: area num 8.
10317 00:25:34.901462 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10318 00:25:35.050446 <6>[ 0.000000] Memory: 7945760K/8385536K available (18112K kernel code, 4120K rwdata, 22648K rodata, 8512K init, 616K bss, 407008K reserved, 32768K cma-reserved)
10319 00:25:35.057296 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10320 00:25:35.063974 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10321 00:25:35.066972 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10322 00:25:35.074594 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10323 00:25:35.080793 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10324 00:25:35.083887 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10325 00:25:35.093734 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10326 00:25:35.100358 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10327 00:25:35.106724 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10328 00:25:35.113244 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10329 00:25:35.116729 <6>[ 0.000000] GICv3: 608 SPIs implemented
10330 00:25:35.119996 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10331 00:25:35.126546 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10332 00:25:35.130818 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10333 00:25:35.136611 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10334 00:25:35.149593 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10335 00:25:35.162631 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10336 00:25:35.169284 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10337 00:25:35.177778 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10338 00:25:35.190892 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10339 00:25:35.198062 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10340 00:25:35.204062 <6>[ 0.009175] Console: colour dummy device 80x25
10341 00:25:35.213949 <6>[ 0.013923] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10342 00:25:35.220917 <6>[ 0.024365] pid_max: default: 32768 minimum: 301
10343 00:25:35.224019 <6>[ 0.029266] LSM: Security Framework initializing
10344 00:25:35.230634 <6>[ 0.034234] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10345 00:25:35.240100 <6>[ 0.042049] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10346 00:25:35.247305 <6>[ 0.051488] cblist_init_generic: Setting adjustable number of callback queues.
10347 00:25:35.253659 <6>[ 0.058977] cblist_init_generic: Setting shift to 3 and lim to 1.
10348 00:25:35.263371 <6>[ 0.065354] cblist_init_generic: Setting adjustable number of callback queues.
10349 00:25:35.270009 <6>[ 0.072782] cblist_init_generic: Setting shift to 3 and lim to 1.
10350 00:25:35.273853 <6>[ 0.079182] rcu: Hierarchical SRCU implementation.
10351 00:25:35.280393 <6>[ 0.084197] rcu: Max phase no-delay instances is 1000.
10352 00:25:35.287452 <6>[ 0.091264] EFI services will not be available.
10353 00:25:35.289805 <6>[ 0.096228] smp: Bringing up secondary CPUs ...
10354 00:25:35.298407 <6>[ 0.101277] Detected VIPT I-cache on CPU1
10355 00:25:35.304641 <6>[ 0.101346] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10356 00:25:35.311747 <6>[ 0.101376] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10357 00:25:35.314871 <6>[ 0.101716] Detected VIPT I-cache on CPU2
10358 00:25:35.320935 <6>[ 0.101766] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10359 00:25:35.331730 <6>[ 0.101782] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10360 00:25:35.334534 <6>[ 0.102036] Detected VIPT I-cache on CPU3
10361 00:25:35.341356 <6>[ 0.102083] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10362 00:25:35.347963 <6>[ 0.102096] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10363 00:25:35.351130 <6>[ 0.102401] CPU features: detected: Spectre-v4
10364 00:25:35.357590 <6>[ 0.102407] CPU features: detected: Spectre-BHB
10365 00:25:35.360450 <6>[ 0.102412] Detected PIPT I-cache on CPU4
10366 00:25:35.367564 <6>[ 0.102469] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10367 00:25:35.374713 <6>[ 0.102485] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10368 00:25:35.380550 <6>[ 0.102778] Detected PIPT I-cache on CPU5
10369 00:25:35.387342 <6>[ 0.102841] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10370 00:25:35.393618 <6>[ 0.102857] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10371 00:25:35.396840 <6>[ 0.103138] Detected PIPT I-cache on CPU6
10372 00:25:35.403570 <6>[ 0.103204] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10373 00:25:35.413449 <6>[ 0.103220] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10374 00:25:35.417187 <6>[ 0.103516] Detected PIPT I-cache on CPU7
10375 00:25:35.423531 <6>[ 0.103582] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10376 00:25:35.429901 <6>[ 0.103598] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10377 00:25:35.433619 <6>[ 0.103646] smp: Brought up 1 node, 8 CPUs
10378 00:25:35.439837 <6>[ 0.244903] SMP: Total of 8 processors activated.
10379 00:25:35.443381 <6>[ 0.249824] CPU features: detected: 32-bit EL0 Support
10380 00:25:35.453062 <6>[ 0.255188] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10381 00:25:35.459495 <6>[ 0.263989] CPU features: detected: Common not Private translations
10382 00:25:35.466313 <6>[ 0.270505] CPU features: detected: CRC32 instructions
10383 00:25:35.473217 <6>[ 0.275890] CPU features: detected: RCpc load-acquire (LDAPR)
10384 00:25:35.476226 <6>[ 0.281850] CPU features: detected: LSE atomic instructions
10385 00:25:35.483147 <6>[ 0.287668] CPU features: detected: Privileged Access Never
10386 00:25:35.489661 <6>[ 0.293448] CPU features: detected: RAS Extension Support
10387 00:25:35.496180 <6>[ 0.299057] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10388 00:25:35.499505 <6>[ 0.306276] CPU: All CPU(s) started at EL2
10389 00:25:35.505592 <6>[ 0.310619] alternatives: applying system-wide alternatives
10390 00:25:35.516223 <6>[ 0.321472] devtmpfs: initialized
10391 00:25:35.531405 <6>[ 0.330324] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10392 00:25:35.538402 <6>[ 0.340283] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10393 00:25:35.544557 <6>[ 0.348294] pinctrl core: initialized pinctrl subsystem
10394 00:25:35.548370 <6>[ 0.354961] DMI not present or invalid.
10395 00:25:35.554336 <6>[ 0.359369] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10396 00:25:35.564745 <6>[ 0.366151] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10397 00:25:35.571318 <6>[ 0.373741] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10398 00:25:35.581067 <6>[ 0.381961] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10399 00:25:35.584186 <6>[ 0.390204] audit: initializing netlink subsys (disabled)
10400 00:25:35.594094 <5>[ 0.395898] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10401 00:25:35.601336 <6>[ 0.396608] thermal_sys: Registered thermal governor 'step_wise'
10402 00:25:35.607738 <6>[ 0.403866] thermal_sys: Registered thermal governor 'power_allocator'
10403 00:25:35.611242 <6>[ 0.410120] cpuidle: using governor menu
10404 00:25:35.617919 <6>[ 0.421080] NET: Registered PF_QIPCRTR protocol family
10405 00:25:35.624172 <6>[ 0.426565] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10406 00:25:35.627989 <6>[ 0.433668] ASID allocator initialised with 32768 entries
10407 00:25:35.635557 <6>[ 0.440236] Serial: AMBA PL011 UART driver
10408 00:25:35.643482 <4>[ 0.449069] Trying to register duplicate clock ID: 134
10409 00:25:35.702088 <6>[ 0.510561] KASLR enabled
10410 00:25:35.716285 <6>[ 0.518269] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10411 00:25:35.723112 <6>[ 0.525285] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10412 00:25:35.729064 <6>[ 0.531777] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10413 00:25:35.735508 <6>[ 0.538780] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10414 00:25:35.742350 <6>[ 0.545266] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10415 00:25:35.748961 <6>[ 0.552269] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10416 00:25:35.755954 <6>[ 0.558753] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10417 00:25:35.762153 <6>[ 0.565760] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10418 00:25:35.765815 <6>[ 0.573272] ACPI: Interpreter disabled.
10419 00:25:35.774189 <6>[ 0.579701] iommu: Default domain type: Translated
10420 00:25:35.781224 <6>[ 0.584815] iommu: DMA domain TLB invalidation policy: strict mode
10421 00:25:35.784705 <5>[ 0.591479] SCSI subsystem initialized
10422 00:25:35.790657 <6>[ 0.595647] usbcore: registered new interface driver usbfs
10423 00:25:35.797587 <6>[ 0.601381] usbcore: registered new interface driver hub
10424 00:25:35.800392 <6>[ 0.606932] usbcore: registered new device driver usb
10425 00:25:35.808032 <6>[ 0.613026] pps_core: LinuxPPS API ver. 1 registered
10426 00:25:35.817383 <6>[ 0.618221] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10427 00:25:35.820866 <6>[ 0.627565] PTP clock support registered
10428 00:25:35.823864 <6>[ 0.631811] EDAC MC: Ver: 3.0.0
10429 00:25:35.831205 <6>[ 0.636953] FPGA manager framework
10430 00:25:35.837995 <6>[ 0.640642] Advanced Linux Sound Architecture Driver Initialized.
10431 00:25:35.842407 <6>[ 0.647418] vgaarb: loaded
10432 00:25:35.847457 <6>[ 0.650515] clocksource: Switched to clocksource arch_sys_counter
10433 00:25:35.851182 <5>[ 0.656954] VFS: Disk quotas dquot_6.6.0
10434 00:25:35.857527 <6>[ 0.661138] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10435 00:25:35.860643 <6>[ 0.668323] pnp: PnP ACPI: disabled
10436 00:25:35.869469 <6>[ 0.674995] NET: Registered PF_INET protocol family
10437 00:25:35.879179 <6>[ 0.680581] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10438 00:25:35.890816 <6>[ 0.692919] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10439 00:25:35.900851 <6>[ 0.701736] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10440 00:25:35.907071 <6>[ 0.709705] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10441 00:25:35.917121 <6>[ 0.718407] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10442 00:25:35.923128 <6>[ 0.728161] TCP: Hash tables configured (established 65536 bind 65536)
10443 00:25:35.929555 <6>[ 0.735031] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10444 00:25:35.939578 <6>[ 0.742231] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10445 00:25:35.946135 <6>[ 0.749936] NET: Registered PF_UNIX/PF_LOCAL protocol family
10446 00:25:35.952796 <6>[ 0.756091] RPC: Registered named UNIX socket transport module.
10447 00:25:35.956207 <6>[ 0.762244] RPC: Registered udp transport module.
10448 00:25:35.962802 <6>[ 0.767175] RPC: Registered tcp transport module.
10449 00:25:35.969004 <6>[ 0.772107] RPC: Registered tcp NFSv4.1 backchannel transport module.
10450 00:25:35.972332 <6>[ 0.778775] PCI: CLS 0 bytes, default 64
10451 00:25:35.975684 <6>[ 0.783177] Unpacking initramfs...
10452 00:25:35.985457 <6>[ 0.786882] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10453 00:25:35.992245 <6>[ 0.795510] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10454 00:25:35.998596 <6>[ 0.804343] kvm [1]: IPA Size Limit: 40 bits
10455 00:25:36.002128 <6>[ 0.808870] kvm [1]: GICv3: no GICV resource entry
10456 00:25:36.008269 <6>[ 0.813893] kvm [1]: disabling GICv2 emulation
10457 00:25:36.015346 <6>[ 0.818579] kvm [1]: GIC system register CPU interface enabled
10458 00:25:36.018561 <6>[ 0.824743] kvm [1]: vgic interrupt IRQ18
10459 00:25:36.024855 <6>[ 0.830579] kvm [1]: VHE mode initialized successfully
10460 00:25:36.032142 <5>[ 0.836980] Initialise system trusted keyrings
10461 00:25:36.038031 <6>[ 0.841800] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10462 00:25:36.046120 <6>[ 0.851818] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10463 00:25:36.052891 <5>[ 0.858193] NFS: Registering the id_resolver key type
10464 00:25:36.056608 <5>[ 0.863501] Key type id_resolver registered
10465 00:25:36.062579 <5>[ 0.867918] Key type id_legacy registered
10466 00:25:36.069430 <6>[ 0.872195] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10467 00:25:36.076404 <6>[ 0.879115] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10468 00:25:36.082726 <6>[ 0.886822] 9p: Installing v9fs 9p2000 file system support
10469 00:25:36.119119 <5>[ 0.924671] Key type asymmetric registered
10470 00:25:36.122621 <5>[ 0.928998] Asymmetric key parser 'x509' registered
10471 00:25:36.132451 <6>[ 0.934135] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10472 00:25:36.135309 <6>[ 0.941751] io scheduler mq-deadline registered
10473 00:25:36.138806 <6>[ 0.946529] io scheduler kyber registered
10474 00:25:36.157715 <6>[ 0.963450] EINJ: ACPI disabled.
10475 00:25:36.191079 <4>[ 0.989556] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10476 00:25:36.200446 <4>[ 1.000204] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10477 00:25:36.215644 <6>[ 1.020998] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10478 00:25:36.223528 <6>[ 1.029038] printk: console [ttyS0] disabled
10479 00:25:36.251319 <6>[ 1.053685] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10480 00:25:36.258272 <6>[ 1.063166] printk: console [ttyS0] enabled
10481 00:25:36.261007 <6>[ 1.063166] printk: console [ttyS0] enabled
10482 00:25:36.267821 <6>[ 1.072064] printk: bootconsole [mtk8250] disabled
10483 00:25:36.271351 <6>[ 1.072064] printk: bootconsole [mtk8250] disabled
10484 00:25:36.277509 <6>[ 1.083152] SuperH (H)SCI(F) driver initialized
10485 00:25:36.281409 <6>[ 1.088449] msm_serial: driver initialized
10486 00:25:36.295151 <6>[ 1.097377] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10487 00:25:36.304711 <6>[ 1.105927] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10488 00:25:36.312001 <6>[ 1.114470] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10489 00:25:36.321563 <6>[ 1.123099] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10490 00:25:36.332024 <6>[ 1.131806] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10491 00:25:36.338113 <6>[ 1.140521] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10492 00:25:36.348429 <6>[ 1.149061] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10493 00:25:36.354838 <6>[ 1.157879] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10494 00:25:36.364766 <6>[ 1.166420] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10495 00:25:36.376981 <6>[ 1.181955] loop: module loaded
10496 00:25:36.383273 <6>[ 1.187928] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10497 00:25:36.405548 <4>[ 1.211265] mtk-pmic-keys: Failed to locate of_node [id: -1]
10498 00:25:36.412778 <6>[ 1.218061] megasas: 07.719.03.00-rc1
10499 00:25:36.422506 <6>[ 1.227587] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10500 00:25:36.428604 <6>[ 1.233904] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10501 00:25:36.445224 <6>[ 1.250595] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10502 00:25:36.501728 <6>[ 1.300423] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10503 00:25:36.773891 <6>[ 1.579512] Freeing initrd memory: 18296K
10504 00:25:36.785626 <6>[ 1.590961] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10505 00:25:36.796338 <6>[ 1.601774] tun: Universal TUN/TAP device driver, 1.6
10506 00:25:36.800301 <6>[ 1.607835] thunder_xcv, ver 1.0
10507 00:25:36.803037 <6>[ 1.611337] thunder_bgx, ver 1.0
10508 00:25:36.806002 <6>[ 1.614830] nicpf, ver 1.0
10509 00:25:36.816434 <6>[ 1.618835] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10510 00:25:36.819966 <6>[ 1.626311] hns3: Copyright (c) 2017 Huawei Corporation.
10511 00:25:36.823624 <6>[ 1.631898] hclge is initializing
10512 00:25:36.830153 <6>[ 1.635474] e1000: Intel(R) PRO/1000 Network Driver
10513 00:25:36.836714 <6>[ 1.640603] e1000: Copyright (c) 1999-2006 Intel Corporation.
10514 00:25:36.840106 <6>[ 1.646615] e1000e: Intel(R) PRO/1000 Network Driver
10515 00:25:36.846957 <6>[ 1.651830] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10516 00:25:36.853110 <6>[ 1.658018] igb: Intel(R) Gigabit Ethernet Network Driver
10517 00:25:36.859663 <6>[ 1.663668] igb: Copyright (c) 2007-2014 Intel Corporation.
10518 00:25:36.866837 <6>[ 1.669503] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10519 00:25:36.873103 <6>[ 1.676022] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10520 00:25:36.876441 <6>[ 1.682476] sky2: driver version 1.30
10521 00:25:36.882931 <6>[ 1.687404] usbcore: registered new device driver r8152-cfgselector
10522 00:25:36.889456 <6>[ 1.693938] usbcore: registered new interface driver r8152
10523 00:25:36.896491 <6>[ 1.699751] VFIO - User Level meta-driver version: 0.3
10524 00:25:36.902821 <6>[ 1.707940] usbcore: registered new interface driver usb-storage
10525 00:25:36.909167 <6>[ 1.714380] usbcore: registered new device driver onboard-usb-hub
10526 00:25:36.917838 <6>[ 1.723529] mt6397-rtc mt6359-rtc: registered as rtc0
10527 00:25:36.928043 <6>[ 1.728995] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-21T00:25:37 UTC (1718929537)
10528 00:25:36.931345 <6>[ 1.738558] i2c_dev: i2c /dev entries driver
10529 00:25:36.945322 <4>[ 1.750452] cpu cpu0: supply cpu not found, using dummy regulator
10530 00:25:36.951816 <4>[ 1.756872] cpu cpu1: supply cpu not found, using dummy regulator
10531 00:25:36.958241 <4>[ 1.763279] cpu cpu2: supply cpu not found, using dummy regulator
10532 00:25:36.964843 <4>[ 1.769677] cpu cpu3: supply cpu not found, using dummy regulator
10533 00:25:36.971209 <4>[ 1.776072] cpu cpu4: supply cpu not found, using dummy regulator
10534 00:25:36.978148 <4>[ 1.782468] cpu cpu5: supply cpu not found, using dummy regulator
10535 00:25:36.984892 <4>[ 1.788882] cpu cpu6: supply cpu not found, using dummy regulator
10536 00:25:36.991567 <4>[ 1.795279] cpu cpu7: supply cpu not found, using dummy regulator
10537 00:25:37.011363 <6>[ 1.816926] cpu cpu0: EM: created perf domain
10538 00:25:37.014702 <6>[ 1.821856] cpu cpu4: EM: created perf domain
10539 00:25:37.022000 <6>[ 1.827439] sdhci: Secure Digital Host Controller Interface driver
10540 00:25:37.028681 <6>[ 1.833870] sdhci: Copyright(c) Pierre Ossman
10541 00:25:37.035197 <6>[ 1.838824] Synopsys Designware Multimedia Card Interface Driver
10542 00:25:37.041749 <6>[ 1.845464] sdhci-pltfm: SDHCI platform and OF driver helper
10543 00:25:37.045392 <6>[ 1.845501] mmc0: CQHCI version 5.10
10544 00:25:37.052047 <6>[ 1.855923] ledtrig-cpu: registered to indicate activity on CPUs
10545 00:25:37.058133 <6>[ 1.863018] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10546 00:25:37.064486 <6>[ 1.870076] usbcore: registered new interface driver usbhid
10547 00:25:37.068645 <6>[ 1.875916] usbhid: USB HID core driver
10548 00:25:37.078373 <6>[ 1.880111] spi_master spi0: will run message pump with realtime priority
10549 00:25:37.121492 <6>[ 1.920081] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10550 00:25:37.139913 <6>[ 1.935758] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10551 00:25:37.143186 <6>[ 1.946184] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x15414
10552 00:25:37.151642 <6>[ 1.956943] cros-ec-spi spi0.0: Chrome EC device registered
10553 00:25:37.157559 <6>[ 1.962970] mmc0: Command Queue Engine enabled
10554 00:25:37.164396 <6>[ 1.967747] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10555 00:25:37.167885 <6>[ 1.975056] mmcblk0: mmc0:0001 DA4128 116 GiB
10556 00:25:37.178235 <6>[ 1.983960] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10557 00:25:37.186169 <6>[ 1.991804] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10558 00:25:37.196375 <6>[ 1.996483] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10559 00:25:37.199958 <6>[ 1.997790] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10560 00:25:37.206424 <6>[ 2.007766] NET: Registered PF_PACKET protocol family
10561 00:25:37.212277 <6>[ 2.012264] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10562 00:25:37.215761 <6>[ 2.016962] 9pnet: Installing 9P2000 support
10563 00:25:37.222406 <5>[ 2.027969] Key type dns_resolver registered
10564 00:25:37.225905 <6>[ 2.033025] registered taskstats version 1
10565 00:25:37.232389 <5>[ 2.037422] Loading compiled-in X.509 certificates
10566 00:25:37.264127 <4>[ 2.063107] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10567 00:25:37.274184 <4>[ 2.073924] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10568 00:25:37.289810 <6>[ 2.095509] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10569 00:25:37.296435 <6>[ 2.102345] xhci-mtk 11200000.usb: xHCI Host Controller
10570 00:25:37.304045 <6>[ 2.107887] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10571 00:25:37.313480 <6>[ 2.115753] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10572 00:25:37.319934 <6>[ 2.125190] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10573 00:25:37.326892 <6>[ 2.131389] xhci-mtk 11200000.usb: xHCI Host Controller
10574 00:25:37.333019 <6>[ 2.136879] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10575 00:25:37.340383 <6>[ 2.144538] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10576 00:25:37.346832 <6>[ 2.152407] hub 1-0:1.0: USB hub found
10577 00:25:37.350264 <6>[ 2.156457] hub 1-0:1.0: 1 port detected
10578 00:25:37.359784 <6>[ 2.160754] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10579 00:25:37.363099 <6>[ 2.169549] hub 2-0:1.0: USB hub found
10580 00:25:37.366582 <6>[ 2.173591] hub 2-0:1.0: 1 port detected
10581 00:25:37.375530 <6>[ 2.181518] mtk-msdc 11f70000.mmc: Got CD GPIO
10582 00:25:37.388160 <6>[ 2.190720] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10583 00:25:37.395567 <6>[ 2.199095] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10584 00:25:37.405642 <6>[ 2.207436] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10585 00:25:37.415647 <6>[ 2.215776] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10586 00:25:37.422227 <6>[ 2.224114] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10587 00:25:37.432134 <6>[ 2.232453] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10588 00:25:37.438582 <6>[ 2.240800] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10589 00:25:37.448438 <6>[ 2.249137] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10590 00:25:37.454877 <6>[ 2.257489] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10591 00:25:37.465501 <6>[ 2.265827] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10592 00:25:37.471775 <6>[ 2.274165] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10593 00:25:37.482006 <6>[ 2.282512] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10594 00:25:37.488549 <6>[ 2.290850] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10595 00:25:37.498445 <6>[ 2.299192] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10596 00:25:37.505253 <6>[ 2.307530] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10597 00:25:37.511694 <6>[ 2.316208] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10598 00:25:37.517852 <6>[ 2.323350] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10599 00:25:37.524935 <6>[ 2.330162] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10600 00:25:37.534344 <6>[ 2.336932] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10601 00:25:37.541557 <6>[ 2.343902] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10602 00:25:37.547876 <6>[ 2.350766] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10603 00:25:37.557859 <6>[ 2.359897] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10604 00:25:37.567994 <6>[ 2.369020] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10605 00:25:37.577623 <6>[ 2.378314] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10606 00:25:37.587567 <6>[ 2.387782] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10607 00:25:37.597407 <6>[ 2.397250] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10608 00:25:37.603841 <6>[ 2.406369] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10609 00:25:37.613954 <6>[ 2.415836] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10610 00:25:37.623903 <6>[ 2.424955] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10611 00:25:37.633396 <6>[ 2.434249] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10612 00:25:37.643307 <6>[ 2.444408] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10613 00:25:37.653422 <6>[ 2.456058] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10614 00:25:37.661509 <6>[ 2.467295] Trying to probe devices needed for running init ...
10615 00:25:37.672409 <3>[ 2.474640] mt8192-audio 11210000.syscon:mt8192-afe-pcm: could not get audiosys reset:-517
10616 00:25:37.776666 <6>[ 2.578663] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10617 00:25:37.931476 <6>[ 2.736461] hub 1-1:1.0: USB hub found
10618 00:25:37.934309 <6>[ 2.740986] hub 1-1:1.0: 4 ports detected
10619 00:25:37.944632 <6>[ 2.750307] hub 1-1:1.0: USB hub found
10620 00:25:37.948313 <6>[ 2.754773] hub 1-1:1.0: 4 ports detected
10621 00:25:38.057090 <6>[ 2.859130] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10622 00:25:38.083371 <6>[ 2.888721] hub 2-1:1.0: USB hub found
10623 00:25:38.086299 <6>[ 2.893238] hub 2-1:1.0: 3 ports detected
10624 00:25:38.098602 <6>[ 2.903942] hub 2-1:1.0: USB hub found
10625 00:25:38.100970 <6>[ 2.908412] hub 2-1:1.0: 3 ports detected
10626 00:25:38.269137 <6>[ 3.070840] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10627 00:25:38.400860 <6>[ 3.206656] hub 1-1.4:1.0: USB hub found
10628 00:25:38.404710 <6>[ 3.211321] hub 1-1.4:1.0: 2 ports detected
10629 00:25:38.416793 <6>[ 3.222333] hub 1-1.4:1.0: USB hub found
10630 00:25:38.419829 <6>[ 3.226976] hub 1-1.4:1.0: 2 ports detected
10631 00:25:38.481010 <6>[ 3.283046] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10632 00:25:38.589216 <6>[ 3.391502] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10633 00:25:38.625484 <4>[ 3.427909] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10634 00:25:38.635004 <4>[ 3.437018] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10635 00:25:38.670889 <6>[ 3.476361] r8152 2-1.3:1.0 eth0: v1.12.13
10636 00:25:38.716169 <6>[ 3.518572] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10637 00:25:38.904511 <6>[ 3.706669] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10638 00:25:40.261354 <6>[ 5.066919] r8152 2-1.3:1.0 eth0: carrier on
10639 00:25:42.076503 <5>[ 5.094615] Sending DHCP requests .
10640 00:25:42.082750 <3>[ 6.882779] DHCP/BOOTP: Reply not for us on eth0, op[2] xid[26d1d0ab]
10641 00:25:42.089537 <3>[ 6.893444] DHCP/BOOTP: Reply not for us on eth0, op[2] xid[26d1d0ab]
10642 00:25:42.606034 <4>[ 7.398810] ., OK
10643 00:25:42.614829 <6>[ 7.416953] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10644 00:25:42.618478 <6>[ 7.425256] IP-Config: Complete:
10645 00:25:42.627929 <6>[ 7.428750] device=eth0, hwaddr=00:24:32:30:7c:7b, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10646 00:25:42.637817 <6>[ 7.439456] host=mt8192-asurada-spherion-r0-cbg-2, domain=lava-rack, nis-domain=(none)
10647 00:25:42.644769 <6>[ 7.448072] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10648 00:25:42.648159 <6>[ 7.448081] nameserver0=192.168.201.1
10649 00:25:42.654723 <6>[ 7.460264] clk: Disabling unused clocks
10650 00:25:42.657900 <6>[ 7.465794] ALSA device list:
10651 00:25:42.660841 <6>[ 7.469091] No soundcards found.
10652 00:25:42.671123 <6>[ 7.476542] Freeing unused kernel memory: 8512K
10653 00:25:42.673227 <6>[ 7.481504] Run /init as init process
10654 00:25:42.683492 Loading, please wait...
10655 00:25:42.712538 Starting systemd-udevd version 252.22-1~deb12u1
10656 00:25:42.989104 <6>[ 7.792005] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10657 00:25:42.995785 <6>[ 7.792123] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10658 00:25:43.001869 <6>[ 7.793221] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10659 00:25:43.011985 <6>[ 7.799840] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10660 00:25:43.018638 <6>[ 7.804421] remoteproc remoteproc0: scp is available
10661 00:25:43.021796 <6>[ 7.804502] remoteproc remoteproc0: powering up scp
10662 00:25:43.031588 <6>[ 7.804509] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10663 00:25:43.038506 <6>[ 7.804527] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10664 00:25:43.045007 <6>[ 7.812783] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10665 00:25:43.054834 <6>[ 7.815154] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10666 00:25:43.061751 <6>[ 7.823787] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10667 00:25:43.071351 <4>[ 7.824144] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10668 00:25:43.078330 <4>[ 7.825386] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10669 00:25:43.084579 <4>[ 7.825644] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10670 00:25:43.091866 <6>[ 7.829670] mc: Linux media interface: v0.10
10671 00:25:43.098865 <3>[ 7.829773] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10672 00:25:43.105456 <3>[ 7.829786] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10673 00:25:43.115656 <3>[ 7.829789] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10674 00:25:43.121741 <3>[ 7.829865] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10675 00:25:43.131986 <3>[ 7.829869] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10676 00:25:43.138565 <3>[ 7.829872] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10677 00:25:43.145556 <3>[ 7.829876] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10678 00:25:43.155218 <3>[ 7.829879] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10679 00:25:43.161932 <3>[ 7.829895] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10680 00:25:43.172287 <3>[ 7.829917] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10681 00:25:43.178840 <3>[ 7.829920] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10682 00:25:43.189465 <3>[ 7.829922] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10683 00:25:43.195272 <3>[ 7.829942] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10684 00:25:43.204790 <3>[ 7.829944] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10685 00:25:43.211909 <3>[ 7.829947] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10686 00:25:43.218472 <3>[ 7.829949] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10687 00:25:43.228385 <3>[ 7.829951] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10688 00:25:43.235166 <3>[ 7.829963] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10689 00:25:43.244760 <6>[ 7.835177] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10690 00:25:43.251208 <6>[ 7.836148] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10691 00:25:43.261345 <4>[ 7.877502] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10692 00:25:43.264437 <4>[ 7.877502] Fallback method does not support PEC.
10693 00:25:43.274442 <6>[ 7.882346] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10694 00:25:43.280853 <3>[ 7.906044] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10695 00:25:43.290903 <6>[ 7.909804] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10696 00:25:43.297901 <6>[ 7.930181] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10697 00:25:43.304421 <6>[ 7.930216] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10698 00:25:43.311132 <6>[ 7.930224] remoteproc remoteproc0: remote processor scp is now up
10699 00:25:43.320615 <6>[ 7.933962] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10700 00:25:43.331043 <6>[ 7.946264] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10701 00:25:43.337357 <6>[ 7.950133] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10702 00:25:43.347722 <6>[ 7.950462] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10703 00:25:43.357048 <6>[ 7.951110] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10704 00:25:43.363918 <6>[ 7.952181] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10705 00:25:43.373427 <6>[ 7.954204] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10706 00:25:43.380462 <6>[ 7.955389] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10707 00:25:43.386550 <6>[ 7.955397] pci_bus 0000:00: root bus resource [bus 00-ff]
10708 00:25:43.393728 <6>[ 7.955405] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10709 00:25:43.402953 <6>[ 7.955411] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10710 00:25:43.409858 <6>[ 7.955450] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10711 00:25:43.416430 <6>[ 7.955475] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10712 00:25:43.419840 <6>[ 7.955565] pci 0000:00:00.0: supports D1 D2
10713 00:25:43.426557 <6>[ 7.955570] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10714 00:25:43.436335 <6>[ 7.957328] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10715 00:25:43.442764 <6>[ 7.957441] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10716 00:25:43.449730 <6>[ 7.957472] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10717 00:25:43.456271 <6>[ 7.957493] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10718 00:25:43.462592 <6>[ 7.957512] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10719 00:25:43.469661 <6>[ 7.957625] pci 0000:01:00.0: supports D1 D2
10720 00:25:43.476040 <6>[ 7.957629] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10721 00:25:43.485956 <3>[ 7.959841] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10722 00:25:43.492608 <6>[ 7.966343] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10723 00:25:43.499048 <6>[ 7.971439] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10724 00:25:43.508969 <6>[ 7.971490] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10725 00:25:43.515431 <6>[ 7.971495] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10726 00:25:43.525178 <6>[ 7.971508] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10727 00:25:43.531875 <6>[ 7.971522] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10728 00:25:43.541773 <6>[ 7.971535] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10729 00:25:43.544902 <6>[ 7.971548] pci 0000:00:00.0: PCI bridge to [bus 01]
10730 00:25:43.554938 <6>[ 7.971554] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10731 00:25:43.558386 <6>[ 7.971763] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10732 00:25:43.565186 <6>[ 7.976849] videodev: Linux video capture interface: v2.00
10733 00:25:43.572233 <6>[ 7.977881] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10734 00:25:43.578179 <6>[ 7.978152] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10735 00:25:43.581476 <6>[ 7.991374] Bluetooth: Core ver 2.22
10736 00:25:43.587815 <5>[ 8.000991] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10737 00:25:43.594821 <6>[ 8.007045] NET: Registered PF_BLUETOOTH protocol family
10738 00:25:43.601474 <5>[ 8.027151] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10739 00:25:43.607796 <6>[ 8.039318] Bluetooth: HCI device and connection manager initialized
10740 00:25:43.614328 <6>[ 8.039352] Bluetooth: HCI socket layer initialized
10741 00:25:43.620998 <5>[ 8.047695] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10742 00:25:43.628079 <6>[ 8.055649] Bluetooth: L2CAP socket layer initialized
10743 00:25:43.634115 <6>[ 8.056765] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10744 00:25:43.647252 <6>[ 8.058038] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10745 00:25:43.653713 <6>[ 8.058194] usbcore: registered new interface driver uvcvideo
10746 00:25:43.661250 <4>[ 8.063301] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10747 00:25:43.667047 <6>[ 8.063863] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10748 00:25:43.673579 <6>[ 8.076884] Bluetooth: SCO socket layer initialized
10749 00:25:43.677292 <6>[ 8.084785] cfg80211: failed to load regulatory.db
10750 00:25:43.687368 <6>[ 8.167498] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10751 00:25:43.691114 <6>[ 8.227967] usbcore: registered new interface driver btusb
10752 00:25:43.701081 <4>[ 8.229091] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10753 00:25:43.706811 <3>[ 8.229107] Bluetooth: hci0: Failed to load firmware file (-2)
10754 00:25:43.713253 <3>[ 8.229113] Bluetooth: hci0: Failed to set up firmware (-2)
10755 00:25:43.723104 <4>[ 8.229120] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10756 00:25:43.729884 <6>[ 8.232087] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10757 00:25:43.752270 <6>[ 8.558864] mt7921e 0000:01:00.0: ASIC revision: 79610010
10758 00:25:43.854526 <6>[ 8.658295] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10759 00:25:43.857983 <6>[ 8.658295]
10760 00:25:43.861302 Begin: Loading essential drivers ... done.
10761 00:25:43.865324 Begin: Running /scripts/init-premount ... done.
10762 00:25:43.871652 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10763 00:25:43.881538 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10764 00:25:43.884683 Device /sys/class/net/eth0 found
10765 00:25:43.884805 done.
10766 00:25:43.890738 Begin: Waiting up to 180 secs for any network device to become available ... done.
10767 00:25:43.936229 IP-Config: eth0 hardware address 00:24:32:30:7c:7b mtu 1500 DHCP
10768 00:25:43.944195 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10769 00:25:43.950617 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10770 00:25:43.957625 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10771 00:25:43.964370 host : mt8192-asurada-spherion-r0-cbg-2
10772 00:25:43.971001 domain : lava-rack
10773 00:25:43.974429 rootserver: 192.168.201.1 rootpath:
10774 00:25:43.977470 filename :
10775 00:25:44.126791 <6>[ 8.930356] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10776 00:25:44.147249 done.
10777 00:25:44.156452 Begin: Running /scripts/nfs-bottom ... done.
10778 00:25:44.172037 Begin: Running /scripts/init-bottom ... done.
10779 00:25:45.570207 <6>[ 10.376909] NET: Registered PF_INET6 protocol family
10780 00:25:45.577908 <6>[ 10.384569] Segment Routing with IPv6
10781 00:25:45.580752 <6>[ 10.388568] In-situ OAM (IOAM) with IPv6
10782 00:25:45.767109 <30>[ 10.547216] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10783 00:25:45.773981 <30>[ 10.580341] systemd[1]: Detected architecture arm64.
10784 00:25:45.784115
10785 00:25:45.787136 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10786 00:25:45.787559
10787 00:25:45.810097 <30>[ 10.617020] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10788 00:25:46.955718 <30>[ 11.759451] systemd[1]: Queued start job for default target graphical.target.
10789 00:25:47.011877 <30>[ 11.815840] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10790 00:25:47.018537 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10791 00:25:47.040968 <30>[ 11.844599] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10792 00:25:47.050886 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10793 00:25:47.069217 <30>[ 11.872551] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10794 00:25:47.078680 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10795 00:25:47.096291 <30>[ 11.900217] systemd[1]: Created slice user.slice - User and Session Slice.
10796 00:25:47.103218 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10797 00:25:47.126951 <30>[ 11.927115] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10798 00:25:47.137188 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10799 00:25:47.155042 <30>[ 11.955050] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10800 00:25:47.161990 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10801 00:25:47.189821 <30>[ 11.983454] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10802 00:25:47.199914 <30>[ 12.003349] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10803 00:25:47.205924 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10804 00:25:47.223500 <30>[ 12.026834] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10805 00:25:47.230064 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10806 00:25:47.247538 <30>[ 12.050879] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10807 00:25:47.257241 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10808 00:25:47.272689 <30>[ 12.078918] systemd[1]: Reached target paths.target - Path Units.
10809 00:25:47.281760 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10810 00:25:47.299654 <30>[ 12.103281] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10811 00:25:47.306318 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10812 00:25:47.319837 <30>[ 12.126801] systemd[1]: Reached target slices.target - Slice Units.
10813 00:25:47.329965 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10814 00:25:47.344155 <30>[ 12.151292] systemd[1]: Reached target swap.target - Swaps.
10815 00:25:47.351004 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10816 00:25:47.371254 <30>[ 12.175336] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10817 00:25:47.380976 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10818 00:25:47.399330 <30>[ 12.203285] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10819 00:25:47.409040 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10820 00:25:47.431051 <30>[ 12.234560] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10821 00:25:47.440839 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10822 00:25:47.456074 <30>[ 12.260279] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10823 00:25:47.466296 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10824 00:25:47.483314 <30>[ 12.287505] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10825 00:25:47.490103 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10826 00:25:47.508686 <30>[ 12.312336] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10827 00:25:47.517852 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10828 00:25:47.538538 <30>[ 12.341843] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10829 00:25:47.548077 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10830 00:25:47.565385 <30>[ 12.367294] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10831 00:25:47.573656 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10832 00:25:47.623552 <30>[ 12.427332] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10833 00:25:47.629756 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10834 00:25:47.648999 <30>[ 12.453321] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10835 00:25:47.655859 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10836 00:25:47.678540 <30>[ 12.482495] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10837 00:25:47.684958 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10838 00:25:47.709690 <30>[ 12.507368] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10839 00:25:47.747369 <30>[ 12.551599] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10840 00:25:47.757764 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10841 00:25:47.780837 <30>[ 12.584684] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10842 00:25:47.787612 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10843 00:25:47.812260 <30>[ 12.616402] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10844 00:25:47.818829 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10845 00:25:47.845060 <30>[ 12.648645] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10846 00:25:47.854626 Startin<6>[ 12.657750] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10847 00:25:47.861102 g [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10848 00:25:47.884396 <30>[ 12.688690] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10849 00:25:47.894609 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10850 00:25:47.951516 <30>[ 12.755677] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10851 00:25:47.958345 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10852 00:25:47.982824 <30>[ 12.786795] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10853 00:25:47.992497 Starting [0;1;39mmodprobe@loop.ser…e<6>[ 12.798298] fuse: init (API version 7.37)
10854 00:25:47.992589 [0m - Load Kernel Module loop...
10855 00:25:48.020524 <30>[ 12.823968] systemd[1]: Starting systemd-journald.service - Journal Service...
10856 00:25:48.026594 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10857 00:25:48.059118 <30>[ 12.863432] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10858 00:25:48.066071 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10859 00:25:48.096338 <30>[ 12.897424] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10860 00:25:48.103126 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10861 00:25:48.129448 <30>[ 12.933562] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10862 00:25:48.139068 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10863 00:25:48.158828 <30>[ 12.961975] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10864 00:25:48.172364 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug Al<3>[ 12.975532] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10865 00:25:48.175065 l udev Devices...
10866 00:25:48.199850 <30>[ 13.003639] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10867 00:25:48.213736 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - H<3>[ 13.016280] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10868 00:25:48.217084 uge Pages File System.
10869 00:25:48.235448 <30>[ 13.039201] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10870 00:25:48.242198 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10871 00:25:48.257687 <3>[ 13.061606] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10872 00:25:48.267655 <30>[ 13.071327] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10873 00:25:48.274689 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10874 00:25:48.287747 <3>[ 13.091807] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10875 00:25:48.298478 <30>[ 13.101404] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10876 00:25:48.307310 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10877 00:25:48.323800 <30>[ 13.127589] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10878 00:25:48.330698 <3>[ 13.130548] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10879 00:25:48.340656 <30>[ 13.135372] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10880 00:25:48.347352 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10881 00:25:48.359796 <3>[ 13.163670] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10882 00:25:48.369592 <30>[ 13.173784] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10883 00:25:48.376646 <30>[ 13.182270] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10884 00:25:48.389723 [[0;32m OK [0m] Finished [0<3>[ 13.192521] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10885 00:25:48.396251 ;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10886 00:25:48.408578 <30>[ 13.215770] systemd[1]: modprobe@drm.service: Deactivated successfully.
10887 00:25:48.419299 <30>[ 13.223626] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10888 00:25:48.426169 <3>[ 13.224138] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10889 00:25:48.436147 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10890 00:25:48.457141 <30>[ 13.260999] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10891 00:25:48.463295 <3>[ 13.261141] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10892 00:25:48.473182 <30>[ 13.269417] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10893 00:25:48.483066 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10894 00:25:48.494085 <3>[ 13.297768] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10895 00:25:48.504654 <30>[ 13.308658] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10896 00:25:48.512457 <30>[ 13.316428] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10897 00:25:48.519326 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10898 00:25:48.541459 <30>[ 13.344752] systemd[1]: modprobe@loop.service: Deactivated successfully.
10899 00:25:48.547826 <30>[ 13.352391] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
10900 00:25:48.558004 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10901 00:25:48.575096 <4>[ 13.372410] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10902 00:25:48.585060 <3>[ 13.388064] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10903 00:25:48.591375 <30>[ 13.388745] systemd[1]: Started systemd-journald.service - Journal Service.
10904 00:25:48.598323 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10905 00:25:48.623818 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10906 00:25:48.640758 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10907 00:25:48.660167 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10908 00:25:48.679945 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10909 00:25:48.701207 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10910 00:25:48.755551 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10911 00:25:48.773211 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10912 00:25:48.793822 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10913 00:25:48.819286 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10914 00:25:48.856517 Starting [0;1;39msyste<46>[ 13.658096] systemd-journald[301]: Received client request to flush runtime journal.
10915 00:25:48.858842 md-sysctl.se…ce[0m - Apply Kernel Variables...
10916 00:25:48.887298 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10917 00:25:48.916034 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10918 00:25:48.936087 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10919 00:25:48.960181 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10920 00:25:48.981083 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10921 00:25:49.979502 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10922 00:25:50.035975 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10923 00:25:50.276591 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10924 00:25:50.396102 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10925 00:25:50.419063 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10926 00:25:50.434833 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10927 00:25:50.496427 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10928 00:25:50.522653 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10929 00:25:50.768035 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10930 00:25:50.831972 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10931 00:25:50.903552 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10932 00:25:51.221662 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10933 00:25:51.228139 <6>[ 16.035035] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10934 00:25:51.246859 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10935 00:25:51.301424 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10936 00:25:51.410845 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10937 00:25:51.434821 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10938 00:25:51.458531 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10939 00:25:51.550232 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10940 00:25:51.593220 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10941 00:25:51.608484 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10942 00:25:51.627311 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10943 00:25:51.643841 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10944 00:25:51.720497 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10945 00:25:51.726537 <46>[ 16.532149] systemd-journald[301]: Time jumped backwards, rotating.
10946 00:25:51.743238 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10947 00:25:51.764139 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10948 00:25:51.783055 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10949 00:25:51.798683 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10950 00:25:52.511135 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
10951 00:25:52.837814 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
10952 00:25:52.858946 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
10953 00:25:53.207472 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
10954 00:25:53.230937 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10955 00:25:53.246515 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10956 00:25:53.266046 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10957 00:25:53.283587 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10958 00:25:53.298779 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10959 00:25:53.336286 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10960 00:25:53.374252 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
10961 00:25:53.443395 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10962 00:25:53.481106 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
10963 00:25:53.499688 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10964 00:25:53.673365 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
10965 00:25:53.735588 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
10966 00:25:53.757661 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
10967 00:25:53.775172 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
10968 00:25:53.792093 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
10969 00:25:53.827773 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
10970 00:25:53.852009 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
10971 00:25:53.876959 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
10972 00:25:53.899685 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
10973 00:25:53.956088 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
10974 00:25:54.005289 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
10975 00:25:54.055357
10976 00:25:54.058537 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
10977 00:25:54.058624
10978 00:25:54.061820 debian-bookworm-arm64 login: root (automatic login)
10979 00:25:54.061902
10980 00:25:54.365022 Linux debian-bookworm-arm64 6.1.94-cip23 #1 SMP PREEMPT Fri Jun 21 00:04:56 UTC 2024 aarch64
10981 00:25:54.365564
10982 00:25:54.371483 The programs included with the Debian GNU/Linux system are free software;
10983 00:25:54.378402 the exact distribution terms for each program are described in the
10984 00:25:54.381382 individual files in /usr/share/doc/*/copyright.
10985 00:25:54.381863
10986 00:25:54.388122 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10987 00:25:54.391494 permitted by applicable law.
10988 00:25:54.502702 Matched prompt #10: / #
10990 00:25:54.502968 Setting prompt string to ['/ #']
10991 00:25:54.503062 end: 2.2.5.1 login-action (duration 00:00:20) [common]
10993 00:25:54.503253 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
10994 00:25:54.503339 start: 2.2.6 expect-shell-connection (timeout 00:03:18) [common]
10995 00:25:54.503410 Setting prompt string to ['/ #']
10996 00:25:54.503471 Forcing a shell prompt, looking for ['/ #']
10998 00:25:54.553685 / #
10999 00:25:54.553788 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11000 00:25:54.553880 Waiting using forced prompt support (timeout 00:02:30)
11001 00:25:54.559027
11002 00:25:54.559296 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11003 00:25:54.559390 start: 2.2.7 export-device-env (timeout 00:03:18) [common]
11005 00:25:54.659730 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14479200/extract-nfsrootfs-ini16oba'
11006 00:25:54.665359 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14479200/extract-nfsrootfs-ini16oba'
11008 00:25:54.766035 / # export NFS_SERVER_IP='192.168.201.1'
11009 00:25:54.772659 export NFS_SERVER_IP='192.168.201.1'
11010 00:25:54.773586 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11011 00:25:54.774124 end: 2.2 depthcharge-retry (duration 00:01:42) [common]
11012 00:25:54.774659 end: 2 depthcharge-action (duration 00:01:42) [common]
11013 00:25:54.775153 start: 3 lava-test-retry (timeout 00:01:00) [common]
11014 00:25:54.775649 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
11015 00:25:54.776069 Using namespace: common
11017 00:25:54.877286 / # #
11018 00:25:54.877932 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11019 00:25:54.883836 #
11020 00:25:54.884703 Using /lava-14479200
11022 00:25:54.985981 / # export SHELL=/bin/sh
11023 00:25:54.992990 export SHELL=/bin/sh
11025 00:25:55.094724 / # . /lava-14479200/environment
11026 00:25:55.101161 . /lava-14479200/environment
11028 00:25:55.210246 / # /lava-14479200/bin/lava-test-runner /lava-14479200/0
11029 00:25:55.210945 Test shell timeout: 10s (minimum of the action and connection timeout)
11030 00:25:55.216356 /lava-14479200/bin/lava-test-runner /lava-14479200/0
11031 00:25:55.501817 + export TESTRUN_ID=0_dmesg
11032 00:25:55.504686 + cd /lava-14479200/0/tests/0_dmesg
11033 00:25:55.508223 + cat uuid
11034 00:25:55.526532 + UUID=14479200_<8>[ 20.330965] <LAVA_SIGNAL_STARTRUN 0_dmesg 14479200_1.6.2.3.1>
11035 00:25:55.526991 1.6.2.3.1
11036 00:25:55.527335 + set +x
11037 00:25:55.527968 Received signal: <STARTRUN> 0_dmesg 14479200_1.6.2.3.1
11038 00:25:55.528336 Starting test lava.0_dmesg (14479200_1.6.2.3.1)
11039 00:25:55.528753 Skipping test definition patterns.
11040 00:25:55.533025 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
11041 00:25:55.680134 <8>[ 20.484898] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
11042 00:25:55.680897 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
11044 00:25:55.788544 <8>[ 20.593264] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
11045 00:25:55.789331 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
11047 00:25:55.886818 <8>[ 20.690826] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
11048 00:25:55.887628 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
11050 00:25:55.889288 + set +x
11051 00:25:55.893360 <8>[ 20.700264] <LAVA_SIGNAL_ENDRUN 0_dmesg 14479200_1.6.2.3.1>
11052 00:25:55.894139 Received signal: <ENDRUN> 0_dmesg 14479200_1.6.2.3.1
11053 00:25:55.894541 Ending use of test pattern.
11054 00:25:55.894908 Ending test lava.0_dmesg (14479200_1.6.2.3.1), duration 0.37
11056 00:25:55.899647 <LAVA_TEST_RUNNER EXIT>
11057 00:25:55.900508 ok: lava_test_shell seems to have completed
11058 00:25:55.901433 alert: pass
crit: pass
emerg: pass
11059 00:25:55.902085 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11060 00:25:55.902770 end: 3 lava-test-retry (duration 00:00:01) [common]
11061 00:25:55.903451 start: 4 finalize (timeout 00:07:52) [common]
11062 00:25:55.904102 start: 4.1 power-off (timeout 00:00:30) [common]
11063 00:25:55.905355 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-2', '--port=1', '--command=off']
11064 00:25:56.151545 >> Command sent successfully.
11065 00:25:56.159101 Returned 0 in 0 seconds
11066 00:25:56.260203 end: 4.1 power-off (duration 00:00:00) [common]
11068 00:25:56.261554 start: 4.2 read-feedback (timeout 00:07:52) [common]
11069 00:25:56.262805 Listened to connection for namespace 'common' for up to 1s
11070 00:25:57.263477 Finalising connection for namespace 'common'
11071 00:25:57.264145 Disconnecting from shell: Finalise
11072 00:25:57.264550 / #
11073 00:25:57.365270 end: 4.2 read-feedback (duration 00:00:01) [common]
11074 00:25:57.365478 end: 4 finalize (duration 00:00:01) [common]
11075 00:25:57.365595 Cleaning after the job
11076 00:25:57.365699 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14479200/tftp-deploy-krd9ty9v/ramdisk
11077 00:25:57.367841 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14479200/tftp-deploy-krd9ty9v/kernel
11078 00:25:57.378247 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14479200/tftp-deploy-krd9ty9v/dtb
11079 00:25:57.378420 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14479200/tftp-deploy-krd9ty9v/nfsrootfs
11080 00:25:57.436148 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14479200/tftp-deploy-krd9ty9v/modules
11081 00:25:57.441815 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14479200
11082 00:25:57.758103 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14479200
11083 00:25:57.758284 Job finished correctly