Boot log: mt8192-asurada-spherion-r0
- Errors: 1
- Kernel Errors: 20
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 22
1 00:21:04.583318 lava-dispatcher, installed at version: 2024.03
2 00:21:04.583535 start: 0 validate
3 00:21:04.583647 Start time: 2024-06-21 00:21:04.583642+00:00 (UTC)
4 00:21:04.583774 Using caching service: 'http://localhost/cache/?uri=%s'
5 00:21:04.583912 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-cros-ec%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 00:21:04.849245 Using caching service: 'http://localhost/cache/?uri=%s'
7 00:21:04.849966 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.94-cip23%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 00:21:18.612280 Using caching service: 'http://localhost/cache/?uri=%s'
9 00:21:18.613212 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.94-cip23%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 00:21:18.874015 Using caching service: 'http://localhost/cache/?uri=%s'
11 00:21:18.874745 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.94-cip23%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 00:21:22.128002 validate duration: 17.54
14 00:21:22.128316 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 00:21:22.128429 start: 1.1 download-retry (timeout 00:10:00) [common]
16 00:21:22.128528 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 00:21:22.128687 Not decompressing ramdisk as can be used compressed.
18 00:21:22.128846 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-cros-ec/20240313.0/arm64/rootfs.cpio.gz
19 00:21:22.128920 saving as /var/lib/lava/dispatcher/tmp/14479150/tftp-deploy-4y6o0n8e/ramdisk/rootfs.cpio.gz
20 00:21:22.129000 total size: 39026414 (37 MB)
21 00:21:22.385908 progress 0 % (0 MB)
22 00:21:22.395855 progress 5 % (1 MB)
23 00:21:22.405640 progress 10 % (3 MB)
24 00:21:22.415170 progress 15 % (5 MB)
25 00:21:22.424942 progress 20 % (7 MB)
26 00:21:22.434783 progress 25 % (9 MB)
27 00:21:22.444789 progress 30 % (11 MB)
28 00:21:22.454444 progress 35 % (13 MB)
29 00:21:22.464285 progress 40 % (14 MB)
30 00:21:22.474082 progress 45 % (16 MB)
31 00:21:22.483890 progress 50 % (18 MB)
32 00:21:22.493934 progress 55 % (20 MB)
33 00:21:22.503752 progress 60 % (22 MB)
34 00:21:22.513615 progress 65 % (24 MB)
35 00:21:22.523231 progress 70 % (26 MB)
36 00:21:22.532971 progress 75 % (27 MB)
37 00:21:22.542541 progress 80 % (29 MB)
38 00:21:22.552333 progress 85 % (31 MB)
39 00:21:22.562054 progress 90 % (33 MB)
40 00:21:22.571699 progress 95 % (35 MB)
41 00:21:22.581182 progress 100 % (37 MB)
42 00:21:22.581456 37 MB downloaded in 0.45 s (82.26 MB/s)
43 00:21:22.581629 end: 1.1.1 http-download (duration 00:00:00) [common]
45 00:21:22.581876 end: 1.1 download-retry (duration 00:00:00) [common]
46 00:21:22.581970 start: 1.2 download-retry (timeout 00:10:00) [common]
47 00:21:22.582060 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 00:21:22.582207 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.94-cip23/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 00:21:22.582273 saving as /var/lib/lava/dispatcher/tmp/14479150/tftp-deploy-4y6o0n8e/kernel/Image
50 00:21:22.582362 total size: 54813184 (52 MB)
51 00:21:22.582450 No compression specified
52 00:21:22.583853 progress 0 % (0 MB)
53 00:21:22.597755 progress 5 % (2 MB)
54 00:21:22.611521 progress 10 % (5 MB)
55 00:21:22.625054 progress 15 % (7 MB)
56 00:21:22.638646 progress 20 % (10 MB)
57 00:21:22.652242 progress 25 % (13 MB)
58 00:21:22.665776 progress 30 % (15 MB)
59 00:21:22.679468 progress 35 % (18 MB)
60 00:21:22.693063 progress 40 % (20 MB)
61 00:21:22.706726 progress 45 % (23 MB)
62 00:21:22.720496 progress 50 % (26 MB)
63 00:21:22.734147 progress 55 % (28 MB)
64 00:21:22.747581 progress 60 % (31 MB)
65 00:21:22.761303 progress 65 % (34 MB)
66 00:21:22.774763 progress 70 % (36 MB)
67 00:21:22.788451 progress 75 % (39 MB)
68 00:21:22.802264 progress 80 % (41 MB)
69 00:21:22.815825 progress 85 % (44 MB)
70 00:21:22.829475 progress 90 % (47 MB)
71 00:21:22.842950 progress 95 % (49 MB)
72 00:21:22.856142 progress 100 % (52 MB)
73 00:21:22.856395 52 MB downloaded in 0.27 s (190.76 MB/s)
74 00:21:22.856570 end: 1.2.1 http-download (duration 00:00:00) [common]
76 00:21:22.856885 end: 1.2 download-retry (duration 00:00:00) [common]
77 00:21:22.856980 start: 1.3 download-retry (timeout 00:09:59) [common]
78 00:21:22.857069 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 00:21:22.857211 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.94-cip23/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 00:21:22.857275 saving as /var/lib/lava/dispatcher/tmp/14479150/tftp-deploy-4y6o0n8e/dtb/mt8192-asurada-spherion-r0.dtb
81 00:21:22.857363 total size: 47258 (0 MB)
82 00:21:22.857452 No compression specified
83 00:21:22.858912 progress 69 % (0 MB)
84 00:21:22.859195 progress 100 % (0 MB)
85 00:21:22.859373 0 MB downloaded in 0.00 s (22.44 MB/s)
86 00:21:22.859501 end: 1.3.1 http-download (duration 00:00:00) [common]
88 00:21:22.859730 end: 1.3 download-retry (duration 00:00:00) [common]
89 00:21:22.859820 start: 1.4 download-retry (timeout 00:09:59) [common]
90 00:21:22.859910 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 00:21:22.860028 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.94-cip23/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 00:21:22.860117 saving as /var/lib/lava/dispatcher/tmp/14479150/tftp-deploy-4y6o0n8e/modules/modules.tar
93 00:21:22.860204 total size: 8618924 (8 MB)
94 00:21:22.860294 Using unxz to decompress xz
95 00:21:22.862017 progress 0 % (0 MB)
96 00:21:22.880971 progress 5 % (0 MB)
97 00:21:22.904604 progress 10 % (0 MB)
98 00:21:22.928940 progress 15 % (1 MB)
99 00:21:22.952840 progress 20 % (1 MB)
100 00:21:22.977194 progress 25 % (2 MB)
101 00:21:23.001295 progress 30 % (2 MB)
102 00:21:23.025926 progress 35 % (2 MB)
103 00:21:23.049618 progress 40 % (3 MB)
104 00:21:23.073334 progress 45 % (3 MB)
105 00:21:23.096578 progress 50 % (4 MB)
106 00:21:23.120531 progress 55 % (4 MB)
107 00:21:23.144482 progress 60 % (4 MB)
108 00:21:23.167507 progress 65 % (5 MB)
109 00:21:23.194287 progress 70 % (5 MB)
110 00:21:23.218470 progress 75 % (6 MB)
111 00:21:23.242788 progress 80 % (6 MB)
112 00:21:23.267892 progress 85 % (7 MB)
113 00:21:23.291102 progress 90 % (7 MB)
114 00:21:23.317500 progress 95 % (7 MB)
115 00:21:23.345410 progress 100 % (8 MB)
116 00:21:23.349821 8 MB downloaded in 0.49 s (16.79 MB/s)
117 00:21:23.349981 end: 1.4.1 http-download (duration 00:00:00) [common]
119 00:21:23.350194 end: 1.4 download-retry (duration 00:00:00) [common]
120 00:21:23.350276 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 00:21:23.350354 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 00:21:23.350424 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 00:21:23.350495 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 00:21:23.350662 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14479150/lava-overlay-rads08rs
125 00:21:23.350820 makedir: /var/lib/lava/dispatcher/tmp/14479150/lava-overlay-rads08rs/lava-14479150/bin
126 00:21:23.350911 makedir: /var/lib/lava/dispatcher/tmp/14479150/lava-overlay-rads08rs/lava-14479150/tests
127 00:21:23.350998 makedir: /var/lib/lava/dispatcher/tmp/14479150/lava-overlay-rads08rs/lava-14479150/results
128 00:21:23.351083 Creating /var/lib/lava/dispatcher/tmp/14479150/lava-overlay-rads08rs/lava-14479150/bin/lava-add-keys
129 00:21:23.351210 Creating /var/lib/lava/dispatcher/tmp/14479150/lava-overlay-rads08rs/lava-14479150/bin/lava-add-sources
130 00:21:23.351325 Creating /var/lib/lava/dispatcher/tmp/14479150/lava-overlay-rads08rs/lava-14479150/bin/lava-background-process-start
131 00:21:23.351439 Creating /var/lib/lava/dispatcher/tmp/14479150/lava-overlay-rads08rs/lava-14479150/bin/lava-background-process-stop
132 00:21:23.351563 Creating /var/lib/lava/dispatcher/tmp/14479150/lava-overlay-rads08rs/lava-14479150/bin/lava-common-functions
133 00:21:23.351678 Creating /var/lib/lava/dispatcher/tmp/14479150/lava-overlay-rads08rs/lava-14479150/bin/lava-echo-ipv4
134 00:21:23.351790 Creating /var/lib/lava/dispatcher/tmp/14479150/lava-overlay-rads08rs/lava-14479150/bin/lava-install-packages
135 00:21:23.351901 Creating /var/lib/lava/dispatcher/tmp/14479150/lava-overlay-rads08rs/lava-14479150/bin/lava-installed-packages
136 00:21:23.352011 Creating /var/lib/lava/dispatcher/tmp/14479150/lava-overlay-rads08rs/lava-14479150/bin/lava-os-build
137 00:21:23.352123 Creating /var/lib/lava/dispatcher/tmp/14479150/lava-overlay-rads08rs/lava-14479150/bin/lava-probe-channel
138 00:21:23.352234 Creating /var/lib/lava/dispatcher/tmp/14479150/lava-overlay-rads08rs/lava-14479150/bin/lava-probe-ip
139 00:21:23.352345 Creating /var/lib/lava/dispatcher/tmp/14479150/lava-overlay-rads08rs/lava-14479150/bin/lava-target-ip
140 00:21:23.352457 Creating /var/lib/lava/dispatcher/tmp/14479150/lava-overlay-rads08rs/lava-14479150/bin/lava-target-mac
141 00:21:23.352566 Creating /var/lib/lava/dispatcher/tmp/14479150/lava-overlay-rads08rs/lava-14479150/bin/lava-target-storage
142 00:21:23.352681 Creating /var/lib/lava/dispatcher/tmp/14479150/lava-overlay-rads08rs/lava-14479150/bin/lava-test-case
143 00:21:23.352840 Creating /var/lib/lava/dispatcher/tmp/14479150/lava-overlay-rads08rs/lava-14479150/bin/lava-test-event
144 00:21:23.352949 Creating /var/lib/lava/dispatcher/tmp/14479150/lava-overlay-rads08rs/lava-14479150/bin/lava-test-feedback
145 00:21:23.353060 Creating /var/lib/lava/dispatcher/tmp/14479150/lava-overlay-rads08rs/lava-14479150/bin/lava-test-raise
146 00:21:23.353174 Creating /var/lib/lava/dispatcher/tmp/14479150/lava-overlay-rads08rs/lava-14479150/bin/lava-test-reference
147 00:21:23.353284 Creating /var/lib/lava/dispatcher/tmp/14479150/lava-overlay-rads08rs/lava-14479150/bin/lava-test-runner
148 00:21:23.353394 Creating /var/lib/lava/dispatcher/tmp/14479150/lava-overlay-rads08rs/lava-14479150/bin/lava-test-set
149 00:21:23.353502 Creating /var/lib/lava/dispatcher/tmp/14479150/lava-overlay-rads08rs/lava-14479150/bin/lava-test-shell
150 00:21:23.353613 Updating /var/lib/lava/dispatcher/tmp/14479150/lava-overlay-rads08rs/lava-14479150/bin/lava-install-packages (oe)
151 00:21:23.353750 Updating /var/lib/lava/dispatcher/tmp/14479150/lava-overlay-rads08rs/lava-14479150/bin/lava-installed-packages (oe)
152 00:21:23.353859 Creating /var/lib/lava/dispatcher/tmp/14479150/lava-overlay-rads08rs/lava-14479150/environment
153 00:21:23.353943 LAVA metadata
154 00:21:23.354008 - LAVA_JOB_ID=14479150
155 00:21:23.354064 - LAVA_DISPATCHER_IP=192.168.201.1
156 00:21:23.354153 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 00:21:23.354209 skipped lava-vland-overlay
158 00:21:23.354275 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 00:21:23.354346 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 00:21:23.354399 skipped lava-multinode-overlay
161 00:21:23.354464 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 00:21:23.354534 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 00:21:23.354595 Loading test definitions
164 00:21:23.354670 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 00:21:23.354753 Using /lava-14479150 at stage 0
166 00:21:23.355058 uuid=14479150_1.5.2.3.1 testdef=None
167 00:21:23.355139 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 00:21:23.355215 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 00:21:23.355642 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 00:21:23.355844 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 00:21:23.356384 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 00:21:23.356593 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 00:21:23.357973 runner path: /var/lib/lava/dispatcher/tmp/14479150/lava-overlay-rads08rs/lava-14479150/0/tests/0_cros-ec test_uuid 14479150_1.5.2.3.1
176 00:21:23.358118 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 00:21:23.358306 Creating lava-test-runner.conf files
179 00:21:23.358362 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14479150/lava-overlay-rads08rs/lava-14479150/0 for stage 0
180 00:21:23.358443 - 0_cros-ec
181 00:21:23.358533 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 00:21:23.358610 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 00:21:23.364667 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 00:21:23.364809 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 00:21:23.364888 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 00:21:23.364965 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 00:21:23.365040 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 00:21:24.560944 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 00:21:24.561090 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 00:21:24.561168 extracting modules file /var/lib/lava/dispatcher/tmp/14479150/tftp-deploy-4y6o0n8e/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14479150/extract-overlay-ramdisk-98vgz185/ramdisk
191 00:21:24.796125 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 00:21:24.796273 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 00:21:24.796353 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14479150/compress-overlay-zpzav6l1/overlay-1.5.2.4.tar.gz to ramdisk
194 00:21:24.796415 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14479150/compress-overlay-zpzav6l1/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14479150/extract-overlay-ramdisk-98vgz185/ramdisk
195 00:21:24.804063 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 00:21:24.804162 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 00:21:24.804241 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 00:21:24.804324 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 00:21:24.804390 Building ramdisk /var/lib/lava/dispatcher/tmp/14479150/extract-overlay-ramdisk-98vgz185/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14479150/extract-overlay-ramdisk-98vgz185/ramdisk
200 00:21:25.670121 >> 336023 blocks
201 00:21:30.891007 rename /var/lib/lava/dispatcher/tmp/14479150/extract-overlay-ramdisk-98vgz185/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14479150/tftp-deploy-4y6o0n8e/ramdisk/ramdisk.cpio.gz
202 00:21:30.891179 end: 1.5.7 compress-ramdisk (duration 00:00:06) [common]
203 00:21:30.891267 start: 1.5.8 prepare-kernel (timeout 00:09:51) [common]
204 00:21:30.891351 start: 1.5.8.1 prepare-fit (timeout 00:09:51) [common]
205 00:21:30.891430 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14479150/tftp-deploy-4y6o0n8e/kernel/Image']
206 00:21:44.095892 Returned 0 in 13 seconds
207 00:21:44.196391 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14479150/tftp-deploy-4y6o0n8e/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14479150/tftp-deploy-4y6o0n8e/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14479150/tftp-deploy-4y6o0n8e/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14479150/tftp-deploy-4y6o0n8e/kernel/image.itb
208 00:21:44.986530 output: FIT description: Kernel Image image with one or more FDT blobs
209 00:21:44.986669 output: Created: Fri Jun 21 01:21:44 2024
210 00:21:44.986760 output: Image 0 (kernel-1)
211 00:21:44.986833 output: Description:
212 00:21:44.986905 output: Created: Fri Jun 21 01:21:44 2024
213 00:21:44.986979 output: Type: Kernel Image
214 00:21:44.987069 output: Compression: lzma compressed
215 00:21:44.987168 output: Data Size: 13124896 Bytes = 12817.28 KiB = 12.52 MiB
216 00:21:44.987260 output: Architecture: AArch64
217 00:21:44.987351 output: OS: Linux
218 00:21:44.987441 output: Load Address: 0x00000000
219 00:21:44.987536 output: Entry Point: 0x00000000
220 00:21:44.987631 output: Hash algo: crc32
221 00:21:44.987721 output: Hash value: ab2f7826
222 00:21:44.987811 output: Image 1 (fdt-1)
223 00:21:44.987899 output: Description: mt8192-asurada-spherion-r0
224 00:21:44.987991 output: Created: Fri Jun 21 01:21:44 2024
225 00:21:44.988077 output: Type: Flat Device Tree
226 00:21:44.988162 output: Compression: uncompressed
227 00:21:44.988249 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 00:21:44.988334 output: Architecture: AArch64
229 00:21:44.988419 output: Hash algo: crc32
230 00:21:44.988501 output: Hash value: 0f8e4d2e
231 00:21:44.988584 output: Image 2 (ramdisk-1)
232 00:21:44.988667 output: Description: unavailable
233 00:21:44.988756 output: Created: Fri Jun 21 01:21:44 2024
234 00:21:44.988839 output: Type: RAMDisk Image
235 00:21:44.988921 output: Compression: uncompressed
236 00:21:44.989003 output: Data Size: 52149824 Bytes = 50927.56 KiB = 49.73 MiB
237 00:21:44.989086 output: Architecture: AArch64
238 00:21:44.989168 output: OS: Linux
239 00:21:44.989250 output: Load Address: unavailable
240 00:21:44.989332 output: Entry Point: unavailable
241 00:21:44.989415 output: Hash algo: crc32
242 00:21:44.989498 output: Hash value: cc9f6fa2
243 00:21:44.989581 output: Default Configuration: 'conf-1'
244 00:21:44.989663 output: Configuration 0 (conf-1)
245 00:21:44.989745 output: Description: mt8192-asurada-spherion-r0
246 00:21:44.989828 output: Kernel: kernel-1
247 00:21:44.989910 output: Init Ramdisk: ramdisk-1
248 00:21:44.989993 output: FDT: fdt-1
249 00:21:44.990076 output: Loadables: kernel-1
250 00:21:44.990158 output:
251 00:21:44.990339 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 00:21:44.990458 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 00:21:44.990583 end: 1.5 prepare-tftp-overlay (duration 00:00:22) [common]
254 00:21:44.990702 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:37) [common]
255 00:21:44.990800 No LXC device requested
256 00:21:44.990912 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 00:21:44.991025 start: 1.7 deploy-device-env (timeout 00:09:37) [common]
258 00:21:44.991131 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 00:21:44.991225 Checking files for TFTP limit of 4294967296 bytes.
260 00:21:44.991820 end: 1 tftp-deploy (duration 00:00:23) [common]
261 00:21:44.991949 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 00:21:44.992068 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 00:21:44.992224 substitutions:
264 00:21:44.992313 - {DTB}: 14479150/tftp-deploy-4y6o0n8e/dtb/mt8192-asurada-spherion-r0.dtb
265 00:21:44.992407 - {INITRD}: 14479150/tftp-deploy-4y6o0n8e/ramdisk/ramdisk.cpio.gz
266 00:21:44.992495 - {KERNEL}: 14479150/tftp-deploy-4y6o0n8e/kernel/Image
267 00:21:44.992582 - {LAVA_MAC}: None
268 00:21:44.992668 - {PRESEED_CONFIG}: None
269 00:21:44.992764 - {PRESEED_LOCAL}: None
270 00:21:44.992850 - {RAMDISK}: 14479150/tftp-deploy-4y6o0n8e/ramdisk/ramdisk.cpio.gz
271 00:21:44.992945 - {ROOT_PART}: None
272 00:21:44.993029 - {ROOT}: None
273 00:21:44.993113 - {SERVER_IP}: 192.168.201.1
274 00:21:44.993197 - {TEE}: None
275 00:21:44.993281 Parsed boot commands:
276 00:21:44.993366 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 00:21:44.993565 Parsed boot commands: tftpboot 192.168.201.1 14479150/tftp-deploy-4y6o0n8e/kernel/image.itb 14479150/tftp-deploy-4y6o0n8e/kernel/cmdline
278 00:21:44.993677 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 00:21:44.993788 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 00:21:44.993903 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 00:21:44.994014 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 00:21:44.994107 Not connected, no need to disconnect.
283 00:21:44.994212 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 00:21:44.994319 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 00:21:44.994413 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-1'
286 00:21:44.997816 Setting prompt string to ['lava-test: # ']
287 00:21:44.998168 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 00:21:44.998274 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 00:21:44.998382 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 00:21:44.998478 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 00:21:44.998668 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-1', '--port=1', '--command=reboot']
292 00:21:54.170663 >> Command sent successfully.
293 00:21:54.173722 Returned 0 in 9 seconds
294 00:21:54.274090 end: 2.2.2.1 pdu-reboot (duration 00:00:09) [common]
296 00:21:54.274378 end: 2.2.2 reset-device (duration 00:00:09) [common]
297 00:21:54.274471 start: 2.2.3 depthcharge-start (timeout 00:04:51) [common]
298 00:21:54.274555 Setting prompt string to 'Starting depthcharge on Spherion...'
299 00:21:54.274612 Changing prompt to 'Starting depthcharge on Spherion...'
300 00:21:54.274670 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 00:21:54.275009 [Enter `^Ec?' for help]
302 00:21:55.362298
303 00:21:55.362436
304 00:21:55.362501 F0: 102B 0000
305 00:21:55.362559
306 00:21:55.362615 F3: 1001 0000 [0200]
307 00:21:55.365408
308 00:21:55.365487 F3: 1001 0000
309 00:21:55.365549
310 00:21:55.365603 F7: 102D 0000
311 00:21:55.365659
312 00:21:55.368900 F1: 0000 0000
313 00:21:55.368980
314 00:21:55.369040 V0: 0000 0000 [0001]
315 00:21:55.369097
316 00:21:55.372312 00: 0007 8000
317 00:21:55.372391
318 00:21:55.372448 01: 0000 0000
319 00:21:55.372504
320 00:21:55.375732 BP: 0C00 0209 [0000]
321 00:21:55.375807
322 00:21:55.375864 G0: 1182 0000
323 00:21:55.375918
324 00:21:55.378750 EC: 0000 0021 [4000]
325 00:21:55.378825
326 00:21:55.378881 S7: 0000 0000 [0000]
327 00:21:55.378934
328 00:21:55.382380 CC: 0000 0000 [0001]
329 00:21:55.382457
330 00:21:55.382515 T0: 0000 0040 [010F]
331 00:21:55.382568
332 00:21:55.385575 Jump to BL
333 00:21:55.385649
334 00:21:55.409069
335 00:21:55.409153
336 00:21:55.418655 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
337 00:21:55.422065 ARM64: Exception handlers installed.
338 00:21:55.422140 ARM64: Testing exception
339 00:21:55.425470 ARM64: Done test exception
340 00:21:55.432024 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
341 00:21:55.442622 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
342 00:21:55.449247 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
343 00:21:55.459827 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
344 00:21:55.466467 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
345 00:21:55.476806 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
346 00:21:55.486794 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
347 00:21:55.493617 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
348 00:21:55.512105 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
349 00:21:55.515267 WDT: Last reset was cold boot
350 00:21:55.519084 SPI1(PAD0) initialized at 2873684 Hz
351 00:21:55.522299 SPI5(PAD0) initialized at 992727 Hz
352 00:21:55.526269 VBOOT: Loading verstage.
353 00:21:55.529589 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
354 00:21:55.533515 FMAP: Found "FLASH" version 1.1 at 0x20000.
355 00:21:55.540666 FMAP: base = 0x0 size = 0x800000 #areas = 25
356 00:21:55.544201 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
357 00:21:55.551460 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
358 00:21:55.558273 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
359 00:21:55.567810 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
360 00:21:55.567894
361 00:21:55.567955
362 00:21:55.578492 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
363 00:21:55.582244 ARM64: Exception handlers installed.
364 00:21:55.582322 ARM64: Testing exception
365 00:21:55.585850 ARM64: Done test exception
366 00:21:55.589538 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
367 00:21:55.592957 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
368 00:21:55.608754 Probing TPM: . done!
369 00:21:55.608846 TPM ready after 0 ms
370 00:21:55.613312 Connected to device vid:did:rid of 1ae0:0028:00
371 00:21:55.684971 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
372 00:21:55.685104 Initialized TPM device CR50 revision 0
373 00:21:55.700600 tlcl_send_startup: Startup return code is 0
374 00:21:55.700734 TPM: setup succeeded
375 00:21:55.712547 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
376 00:21:55.722848 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
377 00:21:55.734457 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
378 00:21:55.744197 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
379 00:21:55.748056 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
380 00:21:55.752289 in-header: 03 07 00 00 08 00 00 00
381 00:21:55.756430 in-data: aa e4 47 04 13 02 00 00
382 00:21:55.756508 Chrome EC: UHEPI supported
383 00:21:55.763511 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
384 00:21:55.767399 in-header: 03 a9 00 00 08 00 00 00
385 00:21:55.771332 in-data: 84 60 60 08 00 00 00 00
386 00:21:55.771448 Phase 1
387 00:21:55.775273 FMAP: area GBB found @ 3f5000 (12032 bytes)
388 00:21:55.782300 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
389 00:21:55.785808 VB2:vb2_check_recovery() Recovery was requested manually
390 00:21:55.793272 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
391 00:21:55.793352 Recovery requested (1009000e)
392 00:21:55.806139 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 00:21:55.809888 tlcl_extend: response is 0
394 00:21:55.820396 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 00:21:55.824044 tlcl_extend: response is 0
396 00:21:55.831083 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 00:21:55.851476 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
398 00:21:55.858805 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 00:21:55.858884
400 00:21:55.858943
401 00:21:55.868822 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 00:21:55.872164 ARM64: Exception handlers installed.
403 00:21:55.872241 ARM64: Testing exception
404 00:21:55.875548 ARM64: Done test exception
405 00:21:55.896344 pmic_efuse_setting: Set efuses in 11 msecs
406 00:21:55.899700 pmwrap_interface_init: Select PMIF_VLD_RDY
407 00:21:55.906675 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 00:21:55.909959 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 00:21:55.916721 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 00:21:55.920579 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 00:21:55.923564 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 00:21:55.930107 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 00:21:55.933282 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 00:21:55.940299 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 00:21:55.943435 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 00:21:55.950279 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 00:21:55.953446 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 00:21:55.956606 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 00:21:55.963237 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 00:21:55.970300 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 00:21:55.973604 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 00:21:55.980413 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 00:21:55.987140 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 00:21:55.990556 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 00:21:55.997359 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 00:21:56.003923 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 00:21:56.007233 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 00:21:56.013937 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 00:21:56.020518 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 00:21:56.023904 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 00:21:56.030770 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 00:21:56.037234 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 00:21:56.040257 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 00:21:56.047384 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 00:21:56.050730 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 00:21:56.054198 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 00:21:56.061196 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 00:21:56.064610 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 00:21:56.071371 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 00:21:56.074684 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 00:21:56.081611 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 00:21:56.084985 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 00:21:56.091241 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 00:21:56.094590 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 00:21:56.101278 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 00:21:56.104562 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 00:21:56.108269 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 00:21:56.111304 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 00:21:56.118056 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 00:21:56.121443 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 00:21:56.124681 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 00:21:56.131402 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 00:21:56.134817 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 00:21:56.138233 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 00:21:56.144813 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 00:21:56.148345 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 00:21:56.151493 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 00:21:56.158055 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
459 00:21:56.168288 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 00:21:56.171609 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 00:21:56.181926 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 00:21:56.188259 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 00:21:56.195087 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 00:21:56.198606 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 00:21:56.201859 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 00:21:56.209045 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x27
467 00:21:56.215815 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 00:21:56.219175 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 00:21:56.222431 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 00:21:56.233845 [RTC]rtc_get_frequency_meter,154: input=15, output=774
471 00:21:56.243053 [RTC]rtc_get_frequency_meter,154: input=23, output=957
472 00:21:56.252804 [RTC]rtc_get_frequency_meter,154: input=19, output=865
473 00:21:56.262600 [RTC]rtc_get_frequency_meter,154: input=17, output=818
474 00:21:56.271794 [RTC]rtc_get_frequency_meter,154: input=16, output=797
475 00:21:56.281491 [RTC]rtc_get_frequency_meter,154: input=15, output=774
476 00:21:56.290931 [RTC]rtc_get_frequency_meter,154: input=16, output=794
477 00:21:56.294350 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
478 00:21:56.301164 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
479 00:21:56.304639 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 00:21:56.308351 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
481 00:21:56.314810 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 00:21:56.318130 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
483 00:21:56.321571 ADC[4]: Raw value=903245 ID=7
484 00:21:56.321648 ADC[3]: Raw value=213179 ID=1
485 00:21:56.324734 RAM Code: 0x71
486 00:21:56.328104 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 00:21:56.334780 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 00:21:56.341549 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 00:21:56.348269 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 00:21:56.351609 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 00:21:56.354566 in-header: 03 07 00 00 08 00 00 00
492 00:21:56.358387 in-data: aa e4 47 04 13 02 00 00
493 00:21:56.361587 Chrome EC: UHEPI supported
494 00:21:56.368462 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 00:21:56.371722 in-header: 03 a9 00 00 08 00 00 00
496 00:21:56.375012 in-data: 84 60 60 08 00 00 00 00
497 00:21:56.378212 MRC: failed to locate region type 0.
498 00:21:56.384915 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 00:21:56.388401 DRAM-K: Running full calibration
500 00:21:56.395155 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 00:21:56.395235 header.status = 0x0
502 00:21:56.398503 header.version = 0x6 (expected: 0x6)
503 00:21:56.401770 header.size = 0xd00 (expected: 0xd00)
504 00:21:56.404946 header.flags = 0x0
505 00:21:56.411590 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 00:21:56.428307 read SPI 0x72590 0x1c583: 12500 us, 9287 KB/s, 74.296 Mbps
507 00:21:56.435459 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 00:21:56.438742 dram_init: ddr_geometry: 2
509 00:21:56.442069 [EMI] MDL number = 2
510 00:21:56.442147 [EMI] Get MDL freq = 0
511 00:21:56.445421 dram_init: ddr_type: 0
512 00:21:56.445499 is_discrete_lpddr4: 1
513 00:21:56.448372 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 00:21:56.448449
515 00:21:56.448508
516 00:21:56.451762 [Bian_co] ETT version 0.0.0.1
517 00:21:56.458431 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 00:21:56.458509
519 00:21:56.461722 dramc_set_vcore_voltage set vcore to 650000
520 00:21:56.461800 Read voltage for 800, 4
521 00:21:56.465065 Vio18 = 0
522 00:21:56.465143 Vcore = 650000
523 00:21:56.465204 Vdram = 0
524 00:21:56.468359 Vddq = 0
525 00:21:56.468459 Vmddr = 0
526 00:21:56.471820 dram_init: config_dvfs: 1
527 00:21:56.475413 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 00:21:56.482158 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 00:21:56.485072 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=9
530 00:21:56.488496 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=9
531 00:21:56.491851 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
532 00:21:56.495041 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
533 00:21:56.498576 MEM_TYPE=3, freq_sel=18
534 00:21:56.501863 sv_algorithm_assistance_LP4_1600
535 00:21:56.505081 ============ PULL DRAM RESETB DOWN ============
536 00:21:56.508978 ========== PULL DRAM RESETB DOWN end =========
537 00:21:56.515238 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 00:21:56.518568 ===================================
539 00:21:56.522371 LPDDR4 DRAM CONFIGURATION
540 00:21:56.522448 ===================================
541 00:21:56.525410 EX_ROW_EN[0] = 0x0
542 00:21:56.528535 EX_ROW_EN[1] = 0x0
543 00:21:56.528612 LP4Y_EN = 0x0
544 00:21:56.531927 WORK_FSP = 0x0
545 00:21:56.532004 WL = 0x2
546 00:21:56.535226 RL = 0x2
547 00:21:56.535303 BL = 0x2
548 00:21:56.538758 RPST = 0x0
549 00:21:56.538836 RD_PRE = 0x0
550 00:21:56.542186 WR_PRE = 0x1
551 00:21:56.542262 WR_PST = 0x0
552 00:21:56.545546 DBI_WR = 0x0
553 00:21:56.545624 DBI_RD = 0x0
554 00:21:56.549018 OTF = 0x1
555 00:21:56.552492 ===================================
556 00:21:56.555853 ===================================
557 00:21:56.555931 ANA top config
558 00:21:56.558769 ===================================
559 00:21:56.562110 DLL_ASYNC_EN = 0
560 00:21:56.565573 ALL_SLAVE_EN = 1
561 00:21:56.565651 NEW_RANK_MODE = 1
562 00:21:56.568871 DLL_IDLE_MODE = 1
563 00:21:56.572644 LP45_APHY_COMB_EN = 1
564 00:21:56.575910 TX_ODT_DIS = 1
565 00:21:56.579255 NEW_8X_MODE = 1
566 00:21:56.582660 ===================================
567 00:21:56.582739 ===================================
568 00:21:56.585695 data_rate = 1600
569 00:21:56.589264 CKR = 1
570 00:21:56.592746 DQ_P2S_RATIO = 8
571 00:21:56.596046 ===================================
572 00:21:56.599363 CA_P2S_RATIO = 8
573 00:21:56.602746 DQ_CA_OPEN = 0
574 00:21:56.602821 DQ_SEMI_OPEN = 0
575 00:21:56.606063 CA_SEMI_OPEN = 0
576 00:21:56.609146 CA_FULL_RATE = 0
577 00:21:56.612619 DQ_CKDIV4_EN = 1
578 00:21:56.616105 CA_CKDIV4_EN = 1
579 00:21:56.619353 CA_PREDIV_EN = 0
580 00:21:56.619445 PH8_DLY = 0
581 00:21:56.622753 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 00:21:56.626296 DQ_AAMCK_DIV = 4
583 00:21:56.629655 CA_AAMCK_DIV = 4
584 00:21:56.632798 CA_ADMCK_DIV = 4
585 00:21:56.636135 DQ_TRACK_CA_EN = 0
586 00:21:56.636212 CA_PICK = 800
587 00:21:56.639142 CA_MCKIO = 800
588 00:21:56.642830 MCKIO_SEMI = 0
589 00:21:56.646259 PLL_FREQ = 3068
590 00:21:56.649436 DQ_UI_PI_RATIO = 32
591 00:21:56.652838 CA_UI_PI_RATIO = 0
592 00:21:56.656029 ===================================
593 00:21:56.659430 ===================================
594 00:21:56.659507 memory_type:LPDDR4
595 00:21:56.662944 GP_NUM : 10
596 00:21:56.666147 SRAM_EN : 1
597 00:21:56.666223 MD32_EN : 0
598 00:21:56.669515 ===================================
599 00:21:56.672929 [ANA_INIT] >>>>>>>>>>>>>>
600 00:21:56.676280 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 00:21:56.679680 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 00:21:56.682917 ===================================
603 00:21:56.686292 data_rate = 1600,PCW = 0X7600
604 00:21:56.689579 ===================================
605 00:21:56.693135 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 00:21:56.696219 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 00:21:56.702904 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 00:21:56.706264 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 00:21:56.709725 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 00:21:56.713023 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 00:21:56.716440 [ANA_INIT] flow start
612 00:21:56.719781 [ANA_INIT] PLL >>>>>>>>
613 00:21:56.719858 [ANA_INIT] PLL <<<<<<<<
614 00:21:56.722855 [ANA_INIT] MIDPI >>>>>>>>
615 00:21:56.726172 [ANA_INIT] MIDPI <<<<<<<<
616 00:21:56.726249 [ANA_INIT] DLL >>>>>>>>
617 00:21:56.729757 [ANA_INIT] flow end
618 00:21:56.732736 ============ LP4 DIFF to SE enter ============
619 00:21:56.736142 ============ LP4 DIFF to SE exit ============
620 00:21:56.739829 [ANA_INIT] <<<<<<<<<<<<<
621 00:21:56.742679 [Flow] Enable top DCM control >>>>>
622 00:21:56.746410 [Flow] Enable top DCM control <<<<<
623 00:21:56.749505 Enable DLL master slave shuffle
624 00:21:56.756221 ==============================================================
625 00:21:56.756300 Gating Mode config
626 00:21:56.762807 ==============================================================
627 00:21:56.762889 Config description:
628 00:21:56.773052 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 00:21:56.779704 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 00:21:56.786505 SELPH_MODE 0: By rank 1: By Phase
631 00:21:56.789899 ==============================================================
632 00:21:56.793198 GAT_TRACK_EN = 1
633 00:21:56.796495 RX_GATING_MODE = 2
634 00:21:56.799693 RX_GATING_TRACK_MODE = 2
635 00:21:56.803240 SELPH_MODE = 1
636 00:21:56.806810 PICG_EARLY_EN = 1
637 00:21:56.809788 VALID_LAT_VALUE = 1
638 00:21:56.816377 ==============================================================
639 00:21:56.819746 Enter into Gating configuration >>>>
640 00:21:56.819853 Exit from Gating configuration <<<<
641 00:21:56.823185 Enter into DVFS_PRE_config >>>>>
642 00:21:56.836273 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 00:21:56.839554 Exit from DVFS_PRE_config <<<<<
644 00:21:56.843310 Enter into PICG configuration >>>>
645 00:21:56.843412 Exit from PICG configuration <<<<
646 00:21:56.846706 [RX_INPUT] configuration >>>>>
647 00:21:56.850045 [RX_INPUT] configuration <<<<<
648 00:21:56.856683 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 00:21:56.859726 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 00:21:56.866742 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 00:21:56.873227 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 00:21:56.879968 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 00:21:56.886802 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 00:21:56.889804 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 00:21:56.893332 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 00:21:56.896513 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 00:21:56.903286 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 00:21:56.906445 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 00:21:56.910048 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 00:21:56.913750 ===================================
661 00:21:56.917422 LPDDR4 DRAM CONFIGURATION
662 00:21:56.921339 ===================================
663 00:21:56.921417 EX_ROW_EN[0] = 0x0
664 00:21:56.924700 EX_ROW_EN[1] = 0x0
665 00:21:56.924793 LP4Y_EN = 0x0
666 00:21:56.928745 WORK_FSP = 0x0
667 00:21:56.928821 WL = 0x2
668 00:21:56.931998 RL = 0x2
669 00:21:56.932075 BL = 0x2
670 00:21:56.935916 RPST = 0x0
671 00:21:56.935994 RD_PRE = 0x0
672 00:21:56.936053 WR_PRE = 0x1
673 00:21:56.939729 WR_PST = 0x0
674 00:21:56.939807 DBI_WR = 0x0
675 00:21:56.942926 DBI_RD = 0x0
676 00:21:56.943003 OTF = 0x1
677 00:21:56.946943 ===================================
678 00:21:56.950154 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 00:21:56.957144 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 00:21:56.960460 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 00:21:56.963592 ===================================
682 00:21:56.967008 LPDDR4 DRAM CONFIGURATION
683 00:21:56.970273 ===================================
684 00:21:56.970351 EX_ROW_EN[0] = 0x10
685 00:21:56.973866 EX_ROW_EN[1] = 0x0
686 00:21:56.973943 LP4Y_EN = 0x0
687 00:21:56.976944 WORK_FSP = 0x0
688 00:21:56.977021 WL = 0x2
689 00:21:56.980667 RL = 0x2
690 00:21:56.980782 BL = 0x2
691 00:21:56.984009 RPST = 0x0
692 00:21:56.984086 RD_PRE = 0x0
693 00:21:56.987226 WR_PRE = 0x1
694 00:21:56.987304 WR_PST = 0x0
695 00:21:56.990721 DBI_WR = 0x0
696 00:21:56.990798 DBI_RD = 0x0
697 00:21:56.993711 OTF = 0x1
698 00:21:56.997456 ===================================
699 00:21:57.004228 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 00:21:57.006963 nWR fixed to 40
701 00:21:57.010323 [ModeRegInit_LP4] CH0 RK0
702 00:21:57.010401 [ModeRegInit_LP4] CH0 RK1
703 00:21:57.013797 [ModeRegInit_LP4] CH1 RK0
704 00:21:57.017014 [ModeRegInit_LP4] CH1 RK1
705 00:21:57.017091 match AC timing 13
706 00:21:57.023767 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 00:21:57.027219 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 00:21:57.030607 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 00:21:57.037334 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 00:21:57.040837 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 00:21:57.040915 [EMI DOE] emi_dcm 0
712 00:21:57.047173 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 00:21:57.047251 ==
714 00:21:57.050768 Dram Type= 6, Freq= 0, CH_0, rank 0
715 00:21:57.054198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 00:21:57.054276 ==
717 00:21:57.060691 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 00:21:57.064387 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 00:21:57.074798 [CA 0] Center 38 (7~69) winsize 63
720 00:21:57.077966 [CA 1] Center 38 (7~69) winsize 63
721 00:21:57.081420 [CA 2] Center 35 (5~66) winsize 62
722 00:21:57.084576 [CA 3] Center 35 (5~66) winsize 62
723 00:21:57.088273 [CA 4] Center 35 (4~66) winsize 63
724 00:21:57.091594 [CA 5] Center 33 (3~64) winsize 62
725 00:21:57.091670
726 00:21:57.094930 [CmdBusTrainingLP45] Vref(ca) range 1: 32
727 00:21:57.095006
728 00:21:57.098325 [CATrainingPosCal] consider 1 rank data
729 00:21:57.101349 u2DelayCellTimex100 = 270/100 ps
730 00:21:57.104790 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
731 00:21:57.107976 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
732 00:21:57.114833 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
733 00:21:57.118275 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
734 00:21:57.121707 CA4 delay=35 (4~66),Diff = 2 PI (14 cell)
735 00:21:57.124911 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
736 00:21:57.124988
737 00:21:57.127859 CA PerBit enable=1, Macro0, CA PI delay=33
738 00:21:57.127936
739 00:21:57.131380 [CBTSetCACLKResult] CA Dly = 33
740 00:21:57.131457 CS Dly: 5 (0~36)
741 00:21:57.134621 ==
742 00:21:57.134698 Dram Type= 6, Freq= 0, CH_0, rank 1
743 00:21:57.141319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 00:21:57.141397 ==
745 00:21:57.144603 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 00:21:57.151267 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 00:21:57.161195 [CA 0] Center 38 (7~69) winsize 63
748 00:21:57.164534 [CA 1] Center 38 (7~69) winsize 63
749 00:21:57.167706 [CA 2] Center 36 (5~67) winsize 63
750 00:21:57.171495 [CA 3] Center 36 (5~67) winsize 63
751 00:21:57.174670 [CA 4] Center 35 (4~66) winsize 63
752 00:21:57.177981 [CA 5] Center 34 (4~65) winsize 62
753 00:21:57.178058
754 00:21:57.181207 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 00:21:57.181283
756 00:21:57.184867 [CATrainingPosCal] consider 2 rank data
757 00:21:57.188246 u2DelayCellTimex100 = 270/100 ps
758 00:21:57.191559 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
759 00:21:57.194696 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
760 00:21:57.198141 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
761 00:21:57.204677 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
762 00:21:57.208067 CA4 delay=35 (4~66),Diff = 1 PI (7 cell)
763 00:21:57.211306 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
764 00:21:57.211383
765 00:21:57.214798 CA PerBit enable=1, Macro0, CA PI delay=34
766 00:21:57.214875
767 00:21:57.218113 [CBTSetCACLKResult] CA Dly = 34
768 00:21:57.218214 CS Dly: 6 (0~38)
769 00:21:57.218302
770 00:21:57.221477 ----->DramcWriteLeveling(PI) begin...
771 00:21:57.221556 ==
772 00:21:57.224898 Dram Type= 6, Freq= 0, CH_0, rank 0
773 00:21:57.231602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 00:21:57.231680 ==
775 00:21:57.234797 Write leveling (Byte 0): 30 => 30
776 00:21:57.238037 Write leveling (Byte 1): 30 => 30
777 00:21:57.238114 DramcWriteLeveling(PI) end<-----
778 00:21:57.238173
779 00:21:57.241397 ==
780 00:21:57.244694 Dram Type= 6, Freq= 0, CH_0, rank 0
781 00:21:57.248458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 00:21:57.248535 ==
783 00:21:57.251409 [Gating] SW mode calibration
784 00:21:57.258000 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 00:21:57.261383 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 00:21:57.268381 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
787 00:21:57.271344 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
788 00:21:57.274746 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 00:21:57.281489 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 00:21:57.284837 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 00:21:57.288113 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 00:21:57.294892 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 00:21:57.298168 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 00:21:57.301578 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 00:21:57.304640 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 00:21:57.311421 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 00:21:57.315003 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 00:21:57.318214 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 00:21:57.325038 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 00:21:57.328433 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 00:21:57.331409 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 00:21:57.338165 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
803 00:21:57.341430 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
804 00:21:57.344752 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
805 00:21:57.351665 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 00:21:57.355106 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 00:21:57.358386 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 00:21:57.364934 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 00:21:57.368397 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 00:21:57.371740 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 00:21:57.378555 0 9 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
812 00:21:57.381829 0 9 8 | B1->B0 | 2323 3434 | 1 1 | (1 1) (1 1)
813 00:21:57.385055 0 9 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
814 00:21:57.388430 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 00:21:57.395241 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 00:21:57.398409 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 00:21:57.402117 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 00:21:57.408631 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 00:21:57.412023 0 10 4 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)
820 00:21:57.415435 0 10 8 | B1->B0 | 3232 2323 | 0 0 | (0 0) (0 0)
821 00:21:57.421915 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 00:21:57.425342 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 00:21:57.428676 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 00:21:57.435296 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 00:21:57.438700 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 00:21:57.442074 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 00:21:57.448847 0 11 4 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
828 00:21:57.451943 0 11 8 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
829 00:21:57.455736 0 11 12 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
830 00:21:57.458986 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 00:21:57.465587 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 00:21:57.468692 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 00:21:57.472121 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 00:21:57.478616 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 00:21:57.482490 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
836 00:21:57.485302 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
837 00:21:57.492064 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 00:21:57.495530 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 00:21:57.499336 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 00:21:57.503230 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 00:21:57.509445 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 00:21:57.512896 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 00:21:57.516165 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 00:21:57.522808 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 00:21:57.526294 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 00:21:57.529468 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 00:21:57.536418 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 00:21:57.539632 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 00:21:57.543169 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 00:21:57.546798 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 00:21:57.553024 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
852 00:21:57.556746 Total UI for P1: 0, mck2ui 16
853 00:21:57.560022 best dqsien dly found for B0: ( 0, 14, 2)
854 00:21:57.563314 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
855 00:21:57.566650 Total UI for P1: 0, mck2ui 16
856 00:21:57.569967 best dqsien dly found for B1: ( 0, 14, 6)
857 00:21:57.573302 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
858 00:21:57.576696 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
859 00:21:57.576816
860 00:21:57.579985 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
861 00:21:57.583365 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
862 00:21:57.586698 [Gating] SW calibration Done
863 00:21:57.586774 ==
864 00:21:57.590047 Dram Type= 6, Freq= 0, CH_0, rank 0
865 00:21:57.593355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
866 00:21:57.596737 ==
867 00:21:57.596833 RX Vref Scan: 0
868 00:21:57.596891
869 00:21:57.600097 RX Vref 0 -> 0, step: 1
870 00:21:57.600171
871 00:21:57.603524 RX Delay -130 -> 252, step: 16
872 00:21:57.606739 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
873 00:21:57.610459 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
874 00:21:57.613677 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
875 00:21:57.616984 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
876 00:21:57.620277 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
877 00:21:57.627135 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
878 00:21:57.630556 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
879 00:21:57.633873 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
880 00:21:57.637267 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
881 00:21:57.640338 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
882 00:21:57.647051 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
883 00:21:57.650163 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
884 00:21:57.653936 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
885 00:21:57.656994 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
886 00:21:57.660268 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
887 00:21:57.666953 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
888 00:21:57.667031 ==
889 00:21:57.670580 Dram Type= 6, Freq= 0, CH_0, rank 0
890 00:21:57.673925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
891 00:21:57.674002 ==
892 00:21:57.674060 DQS Delay:
893 00:21:57.677306 DQS0 = 0, DQS1 = 0
894 00:21:57.677382 DQM Delay:
895 00:21:57.680572 DQM0 = 89, DQM1 = 79
896 00:21:57.680648 DQ Delay:
897 00:21:57.684000 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
898 00:21:57.686924 DQ4 =85, DQ5 =77, DQ6 =101, DQ7 =101
899 00:21:57.690758 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
900 00:21:57.693737 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =85
901 00:21:57.693812
902 00:21:57.693870
903 00:21:57.693922 ==
904 00:21:57.697023 Dram Type= 6, Freq= 0, CH_0, rank 0
905 00:21:57.700815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
906 00:21:57.700893 ==
907 00:21:57.703822
908 00:21:57.703897
909 00:21:57.703955 TX Vref Scan disable
910 00:21:57.707173 == TX Byte 0 ==
911 00:21:57.710671 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
912 00:21:57.714152 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
913 00:21:57.717197 == TX Byte 1 ==
914 00:21:57.720557 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
915 00:21:57.723954 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
916 00:21:57.724030 ==
917 00:21:57.727524 Dram Type= 6, Freq= 0, CH_0, rank 0
918 00:21:57.734085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
919 00:21:57.734161 ==
920 00:21:57.745736 TX Vref=22, minBit 6, minWin=27, winSum=440
921 00:21:57.749148 TX Vref=24, minBit 8, minWin=27, winSum=445
922 00:21:57.752455 TX Vref=26, minBit 8, minWin=27, winSum=451
923 00:21:57.755368 TX Vref=28, minBit 3, minWin=28, winSum=456
924 00:21:57.759183 TX Vref=30, minBit 9, minWin=27, winSum=459
925 00:21:57.762198 TX Vref=32, minBit 6, minWin=28, winSum=458
926 00:21:57.769239 [TxChooseVref] Worse bit 6, Min win 28, Win sum 458, Final Vref 32
927 00:21:57.769319
928 00:21:57.772397 Final TX Range 1 Vref 32
929 00:21:57.772474
930 00:21:57.772532 ==
931 00:21:57.775989 Dram Type= 6, Freq= 0, CH_0, rank 0
932 00:21:57.778902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
933 00:21:57.778979 ==
934 00:21:57.779038
935 00:21:57.782345
936 00:21:57.782421 TX Vref Scan disable
937 00:21:57.785550 == TX Byte 0 ==
938 00:21:57.789145 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
939 00:21:57.792202 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
940 00:21:57.795726 == TX Byte 1 ==
941 00:21:57.798742 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
942 00:21:57.802242 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
943 00:21:57.805306
944 00:21:57.805382 [DATLAT]
945 00:21:57.805440 Freq=800, CH0 RK0
946 00:21:57.805496
947 00:21:57.808749 DATLAT Default: 0xa
948 00:21:57.808826 0, 0xFFFF, sum = 0
949 00:21:57.812188 1, 0xFFFF, sum = 0
950 00:21:57.812265 2, 0xFFFF, sum = 0
951 00:21:57.815554 3, 0xFFFF, sum = 0
952 00:21:57.815631 4, 0xFFFF, sum = 0
953 00:21:57.818772 5, 0xFFFF, sum = 0
954 00:21:57.818849 6, 0xFFFF, sum = 0
955 00:21:57.822387 7, 0xFFFF, sum = 0
956 00:21:57.825318 8, 0xFFFF, sum = 0
957 00:21:57.825395 9, 0x0, sum = 1
958 00:21:57.825455 10, 0x0, sum = 2
959 00:21:57.828900 11, 0x0, sum = 3
960 00:21:57.828977 12, 0x0, sum = 4
961 00:21:57.832252 best_step = 10
962 00:21:57.832327
963 00:21:57.832386 ==
964 00:21:57.835385 Dram Type= 6, Freq= 0, CH_0, rank 0
965 00:21:57.839018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
966 00:21:57.839095 ==
967 00:21:57.842213 RX Vref Scan: 1
968 00:21:57.842290
969 00:21:57.842349 Set Vref Range= 32 -> 127
970 00:21:57.845398
971 00:21:57.845474 RX Vref 32 -> 127, step: 1
972 00:21:57.845533
973 00:21:57.848663 RX Delay -95 -> 252, step: 8
974 00:21:57.848789
975 00:21:57.852098 Set Vref, RX VrefLevel [Byte0]: 32
976 00:21:57.855623 [Byte1]: 32
977 00:21:57.855733
978 00:21:57.858891 Set Vref, RX VrefLevel [Byte0]: 33
979 00:21:57.862234 [Byte1]: 33
980 00:21:57.865729
981 00:21:57.865830 Set Vref, RX VrefLevel [Byte0]: 34
982 00:21:57.869233 [Byte1]: 34
983 00:21:57.873512
984 00:21:57.873611 Set Vref, RX VrefLevel [Byte0]: 35
985 00:21:57.876744 [Byte1]: 35
986 00:21:57.881125
987 00:21:57.881206 Set Vref, RX VrefLevel [Byte0]: 36
988 00:21:57.884179 [Byte1]: 36
989 00:21:57.888427
990 00:21:57.888534 Set Vref, RX VrefLevel [Byte0]: 37
991 00:21:57.891625 [Byte1]: 37
992 00:21:57.896339
993 00:21:57.896478 Set Vref, RX VrefLevel [Byte0]: 38
994 00:21:57.899589 [Byte1]: 38
995 00:21:57.904115
996 00:21:57.904259 Set Vref, RX VrefLevel [Byte0]: 39
997 00:21:57.906963 [Byte1]: 39
998 00:21:57.911343
999 00:21:57.911514 Set Vref, RX VrefLevel [Byte0]: 40
1000 00:21:57.914988 [Byte1]: 40
1001 00:21:57.919452
1002 00:21:57.919610 Set Vref, RX VrefLevel [Byte0]: 41
1003 00:21:57.922770 [Byte1]: 41
1004 00:21:57.927063
1005 00:21:57.927238 Set Vref, RX VrefLevel [Byte0]: 42
1006 00:21:57.930144 [Byte1]: 42
1007 00:21:57.934569
1008 00:21:57.934757 Set Vref, RX VrefLevel [Byte0]: 43
1009 00:21:57.937864 [Byte1]: 43
1010 00:21:57.942013
1011 00:21:57.942224 Set Vref, RX VrefLevel [Byte0]: 44
1012 00:21:57.945090 [Byte1]: 44
1013 00:21:57.949547
1014 00:21:57.949803 Set Vref, RX VrefLevel [Byte0]: 45
1015 00:21:57.953107 [Byte1]: 45
1016 00:21:57.957137
1017 00:21:57.957529 Set Vref, RX VrefLevel [Byte0]: 46
1018 00:21:57.960589 [Byte1]: 46
1019 00:21:57.964989
1020 00:21:57.965143 Set Vref, RX VrefLevel [Byte0]: 47
1021 00:21:57.968189 [Byte1]: 47
1022 00:21:57.972249
1023 00:21:57.972373 Set Vref, RX VrefLevel [Byte0]: 48
1024 00:21:57.975572 [Byte1]: 48
1025 00:21:57.979954
1026 00:21:57.980063 Set Vref, RX VrefLevel [Byte0]: 49
1027 00:21:57.983159 [Byte1]: 49
1028 00:21:57.987290
1029 00:21:57.987387 Set Vref, RX VrefLevel [Byte0]: 50
1030 00:21:57.990576 [Byte1]: 50
1031 00:21:57.995200
1032 00:21:57.995278 Set Vref, RX VrefLevel [Byte0]: 51
1033 00:21:57.998394 [Byte1]: 51
1034 00:21:58.002485
1035 00:21:58.002585 Set Vref, RX VrefLevel [Byte0]: 52
1036 00:21:58.005860 [Byte1]: 52
1037 00:21:58.010174
1038 00:21:58.010272 Set Vref, RX VrefLevel [Byte0]: 53
1039 00:21:58.013618 [Byte1]: 53
1040 00:21:58.017674
1041 00:21:58.017748 Set Vref, RX VrefLevel [Byte0]: 54
1042 00:21:58.021040 [Byte1]: 54
1043 00:21:58.025388
1044 00:21:58.025461 Set Vref, RX VrefLevel [Byte0]: 55
1045 00:21:58.028746 [Byte1]: 55
1046 00:21:58.032871
1047 00:21:58.032961 Set Vref, RX VrefLevel [Byte0]: 56
1048 00:21:58.036048 [Byte1]: 56
1049 00:21:58.040426
1050 00:21:58.040549 Set Vref, RX VrefLevel [Byte0]: 57
1051 00:21:58.043889 [Byte1]: 57
1052 00:21:58.048196
1053 00:21:58.048269 Set Vref, RX VrefLevel [Byte0]: 58
1054 00:21:58.051615 [Byte1]: 58
1055 00:21:58.055853
1056 00:21:58.055930 Set Vref, RX VrefLevel [Byte0]: 59
1057 00:21:58.059148 [Byte1]: 59
1058 00:21:58.063484
1059 00:21:58.063557 Set Vref, RX VrefLevel [Byte0]: 60
1060 00:21:58.066983 [Byte1]: 60
1061 00:21:58.070751
1062 00:21:58.070824 Set Vref, RX VrefLevel [Byte0]: 61
1063 00:21:58.074302 [Byte1]: 61
1064 00:21:58.078567
1065 00:21:58.078641 Set Vref, RX VrefLevel [Byte0]: 62
1066 00:21:58.082129 [Byte1]: 62
1067 00:21:58.086234
1068 00:21:58.086308 Set Vref, RX VrefLevel [Byte0]: 63
1069 00:21:58.089625 [Byte1]: 63
1070 00:21:58.093723
1071 00:21:58.093797 Set Vref, RX VrefLevel [Byte0]: 64
1072 00:21:58.097071 [Byte1]: 64
1073 00:21:58.101510
1074 00:21:58.101585 Set Vref, RX VrefLevel [Byte0]: 65
1075 00:21:58.104809 [Byte1]: 65
1076 00:21:58.109038
1077 00:21:58.109113 Set Vref, RX VrefLevel [Byte0]: 66
1078 00:21:58.112408 [Byte1]: 66
1079 00:21:58.116735
1080 00:21:58.116824 Set Vref, RX VrefLevel [Byte0]: 67
1081 00:21:58.119681 [Byte1]: 67
1082 00:21:58.123975
1083 00:21:58.124050 Set Vref, RX VrefLevel [Byte0]: 68
1084 00:21:58.127474 [Byte1]: 68
1085 00:21:58.131839
1086 00:21:58.131914 Set Vref, RX VrefLevel [Byte0]: 69
1087 00:21:58.135378 [Byte1]: 69
1088 00:21:58.139210
1089 00:21:58.139285 Set Vref, RX VrefLevel [Byte0]: 70
1090 00:21:58.142501 [Byte1]: 70
1091 00:21:58.146901
1092 00:21:58.146978 Set Vref, RX VrefLevel [Byte0]: 71
1093 00:21:58.150363 [Byte1]: 71
1094 00:21:58.154580
1095 00:21:58.154657 Set Vref, RX VrefLevel [Byte0]: 72
1096 00:21:58.157917 [Byte1]: 72
1097 00:21:58.161899
1098 00:21:58.161974 Set Vref, RX VrefLevel [Byte0]: 73
1099 00:21:58.165522 [Byte1]: 73
1100 00:21:58.169842
1101 00:21:58.169918 Set Vref, RX VrefLevel [Byte0]: 74
1102 00:21:58.172829 [Byte1]: 74
1103 00:21:58.177081
1104 00:21:58.177157 Set Vref, RX VrefLevel [Byte0]: 75
1105 00:21:58.180590 [Byte1]: 75
1106 00:21:58.184954
1107 00:21:58.185031 Set Vref, RX VrefLevel [Byte0]: 76
1108 00:21:58.188375 [Byte1]: 76
1109 00:21:58.192653
1110 00:21:58.192766 Set Vref, RX VrefLevel [Byte0]: 77
1111 00:21:58.195548 [Byte1]: 77
1112 00:21:58.199888
1113 00:21:58.199963 Set Vref, RX VrefLevel [Byte0]: 78
1114 00:21:58.203407 [Byte1]: 78
1115 00:21:58.207587
1116 00:21:58.207662 Final RX Vref Byte 0 = 62 to rank0
1117 00:21:58.210997 Final RX Vref Byte 1 = 59 to rank0
1118 00:21:58.214379 Final RX Vref Byte 0 = 62 to rank1
1119 00:21:58.217662 Final RX Vref Byte 1 = 59 to rank1==
1120 00:21:58.221050 Dram Type= 6, Freq= 0, CH_0, rank 0
1121 00:21:58.227701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1122 00:21:58.227782 ==
1123 00:21:58.227861 DQS Delay:
1124 00:21:58.227935 DQS0 = 0, DQS1 = 0
1125 00:21:58.231121 DQM Delay:
1126 00:21:58.231200 DQM0 = 93, DQM1 = 81
1127 00:21:58.234594 DQ Delay:
1128 00:21:58.237943 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1129 00:21:58.238023 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1130 00:21:58.241323 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =76
1131 00:21:58.247980 DQ12 =84, DQ13 =80, DQ14 =92, DQ15 =92
1132 00:21:58.248059
1133 00:21:58.248137
1134 00:21:58.254627 [DQSOSCAuto] RK0, (LSB)MR18= 0x443f, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
1135 00:21:58.258194 CH0 RK0: MR19=606, MR18=443F
1136 00:21:58.264691 CH0_RK0: MR19=0x606, MR18=0x443F, DQSOSC=392, MR23=63, INC=96, DEC=64
1137 00:21:58.264825
1138 00:21:58.268134 ----->DramcWriteLeveling(PI) begin...
1139 00:21:58.268214 ==
1140 00:21:58.271585 Dram Type= 6, Freq= 0, CH_0, rank 1
1141 00:21:58.274956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1142 00:21:58.275037 ==
1143 00:21:58.277973 Write leveling (Byte 0): 32 => 32
1144 00:21:58.281322 Write leveling (Byte 1): 33 => 33
1145 00:21:58.325472 DramcWriteLeveling(PI) end<-----
1146 00:21:58.325567
1147 00:21:58.325645 ==
1148 00:21:58.325718 Dram Type= 6, Freq= 0, CH_0, rank 1
1149 00:21:58.325789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1150 00:21:58.325860 ==
1151 00:21:58.326115 [Gating] SW mode calibration
1152 00:21:58.326202 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1153 00:21:58.326292 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1154 00:21:58.326395 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1155 00:21:58.326482 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1156 00:21:58.326972 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 00:21:58.327059 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 00:21:58.335814 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 00:21:58.338903 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 00:21:58.338982 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 00:21:58.342613 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 00:21:58.346035 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 00:21:58.349256 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 00:21:58.355765 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 00:21:58.359008 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 00:21:58.362460 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 00:21:58.368964 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 00:21:58.372305 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 00:21:58.375858 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 00:21:58.382626 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 00:21:58.386024 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1172 00:21:58.389183 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 00:21:58.395572 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 00:21:58.399011 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 00:21:58.402397 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 00:21:58.409281 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 00:21:58.412754 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 00:21:58.415897 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 00:21:58.423386 0 9 4 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
1180 00:21:58.426679 0 9 8 | B1->B0 | 2c2c 3434 | 1 0 | (1 1) (0 0)
1181 00:21:58.429774 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 00:21:58.436448 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 00:21:58.439954 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 00:21:58.443218 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 00:21:58.446297 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 00:21:58.453667 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1187 00:21:58.456646 0 10 4 | B1->B0 | 3434 3030 | 0 1 | (0 0) (1 0)
1188 00:21:58.460231 0 10 8 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
1189 00:21:58.466097 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 00:21:58.469504 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 00:21:58.473006 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 00:21:58.479504 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 00:21:58.483150 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 00:21:58.486433 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 00:21:58.492988 0 11 4 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)
1196 00:21:58.496250 0 11 8 | B1->B0 | 3b3b 4545 | 0 0 | (0 0) (0 0)
1197 00:21:58.499533 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 00:21:58.505954 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 00:21:58.509613 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 00:21:58.512467 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 00:21:58.519453 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 00:21:58.522894 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 00:21:58.525944 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1204 00:21:58.529448 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 00:21:58.536031 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 00:21:58.539345 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 00:21:58.542473 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 00:21:58.549524 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 00:21:58.552398 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 00:21:58.555821 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 00:21:58.562846 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 00:21:58.565923 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 00:21:58.569260 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 00:21:58.575949 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 00:21:58.579360 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 00:21:58.582608 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 00:21:58.589259 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 00:21:58.592655 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 00:21:58.596021 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1220 00:21:58.602801 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1221 00:21:58.606016 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1222 00:21:58.609096 Total UI for P1: 0, mck2ui 16
1223 00:21:58.612421 best dqsien dly found for B0: ( 0, 14, 6)
1224 00:21:58.616109 Total UI for P1: 0, mck2ui 16
1225 00:21:58.619323 best dqsien dly found for B1: ( 0, 14, 8)
1226 00:21:58.622671 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1227 00:21:58.625972 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1228 00:21:58.626076
1229 00:21:58.629522 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1230 00:21:58.632474 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1231 00:21:58.635984 [Gating] SW calibration Done
1232 00:21:58.636064 ==
1233 00:21:58.639690 Dram Type= 6, Freq= 0, CH_0, rank 1
1234 00:21:58.642614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1235 00:21:58.642684 ==
1236 00:21:58.646190 RX Vref Scan: 0
1237 00:21:58.646266
1238 00:21:58.646324 RX Vref 0 -> 0, step: 1
1239 00:21:58.646379
1240 00:21:58.649321 RX Delay -130 -> 252, step: 16
1241 00:21:58.652674 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1242 00:21:58.659296 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1243 00:21:58.662667 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1244 00:21:58.666246 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1245 00:21:58.669784 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1246 00:21:58.673027 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1247 00:21:58.679541 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1248 00:21:58.682981 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1249 00:21:58.686308 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1250 00:21:58.689806 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
1251 00:21:58.693212 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1252 00:21:58.699405 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1253 00:21:58.702852 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1254 00:21:58.706099 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1255 00:21:58.709541 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1256 00:21:58.712878 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1257 00:21:58.716342 ==
1258 00:21:58.719350 Dram Type= 6, Freq= 0, CH_0, rank 1
1259 00:21:58.722912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1260 00:21:58.723017 ==
1261 00:21:58.723111 DQS Delay:
1262 00:21:58.726105 DQS0 = 0, DQS1 = 0
1263 00:21:58.726264 DQM Delay:
1264 00:21:58.729758 DQM0 = 88, DQM1 = 81
1265 00:21:58.729898 DQ Delay:
1266 00:21:58.732637 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =77
1267 00:21:58.736094 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
1268 00:21:58.739554 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
1269 00:21:58.742823 DQ12 =77, DQ13 =93, DQ14 =93, DQ15 =93
1270 00:21:58.743007
1271 00:21:58.743165
1272 00:21:58.743314 ==
1273 00:21:58.746508 Dram Type= 6, Freq= 0, CH_0, rank 1
1274 00:21:58.749782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1275 00:21:58.749941 ==
1276 00:21:58.750052
1277 00:21:58.750154
1278 00:21:58.753340 TX Vref Scan disable
1279 00:21:58.756582 == TX Byte 0 ==
1280 00:21:58.759634 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1281 00:21:58.763192 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1282 00:21:58.766430 == TX Byte 1 ==
1283 00:21:58.769792 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1284 00:21:58.773075 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1285 00:21:58.773214 ==
1286 00:21:58.776399 Dram Type= 6, Freq= 0, CH_0, rank 1
1287 00:21:58.780174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1288 00:21:58.783059 ==
1289 00:21:58.794502 TX Vref=22, minBit 8, minWin=27, winSum=447
1290 00:21:58.797947 TX Vref=24, minBit 8, minWin=27, winSum=449
1291 00:21:58.801149 TX Vref=26, minBit 8, minWin=28, winSum=457
1292 00:21:58.804632 TX Vref=28, minBit 8, minWin=28, winSum=457
1293 00:21:58.807634 TX Vref=30, minBit 8, minWin=28, winSum=458
1294 00:21:58.811549 TX Vref=32, minBit 6, minWin=28, winSum=457
1295 00:21:58.817980 [TxChooseVref] Worse bit 8, Min win 28, Win sum 458, Final Vref 30
1296 00:21:58.818422
1297 00:21:58.821272 Final TX Range 1 Vref 30
1298 00:21:58.821727
1299 00:21:58.822005 ==
1300 00:21:58.824817 Dram Type= 6, Freq= 0, CH_0, rank 1
1301 00:21:58.828290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1302 00:21:58.828811 ==
1303 00:21:58.829122
1304 00:21:58.830979
1305 00:21:58.831357 TX Vref Scan disable
1306 00:21:58.834473 == TX Byte 0 ==
1307 00:21:58.837800 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1308 00:21:58.841380 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1309 00:21:58.844651 == TX Byte 1 ==
1310 00:21:58.847596 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1311 00:21:58.851453 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1312 00:21:58.854480
1313 00:21:58.854863 [DATLAT]
1314 00:21:58.855159 Freq=800, CH0 RK1
1315 00:21:58.855438
1316 00:21:58.857594 DATLAT Default: 0xa
1317 00:21:58.857976 0, 0xFFFF, sum = 0
1318 00:21:58.861185 1, 0xFFFF, sum = 0
1319 00:21:58.861575 2, 0xFFFF, sum = 0
1320 00:21:58.864730 3, 0xFFFF, sum = 0
1321 00:21:58.865127 4, 0xFFFF, sum = 0
1322 00:21:58.868077 5, 0xFFFF, sum = 0
1323 00:21:58.868478 6, 0xFFFF, sum = 0
1324 00:21:58.871070 7, 0xFFFF, sum = 0
1325 00:21:58.871465 8, 0xFFFF, sum = 0
1326 00:21:58.874555 9, 0x0, sum = 1
1327 00:21:58.875058 10, 0x0, sum = 2
1328 00:21:58.877896 11, 0x0, sum = 3
1329 00:21:58.878288 12, 0x0, sum = 4
1330 00:21:58.881428 best_step = 10
1331 00:21:58.881811
1332 00:21:58.882101 ==
1333 00:21:58.884440 Dram Type= 6, Freq= 0, CH_0, rank 1
1334 00:21:58.887786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1335 00:21:58.888258 ==
1336 00:21:58.891058 RX Vref Scan: 0
1337 00:21:58.891338
1338 00:21:58.891549 RX Vref 0 -> 0, step: 1
1339 00:21:58.891744
1340 00:21:58.894449 RX Delay -95 -> 252, step: 8
1341 00:21:58.901106 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1342 00:21:58.904479 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1343 00:21:58.907892 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1344 00:21:58.911364 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1345 00:21:58.914701 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1346 00:21:58.917591 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1347 00:21:58.924526 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1348 00:21:58.927610 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1349 00:21:58.931511 iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208
1350 00:21:58.934623 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1351 00:21:58.941265 iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208
1352 00:21:58.944308 iDelay=209, Bit 11, Center 80 (-23 ~ 184) 208
1353 00:21:58.947931 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1354 00:21:58.951384 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1355 00:21:58.954464 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1356 00:21:58.961597 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1357 00:21:58.961890 ==
1358 00:21:58.964555 Dram Type= 6, Freq= 0, CH_0, rank 1
1359 00:21:58.968013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1360 00:21:58.968370 ==
1361 00:21:58.968636 DQS Delay:
1362 00:21:58.972007 DQS0 = 0, DQS1 = 0
1363 00:21:58.972476 DQM Delay:
1364 00:21:58.974672 DQM0 = 90, DQM1 = 81
1365 00:21:58.975056 DQ Delay:
1366 00:21:58.978535 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =84
1367 00:21:58.981381 DQ4 =88, DQ5 =80, DQ6 =100, DQ7 =100
1368 00:21:58.984898 DQ8 =72, DQ9 =68, DQ10 =80, DQ11 =80
1369 00:21:58.988618 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =88
1370 00:21:58.989140
1371 00:21:58.989441
1372 00:21:58.995139 [DQSOSCAuto] RK1, (LSB)MR18= 0x4923, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 391 ps
1373 00:21:58.998383 CH0 RK1: MR19=606, MR18=4923
1374 00:21:59.005420 CH0_RK1: MR19=0x606, MR18=0x4923, DQSOSC=391, MR23=63, INC=96, DEC=64
1375 00:21:59.008666 [RxdqsGatingPostProcess] freq 800
1376 00:21:59.015214 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1377 00:21:59.015684 Pre-setting of DQS Precalculation
1378 00:21:59.022004 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1379 00:21:59.022478 ==
1380 00:21:59.025406 Dram Type= 6, Freq= 0, CH_1, rank 0
1381 00:21:59.028367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1382 00:21:59.028882 ==
1383 00:21:59.035100 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1384 00:21:59.041375 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1385 00:21:59.049541 [CA 0] Center 36 (6~67) winsize 62
1386 00:21:59.052770 [CA 1] Center 36 (6~67) winsize 62
1387 00:21:59.056506 [CA 2] Center 34 (4~65) winsize 62
1388 00:21:59.059488 [CA 3] Center 34 (3~65) winsize 63
1389 00:21:59.063185 [CA 4] Center 34 (4~65) winsize 62
1390 00:21:59.066538 [CA 5] Center 34 (3~65) winsize 63
1391 00:21:59.067006
1392 00:21:59.070229 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1393 00:21:59.070709
1394 00:21:59.073380 [CATrainingPosCal] consider 1 rank data
1395 00:21:59.076540 u2DelayCellTimex100 = 270/100 ps
1396 00:21:59.079973 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1397 00:21:59.083295 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1398 00:21:59.089756 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1399 00:21:59.093174 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1400 00:21:59.096531 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1401 00:21:59.100118 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1402 00:21:59.100507
1403 00:21:59.103101 CA PerBit enable=1, Macro0, CA PI delay=34
1404 00:21:59.103488
1405 00:21:59.106840 [CBTSetCACLKResult] CA Dly = 34
1406 00:21:59.107233 CS Dly: 5 (0~36)
1407 00:21:59.107538 ==
1408 00:21:59.109866 Dram Type= 6, Freq= 0, CH_1, rank 1
1409 00:21:59.116857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1410 00:21:59.117328 ==
1411 00:21:59.120011 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1412 00:21:59.126952 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1413 00:21:59.136071 [CA 0] Center 36 (6~67) winsize 62
1414 00:21:59.139466 [CA 1] Center 37 (6~68) winsize 63
1415 00:21:59.142188 [CA 2] Center 35 (4~66) winsize 63
1416 00:21:59.145457 [CA 3] Center 34 (4~65) winsize 62
1417 00:21:59.149090 [CA 4] Center 34 (4~65) winsize 62
1418 00:21:59.152209 [CA 5] Center 34 (4~65) winsize 62
1419 00:21:59.152595
1420 00:21:59.156120 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1421 00:21:59.156598
1422 00:21:59.159268 [CATrainingPosCal] consider 2 rank data
1423 00:21:59.162316 u2DelayCellTimex100 = 270/100 ps
1424 00:21:59.165826 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1425 00:21:59.169185 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1426 00:21:59.172732 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1427 00:21:59.179129 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1428 00:21:59.182816 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1429 00:21:59.186260 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1430 00:21:59.186736
1431 00:21:59.189589 CA PerBit enable=1, Macro0, CA PI delay=34
1432 00:21:59.190062
1433 00:21:59.193200 [CBTSetCACLKResult] CA Dly = 34
1434 00:21:59.193671 CS Dly: 6 (0~38)
1435 00:21:59.193979
1436 00:21:59.196566 ----->DramcWriteLeveling(PI) begin...
1437 00:21:59.197144 ==
1438 00:21:59.199859 Dram Type= 6, Freq= 0, CH_1, rank 0
1439 00:21:59.206373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1440 00:21:59.206849 ==
1441 00:21:59.209207 Write leveling (Byte 0): 26 => 26
1442 00:21:59.212962 Write leveling (Byte 1): 30 => 30
1443 00:21:59.213437 DramcWriteLeveling(PI) end<-----
1444 00:21:59.213748
1445 00:21:59.216306 ==
1446 00:21:59.219460 Dram Type= 6, Freq= 0, CH_1, rank 0
1447 00:21:59.223050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1448 00:21:59.223526 ==
1449 00:21:59.226622 [Gating] SW mode calibration
1450 00:21:59.233049 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1451 00:21:59.236295 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1452 00:21:59.242609 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1453 00:21:59.245979 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1454 00:21:59.249279 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1455 00:21:59.256393 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 00:21:59.259516 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 00:21:59.262973 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 00:21:59.269314 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 00:21:59.273058 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 00:21:59.276217 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 00:21:59.279701 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 00:21:59.286106 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 00:21:59.289665 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 00:21:59.293212 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 00:21:59.299639 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 00:21:59.303230 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 00:21:59.306736 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1468 00:21:59.312884 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1469 00:21:59.316757 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1470 00:21:59.319872 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1471 00:21:59.326932 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 00:21:59.329961 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 00:21:59.333507 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 00:21:59.340213 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 00:21:59.343248 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 00:21:59.346405 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 00:21:59.353053 0 9 4 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
1478 00:21:59.356330 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 00:21:59.359701 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 00:21:59.363134 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 00:21:59.369571 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 00:21:59.373382 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 00:21:59.376763 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 00:21:59.383574 0 10 0 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
1485 00:21:59.386805 0 10 4 | B1->B0 | 3030 2626 | 0 0 | (1 1) (0 0)
1486 00:21:59.389804 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 00:21:59.396730 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 00:21:59.399611 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 00:21:59.403831 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 00:21:59.409727 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 00:21:59.413507 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 00:21:59.416911 0 11 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1493 00:21:59.423239 0 11 4 | B1->B0 | 2e2e 4040 | 0 0 | (0 0) (0 0)
1494 00:21:59.426869 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 00:21:59.430171 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 00:21:59.433639 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 00:21:59.440491 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 00:21:59.443651 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 00:21:59.446869 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 00:21:59.453656 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1501 00:21:59.457094 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1502 00:21:59.459960 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 00:21:59.466432 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 00:21:59.469936 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 00:21:59.473467 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 00:21:59.479836 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 00:21:59.483731 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 00:21:59.487064 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 00:21:59.493219 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 00:21:59.497310 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 00:21:59.499785 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 00:21:59.506734 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 00:21:59.510162 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 00:21:59.513606 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 00:21:59.520110 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 00:21:59.523546 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1517 00:21:59.526987 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1518 00:21:59.530329 Total UI for P1: 0, mck2ui 16
1519 00:21:59.533296 best dqsien dly found for B0: ( 0, 14, 0)
1520 00:21:59.537080 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1521 00:21:59.539841 Total UI for P1: 0, mck2ui 16
1522 00:21:59.543752 best dqsien dly found for B1: ( 0, 14, 4)
1523 00:21:59.546146 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1524 00:21:59.553390 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1525 00:21:59.553857
1526 00:21:59.556740 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1527 00:21:59.560301 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1528 00:21:59.562934 [Gating] SW calibration Done
1529 00:21:59.563319 ==
1530 00:21:59.566489 Dram Type= 6, Freq= 0, CH_1, rank 0
1531 00:21:59.569722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1532 00:21:59.570195 ==
1533 00:21:59.570534 RX Vref Scan: 0
1534 00:21:59.571035
1535 00:21:59.573005 RX Vref 0 -> 0, step: 1
1536 00:21:59.573388
1537 00:21:59.576815 RX Delay -130 -> 252, step: 16
1538 00:21:59.579860 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1539 00:21:59.583276 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1540 00:21:59.589823 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1541 00:21:59.593329 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1542 00:21:59.596601 iDelay=222, Bit 4, Center 77 (-34 ~ 189) 224
1543 00:21:59.599758 iDelay=222, Bit 5, Center 93 (-18 ~ 205) 224
1544 00:21:59.603604 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1545 00:21:59.609874 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1546 00:21:59.613332 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1547 00:21:59.616254 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1548 00:21:59.619801 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1549 00:21:59.623546 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1550 00:21:59.629657 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1551 00:21:59.633284 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1552 00:21:59.636558 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1553 00:21:59.639816 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1554 00:21:59.640206 ==
1555 00:21:59.642881 Dram Type= 6, Freq= 0, CH_1, rank 0
1556 00:21:59.650061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1557 00:21:59.650537 ==
1558 00:21:59.650840 DQS Delay:
1559 00:21:59.651114 DQS0 = 0, DQS1 = 0
1560 00:21:59.653231 DQM Delay:
1561 00:21:59.653700 DQM0 = 86, DQM1 = 80
1562 00:21:59.656676 DQ Delay:
1563 00:21:59.659918 DQ0 =93, DQ1 =77, DQ2 =77, DQ3 =85
1564 00:21:59.660310 DQ4 =77, DQ5 =93, DQ6 =101, DQ7 =85
1565 00:21:59.663748 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1566 00:21:59.666897 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1567 00:21:59.670045
1568 00:21:59.670524
1569 00:21:59.670829 ==
1570 00:21:59.673380 Dram Type= 6, Freq= 0, CH_1, rank 0
1571 00:21:59.676808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1572 00:21:59.677288 ==
1573 00:21:59.677592
1574 00:21:59.677866
1575 00:21:59.680232 TX Vref Scan disable
1576 00:21:59.680620 == TX Byte 0 ==
1577 00:21:59.687385 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1578 00:21:59.690218 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1579 00:21:59.690737 == TX Byte 1 ==
1580 00:21:59.697275 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1581 00:21:59.700026 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1582 00:21:59.700414 ==
1583 00:21:59.703332 Dram Type= 6, Freq= 0, CH_1, rank 0
1584 00:21:59.706721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1585 00:21:59.707197 ==
1586 00:21:59.720775 TX Vref=22, minBit 8, minWin=27, winSum=448
1587 00:21:59.724162 TX Vref=24, minBit 8, minWin=27, winSum=451
1588 00:21:59.727495 TX Vref=26, minBit 15, minWin=27, winSum=456
1589 00:21:59.730481 TX Vref=28, minBit 0, minWin=28, winSum=455
1590 00:21:59.734260 TX Vref=30, minBit 15, minWin=27, winSum=454
1591 00:21:59.740935 TX Vref=32, minBit 15, minWin=27, winSum=455
1592 00:21:59.744048 [TxChooseVref] Worse bit 0, Min win 28, Win sum 455, Final Vref 28
1593 00:21:59.744520
1594 00:21:59.747275 Final TX Range 1 Vref 28
1595 00:21:59.747753
1596 00:21:59.748056 ==
1597 00:21:59.750822 Dram Type= 6, Freq= 0, CH_1, rank 0
1598 00:21:59.754220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1599 00:21:59.754697 ==
1600 00:21:59.757594
1601 00:21:59.758066
1602 00:21:59.758369 TX Vref Scan disable
1603 00:21:59.760736 == TX Byte 0 ==
1604 00:21:59.764220 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1605 00:21:59.767148 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1606 00:21:59.771010 == TX Byte 1 ==
1607 00:21:59.774232 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1608 00:21:59.777353 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1609 00:21:59.780872
1610 00:21:59.781341 [DATLAT]
1611 00:21:59.781644 Freq=800, CH1 RK0
1612 00:21:59.781925
1613 00:21:59.784426 DATLAT Default: 0xa
1614 00:21:59.784949 0, 0xFFFF, sum = 0
1615 00:21:59.787900 1, 0xFFFF, sum = 0
1616 00:21:59.788376 2, 0xFFFF, sum = 0
1617 00:21:59.790836 3, 0xFFFF, sum = 0
1618 00:21:59.791315 4, 0xFFFF, sum = 0
1619 00:21:59.794472 5, 0xFFFF, sum = 0
1620 00:21:59.794951 6, 0xFFFF, sum = 0
1621 00:21:59.797284 7, 0xFFFF, sum = 0
1622 00:21:59.797677 8, 0xFFFF, sum = 0
1623 00:21:59.800929 9, 0x0, sum = 1
1624 00:21:59.801415 10, 0x0, sum = 2
1625 00:21:59.804448 11, 0x0, sum = 3
1626 00:21:59.804964 12, 0x0, sum = 4
1627 00:21:59.808010 best_step = 10
1628 00:21:59.808482
1629 00:21:59.808811 ==
1630 00:21:59.810701 Dram Type= 6, Freq= 0, CH_1, rank 0
1631 00:21:59.814340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1632 00:21:59.814861 ==
1633 00:21:59.817706 RX Vref Scan: 1
1634 00:21:59.818178
1635 00:21:59.818482 Set Vref Range= 32 -> 127
1636 00:21:59.818849
1637 00:21:59.820870 RX Vref 32 -> 127, step: 1
1638 00:21:59.821258
1639 00:21:59.824519 RX Delay -95 -> 252, step: 8
1640 00:21:59.825015
1641 00:21:59.827400 Set Vref, RX VrefLevel [Byte0]: 32
1642 00:21:59.830813 [Byte1]: 32
1643 00:21:59.831286
1644 00:21:59.834552 Set Vref, RX VrefLevel [Byte0]: 33
1645 00:21:59.837460 [Byte1]: 33
1646 00:21:59.841083
1647 00:21:59.841559 Set Vref, RX VrefLevel [Byte0]: 34
1648 00:21:59.844413 [Byte1]: 34
1649 00:21:59.849045
1650 00:21:59.849520 Set Vref, RX VrefLevel [Byte0]: 35
1651 00:21:59.852205 [Byte1]: 35
1652 00:21:59.856497
1653 00:21:59.857015 Set Vref, RX VrefLevel [Byte0]: 36
1654 00:21:59.859598 [Byte1]: 36
1655 00:21:59.863925
1656 00:21:59.864406 Set Vref, RX VrefLevel [Byte0]: 37
1657 00:21:59.867103 [Byte1]: 37
1658 00:21:59.871243
1659 00:21:59.871729 Set Vref, RX VrefLevel [Byte0]: 38
1660 00:21:59.874575 [Byte1]: 38
1661 00:21:59.879048
1662 00:21:59.879518 Set Vref, RX VrefLevel [Byte0]: 39
1663 00:21:59.882307 [Byte1]: 39
1664 00:21:59.886627
1665 00:21:59.887122 Set Vref, RX VrefLevel [Byte0]: 40
1666 00:21:59.889970 [Byte1]: 40
1667 00:21:59.894504
1668 00:21:59.894977 Set Vref, RX VrefLevel [Byte0]: 41
1669 00:21:59.897639 [Byte1]: 41
1670 00:21:59.901885
1671 00:21:59.902360 Set Vref, RX VrefLevel [Byte0]: 42
1672 00:21:59.904879 [Byte1]: 42
1673 00:21:59.909098
1674 00:21:59.909533 Set Vref, RX VrefLevel [Byte0]: 43
1675 00:21:59.913044 [Byte1]: 43
1676 00:21:59.917280
1677 00:21:59.917749 Set Vref, RX VrefLevel [Byte0]: 44
1678 00:21:59.920464 [Byte1]: 44
1679 00:21:59.924433
1680 00:21:59.924871 Set Vref, RX VrefLevel [Byte0]: 45
1681 00:21:59.928184 [Byte1]: 45
1682 00:21:59.932229
1683 00:21:59.932619 Set Vref, RX VrefLevel [Byte0]: 46
1684 00:21:59.935288 [Byte1]: 46
1685 00:21:59.939612
1686 00:21:59.940005 Set Vref, RX VrefLevel [Byte0]: 47
1687 00:21:59.943054 [Byte1]: 47
1688 00:21:59.946950
1689 00:21:59.947350 Set Vref, RX VrefLevel [Byte0]: 48
1690 00:21:59.950663 [Byte1]: 48
1691 00:21:59.954986
1692 00:21:59.955376 Set Vref, RX VrefLevel [Byte0]: 49
1693 00:21:59.958164 [Byte1]: 49
1694 00:21:59.962568
1695 00:21:59.962963 Set Vref, RX VrefLevel [Byte0]: 50
1696 00:21:59.965782 [Byte1]: 50
1697 00:21:59.970024
1698 00:21:59.970449 Set Vref, RX VrefLevel [Byte0]: 51
1699 00:21:59.973310 [Byte1]: 51
1700 00:21:59.977622
1701 00:21:59.978008 Set Vref, RX VrefLevel [Byte0]: 52
1702 00:21:59.980856 [Byte1]: 52
1703 00:21:59.985063
1704 00:21:59.985531 Set Vref, RX VrefLevel [Byte0]: 53
1705 00:21:59.988504 [Byte1]: 53
1706 00:21:59.992923
1707 00:21:59.993402 Set Vref, RX VrefLevel [Byte0]: 54
1708 00:21:59.996274 [Byte1]: 54
1709 00:22:00.000869
1710 00:22:00.001358 Set Vref, RX VrefLevel [Byte0]: 55
1711 00:22:00.003997 [Byte1]: 55
1712 00:22:00.008114
1713 00:22:00.008505 Set Vref, RX VrefLevel [Byte0]: 56
1714 00:22:00.011068 [Byte1]: 56
1715 00:22:00.015967
1716 00:22:00.016440 Set Vref, RX VrefLevel [Byte0]: 57
1717 00:22:00.019451 [Byte1]: 57
1718 00:22:00.023085
1719 00:22:00.023477 Set Vref, RX VrefLevel [Byte0]: 58
1720 00:22:00.026828 [Byte1]: 58
1721 00:22:00.031086
1722 00:22:00.031562 Set Vref, RX VrefLevel [Byte0]: 59
1723 00:22:00.034437 [Byte1]: 59
1724 00:22:00.038645
1725 00:22:00.039035 Set Vref, RX VrefLevel [Byte0]: 60
1726 00:22:00.041807 [Byte1]: 60
1727 00:22:00.046243
1728 00:22:00.046722 Set Vref, RX VrefLevel [Byte0]: 61
1729 00:22:00.049393 [Byte1]: 61
1730 00:22:00.053981
1731 00:22:00.054455 Set Vref, RX VrefLevel [Byte0]: 62
1732 00:22:00.057511 [Byte1]: 62
1733 00:22:00.061310
1734 00:22:00.061787 Set Vref, RX VrefLevel [Byte0]: 63
1735 00:22:00.064685 [Byte1]: 63
1736 00:22:00.069285
1737 00:22:00.069758 Set Vref, RX VrefLevel [Byte0]: 64
1738 00:22:00.072400 [Byte1]: 64
1739 00:22:00.076282
1740 00:22:00.076799 Set Vref, RX VrefLevel [Byte0]: 65
1741 00:22:00.079651 [Byte1]: 65
1742 00:22:00.084227
1743 00:22:00.084694 Set Vref, RX VrefLevel [Byte0]: 66
1744 00:22:00.087726 [Byte1]: 66
1745 00:22:00.091662
1746 00:22:00.092054 Set Vref, RX VrefLevel [Byte0]: 67
1747 00:22:00.095336 [Byte1]: 67
1748 00:22:00.099341
1749 00:22:00.099817 Set Vref, RX VrefLevel [Byte0]: 68
1750 00:22:00.102963 [Byte1]: 68
1751 00:22:00.107064
1752 00:22:00.107573 Set Vref, RX VrefLevel [Byte0]: 69
1753 00:22:00.110095 [Byte1]: 69
1754 00:22:00.114972
1755 00:22:00.115442 Set Vref, RX VrefLevel [Byte0]: 70
1756 00:22:00.117687 [Byte1]: 70
1757 00:22:00.122557
1758 00:22:00.123031 Set Vref, RX VrefLevel [Byte0]: 71
1759 00:22:00.125551 [Byte1]: 71
1760 00:22:00.129910
1761 00:22:00.130382 Set Vref, RX VrefLevel [Byte0]: 72
1762 00:22:00.133574 [Byte1]: 72
1763 00:22:00.137585
1764 00:22:00.138054 Set Vref, RX VrefLevel [Byte0]: 73
1765 00:22:00.140866 [Byte1]: 73
1766 00:22:00.144751
1767 00:22:00.145265 Set Vref, RX VrefLevel [Byte0]: 74
1768 00:22:00.147858 [Byte1]: 74
1769 00:22:00.152735
1770 00:22:00.153214 Set Vref, RX VrefLevel [Byte0]: 75
1771 00:22:00.156217 [Byte1]: 75
1772 00:22:00.160023
1773 00:22:00.160497 Set Vref, RX VrefLevel [Byte0]: 76
1774 00:22:00.163563 [Byte1]: 76
1775 00:22:00.168072
1776 00:22:00.168546 Set Vref, RX VrefLevel [Byte0]: 77
1777 00:22:00.171069 [Byte1]: 77
1778 00:22:00.175376
1779 00:22:00.175853 Set Vref, RX VrefLevel [Byte0]: 78
1780 00:22:00.178567 [Byte1]: 78
1781 00:22:00.183086
1782 00:22:00.183560 Set Vref, RX VrefLevel [Byte0]: 79
1783 00:22:00.186024 [Byte1]: 79
1784 00:22:00.190307
1785 00:22:00.190778 Final RX Vref Byte 0 = 52 to rank0
1786 00:22:00.193969 Final RX Vref Byte 1 = 63 to rank0
1787 00:22:00.197574 Final RX Vref Byte 0 = 52 to rank1
1788 00:22:00.200616 Final RX Vref Byte 1 = 63 to rank1==
1789 00:22:00.204026 Dram Type= 6, Freq= 0, CH_1, rank 0
1790 00:22:00.207591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1791 00:22:00.210650 ==
1792 00:22:00.211040 DQS Delay:
1793 00:22:00.211344 DQS0 = 0, DQS1 = 0
1794 00:22:00.214397 DQM Delay:
1795 00:22:00.214868 DQM0 = 89, DQM1 = 82
1796 00:22:00.217424 DQ Delay:
1797 00:22:00.220927 DQ0 =96, DQ1 =84, DQ2 =80, DQ3 =84
1798 00:22:00.221405 DQ4 =88, DQ5 =96, DQ6 =100, DQ7 =84
1799 00:22:00.223777 DQ8 =72, DQ9 =68, DQ10 =84, DQ11 =80
1800 00:22:00.227285 DQ12 =92, DQ13 =88, DQ14 =84, DQ15 =88
1801 00:22:00.230983
1802 00:22:00.231457
1803 00:22:00.237170 [DQSOSCAuto] RK0, (LSB)MR18= 0x3653, (MSB)MR19= 0x606, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
1804 00:22:00.240850 CH1 RK0: MR19=606, MR18=3653
1805 00:22:00.247591 CH1_RK0: MR19=0x606, MR18=0x3653, DQSOSC=389, MR23=63, INC=97, DEC=65
1806 00:22:00.248073
1807 00:22:00.250845 ----->DramcWriteLeveling(PI) begin...
1808 00:22:00.251322 ==
1809 00:22:00.254468 Dram Type= 6, Freq= 0, CH_1, rank 1
1810 00:22:00.257463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1811 00:22:00.257858 ==
1812 00:22:00.260800 Write leveling (Byte 0): 29 => 29
1813 00:22:00.264638 Write leveling (Byte 1): 31 => 31
1814 00:22:00.267636 DramcWriteLeveling(PI) end<-----
1815 00:22:00.268106
1816 00:22:00.268407 ==
1817 00:22:00.270708 Dram Type= 6, Freq= 0, CH_1, rank 1
1818 00:22:00.274112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1819 00:22:00.274545 ==
1820 00:22:00.277585 [Gating] SW mode calibration
1821 00:22:00.284447 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1822 00:22:00.290634 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1823 00:22:00.294327 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1824 00:22:00.297553 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1825 00:22:00.304552 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 00:22:00.307822 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 00:22:00.311210 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 00:22:00.314661 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 00:22:00.321210 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 00:22:00.324753 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 00:22:00.328305 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 00:22:00.334259 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 00:22:00.338248 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 00:22:00.341169 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 00:22:00.347738 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 00:22:00.351600 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 00:22:00.354261 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 00:22:00.361013 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 00:22:00.364929 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1840 00:22:00.367772 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 00:22:00.375855 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 00:22:00.377459 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 00:22:00.380825 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 00:22:00.383830 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 00:22:00.390993 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 00:22:00.393927 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 00:22:00.397269 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 00:22:00.404440 0 9 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1849 00:22:00.407473 0 9 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
1850 00:22:00.410981 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1851 00:22:00.417658 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1852 00:22:00.422108 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1853 00:22:00.424638 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1854 00:22:00.431633 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1855 00:22:00.434876 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1856 00:22:00.438480 0 10 4 | B1->B0 | 2626 2f2f | 0 0 | (0 1) (0 1)
1857 00:22:00.441632 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1858 00:22:00.448192 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 00:22:00.451648 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 00:22:00.455289 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 00:22:00.461819 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 00:22:00.464740 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 00:22:00.468227 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 00:22:00.474928 0 11 4 | B1->B0 | 3333 2c2b | 1 1 | (1 1) (0 0)
1865 00:22:00.478485 0 11 8 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
1866 00:22:00.481359 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1867 00:22:00.488596 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1868 00:22:00.492066 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1869 00:22:00.494958 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1870 00:22:00.501997 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1871 00:22:00.505190 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1872 00:22:00.508636 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1873 00:22:00.515008 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 00:22:00.518384 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 00:22:00.521611 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 00:22:00.528545 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 00:22:00.532315 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 00:22:00.535217 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 00:22:00.538392 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 00:22:00.545501 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 00:22:00.548539 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 00:22:00.552093 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 00:22:00.558489 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1884 00:22:00.561755 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1885 00:22:00.565283 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1886 00:22:00.571863 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1887 00:22:00.575123 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1888 00:22:00.578992 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1889 00:22:00.585288 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1890 00:22:00.585753 Total UI for P1: 0, mck2ui 16
1891 00:22:00.589055 best dqsien dly found for B0: ( 0, 14, 4)
1892 00:22:00.592466 Total UI for P1: 0, mck2ui 16
1893 00:22:00.595950 best dqsien dly found for B1: ( 0, 14, 4)
1894 00:22:00.598599 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1895 00:22:00.602150 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1896 00:22:00.605661
1897 00:22:00.609153 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1898 00:22:00.612241 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1899 00:22:00.615575 [Gating] SW calibration Done
1900 00:22:00.615961 ==
1901 00:22:00.619306 Dram Type= 6, Freq= 0, CH_1, rank 1
1902 00:22:00.622638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1903 00:22:00.623113 ==
1904 00:22:00.623415 RX Vref Scan: 0
1905 00:22:00.623698
1906 00:22:00.625905 RX Vref 0 -> 0, step: 1
1907 00:22:00.626395
1908 00:22:00.629055 RX Delay -130 -> 252, step: 16
1909 00:22:00.632430 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1910 00:22:00.636032 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1911 00:22:00.639202 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1912 00:22:00.645513 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1913 00:22:00.649375 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1914 00:22:00.652892 iDelay=206, Bit 5, Center 101 (-2 ~ 205) 208
1915 00:22:00.655884 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1916 00:22:00.659218 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1917 00:22:00.666037 iDelay=206, Bit 8, Center 61 (-50 ~ 173) 224
1918 00:22:00.669590 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1919 00:22:00.672753 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1920 00:22:00.675619 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1921 00:22:00.679603 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1922 00:22:00.685517 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1923 00:22:00.688868 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1924 00:22:00.692399 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1925 00:22:00.693032 ==
1926 00:22:00.695748 Dram Type= 6, Freq= 0, CH_1, rank 1
1927 00:22:00.699428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1928 00:22:00.702367 ==
1929 00:22:00.702759 DQS Delay:
1930 00:22:00.703055 DQS0 = 0, DQS1 = 0
1931 00:22:00.705516 DQM Delay:
1932 00:22:00.705901 DQM0 = 87, DQM1 = 80
1933 00:22:00.709366 DQ Delay:
1934 00:22:00.709837 DQ0 =93, DQ1 =77, DQ2 =77, DQ3 =85
1935 00:22:00.712587 DQ4 =93, DQ5 =101, DQ6 =93, DQ7 =77
1936 00:22:00.715800 DQ8 =61, DQ9 =77, DQ10 =85, DQ11 =77
1937 00:22:00.719286 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1938 00:22:00.719765
1939 00:22:00.722180
1940 00:22:00.722563 ==
1941 00:22:00.725786 Dram Type= 6, Freq= 0, CH_1, rank 1
1942 00:22:00.729164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1943 00:22:00.729643 ==
1944 00:22:00.729950
1945 00:22:00.730223
1946 00:22:00.732304 TX Vref Scan disable
1947 00:22:00.732692 == TX Byte 0 ==
1948 00:22:00.739562 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1949 00:22:00.742215 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1950 00:22:00.742605 == TX Byte 1 ==
1951 00:22:00.748840 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1952 00:22:00.752207 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1953 00:22:00.752686 ==
1954 00:22:00.755788 Dram Type= 6, Freq= 0, CH_1, rank 1
1955 00:22:00.758780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1956 00:22:00.759177 ==
1957 00:22:00.772524 TX Vref=22, minBit 6, minWin=27, winSum=447
1958 00:22:00.775846 TX Vref=24, minBit 8, minWin=27, winSum=452
1959 00:22:00.779180 TX Vref=26, minBit 13, minWin=27, winSum=456
1960 00:22:00.782807 TX Vref=28, minBit 13, minWin=27, winSum=458
1961 00:22:00.786026 TX Vref=30, minBit 8, minWin=28, winSum=460
1962 00:22:00.792334 TX Vref=32, minBit 8, minWin=27, winSum=455
1963 00:22:00.796376 [TxChooseVref] Worse bit 8, Min win 28, Win sum 460, Final Vref 30
1964 00:22:00.796900
1965 00:22:00.798928 Final TX Range 1 Vref 30
1966 00:22:00.799396
1967 00:22:00.799694 ==
1968 00:22:00.802337 Dram Type= 6, Freq= 0, CH_1, rank 1
1969 00:22:00.805889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1970 00:22:00.806504 ==
1971 00:22:00.806820
1972 00:22:00.809162
1973 00:22:00.809638 TX Vref Scan disable
1974 00:22:00.812422 == TX Byte 0 ==
1975 00:22:00.815913 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1976 00:22:00.819332 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1977 00:22:00.822719 == TX Byte 1 ==
1978 00:22:00.826161 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1979 00:22:00.829558 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1980 00:22:00.832775
1981 00:22:00.833248 [DATLAT]
1982 00:22:00.833549 Freq=800, CH1 RK1
1983 00:22:00.833831
1984 00:22:00.835908 DATLAT Default: 0xa
1985 00:22:00.836297 0, 0xFFFF, sum = 0
1986 00:22:00.839711 1, 0xFFFF, sum = 0
1987 00:22:00.840193 2, 0xFFFF, sum = 0
1988 00:22:00.842335 3, 0xFFFF, sum = 0
1989 00:22:00.842728 4, 0xFFFF, sum = 0
1990 00:22:00.845809 5, 0xFFFF, sum = 0
1991 00:22:00.846289 6, 0xFFFF, sum = 0
1992 00:22:00.849254 7, 0xFFFF, sum = 0
1993 00:22:00.852815 8, 0xFFFF, sum = 0
1994 00:22:00.853296 9, 0x0, sum = 1
1995 00:22:00.853608 10, 0x0, sum = 2
1996 00:22:00.856411 11, 0x0, sum = 3
1997 00:22:00.856927 12, 0x0, sum = 4
1998 00:22:00.859260 best_step = 10
1999 00:22:00.859729
2000 00:22:00.860030 ==
2001 00:22:00.862473 Dram Type= 6, Freq= 0, CH_1, rank 1
2002 00:22:00.866074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2003 00:22:00.866555 ==
2004 00:22:00.869299 RX Vref Scan: 0
2005 00:22:00.869685
2006 00:22:00.869981 RX Vref 0 -> 0, step: 1
2007 00:22:00.870256
2008 00:22:00.872668 RX Delay -95 -> 252, step: 8
2009 00:22:00.879551 iDelay=209, Bit 0, Center 96 (-7 ~ 200) 208
2010 00:22:00.882985 iDelay=209, Bit 1, Center 84 (-23 ~ 192) 216
2011 00:22:00.885930 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2012 00:22:00.889298 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2013 00:22:00.892883 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
2014 00:22:00.899348 iDelay=209, Bit 5, Center 100 (-7 ~ 208) 216
2015 00:22:00.902448 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2016 00:22:00.906377 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2017 00:22:00.909252 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2018 00:22:00.912939 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2019 00:22:00.916017 iDelay=209, Bit 10, Center 88 (-23 ~ 200) 224
2020 00:22:00.923084 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2021 00:22:00.926076 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
2022 00:22:00.929623 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2023 00:22:00.932804 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2024 00:22:00.936389 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
2025 00:22:00.940055 ==
2026 00:22:00.942908 Dram Type= 6, Freq= 0, CH_1, rank 1
2027 00:22:00.946059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2028 00:22:00.946452 ==
2029 00:22:00.946749 DQS Delay:
2030 00:22:00.949387 DQS0 = 0, DQS1 = 0
2031 00:22:00.949778 DQM Delay:
2032 00:22:00.953414 DQM0 = 90, DQM1 = 83
2033 00:22:00.953887 DQ Delay:
2034 00:22:00.956219 DQ0 =96, DQ1 =84, DQ2 =80, DQ3 =88
2035 00:22:00.959801 DQ4 =92, DQ5 =100, DQ6 =96, DQ7 =88
2036 00:22:00.963118 DQ8 =68, DQ9 =72, DQ10 =88, DQ11 =80
2037 00:22:00.966266 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =92
2038 00:22:00.966658
2039 00:22:00.966956
2040 00:22:00.973088 [DQSOSCAuto] RK1, (LSB)MR18= 0x3f15, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
2041 00:22:00.976299 CH1 RK1: MR19=606, MR18=3F15
2042 00:22:00.983021 CH1_RK1: MR19=0x606, MR18=0x3F15, DQSOSC=393, MR23=63, INC=95, DEC=63
2043 00:22:00.986416 [RxdqsGatingPostProcess] freq 800
2044 00:22:00.989451 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2045 00:22:00.993025 Pre-setting of DQS Precalculation
2046 00:22:00.999675 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2047 00:22:01.006362 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2048 00:22:01.012808 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2049 00:22:01.013264
2050 00:22:01.013573
2051 00:22:01.016427 [Calibration Summary] 1600 Mbps
2052 00:22:01.016846 CH 0, Rank 0
2053 00:22:01.019750 SW Impedance : PASS
2054 00:22:01.023191 DUTY Scan : NO K
2055 00:22:01.023586 ZQ Calibration : PASS
2056 00:22:01.026879 Jitter Meter : NO K
2057 00:22:01.030115 CBT Training : PASS
2058 00:22:01.030591 Write leveling : PASS
2059 00:22:01.032959 RX DQS gating : PASS
2060 00:22:01.036537 RX DQ/DQS(RDDQC) : PASS
2061 00:22:01.036976 TX DQ/DQS : PASS
2062 00:22:01.039492 RX DATLAT : PASS
2063 00:22:01.039827 RX DQ/DQS(Engine): PASS
2064 00:22:01.043062 TX OE : NO K
2065 00:22:01.043456 All Pass.
2066 00:22:01.043758
2067 00:22:01.046412 CH 0, Rank 1
2068 00:22:01.046802 SW Impedance : PASS
2069 00:22:01.049736 DUTY Scan : NO K
2070 00:22:01.053262 ZQ Calibration : PASS
2071 00:22:01.053649 Jitter Meter : NO K
2072 00:22:01.057039 CBT Training : PASS
2073 00:22:01.059706 Write leveling : PASS
2074 00:22:01.060098 RX DQS gating : PASS
2075 00:22:01.063171 RX DQ/DQS(RDDQC) : PASS
2076 00:22:01.066720 TX DQ/DQS : PASS
2077 00:22:01.067108 RX DATLAT : PASS
2078 00:22:01.070641 RX DQ/DQS(Engine): PASS
2079 00:22:01.073620 TX OE : NO K
2080 00:22:01.074097 All Pass.
2081 00:22:01.074396
2082 00:22:01.074673 CH 1, Rank 0
2083 00:22:01.076584 SW Impedance : PASS
2084 00:22:01.080046 DUTY Scan : NO K
2085 00:22:01.080531 ZQ Calibration : PASS
2086 00:22:01.083883 Jitter Meter : NO K
2087 00:22:01.084365 CBT Training : PASS
2088 00:22:01.086724 Write leveling : PASS
2089 00:22:01.090080 RX DQS gating : PASS
2090 00:22:01.090555 RX DQ/DQS(RDDQC) : PASS
2091 00:22:01.093306 TX DQ/DQS : PASS
2092 00:22:01.097169 RX DATLAT : PASS
2093 00:22:01.097648 RX DQ/DQS(Engine): PASS
2094 00:22:01.100595 TX OE : NO K
2095 00:22:01.101119 All Pass.
2096 00:22:01.101427
2097 00:22:01.103307 CH 1, Rank 1
2098 00:22:01.103764 SW Impedance : PASS
2099 00:22:01.107069 DUTY Scan : NO K
2100 00:22:01.110362 ZQ Calibration : PASS
2101 00:22:01.110845 Jitter Meter : NO K
2102 00:22:01.113597 CBT Training : PASS
2103 00:22:01.116876 Write leveling : PASS
2104 00:22:01.117350 RX DQS gating : PASS
2105 00:22:01.120295 RX DQ/DQS(RDDQC) : PASS
2106 00:22:01.123795 TX DQ/DQS : PASS
2107 00:22:01.124316 RX DATLAT : PASS
2108 00:22:01.126709 RX DQ/DQS(Engine): PASS
2109 00:22:01.127219 TX OE : NO K
2110 00:22:01.130358 All Pass.
2111 00:22:01.130830
2112 00:22:01.131135 DramC Write-DBI off
2113 00:22:01.133549 PER_BANK_REFRESH: Hybrid Mode
2114 00:22:01.137112 TX_TRACKING: ON
2115 00:22:01.139841 [GetDramInforAfterCalByMRR] Vendor 6.
2116 00:22:01.143588 [GetDramInforAfterCalByMRR] Revision 606.
2117 00:22:01.147053 [GetDramInforAfterCalByMRR] Revision 2 0.
2118 00:22:01.147531 MR0 0x3b3b
2119 00:22:01.147836 MR8 0x5151
2120 00:22:01.153433 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2121 00:22:01.153912
2122 00:22:01.154243 MR0 0x3b3b
2123 00:22:01.154534 MR8 0x5151
2124 00:22:01.157057 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2125 00:22:01.157544
2126 00:22:01.166703 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2127 00:22:01.170313 [FAST_K] Save calibration result to emmc
2128 00:22:01.174006 [FAST_K] Save calibration result to emmc
2129 00:22:01.176878 dram_init: config_dvfs: 1
2130 00:22:01.180209 dramc_set_vcore_voltage set vcore to 662500
2131 00:22:01.183862 Read voltage for 1200, 2
2132 00:22:01.184337 Vio18 = 0
2133 00:22:01.184640 Vcore = 662500
2134 00:22:01.187119 Vdram = 0
2135 00:22:01.187663 Vddq = 0
2136 00:22:01.187977 Vmddr = 0
2137 00:22:01.193765 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2138 00:22:01.197167 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2139 00:22:01.200393 MEM_TYPE=3, freq_sel=15
2140 00:22:01.204079 sv_algorithm_assistance_LP4_1600
2141 00:22:01.206980 ============ PULL DRAM RESETB DOWN ============
2142 00:22:01.210392 ========== PULL DRAM RESETB DOWN end =========
2143 00:22:01.217094 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2144 00:22:01.220233 ===================================
2145 00:22:01.220752 LPDDR4 DRAM CONFIGURATION
2146 00:22:01.223510 ===================================
2147 00:22:01.226968 EX_ROW_EN[0] = 0x0
2148 00:22:01.230556 EX_ROW_EN[1] = 0x0
2149 00:22:01.231035 LP4Y_EN = 0x0
2150 00:22:01.233475 WORK_FSP = 0x0
2151 00:22:01.233866 WL = 0x4
2152 00:22:01.237092 RL = 0x4
2153 00:22:01.237570 BL = 0x2
2154 00:22:01.240852 RPST = 0x0
2155 00:22:01.241329 RD_PRE = 0x0
2156 00:22:01.243945 WR_PRE = 0x1
2157 00:22:01.244420 WR_PST = 0x0
2158 00:22:01.247390 DBI_WR = 0x0
2159 00:22:01.247867 DBI_RD = 0x0
2160 00:22:01.250269 OTF = 0x1
2161 00:22:01.254142 ===================================
2162 00:22:01.257245 ===================================
2163 00:22:01.257723 ANA top config
2164 00:22:01.260679 ===================================
2165 00:22:01.263599 DLL_ASYNC_EN = 0
2166 00:22:01.267034 ALL_SLAVE_EN = 0
2167 00:22:01.267430 NEW_RANK_MODE = 1
2168 00:22:01.270866 DLL_IDLE_MODE = 1
2169 00:22:01.273714 LP45_APHY_COMB_EN = 1
2170 00:22:01.277167 TX_ODT_DIS = 1
2171 00:22:01.280629 NEW_8X_MODE = 1
2172 00:22:01.284349 ===================================
2173 00:22:01.284972 ===================================
2174 00:22:01.286973 data_rate = 2400
2175 00:22:01.290497 CKR = 1
2176 00:22:01.293798 DQ_P2S_RATIO = 8
2177 00:22:01.297267 ===================================
2178 00:22:01.300548 CA_P2S_RATIO = 8
2179 00:22:01.304034 DQ_CA_OPEN = 0
2180 00:22:01.307021 DQ_SEMI_OPEN = 0
2181 00:22:01.307410 CA_SEMI_OPEN = 0
2182 00:22:01.310830 CA_FULL_RATE = 0
2183 00:22:01.313881 DQ_CKDIV4_EN = 0
2184 00:22:01.317020 CA_CKDIV4_EN = 0
2185 00:22:01.320844 CA_PREDIV_EN = 0
2186 00:22:01.324399 PH8_DLY = 17
2187 00:22:01.324907 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2188 00:22:01.326937 DQ_AAMCK_DIV = 4
2189 00:22:01.330752 CA_AAMCK_DIV = 4
2190 00:22:01.333832 CA_ADMCK_DIV = 4
2191 00:22:01.337338 DQ_TRACK_CA_EN = 0
2192 00:22:01.340497 CA_PICK = 1200
2193 00:22:01.341024 CA_MCKIO = 1200
2194 00:22:01.343837 MCKIO_SEMI = 0
2195 00:22:01.347132 PLL_FREQ = 2366
2196 00:22:01.350750 DQ_UI_PI_RATIO = 32
2197 00:22:01.354452 CA_UI_PI_RATIO = 0
2198 00:22:01.357540 ===================================
2199 00:22:01.360880 ===================================
2200 00:22:01.363954 memory_type:LPDDR4
2201 00:22:01.364432 GP_NUM : 10
2202 00:22:01.367164 SRAM_EN : 1
2203 00:22:01.367613 MD32_EN : 0
2204 00:22:01.370608 ===================================
2205 00:22:01.374314 [ANA_INIT] >>>>>>>>>>>>>>
2206 00:22:01.377702 <<<<<< [CONFIGURE PHASE]: ANA_TX
2207 00:22:01.380514 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2208 00:22:01.384466 ===================================
2209 00:22:01.387198 data_rate = 2400,PCW = 0X5b00
2210 00:22:01.390686 ===================================
2211 00:22:01.394455 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2212 00:22:01.397409 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2213 00:22:01.403984 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2214 00:22:01.407237 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2215 00:22:01.411163 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2216 00:22:01.414007 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2217 00:22:01.417432 [ANA_INIT] flow start
2218 00:22:01.421173 [ANA_INIT] PLL >>>>>>>>
2219 00:22:01.421655 [ANA_INIT] PLL <<<<<<<<
2220 00:22:01.424643 [ANA_INIT] MIDPI >>>>>>>>
2221 00:22:01.427785 [ANA_INIT] MIDPI <<<<<<<<
2222 00:22:01.428173 [ANA_INIT] DLL >>>>>>>>
2223 00:22:01.430748 [ANA_INIT] DLL <<<<<<<<
2224 00:22:01.434166 [ANA_INIT] flow end
2225 00:22:01.437859 ============ LP4 DIFF to SE enter ============
2226 00:22:01.441563 ============ LP4 DIFF to SE exit ============
2227 00:22:01.444534 [ANA_INIT] <<<<<<<<<<<<<
2228 00:22:01.448056 [Flow] Enable top DCM control >>>>>
2229 00:22:01.451611 [Flow] Enable top DCM control <<<<<
2230 00:22:01.454587 Enable DLL master slave shuffle
2231 00:22:01.458214 ==============================================================
2232 00:22:01.461561 Gating Mode config
2233 00:22:01.467852 ==============================================================
2234 00:22:01.468331 Config description:
2235 00:22:01.477876 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2236 00:22:01.484973 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2237 00:22:01.488529 SELPH_MODE 0: By rank 1: By Phase
2238 00:22:01.494932 ==============================================================
2239 00:22:01.498175 GAT_TRACK_EN = 1
2240 00:22:01.501466 RX_GATING_MODE = 2
2241 00:22:01.504766 RX_GATING_TRACK_MODE = 2
2242 00:22:01.508100 SELPH_MODE = 1
2243 00:22:01.511454 PICG_EARLY_EN = 1
2244 00:22:01.511844 VALID_LAT_VALUE = 1
2245 00:22:01.517738 ==============================================================
2246 00:22:01.521527 Enter into Gating configuration >>>>
2247 00:22:01.525077 Exit from Gating configuration <<<<
2248 00:22:01.528011 Enter into DVFS_PRE_config >>>>>
2249 00:22:01.538312 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2250 00:22:01.541828 Exit from DVFS_PRE_config <<<<<
2251 00:22:01.545356 Enter into PICG configuration >>>>
2252 00:22:01.548425 Exit from PICG configuration <<<<
2253 00:22:01.551871 [RX_INPUT] configuration >>>>>
2254 00:22:01.555425 [RX_INPUT] configuration <<<<<
2255 00:22:01.558847 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2256 00:22:01.565183 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2257 00:22:01.571823 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2258 00:22:01.578639 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2259 00:22:01.581688 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2260 00:22:01.589002 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2261 00:22:01.592490 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2262 00:22:01.598968 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2263 00:22:01.602134 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2264 00:22:01.605525 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2265 00:22:01.608460 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2266 00:22:01.615248 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2267 00:22:01.618938 ===================================
2268 00:22:01.619416 LPDDR4 DRAM CONFIGURATION
2269 00:22:01.622063 ===================================
2270 00:22:01.625649 EX_ROW_EN[0] = 0x0
2271 00:22:01.628804 EX_ROW_EN[1] = 0x0
2272 00:22:01.629195 LP4Y_EN = 0x0
2273 00:22:01.632135 WORK_FSP = 0x0
2274 00:22:01.632613 WL = 0x4
2275 00:22:01.635818 RL = 0x4
2276 00:22:01.636291 BL = 0x2
2277 00:22:01.638608 RPST = 0x0
2278 00:22:01.638997 RD_PRE = 0x0
2279 00:22:01.642010 WR_PRE = 0x1
2280 00:22:01.642396 WR_PST = 0x0
2281 00:22:01.645655 DBI_WR = 0x0
2282 00:22:01.646139 DBI_RD = 0x0
2283 00:22:01.648648 OTF = 0x1
2284 00:22:01.652273 ===================================
2285 00:22:01.655961 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2286 00:22:01.658904 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2287 00:22:01.665963 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2288 00:22:01.668797 ===================================
2289 00:22:01.669189 LPDDR4 DRAM CONFIGURATION
2290 00:22:01.672398 ===================================
2291 00:22:01.675733 EX_ROW_EN[0] = 0x10
2292 00:22:01.676206 EX_ROW_EN[1] = 0x0
2293 00:22:01.678788 LP4Y_EN = 0x0
2294 00:22:01.679178 WORK_FSP = 0x0
2295 00:22:01.681869 WL = 0x4
2296 00:22:01.685585 RL = 0x4
2297 00:22:01.685979 BL = 0x2
2298 00:22:01.688969 RPST = 0x0
2299 00:22:01.689363 RD_PRE = 0x0
2300 00:22:01.692700 WR_PRE = 0x1
2301 00:22:01.693245 WR_PST = 0x0
2302 00:22:01.695644 DBI_WR = 0x0
2303 00:22:01.696122 DBI_RD = 0x0
2304 00:22:01.698768 OTF = 0x1
2305 00:22:01.702268 ===================================
2306 00:22:01.705103 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2307 00:22:01.708651 ==
2308 00:22:01.712136 Dram Type= 6, Freq= 0, CH_0, rank 0
2309 00:22:01.715229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2310 00:22:01.715622 ==
2311 00:22:01.719079 [Duty_Offset_Calibration]
2312 00:22:01.719470 B0:2 B1:0 CA:1
2313 00:22:01.719770
2314 00:22:01.722140 [DutyScan_Calibration_Flow] k_type=0
2315 00:22:01.730958
2316 00:22:01.731431 ==CLK 0==
2317 00:22:01.734312 Final CLK duty delay cell = -4
2318 00:22:01.737548 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2319 00:22:01.741434 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2320 00:22:01.741914 [-4] AVG Duty = 4953%(X100)
2321 00:22:01.744544
2322 00:22:01.747687 CH0 CLK Duty spec in!! Max-Min= 156%
2323 00:22:01.750859 [DutyScan_Calibration_Flow] ====Done====
2324 00:22:01.751328
2325 00:22:01.754268 [DutyScan_Calibration_Flow] k_type=1
2326 00:22:01.769862
2327 00:22:01.770342 ==DQS 0 ==
2328 00:22:01.773211 Final DQS duty delay cell = 0
2329 00:22:01.776595 [0] MAX Duty = 5187%(X100), DQS PI = 30
2330 00:22:01.780086 [0] MIN Duty = 4938%(X100), DQS PI = 0
2331 00:22:01.780569 [0] AVG Duty = 5062%(X100)
2332 00:22:01.781144
2333 00:22:01.783100 ==DQS 1 ==
2334 00:22:01.786943 Final DQS duty delay cell = -4
2335 00:22:01.789727 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2336 00:22:01.793282 [-4] MIN Duty = 4907%(X100), DQS PI = 10
2337 00:22:01.796689 [-4] AVG Duty = 5015%(X100)
2338 00:22:01.797125
2339 00:22:01.800066 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2340 00:22:01.800538
2341 00:22:01.803305 CH0 DQS 1 Duty spec in!! Max-Min= 217%
2342 00:22:01.806772 [DutyScan_Calibration_Flow] ====Done====
2343 00:22:01.807248
2344 00:22:01.810215 [DutyScan_Calibration_Flow] k_type=3
2345 00:22:01.826702
2346 00:22:01.827183 ==DQM 0 ==
2347 00:22:01.830124 Final DQM duty delay cell = 0
2348 00:22:01.833601 [0] MAX Duty = 5062%(X100), DQS PI = 24
2349 00:22:01.837041 [0] MIN Duty = 4813%(X100), DQS PI = 0
2350 00:22:01.837523 [0] AVG Duty = 4937%(X100)
2351 00:22:01.840524
2352 00:22:01.841026 ==DQM 1 ==
2353 00:22:01.843484 Final DQM duty delay cell = 0
2354 00:22:01.846653 [0] MAX Duty = 5187%(X100), DQS PI = 48
2355 00:22:01.849933 [0] MIN Duty = 4969%(X100), DQS PI = 24
2356 00:22:01.850407 [0] AVG Duty = 5078%(X100)
2357 00:22:01.853592
2358 00:22:01.856881 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2359 00:22:01.857356
2360 00:22:01.860531 CH0 DQM 1 Duty spec in!! Max-Min= 218%
2361 00:22:01.863263 [DutyScan_Calibration_Flow] ====Done====
2362 00:22:01.863746
2363 00:22:01.866819 [DutyScan_Calibration_Flow] k_type=2
2364 00:22:01.883694
2365 00:22:01.884162 ==DQ 0 ==
2366 00:22:01.887474 Final DQ duty delay cell = 0
2367 00:22:01.890315 [0] MAX Duty = 5156%(X100), DQS PI = 34
2368 00:22:01.893574 [0] MIN Duty = 5000%(X100), DQS PI = 14
2369 00:22:01.893962 [0] AVG Duty = 5078%(X100)
2370 00:22:01.897018
2371 00:22:01.897402 ==DQ 1 ==
2372 00:22:01.900207 Final DQ duty delay cell = 4
2373 00:22:01.903815 [4] MAX Duty = 5093%(X100), DQS PI = 4
2374 00:22:01.907487 [4] MIN Duty = 5031%(X100), DQS PI = 0
2375 00:22:01.907960 [4] AVG Duty = 5062%(X100)
2376 00:22:01.908262
2377 00:22:01.911091 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2378 00:22:01.911563
2379 00:22:01.914091 CH0 DQ 1 Duty spec in!! Max-Min= 62%
2380 00:22:01.920663 [DutyScan_Calibration_Flow] ====Done====
2381 00:22:01.921161 ==
2382 00:22:01.923854 Dram Type= 6, Freq= 0, CH_1, rank 0
2383 00:22:01.927555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2384 00:22:01.928041 ==
2385 00:22:01.930997 [Duty_Offset_Calibration]
2386 00:22:01.931466 B0:0 B1:-1 CA:2
2387 00:22:01.931766
2388 00:22:01.934502 [DutyScan_Calibration_Flow] k_type=0
2389 00:22:01.943941
2390 00:22:01.944409 ==CLK 0==
2391 00:22:01.947436 Final CLK duty delay cell = 0
2392 00:22:01.950440 [0] MAX Duty = 5156%(X100), DQS PI = 8
2393 00:22:01.953468 [0] MIN Duty = 4938%(X100), DQS PI = 44
2394 00:22:01.953859 [0] AVG Duty = 5047%(X100)
2395 00:22:01.954165
2396 00:22:01.957245 CH1 CLK Duty spec in!! Max-Min= 218%
2397 00:22:01.964129 [DutyScan_Calibration_Flow] ====Done====
2398 00:22:01.964600
2399 00:22:01.967129 [DutyScan_Calibration_Flow] k_type=1
2400 00:22:01.982781
2401 00:22:01.983307 ==DQS 0 ==
2402 00:22:01.986081 Final DQS duty delay cell = 0
2403 00:22:01.989794 [0] MAX Duty = 5093%(X100), DQS PI = 24
2404 00:22:01.992874 [0] MIN Duty = 4969%(X100), DQS PI = 0
2405 00:22:01.993339 [0] AVG Duty = 5031%(X100)
2406 00:22:01.996608
2407 00:22:01.997121 ==DQS 1 ==
2408 00:22:01.999667 Final DQS duty delay cell = 0
2409 00:22:02.003133 [0] MAX Duty = 5156%(X100), DQS PI = 0
2410 00:22:02.006132 [0] MIN Duty = 4875%(X100), DQS PI = 34
2411 00:22:02.006519 [0] AVG Duty = 5015%(X100)
2412 00:22:02.009461
2413 00:22:02.012800 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2414 00:22:02.013315
2415 00:22:02.016378 CH1 DQS 1 Duty spec in!! Max-Min= 281%
2416 00:22:02.019904 [DutyScan_Calibration_Flow] ====Done====
2417 00:22:02.020429
2418 00:22:02.022850 [DutyScan_Calibration_Flow] k_type=3
2419 00:22:02.039126
2420 00:22:02.039205 ==DQM 0 ==
2421 00:22:02.042158 Final DQM duty delay cell = 4
2422 00:22:02.045692 [4] MAX Duty = 5093%(X100), DQS PI = 22
2423 00:22:02.048943 [4] MIN Duty = 4907%(X100), DQS PI = 46
2424 00:22:02.049039 [4] AVG Duty = 5000%(X100)
2425 00:22:02.052287
2426 00:22:02.052362 ==DQM 1 ==
2427 00:22:02.055432 Final DQM duty delay cell = -4
2428 00:22:02.059143 [-4] MAX Duty = 5031%(X100), DQS PI = 62
2429 00:22:02.062749 [-4] MIN Duty = 4751%(X100), DQS PI = 36
2430 00:22:02.066470 [-4] AVG Duty = 4891%(X100)
2431 00:22:02.066941
2432 00:22:02.069203 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2433 00:22:02.069591
2434 00:22:02.072933 CH1 DQM 1 Duty spec in!! Max-Min= 280%
2435 00:22:02.076524 [DutyScan_Calibration_Flow] ====Done====
2436 00:22:02.077031
2437 00:22:02.079494 [DutyScan_Calibration_Flow] k_type=2
2438 00:22:02.096460
2439 00:22:02.096989 ==DQ 0 ==
2440 00:22:02.099951 Final DQ duty delay cell = 0
2441 00:22:02.102992 [0] MAX Duty = 5062%(X100), DQS PI = 20
2442 00:22:02.106390 [0] MIN Duty = 4938%(X100), DQS PI = 0
2443 00:22:02.106780 [0] AVG Duty = 5000%(X100)
2444 00:22:02.107086
2445 00:22:02.110020 ==DQ 1 ==
2446 00:22:02.113441 Final DQ duty delay cell = 0
2447 00:22:02.116504 [0] MAX Duty = 5031%(X100), DQS PI = 2
2448 00:22:02.120088 [0] MIN Duty = 4813%(X100), DQS PI = 34
2449 00:22:02.120560 [0] AVG Duty = 4922%(X100)
2450 00:22:02.120917
2451 00:22:02.123730 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2452 00:22:02.124200
2453 00:22:02.126132 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2454 00:22:02.132873 [DutyScan_Calibration_Flow] ====Done====
2455 00:22:02.136244 nWR fixed to 30
2456 00:22:02.136660 [ModeRegInit_LP4] CH0 RK0
2457 00:22:02.139744 [ModeRegInit_LP4] CH0 RK1
2458 00:22:02.143225 [ModeRegInit_LP4] CH1 RK0
2459 00:22:02.143699 [ModeRegInit_LP4] CH1 RK1
2460 00:22:02.146680 match AC timing 7
2461 00:22:02.150320 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2462 00:22:02.153243 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2463 00:22:02.160113 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2464 00:22:02.163192 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2465 00:22:02.169726 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2466 00:22:02.170187 ==
2467 00:22:02.173530 Dram Type= 6, Freq= 0, CH_0, rank 0
2468 00:22:02.177018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2469 00:22:02.177498 ==
2470 00:22:02.183584 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2471 00:22:02.186612 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2472 00:22:02.196221 [CA 0] Center 38 (8~69) winsize 62
2473 00:22:02.199929 [CA 1] Center 38 (7~69) winsize 63
2474 00:22:02.202580 [CA 2] Center 35 (5~66) winsize 62
2475 00:22:02.205874 [CA 3] Center 35 (5~66) winsize 62
2476 00:22:02.209394 [CA 4] Center 34 (4~65) winsize 62
2477 00:22:02.212998 [CA 5] Center 33 (3~63) winsize 61
2478 00:22:02.213387
2479 00:22:02.216315 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2480 00:22:02.216721
2481 00:22:02.219575 [CATrainingPosCal] consider 1 rank data
2482 00:22:02.222742 u2DelayCellTimex100 = 270/100 ps
2483 00:22:02.226368 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2484 00:22:02.229768 CA1 delay=38 (7~69),Diff = 5 PI (24 cell)
2485 00:22:02.236418 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2486 00:22:02.239519 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2487 00:22:02.243341 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2488 00:22:02.246059 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2489 00:22:02.246451
2490 00:22:02.249698 CA PerBit enable=1, Macro0, CA PI delay=33
2491 00:22:02.250170
2492 00:22:02.253245 [CBTSetCACLKResult] CA Dly = 33
2493 00:22:02.253724 CS Dly: 6 (0~37)
2494 00:22:02.254028 ==
2495 00:22:02.256130 Dram Type= 6, Freq= 0, CH_0, rank 1
2496 00:22:02.263276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2497 00:22:02.263740 ==
2498 00:22:02.266072 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2499 00:22:02.272858 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2500 00:22:02.282014 [CA 0] Center 39 (8~70) winsize 63
2501 00:22:02.285303 [CA 1] Center 38 (8~69) winsize 62
2502 00:22:02.288593 [CA 2] Center 35 (5~66) winsize 62
2503 00:22:02.291585 [CA 3] Center 35 (5~66) winsize 62
2504 00:22:02.295523 [CA 4] Center 34 (4~65) winsize 62
2505 00:22:02.298691 [CA 5] Center 34 (4~64) winsize 61
2506 00:22:02.299163
2507 00:22:02.301774 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2508 00:22:02.302165
2509 00:22:02.305217 [CATrainingPosCal] consider 2 rank data
2510 00:22:02.308863 u2DelayCellTimex100 = 270/100 ps
2511 00:22:02.311724 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2512 00:22:02.315107 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2513 00:22:02.322049 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2514 00:22:02.325662 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2515 00:22:02.329013 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2516 00:22:02.331661 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2517 00:22:02.332050
2518 00:22:02.335509 CA PerBit enable=1, Macro0, CA PI delay=33
2519 00:22:02.335982
2520 00:22:02.339180 [CBTSetCACLKResult] CA Dly = 33
2521 00:22:02.339665 CS Dly: 7 (0~39)
2522 00:22:02.339970
2523 00:22:02.341655 ----->DramcWriteLeveling(PI) begin...
2524 00:22:02.345395 ==
2525 00:22:02.348473 Dram Type= 6, Freq= 0, CH_0, rank 0
2526 00:22:02.351965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2527 00:22:02.352448 ==
2528 00:22:02.355243 Write leveling (Byte 0): 34 => 34
2529 00:22:02.358547 Write leveling (Byte 1): 32 => 32
2530 00:22:02.361943 DramcWriteLeveling(PI) end<-----
2531 00:22:02.362417
2532 00:22:02.362718 ==
2533 00:22:02.364909 Dram Type= 6, Freq= 0, CH_0, rank 0
2534 00:22:02.368452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2535 00:22:02.368983 ==
2536 00:22:02.371909 [Gating] SW mode calibration
2537 00:22:02.378507 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2538 00:22:02.381651 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2539 00:22:02.389031 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2540 00:22:02.391902 0 15 4 | B1->B0 | 2f2e 3434 | 1 1 | (0 0) (1 1)
2541 00:22:02.395337 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2542 00:22:02.402019 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2543 00:22:02.405515 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2544 00:22:02.408978 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2545 00:22:02.415275 0 15 24 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
2546 00:22:02.419094 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
2547 00:22:02.422587 1 0 0 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (0 0)
2548 00:22:02.429094 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2549 00:22:02.432458 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2550 00:22:02.435877 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2551 00:22:02.442454 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2552 00:22:02.445306 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2553 00:22:02.448695 1 0 24 | B1->B0 | 2323 3333 | 0 1 | (0 0) (0 0)
2554 00:22:02.452555 1 0 28 | B1->B0 | 2525 4646 | 1 0 | (0 0) (0 0)
2555 00:22:02.459052 1 1 0 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
2556 00:22:02.462357 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2557 00:22:02.465182 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2558 00:22:02.472182 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2559 00:22:02.475788 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2560 00:22:02.479203 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2561 00:22:02.485502 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2562 00:22:02.488849 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2563 00:22:02.492143 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2564 00:22:02.499050 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 00:22:02.502292 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 00:22:02.505487 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 00:22:02.512806 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 00:22:02.515377 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 00:22:02.519065 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 00:22:02.525704 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 00:22:02.529087 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 00:22:02.532530 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 00:22:02.535759 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 00:22:02.542524 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2575 00:22:02.545907 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2576 00:22:02.549112 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2577 00:22:02.555558 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2578 00:22:02.559053 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2579 00:22:02.562728 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2580 00:22:02.565756 Total UI for P1: 0, mck2ui 16
2581 00:22:02.569128 best dqsien dly found for B0: ( 1, 3, 28)
2582 00:22:02.572881 Total UI for P1: 0, mck2ui 16
2583 00:22:02.575838 best dqsien dly found for B1: ( 1, 3, 28)
2584 00:22:02.579248 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2585 00:22:02.582763 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2586 00:22:02.583236
2587 00:22:02.589443 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2588 00:22:02.592588 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2589 00:22:02.593097 [Gating] SW calibration Done
2590 00:22:02.596131 ==
2591 00:22:02.596602 Dram Type= 6, Freq= 0, CH_0, rank 0
2592 00:22:02.602550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2593 00:22:02.603023 ==
2594 00:22:02.603403 RX Vref Scan: 0
2595 00:22:02.603694
2596 00:22:02.605766 RX Vref 0 -> 0, step: 1
2597 00:22:02.606161
2598 00:22:02.609254 RX Delay -40 -> 252, step: 8
2599 00:22:02.612584 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
2600 00:22:02.615793 iDelay=208, Bit 1, Center 127 (56 ~ 199) 144
2601 00:22:02.619336 iDelay=208, Bit 2, Center 119 (48 ~ 191) 144
2602 00:22:02.625958 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
2603 00:22:02.629137 iDelay=208, Bit 4, Center 127 (56 ~ 199) 144
2604 00:22:02.633093 iDelay=208, Bit 5, Center 115 (48 ~ 183) 136
2605 00:22:02.636029 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
2606 00:22:02.639269 iDelay=208, Bit 7, Center 127 (56 ~ 199) 144
2607 00:22:02.642975 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
2608 00:22:02.649024 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
2609 00:22:02.653031 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
2610 00:22:02.656368 iDelay=208, Bit 11, Center 107 (40 ~ 175) 136
2611 00:22:02.659464 iDelay=208, Bit 12, Center 115 (48 ~ 183) 136
2612 00:22:02.662787 iDelay=208, Bit 13, Center 115 (48 ~ 183) 136
2613 00:22:02.669299 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
2614 00:22:02.672869 iDelay=208, Bit 15, Center 115 (48 ~ 183) 136
2615 00:22:02.673370 ==
2616 00:22:02.676099 Dram Type= 6, Freq= 0, CH_0, rank 0
2617 00:22:02.679290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2618 00:22:02.679768 ==
2619 00:22:02.682785 DQS Delay:
2620 00:22:02.683251 DQS0 = 0, DQS1 = 0
2621 00:22:02.683557 DQM Delay:
2622 00:22:02.685925 DQM0 = 123, DQM1 = 110
2623 00:22:02.686319 DQ Delay:
2624 00:22:02.689465 DQ0 =123, DQ1 =127, DQ2 =119, DQ3 =119
2625 00:22:02.693014 DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =127
2626 00:22:02.696017 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2627 00:22:02.703146 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2628 00:22:02.703625
2629 00:22:02.703930
2630 00:22:02.704204 ==
2631 00:22:02.706470 Dram Type= 6, Freq= 0, CH_0, rank 0
2632 00:22:02.709193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2633 00:22:02.709669 ==
2634 00:22:02.709976
2635 00:22:02.710252
2636 00:22:02.712733 TX Vref Scan disable
2637 00:22:02.713132 == TX Byte 0 ==
2638 00:22:02.719738 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2639 00:22:02.722863 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2640 00:22:02.723261 == TX Byte 1 ==
2641 00:22:02.729403 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2642 00:22:02.733321 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2643 00:22:02.733813 ==
2644 00:22:02.736548 Dram Type= 6, Freq= 0, CH_0, rank 0
2645 00:22:02.739464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2646 00:22:02.739950 ==
2647 00:22:02.752014 TX Vref=22, minBit 4, minWin=24, winSum=408
2648 00:22:02.755477 TX Vref=24, minBit 1, minWin=24, winSum=413
2649 00:22:02.759080 TX Vref=26, minBit 7, minWin=24, winSum=417
2650 00:22:02.762541 TX Vref=28, minBit 1, minWin=25, winSum=421
2651 00:22:02.765515 TX Vref=30, minBit 7, minWin=25, winSum=422
2652 00:22:02.768811 TX Vref=32, minBit 1, minWin=25, winSum=416
2653 00:22:02.775459 [TxChooseVref] Worse bit 7, Min win 25, Win sum 422, Final Vref 30
2654 00:22:02.775940
2655 00:22:02.779034 Final TX Range 1 Vref 30
2656 00:22:02.779511
2657 00:22:02.779912 ==
2658 00:22:02.782377 Dram Type= 6, Freq= 0, CH_0, rank 0
2659 00:22:02.785553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2660 00:22:02.786039 ==
2661 00:22:02.786518
2662 00:22:02.786964
2663 00:22:02.788568 TX Vref Scan disable
2664 00:22:02.792408 == TX Byte 0 ==
2665 00:22:02.795438 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2666 00:22:02.798606 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2667 00:22:02.802471 == TX Byte 1 ==
2668 00:22:02.805652 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2669 00:22:02.808516 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2670 00:22:02.808941
2671 00:22:02.812417 [DATLAT]
2672 00:22:02.812921 Freq=1200, CH0 RK0
2673 00:22:02.813232
2674 00:22:02.815413 DATLAT Default: 0xd
2675 00:22:02.815809 0, 0xFFFF, sum = 0
2676 00:22:02.819188 1, 0xFFFF, sum = 0
2677 00:22:02.819661 2, 0xFFFF, sum = 0
2678 00:22:02.822593 3, 0xFFFF, sum = 0
2679 00:22:02.823066 4, 0xFFFF, sum = 0
2680 00:22:02.825415 5, 0xFFFF, sum = 0
2681 00:22:02.825812 6, 0xFFFF, sum = 0
2682 00:22:02.829323 7, 0xFFFF, sum = 0
2683 00:22:02.829794 8, 0xFFFF, sum = 0
2684 00:22:02.832234 9, 0xFFFF, sum = 0
2685 00:22:02.832736 10, 0xFFFF, sum = 0
2686 00:22:02.835995 11, 0xFFFF, sum = 0
2687 00:22:02.836474 12, 0x0, sum = 1
2688 00:22:02.839002 13, 0x0, sum = 2
2689 00:22:02.839399 14, 0x0, sum = 3
2690 00:22:02.842573 15, 0x0, sum = 4
2691 00:22:02.843042 best_step = 13
2692 00:22:02.843346
2693 00:22:02.843622 ==
2694 00:22:02.845398 Dram Type= 6, Freq= 0, CH_0, rank 0
2695 00:22:02.852153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2696 00:22:02.852628 ==
2697 00:22:02.853026 RX Vref Scan: 1
2698 00:22:02.853379
2699 00:22:02.855551 Set Vref Range= 32 -> 127
2700 00:22:02.855948
2701 00:22:02.859011 RX Vref 32 -> 127, step: 1
2702 00:22:02.859509
2703 00:22:02.859829 RX Delay -13 -> 252, step: 4
2704 00:22:02.862374
2705 00:22:02.862865 Set Vref, RX VrefLevel [Byte0]: 32
2706 00:22:02.865684 [Byte1]: 32
2707 00:22:02.870182
2708 00:22:02.870669 Set Vref, RX VrefLevel [Byte0]: 33
2709 00:22:02.873402 [Byte1]: 33
2710 00:22:02.878079
2711 00:22:02.878556 Set Vref, RX VrefLevel [Byte0]: 34
2712 00:22:02.881617 [Byte1]: 34
2713 00:22:02.885819
2714 00:22:02.886296 Set Vref, RX VrefLevel [Byte0]: 35
2715 00:22:02.889009 [Byte1]: 35
2716 00:22:02.893851
2717 00:22:02.894328 Set Vref, RX VrefLevel [Byte0]: 36
2718 00:22:02.896791 [Byte1]: 36
2719 00:22:02.901632
2720 00:22:02.902108 Set Vref, RX VrefLevel [Byte0]: 37
2721 00:22:02.904874 [Byte1]: 37
2722 00:22:02.909451
2723 00:22:02.909931 Set Vref, RX VrefLevel [Byte0]: 38
2724 00:22:02.913043 [Byte1]: 38
2725 00:22:02.917239
2726 00:22:02.917635 Set Vref, RX VrefLevel [Byte0]: 39
2727 00:22:02.921147 [Byte1]: 39
2728 00:22:02.925681
2729 00:22:02.926164 Set Vref, RX VrefLevel [Byte0]: 40
2730 00:22:02.928625 [Byte1]: 40
2731 00:22:02.933625
2732 00:22:02.934135 Set Vref, RX VrefLevel [Byte0]: 41
2733 00:22:02.936988 [Byte1]: 41
2734 00:22:02.941078
2735 00:22:02.941556 Set Vref, RX VrefLevel [Byte0]: 42
2736 00:22:02.945207 [Byte1]: 42
2737 00:22:02.949636
2738 00:22:02.950133 Set Vref, RX VrefLevel [Byte0]: 43
2739 00:22:02.952371 [Byte1]: 43
2740 00:22:02.956986
2741 00:22:02.957384 Set Vref, RX VrefLevel [Byte0]: 44
2742 00:22:02.960166 [Byte1]: 44
2743 00:22:02.964869
2744 00:22:02.965344 Set Vref, RX VrefLevel [Byte0]: 45
2745 00:22:02.968185 [Byte1]: 45
2746 00:22:02.972697
2747 00:22:02.973138 Set Vref, RX VrefLevel [Byte0]: 46
2748 00:22:02.976206 [Byte1]: 46
2749 00:22:02.980870
2750 00:22:02.981384 Set Vref, RX VrefLevel [Byte0]: 47
2751 00:22:02.984129 [Byte1]: 47
2752 00:22:02.988521
2753 00:22:02.989066 Set Vref, RX VrefLevel [Byte0]: 48
2754 00:22:02.992324 [Byte1]: 48
2755 00:22:02.996655
2756 00:22:02.997175 Set Vref, RX VrefLevel [Byte0]: 49
2757 00:22:02.999638 [Byte1]: 49
2758 00:22:03.004095
2759 00:22:03.004500 Set Vref, RX VrefLevel [Byte0]: 50
2760 00:22:03.007218 [Byte1]: 50
2761 00:22:03.012186
2762 00:22:03.012664 Set Vref, RX VrefLevel [Byte0]: 51
2763 00:22:03.015132 [Byte1]: 51
2764 00:22:03.020572
2765 00:22:03.021092 Set Vref, RX VrefLevel [Byte0]: 52
2766 00:22:03.023529 [Byte1]: 52
2767 00:22:03.028251
2768 00:22:03.028759 Set Vref, RX VrefLevel [Byte0]: 53
2769 00:22:03.031220 [Byte1]: 53
2770 00:22:03.036189
2771 00:22:03.036673 Set Vref, RX VrefLevel [Byte0]: 54
2772 00:22:03.039226 [Byte1]: 54
2773 00:22:03.043785
2774 00:22:03.044251 Set Vref, RX VrefLevel [Byte0]: 55
2775 00:22:03.046927 [Byte1]: 55
2776 00:22:03.051992
2777 00:22:03.052458 Set Vref, RX VrefLevel [Byte0]: 56
2778 00:22:03.054644 [Byte1]: 56
2779 00:22:03.059152
2780 00:22:03.059697 Set Vref, RX VrefLevel [Byte0]: 57
2781 00:22:03.062444 [Byte1]: 57
2782 00:22:03.067180
2783 00:22:03.067563 Set Vref, RX VrefLevel [Byte0]: 58
2784 00:22:03.070561 [Byte1]: 58
2785 00:22:03.075033
2786 00:22:03.075582 Set Vref, RX VrefLevel [Byte0]: 59
2787 00:22:03.078525 [Byte1]: 59
2788 00:22:03.082925
2789 00:22:03.083432 Set Vref, RX VrefLevel [Byte0]: 60
2790 00:22:03.086588 [Byte1]: 60
2791 00:22:03.090897
2792 00:22:03.091452 Set Vref, RX VrefLevel [Byte0]: 61
2793 00:22:03.094103 [Byte1]: 61
2794 00:22:03.098865
2795 00:22:03.099394 Set Vref, RX VrefLevel [Byte0]: 62
2796 00:22:03.102185 [Byte1]: 62
2797 00:22:03.106794
2798 00:22:03.107448 Set Vref, RX VrefLevel [Byte0]: 63
2799 00:22:03.109826 [Byte1]: 63
2800 00:22:03.114530
2801 00:22:03.114918 Set Vref, RX VrefLevel [Byte0]: 64
2802 00:22:03.117932 [Byte1]: 64
2803 00:22:03.122340
2804 00:22:03.122725 Set Vref, RX VrefLevel [Byte0]: 65
2805 00:22:03.125831 [Byte1]: 65
2806 00:22:03.130487
2807 00:22:03.130963 Set Vref, RX VrefLevel [Byte0]: 66
2808 00:22:03.133578 [Byte1]: 66
2809 00:22:03.138448
2810 00:22:03.138914 Set Vref, RX VrefLevel [Byte0]: 67
2811 00:22:03.141662 [Byte1]: 67
2812 00:22:03.146275
2813 00:22:03.146746 Set Vref, RX VrefLevel [Byte0]: 68
2814 00:22:03.149411 [Byte1]: 68
2815 00:22:03.154234
2816 00:22:03.154710 Set Vref, RX VrefLevel [Byte0]: 69
2817 00:22:03.157477 [Byte1]: 69
2818 00:22:03.162174
2819 00:22:03.162642 Final RX Vref Byte 0 = 59 to rank0
2820 00:22:03.165550 Final RX Vref Byte 1 = 50 to rank0
2821 00:22:03.168811 Final RX Vref Byte 0 = 59 to rank1
2822 00:22:03.172092 Final RX Vref Byte 1 = 50 to rank1==
2823 00:22:03.175553 Dram Type= 6, Freq= 0, CH_0, rank 0
2824 00:22:03.179060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2825 00:22:03.182290 ==
2826 00:22:03.182760 DQS Delay:
2827 00:22:03.183066 DQS0 = 0, DQS1 = 0
2828 00:22:03.185940 DQM Delay:
2829 00:22:03.186413 DQM0 = 123, DQM1 = 109
2830 00:22:03.188588 DQ Delay:
2831 00:22:03.192138 DQ0 =122, DQ1 =122, DQ2 =120, DQ3 =120
2832 00:22:03.196310 DQ4 =126, DQ5 =116, DQ6 =132, DQ7 =128
2833 00:22:03.198815 DQ8 =102, DQ9 =94, DQ10 =110, DQ11 =104
2834 00:22:03.202531 DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =116
2835 00:22:03.203003
2836 00:22:03.203303
2837 00:22:03.209121 [DQSOSCAuto] RK0, (LSB)MR18= 0xe0a, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 404 ps
2838 00:22:03.212341 CH0 RK0: MR19=404, MR18=E0A
2839 00:22:03.219025 CH0_RK0: MR19=0x404, MR18=0xE0A, DQSOSC=404, MR23=63, INC=40, DEC=26
2840 00:22:03.219499
2841 00:22:03.222018 ----->DramcWriteLeveling(PI) begin...
2842 00:22:03.222409 ==
2843 00:22:03.225558 Dram Type= 6, Freq= 0, CH_0, rank 1
2844 00:22:03.228881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2845 00:22:03.229274 ==
2846 00:22:03.232665 Write leveling (Byte 0): 36 => 36
2847 00:22:03.235713 Write leveling (Byte 1): 31 => 31
2848 00:22:03.239575 DramcWriteLeveling(PI) end<-----
2849 00:22:03.240042
2850 00:22:03.240342 ==
2851 00:22:03.242206 Dram Type= 6, Freq= 0, CH_0, rank 1
2852 00:22:03.245837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2853 00:22:03.246341 ==
2854 00:22:03.249028 [Gating] SW mode calibration
2855 00:22:03.255719 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2856 00:22:03.262741 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2857 00:22:03.265547 0 15 0 | B1->B0 | 3332 3434 | 1 1 | (1 1) (1 1)
2858 00:22:03.272774 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2859 00:22:03.276170 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2860 00:22:03.279187 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2861 00:22:03.285969 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2862 00:22:03.288911 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2863 00:22:03.292198 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
2864 00:22:03.295730 0 15 28 | B1->B0 | 2d2d 2a2a | 0 0 | (0 0) (0 0)
2865 00:22:03.302675 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
2866 00:22:03.306288 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2867 00:22:03.309314 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2868 00:22:03.316279 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2869 00:22:03.319586 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2870 00:22:03.323087 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2871 00:22:03.329637 1 0 24 | B1->B0 | 2626 2d2d | 0 0 | (0 0) (0 0)
2872 00:22:03.332748 1 0 28 | B1->B0 | 3939 4040 | 0 0 | (0 0) (0 0)
2873 00:22:03.336250 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2874 00:22:03.342738 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2875 00:22:03.346310 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2876 00:22:03.349309 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2877 00:22:03.356133 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2878 00:22:03.359697 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2879 00:22:03.362756 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2880 00:22:03.366246 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2881 00:22:03.372858 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 00:22:03.376100 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 00:22:03.379498 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 00:22:03.386577 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 00:22:03.389451 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 00:22:03.392692 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 00:22:03.399236 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 00:22:03.402626 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 00:22:03.405825 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 00:22:03.412472 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 00:22:03.415670 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 00:22:03.419177 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 00:22:03.425909 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 00:22:03.429414 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 00:22:03.432798 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2896 00:22:03.439365 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2897 00:22:03.442552 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2898 00:22:03.445855 Total UI for P1: 0, mck2ui 16
2899 00:22:03.449327 best dqsien dly found for B0: ( 1, 3, 26)
2900 00:22:03.453058 Total UI for P1: 0, mck2ui 16
2901 00:22:03.456352 best dqsien dly found for B1: ( 1, 3, 28)
2902 00:22:03.459196 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2903 00:22:03.462438 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2904 00:22:03.462872
2905 00:22:03.466198 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2906 00:22:03.469588 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2907 00:22:03.472492 [Gating] SW calibration Done
2908 00:22:03.472907 ==
2909 00:22:03.476364 Dram Type= 6, Freq= 0, CH_0, rank 1
2910 00:22:03.479853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2911 00:22:03.480324 ==
2912 00:22:03.483109 RX Vref Scan: 0
2913 00:22:03.483576
2914 00:22:03.486320 RX Vref 0 -> 0, step: 1
2915 00:22:03.486796
2916 00:22:03.487101 RX Delay -40 -> 252, step: 8
2917 00:22:03.492859 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2918 00:22:03.496557 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2919 00:22:03.499463 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2920 00:22:03.503174 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2921 00:22:03.506000 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2922 00:22:03.512793 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2923 00:22:03.516213 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2924 00:22:03.519539 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2925 00:22:03.523069 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2926 00:22:03.526570 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2927 00:22:03.529306 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2928 00:22:03.536585 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2929 00:22:03.539503 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2930 00:22:03.543147 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2931 00:22:03.546538 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2932 00:22:03.549607 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2933 00:22:03.553620 ==
2934 00:22:03.556283 Dram Type= 6, Freq= 0, CH_0, rank 1
2935 00:22:03.559956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2936 00:22:03.560428 ==
2937 00:22:03.560766 DQS Delay:
2938 00:22:03.563200 DQS0 = 0, DQS1 = 0
2939 00:22:03.563586 DQM Delay:
2940 00:22:03.566046 DQM0 = 120, DQM1 = 108
2941 00:22:03.566439 DQ Delay:
2942 00:22:03.569423 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2943 00:22:03.573619 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2944 00:22:03.576567 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =103
2945 00:22:03.580113 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2946 00:22:03.580585
2947 00:22:03.580925
2948 00:22:03.581202 ==
2949 00:22:03.583052 Dram Type= 6, Freq= 0, CH_0, rank 1
2950 00:22:03.589393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2951 00:22:03.589789 ==
2952 00:22:03.590087
2953 00:22:03.590362
2954 00:22:03.590627 TX Vref Scan disable
2955 00:22:03.593075 == TX Byte 0 ==
2956 00:22:03.596407 Update DQ dly =855 (3 ,2, 23) DQ OEN =(2 ,7)
2957 00:22:03.599396 Update DQM dly =855 (3 ,2, 23) DQM OEN =(2 ,7)
2958 00:22:03.602919 == TX Byte 1 ==
2959 00:22:03.606192 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2960 00:22:03.609343 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2961 00:22:03.612999 ==
2962 00:22:03.615921 Dram Type= 6, Freq= 0, CH_0, rank 1
2963 00:22:03.619470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2964 00:22:03.619699 ==
2965 00:22:03.631175 TX Vref=22, minBit 0, minWin=25, winSum=414
2966 00:22:03.634674 TX Vref=24, minBit 5, minWin=25, winSum=424
2967 00:22:03.638077 TX Vref=26, minBit 1, minWin=25, winSum=424
2968 00:22:03.641236 TX Vref=28, minBit 5, minWin=25, winSum=428
2969 00:22:03.644765 TX Vref=30, minBit 5, minWin=25, winSum=430
2970 00:22:03.648401 TX Vref=32, minBit 5, minWin=25, winSum=429
2971 00:22:03.655136 [TxChooseVref] Worse bit 5, Min win 25, Win sum 430, Final Vref 30
2972 00:22:03.655451
2973 00:22:03.658228 Final TX Range 1 Vref 30
2974 00:22:03.658608
2975 00:22:03.658842 ==
2976 00:22:03.661186 Dram Type= 6, Freq= 0, CH_0, rank 1
2977 00:22:03.664760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2978 00:22:03.665156 ==
2979 00:22:03.665461
2980 00:22:03.665801
2981 00:22:03.668168 TX Vref Scan disable
2982 00:22:03.671395 == TX Byte 0 ==
2983 00:22:03.674929 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2984 00:22:03.678154 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2985 00:22:03.681322 == TX Byte 1 ==
2986 00:22:03.685105 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2987 00:22:03.688541 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2988 00:22:03.689056
2989 00:22:03.691686 [DATLAT]
2990 00:22:03.692228 Freq=1200, CH0 RK1
2991 00:22:03.692742
2992 00:22:03.694633 DATLAT Default: 0xd
2993 00:22:03.695033 0, 0xFFFF, sum = 0
2994 00:22:03.698171 1, 0xFFFF, sum = 0
2995 00:22:03.698562 2, 0xFFFF, sum = 0
2996 00:22:03.701265 3, 0xFFFF, sum = 0
2997 00:22:03.701660 4, 0xFFFF, sum = 0
2998 00:22:03.705123 5, 0xFFFF, sum = 0
2999 00:22:03.705594 6, 0xFFFF, sum = 0
3000 00:22:03.708183 7, 0xFFFF, sum = 0
3001 00:22:03.708613 8, 0xFFFF, sum = 0
3002 00:22:03.711645 9, 0xFFFF, sum = 0
3003 00:22:03.714780 10, 0xFFFF, sum = 0
3004 00:22:03.715253 11, 0xFFFF, sum = 0
3005 00:22:03.718292 12, 0x0, sum = 1
3006 00:22:03.718689 13, 0x0, sum = 2
3007 00:22:03.718996 14, 0x0, sum = 3
3008 00:22:03.721441 15, 0x0, sum = 4
3009 00:22:03.721833 best_step = 13
3010 00:22:03.722134
3011 00:22:03.722594 ==
3012 00:22:03.724886 Dram Type= 6, Freq= 0, CH_0, rank 1
3013 00:22:03.731989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3014 00:22:03.732460 ==
3015 00:22:03.732809 RX Vref Scan: 0
3016 00:22:03.733096
3017 00:22:03.734688 RX Vref 0 -> 0, step: 1
3018 00:22:03.735074
3019 00:22:03.738201 RX Delay -21 -> 252, step: 4
3020 00:22:03.741373 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3021 00:22:03.744915 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3022 00:22:03.752110 iDelay=195, Bit 2, Center 116 (51 ~ 182) 132
3023 00:22:03.755090 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3024 00:22:03.758523 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3025 00:22:03.762029 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3026 00:22:03.764842 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3027 00:22:03.772032 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3028 00:22:03.774822 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3029 00:22:03.778406 iDelay=195, Bit 9, Center 94 (31 ~ 158) 128
3030 00:22:03.781569 iDelay=195, Bit 10, Center 108 (47 ~ 170) 124
3031 00:22:03.785359 iDelay=195, Bit 11, Center 104 (43 ~ 166) 124
3032 00:22:03.788793 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3033 00:22:03.795446 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3034 00:22:03.798717 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3035 00:22:03.802179 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3036 00:22:03.802653 ==
3037 00:22:03.805308 Dram Type= 6, Freq= 0, CH_0, rank 1
3038 00:22:03.808403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3039 00:22:03.808836 ==
3040 00:22:03.811980 DQS Delay:
3041 00:22:03.812366 DQS0 = 0, DQS1 = 0
3042 00:22:03.815234 DQM Delay:
3043 00:22:03.815622 DQM0 = 119, DQM1 = 107
3044 00:22:03.818343 DQ Delay:
3045 00:22:03.821507 DQ0 =118, DQ1 =122, DQ2 =116, DQ3 =112
3046 00:22:03.825050 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =126
3047 00:22:03.828667 DQ8 =98, DQ9 =94, DQ10 =108, DQ11 =104
3048 00:22:03.831997 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =114
3049 00:22:03.832464
3050 00:22:03.832807
3051 00:22:03.838942 [DQSOSCAuto] RK1, (LSB)MR18= 0x12f9, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 403 ps
3052 00:22:03.841682 CH0 RK1: MR19=403, MR18=12F9
3053 00:22:03.848325 CH0_RK1: MR19=0x403, MR18=0x12F9, DQSOSC=403, MR23=63, INC=40, DEC=26
3054 00:22:03.852037 [RxdqsGatingPostProcess] freq 1200
3055 00:22:03.858620 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3056 00:22:03.859092 best DQS0 dly(2T, 0.5T) = (0, 11)
3057 00:22:03.861985 best DQS1 dly(2T, 0.5T) = (0, 11)
3058 00:22:03.865078 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3059 00:22:03.868295 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3060 00:22:03.871622 best DQS0 dly(2T, 0.5T) = (0, 11)
3061 00:22:03.875104 best DQS1 dly(2T, 0.5T) = (0, 11)
3062 00:22:03.878603 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3063 00:22:03.881570 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3064 00:22:03.885110 Pre-setting of DQS Precalculation
3065 00:22:03.891614 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3066 00:22:03.892081 ==
3067 00:22:03.894931 Dram Type= 6, Freq= 0, CH_1, rank 0
3068 00:22:03.898347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3069 00:22:03.898821 ==
3070 00:22:03.902083 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3071 00:22:03.908482 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3072 00:22:03.917514 [CA 0] Center 37 (7~68) winsize 62
3073 00:22:03.920964 [CA 1] Center 37 (7~68) winsize 62
3074 00:22:03.924455 [CA 2] Center 35 (5~65) winsize 61
3075 00:22:03.927335 [CA 3] Center 34 (4~65) winsize 62
3076 00:22:03.931065 [CA 4] Center 34 (4~65) winsize 62
3077 00:22:03.934178 [CA 5] Center 33 (3~64) winsize 62
3078 00:22:03.934569
3079 00:22:03.938042 [CmdBusTrainingLP45] Vref(ca) range 1: 31
3080 00:22:03.938525
3081 00:22:03.941334 [CATrainingPosCal] consider 1 rank data
3082 00:22:03.944132 u2DelayCellTimex100 = 270/100 ps
3083 00:22:03.947795 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3084 00:22:03.950710 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3085 00:22:03.957559 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3086 00:22:03.961151 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3087 00:22:03.964597 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3088 00:22:03.967684 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3089 00:22:03.968162
3090 00:22:03.970735 CA PerBit enable=1, Macro0, CA PI delay=33
3091 00:22:03.971120
3092 00:22:03.974111 [CBTSetCACLKResult] CA Dly = 33
3093 00:22:03.974502 CS Dly: 5 (0~36)
3094 00:22:03.977463 ==
3095 00:22:03.977871 Dram Type= 6, Freq= 0, CH_1, rank 1
3096 00:22:03.983865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3097 00:22:03.983943 ==
3098 00:22:03.986776 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3099 00:22:03.993312 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3100 00:22:04.002749 [CA 0] Center 38 (8~68) winsize 61
3101 00:22:04.006138 [CA 1] Center 38 (7~69) winsize 63
3102 00:22:04.009284 [CA 2] Center 35 (5~66) winsize 62
3103 00:22:04.012598 [CA 3] Center 35 (5~65) winsize 61
3104 00:22:04.016142 [CA 4] Center 34 (4~65) winsize 62
3105 00:22:04.019033 [CA 5] Center 34 (4~64) winsize 61
3106 00:22:04.019110
3107 00:22:04.022718 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3108 00:22:04.022795
3109 00:22:04.025828 [CATrainingPosCal] consider 2 rank data
3110 00:22:04.029092 u2DelayCellTimex100 = 270/100 ps
3111 00:22:04.032364 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3112 00:22:04.039204 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3113 00:22:04.042430 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3114 00:22:04.046053 CA3 delay=35 (5~65),Diff = 1 PI (4 cell)
3115 00:22:04.049303 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3116 00:22:04.052830 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3117 00:22:04.052910
3118 00:22:04.055772 CA PerBit enable=1, Macro0, CA PI delay=34
3119 00:22:04.055849
3120 00:22:04.059155 [CBTSetCACLKResult] CA Dly = 34
3121 00:22:04.059233 CS Dly: 6 (0~39)
3122 00:22:04.059293
3123 00:22:04.062793 ----->DramcWriteLeveling(PI) begin...
3124 00:22:04.065704 ==
3125 00:22:04.069272 Dram Type= 6, Freq= 0, CH_1, rank 0
3126 00:22:04.072782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3127 00:22:04.072860 ==
3128 00:22:04.076318 Write leveling (Byte 0): 25 => 25
3129 00:22:04.079297 Write leveling (Byte 1): 29 => 29
3130 00:22:04.082647 DramcWriteLeveling(PI) end<-----
3131 00:22:04.082723
3132 00:22:04.082782 ==
3133 00:22:04.086060 Dram Type= 6, Freq= 0, CH_1, rank 0
3134 00:22:04.089216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3135 00:22:04.089292 ==
3136 00:22:04.092476 [Gating] SW mode calibration
3137 00:22:04.099207 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3138 00:22:04.105917 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3139 00:22:04.108864 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3140 00:22:04.112346 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3141 00:22:04.115700 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3142 00:22:04.122054 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3143 00:22:04.125696 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3144 00:22:04.132369 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3145 00:22:04.135496 0 15 24 | B1->B0 | 2929 2424 | 1 0 | (1 0) (1 0)
3146 00:22:04.138766 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3147 00:22:04.142196 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3148 00:22:04.148496 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3149 00:22:04.151742 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3150 00:22:04.155684 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3151 00:22:04.162117 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3152 00:22:04.165478 1 0 20 | B1->B0 | 2525 2626 | 0 0 | (0 0) (0 0)
3153 00:22:04.168648 1 0 24 | B1->B0 | 3a39 4141 | 1 0 | (0 0) (0 0)
3154 00:22:04.175636 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3155 00:22:04.178564 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3156 00:22:04.182190 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3157 00:22:04.188763 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3158 00:22:04.191786 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3159 00:22:04.195270 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3160 00:22:04.202188 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3161 00:22:04.205112 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3162 00:22:04.208523 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3163 00:22:04.215299 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 00:22:04.218718 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 00:22:04.221767 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 00:22:04.228832 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 00:22:04.231741 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 00:22:04.234960 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 00:22:04.242017 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 00:22:04.245409 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 00:22:04.248636 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 00:22:04.255227 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 00:22:04.258500 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 00:22:04.261796 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 00:22:04.268275 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 00:22:04.271748 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3177 00:22:04.274883 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3178 00:22:04.278278 Total UI for P1: 0, mck2ui 16
3179 00:22:04.281673 best dqsien dly found for B0: ( 1, 3, 20)
3180 00:22:04.285130 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3181 00:22:04.288100 Total UI for P1: 0, mck2ui 16
3182 00:22:04.291730 best dqsien dly found for B1: ( 1, 3, 24)
3183 00:22:04.294885 best DQS0 dly(MCK, UI, PI) = (1, 3, 20)
3184 00:22:04.301493 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3185 00:22:04.301586
3186 00:22:04.304912 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 20)
3187 00:22:04.308024 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3188 00:22:04.311435 [Gating] SW calibration Done
3189 00:22:04.311512 ==
3190 00:22:04.314885 Dram Type= 6, Freq= 0, CH_1, rank 0
3191 00:22:04.318383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3192 00:22:04.318505 ==
3193 00:22:04.318594 RX Vref Scan: 0
3194 00:22:04.318680
3195 00:22:04.321756 RX Vref 0 -> 0, step: 1
3196 00:22:04.321863
3197 00:22:04.324700 RX Delay -40 -> 252, step: 8
3198 00:22:04.328451 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3199 00:22:04.331996 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3200 00:22:04.338385 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3201 00:22:04.341832 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3202 00:22:04.344625 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3203 00:22:04.347893 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3204 00:22:04.351434 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3205 00:22:04.358054 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3206 00:22:04.361752 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3207 00:22:04.364950 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3208 00:22:04.368335 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3209 00:22:04.371693 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3210 00:22:04.378551 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3211 00:22:04.381413 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3212 00:22:04.384906 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3213 00:22:04.387947 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3214 00:22:04.388030 ==
3215 00:22:04.391315 Dram Type= 6, Freq= 0, CH_1, rank 0
3216 00:22:04.397950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3217 00:22:04.398094 ==
3218 00:22:04.398156 DQS Delay:
3219 00:22:04.398243 DQS0 = 0, DQS1 = 0
3220 00:22:04.440826 DQM Delay:
3221 00:22:04.440955 DQM0 = 120, DQM1 = 112
3222 00:22:04.441016 DQ Delay:
3223 00:22:04.441070 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =123
3224 00:22:04.441123 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =119
3225 00:22:04.441174 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3226 00:22:04.441224 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3227 00:22:04.441272
3228 00:22:04.441350
3229 00:22:04.441398 ==
3230 00:22:04.441447 Dram Type= 6, Freq= 0, CH_1, rank 0
3231 00:22:04.441497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3232 00:22:04.441546 ==
3233 00:22:04.441594
3234 00:22:04.441642
3235 00:22:04.441689 TX Vref Scan disable
3236 00:22:04.441738 == TX Byte 0 ==
3237 00:22:04.441786 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3238 00:22:04.441835 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3239 00:22:04.442069 == TX Byte 1 ==
3240 00:22:04.444744 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3241 00:22:04.448039 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3242 00:22:04.448119 ==
3243 00:22:04.451141 Dram Type= 6, Freq= 0, CH_1, rank 0
3244 00:22:04.457565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3245 00:22:04.457694 ==
3246 00:22:04.468448 TX Vref=22, minBit 1, minWin=24, winSum=405
3247 00:22:04.471852 TX Vref=24, minBit 1, minWin=25, winSum=410
3248 00:22:04.474960 TX Vref=26, minBit 3, minWin=25, winSum=413
3249 00:22:04.478437 TX Vref=28, minBit 10, minWin=25, winSum=423
3250 00:22:04.481769 TX Vref=30, minBit 1, minWin=26, winSum=422
3251 00:22:04.488443 TX Vref=32, minBit 9, minWin=25, winSum=420
3252 00:22:04.491801 [TxChooseVref] Worse bit 1, Min win 26, Win sum 422, Final Vref 30
3253 00:22:04.491895
3254 00:22:04.494894 Final TX Range 1 Vref 30
3255 00:22:04.494976
3256 00:22:04.495035 ==
3257 00:22:04.498162 Dram Type= 6, Freq= 0, CH_1, rank 0
3258 00:22:04.501500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3259 00:22:04.501579 ==
3260 00:22:04.504919
3261 00:22:04.504994
3262 00:22:04.505051 TX Vref Scan disable
3263 00:22:04.508177 == TX Byte 0 ==
3264 00:22:04.511453 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3265 00:22:04.518103 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3266 00:22:04.518180 == TX Byte 1 ==
3267 00:22:04.521198 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3268 00:22:04.528001 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3269 00:22:04.528143
3270 00:22:04.528216 [DATLAT]
3271 00:22:04.528276 Freq=1200, CH1 RK0
3272 00:22:04.528333
3273 00:22:04.531435 DATLAT Default: 0xd
3274 00:22:04.531523 0, 0xFFFF, sum = 0
3275 00:22:04.534814 1, 0xFFFF, sum = 0
3276 00:22:04.537981 2, 0xFFFF, sum = 0
3277 00:22:04.538067 3, 0xFFFF, sum = 0
3278 00:22:04.541704 4, 0xFFFF, sum = 0
3279 00:22:04.541781 5, 0xFFFF, sum = 0
3280 00:22:04.544743 6, 0xFFFF, sum = 0
3281 00:22:04.544821 7, 0xFFFF, sum = 0
3282 00:22:04.548256 8, 0xFFFF, sum = 0
3283 00:22:04.548342 9, 0xFFFF, sum = 0
3284 00:22:04.551144 10, 0xFFFF, sum = 0
3285 00:22:04.551229 11, 0xFFFF, sum = 0
3286 00:22:04.554527 12, 0x0, sum = 1
3287 00:22:04.554611 13, 0x0, sum = 2
3288 00:22:04.557983 14, 0x0, sum = 3
3289 00:22:04.558067 15, 0x0, sum = 4
3290 00:22:04.558132 best_step = 13
3291 00:22:04.561467
3292 00:22:04.561552 ==
3293 00:22:04.564754 Dram Type= 6, Freq= 0, CH_1, rank 0
3294 00:22:04.567997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3295 00:22:04.568085 ==
3296 00:22:04.568149 RX Vref Scan: 1
3297 00:22:04.568207
3298 00:22:04.571068 Set Vref Range= 32 -> 127
3299 00:22:04.571148
3300 00:22:04.574683 RX Vref 32 -> 127, step: 1
3301 00:22:04.574761
3302 00:22:04.577750 RX Delay -13 -> 252, step: 4
3303 00:22:04.577826
3304 00:22:04.581212 Set Vref, RX VrefLevel [Byte0]: 32
3305 00:22:04.584605 [Byte1]: 32
3306 00:22:04.584681
3307 00:22:04.588193 Set Vref, RX VrefLevel [Byte0]: 33
3308 00:22:04.591633 [Byte1]: 33
3309 00:22:04.591707
3310 00:22:04.594523 Set Vref, RX VrefLevel [Byte0]: 34
3311 00:22:04.597953 [Byte1]: 34
3312 00:22:04.602732
3313 00:22:04.603114 Set Vref, RX VrefLevel [Byte0]: 35
3314 00:22:04.605970 [Byte1]: 35
3315 00:22:04.610448
3316 00:22:04.610909 Set Vref, RX VrefLevel [Byte0]: 36
3317 00:22:04.613745 [Byte1]: 36
3318 00:22:04.618583
3319 00:22:04.619018 Set Vref, RX VrefLevel [Byte0]: 37
3320 00:22:04.622354 [Byte1]: 37
3321 00:22:04.626591
3322 00:22:04.626977 Set Vref, RX VrefLevel [Byte0]: 38
3323 00:22:04.630093 [Byte1]: 38
3324 00:22:04.634252
3325 00:22:04.634640 Set Vref, RX VrefLevel [Byte0]: 39
3326 00:22:04.637712 [Byte1]: 39
3327 00:22:04.642089
3328 00:22:04.642497 Set Vref, RX VrefLevel [Byte0]: 40
3329 00:22:04.645336 [Byte1]: 40
3330 00:22:04.650170
3331 00:22:04.650685 Set Vref, RX VrefLevel [Byte0]: 41
3332 00:22:04.653589 [Byte1]: 41
3333 00:22:04.657723
3334 00:22:04.658110 Set Vref, RX VrefLevel [Byte0]: 42
3335 00:22:04.661327 [Byte1]: 42
3336 00:22:04.665742
3337 00:22:04.666130 Set Vref, RX VrefLevel [Byte0]: 43
3338 00:22:04.669355 [Byte1]: 43
3339 00:22:04.674085
3340 00:22:04.674470 Set Vref, RX VrefLevel [Byte0]: 44
3341 00:22:04.677214 [Byte1]: 44
3342 00:22:04.681863
3343 00:22:04.682250 Set Vref, RX VrefLevel [Byte0]: 45
3344 00:22:04.685182 [Byte1]: 45
3345 00:22:04.689788
3346 00:22:04.690170 Set Vref, RX VrefLevel [Byte0]: 46
3347 00:22:04.692977 [Byte1]: 46
3348 00:22:04.697067
3349 00:22:04.697342 Set Vref, RX VrefLevel [Byte0]: 47
3350 00:22:04.700761 [Byte1]: 47
3351 00:22:04.705049
3352 00:22:04.705215 Set Vref, RX VrefLevel [Byte0]: 48
3353 00:22:04.708177 [Byte1]: 48
3354 00:22:04.712794
3355 00:22:04.712935 Set Vref, RX VrefLevel [Byte0]: 49
3356 00:22:04.716240 [Byte1]: 49
3357 00:22:04.720574
3358 00:22:04.720680 Set Vref, RX VrefLevel [Byte0]: 50
3359 00:22:04.724066 [Byte1]: 50
3360 00:22:04.728829
3361 00:22:04.728925 Set Vref, RX VrefLevel [Byte0]: 51
3362 00:22:04.731776 [Byte1]: 51
3363 00:22:04.736642
3364 00:22:04.736753 Set Vref, RX VrefLevel [Byte0]: 52
3365 00:22:04.739628 [Byte1]: 52
3366 00:22:04.744688
3367 00:22:04.744808 Set Vref, RX VrefLevel [Byte0]: 53
3368 00:22:04.747553 [Byte1]: 53
3369 00:22:04.752616
3370 00:22:04.752701 Set Vref, RX VrefLevel [Byte0]: 54
3371 00:22:04.755823 [Byte1]: 54
3372 00:22:04.760509
3373 00:22:04.760596 Set Vref, RX VrefLevel [Byte0]: 55
3374 00:22:04.763734 [Byte1]: 55
3375 00:22:04.768204
3376 00:22:04.768296 Set Vref, RX VrefLevel [Byte0]: 56
3377 00:22:04.771318 [Byte1]: 56
3378 00:22:04.775811
3379 00:22:04.775920 Set Vref, RX VrefLevel [Byte0]: 57
3380 00:22:04.779406 [Byte1]: 57
3381 00:22:04.784233
3382 00:22:04.784354 Set Vref, RX VrefLevel [Byte0]: 58
3383 00:22:04.787454 [Byte1]: 58
3384 00:22:04.792243
3385 00:22:04.792462 Set Vref, RX VrefLevel [Byte0]: 59
3386 00:22:04.795623 [Byte1]: 59
3387 00:22:04.800183
3388 00:22:04.800428 Set Vref, RX VrefLevel [Byte0]: 60
3389 00:22:04.803333 [Byte1]: 60
3390 00:22:04.807900
3391 00:22:04.808241 Set Vref, RX VrefLevel [Byte0]: 61
3392 00:22:04.811617 [Byte1]: 61
3393 00:22:04.816478
3394 00:22:04.817039 Set Vref, RX VrefLevel [Byte0]: 62
3395 00:22:04.819251 [Byte1]: 62
3396 00:22:04.823808
3397 00:22:04.824276 Set Vref, RX VrefLevel [Byte0]: 63
3398 00:22:04.827256 [Byte1]: 63
3399 00:22:04.832183
3400 00:22:04.832647 Set Vref, RX VrefLevel [Byte0]: 64
3401 00:22:04.834919 [Byte1]: 64
3402 00:22:04.839714
3403 00:22:04.840233 Set Vref, RX VrefLevel [Byte0]: 65
3404 00:22:04.843287 [Byte1]: 65
3405 00:22:04.847637
3406 00:22:04.848105 Set Vref, RX VrefLevel [Byte0]: 66
3407 00:22:04.851070 [Byte1]: 66
3408 00:22:04.855292
3409 00:22:04.855759 Set Vref, RX VrefLevel [Byte0]: 67
3410 00:22:04.858644 [Byte1]: 67
3411 00:22:04.862972
3412 00:22:04.863357 Final RX Vref Byte 0 = 50 to rank0
3413 00:22:04.866427 Final RX Vref Byte 1 = 52 to rank0
3414 00:22:04.869506 Final RX Vref Byte 0 = 50 to rank1
3415 00:22:04.873167 Final RX Vref Byte 1 = 52 to rank1==
3416 00:22:04.876090 Dram Type= 6, Freq= 0, CH_1, rank 0
3417 00:22:04.883004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3418 00:22:04.883398 ==
3419 00:22:04.883698 DQS Delay:
3420 00:22:04.883973 DQS0 = 0, DQS1 = 0
3421 00:22:04.886317 DQM Delay:
3422 00:22:04.886701 DQM0 = 119, DQM1 = 112
3423 00:22:04.889610 DQ Delay:
3424 00:22:04.892979 DQ0 =118, DQ1 =112, DQ2 =112, DQ3 =118
3425 00:22:04.896428 DQ4 =118, DQ5 =128, DQ6 =128, DQ7 =118
3426 00:22:04.899924 DQ8 =102, DQ9 =100, DQ10 =114, DQ11 =106
3427 00:22:04.903167 DQ12 =122, DQ13 =118, DQ14 =118, DQ15 =118
3428 00:22:04.903552
3429 00:22:04.903847
3430 00:22:04.912764 [DQSOSCAuto] RK0, (LSB)MR18= 0x81b, (MSB)MR19= 0x404, tDQSOscB0 = 399 ps tDQSOscB1 = 406 ps
3431 00:22:04.913160 CH1 RK0: MR19=404, MR18=81B
3432 00:22:04.919770 CH1_RK0: MR19=0x404, MR18=0x81B, DQSOSC=399, MR23=63, INC=41, DEC=27
3433 00:22:04.920159
3434 00:22:04.922746 ----->DramcWriteLeveling(PI) begin...
3435 00:22:04.923137 ==
3436 00:22:04.926092 Dram Type= 6, Freq= 0, CH_1, rank 1
3437 00:22:04.929388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3438 00:22:04.932939 ==
3439 00:22:04.933326 Write leveling (Byte 0): 26 => 26
3440 00:22:04.936363 Write leveling (Byte 1): 29 => 29
3441 00:22:04.939299 DramcWriteLeveling(PI) end<-----
3442 00:22:04.939683
3443 00:22:04.940038 ==
3444 00:22:04.942843 Dram Type= 6, Freq= 0, CH_1, rank 1
3445 00:22:04.949272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3446 00:22:04.949659 ==
3447 00:22:04.949954 [Gating] SW mode calibration
3448 00:22:04.959663 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3449 00:22:04.963014 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3450 00:22:04.966176 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3451 00:22:04.972552 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3452 00:22:04.975820 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3453 00:22:04.979319 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3454 00:22:04.985964 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3455 00:22:04.988980 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3456 00:22:04.992711 0 15 24 | B1->B0 | 2929 3232 | 0 1 | (0 1) (1 0)
3457 00:22:04.999288 0 15 28 | B1->B0 | 2323 2b2b | 0 0 | (1 0) (0 0)
3458 00:22:05.003158 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3459 00:22:05.006460 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3460 00:22:05.013294 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3461 00:22:05.016603 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3462 00:22:05.019918 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3463 00:22:05.026530 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3464 00:22:05.029913 1 0 24 | B1->B0 | 3c3c 2d2d | 0 1 | (0 0) (0 0)
3465 00:22:05.032999 1 0 28 | B1->B0 | 4646 4242 | 0 0 | (0 0) (0 0)
3466 00:22:05.039469 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3467 00:22:05.043132 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3468 00:22:05.046595 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3469 00:22:05.050243 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3470 00:22:05.056852 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3471 00:22:05.060037 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3472 00:22:05.063819 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3473 00:22:05.069745 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3474 00:22:05.073573 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 00:22:05.077050 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 00:22:05.083735 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 00:22:05.086678 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 00:22:05.089689 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 00:22:05.096490 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 00:22:05.100018 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 00:22:05.103219 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 00:22:05.109834 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 00:22:05.113081 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 00:22:05.116909 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 00:22:05.123016 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 00:22:05.126414 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 00:22:05.130014 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 00:22:05.136772 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3489 00:22:05.140293 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3490 00:22:05.143417 Total UI for P1: 0, mck2ui 16
3491 00:22:05.146247 best dqsien dly found for B0: ( 1, 3, 24)
3492 00:22:05.149802 Total UI for P1: 0, mck2ui 16
3493 00:22:05.153335 best dqsien dly found for B1: ( 1, 3, 24)
3494 00:22:05.156383 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3495 00:22:05.159436 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3496 00:22:05.159938
3497 00:22:05.162712 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3498 00:22:05.166225 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3499 00:22:05.169301 [Gating] SW calibration Done
3500 00:22:05.169684 ==
3501 00:22:05.172697 Dram Type= 6, Freq= 0, CH_1, rank 1
3502 00:22:05.176138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3503 00:22:05.176526 ==
3504 00:22:05.179579 RX Vref Scan: 0
3505 00:22:05.180057
3506 00:22:05.183154 RX Vref 0 -> 0, step: 1
3507 00:22:05.183539
3508 00:22:05.183835 RX Delay -40 -> 252, step: 8
3509 00:22:05.189578 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3510 00:22:05.192787 iDelay=200, Bit 1, Center 111 (48 ~ 175) 128
3511 00:22:05.195899 iDelay=200, Bit 2, Center 107 (48 ~ 167) 120
3512 00:22:05.199209 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3513 00:22:05.203451 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3514 00:22:05.209458 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3515 00:22:05.212567 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3516 00:22:05.216555 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3517 00:22:05.219354 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3518 00:22:05.223026 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3519 00:22:05.229320 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3520 00:22:05.233103 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3521 00:22:05.236159 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3522 00:22:05.239686 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3523 00:22:05.243107 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3524 00:22:05.249473 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3525 00:22:05.250014 ==
3526 00:22:05.252636 Dram Type= 6, Freq= 0, CH_1, rank 1
3527 00:22:05.256326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3528 00:22:05.256843 ==
3529 00:22:05.257161 DQS Delay:
3530 00:22:05.259385 DQS0 = 0, DQS1 = 0
3531 00:22:05.259770 DQM Delay:
3532 00:22:05.262784 DQM0 = 118, DQM1 = 112
3533 00:22:05.263170 DQ Delay:
3534 00:22:05.266590 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =115
3535 00:22:05.269488 DQ4 =119, DQ5 =131, DQ6 =127, DQ7 =115
3536 00:22:05.273120 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3537 00:22:05.276646 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3538 00:22:05.277154
3539 00:22:05.277455
3540 00:22:05.279291 ==
3541 00:22:05.279681 Dram Type= 6, Freq= 0, CH_1, rank 1
3542 00:22:05.286266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3543 00:22:05.286678 ==
3544 00:22:05.286980
3545 00:22:05.287257
3546 00:22:05.287518 TX Vref Scan disable
3547 00:22:05.289510 == TX Byte 0 ==
3548 00:22:05.293150 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3549 00:22:05.299677 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3550 00:22:05.300119 == TX Byte 1 ==
3551 00:22:05.303032 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3552 00:22:05.309614 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3553 00:22:05.310024 ==
3554 00:22:05.312779 Dram Type= 6, Freq= 0, CH_1, rank 1
3555 00:22:05.316153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3556 00:22:05.316477 ==
3557 00:22:05.327257 TX Vref=22, minBit 9, minWin=25, winSum=417
3558 00:22:05.330680 TX Vref=24, minBit 1, minWin=25, winSum=422
3559 00:22:05.333839 TX Vref=26, minBit 10, minWin=25, winSum=427
3560 00:22:05.337338 TX Vref=28, minBit 8, minWin=26, winSum=429
3561 00:22:05.340733 TX Vref=30, minBit 8, minWin=26, winSum=428
3562 00:22:05.346968 TX Vref=32, minBit 9, minWin=25, winSum=426
3563 00:22:05.350454 [TxChooseVref] Worse bit 8, Min win 26, Win sum 429, Final Vref 28
3564 00:22:05.350559
3565 00:22:05.353760 Final TX Range 1 Vref 28
3566 00:22:05.353864
3567 00:22:05.353944 ==
3568 00:22:05.357359 Dram Type= 6, Freq= 0, CH_1, rank 1
3569 00:22:05.360727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3570 00:22:05.363739 ==
3571 00:22:05.363840
3572 00:22:05.363918
3573 00:22:05.363990 TX Vref Scan disable
3574 00:22:05.367394 == TX Byte 0 ==
3575 00:22:05.370554 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3576 00:22:05.374048 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3577 00:22:05.377106 == TX Byte 1 ==
3578 00:22:05.380853 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3579 00:22:05.387425 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3580 00:22:05.387617
3581 00:22:05.387719 [DATLAT]
3582 00:22:05.387812 Freq=1200, CH1 RK1
3583 00:22:05.387901
3584 00:22:05.390621 DATLAT Default: 0xd
3585 00:22:05.390763 0, 0xFFFF, sum = 0
3586 00:22:05.394218 1, 0xFFFF, sum = 0
3587 00:22:05.397308 2, 0xFFFF, sum = 0
3588 00:22:05.397585 3, 0xFFFF, sum = 0
3589 00:22:05.400775 4, 0xFFFF, sum = 0
3590 00:22:05.401005 5, 0xFFFF, sum = 0
3591 00:22:05.403790 6, 0xFFFF, sum = 0
3592 00:22:05.404048 7, 0xFFFF, sum = 0
3593 00:22:05.407518 8, 0xFFFF, sum = 0
3594 00:22:05.407779 9, 0xFFFF, sum = 0
3595 00:22:05.410468 10, 0xFFFF, sum = 0
3596 00:22:05.410766 11, 0xFFFF, sum = 0
3597 00:22:05.413648 12, 0x0, sum = 1
3598 00:22:05.413930 13, 0x0, sum = 2
3599 00:22:05.417152 14, 0x0, sum = 3
3600 00:22:05.417524 15, 0x0, sum = 4
3601 00:22:05.417759 best_step = 13
3602 00:22:05.420537
3603 00:22:05.420954 ==
3604 00:22:05.424290 Dram Type= 6, Freq= 0, CH_1, rank 1
3605 00:22:05.427398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3606 00:22:05.427785 ==
3607 00:22:05.428084 RX Vref Scan: 0
3608 00:22:05.428362
3609 00:22:05.430891 RX Vref 0 -> 0, step: 1
3610 00:22:05.431511
3611 00:22:05.434052 RX Delay -13 -> 252, step: 4
3612 00:22:05.437416 iDelay=195, Bit 0, Center 124 (67 ~ 182) 116
3613 00:22:05.443608 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3614 00:22:05.447061 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3615 00:22:05.450713 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3616 00:22:05.453877 iDelay=195, Bit 4, Center 122 (63 ~ 182) 120
3617 00:22:05.457272 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3618 00:22:05.463742 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3619 00:22:05.467043 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3620 00:22:05.470331 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3621 00:22:05.473615 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3622 00:22:05.477436 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3623 00:22:05.483931 iDelay=195, Bit 11, Center 108 (43 ~ 174) 132
3624 00:22:05.486954 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3625 00:22:05.489941 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3626 00:22:05.493242 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3627 00:22:05.496276 iDelay=195, Bit 15, Center 124 (59 ~ 190) 132
3628 00:22:05.499849 ==
3629 00:22:05.503335 Dram Type= 6, Freq= 0, CH_1, rank 1
3630 00:22:05.506168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3631 00:22:05.506292 ==
3632 00:22:05.506362 DQS Delay:
3633 00:22:05.509733 DQS0 = 0, DQS1 = 0
3634 00:22:05.509870 DQM Delay:
3635 00:22:05.513124 DQM0 = 119, DQM1 = 113
3636 00:22:05.513233 DQ Delay:
3637 00:22:05.516615 DQ0 =124, DQ1 =114, DQ2 =108, DQ3 =118
3638 00:22:05.520305 DQ4 =122, DQ5 =130, DQ6 =126, DQ7 =116
3639 00:22:05.523204 DQ8 =98, DQ9 =102, DQ10 =114, DQ11 =108
3640 00:22:05.526649 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =124
3641 00:22:05.527044
3642 00:22:05.527347
3643 00:22:05.536594 [DQSOSCAuto] RK1, (LSB)MR18= 0xdf2, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 405 ps
3644 00:22:05.540043 CH1 RK1: MR19=403, MR18=DF2
3645 00:22:05.543634 CH1_RK1: MR19=0x403, MR18=0xDF2, DQSOSC=405, MR23=63, INC=39, DEC=26
3646 00:22:05.546853 [RxdqsGatingPostProcess] freq 1200
3647 00:22:05.553091 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3648 00:22:05.556389 best DQS0 dly(2T, 0.5T) = (0, 11)
3649 00:22:05.559560 best DQS1 dly(2T, 0.5T) = (0, 11)
3650 00:22:05.563041 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3651 00:22:05.566252 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3652 00:22:05.569901 best DQS0 dly(2T, 0.5T) = (0, 11)
3653 00:22:05.573053 best DQS1 dly(2T, 0.5T) = (0, 11)
3654 00:22:05.576445 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3655 00:22:05.579696 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3656 00:22:05.579907 Pre-setting of DQS Precalculation
3657 00:22:05.585929 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3658 00:22:05.592871 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3659 00:22:05.599824 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3660 00:22:05.599950
3661 00:22:05.600033
3662 00:22:05.602804 [Calibration Summary] 2400 Mbps
3663 00:22:05.606207 CH 0, Rank 0
3664 00:22:05.606297 SW Impedance : PASS
3665 00:22:05.609706 DUTY Scan : NO K
3666 00:22:05.612599 ZQ Calibration : PASS
3667 00:22:05.612715 Jitter Meter : NO K
3668 00:22:05.616111 CBT Training : PASS
3669 00:22:05.616191 Write leveling : PASS
3670 00:22:05.619337 RX DQS gating : PASS
3671 00:22:05.622739 RX DQ/DQS(RDDQC) : PASS
3672 00:22:05.622831 TX DQ/DQS : PASS
3673 00:22:05.626068 RX DATLAT : PASS
3674 00:22:05.629477 RX DQ/DQS(Engine): PASS
3675 00:22:05.629561 TX OE : NO K
3676 00:22:05.632834 All Pass.
3677 00:22:05.632912
3678 00:22:05.632972 CH 0, Rank 1
3679 00:22:05.635818 SW Impedance : PASS
3680 00:22:05.635895 DUTY Scan : NO K
3681 00:22:05.639326 ZQ Calibration : PASS
3682 00:22:05.642624 Jitter Meter : NO K
3683 00:22:05.642708 CBT Training : PASS
3684 00:22:05.645822 Write leveling : PASS
3685 00:22:05.649309 RX DQS gating : PASS
3686 00:22:05.649390 RX DQ/DQS(RDDQC) : PASS
3687 00:22:05.652676 TX DQ/DQS : PASS
3688 00:22:05.655795 RX DATLAT : PASS
3689 00:22:05.655875 RX DQ/DQS(Engine): PASS
3690 00:22:05.659393 TX OE : NO K
3691 00:22:05.659494 All Pass.
3692 00:22:05.659585
3693 00:22:05.662483 CH 1, Rank 0
3694 00:22:05.662561 SW Impedance : PASS
3695 00:22:05.665617 DUTY Scan : NO K
3696 00:22:05.669013 ZQ Calibration : PASS
3697 00:22:05.669100 Jitter Meter : NO K
3698 00:22:05.672419 CBT Training : PASS
3699 00:22:05.672502 Write leveling : PASS
3700 00:22:05.675792 RX DQS gating : PASS
3701 00:22:05.679197 RX DQ/DQS(RDDQC) : PASS
3702 00:22:05.679283 TX DQ/DQS : PASS
3703 00:22:05.682526 RX DATLAT : PASS
3704 00:22:05.685853 RX DQ/DQS(Engine): PASS
3705 00:22:05.685937 TX OE : NO K
3706 00:22:05.689140 All Pass.
3707 00:22:05.689222
3708 00:22:05.689281 CH 1, Rank 1
3709 00:22:05.692674 SW Impedance : PASS
3710 00:22:05.692805 DUTY Scan : NO K
3711 00:22:05.695570 ZQ Calibration : PASS
3712 00:22:05.698953 Jitter Meter : NO K
3713 00:22:05.699048 CBT Training : PASS
3714 00:22:05.702549 Write leveling : PASS
3715 00:22:05.706005 RX DQS gating : PASS
3716 00:22:05.706092 RX DQ/DQS(RDDQC) : PASS
3717 00:22:05.708843 TX DQ/DQS : PASS
3718 00:22:05.712468 RX DATLAT : PASS
3719 00:22:05.712554 RX DQ/DQS(Engine): PASS
3720 00:22:05.715807 TX OE : NO K
3721 00:22:05.715884 All Pass.
3722 00:22:05.715944
3723 00:22:05.718765 DramC Write-DBI off
3724 00:22:05.722483 PER_BANK_REFRESH: Hybrid Mode
3725 00:22:05.722561 TX_TRACKING: ON
3726 00:22:05.732568 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3727 00:22:05.735510 [FAST_K] Save calibration result to emmc
3728 00:22:05.738982 dramc_set_vcore_voltage set vcore to 650000
3729 00:22:05.742409 Read voltage for 600, 5
3730 00:22:05.742493 Vio18 = 0
3731 00:22:05.742553 Vcore = 650000
3732 00:22:05.742608 Vdram = 0
3733 00:22:05.745922 Vddq = 0
3734 00:22:05.746001 Vmddr = 0
3735 00:22:05.752417 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3736 00:22:05.755779 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3737 00:22:05.759135 MEM_TYPE=3, freq_sel=19
3738 00:22:05.762037 sv_algorithm_assistance_LP4_1600
3739 00:22:05.765943 ============ PULL DRAM RESETB DOWN ============
3740 00:22:05.769020 ========== PULL DRAM RESETB DOWN end =========
3741 00:22:05.775681 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3742 00:22:05.779203 ===================================
3743 00:22:05.779285 LPDDR4 DRAM CONFIGURATION
3744 00:22:05.782293 ===================================
3745 00:22:05.785771 EX_ROW_EN[0] = 0x0
3746 00:22:05.785852 EX_ROW_EN[1] = 0x0
3747 00:22:05.789104 LP4Y_EN = 0x0
3748 00:22:05.792310 WORK_FSP = 0x0
3749 00:22:05.792388 WL = 0x2
3750 00:22:05.795715 RL = 0x2
3751 00:22:05.795792 BL = 0x2
3752 00:22:05.799102 RPST = 0x0
3753 00:22:05.799183 RD_PRE = 0x0
3754 00:22:05.802325 WR_PRE = 0x1
3755 00:22:05.802403 WR_PST = 0x0
3756 00:22:05.805869 DBI_WR = 0x0
3757 00:22:05.805947 DBI_RD = 0x0
3758 00:22:05.808707 OTF = 0x1
3759 00:22:05.812296 ===================================
3760 00:22:05.815843 ===================================
3761 00:22:05.815921 ANA top config
3762 00:22:05.818790 ===================================
3763 00:22:05.822295 DLL_ASYNC_EN = 0
3764 00:22:05.825601 ALL_SLAVE_EN = 1
3765 00:22:05.825678 NEW_RANK_MODE = 1
3766 00:22:05.828902 DLL_IDLE_MODE = 1
3767 00:22:05.832073 LP45_APHY_COMB_EN = 1
3768 00:22:05.835797 TX_ODT_DIS = 1
3769 00:22:05.835876 NEW_8X_MODE = 1
3770 00:22:05.838716 ===================================
3771 00:22:05.842184 ===================================
3772 00:22:05.845690 data_rate = 1200
3773 00:22:05.848685 CKR = 1
3774 00:22:05.852064 DQ_P2S_RATIO = 8
3775 00:22:05.855433 ===================================
3776 00:22:05.858748 CA_P2S_RATIO = 8
3777 00:22:05.862002 DQ_CA_OPEN = 0
3778 00:22:05.865546 DQ_SEMI_OPEN = 0
3779 00:22:05.865641 CA_SEMI_OPEN = 0
3780 00:22:05.868964 CA_FULL_RATE = 0
3781 00:22:05.871918 DQ_CKDIV4_EN = 1
3782 00:22:05.875360 CA_CKDIV4_EN = 1
3783 00:22:05.879041 CA_PREDIV_EN = 0
3784 00:22:05.879140 PH8_DLY = 0
3785 00:22:05.881869 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3786 00:22:05.885569 DQ_AAMCK_DIV = 4
3787 00:22:05.888849 CA_AAMCK_DIV = 4
3788 00:22:05.892223 CA_ADMCK_DIV = 4
3789 00:22:05.895590 DQ_TRACK_CA_EN = 0
3790 00:22:05.895668 CA_PICK = 600
3791 00:22:05.898967 CA_MCKIO = 600
3792 00:22:05.902154 MCKIO_SEMI = 0
3793 00:22:05.905691 PLL_FREQ = 2288
3794 00:22:05.908954 DQ_UI_PI_RATIO = 32
3795 00:22:05.912357 CA_UI_PI_RATIO = 0
3796 00:22:05.915413 ===================================
3797 00:22:05.918798 ===================================
3798 00:22:05.922155 memory_type:LPDDR4
3799 00:22:05.922231 GP_NUM : 10
3800 00:22:05.925569 SRAM_EN : 1
3801 00:22:05.925646 MD32_EN : 0
3802 00:22:05.929070 ===================================
3803 00:22:05.932326 [ANA_INIT] >>>>>>>>>>>>>>
3804 00:22:05.935195 <<<<<< [CONFIGURE PHASE]: ANA_TX
3805 00:22:05.938648 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3806 00:22:05.941940 ===================================
3807 00:22:05.945411 data_rate = 1200,PCW = 0X5800
3808 00:22:05.948849 ===================================
3809 00:22:05.952198 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3810 00:22:05.955194 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3811 00:22:05.962322 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3812 00:22:05.965288 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3813 00:22:05.969025 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3814 00:22:05.972364 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3815 00:22:05.975328 [ANA_INIT] flow start
3816 00:22:05.978818 [ANA_INIT] PLL >>>>>>>>
3817 00:22:05.978894 [ANA_INIT] PLL <<<<<<<<
3818 00:22:05.982270 [ANA_INIT] MIDPI >>>>>>>>
3819 00:22:05.985247 [ANA_INIT] MIDPI <<<<<<<<
3820 00:22:05.988651 [ANA_INIT] DLL >>>>>>>>
3821 00:22:05.988763 [ANA_INIT] flow end
3822 00:22:05.992377 ============ LP4 DIFF to SE enter ============
3823 00:22:05.998556 ============ LP4 DIFF to SE exit ============
3824 00:22:05.998687 [ANA_INIT] <<<<<<<<<<<<<
3825 00:22:06.002204 [Flow] Enable top DCM control >>>>>
3826 00:22:06.005630 [Flow] Enable top DCM control <<<<<
3827 00:22:06.008954 Enable DLL master slave shuffle
3828 00:22:06.015165 ==============================================================
3829 00:22:06.015244 Gating Mode config
3830 00:22:06.022085 ==============================================================
3831 00:22:06.025412 Config description:
3832 00:22:06.035062 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3833 00:22:06.041735 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3834 00:22:06.045262 SELPH_MODE 0: By rank 1: By Phase
3835 00:22:06.051681 ==============================================================
3836 00:22:06.055055 GAT_TRACK_EN = 1
3837 00:22:06.055132 RX_GATING_MODE = 2
3838 00:22:06.058524 RX_GATING_TRACK_MODE = 2
3839 00:22:06.061436 SELPH_MODE = 1
3840 00:22:06.065184 PICG_EARLY_EN = 1
3841 00:22:06.068427 VALID_LAT_VALUE = 1
3842 00:22:06.075035 ==============================================================
3843 00:22:06.078243 Enter into Gating configuration >>>>
3844 00:22:06.081866 Exit from Gating configuration <<<<
3845 00:22:06.084693 Enter into DVFS_PRE_config >>>>>
3846 00:22:06.095060 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3847 00:22:06.098176 Exit from DVFS_PRE_config <<<<<
3848 00:22:06.101441 Enter into PICG configuration >>>>
3849 00:22:06.104935 Exit from PICG configuration <<<<
3850 00:22:06.107991 [RX_INPUT] configuration >>>>>
3851 00:22:06.111246 [RX_INPUT] configuration <<<<<
3852 00:22:06.114591 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3853 00:22:06.121384 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3854 00:22:06.128021 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3855 00:22:06.134765 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3856 00:22:06.137785 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3857 00:22:06.144223 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3858 00:22:06.147797 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3859 00:22:06.154311 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3860 00:22:06.157698 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3861 00:22:06.160805 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3862 00:22:06.164232 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3863 00:22:06.170724 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3864 00:22:06.174083 ===================================
3865 00:22:06.174162 LPDDR4 DRAM CONFIGURATION
3866 00:22:06.177538 ===================================
3867 00:22:06.180830 EX_ROW_EN[0] = 0x0
3868 00:22:06.184319 EX_ROW_EN[1] = 0x0
3869 00:22:06.184402 LP4Y_EN = 0x0
3870 00:22:06.187760 WORK_FSP = 0x0
3871 00:22:06.187836 WL = 0x2
3872 00:22:06.190749 RL = 0x2
3873 00:22:06.190826 BL = 0x2
3874 00:22:06.194351 RPST = 0x0
3875 00:22:06.194428 RD_PRE = 0x0
3876 00:22:06.197337 WR_PRE = 0x1
3877 00:22:06.197413 WR_PST = 0x0
3878 00:22:06.200677 DBI_WR = 0x0
3879 00:22:06.200789 DBI_RD = 0x0
3880 00:22:06.203946 OTF = 0x1
3881 00:22:06.207456 ===================================
3882 00:22:06.210785 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3883 00:22:06.214161 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3884 00:22:06.220963 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3885 00:22:06.224184 ===================================
3886 00:22:06.224263 LPDDR4 DRAM CONFIGURATION
3887 00:22:06.227382 ===================================
3888 00:22:06.230948 EX_ROW_EN[0] = 0x10
3889 00:22:06.233809 EX_ROW_EN[1] = 0x0
3890 00:22:06.233887 LP4Y_EN = 0x0
3891 00:22:06.237206 WORK_FSP = 0x0
3892 00:22:06.237285 WL = 0x2
3893 00:22:06.240909 RL = 0x2
3894 00:22:06.240987 BL = 0x2
3895 00:22:06.244080 RPST = 0x0
3896 00:22:06.244157 RD_PRE = 0x0
3897 00:22:06.247701 WR_PRE = 0x1
3898 00:22:06.247778 WR_PST = 0x0
3899 00:22:06.250810 DBI_WR = 0x0
3900 00:22:06.250887 DBI_RD = 0x0
3901 00:22:06.254100 OTF = 0x1
3902 00:22:06.257364 ===================================
3903 00:22:06.263979 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3904 00:22:06.267597 nWR fixed to 30
3905 00:22:06.267677 [ModeRegInit_LP4] CH0 RK0
3906 00:22:06.270481 [ModeRegInit_LP4] CH0 RK1
3907 00:22:06.273881 [ModeRegInit_LP4] CH1 RK0
3908 00:22:06.277365 [ModeRegInit_LP4] CH1 RK1
3909 00:22:06.277443 match AC timing 17
3910 00:22:06.283639 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3911 00:22:06.287145 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3912 00:22:06.290858 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3913 00:22:06.297101 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3914 00:22:06.300596 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3915 00:22:06.300676 ==
3916 00:22:06.303905 Dram Type= 6, Freq= 0, CH_0, rank 0
3917 00:22:06.307311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3918 00:22:06.307390 ==
3919 00:22:06.313950 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3920 00:22:06.320414 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3921 00:22:06.323959 [CA 0] Center 36 (6~67) winsize 62
3922 00:22:06.327333 [CA 1] Center 36 (6~67) winsize 62
3923 00:22:06.330222 [CA 2] Center 34 (4~65) winsize 62
3924 00:22:06.333783 [CA 3] Center 34 (3~65) winsize 63
3925 00:22:06.336957 [CA 4] Center 34 (3~65) winsize 63
3926 00:22:06.340302 [CA 5] Center 33 (3~64) winsize 62
3927 00:22:06.340379
3928 00:22:06.343540 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3929 00:22:06.343618
3930 00:22:06.346998 [CATrainingPosCal] consider 1 rank data
3931 00:22:06.350305 u2DelayCellTimex100 = 270/100 ps
3932 00:22:06.353721 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3933 00:22:06.357183 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3934 00:22:06.360618 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3935 00:22:06.363848 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3936 00:22:06.366974 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
3937 00:22:06.370116 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3938 00:22:06.370193
3939 00:22:06.373519 CA PerBit enable=1, Macro0, CA PI delay=33
3940 00:22:06.376865
3941 00:22:06.376943 [CBTSetCACLKResult] CA Dly = 33
3942 00:22:06.380527 CS Dly: 5 (0~36)
3943 00:22:06.380604 ==
3944 00:22:06.383842 Dram Type= 6, Freq= 0, CH_0, rank 1
3945 00:22:06.386795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3946 00:22:06.386873 ==
3947 00:22:06.393805 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3948 00:22:06.400352 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3949 00:22:06.403558 [CA 0] Center 36 (6~67) winsize 62
3950 00:22:06.406784 [CA 1] Center 36 (6~67) winsize 62
3951 00:22:06.410282 [CA 2] Center 35 (5~66) winsize 62
3952 00:22:06.413717 [CA 3] Center 35 (4~66) winsize 63
3953 00:22:06.416754 [CA 4] Center 34 (3~65) winsize 63
3954 00:22:06.420300 [CA 5] Center 34 (3~65) winsize 63
3955 00:22:06.420378
3956 00:22:06.423789 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3957 00:22:06.423867
3958 00:22:06.427069 [CATrainingPosCal] consider 2 rank data
3959 00:22:06.430238 u2DelayCellTimex100 = 270/100 ps
3960 00:22:06.433752 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3961 00:22:06.437208 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3962 00:22:06.440355 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
3963 00:22:06.443777 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3964 00:22:06.447023 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
3965 00:22:06.450339 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3966 00:22:06.450417
3967 00:22:06.456651 CA PerBit enable=1, Macro0, CA PI delay=33
3968 00:22:06.456739
3969 00:22:06.456800 [CBTSetCACLKResult] CA Dly = 33
3970 00:22:06.460130 CS Dly: 5 (0~37)
3971 00:22:06.460208
3972 00:22:06.463698 ----->DramcWriteLeveling(PI) begin...
3973 00:22:06.463777 ==
3974 00:22:06.466919 Dram Type= 6, Freq= 0, CH_0, rank 0
3975 00:22:06.470393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3976 00:22:06.470472 ==
3977 00:22:06.473270 Write leveling (Byte 0): 33 => 33
3978 00:22:06.476677 Write leveling (Byte 1): 33 => 33
3979 00:22:06.480283 DramcWriteLeveling(PI) end<-----
3980 00:22:06.480360
3981 00:22:06.480419 ==
3982 00:22:06.483224 Dram Type= 6, Freq= 0, CH_0, rank 0
3983 00:22:06.489864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3984 00:22:06.489942 ==
3985 00:22:06.490003 [Gating] SW mode calibration
3986 00:22:06.499622 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3987 00:22:06.503181 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3988 00:22:06.506609 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3989 00:22:06.513271 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3990 00:22:06.516852 0 9 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
3991 00:22:06.519703 0 9 12 | B1->B0 | 3333 2929 | 1 0 | (1 1) (0 0)
3992 00:22:06.526737 0 9 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (1 0)
3993 00:22:06.530070 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3994 00:22:06.533527 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3995 00:22:06.539775 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3996 00:22:06.543002 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3997 00:22:06.546442 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3998 00:22:06.553383 0 10 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
3999 00:22:06.556689 0 10 12 | B1->B0 | 2e2e 3d3d | 0 1 | (0 0) (0 0)
4000 00:22:06.560039 0 10 16 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
4001 00:22:06.566306 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4002 00:22:06.569692 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4003 00:22:06.573098 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4004 00:22:06.579899 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4005 00:22:06.583118 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4006 00:22:06.586278 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4007 00:22:06.592959 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4008 00:22:06.596188 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4009 00:22:06.599708 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 00:22:06.602752 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 00:22:06.609676 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 00:22:06.612732 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 00:22:06.616265 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 00:22:06.623036 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 00:22:06.626029 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 00:22:06.629412 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 00:22:06.636461 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 00:22:06.639276 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 00:22:06.642705 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 00:22:06.649386 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 00:22:06.652723 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 00:22:06.655943 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 00:22:06.662508 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4024 00:22:06.662585 Total UI for P1: 0, mck2ui 16
4025 00:22:06.669561 best dqsien dly found for B0: ( 0, 13, 10)
4026 00:22:06.672463 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4027 00:22:06.675966 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4028 00:22:06.679326 Total UI for P1: 0, mck2ui 16
4029 00:22:06.682898 best dqsien dly found for B1: ( 0, 13, 18)
4030 00:22:06.685786 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4031 00:22:06.689270 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4032 00:22:06.689346
4033 00:22:06.695758 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4034 00:22:06.699522 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4035 00:22:06.699600 [Gating] SW calibration Done
4036 00:22:06.702665 ==
4037 00:22:06.706052 Dram Type= 6, Freq= 0, CH_0, rank 0
4038 00:22:06.709166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4039 00:22:06.709244 ==
4040 00:22:06.709303 RX Vref Scan: 0
4041 00:22:06.709358
4042 00:22:06.712668 RX Vref 0 -> 0, step: 1
4043 00:22:06.712795
4044 00:22:06.716272 RX Delay -230 -> 252, step: 16
4045 00:22:06.719321 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4046 00:22:06.722672 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4047 00:22:06.729045 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4048 00:22:06.732487 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4049 00:22:06.736016 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4050 00:22:06.739638 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4051 00:22:06.746044 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4052 00:22:06.748883 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4053 00:22:06.752701 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4054 00:22:06.755753 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4055 00:22:06.759175 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4056 00:22:06.765364 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4057 00:22:06.769052 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4058 00:22:06.772509 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4059 00:22:06.775745 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4060 00:22:06.782250 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4061 00:22:06.782328 ==
4062 00:22:06.785778 Dram Type= 6, Freq= 0, CH_0, rank 0
4063 00:22:06.788808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4064 00:22:06.788885 ==
4065 00:22:06.788943 DQS Delay:
4066 00:22:06.792304 DQS0 = 0, DQS1 = 0
4067 00:22:06.792379 DQM Delay:
4068 00:22:06.795189 DQM0 = 52, DQM1 = 42
4069 00:22:06.795265 DQ Delay:
4070 00:22:06.798770 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4071 00:22:06.802173 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4072 00:22:06.805093 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =33
4073 00:22:06.808577 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =49
4074 00:22:06.808676
4075 00:22:06.808785
4076 00:22:06.808840 ==
4077 00:22:06.811841 Dram Type= 6, Freq= 0, CH_0, rank 0
4078 00:22:06.815276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4079 00:22:06.818855 ==
4080 00:22:06.818932
4081 00:22:06.818990
4082 00:22:06.819045 TX Vref Scan disable
4083 00:22:06.821711 == TX Byte 0 ==
4084 00:22:06.825265 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4085 00:22:06.828886 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4086 00:22:06.831882 == TX Byte 1 ==
4087 00:22:06.835400 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4088 00:22:06.838608 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4089 00:22:06.842166 ==
4090 00:22:06.845489 Dram Type= 6, Freq= 0, CH_0, rank 0
4091 00:22:06.848426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4092 00:22:06.848528 ==
4093 00:22:06.848616
4094 00:22:06.848699
4095 00:22:06.851908 TX Vref Scan disable
4096 00:22:06.851987 == TX Byte 0 ==
4097 00:22:06.858741 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4098 00:22:06.862056 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4099 00:22:06.862132 == TX Byte 1 ==
4100 00:22:06.868465 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4101 00:22:06.871581 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4102 00:22:06.871657
4103 00:22:06.871719 [DATLAT]
4104 00:22:06.875243 Freq=600, CH0 RK0
4105 00:22:06.875320
4106 00:22:06.875378 DATLAT Default: 0x9
4107 00:22:06.878712 0, 0xFFFF, sum = 0
4108 00:22:06.878790 1, 0xFFFF, sum = 0
4109 00:22:06.881782 2, 0xFFFF, sum = 0
4110 00:22:06.881859 3, 0xFFFF, sum = 0
4111 00:22:06.885179 4, 0xFFFF, sum = 0
4112 00:22:06.885256 5, 0xFFFF, sum = 0
4113 00:22:06.888618 6, 0xFFFF, sum = 0
4114 00:22:06.888746 7, 0xFFFF, sum = 0
4115 00:22:06.891700 8, 0x0, sum = 1
4116 00:22:06.891785 9, 0x0, sum = 2
4117 00:22:06.895033 10, 0x0, sum = 3
4118 00:22:06.895111 11, 0x0, sum = 4
4119 00:22:06.898575 best_step = 9
4120 00:22:06.898651
4121 00:22:06.898709 ==
4122 00:22:06.902033 Dram Type= 6, Freq= 0, CH_0, rank 0
4123 00:22:06.905391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4124 00:22:06.905468 ==
4125 00:22:06.908459 RX Vref Scan: 1
4126 00:22:06.908558
4127 00:22:06.908643 RX Vref 0 -> 0, step: 1
4128 00:22:06.908746
4129 00:22:06.911976 RX Delay -179 -> 252, step: 8
4130 00:22:06.912052
4131 00:22:06.914968 Set Vref, RX VrefLevel [Byte0]: 59
4132 00:22:06.918277 [Byte1]: 50
4133 00:22:06.921923
4134 00:22:06.922014 Final RX Vref Byte 0 = 59 to rank0
4135 00:22:06.925297 Final RX Vref Byte 1 = 50 to rank0
4136 00:22:06.928678 Final RX Vref Byte 0 = 59 to rank1
4137 00:22:06.931838 Final RX Vref Byte 1 = 50 to rank1==
4138 00:22:06.935501 Dram Type= 6, Freq= 0, CH_0, rank 0
4139 00:22:06.938800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4140 00:22:06.942163 ==
4141 00:22:06.942241 DQS Delay:
4142 00:22:06.942301 DQS0 = 0, DQS1 = 0
4143 00:22:06.945734 DQM Delay:
4144 00:22:06.945811 DQM0 = 49, DQM1 = 39
4145 00:22:06.948760 DQ Delay:
4146 00:22:06.952232 DQ0 =48, DQ1 =48, DQ2 =48, DQ3 =44
4147 00:22:06.952310 DQ4 =52, DQ5 =40, DQ6 =60, DQ7 =56
4148 00:22:06.955772 DQ8 =36, DQ9 =24, DQ10 =36, DQ11 =32
4149 00:22:06.958757 DQ12 =44, DQ13 =40, DQ14 =52, DQ15 =48
4150 00:22:06.962149
4151 00:22:06.962225
4152 00:22:06.968872 [DQSOSCAuto] RK0, (LSB)MR18= 0x615b, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 391 ps
4153 00:22:06.972107 CH0 RK0: MR19=808, MR18=615B
4154 00:22:06.978588 CH0_RK0: MR19=0x808, MR18=0x615B, DQSOSC=391, MR23=63, INC=171, DEC=114
4155 00:22:06.978667
4156 00:22:06.982340 ----->DramcWriteLeveling(PI) begin...
4157 00:22:06.982419 ==
4158 00:22:06.985641 Dram Type= 6, Freq= 0, CH_0, rank 1
4159 00:22:06.989008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4160 00:22:06.989088 ==
4161 00:22:06.992118 Write leveling (Byte 0): 33 => 33
4162 00:22:06.995114 Write leveling (Byte 1): 33 => 33
4163 00:22:06.998740 DramcWriteLeveling(PI) end<-----
4164 00:22:06.998818
4165 00:22:06.998879 ==
4166 00:22:07.002058 Dram Type= 6, Freq= 0, CH_0, rank 1
4167 00:22:07.004929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4168 00:22:07.005007 ==
4169 00:22:07.008462 [Gating] SW mode calibration
4170 00:22:07.014992 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4171 00:22:07.022000 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4172 00:22:07.025362 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4173 00:22:07.028220 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4174 00:22:07.035413 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4175 00:22:07.038481 0 9 12 | B1->B0 | 3030 3232 | 1 1 | (1 1) (0 0)
4176 00:22:07.041640 0 9 16 | B1->B0 | 2626 2323 | 0 0 | (0 0) (1 0)
4177 00:22:07.048625 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4178 00:22:07.051981 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4179 00:22:07.055295 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4180 00:22:07.061736 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4181 00:22:07.065156 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4182 00:22:07.068097 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4183 00:22:07.074946 0 10 12 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (0 0)
4184 00:22:07.078674 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4185 00:22:07.081595 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4186 00:22:07.088369 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4187 00:22:07.091443 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4188 00:22:07.094687 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4189 00:22:07.101338 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4190 00:22:07.104693 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4191 00:22:07.108305 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4192 00:22:07.114732 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 00:22:07.118230 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 00:22:07.121789 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 00:22:07.128220 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 00:22:07.131223 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 00:22:07.134688 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 00:22:07.141405 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 00:22:07.144613 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 00:22:07.147905 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 00:22:07.154591 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 00:22:07.158015 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 00:22:07.161230 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 00:22:07.165016 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 00:22:07.171622 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 00:22:07.174935 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 00:22:07.177752 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4208 00:22:07.181668 Total UI for P1: 0, mck2ui 16
4209 00:22:07.184509 best dqsien dly found for B0: ( 0, 13, 10)
4210 00:22:07.191310 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4211 00:22:07.194902 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4212 00:22:07.198182 Total UI for P1: 0, mck2ui 16
4213 00:22:07.201217 best dqsien dly found for B1: ( 0, 13, 14)
4214 00:22:07.204664 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4215 00:22:07.207811 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4216 00:22:07.207887
4217 00:22:07.211515 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4218 00:22:07.214406 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4219 00:22:07.217847 [Gating] SW calibration Done
4220 00:22:07.217925 ==
4221 00:22:07.220953 Dram Type= 6, Freq= 0, CH_0, rank 1
4222 00:22:07.228360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4223 00:22:07.228438 ==
4224 00:22:07.228498 RX Vref Scan: 0
4225 00:22:07.228551
4226 00:22:07.231397 RX Vref 0 -> 0, step: 1
4227 00:22:07.231472
4228 00:22:07.234805 RX Delay -230 -> 252, step: 16
4229 00:22:07.237789 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4230 00:22:07.240943 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4231 00:22:07.244310 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4232 00:22:07.251367 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4233 00:22:07.254437 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4234 00:22:07.258222 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4235 00:22:07.261487 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4236 00:22:07.264296 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4237 00:22:07.271121 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4238 00:22:07.274384 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4239 00:22:07.278001 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4240 00:22:07.281507 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4241 00:22:07.287829 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4242 00:22:07.291280 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4243 00:22:07.294305 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4244 00:22:07.297821 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4245 00:22:07.297900 ==
4246 00:22:07.300925 Dram Type= 6, Freq= 0, CH_0, rank 1
4247 00:22:07.307871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4248 00:22:07.307957 ==
4249 00:22:07.308035 DQS Delay:
4250 00:22:07.311387 DQS0 = 0, DQS1 = 0
4251 00:22:07.311466 DQM Delay:
4252 00:22:07.311544 DQM0 = 49, DQM1 = 40
4253 00:22:07.314699 DQ Delay:
4254 00:22:07.317918 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =41
4255 00:22:07.321389 DQ4 =49, DQ5 =41, DQ6 =65, DQ7 =65
4256 00:22:07.324253 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =41
4257 00:22:07.327914 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =49
4258 00:22:07.327992
4259 00:22:07.328069
4260 00:22:07.328141 ==
4261 00:22:07.331240 Dram Type= 6, Freq= 0, CH_0, rank 1
4262 00:22:07.334254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4263 00:22:07.334333 ==
4264 00:22:07.334411
4265 00:22:07.334482
4266 00:22:07.337911 TX Vref Scan disable
4267 00:22:07.337989 == TX Byte 0 ==
4268 00:22:07.344685 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4269 00:22:07.347588 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4270 00:22:07.347668 == TX Byte 1 ==
4271 00:22:07.354391 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4272 00:22:07.357686 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4273 00:22:07.357765 ==
4274 00:22:07.360946 Dram Type= 6, Freq= 0, CH_0, rank 1
4275 00:22:07.364751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4276 00:22:07.364832 ==
4277 00:22:07.364910
4278 00:22:07.364982
4279 00:22:07.367729 TX Vref Scan disable
4280 00:22:07.371077 == TX Byte 0 ==
4281 00:22:07.374640 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4282 00:22:07.377842 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4283 00:22:07.380992 == TX Byte 1 ==
4284 00:22:07.384160 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4285 00:22:07.387489 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4286 00:22:07.391188
4287 00:22:07.391266 [DATLAT]
4288 00:22:07.391344 Freq=600, CH0 RK1
4289 00:22:07.391417
4290 00:22:07.394128 DATLAT Default: 0x9
4291 00:22:07.394207 0, 0xFFFF, sum = 0
4292 00:22:07.397638 1, 0xFFFF, sum = 0
4293 00:22:07.397718 2, 0xFFFF, sum = 0
4294 00:22:07.401097 3, 0xFFFF, sum = 0
4295 00:22:07.401176 4, 0xFFFF, sum = 0
4296 00:22:07.404420 5, 0xFFFF, sum = 0
4297 00:22:07.407502 6, 0xFFFF, sum = 0
4298 00:22:07.407583 7, 0xFFFF, sum = 0
4299 00:22:07.407661 8, 0x0, sum = 1
4300 00:22:07.411064 9, 0x0, sum = 2
4301 00:22:07.411144 10, 0x0, sum = 3
4302 00:22:07.414389 11, 0x0, sum = 4
4303 00:22:07.414469 best_step = 9
4304 00:22:07.414558
4305 00:22:07.414644 ==
4306 00:22:07.417297 Dram Type= 6, Freq= 0, CH_0, rank 1
4307 00:22:07.424197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4308 00:22:07.424277 ==
4309 00:22:07.424335 RX Vref Scan: 0
4310 00:22:07.424389
4311 00:22:07.427297 RX Vref 0 -> 0, step: 1
4312 00:22:07.427372
4313 00:22:07.430797 RX Delay -179 -> 252, step: 8
4314 00:22:07.434057 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4315 00:22:07.440628 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4316 00:22:07.443981 iDelay=205, Bit 2, Center 44 (-99 ~ 188) 288
4317 00:22:07.447235 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4318 00:22:07.450789 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4319 00:22:07.454217 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4320 00:22:07.460587 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4321 00:22:07.464123 iDelay=205, Bit 7, Center 56 (-91 ~ 204) 296
4322 00:22:07.467083 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4323 00:22:07.470834 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4324 00:22:07.473795 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4325 00:22:07.480346 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4326 00:22:07.483965 iDelay=205, Bit 12, Center 40 (-107 ~ 188) 296
4327 00:22:07.487298 iDelay=205, Bit 13, Center 44 (-99 ~ 188) 288
4328 00:22:07.490450 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4329 00:22:07.497052 iDelay=205, Bit 15, Center 44 (-99 ~ 188) 288
4330 00:22:07.497129 ==
4331 00:22:07.500288 Dram Type= 6, Freq= 0, CH_0, rank 1
4332 00:22:07.503594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4333 00:22:07.503671 ==
4334 00:22:07.503729 DQS Delay:
4335 00:22:07.507313 DQS0 = 0, DQS1 = 0
4336 00:22:07.507387 DQM Delay:
4337 00:22:07.510901 DQM0 = 48, DQM1 = 39
4338 00:22:07.510976 DQ Delay:
4339 00:22:07.513692 DQ0 =48, DQ1 =48, DQ2 =44, DQ3 =44
4340 00:22:07.517062 DQ4 =48, DQ5 =40, DQ6 =56, DQ7 =56
4341 00:22:07.520392 DQ8 =32, DQ9 =28, DQ10 =40, DQ11 =36
4342 00:22:07.523924 DQ12 =40, DQ13 =44, DQ14 =48, DQ15 =44
4343 00:22:07.523999
4344 00:22:07.524057
4345 00:22:07.530635 [DQSOSCAuto] RK1, (LSB)MR18= 0x6c38, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 389 ps
4346 00:22:07.533894 CH0 RK1: MR19=808, MR18=6C38
4347 00:22:07.540394 CH0_RK1: MR19=0x808, MR18=0x6C38, DQSOSC=389, MR23=63, INC=173, DEC=115
4348 00:22:07.543763 [RxdqsGatingPostProcess] freq 600
4349 00:22:07.550164 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4350 00:22:07.553470 Pre-setting of DQS Precalculation
4351 00:22:07.556804 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4352 00:22:07.556880 ==
4353 00:22:07.560304 Dram Type= 6, Freq= 0, CH_1, rank 0
4354 00:22:07.563843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4355 00:22:07.563919 ==
4356 00:22:07.570253 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4357 00:22:07.577218 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
4358 00:22:07.580306 [CA 0] Center 35 (5~66) winsize 62
4359 00:22:07.583995 [CA 1] Center 35 (5~66) winsize 62
4360 00:22:07.586860 [CA 2] Center 34 (4~65) winsize 62
4361 00:22:07.590216 [CA 3] Center 34 (3~65) winsize 63
4362 00:22:07.593684 [CA 4] Center 34 (4~65) winsize 62
4363 00:22:07.597080 [CA 5] Center 33 (3~64) winsize 62
4364 00:22:07.597156
4365 00:22:07.600361 [CmdBusTrainingLP45] Vref(ca) range 1: 31
4366 00:22:07.600437
4367 00:22:07.603863 [CATrainingPosCal] consider 1 rank data
4368 00:22:07.606833 u2DelayCellTimex100 = 270/100 ps
4369 00:22:07.610333 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4370 00:22:07.613882 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4371 00:22:07.616950 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4372 00:22:07.620514 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4373 00:22:07.623615 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4374 00:22:07.626953 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4375 00:22:07.627030
4376 00:22:07.633936 CA PerBit enable=1, Macro0, CA PI delay=33
4377 00:22:07.634013
4378 00:22:07.634071 [CBTSetCACLKResult] CA Dly = 33
4379 00:22:07.636927 CS Dly: 4 (0~35)
4380 00:22:07.637003 ==
4381 00:22:07.640227 Dram Type= 6, Freq= 0, CH_1, rank 1
4382 00:22:07.643894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4383 00:22:07.643972 ==
4384 00:22:07.650277 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4385 00:22:07.657050 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4386 00:22:07.660252 [CA 0] Center 35 (5~66) winsize 62
4387 00:22:07.663837 [CA 1] Center 35 (5~66) winsize 62
4388 00:22:07.666774 [CA 2] Center 34 (4~65) winsize 62
4389 00:22:07.670237 [CA 3] Center 34 (4~65) winsize 62
4390 00:22:07.673771 [CA 4] Center 34 (4~65) winsize 62
4391 00:22:07.676737 [CA 5] Center 33 (3~64) winsize 62
4392 00:22:07.676812
4393 00:22:07.680238 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4394 00:22:07.680313
4395 00:22:07.683486 [CATrainingPosCal] consider 2 rank data
4396 00:22:07.686750 u2DelayCellTimex100 = 270/100 ps
4397 00:22:07.690234 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4398 00:22:07.693753 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4399 00:22:07.696833 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4400 00:22:07.700232 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4401 00:22:07.703658 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4402 00:22:07.706669 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4403 00:22:07.710195
4404 00:22:07.713403 CA PerBit enable=1, Macro0, CA PI delay=33
4405 00:22:07.713479
4406 00:22:07.717086 [CBTSetCACLKResult] CA Dly = 33
4407 00:22:07.717162 CS Dly: 4 (0~36)
4408 00:22:07.717221
4409 00:22:07.720181 ----->DramcWriteLeveling(PI) begin...
4410 00:22:07.720257 ==
4411 00:22:07.723590 Dram Type= 6, Freq= 0, CH_1, rank 0
4412 00:22:07.726648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4413 00:22:07.730065 ==
4414 00:22:07.730144 Write leveling (Byte 0): 29 => 29
4415 00:22:07.733598 Write leveling (Byte 1): 32 => 32
4416 00:22:07.736919 DramcWriteLeveling(PI) end<-----
4417 00:22:07.736998
4418 00:22:07.737075 ==
4419 00:22:07.740480 Dram Type= 6, Freq= 0, CH_1, rank 0
4420 00:22:07.746599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4421 00:22:07.746707 ==
4422 00:22:07.746804 [Gating] SW mode calibration
4423 00:22:07.756964 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4424 00:22:07.760065 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4425 00:22:07.763619 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4426 00:22:07.770056 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4427 00:22:07.773553 0 9 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
4428 00:22:07.776402 0 9 12 | B1->B0 | 2e2e 2727 | 0 0 | (1 0) (1 0)
4429 00:22:07.783281 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4430 00:22:07.786681 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4431 00:22:07.789768 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4432 00:22:07.796630 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4433 00:22:07.799678 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4434 00:22:07.803150 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4435 00:22:07.809902 0 10 8 | B1->B0 | 2929 2c2c | 0 0 | (1 1) (0 0)
4436 00:22:07.813195 0 10 12 | B1->B0 | 3d3d 3d3d | 0 1 | (0 0) (0 0)
4437 00:22:07.816220 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4438 00:22:07.823114 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4439 00:22:07.826286 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4440 00:22:07.829734 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4441 00:22:07.836239 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4442 00:22:07.839686 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4443 00:22:07.843201 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4444 00:22:07.849346 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 00:22:07.853120 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 00:22:07.856552 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 00:22:07.862725 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 00:22:07.866117 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 00:22:07.869778 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 00:22:07.876235 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 00:22:07.879342 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 00:22:07.883054 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 00:22:07.889573 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 00:22:07.892572 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 00:22:07.896028 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 00:22:07.902815 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 00:22:07.905984 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 00:22:07.909233 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 00:22:07.912624 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4460 00:22:07.919495 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4461 00:22:07.922426 Total UI for P1: 0, mck2ui 16
4462 00:22:07.926126 best dqsien dly found for B0: ( 0, 13, 8)
4463 00:22:07.929043 Total UI for P1: 0, mck2ui 16
4464 00:22:07.932578 best dqsien dly found for B1: ( 0, 13, 10)
4465 00:22:07.935843 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4466 00:22:07.939120 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4467 00:22:07.939196
4468 00:22:07.942356 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4469 00:22:07.945744 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4470 00:22:07.949207 [Gating] SW calibration Done
4471 00:22:07.949283 ==
4472 00:22:07.952715 Dram Type= 6, Freq= 0, CH_1, rank 0
4473 00:22:07.955981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4474 00:22:07.956059 ==
4475 00:22:07.959403 RX Vref Scan: 0
4476 00:22:07.959479
4477 00:22:07.962297 RX Vref 0 -> 0, step: 1
4478 00:22:07.962372
4479 00:22:07.962431 RX Delay -230 -> 252, step: 16
4480 00:22:07.968834 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4481 00:22:07.972220 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4482 00:22:07.975791 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4483 00:22:07.979171 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4484 00:22:07.985768 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4485 00:22:07.989213 iDelay=218, Bit 5, Center 57 (-86 ~ 201) 288
4486 00:22:07.992304 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4487 00:22:07.995720 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4488 00:22:07.998753 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4489 00:22:08.005778 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4490 00:22:08.009181 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4491 00:22:08.012831 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4492 00:22:08.015659 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4493 00:22:08.022042 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4494 00:22:08.025412 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4495 00:22:08.029076 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4496 00:22:08.029181 ==
4497 00:22:08.032256 Dram Type= 6, Freq= 0, CH_1, rank 0
4498 00:22:08.035538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4499 00:22:08.035639 ==
4500 00:22:08.039093 DQS Delay:
4501 00:22:08.039190 DQS0 = 0, DQS1 = 0
4502 00:22:08.042455 DQM Delay:
4503 00:22:08.042529 DQM0 = 49, DQM1 = 42
4504 00:22:08.042586 DQ Delay:
4505 00:22:08.045642 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =41
4506 00:22:08.048898 DQ4 =49, DQ5 =57, DQ6 =65, DQ7 =41
4507 00:22:08.052258 DQ8 =25, DQ9 =33, DQ10 =41, DQ11 =41
4508 00:22:08.055194 DQ12 =57, DQ13 =57, DQ14 =41, DQ15 =41
4509 00:22:08.055268
4510 00:22:08.055326
4511 00:22:08.058586 ==
4512 00:22:08.058660 Dram Type= 6, Freq= 0, CH_1, rank 0
4513 00:22:08.065389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4514 00:22:08.065464 ==
4515 00:22:08.065522
4516 00:22:08.065574
4517 00:22:08.068845 TX Vref Scan disable
4518 00:22:08.068920 == TX Byte 0 ==
4519 00:22:08.072179 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4520 00:22:08.078947 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4521 00:22:08.079022 == TX Byte 1 ==
4522 00:22:08.082415 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4523 00:22:08.088859 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4524 00:22:08.088933 ==
4525 00:22:08.092228 Dram Type= 6, Freq= 0, CH_1, rank 0
4526 00:22:08.095705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4527 00:22:08.095795 ==
4528 00:22:08.095865
4529 00:22:08.095918
4530 00:22:08.098734 TX Vref Scan disable
4531 00:22:08.102173 == TX Byte 0 ==
4532 00:22:08.105179 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4533 00:22:08.108579 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4534 00:22:08.111969 == TX Byte 1 ==
4535 00:22:08.115449 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4536 00:22:08.118422 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4537 00:22:08.118499
4538 00:22:08.121952 [DATLAT]
4539 00:22:08.122027 Freq=600, CH1 RK0
4540 00:22:08.122086
4541 00:22:08.125264 DATLAT Default: 0x9
4542 00:22:08.125340 0, 0xFFFF, sum = 0
4543 00:22:08.128407 1, 0xFFFF, sum = 0
4544 00:22:08.128484 2, 0xFFFF, sum = 0
4545 00:22:08.131839 3, 0xFFFF, sum = 0
4546 00:22:08.131917 4, 0xFFFF, sum = 0
4547 00:22:08.135741 5, 0xFFFF, sum = 0
4548 00:22:08.135819 6, 0xFFFF, sum = 0
4549 00:22:08.138600 7, 0xFFFF, sum = 0
4550 00:22:08.138677 8, 0x0, sum = 1
4551 00:22:08.141965 9, 0x0, sum = 2
4552 00:22:08.142042 10, 0x0, sum = 3
4553 00:22:08.145137 11, 0x0, sum = 4
4554 00:22:08.145215 best_step = 9
4555 00:22:08.145274
4556 00:22:08.145327 ==
4557 00:22:08.148296 Dram Type= 6, Freq= 0, CH_1, rank 0
4558 00:22:08.151957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4559 00:22:08.155199 ==
4560 00:22:08.155330 RX Vref Scan: 1
4561 00:22:08.155388
4562 00:22:08.158360 RX Vref 0 -> 0, step: 1
4563 00:22:08.158435
4564 00:22:08.161677 RX Delay -179 -> 252, step: 8
4565 00:22:08.161752
4566 00:22:08.165063 Set Vref, RX VrefLevel [Byte0]: 50
4567 00:22:08.165139 [Byte1]: 52
4568 00:22:08.170034
4569 00:22:08.170109 Final RX Vref Byte 0 = 50 to rank0
4570 00:22:08.173329 Final RX Vref Byte 1 = 52 to rank0
4571 00:22:08.176692 Final RX Vref Byte 0 = 50 to rank1
4572 00:22:08.179829 Final RX Vref Byte 1 = 52 to rank1==
4573 00:22:08.183276 Dram Type= 6, Freq= 0, CH_1, rank 0
4574 00:22:08.189669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4575 00:22:08.189747 ==
4576 00:22:08.189806 DQS Delay:
4577 00:22:08.193092 DQS0 = 0, DQS1 = 0
4578 00:22:08.193169 DQM Delay:
4579 00:22:08.193229 DQM0 = 48, DQM1 = 40
4580 00:22:08.196528 DQ Delay:
4581 00:22:08.199614 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4582 00:22:08.202959 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =44
4583 00:22:08.206501 DQ8 =28, DQ9 =24, DQ10 =48, DQ11 =32
4584 00:22:08.209573 DQ12 =52, DQ13 =48, DQ14 =44, DQ15 =44
4585 00:22:08.209648
4586 00:22:08.209707
4587 00:22:08.216421 [DQSOSCAuto] RK0, (LSB)MR18= 0x557b, (MSB)MR19= 0x808, tDQSOscB0 = 386 ps tDQSOscB1 = 393 ps
4588 00:22:08.219877 CH1 RK0: MR19=808, MR18=557B
4589 00:22:08.226248 CH1_RK0: MR19=0x808, MR18=0x557B, DQSOSC=386, MR23=63, INC=176, DEC=117
4590 00:22:08.226324
4591 00:22:08.229773 ----->DramcWriteLeveling(PI) begin...
4592 00:22:08.229849 ==
4593 00:22:08.232623 Dram Type= 6, Freq= 0, CH_1, rank 1
4594 00:22:08.236194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4595 00:22:08.236270 ==
4596 00:22:08.239788 Write leveling (Byte 0): 28 => 28
4597 00:22:08.243060 Write leveling (Byte 1): 29 => 29
4598 00:22:08.246178 DramcWriteLeveling(PI) end<-----
4599 00:22:08.246254
4600 00:22:08.246312 ==
4601 00:22:08.249264 Dram Type= 6, Freq= 0, CH_1, rank 1
4602 00:22:08.252669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4603 00:22:08.255928 ==
4604 00:22:08.256003 [Gating] SW mode calibration
4605 00:22:08.262579 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4606 00:22:08.269190 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4607 00:22:08.272624 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4608 00:22:08.279555 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4609 00:22:08.282572 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4610 00:22:08.286109 0 9 12 | B1->B0 | 2828 3333 | 1 0 | (0 0) (1 1)
4611 00:22:08.292535 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4612 00:22:08.295639 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4613 00:22:08.299296 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4614 00:22:08.305783 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4615 00:22:08.309434 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4616 00:22:08.312603 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4617 00:22:08.319074 0 10 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4618 00:22:08.322927 0 10 12 | B1->B0 | 4040 3333 | 0 0 | (1 1) (0 0)
4619 00:22:08.325838 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4620 00:22:08.329205 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4621 00:22:08.335556 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4622 00:22:08.339377 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4623 00:22:08.342379 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4624 00:22:08.349321 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4625 00:22:08.352768 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4626 00:22:08.355564 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4627 00:22:08.362416 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 00:22:08.365667 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 00:22:08.369244 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 00:22:08.375836 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 00:22:08.379317 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 00:22:08.382599 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 00:22:08.389111 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 00:22:08.392637 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 00:22:08.395606 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 00:22:08.402293 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 00:22:08.405787 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 00:22:08.409248 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 00:22:08.415675 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 00:22:08.419054 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 00:22:08.422058 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4642 00:22:08.428977 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4643 00:22:08.432342 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4644 00:22:08.435740 Total UI for P1: 0, mck2ui 16
4645 00:22:08.439216 best dqsien dly found for B0: ( 0, 13, 10)
4646 00:22:08.442019 Total UI for P1: 0, mck2ui 16
4647 00:22:08.445439 best dqsien dly found for B1: ( 0, 13, 12)
4648 00:22:08.448858 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4649 00:22:08.452215 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4650 00:22:08.452291
4651 00:22:08.455644 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4652 00:22:08.458715 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4653 00:22:08.461979 [Gating] SW calibration Done
4654 00:22:08.462055 ==
4655 00:22:08.465389 Dram Type= 6, Freq= 0, CH_1, rank 1
4656 00:22:08.468956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4657 00:22:08.469032 ==
4658 00:22:08.471866 RX Vref Scan: 0
4659 00:22:08.471942
4660 00:22:08.475510 RX Vref 0 -> 0, step: 1
4661 00:22:08.475590
4662 00:22:08.475649 RX Delay -230 -> 252, step: 16
4663 00:22:08.482182 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4664 00:22:08.485238 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4665 00:22:08.488656 iDelay=218, Bit 2, Center 41 (-102 ~ 185) 288
4666 00:22:08.492063 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4667 00:22:08.498510 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4668 00:22:08.502037 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4669 00:22:08.505379 iDelay=218, Bit 6, Center 49 (-102 ~ 201) 304
4670 00:22:08.508584 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4671 00:22:08.515273 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4672 00:22:08.518727 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4673 00:22:08.521750 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4674 00:22:08.525187 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4675 00:22:08.528652 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4676 00:22:08.535170 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4677 00:22:08.538502 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4678 00:22:08.541896 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4679 00:22:08.541971 ==
4680 00:22:08.545308 Dram Type= 6, Freq= 0, CH_1, rank 1
4681 00:22:08.548346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4682 00:22:08.551851 ==
4683 00:22:08.551926 DQS Delay:
4684 00:22:08.551985 DQS0 = 0, DQS1 = 0
4685 00:22:08.555318 DQM Delay:
4686 00:22:08.555393 DQM0 = 49, DQM1 = 46
4687 00:22:08.558364 DQ Delay:
4688 00:22:08.561728 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =49
4689 00:22:08.561803 DQ4 =49, DQ5 =57, DQ6 =49, DQ7 =49
4690 00:22:08.565140 DQ8 =25, DQ9 =33, DQ10 =49, DQ11 =41
4691 00:22:08.568191 DQ12 =57, DQ13 =49, DQ14 =57, DQ15 =57
4692 00:22:08.571709
4693 00:22:08.571783
4694 00:22:08.571841 ==
4695 00:22:08.575257 Dram Type= 6, Freq= 0, CH_1, rank 1
4696 00:22:08.578701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4697 00:22:08.578777 ==
4698 00:22:08.578836
4699 00:22:08.578889
4700 00:22:08.581715 TX Vref Scan disable
4701 00:22:08.581790 == TX Byte 0 ==
4702 00:22:08.588809 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4703 00:22:08.591909 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4704 00:22:08.591984 == TX Byte 1 ==
4705 00:22:08.598284 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4706 00:22:08.601642 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4707 00:22:08.601718 ==
4708 00:22:08.605078 Dram Type= 6, Freq= 0, CH_1, rank 1
4709 00:22:08.608399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4710 00:22:08.608505 ==
4711 00:22:08.608565
4712 00:22:08.608618
4713 00:22:08.611640 TX Vref Scan disable
4714 00:22:08.614929 == TX Byte 0 ==
4715 00:22:08.618263 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4716 00:22:08.621700 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4717 00:22:08.625004 == TX Byte 1 ==
4718 00:22:08.628369 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4719 00:22:08.631320 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4720 00:22:08.631395
4721 00:22:08.634817 [DATLAT]
4722 00:22:08.634893 Freq=600, CH1 RK1
4723 00:22:08.634952
4724 00:22:08.638292 DATLAT Default: 0x9
4725 00:22:08.638367 0, 0xFFFF, sum = 0
4726 00:22:08.641759 1, 0xFFFF, sum = 0
4727 00:22:08.641835 2, 0xFFFF, sum = 0
4728 00:22:08.644729 3, 0xFFFF, sum = 0
4729 00:22:08.644806 4, 0xFFFF, sum = 0
4730 00:22:08.648260 5, 0xFFFF, sum = 0
4731 00:22:08.648337 6, 0xFFFF, sum = 0
4732 00:22:08.651680 7, 0xFFFF, sum = 0
4733 00:22:08.651757 8, 0x0, sum = 1
4734 00:22:08.654845 9, 0x0, sum = 2
4735 00:22:08.654922 10, 0x0, sum = 3
4736 00:22:08.658347 11, 0x0, sum = 4
4737 00:22:08.658424 best_step = 9
4738 00:22:08.658482
4739 00:22:08.658535 ==
4740 00:22:08.661661 Dram Type= 6, Freq= 0, CH_1, rank 1
4741 00:22:08.668241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4742 00:22:08.668318 ==
4743 00:22:08.668377 RX Vref Scan: 0
4744 00:22:08.668432
4745 00:22:08.671736 RX Vref 0 -> 0, step: 1
4746 00:22:08.671812
4747 00:22:08.674747 RX Delay -179 -> 252, step: 8
4748 00:22:08.678132 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4749 00:22:08.681196 iDelay=205, Bit 1, Center 40 (-99 ~ 180) 280
4750 00:22:08.687920 iDelay=205, Bit 2, Center 40 (-99 ~ 180) 280
4751 00:22:08.691390 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4752 00:22:08.694779 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4753 00:22:08.697917 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4754 00:22:08.701194 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4755 00:22:08.707906 iDelay=205, Bit 7, Center 48 (-91 ~ 188) 280
4756 00:22:08.711569 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4757 00:22:08.714778 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4758 00:22:08.718277 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4759 00:22:08.721371 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4760 00:22:08.727990 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4761 00:22:08.731136 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4762 00:22:08.734589 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4763 00:22:08.737872 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4764 00:22:08.737978 ==
4765 00:22:08.741308 Dram Type= 6, Freq= 0, CH_1, rank 1
4766 00:22:08.747770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4767 00:22:08.747847 ==
4768 00:22:08.747906 DQS Delay:
4769 00:22:08.751604 DQS0 = 0, DQS1 = 0
4770 00:22:08.751681 DQM Delay:
4771 00:22:08.751740 DQM0 = 49, DQM1 = 43
4772 00:22:08.754954 DQ Delay:
4773 00:22:08.757848 DQ0 =56, DQ1 =40, DQ2 =40, DQ3 =44
4774 00:22:08.761253 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4775 00:22:08.764768 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36
4776 00:22:08.768276 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =56
4777 00:22:08.768374
4778 00:22:08.768459
4779 00:22:08.774751 [DQSOSCAuto] RK1, (LSB)MR18= 0x5b21, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
4780 00:22:08.777772 CH1 RK1: MR19=808, MR18=5B21
4781 00:22:08.784657 CH1_RK1: MR19=0x808, MR18=0x5B21, DQSOSC=392, MR23=63, INC=170, DEC=113
4782 00:22:08.787673 [RxdqsGatingPostProcess] freq 600
4783 00:22:08.791115 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4784 00:22:08.794450 Pre-setting of DQS Precalculation
4785 00:22:08.801280 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4786 00:22:08.807706 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4787 00:22:08.814254 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4788 00:22:08.814331
4789 00:22:08.814390
4790 00:22:08.817782 [Calibration Summary] 1200 Mbps
4791 00:22:08.817862 CH 0, Rank 0
4792 00:22:08.821201 SW Impedance : PASS
4793 00:22:08.824342 DUTY Scan : NO K
4794 00:22:08.824445 ZQ Calibration : PASS
4795 00:22:08.827810 Jitter Meter : NO K
4796 00:22:08.831098 CBT Training : PASS
4797 00:22:08.831174 Write leveling : PASS
4798 00:22:08.834331 RX DQS gating : PASS
4799 00:22:08.837606 RX DQ/DQS(RDDQC) : PASS
4800 00:22:08.837682 TX DQ/DQS : PASS
4801 00:22:08.840991 RX DATLAT : PASS
4802 00:22:08.844076 RX DQ/DQS(Engine): PASS
4803 00:22:08.844152 TX OE : NO K
4804 00:22:08.844212 All Pass.
4805 00:22:08.847848
4806 00:22:08.847924 CH 0, Rank 1
4807 00:22:08.850772 SW Impedance : PASS
4808 00:22:08.850848 DUTY Scan : NO K
4809 00:22:08.854297 ZQ Calibration : PASS
4810 00:22:08.854373 Jitter Meter : NO K
4811 00:22:08.857727 CBT Training : PASS
4812 00:22:08.861149 Write leveling : PASS
4813 00:22:08.861225 RX DQS gating : PASS
4814 00:22:08.864191 RX DQ/DQS(RDDQC) : PASS
4815 00:22:08.867736 TX DQ/DQS : PASS
4816 00:22:08.867813 RX DATLAT : PASS
4817 00:22:08.871144 RX DQ/DQS(Engine): PASS
4818 00:22:08.874146 TX OE : NO K
4819 00:22:08.874223 All Pass.
4820 00:22:08.874282
4821 00:22:08.874335 CH 1, Rank 0
4822 00:22:08.877533 SW Impedance : PASS
4823 00:22:08.880990 DUTY Scan : NO K
4824 00:22:08.881066 ZQ Calibration : PASS
4825 00:22:08.884618 Jitter Meter : NO K
4826 00:22:08.887945 CBT Training : PASS
4827 00:22:08.888044 Write leveling : PASS
4828 00:22:08.891337 RX DQS gating : PASS
4829 00:22:08.891412 RX DQ/DQS(RDDQC) : PASS
4830 00:22:08.894178 TX DQ/DQS : PASS
4831 00:22:08.897714 RX DATLAT : PASS
4832 00:22:08.897790 RX DQ/DQS(Engine): PASS
4833 00:22:08.901248 TX OE : NO K
4834 00:22:08.901324 All Pass.
4835 00:22:08.901383
4836 00:22:08.904176 CH 1, Rank 1
4837 00:22:08.904251 SW Impedance : PASS
4838 00:22:08.907514 DUTY Scan : NO K
4839 00:22:08.910870 ZQ Calibration : PASS
4840 00:22:08.910946 Jitter Meter : NO K
4841 00:22:08.914385 CBT Training : PASS
4842 00:22:08.917823 Write leveling : PASS
4843 00:22:08.917926 RX DQS gating : PASS
4844 00:22:08.921221 RX DQ/DQS(RDDQC) : PASS
4845 00:22:08.924487 TX DQ/DQS : PASS
4846 00:22:08.924590 RX DATLAT : PASS
4847 00:22:08.927893 RX DQ/DQS(Engine): PASS
4848 00:22:08.931241 TX OE : NO K
4849 00:22:08.931317 All Pass.
4850 00:22:08.931374
4851 00:22:08.931427 DramC Write-DBI off
4852 00:22:08.934221 PER_BANK_REFRESH: Hybrid Mode
4853 00:22:08.937845 TX_TRACKING: ON
4854 00:22:08.944446 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4855 00:22:08.947805 [FAST_K] Save calibration result to emmc
4856 00:22:08.954289 dramc_set_vcore_voltage set vcore to 662500
4857 00:22:08.954365 Read voltage for 933, 3
4858 00:22:08.957547 Vio18 = 0
4859 00:22:08.957623 Vcore = 662500
4860 00:22:08.957682 Vdram = 0
4861 00:22:08.957735 Vddq = 0
4862 00:22:08.960961 Vmddr = 0
4863 00:22:08.963987 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4864 00:22:08.970880 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4865 00:22:08.974218 MEM_TYPE=3, freq_sel=17
4866 00:22:08.974294 sv_algorithm_assistance_LP4_1600
4867 00:22:08.980925 ============ PULL DRAM RESETB DOWN ============
4868 00:22:08.984331 ========== PULL DRAM RESETB DOWN end =========
4869 00:22:08.987777 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4870 00:22:08.990837 ===================================
4871 00:22:08.994292 LPDDR4 DRAM CONFIGURATION
4872 00:22:08.997711 ===================================
4873 00:22:09.000679 EX_ROW_EN[0] = 0x0
4874 00:22:09.000790 EX_ROW_EN[1] = 0x0
4875 00:22:09.004211 LP4Y_EN = 0x0
4876 00:22:09.004287 WORK_FSP = 0x0
4877 00:22:09.007680 WL = 0x3
4878 00:22:09.007757 RL = 0x3
4879 00:22:09.010604 BL = 0x2
4880 00:22:09.010679 RPST = 0x0
4881 00:22:09.013955 RD_PRE = 0x0
4882 00:22:09.014031 WR_PRE = 0x1
4883 00:22:09.017396 WR_PST = 0x0
4884 00:22:09.017471 DBI_WR = 0x0
4885 00:22:09.020940 DBI_RD = 0x0
4886 00:22:09.021015 OTF = 0x1
4887 00:22:09.024385 ===================================
4888 00:22:09.027352 ===================================
4889 00:22:09.030947 ANA top config
4890 00:22:09.034322 ===================================
4891 00:22:09.037490 DLL_ASYNC_EN = 0
4892 00:22:09.037593 ALL_SLAVE_EN = 1
4893 00:22:09.040579 NEW_RANK_MODE = 1
4894 00:22:09.044246 DLL_IDLE_MODE = 1
4895 00:22:09.047584 LP45_APHY_COMB_EN = 1
4896 00:22:09.047659 TX_ODT_DIS = 1
4897 00:22:09.050701 NEW_8X_MODE = 1
4898 00:22:09.054223 ===================================
4899 00:22:09.057185 ===================================
4900 00:22:09.060563 data_rate = 1866
4901 00:22:09.064067 CKR = 1
4902 00:22:09.067219 DQ_P2S_RATIO = 8
4903 00:22:09.070582 ===================================
4904 00:22:09.074304 CA_P2S_RATIO = 8
4905 00:22:09.074379 DQ_CA_OPEN = 0
4906 00:22:09.077563 DQ_SEMI_OPEN = 0
4907 00:22:09.080659 CA_SEMI_OPEN = 0
4908 00:22:09.083918 CA_FULL_RATE = 0
4909 00:22:09.087692 DQ_CKDIV4_EN = 1
4910 00:22:09.087769 CA_CKDIV4_EN = 1
4911 00:22:09.090750 CA_PREDIV_EN = 0
4912 00:22:09.094300 PH8_DLY = 0
4913 00:22:09.097612 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4914 00:22:09.100567 DQ_AAMCK_DIV = 4
4915 00:22:09.103991 CA_AAMCK_DIV = 4
4916 00:22:09.104066 CA_ADMCK_DIV = 4
4917 00:22:09.107417 DQ_TRACK_CA_EN = 0
4918 00:22:09.110788 CA_PICK = 933
4919 00:22:09.114224 CA_MCKIO = 933
4920 00:22:09.117573 MCKIO_SEMI = 0
4921 00:22:09.120995 PLL_FREQ = 3732
4922 00:22:09.123879 DQ_UI_PI_RATIO = 32
4923 00:22:09.123955 CA_UI_PI_RATIO = 0
4924 00:22:09.127393 ===================================
4925 00:22:09.130779 ===================================
4926 00:22:09.134234 memory_type:LPDDR4
4927 00:22:09.137352 GP_NUM : 10
4928 00:22:09.137428 SRAM_EN : 1
4929 00:22:09.140666 MD32_EN : 0
4930 00:22:09.144193 ===================================
4931 00:22:09.147052 [ANA_INIT] >>>>>>>>>>>>>>
4932 00:22:09.150601 <<<<<< [CONFIGURE PHASE]: ANA_TX
4933 00:22:09.154010 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4934 00:22:09.157253 ===================================
4935 00:22:09.157328 data_rate = 1866,PCW = 0X8f00
4936 00:22:09.160364 ===================================
4937 00:22:09.163958 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4938 00:22:09.170867 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4939 00:22:09.177356 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4940 00:22:09.180385 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4941 00:22:09.183855 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4942 00:22:09.187185 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4943 00:22:09.190365 [ANA_INIT] flow start
4944 00:22:09.193675 [ANA_INIT] PLL >>>>>>>>
4945 00:22:09.193750 [ANA_INIT] PLL <<<<<<<<
4946 00:22:09.197312 [ANA_INIT] MIDPI >>>>>>>>
4947 00:22:09.200335 [ANA_INIT] MIDPI <<<<<<<<
4948 00:22:09.200410 [ANA_INIT] DLL >>>>>>>>
4949 00:22:09.203816 [ANA_INIT] flow end
4950 00:22:09.207374 ============ LP4 DIFF to SE enter ============
4951 00:22:09.210722 ============ LP4 DIFF to SE exit ============
4952 00:22:09.214128 [ANA_INIT] <<<<<<<<<<<<<
4953 00:22:09.217525 [Flow] Enable top DCM control >>>>>
4954 00:22:09.220668 [Flow] Enable top DCM control <<<<<
4955 00:22:09.224257 Enable DLL master slave shuffle
4956 00:22:09.230851 ==============================================================
4957 00:22:09.230929 Gating Mode config
4958 00:22:09.237299 ==============================================================
4959 00:22:09.237375 Config description:
4960 00:22:09.247170 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4961 00:22:09.253777 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4962 00:22:09.260593 SELPH_MODE 0: By rank 1: By Phase
4963 00:22:09.263642 ==============================================================
4964 00:22:09.267080 GAT_TRACK_EN = 1
4965 00:22:09.270610 RX_GATING_MODE = 2
4966 00:22:09.273952 RX_GATING_TRACK_MODE = 2
4967 00:22:09.277170 SELPH_MODE = 1
4968 00:22:09.280609 PICG_EARLY_EN = 1
4969 00:22:09.283777 VALID_LAT_VALUE = 1
4970 00:22:09.287177 ==============================================================
4971 00:22:09.290549 Enter into Gating configuration >>>>
4972 00:22:09.293981 Exit from Gating configuration <<<<
4973 00:22:09.297325 Enter into DVFS_PRE_config >>>>>
4974 00:22:09.310348 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4975 00:22:09.313749 Exit from DVFS_PRE_config <<<<<
4976 00:22:09.316759 Enter into PICG configuration >>>>
4977 00:22:09.316849 Exit from PICG configuration <<<<
4978 00:22:09.320247 [RX_INPUT] configuration >>>>>
4979 00:22:09.323709 [RX_INPUT] configuration <<<<<
4980 00:22:09.330130 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4981 00:22:09.333671 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4982 00:22:09.340176 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4983 00:22:09.346654 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4984 00:22:09.353873 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4985 00:22:09.360221 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4986 00:22:09.363682 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4987 00:22:09.366760 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4988 00:22:09.370015 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4989 00:22:09.376695 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4990 00:22:09.380415 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4991 00:22:09.383500 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4992 00:22:09.387057 ===================================
4993 00:22:09.390318 LPDDR4 DRAM CONFIGURATION
4994 00:22:09.393607 ===================================
4995 00:22:09.396886 EX_ROW_EN[0] = 0x0
4996 00:22:09.396970 EX_ROW_EN[1] = 0x0
4997 00:22:09.400399 LP4Y_EN = 0x0
4998 00:22:09.400475 WORK_FSP = 0x0
4999 00:22:09.403851 WL = 0x3
5000 00:22:09.403927 RL = 0x3
5001 00:22:09.406683 BL = 0x2
5002 00:22:09.406760 RPST = 0x0
5003 00:22:09.410306 RD_PRE = 0x0
5004 00:22:09.410383 WR_PRE = 0x1
5005 00:22:09.413577 WR_PST = 0x0
5006 00:22:09.413654 DBI_WR = 0x0
5007 00:22:09.416842 DBI_RD = 0x0
5008 00:22:09.416918 OTF = 0x1
5009 00:22:09.420254 ===================================
5010 00:22:09.423344 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5011 00:22:09.430113 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5012 00:22:09.433436 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5013 00:22:09.436846 ===================================
5014 00:22:09.440321 LPDDR4 DRAM CONFIGURATION
5015 00:22:09.443261 ===================================
5016 00:22:09.443336 EX_ROW_EN[0] = 0x10
5017 00:22:09.446795 EX_ROW_EN[1] = 0x0
5018 00:22:09.450226 LP4Y_EN = 0x0
5019 00:22:09.450302 WORK_FSP = 0x0
5020 00:22:09.453678 WL = 0x3
5021 00:22:09.453754 RL = 0x3
5022 00:22:09.456674 BL = 0x2
5023 00:22:09.456754 RPST = 0x0
5024 00:22:09.460221 RD_PRE = 0x0
5025 00:22:09.460296 WR_PRE = 0x1
5026 00:22:09.463609 WR_PST = 0x0
5027 00:22:09.463685 DBI_WR = 0x0
5028 00:22:09.466575 DBI_RD = 0x0
5029 00:22:09.466650 OTF = 0x1
5030 00:22:09.470145 ===================================
5031 00:22:09.476505 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5032 00:22:09.480842 nWR fixed to 30
5033 00:22:09.484336 [ModeRegInit_LP4] CH0 RK0
5034 00:22:09.484412 [ModeRegInit_LP4] CH0 RK1
5035 00:22:09.487281 [ModeRegInit_LP4] CH1 RK0
5036 00:22:09.490666 [ModeRegInit_LP4] CH1 RK1
5037 00:22:09.490742 match AC timing 9
5038 00:22:09.497646 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5039 00:22:09.500640 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5040 00:22:09.504392 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5041 00:22:09.510911 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5042 00:22:09.514006 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5043 00:22:09.514082 ==
5044 00:22:09.517271 Dram Type= 6, Freq= 0, CH_0, rank 0
5045 00:22:09.520750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5046 00:22:09.520827 ==
5047 00:22:09.527424 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5048 00:22:09.534216 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5049 00:22:09.537380 [CA 0] Center 38 (7~69) winsize 63
5050 00:22:09.540862 [CA 1] Center 38 (8~69) winsize 62
5051 00:22:09.544342 [CA 2] Center 35 (5~65) winsize 61
5052 00:22:09.547232 [CA 3] Center 35 (5~65) winsize 61
5053 00:22:09.550777 [CA 4] Center 34 (4~64) winsize 61
5054 00:22:09.554259 [CA 5] Center 33 (3~64) winsize 62
5055 00:22:09.554336
5056 00:22:09.557296 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5057 00:22:09.557372
5058 00:22:09.560800 [CATrainingPosCal] consider 1 rank data
5059 00:22:09.563787 u2DelayCellTimex100 = 270/100 ps
5060 00:22:09.567195 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5061 00:22:09.570741 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5062 00:22:09.574271 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5063 00:22:09.577215 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5064 00:22:09.580654 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5065 00:22:09.584051 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5066 00:22:09.584127
5067 00:22:09.590973 CA PerBit enable=1, Macro0, CA PI delay=33
5068 00:22:09.591050
5069 00:22:09.593962 [CBTSetCACLKResult] CA Dly = 33
5070 00:22:09.594038 CS Dly: 6 (0~37)
5071 00:22:09.594097 ==
5072 00:22:09.597232 Dram Type= 6, Freq= 0, CH_0, rank 1
5073 00:22:09.600981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5074 00:22:09.601058 ==
5075 00:22:09.607169 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5076 00:22:09.614139 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5077 00:22:09.617519 [CA 0] Center 38 (7~69) winsize 63
5078 00:22:09.620735 [CA 1] Center 38 (8~69) winsize 62
5079 00:22:09.624083 [CA 2] Center 36 (6~66) winsize 61
5080 00:22:09.627415 [CA 3] Center 35 (5~66) winsize 62
5081 00:22:09.631115 [CA 4] Center 34 (4~65) winsize 62
5082 00:22:09.634082 [CA 5] Center 34 (4~64) winsize 61
5083 00:22:09.634159
5084 00:22:09.637519 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5085 00:22:09.637619
5086 00:22:09.640861 [CATrainingPosCal] consider 2 rank data
5087 00:22:09.644365 u2DelayCellTimex100 = 270/100 ps
5088 00:22:09.647529 CA0 delay=38 (7~69),Diff = 4 PI (24 cell)
5089 00:22:09.650980 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5090 00:22:09.654410 CA2 delay=35 (6~65),Diff = 1 PI (6 cell)
5091 00:22:09.657243 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5092 00:22:09.660628 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5093 00:22:09.664117 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5094 00:22:09.667616
5095 00:22:09.670579 CA PerBit enable=1, Macro0, CA PI delay=34
5096 00:22:09.670655
5097 00:22:09.673559 [CBTSetCACLKResult] CA Dly = 34
5098 00:22:09.673635 CS Dly: 7 (0~39)
5099 00:22:09.673693
5100 00:22:09.677116 ----->DramcWriteLeveling(PI) begin...
5101 00:22:09.677193 ==
5102 00:22:09.680440 Dram Type= 6, Freq= 0, CH_0, rank 0
5103 00:22:09.683464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5104 00:22:09.687212 ==
5105 00:22:09.687288 Write leveling (Byte 0): 31 => 31
5106 00:22:09.690272 Write leveling (Byte 1): 30 => 30
5107 00:22:09.693771 DramcWriteLeveling(PI) end<-----
5108 00:22:09.693847
5109 00:22:09.693905 ==
5110 00:22:09.697230 Dram Type= 6, Freq= 0, CH_0, rank 0
5111 00:22:09.703656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5112 00:22:09.703732 ==
5113 00:22:09.707056 [Gating] SW mode calibration
5114 00:22:09.713621 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5115 00:22:09.717175 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5116 00:22:09.723331 0 14 0 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
5117 00:22:09.726676 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5118 00:22:09.730185 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5119 00:22:09.736612 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5120 00:22:09.740253 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5121 00:22:09.743560 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5122 00:22:09.746745 0 14 24 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
5123 00:22:09.753409 0 14 28 | B1->B0 | 3030 2323 | 1 0 | (1 0) (0 0)
5124 00:22:09.756665 0 15 0 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
5125 00:22:09.760098 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5126 00:22:09.766697 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5127 00:22:09.770001 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5128 00:22:09.773373 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5129 00:22:09.779811 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5130 00:22:09.783308 0 15 24 | B1->B0 | 2323 302f | 0 1 | (0 0) (0 0)
5131 00:22:09.786712 0 15 28 | B1->B0 | 2e2e 4545 | 0 0 | (0 0) (0 0)
5132 00:22:09.793436 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5133 00:22:09.796933 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5134 00:22:09.799843 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5135 00:22:09.806739 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5136 00:22:09.809911 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5137 00:22:09.813143 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5138 00:22:09.819760 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5139 00:22:09.823125 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5140 00:22:09.826468 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5141 00:22:09.833256 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 00:22:09.836569 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 00:22:09.840248 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 00:22:09.843790 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 00:22:09.850450 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 00:22:09.853479 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 00:22:09.856629 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 00:22:09.863644 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 00:22:09.866993 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5150 00:22:09.870338 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 00:22:09.876658 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 00:22:09.880176 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 00:22:09.883741 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 00:22:09.890145 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5155 00:22:09.893546 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5156 00:22:09.897067 Total UI for P1: 0, mck2ui 16
5157 00:22:09.900416 best dqsien dly found for B0: ( 1, 2, 24)
5158 00:22:09.903327 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5159 00:22:09.906909 Total UI for P1: 0, mck2ui 16
5160 00:22:09.910294 best dqsien dly found for B1: ( 1, 2, 28)
5161 00:22:09.913361 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5162 00:22:09.916795 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5163 00:22:09.916872
5164 00:22:09.920188 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5165 00:22:09.926929 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5166 00:22:09.927005 [Gating] SW calibration Done
5167 00:22:09.927064 ==
5168 00:22:09.930301 Dram Type= 6, Freq= 0, CH_0, rank 0
5169 00:22:09.936821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5170 00:22:09.936897 ==
5171 00:22:09.936956 RX Vref Scan: 0
5172 00:22:09.937010
5173 00:22:09.940311 RX Vref 0 -> 0, step: 1
5174 00:22:09.940387
5175 00:22:09.943765 RX Delay -80 -> 252, step: 8
5176 00:22:09.946969 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5177 00:22:09.950258 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5178 00:22:09.953754 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5179 00:22:09.960154 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5180 00:22:09.963462 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5181 00:22:09.966443 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5182 00:22:09.970198 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5183 00:22:09.973405 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5184 00:22:09.976697 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5185 00:22:09.983099 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5186 00:22:09.986685 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5187 00:22:09.990097 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5188 00:22:09.993159 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5189 00:22:09.996539 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5190 00:22:09.999980 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5191 00:22:10.006649 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5192 00:22:10.006767 ==
5193 00:22:10.009501 Dram Type= 6, Freq= 0, CH_0, rank 0
5194 00:22:10.012858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5195 00:22:10.012936 ==
5196 00:22:10.012995 DQS Delay:
5197 00:22:10.016328 DQS0 = 0, DQS1 = 0
5198 00:22:10.016404 DQM Delay:
5199 00:22:10.019807 DQM0 = 105, DQM1 = 90
5200 00:22:10.019883 DQ Delay:
5201 00:22:10.023222 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5202 00:22:10.026130 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115
5203 00:22:10.029676 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5204 00:22:10.032980 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =99
5205 00:22:10.033056
5206 00:22:10.033114
5207 00:22:10.033168 ==
5208 00:22:10.036176 Dram Type= 6, Freq= 0, CH_0, rank 0
5209 00:22:10.039732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5210 00:22:10.042816 ==
5211 00:22:10.042892
5212 00:22:10.042950
5213 00:22:10.043005 TX Vref Scan disable
5214 00:22:10.046296 == TX Byte 0 ==
5215 00:22:10.049721 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5216 00:22:10.052902 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5217 00:22:10.056297 == TX Byte 1 ==
5218 00:22:10.059635 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5219 00:22:10.063176 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5220 00:22:10.066240 ==
5221 00:22:10.066316 Dram Type= 6, Freq= 0, CH_0, rank 0
5222 00:22:10.073113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5223 00:22:10.073189 ==
5224 00:22:10.073248
5225 00:22:10.073302
5226 00:22:10.073352 TX Vref Scan disable
5227 00:22:10.077657 == TX Byte 0 ==
5228 00:22:10.080728 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5229 00:22:10.084064 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5230 00:22:10.087618 == TX Byte 1 ==
5231 00:22:10.090855 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5232 00:22:10.094308 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5233 00:22:10.097116
5234 00:22:10.097192 [DATLAT]
5235 00:22:10.097250 Freq=933, CH0 RK0
5236 00:22:10.097304
5237 00:22:10.100521 DATLAT Default: 0xd
5238 00:22:10.100620 0, 0xFFFF, sum = 0
5239 00:22:10.104047 1, 0xFFFF, sum = 0
5240 00:22:10.104124 2, 0xFFFF, sum = 0
5241 00:22:10.107601 3, 0xFFFF, sum = 0
5242 00:22:10.107679 4, 0xFFFF, sum = 0
5243 00:22:10.110503 5, 0xFFFF, sum = 0
5244 00:22:10.110580 6, 0xFFFF, sum = 0
5245 00:22:10.114156 7, 0xFFFF, sum = 0
5246 00:22:10.117559 8, 0xFFFF, sum = 0
5247 00:22:10.117636 9, 0xFFFF, sum = 0
5248 00:22:10.120437 10, 0x0, sum = 1
5249 00:22:10.120538 11, 0x0, sum = 2
5250 00:22:10.120642 12, 0x0, sum = 3
5251 00:22:10.123904 13, 0x0, sum = 4
5252 00:22:10.123981 best_step = 11
5253 00:22:10.124040
5254 00:22:10.124093 ==
5255 00:22:10.127420 Dram Type= 6, Freq= 0, CH_0, rank 0
5256 00:22:10.133864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5257 00:22:10.133940 ==
5258 00:22:10.133998 RX Vref Scan: 1
5259 00:22:10.134053
5260 00:22:10.137276 RX Vref 0 -> 0, step: 1
5261 00:22:10.137351
5262 00:22:10.140528 RX Delay -53 -> 252, step: 4
5263 00:22:10.140603
5264 00:22:10.144030 Set Vref, RX VrefLevel [Byte0]: 59
5265 00:22:10.147374 [Byte1]: 50
5266 00:22:10.147450
5267 00:22:10.150785 Final RX Vref Byte 0 = 59 to rank0
5268 00:22:10.154179 Final RX Vref Byte 1 = 50 to rank0
5269 00:22:10.157338 Final RX Vref Byte 0 = 59 to rank1
5270 00:22:10.160850 Final RX Vref Byte 1 = 50 to rank1==
5271 00:22:10.164032 Dram Type= 6, Freq= 0, CH_0, rank 0
5272 00:22:10.167727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5273 00:22:10.167804 ==
5274 00:22:10.170572 DQS Delay:
5275 00:22:10.170647 DQS0 = 0, DQS1 = 0
5276 00:22:10.170704 DQM Delay:
5277 00:22:10.173916 DQM0 = 106, DQM1 = 92
5278 00:22:10.173991 DQ Delay:
5279 00:22:10.177611 DQ0 =106, DQ1 =108, DQ2 =102, DQ3 =106
5280 00:22:10.180886 DQ4 =106, DQ5 =98, DQ6 =116, DQ7 =112
5281 00:22:10.184148 DQ8 =86, DQ9 =78, DQ10 =94, DQ11 =92
5282 00:22:10.187450 DQ12 =96, DQ13 =92, DQ14 =100, DQ15 =98
5283 00:22:10.187526
5284 00:22:10.191015
5285 00:22:10.197338 [DQSOSCAuto] RK0, (LSB)MR18= 0x2622, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 409 ps
5286 00:22:10.200937 CH0 RK0: MR19=505, MR18=2622
5287 00:22:10.207509 CH0_RK0: MR19=0x505, MR18=0x2622, DQSOSC=409, MR23=63, INC=64, DEC=43
5288 00:22:10.207613
5289 00:22:10.210649 ----->DramcWriteLeveling(PI) begin...
5290 00:22:10.210751 ==
5291 00:22:10.214068 Dram Type= 6, Freq= 0, CH_0, rank 1
5292 00:22:10.217669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5293 00:22:10.217764 ==
5294 00:22:10.220852 Write leveling (Byte 0): 33 => 33
5295 00:22:10.224303 Write leveling (Byte 1): 31 => 31
5296 00:22:10.227360 DramcWriteLeveling(PI) end<-----
5297 00:22:10.227469
5298 00:22:10.227554 ==
5299 00:22:10.230742 Dram Type= 6, Freq= 0, CH_0, rank 1
5300 00:22:10.234181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5301 00:22:10.234277 ==
5302 00:22:10.237198 [Gating] SW mode calibration
5303 00:22:10.244107 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5304 00:22:10.250778 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5305 00:22:10.254106 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5306 00:22:10.257236 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5307 00:22:10.263864 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5308 00:22:10.267298 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5309 00:22:10.270541 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5310 00:22:10.276998 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5311 00:22:10.280514 0 14 24 | B1->B0 | 3434 3030 | 0 0 | (0 0) (0 0)
5312 00:22:10.283741 0 14 28 | B1->B0 | 2a2a 2424 | 1 0 | (1 0) (0 0)
5313 00:22:10.290523 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5314 00:22:10.293994 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5315 00:22:10.297288 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5316 00:22:10.303908 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5317 00:22:10.307171 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5318 00:22:10.310427 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5319 00:22:10.317411 0 15 24 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (1 1)
5320 00:22:10.320571 0 15 28 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
5321 00:22:10.323950 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5322 00:22:10.330292 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5323 00:22:10.333789 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5324 00:22:10.336854 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5325 00:22:10.340312 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5326 00:22:10.347214 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5327 00:22:10.350401 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5328 00:22:10.353462 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5329 00:22:10.360175 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 00:22:10.363935 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 00:22:10.366871 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 00:22:10.373750 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 00:22:10.377072 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 00:22:10.380196 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 00:22:10.386739 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 00:22:10.390396 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 00:22:10.393502 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5338 00:22:10.400381 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5339 00:22:10.403619 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5340 00:22:10.406827 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5341 00:22:10.413354 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5342 00:22:10.416898 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 00:22:10.419757 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 00:22:10.426620 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5345 00:22:10.429708 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5346 00:22:10.433142 Total UI for P1: 0, mck2ui 16
5347 00:22:10.436697 best dqsien dly found for B0: ( 1, 2, 28)
5348 00:22:10.439673 Total UI for P1: 0, mck2ui 16
5349 00:22:10.443208 best dqsien dly found for B1: ( 1, 2, 28)
5350 00:22:10.446541 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5351 00:22:10.449572 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5352 00:22:10.449753
5353 00:22:10.453315 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5354 00:22:10.456191 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5355 00:22:10.459762 [Gating] SW calibration Done
5356 00:22:10.459839 ==
5357 00:22:10.463184 Dram Type= 6, Freq= 0, CH_0, rank 1
5358 00:22:10.466162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5359 00:22:10.469529 ==
5360 00:22:10.469622 RX Vref Scan: 0
5361 00:22:10.469694
5362 00:22:10.473048 RX Vref 0 -> 0, step: 1
5363 00:22:10.473124
5364 00:22:10.476165 RX Delay -80 -> 252, step: 8
5365 00:22:10.479525 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5366 00:22:10.482873 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5367 00:22:10.486361 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5368 00:22:10.489385 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5369 00:22:10.493060 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5370 00:22:10.499399 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5371 00:22:10.502857 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5372 00:22:10.506143 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5373 00:22:10.509178 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5374 00:22:10.512851 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5375 00:22:10.519388 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5376 00:22:10.522478 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5377 00:22:10.526140 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5378 00:22:10.529077 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5379 00:22:10.532303 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5380 00:22:10.535640 iDelay=208, Bit 15, Center 95 (8 ~ 183) 176
5381 00:22:10.539201 ==
5382 00:22:10.539279 Dram Type= 6, Freq= 0, CH_0, rank 1
5383 00:22:10.545602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5384 00:22:10.545681 ==
5385 00:22:10.545741 DQS Delay:
5386 00:22:10.548984 DQS0 = 0, DQS1 = 0
5387 00:22:10.549061 DQM Delay:
5388 00:22:10.552300 DQM0 = 104, DQM1 = 90
5389 00:22:10.552379 DQ Delay:
5390 00:22:10.555615 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5391 00:22:10.558917 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =111
5392 00:22:10.562375 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5393 00:22:10.565735 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =95
5394 00:22:10.565815
5395 00:22:10.565874
5396 00:22:10.565929 ==
5397 00:22:10.569238 Dram Type= 6, Freq= 0, CH_0, rank 1
5398 00:22:10.572371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5399 00:22:10.572449 ==
5400 00:22:10.572509
5401 00:22:10.572564
5402 00:22:10.575766 TX Vref Scan disable
5403 00:22:10.579226 == TX Byte 0 ==
5404 00:22:10.582231 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5405 00:22:10.585577 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5406 00:22:10.588913 == TX Byte 1 ==
5407 00:22:10.592433 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5408 00:22:10.595329 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5409 00:22:10.595406 ==
5410 00:22:10.598610 Dram Type= 6, Freq= 0, CH_0, rank 1
5411 00:22:10.605301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5412 00:22:10.605379 ==
5413 00:22:10.605438
5414 00:22:10.605491
5415 00:22:10.605542 TX Vref Scan disable
5416 00:22:10.609677 == TX Byte 0 ==
5417 00:22:10.612602 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5418 00:22:10.619302 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5419 00:22:10.619379 == TX Byte 1 ==
5420 00:22:10.622581 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5421 00:22:10.629766 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5422 00:22:10.629846
5423 00:22:10.629925 [DATLAT]
5424 00:22:10.629997 Freq=933, CH0 RK1
5425 00:22:10.630067
5426 00:22:10.632680 DATLAT Default: 0xb
5427 00:22:10.632823 0, 0xFFFF, sum = 0
5428 00:22:10.636201 1, 0xFFFF, sum = 0
5429 00:22:10.636298 2, 0xFFFF, sum = 0
5430 00:22:10.639647 3, 0xFFFF, sum = 0
5431 00:22:10.642531 4, 0xFFFF, sum = 0
5432 00:22:10.642607 5, 0xFFFF, sum = 0
5433 00:22:10.645762 6, 0xFFFF, sum = 0
5434 00:22:10.645831 7, 0xFFFF, sum = 0
5435 00:22:10.649356 8, 0xFFFF, sum = 0
5436 00:22:10.649432 9, 0xFFFF, sum = 0
5437 00:22:10.652720 10, 0x0, sum = 1
5438 00:22:10.652797 11, 0x0, sum = 2
5439 00:22:10.655767 12, 0x0, sum = 3
5440 00:22:10.655844 13, 0x0, sum = 4
5441 00:22:10.655904 best_step = 11
5442 00:22:10.655958
5443 00:22:10.659242 ==
5444 00:22:10.662505 Dram Type= 6, Freq= 0, CH_0, rank 1
5445 00:22:10.666163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5446 00:22:10.666240 ==
5447 00:22:10.666298 RX Vref Scan: 0
5448 00:22:10.666352
5449 00:22:10.669136 RX Vref 0 -> 0, step: 1
5450 00:22:10.669211
5451 00:22:10.672697 RX Delay -53 -> 252, step: 4
5452 00:22:10.676125 iDelay=199, Bit 0, Center 104 (19 ~ 190) 172
5453 00:22:10.682822 iDelay=199, Bit 1, Center 104 (15 ~ 194) 180
5454 00:22:10.685855 iDelay=199, Bit 2, Center 100 (15 ~ 186) 172
5455 00:22:10.689425 iDelay=199, Bit 3, Center 98 (15 ~ 182) 168
5456 00:22:10.692638 iDelay=199, Bit 4, Center 102 (15 ~ 190) 176
5457 00:22:10.695848 iDelay=199, Bit 5, Center 96 (11 ~ 182) 172
5458 00:22:10.702382 iDelay=199, Bit 6, Center 110 (23 ~ 198) 176
5459 00:22:10.705812 iDelay=199, Bit 7, Center 110 (23 ~ 198) 176
5460 00:22:10.709124 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5461 00:22:10.712616 iDelay=199, Bit 9, Center 80 (-1 ~ 162) 164
5462 00:22:10.716052 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5463 00:22:10.719031 iDelay=199, Bit 11, Center 92 (11 ~ 174) 164
5464 00:22:10.726032 iDelay=199, Bit 12, Center 96 (11 ~ 182) 172
5465 00:22:10.728974 iDelay=199, Bit 13, Center 96 (15 ~ 178) 164
5466 00:22:10.732561 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5467 00:22:10.735589 iDelay=199, Bit 15, Center 98 (15 ~ 182) 168
5468 00:22:10.735665 ==
5469 00:22:10.739171 Dram Type= 6, Freq= 0, CH_0, rank 1
5470 00:22:10.742432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5471 00:22:10.745867 ==
5472 00:22:10.745942 DQS Delay:
5473 00:22:10.746002 DQS0 = 0, DQS1 = 0
5474 00:22:10.748958 DQM Delay:
5475 00:22:10.749034 DQM0 = 103, DQM1 = 92
5476 00:22:10.752453 DQ Delay:
5477 00:22:10.756118 DQ0 =104, DQ1 =104, DQ2 =100, DQ3 =98
5478 00:22:10.759050 DQ4 =102, DQ5 =96, DQ6 =110, DQ7 =110
5479 00:22:10.762633 DQ8 =86, DQ9 =80, DQ10 =94, DQ11 =92
5480 00:22:10.765750 DQ12 =96, DQ13 =96, DQ14 =100, DQ15 =98
5481 00:22:10.765826
5482 00:22:10.765884
5483 00:22:10.772593 [DQSOSCAuto] RK1, (LSB)MR18= 0x2d0d, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 407 ps
5484 00:22:10.775994 CH0 RK1: MR19=505, MR18=2D0D
5485 00:22:10.782590 CH0_RK1: MR19=0x505, MR18=0x2D0D, DQSOSC=407, MR23=63, INC=65, DEC=43
5486 00:22:10.786033 [RxdqsGatingPostProcess] freq 933
5487 00:22:10.789018 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5488 00:22:10.792338 best DQS0 dly(2T, 0.5T) = (0, 10)
5489 00:22:10.795674 best DQS1 dly(2T, 0.5T) = (0, 10)
5490 00:22:10.799250 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5491 00:22:10.802307 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5492 00:22:10.806071 best DQS0 dly(2T, 0.5T) = (0, 10)
5493 00:22:10.809122 best DQS1 dly(2T, 0.5T) = (0, 10)
5494 00:22:10.812689 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5495 00:22:10.815742 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5496 00:22:10.819305 Pre-setting of DQS Precalculation
5497 00:22:10.822738 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5498 00:22:10.822814 ==
5499 00:22:10.825752 Dram Type= 6, Freq= 0, CH_1, rank 0
5500 00:22:10.832673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5501 00:22:10.832768 ==
5502 00:22:10.835847 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5503 00:22:10.842759 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
5504 00:22:10.846020 [CA 0] Center 37 (7~68) winsize 62
5505 00:22:10.849144 [CA 1] Center 38 (7~69) winsize 63
5506 00:22:10.852513 [CA 2] Center 35 (5~66) winsize 62
5507 00:22:10.855788 [CA 3] Center 35 (5~65) winsize 61
5508 00:22:10.859235 [CA 4] Center 35 (5~66) winsize 62
5509 00:22:10.862403 [CA 5] Center 34 (4~65) winsize 62
5510 00:22:10.862481
5511 00:22:10.866065 [CmdBusTrainingLP45] Vref(ca) range 1: 31
5512 00:22:10.866142
5513 00:22:10.869468 [CATrainingPosCal] consider 1 rank data
5514 00:22:10.872401 u2DelayCellTimex100 = 270/100 ps
5515 00:22:10.875823 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5516 00:22:10.879190 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5517 00:22:10.882765 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5518 00:22:10.889091 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5519 00:22:10.892578 CA4 delay=35 (5~66),Diff = 1 PI (6 cell)
5520 00:22:10.895558 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
5521 00:22:10.895634
5522 00:22:10.898920 CA PerBit enable=1, Macro0, CA PI delay=34
5523 00:22:10.898996
5524 00:22:10.902324 [CBTSetCACLKResult] CA Dly = 34
5525 00:22:10.902399 CS Dly: 7 (0~38)
5526 00:22:10.902458 ==
5527 00:22:10.905621 Dram Type= 6, Freq= 0, CH_1, rank 1
5528 00:22:10.912550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5529 00:22:10.912629 ==
5530 00:22:10.915834 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5531 00:22:10.922476 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5532 00:22:10.925930 [CA 0] Center 38 (8~69) winsize 62
5533 00:22:10.928958 [CA 1] Center 38 (8~69) winsize 62
5534 00:22:10.932370 [CA 2] Center 36 (6~66) winsize 61
5535 00:22:10.935875 [CA 3] Center 36 (6~66) winsize 61
5536 00:22:10.939285 [CA 4] Center 35 (5~65) winsize 61
5537 00:22:10.942745 [CA 5] Center 35 (5~65) winsize 61
5538 00:22:10.942820
5539 00:22:10.946102 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5540 00:22:10.946177
5541 00:22:10.949254 [CATrainingPosCal] consider 2 rank data
5542 00:22:10.952419 u2DelayCellTimex100 = 270/100 ps
5543 00:22:10.955886 CA0 delay=38 (8~68),Diff = 3 PI (18 cell)
5544 00:22:10.959160 CA1 delay=38 (8~69),Diff = 3 PI (18 cell)
5545 00:22:10.962483 CA2 delay=36 (6~66),Diff = 1 PI (6 cell)
5546 00:22:10.969274 CA3 delay=35 (6~65),Diff = 0 PI (0 cell)
5547 00:22:10.972625 CA4 delay=35 (5~65),Diff = 0 PI (0 cell)
5548 00:22:10.975670 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
5549 00:22:10.975745
5550 00:22:10.979372 CA PerBit enable=1, Macro0, CA PI delay=35
5551 00:22:10.979447
5552 00:22:10.982356 [CBTSetCACLKResult] CA Dly = 35
5553 00:22:10.982431 CS Dly: 7 (0~39)
5554 00:22:10.982490
5555 00:22:10.985918 ----->DramcWriteLeveling(PI) begin...
5556 00:22:10.985993 ==
5557 00:22:10.989254 Dram Type= 6, Freq= 0, CH_1, rank 0
5558 00:22:10.995738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5559 00:22:10.995815 ==
5560 00:22:10.999193 Write leveling (Byte 0): 28 => 28
5561 00:22:11.002680 Write leveling (Byte 1): 31 => 31
5562 00:22:11.002758 DramcWriteLeveling(PI) end<-----
5563 00:22:11.005727
5564 00:22:11.005803 ==
5565 00:22:11.009190 Dram Type= 6, Freq= 0, CH_1, rank 0
5566 00:22:11.012162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5567 00:22:11.012239 ==
5568 00:22:11.015653 [Gating] SW mode calibration
5569 00:22:11.022270 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5570 00:22:11.025742 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5571 00:22:11.032248 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5572 00:22:11.035799 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5573 00:22:11.039206 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5574 00:22:11.045735 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5575 00:22:11.049253 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5576 00:22:11.052395 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5577 00:22:11.059025 0 14 24 | B1->B0 | 3030 3333 | 0 0 | (0 0) (0 0)
5578 00:22:11.062516 0 14 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5579 00:22:11.065869 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5580 00:22:11.072044 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5581 00:22:11.075703 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5582 00:22:11.079226 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5583 00:22:11.085428 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5584 00:22:11.088906 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5585 00:22:11.092374 0 15 24 | B1->B0 | 2727 2c2c | 0 1 | (0 0) (1 1)
5586 00:22:11.098810 0 15 28 | B1->B0 | 3f3f 4545 | 0 1 | (0 0) (0 0)
5587 00:22:11.102280 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5588 00:22:11.105709 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5589 00:22:11.108672 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5590 00:22:11.115630 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5591 00:22:11.119108 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5592 00:22:11.122593 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5593 00:22:11.128738 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5594 00:22:11.132404 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5595 00:22:11.135642 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 00:22:11.142185 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 00:22:11.145721 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 00:22:11.149166 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 00:22:11.155437 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 00:22:11.158983 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 00:22:11.162088 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 00:22:11.168624 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 00:22:11.172171 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5604 00:22:11.175780 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5605 00:22:11.182286 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5606 00:22:11.185703 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 00:22:11.189059 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 00:22:11.195787 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 00:22:11.198680 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5610 00:22:11.202094 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5611 00:22:11.205481 Total UI for P1: 0, mck2ui 16
5612 00:22:11.208827 best dqsien dly found for B0: ( 1, 2, 24)
5613 00:22:11.212018 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5614 00:22:11.215424 Total UI for P1: 0, mck2ui 16
5615 00:22:11.218837 best dqsien dly found for B1: ( 1, 2, 26)
5616 00:22:11.222340 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5617 00:22:11.228917 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5618 00:22:11.228993
5619 00:22:11.231979 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5620 00:22:11.235297 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5621 00:22:11.238655 [Gating] SW calibration Done
5622 00:22:11.238732 ==
5623 00:22:11.242081 Dram Type= 6, Freq= 0, CH_1, rank 0
5624 00:22:11.245429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5625 00:22:11.245506 ==
5626 00:22:11.245565 RX Vref Scan: 0
5627 00:22:11.248854
5628 00:22:11.248929 RX Vref 0 -> 0, step: 1
5629 00:22:11.248988
5630 00:22:11.251773 RX Delay -80 -> 252, step: 8
5631 00:22:11.255780 iDelay=208, Bit 0, Center 103 (16 ~ 191) 176
5632 00:22:11.258755 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5633 00:22:11.265709 iDelay=208, Bit 2, Center 95 (8 ~ 183) 176
5634 00:22:11.268595 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5635 00:22:11.272094 iDelay=208, Bit 4, Center 103 (16 ~ 191) 176
5636 00:22:11.275383 iDelay=208, Bit 5, Center 115 (32 ~ 199) 168
5637 00:22:11.278623 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5638 00:22:11.282245 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5639 00:22:11.288676 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5640 00:22:11.291832 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5641 00:22:11.294990 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5642 00:22:11.298523 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5643 00:22:11.301925 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5644 00:22:11.308728 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5645 00:22:11.311702 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5646 00:22:11.315265 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5647 00:22:11.315341 ==
5648 00:22:11.318750 Dram Type= 6, Freq= 0, CH_1, rank 0
5649 00:22:11.321878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5650 00:22:11.321955 ==
5651 00:22:11.325215 DQS Delay:
5652 00:22:11.325291 DQS0 = 0, DQS1 = 0
5653 00:22:11.325349 DQM Delay:
5654 00:22:11.328183 DQM0 = 102, DQM1 = 95
5655 00:22:11.328259 DQ Delay:
5656 00:22:11.331737 DQ0 =103, DQ1 =95, DQ2 =95, DQ3 =99
5657 00:22:11.335192 DQ4 =103, DQ5 =115, DQ6 =111, DQ7 =99
5658 00:22:11.338305 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =91
5659 00:22:11.341682 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5660 00:22:11.341771
5661 00:22:11.341848
5662 00:22:11.344980 ==
5663 00:22:11.348293 Dram Type= 6, Freq= 0, CH_1, rank 0
5664 00:22:11.351892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5665 00:22:11.351969 ==
5666 00:22:11.352029
5667 00:22:11.352083
5668 00:22:11.355400 TX Vref Scan disable
5669 00:22:11.355476 == TX Byte 0 ==
5670 00:22:11.358338 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5671 00:22:11.365312 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5672 00:22:11.365388 == TX Byte 1 ==
5673 00:22:11.368226 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5674 00:22:11.375206 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5675 00:22:11.375283 ==
5676 00:22:11.378629 Dram Type= 6, Freq= 0, CH_1, rank 0
5677 00:22:11.381860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5678 00:22:11.381937 ==
5679 00:22:11.381996
5680 00:22:11.382049
5681 00:22:11.384940 TX Vref Scan disable
5682 00:22:11.388242 == TX Byte 0 ==
5683 00:22:11.391396 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5684 00:22:11.395311 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5685 00:22:11.398237 == TX Byte 1 ==
5686 00:22:11.401970 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5687 00:22:11.404936 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5688 00:22:11.405011
5689 00:22:11.405068 [DATLAT]
5690 00:22:11.408390 Freq=933, CH1 RK0
5691 00:22:11.408466
5692 00:22:11.411658 DATLAT Default: 0xd
5693 00:22:11.411733 0, 0xFFFF, sum = 0
5694 00:22:11.415202 1, 0xFFFF, sum = 0
5695 00:22:11.415278 2, 0xFFFF, sum = 0
5696 00:22:11.418786 3, 0xFFFF, sum = 0
5697 00:22:11.418862 4, 0xFFFF, sum = 0
5698 00:22:11.421734 5, 0xFFFF, sum = 0
5699 00:22:11.421810 6, 0xFFFF, sum = 0
5700 00:22:11.424699 7, 0xFFFF, sum = 0
5701 00:22:11.424829 8, 0xFFFF, sum = 0
5702 00:22:11.428145 9, 0xFFFF, sum = 0
5703 00:22:11.428222 10, 0x0, sum = 1
5704 00:22:11.431680 11, 0x0, sum = 2
5705 00:22:11.431757 12, 0x0, sum = 3
5706 00:22:11.435085 13, 0x0, sum = 4
5707 00:22:11.435161 best_step = 11
5708 00:22:11.435218
5709 00:22:11.435272 ==
5710 00:22:11.438538 Dram Type= 6, Freq= 0, CH_1, rank 0
5711 00:22:11.441757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5712 00:22:11.441856 ==
5713 00:22:11.445160 RX Vref Scan: 1
5714 00:22:11.445244
5715 00:22:11.448214 RX Vref 0 -> 0, step: 1
5716 00:22:11.448305
5717 00:22:11.448391 RX Delay -53 -> 252, step: 4
5718 00:22:11.448488
5719 00:22:11.451551 Set Vref, RX VrefLevel [Byte0]: 50
5720 00:22:11.455003 [Byte1]: 52
5721 00:22:11.459598
5722 00:22:11.459688 Final RX Vref Byte 0 = 50 to rank0
5723 00:22:11.463193 Final RX Vref Byte 1 = 52 to rank0
5724 00:22:11.466394 Final RX Vref Byte 0 = 50 to rank1
5725 00:22:11.469474 Final RX Vref Byte 1 = 52 to rank1==
5726 00:22:11.472661 Dram Type= 6, Freq= 0, CH_1, rank 0
5727 00:22:11.479738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5728 00:22:11.479811 ==
5729 00:22:11.479870 DQS Delay:
5730 00:22:11.479931 DQS0 = 0, DQS1 = 0
5731 00:22:11.482756 DQM Delay:
5732 00:22:11.482827 DQM0 = 104, DQM1 = 96
5733 00:22:11.485870 DQ Delay:
5734 00:22:11.489281 DQ0 =108, DQ1 =98, DQ2 =96, DQ3 =104
5735 00:22:11.492620 DQ4 =104, DQ5 =112, DQ6 =114, DQ7 =102
5736 00:22:11.495944 DQ8 =86, DQ9 =84, DQ10 =100, DQ11 =90
5737 00:22:11.499336 DQ12 =104, DQ13 =100, DQ14 =104, DQ15 =102
5738 00:22:11.499416
5739 00:22:11.499475
5740 00:22:11.506461 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f37, (MSB)MR19= 0x505, tDQSOscB0 = 404 ps tDQSOscB1 = 412 ps
5741 00:22:11.509571 CH1 RK0: MR19=505, MR18=1F37
5742 00:22:11.515986 CH1_RK0: MR19=0x505, MR18=0x1F37, DQSOSC=404, MR23=63, INC=66, DEC=44
5743 00:22:11.516065
5744 00:22:11.519743 ----->DramcWriteLeveling(PI) begin...
5745 00:22:11.519821 ==
5746 00:22:11.522815 Dram Type= 6, Freq= 0, CH_1, rank 1
5747 00:22:11.526224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5748 00:22:11.526302 ==
5749 00:22:11.529694 Write leveling (Byte 0): 25 => 25
5750 00:22:11.532854 Write leveling (Byte 1): 30 => 30
5751 00:22:11.536223 DramcWriteLeveling(PI) end<-----
5752 00:22:11.536299
5753 00:22:11.536357 ==
5754 00:22:11.539620 Dram Type= 6, Freq= 0, CH_1, rank 1
5755 00:22:11.545862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5756 00:22:11.545940 ==
5757 00:22:11.546000 [Gating] SW mode calibration
5758 00:22:11.555975 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5759 00:22:11.559256 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5760 00:22:11.562802 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5761 00:22:11.569493 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5762 00:22:11.572682 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5763 00:22:11.576238 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5764 00:22:11.582829 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5765 00:22:11.586219 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5766 00:22:11.589600 0 14 24 | B1->B0 | 3030 3434 | 0 0 | (0 0) (0 0)
5767 00:22:11.596305 0 14 28 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (1 0)
5768 00:22:11.599454 0 15 0 | B1->B0 | 2323 2929 | 0 1 | (0 0) (1 0)
5769 00:22:11.602868 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5770 00:22:11.609181 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5771 00:22:11.612542 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5772 00:22:11.615895 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5773 00:22:11.622624 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5774 00:22:11.625977 0 15 24 | B1->B0 | 2a2a 2828 | 0 0 | (0 0) (0 0)
5775 00:22:11.628890 0 15 28 | B1->B0 | 4545 3a3a | 0 0 | (0 0) (0 0)
5776 00:22:11.635698 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5777 00:22:11.638998 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5778 00:22:11.642572 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5779 00:22:11.649160 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5780 00:22:11.652160 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5781 00:22:11.655495 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5782 00:22:11.662433 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5783 00:22:11.665799 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5784 00:22:11.668902 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 00:22:11.675477 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 00:22:11.678562 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 00:22:11.682113 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 00:22:11.688576 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 00:22:11.691733 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 00:22:11.695181 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 00:22:11.698757 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5792 00:22:11.705248 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5793 00:22:11.708686 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5794 00:22:11.712392 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5795 00:22:11.718685 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5796 00:22:11.722232 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5797 00:22:11.725319 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 00:22:11.731925 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5799 00:22:11.735329 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5800 00:22:11.738569 Total UI for P1: 0, mck2ui 16
5801 00:22:11.742353 best dqsien dly found for B1: ( 1, 2, 24)
5802 00:22:11.745109 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5803 00:22:11.748831 Total UI for P1: 0, mck2ui 16
5804 00:22:11.752077 best dqsien dly found for B0: ( 1, 2, 26)
5805 00:22:11.755362 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5806 00:22:11.758671 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5807 00:22:11.758747
5808 00:22:11.765576 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5809 00:22:11.768563 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5810 00:22:11.768639 [Gating] SW calibration Done
5811 00:22:11.771958 ==
5812 00:22:11.775475 Dram Type= 6, Freq= 0, CH_1, rank 1
5813 00:22:11.778822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5814 00:22:11.778899 ==
5815 00:22:11.778957 RX Vref Scan: 0
5816 00:22:11.779011
5817 00:22:11.781899 RX Vref 0 -> 0, step: 1
5818 00:22:11.781975
5819 00:22:11.785101 RX Delay -80 -> 252, step: 8
5820 00:22:11.788654 iDelay=200, Bit 0, Center 107 (24 ~ 191) 168
5821 00:22:11.791960 iDelay=200, Bit 1, Center 95 (8 ~ 183) 176
5822 00:22:11.795397 iDelay=200, Bit 2, Center 87 (0 ~ 175) 176
5823 00:22:11.798841 iDelay=200, Bit 3, Center 99 (8 ~ 191) 184
5824 00:22:11.805374 iDelay=200, Bit 4, Center 103 (16 ~ 191) 176
5825 00:22:11.808711 iDelay=200, Bit 5, Center 111 (24 ~ 199) 176
5826 00:22:11.812258 iDelay=200, Bit 6, Center 111 (24 ~ 199) 176
5827 00:22:11.815344 iDelay=200, Bit 7, Center 99 (8 ~ 191) 184
5828 00:22:11.818816 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5829 00:22:11.825390 iDelay=200, Bit 9, Center 87 (0 ~ 175) 176
5830 00:22:11.828810 iDelay=200, Bit 10, Center 95 (0 ~ 191) 192
5831 00:22:11.832071 iDelay=200, Bit 11, Center 91 (0 ~ 183) 184
5832 00:22:11.835048 iDelay=200, Bit 12, Center 103 (8 ~ 199) 192
5833 00:22:11.838594 iDelay=200, Bit 13, Center 103 (8 ~ 199) 192
5834 00:22:11.842229 iDelay=200, Bit 14, Center 103 (8 ~ 199) 192
5835 00:22:11.848627 iDelay=200, Bit 15, Center 103 (8 ~ 199) 192
5836 00:22:11.848763 ==
5837 00:22:11.851975 Dram Type= 6, Freq= 0, CH_1, rank 1
5838 00:22:11.855357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5839 00:22:11.855435 ==
5840 00:22:11.855493 DQS Delay:
5841 00:22:11.858711 DQS0 = 0, DQS1 = 0
5842 00:22:11.858786 DQM Delay:
5843 00:22:11.862089 DQM0 = 101, DQM1 = 96
5844 00:22:11.862164 DQ Delay:
5845 00:22:11.865569 DQ0 =107, DQ1 =95, DQ2 =87, DQ3 =99
5846 00:22:11.868473 DQ4 =103, DQ5 =111, DQ6 =111, DQ7 =99
5847 00:22:11.871804 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =91
5848 00:22:11.875376 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5849 00:22:11.875453
5850 00:22:11.875511
5851 00:22:11.875566 ==
5852 00:22:11.878836 Dram Type= 6, Freq= 0, CH_1, rank 1
5853 00:22:11.885332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5854 00:22:11.885408 ==
5855 00:22:11.885466
5856 00:22:11.885520
5857 00:22:11.885571 TX Vref Scan disable
5858 00:22:11.888283 == TX Byte 0 ==
5859 00:22:11.891883 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5860 00:22:11.898244 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5861 00:22:11.898325 == TX Byte 1 ==
5862 00:22:11.901561 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5863 00:22:11.908563 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5864 00:22:11.908638 ==
5865 00:22:11.911719 Dram Type= 6, Freq= 0, CH_1, rank 1
5866 00:22:11.914940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5867 00:22:11.915016 ==
5868 00:22:11.915074
5869 00:22:11.915127
5870 00:22:11.918397 TX Vref Scan disable
5871 00:22:11.918473 == TX Byte 0 ==
5872 00:22:11.925039 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5873 00:22:11.928377 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5874 00:22:11.928454 == TX Byte 1 ==
5875 00:22:11.935031 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5876 00:22:11.938521 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5877 00:22:11.938596
5878 00:22:11.938654 [DATLAT]
5879 00:22:11.941946 Freq=933, CH1 RK1
5880 00:22:11.942022
5881 00:22:11.942081 DATLAT Default: 0xb
5882 00:22:11.944946 0, 0xFFFF, sum = 0
5883 00:22:11.945023 1, 0xFFFF, sum = 0
5884 00:22:11.948168 2, 0xFFFF, sum = 0
5885 00:22:11.948245 3, 0xFFFF, sum = 0
5886 00:22:11.951829 4, 0xFFFF, sum = 0
5887 00:22:11.951906 5, 0xFFFF, sum = 0
5888 00:22:11.955039 6, 0xFFFF, sum = 0
5889 00:22:11.955116 7, 0xFFFF, sum = 0
5890 00:22:11.958242 8, 0xFFFF, sum = 0
5891 00:22:11.961864 9, 0xFFFF, sum = 0
5892 00:22:11.961941 10, 0x0, sum = 1
5893 00:22:11.962000 11, 0x0, sum = 2
5894 00:22:11.965082 12, 0x0, sum = 3
5895 00:22:11.965159 13, 0x0, sum = 4
5896 00:22:11.968466 best_step = 11
5897 00:22:11.968543
5898 00:22:11.968602 ==
5899 00:22:11.971988 Dram Type= 6, Freq= 0, CH_1, rank 1
5900 00:22:11.974938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5901 00:22:11.975015 ==
5902 00:22:11.978533 RX Vref Scan: 0
5903 00:22:11.978609
5904 00:22:11.978667 RX Vref 0 -> 0, step: 1
5905 00:22:11.978722
5906 00:22:11.981432 RX Delay -53 -> 252, step: 4
5907 00:22:11.988726 iDelay=199, Bit 0, Center 108 (31 ~ 186) 156
5908 00:22:11.992202 iDelay=199, Bit 1, Center 98 (19 ~ 178) 160
5909 00:22:11.995723 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5910 00:22:11.998624 iDelay=199, Bit 3, Center 102 (19 ~ 186) 168
5911 00:22:12.002253 iDelay=199, Bit 4, Center 106 (27 ~ 186) 160
5912 00:22:12.008674 iDelay=199, Bit 5, Center 114 (31 ~ 198) 168
5913 00:22:12.012124 iDelay=199, Bit 6, Center 114 (35 ~ 194) 160
5914 00:22:12.015772 iDelay=199, Bit 7, Center 102 (23 ~ 182) 160
5915 00:22:12.018801 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5916 00:22:12.022337 iDelay=199, Bit 9, Center 86 (3 ~ 170) 168
5917 00:22:12.025299 iDelay=199, Bit 10, Center 98 (15 ~ 182) 168
5918 00:22:12.032327 iDelay=199, Bit 11, Center 90 (3 ~ 178) 176
5919 00:22:12.035416 iDelay=199, Bit 12, Center 108 (23 ~ 194) 172
5920 00:22:12.038912 iDelay=199, Bit 13, Center 104 (19 ~ 190) 172
5921 00:22:12.042241 iDelay=199, Bit 14, Center 102 (15 ~ 190) 176
5922 00:22:12.045693 iDelay=199, Bit 15, Center 106 (19 ~ 194) 176
5923 00:22:12.048836 ==
5924 00:22:12.052363 Dram Type= 6, Freq= 0, CH_1, rank 1
5925 00:22:12.055600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5926 00:22:12.055677 ==
5927 00:22:12.055736 DQS Delay:
5928 00:22:12.058617 DQS0 = 0, DQS1 = 0
5929 00:22:12.058692 DQM Delay:
5930 00:22:12.061861 DQM0 = 104, DQM1 = 97
5931 00:22:12.061937 DQ Delay:
5932 00:22:12.065150 DQ0 =108, DQ1 =98, DQ2 =94, DQ3 =102
5933 00:22:12.069050 DQ4 =106, DQ5 =114, DQ6 =114, DQ7 =102
5934 00:22:12.071802 DQ8 =84, DQ9 =86, DQ10 =98, DQ11 =90
5935 00:22:12.075397 DQ12 =108, DQ13 =104, DQ14 =102, DQ15 =106
5936 00:22:12.075473
5937 00:22:12.075532
5938 00:22:12.085193 [DQSOSCAuto] RK1, (LSB)MR18= 0x22ff, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 411 ps
5939 00:22:12.085284 CH1 RK1: MR19=504, MR18=22FF
5940 00:22:12.091683 CH1_RK1: MR19=0x504, MR18=0x22FF, DQSOSC=411, MR23=63, INC=64, DEC=42
5941 00:22:12.095100 [RxdqsGatingPostProcess] freq 933
5942 00:22:12.101681 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5943 00:22:12.105184 best DQS0 dly(2T, 0.5T) = (0, 10)
5944 00:22:12.108567 best DQS1 dly(2T, 0.5T) = (0, 10)
5945 00:22:12.111855 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5946 00:22:12.115428 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5947 00:22:12.115560 best DQS0 dly(2T, 0.5T) = (0, 10)
5948 00:22:12.118368 best DQS1 dly(2T, 0.5T) = (0, 10)
5949 00:22:12.122069 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5950 00:22:12.125429 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5951 00:22:12.128575 Pre-setting of DQS Precalculation
5952 00:22:12.135329 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5953 00:22:12.141667 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5954 00:22:12.148475 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5955 00:22:12.148547
5956 00:22:12.148633
5957 00:22:12.152094 [Calibration Summary] 1866 Mbps
5958 00:22:12.152197 CH 0, Rank 0
5959 00:22:12.155274 SW Impedance : PASS
5960 00:22:12.158685 DUTY Scan : NO K
5961 00:22:12.158749 ZQ Calibration : PASS
5962 00:22:12.162115 Jitter Meter : NO K
5963 00:22:12.164980 CBT Training : PASS
5964 00:22:12.165060 Write leveling : PASS
5965 00:22:12.168742 RX DQS gating : PASS
5966 00:22:12.171673 RX DQ/DQS(RDDQC) : PASS
5967 00:22:12.171758 TX DQ/DQS : PASS
5968 00:22:12.175056 RX DATLAT : PASS
5969 00:22:12.178578 RX DQ/DQS(Engine): PASS
5970 00:22:12.178653 TX OE : NO K
5971 00:22:12.178712 All Pass.
5972 00:22:12.181773
5973 00:22:12.181848 CH 0, Rank 1
5974 00:22:12.185522 SW Impedance : PASS
5975 00:22:12.185597 DUTY Scan : NO K
5976 00:22:12.188391 ZQ Calibration : PASS
5977 00:22:12.188466 Jitter Meter : NO K
5978 00:22:12.191805 CBT Training : PASS
5979 00:22:12.195417 Write leveling : PASS
5980 00:22:12.195492 RX DQS gating : PASS
5981 00:22:12.198819 RX DQ/DQS(RDDQC) : PASS
5982 00:22:12.201746 TX DQ/DQS : PASS
5983 00:22:12.201823 RX DATLAT : PASS
5984 00:22:12.205197 RX DQ/DQS(Engine): PASS
5985 00:22:12.208642 TX OE : NO K
5986 00:22:12.208745 All Pass.
5987 00:22:12.208807
5988 00:22:12.208861 CH 1, Rank 0
5989 00:22:12.211752 SW Impedance : PASS
5990 00:22:12.215157 DUTY Scan : NO K
5991 00:22:12.215233 ZQ Calibration : PASS
5992 00:22:12.218296 Jitter Meter : NO K
5993 00:22:12.221923 CBT Training : PASS
5994 00:22:12.222000 Write leveling : PASS
5995 00:22:12.224875 RX DQS gating : PASS
5996 00:22:12.228763 RX DQ/DQS(RDDQC) : PASS
5997 00:22:12.228842 TX DQ/DQS : PASS
5998 00:22:12.231772 RX DATLAT : PASS
5999 00:22:12.231849 RX DQ/DQS(Engine): PASS
6000 00:22:12.234836 TX OE : NO K
6001 00:22:12.234913 All Pass.
6002 00:22:12.234972
6003 00:22:12.238409 CH 1, Rank 1
6004 00:22:12.238486 SW Impedance : PASS
6005 00:22:12.241902 DUTY Scan : NO K
6006 00:22:12.244981 ZQ Calibration : PASS
6007 00:22:12.245058 Jitter Meter : NO K
6008 00:22:12.248294 CBT Training : PASS
6009 00:22:12.251802 Write leveling : PASS
6010 00:22:12.251879 RX DQS gating : PASS
6011 00:22:12.254978 RX DQ/DQS(RDDQC) : PASS
6012 00:22:12.258343 TX DQ/DQS : PASS
6013 00:22:12.258420 RX DATLAT : PASS
6014 00:22:12.261439 RX DQ/DQS(Engine): PASS
6015 00:22:12.264673 TX OE : NO K
6016 00:22:12.264758 All Pass.
6017 00:22:12.264818
6018 00:22:12.267996 DramC Write-DBI off
6019 00:22:12.268072 PER_BANK_REFRESH: Hybrid Mode
6020 00:22:12.271655 TX_TRACKING: ON
6021 00:22:12.278265 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6022 00:22:12.284586 [FAST_K] Save calibration result to emmc
6023 00:22:12.288051 dramc_set_vcore_voltage set vcore to 650000
6024 00:22:12.288129 Read voltage for 400, 6
6025 00:22:12.291628 Vio18 = 0
6026 00:22:12.291706 Vcore = 650000
6027 00:22:12.291765 Vdram = 0
6028 00:22:12.294816 Vddq = 0
6029 00:22:12.294893 Vmddr = 0
6030 00:22:12.297817 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6031 00:22:12.304812 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6032 00:22:12.307867 MEM_TYPE=3, freq_sel=20
6033 00:22:12.311251 sv_algorithm_assistance_LP4_800
6034 00:22:12.314895 ============ PULL DRAM RESETB DOWN ============
6035 00:22:12.317834 ========== PULL DRAM RESETB DOWN end =========
6036 00:22:12.324641 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6037 00:22:12.324758 ===================================
6038 00:22:12.327896 LPDDR4 DRAM CONFIGURATION
6039 00:22:12.331143 ===================================
6040 00:22:12.334203 EX_ROW_EN[0] = 0x0
6041 00:22:12.334279 EX_ROW_EN[1] = 0x0
6042 00:22:12.338102 LP4Y_EN = 0x0
6043 00:22:12.338178 WORK_FSP = 0x0
6044 00:22:12.340924 WL = 0x2
6045 00:22:12.341000 RL = 0x2
6046 00:22:12.344366 BL = 0x2
6047 00:22:12.344441 RPST = 0x0
6048 00:22:12.347856 RD_PRE = 0x0
6049 00:22:12.350845 WR_PRE = 0x1
6050 00:22:12.350921 WR_PST = 0x0
6051 00:22:12.354383 DBI_WR = 0x0
6052 00:22:12.354458 DBI_RD = 0x0
6053 00:22:12.357856 OTF = 0x1
6054 00:22:12.361176 ===================================
6055 00:22:12.364357 ===================================
6056 00:22:12.364432 ANA top config
6057 00:22:12.367717 ===================================
6058 00:22:12.371079 DLL_ASYNC_EN = 0
6059 00:22:12.374149 ALL_SLAVE_EN = 1
6060 00:22:12.374224 NEW_RANK_MODE = 1
6061 00:22:12.377453 DLL_IDLE_MODE = 1
6062 00:22:12.380693 LP45_APHY_COMB_EN = 1
6063 00:22:12.384163 TX_ODT_DIS = 1
6064 00:22:12.384239 NEW_8X_MODE = 1
6065 00:22:12.387480 ===================================
6066 00:22:12.391023 ===================================
6067 00:22:12.394100 data_rate = 800
6068 00:22:12.397698 CKR = 1
6069 00:22:12.400824 DQ_P2S_RATIO = 4
6070 00:22:12.404115 ===================================
6071 00:22:12.407501 CA_P2S_RATIO = 4
6072 00:22:12.410985 DQ_CA_OPEN = 0
6073 00:22:12.411096 DQ_SEMI_OPEN = 1
6074 00:22:12.414452 CA_SEMI_OPEN = 1
6075 00:22:12.417467 CA_FULL_RATE = 0
6076 00:22:12.420870 DQ_CKDIV4_EN = 0
6077 00:22:12.424401 CA_CKDIV4_EN = 1
6078 00:22:12.427803 CA_PREDIV_EN = 0
6079 00:22:12.427879 PH8_DLY = 0
6080 00:22:12.430724 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6081 00:22:12.434063 DQ_AAMCK_DIV = 0
6082 00:22:12.437481 CA_AAMCK_DIV = 0
6083 00:22:12.440673 CA_ADMCK_DIV = 4
6084 00:22:12.444315 DQ_TRACK_CA_EN = 0
6085 00:22:12.444391 CA_PICK = 800
6086 00:22:12.447777 CA_MCKIO = 400
6087 00:22:12.450684 MCKIO_SEMI = 400
6088 00:22:12.454307 PLL_FREQ = 3016
6089 00:22:12.457736 DQ_UI_PI_RATIO = 32
6090 00:22:12.460644 CA_UI_PI_RATIO = 32
6091 00:22:12.464282 ===================================
6092 00:22:12.467223 ===================================
6093 00:22:12.470987 memory_type:LPDDR4
6094 00:22:12.471062 GP_NUM : 10
6095 00:22:12.473941 SRAM_EN : 1
6096 00:22:12.474017 MD32_EN : 0
6097 00:22:12.477649 ===================================
6098 00:22:12.480607 [ANA_INIT] >>>>>>>>>>>>>>
6099 00:22:12.483828 <<<<<< [CONFIGURE PHASE]: ANA_TX
6100 00:22:12.487302 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6101 00:22:12.490542 ===================================
6102 00:22:12.493752 data_rate = 800,PCW = 0X7400
6103 00:22:12.497183 ===================================
6104 00:22:12.500535 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6105 00:22:12.503972 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6106 00:22:12.517262 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6107 00:22:12.520387 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6108 00:22:12.523704 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6109 00:22:12.527219 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6110 00:22:12.530407 [ANA_INIT] flow start
6111 00:22:12.533950 [ANA_INIT] PLL >>>>>>>>
6112 00:22:12.534025 [ANA_INIT] PLL <<<<<<<<
6113 00:22:12.537314 [ANA_INIT] MIDPI >>>>>>>>
6114 00:22:12.540364 [ANA_INIT] MIDPI <<<<<<<<
6115 00:22:12.540439 [ANA_INIT] DLL >>>>>>>>
6116 00:22:12.544323 [ANA_INIT] flow end
6117 00:22:12.547222 ============ LP4 DIFF to SE enter ============
6118 00:22:12.550731 ============ LP4 DIFF to SE exit ============
6119 00:22:12.554022 [ANA_INIT] <<<<<<<<<<<<<
6120 00:22:12.557469 [Flow] Enable top DCM control >>>>>
6121 00:22:12.560901 [Flow] Enable top DCM control <<<<<
6122 00:22:12.563929 Enable DLL master slave shuffle
6123 00:22:12.570727 ==============================================================
6124 00:22:12.570803 Gating Mode config
6125 00:22:12.577455 ==============================================================
6126 00:22:12.577532 Config description:
6127 00:22:12.587282 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6128 00:22:12.593795 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6129 00:22:12.600362 SELPH_MODE 0: By rank 1: By Phase
6130 00:22:12.603684 ==============================================================
6131 00:22:12.607101 GAT_TRACK_EN = 0
6132 00:22:12.610227 RX_GATING_MODE = 2
6133 00:22:12.613586 RX_GATING_TRACK_MODE = 2
6134 00:22:12.617199 SELPH_MODE = 1
6135 00:22:12.620366 PICG_EARLY_EN = 1
6136 00:22:12.623843 VALID_LAT_VALUE = 1
6137 00:22:12.630283 ==============================================================
6138 00:22:12.633685 Enter into Gating configuration >>>>
6139 00:22:12.636928 Exit from Gating configuration <<<<
6140 00:22:12.640309 Enter into DVFS_PRE_config >>>>>
6141 00:22:12.650217 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6142 00:22:12.653245 Exit from DVFS_PRE_config <<<<<
6143 00:22:12.656821 Enter into PICG configuration >>>>
6144 00:22:12.659906 Exit from PICG configuration <<<<
6145 00:22:12.663351 [RX_INPUT] configuration >>>>>
6146 00:22:12.663428 [RX_INPUT] configuration <<<<<
6147 00:22:12.670288 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6148 00:22:12.676683 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6149 00:22:12.679888 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6150 00:22:12.686685 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6151 00:22:12.693124 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6152 00:22:12.700019 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6153 00:22:12.703055 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6154 00:22:12.706639 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6155 00:22:12.713533 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6156 00:22:12.716412 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6157 00:22:12.719739 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6158 00:22:12.726685 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6159 00:22:12.726760 ===================================
6160 00:22:12.730069 LPDDR4 DRAM CONFIGURATION
6161 00:22:12.733139 ===================================
6162 00:22:12.736413 EX_ROW_EN[0] = 0x0
6163 00:22:12.736487 EX_ROW_EN[1] = 0x0
6164 00:22:12.739846 LP4Y_EN = 0x0
6165 00:22:12.739919 WORK_FSP = 0x0
6166 00:22:12.743297 WL = 0x2
6167 00:22:12.743370 RL = 0x2
6168 00:22:12.746390 BL = 0x2
6169 00:22:12.746464 RPST = 0x0
6170 00:22:12.749864 RD_PRE = 0x0
6171 00:22:12.749938 WR_PRE = 0x1
6172 00:22:12.753407 WR_PST = 0x0
6173 00:22:12.756293 DBI_WR = 0x0
6174 00:22:12.756366 DBI_RD = 0x0
6175 00:22:12.759812 OTF = 0x1
6176 00:22:12.763125 ===================================
6177 00:22:12.766258 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6178 00:22:12.769425 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6179 00:22:12.772992 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6180 00:22:12.776387 ===================================
6181 00:22:12.779726 LPDDR4 DRAM CONFIGURATION
6182 00:22:12.782756 ===================================
6183 00:22:12.786298 EX_ROW_EN[0] = 0x10
6184 00:22:12.786373 EX_ROW_EN[1] = 0x0
6185 00:22:12.789720 LP4Y_EN = 0x0
6186 00:22:12.789794 WORK_FSP = 0x0
6187 00:22:12.792671 WL = 0x2
6188 00:22:12.792752 RL = 0x2
6189 00:22:12.795997 BL = 0x2
6190 00:22:12.796071 RPST = 0x0
6191 00:22:12.799432 RD_PRE = 0x0
6192 00:22:12.799505 WR_PRE = 0x1
6193 00:22:12.802858 WR_PST = 0x0
6194 00:22:12.802932 DBI_WR = 0x0
6195 00:22:12.806360 DBI_RD = 0x0
6196 00:22:12.809732 OTF = 0x1
6197 00:22:12.812636 ===================================
6198 00:22:12.816129 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6199 00:22:12.821290 nWR fixed to 30
6200 00:22:12.824409 [ModeRegInit_LP4] CH0 RK0
6201 00:22:12.824485 [ModeRegInit_LP4] CH0 RK1
6202 00:22:12.827845 [ModeRegInit_LP4] CH1 RK0
6203 00:22:12.831167 [ModeRegInit_LP4] CH1 RK1
6204 00:22:12.831242 match AC timing 19
6205 00:22:12.837895 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6206 00:22:12.841296 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6207 00:22:12.844664 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6208 00:22:12.851318 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6209 00:22:12.854667 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6210 00:22:12.854744 ==
6211 00:22:12.857659 Dram Type= 6, Freq= 0, CH_0, rank 0
6212 00:22:12.861377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6213 00:22:12.861453 ==
6214 00:22:12.867709 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6215 00:22:12.874464 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6216 00:22:12.877752 [CA 0] Center 36 (8~64) winsize 57
6217 00:22:12.881146 [CA 1] Center 36 (8~64) winsize 57
6218 00:22:12.884630 [CA 2] Center 36 (8~64) winsize 57
6219 00:22:12.884715 [CA 3] Center 36 (8~64) winsize 57
6220 00:22:12.887838 [CA 4] Center 36 (8~64) winsize 57
6221 00:22:12.891268 [CA 5] Center 36 (8~64) winsize 57
6222 00:22:12.891345
6223 00:22:12.897579 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6224 00:22:12.897658
6225 00:22:12.900954 [CATrainingPosCal] consider 1 rank data
6226 00:22:12.901032 u2DelayCellTimex100 = 270/100 ps
6227 00:22:12.907711 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6228 00:22:12.911104 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6229 00:22:12.914397 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6230 00:22:12.917522 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6231 00:22:12.920921 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6232 00:22:12.924218 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6233 00:22:12.924296
6234 00:22:12.927630 CA PerBit enable=1, Macro0, CA PI delay=36
6235 00:22:12.927707
6236 00:22:12.930931 [CBTSetCACLKResult] CA Dly = 36
6237 00:22:12.934231 CS Dly: 1 (0~32)
6238 00:22:12.934309 ==
6239 00:22:12.937456 Dram Type= 6, Freq= 0, CH_0, rank 1
6240 00:22:12.940985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6241 00:22:12.941064 ==
6242 00:22:12.947627 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6243 00:22:12.951171 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6244 00:22:12.954419 [CA 0] Center 36 (8~64) winsize 57
6245 00:22:12.957918 [CA 1] Center 36 (8~64) winsize 57
6246 00:22:12.960750 [CA 2] Center 36 (8~64) winsize 57
6247 00:22:12.964293 [CA 3] Center 36 (8~64) winsize 57
6248 00:22:12.967704 [CA 4] Center 36 (8~64) winsize 57
6249 00:22:12.971233 [CA 5] Center 36 (8~64) winsize 57
6250 00:22:12.971311
6251 00:22:12.974153 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6252 00:22:12.974231
6253 00:22:12.977640 [CATrainingPosCal] consider 2 rank data
6254 00:22:12.980746 u2DelayCellTimex100 = 270/100 ps
6255 00:22:12.984257 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6256 00:22:12.987753 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6257 00:22:12.990701 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6258 00:22:12.994484 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6259 00:22:13.000835 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6260 00:22:13.004167 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6261 00:22:13.004247
6262 00:22:13.007736 CA PerBit enable=1, Macro0, CA PI delay=36
6263 00:22:13.007813
6264 00:22:13.010690 [CBTSetCACLKResult] CA Dly = 36
6265 00:22:13.010768 CS Dly: 1 (0~32)
6266 00:22:13.010827
6267 00:22:13.014112 ----->DramcWriteLeveling(PI) begin...
6268 00:22:13.014191 ==
6269 00:22:13.017340 Dram Type= 6, Freq= 0, CH_0, rank 0
6270 00:22:13.024327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6271 00:22:13.024423 ==
6272 00:22:13.027939 Write leveling (Byte 0): 40 => 8
6273 00:22:13.028019 Write leveling (Byte 1): 32 => 0
6274 00:22:13.030811 DramcWriteLeveling(PI) end<-----
6275 00:22:13.030890
6276 00:22:13.030948 ==
6277 00:22:13.034151 Dram Type= 6, Freq= 0, CH_0, rank 0
6278 00:22:13.040700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6279 00:22:13.040837 ==
6280 00:22:13.044218 [Gating] SW mode calibration
6281 00:22:13.050783 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6282 00:22:13.054123 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6283 00:22:13.060931 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6284 00:22:13.064358 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6285 00:22:13.067247 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6286 00:22:13.074143 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6287 00:22:13.077718 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6288 00:22:13.080693 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6289 00:22:13.087254 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6290 00:22:13.090770 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6291 00:22:13.093877 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6292 00:22:13.097701 Total UI for P1: 0, mck2ui 16
6293 00:22:13.100727 best dqsien dly found for B0: ( 0, 14, 24)
6294 00:22:13.104073 Total UI for P1: 0, mck2ui 16
6295 00:22:13.107492 best dqsien dly found for B1: ( 0, 14, 24)
6296 00:22:13.110991 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6297 00:22:13.114464 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6298 00:22:13.114552
6299 00:22:13.117519 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6300 00:22:13.124174 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6301 00:22:13.124273 [Gating] SW calibration Done
6302 00:22:13.124336 ==
6303 00:22:13.127407 Dram Type= 6, Freq= 0, CH_0, rank 0
6304 00:22:13.133936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6305 00:22:13.134039 ==
6306 00:22:13.134101 RX Vref Scan: 0
6307 00:22:13.134156
6308 00:22:13.137377 RX Vref 0 -> 0, step: 1
6309 00:22:13.137456
6310 00:22:13.140690 RX Delay -410 -> 252, step: 16
6311 00:22:13.143917 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6312 00:22:13.147265 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6313 00:22:13.153885 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6314 00:22:13.157382 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6315 00:22:13.160724 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6316 00:22:13.163783 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6317 00:22:13.170346 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6318 00:22:13.173778 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6319 00:22:13.177305 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6320 00:22:13.180708 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6321 00:22:13.187263 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6322 00:22:13.190901 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6323 00:22:13.193763 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6324 00:22:13.197002 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6325 00:22:13.203857 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6326 00:22:13.207280 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6327 00:22:13.207369 ==
6328 00:22:13.210748 Dram Type= 6, Freq= 0, CH_0, rank 0
6329 00:22:13.213730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6330 00:22:13.213814 ==
6331 00:22:13.217170 DQS Delay:
6332 00:22:13.217250 DQS0 = 27, DQS1 = 43
6333 00:22:13.217311 DQM Delay:
6334 00:22:13.220669 DQM0 = 12, DQM1 = 13
6335 00:22:13.220790 DQ Delay:
6336 00:22:13.223634 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6337 00:22:13.227365 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6338 00:22:13.230628 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6339 00:22:13.233712 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6340 00:22:13.233794
6341 00:22:13.233852
6342 00:22:13.233906 ==
6343 00:22:13.237127 Dram Type= 6, Freq= 0, CH_0, rank 0
6344 00:22:13.240655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6345 00:22:13.243798 ==
6346 00:22:13.243878
6347 00:22:13.243936
6348 00:22:13.243990 TX Vref Scan disable
6349 00:22:13.246957 == TX Byte 0 ==
6350 00:22:13.250190 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6351 00:22:13.253576 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6352 00:22:13.257113 == TX Byte 1 ==
6353 00:22:13.260480 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6354 00:22:13.263870 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6355 00:22:13.263952 ==
6356 00:22:13.266889 Dram Type= 6, Freq= 0, CH_0, rank 0
6357 00:22:13.273907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6358 00:22:13.273998 ==
6359 00:22:13.274060
6360 00:22:13.274114
6361 00:22:13.274165 TX Vref Scan disable
6362 00:22:13.276727 == TX Byte 0 ==
6363 00:22:13.280461 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6364 00:22:13.284024 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6365 00:22:13.286850 == TX Byte 1 ==
6366 00:22:13.290373 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6367 00:22:13.293813 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6368 00:22:13.293895
6369 00:22:13.296722 [DATLAT]
6370 00:22:13.296800 Freq=400, CH0 RK0
6371 00:22:13.296861
6372 00:22:13.300344 DATLAT Default: 0xf
6373 00:22:13.300423 0, 0xFFFF, sum = 0
6374 00:22:13.303760 1, 0xFFFF, sum = 0
6375 00:22:13.303841 2, 0xFFFF, sum = 0
6376 00:22:13.307045 3, 0xFFFF, sum = 0
6377 00:22:13.307129 4, 0xFFFF, sum = 0
6378 00:22:13.310431 5, 0xFFFF, sum = 0
6379 00:22:13.310533 6, 0xFFFF, sum = 0
6380 00:22:13.313742 7, 0xFFFF, sum = 0
6381 00:22:13.313828 8, 0xFFFF, sum = 0
6382 00:22:13.317015 9, 0xFFFF, sum = 0
6383 00:22:13.317098 10, 0xFFFF, sum = 0
6384 00:22:13.320380 11, 0xFFFF, sum = 0
6385 00:22:13.320462 12, 0xFFFF, sum = 0
6386 00:22:13.323770 13, 0x0, sum = 1
6387 00:22:13.323852 14, 0x0, sum = 2
6388 00:22:13.327251 15, 0x0, sum = 3
6389 00:22:13.327332 16, 0x0, sum = 4
6390 00:22:13.330460 best_step = 14
6391 00:22:13.330539
6392 00:22:13.330600 ==
6393 00:22:13.333571 Dram Type= 6, Freq= 0, CH_0, rank 0
6394 00:22:13.337045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6395 00:22:13.337127 ==
6396 00:22:13.340021 RX Vref Scan: 1
6397 00:22:13.340099
6398 00:22:13.340159 RX Vref 0 -> 0, step: 1
6399 00:22:13.340216
6400 00:22:13.343485 RX Delay -327 -> 252, step: 8
6401 00:22:13.343562
6402 00:22:13.347004 Set Vref, RX VrefLevel [Byte0]: 59
6403 00:22:13.350205 [Byte1]: 50
6404 00:22:13.355208
6405 00:22:13.355295 Final RX Vref Byte 0 = 59 to rank0
6406 00:22:13.358039 Final RX Vref Byte 1 = 50 to rank0
6407 00:22:13.361851 Final RX Vref Byte 0 = 59 to rank1
6408 00:22:13.364856 Final RX Vref Byte 1 = 50 to rank1==
6409 00:22:13.368423 Dram Type= 6, Freq= 0, CH_0, rank 0
6410 00:22:13.374979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6411 00:22:13.375075 ==
6412 00:22:13.375136 DQS Delay:
6413 00:22:13.378388 DQS0 = 28, DQS1 = 48
6414 00:22:13.378469 DQM Delay:
6415 00:22:13.378530 DQM0 = 12, DQM1 = 14
6416 00:22:13.381564 DQ Delay:
6417 00:22:13.384666 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6418 00:22:13.384808 DQ4 =12, DQ5 =0, DQ6 =24, DQ7 =20
6419 00:22:13.388336 DQ8 =8, DQ9 =0, DQ10 =12, DQ11 =8
6420 00:22:13.391737 DQ12 =20, DQ13 =16, DQ14 =28, DQ15 =24
6421 00:22:13.391820
6422 00:22:13.395205
6423 00:22:13.401632 [DQSOSCAuto] RK0, (LSB)MR18= 0xb7ae, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 387 ps
6424 00:22:13.404642 CH0 RK0: MR19=C0C, MR18=B7AE
6425 00:22:13.411747 CH0_RK0: MR19=0xC0C, MR18=0xB7AE, DQSOSC=387, MR23=63, INC=394, DEC=262
6426 00:22:13.411825 ==
6427 00:22:13.414881 Dram Type= 6, Freq= 0, CH_0, rank 1
6428 00:22:13.418161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6429 00:22:13.418263 ==
6430 00:22:13.421292 [Gating] SW mode calibration
6431 00:22:13.427849 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6432 00:22:13.434679 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6433 00:22:13.438024 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6434 00:22:13.441419 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6435 00:22:13.447770 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6436 00:22:13.451297 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6437 00:22:13.454364 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6438 00:22:13.458089 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6439 00:22:13.464676 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6440 00:22:13.467866 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6441 00:22:13.470914 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6442 00:22:13.474473 Total UI for P1: 0, mck2ui 16
6443 00:22:13.477880 best dqsien dly found for B0: ( 0, 14, 24)
6444 00:22:13.481276 Total UI for P1: 0, mck2ui 16
6445 00:22:13.484232 best dqsien dly found for B1: ( 0, 14, 24)
6446 00:22:13.487624 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6447 00:22:13.494289 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6448 00:22:13.494367
6449 00:22:13.497724 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6450 00:22:13.501315 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6451 00:22:13.504196 [Gating] SW calibration Done
6452 00:22:13.504272 ==
6453 00:22:13.507705 Dram Type= 6, Freq= 0, CH_0, rank 1
6454 00:22:13.511165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6455 00:22:13.511241 ==
6456 00:22:13.514170 RX Vref Scan: 0
6457 00:22:13.514252
6458 00:22:13.514312 RX Vref 0 -> 0, step: 1
6459 00:22:13.514366
6460 00:22:13.517764 RX Delay -410 -> 252, step: 16
6461 00:22:13.520894 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6462 00:22:13.527737 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6463 00:22:13.531257 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6464 00:22:13.534175 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6465 00:22:13.537852 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6466 00:22:13.544087 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6467 00:22:13.547606 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6468 00:22:13.550554 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6469 00:22:13.554119 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6470 00:22:13.560893 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6471 00:22:13.564087 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6472 00:22:13.567360 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6473 00:22:13.570811 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6474 00:22:13.577588 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6475 00:22:13.580721 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6476 00:22:13.584072 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6477 00:22:13.584166 ==
6478 00:22:13.587453 Dram Type= 6, Freq= 0, CH_0, rank 1
6479 00:22:13.593861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6480 00:22:13.593940 ==
6481 00:22:13.594000 DQS Delay:
6482 00:22:13.597181 DQS0 = 27, DQS1 = 43
6483 00:22:13.597259 DQM Delay:
6484 00:22:13.597318 DQM0 = 9, DQM1 = 13
6485 00:22:13.600779 DQ Delay:
6486 00:22:13.600856 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6487 00:22:13.604285 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6488 00:22:13.607328 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6489 00:22:13.610707 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =16
6490 00:22:13.610784
6491 00:22:13.610843
6492 00:22:13.614192 ==
6493 00:22:13.614271 Dram Type= 6, Freq= 0, CH_0, rank 1
6494 00:22:13.620614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6495 00:22:13.620695 ==
6496 00:22:13.620796
6497 00:22:13.620852
6498 00:22:13.624149 TX Vref Scan disable
6499 00:22:13.624226 == TX Byte 0 ==
6500 00:22:13.627456 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6501 00:22:13.633791 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6502 00:22:13.633873 == TX Byte 1 ==
6503 00:22:13.637107 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6504 00:22:13.640650 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6505 00:22:13.644163 ==
6506 00:22:13.647021 Dram Type= 6, Freq= 0, CH_0, rank 1
6507 00:22:13.650724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6508 00:22:13.650802 ==
6509 00:22:13.650861
6510 00:22:13.650916
6511 00:22:13.653887 TX Vref Scan disable
6512 00:22:13.653964 == TX Byte 0 ==
6513 00:22:13.657057 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6514 00:22:13.663891 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6515 00:22:13.663971 == TX Byte 1 ==
6516 00:22:13.667191 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6517 00:22:13.673441 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6518 00:22:13.673521
6519 00:22:13.673581 [DATLAT]
6520 00:22:13.673637 Freq=400, CH0 RK1
6521 00:22:13.673690
6522 00:22:13.676964 DATLAT Default: 0xe
6523 00:22:13.677041 0, 0xFFFF, sum = 0
6524 00:22:13.680583 1, 0xFFFF, sum = 0
6525 00:22:13.683711 2, 0xFFFF, sum = 0
6526 00:22:13.683790 3, 0xFFFF, sum = 0
6527 00:22:13.686773 4, 0xFFFF, sum = 0
6528 00:22:13.686851 5, 0xFFFF, sum = 0
6529 00:22:13.690564 6, 0xFFFF, sum = 0
6530 00:22:13.690642 7, 0xFFFF, sum = 0
6531 00:22:13.693675 8, 0xFFFF, sum = 0
6532 00:22:13.693753 9, 0xFFFF, sum = 0
6533 00:22:13.696966 10, 0xFFFF, sum = 0
6534 00:22:13.697044 11, 0xFFFF, sum = 0
6535 00:22:13.700406 12, 0xFFFF, sum = 0
6536 00:22:13.700484 13, 0x0, sum = 1
6537 00:22:13.703797 14, 0x0, sum = 2
6538 00:22:13.703876 15, 0x0, sum = 3
6539 00:22:13.706956 16, 0x0, sum = 4
6540 00:22:13.707034 best_step = 14
6541 00:22:13.707094
6542 00:22:13.707148 ==
6543 00:22:13.710203 Dram Type= 6, Freq= 0, CH_0, rank 1
6544 00:22:13.713536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6545 00:22:13.713614 ==
6546 00:22:13.717136 RX Vref Scan: 0
6547 00:22:13.717213
6548 00:22:13.720491 RX Vref 0 -> 0, step: 1
6549 00:22:13.720590
6550 00:22:13.720676 RX Delay -327 -> 252, step: 8
6551 00:22:13.729048 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6552 00:22:13.732310 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6553 00:22:13.735726 iDelay=217, Bit 2, Center -24 (-247 ~ 200) 448
6554 00:22:13.739259 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6555 00:22:13.745656 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6556 00:22:13.749236 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6557 00:22:13.752358 iDelay=217, Bit 6, Center -12 (-239 ~ 216) 456
6558 00:22:13.755757 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6559 00:22:13.762228 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6560 00:22:13.765990 iDelay=217, Bit 9, Center -44 (-271 ~ 184) 456
6561 00:22:13.768911 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6562 00:22:13.772170 iDelay=217, Bit 11, Center -32 (-255 ~ 192) 448
6563 00:22:13.778933 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6564 00:22:13.782094 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6565 00:22:13.785546 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6566 00:22:13.792191 iDelay=217, Bit 15, Center -24 (-247 ~ 200) 448
6567 00:22:13.792270 ==
6568 00:22:13.795693 Dram Type= 6, Freq= 0, CH_0, rank 1
6569 00:22:13.799202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6570 00:22:13.799280 ==
6571 00:22:13.799339 DQS Delay:
6572 00:22:13.802102 DQS0 = 28, DQS1 = 44
6573 00:22:13.802203 DQM Delay:
6574 00:22:13.805655 DQM0 = 10, DQM1 = 15
6575 00:22:13.805731 DQ Delay:
6576 00:22:13.809028 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =8
6577 00:22:13.812329 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6578 00:22:13.815438 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =12
6579 00:22:13.818733 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =20
6580 00:22:13.818811
6581 00:22:13.818871
6582 00:22:13.825662 [DQSOSCAuto] RK1, (LSB)MR18= 0xc073, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 386 ps
6583 00:22:13.828580 CH0 RK1: MR19=C0C, MR18=C073
6584 00:22:13.835406 CH0_RK1: MR19=0xC0C, MR18=0xC073, DQSOSC=386, MR23=63, INC=396, DEC=264
6585 00:22:13.838745 [RxdqsGatingPostProcess] freq 400
6586 00:22:13.845117 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6587 00:22:13.848493 best DQS0 dly(2T, 0.5T) = (0, 10)
6588 00:22:13.848571 best DQS1 dly(2T, 0.5T) = (0, 10)
6589 00:22:13.851907 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6590 00:22:13.855443 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6591 00:22:13.858443 best DQS0 dly(2T, 0.5T) = (0, 10)
6592 00:22:13.861856 best DQS1 dly(2T, 0.5T) = (0, 10)
6593 00:22:13.865264 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6594 00:22:13.868779 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6595 00:22:13.871700 Pre-setting of DQS Precalculation
6596 00:22:13.878654 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6597 00:22:13.878768 ==
6598 00:22:13.881789 Dram Type= 6, Freq= 0, CH_1, rank 0
6599 00:22:13.885283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6600 00:22:13.885385 ==
6601 00:22:13.892001 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6602 00:22:13.895172 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
6603 00:22:13.898495 [CA 0] Center 36 (8~64) winsize 57
6604 00:22:13.901821 [CA 1] Center 36 (8~64) winsize 57
6605 00:22:13.905326 [CA 2] Center 36 (8~64) winsize 57
6606 00:22:13.908734 [CA 3] Center 36 (8~64) winsize 57
6607 00:22:13.911735 [CA 4] Center 36 (8~64) winsize 57
6608 00:22:13.915348 [CA 5] Center 36 (8~64) winsize 57
6609 00:22:13.915429
6610 00:22:13.918632 [CmdBusTrainingLP45] Vref(ca) range 1: 31
6611 00:22:13.918710
6612 00:22:13.921814 [CATrainingPosCal] consider 1 rank data
6613 00:22:13.925386 u2DelayCellTimex100 = 270/100 ps
6614 00:22:13.928482 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6615 00:22:13.932037 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6616 00:22:13.935457 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6617 00:22:13.938885 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6618 00:22:13.945532 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6619 00:22:13.948616 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6620 00:22:13.948740
6621 00:22:13.952026 CA PerBit enable=1, Macro0, CA PI delay=36
6622 00:22:13.952124
6623 00:22:13.954976 [CBTSetCACLKResult] CA Dly = 36
6624 00:22:13.955052 CS Dly: 1 (0~32)
6625 00:22:13.955110 ==
6626 00:22:13.958341 Dram Type= 6, Freq= 0, CH_1, rank 1
6627 00:22:13.961840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6628 00:22:13.965257 ==
6629 00:22:13.968372 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6630 00:22:13.975408 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6631 00:22:13.978728 [CA 0] Center 36 (8~64) winsize 57
6632 00:22:13.981873 [CA 1] Center 36 (8~64) winsize 57
6633 00:22:13.985251 [CA 2] Center 36 (8~64) winsize 57
6634 00:22:13.988309 [CA 3] Center 36 (8~64) winsize 57
6635 00:22:13.991723 [CA 4] Center 36 (8~64) winsize 57
6636 00:22:13.995357 [CA 5] Center 36 (8~64) winsize 57
6637 00:22:13.995435
6638 00:22:13.998461 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6639 00:22:13.998538
6640 00:22:14.002144 [CATrainingPosCal] consider 2 rank data
6641 00:22:14.005218 u2DelayCellTimex100 = 270/100 ps
6642 00:22:14.008775 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6643 00:22:14.011808 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6644 00:22:14.015298 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6645 00:22:14.018628 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6646 00:22:14.022025 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6647 00:22:14.025052 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6648 00:22:14.025127
6649 00:22:14.028352 CA PerBit enable=1, Macro0, CA PI delay=36
6650 00:22:14.028427
6651 00:22:14.032056 [CBTSetCACLKResult] CA Dly = 36
6652 00:22:14.035329 CS Dly: 1 (0~32)
6653 00:22:14.035418
6654 00:22:14.038545 ----->DramcWriteLeveling(PI) begin...
6655 00:22:14.038636 ==
6656 00:22:14.041894 Dram Type= 6, Freq= 0, CH_1, rank 0
6657 00:22:14.045004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6658 00:22:14.045080 ==
6659 00:22:14.048784 Write leveling (Byte 0): 40 => 8
6660 00:22:14.051603 Write leveling (Byte 1): 32 => 0
6661 00:22:14.055183 DramcWriteLeveling(PI) end<-----
6662 00:22:14.055264
6663 00:22:14.055321 ==
6664 00:22:14.058715 Dram Type= 6, Freq= 0, CH_1, rank 0
6665 00:22:14.061614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6666 00:22:14.061691 ==
6667 00:22:14.065087 [Gating] SW mode calibration
6668 00:22:14.071731 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6669 00:22:14.078204 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6670 00:22:14.081837 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6671 00:22:14.088209 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6672 00:22:14.091942 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6673 00:22:14.094768 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6674 00:22:14.098341 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6675 00:22:14.105132 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6676 00:22:14.108522 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6677 00:22:14.111381 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6678 00:22:14.118404 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6679 00:22:14.121530 Total UI for P1: 0, mck2ui 16
6680 00:22:14.124751 best dqsien dly found for B0: ( 0, 14, 24)
6681 00:22:14.128177 Total UI for P1: 0, mck2ui 16
6682 00:22:14.131774 best dqsien dly found for B1: ( 0, 14, 24)
6683 00:22:14.134760 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6684 00:22:14.138373 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6685 00:22:14.138456
6686 00:22:14.141571 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6687 00:22:14.145019 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6688 00:22:14.148367 [Gating] SW calibration Done
6689 00:22:14.148444 ==
6690 00:22:14.151701 Dram Type= 6, Freq= 0, CH_1, rank 0
6691 00:22:14.155148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6692 00:22:14.155224 ==
6693 00:22:14.158157 RX Vref Scan: 0
6694 00:22:14.158233
6695 00:22:14.158290 RX Vref 0 -> 0, step: 1
6696 00:22:14.161624
6697 00:22:14.161700 RX Delay -410 -> 252, step: 16
6698 00:22:14.168411 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6699 00:22:14.171779 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6700 00:22:14.174800 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6701 00:22:14.178240 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6702 00:22:14.184700 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6703 00:22:14.188195 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6704 00:22:14.191588 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6705 00:22:14.194755 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6706 00:22:14.201324 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6707 00:22:14.204864 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6708 00:22:14.208186 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6709 00:22:14.211621 iDelay=230, Bit 11, Center -19 (-250 ~ 213) 464
6710 00:22:14.217841 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6711 00:22:14.221151 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6712 00:22:14.224850 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6713 00:22:14.231365 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6714 00:22:14.231443 ==
6715 00:22:14.234287 Dram Type= 6, Freq= 0, CH_1, rank 0
6716 00:22:14.237758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6717 00:22:14.237836 ==
6718 00:22:14.237895 DQS Delay:
6719 00:22:14.241241 DQS0 = 19, DQS1 = 43
6720 00:22:14.241317 DQM Delay:
6721 00:22:14.244528 DQM0 = 2, DQM1 = 21
6722 00:22:14.244604 DQ Delay:
6723 00:22:14.247854 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6724 00:22:14.251207 DQ4 =0, DQ5 =8, DQ6 =8, DQ7 =0
6725 00:22:14.254624 DQ8 =0, DQ9 =8, DQ10 =24, DQ11 =24
6726 00:22:14.257913 DQ12 =32, DQ13 =24, DQ14 =24, DQ15 =32
6727 00:22:14.257989
6728 00:22:14.258048
6729 00:22:14.258102 ==
6730 00:22:14.261469 Dram Type= 6, Freq= 0, CH_1, rank 0
6731 00:22:14.264353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6732 00:22:14.264429 ==
6733 00:22:14.264488
6734 00:22:14.264541
6735 00:22:14.267741 TX Vref Scan disable
6736 00:22:14.267817 == TX Byte 0 ==
6737 00:22:14.274402 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6738 00:22:14.277797 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6739 00:22:14.277887 == TX Byte 1 ==
6740 00:22:14.284335 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6741 00:22:14.287828 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6742 00:22:14.287921 ==
6743 00:22:14.290734 Dram Type= 6, Freq= 0, CH_1, rank 0
6744 00:22:14.294384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6745 00:22:14.294470 ==
6746 00:22:14.294532
6747 00:22:14.294587
6748 00:22:14.297682 TX Vref Scan disable
6749 00:22:14.297766 == TX Byte 0 ==
6750 00:22:14.304213 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6751 00:22:14.307645 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6752 00:22:14.307737 == TX Byte 1 ==
6753 00:22:14.314120 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6754 00:22:14.317401 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6755 00:22:14.317503
6756 00:22:14.317564 [DATLAT]
6757 00:22:14.320998 Freq=400, CH1 RK0
6758 00:22:14.321076
6759 00:22:14.321137 DATLAT Default: 0xf
6760 00:22:14.324273 0, 0xFFFF, sum = 0
6761 00:22:14.324351 1, 0xFFFF, sum = 0
6762 00:22:14.327578 2, 0xFFFF, sum = 0
6763 00:22:14.327656 3, 0xFFFF, sum = 0
6764 00:22:14.331149 4, 0xFFFF, sum = 0
6765 00:22:14.331227 5, 0xFFFF, sum = 0
6766 00:22:14.334029 6, 0xFFFF, sum = 0
6767 00:22:14.334106 7, 0xFFFF, sum = 0
6768 00:22:14.337610 8, 0xFFFF, sum = 0
6769 00:22:14.340661 9, 0xFFFF, sum = 0
6770 00:22:14.340758 10, 0xFFFF, sum = 0
6771 00:22:14.344232 11, 0xFFFF, sum = 0
6772 00:22:14.344309 12, 0xFFFF, sum = 0
6773 00:22:14.347608 13, 0x0, sum = 1
6774 00:22:14.347686 14, 0x0, sum = 2
6775 00:22:14.350848 15, 0x0, sum = 3
6776 00:22:14.350926 16, 0x0, sum = 4
6777 00:22:14.350986 best_step = 14
6778 00:22:14.351040
6779 00:22:14.354244 ==
6780 00:22:14.357767 Dram Type= 6, Freq= 0, CH_1, rank 0
6781 00:22:14.360639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6782 00:22:14.360744 ==
6783 00:22:14.360804 RX Vref Scan: 1
6784 00:22:14.360859
6785 00:22:14.364035 RX Vref 0 -> 0, step: 1
6786 00:22:14.364112
6787 00:22:14.367097 RX Delay -327 -> 252, step: 8
6788 00:22:14.367174
6789 00:22:14.370540 Set Vref, RX VrefLevel [Byte0]: 50
6790 00:22:14.374164 [Byte1]: 52
6791 00:22:14.377618
6792 00:22:14.377693 Final RX Vref Byte 0 = 50 to rank0
6793 00:22:14.380903 Final RX Vref Byte 1 = 52 to rank0
6794 00:22:14.384468 Final RX Vref Byte 0 = 50 to rank1
6795 00:22:14.387394 Final RX Vref Byte 1 = 52 to rank1==
6796 00:22:14.390782 Dram Type= 6, Freq= 0, CH_1, rank 0
6797 00:22:14.397721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6798 00:22:14.397802 ==
6799 00:22:14.397862 DQS Delay:
6800 00:22:14.401052 DQS0 = 32, DQS1 = 40
6801 00:22:14.401130 DQM Delay:
6802 00:22:14.401189 DQM0 = 12, DQM1 = 13
6803 00:22:14.404218 DQ Delay:
6804 00:22:14.407600 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6805 00:22:14.407679 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =8
6806 00:22:14.411005 DQ8 =0, DQ9 =0, DQ10 =20, DQ11 =8
6807 00:22:14.414550 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6808 00:22:14.414653
6809 00:22:14.417318
6810 00:22:14.424423 [DQSOSCAuto] RK0, (LSB)MR18= 0x9bd5, (MSB)MR19= 0xc0c, tDQSOscB0 = 383 ps tDQSOscB1 = 390 ps
6811 00:22:14.427495 CH1 RK0: MR19=C0C, MR18=9BD5
6812 00:22:14.434097 CH1_RK0: MR19=0xC0C, MR18=0x9BD5, DQSOSC=383, MR23=63, INC=402, DEC=268
6813 00:22:14.434240 ==
6814 00:22:14.437673 Dram Type= 6, Freq= 0, CH_1, rank 1
6815 00:22:14.440621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6816 00:22:14.440794 ==
6817 00:22:14.444150 [Gating] SW mode calibration
6818 00:22:14.451175 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6819 00:22:14.457307 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6820 00:22:14.460716 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6821 00:22:14.463861 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6822 00:22:14.470476 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6823 00:22:14.473992 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6824 00:22:14.477770 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6825 00:22:14.484284 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6826 00:22:14.487630 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6827 00:22:14.490865 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6828 00:22:14.497924 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6829 00:22:14.498396 Total UI for P1: 0, mck2ui 16
6830 00:22:14.501068 best dqsien dly found for B0: ( 0, 14, 24)
6831 00:22:14.504408 Total UI for P1: 0, mck2ui 16
6832 00:22:14.508028 best dqsien dly found for B1: ( 0, 14, 24)
6833 00:22:14.511213 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6834 00:22:14.517323 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6835 00:22:14.517718
6836 00:22:14.521080 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6837 00:22:14.524406 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6838 00:22:14.527833 [Gating] SW calibration Done
6839 00:22:14.528304 ==
6840 00:22:14.530995 Dram Type= 6, Freq= 0, CH_1, rank 1
6841 00:22:14.534258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6842 00:22:14.534659 ==
6843 00:22:14.534965 RX Vref Scan: 0
6844 00:22:14.537312
6845 00:22:14.537699 RX Vref 0 -> 0, step: 1
6846 00:22:14.538002
6847 00:22:14.540730 RX Delay -410 -> 252, step: 16
6848 00:22:14.544434 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6849 00:22:14.550998 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6850 00:22:14.554342 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6851 00:22:14.557280 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6852 00:22:14.560515 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6853 00:22:14.567842 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6854 00:22:14.570622 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6855 00:22:14.574015 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6856 00:22:14.577311 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6857 00:22:14.584089 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6858 00:22:14.587212 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6859 00:22:14.590253 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6860 00:22:14.593777 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6861 00:22:14.600505 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6862 00:22:14.603633 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6863 00:22:14.607167 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6864 00:22:14.607628 ==
6865 00:22:14.610562 Dram Type= 6, Freq= 0, CH_1, rank 1
6866 00:22:14.616838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6867 00:22:14.617241 ==
6868 00:22:14.617549 DQS Delay:
6869 00:22:14.620249 DQS0 = 35, DQS1 = 35
6870 00:22:14.620640 DQM Delay:
6871 00:22:14.620990 DQM0 = 18, DQM1 = 13
6872 00:22:14.623865 DQ Delay:
6873 00:22:14.627131 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6874 00:22:14.630490 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6875 00:22:14.630906 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6876 00:22:14.633935 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6877 00:22:14.637259
6878 00:22:14.637647
6879 00:22:14.637948 ==
6880 00:22:14.640513 Dram Type= 6, Freq= 0, CH_1, rank 1
6881 00:22:14.643857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6882 00:22:14.644250 ==
6883 00:22:14.644550
6884 00:22:14.644878
6885 00:22:14.647329 TX Vref Scan disable
6886 00:22:14.647721 == TX Byte 0 ==
6887 00:22:14.650605 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6888 00:22:14.657436 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6889 00:22:14.657914 == TX Byte 1 ==
6890 00:22:14.660603 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6891 00:22:14.667141 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6892 00:22:14.667609 ==
6893 00:22:14.670238 Dram Type= 6, Freq= 0, CH_1, rank 1
6894 00:22:14.673834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6895 00:22:14.674235 ==
6896 00:22:14.674541
6897 00:22:14.674818
6898 00:22:14.677238 TX Vref Scan disable
6899 00:22:14.677708 == TX Byte 0 ==
6900 00:22:14.680759 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6901 00:22:14.686867 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6902 00:22:14.687262 == TX Byte 1 ==
6903 00:22:14.690612 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6904 00:22:14.697127 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6905 00:22:14.697597
6906 00:22:14.697904 [DATLAT]
6907 00:22:14.698184 Freq=400, CH1 RK1
6908 00:22:14.698453
6909 00:22:14.700638 DATLAT Default: 0xe
6910 00:22:14.703741 0, 0xFFFF, sum = 0
6911 00:22:14.704214 1, 0xFFFF, sum = 0
6912 00:22:14.707085 2, 0xFFFF, sum = 0
6913 00:22:14.707561 3, 0xFFFF, sum = 0
6914 00:22:14.710513 4, 0xFFFF, sum = 0
6915 00:22:14.710987 5, 0xFFFF, sum = 0
6916 00:22:14.713984 6, 0xFFFF, sum = 0
6917 00:22:14.714465 7, 0xFFFF, sum = 0
6918 00:22:14.716763 8, 0xFFFF, sum = 0
6919 00:22:14.717192 9, 0xFFFF, sum = 0
6920 00:22:14.720406 10, 0xFFFF, sum = 0
6921 00:22:14.720938 11, 0xFFFF, sum = 0
6922 00:22:14.723582 12, 0xFFFF, sum = 0
6923 00:22:14.723990 13, 0x0, sum = 1
6924 00:22:14.727290 14, 0x0, sum = 2
6925 00:22:14.727842 15, 0x0, sum = 3
6926 00:22:14.730433 16, 0x0, sum = 4
6927 00:22:14.730921 best_step = 14
6928 00:22:14.731359
6929 00:22:14.731735 ==
6930 00:22:14.733506 Dram Type= 6, Freq= 0, CH_1, rank 1
6931 00:22:14.736623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6932 00:22:14.740060 ==
6933 00:22:14.740461 RX Vref Scan: 0
6934 00:22:14.740943
6935 00:22:14.743282 RX Vref 0 -> 0, step: 1
6936 00:22:14.743681
6937 00:22:14.746806 RX Delay -311 -> 252, step: 8
6938 00:22:14.753413 iDelay=217, Bit 0, Center -16 (-231 ~ 200) 432
6939 00:22:14.757162 iDelay=217, Bit 1, Center -28 (-247 ~ 192) 440
6940 00:22:14.760332 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
6941 00:22:14.763611 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6942 00:22:14.766877 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6943 00:22:14.773844 iDelay=217, Bit 5, Center -12 (-239 ~ 216) 456
6944 00:22:14.776973 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6945 00:22:14.780437 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
6946 00:22:14.783236 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6947 00:22:14.789802 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6948 00:22:14.793263 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
6949 00:22:14.796807 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6950 00:22:14.800319 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6951 00:22:14.807218 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
6952 00:22:14.810103 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6953 00:22:14.813307 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6954 00:22:14.813710 ==
6955 00:22:14.817039 Dram Type= 6, Freq= 0, CH_1, rank 1
6956 00:22:14.823505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6957 00:22:14.823992 ==
6958 00:22:14.824339 DQS Delay:
6959 00:22:14.827086 DQS0 = 32, DQS1 = 36
6960 00:22:14.827564 DQM Delay:
6961 00:22:14.829615 DQM0 = 12, DQM1 = 12
6962 00:22:14.830046 DQ Delay:
6963 00:22:14.833040 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =12
6964 00:22:14.836673 DQ4 =16, DQ5 =20, DQ6 =20, DQ7 =12
6965 00:22:14.840128 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =8
6966 00:22:14.843407 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =24
6967 00:22:14.843884
6968 00:22:14.844188
6969 00:22:14.849722 [DQSOSCAuto] RK1, (LSB)MR18= 0xac55, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 388 ps
6970 00:22:14.853464 CH1 RK1: MR19=C0C, MR18=AC55
6971 00:22:14.860422 CH1_RK1: MR19=0xC0C, MR18=0xAC55, DQSOSC=388, MR23=63, INC=392, DEC=261
6972 00:22:14.863485 [RxdqsGatingPostProcess] freq 400
6973 00:22:14.866564 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6974 00:22:14.870398 best DQS0 dly(2T, 0.5T) = (0, 10)
6975 00:22:14.873453 best DQS1 dly(2T, 0.5T) = (0, 10)
6976 00:22:14.876896 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6977 00:22:14.880237 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6978 00:22:14.883176 best DQS0 dly(2T, 0.5T) = (0, 10)
6979 00:22:14.886687 best DQS1 dly(2T, 0.5T) = (0, 10)
6980 00:22:14.889956 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6981 00:22:14.893339 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6982 00:22:14.896482 Pre-setting of DQS Precalculation
6983 00:22:14.900063 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6984 00:22:14.909636 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6985 00:22:14.916445 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6986 00:22:14.916988
6987 00:22:14.917301
6988 00:22:14.919417 [Calibration Summary] 800 Mbps
6989 00:22:14.919885 CH 0, Rank 0
6990 00:22:14.922972 SW Impedance : PASS
6991 00:22:14.923598 DUTY Scan : NO K
6992 00:22:14.926130 ZQ Calibration : PASS
6993 00:22:14.929661 Jitter Meter : NO K
6994 00:22:14.930052 CBT Training : PASS
6995 00:22:14.932562 Write leveling : PASS
6996 00:22:14.935992 RX DQS gating : PASS
6997 00:22:14.936402 RX DQ/DQS(RDDQC) : PASS
6998 00:22:14.939587 TX DQ/DQS : PASS
6999 00:22:14.939996 RX DATLAT : PASS
7000 00:22:14.942482 RX DQ/DQS(Engine): PASS
7001 00:22:14.946032 TX OE : NO K
7002 00:22:14.946471 All Pass.
7003 00:22:14.946792
7004 00:22:14.947092 CH 0, Rank 1
7005 00:22:14.949163 SW Impedance : PASS
7006 00:22:14.952475 DUTY Scan : NO K
7007 00:22:14.952746 ZQ Calibration : PASS
7008 00:22:14.955901 Jitter Meter : NO K
7009 00:22:14.959200 CBT Training : PASS
7010 00:22:14.959390 Write leveling : NO K
7011 00:22:14.962106 RX DQS gating : PASS
7012 00:22:14.965678 RX DQ/DQS(RDDQC) : PASS
7013 00:22:14.965893 TX DQ/DQS : PASS
7014 00:22:14.968757 RX DATLAT : PASS
7015 00:22:14.972400 RX DQ/DQS(Engine): PASS
7016 00:22:14.972492 TX OE : NO K
7017 00:22:14.975194 All Pass.
7018 00:22:14.975301
7019 00:22:14.975385 CH 1, Rank 0
7020 00:22:14.978713 SW Impedance : PASS
7021 00:22:14.978805 DUTY Scan : NO K
7022 00:22:14.982078 ZQ Calibration : PASS
7023 00:22:14.985574 Jitter Meter : NO K
7024 00:22:14.985703 CBT Training : PASS
7025 00:22:14.988956 Write leveling : PASS
7026 00:22:14.989092 RX DQS gating : PASS
7027 00:22:14.992484 RX DQ/DQS(RDDQC) : PASS
7028 00:22:14.995385 TX DQ/DQS : PASS
7029 00:22:14.995497 RX DATLAT : PASS
7030 00:22:14.998514 RX DQ/DQS(Engine): PASS
7031 00:22:15.002202 TX OE : NO K
7032 00:22:15.002329 All Pass.
7033 00:22:15.002461
7034 00:22:15.002585 CH 1, Rank 1
7035 00:22:15.005298 SW Impedance : PASS
7036 00:22:15.008670 DUTY Scan : NO K
7037 00:22:15.008772 ZQ Calibration : PASS
7038 00:22:15.011742 Jitter Meter : NO K
7039 00:22:15.015434 CBT Training : PASS
7040 00:22:15.015542 Write leveling : NO K
7041 00:22:15.018815 RX DQS gating : PASS
7042 00:22:15.021780 RX DQ/DQS(RDDQC) : PASS
7043 00:22:15.021901 TX DQ/DQS : PASS
7044 00:22:15.025211 RX DATLAT : PASS
7045 00:22:15.028806 RX DQ/DQS(Engine): PASS
7046 00:22:15.028886 TX OE : NO K
7047 00:22:15.028946 All Pass.
7048 00:22:15.031707
7049 00:22:15.031806 DramC Write-DBI off
7050 00:22:15.035090 PER_BANK_REFRESH: Hybrid Mode
7051 00:22:15.035220 TX_TRACKING: ON
7052 00:22:15.045279 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7053 00:22:15.048629 [FAST_K] Save calibration result to emmc
7054 00:22:15.052108 dramc_set_vcore_voltage set vcore to 725000
7055 00:22:15.055381 Read voltage for 1600, 0
7056 00:22:15.055496 Vio18 = 0
7057 00:22:15.058366 Vcore = 725000
7058 00:22:15.058470 Vdram = 0
7059 00:22:15.058597 Vddq = 0
7060 00:22:15.058731 Vmddr = 0
7061 00:22:15.065412 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7062 00:22:15.072146 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7063 00:22:15.072224 MEM_TYPE=3, freq_sel=13
7064 00:22:15.075418 sv_algorithm_assistance_LP4_3733
7065 00:22:15.078860 ============ PULL DRAM RESETB DOWN ============
7066 00:22:15.085166 ========== PULL DRAM RESETB DOWN end =========
7067 00:22:15.088594 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7068 00:22:15.091843 ===================================
7069 00:22:15.095087 LPDDR4 DRAM CONFIGURATION
7070 00:22:15.098774 ===================================
7071 00:22:15.098862 EX_ROW_EN[0] = 0x0
7072 00:22:15.101836 EX_ROW_EN[1] = 0x0
7073 00:22:15.101914 LP4Y_EN = 0x0
7074 00:22:15.105208 WORK_FSP = 0x1
7075 00:22:15.105286 WL = 0x5
7076 00:22:15.108511 RL = 0x5
7077 00:22:15.108612 BL = 0x2
7078 00:22:15.112271 RPST = 0x0
7079 00:22:15.112349 RD_PRE = 0x0
7080 00:22:15.115227 WR_PRE = 0x1
7081 00:22:15.118648 WR_PST = 0x1
7082 00:22:15.118726 DBI_WR = 0x0
7083 00:22:15.122121 DBI_RD = 0x0
7084 00:22:15.122198 OTF = 0x1
7085 00:22:15.125413 ===================================
7086 00:22:15.128430 ===================================
7087 00:22:15.128508 ANA top config
7088 00:22:15.132213 ===================================
7089 00:22:15.135261 DLL_ASYNC_EN = 0
7090 00:22:15.138520 ALL_SLAVE_EN = 0
7091 00:22:15.142014 NEW_RANK_MODE = 1
7092 00:22:15.145383 DLL_IDLE_MODE = 1
7093 00:22:15.145480 LP45_APHY_COMB_EN = 1
7094 00:22:15.148404 TX_ODT_DIS = 0
7095 00:22:15.151851 NEW_8X_MODE = 1
7096 00:22:15.155308 ===================================
7097 00:22:15.158232 ===================================
7098 00:22:15.161873 data_rate = 3200
7099 00:22:15.165087 CKR = 1
7100 00:22:15.165204 DQ_P2S_RATIO = 8
7101 00:22:15.168557 ===================================
7102 00:22:15.171505 CA_P2S_RATIO = 8
7103 00:22:15.174776 DQ_CA_OPEN = 0
7104 00:22:15.178272 DQ_SEMI_OPEN = 0
7105 00:22:15.181808 CA_SEMI_OPEN = 0
7106 00:22:15.185006 CA_FULL_RATE = 0
7107 00:22:15.185075 DQ_CKDIV4_EN = 0
7108 00:22:15.188482 CA_CKDIV4_EN = 0
7109 00:22:15.191704 CA_PREDIV_EN = 0
7110 00:22:15.195080 PH8_DLY = 12
7111 00:22:15.198297 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7112 00:22:15.201830 DQ_AAMCK_DIV = 4
7113 00:22:15.201896 CA_AAMCK_DIV = 4
7114 00:22:15.205360 CA_ADMCK_DIV = 4
7115 00:22:15.208407 DQ_TRACK_CA_EN = 0
7116 00:22:15.211807 CA_PICK = 1600
7117 00:22:15.214802 CA_MCKIO = 1600
7118 00:22:15.218537 MCKIO_SEMI = 0
7119 00:22:15.221793 PLL_FREQ = 3068
7120 00:22:15.221869 DQ_UI_PI_RATIO = 32
7121 00:22:15.224921 CA_UI_PI_RATIO = 0
7122 00:22:15.228367 ===================================
7123 00:22:15.231596 ===================================
7124 00:22:15.234719 memory_type:LPDDR4
7125 00:22:15.238326 GP_NUM : 10
7126 00:22:15.238422 SRAM_EN : 1
7127 00:22:15.241698 MD32_EN : 0
7128 00:22:15.244622 ===================================
7129 00:22:15.248173 [ANA_INIT] >>>>>>>>>>>>>>
7130 00:22:15.248288 <<<<<< [CONFIGURE PHASE]: ANA_TX
7131 00:22:15.251591 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7132 00:22:15.255027 ===================================
7133 00:22:15.257908 data_rate = 3200,PCW = 0X7600
7134 00:22:15.261323 ===================================
7135 00:22:15.264804 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7136 00:22:15.271727 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7137 00:22:15.278196 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7138 00:22:15.281587 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7139 00:22:15.284775 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7140 00:22:15.287984 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7141 00:22:15.291540 [ANA_INIT] flow start
7142 00:22:15.291610 [ANA_INIT] PLL >>>>>>>>
7143 00:22:15.294927 [ANA_INIT] PLL <<<<<<<<
7144 00:22:15.298306 [ANA_INIT] MIDPI >>>>>>>>
7145 00:22:15.298382 [ANA_INIT] MIDPI <<<<<<<<
7146 00:22:15.301576 [ANA_INIT] DLL >>>>>>>>
7147 00:22:15.304895 [ANA_INIT] DLL <<<<<<<<
7148 00:22:15.304971 [ANA_INIT] flow end
7149 00:22:15.311315 ============ LP4 DIFF to SE enter ============
7150 00:22:15.314734 ============ LP4 DIFF to SE exit ============
7151 00:22:15.318176 [ANA_INIT] <<<<<<<<<<<<<
7152 00:22:15.321334 [Flow] Enable top DCM control >>>>>
7153 00:22:15.321412 [Flow] Enable top DCM control <<<<<
7154 00:22:15.324884 Enable DLL master slave shuffle
7155 00:22:15.331430 ==============================================================
7156 00:22:15.334900 Gating Mode config
7157 00:22:15.338013 ==============================================================
7158 00:22:15.341358 Config description:
7159 00:22:15.351227 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7160 00:22:15.358219 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7161 00:22:15.361191 SELPH_MODE 0: By rank 1: By Phase
7162 00:22:15.368264 ==============================================================
7163 00:22:15.371690 GAT_TRACK_EN = 1
7164 00:22:15.374714 RX_GATING_MODE = 2
7165 00:22:15.378187 RX_GATING_TRACK_MODE = 2
7166 00:22:15.378263 SELPH_MODE = 1
7167 00:22:15.381605 PICG_EARLY_EN = 1
7168 00:22:15.384891 VALID_LAT_VALUE = 1
7169 00:22:15.391774 ==============================================================
7170 00:22:15.394663 Enter into Gating configuration >>>>
7171 00:22:15.397967 Exit from Gating configuration <<<<
7172 00:22:15.401576 Enter into DVFS_PRE_config >>>>>
7173 00:22:15.411218 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7174 00:22:15.414640 Exit from DVFS_PRE_config <<<<<
7175 00:22:15.418096 Enter into PICG configuration >>>>
7176 00:22:15.421024 Exit from PICG configuration <<<<
7177 00:22:15.424709 [RX_INPUT] configuration >>>>>
7178 00:22:15.427620 [RX_INPUT] configuration <<<<<
7179 00:22:15.431148 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7180 00:22:15.437750 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7181 00:22:15.444508 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7182 00:22:15.450989 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7183 00:22:15.454400 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7184 00:22:15.460973 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7185 00:22:15.464575 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7186 00:22:15.470992 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7187 00:22:15.474384 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7188 00:22:15.478064 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7189 00:22:15.481075 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7190 00:22:15.488039 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7191 00:22:15.491303 ===================================
7192 00:22:15.494222 LPDDR4 DRAM CONFIGURATION
7193 00:22:15.497675 ===================================
7194 00:22:15.497961 EX_ROW_EN[0] = 0x0
7195 00:22:15.500947 EX_ROW_EN[1] = 0x0
7196 00:22:15.501202 LP4Y_EN = 0x0
7197 00:22:15.504412 WORK_FSP = 0x1
7198 00:22:15.504651 WL = 0x5
7199 00:22:15.507948 RL = 0x5
7200 00:22:15.508057 BL = 0x2
7201 00:22:15.510906 RPST = 0x0
7202 00:22:15.511008 RD_PRE = 0x0
7203 00:22:15.514462 WR_PRE = 0x1
7204 00:22:15.514574 WR_PST = 0x1
7205 00:22:15.517286 DBI_WR = 0x0
7206 00:22:15.517385 DBI_RD = 0x0
7207 00:22:15.520816 OTF = 0x1
7208 00:22:15.524254 ===================================
7209 00:22:15.527338 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7210 00:22:15.530841 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7211 00:22:15.537307 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7212 00:22:15.540840 ===================================
7213 00:22:15.540918 LPDDR4 DRAM CONFIGURATION
7214 00:22:15.544236 ===================================
7215 00:22:15.547227 EX_ROW_EN[0] = 0x10
7216 00:22:15.550869 EX_ROW_EN[1] = 0x0
7217 00:22:15.550946 LP4Y_EN = 0x0
7218 00:22:15.554036 WORK_FSP = 0x1
7219 00:22:15.554113 WL = 0x5
7220 00:22:15.557090 RL = 0x5
7221 00:22:15.557167 BL = 0x2
7222 00:22:15.560534 RPST = 0x0
7223 00:22:15.560610 RD_PRE = 0x0
7224 00:22:15.564256 WR_PRE = 0x1
7225 00:22:15.564333 WR_PST = 0x1
7226 00:22:15.567306 DBI_WR = 0x0
7227 00:22:15.567383 DBI_RD = 0x0
7228 00:22:15.570590 OTF = 0x1
7229 00:22:15.573917 ===================================
7230 00:22:15.580822 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7231 00:22:15.580900 ==
7232 00:22:15.583737 Dram Type= 6, Freq= 0, CH_0, rank 0
7233 00:22:15.587234 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7234 00:22:15.587312 ==
7235 00:22:15.590636 [Duty_Offset_Calibration]
7236 00:22:15.590713 B0:2 B1:0 CA:1
7237 00:22:15.590772
7238 00:22:15.594164 [DutyScan_Calibration_Flow] k_type=0
7239 00:22:15.603706
7240 00:22:15.603783 ==CLK 0==
7241 00:22:15.606723 Final CLK duty delay cell = -4
7242 00:22:15.610224 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7243 00:22:15.613729 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7244 00:22:15.616961 [-4] AVG Duty = 4906%(X100)
7245 00:22:15.617038
7246 00:22:15.620418 CH0 CLK Duty spec in!! Max-Min= 187%
7247 00:22:15.623376 [DutyScan_Calibration_Flow] ====Done====
7248 00:22:15.623483
7249 00:22:15.626654 [DutyScan_Calibration_Flow] k_type=1
7250 00:22:15.643116
7251 00:22:15.643238 ==DQS 0 ==
7252 00:22:15.646173 Final DQS duty delay cell = 0
7253 00:22:15.649714 [0] MAX Duty = 5218%(X100), DQS PI = 32
7254 00:22:15.652642 [0] MIN Duty = 4938%(X100), DQS PI = 62
7255 00:22:15.656007 [0] AVG Duty = 5078%(X100)
7256 00:22:15.656086
7257 00:22:15.656145 ==DQS 1 ==
7258 00:22:15.659376 Final DQS duty delay cell = -4
7259 00:22:15.663164 [-4] MAX Duty = 5094%(X100), DQS PI = 28
7260 00:22:15.666275 [-4] MIN Duty = 4844%(X100), DQS PI = 6
7261 00:22:15.669248 [-4] AVG Duty = 4969%(X100)
7262 00:22:15.669322
7263 00:22:15.672635 CH0 DQS 0 Duty spec in!! Max-Min= 280%
7264 00:22:15.672752
7265 00:22:15.675966 CH0 DQS 1 Duty spec in!! Max-Min= 250%
7266 00:22:15.679838 [DutyScan_Calibration_Flow] ====Done====
7267 00:22:15.679995
7268 00:22:15.682540 [DutyScan_Calibration_Flow] k_type=3
7269 00:22:15.700330
7270 00:22:15.700431 ==DQM 0 ==
7271 00:22:15.703781 Final DQM duty delay cell = 0
7272 00:22:15.707118 [0] MAX Duty = 5062%(X100), DQS PI = 10
7273 00:22:15.710535 [0] MIN Duty = 4813%(X100), DQS PI = 50
7274 00:22:15.713659 [0] AVG Duty = 4937%(X100)
7275 00:22:15.713730
7276 00:22:15.713797 ==DQM 1 ==
7277 00:22:15.717015 Final DQM duty delay cell = 0
7278 00:22:15.720443 [0] MAX Duty = 5249%(X100), DQS PI = 30
7279 00:22:15.723786 [0] MIN Duty = 5000%(X100), DQS PI = 20
7280 00:22:15.727092 [0] AVG Duty = 5124%(X100)
7281 00:22:15.727181
7282 00:22:15.730172 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7283 00:22:15.730262
7284 00:22:15.733600 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7285 00:22:15.736944 [DutyScan_Calibration_Flow] ====Done====
7286 00:22:15.737009
7287 00:22:15.740736 [DutyScan_Calibration_Flow] k_type=2
7288 00:22:15.758025
7289 00:22:15.758102 ==DQ 0 ==
7290 00:22:15.760942 Final DQ duty delay cell = 0
7291 00:22:15.764332 [0] MAX Duty = 5124%(X100), DQS PI = 34
7292 00:22:15.767651 [0] MIN Duty = 5000%(X100), DQS PI = 0
7293 00:22:15.767740 [0] AVG Duty = 5062%(X100)
7294 00:22:15.767819
7295 00:22:15.770725 ==DQ 1 ==
7296 00:22:15.774250 Final DQ duty delay cell = 0
7297 00:22:15.777737 [0] MAX Duty = 4969%(X100), DQS PI = 44
7298 00:22:15.781010 [0] MIN Duty = 4875%(X100), DQS PI = 0
7299 00:22:15.781080 [0] AVG Duty = 4922%(X100)
7300 00:22:15.781141
7301 00:22:15.784336 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7302 00:22:15.784433
7303 00:22:15.787878 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7304 00:22:15.794120 [DutyScan_Calibration_Flow] ====Done====
7305 00:22:15.794215 ==
7306 00:22:15.797719 Dram Type= 6, Freq= 0, CH_1, rank 0
7307 00:22:15.800975 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7308 00:22:15.801041 ==
7309 00:22:15.804372 [Duty_Offset_Calibration]
7310 00:22:15.804433 B0:0 B1:-1 CA:2
7311 00:22:15.804517
7312 00:22:15.807476 [DutyScan_Calibration_Flow] k_type=0
7313 00:22:15.818451
7314 00:22:15.819034 ==CLK 0==
7315 00:22:15.821373 Final CLK duty delay cell = 0
7316 00:22:15.824570 [0] MAX Duty = 5156%(X100), DQS PI = 10
7317 00:22:15.828064 [0] MIN Duty = 4906%(X100), DQS PI = 46
7318 00:22:15.828449 [0] AVG Duty = 5031%(X100)
7319 00:22:15.831570
7320 00:22:15.834931 CH1 CLK Duty spec in!! Max-Min= 250%
7321 00:22:15.837950 [DutyScan_Calibration_Flow] ====Done====
7322 00:22:15.838224
7323 00:22:15.841274 [DutyScan_Calibration_Flow] k_type=1
7324 00:22:15.857761
7325 00:22:15.857882 ==DQS 0 ==
7326 00:22:15.860692 Final DQS duty delay cell = 0
7327 00:22:15.864331 [0] MAX Duty = 5093%(X100), DQS PI = 26
7328 00:22:15.867951 [0] MIN Duty = 4969%(X100), DQS PI = 16
7329 00:22:15.870992 [0] AVG Duty = 5031%(X100)
7330 00:22:15.871232
7331 00:22:15.871400 ==DQS 1 ==
7332 00:22:15.874152 Final DQS duty delay cell = 0
7333 00:22:15.877421 [0] MAX Duty = 5187%(X100), DQS PI = 0
7334 00:22:15.880701 [0] MIN Duty = 4844%(X100), DQS PI = 32
7335 00:22:15.884049 [0] AVG Duty = 5015%(X100)
7336 00:22:15.884194
7337 00:22:15.887388 CH1 DQS 0 Duty spec in!! Max-Min= 124%
7338 00:22:15.887512
7339 00:22:15.891012 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7340 00:22:15.893993 [DutyScan_Calibration_Flow] ====Done====
7341 00:22:15.894102
7342 00:22:15.897377 [DutyScan_Calibration_Flow] k_type=3
7343 00:22:15.915259
7344 00:22:15.915337 ==DQM 0 ==
7345 00:22:15.918632 Final DQM duty delay cell = 4
7346 00:22:15.922183 [4] MAX Duty = 5125%(X100), DQS PI = 22
7347 00:22:15.925136 [4] MIN Duty = 4938%(X100), DQS PI = 46
7348 00:22:15.928547 [4] AVG Duty = 5031%(X100)
7349 00:22:15.928622
7350 00:22:15.928680 ==DQM 1 ==
7351 00:22:15.931836 Final DQM duty delay cell = 0
7352 00:22:15.935392 [0] MAX Duty = 5281%(X100), DQS PI = 58
7353 00:22:15.938133 [0] MIN Duty = 4876%(X100), DQS PI = 34
7354 00:22:15.941538 [0] AVG Duty = 5078%(X100)
7355 00:22:15.941612
7356 00:22:15.945053 CH1 DQM 0 Duty spec in!! Max-Min= 187%
7357 00:22:15.945129
7358 00:22:15.948538 CH1 DQM 1 Duty spec in!! Max-Min= 405%
7359 00:22:15.951800 [DutyScan_Calibration_Flow] ====Done====
7360 00:22:15.951875
7361 00:22:15.954761 [DutyScan_Calibration_Flow] k_type=2
7362 00:22:15.972287
7363 00:22:15.972363 ==DQ 0 ==
7364 00:22:15.975236 Final DQ duty delay cell = 0
7365 00:22:15.978973 [0] MAX Duty = 5062%(X100), DQS PI = 18
7366 00:22:15.982176 [0] MIN Duty = 4969%(X100), DQS PI = 0
7367 00:22:15.982250 [0] AVG Duty = 5015%(X100)
7368 00:22:15.982308
7369 00:22:15.985796 ==DQ 1 ==
7370 00:22:15.985872 Final DQ duty delay cell = 0
7371 00:22:15.988747 [0] MAX Duty = 5062%(X100), DQS PI = 2
7372 00:22:15.995570 [0] MIN Duty = 4813%(X100), DQS PI = 34
7373 00:22:15.995647 [0] AVG Duty = 4937%(X100)
7374 00:22:15.995706
7375 00:22:15.998858 CH1 DQ 0 Duty spec in!! Max-Min= 93%
7376 00:22:15.998934
7377 00:22:16.002307 CH1 DQ 1 Duty spec in!! Max-Min= 249%
7378 00:22:16.005801 [DutyScan_Calibration_Flow] ====Done====
7379 00:22:16.011268 nWR fixed to 30
7380 00:22:16.014217 [ModeRegInit_LP4] CH0 RK0
7381 00:22:16.014353 [ModeRegInit_LP4] CH0 RK1
7382 00:22:16.017699 [ModeRegInit_LP4] CH1 RK0
7383 00:22:16.021137 [ModeRegInit_LP4] CH1 RK1
7384 00:22:16.021275 match AC timing 5
7385 00:22:16.027727 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7386 00:22:16.030797 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7387 00:22:16.034361 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7388 00:22:16.040684 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7389 00:22:16.043977 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7390 00:22:16.044082 [MiockJmeterHQA]
7391 00:22:16.044166
7392 00:22:16.047495 [DramcMiockJmeter] u1RxGatingPI = 0
7393 00:22:16.050711 0 : 4252, 4027
7394 00:22:16.050798 4 : 4252, 4026
7395 00:22:16.054172 8 : 4255, 4029
7396 00:22:16.054255 12 : 4257, 4032
7397 00:22:16.057794 16 : 4363, 4138
7398 00:22:16.057876 20 : 4252, 4026
7399 00:22:16.057939 24 : 4252, 4027
7400 00:22:16.060668 28 : 4252, 4027
7401 00:22:16.060767 32 : 4252, 4027
7402 00:22:16.063903 36 : 4252, 4027
7403 00:22:16.063986 40 : 4363, 4137
7404 00:22:16.067277 44 : 4252, 4027
7405 00:22:16.067355 48 : 4252, 4027
7406 00:22:16.070800 52 : 4255, 4029
7407 00:22:16.070882 56 : 4255, 4029
7408 00:22:16.070946 60 : 4363, 4137
7409 00:22:16.074167 64 : 4252, 4027
7410 00:22:16.074249 68 : 4363, 4140
7411 00:22:16.077219 72 : 4250, 4026
7412 00:22:16.077298 76 : 4250, 4027
7413 00:22:16.080770 80 : 4252, 4030
7414 00:22:16.080850 84 : 4250, 4027
7415 00:22:16.084068 88 : 4252, 3308
7416 00:22:16.084146 92 : 4253, 0
7417 00:22:16.084206 96 : 4252, 0
7418 00:22:16.087577 100 : 4361, 0
7419 00:22:16.087657 104 : 4250, 0
7420 00:22:16.087718 108 : 4250, 0
7421 00:22:16.090533 112 : 4249, 0
7422 00:22:16.090615 116 : 4363, 0
7423 00:22:16.093844 120 : 4250, 0
7424 00:22:16.093960 124 : 4250, 0
7425 00:22:16.094023 128 : 4360, 0
7426 00:22:16.097260 132 : 4250, 0
7427 00:22:16.097340 136 : 4250, 0
7428 00:22:16.100641 140 : 4250, 0
7429 00:22:16.100752 144 : 4255, 0
7430 00:22:16.100816 148 : 4361, 0
7431 00:22:16.103880 152 : 4361, 0
7432 00:22:16.103959 156 : 4250, 0
7433 00:22:16.104021 160 : 4250, 0
7434 00:22:16.107311 164 : 4361, 0
7435 00:22:16.107392 168 : 4250, 0
7436 00:22:16.110795 172 : 4250, 0
7437 00:22:16.110874 176 : 4250, 0
7438 00:22:16.110935 180 : 4360, 0
7439 00:22:16.114190 184 : 4250, 0
7440 00:22:16.114271 188 : 4250, 0
7441 00:22:16.117132 192 : 4250, 0
7442 00:22:16.117277 196 : 4255, 0
7443 00:22:16.117370 200 : 4361, 160
7444 00:22:16.120716 204 : 4250, 3541
7445 00:22:16.120843 208 : 4250, 4027
7446 00:22:16.124281 212 : 4250, 4027
7447 00:22:16.124362 216 : 4250, 4027
7448 00:22:16.127291 220 : 4253, 4029
7449 00:22:16.127373 224 : 4250, 4027
7450 00:22:16.130752 228 : 4361, 4137
7451 00:22:16.130835 232 : 4250, 4026
7452 00:22:16.133845 236 : 4250, 4026
7453 00:22:16.133926 240 : 4250, 4027
7454 00:22:16.137294 244 : 4363, 4140
7455 00:22:16.137375 248 : 4360, 4137
7456 00:22:16.137438 252 : 4250, 4026
7457 00:22:16.140302 256 : 4363, 4140
7458 00:22:16.140379 260 : 4252, 4030
7459 00:22:16.144073 264 : 4249, 4027
7460 00:22:16.144150 268 : 4250, 4027
7461 00:22:16.147373 272 : 4253, 4029
7462 00:22:16.147439 276 : 4250, 4027
7463 00:22:16.150800 280 : 4361, 4137
7464 00:22:16.150879 284 : 4250, 4027
7465 00:22:16.154109 288 : 4253, 4029
7466 00:22:16.154187 292 : 4250, 4027
7467 00:22:16.157550 296 : 4363, 4140
7468 00:22:16.157628 300 : 4363, 4137
7469 00:22:16.157690 304 : 4250, 4026
7470 00:22:16.160806 308 : 4363, 4140
7471 00:22:16.160885 312 : 4250, 3173
7472 00:22:16.163918 316 : 4249, 459
7473 00:22:16.163997
7474 00:22:16.167293 MIOCK jitter meter ch=0
7475 00:22:16.167369
7476 00:22:16.167428 1T = (316-92) = 224 dly cells
7477 00:22:16.173866 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7478 00:22:16.173944 ==
7479 00:22:16.177132 Dram Type= 6, Freq= 0, CH_0, rank 0
7480 00:22:16.180595 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7481 00:22:16.184021 ==
7482 00:22:16.187721 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7483 00:22:16.191050 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7484 00:22:16.197631 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7485 00:22:16.201180 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7486 00:22:16.211253 [CA 0] Center 42 (12~73) winsize 62
7487 00:22:16.214644 [CA 1] Center 42 (12~72) winsize 61
7488 00:22:16.217877 [CA 2] Center 37 (7~67) winsize 61
7489 00:22:16.221497 [CA 3] Center 37 (7~67) winsize 61
7490 00:22:16.224356 [CA 4] Center 36 (6~66) winsize 61
7491 00:22:16.227751 [CA 5] Center 35 (5~65) winsize 61
7492 00:22:16.228144
7493 00:22:16.231335 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7494 00:22:16.231614
7495 00:22:16.234545 [CATrainingPosCal] consider 1 rank data
7496 00:22:16.237349 u2DelayCellTimex100 = 290/100 ps
7497 00:22:16.240941 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7498 00:22:16.247394 CA1 delay=42 (12~72),Diff = 7 PI (23 cell)
7499 00:22:16.250834 CA2 delay=37 (7~67),Diff = 2 PI (6 cell)
7500 00:22:16.254025 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7501 00:22:16.257275 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7502 00:22:16.260695 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7503 00:22:16.260812
7504 00:22:16.264195 CA PerBit enable=1, Macro0, CA PI delay=35
7505 00:22:16.264290
7506 00:22:16.267207 [CBTSetCACLKResult] CA Dly = 35
7507 00:22:16.270783 CS Dly: 9 (0~40)
7508 00:22:16.274250 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7509 00:22:16.277310 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7510 00:22:16.277387 ==
7511 00:22:16.280760 Dram Type= 6, Freq= 0, CH_0, rank 1
7512 00:22:16.283830 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7513 00:22:16.283908 ==
7514 00:22:16.290843 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7515 00:22:16.293902 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7516 00:22:16.300826 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7517 00:22:16.304086 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7518 00:22:16.314175 [CA 0] Center 43 (13~73) winsize 61
7519 00:22:16.317673 [CA 1] Center 43 (13~73) winsize 61
7520 00:22:16.321024 [CA 2] Center 38 (9~67) winsize 59
7521 00:22:16.324316 [CA 3] Center 38 (8~68) winsize 61
7522 00:22:16.327295 [CA 4] Center 37 (7~67) winsize 61
7523 00:22:16.330880 [CA 5] Center 36 (6~66) winsize 61
7524 00:22:16.330957
7525 00:22:16.333996 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7526 00:22:16.334074
7527 00:22:16.337255 [CATrainingPosCal] consider 2 rank data
7528 00:22:16.340852 u2DelayCellTimex100 = 290/100 ps
7529 00:22:16.343906 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7530 00:22:16.350839 CA1 delay=42 (13~72),Diff = 7 PI (23 cell)
7531 00:22:16.354290 CA2 delay=38 (9~67),Diff = 3 PI (10 cell)
7532 00:22:16.357902 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7533 00:22:16.361023 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7534 00:22:16.364046 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7535 00:22:16.364125
7536 00:22:16.367236 CA PerBit enable=1, Macro0, CA PI delay=35
7537 00:22:16.367315
7538 00:22:16.370695 [CBTSetCACLKResult] CA Dly = 35
7539 00:22:16.374302 CS Dly: 10 (0~43)
7540 00:22:16.377134 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7541 00:22:16.380727 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7542 00:22:16.380805
7543 00:22:16.383751 ----->DramcWriteLeveling(PI) begin...
7544 00:22:16.383829 ==
7545 00:22:16.387207 Dram Type= 6, Freq= 0, CH_0, rank 0
7546 00:22:16.393757 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7547 00:22:16.393838 ==
7548 00:22:16.397326 Write leveling (Byte 0): 36 => 36
7549 00:22:16.397417 Write leveling (Byte 1): 31 => 31
7550 00:22:16.400226 DramcWriteLeveling(PI) end<-----
7551 00:22:16.400302
7552 00:22:16.400361 ==
7553 00:22:16.403898 Dram Type= 6, Freq= 0, CH_0, rank 0
7554 00:22:16.410588 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7555 00:22:16.410670 ==
7556 00:22:16.413792 [Gating] SW mode calibration
7557 00:22:16.420455 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7558 00:22:16.423595 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7559 00:22:16.430403 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7560 00:22:16.433439 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7561 00:22:16.437007 1 4 8 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
7562 00:22:16.443349 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7563 00:22:16.447005 1 4 16 | B1->B0 | 2323 3434 | 1 1 | (0 0) (1 1)
7564 00:22:16.450436 1 4 20 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
7565 00:22:16.456711 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7566 00:22:16.460196 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7567 00:22:16.463359 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7568 00:22:16.466706 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7569 00:22:16.473697 1 5 8 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 1)
7570 00:22:16.476695 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7571 00:22:16.480046 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7572 00:22:16.486842 1 5 20 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
7573 00:22:16.489797 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7574 00:22:16.493246 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7575 00:22:16.499846 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7576 00:22:16.503267 1 6 4 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
7577 00:22:16.506865 1 6 8 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
7578 00:22:16.513124 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7579 00:22:16.516329 1 6 16 | B1->B0 | 2525 4646 | 1 0 | (0 0) (0 0)
7580 00:22:16.519645 1 6 20 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
7581 00:22:16.526756 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7582 00:22:16.529975 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7583 00:22:16.532956 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7584 00:22:16.540129 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7585 00:22:16.543376 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7586 00:22:16.546702 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7587 00:22:16.553226 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7588 00:22:16.556345 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7589 00:22:16.559789 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7590 00:22:16.566595 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7591 00:22:16.569782 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7592 00:22:16.573098 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7593 00:22:16.579852 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7594 00:22:16.583176 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7595 00:22:16.586735 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7596 00:22:16.590085 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7597 00:22:16.596842 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7598 00:22:16.599770 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7599 00:22:16.603379 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7600 00:22:16.609978 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7601 00:22:16.612819 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7602 00:22:16.616184 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7603 00:22:16.622809 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7604 00:22:16.626150 Total UI for P1: 0, mck2ui 16
7605 00:22:16.629582 best dqsien dly found for B0: ( 1, 9, 10)
7606 00:22:16.632863 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7607 00:22:16.636280 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7608 00:22:16.639625 Total UI for P1: 0, mck2ui 16
7609 00:22:16.642966 best dqsien dly found for B1: ( 1, 9, 20)
7610 00:22:16.646155 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7611 00:22:16.649394 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7612 00:22:16.649473
7613 00:22:16.656288 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7614 00:22:16.659824 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7615 00:22:16.662775 [Gating] SW calibration Done
7616 00:22:16.662854 ==
7617 00:22:16.666373 Dram Type= 6, Freq= 0, CH_0, rank 0
7618 00:22:16.669318 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7619 00:22:16.669397 ==
7620 00:22:16.669474 RX Vref Scan: 0
7621 00:22:16.672681
7622 00:22:16.672799 RX Vref 0 -> 0, step: 1
7623 00:22:16.672877
7624 00:22:16.676037 RX Delay 0 -> 252, step: 8
7625 00:22:16.679498 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7626 00:22:16.682895 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7627 00:22:16.686386 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7628 00:22:16.692675 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7629 00:22:16.696317 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7630 00:22:16.699625 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7631 00:22:16.702861 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7632 00:22:16.706272 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7633 00:22:16.712651 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7634 00:22:16.716266 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7635 00:22:16.719559 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7636 00:22:16.722840 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
7637 00:22:16.726113 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7638 00:22:16.732927 iDelay=200, Bit 13, Center 127 (80 ~ 175) 96
7639 00:22:16.736322 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7640 00:22:16.739601 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7641 00:22:16.739678 ==
7642 00:22:16.742690 Dram Type= 6, Freq= 0, CH_0, rank 0
7643 00:22:16.746161 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7644 00:22:16.746238 ==
7645 00:22:16.749343 DQS Delay:
7646 00:22:16.749419 DQS0 = 0, DQS1 = 0
7647 00:22:16.752857 DQM Delay:
7648 00:22:16.752933 DQM0 = 137, DQM1 = 126
7649 00:22:16.752991 DQ Delay:
7650 00:22:16.759433 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
7651 00:22:16.762782 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =147
7652 00:22:16.765906 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =123
7653 00:22:16.769324 DQ12 =131, DQ13 =127, DQ14 =139, DQ15 =135
7654 00:22:16.769400
7655 00:22:16.769459
7656 00:22:16.769513 ==
7657 00:22:16.772682 Dram Type= 6, Freq= 0, CH_0, rank 0
7658 00:22:16.776218 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7659 00:22:16.776298 ==
7660 00:22:16.776357
7661 00:22:16.776411
7662 00:22:16.779150 TX Vref Scan disable
7663 00:22:16.782795 == TX Byte 0 ==
7664 00:22:16.786197 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7665 00:22:16.789259 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7666 00:22:16.792698 == TX Byte 1 ==
7667 00:22:16.796246 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7668 00:22:16.799234 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7669 00:22:16.799311 ==
7670 00:22:16.802569 Dram Type= 6, Freq= 0, CH_0, rank 0
7671 00:22:16.806110 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7672 00:22:16.808959 ==
7673 00:22:16.820741
7674 00:22:16.823849 TX Vref early break, caculate TX vref
7675 00:22:16.827562 TX Vref=16, minBit 2, minWin=23, winSum=377
7676 00:22:16.830791 TX Vref=18, minBit 2, minWin=23, winSum=386
7677 00:22:16.834314 TX Vref=20, minBit 12, minWin=23, winSum=400
7678 00:22:16.837257 TX Vref=22, minBit 7, minWin=24, winSum=408
7679 00:22:16.840674 TX Vref=24, minBit 0, minWin=25, winSum=413
7680 00:22:16.847673 TX Vref=26, minBit 12, minWin=25, winSum=424
7681 00:22:16.850729 TX Vref=28, minBit 0, minWin=25, winSum=428
7682 00:22:16.853899 TX Vref=30, minBit 0, minWin=25, winSum=423
7683 00:22:16.857594 TX Vref=32, minBit 0, minWin=25, winSum=414
7684 00:22:16.860964 TX Vref=34, minBit 1, minWin=24, winSum=400
7685 00:22:16.867181 [TxChooseVref] Worse bit 0, Min win 25, Win sum 428, Final Vref 28
7686 00:22:16.867258
7687 00:22:16.870576 Final TX Range 0 Vref 28
7688 00:22:16.870652
7689 00:22:16.870711 ==
7690 00:22:16.873991 Dram Type= 6, Freq= 0, CH_0, rank 0
7691 00:22:16.877132 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7692 00:22:16.877208 ==
7693 00:22:16.877268
7694 00:22:16.877322
7695 00:22:16.880464 TX Vref Scan disable
7696 00:22:16.887395 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7697 00:22:16.887471 == TX Byte 0 ==
7698 00:22:16.890735 u2DelayCellOfst[0]=10 cells (3 PI)
7699 00:22:16.893796 u2DelayCellOfst[1]=16 cells (5 PI)
7700 00:22:16.897287 u2DelayCellOfst[2]=13 cells (4 PI)
7701 00:22:16.900774 u2DelayCellOfst[3]=10 cells (3 PI)
7702 00:22:16.903751 u2DelayCellOfst[4]=6 cells (2 PI)
7703 00:22:16.907180 u2DelayCellOfst[5]=0 cells (0 PI)
7704 00:22:16.910451 u2DelayCellOfst[6]=16 cells (5 PI)
7705 00:22:16.913678 u2DelayCellOfst[7]=13 cells (4 PI)
7706 00:22:16.917328 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7707 00:22:16.920343 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7708 00:22:16.923772 == TX Byte 1 ==
7709 00:22:16.923846 u2DelayCellOfst[8]=0 cells (0 PI)
7710 00:22:16.927197 u2DelayCellOfst[9]=0 cells (0 PI)
7711 00:22:16.930489 u2DelayCellOfst[10]=6 cells (2 PI)
7712 00:22:16.933819 u2DelayCellOfst[11]=3 cells (1 PI)
7713 00:22:16.937121 u2DelayCellOfst[12]=10 cells (3 PI)
7714 00:22:16.940413 u2DelayCellOfst[13]=10 cells (3 PI)
7715 00:22:16.943737 u2DelayCellOfst[14]=13 cells (4 PI)
7716 00:22:16.947156 u2DelayCellOfst[15]=10 cells (3 PI)
7717 00:22:16.950409 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7718 00:22:16.957385 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7719 00:22:16.957464 DramC Write-DBI on
7720 00:22:16.957523 ==
7721 00:22:16.960651 Dram Type= 6, Freq= 0, CH_0, rank 0
7722 00:22:16.963654 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7723 00:22:16.963729 ==
7724 00:22:16.966969
7725 00:22:16.967043
7726 00:22:16.967099 TX Vref Scan disable
7727 00:22:16.970271 == TX Byte 0 ==
7728 00:22:16.973594 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7729 00:22:16.976997 == TX Byte 1 ==
7730 00:22:16.980457 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7731 00:22:16.983407 DramC Write-DBI off
7732 00:22:16.983482
7733 00:22:16.983540 [DATLAT]
7734 00:22:16.983593 Freq=1600, CH0 RK0
7735 00:22:16.983644
7736 00:22:16.986743 DATLAT Default: 0xf
7737 00:22:16.986818 0, 0xFFFF, sum = 0
7738 00:22:16.990196 1, 0xFFFF, sum = 0
7739 00:22:16.990272 2, 0xFFFF, sum = 0
7740 00:22:16.993707 3, 0xFFFF, sum = 0
7741 00:22:16.996984 4, 0xFFFF, sum = 0
7742 00:22:16.997106 5, 0xFFFF, sum = 0
7743 00:22:17.000647 6, 0xFFFF, sum = 0
7744 00:22:17.000760 7, 0xFFFF, sum = 0
7745 00:22:17.003425 8, 0xFFFF, sum = 0
7746 00:22:17.003501 9, 0xFFFF, sum = 0
7747 00:22:17.006912 10, 0xFFFF, sum = 0
7748 00:22:17.006988 11, 0xFFFF, sum = 0
7749 00:22:17.009887 12, 0xFFFF, sum = 0
7750 00:22:17.009962 13, 0xFFFF, sum = 0
7751 00:22:17.013415 14, 0x0, sum = 1
7752 00:22:17.013492 15, 0x0, sum = 2
7753 00:22:17.016615 16, 0x0, sum = 3
7754 00:22:17.016738 17, 0x0, sum = 4
7755 00:22:17.020033 best_step = 15
7756 00:22:17.020108
7757 00:22:17.020171 ==
7758 00:22:17.023110 Dram Type= 6, Freq= 0, CH_0, rank 0
7759 00:22:17.026610 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7760 00:22:17.026689 ==
7761 00:22:17.030041 RX Vref Scan: 1
7762 00:22:17.030148
7763 00:22:17.030236 Set Vref Range= 24 -> 127
7764 00:22:17.030360
7765 00:22:17.033215 RX Vref 24 -> 127, step: 1
7766 00:22:17.033318
7767 00:22:17.036540 RX Delay 19 -> 252, step: 4
7768 00:22:17.036642
7769 00:22:17.039885 Set Vref, RX VrefLevel [Byte0]: 24
7770 00:22:17.043333 [Byte1]: 24
7771 00:22:17.043436
7772 00:22:17.046633 Set Vref, RX VrefLevel [Byte0]: 25
7773 00:22:17.049952 [Byte1]: 25
7774 00:22:17.052959
7775 00:22:17.053058 Set Vref, RX VrefLevel [Byte0]: 26
7776 00:22:17.056284 [Byte1]: 26
7777 00:22:17.060818
7778 00:22:17.060917 Set Vref, RX VrefLevel [Byte0]: 27
7779 00:22:17.063763 [Byte1]: 27
7780 00:22:17.068091
7781 00:22:17.068250 Set Vref, RX VrefLevel [Byte0]: 28
7782 00:22:17.071272 [Byte1]: 28
7783 00:22:17.075755
7784 00:22:17.075853 Set Vref, RX VrefLevel [Byte0]: 29
7785 00:22:17.078945 [Byte1]: 29
7786 00:22:17.083113
7787 00:22:17.083212 Set Vref, RX VrefLevel [Byte0]: 30
7788 00:22:17.086641 [Byte1]: 30
7789 00:22:17.091025
7790 00:22:17.091153 Set Vref, RX VrefLevel [Byte0]: 31
7791 00:22:17.094245 [Byte1]: 31
7792 00:22:17.098495
7793 00:22:17.098595 Set Vref, RX VrefLevel [Byte0]: 32
7794 00:22:17.101891 [Byte1]: 32
7795 00:22:17.106032
7796 00:22:17.106134 Set Vref, RX VrefLevel [Byte0]: 33
7797 00:22:17.109078 [Byte1]: 33
7798 00:22:17.113994
7799 00:22:17.114095 Set Vref, RX VrefLevel [Byte0]: 34
7800 00:22:17.117029 [Byte1]: 34
7801 00:22:17.121075
7802 00:22:17.121175 Set Vref, RX VrefLevel [Byte0]: 35
7803 00:22:17.124263 [Byte1]: 35
7804 00:22:17.128664
7805 00:22:17.128786 Set Vref, RX VrefLevel [Byte0]: 36
7806 00:22:17.131730 [Byte1]: 36
7807 00:22:17.136315
7808 00:22:17.136421 Set Vref, RX VrefLevel [Byte0]: 37
7809 00:22:17.139739 [Byte1]: 37
7810 00:22:17.143518
7811 00:22:17.143634 Set Vref, RX VrefLevel [Byte0]: 38
7812 00:22:17.147100 [Byte1]: 38
7813 00:22:17.151277
7814 00:22:17.151407 Set Vref, RX VrefLevel [Byte0]: 39
7815 00:22:17.154722 [Byte1]: 39
7816 00:22:17.159432
7817 00:22:17.159539 Set Vref, RX VrefLevel [Byte0]: 40
7818 00:22:17.162212 [Byte1]: 40
7819 00:22:17.166718
7820 00:22:17.166820 Set Vref, RX VrefLevel [Byte0]: 41
7821 00:22:17.169639 [Byte1]: 41
7822 00:22:17.173976
7823 00:22:17.174085 Set Vref, RX VrefLevel [Byte0]: 42
7824 00:22:17.177807 [Byte1]: 42
7825 00:22:17.181481
7826 00:22:17.181583 Set Vref, RX VrefLevel [Byte0]: 43
7827 00:22:17.185006 [Byte1]: 43
7828 00:22:17.189490
7829 00:22:17.189591 Set Vref, RX VrefLevel [Byte0]: 44
7830 00:22:17.192516 [Byte1]: 44
7831 00:22:17.196620
7832 00:22:17.196729 Set Vref, RX VrefLevel [Byte0]: 45
7833 00:22:17.199969 [Byte1]: 45
7834 00:22:17.204225
7835 00:22:17.204328 Set Vref, RX VrefLevel [Byte0]: 46
7836 00:22:17.207703 [Byte1]: 46
7837 00:22:17.212268
7838 00:22:17.212366 Set Vref, RX VrefLevel [Byte0]: 47
7839 00:22:17.215230 [Byte1]: 47
7840 00:22:17.219347
7841 00:22:17.219449 Set Vref, RX VrefLevel [Byte0]: 48
7842 00:22:17.222871 [Byte1]: 48
7843 00:22:17.227223
7844 00:22:17.227326 Set Vref, RX VrefLevel [Byte0]: 49
7845 00:22:17.230202 [Byte1]: 49
7846 00:22:17.234509
7847 00:22:17.234614 Set Vref, RX VrefLevel [Byte0]: 50
7848 00:22:17.237752 [Byte1]: 50
7849 00:22:17.242163
7850 00:22:17.242266 Set Vref, RX VrefLevel [Byte0]: 51
7851 00:22:17.245623 [Byte1]: 51
7852 00:22:17.249720
7853 00:22:17.249824 Set Vref, RX VrefLevel [Byte0]: 52
7854 00:22:17.253204 [Byte1]: 52
7855 00:22:17.257614
7856 00:22:17.257714 Set Vref, RX VrefLevel [Byte0]: 53
7857 00:22:17.260639 [Byte1]: 53
7858 00:22:17.264863
7859 00:22:17.264967 Set Vref, RX VrefLevel [Byte0]: 54
7860 00:22:17.268135 [Byte1]: 54
7861 00:22:17.272653
7862 00:22:17.272763 Set Vref, RX VrefLevel [Byte0]: 55
7863 00:22:17.275816 [Byte1]: 55
7864 00:22:17.280072
7865 00:22:17.280175 Set Vref, RX VrefLevel [Byte0]: 56
7866 00:22:17.283342 [Byte1]: 56
7867 00:22:17.287713
7868 00:22:17.287817 Set Vref, RX VrefLevel [Byte0]: 57
7869 00:22:17.291235 [Byte1]: 57
7870 00:22:17.295126
7871 00:22:17.295228 Set Vref, RX VrefLevel [Byte0]: 58
7872 00:22:17.298672 [Byte1]: 58
7873 00:22:17.302632
7874 00:22:17.302733 Set Vref, RX VrefLevel [Byte0]: 59
7875 00:22:17.306100 [Byte1]: 59
7876 00:22:17.310184
7877 00:22:17.310283 Set Vref, RX VrefLevel [Byte0]: 60
7878 00:22:17.313732 [Byte1]: 60
7879 00:22:17.318188
7880 00:22:17.318287 Set Vref, RX VrefLevel [Byte0]: 61
7881 00:22:17.321201 [Byte1]: 61
7882 00:22:17.325684
7883 00:22:17.325789 Set Vref, RX VrefLevel [Byte0]: 62
7884 00:22:17.328675 [Byte1]: 62
7885 00:22:17.333049
7886 00:22:17.333149 Set Vref, RX VrefLevel [Byte0]: 63
7887 00:22:17.336103 [Byte1]: 63
7888 00:22:17.340551
7889 00:22:17.340646 Set Vref, RX VrefLevel [Byte0]: 64
7890 00:22:17.343788 [Byte1]: 64
7891 00:22:17.348119
7892 00:22:17.348222 Set Vref, RX VrefLevel [Byte0]: 65
7893 00:22:17.351367 [Byte1]: 65
7894 00:22:17.355939
7895 00:22:17.356040 Set Vref, RX VrefLevel [Byte0]: 66
7896 00:22:17.359132 [Byte1]: 66
7897 00:22:17.363234
7898 00:22:17.363334 Set Vref, RX VrefLevel [Byte0]: 67
7899 00:22:17.366624 [Byte1]: 67
7900 00:22:17.371177
7901 00:22:17.371278 Set Vref, RX VrefLevel [Byte0]: 68
7902 00:22:17.374051 [Byte1]: 68
7903 00:22:17.378535
7904 00:22:17.378636 Set Vref, RX VrefLevel [Byte0]: 69
7905 00:22:17.381873 [Byte1]: 69
7906 00:22:17.386369
7907 00:22:17.386469 Set Vref, RX VrefLevel [Byte0]: 70
7908 00:22:17.389261 [Byte1]: 70
7909 00:22:17.393683
7910 00:22:17.393783 Set Vref, RX VrefLevel [Byte0]: 71
7911 00:22:17.396973 [Byte1]: 71
7912 00:22:17.401390
7913 00:22:17.401490 Set Vref, RX VrefLevel [Byte0]: 72
7914 00:22:17.404995 [Byte1]: 72
7915 00:22:17.408684
7916 00:22:17.408791 Set Vref, RX VrefLevel [Byte0]: 73
7917 00:22:17.411865 [Byte1]: 73
7918 00:22:17.416338
7919 00:22:17.416445 Set Vref, RX VrefLevel [Byte0]: 74
7920 00:22:17.419712 [Byte1]: 74
7921 00:22:17.424140
7922 00:22:17.424241 Set Vref, RX VrefLevel [Byte0]: 75
7923 00:22:17.427575 [Byte1]: 75
7924 00:22:17.431671
7925 00:22:17.431772 Set Vref, RX VrefLevel [Byte0]: 76
7926 00:22:17.434917 [Byte1]: 76
7927 00:22:17.439337
7928 00:22:17.439442 Set Vref, RX VrefLevel [Byte0]: 77
7929 00:22:17.442375 [Byte1]: 77
7930 00:22:17.446539
7931 00:22:17.446642 Set Vref, RX VrefLevel [Byte0]: 78
7932 00:22:17.450036 [Byte1]: 78
7933 00:22:17.454469
7934 00:22:17.454567 Set Vref, RX VrefLevel [Byte0]: 79
7935 00:22:17.457340 [Byte1]: 79
7936 00:22:17.461901
7937 00:22:17.462001 Set Vref, RX VrefLevel [Byte0]: 80
7938 00:22:17.468181 [Byte1]: 80
7939 00:22:17.468295
7940 00:22:17.471702 Final RX Vref Byte 0 = 61 to rank0
7941 00:22:17.475223 Final RX Vref Byte 1 = 59 to rank0
7942 00:22:17.478047 Final RX Vref Byte 0 = 61 to rank1
7943 00:22:17.481634 Final RX Vref Byte 1 = 59 to rank1==
7944 00:22:17.484998 Dram Type= 6, Freq= 0, CH_0, rank 0
7945 00:22:17.488448 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7946 00:22:17.488552 ==
7947 00:22:17.488665 DQS Delay:
7948 00:22:17.491825 DQS0 = 0, DQS1 = 0
7949 00:22:17.491927 DQM Delay:
7950 00:22:17.494877 DQM0 = 136, DQM1 = 123
7951 00:22:17.494976 DQ Delay:
7952 00:22:17.498280 DQ0 =136, DQ1 =136, DQ2 =132, DQ3 =134
7953 00:22:17.501454 DQ4 =140, DQ5 =126, DQ6 =144, DQ7 =144
7954 00:22:17.504794 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =118
7955 00:22:17.508229 DQ12 =128, DQ13 =126, DQ14 =136, DQ15 =132
7956 00:22:17.508326
7957 00:22:17.508409
7958 00:22:17.511270
7959 00:22:17.511367 [DramC_TX_OE_Calibration] TA2
7960 00:22:17.514775 Original DQ_B0 (3 6) =30, OEN = 27
7961 00:22:17.518056 Original DQ_B1 (3 6) =30, OEN = 27
7962 00:22:17.521556 24, 0x0, End_B0=24 End_B1=24
7963 00:22:17.524519 25, 0x0, End_B0=25 End_B1=25
7964 00:22:17.527884 26, 0x0, End_B0=26 End_B1=26
7965 00:22:17.527984 27, 0x0, End_B0=27 End_B1=27
7966 00:22:17.531325 28, 0x0, End_B0=28 End_B1=28
7967 00:22:17.534779 29, 0x0, End_B0=29 End_B1=29
7968 00:22:17.537889 30, 0x0, End_B0=30 End_B1=30
7969 00:22:17.541288 31, 0x4141, End_B0=30 End_B1=30
7970 00:22:17.541389 Byte0 end_step=30 best_step=27
7971 00:22:17.544676 Byte1 end_step=30 best_step=27
7972 00:22:17.547614 Byte0 TX OE(2T, 0.5T) = (3, 3)
7973 00:22:17.550931 Byte1 TX OE(2T, 0.5T) = (3, 3)
7974 00:22:17.551029
7975 00:22:17.551112
7976 00:22:17.557745 [DQSOSCAuto] RK0, (LSB)MR18= 0x201e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
7977 00:22:17.561323 CH0 RK0: MR19=303, MR18=201E
7978 00:22:17.567625 CH0_RK0: MR19=0x303, MR18=0x201E, DQSOSC=393, MR23=63, INC=23, DEC=15
7979 00:22:17.567726
7980 00:22:17.571264 ----->DramcWriteLeveling(PI) begin...
7981 00:22:17.571363 ==
7982 00:22:17.574472 Dram Type= 6, Freq= 0, CH_0, rank 1
7983 00:22:17.577674 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7984 00:22:17.581046 ==
7985 00:22:17.581137 Write leveling (Byte 0): 37 => 37
7986 00:22:17.584312 Write leveling (Byte 1): 29 => 29
7987 00:22:17.587751 DramcWriteLeveling(PI) end<-----
7988 00:22:17.587847
7989 00:22:17.587929 ==
7990 00:22:17.591124 Dram Type= 6, Freq= 0, CH_0, rank 1
7991 00:22:17.597912 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7992 00:22:17.598005 ==
7993 00:22:17.598084 [Gating] SW mode calibration
7994 00:22:17.607480 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7995 00:22:17.611383 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7996 00:22:17.614268 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7997 00:22:17.621055 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7998 00:22:17.624538 1 4 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7999 00:22:17.627530 1 4 12 | B1->B0 | 2a29 3232 | 1 1 | (0 0) (0 0)
8000 00:22:17.634451 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8001 00:22:17.637832 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8002 00:22:17.641262 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8003 00:22:17.647724 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8004 00:22:17.651222 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8005 00:22:17.654465 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8006 00:22:17.660957 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8007 00:22:17.664274 1 5 12 | B1->B0 | 3434 2828 | 0 0 | (0 1) (0 0)
8008 00:22:17.667758 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8009 00:22:17.674136 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8010 00:22:17.677537 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8011 00:22:17.680920 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8012 00:22:17.687860 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8013 00:22:17.690768 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8014 00:22:17.694384 1 6 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
8015 00:22:17.700885 1 6 12 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
8016 00:22:17.704154 1 6 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8017 00:22:17.707702 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8018 00:22:17.714071 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8019 00:22:17.717763 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8020 00:22:17.721123 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8021 00:22:17.724078 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8022 00:22:17.730817 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8023 00:22:17.734268 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8024 00:22:17.737775 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8025 00:22:17.744118 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8026 00:22:17.747727 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8027 00:22:17.751110 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8028 00:22:17.757471 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8029 00:22:17.760723 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8030 00:22:17.764412 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8031 00:22:17.770809 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8032 00:22:17.774162 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8033 00:22:17.777234 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8034 00:22:17.784069 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8035 00:22:17.787312 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8036 00:22:17.790829 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8037 00:22:17.797771 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8038 00:22:17.800675 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8039 00:22:17.803989 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8040 00:22:17.810566 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8041 00:22:17.810642 Total UI for P1: 0, mck2ui 16
8042 00:22:17.817460 best dqsien dly found for B0: ( 1, 9, 10)
8043 00:22:17.817536 Total UI for P1: 0, mck2ui 16
8044 00:22:17.820866 best dqsien dly found for B1: ( 1, 9, 12)
8045 00:22:17.827204 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8046 00:22:17.830699 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8047 00:22:17.830776
8048 00:22:17.834203 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8049 00:22:17.837695 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8050 00:22:17.840665 [Gating] SW calibration Done
8051 00:22:17.840777 ==
8052 00:22:17.843993 Dram Type= 6, Freq= 0, CH_0, rank 1
8053 00:22:17.847363 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8054 00:22:17.847440 ==
8055 00:22:17.850796 RX Vref Scan: 0
8056 00:22:17.850871
8057 00:22:17.850930 RX Vref 0 -> 0, step: 1
8058 00:22:17.850984
8059 00:22:17.854192 RX Delay 0 -> 252, step: 8
8060 00:22:17.857183 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8061 00:22:17.860578 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8062 00:22:17.867303 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8063 00:22:17.870287 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8064 00:22:17.873702 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8065 00:22:17.877197 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8066 00:22:17.880733 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8067 00:22:17.887231 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8068 00:22:17.890780 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8069 00:22:17.893820 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8070 00:22:17.897288 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8071 00:22:17.900435 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8072 00:22:17.907248 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8073 00:22:17.910630 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8074 00:22:17.913637 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8075 00:22:17.917039 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8076 00:22:17.917115 ==
8077 00:22:17.920749 Dram Type= 6, Freq= 0, CH_0, rank 1
8078 00:22:17.927381 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8079 00:22:17.927456 ==
8080 00:22:17.927551 DQS Delay:
8081 00:22:17.930505 DQS0 = 0, DQS1 = 0
8082 00:22:17.930579 DQM Delay:
8083 00:22:17.930637 DQM0 = 135, DQM1 = 125
8084 00:22:17.933796 DQ Delay:
8085 00:22:17.937103 DQ0 =135, DQ1 =135, DQ2 =135, DQ3 =131
8086 00:22:17.940378 DQ4 =135, DQ5 =127, DQ6 =143, DQ7 =143
8087 00:22:17.943881 DQ8 =119, DQ9 =111, DQ10 =123, DQ11 =123
8088 00:22:17.947052 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =135
8089 00:22:17.947126
8090 00:22:17.947183
8091 00:22:17.947234 ==
8092 00:22:17.950728 Dram Type= 6, Freq= 0, CH_0, rank 1
8093 00:22:17.953862 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8094 00:22:17.957325 ==
8095 00:22:17.957399
8096 00:22:17.957456
8097 00:22:17.957509 TX Vref Scan disable
8098 00:22:17.960934 == TX Byte 0 ==
8099 00:22:17.963648 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8100 00:22:17.967515 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8101 00:22:17.970351 == TX Byte 1 ==
8102 00:22:17.973749 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8103 00:22:17.977305 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8104 00:22:17.980721 ==
8105 00:22:17.980818 Dram Type= 6, Freq= 0, CH_0, rank 1
8106 00:22:17.987098 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8107 00:22:17.987173 ==
8108 00:22:18.001534
8109 00:22:18.004441 TX Vref early break, caculate TX vref
8110 00:22:18.007725 TX Vref=16, minBit 0, minWin=23, winSum=385
8111 00:22:18.010941 TX Vref=18, minBit 2, minWin=24, winSum=400
8112 00:22:18.014384 TX Vref=20, minBit 7, minWin=24, winSum=406
8113 00:22:18.017698 TX Vref=22, minBit 0, minWin=25, winSum=412
8114 00:22:18.021061 TX Vref=24, minBit 0, minWin=25, winSum=420
8115 00:22:18.027581 TX Vref=26, minBit 0, minWin=26, winSum=429
8116 00:22:18.031301 TX Vref=28, minBit 0, minWin=26, winSum=427
8117 00:22:18.034385 TX Vref=30, minBit 0, minWin=25, winSum=426
8118 00:22:18.037548 TX Vref=32, minBit 0, minWin=25, winSum=418
8119 00:22:18.041199 TX Vref=34, minBit 0, minWin=24, winSum=409
8120 00:22:18.044179 TX Vref=36, minBit 0, minWin=24, winSum=398
8121 00:22:18.051201 [TxChooseVref] Worse bit 0, Min win 26, Win sum 429, Final Vref 26
8122 00:22:18.051277
8123 00:22:18.054319 Final TX Range 0 Vref 26
8124 00:22:18.054394
8125 00:22:18.054451 ==
8126 00:22:18.057656 Dram Type= 6, Freq= 0, CH_0, rank 1
8127 00:22:18.060915 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8128 00:22:18.060991 ==
8129 00:22:18.061048
8130 00:22:18.061100
8131 00:22:18.064426 TX Vref Scan disable
8132 00:22:18.070976 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8133 00:22:18.071051 == TX Byte 0 ==
8134 00:22:18.073989 u2DelayCellOfst[0]=13 cells (4 PI)
8135 00:22:18.077319 u2DelayCellOfst[1]=20 cells (6 PI)
8136 00:22:18.080844 u2DelayCellOfst[2]=13 cells (4 PI)
8137 00:22:18.084391 u2DelayCellOfst[3]=13 cells (4 PI)
8138 00:22:18.087298 u2DelayCellOfst[4]=10 cells (3 PI)
8139 00:22:18.090793 u2DelayCellOfst[5]=0 cells (0 PI)
8140 00:22:18.094288 u2DelayCellOfst[6]=20 cells (6 PI)
8141 00:22:18.097297 u2DelayCellOfst[7]=20 cells (6 PI)
8142 00:22:18.100737 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8143 00:22:18.104168 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8144 00:22:18.107133 == TX Byte 1 ==
8145 00:22:18.110498 u2DelayCellOfst[8]=0 cells (0 PI)
8146 00:22:18.113868 u2DelayCellOfst[9]=0 cells (0 PI)
8147 00:22:18.117207 u2DelayCellOfst[10]=6 cells (2 PI)
8148 00:22:18.117281 u2DelayCellOfst[11]=3 cells (1 PI)
8149 00:22:18.120756 u2DelayCellOfst[12]=13 cells (4 PI)
8150 00:22:18.123733 u2DelayCellOfst[13]=13 cells (4 PI)
8151 00:22:18.127010 u2DelayCellOfst[14]=13 cells (4 PI)
8152 00:22:18.130564 u2DelayCellOfst[15]=10 cells (3 PI)
8153 00:22:18.137261 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8154 00:22:18.140546 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8155 00:22:18.140621 DramC Write-DBI on
8156 00:22:18.140679 ==
8157 00:22:18.143639 Dram Type= 6, Freq= 0, CH_0, rank 1
8158 00:22:18.150238 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8159 00:22:18.150396 ==
8160 00:22:18.150520
8161 00:22:18.150597
8162 00:22:18.150673 TX Vref Scan disable
8163 00:22:18.154665 == TX Byte 0 ==
8164 00:22:18.158289 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8165 00:22:18.161138 == TX Byte 1 ==
8166 00:22:18.164922 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8167 00:22:18.167801 DramC Write-DBI off
8168 00:22:18.167887
8169 00:22:18.167963 [DATLAT]
8170 00:22:18.168035 Freq=1600, CH0 RK1
8171 00:22:18.168105
8172 00:22:18.171270 DATLAT Default: 0xf
8173 00:22:18.171358 0, 0xFFFF, sum = 0
8174 00:22:18.174615 1, 0xFFFF, sum = 0
8175 00:22:18.177951 2, 0xFFFF, sum = 0
8176 00:22:18.178044 3, 0xFFFF, sum = 0
8177 00:22:18.180905 4, 0xFFFF, sum = 0
8178 00:22:18.180999 5, 0xFFFF, sum = 0
8179 00:22:18.184265 6, 0xFFFF, sum = 0
8180 00:22:18.184358 7, 0xFFFF, sum = 0
8181 00:22:18.187773 8, 0xFFFF, sum = 0
8182 00:22:18.187866 9, 0xFFFF, sum = 0
8183 00:22:18.191223 10, 0xFFFF, sum = 0
8184 00:22:18.191317 11, 0xFFFF, sum = 0
8185 00:22:18.194662 12, 0xFFFF, sum = 0
8186 00:22:18.194755 13, 0xFFFF, sum = 0
8187 00:22:18.197794 14, 0x0, sum = 1
8188 00:22:18.197886 15, 0x0, sum = 2
8189 00:22:18.201189 16, 0x0, sum = 3
8190 00:22:18.201282 17, 0x0, sum = 4
8191 00:22:18.204796 best_step = 15
8192 00:22:18.204888
8193 00:22:18.204965 ==
8194 00:22:18.207871 Dram Type= 6, Freq= 0, CH_0, rank 1
8195 00:22:18.211193 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8196 00:22:18.211283 ==
8197 00:22:18.211360 RX Vref Scan: 0
8198 00:22:18.214667
8199 00:22:18.214755 RX Vref 0 -> 0, step: 1
8200 00:22:18.214829
8201 00:22:18.217884 RX Delay 11 -> 252, step: 4
8202 00:22:18.221410 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8203 00:22:18.228260 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8204 00:22:18.231560 iDelay=191, Bit 2, Center 128 (79 ~ 178) 100
8205 00:22:18.234928 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8206 00:22:18.237801 iDelay=191, Bit 4, Center 132 (83 ~ 182) 100
8207 00:22:18.241440 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8208 00:22:18.244383 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8209 00:22:18.251268 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8210 00:22:18.254381 iDelay=191, Bit 8, Center 114 (63 ~ 166) 104
8211 00:22:18.257942 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8212 00:22:18.261054 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8213 00:22:18.267542 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8214 00:22:18.271040 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8215 00:22:18.274471 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8216 00:22:18.277723 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8217 00:22:18.281069 iDelay=191, Bit 15, Center 128 (75 ~ 182) 108
8218 00:22:18.284223 ==
8219 00:22:18.284313 Dram Type= 6, Freq= 0, CH_0, rank 1
8220 00:22:18.291314 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8221 00:22:18.291411 ==
8222 00:22:18.291491 DQS Delay:
8223 00:22:18.294034 DQS0 = 0, DQS1 = 0
8224 00:22:18.294124 DQM Delay:
8225 00:22:18.297612 DQM0 = 132, DQM1 = 123
8226 00:22:18.297705 DQ Delay:
8227 00:22:18.300989 DQ0 =132, DQ1 =136, DQ2 =128, DQ3 =130
8228 00:22:18.304458 DQ4 =132, DQ5 =124, DQ6 =140, DQ7 =138
8229 00:22:18.307841 DQ8 =114, DQ9 =112, DQ10 =124, DQ11 =118
8230 00:22:18.310892 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =128
8231 00:22:18.310985
8232 00:22:18.311063
8233 00:22:18.311137
8234 00:22:18.314344 [DramC_TX_OE_Calibration] TA2
8235 00:22:18.317807 Original DQ_B0 (3 6) =30, OEN = 27
8236 00:22:18.321235 Original DQ_B1 (3 6) =30, OEN = 27
8237 00:22:18.324167 24, 0x0, End_B0=24 End_B1=24
8238 00:22:18.327647 25, 0x0, End_B0=25 End_B1=25
8239 00:22:18.327745 26, 0x0, End_B0=26 End_B1=26
8240 00:22:18.330712 27, 0x0, End_B0=27 End_B1=27
8241 00:22:18.334181 28, 0x0, End_B0=28 End_B1=28
8242 00:22:18.337745 29, 0x0, End_B0=29 End_B1=29
8243 00:22:18.337841 30, 0x0, End_B0=30 End_B1=30
8244 00:22:18.340943 31, 0x4141, End_B0=30 End_B1=30
8245 00:22:18.344213 Byte0 end_step=30 best_step=27
8246 00:22:18.347734 Byte1 end_step=30 best_step=27
8247 00:22:18.350700 Byte0 TX OE(2T, 0.5T) = (3, 3)
8248 00:22:18.354193 Byte1 TX OE(2T, 0.5T) = (3, 3)
8249 00:22:18.354283
8250 00:22:18.354359
8251 00:22:18.360767 [DQSOSCAuto] RK1, (LSB)MR18= 0x2411, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 391 ps
8252 00:22:18.364274 CH0 RK1: MR19=303, MR18=2411
8253 00:22:18.370721 CH0_RK1: MR19=0x303, MR18=0x2411, DQSOSC=391, MR23=63, INC=24, DEC=16
8254 00:22:18.373978 [RxdqsGatingPostProcess] freq 1600
8255 00:22:18.377747 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8256 00:22:18.380808 best DQS0 dly(2T, 0.5T) = (1, 1)
8257 00:22:18.384221 best DQS1 dly(2T, 0.5T) = (1, 1)
8258 00:22:18.387717 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8259 00:22:18.390917 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8260 00:22:18.394352 best DQS0 dly(2T, 0.5T) = (1, 1)
8261 00:22:18.397437 best DQS1 dly(2T, 0.5T) = (1, 1)
8262 00:22:18.400781 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8263 00:22:18.404264 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8264 00:22:18.407749 Pre-setting of DQS Precalculation
8265 00:22:18.410774 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8266 00:22:18.410864 ==
8267 00:22:18.414245 Dram Type= 6, Freq= 0, CH_1, rank 0
8268 00:22:18.417248 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8269 00:22:18.420718 ==
8270 00:22:18.424120 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8271 00:22:18.427561 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8272 00:22:18.433970 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8273 00:22:18.440341 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8274 00:22:18.447637 [CA 0] Center 40 (11~70) winsize 60
8275 00:22:18.451045 [CA 1] Center 41 (11~71) winsize 61
8276 00:22:18.454582 [CA 2] Center 37 (8~67) winsize 60
8277 00:22:18.457920 [CA 3] Center 36 (6~66) winsize 61
8278 00:22:18.460856 [CA 4] Center 36 (6~66) winsize 61
8279 00:22:18.464293 [CA 5] Center 36 (6~66) winsize 61
8280 00:22:18.464385
8281 00:22:18.467736 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8282 00:22:18.467830
8283 00:22:18.471169 [CATrainingPosCal] consider 1 rank data
8284 00:22:18.474373 u2DelayCellTimex100 = 290/100 ps
8285 00:22:18.477570 CA0 delay=40 (11~70),Diff = 4 PI (13 cell)
8286 00:22:18.484198 CA1 delay=41 (11~71),Diff = 5 PI (16 cell)
8287 00:22:18.487579 CA2 delay=37 (8~67),Diff = 1 PI (3 cell)
8288 00:22:18.490831 CA3 delay=36 (6~66),Diff = 0 PI (0 cell)
8289 00:22:18.494288 CA4 delay=36 (6~66),Diff = 0 PI (0 cell)
8290 00:22:18.497668 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
8291 00:22:18.497759
8292 00:22:18.501302 CA PerBit enable=1, Macro0, CA PI delay=36
8293 00:22:18.501390
8294 00:22:18.504348 [CBTSetCACLKResult] CA Dly = 36
8295 00:22:18.507777 CS Dly: 8 (0~39)
8296 00:22:18.511431 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8297 00:22:18.514582 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8298 00:22:18.514674 ==
8299 00:22:18.517841 Dram Type= 6, Freq= 0, CH_1, rank 1
8300 00:22:18.520806 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8301 00:22:18.520898 ==
8302 00:22:18.527638 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8303 00:22:18.531084 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8304 00:22:18.537337 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8305 00:22:18.540831 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8306 00:22:18.551081 [CA 0] Center 42 (13~71) winsize 59
8307 00:22:18.554374 [CA 1] Center 41 (12~71) winsize 60
8308 00:22:18.557808 [CA 2] Center 37 (8~67) winsize 60
8309 00:22:18.560708 [CA 3] Center 37 (8~67) winsize 60
8310 00:22:18.564296 [CA 4] Center 37 (8~67) winsize 60
8311 00:22:18.567300 [CA 5] Center 37 (7~67) winsize 61
8312 00:22:18.567394
8313 00:22:18.570570 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8314 00:22:18.570663
8315 00:22:18.573832 [CATrainingPosCal] consider 2 rank data
8316 00:22:18.577263 u2DelayCellTimex100 = 290/100 ps
8317 00:22:18.580665 CA0 delay=41 (13~70),Diff = 5 PI (16 cell)
8318 00:22:18.587583 CA1 delay=41 (12~71),Diff = 5 PI (16 cell)
8319 00:22:18.590824 CA2 delay=37 (8~67),Diff = 1 PI (3 cell)
8320 00:22:18.593897 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8321 00:22:18.597209 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8322 00:22:18.600657 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8323 00:22:18.600749
8324 00:22:18.604194 CA PerBit enable=1, Macro0, CA PI delay=36
8325 00:22:18.604285
8326 00:22:18.607089 [CBTSetCACLKResult] CA Dly = 36
8327 00:22:18.610462 CS Dly: 9 (0~42)
8328 00:22:18.613985 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8329 00:22:18.617138 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8330 00:22:18.617230
8331 00:22:18.620861 ----->DramcWriteLeveling(PI) begin...
8332 00:22:18.620967 ==
8333 00:22:18.623819 Dram Type= 6, Freq= 0, CH_1, rank 0
8334 00:22:18.627343 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8335 00:22:18.627440 ==
8336 00:22:18.630688 Write leveling (Byte 0): 25 => 25
8337 00:22:18.634010 Write leveling (Byte 1): 27 => 27
8338 00:22:18.637400 DramcWriteLeveling(PI) end<-----
8339 00:22:18.637496
8340 00:22:18.637575 ==
8341 00:22:18.640864 Dram Type= 6, Freq= 0, CH_1, rank 0
8342 00:22:18.647229 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8343 00:22:18.647325 ==
8344 00:22:18.647408 [Gating] SW mode calibration
8345 00:22:18.657403 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8346 00:22:18.660675 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8347 00:22:18.663775 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8348 00:22:18.670692 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8349 00:22:18.673984 1 4 8 | B1->B0 | 2626 3333 | 1 1 | (0 0) (1 1)
8350 00:22:18.677331 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8351 00:22:18.683793 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8352 00:22:18.687182 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8353 00:22:18.690680 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8354 00:22:18.697226 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8355 00:22:18.700377 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8356 00:22:18.703749 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8357 00:22:18.710763 1 5 8 | B1->B0 | 3131 2929 | 1 0 | (1 1) (1 0)
8358 00:22:18.713884 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8359 00:22:18.717325 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8360 00:22:18.723882 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8361 00:22:18.727109 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8362 00:22:18.730320 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8363 00:22:18.737093 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8364 00:22:18.740216 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8365 00:22:18.743813 1 6 8 | B1->B0 | 3333 4545 | 0 0 | (0 0) (0 0)
8366 00:22:18.750098 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8367 00:22:18.753624 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8368 00:22:18.756679 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8369 00:22:18.763408 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8370 00:22:18.766876 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8371 00:22:18.770354 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8372 00:22:18.776666 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8373 00:22:18.780073 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8374 00:22:18.783627 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8375 00:22:18.789631 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8376 00:22:18.793193 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8377 00:22:18.796614 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8378 00:22:18.803018 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8379 00:22:18.806546 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8380 00:22:18.809984 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8381 00:22:18.816679 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8382 00:22:18.819719 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8383 00:22:18.822787 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8384 00:22:18.829629 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8385 00:22:18.832824 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8386 00:22:18.836293 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8387 00:22:18.839745 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8388 00:22:18.846162 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8389 00:22:18.849554 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8390 00:22:18.852947 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8391 00:22:18.856234 Total UI for P1: 0, mck2ui 16
8392 00:22:18.859622 best dqsien dly found for B0: ( 1, 9, 6)
8393 00:22:18.866006 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8394 00:22:18.869420 Total UI for P1: 0, mck2ui 16
8395 00:22:18.872849 best dqsien dly found for B1: ( 1, 9, 10)
8396 00:22:18.876264 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8397 00:22:18.879345 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8398 00:22:18.879437
8399 00:22:18.882663 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8400 00:22:18.886010 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8401 00:22:18.889458 [Gating] SW calibration Done
8402 00:22:18.889548 ==
8403 00:22:18.892780 Dram Type= 6, Freq= 0, CH_1, rank 0
8404 00:22:18.895803 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8405 00:22:18.895894 ==
8406 00:22:18.899300 RX Vref Scan: 0
8407 00:22:18.899390
8408 00:22:18.902269 RX Vref 0 -> 0, step: 1
8409 00:22:18.902358
8410 00:22:18.902435 RX Delay 0 -> 252, step: 8
8411 00:22:18.909174 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8412 00:22:18.912189 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8413 00:22:18.915613 iDelay=200, Bit 2, Center 127 (80 ~ 175) 96
8414 00:22:18.919372 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8415 00:22:18.922458 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8416 00:22:18.925801 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8417 00:22:18.932627 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8418 00:22:18.935620 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8419 00:22:18.939069 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8420 00:22:18.942417 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8421 00:22:18.945607 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8422 00:22:18.952637 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8423 00:22:18.955621 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8424 00:22:18.959110 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8425 00:22:18.962403 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8426 00:22:18.966073 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8427 00:22:18.969059 ==
8428 00:22:18.969149 Dram Type= 6, Freq= 0, CH_1, rank 0
8429 00:22:18.975894 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8430 00:22:18.975997 ==
8431 00:22:18.976088 DQS Delay:
8432 00:22:18.978885 DQS0 = 0, DQS1 = 0
8433 00:22:18.978980 DQM Delay:
8434 00:22:18.982568 DQM0 = 138, DQM1 = 130
8435 00:22:18.982668 DQ Delay:
8436 00:22:18.985827 DQ0 =139, DQ1 =135, DQ2 =127, DQ3 =139
8437 00:22:18.989205 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8438 00:22:18.992205 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =127
8439 00:22:18.995709 DQ12 =139, DQ13 =135, DQ14 =135, DQ15 =135
8440 00:22:18.995796
8441 00:22:18.995870
8442 00:22:18.995941 ==
8443 00:22:18.999184 Dram Type= 6, Freq= 0, CH_1, rank 0
8444 00:22:19.005696 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8445 00:22:19.005787 ==
8446 00:22:19.005861
8447 00:22:19.005932
8448 00:22:19.006000 TX Vref Scan disable
8449 00:22:19.009104 == TX Byte 0 ==
8450 00:22:19.012166 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8451 00:22:19.019003 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8452 00:22:19.019098 == TX Byte 1 ==
8453 00:22:19.022255 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8454 00:22:19.028651 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8455 00:22:19.028798 ==
8456 00:22:19.032163 Dram Type= 6, Freq= 0, CH_1, rank 0
8457 00:22:19.035372 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8458 00:22:19.035465 ==
8459 00:22:19.047653
8460 00:22:19.050894 TX Vref early break, caculate TX vref
8461 00:22:19.054148 TX Vref=16, minBit 9, minWin=22, winSum=378
8462 00:22:19.057386 TX Vref=18, minBit 15, minWin=23, winSum=390
8463 00:22:19.060725 TX Vref=20, minBit 1, minWin=24, winSum=394
8464 00:22:19.064234 TX Vref=22, minBit 0, minWin=24, winSum=405
8465 00:22:19.067699 TX Vref=24, minBit 15, minWin=24, winSum=415
8466 00:22:19.074081 TX Vref=26, minBit 11, minWin=25, winSum=428
8467 00:22:19.077287 TX Vref=28, minBit 0, minWin=26, winSum=429
8468 00:22:19.081032 TX Vref=30, minBit 10, minWin=25, winSum=427
8469 00:22:19.083904 TX Vref=32, minBit 0, minWin=25, winSum=412
8470 00:22:19.087614 TX Vref=34, minBit 5, minWin=24, winSum=406
8471 00:22:19.093965 [TxChooseVref] Worse bit 0, Min win 26, Win sum 429, Final Vref 28
8472 00:22:19.094057
8473 00:22:19.097445 Final TX Range 0 Vref 28
8474 00:22:19.097605
8475 00:22:19.097693 ==
8476 00:22:19.100851 Dram Type= 6, Freq= 0, CH_1, rank 0
8477 00:22:19.103806 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8478 00:22:19.103894 ==
8479 00:22:19.103968
8480 00:22:19.104037
8481 00:22:19.107225 TX Vref Scan disable
8482 00:22:19.113691 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8483 00:22:19.113787 == TX Byte 0 ==
8484 00:22:19.117170 u2DelayCellOfst[0]=16 cells (5 PI)
8485 00:22:19.120261 u2DelayCellOfst[1]=10 cells (3 PI)
8486 00:22:19.123710 u2DelayCellOfst[2]=0 cells (0 PI)
8487 00:22:19.126973 u2DelayCellOfst[3]=6 cells (2 PI)
8488 00:22:19.130295 u2DelayCellOfst[4]=6 cells (2 PI)
8489 00:22:19.133730 u2DelayCellOfst[5]=16 cells (5 PI)
8490 00:22:19.137278 u2DelayCellOfst[6]=16 cells (5 PI)
8491 00:22:19.140503 u2DelayCellOfst[7]=3 cells (1 PI)
8492 00:22:19.143668 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8493 00:22:19.147081 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8494 00:22:19.150463 == TX Byte 1 ==
8495 00:22:19.153973 u2DelayCellOfst[8]=0 cells (0 PI)
8496 00:22:19.154069 u2DelayCellOfst[9]=3 cells (1 PI)
8497 00:22:19.156894 u2DelayCellOfst[10]=10 cells (3 PI)
8498 00:22:19.160277 u2DelayCellOfst[11]=6 cells (2 PI)
8499 00:22:19.163477 u2DelayCellOfst[12]=16 cells (5 PI)
8500 00:22:19.166728 u2DelayCellOfst[13]=16 cells (5 PI)
8501 00:22:19.170503 u2DelayCellOfst[14]=16 cells (5 PI)
8502 00:22:19.173982 u2DelayCellOfst[15]=13 cells (4 PI)
8503 00:22:19.177093 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8504 00:22:19.183859 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8505 00:22:19.183955 DramC Write-DBI on
8506 00:22:19.184035 ==
8507 00:22:19.186602 Dram Type= 6, Freq= 0, CH_1, rank 0
8508 00:22:19.193353 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8509 00:22:19.193462 ==
8510 00:22:19.193550
8511 00:22:19.193620
8512 00:22:19.193688 TX Vref Scan disable
8513 00:22:19.197219 == TX Byte 0 ==
8514 00:22:19.200628 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8515 00:22:19.203591 == TX Byte 1 ==
8516 00:22:19.207096 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8517 00:22:19.210363 DramC Write-DBI off
8518 00:22:19.210451
8519 00:22:19.210526 [DATLAT]
8520 00:22:19.210598 Freq=1600, CH1 RK0
8521 00:22:19.210669
8522 00:22:19.213948 DATLAT Default: 0xf
8523 00:22:19.214038 0, 0xFFFF, sum = 0
8524 00:22:19.216739 1, 0xFFFF, sum = 0
8525 00:22:19.220184 2, 0xFFFF, sum = 0
8526 00:22:19.220276 3, 0xFFFF, sum = 0
8527 00:22:19.223632 4, 0xFFFF, sum = 0
8528 00:22:19.223725 5, 0xFFFF, sum = 0
8529 00:22:19.227225 6, 0xFFFF, sum = 0
8530 00:22:19.227320 7, 0xFFFF, sum = 0
8531 00:22:19.230384 8, 0xFFFF, sum = 0
8532 00:22:19.230475 9, 0xFFFF, sum = 0
8533 00:22:19.233708 10, 0xFFFF, sum = 0
8534 00:22:19.233797 11, 0xFFFF, sum = 0
8535 00:22:19.236861 12, 0xFFFF, sum = 0
8536 00:22:19.236952 13, 0xFFFF, sum = 0
8537 00:22:19.240224 14, 0x0, sum = 1
8538 00:22:19.240315 15, 0x0, sum = 2
8539 00:22:19.243739 16, 0x0, sum = 3
8540 00:22:19.243832 17, 0x0, sum = 4
8541 00:22:19.246758 best_step = 15
8542 00:22:19.246850
8543 00:22:19.246927 ==
8544 00:22:19.250233 Dram Type= 6, Freq= 0, CH_1, rank 0
8545 00:22:19.253257 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8546 00:22:19.253348 ==
8547 00:22:19.257146 RX Vref Scan: 1
8548 00:22:19.257237
8549 00:22:19.257315 Set Vref Range= 24 -> 127
8550 00:22:19.257390
8551 00:22:19.260155 RX Vref 24 -> 127, step: 1
8552 00:22:19.260244
8553 00:22:19.263788 RX Delay 19 -> 252, step: 4
8554 00:22:19.263880
8555 00:22:19.266664 Set Vref, RX VrefLevel [Byte0]: 24
8556 00:22:19.270149 [Byte1]: 24
8557 00:22:19.270245
8558 00:22:19.273554 Set Vref, RX VrefLevel [Byte0]: 25
8559 00:22:19.276749 [Byte1]: 25
8560 00:22:19.276854
8561 00:22:19.280119 Set Vref, RX VrefLevel [Byte0]: 26
8562 00:22:19.283416 [Byte1]: 26
8563 00:22:19.287353
8564 00:22:19.287447 Set Vref, RX VrefLevel [Byte0]: 27
8565 00:22:19.290689 [Byte1]: 27
8566 00:22:19.295099
8567 00:22:19.295186 Set Vref, RX VrefLevel [Byte0]: 28
8568 00:22:19.298391 [Byte1]: 28
8569 00:22:19.302857
8570 00:22:19.302945 Set Vref, RX VrefLevel [Byte0]: 29
8571 00:22:19.305820 [Byte1]: 29
8572 00:22:19.310096
8573 00:22:19.310185 Set Vref, RX VrefLevel [Byte0]: 30
8574 00:22:19.313374 [Byte1]: 30
8575 00:22:19.317680
8576 00:22:19.317768 Set Vref, RX VrefLevel [Byte0]: 31
8577 00:22:19.320933 [Byte1]: 31
8578 00:22:19.325336
8579 00:22:19.325422 Set Vref, RX VrefLevel [Byte0]: 32
8580 00:22:19.328667 [Byte1]: 32
8581 00:22:19.332596
8582 00:22:19.332684 Set Vref, RX VrefLevel [Byte0]: 33
8583 00:22:19.336486 [Byte1]: 33
8584 00:22:19.340389
8585 00:22:19.340475 Set Vref, RX VrefLevel [Byte0]: 34
8586 00:22:19.343903 [Byte1]: 34
8587 00:22:19.348310
8588 00:22:19.348403 Set Vref, RX VrefLevel [Byte0]: 35
8589 00:22:19.351496 [Byte1]: 35
8590 00:22:19.355363
8591 00:22:19.355452 Set Vref, RX VrefLevel [Byte0]: 36
8592 00:22:19.358863 [Byte1]: 36
8593 00:22:19.363306
8594 00:22:19.363393 Set Vref, RX VrefLevel [Byte0]: 37
8595 00:22:19.366252 [Byte1]: 37
8596 00:22:19.370836
8597 00:22:19.370925 Set Vref, RX VrefLevel [Byte0]: 38
8598 00:22:19.373793 [Byte1]: 38
8599 00:22:19.378165
8600 00:22:19.378258 Set Vref, RX VrefLevel [Byte0]: 39
8601 00:22:19.381727 [Byte1]: 39
8602 00:22:19.386005
8603 00:22:19.386127 Set Vref, RX VrefLevel [Byte0]: 40
8604 00:22:19.389202 [Byte1]: 40
8605 00:22:19.393210
8606 00:22:19.393321 Set Vref, RX VrefLevel [Byte0]: 41
8607 00:22:19.396552 [Byte1]: 41
8608 00:22:19.400866
8609 00:22:19.400962 Set Vref, RX VrefLevel [Byte0]: 42
8610 00:22:19.404065 [Byte1]: 42
8611 00:22:19.408621
8612 00:22:19.408742 Set Vref, RX VrefLevel [Byte0]: 43
8613 00:22:19.411954 [Byte1]: 43
8614 00:22:19.416116
8615 00:22:19.416210 Set Vref, RX VrefLevel [Byte0]: 44
8616 00:22:19.419303 [Byte1]: 44
8617 00:22:19.423640
8618 00:22:19.423726 Set Vref, RX VrefLevel [Byte0]: 45
8619 00:22:19.427043 [Byte1]: 45
8620 00:22:19.431470
8621 00:22:19.431555 Set Vref, RX VrefLevel [Byte0]: 46
8622 00:22:19.434382 [Byte1]: 46
8623 00:22:19.439048
8624 00:22:19.439143 Set Vref, RX VrefLevel [Byte0]: 47
8625 00:22:19.441822 [Byte1]: 47
8626 00:22:19.446309
8627 00:22:19.446401 Set Vref, RX VrefLevel [Byte0]: 48
8628 00:22:19.449758 [Byte1]: 48
8629 00:22:19.454043
8630 00:22:19.454157 Set Vref, RX VrefLevel [Byte0]: 49
8631 00:22:19.457340 [Byte1]: 49
8632 00:22:19.461301
8633 00:22:19.461399 Set Vref, RX VrefLevel [Byte0]: 50
8634 00:22:19.464775 [Byte1]: 50
8635 00:22:19.469236
8636 00:22:19.469326 Set Vref, RX VrefLevel [Byte0]: 51
8637 00:22:19.472180 [Byte1]: 51
8638 00:22:19.476719
8639 00:22:19.476807 Set Vref, RX VrefLevel [Byte0]: 52
8640 00:22:19.480167 [Byte1]: 52
8641 00:22:19.484248
8642 00:22:19.484341 Set Vref, RX VrefLevel [Byte0]: 53
8643 00:22:19.487684 [Byte1]: 53
8644 00:22:19.492035
8645 00:22:19.492129 Set Vref, RX VrefLevel [Byte0]: 54
8646 00:22:19.495407 [Byte1]: 54
8647 00:22:19.499324
8648 00:22:19.499417 Set Vref, RX VrefLevel [Byte0]: 55
8649 00:22:19.502836 [Byte1]: 55
8650 00:22:19.507021
8651 00:22:19.507121 Set Vref, RX VrefLevel [Byte0]: 56
8652 00:22:19.510546 [Byte1]: 56
8653 00:22:19.514786
8654 00:22:19.514880 Set Vref, RX VrefLevel [Byte0]: 57
8655 00:22:19.517721 [Byte1]: 57
8656 00:22:19.522035
8657 00:22:19.522130 Set Vref, RX VrefLevel [Byte0]: 58
8658 00:22:19.525503 [Byte1]: 58
8659 00:22:19.529562
8660 00:22:19.529659 Set Vref, RX VrefLevel [Byte0]: 59
8661 00:22:19.532947 [Byte1]: 59
8662 00:22:19.537201
8663 00:22:19.537288 Set Vref, RX VrefLevel [Byte0]: 60
8664 00:22:19.540564 [Byte1]: 60
8665 00:22:19.544863
8666 00:22:19.544948 Set Vref, RX VrefLevel [Byte0]: 61
8667 00:22:19.548306 [Byte1]: 61
8668 00:22:19.552162
8669 00:22:19.552252 Set Vref, RX VrefLevel [Byte0]: 62
8670 00:22:19.555864 [Byte1]: 62
8671 00:22:19.560103
8672 00:22:19.560193 Set Vref, RX VrefLevel [Byte0]: 63
8673 00:22:19.563437 [Byte1]: 63
8674 00:22:19.567771
8675 00:22:19.567880 Set Vref, RX VrefLevel [Byte0]: 64
8676 00:22:19.570681 [Byte1]: 64
8677 00:22:19.575292
8678 00:22:19.575390 Set Vref, RX VrefLevel [Byte0]: 65
8679 00:22:19.578399 [Byte1]: 65
8680 00:22:19.582715
8681 00:22:19.582813 Set Vref, RX VrefLevel [Byte0]: 66
8682 00:22:19.585813 [Byte1]: 66
8683 00:22:19.590363
8684 00:22:19.590461 Set Vref, RX VrefLevel [Byte0]: 67
8685 00:22:19.593743 [Byte1]: 67
8686 00:22:19.598079
8687 00:22:19.598178 Set Vref, RX VrefLevel [Byte0]: 68
8688 00:22:19.601010 [Byte1]: 68
8689 00:22:19.605305
8690 00:22:19.605401 Set Vref, RX VrefLevel [Byte0]: 69
8691 00:22:19.608772 [Byte1]: 69
8692 00:22:19.612906
8693 00:22:19.612994 Set Vref, RX VrefLevel [Byte0]: 70
8694 00:22:19.616315 [Byte1]: 70
8695 00:22:19.620652
8696 00:22:19.620744 Set Vref, RX VrefLevel [Byte0]: 71
8697 00:22:19.623729 [Byte1]: 71
8698 00:22:19.628024
8699 00:22:19.628117 Set Vref, RX VrefLevel [Byte0]: 72
8700 00:22:19.631623 [Byte1]: 72
8701 00:22:19.635569
8702 00:22:19.635660 Set Vref, RX VrefLevel [Byte0]: 73
8703 00:22:19.638990 [Byte1]: 73
8704 00:22:19.643288
8705 00:22:19.643378 Final RX Vref Byte 0 = 54 to rank0
8706 00:22:19.646547 Final RX Vref Byte 1 = 62 to rank0
8707 00:22:19.649839 Final RX Vref Byte 0 = 54 to rank1
8708 00:22:19.653353 Final RX Vref Byte 1 = 62 to rank1==
8709 00:22:19.656548 Dram Type= 6, Freq= 0, CH_1, rank 0
8710 00:22:19.663218 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8711 00:22:19.663321 ==
8712 00:22:19.663406 DQS Delay:
8713 00:22:19.663488 DQS0 = 0, DQS1 = 0
8714 00:22:19.666536 DQM Delay:
8715 00:22:19.666628 DQM0 = 133, DQM1 = 128
8716 00:22:19.669989 DQ Delay:
8717 00:22:19.673063 DQ0 =136, DQ1 =130, DQ2 =122, DQ3 =132
8718 00:22:19.676732 DQ4 =132, DQ5 =144, DQ6 =144, DQ7 =130
8719 00:22:19.680166 DQ8 =114, DQ9 =120, DQ10 =132, DQ11 =122
8720 00:22:19.683287 DQ12 =138, DQ13 =134, DQ14 =136, DQ15 =134
8721 00:22:19.683377
8722 00:22:19.683452
8723 00:22:19.683524
8724 00:22:19.686682 [DramC_TX_OE_Calibration] TA2
8725 00:22:19.690122 Original DQ_B0 (3 6) =30, OEN = 27
8726 00:22:19.693248 Original DQ_B1 (3 6) =30, OEN = 27
8727 00:22:19.696687 24, 0x0, End_B0=24 End_B1=24
8728 00:22:19.696805 25, 0x0, End_B0=25 End_B1=25
8729 00:22:19.700268 26, 0x0, End_B0=26 End_B1=26
8730 00:22:19.703161 27, 0x0, End_B0=27 End_B1=27
8731 00:22:19.706646 28, 0x0, End_B0=28 End_B1=28
8732 00:22:19.706745 29, 0x0, End_B0=29 End_B1=29
8733 00:22:19.710231 30, 0x0, End_B0=30 End_B1=30
8734 00:22:19.713526 31, 0x4141, End_B0=30 End_B1=30
8735 00:22:19.716615 Byte0 end_step=30 best_step=27
8736 00:22:19.720221 Byte1 end_step=30 best_step=27
8737 00:22:19.723201 Byte0 TX OE(2T, 0.5T) = (3, 3)
8738 00:22:19.723278 Byte1 TX OE(2T, 0.5T) = (3, 3)
8739 00:22:19.723354
8740 00:22:19.723425
8741 00:22:19.733412 [DQSOSCAuto] RK0, (LSB)MR18= 0x1826, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
8742 00:22:19.736863 CH1 RK0: MR19=303, MR18=1826
8743 00:22:19.743667 CH1_RK0: MR19=0x303, MR18=0x1826, DQSOSC=390, MR23=63, INC=24, DEC=16
8744 00:22:19.743744
8745 00:22:19.746904 ----->DramcWriteLeveling(PI) begin...
8746 00:22:19.746983 ==
8747 00:22:19.750216 Dram Type= 6, Freq= 0, CH_1, rank 1
8748 00:22:19.753572 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8749 00:22:19.753649 ==
8750 00:22:19.756883 Write leveling (Byte 0): 24 => 24
8751 00:22:19.760201 Write leveling (Byte 1): 28 => 28
8752 00:22:19.763542 DramcWriteLeveling(PI) end<-----
8753 00:22:19.763618
8754 00:22:19.763694 ==
8755 00:22:19.767093 Dram Type= 6, Freq= 0, CH_1, rank 1
8756 00:22:19.770269 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8757 00:22:19.770362 ==
8758 00:22:19.773589 [Gating] SW mode calibration
8759 00:22:19.779917 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8760 00:22:19.786820 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8761 00:22:19.789767 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8762 00:22:19.793402 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8763 00:22:19.799747 1 4 8 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
8764 00:22:19.803318 1 4 12 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 0)
8765 00:22:19.806439 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8766 00:22:19.813186 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8767 00:22:19.816885 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8768 00:22:19.819598 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8769 00:22:19.826590 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8770 00:22:19.829907 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8771 00:22:19.833058 1 5 8 | B1->B0 | 2d2d 3434 | 0 1 | (0 1) (1 0)
8772 00:22:19.836634 1 5 12 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 0)
8773 00:22:19.843336 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8774 00:22:19.846673 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8775 00:22:19.850061 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8776 00:22:19.856666 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8777 00:22:19.860009 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8778 00:22:19.863607 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8779 00:22:19.870126 1 6 8 | B1->B0 | 3535 2323 | 0 0 | (0 0) (0 0)
8780 00:22:19.873358 1 6 12 | B1->B0 | 4646 3d3d | 0 0 | (0 0) (0 0)
8781 00:22:19.876431 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8782 00:22:19.882864 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8783 00:22:19.886310 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8784 00:22:19.889759 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8785 00:22:19.896230 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8786 00:22:19.899714 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8787 00:22:19.903152 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8788 00:22:19.909707 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8789 00:22:19.913031 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8790 00:22:19.916100 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8791 00:22:19.922979 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8792 00:22:19.926153 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8793 00:22:19.929517 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8794 00:22:19.936192 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8795 00:22:19.939794 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8796 00:22:19.942770 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8797 00:22:19.949179 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8798 00:22:19.952567 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8799 00:22:19.955850 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8800 00:22:19.962625 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8801 00:22:19.966083 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8802 00:22:19.969097 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8803 00:22:19.975560 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8804 00:22:19.978894 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8805 00:22:19.982179 Total UI for P1: 0, mck2ui 16
8806 00:22:19.985607 best dqsien dly found for B0: ( 1, 9, 8)
8807 00:22:19.989185 Total UI for P1: 0, mck2ui 16
8808 00:22:19.992334 best dqsien dly found for B1: ( 1, 9, 8)
8809 00:22:19.995649 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8810 00:22:19.999084 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8811 00:22:19.999160
8812 00:22:20.002587 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8813 00:22:20.006043 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8814 00:22:20.008967 [Gating] SW calibration Done
8815 00:22:20.009043 ==
8816 00:22:20.012452 Dram Type= 6, Freq= 0, CH_1, rank 1
8817 00:22:20.015806 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8818 00:22:20.015882 ==
8819 00:22:20.019095 RX Vref Scan: 0
8820 00:22:20.019170
8821 00:22:20.022067 RX Vref 0 -> 0, step: 1
8822 00:22:20.022143
8823 00:22:20.022200 RX Delay 0 -> 252, step: 8
8824 00:22:20.029008 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8825 00:22:20.031962 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8826 00:22:20.035742 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8827 00:22:20.038655 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8828 00:22:20.042181 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8829 00:22:20.048435 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8830 00:22:20.051785 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8831 00:22:20.055099 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
8832 00:22:20.058550 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8833 00:22:20.061788 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8834 00:22:20.068586 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8835 00:22:20.071582 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8836 00:22:20.075090 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8837 00:22:20.078383 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8838 00:22:20.081640 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8839 00:22:20.088297 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8840 00:22:20.088375 ==
8841 00:22:20.091773 Dram Type= 6, Freq= 0, CH_1, rank 1
8842 00:22:20.094968 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8843 00:22:20.095046 ==
8844 00:22:20.095122 DQS Delay:
8845 00:22:20.098154 DQS0 = 0, DQS1 = 0
8846 00:22:20.098231 DQM Delay:
8847 00:22:20.101775 DQM0 = 138, DQM1 = 131
8848 00:22:20.101851 DQ Delay:
8849 00:22:20.104700 DQ0 =143, DQ1 =135, DQ2 =123, DQ3 =135
8850 00:22:20.108246 DQ4 =139, DQ5 =147, DQ6 =143, DQ7 =139
8851 00:22:20.111111 DQ8 =115, DQ9 =119, DQ10 =135, DQ11 =127
8852 00:22:20.114652 DQ12 =139, DQ13 =143, DQ14 =135, DQ15 =139
8853 00:22:20.118121
8854 00:22:20.118197
8855 00:22:20.118272 ==
8856 00:22:20.121422 Dram Type= 6, Freq= 0, CH_1, rank 1
8857 00:22:20.124405 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8858 00:22:20.124482 ==
8859 00:22:20.124574
8860 00:22:20.124663
8861 00:22:20.127831 TX Vref Scan disable
8862 00:22:20.127908 == TX Byte 0 ==
8863 00:22:20.134404 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8864 00:22:20.137787 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8865 00:22:20.137864 == TX Byte 1 ==
8866 00:22:20.144458 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8867 00:22:20.147466 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8868 00:22:20.147542 ==
8869 00:22:20.151111 Dram Type= 6, Freq= 0, CH_1, rank 1
8870 00:22:20.154728 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8871 00:22:20.154805 ==
8872 00:22:20.167686
8873 00:22:20.171438 TX Vref early break, caculate TX vref
8874 00:22:20.174276 TX Vref=16, minBit 1, minWin=24, winSum=393
8875 00:22:20.177782 TX Vref=18, minBit 1, minWin=24, winSum=399
8876 00:22:20.181197 TX Vref=20, minBit 12, minWin=24, winSum=407
8877 00:22:20.184123 TX Vref=22, minBit 3, minWin=25, winSum=415
8878 00:22:20.187473 TX Vref=24, minBit 9, minWin=25, winSum=416
8879 00:22:20.194268 TX Vref=26, minBit 9, minWin=24, winSum=425
8880 00:22:20.197785 TX Vref=28, minBit 0, minWin=26, winSum=432
8881 00:22:20.201035 TX Vref=30, minBit 0, minWin=26, winSum=424
8882 00:22:20.204344 TX Vref=32, minBit 1, minWin=25, winSum=415
8883 00:22:20.207677 TX Vref=34, minBit 10, minWin=24, winSum=408
8884 00:22:20.214418 [TxChooseVref] Worse bit 0, Min win 26, Win sum 432, Final Vref 28
8885 00:22:20.214492
8886 00:22:20.217782 Final TX Range 0 Vref 28
8887 00:22:20.217871
8888 00:22:20.217941 ==
8889 00:22:20.220818 Dram Type= 6, Freq= 0, CH_1, rank 1
8890 00:22:20.224144 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8891 00:22:20.224231 ==
8892 00:22:20.224302
8893 00:22:20.224367
8894 00:22:20.227644 TX Vref Scan disable
8895 00:22:20.234161 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8896 00:22:20.234295 == TX Byte 0 ==
8897 00:22:20.237566 u2DelayCellOfst[0]=13 cells (4 PI)
8898 00:22:20.241184 u2DelayCellOfst[1]=10 cells (3 PI)
8899 00:22:20.244599 u2DelayCellOfst[2]=0 cells (0 PI)
8900 00:22:20.247501 u2DelayCellOfst[3]=3 cells (1 PI)
8901 00:22:20.250960 u2DelayCellOfst[4]=6 cells (2 PI)
8902 00:22:20.254177 u2DelayCellOfst[5]=16 cells (5 PI)
8903 00:22:20.257681 u2DelayCellOfst[6]=13 cells (4 PI)
8904 00:22:20.257768 u2DelayCellOfst[7]=3 cells (1 PI)
8905 00:22:20.264098 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8906 00:22:20.267850 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8907 00:22:20.267938 == TX Byte 1 ==
8908 00:22:20.271193 u2DelayCellOfst[8]=0 cells (0 PI)
8909 00:22:20.274560 u2DelayCellOfst[9]=3 cells (1 PI)
8910 00:22:20.277928 u2DelayCellOfst[10]=6 cells (2 PI)
8911 00:22:20.281043 u2DelayCellOfst[11]=3 cells (1 PI)
8912 00:22:20.284179 u2DelayCellOfst[12]=13 cells (4 PI)
8913 00:22:20.287549 u2DelayCellOfst[13]=13 cells (4 PI)
8914 00:22:20.290985 u2DelayCellOfst[14]=16 cells (5 PI)
8915 00:22:20.294259 u2DelayCellOfst[15]=13 cells (4 PI)
8916 00:22:20.297893 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8917 00:22:20.300685 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8918 00:22:20.304131 DramC Write-DBI on
8919 00:22:20.304207 ==
8920 00:22:20.307949 Dram Type= 6, Freq= 0, CH_1, rank 1
8921 00:22:20.311260 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8922 00:22:20.311329 ==
8923 00:22:20.311400
8924 00:22:20.314283
8925 00:22:20.314352 TX Vref Scan disable
8926 00:22:20.317746 == TX Byte 0 ==
8927 00:22:20.320846 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8928 00:22:20.324283 == TX Byte 1 ==
8929 00:22:20.327595 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8930 00:22:20.327667 DramC Write-DBI off
8931 00:22:20.327742
8932 00:22:20.331008 [DATLAT]
8933 00:22:20.331087 Freq=1600, CH1 RK1
8934 00:22:20.331164
8935 00:22:20.334308 DATLAT Default: 0xf
8936 00:22:20.334386 0, 0xFFFF, sum = 0
8937 00:22:20.337781 1, 0xFFFF, sum = 0
8938 00:22:20.337860 2, 0xFFFF, sum = 0
8939 00:22:20.340667 3, 0xFFFF, sum = 0
8940 00:22:20.340777 4, 0xFFFF, sum = 0
8941 00:22:20.344266 5, 0xFFFF, sum = 0
8942 00:22:20.344345 6, 0xFFFF, sum = 0
8943 00:22:20.347708 7, 0xFFFF, sum = 0
8944 00:22:20.347787 8, 0xFFFF, sum = 0
8945 00:22:20.351123 9, 0xFFFF, sum = 0
8946 00:22:20.354091 10, 0xFFFF, sum = 0
8947 00:22:20.354170 11, 0xFFFF, sum = 0
8948 00:22:20.357567 12, 0xFFFF, sum = 0
8949 00:22:20.357645 13, 0xFFFF, sum = 0
8950 00:22:20.361147 14, 0x0, sum = 1
8951 00:22:20.361250 15, 0x0, sum = 2
8952 00:22:20.364076 16, 0x0, sum = 3
8953 00:22:20.364155 17, 0x0, sum = 4
8954 00:22:20.364233 best_step = 15
8955 00:22:20.364304
8956 00:22:20.367487 ==
8957 00:22:20.370916 Dram Type= 6, Freq= 0, CH_1, rank 1
8958 00:22:20.374343 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8959 00:22:20.374422 ==
8960 00:22:20.374499 RX Vref Scan: 0
8961 00:22:20.374571
8962 00:22:20.377441 RX Vref 0 -> 0, step: 1
8963 00:22:20.377520
8964 00:22:20.380842 RX Delay 19 -> 252, step: 4
8965 00:22:20.384124 iDelay=195, Bit 0, Center 138 (95 ~ 182) 88
8966 00:22:20.387526 iDelay=195, Bit 1, Center 132 (87 ~ 178) 92
8967 00:22:20.394276 iDelay=195, Bit 2, Center 122 (75 ~ 170) 96
8968 00:22:20.397405 iDelay=195, Bit 3, Center 132 (83 ~ 182) 100
8969 00:22:20.400834 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
8970 00:22:20.404169 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8971 00:22:20.407554 iDelay=195, Bit 6, Center 142 (95 ~ 190) 96
8972 00:22:20.410775 iDelay=195, Bit 7, Center 132 (87 ~ 178) 92
8973 00:22:20.417539 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
8974 00:22:20.420651 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8975 00:22:20.424118 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
8976 00:22:20.427528 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8977 00:22:20.430893 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
8978 00:22:20.437259 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8979 00:22:20.440669 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
8980 00:22:20.444290 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
8981 00:22:20.444366 ==
8982 00:22:20.447217 Dram Type= 6, Freq= 0, CH_1, rank 1
8983 00:22:20.450815 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8984 00:22:20.450891 ==
8985 00:22:20.454195 DQS Delay:
8986 00:22:20.454270 DQS0 = 0, DQS1 = 0
8987 00:22:20.457713 DQM Delay:
8988 00:22:20.457788 DQM0 = 134, DQM1 = 129
8989 00:22:20.460737 DQ Delay:
8990 00:22:20.463984 DQ0 =138, DQ1 =132, DQ2 =122, DQ3 =132
8991 00:22:20.467470 DQ4 =134, DQ5 =146, DQ6 =142, DQ7 =132
8992 00:22:20.470657 DQ8 =112, DQ9 =118, DQ10 =130, DQ11 =124
8993 00:22:20.473973 DQ12 =138, DQ13 =136, DQ14 =138, DQ15 =140
8994 00:22:20.474073
8995 00:22:20.474145
8996 00:22:20.474197
8997 00:22:20.477467 [DramC_TX_OE_Calibration] TA2
8998 00:22:20.480969 Original DQ_B0 (3 6) =30, OEN = 27
8999 00:22:20.484128 Original DQ_B1 (3 6) =30, OEN = 27
9000 00:22:20.484203 24, 0x0, End_B0=24 End_B1=24
9001 00:22:20.487701 25, 0x0, End_B0=25 End_B1=25
9002 00:22:20.490693 26, 0x0, End_B0=26 End_B1=26
9003 00:22:20.494352 27, 0x0, End_B0=27 End_B1=27
9004 00:22:20.494428 28, 0x0, End_B0=28 End_B1=28
9005 00:22:20.497463 29, 0x0, End_B0=29 End_B1=29
9006 00:22:20.500641 30, 0x0, End_B0=30 End_B1=30
9007 00:22:20.503949 31, 0x4141, End_B0=30 End_B1=30
9008 00:22:20.507455 Byte0 end_step=30 best_step=27
9009 00:22:20.510764 Byte1 end_step=30 best_step=27
9010 00:22:20.510860 Byte0 TX OE(2T, 0.5T) = (3, 3)
9011 00:22:20.514280 Byte1 TX OE(2T, 0.5T) = (3, 3)
9012 00:22:20.514373
9013 00:22:20.514452
9014 00:22:20.524236 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e09, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
9015 00:22:20.527535 CH1 RK1: MR19=303, MR18=1E09
9016 00:22:20.530509 CH1_RK1: MR19=0x303, MR18=0x1E09, DQSOSC=394, MR23=63, INC=23, DEC=15
9017 00:22:20.533949 [RxdqsGatingPostProcess] freq 1600
9018 00:22:20.540735 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9019 00:22:20.543667 best DQS0 dly(2T, 0.5T) = (1, 1)
9020 00:22:20.547125 best DQS1 dly(2T, 0.5T) = (1, 1)
9021 00:22:20.550598 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9022 00:22:20.553668 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9023 00:22:20.557137 best DQS0 dly(2T, 0.5T) = (1, 1)
9024 00:22:20.560603 best DQS1 dly(2T, 0.5T) = (1, 1)
9025 00:22:20.560696 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9026 00:22:20.563943 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9027 00:22:20.566932 Pre-setting of DQS Precalculation
9028 00:22:20.573686 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9029 00:22:20.580122 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9030 00:22:20.587165 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9031 00:22:20.587261
9032 00:22:20.587337
9033 00:22:20.590428 [Calibration Summary] 3200 Mbps
9034 00:22:20.593360 CH 0, Rank 0
9035 00:22:20.593454 SW Impedance : PASS
9036 00:22:20.596686 DUTY Scan : NO K
9037 00:22:20.596779 ZQ Calibration : PASS
9038 00:22:20.600345 Jitter Meter : NO K
9039 00:22:20.603860 CBT Training : PASS
9040 00:22:20.603947 Write leveling : PASS
9041 00:22:20.606772 RX DQS gating : PASS
9042 00:22:20.610056 RX DQ/DQS(RDDQC) : PASS
9043 00:22:20.610145 TX DQ/DQS : PASS
9044 00:22:20.613202 RX DATLAT : PASS
9045 00:22:20.616619 RX DQ/DQS(Engine): PASS
9046 00:22:20.616712 TX OE : PASS
9047 00:22:20.620142 All Pass.
9048 00:22:20.620231
9049 00:22:20.620307 CH 0, Rank 1
9050 00:22:20.623556 SW Impedance : PASS
9051 00:22:20.623645 DUTY Scan : NO K
9052 00:22:20.627057 ZQ Calibration : PASS
9053 00:22:20.630339 Jitter Meter : NO K
9054 00:22:20.630432 CBT Training : PASS
9055 00:22:20.633748 Write leveling : PASS
9056 00:22:20.636628 RX DQS gating : PASS
9057 00:22:20.636762 RX DQ/DQS(RDDQC) : PASS
9058 00:22:20.639885 TX DQ/DQS : PASS
9059 00:22:20.643130 RX DATLAT : PASS
9060 00:22:20.643227 RX DQ/DQS(Engine): PASS
9061 00:22:20.646765 TX OE : PASS
9062 00:22:20.646863 All Pass.
9063 00:22:20.646948
9064 00:22:20.649926 CH 1, Rank 0
9065 00:22:20.650022 SW Impedance : PASS
9066 00:22:20.653299 DUTY Scan : NO K
9067 00:22:20.656802 ZQ Calibration : PASS
9068 00:22:20.656900 Jitter Meter : NO K
9069 00:22:20.659785 CBT Training : PASS
9070 00:22:20.659882 Write leveling : PASS
9071 00:22:20.663219 RX DQS gating : PASS
9072 00:22:20.666987 RX DQ/DQS(RDDQC) : PASS
9073 00:22:20.667078 TX DQ/DQS : PASS
9074 00:22:20.669812 RX DATLAT : PASS
9075 00:22:20.673365 RX DQ/DQS(Engine): PASS
9076 00:22:20.673456 TX OE : PASS
9077 00:22:20.676349 All Pass.
9078 00:22:20.676432
9079 00:22:20.676504 CH 1, Rank 1
9080 00:22:20.679757 SW Impedance : PASS
9081 00:22:20.679841 DUTY Scan : NO K
9082 00:22:20.683216 ZQ Calibration : PASS
9083 00:22:20.686285 Jitter Meter : NO K
9084 00:22:20.686376 CBT Training : PASS
9085 00:22:20.689761 Write leveling : PASS
9086 00:22:20.693157 RX DQS gating : PASS
9087 00:22:20.693252 RX DQ/DQS(RDDQC) : PASS
9088 00:22:20.696385 TX DQ/DQS : PASS
9089 00:22:20.699901 RX DATLAT : PASS
9090 00:22:20.699993 RX DQ/DQS(Engine): PASS
9091 00:22:20.702755 TX OE : PASS
9092 00:22:20.702846 All Pass.
9093 00:22:20.702922
9094 00:22:20.706263 DramC Write-DBI on
9095 00:22:20.709629 PER_BANK_REFRESH: Hybrid Mode
9096 00:22:20.709721 TX_TRACKING: ON
9097 00:22:20.719555 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9098 00:22:20.726073 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9099 00:22:20.732623 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9100 00:22:20.736041 [FAST_K] Save calibration result to emmc
9101 00:22:20.739491 sync common calibartion params.
9102 00:22:20.742883 sync cbt_mode0:1, 1:1
9103 00:22:20.746507 dram_init: ddr_geometry: 2
9104 00:22:20.746598 dram_init: ddr_geometry: 2
9105 00:22:20.749429 dram_init: ddr_geometry: 2
9106 00:22:20.752811 0:dram_rank_size:100000000
9107 00:22:20.752902 1:dram_rank_size:100000000
9108 00:22:20.759387 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9109 00:22:20.762606 DFS_SHUFFLE_HW_MODE: ON
9110 00:22:20.766024 dramc_set_vcore_voltage set vcore to 725000
9111 00:22:20.769474 Read voltage for 1600, 0
9112 00:22:20.769563 Vio18 = 0
9113 00:22:20.769640 Vcore = 725000
9114 00:22:20.772909 Vdram = 0
9115 00:22:20.772996 Vddq = 0
9116 00:22:20.773071 Vmddr = 0
9117 00:22:20.776216 switch to 3200 Mbps bootup
9118 00:22:20.776302 [DramcRunTimeConfig]
9119 00:22:20.779427 PHYPLL
9120 00:22:20.779514 DPM_CONTROL_AFTERK: ON
9121 00:22:20.782748 PER_BANK_REFRESH: ON
9122 00:22:20.786256 REFRESH_OVERHEAD_REDUCTION: ON
9123 00:22:20.786347 CMD_PICG_NEW_MODE: OFF
9124 00:22:20.789168 XRTWTW_NEW_MODE: ON
9125 00:22:20.789257 XRTRTR_NEW_MODE: ON
9126 00:22:20.792647 TX_TRACKING: ON
9127 00:22:20.792741 RDSEL_TRACKING: OFF
9128 00:22:20.796030 DQS Precalculation for DVFS: ON
9129 00:22:20.799448 RX_TRACKING: OFF
9130 00:22:20.799539 HW_GATING DBG: ON
9131 00:22:20.802618 ZQCS_ENABLE_LP4: ON
9132 00:22:20.802697 RX_PICG_NEW_MODE: ON
9133 00:22:20.805954 TX_PICG_NEW_MODE: ON
9134 00:22:20.806029 ENABLE_RX_DCM_DPHY: ON
9135 00:22:20.809396 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9136 00:22:20.812730 DUMMY_READ_FOR_TRACKING: OFF
9137 00:22:20.815745 !!! SPM_CONTROL_AFTERK: OFF
9138 00:22:20.819322 !!! SPM could not control APHY
9139 00:22:20.819397 IMPEDANCE_TRACKING: ON
9140 00:22:20.822742 TEMP_SENSOR: ON
9141 00:22:20.822818 HW_SAVE_FOR_SR: OFF
9142 00:22:20.825762 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9143 00:22:20.829208 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9144 00:22:20.832328 Read ODT Tracking: ON
9145 00:22:20.835873 Refresh Rate DeBounce: ON
9146 00:22:20.835966 DFS_NO_QUEUE_FLUSH: ON
9147 00:22:20.839255 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9148 00:22:20.842423 ENABLE_DFS_RUNTIME_MRW: OFF
9149 00:22:20.845708 DDR_RESERVE_NEW_MODE: ON
9150 00:22:20.845802 MR_CBT_SWITCH_FREQ: ON
9151 00:22:20.849336 =========================
9152 00:22:20.867698 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9153 00:22:20.871123 dram_init: ddr_geometry: 2
9154 00:22:20.889582 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9155 00:22:20.893111 dram_init: dram init end (result: 0)
9156 00:22:20.899481 DRAM-K: Full calibration passed in 24499 msecs
9157 00:22:20.902877 MRC: failed to locate region type 0.
9158 00:22:20.902971 DRAM rank0 size:0x100000000,
9159 00:22:20.906275 DRAM rank1 size=0x100000000
9160 00:22:20.916206 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9161 00:22:20.922530 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9162 00:22:20.929270 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9163 00:22:20.935850 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9164 00:22:20.939311 DRAM rank0 size:0x100000000,
9165 00:22:20.942669 DRAM rank1 size=0x100000000
9166 00:22:20.942766 CBMEM:
9167 00:22:20.945762 IMD: root @ 0xfffff000 254 entries.
9168 00:22:20.949065 IMD: root @ 0xffffec00 62 entries.
9169 00:22:20.952449 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9170 00:22:20.955846 WARNING: RO_VPD is uninitialized or empty.
9171 00:22:20.962621 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9172 00:22:20.969771 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9173 00:22:20.982418 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9174 00:22:20.994015 BS: romstage times (exec / console): total (unknown) / 24010 ms
9175 00:22:20.994112
9176 00:22:20.994228
9177 00:22:21.003926 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9178 00:22:21.007018 ARM64: Exception handlers installed.
9179 00:22:21.010285 ARM64: Testing exception
9180 00:22:21.013758 ARM64: Done test exception
9181 00:22:21.013848 Enumerating buses...
9182 00:22:21.017052 Show all devs... Before device enumeration.
9183 00:22:21.020012 Root Device: enabled 1
9184 00:22:21.023661 CPU_CLUSTER: 0: enabled 1
9185 00:22:21.023753 CPU: 00: enabled 1
9186 00:22:21.026879 Compare with tree...
9187 00:22:21.026971 Root Device: enabled 1
9188 00:22:21.030462 CPU_CLUSTER: 0: enabled 1
9189 00:22:21.033396 CPU: 00: enabled 1
9190 00:22:21.033488 Root Device scanning...
9191 00:22:21.036936 scan_static_bus for Root Device
9192 00:22:21.040289 CPU_CLUSTER: 0 enabled
9193 00:22:21.043196 scan_static_bus for Root Device done
9194 00:22:21.046675 scan_bus: bus Root Device finished in 8 msecs
9195 00:22:21.046766 done
9196 00:22:21.053153 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9197 00:22:21.056686 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9198 00:22:21.063317 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9199 00:22:21.066910 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9200 00:22:21.070314 Allocating resources...
9201 00:22:21.073304 Reading resources...
9202 00:22:21.076867 Root Device read_resources bus 0 link: 0
9203 00:22:21.076955 DRAM rank0 size:0x100000000,
9204 00:22:21.079884 DRAM rank1 size=0x100000000
9205 00:22:21.083314 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9206 00:22:21.086758 CPU: 00 missing read_resources
9207 00:22:21.090147 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9208 00:22:21.096570 Root Device read_resources bus 0 link: 0 done
9209 00:22:21.096662 Done reading resources.
9210 00:22:21.103208 Show resources in subtree (Root Device)...After reading.
9211 00:22:21.106518 Root Device child on link 0 CPU_CLUSTER: 0
9212 00:22:21.109647 CPU_CLUSTER: 0 child on link 0 CPU: 00
9213 00:22:21.119957 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9214 00:22:21.120057 CPU: 00
9215 00:22:21.123140 Root Device assign_resources, bus 0 link: 0
9216 00:22:21.126359 CPU_CLUSTER: 0 missing set_resources
9217 00:22:21.133044 Root Device assign_resources, bus 0 link: 0 done
9218 00:22:21.133149 Done setting resources.
9219 00:22:21.139620 Show resources in subtree (Root Device)...After assigning values.
9220 00:22:21.143036 Root Device child on link 0 CPU_CLUSTER: 0
9221 00:22:21.146546 CPU_CLUSTER: 0 child on link 0 CPU: 00
9222 00:22:21.156069 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9223 00:22:21.156165 CPU: 00
9224 00:22:21.159282 Done allocating resources.
9225 00:22:21.162745 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9226 00:22:21.166131 Enabling resources...
9227 00:22:21.166224 done.
9228 00:22:21.172687 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9229 00:22:21.172787 Initializing devices...
9230 00:22:21.176199 Root Device init
9231 00:22:21.176288 init hardware done!
9232 00:22:21.179641 0x00000018: ctrlr->caps
9233 00:22:21.182725 52.000 MHz: ctrlr->f_max
9234 00:22:21.182819 0.400 MHz: ctrlr->f_min
9235 00:22:21.186232 0x40ff8080: ctrlr->voltages
9236 00:22:21.186328 sclk: 390625
9237 00:22:21.189147 Bus Width = 1
9238 00:22:21.189239 sclk: 390625
9239 00:22:21.192857 Bus Width = 1
9240 00:22:21.192948 Early init status = 3
9241 00:22:21.199362 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9242 00:22:21.202725 in-header: 03 fc 00 00 01 00 00 00
9243 00:22:21.206028 in-data: 00
9244 00:22:21.208970 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9245 00:22:21.213896 in-header: 03 fd 00 00 00 00 00 00
9246 00:22:21.216842 in-data:
9247 00:22:21.220142 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9248 00:22:21.224668 in-header: 03 fc 00 00 01 00 00 00
9249 00:22:21.228151 in-data: 00
9250 00:22:21.231273 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9251 00:22:21.236964 in-header: 03 fd 00 00 00 00 00 00
9252 00:22:21.240375 in-data:
9253 00:22:21.243695 [SSUSB] Setting up USB HOST controller...
9254 00:22:21.247159 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9255 00:22:21.250574 [SSUSB] phy power-on done.
9256 00:22:21.253674 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9257 00:22:21.260275 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9258 00:22:21.263548 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9259 00:22:21.270348 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9260 00:22:21.277128 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9261 00:22:21.283435 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9262 00:22:21.290261 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9263 00:22:21.296930 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9264 00:22:21.297023 SPM: binary array size = 0x9dc
9265 00:22:21.303853 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9266 00:22:21.310101 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9267 00:22:21.317075 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9268 00:22:21.320010 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9269 00:22:21.323788 configure_display: Starting display init
9270 00:22:21.360417 anx7625_power_on_init: Init interface.
9271 00:22:21.364021 anx7625_disable_pd_protocol: Disabled PD feature.
9272 00:22:21.367259 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9273 00:22:21.394976 anx7625_start_dp_work: Secure OCM version=00
9274 00:22:21.397813 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9275 00:22:21.412830 sp_tx_get_edid_block: EDID Block = 1
9276 00:22:21.515278 Extracted contents:
9277 00:22:21.518558 header: 00 ff ff ff ff ff ff 00
9278 00:22:21.522091 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9279 00:22:21.525619 version: 01 04
9280 00:22:21.528629 basic params: 95 1f 11 78 0a
9281 00:22:21.531939 chroma info: 76 90 94 55 54 90 27 21 50 54
9282 00:22:21.535241 established: 00 00 00
9283 00:22:21.542215 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9284 00:22:21.545146 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9285 00:22:21.551769 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9286 00:22:21.558472 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9287 00:22:21.565097 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9288 00:22:21.568568 extensions: 00
9289 00:22:21.568660 checksum: fb
9290 00:22:21.568794
9291 00:22:21.571969 Manufacturer: IVO Model 57d Serial Number 0
9292 00:22:21.575379 Made week 0 of 2020
9293 00:22:21.575479 EDID version: 1.4
9294 00:22:21.578689 Digital display
9295 00:22:21.581782 6 bits per primary color channel
9296 00:22:21.581892 DisplayPort interface
9297 00:22:21.585136 Maximum image size: 31 cm x 17 cm
9298 00:22:21.588664 Gamma: 220%
9299 00:22:21.588784 Check DPMS levels
9300 00:22:21.591682 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9301 00:22:21.595040 First detailed timing is preferred timing
9302 00:22:21.598731 Established timings supported:
9303 00:22:21.601746 Standard timings supported:
9304 00:22:21.601841 Detailed timings
9305 00:22:21.608670 Hex of detail: 383680a07038204018303c0035ae10000019
9306 00:22:21.612090 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9307 00:22:21.618361 0780 0798 07c8 0820 hborder 0
9308 00:22:21.621688 0438 043b 0447 0458 vborder 0
9309 00:22:21.621777 -hsync -vsync
9310 00:22:21.625220 Did detailed timing
9311 00:22:21.628680 Hex of detail: 000000000000000000000000000000000000
9312 00:22:21.631792 Manufacturer-specified data, tag 0
9313 00:22:21.638532 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9314 00:22:21.638637 ASCII string: InfoVision
9315 00:22:21.645342 Hex of detail: 000000fe00523134304e574635205248200a
9316 00:22:21.648602 ASCII string: R140NWF5 RH
9317 00:22:21.648694 Checksum
9318 00:22:21.648821 Checksum: 0xfb (valid)
9319 00:22:21.654969 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9320 00:22:21.658445 DSI data_rate: 832800000 bps
9321 00:22:21.661539 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9322 00:22:21.665038 anx7625_parse_edid: pixelclock(138800).
9323 00:22:21.671661 hactive(1920), hsync(48), hfp(24), hbp(88)
9324 00:22:21.675035 vactive(1080), vsync(12), vfp(3), vbp(17)
9325 00:22:21.678370 anx7625_dsi_config: config dsi.
9326 00:22:21.685102 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9327 00:22:21.697453 anx7625_dsi_config: success to config DSI
9328 00:22:21.700894 anx7625_dp_start: MIPI phy setup OK.
9329 00:22:21.704231 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9330 00:22:21.707272 mtk_ddp_mode_set invalid vrefresh 60
9331 00:22:21.710833 main_disp_path_setup
9332 00:22:21.710922 ovl_layer_smi_id_en
9333 00:22:21.714133 ovl_layer_smi_id_en
9334 00:22:21.714221 ccorr_config
9335 00:22:21.714294 aal_config
9336 00:22:21.717534 gamma_config
9337 00:22:21.717619 postmask_config
9338 00:22:21.721030 dither_config
9339 00:22:21.723916 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9340 00:22:21.730701 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9341 00:22:21.734168 Root Device init finished in 554 msecs
9342 00:22:21.734260 CPU_CLUSTER: 0 init
9343 00:22:21.743952 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9344 00:22:21.747274 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9345 00:22:21.750699 APU_MBOX 0x190000b0 = 0x10001
9346 00:22:21.754102 APU_MBOX 0x190001b0 = 0x10001
9347 00:22:21.757083 APU_MBOX 0x190005b0 = 0x10001
9348 00:22:21.760613 APU_MBOX 0x190006b0 = 0x10001
9349 00:22:21.764077 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9350 00:22:21.776475 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9351 00:22:21.788835 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9352 00:22:21.795683 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9353 00:22:21.807151 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9354 00:22:21.816514 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9355 00:22:21.819434 CPU_CLUSTER: 0 init finished in 81 msecs
9356 00:22:21.823128 Devices initialized
9357 00:22:21.826479 Show all devs... After init.
9358 00:22:21.826552 Root Device: enabled 1
9359 00:22:21.829740 CPU_CLUSTER: 0: enabled 1
9360 00:22:21.833225 CPU: 00: enabled 1
9361 00:22:21.836149 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9362 00:22:21.839978 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9363 00:22:21.843270 ELOG: NV offset 0x57f000 size 0x1000
9364 00:22:21.849649 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9365 00:22:21.856381 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9366 00:22:21.859882 ELOG: Event(17) added with size 13 at 2024-06-21 00:22:21 UTC
9367 00:22:21.862798 out: cmd=0x121: 03 db 21 01 00 00 00 00
9368 00:22:21.866838 in-header: 03 35 00 00 2c 00 00 00
9369 00:22:21.879792 in-data: 09 71 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9370 00:22:21.886491 ELOG: Event(A1) added with size 10 at 2024-06-21 00:22:21 UTC
9371 00:22:21.893351 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9372 00:22:21.899861 ELOG: Event(A0) added with size 9 at 2024-06-21 00:22:21 UTC
9373 00:22:21.903413 elog_add_boot_reason: Logged dev mode boot
9374 00:22:21.906331 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9375 00:22:21.909796 Finalize devices...
9376 00:22:21.909869 Devices finalized
9377 00:22:21.916305 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9378 00:22:21.919783 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9379 00:22:21.922952 in-header: 03 07 00 00 08 00 00 00
9380 00:22:21.926079 in-data: aa e4 47 04 13 02 00 00
9381 00:22:21.929459 Chrome EC: UHEPI supported
9382 00:22:21.936425 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9383 00:22:21.939411 in-header: 03 a9 00 00 08 00 00 00
9384 00:22:21.943060 in-data: 84 60 60 08 00 00 00 00
9385 00:22:21.946414 ELOG: Event(91) added with size 10 at 2024-06-21 00:22:21 UTC
9386 00:22:21.952476 Chrome EC: clear events_b mask to 0x0000000020004000
9387 00:22:21.959820 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9388 00:22:21.963297 in-header: 03 fd 00 00 00 00 00 00
9389 00:22:21.963371 in-data:
9390 00:22:21.969817 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9391 00:22:21.973287 Writing coreboot table at 0xffe64000
9392 00:22:21.976605 0. 000000000010a000-0000000000113fff: RAMSTAGE
9393 00:22:21.979943 1. 0000000040000000-00000000400fffff: RAM
9394 00:22:21.983307 2. 0000000040100000-000000004032afff: RAMSTAGE
9395 00:22:21.986266 3. 000000004032b000-00000000545fffff: RAM
9396 00:22:21.993062 4. 0000000054600000-000000005465ffff: BL31
9397 00:22:21.996570 5. 0000000054660000-00000000ffe63fff: RAM
9398 00:22:21.999769 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9399 00:22:22.006365 7. 0000000100000000-000000023fffffff: RAM
9400 00:22:22.006440 Passing 5 GPIOs to payload:
9401 00:22:22.012834 NAME | PORT | POLARITY | VALUE
9402 00:22:22.016442 EC in RW | 0x000000aa | low | undefined
9403 00:22:22.019776 EC interrupt | 0x00000005 | low | undefined
9404 00:22:22.026334 TPM interrupt | 0x000000ab | high | undefined
9405 00:22:22.029727 SD card detect | 0x00000011 | high | undefined
9406 00:22:22.036412 speaker enable | 0x00000093 | high | undefined
9407 00:22:22.039814 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9408 00:22:22.043001 in-header: 03 f9 00 00 02 00 00 00
9409 00:22:22.043077 in-data: 02 00
9410 00:22:22.046267 ADC[4]: Raw value=900295 ID=7
9411 00:22:22.049804 ADC[3]: Raw value=212810 ID=1
9412 00:22:22.049879 RAM Code: 0x71
9413 00:22:22.053035 ADC[6]: Raw value=74502 ID=0
9414 00:22:22.056274 ADC[5]: Raw value=212072 ID=1
9415 00:22:22.056350 SKU Code: 0x1
9416 00:22:22.063216 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum b619
9417 00:22:22.066591 coreboot table: 964 bytes.
9418 00:22:22.069971 IMD ROOT 0. 0xfffff000 0x00001000
9419 00:22:22.072933 IMD SMALL 1. 0xffffe000 0x00001000
9420 00:22:22.076210 RO MCACHE 2. 0xffffc000 0x00001104
9421 00:22:22.079836 CONSOLE 3. 0xfff7c000 0x00080000
9422 00:22:22.082917 FMAP 4. 0xfff7b000 0x00000452
9423 00:22:22.086290 TIME STAMP 5. 0xfff7a000 0x00000910
9424 00:22:22.089633 VBOOT WORK 6. 0xfff66000 0x00014000
9425 00:22:22.093004 RAMOOPS 7. 0xffe66000 0x00100000
9426 00:22:22.096361 COREBOOT 8. 0xffe64000 0x00002000
9427 00:22:22.096449 IMD small region:
9428 00:22:22.099369 IMD ROOT 0. 0xffffec00 0x00000400
9429 00:22:22.102900 VPD 1. 0xffffeb80 0x0000006c
9430 00:22:22.106248 MMC STATUS 2. 0xffffeb60 0x00000004
9431 00:22:22.112882 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9432 00:22:22.119296 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9433 00:22:22.158012 read SPI 0x3990ec 0x4f1b0: 34850 us, 9297 KB/s, 74.376 Mbps
9434 00:22:22.161648 Checking segment from ROM address 0x40100000
9435 00:22:22.164904 Checking segment from ROM address 0x4010001c
9436 00:22:22.171699 Loading segment from ROM address 0x40100000
9437 00:22:22.171775 code (compression=0)
9438 00:22:22.181721 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9439 00:22:22.187978 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9440 00:22:22.188054 it's not compressed!
9441 00:22:22.194798 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9442 00:22:22.198160 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9443 00:22:22.218414 Loading segment from ROM address 0x4010001c
9444 00:22:22.218491 Entry Point 0x80000000
9445 00:22:22.221893 Loaded segments
9446 00:22:22.225297 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9447 00:22:22.231903 Jumping to boot code at 0x80000000(0xffe64000)
9448 00:22:22.238653 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9449 00:22:22.245088 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9450 00:22:22.253063 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9451 00:22:22.256518 Checking segment from ROM address 0x40100000
9452 00:22:22.259791 Checking segment from ROM address 0x4010001c
9453 00:22:22.266344 Loading segment from ROM address 0x40100000
9454 00:22:22.266420 code (compression=1)
9455 00:22:22.273041 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9456 00:22:22.283143 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9457 00:22:22.283220 using LZMA
9458 00:22:22.291266 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9459 00:22:22.298350 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9460 00:22:22.301179 Loading segment from ROM address 0x4010001c
9461 00:22:22.301255 Entry Point 0x54601000
9462 00:22:22.304716 Loaded segments
9463 00:22:22.307681 NOTICE: MT8192 bl31_setup
9464 00:22:22.315017 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9465 00:22:22.318508 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9466 00:22:22.321669 WARNING: region 0:
9467 00:22:22.324845 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9468 00:22:22.324921 WARNING: region 1:
9469 00:22:22.331764 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9470 00:22:22.334826 WARNING: region 2:
9471 00:22:22.338268 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9472 00:22:22.341242 WARNING: region 3:
9473 00:22:22.344700 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9474 00:22:22.348193 WARNING: region 4:
9475 00:22:22.354730 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9476 00:22:22.354805 WARNING: region 5:
9477 00:22:22.358100 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9478 00:22:22.361237 WARNING: region 6:
9479 00:22:22.364649 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9480 00:22:22.368050 WARNING: region 7:
9481 00:22:22.371057 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9482 00:22:22.378062 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9483 00:22:22.381533 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9484 00:22:22.384888 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9485 00:22:22.391187 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9486 00:22:22.394612 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9487 00:22:22.397931 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9488 00:22:22.404336 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9489 00:22:22.407804 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9490 00:22:22.414520 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9491 00:22:22.417998 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9492 00:22:22.421280 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9493 00:22:22.428151 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9494 00:22:22.431468 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9495 00:22:22.434496 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9496 00:22:22.441395 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9497 00:22:22.444731 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9498 00:22:22.451439 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9499 00:22:22.454787 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9500 00:22:22.458301 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9501 00:22:22.464651 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9502 00:22:22.468061 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9503 00:22:22.471749 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9504 00:22:22.477988 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9505 00:22:22.481260 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9506 00:22:22.487793 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9507 00:22:22.491311 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9508 00:22:22.497996 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9509 00:22:22.501267 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9510 00:22:22.504614 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9511 00:22:22.511399 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9512 00:22:22.514507 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9513 00:22:22.517998 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9514 00:22:22.524375 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9515 00:22:22.527843 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9516 00:22:22.530975 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9517 00:22:22.534709 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9518 00:22:22.541323 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9519 00:22:22.544298 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9520 00:22:22.547628 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9521 00:22:22.551201 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9522 00:22:22.557739 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9523 00:22:22.561313 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9524 00:22:22.564908 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9525 00:22:22.567725 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9526 00:22:22.574683 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9527 00:22:22.577727 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9528 00:22:22.581106 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9529 00:22:22.584724 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9530 00:22:22.591213 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9531 00:22:22.594391 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9532 00:22:22.601278 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9533 00:22:22.604595 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9534 00:22:22.611310 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9535 00:22:22.614857 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9536 00:22:22.617700 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9537 00:22:22.624648 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9538 00:22:22.627983 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9539 00:22:22.634636 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9540 00:22:22.637786 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9541 00:22:22.644616 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9542 00:22:22.648074 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9543 00:22:22.651753 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9544 00:22:22.657827 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9545 00:22:22.661217 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9546 00:22:22.667893 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9547 00:22:22.671211 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9548 00:22:22.678172 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9549 00:22:22.681184 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9550 00:22:22.684670 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9551 00:22:22.691169 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9552 00:22:22.694648 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9553 00:22:22.701008 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9554 00:22:22.704584 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9555 00:22:22.711110 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9556 00:22:22.714624 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9557 00:22:22.721163 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9558 00:22:22.724248 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9559 00:22:22.727557 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9560 00:22:22.734499 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9561 00:22:22.738017 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9562 00:22:22.744407 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9563 00:22:22.747692 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9564 00:22:22.754184 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9565 00:22:22.757949 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9566 00:22:22.761478 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9567 00:22:22.767916 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9568 00:22:22.771296 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9569 00:22:22.777813 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9570 00:22:22.781272 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9571 00:22:22.784690 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9572 00:22:22.791230 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9573 00:22:22.794719 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9574 00:22:22.801205 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9575 00:22:22.804554 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9576 00:22:22.811021 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9577 00:22:22.814366 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9578 00:22:22.817672 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9579 00:22:22.824670 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9580 00:22:22.827556 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9581 00:22:22.831043 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9582 00:22:22.834449 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9583 00:22:22.840942 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9584 00:22:22.844317 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9585 00:22:22.851168 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9586 00:22:22.854211 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9587 00:22:22.857720 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9588 00:22:22.864420 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9589 00:22:22.867632 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9590 00:22:22.874966 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9591 00:22:22.877645 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9592 00:22:22.880944 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9593 00:22:22.887406 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9594 00:22:22.891079 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9595 00:22:22.897644 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9596 00:22:22.900635 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9597 00:22:22.903948 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9598 00:22:22.910896 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9599 00:22:22.914160 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9600 00:22:22.917655 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9601 00:22:22.924250 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9602 00:22:22.927566 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9603 00:22:22.930731 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9604 00:22:22.934259 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9605 00:22:22.940545 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9606 00:22:22.943990 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9607 00:22:22.947472 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9608 00:22:22.954361 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9609 00:22:22.957258 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9610 00:22:22.964381 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9611 00:22:22.967480 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9612 00:22:22.970652 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9613 00:22:22.977144 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9614 00:22:22.980855 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9615 00:22:22.983828 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9616 00:22:22.990888 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9617 00:22:22.994386 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9618 00:22:23.000843 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9619 00:22:23.003806 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9620 00:22:23.007196 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9621 00:22:23.013822 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9622 00:22:23.017209 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9623 00:22:23.023670 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9624 00:22:23.027111 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9625 00:22:23.030402 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9626 00:22:23.037161 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9627 00:22:23.040470 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9628 00:22:23.047226 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9629 00:22:23.050252 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9630 00:22:23.053784 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9631 00:22:23.060155 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9632 00:22:23.063470 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9633 00:22:23.066901 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9634 00:22:23.073569 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9635 00:22:23.077019 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9636 00:22:23.083907 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9637 00:22:23.087310 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9638 00:22:23.090247 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9639 00:22:23.097240 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9640 00:22:23.100149 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9641 00:22:23.106839 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9642 00:22:23.110247 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9643 00:22:23.113986 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9644 00:22:23.120638 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9645 00:22:23.123512 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9646 00:22:23.127049 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9647 00:22:23.133804 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9648 00:22:23.137232 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9649 00:22:23.143759 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9650 00:22:23.146793 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9651 00:22:23.150338 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9652 00:22:23.156818 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9653 00:22:23.160356 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9654 00:22:23.167114 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9655 00:22:23.170608 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9656 00:22:23.173519 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9657 00:22:23.180238 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9658 00:22:23.183357 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9659 00:22:23.190446 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9660 00:22:23.193160 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9661 00:22:23.196528 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9662 00:22:23.203144 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9663 00:22:23.206809 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9664 00:22:23.210113 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9665 00:22:23.216563 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9666 00:22:23.220130 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9667 00:22:23.227002 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9668 00:22:23.230330 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9669 00:22:23.233304 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9670 00:22:23.240247 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9671 00:22:23.243275 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9672 00:22:23.249957 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9673 00:22:23.253313 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9674 00:22:23.259827 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9675 00:22:23.263319 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9676 00:22:23.266852 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9677 00:22:23.273405 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9678 00:22:23.276891 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9679 00:22:23.283253 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9680 00:22:23.286786 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9681 00:22:23.289882 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9682 00:22:23.296531 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9683 00:22:23.299749 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9684 00:22:23.306245 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9685 00:22:23.309821 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9686 00:22:23.316445 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9687 00:22:23.319486 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9688 00:22:23.323072 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9689 00:22:23.329547 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9690 00:22:23.333109 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9691 00:22:23.339703 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9692 00:22:23.343174 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9693 00:22:23.346206 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9694 00:22:23.353247 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9695 00:22:23.356370 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9696 00:22:23.363037 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9697 00:22:23.366392 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9698 00:22:23.369874 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9699 00:22:23.376122 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9700 00:22:23.379635 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9701 00:22:23.386134 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9702 00:22:23.389648 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9703 00:22:23.396256 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9704 00:22:23.399516 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9705 00:22:23.402566 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9706 00:22:23.409392 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9707 00:22:23.412765 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9708 00:22:23.419305 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9709 00:22:23.422883 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9710 00:22:23.425842 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9711 00:22:23.432883 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9712 00:22:23.435926 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9713 00:22:23.439430 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9714 00:22:23.442843 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9715 00:22:23.446173 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9716 00:22:23.452997 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9717 00:22:23.455896 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9718 00:22:23.462602 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9719 00:22:23.465879 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9720 00:22:23.469525 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9721 00:22:23.475875 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9722 00:22:23.479162 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9723 00:22:23.486261 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9724 00:22:23.489234 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9725 00:22:23.492756 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9726 00:22:23.499334 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9727 00:22:23.502765 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9728 00:22:23.506186 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9729 00:22:23.512905 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9730 00:22:23.515899 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9731 00:22:23.519179 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9732 00:22:23.525923 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9733 00:22:23.528945 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9734 00:22:23.535716 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9735 00:22:23.539279 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9736 00:22:23.542312 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9737 00:22:23.549040 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9738 00:22:23.552563 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9739 00:22:23.555598 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9740 00:22:23.562466 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9741 00:22:23.565946 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9742 00:22:23.569366 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9743 00:22:23.575522 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9744 00:22:23.578835 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9745 00:22:23.582204 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9746 00:22:23.588895 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9747 00:22:23.592319 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9748 00:22:23.598898 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9749 00:22:23.602373 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9750 00:22:23.605992 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9751 00:22:23.608906 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9752 00:22:23.615739 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9753 00:22:23.618968 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9754 00:22:23.622486 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9755 00:22:23.625874 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9756 00:22:23.632549 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9757 00:22:23.635455 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9758 00:22:23.639040 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9759 00:22:23.642706 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9760 00:22:23.646217 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9761 00:22:23.652636 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9762 00:22:23.655669 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9763 00:22:23.658883 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9764 00:22:23.665771 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9765 00:22:23.669024 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9766 00:22:23.675850 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9767 00:22:23.678830 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9768 00:22:23.685585 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9769 00:22:23.688664 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9770 00:22:23.692043 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9771 00:22:23.698715 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9772 00:22:23.702463 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9773 00:22:23.705506 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9774 00:22:23.712045 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9775 00:22:23.715594 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9776 00:22:23.721970 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9777 00:22:23.725241 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9778 00:22:23.732157 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9779 00:22:23.735261 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9780 00:22:23.738560 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9781 00:22:23.745062 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9782 00:22:23.748608 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9783 00:22:23.755402 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9784 00:22:23.758861 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9785 00:22:23.762113 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9786 00:22:23.768547 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9787 00:22:23.771650 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9788 00:22:23.778321 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9789 00:22:23.781929 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9790 00:22:23.784869 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9791 00:22:23.791722 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9792 00:22:23.795060 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9793 00:22:23.801626 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9794 00:22:23.805142 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9795 00:22:23.811781 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9796 00:22:23.814792 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9797 00:22:23.818237 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9798 00:22:23.824908 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9799 00:22:23.828025 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9800 00:22:23.834852 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9801 00:22:23.838335 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9802 00:22:23.841240 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9803 00:22:23.848148 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9804 00:22:23.851563 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9805 00:22:23.858064 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9806 00:22:23.861461 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9807 00:22:23.864611 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9808 00:22:23.871235 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9809 00:22:23.874416 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9810 00:22:23.880851 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9811 00:22:23.884142 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9812 00:22:23.887538 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9813 00:22:23.894478 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9814 00:22:23.897944 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9815 00:22:23.904649 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9816 00:22:23.907621 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9817 00:22:23.914396 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9818 00:22:23.917959 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9819 00:22:23.921007 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9820 00:22:23.927542 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9821 00:22:23.930938 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9822 00:22:23.937825 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9823 00:22:23.941176 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9824 00:22:23.944734 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9825 00:22:23.951214 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9826 00:22:23.954524 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9827 00:22:23.957910 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9828 00:22:23.964325 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9829 00:22:23.967826 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9830 00:22:23.974281 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9831 00:22:23.977724 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9832 00:22:23.984745 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9833 00:22:23.987842 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9834 00:22:23.991110 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9835 00:22:23.997821 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9836 00:22:24.001137 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9837 00:22:24.007782 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9838 00:22:24.010736 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9839 00:22:24.017660 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9840 00:22:24.020896 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9841 00:22:24.024288 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9842 00:22:24.030908 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9843 00:22:24.034283 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9844 00:22:24.040845 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9845 00:22:24.044326 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9846 00:22:24.050967 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9847 00:22:24.053981 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9848 00:22:24.057562 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9849 00:22:24.063995 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9850 00:22:24.067274 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9851 00:22:24.074026 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9852 00:22:24.077614 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9853 00:22:24.083967 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9854 00:22:24.087002 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9855 00:22:24.090877 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9856 00:22:24.097223 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9857 00:22:24.100814 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9858 00:22:24.107243 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9859 00:22:24.110763 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9860 00:22:24.117291 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9861 00:22:24.120725 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9862 00:22:24.127403 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9863 00:22:24.130814 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9864 00:22:24.133826 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9865 00:22:24.140674 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9866 00:22:24.143603 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9867 00:22:24.150333 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9868 00:22:24.153722 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9869 00:22:24.157168 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9870 00:22:24.163796 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9871 00:22:24.167259 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9872 00:22:24.173869 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9873 00:22:24.177137 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9874 00:22:24.183755 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9875 00:22:24.187072 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9876 00:22:24.190513 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9877 00:22:24.197230 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9878 00:22:24.200782 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9879 00:22:24.207497 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9880 00:22:24.210571 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9881 00:22:24.217243 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9882 00:22:24.220892 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9883 00:22:24.223931 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9884 00:22:24.230456 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9885 00:22:24.233822 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9886 00:22:24.240456 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9887 00:22:24.243903 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9888 00:22:24.250753 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9889 00:22:24.253929 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9890 00:22:24.260939 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9891 00:22:24.263794 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9892 00:22:24.267556 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9893 00:22:24.274001 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9894 00:22:24.277383 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9895 00:22:24.283928 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9896 00:22:24.287248 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9897 00:22:24.293817 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9898 00:22:24.297273 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9899 00:22:24.303756 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9900 00:22:24.307168 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9901 00:22:24.313669 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9902 00:22:24.316948 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9903 00:22:24.323774 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9904 00:22:24.326909 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9905 00:22:24.333754 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9906 00:22:24.337221 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9907 00:22:24.343740 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9908 00:22:24.346844 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9909 00:22:24.353301 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9910 00:22:24.356947 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9911 00:22:24.363334 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9912 00:22:24.366682 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9913 00:22:24.373683 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9914 00:22:24.376792 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9915 00:22:24.383536 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9916 00:22:24.387115 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9917 00:22:24.390406 INFO: [APUAPC] vio 0
9918 00:22:24.393437 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9919 00:22:24.400184 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9920 00:22:24.403792 INFO: [APUAPC] D0_APC_0: 0x400510
9921 00:22:24.403868 INFO: [APUAPC] D0_APC_1: 0x0
9922 00:22:24.406997 INFO: [APUAPC] D0_APC_2: 0x1540
9923 00:22:24.410405 INFO: [APUAPC] D0_APC_3: 0x0
9924 00:22:24.413462 INFO: [APUAPC] D1_APC_0: 0xffffffff
9925 00:22:24.417070 INFO: [APUAPC] D1_APC_1: 0xffffffff
9926 00:22:24.420442 INFO: [APUAPC] D1_APC_2: 0x3fffff
9927 00:22:24.423700 INFO: [APUAPC] D1_APC_3: 0x0
9928 00:22:24.426765 INFO: [APUAPC] D2_APC_0: 0xffffffff
9929 00:22:24.430107 INFO: [APUAPC] D2_APC_1: 0xffffffff
9930 00:22:24.433800 INFO: [APUAPC] D2_APC_2: 0x3fffff
9931 00:22:24.436694 INFO: [APUAPC] D2_APC_3: 0x0
9932 00:22:24.440216 INFO: [APUAPC] D3_APC_0: 0xffffffff
9933 00:22:24.443683 INFO: [APUAPC] D3_APC_1: 0xffffffff
9934 00:22:24.447239 INFO: [APUAPC] D3_APC_2: 0x3fffff
9935 00:22:24.450299 INFO: [APUAPC] D3_APC_3: 0x0
9936 00:22:24.453504 INFO: [APUAPC] D4_APC_0: 0xffffffff
9937 00:22:24.457055 INFO: [APUAPC] D4_APC_1: 0xffffffff
9938 00:22:24.460248 INFO: [APUAPC] D4_APC_2: 0x3fffff
9939 00:22:24.463484 INFO: [APUAPC] D4_APC_3: 0x0
9940 00:22:24.466883 INFO: [APUAPC] D5_APC_0: 0xffffffff
9941 00:22:24.470352 INFO: [APUAPC] D5_APC_1: 0xffffffff
9942 00:22:24.473858 INFO: [APUAPC] D5_APC_2: 0x3fffff
9943 00:22:24.476836 INFO: [APUAPC] D5_APC_3: 0x0
9944 00:22:24.480202 INFO: [APUAPC] D6_APC_0: 0xffffffff
9945 00:22:24.483822 INFO: [APUAPC] D6_APC_1: 0xffffffff
9946 00:22:24.486834 INFO: [APUAPC] D6_APC_2: 0x3fffff
9947 00:22:24.490306 INFO: [APUAPC] D6_APC_3: 0x0
9948 00:22:24.493643 INFO: [APUAPC] D7_APC_0: 0xffffffff
9949 00:22:24.496815 INFO: [APUAPC] D7_APC_1: 0xffffffff
9950 00:22:24.500239 INFO: [APUAPC] D7_APC_2: 0x3fffff
9951 00:22:24.500316 INFO: [APUAPC] D7_APC_3: 0x0
9952 00:22:24.506732 INFO: [APUAPC] D8_APC_0: 0xffffffff
9953 00:22:24.510085 INFO: [APUAPC] D8_APC_1: 0xffffffff
9954 00:22:24.513477 INFO: [APUAPC] D8_APC_2: 0x3fffff
9955 00:22:24.513554 INFO: [APUAPC] D8_APC_3: 0x0
9956 00:22:24.516894 INFO: [APUAPC] D9_APC_0: 0xffffffff
9957 00:22:24.520015 INFO: [APUAPC] D9_APC_1: 0xffffffff
9958 00:22:24.523537 INFO: [APUAPC] D9_APC_2: 0x3fffff
9959 00:22:24.527206 INFO: [APUAPC] D9_APC_3: 0x0
9960 00:22:24.530085 INFO: [APUAPC] D10_APC_0: 0xffffffff
9961 00:22:24.533162 INFO: [APUAPC] D10_APC_1: 0xffffffff
9962 00:22:24.536722 INFO: [APUAPC] D10_APC_2: 0x3fffff
9963 00:22:24.540116 INFO: [APUAPC] D10_APC_3: 0x0
9964 00:22:24.543135 INFO: [APUAPC] D11_APC_0: 0xffffffff
9965 00:22:24.546753 INFO: [APUAPC] D11_APC_1: 0xffffffff
9966 00:22:24.553125 INFO: [APUAPC] D11_APC_2: 0x3fffff
9967 00:22:24.553202 INFO: [APUAPC] D11_APC_3: 0x0
9968 00:22:24.556850 INFO: [APUAPC] D12_APC_0: 0xffffffff
9969 00:22:24.563466 INFO: [APUAPC] D12_APC_1: 0xffffffff
9970 00:22:24.566704 INFO: [APUAPC] D12_APC_2: 0x3fffff
9971 00:22:24.566782 INFO: [APUAPC] D12_APC_3: 0x0
9972 00:22:24.569777 INFO: [APUAPC] D13_APC_0: 0xffffffff
9973 00:22:24.576750 INFO: [APUAPC] D13_APC_1: 0xffffffff
9974 00:22:24.576828 INFO: [APUAPC] D13_APC_2: 0x3fffff
9975 00:22:24.579914 INFO: [APUAPC] D13_APC_3: 0x0
9976 00:22:24.583278 INFO: [APUAPC] D14_APC_0: 0xffffffff
9977 00:22:24.589750 INFO: [APUAPC] D14_APC_1: 0xffffffff
9978 00:22:24.593408 INFO: [APUAPC] D14_APC_2: 0x3fffff
9979 00:22:24.593485 INFO: [APUAPC] D14_APC_3: 0x0
9980 00:22:24.596708 INFO: [APUAPC] D15_APC_0: 0xffffffff
9981 00:22:24.603166 INFO: [APUAPC] D15_APC_1: 0xffffffff
9982 00:22:24.606704 INFO: [APUAPC] D15_APC_2: 0x3fffff
9983 00:22:24.606781 INFO: [APUAPC] D15_APC_3: 0x0
9984 00:22:24.610028 INFO: [APUAPC] APC_CON: 0x4
9985 00:22:24.613070 INFO: [NOCDAPC] D0_APC_0: 0x0
9986 00:22:24.616534 INFO: [NOCDAPC] D0_APC_1: 0x0
9987 00:22:24.619902 INFO: [NOCDAPC] D1_APC_0: 0x0
9988 00:22:24.623405 INFO: [NOCDAPC] D1_APC_1: 0xfff
9989 00:22:24.626782 INFO: [NOCDAPC] D2_APC_0: 0x0
9990 00:22:24.630065 INFO: [NOCDAPC] D2_APC_1: 0xfff
9991 00:22:24.633029 INFO: [NOCDAPC] D3_APC_0: 0x0
9992 00:22:24.633105 INFO: [NOCDAPC] D3_APC_1: 0xfff
9993 00:22:24.636464 INFO: [NOCDAPC] D4_APC_0: 0x0
9994 00:22:24.640159 INFO: [NOCDAPC] D4_APC_1: 0xfff
9995 00:22:24.643361 INFO: [NOCDAPC] D5_APC_0: 0x0
9996 00:22:24.646676 INFO: [NOCDAPC] D5_APC_1: 0xfff
9997 00:22:24.649770 INFO: [NOCDAPC] D6_APC_0: 0x0
9998 00:22:24.652989 INFO: [NOCDAPC] D6_APC_1: 0xfff
9999 00:22:24.656616 INFO: [NOCDAPC] D7_APC_0: 0x0
10000 00:22:24.659864 INFO: [NOCDAPC] D7_APC_1: 0xfff
10001 00:22:24.663331 INFO: [NOCDAPC] D8_APC_0: 0x0
10002 00:22:24.663423 INFO: [NOCDAPC] D8_APC_1: 0xfff
10003 00:22:24.666548 INFO: [NOCDAPC] D9_APC_0: 0x0
10004 00:22:24.670110 INFO: [NOCDAPC] D9_APC_1: 0xfff
10005 00:22:24.673060 INFO: [NOCDAPC] D10_APC_0: 0x0
10006 00:22:24.676343 INFO: [NOCDAPC] D10_APC_1: 0xfff
10007 00:22:24.679903 INFO: [NOCDAPC] D11_APC_0: 0x0
10008 00:22:24.683241 INFO: [NOCDAPC] D11_APC_1: 0xfff
10009 00:22:24.686344 INFO: [NOCDAPC] D12_APC_0: 0x0
10010 00:22:24.689941 INFO: [NOCDAPC] D12_APC_1: 0xfff
10011 00:22:24.693018 INFO: [NOCDAPC] D13_APC_0: 0x0
10012 00:22:24.696582 INFO: [NOCDAPC] D13_APC_1: 0xfff
10013 00:22:24.700116 INFO: [NOCDAPC] D14_APC_0: 0x0
10014 00:22:24.703307 INFO: [NOCDAPC] D14_APC_1: 0xfff
10015 00:22:24.703421 INFO: [NOCDAPC] D15_APC_0: 0x0
10016 00:22:24.706386 INFO: [NOCDAPC] D15_APC_1: 0xfff
10017 00:22:24.709762 INFO: [NOCDAPC] APC_CON: 0x4
10018 00:22:24.713353 INFO: [APUAPC] set_apusys_apc done
10019 00:22:24.716639 INFO: [DEVAPC] devapc_init done
10020 00:22:24.723405 INFO: GICv3 without legacy support detected.
10021 00:22:24.726430 INFO: ARM GICv3 driver initialized in EL3
10022 00:22:24.729961 INFO: Maximum SPI INTID supported: 639
10023 00:22:24.733214 INFO: BL31: Initializing runtime services
10024 00:22:24.739760 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10025 00:22:24.743136 INFO: SPM: enable CPC mode
10026 00:22:24.746670 INFO: mcdi ready for mcusys-off-idle and system suspend
10027 00:22:24.752791 INFO: BL31: Preparing for EL3 exit to normal world
10028 00:22:24.756223 INFO: Entry point address = 0x80000000
10029 00:22:24.756301 INFO: SPSR = 0x8
10030 00:22:24.762837
10031 00:22:24.762915
10032 00:22:24.763008
10033 00:22:24.766085 Starting depthcharge on Spherion...
10034 00:22:24.766162
10035 00:22:24.766221 Wipe memory regions:
10036 00:22:24.766276
10037 00:22:24.766944 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10038 00:22:24.767041 start: 2.2.4 bootloader-commands (timeout 00:04:20) [common]
10039 00:22:24.767118 Setting prompt string to ['asurada:']
10040 00:22:24.767189 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:20)
10041 00:22:24.769493 [0x00000040000000, 0x00000054600000)
10042 00:22:24.891687
10043 00:22:24.891886 [0x00000054660000, 0x00000080000000)
10044 00:22:25.152552
10045 00:22:25.152669 [0x000000821a7280, 0x000000ffe64000)
10046 00:22:25.896991
10047 00:22:25.897124 [0x00000100000000, 0x00000240000000)
10048 00:22:27.786777
10049 00:22:27.789694 Initializing XHCI USB controller at 0x11200000.
10050 00:22:28.829300
10051 00:22:28.832423 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10052 00:22:28.832504
10053 00:22:28.832563
10054 00:22:28.832830 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10056 00:22:28.933111 asurada: tftpboot 192.168.201.1 14479150/tftp-deploy-4y6o0n8e/kernel/image.itb 14479150/tftp-deploy-4y6o0n8e/kernel/cmdline
10057 00:22:28.933296 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10058 00:22:28.933393 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:16)
10059 00:22:28.937906 tftpboot 192.168.201.1 14479150/tftp-deploy-4y6o0n8e/kernel/image.ittp-deploy-4y6o0n8e/kernel/cmdline
10060 00:22:28.937981
10061 00:22:28.938040 Waiting for link
10062 00:22:29.095790
10063 00:22:29.095901 R8152: Initializing
10064 00:22:29.095962
10065 00:22:29.099102 Version 9 (ocp_data = 6010)
10066 00:22:29.099171
10067 00:22:29.102575 R8152: Done initializing
10068 00:22:29.102641
10069 00:22:29.102704 Adding net device
10070 00:22:31.050641
10071 00:22:31.051112 done.
10072 00:22:31.051499
10073 00:22:31.051902 MAC: 00:e0:4c:72:2d:d6
10074 00:22:31.052230
10075 00:22:31.053958 Sending DHCP discover... done.
10076 00:22:31.054469
10077 00:22:31.057370 Waiting for reply... done.
10078 00:22:31.057806
10079 00:22:31.060430 Sending DHCP request... done.
10080 00:22:31.060917
10081 00:22:31.064455 Waiting for reply... done.
10082 00:22:31.064930
10083 00:22:31.065276 My ip is 192.168.201.21
10084 00:22:31.065590
10085 00:22:31.067454 The DHCP server ip is 192.168.201.1
10086 00:22:31.067878
10087 00:22:31.074000 TFTP server IP predefined by user: 192.168.201.1
10088 00:22:31.074432
10089 00:22:31.080641 Bootfile predefined by user: 14479150/tftp-deploy-4y6o0n8e/kernel/image.itb
10090 00:22:31.081107
10091 00:22:31.083854 Sending tftp read request... done.
10092 00:22:31.084280
10093 00:22:31.090632 Waiting for the transfer...
10094 00:22:31.091205
10095 00:22:31.382849 00000000 ################################################################
10096 00:22:31.382992
10097 00:22:31.670488 00080000 ################################################################
10098 00:22:31.670615
10099 00:22:31.960028 00100000 ################################################################
10100 00:22:31.960176
10101 00:22:32.255761 00180000 ################################################################
10102 00:22:32.255899
10103 00:22:32.524250 00200000 ################################################################
10104 00:22:32.524402
10105 00:22:32.798301 00280000 ################################################################
10106 00:22:32.798426
10107 00:22:33.069334 00300000 ################################################################
10108 00:22:33.069467
10109 00:22:33.333486 00380000 ################################################################
10110 00:22:33.333614
10111 00:22:33.600421 00400000 ################################################################
10112 00:22:33.600535
10113 00:22:33.857245 00480000 ################################################################
10114 00:22:33.857363
10115 00:22:34.118657 00500000 ################################################################
10116 00:22:34.118790
10117 00:22:34.383980 00580000 ################################################################
10118 00:22:34.384092
10119 00:22:34.631460 00600000 ################################################################
10120 00:22:34.631575
10121 00:22:34.886659 00680000 ################################################################
10122 00:22:34.886773
10123 00:22:35.139765 00700000 ################################################################
10124 00:22:35.139897
10125 00:22:35.400674 00780000 ################################################################
10126 00:22:35.400815
10127 00:22:35.652300 00800000 ################################################################
10128 00:22:35.652418
10129 00:22:35.898334 00880000 ################################################################
10130 00:22:35.898458
10131 00:22:36.148603 00900000 ################################################################
10132 00:22:36.148768
10133 00:22:36.398516 00980000 ################################################################
10134 00:22:36.398623
10135 00:22:36.648882 00a00000 ################################################################
10136 00:22:36.649093
10137 00:22:36.900542 00a80000 ################################################################
10138 00:22:36.900687
10139 00:22:37.149344 00b00000 ################################################################
10140 00:22:37.149460
10141 00:22:37.414505 00b80000 ################################################################
10142 00:22:37.414652
10143 00:22:37.663715 00c00000 ################################################################
10144 00:22:37.663856
10145 00:22:37.914964 00c80000 ################################################################
10146 00:22:37.915105
10147 00:22:38.173514 00d00000 ################################################################
10148 00:22:38.173626
10149 00:22:38.435081 00d80000 ################################################################
10150 00:22:38.435190
10151 00:22:38.704886 00e00000 ################################################################
10152 00:22:38.704998
10153 00:22:38.968146 00e80000 ################################################################
10154 00:22:38.968260
10155 00:22:39.224443 00f00000 ################################################################
10156 00:22:39.224556
10157 00:22:39.488041 00f80000 ################################################################
10158 00:22:39.488176
10159 00:22:39.755106 01000000 ################################################################
10160 00:22:39.755231
10161 00:22:40.012817 01080000 ################################################################
10162 00:22:40.012933
10163 00:22:40.286662 01100000 ################################################################
10164 00:22:40.286773
10165 00:22:40.556550 01180000 ################################################################
10166 00:22:40.556701
10167 00:22:40.802491 01200000 ################################################################
10168 00:22:40.802606
10169 00:22:41.038428 01280000 ################################################################
10170 00:22:41.038544
10171 00:22:41.284650 01300000 ################################################################
10172 00:22:41.284814
10173 00:22:41.548319 01380000 ################################################################
10174 00:22:41.548425
10175 00:22:41.824041 01400000 ################################################################
10176 00:22:41.824154
10177 00:22:42.074032 01480000 ################################################################
10178 00:22:42.074169
10179 00:22:42.328766 01500000 ################################################################
10180 00:22:42.328881
10181 00:22:42.582992 01580000 ################################################################
10182 00:22:42.583132
10183 00:22:42.835532 01600000 ################################################################
10184 00:22:42.835684
10185 00:22:43.083454 01680000 ################################################################
10186 00:22:43.083578
10187 00:22:43.330416 01700000 ################################################################
10188 00:22:43.330529
10189 00:22:43.580855 01780000 ################################################################
10190 00:22:43.580985
10191 00:22:43.841920 01800000 ################################################################
10192 00:22:43.842056
10193 00:22:44.095506 01880000 ################################################################
10194 00:22:44.095651
10195 00:22:44.361172 01900000 ################################################################
10196 00:22:44.361291
10197 00:22:44.613331 01980000 ################################################################
10198 00:22:44.613447
10199 00:22:44.875713 01a00000 ################################################################
10200 00:22:44.875829
10201 00:22:45.123472 01a80000 ################################################################
10202 00:22:45.123600
10203 00:22:45.369852 01b00000 ################################################################
10204 00:22:45.369971
10205 00:22:45.618631 01b80000 ################################################################
10206 00:22:45.618780
10207 00:22:45.867943 01c00000 ################################################################
10208 00:22:45.868062
10209 00:22:46.124531 01c80000 ################################################################
10210 00:22:46.124653
10211 00:22:46.368887 01d00000 ################################################################
10212 00:22:46.369038
10213 00:22:46.603074 01d80000 ################################################################
10214 00:22:46.603190
10215 00:22:46.846482 01e00000 ################################################################
10216 00:22:46.846632
10217 00:22:47.092938 01e80000 ################################################################
10218 00:22:47.093055
10219 00:22:47.352143 01f00000 ################################################################
10220 00:22:47.352257
10221 00:22:47.603824 01f80000 ################################################################
10222 00:22:47.603968
10223 00:22:47.855428 02000000 ################################################################
10224 00:22:47.855574
10225 00:22:48.104186 02080000 ################################################################
10226 00:22:48.104336
10227 00:22:48.353642 02100000 ################################################################
10228 00:22:48.353777
10229 00:22:48.604890 02180000 ################################################################
10230 00:22:48.605031
10231 00:22:48.860395 02200000 ################################################################
10232 00:22:48.860532
10233 00:22:49.109541 02280000 ################################################################
10234 00:22:49.109665
10235 00:22:49.358209 02300000 ################################################################
10236 00:22:49.358348
10237 00:22:49.611426 02380000 ################################################################
10238 00:22:49.611582
10239 00:22:49.873331 02400000 ################################################################
10240 00:22:49.873467
10241 00:22:50.130007 02480000 ################################################################
10242 00:22:50.130143
10243 00:22:50.375688 02500000 ################################################################
10244 00:22:50.375840
10245 00:22:50.624355 02580000 ################################################################
10246 00:22:50.624516
10247 00:22:50.875313 02600000 ################################################################
10248 00:22:50.875455
10249 00:22:51.125237 02680000 ################################################################
10250 00:22:51.125380
10251 00:22:51.390243 02700000 ################################################################
10252 00:22:51.390378
10253 00:22:51.646057 02780000 ################################################################
10254 00:22:51.646168
10255 00:22:51.902422 02800000 ################################################################
10256 00:22:51.902559
10257 00:22:52.152021 02880000 ################################################################
10258 00:22:52.152156
10259 00:22:52.397811 02900000 ################################################################
10260 00:22:52.397974
10261 00:22:52.661265 02980000 ################################################################
10262 00:22:52.661398
10263 00:22:52.937115 02a00000 ################################################################
10264 00:22:52.937226
10265 00:22:53.194963 02a80000 ################################################################
10266 00:22:53.195069
10267 00:22:53.470664 02b00000 ################################################################
10268 00:22:53.470782
10269 00:22:53.760241 02b80000 ################################################################
10270 00:22:53.760355
10271 00:22:54.022251 02c00000 ################################################################
10272 00:22:54.022358
10273 00:22:54.289245 02c80000 ################################################################
10274 00:22:54.289357
10275 00:22:54.559678 02d00000 ################################################################
10276 00:22:54.559789
10277 00:22:54.823818 02d80000 ################################################################
10278 00:22:54.823946
10279 00:22:55.081890 02e00000 ################################################################
10280 00:22:55.082026
10281 00:22:55.344325 02e80000 ################################################################
10282 00:22:55.344474
10283 00:22:55.625844 02f00000 ################################################################
10284 00:22:55.625981
10285 00:22:55.896450 02f80000 ################################################################
10286 00:22:55.896587
10287 00:22:56.158286 03000000 ################################################################
10288 00:22:56.158407
10289 00:22:56.428822 03080000 ################################################################
10290 00:22:56.428937
10291 00:22:56.686906 03100000 ################################################################
10292 00:22:56.687026
10293 00:22:56.939862 03180000 ################################################################
10294 00:22:56.939974
10295 00:22:57.187486 03200000 ################################################################
10296 00:22:57.187628
10297 00:22:57.437468 03280000 ################################################################
10298 00:22:57.437626
10299 00:22:57.695085 03300000 ################################################################
10300 00:22:57.695230
10301 00:22:57.971223 03380000 ################################################################
10302 00:22:57.971342
10303 00:22:58.270496 03400000 ################################################################
10304 00:22:58.270605
10305 00:22:58.562948 03480000 ################################################################
10306 00:22:58.563075
10307 00:22:58.952241 03500000 ################################################################
10308 00:22:58.952379
10309 00:22:59.281749 03580000 ################################################################
10310 00:22:59.281862
10311 00:22:59.574629 03600000 ################################################################
10312 00:22:59.574763
10313 00:22:59.857762 03680000 ################################################################
10314 00:22:59.857876
10315 00:23:00.151386 03700000 ################################################################
10316 00:23:00.151497
10317 00:23:00.444177 03780000 ################################################################
10318 00:23:00.444287
10319 00:23:00.742980 03800000 ################################################################
10320 00:23:00.743114
10321 00:23:01.025958 03880000 ################################################################
10322 00:23:01.026082
10323 00:23:01.317614 03900000 ################################################################
10324 00:23:01.317756
10325 00:23:01.591028 03980000 ################################################################
10326 00:23:01.591142
10327 00:23:01.860660 03a00000 ################################################################
10328 00:23:01.860836
10329 00:23:02.127365 03a80000 ################################################################
10330 00:23:02.127498
10331 00:23:02.385576 03b00000 ################################################################
10332 00:23:02.385687
10333 00:23:02.643947 03b80000 ################################################################
10334 00:23:02.644061
10335 00:23:02.901849 03c00000 ################################################################
10336 00:23:02.901963
10337 00:23:03.175098 03c80000 ################################################################
10338 00:23:03.175232
10339 00:23:03.456822 03d00000 ################################################################
10340 00:23:03.456933
10341 00:23:03.724881 03d80000 ################################################################
10342 00:23:03.724994
10343 00:23:03.879312 03e00000 ####################################### done.
10344 00:23:03.879418
10345 00:23:03.882760 The bootfile was 65324002 bytes long.
10346 00:23:03.882850
10347 00:23:03.886242 Sending tftp read request... done.
10348 00:23:03.886678
10349 00:23:03.887016 Waiting for the transfer...
10350 00:23:03.889817
10351 00:23:03.890364 00000000 # done.
10352 00:23:03.890823
10353 00:23:03.896179 Command line loaded dynamically from TFTP file: 14479150/tftp-deploy-4y6o0n8e/kernel/cmdline
10354 00:23:03.896619
10355 00:23:03.909495 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10356 00:23:03.912487
10357 00:23:03.913165 Loading FIT.
10358 00:23:03.913674
10359 00:23:03.915928 Image ramdisk-1 has 52149824 bytes.
10360 00:23:03.916443
10361 00:23:03.919414 Image fdt-1 has 47258 bytes.
10362 00:23:03.919984
10363 00:23:03.922515 Image kernel-1 has 13124896 bytes.
10364 00:23:03.922949
10365 00:23:03.929287 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10366 00:23:03.929725
10367 00:23:03.948835 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10368 00:23:03.949354
10369 00:23:03.952358 Choosing best match conf-1 for compat google,spherion-rev2.
10370 00:23:03.957004
10371 00:23:03.961821 Connected to device vid:did:rid of 1ae0:0028:00
10372 00:23:03.969462
10373 00:23:03.973272 tpm_get_response: command 0x17b, return code 0x0
10374 00:23:03.973829
10375 00:23:03.976047 ec_init: CrosEC protocol v3 supported (256, 248)
10376 00:23:03.980370
10377 00:23:03.983815 tpm_cleanup: add release locality here.
10378 00:23:03.984252
10379 00:23:03.984602 Shutting down all USB controllers.
10380 00:23:03.984969
10381 00:23:03.987062 Removing current net device
10382 00:23:03.987495
10383 00:23:03.993508 Exiting depthcharge with code 4 at timestamp: 68580092
10384 00:23:03.993945
10385 00:23:03.997033 LZMA decompressing kernel-1 to 0x821a6718
10386 00:23:03.997470
10387 00:23:04.000302 LZMA decompressing kernel-1 to 0x40000000
10388 00:23:05.616568
10389 00:23:05.617115 jumping to kernel
10390 00:23:05.619225 end: 2.2.4 bootloader-commands (duration 00:00:41) [common]
10391 00:23:05.619726 start: 2.2.5 auto-login-action (timeout 00:03:39) [common]
10392 00:23:05.620096 Setting prompt string to ['Linux version [0-9]']
10393 00:23:05.620446 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10394 00:23:05.620840 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10395 00:23:05.698934
10396 00:23:05.701760 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10397 00:23:05.705676 start: 2.2.5.1 login-action (timeout 00:03:39) [common]
10398 00:23:05.706197 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10399 00:23:05.706569 Setting prompt string to []
10400 00:23:05.706956 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10401 00:23:05.707303 Using line separator: #'\n'#
10402 00:23:05.707835 No login prompt set.
10403 00:23:05.708347 Parsing kernel messages
10404 00:23:05.708929 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10405 00:23:05.709665 [login-action] Waiting for messages, (timeout 00:03:39)
10406 00:23:05.710199 Waiting using forced prompt support (timeout 00:01:50)
10407 00:23:05.725196 [ 0.000000] Linux version 6.1.94-cip23 (KernelCI@build-j239242-arm64-gcc-10-defconfig-arm64-chromebook-c5lwc) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Jun 21 00:04:56 UTC 2024
10408 00:23:05.727997 [ 0.000000] random: crng init done
10409 00:23:05.734797 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10410 00:23:05.738365 [ 0.000000] efi: UEFI not found.
10411 00:23:05.744896 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10412 00:23:05.754575 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10413 00:23:05.764456 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10414 00:23:05.771191 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10415 00:23:05.777436 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10416 00:23:05.784033 [ 0.000000] printk: bootconsole [mtk8250] enabled
10417 00:23:05.790784 [ 0.000000] NUMA: No NUMA configuration found
10418 00:23:05.797063 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10419 00:23:05.804013 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10420 00:23:05.804420 [ 0.000000] Zone ranges:
10421 00:23:05.810474 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10422 00:23:05.813673 [ 0.000000] DMA32 empty
10423 00:23:05.820441 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10424 00:23:05.823894 [ 0.000000] Movable zone start for each node
10425 00:23:05.827103 [ 0.000000] Early memory node ranges
10426 00:23:05.833711 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10427 00:23:05.840142 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10428 00:23:05.846738 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10429 00:23:05.853889 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10430 00:23:05.860258 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10431 00:23:05.866749 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10432 00:23:05.922797 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10433 00:23:05.929366 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10434 00:23:05.935873 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10435 00:23:05.939200 [ 0.000000] psci: probing for conduit method from DT.
10436 00:23:05.946171 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10437 00:23:05.949031 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10438 00:23:05.955827 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10439 00:23:05.958882 [ 0.000000] psci: SMC Calling Convention v1.2
10440 00:23:05.965774 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10441 00:23:05.969327 [ 0.000000] Detected VIPT I-cache on CPU0
10442 00:23:05.975652 [ 0.000000] CPU features: detected: GIC system register CPU interface
10443 00:23:05.982231 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10444 00:23:05.988934 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10445 00:23:05.995538 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10446 00:23:06.002178 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10447 00:23:06.011996 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10448 00:23:06.015679 [ 0.000000] alternatives: applying boot alternatives
10449 00:23:06.022144 [ 0.000000] Fallback order for Node 0: 0
10450 00:23:06.028961 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10451 00:23:06.032148 [ 0.000000] Policy zone: Normal
10452 00:23:06.045295 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10453 00:23:06.055079 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10454 00:23:06.067041 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10455 00:23:06.076900 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10456 00:23:06.083515 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10457 00:23:06.086962 <6>[ 0.000000] software IO TLB: area num 8.
10458 00:23:06.143570 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10459 00:23:06.293075 <6>[ 0.000000] Memory: 7913136K/8385536K available (18112K kernel code, 4120K rwdata, 22648K rodata, 8512K init, 616K bss, 439632K reserved, 32768K cma-reserved)
10460 00:23:06.299716 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10461 00:23:06.306385 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10462 00:23:06.309847 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10463 00:23:06.316429 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10464 00:23:06.323058 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10465 00:23:06.326537 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10466 00:23:06.335731 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10467 00:23:06.342615 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10468 00:23:06.349084 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10469 00:23:06.355333 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10470 00:23:06.358994 <6>[ 0.000000] GICv3: 608 SPIs implemented
10471 00:23:06.361979 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10472 00:23:06.368685 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10473 00:23:06.372116 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10474 00:23:06.378692 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10475 00:23:06.392247 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10476 00:23:06.404819 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10477 00:23:06.411759 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10478 00:23:06.419394 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10479 00:23:06.432489 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10480 00:23:06.439241 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10481 00:23:06.446324 <6>[ 0.009176] Console: colour dummy device 80x25
10482 00:23:06.455909 <6>[ 0.013921] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10483 00:23:06.462564 <6>[ 0.024395] pid_max: default: 32768 minimum: 301
10484 00:23:06.465966 <6>[ 0.029297] LSM: Security Framework initializing
10485 00:23:06.472891 <6>[ 0.034197] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10486 00:23:06.482289 <6>[ 0.042059] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10487 00:23:06.489024 <6>[ 0.051443] cblist_init_generic: Setting adjustable number of callback queues.
10488 00:23:06.495849 <6>[ 0.058885] cblist_init_generic: Setting shift to 3 and lim to 1.
10489 00:23:06.505632 <6>[ 0.065262] cblist_init_generic: Setting adjustable number of callback queues.
10490 00:23:06.512194 <6>[ 0.072689] cblist_init_generic: Setting shift to 3 and lim to 1.
10491 00:23:06.515724 <6>[ 0.079129] rcu: Hierarchical SRCU implementation.
10492 00:23:06.522074 <6>[ 0.084145] rcu: Max phase no-delay instances is 1000.
10493 00:23:06.529230 <6>[ 0.091205] EFI services will not be available.
10494 00:23:06.532200 <6>[ 0.096164] smp: Bringing up secondary CPUs ...
10495 00:23:06.540637 <6>[ 0.101188] Detected VIPT I-cache on CPU1
10496 00:23:06.547008 <6>[ 0.101247] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10497 00:23:06.553996 <6>[ 0.101271] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10498 00:23:06.557295 <6>[ 0.101582] Detected VIPT I-cache on CPU2
10499 00:23:06.567003 <6>[ 0.101631] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10500 00:23:06.573334 <6>[ 0.101648] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10501 00:23:06.576792 <6>[ 0.101905] Detected VIPT I-cache on CPU3
10502 00:23:06.583309 <6>[ 0.101952] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10503 00:23:06.590416 <6>[ 0.101966] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10504 00:23:06.596651 <6>[ 0.102270] CPU features: detected: Spectre-v4
10505 00:23:06.600061 <6>[ 0.102276] CPU features: detected: Spectre-BHB
10506 00:23:06.603195 <6>[ 0.102281] Detected PIPT I-cache on CPU4
10507 00:23:06.609830 <6>[ 0.102338] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10508 00:23:06.616491 <6>[ 0.102354] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10509 00:23:06.623202 <6>[ 0.102652] Detected PIPT I-cache on CPU5
10510 00:23:06.629783 <6>[ 0.102715] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10511 00:23:06.636175 <6>[ 0.102732] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10512 00:23:06.639471 <6>[ 0.103014] Detected PIPT I-cache on CPU6
10513 00:23:06.649288 <6>[ 0.103080] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10514 00:23:06.655911 <6>[ 0.103096] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10515 00:23:06.659292 <6>[ 0.103393] Detected PIPT I-cache on CPU7
10516 00:23:06.665803 <6>[ 0.103459] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10517 00:23:06.672438 <6>[ 0.103475] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10518 00:23:06.675723 <6>[ 0.103523] smp: Brought up 1 node, 8 CPUs
10519 00:23:06.682441 <6>[ 0.244923] SMP: Total of 8 processors activated.
10520 00:23:06.685371 <6>[ 0.249844] CPU features: detected: 32-bit EL0 Support
10521 00:23:06.695786 <6>[ 0.255208] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10522 00:23:06.702538 <6>[ 0.264064] CPU features: detected: Common not Private translations
10523 00:23:06.709211 <6>[ 0.270540] CPU features: detected: CRC32 instructions
10524 00:23:06.712217 <6>[ 0.275924] CPU features: detected: RCpc load-acquire (LDAPR)
10525 00:23:06.719347 <6>[ 0.281885] CPU features: detected: LSE atomic instructions
10526 00:23:06.725313 <6>[ 0.287702] CPU features: detected: Privileged Access Never
10527 00:23:06.732422 <6>[ 0.293482] CPU features: detected: RAS Extension Support
10528 00:23:06.738697 <6>[ 0.299091] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10529 00:23:06.741998 <6>[ 0.306310] CPU: All CPU(s) started at EL2
10530 00:23:06.748257 <6>[ 0.310627] alternatives: applying system-wide alternatives
10531 00:23:06.758497 <6>[ 0.321468] devtmpfs: initialized
10532 00:23:06.774145 <6>[ 0.330422] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10533 00:23:06.780633 <6>[ 0.340383] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10534 00:23:06.787074 <6>[ 0.348557] pinctrl core: initialized pinctrl subsystem
10535 00:23:06.790520 <6>[ 0.355225] DMI not present or invalid.
10536 00:23:06.797072 <6>[ 0.359640] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10537 00:23:06.806972 <6>[ 0.366513] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10538 00:23:06.813558 <6>[ 0.374097] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10539 00:23:06.823690 <6>[ 0.382329] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10540 00:23:06.827335 <6>[ 0.390571] audit: initializing netlink subsys (disabled)
10541 00:23:06.837080 <5>[ 0.396263] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10542 00:23:06.843204 <6>[ 0.396974] thermal_sys: Registered thermal governor 'step_wise'
10543 00:23:06.849773 <6>[ 0.404230] thermal_sys: Registered thermal governor 'power_allocator'
10544 00:23:06.852948 <6>[ 0.410486] cpuidle: using governor menu
10545 00:23:06.859842 <6>[ 0.421444] NET: Registered PF_QIPCRTR protocol family
10546 00:23:06.866664 <6>[ 0.426919] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10547 00:23:06.873040 <6>[ 0.434023] ASID allocator initialised with 32768 entries
10548 00:23:06.876576 <6>[ 0.440602] Serial: AMBA PL011 UART driver
10549 00:23:06.886855 <4>[ 0.449470] Trying to register duplicate clock ID: 134
10550 00:23:06.946319 <6>[ 0.512408] KASLR enabled
10551 00:23:06.960431 <6>[ 0.520090] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10552 00:23:06.967469 <6>[ 0.527105] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10553 00:23:06.973223 <6>[ 0.533595] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10554 00:23:06.979667 <6>[ 0.540600] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10555 00:23:06.986708 <6>[ 0.547086] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10556 00:23:06.993240 <6>[ 0.554090] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10557 00:23:06.999866 <6>[ 0.560575] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10558 00:23:07.006392 <6>[ 0.567580] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10559 00:23:07.009887 <6>[ 0.575052] ACPI: Interpreter disabled.
10560 00:23:07.018316 <6>[ 0.581473] iommu: Default domain type: Translated
10561 00:23:07.025396 <6>[ 0.586626] iommu: DMA domain TLB invalidation policy: strict mode
10562 00:23:07.028741 <5>[ 0.593289] SCSI subsystem initialized
10563 00:23:07.035134 <6>[ 0.597537] usbcore: registered new interface driver usbfs
10564 00:23:07.041423 <6>[ 0.603269] usbcore: registered new interface driver hub
10565 00:23:07.044615 <6>[ 0.608822] usbcore: registered new device driver usb
10566 00:23:07.052000 <6>[ 0.614935] pps_core: LinuxPPS API ver. 1 registered
10567 00:23:07.061700 <6>[ 0.620128] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10568 00:23:07.065367 <6>[ 0.629469] PTP clock support registered
10569 00:23:07.068769 <6>[ 0.633711] EDAC MC: Ver: 3.0.0
10570 00:23:07.076322 <6>[ 0.638872] FPGA manager framework
10571 00:23:07.082828 <6>[ 0.642548] Advanced Linux Sound Architecture Driver Initialized.
10572 00:23:07.085785 <6>[ 0.649327] vgaarb: loaded
10573 00:23:07.092631 <6>[ 0.652470] clocksource: Switched to clocksource arch_sys_counter
10574 00:23:07.096027 <5>[ 0.658911] VFS: Disk quotas dquot_6.6.0
10575 00:23:07.102381 <6>[ 0.663095] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10576 00:23:07.105743 <6>[ 0.670290] pnp: PnP ACPI: disabled
10577 00:23:07.113891 <6>[ 0.677007] NET: Registered PF_INET protocol family
10578 00:23:07.120837 <6>[ 0.682596] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10579 00:23:07.134879 <6>[ 0.694919] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10580 00:23:07.145285 <6>[ 0.703733] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10581 00:23:07.151589 <6>[ 0.711702] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10582 00:23:07.161842 <6>[ 0.720404] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10583 00:23:07.168212 <6>[ 0.730156] TCP: Hash tables configured (established 65536 bind 65536)
10584 00:23:07.174851 <6>[ 0.737029] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10585 00:23:07.184620 <6>[ 0.744227] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10586 00:23:07.190938 <6>[ 0.751933] NET: Registered PF_UNIX/PF_LOCAL protocol family
10587 00:23:07.194363 <6>[ 0.758076] RPC: Registered named UNIX socket transport module.
10588 00:23:07.200765 <6>[ 0.764230] RPC: Registered udp transport module.
10589 00:23:07.204645 <6>[ 0.769163] RPC: Registered tcp transport module.
10590 00:23:07.210686 <6>[ 0.774095] RPC: Registered tcp NFSv4.1 backchannel transport module.
10591 00:23:07.217482 <6>[ 0.780762] PCI: CLS 0 bytes, default 64
10592 00:23:07.220829 <6>[ 0.785129] Unpacking initramfs...
10593 00:23:07.227530 <6>[ 0.788865] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10594 00:23:07.237424 <6>[ 0.797489] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10595 00:23:07.244419 <6>[ 0.806286] kvm [1]: IPA Size Limit: 40 bits
10596 00:23:07.247548 <6>[ 0.810811] kvm [1]: GICv3: no GICV resource entry
10597 00:23:07.250817 <6>[ 0.815834] kvm [1]: disabling GICv2 emulation
10598 00:23:07.257434 <6>[ 0.820523] kvm [1]: GIC system register CPU interface enabled
10599 00:23:07.264104 <6>[ 0.826687] kvm [1]: vgic interrupt IRQ18
10600 00:23:07.270794 <6>[ 0.832523] kvm [1]: VHE mode initialized successfully
10601 00:23:07.274057 <5>[ 0.838796] Initialise system trusted keyrings
10602 00:23:07.280445 <6>[ 0.843585] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10603 00:23:07.290170 <6>[ 0.853577] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10604 00:23:07.297162 <5>[ 0.859946] NFS: Registering the id_resolver key type
10605 00:23:07.300362 <5>[ 0.865251] Key type id_resolver registered
10606 00:23:07.307025 <5>[ 0.869664] Key type id_legacy registered
10607 00:23:07.313630 <6>[ 0.873945] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10608 00:23:07.320371 <6>[ 0.880867] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10609 00:23:07.326875 <6>[ 0.888574] 9p: Installing v9fs 9p2000 file system support
10610 00:23:07.362087 <5>[ 0.925222] Key type asymmetric registered
10611 00:23:07.365164 <5>[ 0.929553] Asymmetric key parser 'x509' registered
10612 00:23:07.375462 <6>[ 0.934685] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10613 00:23:07.379008 <6>[ 0.942301] io scheduler mq-deadline registered
10614 00:23:07.382055 <6>[ 0.947060] io scheduler kyber registered
10615 00:23:07.401143 <6>[ 0.964087] EINJ: ACPI disabled.
10616 00:23:07.433814 <4>[ 0.990222] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10617 00:23:07.444005 <4>[ 1.000854] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10618 00:23:07.459202 <6>[ 1.021812] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10619 00:23:07.466934 <6>[ 1.029761] printk: console [ttyS0] disabled
10620 00:23:07.494838 <6>[ 1.054392] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10621 00:23:07.501208 <6>[ 1.063861] printk: console [ttyS0] enabled
10622 00:23:07.504574 <6>[ 1.063861] printk: console [ttyS0] enabled
10623 00:23:07.511413 <6>[ 1.072754] printk: bootconsole [mtk8250] disabled
10624 00:23:07.514486 <6>[ 1.072754] printk: bootconsole [mtk8250] disabled
10625 00:23:07.521339 <6>[ 1.083755] SuperH (H)SCI(F) driver initialized
10626 00:23:07.524412 <6>[ 1.089030] msm_serial: driver initialized
10627 00:23:07.538651 <6>[ 1.097897] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10628 00:23:07.548294 <6>[ 1.106443] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10629 00:23:07.555098 <6>[ 1.114989] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10630 00:23:07.564640 <6>[ 1.123617] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10631 00:23:07.571541 <6>[ 1.132325] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10632 00:23:07.581637 <6>[ 1.141039] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10633 00:23:07.591588 <6>[ 1.149585] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10634 00:23:07.598198 <6>[ 1.158379] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10635 00:23:07.607784 <6>[ 1.166923] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10636 00:23:07.619261 <6>[ 1.182243] loop: module loaded
10637 00:23:07.626204 <6>[ 1.188163] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10638 00:23:07.648027 <4>[ 1.211287] mtk-pmic-keys: Failed to locate of_node [id: -1]
10639 00:23:07.654969 <6>[ 1.218043] megasas: 07.719.03.00-rc1
10640 00:23:07.664353 <6>[ 1.227586] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10641 00:23:07.672416 <6>[ 1.235857] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10642 00:23:07.689238 <6>[ 1.252409] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10643 00:23:07.745497 <6>[ 1.301839] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10644 00:23:09.453646 <6>[ 3.017240] Freeing initrd memory: 50920K
10645 00:23:09.465092 <6>[ 3.028836] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10646 00:23:09.476082 <6>[ 3.039737] tun: Universal TUN/TAP device driver, 1.6
10647 00:23:09.479703 <6>[ 3.045793] thunder_xcv, ver 1.0
10648 00:23:09.482715 <6>[ 3.049300] thunder_bgx, ver 1.0
10649 00:23:09.486088 <6>[ 3.052794] nicpf, ver 1.0
10650 00:23:09.496773 <6>[ 3.056804] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10651 00:23:09.499766 <6>[ 3.064278] hns3: Copyright (c) 2017 Huawei Corporation.
10652 00:23:09.506621 <6>[ 3.069870] hclge is initializing
10653 00:23:09.509588 <6>[ 3.073450] e1000: Intel(R) PRO/1000 Network Driver
10654 00:23:09.516341 <6>[ 3.078579] e1000: Copyright (c) 1999-2006 Intel Corporation.
10655 00:23:09.519687 <6>[ 3.084591] e1000e: Intel(R) PRO/1000 Network Driver
10656 00:23:09.526144 <6>[ 3.089807] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10657 00:23:09.532739 <6>[ 3.095992] igb: Intel(R) Gigabit Ethernet Network Driver
10658 00:23:09.539237 <6>[ 3.101642] igb: Copyright (c) 2007-2014 Intel Corporation.
10659 00:23:09.546008 <6>[ 3.107481] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10660 00:23:09.552852 <6>[ 3.113999] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10661 00:23:09.555836 <6>[ 3.120455] sky2: driver version 1.30
10662 00:23:09.562647 <6>[ 3.125383] usbcore: registered new device driver r8152-cfgselector
10663 00:23:09.569182 <6>[ 3.131917] usbcore: registered new interface driver r8152
10664 00:23:09.575776 <6>[ 3.137731] VFIO - User Level meta-driver version: 0.3
10665 00:23:09.582561 <6>[ 3.145964] usbcore: registered new interface driver usb-storage
10666 00:23:09.588678 <6>[ 3.152405] usbcore: registered new device driver onboard-usb-hub
10667 00:23:09.597902 <6>[ 3.161549] mt6397-rtc mt6359-rtc: registered as rtc0
10668 00:23:09.608004 <6>[ 3.167041] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-21T00:23:09 UTC (1718929389)
10669 00:23:09.611041 <6>[ 3.176674] i2c_dev: i2c /dev entries driver
10670 00:23:09.625038 <4>[ 3.188655] cpu cpu0: supply cpu not found, using dummy regulator
10671 00:23:09.631671 <4>[ 3.195086] cpu cpu1: supply cpu not found, using dummy regulator
10672 00:23:09.638610 <4>[ 3.201490] cpu cpu2: supply cpu not found, using dummy regulator
10673 00:23:09.645102 <4>[ 3.207888] cpu cpu3: supply cpu not found, using dummy regulator
10674 00:23:09.651716 <4>[ 3.214285] cpu cpu4: supply cpu not found, using dummy regulator
10675 00:23:09.658157 <4>[ 3.220682] cpu cpu5: supply cpu not found, using dummy regulator
10676 00:23:09.664712 <4>[ 3.227079] cpu cpu6: supply cpu not found, using dummy regulator
10677 00:23:09.671511 <4>[ 3.233489] cpu cpu7: supply cpu not found, using dummy regulator
10678 00:23:09.690636 <6>[ 3.254127] cpu cpu0: EM: created perf domain
10679 00:23:09.693567 <6>[ 3.259087] cpu cpu4: EM: created perf domain
10680 00:23:09.700694 <6>[ 3.264650] sdhci: Secure Digital Host Controller Interface driver
10681 00:23:09.707570 <6>[ 3.271080] sdhci: Copyright(c) Pierre Ossman
10682 00:23:09.714219 <6>[ 3.276037] Synopsys Designware Multimedia Card Interface Driver
10683 00:23:09.720842 <6>[ 3.282672] sdhci-pltfm: SDHCI platform and OF driver helper
10684 00:23:09.724094 <6>[ 3.282739] mmc0: CQHCI version 5.10
10685 00:23:09.730923 <6>[ 3.292641] ledtrig-cpu: registered to indicate activity on CPUs
10686 00:23:09.737684 <6>[ 3.299554] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10687 00:23:09.744218 <6>[ 3.306601] usbcore: registered new interface driver usbhid
10688 00:23:09.747714 <6>[ 3.312426] usbhid: USB HID core driver
10689 00:23:09.754011 <6>[ 3.316622] spi_master spi0: will run message pump with realtime priority
10690 00:23:09.800212 <6>[ 3.357213] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10691 00:23:09.819422 <6>[ 3.372416] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10692 00:23:09.822252 <6>[ 3.381513] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x17414
10693 00:23:09.830383 <6>[ 3.393932] cros-ec-spi spi0.0: Chrome EC device registered
10694 00:23:09.837146 <6>[ 3.399919] mmc0: Command Queue Engine enabled
10695 00:23:09.843727 <6>[ 3.404652] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10696 00:23:09.847182 <6>[ 3.412128] mmcblk0: mmc0:0001 DA4128 116 GiB
10697 00:23:09.856867 <6>[ 3.420716] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10698 00:23:09.864289 <6>[ 3.428023] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10699 00:23:09.871164 <6>[ 3.434211] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10700 00:23:09.881047 <6>[ 3.438659] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10701 00:23:09.887743 <6>[ 3.440110] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10702 00:23:09.891195 <6>[ 3.450085] NET: Registered PF_PACKET protocol family
10703 00:23:09.897687 <6>[ 3.460671] 9pnet: Installing 9P2000 support
10704 00:23:09.900763 <5>[ 3.465237] Key type dns_resolver registered
10705 00:23:09.904394 <6>[ 3.470087] registered taskstats version 1
10706 00:23:09.910959 <5>[ 3.474476] Loading compiled-in X.509 certificates
10707 00:23:09.940940 <4>[ 3.497633] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10708 00:23:09.950362 <4>[ 3.508391] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10709 00:23:09.966568 <6>[ 3.530400] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10710 00:23:09.973525 <6>[ 3.537236] xhci-mtk 11200000.usb: xHCI Host Controller
10711 00:23:09.980161 <6>[ 3.542737] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10712 00:23:09.990148 <6>[ 3.550609] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10713 00:23:09.996787 <6>[ 3.560043] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10714 00:23:10.003210 <6>[ 3.566273] xhci-mtk 11200000.usb: xHCI Host Controller
10715 00:23:10.010076 <6>[ 3.571778] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10716 00:23:10.016804 <6>[ 3.579434] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10717 00:23:10.023480 <6>[ 3.587155] hub 1-0:1.0: USB hub found
10718 00:23:10.026970 <6>[ 3.591180] hub 1-0:1.0: 1 port detected
10719 00:23:10.036860 <6>[ 3.595471] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10720 00:23:10.039936 <6>[ 3.604156] hub 2-0:1.0: USB hub found
10721 00:23:10.043617 <6>[ 3.608181] hub 2-0:1.0: 1 port detected
10722 00:23:10.051432 <6>[ 3.615168] mtk-msdc 11f70000.mmc: Got CD GPIO
10723 00:23:10.068788 <6>[ 3.629215] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10724 00:23:10.078887 <6>[ 3.637592] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10725 00:23:10.085648 <6>[ 3.645933] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10726 00:23:10.095367 <6>[ 3.654271] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10727 00:23:10.102297 <6>[ 3.662610] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10728 00:23:10.112272 <6>[ 3.670948] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10729 00:23:10.118899 <6>[ 3.679298] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10730 00:23:10.128587 <6>[ 3.687638] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10731 00:23:10.135081 <6>[ 3.695975] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10732 00:23:10.145353 <6>[ 3.704314] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10733 00:23:10.152169 <6>[ 3.712660] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10734 00:23:10.161845 <6>[ 3.720999] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10735 00:23:10.168059 <6>[ 3.729337] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10736 00:23:10.178472 <6>[ 3.737675] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10737 00:23:10.185100 <6>[ 3.746018] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10738 00:23:10.191803 <6>[ 3.754613] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10739 00:23:10.198313 <6>[ 3.761757] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10740 00:23:10.205087 <6>[ 3.768575] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10741 00:23:10.215186 <6>[ 3.775340] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10742 00:23:10.221474 <6>[ 3.782335] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10743 00:23:10.228310 <6>[ 3.789193] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10744 00:23:10.238158 <6>[ 3.798325] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10745 00:23:10.247917 <6>[ 3.807446] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10746 00:23:10.257930 <6>[ 3.816740] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10747 00:23:10.268192 <6>[ 3.826206] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10748 00:23:10.274426 <6>[ 3.835672] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10749 00:23:10.284188 <6>[ 3.844792] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10750 00:23:10.294074 <6>[ 3.854258] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10751 00:23:10.304134 <6>[ 3.863377] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10752 00:23:10.314153 <6>[ 3.872677] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10753 00:23:10.323891 <6>[ 3.882837] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10754 00:23:10.333871 <6>[ 3.894431] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10755 00:23:10.432626 <6>[ 3.993117] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10756 00:23:10.459816 <6>[ 4.023708] hub 2-1:1.0: USB hub found
10757 00:23:10.463505 <6>[ 4.028155] hub 2-1:1.0: 3 ports detected
10758 00:23:10.472624 <6>[ 4.036306] hub 2-1:1.0: USB hub found
10759 00:23:10.475827 <6>[ 4.040736] hub 2-1:1.0: 3 ports detected
10760 00:23:10.584406 <6>[ 4.144750] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10761 00:23:10.739039 <6>[ 4.302665] hub 1-1:1.0: USB hub found
10762 00:23:10.742167 <6>[ 4.307168] hub 1-1:1.0: 4 ports detected
10763 00:23:10.754649 <6>[ 4.318133] hub 1-1:1.0: USB hub found
10764 00:23:10.757562 <6>[ 4.322438] hub 1-1:1.0: 4 ports detected
10765 00:23:10.824329 <6>[ 4.384873] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10766 00:23:10.933049 <6>[ 4.493167] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10767 00:23:10.980477 <6>[ 4.540694] r8152 2-1.3:1.0: load rtl8153b-2 v1 10/23/19 successfully
10768 00:23:11.017996 <6>[ 4.581534] r8152 2-1.3:1.0 eth0: v1.12.13
10769 00:23:11.080672 <6>[ 4.640807] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10770 00:23:11.212825 <6>[ 4.776075] hub 1-1.4:1.0: USB hub found
10771 00:23:11.215933 <6>[ 4.780693] hub 1-1.4:1.0: 2 ports detected
10772 00:23:11.228380 <6>[ 4.791540] hub 1-1.4:1.0: USB hub found
10773 00:23:11.231411 <6>[ 4.796123] hub 1-1.4:1.0: 2 ports detected
10774 00:23:11.528258 <6>[ 5.088789] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10775 00:23:11.724343 <6>[ 5.284808] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10776 00:23:12.635285 <6>[ 6.199001] r8152 2-1.3:1.0 eth0: carrier on
10777 00:23:12.680709 <5>[ 6.228693] Sending DHCP requests ., OK
10778 00:23:12.687606 <6>[ 6.248797] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.21
10779 00:23:12.690949 <6>[ 6.257090] IP-Config: Complete:
10780 00:23:12.703744 <6>[ 6.260619] device=eth0, hwaddr=00:e0:4c:72:2d:d6, ipaddr=192.168.201.21, mask=255.255.255.0, gw=192.168.201.1
10781 00:23:12.710669 <6>[ 6.271344] host=mt8192-asurada-spherion-r0-cbg-1, domain=lava-rack, nis-domain=(none)
10782 00:23:12.717479 <6>[ 6.279963] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10783 00:23:12.723792 <6>[ 6.279972] nameserver0=192.168.201.1
10784 00:23:12.727319 <6>[ 6.292130] clk: Disabling unused clocks
10785 00:23:12.730311 <6>[ 6.297684] ALSA device list:
10786 00:23:12.736968 <6>[ 6.300955] No soundcards found.
10787 00:23:12.744653 <6>[ 6.308663] Freeing unused kernel memory: 8512K
10788 00:23:12.748023 <6>[ 6.313536] Run /init as init process
10789 00:23:12.778705 <6>[ 6.342760] NET: Registered PF_INET6 protocol family
10790 00:23:12.785572 <6>[ 6.349292] Segment Routing with IPv6
10791 00:23:12.788755 <6>[ 6.353250] In-situ OAM (IOAM) with IPv6
10792 00:23:12.830829 <30>[ 6.367897] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10793 00:23:12.837378 <30>[ 6.400932] systemd[1]: Detected architecture arm64.
10794 00:23:12.837483
10795 00:23:12.840438 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10796 00:23:12.843873
10797 00:23:12.856916 <30>[ 6.420884] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10798 00:23:12.988689 <30>[ 6.548724] systemd[1]: Queued start job for default target graphical.target.
10799 00:23:13.034385 <30>[ 6.594490] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10800 00:23:13.041036 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10801 00:23:13.061147 <30>[ 6.621272] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10802 00:23:13.070745 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10803 00:23:13.089793 <30>[ 6.649857] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10804 00:23:13.099626 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10805 00:23:13.117304 <30>[ 6.677202] systemd[1]: Created slice user.slice - User and Session Slice.
10806 00:23:13.123683 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10807 00:23:13.144122 <30>[ 6.700909] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10808 00:23:13.150608 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10809 00:23:13.172514 <30>[ 6.729414] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10810 00:23:13.179055 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10811 00:23:13.207010 <30>[ 6.756882] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10812 00:23:13.216680 <30>[ 6.776674] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10813 00:23:13.223096 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10814 00:23:13.240921 <30>[ 6.801162] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10815 00:23:13.247853 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10816 00:23:13.269030 <30>[ 6.829268] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10817 00:23:13.279128 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10818 00:23:13.294028 <30>[ 6.857342] systemd[1]: Reached target paths.target - Path Units.
10819 00:23:13.303826 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10820 00:23:13.320580 <30>[ 6.880871] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10821 00:23:13.327213 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10822 00:23:13.341163 <30>[ 6.904770] systemd[1]: Reached target slices.target - Slice Units.
10823 00:23:13.351318 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10824 00:23:13.366226 <30>[ 6.929292] systemd[1]: Reached target swap.target - Swaps.
10825 00:23:13.372342 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10826 00:23:13.393048 <30>[ 6.953293] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10827 00:23:13.403199 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10828 00:23:13.421410 <30>[ 6.981732] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10829 00:23:13.431672 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10830 00:23:13.450536 <30>[ 7.010910] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10831 00:23:13.460250 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10832 00:23:13.477265 <30>[ 7.037389] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10833 00:23:13.487166 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10834 00:23:13.505212 <30>[ 7.065361] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10835 00:23:13.511883 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10836 00:23:13.529539 <30>[ 7.089446] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10837 00:23:13.539285 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10838 00:23:13.557812 <30>[ 7.118181] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10839 00:23:13.567645 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10840 00:23:13.585917 <30>[ 7.145891] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10841 00:23:13.595500 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10842 00:23:13.644357 <30>[ 7.205067] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10843 00:23:13.651347 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10844 00:23:13.676075 <30>[ 7.236912] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10845 00:23:13.683203 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10846 00:23:13.707358 <30>[ 7.268034] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10847 00:23:13.714217 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10848 00:23:13.743856 <30>[ 7.297268] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10849 00:23:13.784991 <30>[ 7.345360] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10850 00:23:13.795041 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10851 00:23:13.818084 <30>[ 7.378270] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10852 00:23:13.824510 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10853 00:23:13.880864 <30>[ 7.441446] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10854 00:23:13.890717 Startin<6>[ 7.450819] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10855 00:23:13.897362 g [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10856 00:23:13.921009 <30>[ 7.481758] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10857 00:23:13.927700 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10858 00:23:13.953801 <30>[ 7.514134] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10859 00:23:13.960071 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10860 00:23:13.985806 <30>[ 7.545794] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10861 00:23:13.992046 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10862 00:23:14.021399 <30>[ 7.581740] systemd[1]: Starting systemd-journald.service - Journal Service...
10863 00:23:14.027833 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10864 00:23:14.061629 <30>[ 7.621625] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10865 00:23:14.067980 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10866 00:23:14.096612 <30>[ 7.653503] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10867 00:23:14.102897 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10868 00:23:14.125323 <30>[ 7.685716] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10869 00:23:14.134930 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10870 00:23:14.154757 <30>[ 7.715769] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10871 00:23:14.164941 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10872 00:23:14.181902 <30>[ 7.742691] systemd[1]: Started systemd-journald.service - Journal Service.
10873 00:23:14.188620 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10874 00:23:14.214713 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10875 00:23:14.237443 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10876 00:23:14.257740 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10877 00:23:14.282058 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10878 00:23:14.302000 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10879 00:23:14.321269 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10880 00:23:14.342400 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10881 00:23:14.361482 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10882 00:23:14.386060 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10883 00:23:14.405889 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10884 00:23:14.426163 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10885 00:23:14.446552 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10886 00:23:14.453624 See 'systemctl status systemd-remount-fs.service' for details.
10887 00:23:14.463178 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10888 00:23:14.483782 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10889 00:23:14.532625 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10890 00:23:14.553280 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10891 00:23:14.574597 <46>[ 8.134743] systemd-journald[191]: Received client request to flush runtime journal.
10892 00:23:14.587440 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10893 00:23:14.613694 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10894 00:23:14.636514 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10895 00:23:14.662899 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10896 00:23:14.682236 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10897 00:23:14.701925 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10898 00:23:14.721925 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10899 00:23:14.741688 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10900 00:23:14.789368 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10901 00:23:14.821130 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10902 00:23:14.841215 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10903 00:23:14.860901 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10904 00:23:14.904994 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10905 00:23:14.925272 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10906 00:23:14.948507 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10907 00:23:15.003471 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10908 00:23:15.029118 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10909 00:23:15.047781 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10910 00:23:15.104153 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10911 00:23:15.126057 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10912 00:23:15.155930 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10913 00:23:15.250795 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10914 00:23:15.269617 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10915 00:23:15.288865 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10916 00:23:15.309844 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10917 00:23:15.329174 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10918 00:23:15.345622 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10919 00:23:15.366975 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10920 00:23:15.394573 <3>[ 8.954353] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10921 00:23:15.404043 <3>[ 8.963220] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10922 00:23:15.410651 <3>[ 8.971332] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10923 00:23:15.425649 <6>[ 8.985953] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10924 00:23:15.432442 <6>[ 8.986938] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10925 00:23:15.439102 <6>[ 8.988727] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10926 00:23:15.448785 <6>[ 8.988754] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10927 00:23:15.458612 <6>[ 8.988761] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10928 00:23:15.465201 <3>[ 9.000982] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10929 00:23:15.475300 <6>[ 9.001602] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10930 00:23:15.481913 <3>[ 9.008958] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10931 00:23:15.491804 <3>[ 9.008963] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10932 00:23:15.498181 <3>[ 9.008969] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10933 00:23:15.504974 <3>[ 9.008972] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10934 00:23:15.515063 <3>[ 9.035150] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10935 00:23:15.518105 <6>[ 9.039550] remoteproc remoteproc0: scp is available
10936 00:23:15.525045 <6>[ 9.039686] remoteproc remoteproc0: powering up scp
10937 00:23:15.534589 <6>[ 9.039692] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10938 00:23:15.537957 <6>[ 9.039716] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10939 00:23:15.547972 <6>[ 9.042667] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10940 00:23:15.554538 <3>[ 9.063572] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10941 00:23:15.557641 <6>[ 9.067245] mc: Linux media interface: v0.10
10942 00:23:15.567728 <4>[ 9.067300] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10943 00:23:15.577171 <6>[ 9.067823] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10944 00:23:15.583837 <6>[ 9.067826] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10945 00:23:15.590762 <3>[ 9.075072] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10946 00:23:15.600640 <6>[ 9.129178] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10947 00:23:15.607393 <6>[ 9.130700] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10948 00:23:15.613975 <6>[ 9.130724] pci_bus 0000:00: root bus resource [bus 00-ff]
10949 00:23:15.620292 <6>[ 9.130745] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10950 00:23:15.630734 <6>[ 9.130775] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10951 00:23:15.636930 <6>[ 9.130864] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10952 00:23:15.643672 <6>[ 9.130898] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10953 00:23:15.646822 <6>[ 9.131001] pci 0000:00:00.0: supports D1 D2
10954 00:23:15.656891 <6>[ 9.131008] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10955 00:23:15.663253 <3>[ 9.137012] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10956 00:23:15.669919 <6>[ 9.145107] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10957 00:23:15.680383 <3>[ 9.155240] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10958 00:23:15.686479 <6>[ 9.160767] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10959 00:23:15.692619 <6>[ 9.160889] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10960 00:23:15.702844 <6>[ 9.160915] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10961 00:23:15.709584 <6>[ 9.160932] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10962 00:23:15.716026 <6>[ 9.160947] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10963 00:23:15.722545 <6>[ 9.161054] pci 0000:01:00.0: supports D1 D2
10964 00:23:15.728949 <6>[ 9.161056] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10965 00:23:15.735693 <6>[ 9.161238] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10966 00:23:15.745565 <6>[ 9.165109] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10967 00:23:15.752440 <6>[ 9.165118] remoteproc remoteproc0: remote processor scp is now up
10968 00:23:15.758853 <6>[ 9.165130] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10969 00:23:15.765660 <3>[ 9.169115] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10970 00:23:15.775536 <6>[ 9.176204] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10971 00:23:15.782173 <4>[ 9.176244] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10972 00:23:15.792269 <3>[ 9.182078] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10973 00:23:15.798354 <6>[ 9.184311] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10974 00:23:15.804848 <6>[ 9.184362] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10975 00:23:15.811794 <6>[ 9.184367] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10976 00:23:15.821552 <6>[ 9.184378] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10977 00:23:15.828009 <6>[ 9.184391] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10978 00:23:15.838273 <6>[ 9.184406] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10979 00:23:15.841616 <6>[ 9.184420] pci 0000:00:00.0: PCI bridge to [bus 01]
10980 00:23:15.851800 <6>[ 9.184427] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10981 00:23:15.858530 <4>[ 9.189915] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10982 00:23:15.865165 <3>[ 9.198932] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10983 00:23:15.875174 <3>[ 9.198939] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10984 00:23:15.881227 <6>[ 9.201194] videodev: Linux video capture interface: v2.00
10985 00:23:15.888029 <3>[ 9.201939] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10986 00:23:15.894563 <6>[ 9.202545] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10987 00:23:15.901196 <6>[ 9.204087] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10988 00:23:15.908268 <6>[ 9.276369] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10989 00:23:15.918014 <6>[ 9.280663] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10990 00:23:15.924389 <6>[ 9.286088] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10991 00:23:15.934198 <6>[ 9.290491] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10992 00:23:15.940897 <4>[ 9.295785] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10993 00:23:15.947606 <4>[ 9.295785] Fallback method does not support PEC.
10994 00:23:15.957353 <6>[ 9.336959] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10995 00:23:15.964082 <5>[ 9.384868] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10996 00:23:15.974137 <6>[ 9.411409] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10997 00:23:15.980412 <5>[ 9.433596] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10998 00:23:15.987168 <6>[ 9.438017] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10999 00:23:15.997238 <5>[ 9.443486] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
11000 00:23:16.000941 <6>[ 9.443889] Bluetooth: Core ver 2.22
11001 00:23:16.003942 <6>[ 9.443981] NET: Registered PF_BLUETOOTH protocol family
11002 00:23:16.010622 <6>[ 9.443983] Bluetooth: HCI device and connection manager initialized
11003 00:23:16.017073 <6>[ 9.444002] Bluetooth: HCI socket layer initialized
11004 00:23:16.024444 <6>[ 9.444008] Bluetooth: L2CAP socket layer initialized
11005 00:23:16.026979 <6>[ 9.444017] Bluetooth: SCO socket layer initialized
11006 00:23:16.033892 <6>[ 9.450356] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11007 00:23:16.043964 <4>[ 9.457255] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11008 00:23:16.056878 <6>[ 9.466105] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11009 00:23:16.060536 <6>[ 9.471185] cfg80211: failed to load regulatory.db
11010 00:23:16.066861 <6>[ 9.477612] usbcore: registered new interface driver uvcvideo
11011 00:23:16.073434 <6>[ 9.488448] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11012 00:23:16.080392 <6>[ 9.517531] usbcore: registered new interface driver btusb
11013 00:23:16.090364 <4>[ 9.518794] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11014 00:23:16.096542 <3>[ 9.518803] Bluetooth: hci0: Failed to load firmware file (-2)
11015 00:23:16.103100 <3>[ 9.518805] Bluetooth: hci0: Failed to set up firmware (-2)
11016 00:23:16.113209 <4>[ 9.518808] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11017 00:23:16.120319 <6>[ 9.568354] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11018 00:23:16.126617 <6>[ 9.688383] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11019 00:23:16.133122 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11020 00:23:16.150379 <6>[ 9.714286] mt7921e 0000:01:00.0: ASIC revision: 79610010
11021 00:23:16.156982 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11022 00:23:16.192787 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11023 00:23:16.220783 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11024 00:23:16.237601 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11025 00:23:16.255845 [[0;32m OK [<6>[ 9.817795] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
11026 00:23:16.259515 <6>[ 9.817795]
11027 00:23:16.266195 0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11028 00:23:16.305887 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11029 00:23:16.328004 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11030 00:23:16.345023 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11031 00:23:16.359250 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11032 00:23:16.378930 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11033 00:23:16.430157 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11034 00:23:16.455591 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11035 00:23:16.479755 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11036 00:23:16.501847 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11037 00:23:16.525608 <6>[ 10.086351] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
11038 00:23:16.550692 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11039 00:23:16.571087 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11040 00:23:16.596816 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11041 00:23:16.616416 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11042 00:23:16.637266 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11043 00:23:16.684125 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11044 00:23:16.708761 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11045 00:23:16.731246 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11046 00:23:16.765993 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11047 00:23:16.805266
11048 00:23:16.808803 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11049 00:23:16.809180
11050 00:23:16.811793 debian-bookworm-arm64 login: root (automatic login)
11051 00:23:16.812156
11052 00:23:16.824464 Linux debian-bookworm-arm64 6.1.94-cip23 #1 SMP PREEMPT Fri Jun 21 00:04:56 UTC 2024 aarch64
11053 00:23:16.824930
11054 00:23:16.830971 The programs included with the Debian GNU/Linux system are free software;
11055 00:23:16.837589 the exact distribution terms for each program are described in the
11056 00:23:16.841353 individual files in /usr/share/doc/*/copyright.
11057 00:23:16.841757
11058 00:23:16.848048 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11059 00:23:16.850687 permitted by applicable law.
11060 00:23:16.852034 Matched prompt #10: / #
11062 00:23:16.853427 Setting prompt string to ['/ #']
11063 00:23:16.853955 end: 2.2.5.1 login-action (duration 00:00:11) [common]
11065 00:23:16.854979 end: 2.2.5 auto-login-action (duration 00:00:11) [common]
11066 00:23:16.855435 start: 2.2.6 expect-shell-connection (timeout 00:03:28) [common]
11067 00:23:16.855817 Setting prompt string to ['/ #']
11068 00:23:16.856131 Forcing a shell prompt, looking for ['/ #']
11070 00:23:16.906835 / #
11071 00:23:16.906992 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11072 00:23:16.907064 Waiting using forced prompt support (timeout 00:02:30)
11073 00:23:16.911953
11074 00:23:16.912245 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11075 00:23:16.912336 start: 2.2.7 export-device-env (timeout 00:03:28) [common]
11076 00:23:16.912421 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11077 00:23:16.912499 end: 2.2 depthcharge-retry (duration 00:01:32) [common]
11078 00:23:16.912580 end: 2 depthcharge-action (duration 00:01:32) [common]
11079 00:23:16.912661 start: 3 lava-test-retry (timeout 00:05:00) [common]
11080 00:23:16.912778 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11081 00:23:16.912845 Using namespace: common
11083 00:23:17.013147 / # #
11084 00:23:17.013305 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11085 00:23:17.018266 #
11086 00:23:17.018517 Using /lava-14479150
11088 00:23:17.118833 / # export SHELL=/bin/sh
11089 00:23:17.124691 export SHELL=/bin/sh
11091 00:23:17.225934 / # . /lava-14479150/environment
11092 00:23:17.232552 . /lava-14479150/environment
11094 00:23:17.333929 / # /lava-14479150/bin/lava-test-runner /lava-14479150/0
11095 00:23:17.334560 Test shell timeout: 10s (minimum of the action and connection timeout)
11096 00:23:17.340287 /lava-14479150/bin/lava-test-runner /lava-14479150/0
11097 00:23:17.364658 + export TESTRUN_ID=0_cros-ec
11098 00:23:17.371087 + c<8>[ 10.934061] <LAVA_SIGNAL_STARTRUN 0_cros-ec 14479150_1.5.2.3.1>
11099 00:23:17.371759 Received signal: <STARTRUN> 0_cros-ec 14479150_1.5.2.3.1
11100 00:23:17.372102 Starting test lava.0_cros-ec (14479150_1.5.2.3.1)
11101 00:23:17.372469 Skipping test definition patterns.
11102 00:23:17.374348 d /lava-14479150/0/tests/0_cros-ec
11103 00:23:17.377927 + cat uuid
11104 00:23:17.378324 + UUID=14479150_1.5.2.3.1
11105 00:23:17.378631 + set +x
11106 00:23:17.384299 + python3 -m cros.runners.lava_runner -v
11107 00:23:17.405284 <6>[ 10.969552] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11108 00:23:17.836461 test_cros_ec_accel_iio_abi (cros.tests.cros_ec_accel.TestCrosECAccel.test_cros_ec_accel_iio_abi)
11109 00:23:17.843081 Checks the cros-ec accelerometer IIO ABI. ... skipped 'No cros-ec-accel found'
11110 00:23:17.843186
11111 00:23:17.849432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip>
11112 00:23:17.849700 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip
11114 00:23:17.859533 test_cros_ec_accel_iio_data_is_valid (cros.tests.cros_ec_accel.TestCrosECAccel.test_cros_ec_accel_iio_data_is_valid)
11115 00:23:17.869612 Validates accelerometer data by computing the magnitude. If the ... skipped 'No accelerometer found'
11116 00:23:17.869726
11117 00:23:17.876138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=skip>
11118 00:23:17.876410 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=skip
11120 00:23:17.886889 test_cros_ec_gyro_iio_abi (cros.tests.cros_ec_gyro.TestCrosECGyro.test_cros_ec_gyro_iio_abi)
11121 00:23:17.892991 Checks the cros-ec gyroscope IIO ABI. ... skipped 'No cros-ec-gyro found'
11122 00:23:17.893124
11123 00:23:17.899327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip>
11124 00:23:17.899576 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip
11126 00:23:17.906192 test_cros_ec_abi (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_ec_abi)
11127 00:23:17.909173 Checks the standard ABI for the main Embedded Controller. ... ok
11128 00:23:17.909257
11129 00:23:17.915845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_abi RESULT=pass>
11130 00:23:17.916104 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_abi RESULT=pass
11132 00:23:17.922464 test_cros_ec_chardev (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_ec_chardev)
11133 00:23:17.929610 Checks the main Embedded controller character device. ... ok
11134 00:23:17.929765
11135 00:23:17.936331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_chardev RESULT=pass>
11136 00:23:17.936743 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_chardev RESULT=pass
11138 00:23:17.942771 test_cros_ec_hello (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_ec_hello)
11139 00:23:17.949187 Checks basic comunication with the main Embedded controller. ... ok
11140 00:23:17.949389
11141 00:23:17.952714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_hello RESULT=pass>
11142 00:23:17.953040 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_hello RESULT=pass
11144 00:23:17.959196 test_cros_fp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_fp_abi)
11145 00:23:17.969290 Checks the standard ABI for the Fingerprint EC. ... skipped 'MCU cros_fp not supported'
11146 00:23:17.969592
11147 00:23:17.973039 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_abi RESULT=skip
11149 00:23:17.976003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_abi RESULT=skip>
11150 00:23:17.982533 test_cros_fp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_fp_hello)
11151 00:23:17.989248 Checks basic comunication with the fingerprint controller. ... skipped 'MCU cros_fp not found'
11152 00:23:17.989679
11153 00:23:17.996184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_hello RESULT=skip>
11154 00:23:17.996951 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_hello RESULT=skip
11156 00:23:18.002722 test_cros_fp_reboot (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_fp_reboot)
11157 00:23:18.009250 Test reboot command on Fingerprint MCU. ... skipped 'MCU cros_fp not found'
11158 00:23:18.009816
11159 00:23:18.015839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_reboot RESULT=skip>
11160 00:23:18.016486 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_reboot RESULT=skip
11162 00:23:18.022889 test_cros_pd_abi (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_pd_abi)
11163 00:23:18.029398 Checks the standard ABI for the Power Delivery EC. ... skipped 'MCU cros_pd not supported'
11164 00:23:18.029910
11165 00:23:18.035992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_abi RESULT=skip>
11166 00:23:18.036821 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_abi RESULT=skip
11168 00:23:18.042521 test_cros_pd_hello (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_pd_hello)
11169 00:23:18.052346 Checks basic comunication with the power delivery controller. ... skipped 'MCU cros_pd not found'
11170 00:23:18.052847
11171 00:23:18.055786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_hello RESULT=skip>
11172 00:23:18.056643 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_hello RESULT=skip
11174 00:23:18.062337 test_cros_tp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_tp_abi)
11175 00:23:18.072421 Checks the standard ABI for the Touchpad EC. ... skipped 'MCU cros_tp not supported'
11176 00:23:18.072974
11177 00:23:18.075642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_abi RESULT=skip>
11178 00:23:18.076417 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_abi RESULT=skip
11180 00:23:18.085440 test_cros_tp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_tp_hello)
11181 00:23:18.092064 Checks basic comunication with the touchpad controller. ... skipped 'MCU cros_tp not found'
11182 00:23:18.092584
11183 00:23:18.098572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_hello RESULT=skip>
11184 00:23:18.099344 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_hello RESULT=skip
11186 00:23:18.105180 test_cros_ec_pwm_backlight (cros.tests.cros_ec_pwm.TestCrosECPWM.test_cros_ec_pwm_backlight)
11187 00:23:18.115120 Check that the backlight is connected to a pwm of the EC and that ... skipped 'No backlight pwm found'
11188 00:23:18.115630
11189 00:23:18.121631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip>
11190 00:23:18.122408 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip
11192 00:23:18.131873 test_cros_ec_battery_abi (cros.tests.cros_ec_power.TestCrosECPower.test_cros_ec_battery_abi)
11193 00:23:18.135065 Check the cros battery ABI. ... skipped 'No BAT found'
11194 00:23:18.135586
11195 00:23:18.141487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip>
11196 00:23:18.142265 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip
11198 00:23:18.151457 test_cros_ec_usbpd_charger_abi (cros.tests.cros_ec_power.TestCrosECPower.test_cros_ec_usbpd_charger_abi)
11199 00:23:18.158560 Check the cros USBPD charger ABI. ... skipped 'No CROS_USBPD_CHARGER found'
11200 00:23:18.159090
11201 00:23:18.165086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip>
11202 00:23:18.165866 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip
11204 00:23:18.171626 test_cros_ec_rtc_abi (cros.tests.cros_ec_rtc.TestCrosECRTC.test_cros_ec_rtc_abi)
11205 00:23:18.178171 Check the cros RTC ABI. ... skipped 'EC_FEATURE_RTC not supported, skipping'
11206 00:23:18.178696
11207 00:23:18.185054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip>
11208 00:23:18.185834 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip
11210 00:23:18.194579 test_cros_ec_extcon_usbc_abi (cros.tests.cros_ec_extcon.TestCrosECextcon.test_cros_ec_extcon_usbc_abi)
11211 00:23:18.201646 Checks the cros-ec extcon ABI. ... skipped 'No extcon device found'
11212 00:23:18.202167
11213 00:23:18.208365 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=ski<8
11214 00:23:18.208981 Bad test result: ski<8
11215 00:23:18.210859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=ski<8>[ 11.775633] <LAVA_SIGNAL_ENDRUN 0_cros-ec 14479150_1.5.2.3.1>
11216 00:23:18.211609 Received signal: <ENDRUN> 0_cros-ec 14479150_1.5.2.3.1
11217 00:23:18.212012 Ending use of test pattern.
11218 00:23:18.212334 Ending test lava.0_cros-ec (14479150_1.5.2.3.1), duration 0.84
11220 00:23:18.214659 p>
11221 00:23:18.215142
11222 00:23:18.221071 ----------------------------------------------------------------------
11223 00:23:18.221671 Ran 18 tests in 0.327s
11224 00:23:18.222023
11225 00:23:18.224202 OK (skipped=15)
11226 00:23:18.224636 + set +x
11227 00:23:18.227539 <LAVA_TEST_RUNNER EXIT>
11228 00:23:18.228210 ok: lava_test_shell seems to have completed
11229 00:23:18.229051 test_cros_ec_abi: pass
test_cros_ec_accel_iio_abi: skip
test_cros_ec_accel_iio_data_is_valid: skip
test_cros_ec_battery_abi: skip
test_cros_ec_chardev: pass
test_cros_ec_gyro_iio_abi: skip
test_cros_ec_hello: pass
test_cros_ec_pwm_backlight: skip
test_cros_ec_rtc_abi: skip
test_cros_ec_usbpd_charger_abi: skip
test_cros_fp_abi: skip
test_cros_fp_hello: skip
test_cros_fp_reboot: skip
test_cros_pd_abi: skip
test_cros_pd_hello: skip
test_cros_tp_abi: skip
test_cros_tp_hello: skip
11230 00:23:18.229487 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11231 00:23:18.229890 end: 3 lava-test-retry (duration 00:00:01) [common]
11232 00:23:18.230358 start: 4 finalize (timeout 00:08:04) [common]
11233 00:23:18.230764 start: 4.1 power-off (timeout 00:00:30) [common]
11234 00:23:18.231413 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-1', '--port=1', '--command=off']
11235 00:23:20.377973 >> Command sent successfully.
11236 00:23:20.384973 Returned 0 in 2 seconds
11237 00:23:20.485689 end: 4.1 power-off (duration 00:00:02) [common]
11239 00:23:20.486934 start: 4.2 read-feedback (timeout 00:08:02) [common]
11240 00:23:20.487954 Listened to connection for namespace 'common' for up to 1s
11241 00:23:21.488532 Finalising connection for namespace 'common'
11242 00:23:21.488765 Disconnecting from shell: Finalise
11243 00:23:21.488942 / #
11244 00:23:21.589236 end: 4.2 read-feedback (duration 00:00:01) [common]
11245 00:23:21.589399 end: 4 finalize (duration 00:00:03) [common]
11246 00:23:21.589517 Cleaning after the job
11247 00:23:21.589627 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14479150/tftp-deploy-4y6o0n8e/ramdisk
11248 00:23:21.594961 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14479150/tftp-deploy-4y6o0n8e/kernel
11249 00:23:21.602164 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14479150/tftp-deploy-4y6o0n8e/dtb
11250 00:23:21.602319 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14479150/tftp-deploy-4y6o0n8e/modules
11251 00:23:21.607731 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14479150
11252 00:23:21.695095 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14479150
11253 00:23:21.695252 Job finished correctly