Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 29
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 23
1 00:24:28.289172 lava-dispatcher, installed at version: 2024.03
2 00:24:28.289385 start: 0 validate
3 00:24:28.289505 Start time: 2024-06-21 00:24:28.289497+00:00 (UTC)
4 00:24:28.289634 Using caching service: 'http://localhost/cache/?uri=%s'
5 00:24:28.289763 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 00:24:28.550586 Using caching service: 'http://localhost/cache/?uri=%s'
7 00:24:28.551310 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.94-cip23%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 00:24:28.815178 Using caching service: 'http://localhost/cache/?uri=%s'
9 00:24:28.816007 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.94-cip23%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 00:24:29.076563 Using caching service: 'http://localhost/cache/?uri=%s'
11 00:24:29.077212 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.94-cip23%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 00:24:29.347233 validate duration: 1.06
14 00:24:29.348454 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 00:24:29.349021 start: 1.1 download-retry (timeout 00:10:00) [common]
16 00:24:29.349507 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 00:24:29.350338 Not decompressing ramdisk as can be used compressed.
18 00:24:29.350910 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 00:24:29.351381 saving as /var/lib/lava/dispatcher/tmp/14479191/tftp-deploy-tqgh2cqp/ramdisk/rootfs.cpio.gz
20 00:24:29.351786 total size: 47897469 (45 MB)
21 00:24:29.356604 progress 0 % (0 MB)
22 00:24:29.394326 progress 5 % (2 MB)
23 00:24:29.410061 progress 10 % (4 MB)
24 00:24:29.422134 progress 15 % (6 MB)
25 00:24:29.433855 progress 20 % (9 MB)
26 00:24:29.445571 progress 25 % (11 MB)
27 00:24:29.457492 progress 30 % (13 MB)
28 00:24:29.469444 progress 35 % (16 MB)
29 00:24:29.481328 progress 40 % (18 MB)
30 00:24:29.493262 progress 45 % (20 MB)
31 00:24:29.505148 progress 50 % (22 MB)
32 00:24:29.516917 progress 55 % (25 MB)
33 00:24:29.528855 progress 60 % (27 MB)
34 00:24:29.540733 progress 65 % (29 MB)
35 00:24:29.552555 progress 70 % (32 MB)
36 00:24:29.564238 progress 75 % (34 MB)
37 00:24:29.575956 progress 80 % (36 MB)
38 00:24:29.587831 progress 85 % (38 MB)
39 00:24:29.599709 progress 90 % (41 MB)
40 00:24:29.611262 progress 95 % (43 MB)
41 00:24:29.622587 progress 100 % (45 MB)
42 00:24:29.622786 45 MB downloaded in 0.27 s (168.55 MB/s)
43 00:24:29.622941 end: 1.1.1 http-download (duration 00:00:00) [common]
45 00:24:29.623155 end: 1.1 download-retry (duration 00:00:00) [common]
46 00:24:29.623233 start: 1.2 download-retry (timeout 00:10:00) [common]
47 00:24:29.623308 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 00:24:29.623436 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.94-cip23/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 00:24:29.623497 saving as /var/lib/lava/dispatcher/tmp/14479191/tftp-deploy-tqgh2cqp/kernel/Image
50 00:24:29.623550 total size: 54813184 (52 MB)
51 00:24:29.623603 No compression specified
52 00:24:29.624600 progress 0 % (0 MB)
53 00:24:29.637914 progress 5 % (2 MB)
54 00:24:29.651497 progress 10 % (5 MB)
55 00:24:29.664731 progress 15 % (7 MB)
56 00:24:29.678009 progress 20 % (10 MB)
57 00:24:29.691548 progress 25 % (13 MB)
58 00:24:29.704971 progress 30 % (15 MB)
59 00:24:29.718430 progress 35 % (18 MB)
60 00:24:29.731688 progress 40 % (20 MB)
61 00:24:29.744942 progress 45 % (23 MB)
62 00:24:29.758456 progress 50 % (26 MB)
63 00:24:29.771861 progress 55 % (28 MB)
64 00:24:29.785187 progress 60 % (31 MB)
65 00:24:29.798648 progress 65 % (34 MB)
66 00:24:29.811950 progress 70 % (36 MB)
67 00:24:29.825751 progress 75 % (39 MB)
68 00:24:29.839273 progress 80 % (41 MB)
69 00:24:29.852545 progress 85 % (44 MB)
70 00:24:29.865917 progress 90 % (47 MB)
71 00:24:29.879187 progress 95 % (49 MB)
72 00:24:29.892173 progress 100 % (52 MB)
73 00:24:29.892375 52 MB downloaded in 0.27 s (194.46 MB/s)
74 00:24:29.892519 end: 1.2.1 http-download (duration 00:00:00) [common]
76 00:24:29.892724 end: 1.2 download-retry (duration 00:00:00) [common]
77 00:24:29.892804 start: 1.3 download-retry (timeout 00:09:59) [common]
78 00:24:29.892878 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 00:24:29.893002 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.94-cip23/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 00:24:29.893063 saving as /var/lib/lava/dispatcher/tmp/14479191/tftp-deploy-tqgh2cqp/dtb/mt8192-asurada-spherion-r0.dtb
81 00:24:29.893116 total size: 47258 (0 MB)
82 00:24:29.893169 No compression specified
83 00:24:29.894166 progress 69 % (0 MB)
84 00:24:29.894460 progress 100 % (0 MB)
85 00:24:29.894604 0 MB downloaded in 0.00 s (30.33 MB/s)
86 00:24:29.894713 end: 1.3.1 http-download (duration 00:00:00) [common]
88 00:24:29.894908 end: 1.3 download-retry (duration 00:00:00) [common]
89 00:24:29.894983 start: 1.4 download-retry (timeout 00:09:59) [common]
90 00:24:29.895056 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 00:24:29.895156 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.94-cip23/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 00:24:29.895216 saving as /var/lib/lava/dispatcher/tmp/14479191/tftp-deploy-tqgh2cqp/modules/modules.tar
93 00:24:29.895268 total size: 8618924 (8 MB)
94 00:24:29.895320 Using unxz to decompress xz
95 00:24:29.896675 progress 0 % (0 MB)
96 00:24:29.915490 progress 5 % (0 MB)
97 00:24:29.938705 progress 10 % (0 MB)
98 00:24:29.962685 progress 15 % (1 MB)
99 00:24:29.986252 progress 20 % (1 MB)
100 00:24:30.010108 progress 25 % (2 MB)
101 00:24:30.033643 progress 30 % (2 MB)
102 00:24:30.057861 progress 35 % (2 MB)
103 00:24:30.081231 progress 40 % (3 MB)
104 00:24:30.104642 progress 45 % (3 MB)
105 00:24:30.127368 progress 50 % (4 MB)
106 00:24:30.150883 progress 55 % (4 MB)
107 00:24:30.174102 progress 60 % (4 MB)
108 00:24:30.196527 progress 65 % (5 MB)
109 00:24:30.222522 progress 70 % (5 MB)
110 00:24:30.245956 progress 75 % (6 MB)
111 00:24:30.269157 progress 80 % (6 MB)
112 00:24:30.293063 progress 85 % (7 MB)
113 00:24:30.316677 progress 90 % (7 MB)
114 00:24:30.344281 progress 95 % (7 MB)
115 00:24:30.372741 progress 100 % (8 MB)
116 00:24:30.377104 8 MB downloaded in 0.48 s (17.06 MB/s)
117 00:24:30.377251 end: 1.4.1 http-download (duration 00:00:00) [common]
119 00:24:30.377461 end: 1.4 download-retry (duration 00:00:00) [common]
120 00:24:30.377541 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 00:24:30.377618 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 00:24:30.377688 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 00:24:30.377759 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 00:24:30.377917 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14479191/lava-overlay-b_l_0xxg
125 00:24:30.378033 makedir: /var/lib/lava/dispatcher/tmp/14479191/lava-overlay-b_l_0xxg/lava-14479191/bin
126 00:24:30.378122 makedir: /var/lib/lava/dispatcher/tmp/14479191/lava-overlay-b_l_0xxg/lava-14479191/tests
127 00:24:30.378207 makedir: /var/lib/lava/dispatcher/tmp/14479191/lava-overlay-b_l_0xxg/lava-14479191/results
128 00:24:30.378331 Creating /var/lib/lava/dispatcher/tmp/14479191/lava-overlay-b_l_0xxg/lava-14479191/bin/lava-add-keys
129 00:24:30.378457 Creating /var/lib/lava/dispatcher/tmp/14479191/lava-overlay-b_l_0xxg/lava-14479191/bin/lava-add-sources
130 00:24:30.378574 Creating /var/lib/lava/dispatcher/tmp/14479191/lava-overlay-b_l_0xxg/lava-14479191/bin/lava-background-process-start
131 00:24:30.378690 Creating /var/lib/lava/dispatcher/tmp/14479191/lava-overlay-b_l_0xxg/lava-14479191/bin/lava-background-process-stop
132 00:24:30.378813 Creating /var/lib/lava/dispatcher/tmp/14479191/lava-overlay-b_l_0xxg/lava-14479191/bin/lava-common-functions
133 00:24:30.378928 Creating /var/lib/lava/dispatcher/tmp/14479191/lava-overlay-b_l_0xxg/lava-14479191/bin/lava-echo-ipv4
134 00:24:30.379042 Creating /var/lib/lava/dispatcher/tmp/14479191/lava-overlay-b_l_0xxg/lava-14479191/bin/lava-install-packages
135 00:24:30.379153 Creating /var/lib/lava/dispatcher/tmp/14479191/lava-overlay-b_l_0xxg/lava-14479191/bin/lava-installed-packages
136 00:24:30.379262 Creating /var/lib/lava/dispatcher/tmp/14479191/lava-overlay-b_l_0xxg/lava-14479191/bin/lava-os-build
137 00:24:30.379373 Creating /var/lib/lava/dispatcher/tmp/14479191/lava-overlay-b_l_0xxg/lava-14479191/bin/lava-probe-channel
138 00:24:30.379485 Creating /var/lib/lava/dispatcher/tmp/14479191/lava-overlay-b_l_0xxg/lava-14479191/bin/lava-probe-ip
139 00:24:30.379595 Creating /var/lib/lava/dispatcher/tmp/14479191/lava-overlay-b_l_0xxg/lava-14479191/bin/lava-target-ip
140 00:24:30.379705 Creating /var/lib/lava/dispatcher/tmp/14479191/lava-overlay-b_l_0xxg/lava-14479191/bin/lava-target-mac
141 00:24:30.379816 Creating /var/lib/lava/dispatcher/tmp/14479191/lava-overlay-b_l_0xxg/lava-14479191/bin/lava-target-storage
142 00:24:30.379930 Creating /var/lib/lava/dispatcher/tmp/14479191/lava-overlay-b_l_0xxg/lava-14479191/bin/lava-test-case
143 00:24:30.380058 Creating /var/lib/lava/dispatcher/tmp/14479191/lava-overlay-b_l_0xxg/lava-14479191/bin/lava-test-event
144 00:24:30.380172 Creating /var/lib/lava/dispatcher/tmp/14479191/lava-overlay-b_l_0xxg/lava-14479191/bin/lava-test-feedback
145 00:24:30.380282 Creating /var/lib/lava/dispatcher/tmp/14479191/lava-overlay-b_l_0xxg/lava-14479191/bin/lava-test-raise
146 00:24:30.380396 Creating /var/lib/lava/dispatcher/tmp/14479191/lava-overlay-b_l_0xxg/lava-14479191/bin/lava-test-reference
147 00:24:30.380507 Creating /var/lib/lava/dispatcher/tmp/14479191/lava-overlay-b_l_0xxg/lava-14479191/bin/lava-test-runner
148 00:24:30.380617 Creating /var/lib/lava/dispatcher/tmp/14479191/lava-overlay-b_l_0xxg/lava-14479191/bin/lava-test-set
149 00:24:30.380727 Creating /var/lib/lava/dispatcher/tmp/14479191/lava-overlay-b_l_0xxg/lava-14479191/bin/lava-test-shell
150 00:24:30.380841 Updating /var/lib/lava/dispatcher/tmp/14479191/lava-overlay-b_l_0xxg/lava-14479191/bin/lava-install-packages (oe)
151 00:24:30.380977 Updating /var/lib/lava/dispatcher/tmp/14479191/lava-overlay-b_l_0xxg/lava-14479191/bin/lava-installed-packages (oe)
152 00:24:30.381092 Creating /var/lib/lava/dispatcher/tmp/14479191/lava-overlay-b_l_0xxg/lava-14479191/environment
153 00:24:30.381176 LAVA metadata
154 00:24:30.381241 - LAVA_JOB_ID=14479191
155 00:24:30.381303 - LAVA_DISPATCHER_IP=192.168.201.1
156 00:24:30.381393 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 00:24:30.381453 skipped lava-vland-overlay
158 00:24:30.381522 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 00:24:30.381592 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 00:24:30.381644 skipped lava-multinode-overlay
161 00:24:30.381708 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 00:24:30.381777 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 00:24:30.381839 Loading test definitions
164 00:24:30.381913 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 00:24:30.381973 Using /lava-14479191 at stage 0
166 00:24:30.382308 uuid=14479191_1.5.2.3.1 testdef=None
167 00:24:30.382397 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 00:24:30.382473 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 00:24:30.382910 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 00:24:30.383112 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 00:24:30.383671 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 00:24:30.383879 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 00:24:30.384417 runner path: /var/lib/lava/dispatcher/tmp/14479191/lava-overlay-b_l_0xxg/lava-14479191/0/tests/0_igt-gpu-panfrost test_uuid 14479191_1.5.2.3.1
176 00:24:30.384568 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 00:24:30.384775 Creating lava-test-runner.conf files
179 00:24:30.384832 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14479191/lava-overlay-b_l_0xxg/lava-14479191/0 for stage 0
180 00:24:30.384914 - 0_igt-gpu-panfrost
181 00:24:30.385004 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 00:24:30.385081 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 00:24:30.391035 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 00:24:30.391129 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 00:24:30.391207 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 00:24:30.391282 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 00:24:30.391356 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 00:24:32.066305 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:02) [common]
189 00:24:32.066452 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
190 00:24:32.066532 extracting modules file /var/lib/lava/dispatcher/tmp/14479191/tftp-deploy-tqgh2cqp/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14479191/extract-overlay-ramdisk-3rvchs06/ramdisk
191 00:24:32.287906 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 00:24:32.288042 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 00:24:32.288118 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14479191/compress-overlay-kp09sst6/overlay-1.5.2.4.tar.gz to ramdisk
194 00:24:32.288178 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14479191/compress-overlay-kp09sst6/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14479191/extract-overlay-ramdisk-3rvchs06/ramdisk
195 00:24:32.294502 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 00:24:32.294595 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 00:24:32.294674 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 00:24:32.294749 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 00:24:32.294819 Building ramdisk /var/lib/lava/dispatcher/tmp/14479191/extract-overlay-ramdisk-3rvchs06/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14479191/extract-overlay-ramdisk-3rvchs06/ramdisk
200 00:24:33.385812 >> 466070 blocks
201 00:24:39.590903 rename /var/lib/lava/dispatcher/tmp/14479191/extract-overlay-ramdisk-3rvchs06/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14479191/tftp-deploy-tqgh2cqp/ramdisk/ramdisk.cpio.gz
202 00:24:39.591114 end: 1.5.7 compress-ramdisk (duration 00:00:07) [common]
203 00:24:39.591201 start: 1.5.8 prepare-kernel (timeout 00:09:50) [common]
204 00:24:39.591279 start: 1.5.8.1 prepare-fit (timeout 00:09:50) [common]
205 00:24:39.591356 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14479191/tftp-deploy-tqgh2cqp/kernel/Image']
206 00:24:52.603914 Returned 0 in 13 seconds
207 00:24:52.704743 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14479191/tftp-deploy-tqgh2cqp/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14479191/tftp-deploy-tqgh2cqp/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14479191/tftp-deploy-tqgh2cqp/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14479191/tftp-deploy-tqgh2cqp/kernel/image.itb
208 00:24:53.744228 output: FIT description: Kernel Image image with one or more FDT blobs
209 00:24:53.744367 output: Created: Fri Jun 21 01:24:53 2024
210 00:24:53.744432 output: Image 0 (kernel-1)
211 00:24:53.744488 output: Description:
212 00:24:53.744546 output: Created: Fri Jun 21 01:24:53 2024
213 00:24:53.744606 output: Type: Kernel Image
214 00:24:53.744665 output: Compression: lzma compressed
215 00:24:53.744724 output: Data Size: 13124896 Bytes = 12817.28 KiB = 12.52 MiB
216 00:24:53.744781 output: Architecture: AArch64
217 00:24:53.744837 output: OS: Linux
218 00:24:53.744893 output: Load Address: 0x00000000
219 00:24:53.744947 output: Entry Point: 0x00000000
220 00:24:53.745000 output: Hash algo: crc32
221 00:24:53.745053 output: Hash value: ab2f7826
222 00:24:53.745104 output: Image 1 (fdt-1)
223 00:24:53.745155 output: Description: mt8192-asurada-spherion-r0
224 00:24:53.745205 output: Created: Fri Jun 21 01:24:53 2024
225 00:24:53.745255 output: Type: Flat Device Tree
226 00:24:53.745303 output: Compression: uncompressed
227 00:24:53.745351 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 00:24:53.745400 output: Architecture: AArch64
229 00:24:53.745446 output: Hash algo: crc32
230 00:24:53.745494 output: Hash value: 0f8e4d2e
231 00:24:53.745541 output: Image 2 (ramdisk-1)
232 00:24:53.745588 output: Description: unavailable
233 00:24:53.745635 output: Created: Fri Jun 21 01:24:53 2024
234 00:24:53.745684 output: Type: RAMDisk Image
235 00:24:53.745731 output: Compression: uncompressed
236 00:24:53.745778 output: Data Size: 61003990 Bytes = 59574.21 KiB = 58.18 MiB
237 00:24:53.745825 output: Architecture: AArch64
238 00:24:53.745871 output: OS: Linux
239 00:24:53.745917 output: Load Address: unavailable
240 00:24:53.745964 output: Entry Point: unavailable
241 00:24:53.746011 output: Hash algo: crc32
242 00:24:53.746057 output: Hash value: e2b8d678
243 00:24:53.746102 output: Default Configuration: 'conf-1'
244 00:24:53.746149 output: Configuration 0 (conf-1)
245 00:24:53.746196 output: Description: mt8192-asurada-spherion-r0
246 00:24:53.746274 output: Kernel: kernel-1
247 00:24:53.746334 output: Init Ramdisk: ramdisk-1
248 00:24:53.746382 output: FDT: fdt-1
249 00:24:53.746430 output: Loadables: kernel-1
250 00:24:53.746477 output:
251 00:24:53.746614 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 00:24:53.746697 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 00:24:53.746784 end: 1.5 prepare-tftp-overlay (duration 00:00:23) [common]
254 00:24:53.746866 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:36) [common]
255 00:24:53.746933 No LXC device requested
256 00:24:53.747005 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 00:24:53.747080 start: 1.7 deploy-device-env (timeout 00:09:36) [common]
258 00:24:53.747150 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 00:24:53.747209 Checking files for TFTP limit of 4294967296 bytes.
260 00:24:53.747708 end: 1 tftp-deploy (duration 00:00:24) [common]
261 00:24:53.747806 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 00:24:53.747886 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 00:24:53.747994 substitutions:
264 00:24:53.748052 - {DTB}: 14479191/tftp-deploy-tqgh2cqp/dtb/mt8192-asurada-spherion-r0.dtb
265 00:24:53.748110 - {INITRD}: 14479191/tftp-deploy-tqgh2cqp/ramdisk/ramdisk.cpio.gz
266 00:24:53.748161 - {KERNEL}: 14479191/tftp-deploy-tqgh2cqp/kernel/Image
267 00:24:53.748210 - {LAVA_MAC}: None
268 00:24:53.748260 - {PRESEED_CONFIG}: None
269 00:24:53.748308 - {PRESEED_LOCAL}: None
270 00:24:53.748356 - {RAMDISK}: 14479191/tftp-deploy-tqgh2cqp/ramdisk/ramdisk.cpio.gz
271 00:24:53.748409 - {ROOT_PART}: None
272 00:24:53.748458 - {ROOT}: None
273 00:24:53.748506 - {SERVER_IP}: 192.168.201.1
274 00:24:53.748554 - {TEE}: None
275 00:24:53.748602 Parsed boot commands:
276 00:24:53.748649 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 00:24:53.748795 Parsed boot commands: tftpboot 192.168.201.1 14479191/tftp-deploy-tqgh2cqp/kernel/image.itb 14479191/tftp-deploy-tqgh2cqp/kernel/cmdline
278 00:24:53.748874 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 00:24:53.748948 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 00:24:53.749026 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 00:24:53.749099 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 00:24:53.749156 Not connected, no need to disconnect.
283 00:24:53.749221 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 00:24:53.749290 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 00:24:53.749348 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
286 00:24:53.752604 Setting prompt string to ['lava-test: # ']
287 00:24:53.752902 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 00:24:53.752993 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 00:24:53.753083 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 00:24:53.753204 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 00:24:53.753419 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-4', '--port=1', '--command=reboot']
292 00:25:02.991589 >> Command sent successfully.
293 00:25:03.006315 Returned 0 in 9 seconds
294 00:25:03.107530 end: 2.2.2.1 pdu-reboot (duration 00:00:09) [common]
296 00:25:03.108844 end: 2.2.2 reset-device (duration 00:00:09) [common]
297 00:25:03.109344 start: 2.2.3 depthcharge-start (timeout 00:04:51) [common]
298 00:25:03.109803 Setting prompt string to 'Starting depthcharge on Spherion...'
299 00:25:03.110149 Changing prompt to 'Starting depthcharge on Spherion...'
300 00:25:03.110566 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 00:25:03.112416 [Enter `^Ec?' for help]
302 00:25:04.277531
303 00:25:04.278067
304 00:25:04.278473 F0: 102B 0000
305 00:25:04.278832
306 00:25:04.279178 F3: 1001 0000 [0200]
307 00:25:04.281038
308 00:25:04.281493 F3: 1001 0000
309 00:25:04.281860
310 00:25:04.282188 F7: 102D 0000
311 00:25:04.282543
312 00:25:04.284017 F1: 0000 0000
313 00:25:04.284463
314 00:25:04.284789 V0: 0000 0000 [0001]
315 00:25:04.285118
316 00:25:04.287442 00: 0007 8000
317 00:25:04.287879
318 00:25:04.288208 01: 0000 0000
319 00:25:04.288582
320 00:25:04.290805 BP: 0C00 0209 [0000]
321 00:25:04.291335
322 00:25:04.291669 G0: 1182 0000
323 00:25:04.291978
324 00:25:04.294636 EC: 0000 0021 [4000]
325 00:25:04.295137
326 00:25:04.295468 S7: 0000 0000 [0000]
327 00:25:04.295772
328 00:25:04.297781 CC: 0000 0000 [0001]
329 00:25:04.298207
330 00:25:04.298562 T0: 0000 0040 [010F]
331 00:25:04.298981
332 00:25:04.300766 Jump to BL
333 00:25:04.301268
334 00:25:04.324449
335 00:25:04.324977
336 00:25:04.335010 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
337 00:25:04.337908 ARM64: Exception handlers installed.
338 00:25:04.338398 ARM64: Testing exception
339 00:25:04.340910 ARM64: Done test exception
340 00:25:04.347776 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
341 00:25:04.357909 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
342 00:25:04.364676 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
343 00:25:04.375001 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
344 00:25:04.381717 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
345 00:25:04.392241 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
346 00:25:04.401981 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
347 00:25:04.408709 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
348 00:25:04.427344 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
349 00:25:04.430609 WDT: Last reset was cold boot
350 00:25:04.433986 SPI1(PAD0) initialized at 2873684 Hz
351 00:25:04.437364 SPI5(PAD0) initialized at 992727 Hz
352 00:25:04.440892 VBOOT: Loading verstage.
353 00:25:04.447623 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
354 00:25:04.450841 FMAP: Found "FLASH" version 1.1 at 0x20000.
355 00:25:04.454310 FMAP: base = 0x0 size = 0x800000 #areas = 25
356 00:25:04.457397 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
357 00:25:04.464824 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
358 00:25:04.471914 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
359 00:25:04.482658 read SPI 0x96554 0xa1eb: 4594 us, 9022 KB/s, 72.176 Mbps
360 00:25:04.483171
361 00:25:04.483505
362 00:25:04.492554 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
363 00:25:04.496079 ARM64: Exception handlers installed.
364 00:25:04.499382 ARM64: Testing exception
365 00:25:04.499896 ARM64: Done test exception
366 00:25:04.506362 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
367 00:25:04.509251 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
368 00:25:04.524309 Probing TPM: . done!
369 00:25:04.524830 TPM ready after 0 ms
370 00:25:04.530078 Connected to device vid:did:rid of 1ae0:0028:00
371 00:25:04.537232 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
372 00:25:04.540729 Initialized TPM device CR50 revision 0
373 00:25:04.587941 tlcl_send_startup: Startup return code is 0
374 00:25:04.588473 TPM: setup succeeded
375 00:25:04.599142 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
376 00:25:04.608065 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
377 00:25:04.618042 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
378 00:25:04.626987 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
379 00:25:04.630304 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
380 00:25:04.633687 in-header: 03 07 00 00 08 00 00 00
381 00:25:04.636632 in-data: aa e4 47 04 13 02 00 00
382 00:25:04.639935 Chrome EC: UHEPI supported
383 00:25:04.646848 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
384 00:25:04.650608 in-header: 03 a9 00 00 08 00 00 00
385 00:25:04.653267 in-data: 84 60 60 08 00 00 00 00
386 00:25:04.653694 Phase 1
387 00:25:04.657447 FMAP: area GBB found @ 3f5000 (12032 bytes)
388 00:25:04.663451 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
389 00:25:04.670265 VB2:vb2_check_recovery() Recovery was requested manually
390 00:25:04.673607 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
391 00:25:04.677201 Recovery requested (1009000e)
392 00:25:04.685113 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 00:25:04.690812 tlcl_extend: response is 0
394 00:25:04.701054 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 00:25:04.704463 tlcl_extend: response is 0
396 00:25:04.711090 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 00:25:04.731517 read SPI 0x210d4 0x2173b: 15144 us, 9047 KB/s, 72.376 Mbps
398 00:25:04.737635 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 00:25:04.738195
400 00:25:04.738596
401 00:25:04.748310 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 00:25:04.751024 ARM64: Exception handlers installed.
403 00:25:04.754504 ARM64: Testing exception
404 00:25:04.754949 ARM64: Done test exception
405 00:25:04.776688 pmic_efuse_setting: Set efuses in 11 msecs
406 00:25:04.780300 pmwrap_interface_init: Select PMIF_VLD_RDY
407 00:25:04.786813 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 00:25:04.790196 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 00:25:04.797157 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 00:25:04.800309 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 00:25:04.807101 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 00:25:04.811039 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 00:25:04.813851 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 00:25:04.820367 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 00:25:04.823477 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 00:25:04.830834 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 00:25:04.833459 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 00:25:04.836983 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 00:25:04.843656 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 00:25:04.850734 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 00:25:04.853315 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 00:25:04.860680 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 00:25:04.867021 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 00:25:04.870143 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 00:25:04.876812 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 00:25:04.883955 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 00:25:04.890255 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 00:25:04.893377 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 00:25:04.900465 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 00:25:04.906644 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 00:25:04.910104 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 00:25:04.916797 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 00:25:04.920160 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 00:25:04.926555 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 00:25:04.929988 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 00:25:04.936511 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 00:25:04.939799 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 00:25:04.946321 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 00:25:04.949874 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 00:25:04.956642 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 00:25:04.959991 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 00:25:04.966286 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 00:25:04.969616 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 00:25:04.976627 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 00:25:04.979958 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 00:25:04.983213 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 00:25:04.990283 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 00:25:04.993577 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 00:25:04.997007 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 00:25:05.003676 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 00:25:05.006919 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 00:25:05.010334 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 00:25:05.013691 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 00:25:05.019972 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 00:25:05.023830 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 00:25:05.026622 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 00:25:05.030153 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 00:25:05.040095 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
459 00:25:05.047340 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 00:25:05.054026 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 00:25:05.060944 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 00:25:05.070884 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 00:25:05.073544 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 00:25:05.077085 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 00:25:05.083462 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 00:25:05.090414 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x38
467 00:25:05.096852 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 00:25:05.100128 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 00:25:05.103273 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 00:25:05.114327 [RTC]rtc_get_frequency_meter,154: input=15, output=764
471 00:25:05.123818 [RTC]rtc_get_frequency_meter,154: input=23, output=949
472 00:25:05.132913 [RTC]rtc_get_frequency_meter,154: input=19, output=858
473 00:25:05.142635 [RTC]rtc_get_frequency_meter,154: input=17, output=811
474 00:25:05.152185 [RTC]rtc_get_frequency_meter,154: input=16, output=788
475 00:25:05.162099 [RTC]rtc_get_frequency_meter,154: input=16, output=788
476 00:25:05.171863 [RTC]rtc_get_frequency_meter,154: input=17, output=811
477 00:25:05.174683 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
478 00:25:05.182029 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
479 00:25:05.185638 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 00:25:05.188547 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
481 00:25:05.194991 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 00:25:05.198158 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
483 00:25:05.201723 ADC[4]: Raw value=670800 ID=5
484 00:25:05.202275 ADC[3]: Raw value=212549 ID=1
485 00:25:05.205423 RAM Code: 0x51
486 00:25:05.208445 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 00:25:05.215122 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 00:25:05.221666 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
489 00:25:05.228200 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
490 00:25:05.231643 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 00:25:05.235212 in-header: 03 07 00 00 08 00 00 00
492 00:25:05.238871 in-data: aa e4 47 04 13 02 00 00
493 00:25:05.241445 Chrome EC: UHEPI supported
494 00:25:05.248276 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 00:25:05.251932 in-header: 03 a9 00 00 08 00 00 00
496 00:25:05.254885 in-data: 84 60 60 08 00 00 00 00
497 00:25:05.257935 MRC: failed to locate region type 0.
498 00:25:05.261838 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 00:25:05.265050 DRAM-K: Running full calibration
500 00:25:05.271405 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
501 00:25:05.274606 header.status = 0x0
502 00:25:05.278325 header.version = 0x6 (expected: 0x6)
503 00:25:05.281514 header.size = 0xd00 (expected: 0xd00)
504 00:25:05.282091 header.flags = 0x0
505 00:25:05.287961 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 00:25:05.306326 read SPI 0x72590 0x1c583: 12502 us, 9286 KB/s, 74.288 Mbps
507 00:25:05.312750 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 00:25:05.316107 dram_init: ddr_geometry: 0
509 00:25:05.319429 [EMI] MDL number = 0
510 00:25:05.319859 [EMI] Get MDL freq = 0
511 00:25:05.323064 dram_init: ddr_type: 0
512 00:25:05.323492 is_discrete_lpddr4: 1
513 00:25:05.326596 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 00:25:05.327035
515 00:25:05.327363
516 00:25:05.329448 [Bian_co] ETT version 0.0.0.1
517 00:25:05.336043 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
518 00:25:05.336499
519 00:25:05.339086 dramc_set_vcore_voltage set vcore to 650000
520 00:25:05.339532 Read voltage for 800, 4
521 00:25:05.342743 Vio18 = 0
522 00:25:05.343484 Vcore = 650000
523 00:25:05.344011 Vdram = 0
524 00:25:05.346098 Vddq = 0
525 00:25:05.346576 Vmddr = 0
526 00:25:05.349326 dram_init: config_dvfs: 1
527 00:25:05.352899 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 00:25:05.359500 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 00:25:05.363163 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
530 00:25:05.366160 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
531 00:25:05.369502 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
532 00:25:05.372945 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
533 00:25:05.376132 MEM_TYPE=3, freq_sel=18
534 00:25:05.379444 sv_algorithm_assistance_LP4_1600
535 00:25:05.382939 ============ PULL DRAM RESETB DOWN ============
536 00:25:05.386071 ========== PULL DRAM RESETB DOWN end =========
537 00:25:05.392775 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 00:25:05.396562 ===================================
539 00:25:05.397075 LPDDR4 DRAM CONFIGURATION
540 00:25:05.399909 ===================================
541 00:25:05.402839 EX_ROW_EN[0] = 0x0
542 00:25:05.406187 EX_ROW_EN[1] = 0x0
543 00:25:05.406754 LP4Y_EN = 0x0
544 00:25:05.409681 WORK_FSP = 0x0
545 00:25:05.410245 WL = 0x2
546 00:25:05.412907 RL = 0x2
547 00:25:05.413338 BL = 0x2
548 00:25:05.416480 RPST = 0x0
549 00:25:05.417265 RD_PRE = 0x0
550 00:25:05.419326 WR_PRE = 0x1
551 00:25:05.419754 WR_PST = 0x0
552 00:25:05.423331 DBI_WR = 0x0
553 00:25:05.423762 DBI_RD = 0x0
554 00:25:05.426109 OTF = 0x1
555 00:25:05.429825 ===================================
556 00:25:05.433218 ===================================
557 00:25:05.433731 ANA top config
558 00:25:05.436179 ===================================
559 00:25:05.439674 DLL_ASYNC_EN = 0
560 00:25:05.443101 ALL_SLAVE_EN = 1
561 00:25:05.446049 NEW_RANK_MODE = 1
562 00:25:05.446589 DLL_IDLE_MODE = 1
563 00:25:05.449753 LP45_APHY_COMB_EN = 1
564 00:25:05.452750 TX_ODT_DIS = 1
565 00:25:05.456014 NEW_8X_MODE = 1
566 00:25:05.459649 ===================================
567 00:25:05.462659 ===================================
568 00:25:05.466628 data_rate = 1600
569 00:25:05.467140 CKR = 1
570 00:25:05.469599 DQ_P2S_RATIO = 8
571 00:25:05.472667 ===================================
572 00:25:05.476345 CA_P2S_RATIO = 8
573 00:25:05.479658 DQ_CA_OPEN = 0
574 00:25:05.482813 DQ_SEMI_OPEN = 0
575 00:25:05.483321 CA_SEMI_OPEN = 0
576 00:25:05.486144 CA_FULL_RATE = 0
577 00:25:05.490377 DQ_CKDIV4_EN = 1
578 00:25:05.492878 CA_CKDIV4_EN = 1
579 00:25:05.496156 CA_PREDIV_EN = 0
580 00:25:05.499454 PH8_DLY = 0
581 00:25:05.499980 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 00:25:05.503131 DQ_AAMCK_DIV = 4
583 00:25:05.506509 CA_AAMCK_DIV = 4
584 00:25:05.509959 CA_ADMCK_DIV = 4
585 00:25:05.512885 DQ_TRACK_CA_EN = 0
586 00:25:05.516433 CA_PICK = 800
587 00:25:05.516862 CA_MCKIO = 800
588 00:25:05.519389 MCKIO_SEMI = 0
589 00:25:05.523501 PLL_FREQ = 3068
590 00:25:05.526558 DQ_UI_PI_RATIO = 32
591 00:25:05.529700 CA_UI_PI_RATIO = 0
592 00:25:05.533355 ===================================
593 00:25:05.536594 ===================================
594 00:25:05.539734 memory_type:LPDDR4
595 00:25:05.540179 GP_NUM : 10
596 00:25:05.542810 SRAM_EN : 1
597 00:25:05.543325 MD32_EN : 0
598 00:25:05.546114 ===================================
599 00:25:05.549670 [ANA_INIT] >>>>>>>>>>>>>>
600 00:25:05.553004 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 00:25:05.556688 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 00:25:05.559533 ===================================
603 00:25:05.562889 data_rate = 1600,PCW = 0X7600
604 00:25:05.566598 ===================================
605 00:25:05.569487 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 00:25:05.573052 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 00:25:05.579806 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 00:25:05.582945 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 00:25:05.589948 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 00:25:05.593198 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 00:25:05.593716 [ANA_INIT] flow start
612 00:25:05.596613 [ANA_INIT] PLL >>>>>>>>
613 00:25:05.597124 [ANA_INIT] PLL <<<<<<<<
614 00:25:05.599825 [ANA_INIT] MIDPI >>>>>>>>
615 00:25:05.603049 [ANA_INIT] MIDPI <<<<<<<<
616 00:25:05.606600 [ANA_INIT] DLL >>>>>>>>
617 00:25:05.607117 [ANA_INIT] flow end
618 00:25:05.610015 ============ LP4 DIFF to SE enter ============
619 00:25:05.616630 ============ LP4 DIFF to SE exit ============
620 00:25:05.617149 [ANA_INIT] <<<<<<<<<<<<<
621 00:25:05.620344 [Flow] Enable top DCM control >>>>>
622 00:25:05.622870 [Flow] Enable top DCM control <<<<<
623 00:25:05.626688 Enable DLL master slave shuffle
624 00:25:05.632831 ==============================================================
625 00:25:05.633333 Gating Mode config
626 00:25:05.639708 ==============================================================
627 00:25:05.643316 Config description:
628 00:25:05.653385 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 00:25:05.656519 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 00:25:05.662810 SELPH_MODE 0: By rank 1: By Phase
631 00:25:05.669810 ==============================================================
632 00:25:05.673138 GAT_TRACK_EN = 1
633 00:25:05.673696 RX_GATING_MODE = 2
634 00:25:05.676191 RX_GATING_TRACK_MODE = 2
635 00:25:05.679561 SELPH_MODE = 1
636 00:25:05.682852 PICG_EARLY_EN = 1
637 00:25:05.686242 VALID_LAT_VALUE = 1
638 00:25:05.693274 ==============================================================
639 00:25:05.696593 Enter into Gating configuration >>>>
640 00:25:05.700022 Exit from Gating configuration <<<<
641 00:25:05.703234 Enter into DVFS_PRE_config >>>>>
642 00:25:05.713201 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 00:25:05.716711 Exit from DVFS_PRE_config <<<<<
644 00:25:05.719635 Enter into PICG configuration >>>>
645 00:25:05.722951 Exit from PICG configuration <<<<
646 00:25:05.725924 [RX_INPUT] configuration >>>>>
647 00:25:05.726394 [RX_INPUT] configuration <<<<<
648 00:25:05.732999 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 00:25:05.739412 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 00:25:05.742970 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 00:25:05.749360 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 00:25:05.756706 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 00:25:05.762976 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 00:25:05.766597 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 00:25:05.769373 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 00:25:05.776146 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 00:25:05.779197 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 00:25:05.783552 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 00:25:05.789515 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 00:25:05.793295 ===================================
661 00:25:05.793806 LPDDR4 DRAM CONFIGURATION
662 00:25:05.796299 ===================================
663 00:25:05.799527 EX_ROW_EN[0] = 0x0
664 00:25:05.799958 EX_ROW_EN[1] = 0x0
665 00:25:05.803172 LP4Y_EN = 0x0
666 00:25:05.803682 WORK_FSP = 0x0
667 00:25:05.806386 WL = 0x2
668 00:25:05.809250 RL = 0x2
669 00:25:05.809678 BL = 0x2
670 00:25:05.812973 RPST = 0x0
671 00:25:05.813482 RD_PRE = 0x0
672 00:25:05.816639 WR_PRE = 0x1
673 00:25:05.817155 WR_PST = 0x0
674 00:25:05.819422 DBI_WR = 0x0
675 00:25:05.819850 DBI_RD = 0x0
676 00:25:05.822840 OTF = 0x1
677 00:25:05.825981 ===================================
678 00:25:05.829300 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 00:25:05.832665 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 00:25:05.836139 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 00:25:05.839112 ===================================
682 00:25:05.842748 LPDDR4 DRAM CONFIGURATION
683 00:25:05.846387 ===================================
684 00:25:05.849869 EX_ROW_EN[0] = 0x10
685 00:25:05.850324 EX_ROW_EN[1] = 0x0
686 00:25:05.852789 LP4Y_EN = 0x0
687 00:25:05.853281 WORK_FSP = 0x0
688 00:25:05.856047 WL = 0x2
689 00:25:05.856468 RL = 0x2
690 00:25:05.859277 BL = 0x2
691 00:25:05.859705 RPST = 0x0
692 00:25:05.862840 RD_PRE = 0x0
693 00:25:05.863263 WR_PRE = 0x1
694 00:25:05.865823 WR_PST = 0x0
695 00:25:05.866290 DBI_WR = 0x0
696 00:25:05.869411 DBI_RD = 0x0
697 00:25:05.872804 OTF = 0x1
698 00:25:05.873228 ===================================
699 00:25:05.879150 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 00:25:05.884400 nWR fixed to 40
701 00:25:05.887760 [ModeRegInit_LP4] CH0 RK0
702 00:25:05.888287 [ModeRegInit_LP4] CH0 RK1
703 00:25:05.890865 [ModeRegInit_LP4] CH1 RK0
704 00:25:05.894684 [ModeRegInit_LP4] CH1 RK1
705 00:25:05.895280 match AC timing 12
706 00:25:05.902106 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
707 00:25:05.904160 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 00:25:05.907407 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 00:25:05.914560 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 00:25:05.917842 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 00:25:05.918392 [EMI DOE] emi_dcm 0
712 00:25:05.924147 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 00:25:05.924641 ==
714 00:25:05.927492 Dram Type= 6, Freq= 0, CH_0, rank 0
715 00:25:05.930709 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
716 00:25:05.931139 ==
717 00:25:05.937298 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 00:25:05.944290 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 00:25:05.951681 [CA 0] Center 37 (7~68) winsize 62
720 00:25:05.955344 [CA 1] Center 37 (7~68) winsize 62
721 00:25:05.958269 [CA 2] Center 35 (5~66) winsize 62
722 00:25:05.962364 [CA 3] Center 35 (4~66) winsize 63
723 00:25:05.964918 [CA 4] Center 34 (3~65) winsize 63
724 00:25:05.968689 [CA 5] Center 33 (3~64) winsize 62
725 00:25:05.969214
726 00:25:05.971842 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 00:25:05.972349
728 00:25:05.975381 [CATrainingPosCal] consider 1 rank data
729 00:25:05.978853 u2DelayCellTimex100 = 270/100 ps
730 00:25:05.982360 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
731 00:25:05.985937 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
732 00:25:05.989292 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
733 00:25:05.992641 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
734 00:25:05.999098 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
735 00:25:06.002608 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
736 00:25:06.003113
737 00:25:06.005862 CA PerBit enable=1, Macro0, CA PI delay=33
738 00:25:06.006393
739 00:25:06.009270 [CBTSetCACLKResult] CA Dly = 33
740 00:25:06.009783 CS Dly: 5 (0~36)
741 00:25:06.010114 ==
742 00:25:06.012634 Dram Type= 6, Freq= 0, CH_0, rank 1
743 00:25:06.018909 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
744 00:25:06.019404 ==
745 00:25:06.022629 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 00:25:06.028827 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 00:25:06.038077 [CA 0] Center 37 (7~68) winsize 62
748 00:25:06.040994 [CA 1] Center 37 (6~68) winsize 63
749 00:25:06.045057 [CA 2] Center 35 (4~66) winsize 63
750 00:25:06.047487 [CA 3] Center 35 (4~66) winsize 63
751 00:25:06.050776 [CA 4] Center 33 (3~64) winsize 62
752 00:25:06.054157 [CA 5] Center 34 (3~65) winsize 63
753 00:25:06.054616
754 00:25:06.057803 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 00:25:06.058268
756 00:25:06.061073 [CATrainingPosCal] consider 2 rank data
757 00:25:06.064554 u2DelayCellTimex100 = 270/100 ps
758 00:25:06.068004 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
759 00:25:06.070700 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
760 00:25:06.077423 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
761 00:25:06.080598 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
762 00:25:06.084042 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
763 00:25:06.087585 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
764 00:25:06.088015
765 00:25:06.091036 CA PerBit enable=1, Macro0, CA PI delay=33
766 00:25:06.091468
767 00:25:06.094366 [CBTSetCACLKResult] CA Dly = 33
768 00:25:06.094800 CS Dly: 5 (0~37)
769 00:25:06.097845
770 00:25:06.100841 ----->DramcWriteLeveling(PI) begin...
771 00:25:06.101279 ==
772 00:25:06.104047 Dram Type= 6, Freq= 0, CH_0, rank 0
773 00:25:06.107398 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
774 00:25:06.107835 ==
775 00:25:06.110910 Write leveling (Byte 0): 31 => 31
776 00:25:06.114200 Write leveling (Byte 1): 30 => 30
777 00:25:06.117551 DramcWriteLeveling(PI) end<-----
778 00:25:06.117937
779 00:25:06.118270 ==
780 00:25:06.121092 Dram Type= 6, Freq= 0, CH_0, rank 0
781 00:25:06.124044 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
782 00:25:06.124478 ==
783 00:25:06.127788 [Gating] SW mode calibration
784 00:25:06.134819 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 00:25:06.137808 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 00:25:06.144602 0 6 0 | B1->B0 | 3434 2f2f | 0 1 | (0 0) (1 1)
787 00:25:06.147433 0 6 4 | B1->B0 | 2d2d 2727 | 0 0 | (0 0) (0 0)
788 00:25:06.150981 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 00:25:06.157705 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 00:25:06.160702 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 00:25:06.164265 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 00:25:06.171386 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 00:25:06.174482 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 00:25:06.178018 0 7 0 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
795 00:25:06.184217 0 7 4 | B1->B0 | 3b3b 4242 | 0 0 | (0 0) (0 0)
796 00:25:06.187841 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
797 00:25:06.191301 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
798 00:25:06.197787 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
799 00:25:06.201173 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
800 00:25:06.204717 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
801 00:25:06.211417 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
802 00:25:06.214319 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
803 00:25:06.218167 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
804 00:25:06.221262 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
805 00:25:06.227816 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
806 00:25:06.231513 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
807 00:25:06.234480 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
808 00:25:06.241497 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
809 00:25:06.244590 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
810 00:25:06.247747 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
811 00:25:06.254741 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
812 00:25:06.257839 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
813 00:25:06.261500 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
814 00:25:06.268521 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
815 00:25:06.271202 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
816 00:25:06.274321 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
817 00:25:06.281176 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
818 00:25:06.284799 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
819 00:25:06.288102 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
820 00:25:06.291120 Total UI for P1: 0, mck2ui 16
821 00:25:06.294865 best dqsien dly found for B0: ( 0, 10, 2)
822 00:25:06.298084 Total UI for P1: 0, mck2ui 16
823 00:25:06.301106 best dqsien dly found for B1: ( 0, 10, 0)
824 00:25:06.304809 best DQS0 dly(MCK, UI, PI) = (0, 10, 2)
825 00:25:06.308347 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
826 00:25:06.308855
827 00:25:06.311987 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 2)
828 00:25:06.317624 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
829 00:25:06.318119 [Gating] SW calibration Done
830 00:25:06.318494 ==
831 00:25:06.321415 Dram Type= 6, Freq= 0, CH_0, rank 0
832 00:25:06.327956 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
833 00:25:06.328452 ==
834 00:25:06.328783 RX Vref Scan: 0
835 00:25:06.329087
836 00:25:06.331773 RX Vref 0 -> 0, step: 1
837 00:25:06.332200
838 00:25:06.334754 RX Delay -130 -> 252, step: 16
839 00:25:06.337804 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
840 00:25:06.341855 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
841 00:25:06.344245 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
842 00:25:06.350916 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
843 00:25:06.354569 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
844 00:25:06.357905 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
845 00:25:06.361111 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
846 00:25:06.364854 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
847 00:25:06.368003 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
848 00:25:06.374605 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
849 00:25:06.378595 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
850 00:25:06.381281 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
851 00:25:06.384394 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
852 00:25:06.391587 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
853 00:25:06.394365 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
854 00:25:06.397984 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
855 00:25:06.398543 ==
856 00:25:06.401226 Dram Type= 6, Freq= 0, CH_0, rank 0
857 00:25:06.404636 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
858 00:25:06.405154 ==
859 00:25:06.408399 DQS Delay:
860 00:25:06.408910 DQS0 = 0, DQS1 = 0
861 00:25:06.411467 DQM Delay:
862 00:25:06.411977 DQM0 = 81, DQM1 = 75
863 00:25:06.412309 DQ Delay:
864 00:25:06.414740 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
865 00:25:06.417824 DQ4 =77, DQ5 =69, DQ6 =93, DQ7 =93
866 00:25:06.421254 DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =69
867 00:25:06.424564 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
868 00:25:06.425074
869 00:25:06.425407
870 00:25:06.425710 ==
871 00:25:06.428168 Dram Type= 6, Freq= 0, CH_0, rank 0
872 00:25:06.434374 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
873 00:25:06.434901 ==
874 00:25:06.435233
875 00:25:06.435539
876 00:25:06.435829 TX Vref Scan disable
877 00:25:06.438048 == TX Byte 0 ==
878 00:25:06.441491 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
879 00:25:06.444938 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
880 00:25:06.448286 == TX Byte 1 ==
881 00:25:06.451480 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
882 00:25:06.454966 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
883 00:25:06.458065 ==
884 00:25:06.461950 Dram Type= 6, Freq= 0, CH_0, rank 0
885 00:25:06.464838 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
886 00:25:06.465354 ==
887 00:25:06.477099 TX Vref=22, minBit 0, minWin=27, winSum=445
888 00:25:06.480826 TX Vref=24, minBit 4, minWin=27, winSum=448
889 00:25:06.483865 TX Vref=26, minBit 1, minWin=28, winSum=452
890 00:25:06.487689 TX Vref=28, minBit 0, minWin=28, winSum=456
891 00:25:06.490770 TX Vref=30, minBit 0, minWin=28, winSum=457
892 00:25:06.493786 TX Vref=32, minBit 0, minWin=28, winSum=454
893 00:25:06.500369 [TxChooseVref] Worse bit 0, Min win 28, Win sum 457, Final Vref 30
894 00:25:06.500807
895 00:25:06.503979 Final TX Range 1 Vref 30
896 00:25:06.504622
897 00:25:06.504969 ==
898 00:25:06.507095 Dram Type= 6, Freq= 0, CH_0, rank 0
899 00:25:06.510943 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
900 00:25:06.511459 ==
901 00:25:06.511794
902 00:25:06.512100
903 00:25:06.513836 TX Vref Scan disable
904 00:25:06.517555 == TX Byte 0 ==
905 00:25:06.521085 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
906 00:25:06.524130 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
907 00:25:06.527070 == TX Byte 1 ==
908 00:25:06.530604 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
909 00:25:06.533665 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
910 00:25:06.537098
911 00:25:06.537604 [DATLAT]
912 00:25:06.537939 Freq=800, CH0 RK0
913 00:25:06.538301
914 00:25:06.540387 DATLAT Default: 0xa
915 00:25:06.540816 0, 0xFFFF, sum = 0
916 00:25:06.544044 1, 0xFFFF, sum = 0
917 00:25:06.544544 2, 0xFFFF, sum = 0
918 00:25:06.547014 3, 0xFFFF, sum = 0
919 00:25:06.547451 4, 0xFFFF, sum = 0
920 00:25:06.550412 5, 0xFFFF, sum = 0
921 00:25:06.550854 6, 0xFFFF, sum = 0
922 00:25:06.553459 7, 0xFFFF, sum = 0
923 00:25:06.553905 8, 0x0, sum = 1
924 00:25:06.557365 9, 0x0, sum = 2
925 00:25:06.557804 10, 0x0, sum = 3
926 00:25:06.560879 11, 0x0, sum = 4
927 00:25:06.561692 best_step = 9
928 00:25:06.562307
929 00:25:06.562645 ==
930 00:25:06.563815 Dram Type= 6, Freq= 0, CH_0, rank 0
931 00:25:06.570360 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
932 00:25:06.571039 ==
933 00:25:06.571606 RX Vref Scan: 1
934 00:25:06.572081
935 00:25:06.573748 Set Vref Range= 32 -> 127
936 00:25:06.574256
937 00:25:06.577318 RX Vref 32 -> 127, step: 1
938 00:25:06.578131
939 00:25:06.578657 RX Delay -111 -> 252, step: 8
940 00:25:06.580284
941 00:25:06.580720 Set Vref, RX VrefLevel [Byte0]: 32
942 00:25:06.583542 [Byte1]: 32
943 00:25:06.587905
944 00:25:06.588333 Set Vref, RX VrefLevel [Byte0]: 33
945 00:25:06.591381 [Byte1]: 33
946 00:25:06.595849
947 00:25:06.596276 Set Vref, RX VrefLevel [Byte0]: 34
948 00:25:06.598977 [Byte1]: 34
949 00:25:06.603518
950 00:25:06.604026 Set Vref, RX VrefLevel [Byte0]: 35
951 00:25:06.606614 [Byte1]: 35
952 00:25:06.610790
953 00:25:06.611265 Set Vref, RX VrefLevel [Byte0]: 36
954 00:25:06.614309 [Byte1]: 36
955 00:25:06.618508
956 00:25:06.618933 Set Vref, RX VrefLevel [Byte0]: 37
957 00:25:06.622183 [Byte1]: 37
958 00:25:06.626502
959 00:25:06.627016 Set Vref, RX VrefLevel [Byte0]: 38
960 00:25:06.629430 [Byte1]: 38
961 00:25:06.633569
962 00:25:06.634001 Set Vref, RX VrefLevel [Byte0]: 39
963 00:25:06.637445 [Byte1]: 39
964 00:25:06.641848
965 00:25:06.642319 Set Vref, RX VrefLevel [Byte0]: 40
966 00:25:06.645203 [Byte1]: 40
967 00:25:06.649335
968 00:25:06.649852 Set Vref, RX VrefLevel [Byte0]: 41
969 00:25:06.652781 [Byte1]: 41
970 00:25:06.656908
971 00:25:06.657339 Set Vref, RX VrefLevel [Byte0]: 42
972 00:25:06.660539 [Byte1]: 42
973 00:25:06.664902
974 00:25:06.665418 Set Vref, RX VrefLevel [Byte0]: 43
975 00:25:06.668070 [Byte1]: 43
976 00:25:06.672451
977 00:25:06.672975 Set Vref, RX VrefLevel [Byte0]: 44
978 00:25:06.675403 [Byte1]: 44
979 00:25:06.679552
980 00:25:06.679980 Set Vref, RX VrefLevel [Byte0]: 45
981 00:25:06.683023 [Byte1]: 45
982 00:25:06.687190
983 00:25:06.687618 Set Vref, RX VrefLevel [Byte0]: 46
984 00:25:06.690600 [Byte1]: 46
985 00:25:06.695461
986 00:25:06.695887 Set Vref, RX VrefLevel [Byte0]: 47
987 00:25:06.698301 [Byte1]: 47
988 00:25:06.702924
989 00:25:06.703350 Set Vref, RX VrefLevel [Byte0]: 48
990 00:25:06.706277 [Byte1]: 48
991 00:25:06.710840
992 00:25:06.711350 Set Vref, RX VrefLevel [Byte0]: 49
993 00:25:06.713692 [Byte1]: 49
994 00:25:06.718035
995 00:25:06.718513 Set Vref, RX VrefLevel [Byte0]: 50
996 00:25:06.721039 [Byte1]: 50
997 00:25:06.725617
998 00:25:06.726044 Set Vref, RX VrefLevel [Byte0]: 51
999 00:25:06.728781 [Byte1]: 51
1000 00:25:06.733206
1001 00:25:06.733641 Set Vref, RX VrefLevel [Byte0]: 52
1002 00:25:06.736483 [Byte1]: 52
1003 00:25:06.741144
1004 00:25:06.741575 Set Vref, RX VrefLevel [Byte0]: 53
1005 00:25:06.743895 [Byte1]: 53
1006 00:25:06.748209
1007 00:25:06.748652 Set Vref, RX VrefLevel [Byte0]: 54
1008 00:25:06.751694 [Byte1]: 54
1009 00:25:06.756860
1010 00:25:06.757292 Set Vref, RX VrefLevel [Byte0]: 55
1011 00:25:06.759685 [Byte1]: 55
1012 00:25:06.764500
1013 00:25:06.765020 Set Vref, RX VrefLevel [Byte0]: 56
1014 00:25:06.767421 [Byte1]: 56
1015 00:25:06.771588
1016 00:25:06.772021 Set Vref, RX VrefLevel [Byte0]: 57
1017 00:25:06.774836 [Byte1]: 57
1018 00:25:06.779604
1019 00:25:06.780116 Set Vref, RX VrefLevel [Byte0]: 58
1020 00:25:06.782431 [Byte1]: 58
1021 00:25:06.786741
1022 00:25:06.787178 Set Vref, RX VrefLevel [Byte0]: 59
1023 00:25:06.793266 [Byte1]: 59
1024 00:25:06.793814
1025 00:25:06.796495 Set Vref, RX VrefLevel [Byte0]: 60
1026 00:25:06.800142 [Byte1]: 60
1027 00:25:06.800669
1028 00:25:06.803514 Set Vref, RX VrefLevel [Byte0]: 61
1029 00:25:06.806589 [Byte1]: 61
1030 00:25:06.807018
1031 00:25:06.810146 Set Vref, RX VrefLevel [Byte0]: 62
1032 00:25:06.813446 [Byte1]: 62
1033 00:25:06.817396
1034 00:25:06.817913 Set Vref, RX VrefLevel [Byte0]: 63
1035 00:25:06.820796 [Byte1]: 63
1036 00:25:06.825188
1037 00:25:06.825752 Set Vref, RX VrefLevel [Byte0]: 64
1038 00:25:06.828456 [Byte1]: 64
1039 00:25:06.832889
1040 00:25:06.833405 Set Vref, RX VrefLevel [Byte0]: 65
1041 00:25:06.835570 [Byte1]: 65
1042 00:25:06.840469
1043 00:25:06.840981 Set Vref, RX VrefLevel [Byte0]: 66
1044 00:25:06.844103 [Byte1]: 66
1045 00:25:06.847995
1046 00:25:06.848505 Set Vref, RX VrefLevel [Byte0]: 67
1047 00:25:06.851195 [Byte1]: 67
1048 00:25:06.855953
1049 00:25:06.856383 Set Vref, RX VrefLevel [Byte0]: 68
1050 00:25:06.859358 [Byte1]: 68
1051 00:25:06.863421
1052 00:25:06.863933 Set Vref, RX VrefLevel [Byte0]: 69
1053 00:25:06.866649 [Byte1]: 69
1054 00:25:06.871042
1055 00:25:06.871559 Set Vref, RX VrefLevel [Byte0]: 70
1056 00:25:06.874423 [Byte1]: 70
1057 00:25:06.878907
1058 00:25:06.879424 Set Vref, RX VrefLevel [Byte0]: 71
1059 00:25:06.881721 [Byte1]: 71
1060 00:25:06.886094
1061 00:25:06.886645 Set Vref, RX VrefLevel [Byte0]: 72
1062 00:25:06.889711 [Byte1]: 72
1063 00:25:06.893965
1064 00:25:06.894526 Final RX Vref Byte 0 = 51 to rank0
1065 00:25:06.897258 Final RX Vref Byte 1 = 55 to rank0
1066 00:25:06.900904 Final RX Vref Byte 0 = 51 to rank1
1067 00:25:06.903636 Final RX Vref Byte 1 = 55 to rank1==
1068 00:25:06.907095 Dram Type= 6, Freq= 0, CH_0, rank 0
1069 00:25:06.914102 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1070 00:25:06.914668 ==
1071 00:25:06.915010 DQS Delay:
1072 00:25:06.915315 DQS0 = 0, DQS1 = 0
1073 00:25:06.917257 DQM Delay:
1074 00:25:06.917767 DQM0 = 83, DQM1 = 72
1075 00:25:06.920453 DQ Delay:
1076 00:25:06.923737 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1077 00:25:06.924221 DQ4 =88, DQ5 =72, DQ6 =92, DQ7 =92
1078 00:25:06.927290 DQ8 =60, DQ9 =56, DQ10 =76, DQ11 =64
1079 00:25:06.930304 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =84
1080 00:25:06.934154
1081 00:25:06.934702
1082 00:25:06.940380 [DQSOSCAuto] RK0, (LSB)MR18= 0x3c3c, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
1083 00:25:06.943840 CH0 RK0: MR19=606, MR18=3C3C
1084 00:25:06.950313 CH0_RK0: MR19=0x606, MR18=0x3C3C, DQSOSC=394, MR23=63, INC=95, DEC=63
1085 00:25:06.950817
1086 00:25:06.953622 ----->DramcWriteLeveling(PI) begin...
1087 00:25:06.954060 ==
1088 00:25:06.956990 Dram Type= 6, Freq= 0, CH_0, rank 1
1089 00:25:06.960251 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1090 00:25:06.960699 ==
1091 00:25:06.963860 Write leveling (Byte 0): 31 => 31
1092 00:25:06.967410 Write leveling (Byte 1): 27 => 27
1093 00:25:06.970409 DramcWriteLeveling(PI) end<-----
1094 00:25:06.970832
1095 00:25:06.971154 ==
1096 00:25:06.973678 Dram Type= 6, Freq= 0, CH_0, rank 1
1097 00:25:06.977166 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1098 00:25:06.977678 ==
1099 00:25:06.980759 [Gating] SW mode calibration
1100 00:25:06.987637 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1101 00:25:06.993753 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1102 00:25:06.997002 0 6 0 | B1->B0 | 3131 3232 | 0 0 | (0 0) (0 0)
1103 00:25:07.000838 0 6 4 | B1->B0 | 2424 2424 | 0 0 | (1 0) (0 0)
1104 00:25:07.006822 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1105 00:25:07.010619 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1106 00:25:07.013944 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1107 00:25:07.020759 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1108 00:25:07.023315 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1109 00:25:07.026656 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1110 00:25:07.033270 0 7 0 | B1->B0 | 2b2b 2f2f | 1 0 | (0 0) (0 0)
1111 00:25:07.037770 0 7 4 | B1->B0 | 4242 4646 | 1 0 | (0 0) (0 0)
1112 00:25:07.040019 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1113 00:25:07.047217 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1114 00:25:07.049952 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1115 00:25:07.053910 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1116 00:25:07.056881 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1117 00:25:07.063800 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1118 00:25:07.066991 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1119 00:25:07.070558 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1120 00:25:07.077156 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1121 00:25:07.080812 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1122 00:25:07.084088 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1123 00:25:07.090557 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1124 00:25:07.093843 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1125 00:25:07.096945 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1126 00:25:07.103769 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1127 00:25:07.106959 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1128 00:25:07.110549 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1129 00:25:07.117215 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1130 00:25:07.120444 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1131 00:25:07.123833 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1132 00:25:07.130084 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1133 00:25:07.133300 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1134 00:25:07.137259 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1135 00:25:07.144181 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1136 00:25:07.144700 Total UI for P1: 0, mck2ui 16
1137 00:25:07.150388 best dqsien dly found for B0: ( 0, 10, 0)
1138 00:25:07.150913 Total UI for P1: 0, mck2ui 16
1139 00:25:07.153794 best dqsien dly found for B1: ( 0, 10, 0)
1140 00:25:07.156770 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
1141 00:25:07.163802 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1142 00:25:07.164320
1143 00:25:07.166874 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
1144 00:25:07.170696 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1145 00:25:07.173579 [Gating] SW calibration Done
1146 00:25:07.174025 ==
1147 00:25:07.177044 Dram Type= 6, Freq= 0, CH_0, rank 1
1148 00:25:07.180511 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1149 00:25:07.181031 ==
1150 00:25:07.181467 RX Vref Scan: 0
1151 00:25:07.183530
1152 00:25:07.183973 RX Vref 0 -> 0, step: 1
1153 00:25:07.184405
1154 00:25:07.186903 RX Delay -130 -> 252, step: 16
1155 00:25:07.190329 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1156 00:25:07.193564 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1157 00:25:07.240985 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1158 00:25:07.241505 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1159 00:25:07.242322 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1160 00:25:07.242710 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1161 00:25:07.243151 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1162 00:25:07.243641 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1163 00:25:07.244026 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1164 00:25:07.244416 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1165 00:25:07.244815 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1166 00:25:07.245198 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1167 00:25:07.245652 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1168 00:25:07.268790 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1169 00:25:07.269336 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1170 00:25:07.269782 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1171 00:25:07.270314 ==
1172 00:25:07.271057 Dram Type= 6, Freq= 0, CH_0, rank 1
1173 00:25:07.271419 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1174 00:25:07.271816 ==
1175 00:25:07.272203 DQS Delay:
1176 00:25:07.272585 DQS0 = 0, DQS1 = 0
1177 00:25:07.272965 DQM Delay:
1178 00:25:07.273340 DQM0 = 82, DQM1 = 73
1179 00:25:07.273715 DQ Delay:
1180 00:25:07.274203 DQ0 =77, DQ1 =85, DQ2 =85, DQ3 =77
1181 00:25:07.274800 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =93
1182 00:25:07.276036 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
1183 00:25:07.279083 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1184 00:25:07.279527
1185 00:25:07.279961
1186 00:25:07.280367 ==
1187 00:25:07.282316 Dram Type= 6, Freq= 0, CH_0, rank 1
1188 00:25:07.286347 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1189 00:25:07.286752 ==
1190 00:25:07.287164
1191 00:25:07.289155
1192 00:25:07.289616 TX Vref Scan disable
1193 00:25:07.292827 == TX Byte 0 ==
1194 00:25:07.295756 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1195 00:25:07.299116 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1196 00:25:07.302715 == TX Byte 1 ==
1197 00:25:07.305848 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1198 00:25:07.309083 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1199 00:25:07.309608 ==
1200 00:25:07.312715 Dram Type= 6, Freq= 0, CH_0, rank 1
1201 00:25:07.318904 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1202 00:25:07.319416 ==
1203 00:25:07.331241 TX Vref=22, minBit 8, minWin=27, winSum=447
1204 00:25:07.334875 TX Vref=24, minBit 14, minWin=27, winSum=450
1205 00:25:07.337891 TX Vref=26, minBit 14, minWin=27, winSum=451
1206 00:25:07.341163 TX Vref=28, minBit 4, minWin=28, winSum=457
1207 00:25:07.344928 TX Vref=30, minBit 2, minWin=28, winSum=456
1208 00:25:07.351479 TX Vref=32, minBit 2, minWin=28, winSum=456
1209 00:25:07.354411 [TxChooseVref] Worse bit 4, Min win 28, Win sum 457, Final Vref 28
1210 00:25:07.355047
1211 00:25:07.357752 Final TX Range 1 Vref 28
1212 00:25:07.358181
1213 00:25:07.358618 ==
1214 00:25:07.361246 Dram Type= 6, Freq= 0, CH_0, rank 1
1215 00:25:07.364977 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1216 00:25:07.365487 ==
1217 00:25:07.367842
1218 00:25:07.368349
1219 00:25:07.368684 TX Vref Scan disable
1220 00:25:07.371874 == TX Byte 0 ==
1221 00:25:07.374395 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1222 00:25:07.381280 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1223 00:25:07.381792 == TX Byte 1 ==
1224 00:25:07.385172 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1225 00:25:07.391786 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1226 00:25:07.392299
1227 00:25:07.392629 [DATLAT]
1228 00:25:07.392935 Freq=800, CH0 RK1
1229 00:25:07.393232
1230 00:25:07.394612 DATLAT Default: 0x9
1231 00:25:07.395041 0, 0xFFFF, sum = 0
1232 00:25:07.397687 1, 0xFFFF, sum = 0
1233 00:25:07.398123 2, 0xFFFF, sum = 0
1234 00:25:07.401488 3, 0xFFFF, sum = 0
1235 00:25:07.402005 4, 0xFFFF, sum = 0
1236 00:25:07.404701 5, 0xFFFF, sum = 0
1237 00:25:07.408321 6, 0xFFFF, sum = 0
1238 00:25:07.408843 7, 0xFFFF, sum = 0
1239 00:25:07.409185 8, 0x0, sum = 1
1240 00:25:07.411417 9, 0x0, sum = 2
1241 00:25:07.411852 10, 0x0, sum = 3
1242 00:25:07.414750 11, 0x0, sum = 4
1243 00:25:07.415186 best_step = 9
1244 00:25:07.415516
1245 00:25:07.415819 ==
1246 00:25:07.418009 Dram Type= 6, Freq= 0, CH_0, rank 1
1247 00:25:07.425160 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1248 00:25:07.425680 ==
1249 00:25:07.426017 RX Vref Scan: 0
1250 00:25:07.426363
1251 00:25:07.427838 RX Vref 0 -> 0, step: 1
1252 00:25:07.428267
1253 00:25:07.431453 RX Delay -111 -> 252, step: 8
1254 00:25:07.434675 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
1255 00:25:07.437798 iDelay=209, Bit 1, Center 88 (-31 ~ 208) 240
1256 00:25:07.444534 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1257 00:25:07.448102 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1258 00:25:07.451330 iDelay=209, Bit 4, Center 88 (-31 ~ 208) 240
1259 00:25:07.454419 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1260 00:25:07.457862 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1261 00:25:07.461549 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1262 00:25:07.468248 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1263 00:25:07.471098 iDelay=209, Bit 9, Center 56 (-55 ~ 168) 224
1264 00:25:07.474902 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1265 00:25:07.478028 iDelay=209, Bit 11, Center 64 (-47 ~ 176) 224
1266 00:25:07.481453 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1267 00:25:07.488292 iDelay=209, Bit 13, Center 76 (-39 ~ 192) 232
1268 00:25:07.491474 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
1269 00:25:07.495493 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1270 00:25:07.496001 ==
1271 00:25:07.497723 Dram Type= 6, Freq= 0, CH_0, rank 1
1272 00:25:07.501322 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1273 00:25:07.504970 ==
1274 00:25:07.505475 DQS Delay:
1275 00:25:07.505816 DQS0 = 0, DQS1 = 0
1276 00:25:07.508119 DQM Delay:
1277 00:25:07.508626 DQM0 = 85, DQM1 = 72
1278 00:25:07.511954 DQ Delay:
1279 00:25:07.512465 DQ0 =80, DQ1 =88, DQ2 =84, DQ3 =84
1280 00:25:07.514763 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =92
1281 00:25:07.518190 DQ8 =64, DQ9 =56, DQ10 =72, DQ11 =64
1282 00:25:07.521569 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =84
1283 00:25:07.522080
1284 00:25:07.524843
1285 00:25:07.531518 [DQSOSCAuto] RK1, (LSB)MR18= 0x4747, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
1286 00:25:07.534712 CH0 RK1: MR19=606, MR18=4747
1287 00:25:07.541196 CH0_RK1: MR19=0x606, MR18=0x4747, DQSOSC=392, MR23=63, INC=96, DEC=64
1288 00:25:07.541710 [RxdqsGatingPostProcess] freq 800
1289 00:25:07.548130 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1290 00:25:07.551452 Pre-setting of DQS Precalculation
1291 00:25:07.554635 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1292 00:25:07.555075 ==
1293 00:25:07.557815 Dram Type= 6, Freq= 0, CH_1, rank 0
1294 00:25:07.564567 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1295 00:25:07.565007 ==
1296 00:25:07.567868 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1297 00:25:07.574340 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1298 00:25:07.584092 [CA 0] Center 37 (6~68) winsize 63
1299 00:25:07.587437 [CA 1] Center 37 (6~68) winsize 63
1300 00:25:07.590886 [CA 2] Center 34 (4~65) winsize 62
1301 00:25:07.594133 [CA 3] Center 34 (4~65) winsize 62
1302 00:25:07.597350 [CA 4] Center 33 (3~64) winsize 62
1303 00:25:07.600685 [CA 5] Center 33 (3~64) winsize 62
1304 00:25:07.601107
1305 00:25:07.604512 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1306 00:25:07.604936
1307 00:25:07.607323 [CATrainingPosCal] consider 1 rank data
1308 00:25:07.610717 u2DelayCellTimex100 = 270/100 ps
1309 00:25:07.614065 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1310 00:25:07.617545 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1311 00:25:07.623867 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1312 00:25:07.627399 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1313 00:25:07.630752 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1314 00:25:07.634084 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1315 00:25:07.634438
1316 00:25:07.637174 CA PerBit enable=1, Macro0, CA PI delay=33
1317 00:25:07.637398
1318 00:25:07.640673 [CBTSetCACLKResult] CA Dly = 33
1319 00:25:07.640922 CS Dly: 5 (0~36)
1320 00:25:07.641095 ==
1321 00:25:07.643582 Dram Type= 6, Freq= 0, CH_1, rank 1
1322 00:25:07.650265 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1323 00:25:07.650553 ==
1324 00:25:07.653906 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1325 00:25:07.660195 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1326 00:25:07.670052 [CA 0] Center 37 (6~68) winsize 63
1327 00:25:07.672877 [CA 1] Center 36 (5~68) winsize 64
1328 00:25:07.676265 [CA 2] Center 34 (4~65) winsize 62
1329 00:25:07.680195 [CA 3] Center 34 (4~65) winsize 62
1330 00:25:07.682852 [CA 4] Center 33 (3~64) winsize 62
1331 00:25:07.686120 [CA 5] Center 33 (2~64) winsize 63
1332 00:25:07.686591
1333 00:25:07.689472 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1334 00:25:07.689900
1335 00:25:07.693385 [CATrainingPosCal] consider 2 rank data
1336 00:25:07.697024 u2DelayCellTimex100 = 270/100 ps
1337 00:25:07.699526 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1338 00:25:07.703261 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1339 00:25:07.709917 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1340 00:25:07.713235 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1341 00:25:07.716593 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1342 00:25:07.719944 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1343 00:25:07.720379
1344 00:25:07.723057 CA PerBit enable=1, Macro0, CA PI delay=33
1345 00:25:07.723489
1346 00:25:07.726648 [CBTSetCACLKResult] CA Dly = 33
1347 00:25:07.727078 CS Dly: 5 (0~36)
1348 00:25:07.727409
1349 00:25:07.729972 ----->DramcWriteLeveling(PI) begin...
1350 00:25:07.733204 ==
1351 00:25:07.736591 Dram Type= 6, Freq= 0, CH_1, rank 0
1352 00:25:07.739510 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1353 00:25:07.739943 ==
1354 00:25:07.743167 Write leveling (Byte 0): 27 => 27
1355 00:25:07.746278 Write leveling (Byte 1): 22 => 22
1356 00:25:07.750327 DramcWriteLeveling(PI) end<-----
1357 00:25:07.750794
1358 00:25:07.751234 ==
1359 00:25:07.753109 Dram Type= 6, Freq= 0, CH_1, rank 0
1360 00:25:07.756270 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1361 00:25:07.756918 ==
1362 00:25:07.759622 [Gating] SW mode calibration
1363 00:25:07.766311 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1364 00:25:07.769537 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1365 00:25:07.776599 0 6 0 | B1->B0 | 2f2f 2424 | 1 0 | (1 0) (1 0)
1366 00:25:07.779842 0 6 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1367 00:25:07.783271 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1368 00:25:07.790122 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1369 00:25:07.793177 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1370 00:25:07.796651 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1371 00:25:07.803098 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1372 00:25:07.806671 0 6 28 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
1373 00:25:07.810003 0 7 0 | B1->B0 | 2e2e 3f3f | 0 0 | (0 0) (0 0)
1374 00:25:07.816815 0 7 4 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
1375 00:25:07.820129 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1376 00:25:07.823169 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1377 00:25:07.830040 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1378 00:25:07.833375 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1379 00:25:07.836958 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1380 00:25:07.839791 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1381 00:25:07.846436 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1382 00:25:07.849780 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1383 00:25:07.853766 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1384 00:25:07.859696 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1385 00:25:07.863665 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1386 00:25:07.866400 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1387 00:25:07.873858 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1388 00:25:07.877096 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1389 00:25:07.879738 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1390 00:25:07.886791 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1391 00:25:07.890135 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1392 00:25:07.893460 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1393 00:25:07.900059 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1394 00:25:07.903126 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1395 00:25:07.906650 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1396 00:25:07.913197 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1397 00:25:07.916610 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1398 00:25:07.920096 Total UI for P1: 0, mck2ui 16
1399 00:25:07.923159 best dqsien dly found for B0: ( 0, 9, 30)
1400 00:25:07.926293 Total UI for P1: 0, mck2ui 16
1401 00:25:07.930164 best dqsien dly found for B1: ( 0, 9, 30)
1402 00:25:07.933528 best DQS0 dly(MCK, UI, PI) = (0, 9, 30)
1403 00:25:07.936165 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1404 00:25:07.936595
1405 00:25:07.939973 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 30)
1406 00:25:07.943150 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1407 00:25:07.946552 [Gating] SW calibration Done
1408 00:25:07.947059 ==
1409 00:25:07.949715 Dram Type= 6, Freq= 0, CH_1, rank 0
1410 00:25:07.953210 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1411 00:25:07.956620 ==
1412 00:25:07.957012 RX Vref Scan: 0
1413 00:25:07.957334
1414 00:25:07.959916 RX Vref 0 -> 0, step: 1
1415 00:25:07.960366
1416 00:25:07.963298 RX Delay -130 -> 252, step: 16
1417 00:25:07.966978 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1418 00:25:07.969858 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1419 00:25:07.973243 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1420 00:25:07.976559 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1421 00:25:07.979599 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1422 00:25:07.986295 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1423 00:25:07.989987 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1424 00:25:07.993298 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1425 00:25:07.996498 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1426 00:25:07.999798 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1427 00:25:08.006328 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1428 00:25:08.009684 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1429 00:25:08.013738 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1430 00:25:08.016938 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1431 00:25:08.020154 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1432 00:25:08.026693 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1433 00:25:08.027114 ==
1434 00:25:08.029687 Dram Type= 6, Freq= 0, CH_1, rank 0
1435 00:25:08.033154 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1436 00:25:08.033665 ==
1437 00:25:08.033995 DQS Delay:
1438 00:25:08.036734 DQS0 = 0, DQS1 = 0
1439 00:25:08.037163 DQM Delay:
1440 00:25:08.040003 DQM0 = 81, DQM1 = 72
1441 00:25:08.040432 DQ Delay:
1442 00:25:08.042861 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1443 00:25:08.047024 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1444 00:25:08.049790 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =69
1445 00:25:08.053290 DQ12 =77, DQ13 =85, DQ14 =77, DQ15 =77
1446 00:25:08.053793
1447 00:25:08.054143
1448 00:25:08.054511 ==
1449 00:25:08.057211 Dram Type= 6, Freq= 0, CH_1, rank 0
1450 00:25:08.059786 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1451 00:25:08.060223 ==
1452 00:25:08.064002
1453 00:25:08.064505
1454 00:25:08.064840 TX Vref Scan disable
1455 00:25:08.066944 == TX Byte 0 ==
1456 00:25:08.069715 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1457 00:25:08.073367 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1458 00:25:08.077014 == TX Byte 1 ==
1459 00:25:08.080139 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
1460 00:25:08.083558 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
1461 00:25:08.083991 ==
1462 00:25:08.086636 Dram Type= 6, Freq= 0, CH_1, rank 0
1463 00:25:08.093442 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1464 00:25:08.093952 ==
1465 00:25:08.105499 TX Vref=22, minBit 0, minWin=27, winSum=448
1466 00:25:08.109143 TX Vref=24, minBit 9, minWin=27, winSum=450
1467 00:25:08.111986 TX Vref=26, minBit 3, minWin=27, winSum=454
1468 00:25:08.115628 TX Vref=28, minBit 3, minWin=28, winSum=458
1469 00:25:08.119174 TX Vref=30, minBit 0, minWin=28, winSum=457
1470 00:25:08.122500 TX Vref=32, minBit 0, minWin=28, winSum=460
1471 00:25:08.128620 [TxChooseVref] Worse bit 0, Min win 28, Win sum 460, Final Vref 32
1472 00:25:08.129124
1473 00:25:08.132047 Final TX Range 1 Vref 32
1474 00:25:08.132481
1475 00:25:08.132811 ==
1476 00:25:08.135303 Dram Type= 6, Freq= 0, CH_1, rank 0
1477 00:25:08.138711 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1478 00:25:08.139147 ==
1479 00:25:08.139478
1480 00:25:08.142298
1481 00:25:08.142806 TX Vref Scan disable
1482 00:25:08.145720 == TX Byte 0 ==
1483 00:25:08.149164 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1484 00:25:08.152076 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1485 00:25:08.155363 == TX Byte 1 ==
1486 00:25:08.158996 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
1487 00:25:08.162315 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
1488 00:25:08.162754
1489 00:25:08.165460 [DATLAT]
1490 00:25:08.165896 Freq=800, CH1 RK0
1491 00:25:08.166425
1492 00:25:08.168938 DATLAT Default: 0xa
1493 00:25:08.169458 0, 0xFFFF, sum = 0
1494 00:25:08.172199 1, 0xFFFF, sum = 0
1495 00:25:08.172641 2, 0xFFFF, sum = 0
1496 00:25:08.175850 3, 0xFFFF, sum = 0
1497 00:25:08.176378 4, 0xFFFF, sum = 0
1498 00:25:08.178928 5, 0xFFFF, sum = 0
1499 00:25:08.179423 6, 0xFFFF, sum = 0
1500 00:25:08.182258 7, 0xFFFF, sum = 0
1501 00:25:08.182789 8, 0x0, sum = 1
1502 00:25:08.185755 9, 0x0, sum = 2
1503 00:25:08.186197 10, 0x0, sum = 3
1504 00:25:08.189595 11, 0x0, sum = 4
1505 00:25:08.190122 best_step = 9
1506 00:25:08.190598
1507 00:25:08.190997 ==
1508 00:25:08.192143 Dram Type= 6, Freq= 0, CH_1, rank 0
1509 00:25:08.198846 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1510 00:25:08.199372 ==
1511 00:25:08.199806 RX Vref Scan: 1
1512 00:25:08.200210
1513 00:25:08.202169 Set Vref Range= 32 -> 127
1514 00:25:08.202636
1515 00:25:08.205962 RX Vref 32 -> 127, step: 1
1516 00:25:08.206444
1517 00:25:08.206783 RX Delay -111 -> 252, step: 8
1518 00:25:08.209056
1519 00:25:08.209558 Set Vref, RX VrefLevel [Byte0]: 32
1520 00:25:08.212375 [Byte1]: 32
1521 00:25:08.216871
1522 00:25:08.217375 Set Vref, RX VrefLevel [Byte0]: 33
1523 00:25:08.219942 [Byte1]: 33
1524 00:25:08.224121
1525 00:25:08.224772 Set Vref, RX VrefLevel [Byte0]: 34
1526 00:25:08.227140 [Byte1]: 34
1527 00:25:08.231856
1528 00:25:08.232364 Set Vref, RX VrefLevel [Byte0]: 35
1529 00:25:08.235358 [Byte1]: 35
1530 00:25:08.239346
1531 00:25:08.239771 Set Vref, RX VrefLevel [Byte0]: 36
1532 00:25:08.242686 [Byte1]: 36
1533 00:25:08.247149
1534 00:25:08.247650 Set Vref, RX VrefLevel [Byte0]: 37
1535 00:25:08.250358 [Byte1]: 37
1536 00:25:08.254758
1537 00:25:08.255278 Set Vref, RX VrefLevel [Byte0]: 38
1538 00:25:08.257934 [Byte1]: 38
1539 00:25:08.262267
1540 00:25:08.262698 Set Vref, RX VrefLevel [Byte0]: 39
1541 00:25:08.265516 [Byte1]: 39
1542 00:25:08.270330
1543 00:25:08.270754 Set Vref, RX VrefLevel [Byte0]: 40
1544 00:25:08.273338 [Byte1]: 40
1545 00:25:08.278063
1546 00:25:08.278628 Set Vref, RX VrefLevel [Byte0]: 41
1547 00:25:08.281113 [Byte1]: 41
1548 00:25:08.285233
1549 00:25:08.285759 Set Vref, RX VrefLevel [Byte0]: 42
1550 00:25:08.289101 [Byte1]: 42
1551 00:25:08.293163
1552 00:25:08.293668 Set Vref, RX VrefLevel [Byte0]: 43
1553 00:25:08.296849 [Byte1]: 43
1554 00:25:08.300924
1555 00:25:08.301432 Set Vref, RX VrefLevel [Byte0]: 44
1556 00:25:08.304735 [Byte1]: 44
1557 00:25:08.308237
1558 00:25:08.308758 Set Vref, RX VrefLevel [Byte0]: 45
1559 00:25:08.311307 [Byte1]: 45
1560 00:25:08.315864
1561 00:25:08.316507 Set Vref, RX VrefLevel [Byte0]: 46
1562 00:25:08.319050 [Byte1]: 46
1563 00:25:08.323870
1564 00:25:08.324396 Set Vref, RX VrefLevel [Byte0]: 47
1565 00:25:08.327501 [Byte1]: 47
1566 00:25:08.331163
1567 00:25:08.331664 Set Vref, RX VrefLevel [Byte0]: 48
1568 00:25:08.334586 [Byte1]: 48
1569 00:25:08.339223
1570 00:25:08.339645 Set Vref, RX VrefLevel [Byte0]: 49
1571 00:25:08.342298 [Byte1]: 49
1572 00:25:08.346748
1573 00:25:08.347270 Set Vref, RX VrefLevel [Byte0]: 50
1574 00:25:08.350121 [Byte1]: 50
1575 00:25:08.354047
1576 00:25:08.354599 Set Vref, RX VrefLevel [Byte0]: 51
1577 00:25:08.357801 [Byte1]: 51
1578 00:25:08.361658
1579 00:25:08.362077 Set Vref, RX VrefLevel [Byte0]: 52
1580 00:25:08.365083 [Byte1]: 52
1581 00:25:08.369411
1582 00:25:08.369909 Set Vref, RX VrefLevel [Byte0]: 53
1583 00:25:08.373222 [Byte1]: 53
1584 00:25:08.377128
1585 00:25:08.377645 Set Vref, RX VrefLevel [Byte0]: 54
1586 00:25:08.380556 [Byte1]: 54
1587 00:25:08.384747
1588 00:25:08.385253 Set Vref, RX VrefLevel [Byte0]: 55
1589 00:25:08.387825 [Byte1]: 55
1590 00:25:08.392557
1591 00:25:08.393060 Set Vref, RX VrefLevel [Byte0]: 56
1592 00:25:08.395869 [Byte1]: 56
1593 00:25:08.399909
1594 00:25:08.400331 Set Vref, RX VrefLevel [Byte0]: 57
1595 00:25:08.403502 [Byte1]: 57
1596 00:25:08.407677
1597 00:25:08.408179 Set Vref, RX VrefLevel [Byte0]: 58
1598 00:25:08.411225 [Byte1]: 58
1599 00:25:08.415372
1600 00:25:08.415874 Set Vref, RX VrefLevel [Byte0]: 59
1601 00:25:08.418371 [Byte1]: 59
1602 00:25:08.423416
1603 00:25:08.423918 Set Vref, RX VrefLevel [Byte0]: 60
1604 00:25:08.426667 [Byte1]: 60
1605 00:25:08.430610
1606 00:25:08.431117 Set Vref, RX VrefLevel [Byte0]: 61
1607 00:25:08.433799 [Byte1]: 61
1608 00:25:08.437958
1609 00:25:08.438433 Set Vref, RX VrefLevel [Byte0]: 62
1610 00:25:08.441592 [Byte1]: 62
1611 00:25:08.445838
1612 00:25:08.446393 Set Vref, RX VrefLevel [Byte0]: 63
1613 00:25:08.449162 [Byte1]: 63
1614 00:25:08.453765
1615 00:25:08.454484 Set Vref, RX VrefLevel [Byte0]: 64
1616 00:25:08.456871 [Byte1]: 64
1617 00:25:08.461164
1618 00:25:08.461591 Set Vref, RX VrefLevel [Byte0]: 65
1619 00:25:08.464778 [Byte1]: 65
1620 00:25:08.468983
1621 00:25:08.469492 Set Vref, RX VrefLevel [Byte0]: 66
1622 00:25:08.472124 [Byte1]: 66
1623 00:25:08.476285
1624 00:25:08.476711 Set Vref, RX VrefLevel [Byte0]: 67
1625 00:25:08.479741 [Byte1]: 67
1626 00:25:08.484275
1627 00:25:08.484716 Set Vref, RX VrefLevel [Byte0]: 68
1628 00:25:08.487778 [Byte1]: 68
1629 00:25:08.491635
1630 00:25:08.492084 Set Vref, RX VrefLevel [Byte0]: 69
1631 00:25:08.494740 [Byte1]: 69
1632 00:25:08.499455
1633 00:25:08.499896 Set Vref, RX VrefLevel [Byte0]: 70
1634 00:25:08.502941 [Byte1]: 70
1635 00:25:08.506845
1636 00:25:08.507267 Set Vref, RX VrefLevel [Byte0]: 71
1637 00:25:08.510287 [Byte1]: 71
1638 00:25:08.515036
1639 00:25:08.515537 Set Vref, RX VrefLevel [Byte0]: 72
1640 00:25:08.517674 [Byte1]: 72
1641 00:25:08.522390
1642 00:25:08.522893 Set Vref, RX VrefLevel [Byte0]: 73
1643 00:25:08.525643 [Byte1]: 73
1644 00:25:08.530076
1645 00:25:08.530641 Set Vref, RX VrefLevel [Byte0]: 74
1646 00:25:08.533377 [Byte1]: 74
1647 00:25:08.537817
1648 00:25:08.538449 Set Vref, RX VrefLevel [Byte0]: 75
1649 00:25:08.540981 [Byte1]: 75
1650 00:25:08.545252
1651 00:25:08.545688 Set Vref, RX VrefLevel [Byte0]: 76
1652 00:25:08.548384 [Byte1]: 76
1653 00:25:08.552815
1654 00:25:08.553247 Set Vref, RX VrefLevel [Byte0]: 77
1655 00:25:08.556010 [Byte1]: 77
1656 00:25:08.560814
1657 00:25:08.561492 Set Vref, RX VrefLevel [Byte0]: 78
1658 00:25:08.563832 [Byte1]: 78
1659 00:25:08.568365
1660 00:25:08.568790 Final RX Vref Byte 0 = 58 to rank0
1661 00:25:08.571297 Final RX Vref Byte 1 = 56 to rank0
1662 00:25:08.574793 Final RX Vref Byte 0 = 58 to rank1
1663 00:25:08.578004 Final RX Vref Byte 1 = 56 to rank1==
1664 00:25:08.581703 Dram Type= 6, Freq= 0, CH_1, rank 0
1665 00:25:08.585023 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1666 00:25:08.588558 ==
1667 00:25:08.589066 DQS Delay:
1668 00:25:08.589396 DQS0 = 0, DQS1 = 0
1669 00:25:08.591765 DQM Delay:
1670 00:25:08.592189 DQM0 = 81, DQM1 = 75
1671 00:25:08.594894 DQ Delay:
1672 00:25:08.595316 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =80
1673 00:25:08.598854 DQ4 =80, DQ5 =92, DQ6 =88, DQ7 =76
1674 00:25:08.601909 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =68
1675 00:25:08.605163 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =84
1676 00:25:08.605661
1677 00:25:08.608698
1678 00:25:08.615660 [DQSOSCAuto] RK0, (LSB)MR18= 0x5050, (MSB)MR19= 0x606, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
1679 00:25:08.618277 CH1 RK0: MR19=606, MR18=5050
1680 00:25:08.625472 CH1_RK0: MR19=0x606, MR18=0x5050, DQSOSC=389, MR23=63, INC=97, DEC=65
1681 00:25:08.625999
1682 00:25:08.628590 ----->DramcWriteLeveling(PI) begin...
1683 00:25:08.629099 ==
1684 00:25:08.631895 Dram Type= 6, Freq= 0, CH_1, rank 1
1685 00:25:08.635282 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1686 00:25:08.635786 ==
1687 00:25:08.638360 Write leveling (Byte 0): 24 => 24
1688 00:25:08.641779 Write leveling (Byte 1): 24 => 24
1689 00:25:08.645098 DramcWriteLeveling(PI) end<-----
1690 00:25:08.645603
1691 00:25:08.645948 ==
1692 00:25:08.648616 Dram Type= 6, Freq= 0, CH_1, rank 1
1693 00:25:08.651978 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1694 00:25:08.652489 ==
1695 00:25:08.655095 [Gating] SW mode calibration
1696 00:25:08.662316 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1697 00:25:08.668657 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1698 00:25:08.671392 0 6 0 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
1699 00:25:08.674821 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1700 00:25:08.681523 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1701 00:25:08.684981 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1702 00:25:08.688269 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1703 00:25:08.695050 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1704 00:25:08.698334 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1705 00:25:08.701585 0 6 28 | B1->B0 | 2424 2c2c | 0 1 | (0 0) (0 0)
1706 00:25:08.708532 0 7 0 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
1707 00:25:08.711606 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1708 00:25:08.715145 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1709 00:25:08.721735 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1710 00:25:08.725001 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1711 00:25:08.728495 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1712 00:25:08.731447 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1713 00:25:08.737940 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1714 00:25:08.741720 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1715 00:25:08.744915 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1716 00:25:08.752008 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1717 00:25:08.754346 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1718 00:25:08.758172 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1719 00:25:08.764890 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1720 00:25:08.768268 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1721 00:25:08.770942 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1722 00:25:08.778392 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1723 00:25:08.781135 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1724 00:25:08.784552 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1725 00:25:08.791325 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1726 00:25:08.794158 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1727 00:25:08.797651 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1728 00:25:08.804463 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1729 00:25:08.807822 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1730 00:25:08.811101 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1731 00:25:08.814303 Total UI for P1: 0, mck2ui 16
1732 00:25:08.818078 best dqsien dly found for B0: ( 0, 9, 28)
1733 00:25:08.820852 Total UI for P1: 0, mck2ui 16
1734 00:25:08.824409 best dqsien dly found for B1: ( 0, 9, 28)
1735 00:25:08.827676 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1736 00:25:08.830997 best DQS1 dly(MCK, UI, PI) = (0, 9, 28)
1737 00:25:08.831429
1738 00:25:08.838004 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1739 00:25:08.841163 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 28)
1740 00:25:08.841716 [Gating] SW calibration Done
1741 00:25:08.844360 ==
1742 00:25:08.847696 Dram Type= 6, Freq= 0, CH_1, rank 1
1743 00:25:08.851153 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1744 00:25:08.851587 ==
1745 00:25:08.851924 RX Vref Scan: 0
1746 00:25:08.852253
1747 00:25:08.854509 RX Vref 0 -> 0, step: 1
1748 00:25:08.854933
1749 00:25:08.857667 RX Delay -130 -> 252, step: 16
1750 00:25:08.861086 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1751 00:25:08.864496 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1752 00:25:08.867884 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1753 00:25:08.874817 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1754 00:25:08.878143 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1755 00:25:08.881325 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1756 00:25:08.885049 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1757 00:25:08.887942 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1758 00:25:08.894928 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1759 00:25:08.898174 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1760 00:25:08.901587 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1761 00:25:08.904798 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1762 00:25:08.907802 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1763 00:25:08.915030 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1764 00:25:08.917874 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1765 00:25:08.921546 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1766 00:25:08.922073 ==
1767 00:25:08.925101 Dram Type= 6, Freq= 0, CH_1, rank 1
1768 00:25:08.928308 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1769 00:25:08.928738 ==
1770 00:25:08.931271 DQS Delay:
1771 00:25:08.931696 DQS0 = 0, DQS1 = 0
1772 00:25:08.934571 DQM Delay:
1773 00:25:08.934999 DQM0 = 85, DQM1 = 74
1774 00:25:08.935329 DQ Delay:
1775 00:25:08.938068 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1776 00:25:08.941126 DQ4 =85, DQ5 =101, DQ6 =85, DQ7 =85
1777 00:25:08.944547 DQ8 =53, DQ9 =61, DQ10 =69, DQ11 =69
1778 00:25:08.948067 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1779 00:25:08.948688
1780 00:25:08.949022
1781 00:25:08.951182 ==
1782 00:25:08.954696 Dram Type= 6, Freq= 0, CH_1, rank 1
1783 00:25:08.958376 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1784 00:25:08.958810 ==
1785 00:25:08.959182
1786 00:25:08.959598
1787 00:25:08.961071 TX Vref Scan disable
1788 00:25:08.961495 == TX Byte 0 ==
1789 00:25:08.964336 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1790 00:25:08.972127 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1791 00:25:08.972719 == TX Byte 1 ==
1792 00:25:08.974379 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1793 00:25:08.981188 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1794 00:25:08.981588 ==
1795 00:25:08.984832 Dram Type= 6, Freq= 0, CH_1, rank 1
1796 00:25:08.987668 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1797 00:25:08.988056 ==
1798 00:25:09.000771 TX Vref=22, minBit 8, minWin=27, winSum=450
1799 00:25:09.004174 TX Vref=24, minBit 8, minWin=27, winSum=453
1800 00:25:09.007859 TX Vref=26, minBit 0, minWin=28, winSum=456
1801 00:25:09.011284 TX Vref=28, minBit 5, minWin=28, winSum=460
1802 00:25:09.014121 TX Vref=30, minBit 0, minWin=28, winSum=459
1803 00:25:09.017815 TX Vref=32, minBit 9, minWin=27, winSum=456
1804 00:25:09.024058 [TxChooseVref] Worse bit 5, Min win 28, Win sum 460, Final Vref 28
1805 00:25:09.024541
1806 00:25:09.027672 Final TX Range 1 Vref 28
1807 00:25:09.028104
1808 00:25:09.028525 ==
1809 00:25:09.030931 Dram Type= 6, Freq= 0, CH_1, rank 1
1810 00:25:09.034131 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1811 00:25:09.034676 ==
1812 00:25:09.035107
1813 00:25:09.037636
1814 00:25:09.038158 TX Vref Scan disable
1815 00:25:09.040643 == TX Byte 0 ==
1816 00:25:09.044074 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1817 00:25:09.047163 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1818 00:25:09.050894 == TX Byte 1 ==
1819 00:25:09.054770 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1820 00:25:09.057932 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1821 00:25:09.058500
1822 00:25:09.061229 [DATLAT]
1823 00:25:09.061663 Freq=800, CH1 RK1
1824 00:25:09.061990
1825 00:25:09.063971 DATLAT Default: 0x9
1826 00:25:09.064397 0, 0xFFFF, sum = 0
1827 00:25:09.067807 1, 0xFFFF, sum = 0
1828 00:25:09.068238 2, 0xFFFF, sum = 0
1829 00:25:09.070884 3, 0xFFFF, sum = 0
1830 00:25:09.071313 4, 0xFFFF, sum = 0
1831 00:25:09.074206 5, 0xFFFF, sum = 0
1832 00:25:09.074716 6, 0xFFFF, sum = 0
1833 00:25:09.077885 7, 0xFFFF, sum = 0
1834 00:25:09.078443 8, 0x0, sum = 1
1835 00:25:09.081254 9, 0x0, sum = 2
1836 00:25:09.081682 10, 0x0, sum = 3
1837 00:25:09.084558 11, 0x0, sum = 4
1838 00:25:09.085070 best_step = 9
1839 00:25:09.085396
1840 00:25:09.085696 ==
1841 00:25:09.087781 Dram Type= 6, Freq= 0, CH_1, rank 1
1842 00:25:09.091165 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1843 00:25:09.094473 ==
1844 00:25:09.095009 RX Vref Scan: 0
1845 00:25:09.095340
1846 00:25:09.097429 RX Vref 0 -> 0, step: 1
1847 00:25:09.097861
1848 00:25:09.101105 RX Delay -111 -> 252, step: 8
1849 00:25:09.104734 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1850 00:25:09.107629 iDelay=217, Bit 1, Center 76 (-39 ~ 192) 232
1851 00:25:09.111193 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
1852 00:25:09.117692 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
1853 00:25:09.121092 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
1854 00:25:09.124385 iDelay=217, Bit 5, Center 96 (-23 ~ 216) 240
1855 00:25:09.127146 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1856 00:25:09.131011 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
1857 00:25:09.137490 iDelay=217, Bit 8, Center 60 (-55 ~ 176) 232
1858 00:25:09.140525 iDelay=217, Bit 9, Center 64 (-55 ~ 184) 240
1859 00:25:09.144050 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1860 00:25:09.147737 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
1861 00:25:09.151010 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1862 00:25:09.157561 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1863 00:25:09.160882 iDelay=217, Bit 14, Center 80 (-39 ~ 200) 240
1864 00:25:09.164057 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1865 00:25:09.164695 ==
1866 00:25:09.167772 Dram Type= 6, Freq= 0, CH_1, rank 1
1867 00:25:09.171069 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1868 00:25:09.174531 ==
1869 00:25:09.174955 DQS Delay:
1870 00:25:09.175283 DQS0 = 0, DQS1 = 0
1871 00:25:09.177802 DQM Delay:
1872 00:25:09.178289 DQM0 = 84, DQM1 = 75
1873 00:25:09.180744 DQ Delay:
1874 00:25:09.181166 DQ0 =84, DQ1 =76, DQ2 =76, DQ3 =84
1875 00:25:09.184052 DQ4 =84, DQ5 =96, DQ6 =92, DQ7 =84
1876 00:25:09.187346 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =68
1877 00:25:09.191019 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =84
1878 00:25:09.191525
1879 00:25:09.191854
1880 00:25:09.201027 [DQSOSCAuto] RK1, (LSB)MR18= 0x3838, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
1881 00:25:09.204445 CH1 RK1: MR19=606, MR18=3838
1882 00:25:09.211014 CH1_RK1: MR19=0x606, MR18=0x3838, DQSOSC=395, MR23=63, INC=94, DEC=63
1883 00:25:09.211533 [RxdqsGatingPostProcess] freq 800
1884 00:25:09.217975 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1885 00:25:09.221348 Pre-setting of DQS Precalculation
1886 00:25:09.224403 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1887 00:25:09.234180 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1888 00:25:09.240529 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1889 00:25:09.241032
1890 00:25:09.241368
1891 00:25:09.243802 [Calibration Summary] 1600 Mbps
1892 00:25:09.244419 CH 0, Rank 0
1893 00:25:09.247059 SW Impedance : PASS
1894 00:25:09.247492 DUTY Scan : NO K
1895 00:25:09.250596 ZQ Calibration : PASS
1896 00:25:09.254310 Jitter Meter : NO K
1897 00:25:09.254828 CBT Training : PASS
1898 00:25:09.257204 Write leveling : PASS
1899 00:25:09.261265 RX DQS gating : PASS
1900 00:25:09.261696 RX DQ/DQS(RDDQC) : PASS
1901 00:25:09.263795 TX DQ/DQS : PASS
1902 00:25:09.267343 RX DATLAT : PASS
1903 00:25:09.267775 RX DQ/DQS(Engine): PASS
1904 00:25:09.270330 TX OE : NO K
1905 00:25:09.270767 All Pass.
1906 00:25:09.271098
1907 00:25:09.273869 CH 0, Rank 1
1908 00:25:09.274456 SW Impedance : PASS
1909 00:25:09.277484 DUTY Scan : NO K
1910 00:25:09.280636 ZQ Calibration : PASS
1911 00:25:09.281145 Jitter Meter : NO K
1912 00:25:09.283741 CBT Training : PASS
1913 00:25:09.284172 Write leveling : PASS
1914 00:25:09.287242 RX DQS gating : PASS
1915 00:25:09.290609 RX DQ/DQS(RDDQC) : PASS
1916 00:25:09.291120 TX DQ/DQS : PASS
1917 00:25:09.293817 RX DATLAT : PASS
1918 00:25:09.297407 RX DQ/DQS(Engine): PASS
1919 00:25:09.297922 TX OE : NO K
1920 00:25:09.301240 All Pass.
1921 00:25:09.301754
1922 00:25:09.302087 CH 1, Rank 0
1923 00:25:09.303925 SW Impedance : PASS
1924 00:25:09.304435 DUTY Scan : NO K
1925 00:25:09.307079 ZQ Calibration : PASS
1926 00:25:09.311006 Jitter Meter : NO K
1927 00:25:09.311521 CBT Training : PASS
1928 00:25:09.313866 Write leveling : PASS
1929 00:25:09.317608 RX DQS gating : PASS
1930 00:25:09.318126 RX DQ/DQS(RDDQC) : PASS
1931 00:25:09.321010 TX DQ/DQS : PASS
1932 00:25:09.321526 RX DATLAT : PASS
1933 00:25:09.323783 RX DQ/DQS(Engine): PASS
1934 00:25:09.327208 TX OE : NO K
1935 00:25:09.327642 All Pass.
1936 00:25:09.327974
1937 00:25:09.328281 CH 1, Rank 1
1938 00:25:09.330620 SW Impedance : PASS
1939 00:25:09.334294 DUTY Scan : NO K
1940 00:25:09.334858 ZQ Calibration : PASS
1941 00:25:09.337276 Jitter Meter : NO K
1942 00:25:09.340490 CBT Training : PASS
1943 00:25:09.340984 Write leveling : PASS
1944 00:25:09.343806 RX DQS gating : PASS
1945 00:25:09.347136 RX DQ/DQS(RDDQC) : PASS
1946 00:25:09.347671 TX DQ/DQS : PASS
1947 00:25:09.351077 RX DATLAT : PASS
1948 00:25:09.354440 RX DQ/DQS(Engine): PASS
1949 00:25:09.354979 TX OE : NO K
1950 00:25:09.357213 All Pass.
1951 00:25:09.357702
1952 00:25:09.358041 DramC Write-DBI off
1953 00:25:09.360763 PER_BANK_REFRESH: Hybrid Mode
1954 00:25:09.361333 TX_TRACKING: ON
1955 00:25:09.364031 [GetDramInforAfterCalByMRR] Vendor 6.
1956 00:25:09.367531 [GetDramInforAfterCalByMRR] Revision 606.
1957 00:25:09.374527 [GetDramInforAfterCalByMRR] Revision 2 0.
1958 00:25:09.374972 MR0 0x3939
1959 00:25:09.375305 MR8 0x1111
1960 00:25:09.377482 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
1961 00:25:09.377916
1962 00:25:09.380895 MR0 0x3939
1963 00:25:09.381324 MR8 0x1111
1964 00:25:09.384002 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
1965 00:25:09.384436
1966 00:25:09.394097 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
1967 00:25:09.397648 [FAST_K] Save calibration result to emmc
1968 00:25:09.400669 [FAST_K] Save calibration result to emmc
1969 00:25:09.404073 dram_init: config_dvfs: 1
1970 00:25:09.407681 dramc_set_vcore_voltage set vcore to 662500
1971 00:25:09.408199 Read voltage for 1200, 2
1972 00:25:09.411044 Vio18 = 0
1973 00:25:09.411559 Vcore = 662500
1974 00:25:09.411895 Vdram = 0
1975 00:25:09.414885 Vddq = 0
1976 00:25:09.415414 Vmddr = 0
1977 00:25:09.420801 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
1978 00:25:09.424272 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
1979 00:25:09.427556 MEM_TYPE=3, freq_sel=15
1980 00:25:09.430563 sv_algorithm_assistance_LP4_1600
1981 00:25:09.434192 ============ PULL DRAM RESETB DOWN ============
1982 00:25:09.437566 ========== PULL DRAM RESETB DOWN end =========
1983 00:25:09.443760 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
1984 00:25:09.447545 ===================================
1985 00:25:09.448061 LPDDR4 DRAM CONFIGURATION
1986 00:25:09.450978 ===================================
1987 00:25:09.454444 EX_ROW_EN[0] = 0x0
1988 00:25:09.454950 EX_ROW_EN[1] = 0x0
1989 00:25:09.457576 LP4Y_EN = 0x0
1990 00:25:09.458030 WORK_FSP = 0x0
1991 00:25:09.460852 WL = 0x4
1992 00:25:09.461281 RL = 0x4
1993 00:25:09.463944 BL = 0x2
1994 00:25:09.467425 RPST = 0x0
1995 00:25:09.467852 RD_PRE = 0x0
1996 00:25:09.470603 WR_PRE = 0x1
1997 00:25:09.471081 WR_PST = 0x0
1998 00:25:09.473933 DBI_WR = 0x0
1999 00:25:09.474398 DBI_RD = 0x0
2000 00:25:09.477614 OTF = 0x1
2001 00:25:09.481198 ===================================
2002 00:25:09.483832 ===================================
2003 00:25:09.484259 ANA top config
2004 00:25:09.487265 ===================================
2005 00:25:09.490877 DLL_ASYNC_EN = 0
2006 00:25:09.494355 ALL_SLAVE_EN = 0
2007 00:25:09.494982 NEW_RANK_MODE = 1
2008 00:25:09.497195 DLL_IDLE_MODE = 1
2009 00:25:09.500619 LP45_APHY_COMB_EN = 1
2010 00:25:09.503994 TX_ODT_DIS = 1
2011 00:25:09.504445 NEW_8X_MODE = 1
2012 00:25:09.507472 ===================================
2013 00:25:09.510523 ===================================
2014 00:25:09.513791 data_rate = 2400
2015 00:25:09.517137 CKR = 1
2016 00:25:09.520591 DQ_P2S_RATIO = 8
2017 00:25:09.524516 ===================================
2018 00:25:09.527211 CA_P2S_RATIO = 8
2019 00:25:09.530732 DQ_CA_OPEN = 0
2020 00:25:09.531155 DQ_SEMI_OPEN = 0
2021 00:25:09.533871 CA_SEMI_OPEN = 0
2022 00:25:09.537836 CA_FULL_RATE = 0
2023 00:25:09.540598 DQ_CKDIV4_EN = 0
2024 00:25:09.543660 CA_CKDIV4_EN = 0
2025 00:25:09.547018 CA_PREDIV_EN = 0
2026 00:25:09.547443 PH8_DLY = 17
2027 00:25:09.550666 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2028 00:25:09.553586 DQ_AAMCK_DIV = 4
2029 00:25:09.557041 CA_AAMCK_DIV = 4
2030 00:25:09.560765 CA_ADMCK_DIV = 4
2031 00:25:09.563920 DQ_TRACK_CA_EN = 0
2032 00:25:09.567414 CA_PICK = 1200
2033 00:25:09.567844 CA_MCKIO = 1200
2034 00:25:09.570307 MCKIO_SEMI = 0
2035 00:25:09.573795 PLL_FREQ = 2366
2036 00:25:09.577319 DQ_UI_PI_RATIO = 32
2037 00:25:09.580166 CA_UI_PI_RATIO = 0
2038 00:25:09.583728 ===================================
2039 00:25:09.586993 ===================================
2040 00:25:09.590773 memory_type:LPDDR4
2041 00:25:09.591198 GP_NUM : 10
2042 00:25:09.593954 SRAM_EN : 1
2043 00:25:09.594598 MD32_EN : 0
2044 00:25:09.597143 ===================================
2045 00:25:09.600561 [ANA_INIT] >>>>>>>>>>>>>>
2046 00:25:09.604151 <<<<<< [CONFIGURE PHASE]: ANA_TX
2047 00:25:09.607120 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2048 00:25:09.610601 ===================================
2049 00:25:09.614144 data_rate = 2400,PCW = 0X5b00
2050 00:25:09.617070 ===================================
2051 00:25:09.620447 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2052 00:25:09.624025 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2053 00:25:09.630814 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2054 00:25:09.633707 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2055 00:25:09.637499 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2056 00:25:09.643610 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2057 00:25:09.644055 [ANA_INIT] flow start
2058 00:25:09.647200 [ANA_INIT] PLL >>>>>>>>
2059 00:25:09.647729 [ANA_INIT] PLL <<<<<<<<
2060 00:25:09.650418 [ANA_INIT] MIDPI >>>>>>>>
2061 00:25:09.653745 [ANA_INIT] MIDPI <<<<<<<<
2062 00:25:09.657331 [ANA_INIT] DLL >>>>>>>>
2063 00:25:09.657860 [ANA_INIT] DLL <<<<<<<<
2064 00:25:09.660695 [ANA_INIT] flow end
2065 00:25:09.664232 ============ LP4 DIFF to SE enter ============
2066 00:25:09.667296 ============ LP4 DIFF to SE exit ============
2067 00:25:09.670739 [ANA_INIT] <<<<<<<<<<<<<
2068 00:25:09.673949 [Flow] Enable top DCM control >>>>>
2069 00:25:09.677251 [Flow] Enable top DCM control <<<<<
2070 00:25:09.680786 Enable DLL master slave shuffle
2071 00:25:09.687232 ==============================================================
2072 00:25:09.687746 Gating Mode config
2073 00:25:09.693935 ==============================================================
2074 00:25:09.694519 Config description:
2075 00:25:09.704698 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2076 00:25:09.710453 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2077 00:25:09.717100 SELPH_MODE 0: By rank 1: By Phase
2078 00:25:09.720406 ==============================================================
2079 00:25:09.724156 GAT_TRACK_EN = 1
2080 00:25:09.727203 RX_GATING_MODE = 2
2081 00:25:09.730352 RX_GATING_TRACK_MODE = 2
2082 00:25:09.733947 SELPH_MODE = 1
2083 00:25:09.737510 PICG_EARLY_EN = 1
2084 00:25:09.740420 VALID_LAT_VALUE = 1
2085 00:25:09.743658 ==============================================================
2086 00:25:09.747539 Enter into Gating configuration >>>>
2087 00:25:09.750337 Exit from Gating configuration <<<<
2088 00:25:09.753844 Enter into DVFS_PRE_config >>>>>
2089 00:25:09.767498 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2090 00:25:09.768235 Exit from DVFS_PRE_config <<<<<
2091 00:25:09.770620 Enter into PICG configuration >>>>
2092 00:25:09.774421 Exit from PICG configuration <<<<
2093 00:25:09.777401 [RX_INPUT] configuration >>>>>
2094 00:25:09.780977 [RX_INPUT] configuration <<<<<
2095 00:25:09.787442 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2096 00:25:09.790966 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2097 00:25:09.797631 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2098 00:25:09.803801 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2099 00:25:09.810668 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2100 00:25:09.817536 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2101 00:25:09.820759 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2102 00:25:09.824180 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2103 00:25:09.827155 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2104 00:25:09.833978 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2105 00:25:09.837543 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2106 00:25:09.841297 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2107 00:25:09.843938 ===================================
2108 00:25:09.847072 LPDDR4 DRAM CONFIGURATION
2109 00:25:09.850640 ===================================
2110 00:25:09.851152 EX_ROW_EN[0] = 0x0
2111 00:25:09.854575 EX_ROW_EN[1] = 0x0
2112 00:25:09.857359 LP4Y_EN = 0x0
2113 00:25:09.857868 WORK_FSP = 0x0
2114 00:25:09.860400 WL = 0x4
2115 00:25:09.860833 RL = 0x4
2116 00:25:09.863790 BL = 0x2
2117 00:25:09.864284 RPST = 0x0
2118 00:25:09.867043 RD_PRE = 0x0
2119 00:25:09.867624 WR_PRE = 0x1
2120 00:25:09.870491 WR_PST = 0x0
2121 00:25:09.870930 DBI_WR = 0x0
2122 00:25:09.873986 DBI_RD = 0x0
2123 00:25:09.874551 OTF = 0x1
2124 00:25:09.877108 ===================================
2125 00:25:09.880732 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2126 00:25:09.887036 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2127 00:25:09.890333 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2128 00:25:09.894002 ===================================
2129 00:25:09.897370 LPDDR4 DRAM CONFIGURATION
2130 00:25:09.900680 ===================================
2131 00:25:09.901209 EX_ROW_EN[0] = 0x10
2132 00:25:09.903399 EX_ROW_EN[1] = 0x0
2133 00:25:09.903841 LP4Y_EN = 0x0
2134 00:25:09.906966 WORK_FSP = 0x0
2135 00:25:09.907494 WL = 0x4
2136 00:25:09.910550 RL = 0x4
2137 00:25:09.913967 BL = 0x2
2138 00:25:09.914530 RPST = 0x0
2139 00:25:09.917398 RD_PRE = 0x0
2140 00:25:09.917920 WR_PRE = 0x1
2141 00:25:09.920488 WR_PST = 0x0
2142 00:25:09.920930 DBI_WR = 0x0
2143 00:25:09.923445 DBI_RD = 0x0
2144 00:25:09.923886 OTF = 0x1
2145 00:25:09.926680 ===================================
2146 00:25:09.933294 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2147 00:25:09.933822 ==
2148 00:25:09.937133 Dram Type= 6, Freq= 0, CH_0, rank 0
2149 00:25:09.940416 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2150 00:25:09.940949 ==
2151 00:25:09.943307 [Duty_Offset_Calibration]
2152 00:25:09.946670 B0:0 B1:2 CA:1
2153 00:25:09.947098
2154 00:25:09.950162 [DutyScan_Calibration_Flow] k_type=0
2155 00:25:09.958145
2156 00:25:09.958696 ==CLK 0==
2157 00:25:09.961432 Final CLK duty delay cell = 0
2158 00:25:09.965047 [0] MAX Duty = 5093%(X100), DQS PI = 12
2159 00:25:09.968001 [0] MIN Duty = 4938%(X100), DQS PI = 54
2160 00:25:09.968573 [0] AVG Duty = 5015%(X100)
2161 00:25:09.971248
2162 00:25:09.974854 CH0 CLK Duty spec in!! Max-Min= 155%
2163 00:25:09.978158 [DutyScan_Calibration_Flow] ====Done====
2164 00:25:09.978619
2165 00:25:09.981061 [DutyScan_Calibration_Flow] k_type=1
2166 00:25:09.997444
2167 00:25:09.997958 ==DQS 0 ==
2168 00:25:10.000817 Final DQS duty delay cell = 0
2169 00:25:10.003911 [0] MAX Duty = 5124%(X100), DQS PI = 50
2170 00:25:10.007689 [0] MIN Duty = 5031%(X100), DQS PI = 4
2171 00:25:10.008136 [0] AVG Duty = 5077%(X100)
2172 00:25:10.010826
2173 00:25:10.011263 ==DQS 1 ==
2174 00:25:10.014399 Final DQS duty delay cell = 0
2175 00:25:10.017295 [0] MAX Duty = 5031%(X100), DQS PI = 54
2176 00:25:10.020333 [0] MIN Duty = 4875%(X100), DQS PI = 20
2177 00:25:10.024175 [0] AVG Duty = 4953%(X100)
2178 00:25:10.024660
2179 00:25:10.027529 CH0 DQS 0 Duty spec in!! Max-Min= 93%
2180 00:25:10.027960
2181 00:25:10.030731 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2182 00:25:10.033809 [DutyScan_Calibration_Flow] ====Done====
2183 00:25:10.034269
2184 00:25:10.037416 [DutyScan_Calibration_Flow] k_type=3
2185 00:25:10.054420
2186 00:25:10.055133 ==DQM 0 ==
2187 00:25:10.057705 Final DQM duty delay cell = 0
2188 00:25:10.061652 [0] MAX Duty = 5124%(X100), DQS PI = 20
2189 00:25:10.064645 [0] MIN Duty = 4969%(X100), DQS PI = 40
2190 00:25:10.067674 [0] AVG Duty = 5046%(X100)
2191 00:25:10.068106
2192 00:25:10.068713 ==DQM 1 ==
2193 00:25:10.071021 Final DQM duty delay cell = 4
2194 00:25:10.074386 [4] MAX Duty = 5187%(X100), DQS PI = 54
2195 00:25:10.077872 [4] MIN Duty = 5000%(X100), DQS PI = 18
2196 00:25:10.081110 [4] AVG Duty = 5093%(X100)
2197 00:25:10.081635
2198 00:25:10.084304 CH0 DQM 0 Duty spec in!! Max-Min= 155%
2199 00:25:10.084739
2200 00:25:10.087930 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2201 00:25:10.091063 [DutyScan_Calibration_Flow] ====Done====
2202 00:25:10.091642
2203 00:25:10.094400 [DutyScan_Calibration_Flow] k_type=2
2204 00:25:10.110093
2205 00:25:10.110656 ==DQ 0 ==
2206 00:25:10.113284 Final DQ duty delay cell = -4
2207 00:25:10.116155 [-4] MAX Duty = 5062%(X100), DQS PI = 18
2208 00:25:10.119657 [-4] MIN Duty = 4813%(X100), DQS PI = 6
2209 00:25:10.122801 [-4] AVG Duty = 4937%(X100)
2210 00:25:10.123315
2211 00:25:10.123649 ==DQ 1 ==
2212 00:25:10.126530 Final DQ duty delay cell = -4
2213 00:25:10.129932 [-4] MAX Duty = 5062%(X100), DQS PI = 6
2214 00:25:10.133344 [-4] MIN Duty = 4876%(X100), DQS PI = 62
2215 00:25:10.136170 [-4] AVG Duty = 4969%(X100)
2216 00:25:10.136630
2217 00:25:10.139394 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2218 00:25:10.139827
2219 00:25:10.142610 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2220 00:25:10.145881 [DutyScan_Calibration_Flow] ====Done====
2221 00:25:10.146420 ==
2222 00:25:10.149452 Dram Type= 6, Freq= 0, CH_1, rank 0
2223 00:25:10.153097 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2224 00:25:10.153612 ==
2225 00:25:10.155880 [Duty_Offset_Calibration]
2226 00:25:10.156339 B0:0 B1:5 CA:-5
2227 00:25:10.156772
2228 00:25:10.159172 [DutyScan_Calibration_Flow] k_type=0
2229 00:25:10.169951
2230 00:25:10.170639 ==CLK 0==
2231 00:25:10.173189 Final CLK duty delay cell = 0
2232 00:25:10.176853 [0] MAX Duty = 5094%(X100), DQS PI = 24
2233 00:25:10.180030 [0] MIN Duty = 4907%(X100), DQS PI = 44
2234 00:25:10.180465 [0] AVG Duty = 5000%(X100)
2235 00:25:10.183309
2236 00:25:10.186547 CH1 CLK Duty spec in!! Max-Min= 187%
2237 00:25:10.190067 [DutyScan_Calibration_Flow] ====Done====
2238 00:25:10.190549
2239 00:25:10.193311 [DutyScan_Calibration_Flow] k_type=1
2240 00:25:10.208818
2241 00:25:10.209247 ==DQS 0 ==
2242 00:25:10.212084 Final DQS duty delay cell = 0
2243 00:25:10.215055 [0] MAX Duty = 5125%(X100), DQS PI = 16
2244 00:25:10.218834 [0] MIN Duty = 4875%(X100), DQS PI = 40
2245 00:25:10.221535 [0] AVG Duty = 5000%(X100)
2246 00:25:10.221923
2247 00:25:10.222337 ==DQS 1 ==
2248 00:25:10.225398 Final DQS duty delay cell = -4
2249 00:25:10.228289 [-4] MAX Duty = 5000%(X100), DQS PI = 4
2250 00:25:10.231751 [-4] MIN Duty = 4876%(X100), DQS PI = 60
2251 00:25:10.235459 [-4] AVG Duty = 4938%(X100)
2252 00:25:10.235848
2253 00:25:10.238932 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2254 00:25:10.239425
2255 00:25:10.241577 CH1 DQS 1 Duty spec in!! Max-Min= 124%
2256 00:25:10.245500 [DutyScan_Calibration_Flow] ====Done====
2257 00:25:10.245966
2258 00:25:10.248254 [DutyScan_Calibration_Flow] k_type=3
2259 00:25:10.264259
2260 00:25:10.264785 ==DQM 0 ==
2261 00:25:10.266978 Final DQM duty delay cell = -4
2262 00:25:10.270514 [-4] MAX Duty = 5062%(X100), DQS PI = 30
2263 00:25:10.273874 [-4] MIN Duty = 4844%(X100), DQS PI = 42
2264 00:25:10.277317 [-4] AVG Duty = 4953%(X100)
2265 00:25:10.277745
2266 00:25:10.278074 ==DQM 1 ==
2267 00:25:10.280090 Final DQM duty delay cell = -4
2268 00:25:10.283508 [-4] MAX Duty = 5094%(X100), DQS PI = 22
2269 00:25:10.286745 [-4] MIN Duty = 4906%(X100), DQS PI = 42
2270 00:25:10.290081 [-4] AVG Duty = 5000%(X100)
2271 00:25:10.290505
2272 00:25:10.293711 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2273 00:25:10.294101
2274 00:25:10.297324 CH1 DQM 1 Duty spec in!! Max-Min= 188%
2275 00:25:10.300223 [DutyScan_Calibration_Flow] ====Done====
2276 00:25:10.300617
2277 00:25:10.303394 [DutyScan_Calibration_Flow] k_type=2
2278 00:25:10.321490
2279 00:25:10.321993 ==DQ 0 ==
2280 00:25:10.324110 Final DQ duty delay cell = 0
2281 00:25:10.327651 [0] MAX Duty = 5062%(X100), DQS PI = 0
2282 00:25:10.331165 [0] MIN Duty = 4938%(X100), DQS PI = 44
2283 00:25:10.331675 [0] AVG Duty = 5000%(X100)
2284 00:25:10.332007
2285 00:25:10.334172 ==DQ 1 ==
2286 00:25:10.338191 Final DQ duty delay cell = 0
2287 00:25:10.340954 [0] MAX Duty = 5000%(X100), DQS PI = 6
2288 00:25:10.344656 [0] MIN Duty = 4907%(X100), DQS PI = 0
2289 00:25:10.345162 [0] AVG Duty = 4953%(X100)
2290 00:25:10.345500
2291 00:25:10.347741 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2292 00:25:10.348171
2293 00:25:10.350710 CH1 DQ 1 Duty spec in!! Max-Min= 93%
2294 00:25:10.358113 [DutyScan_Calibration_Flow] ====Done====
2295 00:25:10.361233 nWR fixed to 30
2296 00:25:10.361757 [ModeRegInit_LP4] CH0 RK0
2297 00:25:10.364658 [ModeRegInit_LP4] CH0 RK1
2298 00:25:10.367372 [ModeRegInit_LP4] CH1 RK0
2299 00:25:10.367802 [ModeRegInit_LP4] CH1 RK1
2300 00:25:10.370628 match AC timing 6
2301 00:25:10.374097 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2302 00:25:10.377811 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2303 00:25:10.384351 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2304 00:25:10.387390 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2305 00:25:10.394145 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2306 00:25:10.394609 ==
2307 00:25:10.397291 Dram Type= 6, Freq= 0, CH_0, rank 0
2308 00:25:10.400612 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2309 00:25:10.401040 ==
2310 00:25:10.407196 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2311 00:25:10.410841 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2312 00:25:10.420545 [CA 0] Center 39 (9~70) winsize 62
2313 00:25:10.424322 [CA 1] Center 39 (8~70) winsize 63
2314 00:25:10.427291 [CA 2] Center 36 (5~67) winsize 63
2315 00:25:10.430744 [CA 3] Center 35 (4~66) winsize 63
2316 00:25:10.434206 [CA 4] Center 34 (3~65) winsize 63
2317 00:25:10.437225 [CA 5] Center 33 (3~64) winsize 62
2318 00:25:10.437604
2319 00:25:10.440220 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2320 00:25:10.440516
2321 00:25:10.443581 [CATrainingPosCal] consider 1 rank data
2322 00:25:10.446925 u2DelayCellTimex100 = 270/100 ps
2323 00:25:10.450490 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2324 00:25:10.453655 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2325 00:25:10.460687 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2326 00:25:10.464431 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2327 00:25:10.466978 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2328 00:25:10.470958 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2329 00:25:10.471494
2330 00:25:10.473700 CA PerBit enable=1, Macro0, CA PI delay=33
2331 00:25:10.474124
2332 00:25:10.477202 [CBTSetCACLKResult] CA Dly = 33
2333 00:25:10.477626 CS Dly: 7 (0~38)
2334 00:25:10.477957 ==
2335 00:25:10.481034 Dram Type= 6, Freq= 0, CH_0, rank 1
2336 00:25:10.487522 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2337 00:25:10.488026 ==
2338 00:25:10.490649 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2339 00:25:10.497532 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2340 00:25:10.505902 [CA 0] Center 39 (8~70) winsize 63
2341 00:25:10.509355 [CA 1] Center 39 (8~70) winsize 63
2342 00:25:10.512841 [CA 2] Center 36 (5~67) winsize 63
2343 00:25:10.516186 [CA 3] Center 35 (4~66) winsize 63
2344 00:25:10.519513 [CA 4] Center 33 (3~64) winsize 62
2345 00:25:10.523120 [CA 5] Center 34 (3~65) winsize 63
2346 00:25:10.523655
2347 00:25:10.526363 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2348 00:25:10.526868
2349 00:25:10.529631 [CATrainingPosCal] consider 2 rank data
2350 00:25:10.533286 u2DelayCellTimex100 = 270/100 ps
2351 00:25:10.536164 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2352 00:25:10.539505 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2353 00:25:10.546183 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2354 00:25:10.549637 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2355 00:25:10.552921 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2356 00:25:10.555910 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2357 00:25:10.556333
2358 00:25:10.559372 CA PerBit enable=1, Macro0, CA PI delay=33
2359 00:25:10.559797
2360 00:25:10.562818 [CBTSetCACLKResult] CA Dly = 33
2361 00:25:10.563329 CS Dly: 7 (0~39)
2362 00:25:10.563658
2363 00:25:10.566299 ----->DramcWriteLeveling(PI) begin...
2364 00:25:10.569492 ==
2365 00:25:10.569992 Dram Type= 6, Freq= 0, CH_0, rank 0
2366 00:25:10.576046 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2367 00:25:10.576554 ==
2368 00:25:10.579530 Write leveling (Byte 0): 28 => 28
2369 00:25:10.583081 Write leveling (Byte 1): 26 => 26
2370 00:25:10.586265 DramcWriteLeveling(PI) end<-----
2371 00:25:10.586794
2372 00:25:10.587127 ==
2373 00:25:10.589651 Dram Type= 6, Freq= 0, CH_0, rank 0
2374 00:25:10.592736 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2375 00:25:10.593168 ==
2376 00:25:10.595888 [Gating] SW mode calibration
2377 00:25:10.602885 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2378 00:25:10.606180 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2379 00:25:10.612926 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2380 00:25:10.616253 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2381 00:25:10.619399 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2382 00:25:10.626037 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2383 00:25:10.629610 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2384 00:25:10.633045 0 11 20 | B1->B0 | 2c2c 2a2a | 1 1 | (1 0) (1 0)
2385 00:25:10.639626 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2386 00:25:10.642991 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2387 00:25:10.646427 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2388 00:25:10.653269 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2389 00:25:10.656336 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2390 00:25:10.659454 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2391 00:25:10.666358 0 12 16 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
2392 00:25:10.669834 0 12 20 | B1->B0 | 3e3e 4141 | 0 0 | (0 0) (0 0)
2393 00:25:10.673106 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2394 00:25:10.679611 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2395 00:25:10.682748 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2396 00:25:10.686366 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2397 00:25:10.689565 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2398 00:25:10.696416 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2399 00:25:10.699771 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2400 00:25:10.703085 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2401 00:25:10.709430 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2402 00:25:10.713237 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2403 00:25:10.716012 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2404 00:25:10.723154 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2405 00:25:10.725987 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2406 00:25:10.729704 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2407 00:25:10.735983 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2408 00:25:10.739494 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2409 00:25:10.742961 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2410 00:25:10.749545 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2411 00:25:10.753147 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2412 00:25:10.755823 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2413 00:25:10.762465 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2414 00:25:10.766139 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2415 00:25:10.769483 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2416 00:25:10.775835 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2417 00:25:10.779019 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2418 00:25:10.782620 Total UI for P1: 0, mck2ui 16
2419 00:25:10.785714 best dqsien dly found for B0: ( 0, 15, 18)
2420 00:25:10.789076 Total UI for P1: 0, mck2ui 16
2421 00:25:10.793090 best dqsien dly found for B1: ( 0, 15, 18)
2422 00:25:10.796173 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2423 00:25:10.799287 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2424 00:25:10.799719
2425 00:25:10.802621 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2426 00:25:10.805927 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2427 00:25:10.809479 [Gating] SW calibration Done
2428 00:25:10.809908 ==
2429 00:25:10.812309 Dram Type= 6, Freq= 0, CH_0, rank 0
2430 00:25:10.816376 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2431 00:25:10.816887 ==
2432 00:25:10.819103 RX Vref Scan: 0
2433 00:25:10.819533
2434 00:25:10.822506 RX Vref 0 -> 0, step: 1
2435 00:25:10.822943
2436 00:25:10.823276 RX Delay -40 -> 252, step: 8
2437 00:25:10.829082 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2438 00:25:10.832769 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2439 00:25:10.835837 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2440 00:25:10.839010 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2441 00:25:10.842743 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2442 00:25:10.849072 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2443 00:25:10.852461 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2444 00:25:10.856130 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2445 00:25:10.859156 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2446 00:25:10.862564 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2447 00:25:10.869516 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2448 00:25:10.872351 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2449 00:25:10.875957 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2450 00:25:10.879044 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2451 00:25:10.882763 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2452 00:25:10.889674 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2453 00:25:10.890182 ==
2454 00:25:10.893051 Dram Type= 6, Freq= 0, CH_0, rank 0
2455 00:25:10.895933 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2456 00:25:10.896443 ==
2457 00:25:10.896780 DQS Delay:
2458 00:25:10.899515 DQS0 = 0, DQS1 = 0
2459 00:25:10.899948 DQM Delay:
2460 00:25:10.902795 DQM0 = 115, DQM1 = 105
2461 00:25:10.903300 DQ Delay:
2462 00:25:10.905945 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =107
2463 00:25:10.909209 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2464 00:25:10.912722 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =99
2465 00:25:10.916195 DQ12 =111, DQ13 =115, DQ14 =115, DQ15 =115
2466 00:25:10.916704
2467 00:25:10.917035
2468 00:25:10.917340 ==
2469 00:25:10.919619 Dram Type= 6, Freq= 0, CH_0, rank 0
2470 00:25:10.926095 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2471 00:25:10.926638 ==
2472 00:25:10.926976
2473 00:25:10.927281
2474 00:25:10.927573 TX Vref Scan disable
2475 00:25:10.929730 == TX Byte 0 ==
2476 00:25:10.933124 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2477 00:25:10.936840 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2478 00:25:10.939377 == TX Byte 1 ==
2479 00:25:10.943389 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2480 00:25:10.946253 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2481 00:25:10.949538 ==
2482 00:25:10.953131 Dram Type= 6, Freq= 0, CH_0, rank 0
2483 00:25:10.956551 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2484 00:25:10.957198 ==
2485 00:25:10.967024 TX Vref=22, minBit 9, minWin=25, winSum=416
2486 00:25:10.970834 TX Vref=24, minBit 9, minWin=25, winSum=421
2487 00:25:10.973827 TX Vref=26, minBit 10, minWin=25, winSum=425
2488 00:25:10.977356 TX Vref=28, minBit 10, minWin=25, winSum=433
2489 00:25:10.980989 TX Vref=30, minBit 8, minWin=26, winSum=435
2490 00:25:10.987516 TX Vref=32, minBit 9, minWin=26, winSum=435
2491 00:25:10.990976 [TxChooseVref] Worse bit 8, Min win 26, Win sum 435, Final Vref 30
2492 00:25:10.991406
2493 00:25:10.993935 Final TX Range 1 Vref 30
2494 00:25:10.994396
2495 00:25:10.994725 ==
2496 00:25:10.997360 Dram Type= 6, Freq= 0, CH_0, rank 0
2497 00:25:11.000696 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2498 00:25:11.003773 ==
2499 00:25:11.004194
2500 00:25:11.004523
2501 00:25:11.004826 TX Vref Scan disable
2502 00:25:11.007327 == TX Byte 0 ==
2503 00:25:11.010371 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2504 00:25:11.017803 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2505 00:25:11.018476 == TX Byte 1 ==
2506 00:25:11.020433 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2507 00:25:11.027464 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2508 00:25:11.027967
2509 00:25:11.028294 [DATLAT]
2510 00:25:11.028597 Freq=1200, CH0 RK0
2511 00:25:11.028893
2512 00:25:11.030329 DATLAT Default: 0xd
2513 00:25:11.030757 0, 0xFFFF, sum = 0
2514 00:25:11.033569 1, 0xFFFF, sum = 0
2515 00:25:11.037049 2, 0xFFFF, sum = 0
2516 00:25:11.037562 3, 0xFFFF, sum = 0
2517 00:25:11.040511 4, 0xFFFF, sum = 0
2518 00:25:11.041052 5, 0xFFFF, sum = 0
2519 00:25:11.043464 6, 0xFFFF, sum = 0
2520 00:25:11.043896 7, 0xFFFF, sum = 0
2521 00:25:11.047002 8, 0xFFFF, sum = 0
2522 00:25:11.047490 9, 0xFFFF, sum = 0
2523 00:25:11.050628 10, 0xFFFF, sum = 0
2524 00:25:11.051143 11, 0x0, sum = 1
2525 00:25:11.054138 12, 0x0, sum = 2
2526 00:25:11.054693 13, 0x0, sum = 3
2527 00:25:11.057026 14, 0x0, sum = 4
2528 00:25:11.057462 best_step = 12
2529 00:25:11.057796
2530 00:25:11.058101 ==
2531 00:25:11.060108 Dram Type= 6, Freq= 0, CH_0, rank 0
2532 00:25:11.063342 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2533 00:25:11.063792 ==
2534 00:25:11.066907 RX Vref Scan: 1
2535 00:25:11.067392
2536 00:25:11.070370 Set Vref Range= 32 -> 127
2537 00:25:11.070801
2538 00:25:11.071134 RX Vref 32 -> 127, step: 1
2539 00:25:11.071445
2540 00:25:11.073345 RX Delay -21 -> 252, step: 4
2541 00:25:11.073792
2542 00:25:11.076742 Set Vref, RX VrefLevel [Byte0]: 32
2543 00:25:11.080695 [Byte1]: 32
2544 00:25:11.084144
2545 00:25:11.084652 Set Vref, RX VrefLevel [Byte0]: 33
2546 00:25:11.087292 [Byte1]: 33
2547 00:25:11.091647
2548 00:25:11.092081 Set Vref, RX VrefLevel [Byte0]: 34
2549 00:25:11.094839 [Byte1]: 34
2550 00:25:11.099580
2551 00:25:11.102905 Set Vref, RX VrefLevel [Byte0]: 35
2552 00:25:11.106014 [Byte1]: 35
2553 00:25:11.106506
2554 00:25:11.109754 Set Vref, RX VrefLevel [Byte0]: 36
2555 00:25:11.113231 [Byte1]: 36
2556 00:25:11.113736
2557 00:25:11.116703 Set Vref, RX VrefLevel [Byte0]: 37
2558 00:25:11.119497 [Byte1]: 37
2559 00:25:11.123521
2560 00:25:11.124023 Set Vref, RX VrefLevel [Byte0]: 38
2561 00:25:11.126951 [Byte1]: 38
2562 00:25:11.131552
2563 00:25:11.132057 Set Vref, RX VrefLevel [Byte0]: 39
2564 00:25:11.135170 [Byte1]: 39
2565 00:25:11.139346
2566 00:25:11.139866 Set Vref, RX VrefLevel [Byte0]: 40
2567 00:25:11.143109 [Byte1]: 40
2568 00:25:11.147433
2569 00:25:11.147945 Set Vref, RX VrefLevel [Byte0]: 41
2570 00:25:11.150682 [Byte1]: 41
2571 00:25:11.155495
2572 00:25:11.155998 Set Vref, RX VrefLevel [Byte0]: 42
2573 00:25:11.159087 [Byte1]: 42
2574 00:25:11.163443
2575 00:25:11.163947 Set Vref, RX VrefLevel [Byte0]: 43
2576 00:25:11.166400 [Byte1]: 43
2577 00:25:11.171112
2578 00:25:11.171615 Set Vref, RX VrefLevel [Byte0]: 44
2579 00:25:11.174480 [Byte1]: 44
2580 00:25:11.179096
2581 00:25:11.179594 Set Vref, RX VrefLevel [Byte0]: 45
2582 00:25:11.182132 [Byte1]: 45
2583 00:25:11.186624
2584 00:25:11.187119 Set Vref, RX VrefLevel [Byte0]: 46
2585 00:25:11.190075 [Byte1]: 46
2586 00:25:11.194619
2587 00:25:11.195195 Set Vref, RX VrefLevel [Byte0]: 47
2588 00:25:11.197995 [Byte1]: 47
2589 00:25:11.203215
2590 00:25:11.203806 Set Vref, RX VrefLevel [Byte0]: 48
2591 00:25:11.205812 [Byte1]: 48
2592 00:25:11.210613
2593 00:25:11.211036 Set Vref, RX VrefLevel [Byte0]: 49
2594 00:25:11.213922 [Byte1]: 49
2595 00:25:11.218405
2596 00:25:11.218866 Set Vref, RX VrefLevel [Byte0]: 50
2597 00:25:11.221725 [Byte1]: 50
2598 00:25:11.226163
2599 00:25:11.226634 Set Vref, RX VrefLevel [Byte0]: 51
2600 00:25:11.229763 [Byte1]: 51
2601 00:25:11.234052
2602 00:25:11.234140 Set Vref, RX VrefLevel [Byte0]: 52
2603 00:25:11.237280 [Byte1]: 52
2604 00:25:11.241731
2605 00:25:11.241823 Set Vref, RX VrefLevel [Byte0]: 53
2606 00:25:11.245153 [Byte1]: 53
2607 00:25:11.249915
2608 00:25:11.249994 Set Vref, RX VrefLevel [Byte0]: 54
2609 00:25:11.253087 [Byte1]: 54
2610 00:25:11.257522
2611 00:25:11.257590 Set Vref, RX VrefLevel [Byte0]: 55
2612 00:25:11.261079 [Byte1]: 55
2613 00:25:11.265697
2614 00:25:11.265765 Set Vref, RX VrefLevel [Byte0]: 56
2615 00:25:11.268825 [Byte1]: 56
2616 00:25:11.273424
2617 00:25:11.273489 Set Vref, RX VrefLevel [Byte0]: 57
2618 00:25:11.276591 [Byte1]: 57
2619 00:25:11.281722
2620 00:25:11.281815 Set Vref, RX VrefLevel [Byte0]: 58
2621 00:25:11.285004 [Byte1]: 58
2622 00:25:11.289161
2623 00:25:11.289236 Set Vref, RX VrefLevel [Byte0]: 59
2624 00:25:11.292931 [Byte1]: 59
2625 00:25:11.297400
2626 00:25:11.297487 Set Vref, RX VrefLevel [Byte0]: 60
2627 00:25:11.300567 [Byte1]: 60
2628 00:25:11.305315
2629 00:25:11.305408 Set Vref, RX VrefLevel [Byte0]: 61
2630 00:25:11.308591 [Byte1]: 61
2631 00:25:11.313244
2632 00:25:11.313356 Set Vref, RX VrefLevel [Byte0]: 62
2633 00:25:11.316458 [Byte1]: 62
2634 00:25:11.321515
2635 00:25:11.321653 Set Vref, RX VrefLevel [Byte0]: 63
2636 00:25:11.324604 [Byte1]: 63
2637 00:25:11.329047
2638 00:25:11.329205 Set Vref, RX VrefLevel [Byte0]: 64
2639 00:25:11.332411 [Byte1]: 64
2640 00:25:11.337639
2641 00:25:11.337930 Set Vref, RX VrefLevel [Byte0]: 65
2642 00:25:11.341190 [Byte1]: 65
2643 00:25:11.344916
2644 00:25:11.345198 Set Vref, RX VrefLevel [Byte0]: 66
2645 00:25:11.348703 [Byte1]: 66
2646 00:25:11.353310
2647 00:25:11.353692 Final RX Vref Byte 0 = 46 to rank0
2648 00:25:11.356501 Final RX Vref Byte 1 = 49 to rank0
2649 00:25:11.359755 Final RX Vref Byte 0 = 46 to rank1
2650 00:25:11.363238 Final RX Vref Byte 1 = 49 to rank1==
2651 00:25:11.366569 Dram Type= 6, Freq= 0, CH_0, rank 0
2652 00:25:11.373467 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2653 00:25:11.373959 ==
2654 00:25:11.374493 DQS Delay:
2655 00:25:11.374810 DQS0 = 0, DQS1 = 0
2656 00:25:11.376386 DQM Delay:
2657 00:25:11.376829 DQM0 = 113, DQM1 = 105
2658 00:25:11.379842 DQ Delay:
2659 00:25:11.383045 DQ0 =110, DQ1 =114, DQ2 =112, DQ3 =108
2660 00:25:11.387129 DQ4 =118, DQ5 =104, DQ6 =124, DQ7 =120
2661 00:25:11.390173 DQ8 =94, DQ9 =86, DQ10 =106, DQ11 =96
2662 00:25:11.393666 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =116
2663 00:25:11.394087
2664 00:25:11.394446
2665 00:25:11.399878 [DQSOSCAuto] RK0, (LSB)MR18= 0x808, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
2666 00:25:11.402908 CH0 RK0: MR19=404, MR18=808
2667 00:25:11.409955 CH0_RK0: MR19=0x404, MR18=0x808, DQSOSC=406, MR23=63, INC=39, DEC=26
2668 00:25:11.410546
2669 00:25:11.413135 ----->DramcWriteLeveling(PI) begin...
2670 00:25:11.413649 ==
2671 00:25:11.416725 Dram Type= 6, Freq= 0, CH_0, rank 1
2672 00:25:11.420200 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2673 00:25:11.420686 ==
2674 00:25:11.423265 Write leveling (Byte 0): 26 => 26
2675 00:25:11.426469 Write leveling (Byte 1): 24 => 24
2676 00:25:11.429641 DramcWriteLeveling(PI) end<-----
2677 00:25:11.430025
2678 00:25:11.430363 ==
2679 00:25:11.433231 Dram Type= 6, Freq= 0, CH_0, rank 1
2680 00:25:11.436613 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2681 00:25:11.440011 ==
2682 00:25:11.440396 [Gating] SW mode calibration
2683 00:25:11.450096 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2684 00:25:11.453156 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2685 00:25:11.456545 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2686 00:25:11.462891 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2687 00:25:11.466463 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2688 00:25:11.469743 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2689 00:25:11.476200 0 11 16 | B1->B0 | 3434 3333 | 1 1 | (1 0) (1 0)
2690 00:25:11.479715 0 11 20 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
2691 00:25:11.483018 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2692 00:25:11.489729 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2693 00:25:11.493243 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2694 00:25:11.496502 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2695 00:25:11.502975 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2696 00:25:11.506393 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2697 00:25:11.509968 0 12 16 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)
2698 00:25:11.516397 0 12 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
2699 00:25:11.519576 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2700 00:25:11.523214 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2701 00:25:11.529875 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2702 00:25:11.533015 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2703 00:25:11.536280 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2704 00:25:11.539591 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2705 00:25:11.546545 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2706 00:25:11.549211 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2707 00:25:11.553169 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2708 00:25:11.559441 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2709 00:25:11.563116 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2710 00:25:11.566362 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2711 00:25:11.572899 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2712 00:25:11.576401 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2713 00:25:11.579440 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2714 00:25:11.586359 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2715 00:25:11.589475 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2716 00:25:11.592833 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2717 00:25:11.599610 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2718 00:25:11.603038 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2719 00:25:11.606294 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2720 00:25:11.613051 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2721 00:25:11.616263 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2722 00:25:11.619846 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2723 00:25:11.626540 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2724 00:25:11.627046 Total UI for P1: 0, mck2ui 16
2725 00:25:11.632937 best dqsien dly found for B0: ( 0, 15, 18)
2726 00:25:11.633440 Total UI for P1: 0, mck2ui 16
2727 00:25:11.636513 best dqsien dly found for B1: ( 0, 15, 20)
2728 00:25:11.643172 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2729 00:25:11.645860 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2730 00:25:11.646317
2731 00:25:11.649382 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2732 00:25:11.652748 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2733 00:25:11.655996 [Gating] SW calibration Done
2734 00:25:11.656502 ==
2735 00:25:11.659204 Dram Type= 6, Freq= 0, CH_0, rank 1
2736 00:25:11.662415 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2737 00:25:11.662851 ==
2738 00:25:11.666088 RX Vref Scan: 0
2739 00:25:11.666612
2740 00:25:11.666947 RX Vref 0 -> 0, step: 1
2741 00:25:11.667252
2742 00:25:11.669371 RX Delay -40 -> 252, step: 8
2743 00:25:11.673059 iDelay=200, Bit 0, Center 107 (32 ~ 183) 152
2744 00:25:11.679111 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2745 00:25:11.683188 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2746 00:25:11.686281 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2747 00:25:11.689477 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2748 00:25:11.693170 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2749 00:25:11.699102 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2750 00:25:11.703107 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2751 00:25:11.706599 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2752 00:25:11.709558 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2753 00:25:11.712748 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2754 00:25:11.716440 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2755 00:25:11.722740 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2756 00:25:11.725940 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2757 00:25:11.729686 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2758 00:25:11.733097 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2759 00:25:11.733622 ==
2760 00:25:11.736441 Dram Type= 6, Freq= 0, CH_0, rank 1
2761 00:25:11.742932 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2762 00:25:11.743459 ==
2763 00:25:11.743793 DQS Delay:
2764 00:25:11.744098 DQS0 = 0, DQS1 = 0
2765 00:25:11.745976 DQM Delay:
2766 00:25:11.746423 DQM0 = 113, DQM1 = 107
2767 00:25:11.749460 DQ Delay:
2768 00:25:11.752578 DQ0 =107, DQ1 =115, DQ2 =111, DQ3 =111
2769 00:25:11.756425 DQ4 =115, DQ5 =107, DQ6 =119, DQ7 =123
2770 00:25:11.759655 DQ8 =91, DQ9 =95, DQ10 =107, DQ11 =99
2771 00:25:11.762709 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
2772 00:25:11.763142
2773 00:25:11.763590
2774 00:25:11.763974 ==
2775 00:25:11.766082 Dram Type= 6, Freq= 0, CH_0, rank 1
2776 00:25:11.769151 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2777 00:25:11.769586 ==
2778 00:25:11.772518
2779 00:25:11.773015
2780 00:25:11.773346 TX Vref Scan disable
2781 00:25:11.776083 == TX Byte 0 ==
2782 00:25:11.779260 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2783 00:25:11.782612 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2784 00:25:11.786364 == TX Byte 1 ==
2785 00:25:11.789522 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
2786 00:25:11.793307 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
2787 00:25:11.793816 ==
2788 00:25:11.796209 Dram Type= 6, Freq= 0, CH_0, rank 1
2789 00:25:11.802703 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2790 00:25:11.803210 ==
2791 00:25:11.813231 TX Vref=22, minBit 1, minWin=24, winSum=412
2792 00:25:11.816572 TX Vref=24, minBit 8, minWin=25, winSum=419
2793 00:25:11.819973 TX Vref=26, minBit 8, minWin=25, winSum=422
2794 00:25:11.823109 TX Vref=28, minBit 9, minWin=25, winSum=425
2795 00:25:11.826343 TX Vref=30, minBit 1, minWin=26, winSum=426
2796 00:25:11.832973 TX Vref=32, minBit 8, minWin=25, winSum=424
2797 00:25:11.836374 [TxChooseVref] Worse bit 1, Min win 26, Win sum 426, Final Vref 30
2798 00:25:11.836881
2799 00:25:11.839654 Final TX Range 1 Vref 30
2800 00:25:11.840081
2801 00:25:11.840410 ==
2802 00:25:11.843302 Dram Type= 6, Freq= 0, CH_0, rank 1
2803 00:25:11.846644 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2804 00:25:11.847076 ==
2805 00:25:11.847507
2806 00:25:11.849870
2807 00:25:11.850314 TX Vref Scan disable
2808 00:25:11.852896 == TX Byte 0 ==
2809 00:25:11.856874 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2810 00:25:11.860277 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2811 00:25:11.862707 == TX Byte 1 ==
2812 00:25:11.865986 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
2813 00:25:11.869632 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
2814 00:25:11.873055
2815 00:25:11.873563 [DATLAT]
2816 00:25:11.873895 Freq=1200, CH0 RK1
2817 00:25:11.874245
2818 00:25:11.876759 DATLAT Default: 0xc
2819 00:25:11.877183 0, 0xFFFF, sum = 0
2820 00:25:11.880039 1, 0xFFFF, sum = 0
2821 00:25:11.880548 2, 0xFFFF, sum = 0
2822 00:25:11.882853 3, 0xFFFF, sum = 0
2823 00:25:11.883288 4, 0xFFFF, sum = 0
2824 00:25:11.885920 5, 0xFFFF, sum = 0
2825 00:25:11.889527 6, 0xFFFF, sum = 0
2826 00:25:11.890043 7, 0xFFFF, sum = 0
2827 00:25:11.892740 8, 0xFFFF, sum = 0
2828 00:25:11.893248 9, 0xFFFF, sum = 0
2829 00:25:11.896074 10, 0xFFFF, sum = 0
2830 00:25:11.896583 11, 0x0, sum = 1
2831 00:25:11.898975 12, 0x0, sum = 2
2832 00:25:11.899409 13, 0x0, sum = 3
2833 00:25:11.902504 14, 0x0, sum = 4
2834 00:25:11.903011 best_step = 12
2835 00:25:11.903343
2836 00:25:11.903645 ==
2837 00:25:11.905928 Dram Type= 6, Freq= 0, CH_0, rank 1
2838 00:25:11.909759 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2839 00:25:11.910324 ==
2840 00:25:11.912736 RX Vref Scan: 0
2841 00:25:11.913243
2842 00:25:11.915962 RX Vref 0 -> 0, step: 1
2843 00:25:11.916506
2844 00:25:11.916850 RX Delay -21 -> 252, step: 4
2845 00:25:11.923289 iDelay=195, Bit 0, Center 110 (39 ~ 182) 144
2846 00:25:11.926552 iDelay=195, Bit 1, Center 116 (43 ~ 190) 148
2847 00:25:11.930259 iDelay=195, Bit 2, Center 112 (43 ~ 182) 140
2848 00:25:11.933241 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
2849 00:25:11.937089 iDelay=195, Bit 4, Center 118 (47 ~ 190) 144
2850 00:25:11.943190 iDelay=195, Bit 5, Center 108 (39 ~ 178) 140
2851 00:25:11.946843 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
2852 00:25:11.949707 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
2853 00:25:11.953414 iDelay=195, Bit 8, Center 94 (31 ~ 158) 128
2854 00:25:11.956735 iDelay=195, Bit 9, Center 90 (27 ~ 154) 128
2855 00:25:11.963235 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
2856 00:25:11.966705 iDelay=195, Bit 11, Center 96 (35 ~ 158) 124
2857 00:25:11.969739 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
2858 00:25:11.973310 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
2859 00:25:11.976296 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
2860 00:25:11.982983 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
2861 00:25:11.983415 ==
2862 00:25:11.986804 Dram Type= 6, Freq= 0, CH_0, rank 1
2863 00:25:11.989917 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2864 00:25:11.990487 ==
2865 00:25:11.990832 DQS Delay:
2866 00:25:11.993057 DQS0 = 0, DQS1 = 0
2867 00:25:11.993482 DQM Delay:
2868 00:25:11.996936 DQM0 = 114, DQM1 = 105
2869 00:25:11.997442 DQ Delay:
2870 00:25:11.999830 DQ0 =110, DQ1 =116, DQ2 =112, DQ3 =108
2871 00:25:12.003392 DQ4 =118, DQ5 =108, DQ6 =122, DQ7 =122
2872 00:25:12.006290 DQ8 =94, DQ9 =90, DQ10 =110, DQ11 =96
2873 00:25:12.009727 DQ12 =112, DQ13 =112, DQ14 =116, DQ15 =114
2874 00:25:12.010281
2875 00:25:12.010623
2876 00:25:12.019804 [DQSOSCAuto] RK1, (LSB)MR18= 0x1414, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 402 ps
2877 00:25:12.023062 CH0 RK1: MR19=404, MR18=1414
2878 00:25:12.026784 CH0_RK1: MR19=0x404, MR18=0x1414, DQSOSC=402, MR23=63, INC=40, DEC=27
2879 00:25:12.029879 [RxdqsGatingPostProcess] freq 1200
2880 00:25:12.036527 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2881 00:25:12.039821 Pre-setting of DQS Precalculation
2882 00:25:12.043538 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2883 00:25:12.046564 ==
2884 00:25:12.047069 Dram Type= 6, Freq= 0, CH_1, rank 0
2885 00:25:12.053301 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2886 00:25:12.053805 ==
2887 00:25:12.056508 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2888 00:25:12.062737 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2889 00:25:12.071966 [CA 0] Center 37 (7~68) winsize 62
2890 00:25:12.075550 [CA 1] Center 37 (7~68) winsize 62
2891 00:25:12.078432 [CA 2] Center 34 (4~65) winsize 62
2892 00:25:12.081967 [CA 3] Center 33 (3~64) winsize 62
2893 00:25:12.085618 [CA 4] Center 32 (1~63) winsize 63
2894 00:25:12.088729 [CA 5] Center 32 (2~63) winsize 62
2895 00:25:12.089277
2896 00:25:12.092248 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2897 00:25:12.092766
2898 00:25:12.094918 [CATrainingPosCal] consider 1 rank data
2899 00:25:12.098592 u2DelayCellTimex100 = 270/100 ps
2900 00:25:12.101877 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2901 00:25:12.105480 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2902 00:25:12.112026 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2903 00:25:12.115550 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2904 00:25:12.118973 CA4 delay=32 (1~63),Diff = 0 PI (0 cell)
2905 00:25:12.122478 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2906 00:25:12.122995
2907 00:25:12.125567 CA PerBit enable=1, Macro0, CA PI delay=32
2908 00:25:12.126085
2909 00:25:12.128499 [CBTSetCACLKResult] CA Dly = 32
2910 00:25:12.128928 CS Dly: 5 (0~36)
2911 00:25:12.129259 ==
2912 00:25:12.131789 Dram Type= 6, Freq= 0, CH_1, rank 1
2913 00:25:12.138537 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2914 00:25:12.139052 ==
2915 00:25:12.141927 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2916 00:25:12.148612 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2917 00:25:12.156984 [CA 0] Center 37 (6~68) winsize 63
2918 00:25:12.160544 [CA 1] Center 37 (7~68) winsize 62
2919 00:25:12.163861 [CA 2] Center 34 (3~65) winsize 63
2920 00:25:12.167664 [CA 3] Center 33 (3~64) winsize 62
2921 00:25:12.170336 [CA 4] Center 32 (2~63) winsize 62
2922 00:25:12.173797 [CA 5] Center 31 (1~62) winsize 62
2923 00:25:12.174363
2924 00:25:12.177363 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2925 00:25:12.177867
2926 00:25:12.180601 [CATrainingPosCal] consider 2 rank data
2927 00:25:12.184015 u2DelayCellTimex100 = 270/100 ps
2928 00:25:12.186848 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2929 00:25:12.190407 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2930 00:25:12.197065 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2931 00:25:12.200367 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2932 00:25:12.204029 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2933 00:25:12.206883 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
2934 00:25:12.207319
2935 00:25:12.210646 CA PerBit enable=1, Macro0, CA PI delay=32
2936 00:25:12.211179
2937 00:25:12.213787 [CBTSetCACLKResult] CA Dly = 32
2938 00:25:12.214390 CS Dly: 6 (0~38)
2939 00:25:12.214823
2940 00:25:12.216980 ----->DramcWriteLeveling(PI) begin...
2941 00:25:12.220499 ==
2942 00:25:12.223848 Dram Type= 6, Freq= 0, CH_1, rank 0
2943 00:25:12.227201 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2944 00:25:12.227735 ==
2945 00:25:12.230808 Write leveling (Byte 0): 20 => 20
2946 00:25:12.233982 Write leveling (Byte 1): 23 => 23
2947 00:25:12.237170 DramcWriteLeveling(PI) end<-----
2948 00:25:12.237700
2949 00:25:12.238141 ==
2950 00:25:12.240611 Dram Type= 6, Freq= 0, CH_1, rank 0
2951 00:25:12.243993 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2952 00:25:12.244524 ==
2953 00:25:12.246837 [Gating] SW mode calibration
2954 00:25:12.253540 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2955 00:25:12.260394 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2956 00:25:12.263427 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2957 00:25:12.267261 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2958 00:25:12.269931 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2959 00:25:12.277099 0 11 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2960 00:25:12.280142 0 11 16 | B1->B0 | 2f2f 2727 | 0 0 | (0 1) (1 0)
2961 00:25:12.283511 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2962 00:25:12.290207 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2963 00:25:12.293939 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2964 00:25:12.297346 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2965 00:25:12.303615 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2966 00:25:12.307085 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2967 00:25:12.310579 0 12 12 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (1 1)
2968 00:25:12.317310 0 12 16 | B1->B0 | 2f2f 4444 | 0 0 | (1 1) (0 0)
2969 00:25:12.320329 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2970 00:25:12.323422 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2971 00:25:12.330359 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2972 00:25:12.333423 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2973 00:25:12.337003 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2974 00:25:12.343556 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2975 00:25:12.346914 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2976 00:25:12.350592 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2977 00:25:12.356986 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2978 00:25:12.360401 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2979 00:25:12.363762 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2980 00:25:12.367409 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2981 00:25:12.373849 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2982 00:25:12.376554 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2983 00:25:12.380634 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2984 00:25:12.386995 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2985 00:25:12.390355 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2986 00:25:12.393748 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2987 00:25:12.399968 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2988 00:25:12.403537 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2989 00:25:12.407027 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2990 00:25:12.414207 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2991 00:25:12.416881 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2992 00:25:12.420814 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2993 00:25:12.426818 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2994 00:25:12.427340 Total UI for P1: 0, mck2ui 16
2995 00:25:12.433710 best dqsien dly found for B0: ( 0, 15, 16)
2996 00:25:12.437180 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2997 00:25:12.439952 Total UI for P1: 0, mck2ui 16
2998 00:25:12.443553 best dqsien dly found for B1: ( 0, 15, 18)
2999 00:25:12.446984 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
3000 00:25:12.450333 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
3001 00:25:12.450866
3002 00:25:12.453675 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
3003 00:25:12.457003 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
3004 00:25:12.460306 [Gating] SW calibration Done
3005 00:25:12.460827 ==
3006 00:25:12.463701 Dram Type= 6, Freq= 0, CH_1, rank 0
3007 00:25:12.466694 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3008 00:25:12.467128 ==
3009 00:25:12.470566 RX Vref Scan: 0
3010 00:25:12.471097
3011 00:25:12.473745 RX Vref 0 -> 0, step: 1
3012 00:25:12.474287
3013 00:25:12.474632 RX Delay -40 -> 252, step: 8
3014 00:25:12.480502 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
3015 00:25:12.483959 iDelay=208, Bit 1, Center 107 (32 ~ 183) 152
3016 00:25:12.486981 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3017 00:25:12.489927 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3018 00:25:12.493858 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3019 00:25:12.500350 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3020 00:25:12.503405 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3021 00:25:12.506850 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3022 00:25:12.510150 iDelay=208, Bit 8, Center 87 (16 ~ 159) 144
3023 00:25:12.513628 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144
3024 00:25:12.520417 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3025 00:25:12.523805 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3026 00:25:12.527442 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3027 00:25:12.530287 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3028 00:25:12.533462 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3029 00:25:12.539967 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3030 00:25:12.540469 ==
3031 00:25:12.543691 Dram Type= 6, Freq= 0, CH_1, rank 0
3032 00:25:12.546703 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3033 00:25:12.547139 ==
3034 00:25:12.547469 DQS Delay:
3035 00:25:12.550534 DQS0 = 0, DQS1 = 0
3036 00:25:12.550968 DQM Delay:
3037 00:25:12.553283 DQM0 = 116, DQM1 = 108
3038 00:25:12.553834 DQ Delay:
3039 00:25:12.556840 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3040 00:25:12.560015 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3041 00:25:12.563191 DQ8 =87, DQ9 =95, DQ10 =111, DQ11 =99
3042 00:25:12.566826 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3043 00:25:12.567253
3044 00:25:12.567581
3045 00:25:12.569857 ==
3046 00:25:12.570464 Dram Type= 6, Freq= 0, CH_1, rank 0
3047 00:25:12.576661 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3048 00:25:12.577107 ==
3049 00:25:12.577537
3050 00:25:12.577933
3051 00:25:12.579890 TX Vref Scan disable
3052 00:25:12.580359 == TX Byte 0 ==
3053 00:25:12.583376 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3054 00:25:12.590290 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3055 00:25:12.590813 == TX Byte 1 ==
3056 00:25:12.593534 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3057 00:25:12.600074 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3058 00:25:12.600518 ==
3059 00:25:12.603043 Dram Type= 6, Freq= 0, CH_1, rank 0
3060 00:25:12.606414 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3061 00:25:12.606850 ==
3062 00:25:12.618546 TX Vref=22, minBit 3, minWin=24, winSum=409
3063 00:25:12.622391 TX Vref=24, minBit 11, minWin=25, winSum=421
3064 00:25:12.625054 TX Vref=26, minBit 1, minWin=25, winSum=420
3065 00:25:12.628585 TX Vref=28, minBit 15, minWin=25, winSum=427
3066 00:25:12.632185 TX Vref=30, minBit 1, minWin=26, winSum=428
3067 00:25:12.638746 TX Vref=32, minBit 3, minWin=26, winSum=426
3068 00:25:12.641615 [TxChooseVref] Worse bit 1, Min win 26, Win sum 428, Final Vref 30
3069 00:25:12.642051
3070 00:25:12.645466 Final TX Range 1 Vref 30
3071 00:25:12.646060
3072 00:25:12.646472 ==
3073 00:25:12.648513 Dram Type= 6, Freq= 0, CH_1, rank 0
3074 00:25:12.651534 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3075 00:25:12.651967 ==
3076 00:25:12.654922
3077 00:25:12.655349
3078 00:25:12.655681 TX Vref Scan disable
3079 00:25:12.658633 == TX Byte 0 ==
3080 00:25:12.661839 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3081 00:25:12.665331 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3082 00:25:12.668549 == TX Byte 1 ==
3083 00:25:12.671781 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3084 00:25:12.675192 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3085 00:25:12.678255
3086 00:25:12.678689 [DATLAT]
3087 00:25:12.679023 Freq=1200, CH1 RK0
3088 00:25:12.679339
3089 00:25:12.681624 DATLAT Default: 0xd
3090 00:25:12.682054 0, 0xFFFF, sum = 0
3091 00:25:12.685085 1, 0xFFFF, sum = 0
3092 00:25:12.685683 2, 0xFFFF, sum = 0
3093 00:25:12.688338 3, 0xFFFF, sum = 0
3094 00:25:12.688769 4, 0xFFFF, sum = 0
3095 00:25:12.691958 5, 0xFFFF, sum = 0
3096 00:25:12.692466 6, 0xFFFF, sum = 0
3097 00:25:12.695212 7, 0xFFFF, sum = 0
3098 00:25:12.698188 8, 0xFFFF, sum = 0
3099 00:25:12.698663 9, 0xFFFF, sum = 0
3100 00:25:12.701833 10, 0xFFFF, sum = 0
3101 00:25:12.702394 11, 0x0, sum = 1
3102 00:25:12.705400 12, 0x0, sum = 2
3103 00:25:12.705915 13, 0x0, sum = 3
3104 00:25:12.706313 14, 0x0, sum = 4
3105 00:25:12.708853 best_step = 12
3106 00:25:12.709360
3107 00:25:12.709687 ==
3108 00:25:12.711659 Dram Type= 6, Freq= 0, CH_1, rank 0
3109 00:25:12.715037 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3110 00:25:12.715523 ==
3111 00:25:12.718464 RX Vref Scan: 1
3112 00:25:12.718974
3113 00:25:12.721596 Set Vref Range= 32 -> 127
3114 00:25:12.722025
3115 00:25:12.722394 RX Vref 32 -> 127, step: 1
3116 00:25:12.722707
3117 00:25:12.725146 RX Delay -29 -> 252, step: 4
3118 00:25:12.725655
3119 00:25:12.728340 Set Vref, RX VrefLevel [Byte0]: 32
3120 00:25:12.731676 [Byte1]: 32
3121 00:25:12.735252
3122 00:25:12.735763 Set Vref, RX VrefLevel [Byte0]: 33
3123 00:25:12.738482 [Byte1]: 33
3124 00:25:12.743516
3125 00:25:12.744023 Set Vref, RX VrefLevel [Byte0]: 34
3126 00:25:12.746303 [Byte1]: 34
3127 00:25:12.750875
3128 00:25:12.751303 Set Vref, RX VrefLevel [Byte0]: 35
3129 00:25:12.754547 [Byte1]: 35
3130 00:25:12.758936
3131 00:25:12.759444 Set Vref, RX VrefLevel [Byte0]: 36
3132 00:25:12.762847 [Byte1]: 36
3133 00:25:12.766931
3134 00:25:12.767438 Set Vref, RX VrefLevel [Byte0]: 37
3135 00:25:12.770556 [Byte1]: 37
3136 00:25:12.775232
3137 00:25:12.775759 Set Vref, RX VrefLevel [Byte0]: 38
3138 00:25:12.778462 [Byte1]: 38
3139 00:25:12.782728
3140 00:25:12.783243 Set Vref, RX VrefLevel [Byte0]: 39
3141 00:25:12.786372 [Byte1]: 39
3142 00:25:12.790740
3143 00:25:12.791248 Set Vref, RX VrefLevel [Byte0]: 40
3144 00:25:12.794138 [Byte1]: 40
3145 00:25:12.798693
3146 00:25:12.799196 Set Vref, RX VrefLevel [Byte0]: 41
3147 00:25:12.802149 [Byte1]: 41
3148 00:25:12.806768
3149 00:25:12.807275 Set Vref, RX VrefLevel [Byte0]: 42
3150 00:25:12.810267 [Byte1]: 42
3151 00:25:12.814647
3152 00:25:12.815154 Set Vref, RX VrefLevel [Byte0]: 43
3153 00:25:12.818127 [Byte1]: 43
3154 00:25:12.822701
3155 00:25:12.823205 Set Vref, RX VrefLevel [Byte0]: 44
3156 00:25:12.826008 [Byte1]: 44
3157 00:25:12.830811
3158 00:25:12.831323 Set Vref, RX VrefLevel [Byte0]: 45
3159 00:25:12.834737 [Byte1]: 45
3160 00:25:12.838655
3161 00:25:12.839163 Set Vref, RX VrefLevel [Byte0]: 46
3162 00:25:12.842098 [Byte1]: 46
3163 00:25:12.846679
3164 00:25:12.847184 Set Vref, RX VrefLevel [Byte0]: 47
3165 00:25:12.849986 [Byte1]: 47
3166 00:25:12.854480
3167 00:25:12.855034 Set Vref, RX VrefLevel [Byte0]: 48
3168 00:25:12.858765 [Byte1]: 48
3169 00:25:12.862397
3170 00:25:12.862837 Set Vref, RX VrefLevel [Byte0]: 49
3171 00:25:12.865779 [Byte1]: 49
3172 00:25:12.870570
3173 00:25:12.871145 Set Vref, RX VrefLevel [Byte0]: 50
3174 00:25:12.873501 [Byte1]: 50
3175 00:25:12.878333
3176 00:25:12.878875 Set Vref, RX VrefLevel [Byte0]: 51
3177 00:25:12.881511 [Byte1]: 51
3178 00:25:12.886506
3179 00:25:12.886947 Set Vref, RX VrefLevel [Byte0]: 52
3180 00:25:12.889783 [Byte1]: 52
3181 00:25:12.894815
3182 00:25:12.895339 Set Vref, RX VrefLevel [Byte0]: 53
3183 00:25:12.897613 [Byte1]: 53
3184 00:25:12.902193
3185 00:25:12.902767 Set Vref, RX VrefLevel [Byte0]: 54
3186 00:25:12.905377 [Byte1]: 54
3187 00:25:12.910251
3188 00:25:12.910781 Set Vref, RX VrefLevel [Byte0]: 55
3189 00:25:12.913688 [Byte1]: 55
3190 00:25:12.918901
3191 00:25:12.919421 Set Vref, RX VrefLevel [Byte0]: 56
3192 00:25:12.921369 [Byte1]: 56
3193 00:25:12.926643
3194 00:25:12.927170 Set Vref, RX VrefLevel [Byte0]: 57
3195 00:25:12.929437 [Byte1]: 57
3196 00:25:12.934207
3197 00:25:12.934771 Set Vref, RX VrefLevel [Byte0]: 58
3198 00:25:12.937426 [Byte1]: 58
3199 00:25:12.942151
3200 00:25:12.942739 Set Vref, RX VrefLevel [Byte0]: 59
3201 00:25:12.945453 [Byte1]: 59
3202 00:25:12.950345
3203 00:25:12.950866 Set Vref, RX VrefLevel [Byte0]: 60
3204 00:25:12.953546 [Byte1]: 60
3205 00:25:12.957988
3206 00:25:12.958567 Set Vref, RX VrefLevel [Byte0]: 61
3207 00:25:12.961265 [Byte1]: 61
3208 00:25:12.965653
3209 00:25:12.966084 Set Vref, RX VrefLevel [Byte0]: 62
3210 00:25:12.968949 [Byte1]: 62
3211 00:25:12.974124
3212 00:25:12.974668 Set Vref, RX VrefLevel [Byte0]: 63
3213 00:25:12.977029 [Byte1]: 63
3214 00:25:12.981979
3215 00:25:12.982520 Set Vref, RX VrefLevel [Byte0]: 64
3216 00:25:12.985049 [Byte1]: 64
3217 00:25:12.989722
3218 00:25:12.990264 Set Vref, RX VrefLevel [Byte0]: 65
3219 00:25:12.993155 [Byte1]: 65
3220 00:25:12.997534
3221 00:25:12.998049 Set Vref, RX VrefLevel [Byte0]: 66
3222 00:25:13.001274 [Byte1]: 66
3223 00:25:13.005627
3224 00:25:13.006141 Final RX Vref Byte 0 = 54 to rank0
3225 00:25:13.009397 Final RX Vref Byte 1 = 49 to rank0
3226 00:25:13.012444 Final RX Vref Byte 0 = 54 to rank1
3227 00:25:13.015493 Final RX Vref Byte 1 = 49 to rank1==
3228 00:25:13.018723 Dram Type= 6, Freq= 0, CH_1, rank 0
3229 00:25:13.025384 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3230 00:25:13.025847 ==
3231 00:25:13.026194 DQS Delay:
3232 00:25:13.028523 DQS0 = 0, DQS1 = 0
3233 00:25:13.029032 DQM Delay:
3234 00:25:13.029365 DQM0 = 115, DQM1 = 105
3235 00:25:13.031887 DQ Delay:
3236 00:25:13.035276 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114
3237 00:25:13.038892 DQ4 =114, DQ5 =124, DQ6 =120, DQ7 =114
3238 00:25:13.041867 DQ8 =86, DQ9 =94, DQ10 =108, DQ11 =96
3239 00:25:13.045390 DQ12 =112, DQ13 =116, DQ14 =114, DQ15 =114
3240 00:25:13.045908
3241 00:25:13.046304
3242 00:25:13.055538 [DQSOSCAuto] RK0, (LSB)MR18= 0x1818, (MSB)MR19= 0x404, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
3243 00:25:13.056059 CH1 RK0: MR19=404, MR18=1818
3244 00:25:13.061744 CH1_RK0: MR19=0x404, MR18=0x1818, DQSOSC=400, MR23=63, INC=40, DEC=27
3245 00:25:13.062273
3246 00:25:13.065277 ----->DramcWriteLeveling(PI) begin...
3247 00:25:13.065792 ==
3248 00:25:13.068794 Dram Type= 6, Freq= 0, CH_1, rank 1
3249 00:25:13.071537 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3250 00:25:13.075128 ==
3251 00:25:13.078534 Write leveling (Byte 0): 23 => 23
3252 00:25:13.078968 Write leveling (Byte 1): 23 => 23
3253 00:25:13.081717 DramcWriteLeveling(PI) end<-----
3254 00:25:13.082146
3255 00:25:13.085210 ==
3256 00:25:13.085657 Dram Type= 6, Freq= 0, CH_1, rank 1
3257 00:25:13.091719 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3258 00:25:13.092247 ==
3259 00:25:13.094810 [Gating] SW mode calibration
3260 00:25:13.101738 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3261 00:25:13.105167 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3262 00:25:13.111632 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3263 00:25:13.114979 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3264 00:25:13.118188 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3265 00:25:13.125359 0 11 12 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
3266 00:25:13.128619 0 11 16 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (0 0)
3267 00:25:13.131443 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3268 00:25:13.138032 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3269 00:25:13.141465 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3270 00:25:13.144709 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3271 00:25:13.151450 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3272 00:25:13.154904 0 12 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3273 00:25:13.158150 0 12 12 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (1 1)
3274 00:25:13.161750 0 12 16 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
3275 00:25:13.168403 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3276 00:25:13.171200 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3277 00:25:13.174916 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3278 00:25:13.181298 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3279 00:25:13.184834 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3280 00:25:13.188073 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3281 00:25:13.194459 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3282 00:25:13.197855 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3283 00:25:13.201356 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3284 00:25:13.207819 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3285 00:25:13.210948 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3286 00:25:13.214516 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3287 00:25:13.221106 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3288 00:25:13.224261 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3289 00:25:13.227240 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3290 00:25:13.234292 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3291 00:25:13.237214 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3292 00:25:13.240586 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3293 00:25:13.247112 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3294 00:25:13.250776 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3295 00:25:13.253750 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3296 00:25:13.260393 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3297 00:25:13.263964 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3298 00:25:13.267206 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3299 00:25:13.270372 Total UI for P1: 0, mck2ui 16
3300 00:25:13.273535 best dqsien dly found for B0: ( 0, 15, 12)
3301 00:25:13.280302 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3302 00:25:13.283768 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3303 00:25:13.287356 Total UI for P1: 0, mck2ui 16
3304 00:25:13.289865 best dqsien dly found for B1: ( 0, 15, 18)
3305 00:25:13.293380 best DQS0 dly(MCK, UI, PI) = (0, 15, 12)
3306 00:25:13.296807 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
3307 00:25:13.297366
3308 00:25:13.300028 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 12)
3309 00:25:13.307048 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
3310 00:25:13.307480 [Gating] SW calibration Done
3311 00:25:13.307812 ==
3312 00:25:13.309760 Dram Type= 6, Freq= 0, CH_1, rank 1
3313 00:25:13.316631 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3314 00:25:13.316932 ==
3315 00:25:13.317166 RX Vref Scan: 0
3316 00:25:13.317378
3317 00:25:13.319867 RX Vref 0 -> 0, step: 1
3318 00:25:13.320166
3319 00:25:13.322967 RX Delay -40 -> 252, step: 8
3320 00:25:13.327000 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3321 00:25:13.329743 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3322 00:25:13.332882 iDelay=200, Bit 2, Center 107 (32 ~ 183) 152
3323 00:25:13.339763 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3324 00:25:13.342746 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3325 00:25:13.346089 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3326 00:25:13.349448 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3327 00:25:13.352764 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3328 00:25:13.359513 iDelay=200, Bit 8, Center 87 (8 ~ 167) 160
3329 00:25:13.362810 iDelay=200, Bit 9, Center 91 (16 ~ 167) 152
3330 00:25:13.366145 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
3331 00:25:13.369934 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
3332 00:25:13.372493 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3333 00:25:13.379523 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3334 00:25:13.382749 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3335 00:25:13.386029 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3336 00:25:13.386814 ==
3337 00:25:13.389471 Dram Type= 6, Freq= 0, CH_1, rank 1
3338 00:25:13.392725 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3339 00:25:13.393152 ==
3340 00:25:13.397021 DQS Delay:
3341 00:25:13.397532 DQS0 = 0, DQS1 = 0
3342 00:25:13.399604 DQM Delay:
3343 00:25:13.400120 DQM0 = 116, DQM1 = 105
3344 00:25:13.402353 DQ Delay:
3345 00:25:13.406453 DQ0 =119, DQ1 =111, DQ2 =107, DQ3 =115
3346 00:25:13.409036 DQ4 =115, DQ5 =123, DQ6 =123, DQ7 =115
3347 00:25:13.412882 DQ8 =87, DQ9 =91, DQ10 =107, DQ11 =99
3348 00:25:13.416417 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =111
3349 00:25:13.416916
3350 00:25:13.417240
3351 00:25:13.417536 ==
3352 00:25:13.419554 Dram Type= 6, Freq= 0, CH_1, rank 1
3353 00:25:13.422371 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3354 00:25:13.422875 ==
3355 00:25:13.423204
3356 00:25:13.423537
3357 00:25:13.425690 TX Vref Scan disable
3358 00:25:13.429184 == TX Byte 0 ==
3359 00:25:13.432421 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3360 00:25:13.435808 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3361 00:25:13.438919 == TX Byte 1 ==
3362 00:25:13.442305 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3363 00:25:13.446179 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3364 00:25:13.446735 ==
3365 00:25:13.448530 Dram Type= 6, Freq= 0, CH_1, rank 1
3366 00:25:13.455448 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3367 00:25:13.455956 ==
3368 00:25:13.465454 TX Vref=22, minBit 7, minWin=25, winSum=417
3369 00:25:13.469167 TX Vref=24, minBit 9, minWin=25, winSum=423
3370 00:25:13.471940 TX Vref=26, minBit 1, minWin=26, winSum=427
3371 00:25:13.475652 TX Vref=28, minBit 8, minWin=26, winSum=429
3372 00:25:13.478748 TX Vref=30, minBit 8, minWin=26, winSum=430
3373 00:25:13.482350 TX Vref=32, minBit 0, minWin=26, winSum=430
3374 00:25:13.488620 [TxChooseVref] Worse bit 8, Min win 26, Win sum 430, Final Vref 30
3375 00:25:13.489048
3376 00:25:13.492560 Final TX Range 1 Vref 30
3377 00:25:13.493191
3378 00:25:13.493528 ==
3379 00:25:13.495215 Dram Type= 6, Freq= 0, CH_1, rank 1
3380 00:25:13.498584 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3381 00:25:13.499009 ==
3382 00:25:13.499332
3383 00:25:13.502062
3384 00:25:13.502519 TX Vref Scan disable
3385 00:25:13.505656 == TX Byte 0 ==
3386 00:25:13.509048 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3387 00:25:13.512061 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3388 00:25:13.515473 == TX Byte 1 ==
3389 00:25:13.518743 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3390 00:25:13.521694 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3391 00:25:13.522113
3392 00:25:13.525490 [DATLAT]
3393 00:25:13.525986 Freq=1200, CH1 RK1
3394 00:25:13.526351
3395 00:25:13.528995 DATLAT Default: 0xc
3396 00:25:13.529424 0, 0xFFFF, sum = 0
3397 00:25:13.531700 1, 0xFFFF, sum = 0
3398 00:25:13.532126 2, 0xFFFF, sum = 0
3399 00:25:13.535786 3, 0xFFFF, sum = 0
3400 00:25:13.536296 4, 0xFFFF, sum = 0
3401 00:25:13.538585 5, 0xFFFF, sum = 0
3402 00:25:13.539119 6, 0xFFFF, sum = 0
3403 00:25:13.542108 7, 0xFFFF, sum = 0
3404 00:25:13.545673 8, 0xFFFF, sum = 0
3405 00:25:13.546102 9, 0xFFFF, sum = 0
3406 00:25:13.548902 10, 0xFFFF, sum = 0
3407 00:25:13.549329 11, 0x0, sum = 1
3408 00:25:13.552070 12, 0x0, sum = 2
3409 00:25:13.552510 13, 0x0, sum = 3
3410 00:25:13.552895 14, 0x0, sum = 4
3411 00:25:13.554915 best_step = 12
3412 00:25:13.555337
3413 00:25:13.555656 ==
3414 00:25:13.558663 Dram Type= 6, Freq= 0, CH_1, rank 1
3415 00:25:13.561656 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3416 00:25:13.562153 ==
3417 00:25:13.564697 RX Vref Scan: 0
3418 00:25:13.565158
3419 00:25:13.567988 RX Vref 0 -> 0, step: 1
3420 00:25:13.568409
3421 00:25:13.568735 RX Delay -37 -> 252, step: 4
3422 00:25:13.575540 iDelay=199, Bit 0, Center 114 (43 ~ 186) 144
3423 00:25:13.578720 iDelay=199, Bit 1, Center 108 (39 ~ 178) 140
3424 00:25:13.582322 iDelay=199, Bit 2, Center 108 (39 ~ 178) 140
3425 00:25:13.585515 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140
3426 00:25:13.588892 iDelay=199, Bit 4, Center 114 (43 ~ 186) 144
3427 00:25:13.595527 iDelay=199, Bit 5, Center 124 (51 ~ 198) 148
3428 00:25:13.598706 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
3429 00:25:13.601963 iDelay=199, Bit 7, Center 112 (43 ~ 182) 140
3430 00:25:13.605473 iDelay=199, Bit 8, Center 86 (19 ~ 154) 136
3431 00:25:13.609266 iDelay=199, Bit 9, Center 90 (23 ~ 158) 136
3432 00:25:13.615100 iDelay=199, Bit 10, Center 106 (39 ~ 174) 136
3433 00:25:13.618524 iDelay=199, Bit 11, Center 98 (31 ~ 166) 136
3434 00:25:13.621983 iDelay=199, Bit 12, Center 112 (43 ~ 182) 140
3435 00:25:13.625219 iDelay=199, Bit 13, Center 110 (43 ~ 178) 136
3436 00:25:13.629040 iDelay=199, Bit 14, Center 112 (43 ~ 182) 140
3437 00:25:13.635398 iDelay=199, Bit 15, Center 110 (43 ~ 178) 136
3438 00:25:13.635890 ==
3439 00:25:13.638251 Dram Type= 6, Freq= 0, CH_1, rank 1
3440 00:25:13.641988 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3441 00:25:13.642580 ==
3442 00:25:13.643060 DQS Delay:
3443 00:25:13.645198 DQS0 = 0, DQS1 = 0
3444 00:25:13.645630 DQM Delay:
3445 00:25:13.649068 DQM0 = 114, DQM1 = 103
3446 00:25:13.649515 DQ Delay:
3447 00:25:13.651745 DQ0 =114, DQ1 =108, DQ2 =108, DQ3 =112
3448 00:25:13.654862 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =112
3449 00:25:13.658305 DQ8 =86, DQ9 =90, DQ10 =106, DQ11 =98
3450 00:25:13.662184 DQ12 =112, DQ13 =110, DQ14 =112, DQ15 =110
3451 00:25:13.662671
3452 00:25:13.665071
3453 00:25:13.672138 [DQSOSCAuto] RK1, (LSB)MR18= 0xc0c, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
3454 00:25:13.674906 CH1 RK1: MR19=404, MR18=C0C
3455 00:25:13.681591 CH1_RK1: MR19=0x404, MR18=0xC0C, DQSOSC=405, MR23=63, INC=39, DEC=26
3456 00:25:13.682029 [RxdqsGatingPostProcess] freq 1200
3457 00:25:13.688303 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3458 00:25:13.691647 Pre-setting of DQS Precalculation
3459 00:25:13.695022 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3460 00:25:13.704973 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3461 00:25:13.711756 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3462 00:25:13.712253
3463 00:25:13.712590
3464 00:25:13.715418 [Calibration Summary] 2400 Mbps
3465 00:25:13.715953 CH 0, Rank 0
3466 00:25:13.718075 SW Impedance : PASS
3467 00:25:13.718545 DUTY Scan : NO K
3468 00:25:13.721407 ZQ Calibration : PASS
3469 00:25:13.724635 Jitter Meter : NO K
3470 00:25:13.725067 CBT Training : PASS
3471 00:25:13.727994 Write leveling : PASS
3472 00:25:13.731540 RX DQS gating : PASS
3473 00:25:13.732052 RX DQ/DQS(RDDQC) : PASS
3474 00:25:13.735040 TX DQ/DQS : PASS
3475 00:25:13.737887 RX DATLAT : PASS
3476 00:25:13.738356 RX DQ/DQS(Engine): PASS
3477 00:25:13.741490 TX OE : NO K
3478 00:25:13.741929 All Pass.
3479 00:25:13.742315
3480 00:25:13.745346 CH 0, Rank 1
3481 00:25:13.745777 SW Impedance : PASS
3482 00:25:13.748232 DUTY Scan : NO K
3483 00:25:13.751209 ZQ Calibration : PASS
3484 00:25:13.751642 Jitter Meter : NO K
3485 00:25:13.754765 CBT Training : PASS
3486 00:25:13.757950 Write leveling : PASS
3487 00:25:13.758428 RX DQS gating : PASS
3488 00:25:13.761451 RX DQ/DQS(RDDQC) : PASS
3489 00:25:13.764503 TX DQ/DQS : PASS
3490 00:25:13.764937 RX DATLAT : PASS
3491 00:25:13.767696 RX DQ/DQS(Engine): PASS
3492 00:25:13.768142 TX OE : NO K
3493 00:25:13.770995 All Pass.
3494 00:25:13.771426
3495 00:25:13.771759 CH 1, Rank 0
3496 00:25:13.774776 SW Impedance : PASS
3497 00:25:13.775209 DUTY Scan : NO K
3498 00:25:13.778157 ZQ Calibration : PASS
3499 00:25:13.781417 Jitter Meter : NO K
3500 00:25:13.781915 CBT Training : PASS
3501 00:25:13.785549 Write leveling : PASS
3502 00:25:13.788089 RX DQS gating : PASS
3503 00:25:13.788651 RX DQ/DQS(RDDQC) : PASS
3504 00:25:13.791021 TX DQ/DQS : PASS
3505 00:25:13.794703 RX DATLAT : PASS
3506 00:25:13.795206 RX DQ/DQS(Engine): PASS
3507 00:25:13.798251 TX OE : NO K
3508 00:25:13.798769 All Pass.
3509 00:25:13.799116
3510 00:25:13.801642 CH 1, Rank 1
3511 00:25:13.802084 SW Impedance : PASS
3512 00:25:13.805048 DUTY Scan : NO K
3513 00:25:13.807516 ZQ Calibration : PASS
3514 00:25:13.807949 Jitter Meter : NO K
3515 00:25:13.811031 CBT Training : PASS
3516 00:25:13.814537 Write leveling : PASS
3517 00:25:13.815037 RX DQS gating : PASS
3518 00:25:13.817489 RX DQ/DQS(RDDQC) : PASS
3519 00:25:13.820842 TX DQ/DQS : PASS
3520 00:25:13.821276 RX DATLAT : PASS
3521 00:25:13.824650 RX DQ/DQS(Engine): PASS
3522 00:25:13.827685 TX OE : NO K
3523 00:25:13.828187 All Pass.
3524 00:25:13.828549
3525 00:25:13.828861 DramC Write-DBI off
3526 00:25:13.830732 PER_BANK_REFRESH: Hybrid Mode
3527 00:25:13.834282 TX_TRACKING: ON
3528 00:25:13.840814 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3529 00:25:13.843846 [FAST_K] Save calibration result to emmc
3530 00:25:13.850998 dramc_set_vcore_voltage set vcore to 650000
3531 00:25:13.851475 Read voltage for 600, 5
3532 00:25:13.853904 Vio18 = 0
3533 00:25:13.854502 Vcore = 650000
3534 00:25:13.854986 Vdram = 0
3535 00:25:13.855445 Vddq = 0
3536 00:25:13.857602 Vmddr = 0
3537 00:25:13.860754 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3538 00:25:13.867186 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3539 00:25:13.870568 MEM_TYPE=3, freq_sel=19
3540 00:25:13.871152 sv_algorithm_assistance_LP4_1600
3541 00:25:13.876886 ============ PULL DRAM RESETB DOWN ============
3542 00:25:13.880492 ========== PULL DRAM RESETB DOWN end =========
3543 00:25:13.883350 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3544 00:25:13.886910 ===================================
3545 00:25:13.889830 LPDDR4 DRAM CONFIGURATION
3546 00:25:13.893359 ===================================
3547 00:25:13.897545 EX_ROW_EN[0] = 0x0
3548 00:25:13.897736 EX_ROW_EN[1] = 0x0
3549 00:25:13.900381 LP4Y_EN = 0x0
3550 00:25:13.900571 WORK_FSP = 0x0
3551 00:25:13.903438 WL = 0x2
3552 00:25:13.903571 RL = 0x2
3553 00:25:13.906449 BL = 0x2
3554 00:25:13.906557 RPST = 0x0
3555 00:25:13.909958 RD_PRE = 0x0
3556 00:25:13.910130 WR_PRE = 0x1
3557 00:25:13.913355 WR_PST = 0x0
3558 00:25:13.916987 DBI_WR = 0x0
3559 00:25:13.917158 DBI_RD = 0x0
3560 00:25:13.919920 OTF = 0x1
3561 00:25:13.923085 ===================================
3562 00:25:13.926815 ===================================
3563 00:25:13.927009 ANA top config
3564 00:25:13.929642 ===================================
3565 00:25:13.933279 DLL_ASYNC_EN = 0
3566 00:25:13.936557 ALL_SLAVE_EN = 1
3567 00:25:13.936780 NEW_RANK_MODE = 1
3568 00:25:13.939646 DLL_IDLE_MODE = 1
3569 00:25:13.943090 LP45_APHY_COMB_EN = 1
3570 00:25:13.946250 TX_ODT_DIS = 1
3571 00:25:13.946518 NEW_8X_MODE = 1
3572 00:25:13.949244 ===================================
3573 00:25:13.952674 ===================================
3574 00:25:13.956275 data_rate = 1200
3575 00:25:13.959697 CKR = 1
3576 00:25:13.962925 DQ_P2S_RATIO = 8
3577 00:25:13.966580 ===================================
3578 00:25:13.969662 CA_P2S_RATIO = 8
3579 00:25:13.972855 DQ_CA_OPEN = 0
3580 00:25:13.976942 DQ_SEMI_OPEN = 0
3581 00:25:13.977396 CA_SEMI_OPEN = 0
3582 00:25:13.979126 CA_FULL_RATE = 0
3583 00:25:13.983021 DQ_CKDIV4_EN = 1
3584 00:25:13.986393 CA_CKDIV4_EN = 1
3585 00:25:13.989868 CA_PREDIV_EN = 0
3586 00:25:13.992840 PH8_DLY = 0
3587 00:25:13.993342 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3588 00:25:13.996264 DQ_AAMCK_DIV = 4
3589 00:25:13.999334 CA_AAMCK_DIV = 4
3590 00:25:14.002662 CA_ADMCK_DIV = 4
3591 00:25:14.006120 DQ_TRACK_CA_EN = 0
3592 00:25:14.009497 CA_PICK = 600
3593 00:25:14.010022 CA_MCKIO = 600
3594 00:25:14.012635 MCKIO_SEMI = 0
3595 00:25:14.016006 PLL_FREQ = 2288
3596 00:25:14.019500 DQ_UI_PI_RATIO = 32
3597 00:25:14.022539 CA_UI_PI_RATIO = 0
3598 00:25:14.026277 ===================================
3599 00:25:14.029445 ===================================
3600 00:25:14.032683 memory_type:LPDDR4
3601 00:25:14.033186 GP_NUM : 10
3602 00:25:14.035701 SRAM_EN : 1
3603 00:25:14.036216 MD32_EN : 0
3604 00:25:14.039022 ===================================
3605 00:25:14.042283 [ANA_INIT] >>>>>>>>>>>>>>
3606 00:25:14.045582 <<<<<< [CONFIGURE PHASE]: ANA_TX
3607 00:25:14.048790 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3608 00:25:14.052157 ===================================
3609 00:25:14.055520 data_rate = 1200,PCW = 0X5800
3610 00:25:14.058598 ===================================
3611 00:25:14.062473 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3612 00:25:14.068593 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3613 00:25:14.072199 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3614 00:25:14.078723 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3615 00:25:14.082133 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3616 00:25:14.085364 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3617 00:25:14.085876 [ANA_INIT] flow start
3618 00:25:14.088419 [ANA_INIT] PLL >>>>>>>>
3619 00:25:14.091771 [ANA_INIT] PLL <<<<<<<<
3620 00:25:14.092199 [ANA_INIT] MIDPI >>>>>>>>
3621 00:25:14.095486 [ANA_INIT] MIDPI <<<<<<<<
3622 00:25:14.098685 [ANA_INIT] DLL >>>>>>>>
3623 00:25:14.099109 [ANA_INIT] flow end
3624 00:25:14.105228 ============ LP4 DIFF to SE enter ============
3625 00:25:14.108608 ============ LP4 DIFF to SE exit ============
3626 00:25:14.111966 [ANA_INIT] <<<<<<<<<<<<<
3627 00:25:14.114913 [Flow] Enable top DCM control >>>>>
3628 00:25:14.118237 [Flow] Enable top DCM control <<<<<
3629 00:25:14.121660 Enable DLL master slave shuffle
3630 00:25:14.125312 ==============================================================
3631 00:25:14.128805 Gating Mode config
3632 00:25:14.131734 ==============================================================
3633 00:25:14.135491 Config description:
3634 00:25:14.145159 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3635 00:25:14.151221 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3636 00:25:14.154712 SELPH_MODE 0: By rank 1: By Phase
3637 00:25:14.161267 ==============================================================
3638 00:25:14.165111 GAT_TRACK_EN = 1
3639 00:25:14.167815 RX_GATING_MODE = 2
3640 00:25:14.170987 RX_GATING_TRACK_MODE = 2
3641 00:25:14.174771 SELPH_MODE = 1
3642 00:25:14.177846 PICG_EARLY_EN = 1
3643 00:25:14.178299 VALID_LAT_VALUE = 1
3644 00:25:14.184648 ==============================================================
3645 00:25:14.188151 Enter into Gating configuration >>>>
3646 00:25:14.191158 Exit from Gating configuration <<<<
3647 00:25:14.194591 Enter into DVFS_PRE_config >>>>>
3648 00:25:14.204159 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3649 00:25:14.208284 Exit from DVFS_PRE_config <<<<<
3650 00:25:14.211492 Enter into PICG configuration >>>>
3651 00:25:14.214834 Exit from PICG configuration <<<<
3652 00:25:14.218433 [RX_INPUT] configuration >>>>>
3653 00:25:14.221151 [RX_INPUT] configuration <<<<<
3654 00:25:14.224542 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3655 00:25:14.231337 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3656 00:25:14.238067 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3657 00:25:14.244297 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3658 00:25:14.250784 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3659 00:25:14.254125 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3660 00:25:14.260915 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3661 00:25:14.263966 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3662 00:25:14.267669 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3663 00:25:14.270558 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3664 00:25:14.277971 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3665 00:25:14.280390 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3666 00:25:14.284062 ===================================
3667 00:25:14.287728 LPDDR4 DRAM CONFIGURATION
3668 00:25:14.290856 ===================================
3669 00:25:14.290935 EX_ROW_EN[0] = 0x0
3670 00:25:14.293984 EX_ROW_EN[1] = 0x0
3671 00:25:14.294063 LP4Y_EN = 0x0
3672 00:25:14.297388 WORK_FSP = 0x0
3673 00:25:14.297540 WL = 0x2
3674 00:25:14.300956 RL = 0x2
3675 00:25:14.301095 BL = 0x2
3676 00:25:14.303903 RPST = 0x0
3677 00:25:14.307220 RD_PRE = 0x0
3678 00:25:14.307337 WR_PRE = 0x1
3679 00:25:14.310510 WR_PST = 0x0
3680 00:25:14.310652 DBI_WR = 0x0
3681 00:25:14.314178 DBI_RD = 0x0
3682 00:25:14.314356 OTF = 0x1
3683 00:25:14.317336 ===================================
3684 00:25:14.320632 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3685 00:25:14.327537 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3686 00:25:14.330452 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3687 00:25:14.334098 ===================================
3688 00:25:14.337772 LPDDR4 DRAM CONFIGURATION
3689 00:25:14.340794 ===================================
3690 00:25:14.341041 EX_ROW_EN[0] = 0x10
3691 00:25:14.343810 EX_ROW_EN[1] = 0x0
3692 00:25:14.343988 LP4Y_EN = 0x0
3693 00:25:14.347293 WORK_FSP = 0x0
3694 00:25:14.347497 WL = 0x2
3695 00:25:14.350668 RL = 0x2
3696 00:25:14.350919 BL = 0x2
3697 00:25:14.353766 RPST = 0x0
3698 00:25:14.354033 RD_PRE = 0x0
3699 00:25:14.357800 WR_PRE = 0x1
3700 00:25:14.358256 WR_PST = 0x0
3701 00:25:14.361515 DBI_WR = 0x0
3702 00:25:14.362038 DBI_RD = 0x0
3703 00:25:14.364249 OTF = 0x1
3704 00:25:14.367823 ===================================
3705 00:25:14.374474 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3706 00:25:14.377478 nWR fixed to 30
3707 00:25:14.380887 [ModeRegInit_LP4] CH0 RK0
3708 00:25:14.381406 [ModeRegInit_LP4] CH0 RK1
3709 00:25:14.384185 [ModeRegInit_LP4] CH1 RK0
3710 00:25:14.387105 [ModeRegInit_LP4] CH1 RK1
3711 00:25:14.387548 match AC timing 16
3712 00:25:14.393758 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3713 00:25:14.397944 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3714 00:25:14.401175 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3715 00:25:14.407350 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3716 00:25:14.410728 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3717 00:25:14.411173 ==
3718 00:25:14.413794 Dram Type= 6, Freq= 0, CH_0, rank 0
3719 00:25:14.417496 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3720 00:25:14.418024 ==
3721 00:25:14.423992 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3722 00:25:14.430685 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3723 00:25:14.434456 [CA 0] Center 35 (5~66) winsize 62
3724 00:25:14.437360 [CA 1] Center 35 (5~66) winsize 62
3725 00:25:14.440825 [CA 2] Center 34 (4~65) winsize 62
3726 00:25:14.443995 [CA 3] Center 34 (4~65) winsize 62
3727 00:25:14.447008 [CA 4] Center 33 (3~64) winsize 62
3728 00:25:14.450292 [CA 5] Center 33 (3~64) winsize 62
3729 00:25:14.450821
3730 00:25:14.453493 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3731 00:25:14.453950
3732 00:25:14.456887 [CATrainingPosCal] consider 1 rank data
3733 00:25:14.460518 u2DelayCellTimex100 = 270/100 ps
3734 00:25:14.463701 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3735 00:25:14.466823 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3736 00:25:14.470037 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3737 00:25:14.473612 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3738 00:25:14.476868 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3739 00:25:14.483812 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3740 00:25:14.484390
3741 00:25:14.486601 CA PerBit enable=1, Macro0, CA PI delay=33
3742 00:25:14.487112
3743 00:25:14.490110 [CBTSetCACLKResult] CA Dly = 33
3744 00:25:14.490688 CS Dly: 5 (0~36)
3745 00:25:14.491124 ==
3746 00:25:14.493064 Dram Type= 6, Freq= 0, CH_0, rank 1
3747 00:25:14.496833 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3748 00:25:14.500173 ==
3749 00:25:14.503096 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3750 00:25:14.510154 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
3751 00:25:14.513837 [CA 0] Center 35 (5~66) winsize 62
3752 00:25:14.517066 [CA 1] Center 35 (5~66) winsize 62
3753 00:25:14.520065 [CA 2] Center 34 (4~65) winsize 62
3754 00:25:14.523049 [CA 3] Center 34 (4~65) winsize 62
3755 00:25:14.526874 [CA 4] Center 33 (3~64) winsize 62
3756 00:25:14.530295 [CA 5] Center 33 (3~64) winsize 62
3757 00:25:14.530863
3758 00:25:14.533328 [CmdBusTrainingLP45] Vref(ca) range 1: 39
3759 00:25:14.533853
3760 00:25:14.536440 [CATrainingPosCal] consider 2 rank data
3761 00:25:14.539677 u2DelayCellTimex100 = 270/100 ps
3762 00:25:14.543069 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3763 00:25:14.546951 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3764 00:25:14.550138 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3765 00:25:14.556294 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3766 00:25:14.559784 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3767 00:25:14.563508 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3768 00:25:14.564030
3769 00:25:14.566582 CA PerBit enable=1, Macro0, CA PI delay=33
3770 00:25:14.567127
3771 00:25:14.569627 [CBTSetCACLKResult] CA Dly = 33
3772 00:25:14.570077 CS Dly: 5 (0~37)
3773 00:25:14.570465
3774 00:25:14.573559 ----->DramcWriteLeveling(PI) begin...
3775 00:25:14.574073 ==
3776 00:25:14.576198 Dram Type= 6, Freq= 0, CH_0, rank 0
3777 00:25:14.583022 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3778 00:25:14.583538 ==
3779 00:25:14.586122 Write leveling (Byte 0): 31 => 31
3780 00:25:14.589312 Write leveling (Byte 1): 31 => 31
3781 00:25:14.589762 DramcWriteLeveling(PI) end<-----
3782 00:25:14.592455
3783 00:25:14.593122 ==
3784 00:25:14.596201 Dram Type= 6, Freq= 0, CH_0, rank 0
3785 00:25:14.599216 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3786 00:25:14.599655 ==
3787 00:25:14.602599 [Gating] SW mode calibration
3788 00:25:14.609598 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3789 00:25:14.612798 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3790 00:25:14.619653 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3791 00:25:14.622679 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3792 00:25:14.626369 0 5 8 | B1->B0 | 3333 3131 | 0 0 | (1 0) (0 0)
3793 00:25:14.632411 0 5 12 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
3794 00:25:14.636033 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3795 00:25:14.639294 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3796 00:25:14.646055 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3797 00:25:14.649258 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3798 00:25:14.652311 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3799 00:25:14.659708 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3800 00:25:14.662663 0 6 8 | B1->B0 | 2d2d 2f2f | 0 0 | (0 0) (0 0)
3801 00:25:14.665935 0 6 12 | B1->B0 | 4343 4444 | 0 0 | (0 0) (0 0)
3802 00:25:14.672092 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3803 00:25:14.675455 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3804 00:25:14.678696 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3805 00:25:14.685940 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3806 00:25:14.689735 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3807 00:25:14.692478 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3808 00:25:14.698783 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3809 00:25:14.702629 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3810 00:25:14.705590 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3811 00:25:14.712037 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3812 00:25:14.715641 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3813 00:25:14.718968 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3814 00:25:14.725225 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3815 00:25:14.728709 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3816 00:25:14.731603 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3817 00:25:14.738937 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3818 00:25:14.742089 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3819 00:25:14.745494 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3820 00:25:14.751631 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3821 00:25:14.755188 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3822 00:25:14.758268 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3823 00:25:14.765222 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3824 00:25:14.768473 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3825 00:25:14.772153 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3826 00:25:14.774969 Total UI for P1: 0, mck2ui 16
3827 00:25:14.778155 best dqsien dly found for B0: ( 0, 9, 10)
3828 00:25:14.781810 Total UI for P1: 0, mck2ui 16
3829 00:25:14.785022 best dqsien dly found for B1: ( 0, 9, 8)
3830 00:25:14.788058 best DQS0 dly(MCK, UI, PI) = (0, 9, 10)
3831 00:25:14.791544 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
3832 00:25:14.792059
3833 00:25:14.794950 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 10)
3834 00:25:14.801630 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
3835 00:25:14.802064 [Gating] SW calibration Done
3836 00:25:14.802452 ==
3837 00:25:14.804550 Dram Type= 6, Freq= 0, CH_0, rank 0
3838 00:25:14.811177 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3839 00:25:14.811688 ==
3840 00:25:14.812038 RX Vref Scan: 0
3841 00:25:14.812348
3842 00:25:14.814590 RX Vref 0 -> 0, step: 1
3843 00:25:14.815020
3844 00:25:14.817810 RX Delay -230 -> 252, step: 16
3845 00:25:14.821165 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
3846 00:25:14.824493 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
3847 00:25:14.830992 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
3848 00:25:14.834411 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
3849 00:25:14.837973 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
3850 00:25:14.841099 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
3851 00:25:14.844710 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3852 00:25:14.850745 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
3853 00:25:14.854415 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3854 00:25:14.858298 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3855 00:25:14.861263 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
3856 00:25:14.867545 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3857 00:25:14.870843 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3858 00:25:14.874113 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3859 00:25:14.877135 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3860 00:25:14.883980 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3861 00:25:14.884479 ==
3862 00:25:14.887079 Dram Type= 6, Freq= 0, CH_0, rank 0
3863 00:25:14.891028 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3864 00:25:14.891542 ==
3865 00:25:14.892089 DQS Delay:
3866 00:25:14.893786 DQS0 = 0, DQS1 = 0
3867 00:25:14.894278 DQM Delay:
3868 00:25:14.897124 DQM0 = 41, DQM1 = 33
3869 00:25:14.897556 DQ Delay:
3870 00:25:14.900891 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =33
3871 00:25:14.904227 DQ4 =49, DQ5 =25, DQ6 =49, DQ7 =49
3872 00:25:14.907282 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
3873 00:25:14.911026 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3874 00:25:14.911598
3875 00:25:14.911943
3876 00:25:14.912248 ==
3877 00:25:14.913724 Dram Type= 6, Freq= 0, CH_0, rank 0
3878 00:25:14.917331 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3879 00:25:14.917852 ==
3880 00:25:14.920555
3881 00:25:14.921065
3882 00:25:14.921401 TX Vref Scan disable
3883 00:25:14.924074 == TX Byte 0 ==
3884 00:25:14.927066 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
3885 00:25:14.930559 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
3886 00:25:14.933843 == TX Byte 1 ==
3887 00:25:14.937031 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
3888 00:25:14.940600 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
3889 00:25:14.941125 ==
3890 00:25:14.943879 Dram Type= 6, Freq= 0, CH_0, rank 0
3891 00:25:14.950289 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3892 00:25:14.950983 ==
3893 00:25:14.951396
3894 00:25:14.951765
3895 00:25:14.952364 TX Vref Scan disable
3896 00:25:14.954767 == TX Byte 0 ==
3897 00:25:14.958074 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
3898 00:25:14.965297 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
3899 00:25:14.965822 == TX Byte 1 ==
3900 00:25:14.968782 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
3901 00:25:14.974553 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
3902 00:25:14.974984
3903 00:25:14.975313 [DATLAT]
3904 00:25:14.975621 Freq=600, CH0 RK0
3905 00:25:14.975912
3906 00:25:14.978101 DATLAT Default: 0x9
3907 00:25:14.978587 0, 0xFFFF, sum = 0
3908 00:25:14.981589 1, 0xFFFF, sum = 0
3909 00:25:14.984942 2, 0xFFFF, sum = 0
3910 00:25:14.985466 3, 0xFFFF, sum = 0
3911 00:25:14.987819 4, 0xFFFF, sum = 0
3912 00:25:14.988257 5, 0xFFFF, sum = 0
3913 00:25:14.991556 6, 0xFFFF, sum = 0
3914 00:25:14.992078 7, 0x0, sum = 1
3915 00:25:14.992421 8, 0x0, sum = 2
3916 00:25:14.994780 9, 0x0, sum = 3
3917 00:25:14.995430 10, 0x0, sum = 4
3918 00:25:14.998185 best_step = 8
3919 00:25:14.998731
3920 00:25:14.999063 ==
3921 00:25:15.001315 Dram Type= 6, Freq= 0, CH_0, rank 0
3922 00:25:15.004750 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3923 00:25:15.005267 ==
3924 00:25:15.007706 RX Vref Scan: 1
3925 00:25:15.008135
3926 00:25:15.008465 RX Vref 0 -> 0, step: 1
3927 00:25:15.008773
3928 00:25:15.011387 RX Delay -195 -> 252, step: 8
3929 00:25:15.011861
3930 00:25:15.014682 Set Vref, RX VrefLevel [Byte0]: 46
3931 00:25:15.017625 [Byte1]: 49
3932 00:25:15.021669
3933 00:25:15.022099 Final RX Vref Byte 0 = 46 to rank0
3934 00:25:15.025127 Final RX Vref Byte 1 = 49 to rank0
3935 00:25:15.028350 Final RX Vref Byte 0 = 46 to rank1
3936 00:25:15.032352 Final RX Vref Byte 1 = 49 to rank1==
3937 00:25:15.035474 Dram Type= 6, Freq= 0, CH_0, rank 0
3938 00:25:15.042151 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3939 00:25:15.042711 ==
3940 00:25:15.043053 DQS Delay:
3941 00:25:15.043367 DQS0 = 0, DQS1 = 0
3942 00:25:15.045160 DQM Delay:
3943 00:25:15.045593 DQM0 = 40, DQM1 = 30
3944 00:25:15.048576 DQ Delay:
3945 00:25:15.052073 DQ0 =36, DQ1 =40, DQ2 =36, DQ3 =36
3946 00:25:15.055384 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
3947 00:25:15.058112 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =24
3948 00:25:15.061993 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =40
3949 00:25:15.062520
3950 00:25:15.062861
3951 00:25:15.068470 [DQSOSCAuto] RK0, (LSB)MR18= 0x5454, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
3952 00:25:15.071394 CH0 RK0: MR19=808, MR18=5454
3953 00:25:15.078367 CH0_RK0: MR19=0x808, MR18=0x5454, DQSOSC=393, MR23=63, INC=169, DEC=113
3954 00:25:15.078887
3955 00:25:15.081511 ----->DramcWriteLeveling(PI) begin...
3956 00:25:15.082034 ==
3957 00:25:15.084984 Dram Type= 6, Freq= 0, CH_0, rank 1
3958 00:25:15.088307 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3959 00:25:15.088755 ==
3960 00:25:15.091240 Write leveling (Byte 0): 29 => 29
3961 00:25:15.095148 Write leveling (Byte 1): 28 => 28
3962 00:25:15.097937 DramcWriteLeveling(PI) end<-----
3963 00:25:15.098437
3964 00:25:15.098773 ==
3965 00:25:15.101352 Dram Type= 6, Freq= 0, CH_0, rank 1
3966 00:25:15.104561 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3967 00:25:15.104992 ==
3968 00:25:15.108358 [Gating] SW mode calibration
3969 00:25:15.115038 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3970 00:25:15.121475 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3971 00:25:15.124891 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3972 00:25:15.131232 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3973 00:25:15.134624 0 5 8 | B1->B0 | 3131 3333 | 1 1 | (1 0) (1 0)
3974 00:25:15.137855 0 5 12 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
3975 00:25:15.144679 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3976 00:25:15.148099 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3977 00:25:15.151227 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3978 00:25:15.157489 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3979 00:25:15.161200 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3980 00:25:15.164772 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3981 00:25:15.170902 0 6 8 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
3982 00:25:15.174548 0 6 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
3983 00:25:15.177809 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3984 00:25:15.184146 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3985 00:25:15.187392 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3986 00:25:15.190962 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3987 00:25:15.193941 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3988 00:25:15.200820 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3989 00:25:15.204522 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3990 00:25:15.207667 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3991 00:25:15.214332 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3992 00:25:15.217295 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3993 00:25:15.220777 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3994 00:25:15.227482 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 00:25:15.231087 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 00:25:15.234341 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 00:25:15.241002 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 00:25:15.244001 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 00:25:15.248110 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 00:25:15.253985 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 00:25:15.257452 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 00:25:15.260463 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 00:25:15.266974 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 00:25:15.270492 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 00:25:15.273696 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4006 00:25:15.280523 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4007 00:25:15.281016 Total UI for P1: 0, mck2ui 16
4008 00:25:15.287634 best dqsien dly found for B0: ( 0, 9, 8)
4009 00:25:15.288143 Total UI for P1: 0, mck2ui 16
4010 00:25:15.293799 best dqsien dly found for B1: ( 0, 9, 10)
4011 00:25:15.297200 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
4012 00:25:15.300635 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
4013 00:25:15.301141
4014 00:25:15.303401 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
4015 00:25:15.306857 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
4016 00:25:15.309951 [Gating] SW calibration Done
4017 00:25:15.310417 ==
4018 00:25:15.313498 Dram Type= 6, Freq= 0, CH_0, rank 1
4019 00:25:15.316675 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4020 00:25:15.317103 ==
4021 00:25:15.320034 RX Vref Scan: 0
4022 00:25:15.320454
4023 00:25:15.320779 RX Vref 0 -> 0, step: 1
4024 00:25:15.321083
4025 00:25:15.323736 RX Delay -230 -> 252, step: 16
4026 00:25:15.326808 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4027 00:25:15.333426 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4028 00:25:15.336964 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4029 00:25:15.340337 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4030 00:25:15.343623 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4031 00:25:15.350360 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4032 00:25:15.353837 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4033 00:25:15.356648 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4034 00:25:15.360697 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4035 00:25:15.363252 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4036 00:25:15.370136 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4037 00:25:15.373571 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4038 00:25:15.376921 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4039 00:25:15.380241 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4040 00:25:15.386555 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4041 00:25:15.389674 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4042 00:25:15.390182 ==
4043 00:25:15.393370 Dram Type= 6, Freq= 0, CH_0, rank 1
4044 00:25:15.396300 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4045 00:25:15.396736 ==
4046 00:25:15.399848 DQS Delay:
4047 00:25:15.400402 DQS0 = 0, DQS1 = 0
4048 00:25:15.402930 DQM Delay:
4049 00:25:15.403371 DQM0 = 43, DQM1 = 33
4050 00:25:15.403695 DQ Delay:
4051 00:25:15.406828 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =33
4052 00:25:15.409995 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4053 00:25:15.413126 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4054 00:25:15.416760 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4055 00:25:15.417268
4056 00:25:15.417594
4057 00:25:15.419485 ==
4058 00:25:15.422975 Dram Type= 6, Freq= 0, CH_0, rank 1
4059 00:25:15.426023 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4060 00:25:15.426601 ==
4061 00:25:15.426940
4062 00:25:15.427246
4063 00:25:15.429309 TX Vref Scan disable
4064 00:25:15.429813 == TX Byte 0 ==
4065 00:25:15.436301 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4066 00:25:15.439459 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4067 00:25:15.439965 == TX Byte 1 ==
4068 00:25:15.446440 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4069 00:25:15.449511 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4070 00:25:15.450019 ==
4071 00:25:15.453188 Dram Type= 6, Freq= 0, CH_0, rank 1
4072 00:25:15.455925 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4073 00:25:15.456355 ==
4074 00:25:15.456687
4075 00:25:15.456991
4076 00:25:15.458921 TX Vref Scan disable
4077 00:25:15.462387 == TX Byte 0 ==
4078 00:25:15.466319 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4079 00:25:15.469136 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4080 00:25:15.472762 == TX Byte 1 ==
4081 00:25:15.475929 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4082 00:25:15.479213 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4083 00:25:15.479644
4084 00:25:15.482825 [DATLAT]
4085 00:25:15.483333 Freq=600, CH0 RK1
4086 00:25:15.483669
4087 00:25:15.485799 DATLAT Default: 0x8
4088 00:25:15.486340 0, 0xFFFF, sum = 0
4089 00:25:15.489359 1, 0xFFFF, sum = 0
4090 00:25:15.489831 2, 0xFFFF, sum = 0
4091 00:25:15.492497 3, 0xFFFF, sum = 0
4092 00:25:15.493009 4, 0xFFFF, sum = 0
4093 00:25:15.495913 5, 0xFFFF, sum = 0
4094 00:25:15.496436 6, 0xFFFF, sum = 0
4095 00:25:15.498883 7, 0x0, sum = 1
4096 00:25:15.499313 8, 0x0, sum = 2
4097 00:25:15.502043 9, 0x0, sum = 3
4098 00:25:15.502523 10, 0x0, sum = 4
4099 00:25:15.505604 best_step = 8
4100 00:25:15.506110
4101 00:25:15.506512 ==
4102 00:25:15.508685 Dram Type= 6, Freq= 0, CH_0, rank 1
4103 00:25:15.512293 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4104 00:25:15.512722 ==
4105 00:25:15.515596 RX Vref Scan: 0
4106 00:25:15.516106
4107 00:25:15.516529 RX Vref 0 -> 0, step: 1
4108 00:25:15.516849
4109 00:25:15.518524 RX Delay -195 -> 252, step: 8
4110 00:25:15.525111 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4111 00:25:15.528767 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4112 00:25:15.532328 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4113 00:25:15.535824 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4114 00:25:15.542350 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4115 00:25:15.545421 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4116 00:25:15.548606 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4117 00:25:15.551847 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4118 00:25:15.558502 iDelay=205, Bit 8, Center 20 (-131 ~ 172) 304
4119 00:25:15.561475 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4120 00:25:15.564992 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4121 00:25:15.568283 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4122 00:25:15.574953 iDelay=205, Bit 12, Center 36 (-115 ~ 188) 304
4123 00:25:15.578507 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4124 00:25:15.581673 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4125 00:25:15.585572 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4126 00:25:15.586081 ==
4127 00:25:15.588699 Dram Type= 6, Freq= 0, CH_0, rank 1
4128 00:25:15.594972 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4129 00:25:15.595484 ==
4130 00:25:15.595817 DQS Delay:
4131 00:25:15.598488 DQS0 = 0, DQS1 = 0
4132 00:25:15.599177 DQM Delay:
4133 00:25:15.599521 DQM0 = 41, DQM1 = 32
4134 00:25:15.601107 DQ Delay:
4135 00:25:15.604379 DQ0 =36, DQ1 =40, DQ2 =40, DQ3 =36
4136 00:25:15.608233 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4137 00:25:15.611029 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =24
4138 00:25:15.615003 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =44
4139 00:25:15.615511
4140 00:25:15.615840
4141 00:25:15.621175 [DQSOSCAuto] RK1, (LSB)MR18= 0x6c6c, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
4142 00:25:15.624759 CH0 RK1: MR19=808, MR18=6C6C
4143 00:25:15.631842 CH0_RK1: MR19=0x808, MR18=0x6C6C, DQSOSC=389, MR23=63, INC=173, DEC=115
4144 00:25:15.634421 [RxdqsGatingPostProcess] freq 600
4145 00:25:15.638094 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4146 00:25:15.641585 Pre-setting of DQS Precalculation
4147 00:25:15.647564 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4148 00:25:15.648060 ==
4149 00:25:15.651161 Dram Type= 6, Freq= 0, CH_1, rank 0
4150 00:25:15.654924 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4151 00:25:15.655468 ==
4152 00:25:15.660629 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4153 00:25:15.667384 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4154 00:25:15.670899 [CA 0] Center 35 (5~66) winsize 62
4155 00:25:15.674073 [CA 1] Center 34 (4~65) winsize 62
4156 00:25:15.677788 [CA 2] Center 33 (3~64) winsize 62
4157 00:25:15.680830 [CA 3] Center 33 (3~64) winsize 62
4158 00:25:15.684232 [CA 4] Center 33 (2~64) winsize 63
4159 00:25:15.687256 [CA 5] Center 33 (2~64) winsize 63
4160 00:25:15.687758
4161 00:25:15.690979 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4162 00:25:15.691483
4163 00:25:15.694066 [CATrainingPosCal] consider 1 rank data
4164 00:25:15.697487 u2DelayCellTimex100 = 270/100 ps
4165 00:25:15.700792 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4166 00:25:15.703672 CA1 delay=34 (4~65),Diff = 1 PI (9 cell)
4167 00:25:15.707339 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4168 00:25:15.710629 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4169 00:25:15.713637 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4170 00:25:15.717136 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4171 00:25:15.717561
4172 00:25:15.723669 CA PerBit enable=1, Macro0, CA PI delay=33
4173 00:25:15.724179
4174 00:25:15.724544 [CBTSetCACLKResult] CA Dly = 33
4175 00:25:15.727702 CS Dly: 3 (0~34)
4176 00:25:15.728207 ==
4177 00:25:15.730366 Dram Type= 6, Freq= 0, CH_1, rank 1
4178 00:25:15.733838 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4179 00:25:15.734521 ==
4180 00:25:15.740687 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4181 00:25:15.747248 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4182 00:25:15.750173 [CA 0] Center 35 (5~66) winsize 62
4183 00:25:15.753392 [CA 1] Center 34 (4~65) winsize 62
4184 00:25:15.756958 [CA 2] Center 33 (3~64) winsize 62
4185 00:25:15.760271 [CA 3] Center 33 (3~64) winsize 62
4186 00:25:15.763162 [CA 4] Center 32 (2~63) winsize 62
4187 00:25:15.766666 [CA 5] Center 32 (2~63) winsize 62
4188 00:25:15.767099
4189 00:25:15.769713 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4190 00:25:15.770136
4191 00:25:15.773195 [CATrainingPosCal] consider 2 rank data
4192 00:25:15.776497 u2DelayCellTimex100 = 270/100 ps
4193 00:25:15.780060 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4194 00:25:15.783145 CA1 delay=34 (4~65),Diff = 2 PI (19 cell)
4195 00:25:15.786622 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4196 00:25:15.789877 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4197 00:25:15.796744 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4198 00:25:15.799613 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4199 00:25:15.800211
4200 00:25:15.803204 CA PerBit enable=1, Macro0, CA PI delay=32
4201 00:25:15.803720
4202 00:25:15.806663 [CBTSetCACLKResult] CA Dly = 32
4203 00:25:15.807170 CS Dly: 3 (0~35)
4204 00:25:15.807502
4205 00:25:15.809222 ----->DramcWriteLeveling(PI) begin...
4206 00:25:15.809655 ==
4207 00:25:15.813042 Dram Type= 6, Freq= 0, CH_1, rank 0
4208 00:25:15.819762 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4209 00:25:15.820259 ==
4210 00:25:15.822862 Write leveling (Byte 0): 28 => 28
4211 00:25:15.823411 Write leveling (Byte 1): 28 => 28
4212 00:25:15.826632 DramcWriteLeveling(PI) end<-----
4213 00:25:15.827135
4214 00:25:15.829136 ==
4215 00:25:15.832645 Dram Type= 6, Freq= 0, CH_1, rank 0
4216 00:25:15.836465 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4217 00:25:15.837051 ==
4218 00:25:15.839779 [Gating] SW mode calibration
4219 00:25:15.846201 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4220 00:25:15.849693 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4221 00:25:15.855933 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4222 00:25:15.859011 0 5 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
4223 00:25:15.862581 0 5 8 | B1->B0 | 3131 2424 | 0 0 | (0 1) (1 0)
4224 00:25:15.869109 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4225 00:25:15.872534 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4226 00:25:15.875746 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4227 00:25:15.882411 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4228 00:25:15.885793 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4229 00:25:15.889233 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4230 00:25:15.895654 0 6 4 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
4231 00:25:15.898887 0 6 8 | B1->B0 | 3b3b 4242 | 0 0 | (0 0) (0 0)
4232 00:25:15.902203 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4233 00:25:15.909204 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4234 00:25:15.912785 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4235 00:25:15.915593 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4236 00:25:15.922423 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4237 00:25:15.925497 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4238 00:25:15.928754 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4239 00:25:15.935427 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 00:25:15.939142 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 00:25:15.942382 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 00:25:15.948341 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 00:25:15.952288 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 00:25:15.955140 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 00:25:15.961957 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 00:25:15.965351 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 00:25:15.968345 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 00:25:15.975116 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 00:25:15.978282 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 00:25:15.981560 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 00:25:15.988189 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 00:25:15.991251 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 00:25:15.994493 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 00:25:16.001107 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4255 00:25:16.005225 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4256 00:25:16.007759 Total UI for P1: 0, mck2ui 16
4257 00:25:16.011196 best dqsien dly found for B0: ( 0, 9, 4)
4258 00:25:16.014329 Total UI for P1: 0, mck2ui 16
4259 00:25:16.017747 best dqsien dly found for B1: ( 0, 9, 4)
4260 00:25:16.021104 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4261 00:25:16.024295 best DQS1 dly(MCK, UI, PI) = (0, 9, 4)
4262 00:25:16.024721
4263 00:25:16.028007 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4264 00:25:16.031237 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 4)
4265 00:25:16.034421 [Gating] SW calibration Done
4266 00:25:16.034847 ==
4267 00:25:16.037715 Dram Type= 6, Freq= 0, CH_1, rank 0
4268 00:25:16.041014 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4269 00:25:16.041521 ==
4270 00:25:16.044467 RX Vref Scan: 0
4271 00:25:16.045050
4272 00:25:16.047604 RX Vref 0 -> 0, step: 1
4273 00:25:16.048031
4274 00:25:16.048360 RX Delay -230 -> 252, step: 16
4275 00:25:16.053876 iDelay=218, Bit 0, Center 41 (-134 ~ 217) 352
4276 00:25:16.057322 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4277 00:25:16.061076 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4278 00:25:16.064117 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4279 00:25:16.070962 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4280 00:25:16.074734 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4281 00:25:16.077429 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4282 00:25:16.080731 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4283 00:25:16.087404 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4284 00:25:16.090742 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4285 00:25:16.094299 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4286 00:25:16.097584 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4287 00:25:16.100753 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4288 00:25:16.106946 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4289 00:25:16.110666 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4290 00:25:16.113695 iDelay=218, Bit 15, Center 41 (-134 ~ 217) 352
4291 00:25:16.114130 ==
4292 00:25:16.117482 Dram Type= 6, Freq= 0, CH_1, rank 0
4293 00:25:16.123963 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4294 00:25:16.124449 ==
4295 00:25:16.124786 DQS Delay:
4296 00:25:16.125144 DQS0 = 0, DQS1 = 0
4297 00:25:16.126743 DQM Delay:
4298 00:25:16.127172 DQM0 = 38, DQM1 = 30
4299 00:25:16.130369 DQ Delay:
4300 00:25:16.133756 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4301 00:25:16.137910 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4302 00:25:16.140582 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4303 00:25:16.143602 DQ12 =33, DQ13 =49, DQ14 =33, DQ15 =41
4304 00:25:16.144034
4305 00:25:16.144362
4306 00:25:16.144664 ==
4307 00:25:16.146805 Dram Type= 6, Freq= 0, CH_1, rank 0
4308 00:25:16.150505 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4309 00:25:16.150935 ==
4310 00:25:16.151266
4311 00:25:16.151568
4312 00:25:16.153549 TX Vref Scan disable
4313 00:25:16.153976 == TX Byte 0 ==
4314 00:25:16.159951 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4315 00:25:16.163291 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4316 00:25:16.163681 == TX Byte 1 ==
4317 00:25:16.170144 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4318 00:25:16.173316 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4319 00:25:16.173814 ==
4320 00:25:16.176619 Dram Type= 6, Freq= 0, CH_1, rank 0
4321 00:25:16.180124 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4322 00:25:16.180618 ==
4323 00:25:16.180956
4324 00:25:16.183419
4325 00:25:16.183859 TX Vref Scan disable
4326 00:25:16.186498 == TX Byte 0 ==
4327 00:25:16.189955 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4328 00:25:16.196503 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4329 00:25:16.196889 == TX Byte 1 ==
4330 00:25:16.199683 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4331 00:25:16.206091 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4332 00:25:16.206587
4333 00:25:16.206920 [DATLAT]
4334 00:25:16.207284 Freq=600, CH1 RK0
4335 00:25:16.207585
4336 00:25:16.209554 DATLAT Default: 0x9
4337 00:25:16.213078 0, 0xFFFF, sum = 0
4338 00:25:16.213494 1, 0xFFFF, sum = 0
4339 00:25:16.216488 2, 0xFFFF, sum = 0
4340 00:25:16.217012 3, 0xFFFF, sum = 0
4341 00:25:16.219502 4, 0xFFFF, sum = 0
4342 00:25:16.219933 5, 0xFFFF, sum = 0
4343 00:25:16.222900 6, 0xFFFF, sum = 0
4344 00:25:16.223331 7, 0x0, sum = 1
4345 00:25:16.226102 8, 0x0, sum = 2
4346 00:25:16.226574 9, 0x0, sum = 3
4347 00:25:16.226911 10, 0x0, sum = 4
4348 00:25:16.229508 best_step = 8
4349 00:25:16.229928
4350 00:25:16.230296 ==
4351 00:25:16.232983 Dram Type= 6, Freq= 0, CH_1, rank 0
4352 00:25:16.236098 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4353 00:25:16.236483 ==
4354 00:25:16.239662 RX Vref Scan: 1
4355 00:25:16.240043
4356 00:25:16.240331 RX Vref 0 -> 0, step: 1
4357 00:25:16.240604
4358 00:25:16.242685 RX Delay -195 -> 252, step: 8
4359 00:25:16.243083
4360 00:25:16.246260 Set Vref, RX VrefLevel [Byte0]: 54
4361 00:25:16.249434 [Byte1]: 49
4362 00:25:16.253848
4363 00:25:16.254354 Final RX Vref Byte 0 = 54 to rank0
4364 00:25:16.256964 Final RX Vref Byte 1 = 49 to rank0
4365 00:25:16.260431 Final RX Vref Byte 0 = 54 to rank1
4366 00:25:16.264143 Final RX Vref Byte 1 = 49 to rank1==
4367 00:25:16.267011 Dram Type= 6, Freq= 0, CH_1, rank 0
4368 00:25:16.273376 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4369 00:25:16.273814 ==
4370 00:25:16.274171 DQS Delay:
4371 00:25:16.276736 DQS0 = 0, DQS1 = 0
4372 00:25:16.277124 DQM Delay:
4373 00:25:16.277422 DQM0 = 38, DQM1 = 30
4374 00:25:16.280186 DQ Delay:
4375 00:25:16.283521 DQ0 =44, DQ1 =32, DQ2 =28, DQ3 =36
4376 00:25:16.287064 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4377 00:25:16.290172 DQ8 =12, DQ9 =20, DQ10 =32, DQ11 =24
4378 00:25:16.293653 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4379 00:25:16.294376
4380 00:25:16.294687
4381 00:25:16.300148 [DQSOSCAuto] RK0, (LSB)MR18= 0x7373, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
4382 00:25:16.303295 CH1 RK0: MR19=808, MR18=7373
4383 00:25:16.309857 CH1_RK0: MR19=0x808, MR18=0x7373, DQSOSC=388, MR23=63, INC=174, DEC=116
4384 00:25:16.310479
4385 00:25:16.313646 ----->DramcWriteLeveling(PI) begin...
4386 00:25:16.314096 ==
4387 00:25:16.316483 Dram Type= 6, Freq= 0, CH_1, rank 1
4388 00:25:16.319664 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4389 00:25:16.320198 ==
4390 00:25:16.323402 Write leveling (Byte 0): 28 => 28
4391 00:25:16.326307 Write leveling (Byte 1): 28 => 28
4392 00:25:16.329784 DramcWriteLeveling(PI) end<-----
4393 00:25:16.330360
4394 00:25:16.330794 ==
4395 00:25:16.333089 Dram Type= 6, Freq= 0, CH_1, rank 1
4396 00:25:16.336414 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4397 00:25:16.336946 ==
4398 00:25:16.339703 [Gating] SW mode calibration
4399 00:25:16.346777 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4400 00:25:16.353003 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4401 00:25:16.356836 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4402 00:25:16.362902 0 5 4 | B1->B0 | 3434 3131 | 1 0 | (1 0) (1 1)
4403 00:25:16.366694 0 5 8 | B1->B0 | 2f2f 2424 | 1 1 | (1 1) (1 0)
4404 00:25:16.369746 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4405 00:25:16.377092 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4406 00:25:16.380080 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4407 00:25:16.382932 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4408 00:25:16.389686 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4409 00:25:16.393271 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4410 00:25:16.396309 0 6 4 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
4411 00:25:16.399326 0 6 8 | B1->B0 | 3232 4545 | 0 0 | (0 0) (0 0)
4412 00:25:16.405868 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4413 00:25:16.409253 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4414 00:25:16.413102 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4415 00:25:16.419502 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4416 00:25:16.422766 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4417 00:25:16.426202 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4418 00:25:16.433346 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4419 00:25:16.436113 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4420 00:25:16.439710 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4421 00:25:16.446053 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4422 00:25:16.449126 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4423 00:25:16.452901 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4424 00:25:16.459474 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4425 00:25:16.463009 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4426 00:25:16.466207 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4427 00:25:16.472591 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4428 00:25:16.476330 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4429 00:25:16.479203 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 00:25:16.485929 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 00:25:16.489109 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 00:25:16.492501 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 00:25:16.499641 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 00:25:16.502402 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4435 00:25:16.505679 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4436 00:25:16.509003 Total UI for P1: 0, mck2ui 16
4437 00:25:16.512402 best dqsien dly found for B0: ( 0, 9, 4)
4438 00:25:16.519215 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4439 00:25:16.519650 Total UI for P1: 0, mck2ui 16
4440 00:25:16.526004 best dqsien dly found for B1: ( 0, 9, 10)
4441 00:25:16.528938 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4442 00:25:16.532593 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
4443 00:25:16.533099
4444 00:25:16.535833 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4445 00:25:16.539032 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
4446 00:25:16.542477 [Gating] SW calibration Done
4447 00:25:16.543011 ==
4448 00:25:16.545494 Dram Type= 6, Freq= 0, CH_1, rank 1
4449 00:25:16.548621 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4450 00:25:16.549061 ==
4451 00:25:16.552119 RX Vref Scan: 0
4452 00:25:16.552617
4453 00:25:16.552953 RX Vref 0 -> 0, step: 1
4454 00:25:16.553260
4455 00:25:16.555315 RX Delay -230 -> 252, step: 16
4456 00:25:16.558502 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4457 00:25:16.565621 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4458 00:25:16.568455 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4459 00:25:16.571955 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4460 00:25:16.575104 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4461 00:25:16.582369 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4462 00:25:16.585168 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4463 00:25:16.588526 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4464 00:25:16.592431 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4465 00:25:16.595126 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4466 00:25:16.601661 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4467 00:25:16.605156 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4468 00:25:16.608464 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4469 00:25:16.611997 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4470 00:25:16.618779 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4471 00:25:16.621799 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4472 00:25:16.622284 ==
4473 00:25:16.625106 Dram Type= 6, Freq= 0, CH_1, rank 1
4474 00:25:16.628571 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4475 00:25:16.629010 ==
4476 00:25:16.632013 DQS Delay:
4477 00:25:16.632399 DQS0 = 0, DQS1 = 0
4478 00:25:16.632700 DQM Delay:
4479 00:25:16.635022 DQM0 = 39, DQM1 = 33
4480 00:25:16.635406 DQ Delay:
4481 00:25:16.638374 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4482 00:25:16.641845 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33
4483 00:25:16.645016 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4484 00:25:16.648275 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41
4485 00:25:16.648665
4486 00:25:16.649014
4487 00:25:16.651641 ==
4488 00:25:16.652031 Dram Type= 6, Freq= 0, CH_1, rank 1
4489 00:25:16.658060 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4490 00:25:16.658709 ==
4491 00:25:16.659173
4492 00:25:16.659594
4493 00:25:16.659887 TX Vref Scan disable
4494 00:25:16.662089 == TX Byte 0 ==
4495 00:25:16.665956 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4496 00:25:16.669082 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4497 00:25:16.672589 == TX Byte 1 ==
4498 00:25:16.675344 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4499 00:25:16.681836 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4500 00:25:16.682315 ==
4501 00:25:16.685107 Dram Type= 6, Freq= 0, CH_1, rank 1
4502 00:25:16.688660 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4503 00:25:16.689161 ==
4504 00:25:16.689500
4505 00:25:16.689782
4506 00:25:16.692337 TX Vref Scan disable
4507 00:25:16.692863 == TX Byte 0 ==
4508 00:25:16.698521 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4509 00:25:16.702151 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4510 00:25:16.705047 == TX Byte 1 ==
4511 00:25:16.708349 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4512 00:25:16.711499 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4513 00:25:16.711970
4514 00:25:16.712278 [DATLAT]
4515 00:25:16.714839 Freq=600, CH1 RK1
4516 00:25:16.715261
4517 00:25:16.715578 DATLAT Default: 0x8
4518 00:25:16.718460 0, 0xFFFF, sum = 0
4519 00:25:16.721496 1, 0xFFFF, sum = 0
4520 00:25:16.721885 2, 0xFFFF, sum = 0
4521 00:25:16.725150 3, 0xFFFF, sum = 0
4522 00:25:16.725540 4, 0xFFFF, sum = 0
4523 00:25:16.728251 5, 0xFFFF, sum = 0
4524 00:25:16.728685 6, 0xFFFF, sum = 0
4525 00:25:16.731787 7, 0x0, sum = 1
4526 00:25:16.732183 8, 0x0, sum = 2
4527 00:25:16.732510 9, 0x0, sum = 3
4528 00:25:16.735037 10, 0x0, sum = 4
4529 00:25:16.735537 best_step = 8
4530 00:25:16.735873
4531 00:25:16.736177 ==
4532 00:25:16.738916 Dram Type= 6, Freq= 0, CH_1, rank 1
4533 00:25:16.745095 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4534 00:25:16.745580 ==
4535 00:25:16.745886 RX Vref Scan: 0
4536 00:25:16.746161
4537 00:25:16.748139 RX Vref 0 -> 0, step: 1
4538 00:25:16.748520
4539 00:25:16.751537 RX Delay -195 -> 252, step: 8
4540 00:25:16.754915 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4541 00:25:16.762418 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4542 00:25:16.765027 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4543 00:25:16.768518 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4544 00:25:16.771368 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4545 00:25:16.778719 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4546 00:25:16.781361 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4547 00:25:16.784987 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4548 00:25:16.787910 iDelay=205, Bit 8, Center 12 (-147 ~ 172) 320
4549 00:25:16.794754 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4550 00:25:16.798430 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4551 00:25:16.801491 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4552 00:25:16.804577 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4553 00:25:16.808471 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4554 00:25:16.814298 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4555 00:25:16.817749 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4556 00:25:16.818293 ==
4557 00:25:16.821052 Dram Type= 6, Freq= 0, CH_1, rank 1
4558 00:25:16.824750 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4559 00:25:16.825261 ==
4560 00:25:16.827586 DQS Delay:
4561 00:25:16.828009 DQS0 = 0, DQS1 = 0
4562 00:25:16.830896 DQM Delay:
4563 00:25:16.831446 DQM0 = 37, DQM1 = 30
4564 00:25:16.831782 DQ Delay:
4565 00:25:16.834612 DQ0 =40, DQ1 =32, DQ2 =32, DQ3 =32
4566 00:25:16.838326 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4567 00:25:16.840970 DQ8 =12, DQ9 =20, DQ10 =32, DQ11 =20
4568 00:25:16.844476 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4569 00:25:16.844982
4570 00:25:16.845308
4571 00:25:16.854093 [DQSOSCAuto] RK1, (LSB)MR18= 0x6161, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
4572 00:25:16.857427 CH1 RK1: MR19=808, MR18=6161
4573 00:25:16.863785 CH1_RK1: MR19=0x808, MR18=0x6161, DQSOSC=391, MR23=63, INC=171, DEC=114
4574 00:25:16.864290 [RxdqsGatingPostProcess] freq 600
4575 00:25:16.870665 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4576 00:25:16.874166 Pre-setting of DQS Precalculation
4577 00:25:16.877160 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4578 00:25:16.887459 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4579 00:25:16.893602 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4580 00:25:16.894035
4581 00:25:16.894425
4582 00:25:16.897218 [Calibration Summary] 1200 Mbps
4583 00:25:16.897739 CH 0, Rank 0
4584 00:25:16.900291 SW Impedance : PASS
4585 00:25:16.900716 DUTY Scan : NO K
4586 00:25:16.904249 ZQ Calibration : PASS
4587 00:25:16.907188 Jitter Meter : NO K
4588 00:25:16.907618 CBT Training : PASS
4589 00:25:16.910278 Write leveling : PASS
4590 00:25:16.913787 RX DQS gating : PASS
4591 00:25:16.914348 RX DQ/DQS(RDDQC) : PASS
4592 00:25:16.916811 TX DQ/DQS : PASS
4593 00:25:16.920565 RX DATLAT : PASS
4594 00:25:16.921079 RX DQ/DQS(Engine): PASS
4595 00:25:16.923442 TX OE : NO K
4596 00:25:16.923867 All Pass.
4597 00:25:16.924189
4598 00:25:16.926653 CH 0, Rank 1
4599 00:25:16.927079 SW Impedance : PASS
4600 00:25:16.930137 DUTY Scan : NO K
4601 00:25:16.934027 ZQ Calibration : PASS
4602 00:25:16.934706 Jitter Meter : NO K
4603 00:25:16.936996 CBT Training : PASS
4604 00:25:16.939733 Write leveling : PASS
4605 00:25:16.940161 RX DQS gating : PASS
4606 00:25:16.943124 RX DQ/DQS(RDDQC) : PASS
4607 00:25:16.946918 TX DQ/DQS : PASS
4608 00:25:16.947429 RX DATLAT : PASS
4609 00:25:16.950056 RX DQ/DQS(Engine): PASS
4610 00:25:16.953216 TX OE : NO K
4611 00:25:16.953727 All Pass.
4612 00:25:16.954057
4613 00:25:16.954431 CH 1, Rank 0
4614 00:25:16.956629 SW Impedance : PASS
4615 00:25:16.960046 DUTY Scan : NO K
4616 00:25:16.960484 ZQ Calibration : PASS
4617 00:25:16.963772 Jitter Meter : NO K
4618 00:25:16.964278 CBT Training : PASS
4619 00:25:16.966438 Write leveling : PASS
4620 00:25:16.969798 RX DQS gating : PASS
4621 00:25:16.970361 RX DQ/DQS(RDDQC) : PASS
4622 00:25:16.973177 TX DQ/DQS : PASS
4623 00:25:16.977000 RX DATLAT : PASS
4624 00:25:16.977506 RX DQ/DQS(Engine): PASS
4625 00:25:16.979711 TX OE : NO K
4626 00:25:16.980138 All Pass.
4627 00:25:16.980465
4628 00:25:16.983045 CH 1, Rank 1
4629 00:25:16.983513 SW Impedance : PASS
4630 00:25:16.986017 DUTY Scan : NO K
4631 00:25:16.989656 ZQ Calibration : PASS
4632 00:25:16.990168 Jitter Meter : NO K
4633 00:25:16.993644 CBT Training : PASS
4634 00:25:16.996704 Write leveling : PASS
4635 00:25:16.997212 RX DQS gating : PASS
4636 00:25:16.999600 RX DQ/DQS(RDDQC) : PASS
4637 00:25:17.002786 TX DQ/DQS : PASS
4638 00:25:17.003289 RX DATLAT : PASS
4639 00:25:17.006101 RX DQ/DQS(Engine): PASS
4640 00:25:17.009584 TX OE : NO K
4641 00:25:17.010089 All Pass.
4642 00:25:17.010469
4643 00:25:17.010779 DramC Write-DBI off
4644 00:25:17.012802 PER_BANK_REFRESH: Hybrid Mode
4645 00:25:17.015905 TX_TRACKING: ON
4646 00:25:17.022726 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4647 00:25:17.025662 [FAST_K] Save calibration result to emmc
4648 00:25:17.032155 dramc_set_vcore_voltage set vcore to 662500
4649 00:25:17.032584 Read voltage for 933, 3
4650 00:25:17.035936 Vio18 = 0
4651 00:25:17.036360 Vcore = 662500
4652 00:25:17.036778 Vdram = 0
4653 00:25:17.039543 Vddq = 0
4654 00:25:17.039970 Vmddr = 0
4655 00:25:17.042452 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4656 00:25:17.049090 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4657 00:25:17.052785 MEM_TYPE=3, freq_sel=17
4658 00:25:17.056251 sv_algorithm_assistance_LP4_1600
4659 00:25:17.058789 ============ PULL DRAM RESETB DOWN ============
4660 00:25:17.062441 ========== PULL DRAM RESETB DOWN end =========
4661 00:25:17.065710 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4662 00:25:17.069251 ===================================
4663 00:25:17.072402 LPDDR4 DRAM CONFIGURATION
4664 00:25:17.075239 ===================================
4665 00:25:17.078998 EX_ROW_EN[0] = 0x0
4666 00:25:17.079505 EX_ROW_EN[1] = 0x0
4667 00:25:17.081970 LP4Y_EN = 0x0
4668 00:25:17.082430 WORK_FSP = 0x0
4669 00:25:17.085728 WL = 0x3
4670 00:25:17.086311 RL = 0x3
4671 00:25:17.088978 BL = 0x2
4672 00:25:17.089472 RPST = 0x0
4673 00:25:17.092222 RD_PRE = 0x0
4674 00:25:17.092727 WR_PRE = 0x1
4675 00:25:17.095793 WR_PST = 0x0
4676 00:25:17.098567 DBI_WR = 0x0
4677 00:25:17.098995 DBI_RD = 0x0
4678 00:25:17.102378 OTF = 0x1
4679 00:25:17.105361 ===================================
4680 00:25:17.108634 ===================================
4681 00:25:17.109063 ANA top config
4682 00:25:17.111908 ===================================
4683 00:25:17.115339 DLL_ASYNC_EN = 0
4684 00:25:17.118610 ALL_SLAVE_EN = 1
4685 00:25:17.119036 NEW_RANK_MODE = 1
4686 00:25:17.121946 DLL_IDLE_MODE = 1
4687 00:25:17.125348 LP45_APHY_COMB_EN = 1
4688 00:25:17.129099 TX_ODT_DIS = 1
4689 00:25:17.129604 NEW_8X_MODE = 1
4690 00:25:17.132197 ===================================
4691 00:25:17.135547 ===================================
4692 00:25:17.138561 data_rate = 1866
4693 00:25:17.142406 CKR = 1
4694 00:25:17.145234 DQ_P2S_RATIO = 8
4695 00:25:17.148842 ===================================
4696 00:25:17.152267 CA_P2S_RATIO = 8
4697 00:25:17.155091 DQ_CA_OPEN = 0
4698 00:25:17.155519 DQ_SEMI_OPEN = 0
4699 00:25:17.158669 CA_SEMI_OPEN = 0
4700 00:25:17.162172 CA_FULL_RATE = 0
4701 00:25:17.165204 DQ_CKDIV4_EN = 1
4702 00:25:17.168686 CA_CKDIV4_EN = 1
4703 00:25:17.172001 CA_PREDIV_EN = 0
4704 00:25:17.172432 PH8_DLY = 0
4705 00:25:17.175156 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4706 00:25:17.178799 DQ_AAMCK_DIV = 4
4707 00:25:17.181991 CA_AAMCK_DIV = 4
4708 00:25:17.185254 CA_ADMCK_DIV = 4
4709 00:25:17.188376 DQ_TRACK_CA_EN = 0
4710 00:25:17.188809 CA_PICK = 933
4711 00:25:17.191822 CA_MCKIO = 933
4712 00:25:17.195394 MCKIO_SEMI = 0
4713 00:25:17.198725 PLL_FREQ = 3732
4714 00:25:17.201879 DQ_UI_PI_RATIO = 32
4715 00:25:17.205045 CA_UI_PI_RATIO = 0
4716 00:25:17.208692 ===================================
4717 00:25:17.211626 ===================================
4718 00:25:17.212056 memory_type:LPDDR4
4719 00:25:17.215103 GP_NUM : 10
4720 00:25:17.218296 SRAM_EN : 1
4721 00:25:17.218756 MD32_EN : 0
4722 00:25:17.221388 ===================================
4723 00:25:17.224825 [ANA_INIT] >>>>>>>>>>>>>>
4724 00:25:17.228050 <<<<<< [CONFIGURE PHASE]: ANA_TX
4725 00:25:17.231452 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4726 00:25:17.235119 ===================================
4727 00:25:17.238338 data_rate = 1866,PCW = 0X8f00
4728 00:25:17.241637 ===================================
4729 00:25:17.244982 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4730 00:25:17.247891 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4731 00:25:17.255214 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4732 00:25:17.258243 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4733 00:25:17.264440 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4734 00:25:17.268280 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4735 00:25:17.268791 [ANA_INIT] flow start
4736 00:25:17.271111 [ANA_INIT] PLL >>>>>>>>
4737 00:25:17.275008 [ANA_INIT] PLL <<<<<<<<
4738 00:25:17.275434 [ANA_INIT] MIDPI >>>>>>>>
4739 00:25:17.277978 [ANA_INIT] MIDPI <<<<<<<<
4740 00:25:17.281413 [ANA_INIT] DLL >>>>>>>>
4741 00:25:17.281933 [ANA_INIT] flow end
4742 00:25:17.287831 ============ LP4 DIFF to SE enter ============
4743 00:25:17.291026 ============ LP4 DIFF to SE exit ============
4744 00:25:17.291568 [ANA_INIT] <<<<<<<<<<<<<
4745 00:25:17.294692 [Flow] Enable top DCM control >>>>>
4746 00:25:17.297930 [Flow] Enable top DCM control <<<<<
4747 00:25:17.301087 Enable DLL master slave shuffle
4748 00:25:17.307539 ==============================================================
4749 00:25:17.310824 Gating Mode config
4750 00:25:17.314262 ==============================================================
4751 00:25:17.317685 Config description:
4752 00:25:17.327461 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4753 00:25:17.334038 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4754 00:25:17.337366 SELPH_MODE 0: By rank 1: By Phase
4755 00:25:17.344119 ==============================================================
4756 00:25:17.347148 GAT_TRACK_EN = 1
4757 00:25:17.350569 RX_GATING_MODE = 2
4758 00:25:17.353846 RX_GATING_TRACK_MODE = 2
4759 00:25:17.354336 SELPH_MODE = 1
4760 00:25:17.357366 PICG_EARLY_EN = 1
4761 00:25:17.360682 VALID_LAT_VALUE = 1
4762 00:25:17.366946 ==============================================================
4763 00:25:17.370967 Enter into Gating configuration >>>>
4764 00:25:17.373597 Exit from Gating configuration <<<<
4765 00:25:17.377245 Enter into DVFS_PRE_config >>>>>
4766 00:25:17.387171 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4767 00:25:17.390186 Exit from DVFS_PRE_config <<<<<
4768 00:25:17.393888 Enter into PICG configuration >>>>
4769 00:25:17.396880 Exit from PICG configuration <<<<
4770 00:25:17.399980 [RX_INPUT] configuration >>>>>
4771 00:25:17.403150 [RX_INPUT] configuration <<<<<
4772 00:25:17.407062 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4773 00:25:17.413454 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4774 00:25:17.419767 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4775 00:25:17.426900 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4776 00:25:17.433327 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4777 00:25:17.436464 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4778 00:25:17.443210 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4779 00:25:17.446682 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4780 00:25:17.449862 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4781 00:25:17.453231 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4782 00:25:17.459853 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4783 00:25:17.463417 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4784 00:25:17.466449 ===================================
4785 00:25:17.469899 LPDDR4 DRAM CONFIGURATION
4786 00:25:17.473242 ===================================
4787 00:25:17.473856 EX_ROW_EN[0] = 0x0
4788 00:25:17.477164 EX_ROW_EN[1] = 0x0
4789 00:25:17.477563 LP4Y_EN = 0x0
4790 00:25:17.479930 WORK_FSP = 0x0
4791 00:25:17.480254 WL = 0x3
4792 00:25:17.483029 RL = 0x3
4793 00:25:17.483416 BL = 0x2
4794 00:25:17.486570 RPST = 0x0
4795 00:25:17.486991 RD_PRE = 0x0
4796 00:25:17.489910 WR_PRE = 0x1
4797 00:25:17.490334 WR_PST = 0x0
4798 00:25:17.493161 DBI_WR = 0x0
4799 00:25:17.496676 DBI_RD = 0x0
4800 00:25:17.497182 OTF = 0x1
4801 00:25:17.499633 ===================================
4802 00:25:17.502853 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4803 00:25:17.506061 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4804 00:25:17.513232 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4805 00:25:17.516050 ===================================
4806 00:25:17.519443 LPDDR4 DRAM CONFIGURATION
4807 00:25:17.522899 ===================================
4808 00:25:17.523287 EX_ROW_EN[0] = 0x10
4809 00:25:17.526084 EX_ROW_EN[1] = 0x0
4810 00:25:17.526557 LP4Y_EN = 0x0
4811 00:25:17.529460 WORK_FSP = 0x0
4812 00:25:17.529899 WL = 0x3
4813 00:25:17.532728 RL = 0x3
4814 00:25:17.533212 BL = 0x2
4815 00:25:17.535921 RPST = 0x0
4816 00:25:17.536306 RD_PRE = 0x0
4817 00:25:17.539663 WR_PRE = 0x1
4818 00:25:17.540051 WR_PST = 0x0
4819 00:25:17.543005 DBI_WR = 0x0
4820 00:25:17.543533 DBI_RD = 0x0
4821 00:25:17.546190 OTF = 0x1
4822 00:25:17.549747 ===================================
4823 00:25:17.555972 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4824 00:25:17.559288 nWR fixed to 30
4825 00:25:17.562919 [ModeRegInit_LP4] CH0 RK0
4826 00:25:17.563369 [ModeRegInit_LP4] CH0 RK1
4827 00:25:17.566006 [ModeRegInit_LP4] CH1 RK0
4828 00:25:17.569350 [ModeRegInit_LP4] CH1 RK1
4829 00:25:17.569760 match AC timing 8
4830 00:25:17.575944 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4831 00:25:17.579823 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4832 00:25:17.583276 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4833 00:25:17.589584 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4834 00:25:17.593335 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4835 00:25:17.593803 ==
4836 00:25:17.596103 Dram Type= 6, Freq= 0, CH_0, rank 0
4837 00:25:17.599417 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4838 00:25:17.599887 ==
4839 00:25:17.606182 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4840 00:25:17.612458 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4841 00:25:17.616030 [CA 0] Center 38 (8~69) winsize 62
4842 00:25:17.619034 [CA 1] Center 38 (7~69) winsize 63
4843 00:25:17.622561 [CA 2] Center 36 (6~67) winsize 62
4844 00:25:17.625928 [CA 3] Center 36 (6~66) winsize 61
4845 00:25:17.629360 [CA 4] Center 34 (4~65) winsize 62
4846 00:25:17.632514 [CA 5] Center 34 (4~65) winsize 62
4847 00:25:17.632979
4848 00:25:17.635768 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4849 00:25:17.636158
4850 00:25:17.638770 [CATrainingPosCal] consider 1 rank data
4851 00:25:17.642609 u2DelayCellTimex100 = 270/100 ps
4852 00:25:17.645971 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4853 00:25:17.649179 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
4854 00:25:17.652483 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4855 00:25:17.655882 CA3 delay=36 (6~66),Diff = 2 PI (12 cell)
4856 00:25:17.658758 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4857 00:25:17.662308 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4858 00:25:17.665874
4859 00:25:17.669237 CA PerBit enable=1, Macro0, CA PI delay=34
4860 00:25:17.669703
4861 00:25:17.672522 [CBTSetCACLKResult] CA Dly = 34
4862 00:25:17.672994 CS Dly: 7 (0~38)
4863 00:25:17.673294 ==
4864 00:25:17.675510 Dram Type= 6, Freq= 0, CH_0, rank 1
4865 00:25:17.678669 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4866 00:25:17.679059 ==
4867 00:25:17.685279 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4868 00:25:17.692308 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4869 00:25:17.695615 [CA 0] Center 38 (8~69) winsize 62
4870 00:25:17.699462 [CA 1] Center 38 (7~69) winsize 63
4871 00:25:17.702197 [CA 2] Center 36 (6~67) winsize 62
4872 00:25:17.705450 [CA 3] Center 35 (5~66) winsize 62
4873 00:25:17.708683 [CA 4] Center 34 (4~65) winsize 62
4874 00:25:17.712395 [CA 5] Center 34 (4~65) winsize 62
4875 00:25:17.712881
4876 00:25:17.715929 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4877 00:25:17.716398
4878 00:25:17.718741 [CATrainingPosCal] consider 2 rank data
4879 00:25:17.722432 u2DelayCellTimex100 = 270/100 ps
4880 00:25:17.725449 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4881 00:25:17.729143 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
4882 00:25:17.732061 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4883 00:25:17.735499 CA3 delay=36 (6~66),Diff = 2 PI (12 cell)
4884 00:25:17.742207 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4885 00:25:17.745317 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4886 00:25:17.745819
4887 00:25:17.748436 CA PerBit enable=1, Macro0, CA PI delay=34
4888 00:25:17.748864
4889 00:25:17.752058 [CBTSetCACLKResult] CA Dly = 34
4890 00:25:17.752486 CS Dly: 7 (0~39)
4891 00:25:17.752816
4892 00:25:17.755132 ----->DramcWriteLeveling(PI) begin...
4893 00:25:17.755603 ==
4894 00:25:17.758541 Dram Type= 6, Freq= 0, CH_0, rank 0
4895 00:25:17.765328 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4896 00:25:17.765824 ==
4897 00:25:17.768855 Write leveling (Byte 0): 30 => 30
4898 00:25:17.769362 Write leveling (Byte 1): 24 => 24
4899 00:25:17.771997 DramcWriteLeveling(PI) end<-----
4900 00:25:17.772419
4901 00:25:17.772747 ==
4902 00:25:17.775035 Dram Type= 6, Freq= 0, CH_0, rank 0
4903 00:25:17.781888 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4904 00:25:17.782427 ==
4905 00:25:17.785406 [Gating] SW mode calibration
4906 00:25:17.791956 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4907 00:25:17.795681 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4908 00:25:17.802470 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4909 00:25:17.805880 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4910 00:25:17.809282 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4911 00:25:17.815907 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4912 00:25:17.818198 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4913 00:25:17.821957 0 10 20 | B1->B0 | 3232 2f2f | 1 1 | (0 0) (0 0)
4914 00:25:17.828271 0 10 24 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
4915 00:25:17.831932 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4916 00:25:17.834961 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4917 00:25:17.841804 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4918 00:25:17.845172 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4919 00:25:17.848338 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4920 00:25:17.854929 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4921 00:25:17.857837 0 11 20 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
4922 00:25:17.861395 0 11 24 | B1->B0 | 3939 4545 | 0 0 | (0 0) (0 0)
4923 00:25:17.868147 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4924 00:25:17.871238 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4925 00:25:17.874389 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4926 00:25:17.881237 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4927 00:25:17.884764 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4928 00:25:17.888002 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4929 00:25:17.891654 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4930 00:25:17.897723 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4931 00:25:17.901352 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4932 00:25:17.904431 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4933 00:25:17.911026 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4934 00:25:17.914428 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4935 00:25:17.917754 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4936 00:25:17.924555 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4937 00:25:17.927824 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4938 00:25:17.930973 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4939 00:25:17.937351 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4940 00:25:17.940738 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4941 00:25:17.944254 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4942 00:25:17.950608 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4943 00:25:17.954152 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4944 00:25:17.957464 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4945 00:25:17.963795 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4946 00:25:17.966995 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4947 00:25:17.970885 Total UI for P1: 0, mck2ui 16
4948 00:25:17.973864 best dqsien dly found for B0: ( 0, 14, 20)
4949 00:25:17.976813 Total UI for P1: 0, mck2ui 16
4950 00:25:17.980371 best dqsien dly found for B1: ( 0, 14, 20)
4951 00:25:17.983494 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
4952 00:25:17.987224 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
4953 00:25:17.987845
4954 00:25:17.990320 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
4955 00:25:17.997240 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
4956 00:25:17.997748 [Gating] SW calibration Done
4957 00:25:17.998088 ==
4958 00:25:18.000681 Dram Type= 6, Freq= 0, CH_0, rank 0
4959 00:25:18.007648 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4960 00:25:18.008156 ==
4961 00:25:18.008490 RX Vref Scan: 0
4962 00:25:18.008794
4963 00:25:18.010192 RX Vref 0 -> 0, step: 1
4964 00:25:18.010668
4965 00:25:18.013815 RX Delay -80 -> 252, step: 8
4966 00:25:18.017249 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
4967 00:25:18.020040 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
4968 00:25:18.023679 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
4969 00:25:18.026808 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
4970 00:25:18.033700 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
4971 00:25:18.036889 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
4972 00:25:18.040390 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
4973 00:25:18.043808 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
4974 00:25:18.047035 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
4975 00:25:18.050419 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
4976 00:25:18.057153 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
4977 00:25:18.060412 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
4978 00:25:18.063836 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
4979 00:25:18.066614 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
4980 00:25:18.069854 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
4981 00:25:18.076818 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
4982 00:25:18.077244 ==
4983 00:25:18.080244 Dram Type= 6, Freq= 0, CH_0, rank 0
4984 00:25:18.083231 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4985 00:25:18.083665 ==
4986 00:25:18.083994 DQS Delay:
4987 00:25:18.086398 DQS0 = 0, DQS1 = 0
4988 00:25:18.086822 DQM Delay:
4989 00:25:18.089711 DQM0 = 95, DQM1 = 85
4990 00:25:18.090134 DQ Delay:
4991 00:25:18.093153 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
4992 00:25:18.096501 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =103
4993 00:25:18.099887 DQ8 =79, DQ9 =75, DQ10 =83, DQ11 =79
4994 00:25:18.103228 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
4995 00:25:18.103661
4996 00:25:18.104021
4997 00:25:18.104342 ==
4998 00:25:18.106587 Dram Type= 6, Freq= 0, CH_0, rank 0
4999 00:25:18.109643 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5000 00:25:18.113552 ==
5001 00:25:18.113975
5002 00:25:18.114342
5003 00:25:18.114655 TX Vref Scan disable
5004 00:25:18.116854 == TX Byte 0 ==
5005 00:25:18.119909 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5006 00:25:18.123361 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5007 00:25:18.126553 == TX Byte 1 ==
5008 00:25:18.130008 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5009 00:25:18.133800 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5010 00:25:18.136422 ==
5011 00:25:18.136935 Dram Type= 6, Freq= 0, CH_0, rank 0
5012 00:25:18.142903 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5013 00:25:18.143336 ==
5014 00:25:18.143661
5015 00:25:18.143962
5016 00:25:18.146595 TX Vref Scan disable
5017 00:25:18.147016 == TX Byte 0 ==
5018 00:25:18.152791 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5019 00:25:18.156098 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5020 00:25:18.156524 == TX Byte 1 ==
5021 00:25:18.163186 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5022 00:25:18.166349 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5023 00:25:18.166735
5024 00:25:18.167026 [DATLAT]
5025 00:25:18.170049 Freq=933, CH0 RK0
5026 00:25:18.170470
5027 00:25:18.170769 DATLAT Default: 0xd
5028 00:25:18.172821 0, 0xFFFF, sum = 0
5029 00:25:18.173207 1, 0xFFFF, sum = 0
5030 00:25:18.176496 2, 0xFFFF, sum = 0
5031 00:25:18.176971 3, 0xFFFF, sum = 0
5032 00:25:18.179387 4, 0xFFFF, sum = 0
5033 00:25:18.179773 5, 0xFFFF, sum = 0
5034 00:25:18.182513 6, 0xFFFF, sum = 0
5035 00:25:18.182901 7, 0xFFFF, sum = 0
5036 00:25:18.186115 8, 0xFFFF, sum = 0
5037 00:25:18.186532 9, 0xFFFF, sum = 0
5038 00:25:18.189430 10, 0x0, sum = 1
5039 00:25:18.189817 11, 0x0, sum = 2
5040 00:25:18.192851 12, 0x0, sum = 3
5041 00:25:18.193242 13, 0x0, sum = 4
5042 00:25:18.196036 best_step = 11
5043 00:25:18.196431
5044 00:25:18.196721 ==
5045 00:25:18.199577 Dram Type= 6, Freq= 0, CH_0, rank 0
5046 00:25:18.202643 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5047 00:25:18.203032 ==
5048 00:25:18.206478 RX Vref Scan: 1
5049 00:25:18.206999
5050 00:25:18.207301 RX Vref 0 -> 0, step: 1
5051 00:25:18.207576
5052 00:25:18.209259 RX Delay -77 -> 252, step: 4
5053 00:25:18.209643
5054 00:25:18.212687 Set Vref, RX VrefLevel [Byte0]: 46
5055 00:25:18.215777 [Byte1]: 49
5056 00:25:18.220384
5057 00:25:18.220846 Final RX Vref Byte 0 = 46 to rank0
5058 00:25:18.223419 Final RX Vref Byte 1 = 49 to rank0
5059 00:25:18.227127 Final RX Vref Byte 0 = 46 to rank1
5060 00:25:18.230082 Final RX Vref Byte 1 = 49 to rank1==
5061 00:25:18.233452 Dram Type= 6, Freq= 0, CH_0, rank 0
5062 00:25:18.239877 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5063 00:25:18.240375 ==
5064 00:25:18.240708 DQS Delay:
5065 00:25:18.241011 DQS0 = 0, DQS1 = 0
5066 00:25:18.243992 DQM Delay:
5067 00:25:18.244416 DQM0 = 97, DQM1 = 86
5068 00:25:18.246770 DQ Delay:
5069 00:25:18.249760 DQ0 =92, DQ1 =96, DQ2 =96, DQ3 =94
5070 00:25:18.253097 DQ4 =100, DQ5 =90, DQ6 =104, DQ7 =104
5071 00:25:18.257051 DQ8 =76, DQ9 =70, DQ10 =86, DQ11 =80
5072 00:25:18.260627 DQ12 =94, DQ13 =94, DQ14 =96, DQ15 =96
5073 00:25:18.261303
5074 00:25:18.261813
5075 00:25:18.266617 [DQSOSCAuto] RK0, (LSB)MR18= 0x2727, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 409 ps
5076 00:25:18.269876 CH0 RK0: MR19=505, MR18=2727
5077 00:25:18.276285 CH0_RK0: MR19=0x505, MR18=0x2727, DQSOSC=409, MR23=63, INC=64, DEC=43
5078 00:25:18.276705
5079 00:25:18.279955 ----->DramcWriteLeveling(PI) begin...
5080 00:25:18.280343 ==
5081 00:25:18.283216 Dram Type= 6, Freq= 0, CH_0, rank 1
5082 00:25:18.286494 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5083 00:25:18.286947 ==
5084 00:25:18.289808 Write leveling (Byte 0): 27 => 27
5085 00:25:18.293086 Write leveling (Byte 1): 27 => 27
5086 00:25:18.296516 DramcWriteLeveling(PI) end<-----
5087 00:25:18.296900
5088 00:25:18.297193 ==
5089 00:25:18.299588 Dram Type= 6, Freq= 0, CH_0, rank 1
5090 00:25:18.303094 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5091 00:25:18.303480 ==
5092 00:25:18.306382 [Gating] SW mode calibration
5093 00:25:18.313030 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5094 00:25:18.320023 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5095 00:25:18.323156 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5096 00:25:18.329951 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5097 00:25:18.333314 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5098 00:25:18.336407 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5099 00:25:18.342917 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5100 00:25:18.346713 0 10 20 | B1->B0 | 2f2f 2f2f | 1 0 | (1 0) (0 0)
5101 00:25:18.349659 0 10 24 | B1->B0 | 2424 2323 | 0 0 | (1 0) (1 0)
5102 00:25:18.353060 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5103 00:25:18.359747 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5104 00:25:18.363591 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5105 00:25:18.369803 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5106 00:25:18.372929 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5107 00:25:18.375964 0 11 16 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)
5108 00:25:18.379406 0 11 20 | B1->B0 | 2b2b 3a3a | 1 1 | (0 0) (0 0)
5109 00:25:18.385894 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5110 00:25:18.389427 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5111 00:25:18.393174 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5112 00:25:18.399037 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5113 00:25:18.402630 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5114 00:25:18.406068 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5115 00:25:18.412435 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5116 00:25:18.415685 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5117 00:25:18.418851 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5118 00:25:18.425776 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5119 00:25:18.429040 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5120 00:25:18.432609 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5121 00:25:18.438875 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5122 00:25:18.442556 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5123 00:25:18.445399 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5124 00:25:18.452130 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5125 00:25:18.455198 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5126 00:25:18.458938 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 00:25:18.465335 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 00:25:18.468584 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 00:25:18.472284 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 00:25:18.478464 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 00:25:18.482020 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 00:25:18.484920 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5133 00:25:18.492023 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5134 00:25:18.495182 Total UI for P1: 0, mck2ui 16
5135 00:25:18.498936 best dqsien dly found for B0: ( 0, 14, 20)
5136 00:25:18.502147 Total UI for P1: 0, mck2ui 16
5137 00:25:18.505175 best dqsien dly found for B1: ( 0, 14, 22)
5138 00:25:18.508683 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
5139 00:25:18.511259 best DQS1 dly(MCK, UI, PI) = (0, 14, 22)
5140 00:25:18.511692
5141 00:25:18.514498 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
5142 00:25:18.518043 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22)
5143 00:25:18.521512 [Gating] SW calibration Done
5144 00:25:18.522016 ==
5145 00:25:18.524500 Dram Type= 6, Freq= 0, CH_0, rank 1
5146 00:25:18.527900 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5147 00:25:18.528348 ==
5148 00:25:18.531240 RX Vref Scan: 0
5149 00:25:18.531664
5150 00:25:18.534309 RX Vref 0 -> 0, step: 1
5151 00:25:18.534880
5152 00:25:18.535263 RX Delay -80 -> 252, step: 8
5153 00:25:18.541281 iDelay=200, Bit 0, Center 91 (-8 ~ 191) 200
5154 00:25:18.544769 iDelay=200, Bit 1, Center 103 (8 ~ 199) 192
5155 00:25:18.547710 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5156 00:25:18.551161 iDelay=200, Bit 3, Center 91 (0 ~ 183) 184
5157 00:25:18.554652 iDelay=200, Bit 4, Center 99 (0 ~ 199) 200
5158 00:25:18.557746 iDelay=200, Bit 5, Center 83 (-16 ~ 183) 200
5159 00:25:18.564347 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5160 00:25:18.567649 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5161 00:25:18.570944 iDelay=200, Bit 8, Center 75 (-16 ~ 167) 184
5162 00:25:18.574337 iDelay=200, Bit 9, Center 71 (-24 ~ 167) 192
5163 00:25:18.577550 iDelay=200, Bit 10, Center 83 (-16 ~ 183) 200
5164 00:25:18.584158 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5165 00:25:18.587741 iDelay=200, Bit 12, Center 99 (8 ~ 191) 184
5166 00:25:18.590595 iDelay=200, Bit 13, Center 99 (8 ~ 191) 184
5167 00:25:18.594078 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5168 00:25:18.597010 iDelay=200, Bit 15, Center 99 (8 ~ 191) 184
5169 00:25:18.600689 ==
5170 00:25:18.601155 Dram Type= 6, Freq= 0, CH_0, rank 1
5171 00:25:18.606885 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5172 00:25:18.607276 ==
5173 00:25:18.607575 DQS Delay:
5174 00:25:18.610790 DQS0 = 0, DQS1 = 0
5175 00:25:18.611271 DQM Delay:
5176 00:25:18.613987 DQM0 = 96, DQM1 = 88
5177 00:25:18.614443 DQ Delay:
5178 00:25:18.616770 DQ0 =91, DQ1 =103, DQ2 =95, DQ3 =91
5179 00:25:18.620349 DQ4 =99, DQ5 =83, DQ6 =103, DQ7 =103
5180 00:25:18.624139 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =79
5181 00:25:18.627230 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5182 00:25:18.627639
5183 00:25:18.627936
5184 00:25:18.628311 ==
5185 00:25:18.630027 Dram Type= 6, Freq= 0, CH_0, rank 1
5186 00:25:18.633755 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5187 00:25:18.634309 ==
5188 00:25:18.634656
5189 00:25:18.634935
5190 00:25:18.636784 TX Vref Scan disable
5191 00:25:18.640259 == TX Byte 0 ==
5192 00:25:18.644136 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5193 00:25:18.647354 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5194 00:25:18.650119 == TX Byte 1 ==
5195 00:25:18.653688 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5196 00:25:18.656990 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5197 00:25:18.657468 ==
5198 00:25:18.660352 Dram Type= 6, Freq= 0, CH_0, rank 1
5199 00:25:18.666907 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5200 00:25:18.667427 ==
5201 00:25:18.667904
5202 00:25:18.668266
5203 00:25:18.668621 TX Vref Scan disable
5204 00:25:18.670548 == TX Byte 0 ==
5205 00:25:18.674021 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5206 00:25:18.677379 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5207 00:25:18.680382 == TX Byte 1 ==
5208 00:25:18.684109 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5209 00:25:18.687685 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5210 00:25:18.690872
5211 00:25:18.691338 [DATLAT]
5212 00:25:18.691637 Freq=933, CH0 RK1
5213 00:25:18.691912
5214 00:25:18.693521 DATLAT Default: 0xb
5215 00:25:18.693902 0, 0xFFFF, sum = 0
5216 00:25:18.697890 1, 0xFFFF, sum = 0
5217 00:25:18.698410 2, 0xFFFF, sum = 0
5218 00:25:18.700582 3, 0xFFFF, sum = 0
5219 00:25:18.701056 4, 0xFFFF, sum = 0
5220 00:25:18.704034 5, 0xFFFF, sum = 0
5221 00:25:18.707294 6, 0xFFFF, sum = 0
5222 00:25:18.707764 7, 0xFFFF, sum = 0
5223 00:25:18.710996 8, 0xFFFF, sum = 0
5224 00:25:18.711515 9, 0xFFFF, sum = 0
5225 00:25:18.714123 10, 0x0, sum = 1
5226 00:25:18.714600 11, 0x0, sum = 2
5227 00:25:18.714907 12, 0x0, sum = 3
5228 00:25:18.717423 13, 0x0, sum = 4
5229 00:25:18.717813 best_step = 11
5230 00:25:18.718109
5231 00:25:18.720665 ==
5232 00:25:18.723532 Dram Type= 6, Freq= 0, CH_0, rank 1
5233 00:25:18.727195 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5234 00:25:18.727582 ==
5235 00:25:18.727878 RX Vref Scan: 0
5236 00:25:18.728152
5237 00:25:18.730360 RX Vref 0 -> 0, step: 1
5238 00:25:18.730745
5239 00:25:18.733860 RX Delay -69 -> 252, step: 4
5240 00:25:18.737240 iDelay=199, Bit 0, Center 94 (3 ~ 186) 184
5241 00:25:18.743625 iDelay=199, Bit 1, Center 100 (7 ~ 194) 188
5242 00:25:18.746821 iDelay=199, Bit 2, Center 96 (3 ~ 190) 188
5243 00:25:18.750364 iDelay=199, Bit 3, Center 92 (3 ~ 182) 180
5244 00:25:18.753502 iDelay=199, Bit 4, Center 100 (7 ~ 194) 188
5245 00:25:18.756534 iDelay=199, Bit 5, Center 88 (-5 ~ 182) 188
5246 00:25:18.759995 iDelay=199, Bit 6, Center 104 (15 ~ 194) 180
5247 00:25:18.766367 iDelay=199, Bit 7, Center 106 (15 ~ 198) 184
5248 00:25:18.770091 iDelay=199, Bit 8, Center 76 (-13 ~ 166) 180
5249 00:25:18.773595 iDelay=199, Bit 9, Center 72 (-17 ~ 162) 180
5250 00:25:18.777125 iDelay=199, Bit 10, Center 88 (-5 ~ 182) 188
5251 00:25:18.779826 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176
5252 00:25:18.786284 iDelay=199, Bit 12, Center 94 (7 ~ 182) 176
5253 00:25:18.789700 iDelay=199, Bit 13, Center 92 (-1 ~ 186) 188
5254 00:25:18.793490 iDelay=199, Bit 14, Center 98 (7 ~ 190) 184
5255 00:25:18.796164 iDelay=199, Bit 15, Center 94 (3 ~ 186) 184
5256 00:25:18.796609 ==
5257 00:25:18.799672 Dram Type= 6, Freq= 0, CH_0, rank 1
5258 00:25:18.806450 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5259 00:25:18.806962 ==
5260 00:25:18.807293 DQS Delay:
5261 00:25:18.807599 DQS0 = 0, DQS1 = 0
5262 00:25:18.809646 DQM Delay:
5263 00:25:18.810162 DQM0 = 97, DQM1 = 86
5264 00:25:18.812991 DQ Delay:
5265 00:25:18.816419 DQ0 =94, DQ1 =100, DQ2 =96, DQ3 =92
5266 00:25:18.819518 DQ4 =100, DQ5 =88, DQ6 =104, DQ7 =106
5267 00:25:18.822702 DQ8 =76, DQ9 =72, DQ10 =88, DQ11 =78
5268 00:25:18.826247 DQ12 =94, DQ13 =92, DQ14 =98, DQ15 =94
5269 00:25:18.826675
5270 00:25:18.827000
5271 00:25:18.832896 [DQSOSCAuto] RK1, (LSB)MR18= 0x3131, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
5272 00:25:18.836072 CH0 RK1: MR19=505, MR18=3131
5273 00:25:18.843204 CH0_RK1: MR19=0x505, MR18=0x3131, DQSOSC=406, MR23=63, INC=65, DEC=43
5274 00:25:18.846348 [RxdqsGatingPostProcess] freq 933
5275 00:25:18.849595 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5276 00:25:18.852681 Pre-setting of DQS Precalculation
5277 00:25:18.859276 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5278 00:25:18.859785 ==
5279 00:25:18.862810 Dram Type= 6, Freq= 0, CH_1, rank 0
5280 00:25:18.865721 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5281 00:25:18.866149 ==
5282 00:25:18.872850 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5283 00:25:18.879037 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
5284 00:25:18.882912 [CA 0] Center 37 (7~68) winsize 62
5285 00:25:18.885654 [CA 1] Center 37 (6~68) winsize 63
5286 00:25:18.889068 [CA 2] Center 34 (4~65) winsize 62
5287 00:25:18.891830 [CA 3] Center 34 (3~65) winsize 63
5288 00:25:18.895697 [CA 4] Center 32 (2~63) winsize 62
5289 00:25:18.899068 [CA 5] Center 33 (3~64) winsize 62
5290 00:25:18.899494
5291 00:25:18.902536 [CmdBusTrainingLP45] Vref(ca) range 1: 39
5292 00:25:18.903087
5293 00:25:18.905437 [CATrainingPosCal] consider 1 rank data
5294 00:25:18.909167 u2DelayCellTimex100 = 270/100 ps
5295 00:25:18.912544 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5296 00:25:18.915576 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5297 00:25:18.919328 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5298 00:25:18.922171 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5299 00:25:18.925760 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
5300 00:25:18.928892 CA5 delay=33 (3~64),Diff = 1 PI (6 cell)
5301 00:25:18.929322
5302 00:25:18.935708 CA PerBit enable=1, Macro0, CA PI delay=32
5303 00:25:18.936228
5304 00:25:18.936559 [CBTSetCACLKResult] CA Dly = 32
5305 00:25:18.938972 CS Dly: 5 (0~36)
5306 00:25:18.939533 ==
5307 00:25:18.942010 Dram Type= 6, Freq= 0, CH_1, rank 1
5308 00:25:18.945353 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5309 00:25:18.945781 ==
5310 00:25:18.952006 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5311 00:25:18.958701 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5312 00:25:18.961861 [CA 0] Center 37 (6~68) winsize 63
5313 00:25:18.965912 [CA 1] Center 37 (6~68) winsize 63
5314 00:25:18.969225 [CA 2] Center 34 (4~65) winsize 62
5315 00:25:18.972330 [CA 3] Center 34 (4~65) winsize 62
5316 00:25:18.975261 [CA 4] Center 33 (3~64) winsize 62
5317 00:25:18.979481 [CA 5] Center 33 (2~64) winsize 63
5318 00:25:18.979861
5319 00:25:18.981945 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5320 00:25:18.982463
5321 00:25:18.985356 [CATrainingPosCal] consider 2 rank data
5322 00:25:18.988710 u2DelayCellTimex100 = 270/100 ps
5323 00:25:18.991796 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5324 00:25:18.995006 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5325 00:25:18.998416 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5326 00:25:19.001774 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5327 00:25:19.005235 CA4 delay=33 (3~63),Diff = 0 PI (0 cell)
5328 00:25:19.008290 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5329 00:25:19.008716
5330 00:25:19.014879 CA PerBit enable=1, Macro0, CA PI delay=33
5331 00:25:19.015262
5332 00:25:19.018237 [CBTSetCACLKResult] CA Dly = 33
5333 00:25:19.018723 CS Dly: 5 (0~37)
5334 00:25:19.019030
5335 00:25:19.021831 ----->DramcWriteLeveling(PI) begin...
5336 00:25:19.022383 ==
5337 00:25:19.024766 Dram Type= 6, Freq= 0, CH_1, rank 0
5338 00:25:19.028353 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5339 00:25:19.031485 ==
5340 00:25:19.031868 Write leveling (Byte 0): 23 => 23
5341 00:25:19.034918 Write leveling (Byte 1): 23 => 23
5342 00:25:19.037958 DramcWriteLeveling(PI) end<-----
5343 00:25:19.038509
5344 00:25:19.038931 ==
5345 00:25:19.041265 Dram Type= 6, Freq= 0, CH_1, rank 0
5346 00:25:19.048303 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5347 00:25:19.048684 ==
5348 00:25:19.048978 [Gating] SW mode calibration
5349 00:25:19.058246 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5350 00:25:19.061643 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5351 00:25:19.064631 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5352 00:25:19.071588 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5353 00:25:19.074853 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5354 00:25:19.077894 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5355 00:25:19.084968 0 10 16 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)
5356 00:25:19.088048 0 10 20 | B1->B0 | 3131 2323 | 0 0 | (0 0) (0 0)
5357 00:25:19.091575 0 10 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5358 00:25:19.098128 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5359 00:25:19.101636 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5360 00:25:19.104720 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5361 00:25:19.111103 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5362 00:25:19.114918 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5363 00:25:19.117785 0 11 16 | B1->B0 | 2323 3333 | 0 1 | (0 0) (0 0)
5364 00:25:19.124772 0 11 20 | B1->B0 | 2f2f 4545 | 0 0 | (0 0) (0 0)
5365 00:25:19.127908 0 11 24 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
5366 00:25:19.130850 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5367 00:25:19.137734 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5368 00:25:19.141127 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5369 00:25:19.144066 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5370 00:25:19.151048 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5371 00:25:19.154453 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5372 00:25:19.157641 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5373 00:25:19.164038 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 00:25:19.167763 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 00:25:19.171099 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 00:25:19.177800 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 00:25:19.180617 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 00:25:19.184390 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 00:25:19.190774 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 00:25:19.194388 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 00:25:19.197328 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 00:25:19.204088 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 00:25:19.207363 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 00:25:19.210569 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 00:25:19.217000 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 00:25:19.220141 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 00:25:19.223631 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5388 00:25:19.230157 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5389 00:25:19.230690 Total UI for P1: 0, mck2ui 16
5390 00:25:19.237300 best dqsien dly found for B0: ( 0, 14, 16)
5391 00:25:19.240156 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5392 00:25:19.243978 Total UI for P1: 0, mck2ui 16
5393 00:25:19.246953 best dqsien dly found for B1: ( 0, 14, 18)
5394 00:25:19.250319 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5395 00:25:19.253423 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5396 00:25:19.253931
5397 00:25:19.257068 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5398 00:25:19.260238 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5399 00:25:19.263520 [Gating] SW calibration Done
5400 00:25:19.263951 ==
5401 00:25:19.266799 Dram Type= 6, Freq= 0, CH_1, rank 0
5402 00:25:19.273450 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5403 00:25:19.273967 ==
5404 00:25:19.274353 RX Vref Scan: 0
5405 00:25:19.274668
5406 00:25:19.276915 RX Vref 0 -> 0, step: 1
5407 00:25:19.277339
5408 00:25:19.280134 RX Delay -80 -> 252, step: 8
5409 00:25:19.283877 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5410 00:25:19.286534 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5411 00:25:19.290085 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5412 00:25:19.293889 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5413 00:25:19.299868 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5414 00:25:19.303158 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5415 00:25:19.306672 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5416 00:25:19.309833 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5417 00:25:19.313152 iDelay=208, Bit 8, Center 75 (-16 ~ 167) 184
5418 00:25:19.316830 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5419 00:25:19.323011 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5420 00:25:19.326268 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5421 00:25:19.329393 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5422 00:25:19.332973 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5423 00:25:19.336149 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5424 00:25:19.342579 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5425 00:25:19.343009 ==
5426 00:25:19.345911 Dram Type= 6, Freq= 0, CH_1, rank 0
5427 00:25:19.349370 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5428 00:25:19.349930 ==
5429 00:25:19.350466 DQS Delay:
5430 00:25:19.353012 DQS0 = 0, DQS1 = 0
5431 00:25:19.353447 DQM Delay:
5432 00:25:19.356118 DQM0 = 94, DQM1 = 88
5433 00:25:19.356554 DQ Delay:
5434 00:25:19.359068 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5435 00:25:19.362597 DQ4 =91, DQ5 =107, DQ6 =103, DQ7 =91
5436 00:25:19.365528 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =79
5437 00:25:19.369621 DQ12 =95, DQ13 =99, DQ14 =91, DQ15 =99
5438 00:25:19.370164
5439 00:25:19.370652
5440 00:25:19.371061 ==
5441 00:25:19.372500 Dram Type= 6, Freq= 0, CH_1, rank 0
5442 00:25:19.376149 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5443 00:25:19.376666 ==
5444 00:25:19.379057
5445 00:25:19.379487
5446 00:25:19.379912 TX Vref Scan disable
5447 00:25:19.382519 == TX Byte 0 ==
5448 00:25:19.386009 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5449 00:25:19.389348 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5450 00:25:19.392477 == TX Byte 1 ==
5451 00:25:19.395828 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5452 00:25:19.399158 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5453 00:25:19.399686 ==
5454 00:25:19.402338 Dram Type= 6, Freq= 0, CH_1, rank 0
5455 00:25:19.409779 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5456 00:25:19.410344 ==
5457 00:25:19.410776
5458 00:25:19.411171
5459 00:25:19.412234 TX Vref Scan disable
5460 00:25:19.412626 == TX Byte 0 ==
5461 00:25:19.418756 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5462 00:25:19.422394 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5463 00:25:19.422910 == TX Byte 1 ==
5464 00:25:19.428959 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5465 00:25:19.432509 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5466 00:25:19.433028
5467 00:25:19.433462 [DATLAT]
5468 00:25:19.435368 Freq=933, CH1 RK0
5469 00:25:19.435819
5470 00:25:19.436246 DATLAT Default: 0xd
5471 00:25:19.438740 0, 0xFFFF, sum = 0
5472 00:25:19.439174 1, 0xFFFF, sum = 0
5473 00:25:19.441895 2, 0xFFFF, sum = 0
5474 00:25:19.442420 3, 0xFFFF, sum = 0
5475 00:25:19.445471 4, 0xFFFF, sum = 0
5476 00:25:19.445978 5, 0xFFFF, sum = 0
5477 00:25:19.448623 6, 0xFFFF, sum = 0
5478 00:25:19.449054 7, 0xFFFF, sum = 0
5479 00:25:19.452280 8, 0xFFFF, sum = 0
5480 00:25:19.452794 9, 0xFFFF, sum = 0
5481 00:25:19.455263 10, 0x0, sum = 1
5482 00:25:19.455694 11, 0x0, sum = 2
5483 00:25:19.459270 12, 0x0, sum = 3
5484 00:25:19.459779 13, 0x0, sum = 4
5485 00:25:19.462147 best_step = 11
5486 00:25:19.462604
5487 00:25:19.462927 ==
5488 00:25:19.465098 Dram Type= 6, Freq= 0, CH_1, rank 0
5489 00:25:19.468563 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5490 00:25:19.468991 ==
5491 00:25:19.471717 RX Vref Scan: 1
5492 00:25:19.472182
5493 00:25:19.472514 RX Vref 0 -> 0, step: 1
5494 00:25:19.472818
5495 00:25:19.475090 RX Delay -61 -> 252, step: 4
5496 00:25:19.475513
5497 00:25:19.478595 Set Vref, RX VrefLevel [Byte0]: 54
5498 00:25:19.481549 [Byte1]: 49
5499 00:25:19.485820
5500 00:25:19.486443 Final RX Vref Byte 0 = 54 to rank0
5501 00:25:19.489847 Final RX Vref Byte 1 = 49 to rank0
5502 00:25:19.492228 Final RX Vref Byte 0 = 54 to rank1
5503 00:25:19.496090 Final RX Vref Byte 1 = 49 to rank1==
5504 00:25:19.499261 Dram Type= 6, Freq= 0, CH_1, rank 0
5505 00:25:19.505570 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5506 00:25:19.506081 ==
5507 00:25:19.506453 DQS Delay:
5508 00:25:19.506755 DQS0 = 0, DQS1 = 0
5509 00:25:19.509030 DQM Delay:
5510 00:25:19.509452 DQM0 = 94, DQM1 = 88
5511 00:25:19.512297 DQ Delay:
5512 00:25:19.516026 DQ0 =98, DQ1 =88, DQ2 =86, DQ3 =92
5513 00:25:19.518948 DQ4 =92, DQ5 =104, DQ6 =100, DQ7 =92
5514 00:25:19.522114 DQ8 =70, DQ9 =76, DQ10 =92, DQ11 =80
5515 00:25:19.525480 DQ12 =96, DQ13 =98, DQ14 =96, DQ15 =98
5516 00:25:19.525990
5517 00:25:19.526385
5518 00:25:19.532246 [DQSOSCAuto] RK0, (LSB)MR18= 0x3737, (MSB)MR19= 0x505, tDQSOscB0 = 404 ps tDQSOscB1 = 404 ps
5519 00:25:19.535568 CH1 RK0: MR19=505, MR18=3737
5520 00:25:19.542031 CH1_RK0: MR19=0x505, MR18=0x3737, DQSOSC=404, MR23=63, INC=66, DEC=44
5521 00:25:19.542588
5522 00:25:19.545381 ----->DramcWriteLeveling(PI) begin...
5523 00:25:19.545890 ==
5524 00:25:19.548948 Dram Type= 6, Freq= 0, CH_1, rank 1
5525 00:25:19.551830 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5526 00:25:19.552346 ==
5527 00:25:19.555483 Write leveling (Byte 0): 25 => 25
5528 00:25:19.558593 Write leveling (Byte 1): 26 => 26
5529 00:25:19.562396 DramcWriteLeveling(PI) end<-----
5530 00:25:19.562940
5531 00:25:19.563272 ==
5532 00:25:19.565208 Dram Type= 6, Freq= 0, CH_1, rank 1
5533 00:25:19.568964 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5534 00:25:19.569490 ==
5535 00:25:19.571979 [Gating] SW mode calibration
5536 00:25:19.578765 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5537 00:25:19.585872 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5538 00:25:19.588766 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5539 00:25:19.595041 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5540 00:25:19.598660 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5541 00:25:19.602066 0 10 12 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
5542 00:25:19.608472 0 10 16 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
5543 00:25:19.612023 0 10 20 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (1 0)
5544 00:25:19.615045 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5545 00:25:19.621544 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5546 00:25:19.625028 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5547 00:25:19.628462 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5548 00:25:19.634706 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5549 00:25:19.638266 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5550 00:25:19.641662 0 11 16 | B1->B0 | 2424 3d3d | 0 0 | (0 0) (1 1)
5551 00:25:19.648924 0 11 20 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
5552 00:25:19.651145 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5553 00:25:19.654862 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5554 00:25:19.657968 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5555 00:25:19.664802 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5556 00:25:19.667903 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5557 00:25:19.671232 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5558 00:25:19.677757 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5559 00:25:19.681375 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5560 00:25:19.684611 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5561 00:25:19.690984 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5562 00:25:19.694865 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5563 00:25:19.697613 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5564 00:25:19.704501 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5565 00:25:19.707741 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5566 00:25:19.710660 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5567 00:25:19.717196 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5568 00:25:19.720422 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5569 00:25:19.724021 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5570 00:25:19.730362 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5571 00:25:19.734075 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5572 00:25:19.737478 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5573 00:25:19.743715 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5574 00:25:19.746917 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5575 00:25:19.750279 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5576 00:25:19.756913 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5577 00:25:19.760208 Total UI for P1: 0, mck2ui 16
5578 00:25:19.763514 best dqsien dly found for B0: ( 0, 14, 18)
5579 00:25:19.766798 Total UI for P1: 0, mck2ui 16
5580 00:25:19.770134 best dqsien dly found for B1: ( 0, 14, 20)
5581 00:25:19.773340 best DQS0 dly(MCK, UI, PI) = (0, 14, 18)
5582 00:25:19.776808 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5583 00:25:19.777246
5584 00:25:19.780036 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 18)
5585 00:25:19.783550 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5586 00:25:19.786995 [Gating] SW calibration Done
5587 00:25:19.787440 ==
5588 00:25:19.790308 Dram Type= 6, Freq= 0, CH_1, rank 1
5589 00:25:19.793179 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5590 00:25:19.793567 ==
5591 00:25:19.796588 RX Vref Scan: 0
5592 00:25:19.796975
5593 00:25:19.799742 RX Vref 0 -> 0, step: 1
5594 00:25:19.800129
5595 00:25:19.800512 RX Delay -80 -> 252, step: 8
5596 00:25:19.806825 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5597 00:25:19.810052 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5598 00:25:19.813039 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5599 00:25:19.816750 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5600 00:25:19.819694 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5601 00:25:19.826455 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5602 00:25:19.829507 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5603 00:25:19.832935 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5604 00:25:19.835916 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5605 00:25:19.839369 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5606 00:25:19.842655 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5607 00:25:19.849264 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5608 00:25:19.852777 iDelay=208, Bit 12, Center 95 (-8 ~ 199) 208
5609 00:25:19.855949 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5610 00:25:19.859699 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5611 00:25:19.862754 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5612 00:25:19.865759 ==
5613 00:25:19.866199 Dram Type= 6, Freq= 0, CH_1, rank 1
5614 00:25:19.872552 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5615 00:25:19.872989 ==
5616 00:25:19.873454 DQS Delay:
5617 00:25:19.875654 DQS0 = 0, DQS1 = 0
5618 00:25:19.876093 DQM Delay:
5619 00:25:19.879268 DQM0 = 95, DQM1 = 87
5620 00:25:19.879816 DQ Delay:
5621 00:25:19.882541 DQ0 =99, DQ1 =91, DQ2 =87, DQ3 =91
5622 00:25:19.885316 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =91
5623 00:25:19.888792 DQ8 =75, DQ9 =79, DQ10 =87, DQ11 =79
5624 00:25:19.891934 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5625 00:25:19.892347
5626 00:25:19.892695
5627 00:25:19.892994 ==
5628 00:25:19.895264 Dram Type= 6, Freq= 0, CH_1, rank 1
5629 00:25:19.898660 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5630 00:25:19.899068 ==
5631 00:25:19.899368
5632 00:25:19.899643
5633 00:25:19.902036 TX Vref Scan disable
5634 00:25:19.905975 == TX Byte 0 ==
5635 00:25:19.909063 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5636 00:25:19.912245 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5637 00:25:19.915371 == TX Byte 1 ==
5638 00:25:19.918786 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5639 00:25:19.921829 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5640 00:25:19.922256 ==
5641 00:25:19.925256 Dram Type= 6, Freq= 0, CH_1, rank 1
5642 00:25:19.932052 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5643 00:25:19.932561 ==
5644 00:25:19.932893
5645 00:25:19.933194
5646 00:25:19.933483 TX Vref Scan disable
5647 00:25:19.936601 == TX Byte 0 ==
5648 00:25:19.939242 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5649 00:25:19.945915 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5650 00:25:19.946489 == TX Byte 1 ==
5651 00:25:19.949466 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5652 00:25:19.955698 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5653 00:25:19.956192
5654 00:25:19.956527 [DATLAT]
5655 00:25:19.956836 Freq=933, CH1 RK1
5656 00:25:19.957149
5657 00:25:19.959304 DATLAT Default: 0xb
5658 00:25:19.959734 0, 0xFFFF, sum = 0
5659 00:25:19.962393 1, 0xFFFF, sum = 0
5660 00:25:19.962827 2, 0xFFFF, sum = 0
5661 00:25:19.965667 3, 0xFFFF, sum = 0
5662 00:25:19.968963 4, 0xFFFF, sum = 0
5663 00:25:19.969396 5, 0xFFFF, sum = 0
5664 00:25:19.972402 6, 0xFFFF, sum = 0
5665 00:25:19.972836 7, 0xFFFF, sum = 0
5666 00:25:19.976033 8, 0xFFFF, sum = 0
5667 00:25:19.976553 9, 0xFFFF, sum = 0
5668 00:25:19.978970 10, 0x0, sum = 1
5669 00:25:19.979406 11, 0x0, sum = 2
5670 00:25:19.982452 12, 0x0, sum = 3
5671 00:25:19.982888 13, 0x0, sum = 4
5672 00:25:19.983225 best_step = 11
5673 00:25:19.983526
5674 00:25:19.986599 ==
5675 00:25:19.989948 Dram Type= 6, Freq= 0, CH_1, rank 1
5676 00:25:19.992348 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5677 00:25:19.992780 ==
5678 00:25:19.993109 RX Vref Scan: 0
5679 00:25:19.993478
5680 00:25:19.995743 RX Vref 0 -> 0, step: 1
5681 00:25:19.996168
5682 00:25:19.999168 RX Delay -69 -> 252, step: 4
5683 00:25:20.002487 iDelay=203, Bit 0, Center 98 (7 ~ 190) 184
5684 00:25:20.009105 iDelay=203, Bit 1, Center 90 (-1 ~ 182) 184
5685 00:25:20.012660 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5686 00:25:20.015590 iDelay=203, Bit 3, Center 92 (-1 ~ 186) 188
5687 00:25:20.019209 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5688 00:25:20.022585 iDelay=203, Bit 5, Center 106 (11 ~ 202) 192
5689 00:25:20.025839 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5690 00:25:20.032629 iDelay=203, Bit 7, Center 92 (-1 ~ 186) 188
5691 00:25:20.035661 iDelay=203, Bit 8, Center 74 (-17 ~ 166) 184
5692 00:25:20.039072 iDelay=203, Bit 9, Center 74 (-17 ~ 166) 184
5693 00:25:20.042831 iDelay=203, Bit 10, Center 86 (-5 ~ 178) 184
5694 00:25:20.045659 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5695 00:25:20.052699 iDelay=203, Bit 12, Center 98 (7 ~ 190) 184
5696 00:25:20.055243 iDelay=203, Bit 13, Center 96 (7 ~ 186) 180
5697 00:25:20.058743 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5698 00:25:20.062823 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5699 00:25:20.063372 ==
5700 00:25:20.065425 Dram Type= 6, Freq= 0, CH_1, rank 1
5701 00:25:20.068540 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5702 00:25:20.071892 ==
5703 00:25:20.072401 DQS Delay:
5704 00:25:20.072736 DQS0 = 0, DQS1 = 0
5705 00:25:20.074967 DQM Delay:
5706 00:25:20.075396 DQM0 = 95, DQM1 = 87
5707 00:25:20.078911 DQ Delay:
5708 00:25:20.081903 DQ0 =98, DQ1 =90, DQ2 =88, DQ3 =92
5709 00:25:20.082527 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =92
5710 00:25:20.085375 DQ8 =74, DQ9 =74, DQ10 =86, DQ11 =80
5711 00:25:20.092008 DQ12 =98, DQ13 =96, DQ14 =96, DQ15 =96
5712 00:25:20.092627
5713 00:25:20.092975
5714 00:25:20.098839 [DQSOSCAuto] RK1, (LSB)MR18= 0x2222, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 411 ps
5715 00:25:20.101798 CH1 RK1: MR19=505, MR18=2222
5716 00:25:20.108662 CH1_RK1: MR19=0x505, MR18=0x2222, DQSOSC=411, MR23=63, INC=64, DEC=42
5717 00:25:20.112162 [RxdqsGatingPostProcess] freq 933
5718 00:25:20.115404 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5719 00:25:20.118340 Pre-setting of DQS Precalculation
5720 00:25:20.124990 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5721 00:25:20.131416 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5722 00:25:20.138249 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5723 00:25:20.138778
5724 00:25:20.139110
5725 00:25:20.141677 [Calibration Summary] 1866 Mbps
5726 00:25:20.142186 CH 0, Rank 0
5727 00:25:20.145254 SW Impedance : PASS
5728 00:25:20.148703 DUTY Scan : NO K
5729 00:25:20.149212 ZQ Calibration : PASS
5730 00:25:20.151395 Jitter Meter : NO K
5731 00:25:20.154894 CBT Training : PASS
5732 00:25:20.155324 Write leveling : PASS
5733 00:25:20.157962 RX DQS gating : PASS
5734 00:25:20.161740 RX DQ/DQS(RDDQC) : PASS
5735 00:25:20.162292 TX DQ/DQS : PASS
5736 00:25:20.164475 RX DATLAT : PASS
5737 00:25:20.167906 RX DQ/DQS(Engine): PASS
5738 00:25:20.168357 TX OE : NO K
5739 00:25:20.168725 All Pass.
5740 00:25:20.171543
5741 00:25:20.172086 CH 0, Rank 1
5742 00:25:20.174691 SW Impedance : PASS
5743 00:25:20.175120 DUTY Scan : NO K
5744 00:25:20.178179 ZQ Calibration : PASS
5745 00:25:20.178654 Jitter Meter : NO K
5746 00:25:20.181125 CBT Training : PASS
5747 00:25:20.184580 Write leveling : PASS
5748 00:25:20.185007 RX DQS gating : PASS
5749 00:25:20.187602 RX DQ/DQS(RDDQC) : PASS
5750 00:25:20.190900 TX DQ/DQS : PASS
5751 00:25:20.191337 RX DATLAT : PASS
5752 00:25:20.194267 RX DQ/DQS(Engine): PASS
5753 00:25:20.197962 TX OE : NO K
5754 00:25:20.198531 All Pass.
5755 00:25:20.198874
5756 00:25:20.199182 CH 1, Rank 0
5757 00:25:20.201244 SW Impedance : PASS
5758 00:25:20.204530 DUTY Scan : NO K
5759 00:25:20.205054 ZQ Calibration : PASS
5760 00:25:20.207765 Jitter Meter : NO K
5761 00:25:20.211017 CBT Training : PASS
5762 00:25:20.211534 Write leveling : PASS
5763 00:25:20.214036 RX DQS gating : PASS
5764 00:25:20.217412 RX DQ/DQS(RDDQC) : PASS
5765 00:25:20.217841 TX DQ/DQS : PASS
5766 00:25:20.220766 RX DATLAT : PASS
5767 00:25:20.224353 RX DQ/DQS(Engine): PASS
5768 00:25:20.224784 TX OE : NO K
5769 00:25:20.227419 All Pass.
5770 00:25:20.227847
5771 00:25:20.228175 CH 1, Rank 1
5772 00:25:20.230823 SW Impedance : PASS
5773 00:25:20.231255 DUTY Scan : NO K
5774 00:25:20.234131 ZQ Calibration : PASS
5775 00:25:20.237698 Jitter Meter : NO K
5776 00:25:20.238257 CBT Training : PASS
5777 00:25:20.241093 Write leveling : PASS
5778 00:25:20.241609 RX DQS gating : PASS
5779 00:25:20.244124 RX DQ/DQS(RDDQC) : PASS
5780 00:25:20.247859 TX DQ/DQS : PASS
5781 00:25:20.248372 RX DATLAT : PASS
5782 00:25:20.250795 RX DQ/DQS(Engine): PASS
5783 00:25:20.254642 TX OE : NO K
5784 00:25:20.255158 All Pass.
5785 00:25:20.255493
5786 00:25:20.257641 DramC Write-DBI off
5787 00:25:20.258071 PER_BANK_REFRESH: Hybrid Mode
5788 00:25:20.260864 TX_TRACKING: ON
5789 00:25:20.267299 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5790 00:25:20.274154 [FAST_K] Save calibration result to emmc
5791 00:25:20.277682 dramc_set_vcore_voltage set vcore to 650000
5792 00:25:20.278193 Read voltage for 400, 6
5793 00:25:20.281069 Vio18 = 0
5794 00:25:20.281513 Vcore = 650000
5795 00:25:20.281847 Vdram = 0
5796 00:25:20.283864 Vddq = 0
5797 00:25:20.284298 Vmddr = 0
5798 00:25:20.287561 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5799 00:25:20.293891 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5800 00:25:20.297513 MEM_TYPE=3, freq_sel=20
5801 00:25:20.301194 sv_algorithm_assistance_LP4_800
5802 00:25:20.303734 ============ PULL DRAM RESETB DOWN ============
5803 00:25:20.306858 ========== PULL DRAM RESETB DOWN end =========
5804 00:25:20.313752 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5805 00:25:20.317406 ===================================
5806 00:25:20.317918 LPDDR4 DRAM CONFIGURATION
5807 00:25:20.320510 ===================================
5808 00:25:20.323655 EX_ROW_EN[0] = 0x0
5809 00:25:20.324283 EX_ROW_EN[1] = 0x0
5810 00:25:20.327088 LP4Y_EN = 0x0
5811 00:25:20.327522 WORK_FSP = 0x0
5812 00:25:20.330400 WL = 0x2
5813 00:25:20.330832 RL = 0x2
5814 00:25:20.333891 BL = 0x2
5815 00:25:20.337693 RPST = 0x0
5816 00:25:20.338208 RD_PRE = 0x0
5817 00:25:20.340493 WR_PRE = 0x1
5818 00:25:20.340926 WR_PST = 0x0
5819 00:25:20.343998 DBI_WR = 0x0
5820 00:25:20.344426 DBI_RD = 0x0
5821 00:25:20.346911 OTF = 0x1
5822 00:25:20.350513 ===================================
5823 00:25:20.354066 ===================================
5824 00:25:20.354621 ANA top config
5825 00:25:20.356971 ===================================
5826 00:25:20.360528 DLL_ASYNC_EN = 0
5827 00:25:20.363916 ALL_SLAVE_EN = 1
5828 00:25:20.364433 NEW_RANK_MODE = 1
5829 00:25:20.366870 DLL_IDLE_MODE = 1
5830 00:25:20.370435 LP45_APHY_COMB_EN = 1
5831 00:25:20.373970 TX_ODT_DIS = 1
5832 00:25:20.374532 NEW_8X_MODE = 1
5833 00:25:20.376576 ===================================
5834 00:25:20.380325 ===================================
5835 00:25:20.383713 data_rate = 800
5836 00:25:20.386591 CKR = 1
5837 00:25:20.390869 DQ_P2S_RATIO = 4
5838 00:25:20.393910 ===================================
5839 00:25:20.396659 CA_P2S_RATIO = 4
5840 00:25:20.399982 DQ_CA_OPEN = 0
5841 00:25:20.403650 DQ_SEMI_OPEN = 1
5842 00:25:20.404162 CA_SEMI_OPEN = 1
5843 00:25:20.406612 CA_FULL_RATE = 0
5844 00:25:20.410076 DQ_CKDIV4_EN = 0
5845 00:25:20.413181 CA_CKDIV4_EN = 1
5846 00:25:20.416319 CA_PREDIV_EN = 0
5847 00:25:20.419573 PH8_DLY = 0
5848 00:25:20.420004 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5849 00:25:20.422852 DQ_AAMCK_DIV = 0
5850 00:25:20.426472 CA_AAMCK_DIV = 0
5851 00:25:20.429824 CA_ADMCK_DIV = 4
5852 00:25:20.433075 DQ_TRACK_CA_EN = 0
5853 00:25:20.436388 CA_PICK = 800
5854 00:25:20.436904 CA_MCKIO = 400
5855 00:25:20.439651 MCKIO_SEMI = 400
5856 00:25:20.442976 PLL_FREQ = 3016
5857 00:25:20.446123 DQ_UI_PI_RATIO = 32
5858 00:25:20.449451 CA_UI_PI_RATIO = 32
5859 00:25:20.453458 ===================================
5860 00:25:20.456400 ===================================
5861 00:25:20.459735 memory_type:LPDDR4
5862 00:25:20.460245 GP_NUM : 10
5863 00:25:20.463162 SRAM_EN : 1
5864 00:25:20.466372 MD32_EN : 0
5865 00:25:20.469248 ===================================
5866 00:25:20.469678 [ANA_INIT] >>>>>>>>>>>>>>
5867 00:25:20.473015 <<<<<< [CONFIGURE PHASE]: ANA_TX
5868 00:25:20.476302 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5869 00:25:20.479109 ===================================
5870 00:25:20.482432 data_rate = 800,PCW = 0X7400
5871 00:25:20.485824 ===================================
5872 00:25:20.489522 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5873 00:25:20.496029 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5874 00:25:20.505900 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5875 00:25:20.509580 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5876 00:25:20.516027 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5877 00:25:20.519481 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5878 00:25:20.519992 [ANA_INIT] flow start
5879 00:25:20.522911 [ANA_INIT] PLL >>>>>>>>
5880 00:25:20.526523 [ANA_INIT] PLL <<<<<<<<
5881 00:25:20.526956 [ANA_INIT] MIDPI >>>>>>>>
5882 00:25:20.529059 [ANA_INIT] MIDPI <<<<<<<<
5883 00:25:20.532650 [ANA_INIT] DLL >>>>>>>>
5884 00:25:20.533078 [ANA_INIT] flow end
5885 00:25:20.536054 ============ LP4 DIFF to SE enter ============
5886 00:25:20.542527 ============ LP4 DIFF to SE exit ============
5887 00:25:20.543026 [ANA_INIT] <<<<<<<<<<<<<
5888 00:25:20.545871 [Flow] Enable top DCM control >>>>>
5889 00:25:20.549437 [Flow] Enable top DCM control <<<<<
5890 00:25:20.552307 Enable DLL master slave shuffle
5891 00:25:20.559333 ==============================================================
5892 00:25:20.559765 Gating Mode config
5893 00:25:20.565982 ==============================================================
5894 00:25:20.568791 Config description:
5895 00:25:20.578944 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5896 00:25:20.585694 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5897 00:25:20.589322 SELPH_MODE 0: By rank 1: By Phase
5898 00:25:20.595584 ==============================================================
5899 00:25:20.598813 GAT_TRACK_EN = 0
5900 00:25:20.602800 RX_GATING_MODE = 2
5901 00:25:20.605413 RX_GATING_TRACK_MODE = 2
5902 00:25:20.605924 SELPH_MODE = 1
5903 00:25:20.608789 PICG_EARLY_EN = 1
5904 00:25:20.612039 VALID_LAT_VALUE = 1
5905 00:25:20.618930 ==============================================================
5906 00:25:20.622085 Enter into Gating configuration >>>>
5907 00:25:20.625140 Exit from Gating configuration <<<<
5908 00:25:20.628456 Enter into DVFS_PRE_config >>>>>
5909 00:25:20.638459 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5910 00:25:20.641959 Exit from DVFS_PRE_config <<<<<
5911 00:25:20.645336 Enter into PICG configuration >>>>
5912 00:25:20.648666 Exit from PICG configuration <<<<
5913 00:25:20.652235 [RX_INPUT] configuration >>>>>
5914 00:25:20.655462 [RX_INPUT] configuration <<<<<
5915 00:25:20.658318 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5916 00:25:20.664809 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5917 00:25:20.671925 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5918 00:25:20.678028 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5919 00:25:20.681147 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5920 00:25:20.687743 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5921 00:25:20.691565 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5922 00:25:20.697712 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5923 00:25:20.701700 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5924 00:25:20.704518 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5925 00:25:20.707831 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5926 00:25:20.714593 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5927 00:25:20.717693 ===================================
5928 00:25:20.720881 LPDDR4 DRAM CONFIGURATION
5929 00:25:20.724407 ===================================
5930 00:25:20.724664 EX_ROW_EN[0] = 0x0
5931 00:25:20.727923 EX_ROW_EN[1] = 0x0
5932 00:25:20.728252 LP4Y_EN = 0x0
5933 00:25:20.731342 WORK_FSP = 0x0
5934 00:25:20.731673 WL = 0x2
5935 00:25:20.734601 RL = 0x2
5936 00:25:20.735028 BL = 0x2
5937 00:25:20.737998 RPST = 0x0
5938 00:25:20.738567 RD_PRE = 0x0
5939 00:25:20.741146 WR_PRE = 0x1
5940 00:25:20.741592 WR_PST = 0x0
5941 00:25:20.744732 DBI_WR = 0x0
5942 00:25:20.745241 DBI_RD = 0x0
5943 00:25:20.747933 OTF = 0x1
5944 00:25:20.750954 ===================================
5945 00:25:20.754314 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5946 00:25:20.757942 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5947 00:25:20.764158 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5948 00:25:20.767414 ===================================
5949 00:25:20.767990 LPDDR4 DRAM CONFIGURATION
5950 00:25:20.771108 ===================================
5951 00:25:20.774074 EX_ROW_EN[0] = 0x10
5952 00:25:20.777339 EX_ROW_EN[1] = 0x0
5953 00:25:20.777815 LP4Y_EN = 0x0
5954 00:25:20.781136 WORK_FSP = 0x0
5955 00:25:20.781566 WL = 0x2
5956 00:25:20.784172 RL = 0x2
5957 00:25:20.784705 BL = 0x2
5958 00:25:20.787651 RPST = 0x0
5959 00:25:20.788081 RD_PRE = 0x0
5960 00:25:20.790873 WR_PRE = 0x1
5961 00:25:20.791315 WR_PST = 0x0
5962 00:25:20.794507 DBI_WR = 0x0
5963 00:25:20.795018 DBI_RD = 0x0
5964 00:25:20.797564 OTF = 0x1
5965 00:25:20.800735 ===================================
5966 00:25:20.807297 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5967 00:25:20.810544 nWR fixed to 30
5968 00:25:20.814492 [ModeRegInit_LP4] CH0 RK0
5969 00:25:20.815041 [ModeRegInit_LP4] CH0 RK1
5970 00:25:20.817329 [ModeRegInit_LP4] CH1 RK0
5971 00:25:20.820806 [ModeRegInit_LP4] CH1 RK1
5972 00:25:20.821220 match AC timing 18
5973 00:25:20.827012 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
5974 00:25:20.830465 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5975 00:25:20.834121 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
5976 00:25:20.840855 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
5977 00:25:20.844121 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
5978 00:25:20.844631 ==
5979 00:25:20.847036 Dram Type= 6, Freq= 0, CH_0, rank 0
5980 00:25:20.850579 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
5981 00:25:20.851094 ==
5982 00:25:20.856969 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
5983 00:25:20.863614 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5984 00:25:20.866926 [CA 0] Center 36 (8~64) winsize 57
5985 00:25:20.870173 [CA 1] Center 36 (8~64) winsize 57
5986 00:25:20.873780 [CA 2] Center 36 (8~64) winsize 57
5987 00:25:20.876924 [CA 3] Center 36 (8~64) winsize 57
5988 00:25:20.880144 [CA 4] Center 36 (8~64) winsize 57
5989 00:25:20.880662 [CA 5] Center 36 (8~64) winsize 57
5990 00:25:20.883237
5991 00:25:20.886535 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5992 00:25:20.886962
5993 00:25:20.890410 [CATrainingPosCal] consider 1 rank data
5994 00:25:20.893127 u2DelayCellTimex100 = 270/100 ps
5995 00:25:20.896784 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
5996 00:25:20.899881 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
5997 00:25:20.903539 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
5998 00:25:20.906609 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
5999 00:25:20.909724 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6000 00:25:20.912773 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6001 00:25:20.913201
6002 00:25:20.916079 CA PerBit enable=1, Macro0, CA PI delay=36
6003 00:25:20.919494
6004 00:25:20.919997 [CBTSetCACLKResult] CA Dly = 36
6005 00:25:20.923102 CS Dly: 1 (0~32)
6006 00:25:20.923534 ==
6007 00:25:20.926190 Dram Type= 6, Freq= 0, CH_0, rank 1
6008 00:25:20.929534 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6009 00:25:20.929972 ==
6010 00:25:20.936337 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6011 00:25:20.942702 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6012 00:25:20.945847 [CA 0] Center 36 (8~64) winsize 57
6013 00:25:20.949298 [CA 1] Center 36 (8~64) winsize 57
6014 00:25:20.949726 [CA 2] Center 36 (8~64) winsize 57
6015 00:25:20.952779 [CA 3] Center 36 (8~64) winsize 57
6016 00:25:20.955750 [CA 4] Center 36 (8~64) winsize 57
6017 00:25:20.959402 [CA 5] Center 36 (8~64) winsize 57
6018 00:25:20.959860
6019 00:25:20.962589 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6020 00:25:20.965508
6021 00:25:20.968989 [CATrainingPosCal] consider 2 rank data
6022 00:25:20.969420 u2DelayCellTimex100 = 270/100 ps
6023 00:25:20.975652 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6024 00:25:20.979135 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6025 00:25:20.982330 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6026 00:25:20.985519 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6027 00:25:20.988825 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6028 00:25:20.992277 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6029 00:25:20.992705
6030 00:25:20.995547 CA PerBit enable=1, Macro0, CA PI delay=36
6031 00:25:20.996061
6032 00:25:20.999266 [CBTSetCACLKResult] CA Dly = 36
6033 00:25:21.002763 CS Dly: 1 (0~32)
6034 00:25:21.003252
6035 00:25:21.005463 ----->DramcWriteLeveling(PI) begin...
6036 00:25:21.005892 ==
6037 00:25:21.009004 Dram Type= 6, Freq= 0, CH_0, rank 0
6038 00:25:21.012121 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6039 00:25:21.012548 ==
6040 00:25:21.015434 Write leveling (Byte 0): 32 => 0
6041 00:25:21.018594 Write leveling (Byte 1): 32 => 0
6042 00:25:21.021924 DramcWriteLeveling(PI) end<-----
6043 00:25:21.022384
6044 00:25:21.022714 ==
6045 00:25:21.024958 Dram Type= 6, Freq= 0, CH_0, rank 0
6046 00:25:21.028659 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6047 00:25:21.029092 ==
6048 00:25:21.031818 [Gating] SW mode calibration
6049 00:25:21.038595 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6050 00:25:21.045195 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6051 00:25:21.048859 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6052 00:25:21.051889 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6053 00:25:21.058687 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6054 00:25:21.062126 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6055 00:25:21.065245 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6056 00:25:21.072280 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6057 00:25:21.074776 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6058 00:25:21.078510 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6059 00:25:21.084693 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6060 00:25:21.088270 Total UI for P1: 0, mck2ui 16
6061 00:25:21.091546 best dqsien dly found for B0: ( 0, 10, 16)
6062 00:25:21.091990 Total UI for P1: 0, mck2ui 16
6063 00:25:21.097930 best dqsien dly found for B1: ( 0, 10, 16)
6064 00:25:21.101219 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6065 00:25:21.105204 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6066 00:25:21.105633
6067 00:25:21.108117 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6068 00:25:21.111555 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6069 00:25:21.114517 [Gating] SW calibration Done
6070 00:25:21.114944 ==
6071 00:25:21.118018 Dram Type= 6, Freq= 0, CH_0, rank 0
6072 00:25:21.121619 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6073 00:25:21.122304 ==
6074 00:25:21.124528 RX Vref Scan: 0
6075 00:25:21.124953
6076 00:25:21.125277 RX Vref 0 -> 0, step: 1
6077 00:25:21.127885
6078 00:25:21.128506 RX Delay -410 -> 252, step: 16
6079 00:25:21.134394 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6080 00:25:21.137817 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6081 00:25:21.141076 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6082 00:25:21.144855 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6083 00:25:21.151089 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6084 00:25:21.154351 iDelay=230, Bit 5, Center -51 (-298 ~ 197) 496
6085 00:25:21.158043 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6086 00:25:21.164485 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6087 00:25:21.167425 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6088 00:25:21.170795 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6089 00:25:21.174934 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6090 00:25:21.181110 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6091 00:25:21.183910 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6092 00:25:21.187490 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6093 00:25:21.190379 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6094 00:25:21.197043 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6095 00:25:21.197491 ==
6096 00:25:21.200448 Dram Type= 6, Freq= 0, CH_0, rank 0
6097 00:25:21.203774 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6098 00:25:21.204334 ==
6099 00:25:21.204967 DQS Delay:
6100 00:25:21.206941 DQS0 = 51, DQS1 = 59
6101 00:25:21.207365 DQM Delay:
6102 00:25:21.210450 DQM0 = 12, DQM1 = 16
6103 00:25:21.210935 DQ Delay:
6104 00:25:21.214019 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6105 00:25:21.216926 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6106 00:25:21.221162 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6107 00:25:21.223758 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6108 00:25:21.224212
6109 00:25:21.224561
6110 00:25:21.224869 ==
6111 00:25:21.226928 Dram Type= 6, Freq= 0, CH_0, rank 0
6112 00:25:21.230279 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6113 00:25:21.230732 ==
6114 00:25:21.231069
6115 00:25:21.231367
6116 00:25:21.233648 TX Vref Scan disable
6117 00:25:21.237027 == TX Byte 0 ==
6118 00:25:21.240345 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6119 00:25:21.243430 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6120 00:25:21.246660 == TX Byte 1 ==
6121 00:25:21.250315 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6122 00:25:21.253374 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6123 00:25:21.253803 ==
6124 00:25:21.256679 Dram Type= 6, Freq= 0, CH_0, rank 0
6125 00:25:21.263810 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6126 00:25:21.264241 ==
6127 00:25:21.264571
6128 00:25:21.264874
6129 00:25:21.265161 TX Vref Scan disable
6130 00:25:21.266705 == TX Byte 0 ==
6131 00:25:21.269908 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6132 00:25:21.273673 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6133 00:25:21.276804 == TX Byte 1 ==
6134 00:25:21.279682 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6135 00:25:21.283255 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6136 00:25:21.283681
6137 00:25:21.286817 [DATLAT]
6138 00:25:21.287345 Freq=400, CH0 RK0
6139 00:25:21.287679
6140 00:25:21.290191 DATLAT Default: 0xf
6141 00:25:21.290736 0, 0xFFFF, sum = 0
6142 00:25:21.293297 1, 0xFFFF, sum = 0
6143 00:25:21.293810 2, 0xFFFF, sum = 0
6144 00:25:21.296612 3, 0xFFFF, sum = 0
6145 00:25:21.297132 4, 0xFFFF, sum = 0
6146 00:25:21.299654 5, 0xFFFF, sum = 0
6147 00:25:21.300170 6, 0xFFFF, sum = 0
6148 00:25:21.302874 7, 0xFFFF, sum = 0
6149 00:25:21.303306 8, 0xFFFF, sum = 0
6150 00:25:21.306142 9, 0xFFFF, sum = 0
6151 00:25:21.309744 10, 0xFFFF, sum = 0
6152 00:25:21.310302 11, 0xFFFF, sum = 0
6153 00:25:21.313146 12, 0x0, sum = 1
6154 00:25:21.313658 13, 0x0, sum = 2
6155 00:25:21.315989 14, 0x0, sum = 3
6156 00:25:21.316501 15, 0x0, sum = 4
6157 00:25:21.316838 best_step = 13
6158 00:25:21.319203
6159 00:25:21.319629 ==
6160 00:25:21.322725 Dram Type= 6, Freq= 0, CH_0, rank 0
6161 00:25:21.326015 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6162 00:25:21.326480 ==
6163 00:25:21.326813 RX Vref Scan: 1
6164 00:25:21.327131
6165 00:25:21.329260 RX Vref 0 -> 0, step: 1
6166 00:25:21.329684
6167 00:25:21.332600 RX Delay -359 -> 252, step: 8
6168 00:25:21.333106
6169 00:25:21.335634 Set Vref, RX VrefLevel [Byte0]: 46
6170 00:25:21.338823 [Byte1]: 49
6171 00:25:21.342816
6172 00:25:21.343242 Final RX Vref Byte 0 = 46 to rank0
6173 00:25:21.346242 Final RX Vref Byte 1 = 49 to rank0
6174 00:25:21.349997 Final RX Vref Byte 0 = 46 to rank1
6175 00:25:21.353229 Final RX Vref Byte 1 = 49 to rank1==
6176 00:25:21.356533 Dram Type= 6, Freq= 0, CH_0, rank 0
6177 00:25:21.363036 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6178 00:25:21.363544 ==
6179 00:25:21.363879 DQS Delay:
6180 00:25:21.366360 DQS0 = 52, DQS1 = 68
6181 00:25:21.366806 DQM Delay:
6182 00:25:21.367174 DQM0 = 8, DQM1 = 17
6183 00:25:21.369607 DQ Delay:
6184 00:25:21.372930 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =4
6185 00:25:21.373357 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6186 00:25:21.376404 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6187 00:25:21.379910 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =28
6188 00:25:21.380414
6189 00:25:21.380747
6190 00:25:21.389720 [DQSOSCAuto] RK0, (LSB)MR18= 0xa0a0, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
6191 00:25:21.393041 CH0 RK0: MR19=C0C, MR18=A0A0
6192 00:25:21.399425 CH0_RK0: MR19=0xC0C, MR18=0xA0A0, DQSOSC=389, MR23=63, INC=390, DEC=260
6193 00:25:21.399935 ==
6194 00:25:21.402797 Dram Type= 6, Freq= 0, CH_0, rank 1
6195 00:25:21.406127 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6196 00:25:21.406598 ==
6197 00:25:21.409591 [Gating] SW mode calibration
6198 00:25:21.416344 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6199 00:25:21.422715 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6200 00:25:21.425683 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6201 00:25:21.429176 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6202 00:25:21.432628 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6203 00:25:21.438791 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6204 00:25:21.442188 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6205 00:25:21.445430 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6206 00:25:21.452385 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6207 00:25:21.455430 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6208 00:25:21.458842 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6209 00:25:21.461914 Total UI for P1: 0, mck2ui 16
6210 00:25:21.465439 best dqsien dly found for B0: ( 0, 10, 16)
6211 00:25:21.468559 Total UI for P1: 0, mck2ui 16
6212 00:25:21.472295 best dqsien dly found for B1: ( 0, 10, 16)
6213 00:25:21.475272 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6214 00:25:21.481947 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6215 00:25:21.482570
6216 00:25:21.485208 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6217 00:25:21.488550 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6218 00:25:21.492579 [Gating] SW calibration Done
6219 00:25:21.493008 ==
6220 00:25:21.495637 Dram Type= 6, Freq= 0, CH_0, rank 1
6221 00:25:21.498862 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6222 00:25:21.499293 ==
6223 00:25:21.502097 RX Vref Scan: 0
6224 00:25:21.502659
6225 00:25:21.502996 RX Vref 0 -> 0, step: 1
6226 00:25:21.503302
6227 00:25:21.505647 RX Delay -410 -> 252, step: 16
6228 00:25:21.512185 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6229 00:25:21.515816 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6230 00:25:21.518634 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6231 00:25:21.521785 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6232 00:25:21.525458 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6233 00:25:21.531586 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6234 00:25:21.535360 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6235 00:25:21.538431 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6236 00:25:21.541919 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6237 00:25:21.548759 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6238 00:25:21.551956 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6239 00:25:21.554806 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6240 00:25:21.562169 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6241 00:25:21.564827 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6242 00:25:21.568138 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6243 00:25:21.571486 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6244 00:25:21.571941 ==
6245 00:25:21.574743 Dram Type= 6, Freq= 0, CH_0, rank 1
6246 00:25:21.581370 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6247 00:25:21.581808 ==
6248 00:25:21.582188 DQS Delay:
6249 00:25:21.584710 DQS0 = 43, DQS1 = 59
6250 00:25:21.585180 DQM Delay:
6251 00:25:21.588120 DQM0 = 7, DQM1 = 16
6252 00:25:21.588554 DQ Delay:
6253 00:25:21.591562 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6254 00:25:21.595043 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6255 00:25:21.595474 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6256 00:25:21.598167 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6257 00:25:21.601245
6258 00:25:21.601773
6259 00:25:21.602107 ==
6260 00:25:21.604849 Dram Type= 6, Freq= 0, CH_0, rank 1
6261 00:25:21.607984 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6262 00:25:21.608414 ==
6263 00:25:21.608803
6264 00:25:21.609111
6265 00:25:21.611664 TX Vref Scan disable
6266 00:25:21.612170 == TX Byte 0 ==
6267 00:25:21.614984 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6268 00:25:21.621411 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6269 00:25:21.621918 == TX Byte 1 ==
6270 00:25:21.625106 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6271 00:25:21.631076 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6272 00:25:21.631503 ==
6273 00:25:21.634672 Dram Type= 6, Freq= 0, CH_0, rank 1
6274 00:25:21.638513 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6275 00:25:21.638995 ==
6276 00:25:21.639429
6277 00:25:21.639798
6278 00:25:21.640961 TX Vref Scan disable
6279 00:25:21.641550 == TX Byte 0 ==
6280 00:25:21.644864 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6281 00:25:21.650954 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6282 00:25:21.651485 == TX Byte 1 ==
6283 00:25:21.655174 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6284 00:25:21.661107 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6285 00:25:21.661643
6286 00:25:21.662103 [DATLAT]
6287 00:25:21.664283 Freq=400, CH0 RK1
6288 00:25:21.664822
6289 00:25:21.665282 DATLAT Default: 0xd
6290 00:25:21.667631 0, 0xFFFF, sum = 0
6291 00:25:21.668183 1, 0xFFFF, sum = 0
6292 00:25:21.671297 2, 0xFFFF, sum = 0
6293 00:25:21.671848 3, 0xFFFF, sum = 0
6294 00:25:21.674569 4, 0xFFFF, sum = 0
6295 00:25:21.675056 5, 0xFFFF, sum = 0
6296 00:25:21.677736 6, 0xFFFF, sum = 0
6297 00:25:21.678439 7, 0xFFFF, sum = 0
6298 00:25:21.681119 8, 0xFFFF, sum = 0
6299 00:25:21.681562 9, 0xFFFF, sum = 0
6300 00:25:21.684095 10, 0xFFFF, sum = 0
6301 00:25:21.684649 11, 0xFFFF, sum = 0
6302 00:25:21.687584 12, 0x0, sum = 1
6303 00:25:21.688127 13, 0x0, sum = 2
6304 00:25:21.691064 14, 0x0, sum = 3
6305 00:25:21.691480 15, 0x0, sum = 4
6306 00:25:21.694438 best_step = 13
6307 00:25:21.694818
6308 00:25:21.695107 ==
6309 00:25:21.697489 Dram Type= 6, Freq= 0, CH_0, rank 1
6310 00:25:21.701170 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6311 00:25:21.701555 ==
6312 00:25:21.704202 RX Vref Scan: 0
6313 00:25:21.704729
6314 00:25:21.705207 RX Vref 0 -> 0, step: 1
6315 00:25:21.705591
6316 00:25:21.707737 RX Delay -359 -> 252, step: 8
6317 00:25:21.715947 iDelay=217, Bit 0, Center -48 (-295 ~ 200) 496
6318 00:25:21.718593 iDelay=217, Bit 1, Center -40 (-295 ~ 216) 512
6319 00:25:21.722081 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6320 00:25:21.725215 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6321 00:25:21.731972 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6322 00:25:21.735369 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6323 00:25:21.738371 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6324 00:25:21.741834 iDelay=217, Bit 7, Center -32 (-279 ~ 216) 496
6325 00:25:21.748783 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6326 00:25:21.751920 iDelay=217, Bit 9, Center -64 (-311 ~ 184) 496
6327 00:25:21.755232 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6328 00:25:21.761470 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6329 00:25:21.764929 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6330 00:25:21.768284 iDelay=217, Bit 13, Center -48 (-295 ~ 200) 496
6331 00:25:21.771497 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6332 00:25:21.778550 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6333 00:25:21.778934 ==
6334 00:25:21.781440 Dram Type= 6, Freq= 0, CH_0, rank 1
6335 00:25:21.784743 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6336 00:25:21.785160 ==
6337 00:25:21.785456 DQS Delay:
6338 00:25:21.788293 DQS0 = 52, DQS1 = 64
6339 00:25:21.788674 DQM Delay:
6340 00:25:21.791857 DQM0 = 9, DQM1 = 13
6341 00:25:21.792241 DQ Delay:
6342 00:25:21.795043 DQ0 =4, DQ1 =12, DQ2 =8, DQ3 =4
6343 00:25:21.798363 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6344 00:25:21.801209 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6345 00:25:21.804746 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =24
6346 00:25:21.805128
6347 00:25:21.805419
6348 00:25:21.811234 [DQSOSCAuto] RK1, (LSB)MR18= 0xc8c8, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 385 ps
6349 00:25:21.814692 CH0 RK1: MR19=C0C, MR18=C8C8
6350 00:25:21.821203 CH0_RK1: MR19=0xC0C, MR18=0xC8C8, DQSOSC=385, MR23=63, INC=398, DEC=265
6351 00:25:21.825152 [RxdqsGatingPostProcess] freq 400
6352 00:25:21.831499 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6353 00:25:21.834459 Pre-setting of DQS Precalculation
6354 00:25:21.837743 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6355 00:25:21.838241 ==
6356 00:25:21.840877 Dram Type= 6, Freq= 0, CH_1, rank 0
6357 00:25:21.844344 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6358 00:25:21.844727 ==
6359 00:25:21.851233 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6360 00:25:21.857777 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6361 00:25:21.861242 [CA 0] Center 36 (8~64) winsize 57
6362 00:25:21.864402 [CA 1] Center 36 (8~64) winsize 57
6363 00:25:21.867397 [CA 2] Center 36 (8~64) winsize 57
6364 00:25:21.871133 [CA 3] Center 36 (8~64) winsize 57
6365 00:25:21.873902 [CA 4] Center 36 (8~64) winsize 57
6366 00:25:21.877463 [CA 5] Center 36 (8~64) winsize 57
6367 00:25:21.877844
6368 00:25:21.880578 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6369 00:25:21.880958
6370 00:25:21.884149 [CATrainingPosCal] consider 1 rank data
6371 00:25:21.887640 u2DelayCellTimex100 = 270/100 ps
6372 00:25:21.890587 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6373 00:25:21.893962 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6374 00:25:21.897739 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6375 00:25:21.900638 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6376 00:25:21.904181 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6377 00:25:21.907470 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6378 00:25:21.907937
6379 00:25:21.910527 CA PerBit enable=1, Macro0, CA PI delay=36
6380 00:25:21.910908
6381 00:25:21.914055 [CBTSetCACLKResult] CA Dly = 36
6382 00:25:21.917197 CS Dly: 1 (0~32)
6383 00:25:21.917694 ==
6384 00:25:21.920532 Dram Type= 6, Freq= 0, CH_1, rank 1
6385 00:25:21.924114 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6386 00:25:21.924637 ==
6387 00:25:21.930541 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6388 00:25:21.937176 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6389 00:25:21.940314 [CA 0] Center 36 (8~64) winsize 57
6390 00:25:21.943385 [CA 1] Center 36 (8~64) winsize 57
6391 00:25:21.946911 [CA 2] Center 36 (8~64) winsize 57
6392 00:25:21.947345 [CA 3] Center 36 (8~64) winsize 57
6393 00:25:21.950118 [CA 4] Center 36 (8~64) winsize 57
6394 00:25:21.953228 [CA 5] Center 36 (8~64) winsize 57
6395 00:25:21.953746
6396 00:25:21.956813 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6397 00:25:21.959993
6398 00:25:21.963497 [CATrainingPosCal] consider 2 rank data
6399 00:25:21.964038 u2DelayCellTimex100 = 270/100 ps
6400 00:25:21.970008 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6401 00:25:21.973264 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6402 00:25:21.977117 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6403 00:25:21.980399 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6404 00:25:21.983136 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6405 00:25:21.986812 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6406 00:25:21.987321
6407 00:25:21.990119 CA PerBit enable=1, Macro0, CA PI delay=36
6408 00:25:21.990672
6409 00:25:21.993280 [CBTSetCACLKResult] CA Dly = 36
6410 00:25:21.996844 CS Dly: 1 (0~32)
6411 00:25:21.997397
6412 00:25:22.000174 ----->DramcWriteLeveling(PI) begin...
6413 00:25:22.000689 ==
6414 00:25:22.003402 Dram Type= 6, Freq= 0, CH_1, rank 0
6415 00:25:22.006337 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6416 00:25:22.006793 ==
6417 00:25:22.009982 Write leveling (Byte 0): 32 => 0
6418 00:25:22.013176 Write leveling (Byte 1): 32 => 0
6419 00:25:22.016519 DramcWriteLeveling(PI) end<-----
6420 00:25:22.017025
6421 00:25:22.017355 ==
6422 00:25:22.019597 Dram Type= 6, Freq= 0, CH_1, rank 0
6423 00:25:22.023048 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6424 00:25:22.023494 ==
6425 00:25:22.026459 [Gating] SW mode calibration
6426 00:25:22.032724 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6427 00:25:22.039405 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6428 00:25:22.043145 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6429 00:25:22.046088 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6430 00:25:22.053250 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6431 00:25:22.056291 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6432 00:25:22.059341 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6433 00:25:22.066045 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6434 00:25:22.069288 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6435 00:25:22.072426 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6436 00:25:22.079713 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6437 00:25:22.080222 Total UI for P1: 0, mck2ui 16
6438 00:25:22.085715 best dqsien dly found for B0: ( 0, 10, 16)
6439 00:25:22.086154 Total UI for P1: 0, mck2ui 16
6440 00:25:22.092514 best dqsien dly found for B1: ( 0, 10, 16)
6441 00:25:22.096111 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6442 00:25:22.099237 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6443 00:25:22.099841
6444 00:25:22.102606 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6445 00:25:22.105748 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6446 00:25:22.109252 [Gating] SW calibration Done
6447 00:25:22.109758 ==
6448 00:25:22.112503 Dram Type= 6, Freq= 0, CH_1, rank 0
6449 00:25:22.116067 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6450 00:25:22.116579 ==
6451 00:25:22.118862 RX Vref Scan: 0
6452 00:25:22.119315
6453 00:25:22.119652 RX Vref 0 -> 0, step: 1
6454 00:25:22.122737
6455 00:25:22.123243 RX Delay -410 -> 252, step: 16
6456 00:25:22.129467 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6457 00:25:22.131901 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6458 00:25:22.136053 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6459 00:25:22.139134 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6460 00:25:22.145665 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6461 00:25:22.149370 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6462 00:25:22.152161 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6463 00:25:22.155685 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6464 00:25:22.161873 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6465 00:25:22.165711 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6466 00:25:22.168782 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6467 00:25:22.175195 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6468 00:25:22.178298 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6469 00:25:22.181838 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6470 00:25:22.185322 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6471 00:25:22.191797 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6472 00:25:22.192308 ==
6473 00:25:22.194956 Dram Type= 6, Freq= 0, CH_1, rank 0
6474 00:25:22.198649 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6475 00:25:22.199163 ==
6476 00:25:22.199500 DQS Delay:
6477 00:25:22.201697 DQS0 = 43, DQS1 = 59
6478 00:25:22.202204 DQM Delay:
6479 00:25:22.204715 DQM0 = 6, DQM1 = 14
6480 00:25:22.205139 DQ Delay:
6481 00:25:22.207898 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6482 00:25:22.211388 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6483 00:25:22.214513 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6484 00:25:22.218597 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6485 00:25:22.219103
6486 00:25:22.219438
6487 00:25:22.219743 ==
6488 00:25:22.221591 Dram Type= 6, Freq= 0, CH_1, rank 0
6489 00:25:22.224923 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6490 00:25:22.225429 ==
6491 00:25:22.225780
6492 00:25:22.226084
6493 00:25:22.228059 TX Vref Scan disable
6494 00:25:22.231084 == TX Byte 0 ==
6495 00:25:22.234272 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6496 00:25:22.238197 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6497 00:25:22.241461 == TX Byte 1 ==
6498 00:25:22.244429 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6499 00:25:22.248235 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6500 00:25:22.248742 ==
6501 00:25:22.250826 Dram Type= 6, Freq= 0, CH_1, rank 0
6502 00:25:22.257663 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6503 00:25:22.258169 ==
6504 00:25:22.258577
6505 00:25:22.258886
6506 00:25:22.259175 TX Vref Scan disable
6507 00:25:22.261129 == TX Byte 0 ==
6508 00:25:22.264129 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6509 00:25:22.267054 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6510 00:25:22.270568 == TX Byte 1 ==
6511 00:25:22.273752 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6512 00:25:22.277710 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6513 00:25:22.278195
6514 00:25:22.280576 [DATLAT]
6515 00:25:22.280999 Freq=400, CH1 RK0
6516 00:25:22.281330
6517 00:25:22.284015 DATLAT Default: 0xf
6518 00:25:22.284489 0, 0xFFFF, sum = 0
6519 00:25:22.287024 1, 0xFFFF, sum = 0
6520 00:25:22.287534 2, 0xFFFF, sum = 0
6521 00:25:22.290578 3, 0xFFFF, sum = 0
6522 00:25:22.291010 4, 0xFFFF, sum = 0
6523 00:25:22.294242 5, 0xFFFF, sum = 0
6524 00:25:22.294674 6, 0xFFFF, sum = 0
6525 00:25:22.297124 7, 0xFFFF, sum = 0
6526 00:25:22.300254 8, 0xFFFF, sum = 0
6527 00:25:22.300685 9, 0xFFFF, sum = 0
6528 00:25:22.303597 10, 0xFFFF, sum = 0
6529 00:25:22.304029 11, 0xFFFF, sum = 0
6530 00:25:22.306818 12, 0x0, sum = 1
6531 00:25:22.307247 13, 0x0, sum = 2
6532 00:25:22.310172 14, 0x0, sum = 3
6533 00:25:22.310631 15, 0x0, sum = 4
6534 00:25:22.310968 best_step = 13
6535 00:25:22.311271
6536 00:25:22.313583 ==
6537 00:25:22.317273 Dram Type= 6, Freq= 0, CH_1, rank 0
6538 00:25:22.320475 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6539 00:25:22.320906 ==
6540 00:25:22.321239 RX Vref Scan: 1
6541 00:25:22.321541
6542 00:25:22.323654 RX Vref 0 -> 0, step: 1
6543 00:25:22.324042
6544 00:25:22.326810 RX Delay -359 -> 252, step: 8
6545 00:25:22.327198
6546 00:25:22.329757 Set Vref, RX VrefLevel [Byte0]: 54
6547 00:25:22.333056 [Byte1]: 49
6548 00:25:22.337090
6549 00:25:22.337563 Final RX Vref Byte 0 = 54 to rank0
6550 00:25:22.340359 Final RX Vref Byte 1 = 49 to rank0
6551 00:25:22.344100 Final RX Vref Byte 0 = 54 to rank1
6552 00:25:22.347744 Final RX Vref Byte 1 = 49 to rank1==
6553 00:25:22.350418 Dram Type= 6, Freq= 0, CH_1, rank 0
6554 00:25:22.357265 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6555 00:25:22.357765 ==
6556 00:25:22.358096 DQS Delay:
6557 00:25:22.360378 DQS0 = 48, DQS1 = 64
6558 00:25:22.360883 DQM Delay:
6559 00:25:22.361212 DQM0 = 8, DQM1 = 16
6560 00:25:22.363397 DQ Delay:
6561 00:25:22.368205 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =4
6562 00:25:22.368711 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6563 00:25:22.370191 DQ8 =0, DQ9 =8, DQ10 =20, DQ11 =8
6564 00:25:22.373514 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6565 00:25:22.373966
6566 00:25:22.374558
6567 00:25:22.383531 [DQSOSCAuto] RK0, (LSB)MR18= 0xdbdb, (MSB)MR19= 0xc0c, tDQSOscB0 = 382 ps tDQSOscB1 = 382 ps
6568 00:25:22.386817 CH1 RK0: MR19=C0C, MR18=DBDB
6569 00:25:22.394036 CH1_RK0: MR19=0xC0C, MR18=0xDBDB, DQSOSC=382, MR23=63, INC=404, DEC=269
6570 00:25:22.394557 ==
6571 00:25:22.397416 Dram Type= 6, Freq= 0, CH_1, rank 1
6572 00:25:22.400487 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6573 00:25:22.401155 ==
6574 00:25:22.403571 [Gating] SW mode calibration
6575 00:25:22.410167 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6576 00:25:22.413617 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6577 00:25:22.419993 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6578 00:25:22.423631 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6579 00:25:22.426839 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6580 00:25:22.433355 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6581 00:25:22.436597 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6582 00:25:22.439924 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6583 00:25:22.446953 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6584 00:25:22.449888 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6585 00:25:22.453751 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6586 00:25:22.456618 Total UI for P1: 0, mck2ui 16
6587 00:25:22.459757 best dqsien dly found for B0: ( 0, 10, 16)
6588 00:25:22.463282 Total UI for P1: 0, mck2ui 16
6589 00:25:22.466805 best dqsien dly found for B1: ( 0, 10, 16)
6590 00:25:22.470040 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6591 00:25:22.472989 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6592 00:25:22.476985
6593 00:25:22.480158 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6594 00:25:22.483221 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6595 00:25:22.486365 [Gating] SW calibration Done
6596 00:25:22.486756 ==
6597 00:25:22.490243 Dram Type= 6, Freq= 0, CH_1, rank 1
6598 00:25:22.493177 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6599 00:25:22.493570 ==
6600 00:25:22.496391 RX Vref Scan: 0
6601 00:25:22.496776
6602 00:25:22.497076 RX Vref 0 -> 0, step: 1
6603 00:25:22.497353
6604 00:25:22.500375 RX Delay -410 -> 252, step: 16
6605 00:25:22.503533 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6606 00:25:22.509796 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6607 00:25:22.513138 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6608 00:25:22.516430 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6609 00:25:22.519950 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6610 00:25:22.526315 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6611 00:25:22.529528 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6612 00:25:22.532601 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6613 00:25:22.535864 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6614 00:25:22.542666 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6615 00:25:22.545765 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6616 00:25:22.549808 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6617 00:25:22.552786 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6618 00:25:22.559231 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6619 00:25:22.562788 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6620 00:25:22.566107 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6621 00:25:22.566656 ==
6622 00:25:22.569225 Dram Type= 6, Freq= 0, CH_1, rank 1
6623 00:25:22.575782 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6624 00:25:22.576298 ==
6625 00:25:22.576630 DQS Delay:
6626 00:25:22.578942 DQS0 = 35, DQS1 = 59
6627 00:25:22.579365 DQM Delay:
6628 00:25:22.579694 DQM0 = 4, DQM1 = 16
6629 00:25:22.582798 DQ Delay:
6630 00:25:22.585960 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6631 00:25:22.586528 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6632 00:25:22.589704 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6633 00:25:22.592530 DQ12 =32, DQ13 =24, DQ14 =24, DQ15 =24
6634 00:25:22.592957
6635 00:25:22.595795
6636 00:25:22.596217 ==
6637 00:25:22.599256 Dram Type= 6, Freq= 0, CH_1, rank 1
6638 00:25:22.602125 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6639 00:25:22.602581 ==
6640 00:25:22.602913
6641 00:25:22.603216
6642 00:25:22.605656 TX Vref Scan disable
6643 00:25:22.606083 == TX Byte 0 ==
6644 00:25:22.609613 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6645 00:25:22.615796 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6646 00:25:22.616303 == TX Byte 1 ==
6647 00:25:22.618752 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6648 00:25:22.625541 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6649 00:25:22.626256 ==
6650 00:25:22.629495 Dram Type= 6, Freq= 0, CH_1, rank 1
6651 00:25:22.632277 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6652 00:25:22.632793 ==
6653 00:25:22.633231
6654 00:25:22.633637
6655 00:25:22.635593 TX Vref Scan disable
6656 00:25:22.636109 == TX Byte 0 ==
6657 00:25:22.638809 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6658 00:25:22.645764 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6659 00:25:22.646315 == TX Byte 1 ==
6660 00:25:22.649184 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6661 00:25:22.655546 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6662 00:25:22.656055
6663 00:25:22.656612 [DATLAT]
6664 00:25:22.656952 Freq=400, CH1 RK1
6665 00:25:22.657265
6666 00:25:22.658682 DATLAT Default: 0xd
6667 00:25:22.662254 0, 0xFFFF, sum = 0
6668 00:25:22.662774 1, 0xFFFF, sum = 0
6669 00:25:22.665545 2, 0xFFFF, sum = 0
6670 00:25:22.666052 3, 0xFFFF, sum = 0
6671 00:25:22.669090 4, 0xFFFF, sum = 0
6672 00:25:22.669629 5, 0xFFFF, sum = 0
6673 00:25:22.672119 6, 0xFFFF, sum = 0
6674 00:25:22.672555 7, 0xFFFF, sum = 0
6675 00:25:22.675596 8, 0xFFFF, sum = 0
6676 00:25:22.676119 9, 0xFFFF, sum = 0
6677 00:25:22.679264 10, 0xFFFF, sum = 0
6678 00:25:22.679715 11, 0xFFFF, sum = 0
6679 00:25:22.681891 12, 0x0, sum = 1
6680 00:25:22.682370 13, 0x0, sum = 2
6681 00:25:22.685175 14, 0x0, sum = 3
6682 00:25:22.685623 15, 0x0, sum = 4
6683 00:25:22.688468 best_step = 13
6684 00:25:22.688906
6685 00:25:22.689338 ==
6686 00:25:22.691994 Dram Type= 6, Freq= 0, CH_1, rank 1
6687 00:25:22.695601 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6688 00:25:22.696127 ==
6689 00:25:22.696570 RX Vref Scan: 0
6690 00:25:22.699355
6691 00:25:22.699798 RX Vref 0 -> 0, step: 1
6692 00:25:22.700238
6693 00:25:22.702159 RX Delay -359 -> 252, step: 8
6694 00:25:22.709468 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6695 00:25:22.713303 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6696 00:25:22.716498 iDelay=217, Bit 2, Center -44 (-287 ~ 200) 488
6697 00:25:22.719493 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
6698 00:25:22.726040 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6699 00:25:22.729700 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6700 00:25:22.732482 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6701 00:25:22.736108 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6702 00:25:22.742578 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6703 00:25:22.746116 iDelay=217, Bit 9, Center -64 (-311 ~ 184) 496
6704 00:25:22.749133 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6705 00:25:22.756096 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6706 00:25:22.758799 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6707 00:25:22.762662 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6708 00:25:22.765636 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6709 00:25:22.772327 iDelay=217, Bit 15, Center -44 (-287 ~ 200) 488
6710 00:25:22.772824 ==
6711 00:25:22.775736 Dram Type= 6, Freq= 0, CH_1, rank 1
6712 00:25:22.778921 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6713 00:25:22.779509 ==
6714 00:25:22.779853 DQS Delay:
6715 00:25:22.782604 DQS0 = 44, DQS1 = 64
6716 00:25:22.783034 DQM Delay:
6717 00:25:22.785283 DQM0 = 6, DQM1 = 14
6718 00:25:22.785864 DQ Delay:
6719 00:25:22.788668 DQ0 =12, DQ1 =0, DQ2 =0, DQ3 =0
6720 00:25:22.792077 DQ4 =4, DQ5 =16, DQ6 =16, DQ7 =4
6721 00:25:22.795494 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6722 00:25:22.798833 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =20
6723 00:25:22.799258
6724 00:25:22.799583
6725 00:25:22.805640 [DQSOSCAuto] RK1, (LSB)MR18= 0xadad, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
6726 00:25:22.808963 CH1 RK1: MR19=C0C, MR18=ADAD
6727 00:25:22.815409 CH1_RK1: MR19=0xC0C, MR18=0xADAD, DQSOSC=388, MR23=63, INC=392, DEC=261
6728 00:25:22.819130 [RxdqsGatingPostProcess] freq 400
6729 00:25:22.825677 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6730 00:25:22.826193 Pre-setting of DQS Precalculation
6731 00:25:22.833179 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6732 00:25:22.838478 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6733 00:25:22.845797 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6734 00:25:22.846354
6735 00:25:22.846692
6736 00:25:22.848896 [Calibration Summary] 800 Mbps
6737 00:25:22.852185 CH 0, Rank 0
6738 00:25:22.852692 SW Impedance : PASS
6739 00:25:22.855845 DUTY Scan : NO K
6740 00:25:22.858521 ZQ Calibration : PASS
6741 00:25:22.858954 Jitter Meter : NO K
6742 00:25:22.861962 CBT Training : PASS
6743 00:25:22.865577 Write leveling : PASS
6744 00:25:22.866078 RX DQS gating : PASS
6745 00:25:22.868846 RX DQ/DQS(RDDQC) : PASS
6746 00:25:22.872082 TX DQ/DQS : PASS
6747 00:25:22.872514 RX DATLAT : PASS
6748 00:25:22.874922 RX DQ/DQS(Engine): PASS
6749 00:25:22.875354 TX OE : NO K
6750 00:25:22.878681 All Pass.
6751 00:25:22.879184
6752 00:25:22.879531 CH 0, Rank 1
6753 00:25:22.881843 SW Impedance : PASS
6754 00:25:22.882392 DUTY Scan : NO K
6755 00:25:22.884804 ZQ Calibration : PASS
6756 00:25:22.888186 Jitter Meter : NO K
6757 00:25:22.888616 CBT Training : PASS
6758 00:25:22.891687 Write leveling : NO K
6759 00:25:22.894584 RX DQS gating : PASS
6760 00:25:22.895017 RX DQ/DQS(RDDQC) : PASS
6761 00:25:22.898313 TX DQ/DQS : PASS
6762 00:25:22.901648 RX DATLAT : PASS
6763 00:25:22.902155 RX DQ/DQS(Engine): PASS
6764 00:25:22.904929 TX OE : NO K
6765 00:25:22.905435 All Pass.
6766 00:25:22.905767
6767 00:25:22.908845 CH 1, Rank 0
6768 00:25:22.909302 SW Impedance : PASS
6769 00:25:22.911503 DUTY Scan : NO K
6770 00:25:22.914556 ZQ Calibration : PASS
6771 00:25:22.914987 Jitter Meter : NO K
6772 00:25:22.918256 CBT Training : PASS
6773 00:25:22.921436 Write leveling : PASS
6774 00:25:22.921866 RX DQS gating : PASS
6775 00:25:22.924910 RX DQ/DQS(RDDQC) : PASS
6776 00:25:22.927792 TX DQ/DQS : PASS
6777 00:25:22.928273 RX DATLAT : PASS
6778 00:25:22.931218 RX DQ/DQS(Engine): PASS
6779 00:25:22.931720 TX OE : NO K
6780 00:25:22.934285 All Pass.
6781 00:25:22.934717
6782 00:25:22.935048 CH 1, Rank 1
6783 00:25:22.937756 SW Impedance : PASS
6784 00:25:22.941494 DUTY Scan : NO K
6785 00:25:22.941997 ZQ Calibration : PASS
6786 00:25:22.944568 Jitter Meter : NO K
6787 00:25:22.945069 CBT Training : PASS
6788 00:25:22.948130 Write leveling : NO K
6789 00:25:22.950880 RX DQS gating : PASS
6790 00:25:22.951308 RX DQ/DQS(RDDQC) : PASS
6791 00:25:22.954598 TX DQ/DQS : PASS
6792 00:25:22.957937 RX DATLAT : PASS
6793 00:25:22.958605 RX DQ/DQS(Engine): PASS
6794 00:25:22.960967 TX OE : NO K
6795 00:25:22.961396 All Pass.
6796 00:25:22.961727
6797 00:25:22.964579 DramC Write-DBI off
6798 00:25:22.967413 PER_BANK_REFRESH: Hybrid Mode
6799 00:25:22.967843 TX_TRACKING: ON
6800 00:25:22.977715 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6801 00:25:22.981096 [FAST_K] Save calibration result to emmc
6802 00:25:22.984313 dramc_set_vcore_voltage set vcore to 725000
6803 00:25:22.987770 Read voltage for 1600, 0
6804 00:25:22.988203 Vio18 = 0
6805 00:25:22.988542 Vcore = 725000
6806 00:25:22.990767 Vdram = 0
6807 00:25:22.991195 Vddq = 0
6808 00:25:22.991523 Vmddr = 0
6809 00:25:22.997225 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6810 00:25:23.000682 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6811 00:25:23.003974 MEM_TYPE=3, freq_sel=13
6812 00:25:23.007165 sv_algorithm_assistance_LP4_3733
6813 00:25:23.010327 ============ PULL DRAM RESETB DOWN ============
6814 00:25:23.017029 ========== PULL DRAM RESETB DOWN end =========
6815 00:25:23.020338 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6816 00:25:23.023653 ===================================
6817 00:25:23.027117 LPDDR4 DRAM CONFIGURATION
6818 00:25:23.030564 ===================================
6819 00:25:23.031000 EX_ROW_EN[0] = 0x0
6820 00:25:23.033881 EX_ROW_EN[1] = 0x0
6821 00:25:23.034352 LP4Y_EN = 0x0
6822 00:25:23.036932 WORK_FSP = 0x1
6823 00:25:23.037360 WL = 0x5
6824 00:25:23.040297 RL = 0x5
6825 00:25:23.040724 BL = 0x2
6826 00:25:23.043416 RPST = 0x0
6827 00:25:23.043848 RD_PRE = 0x0
6828 00:25:23.046659 WR_PRE = 0x1
6829 00:25:23.050194 WR_PST = 0x1
6830 00:25:23.050680 DBI_WR = 0x0
6831 00:25:23.053598 DBI_RD = 0x0
6832 00:25:23.053986 OTF = 0x1
6833 00:25:23.056608 ===================================
6834 00:25:23.060028 ===================================
6835 00:25:23.063556 ANA top config
6836 00:25:23.063945 ===================================
6837 00:25:23.067348 DLL_ASYNC_EN = 0
6838 00:25:23.070367 ALL_SLAVE_EN = 0
6839 00:25:23.073198 NEW_RANK_MODE = 1
6840 00:25:23.077115 DLL_IDLE_MODE = 1
6841 00:25:23.077551 LP45_APHY_COMB_EN = 1
6842 00:25:23.080070 TX_ODT_DIS = 0
6843 00:25:23.083275 NEW_8X_MODE = 1
6844 00:25:23.086376 ===================================
6845 00:25:23.089874 ===================================
6846 00:25:23.093130 data_rate = 3200
6847 00:25:23.096563 CKR = 1
6848 00:25:23.099868 DQ_P2S_RATIO = 8
6849 00:25:23.100331 ===================================
6850 00:25:23.103105 CA_P2S_RATIO = 8
6851 00:25:23.106358 DQ_CA_OPEN = 0
6852 00:25:23.110015 DQ_SEMI_OPEN = 0
6853 00:25:23.113023 CA_SEMI_OPEN = 0
6854 00:25:23.116570 CA_FULL_RATE = 0
6855 00:25:23.117016 DQ_CKDIV4_EN = 0
6856 00:25:23.119795 CA_CKDIV4_EN = 0
6857 00:25:23.122901 CA_PREDIV_EN = 0
6858 00:25:23.126120 PH8_DLY = 12
6859 00:25:23.129432 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6860 00:25:23.132886 DQ_AAMCK_DIV = 4
6861 00:25:23.136297 CA_AAMCK_DIV = 4
6862 00:25:23.136727 CA_ADMCK_DIV = 4
6863 00:25:23.139591 DQ_TRACK_CA_EN = 0
6864 00:25:23.143381 CA_PICK = 1600
6865 00:25:23.146150 CA_MCKIO = 1600
6866 00:25:23.149198 MCKIO_SEMI = 0
6867 00:25:23.152914 PLL_FREQ = 3068
6868 00:25:23.156262 DQ_UI_PI_RATIO = 32
6869 00:25:23.159509 CA_UI_PI_RATIO = 0
6870 00:25:23.162591 ===================================
6871 00:25:23.163023 ===================================
6872 00:25:23.165776 memory_type:LPDDR4
6873 00:25:23.168907 GP_NUM : 10
6874 00:25:23.169334 SRAM_EN : 1
6875 00:25:23.172413 MD32_EN : 0
6876 00:25:23.175971 ===================================
6877 00:25:23.179151 [ANA_INIT] >>>>>>>>>>>>>>
6878 00:25:23.182824 <<<<<< [CONFIGURE PHASE]: ANA_TX
6879 00:25:23.185508 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6880 00:25:23.188830 ===================================
6881 00:25:23.192100 data_rate = 3200,PCW = 0X7600
6882 00:25:23.195292 ===================================
6883 00:25:23.198755 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6884 00:25:23.201968 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6885 00:25:23.208754 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6886 00:25:23.212767 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6887 00:25:23.215697 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6888 00:25:23.218583 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6889 00:25:23.222112 [ANA_INIT] flow start
6890 00:25:23.225716 [ANA_INIT] PLL >>>>>>>>
6891 00:25:23.226108 [ANA_INIT] PLL <<<<<<<<
6892 00:25:23.228569 [ANA_INIT] MIDPI >>>>>>>>
6893 00:25:23.232023 [ANA_INIT] MIDPI <<<<<<<<
6894 00:25:23.232501 [ANA_INIT] DLL >>>>>>>>
6895 00:25:23.235319 [ANA_INIT] DLL <<<<<<<<
6896 00:25:23.238448 [ANA_INIT] flow end
6897 00:25:23.242705 ============ LP4 DIFF to SE enter ============
6898 00:25:23.245409 ============ LP4 DIFF to SE exit ============
6899 00:25:23.248874 [ANA_INIT] <<<<<<<<<<<<<
6900 00:25:23.251854 [Flow] Enable top DCM control >>>>>
6901 00:25:23.254830 [Flow] Enable top DCM control <<<<<
6902 00:25:23.258812 Enable DLL master slave shuffle
6903 00:25:23.262051 ==============================================================
6904 00:25:23.264822 Gating Mode config
6905 00:25:23.271942 ==============================================================
6906 00:25:23.272373 Config description:
6907 00:25:23.281851 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6908 00:25:23.287968 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6909 00:25:23.295159 SELPH_MODE 0: By rank 1: By Phase
6910 00:25:23.298458 ==============================================================
6911 00:25:23.301752 GAT_TRACK_EN = 1
6912 00:25:23.304787 RX_GATING_MODE = 2
6913 00:25:23.308044 RX_GATING_TRACK_MODE = 2
6914 00:25:23.311743 SELPH_MODE = 1
6915 00:25:23.314665 PICG_EARLY_EN = 1
6916 00:25:23.318200 VALID_LAT_VALUE = 1
6917 00:25:23.321088 ==============================================================
6918 00:25:23.324586 Enter into Gating configuration >>>>
6919 00:25:23.327979 Exit from Gating configuration <<<<
6920 00:25:23.331174 Enter into DVFS_PRE_config >>>>>
6921 00:25:23.344610 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6922 00:25:23.347836 Exit from DVFS_PRE_config <<<<<
6923 00:25:23.351268 Enter into PICG configuration >>>>
6924 00:25:23.354152 Exit from PICG configuration <<<<
6925 00:25:23.354624 [RX_INPUT] configuration >>>>>
6926 00:25:23.357638 [RX_INPUT] configuration <<<<<
6927 00:25:23.364291 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6928 00:25:23.367778 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6929 00:25:23.374038 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6930 00:25:23.381208 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6931 00:25:23.387156 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6932 00:25:23.394179 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6933 00:25:23.397424 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6934 00:25:23.400890 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6935 00:25:23.407587 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6936 00:25:23.411140 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6937 00:25:23.413862 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6938 00:25:23.416991 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6939 00:25:23.420523 ===================================
6940 00:25:23.423531 LPDDR4 DRAM CONFIGURATION
6941 00:25:23.427549 ===================================
6942 00:25:23.430149 EX_ROW_EN[0] = 0x0
6943 00:25:23.430618 EX_ROW_EN[1] = 0x0
6944 00:25:23.433649 LP4Y_EN = 0x0
6945 00:25:23.434154 WORK_FSP = 0x1
6946 00:25:23.437164 WL = 0x5
6947 00:25:23.437665 RL = 0x5
6948 00:25:23.440172 BL = 0x2
6949 00:25:23.440598 RPST = 0x0
6950 00:25:23.443467 RD_PRE = 0x0
6951 00:25:23.446633 WR_PRE = 0x1
6952 00:25:23.447060 WR_PST = 0x1
6953 00:25:23.449972 DBI_WR = 0x0
6954 00:25:23.450461 DBI_RD = 0x0
6955 00:25:23.453375 OTF = 0x1
6956 00:25:23.456678 ===================================
6957 00:25:23.460235 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6958 00:25:23.463624 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6959 00:25:23.466383 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6960 00:25:23.470109 ===================================
6961 00:25:23.473324 LPDDR4 DRAM CONFIGURATION
6962 00:25:23.476834 ===================================
6963 00:25:23.479709 EX_ROW_EN[0] = 0x10
6964 00:25:23.480138 EX_ROW_EN[1] = 0x0
6965 00:25:23.483004 LP4Y_EN = 0x0
6966 00:25:23.483432 WORK_FSP = 0x1
6967 00:25:23.487081 WL = 0x5
6968 00:25:23.487507 RL = 0x5
6969 00:25:23.489738 BL = 0x2
6970 00:25:23.493107 RPST = 0x0
6971 00:25:23.493532 RD_PRE = 0x0
6972 00:25:23.496349 WR_PRE = 0x1
6973 00:25:23.496778 WR_PST = 0x1
6974 00:25:23.499587 DBI_WR = 0x0
6975 00:25:23.500021 DBI_RD = 0x0
6976 00:25:23.503418 OTF = 0x1
6977 00:25:23.506825 ===================================
6978 00:25:23.509321 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6979 00:25:23.513034 ==
6980 00:25:23.516322 Dram Type= 6, Freq= 0, CH_0, rank 0
6981 00:25:23.519383 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
6982 00:25:23.519816 ==
6983 00:25:23.523031 [Duty_Offset_Calibration]
6984 00:25:23.523457 B0:0 B1:2 CA:1
6985 00:25:23.523785
6986 00:25:23.526724 [DutyScan_Calibration_Flow] k_type=0
6987 00:25:23.536665
6988 00:25:23.537162 ==CLK 0==
6989 00:25:23.539334 Final CLK duty delay cell = 0
6990 00:25:23.542746 [0] MAX Duty = 5156%(X100), DQS PI = 22
6991 00:25:23.545990 [0] MIN Duty = 4938%(X100), DQS PI = 50
6992 00:25:23.546586 [0] AVG Duty = 5047%(X100)
6993 00:25:23.549147
6994 00:25:23.552908 CH0 CLK Duty spec in!! Max-Min= 218%
6995 00:25:23.556138 [DutyScan_Calibration_Flow] ====Done====
6996 00:25:23.556565
6997 00:25:23.559344 [DutyScan_Calibration_Flow] k_type=1
6998 00:25:23.576319
6999 00:25:23.576818 ==DQS 0 ==
7000 00:25:23.579274 Final DQS duty delay cell = 0
7001 00:25:23.582474 [0] MAX Duty = 5156%(X100), DQS PI = 34
7002 00:25:23.586007 [0] MIN Duty = 5000%(X100), DQS PI = 8
7003 00:25:23.589398 [0] AVG Duty = 5078%(X100)
7004 00:25:23.589820
7005 00:25:23.590144 ==DQS 1 ==
7006 00:25:23.592294 Final DQS duty delay cell = 0
7007 00:25:23.596008 [0] MAX Duty = 5031%(X100), DQS PI = 46
7008 00:25:23.599135 [0] MIN Duty = 4876%(X100), DQS PI = 16
7009 00:25:23.602753 [0] AVG Duty = 4953%(X100)
7010 00:25:23.603177
7011 00:25:23.605719 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7012 00:25:23.606144
7013 00:25:23.608854 CH0 DQS 1 Duty spec in!! Max-Min= 155%
7014 00:25:23.612526 [DutyScan_Calibration_Flow] ====Done====
7015 00:25:23.613033
7016 00:25:23.615678 [DutyScan_Calibration_Flow] k_type=3
7017 00:25:23.633696
7018 00:25:23.634194 ==DQM 0 ==
7019 00:25:23.636346 Final DQM duty delay cell = 0
7020 00:25:23.639733 [0] MAX Duty = 5187%(X100), DQS PI = 24
7021 00:25:23.643191 [0] MIN Duty = 4907%(X100), DQS PI = 56
7022 00:25:23.646816 [0] AVG Duty = 5047%(X100)
7023 00:25:23.647243
7024 00:25:23.647572 ==DQM 1 ==
7025 00:25:23.649880 Final DQM duty delay cell = 0
7026 00:25:23.653288 [0] MAX Duty = 5031%(X100), DQS PI = 50
7027 00:25:23.656415 [0] MIN Duty = 4782%(X100), DQS PI = 14
7028 00:25:23.659518 [0] AVG Duty = 4906%(X100)
7029 00:25:23.659904
7030 00:25:23.663028 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7031 00:25:23.663412
7032 00:25:23.666587 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7033 00:25:23.670085 [DutyScan_Calibration_Flow] ====Done====
7034 00:25:23.670535
7035 00:25:23.672987 [DutyScan_Calibration_Flow] k_type=2
7036 00:25:23.689747
7037 00:25:23.690288 ==DQ 0 ==
7038 00:25:23.693043 Final DQ duty delay cell = 0
7039 00:25:23.696489 [0] MAX Duty = 5218%(X100), DQS PI = 18
7040 00:25:23.699396 [0] MIN Duty = 4938%(X100), DQS PI = 56
7041 00:25:23.699826 [0] AVG Duty = 5078%(X100)
7042 00:25:23.702809
7043 00:25:23.703311 ==DQ 1 ==
7044 00:25:23.706387 Final DQ duty delay cell = -4
7045 00:25:23.709561 [-4] MAX Duty = 5062%(X100), DQS PI = 4
7046 00:25:23.712764 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7047 00:25:23.715929 [-4] AVG Duty = 4953%(X100)
7048 00:25:23.716377
7049 00:25:23.719312 CH0 DQ 0 Duty spec in!! Max-Min= 280%
7050 00:25:23.719747
7051 00:25:23.722835 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7052 00:25:23.725978 [DutyScan_Calibration_Flow] ====Done====
7053 00:25:23.726638 ==
7054 00:25:23.729720 Dram Type= 6, Freq= 0, CH_1, rank 0
7055 00:25:23.733348 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7056 00:25:23.733859 ==
7057 00:25:23.735963 [Duty_Offset_Calibration]
7058 00:25:23.736393 B0:0 B1:5 CA:-5
7059 00:25:23.736726
7060 00:25:23.739169 [DutyScan_Calibration_Flow] k_type=0
7061 00:25:23.750843
7062 00:25:23.751346 ==CLK 0==
7063 00:25:23.753472 Final CLK duty delay cell = 0
7064 00:25:23.757051 [0] MAX Duty = 5156%(X100), DQS PI = 20
7065 00:25:23.760365 [0] MIN Duty = 4906%(X100), DQS PI = 52
7066 00:25:23.763482 [0] AVG Duty = 5031%(X100)
7067 00:25:23.763915
7068 00:25:23.766747 CH1 CLK Duty spec in!! Max-Min= 250%
7069 00:25:23.770615 [DutyScan_Calibration_Flow] ====Done====
7070 00:25:23.771125
7071 00:25:23.773032 [DutyScan_Calibration_Flow] k_type=1
7072 00:25:23.789247
7073 00:25:23.789755 ==DQS 0 ==
7074 00:25:23.792890 Final DQS duty delay cell = 0
7075 00:25:23.795648 [0] MAX Duty = 5156%(X100), DQS PI = 18
7076 00:25:23.799470 [0] MIN Duty = 4907%(X100), DQS PI = 42
7077 00:25:23.802818 [0] AVG Duty = 5031%(X100)
7078 00:25:23.803323
7079 00:25:23.803655 ==DQS 1 ==
7080 00:25:23.805717 Final DQS duty delay cell = -4
7081 00:25:23.809788 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7082 00:25:23.812344 [-4] MIN Duty = 4844%(X100), DQS PI = 40
7083 00:25:23.815800 [-4] AVG Duty = 4922%(X100)
7084 00:25:23.816309
7085 00:25:23.818770 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7086 00:25:23.819207
7087 00:25:23.822424 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7088 00:25:23.825686 [DutyScan_Calibration_Flow] ====Done====
7089 00:25:23.826197
7090 00:25:23.828854 [DutyScan_Calibration_Flow] k_type=3
7091 00:25:23.844827
7092 00:25:23.845331 ==DQM 0 ==
7093 00:25:23.848064 Final DQM duty delay cell = -4
7094 00:25:23.851279 [-4] MAX Duty = 5093%(X100), DQS PI = 34
7095 00:25:23.854747 [-4] MIN Duty = 4782%(X100), DQS PI = 44
7096 00:25:23.858286 [-4] AVG Duty = 4937%(X100)
7097 00:25:23.858715
7098 00:25:23.859048 ==DQM 1 ==
7099 00:25:23.861327 Final DQM duty delay cell = -4
7100 00:25:23.864652 [-4] MAX Duty = 5062%(X100), DQS PI = 16
7101 00:25:23.867845 [-4] MIN Duty = 4907%(X100), DQS PI = 38
7102 00:25:23.871302 [-4] AVG Duty = 4984%(X100)
7103 00:25:23.871731
7104 00:25:23.874962 CH1 DQM 0 Duty spec in!! Max-Min= 311%
7105 00:25:23.875470
7106 00:25:23.877883 CH1 DQM 1 Duty spec in!! Max-Min= 155%
7107 00:25:23.881543 [DutyScan_Calibration_Flow] ====Done====
7108 00:25:23.882051
7109 00:25:23.884565 [DutyScan_Calibration_Flow] k_type=2
7110 00:25:23.903052
7111 00:25:23.903522 ==DQ 0 ==
7112 00:25:23.905517 Final DQ duty delay cell = 0
7113 00:25:23.909164 [0] MAX Duty = 5093%(X100), DQS PI = 36
7114 00:25:23.912814 [0] MIN Duty = 4938%(X100), DQS PI = 48
7115 00:25:23.913243 [0] AVG Duty = 5015%(X100)
7116 00:25:23.915629
7117 00:25:23.916050 ==DQ 1 ==
7118 00:25:23.918930 Final DQ duty delay cell = 0
7119 00:25:23.922166 [0] MAX Duty = 5031%(X100), DQS PI = 4
7120 00:25:23.925524 [0] MIN Duty = 4907%(X100), DQS PI = 22
7121 00:25:23.925744 [0] AVG Duty = 4969%(X100)
7122 00:25:23.925914
7123 00:25:23.928730 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7124 00:25:23.931927
7125 00:25:23.935375 CH1 DQ 1 Duty spec in!! Max-Min= 124%
7126 00:25:23.938723 [DutyScan_Calibration_Flow] ====Done====
7127 00:25:23.941996 nWR fixed to 30
7128 00:25:23.942181 [ModeRegInit_LP4] CH0 RK0
7129 00:25:23.945261 [ModeRegInit_LP4] CH0 RK1
7130 00:25:23.949362 [ModeRegInit_LP4] CH1 RK0
7131 00:25:23.949533 [ModeRegInit_LP4] CH1 RK1
7132 00:25:23.952093 match AC timing 4
7133 00:25:23.954983 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7134 00:25:23.961775 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7135 00:25:23.965545 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7136 00:25:23.971774 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7137 00:25:23.974985 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7138 00:25:23.975210 [MiockJmeterHQA]
7139 00:25:23.975316
7140 00:25:23.978636 [DramcMiockJmeter] u1RxGatingPI = 0
7141 00:25:23.981873 0 : 4252, 4026
7142 00:25:23.982450 4 : 4257, 4032
7143 00:25:23.985340 8 : 4253, 4026
7144 00:25:23.985862 12 : 4252, 4027
7145 00:25:23.986419 16 : 4252, 4027
7146 00:25:23.988948 20 : 4252, 4027
7147 00:25:23.989469 24 : 4257, 4029
7148 00:25:23.991602 28 : 4257, 4029
7149 00:25:23.992047 32 : 4253, 4026
7150 00:25:23.995104 36 : 4262, 4032
7151 00:25:23.995562 40 : 4252, 4027
7152 00:25:23.998203 44 : 4253, 4026
7153 00:25:23.998686 48 : 4365, 4139
7154 00:25:23.999116 52 : 4362, 4137
7155 00:25:24.001894 56 : 4252, 4027
7156 00:25:24.002467 60 : 4257, 4029
7157 00:25:24.005514 64 : 4250, 4027
7158 00:25:24.006023 68 : 4252, 4029
7159 00:25:24.008191 72 : 4249, 4027
7160 00:25:24.008622 76 : 4250, 4026
7161 00:25:24.011895 80 : 4250, 4026
7162 00:25:24.012406 84 : 4250, 4026
7163 00:25:24.012746 88 : 4363, 4140
7164 00:25:24.014868 92 : 4249, 4027
7165 00:25:24.015297 96 : 4363, 4140
7166 00:25:24.018116 100 : 4363, 2469
7167 00:25:24.018708 104 : 4249, 0
7168 00:25:24.021467 108 : 4360, 0
7169 00:25:24.021902 112 : 4252, 0
7170 00:25:24.022276 116 : 4250, 0
7171 00:25:24.024754 120 : 4250, 0
7172 00:25:24.025224 124 : 4250, 0
7173 00:25:24.025565 128 : 4250, 0
7174 00:25:24.028495 132 : 4250, 0
7175 00:25:24.029013 136 : 4253, 0
7176 00:25:24.031660 140 : 4255, 0
7177 00:25:24.032094 144 : 4250, 0
7178 00:25:24.032426 148 : 4252, 0
7179 00:25:24.034698 152 : 4250, 0
7180 00:25:24.035131 156 : 4255, 0
7181 00:25:24.038388 160 : 4250, 0
7182 00:25:24.038826 164 : 4250, 0
7183 00:25:24.039165 168 : 4249, 0
7184 00:25:24.041424 172 : 4249, 0
7185 00:25:24.042063 176 : 4253, 0
7186 00:25:24.044751 180 : 4250, 0
7187 00:25:24.045183 184 : 4250, 0
7188 00:25:24.045518 188 : 4250, 0
7189 00:25:24.048073 192 : 4250, 0
7190 00:25:24.048505 196 : 4365, 0
7191 00:25:24.048839 200 : 4361, 0
7192 00:25:24.051556 204 : 4250, 0
7193 00:25:24.052064 208 : 4249, 0
7194 00:25:24.054814 212 : 4250, 0
7195 00:25:24.055247 216 : 4361, 0
7196 00:25:24.055583 220 : 4249, 253
7197 00:25:24.057967 224 : 4255, 3893
7198 00:25:24.058438 228 : 4252, 4030
7199 00:25:24.061355 232 : 4360, 4138
7200 00:25:24.061787 236 : 4250, 4027
7201 00:25:24.064871 240 : 4250, 4027
7202 00:25:24.065379 244 : 4361, 4137
7203 00:25:24.067826 248 : 4254, 4029
7204 00:25:24.068259 252 : 4249, 4027
7205 00:25:24.071080 256 : 4250, 4027
7206 00:25:24.071516 260 : 4250, 4027
7207 00:25:24.074907 264 : 4363, 4140
7208 00:25:24.075356 268 : 4250, 4027
7209 00:25:24.077986 272 : 4250, 4026
7210 00:25:24.078458 276 : 4250, 4027
7211 00:25:24.078800 280 : 4252, 4029
7212 00:25:24.081178 284 : 4360, 4138
7213 00:25:24.081609 288 : 4250, 4026
7214 00:25:24.084627 292 : 4250, 4026
7215 00:25:24.085137 296 : 4250, 4026
7216 00:25:24.087552 300 : 4249, 4027
7217 00:25:24.087997 304 : 4249, 4027
7218 00:25:24.090940 308 : 4250, 4027
7219 00:25:24.091375 312 : 4250, 4027
7220 00:25:24.094099 316 : 4363, 4140
7221 00:25:24.094563 320 : 4250, 4027
7222 00:25:24.097900 324 : 4250, 4026
7223 00:25:24.098454 328 : 4255, 4029
7224 00:25:24.101205 332 : 4360, 4138
7225 00:25:24.101718 336 : 4360, 4039
7226 00:25:24.104528 340 : 4360, 2216
7227 00:25:24.104964 344 : 4250, 0
7228 00:25:24.105301
7229 00:25:24.108020 MIOCK jitter meter ch=0
7230 00:25:24.108532
7231 00:25:24.111134 1T = (344-104) = 240 dly cells
7232 00:25:24.114447 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 271/100 ps
7233 00:25:24.114879 ==
7234 00:25:24.117596 Dram Type= 6, Freq= 0, CH_0, rank 0
7235 00:25:24.124178 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7236 00:25:24.124608 ==
7237 00:25:24.128231 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7238 00:25:24.134193 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7239 00:25:24.137721 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7240 00:25:24.144171 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7241 00:25:24.150908 [CA 0] Center 42 (12~72) winsize 61
7242 00:25:24.154621 [CA 1] Center 41 (11~72) winsize 62
7243 00:25:24.157626 [CA 2] Center 37 (7~68) winsize 62
7244 00:25:24.161000 [CA 3] Center 37 (7~67) winsize 61
7245 00:25:24.164272 [CA 4] Center 35 (5~66) winsize 62
7246 00:25:24.167465 [CA 5] Center 35 (5~65) winsize 61
7247 00:25:24.167902
7248 00:25:24.170994 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7249 00:25:24.171429
7250 00:25:24.173931 [CATrainingPosCal] consider 1 rank data
7251 00:25:24.177358 u2DelayCellTimex100 = 271/100 ps
7252 00:25:24.180561 CA0 delay=42 (12~72),Diff = 7 PI (25 cell)
7253 00:25:24.187477 CA1 delay=41 (11~72),Diff = 6 PI (21 cell)
7254 00:25:24.190382 CA2 delay=37 (7~68),Diff = 2 PI (7 cell)
7255 00:25:24.193880 CA3 delay=37 (7~67),Diff = 2 PI (7 cell)
7256 00:25:24.197532 CA4 delay=35 (5~66),Diff = 0 PI (0 cell)
7257 00:25:24.201074 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7258 00:25:24.201575
7259 00:25:24.204437 CA PerBit enable=1, Macro0, CA PI delay=35
7260 00:25:24.204947
7261 00:25:24.207629 [CBTSetCACLKResult] CA Dly = 35
7262 00:25:24.210868 CS Dly: 11 (0~42)
7263 00:25:24.214004 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7264 00:25:24.217379 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7265 00:25:24.217882 ==
7266 00:25:24.220870 Dram Type= 6, Freq= 0, CH_0, rank 1
7267 00:25:24.223616 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7268 00:25:24.227118 ==
7269 00:25:24.230530 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7270 00:25:24.234247 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7271 00:25:24.240522 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7272 00:25:24.246669 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7273 00:25:24.253378 [CA 0] Center 42 (12~73) winsize 62
7274 00:25:24.256501 [CA 1] Center 41 (11~72) winsize 62
7275 00:25:24.260088 [CA 2] Center 38 (8~68) winsize 61
7276 00:25:24.263390 [CA 3] Center 37 (7~67) winsize 61
7277 00:25:24.266494 [CA 4] Center 35 (5~65) winsize 61
7278 00:25:24.269867 [CA 5] Center 35 (5~66) winsize 62
7279 00:25:24.270402
7280 00:25:24.273170 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7281 00:25:24.273617
7282 00:25:24.276434 [CATrainingPosCal] consider 2 rank data
7283 00:25:24.279857 u2DelayCellTimex100 = 271/100 ps
7284 00:25:24.283139 CA0 delay=42 (12~72),Diff = 7 PI (25 cell)
7285 00:25:24.289804 CA1 delay=41 (11~72),Diff = 6 PI (21 cell)
7286 00:25:24.293216 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7287 00:25:24.296168 CA3 delay=37 (7~67),Diff = 2 PI (7 cell)
7288 00:25:24.299826 CA4 delay=35 (5~65),Diff = 0 PI (0 cell)
7289 00:25:24.303161 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7290 00:25:24.303594
7291 00:25:24.306314 CA PerBit enable=1, Macro0, CA PI delay=35
7292 00:25:24.306746
7293 00:25:24.309562 [CBTSetCACLKResult] CA Dly = 35
7294 00:25:24.313234 CS Dly: 11 (0~43)
7295 00:25:24.316083 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7296 00:25:24.319713 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7297 00:25:24.320104
7298 00:25:24.322914 ----->DramcWriteLeveling(PI) begin...
7299 00:25:24.323435 ==
7300 00:25:24.326917 Dram Type= 6, Freq= 0, CH_0, rank 0
7301 00:25:24.332871 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7302 00:25:24.333308 ==
7303 00:25:24.336411 Write leveling (Byte 0): 29 => 29
7304 00:25:24.336840 Write leveling (Byte 1): 26 => 26
7305 00:25:24.339394 DramcWriteLeveling(PI) end<-----
7306 00:25:24.339797
7307 00:25:24.343258 ==
7308 00:25:24.343824 Dram Type= 6, Freq= 0, CH_0, rank 0
7309 00:25:24.349559 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7310 00:25:24.350079 ==
7311 00:25:24.352897 [Gating] SW mode calibration
7312 00:25:24.359335 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7313 00:25:24.362757 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7314 00:25:24.369375 0 12 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7315 00:25:24.372808 0 12 4 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7316 00:25:24.376055 0 12 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7317 00:25:24.382799 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7318 00:25:24.385988 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7319 00:25:24.389203 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7320 00:25:24.396501 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7321 00:25:24.399628 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7322 00:25:24.402862 0 13 0 | B1->B0 | 3434 3131 | 1 0 | (1 0) (0 0)
7323 00:25:24.409274 0 13 4 | B1->B0 | 3333 2626 | 1 0 | (1 0) (0 1)
7324 00:25:24.412647 0 13 8 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
7325 00:25:24.416205 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7326 00:25:24.422502 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7327 00:25:24.425751 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7328 00:25:24.429657 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7329 00:25:24.435888 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7330 00:25:24.439164 0 14 0 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (1 1)
7331 00:25:24.442120 0 14 4 | B1->B0 | 3838 4646 | 1 0 | (0 0) (0 0)
7332 00:25:24.445790 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7333 00:25:24.452112 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7334 00:25:24.455480 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7335 00:25:24.458659 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7336 00:25:24.465102 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7337 00:25:24.468472 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7338 00:25:24.472189 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7339 00:25:24.478466 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7340 00:25:24.481871 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7341 00:25:24.485317 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7342 00:25:24.491780 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7343 00:25:24.495595 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7344 00:25:24.498453 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7345 00:25:24.505175 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7346 00:25:24.508384 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7347 00:25:24.511673 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7348 00:25:24.518555 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7349 00:25:24.522027 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7350 00:25:24.525185 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7351 00:25:24.531802 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7352 00:25:24.535254 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7353 00:25:24.538247 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7354 00:25:24.545142 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7355 00:25:24.549271 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7356 00:25:24.551725 Total UI for P1: 0, mck2ui 16
7357 00:25:24.555098 best dqsien dly found for B0: ( 1, 0, 30)
7358 00:25:24.558525 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7359 00:25:24.561591 Total UI for P1: 0, mck2ui 16
7360 00:25:24.564716 best dqsien dly found for B1: ( 1, 1, 4)
7361 00:25:24.568197 best DQS0 dly(MCK, UI, PI) = (1, 0, 30)
7362 00:25:24.571479 best DQS1 dly(MCK, UI, PI) = (1, 1, 4)
7363 00:25:24.571911
7364 00:25:24.577995 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30)
7365 00:25:24.581642 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4)
7366 00:25:24.582074 [Gating] SW calibration Done
7367 00:25:24.584831 ==
7368 00:25:24.588214 Dram Type= 6, Freq= 0, CH_0, rank 0
7369 00:25:24.591516 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7370 00:25:24.591951 ==
7371 00:25:24.592282 RX Vref Scan: 0
7372 00:25:24.592590
7373 00:25:24.594744 RX Vref 0 -> 0, step: 1
7374 00:25:24.595176
7375 00:25:24.598424 RX Delay 0 -> 252, step: 8
7376 00:25:24.601309 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
7377 00:25:24.604738 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7378 00:25:24.607899 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
7379 00:25:24.614302 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7380 00:25:24.617697 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7381 00:25:24.621077 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7382 00:25:24.624375 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7383 00:25:24.627684 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7384 00:25:24.634336 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7385 00:25:24.637615 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7386 00:25:24.640997 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7387 00:25:24.644427 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7388 00:25:24.647889 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7389 00:25:24.654545 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7390 00:25:24.657926 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7391 00:25:24.661818 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7392 00:25:24.662428 ==
7393 00:25:24.664995 Dram Type= 6, Freq= 0, CH_0, rank 0
7394 00:25:24.668452 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7395 00:25:24.670856 ==
7396 00:25:24.671290 DQS Delay:
7397 00:25:24.671626 DQS0 = 0, DQS1 = 0
7398 00:25:24.674269 DQM Delay:
7399 00:25:24.674714 DQM0 = 129, DQM1 = 123
7400 00:25:24.677688 DQ Delay:
7401 00:25:24.680941 DQ0 =123, DQ1 =131, DQ2 =123, DQ3 =127
7402 00:25:24.683965 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7403 00:25:24.687634 DQ8 =111, DQ9 =107, DQ10 =123, DQ11 =115
7404 00:25:24.691064 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7405 00:25:24.691496
7406 00:25:24.691823
7407 00:25:24.692130 ==
7408 00:25:24.693997 Dram Type= 6, Freq= 0, CH_0, rank 0
7409 00:25:24.697358 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7410 00:25:24.697809 ==
7411 00:25:24.700396
7412 00:25:24.700827
7413 00:25:24.701162 TX Vref Scan disable
7414 00:25:24.704238 == TX Byte 0 ==
7415 00:25:24.707773 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7416 00:25:24.710537 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7417 00:25:24.713753 == TX Byte 1 ==
7418 00:25:24.716988 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7419 00:25:24.720616 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7420 00:25:24.721098 ==
7421 00:25:24.724176 Dram Type= 6, Freq= 0, CH_0, rank 0
7422 00:25:24.730688 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7423 00:25:24.731144 ==
7424 00:25:24.743236
7425 00:25:24.746428 TX Vref early break, caculate TX vref
7426 00:25:24.750353 TX Vref=16, minBit 8, minWin=21, winSum=369
7427 00:25:24.753240 TX Vref=18, minBit 8, minWin=22, winSum=379
7428 00:25:24.756870 TX Vref=20, minBit 8, minWin=23, winSum=388
7429 00:25:24.760394 TX Vref=22, minBit 8, minWin=23, winSum=393
7430 00:25:24.762977 TX Vref=24, minBit 8, minWin=23, winSum=404
7431 00:25:24.770320 TX Vref=26, minBit 8, minWin=24, winSum=413
7432 00:25:24.773202 TX Vref=28, minBit 1, minWin=25, winSum=414
7433 00:25:24.776431 TX Vref=30, minBit 0, minWin=25, winSum=412
7434 00:25:24.780364 TX Vref=32, minBit 6, minWin=24, winSum=403
7435 00:25:24.783013 TX Vref=34, minBit 8, minWin=23, winSum=394
7436 00:25:24.786277 TX Vref=36, minBit 1, minWin=23, winSum=386
7437 00:25:24.793044 [TxChooseVref] Worse bit 1, Min win 25, Win sum 414, Final Vref 28
7438 00:25:24.793480
7439 00:25:24.796495 Final TX Range 0 Vref 28
7440 00:25:24.796928
7441 00:25:24.797255 ==
7442 00:25:24.800071 Dram Type= 6, Freq= 0, CH_0, rank 0
7443 00:25:24.803691 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7444 00:25:24.804204 ==
7445 00:25:24.804541
7446 00:25:24.804845
7447 00:25:24.806434 TX Vref Scan disable
7448 00:25:24.812965 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7449 00:25:24.813404 == TX Byte 0 ==
7450 00:25:24.816855 u2DelayCellOfst[0]=14 cells (4 PI)
7451 00:25:24.819695 u2DelayCellOfst[1]=18 cells (5 PI)
7452 00:25:24.822776 u2DelayCellOfst[2]=14 cells (4 PI)
7453 00:25:24.826053 u2DelayCellOfst[3]=10 cells (3 PI)
7454 00:25:24.829703 u2DelayCellOfst[4]=7 cells (2 PI)
7455 00:25:24.832894 u2DelayCellOfst[5]=0 cells (0 PI)
7456 00:25:24.836423 u2DelayCellOfst[6]=18 cells (5 PI)
7457 00:25:24.839346 u2DelayCellOfst[7]=14 cells (4 PI)
7458 00:25:24.842740 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7459 00:25:24.845851 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7460 00:25:24.849383 == TX Byte 1 ==
7461 00:25:24.852839 u2DelayCellOfst[8]=3 cells (1 PI)
7462 00:25:24.855527 u2DelayCellOfst[9]=0 cells (0 PI)
7463 00:25:24.858827 u2DelayCellOfst[10]=10 cells (3 PI)
7464 00:25:24.859003 u2DelayCellOfst[11]=7 cells (2 PI)
7465 00:25:24.862125 u2DelayCellOfst[12]=14 cells (4 PI)
7466 00:25:24.865579 u2DelayCellOfst[13]=14 cells (4 PI)
7467 00:25:24.868676 u2DelayCellOfst[14]=18 cells (5 PI)
7468 00:25:24.872392 u2DelayCellOfst[15]=18 cells (5 PI)
7469 00:25:24.879022 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
7470 00:25:24.882618 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7471 00:25:24.882813 DramC Write-DBI on
7472 00:25:24.882935 ==
7473 00:25:24.885572 Dram Type= 6, Freq= 0, CH_0, rank 0
7474 00:25:24.892026 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7475 00:25:24.892236 ==
7476 00:25:24.892361
7477 00:25:24.892474
7478 00:25:24.895288 TX Vref Scan disable
7479 00:25:24.895439 == TX Byte 0 ==
7480 00:25:24.902452 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7481 00:25:24.902689 == TX Byte 1 ==
7482 00:25:24.905977 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
7483 00:25:24.909133 DramC Write-DBI off
7484 00:25:24.909399
7485 00:25:24.909604 [DATLAT]
7486 00:25:24.912220 Freq=1600, CH0 RK0
7487 00:25:24.912463
7488 00:25:24.912650 DATLAT Default: 0xf
7489 00:25:24.915557 0, 0xFFFF, sum = 0
7490 00:25:24.915942 1, 0xFFFF, sum = 0
7491 00:25:24.919060 2, 0xFFFF, sum = 0
7492 00:25:24.919474 3, 0xFFFF, sum = 0
7493 00:25:24.922523 4, 0xFFFF, sum = 0
7494 00:25:24.922995 5, 0xFFFF, sum = 0
7495 00:25:24.925600 6, 0xFFFF, sum = 0
7496 00:25:24.926038 7, 0xFFFF, sum = 0
7497 00:25:24.928851 8, 0xFFFF, sum = 0
7498 00:25:24.929368 9, 0xFFFF, sum = 0
7499 00:25:24.932629 10, 0xFFFF, sum = 0
7500 00:25:24.935376 11, 0xFFFF, sum = 0
7501 00:25:24.935895 12, 0xFFF, sum = 0
7502 00:25:24.938519 13, 0x0, sum = 1
7503 00:25:24.938955 14, 0x0, sum = 2
7504 00:25:24.942112 15, 0x0, sum = 3
7505 00:25:24.942571 16, 0x0, sum = 4
7506 00:25:24.942912 best_step = 14
7507 00:25:24.943216
7508 00:25:24.945364 ==
7509 00:25:24.948280 Dram Type= 6, Freq= 0, CH_0, rank 0
7510 00:25:24.952280 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7511 00:25:24.952788 ==
7512 00:25:24.953124 RX Vref Scan: 1
7513 00:25:24.953433
7514 00:25:24.955056 Set Vref Range= 24 -> 127
7515 00:25:24.955490
7516 00:25:24.958244 RX Vref 24 -> 127, step: 1
7517 00:25:24.958680
7518 00:25:24.962437 RX Delay 11 -> 252, step: 4
7519 00:25:24.962944
7520 00:25:24.965118 Set Vref, RX VrefLevel [Byte0]: 24
7521 00:25:24.968333 [Byte1]: 24
7522 00:25:24.968808
7523 00:25:24.971781 Set Vref, RX VrefLevel [Byte0]: 25
7524 00:25:24.975077 [Byte1]: 25
7525 00:25:24.975506
7526 00:25:24.978328 Set Vref, RX VrefLevel [Byte0]: 26
7527 00:25:24.982381 [Byte1]: 26
7528 00:25:24.985441
7529 00:25:24.986077 Set Vref, RX VrefLevel [Byte0]: 27
7530 00:25:24.988810 [Byte1]: 27
7531 00:25:24.992876
7532 00:25:24.993381 Set Vref, RX VrefLevel [Byte0]: 28
7533 00:25:24.996235 [Byte1]: 28
7534 00:25:25.000751
7535 00:25:25.001270 Set Vref, RX VrefLevel [Byte0]: 29
7536 00:25:25.004068 [Byte1]: 29
7537 00:25:25.008102
7538 00:25:25.008609 Set Vref, RX VrefLevel [Byte0]: 30
7539 00:25:25.011429 [Byte1]: 30
7540 00:25:25.015621
7541 00:25:25.016053 Set Vref, RX VrefLevel [Byte0]: 31
7542 00:25:25.018635 [Byte1]: 31
7543 00:25:25.023301
7544 00:25:25.023724 Set Vref, RX VrefLevel [Byte0]: 32
7545 00:25:25.027012 [Byte1]: 32
7546 00:25:25.031111
7547 00:25:25.031623 Set Vref, RX VrefLevel [Byte0]: 33
7548 00:25:25.034496 [Byte1]: 33
7549 00:25:25.038627
7550 00:25:25.039128 Set Vref, RX VrefLevel [Byte0]: 34
7551 00:25:25.042000 [Byte1]: 34
7552 00:25:25.046152
7553 00:25:25.046710 Set Vref, RX VrefLevel [Byte0]: 35
7554 00:25:25.049124 [Byte1]: 35
7555 00:25:25.054059
7556 00:25:25.054600 Set Vref, RX VrefLevel [Byte0]: 36
7557 00:25:25.057289 [Byte1]: 36
7558 00:25:25.061694
7559 00:25:25.062197 Set Vref, RX VrefLevel [Byte0]: 37
7560 00:25:25.064939 [Byte1]: 37
7561 00:25:25.069016
7562 00:25:25.069446 Set Vref, RX VrefLevel [Byte0]: 38
7563 00:25:25.072247 [Byte1]: 38
7564 00:25:25.076596
7565 00:25:25.077105 Set Vref, RX VrefLevel [Byte0]: 39
7566 00:25:25.080212 [Byte1]: 39
7567 00:25:25.084431
7568 00:25:25.084934 Set Vref, RX VrefLevel [Byte0]: 40
7569 00:25:25.087262 [Byte1]: 40
7570 00:25:25.092102
7571 00:25:25.092530 Set Vref, RX VrefLevel [Byte0]: 41
7572 00:25:25.095122 [Byte1]: 41
7573 00:25:25.099458
7574 00:25:25.099961 Set Vref, RX VrefLevel [Byte0]: 42
7575 00:25:25.102686 [Byte1]: 42
7576 00:25:25.107286
7577 00:25:25.107792 Set Vref, RX VrefLevel [Byte0]: 43
7578 00:25:25.110745 [Byte1]: 43
7579 00:25:25.114887
7580 00:25:25.115389 Set Vref, RX VrefLevel [Byte0]: 44
7581 00:25:25.118001 [Byte1]: 44
7582 00:25:25.122294
7583 00:25:25.122724 Set Vref, RX VrefLevel [Byte0]: 45
7584 00:25:25.125446 [Byte1]: 45
7585 00:25:25.129982
7586 00:25:25.130561 Set Vref, RX VrefLevel [Byte0]: 46
7587 00:25:25.133197 [Byte1]: 46
7588 00:25:25.137193
7589 00:25:25.137623 Set Vref, RX VrefLevel [Byte0]: 47
7590 00:25:25.140886 [Byte1]: 47
7591 00:25:25.145252
7592 00:25:25.145755 Set Vref, RX VrefLevel [Byte0]: 48
7593 00:25:25.148239 [Byte1]: 48
7594 00:25:25.153215
7595 00:25:25.153716 Set Vref, RX VrefLevel [Byte0]: 49
7596 00:25:25.156005 [Byte1]: 49
7597 00:25:25.160751
7598 00:25:25.161255 Set Vref, RX VrefLevel [Byte0]: 50
7599 00:25:25.163595 [Byte1]: 50
7600 00:25:25.167862
7601 00:25:25.168366 Set Vref, RX VrefLevel [Byte0]: 51
7602 00:25:25.171437 [Byte1]: 51
7603 00:25:25.176103
7604 00:25:25.176622 Set Vref, RX VrefLevel [Byte0]: 52
7605 00:25:25.178940 [Byte1]: 52
7606 00:25:25.183291
7607 00:25:25.183794 Set Vref, RX VrefLevel [Byte0]: 53
7608 00:25:25.186837 [Byte1]: 53
7609 00:25:25.190879
7610 00:25:25.191396 Set Vref, RX VrefLevel [Byte0]: 54
7611 00:25:25.194474 [Byte1]: 54
7612 00:25:25.198168
7613 00:25:25.198695 Set Vref, RX VrefLevel [Byte0]: 55
7614 00:25:25.201636 [Byte1]: 55
7615 00:25:25.205948
7616 00:25:25.206488 Set Vref, RX VrefLevel [Byte0]: 56
7617 00:25:25.209314 [Byte1]: 56
7618 00:25:25.213325
7619 00:25:25.213753 Set Vref, RX VrefLevel [Byte0]: 57
7620 00:25:25.216935 [Byte1]: 57
7621 00:25:25.221370
7622 00:25:25.221878 Set Vref, RX VrefLevel [Byte0]: 58
7623 00:25:25.224650 [Byte1]: 58
7624 00:25:25.228741
7625 00:25:25.229165 Set Vref, RX VrefLevel [Byte0]: 59
7626 00:25:25.231919 [Byte1]: 59
7627 00:25:25.236706
7628 00:25:25.237222 Set Vref, RX VrefLevel [Byte0]: 60
7629 00:25:25.239505 [Byte1]: 60
7630 00:25:25.244439
7631 00:25:25.244999 Set Vref, RX VrefLevel [Byte0]: 61
7632 00:25:25.247398 [Byte1]: 61
7633 00:25:25.252029
7634 00:25:25.252452 Set Vref, RX VrefLevel [Byte0]: 62
7635 00:25:25.254732 [Byte1]: 62
7636 00:25:25.259005
7637 00:25:25.259427 Set Vref, RX VrefLevel [Byte0]: 63
7638 00:25:25.262451 [Byte1]: 63
7639 00:25:25.267043
7640 00:25:25.267509 Set Vref, RX VrefLevel [Byte0]: 64
7641 00:25:25.270095 [Byte1]: 64
7642 00:25:25.274696
7643 00:25:25.275196 Set Vref, RX VrefLevel [Byte0]: 65
7644 00:25:25.277478 [Byte1]: 65
7645 00:25:25.282302
7646 00:25:25.282807 Set Vref, RX VrefLevel [Byte0]: 66
7647 00:25:25.285422 [Byte1]: 66
7648 00:25:25.290128
7649 00:25:25.290697 Set Vref, RX VrefLevel [Byte0]: 67
7650 00:25:25.292948 [Byte1]: 67
7651 00:25:25.297847
7652 00:25:25.298397 Set Vref, RX VrefLevel [Byte0]: 68
7653 00:25:25.300597 [Byte1]: 68
7654 00:25:25.305563
7655 00:25:25.306068 Set Vref, RX VrefLevel [Byte0]: 69
7656 00:25:25.308119 [Byte1]: 69
7657 00:25:25.312663
7658 00:25:25.313089 Final RX Vref Byte 0 = 52 to rank0
7659 00:25:25.315974 Final RX Vref Byte 1 = 54 to rank0
7660 00:25:25.319317 Final RX Vref Byte 0 = 52 to rank1
7661 00:25:25.322489 Final RX Vref Byte 1 = 54 to rank1==
7662 00:25:25.326006 Dram Type= 6, Freq= 0, CH_0, rank 0
7663 00:25:25.332172 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7664 00:25:25.332666 ==
7665 00:25:25.332998 DQS Delay:
7666 00:25:25.335356 DQS0 = 0, DQS1 = 0
7667 00:25:25.335786 DQM Delay:
7668 00:25:25.336117 DQM0 = 126, DQM1 = 120
7669 00:25:25.338802 DQ Delay:
7670 00:25:25.342468 DQ0 =122, DQ1 =128, DQ2 =124, DQ3 =122
7671 00:25:25.345824 DQ4 =130, DQ5 =116, DQ6 =138, DQ7 =134
7672 00:25:25.348643 DQ8 =110, DQ9 =104, DQ10 =120, DQ11 =112
7673 00:25:25.352010 DQ12 =126, DQ13 =126, DQ14 =134, DQ15 =132
7674 00:25:25.352437
7675 00:25:25.352769
7676 00:25:25.353073
7677 00:25:25.355454 [DramC_TX_OE_Calibration] TA2
7678 00:25:25.358731 Original DQ_B0 (3 6) =30, OEN = 27
7679 00:25:25.362000 Original DQ_B1 (3 6) =30, OEN = 27
7680 00:25:25.365624 24, 0x0, End_B0=24 End_B1=24
7681 00:25:25.366061 25, 0x0, End_B0=25 End_B1=25
7682 00:25:25.368921 26, 0x0, End_B0=26 End_B1=26
7683 00:25:25.372473 27, 0x0, End_B0=27 End_B1=27
7684 00:25:25.375100 28, 0x0, End_B0=28 End_B1=28
7685 00:25:25.378649 29, 0x0, End_B0=29 End_B1=29
7686 00:25:25.379084 30, 0x0, End_B0=30 End_B1=30
7687 00:25:25.382013 31, 0x5151, End_B0=30 End_B1=30
7688 00:25:25.385262 Byte0 end_step=30 best_step=27
7689 00:25:25.388565 Byte1 end_step=30 best_step=27
7690 00:25:25.392055 Byte0 TX OE(2T, 0.5T) = (3, 3)
7691 00:25:25.395023 Byte1 TX OE(2T, 0.5T) = (3, 3)
7692 00:25:25.395528
7693 00:25:25.395918
7694 00:25:25.401659 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
7695 00:25:25.405031 CH0 RK0: MR19=303, MR18=1B1B
7696 00:25:25.412014 CH0_RK0: MR19=0x303, MR18=0x1B1B, DQSOSC=396, MR23=63, INC=23, DEC=15
7697 00:25:25.412454
7698 00:25:25.415222 ----->DramcWriteLeveling(PI) begin...
7699 00:25:25.415618 ==
7700 00:25:25.418617 Dram Type= 6, Freq= 0, CH_0, rank 1
7701 00:25:25.421536 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7702 00:25:25.421938 ==
7703 00:25:25.424807 Write leveling (Byte 0): 30 => 30
7704 00:25:25.428027 Write leveling (Byte 1): 26 => 26
7705 00:25:25.431215 DramcWriteLeveling(PI) end<-----
7706 00:25:25.431623
7707 00:25:25.431931 ==
7708 00:25:25.434820 Dram Type= 6, Freq= 0, CH_0, rank 1
7709 00:25:25.437858 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7710 00:25:25.438428 ==
7711 00:25:25.441089 [Gating] SW mode calibration
7712 00:25:25.447604 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7713 00:25:25.455099 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7714 00:25:25.457827 0 12 0 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 1)
7715 00:25:25.464229 0 12 4 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
7716 00:25:25.468129 0 12 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7717 00:25:25.471067 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7718 00:25:25.477819 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7719 00:25:25.481531 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7720 00:25:25.484558 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7721 00:25:25.491207 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7722 00:25:25.494538 0 13 0 | B1->B0 | 3434 2b2b | 1 0 | (1 0) (0 1)
7723 00:25:25.498086 0 13 4 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
7724 00:25:25.504582 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7725 00:25:25.507956 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7726 00:25:25.511059 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7727 00:25:25.517680 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7728 00:25:25.521167 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7729 00:25:25.524422 0 13 28 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
7730 00:25:25.527689 0 14 0 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
7731 00:25:25.533943 0 14 4 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
7732 00:25:25.537491 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7733 00:25:25.540717 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7734 00:25:25.547509 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7735 00:25:25.550736 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7736 00:25:25.554243 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7737 00:25:25.560648 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7738 00:25:25.563968 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7739 00:25:25.566984 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7740 00:25:25.573922 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7741 00:25:25.577163 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7742 00:25:25.580482 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7743 00:25:25.587293 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7744 00:25:25.590366 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7745 00:25:25.593655 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7746 00:25:25.600586 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7747 00:25:25.603483 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7748 00:25:25.606789 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7749 00:25:25.614684 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7750 00:25:25.617086 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7751 00:25:25.620620 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7752 00:25:25.626729 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7753 00:25:25.630156 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7754 00:25:25.633635 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7755 00:25:25.640059 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7756 00:25:25.643276 Total UI for P1: 0, mck2ui 16
7757 00:25:25.646605 best dqsien dly found for B0: ( 1, 0, 28)
7758 00:25:25.649794 Total UI for P1: 0, mck2ui 16
7759 00:25:25.653081 best dqsien dly found for B1: ( 1, 1, 0)
7760 00:25:25.656506 best DQS0 dly(MCK, UI, PI) = (1, 0, 28)
7761 00:25:25.659991 best DQS1 dly(MCK, UI, PI) = (1, 1, 0)
7762 00:25:25.660418
7763 00:25:25.662802 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 28)
7764 00:25:25.666045 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 0)
7765 00:25:25.669717 [Gating] SW calibration Done
7766 00:25:25.670146 ==
7767 00:25:25.673002 Dram Type= 6, Freq= 0, CH_0, rank 1
7768 00:25:25.676424 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7769 00:25:25.676859 ==
7770 00:25:25.680057 RX Vref Scan: 0
7771 00:25:25.680493
7772 00:25:25.680789 RX Vref 0 -> 0, step: 1
7773 00:25:25.681064
7774 00:25:25.682788 RX Delay 0 -> 252, step: 8
7775 00:25:25.686158 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7776 00:25:25.692664 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7777 00:25:25.696038 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7778 00:25:25.699711 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7779 00:25:25.702800 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
7780 00:25:25.706581 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7781 00:25:25.712978 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7782 00:25:25.716182 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7783 00:25:25.719727 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7784 00:25:25.722693 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7785 00:25:25.725848 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7786 00:25:25.732624 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7787 00:25:25.735714 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7788 00:25:25.739221 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7789 00:25:25.742935 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7790 00:25:25.749248 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7791 00:25:25.749650 ==
7792 00:25:25.752485 Dram Type= 6, Freq= 0, CH_0, rank 1
7793 00:25:25.755810 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7794 00:25:25.756203 ==
7795 00:25:25.756601 DQS Delay:
7796 00:25:25.759134 DQS0 = 0, DQS1 = 0
7797 00:25:25.759520 DQM Delay:
7798 00:25:25.762533 DQM0 = 130, DQM1 = 124
7799 00:25:25.762919 DQ Delay:
7800 00:25:25.765439 DQ0 =127, DQ1 =131, DQ2 =131, DQ3 =127
7801 00:25:25.768854 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
7802 00:25:25.772086 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =119
7803 00:25:25.776180 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =131
7804 00:25:25.776568
7805 00:25:25.778866
7806 00:25:25.779249 ==
7807 00:25:25.782476 Dram Type= 6, Freq= 0, CH_0, rank 1
7808 00:25:25.785462 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7809 00:25:25.785934 ==
7810 00:25:25.786280
7811 00:25:25.786567
7812 00:25:25.788523 TX Vref Scan disable
7813 00:25:25.788913 == TX Byte 0 ==
7814 00:25:25.796025 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7815 00:25:25.798495 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7816 00:25:25.798907 == TX Byte 1 ==
7817 00:25:25.805170 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7818 00:25:25.808617 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7819 00:25:25.809031 ==
7820 00:25:25.812387 Dram Type= 6, Freq= 0, CH_0, rank 1
7821 00:25:25.815498 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7822 00:25:25.815890 ==
7823 00:25:25.829931
7824 00:25:25.833501 TX Vref early break, caculate TX vref
7825 00:25:25.836294 TX Vref=16, minBit 1, minWin=22, winSum=373
7826 00:25:25.839730 TX Vref=18, minBit 9, minWin=22, winSum=384
7827 00:25:25.843180 TX Vref=20, minBit 1, minWin=23, winSum=389
7828 00:25:25.846240 TX Vref=22, minBit 9, minWin=23, winSum=399
7829 00:25:25.849818 TX Vref=24, minBit 8, minWin=24, winSum=404
7830 00:25:25.856519 TX Vref=26, minBit 8, minWin=24, winSum=408
7831 00:25:25.860011 TX Vref=28, minBit 8, minWin=24, winSum=410
7832 00:25:25.862782 TX Vref=30, minBit 8, minWin=24, winSum=411
7833 00:25:25.866173 TX Vref=32, minBit 8, minWin=23, winSum=402
7834 00:25:25.869460 TX Vref=34, minBit 8, minWin=22, winSum=391
7835 00:25:25.873140 TX Vref=36, minBit 6, minWin=23, winSum=386
7836 00:25:25.879717 [TxChooseVref] Worse bit 8, Min win 24, Win sum 411, Final Vref 30
7837 00:25:25.880110
7838 00:25:25.882800 Final TX Range 0 Vref 30
7839 00:25:25.883187
7840 00:25:25.883482 ==
7841 00:25:25.885816 Dram Type= 6, Freq= 0, CH_0, rank 1
7842 00:25:25.889466 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7843 00:25:25.889859 ==
7844 00:25:25.890160
7845 00:25:25.892650
7846 00:25:25.893033 TX Vref Scan disable
7847 00:25:25.899566 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7848 00:25:25.899958 == TX Byte 0 ==
7849 00:25:25.902501 u2DelayCellOfst[0]=10 cells (3 PI)
7850 00:25:25.905787 u2DelayCellOfst[1]=14 cells (4 PI)
7851 00:25:25.909312 u2DelayCellOfst[2]=10 cells (3 PI)
7852 00:25:25.912554 u2DelayCellOfst[3]=10 cells (3 PI)
7853 00:25:25.915841 u2DelayCellOfst[4]=7 cells (2 PI)
7854 00:25:25.919126 u2DelayCellOfst[5]=0 cells (0 PI)
7855 00:25:25.922306 u2DelayCellOfst[6]=18 cells (5 PI)
7856 00:25:25.926053 u2DelayCellOfst[7]=14 cells (4 PI)
7857 00:25:25.928961 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7858 00:25:25.932180 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7859 00:25:25.935560 == TX Byte 1 ==
7860 00:25:25.939136 u2DelayCellOfst[8]=0 cells (0 PI)
7861 00:25:25.942485 u2DelayCellOfst[9]=0 cells (0 PI)
7862 00:25:25.946013 u2DelayCellOfst[10]=7 cells (2 PI)
7863 00:25:25.946531 u2DelayCellOfst[11]=3 cells (1 PI)
7864 00:25:25.948815 u2DelayCellOfst[12]=14 cells (4 PI)
7865 00:25:25.952463 u2DelayCellOfst[13]=10 cells (3 PI)
7866 00:25:25.955871 u2DelayCellOfst[14]=18 cells (5 PI)
7867 00:25:25.959041 u2DelayCellOfst[15]=14 cells (4 PI)
7868 00:25:25.965616 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
7869 00:25:25.969427 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7870 00:25:25.969968 DramC Write-DBI on
7871 00:25:25.970506 ==
7872 00:25:25.972317 Dram Type= 6, Freq= 0, CH_0, rank 1
7873 00:25:25.978618 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7874 00:25:25.979138 ==
7875 00:25:25.979572
7876 00:25:25.980098
7877 00:25:25.980659 TX Vref Scan disable
7878 00:25:25.983152 == TX Byte 0 ==
7879 00:25:25.986400 Update DQM dly =729 (2 ,6, 25) DQM OEN =(3 ,3)
7880 00:25:25.989624 == TX Byte 1 ==
7881 00:25:25.993215 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
7882 00:25:25.996453 DramC Write-DBI off
7883 00:25:25.996843
7884 00:25:25.997141 [DATLAT]
7885 00:25:25.997416 Freq=1600, CH0 RK1
7886 00:25:25.997684
7887 00:25:25.999678 DATLAT Default: 0xe
7888 00:25:26.000083 0, 0xFFFF, sum = 0
7889 00:25:26.002893 1, 0xFFFF, sum = 0
7890 00:25:26.006126 2, 0xFFFF, sum = 0
7891 00:25:26.006580 3, 0xFFFF, sum = 0
7892 00:25:26.009636 4, 0xFFFF, sum = 0
7893 00:25:26.010178 5, 0xFFFF, sum = 0
7894 00:25:26.012820 6, 0xFFFF, sum = 0
7895 00:25:26.013327 7, 0xFFFF, sum = 0
7896 00:25:26.016325 8, 0xFFFF, sum = 0
7897 00:25:26.016872 9, 0xFFFF, sum = 0
7898 00:25:26.019659 10, 0xFFFF, sum = 0
7899 00:25:26.020306 11, 0xFFFF, sum = 0
7900 00:25:26.022912 12, 0xFFF, sum = 0
7901 00:25:26.023433 13, 0x0, sum = 1
7902 00:25:26.025921 14, 0x0, sum = 2
7903 00:25:26.026494 15, 0x0, sum = 3
7904 00:25:26.029886 16, 0x0, sum = 4
7905 00:25:26.030507 best_step = 14
7906 00:25:26.030984
7907 00:25:26.031447 ==
7908 00:25:26.033166 Dram Type= 6, Freq= 0, CH_0, rank 1
7909 00:25:26.036100 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7910 00:25:26.039546 ==
7911 00:25:26.039934 RX Vref Scan: 0
7912 00:25:26.040231
7913 00:25:26.042855 RX Vref 0 -> 0, step: 1
7914 00:25:26.043241
7915 00:25:26.043539 RX Delay 11 -> 252, step: 4
7916 00:25:26.049750 iDelay=195, Bit 0, Center 122 (67 ~ 178) 112
7917 00:25:26.053202 iDelay=195, Bit 1, Center 132 (79 ~ 186) 108
7918 00:25:26.056426 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
7919 00:25:26.059828 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
7920 00:25:26.063309 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
7921 00:25:26.069679 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
7922 00:25:26.072828 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
7923 00:25:26.076309 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
7924 00:25:26.079722 iDelay=195, Bit 8, Center 108 (55 ~ 162) 108
7925 00:25:26.083120 iDelay=195, Bit 9, Center 106 (51 ~ 162) 112
7926 00:25:26.089578 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
7927 00:25:26.092996 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
7928 00:25:26.095919 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
7929 00:25:26.099447 iDelay=195, Bit 13, Center 128 (75 ~ 182) 108
7930 00:25:26.106089 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
7931 00:25:26.109863 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
7932 00:25:26.109938 ==
7933 00:25:26.112581 Dram Type= 6, Freq= 0, CH_0, rank 1
7934 00:25:26.115905 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7935 00:25:26.115982 ==
7936 00:25:26.119011 DQS Delay:
7937 00:25:26.119087 DQS0 = 0, DQS1 = 0
7938 00:25:26.119145 DQM Delay:
7939 00:25:26.122678 DQM0 = 128, DQM1 = 120
7940 00:25:26.122754 DQ Delay:
7941 00:25:26.125687 DQ0 =122, DQ1 =132, DQ2 =126, DQ3 =124
7942 00:25:26.129041 DQ4 =130, DQ5 =120, DQ6 =136, DQ7 =138
7943 00:25:26.132247 DQ8 =108, DQ9 =106, DQ10 =122, DQ11 =112
7944 00:25:26.138941 DQ12 =126, DQ13 =128, DQ14 =134, DQ15 =130
7945 00:25:26.139041
7946 00:25:26.139127
7947 00:25:26.139211
7948 00:25:26.142269 [DramC_TX_OE_Calibration] TA2
7949 00:25:26.142349 Original DQ_B0 (3 6) =30, OEN = 27
7950 00:25:26.146002 Original DQ_B1 (3 6) =30, OEN = 27
7951 00:25:26.149310 24, 0x0, End_B0=24 End_B1=24
7952 00:25:26.152522 25, 0x0, End_B0=25 End_B1=25
7953 00:25:26.155445 26, 0x0, End_B0=26 End_B1=26
7954 00:25:26.159397 27, 0x0, End_B0=27 End_B1=27
7955 00:25:26.159464 28, 0x0, End_B0=28 End_B1=28
7956 00:25:26.162309 29, 0x0, End_B0=29 End_B1=29
7957 00:25:26.165521 30, 0x0, End_B0=30 End_B1=30
7958 00:25:26.169014 31, 0x4141, End_B0=30 End_B1=30
7959 00:25:26.172116 Byte0 end_step=30 best_step=27
7960 00:25:26.172209 Byte1 end_step=30 best_step=27
7961 00:25:26.175586 Byte0 TX OE(2T, 0.5T) = (3, 3)
7962 00:25:26.178682 Byte1 TX OE(2T, 0.5T) = (3, 3)
7963 00:25:26.178755
7964 00:25:26.178811
7965 00:25:26.188747 [DQSOSCAuto] RK1, (LSB)MR18= 0x2626, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
7966 00:25:26.188844 CH0 RK1: MR19=303, MR18=2626
7967 00:25:26.195319 CH0_RK1: MR19=0x303, MR18=0x2626, DQSOSC=390, MR23=63, INC=24, DEC=16
7968 00:25:26.198496 [RxdqsGatingPostProcess] freq 1600
7969 00:25:26.205617 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
7970 00:25:26.208982 Pre-setting of DQS Precalculation
7971 00:25:26.212351 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7972 00:25:26.212440 ==
7973 00:25:26.215405 Dram Type= 6, Freq= 0, CH_1, rank 0
7974 00:25:26.221908 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7975 00:25:26.222005 ==
7976 00:25:26.225232 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7977 00:25:26.232048 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
7978 00:25:26.235914 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
7979 00:25:26.241598 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7980 00:25:26.248891 [CA 0] Center 41 (11~71) winsize 61
7981 00:25:26.252220 [CA 1] Center 40 (10~71) winsize 62
7982 00:25:26.255446 [CA 2] Center 36 (7~66) winsize 60
7983 00:25:26.258616 [CA 3] Center 35 (6~65) winsize 60
7984 00:25:26.261913 [CA 4] Center 33 (3~63) winsize 61
7985 00:25:26.265629 [CA 5] Center 33 (4~63) winsize 60
7986 00:25:26.265731
7987 00:25:26.268860 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7988 00:25:26.269025
7989 00:25:26.271945 [CATrainingPosCal] consider 1 rank data
7990 00:25:26.275681 u2DelayCellTimex100 = 271/100 ps
7991 00:25:26.278595 CA0 delay=41 (11~71),Diff = 8 PI (28 cell)
7992 00:25:26.285377 CA1 delay=40 (10~71),Diff = 7 PI (25 cell)
7993 00:25:26.288893 CA2 delay=36 (7~66),Diff = 3 PI (10 cell)
7994 00:25:26.291958 CA3 delay=35 (6~65),Diff = 2 PI (7 cell)
7995 00:25:26.295516 CA4 delay=33 (3~63),Diff = 0 PI (0 cell)
7996 00:25:26.298782 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
7997 00:25:26.299003
7998 00:25:26.301939 CA PerBit enable=1, Macro0, CA PI delay=33
7999 00:25:26.302251
8000 00:25:26.305786 [CBTSetCACLKResult] CA Dly = 33
8001 00:25:26.308714 CS Dly: 8 (0~39)
8002 00:25:26.312023 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8003 00:25:26.315292 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8004 00:25:26.315684 ==
8005 00:25:26.319023 Dram Type= 6, Freq= 0, CH_1, rank 1
8006 00:25:26.322087 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8007 00:25:26.325514 ==
8008 00:25:26.328872 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8009 00:25:26.332084 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8010 00:25:26.338730 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8011 00:25:26.342051 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8012 00:25:26.351493 [CA 0] Center 41 (11~71) winsize 61
8013 00:25:26.354935 [CA 1] Center 41 (11~71) winsize 61
8014 00:25:26.358522 [CA 2] Center 36 (7~66) winsize 60
8015 00:25:26.361589 [CA 3] Center 36 (7~65) winsize 59
8016 00:25:26.364713 [CA 4] Center 34 (5~64) winsize 60
8017 00:25:26.367915 [CA 5] Center 34 (5~64) winsize 60
8018 00:25:26.368303
8019 00:25:26.371761 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8020 00:25:26.372231
8021 00:25:26.374728 [CATrainingPosCal] consider 2 rank data
8022 00:25:26.377908 u2DelayCellTimex100 = 271/100 ps
8023 00:25:26.381382 CA0 delay=41 (11~71),Diff = 7 PI (25 cell)
8024 00:25:26.388357 CA1 delay=41 (11~71),Diff = 7 PI (25 cell)
8025 00:25:26.391423 CA2 delay=36 (7~66),Diff = 2 PI (7 cell)
8026 00:25:26.394934 CA3 delay=36 (7~65),Diff = 2 PI (7 cell)
8027 00:25:26.397618 CA4 delay=34 (5~63),Diff = 0 PI (0 cell)
8028 00:25:26.401312 CA5 delay=34 (5~63),Diff = 0 PI (0 cell)
8029 00:25:26.401793
8030 00:25:26.404650 CA PerBit enable=1, Macro0, CA PI delay=34
8031 00:25:26.405143
8032 00:25:26.407857 [CBTSetCACLKResult] CA Dly = 34
8033 00:25:26.411255 CS Dly: 8 (0~40)
8034 00:25:26.414551 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8035 00:25:26.418026 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8036 00:25:26.418535
8037 00:25:26.421169 ----->DramcWriteLeveling(PI) begin...
8038 00:25:26.421642 ==
8039 00:25:26.424670 Dram Type= 6, Freq= 0, CH_1, rank 0
8040 00:25:26.431253 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8041 00:25:26.431722 ==
8042 00:25:26.434590 Write leveling (Byte 0): 22 => 22
8043 00:25:26.434978 Write leveling (Byte 1): 22 => 22
8044 00:25:26.437677 DramcWriteLeveling(PI) end<-----
8045 00:25:26.438062
8046 00:25:26.438407 ==
8047 00:25:26.441403 Dram Type= 6, Freq= 0, CH_1, rank 0
8048 00:25:26.447781 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8049 00:25:26.448250 ==
8050 00:25:26.451338 [Gating] SW mode calibration
8051 00:25:26.457464 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8052 00:25:26.461015 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8053 00:25:26.467935 0 12 0 | B1->B0 | 3131 3434 | 1 1 | (0 0) (1 1)
8054 00:25:26.470886 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8055 00:25:26.473873 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8056 00:25:26.481232 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8057 00:25:26.484113 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8058 00:25:26.487399 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8059 00:25:26.493898 0 12 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
8060 00:25:26.497103 0 12 28 | B1->B0 | 3434 2525 | 1 0 | (1 0) (0 0)
8061 00:25:26.500642 0 13 0 | B1->B0 | 2e2e 2323 | 0 0 | (1 0) (0 0)
8062 00:25:26.507267 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8063 00:25:26.510430 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8064 00:25:26.513823 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8065 00:25:26.520631 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8066 00:25:26.524014 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8067 00:25:26.527098 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8068 00:25:26.530400 0 13 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8069 00:25:26.537379 0 14 0 | B1->B0 | 3131 4646 | 0 0 | (0 0) (0 0)
8070 00:25:26.540584 0 14 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8071 00:25:26.543969 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8072 00:25:26.550378 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8073 00:25:26.553574 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8074 00:25:26.557161 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8075 00:25:26.563678 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8076 00:25:26.567062 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8077 00:25:26.570599 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8078 00:25:26.577203 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8079 00:25:26.580273 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8080 00:25:26.583612 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8081 00:25:26.590599 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8082 00:25:26.593703 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8083 00:25:26.596876 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8084 00:25:26.603954 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8085 00:25:26.607243 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8086 00:25:26.610150 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8087 00:25:26.616830 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8088 00:25:26.620288 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8089 00:25:26.623343 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8090 00:25:26.629889 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8091 00:25:26.633471 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8092 00:25:26.636803 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8093 00:25:26.643146 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8094 00:25:26.643537 Total UI for P1: 0, mck2ui 16
8095 00:25:26.650357 best dqsien dly found for B0: ( 1, 0, 26)
8096 00:25:26.653525 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8097 00:25:26.656967 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8098 00:25:26.659861 Total UI for P1: 0, mck2ui 16
8099 00:25:26.663972 best dqsien dly found for B1: ( 1, 1, 2)
8100 00:25:26.666709 best DQS0 dly(MCK, UI, PI) = (1, 0, 26)
8101 00:25:26.669744 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
8102 00:25:26.670175
8103 00:25:26.673569 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 26)
8104 00:25:26.680531 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
8105 00:25:26.681051 [Gating] SW calibration Done
8106 00:25:26.681403 ==
8107 00:25:26.683259 Dram Type= 6, Freq= 0, CH_1, rank 0
8108 00:25:26.689902 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8109 00:25:26.690759 ==
8110 00:25:26.691372 RX Vref Scan: 0
8111 00:25:26.691948
8112 00:25:26.693486 RX Vref 0 -> 0, step: 1
8113 00:25:26.694097
8114 00:25:26.696354 RX Delay 0 -> 252, step: 8
8115 00:25:26.699759 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8116 00:25:26.702963 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8117 00:25:26.706111 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8118 00:25:26.709592 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8119 00:25:26.716188 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8120 00:25:26.719459 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8121 00:25:26.723419 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8122 00:25:26.726377 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8123 00:25:26.729421 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8124 00:25:26.736245 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8125 00:25:26.739552 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8126 00:25:26.743018 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8127 00:25:26.746101 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8128 00:25:26.752606 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8129 00:25:26.755943 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8130 00:25:26.759616 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8131 00:25:26.760005 ==
8132 00:25:26.763017 Dram Type= 6, Freq= 0, CH_1, rank 0
8133 00:25:26.766323 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8134 00:25:26.766761 ==
8135 00:25:26.769280 DQS Delay:
8136 00:25:26.769698 DQS0 = 0, DQS1 = 0
8137 00:25:26.772777 DQM Delay:
8138 00:25:26.773166 DQM0 = 130, DQM1 = 125
8139 00:25:26.773468 DQ Delay:
8140 00:25:26.775804 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =127
8141 00:25:26.782650 DQ4 =131, DQ5 =143, DQ6 =135, DQ7 =127
8142 00:25:26.786087 DQ8 =107, DQ9 =115, DQ10 =123, DQ11 =115
8143 00:25:26.789586 DQ12 =131, DQ13 =139, DQ14 =135, DQ15 =135
8144 00:25:26.790050
8145 00:25:26.790405
8146 00:25:26.790688 ==
8147 00:25:26.792756 Dram Type= 6, Freq= 0, CH_1, rank 0
8148 00:25:26.796381 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8149 00:25:26.796774 ==
8150 00:25:26.797075
8151 00:25:26.797349
8152 00:25:26.799241 TX Vref Scan disable
8153 00:25:26.802974 == TX Byte 0 ==
8154 00:25:26.806244 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8155 00:25:26.809342 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8156 00:25:26.812987 == TX Byte 1 ==
8157 00:25:26.815977 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8158 00:25:26.819421 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8159 00:25:26.819946 ==
8160 00:25:26.822531 Dram Type= 6, Freq= 0, CH_1, rank 0
8161 00:25:26.825534 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8162 00:25:26.828705 ==
8163 00:25:26.840718
8164 00:25:26.843550 TX Vref early break, caculate TX vref
8165 00:25:26.847368 TX Vref=16, minBit 1, minWin=21, winSum=366
8166 00:25:26.850654 TX Vref=18, minBit 3, minWin=22, winSum=374
8167 00:25:26.853609 TX Vref=20, minBit 0, minWin=23, winSum=384
8168 00:25:26.856827 TX Vref=22, minBit 3, minWin=23, winSum=392
8169 00:25:26.860594 TX Vref=24, minBit 1, minWin=24, winSum=402
8170 00:25:26.866840 TX Vref=26, minBit 3, minWin=24, winSum=409
8171 00:25:26.870344 TX Vref=28, minBit 0, minWin=24, winSum=412
8172 00:25:26.873411 TX Vref=30, minBit 3, minWin=23, winSum=405
8173 00:25:26.876559 TX Vref=32, minBit 1, minWin=24, winSum=398
8174 00:25:26.880344 TX Vref=34, minBit 3, minWin=23, winSum=392
8175 00:25:26.883838 TX Vref=36, minBit 1, minWin=22, winSum=375
8176 00:25:26.890115 [TxChooseVref] Worse bit 0, Min win 24, Win sum 412, Final Vref 28
8177 00:25:26.890776
8178 00:25:26.893593 Final TX Range 0 Vref 28
8179 00:25:26.894248
8180 00:25:26.894719 ==
8181 00:25:26.896816 Dram Type= 6, Freq= 0, CH_1, rank 0
8182 00:25:26.900152 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8183 00:25:26.900750 ==
8184 00:25:26.903158
8185 00:25:26.903719
8186 00:25:26.904229 TX Vref Scan disable
8187 00:25:26.909699 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8188 00:25:26.910249 == TX Byte 0 ==
8189 00:25:26.912916 u2DelayCellOfst[0]=14 cells (4 PI)
8190 00:25:26.916786 u2DelayCellOfst[1]=10 cells (3 PI)
8191 00:25:26.919576 u2DelayCellOfst[2]=0 cells (0 PI)
8192 00:25:26.922833 u2DelayCellOfst[3]=3 cells (1 PI)
8193 00:25:26.926346 u2DelayCellOfst[4]=7 cells (2 PI)
8194 00:25:26.929508 u2DelayCellOfst[5]=14 cells (4 PI)
8195 00:25:26.933087 u2DelayCellOfst[6]=14 cells (4 PI)
8196 00:25:26.936374 u2DelayCellOfst[7]=3 cells (1 PI)
8197 00:25:26.939558 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8198 00:25:26.943109 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8199 00:25:26.946158 == TX Byte 1 ==
8200 00:25:26.949550 u2DelayCellOfst[8]=0 cells (0 PI)
8201 00:25:26.953172 u2DelayCellOfst[9]=7 cells (2 PI)
8202 00:25:26.953595 u2DelayCellOfst[10]=10 cells (3 PI)
8203 00:25:26.956306 u2DelayCellOfst[11]=3 cells (1 PI)
8204 00:25:26.959540 u2DelayCellOfst[12]=18 cells (5 PI)
8205 00:25:26.962833 u2DelayCellOfst[13]=18 cells (5 PI)
8206 00:25:26.966585 u2DelayCellOfst[14]=18 cells (5 PI)
8207 00:25:26.969440 u2DelayCellOfst[15]=18 cells (5 PI)
8208 00:25:26.976434 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8209 00:25:26.979558 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8210 00:25:26.980040 DramC Write-DBI on
8211 00:25:26.980502 ==
8212 00:25:26.982659 Dram Type= 6, Freq= 0, CH_1, rank 0
8213 00:25:26.989487 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8214 00:25:26.990025 ==
8215 00:25:26.990513
8216 00:25:26.990931
8217 00:25:26.991353 TX Vref Scan disable
8218 00:25:26.993934 == TX Byte 0 ==
8219 00:25:26.996730 Update DQM dly =718 (2 ,6, 14) DQM OEN =(3 ,3)
8220 00:25:27.000240 == TX Byte 1 ==
8221 00:25:27.003287 Update DQM dly =717 (2 ,6, 13) DQM OEN =(3 ,3)
8222 00:25:27.006876 DramC Write-DBI off
8223 00:25:27.007259
8224 00:25:27.007560 [DATLAT]
8225 00:25:27.007837 Freq=1600, CH1 RK0
8226 00:25:27.008104
8227 00:25:27.010296 DATLAT Default: 0xf
8228 00:25:27.010683 0, 0xFFFF, sum = 0
8229 00:25:27.013762 1, 0xFFFF, sum = 0
8230 00:25:27.017069 2, 0xFFFF, sum = 0
8231 00:25:27.017465 3, 0xFFFF, sum = 0
8232 00:25:27.019883 4, 0xFFFF, sum = 0
8233 00:25:27.020381 5, 0xFFFF, sum = 0
8234 00:25:27.023297 6, 0xFFFF, sum = 0
8235 00:25:27.023813 7, 0xFFFF, sum = 0
8236 00:25:27.026574 8, 0xFFFF, sum = 0
8237 00:25:27.026971 9, 0xFFFF, sum = 0
8238 00:25:27.030104 10, 0xFFFF, sum = 0
8239 00:25:27.030569 11, 0xFFFF, sum = 0
8240 00:25:27.033205 12, 0xF7F, sum = 0
8241 00:25:27.033649 13, 0x0, sum = 1
8242 00:25:27.036335 14, 0x0, sum = 2
8243 00:25:27.036765 15, 0x0, sum = 3
8244 00:25:27.039725 16, 0x0, sum = 4
8245 00:25:27.040204 best_step = 14
8246 00:25:27.040613
8247 00:25:27.041021 ==
8248 00:25:27.043021 Dram Type= 6, Freq= 0, CH_1, rank 0
8249 00:25:27.046603 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8250 00:25:27.049728 ==
8251 00:25:27.050119 RX Vref Scan: 1
8252 00:25:27.050465
8253 00:25:27.053064 Set Vref Range= 24 -> 127
8254 00:25:27.053448
8255 00:25:27.056692 RX Vref 24 -> 127, step: 1
8256 00:25:27.057116
8257 00:25:27.057461 RX Delay 3 -> 252, step: 4
8258 00:25:27.057769
8259 00:25:27.059642 Set Vref, RX VrefLevel [Byte0]: 24
8260 00:25:27.063876 [Byte1]: 24
8261 00:25:27.066620
8262 00:25:27.067030 Set Vref, RX VrefLevel [Byte0]: 25
8263 00:25:27.070019 [Byte1]: 25
8264 00:25:27.074396
8265 00:25:27.074857 Set Vref, RX VrefLevel [Byte0]: 26
8266 00:25:27.077617 [Byte1]: 26
8267 00:25:27.081815
8268 00:25:27.082375 Set Vref, RX VrefLevel [Byte0]: 27
8269 00:25:27.085651 [Byte1]: 27
8270 00:25:27.089599
8271 00:25:27.090119 Set Vref, RX VrefLevel [Byte0]: 28
8272 00:25:27.092936 [Byte1]: 28
8273 00:25:27.097591
8274 00:25:27.098037 Set Vref, RX VrefLevel [Byte0]: 29
8275 00:25:27.100517 [Byte1]: 29
8276 00:25:27.105094
8277 00:25:27.105604 Set Vref, RX VrefLevel [Byte0]: 30
8278 00:25:27.108194 [Byte1]: 30
8279 00:25:27.112601
8280 00:25:27.113128 Set Vref, RX VrefLevel [Byte0]: 31
8281 00:25:27.115848 [Byte1]: 31
8282 00:25:27.120434
8283 00:25:27.120816 Set Vref, RX VrefLevel [Byte0]: 32
8284 00:25:27.123665 [Byte1]: 32
8285 00:25:27.128259
8286 00:25:27.128728 Set Vref, RX VrefLevel [Byte0]: 33
8287 00:25:27.132238 [Byte1]: 33
8288 00:25:27.135679
8289 00:25:27.136109 Set Vref, RX VrefLevel [Byte0]: 34
8290 00:25:27.138916 [Byte1]: 34
8291 00:25:27.143579
8292 00:25:27.144071 Set Vref, RX VrefLevel [Byte0]: 35
8293 00:25:27.146316 [Byte1]: 35
8294 00:25:27.151025
8295 00:25:27.151409 Set Vref, RX VrefLevel [Byte0]: 36
8296 00:25:27.154069 [Byte1]: 36
8297 00:25:27.158277
8298 00:25:27.158668 Set Vref, RX VrefLevel [Byte0]: 37
8299 00:25:27.161809 [Byte1]: 37
8300 00:25:27.166546
8301 00:25:27.167076 Set Vref, RX VrefLevel [Byte0]: 38
8302 00:25:27.169636 [Byte1]: 38
8303 00:25:27.173816
8304 00:25:27.174378 Set Vref, RX VrefLevel [Byte0]: 39
8305 00:25:27.177122 [Byte1]: 39
8306 00:25:27.182001
8307 00:25:27.182506 Set Vref, RX VrefLevel [Byte0]: 40
8308 00:25:27.184768 [Byte1]: 40
8309 00:25:27.189108
8310 00:25:27.189643 Set Vref, RX VrefLevel [Byte0]: 41
8311 00:25:27.192645 [Byte1]: 41
8312 00:25:27.196762
8313 00:25:27.197279 Set Vref, RX VrefLevel [Byte0]: 42
8314 00:25:27.200201 [Byte1]: 42
8315 00:25:27.204511
8316 00:25:27.205012 Set Vref, RX VrefLevel [Byte0]: 43
8317 00:25:27.207862 [Byte1]: 43
8318 00:25:27.212088
8319 00:25:27.212470 Set Vref, RX VrefLevel [Byte0]: 44
8320 00:25:27.215649 [Byte1]: 44
8321 00:25:27.219725
8322 00:25:27.220106 Set Vref, RX VrefLevel [Byte0]: 45
8323 00:25:27.223940 [Byte1]: 45
8324 00:25:27.227554
8325 00:25:27.228085 Set Vref, RX VrefLevel [Byte0]: 46
8326 00:25:27.230687 [Byte1]: 46
8327 00:25:27.235527
8328 00:25:27.235991 Set Vref, RX VrefLevel [Byte0]: 47
8329 00:25:27.238423 [Byte1]: 47
8330 00:25:27.242670
8331 00:25:27.243054 Set Vref, RX VrefLevel [Byte0]: 48
8332 00:25:27.246420 [Byte1]: 48
8333 00:25:27.250942
8334 00:25:27.251401 Set Vref, RX VrefLevel [Byte0]: 49
8335 00:25:27.254127 [Byte1]: 49
8336 00:25:27.257969
8337 00:25:27.258462 Set Vref, RX VrefLevel [Byte0]: 50
8338 00:25:27.261549 [Byte1]: 50
8339 00:25:27.265861
8340 00:25:27.266362 Set Vref, RX VrefLevel [Byte0]: 51
8341 00:25:27.268902 [Byte1]: 51
8342 00:25:27.273518
8343 00:25:27.274117 Set Vref, RX VrefLevel [Byte0]: 52
8344 00:25:27.276629 [Byte1]: 52
8345 00:25:27.281088
8346 00:25:27.281512 Set Vref, RX VrefLevel [Byte0]: 53
8347 00:25:27.284443 [Byte1]: 53
8348 00:25:27.288825
8349 00:25:27.289320 Set Vref, RX VrefLevel [Byte0]: 54
8350 00:25:27.291797 [Byte1]: 54
8351 00:25:27.296526
8352 00:25:27.296970 Set Vref, RX VrefLevel [Byte0]: 55
8353 00:25:27.299565 [Byte1]: 55
8354 00:25:27.304063
8355 00:25:27.304515 Set Vref, RX VrefLevel [Byte0]: 56
8356 00:25:27.307454 [Byte1]: 56
8357 00:25:27.311975
8358 00:25:27.312484 Set Vref, RX VrefLevel [Byte0]: 57
8359 00:25:27.315110 [Byte1]: 57
8360 00:25:27.319280
8361 00:25:27.319684 Set Vref, RX VrefLevel [Byte0]: 58
8362 00:25:27.322699 [Byte1]: 58
8363 00:25:27.326818
8364 00:25:27.327202 Set Vref, RX VrefLevel [Byte0]: 59
8365 00:25:27.329966 [Byte1]: 59
8366 00:25:27.334404
8367 00:25:27.334846 Set Vref, RX VrefLevel [Byte0]: 60
8368 00:25:27.337472 [Byte1]: 60
8369 00:25:27.341951
8370 00:25:27.342469 Set Vref, RX VrefLevel [Byte0]: 61
8371 00:25:27.345452 [Byte1]: 61
8372 00:25:27.349938
8373 00:25:27.350472 Set Vref, RX VrefLevel [Byte0]: 62
8374 00:25:27.352998 [Byte1]: 62
8375 00:25:27.357541
8376 00:25:27.357950 Set Vref, RX VrefLevel [Byte0]: 63
8377 00:25:27.361046 [Byte1]: 63
8378 00:25:27.364987
8379 00:25:27.365276 Set Vref, RX VrefLevel [Byte0]: 64
8380 00:25:27.368590 [Byte1]: 64
8381 00:25:27.372857
8382 00:25:27.373258 Set Vref, RX VrefLevel [Byte0]: 65
8383 00:25:27.375647 [Byte1]: 65
8384 00:25:27.380296
8385 00:25:27.380571 Set Vref, RX VrefLevel [Byte0]: 66
8386 00:25:27.384195 [Byte1]: 66
8387 00:25:27.388459
8388 00:25:27.388827 Set Vref, RX VrefLevel [Byte0]: 67
8389 00:25:27.392326 [Byte1]: 67
8390 00:25:27.395533
8391 00:25:27.395835 Set Vref, RX VrefLevel [Byte0]: 68
8392 00:25:27.399118 [Byte1]: 68
8393 00:25:27.403469
8394 00:25:27.403760 Set Vref, RX VrefLevel [Byte0]: 69
8395 00:25:27.406795 [Byte1]: 69
8396 00:25:27.410898
8397 00:25:27.411209 Set Vref, RX VrefLevel [Byte0]: 70
8398 00:25:27.414486 [Byte1]: 70
8399 00:25:27.418879
8400 00:25:27.419179 Set Vref, RX VrefLevel [Byte0]: 71
8401 00:25:27.421808 [Byte1]: 71
8402 00:25:27.426268
8403 00:25:27.426544 Set Vref, RX VrefLevel [Byte0]: 72
8404 00:25:27.429864 [Byte1]: 72
8405 00:25:27.433665
8406 00:25:27.433937 Set Vref, RX VrefLevel [Byte0]: 73
8407 00:25:27.437744 [Byte1]: 73
8408 00:25:27.441589
8409 00:25:27.441980 Set Vref, RX VrefLevel [Byte0]: 74
8410 00:25:27.444783 [Byte1]: 74
8411 00:25:27.449748
8412 00:25:27.450250 Set Vref, RX VrefLevel [Byte0]: 75
8413 00:25:27.452495 [Byte1]: 75
8414 00:25:27.457239
8415 00:25:27.457618 Final RX Vref Byte 0 = 59 to rank0
8416 00:25:27.460303 Final RX Vref Byte 1 = 52 to rank0
8417 00:25:27.463833 Final RX Vref Byte 0 = 59 to rank1
8418 00:25:27.467099 Final RX Vref Byte 1 = 52 to rank1==
8419 00:25:27.470473 Dram Type= 6, Freq= 0, CH_1, rank 0
8420 00:25:27.476916 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8421 00:25:27.477306 ==
8422 00:25:27.477604 DQS Delay:
8423 00:25:27.477878 DQS0 = 0, DQS1 = 0
8424 00:25:27.480039 DQM Delay:
8425 00:25:27.480421 DQM0 = 128, DQM1 = 122
8426 00:25:27.483612 DQ Delay:
8427 00:25:27.486678 DQ0 =132, DQ1 =122, DQ2 =118, DQ3 =126
8428 00:25:27.490167 DQ4 =130, DQ5 =138, DQ6 =138, DQ7 =126
8429 00:25:27.493340 DQ8 =106, DQ9 =114, DQ10 =124, DQ11 =112
8430 00:25:27.496716 DQ12 =130, DQ13 =134, DQ14 =132, DQ15 =130
8431 00:25:27.497275
8432 00:25:27.497641
8433 00:25:27.498099
8434 00:25:27.499916 [DramC_TX_OE_Calibration] TA2
8435 00:25:27.503196 Original DQ_B0 (3 6) =30, OEN = 27
8436 00:25:27.506576 Original DQ_B1 (3 6) =30, OEN = 27
8437 00:25:27.509756 24, 0x0, End_B0=24 End_B1=24
8438 00:25:27.510149 25, 0x0, End_B0=25 End_B1=25
8439 00:25:27.513459 26, 0x0, End_B0=26 End_B1=26
8440 00:25:27.516472 27, 0x0, End_B0=27 End_B1=27
8441 00:25:27.520206 28, 0x0, End_B0=28 End_B1=28
8442 00:25:27.522940 29, 0x0, End_B0=29 End_B1=29
8443 00:25:27.523358 30, 0x0, End_B0=30 End_B1=30
8444 00:25:27.526541 31, 0x4141, End_B0=30 End_B1=30
8445 00:25:27.529624 Byte0 end_step=30 best_step=27
8446 00:25:27.533040 Byte1 end_step=30 best_step=27
8447 00:25:27.536318 Byte0 TX OE(2T, 0.5T) = (3, 3)
8448 00:25:27.539897 Byte1 TX OE(2T, 0.5T) = (3, 3)
8449 00:25:27.540285
8450 00:25:27.540580
8451 00:25:27.546829 [DQSOSCAuto] RK0, (LSB)MR18= 0x2929, (MSB)MR19= 0x303, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
8452 00:25:27.549697 CH1 RK0: MR19=303, MR18=2929
8453 00:25:27.556459 CH1_RK0: MR19=0x303, MR18=0x2929, DQSOSC=389, MR23=63, INC=24, DEC=16
8454 00:25:27.556949
8455 00:25:27.560389 ----->DramcWriteLeveling(PI) begin...
8456 00:25:27.560780 ==
8457 00:25:27.563291 Dram Type= 6, Freq= 0, CH_1, rank 1
8458 00:25:27.566306 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8459 00:25:27.566699 ==
8460 00:25:27.569718 Write leveling (Byte 0): 21 => 21
8461 00:25:27.573000 Write leveling (Byte 1): 19 => 19
8462 00:25:27.576294 DramcWriteLeveling(PI) end<-----
8463 00:25:27.576700
8464 00:25:27.577008 ==
8465 00:25:27.579901 Dram Type= 6, Freq= 0, CH_1, rank 1
8466 00:25:27.582719 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8467 00:25:27.583163 ==
8468 00:25:27.586153 [Gating] SW mode calibration
8469 00:25:27.592784 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8470 00:25:27.599750 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8471 00:25:27.602726 0 12 0 | B1->B0 | 3333 3434 | 1 1 | (0 0) (1 1)
8472 00:25:27.609064 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8473 00:25:27.612523 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8474 00:25:27.616212 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8475 00:25:27.622537 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8476 00:25:27.625999 0 12 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8477 00:25:27.629105 0 12 24 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8478 00:25:27.632813 0 12 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8479 00:25:27.639544 0 13 0 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
8480 00:25:27.642773 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8481 00:25:27.646476 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8482 00:25:27.652965 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8483 00:25:27.656293 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8484 00:25:27.659287 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8485 00:25:27.665665 0 13 24 | B1->B0 | 2323 4040 | 0 0 | (0 0) (1 1)
8486 00:25:27.669093 0 13 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8487 00:25:27.672970 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8488 00:25:27.678893 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8489 00:25:27.682361 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8490 00:25:27.685477 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8491 00:25:27.692304 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8492 00:25:27.695745 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8493 00:25:27.699101 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8494 00:25:27.705944 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8495 00:25:27.708964 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8496 00:25:27.712250 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8497 00:25:27.719172 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8498 00:25:27.722539 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8499 00:25:27.725421 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8500 00:25:27.732194 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8501 00:25:27.735321 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8502 00:25:27.738893 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8503 00:25:27.745379 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8504 00:25:27.748956 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8505 00:25:27.752087 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8506 00:25:27.759302 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8507 00:25:27.762851 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8508 00:25:27.765860 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8509 00:25:27.772246 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8510 00:25:27.775982 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8511 00:25:27.778556 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8512 00:25:27.782063 Total UI for P1: 0, mck2ui 16
8513 00:25:27.785927 best dqsien dly found for B0: ( 1, 0, 26)
8514 00:25:27.788922 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8515 00:25:27.792062 Total UI for P1: 0, mck2ui 16
8516 00:25:27.795058 best dqsien dly found for B1: ( 1, 0, 30)
8517 00:25:27.798748 best DQS0 dly(MCK, UI, PI) = (1, 0, 26)
8518 00:25:27.804990 best DQS1 dly(MCK, UI, PI) = (1, 0, 30)
8519 00:25:27.805465
8520 00:25:27.808530 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 26)
8521 00:25:27.811630 best DQS1 P1 dly(MCK, UI, PI) = (1, 4, 30)
8522 00:25:27.815115 [Gating] SW calibration Done
8523 00:25:27.815720 ==
8524 00:25:27.818274 Dram Type= 6, Freq= 0, CH_1, rank 1
8525 00:25:27.821512 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8526 00:25:27.821964 ==
8527 00:25:27.824767 RX Vref Scan: 0
8528 00:25:27.825192
8529 00:25:27.825516 RX Vref 0 -> 0, step: 1
8530 00:25:27.825817
8531 00:25:27.828260 RX Delay 0 -> 252, step: 8
8532 00:25:27.831664 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8533 00:25:27.834682 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8534 00:25:27.841228 iDelay=200, Bit 2, Center 115 (56 ~ 175) 120
8535 00:25:27.844809 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8536 00:25:27.848251 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8537 00:25:27.851389 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8538 00:25:27.854559 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8539 00:25:27.861194 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8540 00:25:27.864735 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8541 00:25:27.868210 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8542 00:25:27.871252 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8543 00:25:27.874563 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8544 00:25:27.881497 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8545 00:25:27.884886 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8546 00:25:27.888801 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8547 00:25:27.891106 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8548 00:25:27.891539 ==
8549 00:25:27.894547 Dram Type= 6, Freq= 0, CH_1, rank 1
8550 00:25:27.901347 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8551 00:25:27.901778 ==
8552 00:25:27.902112 DQS Delay:
8553 00:25:27.904502 DQS0 = 0, DQS1 = 0
8554 00:25:27.904926 DQM Delay:
8555 00:25:27.907810 DQM0 = 131, DQM1 = 124
8556 00:25:27.908239 DQ Delay:
8557 00:25:27.911247 DQ0 =135, DQ1 =123, DQ2 =115, DQ3 =131
8558 00:25:27.914732 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131
8559 00:25:27.917775 DQ8 =107, DQ9 =115, DQ10 =123, DQ11 =115
8560 00:25:27.921135 DQ12 =135, DQ13 =135, DQ14 =131, DQ15 =135
8561 00:25:27.921645
8562 00:25:27.921974
8563 00:25:27.922329 ==
8564 00:25:27.924664 Dram Type= 6, Freq= 0, CH_1, rank 1
8565 00:25:27.930832 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8566 00:25:27.931263 ==
8567 00:25:27.931596
8568 00:25:27.931899
8569 00:25:27.932267 TX Vref Scan disable
8570 00:25:27.934318 == TX Byte 0 ==
8571 00:25:27.937702 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8572 00:25:27.944399 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8573 00:25:27.944871 == TX Byte 1 ==
8574 00:25:27.947344 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8575 00:25:27.954134 Update DQM dly =973 (3 ,6, 13) DQM OEN =(3 ,3)
8576 00:25:27.954634 ==
8577 00:25:27.957298 Dram Type= 6, Freq= 0, CH_1, rank 1
8578 00:25:27.960637 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8579 00:25:27.961069 ==
8580 00:25:27.973992
8581 00:25:27.977263 TX Vref early break, caculate TX vref
8582 00:25:27.980924 TX Vref=16, minBit 0, minWin=22, winSum=381
8583 00:25:27.984255 TX Vref=18, minBit 1, minWin=23, winSum=390
8584 00:25:27.988267 TX Vref=20, minBit 2, minWin=23, winSum=399
8585 00:25:27.990979 TX Vref=22, minBit 3, minWin=23, winSum=402
8586 00:25:27.994028 TX Vref=24, minBit 3, minWin=24, winSum=413
8587 00:25:28.000842 TX Vref=26, minBit 2, minWin=25, winSum=422
8588 00:25:28.004777 TX Vref=28, minBit 0, minWin=25, winSum=426
8589 00:25:28.007161 TX Vref=30, minBit 0, minWin=25, winSum=417
8590 00:25:28.011076 TX Vref=32, minBit 1, minWin=25, winSum=416
8591 00:25:28.014034 TX Vref=34, minBit 0, minWin=23, winSum=404
8592 00:25:28.017184 TX Vref=36, minBit 0, minWin=24, winSum=398
8593 00:25:28.023815 [TxChooseVref] Worse bit 0, Min win 25, Win sum 426, Final Vref 28
8594 00:25:28.024252
8595 00:25:28.027076 Final TX Range 0 Vref 28
8596 00:25:28.027510
8597 00:25:28.027847 ==
8598 00:25:28.030738 Dram Type= 6, Freq= 0, CH_1, rank 1
8599 00:25:28.033831 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8600 00:25:28.034287 ==
8601 00:25:28.034626
8602 00:25:28.034935
8603 00:25:28.037108 TX Vref Scan disable
8604 00:25:28.043566 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8605 00:25:28.044070 == TX Byte 0 ==
8606 00:25:28.046959 u2DelayCellOfst[0]=18 cells (5 PI)
8607 00:25:28.050591 u2DelayCellOfst[1]=10 cells (3 PI)
8608 00:25:28.053796 u2DelayCellOfst[2]=0 cells (0 PI)
8609 00:25:28.056947 u2DelayCellOfst[3]=7 cells (2 PI)
8610 00:25:28.059911 u2DelayCellOfst[4]=7 cells (2 PI)
8611 00:25:28.063434 u2DelayCellOfst[5]=14 cells (4 PI)
8612 00:25:28.066150 u2DelayCellOfst[6]=14 cells (4 PI)
8613 00:25:28.069484 u2DelayCellOfst[7]=7 cells (2 PI)
8614 00:25:28.072962 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8615 00:25:28.076272 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8616 00:25:28.079755 == TX Byte 1 ==
8617 00:25:28.083039 u2DelayCellOfst[8]=0 cells (0 PI)
8618 00:25:28.086826 u2DelayCellOfst[9]=3 cells (1 PI)
8619 00:25:28.086913 u2DelayCellOfst[10]=7 cells (2 PI)
8620 00:25:28.089921 u2DelayCellOfst[11]=3 cells (1 PI)
8621 00:25:28.093400 u2DelayCellOfst[12]=10 cells (3 PI)
8622 00:25:28.096212 u2DelayCellOfst[13]=18 cells (5 PI)
8623 00:25:28.099721 u2DelayCellOfst[14]=18 cells (5 PI)
8624 00:25:28.103105 u2DelayCellOfst[15]=14 cells (4 PI)
8625 00:25:28.110131 Update DQ dly =971 (3 ,6, 11) DQ OEN =(3 ,3)
8626 00:25:28.113091 Update DQM dly =973 (3 ,6, 13) DQM OEN =(3 ,3)
8627 00:25:28.113319 DramC Write-DBI on
8628 00:25:28.113451 ==
8629 00:25:28.116444 Dram Type= 6, Freq= 0, CH_1, rank 1
8630 00:25:28.122906 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8631 00:25:28.123203 ==
8632 00:25:28.123398
8633 00:25:28.123560
8634 00:25:28.123715 TX Vref Scan disable
8635 00:25:28.126594 == TX Byte 0 ==
8636 00:25:28.130077 Update DQM dly =717 (2 ,6, 13) DQM OEN =(3 ,3)
8637 00:25:28.133356 == TX Byte 1 ==
8638 00:25:28.137183 Update DQM dly =714 (2 ,6, 10) DQM OEN =(3 ,3)
8639 00:25:28.139842 DramC Write-DBI off
8640 00:25:28.139944
8641 00:25:28.140032 [DATLAT]
8642 00:25:28.140114 Freq=1600, CH1 RK1
8643 00:25:28.140193
8644 00:25:28.143442 DATLAT Default: 0xe
8645 00:25:28.143516 0, 0xFFFF, sum = 0
8646 00:25:28.146603 1, 0xFFFF, sum = 0
8647 00:25:28.150128 2, 0xFFFF, sum = 0
8648 00:25:28.150299 3, 0xFFFF, sum = 0
8649 00:25:28.153008 4, 0xFFFF, sum = 0
8650 00:25:28.153169 5, 0xFFFF, sum = 0
8651 00:25:28.156597 6, 0xFFFF, sum = 0
8652 00:25:28.156692 7, 0xFFFF, sum = 0
8653 00:25:28.159855 8, 0xFFFF, sum = 0
8654 00:25:28.159951 9, 0xFFFF, sum = 0
8655 00:25:28.163056 10, 0xFFFF, sum = 0
8656 00:25:28.163161 11, 0xFFFF, sum = 0
8657 00:25:28.166559 12, 0xF5F, sum = 0
8658 00:25:28.166688 13, 0x0, sum = 1
8659 00:25:28.169632 14, 0x0, sum = 2
8660 00:25:28.169746 15, 0x0, sum = 3
8661 00:25:28.173463 16, 0x0, sum = 4
8662 00:25:28.173589 best_step = 14
8663 00:25:28.173726
8664 00:25:28.173820 ==
8665 00:25:28.176225 Dram Type= 6, Freq= 0, CH_1, rank 1
8666 00:25:28.179819 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8667 00:25:28.182983 ==
8668 00:25:28.183141 RX Vref Scan: 0
8669 00:25:28.183262
8670 00:25:28.186680 RX Vref 0 -> 0, step: 1
8671 00:25:28.186838
8672 00:25:28.186961 RX Delay 3 -> 252, step: 4
8673 00:25:28.193643 iDelay=195, Bit 0, Center 128 (75 ~ 182) 108
8674 00:25:28.196976 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
8675 00:25:28.200481 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8676 00:25:28.204427 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8677 00:25:28.207433 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8678 00:25:28.214047 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8679 00:25:28.217872 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8680 00:25:28.220713 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8681 00:25:28.223835 iDelay=195, Bit 8, Center 104 (47 ~ 162) 116
8682 00:25:28.227369 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8683 00:25:28.233493 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116
8684 00:25:28.236942 iDelay=195, Bit 11, Center 112 (55 ~ 170) 116
8685 00:25:28.240074 iDelay=195, Bit 12, Center 130 (71 ~ 190) 120
8686 00:25:28.243773 iDelay=195, Bit 13, Center 130 (79 ~ 182) 104
8687 00:25:28.250046 iDelay=195, Bit 14, Center 132 (75 ~ 190) 116
8688 00:25:28.253690 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8689 00:25:28.254076 ==
8690 00:25:28.257150 Dram Type= 6, Freq= 0, CH_1, rank 1
8691 00:25:28.260149 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8692 00:25:28.260539 ==
8693 00:25:28.263480 DQS Delay:
8694 00:25:28.263866 DQS0 = 0, DQS1 = 0
8695 00:25:28.264169 DQM Delay:
8696 00:25:28.267415 DQM0 = 127, DQM1 = 121
8697 00:25:28.267882 DQ Delay:
8698 00:25:28.270528 DQ0 =128, DQ1 =124, DQ2 =116, DQ3 =124
8699 00:25:28.273558 DQ4 =126, DQ5 =138, DQ6 =136, DQ7 =126
8700 00:25:28.276803 DQ8 =104, DQ9 =110, DQ10 =124, DQ11 =112
8701 00:25:28.283271 DQ12 =130, DQ13 =130, DQ14 =132, DQ15 =132
8702 00:25:28.283655
8703 00:25:28.283953
8704 00:25:28.284225
8705 00:25:28.286719 [DramC_TX_OE_Calibration] TA2
8706 00:25:28.289982 Original DQ_B0 (3 6) =30, OEN = 27
8707 00:25:28.290398 Original DQ_B1 (3 6) =30, OEN = 27
8708 00:25:28.293117 24, 0x0, End_B0=24 End_B1=24
8709 00:25:28.296658 25, 0x0, End_B0=25 End_B1=25
8710 00:25:28.299992 26, 0x0, End_B0=26 End_B1=26
8711 00:25:28.303120 27, 0x0, End_B0=27 End_B1=27
8712 00:25:28.303528 28, 0x0, End_B0=28 End_B1=28
8713 00:25:28.306668 29, 0x0, End_B0=29 End_B1=29
8714 00:25:28.309642 30, 0x0, End_B0=30 End_B1=30
8715 00:25:28.312989 31, 0x4141, End_B0=30 End_B1=30
8716 00:25:28.316222 Byte0 end_step=30 best_step=27
8717 00:25:28.316641 Byte1 end_step=30 best_step=27
8718 00:25:28.319791 Byte0 TX OE(2T, 0.5T) = (3, 3)
8719 00:25:28.322980 Byte1 TX OE(2T, 0.5T) = (3, 3)
8720 00:25:28.323369
8721 00:25:28.323666
8722 00:25:28.333023 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c1c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
8723 00:25:28.333495 CH1 RK1: MR19=303, MR18=1C1C
8724 00:25:28.339923 CH1_RK1: MR19=0x303, MR18=0x1C1C, DQSOSC=395, MR23=63, INC=23, DEC=15
8725 00:25:28.342810 [RxdqsGatingPostProcess] freq 1600
8726 00:25:28.349544 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8727 00:25:28.352667 Pre-setting of DQS Precalculation
8728 00:25:28.356687 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8729 00:25:28.366134 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8730 00:25:28.372864 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8731 00:25:28.373372
8732 00:25:28.373803
8733 00:25:28.376610 [Calibration Summary] 3200 Mbps
8734 00:25:28.377053 CH 0, Rank 0
8735 00:25:28.379459 SW Impedance : PASS
8736 00:25:28.379935 DUTY Scan : NO K
8737 00:25:28.383003 ZQ Calibration : PASS
8738 00:25:28.386170 Jitter Meter : NO K
8739 00:25:28.386647 CBT Training : PASS
8740 00:25:28.389604 Write leveling : PASS
8741 00:25:28.392533 RX DQS gating : PASS
8742 00:25:28.392974 RX DQ/DQS(RDDQC) : PASS
8743 00:25:28.396000 TX DQ/DQS : PASS
8744 00:25:28.399198 RX DATLAT : PASS
8745 00:25:28.399760 RX DQ/DQS(Engine): PASS
8746 00:25:28.402531 TX OE : PASS
8747 00:25:28.402961 All Pass.
8748 00:25:28.403290
8749 00:25:28.403591 CH 0, Rank 1
8750 00:25:28.406045 SW Impedance : PASS
8751 00:25:28.409417 DUTY Scan : NO K
8752 00:25:28.409844 ZQ Calibration : PASS
8753 00:25:28.412936 Jitter Meter : NO K
8754 00:25:28.415922 CBT Training : PASS
8755 00:25:28.416350 Write leveling : PASS
8756 00:25:28.419403 RX DQS gating : PASS
8757 00:25:28.423537 RX DQ/DQS(RDDQC) : PASS
8758 00:25:28.424045 TX DQ/DQS : PASS
8759 00:25:28.425958 RX DATLAT : PASS
8760 00:25:28.429372 RX DQ/DQS(Engine): PASS
8761 00:25:28.429877 TX OE : PASS
8762 00:25:28.432472 All Pass.
8763 00:25:28.432893
8764 00:25:28.433250 CH 1, Rank 0
8765 00:25:28.435813 SW Impedance : PASS
8766 00:25:28.436334 DUTY Scan : NO K
8767 00:25:28.439105 ZQ Calibration : PASS
8768 00:25:28.442288 Jitter Meter : NO K
8769 00:25:28.442743 CBT Training : PASS
8770 00:25:28.445614 Write leveling : PASS
8771 00:25:28.448876 RX DQS gating : PASS
8772 00:25:28.449342 RX DQ/DQS(RDDQC) : PASS
8773 00:25:28.452290 TX DQ/DQS : PASS
8774 00:25:28.455813 RX DATLAT : PASS
8775 00:25:28.456303 RX DQ/DQS(Engine): PASS
8776 00:25:28.459086 TX OE : PASS
8777 00:25:28.459526 All Pass.
8778 00:25:28.459956
8779 00:25:28.462496 CH 1, Rank 1
8780 00:25:28.462978 SW Impedance : PASS
8781 00:25:28.465526 DUTY Scan : NO K
8782 00:25:28.465959 ZQ Calibration : PASS
8783 00:25:28.468886 Jitter Meter : NO K
8784 00:25:28.472455 CBT Training : PASS
8785 00:25:28.473100 Write leveling : PASS
8786 00:25:28.475621 RX DQS gating : PASS
8787 00:25:28.479143 RX DQ/DQS(RDDQC) : PASS
8788 00:25:28.479570 TX DQ/DQS : PASS
8789 00:25:28.481933 RX DATLAT : PASS
8790 00:25:28.485424 RX DQ/DQS(Engine): PASS
8791 00:25:28.486065 TX OE : PASS
8792 00:25:28.489241 All Pass.
8793 00:25:28.489732
8794 00:25:28.490243 DramC Write-DBI on
8795 00:25:28.491964 PER_BANK_REFRESH: Hybrid Mode
8796 00:25:28.492349 TX_TRACKING: ON
8797 00:25:28.502116 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8798 00:25:28.511733 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8799 00:25:28.518974 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8800 00:25:28.522069 [FAST_K] Save calibration result to emmc
8801 00:25:28.525346 sync common calibartion params.
8802 00:25:28.525810 sync cbt_mode0:0, 1:0
8803 00:25:28.528934 dram_init: ddr_geometry: 0
8804 00:25:28.531581 dram_init: ddr_geometry: 0
8805 00:25:28.531968 dram_init: ddr_geometry: 0
8806 00:25:28.535329 0:dram_rank_size:80000000
8807 00:25:28.538480 1:dram_rank_size:80000000
8808 00:25:28.545047 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8809 00:25:28.545513 DFS_SHUFFLE_HW_MODE: ON
8810 00:25:28.548612 dramc_set_vcore_voltage set vcore to 725000
8811 00:25:28.551729 Read voltage for 1600, 0
8812 00:25:28.552114 Vio18 = 0
8813 00:25:28.554824 Vcore = 725000
8814 00:25:28.555208 Vdram = 0
8815 00:25:28.555506 Vddq = 0
8816 00:25:28.558726 Vmddr = 0
8817 00:25:28.559193 switch to 3200 Mbps bootup
8818 00:25:28.561759 [DramcRunTimeConfig]
8819 00:25:28.562153 PHYPLL
8820 00:25:28.564707 DPM_CONTROL_AFTERK: ON
8821 00:25:28.565213 PER_BANK_REFRESH: ON
8822 00:25:28.568476 REFRESH_OVERHEAD_REDUCTION: ON
8823 00:25:28.572096 CMD_PICG_NEW_MODE: OFF
8824 00:25:28.572485 XRTWTW_NEW_MODE: ON
8825 00:25:28.574919 XRTRTR_NEW_MODE: ON
8826 00:25:28.575336 TX_TRACKING: ON
8827 00:25:28.578387 RDSEL_TRACKING: OFF
8828 00:25:28.581529 DQS Precalculation for DVFS: ON
8829 00:25:28.582062 RX_TRACKING: OFF
8830 00:25:28.584592 HW_GATING DBG: ON
8831 00:25:28.585021 ZQCS_ENABLE_LP4: ON
8832 00:25:28.587917 RX_PICG_NEW_MODE: ON
8833 00:25:28.588529 TX_PICG_NEW_MODE: ON
8834 00:25:28.591261 ENABLE_RX_DCM_DPHY: ON
8835 00:25:28.594681 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8836 00:25:28.597995 DUMMY_READ_FOR_TRACKING: OFF
8837 00:25:28.598539 !!! SPM_CONTROL_AFTERK: OFF
8838 00:25:28.601194 !!! SPM could not control APHY
8839 00:25:28.604708 IMPEDANCE_TRACKING: ON
8840 00:25:28.605327 TEMP_SENSOR: ON
8841 00:25:28.607709 HW_SAVE_FOR_SR: OFF
8842 00:25:28.611316 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8843 00:25:28.614687 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8844 00:25:28.615123 Read ODT Tracking: ON
8845 00:25:28.617817 Refresh Rate DeBounce: ON
8846 00:25:28.621178 DFS_NO_QUEUE_FLUSH: ON
8847 00:25:28.624315 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8848 00:25:28.627690 ENABLE_DFS_RUNTIME_MRW: OFF
8849 00:25:28.628159 DDR_RESERVE_NEW_MODE: ON
8850 00:25:28.631075 MR_CBT_SWITCH_FREQ: ON
8851 00:25:28.634087 =========================
8852 00:25:28.651461 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8853 00:25:28.654737 dram_init: ddr_geometry: 0
8854 00:25:28.672977 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8855 00:25:28.676406 dram_init: dram init end (result: 0)
8856 00:25:28.682953 DRAM-K: Full calibration passed in 23405 msecs
8857 00:25:28.686036 MRC: failed to locate region type 0.
8858 00:25:28.686567 DRAM rank0 size:0x80000000,
8859 00:25:28.689368 DRAM rank1 size=0x80000000
8860 00:25:28.699122 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8861 00:25:28.705758 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8862 00:25:28.712366 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8863 00:25:28.719149 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8864 00:25:28.722389 DRAM rank0 size:0x80000000,
8865 00:25:28.725497 DRAM rank1 size=0x80000000
8866 00:25:28.726168 CBMEM:
8867 00:25:28.728904 IMD: root @ 0xfffff000 254 entries.
8868 00:25:28.732507 IMD: root @ 0xffffec00 62 entries.
8869 00:25:28.735582 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8870 00:25:28.738806 WARNING: RO_VPD is uninitialized or empty.
8871 00:25:28.745496 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8872 00:25:28.752994 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8873 00:25:28.765425 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
8874 00:25:28.777299 BS: romstage times (exec / console): total (unknown) / 22942 ms
8875 00:25:28.777811
8876 00:25:28.778143
8877 00:25:28.786753 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8878 00:25:28.789778 ARM64: Exception handlers installed.
8879 00:25:28.793144 ARM64: Testing exception
8880 00:25:28.796831 ARM64: Done test exception
8881 00:25:28.797264 Enumerating buses...
8882 00:25:28.800654 Show all devs... Before device enumeration.
8883 00:25:28.803589 Root Device: enabled 1
8884 00:25:28.806812 CPU_CLUSTER: 0: enabled 1
8885 00:25:28.807243 CPU: 00: enabled 1
8886 00:25:28.809903 Compare with tree...
8887 00:25:28.810389 Root Device: enabled 1
8888 00:25:28.813602 CPU_CLUSTER: 0: enabled 1
8889 00:25:28.816800 CPU: 00: enabled 1
8890 00:25:28.817231 Root Device scanning...
8891 00:25:28.819813 scan_static_bus for Root Device
8892 00:25:28.822709 CPU_CLUSTER: 0 enabled
8893 00:25:28.825989 scan_static_bus for Root Device done
8894 00:25:28.829703 scan_bus: bus Root Device finished in 8 msecs
8895 00:25:28.829779 done
8896 00:25:28.836230 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8897 00:25:28.839985 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8898 00:25:28.846727 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8899 00:25:28.849597 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8900 00:25:28.853114 Allocating resources...
8901 00:25:28.853503 Reading resources...
8902 00:25:28.859931 Root Device read_resources bus 0 link: 0
8903 00:25:28.860437 DRAM rank0 size:0x80000000,
8904 00:25:28.863163 DRAM rank1 size=0x80000000
8905 00:25:28.866492 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8906 00:25:28.869530 CPU: 00 missing read_resources
8907 00:25:28.873302 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8908 00:25:28.879577 Root Device read_resources bus 0 link: 0 done
8909 00:25:28.880011 Done reading resources.
8910 00:25:28.886346 Show resources in subtree (Root Device)...After reading.
8911 00:25:28.889175 Root Device child on link 0 CPU_CLUSTER: 0
8912 00:25:28.893020 CPU_CLUSTER: 0 child on link 0 CPU: 00
8913 00:25:28.902601 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8914 00:25:28.902679 CPU: 00
8915 00:25:28.905795 Root Device assign_resources, bus 0 link: 0
8916 00:25:28.908704 CPU_CLUSTER: 0 missing set_resources
8917 00:25:28.916146 Root Device assign_resources, bus 0 link: 0 done
8918 00:25:28.916222 Done setting resources.
8919 00:25:28.921798 Show resources in subtree (Root Device)...After assigning values.
8920 00:25:28.925111 Root Device child on link 0 CPU_CLUSTER: 0
8921 00:25:28.928347 CPU_CLUSTER: 0 child on link 0 CPU: 00
8922 00:25:28.938480 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8923 00:25:28.938559 CPU: 00
8924 00:25:28.942172 Done allocating resources.
8925 00:25:28.945073 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
8926 00:25:28.948710 Enabling resources...
8927 00:25:28.948783 done.
8928 00:25:28.955213 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
8929 00:25:28.955302 Initializing devices...
8930 00:25:28.958698 Root Device init
8931 00:25:28.958794 init hardware done!
8932 00:25:28.961753 0x00000018: ctrlr->caps
8933 00:25:28.965430 52.000 MHz: ctrlr->f_max
8934 00:25:28.965575 0.400 MHz: ctrlr->f_min
8935 00:25:28.968642 0x40ff8080: ctrlr->voltages
8936 00:25:28.968830 sclk: 390625
8937 00:25:28.971727 Bus Width = 1
8938 00:25:28.971882 sclk: 390625
8939 00:25:28.975088 Bus Width = 1
8940 00:25:28.975265 Early init status = 3
8941 00:25:28.981759 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
8942 00:25:28.985121 in-header: 03 fc 00 00 01 00 00 00
8943 00:25:28.985357 in-data: 00
8944 00:25:28.991643 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
8945 00:25:28.995149 in-header: 03 fd 00 00 00 00 00 00
8946 00:25:28.998258 in-data:
8947 00:25:29.001961 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
8948 00:25:29.005630 in-header: 03 fc 00 00 01 00 00 00
8949 00:25:29.008683 in-data: 00
8950 00:25:29.011730 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
8951 00:25:29.016815 in-header: 03 fd 00 00 00 00 00 00
8952 00:25:29.020290 in-data:
8953 00:25:29.023441 [SSUSB] Setting up USB HOST controller...
8954 00:25:29.026823 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
8955 00:25:29.029843 [SSUSB] phy power-on done.
8956 00:25:29.033025 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
8957 00:25:29.040199 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
8958 00:25:29.043652 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
8959 00:25:29.049595 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
8960 00:25:29.056354 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
8961 00:25:29.063018 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
8962 00:25:29.069849 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
8963 00:25:29.076987 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
8964 00:25:29.079804 SPM: binary array size = 0x9dc
8965 00:25:29.082974 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
8966 00:25:29.089300 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
8967 00:25:29.096174 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
8968 00:25:29.099357 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
8969 00:25:29.105670 configure_display: Starting display init
8970 00:25:29.139657 anx7625_power_on_init: Init interface.
8971 00:25:29.143410 anx7625_disable_pd_protocol: Disabled PD feature.
8972 00:25:29.146366 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
8973 00:25:29.174305 anx7625_start_dp_work: Secure OCM version=00
8974 00:25:29.177394 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
8975 00:25:29.192276 sp_tx_get_edid_block: EDID Block = 1
8976 00:25:29.295052 Extracted contents:
8977 00:25:29.298247 header: 00 ff ff ff ff ff ff 00
8978 00:25:29.301499 serial number: 26 cf 7d 05 00 00 00 00 00 1e
8979 00:25:29.304862 version: 01 04
8980 00:25:29.308197 basic params: 95 1f 11 78 0a
8981 00:25:29.311521 chroma info: 76 90 94 55 54 90 27 21 50 54
8982 00:25:29.314748 established: 00 00 00
8983 00:25:29.321343 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
8984 00:25:29.324418 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
8985 00:25:29.331250 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
8986 00:25:29.337757 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
8987 00:25:29.344611 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
8988 00:25:29.348248 extensions: 00
8989 00:25:29.348760 checksum: fb
8990 00:25:29.349114
8991 00:25:29.351053 Manufacturer: IVO Model 57d Serial Number 0
8992 00:25:29.354468 Made week 0 of 2020
8993 00:25:29.354900 EDID version: 1.4
8994 00:25:29.357811 Digital display
8995 00:25:29.361054 6 bits per primary color channel
8996 00:25:29.361505 DisplayPort interface
8997 00:25:29.364294 Maximum image size: 31 cm x 17 cm
8998 00:25:29.367809 Gamma: 220%
8999 00:25:29.368345 Check DPMS levels
9000 00:25:29.371035 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9001 00:25:29.377545 First detailed timing is preferred timing
9002 00:25:29.377978 Established timings supported:
9003 00:25:29.381170 Standard timings supported:
9004 00:25:29.384185 Detailed timings
9005 00:25:29.387499 Hex of detail: 383680a07038204018303c0035ae10000019
9006 00:25:29.390945 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9007 00:25:29.397365 0780 0798 07c8 0820 hborder 0
9008 00:25:29.400724 0438 043b 0447 0458 vborder 0
9009 00:25:29.403979 -hsync -vsync
9010 00:25:29.404373 Did detailed timing
9011 00:25:29.410803 Hex of detail: 000000000000000000000000000000000000
9012 00:25:29.414037 Manufacturer-specified data, tag 0
9013 00:25:29.417554 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9014 00:25:29.420725 ASCII string: InfoVision
9015 00:25:29.424099 Hex of detail: 000000fe00523134304e574635205248200a
9016 00:25:29.427294 ASCII string: R140NWF5 RH
9017 00:25:29.427960 Checksum
9018 00:25:29.430854 Checksum: 0xfb (valid)
9019 00:25:29.433992 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9020 00:25:29.437229 DSI data_rate: 832800000 bps
9021 00:25:29.444145 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9022 00:25:29.447275 anx7625_parse_edid: pixelclock(138800).
9023 00:25:29.450862 hactive(1920), hsync(48), hfp(24), hbp(88)
9024 00:25:29.454163 vactive(1080), vsync(12), vfp(3), vbp(17)
9025 00:25:29.457296 anx7625_dsi_config: config dsi.
9026 00:25:29.464120 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9027 00:25:29.477230 anx7625_dsi_config: success to config DSI
9028 00:25:29.480427 anx7625_dp_start: MIPI phy setup OK.
9029 00:25:29.484008 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9030 00:25:29.486796 mtk_ddp_mode_set invalid vrefresh 60
9031 00:25:29.490350 main_disp_path_setup
9032 00:25:29.490782 ovl_layer_smi_id_en
9033 00:25:29.493516 ovl_layer_smi_id_en
9034 00:25:29.493950 ccorr_config
9035 00:25:29.494331 aal_config
9036 00:25:29.497028 gamma_config
9037 00:25:29.497456 postmask_config
9038 00:25:29.500512 dither_config
9039 00:25:29.503625 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9040 00:25:29.510088 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9041 00:25:29.513669 Root Device init finished in 551 msecs
9042 00:25:29.514103 CPU_CLUSTER: 0 init
9043 00:25:29.523701 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9044 00:25:29.526953 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9045 00:25:29.529995 APU_MBOX 0x190000b0 = 0x10001
9046 00:25:29.533521 APU_MBOX 0x190001b0 = 0x10001
9047 00:25:29.536895 APU_MBOX 0x190005b0 = 0x10001
9048 00:25:29.540165 APU_MBOX 0x190006b0 = 0x10001
9049 00:25:29.543504 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9050 00:25:29.555759 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9051 00:25:29.568518 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9052 00:25:29.574364 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9053 00:25:29.585952 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9054 00:25:29.595382 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9055 00:25:29.598881 CPU_CLUSTER: 0 init finished in 81 msecs
9056 00:25:29.602372 Devices initialized
9057 00:25:29.605473 Show all devs... After init.
9058 00:25:29.605624 Root Device: enabled 1
9059 00:25:29.609105 CPU_CLUSTER: 0: enabled 1
9060 00:25:29.612119 CPU: 00: enabled 1
9061 00:25:29.615395 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9062 00:25:29.618538 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9063 00:25:29.621880 ELOG: NV offset 0x57f000 size 0x1000
9064 00:25:29.628553 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9065 00:25:29.635362 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9066 00:25:29.638554 ELOG: Event(17) added with size 13 at 2024-06-21 00:25:29 UTC
9067 00:25:29.642136 out: cmd=0x121: 03 db 21 01 00 00 00 00
9068 00:25:29.645879 in-header: 03 29 00 00 2c 00 00 00
9069 00:25:29.659011 in-data: 19 6d 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9070 00:25:29.665636 ELOG: Event(A1) added with size 10 at 2024-06-21 00:25:29 UTC
9071 00:25:29.672548 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9072 00:25:29.678835 ELOG: Event(A0) added with size 9 at 2024-06-21 00:25:29 UTC
9073 00:25:29.682257 elog_add_boot_reason: Logged dev mode boot
9074 00:25:29.686002 BS: BS_POST_DEVICE entry times (exec / console): 1 / 64 ms
9075 00:25:29.688847 Finalize devices...
9076 00:25:29.689276 Devices finalized
9077 00:25:29.695537 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9078 00:25:29.698908 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9079 00:25:29.702109 in-header: 03 07 00 00 08 00 00 00
9080 00:25:29.705362 in-data: aa e4 47 04 13 02 00 00
9081 00:25:29.708820 Chrome EC: UHEPI supported
9082 00:25:29.715780 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9083 00:25:29.719021 in-header: 03 a9 00 00 08 00 00 00
9084 00:25:29.721869 in-data: 84 60 60 08 00 00 00 00
9085 00:25:29.725065 ELOG: Event(91) added with size 10 at 2024-06-21 00:25:29 UTC
9086 00:25:29.731836 Chrome EC: clear events_b mask to 0x0000000020004000
9087 00:25:29.738543 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9088 00:25:29.741969 in-header: 03 fd 00 00 00 00 00 00
9089 00:25:29.742508 in-data:
9090 00:25:29.748813 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9091 00:25:29.752174 Writing coreboot table at 0xffe64000
9092 00:25:29.756190 0. 000000000010a000-0000000000113fff: RAMSTAGE
9093 00:25:29.758871 1. 0000000040000000-00000000400fffff: RAM
9094 00:25:29.765256 2. 0000000040100000-000000004032afff: RAMSTAGE
9095 00:25:29.768685 3. 000000004032b000-00000000545fffff: RAM
9096 00:25:29.772264 4. 0000000054600000-000000005465ffff: BL31
9097 00:25:29.775097 5. 0000000054660000-00000000ffe63fff: RAM
9098 00:25:29.781868 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9099 00:25:29.784736 7. 0000000100000000-000000013fffffff: RAM
9100 00:25:29.785307 Passing 5 GPIOs to payload:
9101 00:25:29.791799 NAME | PORT | POLARITY | VALUE
9102 00:25:29.795430 EC in RW | 0x000000aa | low | undefined
9103 00:25:29.801509 EC interrupt | 0x00000005 | low | undefined
9104 00:25:29.804674 TPM interrupt | 0x000000ab | high | undefined
9105 00:25:29.811474 SD card detect | 0x00000011 | high | undefined
9106 00:25:29.815547 speaker enable | 0x00000093 | high | undefined
9107 00:25:29.818306 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9108 00:25:29.821756 in-header: 03 f8 00 00 02 00 00 00
9109 00:25:29.822148 in-data: 03 00
9110 00:25:29.824690 ADC[4]: Raw value=669695 ID=5
9111 00:25:29.828086 ADC[3]: Raw value=212917 ID=1
9112 00:25:29.831767 RAM Code: 0x51
9113 00:25:29.832156 ADC[6]: Raw value=74410 ID=0
9114 00:25:29.834532 ADC[5]: Raw value=211812 ID=1
9115 00:25:29.837988 SKU Code: 0x1
9116 00:25:29.841514 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 86cf
9117 00:25:29.844544 coreboot table: 964 bytes.
9118 00:25:29.847778 IMD ROOT 0. 0xfffff000 0x00001000
9119 00:25:29.851594 IMD SMALL 1. 0xffffe000 0x00001000
9120 00:25:29.854441 RO MCACHE 2. 0xffffc000 0x00001104
9121 00:25:29.858249 CONSOLE 3. 0xfff7c000 0x00080000
9122 00:25:29.861394 FMAP 4. 0xfff7b000 0x00000452
9123 00:25:29.864430 TIME STAMP 5. 0xfff7a000 0x00000910
9124 00:25:29.867850 VBOOT WORK 6. 0xfff66000 0x00014000
9125 00:25:29.871775 RAMOOPS 7. 0xffe66000 0x00100000
9126 00:25:29.874523 COREBOOT 8. 0xffe64000 0x00002000
9127 00:25:29.874954 IMD small region:
9128 00:25:29.877711 IMD ROOT 0. 0xffffec00 0x00000400
9129 00:25:29.881074 VPD 1. 0xffffeb80 0x0000006c
9130 00:25:29.884474 MMC STATUS 2. 0xffffeb60 0x00000004
9131 00:25:29.891188 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9132 00:25:29.897605 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9133 00:25:29.937487 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9134 00:25:29.940639 Checking segment from ROM address 0x40100000
9135 00:25:29.943879 Checking segment from ROM address 0x4010001c
9136 00:25:29.950727 Loading segment from ROM address 0x40100000
9137 00:25:29.950808 code (compression=0)
9138 00:25:29.960571 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9139 00:25:29.967297 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9140 00:25:29.967374 it's not compressed!
9141 00:25:29.974026 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9142 00:25:29.980544 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9143 00:25:29.998166 Loading segment from ROM address 0x4010001c
9144 00:25:29.998713 Entry Point 0x80000000
9145 00:25:30.001228 Loaded segments
9146 00:25:30.004612 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9147 00:25:30.011801 Jumping to boot code at 0x80000000(0xffe64000)
9148 00:25:30.018285 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9149 00:25:30.024584 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9150 00:25:30.032709 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9151 00:25:30.035979 Checking segment from ROM address 0x40100000
9152 00:25:30.039208 Checking segment from ROM address 0x4010001c
9153 00:25:30.045880 Loading segment from ROM address 0x40100000
9154 00:25:30.046346 code (compression=1)
9155 00:25:30.052462 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9156 00:25:30.062535 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9157 00:25:30.062998 using LZMA
9158 00:25:30.070936 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9159 00:25:30.077490 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9160 00:25:30.081032 Loading segment from ROM address 0x4010001c
9161 00:25:30.081601 Entry Point 0x54601000
9162 00:25:30.084256 Loaded segments
9163 00:25:30.087455 NOTICE: MT8192 bl31_setup
9164 00:25:30.094787 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9165 00:25:30.097954 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9166 00:25:30.100938 WARNING: region 0:
9167 00:25:30.104474 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9168 00:25:30.104941 WARNING: region 1:
9169 00:25:30.110949 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9170 00:25:30.114138 WARNING: region 2:
9171 00:25:30.117387 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9172 00:25:30.121036 WARNING: region 3:
9173 00:25:30.124382 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9174 00:25:30.127366 WARNING: region 4:
9175 00:25:30.133910 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9176 00:25:30.134410 WARNING: region 5:
9177 00:25:30.138026 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9178 00:25:30.140828 WARNING: region 6:
9179 00:25:30.144288 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9180 00:25:30.147341 WARNING: region 7:
9181 00:25:30.150588 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9182 00:25:30.157344 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9183 00:25:30.160576 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9184 00:25:30.164023 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9185 00:25:30.170431 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9186 00:25:30.174454 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9187 00:25:30.181041 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9188 00:25:30.184676 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9189 00:25:30.187383 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9190 00:25:30.194254 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9191 00:25:30.197415 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9192 00:25:30.200696 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9193 00:25:30.207453 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9194 00:25:30.210504 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9195 00:25:30.217158 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9196 00:25:30.220932 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9197 00:25:30.223612 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9198 00:25:30.230456 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9199 00:25:30.233666 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9200 00:25:30.237159 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9201 00:25:30.243840 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9202 00:25:30.247034 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9203 00:25:30.253752 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9204 00:25:30.257046 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9205 00:25:30.260354 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9206 00:25:30.266920 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9207 00:25:30.270128 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9208 00:25:30.276921 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9209 00:25:30.280257 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9210 00:25:30.283289 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9211 00:25:30.289863 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9212 00:25:30.293567 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9213 00:25:30.300324 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9214 00:25:30.303413 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9215 00:25:30.306806 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9216 00:25:30.310245 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9217 00:25:30.316695 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9218 00:25:30.320182 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9219 00:25:30.323629 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9220 00:25:30.326640 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9221 00:25:30.333217 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9222 00:25:30.337039 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9223 00:25:30.339827 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9224 00:25:30.343653 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9225 00:25:30.349977 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9226 00:25:30.353127 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9227 00:25:30.356619 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9228 00:25:30.360175 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9229 00:25:30.366779 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9230 00:25:30.369896 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9231 00:25:30.376773 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9232 00:25:30.379704 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9233 00:25:30.383081 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9234 00:25:30.390076 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9235 00:25:30.393430 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9236 00:25:30.399999 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9237 00:25:30.403898 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9238 00:25:30.406414 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9239 00:25:30.413269 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9240 00:25:30.416549 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9241 00:25:30.423332 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9242 00:25:30.426331 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9243 00:25:30.432987 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9244 00:25:30.436599 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9245 00:25:30.443088 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9246 00:25:30.446764 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9247 00:25:30.453580 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9248 00:25:30.456232 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9249 00:25:30.459904 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9250 00:25:30.466250 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9251 00:25:30.470016 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9252 00:25:30.476153 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9253 00:25:30.479482 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9254 00:25:30.482727 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9255 00:25:30.489275 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9256 00:25:30.493017 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9257 00:25:30.499922 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9258 00:25:30.503000 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9259 00:25:30.509734 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9260 00:25:30.512855 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9261 00:25:30.519851 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9262 00:25:30.523019 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9263 00:25:30.525915 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9264 00:25:30.532778 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9265 00:25:30.536101 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9266 00:25:30.542415 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9267 00:25:30.546055 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9268 00:25:30.552668 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9269 00:25:30.555795 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9270 00:25:30.559171 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9271 00:25:30.566017 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9272 00:25:30.569226 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9273 00:25:30.576153 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9274 00:25:30.579219 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9275 00:25:30.586380 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9276 00:25:30.589481 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9277 00:25:30.595752 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9278 00:25:30.599082 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9279 00:25:30.602549 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9280 00:25:30.605695 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9281 00:25:30.612445 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9282 00:25:30.615685 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9283 00:25:30.619059 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9284 00:25:30.625638 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9285 00:25:30.629255 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9286 00:25:30.635533 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9287 00:25:30.638839 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9288 00:25:30.642395 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9289 00:25:30.648920 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9290 00:25:30.652013 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9291 00:25:30.658716 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9292 00:25:30.662340 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9293 00:25:30.665470 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9294 00:25:30.672268 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9295 00:25:30.675279 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9296 00:25:30.681841 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9297 00:25:30.685726 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9298 00:25:30.688744 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9299 00:25:30.692322 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9300 00:25:30.698700 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9301 00:25:30.702164 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9302 00:25:30.705532 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9303 00:25:30.708790 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9304 00:25:30.715867 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9305 00:25:30.718645 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9306 00:25:30.722111 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9307 00:25:30.728496 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9308 00:25:30.731788 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9309 00:25:30.738149 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9310 00:25:30.741304 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9311 00:25:30.744863 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9312 00:25:30.751291 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9313 00:25:30.754817 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9314 00:25:30.761571 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9315 00:25:30.764487 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9316 00:25:30.768529 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9317 00:25:30.775187 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9318 00:25:30.778577 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9319 00:25:30.784997 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9320 00:25:30.788707 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9321 00:25:30.791557 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9322 00:25:30.798769 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9323 00:25:30.801677 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9324 00:25:30.804976 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9325 00:25:30.811720 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9326 00:25:30.815150 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9327 00:25:30.821585 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9328 00:25:30.824934 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9329 00:25:30.828312 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9330 00:25:30.834909 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9331 00:25:30.838047 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9332 00:25:30.844449 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9333 00:25:30.848053 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9334 00:25:30.851583 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9335 00:25:30.857981 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9336 00:25:30.861629 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9337 00:25:30.868181 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9338 00:25:30.871649 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9339 00:25:30.874474 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9340 00:25:30.881182 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9341 00:25:30.884547 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9342 00:25:30.888048 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9343 00:25:30.894297 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9344 00:25:30.898116 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9345 00:25:30.904649 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9346 00:25:30.907931 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9347 00:25:30.911082 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9348 00:25:30.918014 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9349 00:25:30.921316 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9350 00:25:30.928002 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9351 00:25:30.931013 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9352 00:25:30.934685 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9353 00:25:30.941109 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9354 00:25:30.944342 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9355 00:25:30.950866 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9356 00:25:30.954358 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9357 00:25:30.957531 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9358 00:25:30.964424 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9359 00:25:30.967672 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9360 00:25:30.974155 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9361 00:25:30.977523 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9362 00:25:30.980836 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9363 00:25:30.987699 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9364 00:25:30.991330 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9365 00:25:30.993995 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9366 00:25:31.000987 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9367 00:25:31.004144 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9368 00:25:31.011173 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9369 00:25:31.014424 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9370 00:25:31.017440 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9371 00:25:31.023920 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9372 00:25:31.027720 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9373 00:25:31.034056 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9374 00:25:31.037239 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9375 00:25:31.044219 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9376 00:25:31.047902 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9377 00:25:31.050786 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9378 00:25:31.057271 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9379 00:25:31.061201 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9380 00:25:31.067218 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9381 00:25:31.070912 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9382 00:25:31.074000 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9383 00:25:31.080978 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9384 00:25:31.083854 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9385 00:25:31.090716 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9386 00:25:31.093777 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9387 00:25:31.100538 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9388 00:25:31.103505 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9389 00:25:31.107076 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9390 00:25:31.113884 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9391 00:25:31.117117 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9392 00:25:31.123542 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9393 00:25:31.127062 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9394 00:25:31.130768 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9395 00:25:31.137007 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9396 00:25:31.140199 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9397 00:25:31.147302 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9398 00:25:31.150475 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9399 00:25:31.153900 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9400 00:25:31.160603 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9401 00:25:31.163818 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9402 00:25:31.170419 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9403 00:25:31.173951 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9404 00:25:31.180326 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9405 00:25:31.183444 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9406 00:25:31.186901 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9407 00:25:31.193767 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9408 00:25:31.197218 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9409 00:25:31.203772 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9410 00:25:31.207056 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9411 00:25:31.210289 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9412 00:25:31.213497 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9413 00:25:31.220874 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9414 00:25:31.223521 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9415 00:25:31.227052 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9416 00:25:31.233684 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9417 00:25:31.236952 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9418 00:25:31.240305 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9419 00:25:31.246823 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9420 00:25:31.250381 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9421 00:25:31.253696 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9422 00:25:31.260902 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9423 00:25:31.263514 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9424 00:25:31.267221 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9425 00:25:31.273713 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9426 00:25:31.276995 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9427 00:25:31.283282 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9428 00:25:31.286549 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9429 00:25:31.290046 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9430 00:25:31.297474 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9431 00:25:31.300025 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9432 00:25:31.303271 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9433 00:25:31.309985 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9434 00:25:31.313370 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9435 00:25:31.316623 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9436 00:25:31.323888 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9437 00:25:31.326736 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9438 00:25:31.333129 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9439 00:25:31.336535 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9440 00:25:31.339820 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9441 00:25:31.347241 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9442 00:25:31.350308 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9443 00:25:31.353299 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9444 00:25:31.360402 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9445 00:25:31.363082 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9446 00:25:31.367303 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9447 00:25:31.373138 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9448 00:25:31.376742 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9449 00:25:31.383456 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9450 00:25:31.386789 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9451 00:25:31.389960 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9452 00:25:31.393128 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9453 00:25:31.397072 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9454 00:25:31.402973 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9455 00:25:31.406312 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9456 00:25:31.409702 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9457 00:25:31.412946 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9458 00:25:31.419446 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9459 00:25:31.422809 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9460 00:25:31.426626 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9461 00:25:31.429647 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9462 00:25:31.436051 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9463 00:25:31.439324 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9464 00:25:31.442654 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9465 00:25:31.449878 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9466 00:25:31.452888 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9467 00:25:31.459975 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9468 00:25:31.463405 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9469 00:25:31.469535 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9470 00:25:31.473009 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9471 00:25:31.475995 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9472 00:25:31.482839 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9473 00:25:31.485961 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9474 00:25:31.492761 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9475 00:25:31.496011 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9476 00:25:31.499319 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9477 00:25:31.506408 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9478 00:25:31.509463 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9479 00:25:31.515973 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9480 00:25:31.519600 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9481 00:25:31.523239 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9482 00:25:31.529309 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9483 00:25:31.532882 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9484 00:25:31.539742 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9485 00:25:31.542552 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9486 00:25:31.549642 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9487 00:25:31.552406 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9488 00:25:31.556331 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9489 00:25:31.562361 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9490 00:25:31.565747 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9491 00:25:31.572689 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9492 00:25:31.576057 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9493 00:25:31.579038 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9494 00:25:31.585976 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9495 00:25:31.589124 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9496 00:25:31.592598 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9497 00:25:31.599097 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9498 00:25:31.602769 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9499 00:25:31.608905 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9500 00:25:31.612404 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9501 00:25:31.619031 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9502 00:25:31.622555 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9503 00:25:31.625692 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9504 00:25:31.632620 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9505 00:25:31.635534 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9506 00:25:31.642290 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9507 00:25:31.645714 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9508 00:25:31.648994 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9509 00:25:31.655630 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9510 00:25:31.659065 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9511 00:25:31.665486 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9512 00:25:31.668896 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9513 00:25:31.672132 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9514 00:25:31.678837 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9515 00:25:31.682617 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9516 00:25:31.689283 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9517 00:25:31.692574 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9518 00:25:31.695915 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9519 00:25:31.702365 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9520 00:25:31.705514 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9521 00:25:31.712182 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9522 00:25:31.715501 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9523 00:25:31.718710 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9524 00:25:31.725403 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9525 00:25:31.728550 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9526 00:25:31.735270 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9527 00:25:31.738521 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9528 00:25:31.741675 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9529 00:25:31.748635 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9530 00:25:31.752048 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9531 00:25:31.759011 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9532 00:25:31.762001 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9533 00:25:31.768795 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9534 00:25:31.772099 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9535 00:25:31.775037 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9536 00:25:31.782177 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9537 00:25:31.784963 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9538 00:25:31.791875 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9539 00:25:31.794991 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9540 00:25:31.801501 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9541 00:25:31.805011 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9542 00:25:31.811784 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9543 00:25:31.815015 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9544 00:25:31.818508 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9545 00:25:31.824698 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9546 00:25:31.828370 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9547 00:25:31.834852 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9548 00:25:31.838360 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9549 00:25:31.841928 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9550 00:25:31.848216 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9551 00:25:31.851439 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9552 00:25:31.858034 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9553 00:25:31.861185 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9554 00:25:31.867775 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9555 00:25:31.871146 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9556 00:25:31.877954 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9557 00:25:31.881485 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9558 00:25:31.884859 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9559 00:25:31.891523 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9560 00:25:31.894998 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9561 00:25:31.901361 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9562 00:25:31.904952 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9563 00:25:31.911685 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9564 00:25:31.914713 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9565 00:25:31.918020 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9566 00:25:31.924579 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9567 00:25:31.927892 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9568 00:25:31.934839 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9569 00:25:31.937811 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9570 00:25:31.944332 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9571 00:25:31.948058 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9572 00:25:31.951780 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9573 00:25:31.957826 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9574 00:25:31.961533 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9575 00:25:31.968146 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9576 00:25:31.971168 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9577 00:25:31.977772 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9578 00:25:31.981116 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9579 00:25:31.984513 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9580 00:25:31.991621 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9581 00:25:31.994255 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9582 00:25:32.000942 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9583 00:25:32.004431 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9584 00:25:32.007473 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9585 00:25:32.014083 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9586 00:25:32.017516 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9587 00:25:32.023928 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9588 00:25:32.027937 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9589 00:25:32.034470 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9590 00:25:32.037263 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9591 00:25:32.044549 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9592 00:25:32.047465 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9593 00:25:32.054050 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9594 00:25:32.057244 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9595 00:25:32.064294 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9596 00:25:32.067338 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9597 00:25:32.073808 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9598 00:25:32.077187 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9599 00:25:32.084007 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9600 00:25:32.087567 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9601 00:25:32.093866 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9602 00:25:32.097406 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9603 00:25:32.103839 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9604 00:25:32.107062 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9605 00:25:32.113677 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9606 00:25:32.116781 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9607 00:25:32.123709 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9608 00:25:32.126924 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9609 00:25:32.133634 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9610 00:25:32.136817 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9611 00:25:32.143297 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9612 00:25:32.146350 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9613 00:25:32.153683 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9614 00:25:32.156647 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9615 00:25:32.163228 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9616 00:25:32.166725 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9617 00:25:32.169907 INFO: [APUAPC] vio 0
9618 00:25:32.172925 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9619 00:25:32.179506 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9620 00:25:32.182929 INFO: [APUAPC] D0_APC_0: 0x400510
9621 00:25:32.183358 INFO: [APUAPC] D0_APC_1: 0x0
9622 00:25:32.186572 INFO: [APUAPC] D0_APC_2: 0x1540
9623 00:25:32.189473 INFO: [APUAPC] D0_APC_3: 0x0
9624 00:25:32.193308 INFO: [APUAPC] D1_APC_0: 0xffffffff
9625 00:25:32.196474 INFO: [APUAPC] D1_APC_1: 0xffffffff
9626 00:25:32.199768 INFO: [APUAPC] D1_APC_2: 0x3fffff
9627 00:25:32.202982 INFO: [APUAPC] D1_APC_3: 0x0
9628 00:25:32.206538 INFO: [APUAPC] D2_APC_0: 0xffffffff
9629 00:25:32.209495 INFO: [APUAPC] D2_APC_1: 0xffffffff
9630 00:25:32.213141 INFO: [APUAPC] D2_APC_2: 0x3fffff
9631 00:25:32.216500 INFO: [APUAPC] D2_APC_3: 0x0
9632 00:25:32.219701 INFO: [APUAPC] D3_APC_0: 0xffffffff
9633 00:25:32.222866 INFO: [APUAPC] D3_APC_1: 0xffffffff
9634 00:25:32.226124 INFO: [APUAPC] D3_APC_2: 0x3fffff
9635 00:25:32.229555 INFO: [APUAPC] D3_APC_3: 0x0
9636 00:25:32.232758 INFO: [APUAPC] D4_APC_0: 0xffffffff
9637 00:25:32.236095 INFO: [APUAPC] D4_APC_1: 0xffffffff
9638 00:25:32.239346 INFO: [APUAPC] D4_APC_2: 0x3fffff
9639 00:25:32.243006 INFO: [APUAPC] D4_APC_3: 0x0
9640 00:25:32.246205 INFO: [APUAPC] D5_APC_0: 0xffffffff
9641 00:25:32.249656 INFO: [APUAPC] D5_APC_1: 0xffffffff
9642 00:25:32.253115 INFO: [APUAPC] D5_APC_2: 0x3fffff
9643 00:25:32.256022 INFO: [APUAPC] D5_APC_3: 0x0
9644 00:25:32.259607 INFO: [APUAPC] D6_APC_0: 0xffffffff
9645 00:25:32.262818 INFO: [APUAPC] D6_APC_1: 0xffffffff
9646 00:25:32.265975 INFO: [APUAPC] D6_APC_2: 0x3fffff
9647 00:25:32.269440 INFO: [APUAPC] D6_APC_3: 0x0
9648 00:25:32.272691 INFO: [APUAPC] D7_APC_0: 0xffffffff
9649 00:25:32.276548 INFO: [APUAPC] D7_APC_1: 0xffffffff
9650 00:25:32.279299 INFO: [APUAPC] D7_APC_2: 0x3fffff
9651 00:25:32.282582 INFO: [APUAPC] D7_APC_3: 0x0
9652 00:25:32.286155 INFO: [APUAPC] D8_APC_0: 0xffffffff
9653 00:25:32.289734 INFO: [APUAPC] D8_APC_1: 0xffffffff
9654 00:25:32.293034 INFO: [APUAPC] D8_APC_2: 0x3fffff
9655 00:25:32.293468 INFO: [APUAPC] D8_APC_3: 0x0
9656 00:25:32.299429 INFO: [APUAPC] D9_APC_0: 0xffffffff
9657 00:25:32.302818 INFO: [APUAPC] D9_APC_1: 0xffffffff
9658 00:25:32.306187 INFO: [APUAPC] D9_APC_2: 0x3fffff
9659 00:25:32.306642 INFO: [APUAPC] D9_APC_3: 0x0
9660 00:25:32.310087 INFO: [APUAPC] D10_APC_0: 0xffffffff
9661 00:25:32.313031 INFO: [APUAPC] D10_APC_1: 0xffffffff
9662 00:25:32.319649 INFO: [APUAPC] D10_APC_2: 0x3fffff
9663 00:25:32.320078 INFO: [APUAPC] D10_APC_3: 0x0
9664 00:25:32.322974 INFO: [APUAPC] D11_APC_0: 0xffffffff
9665 00:25:32.329324 INFO: [APUAPC] D11_APC_1: 0xffffffff
9666 00:25:32.332705 INFO: [APUAPC] D11_APC_2: 0x3fffff
9667 00:25:32.333211 INFO: [APUAPC] D11_APC_3: 0x0
9668 00:25:32.335968 INFO: [APUAPC] D12_APC_0: 0xffffffff
9669 00:25:32.342600 INFO: [APUAPC] D12_APC_1: 0xffffffff
9670 00:25:32.346154 INFO: [APUAPC] D12_APC_2: 0x3fffff
9671 00:25:32.346631 INFO: [APUAPC] D12_APC_3: 0x0
9672 00:25:32.352669 INFO: [APUAPC] D13_APC_0: 0xffffffff
9673 00:25:32.355952 INFO: [APUAPC] D13_APC_1: 0xffffffff
9674 00:25:32.358938 INFO: [APUAPC] D13_APC_2: 0x3fffff
9675 00:25:32.359366 INFO: [APUAPC] D13_APC_3: 0x0
9676 00:25:32.365619 INFO: [APUAPC] D14_APC_0: 0xffffffff
9677 00:25:32.369195 INFO: [APUAPC] D14_APC_1: 0xffffffff
9678 00:25:32.372452 INFO: [APUAPC] D14_APC_2: 0x3fffff
9679 00:25:32.372840 INFO: [APUAPC] D14_APC_3: 0x0
9680 00:25:32.378905 INFO: [APUAPC] D15_APC_0: 0xffffffff
9681 00:25:32.382633 INFO: [APUAPC] D15_APC_1: 0xffffffff
9682 00:25:32.385740 INFO: [APUAPC] D15_APC_2: 0x3fffff
9683 00:25:32.388822 INFO: [APUAPC] D15_APC_3: 0x0
9684 00:25:32.389206 INFO: [APUAPC] APC_CON: 0x4
9685 00:25:32.392480 INFO: [NOCDAPC] D0_APC_0: 0x0
9686 00:25:32.395714 INFO: [NOCDAPC] D0_APC_1: 0x0
9687 00:25:32.399507 INFO: [NOCDAPC] D1_APC_0: 0x0
9688 00:25:32.402252 INFO: [NOCDAPC] D1_APC_1: 0xfff
9689 00:25:32.405545 INFO: [NOCDAPC] D2_APC_0: 0x0
9690 00:25:32.408798 INFO: [NOCDAPC] D2_APC_1: 0xfff
9691 00:25:32.412245 INFO: [NOCDAPC] D3_APC_0: 0x0
9692 00:25:32.415883 INFO: [NOCDAPC] D3_APC_1: 0xfff
9693 00:25:32.416311 INFO: [NOCDAPC] D4_APC_0: 0x0
9694 00:25:32.419157 INFO: [NOCDAPC] D4_APC_1: 0xfff
9695 00:25:32.422352 INFO: [NOCDAPC] D5_APC_0: 0x0
9696 00:25:32.425715 INFO: [NOCDAPC] D5_APC_1: 0xfff
9697 00:25:32.429040 INFO: [NOCDAPC] D6_APC_0: 0x0
9698 00:25:32.432358 INFO: [NOCDAPC] D6_APC_1: 0xfff
9699 00:25:32.435625 INFO: [NOCDAPC] D7_APC_0: 0x0
9700 00:25:32.438932 INFO: [NOCDAPC] D7_APC_1: 0xfff
9701 00:25:32.442204 INFO: [NOCDAPC] D8_APC_0: 0x0
9702 00:25:32.445897 INFO: [NOCDAPC] D8_APC_1: 0xfff
9703 00:25:32.446459 INFO: [NOCDAPC] D9_APC_0: 0x0
9704 00:25:32.449138 INFO: [NOCDAPC] D9_APC_1: 0xfff
9705 00:25:32.453043 INFO: [NOCDAPC] D10_APC_0: 0x0
9706 00:25:32.455486 INFO: [NOCDAPC] D10_APC_1: 0xfff
9707 00:25:32.459167 INFO: [NOCDAPC] D11_APC_0: 0x0
9708 00:25:32.462715 INFO: [NOCDAPC] D11_APC_1: 0xfff
9709 00:25:32.466289 INFO: [NOCDAPC] D12_APC_0: 0x0
9710 00:25:32.469127 INFO: [NOCDAPC] D12_APC_1: 0xfff
9711 00:25:32.472696 INFO: [NOCDAPC] D13_APC_0: 0x0
9712 00:25:32.475634 INFO: [NOCDAPC] D13_APC_1: 0xfff
9713 00:25:32.478900 INFO: [NOCDAPC] D14_APC_0: 0x0
9714 00:25:32.482768 INFO: [NOCDAPC] D14_APC_1: 0xfff
9715 00:25:32.485599 INFO: [NOCDAPC] D15_APC_0: 0x0
9716 00:25:32.488975 INFO: [NOCDAPC] D15_APC_1: 0xfff
9717 00:25:32.489484 INFO: [NOCDAPC] APC_CON: 0x4
9718 00:25:32.495669 INFO: [APUAPC] set_apusys_apc done
9719 00:25:32.496117 INFO: [DEVAPC] devapc_init done
9720 00:25:32.501906 INFO: GICv3 without legacy support detected.
9721 00:25:32.505624 INFO: ARM GICv3 driver initialized in EL3
9722 00:25:32.508770 INFO: Maximum SPI INTID supported: 639
9723 00:25:32.511773 INFO: BL31: Initializing runtime services
9724 00:25:32.518967 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9725 00:25:32.521856 INFO: SPM: enable CPC mode
9726 00:25:32.525557 INFO: mcdi ready for mcusys-off-idle and system suspend
9727 00:25:32.532597 INFO: BL31: Preparing for EL3 exit to normal world
9728 00:25:32.535196 INFO: Entry point address = 0x80000000
9729 00:25:32.535624 INFO: SPSR = 0x8
9730 00:25:32.543051
9731 00:25:32.543554
9732 00:25:32.543886
9733 00:25:32.545871 Starting depthcharge on Spherion...
9734 00:25:32.546340
9735 00:25:32.546675 Wipe memory regions:
9736 00:25:32.546980
9737 00:25:32.549285 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
9738 00:25:32.549811 start: 2.2.4 bootloader-commands (timeout 00:04:21) [common]
9739 00:25:32.550267 Setting prompt string to ['asurada:']
9740 00:25:32.550685 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:21)
9741 00:25:32.551325 [0x00000040000000, 0x00000054600000)
9742 00:25:32.671685
9743 00:25:32.672201 [0x00000054660000, 0x00000080000000)
9744 00:25:32.931512
9745 00:25:32.931650 [0x000000821a7280, 0x000000ffe64000)
9746 00:25:33.677527
9747 00:25:33.678002 [0x00000100000000, 0x00000140000000)
9748 00:25:34.057654
9749 00:25:34.061373 Initializing XHCI USB controller at 0x11200000.
9750 00:25:35.099816
9751 00:25:35.102352 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9752 00:25:35.102788
9753 00:25:35.103129
9754 00:25:35.103872 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9756 00:25:35.205031 asurada: tftpboot 192.168.201.1 14479191/tftp-deploy-tqgh2cqp/kernel/image.itb 14479191/tftp-deploy-tqgh2cqp/kernel/cmdline
9757 00:25:35.205733 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9758 00:25:35.206187 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:19)
9759 00:25:35.210743 tftpboot 192.168.201.1 14479191/tftp-deploy-tqgh2cqp/kernel/image.itp-deploy-tqgh2cqp/kernel/cmdline
9760 00:25:35.211193
9761 00:25:35.211518 Waiting for link
9762 00:25:35.368735
9763 00:25:35.368870 R8152: Initializing
9764 00:25:35.368928
9765 00:25:35.371949 Version 9 (ocp_data = 6010)
9766 00:25:35.372024
9767 00:25:35.375063 R8152: Done initializing
9768 00:25:35.375138
9769 00:25:35.375196 Adding net device
9770 00:25:37.292633
9771 00:25:37.293190 done.
9772 00:25:37.293528
9773 00:25:37.293953 MAC: 00:e0:4c:68:03:bd
9774 00:25:37.294312
9775 00:25:37.295205 Sending DHCP discover... done.
9776 00:25:37.295630
9777 00:25:37.298669 Waiting for reply... done.
9778 00:25:37.299122
9779 00:25:37.302288 Sending DHCP request... done.
9780 00:25:37.302726
9781 00:25:37.306199 Waiting for reply... done.
9782 00:25:37.306775
9783 00:25:37.307128 My ip is 192.168.201.16
9784 00:25:37.307461
9785 00:25:37.309881 The DHCP server ip is 192.168.201.1
9786 00:25:37.310479
9787 00:25:37.315862 TFTP server IP predefined by user: 192.168.201.1
9788 00:25:37.316288
9789 00:25:37.323198 Bootfile predefined by user: 14479191/tftp-deploy-tqgh2cqp/kernel/image.itb
9790 00:25:37.323626
9791 00:25:37.325936 Sending tftp read request... done.
9792 00:25:37.326408
9793 00:25:37.333848 Waiting for the transfer...
9794 00:25:37.334318
9795 00:25:37.627636 00000000 ################################################################
9796 00:25:37.627765
9797 00:25:37.880675 00080000 ################################################################
9798 00:25:37.880799
9799 00:25:38.130667 00100000 ################################################################
9800 00:25:38.130792
9801 00:25:38.380323 00180000 ################################################################
9802 00:25:38.380466
9803 00:25:38.629250 00200000 ################################################################
9804 00:25:38.629402
9805 00:25:38.879586 00280000 ################################################################
9806 00:25:38.879708
9807 00:25:39.129680 00300000 ################################################################
9808 00:25:39.129822
9809 00:25:39.380770 00380000 ################################################################
9810 00:25:39.380911
9811 00:25:39.630581 00400000 ################################################################
9812 00:25:39.630725
9813 00:25:39.879838 00480000 ################################################################
9814 00:25:39.879969
9815 00:25:40.129135 00500000 ################################################################
9816 00:25:40.129288
9817 00:25:40.378795 00580000 ################################################################
9818 00:25:40.378916
9819 00:25:40.634670 00600000 ################################################################
9820 00:25:40.634800
9821 00:25:40.883391 00680000 ################################################################
9822 00:25:40.883536
9823 00:25:41.132224 00700000 ################################################################
9824 00:25:41.132347
9825 00:25:41.383098 00780000 ################################################################
9826 00:25:41.383209
9827 00:25:41.633950 00800000 ################################################################
9828 00:25:41.634093
9829 00:25:41.883921 00880000 ################################################################
9830 00:25:41.884041
9831 00:25:42.137630 00900000 ################################################################
9832 00:25:42.137745
9833 00:25:42.390889 00980000 ################################################################
9834 00:25:42.391040
9835 00:25:42.640945 00a00000 ################################################################
9836 00:25:42.641071
9837 00:25:42.906568 00a80000 ################################################################
9838 00:25:42.906688
9839 00:25:43.155332 00b00000 ################################################################
9840 00:25:43.155452
9841 00:25:43.410008 00b80000 ################################################################
9842 00:25:43.410134
9843 00:25:43.659757 00c00000 ################################################################
9844 00:25:43.659901
9845 00:25:43.922036 00c80000 ################################################################
9846 00:25:43.922182
9847 00:25:44.178491 00d00000 ################################################################
9848 00:25:44.178619
9849 00:25:44.427863 00d80000 ################################################################
9850 00:25:44.427987
9851 00:25:44.677175 00e00000 ################################################################
9852 00:25:44.677300
9853 00:25:44.927540 00e80000 ################################################################
9854 00:25:44.927662
9855 00:25:45.177859 00f00000 ################################################################
9856 00:25:45.178002
9857 00:25:45.427153 00f80000 ################################################################
9858 00:25:45.427279
9859 00:25:45.681489 01000000 ################################################################
9860 00:25:45.681614
9861 00:25:45.932645 01080000 ################################################################
9862 00:25:45.932772
9863 00:25:46.181529 01100000 ################################################################
9864 00:25:46.181639
9865 00:25:46.439127 01180000 ################################################################
9866 00:25:46.439254
9867 00:25:46.712967 01200000 ################################################################
9868 00:25:46.713095
9869 00:25:46.961589 01280000 ################################################################
9870 00:25:46.961715
9871 00:25:47.226084 01300000 ################################################################
9872 00:25:47.226223
9873 00:25:47.476117 01380000 ################################################################
9874 00:25:47.476243
9875 00:25:47.728083 01400000 ################################################################
9876 00:25:47.728202
9877 00:25:47.990505 01480000 ################################################################
9878 00:25:47.990624
9879 00:25:48.237455 01500000 ################################################################
9880 00:25:48.237582
9881 00:25:48.485627 01580000 ################################################################
9882 00:25:48.485754
9883 00:25:48.735223 01600000 ################################################################
9884 00:25:48.735347
9885 00:25:48.992441 01680000 ################################################################
9886 00:25:48.992565
9887 00:25:49.248200 01700000 ################################################################
9888 00:25:49.248327
9889 00:25:49.499682 01780000 ################################################################
9890 00:25:49.499808
9891 00:25:49.748963 01800000 ################################################################
9892 00:25:49.749086
9893 00:25:49.998725 01880000 ################################################################
9894 00:25:49.998851
9895 00:25:50.262695 01900000 ################################################################
9896 00:25:50.262821
9897 00:25:50.510829 01980000 ################################################################
9898 00:25:50.510956
9899 00:25:50.759221 01a00000 ################################################################
9900 00:25:50.759349
9901 00:25:51.008968 01a80000 ################################################################
9902 00:25:51.009092
9903 00:25:51.257108 01b00000 ################################################################
9904 00:25:51.257235
9905 00:25:51.505935 01b80000 ################################################################
9906 00:25:51.506063
9907 00:25:51.754896 01c00000 ################################################################
9908 00:25:51.755022
9909 00:25:52.008701 01c80000 ################################################################
9910 00:25:52.008828
9911 00:25:52.263813 01d00000 ################################################################
9912 00:25:52.263934
9913 00:25:52.512606 01d80000 ################################################################
9914 00:25:52.512732
9915 00:25:52.762828 01e00000 ################################################################
9916 00:25:52.762941
9917 00:25:53.011191 01e80000 ################################################################
9918 00:25:53.011318
9919 00:25:53.260455 01f00000 ################################################################
9920 00:25:53.260623
9921 00:25:53.512311 01f80000 ################################################################
9922 00:25:53.512435
9923 00:25:53.774994 02000000 ################################################################
9924 00:25:53.775120
9925 00:25:54.029970 02080000 ################################################################
9926 00:25:54.030087
9927 00:25:54.277871 02100000 ################################################################
9928 00:25:54.278000
9929 00:25:54.527325 02180000 ################################################################
9930 00:25:54.527450
9931 00:25:54.777899 02200000 ################################################################
9932 00:25:54.778020
9933 00:25:55.027360 02280000 ################################################################
9934 00:25:55.027482
9935 00:25:55.289367 02300000 ################################################################
9936 00:25:55.289493
9937 00:25:55.538094 02380000 ################################################################
9938 00:25:55.538239
9939 00:25:55.790894 02400000 ################################################################
9940 00:25:55.791024
9941 00:25:56.043301 02480000 ################################################################
9942 00:25:56.043428
9943 00:25:56.291449 02500000 ################################################################
9944 00:25:56.291575
9945 00:25:56.540419 02580000 ################################################################
9946 00:25:56.540546
9947 00:25:56.789042 02600000 ################################################################
9948 00:25:56.789166
9949 00:25:57.037342 02680000 ################################################################
9950 00:25:57.037469
9951 00:25:57.286602 02700000 ################################################################
9952 00:25:57.286727
9953 00:25:57.534833 02780000 ################################################################
9954 00:25:57.534961
9955 00:25:57.783426 02800000 ################################################################
9956 00:25:57.783550
9957 00:25:58.059504 02880000 ################################################################
9958 00:25:58.059633
9959 00:25:58.321530 02900000 ################################################################
9960 00:25:58.321655
9961 00:25:58.585145 02980000 ################################################################
9962 00:25:58.585282
9963 00:25:58.846914 02a00000 ################################################################
9964 00:25:58.847042
9965 00:25:59.095650 02a80000 ################################################################
9966 00:25:59.095777
9967 00:25:59.345695 02b00000 ################################################################
9968 00:25:59.345819
9969 00:25:59.599327 02b80000 ################################################################
9970 00:25:59.599473
9971 00:25:59.847902 02c00000 ################################################################
9972 00:25:59.848047
9973 00:26:00.101244 02c80000 ################################################################
9974 00:26:00.101367
9975 00:26:00.354014 02d00000 ################################################################
9976 00:26:00.354138
9977 00:26:00.606437 02d80000 ################################################################
9978 00:26:00.606560
9979 00:26:00.858788 02e00000 ################################################################
9980 00:26:00.858957
9981 00:26:01.120632 02e80000 ################################################################
9982 00:26:01.120757
9983 00:26:01.373209 02f00000 ################################################################
9984 00:26:01.373335
9985 00:26:01.628258 02f80000 ################################################################
9986 00:26:01.628381
9987 00:26:01.879579 03000000 ################################################################
9988 00:26:01.879709
9989 00:26:02.137033 03080000 ################################################################
9990 00:26:02.137161
9991 00:26:02.384429 03100000 ################################################################
9992 00:26:02.384558
9993 00:26:02.634042 03180000 ################################################################
9994 00:26:02.634180
9995 00:26:02.881579 03200000 ################################################################
9996 00:26:02.881707
9997 00:26:03.131424 03280000 ################################################################
9998 00:26:03.131548
9999 00:26:03.381024 03300000 ################################################################
10000 00:26:03.381146
10001 00:26:03.631517 03380000 ################################################################
10002 00:26:03.631635
10003 00:26:03.901873 03400000 ################################################################
10004 00:26:03.901996
10005 00:26:04.174956 03480000 ################################################################
10006 00:26:04.175079
10007 00:26:04.427817 03500000 ################################################################
10008 00:26:04.427944
10009 00:26:04.691736 03580000 ################################################################
10010 00:26:04.691867
10011 00:26:04.946516 03600000 ################################################################
10012 00:26:04.946641
10013 00:26:05.198944 03680000 ################################################################
10014 00:26:05.199066
10015 00:26:05.458819 03700000 ################################################################
10016 00:26:05.458944
10017 00:26:05.727233 03780000 ################################################################
10018 00:26:05.727359
10019 00:26:05.993545 03800000 ################################################################
10020 00:26:05.993695
10021 00:26:06.258687 03880000 ################################################################
10022 00:26:06.258812
10023 00:26:06.508504 03900000 ################################################################
10024 00:26:06.508627
10025 00:26:06.759878 03980000 ################################################################
10026 00:26:06.759993
10027 00:26:07.008506 03a00000 ################################################################
10028 00:26:07.008628
10029 00:26:07.257499 03a80000 ################################################################
10030 00:26:07.257621
10031 00:26:07.506078 03b00000 ################################################################
10032 00:26:07.506204
10033 00:26:07.774635 03b80000 ################################################################
10034 00:26:07.774765
10035 00:26:08.028133 03c00000 ################################################################
10036 00:26:08.028256
10037 00:26:08.312470 03c80000 ################################################################
10038 00:26:08.312599
10039 00:26:08.565283 03d00000 ################################################################
10040 00:26:08.565407
10041 00:26:08.827786 03d80000 ################################################################
10042 00:26:08.827913
10043 00:26:09.078034 03e00000 ################################################################
10044 00:26:09.078197
10045 00:26:09.328721 03e80000 ################################################################
10046 00:26:09.328842
10047 00:26:09.578721 03f00000 ################################################################
10048 00:26:09.578842
10049 00:26:09.830366 03f80000 ################################################################
10050 00:26:09.830489
10051 00:26:10.091842 04000000 ################################################################
10052 00:26:10.091971
10053 00:26:10.365920 04080000 ################################################################
10054 00:26:10.366046
10055 00:26:10.629680 04100000 ################################################################
10056 00:26:10.629804
10057 00:26:10.923409 04180000 ################################################################
10058 00:26:10.923559
10059 00:26:11.174925 04200000 ################################################################
10060 00:26:11.175048
10061 00:26:11.426423 04280000 ################################################################
10062 00:26:11.426547
10063 00:26:11.676528 04300000 ################################################################
10064 00:26:11.676655
10065 00:26:11.941567 04380000 ################################################################
10066 00:26:11.941689
10067 00:26:12.199893 04400000 ################################################################
10068 00:26:12.200016
10069 00:26:12.449874 04480000 ################################################################
10070 00:26:12.449996
10071 00:26:12.699135 04500000 ################################################################
10072 00:26:12.699262
10073 00:26:12.949070 04580000 ################################################################
10074 00:26:12.949193
10075 00:26:13.214207 04600000 ################################################################
10076 00:26:13.214339
10077 00:26:13.347165 04680000 ############################### done.
10078 00:26:13.347275
10079 00:26:13.350074 The bootfile was 74178170 bytes long.
10080 00:26:13.350177
10081 00:26:13.353631 Sending tftp read request... done.
10082 00:26:13.353709
10083 00:26:13.353768 Waiting for the transfer...
10084 00:26:13.353823
10085 00:26:13.356708 00000000 # done.
10086 00:26:13.356788
10087 00:26:13.363531 Command line loaded dynamically from TFTP file: 14479191/tftp-deploy-tqgh2cqp/kernel/cmdline
10088 00:26:13.363609
10089 00:26:13.376752 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10090 00:26:13.376830
10091 00:26:13.380001 Loading FIT.
10092 00:26:13.380078
10093 00:26:13.383080 Image ramdisk-1 has 61003990 bytes.
10094 00:26:13.383157
10095 00:26:13.383216 Image fdt-1 has 47258 bytes.
10096 00:26:13.386394
10097 00:26:13.386470 Image kernel-1 has 13124896 bytes.
10098 00:26:13.386530
10099 00:26:13.396358 Compat preference: google,spherion-rev3-sku1 google,spherion-rev3 google,spherion-sku1 google,spherion
10100 00:26:13.396502
10101 00:26:13.412905 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 (match) google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10102 00:26:13.416416
10103 00:26:13.419309 Choosing best match conf-1 for compat google,spherion-rev3.
10104 00:26:13.424257
10105 00:26:13.428344 Connected to device vid:did:rid of 1ae0:0028:00
10106 00:26:13.435457
10107 00:26:13.438791 tpm_get_response: command 0x17b, return code 0x0
10108 00:26:13.438867
10109 00:26:13.442180 ec_init: CrosEC protocol v3 supported (256, 248)
10110 00:26:13.446144
10111 00:26:13.449713 tpm_cleanup: add release locality here.
10112 00:26:13.449813
10113 00:26:13.449898 Shutting down all USB controllers.
10114 00:26:13.452712
10115 00:26:13.452788 Removing current net device
10116 00:26:13.452847
10117 00:26:13.459755 Exiting depthcharge with code 4 at timestamp: 69131936
10118 00:26:13.459833
10119 00:26:13.462952 LZMA decompressing kernel-1 to 0x821a6718
10120 00:26:13.463034
10121 00:26:13.466128 LZMA decompressing kernel-1 to 0x40000000
10122 00:26:15.082106
10123 00:26:15.082626 jumping to kernel
10124 00:26:15.084759 end: 2.2.4 bootloader-commands (duration 00:00:43) [common]
10125 00:26:15.085270 start: 2.2.5 auto-login-action (timeout 00:03:39) [common]
10126 00:26:15.085642 Setting prompt string to ['Linux version [0-9]']
10127 00:26:15.085993 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10128 00:26:15.086381 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10129 00:26:15.134012
10130 00:26:15.137694 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10131 00:26:15.140999 start: 2.2.5.1 login-action (timeout 00:03:39) [common]
10132 00:26:15.141495 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10133 00:26:15.141871 Setting prompt string to []
10134 00:26:15.142318 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10135 00:26:15.142697 Using line separator: #'\n'#
10136 00:26:15.142976 No login prompt set.
10137 00:26:15.143270 Parsing kernel messages
10138 00:26:15.143534 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10139 00:26:15.144044 [login-action] Waiting for messages, (timeout 00:03:39)
10140 00:26:15.144367 Waiting using forced prompt support (timeout 00:01:49)
10141 00:26:15.159818 [ 0.000000] Linux version 6.1.94-cip23 (KernelCI@build-j239242-arm64-gcc-10-defconfig-arm64-chromebook-c5lwc) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Jun 21 00:04:56 UTC 2024
10142 00:26:15.163471 [ 0.000000] random: crng init done
10143 00:26:15.169842 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10144 00:26:15.173109 [ 0.000000] efi: UEFI not found.
10145 00:26:15.179709 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10146 00:26:15.186576 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10147 00:26:15.196651 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10148 00:26:15.206623 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10149 00:26:15.213043 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10150 00:26:15.219760 [ 0.000000] printk: bootconsole [mtk8250] enabled
10151 00:26:15.226362 [ 0.000000] NUMA: No NUMA configuration found
10152 00:26:15.233042 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10153 00:26:15.236474 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d5a00-0x13f7d7fff]
10154 00:26:15.239639 [ 0.000000] Zone ranges:
10155 00:26:15.246131 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10156 00:26:15.249580 [ 0.000000] DMA32 empty
10157 00:26:15.255861 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10158 00:26:15.259563 [ 0.000000] Movable zone start for each node
10159 00:26:15.262359 [ 0.000000] Early memory node ranges
10160 00:26:15.269332 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10161 00:26:15.276380 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10162 00:26:15.282694 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10163 00:26:15.289242 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10164 00:26:15.296178 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10165 00:26:15.301943 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10166 00:26:15.332416 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10167 00:26:15.339256 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10168 00:26:15.345897 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10169 00:26:15.349119 [ 0.000000] psci: probing for conduit method from DT.
10170 00:26:15.356091 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10171 00:26:15.358971 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10172 00:26:15.366035 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10173 00:26:15.369085 [ 0.000000] psci: SMC Calling Convention v1.2
10174 00:26:15.375932 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10175 00:26:15.379133 [ 0.000000] Detected VIPT I-cache on CPU0
10176 00:26:15.385658 [ 0.000000] CPU features: detected: GIC system register CPU interface
10177 00:26:15.392725 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10178 00:26:15.398793 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10179 00:26:15.405281 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10180 00:26:15.412291 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10181 00:26:15.422019 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10182 00:26:15.425127 [ 0.000000] alternatives: applying boot alternatives
10183 00:26:15.431382 [ 0.000000] Fallback order for Node 0: 0
10184 00:26:15.438168 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10185 00:26:15.441630 [ 0.000000] Policy zone: Normal
10186 00:26:15.454883 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10187 00:26:15.465057 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10188 00:26:15.475407 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10189 00:26:15.485043 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10190 00:26:15.491929 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10191 00:26:15.494944 <6>[ 0.000000] software IO TLB: area num 8.
10192 00:26:15.551194 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10193 00:26:15.631789 <6>[ 0.000000] Memory: 3790072K/4191232K available (18112K kernel code, 4120K rwdata, 22648K rodata, 8512K init, 616K bss, 368392K reserved, 32768K cma-reserved)
10194 00:26:15.638457 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10195 00:26:15.645079 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10196 00:26:15.648572 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10197 00:26:15.655188 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10198 00:26:15.661599 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10199 00:26:15.664862 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10200 00:26:15.675016 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10201 00:26:15.681478 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10202 00:26:15.688236 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10203 00:26:15.694600 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10204 00:26:15.698059 <6>[ 0.000000] GICv3: 608 SPIs implemented
10205 00:26:15.701362 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10206 00:26:15.708009 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10207 00:26:15.711384 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10208 00:26:15.718362 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10209 00:26:15.731046 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10210 00:26:15.744225 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10211 00:26:15.751103 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10212 00:26:15.758196 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10213 00:26:15.771245 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10214 00:26:15.777952 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10215 00:26:15.784774 <6>[ 0.009172] Console: colour dummy device 80x25
10216 00:26:15.794626 <6>[ 0.013929] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10217 00:26:15.801151 <6>[ 0.024371] pid_max: default: 32768 minimum: 301
10218 00:26:15.804514 <6>[ 0.029243] LSM: Security Framework initializing
10219 00:26:15.811179 <6>[ 0.034154] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10220 00:26:15.821272 <6>[ 0.041761] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10221 00:26:15.827748 <6>[ 0.050937] cblist_init_generic: Setting adjustable number of callback queues.
10222 00:26:15.834629 <6>[ 0.058379] cblist_init_generic: Setting shift to 3 and lim to 1.
10223 00:26:15.844484 <6>[ 0.064717] cblist_init_generic: Setting adjustable number of callback queues.
10224 00:26:15.847993 <6>[ 0.072144] cblist_init_generic: Setting shift to 3 and lim to 1.
10225 00:26:15.854606 <6>[ 0.078553] rcu: Hierarchical SRCU implementation.
10226 00:26:15.861629 <6>[ 0.083568] rcu: Max phase no-delay instances is 1000.
10227 00:26:15.867524 <6>[ 0.090620] EFI services will not be available.
10228 00:26:15.870968 <6>[ 0.095579] smp: Bringing up secondary CPUs ...
10229 00:26:15.878566 <6>[ 0.100626] Detected VIPT I-cache on CPU1
10230 00:26:15.885076 <6>[ 0.100694] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10231 00:26:15.891581 <6>[ 0.100723] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10232 00:26:15.895071 <6>[ 0.101056] Detected VIPT I-cache on CPU2
10233 00:26:15.901937 <6>[ 0.101104] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10234 00:26:15.911637 <6>[ 0.101119] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10235 00:26:15.914838 <6>[ 0.101375] Detected VIPT I-cache on CPU3
10236 00:26:15.921463 <6>[ 0.101421] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10237 00:26:15.928189 <6>[ 0.101435] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10238 00:26:15.931835 <6>[ 0.101740] CPU features: detected: Spectre-v4
10239 00:26:15.938081 <6>[ 0.101745] CPU features: detected: Spectre-BHB
10240 00:26:15.941864 <6>[ 0.101750] Detected PIPT I-cache on CPU4
10241 00:26:15.948280 <6>[ 0.101807] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10242 00:26:15.954804 <6>[ 0.101823] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10243 00:26:15.961520 <6>[ 0.102118] Detected PIPT I-cache on CPU5
10244 00:26:15.968082 <6>[ 0.102178] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10245 00:26:15.974352 <6>[ 0.102194] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10246 00:26:15.977632 <6>[ 0.102472] Detected PIPT I-cache on CPU6
10247 00:26:15.984203 <6>[ 0.102534] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10248 00:26:15.990955 <6>[ 0.102550] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10249 00:26:15.997580 <6>[ 0.102850] Detected PIPT I-cache on CPU7
10250 00:26:16.004295 <6>[ 0.102914] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10251 00:26:16.010807 <6>[ 0.102930] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10252 00:26:16.014071 <6>[ 0.102978] smp: Brought up 1 node, 8 CPUs
10253 00:26:16.020673 <6>[ 0.244288] SMP: Total of 8 processors activated.
10254 00:26:16.024049 <6>[ 0.249240] CPU features: detected: 32-bit EL0 Support
10255 00:26:16.033945 <6>[ 0.254636] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10256 00:26:16.040312 <6>[ 0.263437] CPU features: detected: Common not Private translations
10257 00:26:16.047021 <6>[ 0.269913] CPU features: detected: CRC32 instructions
10258 00:26:16.050634 <6>[ 0.275264] CPU features: detected: RCpc load-acquire (LDAPR)
10259 00:26:16.056795 <6>[ 0.281224] CPU features: detected: LSE atomic instructions
10260 00:26:16.063345 <6>[ 0.287042] CPU features: detected: Privileged Access Never
10261 00:26:16.070045 <6>[ 0.292822] CPU features: detected: RAS Extension Support
10262 00:26:16.077032 <6>[ 0.298431] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10263 00:26:16.079818 <6>[ 0.305692] CPU: All CPU(s) started at EL2
10264 00:26:16.086453 <6>[ 0.310009] alternatives: applying system-wide alternatives
10265 00:26:16.095630 <6>[ 0.319964] devtmpfs: initialized
10266 00:26:16.110307 <6>[ 0.328164] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10267 00:26:16.116718 <6>[ 0.338123] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10268 00:26:16.123752 <6>[ 0.346368] pinctrl core: initialized pinctrl subsystem
10269 00:26:16.126882 <6>[ 0.353041] DMI not present or invalid.
10270 00:26:16.133396 <6>[ 0.357446] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10271 00:26:16.142894 <6>[ 0.364301] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
10272 00:26:16.149765 <6>[ 0.371744] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10273 00:26:16.159948 <6>[ 0.379834] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10274 00:26:16.163556 <6>[ 0.387989] audit: initializing netlink subsys (disabled)
10275 00:26:16.172579 <5>[ 0.393682] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10276 00:26:16.179247 <6>[ 0.394385] thermal_sys: Registered thermal governor 'step_wise'
10277 00:26:16.186187 <6>[ 0.401651] thermal_sys: Registered thermal governor 'power_allocator'
10278 00:26:16.189583 <6>[ 0.407908] cpuidle: using governor menu
10279 00:26:16.195719 <6>[ 0.418865] NET: Registered PF_QIPCRTR protocol family
10280 00:26:16.202880 <6>[ 0.424338] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10281 00:26:16.208799 <6>[ 0.431438] ASID allocator initialised with 32768 entries
10282 00:26:16.212108 <6>[ 0.437986] Serial: AMBA PL011 UART driver
10283 00:26:16.222707 <4>[ 0.446811] Trying to register duplicate clock ID: 134
10284 00:26:16.280316 <6>[ 0.508107] KASLR enabled
10285 00:26:16.294755 <6>[ 0.515747] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10286 00:26:16.301228 <6>[ 0.522757] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10287 00:26:16.307840 <6>[ 0.529247] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10288 00:26:16.314502 <6>[ 0.536252] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10289 00:26:16.320850 <6>[ 0.542738] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10290 00:26:16.327405 <6>[ 0.549744] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10291 00:26:16.334340 <6>[ 0.556228] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10292 00:26:16.340915 <6>[ 0.563232] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10293 00:26:16.344010 <6>[ 0.570669] ACPI: Interpreter disabled.
10294 00:26:16.352555 <6>[ 0.577061] iommu: Default domain type: Translated
10295 00:26:16.359087 <6>[ 0.582214] iommu: DMA domain TLB invalidation policy: strict mode
10296 00:26:16.362634 <5>[ 0.588873] SCSI subsystem initialized
10297 00:26:16.369180 <6>[ 0.593122] usbcore: registered new interface driver usbfs
10298 00:26:16.376213 <6>[ 0.598854] usbcore: registered new interface driver hub
10299 00:26:16.379420 <6>[ 0.604405] usbcore: registered new device driver usb
10300 00:26:16.386432 <6>[ 0.610516] pps_core: LinuxPPS API ver. 1 registered
10301 00:26:16.395733 <6>[ 0.615711] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10302 00:26:16.399301 <6>[ 0.625055] PTP clock support registered
10303 00:26:16.402609 <6>[ 0.629295] EDAC MC: Ver: 3.0.0
10304 00:26:16.409893 <6>[ 0.634474] FPGA manager framework
10305 00:26:16.416397 <6>[ 0.638152] Advanced Linux Sound Architecture Driver Initialized.
10306 00:26:16.419863 <6>[ 0.644923] vgaarb: loaded
10307 00:26:16.426390 <6>[ 0.648065] clocksource: Switched to clocksource arch_sys_counter
10308 00:26:16.429850 <5>[ 0.654506] VFS: Disk quotas dquot_6.6.0
10309 00:26:16.436428 <6>[ 0.658694] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10310 00:26:16.439630 <6>[ 0.665885] pnp: PnP ACPI: disabled
10311 00:26:16.448589 <6>[ 0.672544] NET: Registered PF_INET protocol family
10312 00:26:16.454920 <6>[ 0.677929] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
10313 00:26:16.466439 <6>[ 0.687933] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
10314 00:26:16.476301 <6>[ 0.696720] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10315 00:26:16.483066 <6>[ 0.704685] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
10316 00:26:16.489465 <6>[ 0.713088] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
10317 00:26:16.500159 <6>[ 0.721746] TCP: Hash tables configured (established 32768 bind 32768)
10318 00:26:16.506795 <6>[ 0.728610] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
10319 00:26:16.513438 <6>[ 0.735631] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
10320 00:26:16.520436 <6>[ 0.743156] NET: Registered PF_UNIX/PF_LOCAL protocol family
10321 00:26:16.526837 <6>[ 0.749299] RPC: Registered named UNIX socket transport module.
10322 00:26:16.530164 <6>[ 0.755453] RPC: Registered udp transport module.
10323 00:26:16.536505 <6>[ 0.760385] RPC: Registered tcp transport module.
10324 00:26:16.543378 <6>[ 0.765318] RPC: Registered tcp NFSv4.1 backchannel transport module.
10325 00:26:16.546489 <6>[ 0.771982] PCI: CLS 0 bytes, default 64
10326 00:26:16.549988 <6>[ 0.776307] Unpacking initramfs...
10327 00:26:16.574550 <6>[ 0.796258] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10328 00:26:16.584718 <6>[ 0.804920] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10329 00:26:16.587787 <6>[ 0.813762] kvm [1]: IPA Size Limit: 40 bits
10330 00:26:16.594573 <6>[ 0.818291] kvm [1]: GICv3: no GICV resource entry
10331 00:26:16.598030 <6>[ 0.823314] kvm [1]: disabling GICv2 emulation
10332 00:26:16.604548 <6>[ 0.827997] kvm [1]: GIC system register CPU interface enabled
10333 00:26:16.607770 <6>[ 0.834159] kvm [1]: vgic interrupt IRQ18
10334 00:26:16.614378 <6>[ 0.838520] kvm [1]: VHE mode initialized successfully
10335 00:26:16.620982 <5>[ 0.844970] Initialise system trusted keyrings
10336 00:26:16.627873 <6>[ 0.849778] workingset: timestamp_bits=42 max_order=20 bucket_order=0
10337 00:26:16.635076 <6>[ 0.859843] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10338 00:26:16.641969 <5>[ 0.866241] NFS: Registering the id_resolver key type
10339 00:26:16.645457 <5>[ 0.871542] Key type id_resolver registered
10340 00:26:16.652034 <5>[ 0.875958] Key type id_legacy registered
10341 00:26:16.658725 <6>[ 0.880239] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10342 00:26:16.664902 <6>[ 0.887164] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10343 00:26:16.671766 <6>[ 0.894887] 9p: Installing v9fs 9p2000 file system support
10344 00:26:16.708431 <5>[ 0.932648] Key type asymmetric registered
10345 00:26:16.711274 <5>[ 0.936978] Asymmetric key parser 'x509' registered
10346 00:26:16.721553 <6>[ 0.942163] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10347 00:26:16.724710 <6>[ 0.949785] io scheduler mq-deadline registered
10348 00:26:16.727834 <6>[ 0.954553] io scheduler kyber registered
10349 00:26:16.747058 <6>[ 0.971501] EINJ: ACPI disabled.
10350 00:26:16.780333 <4>[ 0.998065] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10351 00:26:16.789898 <4>[ 1.008708] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10352 00:26:16.805852 <6>[ 1.030044] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10353 00:26:16.813566 <6>[ 1.038143] printk: console [ttyS0] disabled
10354 00:26:16.841021 <6>[ 1.062781] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10355 00:26:16.847652 <6>[ 1.072255] printk: console [ttyS0] enabled
10356 00:26:16.851288 <6>[ 1.072255] printk: console [ttyS0] enabled
10357 00:26:16.857483 <6>[ 1.081150] printk: bootconsole [mtk8250] disabled
10358 00:26:16.860966 <6>[ 1.081150] printk: bootconsole [mtk8250] disabled
10359 00:26:16.868144 <6>[ 1.092473] SuperH (H)SCI(F) driver initialized
10360 00:26:16.871893 <6>[ 1.097742] msm_serial: driver initialized
10361 00:26:16.885474 <6>[ 1.106759] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10362 00:26:16.895513 <6>[ 1.115312] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10363 00:26:16.902171 <6>[ 1.123858] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10364 00:26:16.911896 <6>[ 1.132490] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10365 00:26:16.918823 <6>[ 1.141197] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10366 00:26:16.928687 <6>[ 1.149911] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10367 00:26:16.939019 <6>[ 1.158451] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10368 00:26:16.945413 <6>[ 1.167261] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10369 00:26:16.955244 <6>[ 1.175806] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10370 00:26:16.966978 <6>[ 1.191389] loop: module loaded
10371 00:26:16.973389 <6>[ 1.197298] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10372 00:26:16.996266 <4>[ 1.220715] mtk-pmic-keys: Failed to locate of_node [id: -1]
10373 00:26:17.002969 <6>[ 1.227666] megasas: 07.719.03.00-rc1
10374 00:26:17.013173 <6>[ 1.237488] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10375 00:26:17.019821 <6>[ 1.243439] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10376 00:26:17.035894 <6>[ 1.259950] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10377 00:26:17.091637 <6>[ 1.309574] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10378 00:26:19.244354 <6>[ 3.469269] Freeing initrd memory: 59568K
10379 00:26:19.255943 <6>[ 3.481003] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10380 00:26:19.266669 <6>[ 3.491953] tun: Universal TUN/TAP device driver, 1.6
10381 00:26:19.270045 <6>[ 3.498010] thunder_xcv, ver 1.0
10382 00:26:19.273434 <6>[ 3.501516] thunder_bgx, ver 1.0
10383 00:26:19.276823 <6>[ 3.505013] nicpf, ver 1.0
10384 00:26:19.287472 <6>[ 3.509036] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10385 00:26:19.290604 <6>[ 3.516513] hns3: Copyright (c) 2017 Huawei Corporation.
10386 00:26:19.297776 <6>[ 3.522104] hclge is initializing
10387 00:26:19.301311 <6>[ 3.525678] e1000: Intel(R) PRO/1000 Network Driver
10388 00:26:19.307479 <6>[ 3.530806] e1000: Copyright (c) 1999-2006 Intel Corporation.
10389 00:26:19.310552 <6>[ 3.536818] e1000e: Intel(R) PRO/1000 Network Driver
10390 00:26:19.317830 <6>[ 3.542034] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10391 00:26:19.324378 <6>[ 3.548219] igb: Intel(R) Gigabit Ethernet Network Driver
10392 00:26:19.330711 <6>[ 3.553868] igb: Copyright (c) 2007-2014 Intel Corporation.
10393 00:26:19.337301 <6>[ 3.559704] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10394 00:26:19.343978 <6>[ 3.566222] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10395 00:26:19.346923 <6>[ 3.572682] sky2: driver version 1.30
10396 00:26:19.353745 <6>[ 3.577604] usbcore: registered new device driver r8152-cfgselector
10397 00:26:19.360843 <6>[ 3.584142] usbcore: registered new interface driver r8152
10398 00:26:19.366850 <6>[ 3.589956] VFIO - User Level meta-driver version: 0.3
10399 00:26:19.373464 <6>[ 3.598176] usbcore: registered new interface driver usb-storage
10400 00:26:19.380464 <6>[ 3.604624] usbcore: registered new device driver onboard-usb-hub
10401 00:26:19.389056 <6>[ 3.613775] mt6397-rtc mt6359-rtc: registered as rtc0
10402 00:26:19.398899 <6>[ 3.619252] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-21T00:26:19 UTC (1718929579)
10403 00:26:19.402800 <6>[ 3.628840] i2c_dev: i2c /dev entries driver
10404 00:26:19.416496 <4>[ 3.640917] cpu cpu0: supply cpu not found, using dummy regulator
10405 00:26:19.422714 <4>[ 3.647340] cpu cpu1: supply cpu not found, using dummy regulator
10406 00:26:19.429420 <4>[ 3.653746] cpu cpu2: supply cpu not found, using dummy regulator
10407 00:26:19.435836 <4>[ 3.660151] cpu cpu3: supply cpu not found, using dummy regulator
10408 00:26:19.442480 <4>[ 3.666553] cpu cpu4: supply cpu not found, using dummy regulator
10409 00:26:19.449153 <4>[ 3.672966] cpu cpu5: supply cpu not found, using dummy regulator
10410 00:26:19.455650 <4>[ 3.679360] cpu cpu6: supply cpu not found, using dummy regulator
10411 00:26:19.462025 <4>[ 3.685757] cpu cpu7: supply cpu not found, using dummy regulator
10412 00:26:19.481709 <6>[ 3.706377] cpu cpu0: EM: created perf domain
10413 00:26:19.485201 <6>[ 3.711304] cpu cpu4: EM: created perf domain
10414 00:26:19.492350 <6>[ 3.716881] sdhci: Secure Digital Host Controller Interface driver
10415 00:26:19.498472 <6>[ 3.723309] sdhci: Copyright(c) Pierre Ossman
10416 00:26:19.505314 <6>[ 3.728222] Synopsys Designware Multimedia Card Interface Driver
10417 00:26:19.512044 <6>[ 3.734826] sdhci-pltfm: SDHCI platform and OF driver helper
10418 00:26:19.515142 <6>[ 3.734896] mmc0: CQHCI version 5.10
10419 00:26:19.521790 <6>[ 3.745159] ledtrig-cpu: registered to indicate activity on CPUs
10420 00:26:19.528203 <6>[ 3.752202] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10421 00:26:19.535562 <6>[ 3.759231] usbcore: registered new interface driver usbhid
10422 00:26:19.538139 <6>[ 3.765052] usbhid: USB HID core driver
10423 00:26:19.544999 <6>[ 3.769244] spi_master spi0: will run message pump with realtime priority
10424 00:26:19.588989 <6>[ 3.806991] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10425 00:26:19.607063 <6>[ 3.821966] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10426 00:26:19.610684 <6>[ 3.831841] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x17414
10427 00:26:19.618671 <6>[ 3.842575] cros-ec-spi spi0.0: Chrome EC device registered
10428 00:26:19.624723 <6>[ 3.848649] mmc0: Command Queue Engine enabled
10429 00:26:19.631749 <6>[ 3.853426] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10430 00:26:19.635074 <6>[ 3.860963] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10431 00:26:19.645368 <6>[ 3.869820] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10432 00:26:19.652585 <6>[ 3.877355] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10433 00:26:19.662846 <6>[ 3.882058] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10434 00:26:19.665511 <6>[ 3.883265] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10435 00:26:19.672512 <6>[ 3.893237] NET: Registered PF_PACKET protocol family
10436 00:26:19.679010 <6>[ 3.897746] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10437 00:26:19.682512 <6>[ 3.902489] 9pnet: Installing 9P2000 support
10438 00:26:19.689010 <5>[ 3.913488] Key type dns_resolver registered
10439 00:26:19.692590 <6>[ 3.918430] registered taskstats version 1
10440 00:26:19.699138 <5>[ 3.922807] Loading compiled-in X.509 certificates
10441 00:26:19.728326 <4>[ 3.946309] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10442 00:26:19.738507 <4>[ 3.957032] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10443 00:26:19.752738 <6>[ 3.977746] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10444 00:26:19.759652 <6>[ 3.984698] xhci-mtk 11200000.usb: xHCI Host Controller
10445 00:26:19.766270 <6>[ 3.990246] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10446 00:26:19.776331 <6>[ 3.998100] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10447 00:26:19.783101 <6>[ 4.007536] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10448 00:26:19.790205 <6>[ 4.013698] xhci-mtk 11200000.usb: xHCI Host Controller
10449 00:26:19.796504 <6>[ 4.019190] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10450 00:26:19.803050 <6>[ 4.026845] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10451 00:26:19.810723 <6>[ 4.034674] hub 1-0:1.0: USB hub found
10452 00:26:19.813127 <6>[ 4.038700] hub 1-0:1.0: 1 port detected
10453 00:26:19.823369 <6>[ 4.042990] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10454 00:26:19.826858 <6>[ 4.051743] hub 2-0:1.0: USB hub found
10455 00:26:19.830201 <6>[ 4.055764] hub 2-0:1.0: 1 port detected
10456 00:26:19.838158 <6>[ 4.062689] mtk-msdc 11f70000.mmc: Got CD GPIO
10457 00:26:19.851311 <6>[ 4.072951] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10458 00:26:19.861532 <6>[ 4.081333] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10459 00:26:19.868443 <6>[ 4.089674] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10460 00:26:19.877854 <6>[ 4.098015] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10461 00:26:19.884430 <6>[ 4.106354] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10462 00:26:19.894404 <6>[ 4.114692] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10463 00:26:19.901068 <6>[ 4.123031] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10464 00:26:19.910877 <6>[ 4.131369] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10465 00:26:19.917631 <6>[ 4.139711] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10466 00:26:19.927862 <6>[ 4.148047] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10467 00:26:19.934314 <6>[ 4.156385] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10468 00:26:19.944265 <6>[ 4.164729] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10469 00:26:19.950767 <6>[ 4.173067] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10470 00:26:19.960305 <6>[ 4.181403] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10471 00:26:19.966976 <6>[ 4.189741] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10472 00:26:19.973734 <6>[ 4.198414] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10473 00:26:19.980592 <6>[ 4.205518] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10474 00:26:19.987440 <6>[ 4.212305] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10475 00:26:19.998131 <6>[ 4.219071] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10476 00:26:20.004172 <6>[ 4.225983] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10477 00:26:20.010901 <6>[ 4.232884] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10478 00:26:20.020536 <6>[ 4.242016] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10479 00:26:20.030661 <6>[ 4.251138] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10480 00:26:20.040536 <6>[ 4.260431] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10481 00:26:20.050694 <6>[ 4.269896] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10482 00:26:20.061074 <6>[ 4.279362] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10483 00:26:20.067040 <6>[ 4.288481] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10484 00:26:20.076887 <6>[ 4.297947] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10485 00:26:20.086509 <6>[ 4.307065] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10486 00:26:20.096210 <6>[ 4.316358] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10487 00:26:20.106199 <6>[ 4.326519] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10488 00:26:20.116190 <6>[ 4.338177] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10489 00:26:20.242399 <6>[ 4.464335] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10490 00:26:20.397227 <6>[ 4.621874] hub 1-1:1.0: USB hub found
10491 00:26:20.400324 <6>[ 4.626406] hub 1-1:1.0: 4 ports detected
10492 00:26:20.411713 <6>[ 4.636107] hub 1-1:1.0: USB hub found
10493 00:26:20.414783 <6>[ 4.640505] hub 1-1:1.0: 4 ports detected
10494 00:26:20.522923 <6>[ 4.744673] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10495 00:26:20.549204 <6>[ 4.774157] hub 2-1:1.0: USB hub found
10496 00:26:20.552572 <6>[ 4.778705] hub 2-1:1.0: 3 ports detected
10497 00:26:20.563744 <6>[ 4.788464] hub 2-1:1.0: USB hub found
10498 00:26:20.567034 <6>[ 4.792787] hub 2-1:1.0: 3 ports detected
10499 00:26:20.734572 <6>[ 4.956453] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10500 00:26:20.866101 <6>[ 5.091306] hub 1-1.4:1.0: USB hub found
10501 00:26:20.869164 <6>[ 5.095799] hub 1-1.4:1.0: 2 ports detected
10502 00:26:20.880450 <6>[ 5.105801] hub 1-1.4:1.0: USB hub found
10503 00:26:20.883805 <6>[ 5.110355] hub 1-1.4:1.0: 2 ports detected
10504 00:26:20.946830 <6>[ 5.168459] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10505 00:26:21.055084 <6>[ 5.276752] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10506 00:26:21.087157 <4>[ 5.308573] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10507 00:26:21.096972 <4>[ 5.317673] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10508 00:26:21.136759 <6>[ 5.361389] r8152 2-1.3:1.0 eth0: v1.12.13
10509 00:26:21.182475 <6>[ 5.404397] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10510 00:26:21.378509 <6>[ 5.600397] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10511 00:26:22.742356 <6>[ 6.967158] r8152 2-1.3:1.0 eth0: carrier on
10512 00:26:25.122682 <5>[ 6.988184] Sending DHCP requests .., OK
10513 00:26:25.129092 <6>[ 9.352516] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.16
10514 00:26:25.132523 <6>[ 9.360816] IP-Config: Complete:
10515 00:26:25.145920 <6>[ 9.364309] device=eth0, hwaddr=00:e0:4c:68:03:bd, ipaddr=192.168.201.16, mask=255.255.255.0, gw=192.168.201.1
10516 00:26:25.152949 <6>[ 9.375018] host=mt8192-asurada-spherion-r0-cbg-4, domain=lava-rack, nis-domain=(none)
10517 00:26:25.158969 <6>[ 9.383635] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10518 00:26:25.165482 <6>[ 9.383645] nameserver0=192.168.201.1
10519 00:26:25.168808 <6>[ 9.395804] clk: Disabling unused clocks
10520 00:26:25.172247 <6>[ 9.401284] ALSA device list:
10521 00:26:25.178512 <6>[ 9.404571] No soundcards found.
10522 00:26:25.186340 <6>[ 9.411848] Freeing unused kernel memory: 8512K
10523 00:26:25.189181 <6>[ 9.416850] Run /init as init process
10524 00:26:25.218970 <6>[ 9.445092] NET: Registered PF_INET6 protocol family
10525 00:26:25.226011 <6>[ 9.451787] Segment Routing with IPv6
10526 00:26:25.229440 <6>[ 9.455774] In-situ OAM (IOAM) with IPv6
10527 00:26:25.270438 <30>[ 9.469651] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10528 00:26:25.276807 <30>[ 9.502722] systemd[1]: Detected architecture arm64.
10529 00:26:25.276884
10530 00:26:25.283526 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10531 00:26:25.283603
10532 00:26:25.298439 <30>[ 9.524374] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10533 00:26:25.429055 <30>[ 9.651959] systemd[1]: Queued start job for default target graphical.target.
10534 00:26:25.494807 <30>[ 9.717439] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10535 00:26:25.501273 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10536 00:26:25.522111 <30>[ 9.744869] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10537 00:26:25.532136 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10538 00:26:25.555264 <30>[ 9.777645] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10539 00:26:25.564979 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10540 00:26:25.583158 <30>[ 9.805675] systemd[1]: Created slice user.slice - User and Session Slice.
10541 00:26:25.590197 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10542 00:26:25.613834 <30>[ 9.832908] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10543 00:26:25.623669 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10544 00:26:25.641089 <30>[ 9.860434] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10545 00:26:25.647588 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10546 00:26:25.676272 <30>[ 9.888912] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10547 00:26:25.686415 <30>[ 9.908803] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10548 00:26:25.692817 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10549 00:26:25.710430 <30>[ 9.932764] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10550 00:26:25.719867 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10551 00:26:25.738252 <30>[ 9.960869] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10552 00:26:25.748374 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10553 00:26:25.763139 <30>[ 9.988871] systemd[1]: Reached target paths.target - Path Units.
10554 00:26:25.773472 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10555 00:26:25.790185 <30>[ 10.012832] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10556 00:26:25.796719 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10557 00:26:25.810283 <30>[ 10.036354] systemd[1]: Reached target slices.target - Slice Units.
10558 00:26:25.821015 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10559 00:26:25.834517 <30>[ 10.060385] systemd[1]: Reached target swap.target - Swaps.
10560 00:26:25.840980 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10561 00:26:25.862486 <30>[ 10.084859] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10562 00:26:25.872207 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10563 00:26:25.891096 <30>[ 10.113319] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10564 00:26:25.900336 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10565 00:26:25.920300 <30>[ 10.142398] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10566 00:26:25.929493 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10567 00:26:25.946376 <30>[ 10.168977] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10568 00:26:25.956321 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10569 00:26:25.974436 <30>[ 10.196949] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10570 00:26:25.981554 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10571 00:26:25.998705 <30>[ 10.221018] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10572 00:26:26.008613 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10573 00:26:26.026322 <30>[ 10.248823] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10574 00:26:26.036141 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10575 00:26:26.078390 <30>[ 10.300649] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10576 00:26:26.084905 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10577 00:26:26.106037 <30>[ 10.328238] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10578 00:26:26.112456 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10579 00:26:26.133132 <30>[ 10.355442] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10580 00:26:26.139695 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10581 00:26:26.164928 <30>[ 10.380735] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10582 00:26:26.214963 <30>[ 10.437084] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10583 00:26:26.224812 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10584 00:26:26.247553 <30>[ 10.469541] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10585 00:26:26.253859 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10586 00:26:26.278680 <30>[ 10.501534] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10587 00:26:26.288998 Startin<6>[ 10.510868] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10588 00:26:26.295480 g [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10589 00:26:26.318810 <30>[ 10.541356] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10590 00:26:26.325727 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10591 00:26:26.350943 <30>[ 10.573392] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10592 00:26:26.360639 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10593 00:26:26.410584 <30>[ 10.632819] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10594 00:26:26.417216 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10595 00:26:26.442925 <30>[ 10.664813] systemd[1]: Starting systemd-journald.service - Journal Service...
10596 00:26:26.448956 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10597 00:26:26.468756 <30>[ 10.691036] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10598 00:26:26.475231 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10599 00:26:26.502106 <30>[ 10.720424] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10600 00:26:26.508183 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10601 00:26:26.530555 <30>[ 10.752862] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10602 00:26:26.540599 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10603 00:26:26.562012 <30>[ 10.783969] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10604 00:26:26.568493 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10605 00:26:26.594652 <30>[ 10.816562] systemd[1]: Started systemd-journald.service - Journal Service.
10606 00:26:26.600723 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10607 00:26:26.623320 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10608 00:26:26.638769 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10609 00:26:26.659003 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10610 00:26:26.679868 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10611 00:26:26.699966 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10612 00:26:26.720022 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10613 00:26:26.744725 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10614 00:26:26.763436 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10615 00:26:26.785468 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10616 00:26:26.804554 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10617 00:26:26.828122 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10618 00:26:26.848866 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10619 00:26:26.855317 See 'systemctl status systemd-remount-fs.service' for details.
10620 00:26:26.864942 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10621 00:26:26.885463 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10622 00:26:26.934815 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10623 00:26:26.959574 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10624 00:26:26.977613 <46>[ 11.199692] systemd-journald[193]: Received client request to flush runtime journal.
10625 00:26:27.002881 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10626 00:26:27.027626 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10627 00:26:27.050656 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10628 00:26:27.075956 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10629 00:26:27.100379 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10630 00:26:27.119463 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10631 00:26:27.139660 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10632 00:26:27.159656 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10633 00:26:27.219138 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10634 00:26:27.244892 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10635 00:26:27.262960 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10636 00:26:27.282430 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10637 00:26:27.327341 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10638 00:26:27.355671 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10639 00:26:27.381382 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10640 00:26:27.435214 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10641 00:26:27.469053 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10642 00:26:27.489370 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10643 00:26:27.537523 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10644 00:26:27.560193 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10645 00:26:27.580868 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10646 00:26:27.682669 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10647 00:26:27.701889 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10648 00:26:27.719156 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10649 00:26:27.739221 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10650 00:26:27.757960 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10651 00:26:27.775302 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10652 00:26:27.781518 <6>[ 12.005453] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10653 00:26:27.791694 <6>[ 12.014114] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10654 00:26:27.798059 <6>[ 12.015856] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10655 00:26:27.808433 <6>[ 12.022939] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10656 00:26:27.818259 <6>[ 12.035984] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10657 00:26:27.825013 <6>[ 12.047868] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10658 00:26:27.834815 [[0;32m OK [<4>[ 12.055993] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10659 00:26:27.844922 0m] Reached targ<6>[ 12.066924] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10660 00:26:27.854766 et [0;1;39msock<3>[ 12.068578] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10661 00:26:27.861133 <6>[ 12.075684] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10662 00:26:27.871153 ets.target[0m -<6>[ 12.085532] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10663 00:26:27.874730 Socket Units.
10664 00:26:27.881747 <6>[ 12.090433] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10665 00:26:27.882166
10666 00:26:27.887783 <3>[ 12.093107] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10667 00:26:27.897773 <3>[ 12.093113] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10668 00:26:27.904427 <6>[ 12.102417] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10669 00:26:27.911036 <6>[ 12.104308] remoteproc remoteproc0: scp is available
10670 00:26:27.914108 <6>[ 12.104401] remoteproc remoteproc0: powering up scp
10671 00:26:27.924179 <6>[ 12.104406] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10672 00:26:27.927319 <6>[ 12.104424] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10673 00:26:27.937694 <3>[ 12.124826] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10674 00:26:27.944154 <6>[ 12.127557] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10675 00:26:27.954069 <3>[ 12.135251] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10676 00:26:27.960790 <6>[ 12.140425] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10677 00:26:27.970843 <3>[ 12.145545] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10678 00:26:27.977879 <3>[ 12.145557] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10679 00:26:27.984852 <6>[ 12.146617] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10680 00:26:27.994702 <4>[ 12.150760] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10681 00:26:27.998178 <6>[ 12.161113] mc: Linux media interface: v0.10
10682 00:26:28.004735 <4>[ 12.163326] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10683 00:26:28.011904 <3>[ 12.167699] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10684 00:26:28.021875 <3>[ 12.170856] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10685 00:26:28.029340 <6>[ 12.177590] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10686 00:26:28.036069 <3>[ 12.183832] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10687 00:26:28.045744 <4>[ 12.191536] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10688 00:26:28.048996 <4>[ 12.191536] Fallback method does not support PEC.
10689 00:26:28.055238 <6>[ 12.193798] pci_bus 0000:00: root bus resource [bus 00-ff]
10690 00:26:28.062109 <3>[ 12.200896] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10691 00:26:28.072310 <3>[ 12.200904] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10692 00:26:28.078873 <3>[ 12.201038] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10693 00:26:28.088969 <3>[ 12.208353] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10694 00:26:28.095708 <6>[ 12.209007] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10695 00:26:28.106451 <3>[ 12.216650] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10696 00:26:28.112515 <6>[ 12.223946] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10697 00:26:28.122536 <6>[ 12.225534] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10698 00:26:28.132716 <6>[ 12.225976] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10699 00:26:28.140141 <3>[ 12.228463] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10700 00:26:28.147008 <6>[ 12.229731] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10701 00:26:28.157185 <6>[ 12.229762] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10702 00:26:28.164275 <6>[ 12.229771] remoteproc remoteproc0: remote processor scp is now up
10703 00:26:28.171030 <6>[ 12.235790] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10704 00:26:28.177424 <3>[ 12.241501] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10705 00:26:28.184646 <3>[ 12.243310] power_supply sbs-5-000b: driver failed to report `temp' property: -6
10706 00:26:28.194453 <3>[ 12.243835] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10707 00:26:28.201900 <6>[ 12.251920] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10708 00:26:28.207950 <3>[ 12.258769] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10709 00:26:28.218337 <3>[ 12.263680] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10710 00:26:28.227994 <6>[ 12.266337] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10711 00:26:28.231383 <6>[ 12.266903] pci 0000:00:00.0: supports D1 D2
10712 00:26:28.241426 <3>[ 12.280507] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10713 00:26:28.248650 <6>[ 12.286211] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10714 00:26:28.255088 <6>[ 12.287257] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10715 00:26:28.262079 <6>[ 12.287574] videodev: Linux video capture interface: v2.00
10716 00:26:28.269495 <6>[ 12.288296] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10717 00:26:28.275703 <6>[ 12.295267] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10718 00:26:28.282434 <6>[ 12.303255] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10719 00:26:28.285974 <6>[ 12.311484] Bluetooth: Core ver 2.22
10720 00:26:28.296496 <6>[ 12.319462] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10721 00:26:28.299701 <6>[ 12.326650] NET: Registered PF_BLUETOOTH protocol family
10722 00:26:28.306626 <6>[ 12.334653] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10723 00:26:28.313692 <6>[ 12.344538] Bluetooth: HCI device and connection manager initialized
10724 00:26:28.323816 <6>[ 12.354623] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10725 00:26:28.330662 <6>[ 12.356065] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10726 00:26:28.339853 <6>[ 12.357521] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10727 00:26:28.346609 <6>[ 12.357627] usbcore: registered new interface driver uvcvideo
10728 00:26:28.356743 <3>[ 12.363025] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10729 00:26:28.360381 <6>[ 12.363655] Bluetooth: HCI socket layer initialized
10730 00:26:28.369520 <3>[ 12.363788] power_supply sbs-5-000b: driver failed to report `current_now' property: -6
10731 00:26:28.372940 <6>[ 12.371836] pci 0000:01:00.0: supports D1 D2
10732 00:26:28.383301 <3>[ 12.374777] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10733 00:26:28.389657 <6>[ 12.378760] Bluetooth: L2CAP socket layer initialized
10734 00:26:28.396214 <6>[ 12.387267] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10735 00:26:28.399425 <6>[ 12.393700] Bluetooth: SCO socket layer initialized
10736 00:26:28.409245 <3>[ 12.394545] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10737 00:26:28.415801 <6>[ 12.400614] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10738 00:26:28.425774 <3>[ 12.417566] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10739 00:26:28.432640 <6>[ 12.424798] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10740 00:26:28.438759 <3>[ 12.451600] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10741 00:26:28.448693 <6>[ 12.458256] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10742 00:26:28.452345 <6>[ 12.458927] usbcore: registered new interface driver btusb
10743 00:26:28.465363 <4>[ 12.459876] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10744 00:26:28.468765 <3>[ 12.459889] Bluetooth: hci0: Failed to load firmware file (-2)
10745 00:26:28.475327 <3>[ 12.459894] Bluetooth: hci0: Failed to set up firmware (-2)
10746 00:26:28.485771 <4>[ 12.459900] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10747 00:26:28.495256 <6>[ 12.717266] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10748 00:26:28.501808 <6>[ 12.717276] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10749 00:26:28.511737 <6>[ 12.717289] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10750 00:26:28.518638 <6>[ 12.717301] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10751 00:26:28.524854 <6>[ 12.717313] pci 0000:00:00.0: PCI bridge to [bus 01]
10752 00:26:28.531706 <6>[ 12.717317] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10753 00:26:28.538067 <6>[ 12.717476] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10754 00:26:28.544659 [[0;32m OK [<6>[ 12.769372] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10755 00:26:28.551533 0m] Reached targ<6>[ 12.776742] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10756 00:26:28.557648 et [0;1;39mbasic.target[0m - Basic System.
10757 00:26:28.568950 <5>[ 12.791389] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10758 00:26:28.594610 <5>[ 12.817345] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10759 00:26:28.601198 <5>[ 12.824360] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10760 00:26:28.611768 <4>[ 12.832785] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10761 00:26:28.614266 <6>[ 12.841663] cfg80211: failed to load regulatory.db
10762 00:26:28.624675 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10763 00:26:28.649690 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10764 00:26:28.664161 <6>[ 12.886684] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10765 00:26:28.670803 <6>[ 12.894307] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10766 00:26:28.690657 <46>[ 12.896919] systemd-journald[193]: Data hash table of /var/log/journal/c3f909ee3e324895ab90ff2613af9260/system.journal has a fill level at 75.1 (1537 of 2047 items, 524288 file size, 341 bytes per hash table item), suggesting rotation.
10767 00:26:28.697127 <6>[ 12.919614] mt7921e 0000:01:00.0: ASIC revision: 79610010
10768 00:26:28.710412 <46>[ 12.921856] systemd-journald[193]: /var/log/journal/c3f909ee3e324895ab90ff2613af9260/system.journal: Journal header limits reached or header out-of-date, rotating.
10769 00:26:28.720064 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
10770 00:26:28.739240 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
10771 00:26:28.771622 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
10772 00:26:28.797085 <6>[ 13.019428] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10773 00:26:28.800233 <6>[ 13.019428]
10774 00:26:28.820592 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
10775 00:26:28.846528 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10776 00:26:28.868960 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10777 00:26:28.889507 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10778 00:26:28.942438 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
10779 00:26:29.007339 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
10780 00:26:29.027046 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
10781 00:26:29.042732 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
10782 00:26:29.069407 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m<6>[ 13.289943] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10783 00:26:29.072639 - Graphical Interface.
10784 00:26:29.116933 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10785 00:26:29.141426 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
10786 00:26:29.166978 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10787 00:26:29.239009 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10788 00:26:29.259616 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10789 00:26:29.284768 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
10790 00:26:29.318718
10791 00:26:29.321699 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
10792 00:26:29.321793
10793 00:26:29.325061 debian-bookworm-arm64 login: root (automatic login)
10794 00:26:29.325137
10795 00:26:29.338880 Linux debian-bookworm-arm64 6.1.94-cip23 #1 SMP PREEMPT Fri Jun 21 00:04:56 UTC 2024 aarch64
10796 00:26:29.339314
10797 00:26:29.345641 The programs included with the Debian GNU/Linux system are free software;
10798 00:26:29.352348 the exact distribution terms for each program are described in the
10799 00:26:29.355583 individual files in /usr/share/doc/*/copyright.
10800 00:26:29.356037
10801 00:26:29.362082 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10802 00:26:29.365137 permitted by applicable law.
10803 00:26:29.366975 Matched prompt #10: / #
10805 00:26:29.368800 Setting prompt string to ['/ #']
10806 00:26:29.369483 end: 2.2.5.1 login-action (duration 00:00:14) [common]
10808 00:26:29.369936 end: 2.2.5 auto-login-action (duration 00:00:14) [common]
10809 00:26:29.370054 start: 2.2.6 expect-shell-connection (timeout 00:03:24) [common]
10810 00:26:29.370146 Setting prompt string to ['/ #']
10811 00:26:29.370294 Forcing a shell prompt, looking for ['/ #']
10813 00:26:29.420501 / #
10814 00:26:29.420811 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10815 00:26:29.420979 Waiting using forced prompt support (timeout 00:02:30)
10816 00:26:29.425683
10817 00:26:29.426049 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10818 00:26:29.426232 start: 2.2.7 export-device-env (timeout 00:03:24) [common]
10819 00:26:29.426420 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10820 00:26:29.426576 end: 2.2 depthcharge-retry (duration 00:01:36) [common]
10821 00:26:29.426741 end: 2 depthcharge-action (duration 00:01:36) [common]
10822 00:26:29.426899 start: 3 lava-test-retry (timeout 00:08:00) [common]
10823 00:26:29.427077 start: 3.1 lava-test-shell (timeout 00:08:00) [common]
10824 00:26:29.427208 Using namespace: common
10826 00:26:29.527718 / # #
10827 00:26:29.527929 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10828 00:26:29.532809 #
10829 00:26:29.533097 Using /lava-14479191
10831 00:26:29.633778 / # export SHELL=/bin/sh
10832 00:26:29.640194 export SHELL=/bin/sh
10834 00:26:29.741720 / # . /lava-14479191/environment
10835 00:26:29.748095 . /lava-14479191/environment
10837 00:26:29.849671 / # /lava-14479191/bin/lava-test-runner /lava-14479191/0
10838 00:26:29.850369 Test shell timeout: 10s (minimum of the action and connection timeout)
10839 00:26:29.856053 /lava-14479191/bin/lava-test-runner /lava-14479191/0
10840 00:26:29.881324 + export TESTRUN<8>[ 14.104857] <LAVA_SIGNAL_STARTRUN 0_igt-gpu-panfrost 14479191_1.5.2.3.1>
10841 00:26:29.882402 Received signal: <STARTRUN> 0_igt-gpu-panfrost 14479191_1.5.2.3.1
10842 00:26:29.882996 Starting test lava.0_igt-gpu-panfrost (14479191_1.5.2.3.1)
10843 00:26:29.883728 Skipping test definition patterns.
10844 00:26:29.884562 _ID=0_igt-gpu-panfrost
10845 00:26:29.887387 + cd /lava-14479191/0/tests/0_igt-gpu-panfrost
10846 00:26:29.888037 + cat uuid
10847 00:26:29.890392 + UUID=14479191_1.5.2.3.1
10848 00:26:29.890488 + set +x
10849 00:26:29.907266 + IGT_FORCE_DRIVER=panfrost /usr/bin/igt-parser.sh panfrost_gem_new panfrost_get_param panfrost_prime p<8>[ 14.131487] <LAVA_SIGNAL_TESTSET START panfrost_gem_new>
10850 00:26:29.907798 anfrost_submit
10851 00:26:29.908531 Received signal: <TESTSET> START panfrost_gem_new
10852 00:26:29.908937 Starting test_set panfrost_gem_new
10853 00:26:29.933515 <6>[ 14.159670] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10854 00:26:29.940546 <14>[ 14.166000] [IGT] panfrost_gem_new: executing
10855 00:26:29.950618 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1<14>[ 14.174160] [IGT] panfrost_gem_new: exiting, ret=77
10856 00:26:29.951079 .94-cip23 aarch64)
10857 00:26:29.957345 Using IGT_SRANDOM=1718929590 for randomisation
10858 00:26:29.963307 Test requirement not met in <8>[ 14.188077] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-4096 RESULT=skip>
10859 00:26:29.964005 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-4096 RESULT=skip
10861 00:26:29.969860 function drm_open_driver, file ../lib/drmtest.c:694:
10862 00:26:29.970329 Test requirement: !(fd<0)
10863 00:26:29.976514 No known gpu found for chipset flags 0x32 (panfrost)
10864 00:26:29.980033 Last errno: 2, No such file or directory
10865 00:26:29.983032 [1mSubtest gem-new-4096: SKIP (0.000s)[0m
10866 00:26:29.995343 <14>[ 14.221377] [IGT] panfrost_gem_new: executing
10867 00:26:30.005775 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1<14>[ 14.229589] [IGT] panfrost_gem_new: exiting, ret=77
10868 00:26:30.006324 .94-cip23 aarch64)
10869 00:26:30.012019 Using IGT_SRANDOM=1718929590 for randomisation
10870 00:26:30.018377 Test require<8>[ 14.241714] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-0 RESULT=skip>
10871 00:26:30.019183 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-0 RESULT=skip
10873 00:26:30.025146 ment not met in function drm_open_driver, file ../lib/drmtest.c:694:
10874 00:26:30.028386 Test requirement: !(fd<0)
10875 00:26:30.031938 No known gpu found for chipset flags 0x32 (panfrost)
10876 00:26:30.038466 Last errn<14>[ 14.262366] [IGT] panfrost_gem_new: executing
10877 00:26:30.041679 o: 2, No such file or directory
10878 00:26:30.044915 <14>[ 14.270005] [IGT] panfrost_gem_new: exiting, ret=77
10879 00:26:30.045426
10880 00:26:30.048454 [1mSubtest gem-new-0: SKIP (0.000s)[0m
10881 00:26:30.058458 IGT-Version: 1.28-ga44ebfe (aarch64) <8>[ 14.282751] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-zeroed RESULT=skip>
10882 00:26:30.059196 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-zeroed RESULT=skip
10884 00:26:30.061396 (Linux: 6.1.94-cip23 aarch64)
10885 00:26:30.064931 U<8>[ 14.291689] <LAVA_SIGNAL_TESTSET STOP>
10886 00:26:30.065631 Received signal: <TESTSET> STOP
10887 00:26:30.066032 Closing test_set panfrost_gem_new
10888 00:26:30.071405 sing IGT_SRANDOM=1718929590 for randomisation
10889 00:26:30.077764 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
10890 00:26:30.081180 Test requirement: !(fd<0)
10891 00:26:30.084170 No known gpu found for chipset flags 0x32 (panfrost)
10892 00:26:30.087796 Last errno: 2, No such file or directory
10893 00:26:30.090996 [1mSubtest gem-new-zeroed: SKIP (0.000s)[0m
10894 00:26:30.102705 <8>[ 14.328933] <LAVA_SIGNAL_TESTSET START panfrost_get_param>
10895 00:26:30.103366 Received signal: <TESTSET> START panfrost_get_param
10896 00:26:30.103788 Starting test_set panfrost_get_param
10897 00:26:30.137287 <14>[ 14.363458] [IGT] panfrost_get_param: executing
10898 00:26:30.147324 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1<14>[ 14.372119] [IGT] panfrost_get_param: exiting, ret=77
10899 00:26:30.147719 .94-cip23 aarch64)
10900 00:26:30.153888 Using IGT_SRANDOM=1718929590 for randomisation
10901 00:26:30.164007 Test requirement not met in function drm_ope<8>[ 14.387543] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=base-params RESULT=skip>
10902 00:26:30.164765 Received signal: <TESTCASE> TEST_CASE_ID=base-params RESULT=skip
10904 00:26:30.167253 n_driver, file ../lib/drmtest.c:694:
10905 00:26:30.170798 Test requirement: !(fd<0)
10906 00:26:30.174306 No known gpu found for chipset flags 0x32 (panfrost)
10907 00:26:30.176976 Last errno: 2, No such file or directory
10908 00:26:30.183712 <14>[ 14.407953] [IGT] panfrost_get_param: executing
10909 00:26:30.184216
10910 00:26:30.190779 [1mSubtest base-params: SKIP (<14>[ 14.415477] [IGT] panfrost_get_param: exiting, ret=77
10911 00:26:30.193950 0.000s)[0m
10912 00:26:30.203994 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.94<8>[ 14.427394] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-param RESULT=skip>
10913 00:26:30.204507 -cip23 aarch64)
10914 00:26:30.205100 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-param RESULT=skip
10916 00:26:30.210689 Using IGT_SRANDOM=1718929590 for randomisation
10917 00:26:30.216799 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
10918 00:26:30.220093 Test requirement: !(fd<0)
10919 00:26:30.223509 No known gpu found for chipset flags 0x32 (panfrost)
10920 00:26:30.226769 Last errno: 2, No such file or directory
10921 00:26:30.233396 [1mSubtest get-ba<14>[ 14.459266] [IGT] panfrost_get_param: executing
10922 00:26:30.236694 d-param: SKIP (0.000s)[0m
10923 00:26:30.243229 IGT-Version: 1.28-ga<14>[ 14.467891] [IGT] panfrost_get_param: exiting, ret=77
10924 00:26:30.246573 44ebfe (aarch64) (Linux: 6.1.94-cip23 aarch64)
10925 00:26:30.256284 Using IGT_SRANDOM=1718929590 for<8>[ 14.479738] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-padding RESULT=skip>
10926 00:26:30.256962 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-padding RESULT=skip
10928 00:26:30.259857 randomisation
10929 00:26:30.263920 Test requirement<8>[ 14.490352] <LAVA_SIGNAL_TESTSET STOP>
10930 00:26:30.264676 Received signal: <TESTSET> STOP
10931 00:26:30.265027 Closing test_set panfrost_get_param
10932 00:26:30.270078 not met in function drm_open_driver, file ../lib/drmtest.c:694:
10933 00:26:30.272983 Test requirement: !(fd<0)
10934 00:26:30.276326 No known gpu found for chipset flags 0x32 (panfrost)
10935 00:26:30.286388 Last errno: 2, No such file o<8>[ 14.510248] <LAVA_SIGNAL_TESTSET START panfrost_prime>
10936 00:26:30.286827 r directory
10937 00:26:30.287413 Received signal: <TESTSET> START panfrost_prime
10938 00:26:30.287759 Starting test_set panfrost_prime
10939 00:26:30.289653 [1mSubtest get-bad-padding: SKIP (0.000s)[0m
10940 00:26:30.301788 <14>[ 14.527706] [IGT] panfrost_prime: executing
10941 00:26:30.308822 IGT-Version: 1.28-ga44ebfe (aarc<14>[ 14.534008] [IGT] panfrost_prime: exiting, ret=77
10942 00:26:30.311465 h64) (Linux: 6.1.94-cip23 aarch64)
10943 00:26:30.324489 Using IGT_SRANDOM=1718929590 for randomisati<8>[ 14.546155] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-prime-import RESULT=skip>
10944 00:26:30.324929 on
10945 00:26:30.325514 Received signal: <TESTCASE> TEST_CASE_ID=gem-prime-import RESULT=skip
10947 00:26:30.331394 Test requirement not met in <8>[ 14.556140] <LAVA_SIGNAL_TESTSET STOP>
10948 00:26:30.332156 Received signal: <TESTSET> STOP
10949 00:26:30.332516 Closing test_set panfrost_prime
10950 00:26:30.334525 function drm_open_driver, file ../lib/drmtest.c:694:
10951 00:26:30.337582 Test requirement: !(fd<0)
10952 00:26:30.341048 No known gpu found for chipset flags 0x32 (panfrost)
10953 00:26:30.344532 Last errno: 2, No such file or directory
10954 00:26:30.351029 [1mSubtest gem-prime-import: SKIP (0.000s)[0m
10955 00:26:30.362169 <8>[ 14.588201] <LAVA_SIGNAL_TESTSET START panfrost_submit>
10956 00:26:30.362970 Received signal: <TESTSET> START panfrost_submit
10957 00:26:30.363330 Starting test_set panfrost_submit
10958 00:26:30.382846 <14>[ 14.608480] [IGT] panfrost_submit: executing
10959 00:26:30.389364 IGT-Version: 1.28-ga44ebfe (aarc<14>[ 14.614875] [IGT] panfrost_submit: exiting, ret=77
10960 00:26:30.392766 h64) (Linux: 6.1.94-cip23 aarch64)
10961 00:26:30.402626 Using IGT_SR<8>[ 14.625272] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit RESULT=skip>
10962 00:26:30.403392 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit RESULT=skip
10964 00:26:30.405814 ANDOM=1718929590 for randomisation
10965 00:26:30.412611 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
10966 00:26:30.413124 Test requirement: !(fd<0)
10967 00:26:30.419051 No known gpu found for chipset flags 0x32 (panfrost)
10968 00:26:30.422486 Last errno: 2, No such file or directory
10969 00:26:30.425787 [1mSubtest pan-submit: SKIP (0.000s)[0m
10970 00:26:30.428767 <14>[ 14.655908] [IGT] panfrost_submit: executing
10971 00:26:30.439344 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1<14>[ 14.664727] [IGT] panfrost_submit: exiting, ret=77
10972 00:26:30.442318 .94-cip23 aarch64)
10973 00:26:30.445287 Using IGT_SRANDOM=1718929590 for randomisation
10974 00:26:30.455261 Test requirement not met in <8>[ 14.677888] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip>
10975 00:26:30.455950 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip
10977 00:26:30.461792 function drm_open_driver, file ../lib/drmtest.c:694:
10978 00:26:30.462319 Test requirement: !(fd<0)
10979 00:26:30.468866 No known gpu found for chipset flags 0x32 (panfrost)
10980 00:26:30.475200 Last errno: 2, No such fi<14>[ 14.699993] [IGT] panfrost_submit: executing
10981 00:26:30.475633 le or directory
10982 00:26:30.481666 [1mSubtest pan<14>[ 14.707392] [IGT] panfrost_submit: exiting, ret=77
10983 00:26:30.484806 -submit-error-no-jc: SKIP (0.000s)[0m
10984 00:26:30.499036 IGT-Version: 1.28-ga44ebfe (aarch64) (Li<8>[ 14.719749] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip>
10985 00:26:30.499819 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip
10987 00:26:30.501706 nux: 6.1.94-cip23 aarch64)
10988 00:26:30.505144 Using IGT_SRANDOM=1718929590 for randomisation
10989 00:26:30.511705 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
10990 00:26:30.518314 Test requirement: <14>[ 14.743080] [IGT] panfrost_submit: executing
10991 00:26:30.518752 !(fd<0)
10992 00:26:30.524678 No known gpu found for <14>[ 14.750759] [IGT] panfrost_submit: exiting, ret=77
10993 00:26:30.527974 chipset flags 0x32 (panfrost)
10994 00:26:30.541210 Last errno: 2, No such file or di<8>[ 14.761910] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip>
10995 00:26:30.541709 rectory
10996 00:26:30.542331 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip
10998 00:26:30.544452 [1mSubtest pan-submit-error-bad-in-syncs: SKIP (0.000s)[0m
10999 00:26:30.551274 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.94-cip23 aarch64)
11000 00:26:30.557585 Using<14>[ 14.783225] [IGT] panfrost_submit: executing
11001 00:26:30.564684 IGT_SRANDOM=1718929590 for rand<14>[ 14.789853] [IGT] panfrost_submit: exiting, ret=77
11002 00:26:30.567507 omisation
11003 00:26:30.581000 Test requirement not met in function drm_open_driver, file ../lib/drm<8>[ 14.801882] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip>
11004 00:26:30.581586 test.c:694:
11005 00:26:30.582332 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip
11007 00:26:30.584092 Test requirement: !(fd<0)
11008 00:26:30.590671 No known gpu found for chipset flags 0x32 (panfrost)
11009 00:26:30.593863 Last errno: 2, No such file or directory
11010 00:26:30.600849 [1mSubtest pan-submit-e<14>[ 14.825089] [IGT] panfrost_submit: executing
11011 00:26:30.607590 rror-bad-bo-handles: SKIP (0.000<14>[ 14.832783] [IGT] panfrost_submit: exiting, ret=77
11012 00:26:30.608061 s)[0m
11013 00:26:30.613858 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.94-cip23 aarch64)
11014 00:26:30.623652 Usin<8>[ 14.844354] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip>
11015 00:26:30.624387 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip
11017 00:26:30.627014 g IGT_SRANDOM=1718929590 for randomisation
11018 00:26:30.633863 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11019 00:26:30.640471 Test requirement: <14>[ 14.866524] [IGT] panfrost_submit: executing
11020 00:26:30.640944 !(fd<0)
11021 00:26:30.647053 No known gpu found for <14>[ 14.873188] [IGT] panfrost_submit: exiting, ret=77
11022 00:26:30.650817 chipset flags 0x32 (panfrost)
11023 00:26:30.660724 Last errno: 2, No such file or di<8>[ 14.884585] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-reset RESULT=skip>
11024 00:26:30.661240 rectory
11025 00:26:30.661831 Received signal: <TESTCASE> TEST_CASE_ID=pan-reset RESULT=skip
11027 00:26:30.667346 [1mSubtest pan-submit-error-bad-requirements: SKIP (0.000s)[0m
11028 00:26:30.673381 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.94-cip23 aarch64)
11029 00:26:30.680185 Using IGT_SRANDOM<14>[ 14.904660] [IGT] panfrost_submit: executing
11030 00:26:30.680823 =1718929590 for randomisation
11031 00:26:30.686696 T<14>[ 14.911979] [IGT] panfrost_submit: exiting, ret=77
11032 00:26:30.693533 est requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11033 00:26:30.700715 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-and-close RESULT=skip
11035 00:26:30.703037 <8>[ 14.923620] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-and-close RESULT=skip>
11036 00:26:30.703490
11037 00:26:30.703824 Test requirement: !(fd<0)
11038 00:26:30.709688 No known gpu found for chipset flags 0x32 (panfrost)
11039 00:26:30.712992 Last errno: 2, No such file or directory
11040 00:26:30.719663 [1mSubtest pan-submit-error-bad-out<14>[ 14.945982] [IGT] panfrost_submit: executing
11041 00:26:30.723225 -sync: SKIP (0.000s)[0m
11042 00:26:30.729469 IGT-Ve<14>[ 14.953172] [IGT] panfrost_submit: exiting, ret=77
11043 00:26:30.732726 rsion: 1.28-ga44ebfe (aarch64) (Linux: 6.1.94-cip23 aarch64)
11044 00:26:30.742893 Us<8>[ 14.964328] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip>
11045 00:26:30.743597 Received signal: <TESTCASE> TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip
11047 00:26:30.749618 ing IGT_SRANDOM=1718929590 for r<8>[ 14.974336] <LAVA_SIGNAL_TESTSET STOP>
11048 00:26:30.750053 andomisation
11049 00:26:30.750680 Received signal: <TESTSET> STOP
11050 00:26:30.751016 Closing test_set panfrost_submit
11051 00:26:30.756047 Te<8>[ 14.980288] <LAVA_SIGNAL_ENDRUN 0_igt-gpu-panfrost 14479191_1.5.2.3.1>
11052 00:26:30.756717 Received signal: <ENDRUN> 0_igt-gpu-panfrost 14479191_1.5.2.3.1
11053 00:26:30.757205 Ending use of test pattern.
11054 00:26:30.757561 Ending test lava.0_igt-gpu-panfrost (14479191_1.5.2.3.1), duration 0.87
11056 00:26:30.762873 st requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11057 00:26:30.765807 Test requirement: !(fd<0)
11058 00:26:30.769554 No known gpu found for chipset flags 0x32 (panfrost)
11059 00:26:30.775758 Last errno: 2, No such file or directory
11060 00:26:30.779216 [1mSubtest pan-reset: SKIP (0.000s)[0m
11061 00:26:30.782581 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.94-cip23 aarch64)
11062 00:26:30.789192 Using IGT_SRANDOM=1718929590 for randomisation
11063 00:26:30.795924 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11064 00:26:30.799446 Test requirement: !(fd<0)
11065 00:26:30.802241 No known gpu found for chipset flags 0x32 (panfrost)
11066 00:26:30.805275 Last errno: 2, No such file or directory
11067 00:26:30.808504 [1mSubtest pan-submit-and-close: SKIP (0.000s)[0m
11068 00:26:30.815510 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.94-cip23 aarch64)
11069 00:26:30.822082 Using IGT_SRANDOM=1718929590 for randomisation
11070 00:26:30.828575 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11071 00:26:30.829158 Test requirement: !(fd<0)
11072 00:26:30.835199 No known gpu found for chipset flags 0x32 (panfrost)
11073 00:26:30.838285 Last errno: 2, No such file or directory
11074 00:26:30.841910 [1mSubtest pan-unhandled-pagefault: SKIP (0.000s)[0m
11075 00:26:30.845464 + set +x
11076 00:26:30.846006 <LAVA_TEST_RUNNER EXIT>
11077 00:26:30.846726 ok: lava_test_shell seems to have completed
11078 00:26:30.849543 base-params:
result: skip
set: panfrost_get_param
gem-new-0:
result: skip
set: panfrost_gem_new
gem-new-4096:
result: skip
set: panfrost_gem_new
gem-new-zeroed:
result: skip
set: panfrost_gem_new
gem-prime-import:
result: skip
set: panfrost_prime
get-bad-padding:
result: skip
set: panfrost_get_param
get-bad-param:
result: skip
set: panfrost_get_param
pan-reset:
result: skip
set: panfrost_submit
pan-submit:
result: skip
set: panfrost_submit
pan-submit-and-close:
result: skip
set: panfrost_submit
pan-submit-error-bad-bo-handles:
result: skip
set: panfrost_submit
pan-submit-error-bad-in-syncs:
result: skip
set: panfrost_submit
pan-submit-error-bad-out-sync:
result: skip
set: panfrost_submit
pan-submit-error-bad-requirements:
result: skip
set: panfrost_submit
pan-submit-error-no-jc:
result: skip
set: panfrost_submit
pan-unhandled-pagefault:
result: skip
set: panfrost_submit
11079 00:26:30.850297 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11080 00:26:30.850900 end: 3 lava-test-retry (duration 00:00:01) [common]
11081 00:26:30.851486 start: 4 finalize (timeout 00:07:58) [common]
11082 00:26:30.852101 start: 4.1 power-off (timeout 00:00:30) [common]
11083 00:26:30.853382 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-4', '--port=1', '--command=off']
11084 00:26:32.987770 >> Command sent successfully.
11085 00:26:32.994549 Returned 0 in 2 seconds
11086 00:26:33.095318 end: 4.1 power-off (duration 00:00:02) [common]
11088 00:26:33.096722 start: 4.2 read-feedback (timeout 00:07:56) [common]
11089 00:26:33.097891 Listened to connection for namespace 'common' for up to 1s
11090 00:26:34.098432 Finalising connection for namespace 'common'
11091 00:26:34.098714 Disconnecting from shell: Finalise
11092 00:26:34.098899 / #
11093 00:26:34.199564 end: 4.2 read-feedback (duration 00:00:01) [common]
11094 00:26:34.200237 end: 4 finalize (duration 00:00:03) [common]
11095 00:26:34.200829 Cleaning after the job
11096 00:26:34.201381 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14479191/tftp-deploy-tqgh2cqp/ramdisk
11097 00:26:34.232531 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14479191/tftp-deploy-tqgh2cqp/kernel
11098 00:26:34.262716 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14479191/tftp-deploy-tqgh2cqp/dtb
11099 00:26:34.263053 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14479191/tftp-deploy-tqgh2cqp/modules
11100 00:26:34.269981 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14479191
11101 00:26:34.376150 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14479191
11102 00:26:34.376324 Job finished correctly