Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 24
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 22
1 00:21:19.266731 lava-dispatcher, installed at version: 2024.03
2 00:21:19.266975 start: 0 validate
3 00:21:19.267101 Start time: 2024-06-21 00:21:19.267093+00:00 (UTC)
4 00:21:19.267261 Using caching service: 'http://localhost/cache/?uri=%s'
5 00:21:19.267453 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 00:21:19.527747 Using caching service: 'http://localhost/cache/?uri=%s'
7 00:21:19.527993 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.94-cip23%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 00:21:35.530575 Using caching service: 'http://localhost/cache/?uri=%s'
9 00:21:35.530756 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.94-cip23%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 00:21:35.780414 Using caching service: 'http://localhost/cache/?uri=%s'
11 00:21:35.780569 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.94-cip23%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 00:21:40.029563 validate duration: 20.76
14 00:21:40.029810 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 00:21:40.029912 start: 1.1 download-retry (timeout 00:10:00) [common]
16 00:21:40.030007 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 00:21:40.030170 Not decompressing ramdisk as can be used compressed.
18 00:21:40.030282 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 00:21:40.030371 saving as /var/lib/lava/dispatcher/tmp/14479141/tftp-deploy-0vfhrgoz/ramdisk/rootfs.cpio.gz
20 00:21:40.030460 total size: 47897469 (45 MB)
21 00:21:40.287211 progress 0 % (0 MB)
22 00:21:40.299643 progress 5 % (2 MB)
23 00:21:40.314787 progress 10 % (4 MB)
24 00:21:40.333043 progress 15 % (6 MB)
25 00:21:40.350500 progress 20 % (9 MB)
26 00:21:40.363067 progress 25 % (11 MB)
27 00:21:40.375621 progress 30 % (13 MB)
28 00:21:40.388768 progress 35 % (16 MB)
29 00:21:40.403804 progress 40 % (18 MB)
30 00:21:40.419855 progress 45 % (20 MB)
31 00:21:40.434600 progress 50 % (22 MB)
32 00:21:40.446901 progress 55 % (25 MB)
33 00:21:40.460392 progress 60 % (27 MB)
34 00:21:40.473259 progress 65 % (29 MB)
35 00:21:40.486092 progress 70 % (32 MB)
36 00:21:40.498699 progress 75 % (34 MB)
37 00:21:40.511412 progress 80 % (36 MB)
38 00:21:40.523897 progress 85 % (38 MB)
39 00:21:40.536518 progress 90 % (41 MB)
40 00:21:40.548905 progress 95 % (43 MB)
41 00:21:40.561307 progress 100 % (45 MB)
42 00:21:40.561570 45 MB downloaded in 0.53 s (86.01 MB/s)
43 00:21:40.561774 end: 1.1.1 http-download (duration 00:00:01) [common]
45 00:21:40.562048 end: 1.1 download-retry (duration 00:00:01) [common]
46 00:21:40.562129 start: 1.2 download-retry (timeout 00:09:59) [common]
47 00:21:40.562205 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 00:21:40.562339 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.94-cip23/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 00:21:40.562432 saving as /var/lib/lava/dispatcher/tmp/14479141/tftp-deploy-0vfhrgoz/kernel/Image
50 00:21:40.562491 total size: 54813184 (52 MB)
51 00:21:40.562545 No compression specified
52 00:21:40.563656 progress 0 % (0 MB)
53 00:21:40.577555 progress 5 % (2 MB)
54 00:21:40.591518 progress 10 % (5 MB)
55 00:21:40.605764 progress 15 % (7 MB)
56 00:21:40.620405 progress 20 % (10 MB)
57 00:21:40.634878 progress 25 % (13 MB)
58 00:21:40.649212 progress 30 % (15 MB)
59 00:21:40.663673 progress 35 % (18 MB)
60 00:21:40.677994 progress 40 % (20 MB)
61 00:21:40.692492 progress 45 % (23 MB)
62 00:21:40.708392 progress 50 % (26 MB)
63 00:21:40.725595 progress 55 % (28 MB)
64 00:21:40.739373 progress 60 % (31 MB)
65 00:21:40.757200 progress 65 % (34 MB)
66 00:21:40.772780 progress 70 % (36 MB)
67 00:21:40.786730 progress 75 % (39 MB)
68 00:21:40.801515 progress 80 % (41 MB)
69 00:21:40.815597 progress 85 % (44 MB)
70 00:21:40.829666 progress 90 % (47 MB)
71 00:21:40.843503 progress 95 % (49 MB)
72 00:21:40.856963 progress 100 % (52 MB)
73 00:21:40.857213 52 MB downloaded in 0.29 s (177.37 MB/s)
74 00:21:40.857367 end: 1.2.1 http-download (duration 00:00:00) [common]
76 00:21:40.857576 end: 1.2 download-retry (duration 00:00:00) [common]
77 00:21:40.857658 start: 1.3 download-retry (timeout 00:09:59) [common]
78 00:21:40.857735 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 00:21:40.857869 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.94-cip23/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 00:21:40.857929 saving as /var/lib/lava/dispatcher/tmp/14479141/tftp-deploy-0vfhrgoz/dtb/mt8192-asurada-spherion-r0.dtb
81 00:21:40.857982 total size: 47258 (0 MB)
82 00:21:40.858036 No compression specified
83 00:21:40.859010 progress 69 % (0 MB)
84 00:21:40.859267 progress 100 % (0 MB)
85 00:21:40.859418 0 MB downloaded in 0.00 s (31.45 MB/s)
86 00:21:40.859532 end: 1.3.1 http-download (duration 00:00:00) [common]
88 00:21:40.859740 end: 1.3 download-retry (duration 00:00:00) [common]
89 00:21:40.859817 start: 1.4 download-retry (timeout 00:09:59) [common]
90 00:21:40.859892 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 00:21:40.860002 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.94-cip23/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 00:21:40.860063 saving as /var/lib/lava/dispatcher/tmp/14479141/tftp-deploy-0vfhrgoz/modules/modules.tar
93 00:21:40.860116 total size: 8618924 (8 MB)
94 00:21:40.860171 Using unxz to decompress xz
95 00:21:40.861426 progress 0 % (0 MB)
96 00:21:40.881091 progress 5 % (0 MB)
97 00:21:40.905063 progress 10 % (0 MB)
98 00:21:40.929823 progress 15 % (1 MB)
99 00:21:40.954035 progress 20 % (1 MB)
100 00:21:40.980016 progress 25 % (2 MB)
101 00:21:41.004931 progress 30 % (2 MB)
102 00:21:41.029887 progress 35 % (2 MB)
103 00:21:41.053953 progress 40 % (3 MB)
104 00:21:41.078279 progress 45 % (3 MB)
105 00:21:41.102484 progress 50 % (4 MB)
106 00:21:41.127087 progress 55 % (4 MB)
107 00:21:41.152099 progress 60 % (4 MB)
108 00:21:41.176503 progress 65 % (5 MB)
109 00:21:41.205413 progress 70 % (5 MB)
110 00:21:41.231359 progress 75 % (6 MB)
111 00:21:41.256551 progress 80 % (6 MB)
112 00:21:41.280738 progress 85 % (7 MB)
113 00:21:41.306724 progress 90 % (7 MB)
114 00:21:41.335110 progress 95 % (7 MB)
115 00:21:41.365330 progress 100 % (8 MB)
116 00:21:41.370115 8 MB downloaded in 0.51 s (16.12 MB/s)
117 00:21:41.370372 end: 1.4.1 http-download (duration 00:00:01) [common]
119 00:21:41.370761 end: 1.4 download-retry (duration 00:00:01) [common]
120 00:21:41.370897 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 00:21:41.371032 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 00:21:41.371148 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 00:21:41.371275 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 00:21:41.371518 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14479141/lava-overlay-r94b4_47
125 00:21:41.371699 makedir: /var/lib/lava/dispatcher/tmp/14479141/lava-overlay-r94b4_47/lava-14479141/bin
126 00:21:41.371844 makedir: /var/lib/lava/dispatcher/tmp/14479141/lava-overlay-r94b4_47/lava-14479141/tests
127 00:21:41.371994 makedir: /var/lib/lava/dispatcher/tmp/14479141/lava-overlay-r94b4_47/lava-14479141/results
128 00:21:41.372129 Creating /var/lib/lava/dispatcher/tmp/14479141/lava-overlay-r94b4_47/lava-14479141/bin/lava-add-keys
129 00:21:41.372328 Creating /var/lib/lava/dispatcher/tmp/14479141/lava-overlay-r94b4_47/lava-14479141/bin/lava-add-sources
130 00:21:41.372511 Creating /var/lib/lava/dispatcher/tmp/14479141/lava-overlay-r94b4_47/lava-14479141/bin/lava-background-process-start
131 00:21:41.372706 Creating /var/lib/lava/dispatcher/tmp/14479141/lava-overlay-r94b4_47/lava-14479141/bin/lava-background-process-stop
132 00:21:41.372899 Creating /var/lib/lava/dispatcher/tmp/14479141/lava-overlay-r94b4_47/lava-14479141/bin/lava-common-functions
133 00:21:41.373085 Creating /var/lib/lava/dispatcher/tmp/14479141/lava-overlay-r94b4_47/lava-14479141/bin/lava-echo-ipv4
134 00:21:41.373268 Creating /var/lib/lava/dispatcher/tmp/14479141/lava-overlay-r94b4_47/lava-14479141/bin/lava-install-packages
135 00:21:41.373450 Creating /var/lib/lava/dispatcher/tmp/14479141/lava-overlay-r94b4_47/lava-14479141/bin/lava-installed-packages
136 00:21:41.373621 Creating /var/lib/lava/dispatcher/tmp/14479141/lava-overlay-r94b4_47/lava-14479141/bin/lava-os-build
137 00:21:41.373778 Creating /var/lib/lava/dispatcher/tmp/14479141/lava-overlay-r94b4_47/lava-14479141/bin/lava-probe-channel
138 00:21:41.373931 Creating /var/lib/lava/dispatcher/tmp/14479141/lava-overlay-r94b4_47/lava-14479141/bin/lava-probe-ip
139 00:21:41.374094 Creating /var/lib/lava/dispatcher/tmp/14479141/lava-overlay-r94b4_47/lava-14479141/bin/lava-target-ip
140 00:21:41.374276 Creating /var/lib/lava/dispatcher/tmp/14479141/lava-overlay-r94b4_47/lava-14479141/bin/lava-target-mac
141 00:21:41.374457 Creating /var/lib/lava/dispatcher/tmp/14479141/lava-overlay-r94b4_47/lava-14479141/bin/lava-target-storage
142 00:21:41.374641 Creating /var/lib/lava/dispatcher/tmp/14479141/lava-overlay-r94b4_47/lava-14479141/bin/lava-test-case
143 00:21:41.374826 Creating /var/lib/lava/dispatcher/tmp/14479141/lava-overlay-r94b4_47/lava-14479141/bin/lava-test-event
144 00:21:41.375015 Creating /var/lib/lava/dispatcher/tmp/14479141/lava-overlay-r94b4_47/lava-14479141/bin/lava-test-feedback
145 00:21:41.375191 Creating /var/lib/lava/dispatcher/tmp/14479141/lava-overlay-r94b4_47/lava-14479141/bin/lava-test-raise
146 00:21:41.375376 Creating /var/lib/lava/dispatcher/tmp/14479141/lava-overlay-r94b4_47/lava-14479141/bin/lava-test-reference
147 00:21:41.375561 Creating /var/lib/lava/dispatcher/tmp/14479141/lava-overlay-r94b4_47/lava-14479141/bin/lava-test-runner
148 00:21:41.375750 Creating /var/lib/lava/dispatcher/tmp/14479141/lava-overlay-r94b4_47/lava-14479141/bin/lava-test-set
149 00:21:41.375925 Creating /var/lib/lava/dispatcher/tmp/14479141/lava-overlay-r94b4_47/lava-14479141/bin/lava-test-shell
150 00:21:41.376108 Updating /var/lib/lava/dispatcher/tmp/14479141/lava-overlay-r94b4_47/lava-14479141/bin/lava-install-packages (oe)
151 00:21:41.376325 Updating /var/lib/lava/dispatcher/tmp/14479141/lava-overlay-r94b4_47/lava-14479141/bin/lava-installed-packages (oe)
152 00:21:41.376506 Creating /var/lib/lava/dispatcher/tmp/14479141/lava-overlay-r94b4_47/lava-14479141/environment
153 00:21:41.376654 LAVA metadata
154 00:21:41.376769 - LAVA_JOB_ID=14479141
155 00:21:41.376875 - LAVA_DISPATCHER_IP=192.168.201.1
156 00:21:41.377042 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 00:21:41.377143 skipped lava-vland-overlay
158 00:21:41.377262 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 00:21:41.377393 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 00:21:41.377493 skipped lava-multinode-overlay
161 00:21:41.377616 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 00:21:41.377739 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 00:21:41.377855 Loading test definitions
164 00:21:41.377991 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 00:21:41.378100 Using /lava-14479141 at stage 0
166 00:21:41.378607 uuid=14479141_1.5.2.3.1 testdef=None
167 00:21:41.378739 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 00:21:41.378872 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 00:21:41.379628 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 00:21:41.379987 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 00:21:41.380935 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 00:21:41.381332 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 00:21:41.385669 runner path: /var/lib/lava/dispatcher/tmp/14479141/lava-overlay-r94b4_47/lava-14479141/0/tests/0_igt-kms-mediatek test_uuid 14479141_1.5.2.3.1
176 00:21:41.385922 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 00:21:41.386292 Creating lava-test-runner.conf files
179 00:21:41.386391 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14479141/lava-overlay-r94b4_47/lava-14479141/0 for stage 0
180 00:21:41.386520 - 0_igt-kms-mediatek
181 00:21:41.386676 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 00:21:41.386801 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 00:21:41.396119 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 00:21:41.396340 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 00:21:41.396474 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 00:21:41.396586 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 00:21:41.396710 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 00:21:43.262751 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:02) [common]
189 00:21:43.262902 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
190 00:21:43.262999 extracting modules file /var/lib/lava/dispatcher/tmp/14479141/tftp-deploy-0vfhrgoz/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14479141/extract-overlay-ramdisk-7ywyedrr/ramdisk
191 00:21:43.562180 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 00:21:43.562324 start: 1.5.5 apply-overlay-tftp (timeout 00:09:56) [common]
193 00:21:43.562421 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14479141/compress-overlay-c35tno0n/overlay-1.5.2.4.tar.gz to ramdisk
194 00:21:43.562494 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14479141/compress-overlay-c35tno0n/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14479141/extract-overlay-ramdisk-7ywyedrr/ramdisk
195 00:21:43.568921 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 00:21:43.569041 start: 1.5.6 configure-preseed-file (timeout 00:09:56) [common]
197 00:21:43.569141 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 00:21:43.569239 start: 1.5.7 compress-ramdisk (timeout 00:09:56) [common]
199 00:21:43.569321 Building ramdisk /var/lib/lava/dispatcher/tmp/14479141/extract-overlay-ramdisk-7ywyedrr/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14479141/extract-overlay-ramdisk-7ywyedrr/ramdisk
200 00:21:44.833398 >> 466070 blocks
201 00:21:51.739913 rename /var/lib/lava/dispatcher/tmp/14479141/extract-overlay-ramdisk-7ywyedrr/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14479141/tftp-deploy-0vfhrgoz/ramdisk/ramdisk.cpio.gz
202 00:21:51.740112 end: 1.5.7 compress-ramdisk (duration 00:00:08) [common]
203 00:21:51.740249 start: 1.5.8 prepare-kernel (timeout 00:09:48) [common]
204 00:21:51.740372 start: 1.5.8.1 prepare-fit (timeout 00:09:48) [common]
205 00:21:51.740487 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14479141/tftp-deploy-0vfhrgoz/kernel/Image']
206 00:22:07.502932 Returned 0 in 15 seconds
207 00:22:07.603473 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14479141/tftp-deploy-0vfhrgoz/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14479141/tftp-deploy-0vfhrgoz/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14479141/tftp-deploy-0vfhrgoz/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14479141/tftp-deploy-0vfhrgoz/kernel/image.itb
208 00:22:08.597640 output: FIT description: Kernel Image image with one or more FDT blobs
209 00:22:08.597759 output: Created: Fri Jun 21 01:22:08 2024
210 00:22:08.597828 output: Image 0 (kernel-1)
211 00:22:08.597885 output: Description:
212 00:22:08.597941 output: Created: Fri Jun 21 01:22:08 2024
213 00:22:08.597994 output: Type: Kernel Image
214 00:22:08.598050 output: Compression: lzma compressed
215 00:22:08.598108 output: Data Size: 13124896 Bytes = 12817.28 KiB = 12.52 MiB
216 00:22:08.598162 output: Architecture: AArch64
217 00:22:08.598216 output: OS: Linux
218 00:22:08.598273 output: Load Address: 0x00000000
219 00:22:08.598334 output: Entry Point: 0x00000000
220 00:22:08.598391 output: Hash algo: crc32
221 00:22:08.598447 output: Hash value: ab2f7826
222 00:22:08.598504 output: Image 1 (fdt-1)
223 00:22:08.598558 output: Description: mt8192-asurada-spherion-r0
224 00:22:08.598611 output: Created: Fri Jun 21 01:22:08 2024
225 00:22:08.598663 output: Type: Flat Device Tree
226 00:22:08.598715 output: Compression: uncompressed
227 00:22:08.598777 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 00:22:08.598834 output: Architecture: AArch64
229 00:22:08.598886 output: Hash algo: crc32
230 00:22:08.598934 output: Hash value: 0f8e4d2e
231 00:22:08.598982 output: Image 2 (ramdisk-1)
232 00:22:08.599046 output: Description: unavailable
233 00:22:08.599119 output: Created: Fri Jun 21 01:22:08 2024
234 00:22:08.599169 output: Type: RAMDisk Image
235 00:22:08.599217 output: Compression: uncompressed
236 00:22:08.599265 output: Data Size: 61025902 Bytes = 59595.61 KiB = 58.20 MiB
237 00:22:08.599349 output: Architecture: AArch64
238 00:22:08.599402 output: OS: Linux
239 00:22:08.599451 output: Load Address: unavailable
240 00:22:08.599499 output: Entry Point: unavailable
241 00:22:08.599546 output: Hash algo: crc32
242 00:22:08.599594 output: Hash value: 7218ae3f
243 00:22:08.599690 output: Default Configuration: 'conf-1'
244 00:22:08.599770 output: Configuration 0 (conf-1)
245 00:22:08.599819 output: Description: mt8192-asurada-spherion-r0
246 00:22:08.599899 output: Kernel: kernel-1
247 00:22:08.599985 output: Init Ramdisk: ramdisk-1
248 00:22:08.600037 output: FDT: fdt-1
249 00:22:08.600092 output: Loadables: kernel-1
250 00:22:08.600145 output:
251 00:22:08.600297 end: 1.5.8.1 prepare-fit (duration 00:00:17) [common]
252 00:22:08.600409 end: 1.5.8 prepare-kernel (duration 00:00:17) [common]
253 00:22:08.600532 end: 1.5 prepare-tftp-overlay (duration 00:00:27) [common]
254 00:22:08.600653 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:31) [common]
255 00:22:08.600783 No LXC device requested
256 00:22:08.600918 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 00:22:08.601035 start: 1.7 deploy-device-env (timeout 00:09:31) [common]
258 00:22:08.601142 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 00:22:08.601236 Checking files for TFTP limit of 4294967296 bytes.
260 00:22:08.601691 end: 1 tftp-deploy (duration 00:00:29) [common]
261 00:22:08.601790 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 00:22:08.601881 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 00:22:08.601994 substitutions:
264 00:22:08.602057 - {DTB}: 14479141/tftp-deploy-0vfhrgoz/dtb/mt8192-asurada-spherion-r0.dtb
265 00:22:08.602118 - {INITRD}: 14479141/tftp-deploy-0vfhrgoz/ramdisk/ramdisk.cpio.gz
266 00:22:08.602172 - {KERNEL}: 14479141/tftp-deploy-0vfhrgoz/kernel/Image
267 00:22:08.602224 - {LAVA_MAC}: None
268 00:22:08.602275 - {PRESEED_CONFIG}: None
269 00:22:08.602326 - {PRESEED_LOCAL}: None
270 00:22:08.602383 - {RAMDISK}: 14479141/tftp-deploy-0vfhrgoz/ramdisk/ramdisk.cpio.gz
271 00:22:08.602448 - {ROOT_PART}: None
272 00:22:08.602524 - {ROOT}: None
273 00:22:08.602604 - {SERVER_IP}: 192.168.201.1
274 00:22:08.602683 - {TEE}: None
275 00:22:08.602761 Parsed boot commands:
276 00:22:08.602842 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 00:22:08.603034 Parsed boot commands: tftpboot 192.168.201.1 14479141/tftp-deploy-0vfhrgoz/kernel/image.itb 14479141/tftp-deploy-0vfhrgoz/kernel/cmdline
278 00:22:08.603142 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 00:22:08.603248 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 00:22:08.603357 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 00:22:08.603471 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 00:22:08.603560 Not connected, no need to disconnect.
283 00:22:08.603656 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 00:22:08.603756 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 00:22:08.603845 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
286 00:22:08.607012 Setting prompt string to ['lava-test: # ']
287 00:22:08.607368 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 00:22:08.607500 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 00:22:08.607626 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 00:22:08.607742 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 00:22:08.608002 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-8']
292 00:22:22.453663 Returned 0 in 13 seconds
293 00:22:22.554248 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
295 00:22:22.554531 end: 2.2.2 reset-device (duration 00:00:14) [common]
296 00:22:22.554630 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
297 00:22:22.554723 Setting prompt string to 'Starting depthcharge on Spherion...'
298 00:22:22.554786 Changing prompt to 'Starting depthcharge on Spherion...'
299 00:22:22.554854 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
300 00:22:22.555247 [Enter `^Ec?' for help]
301 00:22:22.555325
302 00:22:22.555385
303 00:22:22.555443 F0: 102B 0000
304 00:22:22.555498
305 00:22:22.555551 F3: 1001 0000 [0200]
306 00:22:22.555604
307 00:22:22.555659 F3: 1001 0000
308 00:22:22.555712
309 00:22:22.555764 F7: 102D 0000
310 00:22:22.555815
311 00:22:22.555867 F1: 0000 0000
312 00:22:22.555921
313 00:22:22.555973 V0: 0000 0000 [0001]
314 00:22:22.556026
315 00:22:22.556079 00: 0007 8000
316 00:22:22.556129
317 00:22:22.556178 01: 0000 0000
318 00:22:22.556227
319 00:22:22.556276 BP: 0C00 0209 [0000]
320 00:22:22.556324
321 00:22:22.556372 G0: 1182 0000
322 00:22:22.556420
323 00:22:22.556468 EC: 0000 0021 [4000]
324 00:22:22.556516
325 00:22:22.556565 S7: 0000 0000 [0000]
326 00:22:22.556613
327 00:22:22.556702 CC: 0000 0000 [0001]
328 00:22:22.556751
329 00:22:22.556799 T0: 0000 0040 [010F]
330 00:22:22.556847
331 00:22:22.556895 Jump to BL
332 00:22:22.556943
333 00:22:22.556992
334 00:22:22.557040
335 00:22:22.557088 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
336 00:22:22.557140 ARM64: Exception handlers installed.
337 00:22:22.557191 ARM64: Testing exception
338 00:22:22.557240 ARM64: Done test exception
339 00:22:22.557288 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
340 00:22:22.557338 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
341 00:22:22.557388 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
342 00:22:22.557439 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
343 00:22:22.557489 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
344 00:22:22.557538 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
345 00:22:22.557588 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
346 00:22:22.557637 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
347 00:22:22.557687 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
348 00:22:22.557737 WDT: Last reset was cold boot
349 00:22:22.557785 SPI1(PAD0) initialized at 2873684 Hz
350 00:22:22.557834 SPI5(PAD0) initialized at 992727 Hz
351 00:22:22.557882 VBOOT: Loading verstage.
352 00:22:22.557931 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
353 00:22:22.557980 FMAP: Found "FLASH" version 1.1 at 0x20000.
354 00:22:22.558030 FMAP: base = 0x0 size = 0x800000 #areas = 25
355 00:22:22.558078 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
356 00:22:22.558127 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
357 00:22:22.558177 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
358 00:22:22.558227 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
359 00:22:22.558276
360 00:22:22.558324
361 00:22:22.558373 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
362 00:22:22.558423 ARM64: Exception handlers installed.
363 00:22:22.558471 ARM64: Testing exception
364 00:22:22.558529 ARM64: Done test exception
365 00:22:22.558589 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
366 00:22:22.558639 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
367 00:22:22.558688 Probing TPM: . done!
368 00:22:22.558737 TPM ready after 0 ms
369 00:22:22.558786 Connected to device vid:did:rid of 1ae0:0028:00
370 00:22:22.558835 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
371 00:22:22.558885 Initialized TPM device CR50 revision 0
372 00:22:22.558934 tlcl_send_startup: Startup return code is 0
373 00:22:22.558983 TPM: setup succeeded
374 00:22:22.559032 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
375 00:22:22.559081 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
376 00:22:22.559130 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
377 00:22:22.559181 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 00:22:22.559229 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
379 00:22:22.559279 in-header: 03 07 00 00 08 00 00 00
380 00:22:22.559328 in-data: aa e4 47 04 13 02 00 00
381 00:22:22.559377 Chrome EC: UHEPI supported
382 00:22:22.559426 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
383 00:22:22.559475 in-header: 03 a9 00 00 08 00 00 00
384 00:22:22.559523 in-data: 84 60 60 08 00 00 00 00
385 00:22:22.559572 Phase 1
386 00:22:22.559620 FMAP: area GBB found @ 3f5000 (12032 bytes)
387 00:22:22.559669 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
388 00:22:22.559718 VB2:vb2_check_recovery() Recovery was requested manually
389 00:22:22.559768 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
390 00:22:22.559817 Recovery requested (1009000e)
391 00:22:22.559866 TPM: Extending digest for VBOOT: boot mode into PCR 0
392 00:22:22.559915 tlcl_extend: response is 0
393 00:22:22.559964 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
394 00:22:22.560013 tlcl_extend: response is 0
395 00:22:22.560061 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
396 00:22:22.560110 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
397 00:22:22.560159 BS: bootblock times (exec / console): total (unknown) / 148 ms
398 00:22:22.560208
399 00:22:22.560255
400 00:22:22.560304 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
401 00:22:22.560354 ARM64: Exception handlers installed.
402 00:22:22.560403 ARM64: Testing exception
403 00:22:22.560451 ARM64: Done test exception
404 00:22:22.560499 pmic_efuse_setting: Set efuses in 11 msecs
405 00:22:22.560548 pmwrap_interface_init: Select PMIF_VLD_RDY
406 00:22:22.560596 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
407 00:22:22.560668 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
408 00:22:22.560924 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
409 00:22:22.560979 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
410 00:22:22.561047 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
411 00:22:22.561097 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
412 00:22:22.561147 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
413 00:22:22.561197 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
414 00:22:22.561247 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
415 00:22:22.561297 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
416 00:22:22.561347 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
417 00:22:22.561398 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
418 00:22:22.561447 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
419 00:22:22.561497 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
420 00:22:22.561546 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
421 00:22:22.561597 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
422 00:22:22.561647 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
423 00:22:22.561697 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
424 00:22:22.561747 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
425 00:22:22.561797 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
426 00:22:22.561846 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
427 00:22:22.561896 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
428 00:22:22.561951 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
429 00:22:22.562017 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
430 00:22:22.562069 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
431 00:22:22.562119 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
432 00:22:22.562169 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
433 00:22:22.562219 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
434 00:22:22.562269 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
435 00:22:22.562320 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
436 00:22:22.562369 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
437 00:22:22.562419 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
438 00:22:22.562469 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
439 00:22:22.562528 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
440 00:22:22.562585 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
441 00:22:22.562635 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
442 00:22:22.562686 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
443 00:22:22.562736 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
444 00:22:22.562785 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
445 00:22:22.562835 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
446 00:22:22.562884 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
447 00:22:22.562934 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
448 00:22:22.562983 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
449 00:22:22.563033 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
450 00:22:22.563083 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
451 00:22:22.563132 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
452 00:22:22.563181 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
453 00:22:22.563231 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
454 00:22:22.563280 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
455 00:22:22.563329 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
456 00:22:22.563379 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
457 00:22:22.563428 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
458 00:22:22.563479 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
459 00:22:22.563530 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
460 00:22:22.563580 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
461 00:22:22.563630 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
462 00:22:22.563681 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
463 00:22:22.563731 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
464 00:22:22.563780 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 00:22:22.563829 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x39
466 00:22:22.563879 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
467 00:22:22.563928 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
468 00:22:22.563978 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
469 00:22:22.564027 [RTC]rtc_get_frequency_meter,154: input=15, output=794
470 00:22:22.564078 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
471 00:22:22.564127 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
472 00:22:22.564177 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
473 00:22:22.564227 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
474 00:22:22.564276 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
475 00:22:22.564326 ADC[4]: Raw value=895191 ID=7
476 00:22:22.564375 ADC[3]: Raw value=213810 ID=1
477 00:22:22.564424 RAM Code: 0x71
478 00:22:22.564473 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
479 00:22:22.564522 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
480 00:22:22.564760 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
481 00:22:22.564834 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
482 00:22:22.564885 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
483 00:22:22.564934 in-header: 03 07 00 00 08 00 00 00
484 00:22:22.564982 in-data: aa e4 47 04 13 02 00 00
485 00:22:22.565031 Chrome EC: UHEPI supported
486 00:22:22.565079 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
487 00:22:22.565129 in-header: 03 a9 00 00 08 00 00 00
488 00:22:22.565177 in-data: 84 60 60 08 00 00 00 00
489 00:22:22.565225 MRC: failed to locate region type 0.
490 00:22:22.565274 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
491 00:22:22.565331 DRAM-K: Running full calibration
492 00:22:22.565391 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
493 00:22:22.565441 header.status = 0x0
494 00:22:22.565490 header.version = 0x6 (expected: 0x6)
495 00:22:22.565539 header.size = 0xd00 (expected: 0xd00)
496 00:22:22.565587 header.flags = 0x0
497 00:22:22.565636 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
498 00:22:22.565685 read SPI 0x72590 0x1c583: 12497 us, 9290 KB/s, 74.320 Mbps
499 00:22:22.565734 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
500 00:22:22.565783 dram_init: ddr_geometry: 2
501 00:22:22.565831 [EMI] MDL number = 2
502 00:22:22.565879 [EMI] Get MDL freq = 0
503 00:22:22.565927 dram_init: ddr_type: 0
504 00:22:22.565975 is_discrete_lpddr4: 1
505 00:22:22.566024 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
506 00:22:22.566072
507 00:22:22.566120
508 00:22:22.566168 [Bian_co] ETT version 0.0.0.1
509 00:22:22.566227 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
510 00:22:22.566276
511 00:22:22.566327 dramc_set_vcore_voltage set vcore to 650000
512 00:22:22.566377 Read voltage for 800, 4
513 00:22:22.566426 Vio18 = 0
514 00:22:22.566474 Vcore = 650000
515 00:22:22.566522 Vdram = 0
516 00:22:22.566571 Vddq = 0
517 00:22:22.566619 Vmddr = 0
518 00:22:22.566666 dram_init: config_dvfs: 1
519 00:22:22.566715 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
520 00:22:22.566764 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
521 00:22:22.566812 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
522 00:22:22.566861 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
523 00:22:22.566910 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
524 00:22:22.566958 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
525 00:22:22.567006 MEM_TYPE=3, freq_sel=18
526 00:22:22.567055 sv_algorithm_assistance_LP4_1600
527 00:22:22.567103 ============ PULL DRAM RESETB DOWN ============
528 00:22:22.567157 ========== PULL DRAM RESETB DOWN end =========
529 00:22:22.567209 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
530 00:22:22.567265 ===================================
531 00:22:22.567314 LPDDR4 DRAM CONFIGURATION
532 00:22:22.567362 ===================================
533 00:22:22.567411 EX_ROW_EN[0] = 0x0
534 00:22:22.567459 EX_ROW_EN[1] = 0x0
535 00:22:22.567507 LP4Y_EN = 0x0
536 00:22:22.567556 WORK_FSP = 0x0
537 00:22:22.567603 WL = 0x2
538 00:22:22.567651 RL = 0x2
539 00:22:22.567698 BL = 0x2
540 00:22:22.567746 RPST = 0x0
541 00:22:22.567795 RD_PRE = 0x0
542 00:22:22.567843 WR_PRE = 0x1
543 00:22:22.567891 WR_PST = 0x0
544 00:22:22.567938 DBI_WR = 0x0
545 00:22:22.567986 DBI_RD = 0x0
546 00:22:22.568033 OTF = 0x1
547 00:22:22.568082 ===================================
548 00:22:22.568131 ===================================
549 00:22:22.568180 ANA top config
550 00:22:22.568228 ===================================
551 00:22:22.568336 DLL_ASYNC_EN = 0
552 00:22:22.568402 ALL_SLAVE_EN = 1
553 00:22:22.568451 NEW_RANK_MODE = 1
554 00:22:22.568500 DLL_IDLE_MODE = 1
555 00:22:22.568549 LP45_APHY_COMB_EN = 1
556 00:22:22.568597 TX_ODT_DIS = 1
557 00:22:22.568670 NEW_8X_MODE = 1
558 00:22:22.568757 ===================================
559 00:22:22.568810 ===================================
560 00:22:22.568859 data_rate = 1600
561 00:22:22.568908 CKR = 1
562 00:22:22.568956 DQ_P2S_RATIO = 8
563 00:22:22.569005 ===================================
564 00:22:22.569053 CA_P2S_RATIO = 8
565 00:22:22.569101 DQ_CA_OPEN = 0
566 00:22:22.569149 DQ_SEMI_OPEN = 0
567 00:22:22.569197 CA_SEMI_OPEN = 0
568 00:22:22.569245 CA_FULL_RATE = 0
569 00:22:22.569293 DQ_CKDIV4_EN = 1
570 00:22:22.569341 CA_CKDIV4_EN = 1
571 00:22:22.569389 CA_PREDIV_EN = 0
572 00:22:22.569437 PH8_DLY = 0
573 00:22:22.569485 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
574 00:22:22.569533 DQ_AAMCK_DIV = 4
575 00:22:22.569581 CA_AAMCK_DIV = 4
576 00:22:22.569628 CA_ADMCK_DIV = 4
577 00:22:22.569676 DQ_TRACK_CA_EN = 0
578 00:22:22.569724 CA_PICK = 800
579 00:22:22.569772 CA_MCKIO = 800
580 00:22:22.569820 MCKIO_SEMI = 0
581 00:22:22.569882 PLL_FREQ = 3068
582 00:22:22.569932 DQ_UI_PI_RATIO = 32
583 00:22:22.569981 CA_UI_PI_RATIO = 0
584 00:22:22.570028 ===================================
585 00:22:22.570076 ===================================
586 00:22:22.570124 memory_type:LPDDR4
587 00:22:22.570172 GP_NUM : 10
588 00:22:22.570252 SRAM_EN : 1
589 00:22:22.570301 MD32_EN : 0
590 00:22:22.570350 ===================================
591 00:22:22.570399 [ANA_INIT] >>>>>>>>>>>>>>
592 00:22:22.570447 <<<<<< [CONFIGURE PHASE]: ANA_TX
593 00:22:22.570502 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
594 00:22:22.570550 ===================================
595 00:22:22.570599 data_rate = 1600,PCW = 0X7600
596 00:22:22.570647 ===================================
597 00:22:22.570696 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
598 00:22:22.570745 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
599 00:22:22.570794 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
600 00:22:22.571060 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
601 00:22:22.571133 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
602 00:22:22.571183 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
603 00:22:22.571232 [ANA_INIT] flow start
604 00:22:22.571281 [ANA_INIT] PLL >>>>>>>>
605 00:22:22.571330 [ANA_INIT] PLL <<<<<<<<
606 00:22:22.571379 [ANA_INIT] MIDPI >>>>>>>>
607 00:22:22.571427 [ANA_INIT] MIDPI <<<<<<<<
608 00:22:22.571476 [ANA_INIT] DLL >>>>>>>>
609 00:22:22.571525 [ANA_INIT] flow end
610 00:22:22.571573 ============ LP4 DIFF to SE enter ============
611 00:22:22.571622 ============ LP4 DIFF to SE exit ============
612 00:22:22.571670 [ANA_INIT] <<<<<<<<<<<<<
613 00:22:22.571719 [Flow] Enable top DCM control >>>>>
614 00:22:22.571768 [Flow] Enable top DCM control <<<<<
615 00:22:22.571816 Enable DLL master slave shuffle
616 00:22:22.571865 ==============================================================
617 00:22:22.571913 Gating Mode config
618 00:22:22.571966 ==============================================================
619 00:22:22.572054 Config description:
620 00:22:22.572133 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
621 00:22:22.572236 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
622 00:22:22.572332 SELPH_MODE 0: By rank 1: By Phase
623 00:22:22.572390 ==============================================================
624 00:22:22.572454 GAT_TRACK_EN = 1
625 00:22:22.572504 RX_GATING_MODE = 2
626 00:22:22.572553 RX_GATING_TRACK_MODE = 2
627 00:22:22.572602 SELPH_MODE = 1
628 00:22:22.572673 PICG_EARLY_EN = 1
629 00:22:22.572740 VALID_LAT_VALUE = 1
630 00:22:22.572789 ==============================================================
631 00:22:22.572839 Enter into Gating configuration >>>>
632 00:22:22.572887 Exit from Gating configuration <<<<
633 00:22:22.572936 Enter into DVFS_PRE_config >>>>>
634 00:22:22.572985 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
635 00:22:22.573038 Exit from DVFS_PRE_config <<<<<
636 00:22:22.573087 Enter into PICG configuration >>>>
637 00:22:22.573136 Exit from PICG configuration <<<<
638 00:22:22.573185 [RX_INPUT] configuration >>>>>
639 00:22:22.573233 [RX_INPUT] configuration <<<<<
640 00:22:22.573281 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
641 00:22:22.573330 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
642 00:22:22.573380 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
643 00:22:22.573429 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
644 00:22:22.573478 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
645 00:22:22.573527 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
646 00:22:22.573576 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
647 00:22:22.573625 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
648 00:22:22.573672 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
649 00:22:22.573720 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
650 00:22:22.573769 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
651 00:22:22.573817 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
652 00:22:22.573866 ===================================
653 00:22:22.573915 LPDDR4 DRAM CONFIGURATION
654 00:22:22.573963 ===================================
655 00:22:22.574011 EX_ROW_EN[0] = 0x0
656 00:22:22.574059 EX_ROW_EN[1] = 0x0
657 00:22:22.574107 LP4Y_EN = 0x0
658 00:22:22.574154 WORK_FSP = 0x0
659 00:22:22.574202 WL = 0x2
660 00:22:22.574267 RL = 0x2
661 00:22:22.574329 BL = 0x2
662 00:22:22.574377 RPST = 0x0
663 00:22:22.574424 RD_PRE = 0x0
664 00:22:22.574472 WR_PRE = 0x1
665 00:22:22.574519 WR_PST = 0x0
666 00:22:22.574568 DBI_WR = 0x0
667 00:22:22.574616 DBI_RD = 0x0
668 00:22:22.574663 OTF = 0x1
669 00:22:22.574710 ===================================
670 00:22:22.574759 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
671 00:22:22.574808 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
672 00:22:22.574856 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
673 00:22:22.574905 ===================================
674 00:22:22.574954 LPDDR4 DRAM CONFIGURATION
675 00:22:22.575002 ===================================
676 00:22:22.575051 EX_ROW_EN[0] = 0x10
677 00:22:22.575120 EX_ROW_EN[1] = 0x0
678 00:22:22.575173 LP4Y_EN = 0x0
679 00:22:22.575221 WORK_FSP = 0x0
680 00:22:22.575270 WL = 0x2
681 00:22:22.575318 RL = 0x2
682 00:22:22.575366 BL = 0x2
683 00:22:22.575413 RPST = 0x0
684 00:22:22.575460 RD_PRE = 0x0
685 00:22:22.575508 WR_PRE = 0x1
686 00:22:22.575555 WR_PST = 0x0
687 00:22:22.575603 DBI_WR = 0x0
688 00:22:22.575650 DBI_RD = 0x0
689 00:22:22.575698 OTF = 0x1
690 00:22:22.575747 ===================================
691 00:22:22.575796 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
692 00:22:22.575845 nWR fixed to 40
693 00:22:22.575894 [ModeRegInit_LP4] CH0 RK0
694 00:22:22.575960 [ModeRegInit_LP4] CH0 RK1
695 00:22:22.576022 [ModeRegInit_LP4] CH1 RK0
696 00:22:22.576069 [ModeRegInit_LP4] CH1 RK1
697 00:22:22.576116 match AC timing 13
698 00:22:22.576164 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
699 00:22:22.576212 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
700 00:22:22.576260 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
701 00:22:22.576310 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
702 00:22:22.576358 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
703 00:22:22.576407 [EMI DOE] emi_dcm 0
704 00:22:22.576455 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
705 00:22:22.576503 ==
706 00:22:22.576551 Dram Type= 6, Freq= 0, CH_0, rank 0
707 00:22:22.576599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
708 00:22:22.576670 ==
709 00:22:22.576929 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
710 00:22:22.576985 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
711 00:22:22.577036 [CA 0] Center 38 (7~69) winsize 63
712 00:22:22.577086 [CA 1] Center 37 (7~68) winsize 62
713 00:22:22.577134 [CA 2] Center 35 (5~66) winsize 62
714 00:22:22.577190 [CA 3] Center 35 (5~66) winsize 62
715 00:22:22.577243 [CA 4] Center 34 (4~65) winsize 62
716 00:22:22.577292 [CA 5] Center 34 (4~65) winsize 62
717 00:22:22.577340
718 00:22:22.577388 [CmdBusTrainingLP45] Vref(ca) range 1: 34
719 00:22:22.577437
720 00:22:22.577484 [CATrainingPosCal] consider 1 rank data
721 00:22:22.577533 u2DelayCellTimex100 = 270/100 ps
722 00:22:22.577580 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
723 00:22:22.577629 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
724 00:22:22.577677 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
725 00:22:22.577725 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
726 00:22:22.577773 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
727 00:22:22.577821 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
728 00:22:22.577868
729 00:22:22.577916 CA PerBit enable=1, Macro0, CA PI delay=34
730 00:22:22.577964
731 00:22:22.578012 [CBTSetCACLKResult] CA Dly = 34
732 00:22:22.578060 CS Dly: 6 (0~37)
733 00:22:22.578107 ==
734 00:22:22.578155 Dram Type= 6, Freq= 0, CH_0, rank 1
735 00:22:22.578203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
736 00:22:22.578252 ==
737 00:22:22.578300 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
738 00:22:22.578348 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
739 00:22:22.578396 [CA 0] Center 38 (7~69) winsize 63
740 00:22:22.578445 [CA 1] Center 38 (7~69) winsize 63
741 00:22:22.578493 [CA 2] Center 35 (5~66) winsize 62
742 00:22:22.578540 [CA 3] Center 35 (5~66) winsize 62
743 00:22:22.578588 [CA 4] Center 34 (4~65) winsize 62
744 00:22:22.578636 [CA 5] Center 34 (4~65) winsize 62
745 00:22:22.578705
746 00:22:22.578758 [CmdBusTrainingLP45] Vref(ca) range 1: 32
747 00:22:22.578806
748 00:22:22.578854 [CATrainingPosCal] consider 2 rank data
749 00:22:22.578902 u2DelayCellTimex100 = 270/100 ps
750 00:22:22.578951 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
751 00:22:22.578999 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
752 00:22:22.579047 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
753 00:22:22.579095 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
754 00:22:22.579144 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
755 00:22:22.579192 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
756 00:22:22.579240
757 00:22:22.579289 CA PerBit enable=1, Macro0, CA PI delay=34
758 00:22:22.579337
759 00:22:22.579386 [CBTSetCACLKResult] CA Dly = 34
760 00:22:22.579434 CS Dly: 6 (0~38)
761 00:22:22.579482
762 00:22:22.579529 ----->DramcWriteLeveling(PI) begin...
763 00:22:22.579581 ==
764 00:22:22.579631 Dram Type= 6, Freq= 0, CH_0, rank 0
765 00:22:22.579680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
766 00:22:22.579729 ==
767 00:22:22.579777 Write leveling (Byte 0): 30 => 30
768 00:22:22.579825 Write leveling (Byte 1): 30 => 30
769 00:22:22.579874 DramcWriteLeveling(PI) end<-----
770 00:22:22.579921
771 00:22:22.579969 ==
772 00:22:22.580016 Dram Type= 6, Freq= 0, CH_0, rank 0
773 00:22:22.580065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 00:22:22.580114 ==
775 00:22:22.580161 [Gating] SW mode calibration
776 00:22:22.580237 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
777 00:22:22.580314 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
778 00:22:22.580403 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
779 00:22:22.580498 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
780 00:22:22.580576 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
781 00:22:22.580659 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
782 00:22:22.580744 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
783 00:22:22.580793 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
784 00:22:22.580841 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
785 00:22:22.580890 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
786 00:22:22.580939 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 00:22:22.580988 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 00:22:22.581036 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 00:22:22.581085 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 00:22:22.581134 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 00:22:22.581182 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 00:22:22.581230 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 00:22:22.581278 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 00:22:22.581327 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 00:22:22.581376 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
796 00:22:22.581424 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
797 00:22:22.581472 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
798 00:22:22.581540 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 00:22:22.581593 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 00:22:22.581642 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 00:22:22.581690 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 00:22:22.581740 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 00:22:22.581788 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 00:22:22.581837 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 00:22:22.581885 0 9 12 | B1->B0 | 2525 3131 | 1 0 | (1 1) (0 0)
806 00:22:22.581934 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
807 00:22:22.581982 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
808 00:22:22.582030 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
809 00:22:22.582079 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
810 00:22:22.582128 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
811 00:22:22.582176 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 00:22:22.582225 0 10 8 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
813 00:22:22.582294 0 10 12 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
814 00:22:22.582373 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 00:22:22.582634 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 00:22:22.582689 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 00:22:22.582740 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 00:22:22.582789 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 00:22:22.582838 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 00:22:22.582887 0 11 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (1 1)
821 00:22:22.582936 0 11 12 | B1->B0 | 3d3d 4141 | 0 0 | (0 0) (0 0)
822 00:22:22.582984 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
823 00:22:22.583032 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
824 00:22:22.583081 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
825 00:22:22.583129 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
826 00:22:22.583177 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
827 00:22:22.583226 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 00:22:22.583275 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
829 00:22:22.583323 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
830 00:22:22.583371 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
831 00:22:22.583419 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
832 00:22:22.583467 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
833 00:22:22.583520 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
834 00:22:22.583580 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 00:22:22.583629 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 00:22:22.583678 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 00:22:22.583727 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 00:22:22.583775 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 00:22:22.583824 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 00:22:22.583872 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 00:22:22.583922 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 00:22:22.584004 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 00:22:22.584053 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 00:22:22.584101 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
845 00:22:22.584150 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
846 00:22:22.584198 Total UI for P1: 0, mck2ui 16
847 00:22:22.584247 best dqsien dly found for B0: ( 0, 14, 8)
848 00:22:22.584295 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
849 00:22:22.584344 Total UI for P1: 0, mck2ui 16
850 00:22:22.584393 best dqsien dly found for B1: ( 0, 14, 12)
851 00:22:22.584442 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
852 00:22:22.584490 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
853 00:22:22.584538
854 00:22:22.584586 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
855 00:22:22.584636 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
856 00:22:22.584730 [Gating] SW calibration Done
857 00:22:22.584780 ==
858 00:22:22.584829 Dram Type= 6, Freq= 0, CH_0, rank 0
859 00:22:22.584878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
860 00:22:22.584927 ==
861 00:22:22.584975 RX Vref Scan: 0
862 00:22:22.585024
863 00:22:22.585096 RX Vref 0 -> 0, step: 1
864 00:22:22.585147
865 00:22:22.585195 RX Delay -130 -> 252, step: 16
866 00:22:22.585244 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
867 00:22:22.585293 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
868 00:22:22.585341 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
869 00:22:22.585391 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
870 00:22:22.585440 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
871 00:22:22.585489 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
872 00:22:22.585537 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
873 00:22:22.585586 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
874 00:22:22.585643 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
875 00:22:22.585694 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
876 00:22:22.585743 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
877 00:22:22.585792 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
878 00:22:22.585841 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
879 00:22:22.585890 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
880 00:22:22.585938 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
881 00:22:22.585987 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
882 00:22:22.586035 ==
883 00:22:22.586084 Dram Type= 6, Freq= 0, CH_0, rank 0
884 00:22:22.586133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
885 00:22:22.586181 ==
886 00:22:22.586246 DQS Delay:
887 00:22:22.586295 DQS0 = 0, DQS1 = 0
888 00:22:22.586344 DQM Delay:
889 00:22:22.586393 DQM0 = 83, DQM1 = 70
890 00:22:22.586456 DQ Delay:
891 00:22:22.586504 DQ0 =77, DQ1 =85, DQ2 =85, DQ3 =85
892 00:22:22.586552 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =93
893 00:22:22.586599 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
894 00:22:22.586648 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
895 00:22:22.586695
896 00:22:22.586743
897 00:22:22.586790 ==
898 00:22:22.586838 Dram Type= 6, Freq= 0, CH_0, rank 0
899 00:22:22.586887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
900 00:22:22.586935 ==
901 00:22:22.586982
902 00:22:22.587030
903 00:22:22.587095 TX Vref Scan disable
904 00:22:22.587158 == TX Byte 0 ==
905 00:22:22.587205 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
906 00:22:22.587254 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
907 00:22:22.587302 == TX Byte 1 ==
908 00:22:22.587350 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
909 00:22:22.587397 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
910 00:22:22.587445 ==
911 00:22:22.587493 Dram Type= 6, Freq= 0, CH_0, rank 0
912 00:22:22.587542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
913 00:22:22.587591 ==
914 00:22:22.587638 TX Vref=22, minBit 5, minWin=26, winSum=434
915 00:22:22.587687 TX Vref=24, minBit 11, minWin=26, winSum=436
916 00:22:22.587735 TX Vref=26, minBit 1, minWin=27, winSum=440
917 00:22:22.587784 TX Vref=28, minBit 1, minWin=27, winSum=440
918 00:22:22.587833 TX Vref=30, minBit 1, minWin=27, winSum=442
919 00:22:22.587882 TX Vref=32, minBit 1, minWin=27, winSum=441
920 00:22:22.587929 [TxChooseVref] Worse bit 1, Min win 27, Win sum 442, Final Vref 30
921 00:22:22.587978
922 00:22:22.588025 Final TX Range 1 Vref 30
923 00:22:22.588073
924 00:22:22.588120 ==
925 00:22:22.588168 Dram Type= 6, Freq= 0, CH_0, rank 0
926 00:22:22.588429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
927 00:22:22.588515 ==
928 00:22:22.588593
929 00:22:22.588688
930 00:22:22.588740 TX Vref Scan disable
931 00:22:22.588790 == TX Byte 0 ==
932 00:22:22.588840 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
933 00:22:22.588890 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
934 00:22:22.588939 == TX Byte 1 ==
935 00:22:22.588988 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
936 00:22:22.589038 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
937 00:22:22.589087
938 00:22:22.589134 [DATLAT]
939 00:22:22.589183 Freq=800, CH0 RK0
940 00:22:22.589232
941 00:22:22.589279 DATLAT Default: 0xa
942 00:22:22.589328 0, 0xFFFF, sum = 0
943 00:22:22.589377 1, 0xFFFF, sum = 0
944 00:22:22.589427 2, 0xFFFF, sum = 0
945 00:22:22.589476 3, 0xFFFF, sum = 0
946 00:22:22.589528 4, 0xFFFF, sum = 0
947 00:22:22.589578 5, 0xFFFF, sum = 0
948 00:22:22.589658 6, 0xFFFF, sum = 0
949 00:22:22.589708 7, 0xFFFF, sum = 0
950 00:22:22.589757 8, 0xFFFF, sum = 0
951 00:22:22.589806 9, 0x0, sum = 1
952 00:22:22.589855 10, 0x0, sum = 2
953 00:22:22.589904 11, 0x0, sum = 3
954 00:22:22.589953 12, 0x0, sum = 4
955 00:22:22.590001 best_step = 10
956 00:22:22.590050
957 00:22:22.590097 ==
958 00:22:22.590145 Dram Type= 6, Freq= 0, CH_0, rank 0
959 00:22:22.590194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
960 00:22:22.590243 ==
961 00:22:22.590291 RX Vref Scan: 1
962 00:22:22.590339
963 00:22:22.590388 Set Vref Range= 32 -> 127
964 00:22:22.590435
965 00:22:22.590482 RX Vref 32 -> 127, step: 1
966 00:22:22.590530
967 00:22:22.590577 RX Delay -111 -> 252, step: 8
968 00:22:22.590626
969 00:22:22.590674 Set Vref, RX VrefLevel [Byte0]: 32
970 00:22:22.590723 [Byte1]: 32
971 00:22:22.590771
972 00:22:22.590820 Set Vref, RX VrefLevel [Byte0]: 33
973 00:22:22.590869 [Byte1]: 33
974 00:22:22.590917
975 00:22:22.590964 Set Vref, RX VrefLevel [Byte0]: 34
976 00:22:22.591013 [Byte1]: 34
977 00:22:22.591061
978 00:22:22.591110 Set Vref, RX VrefLevel [Byte0]: 35
979 00:22:22.591158 [Byte1]: 35
980 00:22:22.591206
981 00:22:22.591254 Set Vref, RX VrefLevel [Byte0]: 36
982 00:22:22.591302 [Byte1]: 36
983 00:22:22.591351
984 00:22:22.591399 Set Vref, RX VrefLevel [Byte0]: 37
985 00:22:22.591446 [Byte1]: 37
986 00:22:22.591494
987 00:22:22.591546 Set Vref, RX VrefLevel [Byte0]: 38
988 00:22:22.591611 [Byte1]: 38
989 00:22:22.591661
990 00:22:22.591710 Set Vref, RX VrefLevel [Byte0]: 39
991 00:22:22.591759 [Byte1]: 39
992 00:22:22.591807
993 00:22:22.591855 Set Vref, RX VrefLevel [Byte0]: 40
994 00:22:22.591903 [Byte1]: 40
995 00:22:22.591951
996 00:22:22.591999 Set Vref, RX VrefLevel [Byte0]: 41
997 00:22:22.592047 [Byte1]: 41
998 00:22:22.592095
999 00:22:22.592142 Set Vref, RX VrefLevel [Byte0]: 42
1000 00:22:22.592190 [Byte1]: 42
1001 00:22:22.592238
1002 00:22:22.592286 Set Vref, RX VrefLevel [Byte0]: 43
1003 00:22:22.592334 [Byte1]: 43
1004 00:22:22.592382
1005 00:22:22.592430 Set Vref, RX VrefLevel [Byte0]: 44
1006 00:22:22.592478 [Byte1]: 44
1007 00:22:22.592526
1008 00:22:22.592574 Set Vref, RX VrefLevel [Byte0]: 45
1009 00:22:22.592641 [Byte1]: 45
1010 00:22:22.592718
1011 00:22:22.592767 Set Vref, RX VrefLevel [Byte0]: 46
1012 00:22:22.592816 [Byte1]: 46
1013 00:22:22.592865
1014 00:22:22.592913 Set Vref, RX VrefLevel [Byte0]: 47
1015 00:22:22.592962 [Byte1]: 47
1016 00:22:22.593011
1017 00:22:22.593059 Set Vref, RX VrefLevel [Byte0]: 48
1018 00:22:22.593108 [Byte1]: 48
1019 00:22:22.593156
1020 00:22:22.593204 Set Vref, RX VrefLevel [Byte0]: 49
1021 00:22:22.593253 [Byte1]: 49
1022 00:22:22.593303
1023 00:22:22.593352 Set Vref, RX VrefLevel [Byte0]: 50
1024 00:22:22.593401 [Byte1]: 50
1025 00:22:22.593448
1026 00:22:22.593496 Set Vref, RX VrefLevel [Byte0]: 51
1027 00:22:22.593545 [Byte1]: 51
1028 00:22:22.593593
1029 00:22:22.593642 Set Vref, RX VrefLevel [Byte0]: 52
1030 00:22:22.593690 [Byte1]: 52
1031 00:22:22.593739
1032 00:22:22.593787 Set Vref, RX VrefLevel [Byte0]: 53
1033 00:22:22.593836 [Byte1]: 53
1034 00:22:22.593884
1035 00:22:22.593931 Set Vref, RX VrefLevel [Byte0]: 54
1036 00:22:22.593979 [Byte1]: 54
1037 00:22:22.594027
1038 00:22:22.594076 Set Vref, RX VrefLevel [Byte0]: 55
1039 00:22:22.594124 [Byte1]: 55
1040 00:22:22.594172
1041 00:22:22.594220 Set Vref, RX VrefLevel [Byte0]: 56
1042 00:22:22.594268 [Byte1]: 56
1043 00:22:22.594316
1044 00:22:22.594362 Set Vref, RX VrefLevel [Byte0]: 57
1045 00:22:22.594410 [Byte1]: 57
1046 00:22:22.594458
1047 00:22:22.594505 Set Vref, RX VrefLevel [Byte0]: 58
1048 00:22:22.594554 [Byte1]: 58
1049 00:22:22.594602
1050 00:22:22.594675 Set Vref, RX VrefLevel [Byte0]: 59
1051 00:22:22.594738 [Byte1]: 59
1052 00:22:22.594786
1053 00:22:22.594834 Set Vref, RX VrefLevel [Byte0]: 60
1054 00:22:22.594882 [Byte1]: 60
1055 00:22:22.594930
1056 00:22:22.594977 Set Vref, RX VrefLevel [Byte0]: 61
1057 00:22:22.595025 [Byte1]: 61
1058 00:22:22.595099
1059 00:22:22.595150 Set Vref, RX VrefLevel [Byte0]: 62
1060 00:22:22.595199 [Byte1]: 62
1061 00:22:22.595248
1062 00:22:22.595297 Set Vref, RX VrefLevel [Byte0]: 63
1063 00:22:22.595346 [Byte1]: 63
1064 00:22:22.595394
1065 00:22:22.595442 Set Vref, RX VrefLevel [Byte0]: 64
1066 00:22:22.595490 [Byte1]: 64
1067 00:22:22.595539
1068 00:22:22.595587 Set Vref, RX VrefLevel [Byte0]: 65
1069 00:22:22.595636 [Byte1]: 65
1070 00:22:22.595683
1071 00:22:22.595731 Set Vref, RX VrefLevel [Byte0]: 66
1072 00:22:22.595779 [Byte1]: 66
1073 00:22:22.595827
1074 00:22:22.595874 Set Vref, RX VrefLevel [Byte0]: 67
1075 00:22:22.595923 [Byte1]: 67
1076 00:22:22.595971
1077 00:22:22.596019 Set Vref, RX VrefLevel [Byte0]: 68
1078 00:22:22.596067 [Byte1]: 68
1079 00:22:22.596115
1080 00:22:22.596163 Set Vref, RX VrefLevel [Byte0]: 69
1081 00:22:22.596212 [Byte1]: 69
1082 00:22:22.596260
1083 00:22:22.596307 Set Vref, RX VrefLevel [Byte0]: 70
1084 00:22:22.596355 [Byte1]: 70
1085 00:22:22.596403
1086 00:22:22.596450 Set Vref, RX VrefLevel [Byte0]: 71
1087 00:22:22.596499 [Byte1]: 71
1088 00:22:22.596547
1089 00:22:22.596595 Set Vref, RX VrefLevel [Byte0]: 72
1090 00:22:22.596648 [Byte1]: 72
1091 00:22:22.596734
1092 00:22:22.596782 Set Vref, RX VrefLevel [Byte0]: 73
1093 00:22:22.596831 [Byte1]: 73
1094 00:22:22.596879
1095 00:22:22.596927 Set Vref, RX VrefLevel [Byte0]: 74
1096 00:22:22.596975 [Byte1]: 74
1097 00:22:22.597023
1098 00:22:22.597260 Set Vref, RX VrefLevel [Byte0]: 75
1099 00:22:22.597314 [Byte1]: 75
1100 00:22:22.597365
1101 00:22:22.597413 Set Vref, RX VrefLevel [Byte0]: 76
1102 00:22:22.597462 [Byte1]: 76
1103 00:22:22.597511
1104 00:22:22.597559 Set Vref, RX VrefLevel [Byte0]: 77
1105 00:22:22.597607 [Byte1]: 77
1106 00:22:22.597656
1107 00:22:22.597704 Final RX Vref Byte 0 = 63 to rank0
1108 00:22:22.597753 Final RX Vref Byte 1 = 58 to rank0
1109 00:22:22.597801 Final RX Vref Byte 0 = 63 to rank1
1110 00:22:22.597850 Final RX Vref Byte 1 = 58 to rank1==
1111 00:22:22.597897 Dram Type= 6, Freq= 0, CH_0, rank 0
1112 00:22:22.597946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1113 00:22:22.597994 ==
1114 00:22:22.598043 DQS Delay:
1115 00:22:22.598092 DQS0 = 0, DQS1 = 0
1116 00:22:22.598141 DQM Delay:
1117 00:22:22.598204 DQM0 = 81, DQM1 = 67
1118 00:22:22.598259 DQ Delay:
1119 00:22:22.598307 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1120 00:22:22.598355 DQ4 =80, DQ5 =68, DQ6 =88, DQ7 =92
1121 00:22:22.598403 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1122 00:22:22.598452 DQ12 =72, DQ13 =68, DQ14 =76, DQ15 =76
1123 00:22:22.598501
1124 00:22:22.598548
1125 00:22:22.598596 [DQSOSCAuto] RK0, (LSB)MR18= 0x2a29, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
1126 00:22:22.598646 CH0 RK0: MR19=606, MR18=2A29
1127 00:22:22.598694 CH0_RK0: MR19=0x606, MR18=0x2A29, DQSOSC=399, MR23=63, INC=92, DEC=61
1128 00:22:22.598742
1129 00:22:22.598790 ----->DramcWriteLeveling(PI) begin...
1130 00:22:22.598838 ==
1131 00:22:22.598887 Dram Type= 6, Freq= 0, CH_0, rank 1
1132 00:22:22.598936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1133 00:22:22.598985 ==
1134 00:22:22.599033 Write leveling (Byte 0): 32 => 32
1135 00:22:22.599082 Write leveling (Byte 1): 31 => 31
1136 00:22:22.599131 DramcWriteLeveling(PI) end<-----
1137 00:22:22.599178
1138 00:22:22.599226 ==
1139 00:22:22.599274 Dram Type= 6, Freq= 0, CH_0, rank 1
1140 00:22:22.599322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1141 00:22:22.599370 ==
1142 00:22:22.599418 [Gating] SW mode calibration
1143 00:22:22.599467 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1144 00:22:22.599517 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1145 00:22:22.599566 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1146 00:22:22.599615 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1147 00:22:22.599663 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1148 00:22:22.599711 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1149 00:22:22.599759 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1150 00:22:22.599807 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1151 00:22:22.599868 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1152 00:22:22.599918 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 00:22:22.599966 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 00:22:22.600014 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 00:22:22.600063 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 00:22:22.600112 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 00:22:22.600160 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 00:22:22.600209 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 00:22:22.600257 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 00:22:22.600306 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 00:22:22.600354 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1162 00:22:22.600402 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1163 00:22:22.600451 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1164 00:22:22.600499 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 00:22:22.600548 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 00:22:22.600596 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 00:22:22.600715 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 00:22:22.600846 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 00:22:22.600967 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 00:22:22.601018 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 00:22:22.601067 0 9 8 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (1 1)
1172 00:22:22.601116 0 9 12 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
1173 00:22:22.601165 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1174 00:22:22.601213 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1175 00:22:22.601262 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1176 00:22:22.601311 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1177 00:22:22.601361 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1178 00:22:22.601410 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
1179 00:22:22.601459 0 10 8 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (1 0)
1180 00:22:22.601508 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 00:22:22.601557 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 00:22:22.601607 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 00:22:22.601656 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 00:22:22.601727 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 00:22:22.601778 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 00:22:22.601827 0 11 4 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
1187 00:22:22.601875 0 11 8 | B1->B0 | 2d2d 3c3c | 0 0 | (0 0) (0 0)
1188 00:22:22.601924 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1189 00:22:22.601973 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1190 00:22:22.602022 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1191 00:22:22.602071 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1192 00:22:22.602120 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1193 00:22:22.602168 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 00:22:22.602217 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1195 00:22:22.602265 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1196 00:22:22.602313 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1197 00:22:22.602362 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1198 00:22:22.602605 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 00:22:22.602660 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 00:22:22.602710 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 00:22:22.602760 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 00:22:22.602809 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 00:22:22.602857 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 00:22:22.602905 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 00:22:22.602954 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 00:22:22.603002 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 00:22:22.603052 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 00:22:22.603100 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 00:22:22.603149 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 00:22:22.603197 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 00:22:22.603246 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1212 00:22:22.603294 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1213 00:22:22.603342 Total UI for P1: 0, mck2ui 16
1214 00:22:22.603392 best dqsien dly found for B0: ( 0, 14, 8)
1215 00:22:22.603440 Total UI for P1: 0, mck2ui 16
1216 00:22:22.603489 best dqsien dly found for B1: ( 0, 14, 8)
1217 00:22:22.603537 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1218 00:22:22.603586 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1219 00:22:22.603634
1220 00:22:22.603683 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1221 00:22:22.603731 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1222 00:22:22.603780 [Gating] SW calibration Done
1223 00:22:22.603828 ==
1224 00:22:22.603877 Dram Type= 6, Freq= 0, CH_0, rank 1
1225 00:22:22.603925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1226 00:22:22.603974 ==
1227 00:22:22.604022 RX Vref Scan: 0
1228 00:22:22.604071
1229 00:22:22.604119 RX Vref 0 -> 0, step: 1
1230 00:22:22.604167
1231 00:22:22.604214 RX Delay -130 -> 252, step: 16
1232 00:22:22.604262 iDelay=222, Bit 0, Center 77 (-34 ~ 189) 224
1233 00:22:22.604312 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1234 00:22:22.604360 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1235 00:22:22.604409 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1236 00:22:22.604457 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1237 00:22:22.604505 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
1238 00:22:22.604554 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1239 00:22:22.604601 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1240 00:22:22.604675 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1241 00:22:22.604741 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1242 00:22:22.604790 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1243 00:22:22.604838 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1244 00:22:22.604886 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1245 00:22:22.604934 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1246 00:22:22.605007 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1247 00:22:22.605058 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1248 00:22:22.605106 ==
1249 00:22:22.605155 Dram Type= 6, Freq= 0, CH_0, rank 1
1250 00:22:22.605205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1251 00:22:22.605254 ==
1252 00:22:22.605303 DQS Delay:
1253 00:22:22.605351 DQS0 = 0, DQS1 = 0
1254 00:22:22.605400 DQM Delay:
1255 00:22:22.605448 DQM0 = 78, DQM1 = 69
1256 00:22:22.605496 DQ Delay:
1257 00:22:22.605543 DQ0 =77, DQ1 =85, DQ2 =69, DQ3 =69
1258 00:22:22.605591 DQ4 =85, DQ5 =61, DQ6 =85, DQ7 =93
1259 00:22:22.605639 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1260 00:22:22.605687 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1261 00:22:22.605737
1262 00:22:22.605785
1263 00:22:22.605832 ==
1264 00:22:22.605881 Dram Type= 6, Freq= 0, CH_0, rank 1
1265 00:22:22.605930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1266 00:22:22.605979 ==
1267 00:22:22.606027
1268 00:22:22.606074
1269 00:22:22.606122 TX Vref Scan disable
1270 00:22:22.606171 == TX Byte 0 ==
1271 00:22:22.606219 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1272 00:22:22.606268 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1273 00:22:22.606317 == TX Byte 1 ==
1274 00:22:22.606365 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1275 00:22:22.606414 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1276 00:22:22.606461 ==
1277 00:22:22.606509 Dram Type= 6, Freq= 0, CH_0, rank 1
1278 00:22:22.606557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1279 00:22:22.606606 ==
1280 00:22:22.606655 TX Vref=22, minBit 12, minWin=26, winSum=433
1281 00:22:22.606704 TX Vref=24, minBit 13, minWin=26, winSum=435
1282 00:22:22.606753 TX Vref=26, minBit 1, minWin=27, winSum=440
1283 00:22:22.606802 TX Vref=28, minBit 1, minWin=27, winSum=441
1284 00:22:22.606850 TX Vref=30, minBit 1, minWin=27, winSum=445
1285 00:22:22.606898 TX Vref=32, minBit 10, minWin=27, winSum=444
1286 00:22:22.606946 [TxChooseVref] Worse bit 1, Min win 27, Win sum 445, Final Vref 30
1287 00:22:22.606995
1288 00:22:22.607042 Final TX Range 1 Vref 30
1289 00:22:22.607091
1290 00:22:22.607140 ==
1291 00:22:22.607188 Dram Type= 6, Freq= 0, CH_0, rank 1
1292 00:22:22.607236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1293 00:22:22.607285 ==
1294 00:22:22.607334
1295 00:22:22.607380
1296 00:22:22.607427 TX Vref Scan disable
1297 00:22:22.607475 == TX Byte 0 ==
1298 00:22:22.607522 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1299 00:22:22.607571 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1300 00:22:22.607619 == TX Byte 1 ==
1301 00:22:22.607666 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1302 00:22:22.607713 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1303 00:22:22.607761
1304 00:22:22.607809 [DATLAT]
1305 00:22:22.607856 Freq=800, CH0 RK1
1306 00:22:22.607903
1307 00:22:22.607949 DATLAT Default: 0xa
1308 00:22:22.607997 0, 0xFFFF, sum = 0
1309 00:22:22.608046 1, 0xFFFF, sum = 0
1310 00:22:22.608094 2, 0xFFFF, sum = 0
1311 00:22:22.608143 3, 0xFFFF, sum = 0
1312 00:22:22.608190 4, 0xFFFF, sum = 0
1313 00:22:22.608239 5, 0xFFFF, sum = 0
1314 00:22:22.608311 6, 0xFFFF, sum = 0
1315 00:22:22.608362 7, 0xFFFF, sum = 0
1316 00:22:22.608411 8, 0xFFFF, sum = 0
1317 00:22:22.608459 9, 0x0, sum = 1
1318 00:22:22.608507 10, 0x0, sum = 2
1319 00:22:22.608554 11, 0x0, sum = 3
1320 00:22:22.608604 12, 0x0, sum = 4
1321 00:22:22.608677 best_step = 10
1322 00:22:22.608741
1323 00:22:22.608789 ==
1324 00:22:22.608837 Dram Type= 6, Freq= 0, CH_0, rank 1
1325 00:22:22.608885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1326 00:22:22.608933 ==
1327 00:22:22.608981 RX Vref Scan: 0
1328 00:22:22.609028
1329 00:22:22.609074 RX Vref 0 -> 0, step: 1
1330 00:22:22.609121
1331 00:22:22.609168 RX Delay -111 -> 252, step: 8
1332 00:22:22.609215 iDelay=209, Bit 0, Center 80 (-31 ~ 192) 224
1333 00:22:22.609452 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1334 00:22:22.609506 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1335 00:22:22.609555 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1336 00:22:22.609603 iDelay=209, Bit 4, Center 76 (-39 ~ 192) 232
1337 00:22:22.609652 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1338 00:22:22.609701 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
1339 00:22:22.609749 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1340 00:22:22.609796 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
1341 00:22:22.609844 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1342 00:22:22.609892 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1343 00:22:22.609940 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1344 00:22:22.609987 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
1345 00:22:22.610036 iDelay=209, Bit 13, Center 76 (-39 ~ 192) 232
1346 00:22:22.610084 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1347 00:22:22.610131 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
1348 00:22:22.610178 ==
1349 00:22:22.610226 Dram Type= 6, Freq= 0, CH_0, rank 1
1350 00:22:22.610274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1351 00:22:22.610323 ==
1352 00:22:22.610370 DQS Delay:
1353 00:22:22.610417 DQS0 = 0, DQS1 = 0
1354 00:22:22.610464 DQM Delay:
1355 00:22:22.610511 DQM0 = 79, DQM1 = 71
1356 00:22:22.610559 DQ Delay:
1357 00:22:22.610606 DQ0 =80, DQ1 =84, DQ2 =76, DQ3 =72
1358 00:22:22.610654 DQ4 =76, DQ5 =64, DQ6 =88, DQ7 =92
1359 00:22:22.610702 DQ8 =60, DQ9 =56, DQ10 =72, DQ11 =64
1360 00:22:22.610750 DQ12 =80, DQ13 =76, DQ14 =80, DQ15 =80
1361 00:22:22.610798
1362 00:22:22.610845
1363 00:22:22.610892 [DQSOSCAuto] RK1, (LSB)MR18= 0x4a25, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
1364 00:22:22.610941 CH0 RK1: MR19=606, MR18=4A25
1365 00:22:22.610988 CH0_RK1: MR19=0x606, MR18=0x4A25, DQSOSC=391, MR23=63, INC=96, DEC=64
1366 00:22:22.611037 [RxdqsGatingPostProcess] freq 800
1367 00:22:22.611084 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1368 00:22:22.611132 Pre-setting of DQS Precalculation
1369 00:22:22.611180 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1370 00:22:22.611229 ==
1371 00:22:22.611277 Dram Type= 6, Freq= 0, CH_1, rank 0
1372 00:22:22.611325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1373 00:22:22.611374 ==
1374 00:22:22.611422 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1375 00:22:22.611470 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1376 00:22:22.611520 [CA 0] Center 36 (6~67) winsize 62
1377 00:22:22.611568 [CA 1] Center 36 (6~67) winsize 62
1378 00:22:22.611618 [CA 2] Center 34 (4~64) winsize 61
1379 00:22:22.611686 [CA 3] Center 34 (4~64) winsize 61
1380 00:22:22.611735 [CA 4] Center 34 (4~64) winsize 61
1381 00:22:22.611783 [CA 5] Center 33 (3~64) winsize 62
1382 00:22:22.611832
1383 00:22:22.611880 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1384 00:22:22.611928
1385 00:22:22.611975 [CATrainingPosCal] consider 1 rank data
1386 00:22:22.612024 u2DelayCellTimex100 = 270/100 ps
1387 00:22:22.612073 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1388 00:22:22.612122 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1389 00:22:22.612170 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1390 00:22:22.612218 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1391 00:22:22.612266 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
1392 00:22:22.612346 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1393 00:22:22.612394
1394 00:22:22.612442 CA PerBit enable=1, Macro0, CA PI delay=33
1395 00:22:22.612489
1396 00:22:22.612536 [CBTSetCACLKResult] CA Dly = 33
1397 00:22:22.612584 CS Dly: 5 (0~36)
1398 00:22:22.612632 ==
1399 00:22:22.612722 Dram Type= 6, Freq= 0, CH_1, rank 1
1400 00:22:22.612771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1401 00:22:22.612820 ==
1402 00:22:22.612868 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1403 00:22:22.612917 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1404 00:22:22.612965 [CA 0] Center 37 (7~67) winsize 61
1405 00:22:22.613012 [CA 1] Center 36 (6~67) winsize 62
1406 00:22:22.613059 [CA 2] Center 35 (5~65) winsize 61
1407 00:22:22.613106 [CA 3] Center 33 (3~64) winsize 62
1408 00:22:22.613154 [CA 4] Center 34 (4~65) winsize 62
1409 00:22:22.613201 [CA 5] Center 33 (3~64) winsize 62
1410 00:22:22.613248
1411 00:22:22.613295 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1412 00:22:22.613374
1413 00:22:22.613421 [CATrainingPosCal] consider 2 rank data
1414 00:22:22.613469 u2DelayCellTimex100 = 270/100 ps
1415 00:22:22.613518 CA0 delay=37 (7~67),Diff = 4 PI (28 cell)
1416 00:22:22.613565 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1417 00:22:22.613612 CA2 delay=34 (5~64),Diff = 1 PI (7 cell)
1418 00:22:22.613661 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1419 00:22:22.613708 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
1420 00:22:22.613756 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1421 00:22:22.613803
1422 00:22:22.613850 CA PerBit enable=1, Macro0, CA PI delay=33
1423 00:22:22.613898
1424 00:22:22.613944 [CBTSetCACLKResult] CA Dly = 33
1425 00:22:22.613992 CS Dly: 5 (0~37)
1426 00:22:22.614039
1427 00:22:22.614086 ----->DramcWriteLeveling(PI) begin...
1428 00:22:22.614135 ==
1429 00:22:22.614184 Dram Type= 6, Freq= 0, CH_1, rank 0
1430 00:22:22.614232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1431 00:22:22.614280 ==
1432 00:22:22.614327 Write leveling (Byte 0): 28 => 28
1433 00:22:22.614400 Write leveling (Byte 1): 32 => 32
1434 00:22:22.614462 DramcWriteLeveling(PI) end<-----
1435 00:22:22.614510
1436 00:22:22.614557 ==
1437 00:22:22.614604 Dram Type= 6, Freq= 0, CH_1, rank 0
1438 00:22:22.614652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1439 00:22:22.614699 ==
1440 00:22:22.614746 [Gating] SW mode calibration
1441 00:22:22.614794 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1442 00:22:22.614843 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1443 00:22:22.614892 0 6 0 | B1->B0 | 2323 2322 | 0 1 | (1 1) (1 1)
1444 00:22:22.614940 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1445 00:22:22.614988 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1446 00:22:22.615048 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1447 00:22:22.615104 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1448 00:22:22.615153 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1449 00:22:22.615201 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 00:22:22.615440 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 00:22:22.615494 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 00:22:22.615543 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 00:22:22.615593 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 00:22:22.615641 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 00:22:22.615689 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 00:22:22.615737 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 00:22:22.615785 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 00:22:22.615832 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 00:22:22.615879 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 00:22:22.615927 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1461 00:22:22.615976 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1462 00:22:22.616024 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 00:22:22.616072 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 00:22:22.616119 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 00:22:22.616168 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 00:22:22.616215 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 00:22:22.616263 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 00:22:22.616310 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 00:22:22.616358 0 9 8 | B1->B0 | 2a2a 2c2c | 0 0 | (0 0) (0 0)
1470 00:22:22.616405 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1471 00:22:22.616454 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1472 00:22:22.616501 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1473 00:22:22.616549 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1474 00:22:22.616596 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1475 00:22:22.616650 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1476 00:22:22.616704 0 10 4 | B1->B0 | 3333 3434 | 0 0 | (0 0) (0 1)
1477 00:22:22.616753 0 10 8 | B1->B0 | 2f2f 2c2c | 0 0 | (0 1) (1 0)
1478 00:22:22.616801 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 00:22:22.616848 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 00:22:22.616896 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 00:22:22.616943 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 00:22:22.616991 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 00:22:22.617038 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 00:22:22.617085 0 11 4 | B1->B0 | 2727 2626 | 0 0 | (0 0) (0 0)
1485 00:22:22.617133 0 11 8 | B1->B0 | 3939 3939 | 0 0 | (0 0) (0 0)
1486 00:22:22.617181 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1487 00:22:22.617229 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1488 00:22:22.617277 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1489 00:22:22.617325 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1490 00:22:22.617372 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1491 00:22:22.617420 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1492 00:22:22.617467 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 00:22:22.617514 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1494 00:22:22.617561 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1495 00:22:22.617609 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1496 00:22:22.617657 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1497 00:22:22.617704 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 00:22:22.617751 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 00:22:22.617799 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 00:22:22.617846 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 00:22:22.617910 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 00:22:22.617960 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 00:22:22.618008 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 00:22:22.618056 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 00:22:22.618104 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 00:22:22.618151 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 00:22:22.618199 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 00:22:22.618268 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1509 00:22:22.618320 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1510 00:22:22.618368 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1511 00:22:22.618416 Total UI for P1: 0, mck2ui 16
1512 00:22:22.618465 best dqsien dly found for B0: ( 0, 14, 6)
1513 00:22:22.618515 Total UI for P1: 0, mck2ui 16
1514 00:22:22.618563 best dqsien dly found for B1: ( 0, 14, 6)
1515 00:22:22.618611 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1516 00:22:22.618659 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1517 00:22:22.618706
1518 00:22:22.618753 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1519 00:22:22.618800 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1520 00:22:22.618849 [Gating] SW calibration Done
1521 00:22:22.618898 ==
1522 00:22:22.618946 Dram Type= 6, Freq= 0, CH_1, rank 0
1523 00:22:22.618994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1524 00:22:22.619041 ==
1525 00:22:22.619089 RX Vref Scan: 0
1526 00:22:22.619136
1527 00:22:22.619183 RX Vref 0 -> 0, step: 1
1528 00:22:22.619230
1529 00:22:22.619277 RX Delay -130 -> 252, step: 16
1530 00:22:22.619326 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1531 00:22:22.619374 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1532 00:22:22.619422 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1533 00:22:22.619502 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1534 00:22:22.619616 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1535 00:22:22.619664 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1536 00:22:22.619712 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1537 00:22:22.619759 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1538 00:22:22.619806 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1539 00:22:22.619854 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1540 00:22:22.620091 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1541 00:22:22.620149 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1542 00:22:22.620199 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1543 00:22:22.620247 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1544 00:22:22.620295 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1545 00:22:22.620343 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1546 00:22:22.620390 ==
1547 00:22:22.620439 Dram Type= 6, Freq= 0, CH_1, rank 0
1548 00:22:22.620487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1549 00:22:22.620536 ==
1550 00:22:22.620583 DQS Delay:
1551 00:22:22.620630 DQS0 = 0, DQS1 = 0
1552 00:22:22.620721 DQM Delay:
1553 00:22:22.620768 DQM0 = 81, DQM1 = 70
1554 00:22:22.620815 DQ Delay:
1555 00:22:22.620862 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1556 00:22:22.620910 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1557 00:22:22.620958 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
1558 00:22:22.621005 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1559 00:22:22.621052
1560 00:22:22.621099
1561 00:22:22.621146 ==
1562 00:22:22.621194 Dram Type= 6, Freq= 0, CH_1, rank 0
1563 00:22:22.621242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1564 00:22:22.621289 ==
1565 00:22:22.621336
1566 00:22:22.621383
1567 00:22:22.621430 TX Vref Scan disable
1568 00:22:22.621477 == TX Byte 0 ==
1569 00:22:22.621525 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1570 00:22:22.621572 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1571 00:22:22.621619 == TX Byte 1 ==
1572 00:22:22.621666 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1573 00:22:22.621740 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1574 00:22:22.621790 ==
1575 00:22:22.621838 Dram Type= 6, Freq= 0, CH_1, rank 0
1576 00:22:22.621887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1577 00:22:22.621936 ==
1578 00:22:22.621984 TX Vref=22, minBit 1, minWin=27, winSum=440
1579 00:22:22.622032 TX Vref=24, minBit 1, minWin=27, winSum=440
1580 00:22:22.622080 TX Vref=26, minBit 1, minWin=27, winSum=443
1581 00:22:22.622129 TX Vref=28, minBit 5, minWin=27, winSum=444
1582 00:22:22.622177 TX Vref=30, minBit 1, minWin=27, winSum=445
1583 00:22:22.622225 TX Vref=32, minBit 6, minWin=27, winSum=448
1584 00:22:22.622272 [TxChooseVref] Worse bit 6, Min win 27, Win sum 448, Final Vref 32
1585 00:22:22.622321
1586 00:22:22.622368 Final TX Range 1 Vref 32
1587 00:22:22.622416
1588 00:22:22.622462 ==
1589 00:22:22.622510 Dram Type= 6, Freq= 0, CH_1, rank 0
1590 00:22:22.622557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1591 00:22:22.622606 ==
1592 00:22:22.622652
1593 00:22:22.622699
1594 00:22:22.622745 TX Vref Scan disable
1595 00:22:22.622793 == TX Byte 0 ==
1596 00:22:22.622840 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1597 00:22:22.622889 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1598 00:22:22.622937 == TX Byte 1 ==
1599 00:22:22.622985 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1600 00:22:22.623032 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1601 00:22:22.623080
1602 00:22:22.623128 [DATLAT]
1603 00:22:22.623175 Freq=800, CH1 RK0
1604 00:22:22.623223
1605 00:22:22.623270 DATLAT Default: 0xa
1606 00:22:22.623318 0, 0xFFFF, sum = 0
1607 00:22:22.623366 1, 0xFFFF, sum = 0
1608 00:22:22.623415 2, 0xFFFF, sum = 0
1609 00:22:22.623463 3, 0xFFFF, sum = 0
1610 00:22:22.623511 4, 0xFFFF, sum = 0
1611 00:22:22.623560 5, 0xFFFF, sum = 0
1612 00:22:22.623608 6, 0xFFFF, sum = 0
1613 00:22:22.623656 7, 0xFFFF, sum = 0
1614 00:22:22.623705 8, 0xFFFF, sum = 0
1615 00:22:22.623753 9, 0x0, sum = 1
1616 00:22:22.623801 10, 0x0, sum = 2
1617 00:22:22.623849 11, 0x0, sum = 3
1618 00:22:22.623898 12, 0x0, sum = 4
1619 00:22:22.623947 best_step = 10
1620 00:22:22.623994
1621 00:22:22.624041 ==
1622 00:22:22.624089 Dram Type= 6, Freq= 0, CH_1, rank 0
1623 00:22:22.624137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1624 00:22:22.624185 ==
1625 00:22:22.624233 RX Vref Scan: 1
1626 00:22:22.624281
1627 00:22:22.624328 Set Vref Range= 32 -> 127
1628 00:22:22.624376
1629 00:22:22.624449 RX Vref 32 -> 127, step: 1
1630 00:22:22.624510
1631 00:22:22.624557 RX Delay -111 -> 252, step: 8
1632 00:22:22.624605
1633 00:22:22.624680 Set Vref, RX VrefLevel [Byte0]: 32
1634 00:22:22.624764 [Byte1]: 32
1635 00:22:22.624815
1636 00:22:22.624862 Set Vref, RX VrefLevel [Byte0]: 33
1637 00:22:22.624910 [Byte1]: 33
1638 00:22:22.624958
1639 00:22:22.625005 Set Vref, RX VrefLevel [Byte0]: 34
1640 00:22:22.625053 [Byte1]: 34
1641 00:22:22.625101
1642 00:22:22.625148 Set Vref, RX VrefLevel [Byte0]: 35
1643 00:22:22.625196 [Byte1]: 35
1644 00:22:22.625243
1645 00:22:22.625290 Set Vref, RX VrefLevel [Byte0]: 36
1646 00:22:22.625338 [Byte1]: 36
1647 00:22:22.625390
1648 00:22:22.625438 Set Vref, RX VrefLevel [Byte0]: 37
1649 00:22:22.625485 [Byte1]: 37
1650 00:22:22.625533
1651 00:22:22.625579 Set Vref, RX VrefLevel [Byte0]: 38
1652 00:22:22.625627 [Byte1]: 38
1653 00:22:22.625674
1654 00:22:22.625722 Set Vref, RX VrefLevel [Byte0]: 39
1655 00:22:22.625770 [Byte1]: 39
1656 00:22:22.625817
1657 00:22:22.625864 Set Vref, RX VrefLevel [Byte0]: 40
1658 00:22:22.625913 [Byte1]: 40
1659 00:22:22.625959
1660 00:22:22.626006 Set Vref, RX VrefLevel [Byte0]: 41
1661 00:22:22.626053 [Byte1]: 41
1662 00:22:22.626101
1663 00:22:22.626148 Set Vref, RX VrefLevel [Byte0]: 42
1664 00:22:22.626195 [Byte1]: 42
1665 00:22:22.626242
1666 00:22:22.626289 Set Vref, RX VrefLevel [Byte0]: 43
1667 00:22:22.626336 [Byte1]: 43
1668 00:22:22.626384
1669 00:22:22.626431 Set Vref, RX VrefLevel [Byte0]: 44
1670 00:22:22.626478 [Byte1]: 44
1671 00:22:22.626525
1672 00:22:22.626571 Set Vref, RX VrefLevel [Byte0]: 45
1673 00:22:22.626619 [Byte1]: 45
1674 00:22:22.626667
1675 00:22:22.626715 Set Vref, RX VrefLevel [Byte0]: 46
1676 00:22:22.626762 [Byte1]: 46
1677 00:22:22.626809
1678 00:22:22.626872 Set Vref, RX VrefLevel [Byte0]: 47
1679 00:22:22.626922 [Byte1]: 47
1680 00:22:22.626970
1681 00:22:22.627018 Set Vref, RX VrefLevel [Byte0]: 48
1682 00:22:22.627066 [Byte1]: 48
1683 00:22:22.627114
1684 00:22:22.627161 Set Vref, RX VrefLevel [Byte0]: 49
1685 00:22:22.627209 [Byte1]: 49
1686 00:22:22.627257
1687 00:22:22.627305 Set Vref, RX VrefLevel [Byte0]: 50
1688 00:22:22.627352 [Byte1]: 50
1689 00:22:22.627401
1690 00:22:22.627449 Set Vref, RX VrefLevel [Byte0]: 51
1691 00:22:22.627496 [Byte1]: 51
1692 00:22:22.627543
1693 00:22:22.627590 Set Vref, RX VrefLevel [Byte0]: 52
1694 00:22:22.627638 [Byte1]: 52
1695 00:22:22.627686
1696 00:22:22.627733 Set Vref, RX VrefLevel [Byte0]: 53
1697 00:22:22.627781 [Byte1]: 53
1698 00:22:22.627829
1699 00:22:22.627875 Set Vref, RX VrefLevel [Byte0]: 54
1700 00:22:22.627922 [Byte1]: 54
1701 00:22:22.627969
1702 00:22:22.628016 Set Vref, RX VrefLevel [Byte0]: 55
1703 00:22:22.628064 [Byte1]: 55
1704 00:22:22.628119
1705 00:22:22.628369 Set Vref, RX VrefLevel [Byte0]: 56
1706 00:22:22.628426 [Byte1]: 56
1707 00:22:22.628476
1708 00:22:22.628523 Set Vref, RX VrefLevel [Byte0]: 57
1709 00:22:22.628572 [Byte1]: 57
1710 00:22:22.628620
1711 00:22:22.628701 Set Vref, RX VrefLevel [Byte0]: 58
1712 00:22:22.628765 [Byte1]: 58
1713 00:22:22.628813
1714 00:22:22.628860 Set Vref, RX VrefLevel [Byte0]: 59
1715 00:22:22.628908 [Byte1]: 59
1716 00:22:22.628955
1717 00:22:22.629003 Set Vref, RX VrefLevel [Byte0]: 60
1718 00:22:22.629051 [Byte1]: 60
1719 00:22:22.629099
1720 00:22:22.629145 Set Vref, RX VrefLevel [Byte0]: 61
1721 00:22:22.629193 [Byte1]: 61
1722 00:22:22.629241
1723 00:22:22.629289 Set Vref, RX VrefLevel [Byte0]: 62
1724 00:22:22.629337 [Byte1]: 62
1725 00:22:22.629384
1726 00:22:22.629431 Set Vref, RX VrefLevel [Byte0]: 63
1727 00:22:22.629480 [Byte1]: 63
1728 00:22:22.629527
1729 00:22:22.629574 Set Vref, RX VrefLevel [Byte0]: 64
1730 00:22:22.629621 [Byte1]: 64
1731 00:22:22.629670
1732 00:22:22.629719 Set Vref, RX VrefLevel [Byte0]: 65
1733 00:22:22.629767 [Byte1]: 65
1734 00:22:22.629815
1735 00:22:22.629862 Set Vref, RX VrefLevel [Byte0]: 66
1736 00:22:22.629909 [Byte1]: 66
1737 00:22:22.629957
1738 00:22:22.630004 Set Vref, RX VrefLevel [Byte0]: 67
1739 00:22:22.630050 [Byte1]: 67
1740 00:22:22.630097
1741 00:22:22.630144 Set Vref, RX VrefLevel [Byte0]: 68
1742 00:22:22.630192 [Byte1]: 68
1743 00:22:22.630239
1744 00:22:22.630286 Set Vref, RX VrefLevel [Byte0]: 69
1745 00:22:22.630333 [Byte1]: 69
1746 00:22:22.630381
1747 00:22:22.630427 Set Vref, RX VrefLevel [Byte0]: 70
1748 00:22:22.630475 [Byte1]: 70
1749 00:22:22.630522
1750 00:22:22.630568 Set Vref, RX VrefLevel [Byte0]: 71
1751 00:22:22.630616 [Byte1]: 71
1752 00:22:22.630663
1753 00:22:22.630710 Set Vref, RX VrefLevel [Byte0]: 72
1754 00:22:22.630757 [Byte1]: 72
1755 00:22:22.630804
1756 00:22:22.630851 Set Vref, RX VrefLevel [Byte0]: 73
1757 00:22:22.630899 [Byte1]: 73
1758 00:22:22.630947
1759 00:22:22.630994 Final RX Vref Byte 0 = 61 to rank0
1760 00:22:22.631042 Final RX Vref Byte 1 = 56 to rank0
1761 00:22:22.631090 Final RX Vref Byte 0 = 61 to rank1
1762 00:22:22.631138 Final RX Vref Byte 1 = 56 to rank1==
1763 00:22:22.631186 Dram Type= 6, Freq= 0, CH_1, rank 0
1764 00:22:22.631234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1765 00:22:22.631283 ==
1766 00:22:22.631331 DQS Delay:
1767 00:22:22.631379 DQS0 = 0, DQS1 = 0
1768 00:22:22.631426 DQM Delay:
1769 00:22:22.631473 DQM0 = 81, DQM1 = 71
1770 00:22:22.631532 DQ Delay:
1771 00:22:22.631589 DQ0 =88, DQ1 =76, DQ2 =68, DQ3 =76
1772 00:22:22.631638 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
1773 00:22:22.631688 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =68
1774 00:22:22.631736 DQ12 =80, DQ13 =80, DQ14 =76, DQ15 =76
1775 00:22:22.631783
1776 00:22:22.631830
1777 00:22:22.631877 [DQSOSCAuto] RK0, (LSB)MR18= 0x131d, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 405 ps
1778 00:22:22.631925 CH1 RK0: MR19=606, MR18=131D
1779 00:22:22.631973 CH1_RK0: MR19=0x606, MR18=0x131D, DQSOSC=402, MR23=63, INC=91, DEC=60
1780 00:22:22.632021
1781 00:22:22.632069 ----->DramcWriteLeveling(PI) begin...
1782 00:22:22.632117 ==
1783 00:22:22.632164 Dram Type= 6, Freq= 0, CH_1, rank 1
1784 00:22:22.632213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1785 00:22:22.632260 ==
1786 00:22:22.632308 Write leveling (Byte 0): 27 => 27
1787 00:22:22.632356 Write leveling (Byte 1): 28 => 28
1788 00:22:22.632404 DramcWriteLeveling(PI) end<-----
1789 00:22:22.632451
1790 00:22:22.632498 ==
1791 00:22:22.632546 Dram Type= 6, Freq= 0, CH_1, rank 1
1792 00:22:22.632593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1793 00:22:22.632641 ==
1794 00:22:22.632701 [Gating] SW mode calibration
1795 00:22:22.632750 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1796 00:22:22.632798 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1797 00:22:22.632847 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1798 00:22:22.632894 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1799 00:22:22.632942 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1800 00:22:22.632990 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1801 00:22:22.633037 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1802 00:22:22.633085 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1803 00:22:22.633133 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1804 00:22:22.633181 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1805 00:22:22.633228 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 00:22:22.633275 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 00:22:22.633324 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 00:22:22.633372 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 00:22:22.633419 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 00:22:22.633467 0 7 20 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
1811 00:22:22.633515 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 00:22:22.633563 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 00:22:22.633624 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 00:22:22.633673 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1815 00:22:22.633721 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 00:22:22.633769 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1817 00:22:22.633818 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 00:22:22.633866 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 00:22:22.633913 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 00:22:22.633961 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 00:22:22.634009 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 00:22:22.634057 0 9 4 | B1->B0 | 2323 2b2b | 0 1 | (1 1) (1 1)
1823 00:22:22.634104 0 9 8 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
1824 00:22:22.634151 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1825 00:22:22.634199 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1826 00:22:22.634247 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1827 00:22:22.634482 0 9 24 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
1828 00:22:22.634536 0 9 28 | B1->B0 | 3434 3534 | 1 1 | (1 1) (0 0)
1829 00:22:22.634584 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1830 00:22:22.634632 0 10 4 | B1->B0 | 3131 2c2c | 0 1 | (1 0) (1 0)
1831 00:22:22.634679 0 10 8 | B1->B0 | 2626 2423 | 0 1 | (0 0) (0 0)
1832 00:22:22.634727 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 00:22:22.634823 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 00:22:22.634961 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 00:22:22.635025 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 00:22:22.635074 0 10 28 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
1837 00:22:22.635121 0 11 0 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
1838 00:22:22.635169 0 11 4 | B1->B0 | 2929 3838 | 0 1 | (0 0) (0 0)
1839 00:22:22.635217 0 11 8 | B1->B0 | 3f3f 4646 | 1 0 | (0 0) (0 0)
1840 00:22:22.635265 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1841 00:22:22.635313 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1842 00:22:22.635361 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1843 00:22:22.635410 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1844 00:22:22.635458 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1845 00:22:22.635505 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1846 00:22:22.635552 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1847 00:22:22.635599 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1848 00:22:22.635647 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1849 00:22:22.635695 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1850 00:22:22.635743 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1851 00:22:22.635791 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1852 00:22:22.635838 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1853 00:22:22.635886 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 00:22:22.635934 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 00:22:22.635982 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 00:22:22.636030 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 00:22:22.636078 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 00:22:22.636126 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 00:22:22.636174 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 00:22:22.636222 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 00:22:22.636270 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 00:22:22.636317 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1863 00:22:22.636365 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1864 00:22:22.636413 Total UI for P1: 0, mck2ui 16
1865 00:22:22.636462 best dqsien dly found for B0: ( 0, 14, 4)
1866 00:22:22.636510 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1867 00:22:22.636558 Total UI for P1: 0, mck2ui 16
1868 00:22:22.636606 best dqsien dly found for B1: ( 0, 14, 8)
1869 00:22:22.636685 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1870 00:22:22.636752 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1871 00:22:22.636799
1872 00:22:22.636846 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1873 00:22:22.636894 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1874 00:22:22.636942 [Gating] SW calibration Done
1875 00:22:22.636990 ==
1876 00:22:22.637038 Dram Type= 6, Freq= 0, CH_1, rank 1
1877 00:22:22.637086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1878 00:22:22.637135 ==
1879 00:22:22.637183 RX Vref Scan: 0
1880 00:22:22.637231
1881 00:22:22.637278 RX Vref 0 -> 0, step: 1
1882 00:22:22.637325
1883 00:22:22.637372 RX Delay -130 -> 252, step: 16
1884 00:22:22.637420 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1885 00:22:22.637468 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1886 00:22:22.637517 iDelay=222, Bit 2, Center 61 (-66 ~ 189) 256
1887 00:22:22.637564 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1888 00:22:22.637612 iDelay=222, Bit 4, Center 69 (-50 ~ 189) 240
1889 00:22:22.637659 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1890 00:22:22.637707 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1891 00:22:22.637755 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1892 00:22:22.637802 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1893 00:22:22.637849 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1894 00:22:22.637897 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1895 00:22:22.637945 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1896 00:22:22.637993 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1897 00:22:22.638040 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1898 00:22:22.638088 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1899 00:22:22.638135 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1900 00:22:22.638182 ==
1901 00:22:22.638258 Dram Type= 6, Freq= 0, CH_1, rank 1
1902 00:22:22.638311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1903 00:22:22.638360 ==
1904 00:22:22.638407 DQS Delay:
1905 00:22:22.638455 DQS0 = 0, DQS1 = 0
1906 00:22:22.638503 DQM Delay:
1907 00:22:22.638551 DQM0 = 77, DQM1 = 71
1908 00:22:22.638598 DQ Delay:
1909 00:22:22.638646 DQ0 =85, DQ1 =69, DQ2 =61, DQ3 =77
1910 00:22:22.638693 DQ4 =69, DQ5 =85, DQ6 =93, DQ7 =77
1911 00:22:22.638741 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =61
1912 00:22:22.638789 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1913 00:22:22.638849
1914 00:22:22.638898
1915 00:22:22.638945 ==
1916 00:22:22.638993 Dram Type= 6, Freq= 0, CH_1, rank 1
1917 00:22:22.639041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1918 00:22:22.889685 ==
1919 00:22:22.889897
1920 00:22:22.890002
1921 00:22:22.890069 TX Vref Scan disable
1922 00:22:22.890124 == TX Byte 0 ==
1923 00:22:22.890176 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1924 00:22:22.890228 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1925 00:22:22.890279 == TX Byte 1 ==
1926 00:22:22.890328 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1927 00:22:22.890378 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1928 00:22:22.890427 ==
1929 00:22:22.890476 Dram Type= 6, Freq= 0, CH_1, rank 1
1930 00:22:22.890525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1931 00:22:22.890575 ==
1932 00:22:22.890623 TX Vref=22, minBit 0, minWin=28, winSum=452
1933 00:22:22.890674 TX Vref=24, minBit 1, minWin=28, winSum=454
1934 00:22:22.890723 TX Vref=26, minBit 0, minWin=28, winSum=457
1935 00:22:22.890971 TX Vref=28, minBit 1, minWin=28, winSum=461
1936 00:22:22.891026 TX Vref=30, minBit 5, minWin=27, winSum=461
1937 00:22:22.891076 TX Vref=32, minBit 0, minWin=28, winSum=460
1938 00:22:22.891126 [TxChooseVref] Worse bit 1, Min win 28, Win sum 461, Final Vref 28
1939 00:22:22.891182
1940 00:22:22.891232 Final TX Range 1 Vref 28
1941 00:22:22.891281
1942 00:22:22.891329 ==
1943 00:22:22.891377 Dram Type= 6, Freq= 0, CH_1, rank 1
1944 00:22:22.891425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1945 00:22:22.891474 ==
1946 00:22:22.891521
1947 00:22:22.891568
1948 00:22:22.891614 TX Vref Scan disable
1949 00:22:22.891662 == TX Byte 0 ==
1950 00:22:22.891714 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1951 00:22:22.891764 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1952 00:22:22.891838 == TX Byte 1 ==
1953 00:22:22.892032 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1954 00:22:22.892122 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1955 00:22:22.892192
1956 00:22:22.892242 [DATLAT]
1957 00:22:22.892290 Freq=800, CH1 RK1
1958 00:22:22.892344
1959 00:22:22.892421 DATLAT Default: 0xa
1960 00:22:22.892496 0, 0xFFFF, sum = 0
1961 00:22:22.892583 1, 0xFFFF, sum = 0
1962 00:22:22.892698 2, 0xFFFF, sum = 0
1963 00:22:22.892750 3, 0xFFFF, sum = 0
1964 00:22:22.892800 4, 0xFFFF, sum = 0
1965 00:22:22.892849 5, 0xFFFF, sum = 0
1966 00:22:22.892898 6, 0xFFFF, sum = 0
1967 00:22:22.892946 7, 0xFFFF, sum = 0
1968 00:22:22.892994 8, 0xFFFF, sum = 0
1969 00:22:22.893042 9, 0x0, sum = 1
1970 00:22:22.893091 10, 0x0, sum = 2
1971 00:22:22.893143 11, 0x0, sum = 3
1972 00:22:22.893193 12, 0x0, sum = 4
1973 00:22:22.893242 best_step = 10
1974 00:22:22.893290
1975 00:22:22.893337 ==
1976 00:22:22.893385 Dram Type= 6, Freq= 0, CH_1, rank 1
1977 00:22:22.893433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1978 00:22:22.893482 ==
1979 00:22:22.893530 RX Vref Scan: 0
1980 00:22:22.893577
1981 00:22:22.893625 RX Vref 0 -> 0, step: 1
1982 00:22:22.893673
1983 00:22:22.893720 RX Delay -111 -> 252, step: 8
1984 00:22:22.893768 iDelay=209, Bit 0, Center 84 (-39 ~ 208) 248
1985 00:22:22.893817 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
1986 00:22:22.893865 iDelay=209, Bit 2, Center 68 (-55 ~ 192) 248
1987 00:22:22.893912 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1988 00:22:22.893960 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
1989 00:22:22.894008 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
1990 00:22:22.894056 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
1991 00:22:22.894104 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
1992 00:22:22.894152 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
1993 00:22:22.894200 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
1994 00:22:22.894247 iDelay=209, Bit 10, Center 80 (-39 ~ 200) 240
1995 00:22:22.894294 iDelay=209, Bit 11, Center 68 (-55 ~ 192) 248
1996 00:22:22.894342 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
1997 00:22:22.894390 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
1998 00:22:22.894438 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1999 00:22:22.894486 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2000 00:22:22.894533 ==
2001 00:22:22.894581 Dram Type= 6, Freq= 0, CH_1, rank 1
2002 00:22:22.894629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2003 00:22:22.894678 ==
2004 00:22:22.894725 DQS Delay:
2005 00:22:22.894772 DQS0 = 0, DQS1 = 0
2006 00:22:22.894819 DQM Delay:
2007 00:22:22.894867 DQM0 = 78, DQM1 = 74
2008 00:22:22.894914 DQ Delay:
2009 00:22:22.894962 DQ0 =84, DQ1 =72, DQ2 =68, DQ3 =72
2010 00:22:22.895009 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2011 00:22:22.895056 DQ8 =60, DQ9 =64, DQ10 =80, DQ11 =68
2012 00:22:22.895104 DQ12 =84, DQ13 =80, DQ14 =80, DQ15 =80
2013 00:22:22.895152
2014 00:22:22.895199
2015 00:22:22.895246 [DQSOSCAuto] RK1, (LSB)MR18= 0x223a, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 401 ps
2016 00:22:22.895295 CH1 RK1: MR19=606, MR18=223A
2017 00:22:22.895344 CH1_RK1: MR19=0x606, MR18=0x223A, DQSOSC=395, MR23=63, INC=94, DEC=63
2018 00:22:22.895393 [RxdqsGatingPostProcess] freq 800
2019 00:22:22.895441 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2020 00:22:22.895490 Pre-setting of DQS Precalculation
2021 00:22:22.895537 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2022 00:22:22.895586 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2023 00:22:22.895635 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2024 00:22:22.895683
2025 00:22:22.895730
2026 00:22:22.895778 [Calibration Summary] 1600 Mbps
2027 00:22:22.895826 CH 0, Rank 0
2028 00:22:22.895873 SW Impedance : PASS
2029 00:22:22.895924 DUTY Scan : NO K
2030 00:22:22.895990 ZQ Calibration : PASS
2031 00:22:22.896040 Jitter Meter : NO K
2032 00:22:22.896088 CBT Training : PASS
2033 00:22:22.896136 Write leveling : PASS
2034 00:22:22.896184 RX DQS gating : PASS
2035 00:22:22.896231 RX DQ/DQS(RDDQC) : PASS
2036 00:22:22.896279 TX DQ/DQS : PASS
2037 00:22:22.896327 RX DATLAT : PASS
2038 00:22:22.896375 RX DQ/DQS(Engine): PASS
2039 00:22:22.896423 TX OE : NO K
2040 00:22:22.896471 All Pass.
2041 00:22:22.896519
2042 00:22:22.896566 CH 0, Rank 1
2043 00:22:22.896614 SW Impedance : PASS
2044 00:22:22.896693 DUTY Scan : NO K
2045 00:22:22.896760 ZQ Calibration : PASS
2046 00:22:22.896808 Jitter Meter : NO K
2047 00:22:22.896856 CBT Training : PASS
2048 00:22:22.896903 Write leveling : PASS
2049 00:22:22.896951 RX DQS gating : PASS
2050 00:22:22.896998 RX DQ/DQS(RDDQC) : PASS
2051 00:22:22.897046 TX DQ/DQS : PASS
2052 00:22:22.897094 RX DATLAT : PASS
2053 00:22:22.897141 RX DQ/DQS(Engine): PASS
2054 00:22:22.897188 TX OE : NO K
2055 00:22:22.897237 All Pass.
2056 00:22:22.897284
2057 00:22:22.897331 CH 1, Rank 0
2058 00:22:22.897379 SW Impedance : PASS
2059 00:22:22.897427 DUTY Scan : NO K
2060 00:22:22.897475 ZQ Calibration : PASS
2061 00:22:22.897540 Jitter Meter : NO K
2062 00:22:22.897618 CBT Training : PASS
2063 00:22:22.897675 Write leveling : PASS
2064 00:22:22.897740 RX DQS gating : PASS
2065 00:22:22.897788 RX DQ/DQS(RDDQC) : PASS
2066 00:22:22.897836 TX DQ/DQS : PASS
2067 00:22:22.897884 RX DATLAT : PASS
2068 00:22:22.897932 RX DQ/DQS(Engine): PASS
2069 00:22:22.898010 TX OE : NO K
2070 00:22:22.898058 All Pass.
2071 00:22:22.898105
2072 00:22:22.898152 CH 1, Rank 1
2073 00:22:22.898199 SW Impedance : PASS
2074 00:22:22.898246 DUTY Scan : NO K
2075 00:22:22.898294 ZQ Calibration : PASS
2076 00:22:22.898342 Jitter Meter : NO K
2077 00:22:22.898389 CBT Training : PASS
2078 00:22:22.898436 Write leveling : PASS
2079 00:22:22.898484 RX DQS gating : PASS
2080 00:22:22.898531 RX DQ/DQS(RDDQC) : PASS
2081 00:22:22.898579 TX DQ/DQS : PASS
2082 00:22:22.898626 RX DATLAT : PASS
2083 00:22:22.898673 RX DQ/DQS(Engine): PASS
2084 00:22:22.898720 TX OE : NO K
2085 00:22:22.898767 All Pass.
2086 00:22:22.898814
2087 00:22:22.898862 DramC Write-DBI off
2088 00:22:22.898909 PER_BANK_REFRESH: Hybrid Mode
2089 00:22:22.898957 TX_TRACKING: ON
2090 00:22:22.899250 [GetDramInforAfterCalByMRR] Vendor 6.
2091 00:22:22.899447 [GetDramInforAfterCalByMRR] Revision 606.
2092 00:22:22.899525 [GetDramInforAfterCalByMRR] Revision 2 0.
2093 00:22:22.899578 MR0 0x3b3b
2094 00:22:22.899629 MR8 0x5151
2095 00:22:22.899679 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2096 00:22:22.899729
2097 00:22:22.899793 MR0 0x3b3b
2098 00:22:22.899840 MR8 0x5151
2099 00:22:22.899887 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2100 00:22:22.899935
2101 00:22:22.900006 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2102 00:22:22.900074 [FAST_K] Save calibration result to emmc
2103 00:22:22.900123 [FAST_K] Save calibration result to emmc
2104 00:22:22.900171 dram_init: config_dvfs: 1
2105 00:22:22.900219 dramc_set_vcore_voltage set vcore to 662500
2106 00:22:22.900267 Read voltage for 1200, 2
2107 00:22:22.900315 Vio18 = 0
2108 00:22:22.900362 Vcore = 662500
2109 00:22:22.900410 Vdram = 0
2110 00:22:22.900457 Vddq = 0
2111 00:22:22.900505 Vmddr = 0
2112 00:22:22.900552 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2113 00:22:22.900601 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2114 00:22:22.900675 MEM_TYPE=3, freq_sel=15
2115 00:22:22.900740 sv_algorithm_assistance_LP4_1600
2116 00:22:22.900788 ============ PULL DRAM RESETB DOWN ============
2117 00:22:22.900836 ========== PULL DRAM RESETB DOWN end =========
2118 00:22:22.900884 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2119 00:22:22.900932 ===================================
2120 00:22:22.900980 LPDDR4 DRAM CONFIGURATION
2121 00:22:22.901028 ===================================
2122 00:22:22.901077 EX_ROW_EN[0] = 0x0
2123 00:22:22.901125 EX_ROW_EN[1] = 0x0
2124 00:22:22.901172 LP4Y_EN = 0x0
2125 00:22:22.901220 WORK_FSP = 0x0
2126 00:22:22.901267 WL = 0x4
2127 00:22:22.901314 RL = 0x4
2128 00:22:22.901360 BL = 0x2
2129 00:22:22.901408 RPST = 0x0
2130 00:22:22.901456 RD_PRE = 0x0
2131 00:22:22.901504 WR_PRE = 0x1
2132 00:22:22.901551 WR_PST = 0x0
2133 00:22:22.901598 DBI_WR = 0x0
2134 00:22:22.901646 DBI_RD = 0x0
2135 00:22:22.901693 OTF = 0x1
2136 00:22:22.901741 ===================================
2137 00:22:22.901789 ===================================
2138 00:22:22.901837 ANA top config
2139 00:22:22.901884 ===================================
2140 00:22:22.901932 DLL_ASYNC_EN = 0
2141 00:22:22.901981 ALL_SLAVE_EN = 0
2142 00:22:22.902028 NEW_RANK_MODE = 1
2143 00:22:22.902077 DLL_IDLE_MODE = 1
2144 00:22:22.902124 LP45_APHY_COMB_EN = 1
2145 00:22:22.902172 TX_ODT_DIS = 1
2146 00:22:22.902220 NEW_8X_MODE = 1
2147 00:22:22.902267 ===================================
2148 00:22:22.902315 ===================================
2149 00:22:22.902362 data_rate = 2400
2150 00:22:22.902410 CKR = 1
2151 00:22:22.902457 DQ_P2S_RATIO = 8
2152 00:22:22.902505 ===================================
2153 00:22:22.902552 CA_P2S_RATIO = 8
2154 00:22:22.902599 DQ_CA_OPEN = 0
2155 00:22:22.902647 DQ_SEMI_OPEN = 0
2156 00:22:22.902694 CA_SEMI_OPEN = 0
2157 00:22:22.902741 CA_FULL_RATE = 0
2158 00:22:22.902788 DQ_CKDIV4_EN = 0
2159 00:22:22.902836 CA_CKDIV4_EN = 0
2160 00:22:22.902883 CA_PREDIV_EN = 0
2161 00:22:22.902932 PH8_DLY = 17
2162 00:22:22.902980 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2163 00:22:22.903036 DQ_AAMCK_DIV = 4
2164 00:22:22.903097 CA_AAMCK_DIV = 4
2165 00:22:22.903145 CA_ADMCK_DIV = 4
2166 00:22:22.903194 DQ_TRACK_CA_EN = 0
2167 00:22:22.903242 CA_PICK = 1200
2168 00:22:22.903291 CA_MCKIO = 1200
2169 00:22:22.903339 MCKIO_SEMI = 0
2170 00:22:22.903386 PLL_FREQ = 2366
2171 00:22:22.903434 DQ_UI_PI_RATIO = 32
2172 00:22:22.903483 CA_UI_PI_RATIO = 0
2173 00:22:22.903531 ===================================
2174 00:22:22.903579 ===================================
2175 00:22:22.903627 memory_type:LPDDR4
2176 00:22:22.903675 GP_NUM : 10
2177 00:22:22.903722 SRAM_EN : 1
2178 00:22:22.903770 MD32_EN : 0
2179 00:22:22.903818 ===================================
2180 00:22:22.903866 [ANA_INIT] >>>>>>>>>>>>>>
2181 00:22:22.903914 <<<<<< [CONFIGURE PHASE]: ANA_TX
2182 00:22:22.903963 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2183 00:22:22.904011 ===================================
2184 00:22:22.904058 data_rate = 2400,PCW = 0X5b00
2185 00:22:22.904107 ===================================
2186 00:22:22.904157 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2187 00:22:22.904206 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2188 00:22:22.904254 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2189 00:22:22.904303 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2190 00:22:22.904351 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2191 00:22:22.904399 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2192 00:22:22.904447 [ANA_INIT] flow start
2193 00:22:22.904495 [ANA_INIT] PLL >>>>>>>>
2194 00:22:22.904543 [ANA_INIT] PLL <<<<<<<<
2195 00:22:22.904590 [ANA_INIT] MIDPI >>>>>>>>
2196 00:22:22.904639 [ANA_INIT] MIDPI <<<<<<<<
2197 00:22:22.904728 [ANA_INIT] DLL >>>>>>>>
2198 00:22:22.904776 [ANA_INIT] DLL <<<<<<<<
2199 00:22:22.904825 [ANA_INIT] flow end
2200 00:22:22.904873 ============ LP4 DIFF to SE enter ============
2201 00:22:22.904922 ============ LP4 DIFF to SE exit ============
2202 00:22:22.904971 [ANA_INIT] <<<<<<<<<<<<<
2203 00:22:22.905018 [Flow] Enable top DCM control >>>>>
2204 00:22:22.905066 [Flow] Enable top DCM control <<<<<
2205 00:22:22.905115 Enable DLL master slave shuffle
2206 00:22:22.905164 ==============================================================
2207 00:22:22.905213 Gating Mode config
2208 00:22:22.905261 ==============================================================
2209 00:22:22.905309 Config description:
2210 00:22:22.905357 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2211 00:22:22.905406 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2212 00:22:22.905645 SELPH_MODE 0: By rank 1: By Phase
2213 00:22:22.905726 ==============================================================
2214 00:22:22.905841 GAT_TRACK_EN = 1
2215 00:22:22.905891 RX_GATING_MODE = 2
2216 00:22:22.905941 RX_GATING_TRACK_MODE = 2
2217 00:22:22.905990 SELPH_MODE = 1
2218 00:22:22.906050 PICG_EARLY_EN = 1
2219 00:22:22.906123 VALID_LAT_VALUE = 1
2220 00:22:22.906172 ==============================================================
2221 00:22:22.906221 Enter into Gating configuration >>>>
2222 00:22:22.906270 Exit from Gating configuration <<<<
2223 00:22:22.906318 Enter into DVFS_PRE_config >>>>>
2224 00:22:22.906367 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2225 00:22:22.906417 Exit from DVFS_PRE_config <<<<<
2226 00:22:22.906464 Enter into PICG configuration >>>>
2227 00:22:22.906513 Exit from PICG configuration <<<<
2228 00:22:22.906561 [RX_INPUT] configuration >>>>>
2229 00:22:22.906609 [RX_INPUT] configuration <<<<<
2230 00:22:22.906657 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2231 00:22:22.906705 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2232 00:22:22.906754 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2233 00:22:22.906803 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2234 00:22:22.906851 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2235 00:22:22.906900 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2236 00:22:22.906948 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2237 00:22:22.906996 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2238 00:22:22.907045 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2239 00:22:22.907094 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2240 00:22:22.907142 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2241 00:22:22.907190 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2242 00:22:22.907239 ===================================
2243 00:22:22.907286 LPDDR4 DRAM CONFIGURATION
2244 00:22:22.907334 ===================================
2245 00:22:22.907382 EX_ROW_EN[0] = 0x0
2246 00:22:22.907430 EX_ROW_EN[1] = 0x0
2247 00:22:22.907478 LP4Y_EN = 0x0
2248 00:22:22.907525 WORK_FSP = 0x0
2249 00:22:22.907573 WL = 0x4
2250 00:22:22.907621 RL = 0x4
2251 00:22:22.907668 BL = 0x2
2252 00:22:22.907716 RPST = 0x0
2253 00:22:22.907763 RD_PRE = 0x0
2254 00:22:22.907810 WR_PRE = 0x1
2255 00:22:22.907857 WR_PST = 0x0
2256 00:22:22.907905 DBI_WR = 0x0
2257 00:22:22.907953 DBI_RD = 0x0
2258 00:22:22.908001 OTF = 0x1
2259 00:22:22.908049 ===================================
2260 00:22:22.908097 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2261 00:22:22.908145 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2262 00:22:22.908194 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2263 00:22:22.908242 ===================================
2264 00:22:22.908289 LPDDR4 DRAM CONFIGURATION
2265 00:22:22.908337 ===================================
2266 00:22:22.908386 EX_ROW_EN[0] = 0x10
2267 00:22:22.908434 EX_ROW_EN[1] = 0x0
2268 00:22:22.908481 LP4Y_EN = 0x0
2269 00:22:22.908529 WORK_FSP = 0x0
2270 00:22:22.908577 WL = 0x4
2271 00:22:22.908625 RL = 0x4
2272 00:22:22.908702 BL = 0x2
2273 00:22:22.908766 RPST = 0x0
2274 00:22:22.908813 RD_PRE = 0x0
2275 00:22:22.908861 WR_PRE = 0x1
2276 00:22:22.908909 WR_PST = 0x0
2277 00:22:22.908956 DBI_WR = 0x0
2278 00:22:22.909004 DBI_RD = 0x0
2279 00:22:22.909052 OTF = 0x1
2280 00:22:22.909100 ===================================
2281 00:22:22.909148 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2282 00:22:22.909197 ==
2283 00:22:22.909245 Dram Type= 6, Freq= 0, CH_0, rank 0
2284 00:22:22.909294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2285 00:22:22.909349 ==
2286 00:22:22.909437 [Duty_Offset_Calibration]
2287 00:22:22.909566 B0:2 B1:0 CA:3
2288 00:22:22.909658
2289 00:22:22.909714 [DutyScan_Calibration_Flow] k_type=0
2290 00:22:22.909764
2291 00:22:22.909813 ==CLK 0==
2292 00:22:22.909862 Final CLK duty delay cell = 0
2293 00:22:22.909912 [0] MAX Duty = 5031%(X100), DQS PI = 12
2294 00:22:22.909961 [0] MIN Duty = 4906%(X100), DQS PI = 54
2295 00:22:22.910009 [0] AVG Duty = 4968%(X100)
2296 00:22:22.910056
2297 00:22:22.910104 CH0 CLK Duty spec in!! Max-Min= 125%
2298 00:22:22.910152 [DutyScan_Calibration_Flow] ====Done====
2299 00:22:22.910199
2300 00:22:22.910245 [DutyScan_Calibration_Flow] k_type=1
2301 00:22:22.910292
2302 00:22:22.910339 ==DQS 0 ==
2303 00:22:22.910387 Final DQS duty delay cell = 0
2304 00:22:22.910435 [0] MAX Duty = 5062%(X100), DQS PI = 12
2305 00:22:22.910483 [0] MIN Duty = 4907%(X100), DQS PI = 2
2306 00:22:22.910531 [0] AVG Duty = 4984%(X100)
2307 00:22:22.910578
2308 00:22:22.910626 ==DQS 1 ==
2309 00:22:22.910673 Final DQS duty delay cell = -4
2310 00:22:22.910724 [-4] MAX Duty = 4969%(X100), DQS PI = 22
2311 00:22:22.910772 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2312 00:22:22.910820 [-4] AVG Duty = 4938%(X100)
2313 00:22:22.910867
2314 00:22:22.910914 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2315 00:22:22.910962
2316 00:22:22.911009 CH0 DQS 1 Duty spec in!! Max-Min= 62%
2317 00:22:22.911056 [DutyScan_Calibration_Flow] ====Done====
2318 00:22:22.911104
2319 00:22:22.911151 [DutyScan_Calibration_Flow] k_type=3
2320 00:22:22.911198
2321 00:22:22.911244 ==DQM 0 ==
2322 00:22:22.911292 Final DQM duty delay cell = 0
2323 00:22:22.911340 [0] MAX Duty = 5124%(X100), DQS PI = 12
2324 00:22:22.911388 [0] MIN Duty = 4876%(X100), DQS PI = 0
2325 00:22:22.911436 [0] AVG Duty = 5000%(X100)
2326 00:22:22.911483
2327 00:22:22.911530 ==DQM 1 ==
2328 00:22:22.911577 Final DQM duty delay cell = 4
2329 00:22:22.911625 [4] MAX Duty = 5093%(X100), DQS PI = 48
2330 00:22:22.911671 [4] MIN Duty = 5000%(X100), DQS PI = 30
2331 00:22:22.911718 [4] AVG Duty = 5046%(X100)
2332 00:22:22.911765
2333 00:22:22.911812 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2334 00:22:22.911860
2335 00:22:22.911908 CH0 DQM 1 Duty spec in!! Max-Min= 93%
2336 00:22:22.911957 [DutyScan_Calibration_Flow] ====Done====
2337 00:22:22.912004
2338 00:22:22.912051 [DutyScan_Calibration_Flow] k_type=2
2339 00:22:22.912099
2340 00:22:22.912146 ==DQ 0 ==
2341 00:22:22.912192 Final DQ duty delay cell = -4
2342 00:22:22.912240 [-4] MAX Duty = 5000%(X100), DQS PI = 12
2343 00:22:22.912287 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2344 00:22:22.912524 [-4] AVG Duty = 4953%(X100)
2345 00:22:22.912603
2346 00:22:22.912663 ==DQ 1 ==
2347 00:22:22.912744 Final DQ duty delay cell = -4
2348 00:22:22.912793 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2349 00:22:22.912841 [-4] MIN Duty = 4876%(X100), DQS PI = 18
2350 00:22:22.912904 [-4] AVG Duty = 4938%(X100)
2351 00:22:22.912951
2352 00:22:22.912999 CH0 DQ 0 Duty spec in!! Max-Min= 93%
2353 00:22:22.913048
2354 00:22:22.913095 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2355 00:22:22.913143 [DutyScan_Calibration_Flow] ====Done====
2356 00:22:22.913190 ==
2357 00:22:22.913238 Dram Type= 6, Freq= 0, CH_1, rank 0
2358 00:22:22.913287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2359 00:22:22.913335 ==
2360 00:22:22.913382 [Duty_Offset_Calibration]
2361 00:22:22.913430 B0:1 B1:-2 CA:0
2362 00:22:22.913479
2363 00:22:22.913532 [DutyScan_Calibration_Flow] k_type=0
2364 00:22:22.913580
2365 00:22:22.913626 ==CLK 0==
2366 00:22:22.913674 Final CLK duty delay cell = 0
2367 00:22:22.913723 [0] MAX Duty = 5031%(X100), DQS PI = 16
2368 00:22:22.913771 [0] MIN Duty = 4876%(X100), DQS PI = 58
2369 00:22:22.913818 [0] AVG Duty = 4953%(X100)
2370 00:22:22.913872
2371 00:22:22.913922 CH1 CLK Duty spec in!! Max-Min= 155%
2372 00:22:22.913970 [DutyScan_Calibration_Flow] ====Done====
2373 00:22:22.914018
2374 00:22:22.914064 [DutyScan_Calibration_Flow] k_type=1
2375 00:22:22.914112
2376 00:22:22.914159 ==DQS 0 ==
2377 00:22:22.914206 Final DQS duty delay cell = -4
2378 00:22:22.914254 [-4] MAX Duty = 4969%(X100), DQS PI = 8
2379 00:22:22.914302 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2380 00:22:22.914350 [-4] AVG Duty = 4938%(X100)
2381 00:22:22.914398
2382 00:22:22.914445 ==DQS 1 ==
2383 00:22:22.914493 Final DQS duty delay cell = 0
2384 00:22:22.914541 [0] MAX Duty = 5093%(X100), DQS PI = 0
2385 00:22:22.914588 [0] MIN Duty = 4875%(X100), DQS PI = 26
2386 00:22:22.914636 [0] AVG Duty = 4984%(X100)
2387 00:22:22.914684
2388 00:22:22.914731 CH1 DQS 0 Duty spec in!! Max-Min= 62%
2389 00:22:22.914778
2390 00:22:22.914825 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2391 00:22:22.914873 [DutyScan_Calibration_Flow] ====Done====
2392 00:22:22.914921
2393 00:22:22.914968 [DutyScan_Calibration_Flow] k_type=3
2394 00:22:22.915015
2395 00:22:22.915062 ==DQM 0 ==
2396 00:22:22.915109 Final DQM duty delay cell = 0
2397 00:22:22.915156 [0] MAX Duty = 5000%(X100), DQS PI = 24
2398 00:22:22.915204 [0] MIN Duty = 4876%(X100), DQS PI = 0
2399 00:22:22.915251 [0] AVG Duty = 4938%(X100)
2400 00:22:22.915298
2401 00:22:22.915344 ==DQM 1 ==
2402 00:22:22.915392 Final DQM duty delay cell = 0
2403 00:22:22.915441 [0] MAX Duty = 5031%(X100), DQS PI = 36
2404 00:22:22.915488 [0] MIN Duty = 4907%(X100), DQS PI = 4
2405 00:22:22.915536 [0] AVG Duty = 4969%(X100)
2406 00:22:22.915584
2407 00:22:22.915641 CH1 DQM 0 Duty spec in!! Max-Min= 124%
2408 00:22:22.915791
2409 00:22:22.915894 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2410 00:22:22.915968 [DutyScan_Calibration_Flow] ====Done====
2411 00:22:22.916019
2412 00:22:22.916067 [DutyScan_Calibration_Flow] k_type=2
2413 00:22:22.916116
2414 00:22:22.916163 ==DQ 0 ==
2415 00:22:22.916210 Final DQ duty delay cell = 0
2416 00:22:22.916266 [0] MAX Duty = 5062%(X100), DQS PI = 12
2417 00:22:22.916357 [0] MIN Duty = 4938%(X100), DQS PI = 54
2418 00:22:22.916464 [0] AVG Duty = 5000%(X100)
2419 00:22:22.916594
2420 00:22:22.916720 ==DQ 1 ==
2421 00:22:22.916774 Final DQ duty delay cell = 0
2422 00:22:22.916824 [0] MAX Duty = 5125%(X100), DQS PI = 36
2423 00:22:22.916874 [0] MIN Duty = 5000%(X100), DQS PI = 2
2424 00:22:22.916923 [0] AVG Duty = 5062%(X100)
2425 00:22:22.916971
2426 00:22:22.917018 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2427 00:22:22.917066
2428 00:22:22.917113 CH1 DQ 1 Duty spec in!! Max-Min= 125%
2429 00:22:22.917161 [DutyScan_Calibration_Flow] ====Done====
2430 00:22:22.917209 nWR fixed to 30
2431 00:22:22.917257 [ModeRegInit_LP4] CH0 RK0
2432 00:22:22.917305 [ModeRegInit_LP4] CH0 RK1
2433 00:22:22.917353 [ModeRegInit_LP4] CH1 RK0
2434 00:22:22.917400 [ModeRegInit_LP4] CH1 RK1
2435 00:22:22.917447 match AC timing 7
2436 00:22:22.917495 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2437 00:22:22.917544 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2438 00:22:22.917593 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2439 00:22:22.917640 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2440 00:22:22.917688 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2441 00:22:22.917736 ==
2442 00:22:22.917788 Dram Type= 6, Freq= 0, CH_0, rank 0
2443 00:22:22.917854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2444 00:22:22.918010 ==
2445 00:22:22.918108 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2446 00:22:22.918166 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2447 00:22:22.918216 [CA 0] Center 40 (10~71) winsize 62
2448 00:22:22.918265 [CA 1] Center 39 (9~70) winsize 62
2449 00:22:22.918333 [CA 2] Center 36 (6~66) winsize 61
2450 00:22:22.918502 [CA 3] Center 35 (5~66) winsize 62
2451 00:22:22.918599 [CA 4] Center 34 (4~65) winsize 62
2452 00:22:22.918670 [CA 5] Center 33 (3~64) winsize 62
2453 00:22:22.918721
2454 00:22:22.918770 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2455 00:22:22.918819
2456 00:22:22.918867 [CATrainingPosCal] consider 1 rank data
2457 00:22:22.918916 u2DelayCellTimex100 = 270/100 ps
2458 00:22:22.918964 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2459 00:22:22.919013 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2460 00:22:22.919078 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2461 00:22:22.919242 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2462 00:22:22.919336 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2463 00:22:22.919405 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2464 00:22:22.919454
2465 00:22:22.919503 CA PerBit enable=1, Macro0, CA PI delay=33
2466 00:22:22.919553
2467 00:22:22.919601 [CBTSetCACLKResult] CA Dly = 33
2468 00:22:22.919649 CS Dly: 7 (0~38)
2469 00:22:22.919696 ==
2470 00:22:22.919744 Dram Type= 6, Freq= 0, CH_0, rank 1
2471 00:22:22.919793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2472 00:22:22.919842 ==
2473 00:22:22.919889 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2474 00:22:22.919937 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2475 00:22:22.919986 [CA 0] Center 40 (10~71) winsize 62
2476 00:22:22.920034 [CA 1] Center 40 (10~70) winsize 61
2477 00:22:22.920082 [CA 2] Center 35 (5~66) winsize 62
2478 00:22:22.920130 [CA 3] Center 35 (5~66) winsize 62
2479 00:22:22.920178 [CA 4] Center 34 (4~65) winsize 62
2480 00:22:22.920225 [CA 5] Center 33 (3~63) winsize 61
2481 00:22:22.920273
2482 00:22:22.920319 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2483 00:22:22.920367
2484 00:22:22.920414 [CATrainingPosCal] consider 2 rank data
2485 00:22:22.920463 u2DelayCellTimex100 = 270/100 ps
2486 00:22:22.920517 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2487 00:22:22.920784 CA1 delay=40 (10~70),Diff = 7 PI (33 cell)
2488 00:22:22.920841 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2489 00:22:22.920891 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2490 00:22:22.920958 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2491 00:22:22.921021 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2492 00:22:22.921068
2493 00:22:22.921117 CA PerBit enable=1, Macro0, CA PI delay=33
2494 00:22:22.921165
2495 00:22:22.921213 [CBTSetCACLKResult] CA Dly = 33
2496 00:22:22.921261 CS Dly: 8 (0~40)
2497 00:22:22.921308
2498 00:22:22.921355 ----->DramcWriteLeveling(PI) begin...
2499 00:22:22.921404 ==
2500 00:22:22.921452 Dram Type= 6, Freq= 0, CH_0, rank 0
2501 00:22:22.921501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2502 00:22:22.921550 ==
2503 00:22:22.921597 Write leveling (Byte 0): 33 => 33
2504 00:22:22.921645 Write leveling (Byte 1): 31 => 31
2505 00:22:22.921699 DramcWriteLeveling(PI) end<-----
2506 00:22:22.921747
2507 00:22:22.921795 ==
2508 00:22:22.921847 Dram Type= 6, Freq= 0, CH_0, rank 0
2509 00:22:22.921895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2510 00:22:22.921942 ==
2511 00:22:22.921990 [Gating] SW mode calibration
2512 00:22:22.922038 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2513 00:22:22.922086 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2514 00:22:22.922134 0 15 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
2515 00:22:22.922213 0 15 4 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
2516 00:22:22.922293 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2517 00:22:22.922409 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2518 00:22:22.922487 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2519 00:22:22.922539 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2520 00:22:22.922588 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2521 00:22:22.922637 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2522 00:22:22.922685 1 0 0 | B1->B0 | 3333 2a2a | 1 0 | (1 0) (0 0)
2523 00:22:22.922797 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2524 00:22:22.922863 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2525 00:22:22.922925 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2526 00:22:22.922972 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2527 00:22:22.923020 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2528 00:22:22.923068 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2529 00:22:22.923115 1 0 28 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
2530 00:22:22.923163 1 1 0 | B1->B0 | 2727 3232 | 1 0 | (0 0) (0 0)
2531 00:22:22.923210 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2532 00:22:22.923257 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2533 00:22:22.923304 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2534 00:22:22.923352 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2535 00:22:22.923417 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2536 00:22:22.923479 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2537 00:22:22.923527 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2538 00:22:22.923574 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2539 00:22:22.923622 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2540 00:22:22.923669 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2541 00:22:22.923717 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2542 00:22:22.923764 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2543 00:22:22.923812 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2544 00:22:22.923860 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 00:22:22.923907 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 00:22:22.923955 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 00:22:22.924020 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 00:22:22.924082 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 00:22:22.924147 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 00:22:22.924241 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 00:22:22.924289 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 00:22:22.924337 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 00:22:22.924385 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 00:22:22.924433 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2555 00:22:22.924480 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2556 00:22:22.924528 Total UI for P1: 0, mck2ui 16
2557 00:22:22.924576 best dqsien dly found for B0: ( 1, 4, 0)
2558 00:22:22.924638 Total UI for P1: 0, mck2ui 16
2559 00:22:22.924926 best dqsien dly found for B1: ( 1, 4, 2)
2560 00:22:22.925019 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2561 00:22:22.925092 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2562 00:22:22.925142
2563 00:22:22.925191 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2564 00:22:22.925240 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2565 00:22:22.925289 [Gating] SW calibration Done
2566 00:22:22.925337 ==
2567 00:22:22.925385 Dram Type= 6, Freq= 0, CH_0, rank 0
2568 00:22:22.925433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2569 00:22:22.925528 ==
2570 00:22:22.925577 RX Vref Scan: 0
2571 00:22:22.925626
2572 00:22:22.925674 RX Vref 0 -> 0, step: 1
2573 00:22:22.925723
2574 00:22:22.925771 RX Delay -40 -> 252, step: 8
2575 00:22:22.925834 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2576 00:22:22.925882 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2577 00:22:22.925980 iDelay=200, Bit 2, Center 111 (32 ~ 191) 160
2578 00:22:22.926028 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2579 00:22:22.926090 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2580 00:22:22.926138 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2581 00:22:22.926186 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2582 00:22:22.926233 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2583 00:22:22.926281 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2584 00:22:22.926328 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2585 00:22:22.926376 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2586 00:22:22.926423 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
2587 00:22:22.926471 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2588 00:22:22.926519 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2589 00:22:22.926771 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2590 00:22:22.926841 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2591 00:22:22.926890 ==
2592 00:22:22.926939 Dram Type= 6, Freq= 0, CH_0, rank 0
2593 00:22:22.926988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2594 00:22:22.927036 ==
2595 00:22:22.927084 DQS Delay:
2596 00:22:22.927131 DQS0 = 0, DQS1 = 0
2597 00:22:22.927179 DQM Delay:
2598 00:22:22.927239 DQM0 = 112, DQM1 = 103
2599 00:22:22.927288 DQ Delay:
2600 00:22:22.927336 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2601 00:22:22.927384 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2602 00:22:22.927432 DQ8 =91, DQ9 =87, DQ10 =103, DQ11 =99
2603 00:22:22.927479 DQ12 =111, DQ13 =111, DQ14 =115, DQ15 =111
2604 00:22:22.927528
2605 00:22:22.927576
2606 00:22:22.927623 ==
2607 00:22:22.927671 Dram Type= 6, Freq= 0, CH_0, rank 0
2608 00:22:22.927720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2609 00:22:22.927768 ==
2610 00:22:22.927831
2611 00:22:22.927880
2612 00:22:22.927942 TX Vref Scan disable
2613 00:22:22.927991 == TX Byte 0 ==
2614 00:22:22.928039 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2615 00:22:22.928114 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2616 00:22:22.928179 == TX Byte 1 ==
2617 00:22:22.928226 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2618 00:22:22.928292 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2619 00:22:22.928341 ==
2620 00:22:22.928389 Dram Type= 6, Freq= 0, CH_0, rank 0
2621 00:22:22.928438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2622 00:22:22.928487 ==
2623 00:22:22.928536 TX Vref=22, minBit 5, minWin=25, winSum=416
2624 00:22:22.928585 TX Vref=24, minBit 3, minWin=26, winSum=424
2625 00:22:22.928634 TX Vref=26, minBit 1, minWin=26, winSum=428
2626 00:22:22.928707 TX Vref=28, minBit 1, minWin=27, winSum=436
2627 00:22:22.928788 TX Vref=30, minBit 1, minWin=27, winSum=438
2628 00:22:22.928835 TX Vref=32, minBit 1, minWin=26, winSum=430
2629 00:22:22.928902 [TxChooseVref] Worse bit 1, Min win 27, Win sum 438, Final Vref 30
2630 00:22:22.928970
2631 00:22:22.929034 Final TX Range 1 Vref 30
2632 00:22:22.929097
2633 00:22:22.929144 ==
2634 00:22:22.929192 Dram Type= 6, Freq= 0, CH_0, rank 0
2635 00:22:22.929239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2636 00:22:22.929287 ==
2637 00:22:22.929334
2638 00:22:22.929380
2639 00:22:22.929426 TX Vref Scan disable
2640 00:22:22.929473 == TX Byte 0 ==
2641 00:22:22.929520 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2642 00:22:22.929611 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2643 00:22:22.929669 == TX Byte 1 ==
2644 00:22:22.929718 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2645 00:22:22.929766 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2646 00:22:22.929813
2647 00:22:22.929861 [DATLAT]
2648 00:22:22.929908 Freq=1200, CH0 RK0
2649 00:22:22.929955
2650 00:22:22.930002 DATLAT Default: 0xd
2651 00:22:22.930050 0, 0xFFFF, sum = 0
2652 00:22:22.930099 1, 0xFFFF, sum = 0
2653 00:22:22.930148 2, 0xFFFF, sum = 0
2654 00:22:22.930196 3, 0xFFFF, sum = 0
2655 00:22:22.930244 4, 0xFFFF, sum = 0
2656 00:22:22.930292 5, 0xFFFF, sum = 0
2657 00:22:22.930340 6, 0xFFFF, sum = 0
2658 00:22:22.930388 7, 0xFFFF, sum = 0
2659 00:22:22.930436 8, 0xFFFF, sum = 0
2660 00:22:22.930484 9, 0xFFFF, sum = 0
2661 00:22:22.930532 10, 0xFFFF, sum = 0
2662 00:22:22.930580 11, 0xFFFF, sum = 0
2663 00:22:22.930628 12, 0x0, sum = 1
2664 00:22:22.930676 13, 0x0, sum = 2
2665 00:22:22.930723 14, 0x0, sum = 3
2666 00:22:22.930802 15, 0x0, sum = 4
2667 00:22:22.930851 best_step = 13
2668 00:22:22.930897
2669 00:22:22.930944 ==
2670 00:22:22.930992 Dram Type= 6, Freq= 0, CH_0, rank 0
2671 00:22:22.931039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2672 00:22:22.931087 ==
2673 00:22:22.931134 RX Vref Scan: 1
2674 00:22:22.931180
2675 00:22:22.931228 Set Vref Range= 32 -> 127
2676 00:22:22.931275
2677 00:22:22.931322 RX Vref 32 -> 127, step: 1
2678 00:22:22.931369
2679 00:22:22.931416 RX Delay -37 -> 252, step: 4
2680 00:22:22.931463
2681 00:22:22.931510 Set Vref, RX VrefLevel [Byte0]: 32
2682 00:22:22.931559 [Byte1]: 32
2683 00:22:22.931606
2684 00:22:22.931652 Set Vref, RX VrefLevel [Byte0]: 33
2685 00:22:22.931699 [Byte1]: 33
2686 00:22:22.931746
2687 00:22:22.931794 Set Vref, RX VrefLevel [Byte0]: 34
2688 00:22:22.931841 [Byte1]: 34
2689 00:22:22.931889
2690 00:22:22.931936 Set Vref, RX VrefLevel [Byte0]: 35
2691 00:22:22.931984 [Byte1]: 35
2692 00:22:22.932031
2693 00:22:22.932078 Set Vref, RX VrefLevel [Byte0]: 36
2694 00:22:22.932126 [Byte1]: 36
2695 00:22:22.932172
2696 00:22:22.932219 Set Vref, RX VrefLevel [Byte0]: 37
2697 00:22:22.932266 [Byte1]: 37
2698 00:22:22.932313
2699 00:22:22.932361 Set Vref, RX VrefLevel [Byte0]: 38
2700 00:22:22.932445 [Byte1]: 38
2701 00:22:22.932525
2702 00:22:22.932602 Set Vref, RX VrefLevel [Byte0]: 39
2703 00:22:22.932692 [Byte1]: 39
2704 00:22:22.932742
2705 00:22:22.932791 Set Vref, RX VrefLevel [Byte0]: 40
2706 00:22:22.932839 [Byte1]: 40
2707 00:22:22.932887
2708 00:22:22.932935 Set Vref, RX VrefLevel [Byte0]: 41
2709 00:22:22.932983 [Byte1]: 41
2710 00:22:22.933031
2711 00:22:22.933079 Set Vref, RX VrefLevel [Byte0]: 42
2712 00:22:22.933127 [Byte1]: 42
2713 00:22:22.933174
2714 00:22:22.933221 Set Vref, RX VrefLevel [Byte0]: 43
2715 00:22:22.933268 [Byte1]: 43
2716 00:22:22.933316
2717 00:22:22.933363 Set Vref, RX VrefLevel [Byte0]: 44
2718 00:22:22.933411 [Byte1]: 44
2719 00:22:22.933459
2720 00:22:22.933506 Set Vref, RX VrefLevel [Byte0]: 45
2721 00:22:22.933554 [Byte1]: 45
2722 00:22:22.933601
2723 00:22:22.933648 Set Vref, RX VrefLevel [Byte0]: 46
2724 00:22:22.933695 [Byte1]: 46
2725 00:22:22.933742
2726 00:22:22.933789 Set Vref, RX VrefLevel [Byte0]: 47
2727 00:22:22.933837 [Byte1]: 47
2728 00:22:22.933885
2729 00:22:22.933942 Set Vref, RX VrefLevel [Byte0]: 48
2730 00:22:22.933993 [Byte1]: 48
2731 00:22:22.934042
2732 00:22:22.934089 Set Vref, RX VrefLevel [Byte0]: 49
2733 00:22:22.934136 [Byte1]: 49
2734 00:22:22.934183
2735 00:22:22.934231 Set Vref, RX VrefLevel [Byte0]: 50
2736 00:22:22.934279 [Byte1]: 50
2737 00:22:22.934327
2738 00:22:22.934374 Set Vref, RX VrefLevel [Byte0]: 51
2739 00:22:22.934422 [Byte1]: 51
2740 00:22:22.934491
2741 00:22:22.934541 Set Vref, RX VrefLevel [Byte0]: 52
2742 00:22:22.934589 [Byte1]: 52
2743 00:22:22.934636
2744 00:22:22.934683 Set Vref, RX VrefLevel [Byte0]: 53
2745 00:22:22.934732 [Byte1]: 53
2746 00:22:22.934780
2747 00:22:22.934827 Set Vref, RX VrefLevel [Byte0]: 54
2748 00:22:22.934875 [Byte1]: 54
2749 00:22:22.934922
2750 00:22:22.934970 Set Vref, RX VrefLevel [Byte0]: 55
2751 00:22:22.935023 [Byte1]: 55
2752 00:22:22.935076
2753 00:22:22.935124 Set Vref, RX VrefLevel [Byte0]: 56
2754 00:22:22.935172 [Byte1]: 56
2755 00:22:22.935219
2756 00:22:22.935456 Set Vref, RX VrefLevel [Byte0]: 57
2757 00:22:22.935570 [Byte1]: 57
2758 00:22:22.935634
2759 00:22:22.935683 Set Vref, RX VrefLevel [Byte0]: 58
2760 00:22:22.935732 [Byte1]: 58
2761 00:22:22.935779
2762 00:22:22.935826 Set Vref, RX VrefLevel [Byte0]: 59
2763 00:22:22.935898 [Byte1]: 59
2764 00:22:22.935960
2765 00:22:22.936010 Set Vref, RX VrefLevel [Byte0]: 60
2766 00:22:22.936059 [Byte1]: 60
2767 00:22:22.936109
2768 00:22:22.936157 Set Vref, RX VrefLevel [Byte0]: 61
2769 00:22:22.936212 [Byte1]: 61
2770 00:22:22.936260
2771 00:22:22.936310 Set Vref, RX VrefLevel [Byte0]: 62
2772 00:22:22.936390 [Byte1]: 62
2773 00:22:22.936482
2774 00:22:22.936557 Set Vref, RX VrefLevel [Byte0]: 63
2775 00:22:22.936633 [Byte1]: 63
2776 00:22:22.936730
2777 00:22:22.936780 Set Vref, RX VrefLevel [Byte0]: 64
2778 00:22:22.936829 [Byte1]: 64
2779 00:22:22.936877
2780 00:22:22.936924 Set Vref, RX VrefLevel [Byte0]: 65
2781 00:22:22.936976 [Byte1]: 65
2782 00:22:22.937027
2783 00:22:22.937074 Set Vref, RX VrefLevel [Byte0]: 66
2784 00:22:22.937126 [Byte1]: 66
2785 00:22:22.937174
2786 00:22:22.937222 Set Vref, RX VrefLevel [Byte0]: 67
2787 00:22:22.937271 [Byte1]: 67
2788 00:22:22.937318
2789 00:22:22.937365 Set Vref, RX VrefLevel [Byte0]: 68
2790 00:22:22.937413 [Byte1]: 68
2791 00:22:22.937461
2792 00:22:22.937509 Set Vref, RX VrefLevel [Byte0]: 69
2793 00:22:22.937557 [Byte1]: 69
2794 00:22:22.937614
2795 00:22:22.937670 Set Vref, RX VrefLevel [Byte0]: 70
2796 00:22:22.937719 [Byte1]: 70
2797 00:22:22.937766
2798 00:22:22.937813 Set Vref, RX VrefLevel [Byte0]: 71
2799 00:22:22.937861 [Byte1]: 71
2800 00:22:22.937908
2801 00:22:22.937956 Set Vref, RX VrefLevel [Byte0]: 72
2802 00:22:22.938005 [Byte1]: 72
2803 00:22:22.938052
2804 00:22:22.938099 Set Vref, RX VrefLevel [Byte0]: 73
2805 00:22:22.938146 [Byte1]: 73
2806 00:22:22.938226
2807 00:22:22.938294 Set Vref, RX VrefLevel [Byte0]: 74
2808 00:22:22.938346 [Byte1]: 74
2809 00:22:22.938394
2810 00:22:22.938441 Final RX Vref Byte 0 = 62 to rank0
2811 00:22:22.938490 Final RX Vref Byte 1 = 53 to rank0
2812 00:22:22.938538 Final RX Vref Byte 0 = 62 to rank1
2813 00:22:22.938586 Final RX Vref Byte 1 = 53 to rank1==
2814 00:22:22.938634 Dram Type= 6, Freq= 0, CH_0, rank 0
2815 00:22:22.938685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2816 00:22:22.938735 ==
2817 00:22:22.938782 DQS Delay:
2818 00:22:22.938828 DQS0 = 0, DQS1 = 0
2819 00:22:22.938876 DQM Delay:
2820 00:22:22.938932 DQM0 = 112, DQM1 = 101
2821 00:22:22.939012 DQ Delay:
2822 00:22:22.939088 DQ0 =110, DQ1 =112, DQ2 =112, DQ3 =108
2823 00:22:22.939165 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2824 00:22:22.939222 DQ8 =92, DQ9 =86, DQ10 =104, DQ11 =94
2825 00:22:22.939271 DQ12 =106, DQ13 =106, DQ14 =116, DQ15 =108
2826 00:22:22.939319
2827 00:22:22.939374
2828 00:22:22.939435 [DQSOSCAuto] RK0, (LSB)MR18= 0xfefe, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
2829 00:22:22.939486 CH0 RK0: MR19=303, MR18=FEFE
2830 00:22:22.939534 CH0_RK0: MR19=0x303, MR18=0xFEFE, DQSOSC=410, MR23=63, INC=39, DEC=26
2831 00:22:22.939614
2832 00:22:22.939690 ----->DramcWriteLeveling(PI) begin...
2833 00:22:22.939767 ==
2834 00:22:22.939843 Dram Type= 6, Freq= 0, CH_0, rank 1
2835 00:22:22.939920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2836 00:22:22.939995 ==
2837 00:22:22.940071 Write leveling (Byte 0): 31 => 31
2838 00:22:22.940145 Write leveling (Byte 1): 30 => 30
2839 00:22:22.940215 DramcWriteLeveling(PI) end<-----
2840 00:22:22.940290
2841 00:22:22.940364 ==
2842 00:22:22.940439 Dram Type= 6, Freq= 0, CH_0, rank 1
2843 00:22:22.940515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2844 00:22:22.940590 ==
2845 00:22:22.940687 [Gating] SW mode calibration
2846 00:22:22.940760 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2847 00:22:22.940810 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2848 00:22:22.940858 0 15 0 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
2849 00:22:22.940914 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2850 00:22:22.940962 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2851 00:22:22.941010 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2852 00:22:22.941058 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2853 00:22:22.941105 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2854 00:22:22.941153 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
2855 00:22:22.941200 0 15 28 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 0)
2856 00:22:22.941248 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2857 00:22:22.941304 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2858 00:22:22.941359 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2859 00:22:22.941408 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2860 00:22:22.941457 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2861 00:22:22.941505 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2862 00:22:22.941554 1 0 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
2863 00:22:22.941602 1 0 28 | B1->B0 | 2424 4040 | 0 0 | (0 0) (0 0)
2864 00:22:22.941650 1 1 0 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
2865 00:22:22.941698 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2866 00:22:22.941747 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2867 00:22:22.941795 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2868 00:22:22.941849 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2869 00:22:22.941898 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2870 00:22:22.941970 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2871 00:22:22.942035 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2872 00:22:22.942222 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2873 00:22:22.942356 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 00:22:22.942449 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 00:22:22.942552 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 00:22:22.942633 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 00:22:22.942713 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 00:22:22.943025 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 00:22:22.943107 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 00:22:22.943185 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 00:22:22.943266 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 00:22:22.943343 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 00:22:22.943420 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 00:22:22.943496 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 00:22:22.943572 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 00:22:22.943649 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 00:22:22.943726 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2888 00:22:22.943803 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2889 00:22:22.943858 Total UI for P1: 0, mck2ui 16
2890 00:22:22.943908 best dqsien dly found for B0: ( 1, 3, 28)
2891 00:22:22.943956 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2892 00:22:22.944004 Total UI for P1: 0, mck2ui 16
2893 00:22:22.944053 best dqsien dly found for B1: ( 1, 4, 0)
2894 00:22:22.944102 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2895 00:22:22.944151 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2896 00:22:22.944200
2897 00:22:22.944248 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2898 00:22:22.944296 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2899 00:22:22.944344 [Gating] SW calibration Done
2900 00:22:22.944391 ==
2901 00:22:22.944438 Dram Type= 6, Freq= 0, CH_0, rank 1
2902 00:22:22.944518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2903 00:22:22.944594 ==
2904 00:22:22.944694 RX Vref Scan: 0
2905 00:22:22.944787
2906 00:22:22.944851 RX Vref 0 -> 0, step: 1
2907 00:22:22.944916
2908 00:22:22.945001 RX Delay -40 -> 252, step: 8
2909 00:22:22.945063 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2910 00:22:22.945112 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
2911 00:22:22.945160 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2912 00:22:22.945208 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2913 00:22:22.945256 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2914 00:22:22.945303 iDelay=200, Bit 5, Center 99 (32 ~ 167) 136
2915 00:22:22.945351 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2916 00:22:22.945418 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2917 00:22:22.945468 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2918 00:22:22.945521 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2919 00:22:22.945570 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2920 00:22:22.945618 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2921 00:22:22.945666 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2922 00:22:22.945713 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2923 00:22:22.945761 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2924 00:22:22.945847 iDelay=200, Bit 15, Center 107 (32 ~ 183) 152
2925 00:22:22.945918 ==
2926 00:22:22.945968 Dram Type= 6, Freq= 0, CH_0, rank 1
2927 00:22:22.946018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2928 00:22:22.946067 ==
2929 00:22:22.946114 DQS Delay:
2930 00:22:22.946165 DQS0 = 0, DQS1 = 0
2931 00:22:22.946215 DQM Delay:
2932 00:22:22.946262 DQM0 = 111, DQM1 = 101
2933 00:22:22.946310 DQ Delay:
2934 00:22:22.946357 DQ0 =111, DQ1 =107, DQ2 =111, DQ3 =107
2935 00:22:23.106185 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2936 00:22:23.106298 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
2937 00:22:23.106435 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =107
2938 00:22:23.106503
2939 00:22:23.106555
2940 00:22:23.106604 ==
2941 00:22:23.106654 Dram Type= 6, Freq= 0, CH_0, rank 1
2942 00:22:23.106704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2943 00:22:23.106755 ==
2944 00:22:23.106804
2945 00:22:23.106871
2946 00:22:23.106950 TX Vref Scan disable
2947 00:22:23.107016 == TX Byte 0 ==
2948 00:22:23.107065 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2949 00:22:23.107114 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2950 00:22:23.107164 == TX Byte 1 ==
2951 00:22:23.107212 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2952 00:22:23.107260 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2953 00:22:23.107324 ==
2954 00:22:23.107403 Dram Type= 6, Freq= 0, CH_0, rank 1
2955 00:22:23.107454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2956 00:22:23.107504 ==
2957 00:22:23.107554 TX Vref=22, minBit 2, minWin=26, winSum=429
2958 00:22:23.107605 TX Vref=24, minBit 0, minWin=26, winSum=434
2959 00:22:23.107655 TX Vref=26, minBit 1, minWin=26, winSum=431
2960 00:22:23.107704 TX Vref=28, minBit 5, minWin=26, winSum=439
2961 00:22:23.107752 TX Vref=30, minBit 5, minWin=26, winSum=445
2962 00:22:23.107802 TX Vref=32, minBit 10, minWin=26, winSum=438
2963 00:22:23.107852 [TxChooseVref] Worse bit 5, Min win 26, Win sum 445, Final Vref 30
2964 00:22:23.107901
2965 00:22:23.107949 Final TX Range 1 Vref 30
2966 00:22:23.107999
2967 00:22:23.108068 ==
2968 00:22:23.108122 Dram Type= 6, Freq= 0, CH_0, rank 1
2969 00:22:23.108172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2970 00:22:23.108223 ==
2971 00:22:23.108285
2972 00:22:23.108381
2973 00:22:23.108429 TX Vref Scan disable
2974 00:22:23.108479 == TX Byte 0 ==
2975 00:22:23.108528 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2976 00:22:23.108577 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2977 00:22:23.108627 == TX Byte 1 ==
2978 00:22:23.108686 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2979 00:22:23.108736 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2980 00:22:23.108785
2981 00:22:23.108833 [DATLAT]
2982 00:22:23.108882 Freq=1200, CH0 RK1
2983 00:22:23.108948
2984 00:22:23.109013 DATLAT Default: 0xd
2985 00:22:23.109096 0, 0xFFFF, sum = 0
2986 00:22:23.109149 1, 0xFFFF, sum = 0
2987 00:22:23.109201 2, 0xFFFF, sum = 0
2988 00:22:23.109251 3, 0xFFFF, sum = 0
2989 00:22:23.109302 4, 0xFFFF, sum = 0
2990 00:22:23.109352 5, 0xFFFF, sum = 0
2991 00:22:23.109402 6, 0xFFFF, sum = 0
2992 00:22:23.109451 7, 0xFFFF, sum = 0
2993 00:22:23.109500 8, 0xFFFF, sum = 0
2994 00:22:23.109549 9, 0xFFFF, sum = 0
2995 00:22:23.109598 10, 0xFFFF, sum = 0
2996 00:22:23.109649 11, 0xFFFF, sum = 0
2997 00:22:23.109699 12, 0x0, sum = 1
2998 00:22:23.109748 13, 0x0, sum = 2
2999 00:22:23.109799 14, 0x0, sum = 3
3000 00:22:23.109848 15, 0x0, sum = 4
3001 00:22:23.109897 best_step = 13
3002 00:22:23.109945
3003 00:22:23.110008 ==
3004 00:22:23.110056 Dram Type= 6, Freq= 0, CH_0, rank 1
3005 00:22:23.110105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3006 00:22:23.110153 ==
3007 00:22:23.110218 RX Vref Scan: 0
3008 00:22:23.110281
3009 00:22:23.110328 RX Vref 0 -> 0, step: 1
3010 00:22:23.110374
3011 00:22:23.110421 RX Delay -37 -> 252, step: 4
3012 00:22:23.110469 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3013 00:22:23.110517 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3014 00:22:23.110565 iDelay=195, Bit 2, Center 108 (43 ~ 174) 132
3015 00:22:23.110630 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3016 00:22:23.110902 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3017 00:22:23.111005 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3018 00:22:23.111088 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3019 00:22:23.111138 iDelay=195, Bit 7, Center 120 (47 ~ 194) 148
3020 00:22:23.111220 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3021 00:22:23.111273 iDelay=195, Bit 9, Center 84 (15 ~ 154) 140
3022 00:22:23.111322 iDelay=195, Bit 10, Center 104 (35 ~ 174) 140
3023 00:22:23.111372 iDelay=195, Bit 11, Center 92 (23 ~ 162) 140
3024 00:22:23.111435 iDelay=195, Bit 12, Center 108 (39 ~ 178) 140
3025 00:22:23.111484 iDelay=195, Bit 13, Center 108 (39 ~ 178) 140
3026 00:22:23.111566 iDelay=195, Bit 14, Center 114 (47 ~ 182) 136
3027 00:22:23.111620 iDelay=195, Bit 15, Center 110 (43 ~ 178) 136
3028 00:22:23.111669 ==
3029 00:22:23.111719 Dram Type= 6, Freq= 0, CH_0, rank 1
3030 00:22:23.111804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3031 00:22:23.111923 ==
3032 00:22:23.111974 DQS Delay:
3033 00:22:23.112022 DQS0 = 0, DQS1 = 0
3034 00:22:23.112070 DQM Delay:
3035 00:22:23.112117 DQM0 = 111, DQM1 = 101
3036 00:22:23.112196 DQ Delay:
3037 00:22:23.112244 DQ0 =108, DQ1 =112, DQ2 =108, DQ3 =108
3038 00:22:23.112291 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =120
3039 00:22:23.112339 DQ8 =90, DQ9 =84, DQ10 =104, DQ11 =92
3040 00:22:23.112388 DQ12 =108, DQ13 =108, DQ14 =114, DQ15 =110
3041 00:22:23.112459
3042 00:22:23.112547
3043 00:22:23.112627 [DQSOSCAuto] RK1, (LSB)MR18= 0x12fa, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 403 ps
3044 00:22:23.112694 CH0 RK1: MR19=403, MR18=12FA
3045 00:22:23.112744 CH0_RK1: MR19=0x403, MR18=0x12FA, DQSOSC=403, MR23=63, INC=40, DEC=26
3046 00:22:23.112823 [RxdqsGatingPostProcess] freq 1200
3047 00:22:23.112887 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3048 00:22:23.112935 best DQS0 dly(2T, 0.5T) = (0, 12)
3049 00:22:23.112983 best DQS1 dly(2T, 0.5T) = (0, 12)
3050 00:22:23.113051 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3051 00:22:23.113123 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3052 00:22:23.113187 best DQS0 dly(2T, 0.5T) = (0, 11)
3053 00:22:23.113236 best DQS1 dly(2T, 0.5T) = (0, 12)
3054 00:22:23.113285 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3055 00:22:23.113333 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3056 00:22:23.113382 Pre-setting of DQS Precalculation
3057 00:22:23.113430 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3058 00:22:23.113479 ==
3059 00:22:23.113527 Dram Type= 6, Freq= 0, CH_1, rank 0
3060 00:22:23.113604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3061 00:22:23.113686 ==
3062 00:22:23.113736 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3063 00:22:23.113785 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3064 00:22:23.113835 [CA 0] Center 37 (7~67) winsize 61
3065 00:22:23.113913 [CA 1] Center 37 (7~68) winsize 62
3066 00:22:23.113962 [CA 2] Center 34 (4~64) winsize 61
3067 00:22:23.114010 [CA 3] Center 34 (4~64) winsize 61
3068 00:22:23.114058 [CA 4] Center 34 (4~64) winsize 61
3069 00:22:23.114107 [CA 5] Center 33 (3~63) winsize 61
3070 00:22:23.114185
3071 00:22:23.114293 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3072 00:22:23.114343
3073 00:22:23.114392 [CATrainingPosCal] consider 1 rank data
3074 00:22:23.114442 u2DelayCellTimex100 = 270/100 ps
3075 00:22:23.114540 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3076 00:22:23.114592 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3077 00:22:23.114671 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3078 00:22:23.114789 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3079 00:22:23.114845 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3080 00:22:23.114894 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3081 00:22:23.114944
3082 00:22:23.114994 CA PerBit enable=1, Macro0, CA PI delay=33
3083 00:22:23.115044
3084 00:22:23.115093 [CBTSetCACLKResult] CA Dly = 33
3085 00:22:23.115143 CS Dly: 5 (0~36)
3086 00:22:23.115193 ==
3087 00:22:23.115242 Dram Type= 6, Freq= 0, CH_1, rank 1
3088 00:22:23.115291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3089 00:22:23.115342 ==
3090 00:22:23.115391 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3091 00:22:23.115441 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3092 00:22:23.115491 [CA 0] Center 37 (8~67) winsize 60
3093 00:22:23.115540 [CA 1] Center 37 (7~68) winsize 62
3094 00:22:23.115590 [CA 2] Center 34 (4~65) winsize 62
3095 00:22:23.115672 [CA 3] Center 33 (3~64) winsize 62
3096 00:22:23.115725 [CA 4] Center 34 (4~65) winsize 62
3097 00:22:23.115775 [CA 5] Center 32 (2~63) winsize 62
3098 00:22:23.115824
3099 00:22:23.115873 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3100 00:22:23.115923
3101 00:22:23.115972 [CATrainingPosCal] consider 2 rank data
3102 00:22:23.116023 u2DelayCellTimex100 = 270/100 ps
3103 00:22:23.116072 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3104 00:22:23.116122 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3105 00:22:23.116182 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3106 00:22:23.116246 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3107 00:22:23.116296 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3108 00:22:23.116346 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3109 00:22:23.116396
3110 00:22:23.116447 CA PerBit enable=1, Macro0, CA PI delay=33
3111 00:22:23.116497
3112 00:22:23.116546 [CBTSetCACLKResult] CA Dly = 33
3113 00:22:23.116597 CS Dly: 6 (0~39)
3114 00:22:23.116653
3115 00:22:23.116706 ----->DramcWriteLeveling(PI) begin...
3116 00:22:23.116759 ==
3117 00:22:23.116836 Dram Type= 6, Freq= 0, CH_1, rank 0
3118 00:22:23.116895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3119 00:22:23.116969 ==
3120 00:22:23.117020 Write leveling (Byte 0): 26 => 26
3121 00:22:23.117071 Write leveling (Byte 1): 29 => 29
3122 00:22:23.117121 DramcWriteLeveling(PI) end<-----
3123 00:22:23.117171
3124 00:22:23.117220 ==
3125 00:22:23.117270 Dram Type= 6, Freq= 0, CH_1, rank 0
3126 00:22:23.117320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3127 00:22:23.117383 ==
3128 00:22:23.117469 [Gating] SW mode calibration
3129 00:22:23.117569 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3130 00:22:23.117626 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3131 00:22:23.117678 0 15 0 | B1->B0 | 2f2f 2b2b | 0 0 | (0 0) (0 0)
3132 00:22:23.117753 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3133 00:22:23.117805 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3134 00:22:23.118053 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3135 00:22:23.118153 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3136 00:22:23.118239 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3137 00:22:23.118366 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3138 00:22:23.118496 0 15 28 | B1->B0 | 2d2d 2c2c | 1 1 | (1 0) (1 0)
3139 00:22:23.118593 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3140 00:22:23.118679 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3141 00:22:23.118760 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3142 00:22:23.118839 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3143 00:22:23.118917 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3144 00:22:23.118996 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3145 00:22:23.119075 1 0 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3146 00:22:23.119141 1 0 28 | B1->B0 | 3f3f 4141 | 0 0 | (0 0) (0 0)
3147 00:22:23.119193 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3148 00:22:23.119271 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3149 00:22:23.119350 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3150 00:22:23.119429 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3151 00:22:23.119508 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3152 00:22:23.119587 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3153 00:22:23.119666 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3154 00:22:23.119745 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3155 00:22:23.119823 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3156 00:22:23.119902 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 00:22:23.119981 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 00:22:23.120075 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 00:22:23.120151 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 00:22:23.120228 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 00:22:23.120320 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 00:22:23.120416 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 00:22:23.120493 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 00:22:23.120589 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 00:22:23.120686 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 00:22:23.120738 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 00:22:23.120787 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 00:22:23.120836 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 00:22:23.120885 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 00:22:23.120955 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3171 00:22:23.121033 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3172 00:22:23.121082 Total UI for P1: 0, mck2ui 16
3173 00:22:23.121133 best dqsien dly found for B1: ( 1, 3, 28)
3174 00:22:23.121222 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3175 00:22:23.121275 Total UI for P1: 0, mck2ui 16
3176 00:22:23.121326 best dqsien dly found for B0: ( 1, 3, 30)
3177 00:22:23.121374 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3178 00:22:23.121423 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3179 00:22:23.121471
3180 00:22:23.121520 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3181 00:22:23.121569 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3182 00:22:23.121632 [Gating] SW calibration Done
3183 00:22:23.121682 ==
3184 00:22:23.121731 Dram Type= 6, Freq= 0, CH_1, rank 0
3185 00:22:23.121781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3186 00:22:23.121831 ==
3187 00:22:23.121881 RX Vref Scan: 0
3188 00:22:23.121929
3189 00:22:23.121978 RX Vref 0 -> 0, step: 1
3190 00:22:23.122027
3191 00:22:23.122090 RX Delay -40 -> 252, step: 8
3192 00:22:23.122138 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3193 00:22:23.122187 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3194 00:22:23.122236 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3195 00:22:23.122284 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3196 00:22:23.122333 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3197 00:22:23.122381 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3198 00:22:23.122429 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3199 00:22:23.122478 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3200 00:22:23.122526 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3201 00:22:23.122574 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3202 00:22:23.122622 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3203 00:22:23.122669 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3204 00:22:23.122718 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3205 00:22:23.122777 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3206 00:22:23.122862 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3207 00:22:23.122927 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3208 00:22:23.122977 ==
3209 00:22:23.123027 Dram Type= 6, Freq= 0, CH_1, rank 0
3210 00:22:23.123077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3211 00:22:23.123127 ==
3212 00:22:23.123176 DQS Delay:
3213 00:22:23.123226 DQS0 = 0, DQS1 = 0
3214 00:22:23.123275 DQM Delay:
3215 00:22:23.123324 DQM0 = 114, DQM1 = 106
3216 00:22:23.123374 DQ Delay:
3217 00:22:23.123423 DQ0 =119, DQ1 =107, DQ2 =103, DQ3 =115
3218 00:22:23.123473 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3219 00:22:23.123523 DQ8 =95, DQ9 =99, DQ10 =103, DQ11 =103
3220 00:22:23.123572 DQ12 =115, DQ13 =115, DQ14 =111, DQ15 =111
3221 00:22:23.123620
3222 00:22:23.123669
3223 00:22:23.123731 ==
3224 00:22:23.123780 Dram Type= 6, Freq= 0, CH_1, rank 0
3225 00:22:23.123829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3226 00:22:23.123877 ==
3227 00:22:23.123954
3228 00:22:23.124002
3229 00:22:23.124050 TX Vref Scan disable
3230 00:22:23.124128 == TX Byte 0 ==
3231 00:22:23.124193 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3232 00:22:23.124272 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3233 00:22:23.124325 == TX Byte 1 ==
3234 00:22:23.124416 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3235 00:22:23.124497 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3236 00:22:23.124574 ==
3237 00:22:23.124658 Dram Type= 6, Freq= 0, CH_1, rank 0
3238 00:22:23.124725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3239 00:22:23.124775 ==
3240 00:22:23.124824 TX Vref=22, minBit 11, minWin=24, winSum=412
3241 00:22:23.124874 TX Vref=24, minBit 8, minWin=25, winSum=415
3242 00:22:23.125111 TX Vref=26, minBit 8, minWin=25, winSum=422
3243 00:22:23.125165 TX Vref=28, minBit 5, minWin=26, winSum=428
3244 00:22:23.125215 TX Vref=30, minBit 9, minWin=25, winSum=425
3245 00:22:23.125264 TX Vref=32, minBit 9, minWin=25, winSum=424
3246 00:22:23.125330 [TxChooseVref] Worse bit 5, Min win 26, Win sum 428, Final Vref 28
3247 00:22:23.125381
3248 00:22:23.125444 Final TX Range 1 Vref 28
3249 00:22:23.125525
3250 00:22:23.125573 ==
3251 00:22:23.125620 Dram Type= 6, Freq= 0, CH_1, rank 0
3252 00:22:23.125668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3253 00:22:23.125716 ==
3254 00:22:23.125781
3255 00:22:23.125828
3256 00:22:23.125909 TX Vref Scan disable
3257 00:22:23.125971 == TX Byte 0 ==
3258 00:22:23.126019 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3259 00:22:23.126067 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3260 00:22:23.126116 == TX Byte 1 ==
3261 00:22:23.126163 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3262 00:22:23.126211 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3263 00:22:23.126260
3264 00:22:23.126307 [DATLAT]
3265 00:22:23.126354 Freq=1200, CH1 RK0
3266 00:22:23.126402
3267 00:22:23.126449 DATLAT Default: 0xd
3268 00:22:23.126496 0, 0xFFFF, sum = 0
3269 00:22:23.126546 1, 0xFFFF, sum = 0
3270 00:22:23.126595 2, 0xFFFF, sum = 0
3271 00:22:23.126644 3, 0xFFFF, sum = 0
3272 00:22:23.126693 4, 0xFFFF, sum = 0
3273 00:22:23.126741 5, 0xFFFF, sum = 0
3274 00:22:23.126790 6, 0xFFFF, sum = 0
3275 00:22:23.126838 7, 0xFFFF, sum = 0
3276 00:22:23.126886 8, 0xFFFF, sum = 0
3277 00:22:23.126936 9, 0xFFFF, sum = 0
3278 00:22:23.126985 10, 0xFFFF, sum = 0
3279 00:22:23.127034 11, 0xFFFF, sum = 0
3280 00:22:23.127083 12, 0x0, sum = 1
3281 00:22:23.127131 13, 0x0, sum = 2
3282 00:22:23.127179 14, 0x0, sum = 3
3283 00:22:23.127228 15, 0x0, sum = 4
3284 00:22:23.127277 best_step = 13
3285 00:22:23.127325
3286 00:22:23.127372 ==
3287 00:22:23.127420 Dram Type= 6, Freq= 0, CH_1, rank 0
3288 00:22:23.127480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3289 00:22:23.127531 ==
3290 00:22:23.127579 RX Vref Scan: 1
3291 00:22:23.127627
3292 00:22:23.127675 Set Vref Range= 32 -> 127
3293 00:22:23.127722
3294 00:22:23.127771 RX Vref 32 -> 127, step: 1
3295 00:22:23.127818
3296 00:22:23.127895 RX Delay -21 -> 252, step: 4
3297 00:22:23.127987
3298 00:22:23.128065 Set Vref, RX VrefLevel [Byte0]: 32
3299 00:22:23.128118 [Byte1]: 32
3300 00:22:23.128168
3301 00:22:23.128217 Set Vref, RX VrefLevel [Byte0]: 33
3302 00:22:23.128266 [Byte1]: 33
3303 00:22:23.128315
3304 00:22:23.128364 Set Vref, RX VrefLevel [Byte0]: 34
3305 00:22:23.128414 [Byte1]: 34
3306 00:22:23.128463
3307 00:22:23.128511 Set Vref, RX VrefLevel [Byte0]: 35
3308 00:22:23.128560 [Byte1]: 35
3309 00:22:23.128608
3310 00:22:23.128664 Set Vref, RX VrefLevel [Byte0]: 36
3311 00:22:23.128793 [Byte1]: 36
3312 00:22:23.128856
3313 00:22:23.128904 Set Vref, RX VrefLevel [Byte0]: 37
3314 00:22:23.128952 [Byte1]: 37
3315 00:22:23.129019
3316 00:22:23.129067 Set Vref, RX VrefLevel [Byte0]: 38
3317 00:22:23.129116 [Byte1]: 38
3318 00:22:23.129164
3319 00:22:23.129213 Set Vref, RX VrefLevel [Byte0]: 39
3320 00:22:23.129261 [Byte1]: 39
3321 00:22:23.129323
3322 00:22:23.129370 Set Vref, RX VrefLevel [Byte0]: 40
3323 00:22:23.129418 [Byte1]: 40
3324 00:22:23.129483
3325 00:22:23.129589 Set Vref, RX VrefLevel [Byte0]: 41
3326 00:22:23.129640 [Byte1]: 41
3327 00:22:23.129689
3328 00:22:23.129737 Set Vref, RX VrefLevel [Byte0]: 42
3329 00:22:23.129784 [Byte1]: 42
3330 00:22:23.129831
3331 00:22:23.129878 Set Vref, RX VrefLevel [Byte0]: 43
3332 00:22:23.129925 [Byte1]: 43
3333 00:22:23.129972
3334 00:22:23.130020 Set Vref, RX VrefLevel [Byte0]: 44
3335 00:22:23.130067 [Byte1]: 44
3336 00:22:23.130160
3337 00:22:23.130223 Set Vref, RX VrefLevel [Byte0]: 45
3338 00:22:23.130271 [Byte1]: 45
3339 00:22:23.130318
3340 00:22:23.130364 Set Vref, RX VrefLevel [Byte0]: 46
3341 00:22:23.130411 [Byte1]: 46
3342 00:22:23.130458
3343 00:22:23.130505 Set Vref, RX VrefLevel [Byte0]: 47
3344 00:22:23.130553 [Byte1]: 47
3345 00:22:23.130600
3346 00:22:23.130647 Set Vref, RX VrefLevel [Byte0]: 48
3347 00:22:23.130739 [Byte1]: 48
3348 00:22:23.130993
3349 00:22:23.131110 Set Vref, RX VrefLevel [Byte0]: 49
3350 00:22:23.131194 [Byte1]: 49
3351 00:22:23.131261
3352 00:22:23.131356 Set Vref, RX VrefLevel [Byte0]: 50
3353 00:22:23.131406 [Byte1]: 50
3354 00:22:23.131455
3355 00:22:23.131504 Set Vref, RX VrefLevel [Byte0]: 51
3356 00:22:23.131553 [Byte1]: 51
3357 00:22:23.131601
3358 00:22:23.131663 Set Vref, RX VrefLevel [Byte0]: 52
3359 00:22:23.131727 [Byte1]: 52
3360 00:22:23.131808
3361 00:22:23.131995 Set Vref, RX VrefLevel [Byte0]: 53
3362 00:22:23.132183 [Byte1]: 53
3363 00:22:23.132276
3364 00:22:23.132359 Set Vref, RX VrefLevel [Byte0]: 54
3365 00:22:23.132437 [Byte1]: 54
3366 00:22:23.132515
3367 00:22:23.132592 Set Vref, RX VrefLevel [Byte0]: 55
3368 00:22:23.132687 [Byte1]: 55
3369 00:22:23.132738
3370 00:22:23.132787 Set Vref, RX VrefLevel [Byte0]: 56
3371 00:22:23.132835 [Byte1]: 56
3372 00:22:23.132883
3373 00:22:23.132931 Set Vref, RX VrefLevel [Byte0]: 57
3374 00:22:23.132979 [Byte1]: 57
3375 00:22:23.133026
3376 00:22:23.133090 Set Vref, RX VrefLevel [Byte0]: 58
3377 00:22:23.133181 [Byte1]: 58
3378 00:22:23.133228
3379 00:22:23.133275 Set Vref, RX VrefLevel [Byte0]: 59
3380 00:22:23.133324 [Byte1]: 59
3381 00:22:23.133372
3382 00:22:23.133420 Set Vref, RX VrefLevel [Byte0]: 60
3383 00:22:23.133468 [Byte1]: 60
3384 00:22:23.133515
3385 00:22:23.133562 Set Vref, RX VrefLevel [Byte0]: 61
3386 00:22:23.133610 [Byte1]: 61
3387 00:22:23.133657
3388 00:22:23.133704 Set Vref, RX VrefLevel [Byte0]: 62
3389 00:22:23.133751 [Byte1]: 62
3390 00:22:23.133799
3391 00:22:23.133846 Set Vref, RX VrefLevel [Byte0]: 63
3392 00:22:23.133894 [Byte1]: 63
3393 00:22:23.133941
3394 00:22:23.133988 Set Vref, RX VrefLevel [Byte0]: 64
3395 00:22:23.134036 [Byte1]: 64
3396 00:22:23.134083
3397 00:22:23.134131 Set Vref, RX VrefLevel [Byte0]: 65
3398 00:22:23.134204 [Byte1]: 65
3399 00:22:23.134269
3400 00:22:23.134316 Set Vref, RX VrefLevel [Byte0]: 66
3401 00:22:23.134364 [Byte1]: 66
3402 00:22:23.134412
3403 00:22:23.134460 Set Vref, RX VrefLevel [Byte0]: 67
3404 00:22:23.134523 [Byte1]: 67
3405 00:22:23.134587
3406 00:22:23.134634 Set Vref, RX VrefLevel [Byte0]: 68
3407 00:22:23.134681 [Byte1]: 68
3408 00:22:23.134729
3409 00:22:23.134790 Set Vref, RX VrefLevel [Byte0]: 69
3410 00:22:23.135044 [Byte1]: 69
3411 00:22:23.135129
3412 00:22:23.135194 Final RX Vref Byte 0 = 55 to rank0
3413 00:22:23.135243 Final RX Vref Byte 1 = 49 to rank0
3414 00:22:23.135292 Final RX Vref Byte 0 = 55 to rank1
3415 00:22:23.135355 Final RX Vref Byte 1 = 49 to rank1==
3416 00:22:23.135419 Dram Type= 6, Freq= 0, CH_1, rank 0
3417 00:22:23.135467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3418 00:22:23.135515 ==
3419 00:22:23.135563 DQS Delay:
3420 00:22:23.135610 DQS0 = 0, DQS1 = 0
3421 00:22:23.135658 DQM Delay:
3422 00:22:23.135707 DQM0 = 114, DQM1 = 105
3423 00:22:23.135754 DQ Delay:
3424 00:22:23.135801 DQ0 =118, DQ1 =110, DQ2 =104, DQ3 =112
3425 00:22:23.135849 DQ4 =112, DQ5 =122, DQ6 =126, DQ7 =112
3426 00:22:23.135912 DQ8 =92, DQ9 =98, DQ10 =104, DQ11 =100
3427 00:22:23.135975 DQ12 =114, DQ13 =110, DQ14 =112, DQ15 =110
3428 00:22:23.136021
3429 00:22:23.136068
3430 00:22:23.136146 [DQSOSCAuto] RK0, (LSB)MR18= 0xf3fa, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 415 ps
3431 00:22:23.136196 CH1 RK0: MR19=303, MR18=F3FA
3432 00:22:23.136259 CH1_RK0: MR19=0x303, MR18=0xF3FA, DQSOSC=412, MR23=63, INC=38, DEC=25
3433 00:22:23.136337
3434 00:22:23.136386 ----->DramcWriteLeveling(PI) begin...
3435 00:22:23.136436 ==
3436 00:22:23.136485 Dram Type= 6, Freq= 0, CH_1, rank 1
3437 00:22:23.136534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3438 00:22:23.136583 ==
3439 00:22:23.136631 Write leveling (Byte 0): 23 => 23
3440 00:22:23.136723 Write leveling (Byte 1): 29 => 29
3441 00:22:23.136786 DramcWriteLeveling(PI) end<-----
3442 00:22:23.136834
3443 00:22:23.136898 ==
3444 00:22:23.136961 Dram Type= 6, Freq= 0, CH_1, rank 1
3445 00:22:23.137009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3446 00:22:23.137075 ==
3447 00:22:23.137137 [Gating] SW mode calibration
3448 00:22:23.137185 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3449 00:22:23.137233 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3450 00:22:23.137298 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3451 00:22:23.137362 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3452 00:22:23.137410 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3453 00:22:23.137458 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3454 00:22:23.137505 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3455 00:22:23.137553 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3456 00:22:23.137601 0 15 24 | B1->B0 | 3333 2626 | 0 0 | (0 1) (1 0)
3457 00:22:23.137648 0 15 28 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
3458 00:22:23.137695 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3459 00:22:23.137743 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3460 00:22:23.137792 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3461 00:22:23.137840 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3462 00:22:23.137888 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3463 00:22:23.137936 1 0 20 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
3464 00:22:23.137983 1 0 24 | B1->B0 | 2f2f 4646 | 0 0 | (0 0) (0 0)
3465 00:22:23.138031 1 0 28 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
3466 00:22:23.138078 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3467 00:22:23.138126 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3468 00:22:23.138174 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3469 00:22:23.138221 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3470 00:22:23.138268 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3471 00:22:23.138315 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3472 00:22:23.138363 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3473 00:22:23.138410 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3474 00:22:23.138457 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 00:22:23.138505 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 00:22:23.138553 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 00:22:23.138601 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 00:22:23.138648 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 00:22:23.138696 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 00:22:23.138744 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 00:22:23.138791 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 00:22:23.138838 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 00:22:23.138886 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 00:22:23.138933 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 00:22:23.138981 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 00:22:23.139029 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 00:22:23.139077 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3488 00:22:23.139124 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3489 00:22:23.139171 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3490 00:22:23.139218 Total UI for P1: 0, mck2ui 16
3491 00:22:23.139266 best dqsien dly found for B0: ( 1, 3, 22)
3492 00:22:23.139314 Total UI for P1: 0, mck2ui 16
3493 00:22:23.139362 best dqsien dly found for B1: ( 1, 3, 24)
3494 00:22:23.139424 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3495 00:22:23.139474 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3496 00:22:23.139522
3497 00:22:23.139570 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3498 00:22:23.139618 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3499 00:22:23.139666 [Gating] SW calibration Done
3500 00:22:23.139713 ==
3501 00:22:23.139760 Dram Type= 6, Freq= 0, CH_1, rank 1
3502 00:22:23.139808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3503 00:22:23.139856 ==
3504 00:22:23.139904 RX Vref Scan: 0
3505 00:22:23.139951
3506 00:22:23.139997 RX Vref 0 -> 0, step: 1
3507 00:22:23.140045
3508 00:22:23.140092 RX Delay -40 -> 252, step: 8
3509 00:22:23.140139 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3510 00:22:23.140186 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3511 00:22:23.140234 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3512 00:22:23.140281 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3513 00:22:23.140329 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3514 00:22:23.140376 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3515 00:22:23.140424 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3516 00:22:23.140698 iDelay=200, Bit 7, Center 107 (32 ~ 183) 152
3517 00:22:23.140752 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
3518 00:22:23.140801 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3519 00:22:23.140849 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3520 00:22:23.140897 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3521 00:22:23.140946 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3522 00:22:23.141012 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3523 00:22:23.141074 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3524 00:22:23.141121 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3525 00:22:23.141169 ==
3526 00:22:23.141216 Dram Type= 6, Freq= 0, CH_1, rank 1
3527 00:22:23.141263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3528 00:22:23.141311 ==
3529 00:22:23.141360 DQS Delay:
3530 00:22:23.141408 DQS0 = 0, DQS1 = 0
3531 00:22:23.141455 DQM Delay:
3532 00:22:23.141503 DQM0 = 110, DQM1 = 105
3533 00:22:23.141551 DQ Delay:
3534 00:22:23.141599 DQ0 =115, DQ1 =107, DQ2 =99, DQ3 =107
3535 00:22:23.141647 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =107
3536 00:22:23.141695 DQ8 =91, DQ9 =95, DQ10 =111, DQ11 =99
3537 00:22:23.141743 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =111
3538 00:22:23.141791
3539 00:22:23.141838
3540 00:22:23.141885 ==
3541 00:22:23.141932 Dram Type= 6, Freq= 0, CH_1, rank 1
3542 00:22:23.141980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3543 00:22:23.142028 ==
3544 00:22:23.142075
3545 00:22:23.142122
3546 00:22:23.142169 TX Vref Scan disable
3547 00:22:23.142216 == TX Byte 0 ==
3548 00:22:23.142263 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3549 00:22:23.142311 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3550 00:22:23.142359 == TX Byte 1 ==
3551 00:22:23.142407 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3552 00:22:23.142455 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3553 00:22:23.142503 ==
3554 00:22:23.142550 Dram Type= 6, Freq= 0, CH_1, rank 1
3555 00:22:23.142598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3556 00:22:23.142646 ==
3557 00:22:23.142693 TX Vref=22, minBit 0, minWin=25, winSum=419
3558 00:22:23.142767 TX Vref=24, minBit 4, minWin=26, winSum=427
3559 00:22:23.142819 TX Vref=26, minBit 9, minWin=25, winSum=430
3560 00:22:23.142868 TX Vref=28, minBit 0, minWin=26, winSum=432
3561 00:22:23.142917 TX Vref=30, minBit 9, minWin=26, winSum=434
3562 00:22:23.142965 TX Vref=32, minBit 1, minWin=26, winSum=427
3563 00:22:23.143013 [TxChooseVref] Worse bit 9, Min win 26, Win sum 434, Final Vref 30
3564 00:22:23.143091
3565 00:22:23.143138 Final TX Range 1 Vref 30
3566 00:22:23.143186
3567 00:22:23.143234 ==
3568 00:22:23.143282 Dram Type= 6, Freq= 0, CH_1, rank 1
3569 00:22:23.143330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3570 00:22:23.143379 ==
3571 00:22:23.143426
3572 00:22:23.143473
3573 00:22:23.143520 TX Vref Scan disable
3574 00:22:23.143568 == TX Byte 0 ==
3575 00:22:23.143616 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3576 00:22:23.143664 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3577 00:22:23.143712 == TX Byte 1 ==
3578 00:22:23.143760 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3579 00:22:23.143808 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3580 00:22:23.143855
3581 00:22:23.143903 [DATLAT]
3582 00:22:23.143950 Freq=1200, CH1 RK1
3583 00:22:23.143997
3584 00:22:23.144044 DATLAT Default: 0xd
3585 00:22:23.144091 0, 0xFFFF, sum = 0
3586 00:22:23.144139 1, 0xFFFF, sum = 0
3587 00:22:23.144190 2, 0xFFFF, sum = 0
3588 00:22:23.144263 3, 0xFFFF, sum = 0
3589 00:22:23.144343 4, 0xFFFF, sum = 0
3590 00:22:23.144392 5, 0xFFFF, sum = 0
3591 00:22:23.144440 6, 0xFFFF, sum = 0
3592 00:22:23.144489 7, 0xFFFF, sum = 0
3593 00:22:23.144536 8, 0xFFFF, sum = 0
3594 00:22:23.144585 9, 0xFFFF, sum = 0
3595 00:22:23.144633 10, 0xFFFF, sum = 0
3596 00:22:23.144719 11, 0xFFFF, sum = 0
3597 00:22:23.144768 12, 0x0, sum = 1
3598 00:22:23.144816 13, 0x0, sum = 2
3599 00:22:23.144865 14, 0x0, sum = 3
3600 00:22:23.144912 15, 0x0, sum = 4
3601 00:22:23.144960 best_step = 13
3602 00:22:23.145037
3603 00:22:23.145084 ==
3604 00:22:23.145132 Dram Type= 6, Freq= 0, CH_1, rank 1
3605 00:22:23.145179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3606 00:22:23.145227 ==
3607 00:22:23.145274 RX Vref Scan: 0
3608 00:22:23.145322
3609 00:22:23.145368 RX Vref 0 -> 0, step: 1
3610 00:22:23.145415
3611 00:22:23.145462 RX Delay -21 -> 252, step: 4
3612 00:22:23.145510 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3613 00:22:23.145559 iDelay=195, Bit 1, Center 106 (39 ~ 174) 136
3614 00:22:23.145607 iDelay=195, Bit 2, Center 100 (31 ~ 170) 140
3615 00:22:23.145671 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3616 00:22:23.145721 iDelay=195, Bit 4, Center 110 (43 ~ 178) 136
3617 00:22:23.145769 iDelay=195, Bit 5, Center 120 (47 ~ 194) 148
3618 00:22:23.145818 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3619 00:22:23.145867 iDelay=195, Bit 7, Center 110 (43 ~ 178) 136
3620 00:22:23.145915 iDelay=195, Bit 8, Center 94 (31 ~ 158) 128
3621 00:22:23.145964 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3622 00:22:23.146012 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3623 00:22:23.146060 iDelay=195, Bit 11, Center 100 (35 ~ 166) 132
3624 00:22:23.146108 iDelay=195, Bit 12, Center 116 (51 ~ 182) 132
3625 00:22:23.146156 iDelay=195, Bit 13, Center 116 (51 ~ 182) 132
3626 00:22:23.146204 iDelay=195, Bit 14, Center 116 (55 ~ 178) 124
3627 00:22:23.146253 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3628 00:22:23.146300 ==
3629 00:22:23.146348 Dram Type= 6, Freq= 0, CH_1, rank 1
3630 00:22:23.146396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3631 00:22:23.146445 ==
3632 00:22:23.146493 DQS Delay:
3633 00:22:23.146540 DQS0 = 0, DQS1 = 0
3634 00:22:23.146588 DQM Delay:
3635 00:22:23.146636 DQM0 = 111, DQM1 = 108
3636 00:22:23.146685 DQ Delay:
3637 00:22:23.146731 DQ0 =114, DQ1 =106, DQ2 =100, DQ3 =108
3638 00:22:23.146779 DQ4 =110, DQ5 =120, DQ6 =120, DQ7 =110
3639 00:22:23.146827 DQ8 =94, DQ9 =100, DQ10 =110, DQ11 =100
3640 00:22:23.146875 DQ12 =116, DQ13 =116, DQ14 =116, DQ15 =116
3641 00:22:23.146922
3642 00:22:23.146987
3643 00:22:23.147051 [DQSOSCAuto] RK1, (LSB)MR18= 0xfe0d, (MSB)MR19= 0x304, tDQSOscB0 = 405 ps tDQSOscB1 = 410 ps
3644 00:22:23.147100 CH1 RK1: MR19=304, MR18=FE0D
3645 00:22:23.147149 CH1_RK1: MR19=0x304, MR18=0xFE0D, DQSOSC=405, MR23=63, INC=39, DEC=26
3646 00:22:23.147197 [RxdqsGatingPostProcess] freq 1200
3647 00:22:23.147261 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3648 00:22:23.147325 best DQS0 dly(2T, 0.5T) = (0, 11)
3649 00:22:23.147373 best DQS1 dly(2T, 0.5T) = (0, 11)
3650 00:22:23.147421 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3651 00:22:23.147469 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3652 00:22:23.147516 best DQS0 dly(2T, 0.5T) = (0, 11)
3653 00:22:23.147563 best DQS1 dly(2T, 0.5T) = (0, 11)
3654 00:22:23.147611 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3655 00:22:23.147850 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3656 00:22:23.147908 Pre-setting of DQS Precalculation
3657 00:22:23.147958 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3658 00:22:23.148008 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3659 00:22:23.148057 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3660 00:22:23.148105
3661 00:22:23.148152
3662 00:22:23.148199 [Calibration Summary] 2400 Mbps
3663 00:22:23.148247 CH 0, Rank 0
3664 00:22:23.148295 SW Impedance : PASS
3665 00:22:23.148343 DUTY Scan : NO K
3666 00:22:23.148391 ZQ Calibration : PASS
3667 00:22:23.148438 Jitter Meter : NO K
3668 00:22:23.148486 CBT Training : PASS
3669 00:22:23.148533 Write leveling : PASS
3670 00:22:23.148580 RX DQS gating : PASS
3671 00:22:23.148628 RX DQ/DQS(RDDQC) : PASS
3672 00:22:23.148718 TX DQ/DQS : PASS
3673 00:22:23.148767 RX DATLAT : PASS
3674 00:22:23.148815 RX DQ/DQS(Engine): PASS
3675 00:22:23.148862 TX OE : NO K
3676 00:22:23.148910 All Pass.
3677 00:22:23.148957
3678 00:22:23.149050 CH 0, Rank 1
3679 00:22:23.149100 SW Impedance : PASS
3680 00:22:23.149147 DUTY Scan : NO K
3681 00:22:23.149195 ZQ Calibration : PASS
3682 00:22:23.149242 Jitter Meter : NO K
3683 00:22:23.149289 CBT Training : PASS
3684 00:22:23.149337 Write leveling : PASS
3685 00:22:23.149384 RX DQS gating : PASS
3686 00:22:23.149431 RX DQ/DQS(RDDQC) : PASS
3687 00:22:23.149478 TX DQ/DQS : PASS
3688 00:22:23.149526 RX DATLAT : PASS
3689 00:22:23.149574 RX DQ/DQS(Engine): PASS
3690 00:22:23.149621 TX OE : NO K
3691 00:22:23.149668 All Pass.
3692 00:22:23.149714
3693 00:22:23.149761 CH 1, Rank 0
3694 00:22:23.149808 SW Impedance : PASS
3695 00:22:23.149855 DUTY Scan : NO K
3696 00:22:23.149902 ZQ Calibration : PASS
3697 00:22:23.149951 Jitter Meter : NO K
3698 00:22:23.150000 CBT Training : PASS
3699 00:22:23.150047 Write leveling : PASS
3700 00:22:23.150095 RX DQS gating : PASS
3701 00:22:23.150142 RX DQ/DQS(RDDQC) : PASS
3702 00:22:23.150190 TX DQ/DQS : PASS
3703 00:22:23.150237 RX DATLAT : PASS
3704 00:22:23.150283 RX DQ/DQS(Engine): PASS
3705 00:22:23.150331 TX OE : NO K
3706 00:22:23.150378 All Pass.
3707 00:22:23.150426
3708 00:22:23.150473 CH 1, Rank 1
3709 00:22:23.150521 SW Impedance : PASS
3710 00:22:23.150568 DUTY Scan : NO K
3711 00:22:23.150616 ZQ Calibration : PASS
3712 00:22:23.150663 Jitter Meter : NO K
3713 00:22:23.150711 CBT Training : PASS
3714 00:22:23.150758 Write leveling : PASS
3715 00:22:23.150805 RX DQS gating : PASS
3716 00:22:23.150852 RX DQ/DQS(RDDQC) : PASS
3717 00:22:23.150899 TX DQ/DQS : PASS
3718 00:22:23.150947 RX DATLAT : PASS
3719 00:22:23.151006 RX DQ/DQS(Engine): PASS
3720 00:22:23.151084 TX OE : NO K
3721 00:22:23.151147 All Pass.
3722 00:22:23.151195
3723 00:22:23.151242 DramC Write-DBI off
3724 00:22:23.151289 PER_BANK_REFRESH: Hybrid Mode
3725 00:22:23.151337 TX_TRACKING: ON
3726 00:22:23.151385 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3727 00:22:23.151435 [FAST_K] Save calibration result to emmc
3728 00:22:23.151484 dramc_set_vcore_voltage set vcore to 650000
3729 00:22:23.151532 Read voltage for 600, 5
3730 00:22:23.151579 Vio18 = 0
3731 00:22:23.151626 Vcore = 650000
3732 00:22:23.151673 Vdram = 0
3733 00:22:23.151720 Vddq = 0
3734 00:22:23.151767 Vmddr = 0
3735 00:22:23.151815 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3736 00:22:23.151863 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3737 00:22:23.151911 MEM_TYPE=3, freq_sel=19
3738 00:22:23.151958 sv_algorithm_assistance_LP4_1600
3739 00:22:23.152006 ============ PULL DRAM RESETB DOWN ============
3740 00:22:23.152056 ========== PULL DRAM RESETB DOWN end =========
3741 00:22:23.152104 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3742 00:22:23.152152 ===================================
3743 00:22:23.152199 LPDDR4 DRAM CONFIGURATION
3744 00:22:23.152247 ===================================
3745 00:22:23.152295 EX_ROW_EN[0] = 0x0
3746 00:22:23.152342 EX_ROW_EN[1] = 0x0
3747 00:22:23.152389 LP4Y_EN = 0x0
3748 00:22:23.152437 WORK_FSP = 0x0
3749 00:22:23.152484 WL = 0x2
3750 00:22:23.152531 RL = 0x2
3751 00:22:23.152578 BL = 0x2
3752 00:22:23.152624 RPST = 0x0
3753 00:22:23.152698 RD_PRE = 0x0
3754 00:22:23.152793 WR_PRE = 0x1
3755 00:22:23.152901 WR_PST = 0x0
3756 00:22:23.153139 DBI_WR = 0x0
3757 00:22:23.153270 DBI_RD = 0x0
3758 00:22:23.153361 OTF = 0x1
3759 00:22:23.153413 ===================================
3760 00:22:23.153464 ===================================
3761 00:22:23.153513 ANA top config
3762 00:22:23.153563 ===================================
3763 00:22:23.153612 DLL_ASYNC_EN = 0
3764 00:22:23.153661 ALL_SLAVE_EN = 1
3765 00:22:23.153709 NEW_RANK_MODE = 1
3766 00:22:23.153758 DLL_IDLE_MODE = 1
3767 00:22:23.153807 LP45_APHY_COMB_EN = 1
3768 00:22:23.153855 TX_ODT_DIS = 1
3769 00:22:23.153904 NEW_8X_MODE = 1
3770 00:22:23.153953 ===================================
3771 00:22:23.154002 ===================================
3772 00:22:23.154052 data_rate = 1200
3773 00:22:23.154114 CKR = 1
3774 00:22:23.154162 DQ_P2S_RATIO = 8
3775 00:22:23.154209 ===================================
3776 00:22:23.154270 CA_P2S_RATIO = 8
3777 00:22:23.154331 DQ_CA_OPEN = 0
3778 00:22:23.154379 DQ_SEMI_OPEN = 0
3779 00:22:23.154427 CA_SEMI_OPEN = 0
3780 00:22:23.154475 CA_FULL_RATE = 0
3781 00:22:23.154553 DQ_CKDIV4_EN = 1
3782 00:22:23.154619 CA_CKDIV4_EN = 1
3783 00:22:23.154666 CA_PREDIV_EN = 0
3784 00:22:23.154714 PH8_DLY = 0
3785 00:22:23.154761 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3786 00:22:23.154808 DQ_AAMCK_DIV = 4
3787 00:22:23.154855 CA_AAMCK_DIV = 4
3788 00:22:23.154903 CA_ADMCK_DIV = 4
3789 00:22:23.154952 DQ_TRACK_CA_EN = 0
3790 00:22:23.155000 CA_PICK = 600
3791 00:22:23.155047 CA_MCKIO = 600
3792 00:22:23.155094 MCKIO_SEMI = 0
3793 00:22:23.155174 PLL_FREQ = 2288
3794 00:22:23.155222 DQ_UI_PI_RATIO = 32
3795 00:22:23.155269 CA_UI_PI_RATIO = 0
3796 00:22:23.155316 ===================================
3797 00:22:23.155364 ===================================
3798 00:22:23.155412 memory_type:LPDDR4
3799 00:22:23.155460 GP_NUM : 10
3800 00:22:23.155507 SRAM_EN : 1
3801 00:22:23.155555 MD32_EN : 0
3802 00:22:23.155804 ===================================
3803 00:22:23.155860 [ANA_INIT] >>>>>>>>>>>>>>
3804 00:22:23.155910 <<<<<< [CONFIGURE PHASE]: ANA_TX
3805 00:22:23.155959 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3806 00:22:23.156007 ===================================
3807 00:22:23.156055 data_rate = 1200,PCW = 0X5800
3808 00:22:23.156102 ===================================
3809 00:22:23.156151 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3810 00:22:23.156200 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3811 00:22:23.156248 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3812 00:22:23.156311 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3813 00:22:23.156361 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3814 00:22:23.156410 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3815 00:22:23.156459 [ANA_INIT] flow start
3816 00:22:23.156508 [ANA_INIT] PLL >>>>>>>>
3817 00:22:23.156556 [ANA_INIT] PLL <<<<<<<<
3818 00:22:23.156605 [ANA_INIT] MIDPI >>>>>>>>
3819 00:22:23.156662 [ANA_INIT] MIDPI <<<<<<<<
3820 00:22:23.156730 [ANA_INIT] DLL >>>>>>>>
3821 00:22:23.156780 [ANA_INIT] flow end
3822 00:22:23.156827 ============ LP4 DIFF to SE enter ============
3823 00:22:23.156876 ============ LP4 DIFF to SE exit ============
3824 00:22:23.156925 [ANA_INIT] <<<<<<<<<<<<<
3825 00:22:23.157006 [Flow] Enable top DCM control >>>>>
3826 00:22:23.157054 [Flow] Enable top DCM control <<<<<
3827 00:22:23.157102 Enable DLL master slave shuffle
3828 00:22:23.157150 ==============================================================
3829 00:22:23.157198 Gating Mode config
3830 00:22:23.157245 ==============================================================
3831 00:22:23.157293 Config description:
3832 00:22:23.157372 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3833 00:22:23.157624 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3834 00:22:23.160950 SELPH_MODE 0: By rank 1: By Phase
3835 00:22:23.167655 ==============================================================
3836 00:22:23.171094 GAT_TRACK_EN = 1
3837 00:22:23.171171 RX_GATING_MODE = 2
3838 00:22:23.174405 RX_GATING_TRACK_MODE = 2
3839 00:22:23.177313 SELPH_MODE = 1
3840 00:22:23.180855 PICG_EARLY_EN = 1
3841 00:22:23.184349 VALID_LAT_VALUE = 1
3842 00:22:23.190933 ==============================================================
3843 00:22:23.194423 Enter into Gating configuration >>>>
3844 00:22:23.197710 Exit from Gating configuration <<<<
3845 00:22:23.200920 Enter into DVFS_PRE_config >>>>>
3846 00:22:23.210699 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3847 00:22:23.214342 Exit from DVFS_PRE_config <<<<<
3848 00:22:23.217364 Enter into PICG configuration >>>>
3849 00:22:23.220657 Exit from PICG configuration <<<<
3850 00:22:23.223864 [RX_INPUT] configuration >>>>>
3851 00:22:23.227138 [RX_INPUT] configuration <<<<<
3852 00:22:23.230613 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3853 00:22:23.237215 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3854 00:22:23.243730 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3855 00:22:23.247115 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3856 00:22:23.253611 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3857 00:22:23.260254 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3858 00:22:23.264091 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3859 00:22:23.270761 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3860 00:22:23.273652 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3861 00:22:23.277209 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3862 00:22:23.280117 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3863 00:22:23.287189 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3864 00:22:23.290042 ===================================
3865 00:22:23.290122 LPDDR4 DRAM CONFIGURATION
3866 00:22:23.293368 ===================================
3867 00:22:23.296706 EX_ROW_EN[0] = 0x0
3868 00:22:23.300180 EX_ROW_EN[1] = 0x0
3869 00:22:23.300259 LP4Y_EN = 0x0
3870 00:22:23.303585 WORK_FSP = 0x0
3871 00:22:23.303663 WL = 0x2
3872 00:22:23.306713 RL = 0x2
3873 00:22:23.306791 BL = 0x2
3874 00:22:23.310166 RPST = 0x0
3875 00:22:23.310243 RD_PRE = 0x0
3876 00:22:23.313522 WR_PRE = 0x1
3877 00:22:23.313599 WR_PST = 0x0
3878 00:22:23.316911 DBI_WR = 0x0
3879 00:22:23.316988 DBI_RD = 0x0
3880 00:22:23.320251 OTF = 0x1
3881 00:22:23.323186 ===================================
3882 00:22:23.326637 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3883 00:22:23.329876 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3884 00:22:23.336392 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3885 00:22:23.339744 ===================================
3886 00:22:23.339821 LPDDR4 DRAM CONFIGURATION
3887 00:22:23.343288 ===================================
3888 00:22:23.346930 EX_ROW_EN[0] = 0x10
3889 00:22:23.349883 EX_ROW_EN[1] = 0x0
3890 00:22:23.349959 LP4Y_EN = 0x0
3891 00:22:23.353079 WORK_FSP = 0x0
3892 00:22:23.353155 WL = 0x2
3893 00:22:23.356533 RL = 0x2
3894 00:22:23.356609 BL = 0x2
3895 00:22:23.359957 RPST = 0x0
3896 00:22:23.360039 RD_PRE = 0x0
3897 00:22:23.362905 WR_PRE = 0x1
3898 00:22:23.362996 WR_PST = 0x0
3899 00:22:23.366373 DBI_WR = 0x0
3900 00:22:23.366449 DBI_RD = 0x0
3901 00:22:23.370090 OTF = 0x1
3902 00:22:23.373508 ===================================
3903 00:22:23.379944 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3904 00:22:23.383406 nWR fixed to 30
3905 00:22:23.383484 [ModeRegInit_LP4] CH0 RK0
3906 00:22:23.386273 [ModeRegInit_LP4] CH0 RK1
3907 00:22:23.389679 [ModeRegInit_LP4] CH1 RK0
3908 00:22:23.392975 [ModeRegInit_LP4] CH1 RK1
3909 00:22:23.393051 match AC timing 17
3910 00:22:23.396420 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3911 00:22:23.403425 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3912 00:22:23.406286 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3913 00:22:23.413202 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3914 00:22:23.416201 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3915 00:22:23.416278 ==
3916 00:22:23.419500 Dram Type= 6, Freq= 0, CH_0, rank 0
3917 00:22:23.422872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3918 00:22:23.422973 ==
3919 00:22:23.429752 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3920 00:22:23.435730 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3921 00:22:23.439177 [CA 0] Center 37 (7~67) winsize 61
3922 00:22:23.442574 [CA 1] Center 37 (7~67) winsize 61
3923 00:22:23.446043 [CA 2] Center 35 (5~65) winsize 61
3924 00:22:23.449297 [CA 3] Center 35 (5~65) winsize 61
3925 00:22:23.452555 [CA 4] Center 34 (4~64) winsize 61
3926 00:22:23.455859 [CA 5] Center 34 (4~64) winsize 61
3927 00:22:23.455935
3928 00:22:23.459133 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3929 00:22:23.459210
3930 00:22:23.462661 [CATrainingPosCal] consider 1 rank data
3931 00:22:23.466089 u2DelayCellTimex100 = 270/100 ps
3932 00:22:23.469432 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3933 00:22:23.472691 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
3934 00:22:23.475880 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3935 00:22:23.479136 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3936 00:22:23.482294 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
3937 00:22:23.485766 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3938 00:22:23.485842
3939 00:22:23.492164 CA PerBit enable=1, Macro0, CA PI delay=34
3940 00:22:23.492240
3941 00:22:23.495674 [CBTSetCACLKResult] CA Dly = 34
3942 00:22:23.495750 CS Dly: 4 (0~35)
3943 00:22:23.495810 ==
3944 00:22:23.499166 Dram Type= 6, Freq= 0, CH_0, rank 1
3945 00:22:23.502545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3946 00:22:23.502621 ==
3947 00:22:23.508922 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3948 00:22:23.515781 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3949 00:22:23.519225 [CA 0] Center 37 (7~67) winsize 61
3950 00:22:23.522026 [CA 1] Center 36 (6~67) winsize 62
3951 00:22:23.525375 [CA 2] Center 35 (5~65) winsize 61
3952 00:22:23.528797 [CA 3] Center 35 (5~65) winsize 61
3953 00:22:23.532177 [CA 4] Center 34 (4~65) winsize 62
3954 00:22:23.535646 [CA 5] Center 34 (4~65) winsize 62
3955 00:22:23.535723
3956 00:22:23.538940 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3957 00:22:23.539023
3958 00:22:23.542300 [CATrainingPosCal] consider 2 rank data
3959 00:22:23.545804 u2DelayCellTimex100 = 270/100 ps
3960 00:22:23.548849 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3961 00:22:23.552165 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
3962 00:22:23.555390 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3963 00:22:23.558787 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3964 00:22:23.562250 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
3965 00:22:23.568591 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3966 00:22:23.568703
3967 00:22:23.571979 CA PerBit enable=1, Macro0, CA PI delay=34
3968 00:22:23.572054
3969 00:22:23.575153 [CBTSetCACLKResult] CA Dly = 34
3970 00:22:23.575229 CS Dly: 5 (0~37)
3971 00:22:23.575288
3972 00:22:23.578801 ----->DramcWriteLeveling(PI) begin...
3973 00:22:23.578878 ==
3974 00:22:23.581915 Dram Type= 6, Freq= 0, CH_0, rank 0
3975 00:22:23.588323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3976 00:22:23.588399 ==
3977 00:22:23.591948 Write leveling (Byte 0): 35 => 35
3978 00:22:23.592024 Write leveling (Byte 1): 31 => 31
3979 00:22:23.594979 DramcWriteLeveling(PI) end<-----
3980 00:22:23.595055
3981 00:22:23.598240 ==
3982 00:22:23.601755 Dram Type= 6, Freq= 0, CH_0, rank 0
3983 00:22:23.604606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3984 00:22:23.604722 ==
3985 00:22:23.608448 [Gating] SW mode calibration
3986 00:22:23.614719 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3987 00:22:23.618152 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3988 00:22:23.624948 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3989 00:22:23.627820 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3990 00:22:23.631173 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3991 00:22:23.637702 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3992 00:22:23.641078 0 9 16 | B1->B0 | 3131 2c2c | 0 1 | (0 1) (1 1)
3993 00:22:23.644283 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3994 00:22:23.651195 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3995 00:22:23.654669 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3996 00:22:23.657978 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3997 00:22:23.664412 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3998 00:22:23.667804 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3999 00:22:23.670690 0 10 12 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
4000 00:22:23.677694 0 10 16 | B1->B0 | 2929 3f3f | 0 0 | (1 1) (0 0)
4001 00:22:23.681216 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4002 00:22:23.683992 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4003 00:22:23.690556 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4004 00:22:23.694137 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4005 00:22:23.697120 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4006 00:22:23.703614 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4007 00:22:23.707259 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4008 00:22:23.710229 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 00:22:23.717136 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 00:22:23.720201 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 00:22:23.723883 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 00:22:23.730317 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 00:22:23.733688 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 00:22:23.737157 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 00:22:23.743431 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 00:22:23.746788 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 00:22:23.750055 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 00:22:23.756939 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 00:22:23.760358 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 00:22:23.763158 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 00:22:23.770147 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 00:22:23.773638 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 00:22:23.776429 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 00:22:23.783506 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4025 00:22:23.783617 Total UI for P1: 0, mck2ui 16
4026 00:22:23.790038 best dqsien dly found for B0: ( 0, 13, 14)
4027 00:22:23.792946 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4028 00:22:23.796363 Total UI for P1: 0, mck2ui 16
4029 00:22:23.799755 best dqsien dly found for B1: ( 0, 13, 16)
4030 00:22:23.802999 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4031 00:22:23.806295 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4032 00:22:23.806386
4033 00:22:23.809520 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4034 00:22:23.812767 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4035 00:22:23.815835 [Gating] SW calibration Done
4036 00:22:23.815945 ==
4037 00:22:23.819181 Dram Type= 6, Freq= 0, CH_0, rank 0
4038 00:22:23.823029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4039 00:22:23.826170 ==
4040 00:22:23.826281 RX Vref Scan: 0
4041 00:22:23.826384
4042 00:22:23.829266 RX Vref 0 -> 0, step: 1
4043 00:22:23.829376
4044 00:22:23.832385 RX Delay -230 -> 252, step: 16
4045 00:22:23.836166 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4046 00:22:23.838993 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4047 00:22:23.842578 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4048 00:22:23.849229 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4049 00:22:23.852540 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4050 00:22:23.855636 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4051 00:22:23.859044 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4052 00:22:23.862340 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4053 00:22:23.868807 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4054 00:22:23.872266 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4055 00:22:23.875775 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4056 00:22:23.878823 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4057 00:22:23.885696 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4058 00:22:23.889171 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4059 00:22:23.892207 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4060 00:22:23.895102 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4061 00:22:23.898671 ==
4062 00:22:23.902128 Dram Type= 6, Freq= 0, CH_0, rank 0
4063 00:22:23.905616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4064 00:22:23.905724 ==
4065 00:22:23.905825 DQS Delay:
4066 00:22:23.908743 DQS0 = 0, DQS1 = 0
4067 00:22:23.908852 DQM Delay:
4068 00:22:23.912065 DQM0 = 38, DQM1 = 29
4069 00:22:23.912174 DQ Delay:
4070 00:22:23.915468 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4071 00:22:23.918767 DQ4 =33, DQ5 =25, DQ6 =57, DQ7 =49
4072 00:22:23.922128 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4073 00:22:23.925306 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4074 00:22:23.925417
4075 00:22:23.925516
4076 00:22:23.925615 ==
4077 00:22:23.928192 Dram Type= 6, Freq= 0, CH_0, rank 0
4078 00:22:23.931621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4079 00:22:23.931731 ==
4080 00:22:23.931833
4081 00:22:23.931929
4082 00:22:23.934659 TX Vref Scan disable
4083 00:22:23.938253 == TX Byte 0 ==
4084 00:22:23.941604 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4085 00:22:23.944900 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4086 00:22:23.948084 == TX Byte 1 ==
4087 00:22:23.951570 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4088 00:22:23.955156 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4089 00:22:23.955232 ==
4090 00:22:23.957908 Dram Type= 6, Freq= 0, CH_0, rank 0
4091 00:22:23.964572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4092 00:22:23.964692 ==
4093 00:22:23.964788
4094 00:22:23.964880
4095 00:22:23.964932 TX Vref Scan disable
4096 00:22:23.969237 == TX Byte 0 ==
4097 00:22:23.972655 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4098 00:22:23.979408 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4099 00:22:23.979486 == TX Byte 1 ==
4100 00:22:23.982776 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4101 00:22:23.989281 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4102 00:22:23.989360
4103 00:22:23.989421 [DATLAT]
4104 00:22:23.989477 Freq=600, CH0 RK0
4105 00:22:23.989531
4106 00:22:23.992173 DATLAT Default: 0x9
4107 00:22:23.992249 0, 0xFFFF, sum = 0
4108 00:22:23.995561 1, 0xFFFF, sum = 0
4109 00:22:23.998918 2, 0xFFFF, sum = 0
4110 00:22:23.998997 3, 0xFFFF, sum = 0
4111 00:22:24.002377 4, 0xFFFF, sum = 0
4112 00:22:24.002455 5, 0xFFFF, sum = 0
4113 00:22:24.005763 6, 0xFFFF, sum = 0
4114 00:22:24.005841 7, 0xFFFF, sum = 0
4115 00:22:24.008767 8, 0x0, sum = 1
4116 00:22:24.008845 9, 0x0, sum = 2
4117 00:22:24.008907 10, 0x0, sum = 3
4118 00:22:24.012154 11, 0x0, sum = 4
4119 00:22:24.012233 best_step = 9
4120 00:22:24.012292
4121 00:22:24.012347 ==
4122 00:22:24.015889 Dram Type= 6, Freq= 0, CH_0, rank 0
4123 00:22:24.022565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4124 00:22:24.022651 ==
4125 00:22:24.022711 RX Vref Scan: 1
4126 00:22:24.022765
4127 00:22:24.025381 RX Vref 0 -> 0, step: 1
4128 00:22:24.025456
4129 00:22:24.028616 RX Delay -195 -> 252, step: 8
4130 00:22:24.028730
4131 00:22:24.032409 Set Vref, RX VrefLevel [Byte0]: 62
4132 00:22:24.035521 [Byte1]: 53
4133 00:22:24.035596
4134 00:22:24.039059 Final RX Vref Byte 0 = 62 to rank0
4135 00:22:24.042291 Final RX Vref Byte 1 = 53 to rank0
4136 00:22:24.045630 Final RX Vref Byte 0 = 62 to rank1
4137 00:22:24.048820 Final RX Vref Byte 1 = 53 to rank1==
4138 00:22:24.052085 Dram Type= 6, Freq= 0, CH_0, rank 0
4139 00:22:24.055299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4140 00:22:24.055376 ==
4141 00:22:24.058495 DQS Delay:
4142 00:22:24.058570 DQS0 = 0, DQS1 = 0
4143 00:22:24.061991 DQM Delay:
4144 00:22:24.062066 DQM0 = 34, DQM1 = 29
4145 00:22:24.062126 DQ Delay:
4146 00:22:24.065321 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =32
4147 00:22:24.068575 DQ4 =32, DQ5 =24, DQ6 =40, DQ7 =44
4148 00:22:24.072153 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4149 00:22:24.075586 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =36
4150 00:22:24.075662
4151 00:22:24.075721
4152 00:22:24.084935 [DQSOSCAuto] RK0, (LSB)MR18= 0x4240, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 397 ps
4153 00:22:24.088221 CH0 RK0: MR19=808, MR18=4240
4154 00:22:24.095181 CH0_RK0: MR19=0x808, MR18=0x4240, DQSOSC=397, MR23=63, INC=166, DEC=110
4155 00:22:24.095259
4156 00:22:24.098206 ----->DramcWriteLeveling(PI) begin...
4157 00:22:24.098283 ==
4158 00:22:24.101619 Dram Type= 6, Freq= 0, CH_0, rank 1
4159 00:22:24.105157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4160 00:22:24.105233 ==
4161 00:22:24.108071 Write leveling (Byte 0): 33 => 33
4162 00:22:24.111524 Write leveling (Byte 1): 32 => 32
4163 00:22:24.115108 DramcWriteLeveling(PI) end<-----
4164 00:22:24.115186
4165 00:22:24.115262 ==
4166 00:22:24.118565 Dram Type= 6, Freq= 0, CH_0, rank 1
4167 00:22:24.121741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4168 00:22:24.121819 ==
4169 00:22:24.124912 [Gating] SW mode calibration
4170 00:22:24.131240 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4171 00:22:24.138154 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4172 00:22:24.141333 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4173 00:22:24.144465 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4174 00:22:24.151653 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4175 00:22:24.154530 0 9 12 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
4176 00:22:24.157836 0 9 16 | B1->B0 | 3030 2525 | 1 0 | (1 1) (0 0)
4177 00:22:24.164468 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4178 00:22:24.167650 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4179 00:22:24.171432 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4180 00:22:24.177881 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4181 00:22:24.180918 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4182 00:22:24.184381 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4183 00:22:24.190766 0 10 12 | B1->B0 | 2a2a 3535 | 0 1 | (0 0) (0 0)
4184 00:22:24.194375 0 10 16 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
4185 00:22:24.197710 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4186 00:22:24.204013 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4187 00:22:24.207456 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4188 00:22:24.210879 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4189 00:22:24.217747 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4190 00:22:24.221099 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4191 00:22:24.224056 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4192 00:22:24.230986 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4193 00:22:24.234290 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 00:22:24.237356 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 00:22:24.243987 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 00:22:24.247266 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 00:22:24.250414 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 00:22:24.257391 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 00:22:24.260597 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 00:22:24.264138 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 00:22:24.270827 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 00:22:24.274222 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 00:22:24.277362 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 00:22:24.283782 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 00:22:24.287076 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 00:22:24.290526 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 00:22:24.294061 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4208 00:22:24.296802 Total UI for P1: 0, mck2ui 16
4209 00:22:24.300283 best dqsien dly found for B0: ( 0, 13, 10)
4210 00:22:24.307191 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4211 00:22:24.310537 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4212 00:22:24.313863 Total UI for P1: 0, mck2ui 16
4213 00:22:24.316761 best dqsien dly found for B1: ( 0, 13, 14)
4214 00:22:24.320189 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4215 00:22:24.323749 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4216 00:22:24.323824
4217 00:22:24.327140 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4218 00:22:24.333842 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4219 00:22:24.333947 [Gating] SW calibration Done
4220 00:22:24.334007 ==
4221 00:22:24.336836 Dram Type= 6, Freq= 0, CH_0, rank 1
4222 00:22:24.343574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4223 00:22:24.343653 ==
4224 00:22:24.343747 RX Vref Scan: 0
4225 00:22:24.343838
4226 00:22:24.346743 RX Vref 0 -> 0, step: 1
4227 00:22:24.346833
4228 00:22:24.350334 RX Delay -230 -> 252, step: 16
4229 00:22:24.353550 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4230 00:22:24.356751 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4231 00:22:24.359875 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4232 00:22:24.366769 iDelay=218, Bit 3, Center 25 (-150 ~ 201) 352
4233 00:22:24.369830 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4234 00:22:24.373489 iDelay=218, Bit 5, Center 17 (-150 ~ 185) 336
4235 00:22:24.376936 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4236 00:22:24.383268 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4237 00:22:24.386518 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4238 00:22:24.390288 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4239 00:22:24.393732 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4240 00:22:24.396745 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4241 00:22:24.403324 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4242 00:22:24.407045 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4243 00:22:24.410436 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4244 00:22:24.413469 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4245 00:22:24.416554 ==
4246 00:22:24.416663 Dram Type= 6, Freq= 0, CH_0, rank 1
4247 00:22:24.423264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4248 00:22:24.423371 ==
4249 00:22:24.423459 DQS Delay:
4250 00:22:24.426699 DQS0 = 0, DQS1 = 0
4251 00:22:24.426776 DQM Delay:
4252 00:22:24.430168 DQM0 = 34, DQM1 = 28
4253 00:22:24.430245 DQ Delay:
4254 00:22:24.433652 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =25
4255 00:22:24.436515 DQ4 =33, DQ5 =17, DQ6 =49, DQ7 =49
4256 00:22:24.439950 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4257 00:22:24.443451 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4258 00:22:24.443552
4259 00:22:24.443638
4260 00:22:24.443730 ==
4261 00:22:24.446934 Dram Type= 6, Freq= 0, CH_0, rank 1
4262 00:22:24.449793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4263 00:22:24.449860 ==
4264 00:22:24.449916
4265 00:22:24.449998
4266 00:22:24.453380 TX Vref Scan disable
4267 00:22:24.456520 == TX Byte 0 ==
4268 00:22:24.459892 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4269 00:22:24.462807 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4270 00:22:24.466432 == TX Byte 1 ==
4271 00:22:24.469705 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4272 00:22:24.472849 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4273 00:22:24.472947 ==
4274 00:22:24.476102 Dram Type= 6, Freq= 0, CH_0, rank 1
4275 00:22:24.482923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4276 00:22:24.483053 ==
4277 00:22:24.483153
4278 00:22:24.483235
4279 00:22:24.483315 TX Vref Scan disable
4280 00:22:24.486977 == TX Byte 0 ==
4281 00:22:24.490486 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4282 00:22:24.497282 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4283 00:22:24.497367 == TX Byte 1 ==
4284 00:22:24.500578 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4285 00:22:24.507181 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4286 00:22:24.507285
4287 00:22:24.507360 [DATLAT]
4288 00:22:24.507446 Freq=600, CH0 RK1
4289 00:22:24.507517
4290 00:22:24.510082 DATLAT Default: 0x9
4291 00:22:24.510160 0, 0xFFFF, sum = 0
4292 00:22:24.513575 1, 0xFFFF, sum = 0
4293 00:22:24.513654 2, 0xFFFF, sum = 0
4294 00:22:24.516999 3, 0xFFFF, sum = 0
4295 00:22:24.520478 4, 0xFFFF, sum = 0
4296 00:22:24.520587 5, 0xFFFF, sum = 0
4297 00:22:24.523769 6, 0xFFFF, sum = 0
4298 00:22:24.523847 7, 0xFFFF, sum = 0
4299 00:22:24.526905 8, 0x0, sum = 1
4300 00:22:24.526983 9, 0x0, sum = 2
4301 00:22:24.527045 10, 0x0, sum = 3
4302 00:22:24.530361 11, 0x0, sum = 4
4303 00:22:24.530440 best_step = 9
4304 00:22:24.530500
4305 00:22:24.530555 ==
4306 00:22:24.533817 Dram Type= 6, Freq= 0, CH_0, rank 1
4307 00:22:24.540196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4308 00:22:24.540275 ==
4309 00:22:24.540336 RX Vref Scan: 0
4310 00:22:24.540391
4311 00:22:24.543670 RX Vref 0 -> 0, step: 1
4312 00:22:24.543746
4313 00:22:24.547070 RX Delay -195 -> 252, step: 8
4314 00:22:24.549931 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4315 00:22:24.556842 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4316 00:22:24.560122 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4317 00:22:24.563375 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4318 00:22:24.566766 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4319 00:22:24.573624 iDelay=205, Bit 5, Center 20 (-139 ~ 180) 320
4320 00:22:24.576914 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4321 00:22:24.580378 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4322 00:22:24.583303 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4323 00:22:24.586643 iDelay=205, Bit 9, Center 12 (-147 ~ 172) 320
4324 00:22:24.593675 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4325 00:22:24.596861 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4326 00:22:24.600362 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4327 00:22:24.603384 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4328 00:22:24.610413 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4329 00:22:24.613625 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4330 00:22:24.613701 ==
4331 00:22:24.616950 Dram Type= 6, Freq= 0, CH_0, rank 1
4332 00:22:24.619925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4333 00:22:24.620002 ==
4334 00:22:24.623342 DQS Delay:
4335 00:22:24.623417 DQS0 = 0, DQS1 = 0
4336 00:22:24.623476 DQM Delay:
4337 00:22:24.626900 DQM0 = 33, DQM1 = 28
4338 00:22:24.626976 DQ Delay:
4339 00:22:24.629796 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =28
4340 00:22:24.633099 DQ4 =32, DQ5 =20, DQ6 =44, DQ7 =44
4341 00:22:24.636854 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4342 00:22:24.639811 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4343 00:22:24.639886
4344 00:22:24.639944
4345 00:22:24.649669 [DQSOSCAuto] RK1, (LSB)MR18= 0x6b3a, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 389 ps
4346 00:22:24.653171 CH0 RK1: MR19=808, MR18=6B3A
4347 00:22:24.656613 CH0_RK1: MR19=0x808, MR18=0x6B3A, DQSOSC=389, MR23=63, INC=173, DEC=115
4348 00:22:24.660036 [RxdqsGatingPostProcess] freq 600
4349 00:22:24.666674 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4350 00:22:24.669667 Pre-setting of DQS Precalculation
4351 00:22:24.673038 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4352 00:22:24.673114 ==
4353 00:22:24.676321 Dram Type= 6, Freq= 0, CH_1, rank 0
4354 00:22:24.683097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4355 00:22:24.683174 ==
4356 00:22:24.686523 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4357 00:22:24.693028 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4358 00:22:24.696412 [CA 0] Center 36 (6~66) winsize 61
4359 00:22:24.699821 [CA 1] Center 35 (5~66) winsize 62
4360 00:22:24.703220 [CA 2] Center 34 (4~65) winsize 62
4361 00:22:24.706082 [CA 3] Center 34 (4~65) winsize 62
4362 00:22:24.709699 [CA 4] Center 34 (4~65) winsize 62
4363 00:22:24.712855 [CA 5] Center 33 (3~64) winsize 62
4364 00:22:24.712930
4365 00:22:24.715937 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4366 00:22:24.716012
4367 00:22:24.719647 [CATrainingPosCal] consider 1 rank data
4368 00:22:24.722761 u2DelayCellTimex100 = 270/100 ps
4369 00:22:24.726119 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4370 00:22:24.732593 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4371 00:22:24.736165 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4372 00:22:24.739457 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4373 00:22:24.742558 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4374 00:22:24.745637 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4375 00:22:24.745713
4376 00:22:24.749088 CA PerBit enable=1, Macro0, CA PI delay=33
4377 00:22:24.749163
4378 00:22:24.752335 [CBTSetCACLKResult] CA Dly = 33
4379 00:22:24.752411 CS Dly: 4 (0~35)
4380 00:22:24.755901 ==
4381 00:22:24.759418 Dram Type= 6, Freq= 0, CH_1, rank 1
4382 00:22:24.762251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4383 00:22:24.762328 ==
4384 00:22:24.765602 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4385 00:22:24.772219 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4386 00:22:24.776125 [CA 0] Center 36 (6~66) winsize 61
4387 00:22:24.779575 [CA 1] Center 35 (5~66) winsize 62
4388 00:22:24.782918 [CA 2] Center 34 (4~65) winsize 62
4389 00:22:24.786240 [CA 3] Center 34 (3~65) winsize 63
4390 00:22:24.789823 [CA 4] Center 34 (4~65) winsize 62
4391 00:22:24.793172 [CA 5] Center 33 (3~64) winsize 62
4392 00:22:24.793248
4393 00:22:24.796156 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4394 00:22:24.796232
4395 00:22:24.799671 [CATrainingPosCal] consider 2 rank data
4396 00:22:24.802960 u2DelayCellTimex100 = 270/100 ps
4397 00:22:24.806198 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4398 00:22:24.809771 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4399 00:22:24.815951 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4400 00:22:24.819335 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4401 00:22:24.822567 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4402 00:22:24.826001 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4403 00:22:24.826077
4404 00:22:24.829452 CA PerBit enable=1, Macro0, CA PI delay=33
4405 00:22:24.829527
4406 00:22:24.832738 [CBTSetCACLKResult] CA Dly = 33
4407 00:22:24.832814 CS Dly: 5 (0~37)
4408 00:22:24.832873
4409 00:22:24.836227 ----->DramcWriteLeveling(PI) begin...
4410 00:22:24.839257 ==
4411 00:22:24.842968 Dram Type= 6, Freq= 0, CH_1, rank 0
4412 00:22:24.846149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4413 00:22:24.846226 ==
4414 00:22:24.849374 Write leveling (Byte 0): 29 => 29
4415 00:22:24.852529 Write leveling (Byte 1): 29 => 29
4416 00:22:24.856265 DramcWriteLeveling(PI) end<-----
4417 00:22:24.856340
4418 00:22:24.856398 ==
4419 00:22:24.859194 Dram Type= 6, Freq= 0, CH_1, rank 0
4420 00:22:24.862719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4421 00:22:24.862795 ==
4422 00:22:24.865655 [Gating] SW mode calibration
4423 00:22:24.872364 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4424 00:22:24.879151 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4425 00:22:24.882406 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4426 00:22:24.885833 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4427 00:22:24.892403 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4428 00:22:24.895857 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
4429 00:22:24.899160 0 9 16 | B1->B0 | 2626 2525 | 0 0 | (0 0) (1 1)
4430 00:22:24.905652 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4431 00:22:24.909148 0 9 24 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
4432 00:22:24.912087 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4433 00:22:24.918664 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4434 00:22:24.922084 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4435 00:22:24.925644 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4436 00:22:24.932087 0 10 12 | B1->B0 | 2f2f 3030 | 0 0 | (1 1) (0 0)
4437 00:22:24.935565 0 10 16 | B1->B0 | 3d3d 4141 | 0 0 | (0 0) (0 0)
4438 00:22:24.938943 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4439 00:22:24.942196 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4440 00:22:24.948601 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4441 00:22:24.952070 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4442 00:22:24.955358 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4443 00:22:24.961887 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4444 00:22:24.965020 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4445 00:22:24.968256 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4446 00:22:24.975072 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 00:22:24.978349 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 00:22:24.981829 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 00:22:24.988045 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 00:22:24.991314 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 00:22:24.994630 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 00:22:25.001500 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 00:22:25.004867 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 00:22:25.008151 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 00:22:25.014855 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 00:22:25.017863 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 00:22:25.021222 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 00:22:25.027885 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 00:22:25.031278 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 00:22:25.034769 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4461 00:22:25.037695 Total UI for P1: 0, mck2ui 16
4462 00:22:25.041107 best dqsien dly found for B0: ( 0, 13, 10)
4463 00:22:25.047639 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4464 00:22:25.050801 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4465 00:22:25.054595 Total UI for P1: 0, mck2ui 16
4466 00:22:25.057412 best dqsien dly found for B1: ( 0, 13, 16)
4467 00:22:25.060811 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4468 00:22:25.064194 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4469 00:22:25.064270
4470 00:22:25.067647 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4471 00:22:25.074144 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4472 00:22:25.074221 [Gating] SW calibration Done
4473 00:22:25.074280 ==
4474 00:22:25.077162 Dram Type= 6, Freq= 0, CH_1, rank 0
4475 00:22:25.083750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4476 00:22:25.083828 ==
4477 00:22:25.083888 RX Vref Scan: 0
4478 00:22:25.083943
4479 00:22:25.087409 RX Vref 0 -> 0, step: 1
4480 00:22:25.087491
4481 00:22:25.090634 RX Delay -230 -> 252, step: 16
4482 00:22:25.094017 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4483 00:22:25.097322 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4484 00:22:25.103551 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4485 00:22:25.106869 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4486 00:22:25.110162 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4487 00:22:25.113450 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4488 00:22:25.116988 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4489 00:22:25.123819 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4490 00:22:25.127174 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4491 00:22:25.130412 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4492 00:22:25.133815 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4493 00:22:25.140143 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4494 00:22:25.143730 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4495 00:22:25.146681 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4496 00:22:25.150120 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4497 00:22:25.156813 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4498 00:22:25.156888 ==
4499 00:22:25.160086 Dram Type= 6, Freq= 0, CH_1, rank 0
4500 00:22:25.163392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4501 00:22:25.163468 ==
4502 00:22:25.163527 DQS Delay:
4503 00:22:25.166828 DQS0 = 0, DQS1 = 0
4504 00:22:25.166904 DQM Delay:
4505 00:22:25.170314 DQM0 = 39, DQM1 = 28
4506 00:22:25.170389 DQ Delay:
4507 00:22:25.173230 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4508 00:22:25.176763 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4509 00:22:25.180140 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4510 00:22:25.183583 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4511 00:22:25.183699
4512 00:22:25.183803
4513 00:22:25.183888 ==
4514 00:22:25.186552 Dram Type= 6, Freq= 0, CH_1, rank 0
4515 00:22:25.189798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4516 00:22:25.189875 ==
4517 00:22:25.189935
4518 00:22:25.189990
4519 00:22:25.193145 TX Vref Scan disable
4520 00:22:25.196742 == TX Byte 0 ==
4521 00:22:25.200224 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4522 00:22:25.203322 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4523 00:22:25.206271 == TX Byte 1 ==
4524 00:22:25.209811 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4525 00:22:25.213387 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4526 00:22:25.213526 ==
4527 00:22:25.216688 Dram Type= 6, Freq= 0, CH_1, rank 0
4528 00:22:25.223010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4529 00:22:25.223086 ==
4530 00:22:25.223179
4531 00:22:25.223248
4532 00:22:25.223333 TX Vref Scan disable
4533 00:22:25.227869 == TX Byte 0 ==
4534 00:22:25.230768 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4535 00:22:25.237542 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4536 00:22:25.237619 == TX Byte 1 ==
4537 00:22:25.240638 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4538 00:22:25.247315 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4539 00:22:25.247416
4540 00:22:25.247493 [DATLAT]
4541 00:22:25.247564 Freq=600, CH1 RK0
4542 00:22:25.247654
4543 00:22:25.250952 DATLAT Default: 0x9
4544 00:22:25.251030 0, 0xFFFF, sum = 0
4545 00:22:25.253925 1, 0xFFFF, sum = 0
4546 00:22:25.257393 2, 0xFFFF, sum = 0
4547 00:22:25.257472 3, 0xFFFF, sum = 0
4548 00:22:25.260560 4, 0xFFFF, sum = 0
4549 00:22:25.260698 5, 0xFFFF, sum = 0
4550 00:22:25.263744 6, 0xFFFF, sum = 0
4551 00:22:25.263847 7, 0xFFFF, sum = 0
4552 00:22:25.267154 8, 0x0, sum = 1
4553 00:22:25.267232 9, 0x0, sum = 2
4554 00:22:25.267311 10, 0x0, sum = 3
4555 00:22:25.270449 11, 0x0, sum = 4
4556 00:22:25.270527 best_step = 9
4557 00:22:25.270604
4558 00:22:25.270675 ==
4559 00:22:25.273870 Dram Type= 6, Freq= 0, CH_1, rank 0
4560 00:22:25.280803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4561 00:22:25.280902 ==
4562 00:22:25.280989 RX Vref Scan: 1
4563 00:22:25.281070
4564 00:22:25.283647 RX Vref 0 -> 0, step: 1
4565 00:22:25.283740
4566 00:22:25.287071 RX Delay -195 -> 252, step: 8
4567 00:22:25.287146
4568 00:22:25.290347 Set Vref, RX VrefLevel [Byte0]: 55
4569 00:22:25.294115 [Byte1]: 49
4570 00:22:25.294190
4571 00:22:25.296953 Final RX Vref Byte 0 = 55 to rank0
4572 00:22:25.300352 Final RX Vref Byte 1 = 49 to rank0
4573 00:22:25.303649 Final RX Vref Byte 0 = 55 to rank1
4574 00:22:25.306936 Final RX Vref Byte 1 = 49 to rank1==
4575 00:22:25.310324 Dram Type= 6, Freq= 0, CH_1, rank 0
4576 00:22:25.313667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4577 00:22:25.313769 ==
4578 00:22:25.317081 DQS Delay:
4579 00:22:25.317158 DQS0 = 0, DQS1 = 0
4580 00:22:25.320126 DQM Delay:
4581 00:22:25.320202 DQM0 = 38, DQM1 = 28
4582 00:22:25.320262 DQ Delay:
4583 00:22:25.323690 DQ0 =44, DQ1 =32, DQ2 =28, DQ3 =36
4584 00:22:25.327028 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4585 00:22:25.330125 DQ8 =12, DQ9 =16, DQ10 =28, DQ11 =20
4586 00:22:25.333623 DQ12 =40, DQ13 =36, DQ14 =36, DQ15 =36
4587 00:22:25.333735
4588 00:22:25.333838
4589 00:22:25.343601 [DQSOSCAuto] RK0, (LSB)MR18= 0x2936, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 402 ps
4590 00:22:25.347042 CH1 RK0: MR19=808, MR18=2936
4591 00:22:25.353664 CH1_RK0: MR19=0x808, MR18=0x2936, DQSOSC=399, MR23=63, INC=164, DEC=109
4592 00:22:25.353766
4593 00:22:25.356837 ----->DramcWriteLeveling(PI) begin...
4594 00:22:25.356940 ==
4595 00:22:25.360278 Dram Type= 6, Freq= 0, CH_1, rank 1
4596 00:22:25.363813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4597 00:22:25.363891 ==
4598 00:22:25.366588 Write leveling (Byte 0): 29 => 29
4599 00:22:25.370366 Write leveling (Byte 1): 30 => 30
4600 00:22:25.373081 DramcWriteLeveling(PI) end<-----
4601 00:22:25.373153
4602 00:22:25.373212 ==
4603 00:22:25.376863 Dram Type= 6, Freq= 0, CH_1, rank 1
4604 00:22:25.380234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4605 00:22:25.380336 ==
4606 00:22:25.383263 [Gating] SW mode calibration
4607 00:22:25.390158 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4608 00:22:25.396815 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4609 00:22:25.400154 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4610 00:22:25.403635 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4611 00:22:25.409781 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4612 00:22:25.413200 0 9 12 | B1->B0 | 3131 2e2e | 0 0 | (0 1) (1 1)
4613 00:22:25.416924 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4614 00:22:25.422949 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4615 00:22:25.426381 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4616 00:22:25.430031 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4617 00:22:25.436759 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4618 00:22:25.439799 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4619 00:22:25.443497 0 10 8 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
4620 00:22:25.449803 0 10 12 | B1->B0 | 2e2e 4040 | 1 0 | (1 1) (0 0)
4621 00:22:25.453347 0 10 16 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
4622 00:22:25.456236 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4623 00:22:25.463104 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4624 00:22:25.466551 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4625 00:22:25.469893 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4626 00:22:25.476328 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4627 00:22:25.479403 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4628 00:22:25.482760 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4629 00:22:25.489571 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 00:22:25.492908 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 00:22:25.496362 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 00:22:25.499227 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 00:22:25.505783 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 00:22:25.509111 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 00:22:25.515745 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 00:22:25.519244 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 00:22:25.522550 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 00:22:25.529092 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 00:22:25.532529 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 00:22:25.535320 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 00:22:25.542392 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 00:22:25.545627 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 00:22:25.548565 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 00:22:25.552005 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4645 00:22:25.558518 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4646 00:22:25.561861 Total UI for P1: 0, mck2ui 16
4647 00:22:25.565312 best dqsien dly found for B0: ( 0, 13, 12)
4648 00:22:25.568913 Total UI for P1: 0, mck2ui 16
4649 00:22:25.571789 best dqsien dly found for B1: ( 0, 13, 14)
4650 00:22:25.575341 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4651 00:22:25.578312 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4652 00:22:25.578410
4653 00:22:25.581751 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4654 00:22:25.585042 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4655 00:22:25.588855 [Gating] SW calibration Done
4656 00:22:25.588931 ==
4657 00:22:25.591568 Dram Type= 6, Freq= 0, CH_1, rank 1
4658 00:22:25.595201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4659 00:22:25.595301 ==
4660 00:22:25.598204 RX Vref Scan: 0
4661 00:22:25.598293
4662 00:22:25.601679 RX Vref 0 -> 0, step: 1
4663 00:22:25.601743
4664 00:22:25.605077 RX Delay -230 -> 252, step: 16
4665 00:22:25.608510 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4666 00:22:25.611192 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4667 00:22:25.614537 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4668 00:22:25.617750 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4669 00:22:25.624812 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4670 00:22:25.627762 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4671 00:22:25.631468 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4672 00:22:25.634406 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4673 00:22:25.641082 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4674 00:22:25.644337 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4675 00:22:25.647895 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4676 00:22:25.650858 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4677 00:22:25.657783 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4678 00:22:25.661194 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4679 00:22:25.664463 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4680 00:22:25.667743 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4681 00:22:25.667853 ==
4682 00:22:25.670990 Dram Type= 6, Freq= 0, CH_1, rank 1
4683 00:22:25.677641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4684 00:22:25.677767 ==
4685 00:22:25.677870 DQS Delay:
4686 00:22:25.680611 DQS0 = 0, DQS1 = 0
4687 00:22:25.680739 DQM Delay:
4688 00:22:25.684317 DQM0 = 39, DQM1 = 29
4689 00:22:25.684425 DQ Delay:
4690 00:22:25.687382 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =33
4691 00:22:25.690580 DQ4 =33, DQ5 =57, DQ6 =57, DQ7 =33
4692 00:22:25.694036 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4693 00:22:25.697343 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4694 00:22:25.697422
4695 00:22:25.697481
4696 00:22:25.697541 ==
4697 00:22:25.700668 Dram Type= 6, Freq= 0, CH_1, rank 1
4698 00:22:25.703838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4699 00:22:25.703914 ==
4700 00:22:25.703973
4701 00:22:25.704028
4702 00:22:25.707331 TX Vref Scan disable
4703 00:22:25.710287 == TX Byte 0 ==
4704 00:22:25.713587 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4705 00:22:25.717284 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4706 00:22:25.720226 == TX Byte 1 ==
4707 00:22:25.723471 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4708 00:22:25.726790 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4709 00:22:25.726862 ==
4710 00:22:25.730335 Dram Type= 6, Freq= 0, CH_1, rank 1
4711 00:22:25.733331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4712 00:22:25.736948 ==
4713 00:22:25.737040
4714 00:22:25.737129
4715 00:22:25.737223 TX Vref Scan disable
4716 00:22:25.741145 == TX Byte 0 ==
4717 00:22:25.744151 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4718 00:22:25.750605 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4719 00:22:25.750715 == TX Byte 1 ==
4720 00:22:25.754177 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4721 00:22:25.760563 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4722 00:22:25.760687
4723 00:22:25.760787 [DATLAT]
4724 00:22:25.760891 Freq=600, CH1 RK1
4725 00:22:25.760994
4726 00:22:25.764062 DATLAT Default: 0x9
4727 00:22:25.764136 0, 0xFFFF, sum = 0
4728 00:22:25.767573 1, 0xFFFF, sum = 0
4729 00:22:25.770493 2, 0xFFFF, sum = 0
4730 00:22:25.770569 3, 0xFFFF, sum = 0
4731 00:22:25.774239 4, 0xFFFF, sum = 0
4732 00:22:25.774312 5, 0xFFFF, sum = 0
4733 00:22:25.777445 6, 0xFFFF, sum = 0
4734 00:22:25.777551 7, 0xFFFF, sum = 0
4735 00:22:25.780767 8, 0x0, sum = 1
4736 00:22:25.780865 9, 0x0, sum = 2
4737 00:22:25.780958 10, 0x0, sum = 3
4738 00:22:25.783821 11, 0x0, sum = 4
4739 00:22:25.783886 best_step = 9
4740 00:22:25.783942
4741 00:22:25.783994 ==
4742 00:22:25.787346 Dram Type= 6, Freq= 0, CH_1, rank 1
4743 00:22:25.794161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4744 00:22:25.794232 ==
4745 00:22:25.794290 RX Vref Scan: 0
4746 00:22:25.794350
4747 00:22:25.797170 RX Vref 0 -> 0, step: 1
4748 00:22:25.797235
4749 00:22:25.800465 RX Delay -195 -> 252, step: 8
4750 00:22:25.803846 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4751 00:22:25.810655 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4752 00:22:25.813538 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4753 00:22:25.817222 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4754 00:22:25.820164 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4755 00:22:25.827097 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4756 00:22:25.830392 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4757 00:22:25.833448 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4758 00:22:25.837015 iDelay=205, Bit 8, Center 16 (-147 ~ 180) 328
4759 00:22:25.843285 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4760 00:22:25.846781 iDelay=205, Bit 10, Center 32 (-131 ~ 196) 328
4761 00:22:25.850114 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4762 00:22:25.853493 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4763 00:22:25.859996 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4764 00:22:25.863344 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4765 00:22:25.866661 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4766 00:22:25.866760 ==
4767 00:22:25.869982 Dram Type= 6, Freq= 0, CH_1, rank 1
4768 00:22:25.873497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4769 00:22:25.873569 ==
4770 00:22:25.876350 DQS Delay:
4771 00:22:25.876414 DQS0 = 0, DQS1 = 0
4772 00:22:25.879754 DQM Delay:
4773 00:22:25.879864 DQM0 = 36, DQM1 = 29
4774 00:22:25.879971 DQ Delay:
4775 00:22:25.883048 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4776 00:22:25.886384 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =32
4777 00:22:25.889594 DQ8 =16, DQ9 =20, DQ10 =32, DQ11 =20
4778 00:22:25.893156 DQ12 =36, DQ13 =36, DQ14 =40, DQ15 =36
4779 00:22:25.893266
4780 00:22:25.893361
4781 00:22:25.902776 [DQSOSCAuto] RK1, (LSB)MR18= 0x3959, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 399 ps
4782 00:22:25.906201 CH1 RK1: MR19=808, MR18=3959
4783 00:22:25.912978 CH1_RK1: MR19=0x808, MR18=0x3959, DQSOSC=393, MR23=63, INC=169, DEC=113
4784 00:22:25.913063 [RxdqsGatingPostProcess] freq 600
4785 00:22:25.919336 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4786 00:22:25.922817 Pre-setting of DQS Precalculation
4787 00:22:25.926528 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4788 00:22:25.936426 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4789 00:22:25.942654 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4790 00:22:25.942728
4791 00:22:25.942795
4792 00:22:25.946198 [Calibration Summary] 1200 Mbps
4793 00:22:25.946362 CH 0, Rank 0
4794 00:22:25.949572 SW Impedance : PASS
4795 00:22:25.949640 DUTY Scan : NO K
4796 00:22:25.953004 ZQ Calibration : PASS
4797 00:22:25.956318 Jitter Meter : NO K
4798 00:22:25.956392 CBT Training : PASS
4799 00:22:25.959754 Write leveling : PASS
4800 00:22:25.962825 RX DQS gating : PASS
4801 00:22:25.962933 RX DQ/DQS(RDDQC) : PASS
4802 00:22:25.966301 TX DQ/DQS : PASS
4803 00:22:25.969777 RX DATLAT : PASS
4804 00:22:25.969952 RX DQ/DQS(Engine): PASS
4805 00:22:25.972823 TX OE : NO K
4806 00:22:25.972933 All Pass.
4807 00:22:25.973046
4808 00:22:25.975784 CH 0, Rank 1
4809 00:22:25.975892 SW Impedance : PASS
4810 00:22:25.979464 DUTY Scan : NO K
4811 00:22:25.982849 ZQ Calibration : PASS
4812 00:22:25.982971 Jitter Meter : NO K
4813 00:22:25.986239 CBT Training : PASS
4814 00:22:25.989004 Write leveling : PASS
4815 00:22:25.989125 RX DQS gating : PASS
4816 00:22:25.992720 RX DQ/DQS(RDDQC) : PASS
4817 00:22:25.992832 TX DQ/DQS : PASS
4818 00:22:25.996147 RX DATLAT : PASS
4819 00:22:25.999404 RX DQ/DQS(Engine): PASS
4820 00:22:25.999545 TX OE : NO K
4821 00:22:26.002249 All Pass.
4822 00:22:26.002386
4823 00:22:26.002498 CH 1, Rank 0
4824 00:22:26.005956 SW Impedance : PASS
4825 00:22:26.006067 DUTY Scan : NO K
4826 00:22:26.009313 ZQ Calibration : PASS
4827 00:22:26.012698 Jitter Meter : NO K
4828 00:22:26.012813 CBT Training : PASS
4829 00:22:26.015805 Write leveling : PASS
4830 00:22:26.018930 RX DQS gating : PASS
4831 00:22:26.019042 RX DQ/DQS(RDDQC) : PASS
4832 00:22:26.022153 TX DQ/DQS : PASS
4833 00:22:26.025600 RX DATLAT : PASS
4834 00:22:26.025712 RX DQ/DQS(Engine): PASS
4835 00:22:26.029271 TX OE : NO K
4836 00:22:26.029382 All Pass.
4837 00:22:26.029480
4838 00:22:26.032118 CH 1, Rank 1
4839 00:22:26.032235 SW Impedance : PASS
4840 00:22:26.035537 DUTY Scan : NO K
4841 00:22:26.039019 ZQ Calibration : PASS
4842 00:22:26.039115 Jitter Meter : NO K
4843 00:22:26.042401 CBT Training : PASS
4844 00:22:26.045597 Write leveling : PASS
4845 00:22:26.045670 RX DQS gating : PASS
4846 00:22:26.049147 RX DQ/DQS(RDDQC) : PASS
4847 00:22:26.049216 TX DQ/DQS : PASS
4848 00:22:26.052222 RX DATLAT : PASS
4849 00:22:26.055798 RX DQ/DQS(Engine): PASS
4850 00:22:26.055873 TX OE : NO K
4851 00:22:26.058745 All Pass.
4852 00:22:26.058821
4853 00:22:26.058881 DramC Write-DBI off
4854 00:22:26.062222 PER_BANK_REFRESH: Hybrid Mode
4855 00:22:26.065292 TX_TRACKING: ON
4856 00:22:26.072244 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4857 00:22:26.075132 [FAST_K] Save calibration result to emmc
4858 00:22:26.078688 dramc_set_vcore_voltage set vcore to 662500
4859 00:22:26.082261 Read voltage for 933, 3
4860 00:22:26.082350 Vio18 = 0
4861 00:22:26.085116 Vcore = 662500
4862 00:22:26.085193 Vdram = 0
4863 00:22:26.085257 Vddq = 0
4864 00:22:26.088813 Vmddr = 0
4865 00:22:26.092108 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4866 00:22:26.098607 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4867 00:22:26.098680 MEM_TYPE=3, freq_sel=17
4868 00:22:26.102062 sv_algorithm_assistance_LP4_1600
4869 00:22:26.108774 ============ PULL DRAM RESETB DOWN ============
4870 00:22:26.111618 ========== PULL DRAM RESETB DOWN end =========
4871 00:22:26.115130 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4872 00:22:26.118493 ===================================
4873 00:22:26.121815 LPDDR4 DRAM CONFIGURATION
4874 00:22:26.125295 ===================================
4875 00:22:26.128624 EX_ROW_EN[0] = 0x0
4876 00:22:26.128717 EX_ROW_EN[1] = 0x0
4877 00:22:26.131691 LP4Y_EN = 0x0
4878 00:22:26.131759 WORK_FSP = 0x0
4879 00:22:26.134918 WL = 0x3
4880 00:22:26.134987 RL = 0x3
4881 00:22:26.138512 BL = 0x2
4882 00:22:26.138582 RPST = 0x0
4883 00:22:26.141766 RD_PRE = 0x0
4884 00:22:26.141838 WR_PRE = 0x1
4885 00:22:26.145221 WR_PST = 0x0
4886 00:22:26.145287 DBI_WR = 0x0
4887 00:22:26.148099 DBI_RD = 0x0
4888 00:22:26.148179 OTF = 0x1
4889 00:22:26.151634 ===================================
4890 00:22:26.155000 ===================================
4891 00:22:26.158169 ANA top config
4892 00:22:26.161795 ===================================
4893 00:22:26.165098 DLL_ASYNC_EN = 0
4894 00:22:26.165185 ALL_SLAVE_EN = 1
4895 00:22:26.168041 NEW_RANK_MODE = 1
4896 00:22:26.171665 DLL_IDLE_MODE = 1
4897 00:22:26.174681 LP45_APHY_COMB_EN = 1
4898 00:22:26.174750 TX_ODT_DIS = 1
4899 00:22:26.178144 NEW_8X_MODE = 1
4900 00:22:26.181680 ===================================
4901 00:22:26.184637 ===================================
4902 00:22:26.188255 data_rate = 1866
4903 00:22:26.191712 CKR = 1
4904 00:22:26.194746 DQ_P2S_RATIO = 8
4905 00:22:26.198094 ===================================
4906 00:22:26.201528 CA_P2S_RATIO = 8
4907 00:22:26.201600 DQ_CA_OPEN = 0
4908 00:22:26.204703 DQ_SEMI_OPEN = 0
4909 00:22:26.208040 CA_SEMI_OPEN = 0
4910 00:22:26.211288 CA_FULL_RATE = 0
4911 00:22:26.214665 DQ_CKDIV4_EN = 1
4912 00:22:26.218184 CA_CKDIV4_EN = 1
4913 00:22:26.218277 CA_PREDIV_EN = 0
4914 00:22:26.221116 PH8_DLY = 0
4915 00:22:26.224473 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4916 00:22:26.227970 DQ_AAMCK_DIV = 4
4917 00:22:26.230995 CA_AAMCK_DIV = 4
4918 00:22:26.234543 CA_ADMCK_DIV = 4
4919 00:22:26.234620 DQ_TRACK_CA_EN = 0
4920 00:22:26.238010 CA_PICK = 933
4921 00:22:26.240911 CA_MCKIO = 933
4922 00:22:26.244164 MCKIO_SEMI = 0
4923 00:22:26.247971 PLL_FREQ = 3732
4924 00:22:26.251314 DQ_UI_PI_RATIO = 32
4925 00:22:26.254565 CA_UI_PI_RATIO = 0
4926 00:22:26.257495 ===================================
4927 00:22:26.260995 ===================================
4928 00:22:26.261072 memory_type:LPDDR4
4929 00:22:26.264464 GP_NUM : 10
4930 00:22:26.267590 SRAM_EN : 1
4931 00:22:26.267667 MD32_EN : 0
4932 00:22:26.270602 ===================================
4933 00:22:26.274269 [ANA_INIT] >>>>>>>>>>>>>>
4934 00:22:26.277572 <<<<<< [CONFIGURE PHASE]: ANA_TX
4935 00:22:26.280606 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4936 00:22:26.284109 ===================================
4937 00:22:26.287580 data_rate = 1866,PCW = 0X8f00
4938 00:22:26.290613 ===================================
4939 00:22:26.294147 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4940 00:22:26.297244 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4941 00:22:26.304219 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4942 00:22:26.307327 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4943 00:22:26.310857 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4944 00:22:26.313808 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4945 00:22:26.317365 [ANA_INIT] flow start
4946 00:22:26.320610 [ANA_INIT] PLL >>>>>>>>
4947 00:22:26.320701 [ANA_INIT] PLL <<<<<<<<
4948 00:22:26.324182 [ANA_INIT] MIDPI >>>>>>>>
4949 00:22:26.327536 [ANA_INIT] MIDPI <<<<<<<<
4950 00:22:26.330533 [ANA_INIT] DLL >>>>>>>>
4951 00:22:26.330601 [ANA_INIT] flow end
4952 00:22:26.334087 ============ LP4 DIFF to SE enter ============
4953 00:22:26.340557 ============ LP4 DIFF to SE exit ============
4954 00:22:26.340625 [ANA_INIT] <<<<<<<<<<<<<
4955 00:22:26.343759 [Flow] Enable top DCM control >>>>>
4956 00:22:26.347267 [Flow] Enable top DCM control <<<<<
4957 00:22:26.350147 Enable DLL master slave shuffle
4958 00:22:26.356915 ==============================================================
4959 00:22:26.357000 Gating Mode config
4960 00:22:26.363550 ==============================================================
4961 00:22:26.366963 Config description:
4962 00:22:26.376969 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4963 00:22:26.383616 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4964 00:22:26.386554 SELPH_MODE 0: By rank 1: By Phase
4965 00:22:26.393503 ==============================================================
4966 00:22:26.397058 GAT_TRACK_EN = 1
4967 00:22:26.399845 RX_GATING_MODE = 2
4968 00:22:26.399914 RX_GATING_TRACK_MODE = 2
4969 00:22:26.403198 SELPH_MODE = 1
4970 00:22:26.406756 PICG_EARLY_EN = 1
4971 00:22:26.410088 VALID_LAT_VALUE = 1
4972 00:22:26.416452 ==============================================================
4973 00:22:26.419712 Enter into Gating configuration >>>>
4974 00:22:26.423405 Exit from Gating configuration <<<<
4975 00:22:26.426689 Enter into DVFS_PRE_config >>>>>
4976 00:22:26.436140 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4977 00:22:26.439601 Exit from DVFS_PRE_config <<<<<
4978 00:22:26.443044 Enter into PICG configuration >>>>
4979 00:22:26.446010 Exit from PICG configuration <<<<
4980 00:22:26.449567 [RX_INPUT] configuration >>>>>
4981 00:22:26.452846 [RX_INPUT] configuration <<<<<
4982 00:22:26.456165 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4983 00:22:26.462663 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4984 00:22:26.469085 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4985 00:22:26.475959 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4986 00:22:26.482386 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4987 00:22:26.485696 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4988 00:22:26.492415 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4989 00:22:26.495972 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4990 00:22:26.499018 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4991 00:22:26.502466 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4992 00:22:26.505876 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4993 00:22:26.512781 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4994 00:22:26.515728 ===================================
4995 00:22:26.519002 LPDDR4 DRAM CONFIGURATION
4996 00:22:26.522492 ===================================
4997 00:22:26.522559 EX_ROW_EN[0] = 0x0
4998 00:22:26.525891 EX_ROW_EN[1] = 0x0
4999 00:22:26.525962 LP4Y_EN = 0x0
5000 00:22:26.529017 WORK_FSP = 0x0
5001 00:22:26.529086 WL = 0x3
5002 00:22:26.532219 RL = 0x3
5003 00:22:26.532286 BL = 0x2
5004 00:22:26.535502 RPST = 0x0
5005 00:22:26.535607 RD_PRE = 0x0
5006 00:22:26.538909 WR_PRE = 0x1
5007 00:22:26.538974 WR_PST = 0x0
5008 00:22:26.542340 DBI_WR = 0x0
5009 00:22:26.542403 DBI_RD = 0x0
5010 00:22:26.545706 OTF = 0x1
5011 00:22:26.549129 ===================================
5012 00:22:26.552570 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5013 00:22:26.555400 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5014 00:22:26.562163 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5015 00:22:26.565655 ===================================
5016 00:22:26.565768 LPDDR4 DRAM CONFIGURATION
5017 00:22:26.569056 ===================================
5018 00:22:26.572558 EX_ROW_EN[0] = 0x10
5019 00:22:26.575517 EX_ROW_EN[1] = 0x0
5020 00:22:26.575626 LP4Y_EN = 0x0
5021 00:22:26.578914 WORK_FSP = 0x0
5022 00:22:26.579024 WL = 0x3
5023 00:22:26.582767 RL = 0x3
5024 00:22:26.582882 BL = 0x2
5025 00:22:26.585472 RPST = 0x0
5026 00:22:26.585581 RD_PRE = 0x0
5027 00:22:26.588566 WR_PRE = 0x1
5028 00:22:26.588696 WR_PST = 0x0
5029 00:22:26.591968 DBI_WR = 0x0
5030 00:22:26.592075 DBI_RD = 0x0
5031 00:22:26.595267 OTF = 0x1
5032 00:22:26.598743 ===================================
5033 00:22:26.605259 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5034 00:22:26.608537 nWR fixed to 30
5035 00:22:26.612103 [ModeRegInit_LP4] CH0 RK0
5036 00:22:26.612207 [ModeRegInit_LP4] CH0 RK1
5037 00:22:26.615420 [ModeRegInit_LP4] CH1 RK0
5038 00:22:26.619062 [ModeRegInit_LP4] CH1 RK1
5039 00:22:26.619172 match AC timing 9
5040 00:22:26.625285 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5041 00:22:26.628704 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5042 00:22:26.632141 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5043 00:22:26.639014 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5044 00:22:26.642024 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5045 00:22:26.642136 ==
5046 00:22:26.645429 Dram Type= 6, Freq= 0, CH_0, rank 0
5047 00:22:26.649037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5048 00:22:26.649150 ==
5049 00:22:26.655441 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5050 00:22:26.661819 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5051 00:22:26.665158 [CA 0] Center 38 (8~69) winsize 62
5052 00:22:26.668524 [CA 1] Center 38 (8~69) winsize 62
5053 00:22:26.672028 [CA 2] Center 35 (5~65) winsize 61
5054 00:22:26.675433 [CA 3] Center 35 (5~65) winsize 61
5055 00:22:26.678920 [CA 4] Center 34 (4~64) winsize 61
5056 00:22:26.681940 [CA 5] Center 33 (3~64) winsize 62
5057 00:22:26.682053
5058 00:22:26.685482 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5059 00:22:26.685591
5060 00:22:26.688468 [CATrainingPosCal] consider 1 rank data
5061 00:22:26.691651 u2DelayCellTimex100 = 270/100 ps
5062 00:22:26.695172 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5063 00:22:26.698614 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5064 00:22:26.701890 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5065 00:22:26.704862 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5066 00:22:26.708215 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5067 00:22:26.711621 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5068 00:22:26.711725
5069 00:22:26.718275 CA PerBit enable=1, Macro0, CA PI delay=33
5070 00:22:26.718366
5071 00:22:26.721553 [CBTSetCACLKResult] CA Dly = 33
5072 00:22:26.721634 CS Dly: 7 (0~38)
5073 00:22:26.721704 ==
5074 00:22:26.724489 Dram Type= 6, Freq= 0, CH_0, rank 1
5075 00:22:26.728399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5076 00:22:26.728470 ==
5077 00:22:26.735179 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5078 00:22:26.741459 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5079 00:22:26.744773 [CA 0] Center 38 (8~69) winsize 62
5080 00:22:26.747932 [CA 1] Center 38 (8~69) winsize 62
5081 00:22:26.751153 [CA 2] Center 35 (5~66) winsize 62
5082 00:22:26.754672 [CA 3] Center 35 (5~66) winsize 62
5083 00:22:26.757800 [CA 4] Center 34 (4~65) winsize 62
5084 00:22:26.761236 [CA 5] Center 33 (3~64) winsize 62
5085 00:22:26.761353
5086 00:22:26.764712 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5087 00:22:26.764839
5088 00:22:26.767586 [CATrainingPosCal] consider 2 rank data
5089 00:22:26.771090 u2DelayCellTimex100 = 270/100 ps
5090 00:22:26.774614 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5091 00:22:26.777613 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5092 00:22:26.781298 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5093 00:22:26.784228 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5094 00:22:26.790962 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5095 00:22:26.794473 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5096 00:22:26.794601
5097 00:22:26.797494 CA PerBit enable=1, Macro0, CA PI delay=33
5098 00:22:26.797636
5099 00:22:26.801058 [CBTSetCACLKResult] CA Dly = 33
5100 00:22:26.801179 CS Dly: 7 (0~39)
5101 00:22:26.801298
5102 00:22:26.804028 ----->DramcWriteLeveling(PI) begin...
5103 00:22:26.804170 ==
5104 00:22:26.807474 Dram Type= 6, Freq= 0, CH_0, rank 0
5105 00:22:26.814188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5106 00:22:26.814288 ==
5107 00:22:26.817411 Write leveling (Byte 0): 32 => 32
5108 00:22:26.820534 Write leveling (Byte 1): 31 => 31
5109 00:22:26.820625 DramcWriteLeveling(PI) end<-----
5110 00:22:26.820696
5111 00:22:26.824143 ==
5112 00:22:26.827159 Dram Type= 6, Freq= 0, CH_0, rank 0
5113 00:22:26.830698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5114 00:22:26.830777 ==
5115 00:22:26.833828 [Gating] SW mode calibration
5116 00:22:26.840614 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5117 00:22:26.844094 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5118 00:22:26.850754 0 14 0 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
5119 00:22:26.853518 0 14 4 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
5120 00:22:26.856901 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5121 00:22:26.863795 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5122 00:22:26.866712 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5123 00:22:26.870208 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5124 00:22:26.876793 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5125 00:22:26.880337 0 14 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (1 0)
5126 00:22:26.883372 0 15 0 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 0)
5127 00:22:26.889942 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
5128 00:22:26.893530 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5129 00:22:26.897079 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5130 00:22:26.903686 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5131 00:22:26.906623 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5132 00:22:26.910258 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5133 00:22:26.916539 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5134 00:22:26.920156 1 0 0 | B1->B0 | 2929 3a3a | 1 0 | (0 0) (0 0)
5135 00:22:26.923157 1 0 4 | B1->B0 | 4242 4646 | 1 0 | (0 0) (0 0)
5136 00:22:26.929918 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5137 00:22:26.933049 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5138 00:22:26.936437 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5139 00:22:26.943348 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5140 00:22:26.946696 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5141 00:22:26.950006 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5142 00:22:26.956489 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5143 00:22:26.959911 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5144 00:22:26.963222 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 00:22:26.969534 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 00:22:26.973135 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 00:22:26.976260 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 00:22:26.983063 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 00:22:26.986093 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5150 00:22:26.989621 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 00:22:26.996337 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 00:22:26.999226 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 00:22:27.002933 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 00:22:27.009492 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 00:22:27.012937 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 00:22:27.015897 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 00:22:27.019459 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5158 00:22:27.026092 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5159 00:22:27.029112 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5160 00:22:27.032775 Total UI for P1: 0, mck2ui 16
5161 00:22:27.036217 best dqsien dly found for B0: ( 1, 3, 0)
5162 00:22:27.039033 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5163 00:22:27.042299 Total UI for P1: 0, mck2ui 16
5164 00:22:27.045913 best dqsien dly found for B1: ( 1, 3, 4)
5165 00:22:27.049099 best DQS0 dly(MCK, UI, PI) = (1, 3, 0)
5166 00:22:27.052722 best DQS1 dly(MCK, UI, PI) = (1, 3, 4)
5167 00:22:27.052801
5168 00:22:27.059072 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 0)
5169 00:22:27.062492 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 4)
5170 00:22:27.065707 [Gating] SW calibration Done
5171 00:22:27.065798 ==
5172 00:22:27.068876 Dram Type= 6, Freq= 0, CH_0, rank 0
5173 00:22:27.072493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5174 00:22:27.072596 ==
5175 00:22:27.072690 RX Vref Scan: 0
5176 00:22:27.072749
5177 00:22:27.075677 RX Vref 0 -> 0, step: 1
5178 00:22:27.075756
5179 00:22:27.079242 RX Delay -80 -> 252, step: 8
5180 00:22:27.082264 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5181 00:22:27.085836 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5182 00:22:27.089035 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5183 00:22:27.095443 iDelay=208, Bit 3, Center 87 (-8 ~ 183) 192
5184 00:22:27.099077 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5185 00:22:27.102013 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5186 00:22:27.105572 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5187 00:22:27.109249 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5188 00:22:27.115530 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5189 00:22:27.119136 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5190 00:22:27.122110 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5191 00:22:27.125656 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5192 00:22:27.128670 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5193 00:22:27.135469 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5194 00:22:27.138900 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5195 00:22:27.142231 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5196 00:22:27.142309 ==
5197 00:22:27.145224 Dram Type= 6, Freq= 0, CH_0, rank 0
5198 00:22:27.148600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5199 00:22:27.148699 ==
5200 00:22:27.152259 DQS Delay:
5201 00:22:27.152365 DQS0 = 0, DQS1 = 0
5202 00:22:27.155088 DQM Delay:
5203 00:22:27.155190 DQM0 = 93, DQM1 = 83
5204 00:22:27.155272 DQ Delay:
5205 00:22:27.158591 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =87
5206 00:22:27.162005 DQ4 =95, DQ5 =79, DQ6 =103, DQ7 =107
5207 00:22:27.165076 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =75
5208 00:22:27.168595 DQ12 =91, DQ13 =87, DQ14 =91, DQ15 =91
5209 00:22:27.168694
5210 00:22:27.168757
5211 00:22:27.171539 ==
5212 00:22:27.174877 Dram Type= 6, Freq= 0, CH_0, rank 0
5213 00:22:27.178694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5214 00:22:27.178773 ==
5215 00:22:27.178833
5216 00:22:27.178887
5217 00:22:27.181843 TX Vref Scan disable
5218 00:22:27.181928 == TX Byte 0 ==
5219 00:22:27.185237 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5220 00:22:27.192148 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5221 00:22:27.192227 == TX Byte 1 ==
5222 00:22:27.195063 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5223 00:22:27.201616 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5224 00:22:27.201694 ==
5225 00:22:27.205080 Dram Type= 6, Freq= 0, CH_0, rank 0
5226 00:22:27.208393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5227 00:22:27.208495 ==
5228 00:22:27.208583
5229 00:22:27.208674
5230 00:22:27.211411 TX Vref Scan disable
5231 00:22:27.215011 == TX Byte 0 ==
5232 00:22:27.217967 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5233 00:22:27.221549 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5234 00:22:27.225038 == TX Byte 1 ==
5235 00:22:27.228457 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5236 00:22:27.231319 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5237 00:22:27.231399
5238 00:22:27.234790 [DATLAT]
5239 00:22:27.234868 Freq=933, CH0 RK0
5240 00:22:27.234930
5241 00:22:27.238286 DATLAT Default: 0xd
5242 00:22:27.238379 0, 0xFFFF, sum = 0
5243 00:22:27.241240 1, 0xFFFF, sum = 0
5244 00:22:27.241340 2, 0xFFFF, sum = 0
5245 00:22:27.244803 3, 0xFFFF, sum = 0
5246 00:22:27.244900 4, 0xFFFF, sum = 0
5247 00:22:27.248306 5, 0xFFFF, sum = 0
5248 00:22:27.248398 6, 0xFFFF, sum = 0
5249 00:22:27.251748 7, 0xFFFF, sum = 0
5250 00:22:27.251818 8, 0xFFFF, sum = 0
5251 00:22:27.254960 9, 0xFFFF, sum = 0
5252 00:22:27.255060 10, 0x0, sum = 1
5253 00:22:27.258360 11, 0x0, sum = 2
5254 00:22:27.258453 12, 0x0, sum = 3
5255 00:22:27.261230 13, 0x0, sum = 4
5256 00:22:27.261301 best_step = 11
5257 00:22:27.261359
5258 00:22:27.261416 ==
5259 00:22:27.264586 Dram Type= 6, Freq= 0, CH_0, rank 0
5260 00:22:27.267969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5261 00:22:27.271194 ==
5262 00:22:27.271260 RX Vref Scan: 1
5263 00:22:27.271316
5264 00:22:27.274990 RX Vref 0 -> 0, step: 1
5265 00:22:27.275055
5266 00:22:27.277897 RX Delay -69 -> 252, step: 4
5267 00:22:27.277966
5268 00:22:27.281314 Set Vref, RX VrefLevel [Byte0]: 62
5269 00:22:27.281386 [Byte1]: 53
5270 00:22:27.286646
5271 00:22:27.286718 Final RX Vref Byte 0 = 62 to rank0
5272 00:22:27.289812 Final RX Vref Byte 1 = 53 to rank0
5273 00:22:27.292954 Final RX Vref Byte 0 = 62 to rank1
5274 00:22:27.296110 Final RX Vref Byte 1 = 53 to rank1==
5275 00:22:27.299754 Dram Type= 6, Freq= 0, CH_0, rank 0
5276 00:22:27.306160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5277 00:22:27.306253 ==
5278 00:22:27.306338 DQS Delay:
5279 00:22:27.309438 DQS0 = 0, DQS1 = 0
5280 00:22:27.309505 DQM Delay:
5281 00:22:27.309560 DQM0 = 95, DQM1 = 84
5282 00:22:27.312595 DQ Delay:
5283 00:22:27.316289 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =92
5284 00:22:27.319268 DQ4 =96, DQ5 =84, DQ6 =102, DQ7 =104
5285 00:22:27.322470 DQ8 =76, DQ9 =70, DQ10 =82, DQ11 =80
5286 00:22:27.326252 DQ12 =88, DQ13 =90, DQ14 =96, DQ15 =90
5287 00:22:27.326331
5288 00:22:27.326395
5289 00:22:27.332756 [DQSOSCAuto] RK0, (LSB)MR18= 0x1515, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 415 ps
5290 00:22:27.336192 CH0 RK0: MR19=505, MR18=1515
5291 00:22:27.342634 CH0_RK0: MR19=0x505, MR18=0x1515, DQSOSC=415, MR23=63, INC=62, DEC=41
5292 00:22:27.342712
5293 00:22:27.346146 ----->DramcWriteLeveling(PI) begin...
5294 00:22:27.346225 ==
5295 00:22:27.349069 Dram Type= 6, Freq= 0, CH_0, rank 1
5296 00:22:27.352543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5297 00:22:27.352653 ==
5298 00:22:27.356028 Write leveling (Byte 0): 33 => 33
5299 00:22:27.359341 Write leveling (Byte 1): 32 => 32
5300 00:22:27.362729 DramcWriteLeveling(PI) end<-----
5301 00:22:27.362807
5302 00:22:27.362867 ==
5303 00:22:27.365601 Dram Type= 6, Freq= 0, CH_0, rank 1
5304 00:22:27.368985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5305 00:22:27.372347 ==
5306 00:22:27.372425 [Gating] SW mode calibration
5307 00:22:27.379063 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5308 00:22:27.385441 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5309 00:22:27.389227 0 14 0 | B1->B0 | 2b2b 3434 | 1 1 | (0 0) (1 1)
5310 00:22:27.395787 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5311 00:22:27.399089 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5312 00:22:27.402379 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5313 00:22:27.408862 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5314 00:22:27.412453 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5315 00:22:27.415802 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5316 00:22:27.422141 0 14 28 | B1->B0 | 3232 2929 | 1 0 | (1 0) (1 0)
5317 00:22:27.425425 0 15 0 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
5318 00:22:27.428580 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5319 00:22:27.435412 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5320 00:22:27.439052 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5321 00:22:27.442258 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5322 00:22:27.448509 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5323 00:22:27.451845 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5324 00:22:27.455263 0 15 28 | B1->B0 | 2525 3535 | 0 0 | (0 0) (0 0)
5325 00:22:27.462159 1 0 0 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
5326 00:22:27.465299 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5327 00:22:27.468867 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5328 00:22:27.471807 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5329 00:22:27.478680 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5330 00:22:27.482096 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5331 00:22:27.485172 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5332 00:22:27.491860 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5333 00:22:27.495668 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5334 00:22:27.498972 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 00:22:27.505357 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 00:22:27.508534 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 00:22:27.512155 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5338 00:22:27.518473 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5339 00:22:27.521962 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5340 00:22:27.524814 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5341 00:22:27.531451 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5342 00:22:27.534792 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 00:22:27.538074 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 00:22:27.544997 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 00:22:27.548109 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 00:22:27.551272 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5347 00:22:27.557826 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5348 00:22:27.561232 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5349 00:22:27.564555 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5350 00:22:27.567927 Total UI for P1: 0, mck2ui 16
5351 00:22:27.571141 best dqsien dly found for B0: ( 1, 2, 30)
5352 00:22:27.574582 Total UI for P1: 0, mck2ui 16
5353 00:22:27.578100 best dqsien dly found for B1: ( 1, 2, 30)
5354 00:22:27.581612 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5355 00:22:27.584625 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5356 00:22:27.584727
5357 00:22:27.591474 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5358 00:22:27.594327 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5359 00:22:27.594412 [Gating] SW calibration Done
5360 00:22:27.597768 ==
5361 00:22:27.601322 Dram Type= 6, Freq= 0, CH_0, rank 1
5362 00:22:27.604196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5363 00:22:27.604273 ==
5364 00:22:27.604333 RX Vref Scan: 0
5365 00:22:27.604388
5366 00:22:27.607563 RX Vref 0 -> 0, step: 1
5367 00:22:27.607639
5368 00:22:27.611380 RX Delay -80 -> 252, step: 8
5369 00:22:27.614547 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5370 00:22:27.617689 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5371 00:22:27.621220 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5372 00:22:27.627241 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5373 00:22:27.630718 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5374 00:22:27.634190 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5375 00:22:27.637419 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5376 00:22:27.640764 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5377 00:22:27.647110 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5378 00:22:27.650478 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5379 00:22:27.653736 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5380 00:22:27.657006 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5381 00:22:27.660367 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5382 00:22:27.667056 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5383 00:22:27.670611 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5384 00:22:27.673805 iDelay=208, Bit 15, Center 87 (-8 ~ 183) 192
5385 00:22:27.673882 ==
5386 00:22:27.677268 Dram Type= 6, Freq= 0, CH_0, rank 1
5387 00:22:27.680227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5388 00:22:27.680307 ==
5389 00:22:27.683706 DQS Delay:
5390 00:22:27.683798 DQS0 = 0, DQS1 = 0
5391 00:22:27.687177 DQM Delay:
5392 00:22:27.687268 DQM0 = 92, DQM1 = 83
5393 00:22:27.687360 DQ Delay:
5394 00:22:27.690141 DQ0 =91, DQ1 =91, DQ2 =87, DQ3 =91
5395 00:22:27.693670 DQ4 =91, DQ5 =79, DQ6 =107, DQ7 =103
5396 00:22:27.697161 DQ8 =75, DQ9 =67, DQ10 =83, DQ11 =79
5397 00:22:27.700483 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =87
5398 00:22:27.700598
5399 00:22:27.703397
5400 00:22:27.703489 ==
5401 00:22:27.706846 Dram Type= 6, Freq= 0, CH_0, rank 1
5402 00:22:27.710252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5403 00:22:27.710346 ==
5404 00:22:27.710437
5405 00:22:27.710506
5406 00:22:27.713664 TX Vref Scan disable
5407 00:22:27.713743 == TX Byte 0 ==
5408 00:22:27.720041 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5409 00:22:27.723469 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5410 00:22:27.723545 == TX Byte 1 ==
5411 00:22:27.730190 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5412 00:22:27.733389 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5413 00:22:27.733466 ==
5414 00:22:27.736629 Dram Type= 6, Freq= 0, CH_0, rank 1
5415 00:22:27.739849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5416 00:22:27.739927 ==
5417 00:22:27.739986
5418 00:22:27.740040
5419 00:22:27.743691 TX Vref Scan disable
5420 00:22:27.746531 == TX Byte 0 ==
5421 00:22:27.750117 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5422 00:22:27.753629 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5423 00:22:27.756179 == TX Byte 1 ==
5424 00:22:27.759679 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5425 00:22:27.763007 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5426 00:22:27.763083
5427 00:22:27.766094 [DATLAT]
5428 00:22:27.766183 Freq=933, CH0 RK1
5429 00:22:27.766261
5430 00:22:27.769760 DATLAT Default: 0xb
5431 00:22:27.769837 0, 0xFFFF, sum = 0
5432 00:22:27.773083 1, 0xFFFF, sum = 0
5433 00:22:27.773161 2, 0xFFFF, sum = 0
5434 00:22:27.776278 3, 0xFFFF, sum = 0
5435 00:22:27.776357 4, 0xFFFF, sum = 0
5436 00:22:27.779544 5, 0xFFFF, sum = 0
5437 00:22:27.779621 6, 0xFFFF, sum = 0
5438 00:22:27.782816 7, 0xFFFF, sum = 0
5439 00:22:27.782897 8, 0xFFFF, sum = 0
5440 00:22:27.786100 9, 0xFFFF, sum = 0
5441 00:22:27.786192 10, 0x0, sum = 1
5442 00:22:27.789648 11, 0x0, sum = 2
5443 00:22:27.789726 12, 0x0, sum = 3
5444 00:22:27.793062 13, 0x0, sum = 4
5445 00:22:27.793140 best_step = 11
5446 00:22:27.793199
5447 00:22:27.793254 ==
5448 00:22:27.796058 Dram Type= 6, Freq= 0, CH_0, rank 1
5449 00:22:27.802431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5450 00:22:27.802507 ==
5451 00:22:27.802568 RX Vref Scan: 0
5452 00:22:27.802622
5453 00:22:27.805838 RX Vref 0 -> 0, step: 1
5454 00:22:27.805917
5455 00:22:27.809307 RX Delay -77 -> 252, step: 4
5456 00:22:27.812623 iDelay=199, Bit 0, Center 92 (-1 ~ 186) 188
5457 00:22:27.819022 iDelay=199, Bit 1, Center 94 (3 ~ 186) 184
5458 00:22:27.822471 iDelay=199, Bit 2, Center 90 (-1 ~ 182) 184
5459 00:22:27.825378 iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196
5460 00:22:27.828877 iDelay=199, Bit 4, Center 92 (-1 ~ 186) 188
5461 00:22:27.832277 iDelay=199, Bit 5, Center 82 (-9 ~ 174) 184
5462 00:22:27.839073 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5463 00:22:27.841995 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5464 00:22:27.845379 iDelay=199, Bit 8, Center 78 (-13 ~ 170) 184
5465 00:22:27.848839 iDelay=199, Bit 9, Center 68 (-21 ~ 158) 180
5466 00:22:27.852193 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5467 00:22:27.858401 iDelay=199, Bit 11, Center 78 (-13 ~ 170) 184
5468 00:22:27.861711 iDelay=199, Bit 12, Center 90 (-5 ~ 186) 192
5469 00:22:27.865330 iDelay=199, Bit 13, Center 90 (-5 ~ 186) 192
5470 00:22:27.868601 iDelay=199, Bit 14, Center 94 (3 ~ 186) 184
5471 00:22:27.871894 iDelay=199, Bit 15, Center 92 (-1 ~ 186) 188
5472 00:22:27.871973 ==
5473 00:22:27.874976 Dram Type= 6, Freq= 0, CH_0, rank 1
5474 00:22:27.881453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5475 00:22:27.881572 ==
5476 00:22:27.881680 DQS Delay:
5477 00:22:27.885248 DQS0 = 0, DQS1 = 0
5478 00:22:27.885347 DQM Delay:
5479 00:22:27.885435 DQM0 = 93, DQM1 = 84
5480 00:22:27.888228 DQ Delay:
5481 00:22:27.891700 DQ0 =92, DQ1 =94, DQ2 =90, DQ3 =88
5482 00:22:27.894816 DQ4 =92, DQ5 =82, DQ6 =106, DQ7 =102
5483 00:22:27.898407 DQ8 =78, DQ9 =68, DQ10 =86, DQ11 =78
5484 00:22:27.901588 DQ12 =90, DQ13 =90, DQ14 =94, DQ15 =92
5485 00:22:27.901668
5486 00:22:27.901729
5487 00:22:27.908150 [DQSOSCAuto] RK1, (LSB)MR18= 0x2e10, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 407 ps
5488 00:22:27.911607 CH0 RK1: MR19=505, MR18=2E10
5489 00:22:27.917960 CH0_RK1: MR19=0x505, MR18=0x2E10, DQSOSC=407, MR23=63, INC=65, DEC=43
5490 00:22:27.921377 [RxdqsGatingPostProcess] freq 933
5491 00:22:27.924862 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5492 00:22:27.927742 best DQS0 dly(2T, 0.5T) = (0, 11)
5493 00:22:27.931246 best DQS1 dly(2T, 0.5T) = (0, 11)
5494 00:22:27.934669 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
5495 00:22:27.937947 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5496 00:22:27.941220 best DQS0 dly(2T, 0.5T) = (0, 10)
5497 00:22:27.944204 best DQS1 dly(2T, 0.5T) = (0, 10)
5498 00:22:27.947641 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5499 00:22:27.951131 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5500 00:22:27.954555 Pre-setting of DQS Precalculation
5501 00:22:27.960907 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5502 00:22:27.960985 ==
5503 00:22:27.964479 Dram Type= 6, Freq= 0, CH_1, rank 0
5504 00:22:27.967902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5505 00:22:27.967980 ==
5506 00:22:27.974310 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5507 00:22:27.977780 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5508 00:22:27.981674 [CA 0] Center 37 (7~68) winsize 62
5509 00:22:27.984786 [CA 1] Center 37 (7~68) winsize 62
5510 00:22:27.988049 [CA 2] Center 34 (5~64) winsize 60
5511 00:22:27.991500 [CA 3] Center 34 (5~64) winsize 60
5512 00:22:27.995035 [CA 4] Center 34 (5~64) winsize 60
5513 00:22:27.997752 [CA 5] Center 34 (4~64) winsize 61
5514 00:22:27.997863
5515 00:22:28.001053 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5516 00:22:28.001165
5517 00:22:28.004800 [CATrainingPosCal] consider 1 rank data
5518 00:22:28.008096 u2DelayCellTimex100 = 270/100 ps
5519 00:22:28.010961 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5520 00:22:28.017927 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5521 00:22:28.020953 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5522 00:22:28.024300 CA3 delay=34 (5~64),Diff = 0 PI (0 cell)
5523 00:22:28.027817 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5524 00:22:28.031221 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5525 00:22:28.031298
5526 00:22:28.034489 CA PerBit enable=1, Macro0, CA PI delay=34
5527 00:22:28.034565
5528 00:22:28.037497 [CBTSetCACLKResult] CA Dly = 34
5529 00:22:28.037574 CS Dly: 6 (0~37)
5530 00:22:28.040785 ==
5531 00:22:28.044046 Dram Type= 6, Freq= 0, CH_1, rank 1
5532 00:22:28.047428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5533 00:22:28.047505 ==
5534 00:22:28.054282 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5535 00:22:28.057255 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5536 00:22:28.061622 [CA 0] Center 38 (8~68) winsize 61
5537 00:22:28.064480 [CA 1] Center 37 (7~68) winsize 62
5538 00:22:28.068068 [CA 2] Center 35 (5~65) winsize 61
5539 00:22:28.071556 [CA 3] Center 34 (4~64) winsize 61
5540 00:22:28.074974 [CA 4] Center 35 (5~65) winsize 61
5541 00:22:28.077839 [CA 5] Center 34 (4~64) winsize 61
5542 00:22:28.077915
5543 00:22:28.081235 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5544 00:22:28.081311
5545 00:22:28.084508 [CATrainingPosCal] consider 2 rank data
5546 00:22:28.087645 u2DelayCellTimex100 = 270/100 ps
5547 00:22:28.091020 CA0 delay=38 (8~68),Diff = 4 PI (24 cell)
5548 00:22:28.097967 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5549 00:22:28.100954 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5550 00:22:28.104217 CA3 delay=34 (5~64),Diff = 0 PI (0 cell)
5551 00:22:28.107644 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5552 00:22:28.111113 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5553 00:22:28.111190
5554 00:22:28.114643 CA PerBit enable=1, Macro0, CA PI delay=34
5555 00:22:28.114719
5556 00:22:28.117554 [CBTSetCACLKResult] CA Dly = 34
5557 00:22:28.117631 CS Dly: 7 (0~39)
5558 00:22:28.117691
5559 00:22:28.124393 ----->DramcWriteLeveling(PI) begin...
5560 00:22:28.124471 ==
5561 00:22:28.127551 Dram Type= 6, Freq= 0, CH_1, rank 0
5562 00:22:28.130838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5563 00:22:28.130915 ==
5564 00:22:28.134613 Write leveling (Byte 0): 25 => 25
5565 00:22:28.137551 Write leveling (Byte 1): 27 => 27
5566 00:22:28.140965 DramcWriteLeveling(PI) end<-----
5567 00:22:28.141042
5568 00:22:28.141121 ==
5569 00:22:28.144164 Dram Type= 6, Freq= 0, CH_1, rank 0
5570 00:22:28.147766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5571 00:22:28.147843 ==
5572 00:22:28.151017 [Gating] SW mode calibration
5573 00:22:28.157576 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5574 00:22:28.164164 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5575 00:22:28.167586 0 14 0 | B1->B0 | 3333 3231 | 1 1 | (1 1) (0 0)
5576 00:22:28.171012 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5577 00:22:28.177414 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5578 00:22:28.181120 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5579 00:22:28.184079 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5580 00:22:28.191006 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5581 00:22:28.194337 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 0)
5582 00:22:28.197283 0 14 28 | B1->B0 | 2f2f 3030 | 1 0 | (1 0) (0 0)
5583 00:22:28.204142 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5584 00:22:28.207166 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5585 00:22:28.210625 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5586 00:22:28.217004 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5587 00:22:28.220506 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5588 00:22:28.224064 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5589 00:22:28.230637 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5590 00:22:28.233803 0 15 28 | B1->B0 | 2f2f 3030 | 0 0 | (0 0) (0 0)
5591 00:22:28.237207 1 0 0 | B1->B0 | 4545 4343 | 0 0 | (0 0) (0 0)
5592 00:22:28.240840 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5593 00:22:28.247400 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5594 00:22:28.250456 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5595 00:22:28.253644 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5596 00:22:28.260582 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5597 00:22:28.263969 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5598 00:22:28.267106 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5599 00:22:28.273665 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5600 00:22:28.276787 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 00:22:28.280495 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 00:22:28.286992 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 00:22:28.290422 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5604 00:22:28.293655 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5605 00:22:28.300018 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5606 00:22:28.303648 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 00:22:28.306989 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 00:22:28.313283 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 00:22:28.316811 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 00:22:28.320307 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 00:22:28.326775 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 00:22:28.330094 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 00:22:28.333540 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5614 00:22:28.339742 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5615 00:22:28.343168 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5616 00:22:28.346636 Total UI for P1: 0, mck2ui 16
5617 00:22:28.350137 best dqsien dly found for B0: ( 1, 2, 28)
5618 00:22:28.353029 Total UI for P1: 0, mck2ui 16
5619 00:22:28.356392 best dqsien dly found for B1: ( 1, 2, 28)
5620 00:22:28.359661 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5621 00:22:28.363401 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5622 00:22:28.363479
5623 00:22:28.366422 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5624 00:22:28.369728 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5625 00:22:28.373284 [Gating] SW calibration Done
5626 00:22:28.373362 ==
5627 00:22:28.376272 Dram Type= 6, Freq= 0, CH_1, rank 0
5628 00:22:28.379562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5629 00:22:28.382740 ==
5630 00:22:28.382846 RX Vref Scan: 0
5631 00:22:28.382907
5632 00:22:28.385963 RX Vref 0 -> 0, step: 1
5633 00:22:28.386040
5634 00:22:28.389601 RX Delay -80 -> 252, step: 8
5635 00:22:28.392780 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5636 00:22:28.395979 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5637 00:22:28.399116 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5638 00:22:28.402513 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5639 00:22:28.405793 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5640 00:22:28.412446 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5641 00:22:28.415718 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5642 00:22:28.418945 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5643 00:22:28.422505 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5644 00:22:28.425971 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5645 00:22:28.432719 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5646 00:22:28.435625 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5647 00:22:28.438965 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5648 00:22:28.442321 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5649 00:22:28.445777 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5650 00:22:28.452079 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5651 00:22:28.452157 ==
5652 00:22:28.455597 Dram Type= 6, Freq= 0, CH_1, rank 0
5653 00:22:28.459264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5654 00:22:28.459343 ==
5655 00:22:28.459403 DQS Delay:
5656 00:22:28.462059 DQS0 = 0, DQS1 = 0
5657 00:22:28.462137 DQM Delay:
5658 00:22:28.465581 DQM0 = 94, DQM1 = 86
5659 00:22:28.465659 DQ Delay:
5660 00:22:28.468947 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5661 00:22:28.472077 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5662 00:22:28.475773 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =83
5663 00:22:28.479018 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5664 00:22:28.479096
5665 00:22:28.479156
5666 00:22:28.479211 ==
5667 00:22:28.482357 Dram Type= 6, Freq= 0, CH_1, rank 0
5668 00:22:28.485301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5669 00:22:28.485379 ==
5670 00:22:28.488955
5671 00:22:28.489033
5672 00:22:28.489093 TX Vref Scan disable
5673 00:22:28.492150 == TX Byte 0 ==
5674 00:22:28.495461 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5675 00:22:28.498904 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5676 00:22:28.501908 == TX Byte 1 ==
5677 00:22:28.505306 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5678 00:22:28.508759 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5679 00:22:28.508836 ==
5680 00:22:28.512039 Dram Type= 6, Freq= 0, CH_1, rank 0
5681 00:22:28.518776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5682 00:22:28.518854 ==
5683 00:22:28.518913
5684 00:22:28.518967
5685 00:22:28.519020 TX Vref Scan disable
5686 00:22:28.523054 == TX Byte 0 ==
5687 00:22:28.526304 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5688 00:22:28.532931 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5689 00:22:28.533009 == TX Byte 1 ==
5690 00:22:28.536147 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5691 00:22:28.542551 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5692 00:22:28.542629
5693 00:22:28.542689 [DATLAT]
5694 00:22:28.542761 Freq=933, CH1 RK0
5695 00:22:28.542830
5696 00:22:28.545949 DATLAT Default: 0xd
5697 00:22:28.549298 0, 0xFFFF, sum = 0
5698 00:22:28.549376 1, 0xFFFF, sum = 0
5699 00:22:28.552612 2, 0xFFFF, sum = 0
5700 00:22:28.552705 3, 0xFFFF, sum = 0
5701 00:22:28.556361 4, 0xFFFF, sum = 0
5702 00:22:28.556438 5, 0xFFFF, sum = 0
5703 00:22:28.559097 6, 0xFFFF, sum = 0
5704 00:22:28.559175 7, 0xFFFF, sum = 0
5705 00:22:28.562460 8, 0xFFFF, sum = 0
5706 00:22:28.562539 9, 0xFFFF, sum = 0
5707 00:22:28.565963 10, 0x0, sum = 1
5708 00:22:28.566042 11, 0x0, sum = 2
5709 00:22:28.569455 12, 0x0, sum = 3
5710 00:22:28.569533 13, 0x0, sum = 4
5711 00:22:28.569595 best_step = 11
5712 00:22:28.569649
5713 00:22:28.572963 ==
5714 00:22:28.575817 Dram Type= 6, Freq= 0, CH_1, rank 0
5715 00:22:28.579067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5716 00:22:28.579143 ==
5717 00:22:28.579202 RX Vref Scan: 1
5718 00:22:28.579257
5719 00:22:28.582673 RX Vref 0 -> 0, step: 1
5720 00:22:28.582750
5721 00:22:28.585850 RX Delay -69 -> 252, step: 4
5722 00:22:28.585926
5723 00:22:28.589088 Set Vref, RX VrefLevel [Byte0]: 55
5724 00:22:28.592211 [Byte1]: 49
5725 00:22:28.595651
5726 00:22:28.595728 Final RX Vref Byte 0 = 55 to rank0
5727 00:22:28.599071 Final RX Vref Byte 1 = 49 to rank0
5728 00:22:28.602327 Final RX Vref Byte 0 = 55 to rank1
5729 00:22:28.605281 Final RX Vref Byte 1 = 49 to rank1==
5730 00:22:28.609098 Dram Type= 6, Freq= 0, CH_1, rank 0
5731 00:22:28.615280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5732 00:22:28.615381 ==
5733 00:22:28.615473 DQS Delay:
5734 00:22:28.615560 DQS0 = 0, DQS1 = 0
5735 00:22:28.618799 DQM Delay:
5736 00:22:28.618875 DQM0 = 96, DQM1 = 87
5737 00:22:28.622246 DQ Delay:
5738 00:22:28.625090 DQ0 =100, DQ1 =94, DQ2 =84, DQ3 =94
5739 00:22:28.628448 DQ4 =94, DQ5 =106, DQ6 =108, DQ7 =94
5740 00:22:28.631891 DQ8 =74, DQ9 =78, DQ10 =88, DQ11 =82
5741 00:22:28.635555 DQ12 =96, DQ13 =94, DQ14 =94, DQ15 =94
5742 00:22:28.635658
5743 00:22:28.635746
5744 00:22:28.641924 [DQSOSCAuto] RK0, (LSB)MR18= 0x40c, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 420 ps
5745 00:22:28.645092 CH1 RK0: MR19=505, MR18=40C
5746 00:22:28.652035 CH1_RK0: MR19=0x505, MR18=0x40C, DQSOSC=418, MR23=63, INC=62, DEC=41
5747 00:22:28.652161
5748 00:22:28.655493 ----->DramcWriteLeveling(PI) begin...
5749 00:22:28.655572 ==
5750 00:22:28.658702 Dram Type= 6, Freq= 0, CH_1, rank 1
5751 00:22:28.661911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5752 00:22:28.661990 ==
5753 00:22:28.665202 Write leveling (Byte 0): 24 => 24
5754 00:22:28.668605 Write leveling (Byte 1): 26 => 26
5755 00:22:28.672035 DramcWriteLeveling(PI) end<-----
5756 00:22:28.672112
5757 00:22:28.672172 ==
5758 00:22:28.674980 Dram Type= 6, Freq= 0, CH_1, rank 1
5759 00:22:28.678490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5760 00:22:28.678568 ==
5761 00:22:28.681885 [Gating] SW mode calibration
5762 00:22:28.688051 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5763 00:22:28.695063 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5764 00:22:28.698077 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
5765 00:22:28.704761 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5766 00:22:28.708341 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5767 00:22:28.711736 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5768 00:22:28.718013 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5769 00:22:28.721591 0 14 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5770 00:22:28.725010 0 14 24 | B1->B0 | 3333 2f2f | 0 1 | (0 0) (1 0)
5771 00:22:28.728340 0 14 28 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
5772 00:22:28.734632 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5773 00:22:28.738109 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5774 00:22:28.741593 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5775 00:22:28.747807 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5776 00:22:28.751148 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5777 00:22:28.754623 0 15 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5778 00:22:28.761358 0 15 24 | B1->B0 | 2626 3131 | 0 0 | (0 0) (0 0)
5779 00:22:28.764568 0 15 28 | B1->B0 | 3636 4646 | 1 0 | (0 0) (0 0)
5780 00:22:28.767763 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5781 00:22:28.774661 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5782 00:22:28.777801 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5783 00:22:28.781017 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5784 00:22:28.788044 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5785 00:22:28.790968 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5786 00:22:28.794161 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5787 00:22:28.800974 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5788 00:22:28.804170 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 00:22:28.807808 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 00:22:28.814046 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 00:22:28.817492 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5792 00:22:28.820951 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5793 00:22:28.827250 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5794 00:22:28.830612 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5795 00:22:28.834084 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5796 00:22:28.840469 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5797 00:22:28.844328 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 00:22:28.847039 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 00:22:28.854000 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 00:22:28.857270 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5801 00:22:28.860552 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5802 00:22:28.867204 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5803 00:22:28.870238 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5804 00:22:28.873681 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5805 00:22:28.877009 Total UI for P1: 0, mck2ui 16
5806 00:22:28.880249 best dqsien dly found for B0: ( 1, 2, 26)
5807 00:22:28.883706 Total UI for P1: 0, mck2ui 16
5808 00:22:28.887151 best dqsien dly found for B1: ( 1, 2, 28)
5809 00:22:28.890426 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5810 00:22:28.893660 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5811 00:22:28.893761
5812 00:22:28.900183 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5813 00:22:28.903315 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5814 00:22:28.903391 [Gating] SW calibration Done
5815 00:22:28.906702 ==
5816 00:22:28.910151 Dram Type= 6, Freq= 0, CH_1, rank 1
5817 00:22:28.913456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5818 00:22:28.913538 ==
5819 00:22:28.913618 RX Vref Scan: 0
5820 00:22:28.913693
5821 00:22:28.916538 RX Vref 0 -> 0, step: 1
5822 00:22:28.916641
5823 00:22:28.920094 RX Delay -80 -> 252, step: 8
5824 00:22:28.923212 iDelay=208, Bit 0, Center 95 (-8 ~ 199) 208
5825 00:22:28.926865 iDelay=208, Bit 1, Center 87 (-16 ~ 191) 208
5826 00:22:28.930384 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5827 00:22:28.936504 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5828 00:22:28.940024 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5829 00:22:28.942969 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5830 00:22:28.946488 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5831 00:22:28.949859 iDelay=208, Bit 7, Center 87 (-16 ~ 191) 208
5832 00:22:28.956560 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5833 00:22:28.959537 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5834 00:22:28.962982 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5835 00:22:28.966457 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5836 00:22:28.969800 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5837 00:22:28.976131 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5838 00:22:28.979607 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5839 00:22:28.982977 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5840 00:22:28.983066 ==
5841 00:22:28.986419 Dram Type= 6, Freq= 0, CH_1, rank 1
5842 00:22:28.989598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5843 00:22:28.989677 ==
5844 00:22:28.992619 DQS Delay:
5845 00:22:28.992708 DQS0 = 0, DQS1 = 0
5846 00:22:28.996317 DQM Delay:
5847 00:22:28.996394 DQM0 = 92, DQM1 = 87
5848 00:22:28.996456 DQ Delay:
5849 00:22:28.999721 DQ0 =95, DQ1 =87, DQ2 =83, DQ3 =87
5850 00:22:29.002587 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =87
5851 00:22:29.006578 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =83
5852 00:22:29.009561 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =95
5853 00:22:29.009678
5854 00:22:29.009766
5855 00:22:29.012593 ==
5856 00:22:29.015981 Dram Type= 6, Freq= 0, CH_1, rank 1
5857 00:22:29.019324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5858 00:22:29.019427 ==
5859 00:22:29.019520
5860 00:22:29.019585
5861 00:22:29.022646 TX Vref Scan disable
5862 00:22:29.022713 == TX Byte 0 ==
5863 00:22:29.026072 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5864 00:22:29.032489 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5865 00:22:29.032604 == TX Byte 1 ==
5866 00:22:29.039395 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5867 00:22:29.042341 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5868 00:22:29.042442 ==
5869 00:22:29.045946 Dram Type= 6, Freq= 0, CH_1, rank 1
5870 00:22:29.049571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5871 00:22:29.049685 ==
5872 00:22:29.049779
5873 00:22:29.049871
5874 00:22:29.052311 TX Vref Scan disable
5875 00:22:29.056151 == TX Byte 0 ==
5876 00:22:29.059548 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5877 00:22:29.062352 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5878 00:22:29.065861 == TX Byte 1 ==
5879 00:22:29.069324 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5880 00:22:29.072639 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5881 00:22:29.072726
5882 00:22:29.075819 [DATLAT]
5883 00:22:29.075897 Freq=933, CH1 RK1
5884 00:22:29.075957
5885 00:22:29.079353 DATLAT Default: 0xb
5886 00:22:29.079431 0, 0xFFFF, sum = 0
5887 00:22:29.082212 1, 0xFFFF, sum = 0
5888 00:22:29.082292 2, 0xFFFF, sum = 0
5889 00:22:29.085625 3, 0xFFFF, sum = 0
5890 00:22:29.085705 4, 0xFFFF, sum = 0
5891 00:22:29.089032 5, 0xFFFF, sum = 0
5892 00:22:29.089111 6, 0xFFFF, sum = 0
5893 00:22:29.092427 7, 0xFFFF, sum = 0
5894 00:22:29.092506 8, 0xFFFF, sum = 0
5895 00:22:29.095733 9, 0xFFFF, sum = 0
5896 00:22:29.095813 10, 0x0, sum = 1
5897 00:22:29.099072 11, 0x0, sum = 2
5898 00:22:29.099151 12, 0x0, sum = 3
5899 00:22:29.102194 13, 0x0, sum = 4
5900 00:22:29.102273 best_step = 11
5901 00:22:29.102334
5902 00:22:29.102391 ==
5903 00:22:29.105726 Dram Type= 6, Freq= 0, CH_1, rank 1
5904 00:22:29.109087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5905 00:22:29.112487 ==
5906 00:22:29.112578 RX Vref Scan: 0
5907 00:22:29.112640
5908 00:22:29.115346 RX Vref 0 -> 0, step: 1
5909 00:22:29.115439
5910 00:22:29.118676 RX Delay -69 -> 252, step: 4
5911 00:22:29.121824 iDelay=203, Bit 0, Center 96 (-1 ~ 194) 196
5912 00:22:29.125688 iDelay=203, Bit 1, Center 86 (-9 ~ 182) 192
5913 00:22:29.132333 iDelay=203, Bit 2, Center 80 (-17 ~ 178) 196
5914 00:22:29.135669 iDelay=203, Bit 3, Center 88 (-9 ~ 186) 196
5915 00:22:29.139013 iDelay=203, Bit 4, Center 90 (-5 ~ 186) 192
5916 00:22:29.142198 iDelay=203, Bit 5, Center 102 (7 ~ 198) 192
5917 00:22:29.145524 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
5918 00:22:29.149058 iDelay=203, Bit 7, Center 88 (-9 ~ 186) 196
5919 00:22:29.155436 iDelay=203, Bit 8, Center 76 (-17 ~ 170) 188
5920 00:22:29.158796 iDelay=203, Bit 9, Center 82 (-13 ~ 178) 192
5921 00:22:29.162082 iDelay=203, Bit 10, Center 92 (-1 ~ 186) 188
5922 00:22:29.165331 iDelay=203, Bit 11, Center 84 (-9 ~ 178) 188
5923 00:22:29.168764 iDelay=203, Bit 12, Center 100 (11 ~ 190) 180
5924 00:22:29.175143 iDelay=203, Bit 13, Center 98 (7 ~ 190) 184
5925 00:22:29.178675 iDelay=203, Bit 14, Center 100 (11 ~ 190) 180
5926 00:22:29.182171 iDelay=203, Bit 15, Center 98 (7 ~ 190) 184
5927 00:22:29.182241 ==
5928 00:22:29.185655 Dram Type= 6, Freq= 0, CH_1, rank 1
5929 00:22:29.188533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5930 00:22:29.188638 ==
5931 00:22:29.191784 DQS Delay:
5932 00:22:29.191854 DQS0 = 0, DQS1 = 0
5933 00:22:29.191946 DQM Delay:
5934 00:22:29.195486 DQM0 = 91, DQM1 = 91
5935 00:22:29.195565 DQ Delay:
5936 00:22:29.198272 DQ0 =96, DQ1 =86, DQ2 =80, DQ3 =88
5937 00:22:29.201863 DQ4 =90, DQ5 =102, DQ6 =104, DQ7 =88
5938 00:22:29.205294 DQ8 =76, DQ9 =82, DQ10 =92, DQ11 =84
5939 00:22:29.208528 DQ12 =100, DQ13 =98, DQ14 =100, DQ15 =98
5940 00:22:29.208606
5941 00:22:29.208677
5942 00:22:29.218492 [DQSOSCAuto] RK1, (LSB)MR18= 0x1428, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 415 ps
5943 00:22:29.221447 CH1 RK1: MR19=505, MR18=1428
5944 00:22:29.228386 CH1_RK1: MR19=0x505, MR18=0x1428, DQSOSC=409, MR23=63, INC=64, DEC=43
5945 00:22:29.231676 [RxdqsGatingPostProcess] freq 933
5946 00:22:29.234519 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5947 00:22:29.238079 best DQS0 dly(2T, 0.5T) = (0, 10)
5948 00:22:29.241433 best DQS1 dly(2T, 0.5T) = (0, 10)
5949 00:22:29.244543 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5950 00:22:29.247615 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5951 00:22:29.251073 best DQS0 dly(2T, 0.5T) = (0, 10)
5952 00:22:29.254597 best DQS1 dly(2T, 0.5T) = (0, 10)
5953 00:22:29.257805 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5954 00:22:29.261328 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5955 00:22:29.264390 Pre-setting of DQS Precalculation
5956 00:22:29.267581 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5957 00:22:29.274478 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5958 00:22:29.284137 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5959 00:22:29.284220
5960 00:22:29.284300
5961 00:22:29.287406 [Calibration Summary] 1866 Mbps
5962 00:22:29.287501 CH 0, Rank 0
5963 00:22:29.290865 SW Impedance : PASS
5964 00:22:29.290947 DUTY Scan : NO K
5965 00:22:29.294332 ZQ Calibration : PASS
5966 00:22:29.297777 Jitter Meter : NO K
5967 00:22:29.297858 CBT Training : PASS
5968 00:22:29.301157 Write leveling : PASS
5969 00:22:29.301239 RX DQS gating : PASS
5970 00:22:29.304054 RX DQ/DQS(RDDQC) : PASS
5971 00:22:29.307599 TX DQ/DQS : PASS
5972 00:22:29.307679 RX DATLAT : PASS
5973 00:22:29.311062 RX DQ/DQS(Engine): PASS
5974 00:22:29.314339 TX OE : NO K
5975 00:22:29.314419 All Pass.
5976 00:22:29.314497
5977 00:22:29.314571 CH 0, Rank 1
5978 00:22:29.317617 SW Impedance : PASS
5979 00:22:29.320859 DUTY Scan : NO K
5980 00:22:29.320954 ZQ Calibration : PASS
5981 00:22:29.324120 Jitter Meter : NO K
5982 00:22:29.327450 CBT Training : PASS
5983 00:22:29.327522 Write leveling : PASS
5984 00:22:29.330745 RX DQS gating : PASS
5985 00:22:29.334282 RX DQ/DQS(RDDQC) : PASS
5986 00:22:29.334376 TX DQ/DQS : PASS
5987 00:22:29.337189 RX DATLAT : PASS
5988 00:22:29.340788 RX DQ/DQS(Engine): PASS
5989 00:22:29.340864 TX OE : NO K
5990 00:22:29.344086 All Pass.
5991 00:22:29.344162
5992 00:22:29.344222 CH 1, Rank 0
5993 00:22:29.347011 SW Impedance : PASS
5994 00:22:29.347087 DUTY Scan : NO K
5995 00:22:29.350648 ZQ Calibration : PASS
5996 00:22:29.354007 Jitter Meter : NO K
5997 00:22:29.354084 CBT Training : PASS
5998 00:22:29.357103 Write leveling : PASS
5999 00:22:29.357180 RX DQS gating : PASS
6000 00:22:29.360585 RX DQ/DQS(RDDQC) : PASS
6001 00:22:29.363782 TX DQ/DQS : PASS
6002 00:22:29.363858 RX DATLAT : PASS
6003 00:22:29.367296 RX DQ/DQS(Engine): PASS
6004 00:22:29.370307 TX OE : NO K
6005 00:22:29.370385 All Pass.
6006 00:22:29.370445
6007 00:22:29.370500 CH 1, Rank 1
6008 00:22:29.373820 SW Impedance : PASS
6009 00:22:29.376871 DUTY Scan : NO K
6010 00:22:29.376947 ZQ Calibration : PASS
6011 00:22:29.380409 Jitter Meter : NO K
6012 00:22:29.383605 CBT Training : PASS
6013 00:22:29.383717 Write leveling : PASS
6014 00:22:29.386777 RX DQS gating : PASS
6015 00:22:29.390116 RX DQ/DQS(RDDQC) : PASS
6016 00:22:29.390184 TX DQ/DQS : PASS
6017 00:22:29.393637 RX DATLAT : PASS
6018 00:22:29.396967 RX DQ/DQS(Engine): PASS
6019 00:22:29.397044 TX OE : NO K
6020 00:22:29.397104 All Pass.
6021 00:22:29.400246
6022 00:22:29.400338 DramC Write-DBI off
6023 00:22:29.403871 PER_BANK_REFRESH: Hybrid Mode
6024 00:22:29.403962 TX_TRACKING: ON
6025 00:22:29.413713 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6026 00:22:29.416685 [FAST_K] Save calibration result to emmc
6027 00:22:29.420204 dramc_set_vcore_voltage set vcore to 650000
6028 00:22:29.423447 Read voltage for 400, 6
6029 00:22:29.423524 Vio18 = 0
6030 00:22:29.426838 Vcore = 650000
6031 00:22:29.426913 Vdram = 0
6032 00:22:29.426972 Vddq = 0
6033 00:22:29.427028 Vmddr = 0
6034 00:22:29.433380 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6035 00:22:29.440100 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6036 00:22:29.440177 MEM_TYPE=3, freq_sel=20
6037 00:22:29.443549 sv_algorithm_assistance_LP4_800
6038 00:22:29.446542 ============ PULL DRAM RESETB DOWN ============
6039 00:22:29.453526 ========== PULL DRAM RESETB DOWN end =========
6040 00:22:29.456497 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6041 00:22:29.459859 ===================================
6042 00:22:29.463152 LPDDR4 DRAM CONFIGURATION
6043 00:22:29.466702 ===================================
6044 00:22:29.466778 EX_ROW_EN[0] = 0x0
6045 00:22:29.470034 EX_ROW_EN[1] = 0x0
6046 00:22:29.470110 LP4Y_EN = 0x0
6047 00:22:29.473487 WORK_FSP = 0x0
6048 00:22:29.476413 WL = 0x2
6049 00:22:29.476490 RL = 0x2
6050 00:22:29.479703 BL = 0x2
6051 00:22:29.479779 RPST = 0x0
6052 00:22:29.483064 RD_PRE = 0x0
6053 00:22:29.483141 WR_PRE = 0x1
6054 00:22:29.486300 WR_PST = 0x0
6055 00:22:29.486402 DBI_WR = 0x0
6056 00:22:29.489913 DBI_RD = 0x0
6057 00:22:29.490034 OTF = 0x1
6058 00:22:29.492898 ===================================
6059 00:22:29.496276 ===================================
6060 00:22:29.499545 ANA top config
6061 00:22:29.502688 ===================================
6062 00:22:29.502812 DLL_ASYNC_EN = 0
6063 00:22:29.506009 ALL_SLAVE_EN = 1
6064 00:22:29.509673 NEW_RANK_MODE = 1
6065 00:22:29.512878 DLL_IDLE_MODE = 1
6066 00:22:29.512956 LP45_APHY_COMB_EN = 1
6067 00:22:29.516366 TX_ODT_DIS = 1
6068 00:22:29.519799 NEW_8X_MODE = 1
6069 00:22:29.522776 ===================================
6070 00:22:29.526125 ===================================
6071 00:22:29.529441 data_rate = 800
6072 00:22:29.532939 CKR = 1
6073 00:22:29.536268 DQ_P2S_RATIO = 4
6074 00:22:29.539544 ===================================
6075 00:22:29.539621 CA_P2S_RATIO = 4
6076 00:22:29.543124 DQ_CA_OPEN = 0
6077 00:22:29.546355 DQ_SEMI_OPEN = 1
6078 00:22:29.549834 CA_SEMI_OPEN = 1
6079 00:22:29.552674 CA_FULL_RATE = 0
6080 00:22:29.556264 DQ_CKDIV4_EN = 0
6081 00:22:29.556376 CA_CKDIV4_EN = 1
6082 00:22:29.559636 CA_PREDIV_EN = 0
6083 00:22:29.562574 PH8_DLY = 0
6084 00:22:29.565800 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6085 00:22:29.569717 DQ_AAMCK_DIV = 0
6086 00:22:29.572625 CA_AAMCK_DIV = 0
6087 00:22:29.572772 CA_ADMCK_DIV = 4
6088 00:22:29.576148 DQ_TRACK_CA_EN = 0
6089 00:22:29.579518 CA_PICK = 800
6090 00:22:29.582396 CA_MCKIO = 400
6091 00:22:29.585693 MCKIO_SEMI = 400
6092 00:22:29.589210 PLL_FREQ = 3016
6093 00:22:29.592676 DQ_UI_PI_RATIO = 32
6094 00:22:29.592799 CA_UI_PI_RATIO = 32
6095 00:22:29.595526 ===================================
6096 00:22:29.598812 ===================================
6097 00:22:29.602660 memory_type:LPDDR4
6098 00:22:29.606035 GP_NUM : 10
6099 00:22:29.606146 SRAM_EN : 1
6100 00:22:29.609391 MD32_EN : 0
6101 00:22:29.612328 ===================================
6102 00:22:29.615514 [ANA_INIT] >>>>>>>>>>>>>>
6103 00:22:29.619083 <<<<<< [CONFIGURE PHASE]: ANA_TX
6104 00:22:29.622436 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6105 00:22:29.625671 ===================================
6106 00:22:29.625782 data_rate = 800,PCW = 0X7400
6107 00:22:29.629130 ===================================
6108 00:22:29.632337 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6109 00:22:29.639049 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6110 00:22:29.652237 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6111 00:22:29.655358 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6112 00:22:29.658775 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6113 00:22:29.662064 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6114 00:22:29.665576 [ANA_INIT] flow start
6115 00:22:29.665641 [ANA_INIT] PLL >>>>>>>>
6116 00:22:29.668972 [ANA_INIT] PLL <<<<<<<<
6117 00:22:29.671867 [ANA_INIT] MIDPI >>>>>>>>
6118 00:22:29.671933 [ANA_INIT] MIDPI <<<<<<<<
6119 00:22:29.675226 [ANA_INIT] DLL >>>>>>>>
6120 00:22:29.678759 [ANA_INIT] flow end
6121 00:22:29.682141 ============ LP4 DIFF to SE enter ============
6122 00:22:29.685511 ============ LP4 DIFF to SE exit ============
6123 00:22:29.688412 [ANA_INIT] <<<<<<<<<<<<<
6124 00:22:29.692258 [Flow] Enable top DCM control >>>>>
6125 00:22:29.695663 [Flow] Enable top DCM control <<<<<
6126 00:22:29.698574 Enable DLL master slave shuffle
6127 00:22:29.702051 ==============================================================
6128 00:22:29.705293 Gating Mode config
6129 00:22:29.712155 ==============================================================
6130 00:22:29.712245 Config description:
6131 00:22:29.722126 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6132 00:22:29.728461 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6133 00:22:29.735303 SELPH_MODE 0: By rank 1: By Phase
6134 00:22:29.738405 ==============================================================
6135 00:22:29.741997 GAT_TRACK_EN = 0
6136 00:22:29.745111 RX_GATING_MODE = 2
6137 00:22:29.748167 RX_GATING_TRACK_MODE = 2
6138 00:22:29.752031 SELPH_MODE = 1
6139 00:22:29.755049 PICG_EARLY_EN = 1
6140 00:22:29.758116 VALID_LAT_VALUE = 1
6141 00:22:29.761544 ==============================================================
6142 00:22:29.764578 Enter into Gating configuration >>>>
6143 00:22:29.768349 Exit from Gating configuration <<<<
6144 00:22:29.771785 Enter into DVFS_PRE_config >>>>>
6145 00:22:29.784439 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6146 00:22:29.787873 Exit from DVFS_PRE_config <<<<<
6147 00:22:29.791451 Enter into PICG configuration >>>>
6148 00:22:29.794464 Exit from PICG configuration <<<<
6149 00:22:29.794579 [RX_INPUT] configuration >>>>>
6150 00:22:29.797999 [RX_INPUT] configuration <<<<<
6151 00:22:29.804298 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6152 00:22:29.807831 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6153 00:22:29.814533 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6154 00:22:29.820987 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6155 00:22:29.827790 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6156 00:22:29.834054 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6157 00:22:29.837554 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6158 00:22:29.840859 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6159 00:22:29.847374 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6160 00:22:29.850922 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6161 00:22:29.853799 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6162 00:22:29.857163 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6163 00:22:29.860664 ===================================
6164 00:22:29.863967 LPDDR4 DRAM CONFIGURATION
6165 00:22:29.867041 ===================================
6166 00:22:29.870587 EX_ROW_EN[0] = 0x0
6167 00:22:29.870665 EX_ROW_EN[1] = 0x0
6168 00:22:29.874082 LP4Y_EN = 0x0
6169 00:22:29.874161 WORK_FSP = 0x0
6170 00:22:29.877211 WL = 0x2
6171 00:22:29.877289 RL = 0x2
6172 00:22:29.880624 BL = 0x2
6173 00:22:29.880711 RPST = 0x0
6174 00:22:29.884032 RD_PRE = 0x0
6175 00:22:29.887222 WR_PRE = 0x1
6176 00:22:29.887300 WR_PST = 0x0
6177 00:22:29.890649 DBI_WR = 0x0
6178 00:22:29.890727 DBI_RD = 0x0
6179 00:22:29.893684 OTF = 0x1
6180 00:22:29.897105 ===================================
6181 00:22:29.900595 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6182 00:22:29.903541 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6183 00:22:29.907278 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6184 00:22:29.910650 ===================================
6185 00:22:29.913923 LPDDR4 DRAM CONFIGURATION
6186 00:22:29.916824 ===================================
6187 00:22:29.920060 EX_ROW_EN[0] = 0x10
6188 00:22:29.920130 EX_ROW_EN[1] = 0x0
6189 00:22:29.923576 LP4Y_EN = 0x0
6190 00:22:29.923646 WORK_FSP = 0x0
6191 00:22:29.926971 WL = 0x2
6192 00:22:29.927040 RL = 0x2
6193 00:22:29.930358 BL = 0x2
6194 00:22:29.930424 RPST = 0x0
6195 00:22:29.933789 RD_PRE = 0x0
6196 00:22:29.933856 WR_PRE = 0x1
6197 00:22:29.936747 WR_PST = 0x0
6198 00:22:29.940161 DBI_WR = 0x0
6199 00:22:29.940230 DBI_RD = 0x0
6200 00:22:29.943624 OTF = 0x1
6201 00:22:29.947008 ===================================
6202 00:22:29.949869 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6203 00:22:29.955210 nWR fixed to 30
6204 00:22:29.958702 [ModeRegInit_LP4] CH0 RK0
6205 00:22:29.958790 [ModeRegInit_LP4] CH0 RK1
6206 00:22:29.961609 [ModeRegInit_LP4] CH1 RK0
6207 00:22:29.965177 [ModeRegInit_LP4] CH1 RK1
6208 00:22:29.965253 match AC timing 19
6209 00:22:29.971969 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6210 00:22:29.975235 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6211 00:22:29.978348 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6212 00:22:29.985253 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6213 00:22:29.988529 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6214 00:22:29.988615 ==
6215 00:22:29.991764 Dram Type= 6, Freq= 0, CH_0, rank 0
6216 00:22:29.995198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6217 00:22:29.995292 ==
6218 00:22:30.001359 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6219 00:22:30.008154 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6220 00:22:30.011542 [CA 0] Center 36 (8~64) winsize 57
6221 00:22:30.015216 [CA 1] Center 36 (8~64) winsize 57
6222 00:22:30.018405 [CA 2] Center 36 (8~64) winsize 57
6223 00:22:30.021833 [CA 3] Center 36 (8~64) winsize 57
6224 00:22:30.021912 [CA 4] Center 36 (8~64) winsize 57
6225 00:22:30.025120 [CA 5] Center 36 (8~64) winsize 57
6226 00:22:30.025199
6227 00:22:30.031494 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6228 00:22:30.031571
6229 00:22:30.034876 [CATrainingPosCal] consider 1 rank data
6230 00:22:30.038333 u2DelayCellTimex100 = 270/100 ps
6231 00:22:30.041246 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6232 00:22:30.044667 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6233 00:22:30.048187 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6234 00:22:30.051558 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6235 00:22:30.054910 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6236 00:22:30.058269 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6237 00:22:30.058346
6238 00:22:30.061675 CA PerBit enable=1, Macro0, CA PI delay=36
6239 00:22:30.061754
6240 00:22:30.064589 [CBTSetCACLKResult] CA Dly = 36
6241 00:22:30.067999 CS Dly: 1 (0~32)
6242 00:22:30.068077 ==
6243 00:22:30.071242 Dram Type= 6, Freq= 0, CH_0, rank 1
6244 00:22:30.074706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6245 00:22:30.074784 ==
6246 00:22:30.081124 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6247 00:22:30.084468 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6248 00:22:30.088263 [CA 0] Center 36 (8~64) winsize 57
6249 00:22:30.091517 [CA 1] Center 36 (8~64) winsize 57
6250 00:22:30.094496 [CA 2] Center 36 (8~64) winsize 57
6251 00:22:30.097977 [CA 3] Center 36 (8~64) winsize 57
6252 00:22:30.101177 [CA 4] Center 36 (8~64) winsize 57
6253 00:22:30.104361 [CA 5] Center 36 (8~64) winsize 57
6254 00:22:30.104437
6255 00:22:30.107577 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6256 00:22:30.107654
6257 00:22:30.111148 [CATrainingPosCal] consider 2 rank data
6258 00:22:30.114362 u2DelayCellTimex100 = 270/100 ps
6259 00:22:30.117809 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6260 00:22:30.120893 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6261 00:22:30.127957 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6262 00:22:30.131110 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6263 00:22:30.134503 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6264 00:22:30.137973 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6265 00:22:30.138050
6266 00:22:30.141340 CA PerBit enable=1, Macro0, CA PI delay=36
6267 00:22:30.141417
6268 00:22:30.144277 [CBTSetCACLKResult] CA Dly = 36
6269 00:22:30.144353 CS Dly: 1 (0~32)
6270 00:22:30.144414
6271 00:22:30.147671 ----->DramcWriteLeveling(PI) begin...
6272 00:22:30.150992 ==
6273 00:22:30.154316 Dram Type= 6, Freq= 0, CH_0, rank 0
6274 00:22:30.157834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6275 00:22:30.157912 ==
6276 00:22:30.161159 Write leveling (Byte 0): 40 => 8
6277 00:22:30.164572 Write leveling (Byte 1): 40 => 8
6278 00:22:30.167438 DramcWriteLeveling(PI) end<-----
6279 00:22:30.167515
6280 00:22:30.167575 ==
6281 00:22:30.170779 Dram Type= 6, Freq= 0, CH_0, rank 0
6282 00:22:30.174048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6283 00:22:30.174125 ==
6284 00:22:30.177547 [Gating] SW mode calibration
6285 00:22:30.184518 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6286 00:22:30.187565 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6287 00:22:30.194243 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6288 00:22:30.197570 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6289 00:22:30.200556 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6290 00:22:30.207505 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6291 00:22:30.210827 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6292 00:22:30.214132 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6293 00:22:30.220438 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6294 00:22:30.223725 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6295 00:22:30.227261 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6296 00:22:30.230676 Total UI for P1: 0, mck2ui 16
6297 00:22:30.234010 best dqsien dly found for B0: ( 0, 14, 24)
6298 00:22:30.237076 Total UI for P1: 0, mck2ui 16
6299 00:22:30.240379 best dqsien dly found for B1: ( 0, 14, 24)
6300 00:22:30.243845 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6301 00:22:30.250657 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6302 00:22:30.250771
6303 00:22:30.253622 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6304 00:22:30.256907 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6305 00:22:30.260266 [Gating] SW calibration Done
6306 00:22:30.260380 ==
6307 00:22:30.263549 Dram Type= 6, Freq= 0, CH_0, rank 0
6308 00:22:30.266804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6309 00:22:30.266919 ==
6310 00:22:30.267021 RX Vref Scan: 0
6311 00:22:30.270280
6312 00:22:30.270391 RX Vref 0 -> 0, step: 1
6313 00:22:30.270495
6314 00:22:30.273779 RX Delay -410 -> 252, step: 16
6315 00:22:30.277135 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6316 00:22:30.283527 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6317 00:22:30.286899 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6318 00:22:30.290286 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6319 00:22:30.293255 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6320 00:22:30.300236 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6321 00:22:30.303492 iDelay=230, Bit 6, Center -35 (-282 ~ 213) 496
6322 00:22:30.306717 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6323 00:22:30.310032 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6324 00:22:30.317187 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6325 00:22:30.319996 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6326 00:22:30.323399 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6327 00:22:30.326705 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6328 00:22:30.333642 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6329 00:22:30.336876 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6330 00:22:30.339729 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6331 00:22:30.339843 ==
6332 00:22:30.343634 Dram Type= 6, Freq= 0, CH_0, rank 0
6333 00:22:30.350001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6334 00:22:30.350111 ==
6335 00:22:30.350213 DQS Delay:
6336 00:22:30.353170 DQS0 = 59, DQS1 = 59
6337 00:22:30.353292 DQM Delay:
6338 00:22:30.353377 DQM0 = 17, DQM1 = 10
6339 00:22:30.356576 DQ Delay:
6340 00:22:30.360005 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6341 00:22:30.363293 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =32
6342 00:22:30.363391 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6343 00:22:30.369857 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6344 00:22:30.369965
6345 00:22:30.370064
6346 00:22:30.370159 ==
6347 00:22:30.373151 Dram Type= 6, Freq= 0, CH_0, rank 0
6348 00:22:30.376080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6349 00:22:30.376187 ==
6350 00:22:30.376286
6351 00:22:30.376382
6352 00:22:30.379566 TX Vref Scan disable
6353 00:22:30.379671 == TX Byte 0 ==
6354 00:22:30.386449 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6355 00:22:30.389635 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6356 00:22:30.389711 == TX Byte 1 ==
6357 00:22:30.392936 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6358 00:22:30.399588 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6359 00:22:30.399665 ==
6360 00:22:30.402469 Dram Type= 6, Freq= 0, CH_0, rank 0
6361 00:22:30.406077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6362 00:22:30.406155 ==
6363 00:22:30.406216
6364 00:22:30.406272
6365 00:22:30.409200 TX Vref Scan disable
6366 00:22:30.409279 == TX Byte 0 ==
6367 00:22:30.416157 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6368 00:22:30.419488 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6369 00:22:30.419615 == TX Byte 1 ==
6370 00:22:30.425802 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6371 00:22:30.429158 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6372 00:22:30.429281
6373 00:22:30.429346 [DATLAT]
6374 00:22:30.432508 Freq=400, CH0 RK0
6375 00:22:30.432600
6376 00:22:30.432671 DATLAT Default: 0xf
6377 00:22:30.435628 0, 0xFFFF, sum = 0
6378 00:22:30.435752 1, 0xFFFF, sum = 0
6379 00:22:30.438955 2, 0xFFFF, sum = 0
6380 00:22:30.439029 3, 0xFFFF, sum = 0
6381 00:22:30.442271 4, 0xFFFF, sum = 0
6382 00:22:30.442351 5, 0xFFFF, sum = 0
6383 00:22:30.445876 6, 0xFFFF, sum = 0
6384 00:22:30.445956 7, 0xFFFF, sum = 0
6385 00:22:30.449220 8, 0xFFFF, sum = 0
6386 00:22:30.449300 9, 0xFFFF, sum = 0
6387 00:22:30.452554 10, 0xFFFF, sum = 0
6388 00:22:30.455957 11, 0xFFFF, sum = 0
6389 00:22:30.456037 12, 0xFFFF, sum = 0
6390 00:22:30.459241 13, 0x0, sum = 1
6391 00:22:30.459320 14, 0x0, sum = 2
6392 00:22:30.459386 15, 0x0, sum = 3
6393 00:22:30.462493 16, 0x0, sum = 4
6394 00:22:30.462572 best_step = 14
6395 00:22:30.462634
6396 00:22:30.465842 ==
6397 00:22:30.465920 Dram Type= 6, Freq= 0, CH_0, rank 0
6398 00:22:30.472400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6399 00:22:30.472480 ==
6400 00:22:30.472541 RX Vref Scan: 1
6401 00:22:30.472598
6402 00:22:30.475275 RX Vref 0 -> 0, step: 1
6403 00:22:30.475353
6404 00:22:30.478872 RX Delay -359 -> 252, step: 8
6405 00:22:30.478950
6406 00:22:30.482270 Set Vref, RX VrefLevel [Byte0]: 62
6407 00:22:30.485416 [Byte1]: 53
6408 00:22:30.488689
6409 00:22:30.488805 Final RX Vref Byte 0 = 62 to rank0
6410 00:22:30.492324 Final RX Vref Byte 1 = 53 to rank0
6411 00:22:30.495867 Final RX Vref Byte 0 = 62 to rank1
6412 00:22:30.499336 Final RX Vref Byte 1 = 53 to rank1==
6413 00:22:30.502103 Dram Type= 6, Freq= 0, CH_0, rank 0
6414 00:22:30.509007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6415 00:22:30.509120 ==
6416 00:22:30.509220 DQS Delay:
6417 00:22:30.509319 DQS0 = 60, DQS1 = 68
6418 00:22:30.512250 DQM Delay:
6419 00:22:30.512331 DQM0 = 14, DQM1 = 14
6420 00:22:30.515623 DQ Delay:
6421 00:22:30.519124 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =12
6422 00:22:30.521984 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6423 00:22:30.522063 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6424 00:22:30.525811 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =20
6425 00:22:30.528678
6426 00:22:30.528770
6427 00:22:30.535285 [DQSOSCAuto] RK0, (LSB)MR18= 0x8f8c, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 391 ps
6428 00:22:30.538514 CH0 RK0: MR19=C0C, MR18=8F8C
6429 00:22:30.545112 CH0_RK0: MR19=0xC0C, MR18=0x8F8C, DQSOSC=391, MR23=63, INC=386, DEC=257
6430 00:22:30.545245 ==
6431 00:22:30.548934 Dram Type= 6, Freq= 0, CH_0, rank 1
6432 00:22:30.552184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6433 00:22:30.552278 ==
6434 00:22:30.555558 [Gating] SW mode calibration
6435 00:22:30.561861 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6436 00:22:30.568574 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6437 00:22:30.571980 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6438 00:22:30.575298 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6439 00:22:30.582158 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6440 00:22:30.585051 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6441 00:22:30.588549 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6442 00:22:30.595262 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6443 00:22:30.598536 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6444 00:22:30.602017 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6445 00:22:30.608436 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6446 00:22:30.608544 Total UI for P1: 0, mck2ui 16
6447 00:22:30.611504 best dqsien dly found for B0: ( 0, 14, 24)
6448 00:22:30.615051 Total UI for P1: 0, mck2ui 16
6449 00:22:30.617979 best dqsien dly found for B1: ( 0, 14, 24)
6450 00:22:30.624948 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6451 00:22:30.628335 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6452 00:22:30.628411
6453 00:22:30.631723 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6454 00:22:30.634671 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6455 00:22:30.638216 [Gating] SW calibration Done
6456 00:22:30.638292 ==
6457 00:22:30.641317 Dram Type= 6, Freq= 0, CH_0, rank 1
6458 00:22:30.644595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6459 00:22:30.644709 ==
6460 00:22:30.648483 RX Vref Scan: 0
6461 00:22:30.648595
6462 00:22:30.648712 RX Vref 0 -> 0, step: 1
6463 00:22:30.648770
6464 00:22:30.651636 RX Delay -410 -> 252, step: 16
6465 00:22:30.658228 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6466 00:22:30.664353 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6467 00:22:30.664668 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6468 00:22:30.668020 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6469 00:22:30.671489 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6470 00:22:30.678179 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6471 00:22:30.681110 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6472 00:22:30.684548 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6473 00:22:30.691251 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6474 00:22:30.694523 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6475 00:22:30.697934 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6476 00:22:30.701427 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6477 00:22:30.707800 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6478 00:22:30.711360 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6479 00:22:30.714255 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6480 00:22:30.717893 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6481 00:22:30.721102 ==
6482 00:22:30.721203 Dram Type= 6, Freq= 0, CH_0, rank 1
6483 00:22:30.727543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6484 00:22:30.727621 ==
6485 00:22:30.727682 DQS Delay:
6486 00:22:30.730953 DQS0 = 59, DQS1 = 59
6487 00:22:30.731029 DQM Delay:
6488 00:22:30.734411 DQM0 = 16, DQM1 = 10
6489 00:22:30.734489 DQ Delay:
6490 00:22:30.737422 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6491 00:22:30.740908 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6492 00:22:30.744105 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6493 00:22:30.747457 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6494 00:22:30.747536
6495 00:22:30.747597
6496 00:22:30.747654 ==
6497 00:22:30.750875 Dram Type= 6, Freq= 0, CH_0, rank 1
6498 00:22:30.754103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6499 00:22:30.754194 ==
6500 00:22:30.754255
6501 00:22:30.754311
6502 00:22:30.757801 TX Vref Scan disable
6503 00:22:30.757880 == TX Byte 0 ==
6504 00:22:30.764123 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6505 00:22:30.767578 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6506 00:22:30.767655 == TX Byte 1 ==
6507 00:22:30.774296 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6508 00:22:30.777543 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6509 00:22:30.777649 ==
6510 00:22:30.780969 Dram Type= 6, Freq= 0, CH_0, rank 1
6511 00:22:30.783820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6512 00:22:30.783911 ==
6513 00:22:30.783971
6514 00:22:30.784026
6515 00:22:30.787239 TX Vref Scan disable
6516 00:22:30.787317 == TX Byte 0 ==
6517 00:22:30.794034 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6518 00:22:30.796952 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6519 00:22:30.797028 == TX Byte 1 ==
6520 00:22:30.803682 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6521 00:22:30.807200 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6522 00:22:30.807299
6523 00:22:30.807386 [DATLAT]
6524 00:22:30.810496 Freq=400, CH0 RK1
6525 00:22:30.810561
6526 00:22:30.810617 DATLAT Default: 0xe
6527 00:22:30.813969 0, 0xFFFF, sum = 0
6528 00:22:30.814049 1, 0xFFFF, sum = 0
6529 00:22:30.816822 2, 0xFFFF, sum = 0
6530 00:22:30.816901 3, 0xFFFF, sum = 0
6531 00:22:30.820274 4, 0xFFFF, sum = 0
6532 00:22:30.820354 5, 0xFFFF, sum = 0
6533 00:22:30.823551 6, 0xFFFF, sum = 0
6534 00:22:30.823630 7, 0xFFFF, sum = 0
6535 00:22:30.827012 8, 0xFFFF, sum = 0
6536 00:22:30.830419 9, 0xFFFF, sum = 0
6537 00:22:30.830499 10, 0xFFFF, sum = 0
6538 00:22:30.833266 11, 0xFFFF, sum = 0
6539 00:22:30.833349 12, 0xFFFF, sum = 0
6540 00:22:30.836534 13, 0x0, sum = 1
6541 00:22:30.836607 14, 0x0, sum = 2
6542 00:22:30.839936 15, 0x0, sum = 3
6543 00:22:30.840016 16, 0x0, sum = 4
6544 00:22:30.840078 best_step = 14
6545 00:22:30.843235
6546 00:22:30.843313 ==
6547 00:22:30.846629 Dram Type= 6, Freq= 0, CH_0, rank 1
6548 00:22:30.849741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6549 00:22:30.849818 ==
6550 00:22:30.849879 RX Vref Scan: 0
6551 00:22:30.849938
6552 00:22:30.853193 RX Vref 0 -> 0, step: 1
6553 00:22:30.853265
6554 00:22:30.856662 RX Delay -359 -> 252, step: 8
6555 00:22:30.863815 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6556 00:22:30.867431 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6557 00:22:30.870467 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6558 00:22:30.873728 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6559 00:22:30.880470 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6560 00:22:30.883500 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6561 00:22:30.886712 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6562 00:22:30.890179 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6563 00:22:30.896998 iDelay=217, Bit 8, Center -60 (-311 ~ 192) 504
6564 00:22:30.900452 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6565 00:22:30.903860 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6566 00:22:30.910279 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6567 00:22:30.913301 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6568 00:22:30.916666 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6569 00:22:30.920002 iDelay=217, Bit 14, Center -44 (-295 ~ 208) 504
6570 00:22:30.926582 iDelay=217, Bit 15, Center -52 (-303 ~ 200) 504
6571 00:22:30.926661 ==
6572 00:22:30.930289 Dram Type= 6, Freq= 0, CH_0, rank 1
6573 00:22:30.933263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6574 00:22:30.933332 ==
6575 00:22:30.933390 DQS Delay:
6576 00:22:30.936617 DQS0 = 60, DQS1 = 72
6577 00:22:30.936706 DQM Delay:
6578 00:22:30.939901 DQM0 = 11, DQM1 = 17
6579 00:22:30.939968 DQ Delay:
6580 00:22:30.943228 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6581 00:22:30.946637 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6582 00:22:30.950049 DQ8 =12, DQ9 =0, DQ10 =20, DQ11 =12
6583 00:22:30.953228 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =20
6584 00:22:30.953298
6585 00:22:30.953356
6586 00:22:30.959751 [DQSOSCAuto] RK1, (LSB)MR18= 0xd086, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 384 ps
6587 00:22:30.963128 CH0 RK1: MR19=C0C, MR18=D086
6588 00:22:30.970006 CH0_RK1: MR19=0xC0C, MR18=0xD086, DQSOSC=384, MR23=63, INC=400, DEC=267
6589 00:22:30.972991 [RxdqsGatingPostProcess] freq 400
6590 00:22:30.979699 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6591 00:22:30.982804 best DQS0 dly(2T, 0.5T) = (0, 10)
6592 00:22:30.982933 best DQS1 dly(2T, 0.5T) = (0, 10)
6593 00:22:30.986131 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6594 00:22:30.989527 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6595 00:22:30.993107 best DQS0 dly(2T, 0.5T) = (0, 10)
6596 00:22:30.996236 best DQS1 dly(2T, 0.5T) = (0, 10)
6597 00:22:30.999568 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6598 00:22:31.003006 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6599 00:22:31.006385 Pre-setting of DQS Precalculation
6600 00:22:31.012628 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6601 00:22:31.012751 ==
6602 00:22:31.016113 Dram Type= 6, Freq= 0, CH_1, rank 0
6603 00:22:31.019346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6604 00:22:31.019461 ==
6605 00:22:31.025929 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6606 00:22:31.032428 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6607 00:22:31.032543 [CA 0] Center 36 (8~64) winsize 57
6608 00:22:31.035713 [CA 1] Center 36 (8~64) winsize 57
6609 00:22:31.039298 [CA 2] Center 36 (8~64) winsize 57
6610 00:22:31.042499 [CA 3] Center 36 (8~64) winsize 57
6611 00:22:31.045660 [CA 4] Center 36 (8~64) winsize 57
6612 00:22:31.049088 [CA 5] Center 36 (8~64) winsize 57
6613 00:22:31.049201
6614 00:22:31.052513 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6615 00:22:31.052626
6616 00:22:31.055920 [CATrainingPosCal] consider 1 rank data
6617 00:22:31.059178 u2DelayCellTimex100 = 270/100 ps
6618 00:22:31.062475 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6619 00:22:31.068763 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6620 00:22:31.072227 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6621 00:22:31.075589 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6622 00:22:31.078743 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6623 00:22:31.082138 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6624 00:22:31.082252
6625 00:22:31.085461 CA PerBit enable=1, Macro0, CA PI delay=36
6626 00:22:31.085574
6627 00:22:31.088830 [CBTSetCACLKResult] CA Dly = 36
6628 00:22:31.091833 CS Dly: 1 (0~32)
6629 00:22:31.091948 ==
6630 00:22:31.095325 Dram Type= 6, Freq= 0, CH_1, rank 1
6631 00:22:31.098526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6632 00:22:31.098641 ==
6633 00:22:31.105112 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6634 00:22:31.108486 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6635 00:22:31.111950 [CA 0] Center 36 (8~64) winsize 57
6636 00:22:31.115235 [CA 1] Center 36 (8~64) winsize 57
6637 00:22:31.118650 [CA 2] Center 36 (8~64) winsize 57
6638 00:22:31.121527 [CA 3] Center 36 (8~64) winsize 57
6639 00:22:31.124969 [CA 4] Center 36 (8~64) winsize 57
6640 00:22:31.128286 [CA 5] Center 36 (8~64) winsize 57
6641 00:22:31.128400
6642 00:22:31.131543 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6643 00:22:31.131654
6644 00:22:31.134898 [CATrainingPosCal] consider 2 rank data
6645 00:22:31.138094 u2DelayCellTimex100 = 270/100 ps
6646 00:22:31.141657 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6647 00:22:31.144677 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6648 00:22:31.148360 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6649 00:22:31.154345 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6650 00:22:31.158251 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6651 00:22:31.161045 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6652 00:22:31.161121
6653 00:22:31.164851 CA PerBit enable=1, Macro0, CA PI delay=36
6654 00:22:31.164923
6655 00:22:31.167734 [CBTSetCACLKResult] CA Dly = 36
6656 00:22:31.167852 CS Dly: 1 (0~32)
6657 00:22:31.167956
6658 00:22:31.171091 ----->DramcWriteLeveling(PI) begin...
6659 00:22:31.174554 ==
6660 00:22:31.178028 Dram Type= 6, Freq= 0, CH_1, rank 0
6661 00:22:31.181296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6662 00:22:31.181410 ==
6663 00:22:31.184585 Write leveling (Byte 0): 40 => 8
6664 00:22:31.187888 Write leveling (Byte 1): 40 => 8
6665 00:22:31.190718 DramcWriteLeveling(PI) end<-----
6666 00:22:31.190832
6667 00:22:31.190938 ==
6668 00:22:31.194509 Dram Type= 6, Freq= 0, CH_1, rank 0
6669 00:22:31.197585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6670 00:22:31.197699 ==
6671 00:22:31.201240 [Gating] SW mode calibration
6672 00:22:31.207494 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6673 00:22:31.214075 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6674 00:22:31.217449 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6675 00:22:31.220804 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6676 00:22:31.227050 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6677 00:22:31.230449 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6678 00:22:31.233798 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6679 00:22:31.240375 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6680 00:22:31.243824 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6681 00:22:31.247077 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6682 00:22:31.253715 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6683 00:22:31.253902 Total UI for P1: 0, mck2ui 16
6684 00:22:31.260180 best dqsien dly found for B0: ( 0, 14, 24)
6685 00:22:31.260352 Total UI for P1: 0, mck2ui 16
6686 00:22:31.263868 best dqsien dly found for B1: ( 0, 14, 24)
6687 00:22:31.270436 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6688 00:22:31.273485 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6689 00:22:31.273603
6690 00:22:31.276726 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6691 00:22:31.280000 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6692 00:22:31.283409 [Gating] SW calibration Done
6693 00:22:31.283521 ==
6694 00:22:31.286678 Dram Type= 6, Freq= 0, CH_1, rank 0
6695 00:22:31.290117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6696 00:22:31.290202 ==
6697 00:22:31.293609 RX Vref Scan: 0
6698 00:22:31.293686
6699 00:22:31.293747 RX Vref 0 -> 0, step: 1
6700 00:22:31.293804
6701 00:22:31.296475 RX Delay -410 -> 252, step: 16
6702 00:22:31.303233 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6703 00:22:31.306681 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6704 00:22:31.310063 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6705 00:22:31.313259 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6706 00:22:31.319988 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6707 00:22:31.323036 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6708 00:22:31.326524 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6709 00:22:31.329828 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6710 00:22:31.336165 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6711 00:22:31.339947 iDelay=230, Bit 9, Center -67 (-330 ~ 197) 528
6712 00:22:31.342739 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6713 00:22:31.346124 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6714 00:22:31.352800 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6715 00:22:31.356384 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6716 00:22:31.359253 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6717 00:22:31.362731 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6718 00:22:31.366141 ==
6719 00:22:31.369237 Dram Type= 6, Freq= 0, CH_1, rank 0
6720 00:22:31.373053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6721 00:22:31.373131 ==
6722 00:22:31.373192 DQS Delay:
6723 00:22:31.376170 DQS0 = 51, DQS1 = 67
6724 00:22:31.376270 DQM Delay:
6725 00:22:31.379075 DQM0 = 12, DQM1 = 17
6726 00:22:31.379190 DQ Delay:
6727 00:22:31.382917 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6728 00:22:31.385997 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6729 00:22:31.389290 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6730 00:22:31.392540 DQ12 =24, DQ13 =32, DQ14 =24, DQ15 =24
6731 00:22:31.392663
6732 00:22:31.392739
6733 00:22:31.392794 ==
6734 00:22:31.395915 Dram Type= 6, Freq= 0, CH_1, rank 0
6735 00:22:31.399369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6736 00:22:31.399446 ==
6737 00:22:31.399506
6738 00:22:31.399561
6739 00:22:31.402267 TX Vref Scan disable
6740 00:22:31.402343 == TX Byte 0 ==
6741 00:22:31.409343 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6742 00:22:31.412277 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6743 00:22:31.412353 == TX Byte 1 ==
6744 00:22:31.418985 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6745 00:22:31.422178 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6746 00:22:31.422255 ==
6747 00:22:31.425524 Dram Type= 6, Freq= 0, CH_1, rank 0
6748 00:22:31.428544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6749 00:22:31.428653 ==
6750 00:22:31.428731
6751 00:22:31.428787
6752 00:22:31.432324 TX Vref Scan disable
6753 00:22:31.435053 == TX Byte 0 ==
6754 00:22:31.438544 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6755 00:22:31.441861 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6756 00:22:31.445086 == TX Byte 1 ==
6757 00:22:31.448527 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6758 00:22:31.451876 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6759 00:22:31.451953
6760 00:22:31.452012 [DATLAT]
6761 00:22:31.455166 Freq=400, CH1 RK0
6762 00:22:31.455242
6763 00:22:31.455302 DATLAT Default: 0xf
6764 00:22:31.458412 0, 0xFFFF, sum = 0
6765 00:22:31.458491 1, 0xFFFF, sum = 0
6766 00:22:31.461568 2, 0xFFFF, sum = 0
6767 00:22:31.465451 3, 0xFFFF, sum = 0
6768 00:22:31.465562 4, 0xFFFF, sum = 0
6769 00:22:31.468338 5, 0xFFFF, sum = 0
6770 00:22:31.468416 6, 0xFFFF, sum = 0
6771 00:22:31.471659 7, 0xFFFF, sum = 0
6772 00:22:31.471737 8, 0xFFFF, sum = 0
6773 00:22:31.474962 9, 0xFFFF, sum = 0
6774 00:22:31.475039 10, 0xFFFF, sum = 0
6775 00:22:31.478213 11, 0xFFFF, sum = 0
6776 00:22:31.478291 12, 0xFFFF, sum = 0
6777 00:22:31.481947 13, 0x0, sum = 1
6778 00:22:31.482066 14, 0x0, sum = 2
6779 00:22:31.485041 15, 0x0, sum = 3
6780 00:22:31.485156 16, 0x0, sum = 4
6781 00:22:31.488266 best_step = 14
6782 00:22:31.488377
6783 00:22:31.488476 ==
6784 00:22:31.491375 Dram Type= 6, Freq= 0, CH_1, rank 0
6785 00:22:31.494585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6786 00:22:31.494690 ==
6787 00:22:31.498031 RX Vref Scan: 1
6788 00:22:31.498136
6789 00:22:31.498235 RX Vref 0 -> 0, step: 1
6790 00:22:31.498330
6791 00:22:31.501186 RX Delay -375 -> 252, step: 8
6792 00:22:31.501294
6793 00:22:31.504589 Set Vref, RX VrefLevel [Byte0]: 55
6794 00:22:31.508051 [Byte1]: 49
6795 00:22:31.512266
6796 00:22:31.512376 Final RX Vref Byte 0 = 55 to rank0
6797 00:22:31.515748 Final RX Vref Byte 1 = 49 to rank0
6798 00:22:31.519091 Final RX Vref Byte 0 = 55 to rank1
6799 00:22:31.522640 Final RX Vref Byte 1 = 49 to rank1==
6800 00:22:31.525904 Dram Type= 6, Freq= 0, CH_1, rank 0
6801 00:22:31.532281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6802 00:22:31.532357 ==
6803 00:22:31.532417 DQS Delay:
6804 00:22:31.535663 DQS0 = 52, DQS1 = 64
6805 00:22:31.535741 DQM Delay:
6806 00:22:31.535801 DQM0 = 9, DQM1 = 10
6807 00:22:31.538772 DQ Delay:
6808 00:22:31.542462 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6809 00:22:31.542539 DQ4 =8, DQ5 =16, DQ6 =20, DQ7 =4
6810 00:22:31.545670 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6811 00:22:31.548949 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
6812 00:22:31.549068
6813 00:22:31.549128
6814 00:22:31.558952 [DQSOSCAuto] RK0, (LSB)MR18= 0x6376, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 397 ps
6815 00:22:31.562252 CH1 RK0: MR19=C0C, MR18=6376
6816 00:22:31.568972 CH1_RK0: MR19=0xC0C, MR18=0x6376, DQSOSC=394, MR23=63, INC=380, DEC=253
6817 00:22:31.569071 ==
6818 00:22:31.571772 Dram Type= 6, Freq= 0, CH_1, rank 1
6819 00:22:31.575289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6820 00:22:31.575366 ==
6821 00:22:31.578645 [Gating] SW mode calibration
6822 00:22:31.585182 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6823 00:22:31.591650 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6824 00:22:31.595018 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6825 00:22:31.598445 0 11 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
6826 00:22:31.601698 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6827 00:22:31.608509 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6828 00:22:31.611896 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6829 00:22:31.615151 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6830 00:22:31.622059 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6831 00:22:31.625434 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6832 00:22:31.628159 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6833 00:22:31.631591 Total UI for P1: 0, mck2ui 16
6834 00:22:31.635044 best dqsien dly found for B0: ( 0, 14, 24)
6835 00:22:31.638455 Total UI for P1: 0, mck2ui 16
6836 00:22:31.641826 best dqsien dly found for B1: ( 0, 14, 24)
6837 00:22:31.645119 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6838 00:22:31.652026 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6839 00:22:31.652137
6840 00:22:31.654983 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6841 00:22:31.658552 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6842 00:22:31.661510 [Gating] SW calibration Done
6843 00:22:31.661621 ==
6844 00:22:31.664896 Dram Type= 6, Freq= 0, CH_1, rank 1
6845 00:22:31.668271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6846 00:22:31.668376 ==
6847 00:22:31.671506 RX Vref Scan: 0
6848 00:22:31.671612
6849 00:22:31.671711 RX Vref 0 -> 0, step: 1
6850 00:22:31.671809
6851 00:22:31.674679 RX Delay -410 -> 252, step: 16
6852 00:22:31.678185 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6853 00:22:31.684896 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6854 00:22:31.687832 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6855 00:22:31.691210 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6856 00:22:31.694510 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6857 00:22:31.701464 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6858 00:22:31.704803 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6859 00:22:31.708172 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6860 00:22:31.711305 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6861 00:22:31.718175 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6862 00:22:31.721206 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6863 00:22:31.724509 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6864 00:22:31.727837 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6865 00:22:31.734635 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6866 00:22:31.737572 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6867 00:22:31.740963 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6868 00:22:31.741073 ==
6869 00:22:31.744501 Dram Type= 6, Freq= 0, CH_1, rank 1
6870 00:22:31.751317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6871 00:22:31.751418 ==
6872 00:22:31.751510 DQS Delay:
6873 00:22:31.754394 DQS0 = 59, DQS1 = 59
6874 00:22:31.754471 DQM Delay:
6875 00:22:31.754532 DQM0 = 19, DQM1 = 13
6876 00:22:31.757739 DQ Delay:
6877 00:22:31.761109 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6878 00:22:31.764219 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6879 00:22:31.767652 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6880 00:22:31.770793 DQ12 =16, DQ13 =24, DQ14 =16, DQ15 =16
6881 00:22:31.770905
6882 00:22:31.770995
6883 00:22:31.771058 ==
6884 00:22:31.774357 Dram Type= 6, Freq= 0, CH_1, rank 1
6885 00:22:31.777716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6886 00:22:31.777793 ==
6887 00:22:31.777876
6888 00:22:31.777975
6889 00:22:31.780947 TX Vref Scan disable
6890 00:22:31.781023 == TX Byte 0 ==
6891 00:22:31.787571 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6892 00:22:31.790675 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6893 00:22:31.790789 == TX Byte 1 ==
6894 00:22:31.794121 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6895 00:22:31.800770 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6896 00:22:31.800869 ==
6897 00:22:31.804236 Dram Type= 6, Freq= 0, CH_1, rank 1
6898 00:22:31.807459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6899 00:22:31.807578 ==
6900 00:22:31.807685
6901 00:22:31.807788
6902 00:22:31.810788 TX Vref Scan disable
6903 00:22:31.810903 == TX Byte 0 ==
6904 00:22:31.817426 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6905 00:22:31.820730 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6906 00:22:31.820842 == TX Byte 1 ==
6907 00:22:31.827124 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6908 00:22:31.830733 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6909 00:22:31.830845
6910 00:22:31.830951 [DATLAT]
6911 00:22:31.834081 Freq=400, CH1 RK1
6912 00:22:31.834191
6913 00:22:31.834293 DATLAT Default: 0xe
6914 00:22:31.836938 0, 0xFFFF, sum = 0
6915 00:22:31.837057 1, 0xFFFF, sum = 0
6916 00:22:31.840392 2, 0xFFFF, sum = 0
6917 00:22:31.840505 3, 0xFFFF, sum = 0
6918 00:22:31.843757 4, 0xFFFF, sum = 0
6919 00:22:31.843872 5, 0xFFFF, sum = 0
6920 00:22:31.847224 6, 0xFFFF, sum = 0
6921 00:22:31.847338 7, 0xFFFF, sum = 0
6922 00:22:31.850712 8, 0xFFFF, sum = 0
6923 00:22:31.850824 9, 0xFFFF, sum = 0
6924 00:22:31.854111 10, 0xFFFF, sum = 0
6925 00:22:31.854229 11, 0xFFFF, sum = 0
6926 00:22:31.856929 12, 0xFFFF, sum = 0
6927 00:22:31.857049 13, 0x0, sum = 1
6928 00:22:31.860357 14, 0x0, sum = 2
6929 00:22:31.860470 15, 0x0, sum = 3
6930 00:22:31.863748 16, 0x0, sum = 4
6931 00:22:31.863862 best_step = 14
6932 00:22:31.863967
6933 00:22:31.864068 ==
6934 00:22:31.867169 Dram Type= 6, Freq= 0, CH_1, rank 1
6935 00:22:31.874025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6936 00:22:31.874130 ==
6937 00:22:31.874218 RX Vref Scan: 0
6938 00:22:31.874302
6939 00:22:31.877036 RX Vref 0 -> 0, step: 1
6940 00:22:31.877126
6941 00:22:31.880442 RX Delay -359 -> 252, step: 8
6942 00:22:31.887518 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6943 00:22:31.890724 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
6944 00:22:31.893811 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
6945 00:22:31.897291 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6946 00:22:31.903637 iDelay=217, Bit 4, Center -48 (-303 ~ 208) 512
6947 00:22:31.907137 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
6948 00:22:31.910345 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6949 00:22:31.913579 iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504
6950 00:22:31.920379 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
6951 00:22:31.923698 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
6952 00:22:31.927185 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
6953 00:22:31.930488 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6954 00:22:31.936806 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6955 00:22:31.940076 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6956 00:22:31.943305 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
6957 00:22:31.950106 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
6958 00:22:31.950211 ==
6959 00:22:31.953626 Dram Type= 6, Freq= 0, CH_1, rank 1
6960 00:22:31.956899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6961 00:22:31.956998 ==
6962 00:22:31.957083 DQS Delay:
6963 00:22:31.959851 DQS0 = 60, DQS1 = 64
6964 00:22:31.959951 DQM Delay:
6965 00:22:31.963230 DQM0 = 12, DQM1 = 10
6966 00:22:31.963311 DQ Delay:
6967 00:22:31.966513 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6968 00:22:31.970075 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6969 00:22:31.973401 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6970 00:22:31.976825 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6971 00:22:31.976897
6972 00:22:31.976954
6973 00:22:31.983365 [DQSOSCAuto] RK1, (LSB)MR18= 0x7dac, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 394 ps
6974 00:22:31.986562 CH1 RK1: MR19=C0C, MR18=7DAC
6975 00:22:31.992874 CH1_RK1: MR19=0xC0C, MR18=0x7DAC, DQSOSC=388, MR23=63, INC=392, DEC=261
6976 00:22:31.996496 [RxdqsGatingPostProcess] freq 400
6977 00:22:32.003099 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6978 00:22:32.006529 best DQS0 dly(2T, 0.5T) = (0, 10)
6979 00:22:32.006634 best DQS1 dly(2T, 0.5T) = (0, 10)
6980 00:22:32.009755 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6981 00:22:32.013012 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6982 00:22:32.016212 best DQS0 dly(2T, 0.5T) = (0, 10)
6983 00:22:32.019361 best DQS1 dly(2T, 0.5T) = (0, 10)
6984 00:22:32.022726 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6985 00:22:32.026060 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6986 00:22:32.029448 Pre-setting of DQS Precalculation
6987 00:22:32.036194 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6988 00:22:32.042925 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6989 00:22:32.049234 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6990 00:22:32.049332
6991 00:22:32.049421
6992 00:22:32.052748 [Calibration Summary] 800 Mbps
6993 00:22:32.052819 CH 0, Rank 0
6994 00:22:32.056221 SW Impedance : PASS
6995 00:22:32.059607 DUTY Scan : NO K
6996 00:22:32.059704 ZQ Calibration : PASS
6997 00:22:32.062495 Jitter Meter : NO K
6998 00:22:32.065871 CBT Training : PASS
6999 00:22:32.065970 Write leveling : PASS
7000 00:22:32.069290 RX DQS gating : PASS
7001 00:22:32.069362 RX DQ/DQS(RDDQC) : PASS
7002 00:22:32.072783 TX DQ/DQS : PASS
7003 00:22:32.076241 RX DATLAT : PASS
7004 00:22:32.076315 RX DQ/DQS(Engine): PASS
7005 00:22:32.079056 TX OE : NO K
7006 00:22:32.079145 All Pass.
7007 00:22:32.079231
7008 00:22:32.082574 CH 0, Rank 1
7009 00:22:32.082641 SW Impedance : PASS
7010 00:22:32.086009 DUTY Scan : NO K
7011 00:22:32.089330 ZQ Calibration : PASS
7012 00:22:32.089404 Jitter Meter : NO K
7013 00:22:32.092493 CBT Training : PASS
7014 00:22:32.096110 Write leveling : NO K
7015 00:22:32.096215 RX DQS gating : PASS
7016 00:22:32.099393 RX DQ/DQS(RDDQC) : PASS
7017 00:22:32.102502 TX DQ/DQS : PASS
7018 00:22:32.102613 RX DATLAT : PASS
7019 00:22:32.105933 RX DQ/DQS(Engine): PASS
7020 00:22:32.109330 TX OE : NO K
7021 00:22:32.109409 All Pass.
7022 00:22:32.109470
7023 00:22:32.109528 CH 1, Rank 0
7024 00:22:32.112553 SW Impedance : PASS
7025 00:22:32.115630 DUTY Scan : NO K
7026 00:22:32.115722 ZQ Calibration : PASS
7027 00:22:32.119086 Jitter Meter : NO K
7028 00:22:32.122428 CBT Training : PASS
7029 00:22:32.122501 Write leveling : PASS
7030 00:22:32.125422 RX DQS gating : PASS
7031 00:22:32.125502 RX DQ/DQS(RDDQC) : PASS
7032 00:22:32.129005 TX DQ/DQS : PASS
7033 00:22:32.132029 RX DATLAT : PASS
7034 00:22:32.132103 RX DQ/DQS(Engine): PASS
7035 00:22:32.135520 TX OE : NO K
7036 00:22:32.135633 All Pass.
7037 00:22:32.135736
7038 00:22:32.138965 CH 1, Rank 1
7039 00:22:32.139076 SW Impedance : PASS
7040 00:22:32.142161 DUTY Scan : NO K
7041 00:22:32.144981 ZQ Calibration : PASS
7042 00:22:32.145092 Jitter Meter : NO K
7043 00:22:32.148447 CBT Training : PASS
7044 00:22:32.151742 Write leveling : NO K
7045 00:22:32.151839 RX DQS gating : PASS
7046 00:22:32.155429 RX DQ/DQS(RDDQC) : PASS
7047 00:22:32.158668 TX DQ/DQS : PASS
7048 00:22:32.158773 RX DATLAT : PASS
7049 00:22:32.162136 RX DQ/DQS(Engine): PASS
7050 00:22:32.165038 TX OE : NO K
7051 00:22:32.165137 All Pass.
7052 00:22:32.165229
7053 00:22:32.168388 DramC Write-DBI off
7054 00:22:32.168505 PER_BANK_REFRESH: Hybrid Mode
7055 00:22:32.171821 TX_TRACKING: ON
7056 00:22:32.178587 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7057 00:22:32.184821 [FAST_K] Save calibration result to emmc
7058 00:22:32.188216 dramc_set_vcore_voltage set vcore to 725000
7059 00:22:32.188331 Read voltage for 1600, 0
7060 00:22:32.191607 Vio18 = 0
7061 00:22:32.191705 Vcore = 725000
7062 00:22:32.191767 Vdram = 0
7063 00:22:32.195067 Vddq = 0
7064 00:22:32.195161 Vmddr = 0
7065 00:22:32.198217 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7066 00:22:32.204930 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7067 00:22:32.208346 MEM_TYPE=3, freq_sel=13
7068 00:22:32.211707 sv_algorithm_assistance_LP4_3733
7069 00:22:32.214968 ============ PULL DRAM RESETB DOWN ============
7070 00:22:32.217840 ========== PULL DRAM RESETB DOWN end =========
7071 00:22:32.224839 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7072 00:22:32.228001 ===================================
7073 00:22:32.228121 LPDDR4 DRAM CONFIGURATION
7074 00:22:32.231146 ===================================
7075 00:22:32.234299 EX_ROW_EN[0] = 0x0
7076 00:22:32.234396 EX_ROW_EN[1] = 0x0
7077 00:22:32.237980 LP4Y_EN = 0x0
7078 00:22:32.241137 WORK_FSP = 0x1
7079 00:22:32.241233 WL = 0x5
7080 00:22:32.244566 RL = 0x5
7081 00:22:32.244663 BL = 0x2
7082 00:22:32.247898 RPST = 0x0
7083 00:22:32.247993 RD_PRE = 0x0
7084 00:22:32.251381 WR_PRE = 0x1
7085 00:22:32.251484 WR_PST = 0x1
7086 00:22:32.254221 DBI_WR = 0x0
7087 00:22:32.254315 DBI_RD = 0x0
7088 00:22:32.257604 OTF = 0x1
7089 00:22:32.261082 ===================================
7090 00:22:32.264300 ===================================
7091 00:22:32.264403 ANA top config
7092 00:22:32.267527 ===================================
7093 00:22:32.270905 DLL_ASYNC_EN = 0
7094 00:22:32.274367 ALL_SLAVE_EN = 0
7095 00:22:32.274463 NEW_RANK_MODE = 1
7096 00:22:32.277163 DLL_IDLE_MODE = 1
7097 00:22:32.280560 LP45_APHY_COMB_EN = 1
7098 00:22:32.284016 TX_ODT_DIS = 0
7099 00:22:32.287475 NEW_8X_MODE = 1
7100 00:22:32.290905 ===================================
7101 00:22:32.294305 ===================================
7102 00:22:32.294399 data_rate = 3200
7103 00:22:32.297121 CKR = 1
7104 00:22:32.300553 DQ_P2S_RATIO = 8
7105 00:22:32.303708 ===================================
7106 00:22:32.307110 CA_P2S_RATIO = 8
7107 00:22:32.310531 DQ_CA_OPEN = 0
7108 00:22:32.313969 DQ_SEMI_OPEN = 0
7109 00:22:32.317000 CA_SEMI_OPEN = 0
7110 00:22:32.317093 CA_FULL_RATE = 0
7111 00:22:32.320356 DQ_CKDIV4_EN = 0
7112 00:22:32.323682 CA_CKDIV4_EN = 0
7113 00:22:32.326931 CA_PREDIV_EN = 0
7114 00:22:32.330463 PH8_DLY = 12
7115 00:22:32.333325 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7116 00:22:32.333414 DQ_AAMCK_DIV = 4
7117 00:22:32.337016 CA_AAMCK_DIV = 4
7118 00:22:32.339986 CA_ADMCK_DIV = 4
7119 00:22:32.343734 DQ_TRACK_CA_EN = 0
7120 00:22:32.346509 CA_PICK = 1600
7121 00:22:32.349944 CA_MCKIO = 1600
7122 00:22:32.353211 MCKIO_SEMI = 0
7123 00:22:32.353327 PLL_FREQ = 3068
7124 00:22:32.356937 DQ_UI_PI_RATIO = 32
7125 00:22:32.359912 CA_UI_PI_RATIO = 0
7126 00:22:32.363616 ===================================
7127 00:22:32.367015 ===================================
7128 00:22:32.370217 memory_type:LPDDR4
7129 00:22:32.370337 GP_NUM : 10
7130 00:22:32.373344 SRAM_EN : 1
7131 00:22:32.376512 MD32_EN : 0
7132 00:22:32.379380 ===================================
7133 00:22:32.379454 [ANA_INIT] >>>>>>>>>>>>>>
7134 00:22:32.382751 <<<<<< [CONFIGURE PHASE]: ANA_TX
7135 00:22:32.386215 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7136 00:22:32.389648 ===================================
7137 00:22:32.393021 data_rate = 3200,PCW = 0X7600
7138 00:22:32.396424 ===================================
7139 00:22:32.399320 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7140 00:22:32.405983 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7141 00:22:32.412670 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7142 00:22:32.416141 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7143 00:22:32.419483 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7144 00:22:32.422871 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7145 00:22:32.426304 [ANA_INIT] flow start
7146 00:22:32.426397 [ANA_INIT] PLL >>>>>>>>
7147 00:22:32.429102 [ANA_INIT] PLL <<<<<<<<
7148 00:22:32.432482 [ANA_INIT] MIDPI >>>>>>>>
7149 00:22:32.432580 [ANA_INIT] MIDPI <<<<<<<<
7150 00:22:32.435891 [ANA_INIT] DLL >>>>>>>>
7151 00:22:32.439214 [ANA_INIT] DLL <<<<<<<<
7152 00:22:32.439304 [ANA_INIT] flow end
7153 00:22:32.446210 ============ LP4 DIFF to SE enter ============
7154 00:22:32.449534 ============ LP4 DIFF to SE exit ============
7155 00:22:32.452625 [ANA_INIT] <<<<<<<<<<<<<
7156 00:22:32.455852 [Flow] Enable top DCM control >>>>>
7157 00:22:32.459345 [Flow] Enable top DCM control <<<<<
7158 00:22:32.459446 Enable DLL master slave shuffle
7159 00:22:32.465564 ==============================================================
7160 00:22:32.469392 Gating Mode config
7161 00:22:32.472492 ==============================================================
7162 00:22:32.475503 Config description:
7163 00:22:32.485435 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7164 00:22:32.492278 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7165 00:22:32.495703 SELPH_MODE 0: By rank 1: By Phase
7166 00:22:32.501993 ==============================================================
7167 00:22:32.505343 GAT_TRACK_EN = 1
7168 00:22:32.508731 RX_GATING_MODE = 2
7169 00:22:32.512029 RX_GATING_TRACK_MODE = 2
7170 00:22:32.515374 SELPH_MODE = 1
7171 00:22:32.515477 PICG_EARLY_EN = 1
7172 00:22:32.518978 VALID_LAT_VALUE = 1
7173 00:22:32.525177 ==============================================================
7174 00:22:32.528578 Enter into Gating configuration >>>>
7175 00:22:32.531889 Exit from Gating configuration <<<<
7176 00:22:32.535309 Enter into DVFS_PRE_config >>>>>
7177 00:22:32.545619 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7178 00:22:32.548570 Exit from DVFS_PRE_config <<<<<
7179 00:22:32.551915 Enter into PICG configuration >>>>
7180 00:22:32.555231 Exit from PICG configuration <<<<
7181 00:22:32.558942 [RX_INPUT] configuration >>>>>
7182 00:22:32.562100 [RX_INPUT] configuration <<<<<
7183 00:22:32.565317 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7184 00:22:32.571977 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7185 00:22:32.578416 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7186 00:22:32.585278 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7187 00:22:32.591961 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7188 00:22:32.598421 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7189 00:22:32.601782 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7190 00:22:32.604939 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7191 00:22:32.608364 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7192 00:22:32.611548 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7193 00:22:32.618075 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7194 00:22:32.621531 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7195 00:22:32.624995 ===================================
7196 00:22:32.628509 LPDDR4 DRAM CONFIGURATION
7197 00:22:32.631400 ===================================
7198 00:22:32.631517 EX_ROW_EN[0] = 0x0
7199 00:22:32.634774 EX_ROW_EN[1] = 0x0
7200 00:22:32.634873 LP4Y_EN = 0x0
7201 00:22:32.638202 WORK_FSP = 0x1
7202 00:22:32.638296 WL = 0x5
7203 00:22:32.641643 RL = 0x5
7204 00:22:32.641756 BL = 0x2
7205 00:22:32.644929 RPST = 0x0
7206 00:22:32.648375 RD_PRE = 0x0
7207 00:22:32.648473 WR_PRE = 0x1
7208 00:22:32.651202 WR_PST = 0x1
7209 00:22:32.651294 DBI_WR = 0x0
7210 00:22:32.654667 DBI_RD = 0x0
7211 00:22:32.654747 OTF = 0x1
7212 00:22:32.658100 ===================================
7213 00:22:32.661552 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7214 00:22:32.668120 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7215 00:22:32.671451 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7216 00:22:32.674286 ===================================
7217 00:22:32.678141 LPDDR4 DRAM CONFIGURATION
7218 00:22:32.681238 ===================================
7219 00:22:32.681317 EX_ROW_EN[0] = 0x10
7220 00:22:32.684685 EX_ROW_EN[1] = 0x0
7221 00:22:32.684800 LP4Y_EN = 0x0
7222 00:22:32.687699 WORK_FSP = 0x1
7223 00:22:32.687812 WL = 0x5
7224 00:22:32.690897 RL = 0x5
7225 00:22:32.691015 BL = 0x2
7226 00:22:32.694387 RPST = 0x0
7227 00:22:32.694502 RD_PRE = 0x0
7228 00:22:32.697670 WR_PRE = 0x1
7229 00:22:32.700948 WR_PST = 0x1
7230 00:22:32.701062 DBI_WR = 0x0
7231 00:22:32.704317 DBI_RD = 0x0
7232 00:22:32.704455 OTF = 0x1
7233 00:22:32.707567 ===================================
7234 00:22:32.714317 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7235 00:22:32.714433 ==
7236 00:22:32.717541 Dram Type= 6, Freq= 0, CH_0, rank 0
7237 00:22:32.721061 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7238 00:22:32.721174 ==
7239 00:22:32.724285 [Duty_Offset_Calibration]
7240 00:22:32.727641 B0:2 B1:0 CA:3
7241 00:22:32.727754
7242 00:22:32.730718 [DutyScan_Calibration_Flow] k_type=0
7243 00:22:32.739051
7244 00:22:32.739165 ==CLK 0==
7245 00:22:32.742455 Final CLK duty delay cell = 0
7246 00:22:32.745898 [0] MAX Duty = 5031%(X100), DQS PI = 12
7247 00:22:32.749254 [0] MIN Duty = 4907%(X100), DQS PI = 4
7248 00:22:32.749365 [0] AVG Duty = 4969%(X100)
7249 00:22:32.752652
7250 00:22:32.752761 CH0 CLK Duty spec in!! Max-Min= 124%
7251 00:22:32.759376 [DutyScan_Calibration_Flow] ====Done====
7252 00:22:32.759473
7253 00:22:32.762291 [DutyScan_Calibration_Flow] k_type=1
7254 00:22:32.778887
7255 00:22:32.778965 ==DQS 0 ==
7256 00:22:32.782287 Final DQS duty delay cell = 0
7257 00:22:32.785674 [0] MAX Duty = 5094%(X100), DQS PI = 14
7258 00:22:32.789003 [0] MIN Duty = 4875%(X100), DQS PI = 48
7259 00:22:32.792196 [0] AVG Duty = 4984%(X100)
7260 00:22:32.792297
7261 00:22:32.792384 ==DQS 1 ==
7262 00:22:32.795358 Final DQS duty delay cell = 0
7263 00:22:32.799065 [0] MAX Duty = 5156%(X100), DQS PI = 32
7264 00:22:32.802217 [0] MIN Duty = 5062%(X100), DQS PI = 0
7265 00:22:32.805802 [0] AVG Duty = 5109%(X100)
7266 00:22:32.805880
7267 00:22:32.808769 CH0 DQS 0 Duty spec in!! Max-Min= 219%
7268 00:22:32.808847
7269 00:22:32.812028 CH0 DQS 1 Duty spec in!! Max-Min= 94%
7270 00:22:32.815422 [DutyScan_Calibration_Flow] ====Done====
7271 00:22:32.815500
7272 00:22:32.818724 [DutyScan_Calibration_Flow] k_type=3
7273 00:22:32.836668
7274 00:22:32.836749 ==DQM 0 ==
7275 00:22:32.840021 Final DQM duty delay cell = 0
7276 00:22:32.843686 [0] MAX Duty = 5187%(X100), DQS PI = 30
7277 00:22:32.846632 [0] MIN Duty = 4844%(X100), DQS PI = 50
7278 00:22:32.849937 [0] AVG Duty = 5015%(X100)
7279 00:22:32.850008
7280 00:22:32.850067 ==DQM 1 ==
7281 00:22:32.853348 Final DQM duty delay cell = 4
7282 00:22:32.856693 [4] MAX Duty = 5187%(X100), DQS PI = 60
7283 00:22:32.859996 [4] MIN Duty = 5000%(X100), DQS PI = 14
7284 00:22:32.863503 [4] AVG Duty = 5093%(X100)
7285 00:22:32.863580
7286 00:22:32.866911 CH0 DQM 0 Duty spec in!! Max-Min= 343%
7287 00:22:32.867003
7288 00:22:32.870292 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7289 00:22:32.873590 [DutyScan_Calibration_Flow] ====Done====
7290 00:22:32.873668
7291 00:22:32.876442 [DutyScan_Calibration_Flow] k_type=2
7292 00:22:32.893571
7293 00:22:32.893720 ==DQ 0 ==
7294 00:22:32.896446 Final DQ duty delay cell = -4
7295 00:22:32.900063 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7296 00:22:32.903242 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7297 00:22:32.906572 [-4] AVG Duty = 4938%(X100)
7298 00:22:32.906697
7299 00:22:32.906811 ==DQ 1 ==
7300 00:22:32.909909 Final DQ duty delay cell = 0
7301 00:22:32.913417 [0] MAX Duty = 5156%(X100), DQS PI = 58
7302 00:22:32.916513 [0] MIN Duty = 5000%(X100), DQS PI = 16
7303 00:22:32.920070 [0] AVG Duty = 5078%(X100)
7304 00:22:32.920175
7305 00:22:32.923082 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7306 00:22:32.923235
7307 00:22:32.926542 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7308 00:22:32.929934 [DutyScan_Calibration_Flow] ====Done====
7309 00:22:32.930046 ==
7310 00:22:32.933132 Dram Type= 6, Freq= 0, CH_1, rank 0
7311 00:22:32.936196 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7312 00:22:32.936322 ==
7313 00:22:32.939646 [Duty_Offset_Calibration]
7314 00:22:32.939784 B0:1 B1:-2 CA:0
7315 00:22:32.939880
7316 00:22:32.943052 [DutyScan_Calibration_Flow] k_type=0
7317 00:22:32.953987
7318 00:22:32.954087 ==CLK 0==
7319 00:22:32.957394 Final CLK duty delay cell = 0
7320 00:22:32.960753 [0] MAX Duty = 5062%(X100), DQS PI = 20
7321 00:22:32.963915 [0] MIN Duty = 4844%(X100), DQS PI = 0
7322 00:22:32.963993 [0] AVG Duty = 4953%(X100)
7323 00:22:32.967357
7324 00:22:32.970156 CH1 CLK Duty spec in!! Max-Min= 218%
7325 00:22:32.973542 [DutyScan_Calibration_Flow] ====Done====
7326 00:22:32.973620
7327 00:22:32.976747 [DutyScan_Calibration_Flow] k_type=1
7328 00:22:32.993701
7329 00:22:32.993810 ==DQS 0 ==
7330 00:22:32.996605 Final DQS duty delay cell = 0
7331 00:22:33.000142 [0] MAX Duty = 5187%(X100), DQS PI = 24
7332 00:22:33.003559 [0] MIN Duty = 5031%(X100), DQS PI = 54
7333 00:22:33.006657 [0] AVG Duty = 5109%(X100)
7334 00:22:33.006750
7335 00:22:33.006835 ==DQS 1 ==
7336 00:22:33.010366 Final DQS duty delay cell = 0
7337 00:22:33.013731 [0] MAX Duty = 5093%(X100), DQS PI = 60
7338 00:22:33.017149 [0] MIN Duty = 4844%(X100), DQS PI = 26
7339 00:22:33.019913 [0] AVG Duty = 4968%(X100)
7340 00:22:33.020013
7341 00:22:33.023233 CH1 DQS 0 Duty spec in!! Max-Min= 156%
7342 00:22:33.023299
7343 00:22:33.026548 CH1 DQS 1 Duty spec in!! Max-Min= 249%
7344 00:22:33.030249 [DutyScan_Calibration_Flow] ====Done====
7345 00:22:33.030342
7346 00:22:33.033435 [DutyScan_Calibration_Flow] k_type=3
7347 00:22:33.050592
7348 00:22:33.050688 ==DQM 0 ==
7349 00:22:33.054048 Final DQM duty delay cell = 0
7350 00:22:33.057274 [0] MAX Duty = 5031%(X100), DQS PI = 26
7351 00:22:33.060447 [0] MIN Duty = 4813%(X100), DQS PI = 54
7352 00:22:33.063553 [0] AVG Duty = 4922%(X100)
7353 00:22:33.063647
7354 00:22:33.063733 ==DQM 1 ==
7355 00:22:33.067229 Final DQM duty delay cell = 0
7356 00:22:33.070570 [0] MAX Duty = 5062%(X100), DQS PI = 34
7357 00:22:33.073798 [0] MIN Duty = 4875%(X100), DQS PI = 24
7358 00:22:33.077227 [0] AVG Duty = 4968%(X100)
7359 00:22:33.077320
7360 00:22:33.080048 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7361 00:22:33.080120
7362 00:22:33.083389 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7363 00:22:33.086745 [DutyScan_Calibration_Flow] ====Done====
7364 00:22:33.086816
7365 00:22:33.090209 [DutyScan_Calibration_Flow] k_type=2
7366 00:22:33.107609
7367 00:22:33.107682 ==DQ 0 ==
7368 00:22:33.110974 Final DQ duty delay cell = 0
7369 00:22:33.114152 [0] MAX Duty = 5093%(X100), DQS PI = 20
7370 00:22:33.117326 [0] MIN Duty = 4907%(X100), DQS PI = 48
7371 00:22:33.117405 [0] AVG Duty = 5000%(X100)
7372 00:22:33.121116
7373 00:22:33.121195 ==DQ 1 ==
7374 00:22:33.123948 Final DQ duty delay cell = 0
7375 00:22:33.127246 [0] MAX Duty = 5156%(X100), DQS PI = 34
7376 00:22:33.130684 [0] MIN Duty = 4969%(X100), DQS PI = 24
7377 00:22:33.130763 [0] AVG Duty = 5062%(X100)
7378 00:22:33.130824
7379 00:22:33.133993 CH1 DQ 0 Duty spec in!! Max-Min= 186%
7380 00:22:33.137418
7381 00:22:33.140654 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7382 00:22:33.143792 [DutyScan_Calibration_Flow] ====Done====
7383 00:22:33.147379 nWR fixed to 30
7384 00:22:33.147478 [ModeRegInit_LP4] CH0 RK0
7385 00:22:33.150729 [ModeRegInit_LP4] CH0 RK1
7386 00:22:33.154026 [ModeRegInit_LP4] CH1 RK0
7387 00:22:33.157353 [ModeRegInit_LP4] CH1 RK1
7388 00:22:33.157432 match AC timing 5
7389 00:22:33.160445 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7390 00:22:33.167004 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7391 00:22:33.170695 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7392 00:22:33.177085 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7393 00:22:33.180338 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7394 00:22:33.180416 [MiockJmeterHQA]
7395 00:22:33.180477
7396 00:22:33.183759 [DramcMiockJmeter] u1RxGatingPI = 0
7397 00:22:33.187002 0 : 4257, 4029
7398 00:22:33.187123 4 : 4363, 4138
7399 00:22:33.187233 8 : 4252, 4027
7400 00:22:33.190396 12 : 4252, 4027
7401 00:22:33.190516 16 : 4253, 4027
7402 00:22:33.193851 20 : 4253, 4026
7403 00:22:33.193964 24 : 4255, 4030
7404 00:22:33.197388 28 : 4253, 4027
7405 00:22:33.197501 32 : 4252, 4027
7406 00:22:33.200257 36 : 4365, 4140
7407 00:22:33.200366 40 : 4253, 4026
7408 00:22:33.200468 44 : 4255, 4029
7409 00:22:33.203710 48 : 4252, 4027
7410 00:22:33.203824 52 : 4363, 4137
7411 00:22:33.207208 56 : 4253, 4027
7412 00:22:33.207320 60 : 4361, 4138
7413 00:22:33.210654 64 : 4250, 4027
7414 00:22:33.210771 68 : 4250, 4027
7415 00:22:33.213538 72 : 4250, 4027
7416 00:22:33.213653 76 : 4252, 4029
7417 00:22:33.213756 80 : 4361, 4138
7418 00:22:33.216982 84 : 4250, 4027
7419 00:22:33.217096 88 : 4361, 4137
7420 00:22:33.220425 92 : 4250, 4026
7421 00:22:33.220541 96 : 4250, 4027
7422 00:22:33.223522 100 : 4250, 4027
7423 00:22:33.223637 104 : 4250, 3234
7424 00:22:33.227257 108 : 4252, 0
7425 00:22:33.227375 112 : 4361, 0
7426 00:22:33.227483 116 : 4360, 0
7427 00:22:33.230100 120 : 4250, 0
7428 00:22:33.230211 124 : 4250, 0
7429 00:22:33.230313 128 : 4249, 0
7430 00:22:33.233990 132 : 4250, 0
7431 00:22:33.234105 136 : 4250, 0
7432 00:22:33.236846 140 : 4250, 0
7433 00:22:33.236962 144 : 4252, 0
7434 00:22:33.237071 148 : 4361, 0
7435 00:22:33.240253 152 : 4250, 0
7436 00:22:33.240369 156 : 4250, 0
7437 00:22:33.243587 160 : 4360, 0
7438 00:22:33.243694 164 : 4361, 0
7439 00:22:33.243799 168 : 4363, 0
7440 00:22:33.247076 172 : 4250, 0
7441 00:22:33.247190 176 : 4361, 0
7442 00:22:33.250425 180 : 4251, 0
7443 00:22:33.250535 184 : 4250, 0
7444 00:22:33.250638 188 : 4250, 0
7445 00:22:33.253710 192 : 4250, 0
7446 00:22:33.253825 196 : 4252, 0
7447 00:22:33.253932 200 : 4361, 0
7448 00:22:33.257055 204 : 4250, 0
7449 00:22:33.257172 208 : 4250, 0
7450 00:22:33.260318 212 : 4360, 0
7451 00:22:33.260431 216 : 4361, 0
7452 00:22:33.260537 220 : 4363, 0
7453 00:22:33.263605 224 : 4250, 0
7454 00:22:33.263717 228 : 4250, 0
7455 00:22:33.266978 232 : 4250, 0
7456 00:22:33.267093 236 : 4252, 982
7457 00:22:33.270230 240 : 4250, 4027
7458 00:22:33.270346 244 : 4250, 4027
7459 00:22:33.270450 248 : 4361, 4138
7460 00:22:33.273290 252 : 4250, 4027
7461 00:22:33.273403 256 : 4250, 4027
7462 00:22:33.277136 260 : 4361, 4137
7463 00:22:33.277238 264 : 4361, 4137
7464 00:22:33.280309 268 : 4250, 4027
7465 00:22:33.280405 272 : 4364, 4140
7466 00:22:33.283244 276 : 4360, 4138
7467 00:22:33.283324 280 : 4250, 4027
7468 00:22:33.286684 284 : 4250, 4027
7469 00:22:33.286764 288 : 4252, 4029
7470 00:22:33.289739 292 : 4250, 4027
7471 00:22:33.289858 296 : 4250, 4027
7472 00:22:33.293079 300 : 4250, 4027
7473 00:22:33.293197 304 : 4252, 4029
7474 00:22:33.293301 308 : 4249, 4027
7475 00:22:33.296350 312 : 4361, 4137
7476 00:22:33.296467 316 : 4363, 4140
7477 00:22:33.300026 320 : 4250, 4027
7478 00:22:33.300140 324 : 4363, 4140
7479 00:22:33.303468 328 : 4250, 4027
7480 00:22:33.303581 332 : 4250, 4027
7481 00:22:33.306362 336 : 4252, 4027
7482 00:22:33.306479 340 : 4252, 4029
7483 00:22:33.309793 344 : 4250, 4027
7484 00:22:33.309909 348 : 4250, 4026
7485 00:22:33.313318 352 : 4252, 3986
7486 00:22:33.313433 356 : 4252, 2501
7487 00:22:33.313542 360 : 4250, 0
7488 00:22:33.316632
7489 00:22:33.316753 MIOCK jitter meter ch=0
7490 00:22:33.316854
7491 00:22:33.319496 1T = (360-108) = 252 dly cells
7492 00:22:33.326257 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7493 00:22:33.326370 ==
7494 00:22:33.329676 Dram Type= 6, Freq= 0, CH_0, rank 0
7495 00:22:33.332836 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7496 00:22:33.332949 ==
7497 00:22:33.339152 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7498 00:22:33.342516 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7499 00:22:33.346014 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7500 00:22:33.352802 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7501 00:22:33.362166 [CA 0] Center 43 (13~74) winsize 62
7502 00:22:33.365562 [CA 1] Center 43 (13~74) winsize 62
7503 00:22:33.369015 [CA 2] Center 39 (10~68) winsize 59
7504 00:22:33.372464 [CA 3] Center 39 (10~68) winsize 59
7505 00:22:33.375433 [CA 4] Center 36 (7~66) winsize 60
7506 00:22:33.378757 [CA 5] Center 36 (7~66) winsize 60
7507 00:22:33.378827
7508 00:22:33.382493 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7509 00:22:33.382568
7510 00:22:33.385703 [CATrainingPosCal] consider 1 rank data
7511 00:22:33.388896 u2DelayCellTimex100 = 258/100 ps
7512 00:22:33.395858 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7513 00:22:33.398591 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7514 00:22:33.402082 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7515 00:22:33.405442 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7516 00:22:33.408574 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7517 00:22:33.412224 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7518 00:22:33.412292
7519 00:22:33.415364 CA PerBit enable=1, Macro0, CA PI delay=36
7520 00:22:33.415433
7521 00:22:33.418718 [CBTSetCACLKResult] CA Dly = 36
7522 00:22:33.422125 CS Dly: 11 (0~42)
7523 00:22:33.425516 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7524 00:22:33.428384 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7525 00:22:33.428452 ==
7526 00:22:33.431752 Dram Type= 6, Freq= 0, CH_0, rank 1
7527 00:22:33.438330 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7528 00:22:33.438404 ==
7529 00:22:33.441963 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7530 00:22:33.448254 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7531 00:22:33.451606 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7532 00:22:33.458580 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7533 00:22:33.466398 [CA 0] Center 44 (14~75) winsize 62
7534 00:22:33.469826 [CA 1] Center 43 (13~74) winsize 62
7535 00:22:33.473201 [CA 2] Center 39 (10~69) winsize 60
7536 00:22:33.476062 [CA 3] Center 39 (10~69) winsize 60
7537 00:22:33.479467 [CA 4] Center 37 (8~67) winsize 60
7538 00:22:33.482821 [CA 5] Center 37 (7~67) winsize 61
7539 00:22:33.482894
7540 00:22:33.486025 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7541 00:22:33.486096
7542 00:22:33.492753 [CATrainingPosCal] consider 2 rank data
7543 00:22:33.492855 u2DelayCellTimex100 = 258/100 ps
7544 00:22:33.499535 CA0 delay=44 (14~74),Diff = 8 PI (30 cell)
7545 00:22:33.502915 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7546 00:22:33.506202 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7547 00:22:33.509536 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7548 00:22:33.512531 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7549 00:22:33.516021 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7550 00:22:33.516098
7551 00:22:33.519236 CA PerBit enable=1, Macro0, CA PI delay=36
7552 00:22:33.519304
7553 00:22:33.522591 [CBTSetCACLKResult] CA Dly = 36
7554 00:22:33.525938 CS Dly: 11 (0~43)
7555 00:22:33.529444 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7556 00:22:33.532685 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7557 00:22:33.532789
7558 00:22:33.535732 ----->DramcWriteLeveling(PI) begin...
7559 00:22:33.535803 ==
7560 00:22:33.538998 Dram Type= 6, Freq= 0, CH_0, rank 0
7561 00:22:33.545561 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7562 00:22:33.545638 ==
7563 00:22:33.548904 Write leveling (Byte 0): 36 => 36
7564 00:22:33.552614 Write leveling (Byte 1): 28 => 28
7565 00:22:33.552696 DramcWriteLeveling(PI) end<-----
7566 00:22:33.555751
7567 00:22:33.555818 ==
7568 00:22:33.559040 Dram Type= 6, Freq= 0, CH_0, rank 0
7569 00:22:33.562438 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7570 00:22:33.562512 ==
7571 00:22:33.565452 [Gating] SW mode calibration
7572 00:22:33.572285 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7573 00:22:33.575677 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7574 00:22:33.582482 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7575 00:22:33.585769 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7576 00:22:33.589066 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7577 00:22:33.595276 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7578 00:22:33.598723 1 4 16 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
7579 00:22:33.602000 1 4 20 | B1->B0 | 2423 3434 | 1 1 | (0 0) (1 1)
7580 00:22:33.608946 1 4 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7581 00:22:33.612256 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7582 00:22:33.615599 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7583 00:22:33.622233 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7584 00:22:33.625450 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7585 00:22:33.628532 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7586 00:22:33.635411 1 5 16 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 1)
7587 00:22:33.638767 1 5 20 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
7588 00:22:33.642184 1 5 24 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
7589 00:22:33.648455 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7590 00:22:33.651894 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7591 00:22:33.655073 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7592 00:22:33.661717 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7593 00:22:33.665012 1 6 12 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
7594 00:22:33.668174 1 6 16 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
7595 00:22:33.674915 1 6 20 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
7596 00:22:33.678155 1 6 24 | B1->B0 | 3e3e 4646 | 1 0 | (0 0) (0 0)
7597 00:22:33.681516 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7598 00:22:33.688337 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7599 00:22:33.691177 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7600 00:22:33.694495 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7601 00:22:33.701318 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7602 00:22:33.704536 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7603 00:22:33.707898 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7604 00:22:33.714925 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7605 00:22:33.718393 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7606 00:22:33.721325 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7607 00:22:33.727819 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7608 00:22:33.731586 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7609 00:22:33.734352 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7610 00:22:33.741375 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7611 00:22:33.744594 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7612 00:22:33.748130 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7613 00:22:33.754269 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7614 00:22:33.757614 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7615 00:22:33.760953 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7616 00:22:33.767731 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7617 00:22:33.770843 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7618 00:22:33.774272 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7619 00:22:33.777702 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7620 00:22:33.781032 Total UI for P1: 0, mck2ui 16
7621 00:22:33.784095 best dqsien dly found for B0: ( 1, 9, 14)
7622 00:22:33.790940 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7623 00:22:33.794028 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7624 00:22:33.797669 1 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7625 00:22:33.801072 Total UI for P1: 0, mck2ui 16
7626 00:22:33.803960 best dqsien dly found for B1: ( 1, 9, 26)
7627 00:22:33.807188 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7628 00:22:33.813972 best DQS1 dly(MCK, UI, PI) = (1, 9, 26)
7629 00:22:33.814061
7630 00:22:33.817439 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7631 00:22:33.820967 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 26)
7632 00:22:33.824006 [Gating] SW calibration Done
7633 00:22:33.824085 ==
7634 00:22:33.827358 Dram Type= 6, Freq= 0, CH_0, rank 0
7635 00:22:33.830629 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7636 00:22:33.830701 ==
7637 00:22:33.834018 RX Vref Scan: 0
7638 00:22:33.834090
7639 00:22:33.834156 RX Vref 0 -> 0, step: 1
7640 00:22:33.834217
7641 00:22:33.837409 RX Delay 0 -> 252, step: 8
7642 00:22:33.840612 iDelay=192, Bit 0, Center 127 (72 ~ 183) 112
7643 00:22:33.843756 iDelay=192, Bit 1, Center 131 (80 ~ 183) 104
7644 00:22:33.850499 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7645 00:22:33.853988 iDelay=192, Bit 3, Center 123 (72 ~ 175) 104
7646 00:22:33.857400 iDelay=192, Bit 4, Center 127 (72 ~ 183) 112
7647 00:22:33.860801 iDelay=192, Bit 5, Center 111 (56 ~ 167) 112
7648 00:22:33.864306 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7649 00:22:33.870785 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7650 00:22:33.874076 iDelay=192, Bit 8, Center 115 (56 ~ 175) 120
7651 00:22:33.877240 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7652 00:22:33.880496 iDelay=192, Bit 10, Center 123 (64 ~ 183) 120
7653 00:22:33.884005 iDelay=192, Bit 11, Center 115 (56 ~ 175) 120
7654 00:22:33.890352 iDelay=192, Bit 12, Center 127 (72 ~ 183) 112
7655 00:22:33.893780 iDelay=192, Bit 13, Center 131 (72 ~ 191) 120
7656 00:22:33.897213 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7657 00:22:33.900527 iDelay=192, Bit 15, Center 131 (72 ~ 191) 120
7658 00:22:33.900597 ==
7659 00:22:33.903895 Dram Type= 6, Freq= 0, CH_0, rank 0
7660 00:22:33.910224 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7661 00:22:33.910295 ==
7662 00:22:33.910354 DQS Delay:
7663 00:22:33.913879 DQS0 = 0, DQS1 = 0
7664 00:22:33.913957 DQM Delay:
7665 00:22:33.914019 DQM0 = 128, DQM1 = 123
7666 00:22:33.917139 DQ Delay:
7667 00:22:33.920430 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
7668 00:22:33.923580 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =139
7669 00:22:33.926746 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =115
7670 00:22:33.930591 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
7671 00:22:33.930670
7672 00:22:33.930731
7673 00:22:33.930787 ==
7674 00:22:33.933738 Dram Type= 6, Freq= 0, CH_0, rank 0
7675 00:22:33.937163 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7676 00:22:33.940587 ==
7677 00:22:33.940677
7678 00:22:33.940766
7679 00:22:33.940851 TX Vref Scan disable
7680 00:22:33.943847 == TX Byte 0 ==
7681 00:22:33.947084 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
7682 00:22:33.950263 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7683 00:22:33.953519 == TX Byte 1 ==
7684 00:22:33.956879 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7685 00:22:33.960253 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7686 00:22:33.963508 ==
7687 00:22:33.966945 Dram Type= 6, Freq= 0, CH_0, rank 0
7688 00:22:33.969822 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7689 00:22:33.969902 ==
7690 00:22:33.983013
7691 00:22:33.986497 TX Vref early break, caculate TX vref
7692 00:22:33.989979 TX Vref=16, minBit 8, minWin=21, winSum=363
7693 00:22:33.993343 TX Vref=18, minBit 8, minWin=21, winSum=369
7694 00:22:33.996232 TX Vref=20, minBit 8, minWin=22, winSum=382
7695 00:22:33.999642 TX Vref=22, minBit 8, minWin=23, winSum=388
7696 00:22:34.003194 TX Vref=24, minBit 9, minWin=23, winSum=400
7697 00:22:34.009559 TX Vref=26, minBit 4, minWin=25, winSum=410
7698 00:22:34.012936 TX Vref=28, minBit 8, minWin=24, winSum=410
7699 00:22:34.016332 TX Vref=30, minBit 9, minWin=24, winSum=401
7700 00:22:34.019815 TX Vref=32, minBit 8, minWin=23, winSum=392
7701 00:22:34.022722 TX Vref=34, minBit 9, minWin=22, winSum=387
7702 00:22:34.029803 [TxChooseVref] Worse bit 4, Min win 25, Win sum 410, Final Vref 26
7703 00:22:34.029884
7704 00:22:34.032923 Final TX Range 0 Vref 26
7705 00:22:34.033003
7706 00:22:34.033063 ==
7707 00:22:34.036496 Dram Type= 6, Freq= 0, CH_0, rank 0
7708 00:22:34.039432 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7709 00:22:34.039511 ==
7710 00:22:34.039573
7711 00:22:34.039629
7712 00:22:34.042745 TX Vref Scan disable
7713 00:22:34.049673 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7714 00:22:34.049752 == TX Byte 0 ==
7715 00:22:34.052597 u2DelayCellOfst[0]=15 cells (4 PI)
7716 00:22:34.055879 u2DelayCellOfst[1]=18 cells (5 PI)
7717 00:22:34.059562 u2DelayCellOfst[2]=11 cells (3 PI)
7718 00:22:34.062369 u2DelayCellOfst[3]=11 cells (3 PI)
7719 00:22:34.065637 u2DelayCellOfst[4]=11 cells (3 PI)
7720 00:22:34.069073 u2DelayCellOfst[5]=0 cells (0 PI)
7721 00:22:34.072470 u2DelayCellOfst[6]=18 cells (5 PI)
7722 00:22:34.075941 u2DelayCellOfst[7]=18 cells (5 PI)
7723 00:22:34.079150 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7724 00:22:34.082518 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7725 00:22:34.085853 == TX Byte 1 ==
7726 00:22:34.089285 u2DelayCellOfst[8]=0 cells (0 PI)
7727 00:22:34.089364 u2DelayCellOfst[9]=3 cells (1 PI)
7728 00:22:34.092538 u2DelayCellOfst[10]=7 cells (2 PI)
7729 00:22:34.095587 u2DelayCellOfst[11]=3 cells (1 PI)
7730 00:22:34.099027 u2DelayCellOfst[12]=11 cells (3 PI)
7731 00:22:34.102386 u2DelayCellOfst[13]=11 cells (3 PI)
7732 00:22:34.105771 u2DelayCellOfst[14]=15 cells (4 PI)
7733 00:22:34.108573 u2DelayCellOfst[15]=11 cells (3 PI)
7734 00:22:34.115332 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7735 00:22:34.118807 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7736 00:22:34.118885 DramC Write-DBI on
7737 00:22:34.118947 ==
7738 00:22:34.122105 Dram Type= 6, Freq= 0, CH_0, rank 0
7739 00:22:34.128628 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7740 00:22:34.128716 ==
7741 00:22:34.128778
7742 00:22:34.128835
7743 00:22:34.128890 TX Vref Scan disable
7744 00:22:34.132950 == TX Byte 0 ==
7745 00:22:34.135810 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7746 00:22:34.139127 == TX Byte 1 ==
7747 00:22:34.142473 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7748 00:22:34.146210 DramC Write-DBI off
7749 00:22:34.146289
7750 00:22:34.146350 [DATLAT]
7751 00:22:34.146407 Freq=1600, CH0 RK0
7752 00:22:34.146463
7753 00:22:34.149460 DATLAT Default: 0xf
7754 00:22:34.152818 0, 0xFFFF, sum = 0
7755 00:22:34.152923 1, 0xFFFF, sum = 0
7756 00:22:34.155998 2, 0xFFFF, sum = 0
7757 00:22:34.156085 3, 0xFFFF, sum = 0
7758 00:22:34.158972 4, 0xFFFF, sum = 0
7759 00:22:34.159052 5, 0xFFFF, sum = 0
7760 00:22:34.162548 6, 0xFFFF, sum = 0
7761 00:22:34.162656 7, 0xFFFF, sum = 0
7762 00:22:34.166080 8, 0xFFFF, sum = 0
7763 00:22:34.166160 9, 0xFFFF, sum = 0
7764 00:22:34.168994 10, 0xFFFF, sum = 0
7765 00:22:34.169074 11, 0xFFFF, sum = 0
7766 00:22:34.172564 12, 0xFFFF, sum = 0
7767 00:22:34.172681 13, 0xEFFF, sum = 0
7768 00:22:34.175654 14, 0x0, sum = 1
7769 00:22:34.175734 15, 0x0, sum = 2
7770 00:22:34.179059 16, 0x0, sum = 3
7771 00:22:34.179140 17, 0x0, sum = 4
7772 00:22:34.182404 best_step = 15
7773 00:22:34.182507
7774 00:22:34.182596 ==
7775 00:22:34.185547 Dram Type= 6, Freq= 0, CH_0, rank 0
7776 00:22:34.189097 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7777 00:22:34.189176 ==
7778 00:22:34.192455 RX Vref Scan: 1
7779 00:22:34.192534
7780 00:22:34.192595 Set Vref Range= 24 -> 127
7781 00:22:34.192660
7782 00:22:34.195842 RX Vref 24 -> 127, step: 1
7783 00:22:34.195920
7784 00:22:34.199069 RX Delay 11 -> 252, step: 4
7785 00:22:34.199148
7786 00:22:34.202109 Set Vref, RX VrefLevel [Byte0]: 24
7787 00:22:34.205372 [Byte1]: 24
7788 00:22:34.205450
7789 00:22:34.208722 Set Vref, RX VrefLevel [Byte0]: 25
7790 00:22:34.212127 [Byte1]: 25
7791 00:22:34.215527
7792 00:22:34.215630 Set Vref, RX VrefLevel [Byte0]: 26
7793 00:22:34.219026 [Byte1]: 26
7794 00:22:34.223064
7795 00:22:34.223142 Set Vref, RX VrefLevel [Byte0]: 27
7796 00:22:34.226478 [Byte1]: 27
7797 00:22:34.231039
7798 00:22:34.231117 Set Vref, RX VrefLevel [Byte0]: 28
7799 00:22:34.233924 [Byte1]: 28
7800 00:22:34.238280
7801 00:22:34.238358 Set Vref, RX VrefLevel [Byte0]: 29
7802 00:22:34.241434 [Byte1]: 29
7803 00:22:34.246086
7804 00:22:34.246163 Set Vref, RX VrefLevel [Byte0]: 30
7805 00:22:34.249362 [Byte1]: 30
7806 00:22:34.253592
7807 00:22:34.253670 Set Vref, RX VrefLevel [Byte0]: 31
7808 00:22:34.256956 [Byte1]: 31
7809 00:22:34.261446
7810 00:22:34.261517 Set Vref, RX VrefLevel [Byte0]: 32
7811 00:22:34.264763 [Byte1]: 32
7812 00:22:34.268708
7813 00:22:34.268779 Set Vref, RX VrefLevel [Byte0]: 33
7814 00:22:34.272255 [Byte1]: 33
7815 00:22:34.276636
7816 00:22:34.276718 Set Vref, RX VrefLevel [Byte0]: 34
7817 00:22:34.279571 [Byte1]: 34
7818 00:22:34.284131
7819 00:22:34.284229 Set Vref, RX VrefLevel [Byte0]: 35
7820 00:22:34.287585 [Byte1]: 35
7821 00:22:34.291496
7822 00:22:34.291626 Set Vref, RX VrefLevel [Byte0]: 36
7823 00:22:34.294891 [Byte1]: 36
7824 00:22:34.299071
7825 00:22:34.299184 Set Vref, RX VrefLevel [Byte0]: 37
7826 00:22:34.302622 [Byte1]: 37
7827 00:22:34.306984
7828 00:22:34.307096 Set Vref, RX VrefLevel [Byte0]: 38
7829 00:22:34.310126 [Byte1]: 38
7830 00:22:34.314628
7831 00:22:34.314741 Set Vref, RX VrefLevel [Byte0]: 39
7832 00:22:34.317545 [Byte1]: 39
7833 00:22:34.322057
7834 00:22:34.322178 Set Vref, RX VrefLevel [Byte0]: 40
7835 00:22:34.325506 [Byte1]: 40
7836 00:22:34.329429
7837 00:22:34.329540 Set Vref, RX VrefLevel [Byte0]: 41
7838 00:22:34.332726 [Byte1]: 41
7839 00:22:34.337284
7840 00:22:34.337389 Set Vref, RX VrefLevel [Byte0]: 42
7841 00:22:34.340720 [Byte1]: 42
7842 00:22:34.344740
7843 00:22:34.344810 Set Vref, RX VrefLevel [Byte0]: 43
7844 00:22:34.348006 [Byte1]: 43
7845 00:22:34.352377
7846 00:22:34.352447 Set Vref, RX VrefLevel [Byte0]: 44
7847 00:22:34.355956 [Byte1]: 44
7848 00:22:34.359907
7849 00:22:34.359974 Set Vref, RX VrefLevel [Byte0]: 45
7850 00:22:34.363502 [Byte1]: 45
7851 00:22:34.367541
7852 00:22:34.367608 Set Vref, RX VrefLevel [Byte0]: 46
7853 00:22:34.371021 [Byte1]: 46
7854 00:22:34.375390
7855 00:22:34.375463 Set Vref, RX VrefLevel [Byte0]: 47
7856 00:22:34.378691 [Byte1]: 47
7857 00:22:34.383195
7858 00:22:34.383270 Set Vref, RX VrefLevel [Byte0]: 48
7859 00:22:34.385979 [Byte1]: 48
7860 00:22:34.390401
7861 00:22:34.390475 Set Vref, RX VrefLevel [Byte0]: 49
7862 00:22:34.393696 [Byte1]: 49
7863 00:22:34.398175
7864 00:22:34.398269 Set Vref, RX VrefLevel [Byte0]: 50
7865 00:22:34.401713 [Byte1]: 50
7866 00:22:34.405715
7867 00:22:34.405813 Set Vref, RX VrefLevel [Byte0]: 51
7868 00:22:34.408985 [Byte1]: 51
7869 00:22:34.413338
7870 00:22:34.413435 Set Vref, RX VrefLevel [Byte0]: 52
7871 00:22:34.417195 [Byte1]: 52
7872 00:22:34.421315
7873 00:22:34.421407 Set Vref, RX VrefLevel [Byte0]: 53
7874 00:22:34.424440 [Byte1]: 53
7875 00:22:34.428422
7876 00:22:34.428534 Set Vref, RX VrefLevel [Byte0]: 54
7877 00:22:34.431692 [Byte1]: 54
7878 00:22:34.436364
7879 00:22:34.436450 Set Vref, RX VrefLevel [Byte0]: 55
7880 00:22:34.439798 [Byte1]: 55
7881 00:22:34.443809
7882 00:22:34.443911 Set Vref, RX VrefLevel [Byte0]: 56
7883 00:22:34.447336 [Byte1]: 56
7884 00:22:34.451347
7885 00:22:34.451432 Set Vref, RX VrefLevel [Byte0]: 57
7886 00:22:34.454733 [Byte1]: 57
7887 00:22:34.459090
7888 00:22:34.459160 Set Vref, RX VrefLevel [Byte0]: 58
7889 00:22:34.462261 [Byte1]: 58
7890 00:22:34.466900
7891 00:22:34.466987 Set Vref, RX VrefLevel [Byte0]: 59
7892 00:22:34.469950 [Byte1]: 59
7893 00:22:34.474537
7894 00:22:34.474665 Set Vref, RX VrefLevel [Byte0]: 60
7895 00:22:34.477834 [Byte1]: 60
7896 00:22:34.481731
7897 00:22:34.481844 Set Vref, RX VrefLevel [Byte0]: 61
7898 00:22:34.485268 [Byte1]: 61
7899 00:22:34.489747
7900 00:22:34.489857 Set Vref, RX VrefLevel [Byte0]: 62
7901 00:22:34.492984 [Byte1]: 62
7902 00:22:34.496989
7903 00:22:34.497060 Set Vref, RX VrefLevel [Byte0]: 63
7904 00:22:34.500359 [Byte1]: 63
7905 00:22:34.504965
7906 00:22:34.505043 Set Vref, RX VrefLevel [Byte0]: 64
7907 00:22:34.507793 [Byte1]: 64
7908 00:22:34.512409
7909 00:22:34.512479 Set Vref, RX VrefLevel [Byte0]: 65
7910 00:22:34.515787 [Byte1]: 65
7911 00:22:34.519972
7912 00:22:34.520045 Set Vref, RX VrefLevel [Byte0]: 66
7913 00:22:34.523503 [Byte1]: 66
7914 00:22:34.527699
7915 00:22:34.527769 Set Vref, RX VrefLevel [Byte0]: 67
7916 00:22:34.530756 [Byte1]: 67
7917 00:22:34.534972
7918 00:22:34.535041 Set Vref, RX VrefLevel [Byte0]: 68
7919 00:22:34.538477 [Byte1]: 68
7920 00:22:34.542956
7921 00:22:34.543068 Set Vref, RX VrefLevel [Byte0]: 69
7922 00:22:34.546391 [Byte1]: 69
7923 00:22:34.550329
7924 00:22:34.550398 Set Vref, RX VrefLevel [Byte0]: 70
7925 00:22:34.553718 [Byte1]: 70
7926 00:22:34.558360
7927 00:22:34.558436 Set Vref, RX VrefLevel [Byte0]: 71
7928 00:22:34.561233 [Byte1]: 71
7929 00:22:34.565612
7930 00:22:34.565682 Set Vref, RX VrefLevel [Byte0]: 72
7931 00:22:34.569101 [Byte1]: 72
7932 00:22:34.573341
7933 00:22:34.573408 Set Vref, RX VrefLevel [Byte0]: 73
7934 00:22:34.576493 [Byte1]: 73
7935 00:22:34.581135
7936 00:22:34.581236 Set Vref, RX VrefLevel [Byte0]: 74
7937 00:22:34.584253 [Byte1]: 74
7938 00:22:34.588462
7939 00:22:34.588572 Set Vref, RX VrefLevel [Byte0]: 75
7940 00:22:34.591917 [Byte1]: 75
7941 00:22:34.596253
7942 00:22:34.596368 Set Vref, RX VrefLevel [Byte0]: 76
7943 00:22:34.599099 [Byte1]: 76
7944 00:22:34.603622
7945 00:22:34.603734 Set Vref, RX VrefLevel [Byte0]: 77
7946 00:22:34.607067 [Byte1]: 77
7947 00:22:34.611109
7948 00:22:34.611202 Set Vref, RX VrefLevel [Byte0]: 78
7949 00:22:34.614595 [Byte1]: 78
7950 00:22:34.619054
7951 00:22:34.619117 Set Vref, RX VrefLevel [Byte0]: 79
7952 00:22:34.622416 [Byte1]: 79
7953 00:22:34.626393
7954 00:22:34.626456 Final RX Vref Byte 0 = 65 to rank0
7955 00:22:34.629708 Final RX Vref Byte 1 = 57 to rank0
7956 00:22:34.633015 Final RX Vref Byte 0 = 65 to rank1
7957 00:22:34.636492 Final RX Vref Byte 1 = 57 to rank1==
7958 00:22:34.639634 Dram Type= 6, Freq= 0, CH_0, rank 0
7959 00:22:34.646421 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7960 00:22:34.646495 ==
7961 00:22:34.646558 DQS Delay:
7962 00:22:34.646613 DQS0 = 0, DQS1 = 0
7963 00:22:34.649547 DQM Delay:
7964 00:22:34.649610 DQM0 = 126, DQM1 = 119
7965 00:22:34.653212 DQ Delay:
7966 00:22:34.656639 DQ0 =126, DQ1 =128, DQ2 =126, DQ3 =122
7967 00:22:34.659937 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =138
7968 00:22:34.663239 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =114
7969 00:22:34.666614 DQ12 =124, DQ13 =124, DQ14 =130, DQ15 =128
7970 00:22:34.666684
7971 00:22:34.666743
7972 00:22:34.666795
7973 00:22:34.669985 [DramC_TX_OE_Calibration] TA2
7974 00:22:34.672803 Original DQ_B0 (3 6) =30, OEN = 27
7975 00:22:34.676243 Original DQ_B1 (3 6) =30, OEN = 27
7976 00:22:34.679572 24, 0x0, End_B0=24 End_B1=24
7977 00:22:34.679640 25, 0x0, End_B0=25 End_B1=25
7978 00:22:34.683185 26, 0x0, End_B0=26 End_B1=26
7979 00:22:34.686410 27, 0x0, End_B0=27 End_B1=27
7980 00:22:34.689507 28, 0x0, End_B0=28 End_B1=28
7981 00:22:34.692898 29, 0x0, End_B0=29 End_B1=29
7982 00:22:34.692971 30, 0x0, End_B0=30 End_B1=30
7983 00:22:34.696011 31, 0x4141, End_B0=30 End_B1=30
7984 00:22:34.699707 Byte0 end_step=30 best_step=27
7985 00:22:34.702577 Byte1 end_step=30 best_step=27
7986 00:22:34.705877 Byte0 TX OE(2T, 0.5T) = (3, 3)
7987 00:22:34.709299 Byte1 TX OE(2T, 0.5T) = (3, 3)
7988 00:22:34.709407
7989 00:22:34.709509
7990 00:22:34.716207 [DQSOSCAuto] RK0, (LSB)MR18= 0x1515, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
7991 00:22:34.719613 CH0 RK0: MR19=303, MR18=1515
7992 00:22:34.726433 CH0_RK0: MR19=0x303, MR18=0x1515, DQSOSC=399, MR23=63, INC=23, DEC=15
7993 00:22:34.726547
7994 00:22:34.729282 ----->DramcWriteLeveling(PI) begin...
7995 00:22:34.729409 ==
7996 00:22:34.732581 Dram Type= 6, Freq= 0, CH_0, rank 1
7997 00:22:34.735738 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7998 00:22:34.735806 ==
7999 00:22:34.739183 Write leveling (Byte 0): 33 => 33
8000 00:22:34.742727 Write leveling (Byte 1): 28 => 28
8001 00:22:34.746133 DramcWriteLeveling(PI) end<-----
8002 00:22:34.746249
8003 00:22:34.746356 ==
8004 00:22:34.748958 Dram Type= 6, Freq= 0, CH_0, rank 1
8005 00:22:34.752217 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8006 00:22:34.752331 ==
8007 00:22:34.755571 [Gating] SW mode calibration
8008 00:22:34.762212 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8009 00:22:34.768826 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8010 00:22:34.772190 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8011 00:22:34.779166 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8012 00:22:34.782459 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8013 00:22:34.785735 1 4 12 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (0 0)
8014 00:22:34.792466 1 4 16 | B1->B0 | 2525 3434 | 1 1 | (1 1) (1 1)
8015 00:22:34.795347 1 4 20 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
8016 00:22:34.799046 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8017 00:22:34.805501 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8018 00:22:34.808873 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8019 00:22:34.812197 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8020 00:22:34.815554 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8021 00:22:34.822442 1 5 12 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 0)
8022 00:22:34.825830 1 5 16 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
8023 00:22:34.828597 1 5 20 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
8024 00:22:34.835580 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8025 00:22:34.838680 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8026 00:22:34.842042 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8027 00:22:34.848918 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8028 00:22:34.852388 1 6 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8029 00:22:34.855244 1 6 12 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
8030 00:22:34.861914 1 6 16 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
8031 00:22:34.865355 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8032 00:22:34.868757 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8033 00:22:34.875443 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8034 00:22:34.878798 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8035 00:22:34.882182 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8036 00:22:34.888656 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8037 00:22:34.891807 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8038 00:22:34.895977 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8039 00:22:34.901923 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8040 00:22:34.904909 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8041 00:22:34.908153 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8042 00:22:34.914913 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8043 00:22:34.918278 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8044 00:22:34.921728 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8045 00:22:34.928469 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8046 00:22:34.931774 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8047 00:22:34.934696 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8048 00:22:34.941340 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8049 00:22:34.944523 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8050 00:22:34.948050 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8051 00:22:34.954879 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8052 00:22:34.958222 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8053 00:22:34.961547 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8054 00:22:34.968273 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8055 00:22:34.968352 Total UI for P1: 0, mck2ui 16
8056 00:22:34.971153 best dqsien dly found for B0: ( 1, 9, 10)
8057 00:22:34.978197 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8058 00:22:34.981529 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8059 00:22:34.984702 Total UI for P1: 0, mck2ui 16
8060 00:22:34.988109 best dqsien dly found for B1: ( 1, 9, 18)
8061 00:22:34.991076 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8062 00:22:34.994511 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8063 00:22:34.994587
8064 00:22:34.997931 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8065 00:22:35.004514 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8066 00:22:35.004611 [Gating] SW calibration Done
8067 00:22:35.004707 ==
8068 00:22:35.007949 Dram Type= 6, Freq= 0, CH_0, rank 1
8069 00:22:35.014233 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8070 00:22:35.014309 ==
8071 00:22:35.014369 RX Vref Scan: 0
8072 00:22:35.014425
8073 00:22:35.017706 RX Vref 0 -> 0, step: 1
8074 00:22:35.017772
8075 00:22:35.020900 RX Delay 0 -> 252, step: 8
8076 00:22:35.024471 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8077 00:22:35.027930 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8078 00:22:35.030984 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8079 00:22:35.037714 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8080 00:22:35.041114 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8081 00:22:35.044033 iDelay=200, Bit 5, Center 111 (56 ~ 167) 112
8082 00:22:35.047534 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8083 00:22:35.050970 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8084 00:22:35.057225 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8085 00:22:35.060548 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8086 00:22:35.063997 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8087 00:22:35.067333 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8088 00:22:35.070494 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8089 00:22:35.077369 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8090 00:22:35.080669 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8091 00:22:35.084045 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8092 00:22:35.084122 ==
8093 00:22:35.087429 Dram Type= 6, Freq= 0, CH_0, rank 1
8094 00:22:35.090740 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8095 00:22:35.090832 ==
8096 00:22:35.093656 DQS Delay:
8097 00:22:35.093732 DQS0 = 0, DQS1 = 0
8098 00:22:35.097113 DQM Delay:
8099 00:22:35.097187 DQM0 = 127, DQM1 = 121
8100 00:22:35.100587 DQ Delay:
8101 00:22:35.103974 DQ0 =127, DQ1 =131, DQ2 =123, DQ3 =123
8102 00:22:35.107409 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =139
8103 00:22:35.110239 DQ8 =111, DQ9 =107, DQ10 =123, DQ11 =115
8104 00:22:35.113622 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =127
8105 00:22:35.113693
8106 00:22:35.113750
8107 00:22:35.113804 ==
8108 00:22:35.117010 Dram Type= 6, Freq= 0, CH_0, rank 1
8109 00:22:35.120427 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8110 00:22:35.120491 ==
8111 00:22:35.120550
8112 00:22:35.120603
8113 00:22:35.123878 TX Vref Scan disable
8114 00:22:35.127168 == TX Byte 0 ==
8115 00:22:35.130334 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8116 00:22:35.133425 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8117 00:22:35.137316 == TX Byte 1 ==
8118 00:22:35.140387 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8119 00:22:35.143818 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8120 00:22:35.143921 ==
8121 00:22:35.146842 Dram Type= 6, Freq= 0, CH_0, rank 1
8122 00:22:35.153332 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8123 00:22:35.153412 ==
8124 00:22:35.165296
8125 00:22:35.168667 TX Vref early break, caculate TX vref
8126 00:22:35.172100 TX Vref=16, minBit 0, minWin=22, winSum=364
8127 00:22:35.175392 TX Vref=18, minBit 9, minWin=22, winSum=373
8128 00:22:35.178654 TX Vref=20, minBit 1, minWin=23, winSum=386
8129 00:22:35.182138 TX Vref=22, minBit 8, minWin=22, winSum=391
8130 00:22:35.185323 TX Vref=24, minBit 0, minWin=24, winSum=398
8131 00:22:35.191986 TX Vref=26, minBit 7, minWin=24, winSum=409
8132 00:22:35.195357 TX Vref=28, minBit 8, minWin=24, winSum=411
8133 00:22:35.198751 TX Vref=30, minBit 8, minWin=24, winSum=404
8134 00:22:35.202121 TX Vref=32, minBit 8, minWin=23, winSum=396
8135 00:22:35.205467 TX Vref=34, minBit 8, minWin=23, winSum=388
8136 00:22:35.211718 [TxChooseVref] Worse bit 8, Min win 24, Win sum 411, Final Vref 28
8137 00:22:35.211797
8138 00:22:35.215249 Final TX Range 0 Vref 28
8139 00:22:35.215328
8140 00:22:35.215388 ==
8141 00:22:35.218250 Dram Type= 6, Freq= 0, CH_0, rank 1
8142 00:22:35.221622 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8143 00:22:35.221701 ==
8144 00:22:35.221761
8145 00:22:35.221817
8146 00:22:35.225236 TX Vref Scan disable
8147 00:22:35.231490 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8148 00:22:35.231569 == TX Byte 0 ==
8149 00:22:35.235012 u2DelayCellOfst[0]=11 cells (3 PI)
8150 00:22:35.238357 u2DelayCellOfst[1]=18 cells (5 PI)
8151 00:22:35.241791 u2DelayCellOfst[2]=11 cells (3 PI)
8152 00:22:35.244952 u2DelayCellOfst[3]=7 cells (2 PI)
8153 00:22:35.248487 u2DelayCellOfst[4]=7 cells (2 PI)
8154 00:22:35.251776 u2DelayCellOfst[5]=0 cells (0 PI)
8155 00:22:35.255085 u2DelayCellOfst[6]=18 cells (5 PI)
8156 00:22:35.258025 u2DelayCellOfst[7]=18 cells (5 PI)
8157 00:22:35.261376 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8158 00:22:35.264600 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8159 00:22:35.268212 == TX Byte 1 ==
8160 00:22:35.268285 u2DelayCellOfst[8]=0 cells (0 PI)
8161 00:22:35.271344 u2DelayCellOfst[9]=0 cells (0 PI)
8162 00:22:35.274638 u2DelayCellOfst[10]=3 cells (1 PI)
8163 00:22:35.278236 u2DelayCellOfst[11]=3 cells (1 PI)
8164 00:22:35.281381 u2DelayCellOfst[12]=11 cells (3 PI)
8165 00:22:35.284743 u2DelayCellOfst[13]=7 cells (2 PI)
8166 00:22:35.288026 u2DelayCellOfst[14]=11 cells (3 PI)
8167 00:22:35.291455 u2DelayCellOfst[15]=7 cells (2 PI)
8168 00:22:35.294539 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8169 00:22:35.301058 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8170 00:22:35.301138 DramC Write-DBI on
8171 00:22:35.301228 ==
8172 00:22:35.304854 Dram Type= 6, Freq= 0, CH_0, rank 1
8173 00:22:35.308157 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8174 00:22:35.311103 ==
8175 00:22:35.311180
8176 00:22:35.311239
8177 00:22:35.311296 TX Vref Scan disable
8178 00:22:35.314828 == TX Byte 0 ==
8179 00:22:35.317746 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
8180 00:22:35.321285 == TX Byte 1 ==
8181 00:22:35.324763 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8182 00:22:35.327648 DramC Write-DBI off
8183 00:22:35.327726
8184 00:22:35.327788 [DATLAT]
8185 00:22:35.327845 Freq=1600, CH0 RK1
8186 00:22:35.327900
8187 00:22:35.331040 DATLAT Default: 0xf
8188 00:22:35.331120 0, 0xFFFF, sum = 0
8189 00:22:35.334623 1, 0xFFFF, sum = 0
8190 00:22:35.338063 2, 0xFFFF, sum = 0
8191 00:22:35.338144 3, 0xFFFF, sum = 0
8192 00:22:35.341038 4, 0xFFFF, sum = 0
8193 00:22:35.341117 5, 0xFFFF, sum = 0
8194 00:22:35.344500 6, 0xFFFF, sum = 0
8195 00:22:35.344580 7, 0xFFFF, sum = 0
8196 00:22:35.347824 8, 0xFFFF, sum = 0
8197 00:22:35.347903 9, 0xFFFF, sum = 0
8198 00:22:35.351068 10, 0xFFFF, sum = 0
8199 00:22:35.351176 11, 0xFFFF, sum = 0
8200 00:22:35.354628 12, 0xFFFF, sum = 0
8201 00:22:35.354747 13, 0xCFFF, sum = 0
8202 00:22:35.357846 14, 0x0, sum = 1
8203 00:22:35.357925 15, 0x0, sum = 2
8204 00:22:35.361028 16, 0x0, sum = 3
8205 00:22:35.361109 17, 0x0, sum = 4
8206 00:22:35.364423 best_step = 15
8207 00:22:35.364504
8208 00:22:35.364564 ==
8209 00:22:35.367806 Dram Type= 6, Freq= 0, CH_0, rank 1
8210 00:22:35.371188 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8211 00:22:35.371266 ==
8212 00:22:35.374017 RX Vref Scan: 0
8213 00:22:35.374096
8214 00:22:35.374157 RX Vref 0 -> 0, step: 1
8215 00:22:35.374214
8216 00:22:35.377551 RX Delay 3 -> 252, step: 4
8217 00:22:35.381012 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8218 00:22:35.387667 iDelay=191, Bit 1, Center 124 (71 ~ 178) 108
8219 00:22:35.390994 iDelay=191, Bit 2, Center 122 (71 ~ 174) 104
8220 00:22:35.394021 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8221 00:22:35.397491 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8222 00:22:35.400849 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8223 00:22:35.407579 iDelay=191, Bit 6, Center 136 (83 ~ 190) 108
8224 00:22:35.410824 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8225 00:22:35.414045 iDelay=191, Bit 8, Center 112 (55 ~ 170) 116
8226 00:22:35.417283 iDelay=191, Bit 9, Center 106 (51 ~ 162) 112
8227 00:22:35.420637 iDelay=191, Bit 10, Center 120 (63 ~ 178) 116
8228 00:22:35.427496 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8229 00:22:35.430790 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8230 00:22:35.433964 iDelay=191, Bit 13, Center 122 (67 ~ 178) 112
8231 00:22:35.437419 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8232 00:22:35.443710 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8233 00:22:35.443790 ==
8234 00:22:35.447176 Dram Type= 6, Freq= 0, CH_0, rank 1
8235 00:22:35.450479 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8236 00:22:35.450558 ==
8237 00:22:35.450620 DQS Delay:
8238 00:22:35.453857 DQS0 = 0, DQS1 = 0
8239 00:22:35.453935 DQM Delay:
8240 00:22:35.457141 DQM0 = 124, DQM1 = 118
8241 00:22:35.457221 DQ Delay:
8242 00:22:35.460294 DQ0 =124, DQ1 =124, DQ2 =122, DQ3 =122
8243 00:22:35.463556 DQ4 =124, DQ5 =112, DQ6 =136, DQ7 =134
8244 00:22:35.467519 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =112
8245 00:22:35.470231 DQ12 =124, DQ13 =122, DQ14 =128, DQ15 =124
8246 00:22:35.470309
8247 00:22:35.470372
8248 00:22:35.470466
8249 00:22:35.473656 [DramC_TX_OE_Calibration] TA2
8250 00:22:35.477102 Original DQ_B0 (3 6) =30, OEN = 27
8251 00:22:35.480603 Original DQ_B1 (3 6) =30, OEN = 27
8252 00:22:35.484053 24, 0x0, End_B0=24 End_B1=24
8253 00:22:35.486839 25, 0x0, End_B0=25 End_B1=25
8254 00:22:35.486910 26, 0x0, End_B0=26 End_B1=26
8255 00:22:35.490252 27, 0x0, End_B0=27 End_B1=27
8256 00:22:35.493689 28, 0x0, End_B0=28 End_B1=28
8257 00:22:35.497144 29, 0x0, End_B0=29 End_B1=29
8258 00:22:35.500571 30, 0x0, End_B0=30 End_B1=30
8259 00:22:35.500672 31, 0x4141, End_B0=30 End_B1=30
8260 00:22:35.503479 Byte0 end_step=30 best_step=27
8261 00:22:35.506851 Byte1 end_step=30 best_step=27
8262 00:22:35.510245 Byte0 TX OE(2T, 0.5T) = (3, 3)
8263 00:22:35.513644 Byte1 TX OE(2T, 0.5T) = (3, 3)
8264 00:22:35.513712
8265 00:22:35.513769
8266 00:22:35.520285 [DQSOSCAuto] RK1, (LSB)MR18= 0x2815, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 389 ps
8267 00:22:35.523399 CH0 RK1: MR19=303, MR18=2815
8268 00:22:35.530082 CH0_RK1: MR19=0x303, MR18=0x2815, DQSOSC=389, MR23=63, INC=24, DEC=16
8269 00:22:35.533497 [RxdqsGatingPostProcess] freq 1600
8270 00:22:35.539978 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8271 00:22:35.540049 best DQS0 dly(2T, 0.5T) = (1, 1)
8272 00:22:35.543578 best DQS1 dly(2T, 0.5T) = (1, 1)
8273 00:22:35.546987 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8274 00:22:35.549902 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8275 00:22:35.553259 best DQS0 dly(2T, 0.5T) = (1, 1)
8276 00:22:35.556699 best DQS1 dly(2T, 0.5T) = (1, 1)
8277 00:22:35.559979 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8278 00:22:35.563085 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8279 00:22:35.566580 Pre-setting of DQS Precalculation
8280 00:22:35.569742 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8281 00:22:35.573379 ==
8282 00:22:35.573454 Dram Type= 6, Freq= 0, CH_1, rank 0
8283 00:22:35.580119 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8284 00:22:35.580192 ==
8285 00:22:35.583507 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8286 00:22:35.589893 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8287 00:22:35.593259 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8288 00:22:35.599600 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8289 00:22:35.607676 [CA 0] Center 42 (13~71) winsize 59
8290 00:22:35.611158 [CA 1] Center 42 (12~72) winsize 61
8291 00:22:35.614553 [CA 2] Center 37 (9~66) winsize 58
8292 00:22:35.617924 [CA 3] Center 37 (8~66) winsize 59
8293 00:22:35.621381 [CA 4] Center 37 (8~66) winsize 59
8294 00:22:35.624637 [CA 5] Center 36 (7~66) winsize 60
8295 00:22:35.624751
8296 00:22:35.627528 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8297 00:22:35.627594
8298 00:22:35.631050 [CATrainingPosCal] consider 1 rank data
8299 00:22:35.634450 u2DelayCellTimex100 = 258/100 ps
8300 00:22:35.637605 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8301 00:22:35.643953 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8302 00:22:35.647705 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8303 00:22:35.650938 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8304 00:22:35.653912 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8305 00:22:35.657373 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8306 00:22:35.657439
8307 00:22:35.660623 CA PerBit enable=1, Macro0, CA PI delay=36
8308 00:22:35.660727
8309 00:22:35.664334 [CBTSetCACLKResult] CA Dly = 36
8310 00:22:35.667302 CS Dly: 10 (0~41)
8311 00:22:35.670528 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8312 00:22:35.673925 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8313 00:22:35.673990 ==
8314 00:22:35.677306 Dram Type= 6, Freq= 0, CH_1, rank 1
8315 00:22:35.680782 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8316 00:22:35.684143 ==
8317 00:22:35.687078 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8318 00:22:35.690536 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8319 00:22:35.697390 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8320 00:22:35.703756 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8321 00:22:35.711124 [CA 0] Center 42 (13~71) winsize 59
8322 00:22:35.713951 [CA 1] Center 42 (12~72) winsize 61
8323 00:22:35.717496 [CA 2] Center 37 (8~66) winsize 59
8324 00:22:35.721018 [CA 3] Center 36 (6~66) winsize 61
8325 00:22:35.723879 [CA 4] Center 37 (7~67) winsize 61
8326 00:22:35.727432 [CA 5] Center 36 (6~66) winsize 61
8327 00:22:35.727531
8328 00:22:35.730887 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8329 00:22:35.730986
8330 00:22:35.734371 [CATrainingPosCal] consider 2 rank data
8331 00:22:35.737177 u2DelayCellTimex100 = 258/100 ps
8332 00:22:35.740963 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8333 00:22:35.747169 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8334 00:22:35.750396 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8335 00:22:35.754179 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8336 00:22:35.757504 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8337 00:22:35.760785 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8338 00:22:35.760852
8339 00:22:35.764235 CA PerBit enable=1, Macro0, CA PI delay=36
8340 00:22:35.764362
8341 00:22:35.767312 [CBTSetCACLKResult] CA Dly = 36
8342 00:22:35.770488 CS Dly: 11 (0~43)
8343 00:22:35.773911 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8344 00:22:35.777002 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8345 00:22:35.777072
8346 00:22:35.780627 ----->DramcWriteLeveling(PI) begin...
8347 00:22:35.780734 ==
8348 00:22:35.784007 Dram Type= 6, Freq= 0, CH_1, rank 0
8349 00:22:35.790641 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8350 00:22:35.790744 ==
8351 00:22:35.793931 Write leveling (Byte 0): 24 => 24
8352 00:22:35.794009 Write leveling (Byte 1): 30 => 30
8353 00:22:35.797025 DramcWriteLeveling(PI) end<-----
8354 00:22:35.797139
8355 00:22:35.797250 ==
8356 00:22:35.800659 Dram Type= 6, Freq= 0, CH_1, rank 0
8357 00:22:35.807293 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8358 00:22:35.807393 ==
8359 00:22:35.810420 [Gating] SW mode calibration
8360 00:22:35.816957 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8361 00:22:35.820403 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8362 00:22:35.826709 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8363 00:22:35.830137 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8364 00:22:35.833601 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8365 00:22:35.840461 1 4 12 | B1->B0 | 2322 2323 | 1 0 | (0 0) (0 0)
8366 00:22:35.843777 1 4 16 | B1->B0 | 3030 3231 | 0 1 | (0 0) (0 0)
8367 00:22:35.847164 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8368 00:22:35.853472 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8369 00:22:35.856700 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8370 00:22:35.860315 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8371 00:22:35.867032 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8372 00:22:35.870451 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8373 00:22:35.873746 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8374 00:22:35.877037 1 5 16 | B1->B0 | 2b2b 2626 | 1 0 | (0 1) (1 0)
8375 00:22:35.883304 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8376 00:22:35.886840 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8377 00:22:35.890419 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8378 00:22:35.896725 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8379 00:22:35.899892 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8380 00:22:35.903151 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8381 00:22:35.909777 1 6 12 | B1->B0 | 2929 2b2b | 0 0 | (0 0) (0 0)
8382 00:22:35.913089 1 6 16 | B1->B0 | 3c3c 4040 | 1 0 | (0 0) (0 0)
8383 00:22:35.916628 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8384 00:22:35.923029 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8385 00:22:35.926561 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8386 00:22:35.929665 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8387 00:22:35.936441 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8388 00:22:35.939300 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8389 00:22:35.942742 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8390 00:22:35.949358 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8391 00:22:35.952815 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8392 00:22:35.956262 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8393 00:22:35.962944 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8394 00:22:35.965872 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8395 00:22:35.969171 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 00:22:35.976113 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8397 00:22:35.979435 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 00:22:35.982545 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 00:22:35.989290 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 00:22:35.992268 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 00:22:35.995931 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 00:22:36.002652 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 00:22:36.005396 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 00:22:36.008856 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 00:22:36.015774 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8406 00:22:36.018711 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8407 00:22:36.022116 Total UI for P1: 0, mck2ui 16
8408 00:22:36.025525 best dqsien dly found for B1: ( 1, 9, 12)
8409 00:22:36.028915 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8410 00:22:36.032236 Total UI for P1: 0, mck2ui 16
8411 00:22:36.035646 best dqsien dly found for B0: ( 1, 9, 14)
8412 00:22:36.038832 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8413 00:22:36.041984 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8414 00:22:36.042094
8415 00:22:36.048680 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8416 00:22:36.052048 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8417 00:22:36.055402 [Gating] SW calibration Done
8418 00:22:36.055521 ==
8419 00:22:36.058681 Dram Type= 6, Freq= 0, CH_1, rank 0
8420 00:22:36.062097 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8421 00:22:36.062211 ==
8422 00:22:36.062324 RX Vref Scan: 0
8423 00:22:36.062425
8424 00:22:36.065289 RX Vref 0 -> 0, step: 1
8425 00:22:36.065369
8426 00:22:36.068776 RX Delay 0 -> 252, step: 8
8427 00:22:36.071623 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8428 00:22:36.075002 iDelay=200, Bit 1, Center 127 (64 ~ 191) 128
8429 00:22:36.082073 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8430 00:22:36.084948 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8431 00:22:36.088710 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8432 00:22:36.091566 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8433 00:22:36.094906 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8434 00:22:36.101610 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8435 00:22:36.104748 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8436 00:22:36.108207 iDelay=200, Bit 9, Center 111 (48 ~ 175) 128
8437 00:22:36.111597 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8438 00:22:36.114870 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8439 00:22:36.121491 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8440 00:22:36.124500 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8441 00:22:36.127836 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8442 00:22:36.131267 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8443 00:22:36.131390 ==
8444 00:22:36.134636 Dram Type= 6, Freq= 0, CH_1, rank 0
8445 00:22:36.141007 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8446 00:22:36.141132 ==
8447 00:22:36.141235 DQS Delay:
8448 00:22:36.144477 DQS0 = 0, DQS1 = 0
8449 00:22:36.144588 DQM Delay:
8450 00:22:36.147912 DQM0 = 131, DQM1 = 125
8451 00:22:36.148028 DQ Delay:
8452 00:22:36.151305 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8453 00:22:36.154581 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =127
8454 00:22:36.157993 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =119
8455 00:22:36.161039 DQ12 =135, DQ13 =131, DQ14 =135, DQ15 =135
8456 00:22:36.161153
8457 00:22:36.161266
8458 00:22:36.161367 ==
8459 00:22:36.164660 Dram Type= 6, Freq= 0, CH_1, rank 0
8460 00:22:36.171082 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8461 00:22:36.171204 ==
8462 00:22:36.171307
8463 00:22:36.171416
8464 00:22:36.171540 TX Vref Scan disable
8465 00:22:36.174076 == TX Byte 0 ==
8466 00:22:36.177668 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8467 00:22:36.184348 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8468 00:22:36.184422 == TX Byte 1 ==
8469 00:22:36.187568 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8470 00:22:36.194217 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8471 00:22:36.194296 ==
8472 00:22:36.197146 Dram Type= 6, Freq= 0, CH_1, rank 0
8473 00:22:36.200567 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8474 00:22:36.200637 ==
8475 00:22:36.214692
8476 00:22:36.217975 TX Vref early break, caculate TX vref
8477 00:22:36.221405 TX Vref=16, minBit 8, minWin=21, winSum=367
8478 00:22:36.224667 TX Vref=18, minBit 9, minWin=21, winSum=369
8479 00:22:36.228020 TX Vref=20, minBit 8, minWin=22, winSum=381
8480 00:22:36.231084 TX Vref=22, minBit 8, minWin=23, winSum=391
8481 00:22:36.234700 TX Vref=24, minBit 9, minWin=23, winSum=397
8482 00:22:36.241400 TX Vref=26, minBit 10, minWin=24, winSum=411
8483 00:22:36.244291 TX Vref=28, minBit 9, minWin=24, winSum=415
8484 00:22:36.247697 TX Vref=30, minBit 9, minWin=24, winSum=411
8485 00:22:36.251161 TX Vref=32, minBit 9, minWin=24, winSum=405
8486 00:22:36.254537 TX Vref=34, minBit 9, minWin=23, winSum=397
8487 00:22:36.257470 TX Vref=36, minBit 8, minWin=22, winSum=382
8488 00:22:36.264287 [TxChooseVref] Worse bit 9, Min win 24, Win sum 415, Final Vref 28
8489 00:22:36.264400
8490 00:22:36.267739 Final TX Range 0 Vref 28
8491 00:22:36.267854
8492 00:22:36.267955 ==
8493 00:22:36.271091 Dram Type= 6, Freq= 0, CH_1, rank 0
8494 00:22:36.274470 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8495 00:22:36.274582 ==
8496 00:22:36.274686
8497 00:22:36.277603
8498 00:22:36.277713 TX Vref Scan disable
8499 00:22:36.284277 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8500 00:22:36.284392 == TX Byte 0 ==
8501 00:22:36.287491 u2DelayCellOfst[0]=18 cells (5 PI)
8502 00:22:36.290826 u2DelayCellOfst[1]=15 cells (4 PI)
8503 00:22:36.294089 u2DelayCellOfst[2]=0 cells (0 PI)
8504 00:22:36.297585 u2DelayCellOfst[3]=7 cells (2 PI)
8505 00:22:36.300577 u2DelayCellOfst[4]=7 cells (2 PI)
8506 00:22:36.304161 u2DelayCellOfst[5]=22 cells (6 PI)
8507 00:22:36.307258 u2DelayCellOfst[6]=22 cells (6 PI)
8508 00:22:36.310703 u2DelayCellOfst[7]=7 cells (2 PI)
8509 00:22:36.314157 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8510 00:22:36.316914 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8511 00:22:36.320537 == TX Byte 1 ==
8512 00:22:36.324016 u2DelayCellOfst[8]=0 cells (0 PI)
8513 00:22:36.327281 u2DelayCellOfst[9]=7 cells (2 PI)
8514 00:22:36.330570 u2DelayCellOfst[10]=15 cells (4 PI)
8515 00:22:36.333459 u2DelayCellOfst[11]=11 cells (3 PI)
8516 00:22:36.333538 u2DelayCellOfst[12]=15 cells (4 PI)
8517 00:22:36.336887 u2DelayCellOfst[13]=18 cells (5 PI)
8518 00:22:36.340058 u2DelayCellOfst[14]=18 cells (5 PI)
8519 00:22:36.343509 u2DelayCellOfst[15]=18 cells (5 PI)
8520 00:22:36.350014 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8521 00:22:36.353501 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8522 00:22:36.353617 DramC Write-DBI on
8523 00:22:36.356716 ==
8524 00:22:36.356830 Dram Type= 6, Freq= 0, CH_1, rank 0
8525 00:22:36.363526 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8526 00:22:36.363606 ==
8527 00:22:36.363668
8528 00:22:36.363732
8529 00:22:36.366976 TX Vref Scan disable
8530 00:22:36.367043 == TX Byte 0 ==
8531 00:22:36.373332 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8532 00:22:36.373401 == TX Byte 1 ==
8533 00:22:36.376735 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8534 00:22:36.380140 DramC Write-DBI off
8535 00:22:36.380205
8536 00:22:36.380260 [DATLAT]
8537 00:22:36.383514 Freq=1600, CH1 RK0
8538 00:22:36.383584
8539 00:22:36.383638 DATLAT Default: 0xf
8540 00:22:36.387004 0, 0xFFFF, sum = 0
8541 00:22:36.387068 1, 0xFFFF, sum = 0
8542 00:22:36.389869 2, 0xFFFF, sum = 0
8543 00:22:36.389937 3, 0xFFFF, sum = 0
8544 00:22:36.393639 4, 0xFFFF, sum = 0
8545 00:22:36.393702 5, 0xFFFF, sum = 0
8546 00:22:36.396477 6, 0xFFFF, sum = 0
8547 00:22:36.396544 7, 0xFFFF, sum = 0
8548 00:22:36.399915 8, 0xFFFF, sum = 0
8549 00:22:36.399979 9, 0xFFFF, sum = 0
8550 00:22:36.403635 10, 0xFFFF, sum = 0
8551 00:22:36.406528 11, 0xFFFF, sum = 0
8552 00:22:36.406592 12, 0xFFFF, sum = 0
8553 00:22:36.409940 13, 0x8FFF, sum = 0
8554 00:22:36.410004 14, 0x0, sum = 1
8555 00:22:36.413557 15, 0x0, sum = 2
8556 00:22:36.413621 16, 0x0, sum = 3
8557 00:22:36.413681 17, 0x0, sum = 4
8558 00:22:36.416500 best_step = 15
8559 00:22:36.416562
8560 00:22:36.416614 ==
8561 00:22:36.419898 Dram Type= 6, Freq= 0, CH_1, rank 0
8562 00:22:36.423207 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8563 00:22:36.423275 ==
8564 00:22:36.426363 RX Vref Scan: 1
8565 00:22:36.426482
8566 00:22:36.429850 Set Vref Range= 24 -> 127
8567 00:22:36.429967
8568 00:22:36.430069 RX Vref 24 -> 127, step: 1
8569 00:22:36.430173
8570 00:22:36.433383 RX Delay 3 -> 252, step: 4
8571 00:22:36.433456
8572 00:22:36.436790 Set Vref, RX VrefLevel [Byte0]: 24
8573 00:22:36.439681 [Byte1]: 24
8574 00:22:36.439753
8575 00:22:36.443294 Set Vref, RX VrefLevel [Byte0]: 25
8576 00:22:36.446620 [Byte1]: 25
8577 00:22:36.450532
8578 00:22:36.450631 Set Vref, RX VrefLevel [Byte0]: 26
8579 00:22:36.454190 [Byte1]: 26
8580 00:22:36.458208
8581 00:22:36.458283 Set Vref, RX VrefLevel [Byte0]: 27
8582 00:22:36.461685 [Byte1]: 27
8583 00:22:36.466253
8584 00:22:36.466334 Set Vref, RX VrefLevel [Byte0]: 28
8585 00:22:36.469118 [Byte1]: 28
8586 00:22:36.473663
8587 00:22:36.473757 Set Vref, RX VrefLevel [Byte0]: 29
8588 00:22:36.477072 [Byte1]: 29
8589 00:22:36.481103
8590 00:22:36.481172 Set Vref, RX VrefLevel [Byte0]: 30
8591 00:22:36.484539 [Byte1]: 30
8592 00:22:36.489069
8593 00:22:36.489168 Set Vref, RX VrefLevel [Byte0]: 31
8594 00:22:36.492474 [Byte1]: 31
8595 00:22:36.496767
8596 00:22:36.496841 Set Vref, RX VrefLevel [Byte0]: 32
8597 00:22:36.499669 [Byte1]: 32
8598 00:22:36.504176
8599 00:22:36.504250 Set Vref, RX VrefLevel [Byte0]: 33
8600 00:22:36.507466 [Byte1]: 33
8601 00:22:36.512047
8602 00:22:36.512122 Set Vref, RX VrefLevel [Byte0]: 34
8603 00:22:36.515435 [Byte1]: 34
8604 00:22:36.519430
8605 00:22:36.519504 Set Vref, RX VrefLevel [Byte0]: 35
8606 00:22:36.522898 [Byte1]: 35
8607 00:22:36.527404
8608 00:22:36.527491 Set Vref, RX VrefLevel [Byte0]: 36
8609 00:22:36.530737 [Byte1]: 36
8610 00:22:36.535085
8611 00:22:36.535158 Set Vref, RX VrefLevel [Byte0]: 37
8612 00:22:36.538237 [Byte1]: 37
8613 00:22:36.542535
8614 00:22:36.542634 Set Vref, RX VrefLevel [Byte0]: 38
8615 00:22:36.545641 [Byte1]: 38
8616 00:22:36.550338
8617 00:22:36.550423 Set Vref, RX VrefLevel [Byte0]: 39
8618 00:22:36.553228 [Byte1]: 39
8619 00:22:36.557736
8620 00:22:36.557846 Set Vref, RX VrefLevel [Byte0]: 40
8621 00:22:36.561025 [Byte1]: 40
8622 00:22:36.565291
8623 00:22:36.565413 Set Vref, RX VrefLevel [Byte0]: 41
8624 00:22:36.568949 [Byte1]: 41
8625 00:22:36.572896
8626 00:22:36.573010 Set Vref, RX VrefLevel [Byte0]: 42
8627 00:22:36.576381 [Byte1]: 42
8628 00:22:36.580712
8629 00:22:36.580836 Set Vref, RX VrefLevel [Byte0]: 43
8630 00:22:36.584120 [Byte1]: 43
8631 00:22:36.588690
8632 00:22:36.588801 Set Vref, RX VrefLevel [Byte0]: 44
8633 00:22:36.591485 [Byte1]: 44
8634 00:22:36.596039
8635 00:22:36.596158 Set Vref, RX VrefLevel [Byte0]: 45
8636 00:22:36.599544 [Byte1]: 45
8637 00:22:36.603988
8638 00:22:36.604105 Set Vref, RX VrefLevel [Byte0]: 46
8639 00:22:36.606834 [Byte1]: 46
8640 00:22:36.611194
8641 00:22:36.611313 Set Vref, RX VrefLevel [Byte0]: 47
8642 00:22:36.614590 [Byte1]: 47
8643 00:22:36.619160
8644 00:22:36.619283 Set Vref, RX VrefLevel [Byte0]: 48
8645 00:22:36.622481 [Byte1]: 48
8646 00:22:36.626541
8647 00:22:36.626652 Set Vref, RX VrefLevel [Byte0]: 49
8648 00:22:36.629842 [Byte1]: 49
8649 00:22:36.634194
8650 00:22:36.634319 Set Vref, RX VrefLevel [Byte0]: 50
8651 00:22:36.637545 [Byte1]: 50
8652 00:22:36.641798
8653 00:22:36.641917 Set Vref, RX VrefLevel [Byte0]: 51
8654 00:22:36.645136 [Byte1]: 51
8655 00:22:36.649842
8656 00:22:36.649952 Set Vref, RX VrefLevel [Byte0]: 52
8657 00:22:36.653241 [Byte1]: 52
8658 00:22:36.657232
8659 00:22:36.657336 Set Vref, RX VrefLevel [Byte0]: 53
8660 00:22:36.660670 [Byte1]: 53
8661 00:22:36.664697
8662 00:22:36.664808 Set Vref, RX VrefLevel [Byte0]: 54
8663 00:22:36.668037 [Byte1]: 54
8664 00:22:36.672640
8665 00:22:36.672764 Set Vref, RX VrefLevel [Byte0]: 55
8666 00:22:36.676078 [Byte1]: 55
8667 00:22:36.680283
8668 00:22:36.680403 Set Vref, RX VrefLevel [Byte0]: 56
8669 00:22:36.683377 [Byte1]: 56
8670 00:22:36.688132
8671 00:22:36.688244 Set Vref, RX VrefLevel [Byte0]: 57
8672 00:22:36.691145 [Byte1]: 57
8673 00:22:36.695410
8674 00:22:36.695512 Set Vref, RX VrefLevel [Byte0]: 58
8675 00:22:36.698781 [Byte1]: 58
8676 00:22:36.703208
8677 00:22:36.703334 Set Vref, RX VrefLevel [Byte0]: 59
8678 00:22:36.706406 [Byte1]: 59
8679 00:22:36.710696
8680 00:22:36.710800 Set Vref, RX VrefLevel [Byte0]: 60
8681 00:22:36.714009 [Byte1]: 60
8682 00:22:36.718444
8683 00:22:36.718566 Set Vref, RX VrefLevel [Byte0]: 61
8684 00:22:36.721887 [Byte1]: 61
8685 00:22:36.726400
8686 00:22:36.726517 Set Vref, RX VrefLevel [Byte0]: 62
8687 00:22:36.729268 [Byte1]: 62
8688 00:22:36.733869
8689 00:22:36.733987 Set Vref, RX VrefLevel [Byte0]: 63
8690 00:22:36.737192 [Byte1]: 63
8691 00:22:36.741719
8692 00:22:36.741839 Set Vref, RX VrefLevel [Byte0]: 64
8693 00:22:36.744888 [Byte1]: 64
8694 00:22:36.748964
8695 00:22:36.749082 Set Vref, RX VrefLevel [Byte0]: 65
8696 00:22:36.752283 [Byte1]: 65
8697 00:22:36.756840
8698 00:22:36.756959 Set Vref, RX VrefLevel [Byte0]: 66
8699 00:22:36.760217 [Byte1]: 66
8700 00:22:36.764629
8701 00:22:36.764752 Set Vref, RX VrefLevel [Byte0]: 67
8702 00:22:36.767540 [Byte1]: 67
8703 00:22:36.771988
8704 00:22:36.772106 Set Vref, RX VrefLevel [Byte0]: 68
8705 00:22:36.775429 [Byte1]: 68
8706 00:22:36.779487
8707 00:22:36.779596 Set Vref, RX VrefLevel [Byte0]: 69
8708 00:22:36.782939 [Byte1]: 69
8709 00:22:36.787523
8710 00:22:36.787633 Set Vref, RX VrefLevel [Byte0]: 70
8711 00:22:36.790864 [Byte1]: 70
8712 00:22:36.795223
8713 00:22:36.795323 Final RX Vref Byte 0 = 56 to rank0
8714 00:22:36.798591 Final RX Vref Byte 1 = 58 to rank0
8715 00:22:36.801577 Final RX Vref Byte 0 = 56 to rank1
8716 00:22:36.805070 Final RX Vref Byte 1 = 58 to rank1==
8717 00:22:36.808547 Dram Type= 6, Freq= 0, CH_1, rank 0
8718 00:22:36.815161 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8719 00:22:36.815270 ==
8720 00:22:36.815382 DQS Delay:
8721 00:22:36.815483 DQS0 = 0, DQS1 = 0
8722 00:22:36.818332 DQM Delay:
8723 00:22:36.818438 DQM0 = 130, DQM1 = 122
8724 00:22:36.821551 DQ Delay:
8725 00:22:36.824639 DQ0 =136, DQ1 =126, DQ2 =118, DQ3 =126
8726 00:22:36.828380 DQ4 =128, DQ5 =140, DQ6 =140, DQ7 =126
8727 00:22:36.831523 DQ8 =108, DQ9 =112, DQ10 =124, DQ11 =116
8728 00:22:36.835034 DQ12 =130, DQ13 =130, DQ14 =130, DQ15 =132
8729 00:22:36.835143
8730 00:22:36.835256
8731 00:22:36.835357
8732 00:22:36.838301 [DramC_TX_OE_Calibration] TA2
8733 00:22:36.841480 Original DQ_B0 (3 6) =30, OEN = 27
8734 00:22:36.844715 Original DQ_B1 (3 6) =30, OEN = 27
8735 00:22:36.848081 24, 0x0, End_B0=24 End_B1=24
8736 00:22:36.848195 25, 0x0, End_B0=25 End_B1=25
8737 00:22:36.851365 26, 0x0, End_B0=26 End_B1=26
8738 00:22:36.854737 27, 0x0, End_B0=27 End_B1=27
8739 00:22:36.858220 28, 0x0, End_B0=28 End_B1=28
8740 00:22:36.861171 29, 0x0, End_B0=29 End_B1=29
8741 00:22:36.861286 30, 0x0, End_B0=30 End_B1=30
8742 00:22:36.864686 31, 0x4141, End_B0=30 End_B1=30
8743 00:22:36.868058 Byte0 end_step=30 best_step=27
8744 00:22:36.870981 Byte1 end_step=30 best_step=27
8745 00:22:36.874458 Byte0 TX OE(2T, 0.5T) = (3, 3)
8746 00:22:36.877807 Byte1 TX OE(2T, 0.5T) = (3, 3)
8747 00:22:36.877924
8748 00:22:36.878028
8749 00:22:36.884712 [DQSOSCAuto] RK0, (LSB)MR18= 0x80c, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 405 ps
8750 00:22:36.887534 CH1 RK0: MR19=303, MR18=80C
8751 00:22:36.894488 CH1_RK0: MR19=0x303, MR18=0x80C, DQSOSC=403, MR23=63, INC=22, DEC=15
8752 00:22:36.894608
8753 00:22:36.897752 ----->DramcWriteLeveling(PI) begin...
8754 00:22:36.897859 ==
8755 00:22:36.901015 Dram Type= 6, Freq= 0, CH_1, rank 1
8756 00:22:36.904288 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8757 00:22:36.904379 ==
8758 00:22:36.907762 Write leveling (Byte 0): 25 => 25
8759 00:22:36.911121 Write leveling (Byte 1): 29 => 29
8760 00:22:36.914057 DramcWriteLeveling(PI) end<-----
8761 00:22:36.914170
8762 00:22:36.914282 ==
8763 00:22:36.917399 Dram Type= 6, Freq= 0, CH_1, rank 1
8764 00:22:36.920776 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8765 00:22:36.920941 ==
8766 00:22:36.924020 [Gating] SW mode calibration
8767 00:22:36.930778 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8768 00:22:36.937177 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8769 00:22:36.940764 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8770 00:22:36.944198 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8771 00:22:36.950580 1 4 8 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (1 1)
8772 00:22:36.954063 1 4 12 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
8773 00:22:36.957285 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8774 00:22:36.963812 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8775 00:22:36.967379 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8776 00:22:36.970384 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8777 00:22:36.977057 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8778 00:22:36.980318 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8779 00:22:36.983824 1 5 8 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 0)
8780 00:22:36.990700 1 5 12 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
8781 00:22:36.993449 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8782 00:22:36.996912 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8783 00:22:37.003674 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8784 00:22:37.006872 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8785 00:22:37.010250 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8786 00:22:37.017087 1 6 4 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
8787 00:22:37.020519 1 6 8 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
8788 00:22:37.023875 1 6 12 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)
8789 00:22:37.030193 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8790 00:22:37.033652 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8791 00:22:37.036814 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8792 00:22:37.043693 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8793 00:22:37.047167 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8794 00:22:37.049970 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8795 00:22:37.056533 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8796 00:22:37.059916 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8797 00:22:37.063344 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8798 00:22:37.070356 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8799 00:22:37.073549 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8800 00:22:37.076876 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8801 00:22:37.083214 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8802 00:22:37.086559 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8803 00:22:37.090074 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8804 00:22:37.096355 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8805 00:22:37.099781 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 00:22:37.103142 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 00:22:37.109986 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 00:22:37.113019 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 00:22:37.116241 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8810 00:22:37.123090 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 00:22:37.126412 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8812 00:22:37.129948 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8813 00:22:37.132800 Total UI for P1: 0, mck2ui 16
8814 00:22:37.136129 best dqsien dly found for B0: ( 1, 9, 8)
8815 00:22:37.139628 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8816 00:22:37.146134 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8817 00:22:37.149625 Total UI for P1: 0, mck2ui 16
8818 00:22:37.152559 best dqsien dly found for B1: ( 1, 9, 14)
8819 00:22:37.155904 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8820 00:22:37.159195 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8821 00:22:37.159265
8822 00:22:37.162512 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8823 00:22:37.165786 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8824 00:22:37.169181 [Gating] SW calibration Done
8825 00:22:37.169253 ==
8826 00:22:37.172411 Dram Type= 6, Freq= 0, CH_1, rank 1
8827 00:22:37.175890 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8828 00:22:37.175977 ==
8829 00:22:37.179281 RX Vref Scan: 0
8830 00:22:37.179368
8831 00:22:37.182632 RX Vref 0 -> 0, step: 1
8832 00:22:37.182701
8833 00:22:37.182759 RX Delay 0 -> 252, step: 8
8834 00:22:37.188981 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8835 00:22:37.192467 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8836 00:22:37.195691 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8837 00:22:37.198967 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8838 00:22:37.202495 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8839 00:22:37.208871 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8840 00:22:37.212147 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8841 00:22:37.215505 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8842 00:22:37.218986 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8843 00:22:37.222568 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8844 00:22:37.228959 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8845 00:22:37.232441 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8846 00:22:37.235802 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8847 00:22:37.239237 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8848 00:22:37.242015 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8849 00:22:37.248860 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8850 00:22:37.248938 ==
8851 00:22:37.252221 Dram Type= 6, Freq= 0, CH_1, rank 1
8852 00:22:37.255581 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8853 00:22:37.255666 ==
8854 00:22:37.255728 DQS Delay:
8855 00:22:37.259017 DQS0 = 0, DQS1 = 0
8856 00:22:37.259088 DQM Delay:
8857 00:22:37.262240 DQM0 = 131, DQM1 = 127
8858 00:22:37.262322 DQ Delay:
8859 00:22:37.265533 DQ0 =131, DQ1 =127, DQ2 =119, DQ3 =131
8860 00:22:37.268892 DQ4 =131, DQ5 =139, DQ6 =139, DQ7 =131
8861 00:22:37.272238 DQ8 =107, DQ9 =115, DQ10 =131, DQ11 =123
8862 00:22:37.275514 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =139
8863 00:22:37.275616
8864 00:22:37.278942
8865 00:22:37.279015 ==
8866 00:22:37.282448 Dram Type= 6, Freq= 0, CH_1, rank 1
8867 00:22:37.285083 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8868 00:22:37.285155 ==
8869 00:22:37.285221
8870 00:22:37.285278
8871 00:22:37.288461 TX Vref Scan disable
8872 00:22:37.288531 == TX Byte 0 ==
8873 00:22:37.295384 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8874 00:22:37.298710 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8875 00:22:37.298785 == TX Byte 1 ==
8876 00:22:37.305341 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8877 00:22:37.308733 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8878 00:22:37.308811 ==
8879 00:22:37.311537 Dram Type= 6, Freq= 0, CH_1, rank 1
8880 00:22:37.315020 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8881 00:22:37.315092 ==
8882 00:22:37.329741
8883 00:22:37.332962 TX Vref early break, caculate TX vref
8884 00:22:37.336513 TX Vref=16, minBit 11, minWin=22, winSum=382
8885 00:22:37.339649 TX Vref=18, minBit 0, minWin=23, winSum=397
8886 00:22:37.342951 TX Vref=20, minBit 0, minWin=24, winSum=403
8887 00:22:37.346422 TX Vref=22, minBit 0, minWin=25, winSum=413
8888 00:22:37.349559 TX Vref=24, minBit 0, minWin=25, winSum=419
8889 00:22:37.356443 TX Vref=26, minBit 0, minWin=25, winSum=419
8890 00:22:37.359895 TX Vref=28, minBit 1, minWin=25, winSum=426
8891 00:22:37.363257 TX Vref=30, minBit 1, minWin=25, winSum=420
8892 00:22:37.366488 TX Vref=32, minBit 8, minWin=24, winSum=411
8893 00:22:37.369818 TX Vref=34, minBit 0, minWin=24, winSum=405
8894 00:22:37.373071 TX Vref=36, minBit 0, minWin=24, winSum=395
8895 00:22:37.379907 [TxChooseVref] Worse bit 1, Min win 25, Win sum 426, Final Vref 28
8896 00:22:37.379992
8897 00:22:37.382647 Final TX Range 0 Vref 28
8898 00:22:37.382717
8899 00:22:37.382781 ==
8900 00:22:37.386039 Dram Type= 6, Freq= 0, CH_1, rank 1
8901 00:22:37.389397 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8902 00:22:37.389516 ==
8903 00:22:37.389628
8904 00:22:37.392715
8905 00:22:37.392828 TX Vref Scan disable
8906 00:22:37.399620 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8907 00:22:37.399749 == TX Byte 0 ==
8908 00:22:37.402573 u2DelayCellOfst[0]=18 cells (5 PI)
8909 00:22:37.405832 u2DelayCellOfst[1]=15 cells (4 PI)
8910 00:22:37.409243 u2DelayCellOfst[2]=0 cells (0 PI)
8911 00:22:37.412682 u2DelayCellOfst[3]=7 cells (2 PI)
8912 00:22:37.416077 u2DelayCellOfst[4]=7 cells (2 PI)
8913 00:22:37.419465 u2DelayCellOfst[5]=22 cells (6 PI)
8914 00:22:37.422324 u2DelayCellOfst[6]=22 cells (6 PI)
8915 00:22:37.425783 u2DelayCellOfst[7]=7 cells (2 PI)
8916 00:22:37.429155 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8917 00:22:37.432560 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8918 00:22:37.435767 == TX Byte 1 ==
8919 00:22:37.438958 u2DelayCellOfst[8]=0 cells (0 PI)
8920 00:22:37.442062 u2DelayCellOfst[9]=3 cells (1 PI)
8921 00:22:37.445705 u2DelayCellOfst[10]=11 cells (3 PI)
8922 00:22:37.445823 u2DelayCellOfst[11]=3 cells (1 PI)
8923 00:22:37.448930 u2DelayCellOfst[12]=15 cells (4 PI)
8924 00:22:37.452103 u2DelayCellOfst[13]=15 cells (4 PI)
8925 00:22:37.455762 u2DelayCellOfst[14]=18 cells (5 PI)
8926 00:22:37.459092 u2DelayCellOfst[15]=15 cells (4 PI)
8927 00:22:37.465284 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8928 00:22:37.468813 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8929 00:22:37.468909 DramC Write-DBI on
8930 00:22:37.469002 ==
8931 00:22:37.472072 Dram Type= 6, Freq= 0, CH_1, rank 1
8932 00:22:37.479162 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8933 00:22:37.479327 ==
8934 00:22:37.479439
8935 00:22:37.479542
8936 00:22:37.482055 TX Vref Scan disable
8937 00:22:37.482168 == TX Byte 0 ==
8938 00:22:37.489038 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8939 00:22:37.489152 == TX Byte 1 ==
8940 00:22:37.492061 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8941 00:22:37.495430 DramC Write-DBI off
8942 00:22:37.495546
8943 00:22:37.495644 [DATLAT]
8944 00:22:37.498959 Freq=1600, CH1 RK1
8945 00:22:37.499069
8946 00:22:37.499169 DATLAT Default: 0xf
8947 00:22:37.501812 0, 0xFFFF, sum = 0
8948 00:22:37.501907 1, 0xFFFF, sum = 0
8949 00:22:37.505267 2, 0xFFFF, sum = 0
8950 00:22:37.505337 3, 0xFFFF, sum = 0
8951 00:22:37.508511 4, 0xFFFF, sum = 0
8952 00:22:37.508585 5, 0xFFFF, sum = 0
8953 00:22:37.511743 6, 0xFFFF, sum = 0
8954 00:22:37.511814 7, 0xFFFF, sum = 0
8955 00:22:37.515347 8, 0xFFFF, sum = 0
8956 00:22:37.515417 9, 0xFFFF, sum = 0
8957 00:22:37.518757 10, 0xFFFF, sum = 0
8958 00:22:37.522155 11, 0xFFFF, sum = 0
8959 00:22:37.522235 12, 0xFFFF, sum = 0
8960 00:22:37.524975 13, 0x8FFF, sum = 0
8961 00:22:37.525041 14, 0x0, sum = 1
8962 00:22:37.528436 15, 0x0, sum = 2
8963 00:22:37.528499 16, 0x0, sum = 3
8964 00:22:37.531831 17, 0x0, sum = 4
8965 00:22:37.531896 best_step = 15
8966 00:22:37.531950
8967 00:22:37.532001 ==
8968 00:22:37.535222 Dram Type= 6, Freq= 0, CH_1, rank 1
8969 00:22:37.538544 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8970 00:22:37.538606 ==
8971 00:22:37.541667 RX Vref Scan: 0
8972 00:22:37.541728
8973 00:22:37.545354 RX Vref 0 -> 0, step: 1
8974 00:22:37.545416
8975 00:22:37.545476 RX Delay 3 -> 252, step: 4
8976 00:22:37.551806 iDelay=195, Bit 0, Center 132 (79 ~ 186) 108
8977 00:22:37.555250 iDelay=195, Bit 1, Center 128 (79 ~ 178) 100
8978 00:22:37.558605 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8979 00:22:37.561991 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8980 00:22:37.568543 iDelay=195, Bit 4, Center 124 (67 ~ 182) 116
8981 00:22:37.571866 iDelay=195, Bit 5, Center 140 (87 ~ 194) 108
8982 00:22:37.575035 iDelay=195, Bit 6, Center 140 (87 ~ 194) 108
8983 00:22:37.578484 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8984 00:22:37.581732 iDelay=195, Bit 8, Center 108 (51 ~ 166) 116
8985 00:22:37.585273 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8986 00:22:37.591409 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8987 00:22:37.594676 iDelay=195, Bit 11, Center 118 (63 ~ 174) 112
8988 00:22:37.598388 iDelay=195, Bit 12, Center 132 (75 ~ 190) 116
8989 00:22:37.601574 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8990 00:22:37.608138 iDelay=195, Bit 14, Center 132 (75 ~ 190) 116
8991 00:22:37.611521 iDelay=195, Bit 15, Center 134 (79 ~ 190) 112
8992 00:22:37.611625 ==
8993 00:22:37.614688 Dram Type= 6, Freq= 0, CH_1, rank 1
8994 00:22:37.618176 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8995 00:22:37.618274 ==
8996 00:22:37.621515 DQS Delay:
8997 00:22:37.621586 DQS0 = 0, DQS1 = 0
8998 00:22:37.621642 DQM Delay:
8999 00:22:37.624955 DQM0 = 128, DQM1 = 124
9000 00:22:37.625022 DQ Delay:
9001 00:22:37.628376 DQ0 =132, DQ1 =128, DQ2 =116, DQ3 =124
9002 00:22:37.631237 DQ4 =124, DQ5 =140, DQ6 =140, DQ7 =126
9003 00:22:37.634753 DQ8 =108, DQ9 =112, DQ10 =126, DQ11 =118
9004 00:22:37.641549 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =134
9005 00:22:37.641630
9006 00:22:37.641717
9007 00:22:37.641800
9008 00:22:37.644953 [DramC_TX_OE_Calibration] TA2
9009 00:22:37.645068 Original DQ_B0 (3 6) =30, OEN = 27
9010 00:22:37.648296 Original DQ_B1 (3 6) =30, OEN = 27
9011 00:22:37.651550 24, 0x0, End_B0=24 End_B1=24
9012 00:22:37.654767 25, 0x0, End_B0=25 End_B1=25
9013 00:22:37.657895 26, 0x0, End_B0=26 End_B1=26
9014 00:22:37.657972 27, 0x0, End_B0=27 End_B1=27
9015 00:22:37.661212 28, 0x0, End_B0=28 End_B1=28
9016 00:22:37.664652 29, 0x0, End_B0=29 End_B1=29
9017 00:22:37.668127 30, 0x0, End_B0=30 End_B1=30
9018 00:22:37.671544 31, 0x4141, End_B0=30 End_B1=30
9019 00:22:37.674632 Byte0 end_step=30 best_step=27
9020 00:22:37.674744 Byte1 end_step=30 best_step=27
9021 00:22:37.678041 Byte0 TX OE(2T, 0.5T) = (3, 3)
9022 00:22:37.681460 Byte1 TX OE(2T, 0.5T) = (3, 3)
9023 00:22:37.681554
9024 00:22:37.681643
9025 00:22:37.691145 [DQSOSCAuto] RK1, (LSB)MR18= 0xf1c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 402 ps
9026 00:22:37.691217 CH1 RK1: MR19=303, MR18=F1C
9027 00:22:37.697958 CH1_RK1: MR19=0x303, MR18=0xF1C, DQSOSC=395, MR23=63, INC=23, DEC=15
9028 00:22:37.700971 [RxdqsGatingPostProcess] freq 1600
9029 00:22:37.707672 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9030 00:22:37.710920 best DQS0 dly(2T, 0.5T) = (1, 1)
9031 00:22:37.714302 best DQS1 dly(2T, 0.5T) = (1, 1)
9032 00:22:37.718184 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9033 00:22:37.718299 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9034 00:22:37.721053 best DQS0 dly(2T, 0.5T) = (1, 1)
9035 00:22:37.724485 best DQS1 dly(2T, 0.5T) = (1, 1)
9036 00:22:37.727653 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9037 00:22:37.730898 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9038 00:22:37.734533 Pre-setting of DQS Precalculation
9039 00:22:37.740621 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9040 00:22:37.747572 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9041 00:22:37.754177 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9042 00:22:37.754300
9043 00:22:37.754403
9044 00:22:37.757616 [Calibration Summary] 3200 Mbps
9045 00:22:37.757729 CH 0, Rank 0
9046 00:22:37.760780 SW Impedance : PASS
9047 00:22:37.764084 DUTY Scan : NO K
9048 00:22:37.764193 ZQ Calibration : PASS
9049 00:22:37.767459 Jitter Meter : NO K
9050 00:22:37.770839 CBT Training : PASS
9051 00:22:37.770952 Write leveling : PASS
9052 00:22:37.774248 RX DQS gating : PASS
9053 00:22:37.777039 RX DQ/DQS(RDDQC) : PASS
9054 00:22:37.777152 TX DQ/DQS : PASS
9055 00:22:37.780756 RX DATLAT : PASS
9056 00:22:37.780869 RX DQ/DQS(Engine): PASS
9057 00:22:37.784213 TX OE : PASS
9058 00:22:37.784331 All Pass.
9059 00:22:37.784436
9060 00:22:37.787097 CH 0, Rank 1
9061 00:22:37.787206 SW Impedance : PASS
9062 00:22:37.790432 DUTY Scan : NO K
9063 00:22:37.793961 ZQ Calibration : PASS
9064 00:22:37.794068 Jitter Meter : NO K
9065 00:22:37.797402 CBT Training : PASS
9066 00:22:37.800759 Write leveling : PASS
9067 00:22:37.800869 RX DQS gating : PASS
9068 00:22:37.804011 RX DQ/DQS(RDDQC) : PASS
9069 00:22:37.807241 TX DQ/DQS : PASS
9070 00:22:37.807358 RX DATLAT : PASS
9071 00:22:37.810713 RX DQ/DQS(Engine): PASS
9072 00:22:37.813941 TX OE : PASS
9073 00:22:37.814053 All Pass.
9074 00:22:37.814164
9075 00:22:37.814266 CH 1, Rank 0
9076 00:22:37.817319 SW Impedance : PASS
9077 00:22:37.820328 DUTY Scan : NO K
9078 00:22:37.820433 ZQ Calibration : PASS
9079 00:22:37.823702 Jitter Meter : NO K
9080 00:22:37.827138 CBT Training : PASS
9081 00:22:37.827256 Write leveling : PASS
9082 00:22:37.830316 RX DQS gating : PASS
9083 00:22:37.830419 RX DQ/DQS(RDDQC) : PASS
9084 00:22:37.833592 TX DQ/DQS : PASS
9085 00:22:37.837312 RX DATLAT : PASS
9086 00:22:37.837425 RX DQ/DQS(Engine): PASS
9087 00:22:37.840278 TX OE : PASS
9088 00:22:37.840387 All Pass.
9089 00:22:37.840498
9090 00:22:37.843721 CH 1, Rank 1
9091 00:22:37.843842 SW Impedance : PASS
9092 00:22:37.846934 DUTY Scan : NO K
9093 00:22:37.850568 ZQ Calibration : PASS
9094 00:22:37.850678 Jitter Meter : NO K
9095 00:22:37.853792 CBT Training : PASS
9096 00:22:37.856918 Write leveling : PASS
9097 00:22:37.857039 RX DQS gating : PASS
9098 00:22:37.859980 RX DQ/DQS(RDDQC) : PASS
9099 00:22:37.863384 TX DQ/DQS : PASS
9100 00:22:37.863492 RX DATLAT : PASS
9101 00:22:37.867533 RX DQ/DQS(Engine): PASS
9102 00:22:37.870195 TX OE : PASS
9103 00:22:37.870315 All Pass.
9104 00:22:37.870417
9105 00:22:37.870527 DramC Write-DBI on
9106 00:22:37.873645 PER_BANK_REFRESH: Hybrid Mode
9107 00:22:37.877029 TX_TRACKING: ON
9108 00:22:37.883886 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9109 00:22:37.893268 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9110 00:22:37.900277 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9111 00:22:37.903702 [FAST_K] Save calibration result to emmc
9112 00:22:37.906962 sync common calibartion params.
9113 00:22:37.910251 sync cbt_mode0:1, 1:1
9114 00:22:37.910338 dram_init: ddr_geometry: 2
9115 00:22:37.913579 dram_init: ddr_geometry: 2
9116 00:22:37.916818 dram_init: ddr_geometry: 2
9117 00:22:37.916888 0:dram_rank_size:100000000
9118 00:22:37.920188 1:dram_rank_size:100000000
9119 00:22:37.926995 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9120 00:22:37.927083 DFS_SHUFFLE_HW_MODE: ON
9121 00:22:37.933236 dramc_set_vcore_voltage set vcore to 725000
9122 00:22:37.933323 Read voltage for 1600, 0
9123 00:22:37.936496 Vio18 = 0
9124 00:22:37.936565 Vcore = 725000
9125 00:22:37.936622 Vdram = 0
9126 00:22:37.939971 Vddq = 0
9127 00:22:37.940052 Vmddr = 0
9128 00:22:37.943283 switch to 3200 Mbps bootup
9129 00:22:37.943387 [DramcRunTimeConfig]
9130 00:22:37.943506 PHYPLL
9131 00:22:37.946634 DPM_CONTROL_AFTERK: ON
9132 00:22:37.949997 PER_BANK_REFRESH: ON
9133 00:22:37.950089 REFRESH_OVERHEAD_REDUCTION: ON
9134 00:22:37.953253 CMD_PICG_NEW_MODE: OFF
9135 00:22:37.956465 XRTWTW_NEW_MODE: ON
9136 00:22:37.956548 XRTRTR_NEW_MODE: ON
9137 00:22:37.960067 TX_TRACKING: ON
9138 00:22:37.960158 RDSEL_TRACKING: OFF
9139 00:22:37.962942 DQS Precalculation for DVFS: ON
9140 00:22:37.963029 RX_TRACKING: OFF
9141 00:22:37.966704 HW_GATING DBG: ON
9142 00:22:37.966799 ZQCS_ENABLE_LP4: ON
9143 00:22:37.969997 RX_PICG_NEW_MODE: ON
9144 00:22:37.973081 TX_PICG_NEW_MODE: ON
9145 00:22:37.973216 ENABLE_RX_DCM_DPHY: ON
9146 00:22:37.976346 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9147 00:22:37.979642 DUMMY_READ_FOR_TRACKING: OFF
9148 00:22:37.983388 !!! SPM_CONTROL_AFTERK: OFF
9149 00:22:37.983519 !!! SPM could not control APHY
9150 00:22:37.986406 IMPEDANCE_TRACKING: ON
9151 00:22:37.989758 TEMP_SENSOR: ON
9152 00:22:37.989874 HW_SAVE_FOR_SR: OFF
9153 00:22:37.992931 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9154 00:22:37.996412 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9155 00:22:37.999951 Read ODT Tracking: ON
9156 00:22:38.000078 Refresh Rate DeBounce: ON
9157 00:22:38.002761 DFS_NO_QUEUE_FLUSH: ON
9158 00:22:38.006163 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9159 00:22:38.009574 ENABLE_DFS_RUNTIME_MRW: OFF
9160 00:22:38.009687 DDR_RESERVE_NEW_MODE: ON
9161 00:22:38.012768 MR_CBT_SWITCH_FREQ: ON
9162 00:22:38.016113 =========================
9163 00:22:38.034073 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9164 00:22:38.037370 dram_init: ddr_geometry: 2
9165 00:22:38.056021 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9166 00:22:38.059391 dram_init: dram init end (result: 0)
9167 00:22:38.065701 DRAM-K: Full calibration passed in 24593 msecs
9168 00:22:38.069119 MRC: failed to locate region type 0.
9169 00:22:38.069197 DRAM rank0 size:0x100000000,
9170 00:22:38.072388 DRAM rank1 size=0x100000000
9171 00:22:38.082556 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9172 00:22:38.088598 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9173 00:22:38.095753 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9174 00:22:38.101892 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9175 00:22:38.105417 DRAM rank0 size:0x100000000,
9176 00:22:38.108927 DRAM rank1 size=0x100000000
9177 00:22:38.109005 CBMEM:
9178 00:22:38.112047 IMD: root @ 0xfffff000 254 entries.
9179 00:22:38.115398 IMD: root @ 0xffffec00 62 entries.
9180 00:22:38.118678 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9181 00:22:38.122114 WARNING: RO_VPD is uninitialized or empty.
9182 00:22:38.128763 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9183 00:22:38.135629 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9184 00:22:38.148767 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9185 00:22:38.160038 BS: romstage times (exec / console): total (unknown) / 24052 ms
9186 00:22:38.160138
9187 00:22:38.160227
9188 00:22:38.169685 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9189 00:22:38.173123 ARM64: Exception handlers installed.
9190 00:22:38.176538 ARM64: Testing exception
9191 00:22:38.179793 ARM64: Done test exception
9192 00:22:38.179871 Enumerating buses...
9193 00:22:38.183451 Show all devs... Before device enumeration.
9194 00:22:38.186780 Root Device: enabled 1
9195 00:22:38.190063 CPU_CLUSTER: 0: enabled 1
9196 00:22:38.190153 CPU: 00: enabled 1
9197 00:22:38.193245 Compare with tree...
9198 00:22:38.193339 Root Device: enabled 1
9199 00:22:38.196625 CPU_CLUSTER: 0: enabled 1
9200 00:22:38.200037 CPU: 00: enabled 1
9201 00:22:38.200126 Root Device scanning...
9202 00:22:38.202892 scan_static_bus for Root Device
9203 00:22:38.206300 CPU_CLUSTER: 0 enabled
9204 00:22:38.209552 scan_static_bus for Root Device done
9205 00:22:38.213254 scan_bus: bus Root Device finished in 8 msecs
9206 00:22:38.213323 done
9207 00:22:38.219776 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9208 00:22:38.222753 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9209 00:22:38.229567 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9210 00:22:38.232763 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9211 00:22:38.235989 Allocating resources...
9212 00:22:38.239591 Reading resources...
9213 00:22:38.243051 Root Device read_resources bus 0 link: 0
9214 00:22:38.243154 DRAM rank0 size:0x100000000,
9215 00:22:38.245885 DRAM rank1 size=0x100000000
9216 00:22:38.249287 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9217 00:22:38.252699 CPU: 00 missing read_resources
9218 00:22:38.259513 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9219 00:22:38.262424 Root Device read_resources bus 0 link: 0 done
9220 00:22:38.262505 Done reading resources.
9221 00:22:38.269059 Show resources in subtree (Root Device)...After reading.
9222 00:22:38.272556 Root Device child on link 0 CPU_CLUSTER: 0
9223 00:22:38.275940 CPU_CLUSTER: 0 child on link 0 CPU: 00
9224 00:22:38.285531 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9225 00:22:38.285645 CPU: 00
9226 00:22:38.288911 Root Device assign_resources, bus 0 link: 0
9227 00:22:38.292080 CPU_CLUSTER: 0 missing set_resources
9228 00:22:38.298720 Root Device assign_resources, bus 0 link: 0 done
9229 00:22:38.298798 Done setting resources.
9230 00:22:38.305103 Show resources in subtree (Root Device)...After assigning values.
9231 00:22:38.308515 Root Device child on link 0 CPU_CLUSTER: 0
9232 00:22:38.311924 CPU_CLUSTER: 0 child on link 0 CPU: 00
9233 00:22:38.321643 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9234 00:22:38.321714 CPU: 00
9235 00:22:38.325047 Done allocating resources.
9236 00:22:38.331969 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9237 00:22:38.332042 Enabling resources...
9238 00:22:38.332102 done.
9239 00:22:38.338632 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9240 00:22:38.341869 Initializing devices...
9241 00:22:38.341936 Root Device init
9242 00:22:38.344930 init hardware done!
9243 00:22:38.344998 0x00000018: ctrlr->caps
9244 00:22:38.348346 52.000 MHz: ctrlr->f_max
9245 00:22:38.351647 0.400 MHz: ctrlr->f_min
9246 00:22:38.351721 0x40ff8080: ctrlr->voltages
9247 00:22:38.354774 sclk: 390625
9248 00:22:38.354839 Bus Width = 1
9249 00:22:38.354896 sclk: 390625
9250 00:22:38.358130 Bus Width = 1
9251 00:22:38.361635 Early init status = 3
9252 00:22:38.364495 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9253 00:22:38.368547 in-header: 03 fc 00 00 01 00 00 00
9254 00:22:38.371960 in-data: 00
9255 00:22:38.375400 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9256 00:22:38.381039 in-header: 03 fd 00 00 00 00 00 00
9257 00:22:38.384515 in-data:
9258 00:22:38.387891 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9259 00:22:38.391782 in-header: 03 fc 00 00 01 00 00 00
9260 00:22:38.395239 in-data: 00
9261 00:22:38.398629 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9262 00:22:38.404041 in-header: 03 fd 00 00 00 00 00 00
9263 00:22:38.407139 in-data:
9264 00:22:38.410307 [SSUSB] Setting up USB HOST controller...
9265 00:22:38.413914 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9266 00:22:38.417238 [SSUSB] phy power-on done.
9267 00:22:38.420675 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9268 00:22:38.426921 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9269 00:22:38.430413 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9270 00:22:38.437233 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9271 00:22:38.443561 read SPI 0x50eb0 0x2ad3: 1173 us, 9346 KB/s, 74.768 Mbps
9272 00:22:38.450444 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9273 00:22:38.456952 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9274 00:22:38.463552 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9275 00:22:38.466915 SPM: binary array size = 0x9dc
9276 00:22:38.470242 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9277 00:22:38.476885 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9278 00:22:38.483519 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9279 00:22:38.487086 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9280 00:22:38.493487 configure_display: Starting display init
9281 00:22:38.527101 anx7625_power_on_init: Init interface.
9282 00:22:38.530568 anx7625_disable_pd_protocol: Disabled PD feature.
9283 00:22:38.534036 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9284 00:22:38.561689 anx7625_start_dp_work: Secure OCM version=00
9285 00:22:38.565097 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9286 00:22:38.579764 sp_tx_get_edid_block: EDID Block = 1
9287 00:22:38.682223 Extracted contents:
9288 00:22:38.685587 header: 00 ff ff ff ff ff ff 00
9289 00:22:38.689135 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9290 00:22:38.691938 version: 01 04
9291 00:22:38.695806 basic params: 95 1f 11 78 0a
9292 00:22:38.698725 chroma info: 76 90 94 55 54 90 27 21 50 54
9293 00:22:38.702117 established: 00 00 00
9294 00:22:38.708627 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9295 00:22:38.712000 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9296 00:22:38.718663 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9297 00:22:38.724962 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9298 00:22:38.731747 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9299 00:22:38.734904 extensions: 00
9300 00:22:38.734977 checksum: fb
9301 00:22:38.735036
9302 00:22:38.741484 Manufacturer: IVO Model 57d Serial Number 0
9303 00:22:38.741556 Made week 0 of 2020
9304 00:22:38.744881 EDID version: 1.4
9305 00:22:38.744948 Digital display
9306 00:22:38.748431 6 bits per primary color channel
9307 00:22:38.748529 DisplayPort interface
9308 00:22:38.751243 Maximum image size: 31 cm x 17 cm
9309 00:22:38.754583 Gamma: 220%
9310 00:22:38.754647 Check DPMS levels
9311 00:22:38.761493 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9312 00:22:38.764776 First detailed timing is preferred timing
9313 00:22:38.764849 Established timings supported:
9314 00:22:38.768183 Standard timings supported:
9315 00:22:38.771056 Detailed timings
9316 00:22:38.774291 Hex of detail: 383680a07038204018303c0035ae10000019
9317 00:22:38.780977 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9318 00:22:38.784386 0780 0798 07c8 0820 hborder 0
9319 00:22:38.787760 0438 043b 0447 0458 vborder 0
9320 00:22:38.791258 -hsync -vsync
9321 00:22:38.791327 Did detailed timing
9322 00:22:38.797379 Hex of detail: 000000000000000000000000000000000000
9323 00:22:38.800756 Manufacturer-specified data, tag 0
9324 00:22:38.804150 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9325 00:22:38.807679 ASCII string: InfoVision
9326 00:22:38.811010 Hex of detail: 000000fe00523134304e574635205248200a
9327 00:22:38.813767 ASCII string: R140NWF5 RH
9328 00:22:38.813835 Checksum
9329 00:22:38.817189 Checksum: 0xfb (valid)
9330 00:22:38.820595 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9331 00:22:38.823951 DSI data_rate: 832800000 bps
9332 00:22:38.830518 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9333 00:22:38.833974 anx7625_parse_edid: pixelclock(138800).
9334 00:22:38.837348 hactive(1920), hsync(48), hfp(24), hbp(88)
9335 00:22:38.840720 vactive(1080), vsync(12), vfp(3), vbp(17)
9336 00:22:38.844039 anx7625_dsi_config: config dsi.
9337 00:22:38.850426 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9338 00:22:38.864425 anx7625_dsi_config: success to config DSI
9339 00:22:38.867511 anx7625_dp_start: MIPI phy setup OK.
9340 00:22:38.871062 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9341 00:22:38.874137 mtk_ddp_mode_set invalid vrefresh 60
9342 00:22:38.877309 main_disp_path_setup
9343 00:22:38.877376 ovl_layer_smi_id_en
9344 00:22:38.880775 ovl_layer_smi_id_en
9345 00:22:38.880850 ccorr_config
9346 00:22:38.880909 aal_config
9347 00:22:38.883963 gamma_config
9348 00:22:38.884027 postmask_config
9349 00:22:38.887441 dither_config
9350 00:22:38.890994 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9351 00:22:38.897276 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9352 00:22:38.900620 Root Device init finished in 555 msecs
9353 00:22:38.904076 CPU_CLUSTER: 0 init
9354 00:22:38.911055 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9355 00:22:38.913757 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9356 00:22:38.918619 APU_MBOX 0x190000b0 = 0x10001
9357 00:22:38.920562 APU_MBOX 0x190001b0 = 0x10001
9358 00:22:38.924046 APU_MBOX 0x190005b0 = 0x10001
9359 00:22:38.926960 APU_MBOX 0x190006b0 = 0x10001
9360 00:22:38.933570 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9361 00:22:38.943102 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9362 00:22:38.955684 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9363 00:22:38.962269 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9364 00:22:38.973979 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9365 00:22:38.982974 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9366 00:22:38.986288 CPU_CLUSTER: 0 init finished in 81 msecs
9367 00:22:38.989987 Devices initialized
9368 00:22:38.992933 Show all devs... After init.
9369 00:22:38.993007 Root Device: enabled 1
9370 00:22:38.996571 CPU_CLUSTER: 0: enabled 1
9371 00:22:38.999709 CPU: 00: enabled 1
9372 00:22:39.002740 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9373 00:22:39.006220 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9374 00:22:39.009456 ELOG: NV offset 0x57f000 size 0x1000
9375 00:22:39.016162 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9376 00:22:39.022747 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9377 00:22:39.026182 ELOG: Event(17) added with size 13 at 2024-06-21 00:22:39 UTC
9378 00:22:39.033018 out: cmd=0x121: 03 db 21 01 00 00 00 00
9379 00:22:39.035924 in-header: 03 68 00 00 2c 00 00 00
9380 00:22:39.046071 in-data: d5 72 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9381 00:22:39.052422 ELOG: Event(A1) added with size 10 at 2024-06-21 00:22:39 UTC
9382 00:22:39.059508 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9383 00:22:39.065568 ELOG: Event(A0) added with size 9 at 2024-06-21 00:22:39 UTC
9384 00:22:39.068975 elog_add_boot_reason: Logged dev mode boot
9385 00:22:39.072666 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9386 00:22:39.076090 Finalize devices...
9387 00:22:39.079290 Devices finalized
9388 00:22:39.082537 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9389 00:22:39.085687 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9390 00:22:39.089120 in-header: 03 07 00 00 08 00 00 00
9391 00:22:39.092538 in-data: aa e4 47 04 13 02 00 00
9392 00:22:39.095935 Chrome EC: UHEPI supported
9393 00:22:39.102041 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9394 00:22:39.105900 in-header: 03 a9 00 00 08 00 00 00
9395 00:22:39.109141 in-data: 84 60 60 08 00 00 00 00
9396 00:22:39.112157 ELOG: Event(91) added with size 10 at 2024-06-21 00:22:39 UTC
9397 00:22:39.119085 Chrome EC: clear events_b mask to 0x0000000020004000
9398 00:22:39.125541 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9399 00:22:39.129741 in-header: 03 fd 00 00 00 00 00 00
9400 00:22:39.129835 in-data:
9401 00:22:39.136341 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9402 00:22:39.139187 Writing coreboot table at 0xffe64000
9403 00:22:39.142605 0. 000000000010a000-0000000000113fff: RAMSTAGE
9404 00:22:39.146030 1. 0000000040000000-00000000400fffff: RAM
9405 00:22:39.152732 2. 0000000040100000-000000004032afff: RAMSTAGE
9406 00:22:39.155654 3. 000000004032b000-00000000545fffff: RAM
9407 00:22:39.159061 4. 0000000054600000-000000005465ffff: BL31
9408 00:22:39.162428 5. 0000000054660000-00000000ffe63fff: RAM
9409 00:22:39.168727 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9410 00:22:39.172081 7. 0000000100000000-000000023fffffff: RAM
9411 00:22:39.175402 Passing 5 GPIOs to payload:
9412 00:22:39.178634 NAME | PORT | POLARITY | VALUE
9413 00:22:39.181872 EC in RW | 0x000000aa | low | undefined
9414 00:22:39.188869 EC interrupt | 0x00000005 | low | undefined
9415 00:22:39.191684 TPM interrupt | 0x000000ab | high | undefined
9416 00:22:39.198444 SD card detect | 0x00000011 | high | undefined
9417 00:22:39.201871 speaker enable | 0x00000093 | high | undefined
9418 00:22:39.205199 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9419 00:22:39.208466 in-header: 03 f9 00 00 02 00 00 00
9420 00:22:39.211748 in-data: 02 00
9421 00:22:39.211821 ADC[4]: Raw value=893341 ID=7
9422 00:22:39.215271 ADC[3]: Raw value=213440 ID=1
9423 00:22:39.218563 RAM Code: 0x71
9424 00:22:39.221519 ADC[6]: Raw value=74722 ID=0
9425 00:22:39.221586 ADC[5]: Raw value=212330 ID=1
9426 00:22:39.224974 SKU Code: 0x1
9427 00:22:39.228107 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 93c5
9428 00:22:39.231750 coreboot table: 964 bytes.
9429 00:22:39.234935 IMD ROOT 0. 0xfffff000 0x00001000
9430 00:22:39.237951 IMD SMALL 1. 0xffffe000 0x00001000
9431 00:22:39.241552 RO MCACHE 2. 0xffffc000 0x00001104
9432 00:22:39.244953 CONSOLE 3. 0xfff7c000 0x00080000
9433 00:22:39.248040 FMAP 4. 0xfff7b000 0x00000452
9434 00:22:39.251345 TIME STAMP 5. 0xfff7a000 0x00000910
9435 00:22:39.254867 VBOOT WORK 6. 0xfff66000 0x00014000
9436 00:22:39.258318 RAMOOPS 7. 0xffe66000 0x00100000
9437 00:22:39.261667 COREBOOT 8. 0xffe64000 0x00002000
9438 00:22:39.264478 IMD small region:
9439 00:22:39.268032 IMD ROOT 0. 0xffffec00 0x00000400
9440 00:22:39.271345 VPD 1. 0xffffeb80 0x0000006c
9441 00:22:39.274744 MMC STATUS 2. 0xffffeb60 0x00000004
9442 00:22:39.278296 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9443 00:22:39.284326 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9444 00:22:39.325400 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9445 00:22:39.328687 Checking segment from ROM address 0x40100000
9446 00:22:39.332009 Checking segment from ROM address 0x4010001c
9447 00:22:39.338215 Loading segment from ROM address 0x40100000
9448 00:22:39.338313 code (compression=0)
9449 00:22:39.348202 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9450 00:22:39.354902 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9451 00:22:39.355001 it's not compressed!
9452 00:22:39.361655 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9453 00:22:39.368172 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9454 00:22:39.385641 Loading segment from ROM address 0x4010001c
9455 00:22:39.385723 Entry Point 0x80000000
9456 00:22:39.388911 Loaded segments
9457 00:22:39.392037 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9458 00:22:39.398656 Jumping to boot code at 0x80000000(0xffe64000)
9459 00:22:39.405143 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9460 00:22:39.411841 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9461 00:22:39.419864 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9462 00:22:39.423627 Checking segment from ROM address 0x40100000
9463 00:22:39.426473 Checking segment from ROM address 0x4010001c
9464 00:22:39.433394 Loading segment from ROM address 0x40100000
9465 00:22:39.433511 code (compression=1)
9466 00:22:39.439671 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9467 00:22:39.449903 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9468 00:22:39.450021 using LZMA
9469 00:22:39.458152 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9470 00:22:39.464984 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9471 00:22:39.468260 Loading segment from ROM address 0x4010001c
9472 00:22:39.468368 Entry Point 0x54601000
9473 00:22:39.472044 Loaded segments
9474 00:22:39.474859 NOTICE: MT8192 bl31_setup
9475 00:22:39.482004 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9476 00:22:39.485549 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9477 00:22:39.488980 WARNING: region 0:
9478 00:22:39.491800 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9479 00:22:39.491878 WARNING: region 1:
9480 00:22:39.498651 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9481 00:22:39.502173 WARNING: region 2:
9482 00:22:39.505416 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9483 00:22:39.508543 WARNING: region 3:
9484 00:22:39.512021 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9485 00:22:39.515040 WARNING: region 4:
9486 00:22:39.521677 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9487 00:22:39.521755 WARNING: region 5:
9488 00:22:39.525043 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9489 00:22:39.528259 WARNING: region 6:
9490 00:22:39.531650 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9491 00:22:39.535043 WARNING: region 7:
9492 00:22:39.538325 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9493 00:22:39.545045 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9494 00:22:39.548344 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9495 00:22:39.551629 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9496 00:22:39.558223 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9497 00:22:39.561747 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9498 00:22:39.568043 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9499 00:22:39.571473 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9500 00:22:39.574924 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9501 00:22:39.581580 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9502 00:22:39.584655 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9503 00:22:39.591204 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9504 00:22:39.594416 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9505 00:22:39.597818 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9506 00:22:39.604147 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9507 00:22:39.607520 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9508 00:22:39.610999 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9509 00:22:39.617570 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9510 00:22:39.620740 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9511 00:22:39.627381 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9512 00:22:39.631044 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9513 00:22:39.634098 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9514 00:22:39.640916 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9515 00:22:39.644355 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9516 00:22:39.650650 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9517 00:22:39.654066 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9518 00:22:39.657566 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9519 00:22:39.664003 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9520 00:22:39.667074 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9521 00:22:39.673605 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9522 00:22:39.677094 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9523 00:22:39.680597 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9524 00:22:39.686875 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9525 00:22:39.690223 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9526 00:22:39.693493 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9527 00:22:39.700546 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9528 00:22:39.703655 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9529 00:22:39.706939 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9530 00:22:39.710392 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9531 00:22:39.717027 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9532 00:22:39.720443 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9533 00:22:39.723607 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9534 00:22:39.726959 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9535 00:22:39.733298 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9536 00:22:39.736927 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9537 00:22:39.740088 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9538 00:22:39.743306 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9539 00:22:39.749866 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9540 00:22:39.753283 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9541 00:22:39.756757 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9542 00:22:39.763075 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9543 00:22:39.766661 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9544 00:22:39.773321 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9545 00:22:39.776453 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9546 00:22:39.782980 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9547 00:22:39.786309 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9548 00:22:39.789713 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9549 00:22:39.796581 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9550 00:22:39.799491 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9551 00:22:39.806379 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9552 00:22:39.809502 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9553 00:22:39.816037 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9554 00:22:39.819229 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9555 00:22:39.826014 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9556 00:22:39.829333 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9557 00:22:39.832707 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9558 00:22:39.839368 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9559 00:22:39.842514 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9560 00:22:39.848967 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9561 00:22:39.852427 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9562 00:22:39.859103 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9563 00:22:39.862526 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9564 00:22:39.865891 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9565 00:22:39.872167 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9566 00:22:39.875615 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9567 00:22:39.882577 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9568 00:22:39.885629 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9569 00:22:39.892171 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9570 00:22:39.895540 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9571 00:22:39.902476 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9572 00:22:39.905342 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9573 00:22:39.908730 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9574 00:22:39.915505 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9575 00:22:39.918734 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9576 00:22:39.925310 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9577 00:22:39.929002 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9578 00:22:39.935235 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9579 00:22:39.938690 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9580 00:22:39.942067 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9581 00:22:39.948686 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9582 00:22:39.952150 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9583 00:22:39.958945 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9584 00:22:39.961719 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9585 00:22:39.968370 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9586 00:22:39.971988 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9587 00:22:39.978620 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9588 00:22:39.981915 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9589 00:22:39.984864 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9590 00:22:39.991793 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9591 00:22:39.994938 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9592 00:22:39.998471 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9593 00:22:40.001873 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9594 00:22:40.008079 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9595 00:22:40.011465 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9596 00:22:40.018335 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9597 00:22:40.021742 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9598 00:22:40.025184 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9599 00:22:40.031618 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9600 00:22:40.034668 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9601 00:22:40.041693 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9602 00:22:40.044803 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9603 00:22:40.048117 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9604 00:22:40.054809 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9605 00:22:40.058028 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9606 00:22:40.064723 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9607 00:22:40.067556 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9608 00:22:40.070996 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9609 00:22:40.078260 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9610 00:22:40.080863 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9611 00:22:40.084078 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9612 00:22:40.090685 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9613 00:22:40.094091 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9614 00:22:40.097492 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9615 00:22:40.100880 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9616 00:22:40.107232 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9617 00:22:40.110745 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9618 00:22:40.113919 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9619 00:22:40.120618 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9620 00:22:40.124082 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9621 00:22:40.130232 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9622 00:22:40.133667 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9623 00:22:40.137161 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9624 00:22:40.143574 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9625 00:22:40.146677 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9626 00:22:40.153530 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9627 00:22:40.157075 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9628 00:22:40.163115 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9629 00:22:40.166911 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9630 00:22:40.169897 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9631 00:22:40.176621 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9632 00:22:40.180053 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9633 00:22:40.186366 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9634 00:22:40.189732 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9635 00:22:40.193239 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9636 00:22:40.199771 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9637 00:22:40.202923 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9638 00:22:40.206269 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9639 00:22:40.213043 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9640 00:22:40.216143 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9641 00:22:40.222534 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9642 00:22:40.225902 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9643 00:22:40.232885 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9644 00:22:40.235732 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9645 00:22:40.239157 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9646 00:22:40.246068 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9647 00:22:40.248859 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9648 00:22:40.255613 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9649 00:22:40.258856 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9650 00:22:40.262000 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9651 00:22:40.268668 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9652 00:22:40.272024 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9653 00:22:40.278591 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9654 00:22:40.281914 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9655 00:22:40.285309 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9656 00:22:40.292076 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9657 00:22:40.295556 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9658 00:22:40.298361 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9659 00:22:40.305027 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9660 00:22:40.308287 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9661 00:22:40.314974 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9662 00:22:40.318458 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9663 00:22:40.324548 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9664 00:22:40.328207 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9665 00:22:40.331217 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9666 00:22:40.337799 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9667 00:22:40.341190 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9668 00:22:40.348021 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9669 00:22:40.351419 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9670 00:22:40.354203 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9671 00:22:40.361159 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9672 00:22:40.364236 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9673 00:22:40.370792 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9674 00:22:40.373967 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9675 00:22:40.377676 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9676 00:22:40.384029 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9677 00:22:40.387544 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9678 00:22:40.393962 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9679 00:22:40.397450 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9680 00:22:40.400907 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9681 00:22:40.407246 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9682 00:22:40.410643 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9683 00:22:40.417326 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9684 00:22:40.420484 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9685 00:22:40.427107 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9686 00:22:40.430019 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9687 00:22:40.433360 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9688 00:22:40.439953 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9689 00:22:40.443225 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9690 00:22:40.450064 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9691 00:22:40.453511 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9692 00:22:40.459642 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9693 00:22:40.463125 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9694 00:22:40.466419 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9695 00:22:40.473098 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9696 00:22:40.476296 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9697 00:22:40.483035 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9698 00:22:40.486347 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9699 00:22:40.492690 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9700 00:22:40.496287 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9701 00:22:40.501560 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9702 00:22:40.506378 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9703 00:22:40.509276 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9704 00:22:40.516088 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9705 00:22:40.519557 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9706 00:22:40.525891 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9707 00:22:40.529203 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9708 00:22:40.532490 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9709 00:22:40.539077 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9710 00:22:40.541935 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9711 00:22:40.548887 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9712 00:22:40.551962 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9713 00:22:40.558560 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9714 00:22:40.562055 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9715 00:22:40.565457 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9716 00:22:40.571639 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9717 00:22:40.574920 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9718 00:22:40.581783 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9719 00:22:40.584997 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9720 00:22:40.591355 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9721 00:22:40.595261 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9722 00:22:40.598304 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9723 00:22:40.601517 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9724 00:22:40.608409 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9725 00:22:40.611739 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9726 00:22:40.614581 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9727 00:22:40.617961 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9728 00:22:40.624731 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9729 00:22:40.628210 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9730 00:22:40.634590 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9731 00:22:40.638029 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9732 00:22:40.640851 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9733 00:22:40.647564 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9734 00:22:40.651105 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9735 00:22:40.657409 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9736 00:22:40.660560 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9737 00:22:40.664062 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9738 00:22:40.670664 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9739 00:22:40.674099 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9740 00:22:40.677078 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9741 00:22:40.683982 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9742 00:22:40.687312 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9743 00:22:40.690670 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9744 00:22:40.697009 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9745 00:22:40.700555 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9746 00:22:40.706994 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9747 00:22:40.710495 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9748 00:22:40.713576 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9749 00:22:40.720250 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9750 00:22:40.723621 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9751 00:22:40.726541 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9752 00:22:40.733369 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9753 00:22:40.736760 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9754 00:22:40.743181 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9755 00:22:40.746659 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9756 00:22:40.749989 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9757 00:22:40.756022 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9758 00:22:40.759547 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9759 00:22:40.765937 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9760 00:22:40.769240 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9761 00:22:40.772936 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9762 00:22:40.775884 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9763 00:22:40.782589 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9764 00:22:40.785914 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9765 00:22:40.789088 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9766 00:22:40.792979 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9767 00:22:40.798969 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9768 00:22:40.802313 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9769 00:22:40.805542 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9770 00:22:40.809215 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9771 00:22:40.815646 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9772 00:22:40.818936 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9773 00:22:40.821947 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9774 00:22:40.828754 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9775 00:22:40.832312 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9776 00:22:40.835791 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9777 00:22:40.841968 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9778 00:22:40.845431 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9779 00:22:40.852240 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9780 00:22:40.855182 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9781 00:22:40.862101 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9782 00:22:40.864850 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9783 00:22:40.868617 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9784 00:22:40.875179 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9785 00:22:40.878202 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9786 00:22:40.884718 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9787 00:22:40.887794 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9788 00:22:40.894876 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9789 00:22:40.898094 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9790 00:22:40.901054 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9791 00:22:40.907851 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9792 00:22:40.911008 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9793 00:22:40.917586 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9794 00:22:40.920936 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9795 00:22:40.924481 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9796 00:22:40.930994 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9797 00:22:40.933916 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9798 00:22:40.940880 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9799 00:22:40.943731 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9800 00:22:40.947188 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9801 00:22:40.953970 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9802 00:22:40.956881 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9803 00:22:40.963599 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9804 00:22:40.967050 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9805 00:22:40.973977 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9806 00:22:40.977133 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9807 00:22:40.980411 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9808 00:22:40.986963 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9809 00:22:40.989917 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9810 00:22:40.996477 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9811 00:22:40.999676 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9812 00:22:41.006449 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9813 00:22:41.009850 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9814 00:22:41.013272 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9815 00:22:41.019496 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9816 00:22:41.023154 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9817 00:22:41.029690 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9818 00:22:41.032877 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9819 00:22:41.039564 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9820 00:22:41.042972 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9821 00:22:41.045903 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9822 00:22:41.052877 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9823 00:22:41.055602 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9824 00:22:41.062417 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9825 00:22:41.065679 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9826 00:22:41.069106 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9827 00:22:41.075787 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9828 00:22:41.079251 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9829 00:22:41.085713 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9830 00:22:41.089040 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9831 00:22:41.092316 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9832 00:22:41.098897 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9833 00:22:41.102353 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9834 00:22:41.108780 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9835 00:22:41.111977 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9836 00:22:41.118247 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9837 00:22:41.122080 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9838 00:22:41.125055 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9839 00:22:41.131948 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9840 00:22:41.134868 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9841 00:22:41.141553 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9842 00:22:41.145107 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9843 00:22:41.151465 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9844 00:22:41.154891 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9845 00:22:41.158312 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9846 00:22:41.164695 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9847 00:22:41.168068 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9848 00:22:41.174357 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9849 00:22:41.177763 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9850 00:22:41.184637 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9851 00:22:41.187454 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9852 00:22:41.194144 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9853 00:22:41.197528 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9854 00:22:41.200872 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9855 00:22:41.207313 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9856 00:22:41.210818 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9857 00:22:41.217253 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9858 00:22:41.220931 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9859 00:22:41.227186 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9860 00:22:41.230621 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9861 00:22:41.233895 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9862 00:22:41.240816 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9863 00:22:41.243798 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9864 00:22:41.250085 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9865 00:22:41.253907 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9866 00:22:41.260325 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9867 00:22:41.263935 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9868 00:22:41.270038 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9869 00:22:41.273395 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9870 00:22:41.276870 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9871 00:22:41.283687 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9872 00:22:41.286509 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9873 00:22:41.293381 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9874 00:22:41.296760 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9875 00:22:41.303046 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9876 00:22:41.306464 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9877 00:22:41.313248 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9878 00:22:41.316611 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9879 00:22:41.319573 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9880 00:22:41.326375 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9881 00:22:41.329810 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9882 00:22:41.336410 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9883 00:22:41.339558 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9884 00:22:41.346412 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9885 00:22:41.349688 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9886 00:22:41.352794 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9887 00:22:41.359659 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9888 00:22:41.362914 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9889 00:22:41.369203 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9890 00:22:41.372658 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9891 00:22:41.378728 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9892 00:22:41.382174 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9893 00:22:41.389038 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9894 00:22:41.392004 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9895 00:22:41.395416 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9896 00:22:41.402241 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9897 00:22:41.405552 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9898 00:22:41.411956 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9899 00:22:41.415313 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9900 00:22:41.422192 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9901 00:22:41.425613 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9902 00:22:41.431956 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9903 00:22:41.435279 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9904 00:22:41.441561 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9905 00:22:41.444920 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9906 00:22:41.452032 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9907 00:22:41.454863 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9908 00:22:41.461410 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9909 00:22:41.464955 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9910 00:22:41.471354 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9911 00:22:41.474945 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9912 00:22:41.481605 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9913 00:22:41.485162 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9914 00:22:41.488431 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9915 00:22:41.494594 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9916 00:22:41.501416 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9917 00:22:41.504747 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9918 00:22:41.511095 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9919 00:22:41.514409 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9920 00:22:41.521301 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9921 00:22:41.524698 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9922 00:22:41.531026 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9923 00:22:41.534272 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9924 00:22:41.540889 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9925 00:22:41.544269 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9926 00:22:41.550889 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9927 00:22:41.554167 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9928 00:22:41.557252 INFO: [APUAPC] vio 0
9929 00:22:41.560805 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9930 00:22:41.567265 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9931 00:22:41.567364 INFO: [APUAPC] D0_APC_0: 0x400510
9932 00:22:41.570608 INFO: [APUAPC] D0_APC_1: 0x0
9933 00:22:41.573863 INFO: [APUAPC] D0_APC_2: 0x1540
9934 00:22:41.576961 INFO: [APUAPC] D0_APC_3: 0x0
9935 00:22:41.580349 INFO: [APUAPC] D1_APC_0: 0xffffffff
9936 00:22:41.583793 INFO: [APUAPC] D1_APC_1: 0xffffffff
9937 00:22:41.587344 INFO: [APUAPC] D1_APC_2: 0x3fffff
9938 00:22:41.590421 INFO: [APUAPC] D1_APC_3: 0x0
9939 00:22:41.593919 INFO: [APUAPC] D2_APC_0: 0xffffffff
9940 00:22:41.596974 INFO: [APUAPC] D2_APC_1: 0xffffffff
9941 00:22:41.600337 INFO: [APUAPC] D2_APC_2: 0x3fffff
9942 00:22:41.603709 INFO: [APUAPC] D2_APC_3: 0x0
9943 00:22:41.607133 INFO: [APUAPC] D3_APC_0: 0xffffffff
9944 00:22:41.610537 INFO: [APUAPC] D3_APC_1: 0xffffffff
9945 00:22:41.613923 INFO: [APUAPC] D3_APC_2: 0x3fffff
9946 00:22:41.616879 INFO: [APUAPC] D3_APC_3: 0x0
9947 00:22:41.620327 INFO: [APUAPC] D4_APC_0: 0xffffffff
9948 00:22:41.623634 INFO: [APUAPC] D4_APC_1: 0xffffffff
9949 00:22:41.626999 INFO: [APUAPC] D4_APC_2: 0x3fffff
9950 00:22:41.630393 INFO: [APUAPC] D4_APC_3: 0x0
9951 00:22:41.633245 INFO: [APUAPC] D5_APC_0: 0xffffffff
9952 00:22:41.636723 INFO: [APUAPC] D5_APC_1: 0xffffffff
9953 00:22:41.640078 INFO: [APUAPC] D5_APC_2: 0x3fffff
9954 00:22:41.643404 INFO: [APUAPC] D5_APC_3: 0x0
9955 00:22:41.646954 INFO: [APUAPC] D6_APC_0: 0xffffffff
9956 00:22:41.650068 INFO: [APUAPC] D6_APC_1: 0xffffffff
9957 00:22:41.653487 INFO: [APUAPC] D6_APC_2: 0x3fffff
9958 00:22:41.656905 INFO: [APUAPC] D6_APC_3: 0x0
9959 00:22:41.660296 INFO: [APUAPC] D7_APC_0: 0xffffffff
9960 00:22:41.663505 INFO: [APUAPC] D7_APC_1: 0xffffffff
9961 00:22:41.666556 INFO: [APUAPC] D7_APC_2: 0x3fffff
9962 00:22:41.670184 INFO: [APUAPC] D7_APC_3: 0x0
9963 00:22:41.673181 INFO: [APUAPC] D8_APC_0: 0xffffffff
9964 00:22:41.676911 INFO: [APUAPC] D8_APC_1: 0xffffffff
9965 00:22:41.679742 INFO: [APUAPC] D8_APC_2: 0x3fffff
9966 00:22:41.682988 INFO: [APUAPC] D8_APC_3: 0x0
9967 00:22:41.686301 INFO: [APUAPC] D9_APC_0: 0xffffffff
9968 00:22:41.689939 INFO: [APUAPC] D9_APC_1: 0xffffffff
9969 00:22:41.693347 INFO: [APUAPC] D9_APC_2: 0x3fffff
9970 00:22:41.693419 INFO: [APUAPC] D9_APC_3: 0x0
9971 00:22:41.699795 INFO: [APUAPC] D10_APC_0: 0xffffffff
9972 00:22:41.703178 INFO: [APUAPC] D10_APC_1: 0xffffffff
9973 00:22:41.706113 INFO: [APUAPC] D10_APC_2: 0x3fffff
9974 00:22:41.709640 INFO: [APUAPC] D10_APC_3: 0x0
9975 00:22:41.713100 INFO: [APUAPC] D11_APC_0: 0xffffffff
9976 00:22:41.716502 INFO: [APUAPC] D11_APC_1: 0xffffffff
9977 00:22:41.719377 INFO: [APUAPC] D11_APC_2: 0x3fffff
9978 00:22:41.722820 INFO: [APUAPC] D11_APC_3: 0x0
9979 00:22:41.726234 INFO: [APUAPC] D12_APC_0: 0xffffffff
9980 00:22:41.729758 INFO: [APUAPC] D12_APC_1: 0xffffffff
9981 00:22:41.732657 INFO: [APUAPC] D12_APC_2: 0x3fffff
9982 00:22:41.736089 INFO: [APUAPC] D12_APC_3: 0x0
9983 00:22:41.739539 INFO: [APUAPC] D13_APC_0: 0xffffffff
9984 00:22:41.742477 INFO: [APUAPC] D13_APC_1: 0xffffffff
9985 00:22:41.745913 INFO: [APUAPC] D13_APC_2: 0x3fffff
9986 00:22:41.749287 INFO: [APUAPC] D13_APC_3: 0x0
9987 00:22:41.752515 INFO: [APUAPC] D14_APC_0: 0xffffffff
9988 00:22:41.755803 INFO: [APUAPC] D14_APC_1: 0xffffffff
9989 00:22:41.759482 INFO: [APUAPC] D14_APC_2: 0x3fffff
9990 00:22:41.762395 INFO: [APUAPC] D14_APC_3: 0x0
9991 00:22:41.765975 INFO: [APUAPC] D15_APC_0: 0xffffffff
9992 00:22:41.768799 INFO: [APUAPC] D15_APC_1: 0xffffffff
9993 00:22:41.772269 INFO: [APUAPC] D15_APC_2: 0x3fffff
9994 00:22:41.775534 INFO: [APUAPC] D15_APC_3: 0x0
9995 00:22:41.778837 INFO: [APUAPC] APC_CON: 0x4
9996 00:22:41.778932 INFO: [NOCDAPC] D0_APC_0: 0x0
9997 00:22:41.782305 INFO: [NOCDAPC] D0_APC_1: 0x0
9998 00:22:41.785875 INFO: [NOCDAPC] D1_APC_0: 0x0
9999 00:22:41.789025 INFO: [NOCDAPC] D1_APC_1: 0xfff
10000 00:22:41.791954 INFO: [NOCDAPC] D2_APC_0: 0x0
10001 00:22:41.795261 INFO: [NOCDAPC] D2_APC_1: 0xfff
10002 00:22:41.799035 INFO: [NOCDAPC] D3_APC_0: 0x0
10003 00:22:41.802100 INFO: [NOCDAPC] D3_APC_1: 0xfff
10004 00:22:41.805540 INFO: [NOCDAPC] D4_APC_0: 0x0
10005 00:22:41.808445 INFO: [NOCDAPC] D4_APC_1: 0xfff
10006 00:22:41.811895 INFO: [NOCDAPC] D5_APC_0: 0x0
10007 00:22:41.815334 INFO: [NOCDAPC] D5_APC_1: 0xfff
10008 00:22:41.815445 INFO: [NOCDAPC] D6_APC_0: 0x0
10009 00:22:41.818323 INFO: [NOCDAPC] D6_APC_1: 0xfff
10010 00:22:41.821908 INFO: [NOCDAPC] D7_APC_0: 0x0
10011 00:22:41.825196 INFO: [NOCDAPC] D7_APC_1: 0xfff
10012 00:22:41.828700 INFO: [NOCDAPC] D8_APC_0: 0x0
10013 00:22:41.831553 INFO: [NOCDAPC] D8_APC_1: 0xfff
10014 00:22:41.835048 INFO: [NOCDAPC] D9_APC_0: 0x0
10015 00:22:41.838494 INFO: [NOCDAPC] D9_APC_1: 0xfff
10016 00:22:41.841914 INFO: [NOCDAPC] D10_APC_0: 0x0
10017 00:22:41.844733 INFO: [NOCDAPC] D10_APC_1: 0xfff
10018 00:22:41.848146 INFO: [NOCDAPC] D11_APC_0: 0x0
10019 00:22:41.851567 INFO: [NOCDAPC] D11_APC_1: 0xfff
10020 00:22:41.854966 INFO: [NOCDAPC] D12_APC_0: 0x0
10021 00:22:41.855080 INFO: [NOCDAPC] D12_APC_1: 0xfff
10022 00:22:41.858151 INFO: [NOCDAPC] D13_APC_0: 0x0
10023 00:22:41.861452 INFO: [NOCDAPC] D13_APC_1: 0xfff
10024 00:22:41.864694 INFO: [NOCDAPC] D14_APC_0: 0x0
10025 00:22:41.868040 INFO: [NOCDAPC] D14_APC_1: 0xfff
10026 00:22:41.871499 INFO: [NOCDAPC] D15_APC_0: 0x0
10027 00:22:41.874355 INFO: [NOCDAPC] D15_APC_1: 0xfff
10028 00:22:41.877791 INFO: [NOCDAPC] APC_CON: 0x4
10029 00:22:41.881195 INFO: [APUAPC] set_apusys_apc done
10030 00:22:41.884698 INFO: [DEVAPC] devapc_init done
10031 00:22:41.887779 INFO: GICv3 without legacy support detected.
10032 00:22:41.891073 INFO: ARM GICv3 driver initialized in EL3
10033 00:22:41.897877 INFO: Maximum SPI INTID supported: 639
10034 00:22:41.900937 INFO: BL31: Initializing runtime services
10035 00:22:41.907429 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10036 00:22:41.907542 INFO: SPM: enable CPC mode
10037 00:22:41.914148 INFO: mcdi ready for mcusys-off-idle and system suspend
10038 00:22:41.917273 INFO: BL31: Preparing for EL3 exit to normal world
10039 00:22:41.921082 INFO: Entry point address = 0x80000000
10040 00:22:41.923908 INFO: SPSR = 0x8
10041 00:22:41.930219
10042 00:22:41.930330
10043 00:22:41.930433
10044 00:22:41.933290 Starting depthcharge on Spherion...
10045 00:22:41.933369
10046 00:22:41.933430 Wipe memory regions:
10047 00:22:41.933487
10048 00:22:41.934097 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
10049 00:22:41.934189 start: 2.2.4 bootloader-commands (timeout 00:04:27) [common]
10050 00:22:41.934268 Setting prompt string to ['asurada:']
10051 00:22:41.934347 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:27)
10052 00:22:41.936512 [0x00000040000000, 0x00000054600000)
10053 00:22:42.059498
10054 00:22:42.059644 [0x00000054660000, 0x00000080000000)
10055 00:22:42.319441
10056 00:22:42.319599 [0x000000821a7280, 0x000000ffe64000)
10057 00:22:43.064550
10058 00:22:43.064691 [0x00000100000000, 0x00000240000000)
10059 00:22:44.954604
10060 00:22:44.957453 Initializing XHCI USB controller at 0x11200000.
10061 00:22:45.997014
10062 00:22:45.999887 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10063 00:22:45.999988
10064 00:22:46.000066
10065 00:22:46.000355 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10067 00:22:46.100667 asurada: tftpboot 192.168.201.1 14479141/tftp-deploy-0vfhrgoz/kernel/image.itb 14479141/tftp-deploy-0vfhrgoz/kernel/cmdline
10068 00:22:46.100860 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10069 00:22:46.100956 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:23)
10070 00:22:46.104682 tftpboot 192.168.201.1 14479141/tftp-deploy-0vfhrgoz/kernel/image.ittp-deploy-0vfhrgoz/kernel/cmdline
10071 00:22:46.104784
10072 00:22:46.104864 Waiting for link
10073 00:22:46.262812
10074 00:22:46.262932 R8152: Initializing
10075 00:22:46.263017
10076 00:22:46.266375 Version 6 (ocp_data = 5c30)
10077 00:22:46.266475
10078 00:22:46.269457 R8152: Done initializing
10079 00:22:46.269556
10080 00:22:46.269651 Adding net device
10081 00:22:48.176031
10082 00:22:48.176196 done.
10083 00:22:48.176304
10084 00:22:48.176436 MAC: 00:24:32:30:78:ff
10085 00:22:48.176552
10086 00:22:48.179464 Sending DHCP discover... done.
10087 00:22:48.179566
10088 00:22:48.182728 Waiting for reply... done.
10089 00:22:48.182833
10090 00:22:48.186207 Sending DHCP request... done.
10091 00:22:48.186291
10092 00:22:48.190351 Waiting for reply... done.
10093 00:22:48.190453
10094 00:22:48.190542 My ip is 192.168.201.21
10095 00:22:48.190628
10096 00:22:48.193791 The DHCP server ip is 192.168.201.1
10097 00:22:48.193870
10098 00:22:48.200820 TFTP server IP predefined by user: 192.168.201.1
10099 00:22:48.200899
10100 00:22:48.207268 Bootfile predefined by user: 14479141/tftp-deploy-0vfhrgoz/kernel/image.itb
10101 00:22:48.207349
10102 00:22:48.207410 Sending tftp read request... done.
10103 00:22:48.210230
10104 00:22:48.214297 Waiting for the transfer...
10105 00:22:48.214424
10106 00:22:48.750252 00000000 ################################################################
10107 00:22:48.750378
10108 00:22:49.325000 00080000 ################################################################
10109 00:22:49.325132
10110 00:22:49.898712 00100000 ################################################################
10111 00:22:49.898841
10112 00:22:50.450085 00180000 ################################################################
10113 00:22:50.450256
10114 00:22:51.000081 00200000 ################################################################
10115 00:22:51.000221
10116 00:22:51.558981 00280000 ################################################################
10117 00:22:51.559096
10118 00:22:52.123714 00300000 ################################################################
10119 00:22:52.123854
10120 00:22:52.674171 00380000 ################################################################
10121 00:22:52.674284
10122 00:22:53.213671 00400000 ################################################################
10123 00:22:53.213782
10124 00:22:53.787158 00480000 ################################################################
10125 00:22:53.787327
10126 00:22:54.352074 00500000 ################################################################
10127 00:22:54.352241
10128 00:22:54.897766 00580000 ################################################################
10129 00:22:54.897927
10130 00:22:55.464750 00600000 ################################################################
10131 00:22:55.464859
10132 00:22:56.013450 00680000 ################################################################
10133 00:22:56.013562
10134 00:22:56.551481 00700000 ################################################################
10135 00:22:56.551621
10136 00:22:57.101934 00780000 ################################################################
10137 00:22:57.102115
10138 00:22:57.666971 00800000 ################################################################
10139 00:22:57.667113
10140 00:22:58.201960 00880000 ################################################################
10141 00:22:58.202146
10142 00:22:58.730981 00900000 ################################################################
10143 00:22:58.731123
10144 00:22:59.261807 00980000 ################################################################
10145 00:22:59.261933
10146 00:22:59.791849 00a00000 ################################################################
10147 00:22:59.791965
10148 00:23:00.332244 00a80000 ################################################################
10149 00:23:00.332357
10150 00:23:00.874450 00b00000 ################################################################
10151 00:23:00.874577
10152 00:23:01.405258 00b80000 ################################################################
10153 00:23:01.405376
10154 00:23:01.943995 00c00000 ################################################################
10155 00:23:01.944159
10156 00:23:02.483473 00c80000 ################################################################
10157 00:23:02.483593
10158 00:23:03.093426 00d00000 ################################################################
10159 00:23:03.093567
10160 00:23:03.719680 00d80000 ################################################################
10161 00:23:03.719828
10162 00:23:04.297196 00e00000 ################################################################
10163 00:23:04.297380
10164 00:23:04.840165 00e80000 ################################################################
10165 00:23:04.840288
10166 00:23:05.377738 00f00000 ################################################################
10167 00:23:05.377855
10168 00:23:05.910823 00f80000 ################################################################
10169 00:23:05.910951
10170 00:23:06.444884 01000000 ################################################################
10171 00:23:06.445051
10172 00:23:06.977237 01080000 ################################################################
10173 00:23:06.977414
10174 00:23:07.504718 01100000 ################################################################
10175 00:23:07.504846
10176 00:23:08.032843 01180000 ################################################################
10177 00:23:08.032973
10178 00:23:08.558700 01200000 ################################################################
10179 00:23:08.558819
10180 00:23:09.082878 01280000 ################################################################
10181 00:23:09.082993
10182 00:23:09.607063 01300000 ################################################################
10183 00:23:09.607179
10184 00:23:10.137407 01380000 ################################################################
10185 00:23:10.137541
10186 00:23:10.681954 01400000 ################################################################
10187 00:23:10.682167
10188 00:23:11.213366 01480000 ################################################################
10189 00:23:11.213483
10190 00:23:11.763153 01500000 ################################################################
10191 00:23:11.763293
10192 00:23:12.315454 01580000 ################################################################
10193 00:23:12.315588
10194 00:23:12.856529 01600000 ################################################################
10195 00:23:12.856709
10196 00:23:13.381868 01680000 ################################################################
10197 00:23:13.382024
10198 00:23:13.920045 01700000 ################################################################
10199 00:23:13.920164
10200 00:23:14.440756 01780000 ################################################################
10201 00:23:14.440873
10202 00:23:14.964692 01800000 ################################################################
10203 00:23:14.964814
10204 00:23:15.502676 01880000 ################################################################
10205 00:23:15.502855
10206 00:23:16.035952 01900000 ################################################################
10207 00:23:16.036083
10208 00:23:16.573452 01980000 ################################################################
10209 00:23:16.573580
10210 00:23:17.110418 01a00000 ################################################################
10211 00:23:17.110544
10212 00:23:17.641969 01a80000 ################################################################
10213 00:23:17.642152
10214 00:23:18.173021 01b00000 ################################################################
10215 00:23:18.173205
10216 00:23:18.713363 01b80000 ################################################################
10217 00:23:18.713491
10218 00:23:19.274012 01c00000 ################################################################
10219 00:23:19.274142
10220 00:23:19.817398 01c80000 ################################################################
10221 00:23:19.817517
10222 00:23:20.344598 01d00000 ################################################################
10223 00:23:20.344773
10224 00:23:20.879540 01d80000 ################################################################
10225 00:23:20.879672
10226 00:23:21.424817 01e00000 ################################################################
10227 00:23:21.424965
10228 00:23:21.951154 01e80000 ################################################################
10229 00:23:21.951343
10230 00:23:22.489055 01f00000 ################################################################
10231 00:23:22.489230
10232 00:23:23.024148 01f80000 ################################################################
10233 00:23:23.024273
10234 00:23:23.552753 02000000 ################################################################
10235 00:23:23.552940
10236 00:23:24.076763 02080000 ################################################################
10237 00:23:24.076950
10238 00:23:24.613278 02100000 ################################################################
10239 00:23:24.613409
10240 00:23:25.152463 02180000 ################################################################
10241 00:23:25.152615
10242 00:23:25.695049 02200000 ################################################################
10243 00:23:25.695213
10244 00:23:26.238522 02280000 ################################################################
10245 00:23:26.238675
10246 00:23:26.785949 02300000 ################################################################
10247 00:23:26.786081
10248 00:23:27.330312 02380000 ################################################################
10249 00:23:27.330480
10250 00:23:27.875834 02400000 ################################################################
10251 00:23:27.876003
10252 00:23:28.415054 02480000 ################################################################
10253 00:23:28.415176
10254 00:23:28.947145 02500000 ################################################################
10255 00:23:28.947281
10256 00:23:29.502333 02580000 ################################################################
10257 00:23:29.502474
10258 00:23:30.066279 02600000 ################################################################
10259 00:23:30.066398
10260 00:23:30.603798 02680000 ################################################################
10261 00:23:30.603926
10262 00:23:31.149569 02700000 ################################################################
10263 00:23:31.149697
10264 00:23:31.682882 02780000 ################################################################
10265 00:23:31.683036
10266 00:23:32.213417 02800000 ################################################################
10267 00:23:32.213606
10268 00:23:32.737382 02880000 ################################################################
10269 00:23:32.737506
10270 00:23:33.279886 02900000 ################################################################
10271 00:23:33.280070
10272 00:23:33.831383 02980000 ################################################################
10273 00:23:33.831594
10274 00:23:34.381964 02a00000 ################################################################
10275 00:23:34.382084
10276 00:23:34.938130 02a80000 ################################################################
10277 00:23:34.938245
10278 00:23:35.510070 02b00000 ################################################################
10279 00:23:35.510186
10280 00:23:36.070130 02b80000 ################################################################
10281 00:23:36.070294
10282 00:23:36.635422 02c00000 ################################################################
10283 00:23:36.635597
10284 00:23:37.172906 02c80000 ################################################################
10285 00:23:37.173032
10286 00:23:37.721911 02d00000 ################################################################
10287 00:23:37.722033
10288 00:23:38.275545 02d80000 ################################################################
10289 00:23:38.275666
10290 00:23:38.803761 02e00000 ################################################################
10291 00:23:38.803938
10292 00:23:39.327088 02e80000 ################################################################
10293 00:23:39.327216
10294 00:23:39.854142 02f00000 ################################################################
10295 00:23:39.854273
10296 00:23:40.403357 02f80000 ################################################################
10297 00:23:40.403577
10298 00:23:40.965073 03000000 ################################################################
10299 00:23:40.965202
10300 00:23:41.505227 03080000 ################################################################
10301 00:23:41.505357
10302 00:23:42.050348 03100000 ################################################################
10303 00:23:42.050467
10304 00:23:42.608489 03180000 ################################################################
10305 00:23:42.608608
10306 00:23:43.159659 03200000 ################################################################
10307 00:23:43.159773
10308 00:23:43.700420 03280000 ################################################################
10309 00:23:43.700585
10310 00:23:44.250270 03300000 ################################################################
10311 00:23:44.250389
10312 00:23:44.791986 03380000 ################################################################
10313 00:23:44.792145
10314 00:23:45.331672 03400000 ################################################################
10315 00:23:45.331788
10316 00:23:45.900444 03480000 ################################################################
10317 00:23:45.900621
10318 00:23:46.431441 03500000 ################################################################
10319 00:23:46.431585
10320 00:23:46.970555 03580000 ################################################################
10321 00:23:46.970669
10322 00:23:47.503213 03600000 ################################################################
10323 00:23:47.503359
10324 00:23:48.032207 03680000 ################################################################
10325 00:23:48.032329
10326 00:23:48.572591 03700000 ################################################################
10327 00:23:48.572795
10328 00:23:49.119812 03780000 ################################################################
10329 00:23:49.119956
10330 00:23:49.669984 03800000 ################################################################
10331 00:23:49.670124
10332 00:23:50.209175 03880000 ################################################################
10333 00:23:50.209296
10334 00:23:50.742902 03900000 ################################################################
10335 00:23:50.743048
10336 00:23:51.277885 03980000 ################################################################
10337 00:23:51.278029
10338 00:23:51.833247 03a00000 ################################################################
10339 00:23:51.833367
10340 00:23:52.377803 03a80000 ################################################################
10341 00:23:52.377927
10342 00:23:52.913918 03b00000 ################################################################
10343 00:23:52.914060
10344 00:23:53.448833 03b80000 ################################################################
10345 00:23:53.448960
10346 00:23:53.993111 03c00000 ################################################################
10347 00:23:53.993354
10348 00:23:54.542648 03c80000 ################################################################
10349 00:23:54.542796
10350 00:23:55.082773 03d00000 ################################################################
10351 00:23:55.082912
10352 00:23:55.649203 03d80000 ################################################################
10353 00:23:55.649320
10354 00:23:56.193487 03e00000 ################################################################
10355 00:23:56.193613
10356 00:23:56.733761 03e80000 ################################################################
10357 00:23:56.733939
10358 00:23:57.284270 03f00000 ################################################################
10359 00:23:57.284386
10360 00:23:57.825870 03f80000 ################################################################
10361 00:23:57.826018
10362 00:23:58.364569 04000000 ################################################################
10363 00:23:58.364717
10364 00:23:58.899690 04080000 ################################################################
10365 00:23:58.899837
10366 00:23:59.441319 04100000 ################################################################
10367 00:23:59.441459
10368 00:24:00.551161 04180000 ################################################################
10369 00:24:00.551356
10370 00:24:00.551468 04200000 ################################################################
10371 00:24:00.551579
10372 00:24:01.042817 04280000 ################################################################
10373 00:24:01.042946
10374 00:24:01.599409 04300000 ################################################################
10375 00:24:01.599529
10376 00:24:02.141305 04380000 ################################################################
10377 00:24:02.141434
10378 00:24:02.679912 04400000 ################################################################
10379 00:24:02.680067
10380 00:24:03.209381 04480000 ################################################################
10381 00:24:03.209542
10382 00:24:03.740843 04500000 ################################################################
10383 00:24:03.741048
10384 00:24:04.267484 04580000 ################################################################
10385 00:24:04.267609
10386 00:24:04.786369 04600000 ################################################################
10387 00:24:04.786499
10388 00:24:05.059653 04680000 ################################## done.
10389 00:24:05.059836
10390 00:24:05.063004 The bootfile was 74200082 bytes long.
10391 00:24:05.063120
10392 00:24:05.066636 Sending tftp read request... done.
10393 00:24:05.066736
10394 00:24:05.066824 Waiting for the transfer...
10395 00:24:05.066908
10396 00:24:05.070026 00000000 # done.
10397 00:24:05.070122
10398 00:24:05.076364 Command line loaded dynamically from TFTP file: 14479141/tftp-deploy-0vfhrgoz/kernel/cmdline
10399 00:24:05.076445
10400 00:24:05.089512 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10401 00:24:05.089596
10402 00:24:05.093003 Loading FIT.
10403 00:24:05.093081
10404 00:24:05.096274 Image ramdisk-1 has 61025902 bytes.
10405 00:24:05.096353
10406 00:24:05.099699 Image fdt-1 has 47258 bytes.
10407 00:24:05.099777
10408 00:24:05.099837 Image kernel-1 has 13124896 bytes.
10409 00:24:05.102665
10410 00:24:05.109589 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10411 00:24:05.109673
10412 00:24:05.125814 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10413 00:24:05.129336
10414 00:24:05.132678 Choosing best match conf-1 for compat google,spherion-rev2.
10415 00:24:05.137160
10416 00:24:05.141795 Connected to device vid:did:rid of 1ae0:0028:00
10417 00:24:05.148614
10418 00:24:05.151744 tpm_get_response: command 0x17b, return code 0x0
10419 00:24:05.151822
10420 00:24:05.158854 ec_init: CrosEC protocol v3 supported (256, 248)
10421 00:24:05.158938
10422 00:24:05.161735 tpm_cleanup: add release locality here.
10423 00:24:05.161814
10424 00:24:05.164945 Shutting down all USB controllers.
10425 00:24:05.165024
10426 00:24:05.168480 Removing current net device
10427 00:24:05.168559
10428 00:24:05.171559 Exiting depthcharge with code 4 at timestamp: 112625503
10429 00:24:05.174773
10430 00:24:05.178206 LZMA decompressing kernel-1 to 0x821a6718
10431 00:24:05.178280
10432 00:24:05.181412 LZMA decompressing kernel-1 to 0x40000000
10433 00:24:06.797226
10434 00:24:06.797378 jumping to kernel
10435 00:24:06.797980 end: 2.2.4 bootloader-commands (duration 00:01:25) [common]
10436 00:24:06.798072 start: 2.2.5 auto-login-action (timeout 00:03:02) [common]
10437 00:24:06.798143 Setting prompt string to ['Linux version [0-9]']
10438 00:24:06.798215 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10439 00:24:06.798280 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10440 00:24:06.880330
10441 00:24:06.883621 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10442 00:24:06.887188 start: 2.2.5.1 login-action (timeout 00:03:02) [common]
10443 00:24:06.887350 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10444 00:24:06.887470 Setting prompt string to []
10445 00:24:06.887583 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10446 00:24:06.887681 Using line separator: #'\n'#
10447 00:24:06.887764 No login prompt set.
10448 00:24:06.887864 Parsing kernel messages
10449 00:24:06.887955 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10450 00:24:06.888131 [login-action] Waiting for messages, (timeout 00:03:02)
10451 00:24:06.888224 Waiting using forced prompt support (timeout 00:01:31)
10452 00:24:06.906349 [ 0.000000] Linux version 6.1.94-cip23 (KernelCI@build-j239242-arm64-gcc-10-defconfig-arm64-chromebook-c5lwc) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Jun 21 00:04:56 UTC 2024
10453 00:24:06.909934 [ 0.000000] random: crng init done
10454 00:24:06.916576 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10455 00:24:06.919959 [ 0.000000] efi: UEFI not found.
10456 00:24:06.926395 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10457 00:24:06.933241 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10458 00:24:06.943175 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10459 00:24:06.953146 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10460 00:24:06.959394 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10461 00:24:06.966140 [ 0.000000] printk: bootconsole [mtk8250] enabled
10462 00:24:06.972920 [ 0.000000] NUMA: No NUMA configuration found
10463 00:24:06.979516 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10464 00:24:06.982489 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10465 00:24:06.986014 [ 0.000000] Zone ranges:
10466 00:24:06.992927 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10467 00:24:06.995955 [ 0.000000] DMA32 empty
10468 00:24:07.002576 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10469 00:24:07.005704 [ 0.000000] Movable zone start for each node
10470 00:24:07.009285 [ 0.000000] Early memory node ranges
10471 00:24:07.015759 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10472 00:24:07.022237 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10473 00:24:07.029239 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10474 00:24:07.035895 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10475 00:24:07.042336 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10476 00:24:07.048857 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10477 00:24:07.104552 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10478 00:24:07.111081 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10479 00:24:07.117992 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10480 00:24:07.121458 [ 0.000000] psci: probing for conduit method from DT.
10481 00:24:07.127855 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10482 00:24:07.131284 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10483 00:24:07.137733 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10484 00:24:07.141268 [ 0.000000] psci: SMC Calling Convention v1.2
10485 00:24:07.147586 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10486 00:24:07.150913 [ 0.000000] Detected VIPT I-cache on CPU0
10487 00:24:07.157441 [ 0.000000] CPU features: detected: GIC system register CPU interface
10488 00:24:07.164242 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10489 00:24:07.171072 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10490 00:24:07.177663 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10491 00:24:07.187377 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10492 00:24:07.194079 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10493 00:24:07.197006 [ 0.000000] alternatives: applying boot alternatives
10494 00:24:07.203966 [ 0.000000] Fallback order for Node 0: 0
10495 00:24:07.210264 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10496 00:24:07.213796 [ 0.000000] Policy zone: Normal
10497 00:24:07.226712 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10498 00:24:07.236588 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10499 00:24:07.249361 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10500 00:24:07.259217 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10501 00:24:07.265771 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10502 00:24:07.268714 <6>[ 0.000000] software IO TLB: area num 8.
10503 00:24:07.326045 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10504 00:24:07.475225 <6>[ 0.000000] Memory: 7904468K/8385536K available (18112K kernel code, 4120K rwdata, 22648K rodata, 8512K init, 616K bss, 448300K reserved, 32768K cma-reserved)
10505 00:24:07.481734 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10506 00:24:07.488062 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10507 00:24:07.491733 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10508 00:24:07.497954 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10509 00:24:07.504585 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10510 00:24:07.507932 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10511 00:24:07.518150 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10512 00:24:07.524637 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10513 00:24:07.531208 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10514 00:24:07.537647 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10515 00:24:07.541198 <6>[ 0.000000] GICv3: 608 SPIs implemented
10516 00:24:07.544729 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10517 00:24:07.551205 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10518 00:24:07.554244 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10519 00:24:07.561080 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10520 00:24:07.574213 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10521 00:24:07.587864 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10522 00:24:07.594161 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10523 00:24:07.601677 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10524 00:24:07.614979 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10525 00:24:07.621668 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10526 00:24:07.628417 <6>[ 0.009181] Console: colour dummy device 80x25
10527 00:24:07.638437 <6>[ 0.013909] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10528 00:24:07.644831 <6>[ 0.024351] pid_max: default: 32768 minimum: 301
10529 00:24:07.648369 <6>[ 0.029222] LSM: Security Framework initializing
10530 00:24:07.654758 <6>[ 0.034161] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10531 00:24:07.664853 <6>[ 0.041975] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10532 00:24:07.671356 <6>[ 0.051393] cblist_init_generic: Setting adjustable number of callback queues.
10533 00:24:07.678094 <6>[ 0.058836] cblist_init_generic: Setting shift to 3 and lim to 1.
10534 00:24:07.688080 <6>[ 0.065173] cblist_init_generic: Setting adjustable number of callback queues.
10535 00:24:07.694473 <6>[ 0.072646] cblist_init_generic: Setting shift to 3 and lim to 1.
10536 00:24:07.697502 <6>[ 0.079088] rcu: Hierarchical SRCU implementation.
10537 00:24:07.704277 <6>[ 0.084104] rcu: Max phase no-delay instances is 1000.
10538 00:24:07.711214 <6>[ 0.091128] EFI services will not be available.
10539 00:24:07.714190 <6>[ 0.096087] smp: Bringing up secondary CPUs ...
10540 00:24:07.722530 <6>[ 0.101137] Detected VIPT I-cache on CPU1
10541 00:24:07.729042 <6>[ 0.101208] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10542 00:24:07.735738 <6>[ 0.101237] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10543 00:24:07.739235 <6>[ 0.101574] Detected VIPT I-cache on CPU2
10544 00:24:07.748697 <6>[ 0.101623] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10545 00:24:07.755706 <6>[ 0.101639] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10546 00:24:07.758634 <6>[ 0.101896] Detected VIPT I-cache on CPU3
10547 00:24:07.765152 <6>[ 0.101941] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10548 00:24:07.772176 <6>[ 0.101955] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10549 00:24:07.778737 <6>[ 0.102257] CPU features: detected: Spectre-v4
10550 00:24:07.782171 <6>[ 0.102263] CPU features: detected: Spectre-BHB
10551 00:24:07.785126 <6>[ 0.102268] Detected PIPT I-cache on CPU4
10552 00:24:07.791665 <6>[ 0.102326] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10553 00:24:07.801406 <6>[ 0.102343] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10554 00:24:07.804992 <6>[ 0.102637] Detected PIPT I-cache on CPU5
10555 00:24:07.811651 <6>[ 0.102700] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10556 00:24:07.818031 <6>[ 0.102716] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10557 00:24:07.821544 <6>[ 0.102995] Detected PIPT I-cache on CPU6
10558 00:24:07.831199 <6>[ 0.103060] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10559 00:24:07.837929 <6>[ 0.103077] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10560 00:24:07.841124 <6>[ 0.103375] Detected PIPT I-cache on CPU7
10561 00:24:07.847664 <6>[ 0.103442] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10562 00:24:07.854120 <6>[ 0.103458] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10563 00:24:07.857731 <6>[ 0.103505] smp: Brought up 1 node, 8 CPUs
10564 00:24:07.864174 <6>[ 0.244951] SMP: Total of 8 processors activated.
10565 00:24:07.870657 <6>[ 0.249872] CPU features: detected: 32-bit EL0 Support
10566 00:24:07.877662 <6>[ 0.255269] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10567 00:24:07.884129 <6>[ 0.264070] CPU features: detected: Common not Private translations
10568 00:24:07.890627 <6>[ 0.270545] CPU features: detected: CRC32 instructions
10569 00:24:07.897595 <6>[ 0.275930] CPU features: detected: RCpc load-acquire (LDAPR)
10570 00:24:07.900379 <6>[ 0.281890] CPU features: detected: LSE atomic instructions
10571 00:24:07.906923 <6>[ 0.287671] CPU features: detected: Privileged Access Never
10572 00:24:07.913873 <6>[ 0.293451] CPU features: detected: RAS Extension Support
10573 00:24:07.920582 <6>[ 0.299094] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10574 00:24:07.923756 <6>[ 0.306314] CPU: All CPU(s) started at EL2
10575 00:24:07.929956 <6>[ 0.310631] alternatives: applying system-wide alternatives
10576 00:24:07.940230 <6>[ 0.321522] devtmpfs: initialized
10577 00:24:07.952610 <6>[ 0.330475] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10578 00:24:07.963027 <6>[ 0.340431] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10579 00:24:07.969321 <6>[ 0.348665] pinctrl core: initialized pinctrl subsystem
10580 00:24:07.972883 <6>[ 0.355336] DMI not present or invalid.
10581 00:24:07.979314 <6>[ 0.359754] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10582 00:24:07.989277 <6>[ 0.366631] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10583 00:24:07.995962 <6>[ 0.374203] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10584 00:24:08.006302 <6>[ 0.382439] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10585 00:24:08.009240 <6>[ 0.390680] audit: initializing netlink subsys (disabled)
10586 00:24:08.019401 <5>[ 0.396374] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10587 00:24:08.026109 <6>[ 0.397085] thermal_sys: Registered thermal governor 'step_wise'
10588 00:24:08.032502 <6>[ 0.404342] thermal_sys: Registered thermal governor 'power_allocator'
10589 00:24:08.035841 <6>[ 0.410599] cpuidle: using governor menu
10590 00:24:08.042909 <6>[ 0.421558] NET: Registered PF_QIPCRTR protocol family
10591 00:24:08.049123 <6>[ 0.427034] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10592 00:24:08.052319 <6>[ 0.434136] ASID allocator initialised with 32768 entries
10593 00:24:08.059707 <6>[ 0.440716] Serial: AMBA PL011 UART driver
10594 00:24:08.068479 <4>[ 0.449543] Trying to register duplicate clock ID: 134
10595 00:24:08.128214 <6>[ 0.512494] KASLR enabled
10596 00:24:08.142354 <6>[ 0.520197] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10597 00:24:08.149324 <6>[ 0.527210] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10598 00:24:08.155763 <6>[ 0.533700] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10599 00:24:08.162261 <6>[ 0.540705] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10600 00:24:08.168498 <6>[ 0.547194] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10601 00:24:08.175393 <6>[ 0.554200] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10602 00:24:08.181841 <6>[ 0.560688] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10603 00:24:08.188729 <6>[ 0.567691] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10604 00:24:08.191654 <6>[ 0.575136] ACPI: Interpreter disabled.
10605 00:24:08.200288 <6>[ 0.581550] iommu: Default domain type: Translated
10606 00:24:08.206907 <6>[ 0.586700] iommu: DMA domain TLB invalidation policy: strict mode
10607 00:24:08.210257 <5>[ 0.593359] SCSI subsystem initialized
10608 00:24:08.217121 <6>[ 0.597609] usbcore: registered new interface driver usbfs
10609 00:24:08.223619 <6>[ 0.603342] usbcore: registered new interface driver hub
10610 00:24:08.226597 <6>[ 0.608894] usbcore: registered new device driver usb
10611 00:24:08.233965 <6>[ 0.615011] pps_core: LinuxPPS API ver. 1 registered
10612 00:24:08.243746 <6>[ 0.620205] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10613 00:24:08.247118 <6>[ 0.629549] PTP clock support registered
10614 00:24:08.250334 <6>[ 0.633791] EDAC MC: Ver: 3.0.0
10615 00:24:08.258065 <6>[ 0.638991] FPGA manager framework
10616 00:24:08.264483 <6>[ 0.642670] Advanced Linux Sound Architecture Driver Initialized.
10617 00:24:08.268017 <6>[ 0.649450] vgaarb: loaded
10618 00:24:08.274556 <6>[ 0.652604] clocksource: Switched to clocksource arch_sys_counter
10619 00:24:08.278110 <5>[ 0.659033] VFS: Disk quotas dquot_6.6.0
10620 00:24:08.284871 <6>[ 0.663215] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10621 00:24:08.288110 <6>[ 0.670409] pnp: PnP ACPI: disabled
10622 00:24:08.295975 <6>[ 0.677056] NET: Registered PF_INET protocol family
10623 00:24:08.305846 <6>[ 0.682646] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10624 00:24:08.317319 <6>[ 0.694964] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10625 00:24:08.326906 <6>[ 0.703783] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10626 00:24:08.333952 <6>[ 0.711753] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10627 00:24:08.343874 <6>[ 0.720458] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10628 00:24:08.350255 <6>[ 0.730211] TCP: Hash tables configured (established 65536 bind 65536)
10629 00:24:08.357069 <6>[ 0.737083] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10630 00:24:08.366358 <6>[ 0.744283] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10631 00:24:08.373357 <6>[ 0.751990] NET: Registered PF_UNIX/PF_LOCAL protocol family
10632 00:24:08.379705 <6>[ 0.758142] RPC: Registered named UNIX socket transport module.
10633 00:24:08.383010 <6>[ 0.764299] RPC: Registered udp transport module.
10634 00:24:08.389974 <6>[ 0.769233] RPC: Registered tcp transport module.
10635 00:24:08.396125 <6>[ 0.774167] RPC: Registered tcp NFSv4.1 backchannel transport module.
10636 00:24:08.399493 <6>[ 0.780835] PCI: CLS 0 bytes, default 64
10637 00:24:08.403146 <6>[ 0.785209] Unpacking initramfs...
10638 00:24:08.412809 <6>[ 0.788918] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10639 00:24:08.419297 <6>[ 0.797543] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10640 00:24:08.425734 <6>[ 0.806343] kvm [1]: IPA Size Limit: 40 bits
10641 00:24:08.429315 <6>[ 0.810867] kvm [1]: GICv3: no GICV resource entry
10642 00:24:08.435941 <6>[ 0.815891] kvm [1]: disabling GICv2 emulation
10643 00:24:08.438861 <6>[ 0.820578] kvm [1]: GIC system register CPU interface enabled
10644 00:24:08.445711 <6>[ 0.826737] kvm [1]: vgic interrupt IRQ18
10645 00:24:08.452483 <6>[ 0.832788] kvm [1]: VHE mode initialized successfully
10646 00:24:08.458993 <5>[ 0.839191] Initialise system trusted keyrings
10647 00:24:08.465162 <6>[ 0.844013] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10648 00:24:08.473207 <6>[ 0.854027] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10649 00:24:08.479759 <5>[ 0.860384] NFS: Registering the id_resolver key type
10650 00:24:08.482754 <5>[ 0.865697] Key type id_resolver registered
10651 00:24:08.489575 <5>[ 0.870114] Key type id_legacy registered
10652 00:24:08.496278 <6>[ 0.874395] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10653 00:24:08.502784 <6>[ 0.881318] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10654 00:24:08.509118 <6>[ 0.889031] 9p: Installing v9fs 9p2000 file system support
10655 00:24:08.546083 <5>[ 0.926927] Key type asymmetric registered
10656 00:24:08.549431 <5>[ 0.931254] Asymmetric key parser 'x509' registered
10657 00:24:08.559004 <6>[ 0.936385] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10658 00:24:08.562619 <6>[ 0.943997] io scheduler mq-deadline registered
10659 00:24:08.565365 <6>[ 0.948771] io scheduler kyber registered
10660 00:24:08.584368 <6>[ 0.965672] EINJ: ACPI disabled.
10661 00:24:08.617698 <4>[ 0.992049] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10662 00:24:08.627633 <4>[ 1.002662] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10663 00:24:08.642230 <6>[ 1.023471] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10664 00:24:08.650497 <6>[ 1.031376] printk: console [ttyS0] disabled
10665 00:24:08.678621 <6>[ 1.056003] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10666 00:24:08.685179 <6>[ 1.065476] printk: console [ttyS0] enabled
10667 00:24:08.688116 <6>[ 1.065476] printk: console [ttyS0] enabled
10668 00:24:08.695184 <6>[ 1.074370] printk: bootconsole [mtk8250] disabled
10669 00:24:08.698190 <6>[ 1.074370] printk: bootconsole [mtk8250] disabled
10670 00:24:08.704757 <6>[ 1.085353] SuperH (H)SCI(F) driver initialized
10671 00:24:08.708194 <6>[ 1.090620] msm_serial: driver initialized
10672 00:24:08.721936 <6>[ 1.099501] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10673 00:24:08.731527 <6>[ 1.108046] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10674 00:24:08.737938 <6>[ 1.116589] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10675 00:24:08.747819 <6>[ 1.125224] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10676 00:24:08.757876 <6>[ 1.133931] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10677 00:24:08.764854 <6>[ 1.142651] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10678 00:24:08.774428 <6>[ 1.151191] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10679 00:24:08.781126 <6>[ 1.159985] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10680 00:24:08.791098 <6>[ 1.168526] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10681 00:24:08.802469 <6>[ 1.183821] loop: module loaded
10682 00:24:08.809133 <6>[ 1.189838] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10683 00:24:08.831710 <4>[ 1.212501] mtk-pmic-keys: Failed to locate of_node [id: -1]
10684 00:24:08.838521 <6>[ 1.219331] megasas: 07.719.03.00-rc1
10685 00:24:08.848190 <6>[ 1.229113] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10686 00:24:08.854937 <6>[ 1.236018] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10687 00:24:08.872031 <6>[ 1.252591] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10688 00:24:08.927590 <6>[ 1.301981] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10689 00:24:11.113276 <6>[ 3.494540] Freeing initrd memory: 59588K
10690 00:24:11.124852 <6>[ 3.506338] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10691 00:24:11.136097 <6>[ 3.517197] tun: Universal TUN/TAP device driver, 1.6
10692 00:24:11.139018 <6>[ 3.523238] thunder_xcv, ver 1.0
10693 00:24:11.142443 <6>[ 3.526744] thunder_bgx, ver 1.0
10694 00:24:11.146134 <6>[ 3.530239] nicpf, ver 1.0
10695 00:24:11.156002 <6>[ 3.534237] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10696 00:24:11.159421 <6>[ 3.541713] hns3: Copyright (c) 2017 Huawei Corporation.
10697 00:24:11.166205 <6>[ 3.547302] hclge is initializing
10698 00:24:11.169777 <6>[ 3.550892] e1000: Intel(R) PRO/1000 Network Driver
10699 00:24:11.176235 <6>[ 3.556021] e1000: Copyright (c) 1999-2006 Intel Corporation.
10700 00:24:11.179508 <6>[ 3.562034] e1000e: Intel(R) PRO/1000 Network Driver
10701 00:24:11.186112 <6>[ 3.567249] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10702 00:24:11.192605 <6>[ 3.573434] igb: Intel(R) Gigabit Ethernet Network Driver
10703 00:24:11.199426 <6>[ 3.579084] igb: Copyright (c) 2007-2014 Intel Corporation.
10704 00:24:11.206047 <6>[ 3.584922] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10705 00:24:11.212332 <6>[ 3.591440] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10706 00:24:11.215826 <6>[ 3.597900] sky2: driver version 1.30
10707 00:24:11.222263 <6>[ 3.602822] usbcore: registered new device driver r8152-cfgselector
10708 00:24:11.228973 <6>[ 3.609357] usbcore: registered new interface driver r8152
10709 00:24:11.235754 <6>[ 3.615164] VFIO - User Level meta-driver version: 0.3
10710 00:24:11.242111 <6>[ 3.623377] usbcore: registered new interface driver usb-storage
10711 00:24:11.248823 <6>[ 3.629819] usbcore: registered new device driver onboard-usb-hub
10712 00:24:11.257600 <6>[ 3.638938] mt6397-rtc mt6359-rtc: registered as rtc0
10713 00:24:11.267638 <6>[ 3.644406] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-21T00:24:11 UTC (1718929451)
10714 00:24:11.271067 <6>[ 3.653964] i2c_dev: i2c /dev entries driver
10715 00:24:11.284761 <4>[ 3.665866] cpu cpu0: supply cpu not found, using dummy regulator
10716 00:24:11.291247 <4>[ 3.672290] cpu cpu1: supply cpu not found, using dummy regulator
10717 00:24:11.297431 <4>[ 3.678693] cpu cpu2: supply cpu not found, using dummy regulator
10718 00:24:11.304410 <4>[ 3.685094] cpu cpu3: supply cpu not found, using dummy regulator
10719 00:24:11.310964 <4>[ 3.691498] cpu cpu4: supply cpu not found, using dummy regulator
10720 00:24:11.317361 <4>[ 3.697911] cpu cpu5: supply cpu not found, using dummy regulator
10721 00:24:11.324479 <4>[ 3.704308] cpu cpu6: supply cpu not found, using dummy regulator
10722 00:24:11.330990 <4>[ 3.710703] cpu cpu7: supply cpu not found, using dummy regulator
10723 00:24:11.350931 <6>[ 3.732365] cpu cpu0: EM: created perf domain
10724 00:24:11.354368 <6>[ 3.737310] cpu cpu4: EM: created perf domain
10725 00:24:11.361558 <6>[ 3.742620] sdhci: Secure Digital Host Controller Interface driver
10726 00:24:11.368180 <6>[ 3.749052] sdhci: Copyright(c) Pierre Ossman
10727 00:24:11.374922 <6>[ 3.753999] Synopsys Designware Multimedia Card Interface Driver
10728 00:24:11.381411 <6>[ 3.760643] sdhci-pltfm: SDHCI platform and OF driver helper
10729 00:24:11.384987 <6>[ 3.760682] mmc0: CQHCI version 5.10
10730 00:24:11.391081 <6>[ 3.770961] ledtrig-cpu: registered to indicate activity on CPUs
10731 00:24:11.397807 <6>[ 3.777968] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10732 00:24:11.404177 <6>[ 3.785029] usbcore: registered new interface driver usbhid
10733 00:24:11.408056 <6>[ 3.790851] usbhid: USB HID core driver
10734 00:24:11.414141 <6>[ 3.795050] spi_master spi0: will run message pump with realtime priority
10735 00:24:11.459423 <6>[ 3.834056] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10736 00:24:11.478606 <6>[ 3.849530] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10737 00:24:11.485201 <6>[ 3.864388] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x15414
10738 00:24:11.492169 <6>[ 3.870630] cros-ec-spi spi0.0: Chrome EC device registered
10739 00:24:11.495566 <6>[ 3.876635] mmc0: Command Queue Engine enabled
10740 00:24:11.502130 <6>[ 3.881392] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10741 00:24:11.508554 <6>[ 3.889267] mmcblk0: mmc0:0001 DA4128 116 GiB
10742 00:24:11.517023 <6>[ 3.898190] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10743 00:24:11.524782 <6>[ 3.905992] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10744 00:24:11.534495 <6>[ 3.910163] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10745 00:24:11.537673 <6>[ 3.911951] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10746 00:24:11.544724 <6>[ 3.921889] NET: Registered PF_PACKET protocol family
10747 00:24:11.551065 <6>[ 3.926506] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10748 00:24:11.554482 <6>[ 3.931129] 9pnet: Installing 9P2000 support
10749 00:24:11.561006 <5>[ 3.942144] Key type dns_resolver registered
10750 00:24:11.564326 <6>[ 3.947096] registered taskstats version 1
10751 00:24:11.570769 <5>[ 3.951477] Loading compiled-in X.509 certificates
10752 00:24:11.599774 <4>[ 3.974676] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10753 00:24:11.609750 <4>[ 3.985634] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10754 00:24:11.624605 <6>[ 4.006127] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10755 00:24:11.631656 <6>[ 4.013165] xhci-mtk 11200000.usb: xHCI Host Controller
10756 00:24:11.638673 <6>[ 4.018672] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10757 00:24:11.648633 <6>[ 4.026578] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10758 00:24:11.655445 <6>[ 4.036117] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10759 00:24:11.661796 <6>[ 4.042210] xhci-mtk 11200000.usb: xHCI Host Controller
10760 00:24:11.668445 <6>[ 4.047695] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10761 00:24:11.675265 <6>[ 4.055355] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10762 00:24:11.681814 <6>[ 4.063189] hub 1-0:1.0: USB hub found
10763 00:24:11.685115 <6>[ 4.067221] hub 1-0:1.0: 1 port detected
10764 00:24:11.695016 <6>[ 4.071515] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10765 00:24:11.698380 <6>[ 4.080255] hub 2-0:1.0: USB hub found
10766 00:24:11.701774 <6>[ 4.084281] hub 2-0:1.0: 1 port detected
10767 00:24:11.709806 <6>[ 4.091016] mtk-msdc 11f70000.mmc: Got CD GPIO
10768 00:24:11.724019 <6>[ 4.101637] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10769 00:24:11.730564 <6>[ 4.110012] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10770 00:24:11.740463 <6>[ 4.118351] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10771 00:24:11.749987 <6>[ 4.126696] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10772 00:24:11.756655 <6>[ 4.135035] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10773 00:24:11.766680 <6>[ 4.143373] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10774 00:24:11.773571 <6>[ 4.151713] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10775 00:24:11.783186 <6>[ 4.160056] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10776 00:24:11.789661 <6>[ 4.168397] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10777 00:24:11.799837 <6>[ 4.176736] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10778 00:24:11.806294 <6>[ 4.185074] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10779 00:24:11.816379 <6>[ 4.193421] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10780 00:24:11.822944 <6>[ 4.201760] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10781 00:24:11.832599 <6>[ 4.210098] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10782 00:24:11.839509 <6>[ 4.218436] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10783 00:24:11.846034 <6>[ 4.227167] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10784 00:24:11.852929 <6>[ 4.234316] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10785 00:24:11.859822 <6>[ 4.241079] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10786 00:24:11.869909 <6>[ 4.247832] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10787 00:24:11.876403 <6>[ 4.254765] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10788 00:24:11.883148 <6>[ 4.261627] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10789 00:24:11.892808 <6>[ 4.270758] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10790 00:24:11.902985 <6>[ 4.279882] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10791 00:24:11.912966 <6>[ 4.289177] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10792 00:24:11.922558 <6>[ 4.298645] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10793 00:24:11.929202 <6>[ 4.308112] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10794 00:24:11.939380 <6>[ 4.317233] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10795 00:24:11.948921 <6>[ 4.326699] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10796 00:24:11.959142 <6>[ 4.335817] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10797 00:24:11.969065 <6>[ 4.345112] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10798 00:24:11.979048 <6>[ 4.355272] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10799 00:24:11.989141 <6>[ 4.367304] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10800 00:24:12.110659 <6>[ 4.489027] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10801 00:24:12.264887 <6>[ 4.646130] hub 1-1:1.0: USB hub found
10802 00:24:12.268217 <6>[ 4.650585] hub 1-1:1.0: 4 ports detected
10803 00:24:12.278875 <6>[ 4.660126] hub 1-1:1.0: USB hub found
10804 00:24:12.282252 <6>[ 4.664450] hub 1-1:1.0: 4 ports detected
10805 00:24:12.390801 <6>[ 4.769229] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10806 00:24:12.418018 <6>[ 4.799730] hub 2-1:1.0: USB hub found
10807 00:24:12.421382 <6>[ 4.804289] hub 2-1:1.0: 3 ports detected
10808 00:24:12.434858 <6>[ 4.815973] hub 2-1:1.0: USB hub found
10809 00:24:12.437738 <6>[ 4.820395] hub 2-1:1.0: 3 ports detected
10810 00:24:12.602695 <6>[ 4.980923] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10811 00:24:12.735398 <6>[ 5.116712] hub 1-1.4:1.0: USB hub found
10812 00:24:12.738846 <6>[ 5.121366] hub 1-1.4:1.0: 2 ports detected
10813 00:24:12.753360 <6>[ 5.134928] hub 1-1.4:1.0: USB hub found
10814 00:24:12.756624 <6>[ 5.139523] hub 1-1.4:1.0: 2 ports detected
10815 00:24:12.815083 <6>[ 5.193132] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10816 00:24:12.923346 <6>[ 5.301514] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10817 00:24:12.960043 <4>[ 5.338019] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10818 00:24:12.969689 <4>[ 5.347115] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10819 00:24:13.008877 <6>[ 5.390375] r8152 2-1.3:1.0 eth0: v1.12.13
10820 00:24:13.058460 <6>[ 5.436922] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10821 00:24:13.254921 <6>[ 5.632941] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10822 00:24:14.579535 <6>[ 6.961373] r8152 2-1.3:1.0 eth0: carrier on
10823 00:24:17.458780 <5>[ 6.984661] Sending DHCP requests .., OK
10824 00:24:17.465277 <6>[ 9.845005] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.21
10825 00:24:17.468605 <6>[ 9.853294] IP-Config: Complete:
10826 00:24:17.482180 <6>[ 9.856789] device=eth0, hwaddr=00:24:32:30:78:ff, ipaddr=192.168.201.21, mask=255.255.255.0, gw=192.168.201.1
10827 00:24:17.488787 <6>[ 9.867506] host=mt8192-asurada-spherion-r0-cbg-8, domain=lava-rack, nis-domain=(none)
10828 00:24:17.495312 <6>[ 9.876125] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10829 00:24:17.501950 <6>[ 9.876135] nameserver0=192.168.201.1
10830 00:24:17.505337 <6>[ 9.888238] clk: Disabling unused clocks
10831 00:24:17.508631 <6>[ 9.893675] ALSA device list:
10832 00:24:17.514754 <6>[ 9.896953] No soundcards found.
10833 00:24:17.522798 <6>[ 9.904542] Freeing unused kernel memory: 8512K
10834 00:24:17.526051 <6>[ 9.909592] Run /init as init process
10835 00:24:17.556216 <6>[ 9.938093] NET: Registered PF_INET6 protocol family
10836 00:24:17.563351 <6>[ 9.945045] Segment Routing with IPv6
10837 00:24:17.566267 <6>[ 9.948986] In-situ OAM (IOAM) with IPv6
10838 00:24:17.606758 <30>[ 9.962484] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10839 00:24:17.613758 <30>[ 9.995516] systemd[1]: Detected architecture arm64.
10840 00:24:17.613850
10841 00:24:17.619922 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10842 00:24:17.620040
10843 00:24:17.635210 <30>[ 10.016948] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10844 00:24:17.758975 <30>[ 10.137563] systemd[1]: Queued start job for default target graphical.target.
10845 00:24:17.808356 <30>[ 10.186691] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10846 00:24:17.814965 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10847 00:24:17.835190 <30>[ 10.213687] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10848 00:24:17.844765 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10849 00:24:17.863292 <30>[ 10.241954] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10850 00:24:17.873319 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10851 00:24:17.891702 <30>[ 10.270414] systemd[1]: Created slice user.slice - User and Session Slice.
10852 00:24:17.898522 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10853 00:24:17.922151 <30>[ 10.297710] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10854 00:24:17.931920 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10855 00:24:17.949782 <30>[ 10.325071] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10856 00:24:17.956451 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10857 00:24:17.984344 <30>[ 10.353312] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10858 00:24:17.994457 <30>[ 10.373200] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10859 00:24:18.001305 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10860 00:24:18.018765 <30>[ 10.397274] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10861 00:24:18.028286 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10862 00:24:18.046389 <30>[ 10.425346] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10863 00:24:18.056598 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10864 00:24:18.071194 <30>[ 10.453417] systemd[1]: Reached target paths.target - Path Units.
10865 00:24:18.081678 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10866 00:24:18.098579 <30>[ 10.477307] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10867 00:24:18.104844 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10868 00:24:18.118797 <30>[ 10.500859] systemd[1]: Reached target slices.target - Slice Units.
10869 00:24:18.128898 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10870 00:24:18.143261 <30>[ 10.525374] systemd[1]: Reached target swap.target - Swaps.
10871 00:24:18.149954 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10872 00:24:18.170304 <30>[ 10.549381] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10873 00:24:18.180420 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10874 00:24:18.198813 <30>[ 10.577348] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10875 00:24:18.208740 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10876 00:24:18.228550 <30>[ 10.607067] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10877 00:24:18.238341 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10878 00:24:18.255014 <30>[ 10.633636] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10879 00:24:18.264925 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10880 00:24:18.282746 <30>[ 10.661504] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10881 00:24:18.289469 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10882 00:24:18.306786 <30>[ 10.685546] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10883 00:24:18.316793 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10884 00:24:18.334621 <30>[ 10.713386] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10885 00:24:18.344297 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10886 00:24:18.398516 <30>[ 10.777118] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10887 00:24:18.404823 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10888 00:24:18.426210 <30>[ 10.805057] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10889 00:24:18.432879 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10890 00:24:18.454648 <30>[ 10.833334] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10891 00:24:18.461144 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10892 00:24:18.488823 <30>[ 10.861394] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10893 00:24:18.538337 <30>[ 10.917248] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10894 00:24:18.548171 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10895 00:24:18.571236 <30>[ 10.950012] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10896 00:24:18.577758 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10897 00:24:18.603263 <30>[ 10.982107] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10898 00:24:18.616829 Starting [0;1;39mmodprobe@dm_mod.s…[<6>[ 10.994422] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10899 00:24:18.619780 0m - Load Kernel Module dm_mod...
10900 00:24:18.666543 <30>[ 11.045372] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10901 00:24:18.673145 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10902 00:24:18.695518 <30>[ 11.074050] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10903 00:24:18.705231 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10904 00:24:18.758337 <30>[ 11.137316] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10905 00:24:18.765251 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10906 00:24:18.794761 <30>[ 11.173668] systemd[1]: Starting systemd-journald.service - Journal Service...
10907 00:24:18.801240 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10908 00:24:18.820877 <30>[ 11.199961] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10909 00:24:18.827587 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10910 00:24:18.852769 <30>[ 11.228043] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10911 00:24:18.858932 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10912 00:24:18.881641 <30>[ 11.260679] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10913 00:24:18.891729 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10914 00:24:18.913799 <30>[ 11.292483] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10915 00:24:18.923531 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10916 00:24:18.949619 <30>[ 11.328147] systemd[1]: Started systemd-journald.service - Journal Service.
10917 00:24:18.956123 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10918 00:24:18.978280 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10919 00:24:18.995571 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10920 00:24:19.015175 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10921 00:24:19.035634 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10922 00:24:19.055839 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10923 00:24:19.076109 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10924 00:24:19.096179 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10925 00:24:19.116550 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10926 00:24:19.139001 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10927 00:24:19.160355 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10928 00:24:19.179553 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10929 00:24:19.204302 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10930 00:24:19.211464 See 'systemctl status systemd-remount-fs.service' for details.
10931 00:24:19.221308 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10932 00:24:19.240652 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10933 00:24:19.299126 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10934 00:24:19.327411 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10935 00:24:19.337659 <46>[ 11.716788] systemd-journald[190]: Received client request to flush runtime journal.
10936 00:24:19.351720 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10937 00:24:19.373102 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10938 00:24:19.394158 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10939 00:24:19.416916 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10940 00:24:19.439822 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10941 00:24:19.463439 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10942 00:24:19.487565 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10943 00:24:19.507071 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10944 00:24:19.562634 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10945 00:24:19.596712 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10946 00:24:19.614623 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10947 00:24:19.634073 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10948 00:24:19.674577 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10949 00:24:19.695305 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10950 00:24:19.718579 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10951 00:24:19.769502 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10952 00:24:19.795058 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10953 00:24:19.806743 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10954 00:24:19.839793 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10955 00:24:19.864560 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10956 00:24:19.894601 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10957 00:24:20.001512 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10958 00:24:20.018703 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10959 00:24:20.038346 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10960 00:24:20.056378 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10961 00:24:20.075131 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10962 00:24:20.096147 [[0;32m OK [0m] Listening on [0;1;39mdbus.s<6>[ 12.475208] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10963 00:24:20.099480 ocket[…- D-Bus System Message Bus Socket.
10964 00:24:20.110146 <6>[ 12.489180] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10965 00:24:20.117262 <6>[ 12.497204] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10966 00:24:20.126645 <4>[ 12.505311] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10967 00:24:20.136855 [[0;32m OK [<6>[ 12.515002] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10968 00:24:20.143352 <6>[ 12.517228] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10969 00:24:20.153377 0m] Reached targ<6>[ 12.524013] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10970 00:24:20.163516 et [0;1;39msock<6>[ 12.532183] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10971 00:24:20.172917 ets.target[0m -<6>[ 12.551923] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10972 00:24:20.182746 <6>[ 12.555542] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10973 00:24:20.182876 Socket Units.
10974 00:24:20.189753 <6>[ 12.568998] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10975 00:24:20.199650 <6>[ 12.578172] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10976 00:24:20.202939 <6>[ 12.585340] mc: Linux media interface: v0.10
10977 00:24:20.212386 <6>[ 12.585998] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10978 00:24:20.212500
10979 00:24:20.226241 <6>[ 12.605107] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10980 00:24:20.232744 <3>[ 12.611176] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10981 00:24:20.242752 [[0;32m OK [<3>[ 12.620985] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10982 00:24:20.252800 0m] Reached targ<3>[ 12.630610] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10983 00:24:20.259049 <6>[ 12.633757] remoteproc remoteproc0: scp is available
10984 00:24:20.266198 et [0;1;39mbasi<4>[ 12.637811] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10985 00:24:20.272488 c.target[0m - B<6>[ 12.654004] remoteproc remoteproc0: powering up scp
10986 00:24:20.279088 <4>[ 12.659432] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10987 00:24:20.282664 asic System.
10988 00:24:20.288970 <6>[ 12.660453] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10989 00:24:20.299158 <3>[ 12.661776] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10990 00:24:20.305312 <3>[ 12.661794] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10991 00:24:20.315353 <3>[ 12.661799] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10992 00:24:20.322257 <3>[ 12.661805] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10993 00:24:20.332212 <3>[ 12.661809] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10994 00:24:20.338765 <3>[ 12.678993] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10995 00:24:20.345199 <6>[ 12.685586] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10996 00:24:20.348662 <6>[ 12.689459] videodev: Linux video capture interface: v2.00
10997 00:24:20.358420 <3>[ 12.694367] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10998 00:24:20.365179 <6>[ 12.694472] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10999 00:24:20.372109 <6>[ 12.694480] pci_bus 0000:00: root bus resource [bus 00-ff]
11000 00:24:20.378671 <6>[ 12.694487] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
11001 00:24:20.388265 <6>[ 12.694492] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
11002 00:24:20.395151 <6>[ 12.694527] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
11003 00:24:20.401745 <6>[ 12.694548] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
11004 00:24:20.405250 <6>[ 12.694632] pci 0000:00:00.0: supports D1 D2
11005 00:24:20.411922 <6>[ 12.694636] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11006 00:24:20.421412 <6>[ 12.696330] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
11007 00:24:20.427852 <6>[ 12.696470] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
11008 00:24:20.435143 <6>[ 12.696502] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
11009 00:24:20.442012 <6>[ 12.696523] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
11010 00:24:20.448574 <6>[ 12.696542] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
11011 00:24:20.455134 <6>[ 12.696677] pci 0000:01:00.0: supports D1 D2
11012 00:24:20.462576 <6>[ 12.696681] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11013 00:24:20.472442 <6>[ 12.721528] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
11014 00:24:20.478834 <3>[ 12.726154] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11015 00:24:20.485927 <6>[ 12.733048] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
11016 00:24:20.495795 <3>[ 12.737447] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11017 00:24:20.502147 <6>[ 12.745731] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
11018 00:24:20.508747 <6>[ 12.766589] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
11019 00:24:20.518947 <6>[ 12.775183] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
11020 00:24:20.525319 <6>[ 12.775202] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11021 00:24:20.535075 <6>[ 12.782557] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
11022 00:24:20.541594 <6>[ 12.789040] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11023 00:24:20.551651 <3>[ 12.796410] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11024 00:24:20.558078 <6>[ 12.800351] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11025 00:24:20.568158 <3>[ 12.808878] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11026 00:24:20.574869 <4>[ 12.810103] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
11027 00:24:20.581692 <4>[ 12.810103] Fallback method does not support PEC.
11028 00:24:20.584901 <6>[ 12.814866] pci 0000:00:00.0: PCI bridge to [bus 01]
11029 00:24:20.594733 <3>[ 12.822593] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11030 00:24:20.604611 <3>[ 12.827107] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11031 00:24:20.611078 <6>[ 12.827400] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
11032 00:24:20.617855 <6>[ 12.827410] remoteproc remoteproc0: remote processor scp is now up
11033 00:24:20.624405 <6>[ 12.827411] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
11034 00:24:20.634406 <6>[ 12.829807] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11035 00:24:20.640805 <6>[ 12.831086] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
11036 00:24:20.650839 <3>[ 12.837311] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11037 00:24:20.657662 <3>[ 12.837316] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11038 00:24:20.667127 <3>[ 12.849737] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11039 00:24:20.673807 <6>[ 12.859799] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11040 00:24:20.680417 <3>[ 12.871790] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11041 00:24:20.687063 <6>[ 12.953352] Bluetooth: Core ver 2.22
11042 00:24:20.693460 <6>[ 13.026107] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11043 00:24:20.697011 <6>[ 13.079525] NET: Registered PF_BLUETOOTH protocol family
11044 00:24:20.710175 <6>[ 13.084751] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11045 00:24:20.716631 <6>[ 13.085884] Bluetooth: HCI device and connection manager initialized
11046 00:24:20.723243 <6>[ 13.098299] usbcore: registered new interface driver uvcvideo
11047 00:24:20.729858 <6>[ 13.101111] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
11048 00:24:20.736416 <6>[ 13.101511] pcieport 0000:00:00.0: AER: enabled with IRQ 282
11049 00:24:20.739895 <6>[ 13.104623] Bluetooth: HCI socket layer initialized
11050 00:24:20.746367 <6>[ 13.112261] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11051 00:24:20.756215 <6>[ 13.114956] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
11052 00:24:20.759834 <6>[ 13.116922] Bluetooth: L2CAP socket layer initialized
11053 00:24:20.769780 <6>[ 13.128808] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
11054 00:24:20.772641 <6>[ 13.134428] Bluetooth: SCO socket layer initialized
11055 00:24:20.782816 <5>[ 13.146851] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11056 00:24:20.789777 Starting [0;1;39mdbus.<6>[ 13.172464] usbcore: registered new interface driver btusb
11057 00:24:20.803952 service[0m - D-<4>[ 13.172948] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11058 00:24:20.813658 Bus System Messa<3>[ 13.189449] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11059 00:24:20.820527 <3>[ 13.190450] Bluetooth: hci0: Failed to load firmware file (-2)
11060 00:24:20.820629 ge Bus...
11061 00:24:20.830645 <3>[ 13.201397] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11062 00:24:20.837203 <5>[ 13.201664] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11063 00:24:20.843696 <5>[ 13.202208] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
11064 00:24:20.853887 <4>[ 13.202292] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11065 00:24:20.857438 <6>[ 13.202299] cfg80211: failed to load regulatory.db
11066 00:24:20.864008 <3>[ 13.206686] Bluetooth: hci0: Failed to set up firmware (-2)
11067 00:24:20.873441 <4>[ 13.206689] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11068 00:24:20.886466 <3>[ 13.265388] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11069 00:24:20.923208 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management..<3>[ 13.301702] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11070 00:24:20.930179 <6>[ 13.305015] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11071 00:24:20.930258 .
11072 00:24:20.936783 <6>[ 13.318609] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11073 00:24:20.958981 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions..<3>[ 13.337085] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11074 00:24:20.965589 <6>[ 13.346229] mt7921e 0000:01:00.0: ASIC revision: 79610010
11075 00:24:20.965674 .
11076 00:24:20.992803 [[0;32m OK [0m] Started [0;1;39mdbus.servic<3>[ 13.371306] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11077 00:24:20.996053 e[0m - D-Bus System Message Bus.
11078 00:24:21.025565 <3>[ 13.404337] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11079 00:24:21.034861 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11080 00:24:21.057239 <3>[ 13.436302] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11081 00:24:21.070967 <6>[ 13.449756] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
11082 00:24:21.074060 <6>[ 13.449756]
11083 00:24:21.087076 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11084 00:24:21.108448 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11085 00:24:21.125627 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11086 00:24:21.142183 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11087 00:24:21.221084 [[0;32m OK [0m] Started [0;<46>[ 13.585925] systemd-journald[190]: Data hash table of /var/log/journal/c3f909ee3e324895ab90ff2613af9260/system.journal has a fill level at 75.6 (1547 of 2047 items, 524288 file size, 338 bytes per hash table item), suggesting rotation.
11088 00:24:21.237895 1;39mgetty@tty1.<46>[ 13.608045] systemd-journald[190]: /var/log/journal/c3f909ee3e324895ab90ff2613af9260/system.journal: Journal header limits reached or header out-of-date, rotating.
11089 00:24:21.241062 service[0m - Getty on tty1.
11090 00:24:21.304293 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11091 00:24:21.324449 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11092 00:24:21.338348 <6>[ 13.717258] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
11093 00:24:21.348276 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11094 00:24:21.364971 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11095 00:24:21.399403 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11096 00:24:21.428470 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11097 00:24:21.461354 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11098 00:24:21.532298 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11099 00:24:21.557229 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11100 00:24:21.586245 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11101 00:24:21.633792
11102 00:24:21.637226 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11103 00:24:21.637304
11104 00:24:21.640109 debian-bookworm-arm64 login: root (automatic login)
11105 00:24:21.640186
11106 00:24:21.652774 Linux debian-bookworm-arm64 6.1.94-cip23 #1 SMP PREEMPT Fri Jun 21 00:04:56 UTC 2024 aarch64
11107 00:24:21.652852
11108 00:24:21.659208 The programs included with the Debian GNU/Linux system are free software;
11109 00:24:21.665441 the exact distribution terms for each program are described in the
11110 00:24:21.668994 individual files in /usr/share/doc/*/copyright.
11111 00:24:21.669075
11112 00:24:21.675479 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11113 00:24:21.678993 permitted by applicable law.
11114 00:24:21.679363 Matched prompt #10: / #
11116 00:24:21.679549 Setting prompt string to ['/ #']
11117 00:24:21.679635 end: 2.2.5.1 login-action (duration 00:00:15) [common]
11119 00:24:21.679816 end: 2.2.5 auto-login-action (duration 00:00:15) [common]
11120 00:24:21.679898 start: 2.2.6 expect-shell-connection (timeout 00:02:47) [common]
11121 00:24:21.679967 Setting prompt string to ['/ #']
11122 00:24:21.680074 Forcing a shell prompt, looking for ['/ #']
11124 00:24:21.730252 / #
11125 00:24:21.730437 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11126 00:24:21.730562 Waiting using forced prompt support (timeout 00:02:30)
11127 00:24:21.735045
11128 00:24:21.735309 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11129 00:24:21.735402 start: 2.2.7 export-device-env (timeout 00:02:47) [common]
11130 00:24:21.735490 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11131 00:24:21.735613 end: 2.2 depthcharge-retry (duration 00:02:13) [common]
11132 00:24:21.735706 end: 2 depthcharge-action (duration 00:02:13) [common]
11133 00:24:21.735788 start: 3 lava-test-retry (timeout 00:07:18) [common]
11134 00:24:21.735870 start: 3.1 lava-test-shell (timeout 00:07:18) [common]
11135 00:24:21.735938 Using namespace: common
11137 00:24:21.836287 / # #
11138 00:24:21.836523 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11139 00:24:21.841025 #
11140 00:24:21.841280 Using /lava-14479141
11142 00:24:21.941596 / # export SHELL=/bin/sh
11143 00:24:21.946709 export SHELL=/bin/sh
11145 00:24:22.047221 / # . /lava-14479141/environment
11146 00:24:22.052425 . /lava-14479141/environment
11148 00:24:22.152902 / # /lava-14479141/bin/lava-test-runner /lava-14479141/0
11149 00:24:22.153067 Test shell timeout: 10s (minimum of the action and connection timeout)
11150 00:24:22.157582 /lava-14479141/bin/lava-test-runner /lava-14479141/0
11151 00:24:22.186627 + export TESTRUN_ID=0_igt-kms-me<8>[ 14.567157] <LAVA_SIGNAL_STARTRUN 0_igt-kms-mediatek 14479141_1.5.2.3.1>
11152 00:24:22.186890 Received signal: <STARTRUN> 0_igt-kms-mediatek 14479141_1.5.2.3.1
11153 00:24:22.186962 Starting test lava.0_igt-kms-mediatek (14479141_1.5.2.3.1)
11154 00:24:22.187041 Skipping test definition patterns.
11155 00:24:22.189657 diatek
11156 00:24:22.193257 + cd /lava-14479141/0/tests/0_igt-kms-mediatek
11157 00:24:22.193365 + cat uuid
11158 00:24:22.196258 + UUID=14479141_1.5.2.3.1
11159 00:24:22.196369 + set +x
11160 00:24:22.213171 + IGT_FORCE_DRIVER=mediatek /usr/bin/igt-parser.sh core_auth core_getclient core_getstats core_getversi<6>[ 14.592142] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11161 00:24:22.216458 <8>[ 14.593412] <LAVA_SIGNAL_TESTSET START core_auth>
11162 00:24:22.216665 Received signal: <TESTSET> START core_auth
11163 00:24:22.216779 Starting test_set core_auth
11164 00:24:22.226117 on core_setmaster_vs_auth drm_read kms_addfb_basic kms_atomic kms_flip_event_leak kms_prop_blob kms_setmode kms_vblank
11165 00:24:22.238315 <14>[ 14.620772] [IGT] core_auth: executing
11166 00:24:22.244654 IGT-Version: 1.2<14>[ 14.625113] [IGT] core_auth: starting subtest getclient-simple
11167 00:24:22.254934 8-ga44ebfe (aarc<14>[ 14.632793] [IGT] core_auth: finished subtest getclient-simple, SUCCESS
11168 00:24:22.257996 h64) (Linux: 6.1<14>[ 14.641026] [IGT] core_auth: exiting, ret=0
11169 00:24:22.261646 .94-cip23 aarch64)
11170 00:24:22.271095 Using IGT_SRANDOM=1718929462 for randomisati<8>[ 14.651179] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-simple RESULT=pass>
11171 00:24:22.271204 on
11172 00:24:22.271483 Received signal: <TESTCASE> TEST_CASE_ID=getclient-simple RESULT=pass
11174 00:24:22.274434 Starting subtest: getclient-simple
11175 00:24:22.277640 Opened device: /dev/dri/card0
11176 00:24:22.284540 [1mSubtest getclient-simple: SUCCESS (0.000s)[0m
11177 00:24:22.293386 <14>[ 14.675699] [IGT] core_auth: executing
11178 00:24:22.300071 IGT-Version: 1.2<14>[ 14.680293] [IGT] core_auth: starting subtest getclient-master-drop
11179 00:24:22.309614 8-ga44ebfe (aarc<14>[ 14.688367] [IGT] core_auth: finished subtest getclient-master-drop, SUCCESS
11180 00:24:22.316221 h64) (Linux: 6.1<14>[ 14.697051] [IGT] core_auth: exiting, ret=0
11181 00:24:22.316293 .94-cip23 aarch64)
11182 00:24:22.329531 Using IGT_SRANDOM=1718929462 for randomisati<8>[ 14.707432] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-master-drop RESULT=pass>
11183 00:24:22.329634 on
11184 00:24:22.329913 Received signal: <TESTCASE> TEST_CASE_ID=getclient-master-drop RESULT=pass
11186 00:24:22.332937 Starting subtest: getclient-master-drop
11187 00:24:22.336479 Opened device: /dev/dri/card0
11188 00:24:22.339474 [1mSubtest getclient-master-drop: SUCCESS (0.000s)[0m
11189 00:24:22.346864 <14>[ 14.729724] [IGT] core_auth: executing
11190 00:24:22.354037 IGT-Version: 1.2<14>[ 14.734174] [IGT] core_auth: starting subtest basic-auth
11191 00:24:22.360391 8-ga44ebfe (aarc<14>[ 14.741145] [IGT] core_auth: finished subtest basic-auth, SUCCESS
11192 00:24:22.367050 h64) (Linux: 6.1<14>[ 14.748916] [IGT] core_auth: exiting, ret=0
11193 00:24:22.370735 .94-cip23 aarch64)
11194 00:24:22.377397 Using IGT_SRANDOM=1718929462<8>[ 14.758898] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-auth RESULT=pass>
11195 00:24:22.377692 Received signal: <TESTCASE> TEST_CASE_ID=basic-auth RESULT=pass
11197 00:24:22.380254 for randomisation
11198 00:24:22.383900 Opened device: /dev/dri/card0
11199 00:24:22.387137 Starting subtest: basic-auth
11200 00:24:22.390391 [1mSubtest basic-auth: SUCCESS (0.000s)[0m
11201 00:24:22.396619 <14>[ 14.779253] [IGT] core_auth: executing
11202 00:24:22.403640 IGT-Version: 1.2<14>[ 14.783699] [IGT] core_auth: starting subtest many-magics
11203 00:24:22.406781 8-ga44ebfe (aarch64) (Linux: 6.1.94-cip23 aarch64)
11204 00:24:22.417104 Using IGT_SRANDOM=1718929462 for randomisati<14>[ 14.797830] [IGT] core_auth: finished subtest many-magics, SUCCESS
11205 00:24:22.420036 on
11206 00:24:22.423479 Opened devic<14>[ 14.805703] [IGT] core_auth: exiting, ret=0
11207 00:24:22.426972 e: /dev/dri/card0
11208 00:24:22.429968 Starting subtest: many-magics
11209 00:24:22.436751 Reopening devi<8>[ 14.816852] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=many-magics RESULT=pass>
11210 00:24:22.437023 Received signal: <TESTCASE> TEST_CASE_ID=many-magics RESULT=pass
11212 00:24:22.439927 ce failed after 1020 opens
11213 00:24:22.443373 [1m<8>[ 14.825505] <LAVA_SIGNAL_TESTSET STOP>
11214 00:24:22.443640 Received signal: <TESTSET> STOP
11215 00:24:22.443730 Closing test_set core_auth
11216 00:24:22.446269 Subtest many-magics: SUCCESS (0.007s)[0m
11217 00:24:22.477140 <14>[ 14.859563] [IGT] core_getclient: executing
11218 00:24:22.483480 IGT-Version: 1.2<14>[ 14.864640] [IGT] core_getclient: exiting, ret=0
11219 00:24:22.486825 8-ga44ebfe (aarch64) (Linux: 6.1.94-cip23 aarch64)
11220 00:24:22.496877 Using IGT_SR<8>[ 14.875227] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getclient RESULT=pass>
11221 00:24:22.497186 Received signal: <TESTCASE> TEST_CASE_ID=core_getclient RESULT=pass
11223 00:24:22.500156 ANDOM=1718929462 for randomisation
11224 00:24:22.503239 Opened device: /dev/dri/card0
11225 00:24:22.503321 SUCCESS (0.006s)
11226 00:24:22.542667 <14>[ 14.925290] [IGT] core_getstats: executing
11227 00:24:22.549225 IGT-Version: 1.2<14>[ 14.930083] [IGT] core_getstats: exiting, ret=0
11228 00:24:22.553036 8-ga44ebfe (aarch64) (Linux: 6.1.94-cip23 aarch64)
11229 00:24:22.562346 Using IGT_SR<8>[ 14.940686] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getstats RESULT=pass>
11230 00:24:22.562639 Received signal: <TESTCASE> TEST_CASE_ID=core_getstats RESULT=pass
11232 00:24:22.565916 ANDOM=1718929462 for randomisation
11233 00:24:22.566005 Opened device: /dev/dri/card0
11234 00:24:22.568828 SUCCESS (0.006s)
11235 00:24:22.593559 <14>[ 14.975846] [IGT] core_getversion: executing
11236 00:24:22.599712 IGT-Version: 1.2<14>[ 14.980810] [IGT] core_getversion: exiting, ret=0
11237 00:24:22.603189 8-ga44ebfe (aarch64) (Linux: 6.1.94-cip23 aarch64)
11238 00:24:22.613031 Using IGT_SR<8>[ 14.991391] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getversion RESULT=pass>
11239 00:24:22.613276 Received signal: <TESTCASE> TEST_CASE_ID=core_getversion RESULT=pass
11241 00:24:22.616219 ANDOM=1718929462 for randomisation
11242 00:24:22.616347 Opened device: /dev/dri/card0
11243 00:24:22.619639 SUCCESS (0.006s)
11244 00:24:22.644663 <14>[ 15.027377] [IGT] core_setmaster_vs_auth: executing
11245 00:24:22.651251 IGT-Version: 1.2<14>[ 15.033003] [IGT] core_setmaster_vs_auth: exiting, ret=0
11246 00:24:22.658260 8-ga44ebfe (aarch64) (Linux: 6.1.94-cip23 aarch64)
11247 00:24:22.664791 Using IGT_SR<8>[ 15.044207] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass>
11248 00:24:22.665079 Received signal: <TESTCASE> TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass
11250 00:24:22.667842 ANDOM=1718929462 for randomisation
11251 00:24:22.670972 Opened device: /dev/dri/card0
11252 00:24:22.674584 SUCCESS (0.007s)
11253 00:24:22.687309 <8>[ 15.069940] <LAVA_SIGNAL_TESTSET START drm_read>
11254 00:24:22.687574 Received signal: <TESTSET> START drm_read
11255 00:24:22.687665 Starting test_set drm_read
11256 00:24:22.710029 <14>[ 15.092396] [IGT] drm_read: executing
11257 00:24:22.716589 IGT-Version: 1.2<14>[ 15.096983] [IGT] drm_read: exiting, ret=77
11258 00:24:22.719803 8-ga44ebfe (aarch64) (Linux: 6.1.94-cip23 aarch64)
11259 00:24:22.726260 Using IGT_SR<8>[ 15.107049] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-buffer RESULT=skip>
11260 00:24:22.726520 Received signal: <TESTCASE> TEST_CASE_ID=invalid-buffer RESULT=skip
11262 00:24:22.729583 ANDOM=1718929462 for randomisation
11263 00:24:22.732801 Opened device: /dev/dri/card0
11264 00:24:22.739412 No KMS driver or no outputs, pipes: 16, outputs: 0
11265 00:24:22.746345 [1mSubtest invalid-buffer: SKIP (0.000s)<14>[ 15.128615] [IGT] drm_read: executing
11266 00:24:22.746425 [0m
11267 00:24:22.749307 <14>[ 15.133658] [IGT] drm_read: exiting, ret=77
11268 00:24:22.762400 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.94-cip23 aarch6<8>[ 15.142680] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=fault-buffer RESULT=skip>
11269 00:24:22.762518 4)
11270 00:24:22.762813 Received signal: <TESTCASE> TEST_CASE_ID=fault-buffer RESULT=skip
11272 00:24:22.769246 Using IGT_SRANDOM=1718929462 for randomisation
11273 00:24:22.769326 Opened device: /dev/dri/card0
11274 00:24:22.776048 No KMS driver or no outputs, pipes: 16, outputs: 0
11275 00:24:22.782418 [1mSubtest fault-buffer:<14>[ 15.164179] [IGT] drm_read: executing
11276 00:24:22.785875 SKIP (0.000s)[<14>[ 15.169377] [IGT] drm_read: exiting, ret=77
11277 00:24:22.789301 0m
11278 00:24:22.798806 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.94-cip23 aa<8>[ 15.179459] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-block RESULT=skip>
11279 00:24:22.798885 rch64)
11280 00:24:22.799121 Received signal: <TESTCASE> TEST_CASE_ID=empty-block RESULT=skip
11282 00:24:22.805552 Using IGT_SRANDOM=1718929462 for randomisation
11283 00:24:22.809201 Opened device: /dev/dri/card0
11284 00:24:22.812017 No KMS driver or no outputs, pipes: 16, outputs: 0
11285 00:24:22.819174 [1mSubtest empty-blo<14>[ 15.200097] [IGT] drm_read: executing
11286 00:24:22.822116 ck: SKIP (0.000s<14>[ 15.205723] [IGT] drm_read: exiting, ret=77
11287 00:24:22.825684 )[0m
11288 00:24:22.835267 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.94-cip23<8>[ 15.215773] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-nonblock RESULT=skip>
11289 00:24:22.835517 Received signal: <TESTCASE> TEST_CASE_ID=empty-nonblock RESULT=skip
11291 00:24:22.838854 aarch64)
11292 00:24:22.842373 Using IGT_SRANDOM=1718929462 for randomisation
11293 00:24:22.845120 Opened device: /dev/dri/card0
11294 00:24:22.848418 No KMS driver or no outputs, pipes: 16, outputs: 0
11295 00:24:22.855387 [1mSubtest empty-<14>[ 15.237294] [IGT] drm_read: executing
11296 00:24:22.862158 nonblock: SKIP (<14>[ 15.242527] [IGT] drm_read: exiting, ret=77
11297 00:24:22.862252 0.000s)[0m
11298 00:24:22.871944 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-block RESULT=skip
11300 00:24:22.875205 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.94<8>[ 15.252511] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-block RESULT=skip>
11301 00:24:22.875315 -cip23 aarch64)
11302 00:24:22.878325 Using IGT_SRANDOM=1718929463 for randomisation
11303 00:24:22.881878 Opened device: /dev/dri/card0
11304 00:24:22.884839 No KMS driver or no outputs, pipes: 16, outputs: 0
11305 00:24:22.891631 [1mSubtest <14>[ 15.274191] [IGT] drm_read: executing
11306 00:24:22.898150 short-buffer-blo<14>[ 15.279550] [IGT] drm_read: exiting, ret=77
11307 00:24:22.898226 ck: SKIP (0.000s)[0m
11308 00:24:22.911662 IGT-Version: 1.28-ga44ebfe (aarch64) (Lin<8>[ 15.289590] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-nonblock RESULT=skip>
11309 00:24:22.911916 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-nonblock RESULT=skip
11311 00:24:22.914648 ux: 6.1.94-cip23 aarch64)
11312 00:24:22.918036 Using IGT_SRANDOM=1718929463 for randomisation
11313 00:24:22.921564 Opened device: /dev/dri/card0
11314 00:24:22.924496 No KMS driver or no outputs, pipes: 16, outputs: 0
11315 00:24:22.927972 [<14>[ 15.311715] [IGT] drm_read: executing
11316 00:24:22.935093 1mSubtest short-<14>[ 15.316855] [IGT] drm_read: exiting, ret=77
11317 00:24:22.938154 buffer-nonblock: SKIP (0.000s)[0m
11318 00:24:22.947949 IGT-Version: 1.28-ga44ebfe (<8>[ 15.326991] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-wakeup RESULT=skip>
11319 00:24:22.948223 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-wakeup RESULT=skip
11321 00:24:22.954345 aarch64) (Linux:<8>[ 15.336826] <LAVA_SIGNAL_TESTSET STOP>
11322 00:24:22.954449 6.1.94-cip23 aarch64)
11323 00:24:22.954705 Received signal: <TESTSET> STOP
11324 00:24:22.954797 Closing test_set drm_read
11325 00:24:22.960958 Using IGT_SRANDOM=1718929463 for randomisation
11326 00:24:22.961036 Opened device: /dev/dri/card0
11327 00:24:22.967616 No KMS driver or no outputs, pipes: 16, outputs: 0
11328 00:24:22.974173 [1mSubtest short-buffer-wakeup: SKIP<8>[ 15.357230] <LAVA_SIGNAL_TESTSET START kms_addfb_basic>
11329 00:24:22.974421 Received signal: <TESTSET> START kms_addfb_basic
11330 00:24:22.974491 Starting test_set kms_addfb_basic
11331 00:24:22.977643 (0.000s)[0m
11332 00:24:22.994073 <14>[ 15.376762] [IGT] kms_addfb_basic: executing
11333 00:24:23.007577 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.94-cip23 aarch6<14>[ 15.385923] [IGT] kms_addfb_basic: starting subtest unused-handle
11334 00:24:23.007658 4)
11335 00:24:23.013927 Using IGT_SR<14>[ 15.393818] [IGT] kms_addfb_basic: finished subtest unused-handle, SUCCESS
11336 00:24:23.017200 ANDOM=1718929463 for randomisation
11337 00:24:23.020617 Opened device: /dev/dri/card0
11338 00:24:23.027694 Starting subtest: unused-hand<14>[ 15.410299] [IGT] kms_addfb_basic: exiting, ret=0
11339 00:24:23.027772 le
11340 00:24:23.034059 [1mSubtest unused-handle: SUCCESS (0.000s)[0m
11341 00:24:23.040571 Test requirement not met in<8>[ 15.421528] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-handle RESULT=pass>
11342 00:24:23.040856 Received signal: <TESTCASE> TEST_CASE_ID=unused-handle RESULT=pass
11344 00:24:23.047142 function igt_require_intel, file ../lib/drmtest.c:880:
11345 00:24:23.050497 Test requirement: is_intel_device(fd)
11346 00:24:23.063715 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:88<14>[ 15.443944] [IGT] kms_addfb_basic: executing
11347 00:24:23.063793 0:
11348 00:24:23.067254 Test requirement: is_intel_device(fd)
11349 00:24:23.073522 No KMS driver or no o<14>[ 15.454502] [IGT] kms_addfb_basic: starting subtest unused-pitches
11350 00:24:23.083700 utputs, pipes: 1<14>[ 15.462067] [IGT] kms_addfb_basic: finished subtest unused-pitches, SUCCESS
11351 00:24:23.083793 6, outputs: 0
11352 00:24:23.090342 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.94-cip23 aarch64)
11353 00:24:23.097031 Using IGT_SRA<14>[ 15.478712] [IGT] kms_addfb_basic: exiting, ret=0
11354 00:24:23.100153 NDOM=1718929463 for randomisation
11355 00:24:23.103349 Opened device: /dev/dri/card0
11356 00:24:23.110154 Starting subte<8>[ 15.489996] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-pitches RESULT=pass>
11357 00:24:23.110496 Received signal: <TESTCASE> TEST_CASE_ID=unused-pitches RESULT=pass
11359 00:24:23.113697 st: unused-pitches
11360 00:24:23.116599 [1mSubtest unused-pitches: SUCCESS (0.000s)[0m
11361 00:24:23.123258 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11362 00:24:23.129898 Test r<14>[ 15.512283] [IGT] kms_addfb_basic: executing
11363 00:24:23.133518 equirement: is_intel_device(fd)
11364 00:24:23.143070 Test requirement not met in fun<14>[ 15.521436] [IGT] kms_addfb_basic: starting subtest unused-offsets
11365 00:24:23.149630 ction igt_requir<14>[ 15.529226] [IGT] kms_addfb_basic: finished subtest unused-offsets, SUCCESS
11366 00:24:23.153214 e_intel, file ../lib/drmtest.c:880:
11367 00:24:23.156161 Test requirement: is_intel_device(fd)
11368 00:24:23.163028 No KMS driver or no <14>[ 15.546013] [IGT] kms_addfb_basic: exiting, ret=0
11369 00:24:23.166561 outputs, pipes: 16, outputs: 0
11370 00:24:23.176042 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1<8>[ 15.557140] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-offsets RESULT=pass>
11371 00:24:23.176293 Received signal: <TESTCASE> TEST_CASE_ID=unused-offsets RESULT=pass
11373 00:24:23.179431 .94-cip23 aarch64)
11374 00:24:23.182976 Using IGT_SRANDOM=1718929463 for randomisation
11375 00:24:23.186340 Opened device: /dev/dri/card0
11376 00:24:23.189658 Starting subtest: unused-offsets
11377 00:24:23.199553 [1mSubtest unused-offsets: SUCCESS (0.000s<14>[ 15.579740] [IGT] kms_addfb_basic: executing
11378 00:24:23.199634 )[0m
11379 00:24:23.209264 Test requirement not met in function igt_require_intel, f<14>[ 15.589831] [IGT] kms_addfb_basic: starting subtest unused-modifier
11380 00:24:23.219155 ile ../lib/drmte<14>[ 15.597700] [IGT] kms_addfb_basic: finished subtest unused-modifier, SUCCESS
11381 00:24:23.219232 st.c:880:
11382 00:24:23.222739 Test requirement: is_intel_device(fd)
11383 00:24:23.232423 Test requirement not met in function igt_requi<14>[ 15.614859] [IGT] kms_addfb_basic: exiting, ret=0
11384 00:24:23.235787 re_intel, file ../lib/drmtest.c:880:
11385 00:24:23.239478 Test requirement: is_intel_device(fd)
11386 00:24:23.245531 No <8>[ 15.625592] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-modifier RESULT=pass>
11387 00:24:23.245778 Received signal: <TESTCASE> TEST_CASE_ID=unused-modifier RESULT=pass
11389 00:24:23.252481 KMS driver or no outputs, pipes: 16, outputs: 0
11390 00:24:23.255483 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.94-cip23 aarch64)
11391 00:24:23.262719 Using IGT_SRANDOM=1718929463 for randomisation
11392 00:24:23.265581 Opened devi<14>[ 15.648367] [IGT] kms_addfb_basic: executing
11393 00:24:23.268844 ce: /dev/dri/card0
11394 00:24:23.272518 Starting subtest: unused-modifier
11395 00:24:23.279010 [1mSubte<14>[ 15.658974] [IGT] kms_addfb_basic: starting subtest clobberred-modifier
11396 00:24:23.288874 st unused-modifi<14>[ 15.667121] [IGT] kms_addfb_basic: finished subtest clobberred-modifier, SKIP
11397 00:24:23.291839 er: SUCCESS (0.000s)[0m
11398 00:24:23.302232 Test requirement not met in function igt_require_intel, file ../lib/dr<14>[ 15.683853] [IGT] kms_addfb_basic: exiting, ret=77
11399 00:24:23.302304 mtest.c:880:
11400 00:24:23.305448 Test requirement: is_intel_device(fd)
11401 00:24:23.315520 Test requirement not met in<8>[ 15.694992] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clobberred-modifier RESULT=skip>
11402 00:24:23.315759 Received signal: <TESTCASE> TEST_CASE_ID=clobberred-modifier RESULT=skip
11404 00:24:23.321986 function igt_require_intel, file ../lib/drmtest.c:880:
11405 00:24:23.324923 Test requirement: is_intel_device(fd)
11406 00:24:23.328478 No KMS driver or no outputs, pipes: 16, outputs: 0
11407 00:24:23.334871 IGT-Version: 1.28-ga44ebfe (<14>[ 15.717944] [IGT] kms_addfb_basic: executing
11408 00:24:23.338186 aarch64) (Linux: 6.1.94-cip23 aarch64)
11409 00:24:23.348605 Using IGT_SRANDOM=171892<14>[ 15.728552] [IGT] kms_addfb_basic: starting subtest invalid-smem-bo-on-discrete
11410 00:24:23.358241 9463 for randomi<14>[ 15.737466] [IGT] kms_addfb_basic: finished subtest invalid-smem-bo-on-discrete, SKIP
11411 00:24:23.361728 sation
11412 00:24:23.361792 Opened device: /dev/dri/card0
11413 00:24:23.364797 Starting subtest: clobberred-modifier
11414 00:24:23.371869 Test requirement n<14>[ 15.754948] [IGT] kms_addfb_basic: exiting, ret=77
11415 00:24:23.377837 ot met in function igt_require_i915, file ../lib/drmtest.c:885:
11416 00:24:23.387825 Test requiremen<8>[ 15.766262] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip>
11417 00:24:23.388074 Received signal: <TESTCASE> TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip
11419 00:24:23.391311 t: is_i915_device(fd)
11420 00:24:23.394767 [1mSubtest clobberred-modifier: SKIP (0.000s)[0m
11421 00:24:23.401374 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11422 00:24:23.407778 Test requirement:<14>[ 15.790108] [IGT] kms_addfb_basic: executing
11423 00:24:23.411008 is_intel_device(fd)
11424 00:24:23.420743 Test requirement not met in function igt_r<14>[ 15.800155] [IGT] kms_addfb_basic: starting subtest legacy-format
11425 00:24:23.424473 equire_intel, file ../lib/drmtest.c:880:
11426 00:24:23.427319 Test requirement: is_intel_device(fd)
11427 00:24:23.434447 <14>[ 15.813541] [IGT] kms_addfb_basic: finished subtest legacy-format, SUCCESS
11428 00:24:23.434586
11429 00:24:23.437297 No KMS driver or no outputs, pipes: 16, outputs: 0
11430 00:24:23.447515 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux<14>[ 15.830010] [IGT] kms_addfb_basic: exiting, ret=0
11431 00:24:23.450770 : 6.1.94-cip23 aarch64)
11432 00:24:23.460768 Using IGT_SRANDOM=1718929463 for random<8>[ 15.840833] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=legacy-format RESULT=pass>
11433 00:24:23.460841 isation
11434 00:24:23.461066 Received signal: <TESTCASE> TEST_CASE_ID=legacy-format RESULT=pass
11436 00:24:23.463715 Opened device: /dev/dri/card0
11437 00:24:23.467326 Starting subtest: invalid-smem-bo-on-discrete
11438 00:24:23.480336 Test requirement not met in function igt_require_intel, file ../lib/drmte<14>[ 15.862036] [IGT] kms_addfb_basic: executing
11439 00:24:23.480410 st.c:880:
11440 00:24:23.483910 Test requirement: is_intel_device(fd)
11441 00:24:23.494000 [1mSubtest invalid-smem-bo-on<14>[ 15.873537] [IGT] kms_addfb_basic: starting subtest no-handle
11442 00:24:23.500490 -discrete: SKIP <14>[ 15.880161] [IGT] kms_addfb_basic: finished subtest no-handle, SUCCESS
11443 00:24:23.500561 (0.000s)[0m
11444 00:24:23.513376 Test requirement not met in function igt_require_intel, file ../li<14>[ 15.894187] [IGT] kms_addfb_basic: exiting, ret=0
11445 00:24:23.513446 b/drmtest.c:880:
11446 00:24:23.516883 Test requirement: is_intel_device(fd)
11447 00:24:23.523294 Test re<8>[ 15.905810] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=no-handle RESULT=pass>
11448 00:24:23.523537 Received signal: <TESTCASE> TEST_CASE_ID=no-handle RESULT=pass
11450 00:24:23.533412 quirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11451 00:24:23.536807 Test requirement: is_intel_device(fd)
11452 00:24:23.539694 No KMS driver or no outputs, pipes: 16, outputs: 0
11453 00:24:23.546505 IGT-Vers<14>[ 15.926822] [IGT] kms_addfb_basic: executing
11454 00:24:23.549960 ion: 1.28-ga44ebfe (aarch64) (Linux: 6.1.94-cip23 aarch64)
11455 00:24:23.556525 Using IGT_SRANDOM=17<14>[ 15.939397] [IGT] kms_addfb_basic: starting subtest basic
11456 00:24:23.566729 18929463 for ran<14>[ 15.945730] [IGT] kms_addfb_basic: finished subtest basic, SUCCESS
11457 00:24:23.566835 domisation
11458 00:24:23.570047 Opened device: /dev/dri/card0
11459 00:24:23.573172 Starting subtest: legacy-format
11460 00:24:23.576338 Succ<14>[ 15.959486] [IGT] kms_addfb_basic: exiting, ret=0
11461 00:24:23.583300 essfully fuzzed 10000 {bpp, depth} variations
11462 00:24:23.590050 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
11464 00:24:23.592771 [1mSubtest legacy-format: SUCCES<8>[ 15.971327] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>
11465 00:24:23.592884 S (0.006s)[0m
11466 00:24:23.599720 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11467 00:24:23.602737 Test requirement: is_intel_device(fd)
11468 00:24:23.609346 Test requirement not <14>[ 15.992937] [IGT] kms_addfb_basic: executing
11469 00:24:23.615926 met in function igt_require_intel, file ../lib/drmtest.c:880:
11470 00:24:23.622470 Test requirement:<14>[ 16.004224] [IGT] kms_addfb_basic: starting subtest bad-pitch-0
11471 00:24:23.632636 is_intel_device<14>[ 16.011053] [IGT] kms_addfb_basic: finished subtest bad-pitch-0, SUCCESS
11472 00:24:23.632783 (fd)
11473 00:24:23.635998 No KMS driver or no outputs, pipes: 16, outputs: 0
11474 00:24:23.642694 IGT-Version: 1.28-ga44<14>[ 16.025426] [IGT] kms_addfb_basic: exiting, ret=0
11475 00:24:23.649128 ebfe (aarch64) (Linux: 6.1.94-cip23 aarch64)
11476 00:24:23.658714 Using IGT_SRANDOM=1718929463 for r<8>[ 16.037103] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-0 RESULT=pass>
11477 00:24:23.658829 andomisation
11478 00:24:23.659108 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-0 RESULT=pass
11480 00:24:23.662224 Opened device: /dev/dri/card0
11481 00:24:23.665722 Starting subtest: no-handle
11482 00:24:23.668759 [1mSubtest no-handle: SUCCESS (0.000s)[0m
11483 00:24:23.675548 Test requirement not met in function igt_<14>[ 16.059053] [IGT] kms_addfb_basic: executing
11484 00:24:23.678644 require_intel, file ../lib/drmtest.c:880:
11485 00:24:23.688785 Test requirement: is_intel_device(fd)<14>[ 16.070844] [IGT] kms_addfb_basic: starting subtest bad-pitch-32
11486 00:24:23.688898
11487 00:24:23.698551 Test requireme<14>[ 16.077422] [IGT] kms_addfb_basic: finished subtest bad-pitch-32, SUCCESS
11488 00:24:23.705565 nt not met in function igt_require_intel, file ../lib/drmtest.c:880:
11489 00:24:23.712224 Test requi<14>[ 16.091843] [IGT] kms_addfb_basic: exiting, ret=0
11490 00:24:23.712334 rement: is_intel_device(fd)
11491 00:24:23.718827 No KMS driver or no outputs, pipes: 16, outputs: 0
11492 00:24:23.725402 <8>[ 16.103829] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-32 RESULT=pass>
11493 00:24:23.725517
11494 00:24:23.725794 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-32 RESULT=pass
11496 00:24:23.731830 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.94-cip23 aarch64)
11497 00:24:23.735213 Using IGT_SRANDOM=1718929463 for randomisation
11498 00:24:23.738513 Opened device: /dev/dri/card0
11499 00:24:23.741627 Starting sub<14>[ 16.125948] [IGT] kms_addfb_basic: executing
11500 00:24:23.745038 test: basic
11501 00:24:23.748201 [1mSubtest basic: SUCCESS (0.000s)[0m
11502 00:24:23.755107 Test requirement not met i<14>[ 16.137357] [IGT] kms_addfb_basic: starting subtest bad-pitch-63
11503 00:24:23.764952 n function igt_r<14>[ 16.144403] [IGT] kms_addfb_basic: finished subtest bad-pitch-63, SUCCESS
11504 00:24:23.768201 equire_intel, file ../lib/drmtest.c:880:
11505 00:24:23.771621 Test requirement: is_intel_device(fd)
11506 00:24:23.778054 <14>[ 16.158676] [IGT] kms_addfb_basic: exiting, ret=0
11507 00:24:23.778169
11508 00:24:23.791321 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:8<8>[ 16.170728] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-63 RESULT=pass>
11509 00:24:23.791436 80:
11510 00:24:23.791720 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-63 RESULT=pass
11512 00:24:23.794839 Test requirement: is_intel_device(fd)
11513 00:24:23.801456 No KMS driver or no outputs, pipes: 16, outputs: 0
11514 00:24:23.804446 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.94-cip23 aarch64)
11515 00:24:23.810983 Using IGT_SR<14>[ 16.193021] [IGT] kms_addfb_basic: executing
11516 00:24:23.814211 ANDOM=1718929463 for randomisation
11517 00:24:23.817756 Opened device: /dev/dri/card0
11518 00:24:23.824330 Starting subt<14>[ 16.205762] [IGT] kms_addfb_basic: starting subtest bad-pitch-128
11519 00:24:23.834396 est: bad-pitch-0<14>[ 16.212383] [IGT] kms_addfb_basic: finished subtest bad-pitch-128, SUCCESS
11520 00:24:23.834509
11521 00:24:23.837833 [1mSubtest bad-pitch-0: SUCCESS (0.000s)[0m
11522 00:24:23.844395 Test requirement not met in fun<14>[ 16.226970] [IGT] kms_addfb_basic: exiting, ret=0
11523 00:24:23.851250 ction igt_require_intel, file ../lib/drmtest.c:880:
11524 00:24:23.857580 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-128 RESULT=pass
11526 00:24:23.860830 Test requirement: is_intel_<8>[ 16.238806] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-128 RESULT=pass>
11527 00:24:23.860942 device(fd)
11528 00:24:23.867995 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11529 00:24:23.870864 Test requirement: is_intel_device(fd)
11530 00:24:23.877639 No KMS driver or no outpu<14>[ 16.261098] [IGT] kms_addfb_basic: executing
11531 00:24:23.880880 ts, pipes: 16, outputs: 0
11532 00:24:23.890433 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.94-c<14>[ 16.272588] [IGT] kms_addfb_basic: starting subtest bad-pitch-256
11533 00:24:23.893939 ip23 aarch64)
11534 00:24:23.900459 U<14>[ 16.279669] [IGT] kms_addfb_basic: finished subtest bad-pitch-256, SUCCESS
11535 00:24:23.904013 sing IGT_SRANDOM=1718929463 for randomisation
11536 00:24:23.907617 Opened device: /dev/dri/card0
11537 00:24:23.913840 St<14>[ 16.294234] [IGT] kms_addfb_basic: exiting, ret=0
11538 00:24:23.913953 arting subtest: bad-pitch-32
11539 00:24:23.920498 [1mSubtest bad-pitch-32: SUCCESS (0.000s)[0m
11540 00:24:23.927430 Te<8>[ 16.306051] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-256 RESULT=pass>
11541 00:24:23.927740 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-256 RESULT=pass
11543 00:24:23.933628 st requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11544 00:24:23.937242 Test requirement: is_intel_device(fd)
11545 00:24:23.943991 Test requirement not met in function ig<14>[ 16.328088] [IGT] kms_addfb_basic: executing
11546 00:24:23.950243 t_require_intel, file ../lib/drmtest.c:880:
11547 00:24:23.960550 Test requirement: is_intel_device(f<14>[ 16.339515] [IGT] kms_addfb_basic: starting subtest bad-pitch-1024
11548 00:24:23.960709 d)
11549 00:24:23.967110 No KMS drive<14>[ 16.346665] [IGT] kms_addfb_basic: finished subtest bad-pitch-1024, SUCCESS
11550 00:24:23.970023 r or no outputs, pipes: 16, outputs: 0
11551 00:24:23.979977 IGT-Version: 1.28-ga44ebfe (aarch64) (Li<14>[ 16.361069] [IGT] kms_addfb_basic: exiting, ret=0
11552 00:24:23.983354 nux: 6.1.94-cip23 aarch64)
11553 00:24:23.986661 Using IGT_SRANDOM=1718929463 for randomisation
11554 00:24:23.993337 Open<8>[ 16.372854] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-1024 RESULT=pass>
11555 00:24:23.993632 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-1024 RESULT=pass
11557 00:24:23.996826 ed device: /dev/dri/card0
11558 00:24:23.999845 Starting subtest: bad-pitch-63
11559 00:24:24.003454 [1mSubtest bad-pitch-63: SUCCESS (0.000s)[0m
11560 00:24:24.013431 Test requirement not met in function igt_require_inte<14>[ 16.395161] [IGT] kms_addfb_basic: executing
11561 00:24:24.016361 l, file ../lib/drmtest.c:880:
11562 00:24:24.019887 Test requirement: is_intel_device(fd)
11563 00:24:24.026400 Test requi<14>[ 16.406617] [IGT] kms_addfb_basic: starting subtest bad-pitch-999
11564 00:24:24.033134 rement not met i<14>[ 16.413533] [IGT] kms_addfb_basic: finished subtest bad-pitch-999, SUCCESS
11565 00:24:24.039719 n function igt_require_intel, file ../lib/drmtest.c:880:
11566 00:24:24.045898 Test requirement: is_i<14>[ 16.428228] [IGT] kms_addfb_basic: exiting, ret=0
11567 00:24:24.049511 ntel_device(fd)
11568 00:24:24.053064 No KMS driver or no outputs, pipes: 16, outputs: 0
11569 00:24:24.059250 IGT-Version<8>[ 16.439862] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-999 RESULT=pass>
11570 00:24:24.059540 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-999 RESULT=pass
11572 00:24:24.065886 : 1.28-ga44ebfe (aarch64) (Linux: 6.1.94-cip23 aarch64)
11573 00:24:24.069648 Using IGT_SRANDOM=1718929463 for randomisation
11574 00:24:24.072442 Opened device: /dev/dri/card0
11575 00:24:24.076126 Starting subtest: bad-pitch-128
11576 00:24:24.079208 [1mSub<14>[ 16.462405] [IGT] kms_addfb_basic: executing
11577 00:24:24.085764 test bad-pitch-128: SUCCESS (0.000s)[0m
11578 00:24:24.095988 Test requirement not met in function i<14>[ 16.474960] [IGT] kms_addfb_basic: starting subtest bad-pitch-65536
11579 00:24:24.102132 gt_require_intel<14>[ 16.482135] [IGT] kms_addfb_basic: finished subtest bad-pitch-65536, SUCCESS
11580 00:24:24.105650 , file ../lib/drmtest.c:880:
11581 00:24:24.108616 Test requirement: is_intel_device(fd)
11582 00:24:24.115225 Test requir<14>[ 16.496671] [IGT] kms_addfb_basic: exiting, ret=0
11583 00:24:24.122286 ement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11584 00:24:24.128802 Test re<8>[ 16.508532] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-65536 RESULT=pass>
11585 00:24:24.129093 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-65536 RESULT=pass
11587 00:24:24.132306 quirement: is_intel_device(fd)
11588 00:24:24.135238 No KMS driver or no outputs, pipes: 16, outputs: 0
11589 00:24:24.141738 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.94-cip23 aarch64)
11590 00:24:24.148608 Using IGT_SRANDOM=171892<14>[ 16.531018] [IGT] kms_addfb_basic: executing
11591 00:24:24.151673 9464 for randomisation
11592 00:24:24.155040 Opened device: /dev/dri/card0
11593 00:24:24.158664 Starting subtest: bad-pitch-256
11594 00:24:24.165010 [1mSubtest bad-pitch-25<14>[ 16.545907] [IGT] kms_addfb_basic: starting subtest invalid-get-prop-any
11595 00:24:24.174855 6: SUCCESS (0.00<14>[ 16.554075] [IGT] kms_addfb_basic: finished subtest invalid-get-prop-any, SUCCESS
11596 00:24:24.174959 0s)[0m
11597 00:24:24.185180 Test requirement not met in function igt_require_intel,<14>[ 16.567494] [IGT] kms_addfb_basic: exiting, ret=0
11598 00:24:24.188187 file ../lib/drmtest.c:880:
11599 00:24:24.191611 Test requirement: is_intel_device(fd)
11600 00:24:24.201254 Test require<8>[ 16.579855] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>
11601 00:24:24.201546 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
11603 00:24:24.207928 ment not met in function igt_require_intel, file ../lib/drmtest.c:880:
11604 00:24:24.211586 Test requirement: is_intel_device(fd)
11605 00:24:24.218049 No KMS driver or no outputs, pipes: 16, outputs: <14>[ 16.602427] [IGT] kms_addfb_basic: executing
11606 00:24:24.221475 0
11607 00:24:24.224398 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.94-cip23 aarch64)
11608 00:24:24.234451 Using IGT_SRANDOM=1718929464 for randomis<14>[ 16.615799] [IGT] kms_addfb_basic: starting subtest invalid-get-prop
11609 00:24:24.238084 ation
11610 00:24:24.244282 Opened de<14>[ 16.623912] [IGT] kms_addfb_basic: finished subtest invalid-get-prop, SUCCESS
11611 00:24:24.247954 vice: /dev/dri/card0
11612 00:24:24.254433 Starting subtest: bad-pitc<14>[ 16.636716] [IGT] kms_addfb_basic: exiting, ret=0
11613 00:24:24.254547 h-1024
11614 00:24:24.257434 [1mSubtest bad-pitch-1024: SUCCESS (0.000s)[0m
11615 00:24:24.267664 Test requirement not m<8>[ 16.647882] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>
11616 00:24:24.267955 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
11618 00:24:24.274166 et in function igt_require_intel, file ../lib/drmtest.c:880:
11619 00:24:24.277370 Test requirement: is_intel_device(fd)
11620 00:24:24.287312 Test requirement not met in function igt_require_intel, fil<14>[ 16.670216] [IGT] kms_addfb_basic: executing
11621 00:24:24.290925 e ../lib/drmtest.c:880:
11622 00:24:24.293982 Test requirement: is_intel_device(fd)
11623 00:24:24.303781 No KMS driver or no outputs, pipes: 16, outputs:<14>[ 16.683626] [IGT] kms_addfb_basic: starting subtest invalid-set-prop-any
11624 00:24:24.303942 0
11625 00:24:24.314091 IGT-Version:<14>[ 16.691945] [IGT] kms_addfb_basic: finished subtest invalid-set-prop-any, SUCCESS
11626 00:24:24.324102 1.28-ga44ebfe (aarch64) (Linux: 6.1.94-cip23 aa<14>[ 16.705184] [IGT] kms_addfb_basic: exiting, ret=0
11627 00:24:24.324218 rch64)
11628 00:24:24.326964 Using IGT_SRANDOM=1718929464 for randomisation
11629 00:24:24.337156 Opened device: /dev/dri/<8>[ 16.716010] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>
11630 00:24:24.337241 card0
11631 00:24:24.337544 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
11633 00:24:24.340219 Starting subtest: bad-pitch-999
11634 00:24:24.343353 [1mSubtest bad-pitch-999: SUCCESS (0.000s)[0m
11635 00:24:24.356888 Test requirement not met in function igt_require_intel, file ../lib/drm<14>[ 16.738950] [IGT] kms_addfb_basic: executing
11636 00:24:24.357054 test.c:880:
11637 00:24:24.360506 Test requirement: is_intel_device(fd)
11638 00:24:24.373181 Test requirement not met in function igt_require_intel, file<14>[ 16.752187] [IGT] kms_addfb_basic: starting subtest invalid-set-prop
11639 00:24:24.379690 ../lib/drmtest.<14>[ 16.760382] [IGT] kms_addfb_basic: finished subtest invalid-set-prop, SUCCESS
11640 00:24:24.383057 c:880:
11641 00:24:24.386932 Test requirement: is_intel_device(fd)
11642 00:24:24.389779 N<14>[ 16.773107] [IGT] kms_addfb_basic: exiting, ret=0
11643 00:24:24.396264 o KMS driver or no outputs, pipes: 16, outputs: 0
11644 00:24:24.403065 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
11646 00:24:24.406551 IGT-Version: 1.28-ga44ebfe (a<8>[ 16.784066] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>
11647 00:24:24.409922 arch64) (Linux: 6.1.94-cip23 aarch64)
11648 00:24:24.413116 Using IGT_SRANDOM=1718929464 for randomisation
11649 00:24:24.416337 Opened device: /dev/dri/card0
11650 00:24:24.419654 Starting subtest: bad-pitch-65536
11651 00:24:24.423124 [1mSub<14>[ 16.806621] [IGT] kms_addfb_basic: executing
11652 00:24:24.426185 test bad-pitch-65536: SUCCESS (0.000s)[0m
11653 00:24:24.436120 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11654 00:24:24.439647 <14>[ 16.821951] [IGT] kms_addfb_basic: starting subtest master-rmfb
11655 00:24:24.449276 Test requirement<14>[ 16.829101] [IGT] kms_addfb_basic: finished subtest master-rmfb, SUCCESS
11656 00:24:24.452596 : is_intel_device(fd)
11657 00:24:24.456191 Test requ<14>[ 16.839469] [IGT] kms_addfb_basic: exiting, ret=0
11658 00:24:24.469567 irement not met in function igt_require_intel, file ../lib/drmte<8>[ 16.849567] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=master-rmfb RESULT=pass>
11659 00:24:24.469810 Received signal: <TESTCASE> TEST_CASE_ID=master-rmfb RESULT=pass
11661 00:24:24.472460 st.c:880:
11662 00:24:24.476053 Test requirement: is_intel_device(fd)
11663 00:24:24.479027 No KMS driver or no outputs, pipes: 16, outputs: 0
11664 00:24:24.488806 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.94-cip23 <14>[ 16.870913] [IGT] kms_addfb_basic: executing
11665 00:24:24.488877 aarch64)
11666 00:24:24.492304 Using IGT_SRANDOM=1718929464 for randomisation
11667 00:24:24.495938 Opened device: /dev/dri/card0
11668 00:24:24.499044 Starting subtest: invalid-get-prop-any
11669 00:24:24.508899 [1mSubtest inv<14>[ 16.888793] [IGT] kms_addfb_basic: starting subtest addfb25-modifier-no-flag
11670 00:24:24.518806 alid-get-prop-an<14>[ 16.896437] [IGT] kms_addfb_basic: finished subtest addfb25-modifier-no-flag, SUCCESS
11671 00:24:24.525650 y: SUCCESS (0.00<14>[ 16.906211] [IGT] kms_addfb_basic: exiting, ret=0
11672 00:24:24.525718 0s)[0m
11673 00:24:24.538730 Test requirement not met in function igt_require_intel,<8>[ 16.916823] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass>
11674 00:24:24.538978 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass
11676 00:24:24.542386 file ../lib/drmtest.c:880:
11677 00:24:24.545378 Test requirement: is_intel_device(fd)
11678 00:24:24.551962 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11679 00:24:24.555550 Test req<14>[ 16.939529] [IGT] kms_addfb_basic: executing
11680 00:24:24.558965 uirement: is_intel_device(fd)
11681 00:24:24.565597 No KMS driver or no outputs, pipes: 16, outputs: 0
11682 00:24:24.575076 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.94-cip23 aar<14>[ 16.956828] [IGT] kms_addfb_basic: starting subtest addfb25-bad-modifier
11683 00:24:24.578694 ch64)
11684 00:24:24.582135 Using IGT_SRANDOM=1718929464 for randomisation
11685 00:24:24.585005 Opened device: /dev/dri/card0
11686 00:24:24.588550 Starting subtest: invalid-get-prop
11687 00:24:24.591596 [1mSubtest invalid-get-prop: SUCCESS (0.000s)[0m
11688 00:24:24.598385 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11689 00:24:24.601646 Test requirement: is_intel_device(fd)
11690 00:24:24.608431 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11691 00:24:24.611516 Test requirement: is_intel_device(fd)
11692 00:24:24.618154 No KMS driver or no outputs, pipes: 16, outputs: 0
11693 00:24:24.625044 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.94-cip23 aarch64)
11694 00:24:24.627617 Using IGT_SRANDOM=1718929464 for randomisation
11695 00:24:24.631396 Opened device: /dev/dri/card0
11696 00:24:24.634703 Starting subtest: invalid-set-prop-any
11697 00:24:24.638021 [1mSubtest invalid-set-prop-any: SUCCESS (0.000s)[0m
11698 00:24:24.644301 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11699 00:24:24.647855 Test requirement: is_intel_device(fd)
11700 00:24:24.657482 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11701 00:24:24.660845 Test requirement: is_intel_device(fd)
11702 00:24:24.663919 No KMS driver or no outputs, pipes: 16, outputs: 0
11703 00:24:24.670979 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.94-cip23 aarch64)
11704 00:24:24.674100 Using IGT_SRANDOM=1718929464 for randomisation
11705 00:24:24.677559 Opened device: /dev/dri/card0
11706 00:24:24.680507 Starting subtest: invalid-set-prop
11707 00:24:24.684164 [1mSubtest invalid-set-prop: SUCCESS (0.000s)[0m
11708 00:24:24.690808 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11709 00:24:24.693698 Test requirement: is_intel_device(fd)
11710 00:24:24.703835 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11711 00:24:24.707202 Test requirement: is_intel_device(fd)
11712 00:24:24.710372 No KMS driver or no outputs, pipes: 16, outputs: 0
11713 00:24:24.716829 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.94-cip23 aarch64)
11714 00:24:24.720205 Using IGT_SRANDOM=1718929464 for randomisation
11715 00:24:24.723619 Opened device: /dev/dri/card0
11716 00:24:24.726961 Starting subtest: master-rmfb
11717 00:24:24.730386 [1mSubtest master-rmfb: SUCCESS (0.000s)[0m
11718 00:24:24.736636 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11719 00:24:24.739988 Test requirement: is_intel_device(fd)
11720 00:24:24.746597 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11721 00:24:24.749711 Test requirement: is_intel_device(fd)
11722 00:24:24.756342 No KMS driver or no outputs, pipes: 16, outputs: 0
11723 00:24:24.763078 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.94-cip23 aarch64)
11724 00:24:24.766473 Using IGT_SRANDOM=1718929464 for randomisation
11725 00:24:24.769471 Opened device: /dev/dri/card0
11726 00:24:24.773170 Starting subtest: addfb25-modifier-no-flag
11727 00:24:24.776096 [1mSubtest addfb25-modifier-no-flag: SUCCESS (0.000s)[0m
11728 00:24:24.786273 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11729 00:24:24.789296 Test requirement: is_intel_device(fd)
11730 00:24:24.796011 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11731 00:24:24.799619 Test requirement: is_intel_device(fd)
11732 00:24:24.802588 No KMS driver or no outputs, pipes: 16, outputs: 0
11733 00:24:24.809216 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.94-cip23 aarch64)
11734 00:24:24.812587 Using IGT_SRANDOM=1718929464 for randomisation
11735 00:24:24.815973 Opened device: /dev/dri/card0
11736 00:24:24.819093 Starting subtest: addfb25-bad-modifier
11737 00:24:24.829287 (kms_addfb_basic:440) CRITICAL: Test assertion failure function addfb25_tests, file ../tests/kms_addfb_basic.c:714:
11738 00:24:24.849020 (kms_addfb_basic:440) CRITICAL: Failed assertion: igt_ioctl((fd), ((((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0xB8)) << 0) | ((((sizeof(struct drm_mode_fb_cmd2)))) << ((0+8)+8)))), (&f)) == -1
11739 00:24:24.852403 (kms_addfb_basic:440) CRITICAL: error: 0 != -1
11740 00:24:24.852508 Stack trace:
11741 00:24:24.858431 #0 ../lib/igt_core.c:1989 __igt_fail_assert()
11742 00:24:24.858521 #1 [<unknown>+0xcd0f4358]
11743 00:24:24.861681 #2 [<unknown>+0xcd0f5fbc]
11744 00:24:24.865148 #3 [<unknown>+0xcd0f156c]
11745 00:24:24.868604 #4 [__libc_init_first+0x80]
11746 00:24:24.871639 #5 [__libc_start_main+0x98]
11747 00:24:24.871721 #6 [<unknown>+0xcd0f15b0]
11748 00:24:24.875143 Subtest addfb25-bad-modifier failed.
11749 00:24:24.878378 **** DEBUG ****
11750 00:24:24.884851 (kms_addfb_basic:440) ioctl_wrappers-DEBUG: Test requirement passed: igt_has_fb_modifiers(fd)
11751 00:24:24.894944 (kms_addfb_basic:440) CRITICAL: Test assertion failure function addfb25_tests, file ../tests/kms_addfb_basic.c:714:
11752 00:24:24.914917 (kms_addfb_basic:440) CRITICAL: Failed assertion: igt_ioctl((fd), ((((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0xB8)) << 0) | ((((sizeof(struct drm_mode_fb_cmd2)))) << ((0+8)+8)))), (&f)) == -1
11753 00:24:24.924790 (kms_addfb_basic:440) CRITICAL<14>[ 17.303375] [IGT] kms_addfb_basic: finished subtest addfb25-bad-modifier, FAIL
11754 00:24:24.931364 : error: 0 != -1<14>[ 17.312382] [IGT] kms_addfb_basic: exiting, ret=98
11755 00:24:24.931442
11756 00:24:24.934572 (kms_addfb_basic:440) igt_core-INFO: Stack trace:
11757 00:24:24.944839 (kms_addfb_basic:440) igt_c<8>[ 17.324432] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-bad-modifier RESULT=fail>
11758 00:24:24.945094 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-bad-modifier RESULT=fail
11760 00:24:24.951202 ore-INFO: #0 ../lib/igt_core.c:1989 __igt_fail_assert()
11761 00:24:24.957630 (kms_addfb_basic:440) igt_core-INFO: #1 [<unknown>+0xcd0f4358]
11762 00:24:24.964088 (kms_addfb_basic:440) igt_core-INFO: #2 [<unknown<14>[ 17.347339] [IGT] kms_addfb_basic: executing
11763 00:24:24.967720 >+0xcd0f5fbc]
11764 00:24:24.971233 (kms_addfb_basic:440) igt_core-INFO: #3 [<unknown>+0xcd0f156c]
11765 00:24:24.977845 (kms_addfb_basic:440) igt_core-INFO: #4 [__libc_init_first+0x80]
11766 00:24:24.984070 (kms_addfb_<14>[ 17.366315] [IGT] kms_addfb_basic: exiting, ret=77
11767 00:24:24.990896 basic:440) igt_core-INFO: #5 [__libc_start_main+0x98]
11768 00:24:24.997829 (kms_ad<8>[ 17.377204] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip>
11769 00:24:24.998097 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip
11771 00:24:25.004237 dfb_basic:440) igt_core-INFO: #6 [<unknown>+0xcd0f15b0]
11772 00:24:25.004311 **** END ****
11773 00:24:25.010778 [1mSubtest addfb25-bad-modifier: FAIL (0.339s)[0m
11774 00:24:25.017486 Test requirement not met in fun<14>[ 17.399795] [IGT] kms_addfb_basic: executing
11775 00:24:25.020464 ction igt_require_intel, file ../lib/drmtest.c:880:
11776 00:24:25.024145 Test requirement: is_intel_device(fd)
11777 00:24:25.037700 Test requirement not met in function igt_require_intel, file ../lib/<14>[ 17.417853] [IGT] kms_addfb_basic: exiting, ret=77
11778 00:24:25.037777 drmtest.c:880:
11779 00:24:25.040611 Test requirement: is_intel_device(fd)
11780 00:24:25.050405 No KMS dr<8>[ 17.428915] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip>
11781 00:24:25.050649 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip
11783 00:24:25.053981 iver or no outputs, pipes: 16, outputs: 0
11784 00:24:25.060372 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.94-cip23 aarch64)
11785 00:24:25.063968 Using IGT_SRANDOM=1718929465 for randomisation
11786 00:24:25.066793 O<14>[ 17.451345] [IGT] kms_addfb_basic: executing
11787 00:24:25.070223 pened device: /dev/dri/card0
11788 00:24:25.076755 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11789 00:24:25.080405 Test requirement: is_intel_device(fd)
11790 00:24:25.086986 [1mSub<14>[ 17.469512] [IGT] kms_addfb_basic: exiting, ret=77
11791 00:24:25.093729 test addfb25-x-tiled-mismatch-legacy: SKIP (0.000s)[0m
11792 00:24:25.103099 Test re<8>[ 17.480197] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip>
11793 00:24:25.103369 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip
11795 00:24:25.110265 quirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11796 00:24:25.113319 Test requirement: is_intel_device(fd)
11797 00:24:25.119901 No KMS driver or no outputs, pipes: 16, outp<14>[ 17.503183] [IGT] kms_addfb_basic: executing
11798 00:24:25.119978 uts: 0
11799 00:24:25.126385 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.94-cip23 aarch64)
11800 00:24:25.132985 Using IGT_SRANDOM=1718929465 for randomisation
11801 00:24:25.133062 Opened device: /dev/dri/card0
11802 00:24:25.139898 Test <14>[ 17.521223] [IGT] kms_addfb_basic: exiting, ret=77
11803 00:24:25.153315 requirement not met in function igt_require_intel, file ../lib/d<8>[ 17.532501] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip>
11804 00:24:25.153389 rmtest.c:880:
11805 00:24:25.153619 Received signal: <TESTCASE> TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip
11807 00:24:25.156172 Test requirement: is_intel_device(fd)
11808 00:24:25.163105 [1mSubtest addfb25-x-tiled-legacy: SKIP (0.000s)[0m
11809 00:24:25.172840 Test requirement not met in function igt_require_in<14>[ 17.554014] [IGT] kms_addfb_basic: executing
11810 00:24:25.172915 tel, file ../lib/drmtest.c:880:
11811 00:24:25.179364 Test requirement: is_intel_device(fd)
11812 00:24:25.182524 No KMS driver or no outputs, pipes: 16, outputs: 0
11813 00:24:25.189698 IGT-Version: 1.28-ga44ebfe (aarch64)<14>[ 17.572112] [IGT] kms_addfb_basic: exiting, ret=77
11814 00:24:25.192541 (Linux: 6.1.94-cip23 aarch64)
11815 00:24:25.202886 Received signal: <TESTCASE> TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip
11817 00:24:25.206129 Using IGT_SRANDOM=1718929465 for<8>[ 17.583211] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip>
11818 00:24:25.206205 randomisation
11819 00:24:25.209484 Opened device: /dev/dri/card0
11820 00:24:25.215815 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11821 00:24:25.222735 Test requirement: is_intel_de<14>[ 17.605835] [IGT] kms_addfb_basic: executing
11822 00:24:25.222803 vice(fd)
11823 00:24:25.229195 [1mSubtest addfb25-framebuffer-vs-set-tiling: SKIP (0.000s)[0m
11824 00:24:25.235647 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11825 00:24:25.242228 <14>[ 17.623816] [IGT] kms_addfb_basic: exiting, ret=77
11826 00:24:25.245671 Test requirement: is_intel_device(fd)
11827 00:24:25.255496 No KMS driver or no outpu<8>[ 17.634467] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tile-pitch-mismatch RESULT=skip>
11828 00:24:25.255741 Received signal: <TESTCASE> TEST_CASE_ID=tile-pitch-mismatch RESULT=skip
11830 00:24:25.259002 ts, pipes: 16, outputs: 0
11831 00:24:25.262203 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.94-cip23 aarch64)
11832 00:24:25.269161 Using IGT_SRANDOM=1718929465 for randomisation
11833 00:24:25.269238 Opened device: /dev/dri/card0
11834 00:24:25.278975 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11835 00:24:25.285231 Test requirement: is_intel_dev<14>[ 17.668025] [IGT] kms_addfb_basic: executing
11836 00:24:25.285308 ice(fd)
11837 00:24:25.292169 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11838 00:24:25.295604 Test requirement: is_intel_device(fd)
11839 00:24:25.305596 [1mSubtest basic-x-tiled-legacy: SKIP (0.00<14>[ 17.687368] [IGT] kms_addfb_basic: exiting, ret=77
11840 00:24:25.305673 0s)[0m
11841 00:24:25.311953 No KMS driver or no outputs, pipes: 16, outputs: 0
11842 00:24:25.318452 IGT<8>[ 17.698481] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip>
11843 00:24:25.318697 Received signal: <TESTCASE> TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip
11845 00:24:25.325430 -Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.94-cip23 aarch64)
11846 00:24:25.328888 Using IGT_SRANDOM=1718929465 for randomisation
11847 00:24:25.331983 Opened device: /dev/dri/card0
11848 00:24:25.338227 Test requirement<14>[ 17.720179] [IGT] kms_addfb_basic: executing
11849 00:24:25.341689 not met in function igt_require_intel, file ../lib/drmtest.c:880:
11850 00:24:25.345212 Test requirement: is_intel_device(fd)
11851 00:24:25.355190 Test requirement not met in function igt_require_inte<14>[ 17.738041] [IGT] kms_addfb_basic: exiting, ret=77
11852 00:24:25.358206 l, file ../lib/drmtest.c:880:
11853 00:24:25.367934 Test requirement: is_intel_device<8>[ 17.748617] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=size-max RESULT=skip>
11854 00:24:25.368029 (fd)
11855 00:24:25.368256 Received signal: <TESTCASE> TEST_CASE_ID=size-max RESULT=skip
11857 00:24:25.374703 [1mSubtest framebuffer-vs-set-tiling: SKIP (0.000s)[0m
11858 00:24:25.378332 No KMS driver or no outputs, pipes: 16, outputs: 0
11859 00:24:25.387982 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux:<14>[ 17.769475] [IGT] kms_addfb_basic: executing
11860 00:24:25.388061 6.1.94-cip23 aarch64)
11861 00:24:25.394293 Using IGT_SRANDOM=1718929465 for randomisation
11862 00:24:25.394370 Opened device: /dev/dri/card0
11863 00:24:25.407556 Test requirement not met in function igt_require_intel, f<14>[ 17.787663] [IGT] kms_addfb_basic: exiting, ret=77
11864 00:24:25.407659 ile ../lib/drmtest.c:880:
11865 00:24:25.417574 Test requirement: is_intel_device(fd)<8>[ 17.798607] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-wide RESULT=skip>
11866 00:24:25.417675
11867 00:24:25.417931 Received signal: <TESTCASE> TEST_CASE_ID=too-wide RESULT=skip
11869 00:24:25.427745 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11870 00:24:25.430716 Test requirement: is_intel_device(fd)
11871 00:24:25.437630 [1mSubtest tile-pitch-mismatch: SK<14>[ 17.819855] [IGT] kms_addfb_basic: executing
11872 00:24:25.437734 IP (0.000s)[0m
11873 00:24:25.444127 No KMS driver or no outputs, pipes: 16, outputs: 0
11874 00:24:25.447166 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.94-cip23 aarch64)
11875 00:24:25.457465 Using IGT_SRANDOM=17189<14>[ 17.837475] [IGT] kms_addfb_basic: exiting, ret=77
11876 00:24:25.457568 29465 for randomisation
11877 00:24:25.460265 Opened device: /dev/dri/card0
11878 00:24:25.466924 Test req<8>[ 17.848483] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-high RESULT=skip>
11879 00:24:25.467188 Received signal: <TESTCASE> TEST_CASE_ID=too-high RESULT=skip
11881 00:24:25.473503 uirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11882 00:24:25.476885 Test requirement: is_intel_device(fd)
11883 00:24:25.486751 Test requirement not met in function igt_requ<14>[ 17.869410] [IGT] kms_addfb_basic: executing
11884 00:24:25.490317 ire_intel, file ../lib/drmtest.c:880:
11885 00:24:25.493216 Test requirement: is_intel_device(fd)
11886 00:24:25.496815 [1mSubtest basic-y-tiled-legacy: SKIP (0.000s)[0m
11887 00:24:25.506809 No KMS driver or no outputs, <14>[ 17.887314] [IGT] kms_addfb_basic: exiting, ret=77
11888 00:24:25.506891 pipes: 16, outputs: 0
11889 00:24:25.519827 IGT-Version: 1.28-ga44ebfe (aarch64) (Lin<8>[ 17.898731] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small RESULT=skip>
11890 00:24:25.519929 ux: 6.1.94-cip23 aarch64)
11891 00:24:25.520183 Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small RESULT=skip
11893 00:24:25.526850 Using IGT_SRANDOM=1718929465 for randomisation
11894 00:24:25.526919 Opened device: /dev/dri/card0
11895 00:24:25.536991 Test requirement not met in function igt_require_intel<14>[ 17.919675] [IGT] kms_addfb_basic: executing
11896 00:24:25.539947 , file ../lib/drmtest.c:880:
11897 00:24:25.543335 Test requirement: is_intel_device(fd)
11898 00:24:25.549704 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11899 00:24:25.556316 Test re<14>[ 17.937911] [IGT] kms_addfb_basic: exiting, ret=77
11900 00:24:25.559715 quirement: is_intel_device(fd)
11901 00:24:25.569773 No KMS driver or no outputs, pip<8>[ 17.948644] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=small-bo RESULT=skip>
11902 00:24:25.569851 es: 16, outputs: 0
11903 00:24:25.570078 Received signal: <TESTCASE> TEST_CASE_ID=small-bo RESULT=skip
11905 00:24:25.572722 [1mSubtest size-max: SKIP (0.000s)[0m
11906 00:24:25.579870 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.94-cip23 aarch64)
11907 00:24:25.586443 Using IGT_SRANDOM=1718929465 fo<14>[ 17.969986] [IGT] kms_addfb_basic: executing
11908 00:24:25.589427 r randomisation
11909 00:24:25.593131 Opened device: /dev/dri/card0
11910 00:24:25.599679 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11911 00:24:25.606311 Test requirement: is_intel_d<14>[ 17.987828] [IGT] kms_addfb_basic: exiting, ret=77
11912 00:24:25.606387 evice(fd)
11913 00:24:25.619140 Test requirement not met in function igt_require_inte<8>[ 17.998877] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip>
11914 00:24:25.619409 Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip
11916 00:24:25.622802 l, file ../lib/drmtest.c:880:
11917 00:24:25.626077 Test requirement: is_intel_device(fd)
11918 00:24:25.629272 No KMS driver or no outputs, pipes: 16, outputs: 0
11919 00:24:25.636194 [1mSubtest too-wide: <14>[ 18.020647] [IGT] kms_addfb_basic: executing
11920 00:24:25.639098 SKIP (0.000s)[0m
11921 00:24:25.646074 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.94-cip23 aarch64)
11922 00:24:25.648886 Using IGT_SRANDOM=1718929465 for randomisation
11923 00:24:25.655895 Opened device: /dev/dri/c<14>[ 18.038107] [IGT] kms_addfb_basic: exiting, ret=77
11924 00:24:25.655964 ard0
11925 00:24:25.669126 Test requirement not met in function igt_require_intel, fi<8>[ 18.049441] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip>
11926 00:24:25.669384 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip
11928 00:24:25.672472 le ../lib/drmtest.c:880:
11929 00:24:25.675706 Test requirement: is_intel_device(fd)
11930 00:24:25.682269 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11931 00:24:25.688680 Test requir<14>[ 18.071403] [IGT] kms_addfb_basic: executing
11932 00:24:25.692140 ement: is_intel_device(fd)
11933 00:24:25.695258 No KMS driver or no outputs, pipes: 16, outputs: 0
11934 00:24:25.698810 [1mSubtest too-high: SKIP (0.000s)[0m
11935 00:24:25.708501 IGT-Version: 1.28-ga44ebfe (aarch64) (L<14>[ 18.089200] [IGT] kms_addfb_basic: exiting, ret=77
11936 00:24:25.708593 inux: 6.1.94-cip23 aarch64)
11937 00:24:25.721924 Using IGT_SRANDOM=1718929465 for ra<8>[ 18.100368] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip>
11938 00:24:25.722018 ndomisation
11939 00:24:25.722271 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip
11941 00:24:25.725592 Opened device: /dev/dri/card0
11942 00:24:25.731623 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11943 00:24:25.738275 Test requirement: is_intel_devic<14>[ 18.122422] [IGT] kms_addfb_basic: executing
11944 00:24:25.742060 e(fd)
11945 00:24:25.748207 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11946 00:24:25.751631 Test requirement: is_intel_device(fd)
11947 00:24:25.758233 No KMS driver or no outputs, p<14>[ 18.140627] [IGT] kms_addfb_basic: exiting, ret=77
11948 00:24:25.761814 ipes: 16, outputs: 0
11949 00:24:25.771178 [1mSubtest bo-too-small: SKIP (0.000s)[0<8>[ 18.151585] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip>
11950 00:24:25.771441 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip
11952 00:24:25.774924 m
11953 00:24:25.777817 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.94-cip23 aarch64)
11954 00:24:25.784426 Using IGT_SRANDOM=1718929465 for randomisation
11955 00:24:25.784520 Opened device: /dev/dri/card0
11956 00:24:25.791440 Test requi<14>[ 18.173855] [IGT] kms_addfb_basic: executing
11957 00:24:25.798054 rement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11958 00:24:25.800920 Test requirement: is_intel_device(fd)
11959 00:24:25.811165 Test requirement not met in function igt_requir<14>[ 18.191961] [IGT] kms_addfb_basic: exiting, ret=77
11960 00:24:25.814202 e_intel, file ../lib/drmtest.c:880:
11961 00:24:25.817577 Test requirement: is_intel_device(fd)
11962 00:24:25.824295 No K<8>[ 18.204280] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-4-tiled RESULT=skip>
11963 00:24:25.824532 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-4-tiled RESULT=skip
11965 00:24:25.830752 MS driver or no outputs, pipes: <8>[ 18.214531] <LAVA_SIGNAL_TESTSET STOP>
11966 00:24:25.830986 Received signal: <TESTSET> STOP
11967 00:24:25.831069 Closing test_set kms_addfb_basic
11968 00:24:25.834341 16, outputs: 0
11969 00:24:25.837279 [1mSubtest small-bo: SKIP (0.000s)[0m
11970 00:24:25.843719 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.94-cip23 aarch64)
11971 00:24:25.847346 Using IGT_SRANDOM=1718929465 for randomisation
11972 00:24:25.854054 Opened device: /dev<8>[ 18.236204] <LAVA_SIGNAL_TESTSET START kms_atomic>
11973 00:24:25.854124 /dri/card0
11974 00:24:25.854348 Received signal: <TESTSET> START kms_atomic
11975 00:24:25.854406 Starting test_set kms_atomic
11976 00:24:25.860738 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11977 00:24:25.863717 Test requirement: is_intel_device(fd)
11978 00:24:25.870280 Test requ<14>[ 18.253995] [IGT] kms_atomic: executing
11979 00:24:25.877271 irement not met <14>[ 18.258624] [IGT] kms_atomic: exiting, ret=77
11980 00:24:25.880564 in function igt_require_intel, file ../lib/drmtest.c:880:
11981 00:24:25.890282 Test <8>[ 18.268887] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-overlay-legacy RESULT=skip>
11982 00:24:25.890545 Received signal: <TESTCASE> TEST_CASE_ID=plane-overlay-legacy RESULT=skip
11984 00:24:25.893763 requirement: is_intel_device(fd)
11985 00:24:25.897276 No KMS driver or no outputs, pipes: 16, outputs: 0
11986 00:24:25.903810 [1mSubtest bo-too-small-due-to-tiling: SKIP (0.000s)[0m
11987 00:24:25.906719 IGT-Version: 1.<14>[ 18.291536] [IGT] kms_atomic: executing
11988 00:24:25.913240 28-ga44ebfe (aar<14>[ 18.296320] [IGT] kms_atomic: exiting, ret=77
11989 00:24:25.916870 ch64) (Linux: 6.1.94-cip23 aarch64)
11990 00:24:25.926820 Using IGT_SRANDOM=171892946<8>[ 18.306735] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-legacy RESULT=skip>
11991 00:24:25.927086 Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-legacy RESULT=skip
11993 00:24:25.929742 5 for randomisation
11994 00:24:25.933311 Opened device: /dev/dri/card0
11995 00:24:25.939667 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11996 00:24:25.946711 Test requirement: is_int<14>[ 18.328911] [IGT] kms_atomic: executing
11997 00:24:25.946788 el_device(fd)
11998 00:24:25.952912 T<14>[ 18.333867] [IGT] kms_atomic: exiting, ret=77
11999 00:24:25.966182 est requirement not met in function igt_require_intel, file ../l<8>[ 18.344060] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip>
12000 00:24:25.966281 ib/drmtest.c:880:
12001 00:24:25.966538 Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip
12003 00:24:25.969864 Test requirement: is_intel_device(fd)
12004 00:24:25.976419 No KMS driver or no outputs, pipes: 16, outputs: 0
12005 00:24:25.983089 [1mSubtest addfb25-y-tiled-legacy: SKIP (0.000s)<14>[ 18.367732] [IGT] kms_atomic: executing
12006 00:24:25.986090 [0m
12007 00:24:25.989314 IGT-Version<14>[ 18.372714] [IGT] kms_atomic: exiting, ret=77
12008 00:24:25.996145 : 1.28-ga44ebfe (aarch64) (Linux: 6.1.94-cip23 aarch64)
12009 00:24:26.002658 Using I<8>[ 18.383034] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-immutable-zpos RESULT=skip>
12010 00:24:26.002932 Received signal: <TESTCASE> TEST_CASE_ID=plane-immutable-zpos RESULT=skip
12012 00:24:26.006251 GT_SRANDOM=1718929465 for randomisation
12013 00:24:26.009255 Opened device: /dev/dri/card0
12014 00:24:26.015633 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
12015 00:24:26.022430 Test<14>[ 18.405070] [IGT] kms_atomic: executing
12016 00:24:26.029389 requirement: is<14>[ 18.410367] [IGT] kms_atomic: exiting, ret=77
12017 00:24:26.029468 _intel_device(fd)
12018 00:24:26.039470 Test requirement not met in function igt_requ<8>[ 18.420849] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test-only RESULT=skip>
12019 00:24:26.039720 Received signal: <TESTCASE> TEST_CASE_ID=test-only RESULT=skip
12021 00:24:26.042813 ire_intel, file ../lib/drmtest.c:880:
12022 00:24:26.045825 Test requirement: is_intel_device(fd)
12023 00:24:26.052269 No KMS driver or no outputs, pipes: 16, outputs: 0
12024 00:24:26.059327 [1mSubtest addfb25-yf-tiled-l<14>[ 18.441961] [IGT] kms_atomic: executing
12025 00:24:26.065644 egacy: SKIP (0.0<14>[ 18.447201] [IGT] kms_atomic: exiting, ret=77
12026 00:24:26.065724 00s)[0m
12027 00:24:26.079040 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.94-ci<8>[ 18.457485] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-cursor-legacy RESULT=skip>
12028 00:24:26.079126 p23 aarch64)
12029 00:24:26.079356 Received signal: <TESTCASE> TEST_CASE_ID=plane-cursor-legacy RESULT=skip
12031 00:24:26.081865 Using IGT_SRANDOM=1718929465 for randomisation
12032 00:24:26.085654 Opened device: /dev/dri/card0
12033 00:24:26.092090 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
12034 00:24:26.098785 Test requirement: is_intel_devi<14>[ 18.482829] [IGT] kms_atomic: executing
12035 00:24:26.101941 ce(fd)
12036 00:24:26.105165 Test req<14>[ 18.488706] [IGT] kms_atomic: exiting, ret=77
12037 00:24:26.118546 uirement not met in function igt_require_intel, file ../lib/drmt<8>[ 18.499190] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params RESULT=skip>
12038 00:24:26.118848 Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params RESULT=skip
12040 00:24:26.121577 est.c:880:
12041 00:24:26.124969 Test requirement: is_intel_device(fd)
12042 00:24:26.128655 No KMS driver or no outputs, pipes: 16, outputs: 0
12043 00:24:26.138469 [1mSubtest addfb25-y-tiled-small-legacy: SKIP (0.000s)[<14>[ 18.520787] [IGT] kms_atomic: executing
12044 00:24:26.138582 0m
12045 00:24:26.145031 IGT-Version:<14>[ 18.526282] [IGT] kms_atomic: exiting, ret=77
12046 00:24:26.148358 1.28-ga44ebfe (aarch64) (Linux: 6.1.94-cip23 aarch64)
12047 00:24:26.158466 Using IG<8>[ 18.536386] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params-fence RESULT=skip>
12048 00:24:26.158754 Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params-fence RESULT=skip
12050 00:24:26.161369 T_SRANDOM=1718929465 for randomisation
12051 00:24:26.164834 Opened device: /dev/dri/card0
12052 00:24:26.171750 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
12053 00:24:26.174628 Test <14>[ 18.558966] [IGT] kms_atomic: executing
12054 00:24:26.181560 requirement: is_<14>[ 18.564369] [IGT] kms_atomic: exiting, ret=77
12055 00:24:26.184885 intel_device(fd)
12056 00:24:26.194607 Test requirement not met in function igt_requi<8>[ 18.574632] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params RESULT=skip>
12057 00:24:26.194895 Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params RESULT=skip
12059 00:24:26.198105 re_intel, file ../lib/drmtest.c:880:
12060 00:24:26.201109 Test requirement: is_intel_device(fd)
12061 00:24:26.207968 No KMS driver or no outputs, pipes: 16, outputs: 0
12062 00:24:26.214627 [1mSubtest addfb25-4-tiled: SK<14>[ 18.596915] [IGT] kms_atomic: executing
12063 00:24:26.214750 IP (0.000s)[0m
12064 00:24:26.221007 <14>[ 18.601848] [IGT] kms_atomic: exiting, ret=77
12065 00:24:26.221120
12066 00:24:26.234440 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.94-cip23 aarch<8>[ 18.612107] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip>
12067 00:24:26.234565 64)
12068 00:24:26.234850 Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip
12070 00:24:26.237710 Using IGT_SRANDOM=1718929465 for randomisation
12071 00:24:26.240757 Opened device: /dev/dri/card0
12072 00:24:26.244199 No KMS driver or no outputs, pipes: 16, outputs: 0
12073 00:24:26.250715 [1mSubtest plane-overla<14>[ 18.634310] [IGT] kms_atomic: executing
12074 00:24:26.257749 y-legacy: SKIP (<14>[ 18.639941] [IGT] kms_atomic: exiting, ret=77
12075 00:24:26.257864 0.000s)[0m
12076 00:24:26.270824 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.94<8>[ 18.650050] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic-invalid-params RESULT=skip>
12077 00:24:26.271117 Received signal: <TESTCASE> TEST_CASE_ID=atomic-invalid-params RESULT=skip
12079 00:24:26.274301 -cip23 aarch64)
12080 00:24:26.277147 Using IGT_SRANDOM=1718929466 for randomisation
12081 00:24:26.280798 Opened device: /dev/dri/card0
12082 00:24:26.283722 No KMS driver or no outputs, pipes: 16, outputs: 0
12083 00:24:26.290732 [1mSubtest <14>[ 18.672300] [IGT] kms_atomic: executing
12084 00:24:26.293630 plane-primary-le<14>[ 18.677751] [IGT] kms_atomic: exiting, ret=77
12085 00:24:26.296976 gacy: SKIP (0.000s)[0m
12086 00:24:26.307068 IGT-Version: 1.28-ga44ebfe (aarch64) (L<8>[ 18.687959] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic-plane-damage RESULT=skip>
12087 00:24:26.307361 Received signal: <TESTCASE> TEST_CASE_ID=atomic-plane-damage RESULT=skip
12089 00:24:26.310472 inux: 6.1.94-cip23 aarch64)
12090 00:24:26.313618 Received signal: <TESTSET> STOP
12091 00:24:26.313728 Closing test_set kms_atomic
12092 00:24:26.317075 Usi<8>[ 18.698037] <LAVA_SIGNAL_TESTSET STOP>
12093 00:24:26.320383 ng IGT_SRANDOM=1718929466 for randomisation
12094 00:24:26.323713 Opened device: /dev/dri/card0
12095 00:24:26.326625 No KMS driver or no outputs, pipes: 16, outputs: 0
12096 00:24:26.336924 [1mSubtest plane-primary-overlay-mutable-zpos: SKIP (0.000s)[0<8>[ 18.719602] <LAVA_SIGNAL_TESTSET START kms_flip_event_leak>
12097 00:24:26.337045 m
12098 00:24:26.337317 Received signal: <TESTSET> START kms_flip_event_leak
12099 00:24:26.337425 Starting test_set kms_flip_event_leak
12100 00:24:26.343334 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.94-cip23 aarch64)
12101 00:24:26.349778 Using IGT_SRANDOM=1718929466 for randomisation
12102 00:24:26.349891 Opened device: /dev/dri/card0
12103 00:24:26.356269 No KMS dri<14>[ 18.739235] [IGT] kms_flip_event_leak: executing
12104 00:24:26.363008 ver or no output<14>[ 18.745245] [IGT] kms_flip_event_leak: exiting, ret=77
12105 00:24:26.366499 s, pipes: 16, outputs: 0
12106 00:24:26.376387 [1mSubtest plane-immutable-zpos: SKIP<8>[ 18.756248] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>
12107 00:24:26.376502 (0.000s)[0m
12108 00:24:26.376778 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
12110 00:24:26.379855 I<8>[ 18.765031] <LAVA_SIGNAL_TESTSET STOP>
12111 00:24:26.380143 Received signal: <TESTSET> STOP
12112 00:24:26.380245 Closing test_set kms_flip_event_leak
12113 00:24:26.386270 GT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.94-cip23 aarch64)
12114 00:24:26.392650 Using IGT_SRANDOM=1718929466 for randomisation
12115 00:24:26.392775 Opened device: /dev/dri/card0
12116 00:24:26.402420 No KMS driver or no outputs, pipes: 16, output<8>[ 18.785449] <LAVA_SIGNAL_TESTSET START kms_prop_blob>
12117 00:24:26.402534 s: 0
12118 00:24:26.402802 Received signal: <TESTSET> START kms_prop_blob
12119 00:24:26.402913 Starting test_set kms_prop_blob
12120 00:24:26.405937 [1mSubtest test-only: SKIP (0.000s)[0m
12121 00:24:26.412408 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.94-cip23 aarch64)
12122 00:24:26.418935 Using IGT_SRANDOM=1718929466 for randomisation
12123 00:24:26.419048 Opened device: /dev/dri/card0
12124 00:24:26.425815 No KMS driver<14>[ 18.808070] [IGT] kms_prop_blob: executing
12125 00:24:26.432167 or no outputs, <14>[ 18.814305] [IGT] kms_prop_blob: starting subtest basic
12126 00:24:26.438878 <14>[ 18.820937] [IGT] kms_prop_blob: finished subtest basic, SUCCESS
12127 00:24:26.445669 pipes: 16, outpu<14>[ 18.827385] [IGT] kms_prop_blob: exiting, ret=0
12128 00:24:26.445783 ts: 0
12129 00:24:26.452049 [1mSubtest plane-cursor-legacy: SKIP (0.000s)[0m
12130 00:24:26.458620 IGT-V<8>[ 18.837872] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>
12131 00:24:26.458909 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
12133 00:24:26.461853 ersion: 1.28-ga44ebfe (aarch64) (Linux: 6.1.94-cip23 aarch64)
12134 00:24:26.468788 Using IGT_SRANDOM=1718929466 for randomisation
12135 00:24:26.468899 Opened device: /dev/dri/card0
12136 00:24:26.475191 No KMS driver or n<14>[ 18.858971] [IGT] kms_prop_blob: executing
12137 00:24:26.484994 o outputs, pipes<14>[ 18.864291] [IGT] kms_prop_blob: starting subtest blob-prop-core
12138 00:24:26.492018 : 16, outputs: 0<14>[ 18.871824] [IGT] kms_prop_blob: finished subtest blob-prop-core, SUCCESS
12139 00:24:26.492130
12140 00:24:26.498315 [1mSubtest pl<14>[ 18.880397] [IGT] kms_prop_blob: exiting, ret=0
12141 00:24:26.501982 ane-invalid-params: SKIP (0.000s)[0m
12142 00:24:26.511745 IGT-Version: 1.28-ga44ebf<8>[ 18.890949] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-core RESULT=pass>
12143 00:24:26.512086 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-core RESULT=pass
12145 00:24:26.514688 e (aarch64) (Linux: 6.1.94-cip23 aarch64)
12146 00:24:26.518116 Using IGT_SRANDOM=1718929466 for randomisation
12147 00:24:26.521705 Opened device: /dev/dri/card0
12148 00:24:26.531393 No KMS driver or no outputs, pipes: 16<14>[ 18.912738] [IGT] kms_prop_blob: executing
12149 00:24:26.531510 , outputs: 0
12150 00:24:26.537918 [<14>[ 18.918094] [IGT] kms_prop_blob: starting subtest blob-prop-validate
12151 00:24:26.547930 1mSubtest plane-<14>[ 18.926026] [IGT] kms_prop_blob: finished subtest blob-prop-validate, SUCCESS
12152 00:24:26.554491 invalid-params-f<14>[ 18.934885] [IGT] kms_prop_blob: exiting, ret=0
12153 00:24:26.554604 ence: SKIP (0.000s)[0m
12154 00:24:26.564747 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-validate RESULT=pass
12156 00:24:26.568092 IGT-Version: 1.28-ga44ebfe (aarch64) (L<8>[ 18.945451] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-validate RESULT=pass>
12157 00:24:26.568210 inux: 6.1.94-cip23 aarch64)
12158 00:24:26.574481 Using IGT_SRANDOM=1718929466 for randomisation
12159 00:24:26.574617 Opened device: /dev/dri/card0
12160 00:24:26.581088 No KMS driver or no outputs, pipes: 16, outputs: 0
12161 00:24:26.584595 <14>[ 18.967301] [IGT] kms_prop_blob: executing
12162 00:24:26.594695 [1mSubtest crtc<14>[ 18.972943] [IGT] kms_prop_blob: starting subtest blob-prop-lifetime
12163 00:24:26.600966 -invalid-params:<14>[ 18.981061] [IGT] kms_prop_blob: finished subtest blob-prop-lifetime, SUCCESS
12164 00:24:26.607475 <14>[ 18.989831] [IGT] kms_prop_blob: exiting, ret=0
12165 00:24:26.607554 SKIP (0.000s)[0m
12166 00:24:26.620581 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux:<8>[ 18.999180] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-lifetime RESULT=pass>
12167 00:24:26.620682 6.1.94-cip23 aarch64)
12168 00:24:26.620913 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-lifetime RESULT=pass
12170 00:24:26.627648 Using IGT_SRANDOM=1718929466 for randomisation
12171 00:24:26.627726 Opened device: /dev/dri/card0
12172 00:24:26.634108 No KMS driver or no outputs, pipes: 16, outputs: 0
12173 00:24:26.637119 [1mS<14>[ 19.020870] [IGT] kms_prop_blob: executing
12174 00:24:26.646970 ubtest crtc-inva<14>[ 19.026615] [IGT] kms_prop_blob: starting subtest blob-multiple
12175 00:24:26.654077 lid-params-fence<14>[ 19.034165] [IGT] kms_prop_blob: finished subtest blob-multiple, SUCCESS
12176 00:24:26.660313 : SKIP (0.000s)<14>[ 19.042518] [IGT] kms_prop_blob: exiting, ret=0
12177 00:24:26.660446 [0m
12178 00:24:26.673810 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.94-cip23 a<8>[ 19.053043] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-multiple RESULT=pass>
12179 00:24:26.673928 arch64)
12180 00:24:26.674218 Received signal: <TESTCASE> TEST_CASE_ID=blob-multiple RESULT=pass
12182 00:24:26.676862 Using IGT_SRANDOM=1718929466 for randomisation
12183 00:24:26.680043 Opened device: /dev/dri/card0
12184 00:24:26.686676 No KMS driver or no outputs, pipes: 16, outputs: 0
12185 00:24:26.693388 [1mSubtest atomic-i<14>[ 19.074730] [IGT] kms_prop_blob: executing
12186 00:24:26.700183 nvalid-params: S<14>[ 19.080284] [IGT] kms_prop_blob: starting subtest invalid-get-prop-any
12187 00:24:26.709814 KIP (0.000s)[0m<14>[ 19.088227] [IGT] kms_prop_blob: finished subtest invalid-get-prop-any, SUCCESS
12188 00:24:26.709897
12189 00:24:26.716316 IGT-Version: 1<14>[ 19.097330] [IGT] kms_prop_blob: exiting, ret=0
12190 00:24:26.720087 .28-ga44ebfe (aarch64) (Linux: 6.1.94-cip23 aarch64)
12191 00:24:26.730007 Using IGT_<8>[ 19.107842] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>
12192 00:24:26.730253 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
12194 00:24:26.733049 SRANDOM=1718929466 for randomisation
12195 00:24:26.736620 Opened device: /dev/dri/card0
12196 00:24:26.739561 No KMS driver or no outputs, pipes: 16, outputs: 0
12197 00:24:26.746156 [1mSubtest atomic-plane-damage: SKIP (<14>[ 19.130237] [IGT] kms_prop_blob: executing
12198 00:24:26.749262 0.000s)[0m
12199 00:24:26.756006 IGT<14>[ 19.135516] [IGT] kms_prop_blob: starting subtest invalid-get-prop
12200 00:24:26.762938 -Version: 1.28-g<14>[ 19.143333] [IGT] kms_prop_blob: finished subtest invalid-get-prop, SUCCESS
12201 00:24:26.769180 a44ebfe (aarch64<14>[ 19.151972] [IGT] kms_prop_blob: exiting, ret=0
12202 00:24:26.772683 ) (Linux: 6.1.94-cip23 aarch64)
12203 00:24:26.782596 Using IGT_SRAND<8>[ 19.162322] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>
12204 00:24:26.782881 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
12206 00:24:26.785453 OM=1718929466 for randomisation
12207 00:24:26.788765 Opened device: /dev/dri/card0
12208 00:24:26.791978 No KMS driver or no outputs, pipes: 16, outputs: 0
12209 00:24:26.795567 [1mSubtest basic: SKIP (0.000s)[0m
12210 00:24:26.798933 IGT-Ve<14>[ 19.183247] [IGT] kms_prop_blob: executing
12211 00:24:26.808661 rsion: 1.28-ga44<14>[ 19.188739] [IGT] kms_prop_blob: starting subtest invalid-set-prop-any
12212 00:24:26.815261 <14>[ 19.196652] [IGT] kms_prop_blob: finished subtest invalid-set-prop-any, SUCCESS
12213 00:24:26.821967 ebfe (aarch64) (<14>[ 19.204480] [IGT] kms_prop_blob: exiting, ret=0
12214 00:24:26.825425 Linux: 6.1.94-cip23 aarch64)
12215 00:24:26.835294 Using IGT_SRANDOM=<8>[ 19.214783] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>
12216 00:24:26.835554 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
12218 00:24:26.838458 1718929466 for randomisation
12219 00:24:26.838543 Opened device: /dev/dri/card0
12220 00:24:26.841849 Starting subtest: basic
12221 00:24:26.845214 [1mSubtest basic: SUCCESS (0.000s)[0m
12222 00:24:26.851657 IGT-Version: 1.28-ga44ebfe (aarch<14>[ 19.235130] [IGT] kms_prop_blob: executing
12223 00:24:26.861326 64) (Linux: 6.1.<14>[ 19.241339] [IGT] kms_prop_blob: starting subtest invalid-set-prop
12224 00:24:26.868060 94-cip23 aarch64<14>[ 19.248942] [IGT] kms_prop_blob: finished subtest invalid-set-prop, SUCCESS
12225 00:24:26.871504 )
12226 00:24:26.874866 Using IGT_SRA<14>[ 19.257726] [IGT] kms_prop_blob: exiting, ret=0
12227 00:24:26.877889 NDOM=1718929466 for randomisation
12228 00:24:26.887811 Opened device: /dev/dri/card0<8>[ 19.268323] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>
12229 00:24:26.887892
12230 00:24:26.888136 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
12232 00:24:26.894836 Starting subte<8>[ 19.278192] <LAVA_SIGNAL_TESTSET STOP>
12233 00:24:26.894909 st: blob-prop-core
12234 00:24:26.895134 Received signal: <TESTSET> STOP
12235 00:24:26.895192 Closing test_set kms_prop_blob
12236 00:24:26.901340 [1mSubtest blob-prop-core: SUCCESS (0.000s)[0m
12237 00:24:26.908094 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.94-cip23 aarch64)
12238 00:24:26.911323 Using IGT_SRANDOM=1718929466 for randomisation
12239 00:24:26.914790 Received signal: <TESTSET> START kms_setmode
12240 00:24:26.914865 Starting test_set kms_setmode
12241 00:24:26.917638 Opened<8>[ 19.298461] <LAVA_SIGNAL_TESTSET START kms_setmode>
12242 00:24:26.917714 device: /dev/dri/card0
12243 00:24:26.921073 Starting subtest: blob-prop-validate
12244 00:24:26.927631 [1mSubtest blob-prop-validate: SUCCESS (0.000s)[0m
12245 00:24:26.934281 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.94-cip23 a<14>[ 19.318491] [IGT] kms_setmode: executing
12246 00:24:26.937598 arch64)
12247 00:24:26.944062 Using I<14>[ 19.324499] [IGT] kms_setmode: starting subtest basic
12248 00:24:26.951027 GT_SRANDOM=17189<14>[ 19.330942] [IGT] kms_setmode: finished subtest basic, SKIP
12249 00:24:26.957594 29466 for random<14>[ 19.338291] [IGT] kms_setmode: exiting, ret=77
12250 00:24:26.957710 isation
12251 00:24:26.960601 Opened device: /dev/dri/card0
12252 00:24:26.967681 Starting subtest: blob-p<8>[ 19.348681] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>
12253 00:24:26.967921 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
12255 00:24:26.970726 rop-lifetime
12256 00:24:26.974098 [1mSubtest blob-prop-lifetime: SUCCESS (0.000s)[0m
12257 00:24:26.980843 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.94-cip23 aarch64)
12258 00:24:26.987138 Using IGT_SRANDOM=171892<14>[ 19.369694] [IGT] kms_setmode: executing
12259 00:24:26.994255 9466 for randomi<14>[ 19.375174] [IGT] kms_setmode: starting subtest basic-clone-single-crtc
12260 00:24:26.997255 sation
12261 00:24:27.003870 Opened d<14>[ 19.383155] [IGT] kms_setmode: finished subtest basic-clone-single-crtc, SKIP
12262 00:24:27.010609 evice: /dev/dri/<14>[ 19.392207] [IGT] kms_setmode: exiting, ret=77
12263 00:24:27.010703 card0
12264 00:24:27.014056 Starting subtest: blob-multiple
12265 00:24:27.023787 [1mSubtest blob-multipl<8>[ 19.402680] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-clone-single-crtc RESULT=skip>
12266 00:24:27.024060 Received signal: <TESTCASE> TEST_CASE_ID=basic-clone-single-crtc RESULT=skip
12268 00:24:27.026673 e: SUCCESS (0.000s)[0m
12269 00:24:27.030369 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.94-cip23 aarch64)
12270 00:24:27.036956 Using IGT_SRANDOM=1718929466 for randomisation
12271 00:24:27.043530 Opened device: /dev<14>[ 19.424840] [IGT] kms_setmode: executing
12272 00:24:27.043609 /dri/card0
12273 00:24:27.050193 Star<14>[ 19.430443] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc
12274 00:24:27.060172 ting subtest: in<14>[ 19.438611] [IGT] kms_setmode: finished subtest invalid-clone-single-crtc, SKIP
12275 00:24:27.066638 valid-get-prop-a<14>[ 19.447845] [IGT] kms_setmode: exiting, ret=77
12276 00:24:27.066716 ny
12277 00:24:27.070227 [1mSubtest invalid-get-prop-any: SUCCESS (0.000s)[0m
12278 00:24:27.080124 IGT-<8>[ 19.458093] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip>
12279 00:24:27.080373 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip
12281 00:24:27.086607 Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.94-cip23 aarch64)
12282 00:24:27.089609 Using IGT_SRANDOM=1718929466 for randomisation
12283 00:24:27.093260 Opened device: /dev/dri/card0
12284 00:24:27.096777 Starting subtest:<14>[ 19.480373] [IGT] kms_setmode: executing
12285 00:24:27.106716 invalid-get-pro<14>[ 19.486409] [IGT] kms_setmode: starting subtest invalid-clone-exclusive-crtc
12286 00:24:27.106796 p
12287 00:24:27.116580 [1mSubtest i<14>[ 19.494763] [IGT] kms_setmode: finished subtest invalid-clone-exclusive-crtc, SKIP
12288 00:24:27.122949 nvalid-get-prop:<14>[ 19.504113] [IGT] kms_setmode: exiting, ret=77
12289 00:24:27.123028 SUCCESS (0.000s)[0m
12290 00:24:27.136371 IGT-Version: 1.28-ga44ebfe (aarch64) (Lin<8>[ 19.514778] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip>
12291 00:24:27.136620 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip
12293 00:24:27.139392 ux: 6.1.94-cip23 aarch64)
12294 00:24:27.142954 Using IGT_SRANDOM=1718929466 for randomisation
12295 00:24:27.146150 Opened device: /dev/dri/card0
12296 00:24:27.149692 Starting subtest: invalid-set-prop-any
12297 00:24:27.156291 [1mSubtest invalid-set-prop-a<14>[ 19.538266] [IGT] kms_setmode: executing
12298 00:24:27.162772 ny: SUCCESS (0.0<14>[ 19.544245] [IGT] kms_setmode: starting subtest clone-exclusive-crtc
12299 00:24:27.165766 00s)[0m
12300 00:24:27.172748 IGT-Ve<14>[ 19.552070] [IGT] kms_setmode: finished subtest clone-exclusive-crtc, SKIP
12301 00:24:27.179074 rsion: 1.28-ga44<14>[ 19.560714] [IGT] kms_setmode: exiting, ret=77
12302 00:24:27.182622 ebfe (aarch64) (Linux: 6.1.94-cip23 aarch64)
12303 00:24:27.192208 Using IGT_SRANDOM=<8>[ 19.571369] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clone-exclusive-crtc RESULT=skip>
12304 00:24:27.192475 Received signal: <TESTCASE> TEST_CASE_ID=clone-exclusive-crtc RESULT=skip
12306 00:24:27.195790 1718929466 for randomisation
12307 00:24:27.195866 Opened device: /dev/dri/card0
12308 00:24:27.198895 Starting subtest: invalid-set-prop
12309 00:24:27.205688 [1mSubtest invalid-set-prop: SUCCESS (0.000s)[0m
12310 00:24:27.209013 IGT-Version<14>[ 19.593367] [IGT] kms_setmode: executing
12311 00:24:27.218944 : 1.28-ga44ebfe <14>[ 19.598890] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc-stealing
12312 00:24:27.228868 (aarch64) (Linux<14>[ 19.607820] [IGT] kms_setmode: finished subtest invalid-clone-single-crtc-stealing, SKIP
12313 00:24:27.235344 : 6.1.94-cip23 a<14>[ 19.617785] [IGT] kms_setmode: exiting, ret=77
12314 00:24:27.235435 arch64)
12315 00:24:27.242566 Using IGT_SRANDOM=1718929467 for randomisation
12316 00:24:27.248958 Opened <8>[ 19.628310] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip>
12317 00:24:27.249216 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip
12319 00:24:27.255508 device: /dev/dri<8>[ 19.639642] <LAVA_SIGNAL_TESTSET STOP>
12320 00:24:27.255585 /card0
12321 00:24:27.255812 Received signal: <TESTSET> STOP
12322 00:24:27.255877 Closing test_set kms_setmode
12323 00:24:27.258477 Starting subtest: basic
12324 00:24:27.261820 No dynamic tests executed.
12325 00:24:27.265184 [1mSubtest basic: SKIP (0.000s)[0m
12326 00:24:27.268900 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.94-cip23 aarch64)
12327 00:24:27.278188 Using IGT_SRANDOM=1718929<8>[ 19.659232] <LAVA_SIGNAL_TESTSET START kms_vblank>
12328 00:24:27.278316 467 for randomisation
12329 00:24:27.278597 Received signal: <TESTSET> START kms_vblank
12330 00:24:27.278705 Starting test_set kms_vblank
12331 00:24:27.281861 Opened device: /dev/dri/card0
12332 00:24:27.285324 Starting subtest: basic-clone-single-crtc
12333 00:24:27.288216 No dynamic tests executed.
12334 00:24:27.291715 [1mSubtest basic-clone-single-crtc: SKIP (0.000s)[0m
12335 00:24:27.298304 IGT-Version: 1.28-ga44ebfe <14>[ 19.682355] [IGT] kms_vblank: executing
12336 00:24:27.304976 (aarch64) (Linux<14>[ 19.688312] [IGT] kms_vblank: exiting, ret=77
12337 00:24:27.307969 : 6.1.94-cip23 aarch64)
12338 00:24:27.318096 Using IGT_SRANDOM=1718929467 for random<8>[ 19.698517] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid RESULT=skip>
12339 00:24:27.318213 isation
12340 00:24:27.318489 Received signal: <TESTCASE> TEST_CASE_ID=invalid RESULT=skip
12342 00:24:27.321408 Opened device: /dev/dri/card0
12343 00:24:27.324660 Starting subtest: invalid-clone-single-crtc
12344 00:24:27.327989 No dynamic tests executed.
12345 00:24:27.334569 [1mSubtest invalid-clone-single-crtc: SKIP (0.<14>[ 19.719773] [IGT] kms_vblank: executing
12346 00:24:27.338027 000s)[0m
12347 00:24:27.341624 IGT-V<14>[ 19.724821] [IGT] kms_vblank: exiting, ret=77
12348 00:24:27.347744 ersion: 1.28-ga44ebfe (aarch64) (Linux: 6.1.94-cip23 aarch64)
12349 00:24:27.354696 U<8>[ 19.735083] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-id RESULT=skip>
12350 00:24:27.354951 Received signal: <TESTCASE> TEST_CASE_ID=crtc-id RESULT=skip
12352 00:24:27.358176 sing IGT_SRANDOM=1718929467 for randomisation
12353 00:24:27.361371 Opened device: /dev/dri/card0
12354 00:24:27.364835 Starting subtest: invalid-clone-exclusive-crtc
12355 00:24:27.367642 No dynamic tests executed.
12356 00:24:27.371212 [1mSu<14>[ 19.755581] [IGT] kms_vblank: executing
12357 00:24:27.377852 btest invalid-cl<14>[ 19.761091] [IGT] kms_vblank: exiting, ret=77
12358 00:24:27.381251 one-exclusive-crtc: SKIP (0.000s)[0m
12359 00:24:27.391411 IGT-Version: 1.28-ga44ebf<8>[ 19.771254] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=accuracy-idle RESULT=skip>
12360 00:24:27.391683 Received signal: <TESTCASE> TEST_CASE_ID=accuracy-idle RESULT=skip
12362 00:24:27.394360 e (aarch64) (Linux: 6.1.94-cip23 aarch64)
12363 00:24:27.397849 Using IGT_SRANDOM=1718929467 for randomisation
12364 00:24:27.400882 Opened device: /dev/dri/card0
12365 00:24:27.411031 Starting subtest: clone-exclusive-crtc<14>[ 19.792805] [IGT] kms_vblank: executing
12366 00:24:27.411105
12367 00:24:27.414577 No dynamic tes<14>[ 19.798157] [IGT] kms_vblank: exiting, ret=77
12368 00:24:27.417659 ts executed.
12369 00:24:27.427379 [1mSubtest clone-exclusive-crtc: SKIP (0.000s)[0<8>[ 19.808152] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-idle RESULT=skip>
12370 00:24:27.427457 m
12371 00:24:27.427685 Received signal: <TESTCASE> TEST_CASE_ID=query-idle RESULT=skip
12373 00:24:27.434055 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.94-cip23 aarch64)
12374 00:24:27.437430 Using IGT_SRANDOM=1718929467 for randomisation
12375 00:24:27.440727 Opened device: /dev/dri/card0
12376 00:24:27.447115 Starting s<14>[ 19.829411] [IGT] kms_vblank: executing
12377 00:24:27.450615 ubtest: invalid-<14>[ 19.834767] [IGT] kms_vblank: exiting, ret=77
12378 00:24:27.454174 clone-single-crtc-stealing
12379 00:24:27.457142 No dynamic tests executed.
12380 00:24:27.464053 [1mSubt<8>[ 19.844971] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-idle-hang RESULT=skip>
12381 00:24:27.464339 Received signal: <TESTCASE> TEST_CASE_ID=query-idle-hang RESULT=skip
12383 00:24:27.470377 est invalid-clone-single-crtc-stealing: SKIP (0.000s)[0m
12384 00:24:27.476909 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.94-cip23 aarch64)
12385 00:24:27.483638 Using IGT_SRANDOM=1718929467 for <14>[ 19.866476] [IGT] kms_vblank: executing
12386 00:24:27.483759 randomisation
12387 00:24:27.490271 O<14>[ 19.871908] [IGT] kms_vblank: exiting, ret=77
12388 00:24:27.493915 pened device: /dev/dri/card0
12389 00:24:27.500337 Received signal: <TESTCASE> TEST_CASE_ID=query-forked RESULT=skip
12391 00:24:27.503667 No KMS driver or no outputs, pipes<8>[ 19.882182] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked RESULT=skip>
12392 00:24:27.503748 : 16, outputs: 0
12393 00:24:27.507200 [1mSubtest invalid: SKIP (0.000s)[0m
12394 00:24:27.513663 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.94-cip23 aarch64)
12395 00:24:27.520267 Using IGT_SRANDOM=1718929467 for r<14>[ 19.903836] [IGT] kms_vblank: executing
12396 00:24:27.520344 andomisation
12397 00:24:27.526926 Op<14>[ 19.908967] [IGT] kms_vblank: exiting, ret=77
12398 00:24:27.529877 ened device: /dev/dri/card0
12399 00:24:27.540094 No KMS driver or no outputs, pipes:<8>[ 19.919204] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked-hang RESULT=skip>
12400 00:24:27.540172 16, outputs: 0
12401 00:24:27.540399 Received signal: <TESTCASE> TEST_CASE_ID=query-forked-hang RESULT=skip
12403 00:24:27.543371 [1mSubtest crtc-id: SKIP (0.000s)[0m
12404 00:24:27.550249 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.94-cip23 aarch64)
12405 00:24:27.556743 Using IGT_SRANDOM=1718929467 for ra<14>[ 19.941415] [IGT] kms_vblank: executing
12406 00:24:27.559702 ndomisation
12407 00:24:27.566627 Opened device: /dev<14>[ 19.947692] [IGT] kms_vblank: exiting, ret=77
12408 00:24:27.566704 /dri/card0
12409 00:24:27.569736 No KMS driver or no outputs, pipes: 16, outputs: 0
12410 00:24:27.576131 [1mSubtest accuracy-idle: SKIP (0.000s)[0m
12411 00:24:27.582767 IG<8>[ 19.962689] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-busy RESULT=skip>
12412 00:24:27.583014 Received signal: <TESTCASE> TEST_CASE_ID=query-busy RESULT=skip
12414 00:24:27.586319 T-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.94-cip23 aarch64)
12415 00:24:27.592993 Using IGT_SRANDOM=1718929467 for randomisation
12416 00:24:27.593093 Opened device: /dev/dri/card0
12417 00:24:27.599617 No KMS driver or no outputs, pipes: 16, outputs: 0
12418 00:24:27.602760 [1mSubtest<14>[ 19.986765] [IGT] kms_vblank: executing
12419 00:24:27.609583 query-idle: SKI<14>[ 19.992647] [IGT] kms_vblank: exiting, ret=77
12420 00:24:27.612524 P (0.000s)[0m
12421 00:24:27.622911 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1<8>[ 20.002778] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-busy-hang RESULT=skip>
12422 00:24:27.623159 Received signal: <TESTCASE> TEST_CASE_ID=query-busy-hang RESULT=skip
12424 00:24:27.625827 .94-cip23 aarch64)
12425 00:24:27.629603 Using IGT_SRANDOM=1718929467 for randomisation
12426 00:24:27.632480 Opened device: /dev/dri/card0
12427 00:24:27.636074 No KMS driver or no outputs, pipes: 16, outputs: 0
12428 00:24:27.642556 [1mSubte<14>[ 20.024728] [IGT] kms_vblank: executing
12429 00:24:27.645478 st query-idle-ha<14>[ 20.029857] [IGT] kms_vblank: exiting, ret=77
12430 00:24:27.648879 ng: SKIP (0.000s)[0m
12431 00:24:27.659363 IGT-Version: 1.28-ga44ebfe (aarch64) (Lin<8>[ 20.039919] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked-busy RESULT=skip>
12432 00:24:27.659658 Received signal: <TESTCASE> TEST_CASE_ID=query-forked-busy RESULT=skip
12434 00:24:27.662288 ux: 6.1.94-cip23 aarch64)
12435 00:24:27.665865 Using IGT_SRANDOM=1718929467 for randomisation
12436 00:24:27.668801 Opened device: /dev/dri/card0
12437 00:24:27.675645 No KMS driver or no outputs, pipes: 16, outputs: 0
12438 00:24:27.679041 [<14>[ 20.062115] [IGT] kms_vblank: executing
12439 00:24:27.685631 1mSubtest query-<14>[ 20.066967] [IGT] kms_vblank: exiting, ret=77
12440 00:24:27.685710 forked: SKIP (0.000s)[0m
12441 00:24:27.698649 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.94-c<8>[ 20.079473] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked-busy-hang RESULT=skip>
12442 00:24:27.698896 Received signal: <TESTCASE> TEST_CASE_ID=query-forked-busy-hang RESULT=skip
12444 00:24:27.701993 ip23 aarch64)
12445 00:24:27.705311 Using IGT_SRANDOM=1718929467 for randomisation
12446 00:24:27.708899 Opened device: /dev/dri/card0
12447 00:24:27.711932 No KMS driver or no outputs, pipes: 16, outputs: 0
12448 00:24:27.718632 [1mSubtest qu<14>[ 20.101165] [IGT] kms_vblank: executing
12449 00:24:27.721838 ery-forked-hang:<14>[ 20.106210] [IGT] kms_vblank: exiting, ret=77
12450 00:24:27.725525 SKIP (0.000s)[0m
12451 00:24:27.735250 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux:<8>[ 20.116684] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-idle RESULT=skip>
12452 00:24:27.735607 Received signal: <TESTCASE> TEST_CASE_ID=wait-idle RESULT=skip
12454 00:24:27.738215 6.1.94-cip23 aarch64)
12455 00:24:27.741704 Using IGT_SRANDOM=1718929467 for randomisation
12456 00:24:27.745382 Opened device: /dev/dri/card0
12457 00:24:27.748282 No KMS driver or no outputs, pipes: 16, outputs: 0
12458 00:24:27.751827 [1mSubtest query-busy: SKIP (0.000s)[0m
12459 00:24:27.758108 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.94-cip23 aarch64)
12460 00:24:27.765009 Using IGT_SRANDOM=1718<14>[ 20.148557] [IGT] kms_vblank: executing
12461 00:24:27.771542 929467 for rando<14>[ 20.154125] [IGT] kms_vblank: exiting, ret=77
12462 00:24:27.771620 misation
12463 00:24:27.774687 Opened device: /dev/dri/card0
12464 00:24:27.784813 No KMS driver or no outputs, pipes: 16,<8>[ 20.165532] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-idle-hang RESULT=skip>
12465 00:24:27.785065 Received signal: <TESTCASE> TEST_CASE_ID=wait-idle-hang RESULT=skip
12467 00:24:27.788330 outputs: 0
12468 00:24:27.791286 [1mSubtest query-busy-hang: SKIP (0.000s)[0m
12469 00:24:27.797953 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.94-cip23 aarch64)
12470 00:24:27.804828 Using IGT_SRANDOM=1718929467 fo<14>[ 20.187436] [IGT] kms_vblank: executing
12471 00:24:27.804910 r randomisation
12472 00:24:27.811431 <14>[ 20.192260] [IGT] kms_vblank: exiting, ret=77
12473 00:24:27.811513
12474 00:24:27.811592 Opened device: /dev/dri/card0
12475 00:24:27.821415 No KMS driver or no outputs, pip<8>[ 20.202661] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked RESULT=skip>
12476 00:24:27.821664 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked RESULT=skip
12478 00:24:27.824792 es: 16, outputs: 0
12479 00:24:27.827797 [1mSubtest query-forked-busy: SKIP (0.000s)[0m
12480 00:24:27.834584 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.94-cip23 aarch64)
12481 00:24:27.840888 Using IGT_SRANDOM=1718<14>[ 20.223838] [IGT] kms_vblank: executing
12482 00:24:27.847798 929467 for rando<14>[ 20.229215] [IGT] kms_vblank: exiting, ret=77
12483 00:24:27.847880 misation
12484 00:24:27.851333 Opened device: /dev/dri/card0
12485 00:24:27.860933 No KMS driver or no out<8>[ 20.239361] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked-hang RESULT=skip>
12486 00:24:27.861038 puts, pipes: 16, outputs: 0
12487 00:24:27.861296 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked-hang RESULT=skip
12489 00:24:27.867220 [1mSubtest query-forked-busy-hang: SKIP (0.000s)[0m
12490 00:24:27.874185 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.94-cip23 aarch64)
12491 00:24:27.877556 Using IG<14>[ 20.260726] [IGT] kms_vblank: executing
12492 00:24:27.884128 T_SRANDOM=171892<14>[ 20.266300] [IGT] kms_vblank: exiting, ret=77
12493 00:24:27.887637 9467 for randomisation
12494 00:24:27.887719 Opened device: /dev/dri/card0
12495 00:24:27.897061 No KMS dr<8>[ 20.276539] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-busy RESULT=skip>
12496 00:24:27.897307 Received signal: <TESTCASE> TEST_CASE_ID=wait-busy RESULT=skip
12498 00:24:27.900621 iver or no outputs, pipes: 16, outputs: 0
12499 00:24:27.904002 [1mSubtest wait-idle: SKIP (0.000s)[0m
12500 00:24:27.910354 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.94-cip23 aarch64)
12501 00:24:27.913894 Using I<14>[ 20.297223] [IGT] kms_vblank: executing
12502 00:24:27.920763 GT_SRANDOM=17189<14>[ 20.302980] [IGT] kms_vblank: exiting, ret=77
12503 00:24:27.924056 29467 for randomisation
12504 00:24:27.927210 Opened device: /dev/dri/card0
12505 00:24:27.933422 No KMS d<8>[ 20.313182] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-busy-hang RESULT=skip>
12506 00:24:27.933682 Received signal: <TESTCASE> TEST_CASE_ID=wait-busy-hang RESULT=skip
12508 00:24:27.936983 river or no outputs, pipes: 16, outputs: 0
12509 00:24:27.940029 [1mSubtest wait-idle-hang: SKIP (0.000s)[0m
12510 00:24:27.946906 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.94-cip23 aarch64)
12511 00:24:27.950257 U<14>[ 20.334081] [IGT] kms_vblank: executing
12512 00:24:27.956768 sing IGT_SRANDOM<14>[ 20.340010] [IGT] kms_vblank: exiting, ret=77
12513 00:24:27.960329 =1718929467 for randomisation
12514 00:24:27.963363 Opened device: /dev/dri/card0
12515 00:24:27.969890 No<8>[ 20.350444] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked-busy RESULT=skip>
12516 00:24:27.970139 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked-busy RESULT=skip
12518 00:24:27.973492 KMS driver or no outputs, pipes: 16, outputs: 0
12519 00:24:27.980173 [1mSubtest wait-forked: SKIP (0.000s)[0m
12520 00:24:27.989689 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.94-cip23 aarch64)<14>[ 20.371739] [IGT] kms_vblank: executing
12521 00:24:27.989770
12522 00:24:27.993182 Using IGT_SRAN<14>[ 20.377206] [IGT] kms_vblank: exiting, ret=77
12523 00:24:27.996180 DOM=1718929467 for randomisation
12524 00:24:27.999657 Opened device: /dev/dri/card0
12525 00:24:28.006409 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked-busy-hang RESULT=skip
12527 00:24:28.009545 <8>[ 20.387633] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked-busy-hang RESULT=skip>
12528 00:24:28.009624
12529 00:24:28.012986 No KMS driver or no outputs, pipes: 16, outputs: 0
12530 00:24:28.016344 [1mSubtest wait-forked-hang: SKIP (0.000s)[0m
12531 00:24:28.026097 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.94-cip23 <14>[ 20.409647] [IGT] kms_vblank: executing
12532 00:24:28.026177 aarch64)
12533 00:24:28.032974 Using <14>[ 20.414972] [IGT] kms_vblank: exiting, ret=77
12534 00:24:28.036166 IGT_SRANDOM=1718929467 for randomisation
12535 00:24:28.046065 Opened device: /dev/dr<8>[ 20.425279] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-idle RESULT=skip>
12536 00:24:28.046190 i/card0
12537 00:24:28.046475 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-idle RESULT=skip
12539 00:24:28.052719 No KMS driver or no outputs, pipes: 16, outputs: 0
12540 00:24:28.056250 [1mSubtest wait-busy: SKIP (0.000s)[0m
12541 00:24:28.062877 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.94-cip23<14>[ 20.447768] [IGT] kms_vblank: executing
12542 00:24:28.065904 aarch64)
12543 00:24:28.069283 Using<14>[ 20.452547] [IGT] kms_vblank: exiting, ret=77
12544 00:24:28.072800 IGT_SRANDOM=1718929468 for randomisation
12545 00:24:28.082542 Opened device: /dev/d<8>[ 20.462709] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-idle-hang RESULT=skip>
12546 00:24:28.082864 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-idle-hang RESULT=skip
12548 00:24:28.085919 ri/card0
12549 00:24:28.088820 No KMS driver or no outputs, pipes: 16, outputs: 0
12550 00:24:28.092427 [1mSubtest wait-busy-hang: SKIP (0.000s)[0m
12551 00:24:28.102435 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.94<14>[ 20.485681] [IGT] kms_vblank: executing
12552 00:24:28.102571 -cip23 aarch64)
12553 00:24:28.108818 <14>[ 20.490548] [IGT] kms_vblank: exiting, ret=77
12554 00:24:28.108944
12555 00:24:28.112180 Using IGT_SRANDOM=1718929468 for randomisation
12556 00:24:28.121923 Opened device: <8>[ 20.500903] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-dpms-rpm RESULT=skip>
12557 00:24:28.122029 /dev/dri/card0
12558 00:24:28.122259 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-dpms-rpm RESULT=skip
12560 00:24:28.128855 No KMS driver or no outputs, pipes: 16, outputs: 0
12561 00:24:28.132257 [1mSubtest wait-forked-busy: SKIP (0.000s)[0m
12562 00:24:28.138756 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux<14>[ 20.523002] [IGT] kms_vblank: executing
12563 00:24:28.145284 : 6.1.94-cip23 a<14>[ 20.528378] [IGT] kms_vblank: exiting, ret=77
12564 00:24:28.145362 arch64)
12565 00:24:28.151630 Using IGT_SRANDOM=1718929468 for randomisation
12566 00:24:28.158479 Opened <8>[ 20.538679] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-dpms-suspend RESULT=skip>
12567 00:24:28.158726 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-dpms-suspend RESULT=skip
12569 00:24:28.161987 device: /dev/dri/card0
12570 00:24:28.164861 No KMS driver or no outputs, pipes: 16, outputs: 0
12571 00:24:28.171903 [1mSubtest wait-forked-busy-hang: SKIP (0.000s)[0m
12572 00:24:28.178285 IGT-Version: 1.28-ga44ebfe (aa<14>[ 20.561523] [IGT] kms_vblank: executing
12573 00:24:28.184612 rch64) (Linux: 6<14>[ 20.566731] [IGT] kms_vblank: exiting, ret=77
12574 00:24:28.184745 .1.94-cip23 aarch64)
12575 00:24:28.197939 Using IGT_SRANDOM=1718929468 for randomisa<8>[ 20.577139] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-suspend RESULT=skip>
12576 00:24:28.198053 tion
12577 00:24:28.198327 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-suspend RESULT=skip
12579 00:24:28.201583 Opened device: /dev/dri/card0
12580 00:24:28.204810 No KMS driver or no outputs, pipes: 16, outputs: 0
12581 00:24:28.211661 [1mSubtest ts-continuation-idle: SKIP (0.000s)[0m
12582 00:24:28.214468 IGT-Version: 1.28-<14>[ 20.598977] [IGT] kms_vblank: executing
12583 00:24:28.221088 ga44ebfe (aarch6<14>[ 20.604814] [IGT] kms_vblank: exiting, ret=77
12584 00:24:28.224656 4) (Linux: 6.1.94-cip23 aarch64)
12585 00:24:28.234214 Using IGT_SRANDOM=1718929468 f<8>[ 20.614923] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-modeset RESULT=skip>
12586 00:24:28.234496 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-modeset RESULT=skip
12588 00:24:28.237722 or randomisation
12589 00:24:28.241051 Opened device: /dev/dri/card0
12590 00:24:28.244347 No KMS driver or no outputs, pipes: 16, outputs: 0
12591 00:24:28.251026 [1mSubtest ts-continuation-idle-hang: SKIP (0.000s)[0m
12592 00:24:28.254187 I<14>[ 20.637470] [IGT] kms_vblank: executing
12593 00:24:28.260976 GT-Version: 1.28<14>[ 20.642428] [IGT] kms_vblank: exiting, ret=77
12594 00:24:28.264132 -ga44ebfe (aarch64) (Linux: 6.1.94-cip23 aarch64)
12595 00:24:28.274301 Using IGT_SRA<8>[ 20.652642] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-modeset-hang RESULT=skip>
12596 00:24:28.274544 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-modeset-hang RESULT=skip
12598 00:24:28.277752 NDOM=1718929468 for randomisation
12599 00:24:28.281145 Opened device: /dev/dri/card0
12600 00:24:28.283977 No KMS driver or no outputs, pipes: 16, outputs: 0
12601 00:24:28.290918 [1mSubtest ts-continuation-dpms-rpm: SKIP<14>[ 20.675010] [IGT] kms_vblank: executing
12602 00:24:28.293929 (0.000s)[0m
12603 00:24:28.297131 I<14>[ 20.680774] [IGT] kms_vblank: exiting, ret=77
12604 00:24:28.310682 GT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.94-cip23 aarch64<8>[ 20.690872] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-modeset-rpm RESULT=skip>
12605 00:24:28.310926 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-modeset-rpm RESULT=skip
12607 00:24:28.313891 )
12608 00:24:28.317260 Using IGT_SRANDOM=1718929468 <8>[ 20.701614] <LAVA_SIGNAL_TESTSET STOP>
12609 00:24:28.317504 Received signal: <TESTSET> STOP
12610 00:24:28.317566 Closing test_set kms_vblank
12611 00:24:28.327391 for randomisatio<8>[ 20.707987] <LAVA_SIGNAL_ENDRUN 0_igt-kms-mediatek 14479141_1.5.2.3.1>
12612 00:24:28.327468 n
12613 00:24:28.327694 Received signal: <ENDRUN> 0_igt-kms-mediatek 14479141_1.5.2.3.1
12614 00:24:28.327772 Ending use of test pattern.
12615 00:24:28.327827 Ending test lava.0_igt-kms-mediatek (14479141_1.5.2.3.1), duration 6.14
12617 00:24:28.330226 Opened device: /dev/dri/card0
12618 00:24:28.333517 No KMS driver or no outputs, pipes: 16, outputs: 0
12619 00:24:28.340376 [1mSubtest ts-continuation-dpms-suspend: SKIP (0.000s)[0m
12620 00:24:28.346733 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.94-cip23 aarch64)
12621 00:24:28.350084 Using IGT_SRANDOM=1718929468 for randomisation
12622 00:24:28.353437 Opened device: /dev/dri/card0
12623 00:24:28.357001 No KMS driver or no outputs, pipes: 16, outputs: 0
12624 00:24:28.363254 [1mSubtest ts-continuation-suspend: SKIP (0.000s)[0m
12625 00:24:28.366508 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.94-cip23 aarch64)
12626 00:24:28.373391 Using IGT_SRANDOM=1718929468 for randomisation
12627 00:24:28.373467 Opened device: /dev/dri/card0
12628 00:24:28.379970 No KMS driver or no outputs, pipes: 16, outputs: 0
12629 00:24:28.383009 [1mSubtest ts-continuation-modeset: SKIP (0.000s)[0m
12630 00:24:28.390051 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.94-cip23 aarch64)
12631 00:24:28.392978 Using IGT_SRANDOM=1718929468 for randomisation
12632 00:24:28.396203 Opened device: /dev/dri/card0
12633 00:24:28.403318 No KMS driver or no outputs, pipes: 16, outputs: 0
12634 00:24:28.406283 [1mSubtest ts-continuation-modeset-hang: SKIP (0.000s)[0m
12635 00:24:28.412781 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.94-cip23 aarch64)
12636 00:24:28.416470 Using IGT_SRANDOM=1718929468 for randomisation
12637 00:24:28.419564 Opened device: /dev/dri/card0
12638 00:24:28.423007 No KMS driver or no outputs, pipes: 16, outputs: 0
12639 00:24:28.429566 [1mSubtest ts-continuation-modeset-rpm: SKIP (0.000s)[0m
12640 00:24:28.429681 + set +x
12641 00:24:28.432908 <LAVA_TEST_RUNNER EXIT>
12642 00:24:28.433195 ok: lava_test_shell seems to have completed
12643 00:24:28.436221 accuracy-idle:
result: skip
set: kms_vblank
addfb25-4-tiled:
result: skip
set: kms_addfb_basic
addfb25-bad-modifier:
result: fail
set: kms_addfb_basic
addfb25-framebuffer-vs-set-tiling:
result: skip
set: kms_addfb_basic
addfb25-modifier-no-flag:
result: pass
set: kms_addfb_basic
addfb25-x-tiled-legacy:
result: skip
set: kms_addfb_basic
addfb25-x-tiled-mismatch-legacy:
result: skip
set: kms_addfb_basic
addfb25-y-tiled-legacy:
result: skip
set: kms_addfb_basic
addfb25-y-tiled-small-legacy:
result: skip
set: kms_addfb_basic
addfb25-yf-tiled-legacy:
result: skip
set: kms_addfb_basic
atomic-invalid-params:
result: skip
set: kms_atomic
atomic-plane-damage:
result: skip
set: kms_atomic
bad-pitch-0:
result: pass
set: kms_addfb_basic
bad-pitch-1024:
result: pass
set: kms_addfb_basic
bad-pitch-128:
result: pass
set: kms_addfb_basic
bad-pitch-256:
result: pass
set: kms_addfb_basic
bad-pitch-32:
result: pass
set: kms_addfb_basic
bad-pitch-63:
result: pass
set: kms_addfb_basic
bad-pitch-65536:
result: pass
set: kms_addfb_basic
bad-pitch-999:
result: pass
set: kms_addfb_basic
basic:
result: skip
set: kms_setmode
basic-auth:
result: pass
set: core_auth
basic-clone-single-crtc:
result: skip
set: kms_setmode
basic-x-tiled-legacy:
result: skip
set: kms_addfb_basic
basic-y-tiled-legacy:
result: skip
set: kms_addfb_basic
blob-multiple:
result: pass
set: kms_prop_blob
blob-prop-core:
result: pass
set: kms_prop_blob
blob-prop-lifetime:
result: pass
set: kms_prop_blob
blob-prop-validate:
result: pass
set: kms_prop_blob
bo-too-small:
result: skip
set: kms_addfb_basic
bo-too-small-due-to-tiling:
result: skip
set: kms_addfb_basic
clobberred-modifier:
result: skip
set: kms_addfb_basic
clone-exclusive-crtc:
result: skip
set: kms_setmode
core_getclient: pass
core_getstats: pass
core_getversion: pass
core_setmaster_vs_auth: pass
crtc-id:
result: skip
set: kms_vblank
crtc-invalid-params:
result: skip
set: kms_atomic
crtc-invalid-params-fence:
result: skip
set: kms_atomic
empty-block:
result: skip
set: drm_read
empty-nonblock:
result: skip
set: drm_read
fault-buffer:
result: skip
set: drm_read
framebuffer-vs-set-tiling:
result: skip
set: kms_addfb_basic
getclient-master-drop:
result: pass
set: core_auth
getclient-simple:
result: pass
set: core_auth
invalid:
result: skip
set: kms_vblank
invalid-buffer:
result: skip
set: drm_read
invalid-clone-exclusive-crtc:
result: skip
set: kms_setmode
invalid-clone-single-crtc:
result: skip
set: kms_setmode
invalid-clone-single-crtc-stealing:
result: skip
set: kms_setmode
invalid-get-prop:
result: pass
set: kms_prop_blob
invalid-get-prop-any:
result: pass
set: kms_prop_blob
invalid-set-prop:
result: pass
set: kms_prop_blob
invalid-set-prop-any:
result: pass
set: kms_prop_blob
invalid-smem-bo-on-discrete:
result: skip
set: kms_addfb_basic
legacy-format:
result: pass
set: kms_addfb_basic
many-magics:
result: pass
set: core_auth
master-rmfb:
result: pass
set: kms_addfb_basic
no-handle:
result: pass
set: kms_addfb_basic
plane-cursor-legacy:
result: skip
set: kms_atomic
plane-immutable-zpos:
result: skip
set: kms_atomic
plane-invalid-params:
result: skip
set: kms_atomic
plane-invalid-params-fence:
result: skip
set: kms_atomic
plane-overlay-legacy:
result: skip
set: kms_atomic
plane-primary-legacy:
result: skip
set: kms_atomic
plane-primary-overlay-mutable-zpos:
result: skip
set: kms_atomic
query-busy:
result: skip
set: kms_vblank
query-busy-hang:
result: skip
set: kms_vblank
query-forked:
result: skip
set: kms_vblank
query-forked-busy:
result: skip
set: kms_vblank
query-forked-busy-hang:
result: skip
set: kms_vblank
query-forked-hang:
result: skip
set: kms_vblank
query-idle:
result: skip
set: kms_vblank
query-idle-hang:
result: skip
set: kms_vblank
short-buffer-block:
result: skip
set: drm_read
short-buffer-nonblock:
result: skip
set: drm_read
short-buffer-wakeup:
result: skip
set: drm_read
size-max:
result: skip
set: kms_addfb_basic
small-bo:
result: skip
set: kms_addfb_basic
test-only:
result: skip
set: kms_atomic
tile-pitch-mismatch:
result: skip
set: kms_addfb_basic
too-high:
result: skip
set: kms_addfb_basic
too-wide:
result: skip
set: kms_addfb_basic
ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
ts-continuation-idle:
result: skip
set: kms_vblank
ts-continuation-idle-hang:
result: skip
set: kms_vblank
ts-continuation-modeset:
result: skip
set: kms_vblank
ts-continuation-modeset-hang:
result: skip
set: kms_vblank
ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
ts-continuation-suspend:
result: skip
set: kms_vblank
unused-handle:
result: pass
set: kms_addfb_basic
unused-modifier:
result: pass
set: kms_addfb_basic
unused-offsets:
result: pass
set: kms_addfb_basic
unused-pitches:
result: pass
set: kms_addfb_basic
wait-busy:
result: skip
set: kms_vblank
wait-busy-hang:
result: skip
set: kms_vblank
wait-forked:
result: skip
set: kms_vblank
wait-forked-busy:
result: skip
set: kms_vblank
wait-forked-busy-hang:
result: skip
set: kms_vblank
wait-forked-hang:
result: skip
set: kms_vblank
wait-idle:
result: skip
set: kms_vblank
wait-idle-hang:
result: skip
set: kms_vblank
12644 00:24:28.436463 end: 3.1 lava-test-shell (duration 00:00:07) [common]
12645 00:24:28.436589 end: 3 lava-test-retry (duration 00:00:07) [common]
12646 00:24:28.436760 start: 4 finalize (timeout 00:07:12) [common]
12647 00:24:28.436896 start: 4.1 power-off (timeout 00:00:30) [common]
12648 00:24:28.437122 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-8', '--port=1', '--command=off']
12649 00:24:28.635310 >> Command sent successfully.
12650 00:24:28.638465 Returned 0 in 0 seconds
12651 00:24:28.738795 end: 4.1 power-off (duration 00:00:00) [common]
12653 00:24:28.739061 start: 4.2 read-feedback (timeout 00:07:11) [common]
12654 00:24:28.739289 Listened to connection for namespace 'common' for up to 1s
12655 00:24:29.739317 Finalising connection for namespace 'common'
12656 00:24:29.739495 Disconnecting from shell: Finalise
12657 00:24:29.739598 / #
12658 00:24:29.839884 end: 4.2 read-feedback (duration 00:00:01) [common]
12659 00:24:29.840027 end: 4 finalize (duration 00:00:01) [common]
12660 00:24:29.840162 Cleaning after the job
12661 00:24:29.840278 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14479141/tftp-deploy-0vfhrgoz/ramdisk
12662 00:24:29.846370 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14479141/tftp-deploy-0vfhrgoz/kernel
12663 00:24:29.861314 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14479141/tftp-deploy-0vfhrgoz/dtb
12664 00:24:29.861544 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14479141/tftp-deploy-0vfhrgoz/modules
12665 00:24:29.866580 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14479141
12666 00:24:29.971572 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14479141
12667 00:24:29.971722 Job finished correctly