Boot log: mt8183-kukui-jacuzzi-juniper-sku16
- Errors: 0
- Kernel Errors: 43
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 89
1 01:55:50.015418 lava-dispatcher, installed at version: 2024.03
2 01:55:50.015619 start: 0 validate
3 01:55:50.015760 Start time: 2024-06-21 01:55:50.015752+00:00 (UTC)
4 01:55:50.015881 Using caching service: 'http://localhost/cache/?uri=%s'
5 01:55:50.016010 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 01:55:50.277487 Using caching service: 'http://localhost/cache/?uri=%s'
7 01:55:50.278163 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.94-cip23%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 01:55:50.538522 Using caching service: 'http://localhost/cache/?uri=%s'
9 01:55:50.539288 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.94-cip23%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8183-kukui-jacuzzi-juniper-sku16.dtb exists
10 01:55:50.803125 Using caching service: 'http://localhost/cache/?uri=%s'
11 01:55:50.803831 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 01:55:51.058865 Using caching service: 'http://localhost/cache/?uri=%s'
13 01:55:51.059648 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.94-cip23%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 01:55:51.328416 validate duration: 1.31
16 01:55:51.328698 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 01:55:51.328802 start: 1.1 download-retry (timeout 00:10:00) [common]
18 01:55:51.328887 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 01:55:51.329007 Not decompressing ramdisk as can be used compressed.
20 01:55:51.329090 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 01:55:51.329152 saving as /var/lib/lava/dispatcher/tmp/14479169/tftp-deploy-fdqb7x23/ramdisk/initrd.cpio.gz
22 01:55:51.329217 total size: 5628169 (5 MB)
23 01:55:51.330509 progress 0 % (0 MB)
24 01:55:51.332261 progress 5 % (0 MB)
25 01:55:51.333873 progress 10 % (0 MB)
26 01:55:51.335236 progress 15 % (0 MB)
27 01:55:51.336766 progress 20 % (1 MB)
28 01:55:51.338153 progress 25 % (1 MB)
29 01:55:51.339666 progress 30 % (1 MB)
30 01:55:51.341178 progress 35 % (1 MB)
31 01:55:51.342547 progress 40 % (2 MB)
32 01:55:51.344076 progress 45 % (2 MB)
33 01:55:51.345443 progress 50 % (2 MB)
34 01:55:51.346955 progress 55 % (2 MB)
35 01:55:51.348475 progress 60 % (3 MB)
36 01:55:51.349847 progress 65 % (3 MB)
37 01:55:51.351488 progress 70 % (3 MB)
38 01:55:51.352892 progress 75 % (4 MB)
39 01:55:51.354539 progress 80 % (4 MB)
40 01:55:51.355876 progress 85 % (4 MB)
41 01:55:51.357523 progress 90 % (4 MB)
42 01:55:51.359012 progress 95 % (5 MB)
43 01:55:51.360458 progress 100 % (5 MB)
44 01:55:51.360658 5 MB downloaded in 0.03 s (170.71 MB/s)
45 01:55:51.360810 end: 1.1.1 http-download (duration 00:00:00) [common]
47 01:55:51.361050 end: 1.1 download-retry (duration 00:00:00) [common]
48 01:55:51.361135 start: 1.2 download-retry (timeout 00:10:00) [common]
49 01:55:51.361218 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 01:55:51.361403 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.94-cip23/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 01:55:51.361472 saving as /var/lib/lava/dispatcher/tmp/14479169/tftp-deploy-fdqb7x23/kernel/Image
52 01:55:51.361533 total size: 54813184 (52 MB)
53 01:55:51.361594 No compression specified
54 01:55:51.362765 progress 0 % (0 MB)
55 01:55:51.377212 progress 5 % (2 MB)
56 01:55:51.391789 progress 10 % (5 MB)
57 01:55:51.406284 progress 15 % (7 MB)
58 01:55:51.420422 progress 20 % (10 MB)
59 01:55:51.434454 progress 25 % (13 MB)
60 01:55:51.448374 progress 30 % (15 MB)
61 01:55:51.462510 progress 35 % (18 MB)
62 01:55:51.476437 progress 40 % (20 MB)
63 01:55:51.490410 progress 45 % (23 MB)
64 01:55:51.504389 progress 50 % (26 MB)
65 01:55:51.518452 progress 55 % (28 MB)
66 01:55:51.532346 progress 60 % (31 MB)
67 01:55:51.546547 progress 65 % (34 MB)
68 01:55:51.560396 progress 70 % (36 MB)
69 01:55:51.574456 progress 75 % (39 MB)
70 01:55:51.588310 progress 80 % (41 MB)
71 01:55:51.601927 progress 85 % (44 MB)
72 01:55:51.615689 progress 90 % (47 MB)
73 01:55:51.629161 progress 95 % (49 MB)
74 01:55:51.642699 progress 100 % (52 MB)
75 01:55:51.642932 52 MB downloaded in 0.28 s (185.77 MB/s)
76 01:55:51.643082 end: 1.2.1 http-download (duration 00:00:00) [common]
78 01:55:51.643316 end: 1.2 download-retry (duration 00:00:00) [common]
79 01:55:51.643404 start: 1.3 download-retry (timeout 00:10:00) [common]
80 01:55:51.643492 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 01:55:51.643628 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.94-cip23/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dtb
82 01:55:51.643698 saving as /var/lib/lava/dispatcher/tmp/14479169/tftp-deploy-fdqb7x23/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb
83 01:55:51.643760 total size: 57695 (0 MB)
84 01:55:51.643822 No compression specified
85 01:55:51.644936 progress 56 % (0 MB)
86 01:55:51.645212 progress 100 % (0 MB)
87 01:55:51.645465 0 MB downloaded in 0.00 s (32.32 MB/s)
88 01:55:51.645588 end: 1.3.1 http-download (duration 00:00:00) [common]
90 01:55:51.645811 end: 1.3 download-retry (duration 00:00:00) [common]
91 01:55:51.645897 start: 1.4 download-retry (timeout 00:10:00) [common]
92 01:55:51.645982 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 01:55:51.646093 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 01:55:51.646160 saving as /var/lib/lava/dispatcher/tmp/14479169/tftp-deploy-fdqb7x23/nfsrootfs/full.rootfs.tar
95 01:55:51.646221 total size: 120894716 (115 MB)
96 01:55:51.646283 Using unxz to decompress xz
97 01:55:51.650423 progress 0 % (0 MB)
98 01:55:51.994893 progress 5 % (5 MB)
99 01:55:52.359698 progress 10 % (11 MB)
100 01:55:52.718218 progress 15 % (17 MB)
101 01:55:53.043188 progress 20 % (23 MB)
102 01:55:53.336256 progress 25 % (28 MB)
103 01:55:53.704057 progress 30 % (34 MB)
104 01:55:54.048942 progress 35 % (40 MB)
105 01:55:54.211492 progress 40 % (46 MB)
106 01:55:54.394055 progress 45 % (51 MB)
107 01:55:54.713350 progress 50 % (57 MB)
108 01:55:55.098144 progress 55 % (63 MB)
109 01:55:55.456032 progress 60 % (69 MB)
110 01:55:55.805799 progress 65 % (74 MB)
111 01:55:56.160196 progress 70 % (80 MB)
112 01:55:56.532587 progress 75 % (86 MB)
113 01:55:56.883583 progress 80 % (92 MB)
114 01:55:57.232928 progress 85 % (98 MB)
115 01:55:57.599858 progress 90 % (103 MB)
116 01:55:57.933451 progress 95 % (109 MB)
117 01:55:58.298347 progress 100 % (115 MB)
118 01:55:58.303670 115 MB downloaded in 6.66 s (17.32 MB/s)
119 01:55:58.303967 end: 1.4.1 http-download (duration 00:00:07) [common]
121 01:55:58.304364 end: 1.4 download-retry (duration 00:00:07) [common]
122 01:55:58.304486 start: 1.5 download-retry (timeout 00:09:53) [common]
123 01:55:58.304605 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 01:55:58.304785 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.94-cip23/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 01:55:58.304880 saving as /var/lib/lava/dispatcher/tmp/14479169/tftp-deploy-fdqb7x23/modules/modules.tar
126 01:55:58.304969 total size: 8618924 (8 MB)
127 01:55:58.305062 Using unxz to decompress xz
128 01:55:58.309504 progress 0 % (0 MB)
129 01:55:58.329234 progress 5 % (0 MB)
130 01:55:58.353676 progress 10 % (0 MB)
131 01:55:58.378801 progress 15 % (1 MB)
132 01:55:58.403427 progress 20 % (1 MB)
133 01:55:58.428733 progress 25 % (2 MB)
134 01:55:58.453564 progress 30 % (2 MB)
135 01:55:58.479309 progress 35 % (2 MB)
136 01:55:58.504750 progress 40 % (3 MB)
137 01:55:58.530599 progress 45 % (3 MB)
138 01:55:58.555706 progress 50 % (4 MB)
139 01:55:58.581768 progress 55 % (4 MB)
140 01:55:58.606909 progress 60 % (4 MB)
141 01:55:58.631733 progress 65 % (5 MB)
142 01:55:58.661587 progress 70 % (5 MB)
143 01:55:58.688046 progress 75 % (6 MB)
144 01:55:58.712235 progress 80 % (6 MB)
145 01:55:58.737008 progress 85 % (7 MB)
146 01:55:58.762202 progress 90 % (7 MB)
147 01:55:58.791550 progress 95 % (7 MB)
148 01:55:58.822515 progress 100 % (8 MB)
149 01:55:58.827349 8 MB downloaded in 0.52 s (15.74 MB/s)
150 01:55:58.827613 end: 1.5.1 http-download (duration 00:00:01) [common]
152 01:55:58.827879 end: 1.5 download-retry (duration 00:00:01) [common]
153 01:55:58.827974 start: 1.6 prepare-tftp-overlay (timeout 00:09:53) [common]
154 01:55:58.828068 start: 1.6.1 extract-nfsrootfs (timeout 00:09:53) [common]
155 01:56:02.273886 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14479169/extract-nfsrootfs-rq4f2012
156 01:56:02.274091 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 01:56:02.274194 start: 1.6.2 lava-overlay (timeout 00:09:49) [common]
158 01:56:02.274362 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14479169/lava-overlay-yqd09_uv
159 01:56:02.274489 makedir: /var/lib/lava/dispatcher/tmp/14479169/lava-overlay-yqd09_uv/lava-14479169/bin
160 01:56:02.274588 makedir: /var/lib/lava/dispatcher/tmp/14479169/lava-overlay-yqd09_uv/lava-14479169/tests
161 01:56:02.274685 makedir: /var/lib/lava/dispatcher/tmp/14479169/lava-overlay-yqd09_uv/lava-14479169/results
162 01:56:02.274783 Creating /var/lib/lava/dispatcher/tmp/14479169/lava-overlay-yqd09_uv/lava-14479169/bin/lava-add-keys
163 01:56:02.274922 Creating /var/lib/lava/dispatcher/tmp/14479169/lava-overlay-yqd09_uv/lava-14479169/bin/lava-add-sources
164 01:56:02.275048 Creating /var/lib/lava/dispatcher/tmp/14479169/lava-overlay-yqd09_uv/lava-14479169/bin/lava-background-process-start
165 01:56:02.275173 Creating /var/lib/lava/dispatcher/tmp/14479169/lava-overlay-yqd09_uv/lava-14479169/bin/lava-background-process-stop
166 01:56:02.275298 Creating /var/lib/lava/dispatcher/tmp/14479169/lava-overlay-yqd09_uv/lava-14479169/bin/lava-common-functions
167 01:56:02.275429 Creating /var/lib/lava/dispatcher/tmp/14479169/lava-overlay-yqd09_uv/lava-14479169/bin/lava-echo-ipv4
168 01:56:02.275557 Creating /var/lib/lava/dispatcher/tmp/14479169/lava-overlay-yqd09_uv/lava-14479169/bin/lava-install-packages
169 01:56:02.275682 Creating /var/lib/lava/dispatcher/tmp/14479169/lava-overlay-yqd09_uv/lava-14479169/bin/lava-installed-packages
170 01:56:02.275806 Creating /var/lib/lava/dispatcher/tmp/14479169/lava-overlay-yqd09_uv/lava-14479169/bin/lava-os-build
171 01:56:02.275929 Creating /var/lib/lava/dispatcher/tmp/14479169/lava-overlay-yqd09_uv/lava-14479169/bin/lava-probe-channel
172 01:56:02.276053 Creating /var/lib/lava/dispatcher/tmp/14479169/lava-overlay-yqd09_uv/lava-14479169/bin/lava-probe-ip
173 01:56:02.276176 Creating /var/lib/lava/dispatcher/tmp/14479169/lava-overlay-yqd09_uv/lava-14479169/bin/lava-target-ip
174 01:56:02.276297 Creating /var/lib/lava/dispatcher/tmp/14479169/lava-overlay-yqd09_uv/lava-14479169/bin/lava-target-mac
175 01:56:02.276419 Creating /var/lib/lava/dispatcher/tmp/14479169/lava-overlay-yqd09_uv/lava-14479169/bin/lava-target-storage
176 01:56:02.276543 Creating /var/lib/lava/dispatcher/tmp/14479169/lava-overlay-yqd09_uv/lava-14479169/bin/lava-test-case
177 01:56:02.276668 Creating /var/lib/lava/dispatcher/tmp/14479169/lava-overlay-yqd09_uv/lava-14479169/bin/lava-test-event
178 01:56:02.276790 Creating /var/lib/lava/dispatcher/tmp/14479169/lava-overlay-yqd09_uv/lava-14479169/bin/lava-test-feedback
179 01:56:02.276913 Creating /var/lib/lava/dispatcher/tmp/14479169/lava-overlay-yqd09_uv/lava-14479169/bin/lava-test-raise
180 01:56:02.277034 Creating /var/lib/lava/dispatcher/tmp/14479169/lava-overlay-yqd09_uv/lava-14479169/bin/lava-test-reference
181 01:56:02.277156 Creating /var/lib/lava/dispatcher/tmp/14479169/lava-overlay-yqd09_uv/lava-14479169/bin/lava-test-runner
182 01:56:02.277314 Creating /var/lib/lava/dispatcher/tmp/14479169/lava-overlay-yqd09_uv/lava-14479169/bin/lava-test-set
183 01:56:02.277453 Creating /var/lib/lava/dispatcher/tmp/14479169/lava-overlay-yqd09_uv/lava-14479169/bin/lava-test-shell
184 01:56:02.277580 Updating /var/lib/lava/dispatcher/tmp/14479169/lava-overlay-yqd09_uv/lava-14479169/bin/lava-add-keys (debian)
185 01:56:02.277730 Updating /var/lib/lava/dispatcher/tmp/14479169/lava-overlay-yqd09_uv/lava-14479169/bin/lava-add-sources (debian)
186 01:56:02.277867 Updating /var/lib/lava/dispatcher/tmp/14479169/lava-overlay-yqd09_uv/lava-14479169/bin/lava-install-packages (debian)
187 01:56:02.278001 Updating /var/lib/lava/dispatcher/tmp/14479169/lava-overlay-yqd09_uv/lava-14479169/bin/lava-installed-packages (debian)
188 01:56:02.278135 Updating /var/lib/lava/dispatcher/tmp/14479169/lava-overlay-yqd09_uv/lava-14479169/bin/lava-os-build (debian)
189 01:56:02.278252 Creating /var/lib/lava/dispatcher/tmp/14479169/lava-overlay-yqd09_uv/lava-14479169/environment
190 01:56:02.278349 LAVA metadata
191 01:56:02.278414 - LAVA_JOB_ID=14479169
192 01:56:02.278476 - LAVA_DISPATCHER_IP=192.168.201.1
193 01:56:02.278574 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:49) [common]
194 01:56:02.278640 skipped lava-vland-overlay
195 01:56:02.278713 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 01:56:02.278792 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:49) [common]
197 01:56:02.278852 skipped lava-multinode-overlay
198 01:56:02.278923 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 01:56:02.279000 start: 1.6.2.3 test-definition (timeout 00:09:49) [common]
200 01:56:02.279085 Loading test definitions
201 01:56:02.279175 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:49) [common]
202 01:56:02.279246 Using /lava-14479169 at stage 0
203 01:56:02.279518 uuid=14479169_1.6.2.3.1 testdef=None
204 01:56:02.279605 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 01:56:02.279689 start: 1.6.2.3.2 test-overlay (timeout 00:09:49) [common]
206 01:56:02.280139 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 01:56:02.280360 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:49) [common]
209 01:56:02.280909 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 01:56:02.281138 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:49) [common]
212 01:56:02.281925 runner path: /var/lib/lava/dispatcher/tmp/14479169/lava-overlay-yqd09_uv/lava-14479169/0/tests/0_timesync-off test_uuid 14479169_1.6.2.3.1
213 01:56:02.282081 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 01:56:02.282305 start: 1.6.2.3.5 git-repo-action (timeout 00:09:49) [common]
216 01:56:02.282378 Using /lava-14479169 at stage 0
217 01:56:02.282476 Fetching tests from https://github.com/kernelci/test-definitions.git
218 01:56:02.282562 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14479169/lava-overlay-yqd09_uv/lava-14479169/0/tests/1_kselftest-alsa'
219 01:56:05.136059 Running '/usr/bin/git checkout kernelci.org
220 01:56:05.240298 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14479169/lava-overlay-yqd09_uv/lava-14479169/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
221 01:56:05.241037 uuid=14479169_1.6.2.3.5 testdef=None
222 01:56:05.241196 end: 1.6.2.3.5 git-repo-action (duration 00:00:03) [common]
224 01:56:05.241523 start: 1.6.2.3.6 test-overlay (timeout 00:09:46) [common]
225 01:56:05.242273 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 01:56:05.242509 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:46) [common]
228 01:56:05.243487 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 01:56:05.243728 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:46) [common]
231 01:56:05.244649 runner path: /var/lib/lava/dispatcher/tmp/14479169/lava-overlay-yqd09_uv/lava-14479169/0/tests/1_kselftest-alsa test_uuid 14479169_1.6.2.3.5
232 01:56:05.244761 BOARD='mt8183-kukui-jacuzzi-juniper-sku16'
233 01:56:05.244840 BRANCH='cip'
234 01:56:05.244900 SKIPFILE='/dev/null'
235 01:56:05.244958 SKIP_INSTALL='True'
236 01:56:05.245014 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.94-cip23/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 01:56:05.245073 TST_CASENAME=''
238 01:56:05.245129 TST_CMDFILES='alsa'
239 01:56:05.245361 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 01:56:05.245584 Creating lava-test-runner.conf files
242 01:56:05.245648 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14479169/lava-overlay-yqd09_uv/lava-14479169/0 for stage 0
243 01:56:05.245742 - 0_timesync-off
244 01:56:05.245819 - 1_kselftest-alsa
245 01:56:05.245933 end: 1.6.2.3 test-definition (duration 00:00:03) [common]
246 01:56:05.246023 start: 1.6.2.4 compress-overlay (timeout 00:09:46) [common]
247 01:56:12.783200 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 01:56:12.783358 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:39) [common]
249 01:56:12.783452 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 01:56:12.783549 end: 1.6.2 lava-overlay (duration 00:00:11) [common]
251 01:56:12.783640 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:39) [common]
252 01:56:12.947376 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 01:56:12.947767 start: 1.6.4 extract-modules (timeout 00:09:38) [common]
254 01:56:12.947882 extracting modules file /var/lib/lava/dispatcher/tmp/14479169/tftp-deploy-fdqb7x23/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14479169/extract-nfsrootfs-rq4f2012
255 01:56:13.162725 extracting modules file /var/lib/lava/dispatcher/tmp/14479169/tftp-deploy-fdqb7x23/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14479169/extract-overlay-ramdisk-rnqyv31h/ramdisk
256 01:56:13.381792 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 01:56:13.381966 start: 1.6.5 apply-overlay-tftp (timeout 00:09:38) [common]
258 01:56:13.382066 [common] Applying overlay to NFS
259 01:56:13.382136 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14479169/compress-overlay-0zkp6xov/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14479169/extract-nfsrootfs-rq4f2012
260 01:56:14.296051 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 01:56:14.296225 start: 1.6.6 configure-preseed-file (timeout 00:09:37) [common]
262 01:56:14.296321 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 01:56:14.296411 start: 1.6.7 compress-ramdisk (timeout 00:09:37) [common]
264 01:56:14.296495 Building ramdisk /var/lib/lava/dispatcher/tmp/14479169/extract-overlay-ramdisk-rnqyv31h/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14479169/extract-overlay-ramdisk-rnqyv31h/ramdisk
265 01:56:14.638628 >> 130487 blocks
266 01:56:16.675283 rename /var/lib/lava/dispatcher/tmp/14479169/extract-overlay-ramdisk-rnqyv31h/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14479169/tftp-deploy-fdqb7x23/ramdisk/ramdisk.cpio.gz
267 01:56:16.675750 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 01:56:16.675895 start: 1.6.8 prepare-kernel (timeout 00:09:35) [common]
269 01:56:16.675995 start: 1.6.8.1 prepare-fit (timeout 00:09:35) [common]
270 01:56:16.676098 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14479169/tftp-deploy-fdqb7x23/kernel/Image']
271 01:56:29.635851 Returned 0 in 12 seconds
272 01:56:29.736832 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14479169/tftp-deploy-fdqb7x23/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14479169/tftp-deploy-fdqb7x23/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb -i /var/lib/lava/dispatcher/tmp/14479169/tftp-deploy-fdqb7x23/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14479169/tftp-deploy-fdqb7x23/kernel/image.itb
273 01:56:30.118344 output: FIT description: Kernel Image image with one or more FDT blobs
274 01:56:30.118813 output: Created: Fri Jun 21 02:56:30 2024
275 01:56:30.118943 output: Image 0 (kernel-1)
276 01:56:30.119012 output: Description:
277 01:56:30.119102 output: Created: Fri Jun 21 02:56:30 2024
278 01:56:30.119178 output: Type: Kernel Image
279 01:56:30.119240 output: Compression: lzma compressed
280 01:56:30.119300 output: Data Size: 13124896 Bytes = 12817.28 KiB = 12.52 MiB
281 01:56:30.119359 output: Architecture: AArch64
282 01:56:30.119415 output: OS: Linux
283 01:56:30.119472 output: Load Address: 0x00000000
284 01:56:30.119528 output: Entry Point: 0x00000000
285 01:56:30.119583 output: Hash algo: crc32
286 01:56:30.119636 output: Hash value: ab2f7826
287 01:56:30.119691 output: Image 1 (fdt-1)
288 01:56:30.119746 output: Description: mt8183-kukui-jacuzzi-juniper-sku16
289 01:56:30.119800 output: Created: Fri Jun 21 02:56:30 2024
290 01:56:30.119855 output: Type: Flat Device Tree
291 01:56:30.119907 output: Compression: uncompressed
292 01:56:30.119959 output: Data Size: 57695 Bytes = 56.34 KiB = 0.06 MiB
293 01:56:30.120012 output: Architecture: AArch64
294 01:56:30.120064 output: Hash algo: crc32
295 01:56:30.120116 output: Hash value: a9713552
296 01:56:30.120168 output: Image 2 (ramdisk-1)
297 01:56:30.120220 output: Description: unavailable
298 01:56:30.120273 output: Created: Fri Jun 21 02:56:30 2024
299 01:56:30.120325 output: Type: RAMDisk Image
300 01:56:30.120376 output: Compression: Unknown Compression
301 01:56:30.120429 output: Data Size: 18738626 Bytes = 18299.44 KiB = 17.87 MiB
302 01:56:30.120481 output: Architecture: AArch64
303 01:56:30.120534 output: OS: Linux
304 01:56:30.120586 output: Load Address: unavailable
305 01:56:30.120638 output: Entry Point: unavailable
306 01:56:30.120690 output: Hash algo: crc32
307 01:56:30.120742 output: Hash value: a80bef84
308 01:56:30.120794 output: Default Configuration: 'conf-1'
309 01:56:30.120849 output: Configuration 0 (conf-1)
310 01:56:30.120901 output: Description: mt8183-kukui-jacuzzi-juniper-sku16
311 01:56:30.120953 output: Kernel: kernel-1
312 01:56:30.121020 output: Init Ramdisk: ramdisk-1
313 01:56:30.121087 output: FDT: fdt-1
314 01:56:30.121138 output: Loadables: kernel-1
315 01:56:30.121191 output:
316 01:56:30.121429 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
317 01:56:30.121549 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
318 01:56:30.121657 end: 1.6 prepare-tftp-overlay (duration 00:00:31) [common]
319 01:56:30.121745 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:21) [common]
320 01:56:30.121822 No LXC device requested
321 01:56:30.121897 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 01:56:30.121986 start: 1.8 deploy-device-env (timeout 00:09:21) [common]
323 01:56:30.122062 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 01:56:30.122127 Checking files for TFTP limit of 4294967296 bytes.
325 01:56:30.122614 end: 1 tftp-deploy (duration 00:00:39) [common]
326 01:56:30.122721 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 01:56:30.122810 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 01:56:30.122930 substitutions:
329 01:56:30.123014 - {DTB}: 14479169/tftp-deploy-fdqb7x23/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb
330 01:56:30.123092 - {INITRD}: 14479169/tftp-deploy-fdqb7x23/ramdisk/ramdisk.cpio.gz
331 01:56:30.123151 - {KERNEL}: 14479169/tftp-deploy-fdqb7x23/kernel/Image
332 01:56:30.123208 - {LAVA_MAC}: None
333 01:56:30.123263 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14479169/extract-nfsrootfs-rq4f2012
334 01:56:30.123318 - {NFS_SERVER_IP}: 192.168.201.1
335 01:56:30.123372 - {PRESEED_CONFIG}: None
336 01:56:30.123425 - {PRESEED_LOCAL}: None
337 01:56:30.123508 - {RAMDISK}: 14479169/tftp-deploy-fdqb7x23/ramdisk/ramdisk.cpio.gz
338 01:56:30.123595 - {ROOT_PART}: None
339 01:56:30.123648 - {ROOT}: None
340 01:56:30.123701 - {SERVER_IP}: 192.168.201.1
341 01:56:30.123790 - {TEE}: None
342 01:56:30.123843 Parsed boot commands:
343 01:56:30.123895 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 01:56:30.124074 Parsed boot commands: tftpboot 192.168.201.1 14479169/tftp-deploy-fdqb7x23/kernel/image.itb 14479169/tftp-deploy-fdqb7x23/kernel/cmdline
345 01:56:30.124163 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 01:56:30.124249 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 01:56:30.124341 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 01:56:30.124426 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 01:56:30.124497 Not connected, no need to disconnect.
350 01:56:30.124570 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 01:56:30.124650 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 01:56:30.124720 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8183-kukui-jacuzzi-juniper-sku16-cbg-3'
353 01:56:30.128595 Setting prompt string to ['lava-test: # ']
354 01:56:30.129023 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 01:56:30.129183 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 01:56:30.129377 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 01:56:30.129467 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 01:56:30.129691 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8183-kukui-jacuzzi-juniper-sku16-cbg-3']
359 01:56:54.704057 Returned 0 in 24 seconds
360 01:56:54.805176 end: 2.2.2.1 pdu-reboot (duration 00:00:25) [common]
362 01:56:54.806633 end: 2.2.2 reset-device (duration 00:00:25) [common]
363 01:56:54.807139 start: 2.2.3 depthcharge-start (timeout 00:04:35) [common]
364 01:56:54.807596 Setting prompt string to 'Starting depthcharge on Juniper...'
365 01:56:54.807954 Changing prompt to 'Starting depthcharge on Juniper...'
366 01:56:54.808308 depthcharge-start: Wait for prompt Starting depthcharge on Juniper... (timeout 00:05:00)
367 01:56:54.810327 [Enter `^Ec?' for help]
368 01:56:54.811078 [DL] 00000000 00000000 010701
369 01:56:54.811754
370 01:56:54.812276
371 01:56:54.812849 F0: 102B 0000
372 01:56:54.813212
373 01:56:54.813730 F3: 1006 0033 [0200]
374 01:56:54.814199
375 01:56:54.814667 F3: 4001 00E0 [0200]
376 01:56:54.815110
377 01:56:54.815544 F3: 0000 0000
378 01:56:54.815978
379 01:56:54.816410 V0: 0000 0000 [0001]
380 01:56:54.816830
381 01:56:54.817131 00: 1027 0002
382 01:56:54.817482
383 01:56:54.817769 01: 0000 0000
384 01:56:54.818061
385 01:56:54.818341 BP: 0C00 0251 [0000]
386 01:56:54.818624
387 01:56:54.818900 G0: 1182 0000
388 01:56:54.819176
389 01:56:54.819454 EC: 0004 0000 [0001]
390 01:56:54.819734
391 01:56:54.820013 S7: 0000 0000 [0000]
392 01:56:54.820319
393 01:56:54.820602 CC: 0000 0000 [0001]
394 01:56:54.820941
395 01:56:54.821238 T0: 0000 00DB [000F]
396 01:56:54.821561
397 01:56:54.821840 Jump to BL
398 01:56:54.822119
399 01:56:54.822395
400 01:56:54.822671
401 01:56:54.822953 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 verstage starting (log level: 8)...
402 01:56:54.823250 ARM64: Exception handlers installed.
403 01:56:54.823532 ARM64: Testing exception
404 01:56:54.823840 ARM64: Done test exception
405 01:56:54.824124 WDT: Last reset was cold boot
406 01:56:54.824405 SPI0(PAD0) initialized at 992727 Hz
407 01:56:54.824685 FMAP: area RW_NVRAM found @ 554000 (8192 bytes)
408 01:56:54.824967 Manufacturer: ef
409 01:56:54.825244 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
410 01:56:54.825570 Probing TPM: . done!
411 01:56:54.825944 TPM ready after 0 ms
412 01:56:54.826235 Connected to device vid:did:rid of 1ae0:0028:00
413 01:56:54.826517 Firmware version: B2-C:0 RO_A:0.0.12/bf248b9d RW_B:0.5.171/cr50_v2.94_mp.164-2fb1dd676c
414 01:56:54.826823 Initialized TPM device CR50 revision 0
415 01:56:54.827188 tlcl_send_startup: Startup return code is 0
416 01:56:54.827481 TPM: setup succeeded
417 01:56:54.827765 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x1007 return code 0
418 01:56:54.828048 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
419 01:56:54.828328 in-header: 03 19 00 00 08 00 00 00
420 01:56:54.828607 in-data: a2 e0 47 00 13 00 00 00
421 01:56:54.828888 Chrome EC: UHEPI supported
422 01:56:54.829166 out: cmd=0xa4: 03 5d a4 00 00 00 0c 00 00 01 00 00 f4 fb 00 00 00 00 00 00
423 01:56:54.829500 in-header: 03 a1 00 00 08 00 00 00
424 01:56:54.829797 in-data: 84 60 60 10 00 00 00 00
425 01:56:54.830076 Phase 1
426 01:56:54.830353 FMAP: area GBB found @ 3f5000 (12032 bytes)
427 01:56:54.830669 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x0 / 0x0
428 01:56:54.830954 VB2:vb2_check_recovery() Recovery was requested manually
429 01:56:54.831235 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x0
430 01:56:54.831517 Recovery requested (1009000e)
431 01:56:54.831837 tlcl_extend: response is 0
432 01:56:54.832118 tlcl_extend: response is 0
433 01:56:54.832398
434 01:56:54.832676
435 01:56:54.832921 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 romstage starting (log level: 8)...
436 01:56:54.833127 ARM64: Exception handlers installed.
437 01:56:54.833373 ARM64: Testing exception
438 01:56:54.833580 ARM64: Done test exception
439 01:56:54.833779 [RTC]rtc_enable_dcxo,41: con=0x482, osc32con=0xea6b, sec=0x2000
440 01:56:54.833982 [RTC]rtc_check_state,142: con=482, pwrkey1=a357, pwrkey2=67d2
441 01:56:54.834211 [RTC]rtc_eosc_cali,157: PMIC_RG_FQMTR_CKSEL=0x4a
442 01:56:54.834414 [RTC]rtc_get_frequency_meter,134: input=0xf, output=863
443 01:56:54.834616 [RTC]rtc_get_frequency_meter,134: input=0x7, output=733
444 01:56:54.834817 [RTC]rtc_get_frequency_meter,134: input=0xb, output=796
445 01:56:54.835016 [RTC]rtc_osc_init,208: EOSC32 cali val = 0xea6b
446 01:56:54.835218 [RTC]rtc_boot_common,186: irqsta=0, bbpu=0, con=482
447 01:56:54.835420 [RTC]rtc_bbpu_power_on,373: rtc_write_trigger=1
448 01:56:54.835621 [RTC]rtc_bbpu_power_on,376: done BBPU=0x9
449 01:56:54.835843 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
450 01:56:54.836158 in-header: 03 19 00 00 08 00 00 00
451 01:56:54.836371 in-data: a2 e0 47 00 13 00 00 00
452 01:56:54.836573 Chrome EC: UHEPI supported
453 01:56:54.836776 out: cmd=0xa4: 03 5d a4 00 00 00 0c 00 00 01 00 00 f4 fb 00 00 00 00 00 00
454 01:56:54.837005 in-header: 03 a1 00 00 08 00 00 00
455 01:56:54.837208 in-data: 84 60 60 10 00 00 00 00
456 01:56:54.837447 Skip loading cached calibration data
457 01:56:54.837674 out: cmd=0xa4: 03 7f a4 00 00 00 0c 00 00 01 00 00 d0 ff ff ff 00 00 00 00
458 01:56:54.837871 in-header: 03 a1 00 00 08 00 00 00
459 01:56:54.838021 in-data: 84 60 60 10 00 00 00 00
460 01:56:54.838172 out: cmd=0xa4: 03 79 a4 00 00 00 0c 00 00 01 00 00 f0 7e 11 00 84 60 60 10
461 01:56:54.838324 in-header: 03 a1 00 00 08 00 00 00
462 01:56:54.838473 in-data: 84 60 60 10 00 00 00 00
463 01:56:54.838623 ADC[3]: Raw value=1037832 ID=8
464 01:56:54.838795 Manufacturer: ef
465 01:56:54.838961 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
466 01:56:54.839115 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
467 01:56:54.839266 CBFS @ 21000 size 3d4000
468 01:56:54.839459 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
469 01:56:54.839615 CBFS: Locating 'sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB'
470 01:56:54.839767 CBFS: Found @ offset 3c880 size 4b
471 01:56:54.839920 DRAM-K: Full Calibration
472 01:56:54.840070 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
473 01:56:54.840221 CBFS @ 21000 size 3d4000
474 01:56:54.840388 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
475 01:56:54.840542 CBFS: Locating 'fallback/dram'
476 01:56:54.840694 CBFS: Found @ offset 24b00 size 12268
477 01:56:54.840865 read SPI 0x45b44 0x1224c: 22775 us, 3263 KB/s, 26.104 Mbps
478 01:56:54.841017 ddr_geometry: 1, config: 0x0
479 01:56:54.841168 header.status = 0x0
480 01:56:54.841336 header.magic = 0x44524d4b (expected: 0x44524d4b)
481 01:56:54.841490 header.version = 0x5 (expected: 0x5)
482 01:56:54.841641 header.size = 0x8f0 (expected: 0x8f0)
483 01:56:54.841791 header.config = 0x0
484 01:56:54.841940 header.flags = 0x0
485 01:56:54.842087 header.checksum = 0x0
486 01:56:54.842239 dram_init: MediaTek DRAM firmware version: 1.5.0, accepting param version 5
487 01:56:54.842390 Set DRAM voltage: vdram1 = 1125000, vddq = 600000
488 01:56:54.842806 Get DRAM voltage to vdram1 = 1125000, vddq = 600000
489 01:56:54.843068 ddr_geometry:1
490 01:56:54.843325 [EMI] new MDL number = 1
491 01:56:54.843585 dram_cbt_mode_extern: 0
492 01:56:54.843794 dram_cbt_mode [RK0]: 0, [RK1]: 0
493 01:56:54.844000 Rank info: 0 emi_setting_index: 1 CONA[0xf053f154]
494 01:56:54.844195
495 01:56:54.844381
496 01:56:54.844568 [Bianco] ETT version 0.0.0.1
497 01:56:54.844756 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
498 01:56:54.844940
499 01:56:54.845269 vSetVcoreByFreq with vcore:762500, freq=1600
500 01:56:54.845474
501 01:56:54.845662 [DramcInit]
502 01:56:54.845896 AutoRefreshCKEOff AutoREF OFF
503 01:56:54.846086 DDRPhyPLLSetting-CKEOFF
504 01:56:54.846273 DDRPhyPLLSetting-CKEON
505 01:56:54.846464
506 01:56:54.846598 Enable WDQS
507 01:56:54.846722 [ModeRegInit_LP4] CH0 RK0
508 01:56:54.846868 Write Rank0 MR13 =0x18
509 01:56:54.847087 Write Rank0 MR12 =0x5d
510 01:56:54.847221 Write Rank0 MR1 =0x56
511 01:56:54.847347 Write Rank0 MR2 =0x1a
512 01:56:54.847490 Write Rank0 MR11 =0x0
513 01:56:54.847615 Write Rank0 MR22 =0x38
514 01:56:54.847736 Write Rank0 MR14 =0x5d
515 01:56:54.847879 Write Rank0 MR3 =0x30
516 01:56:54.848143 Write Rank0 MR13 =0x58
517 01:56:54.848332 Write Rank0 MR12 =0x5d
518 01:56:54.848444 Write Rank0 MR1 =0x56
519 01:56:54.848565 Write Rank0 MR2 =0x2d
520 01:56:54.848669 Write Rank0 MR11 =0x23
521 01:56:54.848773 Write Rank0 MR22 =0x34
522 01:56:54.848875 Write Rank0 MR14 =0x10
523 01:56:54.848976 Write Rank0 MR3 =0x30
524 01:56:54.849077 Write Rank0 MR13 =0xd8
525 01:56:54.849178 [ModeRegInit_LP4] CH0 RK1
526 01:56:54.849288 Write Rank1 MR13 =0x18
527 01:56:54.849392 Write Rank1 MR12 =0x5d
528 01:56:54.849510 Write Rank1 MR1 =0x56
529 01:56:54.849612 Write Rank1 MR2 =0x1a
530 01:56:54.849713 Write Rank1 MR11 =0x0
531 01:56:54.849815 Write Rank1 MR22 =0x38
532 01:56:54.849915 Write Rank1 MR14 =0x5d
533 01:56:54.850015 Write Rank1 MR3 =0x30
534 01:56:54.850114 Write Rank1 MR13 =0x58
535 01:56:54.850214 Write Rank1 MR12 =0x5d
536 01:56:54.850314 Write Rank1 MR1 =0x56
537 01:56:54.850431 Write Rank1 MR2 =0x2d
538 01:56:54.850533 Write Rank1 MR11 =0x23
539 01:56:54.850632 Write Rank1 MR22 =0x34
540 01:56:54.850733 Write Rank1 MR14 =0x10
541 01:56:54.850833 Write Rank1 MR3 =0x30
542 01:56:54.850933 Write Rank1 MR13 =0xd8
543 01:56:54.851034 [ModeRegInit_LP4] CH1 RK0
544 01:56:54.851135 Write Rank0 MR13 =0x18
545 01:56:54.851235 Write Rank0 MR12 =0x5d
546 01:56:54.851357 Write Rank0 MR1 =0x56
547 01:56:54.851459 Write Rank0 MR2 =0x1a
548 01:56:54.851560 Write Rank0 MR11 =0x0
549 01:56:54.851659 Write Rank0 MR22 =0x38
550 01:56:54.851758 Write Rank0 MR14 =0x5d
551 01:56:54.851860 Write Rank0 MR3 =0x30
552 01:56:54.851960 Write Rank0 MR13 =0x58
553 01:56:54.852060 Write Rank0 MR12 =0x5d
554 01:56:54.852315 Write Rank0 MR1 =0x56
555 01:56:54.852514 Write Rank0 MR2 =0x2d
556 01:56:54.852635 Write Rank0 MR11 =0x23
557 01:56:54.852752 Write Rank0 MR22 =0x34
558 01:56:54.852839 Write Rank0 MR14 =0x10
559 01:56:54.852925 Write Rank0 MR3 =0x30
560 01:56:54.853012 Write Rank0 MR13 =0xd8
561 01:56:54.853099 [ModeRegInit_LP4] CH1 RK1
562 01:56:54.853186 Write Rank1 MR13 =0x18
563 01:56:54.853324 Write Rank1 MR12 =0x5d
564 01:56:54.853422 Write Rank1 MR1 =0x56
565 01:56:54.853509 Write Rank1 MR2 =0x1a
566 01:56:54.853596 Write Rank1 MR11 =0x0
567 01:56:54.853680 Write Rank1 MR22 =0x38
568 01:56:54.853766 Write Rank1 MR14 =0x5d
569 01:56:54.853851 Write Rank1 MR3 =0x30
570 01:56:54.853937 Write Rank1 MR13 =0x58
571 01:56:54.854022 Write Rank1 MR12 =0x5d
572 01:56:54.854107 Write Rank1 MR1 =0x56
573 01:56:54.854192 Write Rank1 MR2 =0x2d
574 01:56:54.854278 Write Rank1 MR11 =0x23
575 01:56:54.854363 Write Rank1 MR22 =0x34
576 01:56:54.854449 Write Rank1 MR14 =0x10
577 01:56:54.854536 Write Rank1 MR3 =0x30
578 01:56:54.854622 Write Rank1 MR13 =0xd8
579 01:56:54.854707 match AC timing 3
580 01:56:54.854794 [DdrUpdateACTimingReg] Freq = 1600, tRFCab = 141, tRFCab_05T = 0, TXREFCNT = 159, tRFCpb = 65, tRFCpb_05T = 0
581 01:56:54.854883 [MiockJmeterHQA]
582 01:56:54.854969 vSetVcoreByFreq with vcore:762500, freq=1600
583 01:56:54.855055
584 01:56:54.855141 MIOCK jitter meter ch=0
585 01:56:54.855227
586 01:56:54.855312 1T = (100-18) = 82 dly cells
587 01:56:54.855399 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 762/100 ps
588 01:56:54.855485 vSetVcoreByFreq with vcore:725000, freq=1200
589 01:56:54.855572
590 01:56:54.855657 MIOCK jitter meter ch=0
591 01:56:54.855742
592 01:56:54.855827 1T = (95-17) = 78 dly cells
593 01:56:54.855916 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 801/100 ps
594 01:56:54.856003 vSetVcoreByFreq with vcore:725000, freq=800
595 01:56:54.856089
596 01:56:54.856175 MIOCK jitter meter ch=0
597 01:56:54.856262
598 01:56:54.856346 1T = (95-17) = 78 dly cells
599 01:56:54.856442 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 801/100 ps
600 01:56:54.856542 vSetVcoreByFreq with vcore:762500, freq=1600
601 01:56:54.856657 vSetVcoreByFreq with vcore:762500, freq=1600
602 01:56:54.856747
603 01:56:54.856834 K DRVP
604 01:56:54.856921 1. OCD DRVP=0 CALOUT=0
605 01:56:54.857009 1. OCD DRVP=1 CALOUT=0
606 01:56:54.857150 1. OCD DRVP=2 CALOUT=0
607 01:56:54.857295 1. OCD DRVP=3 CALOUT=0
608 01:56:54.857389 1. OCD DRVP=4 CALOUT=0
609 01:56:54.857478 1. OCD DRVP=5 CALOUT=0
610 01:56:54.857567 1. OCD DRVP=6 CALOUT=0
611 01:56:54.857656 1. OCD DRVP=7 CALOUT=0
612 01:56:54.857744 1. OCD DRVP=8 CALOUT=0
613 01:56:54.857838 1. OCD DRVP=9 CALOUT=1
614 01:56:54.857914
615 01:56:54.857989 1. OCD DRVP calibration OK! DRVP=9
616 01:56:54.858067
617 01:56:54.858142
618 01:56:54.858216
619 01:56:54.858290 K ODTN
620 01:56:54.858365 3. OCD ODTN=0 ,CALOUT=1
621 01:56:54.858447 3. OCD ODTN=1 ,CALOUT=1
622 01:56:54.858524 3. OCD ODTN=2 ,CALOUT=1
623 01:56:54.858599 3. OCD ODTN=3 ,CALOUT=1
624 01:56:54.858676 3. OCD ODTN=4 ,CALOUT=1
625 01:56:54.858752 3. OCD ODTN=5 ,CALOUT=1
626 01:56:54.858828 3. OCD ODTN=6 ,CALOUT=1
627 01:56:54.858905 3. OCD ODTN=7 ,CALOUT=0
628 01:56:54.858980
629 01:56:54.859056 3. OCD ODTN calibration OK! ODTN=7
630 01:56:54.859132
631 01:56:54.859208 [SwImpedanceCal] DRVP=9, DRVN=9, ODTN=7
632 01:56:54.859284 term_option=0, Reg: DRVP=9, DRVN=7, ODTN=15
633 01:56:54.859360 term_option=0, Reg: DRVP=9, DRVN=7, ODTN=15 (After Adjust)
634 01:56:54.859436
635 01:56:54.859510 K DRVP
636 01:56:54.859585 1. OCD DRVP=0 CALOUT=0
637 01:56:54.859666 1. OCD DRVP=1 CALOUT=0
638 01:56:54.859744 1. OCD DRVP=2 CALOUT=0
639 01:56:54.859821 1. OCD DRVP=3 CALOUT=0
640 01:56:54.859902 1. OCD DRVP=4 CALOUT=0
641 01:56:54.859979 1. OCD DRVP=5 CALOUT=0
642 01:56:54.860056 1. OCD DRVP=6 CALOUT=0
643 01:56:54.860133 1. OCD DRVP=7 CALOUT=0
644 01:56:54.860219 1. OCD DRVP=8 CALOUT=0
645 01:56:54.860306 1. OCD DRVP=9 CALOUT=0
646 01:56:54.860389 1. OCD DRVP=10 CALOUT=1
647 01:56:54.860467
648 01:56:54.860542 1. OCD DRVP calibration OK! DRVP=10
649 01:56:54.860618
650 01:56:54.860693
651 01:56:54.860769
652 01:56:54.860843 K ODTN
653 01:56:54.860917 3. OCD ODTN=0 ,CALOUT=1
654 01:56:54.860995 3. OCD ODTN=1 ,CALOUT=1
655 01:56:54.861073 3. OCD ODTN=2 ,CALOUT=1
656 01:56:54.861150 3. OCD ODTN=3 ,CALOUT=1
657 01:56:54.861228 3. OCD ODTN=4 ,CALOUT=1
658 01:56:54.861322 3. OCD ODTN=5 ,CALOUT=1
659 01:56:54.861606 3. OCD ODTN=6 ,CALOUT=1
660 01:56:54.861696 3. OCD ODTN=7 ,CALOUT=1
661 01:56:54.861776 3. OCD ODTN=8 ,CALOUT=1
662 01:56:54.861853 3. OCD ODTN=9 ,CALOUT=1
663 01:56:54.861931 3. OCD ODTN=10 ,CALOUT=1
664 01:56:54.862008 3. OCD ODTN=11 ,CALOUT=1
665 01:56:54.862084 3. OCD ODTN=12 ,CALOUT=1
666 01:56:54.862161 3. OCD ODTN=13 ,CALOUT=1
667 01:56:54.862238 3. OCD ODTN=14 ,CALOUT=0
668 01:56:54.862315
669 01:56:54.862390 3. OCD ODTN calibration OK! ODTN=14
670 01:56:54.862467
671 01:56:54.862543 [SwImpedanceCal] DRVP=10, DRVN=9, ODTN=14
672 01:56:54.862619 term_option=1, Reg: DRVP=10, DRVN=9, ODTN=14
673 01:56:54.862695 term_option=1, Reg: DRVP=10, DRVN=9, ODTN=14 (After Adjust)
674 01:56:54.862807
675 01:56:54.862875 [DramcInit]
676 01:56:54.862942 AutoRefreshCKEOff AutoREF OFF
677 01:56:54.863010 DDRPhyPLLSetting-CKEOFF
678 01:56:54.863076 DDRPhyPLLSetting-CKEON
679 01:56:54.863144
680 01:56:54.863210 Enable WDQS
681 01:56:54.863278 ==
682 01:56:54.863345 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
683 01:56:54.863412 fsp= 1, odt_onoff= 1, Byte mode= 0
684 01:56:54.863482 ==
685 01:56:54.863559 [Duty_Offset_Calibration]
686 01:56:54.863627
687 01:56:54.863694 ===========================
688 01:56:54.863760 B0:0 B1:1 CA:1
689 01:56:54.863827 ==
690 01:56:54.863894 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
691 01:56:54.863962 fsp= 1, odt_onoff= 1, Byte mode= 0
692 01:56:54.864029 ==
693 01:56:54.864096 [Duty_Offset_Calibration]
694 01:56:54.864163
695 01:56:54.864230 ===========================
696 01:56:54.864314 B0:1 B1:1 CA:0
697 01:56:54.864383 [ModeRegInit_LP4] CH0 RK0
698 01:56:54.864450 Write Rank0 MR13 =0x18
699 01:56:54.864517 Write Rank0 MR12 =0x5d
700 01:56:54.864584 Write Rank0 MR1 =0x56
701 01:56:54.864651 Write Rank0 MR2 =0x1a
702 01:56:54.864718 Write Rank0 MR11 =0x0
703 01:56:54.864785 Write Rank0 MR22 =0x38
704 01:56:54.864852 Write Rank0 MR14 =0x5d
705 01:56:54.864918 Write Rank0 MR3 =0x30
706 01:56:54.864985 Write Rank0 MR13 =0x58
707 01:56:54.865051 Write Rank0 MR12 =0x5d
708 01:56:54.865117 Write Rank0 MR1 =0x56
709 01:56:54.865184 Write Rank0 MR2 =0x2d
710 01:56:54.865251 Write Rank0 MR11 =0x23
711 01:56:54.865326 Write Rank0 MR22 =0x34
712 01:56:54.865393 Write Rank0 MR14 =0x10
713 01:56:54.865460 Write Rank0 MR3 =0x30
714 01:56:54.865526 Write Rank0 MR13 =0xd8
715 01:56:54.865593 [ModeRegInit_LP4] CH0 RK1
716 01:56:54.865660 Write Rank1 MR13 =0x18
717 01:56:54.865726 Write Rank1 MR12 =0x5d
718 01:56:54.865793 Write Rank1 MR1 =0x56
719 01:56:54.865859 Write Rank1 MR2 =0x1a
720 01:56:54.865926 Write Rank1 MR11 =0x0
721 01:56:54.865993 Write Rank1 MR22 =0x38
722 01:56:54.866060 Write Rank1 MR14 =0x5d
723 01:56:54.866126 Write Rank1 MR3 =0x30
724 01:56:54.866193 Write Rank1 MR13 =0x58
725 01:56:54.866260 Write Rank1 MR12 =0x5d
726 01:56:54.866327 Write Rank1 MR1 =0x56
727 01:56:54.866394 Write Rank1 MR2 =0x2d
728 01:56:54.866461 Write Rank1 MR11 =0x23
729 01:56:54.866528 Write Rank1 MR22 =0x34
730 01:56:54.866595 Write Rank1 MR14 =0x10
731 01:56:54.866661 Write Rank1 MR3 =0x30
732 01:56:54.866738 Write Rank1 MR13 =0xd8
733 01:56:54.866806 [ModeRegInit_LP4] CH1 RK0
734 01:56:54.866874 Write Rank0 MR13 =0x18
735 01:56:54.866940 Write Rank0 MR12 =0x5d
736 01:56:54.867008 Write Rank0 MR1 =0x56
737 01:56:54.867074 Write Rank0 MR2 =0x1a
738 01:56:54.867140 Write Rank0 MR11 =0x0
739 01:56:54.867206 Write Rank0 MR22 =0x38
740 01:56:54.867273 Write Rank0 MR14 =0x5d
741 01:56:54.867340 Write Rank0 MR3 =0x30
742 01:56:54.867406 Write Rank0 MR13 =0x58
743 01:56:54.867472 Write Rank0 MR12 =0x5d
744 01:56:54.867539 Write Rank0 MR1 =0x56
745 01:56:54.867605 Write Rank0 MR2 =0x2d
746 01:56:54.867672 Write Rank0 MR11 =0x23
747 01:56:54.867738 Write Rank0 MR22 =0x34
748 01:56:54.867815 Write Rank0 MR14 =0x10
749 01:56:54.867875 Write Rank0 MR3 =0x30
750 01:56:54.867934 Write Rank0 MR13 =0xd8
751 01:56:54.867994 [ModeRegInit_LP4] CH1 RK1
752 01:56:54.868053 Write Rank1 MR13 =0x18
753 01:56:54.868113 Write Rank1 MR12 =0x5d
754 01:56:54.868173 Write Rank1 MR1 =0x56
755 01:56:54.868232 Write Rank1 MR2 =0x1a
756 01:56:54.868292 Write Rank1 MR11 =0x0
757 01:56:54.868352 Write Rank1 MR22 =0x38
758 01:56:54.868411 Write Rank1 MR14 =0x5d
759 01:56:54.868470 Write Rank1 MR3 =0x30
760 01:56:54.868530 Write Rank1 MR13 =0x58
761 01:56:54.868589 Write Rank1 MR12 =0x5d
762 01:56:54.868649 Write Rank1 MR1 =0x56
763 01:56:54.868709 Write Rank1 MR2 =0x2d
764 01:56:54.868769 Write Rank1 MR11 =0x23
765 01:56:54.868829 Write Rank1 MR22 =0x34
766 01:56:54.868890 Write Rank1 MR14 =0x10
767 01:56:54.868949 Write Rank1 MR3 =0x30
768 01:56:54.869009 Write Rank1 MR13 =0xd8
769 01:56:54.869068 match AC timing 3
770 01:56:54.869129 [DdrUpdateACTimingReg] Freq = 1600, tRFCab = 141, tRFCab_05T = 0, TXREFCNT = 159, tRFCpb = 65, tRFCpb_05T = 0
771 01:56:54.869190 DramC Write-DBI off
772 01:56:54.869250 DramC Read-DBI off
773 01:56:54.869324 Write Rank0 MR13 =0x59
774 01:56:54.869384 ==
775 01:56:54.869445 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
776 01:56:54.869506 fsp= 1, odt_onoff= 1, Byte mode= 0
777 01:56:54.869566 ==
778 01:56:54.869626 === u2Vref_new: 0x56 --> 0x2d
779 01:56:54.869686 === u2Vref_new: 0x58 --> 0x38
780 01:56:54.869747 === u2Vref_new: 0x5a --> 0x39
781 01:56:54.869808 === u2Vref_new: 0x5c --> 0x3c
782 01:56:54.869868 === u2Vref_new: 0x5e --> 0x3d
783 01:56:54.869929 === u2Vref_new: 0x60 --> 0xa0
784 01:56:54.869989
785 01:56:54.870049 CBT Vref found, early break!
786 01:56:54.870109 [CA 0] Center 33 (4~63) winsize 60
787 01:56:54.870169 [CA 1] Center 34 (5~63) winsize 59
788 01:56:54.870229 [CA 2] Center 29 (1~57) winsize 57
789 01:56:54.870289 [CA 3] Center 24 (-3~51) winsize 55
790 01:56:54.870349 [CA 4] Center 25 (-3~53) winsize 57
791 01:56:54.870409 [CA 5] Center 30 (2~58) winsize 57
792 01:56:54.870469
793 01:56:54.870530 [CATrainingPosCal] consider 1 rank data
794 01:56:54.870590 u2DelayCellTimex100 = 762/100 ps
795 01:56:54.870650 CA0 delay=33 (4~63),Diff = 9 PI (11 cell)
796 01:56:54.870710 CA1 delay=34 (5~63),Diff = 10 PI (12 cell)
797 01:56:54.870770 CA2 delay=29 (1~57),Diff = 5 PI (6 cell)
798 01:56:54.870830 CA3 delay=24 (-3~51),Diff = 0 PI (0 cell)
799 01:56:54.870890 CA4 delay=25 (-3~53),Diff = 1 PI (1 cell)
800 01:56:54.870950 CA5 delay=30 (2~58),Diff = 6 PI (7 cell)
801 01:56:54.871010
802 01:56:54.871070 CA PerBit enable=1, Macro0, CA PI delay=24
803 01:56:54.871130 === u2Vref_new: 0x56 --> 0x2d
804 01:56:54.871191
805 01:56:54.871250 Vref(ca) range 1: 22
806 01:56:54.871311
807 01:56:54.871371 CS Dly= 10 (41-0-32)
808 01:56:54.871431 Write Rank0 MR13 =0xd8
809 01:56:54.871491 Write Rank0 MR13 =0xd8
810 01:56:54.871551 Write Rank0 MR12 =0x56
811 01:56:54.871611 Write Rank1 MR13 =0x59
812 01:56:54.871671 ==
813 01:56:54.871731 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
814 01:56:54.871792 fsp= 1, odt_onoff= 1, Byte mode= 0
815 01:56:54.871852 ==
816 01:56:54.871912 === u2Vref_new: 0x56 --> 0x2d
817 01:56:54.871973 === u2Vref_new: 0x58 --> 0x38
818 01:56:54.872033 === u2Vref_new: 0x5a --> 0x39
819 01:56:54.872316 === u2Vref_new: 0x5c --> 0x3c
820 01:56:54.872414 === u2Vref_new: 0x5e --> 0x3d
821 01:56:54.872482 === u2Vref_new: 0x60 --> 0xa0
822 01:56:54.872545 [CA 0] Center 34 (5~63) winsize 59
823 01:56:54.872606 [CA 1] Center 34 (6~63) winsize 58
824 01:56:54.872677 [CA 2] Center 29 (0~58) winsize 59
825 01:56:54.872749 [CA 3] Center 23 (-4~51) winsize 56
826 01:56:54.872826 [CA 4] Center 24 (-3~52) winsize 56
827 01:56:54.872892 [CA 5] Center 30 (1~59) winsize 59
828 01:56:54.872949
829 01:56:54.873005 [CATrainingPosCal] consider 2 rank data
830 01:56:54.873061 u2DelayCellTimex100 = 762/100 ps
831 01:56:54.873117 CA0 delay=34 (5~63),Diff = 10 PI (12 cell)
832 01:56:54.873172 CA1 delay=34 (6~63),Diff = 10 PI (12 cell)
833 01:56:54.873228 CA2 delay=29 (1~57),Diff = 5 PI (6 cell)
834 01:56:54.873295 CA3 delay=24 (-3~51),Diff = 0 PI (0 cell)
835 01:56:54.873351 CA4 delay=24 (-3~52),Diff = 0 PI (0 cell)
836 01:56:54.873407 CA5 delay=30 (2~58),Diff = 6 PI (7 cell)
837 01:56:54.873462
838 01:56:54.873517 CA PerBit enable=1, Macro0, CA PI delay=24
839 01:56:54.873572 === u2Vref_new: 0x56 --> 0x2d
840 01:56:54.873627
841 01:56:54.873682 Vref(ca) range 1: 22
842 01:56:54.873737
843 01:56:54.873791 CS Dly= 11 (42-0-32)
844 01:56:54.873846 Write Rank1 MR13 =0xd8
845 01:56:54.873901 Write Rank1 MR13 =0xd8
846 01:56:54.873956 Write Rank1 MR12 =0x56
847 01:56:54.874010 [RankSwap] Rank num 2, (Multi 1), Rank 0
848 01:56:54.874065 Write Rank0 MR2 =0xad
849 01:56:54.874120 [Write Leveling]
850 01:56:54.874175 delay byte0 byte1 byte2 byte3
851 01:56:54.874230
852 01:56:54.874284 10 0 0
853 01:56:54.874340 11 0 0
854 01:56:54.874396 12 0 0
855 01:56:54.874452 13 0 0
856 01:56:54.874512 14 0 0
857 01:56:54.874572 15 0 0
858 01:56:54.874630 16 0 0
859 01:56:54.874702 17 0 0
860 01:56:54.874867 18 0 0
861 01:56:54.874979 19 0 0
862 01:56:54.875075 20 0 0
863 01:56:54.875167 21 0 0
864 01:56:54.875258 22 0 0
865 01:56:54.875346 23 0 0
866 01:56:54.875434 24 0 0
867 01:56:54.875521 25 0 0
868 01:56:54.875608 26 0 0
869 01:56:54.875696 27 0 0
870 01:56:54.875783 28 0 ff
871 01:56:54.875870 29 0 ff
872 01:56:54.875957 30 0 ff
873 01:56:54.876045 31 0 ff
874 01:56:54.876132 32 ff ff
875 01:56:54.876219 33 ff ff
876 01:56:54.876306 34 ff ff
877 01:56:54.876394 35 ff ff
878 01:56:54.876481 36 ff ff
879 01:56:54.876568 37 ff ff
880 01:56:54.876655 38 ff ff
881 01:56:54.876747 pass bytecount = 0xff (0xff: all bytes pass)
882 01:56:54.876833
883 01:56:54.876918 DQS0 dly: 32
884 01:56:54.877003 DQS1 dly: 28
885 01:56:54.877088 Write Rank0 MR2 =0x2d
886 01:56:54.877174 [RankSwap] Rank num 2, (Multi 1), Rank 0
887 01:56:54.877265 Write Rank0 MR1 =0xd6
888 01:56:54.877324 [Gating]
889 01:56:54.877379 ==
890 01:56:54.877434 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
891 01:56:54.877491 fsp= 1, odt_onoff= 1, Byte mode= 0
892 01:56:54.877547 ==
893 01:56:54.877602 3 1 0 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
894 01:56:54.877659 3 1 4 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
895 01:56:54.877715 3 1 8 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
896 01:56:54.877784 3 1 12 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
897 01:56:54.877840 3 1 16 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
898 01:56:54.877894 3 1 20 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
899 01:56:54.877949 3 1 24 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
900 01:56:54.878003 3 1 28 |302 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
901 01:56:54.878058 3 2 0 |606 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
902 01:56:54.878113 3 2 4 |3534 404 |(11 11)(11 11) |(0 0)(0 0)| 0
903 01:56:54.878169 3 2 8 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
904 01:56:54.878223 3 2 12 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
905 01:56:54.878278 3 2 16 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
906 01:56:54.878332 3 2 20 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
907 01:56:54.878387 3 2 24 |3534 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
908 01:56:54.878441 3 2 28 |3534 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
909 01:56:54.878496 3 3 0 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
910 01:56:54.878551 3 3 4 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
911 01:56:54.878605 3 3 8 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
912 01:56:54.878664 3 3 12 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
913 01:56:54.878741 3 3 16 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
914 01:56:54.878798 3 3 20 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
915 01:56:54.878853 3 3 24 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
916 01:56:54.878907 3 3 28 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
917 01:56:54.878962 3 4 0 |707 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
918 01:56:54.879017 3 4 4 |3d3d 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
919 01:56:54.879072 3 4 8 |3d3d 403 |(11 11)(11 11) |(1 1)(1 1)| 0
920 01:56:54.879126 3 4 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
921 01:56:54.879182 3 4 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
922 01:56:54.879236 3 4 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
923 01:56:54.879292 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
924 01:56:54.879347 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
925 01:56:54.879400 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
926 01:56:54.879456 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
927 01:56:54.879510 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
928 01:56:54.879569 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
929 01:56:54.879625 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
930 01:56:54.879680 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
931 01:56:54.879735 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
932 01:56:54.879789 [Byte 0] Lead/lag falling Transition (3, 5, 24)
933 01:56:54.879844 [Byte 1] Lead/lag falling Transition (3, 5, 24)
934 01:56:54.879899 3 5 28 |3e3d 3d3d |(11 11)(11 11) |(1 0)(1 0)| 0
935 01:56:54.879953 [Byte 0] Lead/lag Transition tap number (2)
936 01:56:54.880008 [Byte 1] Lead/lag Transition tap number (2)
937 01:56:54.880062 3 6 0 |404 3d3d |(11 11)(11 11) |(0 0)(0 0)| 0
938 01:56:54.880116 3 6 4 |4646 3e3d |(0 0)(11 11) |(0 0)(0 0)| 0
939 01:56:54.880171 [Byte 0]First pass (3, 6, 4)
940 01:56:54.880224 3 6 8 |4646 202 |(0 0)(11 11) |(0 0)(0 0)| 0
941 01:56:54.880473 3 6 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
942 01:56:54.880535 [Byte 1]First pass (3, 6, 12)
943 01:56:54.880590 3 6 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
944 01:56:54.880645 3 6 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
945 01:56:54.880727 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
946 01:56:54.880798 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
947 01:56:54.880853 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
948 01:56:54.880907 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
949 01:56:54.880962 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
950 01:56:54.881016 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
951 01:56:54.881072 All bytes gating window > 1UI, Early break!
952 01:56:54.881125
953 01:56:54.881179 best DQS0 dly(2T, 0.5T, PI) = (3, 5, 28)
954 01:56:54.881233
955 01:56:54.881331 best DQS1 dly(2T, 0.5T, PI) = (3, 5, 28)
956 01:56:54.881386
957 01:56:54.881439
958 01:56:54.881492
959 01:56:54.881545 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 1, 28)
960 01:56:54.881598
961 01:56:54.881652 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 1, 28)
962 01:56:54.881705
963 01:56:54.881759
964 01:56:54.881812 Write Rank0 MR1 =0x56
965 01:56:54.881865
966 01:56:54.881919 best RODT dly(2T, 0.5T) = (2, 2)
967 01:56:54.881973
968 01:56:54.882026 best RODT dly(2T, 0.5T) = (2, 2)
969 01:56:54.882079 ==
970 01:56:54.882132 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
971 01:56:54.882187 fsp= 1, odt_onoff= 1, Byte mode= 0
972 01:56:54.882240 ==
973 01:56:54.882294 Start DQ dly to find pass range UseTestEngine =0
974 01:56:54.882348 x-axis: bit #, y-axis: DQ dly (-127~63)
975 01:56:54.882402 RX Vref Scan = 0
976 01:56:54.882458 -26, [0] xxxxxxxx xxxxxxxx [MSB]
977 01:56:54.882516 -25, [0] xxxxxxxx xxxxxxxx [MSB]
978 01:56:54.882571 -24, [0] xxxxxxxx xxxxxxxx [MSB]
979 01:56:54.882626 -23, [0] xxxxxxxx xxxxxxxx [MSB]
980 01:56:54.882680 -22, [0] xxxxxxxx xxxxxxxx [MSB]
981 01:56:54.882735 -21, [0] xxxxxxxx xxxxxxxx [MSB]
982 01:56:54.882789 -20, [0] xxxxxxxx xxxxxxxx [MSB]
983 01:56:54.882843 -19, [0] xxxxxxxx xxxxxxxx [MSB]
984 01:56:54.882898 -18, [0] xxxxxxxx xxxxxxxx [MSB]
985 01:56:54.882952 -17, [0] xxxxxxxx xxxxxxxx [MSB]
986 01:56:54.883007 -16, [0] xxxxxxxx xxxxxxxx [MSB]
987 01:56:54.883062 -15, [0] xxxxxxxx xxxxxxxx [MSB]
988 01:56:54.883117 -14, [0] xxxxxxxx xxxxxxxx [MSB]
989 01:56:54.883171 -13, [0] xxxxxxxx xxxxxxxx [MSB]
990 01:56:54.883226 -12, [0] xxxxxxxx xxxxxxxx [MSB]
991 01:56:54.883281 -11, [0] xxxxxxxx xxxxxxxx [MSB]
992 01:56:54.883336 -10, [0] xxxxxxxx xxxxxxxx [MSB]
993 01:56:54.883391 -9, [0] xxxxxxxx xxxxxxxx [MSB]
994 01:56:54.883445 -8, [0] xxxxxxxx xxxxxxxx [MSB]
995 01:56:54.883500 -7, [0] xxxxxxxx xxxxxxxx [MSB]
996 01:56:54.883554 -6, [0] xxxxxxxx xxxxxxxx [MSB]
997 01:56:54.883609 -5, [0] xxxxxxxx xxxxxxxx [MSB]
998 01:56:54.883663 -4, [0] xxxxxxxx xxxxxxxx [MSB]
999 01:56:54.883717 -3, [0] xxxxxxxx xxxxxxxx [MSB]
1000 01:56:54.883772 -2, [0] xxxxxxxx xxxxxxxx [MSB]
1001 01:56:54.883826 -1, [0] xxxxxxxx xxxxxxxx [MSB]
1002 01:56:54.883880 0, [0] xxxoxxxx xxxxxxxx [MSB]
1003 01:56:54.883935 1, [0] xxxoxoxx xxxoxxxx [MSB]
1004 01:56:54.883990 2, [0] xxxoxoxx xxxoxxxx [MSB]
1005 01:56:54.884043 3, [0] xxxoxooo oxxoxoox [MSB]
1006 01:56:54.884098 4, [0] xxxoxooo oxxoxoox [MSB]
1007 01:56:54.884153 5, [0] xxxoxooo ooxooooo [MSB]
1008 01:56:54.884207 6, [0] xxxoxooo ooxooooo [MSB]
1009 01:56:54.884262 7, [0] xxoooooo ooxooooo [MSB]
1010 01:56:54.884316 8, [0] xooooooo oooooooo [MSB]
1011 01:56:54.884372 9, [0] xooooooo oooooooo [MSB]
1012 01:56:54.884428 31, [0] oooooooo oooooooo [MSB]
1013 01:56:54.884484 32, [0] oooxoooo oooooooo [MSB]
1014 01:56:54.884538 33, [0] oooxoooo oooooxoo [MSB]
1015 01:56:54.884593 34, [0] oooxoxxo oooooxxo [MSB]
1016 01:56:54.884647 35, [0] oooxoxxx xooooxxo [MSB]
1017 01:56:54.884702 36, [0] oooxoxxx xooxoxxx [MSB]
1018 01:56:54.884757 37, [0] oooxoxxx xxoxxxxx [MSB]
1019 01:56:54.884811 38, [0] oooxoxxx xxoxxxxx [MSB]
1020 01:56:54.884865 39, [0] oooxoxxx xxoxxxxx [MSB]
1021 01:56:54.884920 40, [0] oooxoxxx xxoxxxxx [MSB]
1022 01:56:54.884974 41, [0] xoxxxxxx xxoxxxxx [MSB]
1023 01:56:54.885029 42, [0] xxxxxxxx xxoxxxxx [MSB]
1024 01:56:54.885083 43, [0] xxxxxxxx xxxxxxxx [MSB]
1025 01:56:54.885146 iDelay=43, Bit 0, Center 25 (10 ~ 40) 31
1026 01:56:54.885202 iDelay=43, Bit 1, Center 24 (8 ~ 41) 34
1027 01:56:54.885261 iDelay=43, Bit 2, Center 23 (7 ~ 40) 34
1028 01:56:54.885352 iDelay=43, Bit 3, Center 15 (0 ~ 31) 32
1029 01:56:54.885405 iDelay=43, Bit 4, Center 23 (7 ~ 40) 34
1030 01:56:54.885458 iDelay=43, Bit 5, Center 17 (1 ~ 33) 33
1031 01:56:54.885511 iDelay=43, Bit 6, Center 18 (3 ~ 33) 31
1032 01:56:54.885563 iDelay=43, Bit 7, Center 18 (3 ~ 34) 32
1033 01:56:54.885616 iDelay=43, Bit 8, Center 18 (3 ~ 34) 32
1034 01:56:54.885669 iDelay=43, Bit 9, Center 20 (5 ~ 36) 32
1035 01:56:54.885721 iDelay=43, Bit 10, Center 25 (8 ~ 42) 35
1036 01:56:54.885774 iDelay=43, Bit 11, Center 18 (1 ~ 35) 35
1037 01:56:54.885826 iDelay=43, Bit 12, Center 20 (5 ~ 36) 32
1038 01:56:54.885878 iDelay=43, Bit 13, Center 17 (3 ~ 32) 30
1039 01:56:54.885931 iDelay=43, Bit 14, Center 18 (3 ~ 33) 31
1040 01:56:54.885983 iDelay=43, Bit 15, Center 20 (5 ~ 35) 31
1041 01:56:54.886053 ==
1042 01:56:54.886107 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1043 01:56:54.886161 fsp= 1, odt_onoff= 1, Byte mode= 0
1044 01:56:54.886236 ==
1045 01:56:54.886404 DQS Delay:
1046 01:56:54.886505 DQS0 = 0, DQS1 = 0
1047 01:56:54.886565 DQM Delay:
1048 01:56:54.886620 DQM0 = 20, DQM1 = 19
1049 01:56:54.886675 DQ Delay:
1050 01:56:54.886733 DQ0 =25, DQ1 =24, DQ2 =23, DQ3 =15
1051 01:56:54.886787 DQ4 =23, DQ5 =17, DQ6 =18, DQ7 =18
1052 01:56:54.886840 DQ8 =18, DQ9 =20, DQ10 =25, DQ11 =18
1053 01:56:54.886893 DQ12 =20, DQ13 =17, DQ14 =18, DQ15 =20
1054 01:56:54.886946
1055 01:56:54.886998
1056 01:56:54.887051 DramC Write-DBI off
1057 01:56:54.887104 ==
1058 01:56:54.887156 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1059 01:56:54.887210 fsp= 1, odt_onoff= 1, Byte mode= 0
1060 01:56:54.887263 ==
1061 01:56:54.887315 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
1062 01:56:54.887368
1063 01:56:54.887420 Begin, DQ Scan Range 924~1180
1064 01:56:54.887472
1065 01:56:54.887525
1066 01:56:54.887577 TX Vref Scan disable
1067 01:56:54.887630 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB]
1068 01:56:54.887684 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
1069 01:56:54.887738 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
1070 01:56:54.887792 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
1071 01:56:54.887846 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
1072 01:56:54.887900 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
1073 01:56:54.888146 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
1074 01:56:54.888209 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
1075 01:56:54.888264 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
1076 01:56:54.888318 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
1077 01:56:54.888372 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
1078 01:56:54.888426 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
1079 01:56:54.888479 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
1080 01:56:54.888533 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
1081 01:56:54.888587 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
1082 01:56:54.888641 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
1083 01:56:54.888699 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
1084 01:56:54.888793 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
1085 01:56:54.888848 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
1086 01:56:54.888902 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
1087 01:56:54.888956 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
1088 01:56:54.889010 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
1089 01:56:54.889064 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
1090 01:56:54.889117 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
1091 01:56:54.889172 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
1092 01:56:54.889226 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
1093 01:56:54.889319 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
1094 01:56:54.889419 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
1095 01:56:54.889504 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
1096 01:56:54.889572 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
1097 01:56:54.889628 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
1098 01:56:54.889682 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
1099 01:56:54.889736 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1100 01:56:54.889790 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1101 01:56:54.889844 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1102 01:56:54.889916 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1103 01:56:54.889972 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1104 01:56:54.890043 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1105 01:56:54.890210 962 |3 6 2|[0] xxxxxxxx xxxoxxxx [MSB]
1106 01:56:54.890324 963 |3 6 3|[0] xxxxxxxx xxxoxxxx [MSB]
1107 01:56:54.890392 964 |3 6 4|[0] xxxxxxxx ooxoxoxx [MSB]
1108 01:56:54.890454 965 |3 6 5|[0] xxxxxxxx ooxoooox [MSB]
1109 01:56:54.890515 966 |3 6 6|[0] xxxxxxxx ooxoooox [MSB]
1110 01:56:54.890577 967 |3 6 7|[0] xxxxxxxx ooxoooox [MSB]
1111 01:56:54.890633 968 |3 6 8|[0] xxxoxxxx ooxooooo [MSB]
1112 01:56:54.890691 969 |3 6 9|[0] xxxoxoox oooooooo [MSB]
1113 01:56:54.890747 970 |3 6 10|[0] xxxoxoox oooooooo [MSB]
1114 01:56:54.890802 971 |3 6 11|[0] xxxoooox oooooooo [MSB]
1115 01:56:54.890857 972 |3 6 12|[0] xxxooooo oooooooo [MSB]
1116 01:56:54.890911 973 |3 6 13|[0] xxoooooo oooooooo [MSB]
1117 01:56:54.890965 974 |3 6 14|[0] xooooooo oooooooo [MSB]
1118 01:56:54.891020 987 |3 6 27|[0] oooooooo oooooxoo [MSB]
1119 01:56:54.891074 988 |3 6 28|[0] oooooooo xxxxxxxx [MSB]
1120 01:56:54.891129 989 |3 6 29|[0] oooxoooo xxxxxxxx [MSB]
1121 01:56:54.891183 990 |3 6 30|[0] oooxoooo xxxxxxxx [MSB]
1122 01:56:54.891237 991 |3 6 31|[0] oooxoxoo xxxxxxxx [MSB]
1123 01:56:54.891291 992 |3 6 32|[0] xxxxxxxx xxxxxxxx [MSB]
1124 01:56:54.891345 Byte0, DQ PI dly=980, DQM PI dly= 980
1125 01:56:54.891398 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 20)
1126 01:56:54.891451
1127 01:56:54.891504 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 20)
1128 01:56:54.891557
1129 01:56:54.891609 Byte1, DQ PI dly=976, DQM PI dly= 976
1130 01:56:54.891662 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 16)
1131 01:56:54.891715
1132 01:56:54.891767 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 16)
1133 01:56:54.891824
1134 01:56:54.891876 ==
1135 01:56:54.891930 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1136 01:56:54.891983 fsp= 1, odt_onoff= 1, Byte mode= 0
1137 01:56:54.892037 ==
1138 01:56:54.892089 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
1139 01:56:54.892142
1140 01:56:54.892194 Begin, DQ Scan Range 952~1016
1141 01:56:54.892247 Write Rank0 MR14 =0x0
1142 01:56:54.892300
1143 01:56:54.892352 CH=0, VrefRange= 0, VrefLevel = 0
1144 01:56:54.892405 TX Bit0 (976~993) 18 984, Bit8 (966~983) 18 974,
1145 01:56:54.892459 TX Bit1 (976~992) 17 984, Bit9 (967~984) 18 975,
1146 01:56:54.892512 TX Bit2 (976~991) 16 983, Bit10 (970~989) 20 979,
1147 01:56:54.892566 TX Bit3 (969~985) 17 977, Bit11 (966~983) 18 974,
1148 01:56:54.892619 TX Bit4 (974~992) 19 983, Bit12 (967~983) 17 975,
1149 01:56:54.892672 TX Bit5 (970~986) 17 978, Bit13 (967~982) 16 974,
1150 01:56:54.892782 TX Bit6 (972~986) 15 979, Bit14 (968~984) 17 976,
1151 01:56:54.892892 TX Bit7 (976~989) 14 982, Bit15 (969~985) 17 977,
1152 01:56:54.892979
1153 01:56:54.893130 Write Rank0 MR14 =0x2
1154 01:56:54.893219
1155 01:56:54.893312 CH=0, VrefRange= 0, VrefLevel = 2
1156 01:56:54.893367 TX Bit0 (976~993) 18 984, Bit8 (966~984) 19 975,
1157 01:56:54.893421 TX Bit1 (975~992) 18 983, Bit9 (967~984) 18 975,
1158 01:56:54.893475 TX Bit2 (975~992) 18 983, Bit10 (970~989) 20 979,
1159 01:56:54.893529 TX Bit3 (969~985) 17 977, Bit11 (965~984) 20 974,
1160 01:56:54.893582 TX Bit4 (974~992) 19 983, Bit12 (967~984) 18 975,
1161 01:56:54.893636 TX Bit5 (970~986) 17 978, Bit13 (966~983) 18 974,
1162 01:56:54.893690 TX Bit6 (971~987) 17 979, Bit14 (968~984) 17 976,
1163 01:56:54.893743 TX Bit7 (976~990) 15 983, Bit15 (969~986) 18 977,
1164 01:56:54.893796
1165 01:56:54.893849 Write Rank0 MR14 =0x4
1166 01:56:54.893932
1167 01:56:54.893984 CH=0, VrefRange= 0, VrefLevel = 4
1168 01:56:54.894038 TX Bit0 (976~993) 18 984, Bit8 (965~984) 20 974,
1169 01:56:54.894090 TX Bit1 (976~992) 17 984, Bit9 (967~984) 18 975,
1170 01:56:54.894144 TX Bit2 (975~992) 18 983, Bit10 (970~989) 20 979,
1171 01:56:54.894196 TX Bit3 (969~985) 17 977, Bit11 (964~984) 21 974,
1172 01:56:54.894249 TX Bit4 (974~992) 19 983, Bit12 (967~984) 18 975,
1173 01:56:54.894302 TX Bit5 (970~986) 17 978, Bit13 (966~983) 18 974,
1174 01:56:54.894355 TX Bit6 (971~988) 18 979, Bit14 (967~985) 19 976,
1175 01:56:54.894408 TX Bit7 (975~990) 16 982, Bit15 (969~987) 19 978,
1176 01:56:54.894461
1177 01:56:54.894513 Write Rank0 MR14 =0x6
1178 01:56:54.894566
1179 01:56:54.894618 CH=0, VrefRange= 0, VrefLevel = 6
1180 01:56:54.894885 TX Bit0 (976~994) 19 985, Bit8 (964~985) 22 974,
1181 01:56:54.894948 TX Bit1 (975~993) 19 984, Bit9 (966~985) 20 975,
1182 01:56:54.895004 TX Bit2 (975~992) 18 983, Bit10 (969~990) 22 979,
1183 01:56:54.895059 TX Bit3 (969~986) 18 977, Bit11 (964~984) 21 974,
1184 01:56:54.895114 TX Bit4 (974~993) 20 983, Bit12 (967~985) 19 976,
1185 01:56:54.895168 TX Bit5 (970~987) 18 978, Bit13 (966~984) 19 975,
1186 01:56:54.895223 TX Bit6 (971~988) 18 979, Bit14 (967~985) 19 976,
1187 01:56:54.895277 TX Bit7 (975~991) 17 983, Bit15 (969~988) 20 978,
1188 01:56:54.895331
1189 01:56:54.895384 Write Rank0 MR14 =0x8
1190 01:56:54.895438
1191 01:56:54.895491 CH=0, VrefRange= 0, VrefLevel = 8
1192 01:56:54.895545 TX Bit0 (976~994) 19 985, Bit8 (964~985) 22 974,
1193 01:56:54.895608 TX Bit1 (975~993) 19 984, Bit9 (966~985) 20 975,
1194 01:56:54.895699 TX Bit2 (975~993) 19 984, Bit10 (969~990) 22 979,
1195 01:56:54.895801 TX Bit3 (968~986) 19 977, Bit11 (964~985) 22 974,
1196 01:56:54.895876 TX Bit4 (973~993) 21 983, Bit12 (966~985) 20 975,
1197 01:56:54.895932 TX Bit5 (969~988) 20 978, Bit13 (965~983) 19 974,
1198 01:56:54.895986 TX Bit6 (970~989) 20 979, Bit14 (967~986) 20 976,
1199 01:56:54.896040 TX Bit7 (974~991) 18 982, Bit15 (969~988) 20 978,
1200 01:56:54.896093
1201 01:56:54.896146 Write Rank0 MR14 =0xa
1202 01:56:54.896205
1203 01:56:54.896267 CH=0, VrefRange= 0, VrefLevel = 10
1204 01:56:54.896323 TX Bit0 (975~994) 20 984, Bit8 (963~985) 23 974,
1205 01:56:54.896377 TX Bit1 (975~993) 19 984, Bit9 (965~986) 22 975,
1206 01:56:54.896430 TX Bit2 (974~993) 20 983, Bit10 (969~990) 22 979,
1207 01:56:54.896483 TX Bit3 (968~987) 20 977, Bit11 (963~985) 23 974,
1208 01:56:54.896536 TX Bit4 (973~993) 21 983, Bit12 (965~986) 22 975,
1209 01:56:54.896589 TX Bit5 (969~988) 20 978, Bit13 (965~984) 20 974,
1210 01:56:54.896642 TX Bit6 (970~990) 21 980, Bit14 (966~987) 22 976,
1211 01:56:54.896695 TX Bit7 (973~991) 19 982, Bit15 (968~988) 21 978,
1212 01:56:54.896748
1213 01:56:54.896831 Write Rank0 MR14 =0xc
1214 01:56:54.896883
1215 01:56:54.896936 CH=0, VrefRange= 0, VrefLevel = 12
1216 01:56:54.896989 TX Bit0 (975~994) 20 984, Bit8 (963~986) 24 974,
1217 01:56:54.897042 TX Bit1 (974~994) 21 984, Bit9 (966~986) 21 976,
1218 01:56:54.897096 TX Bit2 (974~993) 20 983, Bit10 (969~990) 22 979,
1219 01:56:54.897149 TX Bit3 (968~987) 20 977, Bit11 (963~986) 24 974,
1220 01:56:54.897203 TX Bit4 (972~994) 23 983, Bit12 (965~986) 22 975,
1221 01:56:54.897262 TX Bit5 (969~990) 22 979, Bit13 (964~984) 21 974,
1222 01:56:54.897361 TX Bit6 (969~990) 22 979, Bit14 (966~988) 23 977,
1223 01:56:54.897415 TX Bit7 (972~992) 21 982, Bit15 (968~989) 22 978,
1224 01:56:54.897468
1225 01:56:54.897521 Write Rank0 MR14 =0xe
1226 01:56:54.897574
1227 01:56:54.897627 CH=0, VrefRange= 0, VrefLevel = 14
1228 01:56:54.897680 TX Bit0 (975~995) 21 985, Bit8 (963~986) 24 974,
1229 01:56:54.897733 TX Bit1 (974~993) 20 983, Bit9 (966~987) 22 976,
1230 01:56:54.897787 TX Bit2 (974~993) 20 983, Bit10 (969~991) 23 980,
1231 01:56:54.897840 TX Bit3 (968~988) 21 978, Bit11 (963~986) 24 974,
1232 01:56:54.897893 TX Bit4 (972~994) 23 983, Bit12 (965~987) 23 976,
1233 01:56:54.897946 TX Bit5 (969~990) 22 979, Bit13 (964~985) 22 974,
1234 01:56:54.897999 TX Bit6 (969~991) 23 980, Bit14 (966~988) 23 977,
1235 01:56:54.898053 TX Bit7 (972~992) 21 982, Bit15 (968~989) 22 978,
1236 01:56:54.898106
1237 01:56:54.898158 Write Rank0 MR14 =0x10
1238 01:56:54.898211
1239 01:56:54.898263 CH=0, VrefRange= 0, VrefLevel = 16
1240 01:56:54.898316 TX Bit0 (975~996) 22 985, Bit8 (962~987) 26 974,
1241 01:56:54.898379 TX Bit1 (974~994) 21 984, Bit9 (964~988) 25 976,
1242 01:56:54.898434 TX Bit2 (973~994) 22 983, Bit10 (969~991) 23 980,
1243 01:56:54.898487 TX Bit3 (967~988) 22 977, Bit11 (962~987) 26 974,
1244 01:56:54.898540 TX Bit4 (971~995) 25 983, Bit12 (964~988) 25 976,
1245 01:56:54.898593 TX Bit5 (969~990) 22 979, Bit13 (963~986) 24 974,
1246 01:56:54.898646 TX Bit6 (969~991) 23 980, Bit14 (965~988) 24 976,
1247 01:56:54.898699 TX Bit7 (972~992) 21 982, Bit15 (968~989) 22 978,
1248 01:56:54.898752
1249 01:56:54.898804 Write Rank0 MR14 =0x12
1250 01:56:54.898857
1251 01:56:54.898909 CH=0, VrefRange= 0, VrefLevel = 18
1252 01:56:54.898962 TX Bit0 (974~996) 23 985, Bit8 (963~988) 26 975,
1253 01:56:54.899015 TX Bit1 (974~994) 21 984, Bit9 (965~988) 24 976,
1254 01:56:54.899068 TX Bit2 (973~994) 22 983, Bit10 (969~991) 23 980,
1255 01:56:54.899122 TX Bit3 (967~989) 23 978, Bit11 (962~987) 26 974,
1256 01:56:54.899175 TX Bit4 (971~995) 25 983, Bit12 (963~988) 26 975,
1257 01:56:54.899228 TX Bit5 (968~991) 24 979, Bit13 (963~986) 24 974,
1258 01:56:54.899280 TX Bit6 (969~991) 23 980, Bit14 (964~988) 25 976,
1259 01:56:54.899333 TX Bit7 (971~993) 23 982, Bit15 (968~990) 23 979,
1260 01:56:54.899386
1261 01:56:54.899441 Write Rank0 MR14 =0x14
1262 01:56:54.899494
1263 01:56:54.899546 CH=0, VrefRange= 0, VrefLevel = 20
1264 01:56:54.899599 TX Bit0 (974~996) 23 985, Bit8 (963~988) 26 975,
1265 01:56:54.899652 TX Bit1 (973~995) 23 984, Bit9 (964~988) 25 976,
1266 01:56:54.899705 TX Bit2 (972~994) 23 983, Bit10 (969~992) 24 980,
1267 01:56:54.899758 TX Bit3 (967~990) 24 978, Bit11 (962~988) 27 975,
1268 01:56:54.899811 TX Bit4 (970~995) 26 982, Bit12 (963~989) 27 976,
1269 01:56:54.899864 TX Bit5 (968~991) 24 979, Bit13 (962~987) 26 974,
1270 01:56:54.899917 TX Bit6 (969~992) 24 980, Bit14 (964~989) 26 976,
1271 01:56:54.899970 TX Bit7 (971~993) 23 982, Bit15 (968~990) 23 979,
1272 01:56:54.900023
1273 01:56:54.900075 Write Rank0 MR14 =0x16
1274 01:56:54.900127
1275 01:56:54.900180 CH=0, VrefRange= 0, VrefLevel = 22
1276 01:56:54.900233 TX Bit0 (973~997) 25 985, Bit8 (962~987) 26 974,
1277 01:56:54.900286 TX Bit1 (972~995) 24 983, Bit9 (963~989) 27 976,
1278 01:56:54.900339 TX Bit2 (972~995) 24 983, Bit10 (968~991) 24 979,
1279 01:56:54.900392 TX Bit3 (967~990) 24 978, Bit11 (962~988) 27 975,
1280 01:56:54.900637 TX Bit4 (971~996) 26 983, Bit12 (963~988) 26 975,
1281 01:56:54.900697 TX Bit5 (968~991) 24 979, Bit13 (963~987) 25 975,
1282 01:56:54.900752 TX Bit6 (968~992) 25 980, Bit14 (963~989) 27 976,
1283 01:56:54.900805 TX Bit7 (971~993) 23 982, Bit15 (967~990) 24 978,
1284 01:56:54.900858
1285 01:56:54.900910 Write Rank0 MR14 =0x18
1286 01:56:54.900963
1287 01:56:54.901015 CH=0, VrefRange= 0, VrefLevel = 24
1288 01:56:54.901069 TX Bit0 (973~997) 25 985, Bit8 (962~986) 25 974,
1289 01:56:54.901122 TX Bit1 (972~995) 24 983, Bit9 (963~988) 26 975,
1290 01:56:54.901175 TX Bit2 (972~995) 24 983, Bit10 (968~991) 24 979,
1291 01:56:54.901229 TX Bit3 (967~991) 25 979, Bit11 (962~988) 27 975,
1292 01:56:54.901329 TX Bit4 (972~996) 25 984, Bit12 (963~989) 27 976,
1293 01:56:54.901383 TX Bit5 (968~991) 24 979, Bit13 (962~987) 26 974,
1294 01:56:54.901437 TX Bit6 (968~992) 25 980, Bit14 (964~988) 25 976,
1295 01:56:54.901490 TX Bit7 (970~993) 24 981, Bit15 (967~990) 24 978,
1296 01:56:54.901544
1297 01:56:54.901596 Write Rank0 MR14 =0x1a
1298 01:56:54.901649
1299 01:56:54.901702 CH=0, VrefRange= 0, VrefLevel = 26
1300 01:56:54.901755 TX Bit0 (973~997) 25 985, Bit8 (962~986) 25 974,
1301 01:56:54.901808 TX Bit1 (972~995) 24 983, Bit9 (963~988) 26 975,
1302 01:56:54.901861 TX Bit2 (972~995) 24 983, Bit10 (968~991) 24 979,
1303 01:56:54.901914 TX Bit3 (967~991) 25 979, Bit11 (962~988) 27 975,
1304 01:56:54.901967 TX Bit4 (972~996) 25 984, Bit12 (963~989) 27 976,
1305 01:56:54.902020 TX Bit5 (968~991) 24 979, Bit13 (962~987) 26 974,
1306 01:56:54.902073 TX Bit6 (968~992) 25 980, Bit14 (964~988) 25 976,
1307 01:56:54.902125 TX Bit7 (970~993) 24 981, Bit15 (967~990) 24 978,
1308 01:56:54.902179
1309 01:56:54.902231 Write Rank0 MR14 =0x1c
1310 01:56:54.902283
1311 01:56:54.902335 CH=0, VrefRange= 0, VrefLevel = 28
1312 01:56:54.902388 TX Bit0 (973~997) 25 985, Bit8 (962~986) 25 974,
1313 01:56:54.902441 TX Bit1 (972~995) 24 983, Bit9 (963~988) 26 975,
1314 01:56:54.902493 TX Bit2 (972~995) 24 983, Bit10 (968~991) 24 979,
1315 01:56:54.902547 TX Bit3 (967~991) 25 979, Bit11 (962~988) 27 975,
1316 01:56:54.902619 TX Bit4 (972~996) 25 984, Bit12 (963~989) 27 976,
1317 01:56:54.902674 TX Bit5 (968~991) 24 979, Bit13 (962~987) 26 974,
1318 01:56:54.902727 TX Bit6 (968~992) 25 980, Bit14 (964~988) 25 976,
1319 01:56:54.902780 TX Bit7 (970~993) 24 981, Bit15 (967~990) 24 978,
1320 01:56:54.902833
1321 01:56:54.902885 Write Rank0 MR14 =0x1e
1322 01:56:54.902938
1323 01:56:54.903014 CH=0, VrefRange= 0, VrefLevel = 30
1324 01:56:54.903193 TX Bit0 (973~997) 25 985, Bit8 (962~986) 25 974,
1325 01:56:54.903302 TX Bit1 (972~995) 24 983, Bit9 (963~988) 26 975,
1326 01:56:54.903363 TX Bit2 (972~995) 24 983, Bit10 (968~991) 24 979,
1327 01:56:54.903419 TX Bit3 (967~991) 25 979, Bit11 (962~988) 27 975,
1328 01:56:54.903473 TX Bit4 (972~996) 25 984, Bit12 (963~989) 27 976,
1329 01:56:54.903526 TX Bit5 (968~991) 24 979, Bit13 (962~987) 26 974,
1330 01:56:54.903580 TX Bit6 (968~992) 25 980, Bit14 (964~988) 25 976,
1331 01:56:54.903633 TX Bit7 (970~993) 24 981, Bit15 (967~990) 24 978,
1332 01:56:54.903686
1333 01:56:54.903740
1334 01:56:54.903792 TX Vref found, early break! 369< 380
1335 01:56:54.903846 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =762/100 ps
1336 01:56:54.903899 u1DelayCellOfst[0]=7 cells (6 PI)
1337 01:56:54.903952 u1DelayCellOfst[1]=5 cells (4 PI)
1338 01:56:54.904005 u1DelayCellOfst[2]=5 cells (4 PI)
1339 01:56:54.904058 u1DelayCellOfst[3]=0 cells (0 PI)
1340 01:56:54.904111 u1DelayCellOfst[4]=6 cells (5 PI)
1341 01:56:54.904163 u1DelayCellOfst[5]=0 cells (0 PI)
1342 01:56:54.904216 u1DelayCellOfst[6]=1 cells (1 PI)
1343 01:56:54.904268 u1DelayCellOfst[7]=2 cells (2 PI)
1344 01:56:54.904321 Byte0, DQ PI dly=979, DQM PI dly= 982
1345 01:56:54.904373 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 19)
1346 01:56:54.904427
1347 01:56:54.904480 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 19)
1348 01:56:54.904533
1349 01:56:54.904609 u1DelayCellOfst[8]=0 cells (0 PI)
1350 01:56:54.904696 u1DelayCellOfst[9]=1 cells (1 PI)
1351 01:56:54.904786 u1DelayCellOfst[10]=6 cells (5 PI)
1352 01:56:54.904868 u1DelayCellOfst[11]=1 cells (1 PI)
1353 01:56:54.904951 u1DelayCellOfst[12]=2 cells (2 PI)
1354 01:56:54.905033 u1DelayCellOfst[13]=0 cells (0 PI)
1355 01:56:54.905115 u1DelayCellOfst[14]=2 cells (2 PI)
1356 01:56:54.905197 u1DelayCellOfst[15]=5 cells (4 PI)
1357 01:56:54.905305 Byte1, DQ PI dly=974, DQM PI dly= 976
1358 01:56:54.905375 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 14)
1359 01:56:54.905429
1360 01:56:54.905482 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 14)
1361 01:56:54.905535
1362 01:56:54.905587 Write Rank0 MR14 =0x18
1363 01:56:54.905640
1364 01:56:54.905692 Final TX Range 0 Vref 24
1365 01:56:54.905744
1366 01:56:54.905796 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
1367 01:56:54.905849
1368 01:56:54.905901 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
1369 01:56:54.905954 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
1370 01:56:54.906007 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
1371 01:56:54.906059 Write Rank0 MR3 =0xb0
1372 01:56:54.906111 DramC Write-DBI on
1373 01:56:54.906163 ==
1374 01:56:54.906216 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1375 01:56:54.906268 fsp= 1, odt_onoff= 1, Byte mode= 0
1376 01:56:54.906320 ==
1377 01:56:54.906372 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
1378 01:56:54.906425
1379 01:56:54.906477 Begin, DQ Scan Range 696~760
1380 01:56:54.906528
1381 01:56:54.906580
1382 01:56:54.906632 TX Vref Scan disable
1383 01:56:54.906684 696 |2 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
1384 01:56:54.906738 697 |2 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
1385 01:56:54.906791 698 |2 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
1386 01:56:54.906844 699 |2 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
1387 01:56:54.906897 700 |2 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1388 01:56:54.906950 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1389 01:56:54.907004 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1390 01:56:54.907057 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1391 01:56:54.907111 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1392 01:56:54.907356 705 |2 6 1|[0] xxxxxxxx oooooooo [MSB]
1393 01:56:54.907418 706 |2 6 2|[0] xxxxxxxx oooooooo [MSB]
1394 01:56:54.907473 707 |2 6 3|[0] xxxxxxxx oooooooo [MSB]
1395 01:56:54.907527 708 |2 6 4|[0] xxxxxxxx oooooooo [MSB]
1396 01:56:54.907580 709 |2 6 5|[0] xxxxxxxx oooooooo [MSB]
1397 01:56:54.907633 710 |2 6 6|[0] xxxxxxxx oooooooo [MSB]
1398 01:56:54.907686 711 |2 6 7|[0] xxxxxxxx oooooooo [MSB]
1399 01:56:54.907740 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
1400 01:56:54.907794 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
1401 01:56:54.907848 734 |2 6 30|[0] oooooooo xxxxxxxx [MSB]
1402 01:56:54.907902 735 |2 6 31|[0] oooooooo xxxxxxxx [MSB]
1403 01:56:54.907955 736 |2 6 32|[0] oooooooo xxxxxxxx [MSB]
1404 01:56:54.908008 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
1405 01:56:54.908061 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
1406 01:56:54.908113 739 |2 6 35|[0] xxxxxxxx xxxxxxxx [MSB]
1407 01:56:54.908166 Byte0, DQ PI dly=726, DQM PI dly= 726
1408 01:56:54.908218 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 22)
1409 01:56:54.908271
1410 01:56:54.908323 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 22)
1411 01:56:54.908375
1412 01:56:54.908427 Byte1, DQ PI dly=719, DQM PI dly= 719
1413 01:56:54.908479 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 15)
1414 01:56:54.908531
1415 01:56:54.908583 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 15)
1416 01:56:54.908635
1417 01:56:54.908687 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
1418 01:56:54.908739 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
1419 01:56:54.908792 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
1420 01:56:54.908845 Write Rank0 MR3 =0x30
1421 01:56:54.908897 DramC Write-DBI off
1422 01:56:54.908948
1423 01:56:54.909000 [DATLAT]
1424 01:56:54.909052 Freq=1600, CH0 RK0, use_rxtx_scan=0
1425 01:56:54.909104
1426 01:56:54.909156 DATLAT Default: 0xf
1427 01:56:54.909207 7, 0xFFFF, sum=0
1428 01:56:54.909287 8, 0xFFFF, sum=0
1429 01:56:54.909356 9, 0xFFFF, sum=0
1430 01:56:54.909409 10, 0xFFFF, sum=0
1431 01:56:54.909465 11, 0xFFFF, sum=0
1432 01:56:54.909519 12, 0xFFFF, sum=0
1433 01:56:54.909578 13, 0xFFFF, sum=0
1434 01:56:54.909637 14, 0x0, sum=1
1435 01:56:54.909691 15, 0x0, sum=2
1436 01:56:54.909744 16, 0x0, sum=3
1437 01:56:54.909797 17, 0x0, sum=4
1438 01:56:54.909850 pattern=2 first_step=14 total pass=5 best_step=16
1439 01:56:54.909905 ==
1440 01:56:54.909959 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1441 01:56:54.910017 fsp= 1, odt_onoff= 1, Byte mode= 0
1442 01:56:54.910070 ==
1443 01:56:54.910128 Start DQ dly to find pass range UseTestEngine =1
1444 01:56:54.910207 x-axis: bit #, y-axis: DQ dly (-127~63)
1445 01:56:54.910291 RX Vref Scan = 1
1446 01:56:54.910381
1447 01:56:54.910465 RX Vref found, early break!
1448 01:56:54.910546
1449 01:56:54.910628 Final RX Vref 13, apply to both rank0 and 1
1450 01:56:54.910713 ==
1451 01:56:54.910795 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1452 01:56:54.910877 fsp= 1, odt_onoff= 1, Byte mode= 0
1453 01:56:54.910961 ==
1454 01:56:54.911051 DQS Delay:
1455 01:56:54.911133 DQS0 = 0, DQS1 = 0
1456 01:56:54.911214 DQM Delay:
1457 01:56:54.911295 DQM0 = 20, DQM1 = 19
1458 01:56:54.911375 DQ Delay:
1459 01:56:54.911457 DQ0 =25, DQ1 =24, DQ2 =24, DQ3 =15
1460 01:56:54.911538 DQ4 =22, DQ5 =16, DQ6 =18, DQ7 =19
1461 01:56:54.911620 DQ8 =18, DQ9 =20, DQ10 =24, DQ11 =16
1462 01:56:54.911701 DQ12 =20, DQ13 =16, DQ14 =18, DQ15 =20
1463 01:56:54.911786
1464 01:56:54.911936
1465 01:56:54.912051
1466 01:56:54.912147 [DramC_TX_OE_Calibration] TA2
1467 01:56:54.912230 Original DQ_B0 (3 6) =30, OEN = 27
1468 01:56:54.912313 Original DQ_B1 (3 6) =30, OEN = 27
1469 01:56:54.912395 23, 0x0, End_B0=23 End_B1=23
1470 01:56:54.912479 24, 0x0, End_B0=24 End_B1=24
1471 01:56:54.912562 25, 0x0, End_B0=25 End_B1=25
1472 01:56:54.912646 26, 0x0, End_B0=26 End_B1=26
1473 01:56:54.912729 27, 0x0, End_B0=27 End_B1=27
1474 01:56:54.912811 28, 0x0, End_B0=28 End_B1=28
1475 01:56:54.912993 29, 0x0, End_B0=29 End_B1=29
1476 01:56:54.913093 30, 0x0, End_B0=30 End_B1=30
1477 01:56:54.913181 31, 0xFFFF, End_B0=30 End_B1=30
1478 01:56:54.913288 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
1479 01:56:54.913360 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
1480 01:56:54.913414
1481 01:56:54.913467
1482 01:56:54.913530 Write Rank0 MR23 =0x3f
1483 01:56:54.913584 [DQSOSC]
1484 01:56:54.913638 [DQSOSCAuto] RK0, (LSB)MR18= 0xaa, (MSB)MR19= 0x3, tDQSOscB0 = 335 ps tDQSOscB1 = 0 ps
1485 01:56:54.913691 CH0_RK0: MR19=0x3, MR18=0xAA, DQSOSC=335, MR23=63, INC=21, DEC=32
1486 01:56:54.913744 Write Rank0 MR23 =0x3f
1487 01:56:54.913797 [DQSOSC]
1488 01:56:54.913849 [DQSOSCAuto] RK0, (LSB)MR18= 0xad, (MSB)MR19= 0x3, tDQSOscB0 = 334 ps tDQSOscB1 = 0 ps
1489 01:56:54.913902 CH0 RK0: MR19=3, MR18=AD
1490 01:56:54.913954 [RankSwap] Rank num 2, (Multi 1), Rank 1
1491 01:56:54.914006 Write Rank0 MR2 =0xad
1492 01:56:54.914059 [Write Leveling]
1493 01:56:54.914110 delay byte0 byte1 byte2 byte3
1494 01:56:54.914163
1495 01:56:54.914215 10 0 0
1496 01:56:54.914268 11 0 0
1497 01:56:54.914322 12 0 0
1498 01:56:54.914375 13 0 0
1499 01:56:54.914428 14 0 0
1500 01:56:54.914481 15 0 0
1501 01:56:54.914533 16 0 0
1502 01:56:54.914586 17 0 0
1503 01:56:54.914638 18 0 0
1504 01:56:54.914691 19 0 0
1505 01:56:54.914743 20 0 0
1506 01:56:54.914795 21 0 0
1507 01:56:54.914848 22 0 0
1508 01:56:54.914901 23 0 0
1509 01:56:54.914953 24 0 0
1510 01:56:54.915006 25 0 0
1511 01:56:54.915059 26 0 0
1512 01:56:54.915111 27 0 0
1513 01:56:54.915164 28 0 0
1514 01:56:54.915216 29 0 0
1515 01:56:54.915268 30 0 0
1516 01:56:54.915321 31 0 ff
1517 01:56:54.915374 32 0 ff
1518 01:56:54.915427 33 0 ff
1519 01:56:54.915479 34 ff ff
1520 01:56:54.915531 35 ff ff
1521 01:56:54.915584 36 ff ff
1522 01:56:54.915637 37 ff ff
1523 01:56:54.915689 38 ff ff
1524 01:56:54.915742 39 ff ff
1525 01:56:54.915795 40 ff ff
1526 01:56:54.915848 pass bytecount = 0xff (0xff: all bytes pass)
1527 01:56:54.915901
1528 01:56:54.915953 DQS0 dly: 34
1529 01:56:54.916005 DQS1 dly: 31
1530 01:56:54.916057 Write Rank0 MR2 =0x2d
1531 01:56:54.916109 [RankSwap] Rank num 2, (Multi 1), Rank 0
1532 01:56:54.916161 Write Rank1 MR1 =0xd6
1533 01:56:54.916213 [Gating]
1534 01:56:54.916265 ==
1535 01:56:54.916317 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1536 01:56:54.916368 fsp= 1, odt_onoff= 1, Byte mode= 0
1537 01:56:54.916420 ==
1538 01:56:54.916472 3 1 0 |2c2b 2c2b |(11 11)(11 11) |(1 1)(1 1)| 0
1539 01:56:54.916526 3 1 4 |2c2b 2c2b |(11 11)(11 11) |(0 0)(0 0)| 0
1540 01:56:54.916579 3 1 8 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 1)| 0
1541 01:56:54.916641 3 1 12 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
1542 01:56:54.916695 3 1 16 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
1543 01:56:54.916949 3 1 20 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
1544 01:56:54.917008 3 1 24 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
1545 01:56:54.917063 3 1 28 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
1546 01:56:54.917117 3 2 0 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
1547 01:56:54.917171 3 2 4 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
1548 01:56:54.917225 3 2 8 |2c2b 2c2b |(11 1)(11 11) |(1 0)(1 0)| 0
1549 01:56:54.917292 3 2 12 |201 2c2c |(11 11)(11 11) |(0 0)(0 0)| 0
1550 01:56:54.917346 3 2 16 |3534 201 |(11 11)(11 11) |(0 0)(0 0)| 0
1551 01:56:54.917400 3 2 20 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
1552 01:56:54.917454 3 2 24 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
1553 01:56:54.917507 3 2 28 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
1554 01:56:54.917560 3 3 0 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
1555 01:56:54.917614 3 3 4 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
1556 01:56:54.917667 3 3 8 |3534 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
1557 01:56:54.917720 3 3 12 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
1558 01:56:54.917773 3 3 16 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
1559 01:56:54.917826 3 3 20 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1560 01:56:54.917879 3 3 24 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1561 01:56:54.917932 3 3 28 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1562 01:56:54.917985 3 4 0 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
1563 01:56:54.918039 3 4 4 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
1564 01:56:54.918092 3 4 8 |1110 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
1565 01:56:54.918145 3 4 12 |706 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
1566 01:56:54.918199 3 4 16 |3d3d 505 |(11 11)(11 11) |(1 1)(1 1)| 0
1567 01:56:54.918252 3 4 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1568 01:56:54.918305 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1569 01:56:54.918358 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1570 01:56:54.918411 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1571 01:56:54.918463 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1572 01:56:54.918516 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1573 01:56:54.918570 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1574 01:56:54.918623 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1575 01:56:54.918676 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1576 01:56:54.918729 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1577 01:56:54.918783 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1578 01:56:54.918836 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1579 01:56:54.918889 [Byte 0] Lead/lag falling Transition (3, 6, 0)
1580 01:56:54.918942 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
1581 01:56:54.918994 [Byte 0] Lead/lag Transition tap number (2)
1582 01:56:54.919047 [Byte 1] Lead/lag Transition tap number (1)
1583 01:56:54.919098 3 6 8 |202 3d3d |(11 11)(11 11) |(0 0)(0 0)| 0
1584 01:56:54.919152 3 6 12 |202 3e3d |(11 11)(11 11) |(0 0)(0 0)| 0
1585 01:56:54.919205 3 6 16 |4646 202 |(0 0)(11 11) |(0 0)(0 0)| 0
1586 01:56:54.919258 [Byte 0]First pass (3, 6, 16)
1587 01:56:54.919310 3 6 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1588 01:56:54.919364 [Byte 1]First pass (3, 6, 20)
1589 01:56:54.919417 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1590 01:56:54.919470 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1591 01:56:54.919523 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1592 01:56:54.919576 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1593 01:56:54.919629 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1594 01:56:54.919683 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1595 01:56:54.919736 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1596 01:56:54.919789 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1597 01:56:54.919843 All bytes gating window > 1UI, Early break!
1598 01:56:54.919895
1599 01:56:54.919947 best DQS0 dly(2T, 0.5T, PI) = (3, 6, 4)
1600 01:56:54.919999
1601 01:56:54.920051 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 6)
1602 01:56:54.920103
1603 01:56:54.920154
1604 01:56:54.920206
1605 01:56:54.920258 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 4)
1606 01:56:54.920310
1607 01:56:54.920361 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 6)
1608 01:56:54.920413
1609 01:56:54.920465
1610 01:56:54.920516 Write Rank1 MR1 =0x56
1611 01:56:54.920568
1612 01:56:54.920639 best RODT dly(2T, 0.5T) = (2, 3)
1613 01:56:54.920720
1614 01:56:54.920788 best RODT dly(2T, 0.5T) = (2, 3)
1615 01:56:54.920842 ==
1616 01:56:54.920895 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1617 01:56:54.920949 fsp= 1, odt_onoff= 1, Byte mode= 0
1618 01:56:54.921004 ==
1619 01:56:54.921057 Start DQ dly to find pass range UseTestEngine =0
1620 01:56:54.921109 x-axis: bit #, y-axis: DQ dly (-127~63)
1621 01:56:54.921162 RX Vref Scan = 0
1622 01:56:54.921214 -26, [0] xxxxxxxx xxxxxxxx [MSB]
1623 01:56:54.921290 -25, [0] xxxxxxxx xxxxxxxx [MSB]
1624 01:56:54.921358 -24, [0] xxxxxxxx xxxxxxxx [MSB]
1625 01:56:54.921412 -23, [0] xxxxxxxx xxxxxxxx [MSB]
1626 01:56:54.921465 -22, [0] xxxxxxxx xxxxxxxx [MSB]
1627 01:56:54.921518 -21, [0] xxxxxxxx xxxxxxxx [MSB]
1628 01:56:54.921572 -20, [0] xxxxxxxx xxxxxxxx [MSB]
1629 01:56:54.921625 -19, [0] xxxxxxxx xxxxxxxx [MSB]
1630 01:56:54.921677 -18, [0] xxxxxxxx xxxxxxxx [MSB]
1631 01:56:54.921730 -17, [0] xxxxxxxx xxxxxxxx [MSB]
1632 01:56:54.921783 -16, [0] xxxxxxxx xxxxxxxx [MSB]
1633 01:56:54.921836 -15, [0] xxxxxxxx xxxxxxxx [MSB]
1634 01:56:54.921890 -14, [0] xxxxxxxx xxxxxxxx [MSB]
1635 01:56:54.921943 -13, [0] xxxxxxxx xxxxxxxx [MSB]
1636 01:56:54.921996 -12, [0] xxxxxxxx xxxxxxxx [MSB]
1637 01:56:54.922050 -11, [0] xxxxxxxx xxxxxxxx [MSB]
1638 01:56:54.922103 -10, [0] xxxxxxxx xxxxxxxx [MSB]
1639 01:56:54.922157 -9, [0] xxxxxxxx xxxxxxxx [MSB]
1640 01:56:54.922211 -8, [0] xxxxxxxx xxxxxxxx [MSB]
1641 01:56:54.922265 -7, [0] xxxxxxxx xxxxxxxx [MSB]
1642 01:56:54.922318 -6, [0] xxxxxxxx xxxxxxxx [MSB]
1643 01:56:54.922371 -5, [0] xxxxxxxx xxxxxxxx [MSB]
1644 01:56:54.922425 -4, [0] xxxxxxxx xxxxxxxx [MSB]
1645 01:56:54.922477 -3, [0] xxxxxxxx xxxxxxxx [MSB]
1646 01:56:54.922531 -2, [0] xxxxxxxx xxxxxxxx [MSB]
1647 01:56:54.922584 -1, [0] xxxoxxxx xxxxxxxx [MSB]
1648 01:56:54.922637 0, [0] xxxoxxxx oxxoxoox [MSB]
1649 01:56:54.922884 1, [0] xxxoxoxx oxxoxoox [MSB]
1650 01:56:54.922943 2, [0] xxxoxooo ooxoooox [MSB]
1651 01:56:54.922998 3, [0] xxxoxooo ooxooooo [MSB]
1652 01:56:54.923051 4, [0] xxxoxooo ooxooooo [MSB]
1653 01:56:54.923105 5, [0] xxxoxooo ooxooooo [MSB]
1654 01:56:54.923158 6, [0] xxxooooo oooooooo [MSB]
1655 01:56:54.923211 7, [0] xooooooo oooooooo [MSB]
1656 01:56:54.923264 8, [0] xooooooo oooooooo [MSB]
1657 01:56:54.923317 34, [0] oooooooo oooooooo [MSB]
1658 01:56:54.923371 35, [0] oooxoooo oooxoooo [MSB]
1659 01:56:54.923424 36, [0] oooxoooo oooxoxxo [MSB]
1660 01:56:54.923477 37, [0] oooxoxxx xooxoxxo [MSB]
1661 01:56:54.923549 38, [0] oooxoxxx xxoxxxxo [MSB]
1662 01:56:54.923605 39, [0] oooxoxxx xxoxxxxx [MSB]
1663 01:56:54.923690 40, [0] oooxoxxx xxoxxxxx [MSB]
1664 01:56:54.923861 41, [0] oooxoxxx xxoxxxxx [MSB]
1665 01:56:54.923955 42, [0] oooxxxxx xxoxxxxx [MSB]
1666 01:56:54.924014 43, [0] xoxxxxxx xxxxxxxx [MSB]
1667 01:56:54.924074 44, [0] xxxxxxxx xxxxxxxx [MSB]
1668 01:56:54.924147 iDelay=44, Bit 0, Center 25 (9 ~ 42) 34
1669 01:56:54.924231 iDelay=44, Bit 1, Center 25 (7 ~ 43) 37
1670 01:56:54.924313 iDelay=44, Bit 2, Center 24 (7 ~ 42) 36
1671 01:56:54.924395 iDelay=44, Bit 3, Center 16 (-1 ~ 34) 36
1672 01:56:54.924477 iDelay=44, Bit 4, Center 23 (6 ~ 41) 36
1673 01:56:54.924558 iDelay=44, Bit 5, Center 18 (1 ~ 36) 36
1674 01:56:54.924640 iDelay=44, Bit 6, Center 19 (2 ~ 36) 35
1675 01:56:54.924721 iDelay=44, Bit 7, Center 19 (2 ~ 36) 35
1676 01:56:54.924803 iDelay=44, Bit 8, Center 18 (0 ~ 36) 37
1677 01:56:54.924884 iDelay=44, Bit 9, Center 19 (2 ~ 37) 36
1678 01:56:54.924967 iDelay=44, Bit 10, Center 24 (6 ~ 42) 37
1679 01:56:54.925049 iDelay=44, Bit 11, Center 17 (0 ~ 34) 35
1680 01:56:54.925131 iDelay=44, Bit 12, Center 19 (2 ~ 37) 36
1681 01:56:54.925212 iDelay=44, Bit 13, Center 17 (0 ~ 35) 36
1682 01:56:54.925313 iDelay=44, Bit 14, Center 17 (0 ~ 35) 36
1683 01:56:54.925382 iDelay=44, Bit 15, Center 20 (3 ~ 38) 36
1684 01:56:54.925435 ==
1685 01:56:54.925488 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1686 01:56:54.925541 fsp= 1, odt_onoff= 1, Byte mode= 0
1687 01:56:54.925594 ==
1688 01:56:54.925646 DQS Delay:
1689 01:56:54.925698 DQS0 = 0, DQS1 = 0
1690 01:56:54.925750 DQM Delay:
1691 01:56:54.925802 DQM0 = 21, DQM1 = 18
1692 01:56:54.925858 DQ Delay:
1693 01:56:54.925910 DQ0 =25, DQ1 =25, DQ2 =24, DQ3 =16
1694 01:56:54.925963 DQ4 =23, DQ5 =18, DQ6 =19, DQ7 =19
1695 01:56:54.926015 DQ8 =18, DQ9 =19, DQ10 =24, DQ11 =17
1696 01:56:54.926068 DQ12 =19, DQ13 =17, DQ14 =17, DQ15 =20
1697 01:56:54.926119
1698 01:56:54.926172
1699 01:56:54.926223 DramC Write-DBI off
1700 01:56:54.926275 ==
1701 01:56:54.926328 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1702 01:56:54.926380 fsp= 1, odt_onoff= 1, Byte mode= 0
1703 01:56:54.926432 ==
1704 01:56:54.926484 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
1705 01:56:54.926537
1706 01:56:54.926589 Begin, DQ Scan Range 927~1183
1707 01:56:54.926641
1708 01:56:54.926693
1709 01:56:54.926745 TX Vref Scan disable
1710 01:56:54.926797 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
1711 01:56:54.926851 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
1712 01:56:54.926904 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
1713 01:56:54.926957 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
1714 01:56:54.927010 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
1715 01:56:54.927064 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
1716 01:56:54.927116 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
1717 01:56:54.927170 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
1718 01:56:54.927223 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
1719 01:56:54.927276 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
1720 01:56:54.927329 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
1721 01:56:54.927382 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
1722 01:56:54.927435 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
1723 01:56:54.927488 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
1724 01:56:54.927541 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
1725 01:56:54.927594 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
1726 01:56:54.927647 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
1727 01:56:54.927700 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
1728 01:56:54.927753 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
1729 01:56:54.927806 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
1730 01:56:54.927859 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
1731 01:56:54.927913 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
1732 01:56:54.927966 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
1733 01:56:54.928019 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
1734 01:56:54.928073 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
1735 01:56:54.928126 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
1736 01:56:54.928179 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
1737 01:56:54.928232 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
1738 01:56:54.928285 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
1739 01:56:54.928338 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1740 01:56:54.928391 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1741 01:56:54.928444 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1742 01:56:54.928497 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1743 01:56:54.928550 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1744 01:56:54.928603 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1745 01:56:54.928657 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
1746 01:56:54.928710 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
1747 01:56:54.928763 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
1748 01:56:54.928815 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
1749 01:56:54.928868 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
1750 01:56:54.928921 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
1751 01:56:54.928974 968 |3 6 8|[0] xxxxxxxx xxxoxxxx [MSB]
1752 01:56:54.929027 969 |3 6 9|[0] xxxxxxxx ooxoooox [MSB]
1753 01:56:54.929080 970 |3 6 10|[0] xxxxxxxx ooxoooox [MSB]
1754 01:56:54.929133 971 |3 6 11|[0] xxxxxxxx ooxoooox [MSB]
1755 01:56:54.929188 972 |3 6 12|[0] xxxoxoxx ooxoooox [MSB]
1756 01:56:54.929241 973 |3 6 13|[0] xxxoxoox ooxooooo [MSB]
1757 01:56:54.929340 974 |3 6 14|[0] xxxoxoox ooxooooo [MSB]
1758 01:56:54.929394 975 |3 6 15|[0] xxxoxoox oooooooo [MSB]
1759 01:56:54.929448 976 |3 6 16|[0] xxxoxooo oooooooo [MSB]
1760 01:56:54.929501 977 |3 6 17|[0] xooooooo oooooooo [MSB]
1761 01:56:54.929554 991 |3 6 31|[0] oooooooo oxxxxxxx [MSB]
1762 01:56:54.929608 992 |3 6 32|[0] oooooooo xxxxxxxx [MSB]
1763 01:56:54.929661 993 |3 6 33|[0] oooooooo xxxxxxxx [MSB]
1764 01:56:54.929715 994 |3 6 34|[0] oooooxoo xxxxxxxx [MSB]
1765 01:56:54.929963 995 |3 6 35|[0] oooxoxoo xxxxxxxx [MSB]
1766 01:56:54.930025 996 |3 6 36|[0] oooxoxxo xxxxxxxx [MSB]
1767 01:56:54.930079 997 |3 6 37|[0] xxxxxxxx xxxxxxxx [MSB]
1768 01:56:54.930133 Byte0, DQ PI dly=984, DQM PI dly= 984
1769 01:56:54.930185 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 24)
1770 01:56:54.930238
1771 01:56:54.930290 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 24)
1772 01:56:54.930343
1773 01:56:54.930395 Byte1, DQ PI dly=980, DQM PI dly= 980
1774 01:56:54.930447 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 20)
1775 01:56:54.930499
1776 01:56:54.930560 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 20)
1777 01:56:54.930614
1778 01:56:54.930666 ==
1779 01:56:54.930718 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1780 01:56:54.930770 fsp= 1, odt_onoff= 1, Byte mode= 0
1781 01:56:54.930823 ==
1782 01:56:54.930875 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
1783 01:56:54.930928
1784 01:56:54.930979 Begin, DQ Scan Range 956~1020
1785 01:56:54.931031 Write Rank1 MR14 =0x0
1786 01:56:54.931083
1787 01:56:54.931135 CH=0, VrefRange= 0, VrefLevel = 0
1788 01:56:54.931188 TX Bit0 (979~998) 20 988, Bit8 (971~988) 18 979,
1789 01:56:54.931241 TX Bit1 (979~996) 18 987, Bit9 (973~989) 17 981,
1790 01:56:54.931294 TX Bit2 (979~996) 18 987, Bit10 (976~992) 17 984,
1791 01:56:54.931346 TX Bit3 (973~991) 19 982, Bit11 (969~989) 21 979,
1792 01:56:54.931399 TX Bit4 (979~996) 18 987, Bit12 (972~989) 18 980,
1793 01:56:54.931452 TX Bit5 (976~990) 15 983, Bit13 (970~987) 18 978,
1794 01:56:54.931504 TX Bit6 (976~992) 17 984, Bit14 (973~989) 17 981,
1795 01:56:54.931557 TX Bit7 (977~993) 17 985, Bit15 (976~990) 15 983,
1796 01:56:54.931610
1797 01:56:54.931661 Write Rank1 MR14 =0x2
1798 01:56:54.931713
1799 01:56:54.931765 CH=0, VrefRange= 0, VrefLevel = 2
1800 01:56:54.931817 TX Bit0 (979~998) 20 988, Bit8 (971~989) 19 980,
1801 01:56:54.931869 TX Bit1 (978~997) 20 987, Bit9 (971~989) 19 980,
1802 01:56:54.931921 TX Bit2 (979~996) 18 987, Bit10 (976~992) 17 984,
1803 01:56:54.931974 TX Bit3 (973~991) 19 982, Bit11 (969~989) 21 979,
1804 01:56:54.932026 TX Bit4 (978~997) 20 987, Bit12 (971~990) 20 980,
1805 01:56:54.932079 TX Bit5 (976~991) 16 983, Bit13 (970~988) 19 979,
1806 01:56:54.932131 TX Bit6 (976~992) 17 984, Bit14 (971~989) 19 980,
1807 01:56:54.932184 TX Bit7 (977~993) 17 985, Bit15 (975~990) 16 982,
1808 01:56:54.932236
1809 01:56:54.932287 Write Rank1 MR14 =0x4
1810 01:56:54.932338
1811 01:56:54.932390 CH=0, VrefRange= 0, VrefLevel = 4
1812 01:56:54.932442 TX Bit0 (979~999) 21 989, Bit8 (971~989) 19 980,
1813 01:56:54.932495 TX Bit1 (978~997) 20 987, Bit9 (972~990) 19 981,
1814 01:56:54.932547 TX Bit2 (978~997) 20 987, Bit10 (976~993) 18 984,
1815 01:56:54.932600 TX Bit3 (972~991) 20 981, Bit11 (970~989) 20 979,
1816 01:56:54.932652 TX Bit4 (978~998) 21 988, Bit12 (971~990) 20 980,
1817 01:56:54.932704 TX Bit5 (976~991) 16 983, Bit13 (970~989) 20 979,
1818 01:56:54.932756 TX Bit6 (975~992) 18 983, Bit14 (971~990) 20 980,
1819 01:56:54.932809 TX Bit7 (977~994) 18 985, Bit15 (975~991) 17 983,
1820 01:56:54.932861
1821 01:56:54.932912 Write Rank1 MR14 =0x6
1822 01:56:54.932963
1823 01:56:54.933016 CH=0, VrefRange= 0, VrefLevel = 6
1824 01:56:54.933068 TX Bit0 (978~999) 22 988, Bit8 (970~990) 21 980,
1825 01:56:54.933121 TX Bit1 (978~998) 21 988, Bit9 (972~990) 19 981,
1826 01:56:54.933172 TX Bit2 (978~998) 21 988, Bit10 (976~993) 18 984,
1827 01:56:54.933224 TX Bit3 (972~992) 21 982, Bit11 (969~990) 22 979,
1828 01:56:54.933318 TX Bit4 (978~998) 21 988, Bit12 (971~990) 20 980,
1829 01:56:54.933373 TX Bit5 (975~991) 17 983, Bit13 (970~989) 20 979,
1830 01:56:54.933426 TX Bit6 (975~993) 19 984, Bit14 (971~990) 20 980,
1831 01:56:54.933478 TX Bit7 (977~994) 18 985, Bit15 (974~991) 18 982,
1832 01:56:54.933530
1833 01:56:54.933582 Write Rank1 MR14 =0x8
1834 01:56:54.933633
1835 01:56:54.933685 CH=0, VrefRange= 0, VrefLevel = 8
1836 01:56:54.933737 TX Bit0 (978~999) 22 988, Bit8 (970~990) 21 980,
1837 01:56:54.933789 TX Bit1 (977~998) 22 987, Bit9 (971~991) 21 981,
1838 01:56:54.933842 TX Bit2 (978~998) 21 988, Bit10 (976~993) 18 984,
1839 01:56:54.933894 TX Bit3 (971~992) 22 981, Bit11 (968~990) 23 979,
1840 01:56:54.933947 TX Bit4 (977~998) 22 987, Bit12 (970~991) 22 980,
1841 01:56:54.933999 TX Bit5 (975~992) 18 983, Bit13 (969~990) 22 979,
1842 01:56:54.934052 TX Bit6 (975~993) 19 984, Bit14 (971~990) 20 980,
1843 01:56:54.934104 TX Bit7 (977~995) 19 986, Bit15 (975~991) 17 983,
1844 01:56:54.934156
1845 01:56:54.934207 Write Rank1 MR14 =0xa
1846 01:56:54.934259
1847 01:56:54.934311 CH=0, VrefRange= 0, VrefLevel = 10
1848 01:56:54.934363 TX Bit0 (978~1000) 23 989, Bit8 (969~990) 22 979,
1849 01:56:54.934416 TX Bit1 (978~999) 22 988, Bit9 (970~991) 22 980,
1850 01:56:54.934468 TX Bit2 (977~998) 22 987, Bit10 (975~994) 20 984,
1851 01:56:54.934520 TX Bit3 (971~993) 23 982, Bit11 (969~990) 22 979,
1852 01:56:54.934573 TX Bit4 (978~999) 22 988, Bit12 (970~991) 22 980,
1853 01:56:54.934625 TX Bit5 (974~992) 19 983, Bit13 (969~990) 22 979,
1854 01:56:54.934678 TX Bit6 (974~994) 21 984, Bit14 (970~990) 21 980,
1855 01:56:54.934730 TX Bit7 (976~996) 21 986, Bit15 (974~992) 19 983,
1856 01:56:54.934782
1857 01:56:54.934834 Write Rank1 MR14 =0xc
1858 01:56:54.934886
1859 01:56:54.934938 CH=0, VrefRange= 0, VrefLevel = 12
1860 01:56:54.934989 TX Bit0 (978~1000) 23 989, Bit8 (969~990) 22 979,
1861 01:56:54.935042 TX Bit1 (978~999) 22 988, Bit9 (971~991) 21 981,
1862 01:56:54.935095 TX Bit2 (977~999) 23 988, Bit10 (975~994) 20 984,
1863 01:56:54.935147 TX Bit3 (970~993) 24 981, Bit11 (969~991) 23 980,
1864 01:56:54.935199 TX Bit4 (978~999) 22 988, Bit12 (969~991) 23 980,
1865 01:56:54.935252 TX Bit5 (974~992) 19 983, Bit13 (969~990) 22 979,
1866 01:56:54.935305 TX Bit6 (974~994) 21 984, Bit14 (969~991) 23 980,
1867 01:56:54.935357 TX Bit7 (976~995) 20 985, Bit15 (974~992) 19 983,
1868 01:56:54.935409
1869 01:56:54.935461 Write Rank1 MR14 =0xe
1870 01:56:54.935512
1871 01:56:54.935564 CH=0, VrefRange= 0, VrefLevel = 14
1872 01:56:54.935616 TX Bit0 (978~1000) 23 989, Bit8 (969~991) 23 980,
1873 01:56:54.935911 TX Bit1 (978~999) 22 988, Bit9 (970~991) 22 980,
1874 01:56:54.936025 TX Bit2 (977~999) 23 988, Bit10 (975~995) 21 985,
1875 01:56:54.936086 TX Bit3 (970~993) 24 981, Bit11 (968~991) 24 979,
1876 01:56:54.936142 TX Bit4 (977~999) 23 988, Bit12 (969~991) 23 980,
1877 01:56:54.936199 TX Bit5 (973~993) 21 983, Bit13 (969~990) 22 979,
1878 01:56:54.936253 TX Bit6 (973~995) 23 984, Bit14 (970~991) 22 980,
1879 01:56:54.936306 TX Bit7 (976~997) 22 986, Bit15 (973~993) 21 983,
1880 01:56:54.936359
1881 01:56:54.936411 Write Rank1 MR14 =0x10
1882 01:56:54.936464
1883 01:56:54.936516 CH=0, VrefRange= 0, VrefLevel = 16
1884 01:56:54.936568 TX Bit0 (978~1000) 23 989, Bit8 (969~991) 23 980,
1885 01:56:54.936621 TX Bit1 (978~999) 22 988, Bit9 (970~991) 22 980,
1886 01:56:54.936674 TX Bit2 (977~999) 23 988, Bit10 (975~995) 21 985,
1887 01:56:54.936726 TX Bit3 (970~993) 24 981, Bit11 (968~991) 24 979,
1888 01:56:54.936779 TX Bit4 (977~999) 23 988, Bit12 (969~991) 23 980,
1889 01:56:54.936831 TX Bit5 (973~993) 21 983, Bit13 (969~990) 22 979,
1890 01:56:54.936883 TX Bit6 (973~995) 23 984, Bit14 (970~991) 22 980,
1891 01:56:54.936935 TX Bit7 (976~997) 22 986, Bit15 (973~993) 21 983,
1892 01:56:54.936987
1893 01:56:54.937039 Write Rank1 MR14 =0x12
1894 01:56:54.937091
1895 01:56:54.937142 CH=0, VrefRange= 0, VrefLevel = 18
1896 01:56:54.937195 TX Bit0 (978~1001) 24 989, Bit8 (969~991) 23 980,
1897 01:56:54.937248 TX Bit1 (977~1000) 24 988, Bit9 (969~992) 24 980,
1898 01:56:54.937309 TX Bit2 (977~999) 23 988, Bit10 (974~996) 23 985,
1899 01:56:54.937362 TX Bit3 (970~994) 25 982, Bit11 (968~991) 24 979,
1900 01:56:54.937415 TX Bit4 (977~1000) 24 988, Bit12 (969~992) 24 980,
1901 01:56:54.937468 TX Bit5 (972~994) 23 983, Bit13 (968~991) 24 979,
1902 01:56:54.937521 TX Bit6 (972~996) 25 984, Bit14 (969~991) 23 980,
1903 01:56:54.937574 TX Bit7 (976~998) 23 987, Bit15 (972~993) 22 982,
1904 01:56:54.937626
1905 01:56:54.937678 Write Rank1 MR14 =0x14
1906 01:56:54.937730
1907 01:56:54.937781 CH=0, VrefRange= 0, VrefLevel = 20
1908 01:56:54.937834 TX Bit0 (978~1001) 24 989, Bit8 (968~991) 24 979,
1909 01:56:54.937886 TX Bit1 (977~1000) 24 988, Bit9 (969~992) 24 980,
1910 01:56:54.937939 TX Bit2 (977~999) 23 988, Bit10 (975~997) 23 986,
1911 01:56:54.937991 TX Bit3 (970~995) 26 982, Bit11 (967~991) 25 979,
1912 01:56:54.938043 TX Bit4 (976~1000) 25 988, Bit12 (968~992) 25 980,
1913 01:56:54.938096 TX Bit5 (971~994) 24 982, Bit13 (968~991) 24 979,
1914 01:56:54.938148 TX Bit6 (972~997) 26 984, Bit14 (969~992) 24 980,
1915 01:56:54.938201 TX Bit7 (975~998) 24 986, Bit15 (971~994) 24 982,
1916 01:56:54.938253
1917 01:56:54.938305 Write Rank1 MR14 =0x16
1918 01:56:54.938357
1919 01:56:54.938408 CH=0, VrefRange= 0, VrefLevel = 22
1920 01:56:54.938461 TX Bit0 (977~1001) 25 989, Bit8 (968~991) 24 979,
1921 01:56:54.938514 TX Bit1 (977~1000) 24 988, Bit9 (969~992) 24 980,
1922 01:56:54.938566 TX Bit2 (977~1000) 24 988, Bit10 (974~997) 24 985,
1923 01:56:54.938619 TX Bit3 (969~995) 27 982, Bit11 (968~991) 24 979,
1924 01:56:54.938671 TX Bit4 (976~1000) 25 988, Bit12 (969~992) 24 980,
1925 01:56:54.938724 TX Bit5 (971~994) 24 982, Bit13 (968~991) 24 979,
1926 01:56:54.938777 TX Bit6 (971~998) 28 984, Bit14 (969~992) 24 980,
1927 01:56:54.938830 TX Bit7 (974~998) 25 986, Bit15 (971~994) 24 982,
1928 01:56:54.938882
1929 01:56:54.938937 Write Rank1 MR14 =0x18
1930 01:56:54.938989
1931 01:56:54.939040 CH=0, VrefRange= 0, VrefLevel = 24
1932 01:56:54.939093 TX Bit0 (977~1001) 25 989, Bit8 (968~991) 24 979,
1933 01:56:54.939145 TX Bit1 (977~1000) 24 988, Bit9 (969~992) 24 980,
1934 01:56:54.939198 TX Bit2 (977~1000) 24 988, Bit10 (974~997) 24 985,
1935 01:56:54.939251 TX Bit3 (969~995) 27 982, Bit11 (968~991) 24 979,
1936 01:56:54.939303 TX Bit4 (976~1000) 25 988, Bit12 (969~992) 24 980,
1937 01:56:54.939357 TX Bit5 (971~994) 24 982, Bit13 (968~991) 24 979,
1938 01:56:54.939409 TX Bit6 (971~998) 28 984, Bit14 (969~992) 24 980,
1939 01:56:54.939461 TX Bit7 (974~998) 25 986, Bit15 (971~994) 24 982,
1940 01:56:54.939514
1941 01:56:54.939566 Write Rank1 MR14 =0x1a
1942 01:56:54.939618
1943 01:56:54.939669 CH=0, VrefRange= 0, VrefLevel = 26
1944 01:56:54.939721 TX Bit0 (977~1001) 25 989, Bit8 (968~991) 24 979,
1945 01:56:54.939774 TX Bit1 (977~1000) 24 988, Bit9 (969~992) 24 980,
1946 01:56:54.939826 TX Bit2 (977~1000) 24 988, Bit10 (974~997) 24 985,
1947 01:56:54.939879 TX Bit3 (969~995) 27 982, Bit11 (968~991) 24 979,
1948 01:56:54.939931 TX Bit4 (976~1000) 25 988, Bit12 (969~992) 24 980,
1949 01:56:54.939983 TX Bit5 (971~994) 24 982, Bit13 (968~991) 24 979,
1950 01:56:54.940036 TX Bit6 (971~998) 28 984, Bit14 (969~992) 24 980,
1951 01:56:54.940089 TX Bit7 (974~998) 25 986, Bit15 (971~994) 24 982,
1952 01:56:54.940140
1953 01:56:54.940191 Write Rank1 MR14 =0x1c
1954 01:56:54.940243
1955 01:56:54.940295 CH=0, VrefRange= 0, VrefLevel = 28
1956 01:56:54.940347 TX Bit0 (977~1001) 25 989, Bit8 (968~991) 24 979,
1957 01:56:54.940400 TX Bit1 (977~1000) 24 988, Bit9 (969~992) 24 980,
1958 01:56:54.940452 TX Bit2 (977~1000) 24 988, Bit10 (974~997) 24 985,
1959 01:56:54.940505 TX Bit3 (969~995) 27 982, Bit11 (968~991) 24 979,
1960 01:56:54.940557 TX Bit4 (976~1000) 25 988, Bit12 (969~992) 24 980,
1961 01:56:54.940610 TX Bit5 (971~994) 24 982, Bit13 (968~991) 24 979,
1962 01:56:54.940663 TX Bit6 (971~998) 28 984, Bit14 (969~992) 24 980,
1963 01:56:54.940715 TX Bit7 (974~998) 25 986, Bit15 (971~994) 24 982,
1964 01:56:54.940768
1965 01:56:54.940820 Write Rank1 MR14 =0x1e
1966 01:56:54.940871
1967 01:56:54.940923 CH=0, VrefRange= 0, VrefLevel = 30
1968 01:56:54.940976 TX Bit0 (977~1001) 25 989, Bit8 (968~991) 24 979,
1969 01:56:54.941028 TX Bit1 (977~1000) 24 988, Bit9 (969~992) 24 980,
1970 01:56:54.941080 TX Bit2 (977~1000) 24 988, Bit10 (974~997) 24 985,
1971 01:56:54.941133 TX Bit3 (969~995) 27 982, Bit11 (968~991) 24 979,
1972 01:56:54.941377 TX Bit4 (976~1000) 25 988, Bit12 (969~992) 24 980,
1973 01:56:55.093754 TX Bit5 (971~994) 24 982, Bit13 (968~991) 24 979,
1974 01:56:55.094274 TX Bit6 (971~998) 28 984, Bit14 (969~992) 24 980,
1975 01:56:55.094718 TX Bit7 (974~998) 25 986, Bit15 (971~994) 24 982,
1976 01:56:55.095206
1977 01:56:55.095652 Write Rank1 MR14 =0x20
1978 01:56:55.096103
1979 01:56:55.096444 CH=0, VrefRange= 0, VrefLevel = 32
1980 01:56:55.096736 TX Bit0 (977~1001) 25 989, Bit8 (968~991) 24 979,
1981 01:56:55.097023 TX Bit1 (977~1000) 24 988, Bit9 (969~992) 24 980,
1982 01:56:55.097335 TX Bit2 (977~1000) 24 988, Bit10 (974~997) 24 985,
1983 01:56:55.097619 TX Bit3 (969~995) 27 982, Bit11 (968~991) 24 979,
1984 01:56:55.097899 TX Bit4 (976~1000) 25 988, Bit12 (969~992) 24 980,
1985 01:56:55.098176 TX Bit5 (971~994) 24 982, Bit13 (968~991) 24 979,
1986 01:56:55.098452 TX Bit6 (971~998) 28 984, Bit14 (969~992) 24 980,
1987 01:56:55.098751 TX Bit7 (974~998) 25 986, Bit15 (971~994) 24 982,
1988 01:56:55.099359
1989 01:56:55.099820
1990 01:56:55.100117 TX Vref found, early break! 368< 374
1991 01:56:55.100406 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =762/100 ps
1992 01:56:55.100683 u1DelayCellOfst[0]=8 cells (7 PI)
1993 01:56:55.100962 u1DelayCellOfst[1]=7 cells (6 PI)
1994 01:56:55.101234 u1DelayCellOfst[2]=7 cells (6 PI)
1995 01:56:55.101551 u1DelayCellOfst[3]=0 cells (0 PI)
1996 01:56:55.101986 u1DelayCellOfst[4]=7 cells (6 PI)
1997 01:56:55.102280 u1DelayCellOfst[5]=0 cells (0 PI)
1998 01:56:55.102659 u1DelayCellOfst[6]=2 cells (2 PI)
1999 01:56:55.102944 u1DelayCellOfst[7]=5 cells (4 PI)
2000 01:56:55.103220 Byte0, DQ PI dly=982, DQM PI dly= 985
2001 01:56:55.103492 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 22)
2002 01:56:55.103766
2003 01:56:55.104038 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 22)
2004 01:56:55.104316
2005 01:56:55.104631 u1DelayCellOfst[8]=0 cells (0 PI)
2006 01:56:55.104902 u1DelayCellOfst[9]=1 cells (1 PI)
2007 01:56:55.105176 u1DelayCellOfst[10]=7 cells (6 PI)
2008 01:56:55.105495 u1DelayCellOfst[11]=0 cells (0 PI)
2009 01:56:55.105769 u1DelayCellOfst[12]=1 cells (1 PI)
2010 01:56:55.106038 u1DelayCellOfst[13]=0 cells (0 PI)
2011 01:56:55.106312 u1DelayCellOfst[14]=1 cells (1 PI)
2012 01:56:55.106584 u1DelayCellOfst[15]=3 cells (3 PI)
2013 01:56:55.106855 Byte1, DQ PI dly=979, DQM PI dly= 982
2014 01:56:55.107130 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 19)
2015 01:56:55.107639
2016 01:56:55.108162 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 19)
2017 01:56:55.108472
2018 01:56:55.108756 Write Rank1 MR14 =0x16
2019 01:56:55.109364
2020 01:56:55.109834 Final TX Range 0 Vref 22
2021 01:56:55.110135
2022 01:56:55.110416 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
2023 01:56:55.110699
2024 01:56:55.110974 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
2025 01:56:55.111252 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2026 01:56:55.111528 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2027 01:56:55.111817 Write Rank1 MR3 =0xb0
2028 01:56:55.112322 DramC Write-DBI on
2029 01:56:55.112867 ==
2030 01:56:55.113351 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2031 01:56:55.113655 fsp= 1, odt_onoff= 1, Byte mode= 0
2032 01:56:55.113938 ==
2033 01:56:55.114215 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
2034 01:56:55.114491
2035 01:56:55.114764 Begin, DQ Scan Range 702~766
2036 01:56:55.115135
2037 01:56:55.115687
2038 01:56:55.116105 TX Vref Scan disable
2039 01:56:55.116393 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
2040 01:56:55.116679 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
2041 01:56:55.116960 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
2042 01:56:55.117238 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
2043 01:56:55.117570 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
2044 01:56:55.117846 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
2045 01:56:55.118046 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
2046 01:56:55.118245 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
2047 01:56:55.118444 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
2048 01:56:55.118640 711 |2 6 7|[0] xxxxxxxx oooooooo [MSB]
2049 01:56:55.118836 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
2050 01:56:55.119033 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
2051 01:56:55.119231 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
2052 01:56:55.119429 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
2053 01:56:55.119627 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
2054 01:56:55.119824 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
2055 01:56:55.120142 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
2056 01:56:55.120549 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
2057 01:56:55.120802 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
2058 01:56:55.121008 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
2059 01:56:55.121210 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
2060 01:56:55.121542 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
2061 01:56:55.121753 744 |2 6 40|[0] xxxxxxxx xxxxxxxx [MSB]
2062 01:56:55.121953 Byte0, DQ PI dly=730, DQM PI dly= 730
2063 01:56:55.122149 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 26)
2064 01:56:55.122383
2065 01:56:55.122782 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 26)
2066 01:56:55.123089
2067 01:56:55.123321 Byte1, DQ PI dly=723, DQM PI dly= 723
2068 01:56:55.123487 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 19)
2069 01:56:55.123642
2070 01:56:55.123791 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 19)
2071 01:56:55.123942
2072 01:56:55.124090 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
2073 01:56:55.124242 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2074 01:56:55.124391 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2075 01:56:55.124541 Write Rank1 MR3 =0x30
2076 01:56:55.124690 DramC Write-DBI off
2077 01:56:55.124838
2078 01:56:55.124998 [DATLAT]
2079 01:56:55.125314 Freq=1600, CH0 RK1, use_rxtx_scan=0
2080 01:56:55.125627
2081 01:56:55.125959 DATLAT Default: 0x10
2082 01:56:55.126252 7, 0xFFFF, sum=0
2083 01:56:55.126490 8, 0xFFFF, sum=0
2084 01:56:55.126677 9, 0xFFFF, sum=0
2085 01:56:55.126835 10, 0xFFFF, sum=0
2086 01:56:55.126990 11, 0xFFFF, sum=0
2087 01:56:55.127141 12, 0xFFFF, sum=0
2088 01:56:55.127293 13, 0xFFFF, sum=0
2089 01:56:55.127444 14, 0x0, sum=1
2090 01:56:55.127595 15, 0x0, sum=2
2091 01:56:55.127746 16, 0x0, sum=3
2092 01:56:55.127887 17, 0x0, sum=4
2093 01:56:55.128008 pattern=2 first_step=14 total pass=5 best_step=16
2094 01:56:55.128126 ==
2095 01:56:55.128509 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2096 01:56:55.128644 fsp= 1, odt_onoff= 1, Byte mode= 0
2097 01:56:55.128767 ==
2098 01:56:55.128888 Start DQ dly to find pass range UseTestEngine =1
2099 01:56:55.129008 x-axis: bit #, y-axis: DQ dly (-127~63)
2100 01:56:55.129128 RX Vref Scan = 0
2101 01:56:55.129245 -26, [0] xxxxxxxx xxxxxxxx [MSB]
2102 01:56:55.129395 -25, [0] xxxxxxxx xxxxxxxx [MSB]
2103 01:56:55.129517 -24, [0] xxxxxxxx xxxxxxxx [MSB]
2104 01:56:55.129639 -23, [0] xxxxxxxx xxxxxxxx [MSB]
2105 01:56:55.129759 -22, [0] xxxxxxxx xxxxxxxx [MSB]
2106 01:56:55.129879 -21, [0] xxxxxxxx xxxxxxxx [MSB]
2107 01:56:55.129999 -20, [0] xxxxxxxx xxxxxxxx [MSB]
2108 01:56:55.130119 -19, [0] xxxxxxxx xxxxxxxx [MSB]
2109 01:56:55.130237 -18, [0] xxxxxxxx xxxxxxxx [MSB]
2110 01:56:55.130357 -17, [0] xxxxxxxx xxxxxxxx [MSB]
2111 01:56:55.130579 -16, [0] xxxxxxxx xxxxxxxx [MSB]
2112 01:56:55.130826 -15, [0] xxxxxxxx xxxxxxxx [MSB]
2113 01:56:55.130998 -14, [0] xxxxxxxx xxxxxxxx [MSB]
2114 01:56:55.131124 -13, [0] xxxxxxxx xxxxxxxx [MSB]
2115 01:56:55.131246 -12, [0] xxxxxxxx xxxxxxxx [MSB]
2116 01:56:55.131417 -11, [0] xxxxxxxx xxxxxxxx [MSB]
2117 01:56:55.131698 -10, [0] xxxxxxxx xxxxxxxx [MSB]
2118 01:56:55.131906 -9, [0] xxxxxxxx xxxxxxxx [MSB]
2119 01:56:55.132038 -8, [0] xxxxxxxx xxxxxxxx [MSB]
2120 01:56:55.132163 -7, [0] xxxxxxxx xxxxxxxx [MSB]
2121 01:56:55.132287 -6, [0] xxxxxxxx xxxxxxxx [MSB]
2122 01:56:55.132410 -5, [0] xxxxxxxx xxxxxxxx [MSB]
2123 01:56:55.132565 -4, [0] xxxxxxxx xxxxxxxx [MSB]
2124 01:56:55.132896 -3, [0] xxxxxxxx xxxxxxxx [MSB]
2125 01:56:55.133094 -2, [0] xxxoxxxx xxxxxxxx [MSB]
2126 01:56:55.133282 -1, [0] xxxoxxxx xxxxxoxx [MSB]
2127 01:56:55.133399 0, [0] xxxoxxxx oxxxxoxx [MSB]
2128 01:56:55.133511 1, [0] xxxoxoxx oxxoooox [MSB]
2129 01:56:55.133614 2, [0] xxxoxooo ooxoooox [MSB]
2130 01:56:55.133717 3, [0] xxxoxooo ooxooooo [MSB]
2131 01:56:55.133819 4, [0] xxxoxooo ooxooooo [MSB]
2132 01:56:55.133921 5, [0] xxxooooo ooxooooo [MSB]
2133 01:56:55.134021 6, [0] xxxooooo oooooooo [MSB]
2134 01:56:55.134121 7, [0] xooooooo oooooooo [MSB]
2135 01:56:55.134221 8, [0] xooooooo oooooooo [MSB]
2136 01:56:55.134322 34, [0] oooxoooo oooxoooo [MSB]
2137 01:56:55.134422 35, [0] oooxoxoo oooxoxoo [MSB]
2138 01:56:55.134523 36, [0] oooxoxxo oooxoxoo [MSB]
2139 01:56:55.134624 37, [0] oooxoxxx xooxxxxo [MSB]
2140 01:56:55.134725 38, [0] oooxoxxx xooxxxxo [MSB]
2141 01:56:55.134826 39, [0] oooxoxxx xxoxxxxx [MSB]
2142 01:56:55.134933 40, [0] oooxoxxx xxoxxxxx [MSB]
2143 01:56:55.135155 41, [0] oooxxxxx xxoxxxxx [MSB]
2144 01:56:55.135376 42, [0] oooxxxxx xxxxxxxx [MSB]
2145 01:56:55.135567 43, [0] oxxxxxxx xxxxxxxx [MSB]
2146 01:56:55.135728 44, [0] xxxxxxxx xxxxxxxx [MSB]
2147 01:56:55.135889 iDelay=44, Bit 0, Center 26 (9 ~ 43) 35
2148 01:56:55.136045 iDelay=44, Bit 1, Center 24 (7 ~ 42) 36
2149 01:56:55.136197 iDelay=44, Bit 2, Center 24 (7 ~ 42) 36
2150 01:56:55.136350 iDelay=44, Bit 3, Center 15 (-2 ~ 33) 36
2151 01:56:55.136503 iDelay=44, Bit 4, Center 22 (5 ~ 40) 36
2152 01:56:55.136660 iDelay=44, Bit 5, Center 17 (1 ~ 34) 34
2153 01:56:55.136813 iDelay=44, Bit 6, Center 18 (2 ~ 35) 34
2154 01:56:55.136965 iDelay=44, Bit 7, Center 19 (2 ~ 36) 35
2155 01:56:55.137117 iDelay=44, Bit 8, Center 18 (0 ~ 36) 37
2156 01:56:55.137287 iDelay=44, Bit 9, Center 20 (2 ~ 38) 37
2157 01:56:55.137444 iDelay=44, Bit 10, Center 23 (6 ~ 41) 36
2158 01:56:55.137603 iDelay=44, Bit 11, Center 17 (1 ~ 33) 33
2159 01:56:55.137708 iDelay=44, Bit 12, Center 18 (1 ~ 36) 36
2160 01:56:55.137815 iDelay=44, Bit 13, Center 16 (-1 ~ 34) 36
2161 01:56:55.137904 iDelay=44, Bit 14, Center 18 (1 ~ 36) 36
2162 01:56:55.137989 iDelay=44, Bit 15, Center 20 (3 ~ 38) 36
2163 01:56:55.138074 ==
2164 01:56:55.138160 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2165 01:56:55.138246 fsp= 1, odt_onoff= 1, Byte mode= 0
2166 01:56:55.138331 ==
2167 01:56:55.138415 DQS Delay:
2168 01:56:55.138500 DQS0 = 0, DQS1 = 0
2169 01:56:55.138592 DQM Delay:
2170 01:56:55.138732 DQM0 = 20, DQM1 = 18
2171 01:56:55.138949 DQ Delay:
2172 01:56:55.139094 DQ0 =26, DQ1 =24, DQ2 =24, DQ3 =15
2173 01:56:55.139193 DQ4 =22, DQ5 =17, DQ6 =18, DQ7 =19
2174 01:56:55.139295 DQ8 =18, DQ9 =20, DQ10 =23, DQ11 =17
2175 01:56:55.139430 DQ12 =18, DQ13 =16, DQ14 =18, DQ15 =20
2176 01:56:55.139561
2177 01:56:55.139694
2178 01:56:55.139843
2179 01:56:55.139996 [DramC_TX_OE_Calibration] TA2
2180 01:56:55.140131 Original DQ_B0 (3 6) =30, OEN = 27
2181 01:56:55.140265 Original DQ_B1 (3 6) =30, OEN = 27
2182 01:56:55.140398 23, 0x0, End_B0=23 End_B1=23
2183 01:56:55.140533 24, 0x0, End_B0=24 End_B1=24
2184 01:56:55.140667 25, 0x0, End_B0=25 End_B1=25
2185 01:56:55.140800 26, 0x0, End_B0=26 End_B1=26
2186 01:56:55.140934 27, 0x0, End_B0=27 End_B1=27
2187 01:56:55.141069 28, 0x0, End_B0=28 End_B1=28
2188 01:56:55.141203 29, 0x0, End_B0=29 End_B1=29
2189 01:56:55.141349 30, 0x0, End_B0=30 End_B1=30
2190 01:56:55.141484 31, 0xFFFF, End_B0=30 End_B1=30
2191 01:56:55.141620 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
2192 01:56:55.141753 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
2193 01:56:55.141883
2194 01:56:55.142013
2195 01:56:55.142143 Write Rank1 MR23 =0x3f
2196 01:56:55.142273 [DQSOSC]
2197 01:56:55.142406 [DQSOSCAuto] RK1, (LSB)MR18= 0x79, (MSB)MR19= 0x3, tDQSOscB0 = 354 ps tDQSOscB1 = 0 ps
2198 01:56:55.142540 CH0_RK1: MR19=0x3, MR18=0x79, DQSOSC=354, MR23=63, INC=19, DEC=29
2199 01:56:55.142671 Write Rank1 MR23 =0x3f
2200 01:56:55.142808 [DQSOSC]
2201 01:56:55.142924 [DQSOSCAuto] RK1, (LSB)MR18= 0x7a, (MSB)MR19= 0x3, tDQSOscB0 = 353 ps tDQSOscB1 = 0 ps
2202 01:56:55.143039 CH0 RK1: MR19=3, MR18=7A
2203 01:56:55.143153 [RxdqsGatingPostProcess] freq 1600
2204 01:56:55.143270 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
2205 01:56:55.143384 Rank: 0
2206 01:56:55.143499 best DQS0 dly(2T, 0.5T) = (2, 5)
2207 01:56:55.143614 best DQS1 dly(2T, 0.5T) = (2, 5)
2208 01:56:55.143728 best DQS0 P1 dly(2T, 0.5T) = (3, 1)
2209 01:56:55.143843 best DQS1 P1 dly(2T, 0.5T) = (3, 1)
2210 01:56:55.143957 Rank: 1
2211 01:56:55.144073 best DQS0 dly(2T, 0.5T) = (2, 6)
2212 01:56:55.144187 best DQS1 dly(2T, 0.5T) = (2, 6)
2213 01:56:55.144302 best DQS0 P1 dly(2T, 0.5T) = (3, 2)
2214 01:56:55.144417 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
2215 01:56:55.144532 TX_dly_DQSgated check: min 2 max 3, ChangeDQSINCTL=-1
2216 01:56:55.144649 DQSINCTL=5, RANKINCTL=3, u4XRTR2R=9
2217 01:56:55.144979 [DualRankRxdatlatCal] RK0: 16, RK1: 16, Final_Datlat 16
2218 01:56:55.145100 Write Rank0 MR13 =0x59
2219 01:56:55.145215 ==
2220 01:56:55.145326 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2221 01:56:55.145405 fsp= 1, odt_onoff= 1, Byte mode= 0
2222 01:56:55.145480 ==
2223 01:56:55.145555 === u2Vref_new: 0x56 --> 0x3a
2224 01:56:55.145630 === u2Vref_new: 0x58 --> 0x58
2225 01:56:55.145703 === u2Vref_new: 0x5a --> 0x5a
2226 01:56:55.145789 === u2Vref_new: 0x5c --> 0x78
2227 01:56:55.145864 === u2Vref_new: 0x5e --> 0x7a
2228 01:56:55.145938 === u2Vref_new: 0x60 --> 0x90
2229 01:56:55.146013 [CA 0] Center 36 (9~63) winsize 55
2230 01:56:55.146088 [CA 1] Center 35 (7~63) winsize 57
2231 01:56:55.146162 [CA 2] Center 32 (3~62) winsize 60
2232 01:56:55.146236 [CA 3] Center 32 (3~62) winsize 60
2233 01:56:55.146310 [CA 4] Center 33 (4~63) winsize 60
2234 01:56:55.146385 [CA 5] Center 25 (-2~53) winsize 56
2235 01:56:55.146459
2236 01:56:55.146533 [CATrainingPosCal] consider 1 rank data
2237 01:56:55.146608 u2DelayCellTimex100 = 762/100 ps
2238 01:56:55.146682 CA0 delay=36 (9~63),Diff = 11 PI (14 cell)
2239 01:56:55.146756 CA1 delay=35 (7~63),Diff = 10 PI (12 cell)
2240 01:56:55.146830 CA2 delay=32 (3~62),Diff = 7 PI (8 cell)
2241 01:56:55.146904 CA3 delay=32 (3~62),Diff = 7 PI (8 cell)
2242 01:56:55.146978 CA4 delay=33 (4~63),Diff = 8 PI (10 cell)
2243 01:56:55.147052 CA5 delay=25 (-2~53),Diff = 0 PI (0 cell)
2244 01:56:55.147125
2245 01:56:55.147200 CA PerBit enable=1, Macro0, CA PI delay=25
2246 01:56:55.147274 === u2Vref_new: 0x56 --> 0x3a
2247 01:56:55.147349
2248 01:56:55.147422 Vref(ca) range 1: 22
2249 01:56:55.147496
2250 01:56:55.147569 CS Dly= 11 (42-0-32)
2251 01:56:55.147648 Write Rank0 MR13 =0xd8
2252 01:56:55.147785 Write Rank0 MR13 =0xd8
2253 01:56:55.147888 Write Rank0 MR12 =0x56
2254 01:56:55.148007 Write Rank1 MR13 =0x59
2255 01:56:55.148106 ==
2256 01:56:55.148177 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
2257 01:56:55.148244 fsp= 1, odt_onoff= 1, Byte mode= 0
2258 01:56:55.148312 ==
2259 01:56:55.148377 === u2Vref_new: 0x56 --> 0x3a
2260 01:56:55.148444 === u2Vref_new: 0x58 --> 0x58
2261 01:56:55.148511 === u2Vref_new: 0x5a --> 0x5a
2262 01:56:55.148578 === u2Vref_new: 0x5c --> 0x78
2263 01:56:55.148643 === u2Vref_new: 0x5e --> 0x7a
2264 01:56:55.148709 === u2Vref_new: 0x60 --> 0x90
2265 01:56:55.148776 [CA 0] Center 36 (10~63) winsize 54
2266 01:56:55.148842 [CA 1] Center 35 (8~63) winsize 56
2267 01:56:55.148908 [CA 2] Center 33 (3~63) winsize 61
2268 01:56:55.148974 [CA 3] Center 33 (3~63) winsize 61
2269 01:56:55.149040 [CA 4] Center 33 (4~63) winsize 60
2270 01:56:55.149105 [CA 5] Center 25 (-2~53) winsize 56
2271 01:56:55.149170
2272 01:56:55.149236 [CATrainingPosCal] consider 2 rank data
2273 01:56:55.149314 u2DelayCellTimex100 = 762/100 ps
2274 01:56:55.149381 CA0 delay=36 (10~63),Diff = 11 PI (14 cell)
2275 01:56:55.149448 CA1 delay=35 (8~63),Diff = 10 PI (12 cell)
2276 01:56:55.149514 CA2 delay=32 (3~62),Diff = 7 PI (8 cell)
2277 01:56:55.149581 CA3 delay=32 (3~62),Diff = 7 PI (8 cell)
2278 01:56:55.149647 CA4 delay=33 (4~63),Diff = 8 PI (10 cell)
2279 01:56:55.149713 CA5 delay=25 (-2~53),Diff = 0 PI (0 cell)
2280 01:56:55.149779
2281 01:56:55.149844 CA PerBit enable=1, Macro0, CA PI delay=25
2282 01:56:55.149910 === u2Vref_new: 0x56 --> 0x3a
2283 01:56:55.149977
2284 01:56:55.150043 Vref(ca) range 1: 22
2285 01:56:55.150109
2286 01:56:55.150174 CS Dly= 11 (42-0-32)
2287 01:56:55.150240 Write Rank1 MR13 =0xd8
2288 01:56:55.150306 Write Rank1 MR13 =0xd8
2289 01:56:55.150371 Write Rank1 MR12 =0x56
2290 01:56:55.150437 [RankSwap] Rank num 2, (Multi 1), Rank 0
2291 01:56:55.150504 Write Rank0 MR2 =0xad
2292 01:56:55.150570 [Write Leveling]
2293 01:56:55.150637 delay byte0 byte1 byte2 byte3
2294 01:56:55.150703
2295 01:56:55.150768 10 0 0
2296 01:56:55.150835 11 0 0
2297 01:56:55.150903 12 0 0
2298 01:56:55.150969 13 0 0
2299 01:56:55.151035 14 0 0
2300 01:56:55.151102 15 0 0
2301 01:56:55.151169 16 0 0
2302 01:56:55.151235 17 0 0
2303 01:56:55.151302 18 0 0
2304 01:56:55.151369 19 0 0
2305 01:56:55.151435 20 0 0
2306 01:56:55.151501 21 0 0
2307 01:56:55.151568 22 0 0
2308 01:56:55.151634 23 0 0
2309 01:56:55.151708 24 0 0
2310 01:56:55.151775 25 0 0
2311 01:56:55.151842 26 0 0
2312 01:56:55.151909 27 0 0
2313 01:56:55.151976 28 0 0
2314 01:56:55.152043 29 0 0
2315 01:56:55.152110 30 0 0
2316 01:56:55.152177 31 0 ff
2317 01:56:55.152244 32 0 ff
2318 01:56:55.152311 33 0 ff
2319 01:56:55.152378 34 0 ff
2320 01:56:55.152444 35 0 ff
2321 01:56:55.152510 36 ff ff
2322 01:56:55.152576 37 ff ff
2323 01:56:55.152643 38 ff ff
2324 01:56:55.152710 39 ff ff
2325 01:56:55.152777 40 ff ff
2326 01:56:55.152850 41 ff ff
2327 01:56:55.152910 42 ff ff
2328 01:56:55.152970 pass bytecount = 0xff (0xff: all bytes pass)
2329 01:56:55.153030
2330 01:56:55.153089 DQS0 dly: 36
2331 01:56:55.153148 DQS1 dly: 31
2332 01:56:55.153207 Write Rank0 MR2 =0x2d
2333 01:56:55.153276 [RankSwap] Rank num 2, (Multi 1), Rank 0
2334 01:56:55.153357 Write Rank0 MR1 =0xd6
2335 01:56:55.153421 [Gating]
2336 01:56:55.153481 ==
2337 01:56:55.153541 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2338 01:56:55.155729 fsp= 1, odt_onoff= 1, Byte mode= 0
2339 01:56:55.155821 ==
2340 01:56:55.159154 3 1 0 |1615 3534 |(11 11)(11 11) |(0 1)(1 1)| 0
2341 01:56:55.162493 3 1 4 |2d2d 3534 |(11 11)(11 11) |(1 0)(1 1)| 0
2342 01:56:55.169237 3 1 8 |2d2c 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
2343 01:56:55.172407 3 1 12 |2d2d 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
2344 01:56:55.176035 3 1 16 |302f 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
2345 01:56:55.182603 3 1 20 |2e2d 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
2346 01:56:55.185869 3 1 24 |3131 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
2347 01:56:55.189532 3 1 28 |303 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
2348 01:56:55.192668 3 2 0 |2d2c 201 |(11 11)(11 11) |(1 1)(1 1)| 0
2349 01:56:55.199716 3 2 4 |1a1a 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
2350 01:56:55.202759 3 2 8 |1b1a 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
2351 01:56:55.206394 3 2 12 |1817 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
2352 01:56:55.212979 3 2 16 |3c3b 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2353 01:56:55.216370 3 2 20 |3131 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
2354 01:56:55.219475 3 2 24 |3636 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2355 01:56:55.226430 3 2 28 |3635 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2356 01:56:55.230064 3 3 0 |504 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2357 01:56:55.233047 3 3 4 |3534 909 |(11 11)(11 11) |(1 1)(1 1)| 0
2358 01:56:55.236341 [Byte 0] Lead/lag falling Transition (3, 3, 4)
2359 01:56:55.242746 3 3 8 |3534 2f2e |(11 11)(11 11) |(0 1)(1 1)| 0
2360 01:56:55.245914 [Byte 1] Lead/lag falling Transition (3, 3, 8)
2361 01:56:55.249371 3 3 12 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
2362 01:56:55.255913 3 3 16 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
2363 01:56:55.259365 3 3 20 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
2364 01:56:55.262921 3 3 24 |3534 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
2365 01:56:55.269328 3 3 28 |201 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
2366 01:56:55.272942 3 4 0 |3d3d 505 |(11 11)(11 11) |(1 1)(1 1)| 0
2367 01:56:55.276593 3 4 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2368 01:56:55.279830 3 4 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2369 01:56:55.286588 3 4 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2370 01:56:55.289544 3 4 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2371 01:56:55.292918 3 4 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2372 01:56:55.299650 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2373 01:56:55.303119 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2374 01:56:55.306996 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2375 01:56:55.309979 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2376 01:56:55.316882 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2377 01:56:55.320162 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2378 01:56:55.323481 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2379 01:56:55.330288 [Byte 0] Lead/lag falling Transition (3, 5, 16)
2380 01:56:55.333419 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
2381 01:56:55.336519 [Byte 0] Lead/lag Transition tap number (2)
2382 01:56:55.340407 3 5 24 |3e3d 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
2383 01:56:55.346732 [Byte 1] Lead/lag falling Transition (3, 5, 24)
2384 01:56:55.350086 3 5 28 |909 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
2385 01:56:55.353420 [Byte 1] Lead/lag Transition tap number (2)
2386 01:56:55.356621 3 6 0 |4646 202 |(0 0)(11 11) |(0 0)(0 0)| 0
2387 01:56:55.359959 [Byte 0]First pass (3, 6, 0)
2388 01:56:55.363262 3 6 4 |4646 4646 |(0 0)(10 10) |(0 0)(0 0)| 0
2389 01:56:55.370360 3 6 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2390 01:56:55.370910 [Byte 1]First pass (3, 6, 8)
2391 01:56:55.377565 3 6 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2392 01:56:55.380066 3 6 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2393 01:56:55.383640 3 6 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2394 01:56:55.386995 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2395 01:56:55.389906 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2396 01:56:55.397086 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2397 01:56:55.400088 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2398 01:56:55.403499 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2399 01:56:55.406683 All bytes gating window > 1UI, Early break!
2400 01:56:55.407232
2401 01:56:55.409962 best DQS0 dly(2T, 0.5T, PI) = (3, 5, 20)
2402 01:56:55.410419
2403 01:56:55.413466 best DQS1 dly(2T, 0.5T, PI) = (3, 5, 28)
2404 01:56:55.414019
2405 01:56:55.416908
2406 01:56:55.417500
2407 01:56:55.419919 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 1, 20)
2408 01:56:55.420378
2409 01:56:55.423208 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 1, 28)
2410 01:56:55.423838
2411 01:56:55.424215
2412 01:56:55.426536 Write Rank0 MR1 =0x56
2413 01:56:55.426987
2414 01:56:55.430038 best RODT dly(2T, 0.5T) = (2, 2)
2415 01:56:55.430455
2416 01:56:55.433407 best RODT dly(2T, 0.5T) = (2, 2)
2417 01:56:55.433911 ==
2418 01:56:55.436781 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2419 01:56:55.439884 fsp= 1, odt_onoff= 1, Byte mode= 0
2420 01:56:55.440303 ==
2421 01:56:55.443177 Start DQ dly to find pass range UseTestEngine =0
2422 01:56:55.446846 x-axis: bit #, y-axis: DQ dly (-127~63)
2423 01:56:55.450058 RX Vref Scan = 0
2424 01:56:55.453338 -26, [0] xxxxxxxx xxxxxxxx [MSB]
2425 01:56:55.456872 -25, [0] xxxxxxxx xxxxxxxx [MSB]
2426 01:56:55.459997 -24, [0] xxxxxxxx xxxxxxxx [MSB]
2427 01:56:55.460469 -23, [0] xxxxxxxx xxxxxxxx [MSB]
2428 01:56:55.463341 -22, [0] xxxxxxxx xxxxxxxx [MSB]
2429 01:56:55.466633 -21, [0] xxxxxxxx xxxxxxxx [MSB]
2430 01:56:55.469883 -20, [0] xxxxxxxx xxxxxxxx [MSB]
2431 01:56:55.473451 -19, [0] xxxxxxxx xxxxxxxx [MSB]
2432 01:56:55.477020 -18, [0] xxxxxxxx xxxxxxxx [MSB]
2433 01:56:55.480060 -17, [0] xxxxxxxx xxxxxxxx [MSB]
2434 01:56:55.483926 -16, [0] xxxxxxxx xxxxxxxx [MSB]
2435 01:56:55.484448 -15, [0] xxxxxxxx xxxxxxxx [MSB]
2436 01:56:55.486777 -14, [0] xxxxxxxx xxxxxxxx [MSB]
2437 01:56:55.490000 -13, [0] xxxxxxxx xxxxxxxx [MSB]
2438 01:56:55.493692 -12, [0] xxxxxxxx xxxxxxxx [MSB]
2439 01:56:55.497236 -11, [0] xxxxxxxx xxxxxxxx [MSB]
2440 01:56:55.500450 -10, [0] xxxxxxxx xxxxxxxx [MSB]
2441 01:56:55.503610 -9, [0] xxxxxxxx xxxxxxxx [MSB]
2442 01:56:55.507454 -8, [0] xxxxxxxx xxxxxxxx [MSB]
2443 01:56:55.507982 -7, [0] xxxxxxxx xxxxxxxx [MSB]
2444 01:56:55.510791 -6, [0] xxxxxxxx xxxxxxxx [MSB]
2445 01:56:55.513943 -5, [0] xxxxxxxx xxxxxxxx [MSB]
2446 01:56:55.517089 -4, [0] xxxxxxxx xxxxxxxx [MSB]
2447 01:56:55.520254 -3, [0] xxxxxxxx xxxxxxxx [MSB]
2448 01:56:55.523728 -2, [0] xxxxxxxx xxxxxxxx [MSB]
2449 01:56:55.524157 -1, [0] xxxxxxxx xxxxxxxx [MSB]
2450 01:56:55.527216 0, [0] xxxoxxxx xxxxxxxx [MSB]
2451 01:56:55.530654 1, [0] xxooxxxx xxxxxxxo [MSB]
2452 01:56:55.534205 2, [0] xxooxxxo xxxxxxxo [MSB]
2453 01:56:55.537735 3, [0] xxoooxxo oooxxoxo [MSB]
2454 01:56:55.540408 4, [0] xxoooxxo oooxooxo [MSB]
2455 01:56:55.540948 5, [0] xxoooxxo oooooooo [MSB]
2456 01:56:55.544012 6, [0] xoooooxo oooooooo [MSB]
2457 01:56:55.547484 7, [0] xoooooxo oooooooo [MSB]
2458 01:56:55.551019 8, [0] xoooooxo oooooooo [MSB]
2459 01:56:55.553728 32, [0] ooxxoooo oooooooo [MSB]
2460 01:56:55.557640 33, [0] ooxxoooo ooooooox [MSB]
2461 01:56:55.558092 34, [0] ooxxoooo ooooooox [MSB]
2462 01:56:55.561033 35, [0] ooxxoooo ooxoooox [MSB]
2463 01:56:55.564175 36, [0] ooxxxooo ooxoooox [MSB]
2464 01:56:55.567610 37, [0] ooxxxoox xxxxoxxx [MSB]
2465 01:56:55.571245 38, [0] ooxxxoox xxxxoxxx [MSB]
2466 01:56:55.574668 39, [0] ooxxxoox xxxxxxxx [MSB]
2467 01:56:55.575189 40, [0] xxxxxoox xxxxxxxx [MSB]
2468 01:56:55.577415 41, [0] xxxxxxxx xxxxxxxx [MSB]
2469 01:56:55.581172 iDelay=41, Bit 0, Center 24 (9 ~ 39) 31
2470 01:56:55.584684 iDelay=41, Bit 1, Center 22 (6 ~ 39) 34
2471 01:56:55.587722 iDelay=41, Bit 2, Center 16 (1 ~ 31) 31
2472 01:56:55.590776 iDelay=41, Bit 3, Center 15 (0 ~ 31) 32
2473 01:56:55.597595 iDelay=41, Bit 4, Center 19 (3 ~ 35) 33
2474 01:56:55.600975 iDelay=41, Bit 5, Center 23 (6 ~ 40) 35
2475 01:56:55.604978 iDelay=41, Bit 6, Center 24 (9 ~ 40) 32
2476 01:56:55.607848 iDelay=41, Bit 7, Center 19 (2 ~ 36) 35
2477 01:56:55.611152 iDelay=41, Bit 8, Center 19 (3 ~ 36) 34
2478 01:56:55.614763 iDelay=41, Bit 9, Center 19 (3 ~ 36) 34
2479 01:56:55.617889 iDelay=41, Bit 10, Center 18 (3 ~ 34) 32
2480 01:56:55.621585 iDelay=41, Bit 11, Center 20 (5 ~ 36) 32
2481 01:56:55.624701 iDelay=41, Bit 12, Center 21 (4 ~ 38) 35
2482 01:56:55.627885 iDelay=41, Bit 13, Center 19 (3 ~ 36) 34
2483 01:56:55.631687 iDelay=41, Bit 14, Center 20 (5 ~ 36) 32
2484 01:56:55.634854 iDelay=41, Bit 15, Center 16 (1 ~ 32) 32
2485 01:56:55.635407 ==
2486 01:56:55.641371 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2487 01:56:55.644535 fsp= 1, odt_onoff= 1, Byte mode= 0
2488 01:56:55.644999 ==
2489 01:56:55.645403 DQS Delay:
2490 01:56:55.647946 DQS0 = 0, DQS1 = 0
2491 01:56:55.648499 DQM Delay:
2492 01:56:55.651270 DQM0 = 20, DQM1 = 19
2493 01:56:55.651733 DQ Delay:
2494 01:56:55.654582 DQ0 =24, DQ1 =22, DQ2 =16, DQ3 =15
2495 01:56:55.658588 DQ4 =19, DQ5 =23, DQ6 =24, DQ7 =19
2496 01:56:55.661433 DQ8 =19, DQ9 =19, DQ10 =18, DQ11 =20
2497 01:56:55.665205 DQ12 =21, DQ13 =19, DQ14 =20, DQ15 =16
2498 01:56:55.665793
2499 01:56:55.666143
2500 01:56:55.666452 DramC Write-DBI off
2501 01:56:55.666749 ==
2502 01:56:55.671280 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2503 01:56:55.675232 fsp= 1, odt_onoff= 1, Byte mode= 0
2504 01:56:55.675750 ==
2505 01:56:55.678605 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
2506 01:56:55.679029
2507 01:56:55.681820 Begin, DQ Scan Range 927~1183
2508 01:56:55.682241
2509 01:56:55.682570
2510 01:56:55.685199 TX Vref Scan disable
2511 01:56:55.688299 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
2512 01:56:55.691891 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
2513 01:56:55.694913 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
2514 01:56:55.698135 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
2515 01:56:55.701750 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
2516 01:56:55.704938 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
2517 01:56:55.708719 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
2518 01:56:55.711963 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
2519 01:56:55.715117 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
2520 01:56:55.718363 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
2521 01:56:55.721636 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
2522 01:56:55.727903 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
2523 01:56:55.731670 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
2524 01:56:55.735322 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
2525 01:56:55.738171 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
2526 01:56:55.742055 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
2527 01:56:55.745825 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
2528 01:56:55.748257 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
2529 01:56:55.751376 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
2530 01:56:55.754761 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
2531 01:56:55.758248 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
2532 01:56:55.761980 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
2533 01:56:55.765009 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
2534 01:56:55.768109 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
2535 01:56:55.771439 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
2536 01:56:55.774933 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
2537 01:56:55.778279 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
2538 01:56:55.781432 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
2539 01:56:55.788818 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
2540 01:56:55.791529 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
2541 01:56:55.794547 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
2542 01:56:55.798585 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
2543 01:56:55.801799 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
2544 01:56:55.804687 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
2545 01:56:55.808240 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
2546 01:56:55.811509 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
2547 01:56:55.814860 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
2548 01:56:55.818203 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
2549 01:56:55.821161 965 |3 6 5|[0] xxxxxxxx xxxxxxxo [MSB]
2550 01:56:55.824890 966 |3 6 6|[0] xxxxxxxx xxxxxxxo [MSB]
2551 01:56:55.827642 967 |3 6 7|[0] xxxxxxxx ooxxxxxo [MSB]
2552 01:56:55.831422 968 |3 6 8|[0] xxxxxxxx ooxxxxoo [MSB]
2553 01:56:55.834764 969 |3 6 9|[0] xxxxxxxx oooooxoo [MSB]
2554 01:56:55.837965 970 |3 6 10|[0] xxxxxxxx oooooooo [MSB]
2555 01:56:55.841671 971 |3 6 11|[0] xxxxxxxx oooooooo [MSB]
2556 01:56:55.844884 972 |3 6 12|[0] xxxxxxxx oooooooo [MSB]
2557 01:56:55.847996 973 |3 6 13|[0] xxxxxxxx oooooooo [MSB]
2558 01:56:55.851604 974 |3 6 14|[0] xxxxxxxx oooooooo [MSB]
2559 01:56:55.857939 975 |3 6 15|[0] xxooxxxx oooooooo [MSB]
2560 01:56:55.861428 976 |3 6 16|[0] xooooxxo oooooooo [MSB]
2561 01:56:55.864347 977 |3 6 17|[0] xoooooxo oooooooo [MSB]
2562 01:56:55.868132 989 |3 6 29|[0] oooooooo ooooooox [MSB]
2563 01:56:55.871065 990 |3 6 30|[0] oooooooo xxooooox [MSB]
2564 01:56:55.874393 991 |3 6 31|[0] oooooooo xxxxxxxx [MSB]
2565 01:56:55.878112 992 |3 6 32|[0] oooooooo xxxxxxxx [MSB]
2566 01:56:55.884653 993 |3 6 33|[0] oooooooo xxxxxxxx [MSB]
2567 01:56:55.887769 994 |3 6 34|[0] oooooooo xxxxxxxx [MSB]
2568 01:56:55.890768 995 |3 6 35|[0] oooxoooo xxxxxxxx [MSB]
2569 01:56:55.894327 996 |3 6 36|[0] oooxoooo xxxxxxxx [MSB]
2570 01:56:55.897413 997 |3 6 37|[0] ooxxoooo xxxxxxxx [MSB]
2571 01:56:55.901388 998 |3 6 38|[0] ooxxooox xxxxxxxx [MSB]
2572 01:56:55.904460 999 |3 6 39|[0] xxxxxxxx xxxxxxxx [MSB]
2573 01:56:55.908079 Byte0, DQ PI dly=986, DQM PI dly= 986
2574 01:56:55.911007 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 26)
2575 01:56:55.911570
2576 01:56:55.917877 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 26)
2577 01:56:55.918457
2578 01:56:55.920936 Byte1, DQ PI dly=978, DQM PI dly= 978
2579 01:56:55.924785 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 18)
2580 01:56:55.925378
2581 01:56:55.927433 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 18)
2582 01:56:55.927900
2583 01:56:55.928268 ==
2584 01:56:55.934039 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2585 01:56:55.938908 fsp= 1, odt_onoff= 1, Byte mode= 0
2586 01:56:55.939562 ==
2587 01:56:55.941038 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
2588 01:56:55.941499
2589 01:56:55.944418 Begin, DQ Scan Range 954~1018
2590 01:56:55.947957 Write Rank0 MR14 =0x0
2591 01:56:55.954970
2592 01:56:55.955433 CH=1, VrefRange= 0, VrefLevel = 0
2593 01:56:55.961669 TX Bit0 (979~998) 20 988, Bit8 (969~985) 17 977,
2594 01:56:55.965386 TX Bit1 (978~996) 19 987, Bit9 (969~985) 17 977,
2595 01:56:55.971925 TX Bit2 (977~992) 16 984, Bit10 (970~985) 16 977,
2596 01:56:55.975611 TX Bit3 (975~990) 16 982, Bit11 (972~988) 17 980,
2597 01:56:55.978720 TX Bit4 (977~993) 17 985, Bit12 (970~988) 19 979,
2598 01:56:55.985664 TX Bit5 (978~997) 20 987, Bit13 (972~988) 17 980,
2599 01:56:55.989174 TX Bit6 (980~997) 18 988, Bit14 (970~986) 17 978,
2600 01:56:55.991810 TX Bit7 (978~992) 15 985, Bit15 (967~985) 19 976,
2601 01:56:55.992235
2602 01:56:55.995511 Write Rank0 MR14 =0x2
2603 01:56:56.004139
2604 01:56:56.004644 CH=1, VrefRange= 0, VrefLevel = 2
2605 01:56:56.010619 TX Bit0 (979~998) 20 988, Bit8 (968~985) 18 976,
2606 01:56:56.014186 TX Bit1 (977~997) 21 987, Bit9 (968~985) 18 976,
2607 01:56:56.020881 TX Bit2 (977~992) 16 984, Bit10 (970~985) 16 977,
2608 01:56:56.023838 TX Bit3 (975~990) 16 982, Bit11 (971~988) 18 979,
2609 01:56:56.027254 TX Bit4 (978~994) 17 986, Bit12 (970~989) 20 979,
2610 01:56:56.033781 TX Bit5 (978~997) 20 987, Bit13 (972~988) 17 980,
2611 01:56:56.037233 TX Bit6 (979~997) 19 988, Bit14 (970~986) 17 978,
2612 01:56:56.040548 TX Bit7 (977~992) 16 984, Bit15 (967~985) 19 976,
2613 01:56:56.040971
2614 01:56:56.043803 Write Rank0 MR14 =0x4
2615 01:56:56.052897
2616 01:56:56.053449 CH=1, VrefRange= 0, VrefLevel = 4
2617 01:56:56.059763 TX Bit0 (978~998) 21 988, Bit8 (968~985) 18 976,
2618 01:56:56.062829 TX Bit1 (977~997) 21 987, Bit9 (969~986) 18 977,
2619 01:56:56.069480 TX Bit2 (977~993) 17 985, Bit10 (970~986) 17 978,
2620 01:56:56.072749 TX Bit3 (975~991) 17 983, Bit11 (970~989) 20 979,
2621 01:56:56.076167 TX Bit4 (977~995) 19 986, Bit12 (970~989) 20 979,
2622 01:56:56.082889 TX Bit5 (978~998) 21 988, Bit13 (971~989) 19 980,
2623 01:56:56.086289 TX Bit6 (979~998) 20 988, Bit14 (970~987) 18 978,
2624 01:56:56.089411 TX Bit7 (977~993) 17 985, Bit15 (966~985) 20 975,
2625 01:56:56.089918
2626 01:56:56.092415 Write Rank0 MR14 =0x6
2627 01:56:56.101791
2628 01:56:56.102313 CH=1, VrefRange= 0, VrefLevel = 6
2629 01:56:56.108396 TX Bit0 (978~998) 21 988, Bit8 (968~986) 19 977,
2630 01:56:56.112014 TX Bit1 (977~997) 21 987, Bit9 (968~986) 19 977,
2631 01:56:56.118575 TX Bit2 (976~993) 18 984, Bit10 (970~987) 18 978,
2632 01:56:56.122272 TX Bit3 (974~991) 18 982, Bit11 (970~990) 21 980,
2633 01:56:56.125291 TX Bit4 (977~995) 19 986, Bit12 (970~990) 21 980,
2634 01:56:56.131920 TX Bit5 (977~998) 22 987, Bit13 (971~990) 20 980,
2635 01:56:56.135586 TX Bit6 (979~998) 20 988, Bit14 (970~988) 19 979,
2636 01:56:56.138370 TX Bit7 (977~993) 17 985, Bit15 (966~986) 21 976,
2637 01:56:56.138852
2638 01:56:56.142027 Write Rank0 MR14 =0x8
2639 01:56:56.150823
2640 01:56:56.151384 CH=1, VrefRange= 0, VrefLevel = 8
2641 01:56:56.157433 TX Bit0 (978~998) 21 988, Bit8 (968~987) 20 977,
2642 01:56:56.160862 TX Bit1 (977~998) 22 987, Bit9 (968~987) 20 977,
2643 01:56:56.167054 TX Bit2 (976~994) 19 985, Bit10 (969~987) 19 978,
2644 01:56:56.170910 TX Bit3 (974~992) 19 983, Bit11 (970~990) 21 980,
2645 01:56:56.174167 TX Bit4 (977~996) 20 986, Bit12 (969~990) 22 979,
2646 01:56:56.180501 TX Bit5 (978~998) 21 988, Bit13 (971~990) 20 980,
2647 01:56:56.184488 TX Bit6 (979~998) 20 988, Bit14 (969~988) 20 978,
2648 01:56:56.187277 TX Bit7 (977~994) 18 985, Bit15 (966~986) 21 976,
2649 01:56:56.187800
2650 01:56:56.190602 Write Rank0 MR14 =0xa
2651 01:56:56.199849
2652 01:56:56.203152 CH=1, VrefRange= 0, VrefLevel = 10
2653 01:56:56.206556 TX Bit0 (978~999) 22 988, Bit8 (968~988) 21 978,
2654 01:56:56.210055 TX Bit1 (977~997) 21 987, Bit9 (968~987) 20 977,
2655 01:56:56.216790 TX Bit2 (976~994) 19 985, Bit10 (969~988) 20 978,
2656 01:56:56.219879 TX Bit3 (974~992) 19 983, Bit11 (970~991) 22 980,
2657 01:56:56.223235 TX Bit4 (977~997) 21 987, Bit12 (969~991) 23 980,
2658 01:56:56.230148 TX Bit5 (977~999) 23 988, Bit13 (970~991) 22 980,
2659 01:56:56.232927 TX Bit6 (978~999) 22 988, Bit14 (969~989) 21 979,
2660 01:56:56.236498 TX Bit7 (977~995) 19 986, Bit15 (966~987) 22 976,
2661 01:56:56.237064
2662 01:56:56.239500 Write Rank0 MR14 =0xc
2663 01:56:56.249236
2664 01:56:56.252447 CH=1, VrefRange= 0, VrefLevel = 12
2665 01:56:56.256323 TX Bit0 (978~1000) 23 989, Bit8 (967~988) 22 977,
2666 01:56:56.258715 TX Bit1 (977~998) 22 987, Bit9 (968~988) 21 978,
2667 01:56:56.265720 TX Bit2 (976~995) 20 985, Bit10 (968~989) 22 978,
2668 01:56:56.268849 TX Bit3 (974~993) 20 983, Bit11 (970~991) 22 980,
2669 01:56:56.272259 TX Bit4 (976~997) 22 986, Bit12 (969~991) 23 980,
2670 01:56:56.279258 TX Bit5 (977~999) 23 988, Bit13 (970~991) 22 980,
2671 01:56:56.281989 TX Bit6 (978~999) 22 988, Bit14 (969~990) 22 979,
2672 01:56:56.285450 TX Bit7 (976~996) 21 986, Bit15 (966~987) 22 976,
2673 01:56:56.285874
2674 01:56:56.288671 Write Rank0 MR14 =0xe
2675 01:56:56.298346
2676 01:56:56.301625 CH=1, VrefRange= 0, VrefLevel = 14
2677 01:56:56.305314 TX Bit0 (978~1000) 23 989, Bit8 (968~989) 22 978,
2678 01:56:56.308438 TX Bit1 (976~998) 23 987, Bit9 (968~989) 22 978,
2679 01:56:56.315060 TX Bit2 (975~996) 22 985, Bit10 (968~990) 23 979,
2680 01:56:56.318666 TX Bit3 (973~993) 21 983, Bit11 (969~991) 23 980,
2681 01:56:56.321241 TX Bit4 (976~997) 22 986, Bit12 (969~991) 23 980,
2682 01:56:56.328401 TX Bit5 (977~999) 23 988, Bit13 (970~991) 22 980,
2683 01:56:56.332114 TX Bit6 (978~999) 22 988, Bit14 (969~990) 22 979,
2684 01:56:56.334983 TX Bit7 (976~996) 21 986, Bit15 (965~988) 24 976,
2685 01:56:56.338212
2686 01:56:56.338647 Write Rank0 MR14 =0x10
2687 01:56:56.347999
2688 01:56:56.350822 CH=1, VrefRange= 0, VrefLevel = 16
2689 01:56:56.354273 TX Bit0 (978~1000) 23 989, Bit8 (967~990) 24 978,
2690 01:56:56.357658 TX Bit1 (977~999) 23 988, Bit9 (967~989) 23 978,
2691 01:56:56.364524 TX Bit2 (975~996) 22 985, Bit10 (968~990) 23 979,
2692 01:56:56.367962 TX Bit3 (972~993) 22 982, Bit11 (969~991) 23 980,
2693 01:56:56.370860 TX Bit4 (976~998) 23 987, Bit12 (969~991) 23 980,
2694 01:56:56.377580 TX Bit5 (977~1000) 24 988, Bit13 (969~991) 23 980,
2695 01:56:56.381212 TX Bit6 (978~1000) 23 989, Bit14 (969~990) 22 979,
2696 01:56:56.387638 TX Bit7 (976~997) 22 986, Bit15 (964~988) 25 976,
2697 01:56:56.388057
2698 01:56:56.388388 Write Rank0 MR14 =0x12
2699 01:56:56.397509
2700 01:56:56.400811 CH=1, VrefRange= 0, VrefLevel = 18
2701 01:56:56.404909 TX Bit0 (977~1001) 25 989, Bit8 (967~990) 24 978,
2702 01:56:56.407494 TX Bit1 (977~999) 23 988, Bit9 (967~990) 24 978,
2703 01:56:56.413983 TX Bit2 (975~997) 23 986, Bit10 (968~991) 24 979,
2704 01:56:56.417527 TX Bit3 (972~994) 23 983, Bit11 (969~992) 24 980,
2705 01:56:56.420621 TX Bit4 (976~998) 23 987, Bit12 (969~991) 23 980,
2706 01:56:56.427263 TX Bit5 (977~1000) 24 988, Bit13 (970~991) 22 980,
2707 01:56:56.430852 TX Bit6 (977~1000) 24 988, Bit14 (969~991) 23 980,
2708 01:56:56.437137 TX Bit7 (976~997) 22 986, Bit15 (963~989) 27 976,
2709 01:56:56.437592
2710 01:56:56.437925 Write Rank0 MR14 =0x14
2711 01:56:56.447658
2712 01:56:56.450856 CH=1, VrefRange= 0, VrefLevel = 20
2713 01:56:56.453729 TX Bit0 (977~1001) 25 989, Bit8 (967~991) 25 979,
2714 01:56:56.457155 TX Bit1 (976~999) 24 987, Bit9 (967~990) 24 978,
2715 01:56:56.463851 TX Bit2 (975~997) 23 986, Bit10 (967~991) 25 979,
2716 01:56:56.467073 TX Bit3 (971~995) 25 983, Bit11 (969~992) 24 980,
2717 01:56:56.470557 TX Bit4 (975~999) 25 987, Bit12 (968~992) 25 980,
2718 01:56:56.477161 TX Bit5 (977~1000) 24 988, Bit13 (969~991) 23 980,
2719 01:56:56.480544 TX Bit6 (977~1001) 25 989, Bit14 (969~991) 23 980,
2720 01:56:56.486936 TX Bit7 (976~998) 23 987, Bit15 (963~989) 27 976,
2721 01:56:56.487101
2722 01:56:56.487180 Write Rank0 MR14 =0x16
2723 01:56:56.497322
2724 01:56:56.497498 CH=1, VrefRange= 0, VrefLevel = 22
2725 01:56:56.504255 TX Bit0 (977~1002) 26 989, Bit8 (966~991) 26 978,
2726 01:56:56.507401 TX Bit1 (976~1000) 25 988, Bit9 (966~991) 26 978,
2727 01:56:56.513846 TX Bit2 (974~998) 25 986, Bit10 (967~991) 25 979,
2728 01:56:56.517416 TX Bit3 (971~995) 25 983, Bit11 (969~992) 24 980,
2729 01:56:56.520603 TX Bit4 (975~999) 25 987, Bit12 (968~992) 25 980,
2730 01:56:56.527133 TX Bit5 (977~1001) 25 989, Bit13 (968~991) 24 979,
2731 01:56:56.530232 TX Bit6 (977~1001) 25 989, Bit14 (968~991) 24 979,
2732 01:56:56.537210 TX Bit7 (975~998) 24 986, Bit15 (964~988) 25 976,
2733 01:56:56.537647
2734 01:56:56.537961 Write Rank0 MR14 =0x18
2735 01:56:56.547282
2736 01:56:56.551220 CH=1, VrefRange= 0, VrefLevel = 24
2737 01:56:56.553996 TX Bit0 (977~1002) 26 989, Bit8 (966~991) 26 978,
2738 01:56:56.557381 TX Bit1 (976~1000) 25 988, Bit9 (966~991) 26 978,
2739 01:56:56.563968 TX Bit2 (974~998) 25 986, Bit10 (967~991) 25 979,
2740 01:56:56.567825 TX Bit3 (971~995) 25 983, Bit11 (969~992) 24 980,
2741 01:56:56.571084 TX Bit4 (975~999) 25 987, Bit12 (968~992) 25 980,
2742 01:56:56.577893 TX Bit5 (977~1001) 25 989, Bit13 (968~991) 24 979,
2743 01:56:56.581475 TX Bit6 (977~1001) 25 989, Bit14 (968~991) 24 979,
2744 01:56:56.584272 TX Bit7 (975~998) 24 986, Bit15 (964~988) 25 976,
2745 01:56:56.587925
2746 01:56:56.588386 Write Rank0 MR14 =0x1a
2747 01:56:56.597632
2748 01:56:56.601091 CH=1, VrefRange= 0, VrefLevel = 26
2749 01:56:56.604191 TX Bit0 (977~1002) 26 989, Bit8 (966~991) 26 978,
2750 01:56:56.607756 TX Bit1 (976~1000) 25 988, Bit9 (966~991) 26 978,
2751 01:56:56.614041 TX Bit2 (974~998) 25 986, Bit10 (967~991) 25 979,
2752 01:56:56.617423 TX Bit3 (971~995) 25 983, Bit11 (969~992) 24 980,
2753 01:56:56.620846 TX Bit4 (975~999) 25 987, Bit12 (968~992) 25 980,
2754 01:56:56.627653 TX Bit5 (977~1001) 25 989, Bit13 (968~991) 24 979,
2755 01:56:56.630366 TX Bit6 (977~1001) 25 989, Bit14 (968~991) 24 979,
2756 01:56:56.637322 TX Bit7 (975~998) 24 986, Bit15 (964~988) 25 976,
2757 01:56:56.637941
2758 01:56:56.638477 Write Rank0 MR14 =0x1c
2759 01:56:56.647270
2760 01:56:56.650433 CH=1, VrefRange= 0, VrefLevel = 28
2761 01:56:56.654120 TX Bit0 (977~1002) 26 989, Bit8 (966~991) 26 978,
2762 01:56:56.656996 TX Bit1 (976~1000) 25 988, Bit9 (966~991) 26 978,
2763 01:56:56.664134 TX Bit2 (974~998) 25 986, Bit10 (967~991) 25 979,
2764 01:56:56.666878 TX Bit3 (971~995) 25 983, Bit11 (969~992) 24 980,
2765 01:56:56.670481 TX Bit4 (975~999) 25 987, Bit12 (968~992) 25 980,
2766 01:56:56.677327 TX Bit5 (977~1001) 25 989, Bit13 (968~991) 24 979,
2767 01:56:56.680891 TX Bit6 (977~1001) 25 989, Bit14 (968~991) 24 979,
2768 01:56:56.686978 TX Bit7 (975~998) 24 986, Bit15 (964~988) 25 976,
2769 01:56:56.687483
2770 01:56:56.687816 Write Rank0 MR14 =0x1e
2771 01:56:56.697333
2772 01:56:56.700438 CH=1, VrefRange= 0, VrefLevel = 30
2773 01:56:56.703907 TX Bit0 (977~1002) 26 989, Bit8 (966~991) 26 978,
2774 01:56:56.707132 TX Bit1 (976~1000) 25 988, Bit9 (966~991) 26 978,
2775 01:56:56.714234 TX Bit2 (974~998) 25 986, Bit10 (967~991) 25 979,
2776 01:56:56.717333 TX Bit3 (971~995) 25 983, Bit11 (969~992) 24 980,
2777 01:56:56.721154 TX Bit4 (975~999) 25 987, Bit12 (968~992) 25 980,
2778 01:56:56.727457 TX Bit5 (977~1001) 25 989, Bit13 (968~991) 24 979,
2779 01:56:56.730173 TX Bit6 (977~1001) 25 989, Bit14 (968~991) 24 979,
2780 01:56:56.737122 TX Bit7 (975~998) 24 986, Bit15 (964~988) 25 976,
2781 01:56:56.737733
2782 01:56:56.738101 Write Rank0 MR14 =0x20
2783 01:56:56.746903
2784 01:56:56.750515 CH=1, VrefRange= 0, VrefLevel = 32
2785 01:56:56.753708 TX Bit0 (977~1002) 26 989, Bit8 (966~991) 26 978,
2786 01:56:56.757247 TX Bit1 (976~1000) 25 988, Bit9 (966~991) 26 978,
2787 01:56:56.763584 TX Bit2 (974~998) 25 986, Bit10 (967~991) 25 979,
2788 01:56:56.766713 TX Bit3 (971~995) 25 983, Bit11 (969~992) 24 980,
2789 01:56:56.770696 TX Bit4 (975~999) 25 987, Bit12 (968~992) 25 980,
2790 01:56:56.776755 TX Bit5 (977~1001) 25 989, Bit13 (968~991) 24 979,
2791 01:56:56.780403 TX Bit6 (977~1001) 25 989, Bit14 (968~991) 24 979,
2792 01:56:56.786747 TX Bit7 (975~998) 24 986, Bit15 (964~988) 25 976,
2793 01:56:56.787251
2794 01:56:56.787586
2795 01:56:56.790421 TX Vref found, early break! 369< 379
2796 01:56:56.794053 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =762/100 ps
2797 01:56:56.797322 u1DelayCellOfst[0]=7 cells (6 PI)
2798 01:56:56.800179 u1DelayCellOfst[1]=6 cells (5 PI)
2799 01:56:56.803931 u1DelayCellOfst[2]=3 cells (3 PI)
2800 01:56:56.807112 u1DelayCellOfst[3]=0 cells (0 PI)
2801 01:56:56.810675 u1DelayCellOfst[4]=5 cells (4 PI)
2802 01:56:56.811188 u1DelayCellOfst[5]=7 cells (6 PI)
2803 01:56:56.813846 u1DelayCellOfst[6]=7 cells (6 PI)
2804 01:56:56.817761 u1DelayCellOfst[7]=3 cells (3 PI)
2805 01:56:56.820212 Byte0, DQ PI dly=983, DQM PI dly= 986
2806 01:56:56.827357 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 23)
2807 01:56:56.827870
2808 01:56:56.830313 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 23)
2809 01:56:56.830737
2810 01:56:56.833430 u1DelayCellOfst[8]=2 cells (2 PI)
2811 01:56:56.837087 u1DelayCellOfst[9]=2 cells (2 PI)
2812 01:56:56.840214 u1DelayCellOfst[10]=3 cells (3 PI)
2813 01:56:56.843471 u1DelayCellOfst[11]=5 cells (4 PI)
2814 01:56:56.847126 u1DelayCellOfst[12]=5 cells (4 PI)
2815 01:56:56.850211 u1DelayCellOfst[13]=3 cells (3 PI)
2816 01:56:56.850635 u1DelayCellOfst[14]=3 cells (3 PI)
2817 01:56:56.853457 u1DelayCellOfst[15]=0 cells (0 PI)
2818 01:56:56.856909 Byte1, DQ PI dly=976, DQM PI dly= 978
2819 01:56:56.863856 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 16)
2820 01:56:56.864391
2821 01:56:56.866945 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 16)
2822 01:56:56.867345
2823 01:56:56.870531 Write Rank0 MR14 =0x16
2824 01:56:56.871046
2825 01:56:56.871381 Final TX Range 0 Vref 22
2826 01:56:56.871691
2827 01:56:56.876718 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
2828 01:56:56.877159
2829 01:56:56.883510 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
2830 01:56:56.889913 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2831 01:56:56.900330 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2832 01:56:56.900752 Write Rank0 MR3 =0xb0
2833 01:56:56.904174 DramC Write-DBI on
2834 01:56:56.904700 ==
2835 01:56:56.907220 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2836 01:56:56.910634 fsp= 1, odt_onoff= 1, Byte mode= 0
2837 01:56:56.911158 ==
2838 01:56:56.917063 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
2839 01:56:56.917628
2840 01:56:56.917972 Begin, DQ Scan Range 698~762
2841 01:56:56.918373
2842 01:56:56.920364
2843 01:56:56.920880 TX Vref Scan disable
2844 01:56:56.923457 698 |2 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
2845 01:56:56.927129 699 |2 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
2846 01:56:56.930508 700 |2 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
2847 01:56:56.933668 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
2848 01:56:56.937165 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
2849 01:56:56.940257 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
2850 01:56:56.947046 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
2851 01:56:56.950270 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
2852 01:56:56.953366 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
2853 01:56:56.956724 707 |2 6 3|[0] xxxxxxxx oooooooo [MSB]
2854 01:56:56.960438 708 |2 6 4|[0] xxxxxxxx oooooooo [MSB]
2855 01:56:56.964018 709 |2 6 5|[0] xxxxxxxx oooooooo [MSB]
2856 01:56:56.966752 710 |2 6 6|[0] xxxxxxxx oooooooo [MSB]
2857 01:56:56.970484 711 |2 6 7|[0] xxxxxxxx oooooooo [MSB]
2858 01:56:56.973846 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
2859 01:56:56.976843 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
2860 01:56:56.980538 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
2861 01:56:56.983690 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
2862 01:56:56.987412 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
2863 01:56:56.990445 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB]
2864 01:56:56.993439 718 |2 6 14|[0] xxxxxxxx oooooooo [MSB]
2865 01:56:57.001388 736 |2 6 32|[0] oooooooo xxxxxxxx [MSB]
2866 01:56:57.005391 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
2867 01:56:57.008304 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
2868 01:56:57.011954 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
2869 01:56:57.015292 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
2870 01:56:57.018691 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
2871 01:56:57.022172 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
2872 01:56:57.025123 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
2873 01:56:57.028355 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB]
2874 01:56:57.031766 745 |2 6 41|[0] xxxxxxxx xxxxxxxx [MSB]
2875 01:56:57.035445 Byte0, DQ PI dly=731, DQM PI dly= 731
2876 01:56:57.038697 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 27)
2877 01:56:57.039273
2878 01:56:57.044958 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 27)
2879 01:56:57.045572
2880 01:56:57.048673 Byte1, DQ PI dly=721, DQM PI dly= 721
2881 01:56:57.052311 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 17)
2882 01:56:57.052870
2883 01:56:57.055182 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 17)
2884 01:56:57.055744
2885 01:56:57.061505 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
2886 01:56:57.071951 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2887 01:56:57.078088 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2888 01:56:57.078551 Write Rank0 MR3 =0x30
2889 01:56:57.081622 DramC Write-DBI off
2890 01:56:57.082134
2891 01:56:57.082466 [DATLAT]
2892 01:56:57.084912 Freq=1600, CH1 RK0, use_rxtx_scan=0
2893 01:56:57.085473
2894 01:56:57.087887 DATLAT Default: 0xf
2895 01:56:57.088396 7, 0xFFFF, sum=0
2896 01:56:57.091049 8, 0xFFFF, sum=0
2897 01:56:57.091477 9, 0xFFFF, sum=0
2898 01:56:57.094925 10, 0xFFFF, sum=0
2899 01:56:57.095353 11, 0xFFFF, sum=0
2900 01:56:57.098230 12, 0xFFFF, sum=0
2901 01:56:57.098748 13, 0xFFFF, sum=0
2902 01:56:57.099089 14, 0x0, sum=1
2903 01:56:57.101336 15, 0x0, sum=2
2904 01:56:57.101766 16, 0x0, sum=3
2905 01:56:57.104986 17, 0x0, sum=4
2906 01:56:57.108368 pattern=2 first_step=14 total pass=5 best_step=16
2907 01:56:57.108887 ==
2908 01:56:57.115115 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2909 01:56:57.118359 fsp= 1, odt_onoff= 1, Byte mode= 0
2910 01:56:57.118880 ==
2911 01:56:57.121475 Start DQ dly to find pass range UseTestEngine =1
2912 01:56:57.124872 x-axis: bit #, y-axis: DQ dly (-127~63)
2913 01:56:57.125447 RX Vref Scan = 1
2914 01:56:57.249214
2915 01:56:57.249813 RX Vref found, early break!
2916 01:56:57.250181
2917 01:56:57.255742 Final RX Vref 12, apply to both rank0 and 1
2918 01:56:57.256294 ==
2919 01:56:57.258998 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2920 01:56:57.261778 fsp= 1, odt_onoff= 1, Byte mode= 0
2921 01:56:57.262244 ==
2922 01:56:57.262609 DQS Delay:
2923 01:56:57.265620 DQS0 = 0, DQS1 = 0
2924 01:56:57.266098 DQM Delay:
2925 01:56:57.268919 DQM0 = 20, DQM1 = 19
2926 01:56:57.269429 DQ Delay:
2927 01:56:57.272345 DQ0 =24, DQ1 =23, DQ2 =16, DQ3 =15
2928 01:56:57.276093 DQ4 =19, DQ5 =24, DQ6 =24, DQ7 =19
2929 01:56:57.278575 DQ8 =19, DQ9 =19, DQ10 =18, DQ11 =20
2930 01:56:57.282205 DQ12 =21, DQ13 =19, DQ14 =19, DQ15 =17
2931 01:56:57.282774
2932 01:56:57.283105
2933 01:56:57.283410
2934 01:56:57.285661 [DramC_TX_OE_Calibration] TA2
2935 01:56:57.289104 Original DQ_B0 (3 6) =30, OEN = 27
2936 01:56:57.292492 Original DQ_B1 (3 6) =30, OEN = 27
2937 01:56:57.295376 23, 0x0, End_B0=23 End_B1=23
2938 01:56:57.295848 24, 0x0, End_B0=24 End_B1=24
2939 01:56:57.298894 25, 0x0, End_B0=25 End_B1=25
2940 01:56:57.302016 26, 0x0, End_B0=26 End_B1=26
2941 01:56:57.305447 27, 0x0, End_B0=27 End_B1=27
2942 01:56:57.309079 28, 0x0, End_B0=28 End_B1=28
2943 01:56:57.309642 29, 0x0, End_B0=29 End_B1=29
2944 01:56:57.312199 30, 0x0, End_B0=30 End_B1=30
2945 01:56:57.315498 31, 0xFFFF, End_B0=30 End_B1=30
2946 01:56:57.322088 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
2947 01:56:57.325635 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
2948 01:56:57.326152
2949 01:56:57.326481
2950 01:56:57.328495 Write Rank0 MR23 =0x3f
2951 01:56:57.328915 [DQSOSC]
2952 01:56:57.335579 [DQSOSCAuto] RK0, (LSB)MR18= 0xbf, (MSB)MR19= 0x3, tDQSOscB0 = 328 ps tDQSOscB1 = 0 ps
2953 01:56:57.341914 CH1_RK0: MR19=0x3, MR18=0xBF, DQSOSC=328, MR23=63, INC=22, DEC=34
2954 01:56:57.345445 Write Rank0 MR23 =0x3f
2955 01:56:57.345863 [DQSOSC]
2956 01:56:57.352484 [DQSOSCAuto] RK0, (LSB)MR18= 0xbe, (MSB)MR19= 0x3, tDQSOscB0 = 328 ps tDQSOscB1 = 0 ps
2957 01:56:57.355901 CH1 RK0: MR19=3, MR18=BE
2958 01:56:57.358844 [RankSwap] Rank num 2, (Multi 1), Rank 1
2959 01:56:57.361881 Write Rank0 MR2 =0xad
2960 01:56:57.362299 [Write Leveling]
2961 01:56:57.365329 delay byte0 byte1 byte2 byte3
2962 01:56:57.365777
2963 01:56:57.368467 10 0 0
2964 01:56:57.368892 11 0 0
2965 01:56:57.369226 12 0 0
2966 01:56:57.372401 13 0 0
2967 01:56:57.372915 14 0 0
2968 01:56:57.375129 15 0 0
2969 01:56:57.375555 16 0 0
2970 01:56:57.375891 17 0 0
2971 01:56:57.379266 18 0 0
2972 01:56:57.379787 19 0 0
2973 01:56:57.381851 20 0 0
2974 01:56:57.382280 21 0 0
2975 01:56:57.385382 22 0 0
2976 01:56:57.385811 23 0 0
2977 01:56:57.386148 24 0 0
2978 01:56:57.388813 25 0 0
2979 01:56:57.389391 26 0 0
2980 01:56:57.392360 27 0 0
2981 01:56:57.392878 28 0 0
2982 01:56:57.393221 29 0 0
2983 01:56:57.395437 30 0 0
2984 01:56:57.395863 31 0 0
2985 01:56:57.399201 32 0 ff
2986 01:56:57.399736 33 0 ff
2987 01:56:57.402079 34 0 ff
2988 01:56:57.402504 35 ff ff
2989 01:56:57.405693 36 ff ff
2990 01:56:57.406209 37 ff ff
2991 01:56:57.406548 38 ff ff
2992 01:56:57.408818 39 ff ff
2993 01:56:57.409295 40 ff ff
2994 01:56:57.412633 41 ff ff
2995 01:56:57.415611 pass bytecount = 0xff (0xff: all bytes pass)
2996 01:56:57.416116
2997 01:56:57.416452 DQS0 dly: 35
2998 01:56:57.418976 DQS1 dly: 32
2999 01:56:57.419454 Write Rank0 MR2 =0x2d
3000 01:56:57.422242 [RankSwap] Rank num 2, (Multi 1), Rank 0
3001 01:56:57.425417 Write Rank1 MR1 =0xd6
3002 01:56:57.425928 [Gating]
3003 01:56:57.426260 ==
3004 01:56:57.432020 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3005 01:56:57.435099 fsp= 1, odt_onoff= 1, Byte mode= 0
3006 01:56:57.435522 ==
3007 01:56:57.438473 3 1 0 |3030 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
3008 01:56:57.445432 3 1 4 |3231 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
3009 01:56:57.448815 3 1 8 |2d2c 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
3010 01:56:57.451917 3 1 12 |302 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
3011 01:56:57.455614 3 1 16 |2b2a 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
3012 01:56:57.461945 3 1 20 |2e2e 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
3013 01:56:57.465113 3 1 24 |2e2e 3534 |(0 11)(11 11) |(0 1)(0 1)| 0
3014 01:56:57.468945 3 1 28 |201 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
3015 01:56:57.475063 3 2 0 |1e1e 908 |(11 11)(11 11) |(0 0)(1 1)| 0
3016 01:56:57.478450 3 2 4 |3636 3d3d |(0 0)(11 11) |(0 0)(1 1)| 0
3017 01:56:57.481929 3 2 8 |3737 3d3d |(0 0)(11 11) |(1 1)(1 1)| 0
3018 01:56:57.485394 3 2 12 |3231 3d3d |(1 1)(11 11) |(0 0)(1 1)| 0
3019 01:56:57.492023 3 2 16 |3535 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
3020 01:56:57.495338 3 2 20 |3535 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
3021 01:56:57.499156 3 2 24 |3636 3d3d |(0 0)(11 11) |(1 1)(1 1)| 0
3022 01:56:57.505537 3 2 28 |1a19 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3023 01:56:57.508791 3 3 0 |2f2e 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3024 01:56:57.511978 [Byte 0] Lead/lag falling Transition (3, 3, 0)
3025 01:56:57.515258 3 3 4 |3534 1010 |(11 11)(11 11) |(0 1)(1 1)| 0
3026 01:56:57.522040 3 3 8 |3534 807 |(11 11)(11 11) |(0 1)(1 1)| 0
3027 01:56:57.524894 [Byte 1] Lead/lag falling Transition (3, 3, 8)
3028 01:56:57.528646 3 3 12 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
3029 01:56:57.535349 3 3 16 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
3030 01:56:57.538233 3 3 20 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
3031 01:56:57.541728 3 3 24 |3534 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
3032 01:56:57.548660 3 3 28 |201 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
3033 01:56:57.551653 3 4 0 |3d3d 403 |(11 11)(11 11) |(1 1)(1 1)| 0
3034 01:56:57.555177 3 4 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3035 01:56:57.558556 3 4 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3036 01:56:57.565103 3 4 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3037 01:56:57.568340 3 4 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3038 01:56:57.571475 3 4 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3039 01:56:57.578025 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3040 01:56:57.581787 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3041 01:56:57.585072 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3042 01:56:57.591795 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3043 01:56:57.595066 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3044 01:56:57.598333 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3045 01:56:57.601447 [Byte 0] Lead/lag falling Transition (3, 5, 12)
3046 01:56:57.608286 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
3047 01:56:57.611616 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
3048 01:56:57.614890 [Byte 0] Lead/lag Transition tap number (3)
3049 01:56:57.621622 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
3050 01:56:57.624882 [Byte 1] Lead/lag Transition tap number (1)
3051 01:56:57.628147 3 5 28 |605 3d3d |(11 11)(11 11) |(0 0)(0 0)| 0
3052 01:56:57.631277 3 6 0 |4646 202 |(0 0)(11 11) |(0 0)(0 0)| 0
3053 01:56:57.634848 [Byte 0]First pass (3, 6, 0)
3054 01:56:57.638359 3 6 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3055 01:56:57.641438 [Byte 1]First pass (3, 6, 4)
3056 01:56:57.644967 3 6 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3057 01:56:57.648424 3 6 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3058 01:56:57.655098 3 6 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3059 01:56:57.658017 3 6 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3060 01:56:57.661802 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3061 01:56:57.664769 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3062 01:56:57.668144 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3063 01:56:57.674813 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3064 01:56:57.678523 All bytes gating window > 1UI, Early break!
3065 01:56:57.679034
3066 01:56:57.681726 best DQS0 dly(2T, 0.5T, PI) = (3, 5, 18)
3067 01:56:57.682150
3068 01:56:57.685002 best DQS1 dly(2T, 0.5T, PI) = (3, 5, 26)
3069 01:56:57.685559
3070 01:56:57.685898
3071 01:56:57.686207
3072 01:56:57.688018 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 1, 18)
3073 01:56:57.688440
3074 01:56:57.694929 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 1, 26)
3075 01:56:57.695357
3076 01:56:57.695732
3077 01:56:57.696046 Write Rank1 MR1 =0x56
3078 01:56:57.696347
3079 01:56:57.697904 best RODT dly(2T, 0.5T) = (2, 2)
3080 01:56:57.698325
3081 01:56:57.701598 best RODT dly(2T, 0.5T) = (2, 2)
3082 01:56:57.702021 ==
3083 01:56:57.708521 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3084 01:56:57.711768 fsp= 1, odt_onoff= 1, Byte mode= 0
3085 01:56:57.712280 ==
3086 01:56:57.714839 Start DQ dly to find pass range UseTestEngine =0
3087 01:56:57.718324 x-axis: bit #, y-axis: DQ dly (-127~63)
3088 01:56:57.721884 RX Vref Scan = 0
3089 01:56:57.724664 -26, [0] xxxxxxxx xxxxxxxx [MSB]
3090 01:56:57.725096 -25, [0] xxxxxxxx xxxxxxxx [MSB]
3091 01:56:57.728416 -24, [0] xxxxxxxx xxxxxxxx [MSB]
3092 01:56:57.731351 -23, [0] xxxxxxxx xxxxxxxx [MSB]
3093 01:56:57.734565 -22, [0] xxxxxxxx xxxxxxxx [MSB]
3094 01:56:57.738326 -21, [0] xxxxxxxx xxxxxxxx [MSB]
3095 01:56:57.741705 -20, [0] xxxxxxxx xxxxxxxx [MSB]
3096 01:56:57.745142 -19, [0] xxxxxxxx xxxxxxxx [MSB]
3097 01:56:57.748147 -18, [0] xxxxxxxx xxxxxxxx [MSB]
3098 01:56:57.748575 -17, [0] xxxxxxxx xxxxxxxx [MSB]
3099 01:56:57.752062 -16, [0] xxxxxxxx xxxxxxxx [MSB]
3100 01:56:57.754797 -15, [0] xxxxxxxx xxxxxxxx [MSB]
3101 01:56:57.758584 -14, [0] xxxxxxxx xxxxxxxx [MSB]
3102 01:56:57.761330 -13, [0] xxxxxxxx xxxxxxxx [MSB]
3103 01:56:57.764803 -12, [0] xxxxxxxx xxxxxxxx [MSB]
3104 01:56:57.768262 -11, [0] xxxxxxxx xxxxxxxx [MSB]
3105 01:56:57.771810 -10, [0] xxxxxxxx xxxxxxxx [MSB]
3106 01:56:57.772343 -9, [0] xxxxxxxx xxxxxxxx [MSB]
3107 01:56:57.774854 -8, [0] xxxxxxxx xxxxxxxx [MSB]
3108 01:56:57.777964 -7, [0] xxxxxxxx xxxxxxxx [MSB]
3109 01:56:57.781901 -6, [0] xxxxxxxx xxxxxxxx [MSB]
3110 01:56:57.784853 -5, [0] xxxxxxxx xxxxxxxx [MSB]
3111 01:56:57.788530 -4, [0] xxxxxxxx xxxxxxxx [MSB]
3112 01:56:57.791839 -3, [0] xxxxxxxx xxxxxxxx [MSB]
3113 01:56:57.792404 -2, [0] xxxxxxxx xxxxxxxx [MSB]
3114 01:56:57.795082 -1, [0] xxxoxxxx xxxxxxxx [MSB]
3115 01:56:57.798631 0, [0] xxxoxxxx xxxxxxxo [MSB]
3116 01:56:57.801946 1, [0] xxooxxxx xxxxxxxo [MSB]
3117 01:56:57.805431 2, [0] xxooxxxo xxxxxxxo [MSB]
3118 01:56:57.808679 3, [0] xxoooxxo oooxxoxo [MSB]
3119 01:56:57.809237 4, [0] xxoooxxo oooxxoxo [MSB]
3120 01:56:57.811695 5, [0] xooooxxo oooooooo [MSB]
3121 01:56:57.814914 6, [0] xooooxxo oooooooo [MSB]
3122 01:56:57.818443 7, [0] xoooooxo oooooooo [MSB]
3123 01:56:57.821737 33, [0] oooxoooo oooooooo [MSB]
3124 01:56:57.824971 34, [0] ooxxoooo ooooooox [MSB]
3125 01:56:57.828915 35, [0] ooxxoooo ooooooox [MSB]
3126 01:56:57.829590 36, [0] ooxxoooo ooxoooox [MSB]
3127 01:56:57.831409 37, [0] ooxxxoox xoxoooox [MSB]
3128 01:56:57.834780 38, [0] ooxxxoox xxxooxxx [MSB]
3129 01:56:57.838524 39, [0] ooxxxoox xxxxoxxx [MSB]
3130 01:56:57.841464 40, [0] ooxxxoox xxxxoxxx [MSB]
3131 01:56:57.844835 41, [0] oxxxxxxx xxxxxxxx [MSB]
3132 01:56:57.847983 42, [0] xxxxxxxx xxxxxxxx [MSB]
3133 01:56:57.851703 iDelay=42, Bit 0, Center 24 (8 ~ 41) 34
3134 01:56:57.854755 iDelay=42, Bit 1, Center 22 (5 ~ 40) 36
3135 01:56:57.857987 iDelay=42, Bit 2, Center 17 (1 ~ 33) 33
3136 01:56:57.861318 iDelay=42, Bit 3, Center 15 (-1 ~ 32) 34
3137 01:56:57.865143 iDelay=42, Bit 4, Center 19 (3 ~ 36) 34
3138 01:56:57.868344 iDelay=42, Bit 5, Center 23 (7 ~ 40) 34
3139 01:56:57.871621 iDelay=42, Bit 6, Center 24 (8 ~ 40) 33
3140 01:56:57.874537 iDelay=42, Bit 7, Center 19 (2 ~ 36) 35
3141 01:56:57.878007 iDelay=42, Bit 8, Center 19 (3 ~ 36) 34
3142 01:56:57.881569 iDelay=42, Bit 9, Center 20 (3 ~ 37) 35
3143 01:56:57.884819 iDelay=42, Bit 10, Center 19 (3 ~ 35) 33
3144 01:56:57.888894 iDelay=42, Bit 11, Center 21 (5 ~ 38) 34
3145 01:56:57.891668 iDelay=42, Bit 12, Center 22 (5 ~ 40) 36
3146 01:56:57.894675 iDelay=42, Bit 13, Center 20 (3 ~ 37) 35
3147 01:56:57.901639 iDelay=42, Bit 14, Center 21 (5 ~ 37) 33
3148 01:56:57.905154 iDelay=42, Bit 15, Center 16 (0 ~ 33) 34
3149 01:56:57.905785 ==
3150 01:56:57.908487 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3151 01:56:57.911587 fsp= 1, odt_onoff= 1, Byte mode= 0
3152 01:56:57.912136 ==
3153 01:56:57.914961 DQS Delay:
3154 01:56:57.915516 DQS0 = 0, DQS1 = 0
3155 01:56:57.915882 DQM Delay:
3156 01:56:57.918521 DQM0 = 20, DQM1 = 19
3157 01:56:57.919075 DQ Delay:
3158 01:56:57.921786 DQ0 =24, DQ1 =22, DQ2 =17, DQ3 =15
3159 01:56:57.925346 DQ4 =19, DQ5 =23, DQ6 =24, DQ7 =19
3160 01:56:57.928099 DQ8 =19, DQ9 =20, DQ10 =19, DQ11 =21
3161 01:56:57.931771 DQ12 =22, DQ13 =20, DQ14 =21, DQ15 =16
3162 01:56:57.932321
3163 01:56:57.932687
3164 01:56:57.934674 DramC Write-DBI off
3165 01:56:57.935136 ==
3166 01:56:57.938282 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3167 01:56:57.941528 fsp= 1, odt_onoff= 1, Byte mode= 0
3168 01:56:57.941996 ==
3169 01:56:57.948150 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
3170 01:56:57.948699
3171 01:56:57.949065 Begin, DQ Scan Range 928~1184
3172 01:56:57.952059
3173 01:56:57.952605
3174 01:56:57.952972 TX Vref Scan disable
3175 01:56:57.954809 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
3176 01:56:57.958133 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
3177 01:56:57.961352 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
3178 01:56:57.964960 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
3179 01:56:57.967889 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
3180 01:56:57.975023 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
3181 01:56:57.978000 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
3182 01:56:57.981655 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
3183 01:56:57.984698 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
3184 01:56:57.988877 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
3185 01:56:57.991537 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
3186 01:56:57.994926 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
3187 01:56:57.997919 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
3188 01:56:58.001112 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
3189 01:56:58.004985 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
3190 01:56:58.008056 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
3191 01:56:58.012195 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
3192 01:56:58.014956 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
3193 01:56:58.018446 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
3194 01:56:58.021833 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
3195 01:56:58.024738 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
3196 01:56:58.028461 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
3197 01:56:58.034912 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
3198 01:56:58.038252 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
3199 01:56:58.041440 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
3200 01:56:58.044609 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
3201 01:56:58.048135 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
3202 01:56:58.051532 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
3203 01:56:58.055052 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
3204 01:56:58.057965 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
3205 01:56:58.061168 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
3206 01:56:58.064750 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
3207 01:56:58.068199 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
3208 01:56:58.071568 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
3209 01:56:58.074563 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
3210 01:56:58.078413 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
3211 01:56:58.081523 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
3212 01:56:58.085062 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
3213 01:56:58.088819 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
3214 01:56:58.091895 967 |3 6 7|[0] xxxxxxxx xxxxxxxo [MSB]
3215 01:56:58.094393 968 |3 6 8|[0] xxxxxxxx xoxxxxxo [MSB]
3216 01:56:58.098019 969 |3 6 9|[0] xxxxxxxx ooxxxxxo [MSB]
3217 01:56:58.104414 970 |3 6 10|[0] xxxxxxxx oooxoxoo [MSB]
3218 01:56:58.107860 971 |3 6 11|[0] xxxxxxxx oooooooo [MSB]
3219 01:56:58.110930 972 |3 6 12|[0] xxxxxxxx oooooooo [MSB]
3220 01:56:58.114723 973 |3 6 13|[0] xxxoxxxx oooooooo [MSB]
3221 01:56:58.118221 974 |3 6 14|[0] xxooxxxx oooooooo [MSB]
3222 01:56:58.121417 975 |3 6 15|[0] xxoooxxx oooooooo [MSB]
3223 01:56:58.124860 976 |3 6 16|[0] xxoooxxo oooooooo [MSB]
3224 01:56:58.131114 989 |3 6 29|[0] oooooooo ooooooox [MSB]
3225 01:56:58.135279 990 |3 6 30|[0] oooooooo ooooooox [MSB]
3226 01:56:58.138244 991 |3 6 31|[0] oooooooo xxxxxxxx [MSB]
3227 01:56:58.141670 992 |3 6 32|[0] oooooooo xxxxxxxx [MSB]
3228 01:56:58.145004 993 |3 6 33|[0] oooooooo xxxxxxxx [MSB]
3229 01:56:58.148299 994 |3 6 34|[0] oooxoooo xxxxxxxx [MSB]
3230 01:56:58.151622 995 |3 6 35|[0] ooxxoooo xxxxxxxx [MSB]
3231 01:56:58.154915 996 |3 6 36|[0] ooxxoooo xxxxxxxx [MSB]
3232 01:56:58.158243 997 |3 6 37|[0] ooxxooox xxxxxxxx [MSB]
3233 01:56:58.162166 998 |3 6 38|[0] ooxxxoox xxxxxxxx [MSB]
3234 01:56:58.164611 999 |3 6 39|[0] xxxxxxxx xxxxxxxx [MSB]
3235 01:56:58.168066 Byte0, DQ PI dly=985, DQM PI dly= 985
3236 01:56:58.171317 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 25)
3237 01:56:58.171777
3238 01:56:58.178037 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 25)
3239 01:56:58.178496
3240 01:56:58.181246 Byte1, DQ PI dly=978, DQM PI dly= 978
3241 01:56:58.184846 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 18)
3242 01:56:58.185482
3243 01:56:58.188300 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 18)
3244 01:56:58.191385
3245 01:56:58.191835 ==
3246 01:56:58.194667 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3247 01:56:58.198068 fsp= 1, odt_onoff= 1, Byte mode= 0
3248 01:56:58.198555 ==
3249 01:56:58.201410 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
3250 01:56:58.201899
3251 01:56:58.204738 Begin, DQ Scan Range 954~1018
3252 01:56:58.207825 Write Rank1 MR14 =0x0
3253 01:56:58.216088
3254 01:56:58.216570 CH=1, VrefRange= 0, VrefLevel = 0
3255 01:56:58.222866 TX Bit0 (979~998) 20 988, Bit8 (971~986) 16 978,
3256 01:56:58.226453 TX Bit1 (978~996) 19 987, Bit9 (970~986) 17 978,
3257 01:56:58.233136 TX Bit2 (976~991) 16 983, Bit10 (972~986) 15 979,
3258 01:56:58.236689 TX Bit3 (975~990) 16 982, Bit11 (974~990) 17 982,
3259 01:56:58.239700 TX Bit4 (976~992) 17 984, Bit12 (973~988) 16 980,
3260 01:56:58.246078 TX Bit5 (978~997) 20 987, Bit13 (975~987) 13 981,
3261 01:56:58.249504 TX Bit6 (978~997) 20 987, Bit14 (973~987) 15 980,
3262 01:56:58.252707 TX Bit7 (977~992) 16 984, Bit15 (968~985) 18 976,
3263 01:56:58.253284
3264 01:56:58.256176 Write Rank1 MR14 =0x2
3265 01:56:58.265121
3266 01:56:58.265607 CH=1, VrefRange= 0, VrefLevel = 2
3267 01:56:58.271813 TX Bit0 (979~998) 20 988, Bit8 (971~987) 17 979,
3268 01:56:58.275172 TX Bit1 (978~996) 19 987, Bit9 (970~987) 18 978,
3269 01:56:58.281337 TX Bit2 (976~991) 16 983, Bit10 (972~987) 16 979,
3270 01:56:58.284742 TX Bit3 (975~991) 17 983, Bit11 (973~991) 19 982,
3271 01:56:58.288605 TX Bit4 (976~993) 18 984, Bit12 (972~988) 17 980,
3272 01:56:58.295016 TX Bit5 (978~997) 20 987, Bit13 (974~987) 14 980,
3273 01:56:58.298509 TX Bit6 (978~998) 21 988, Bit14 (973~988) 16 980,
3274 01:56:58.301713 TX Bit7 (977~992) 16 984, Bit15 (968~985) 18 976,
3275 01:56:58.301977
3276 01:56:58.304656 Write Rank1 MR14 =0x4
3277 01:56:58.314219
3278 01:56:58.314513 CH=1, VrefRange= 0, VrefLevel = 4
3279 01:56:58.321161 TX Bit0 (979~998) 20 988, Bit8 (970~987) 18 978,
3280 01:56:58.324183 TX Bit1 (978~997) 20 987, Bit9 (970~987) 18 978,
3281 01:56:58.331251 TX Bit2 (975~992) 18 983, Bit10 (971~987) 17 979,
3282 01:56:58.334462 TX Bit3 (974~991) 18 982, Bit11 (973~991) 19 982,
3283 01:56:58.337579 TX Bit4 (976~994) 19 985, Bit12 (972~989) 18 980,
3284 01:56:58.344493 TX Bit5 (978~997) 20 987, Bit13 (974~988) 15 981,
3285 01:56:58.347697 TX Bit6 (978~998) 21 988, Bit14 (972~988) 17 980,
3286 01:56:58.351146 TX Bit7 (977~993) 17 985, Bit15 (968~985) 18 976,
3287 01:56:58.351839
3288 01:56:58.353990 Write Rank1 MR14 =0x6
3289 01:56:58.363228
3290 01:56:58.363773 CH=1, VrefRange= 0, VrefLevel = 6
3291 01:56:58.369798 TX Bit0 (978~998) 21 988, Bit8 (970~988) 19 979,
3292 01:56:58.373226 TX Bit1 (977~997) 21 987, Bit9 (969~987) 19 978,
3293 01:56:58.380032 TX Bit2 (975~992) 18 983, Bit10 (970~987) 18 978,
3294 01:56:58.383322 TX Bit3 (974~991) 18 982, Bit11 (972~991) 20 981,
3295 01:56:58.386335 TX Bit4 (976~994) 19 985, Bit12 (972~990) 19 981,
3296 01:56:58.393066 TX Bit5 (978~998) 21 988, Bit13 (973~989) 17 981,
3297 01:56:58.396467 TX Bit6 (978~998) 21 988, Bit14 (972~989) 18 980,
3298 01:56:58.400052 TX Bit7 (977~993) 17 985, Bit15 (968~986) 19 977,
3299 01:56:58.400617
3300 01:56:58.403073 Write Rank1 MR14 =0x8
3301 01:56:58.412561
3302 01:56:58.413113 CH=1, VrefRange= 0, VrefLevel = 8
3303 01:56:58.419695 TX Bit0 (978~999) 22 988, Bit8 (970~989) 20 979,
3304 01:56:58.422066 TX Bit1 (978~997) 20 987, Bit9 (970~988) 19 979,
3305 01:56:58.429117 TX Bit2 (975~992) 18 983, Bit10 (970~988) 19 979,
3306 01:56:58.432709 TX Bit3 (973~992) 20 982, Bit11 (972~991) 20 981,
3307 01:56:58.435707 TX Bit4 (976~994) 19 985, Bit12 (971~990) 20 980,
3308 01:56:58.442292 TX Bit5 (978~998) 21 988, Bit13 (972~989) 18 980,
3309 01:56:58.445665 TX Bit6 (978~999) 22 988, Bit14 (971~990) 20 980,
3310 01:56:58.449445 TX Bit7 (977~994) 18 985, Bit15 (968~986) 19 977,
3311 01:56:58.450000
3312 01:56:58.452145 Write Rank1 MR14 =0xa
3313 01:56:58.461494
3314 01:56:58.465017 CH=1, VrefRange= 0, VrefLevel = 10
3315 01:56:58.468147 TX Bit0 (978~999) 22 988, Bit8 (970~988) 19 979,
3316 01:56:58.471186 TX Bit1 (978~998) 21 988, Bit9 (969~988) 20 978,
3317 01:56:58.477972 TX Bit2 (975~993) 19 984, Bit10 (970~989) 20 979,
3318 01:56:58.481447 TX Bit3 (973~992) 20 982, Bit11 (972~992) 21 982,
3319 01:56:58.485170 TX Bit4 (976~995) 20 985, Bit12 (970~991) 22 980,
3320 01:56:58.491390 TX Bit5 (977~998) 22 987, Bit13 (972~990) 19 981,
3321 01:56:58.494889 TX Bit6 (978~999) 22 988, Bit14 (971~990) 20 980,
3322 01:56:58.498260 TX Bit7 (977~994) 18 985, Bit15 (967~986) 20 976,
3323 01:56:58.498725
3324 01:56:58.501555 Write Rank1 MR14 =0xc
3325 01:56:58.510615
3326 01:56:58.514028 CH=1, VrefRange= 0, VrefLevel = 12
3327 01:56:58.517310 TX Bit0 (978~999) 22 988, Bit8 (969~991) 23 980,
3328 01:56:58.521053 TX Bit1 (977~998) 22 987, Bit9 (969~989) 21 979,
3329 01:56:58.527082 TX Bit2 (975~993) 19 984, Bit10 (970~991) 22 980,
3330 01:56:58.530998 TX Bit3 (973~993) 21 983, Bit11 (971~992) 22 981,
3331 01:56:58.534029 TX Bit4 (975~996) 22 985, Bit12 (970~991) 22 980,
3332 01:56:58.541003 TX Bit5 (977~998) 22 987, Bit13 (972~991) 20 981,
3333 01:56:58.544034 TX Bit6 (977~999) 23 988, Bit14 (970~991) 22 980,
3334 01:56:58.547101 TX Bit7 (976~995) 20 985, Bit15 (967~987) 21 977,
3335 01:56:58.547562
3336 01:56:58.550924 Write Rank1 MR14 =0xe
3337 01:56:58.560215
3338 01:56:58.563568 CH=1, VrefRange= 0, VrefLevel = 14
3339 01:56:58.566518 TX Bit0 (977~1000) 24 988, Bit8 (969~991) 23 980,
3340 01:56:58.570032 TX Bit1 (977~998) 22 987, Bit9 (969~990) 22 979,
3341 01:56:58.577137 TX Bit2 (974~994) 21 984, Bit10 (970~991) 22 980,
3342 01:56:58.580629 TX Bit3 (972~993) 22 982, Bit11 (971~992) 22 981,
3343 01:56:58.583794 TX Bit4 (975~997) 23 986, Bit12 (970~991) 22 980,
3344 01:56:58.590463 TX Bit5 (977~999) 23 988, Bit13 (971~991) 21 981,
3345 01:56:58.593533 TX Bit6 (977~1000) 24 988, Bit14 (970~991) 22 980,
3346 01:56:58.596823 TX Bit7 (976~995) 20 985, Bit15 (967~987) 21 977,
3347 01:56:58.600264
3348 01:56:58.600848 Write Rank1 MR14 =0x10
3349 01:56:58.609919
3350 01:56:58.613226 CH=1, VrefRange= 0, VrefLevel = 16
3351 01:56:58.616606 TX Bit0 (977~1000) 24 988, Bit8 (969~991) 23 980,
3352 01:56:58.619737 TX Bit1 (977~998) 22 987, Bit9 (969~990) 22 979,
3353 01:56:58.626432 TX Bit2 (973~994) 22 983, Bit10 (970~991) 22 980,
3354 01:56:58.629635 TX Bit3 (971~994) 24 982, Bit11 (970~993) 24 981,
3355 01:56:58.632964 TX Bit4 (975~997) 23 986, Bit12 (970~991) 22 980,
3356 01:56:58.639778 TX Bit5 (977~999) 23 988, Bit13 (972~991) 20 981,
3357 01:56:58.643082 TX Bit6 (977~999) 23 988, Bit14 (969~991) 23 980,
3358 01:56:58.646343 TX Bit7 (976~996) 21 986, Bit15 (967~987) 21 977,
3359 01:56:58.649516
3360 01:56:58.650113 Write Rank1 MR14 =0x12
3361 01:56:58.659176
3362 01:56:58.662166 CH=1, VrefRange= 0, VrefLevel = 18
3363 01:56:58.666329 TX Bit0 (977~1000) 24 988, Bit8 (969~991) 23 980,
3364 01:56:58.668809 TX Bit1 (977~999) 23 988, Bit9 (969~991) 23 980,
3365 01:56:58.675478 TX Bit2 (973~995) 23 984, Bit10 (969~991) 23 980,
3366 01:56:58.678732 TX Bit3 (971~994) 24 982, Bit11 (970~993) 24 981,
3367 01:56:58.682219 TX Bit4 (975~998) 24 986, Bit12 (970~992) 23 981,
3368 01:56:58.688907 TX Bit5 (977~999) 23 988, Bit13 (971~991) 21 981,
3369 01:56:58.692355 TX Bit6 (977~1000) 24 988, Bit14 (970~992) 23 981,
3370 01:56:58.698593 TX Bit7 (976~997) 22 986, Bit15 (967~988) 22 977,
3371 01:56:58.699036
3372 01:56:58.699365 Write Rank1 MR14 =0x14
3373 01:56:58.709095
3374 01:56:58.712436 CH=1, VrefRange= 0, VrefLevel = 20
3375 01:56:58.715898 TX Bit0 (977~1001) 25 989, Bit8 (969~991) 23 980,
3376 01:56:58.718750 TX Bit1 (976~999) 24 987, Bit9 (968~991) 24 979,
3377 01:56:58.725684 TX Bit2 (973~996) 24 984, Bit10 (968~991) 24 979,
3378 01:56:58.728969 TX Bit3 (970~995) 26 982, Bit11 (970~993) 24 981,
3379 01:56:58.732089 TX Bit4 (974~997) 24 985, Bit12 (970~992) 23 981,
3380 01:56:58.738880 TX Bit5 (976~999) 24 987, Bit13 (970~992) 23 981,
3381 01:56:58.742178 TX Bit6 (977~1000) 24 988, Bit14 (970~992) 23 981,
3382 01:56:58.745465 TX Bit7 (975~997) 23 986, Bit15 (967~988) 22 977,
3383 01:56:58.748927
3384 01:56:58.749382 Write Rank1 MR14 =0x16
3385 01:56:58.758765
3386 01:56:58.762013 CH=1, VrefRange= 0, VrefLevel = 22
3387 01:56:58.765357 TX Bit0 (977~1001) 25 989, Bit8 (969~991) 23 980,
3388 01:56:58.768560 TX Bit1 (977~1000) 24 988, Bit9 (968~991) 24 979,
3389 01:56:58.775459 TX Bit2 (973~996) 24 984, Bit10 (968~991) 24 979,
3390 01:56:58.778670 TX Bit3 (970~995) 26 982, Bit11 (970~993) 24 981,
3391 01:56:58.781993 TX Bit4 (974~998) 25 986, Bit12 (969~992) 24 980,
3392 01:56:58.788485 TX Bit5 (976~1000) 25 988, Bit13 (970~992) 23 981,
3393 01:56:58.792213 TX Bit6 (976~1001) 26 988, Bit14 (969~992) 24 980,
3394 01:56:58.798743 TX Bit7 (975~997) 23 986, Bit15 (966~989) 24 977,
3395 01:56:58.799177
3396 01:56:58.799507 Write Rank1 MR14 =0x18
3397 01:56:58.808900
3398 01:56:58.811772 CH=1, VrefRange= 0, VrefLevel = 24
3399 01:56:58.815162 TX Bit0 (977~1001) 25 989, Bit8 (969~991) 23 980,
3400 01:56:58.818870 TX Bit1 (977~1000) 24 988, Bit9 (968~991) 24 979,
3401 01:56:58.825369 TX Bit2 (973~996) 24 984, Bit10 (968~991) 24 979,
3402 01:56:58.828647 TX Bit3 (970~995) 26 982, Bit11 (970~993) 24 981,
3403 01:56:58.832192 TX Bit4 (974~998) 25 986, Bit12 (969~992) 24 980,
3404 01:56:58.838791 TX Bit5 (976~1000) 25 988, Bit13 (970~992) 23 981,
3405 01:56:58.842167 TX Bit6 (976~1001) 26 988, Bit14 (969~992) 24 980,
3406 01:56:58.848337 TX Bit7 (975~997) 23 986, Bit15 (966~989) 24 977,
3407 01:56:58.848751
3408 01:56:58.849073 Write Rank1 MR14 =0x1a
3409 01:56:58.858722
3410 01:56:58.862156 CH=1, VrefRange= 0, VrefLevel = 26
3411 01:56:58.865530 TX Bit0 (977~1001) 25 989, Bit8 (969~991) 23 980,
3412 01:56:58.868656 TX Bit1 (977~1000) 24 988, Bit9 (968~991) 24 979,
3413 01:56:58.875728 TX Bit2 (973~996) 24 984, Bit10 (968~991) 24 979,
3414 01:56:58.878669 TX Bit3 (970~995) 26 982, Bit11 (970~993) 24 981,
3415 01:56:58.882276 TX Bit4 (974~998) 25 986, Bit12 (969~992) 24 980,
3416 01:56:58.888898 TX Bit5 (976~1000) 25 988, Bit13 (970~992) 23 981,
3417 01:56:58.892584 TX Bit6 (976~1001) 26 988, Bit14 (969~992) 24 980,
3418 01:56:58.898627 TX Bit7 (975~997) 23 986, Bit15 (966~989) 24 977,
3419 01:56:58.899049
3420 01:56:58.899370 Write Rank1 MR14 =0x1c
3421 01:56:58.909087
3422 01:56:58.909699 CH=1, VrefRange= 0, VrefLevel = 28
3423 01:56:58.915900 TX Bit0 (977~1001) 25 989, Bit8 (969~991) 23 980,
3424 01:56:58.918925 TX Bit1 (977~1000) 24 988, Bit9 (968~991) 24 979,
3425 01:56:58.925970 TX Bit2 (973~996) 24 984, Bit10 (968~991) 24 979,
3426 01:56:58.929330 TX Bit3 (970~995) 26 982, Bit11 (970~993) 24 981,
3427 01:56:58.932634 TX Bit4 (974~998) 25 986, Bit12 (969~992) 24 980,
3428 01:56:58.939164 TX Bit5 (976~1000) 25 988, Bit13 (970~992) 23 981,
3429 01:56:58.942355 TX Bit6 (976~1001) 26 988, Bit14 (969~992) 24 980,
3430 01:56:58.949054 TX Bit7 (975~997) 23 986, Bit15 (966~989) 24 977,
3431 01:56:58.949611
3432 01:56:58.949939 Write Rank1 MR14 =0x1e
3433 01:56:58.959048
3434 01:56:58.962167 CH=1, VrefRange= 0, VrefLevel = 30
3435 01:56:58.965653 TX Bit0 (977~1001) 25 989, Bit8 (969~991) 23 980,
3436 01:56:58.968746 TX Bit1 (977~1000) 24 988, Bit9 (968~991) 24 979,
3437 01:56:58.975386 TX Bit2 (973~996) 24 984, Bit10 (968~991) 24 979,
3438 01:56:58.978883 TX Bit3 (970~995) 26 982, Bit11 (970~993) 24 981,
3439 01:56:58.982041 TX Bit4 (974~998) 25 986, Bit12 (969~992) 24 980,
3440 01:56:58.989215 TX Bit5 (976~1000) 25 988, Bit13 (970~992) 23 981,
3441 01:56:58.992232 TX Bit6 (976~1001) 26 988, Bit14 (969~992) 24 980,
3442 01:56:58.998722 TX Bit7 (975~997) 23 986, Bit15 (966~989) 24 977,
3443 01:56:58.999225
3444 01:56:58.999548 Write Rank1 MR14 =0x20
3445 01:56:59.008915
3446 01:56:59.012493 CH=1, VrefRange= 0, VrefLevel = 32
3447 01:56:59.015198 TX Bit0 (977~1001) 25 989, Bit8 (969~991) 23 980,
3448 01:56:59.018902 TX Bit1 (977~1000) 24 988, Bit9 (968~991) 24 979,
3449 01:56:59.025253 TX Bit2 (973~996) 24 984, Bit10 (968~991) 24 979,
3450 01:56:59.028703 TX Bit3 (970~995) 26 982, Bit11 (970~993) 24 981,
3451 01:56:59.032288 TX Bit4 (974~998) 25 986, Bit12 (969~992) 24 980,
3452 01:56:59.038601 TX Bit5 (976~1000) 25 988, Bit13 (970~992) 23 981,
3453 01:56:59.042225 TX Bit6 (976~1001) 26 988, Bit14 (969~992) 24 980,
3454 01:56:59.048895 TX Bit7 (975~997) 23 986, Bit15 (966~989) 24 977,
3455 01:56:59.049445
3456 01:56:59.049776
3457 01:56:59.052382 TX Vref found, early break! 358< 368
3458 01:56:59.055934 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =762/100 ps
3459 01:56:59.059031 u1DelayCellOfst[0]=8 cells (7 PI)
3460 01:56:59.062179 u1DelayCellOfst[1]=7 cells (6 PI)
3461 01:56:59.065643 u1DelayCellOfst[2]=2 cells (2 PI)
3462 01:56:59.068364 u1DelayCellOfst[3]=0 cells (0 PI)
3463 01:56:59.072101 u1DelayCellOfst[4]=5 cells (4 PI)
3464 01:56:59.072515 u1DelayCellOfst[5]=7 cells (6 PI)
3465 01:56:59.075302 u1DelayCellOfst[6]=7 cells (6 PI)
3466 01:56:59.078968 u1DelayCellOfst[7]=5 cells (4 PI)
3467 01:56:59.081944 Byte0, DQ PI dly=982, DQM PI dly= 985
3468 01:56:59.088757 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 22)
3469 01:56:59.089309
3470 01:56:59.091751 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 22)
3471 01:56:59.092167
3472 01:56:59.095506 u1DelayCellOfst[8]=3 cells (3 PI)
3473 01:56:59.098946 u1DelayCellOfst[9]=2 cells (2 PI)
3474 01:56:59.101928 u1DelayCellOfst[10]=2 cells (2 PI)
3475 01:56:59.105723 u1DelayCellOfst[11]=5 cells (4 PI)
3476 01:56:59.108950 u1DelayCellOfst[12]=3 cells (3 PI)
3477 01:56:59.112766 u1DelayCellOfst[13]=5 cells (4 PI)
3478 01:56:59.113323 u1DelayCellOfst[14]=3 cells (3 PI)
3479 01:56:59.115561 u1DelayCellOfst[15]=0 cells (0 PI)
3480 01:56:59.118772 Byte1, DQ PI dly=977, DQM PI dly= 979
3481 01:56:59.125297 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 17)
3482 01:56:59.125816
3483 01:56:59.128619 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 17)
3484 01:56:59.129049
3485 01:56:59.132501 Write Rank1 MR14 =0x16
3486 01:56:59.133005
3487 01:56:59.133395 Final TX Range 0 Vref 22
3488 01:56:59.133714
3489 01:56:59.138754 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
3490 01:56:59.139167
3491 01:56:59.145361 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3492 01:56:59.155855 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3493 01:56:59.162536 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3494 01:56:59.163052 Write Rank1 MR3 =0xb0
3495 01:56:59.165482 DramC Write-DBI on
3496 01:56:59.165896 ==
3497 01:56:59.168536 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3498 01:56:59.171896 fsp= 1, odt_onoff= 1, Byte mode= 0
3499 01:56:59.172308 ==
3500 01:56:59.178617 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
3501 01:56:59.179149
3502 01:56:59.179498 Begin, DQ Scan Range 699~763
3503 01:56:59.181751
3504 01:56:59.182157
3505 01:56:59.182478 TX Vref Scan disable
3506 01:56:59.185094 699 |2 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
3507 01:56:59.189036 700 |2 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
3508 01:56:59.192450 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
3509 01:56:59.195555 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
3510 01:56:59.198738 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
3511 01:56:59.201785 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
3512 01:56:59.209203 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
3513 01:56:59.212016 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
3514 01:56:59.215323 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
3515 01:56:59.218870 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
3516 01:56:59.222198 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
3517 01:56:59.225476 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
3518 01:56:59.228895 711 |2 6 7|[0] xxxxxxxx oooooooo [MSB]
3519 01:56:59.232060 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
3520 01:56:59.235429 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
3521 01:56:59.238717 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
3522 01:56:59.241879 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
3523 01:56:59.244940 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
3524 01:56:59.248628 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB]
3525 01:56:59.251925 718 |2 6 14|[0] xxxxxxxx oooooooo [MSB]
3526 01:56:59.260339 736 |2 6 32|[0] oooooooo xxxxxxxx [MSB]
3527 01:56:59.263019 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
3528 01:56:59.266557 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
3529 01:56:59.269934 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
3530 01:56:59.272988 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
3531 01:56:59.276933 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
3532 01:56:59.279754 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
3533 01:56:59.283368 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
3534 01:56:59.286719 744 |2 6 40|[0] xxxxxxxx xxxxxxxx [MSB]
3535 01:56:59.289972 Byte0, DQ PI dly=731, DQM PI dly= 731
3536 01:56:59.293172 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 27)
3537 01:56:59.293672
3538 01:56:59.299804 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 27)
3539 01:56:59.300329
3540 01:56:59.303441 Byte1, DQ PI dly=723, DQM PI dly= 723
3541 01:56:59.306617 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 19)
3542 01:56:59.307172
3543 01:56:59.309655 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 19)
3544 01:56:59.310116
3545 01:56:59.316928 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
3546 01:56:59.326529 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3547 01:56:59.333401 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3548 01:56:59.333916 Write Rank1 MR3 =0x30
3549 01:56:59.336628 DramC Write-DBI off
3550 01:56:59.337142
3551 01:56:59.337530 [DATLAT]
3552 01:56:59.339753 Freq=1600, CH1 RK1, use_rxtx_scan=0
3553 01:56:59.340264
3554 01:56:59.343510 DATLAT Default: 0x10
3555 01:56:59.344016 7, 0xFFFF, sum=0
3556 01:56:59.346123 8, 0xFFFF, sum=0
3557 01:56:59.346542 9, 0xFFFF, sum=0
3558 01:56:59.349748 10, 0xFFFF, sum=0
3559 01:56:59.350167 11, 0xFFFF, sum=0
3560 01:56:59.353134 12, 0xFFFF, sum=0
3561 01:56:59.353698 13, 0xFFFF, sum=0
3562 01:56:59.354036 14, 0x0, sum=1
3563 01:56:59.356184 15, 0x0, sum=2
3564 01:56:59.356605 16, 0x0, sum=3
3565 01:56:59.359917 17, 0x0, sum=4
3566 01:56:59.363237 pattern=2 first_step=14 total pass=5 best_step=16
3567 01:56:59.363653 ==
3568 01:56:59.369714 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3569 01:56:59.370217 fsp= 1, odt_onoff= 1, Byte mode= 0
3570 01:56:59.373012 ==
3571 01:56:59.376812 Start DQ dly to find pass range UseTestEngine =1
3572 01:56:59.379929 x-axis: bit #, y-axis: DQ dly (-127~63)
3573 01:56:59.380346 RX Vref Scan = 0
3574 01:56:59.383273 -26, [0] xxxxxxxx xxxxxxxx [MSB]
3575 01:56:59.386705 -25, [0] xxxxxxxx xxxxxxxx [MSB]
3576 01:56:59.390278 -24, [0] xxxxxxxx xxxxxxxx [MSB]
3577 01:56:59.393347 -23, [0] xxxxxxxx xxxxxxxx [MSB]
3578 01:56:59.396987 -22, [0] xxxxxxxx xxxxxxxx [MSB]
3579 01:56:59.399880 -21, [0] xxxxxxxx xxxxxxxx [MSB]
3580 01:56:59.403445 -20, [0] xxxxxxxx xxxxxxxx [MSB]
3581 01:56:59.403959 -19, [0] xxxxxxxx xxxxxxxx [MSB]
3582 01:56:59.406571 -18, [0] xxxxxxxx xxxxxxxx [MSB]
3583 01:56:59.409946 -17, [0] xxxxxxxx xxxxxxxx [MSB]
3584 01:56:59.413513 -16, [0] xxxxxxxx xxxxxxxx [MSB]
3585 01:56:59.416801 -15, [0] xxxxxxxx xxxxxxxx [MSB]
3586 01:56:59.419919 -14, [0] xxxxxxxx xxxxxxxx [MSB]
3587 01:56:59.423283 -13, [0] xxxxxxxx xxxxxxxx [MSB]
3588 01:56:59.426530 -12, [0] xxxxxxxx xxxxxxxx [MSB]
3589 01:56:59.427047 -11, [0] xxxxxxxx xxxxxxxx [MSB]
3590 01:56:59.429589 -10, [0] xxxxxxxx xxxxxxxx [MSB]
3591 01:56:59.433304 -9, [0] xxxxxxxx xxxxxxxx [MSB]
3592 01:56:59.436645 -8, [0] xxxxxxxx xxxxxxxx [MSB]
3593 01:56:59.439949 -7, [0] xxxxxxxx xxxxxxxx [MSB]
3594 01:56:59.443159 -6, [0] xxxxxxxx xxxxxxxx [MSB]
3595 01:56:59.446422 -5, [0] xxxxxxxx xxxxxxxx [MSB]
3596 01:56:59.446890 -4, [0] xxxxxxxx xxxxxxxx [MSB]
3597 01:56:59.449688 -3, [0] xxxxxxxx xxxxxxxx [MSB]
3598 01:56:59.453465 -2, [0] xxxoxxxx xxxxxxxx [MSB]
3599 01:56:59.456678 -1, [0] xxxoxxxx xxxxxxxx [MSB]
3600 01:56:59.460103 0, [0] xxxoxxxx xxxxxxxx [MSB]
3601 01:56:59.463343 1, [0] xxooxxxx xxxxxxxo [MSB]
3602 01:56:59.466709 2, [0] xxoooxxo ooxxxxxo [MSB]
3603 01:56:59.467273 3, [0] xxoooxxo oooxxooo [MSB]
3604 01:56:59.469494 4, [0] xxoooxxo ooooxooo [MSB]
3605 01:56:59.472992 5, [0] xoooooxo oooooooo [MSB]
3606 01:56:59.476714 6, [0] xoooooxo oooooooo [MSB]
3607 01:56:59.479968 7, [0] ooooooxo oooooooo [MSB]
3608 01:56:59.483250 8, [0] ooooooxo oooooooo [MSB]
3609 01:56:59.486786 33, [0] oooxoooo oooooooo [MSB]
3610 01:56:59.489590 34, [0] oooxoooo ooooooox [MSB]
3611 01:56:59.492957 35, [0] ooxxoooo ooxoooox [MSB]
3612 01:56:59.496587 36, [0] ooxxoooo ooxoooox [MSB]
3613 01:56:59.497009 37, [0] ooxxxoox oxxoooxx [MSB]
3614 01:56:59.499509 38, [0] ooxxxoox xxxooxxx [MSB]
3615 01:56:59.503477 39, [0] ooxxxoox xxxxoxxx [MSB]
3616 01:56:59.506930 40, [0] ooxxxoox xxxxoxxx [MSB]
3617 01:56:59.509669 41, [0] ooxxxxox xxxxxxxx [MSB]
3618 01:56:59.513357 42, [0] xxxxxxxx xxxxxxxx [MSB]
3619 01:56:59.516555 iDelay=42, Bit 0, Center 24 (7 ~ 41) 35
3620 01:56:59.519852 iDelay=42, Bit 1, Center 23 (5 ~ 41) 37
3621 01:56:59.523119 iDelay=42, Bit 2, Center 17 (1 ~ 34) 34
3622 01:56:59.526462 iDelay=42, Bit 3, Center 15 (-2 ~ 32) 35
3623 01:56:59.529591 iDelay=42, Bit 4, Center 19 (2 ~ 36) 35
3624 01:56:59.532755 iDelay=42, Bit 5, Center 22 (5 ~ 40) 36
3625 01:56:59.536246 iDelay=42, Bit 6, Center 25 (9 ~ 41) 33
3626 01:56:59.539452 iDelay=42, Bit 7, Center 19 (2 ~ 36) 35
3627 01:56:59.543218 iDelay=42, Bit 8, Center 19 (2 ~ 37) 36
3628 01:56:59.546316 iDelay=42, Bit 9, Center 19 (2 ~ 36) 35
3629 01:56:59.549809 iDelay=42, Bit 10, Center 18 (3 ~ 34) 32
3630 01:56:59.552916 iDelay=42, Bit 11, Center 21 (4 ~ 38) 35
3631 01:56:59.559766 iDelay=42, Bit 12, Center 22 (5 ~ 40) 36
3632 01:56:59.563003 iDelay=42, Bit 13, Center 20 (3 ~ 37) 35
3633 01:56:59.566391 iDelay=42, Bit 14, Center 19 (3 ~ 36) 34
3634 01:56:59.570259 iDelay=42, Bit 15, Center 17 (1 ~ 33) 33
3635 01:56:59.570995 ==
3636 01:56:59.573194 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3637 01:56:59.576392 fsp= 1, odt_onoff= 1, Byte mode= 0
3638 01:56:59.576897 ==
3639 01:56:59.579954 DQS Delay:
3640 01:56:59.580376 DQS0 = 0, DQS1 = 0
3641 01:56:59.580703 DQM Delay:
3642 01:56:59.583896 DQM0 = 20, DQM1 = 19
3643 01:56:59.584406 DQ Delay:
3644 01:56:59.586773 DQ0 =24, DQ1 =23, DQ2 =17, DQ3 =15
3645 01:56:59.589837 DQ4 =19, DQ5 =22, DQ6 =25, DQ7 =19
3646 01:56:59.593478 DQ8 =19, DQ9 =19, DQ10 =18, DQ11 =21
3647 01:56:59.596660 DQ12 =22, DQ13 =20, DQ14 =19, DQ15 =17
3648 01:56:59.597177
3649 01:56:59.597712
3650 01:56:59.598041
3651 01:56:59.599787 [DramC_TX_OE_Calibration] TA2
3652 01:56:59.603491 Original DQ_B0 (3 6) =30, OEN = 27
3653 01:56:59.606150 Original DQ_B1 (3 6) =30, OEN = 27
3654 01:56:59.609812 23, 0x0, End_B0=23 End_B1=23
3655 01:56:59.612865 24, 0x0, End_B0=24 End_B1=24
3656 01:56:59.613321 25, 0x0, End_B0=25 End_B1=25
3657 01:56:59.617047 26, 0x0, End_B0=26 End_B1=26
3658 01:56:59.619652 27, 0x0, End_B0=27 End_B1=27
3659 01:56:59.623237 28, 0x0, End_B0=28 End_B1=28
3660 01:56:59.626321 29, 0x0, End_B0=29 End_B1=29
3661 01:56:59.626839 30, 0x0, End_B0=30 End_B1=30
3662 01:56:59.629727 31, 0xFFFF, End_B0=30 End_B1=30
3663 01:56:59.636414 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3664 01:56:59.639724 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3665 01:56:59.642957
3666 01:56:59.643367
3667 01:56:59.643690 Write Rank1 MR23 =0x3f
3668 01:56:59.643994 [DQSOSC]
3669 01:56:59.652971 [DQSOSCAuto] RK1, (LSB)MR18= 0xb3, (MSB)MR19= 0x3, tDQSOscB0 = 332 ps tDQSOscB1 = 0 ps
3670 01:56:59.656620 CH1_RK1: MR19=0x3, MR18=0xB3, DQSOSC=332, MR23=63, INC=22, DEC=33
3671 01:56:59.659487 Write Rank1 MR23 =0x3f
3672 01:56:59.659993 [DQSOSC]
3673 01:56:59.669491 [DQSOSCAuto] RK1, (LSB)MR18= 0xb3, (MSB)MR19= 0x3, tDQSOscB0 = 332 ps tDQSOscB1 = 0 ps
3674 01:56:59.670004 CH1 RK1: MR19=3, MR18=B3
3675 01:56:59.672651 [RxdqsGatingPostProcess] freq 1600
3676 01:56:59.679283 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
3677 01:56:59.679783 Rank: 0
3678 01:56:59.682723 best DQS0 dly(2T, 0.5T) = (2, 5)
3679 01:56:59.686205 best DQS1 dly(2T, 0.5T) = (2, 5)
3680 01:56:59.689424 best DQS0 P1 dly(2T, 0.5T) = (3, 1)
3681 01:56:59.693141 best DQS1 P1 dly(2T, 0.5T) = (3, 1)
3682 01:56:59.693742 Rank: 1
3683 01:56:59.696477 best DQS0 dly(2T, 0.5T) = (2, 5)
3684 01:56:59.699241 best DQS1 dly(2T, 0.5T) = (2, 5)
3685 01:56:59.702982 best DQS0 P1 dly(2T, 0.5T) = (3, 1)
3686 01:56:59.706057 best DQS1 P1 dly(2T, 0.5T) = (3, 1)
3687 01:56:59.709746 TX_dly_DQSgated check: min 2 max 3, ChangeDQSINCTL=-1
3688 01:56:59.712995 DQSINCTL=5, RANKINCTL=3, u4XRTR2R=9
3689 01:56:59.720010 [DualRankRxdatlatCal] RK0: 16, RK1: 16, Final_Datlat 16
3690 01:56:59.720520
3691 01:56:59.720848
3692 01:56:59.723144 [Calibration Summary] Freqency 1600
3693 01:56:59.723695 CH 0, Rank 0
3694 01:56:59.724056 All Pass.
3695 01:56:59.724389
3696 01:56:59.726548 CH 0, Rank 1
3697 01:56:59.727098 All Pass.
3698 01:56:59.727454
3699 01:56:59.727785 CH 1, Rank 0
3700 01:56:59.729347 All Pass.
3701 01:56:59.729800
3702 01:56:59.730155 CH 1, Rank 1
3703 01:56:59.730485 All Pass.
3704 01:56:59.730805
3705 01:56:59.736591 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3706 01:56:59.743168 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3707 01:56:59.753083 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3708 01:56:59.753655 Write Rank0 MR3 =0xb0
3709 01:56:59.759565 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3710 01:56:59.766440 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3711 01:56:59.772994 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3712 01:56:59.776854 Write Rank1 MR3 =0xb0
3713 01:56:59.782638 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3714 01:56:59.789842 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3715 01:56:59.795920 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3716 01:56:59.799699 Write Rank0 MR3 =0xb0
3717 01:56:59.805997 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3718 01:56:59.812873 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3719 01:56:59.819565 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3720 01:56:59.820114 Write Rank1 MR3 =0xb0
3721 01:56:59.823191 DramC Write-DBI on
3722 01:56:59.826092 [GetDramInforAfterCalByMRR] Vendor 1.
3723 01:56:59.829421 [GetDramInforAfterCalByMRR] Revision 7.
3724 01:56:59.829966 MR8 12
3725 01:56:59.835958 CH0, RK0, DieNum 1, Density 80000000, RKsize 80000000.
3726 01:56:59.836502 MR8 12
3727 01:56:59.839578 CH0, RK1, DieNum 1, Density 80000000, RKsize 80000000.
3728 01:56:59.842594 MR8 12
3729 01:56:59.846203 CH1, RK0, DieNum 1, Density 80000000, RKsize 80000000.
3730 01:56:59.846746 MR8 12
3731 01:56:59.852123 CH1, RK1, DieNum 1, Density 80000000, RKsize 80000000.
3732 01:56:59.859524 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 119, TRFCpb 44, TRFCpb_05T 0
3733 01:56:59.862277 Write Rank0 MR13 =0xd0
3734 01:56:59.865688 Write Rank1 MR13 =0xd0
3735 01:56:59.866187 Write Rank0 MR13 =0xd0
3736 01:56:59.869069 Write Rank1 MR13 =0xd0
3737 01:56:59.872620 Save calibration result to emmc
3738 01:56:59.873060
3739 01:56:59.873494
3740 01:56:59.875922 [DramcModeReg_Check] Freq_1600, FSP_1
3741 01:56:59.876331 FSP_1, CH_0, RK0
3742 01:56:59.879255 Write Rank0 MR13 =0xd8
3743 01:56:59.882657 MR12 = 0x56 (global = 0x56) match
3744 01:56:59.885887 MR14 = 0x18 (global = 0x18) match
3745 01:56:59.886357 FSP_1, CH_0, RK1
3746 01:56:59.889331 Write Rank1 MR13 =0xd8
3747 01:56:59.892491 MR12 = 0x56 (global = 0x56) match
3748 01:56:59.895895 MR14 = 0x16 (global = 0x16) match
3749 01:56:59.896511 FSP_1, CH_1, RK0
3750 01:56:59.898951 Write Rank0 MR13 =0xd8
3751 01:56:59.902978 MR12 = 0x56 (global = 0x56) match
3752 01:56:59.905823 MR14 = 0x16 (global = 0x16) match
3753 01:56:59.906285 FSP_1, CH_1, RK1
3754 01:56:59.909076 Write Rank1 MR13 =0xd8
3755 01:56:59.912373 MR12 = 0x56 (global = 0x56) match
3756 01:56:59.915726 MR14 = 0x16 (global = 0x16) match
3757 01:56:59.916142
3758 01:56:59.919538 [MEM_TEST] 02: After DFS, before run time config
3759 01:56:59.930541 [MEM_TEST] Rank 0 OK.(uiFixedAddr 0x40000000, Pass count =16384, Fail count =0)
3760 01:56:59.931034
3761 01:56:59.931448 [TA2_TEST]
3762 01:56:59.931763 === TA2 HW
3763 01:56:59.933914 TA2 PAT: XTALK
3764 01:56:59.937099 HW channel(0) Rank(0), TA2 pass, pass_cnt:1, err_cnt:0
3765 01:56:59.943719 HW channel(0) Rank(1), TA2 pass, pass_cnt:2, err_cnt:0
3766 01:56:59.947069 HW channel(1) Rank(0), TA2 pass, pass_cnt:3, err_cnt:0
3767 01:56:59.954039 HW channel(1) Rank(1), TA2 pass, pass_cnt:4, err_cnt:0
3768 01:56:59.954487
3769 01:56:59.954810
3770 01:56:59.955113 Settings after calibration
3771 01:56:59.955405
3772 01:56:59.957464 [DramcRunTimeConfig]
3773 01:56:59.960426 TransferPLLToSPMControl - MODE SW PHYPLL
3774 01:56:59.960839 TX_TRACKING: ON
3775 01:56:59.963601 RX_TRACKING: ON
3776 01:56:59.964095 HW_GATING: ON
3777 01:56:59.966909 HW_GATING DBG: OFF
3778 01:56:59.967317 ddr_geometry:1
3779 01:56:59.970485 ddr_geometry:1
3780 01:56:59.971010 ddr_geometry:1
3781 01:56:59.973778 ddr_geometry:1
3782 01:56:59.974184 ddr_geometry:1
3783 01:56:59.974551 ddr_geometry:1
3784 01:56:59.976808 ddr_geometry:1
3785 01:56:59.977359 ddr_geometry:1
3786 01:56:59.980683 High Freq DUMMY_READ_FOR_TRACKING: ON
3787 01:56:59.983618 ZQCS_ENABLE_LP4: OFF
3788 01:56:59.986936 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
3789 01:56:59.990166 DUMMY_READ_FOR_DQS_GATING_RETRY: OFF
3790 01:56:59.990584 SPM_CONTROL_AFTERK: ON
3791 01:56:59.993414 IMPEDANCE_TRACKING: ON
3792 01:56:59.993833 TEMP_SENSOR: ON
3793 01:56:59.996868 PER_BANK_REFRESH: ON
3794 01:56:59.997424 HW_SAVE_FOR_SR: ON
3795 01:57:00.003428 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3796 01:57:00.003883 CLK_FREE_FUN_FOR_DRAMC_PSEL: ON
3797 01:57:00.006538 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: ON
3798 01:57:00.010278 Read ODT Tracking: ON
3799 01:57:00.013172 =========================
3800 01:57:00.013641
3801 01:57:00.013976 [TA2_TEST]
3802 01:57:00.014285 === TA2 HW
3803 01:57:00.020111 HW channel(0) Rank(0), TA2 pass, pass_cnt:5, err_cnt:0
3804 01:57:00.023260 HW channel(0) Rank(1), TA2 pass, pass_cnt:6, err_cnt:0
3805 01:57:00.030132 HW channel(1) Rank(0), TA2 pass, pass_cnt:7, err_cnt:0
3806 01:57:00.033295 HW channel(1) Rank(1), TA2 pass, pass_cnt:8, err_cnt:0
3807 01:57:00.033722
3808 01:57:00.036590 [MEM_TEST] 03: After run time config
3809 01:57:00.048883 [MEM_TEST] Rank 0 OK.(uiFixedAddr 0x40000000, Pass count =16384, Fail count =0)
3810 01:57:00.051546 [complex_mem_test] start addr:0x40024000, len:131072
3811 01:57:00.255883 1st complex R/W mem test pass
3812 01:57:00.262312 save_calibration_params with freq_sel:1, frequency:1600, _MappingFreqArray:0
3813 01:57:00.265654 sync preloader write leveling
3814 01:57:00.269604 sync preloader cbt_mr12
3815 01:57:00.272573 sync preloader cbt_clk_dly
3816 01:57:00.272987 sync preloader cbt_cmd_dly
3817 01:57:00.275775 sync preloader cbt_cs
3818 01:57:00.279316 sync preloader cbt_ca_perbit_delay
3819 01:57:00.279826 sync preloader clk_delay
3820 01:57:00.282417 sync preloader dqs_delay
3821 01:57:00.285873 sync preloader u1Gating2T_Save
3822 01:57:00.289190 sync preloader u1Gating05T_Save
3823 01:57:00.292808 sync preloader u1Gatingfine_tune_Save
3824 01:57:00.296308 sync preloader u1Gatingucpass_count_Save
3825 01:57:00.299548 sync preloader u1TxWindowPerbitVref_Save
3826 01:57:00.302504 sync preloader u1TxCenter_min_Save
3827 01:57:00.306398 sync preloader u1TxCenter_max_Save
3828 01:57:00.309480 sync preloader u1Txwin_center_Save
3829 01:57:00.312549 sync preloader u1Txfirst_pass_Save
3830 01:57:00.315925 sync preloader u1Txlast_pass_Save
3831 01:57:00.316525 sync preloader u1RxDatlat_Save
3832 01:57:00.319364 sync preloader u1RxWinPerbitVref_Save
3833 01:57:00.326179 sync preloader u1RxWinPerbitDQ_firsbypass_Save
3834 01:57:00.329104 sync preloader u1RxWinPerbitDQ_lastbypass_Save
3835 01:57:00.332755 sync preloader delay_cell_unit
3836 01:57:00.339436 save_calibration_params with freq_sel:3, frequency:1200, _MappingFreqArray:1
3837 01:57:00.342763 sync preloader write leveling
3838 01:57:00.343218 sync preloader cbt_mr12
3839 01:57:00.345969 sync preloader cbt_clk_dly
3840 01:57:00.349314 sync preloader cbt_cmd_dly
3841 01:57:00.349868 sync preloader cbt_cs
3842 01:57:00.352931 sync preloader cbt_ca_perbit_delay
3843 01:57:00.355650 sync preloader clk_delay
3844 01:57:00.359300 sync preloader dqs_delay
3845 01:57:00.359851 sync preloader u1Gating2T_Save
3846 01:57:00.362516 sync preloader u1Gating05T_Save
3847 01:57:00.365766 sync preloader u1Gatingfine_tune_Save
3848 01:57:00.368870 sync preloader u1Gatingucpass_count_Save
3849 01:57:00.375723 sync preloader u1TxWindowPerbitVref_Save
3850 01:57:00.376174 sync preloader u1TxCenter_min_Save
3851 01:57:00.379327 sync preloader u1TxCenter_max_Save
3852 01:57:00.382156 sync preloader u1Txwin_center_Save
3853 01:57:00.385906 sync preloader u1Txfirst_pass_Save
3854 01:57:00.389176 sync preloader u1Txlast_pass_Save
3855 01:57:00.392665 sync preloader u1RxDatlat_Save
3856 01:57:00.395922 sync preloader u1RxWinPerbitVref_Save
3857 01:57:00.398665 sync preloader u1RxWinPerbitDQ_firsbypass_Save
3858 01:57:00.402307 sync preloader u1RxWinPerbitDQ_lastbypass_Save
3859 01:57:00.405688 sync preloader delay_cell_unit
3860 01:57:00.412239 save_calibration_params with freq_sel:5, frequency:800, _MappingFreqArray:2
3861 01:57:00.415492 sync preloader write leveling
3862 01:57:00.419091 sync preloader cbt_mr12
3863 01:57:00.422117 sync preloader cbt_clk_dly
3864 01:57:00.422669 sync preloader cbt_cmd_dly
3865 01:57:00.425207 sync preloader cbt_cs
3866 01:57:00.428708 sync preloader cbt_ca_perbit_delay
3867 01:57:00.429253 sync preloader clk_delay
3868 01:57:00.431863 sync preloader dqs_delay
3869 01:57:00.435125 sync preloader u1Gating2T_Save
3870 01:57:00.438543 sync preloader u1Gating05T_Save
3871 01:57:00.441854 sync preloader u1Gatingfine_tune_Save
3872 01:57:00.445688 sync preloader u1Gatingucpass_count_Save
3873 01:57:00.448882 sync preloader u1TxWindowPerbitVref_Save
3874 01:57:00.451833 sync preloader u1TxCenter_min_Save
3875 01:57:00.455509 sync preloader u1TxCenter_max_Save
3876 01:57:00.458775 sync preloader u1Txwin_center_Save
3877 01:57:00.462076 sync preloader u1Txfirst_pass_Save
3878 01:57:00.465548 sync preloader u1Txlast_pass_Save
3879 01:57:00.466101 sync preloader u1RxDatlat_Save
3880 01:57:00.468628 sync preloader u1RxWinPerbitVref_Save
3881 01:57:00.475439 sync preloader u1RxWinPerbitDQ_firsbypass_Save
3882 01:57:00.478906 sync preloader u1RxWinPerbitDQ_lastbypass_Save
3883 01:57:00.481906 sync preloader delay_cell_unit
3884 01:57:00.485058 just_for_test_dump_coreboot_params dump all params
3885 01:57:00.488654 dump source = 0x0
3886 01:57:00.489204 dump params frequency:1600
3887 01:57:00.492280 dump params rank number:2
3888 01:57:00.492788
3889 01:57:00.495337 dump params write leveling
3890 01:57:00.498680 write leveling[0][0][0] = 0x20
3891 01:57:00.499140 write leveling[0][0][1] = 0x1c
3892 01:57:00.501751 write leveling[0][1][0] = 0x22
3893 01:57:00.505233 write leveling[0][1][1] = 0x1f
3894 01:57:00.508362 write leveling[1][0][0] = 0x24
3895 01:57:00.512190 write leveling[1][0][1] = 0x1f
3896 01:57:00.515237 write leveling[1][1][0] = 0x23
3897 01:57:00.515789 write leveling[1][1][1] = 0x20
3898 01:57:00.518733 dump params cbt_cs
3899 01:57:00.522220 cbt_cs[0][0] = 0xa
3900 01:57:00.522773 cbt_cs[0][1] = 0xa
3901 01:57:00.525451 cbt_cs[1][0] = 0xb
3902 01:57:00.525999 cbt_cs[1][1] = 0xb
3903 01:57:00.529157 dump params cbt_mr12
3904 01:57:00.529749 cbt_mr12[0][0] = 0x16
3905 01:57:00.531750 cbt_mr12[0][1] = 0x16
3906 01:57:00.532205 cbt_mr12[1][0] = 0x16
3907 01:57:00.535464 cbt_mr12[1][1] = 0x16
3908 01:57:00.538574 dump params tx window
3909 01:57:00.539116 tx_center_min[0][0][0] = 979
3910 01:57:00.542016 tx_center_max[0][0][0] = 985
3911 01:57:00.545700 tx_center_min[0][0][1] = 974
3912 01:57:00.548422 tx_center_max[0][0][1] = 979
3913 01:57:00.551798 tx_center_min[0][1][0] = 982
3914 01:57:00.552341 tx_center_max[0][1][0] = 989
3915 01:57:00.555557 tx_center_min[0][1][1] = 979
3916 01:57:00.558631 tx_center_max[0][1][1] = 985
3917 01:57:00.561949 tx_center_min[1][0][0] = 983
3918 01:57:00.565307 tx_center_max[1][0][0] = 989
3919 01:57:00.565879 tx_center_min[1][0][1] = 976
3920 01:57:00.568728 tx_center_max[1][0][1] = 980
3921 01:57:00.571741 tx_center_min[1][1][0] = 982
3922 01:57:00.574946 tx_center_max[1][1][0] = 989
3923 01:57:00.575405 tx_center_min[1][1][1] = 977
3924 01:57:00.578406 tx_center_max[1][1][1] = 981
3925 01:57:00.582014 dump params tx window
3926 01:57:00.584989 tx_win_center[0][0][0] = 985
3927 01:57:00.585542 tx_first_pass[0][0][0] = 973
3928 01:57:00.588614 tx_last_pass[0][0][0] = 997
3929 01:57:00.592464 tx_win_center[0][0][1] = 983
3930 01:57:00.595132 tx_first_pass[0][0][1] = 972
3931 01:57:00.598161 tx_last_pass[0][0][1] = 995
3932 01:57:00.598577 tx_win_center[0][0][2] = 983
3933 01:57:00.601871 tx_first_pass[0][0][2] = 972
3934 01:57:00.604855 tx_last_pass[0][0][2] = 995
3935 01:57:00.608964 tx_win_center[0][0][3] = 979
3936 01:57:00.609523 tx_first_pass[0][0][3] = 967
3937 01:57:00.611598 tx_last_pass[0][0][3] = 991
3938 01:57:00.614811 tx_win_center[0][0][4] = 984
3939 01:57:00.618374 tx_first_pass[0][0][4] = 972
3940 01:57:00.621706 tx_last_pass[0][0][4] = 996
3941 01:57:00.622212 tx_win_center[0][0][5] = 979
3942 01:57:00.625456 tx_first_pass[0][0][5] = 968
3943 01:57:00.628687 tx_last_pass[0][0][5] = 991
3944 01:57:00.631986 tx_win_center[0][0][6] = 980
3945 01:57:00.632497 tx_first_pass[0][0][6] = 968
3946 01:57:00.634941 tx_last_pass[0][0][6] = 992
3947 01:57:00.638629 tx_win_center[0][0][7] = 981
3948 01:57:00.642189 tx_first_pass[0][0][7] = 970
3949 01:57:00.642711 tx_last_pass[0][0][7] = 993
3950 01:57:00.645358 tx_win_center[0][0][8] = 974
3951 01:57:00.648196 tx_first_pass[0][0][8] = 962
3952 01:57:00.651472 tx_last_pass[0][0][8] = 986
3953 01:57:00.654965 tx_win_center[0][0][9] = 975
3954 01:57:00.655516 tx_first_pass[0][0][9] = 963
3955 01:57:00.658379 tx_last_pass[0][0][9] = 988
3956 01:57:00.661924 tx_win_center[0][0][10] = 979
3957 01:57:00.665653 tx_first_pass[0][0][10] = 968
3958 01:57:00.668637 tx_last_pass[0][0][10] = 991
3959 01:57:00.669189 tx_win_center[0][0][11] = 975
3960 01:57:00.671699 tx_first_pass[0][0][11] = 962
3961 01:57:00.675001 tx_last_pass[0][0][11] = 988
3962 01:57:00.678349 tx_win_center[0][0][12] = 976
3963 01:57:00.681427 tx_first_pass[0][0][12] = 963
3964 01:57:00.681893 tx_last_pass[0][0][12] = 989
3965 01:57:00.685821 tx_win_center[0][0][13] = 974
3966 01:57:00.688591 tx_first_pass[0][0][13] = 962
3967 01:57:00.691875 tx_last_pass[0][0][13] = 987
3968 01:57:00.695086 tx_win_center[0][0][14] = 976
3969 01:57:00.695548 tx_first_pass[0][0][14] = 964
3970 01:57:00.698061 tx_last_pass[0][0][14] = 988
3971 01:57:00.701694 tx_win_center[0][0][15] = 978
3972 01:57:00.705046 tx_first_pass[0][0][15] = 967
3973 01:57:00.708190 tx_last_pass[0][0][15] = 990
3974 01:57:00.708647 tx_win_center[0][1][0] = 989
3975 01:57:00.711901 tx_first_pass[0][1][0] = 977
3976 01:57:00.714754 tx_last_pass[0][1][0] = 1001
3977 01:57:00.718812 tx_win_center[0][1][1] = 988
3978 01:57:00.721377 tx_first_pass[0][1][1] = 977
3979 01:57:00.721834 tx_last_pass[0][1][1] = 1000
3980 01:57:00.725225 tx_win_center[0][1][2] = 988
3981 01:57:00.728376 tx_first_pass[0][1][2] = 977
3982 01:57:00.731972 tx_last_pass[0][1][2] = 1000
3983 01:57:00.732527 tx_win_center[0][1][3] = 982
3984 01:57:00.734824 tx_first_pass[0][1][3] = 969
3985 01:57:00.738212 tx_last_pass[0][1][3] = 995
3986 01:57:00.741605 tx_win_center[0][1][4] = 988
3987 01:57:00.744826 tx_first_pass[0][1][4] = 976
3988 01:57:00.745241 tx_last_pass[0][1][4] = 1000
3989 01:57:00.748519 tx_win_center[0][1][5] = 982
3990 01:57:00.751599 tx_first_pass[0][1][5] = 971
3991 01:57:00.755492 tx_last_pass[0][1][5] = 994
3992 01:57:00.756007 tx_win_center[0][1][6] = 984
3993 01:57:00.758392 tx_first_pass[0][1][6] = 971
3994 01:57:00.762306 tx_last_pass[0][1][6] = 998
3995 01:57:00.765709 tx_win_center[0][1][7] = 986
3996 01:57:00.768645 tx_first_pass[0][1][7] = 974
3997 01:57:00.769200 tx_last_pass[0][1][7] = 998
3998 01:57:00.772309 tx_win_center[0][1][8] = 979
3999 01:57:00.775057 tx_first_pass[0][1][8] = 968
4000 01:57:00.778246 tx_last_pass[0][1][8] = 991
4001 01:57:00.778727 tx_win_center[0][1][9] = 980
4002 01:57:00.781381 tx_first_pass[0][1][9] = 969
4003 01:57:00.785077 tx_last_pass[0][1][9] = 992
4004 01:57:00.788630 tx_win_center[0][1][10] = 985
4005 01:57:00.792527 tx_first_pass[0][1][10] = 974
4006 01:57:00.793092 tx_last_pass[0][1][10] = 997
4007 01:57:00.795355 tx_win_center[0][1][11] = 979
4008 01:57:00.798469 tx_first_pass[0][1][11] = 968
4009 01:57:00.801816 tx_last_pass[0][1][11] = 991
4010 01:57:00.805157 tx_win_center[0][1][12] = 980
4011 01:57:00.805657 tx_first_pass[0][1][12] = 969
4012 01:57:00.808303 tx_last_pass[0][1][12] = 992
4013 01:57:00.812479 tx_win_center[0][1][13] = 979
4014 01:57:00.814874 tx_first_pass[0][1][13] = 968
4015 01:57:00.818216 tx_last_pass[0][1][13] = 991
4016 01:57:00.818771 tx_win_center[0][1][14] = 980
4017 01:57:00.821519 tx_first_pass[0][1][14] = 969
4018 01:57:00.825287 tx_last_pass[0][1][14] = 992
4019 01:57:00.828526 tx_win_center[0][1][15] = 982
4020 01:57:00.831887 tx_first_pass[0][1][15] = 971
4021 01:57:00.832441 tx_last_pass[0][1][15] = 994
4022 01:57:00.834671 tx_win_center[1][0][0] = 989
4023 01:57:00.838082 tx_first_pass[1][0][0] = 977
4024 01:57:00.841902 tx_last_pass[1][0][0] = 1002
4025 01:57:00.844975 tx_win_center[1][0][1] = 988
4026 01:57:00.845564 tx_first_pass[1][0][1] = 976
4027 01:57:00.848091 tx_last_pass[1][0][1] = 1000
4028 01:57:00.851454 tx_win_center[1][0][2] = 986
4029 01:57:00.854868 tx_first_pass[1][0][2] = 974
4030 01:57:00.855421 tx_last_pass[1][0][2] = 998
4031 01:57:00.858204 tx_win_center[1][0][3] = 983
4032 01:57:00.861218 tx_first_pass[1][0][3] = 971
4033 01:57:00.864829 tx_last_pass[1][0][3] = 995
4034 01:57:00.868554 tx_win_center[1][0][4] = 987
4035 01:57:00.869064 tx_first_pass[1][0][4] = 975
4036 01:57:00.871145 tx_last_pass[1][0][4] = 999
4037 01:57:00.874712 tx_win_center[1][0][5] = 989
4038 01:57:00.878084 tx_first_pass[1][0][5] = 977
4039 01:57:00.878502 tx_last_pass[1][0][5] = 1001
4040 01:57:00.881291 tx_win_center[1][0][6] = 989
4041 01:57:00.884749 tx_first_pass[1][0][6] = 977
4042 01:57:00.888176 tx_last_pass[1][0][6] = 1001
4043 01:57:00.891404 tx_win_center[1][0][7] = 986
4044 01:57:00.891917 tx_first_pass[1][0][7] = 975
4045 01:57:00.894795 tx_last_pass[1][0][7] = 998
4046 01:57:00.897775 tx_win_center[1][0][8] = 978
4047 01:57:00.901086 tx_first_pass[1][0][8] = 966
4048 01:57:00.905008 tx_last_pass[1][0][8] = 991
4049 01:57:00.905587 tx_win_center[1][0][9] = 978
4050 01:57:00.908283 tx_first_pass[1][0][9] = 966
4051 01:57:00.911641 tx_last_pass[1][0][9] = 991
4052 01:57:00.914747 tx_win_center[1][0][10] = 979
4053 01:57:00.917637 tx_first_pass[1][0][10] = 967
4054 01:57:00.918171 tx_last_pass[1][0][10] = 991
4055 01:57:00.921105 tx_win_center[1][0][11] = 980
4056 01:57:00.924658 tx_first_pass[1][0][11] = 969
4057 01:57:00.927542 tx_last_pass[1][0][11] = 992
4058 01:57:00.931167 tx_win_center[1][0][12] = 980
4059 01:57:00.931677 tx_first_pass[1][0][12] = 968
4060 01:57:00.934319 tx_last_pass[1][0][12] = 992
4061 01:57:00.938198 tx_win_center[1][0][13] = 979
4062 01:57:00.940962 tx_first_pass[1][0][13] = 968
4063 01:57:00.945110 tx_last_pass[1][0][13] = 991
4064 01:57:00.945712 tx_win_center[1][0][14] = 979
4065 01:57:00.948640 tx_first_pass[1][0][14] = 968
4066 01:57:00.951228 tx_last_pass[1][0][14] = 991
4067 01:57:00.954927 tx_win_center[1][0][15] = 976
4068 01:57:00.957840 tx_first_pass[1][0][15] = 964
4069 01:57:00.958417 tx_last_pass[1][0][15] = 988
4070 01:57:00.961111 tx_win_center[1][1][0] = 989
4071 01:57:00.964856 tx_first_pass[1][1][0] = 977
4072 01:57:00.967736 tx_last_pass[1][1][0] = 1001
4073 01:57:00.968197 tx_win_center[1][1][1] = 988
4074 01:57:00.971081 tx_first_pass[1][1][1] = 977
4075 01:57:00.974362 tx_last_pass[1][1][1] = 1000
4076 01:57:00.977580 tx_win_center[1][1][2] = 984
4077 01:57:00.981292 tx_first_pass[1][1][2] = 973
4078 01:57:00.981815 tx_last_pass[1][1][2] = 996
4079 01:57:00.984676 tx_win_center[1][1][3] = 982
4080 01:57:00.987892 tx_first_pass[1][1][3] = 970
4081 01:57:00.991253 tx_last_pass[1][1][3] = 995
4082 01:57:00.991762 tx_win_center[1][1][4] = 986
4083 01:57:00.994295 tx_first_pass[1][1][4] = 974
4084 01:57:00.998226 tx_last_pass[1][1][4] = 998
4085 01:57:01.001116 tx_win_center[1][1][5] = 988
4086 01:57:01.004423 tx_first_pass[1][1][5] = 976
4087 01:57:01.004945 tx_last_pass[1][1][5] = 1000
4088 01:57:01.007401 tx_win_center[1][1][6] = 988
4089 01:57:01.010700 tx_first_pass[1][1][6] = 976
4090 01:57:01.014224 tx_last_pass[1][1][6] = 1001
4091 01:57:01.017319 tx_win_center[1][1][7] = 986
4092 01:57:01.017737 tx_first_pass[1][1][7] = 975
4093 01:57:01.021180 tx_last_pass[1][1][7] = 997
4094 01:57:01.024148 tx_win_center[1][1][8] = 980
4095 01:57:01.027766 tx_first_pass[1][1][8] = 969
4096 01:57:01.028281 tx_last_pass[1][1][8] = 991
4097 01:57:01.030969 tx_win_center[1][1][9] = 979
4098 01:57:01.033914 tx_first_pass[1][1][9] = 968
4099 01:57:01.037590 tx_last_pass[1][1][9] = 991
4100 01:57:01.040887 tx_win_center[1][1][10] = 979
4101 01:57:01.041420 tx_first_pass[1][1][10] = 968
4102 01:57:01.044463 tx_last_pass[1][1][10] = 991
4103 01:57:01.047561 tx_win_center[1][1][11] = 981
4104 01:57:01.050777 tx_first_pass[1][1][11] = 970
4105 01:57:01.053968 tx_last_pass[1][1][11] = 993
4106 01:57:01.054386 tx_win_center[1][1][12] = 980
4107 01:57:01.057657 tx_first_pass[1][1][12] = 969
4108 01:57:01.060709 tx_last_pass[1][1][12] = 992
4109 01:57:01.064300 tx_win_center[1][1][13] = 981
4110 01:57:01.067268 tx_first_pass[1][1][13] = 970
4111 01:57:01.067707 tx_last_pass[1][1][13] = 992
4112 01:57:01.070644 tx_win_center[1][1][14] = 980
4113 01:57:01.073886 tx_first_pass[1][1][14] = 969
4114 01:57:01.077427 tx_last_pass[1][1][14] = 992
4115 01:57:01.080922 tx_win_center[1][1][15] = 977
4116 01:57:01.081369 tx_first_pass[1][1][15] = 966
4117 01:57:01.084217 tx_last_pass[1][1][15] = 989
4118 01:57:01.087339 dump params rx window
4119 01:57:01.087755 rx_firspass[0][0][0] = 9
4120 01:57:01.091033 rx_lastpass[0][0][0] = 42
4121 01:57:01.093790 rx_firspass[0][0][1] = 8
4122 01:57:01.097512 rx_lastpass[0][0][1] = 40
4123 01:57:01.098014 rx_firspass[0][0][2] = 9
4124 01:57:01.100839 rx_lastpass[0][0][2] = 39
4125 01:57:01.104324 rx_firspass[0][0][3] = -1
4126 01:57:01.104827 rx_lastpass[0][0][3] = 31
4127 01:57:01.107754 rx_firspass[0][0][4] = 7
4128 01:57:01.110508 rx_lastpass[0][0][4] = 39
4129 01:57:01.113846 rx_firspass[0][0][5] = 3
4130 01:57:01.114354 rx_lastpass[0][0][5] = 29
4131 01:57:01.117829 rx_firspass[0][0][6] = 2
4132 01:57:01.120791 rx_lastpass[0][0][6] = 32
4133 01:57:01.121367 rx_firspass[0][0][7] = 4
4134 01:57:01.124154 rx_lastpass[0][0][7] = 34
4135 01:57:01.127198 rx_firspass[0][0][8] = 2
4136 01:57:01.127708 rx_lastpass[0][0][8] = 34
4137 01:57:01.130823 rx_firspass[0][0][9] = 5
4138 01:57:01.134193 rx_lastpass[0][0][9] = 35
4139 01:57:01.137389 rx_firspass[0][0][10] = 9
4140 01:57:01.137929 rx_lastpass[0][0][10] = 38
4141 01:57:01.140654 rx_firspass[0][0][11] = 3
4142 01:57:01.143937 rx_lastpass[0][0][11] = 31
4143 01:57:01.144448 rx_firspass[0][0][12] = 5
4144 01:57:01.147254 rx_lastpass[0][0][12] = 34
4145 01:57:01.150576 rx_firspass[0][0][13] = 1
4146 01:57:01.154018 rx_lastpass[0][0][13] = 32
4147 01:57:01.154530 rx_firspass[0][0][14] = 3
4148 01:57:01.157329 rx_lastpass[0][0][14] = 33
4149 01:57:01.160725 rx_firspass[0][0][15] = 4
4150 01:57:01.163805 rx_lastpass[0][0][15] = 35
4151 01:57:01.164312 rx_firspass[0][1][0] = 9
4152 01:57:01.167095 rx_lastpass[0][1][0] = 43
4153 01:57:01.170118 rx_firspass[0][1][1] = 7
4154 01:57:01.170532 rx_lastpass[0][1][1] = 42
4155 01:57:01.173753 rx_firspass[0][1][2] = 7
4156 01:57:01.176966 rx_lastpass[0][1][2] = 42
4157 01:57:01.177415 rx_firspass[0][1][3] = -2
4158 01:57:01.180384 rx_lastpass[0][1][3] = 33
4159 01:57:01.183587 rx_firspass[0][1][4] = 5
4160 01:57:01.187384 rx_lastpass[0][1][4] = 40
4161 01:57:01.187798 rx_firspass[0][1][5] = 1
4162 01:57:01.190412 rx_lastpass[0][1][5] = 34
4163 01:57:01.193729 rx_firspass[0][1][6] = 2
4164 01:57:01.194141 rx_lastpass[0][1][6] = 35
4165 01:57:01.197104 rx_firspass[0][1][7] = 2
4166 01:57:01.200461 rx_lastpass[0][1][7] = 36
4167 01:57:01.200974 rx_firspass[0][1][8] = 0
4168 01:57:01.203557 rx_lastpass[0][1][8] = 36
4169 01:57:01.206650 rx_firspass[0][1][9] = 2
4170 01:57:01.210090 rx_lastpass[0][1][9] = 38
4171 01:57:01.210502 rx_firspass[0][1][10] = 6
4172 01:57:01.213868 rx_lastpass[0][1][10] = 41
4173 01:57:01.216901 rx_firspass[0][1][11] = 1
4174 01:57:01.217446 rx_lastpass[0][1][11] = 33
4175 01:57:01.220506 rx_firspass[0][1][12] = 1
4176 01:57:01.224183 rx_lastpass[0][1][12] = 36
4177 01:57:01.226995 rx_firspass[0][1][13] = -1
4178 01:57:01.227502 rx_lastpass[0][1][13] = 34
4179 01:57:01.230345 rx_firspass[0][1][14] = 1
4180 01:57:01.233803 rx_lastpass[0][1][14] = 36
4181 01:57:01.236673 rx_firspass[0][1][15] = 3
4182 01:57:01.237089 rx_lastpass[0][1][15] = 38
4183 01:57:01.240554 rx_firspass[1][0][0] = 8
4184 01:57:01.243671 rx_lastpass[1][0][0] = 40
4185 01:57:01.244189 rx_firspass[1][0][1] = 7
4186 01:57:01.247143 rx_lastpass[1][0][1] = 38
4187 01:57:01.250137 rx_firspass[1][0][2] = 1
4188 01:57:01.254078 rx_lastpass[1][0][2] = 32
4189 01:57:01.254638 rx_firspass[1][0][3] = 0
4190 01:57:01.257059 rx_lastpass[1][0][3] = 31
4191 01:57:01.260597 rx_firspass[1][0][4] = 4
4192 01:57:01.261160 rx_lastpass[1][0][4] = 33
4193 01:57:01.263863 rx_firspass[1][0][5] = 9
4194 01:57:01.267184 rx_lastpass[1][0][5] = 38
4195 01:57:01.267774 rx_firspass[1][0][6] = 10
4196 01:57:01.270168 rx_lastpass[1][0][6] = 40
4197 01:57:01.273763 rx_firspass[1][0][7] = 5
4198 01:57:01.274369 rx_lastpass[1][0][7] = 33
4199 01:57:01.277434 rx_firspass[1][0][8] = 3
4200 01:57:01.280173 rx_lastpass[1][0][8] = 34
4201 01:57:01.283629 rx_firspass[1][0][9] = 3
4202 01:57:01.284141 rx_lastpass[1][0][9] = 35
4203 01:57:01.287002 rx_firspass[1][0][10] = 2
4204 01:57:01.290200 rx_lastpass[1][0][10] = 34
4205 01:57:01.290660 rx_firspass[1][0][11] = 4
4206 01:57:01.293927 rx_lastpass[1][0][11] = 34
4207 01:57:01.297033 rx_firspass[1][0][12] = 5
4208 01:57:01.299974 rx_lastpass[1][0][12] = 35
4209 01:57:01.300399 rx_firspass[1][0][13] = 5
4210 01:57:01.303578 rx_lastpass[1][0][13] = 32
4211 01:57:01.307403 rx_firspass[1][0][14] = 4
4212 01:57:01.317696 rx_lastpass[1][0][14] = 34
4213 01:57:01.318364 rx_firspass[1][0][15] = 0
4214 01:57:01.318911 rx_lastpass[1][0][15] = 32
4215 01:57:01.319434 rx_firspass[1][1][0] = 7
4216 01:57:01.319944 rx_lastpass[1][1][0] = 41
4217 01:57:01.320787 rx_firspass[1][1][1] = 5
4218 01:57:01.323307 rx_lastpass[1][1][1] = 41
4219 01:57:01.323719 rx_firspass[1][1][2] = 1
4220 01:57:01.327713 rx_lastpass[1][1][2] = 34
4221 01:57:01.330248 rx_firspass[1][1][3] = -2
4222 01:57:01.333616 rx_lastpass[1][1][3] = 32
4223 01:57:01.334056 rx_firspass[1][1][4] = 2
4224 01:57:01.337224 rx_lastpass[1][1][4] = 36
4225 01:57:01.340188 rx_firspass[1][1][5] = 5
4226 01:57:01.340597 rx_lastpass[1][1][5] = 40
4227 01:57:01.343682 rx_firspass[1][1][6] = 9
4228 01:57:01.346959 rx_lastpass[1][1][6] = 41
4229 01:57:01.347484 rx_firspass[1][1][7] = 2
4230 01:57:01.350306 rx_lastpass[1][1][7] = 36
4231 01:57:01.353455 rx_firspass[1][1][8] = 2
4232 01:57:01.356830 rx_lastpass[1][1][8] = 37
4233 01:57:01.357395 rx_firspass[1][1][9] = 2
4234 01:57:01.359939 rx_lastpass[1][1][9] = 36
4235 01:57:01.363182 rx_firspass[1][1][10] = 3
4236 01:57:01.363599 rx_lastpass[1][1][10] = 34
4237 01:57:01.366810 rx_firspass[1][1][11] = 4
4238 01:57:01.369898 rx_lastpass[1][1][11] = 38
4239 01:57:01.373616 rx_firspass[1][1][12] = 5
4240 01:57:01.374033 rx_lastpass[1][1][12] = 40
4241 01:57:01.376529 rx_firspass[1][1][13] = 3
4242 01:57:01.379887 rx_lastpass[1][1][13] = 37
4243 01:57:01.383123 rx_firspass[1][1][14] = 3
4244 01:57:01.383541 rx_lastpass[1][1][14] = 36
4245 01:57:01.386678 rx_firspass[1][1][15] = 1
4246 01:57:01.389989 rx_lastpass[1][1][15] = 33
4247 01:57:01.390419 dump params clk_delay
4248 01:57:01.393178 clk_delay[0] = -1
4249 01:57:01.393763 clk_delay[1] = 0
4250 01:57:01.396728 dump params dqs_delay
4251 01:57:01.397147 dqs_delay[0][0] = 0
4252 01:57:01.400361 dqs_delay[0][1] = 0
4253 01:57:01.403385 dqs_delay[1][0] = -1
4254 01:57:01.403802 dqs_delay[1][1] = 0
4255 01:57:01.406298 dump params delay_cell_unit = 762
4256 01:57:01.406727 dump source = 0x0
4257 01:57:01.409896 dump params frequency:1200
4258 01:57:01.413921 dump params rank number:2
4259 01:57:01.414445
4260 01:57:01.416500 dump params write leveling
4261 01:57:01.416918 write leveling[0][0][0] = 0x0
4262 01:57:01.420484 write leveling[0][0][1] = 0x0
4263 01:57:01.423683 write leveling[0][1][0] = 0x0
4264 01:57:01.426658 write leveling[0][1][1] = 0x0
4265 01:57:01.429717 write leveling[1][0][0] = 0x0
4266 01:57:01.433034 write leveling[1][0][1] = 0x0
4267 01:57:01.433603 write leveling[1][1][0] = 0x0
4268 01:57:01.436333 write leveling[1][1][1] = 0x0
4269 01:57:01.439838 dump params cbt_cs
4270 01:57:01.440254 cbt_cs[0][0] = 0x0
4271 01:57:01.442943 cbt_cs[0][1] = 0x0
4272 01:57:01.443364 cbt_cs[1][0] = 0x0
4273 01:57:01.446467 cbt_cs[1][1] = 0x0
4274 01:57:01.446885 dump params cbt_mr12
4275 01:57:01.449676 cbt_mr12[0][0] = 0x0
4276 01:57:01.450092 cbt_mr12[0][1] = 0x0
4277 01:57:01.453322 cbt_mr12[1][0] = 0x0
4278 01:57:01.456259 cbt_mr12[1][1] = 0x0
4279 01:57:01.456678 dump params tx window
4280 01:57:01.459703 tx_center_min[0][0][0] = 0
4281 01:57:01.462973 tx_center_max[0][0][0] = 0
4282 01:57:01.463395 tx_center_min[0][0][1] = 0
4283 01:57:01.466225 tx_center_max[0][0][1] = 0
4284 01:57:01.469584 tx_center_min[0][1][0] = 0
4285 01:57:01.472858 tx_center_max[0][1][0] = 0
4286 01:57:01.473300 tx_center_min[0][1][1] = 0
4287 01:57:01.476235 tx_center_max[0][1][1] = 0
4288 01:57:01.479477 tx_center_min[1][0][0] = 0
4289 01:57:01.482667 tx_center_max[1][0][0] = 0
4290 01:57:01.483125 tx_center_min[1][0][1] = 0
4291 01:57:01.486445 tx_center_max[1][0][1] = 0
4292 01:57:01.489682 tx_center_min[1][1][0] = 0
4293 01:57:01.492896 tx_center_max[1][1][0] = 0
4294 01:57:01.493330 tx_center_min[1][1][1] = 0
4295 01:57:01.495928 tx_center_max[1][1][1] = 0
4296 01:57:01.499244 dump params tx window
4297 01:57:01.499656 tx_win_center[0][0][0] = 0
4298 01:57:01.503020 tx_first_pass[0][0][0] = 0
4299 01:57:01.505909 tx_last_pass[0][0][0] = 0
4300 01:57:01.509911 tx_win_center[0][0][1] = 0
4301 01:57:01.510419 tx_first_pass[0][0][1] = 0
4302 01:57:01.512765 tx_last_pass[0][0][1] = 0
4303 01:57:01.516130 tx_win_center[0][0][2] = 0
4304 01:57:01.516541 tx_first_pass[0][0][2] = 0
4305 01:57:01.519629 tx_last_pass[0][0][2] = 0
4306 01:57:01.522798 tx_win_center[0][0][3] = 0
4307 01:57:01.526203 tx_first_pass[0][0][3] = 0
4308 01:57:01.526687 tx_last_pass[0][0][3] = 0
4309 01:57:01.529578 tx_win_center[0][0][4] = 0
4310 01:57:01.532604 tx_first_pass[0][0][4] = 0
4311 01:57:01.533123 tx_last_pass[0][0][4] = 0
4312 01:57:01.536057 tx_win_center[0][0][5] = 0
4313 01:57:01.539452 tx_first_pass[0][0][5] = 0
4314 01:57:01.542804 tx_last_pass[0][0][5] = 0
4315 01:57:01.543328 tx_win_center[0][0][6] = 0
4316 01:57:01.546128 tx_first_pass[0][0][6] = 0
4317 01:57:01.549417 tx_last_pass[0][0][6] = 0
4318 01:57:01.552846 tx_win_center[0][0][7] = 0
4319 01:57:01.553387 tx_first_pass[0][0][7] = 0
4320 01:57:01.556111 tx_last_pass[0][0][7] = 0
4321 01:57:01.559579 tx_win_center[0][0][8] = 0
4322 01:57:01.560060 tx_first_pass[0][0][8] = 0
4323 01:57:01.562874 tx_last_pass[0][0][8] = 0
4324 01:57:01.566242 tx_win_center[0][0][9] = 0
4325 01:57:01.569853 tx_first_pass[0][0][9] = 0
4326 01:57:01.570399 tx_last_pass[0][0][9] = 0
4327 01:57:01.572629 tx_win_center[0][0][10] = 0
4328 01:57:01.575998 tx_first_pass[0][0][10] = 0
4329 01:57:01.579466 tx_last_pass[0][0][10] = 0
4330 01:57:01.579875 tx_win_center[0][0][11] = 0
4331 01:57:01.582778 tx_first_pass[0][0][11] = 0
4332 01:57:01.586047 tx_last_pass[0][0][11] = 0
4333 01:57:01.589714 tx_win_center[0][0][12] = 0
4334 01:57:01.590125 tx_first_pass[0][0][12] = 0
4335 01:57:01.592846 tx_last_pass[0][0][12] = 0
4336 01:57:01.596090 tx_win_center[0][0][13] = 0
4337 01:57:01.599862 tx_first_pass[0][0][13] = 0
4338 01:57:01.600272 tx_last_pass[0][0][13] = 0
4339 01:57:01.602873 tx_win_center[0][0][14] = 0
4340 01:57:01.606470 tx_first_pass[0][0][14] = 0
4341 01:57:01.609437 tx_last_pass[0][0][14] = 0
4342 01:57:01.609854 tx_win_center[0][0][15] = 0
4343 01:57:01.612919 tx_first_pass[0][0][15] = 0
4344 01:57:01.616348 tx_last_pass[0][0][15] = 0
4345 01:57:01.619410 tx_win_center[0][1][0] = 0
4346 01:57:01.619849 tx_first_pass[0][1][0] = 0
4347 01:57:01.622740 tx_last_pass[0][1][0] = 0
4348 01:57:01.625810 tx_win_center[0][1][1] = 0
4349 01:57:01.626358 tx_first_pass[0][1][1] = 0
4350 01:57:01.629419 tx_last_pass[0][1][1] = 0
4351 01:57:01.632604 tx_win_center[0][1][2] = 0
4352 01:57:01.635802 tx_first_pass[0][1][2] = 0
4353 01:57:01.636231 tx_last_pass[0][1][2] = 0
4354 01:57:01.639243 tx_win_center[0][1][3] = 0
4355 01:57:01.642510 tx_first_pass[0][1][3] = 0
4356 01:57:01.646114 tx_last_pass[0][1][3] = 0
4357 01:57:01.646526 tx_win_center[0][1][4] = 0
4358 01:57:01.649202 tx_first_pass[0][1][4] = 0
4359 01:57:01.652499 tx_last_pass[0][1][4] = 0
4360 01:57:01.652906 tx_win_center[0][1][5] = 0
4361 01:57:01.656070 tx_first_pass[0][1][5] = 0
4362 01:57:01.659327 tx_last_pass[0][1][5] = 0
4363 01:57:01.662923 tx_win_center[0][1][6] = 0
4364 01:57:01.663330 tx_first_pass[0][1][6] = 0
4365 01:57:01.665970 tx_last_pass[0][1][6] = 0
4366 01:57:01.669233 tx_win_center[0][1][7] = 0
4367 01:57:01.672698 tx_first_pass[0][1][7] = 0
4368 01:57:01.673102 tx_last_pass[0][1][7] = 0
4369 01:57:01.675886 tx_win_center[0][1][8] = 0
4370 01:57:01.679016 tx_first_pass[0][1][8] = 0
4371 01:57:01.679425 tx_last_pass[0][1][8] = 0
4372 01:57:01.682494 tx_win_center[0][1][9] = 0
4373 01:57:01.686030 tx_first_pass[0][1][9] = 0
4374 01:57:01.689422 tx_last_pass[0][1][9] = 0
4375 01:57:01.689831 tx_win_center[0][1][10] = 0
4376 01:57:01.692907 tx_first_pass[0][1][10] = 0
4377 01:57:01.695896 tx_last_pass[0][1][10] = 0
4378 01:57:01.699591 tx_win_center[0][1][11] = 0
4379 01:57:01.700004 tx_first_pass[0][1][11] = 0
4380 01:57:01.702945 tx_last_pass[0][1][11] = 0
4381 01:57:01.705625 tx_win_center[0][1][12] = 0
4382 01:57:01.709087 tx_first_pass[0][1][12] = 0
4383 01:57:01.709579 tx_last_pass[0][1][12] = 0
4384 01:57:01.712755 tx_win_center[0][1][13] = 0
4385 01:57:01.715714 tx_first_pass[0][1][13] = 0
4386 01:57:01.719032 tx_last_pass[0][1][13] = 0
4387 01:57:01.719440 tx_win_center[0][1][14] = 0
4388 01:57:01.722249 tx_first_pass[0][1][14] = 0
4389 01:57:01.726176 tx_last_pass[0][1][14] = 0
4390 01:57:01.729150 tx_win_center[0][1][15] = 0
4391 01:57:01.729711 tx_first_pass[0][1][15] = 0
4392 01:57:01.732627 tx_last_pass[0][1][15] = 0
4393 01:57:01.735897 tx_win_center[1][0][0] = 0
4394 01:57:01.739346 tx_first_pass[1][0][0] = 0
4395 01:57:01.739898 tx_last_pass[1][0][0] = 0
4396 01:57:01.742426 tx_win_center[1][0][1] = 0
4397 01:57:01.745807 tx_first_pass[1][0][1] = 0
4398 01:57:01.746215 tx_last_pass[1][0][1] = 0
4399 01:57:01.748921 tx_win_center[1][0][2] = 0
4400 01:57:01.752624 tx_first_pass[1][0][2] = 0
4401 01:57:01.755531 tx_last_pass[1][0][2] = 0
4402 01:57:01.755958 tx_win_center[1][0][3] = 0
4403 01:57:01.759318 tx_first_pass[1][0][3] = 0
4404 01:57:01.762812 tx_last_pass[1][0][3] = 0
4405 01:57:01.765808 tx_win_center[1][0][4] = 0
4406 01:57:01.766220 tx_first_pass[1][0][4] = 0
4407 01:57:01.769095 tx_last_pass[1][0][4] = 0
4408 01:57:01.772568 tx_win_center[1][0][5] = 0
4409 01:57:01.773084 tx_first_pass[1][0][5] = 0
4410 01:57:01.775799 tx_last_pass[1][0][5] = 0
4411 01:57:01.779132 tx_win_center[1][0][6] = 0
4412 01:57:01.781984 tx_first_pass[1][0][6] = 0
4413 01:57:01.782606 tx_last_pass[1][0][6] = 0
4414 01:57:01.785871 tx_win_center[1][0][7] = 0
4415 01:57:01.789150 tx_first_pass[1][0][7] = 0
4416 01:57:01.792669 tx_last_pass[1][0][7] = 0
4417 01:57:01.793215 tx_win_center[1][0][8] = 0
4418 01:57:01.795553 tx_first_pass[1][0][8] = 0
4419 01:57:01.799144 tx_last_pass[1][0][8] = 0
4420 01:57:01.799666 tx_win_center[1][0][9] = 0
4421 01:57:01.802356 tx_first_pass[1][0][9] = 0
4422 01:57:01.805923 tx_last_pass[1][0][9] = 0
4423 01:57:01.808958 tx_win_center[1][0][10] = 0
4424 01:57:01.809401 tx_first_pass[1][0][10] = 0
4425 01:57:01.812330 tx_last_pass[1][0][10] = 0
4426 01:57:01.815838 tx_win_center[1][0][11] = 0
4427 01:57:01.818997 tx_first_pass[1][0][11] = 0
4428 01:57:01.819506 tx_last_pass[1][0][11] = 0
4429 01:57:01.822709 tx_win_center[1][0][12] = 0
4430 01:57:01.825901 tx_first_pass[1][0][12] = 0
4431 01:57:01.829727 tx_last_pass[1][0][12] = 0
4432 01:57:01.830239 tx_win_center[1][0][13] = 0
4433 01:57:01.832407 tx_first_pass[1][0][13] = 0
4434 01:57:01.835667 tx_last_pass[1][0][13] = 0
4435 01:57:01.839143 tx_win_center[1][0][14] = 0
4436 01:57:01.839550 tx_first_pass[1][0][14] = 0
4437 01:57:01.842351 tx_last_pass[1][0][14] = 0
4438 01:57:01.845921 tx_win_center[1][0][15] = 0
4439 01:57:01.848859 tx_first_pass[1][0][15] = 0
4440 01:57:01.849390 tx_last_pass[1][0][15] = 0
4441 01:57:01.852575 tx_win_center[1][1][0] = 0
4442 01:57:01.855789 tx_first_pass[1][1][0] = 0
4443 01:57:01.859131 tx_last_pass[1][1][0] = 0
4444 01:57:01.859632 tx_win_center[1][1][1] = 0
4445 01:57:01.862662 tx_first_pass[1][1][1] = 0
4446 01:57:01.865778 tx_last_pass[1][1][1] = 0
4447 01:57:01.866287 tx_win_center[1][1][2] = 0
4448 01:57:01.868659 tx_first_pass[1][1][2] = 0
4449 01:57:01.872234 tx_last_pass[1][1][2] = 0
4450 01:57:01.875740 tx_win_center[1][1][3] = 0
4451 01:57:01.876252 tx_first_pass[1][1][3] = 0
4452 01:57:01.878619 tx_last_pass[1][1][3] = 0
4453 01:57:01.882188 tx_win_center[1][1][4] = 0
4454 01:57:01.885685 tx_first_pass[1][1][4] = 0
4455 01:57:01.886099 tx_last_pass[1][1][4] = 0
4456 01:57:01.888833 tx_win_center[1][1][5] = 0
4457 01:57:01.892331 tx_first_pass[1][1][5] = 0
4458 01:57:01.893046 tx_last_pass[1][1][5] = 0
4459 01:57:01.895370 tx_win_center[1][1][6] = 0
4460 01:57:01.898464 tx_first_pass[1][1][6] = 0
4461 01:57:01.902114 tx_last_pass[1][1][6] = 0
4462 01:57:01.902524 tx_win_center[1][1][7] = 0
4463 01:57:01.905094 tx_first_pass[1][1][7] = 0
4464 01:57:01.909065 tx_last_pass[1][1][7] = 0
4465 01:57:01.912740 tx_win_center[1][1][8] = 0
4466 01:57:01.913152 tx_first_pass[1][1][8] = 0
4467 01:57:01.915719 tx_last_pass[1][1][8] = 0
4468 01:57:01.918672 tx_win_center[1][1][9] = 0
4469 01:57:01.922174 tx_first_pass[1][1][9] = 0
4470 01:57:01.922687 tx_last_pass[1][1][9] = 0
4471 01:57:01.925697 tx_win_center[1][1][10] = 0
4472 01:57:01.928854 tx_first_pass[1][1][10] = 0
4473 01:57:01.929387 tx_last_pass[1][1][10] = 0
4474 01:57:01.932344 tx_win_center[1][1][11] = 0
4475 01:57:01.935148 tx_first_pass[1][1][11] = 0
4476 01:57:01.939008 tx_last_pass[1][1][11] = 0
4477 01:57:01.939517 tx_win_center[1][1][12] = 0
4478 01:57:01.941678 tx_first_pass[1][1][12] = 0
4479 01:57:01.945023 tx_last_pass[1][1][12] = 0
4480 01:57:01.948693 tx_win_center[1][1][13] = 0
4481 01:57:01.949200 tx_first_pass[1][1][13] = 0
4482 01:57:01.952022 tx_last_pass[1][1][13] = 0
4483 01:57:01.955581 tx_win_center[1][1][14] = 0
4484 01:57:01.959024 tx_first_pass[1][1][14] = 0
4485 01:57:01.959539 tx_last_pass[1][1][14] = 0
4486 01:57:01.961896 tx_win_center[1][1][15] = 0
4487 01:57:01.965640 tx_first_pass[1][1][15] = 0
4488 01:57:01.968601 tx_last_pass[1][1][15] = 0
4489 01:57:01.969118 dump params rx window
4490 01:57:01.971835 rx_firspass[0][0][0] = 0
4491 01:57:01.975107 rx_lastpass[0][0][0] = 0
4492 01:57:01.975517 rx_firspass[0][0][1] = 0
4493 01:57:01.978436 rx_lastpass[0][0][1] = 0
4494 01:57:01.981858 rx_firspass[0][0][2] = 0
4495 01:57:01.982264 rx_lastpass[0][0][2] = 0
4496 01:57:01.985213 rx_firspass[0][0][3] = 0
4497 01:57:01.988469 rx_lastpass[0][0][3] = 0
4498 01:57:01.991729 rx_firspass[0][0][4] = 0
4499 01:57:01.992138 rx_lastpass[0][0][4] = 0
4500 01:57:01.995302 rx_firspass[0][0][5] = 0
4501 01:57:01.998762 rx_lastpass[0][0][5] = 0
4502 01:57:01.999273 rx_firspass[0][0][6] = 0
4503 01:57:02.001755 rx_lastpass[0][0][6] = 0
4504 01:57:02.004838 rx_firspass[0][0][7] = 0
4505 01:57:02.005246 rx_lastpass[0][0][7] = 0
4506 01:57:02.008653 rx_firspass[0][0][8] = 0
4507 01:57:02.011794 rx_lastpass[0][0][8] = 0
4508 01:57:02.012163 rx_firspass[0][0][9] = 0
4509 01:57:02.014949 rx_lastpass[0][0][9] = 0
4510 01:57:02.018501 rx_firspass[0][0][10] = 0
4511 01:57:02.019007 rx_lastpass[0][0][10] = 0
4512 01:57:02.021720 rx_firspass[0][0][11] = 0
4513 01:57:02.025302 rx_lastpass[0][0][11] = 0
4514 01:57:02.028486 rx_firspass[0][0][12] = 0
4515 01:57:02.028989 rx_lastpass[0][0][12] = 0
4516 01:57:02.032040 rx_firspass[0][0][13] = 0
4517 01:57:02.035440 rx_lastpass[0][0][13] = 0
4518 01:57:02.035855 rx_firspass[0][0][14] = 0
4519 01:57:02.038537 rx_lastpass[0][0][14] = 0
4520 01:57:02.042160 rx_firspass[0][0][15] = 0
4521 01:57:02.045632 rx_lastpass[0][0][15] = 0
4522 01:57:02.046134 rx_firspass[0][1][0] = 0
4523 01:57:02.049085 rx_lastpass[0][1][0] = 0
4524 01:57:02.052457 rx_firspass[0][1][1] = 0
4525 01:57:02.052964 rx_lastpass[0][1][1] = 0
4526 01:57:02.055293 rx_firspass[0][1][2] = 0
4527 01:57:02.058561 rx_lastpass[0][1][2] = 0
4528 01:57:02.058978 rx_firspass[0][1][3] = 0
4529 01:57:02.062080 rx_lastpass[0][1][3] = 0
4530 01:57:02.065776 rx_firspass[0][1][4] = 0
4531 01:57:02.066323 rx_lastpass[0][1][4] = 0
4532 01:57:02.068836 rx_firspass[0][1][5] = 0
4533 01:57:02.072314 rx_lastpass[0][1][5] = 0
4534 01:57:02.072825 rx_firspass[0][1][6] = 0
4535 01:57:02.075486 rx_lastpass[0][1][6] = 0
4536 01:57:02.078439 rx_firspass[0][1][7] = 0
4537 01:57:02.082117 rx_lastpass[0][1][7] = 0
4538 01:57:02.082628 rx_firspass[0][1][8] = 0
4539 01:57:02.085183 rx_lastpass[0][1][8] = 0
4540 01:57:02.088800 rx_firspass[0][1][9] = 0
4541 01:57:02.089356 rx_lastpass[0][1][9] = 0
4542 01:57:02.092197 rx_firspass[0][1][10] = 0
4543 01:57:02.095188 rx_lastpass[0][1][10] = 0
4544 01:57:02.095700 rx_firspass[0][1][11] = 0
4545 01:57:02.099151 rx_lastpass[0][1][11] = 0
4546 01:57:02.101456 rx_firspass[0][1][12] = 0
4547 01:57:02.105063 rx_lastpass[0][1][12] = 0
4548 01:57:02.105524 rx_firspass[0][1][13] = 0
4549 01:57:02.108583 rx_lastpass[0][1][13] = 0
4550 01:57:02.112069 rx_firspass[0][1][14] = 0
4551 01:57:02.112588 rx_lastpass[0][1][14] = 0
4552 01:57:02.114919 rx_firspass[0][1][15] = 0
4553 01:57:02.118561 rx_lastpass[0][1][15] = 0
4554 01:57:02.119076 rx_firspass[1][0][0] = 0
4555 01:57:02.121835 rx_lastpass[1][0][0] = 0
4556 01:57:02.125506 rx_firspass[1][0][1] = 0
4557 01:57:02.128617 rx_lastpass[1][0][1] = 0
4558 01:57:02.129131 rx_firspass[1][0][2] = 0
4559 01:57:02.131990 rx_lastpass[1][0][2] = 0
4560 01:57:02.135097 rx_firspass[1][0][3] = 0
4561 01:57:02.135619 rx_lastpass[1][0][3] = 0
4562 01:57:02.138234 rx_firspass[1][0][4] = 0
4563 01:57:02.141935 rx_lastpass[1][0][4] = 0
4564 01:57:02.142447 rx_firspass[1][0][5] = 0
4565 01:57:02.145085 rx_lastpass[1][0][5] = 0
4566 01:57:02.148853 rx_firspass[1][0][6] = 0
4567 01:57:02.149400 rx_lastpass[1][0][6] = 0
4568 01:57:02.151850 rx_firspass[1][0][7] = 0
4569 01:57:02.154839 rx_lastpass[1][0][7] = 0
4570 01:57:02.155245 rx_firspass[1][0][8] = 0
4571 01:57:02.158281 rx_lastpass[1][0][8] = 0
4572 01:57:02.161930 rx_firspass[1][0][9] = 0
4573 01:57:02.165130 rx_lastpass[1][0][9] = 0
4574 01:57:02.165681 rx_firspass[1][0][10] = 0
4575 01:57:02.168891 rx_lastpass[1][0][10] = 0
4576 01:57:02.171934 rx_firspass[1][0][11] = 0
4577 01:57:02.172355 rx_lastpass[1][0][11] = 0
4578 01:57:02.174798 rx_firspass[1][0][12] = 0
4579 01:57:02.178328 rx_lastpass[1][0][12] = 0
4580 01:57:02.182188 rx_firspass[1][0][13] = 0
4581 01:57:02.182713 rx_lastpass[1][0][13] = 0
4582 01:57:02.184880 rx_firspass[1][0][14] = 0
4583 01:57:02.188557 rx_lastpass[1][0][14] = 0
4584 01:57:02.189079 rx_firspass[1][0][15] = 0
4585 01:57:02.192107 rx_lastpass[1][0][15] = 0
4586 01:57:02.195278 rx_firspass[1][1][0] = 0
4587 01:57:02.195836 rx_lastpass[1][1][0] = 0
4588 01:57:02.198654 rx_firspass[1][1][1] = 0
4589 01:57:02.201856 rx_lastpass[1][1][1] = 0
4590 01:57:02.202297 rx_firspass[1][1][2] = 0
4591 01:57:02.204736 rx_lastpass[1][1][2] = 0
4592 01:57:02.208415 rx_firspass[1][1][3] = 0
4593 01:57:02.211858 rx_lastpass[1][1][3] = 0
4594 01:57:02.212395 rx_firspass[1][1][4] = 0
4595 01:57:02.214822 rx_lastpass[1][1][4] = 0
4596 01:57:02.218081 rx_firspass[1][1][5] = 0
4597 01:57:02.218652 rx_lastpass[1][1][5] = 0
4598 01:57:02.221562 rx_firspass[1][1][6] = 0
4599 01:57:02.224758 rx_lastpass[1][1][6] = 0
4600 01:57:02.225326 rx_firspass[1][1][7] = 0
4601 01:57:02.228689 rx_lastpass[1][1][7] = 0
4602 01:57:02.231518 rx_firspass[1][1][8] = 0
4603 01:57:02.232039 rx_lastpass[1][1][8] = 0
4604 01:57:02.235008 rx_firspass[1][1][9] = 0
4605 01:57:02.238104 rx_lastpass[1][1][9] = 0
4606 01:57:02.241702 rx_firspass[1][1][10] = 0
4607 01:57:02.242270 rx_lastpass[1][1][10] = 0
4608 01:57:02.245141 rx_firspass[1][1][11] = 0
4609 01:57:02.248442 rx_lastpass[1][1][11] = 0
4610 01:57:02.249006 rx_firspass[1][1][12] = 0
4611 01:57:02.251190 rx_lastpass[1][1][12] = 0
4612 01:57:02.255267 rx_firspass[1][1][13] = 0
4613 01:57:02.258066 rx_lastpass[1][1][13] = 0
4614 01:57:02.258539 rx_firspass[1][1][14] = 0
4615 01:57:02.261956 rx_lastpass[1][1][14] = 0
4616 01:57:02.265750 rx_firspass[1][1][15] = 0
4617 01:57:02.266271 rx_lastpass[1][1][15] = 0
4618 01:57:02.268116 dump params clk_delay
4619 01:57:02.268633 clk_delay[0] = 0
4620 01:57:02.271879 clk_delay[1] = 0
4621 01:57:02.272408 dump params dqs_delay
4622 01:57:02.274704 dqs_delay[0][0] = 0
4623 01:57:02.278266 dqs_delay[0][1] = 0
4624 01:57:02.278831 dqs_delay[1][0] = 0
4625 01:57:02.281536 dqs_delay[1][1] = 0
4626 01:57:02.284553 dump params delay_cell_unit = 762
4627 01:57:02.285172 dump source = 0x0
4628 01:57:02.288167 dump params frequency:800
4629 01:57:02.288676 dump params rank number:2
4630 01:57:02.289007
4631 01:57:02.291853 dump params write leveling
4632 01:57:02.295128 write leveling[0][0][0] = 0x0
4633 01:57:02.298015 write leveling[0][0][1] = 0x0
4634 01:57:02.301639 write leveling[0][1][0] = 0x0
4635 01:57:02.302157 write leveling[0][1][1] = 0x0
4636 01:57:02.305136 write leveling[1][0][0] = 0x0
4637 01:57:02.308518 write leveling[1][0][1] = 0x0
4638 01:57:02.311815 write leveling[1][1][0] = 0x0
4639 01:57:02.315201 write leveling[1][1][1] = 0x0
4640 01:57:02.315711 dump params cbt_cs
4641 01:57:02.318181 cbt_cs[0][0] = 0x0
4642 01:57:02.318710 cbt_cs[0][1] = 0x0
4643 01:57:02.321768 cbt_cs[1][0] = 0x0
4644 01:57:02.322274 cbt_cs[1][1] = 0x0
4645 01:57:02.325298 dump params cbt_mr12
4646 01:57:02.325810 cbt_mr12[0][0] = 0x0
4647 01:57:02.328294 cbt_mr12[0][1] = 0x0
4648 01:57:02.331517 cbt_mr12[1][0] = 0x0
4649 01:57:02.332054 cbt_mr12[1][1] = 0x0
4650 01:57:02.334795 dump params tx window
4651 01:57:02.335206 tx_center_min[0][0][0] = 0
4652 01:57:02.338173 tx_center_max[0][0][0] = 0
4653 01:57:02.341564 tx_center_min[0][0][1] = 0
4654 01:57:02.344455 tx_center_max[0][0][1] = 0
4655 01:57:02.344867 tx_center_min[0][1][0] = 0
4656 01:57:02.348018 tx_center_max[0][1][0] = 0
4657 01:57:02.351809 tx_center_min[0][1][1] = 0
4658 01:57:02.354550 tx_center_max[0][1][1] = 0
4659 01:57:02.354962 tx_center_min[1][0][0] = 0
4660 01:57:02.357865 tx_center_max[1][0][0] = 0
4661 01:57:02.361521 tx_center_min[1][0][1] = 0
4662 01:57:02.364900 tx_center_max[1][0][1] = 0
4663 01:57:02.365475 tx_center_min[1][1][0] = 0
4664 01:57:02.367973 tx_center_max[1][1][0] = 0
4665 01:57:02.371475 tx_center_min[1][1][1] = 0
4666 01:57:02.375123 tx_center_max[1][1][1] = 0
4667 01:57:02.375648 dump params tx window
4668 01:57:02.378674 tx_win_center[0][0][0] = 0
4669 01:57:02.381376 tx_first_pass[0][0][0] = 0
4670 01:57:02.381935 tx_last_pass[0][0][0] = 0
4671 01:57:02.384936 tx_win_center[0][0][1] = 0
4672 01:57:02.388232 tx_first_pass[0][0][1] = 0
4673 01:57:02.388795 tx_last_pass[0][0][1] = 0
4674 01:57:02.391462 tx_win_center[0][0][2] = 0
4675 01:57:02.395162 tx_first_pass[0][0][2] = 0
4676 01:57:02.398230 tx_last_pass[0][0][2] = 0
4677 01:57:02.398696 tx_win_center[0][0][3] = 0
4678 01:57:02.401789 tx_first_pass[0][0][3] = 0
4679 01:57:02.404963 tx_last_pass[0][0][3] = 0
4680 01:57:02.408119 tx_win_center[0][0][4] = 0
4681 01:57:02.408683 tx_first_pass[0][0][4] = 0
4682 01:57:02.411569 tx_last_pass[0][0][4] = 0
4683 01:57:02.415071 tx_win_center[0][0][5] = 0
4684 01:57:02.415641 tx_first_pass[0][0][5] = 0
4685 01:57:02.418004 tx_last_pass[0][0][5] = 0
4686 01:57:02.421361 tx_win_center[0][0][6] = 0
4687 01:57:02.425411 tx_first_pass[0][0][6] = 0
4688 01:57:02.425975 tx_last_pass[0][0][6] = 0
4689 01:57:02.428195 tx_win_center[0][0][7] = 0
4690 01:57:02.431471 tx_first_pass[0][0][7] = 0
4691 01:57:02.432028 tx_last_pass[0][0][7] = 0
4692 01:57:02.434598 tx_win_center[0][0][8] = 0
4693 01:57:02.437855 tx_first_pass[0][0][8] = 0
4694 01:57:02.441797 tx_last_pass[0][0][8] = 0
4695 01:57:02.442358 tx_win_center[0][0][9] = 0
4696 01:57:02.444735 tx_first_pass[0][0][9] = 0
4697 01:57:02.447759 tx_last_pass[0][0][9] = 0
4698 01:57:02.451454 tx_win_center[0][0][10] = 0
4699 01:57:02.451876 tx_first_pass[0][0][10] = 0
4700 01:57:02.454816 tx_last_pass[0][0][10] = 0
4701 01:57:02.457782 tx_win_center[0][0][11] = 0
4702 01:57:02.461236 tx_first_pass[0][0][11] = 0
4703 01:57:02.461678 tx_last_pass[0][0][11] = 0
4704 01:57:02.464914 tx_win_center[0][0][12] = 0
4705 01:57:02.468125 tx_first_pass[0][0][12] = 0
4706 01:57:02.471141 tx_last_pass[0][0][12] = 0
4707 01:57:02.471566 tx_win_center[0][0][13] = 0
4708 01:57:02.474561 tx_first_pass[0][0][13] = 0
4709 01:57:02.477801 tx_last_pass[0][0][13] = 0
4710 01:57:02.481150 tx_win_center[0][0][14] = 0
4711 01:57:02.481604 tx_first_pass[0][0][14] = 0
4712 01:57:02.484509 tx_last_pass[0][0][14] = 0
4713 01:57:02.487915 tx_win_center[0][0][15] = 0
4714 01:57:02.491594 tx_first_pass[0][0][15] = 0
4715 01:57:02.492124 tx_last_pass[0][0][15] = 0
4716 01:57:02.494649 tx_win_center[0][1][0] = 0
4717 01:57:02.497688 tx_first_pass[0][1][0] = 0
4718 01:57:02.500999 tx_last_pass[0][1][0] = 0
4719 01:57:02.501505 tx_win_center[0][1][1] = 0
4720 01:57:02.504613 tx_first_pass[0][1][1] = 0
4721 01:57:02.507729 tx_last_pass[0][1][1] = 0
4722 01:57:02.508148 tx_win_center[0][1][2] = 0
4723 01:57:02.511276 tx_first_pass[0][1][2] = 0
4724 01:57:02.514750 tx_last_pass[0][1][2] = 0
4725 01:57:02.517916 tx_win_center[0][1][3] = 0
4726 01:57:02.518439 tx_first_pass[0][1][3] = 0
4727 01:57:02.521477 tx_last_pass[0][1][3] = 0
4728 01:57:02.524712 tx_win_center[0][1][4] = 0
4729 01:57:02.525238 tx_first_pass[0][1][4] = 0
4730 01:57:02.528042 tx_last_pass[0][1][4] = 0
4731 01:57:02.531560 tx_win_center[0][1][5] = 0
4732 01:57:02.534816 tx_first_pass[0][1][5] = 0
4733 01:57:02.535331 tx_last_pass[0][1][5] = 0
4734 01:57:02.537695 tx_win_center[0][1][6] = 0
4735 01:57:02.541245 tx_first_pass[0][1][6] = 0
4736 01:57:02.541795 tx_last_pass[0][1][6] = 0
4737 01:57:02.544593 tx_win_center[0][1][7] = 0
4738 01:57:02.547967 tx_first_pass[0][1][7] = 0
4739 01:57:02.551140 tx_last_pass[0][1][7] = 0
4740 01:57:02.551561 tx_win_center[0][1][8] = 0
4741 01:57:02.554456 tx_first_pass[0][1][8] = 0
4742 01:57:02.558256 tx_last_pass[0][1][8] = 0
4743 01:57:02.561528 tx_win_center[0][1][9] = 0
4744 01:57:02.561948 tx_first_pass[0][1][9] = 0
4745 01:57:02.564375 tx_last_pass[0][1][9] = 0
4746 01:57:02.567980 tx_win_center[0][1][10] = 0
4747 01:57:02.571063 tx_first_pass[0][1][10] = 0
4748 01:57:02.571482 tx_last_pass[0][1][10] = 0
4749 01:57:02.574411 tx_win_center[0][1][11] = 0
4750 01:57:02.577966 tx_first_pass[0][1][11] = 0
4751 01:57:02.581216 tx_last_pass[0][1][11] = 0
4752 01:57:02.581671 tx_win_center[0][1][12] = 0
4753 01:57:02.584469 tx_first_pass[0][1][12] = 0
4754 01:57:02.587714 tx_last_pass[0][1][12] = 0
4755 01:57:02.591389 tx_win_center[0][1][13] = 0
4756 01:57:02.591809 tx_first_pass[0][1][13] = 0
4757 01:57:02.594763 tx_last_pass[0][1][13] = 0
4758 01:57:02.597641 tx_win_center[0][1][14] = 0
4759 01:57:02.600932 tx_first_pass[0][1][14] = 0
4760 01:57:02.601398 tx_last_pass[0][1][14] = 0
4761 01:57:02.604171 tx_win_center[0][1][15] = 0
4762 01:57:02.607934 tx_first_pass[0][1][15] = 0
4763 01:57:02.611163 tx_last_pass[0][1][15] = 0
4764 01:57:02.611688 tx_win_center[1][0][0] = 0
4765 01:57:02.614214 tx_first_pass[1][0][0] = 0
4766 01:57:02.618018 tx_last_pass[1][0][0] = 0
4767 01:57:02.618440 tx_win_center[1][0][1] = 0
4768 01:57:02.621036 tx_first_pass[1][0][1] = 0
4769 01:57:02.624134 tx_last_pass[1][0][1] = 0
4770 01:57:02.627540 tx_win_center[1][0][2] = 0
4771 01:57:02.627958 tx_first_pass[1][0][2] = 0
4772 01:57:02.631195 tx_last_pass[1][0][2] = 0
4773 01:57:02.634545 tx_win_center[1][0][3] = 0
4774 01:57:02.637749 tx_first_pass[1][0][3] = 0
4775 01:57:02.638170 tx_last_pass[1][0][3] = 0
4776 01:57:02.640902 tx_win_center[1][0][4] = 0
4777 01:57:02.644500 tx_first_pass[1][0][4] = 0
4778 01:57:02.644920 tx_last_pass[1][0][4] = 0
4779 01:57:02.647582 tx_win_center[1][0][5] = 0
4780 01:57:02.650958 tx_first_pass[1][0][5] = 0
4781 01:57:02.654349 tx_last_pass[1][0][5] = 0
4782 01:57:02.654769 tx_win_center[1][0][6] = 0
4783 01:57:02.657621 tx_first_pass[1][0][6] = 0
4784 01:57:02.660986 tx_last_pass[1][0][6] = 0
4785 01:57:02.664439 tx_win_center[1][0][7] = 0
4786 01:57:02.664896 tx_first_pass[1][0][7] = 0
4787 01:57:02.667598 tx_last_pass[1][0][7] = 0
4788 01:57:02.670885 tx_win_center[1][0][8] = 0
4789 01:57:02.671304 tx_first_pass[1][0][8] = 0
4790 01:57:02.674361 tx_last_pass[1][0][8] = 0
4791 01:57:02.677449 tx_win_center[1][0][9] = 0
4792 01:57:02.680701 tx_first_pass[1][0][9] = 0
4793 01:57:02.681192 tx_last_pass[1][0][9] = 0
4794 01:57:02.683977 tx_win_center[1][0][10] = 0
4795 01:57:02.687848 tx_first_pass[1][0][10] = 0
4796 01:57:02.691015 tx_last_pass[1][0][10] = 0
4797 01:57:02.691542 tx_win_center[1][0][11] = 0
4798 01:57:02.694066 tx_first_pass[1][0][11] = 0
4799 01:57:02.697366 tx_last_pass[1][0][11] = 0
4800 01:57:02.700882 tx_win_center[1][0][12] = 0
4801 01:57:02.701344 tx_first_pass[1][0][12] = 0
4802 01:57:02.704041 tx_last_pass[1][0][12] = 0
4803 01:57:02.708330 tx_win_center[1][0][13] = 0
4804 01:57:02.711037 tx_first_pass[1][0][13] = 0
4805 01:57:02.711564 tx_last_pass[1][0][13] = 0
4806 01:57:02.714186 tx_win_center[1][0][14] = 0
4807 01:57:02.717386 tx_first_pass[1][0][14] = 0
4808 01:57:02.720755 tx_last_pass[1][0][14] = 0
4809 01:57:02.721178 tx_win_center[1][0][15] = 0
4810 01:57:02.724097 tx_first_pass[1][0][15] = 0
4811 01:57:02.727463 tx_last_pass[1][0][15] = 0
4812 01:57:02.731057 tx_win_center[1][1][0] = 0
4813 01:57:02.731581 tx_first_pass[1][1][0] = 0
4814 01:57:02.733991 tx_last_pass[1][1][0] = 0
4815 01:57:02.737860 tx_win_center[1][1][1] = 0
4816 01:57:02.740958 tx_first_pass[1][1][1] = 0
4817 01:57:02.741531 tx_last_pass[1][1][1] = 0
4818 01:57:02.744532 tx_win_center[1][1][2] = 0
4819 01:57:02.747895 tx_first_pass[1][1][2] = 0
4820 01:57:02.748425 tx_last_pass[1][1][2] = 0
4821 01:57:02.750798 tx_win_center[1][1][3] = 0
4822 01:57:02.753970 tx_first_pass[1][1][3] = 0
4823 01:57:02.757477 tx_last_pass[1][1][3] = 0
4824 01:57:02.758034 tx_win_center[1][1][4] = 0
4825 01:57:02.760753 tx_first_pass[1][1][4] = 0
4826 01:57:02.764261 tx_last_pass[1][1][4] = 0
4827 01:57:02.764837 tx_win_center[1][1][5] = 0
4828 01:57:02.767726 tx_first_pass[1][1][5] = 0
4829 01:57:02.770844 tx_last_pass[1][1][5] = 0
4830 01:57:02.774107 tx_win_center[1][1][6] = 0
4831 01:57:02.774576 tx_first_pass[1][1][6] = 0
4832 01:57:02.777967 tx_last_pass[1][1][6] = 0
4833 01:57:02.780846 tx_win_center[1][1][7] = 0
4834 01:57:02.784073 tx_first_pass[1][1][7] = 0
4835 01:57:02.784636 tx_last_pass[1][1][7] = 0
4836 01:57:02.787529 tx_win_center[1][1][8] = 0
4837 01:57:02.790824 tx_first_pass[1][1][8] = 0
4838 01:57:02.791394 tx_last_pass[1][1][8] = 0
4839 01:57:02.793857 tx_win_center[1][1][9] = 0
4840 01:57:02.797048 tx_first_pass[1][1][9] = 0
4841 01:57:02.800799 tx_last_pass[1][1][9] = 0
4842 01:57:02.801375 tx_win_center[1][1][10] = 0
4843 01:57:02.804253 tx_first_pass[1][1][10] = 0
4844 01:57:02.807469 tx_last_pass[1][1][10] = 0
4845 01:57:02.810716 tx_win_center[1][1][11] = 0
4846 01:57:02.811239 tx_first_pass[1][1][11] = 0
4847 01:57:02.813786 tx_last_pass[1][1][11] = 0
4848 01:57:02.817974 tx_win_center[1][1][12] = 0
4849 01:57:02.820785 tx_first_pass[1][1][12] = 0
4850 01:57:02.821347 tx_last_pass[1][1][12] = 0
4851 01:57:02.823823 tx_win_center[1][1][13] = 0
4852 01:57:02.827311 tx_first_pass[1][1][13] = 0
4853 01:57:02.830382 tx_last_pass[1][1][13] = 0
4854 01:57:02.830909 tx_win_center[1][1][14] = 0
4855 01:57:02.833915 tx_first_pass[1][1][14] = 0
4856 01:57:02.836980 tx_last_pass[1][1][14] = 0
4857 01:57:02.840144 tx_win_center[1][1][15] = 0
4858 01:57:02.843866 tx_first_pass[1][1][15] = 0
4859 01:57:02.844456 tx_last_pass[1][1][15] = 0
4860 01:57:02.846814 dump params rx window
4861 01:57:02.847239 rx_firspass[0][0][0] = 0
4862 01:57:02.850121 rx_lastpass[0][0][0] = 0
4863 01:57:02.853832 rx_firspass[0][0][1] = 0
4864 01:57:02.857231 rx_lastpass[0][0][1] = 0
4865 01:57:02.857810 rx_firspass[0][0][2] = 0
4866 01:57:02.860648 rx_lastpass[0][0][2] = 0
4867 01:57:02.863608 rx_firspass[0][0][3] = 0
4868 01:57:02.864038 rx_lastpass[0][0][3] = 0
4869 01:57:02.867341 rx_firspass[0][0][4] = 0
4870 01:57:02.870318 rx_lastpass[0][0][4] = 0
4871 01:57:02.870743 rx_firspass[0][0][5] = 0
4872 01:57:02.873604 rx_lastpass[0][0][5] = 0
4873 01:57:02.876997 rx_firspass[0][0][6] = 0
4874 01:57:02.877448 rx_lastpass[0][0][6] = 0
4875 01:57:02.879873 rx_firspass[0][0][7] = 0
4876 01:57:02.883630 rx_lastpass[0][0][7] = 0
4877 01:57:02.886738 rx_firspass[0][0][8] = 0
4878 01:57:02.887161 rx_lastpass[0][0][8] = 0
4879 01:57:02.890615 rx_firspass[0][0][9] = 0
4880 01:57:02.893486 rx_lastpass[0][0][9] = 0
4881 01:57:02.893908 rx_firspass[0][0][10] = 0
4882 01:57:02.896572 rx_lastpass[0][0][10] = 0
4883 01:57:02.900207 rx_firspass[0][0][11] = 0
4884 01:57:02.900769 rx_lastpass[0][0][11] = 0
4885 01:57:02.903271 rx_firspass[0][0][12] = 0
4886 01:57:02.906208 rx_lastpass[0][0][12] = 0
4887 01:57:02.909431 rx_firspass[0][0][13] = 0
4888 01:57:02.910042 rx_lastpass[0][0][13] = 0
4889 01:57:02.912965 rx_firspass[0][0][14] = 0
4890 01:57:02.916726 rx_lastpass[0][0][14] = 0
4891 01:57:02.919847 rx_firspass[0][0][15] = 0
4892 01:57:02.920423 rx_lastpass[0][0][15] = 0
4893 01:57:02.923228 rx_firspass[0][1][0] = 0
4894 01:57:02.926337 rx_lastpass[0][1][0] = 0
4895 01:57:02.926897 rx_firspass[0][1][1] = 0
4896 01:57:02.929783 rx_lastpass[0][1][1] = 0
4897 01:57:02.933624 rx_firspass[0][1][2] = 0
4898 01:57:02.934185 rx_lastpass[0][1][2] = 0
4899 01:57:02.936549 rx_firspass[0][1][3] = 0
4900 01:57:02.939750 rx_lastpass[0][1][3] = 0
4901 01:57:02.940213 rx_firspass[0][1][4] = 0
4902 01:57:02.943135 rx_lastpass[0][1][4] = 0
4903 01:57:02.946391 rx_firspass[0][1][5] = 0
4904 01:57:02.946929 rx_lastpass[0][1][5] = 0
4905 01:57:02.949613 rx_firspass[0][1][6] = 0
4906 01:57:02.953126 rx_lastpass[0][1][6] = 0
4907 01:57:02.956551 rx_firspass[0][1][7] = 0
4908 01:57:02.957074 rx_lastpass[0][1][7] = 0
4909 01:57:02.960589 rx_firspass[0][1][8] = 0
4910 01:57:02.962972 rx_lastpass[0][1][8] = 0
4911 01:57:02.963568 rx_firspass[0][1][9] = 0
4912 01:57:02.966524 rx_lastpass[0][1][9] = 0
4913 01:57:02.969639 rx_firspass[0][1][10] = 0
4914 01:57:02.970203 rx_lastpass[0][1][10] = 0
4915 01:57:02.973501 rx_firspass[0][1][11] = 0
4916 01:57:02.976344 rx_lastpass[0][1][11] = 0
4917 01:57:02.976908 rx_firspass[0][1][12] = 0
4918 01:57:02.979559 rx_lastpass[0][1][12] = 0
4919 01:57:02.983013 rx_firspass[0][1][13] = 0
4920 01:57:02.987229 rx_lastpass[0][1][13] = 0
4921 01:57:02.987804 rx_firspass[0][1][14] = 0
4922 01:57:02.989471 rx_lastpass[0][1][14] = 0
4923 01:57:02.993042 rx_firspass[0][1][15] = 0
4924 01:57:02.993645 rx_lastpass[0][1][15] = 0
4925 01:57:02.996495 rx_firspass[1][0][0] = 0
4926 01:57:03.000063 rx_lastpass[1][0][0] = 0
4927 01:57:03.000626 rx_firspass[1][0][1] = 0
4928 01:57:03.003021 rx_lastpass[1][0][1] = 0
4929 01:57:03.006188 rx_firspass[1][0][2] = 0
4930 01:57:03.009755 rx_lastpass[1][0][2] = 0
4931 01:57:03.010318 rx_firspass[1][0][3] = 0
4932 01:57:03.012809 rx_lastpass[1][0][3] = 0
4933 01:57:03.016401 rx_firspass[1][0][4] = 0
4934 01:57:03.016969 rx_lastpass[1][0][4] = 0
4935 01:57:03.019902 rx_firspass[1][0][5] = 0
4936 01:57:03.023417 rx_lastpass[1][0][5] = 0
4937 01:57:03.023983 rx_firspass[1][0][6] = 0
4938 01:57:03.026180 rx_lastpass[1][0][6] = 0
4939 01:57:03.030051 rx_firspass[1][0][7] = 0
4940 01:57:03.030621 rx_lastpass[1][0][7] = 0
4941 01:57:03.033297 rx_firspass[1][0][8] = 0
4942 01:57:03.036922 rx_lastpass[1][0][8] = 0
4943 01:57:03.037529 rx_firspass[1][0][9] = 0
4944 01:57:03.039970 rx_lastpass[1][0][9] = 0
4945 01:57:03.043078 rx_firspass[1][0][10] = 0
4946 01:57:03.046680 rx_lastpass[1][0][10] = 0
4947 01:57:03.047240 rx_firspass[1][0][11] = 0
4948 01:57:03.050249 rx_lastpass[1][0][11] = 0
4949 01:57:03.052820 rx_firspass[1][0][12] = 0
4950 01:57:03.053312 rx_lastpass[1][0][12] = 0
4951 01:57:03.056917 rx_firspass[1][0][13] = 0
4952 01:57:03.059638 rx_lastpass[1][0][13] = 0
4953 01:57:03.062961 rx_firspass[1][0][14] = 0
4954 01:57:03.063429 rx_lastpass[1][0][14] = 0
4955 01:57:03.066452 rx_firspass[1][0][15] = 0
4956 01:57:03.069638 rx_lastpass[1][0][15] = 0
4957 01:57:03.070207 rx_firspass[1][1][0] = 0
4958 01:57:03.072817 rx_lastpass[1][1][0] = 0
4959 01:57:03.076163 rx_firspass[1][1][1] = 0
4960 01:57:03.076729 rx_lastpass[1][1][1] = 0
4961 01:57:03.079853 rx_firspass[1][1][2] = 0
4962 01:57:03.083052 rx_lastpass[1][1][2] = 0
4963 01:57:03.083614 rx_firspass[1][1][3] = 0
4964 01:57:03.086210 rx_lastpass[1][1][3] = 0
4965 01:57:03.089621 rx_firspass[1][1][4] = 0
4966 01:57:03.093234 rx_lastpass[1][1][4] = 0
4967 01:57:03.093833 rx_firspass[1][1][5] = 0
4968 01:57:03.096589 rx_lastpass[1][1][5] = 0
4969 01:57:03.099967 rx_firspass[1][1][6] = 0
4970 01:57:03.100521 rx_lastpass[1][1][6] = 0
4971 01:57:03.102827 rx_firspass[1][1][7] = 0
4972 01:57:03.106499 rx_lastpass[1][1][7] = 0
4973 01:57:03.107059 rx_firspass[1][1][8] = 0
4974 01:57:03.109769 rx_lastpass[1][1][8] = 0
4975 01:57:03.113121 rx_firspass[1][1][9] = 0
4976 01:57:03.113737 rx_lastpass[1][1][9] = 0
4977 01:57:03.116288 rx_firspass[1][1][10] = 0
4978 01:57:03.119494 rx_lastpass[1][1][10] = 0
4979 01:57:03.122976 rx_firspass[1][1][11] = 0
4980 01:57:03.123539 rx_lastpass[1][1][11] = 0
4981 01:57:03.126738 rx_firspass[1][1][12] = 0
4982 01:57:03.130151 rx_lastpass[1][1][12] = 0
4983 01:57:03.130717 rx_firspass[1][1][13] = 0
4984 01:57:03.133292 rx_lastpass[1][1][13] = 0
4985 01:57:03.136246 rx_firspass[1][1][14] = 0
4986 01:57:03.139405 rx_lastpass[1][1][14] = 0
4987 01:57:03.139959 rx_firspass[1][1][15] = 0
4988 01:57:03.143044 rx_lastpass[1][1][15] = 0
4989 01:57:03.145928 dump params clk_delay
4990 01:57:03.146390 clk_delay[0] = 0
4991 01:57:03.149439 clk_delay[1] = 0
4992 01:57:03.149999 dump params dqs_delay
4993 01:57:03.153158 dqs_delay[0][0] = 0
4994 01:57:03.153655 dqs_delay[0][1] = 0
4995 01:57:03.156187 dqs_delay[1][0] = 0
4996 01:57:03.156746 dqs_delay[1][1] = 0
4997 01:57:03.159843 dump params delay_cell_unit = 762
4998 01:57:03.163136 mt_set_emi_preloader end
4999 01:57:03.166408 [mt_mem_init] dram size: 0x100000000, rank number: 2
5000 01:57:03.172573 [complex_mem_test] start addr:0x40000000, len:20480
5001 01:57:03.208741 [mt_mem_init] preloader addr:0x40000000 complex R/W mem test pass : 0
5002 01:57:03.214792 [complex_mem_test] start addr:0x80000000, len:20480
5003 01:57:03.250617 [mt_mem_init] preloader addr:0x80000000 complex R/W mem test pass : 0
5004 01:57:03.257182 [complex_mem_test] start addr:0xc0000000, len:20480
5005 01:57:03.293160 [mt_mem_init] preloader addr:0xc0000000 complex R/W mem test pass : 0
5006 01:57:03.299558 [complex_mem_test] start addr:0x56000000, len:8192
5007 01:57:03.316428 [MEM] 1st complex R/W mem test pass (start addr:0x56000000)
5008 01:57:03.316979 ddr_geometry:1
5009 01:57:03.323071 [complex_mem_test] start addr:0x80000000, len:8192
5010 01:57:03.340217 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
5011 01:57:03.343553 dram_init: dram init end (result: 0)
5012 01:57:03.349995 Successfully loaded DRAM blobs and ran DRAM calibration
5013 01:57:03.360293 Mapping address range [0000000040000000:0000000140000000) as cacheable | read-write | non-secure | normal
5014 01:57:03.360853 CBMEM:
5015 01:57:03.363644 IMD: root @ 00000000fffff000 254 entries.
5016 01:57:03.366635 IMD: root @ 00000000ffffec00 62 entries.
5017 01:57:03.373306 VBOOT: copying vboot_working_data (256 bytes) to CBMEM...
5018 01:57:03.380280 out: cmd=0xa4: 03 6c a4 00 00 00 0c 00 00 01 00 00 50 7f 11 00 00 00 00 00
5019 01:57:03.383234 in-header: 03 a1 00 00 08 00 00 00
5020 01:57:03.386199 in-data: 84 60 60 10 00 00 00 00
5021 01:57:03.389738 Chrome EC: clear events_b mask to 0x0000000020004000
5022 01:57:03.397582 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
5023 01:57:03.400485 in-header: 03 fd 00 00 00 00 00 00
5024 01:57:03.401043 in-data:
5025 01:57:03.406896 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5026 01:57:03.407373 CBFS @ 21000 size 3d4000
5027 01:57:03.413953 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5028 01:57:03.417442 CBFS: Locating 'fallback/ramstage'
5029 01:57:03.420656 CBFS: Found @ offset 10d40 size d563
5030 01:57:03.441945 read SPI 0x31d94 0xd547: 16640 us, 3281 KB/s, 26.248 Mbps
5031 01:57:03.454180 Accumulated console time in romstage 12793 ms
5032 01:57:03.454735
5033 01:57:03.455099
5034 01:57:03.464149 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 ramstage starting (log level: 8)...
5035 01:57:03.467399 ARM64: Exception handlers installed.
5036 01:57:03.467850 ARM64: Testing exception
5037 01:57:03.471226 ARM64: Done test exception
5038 01:57:03.473799 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
5039 01:57:03.477150 Manufacturer: ef
5040 01:57:03.480743 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
5041 01:57:03.487738 WARNING: RO_VPD is uninitialized or empty.
5042 01:57:03.490554 FMAP: area RW_VPD found @ 550000 (16384 bytes)
5043 01:57:03.493807 FMAP: area RW_VPD found @ 550000 (16384 bytes)
5044 01:57:03.504370 read SPI 0x550600 0x3a00: 4532 us, 3276 KB/s, 26.208 Mbps
5045 01:57:03.506730 BS: BS_PRE_DEVICE times (ms): entry 0 run 0 exit 0
5046 01:57:03.513946 BS: BS_DEV_INIT_CHIPS times (ms): entry 0 run 0 exit 0
5047 01:57:03.514529 Enumerating buses...
5048 01:57:03.520668 Show all devs... Before device enumeration.
5049 01:57:03.521228 Root Device: enabled 1
5050 01:57:03.523895 CPU_CLUSTER: 0: enabled 1
5051 01:57:03.524457 CPU: 00: enabled 1
5052 01:57:03.527712 Compare with tree...
5053 01:57:03.530526 Root Device: enabled 1
5054 01:57:03.531089 CPU_CLUSTER: 0: enabled 1
5055 01:57:03.533682 CPU: 00: enabled 1
5056 01:57:03.537074 Root Device scanning...
5057 01:57:03.537699 root_dev_scan_bus for Root Device
5058 01:57:03.540748 CPU_CLUSTER: 0 enabled
5059 01:57:03.543676 root_dev_scan_bus for Root Device done
5060 01:57:03.550525 scan_bus: scanning of bus Root Device took 10689 usecs
5061 01:57:03.551104 done
5062 01:57:03.553590 BS: BS_DEV_ENUMERATE times (ms): entry 0 run 0 exit 0
5063 01:57:03.557159 Allocating resources...
5064 01:57:03.557755 Reading resources...
5065 01:57:03.560399 Root Device read_resources bus 0 link: 0
5066 01:57:03.567023 CPU_CLUSTER: 0 read_resources bus 0 link: 0
5067 01:57:03.567576 CPU: 00 missing read_resources
5068 01:57:03.574114 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
5069 01:57:03.576820 Root Device read_resources bus 0 link: 0 done
5070 01:57:03.580416 Done reading resources.
5071 01:57:03.583882 Show resources in subtree (Root Device)...After reading.
5072 01:57:03.586883 Root Device child on link 0 CPU_CLUSTER: 0
5073 01:57:03.590121 CPU_CLUSTER: 0 child on link 0 CPU: 00
5074 01:57:03.600357 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
5075 01:57:03.600826 CPU: 00
5076 01:57:03.603219 Setting resources...
5077 01:57:03.606646 Root Device assign_resources, bus 0 link: 0
5078 01:57:03.609847 CPU_CLUSTER: 0 missing set_resources
5079 01:57:03.613200 Root Device assign_resources, bus 0 link: 0
5080 01:57:03.616691 Done setting resources.
5081 01:57:03.623496 Show resources in subtree (Root Device)...After assigning values.
5082 01:57:03.626918 Root Device child on link 0 CPU_CLUSTER: 0
5083 01:57:03.630316 CPU_CLUSTER: 0 child on link 0 CPU: 00
5084 01:57:03.637029 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
5085 01:57:03.640252 CPU: 00
5086 01:57:03.643503 Done allocating resources.
5087 01:57:03.646788 BS: BS_DEV_RESOURCES times (ms): entry 0 run 0 exit 0
5088 01:57:03.650144 Enabling resources...
5089 01:57:03.650698 done.
5090 01:57:03.653240 BS: BS_DEV_ENABLE times (ms): entry 0 run 0 exit 0
5091 01:57:03.656946 Initializing devices...
5092 01:57:03.657536 Root Device init ...
5093 01:57:03.660043 mainboard_init: Starting display init.
5094 01:57:03.663388 ADC[4]: Raw value=76494 ID=0
5095 01:57:03.686637 anx7625_power_on_init: Init interface.
5096 01:57:03.689871 anx7625_disable_pd_protocol: Disabled PD feature.
5097 01:57:03.696389 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
5098 01:57:03.743228 anx7625_start_dp_work: Secure OCM version=00
5099 01:57:03.746344 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
5100 01:57:03.763240 sp_tx_get_edid_block: EDID Block = 1
5101 01:57:03.880992 Extracted contents:
5102 01:57:03.883924 header: 00 ff ff ff ff ff ff 00
5103 01:57:03.887555 serial number: 06 af 5c 14 00 00 00 00 00 1a
5104 01:57:03.890896 version: 01 04
5105 01:57:03.894108 basic params: 95 1a 0e 78 02
5106 01:57:03.897184 chroma info: 99 85 95 55 56 92 28 22 50 54
5107 01:57:03.900515 established: 00 00 00
5108 01:57:03.907111 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
5109 01:57:03.910928 descriptor 1: ce 1d 56 ea 50 00 1a 30 30 20 46 00 00 90 10 00 00 18
5110 01:57:03.917666 descriptor 2: 00 00 00 0f 00 00 00 00 00 00 00 00 00 00 00 00 00 20
5111 01:57:03.924100 descriptor 3: 00 00 00 fe 00 41 55 4f 0a 20 20 20 20 20 20 20 20 20
5112 01:57:03.930520 descriptor 4: 00 00 00 fe 00 42 31 31 36 58 41 42 30 31 2e 34 20 0a
5113 01:57:03.934212 extensions: 00
5114 01:57:03.934777 checksum: ae
5115 01:57:03.935266
5116 01:57:03.937429 Manufacturer: AUO Model 145c Serial Number 0
5117 01:57:03.940517 Made week 0 of 2016
5118 01:57:03.940994 EDID version: 1.4
5119 01:57:03.943824 Digital display
5120 01:57:03.946993 6 bits per primary color channel
5121 01:57:03.947484 DisplayPort interface
5122 01:57:03.950680 Maximum image size: 26 cm x 14 cm
5123 01:57:03.953860 Gamma: 220%
5124 01:57:03.954358 Check DPMS levels
5125 01:57:03.957361 Supported color formats: RGB 4:4:4
5126 01:57:03.960424 First detailed timing is preferred timing
5127 01:57:03.964110 Established timings supported:
5128 01:57:03.967589 Standard timings supported:
5129 01:57:03.968153 Detailed timings
5130 01:57:03.970384 Hex of detail: ce1d56ea50001a3030204600009010000018
5131 01:57:03.977636 Detailed mode (IN HEX): Clock 76300 KHz, 100 mm x 90 mm
5132 01:57:03.981371 0556 0586 05a6 0640 hborder 0
5133 01:57:03.984257 0300 0304 030a 031a vborder 0
5134 01:57:03.987491 -hsync -vsync
5135 01:57:03.990910 Did detailed timing
5136 01:57:03.994057 Hex of detail: 0000000f0000000000000000000000000020
5137 01:57:03.997304 Manufacturer-specified data, tag 15
5138 01:57:04.000592 Hex of detail: 000000fe0041554f0a202020202020202020
5139 01:57:04.003887 ASCII string: AUO
5140 01:57:04.007167 Hex of detail: 000000fe004231313658414230312e34200a
5141 01:57:04.010875 ASCII string: B116XAB01.4
5142 01:57:04.011426 Checksum
5143 01:57:04.013692 Checksum: 0xae (valid)
5144 01:57:04.020528 get_active_panel: Found ID 1: 'AUO B116XAB01.4 ' 1366x768@0Hz
5145 01:57:04.021081 DSI data_rate: 457800000 bps
5146 01:57:04.027902 anx7625_parse_edid: set default k value to 0x3d for panel
5147 01:57:04.031497 anx7625_parse_edid: pixelclock(76300).
5148 01:57:04.034106 hactive(1366), hsync(32), hfp(48), hbp(154)
5149 01:57:04.037693 vactive(768), vsync(6), vfp(4), vbp(16)
5150 01:57:04.041095 anx7625_dsi_config: config dsi.
5151 01:57:04.048778 anx7625_dsi_video_config: compute M(12500992), N(552960), divider(8).
5152 01:57:04.069904 anx7625_dsi_config: success to config DSI
5153 01:57:04.073339 anx7625_dp_start: MIPI phy setup OK.
5154 01:57:04.076419 [SSUSB] Setting up USB HOST controller...
5155 01:57:04.080220 [SSUSB] u3phy_ports_enable u2p:1, u3p:0
5156 01:57:04.083185 [SSUSB] phy power-on done.
5157 01:57:04.087248 out: cmd=0xf: 03 da 0f 00 00 00 04 00 10 00 00 00
5158 01:57:04.090538 in-header: 03 fc 01 00 00 00 00 00
5159 01:57:04.091004 in-data:
5160 01:57:04.093817 handle_proto3_response: EC response with error code: 1
5161 01:57:04.097175 SPM: pcm index = 1
5162 01:57:04.101123 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5163 01:57:04.104303 CBFS @ 21000 size 3d4000
5164 01:57:04.110637 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5165 01:57:04.113855 CBFS: Locating 'pcm_allinone_lp4_3200.bin'
5166 01:57:04.117648 CBFS: Found @ offset 1e7c0 size 1026
5167 01:57:04.124280 read SPI 0x3f808 0x1026: 1270 us, 3255 KB/s, 26.040 Mbps
5168 01:57:04.127118 SPM: binary array size = 2988
5169 01:57:04.130863 SPM: version = pcm_allinone_v1.17.2_20180829
5170 01:57:04.134118 SPM binary loaded in 32 msecs
5171 01:57:04.140963 spm_kick_im_to_fetch: ptr = 000000004021eec2
5172 01:57:04.144335 spm_kick_im_to_fetch: len = 2988
5173 01:57:04.144795 SPM: spm_kick_pcm_to_run
5174 01:57:04.148095 SPM: spm_kick_pcm_to_run done
5175 01:57:04.151445 SPM: spm_init done in 52 msecs
5176 01:57:04.154418 Root Device init finished in 494997 usecs
5177 01:57:04.158088 CPU_CLUSTER: 0 init ...
5178 01:57:04.164408 Mapping address range [0000000000200000:0000000000280000) as cacheable | read-write | secure | device
5179 01:57:04.171261 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5180 01:57:04.174644 CBFS @ 21000 size 3d4000
5181 01:57:04.177831 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5182 01:57:04.181368 CBFS: Locating 'sspm.bin'
5183 01:57:04.184388 CBFS: Found @ offset 208c0 size 41cb
5184 01:57:04.194307 read SPI 0x418f8 0x41cb: 5141 us, 3276 KB/s, 26.208 Mbps
5185 01:57:04.202073 CPU_CLUSTER: 0 init finished in 42801 usecs
5186 01:57:04.202632 Devices initialized
5187 01:57:04.205784 Show all devs... After init.
5188 01:57:04.208691 Root Device: enabled 1
5189 01:57:04.209168 CPU_CLUSTER: 0: enabled 1
5190 01:57:04.212599 CPU: 00: enabled 1
5191 01:57:04.215903 BS: BS_DEV_INIT times (ms): entry 0 run 224 exit 0
5192 01:57:04.219299 FMAP: area RW_ELOG found @ 558000 (4096 bytes)
5193 01:57:04.222041 ELOG: NV offset 0x558000 size 0x1000
5194 01:57:04.229825 read SPI 0x558000 0x1000: 1263 us, 3243 KB/s, 25.944 Mbps
5195 01:57:04.236569 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
5196 01:57:04.239695 ELOG: Event(17) added with size 13 at 2024-06-21 01:57:03 UTC
5197 01:57:04.243206 out: cmd=0x121: 03 db 21 01 00 00 00 00
5198 01:57:04.246723 in-header: 03 64 00 00 2c 00 00 00
5199 01:57:04.260222 in-data: fc 47 00 00 00 00 00 00 02 10 00 00 06 80 00 00 06 33 01 00 06 80 00 00 ba 2b 02 00 06 80 00 00 4d 2b 01 00 06 80 00 00 2a 3a 02 00
5200 01:57:04.262862 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
5201 01:57:04.266576 in-header: 03 19 00 00 08 00 00 00
5202 01:57:04.270167 in-data: a2 e0 47 00 13 00 00 00
5203 01:57:04.273422 Chrome EC: UHEPI supported
5204 01:57:04.280136 out: cmd=0xa4: 03 54 a4 00 00 00 0c 00 00 01 00 00 f8 ff 01 00 00 00 00 00
5205 01:57:04.282940 in-header: 03 e1 00 00 08 00 00 00
5206 01:57:04.286432 in-data: 84 20 60 10 00 00 00 00
5207 01:57:04.289633 FMAP: area RW_NVRAM found @ 554000 (8192 bytes)
5208 01:57:04.296224 out: cmd=0xa4: 03 c9 a4 00 00 00 0c 00 00 01 00 00 00 20 23 40 00 00 00 00
5209 01:57:04.300138 in-header: 03 e1 00 00 08 00 00 00
5210 01:57:04.302876 in-data: 84 20 60 10 00 00 00 00
5211 01:57:04.309839 ELOG: Event(A1) added with size 10 at 2024-06-21 01:57:04 UTC
5212 01:57:04.313322 ELOG: Event(16) added with size 11 at 2024-06-21 01:57:04 UTC
5213 01:57:04.390451 SF: Successfully erased 4096 bytes @ 0x558000
5214 01:57:04.402368 read SPI 0x558000 0x1000: 1258 us, 3255 KB/s, 26.040 Mbps
5215 01:57:04.408607 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
5216 01:57:04.416056 ELOG: Event(A0) added with size 9 at 2024-06-21 01:57:04 UTC
5217 01:57:04.419702 elog_add_boot_reason: Logged dev mode boot
5218 01:57:04.420262 Finalize devices...
5219 01:57:04.422802 Devices finalized
5220 01:57:04.425841 BS: BS_POST_DEVICE times (ms): entry 82 run 0 exit 0
5221 01:57:04.432437 BS: BS_OS_RESUME_CHECK times (ms): entry 0 run 0 exit 0
5222 01:57:04.435886 ELOG: Event(91) added with size 10 at 2024-06-21 01:57:04 UTC
5223 01:57:04.439179 Writing coreboot table at 0xffeda000
5224 01:57:04.445593 0. 0000000000114000-000000000011efff: RAMSTAGE
5225 01:57:04.448978 1. 0000000040000000-000000004023cfff: RAMSTAGE
5226 01:57:04.452530 2. 000000004023d000-00000000545fffff: RAM
5227 01:57:04.455583 3. 0000000054600000-000000005465ffff: BL31
5228 01:57:04.458719 4. 0000000054660000-00000000ffed9fff: RAM
5229 01:57:04.465673 5. 00000000ffeda000-00000000ffffffff: CONFIGURATION TABLES
5230 01:57:04.469064 6. 0000000100000000-000000013fffffff: RAM
5231 01:57:04.472266 Passing 5 GPIOs to payload:
5232 01:57:04.475873 NAME | PORT | POLARITY | VALUE
5233 01:57:04.482261 write protect | 0x00000096 | low | high
5234 01:57:04.485367 EC in RW | 0x000000b1 | high | undefined
5235 01:57:04.489112 EC interrupt | 0x00000097 | low | undefined
5236 01:57:04.496139 TPM interrupt | 0x00000099 | high | undefined
5237 01:57:04.498983 speaker enable | 0x000000af | high | undefined
5238 01:57:04.502156 out: cmd=0x6: 03 f7 06 00 00 00 00 00
5239 01:57:04.505617 in-header: 03 f7 00 00 02 00 00 00
5240 01:57:04.508723 in-data: 04 00
5241 01:57:04.509199 Board ID: 4
5242 01:57:04.512903 ADC[3]: Raw value=1034629 ID=8
5243 01:57:04.513532 RAM code: 8
5244 01:57:04.515563 SKU ID: 16
5245 01:57:04.518610 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5246 01:57:04.522075 CBFS @ 21000 size 3d4000
5247 01:57:04.525618 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5248 01:57:04.532234 Wrote coreboot table at: 00000000ffeda000, 0x394 bytes, checksum 26c5
5249 01:57:04.535661 coreboot table: 940 bytes.
5250 01:57:04.538824 IMD ROOT 0. 00000000fffff000 00001000
5251 01:57:04.541897 IMD SMALL 1. 00000000ffffe000 00001000
5252 01:57:04.545463 CONSOLE 2. 00000000fffde000 00020000
5253 01:57:04.548639 FMAP 3. 00000000fffdd000 0000047c
5254 01:57:04.552487 TIME STAMP 4. 00000000fffdc000 00000910
5255 01:57:04.555538 RAMOOPS 5. 00000000ffedc000 00100000
5256 01:57:04.558948 COREBOOT 6. 00000000ffeda000 00002000
5257 01:57:04.562193 IMD small region:
5258 01:57:04.565785 IMD ROOT 0. 00000000ffffec00 00000400
5259 01:57:04.568532 VBOOT WORK 1. 00000000ffffeb00 00000100
5260 01:57:04.571887 EC HOSTEVENT 2. 00000000ffffeae0 00000008
5261 01:57:04.575229 VPD 3. 00000000ffffea60 0000006c
5262 01:57:04.582185 BS: BS_WRITE_TABLES times (ms): entry 0 run 0 exit 0
5263 01:57:04.588972 out: cmd=0xa4: 03 95 a4 00 00 00 0c 00 00 01 00 00 24 32 21 40 00 00 00 00
5264 01:57:04.592294 in-header: 03 e1 00 00 08 00 00 00
5265 01:57:04.596086 in-data: 84 20 60 10 00 00 00 00
5266 01:57:04.599253 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5267 01:57:04.602451 CBFS @ 21000 size 3d4000
5268 01:57:04.605772 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5269 01:57:04.608759 CBFS: Locating 'fallback/payload'
5270 01:57:04.617943 CBFS: Found @ offset dc040 size 439a0
5271 01:57:04.705683 read SPI 0xfd078 0x439a0: 84378 us, 3281 KB/s, 26.248 Mbps
5272 01:57:04.709203 Checking segment from ROM address 0x0000000040003a00
5273 01:57:04.715448 Checking segment from ROM address 0x0000000040003a1c
5274 01:57:04.719509 Loading segment from ROM address 0x0000000040003a00
5275 01:57:04.722427 code (compression=0)
5276 01:57:04.732510 New segment dstaddr 0x0000000080000000 memsize 0x11994a0 srcaddr 0x0000000040003a38 filesize 0x43968
5277 01:57:04.739423 Loading Segment: addr: 0x0000000080000000 memsz: 0x00000000011994a0 filesz: 0x0000000000043968
5278 01:57:04.742417 it's not compressed!
5279 01:57:04.745509 [ 0x80000000, 80043968, 0x811994a0) <- 40003a38
5280 01:57:04.752186 Clearing Segment: addr: 0x0000000080043968 memsz: 0x0000000001155b38
5281 01:57:04.760363 Loading segment from ROM address 0x0000000040003a1c
5282 01:57:04.763269 Entry Point 0x0000000080000000
5283 01:57:04.763826 Loaded segments
5284 01:57:04.770054 BS: BS_PAYLOAD_LOAD times (ms): entry 0 run 92 exit 0
5285 01:57:04.773499 Jumping to boot code at 0000000080000000(00000000ffeda000)
5286 01:57:04.783264 CPU0: stack: 0000000000114000 - 0000000000118000, lowest used address 0000000000117540, stack used: 2752 bytes
5287 01:57:04.786851 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5288 01:57:04.789918 CBFS @ 21000 size 3d4000
5289 01:57:04.796579 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5290 01:57:04.799602 CBFS: Locating 'fallback/bl31'
5291 01:57:04.802852 CBFS: Found @ offset 36dc0 size 5820
5292 01:57:04.813614 read SPI 0x57de8 0x5820: 6880 us, 3279 KB/s, 26.232 Mbps
5293 01:57:04.817115 Checking segment from ROM address 0x0000000040003a00
5294 01:57:04.824438 Checking segment from ROM address 0x0000000040003a1c
5295 01:57:04.827424 Loading segment from ROM address 0x0000000040003a00
5296 01:57:04.830873 code (compression=1)
5297 01:57:04.837339 New segment dstaddr 0x0000000054600000 memsize 0x29000 srcaddr 0x0000000040003a38 filesize 0x57e8
5298 01:57:04.847564 Loading Segment: addr: 0x0000000054600000 memsz: 0x0000000000029000 filesz: 0x00000000000057e8
5299 01:57:04.848175 using LZMA
5300 01:57:04.855704 [ 0x54600000, 5460f420, 0x54629000) <- 40003a38
5301 01:57:04.862943 Clearing Segment: addr: 0x000000005460f420 memsz: 0x0000000000019be0
5302 01:57:04.865396 Loading segment from ROM address 0x0000000040003a1c
5303 01:57:04.868708 Entry Point 0x0000000054601000
5304 01:57:04.869159 Loaded segments
5305 01:57:04.872247 NOTICE: MT8183 bl31_setup
5306 01:57:04.879552 NOTICE: BL31: v2.1(debug):v2.1-806-g3addeb68c
5307 01:57:04.882791 NOTICE: BL31: Built : Sun Jan 30 03:25:20 UTC 2022
5308 01:57:04.885693 INFO: [DEVAPC] dump DEVAPC registers:
5309 01:57:04.895722 INFO: [DEVAPC] (INFRA)D0_APC_0 = 0x0, (INFRA)D1_APC_0 = 0xfcfffffc, (INFRA)D2_APC_0 = 0x0
5310 01:57:04.902995 INFO: [DEVAPC] (INFRA)D0_APC_1 = 0x0, (INFRA)D1_APC_1 = 0xffffffff, (INFRA)D2_APC_1 = 0x0
5311 01:57:04.912205 INFO: [DEVAPC] (INFRA)D0_APC_2 = 0x0, (INFRA)D1_APC_2 = 0xffffffff, (INFRA)D2_APC_2 = 0x0
5312 01:57:04.919685 INFO: [DEVAPC] (INFRA)D0_APC_3 = 0x0, (INFRA)D1_APC_3 = 0xffffffff, (INFRA)D2_APC_3 = 0x0
5313 01:57:04.928768 INFO: [DEVAPC] (INFRA)D0_APC_4 = 0x80000000, (INFRA)D1_APC_4 = 0xffffffff, (INFRA)D2_APC_4 = 0x0
5314 01:57:04.935646 INFO: [DEVAPC] (INFRA)D0_APC_5 = 0x2aaa, (INFRA)D1_APC_5 = 0xfcff3fff, (INFRA)D2_APC_5 = 0x0
5315 01:57:04.945382 INFO: [DEVAPC] (INFRA)D0_APC_6 = 0x0, (INFRA)D1_APC_6 = 0xffffffff, (INFRA)D2_APC_6 = 0x0
5316 01:57:04.952060 INFO: [DEVAPC] (INFRA)D0_APC_7 = 0x0, (INFRA)D1_APC_7 = 0xffffffff, (INFRA)D2_APC_7 = 0x0
5317 01:57:04.962347 INFO: [DEVAPC] (INFRA)D0_APC_8 = 0x0, (INFRA)D1_APC_8 = 0xffffffff, (INFRA)D2_APC_8 = 0x0
5318 01:57:04.969044 INFO: [DEVAPC] (INFRA)D0_APC_9 = 0x0, (INFRA)D1_APC_9 = 0xffffffff, (INFRA)D2_APC_9 = 0x0
5319 01:57:04.975922 INFO: [DEVAPC] (INFRA)D0_APC_10 = 0x0, (INFRA)D1_APC_10 = 0xffffffff, (INFRA)D2_APC_10 = 0x0
5320 01:57:04.985657 INFO: [DEVAPC] (INFRA)D0_APC_11 = 0x0, (INFRA)D1_APC_11 = 0xffffffff, (INFRA)D2_APC_11 = 0x0
5321 01:57:04.992016 INFO: [DEVAPC] (INFRA)D0_APC_12 = 0x0, (INFRA)D1_APC_12 = 0xff, (INFRA)D2_APC_12 = 0x0
5322 01:57:05.001898 INFO: [DEVAPC] (MM)D0_APC_0 = 0x0, (MM)D1_APC_0 = 0xffc000ff, (MM)D2_APC_0 = 0x0
5323 01:57:05.008775 INFO: [DEVAPC] (MM)D0_APC_1 = 0x0, (MM)D1_APC_1 = 0x3fffffff, (MM)D2_APC_1 = 0x0
5324 01:57:05.015983 INFO: [DEVAPC] (MM)D0_APC_2 = 0x0, (MM)D1_APC_2 = 0xcffff33c, (MM)D2_APC_2 = 0x0
5325 01:57:05.021922 INFO: [DEVAPC] (MM)D0_APC_3 = 0x0, (MM)D1_APC_3 = 0x3ccfc0ff, (MM)D2_APC_3 = 0x0
5326 01:57:05.028833 INFO: [DEVAPC] (MM)D0_APC_4 = 0x0, (MM)D1_APC_4 = 0xffff0000, (MM)D2_APC_4 = 0x0
5327 01:57:05.038402 INFO: [DEVAPC] (MM)D0_APC_5 = 0x0, (MM)D1_APC_5 = 0xffffffff, (MM)D2_APC_5 = 0x0
5328 01:57:05.045217 INFO: [DEVAPC] (MM)D0_APC_6 = 0x0, (MM)D1_APC_6 = 0xffffffff, (MM)D2_APC_6 = 0x0
5329 01:57:05.052102 INFO: [DEVAPC] (MM)D0_APC_7 = 0x0, (MM)D1_APC_7 = 0xffffffff, (MM)D2_APC_7 = 0x0
5330 01:57:05.058866 INFO: [DEVAPC] (MM)D0_APC_8 = 0x0, (MM)D1_APC_8 = 0x3ffffff, (MM)D2_APC_8 = 0x0
5331 01:57:05.061637 INFO: [DEVAPC] MAS_DOM_0 = 0x1
5332 01:57:05.065251 INFO: [DEVAPC] MAS_DOM_1 = 0x200
5333 01:57:05.068824 INFO: [DEVAPC] MAS_DOM_2 = 0x0
5334 01:57:05.071919 INFO: [DEVAPC] MAS_DOM_3 = 0x2000
5335 01:57:05.075050 INFO: [DEVAPC] MAS_SEC_0 = 0x8000000
5336 01:57:05.081795 INFO: [DEVAPC] (INFRA)MAS_DOMAIN_REMAP_0 = 0x88, (INFRA)MAS_DOMAIN_REMAP_1 = 0x0
5337 01:57:05.088981 INFO: [DEVAPC] (MM)MAS_DOMAIN_REMAP_0 = 0x24
5338 01:57:05.089548 WARNING: region 0:
5339 01:57:05.091697 WARNING: apc:0x168, sa:0x0, ea:0xfff
5340 01:57:05.094898 WARNING: region 1:
5341 01:57:05.098525 WARNING: apc:0x140, sa:0x1000, ea:0x128f
5342 01:57:05.098943 WARNING: region 2:
5343 01:57:05.101502 WARNING: apc:0x168, sa:0x1290, ea:0x1fff
5344 01:57:05.104965 WARNING: region 3:
5345 01:57:05.108460 WARNING: apc:0x168, sa:0x2000, ea:0xbfff
5346 01:57:05.111517 WARNING: region 4:
5347 01:57:05.115256 WARNING: apc:0x168, sa:0xc000, ea:0x1ffff
5348 01:57:05.115783 WARNING: region 5:
5349 01:57:05.118295 WARNING: apc:0x0, sa:0x0, ea:0x0
5350 01:57:05.121599 WARNING: region 6:
5351 01:57:05.125298 WARNING: apc:0x0, sa:0x0, ea:0x0
5352 01:57:05.125759 WARNING: region 7:
5353 01:57:05.128253 WARNING: apc:0x0, sa:0x0, ea:0x0
5354 01:57:05.134790 INFO: GICv3 without legacy support detected. ARM GICv3 driver initialized in EL3
5355 01:57:05.138389 INFO: SPM: enable SPMC mode
5356 01:57:05.141457 NOTICE: spm_boot_init() start
5357 01:57:05.144821 NOTICE: spm_boot_init() end
5358 01:57:05.148115 INFO: BL31: Initializing runtime services
5359 01:57:05.154996 INFO: BL31: cortex_a53: CPU workaround for 855873 was applied
5360 01:57:05.158100 INFO: BL31: Preparing for EL3 exit to normal world
5361 01:57:05.161249 INFO: Entry point address = 0x80000000
5362 01:57:05.164499 INFO: SPSR = 0x8
5363 01:57:05.185638
5364 01:57:05.186058
5365 01:57:05.186385
5366 01:57:05.187884 end: 2.2.3 depthcharge-start (duration 00:00:10) [common]
5367 01:57:05.188375 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
5368 01:57:05.188787 Setting prompt string to ['jacuzzi:']
5369 01:57:05.189181 bootloader-commands: Wait for prompt ['jacuzzi:'] (timeout 00:04:25)
5370 01:57:05.189938 Starting depthcharge on Juniper...
5371 01:57:05.190297
5372 01:57:05.192260 vboot_handoff: creating legacy vboot_handoff structure
5373 01:57:05.192860
5374 01:57:05.196133 ec_init(0): CrosEC protocol v3 supported (544, 544)
5375 01:57:05.196730
5376 01:57:05.199128 Wipe memory regions:
5377 01:57:05.199674
5378 01:57:05.202018 [0x00000040000000, 0x00000054600000)
5379 01:57:05.245395
5380 01:57:05.245901 [0x00000054660000, 0x00000080000000)
5381 01:57:05.336497
5382 01:57:05.337047 [0x000000811994a0, 0x000000ffeda000)
5383 01:57:05.596073
5384 01:57:05.596639 [0x00000100000000, 0x00000140000000)
5385 01:57:05.728398
5386 01:57:05.731891 Initializing XHCI USB controller at 0x11200000.
5387 01:57:05.755076
5388 01:57:05.757758 [firmware-jacuzzi-12573.B-collabora] Jun 8 2022 08:18:54
5389 01:57:05.758225
5390 01:57:05.758591
5391 01:57:05.759408 Setting prompt string to ['jacuzzi:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5393 01:57:05.860792 jacuzzi: tftpboot 192.168.201.1 14479169/tftp-deploy-fdqb7x23/kernel/image.itb 14479169/tftp-deploy-fdqb7x23/kernel/cmdline
5394 01:57:05.861495 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5395 01:57:05.861954 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:24)
5396 01:57:05.866552 tftpboot 192.168.201.1 14479169/tftp-deploy-fdqb7x23/kernel/image.ittp-deploy-fdqb7x23/kernel/cmdline
5397 01:57:05.867023
5398 01:57:05.867388 Waiting for link
5399 01:57:06.268582
5400 01:57:06.269135 R8152: Initializing
5401 01:57:06.269570
5402 01:57:06.271908 Version 9 (ocp_data = 6010)
5403 01:57:06.272370
5404 01:57:06.275091 R8152: Done initializing
5405 01:57:06.275648
5406 01:57:06.276021 Adding net device
5407 01:57:06.661096
5408 01:57:06.661847 done.
5409 01:57:06.662399
5410 01:57:06.662791 MAC: 00:e0:4c:71:a7:1f
5411 01:57:06.663139
5412 01:57:06.664026 Sending DHCP discover... done.
5413 01:57:06.664487
5414 01:57:06.667665 Waiting for reply... done.
5415 01:57:06.668128
5416 01:57:06.670667 Sending DHCP request... done.
5417 01:57:06.671133
5418 01:57:06.676409 Waiting for reply... done.
5419 01:57:06.676963
5420 01:57:06.677385 My ip is 192.168.201.23
5421 01:57:06.677744
5422 01:57:06.679982 The DHCP server ip is 192.168.201.1
5423 01:57:06.680538
5424 01:57:06.686650 TFTP server IP predefined by user: 192.168.201.1
5425 01:57:06.687210
5426 01:57:06.693281 Bootfile predefined by user: 14479169/tftp-deploy-fdqb7x23/kernel/image.itb
5427 01:57:06.693846
5428 01:57:06.694215 Sending tftp read request... done.
5429 01:57:06.694615
5430 01:57:06.702817 Waiting for the transfer...
5431 01:57:06.703425
5432 01:57:06.993478 00000000 ################################################################
5433 01:57:06.993619
5434 01:57:07.273897 00080000 ################################################################
5435 01:57:07.274034
5436 01:57:07.561663 00100000 ################################################################
5437 01:57:07.561809
5438 01:57:07.834149 00180000 ################################################################
5439 01:57:07.834288
5440 01:57:08.123036 00200000 ################################################################
5441 01:57:08.123178
5442 01:57:08.396065 00280000 ################################################################
5443 01:57:08.396234
5444 01:57:08.682383 00300000 ################################################################
5445 01:57:08.682522
5446 01:57:08.947627 00380000 ################################################################
5447 01:57:08.947797
5448 01:57:09.237248 00400000 ################################################################
5449 01:57:09.237398
5450 01:57:09.517459 00480000 ################################################################
5451 01:57:09.517600
5452 01:57:09.813601 00500000 ################################################################
5453 01:57:09.813732
5454 01:57:10.084899 00580000 ################################################################
5455 01:57:10.085069
5456 01:57:10.373469 00600000 ################################################################
5457 01:57:10.373610
5458 01:57:10.648499 00680000 ################################################################
5459 01:57:10.648661
5460 01:57:10.944923 00700000 ################################################################
5461 01:57:10.945091
5462 01:57:11.218219 00780000 ################################################################
5463 01:57:11.218358
5464 01:57:11.483167 00800000 ################################################################
5465 01:57:11.483337
5466 01:57:11.765602 00880000 ################################################################
5467 01:57:11.765764
5468 01:57:12.047153 00900000 ################################################################
5469 01:57:12.047327
5470 01:57:12.327436 00980000 ################################################################
5471 01:57:12.327600
5472 01:57:12.610414 00a00000 ################################################################
5473 01:57:12.610563
5474 01:57:12.897771 00a80000 ################################################################
5475 01:57:12.897926
5476 01:57:13.179498 00b00000 ################################################################
5477 01:57:13.179634
5478 01:57:13.470480 00b80000 ################################################################
5479 01:57:13.470644
5480 01:57:13.752663 00c00000 ################################################################
5481 01:57:13.752829
5482 01:57:14.021541 00c80000 ################################################################
5483 01:57:14.021684
5484 01:57:14.303103 00d00000 ################################################################
5485 01:57:14.303257
5486 01:57:14.583681 00d80000 ################################################################
5487 01:57:14.583815
5488 01:57:14.850176 00e00000 ################################################################
5489 01:57:14.850348
5490 01:57:15.108105 00e80000 ################################################################
5491 01:57:15.108271
5492 01:57:15.399216 00f00000 ################################################################
5493 01:57:15.399387
5494 01:57:15.688536 00f80000 ################################################################
5495 01:57:15.688701
5496 01:57:15.975779 01000000 ################################################################
5497 01:57:15.975946
5498 01:57:16.234817 01080000 ################################################################
5499 01:57:16.234995
5500 01:57:16.506276 01100000 ################################################################
5501 01:57:16.506442
5502 01:57:16.804135 01180000 ################################################################
5503 01:57:16.804306
5504 01:57:17.084805 01200000 ################################################################
5505 01:57:17.084972
5506 01:57:17.372966 01280000 ################################################################
5507 01:57:17.373133
5508 01:57:17.627949 01300000 ################################################################
5509 01:57:17.628118
5510 01:57:17.894525 01380000 ################################################################
5511 01:57:17.894683
5512 01:57:18.191122 01400000 ################################################################
5513 01:57:18.191285
5514 01:57:18.489408 01480000 ################################################################
5515 01:57:18.489544
5516 01:57:18.766741 01500000 ################################################################
5517 01:57:18.766885
5518 01:57:19.059847 01580000 ################################################################
5519 01:57:19.060011
5520 01:57:19.353890 01600000 ################################################################
5521 01:57:19.354050
5522 01:57:19.652415 01680000 ################################################################
5523 01:57:19.652575
5524 01:57:19.918255 01700000 ################################################################
5525 01:57:19.918419
5526 01:57:20.205738 01780000 ################################################################
5527 01:57:20.205882
5528 01:57:20.493131 01800000 ################################################################
5529 01:57:20.493327
5530 01:57:20.784770 01880000 ################################################################
5531 01:57:20.784932
5532 01:57:21.063547 01900000 ################################################################
5533 01:57:21.063699
5534 01:57:21.317192 01980000 ################################################################
5535 01:57:21.317349
5536 01:57:21.572810 01a00000 ################################################################
5537 01:57:21.572946
5538 01:57:21.828125 01a80000 ################################################################
5539 01:57:21.828262
5540 01:57:22.110830 01b00000 ################################################################
5541 01:57:22.110980
5542 01:57:22.399154 01b80000 ################################################################
5543 01:57:22.399315
5544 01:57:22.691559 01c00000 ################################################################
5545 01:57:22.691699
5546 01:57:22.985081 01c80000 ################################################################
5547 01:57:22.985245
5548 01:57:23.262496 01d00000 ################################################################
5549 01:57:23.262637
5550 01:57:23.538411 01d80000 ################################################################
5551 01:57:23.538547
5552 01:57:23.791206 01e00000 ######################################################### done.
5553 01:57:23.791347
5554 01:57:23.794268 The bootfile was 31923266 bytes long.
5555 01:57:23.794360
5556 01:57:23.797649 Sending tftp read request... done.
5557 01:57:23.797738
5558 01:57:23.797828 Waiting for the transfer...
5559 01:57:23.797912
5560 01:57:23.801138 00000000 # done.
5561 01:57:23.801260
5562 01:57:23.807728 Command line loaded dynamically from TFTP file: 14479169/tftp-deploy-fdqb7x23/kernel/cmdline
5563 01:57:23.807909
5564 01:57:23.834579 The command line is: earlyprintk=ttyS0,115200n8 console=tty1 console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14479169/extract-nfsrootfs-rq4f2012,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
5565 01:57:23.834874
5566 01:57:23.835117 Loading FIT.
5567 01:57:23.835313
5568 01:57:23.837693 Image ramdisk-1 has 18738626 bytes.
5569 01:57:23.837897
5570 01:57:23.841434 Image fdt-1 has 57695 bytes.
5571 01:57:23.841781
5572 01:57:23.844847 Image kernel-1 has 13124896 bytes.
5573 01:57:23.845233
5574 01:57:23.854569 Compat preference: google,juniper-rev4-sku16 google,juniper-sku16 google,juniper-rev4 google,juniper
5575 01:57:23.855102
5576 01:57:23.864380 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,juniper-sku16 (match) google,juniper mediatek,mt8183
5577 01:57:23.864922
5578 01:57:23.871151 Choosing best match conf-1 for compat google,juniper-sku16.
5579 01:57:23.875294
5580 01:57:23.879701 Connected to device vid:did:rid of 1ae0:0028:00
5581 01:57:23.886669
5582 01:57:23.889577 tpm_get_response: command 0x17b, return code 0x0
5583 01:57:23.890059
5584 01:57:23.893331 tpm_cleanup: add release locality here.
5585 01:57:23.893944
5586 01:57:23.897063 Shutting down all USB controllers.
5587 01:57:23.897660
5588 01:57:23.900772 Removing current net device
5589 01:57:23.901294
5590 01:57:23.902961 Exiting depthcharge with code 4 at timestamp: 35153369
5591 01:57:23.903392
5592 01:57:23.906599 LZMA decompressing kernel-1 to 0x80193568
5593 01:57:23.907033
5594 01:57:23.913245 LZMA decompressing kernel-1 to 0x40000000
5595 01:57:25.777453
5596 01:57:25.778018 jumping to kernel
5597 01:57:25.780883 end: 2.2.4 bootloader-commands (duration 00:00:21) [common]
5598 01:57:25.781664 start: 2.2.5 auto-login-action (timeout 00:04:04) [common]
5599 01:57:25.782249 Setting prompt string to ['Linux version [0-9]']
5600 01:57:25.782851 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5601 01:57:25.782988 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
5602 01:57:25.852581
5603 01:57:25.855496 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
5604 01:57:25.859275 start: 2.2.5.1 login-action (timeout 00:04:04) [common]
5605 01:57:25.859809 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
5606 01:57:25.860217 Setting prompt string to []
5607 01:57:25.860626 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
5608 01:57:25.861013 Using line separator: #'\n'#
5609 01:57:25.861467 No login prompt set.
5610 01:57:25.861829 Parsing kernel messages
5611 01:57:25.862144 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
5612 01:57:25.862707 [login-action] Waiting for messages, (timeout 00:04:04)
5613 01:57:25.863073 Waiting using forced prompt support (timeout 00:02:02)
5614 01:57:25.878809 [ 0.000000] Linux version 6.1.94-cip23 (KernelCI@build-j239242-arm64-gcc-10-defconfig-arm64-chromebook-c5lwc) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Jun 21 00:04:56 UTC 2024
5615 01:57:25.882118 [ 0.000000] random: crng init done
5616 01:57:25.889035 [ 0.000000] Machine model: Google juniper sku16 board
5617 01:57:25.892764 [ 0.000000] efi: UEFI not found.
5618 01:57:25.898653 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
5619 01:57:25.905144 [ 0.000000] OF: reserved mem: initialized node memory@50000000, compatible id shared-dma-pool
5620 01:57:25.915242 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
5621 01:57:25.918545 [ 0.000000] printk: bootconsole [mtk8250] enabled
5622 01:57:25.927033 [ 0.000000] NUMA: No NUMA configuration found
5623 01:57:25.933812 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
5624 01:57:25.940509 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7bda00-0x13f7bffff]
5625 01:57:25.941003 [ 0.000000] Zone ranges:
5626 01:57:25.946926 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
5627 01:57:25.950822 [ 0.000000] DMA32 empty
5628 01:57:25.957314 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
5629 01:57:25.960260 [ 0.000000] Movable zone start for each node
5630 01:57:25.963744 [ 0.000000] Early memory node ranges
5631 01:57:25.970541 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
5632 01:57:25.977061 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
5633 01:57:25.983500 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
5634 01:57:25.990238 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
5635 01:57:25.996889 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
5636 01:57:26.003258 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
5637 01:57:26.019773 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
5638 01:57:26.026500 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
5639 01:57:26.032752 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
5640 01:57:26.036210 [ 0.000000] psci: probing for conduit method from DT.
5641 01:57:26.042843 [ 0.000000] psci: PSCIv1.1 detected in firmware.
5642 01:57:26.046060 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
5643 01:57:26.053128 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
5644 01:57:26.056433 [ 0.000000] psci: SMC Calling Convention v1.1
5645 01:57:26.062922 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
5646 01:57:26.066154 [ 0.000000] Detected VIPT I-cache on CPU0
5647 01:57:26.073011 [ 0.000000] CPU features: detected: GIC system register CPU interface
5648 01:57:26.079633 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
5649 01:57:26.086174 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
5650 01:57:26.089654 [ 0.000000] CPU features: detected: ARM erratum 845719
5651 01:57:26.095954 [ 0.000000] alternatives: applying boot alternatives
5652 01:57:26.099517 [ 0.000000] Fallback order for Node 0: 0
5653 01:57:26.105996 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
5654 01:57:26.109038 [ 0.000000] Policy zone: Normal
5655 01:57:26.136209 [ 0.000000] Kernel command line: earlyprintk=ttyS0,115200n8 console=tty1 console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14479169/extract-nfsrootfs-rq4f2012,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
5656 01:57:26.148913 <5>[ 0.000000] Unknown kernel command line parameters "earlyprintk=ttyS0,115200n8 tftpserverip=192.168.201.1", will be passed to user space.
5657 01:57:26.158882 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
5658 01:57:26.165493 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
5659 01:57:26.172371 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
5660 01:57:26.178875 <6>[ 0.000000] software IO TLB: area num 8.
5661 01:57:26.203457 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
5662 01:57:26.260853 <6>[ 0.000000] Memory: 3896768K/4191232K available (18112K kernel code, 4120K rwdata, 22648K rodata, 8512K init, 616K bss, 261696K reserved, 32768K cma-reserved)
5663 01:57:26.267297 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
5664 01:57:26.274036 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
5665 01:57:26.277486 <6>[ 0.000000] rcu: RCU event tracing is enabled.
5666 01:57:26.283976 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
5667 01:57:26.291102 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
5668 01:57:26.294181 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
5669 01:57:26.304017 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
5670 01:57:26.310810 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
5671 01:57:26.313973 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
5672 01:57:26.326166 <6>[ 0.000000] GIC: enabling workaround for GICv3: Mediatek Chromebook GICR save problem
5673 01:57:26.332851 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
5674 01:57:26.336188 <6>[ 0.000000] GICv3: 640 SPIs implemented
5675 01:57:26.339254 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
5676 01:57:26.345991 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
5677 01:57:26.349417 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
5678 01:57:26.356245 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c100000
5679 01:57:26.366174 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@1[1] /cpus/cpu@2[2] /cpus/cpu@3[3] }
5680 01:57:26.379397 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@100[4] /cpus/cpu@101[5] /cpus/cpu@102[6] /cpus/cpu@103[7] }
5681 01:57:26.385945 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
5682 01:57:26.397766 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
5683 01:57:26.411371 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
5684 01:57:26.417716 <6>[ 0.000001] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
5685 01:57:26.424765 <6>[ 0.009469] Console: colour dummy device 80x25
5686 01:57:26.428541 <6>[ 0.014513] printk: console [tty1] enabled
5687 01:57:26.437948 <6>[ 0.018903] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
5688 01:57:26.445059 <6>[ 0.029368] pid_max: default: 32768 minimum: 301
5689 01:57:26.447877 <6>[ 0.034250] LSM: Security Framework initializing
5690 01:57:26.457896 <6>[ 0.039166] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
5691 01:57:26.464591 <6>[ 0.046789] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
5692 01:57:26.471341 <4>[ 0.055653] cacheinfo: Unable to detect cache hierarchy for CPU 0
5693 01:57:26.481187 <6>[ 0.062280] cblist_init_generic: Setting adjustable number of callback queues.
5694 01:57:26.488198 <6>[ 0.069726] cblist_init_generic: Setting shift to 3 and lim to 1.
5695 01:57:26.494689 <6>[ 0.076079] cblist_init_generic: Setting adjustable number of callback queues.
5696 01:57:26.501198 <6>[ 0.083524] cblist_init_generic: Setting shift to 3 and lim to 1.
5697 01:57:26.504115 <6>[ 0.089923] rcu: Hierarchical SRCU implementation.
5698 01:57:26.510911 <6>[ 0.094949] rcu: Max phase no-delay instances is 1000.
5699 01:57:26.517784 <6>[ 0.102858] EFI services will not be available.
5700 01:57:26.521029 <6>[ 0.107808] smp: Bringing up secondary CPUs ...
5701 01:57:26.532103 <6>[ 0.113111] Detected VIPT I-cache on CPU1
5702 01:57:26.538972 <4>[ 0.113157] cacheinfo: Unable to detect cache hierarchy for CPU 1
5703 01:57:26.545510 <6>[ 0.113166] GICv3: CPU1: found redistributor 1 region 0:0x000000000c120000
5704 01:57:26.552344 <6>[ 0.113197] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
5705 01:57:26.555233 <6>[ 0.113679] Detected VIPT I-cache on CPU2
5706 01:57:26.561639 <4>[ 0.113711] cacheinfo: Unable to detect cache hierarchy for CPU 2
5707 01:57:26.568530 <6>[ 0.113716] GICv3: CPU2: found redistributor 2 region 0:0x000000000c140000
5708 01:57:26.575010 <6>[ 0.113729] CPU2: Booted secondary processor 0x0000000002 [0x410fd034]
5709 01:57:26.578494 <6>[ 0.114176] Detected VIPT I-cache on CPU3
5710 01:57:26.585381 <4>[ 0.114206] cacheinfo: Unable to detect cache hierarchy for CPU 3
5711 01:57:26.591862 <6>[ 0.114210] GICv3: CPU3: found redistributor 3 region 0:0x000000000c160000
5712 01:57:26.598208 <6>[ 0.114222] CPU3: Booted secondary processor 0x0000000003 [0x410fd034]
5713 01:57:26.605052 <6>[ 0.114797] CPU features: detected: Spectre-v2
5714 01:57:26.608466 <6>[ 0.114808] CPU features: detected: Spectre-BHB
5715 01:57:26.615189 <6>[ 0.114812] CPU features: detected: ARM erratum 858921
5716 01:57:26.618573 <6>[ 0.114817] Detected VIPT I-cache on CPU4
5717 01:57:26.625363 <4>[ 0.114865] cacheinfo: Unable to detect cache hierarchy for CPU 4
5718 01:57:26.632042 <6>[ 0.114873] GICv3: CPU4: found redistributor 100 region 0:0x000000000c180000
5719 01:57:26.638256 <6>[ 0.114881] arch_timer: Enabling local workaround for ARM erratum 858921
5720 01:57:26.644937 <6>[ 0.114891] arch_timer: CPU4: Trapping CNTVCT access
5721 01:57:26.651269 <6>[ 0.114899] CPU4: Booted secondary processor 0x0000000100 [0x410fd092]
5722 01:57:26.654445 <6>[ 0.115384] Detected VIPT I-cache on CPU5
5723 01:57:26.661442 <4>[ 0.115425] cacheinfo: Unable to detect cache hierarchy for CPU 5
5724 01:57:26.668229 <6>[ 0.115430] GICv3: CPU5: found redistributor 101 region 0:0x000000000c1a0000
5725 01:57:26.674790 <6>[ 0.115437] arch_timer: Enabling local workaround for ARM erratum 858921
5726 01:57:26.681401 <6>[ 0.115443] arch_timer: CPU5: Trapping CNTVCT access
5727 01:57:26.687704 <6>[ 0.115448] CPU5: Booted secondary processor 0x0000000101 [0x410fd092]
5728 01:57:26.691153 <6>[ 0.115884] Detected VIPT I-cache on CPU6
5729 01:57:26.697789 <4>[ 0.115931] cacheinfo: Unable to detect cache hierarchy for CPU 6
5730 01:57:26.704572 <6>[ 0.115937] GICv3: CPU6: found redistributor 102 region 0:0x000000000c1c0000
5731 01:57:26.711015 <6>[ 0.115944] arch_timer: Enabling local workaround for ARM erratum 858921
5732 01:57:26.718375 <6>[ 0.115950] arch_timer: CPU6: Trapping CNTVCT access
5733 01:57:26.724846 <6>[ 0.115956] CPU6: Booted secondary processor 0x0000000102 [0x410fd092]
5734 01:57:26.727850 <6>[ 0.116484] Detected VIPT I-cache on CPU7
5735 01:57:26.734459 <4>[ 0.116530] cacheinfo: Unable to detect cache hierarchy for CPU 7
5736 01:57:26.741146 <6>[ 0.116536] GICv3: CPU7: found redistributor 103 region 0:0x000000000c1e0000
5737 01:57:26.747728 <6>[ 0.116543] arch_timer: Enabling local workaround for ARM erratum 858921
5738 01:57:26.754455 <6>[ 0.116549] arch_timer: CPU7: Trapping CNTVCT access
5739 01:57:26.761547 <6>[ 0.116554] CPU7: Booted secondary processor 0x0000000103 [0x410fd092]
5740 01:57:26.764398 <6>[ 0.116630] smp: Brought up 1 node, 8 CPUs
5741 01:57:26.771146 <6>[ 0.355512] SMP: Total of 8 processors activated.
5742 01:57:26.774217 <6>[ 0.360450] CPU features: detected: 32-bit EL0 Support
5743 01:57:26.780852 <6>[ 0.365822] CPU features: detected: 32-bit EL1 Support
5744 01:57:26.787577 <6>[ 0.371188] CPU features: detected: CRC32 instructions
5745 01:57:26.790968 <6>[ 0.376615] CPU: All CPU(s) started at EL2
5746 01:57:26.797904 <6>[ 0.380953] alternatives: applying system-wide alternatives
5747 01:57:26.804254 <6>[ 0.389079] devtmpfs: initialized
5748 01:57:26.816557 <6>[ 0.398037] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
5749 01:57:26.826842 <6>[ 0.407984] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
5750 01:57:26.829813 <6>[ 0.415717] pinctrl core: initialized pinctrl subsystem
5751 01:57:26.838517 <6>[ 0.422812] DMI not present or invalid.
5752 01:57:26.844740 <6>[ 0.427181] NET: Registered PF_NETLINK/PF_ROUTE protocol family
5753 01:57:26.851030 <6>[ 0.434087] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
5754 01:57:26.861365 <6>[ 0.441617] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
5755 01:57:26.868090 <6>[ 0.449867] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
5756 01:57:26.874485 <6>[ 0.458043] audit: initializing netlink subsys (disabled)
5757 01:57:26.881422 <5>[ 0.463748] audit: type=2000 audit(0.332:1): state=initialized audit_enabled=0 res=1
5758 01:57:26.887757 <6>[ 0.464717] thermal_sys: Registered thermal governor 'step_wise'
5759 01:57:26.894384 <6>[ 0.471714] thermal_sys: Registered thermal governor 'power_allocator'
5760 01:57:26.897816 <6>[ 0.478011] cpuidle: using governor menu
5761 01:57:26.904597 <6>[ 0.488973] NET: Registered PF_QIPCRTR protocol family
5762 01:57:26.911061 <6>[ 0.494469] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
5763 01:57:26.917961 <6>[ 0.501566] ASID allocator initialised with 32768 entries
5764 01:57:26.921416 <6>[ 0.508318] Serial: AMBA PL011 UART driver
5765 01:57:26.934384 <4>[ 0.518693] Trying to register duplicate clock ID: 113
5766 01:57:26.993249 <6>[ 0.574904] platform 14014000.dsi: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
5767 01:57:27.007627 <6>[ 0.589216] platform panel: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
5768 01:57:27.011047 <6>[ 0.598954] KASLR enabled
5769 01:57:27.025660 <6>[ 0.606985] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
5770 01:57:27.032196 <6>[ 0.613988] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
5771 01:57:27.039082 <6>[ 0.620464] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
5772 01:57:27.045439 <6>[ 0.627456] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
5773 01:57:27.051977 <6>[ 0.633929] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
5774 01:57:27.058738 <6>[ 0.640919] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
5775 01:57:27.065372 <6>[ 0.647393] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
5776 01:57:27.072148 <6>[ 0.654382] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
5777 01:57:27.075546 <6>[ 0.661944] ACPI: Interpreter disabled.
5778 01:57:27.085402 <6>[ 0.669899] iommu: Default domain type: Translated
5779 01:57:27.091601 <6>[ 0.675006] iommu: DMA domain TLB invalidation policy: strict mode
5780 01:57:27.095183 <5>[ 0.681639] SCSI subsystem initialized
5781 01:57:27.101683 <6>[ 0.686054] usbcore: registered new interface driver usbfs
5782 01:57:27.108540 <6>[ 0.691784] usbcore: registered new interface driver hub
5783 01:57:27.111533 <6>[ 0.697326] usbcore: registered new device driver usb
5784 01:57:27.118828 <6>[ 0.703623] pps_core: LinuxPPS API ver. 1 registered
5785 01:57:27.128651 <6>[ 0.708808] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
5786 01:57:27.132938 <6>[ 0.718134] PTP clock support registered
5787 01:57:27.136077 <6>[ 0.722385] EDAC MC: Ver: 3.0.0
5788 01:57:27.143242 <6>[ 0.728015] FPGA manager framework
5789 01:57:27.150001 <6>[ 0.731696] Advanced Linux Sound Architecture Driver Initialized.
5790 01:57:27.153036 <6>[ 0.738450] vgaarb: loaded
5791 01:57:27.156685 <6>[ 0.741579] clocksource: Switched to clocksource arch_sys_counter
5792 01:57:27.163355 <5>[ 0.748009] VFS: Disk quotas dquot_6.6.0
5793 01:57:27.170079 <6>[ 0.752185] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
5794 01:57:27.173170 <6>[ 0.759356] pnp: PnP ACPI: disabled
5795 01:57:27.181293 <6>[ 0.766227] NET: Registered PF_INET protocol family
5796 01:57:27.187993 <6>[ 0.771452] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
5797 01:57:27.200267 <6>[ 0.781358] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
5798 01:57:27.209856 <6>[ 0.790111] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
5799 01:57:27.216318 <6>[ 0.798062] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
5800 01:57:27.222917 <6>[ 0.806297] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
5801 01:57:27.230102 <6>[ 0.814395] TCP: Hash tables configured (established 32768 bind 32768)
5802 01:57:27.239916 <6>[ 0.821223] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
5803 01:57:27.246293 <6>[ 0.828196] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
5804 01:57:27.253036 <6>[ 0.835677] NET: Registered PF_UNIX/PF_LOCAL protocol family
5805 01:57:27.259716 <6>[ 0.841805] RPC: Registered named UNIX socket transport module.
5806 01:57:27.262987 <6>[ 0.847949] RPC: Registered udp transport module.
5807 01:57:27.266567 <6>[ 0.852874] RPC: Registered tcp transport module.
5808 01:57:27.273050 <6>[ 0.857797] RPC: Registered tcp NFSv4.1 backchannel transport module.
5809 01:57:27.279844 <6>[ 0.864450] PCI: CLS 0 bytes, default 64
5810 01:57:27.283482 <6>[ 0.868733] Unpacking initramfs...
5811 01:57:27.308207 <6>[ 0.889627] hw perfevents: enabled with armv8_cortex_a53 PMU driver, 7 counters available
5812 01:57:27.318686 <6>[ 0.898397] hw perfevents: enabled with armv8_cortex_a73 PMU driver, 7 counters available
5813 01:57:27.321207 <6>[ 0.907312] kvm [1]: IPA Size Limit: 40 bits
5814 01:57:27.329031 <6>[ 0.913677] kvm [1]: vgic-v2@c420000
5815 01:57:27.332181 <6>[ 0.917505] kvm [1]: GIC system register CPU interface enabled
5816 01:57:27.338842 <6>[ 0.923695] kvm [1]: vgic interrupt IRQ18
5817 01:57:27.342124 <6>[ 0.928070] kvm [1]: Hyp mode initialized successfully
5818 01:57:27.349962 <5>[ 0.934442] Initialise system trusted keyrings
5819 01:57:27.355849 <6>[ 0.939300] workingset: timestamp_bits=42 max_order=20 bucket_order=0
5820 01:57:27.364878 <6>[ 0.949294] squashfs: version 4.0 (2009/01/31) Phillip Lougher
5821 01:57:27.371275 <5>[ 0.955757] NFS: Registering the id_resolver key type
5822 01:57:27.374283 <5>[ 0.961067] Key type id_resolver registered
5823 01:57:27.381252 <5>[ 0.965482] Key type id_legacy registered
5824 01:57:27.387732 <6>[ 0.969791] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
5825 01:57:27.394696 <6>[ 0.976711] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
5826 01:57:27.400911 <6>[ 0.984475] 9p: Installing v9fs 9p2000 file system support
5827 01:57:27.428743 <5>[ 1.013352] Key type asymmetric registered
5828 01:57:27.431883 <5>[ 1.017703] Asymmetric key parser 'x509' registered
5829 01:57:27.442172 <6>[ 1.022859] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
5830 01:57:27.445012 <6>[ 1.030479] io scheduler mq-deadline registered
5831 01:57:27.448646 <6>[ 1.035237] io scheduler kyber registered
5832 01:57:27.471011 <6>[ 1.055949] EINJ: ACPI disabled.
5833 01:57:27.477754 <4>[ 1.059704] of_fixed_factor_clk: probe of fixed-factor-clock-13m failed with error -17
5834 01:57:27.515466 <6>[ 1.100393] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
5835 01:57:27.524404 <6>[ 1.108887] printk: console [ttyS0] disabled
5836 01:57:27.552093 <6>[ 1.133541] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 242, base_baud = 1625000) is a ST16650V2
5837 01:57:27.558703 <6>[ 1.143018] printk: console [ttyS0] enabled
5838 01:57:27.562215 <6>[ 1.143018] printk: console [ttyS0] enabled
5839 01:57:27.568853 <6>[ 1.151941] printk: bootconsole [mtk8250] disabled
5840 01:57:27.572191 <6>[ 1.151941] printk: bootconsole [mtk8250] disabled
5841 01:57:27.581980 <3>[ 1.162481] mt8183-pinctrl 10005000.pinctrl: pin_config_group_set op failed for group 47
5842 01:57:27.588383 <3>[ 1.170862] mt6577-uart 11003000.serial: Error applying setting, reverse things back
5843 01:57:27.618043 <6>[ 1.199276] 11003000.serial: ttyS1 at MMIO 0x11003000 (irq = 243, base_baud = 1625000) is a ST16650V2
5844 01:57:27.624391 <6>[ 1.208934] serial serial0: tty port ttyS1 registered
5845 01:57:27.630864 <6>[ 1.215473] SuperH (H)SCI(F) driver initialized
5846 01:57:27.634761 <6>[ 1.220959] msm_serial: driver initialized
5847 01:57:27.649929 <6>[ 1.231279] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14008000
5848 01:57:27.660030 <6>[ 1.239879] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14009000
5849 01:57:27.666638 <6>[ 1.248453] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@1400a000
5850 01:57:27.677190 <6>[ 1.257025] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@1400b000
5851 01:57:27.683183 <6>[ 1.265687] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@1400c000
5852 01:57:27.693208 <6>[ 1.274353] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@1400e000
5853 01:57:27.703592 <6>[ 1.283095] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400f000
5854 01:57:27.709858 <6>[ 1.291834] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@14010000
5855 01:57:27.719824 <6>[ 1.300402] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@14011000
5856 01:57:27.726667 <6>[ 1.309200] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/dsi@14014000
5857 01:57:27.737214 <4>[ 1.321548] cacheinfo: Unable to detect cache hierarchy for CPU 0
5858 01:57:27.745856 <6>[ 1.330903] loop: module loaded
5859 01:57:27.757810 <6>[ 1.342883] vsim1: Bringing 1800000uV into 2700000-2700000uV
5860 01:57:27.776049 <6>[ 1.360867] megasas: 07.719.03.00-rc1
5861 01:57:27.784963 <6>[ 1.369643] spi-nor spi1.0: w25q64dw (8192 Kbytes)
5862 01:57:27.792153 <6>[ 1.376963] tpm_tis_spi spi0.0: TPM ready IRQ confirmed on attempt 2
5863 01:57:27.808890 <6>[ 1.393565] tpm_tis_spi spi0.0: 2.0 TPM (device-id 0x28, rev-id 0)
5864 01:57:27.865686 <6>[ 1.443518] tpm_tis_spi spi0.0: Cr50 firmware version: B2-C:0 RO_A:0.0.12/bf248b9d RW_B:0.5.171/cr50_v2.94_mp.164-2fb1d
5865 01:57:27.901489 <6>[ 1.486008] Freeing initrd memory: 18296K
5866 01:57:27.916545 <4>[ 1.497821] sysfs: cannot create duplicate filename '/bus/platform/devices/fixed-factor-clock-13m'
5867 01:57:27.923034 <4>[ 1.507052] CPU: 6 PID: 1 Comm: swapper/0 Not tainted 6.1.94-cip23 #1
5868 01:57:27.929853 <4>[ 1.513751] Hardware name: Google juniper sku16 board (DT)
5869 01:57:27.933619 <4>[ 1.519490] Call trace:
5870 01:57:27.936934 <4>[ 1.522190] dump_backtrace.part.0+0xe0/0xf0
5871 01:57:27.939881 <4>[ 1.526727] show_stack+0x18/0x30
5872 01:57:27.943040 <4>[ 1.530299] dump_stack_lvl+0x68/0x84
5873 01:57:27.949665 <4>[ 1.534221] dump_stack+0x18/0x34
5874 01:57:27.952938 <4>[ 1.537791] sysfs_warn_dup+0x64/0x80
5875 01:57:27.956398 <4>[ 1.541712] sysfs_do_create_link_sd+0xf0/0x100
5876 01:57:27.960367 <4>[ 1.546498] sysfs_create_link+0x20/0x40
5877 01:57:27.966607 <4>[ 1.550674] bus_add_device+0x68/0x10c
5878 01:57:27.969861 <4>[ 1.554680] device_add+0x364/0x7cc
5879 01:57:27.973116 <4>[ 1.558423] of_device_add+0x44/0x60
5880 01:57:27.976640 <4>[ 1.562257] of_platform_device_create_pdata+0x90/0x120
5881 01:57:27.983422 <4>[ 1.567739] of_platform_bus_create+0x170/0x370
5882 01:57:27.986675 <4>[ 1.572523] of_platform_populate+0x50/0xfc
5883 01:57:27.993437 <4>[ 1.576960] parse_mtd_partitions+0x1dc/0x510
5884 01:57:27.996765 <4>[ 1.581573] mtd_device_parse_register+0xf0/0x2e4
5885 01:57:28.000145 <4>[ 1.586532] spi_nor_probe+0x21c/0x2f0
5886 01:57:28.003304 <4>[ 1.590538] spi_mem_probe+0x6c/0xb0
5887 01:57:28.006355 <4>[ 1.594370] spi_probe+0x84/0xe4
5888 01:57:28.013472 <4>[ 1.597852] really_probe+0xbc/0x2e0
5889 01:57:28.016573 <4>[ 1.601682] __driver_probe_device+0x78/0x11c
5890 01:57:28.020047 <4>[ 1.606294] driver_probe_device+0xd8/0x160
5891 01:57:28.026769 <4>[ 1.610733] __device_attach_driver+0xb8/0x134
5892 01:57:28.029779 <4>[ 1.615432] bus_for_each_drv+0x78/0xd0
5893 01:57:28.033911 <4>[ 1.619522] __device_attach+0xa8/0x1c0
5894 01:57:28.036738 <4>[ 1.623613] device_initial_probe+0x14/0x20
5895 01:57:28.043139 <4>[ 1.628051] bus_probe_device+0x9c/0xa4
5896 01:57:28.047041 <4>[ 1.632142] device_add+0x3d0/0x7cc
5897 01:57:28.049887 <4>[ 1.635885] __spi_add_device+0x78/0x120
5898 01:57:28.053665 <4>[ 1.640063] spi_add_device+0x40/0x7c
5899 01:57:28.060399 <4>[ 1.643981] spi_register_controller+0x610/0xad0
5900 01:57:28.063540 <4>[ 1.648854] devm_spi_register_controller+0x4c/0xa4
5901 01:57:28.066531 <4>[ 1.653987] mtk_spi_probe+0x3f8/0x650
5902 01:57:28.073362 <4>[ 1.657991] platform_probe+0x68/0xe0
5903 01:57:28.076566 <4>[ 1.661910] really_probe+0xbc/0x2e0
5904 01:57:28.080207 <4>[ 1.665740] __driver_probe_device+0x78/0x11c
5905 01:57:28.083227 <4>[ 1.670352] driver_probe_device+0xd8/0x160
5906 01:57:28.090301 <4>[ 1.674790] __driver_attach+0x94/0x19c
5907 01:57:28.093577 <4>[ 1.678880] bus_for_each_dev+0x70/0xd0
5908 01:57:28.097105 <4>[ 1.682970] driver_attach+0x24/0x30
5909 01:57:28.100486 <4>[ 1.686800] bus_add_driver+0x154/0x20c
5910 01:57:28.106962 <4>[ 1.690891] driver_register+0x78/0x130
5911 01:57:28.110310 <4>[ 1.694982] __platform_driver_register+0x28/0x34
5912 01:57:28.113319 <4>[ 1.699941] mtk_spi_driver_init+0x1c/0x28
5913 01:57:28.120369 <4>[ 1.704295] do_one_initcall+0x50/0x1d0
5914 01:57:28.123876 <4>[ 1.708385] kernel_init_freeable+0x21c/0x288
5915 01:57:28.127340 <4>[ 1.712998] kernel_init+0x24/0x12c
5916 01:57:28.130519 <4>[ 1.716744] ret_from_fork+0x10/0x20
5917 01:57:28.141156 <6>[ 1.725687] tun: Universal TUN/TAP device driver, 1.6
5918 01:57:28.144498 <6>[ 1.731968] thunder_xcv, ver 1.0
5919 01:57:28.148019 <6>[ 1.735484] thunder_bgx, ver 1.0
5920 01:57:28.151217 <6>[ 1.738987] nicpf, ver 1.0
5921 01:57:28.161637 <6>[ 1.743347] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
5922 01:57:28.165080 <6>[ 1.750832] hns3: Copyright (c) 2017 Huawei Corporation.
5923 01:57:28.171959 <6>[ 1.756429] hclge is initializing
5924 01:57:28.175217 <6>[ 1.760014] e1000: Intel(R) PRO/1000 Network Driver
5925 01:57:28.182159 <6>[ 1.765149] e1000: Copyright (c) 1999-2006 Intel Corporation.
5926 01:57:28.185374 <6>[ 1.771173] e1000e: Intel(R) PRO/1000 Network Driver
5927 01:57:28.191798 <6>[ 1.776394] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
5928 01:57:28.198380 <6>[ 1.782590] igb: Intel(R) Gigabit Ethernet Network Driver
5929 01:57:28.205860 <6>[ 1.788245] igb: Copyright (c) 2007-2014 Intel Corporation.
5930 01:57:28.212024 <6>[ 1.794089] igbvf: Intel(R) Gigabit Virtual Function Network Driver
5931 01:57:28.218736 <6>[ 1.800612] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
5932 01:57:28.221501 <6>[ 1.807161] sky2: driver version 1.30
5933 01:57:28.228673 <6>[ 1.812412] usbcore: registered new device driver r8152-cfgselector
5934 01:57:28.235179 <6>[ 1.818955] usbcore: registered new interface driver r8152
5935 01:57:28.241821 <6>[ 1.824794] VFIO - User Level meta-driver version: 0.3
5936 01:57:28.249031 <6>[ 1.832590] mtu3 11201000.usb: uwk - reg:0x420, version:101
5937 01:57:28.254961 <4>[ 1.838463] mtu3 11201000.usb: supply vbus not found, using dummy regulator
5938 01:57:28.261700 <6>[ 1.845741] mtu3 11201000.usb: dr_mode: 1, drd: auto
5939 01:57:28.268548 <6>[ 1.850971] mtu3 11201000.usb: u2p_dis_msk: 0, u3p_dis_msk: 0
5940 01:57:28.271854 <6>[ 1.857156] mtu3 11201000.usb: usb3-drd: 0
5941 01:57:28.278530 <6>[ 1.862718] mtu3 11201000.usb: xHCI platform device register success...
5942 01:57:28.289847 <4>[ 1.871334] xhci-mtk 11200000.usb: supply vbus not found, using dummy regulator
5943 01:57:28.296643 <6>[ 1.879273] xhci-mtk 11200000.usb: xHCI Host Controller
5944 01:57:28.303510 <6>[ 1.884777] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
5945 01:57:28.309842 <6>[ 1.892507] xhci-mtk 11200000.usb: USB3 root hub has no ports
5946 01:57:28.316817 <6>[ 1.898516] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
5947 01:57:28.323298 <6>[ 1.907938] xhci-mtk 11200000.usb: irq 253, io mem 0x11200000
5948 01:57:28.330131 <6>[ 1.914004] xhci-mtk 11200000.usb: xHCI Host Controller
5949 01:57:28.336769 <6>[ 1.919491] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
5950 01:57:28.343235 <6>[ 1.927149] xhci-mtk 11200000.usb: Host supports USB 3.0 SuperSpeed
5951 01:57:28.347540 <6>[ 1.933968] hub 1-0:1.0: USB hub found
5952 01:57:28.353510 <6>[ 1.937997] hub 1-0:1.0: 1 port detected
5953 01:57:28.360011 <6>[ 1.943357] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
5954 01:57:28.367253 <6>[ 1.951976] hub 2-0:1.0: USB hub found
5955 01:57:28.373668 <3>[ 1.956002] hub 2-0:1.0: config failed, hub doesn't have any ports! (err -19)
5956 01:57:28.380544 <6>[ 1.963887] usbcore: registered new interface driver usb-storage
5957 01:57:28.387612 <6>[ 1.970497] usbcore: registered new device driver onboard-usb-hub
5958 01:57:28.404399 <4>[ 1.985679] onboard-usb-hub 11200000.usb:hub@1: supply vdd not found, using dummy regulator
5959 01:57:28.413244 <6>[ 1.997965] mt6397-rtc mt6358-rtc: registered as rtc0
5960 01:57:28.423448 <6>[ 2.003447] mt6397-rtc mt6358-rtc: setting system clock to 2024-06-21T01:57:28 UTC (1718935048)
5961 01:57:28.426793 <6>[ 2.013335] i2c_dev: i2c /dev entries driver
5962 01:57:28.438382 <6>[ 2.019748] platform panel: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
5963 01:57:28.448465 <6>[ 2.028072] platform 14014000.dsi: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
5964 01:57:28.451655 <6>[ 2.036979] i2c 4-0058: Fixed dependency cycle(s) with /panel
5965 01:57:28.461494 <6>[ 2.043011] i2c 4-0058: Fixed dependency cycle(s) with /soc/dsi@14014000
5966 01:57:28.477866 <6>[ 2.062505] cpu cpu0: EM: created perf domain
5967 01:57:28.487733 <6>[ 2.068024] cpufreq: cpufreq_online: CPU4: Running at unlisted initial frequency: 1199999 KHz, changing to: 1248000 KHz
5968 01:57:28.494759 <6>[ 2.079304] cpu cpu4: EM: created perf domain
5969 01:57:28.501901 <6>[ 2.086390] sdhci: Secure Digital Host Controller Interface driver
5970 01:57:28.508434 <6>[ 2.092846] sdhci: Copyright(c) Pierre Ossman
5971 01:57:28.515184 <6>[ 2.098261] Synopsys Designware Multimedia Card Interface Driver
5972 01:57:28.521640 <6>[ 2.098810] mtk-msdc 11240000.mmc: allocated mmc-pwrseq
5973 01:57:28.524708 <6>[ 2.105324] sdhci-pltfm: SDHCI platform and OF driver helper
5974 01:57:28.534052 <6>[ 2.118872] ledtrig-cpu: registered to indicate activity on CPUs
5975 01:57:28.542130 <6>[ 2.126632] usbcore: registered new interface driver usbhid
5976 01:57:28.545556 <6>[ 2.132471] usbhid: USB HID core driver
5977 01:57:28.556117 <6>[ 2.136787] spi_master spi2: will run message pump with realtime priority
5978 01:57:28.559522 <4>[ 2.137006] i2c_hid_of 2-002c: supply vdd not found, using dummy regulator
5979 01:57:28.566808 <4>[ 2.151086] i2c_hid_of 2-002c: supply vddl not found, using dummy regulator
5980 01:57:28.580172 <6>[ 2.154531] input: cros_ec as /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:keyboard-controller/input/input0
5981 01:57:28.598549 <6>[ 2.173162] input: cros_ec_buttons as /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:keyboard-controller/input/input1
5982 01:57:28.605003 <4>[ 2.182302] mmc1: queuing unknown CIS tuple 0x01 [d9 01 ff] (3 bytes)
5983 01:57:28.611801 <6>[ 2.194460] cros-ec-spi spi2.0: Chrome EC device registered
5984 01:57:28.617946 <4>[ 2.202184] mmc1: queuing unknown CIS tuple 0x1a [01 01 00 02 07] (5 bytes)
5985 01:57:28.631868 <4>[ 2.213405] mmc1: queuing unknown CIS tuple 0x1b [c1 41 30 30 ff ff 32 00] (8 bytes)
5986 01:57:28.638449 <4>[ 2.222266] mmc1: queuing unknown CIS tuple 0x14 [] (0 bytes)
5987 01:57:28.651284 <6>[ 2.232488] mmc1: new ultra high speed SDR104 SDIO card at address 0001
5988 01:57:28.663834 <6>[ 2.248563] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x11c14
5989 01:57:28.671151 <6>[ 2.254957] mmc0: new HS400 MMC card at address 0001
5990 01:57:28.677223 <6>[ 2.261009] mmcblk0: mmc0:0001 TB2932 29.2 GiB
5991 01:57:28.684434 <6>[ 2.269363] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
5992 01:57:28.693482 <6>[ 2.278764] mmcblk0boot0: mmc0:0001 TB2932 4.00 MiB
5993 01:57:28.700875 <6>[ 2.285602] mmcblk0boot1: mmc0:0001 TB2932 4.00 MiB
5994 01:57:28.707261 <6>[ 2.292171] mmcblk0rpmb: mmc0:0001 TB2932 4.00 MiB, chardev (507:0)
5995 01:57:28.717530 <6>[ 2.295408] mt6358-sound mt6358-sound: mt6358_platform_driver_probe(), dev name mt6358-sound
5996 01:57:28.731449 <6>[ 2.305714] input: hid-over-i2c 06CB:CDB5 Mouse as /devices/platform/soc/11009000.i2c/i2c-2/2-002c/0018:06CB:CDB5.0001/input/input2
5997 01:57:28.740886 <6>[ 2.311008] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
5998 01:57:28.751226 <6>[ 2.319648] hid-generic 0018:06CB:CDB5.0001: input: I2C HID v1.00 Mouse [hid-over-i2c 06CB:CDB5] on 2-002c
5999 01:57:28.754585 <6>[ 2.331886] NET: Registered PF_PACKET protocol family
6000 01:57:28.760834 <6>[ 2.345728] 9pnet: Installing 9P2000 support
6001 01:57:28.764690 <5>[ 2.350310] Key type dns_resolver registered
6002 01:57:28.771051 <6>[ 2.355646] registered taskstats version 1
6003 01:57:28.774360 <5>[ 2.360168] Loading compiled-in X.509 certificates
6004 01:57:28.784247 <6>[ 2.365592] usb 1-1: new high-speed USB device number 2 using xhci-mtk
6005 01:57:28.819200 <3>[ 2.400795] anx7625 4-0058: [drm:anx7625_link_bridge] *ERROR* fail to parse DT for panel : -517
6006 01:57:28.851015 <6>[ 2.429253] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6007 01:57:28.862097 <6>[ 2.443601] mtk-iommu 10205000.iommu: bound 14017000.larb (ops mtk_smi_larb_component_ops)
6008 01:57:28.872146 <6>[ 2.452186] mtk-iommu 10205000.iommu: bound 16010000.larb (ops mtk_smi_larb_component_ops)
6009 01:57:28.879420 <6>[ 2.460935] mtk-iommu 10205000.iommu: bound 1502f000.larb (ops mtk_smi_larb_component_ops)
6010 01:57:28.888684 <6>[ 2.469528] mtk-iommu 10205000.iommu: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
6011 01:57:28.894997 <6>[ 2.478059] mtk-iommu 10205000.iommu: bound 17010000.larb (ops mtk_smi_larb_component_ops)
6012 01:57:28.905135 <6>[ 2.486581] mtk-iommu 10205000.iommu: bound 15021000.larb (ops mtk_smi_larb_component_ops)
6013 01:57:28.915721 <6>[ 2.495101] mtk-iommu 10205000.iommu: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
6014 01:57:28.921624 <6>[ 2.504455] mediatek-disp-ovl 14008000.ovl: Adding to iommu group 0
6015 01:57:28.928356 <6>[ 2.511994] mediatek-disp-ovl 14009000.ovl: Adding to iommu group 0
6016 01:57:28.935151 <6>[ 2.519319] mediatek-disp-ovl 1400a000.ovl: Adding to iommu group 0
6017 01:57:28.941934 <6>[ 2.521136] hub 1-1:1.0: USB hub found
6018 01:57:28.948328 <6>[ 2.526633] mediatek-disp-rdma 1400b000.rdma: Adding to iommu group 0
6019 01:57:28.952022 <6>[ 2.530401] hub 1-1:1.0: 3 ports detected
6020 01:57:28.958421 <6>[ 2.537313] mediatek-disp-rdma 1400c000.rdma: Adding to iommu group 0
6021 01:57:28.964889 <6>[ 2.549244] panfrost 13040000.gpu: clock rate = 511999970
6022 01:57:28.975070 <6>[ 2.554950] panfrost 13040000.gpu: [drm:panfrost_devfreq_init] More than 1 supply is not supported yet
6023 01:57:28.985425 <6>[ 2.565006] panfrost 13040000.gpu: mali-g72 id 0x6221 major 0x0 minor 0x3 status 0x0
6024 01:57:28.991733 <6>[ 2.573015] panfrost 13040000.gpu: features: 00000000,000004f7, issues: 00000000,00000400
6025 01:57:29.004543 <6>[ 2.581448] panfrost 13040000.gpu: Features: L2:0x07120206 Shader:0x00000000 Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7
6026 01:57:29.011053 <6>[ 2.593529] panfrost 13040000.gpu: shader_present=0x7 l2_present=0x1
6027 01:57:29.022646 <6>[ 2.603963] [drm] Initialized panfrost 1.2.0 20180908 for 13040000.gpu on minor 0
6028 01:57:29.032818 <6>[ 2.612807] mediatek-drm mediatek-drm.1.auto: bound 14008000.ovl (ops mtk_disp_ovl_component_ops)
6029 01:57:29.042932 <6>[ 2.621955] mediatek-drm mediatek-drm.1.auto: bound 14009000.ovl (ops mtk_disp_ovl_component_ops)
6030 01:57:29.049358 <6>[ 2.631086] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ovl (ops mtk_disp_ovl_component_ops)
6031 01:57:29.059535 <6>[ 2.640213] mediatek-drm mediatek-drm.1.auto: bound 1400b000.rdma (ops mtk_disp_rdma_component_ops)
6032 01:57:29.069370 <6>[ 2.649513] mediatek-drm mediatek-drm.1.auto: bound 1400c000.rdma (ops mtk_disp_rdma_component_ops)
6033 01:57:29.078988 <6>[ 2.658814] mediatek-drm mediatek-drm.1.auto: bound 1400e000.color (ops mtk_disp_color_component_ops)
6034 01:57:29.089029 <6>[ 2.668287] mediatek-drm mediatek-drm.1.auto: bound 1400f000.ccorr (ops mtk_disp_ccorr_component_ops)
6035 01:57:29.096373 <6>[ 2.677761] mediatek-drm mediatek-drm.1.auto: bound 14010000.aal (ops mtk_disp_aal_component_ops)
6036 01:57:29.106016 <6>[ 2.686887] mediatek-drm mediatek-drm.1.auto: bound 14011000.gamma (ops mtk_disp_gamma_component_ops)
6037 01:57:29.180355 <6>[ 2.761455] mediatek-drm mediatek-drm.1.auto: bound 14014000.dsi (ops mtk_dsi_component_ops)
6038 01:57:29.189967 <6>[ 2.770380] mediatek-drm mediatek-drm.1.auto: Not creating crtc 1 because component 10 is disabled or missing
6039 01:57:29.201424 <6>[ 2.782883] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 1
6040 01:57:29.248189 <6>[ 2.829630] usb 1-1.2: new high-speed USB device number 3 using xhci-mtk
6041 01:57:29.894179 <6>[ 3.013877] r8152-cfgselector 1-1.2: reset high-speed USB device number 3 using xhci-mtk
6042 01:57:29.903793 <4>[ 3.117280] r8152 1-1.2:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
6043 01:57:29.910555 <4>[ 3.117297] r8152 1-1.2:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
6044 01:57:29.917347 <6>[ 3.154728] r8152 1-1.2:1.0 eth0: v1.12.13
6045 01:57:29.923676 <6>[ 3.233648] usb 1-1.3: new high-speed USB device number 4 using xhci-mtk
6046 01:57:29.930874 <6>[ 3.459079] Console: switching to colour frame buffer device 170x48
6047 01:57:29.937386 <6>[ 3.519746] mediatek-drm mediatek-drm.1.auto: [drm] fb0: mediatekdrmfb frame buffer device
6048 01:57:29.958027 <6>[ 3.535835] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6049 01:57:29.975117 <6>[ 3.552899] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6050 01:57:29.981757 <6>[ 3.565423] input: wifi-wakeup as /devices/platform/wifi-wakeup/input/input4
6051 01:57:29.992996 <6>[ 3.573668] input: volume-buttons as /devices/platform/volume-buttons/input/input5
6052 01:57:30.002275 <6>[ 3.580215] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6053 01:57:30.021457 <6>[ 3.599567] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6054 01:57:31.152964 <6>[ 4.737481] r8152 1-1.2:1.0 eth0: carrier on
6055 01:57:33.361139 <5>[ 4.761618] Sending DHCP requests .., OK
6056 01:57:33.367885 <6>[ 6.950000] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.23
6057 01:57:33.371043 <6>[ 6.958467] IP-Config: Complete:
6058 01:57:33.384157 <6>[ 6.962040] device=eth0, hwaddr=00:e0:4c:71:a7:1f, ipaddr=192.168.201.23, mask=255.255.255.0, gw=192.168.201.1
6059 01:57:33.393756 <6>[ 6.972946] host=mt8183-kukui-jacuzzi-juniper-sku16-cbg-3, domain=lava-rack, nis-domain=(none)
6060 01:57:33.406287 <6>[ 6.987321] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
6061 01:57:33.414481 <6>[ 6.987332] nameserver0=192.168.201.1
6062 01:57:33.422655 <6>[ 7.007218] clk: Disabling unused clocks
6063 01:57:33.427589 <6>[ 7.015164] ALSA device list:
6064 01:57:33.436544 <6>[ 7.021213] No soundcards found.
6065 01:57:33.445999 <6>[ 7.030236] Freeing unused kernel memory: 8512K
6066 01:57:33.452655 <6>[ 7.037392] Run /init as init process
6067 01:57:33.466970 Loading, please wait...
6068 01:57:33.497045 Starting systemd-udevd version 252.22-1~deb12u1
6069 01:57:33.808946 <6>[ 7.390268] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
6070 01:57:33.826207 <4>[ 7.407575] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: No cache defaults, reading back from HW
6071 01:57:33.832637 <3>[ 7.413501] mtk-scp 10500000.scp: invalid resource
6072 01:57:33.843595 <6>[ 7.424324] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 20
6073 01:57:33.853145 <6>[ 7.424739] mtk-scp 10500000.scp: assigned reserved memory node memory@50000000
6074 01:57:33.863448 <6>[ 7.439417] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6075 01:57:33.873445 <3>[ 7.445339] mt8183-pinctrl 10005000.pinctrl: pin GPIO7 already requested by 2-002c; cannot claim for 2-0015
6076 01:57:33.876629 <6>[ 7.453584] mc: Linux media interface: v0.10
6077 01:57:33.886628 <4>[ 7.453825] elants_i2c 0-0010: supply vcc33 not found, using dummy regulator
6078 01:57:33.893181 <4>[ 7.453942] elants_i2c 0-0010: supply vccio not found, using dummy regulator
6079 01:57:33.899668 <6>[ 7.462731] remoteproc remoteproc0: scp is available
6080 01:57:33.906360 <3>[ 7.463105] mt8183-pinctrl 10005000.pinctrl: pin-7 (2-0015) status -22
6081 01:57:33.916391 <4>[ 7.463499] remoteproc remoteproc0: Direct firmware load for scp.img failed with error -2
6082 01:57:33.922778 <6>[ 7.463512] remoteproc remoteproc0: powering up scp
6083 01:57:33.929713 <4>[ 7.463538] remoteproc remoteproc0: Direct firmware load for scp.img failed with error -2
6084 01:57:33.936361 <3>[ 7.463543] remoteproc remoteproc0: request_firmware failed: -2
6085 01:57:33.947620 <5>[ 7.497551] cfg80211: Loading compiled-in X.509 certificates for regulatory database
6086 01:57:33.957121 <3>[ 7.497639] mt8183-pinctrl 10005000.pinctrl: could not request pin 7 (GPIO7) from group GPIO7 on device pinctrl_paris
6087 01:57:33.963983 <5>[ 7.515767] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
6088 01:57:33.974330 <3>[ 7.520491] elan_i2c 2-0015: Error applying setting, reverse things back
6089 01:57:33.984321 <3>[ 7.527167] debugfs: Directory '11220000.audio-controller:mt8183-afe-pcm' with parent 'mt8183_mt6358_ts3a227_max98357' already present!
6090 01:57:33.991087 <6>[ 7.527179] videodev: Linux video capture interface: v2.00
6091 01:57:34.000951 <3>[ 7.528642] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6092 01:57:34.008334 <5>[ 7.529279] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
6093 01:57:34.017752 <4>[ 7.529361] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
6094 01:57:34.024699 <6>[ 7.529370] cfg80211: failed to load regulatory.db
6095 01:57:34.031587 <6>[ 7.556299] cs_system_cfg: CoreSight Configuration manager initialised
6096 01:57:34.041447 <3>[ 7.563028] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6097 01:57:34.051041 <6>[ 7.584294] sbs-battery 12-000b: sbs-battery: battery gas gauge device registered
6098 01:57:34.058166 <6>[ 7.589464] input: Elan Touchscreen as /devices/platform/soc/11007000.i2c/i2c-0/0-0010/input/input7
6099 01:57:34.067859 <3>[ 7.590908] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6100 01:57:34.074877 <6>[ 7.617688] coresight-cpu-debug d410000.cpu-debug: Coresight debug-CPU0 initialized
6101 01:57:34.084629 <3>[ 7.630979] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6102 01:57:34.091050 <6>[ 7.632106] coresight-cpu-debug d510000.cpu-debug: Coresight debug-CPU1 initialized
6103 01:57:34.101502 <3>[ 7.641073] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6104 01:57:34.107940 <6>[ 7.649420] coresight-cpu-debug d610000.cpu-debug: Coresight debug-CPU2 initialized
6105 01:57:34.114418 <6>[ 7.651989] usb 1-1.3: Found UVC 1.00 device HD WebCam (04f2:b567)
6106 01:57:34.124401 <3>[ 7.657617] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6107 01:57:34.131042 <6>[ 7.665698] coresight-cpu-debug d710000.cpu-debug: Coresight debug-CPU3 initialized
6108 01:57:34.134345 <6>[ 7.666225] Bluetooth: Core ver 2.22
6109 01:57:34.141320 <6>[ 7.666267] NET: Registered PF_BLUETOOTH protocol family
6110 01:57:34.147831 <6>[ 7.666269] Bluetooth: HCI device and connection manager initialized
6111 01:57:34.158016 <3>[ 7.674162] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6112 01:57:34.164789 <6>[ 7.674225] Bluetooth: HCI socket layer initialized
6113 01:57:34.171756 <6>[ 7.674237] Bluetooth: L2CAP socket layer initialized
6114 01:57:34.174745 <6>[ 7.674251] Bluetooth: SCO socket layer initialized
6115 01:57:34.188636 <3>[ 7.674263] mt8183_mt6358_ts3a227 mt8183-sound: ASoC: driver name too long 'mt8183_mt6358_ts3a227_max98357' -> 'mt8183_mt6358_t'
6116 01:57:34.195143 <3>[ 7.675046] debugfs: File 'Playback' in directory 'dapm' already present!
6117 01:57:34.205451 <3>[ 7.675051] debugfs: File 'Capture' in directory 'dapm' already present!
6118 01:57:34.215558 <6>[ 7.676317] input: mt8183_mt6358_ts3a227_max98357 Headset Jack as /devices/platform/mt8183-sound/sound/card0/input6
6119 01:57:34.222162 <3>[ 7.678973] thermal_sys: Failed to find 'trips' node
6120 01:57:34.228898 <3>[ 7.678977] thermal_sys: Failed to find trip points for thermal-sensor1 id=0
6121 01:57:34.239513 <3>[ 7.678985] generic-adc-thermal thermal-sensor1: Thermal zone sensor register failed: -22
6122 01:57:34.246180 <4>[ 7.678989] generic-adc-thermal: probe of thermal-sensor1 failed with error -22
6123 01:57:34.252934 <3>[ 7.681473] thermal_sys: Failed to find 'trips' node
6124 01:57:34.259560 <3>[ 7.681477] thermal_sys: Failed to find trip points for thermal-sensor2 id=0
6125 01:57:34.270044 <3>[ 7.681485] generic-adc-thermal thermal-sensor2: Thermal zone sensor register failed: -22
6126 01:57:34.276785 <4>[ 7.681489] generic-adc-thermal: probe of thermal-sensor2 failed with error -22
6127 01:57:34.286774 <6>[ 7.682176] coresight-cpu-debug d810000.cpu-debug: Coresight debug-CPU4 initialized
6128 01:57:34.293095 <6>[ 7.682698] mtk-mdp3 14001000.dma-controller0: Adding to iommu group 0
6129 01:57:34.299769 <6>[ 7.683188] mtk-jpeg 17030000.venc_jpg: Adding to iommu group 0
6130 01:57:34.310011 <6>[ 7.684325] mtk-jpeg 17030000.venc_jpg: mtk-jpeg-enc device registered as /dev/video0 (81,0)
6131 01:57:34.316613 <6>[ 7.684412] mtk-mdp3 14001000.dma-controller0: Driver registered as /dev/video1
6132 01:57:34.330279 <6>[ 7.685368] input: HD WebCam: HD WebCam as /devices/platform/soc/11201000.usb/11200000.usb/usb1/1-1/1-1.3/1-1.3:1.0/input/input8
6133 01:57:34.336525 <6>[ 7.685874] usbcore: registered new interface driver uvcvideo
6134 01:57:34.347148 <3>[ 7.690430] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6135 01:57:34.353337 <6>[ 7.698555] coresight-cpu-debug d910000.cpu-debug: Coresight debug-CPU5 initialized
6136 01:57:34.364657 <3>[ 7.704967] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6137 01:57:34.375130 <6>[ 7.713464] coresight-cpu-debug da10000.cpu-debug: Coresight debug-CPU6 initialized
6138 01:57:34.382218 <6>[ 7.713643] Bluetooth: HCI UART driver ver 2.3
6139 01:57:34.388679 <6>[ 7.713648] Bluetooth: HCI UART protocol H4 registered
6140 01:57:34.396205 <6>[ 7.713684] Bluetooth: HCI UART protocol LL registered
6141 01:57:34.403889 <6>[ 7.713697] Bluetooth: HCI UART protocol Three-wire (H5) registered
6142 01:57:34.412482 <6>[ 7.714010] Bluetooth: HCI UART protocol Broadcom registered
6143 01:57:34.420333 <6>[ 7.714029] Bluetooth: HCI UART protocol QCA registered
6144 01:57:34.427507 <6>[ 7.714041] Bluetooth: HCI UART protocol Marvell registered
6145 01:57:34.435628 <6>[ 7.714945] Bluetooth: hci0: setting up ROME/QCA6390
6146 01:57:34.446101 <6>[ 7.718552] ath10k_sdio mmc1:0001:1: qca6174 hw3.2 sdio target 0x05030000 chip_id 0x00000000 sub 0000:0000
6147 01:57:34.457866 <6>[ 7.718558] ath10k_sdio mmc1:0001:1: kconfig debug 0 debugfs 0 tracing 0 dfs 0 testmode 0
6148 01:57:34.471848 <6>[ 7.718648] ath10k_sdio mmc1:0001:1: firmware ver WLAN.RMH.4.4.1-00174 api 6 features wowlan,ignore-otp,mfp crc32 7319fa77
6149 01:57:34.481841 <6>[ 7.866679] ath10k_sdio mmc1:0001:1: board_file api 2 bmi_id 0:4 crc32 d2863f91
6150 01:57:34.491749 <6>[ 7.868237] coresight-cpu-debug db10000.cpu-debug: Coresight debug-CPU7 initialized
6151 01:57:34.498765 <3>[ 7.932659] Bluetooth: hci0: Frame reassembly failed (-84)
6152 01:57:34.566280 Begin: Loading e<4>[ 8.144743] sbs-battery 12-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
6153 01:57:34.569182 <4>[ 8.144743] Fallback method does not support PEC.
6154 01:57:34.573974 ssential drivers ... done.
6155 01:57:34.577583 Begin: Running /scripts/init-premount ... done.
6156 01:57:34.584359 Beg<3>[ 8.165126] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6157 01:57:34.591457 in: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
6158 01:57:34.601560 Begin: Running /scr<3>[ 8.182382] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6159 01:57:34.607930 ipts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
6160 01:57:34.615087 Device /sys/cl<6>[ 8.198189] Bluetooth: hci0: QCA Product ID :0x00000008
6161 01:57:34.618491 ass/net/eth0 found
6162 01:57:34.618950 done.
6163 01:57:34.624553 <6>[ 8.207212] Bluetooth: hci0: QCA SOC Version :0x00000044
6164 01:57:34.631299 <6>[ 8.215850] Bluetooth: hci0: QCA ROM Version :0x00000302
6165 01:57:34.641492 Begin: Waiting up to 180 secs for any network de<6>[ 8.225178] Bluetooth: hci0: QCA Patch Version:0x00000111
6166 01:57:34.644941 vice to become available ... done.
6167 01:57:34.651279 <6>[ 8.235186] Bluetooth: hci0: QCA controller version 0x00440302
6168 01:57:34.663263 <6>[ 8.244233] Bluetooth: hci0: QCA Downloading qca/rampatch_00440302.bin
6169 01:57:34.672679 <4>[ 8.253915] bluetooth hci0: Direct firmware load for qca/rampatch_00440302.bin failed with error -2
6170 01:57:34.686057 IP-Config: eth0 hardware address<3>[ 8.265654] Bluetooth: hci0: QCA Failed to request file: qca/rampatch_00440302.bin (-2)
6171 01:57:34.692598 00:e0:4c:71:a7:1f mtu 1500 DHCP<3>[ 8.276236] Bluetooth: hci0: QCA Failed to download patch (-2)
6172 01:57:34.693022
6173 01:57:34.699674 IP-Config: eth0 complete (dhcp from 192.168.201.1):
6174 01:57:34.705973 address: 192.168.201.23 broadcast: 192.168.201.255 netmask: 255.255.255.0
6175 01:57:34.712705 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
6176 01:57:34.718975 host : mt8183-kukui-jacuzzi-juniper-sku16-cbg-3
6177 01:57:34.725735 domain : lava-rack
6178 01:57:34.729156 rootserver: 192.168.201.1 rootpath:
6179 01:57:34.729655 filename :
6180 01:57:34.852927 <6>[ 8.434628] ath10k_sdio mmc1:0001:1: htt-ver 3.87 wmi-op 4 htt-op 3 cal otp max-sta 32 raw 0 hwcrypto 1
6181 01:57:34.875214 done.
6182 01:57:34.882391 Begin: Running /scripts/nfs-bottom ... done.
6183 01:57:34.896175 Begin: Running /scripts/init-bottom ... done.
6184 01:57:34.937808 <4>[ 8.521973] mmc1: queuing unknown CIS tuple 0x01 [d9 01 ff] (3 bytes)
6185 01:57:34.958907 <4>[ 8.540444] mmc1: queuing unknown CIS tuple 0x1a [01 01 00 02 07] (5 bytes)
6186 01:57:34.972493 <4>[ 8.553792] mmc1: queuing unknown CIS tuple 0x1b [c1 41 30 30 ff ff 32 00] (8 bytes)
6187 01:57:34.980479 <4>[ 8.564732] mmc1: queuing unknown CIS tuple 0x14 [] (0 bytes)
6188 01:57:36.264165 <6>[ 9.848978] NET: Registered PF_INET6 protocol family
6189 01:57:36.275204 <6>[ 9.860172] Segment Routing with IPv6
6190 01:57:36.283201 <6>[ 9.868066] In-situ OAM (IOAM) with IPv6
6191 01:57:36.471187 <30>[ 10.028725] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
6192 01:57:36.490362 <30>[ 10.074458] systemd[1]: Detected architecture arm64.
6193 01:57:36.502819
6194 01:57:36.505937 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
6195 01:57:36.506358
6196 01:57:36.531438 <30>[ 10.116021] systemd[1]: Hostname set to <debian-bookworm-arm64>.
6197 01:57:37.681770 <30>[ 11.263018] systemd[1]: Queued start job for default target graphical.target.
6198 01:57:37.717840 <30>[ 11.298885] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
6199 01:57:37.730443 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
6200 01:57:37.750616 <30>[ 11.331757] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
6201 01:57:37.763011 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
6202 01:57:37.782771 <30>[ 11.364026] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
6203 01:57:37.796302 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
6204 01:57:37.814234 <30>[ 11.395361] systemd[1]: Created slice user.slice - User and Session Slice.
6205 01:57:37.825684 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
6206 01:57:37.848478 <30>[ 11.426219] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
6207 01:57:37.861149 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
6208 01:57:37.880135 <30>[ 11.458007] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
6209 01:57:37.891975 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
6210 01:57:37.919063 <30>[ 11.489949] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
6211 01:57:37.937787 <30>[ 11.518897] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
6212 01:57:37.945746 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
6213 01:57:37.964496 <30>[ 11.545787] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
6214 01:57:37.977400 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
6215 01:57:37.996763 <30>[ 11.577832] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
6216 01:57:38.010743 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
6217 01:57:38.025410 <30>[ 11.609891] systemd[1]: Reached target paths.target - Path Units.
6218 01:57:38.039891 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
6219 01:57:38.056791 <30>[ 11.637778] systemd[1]: Reached target remote-fs.target - Remote File Systems.
6220 01:57:38.068962 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
6221 01:57:38.081312 <30>[ 11.665744] systemd[1]: Reached target slices.target - Slice Units.
6222 01:57:38.095648 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
6223 01:57:38.108976 <30>[ 11.693792] systemd[1]: Reached target swap.target - Swaps.
6224 01:57:38.119446 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
6225 01:57:38.141005 <30>[ 11.721840] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
6226 01:57:38.154144 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
6227 01:57:38.173124 <30>[ 11.754175] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
6228 01:57:38.186758 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
6229 01:57:38.208502 <30>[ 11.789436] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
6230 01:57:38.218953 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
6231 01:57:38.239057 <30>[ 11.820156] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
6232 01:57:38.253654 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
6233 01:57:38.273600 <30>[ 11.854466] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
6234 01:57:38.285692 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
6235 01:57:38.306677 <30>[ 11.887773] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
6236 01:57:38.320030 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
6237 01:57:38.340051 <30>[ 11.921287] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
6238 01:57:38.353338 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
6239 01:57:38.372993 <30>[ 11.954379] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
6240 01:57:38.385919 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
6241 01:57:38.428509 <30>[ 12.009959] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
6242 01:57:38.440753 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
6243 01:57:38.463822 <30>[ 12.045114] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
6244 01:57:38.474992 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
6245 01:57:38.497369 <30>[ 12.078748] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
6246 01:57:38.510943 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
6247 01:57:38.535547 <30>[ 12.110435] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
6248 01:57:38.577360 <30>[ 12.158763] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
6249 01:57:38.590207 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
6250 01:57:38.615023 <30>[ 12.196192] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
6251 01:57:38.626004 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
6252 01:57:38.650302 <30>[ 12.231536] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
6253 01:57:38.661093 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
6254 01:57:38.695671 <6>[ 12.276830] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
6255 01:57:38.717737 <30>[ 12.298817] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
6256 01:57:38.729564 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
6257 01:57:38.755852 <30>[ 12.336790] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
6258 01:57:38.769747 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
6259 01:57:38.794345 <30>[ 12.375613] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
6260 01:57:38.807691 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
6261 01:57:38.835509 <30>[ 12.416793] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
6262 01:57:38.848133 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
6263 01:57:38.884419 <6>[ 12.468484] fuse: init (API version 7.37)
6264 01:57:38.917790 <30>[ 12.498986] systemd[1]: Starting systemd-journald.service - Journal Service...
6265 01:57:38.930818 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
6266 01:57:38.952847 <30>[ 12.534490] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
6267 01:57:38.963909 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
6268 01:57:38.989978 <30>[ 12.568034] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
6269 01:57:39.001533 Starting [0;1;39msystemd-network-g… units from Kernel command line...
6270 01:57:39.031312 <30>[ 12.612704] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
6271 01:57:39.045302 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
6272 01:57:39.071626 <30>[ 12.652586] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
6273 01:57:39.083546 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
6274 01:57:39.106922 <30>[ 12.688328] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
6275 01:57:39.117816 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
6276 01:57:39.137310 <30>[ 12.718388] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
6277 01:57:39.156834 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue <3>[ 12.736643] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6278 01:57:39.157395 File System.
6279 01:57:39.171592 <3>[ 12.752819] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6280 01:57:39.183049 <30>[ 12.763361] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
6281 01:57:39.189767 <3>[ 12.770851] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6282 01:57:39.208175 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug <3>[ 12.788135] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6283 01:57:39.208617 File System.
6284 01:57:39.223863 <3>[ 12.804802] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6285 01:57:39.233733 <30>[ 12.814236] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
6286 01:57:39.249565 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate <3>[ 12.831477] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6287 01:57:39.252615 List of Static Device Nodes.
6288 01:57:39.266468 <3>[ 12.847983] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6289 01:57:39.276386 <30>[ 12.859291] systemd[1]: modprobe@configfs.service: Deactivated successfully.
6290 01:57:39.286037 <3>[ 12.863956] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6291 01:57:39.293334 <30>[ 12.867293] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
6292 01:57:39.305917 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
6293 01:57:39.324989 <30>[ 12.906492] systemd[1]: Started systemd-journald.service - Journal Service.
6294 01:57:39.335696 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
6295 01:57:39.361638 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
6296 01:57:39.387826 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
6297 01:57:39.407746 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
6298 01:57:39.431390 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
6299 01:57:39.451712 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
6300 01:57:39.474633 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
6301 01:57:39.498165 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
6302 01:57:39.522370 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
6303 01:57:39.547558 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
6304 01:57:39.567723 <4>[ 13.141992] synth uevent: /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:i2c-tunnel/i2c-12/12-000b/power_supply/sbs-12-000b: failed to send uevent
6305 01:57:39.578411 <3>[ 13.159742] power_supply sbs-12-000b: uevent: failed to send synthetic uevent: -5
6306 01:57:39.590143 <4>[ 13.174515] power_supply_show_property: 3 callbacks suppressed
6307 01:57:39.603355 <3>[ 13.174529] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6308 01:57:39.626405 Mountin<3>[ 13.208067] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6309 01:57:39.633056 g [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
6310 01:57:39.647413 <3>[ 13.228156] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6311 01:57:39.668637 Mounting [0;1;39msys-kernel-config…ernel Configuration File System..<3>[ 13.247683] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6312 01:57:39.669213 .
6313 01:57:39.687953 <3>[ 13.268859] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6314 01:57:39.703963 <3>[ 13.285003] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6315 01:57:39.722117 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage..<3>[ 13.301822] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6316 01:57:39.722565 .
6317 01:57:39.737646 <3>[ 13.318342] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6318 01:57:39.756220 <3>[ 13.337258] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6319 01:57:39.777134 <3>[ 13.358227] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6320 01:57:39.793345 Starting [0;1;39msystemd-random-se…ice[0m - Load/Sa<46>[ 13.375006] systemd-journald[319]: Received client request to flush runtime journal.
6321 01:57:39.796486 ve Random Seed...
6322 01:57:39.823504 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
6323 01:57:39.849795 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
6324 01:57:40.122300 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
6325 01:57:40.146292 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
6326 01:57:40.165124 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
6327 01:57:40.186250 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
6328 01:57:40.920637 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
6329 01:57:40.939026 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
6330 01:57:40.990072 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
6331 01:57:41.265891 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
6332 01:57:41.399660 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
6333 01:57:41.418268 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
6334 01:57:41.437506 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
6335 01:57:41.477987 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
6336 01:57:41.504932 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
6337 01:57:41.784997 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
6338 01:57:41.845104 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
6339 01:57:41.890355 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
6340 01:57:42.133189 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
6341 01:57:42.152379 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
6342 01:57:42.201207 Starting [0;1;39msystemd-backlight…ess of backlight:backlight_lcd0...
6343 01:57:42.222143 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
6344 01:57:42.262219 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
6345 01:57:42.345581 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
6346 01:57:42.370968 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
6347 01:57:42.387994 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
6348 01:57:42.410670 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of backlight:backlight_lcd0.
6349 01:57:42.543061 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
6350 01:57:42.608639 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
6351 01:57:42.622718 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
6352 01:57:42.666240 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
6353 01:57:42.690343 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
6354 01:57:42.715126 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
6355 01:57:42.748724 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
6356 01:57:42.771099 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
6357 01:57:42.797021 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
6358 01:57:42.815978 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
6359 01:57:42.839342 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
6360 01:57:42.861166 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
6361 01:57:42.882849 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
6362 01:57:42.908967 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
6363 01:57:42.928488 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
6364 01:57:42.945441 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
6365 01:57:42.965502 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
6366 01:57:42.984901 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
6367 01:57:43.002032 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
6368 01:57:43.017329 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
6369 01:57:43.036142 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
6370 01:57:43.054157 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
6371 01:57:43.070382 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
6372 01:57:43.112331 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
6373 01:57:43.133146 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
6374 01:57:43.193241 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
6375 01:57:43.351054 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
6376 01:57:43.378964 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
6377 01:57:43.416309 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
6378 01:57:43.436559 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
6379 01:57:43.518636 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
6380 01:57:43.540917 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
6381 01:57:43.588834 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
6382 01:57:43.645363 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
6383 01:57:43.666153 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
6384 01:57:43.690032 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
6385 01:57:43.713373 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
6386 01:57:43.732153 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
6387 01:57:43.751461 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
6388 01:57:43.794909 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
6389 01:57:43.855349 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
6390 01:57:43.949044
6391 01:57:43.952108 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
6392 01:57:43.952536
6393 01:57:43.955452 debian-bookworm-arm64 login: root (automatic login)
6394 01:57:43.955874
6395 01:57:44.283280 Linux debian-bookworm-arm64 6.1.94-cip23 #1 SMP PREEMPT Fri Jun 21 00:04:56 UTC 2024 aarch64
6396 01:57:44.283812
6397 01:57:44.290592 The programs included with the Debian GNU/Linux system are free software;
6398 01:57:44.296611 the exact distribution terms for each program are described in the
6399 01:57:44.299829 individual files in /usr/share/doc/*/copyright.
6400 01:57:44.300261
6401 01:57:44.306707 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
6402 01:57:44.310158 permitted by applicable law.
6403 01:57:45.514188 Matched prompt #10: / #
6405 01:57:45.515331 Setting prompt string to ['/ #']
6406 01:57:45.515774 end: 2.2.5.1 login-action (duration 00:00:20) [common]
6408 01:57:45.516757 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
6409 01:57:45.517207 start: 2.2.6 expect-shell-connection (timeout 00:03:45) [common]
6410 01:57:45.517592 Setting prompt string to ['/ #']
6411 01:57:45.517907 Forcing a shell prompt, looking for ['/ #']
6413 01:57:45.568690 / #
6414 01:57:45.569069 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
6415 01:57:45.569357 Waiting using forced prompt support (timeout 00:02:30)
6416 01:57:45.574051
6417 01:57:45.574750 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
6418 01:57:45.575125 start: 2.2.7 export-device-env (timeout 00:03:45) [common]
6420 01:57:45.676253 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14479169/extract-nfsrootfs-rq4f2012'
6421 01:57:45.682970 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14479169/extract-nfsrootfs-rq4f2012'
6423 01:57:45.784792 / # export NFS_SERVER_IP='192.168.201.1'
6424 01:57:45.791657 export NFS_SERVER_IP='192.168.201.1'
6425 01:57:45.792576 end: 2.2.7 export-device-env (duration 00:00:00) [common]
6426 01:57:45.793108 end: 2.2 depthcharge-retry (duration 00:01:16) [common]
6427 01:57:45.793678 end: 2 depthcharge-action (duration 00:01:16) [common]
6428 01:57:45.794198 start: 3 lava-test-retry (timeout 00:08:06) [common]
6429 01:57:45.794690 start: 3.1 lava-test-shell (timeout 00:08:06) [common]
6430 01:57:45.795116 Using namespace: common
6432 01:57:45.896395 / # #
6433 01:57:45.897044 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
6434 01:57:45.902054 #
6435 01:57:45.902812 Using /lava-14479169
6437 01:57:46.003959 / # export SHELL=/bin/bash
6438 01:57:46.010260 export SHELL=/bin/bash
6440 01:57:46.112317 / # . /lava-14479169/environment
6441 01:57:46.118821 . /lava-14479169/environment
6443 01:57:46.226996 / # /lava-14479169/bin/lava-test-runner /lava-14479169/0
6444 01:57:46.227694 Test shell timeout: 10s (minimum of the action and connection timeout)
6445 01:57:46.233353 /lava-14479169/bin/lava-test-runner /lava-14479169/0
6446 01:57:46.525168 + export TESTRUN_ID=0_timesync-off
6447 01:57:46.528422 + TESTRUN_ID=0_timesync-off
6448 01:57:46.531712 + cd /lava-14479169/0/tests/0_timesync-off
6449 01:57:46.535191 ++ cat uuid
6450 01:57:46.543058 + UUID=14479169_1.6.2.3.1
6451 01:57:46.543655 + set +x
6452 01:57:46.549723 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14479169_1.6.2.3.1>
6453 01:57:46.550396 Received signal: <STARTRUN> 0_timesync-off 14479169_1.6.2.3.1
6454 01:57:46.550786 Starting test lava.0_timesync-off (14479169_1.6.2.3.1)
6455 01:57:46.551242 Skipping test definition patterns.
6456 01:57:46.553123 + systemctl stop systemd-timesyncd
6457 01:57:46.621486 + set +x
6458 01:57:46.624855 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14479169_1.6.2.3.1>
6459 01:57:46.625560 Received signal: <ENDRUN> 0_timesync-off 14479169_1.6.2.3.1
6460 01:57:46.625969 Ending use of test pattern.
6461 01:57:46.626312 Ending test lava.0_timesync-off (14479169_1.6.2.3.1), duration 0.08
6463 01:57:46.725964 + export TESTRUN_ID=1_kselftest-alsa
6464 01:57:46.729471 + TESTRUN_ID=1_kselftest-alsa
6465 01:57:46.735613 + cd /lava-14479169/0/tests/1_kselftest-alsa
6466 01:57:46.736052 ++ cat uuid
6467 01:57:46.741713 + UUID=14479169_1.6.2.3.5
6468 01:57:46.742354 + set +x
6469 01:57:46.748134 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 14479169_1.6.2.3.5>
6470 01:57:46.748954 Received signal: <STARTRUN> 1_kselftest-alsa 14479169_1.6.2.3.5
6471 01:57:46.749478 Starting test lava.1_kselftest-alsa (14479169_1.6.2.3.5)
6472 01:57:46.749875 Skipping test definition patterns.
6473 01:57:46.751158 + cd ./automated/linux/kselftest/
6474 01:57:46.777779 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.94-cip23/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8183-kukui-jacuzzi-juniper-sku16 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
6475 01:57:46.822403 INFO: install_deps skipped
6476 01:57:47.318821 --2024-06-21 01:57:47-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.94-cip23/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
6477 01:57:47.345147 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
6478 01:57:47.473975 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
6479 01:57:47.603051 HTTP request sent, awaiting response... 200 OK
6480 01:57:47.606463 Length: 1642760 (1.6M) [application/octet-stream]
6481 01:57:47.609845 Saving to: 'kselftest_armhf.tar.gz'
6482 01:57:47.610393
6483 01:57:47.610763
6484 01:57:47.864702 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
6485 01:57:48.122950 kselftest_armhf.tar 2%[ ] 44.98K 174KB/s
6486 01:57:48.428785 kselftest_armhf.tar 13%[=> ] 216.08K 419KB/s
6487 01:57:48.558597 kselftest_armhf.tar 51%[=========> ] 826.96K 1008KB/s
6488 01:57:48.564722 kselftest_armhf.tar 100%[===================>] 1.57M 1.65MB/s in 0.9s
6489 01:57:48.565217
6490 01:57:48.709089 2024-06-21 01:57:48 (1.65 MB/s) - 'kselftest_armhf.tar.gz' saved [1642760/1642760]
6491 01:57:48.709497
6492 01:57:53.199040 skiplist:
6493 01:57:53.202122 ========================================
6494 01:57:53.205763 ========================================
6495 01:57:53.251719 alsa:mixer-test
6496 01:57:53.271800 ============== Tests to run ===============
6497 01:57:53.272228 alsa:mixer-test
6498 01:57:53.275340 ===========End Tests to run ===============
6499 01:57:53.279810 shardfile-alsa pass
6500 01:57:53.398805 <12>[ 26.983225] kselftest: Running tests in alsa
6501 01:57:53.409839 TAP version 13
6502 01:57:53.425666 1..1
6503 01:57:53.445059 # selftests: alsa: mixer-test
6504 01:57:53.572636 <6>[ 27.150297] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_adda_dmic_set(), kcontrol name MTKAIF_DMIC, mtkaif_dmic 0
6505 01:57:53.585991 <6>[ 27.162969] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_adda_dmic_set(), kcontrol name MTKAIF_DMIC, mtkaif_dmic 0
6506 01:57:53.599610 <6>[ 27.175739] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_adda_dmic_set(), kcontrol name MTKAIF_DMIC, mtkaif_dmic 1
6507 01:57:53.612226 <6>[ 27.188361] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_adda_dmic_set(), kcontrol name MTKAIF_DMIC, mtkaif_dmic 0
6508 01:57:53.622358 <6>[ 27.200822] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_adda_dmic_set(), kcontrol name MTKAIF_DMIC, mtkaif_dmic 0
6509 01:57:53.635928 <6>[ 27.213241] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S5_HD_Mux, hd_en 0
6510 01:57:53.645969 <6>[ 27.224801] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S5_HD_Mux, hd_en 0
6511 01:57:53.659158 <6>[ 27.236390] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S5_HD_Mux, hd_en 1
6512 01:57:53.668659 <6>[ 27.247991] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S5_HD_Mux, hd_en 0
6513 01:57:53.682186 <6>[ 27.259543] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S5_HD_Mux, hd_en 0
6514 01:57:53.691700 <6>[ 27.271041] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S3_HD_Mux, hd_en 0
6515 01:57:53.705337 <6>[ 27.282502] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S3_HD_Mux, hd_en 0
6516 01:57:53.715037 <6>[ 27.293889] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S3_HD_Mux, hd_en 1
6517 01:57:53.728403 <6>[ 27.305234] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S3_HD_Mux, hd_en 0
6518 01:57:53.738609 <6>[ 27.316576] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S3_HD_Mux, hd_en 0
6519 01:57:53.748430 <6>[ 27.327916] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S2_HD_Mux, hd_en 0
6520 01:57:53.761656 <6>[ 27.339247] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S2_HD_Mux, hd_en 0
6521 01:57:53.771330 <6>[ 27.350578] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S2_HD_Mux, hd_en 1
6522 01:57:53.785176 <6>[ 27.361938] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S2_HD_Mux, hd_en 0
6523 01:57:53.794806 <6>[ 27.373280] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S2_HD_Mux, hd_en 0
6524 01:57:53.808391 <6>[ 27.384623] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S1_HD_Mux, hd_en 0
6525 01:57:53.818522 <6>[ 27.395958] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S1_HD_Mux, hd_en 0
6526 01:57:53.828317 <6>[ 27.407286] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S1_HD_Mux, hd_en 1
6527 01:57:53.841743 <6>[ 27.418615] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S1_HD_Mux, hd_en 0
6528 01:57:53.851452 <6>[ 27.429952] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S1_HD_Mux, hd_en 0
6529 01:57:53.865130 <6>[ 27.441296] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S0_HD_Mux, hd_en 0
6530 01:57:53.874797 <6>[ 27.452627] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S0_HD_Mux, hd_en 0
6531 01:57:53.884964 <6>[ 27.463954] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S0_HD_Mux, hd_en 1
6532 01:57:53.897677 <6>[ 27.475282] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S0_HD_Mux, hd_en 0
6533 01:57:53.907901 <6>[ 27.486617] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S0_HD_Mux, hd_en 0
6534 01:57:53.917822 # TAP version 13
6535 01:57:53.918333 # 1..658
6536 01:57:53.920905 # ok 1 get_value.0.93
6537 01:57:53.921465 # ok 2 name.0.93
6538 01:57:53.924623 # ok 3 write_default.0.93
6539 01:57:53.927953 # ok 4 write_valid.0.93
6540 01:57:53.928463 # ok 5 write_invalid.0.93
6541 01:57:53.931732 # ok 6 event_missing.0.93
6542 01:57:53.934894 # ok 7 event_spurious.0.93
6543 01:57:53.935453 # ok 8 get_value.0.92
6544 01:57:53.938125 # ok 9 name.0.92
6545 01:57:53.941468 # ok 10 write_default.0.92
6546 01:57:53.942014 # ok 11 write_valid.0.92
6547 01:57:53.944708 # ok 12 write_invalid.0.92
6548 01:57:53.948112 # ok 13 event_missing.0.92
6549 01:57:53.951410 # ok 14 event_spurious.0.92
6550 01:57:53.951964 # ok 15 get_value.0.91
6551 01:57:53.954403 # ok 16 name.0.91
6552 01:57:53.954862 # ok 17 write_default.0.91
6553 01:57:53.958182 # ok 18 write_valid.0.91
6554 01:57:53.961426 # ok 19 write_invalid.0.91
6555 01:57:53.964491 # ok 20 event_missing.0.91
6556 01:57:53.964950 # ok 21 event_spurious.0.91
6557 01:57:53.967814 # ok 22 get_value.0.90
6558 01:57:53.971004 # ok 23 name.0.90
6559 01:57:53.971464 # ok 24 write_default.0.90
6560 01:57:53.974110 # ok 25 write_valid.0.90
6561 01:57:53.977810 # ok 26 write_invalid.0.90
6562 01:57:53.978528 # ok 27 event_missing.0.90
6563 01:57:53.980802 # ok 28 event_spurious.0.90
6564 01:57:53.984020 # ok 29 get_value.0.89
6565 01:57:53.984615 # ok 30 name.0.89
6566 01:57:53.987404 # ok 31 write_default.0.89
6567 01:57:53.991015 # ok 32 write_valid.0.89
6568 01:57:53.991581 # ok 33 write_invalid.0.89
6569 01:57:53.994374 # ok 34 event_missing.0.89
6570 01:57:53.997569 # ok 35 event_spurious.0.89
6571 01:57:53.998004 # ok 36 get_value.0.88
6572 01:57:54.000951 # ok 37 name.0.88
6573 01:57:54.004295 # ok 38 write_default.0.88
6574 01:57:54.007917 # # Spurious event generated for AIF Out Mux
6575 01:57:54.011204 # # AIF Out Mux.0 expected 1 but read 0, is_volatile 0
6576 01:57:54.017841 # # Spurious event generated for AIF Out Mux
6577 01:57:54.018343 # not ok 39 write_valid.0.88
6578 01:57:54.021048 # ok 40 write_invalid.0.88
6579 01:57:54.024028 # ok 41 event_missing.0.88
6580 01:57:54.027785 # not ok 42 event_spurious.0.88
6581 01:57:54.028217 # ok 43 get_value.0.87
6582 01:57:54.030865 # ok 44 name.0.87
6583 01:57:54.034223 # ok 45 write_default.0.87
6584 01:57:54.034682 # ok 46 write_valid.0.87
6585 01:57:54.037252 # ok 47 write_invalid.0.87
6586 01:57:54.040735 # ok 48 event_missing.0.87
6587 01:57:54.043963 # ok 49 event_spurious.0.87
6588 01:57:54.044453 # ok 50 get_value.0.86
6589 01:57:54.047789 # ok 51 name.0.86
6590 01:57:54.050803 # ok 52 write_default.0.86
6591 01:57:54.054108 # # HPR Mux.0 expected 5 but read 0, is_volatile 0
6592 01:57:54.057932 # # HPR Mux.0 expected 6 but read 0, is_volatile 0
6593 01:57:54.064328 # # HPR Mux.0 expected 7 but read 0, is_volatile 0
6594 01:57:54.067829 # not ok 53 write_valid.0.86
6595 01:57:54.068261 # ok 54 write_invalid.0.86
6596 01:57:54.070672 # ok 55 event_missing.0.86
6597 01:57:54.073846 # ok 56 event_spurious.0.86
6598 01:57:54.077595 # ok 57 get_value.0.85
6599 01:57:54.078129 # ok 58 name.0.85
6600 01:57:54.080615 # ok 59 write_default.0.85
6601 01:57:54.084216 # # HPL Mux.0 expected 5 but read 0, is_volatile 0
6602 01:57:54.090432 # # HPL Mux.0 expected 6 but read 0, is_volatile 0
6603 01:57:54.094241 # # HPL Mux.0 expected 7 but read 0, is_volatile 0
6604 01:57:54.097063 # not ok 60 write_valid.0.85
6605 01:57:54.100400 # ok 61 write_invalid.0.85
6606 01:57:54.100827 # ok 62 event_missing.0.85
6607 01:57:54.103659 # ok 63 event_spurious.0.85
6608 01:57:54.107233 # ok 64 get_value.0.84
6609 01:57:54.107663 # ok 65 name.0.84
6610 01:57:54.110411 # ok 66 write_default.0.84
6611 01:57:54.113845 # ok 67 write_valid.0.84
6612 01:57:54.114258 # ok 68 write_invalid.0.84
6613 01:57:54.117169 # ok 69 event_missing.0.84
6614 01:57:54.120262 # ok 70 event_spurious.0.84
6615 01:57:54.124107 # ok 71 get_value.0.83
6616 01:57:54.124620 # ok 72 name.0.83
6617 01:57:54.127294 # ok 73 write_default.0.83
6618 01:57:54.130469 # ok 74 write_valid.0.83
6619 01:57:54.130990 # ok 75 write_invalid.0.83
6620 01:57:54.134016 # ok 76 event_missing.0.83
6621 01:57:54.136968 # ok 77 event_spurious.0.83
6622 01:57:54.140265 # ok 78 get_value.0.82
6623 01:57:54.140718 # ok 79 name.0.82
6624 01:57:54.144115 # # Headset Jack is not writeable
6625 01:57:54.147282 # ok 80 # SKIP write_default.0.82
6626 01:57:54.150357 # # Headset Jack is not writeable
6627 01:57:54.153874 # ok 81 # SKIP write_valid.0.82
6628 01:57:54.156797 # # Headset Jack is not writeable
6629 01:57:54.160216 # ok 82 # SKIP write_invalid.0.82
6630 01:57:54.160630 # ok 83 event_missing.0.82
6631 01:57:54.163728 # ok 84 event_spurious.0.82
6632 01:57:54.167257 # ok 85 get_value.0.81
6633 01:57:54.167764 # ok 86 name.0.81
6634 01:57:54.170168 # ok 87 write_default.0.81
6635 01:57:54.174218 # # No event generated for Wake-on-Voice Phase2 Switch
6636 01:57:54.180673 # # No event generated for Wake-on-Voice Phase2 Switch
6637 01:57:54.183376 # ok 88 write_valid.0.81
6638 01:57:54.187128 # # Wake-on-Voice Phase2 Switch.0 Invalid boolean value 2
6639 01:57:54.193642 # # No event generated for Wake-on-Voice Phase2 Switch
6640 01:57:54.194103 # not ok 89 write_invalid.0.81
6641 01:57:54.197467 # not ok 90 event_missing.0.81
6642 01:57:54.200671 # ok 91 event_spurious.0.81
6643 01:57:54.203827 # ok 92 get_value.0.80
6644 01:57:54.204265 # ok 93 name.0.80
6645 01:57:54.206921 # ok 94 write_default.0.80
6646 01:57:54.207351 # ok 95 write_valid.0.80
6647 01:57:54.210237 # ok 96 write_invalid.0.80
6648 01:57:54.214109 # ok 97 event_missing.0.80
6649 01:57:54.217164 # ok 98 event_spurious.0.80
6650 01:57:54.220169 # # Handset Volume.0 value -13 less than minimum 0
6651 01:57:54.223693 # not ok 99 get_value.0.79
6652 01:57:54.224273 # ok 100 name.0.79
6653 01:57:54.230252 # # snd_ctl_elem_write() failed: Invalid argument
6654 01:57:54.230887 # not ok 101 write_default.0.79
6655 01:57:54.237157 # # snd_ctl_elem_write() failed: Invalid argument
6656 01:57:54.240501 # not ok 102 write_valid.0.79
6657 01:57:54.243528 # # snd_ctl_elem_write() failed: Invalid argument
6658 01:57:54.247422 # not ok 103 write_invalid.0.79
6659 01:57:54.250795 # ok 104 event_missing.0.79
6660 01:57:54.251370 # ok 105 event_spurious.0.79
6661 01:57:54.257234 # # Lineout Volume.0 value -13 less than minimum 0
6662 01:57:54.260157 # # Lineout Volume.1 value -13 less than minimum 0
6663 01:57:54.263426 # not ok 106 get_value.0.78
6664 01:57:54.263902 # ok 107 name.0.78
6665 01:57:54.270218 # # snd_ctl_elem_write() failed: Invalid argument
6666 01:57:54.273024 # not ok 108 write_default.0.78
6667 01:57:54.277146 # # snd_ctl_elem_write() failed: Invalid argument
6668 01:57:54.280189 # not ok 109 write_valid.0.78
6669 01:57:54.283342 # # snd_ctl_elem_write() failed: Invalid argument
6670 01:57:54.286984 # not ok 110 write_invalid.0.78
6671 01:57:54.290138 # ok 111 event_missing.0.78
6672 01:57:54.290716 # ok 112 event_spurious.0.78
6673 01:57:54.296932 # # Headphone Volume.0 value -13 less than minimum 0
6674 01:57:54.300260 # # Headphone Volume.1 value -13 less than minimum 0
6675 01:57:54.303108 # not ok 113 get_value.0.77
6676 01:57:54.306333 # ok 114 name.0.77
6677 01:57:54.309746 # # snd_ctl_elem_write() failed: Invalid argument
6678 01:57:54.313437 # not ok 115 write_default.0.77
6679 01:57:54.316406 # # snd_ctl_elem_write() failed: Invalid argument
6680 01:57:54.319723 # not ok 116 write_valid.0.77
6681 01:57:54.322931 # # snd_ctl_elem_write() failed: Invalid argument
6682 01:57:54.326171 # not ok 117 write_invalid.0.77
6683 01:57:54.329736 # ok 118 event_missing.0.77
6684 01:57:54.333205 # ok 119 event_spurious.0.77
6685 01:57:54.336246 # ok 120 get_value.0.76
6686 01:57:54.343001 # # 0.76 ADDA_DL_CH2 PCM_2_CAP_CH2 is a writeable boolean but not a Switch
6687 01:57:54.343582 # not ok 121 name.0.76
6688 01:57:54.346037 # ok 122 write_default.0.76
6689 01:57:54.349807 # ok 123 write_valid.0.76
6690 01:57:54.352940 # ok 124 write_invalid.0.76
6691 01:57:54.353548 # ok 125 event_missing.0.76
6692 01:57:54.356942 # ok 126 event_spurious.0.76
6693 01:57:54.359398 # ok 127 get_value.0.75
6694 01:57:54.366577 # # 0.75 ADDA_DL_CH2 PCM_1_CAP_CH2 is a writeable boolean but not a Switch
6695 01:57:54.369627 # not ok 128 name.0.75
6696 01:57:54.370203 # ok 129 write_default.0.75
6697 01:57:54.372763 # ok 130 write_valid.0.75
6698 01:57:54.376044 # ok 131 write_invalid.0.75
6699 01:57:54.379425 # ok 132 event_missing.0.75
6700 01:57:54.379895 # ok 133 event_spurious.0.75
6701 01:57:54.382638 # ok 134 get_value.0.74
6702 01:57:54.389466 # # 0.74 ADDA_DL_CH2 PCM_2_CAP_CH1 is a writeable boolean but not a Switch
6703 01:57:54.392574 # not ok 135 name.0.74
6704 01:57:54.396396 # ok 136 write_default.0.74
6705 01:57:54.396948 # ok 137 write_valid.0.74
6706 01:57:54.399710 # ok 138 write_invalid.0.74
6707 01:57:54.402553 # ok 139 event_missing.0.74
6708 01:57:54.405992 # ok 140 event_spurious.0.74
6709 01:57:54.406546 # ok 141 get_value.0.73
6710 01:57:54.416205 # # 0.73 ADDA_DL_CH2 PCM_1_CAP_CH1 is a writeable boolean but not a Switch
6711 01:57:54.416759 # not ok 142 name.0.73
6712 01:57:54.419296 # ok 143 write_default.0.73
6713 01:57:54.422244 # ok 144 write_valid.0.73
6714 01:57:54.422706 # ok 145 write_invalid.0.73
6715 01:57:54.425823 # ok 146 event_missing.0.73
6716 01:57:54.429106 # ok 147 event_spurious.0.73
6717 01:57:54.432368 # ok 148 get_value.0.72
6718 01:57:54.439305 # # 0.72 ADDA_DL_CH2 ADDA_UL_CH1 is a writeable boolean but not a Switch
6719 01:57:54.439887 # not ok 149 name.0.72
6720 01:57:54.442326 # ok 150 write_default.0.72
6721 01:57:54.445401 # ok 151 write_valid.0.72
6722 01:57:54.448982 # ok 152 write_invalid.0.72
6723 01:57:54.452310 # ok 153 event_missing.0.72
6724 01:57:54.452863 # ok 154 event_spurious.0.72
6725 01:57:54.455718 # ok 155 get_value.0.71
6726 01:57:54.462367 # # 0.71 ADDA_DL_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
6727 01:57:54.465848 # not ok 156 name.0.71
6728 01:57:54.466403 # ok 157 write_default.0.71
6729 01:57:54.469010 # ok 158 write_valid.0.71
6730 01:57:54.472055 # ok 159 write_invalid.0.71
6731 01:57:54.475552 # ok 160 event_missing.0.71
6732 01:57:54.478991 # ok 161 event_spurious.0.71
6733 01:57:54.479544 # ok 162 get_value.0.70
6734 01:57:54.485352 # # 0.70 ADDA_DL_CH2 DL3_CH2 is a writeable boolean but not a Switch
6735 01:57:54.489020 # not ok 163 name.0.70
6736 01:57:54.492544 # ok 164 write_default.0.70
6737 01:57:54.493152 # ok 165 write_valid.0.70
6738 01:57:54.495436 # ok 166 write_invalid.0.70
6739 01:57:54.498703 # ok 167 event_missing.0.70
6740 01:57:54.502163 # ok 168 event_spurious.0.70
6741 01:57:54.502717 # ok 169 get_value.0.69
6742 01:57:54.508945 # # 0.69 ADDA_DL_CH2 DL3_CH1 is a writeable boolean but not a Switch
6743 01:57:54.512145 # not ok 170 name.0.69
6744 01:57:54.515744 # ok 171 write_default.0.69
6745 01:57:54.516300 # ok 172 write_valid.0.69
6746 01:57:54.519265 # ok 173 write_invalid.0.69
6747 01:57:54.522224 # ok 174 event_missing.0.69
6748 01:57:54.525941 # ok 175 event_spurious.0.69
6749 01:57:54.526492 # ok 176 get_value.0.68
6750 01:57:54.531997 # # 0.68 ADDA_DL_CH2 DL2_CH2 is a writeable boolean but not a Switch
6751 01:57:54.535874 # not ok 177 name.0.68
6752 01:57:54.538897 # ok 178 write_default.0.68
6753 01:57:54.539359 # ok 179 write_valid.0.68
6754 01:57:54.542060 # ok 180 write_invalid.0.68
6755 01:57:54.545009 # ok 181 event_missing.0.68
6756 01:57:54.548719 # ok 182 event_spurious.0.68
6757 01:57:54.551927 # ok 183 get_value.0.67
6758 01:57:54.554951 # # 0.67 ADDA_DL_CH2 DL2_CH1 is a writeable boolean but not a Switch
6759 01:57:54.558404 # not ok 184 name.0.67
6760 01:57:54.561858 # ok 185 write_default.0.67
6761 01:57:54.565665 # ok 186 write_valid.0.67
6762 01:57:54.566232 # ok 187 write_invalid.0.67
6763 01:57:54.568370 # ok 188 event_missing.0.67
6764 01:57:54.571668 # ok 189 event_spurious.0.67
6765 01:57:54.574927 # ok 190 get_value.0.66
6766 01:57:54.581778 # # 0.66 ADDA_DL_CH2 DL1_CH2 is a writeable boolean but not a Switch
6767 01:57:54.582340 # not ok 191 name.0.66
6768 01:57:54.585139 # ok 192 write_default.0.66
6769 01:57:54.588652 # ok 193 write_valid.0.66
6770 01:57:54.591323 # ok 194 write_invalid.0.66
6771 01:57:54.591787 # ok 195 event_missing.0.66
6772 01:57:54.594868 # ok 196 event_spurious.0.66
6773 01:57:54.597976 # ok 197 get_value.0.65
6774 01:57:54.605094 # # 0.65 ADDA_DL_CH2 DL1_CH1 is a writeable boolean but not a Switch
6775 01:57:54.605724 # not ok 198 name.0.65
6776 01:57:54.608350 # ok 199 write_default.0.65
6777 01:57:54.611823 # ok 200 write_valid.0.65
6778 01:57:54.615220 # ok 201 write_invalid.0.65
6779 01:57:54.615774 # ok 202 event_missing.0.65
6780 01:57:54.618307 # ok 203 event_spurious.0.65
6781 01:57:54.622126 # ok 204 get_value.0.64
6782 01:57:54.628216 # # 0.64 ADDA_DL_CH1 PCM_2_CAP_CH1 is a writeable boolean but not a Switch
6783 01:57:54.631763 # not ok 205 name.0.64
6784 01:57:54.632316 # ok 206 write_default.0.64
6785 01:57:54.634677 # ok 207 write_valid.0.64
6786 01:57:54.638084 # ok 208 write_invalid.0.64
6787 01:57:54.641391 # ok 209 event_missing.0.64
6788 01:57:54.644553 # ok 210 event_spurious.0.64
6789 01:57:54.645027 # ok 211 get_value.0.63
6790 01:57:54.651220 # # 0.63 ADDA_DL_CH1 PCM_1_CAP_CH1 is a writeable boolean but not a Switch
6791 01:57:54.654757 # not ok 212 name.0.63
6792 01:57:54.657854 # ok 213 write_default.0.63
6793 01:57:54.661471 # ok 214 write_valid.0.63
6794 01:57:54.662044 # ok 215 write_invalid.0.63
6795 01:57:54.664469 # ok 216 event_missing.0.63
6796 01:57:54.668050 # ok 217 event_spurious.0.63
6797 01:57:54.671049 # ok 218 get_value.0.62
6798 01:57:54.677651 # # 0.62 ADDA_DL_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
6799 01:57:54.678130 # not ok 219 name.0.62
6800 01:57:54.680902 # ok 220 write_default.0.62
6801 01:57:54.684381 # ok 221 write_valid.0.62
6802 01:57:54.687921 # ok 222 write_invalid.0.62
6803 01:57:54.688491 # ok 223 event_missing.0.62
6804 01:57:54.691089 # ok 224 event_spurious.0.62
6805 01:57:54.694369 # ok 225 get_value.0.61
6806 01:57:54.701041 # # 0.61 ADDA_DL_CH1 ADDA_UL_CH2 is a writeable boolean but not a Switch
6807 01:57:54.701677 # not ok 226 name.0.61
6808 01:57:54.704900 # ok 227 write_default.0.61
6809 01:57:54.708251 # ok 228 write_valid.0.61
6810 01:57:54.711259 # ok 229 write_invalid.0.61
6811 01:57:54.716670 # ok 230 event_missing.0.61
6812 01:57:54.717312 # ok 231 event_spurious.0.61
6813 01:57:54.718186 # ok 232 get_value.0.60
6814 01:57:54.724478 # # 0.60 ADDA_DL_CH1 DL3_CH1 is a writeable boolean but not a Switch
6815 01:57:54.727940 # not ok 233 name.0.60
6816 01:57:54.728517 # ok 234 write_default.0.60
6817 01:57:54.731847 # ok 235 write_valid.0.60
6818 01:57:54.734524 # ok 236 write_invalid.0.60
6819 01:57:54.737842 # ok 237 event_missing.0.60
6820 01:57:54.741219 # ok 238 event_spurious.0.60
6821 01:57:54.741727 # ok 239 get_value.0.59
6822 01:57:54.748000 # # 0.59 ADDA_DL_CH1 DL2_CH1 is a writeable boolean but not a Switch
6823 01:57:54.750922 # not ok 240 name.0.59
6824 01:57:54.754195 # ok 241 write_default.0.59
6825 01:57:54.754675 # ok 242 write_valid.0.59
6826 01:57:54.757821 # ok 243 write_invalid.0.59
6827 01:57:54.761403 # ok 244 event_missing.0.59
6828 01:57:54.763800 # ok 245 event_spurious.0.59
6829 01:57:54.764277 # ok 246 get_value.0.58
6830 01:57:54.770608 # # 0.58 ADDA_DL_CH1 DL1_CH1 is a writeable boolean but not a Switch
6831 01:57:54.773731 # not ok 247 name.0.58
6832 01:57:54.777248 # ok 248 write_default.0.58
6833 01:57:54.777764 # ok 249 write_valid.0.58
6834 01:57:54.780690 # ok 250 write_invalid.0.58
6835 01:57:54.784158 # ok 251 event_missing.0.58
6836 01:57:54.787220 # ok 252 event_spurious.0.58
6837 01:57:54.787700 # ok 253 get_value.0.57
6838 01:57:54.794012 # # 0.57 I2S5_CH2 DL3_CH2 is a writeable boolean but not a Switch
6839 01:57:54.797196 # not ok 254 name.0.57
6840 01:57:54.800570 # ok 255 write_default.0.57
6841 01:57:54.801047 # ok 256 write_valid.0.57
6842 01:57:54.803822 # ok 257 write_invalid.0.57
6843 01:57:54.807228 # ok 258 event_missing.0.57
6844 01:57:54.810799 # ok 259 event_spurious.0.57
6845 01:57:54.811274 # ok 260 get_value.0.56
6846 01:57:54.817241 # # 0.56 I2S5_CH2 DL2_CH2 is a writeable boolean but not a Switch
6847 01:57:54.820610 # not ok 261 name.0.56
6848 01:57:54.824249 # ok 262 write_default.0.56
6849 01:57:54.824728 # ok 263 write_valid.0.56
6850 01:57:54.827190 # ok 264 write_invalid.0.56
6851 01:57:54.830196 # ok 265 event_missing.0.56
6852 01:57:54.833365 # ok 266 event_spurious.0.56
6853 01:57:54.837028 # ok 267 get_value.0.55
6854 01:57:54.840358 # # 0.55 I2S5_CH2 DL1_CH2 is a writeable boolean but not a Switch
6855 01:57:54.843450 # not ok 268 name.0.55
6856 01:57:54.847045 # ok 269 write_default.0.55
6857 01:57:54.850121 # ok 270 write_valid.0.55
6858 01:57:54.850550 # ok 271 write_invalid.0.55
6859 01:57:54.853877 # ok 272 event_missing.0.55
6860 01:57:54.856717 # ok 273 event_spurious.0.55
6861 01:57:54.859883 # ok 274 get_value.0.54
6862 01:57:54.863070 # # 0.54 I2S5_CH1 DL3_CH1 is a writeable boolean but not a Switch
6863 01:57:54.866696 # not ok 275 name.0.54
6864 01:57:54.869867 # ok 276 write_default.0.54
6865 01:57:54.873184 # ok 277 write_valid.0.54
6866 01:57:54.873656 # ok 278 write_invalid.0.54
6867 01:57:54.876509 # ok 279 event_missing.0.54
6868 01:57:54.879576 # ok 280 event_spurious.0.54
6869 01:57:54.883683 # ok 281 get_value.0.53
6870 01:57:54.889882 # # 0.53 I2S5_CH1 DL2_CH1 is a writeable boolean but not a Switch
6871 01:57:54.890317 # not ok 282 name.0.53
6872 01:57:54.893556 # ok 283 write_default.0.53
6873 01:57:54.896410 # ok 284 write_valid.0.53
6874 01:57:54.896929 # ok 285 write_invalid.0.53
6875 01:57:54.899637 # ok 286 event_missing.0.53
6876 01:57:54.902888 # ok 287 event_spurious.0.53
6877 01:57:54.906362 # ok 288 get_value.0.52
6878 01:57:54.912812 # # 0.52 I2S5_CH1 DL1_CH1 is a writeable boolean but not a Switch
6879 01:57:54.913233 # not ok 289 name.0.52
6880 01:57:54.916286 # ok 290 write_default.0.52
6881 01:57:54.919701 # ok 291 write_valid.0.52
6882 01:57:54.922766 # ok 292 write_invalid.0.52
6883 01:57:54.923181 # ok 293 event_missing.0.52
6884 01:57:54.926379 # ok 294 event_spurious.0.52
6885 01:57:54.929627 # ok 295 get_value.0.51
6886 01:57:54.936595 # # 0.51 I2S3_CH2 DL3_CH2 is a writeable boolean but not a Switch
6887 01:57:54.937015 # not ok 296 name.0.51
6888 01:57:54.940056 # ok 297 write_default.0.51
6889 01:57:54.942761 # ok 298 write_valid.0.51
6890 01:57:54.946549 # ok 299 write_invalid.0.51
6891 01:57:54.946966 # ok 300 event_missing.0.51
6892 01:57:54.950126 # ok 301 event_spurious.0.51
6893 01:57:54.952628 # ok 302 get_value.0.50
6894 01:57:54.959403 # # 0.50 I2S3_CH2 DL2_CH2 is a writeable boolean but not a Switch
6895 01:57:54.959822 # not ok 303 name.0.50
6896 01:57:54.962807 # ok 304 write_default.0.50
6897 01:57:54.966179 # ok 305 write_valid.0.50
6898 01:57:54.969781 # ok 306 write_invalid.0.50
6899 01:57:54.970341 # ok 307 event_missing.0.50
6900 01:57:54.973085 # ok 308 event_spurious.0.50
6901 01:57:54.976083 # ok 309 get_value.0.49
6902 01:57:54.983250 # # 0.49 I2S3_CH2 DL1_CH2 is a writeable boolean but not a Switch
6903 01:57:54.983966 # not ok 310 name.0.49
6904 01:57:54.986270 # ok 311 write_default.0.49
6905 01:57:54.990673 # ok 312 write_valid.0.49
6906 01:57:54.992938 # ok 313 write_invalid.0.49
6907 01:57:54.993410 # ok 314 event_missing.0.49
6908 01:57:54.996390 # ok 315 event_spurious.0.49
6909 01:57:54.999788 # ok 316 get_value.0.48
6910 01:57:55.006608 # # 0.48 I2S3_CH1 DL3_CH1 is a writeable boolean but not a Switch
6911 01:57:55.007155 # not ok 317 name.0.48
6912 01:57:55.009873 # ok 318 write_default.0.48
6913 01:57:55.013021 # ok 319 write_valid.0.48
6914 01:57:55.016417 # ok 320 write_invalid.0.48
6915 01:57:55.016936 # ok 321 event_missing.0.48
6916 01:57:55.020091 # ok 322 event_spurious.0.48
6917 01:57:55.022843 # ok 323 get_value.0.47
6918 01:57:55.029624 # # 0.47 I2S3_CH1 DL2_CH1 is a writeable boolean but not a Switch
6919 01:57:55.030182 # not ok 324 name.0.47
6920 01:57:55.033163 # ok 325 write_default.0.47
6921 01:57:55.036513 # ok 326 write_valid.0.47
6922 01:57:55.039515 # ok 327 write_invalid.0.47
6923 01:57:55.040022 # ok 328 event_missing.0.47
6924 01:57:55.042816 # ok 329 event_spurious.0.47
6925 01:57:55.045985 # ok 330 get_value.0.46
6926 01:57:55.052681 # # 0.46 I2S3_CH1 DL1_CH1 is a writeable boolean but not a Switch
6927 01:57:55.053242 # not ok 331 name.0.46
6928 01:57:55.056231 # ok 332 write_default.0.46
6929 01:57:55.059607 # ok 333 write_valid.0.46
6930 01:57:55.063123 # ok 334 write_invalid.0.46
6931 01:57:55.063687 # ok 335 event_missing.0.46
6932 01:57:55.066169 # ok 336 event_spurious.0.46
6933 01:57:55.069768 # ok 337 get_value.0.45
6934 01:57:55.075882 # # 0.45 I2S1_CH2 DL3_CH2 is a writeable boolean but not a Switch
6935 01:57:55.076368 # not ok 338 name.0.45
6936 01:57:55.079316 # ok 339 write_default.0.45
6937 01:57:55.082691 # ok 340 write_valid.0.45
6938 01:57:55.086071 # ok 341 write_invalid.0.45
6939 01:57:55.086533 # ok 342 event_missing.0.45
6940 01:57:55.089072 # ok 343 event_spurious.0.45
6941 01:57:55.092741 # ok 344 get_value.0.44
6942 01:57:55.099249 # # 0.44 I2S1_CH2 DL2_CH2 is a writeable boolean but not a Switch
6943 01:57:55.099814 # not ok 345 name.0.44
6944 01:57:55.102798 # ok 346 write_default.0.44
6945 01:57:55.105659 # ok 347 write_valid.0.44
6946 01:57:55.109298 # ok 348 write_invalid.0.44
6947 01:57:55.112636 # ok 349 event_missing.0.44
6948 01:57:55.113195 # ok 350 event_spurious.0.44
6949 01:57:55.115827 # ok 351 get_value.0.43
6950 01:57:55.122651 # # 0.43 I2S1_CH2 DL1_CH2 is a writeable boolean but not a Switch
6951 01:57:55.123215 # not ok 352 name.0.43
6952 01:57:55.125648 # ok 353 write_default.0.43
6953 01:57:55.129187 # ok 354 write_valid.0.43
6954 01:57:55.132439 # ok 355 write_invalid.0.43
6955 01:57:55.136305 # ok 356 event_missing.0.43
6956 01:57:55.136899 # ok 357 event_spurious.0.43
6957 01:57:55.139318 # ok 358 get_value.0.42
6958 01:57:55.145744 # # 0.42 I2S1_CH1 DL3_CH1 is a writeable boolean but not a Switch
6959 01:57:55.149179 # not ok 359 name.0.42
6960 01:57:55.149791 # ok 360 write_default.0.42
6961 01:57:55.153068 # ok 361 write_valid.0.42
6962 01:57:55.155857 # ok 362 write_invalid.0.42
6963 01:57:55.159005 # ok 363 event_missing.0.42
6964 01:57:55.159466 # ok 364 event_spurious.0.42
6965 01:57:55.162230 # ok 365 get_value.0.41
6966 01:57:55.168929 # # 0.41 I2S1_CH1 DL2_CH1 is a writeable boolean but not a Switch
6967 01:57:55.172053 # not ok 366 name.0.41
6968 01:57:55.172517 # ok 367 write_default.0.41
6969 01:57:55.175589 # ok 368 write_valid.0.41
6970 01:57:55.178744 # ok 369 write_invalid.0.41
6971 01:57:55.182188 # ok 370 event_missing.0.41
6972 01:57:55.182648 # ok 371 event_spurious.0.41
6973 01:57:55.185499 # ok 372 get_value.0.40
6974 01:57:55.192201 # # 0.40 I2S1_CH1 DL1_CH1 is a writeable boolean but not a Switch
6975 01:57:55.195524 # not ok 373 name.0.40
6976 01:57:55.196009 # ok 374 write_default.0.40
6977 01:57:55.198748 # ok 375 write_valid.0.40
6978 01:57:55.202081 # ok 376 write_invalid.0.40
6979 01:57:55.205719 # ok 377 event_missing.0.40
6980 01:57:55.208711 # ok 378 event_spurious.0.40
6981 01:57:55.209311 # ok 379 get_value.0.39
6982 01:57:55.215474 # # 0.39 PCM_2_PB_CH4 DL1_CH1 is a writeable boolean but not a Switch
6983 01:57:55.218919 # not ok 380 name.0.39
6984 01:57:55.219478 # ok 381 write_default.0.39
6985 01:57:55.221945 # ok 382 write_valid.0.39
6986 01:57:55.225739 # ok 383 write_invalid.0.39
6987 01:57:55.228798 # ok 384 event_missing.0.39
6988 01:57:55.229406 # ok 385 event_spurious.0.39
6989 01:57:55.231969 # ok 386 get_value.0.38
6990 01:57:55.238758 # # 0.38 PCM_2_PB_CH2 DL2_CH2 is a writeable boolean but not a Switch
6991 01:57:55.241945 # not ok 387 name.0.38
6992 01:57:55.242504 # ok 388 write_default.0.38
6993 01:57:55.244926 # ok 389 write_valid.0.38
6994 01:57:55.248599 # ok 390 write_invalid.0.38
6995 01:57:55.251970 # ok 391 event_missing.0.38
6996 01:57:55.252527 # ok 392 event_spurious.0.38
6997 01:57:55.254788 # ok 393 get_value.0.37
6998 01:57:55.261971 # # 0.37 PCM_2_PB_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
6999 01:57:55.265150 # not ok 394 name.0.37
7000 01:57:55.265755 # ok 395 write_default.0.37
7001 01:57:55.268560 # ok 396 write_valid.0.37
7002 01:57:55.271808 # ok 397 write_invalid.0.37
7003 01:57:55.274988 # ok 398 event_missing.0.37
7004 01:57:55.278489 # ok 399 event_spurious.0.37
7005 01:57:55.278951 # ok 400 get_value.0.36
7006 01:57:55.284834 # # 0.36 PCM_2_PB_CH1 DL2_CH1 is a writeable boolean but not a Switch
7007 01:57:55.288346 # not ok 401 name.0.36
7008 01:57:55.291421 # ok 402 write_default.0.36
7009 01:57:55.291882 # ok 403 write_valid.0.36
7010 01:57:55.294728 # ok 404 write_invalid.0.36
7011 01:57:55.298239 # ok 405 event_missing.0.36
7012 01:57:55.301571 # ok 406 event_spurious.0.36
7013 01:57:55.302133 # ok 407 get_value.0.35
7014 01:57:55.308579 # # 0.35 PCM_2_PB_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7015 01:57:55.311438 # not ok 408 name.0.35
7016 01:57:55.314975 # ok 409 write_default.0.35
7017 01:57:55.317836 # ok 410 write_valid.0.35
7018 01:57:55.318296 # ok 411 write_invalid.0.35
7019 01:57:55.321911 # ok 412 event_missing.0.35
7020 01:57:55.325114 # ok 413 event_spurious.0.35
7021 01:57:55.328029 # ok 414 get_value.0.34
7022 01:57:55.334996 # # 0.34 PCM_1_PB_CH4 DL1_CH1 is a writeable boolean but not a Switch
7023 01:57:55.335558 # not ok 415 name.0.34
7024 01:57:55.338279 # ok 416 write_default.0.34
7025 01:57:55.341160 # ok 417 write_valid.0.34
7026 01:57:55.344440 # ok 418 write_invalid.0.34
7027 01:57:55.344898 # ok 419 event_missing.0.34
7028 01:57:55.348495 # ok 420 event_spurious.0.34
7029 01:57:55.351454 # ok 421 get_value.0.33
7030 01:57:55.357993 # # 0.33 PCM_1_PB_CH2 DL2_CH2 is a writeable boolean but not a Switch
7031 01:57:55.358557 # not ok 422 name.0.33
7032 01:57:55.361378 # ok 423 write_default.0.33
7033 01:57:55.364767 # ok 424 write_valid.0.33
7034 01:57:55.367527 # ok 425 write_invalid.0.33
7035 01:57:55.371479 # ok 426 event_missing.0.33
7036 01:57:55.372042 # ok 427 event_spurious.0.33
7037 01:57:55.374305 # ok 428 get_value.0.32
7038 01:57:55.380867 # # 0.32 PCM_1_PB_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
7039 01:57:55.384427 # not ok 429 name.0.32
7040 01:57:55.387878 # ok 430 write_default.0.32
7041 01:57:55.388487 # ok 431 write_valid.0.32
7042 01:57:55.391332 # ok 432 write_invalid.0.32
7043 01:57:55.394098 # ok 433 event_missing.0.32
7044 01:57:55.397835 # ok 434 event_spurious.0.32
7045 01:57:55.398397 # ok 435 get_value.0.31
7046 01:57:55.404484 # # 0.31 PCM_1_PB_CH1 DL2_CH1 is a writeable boolean but not a Switch
7047 01:57:55.407450 # not ok 436 name.0.31
7048 01:57:55.410943 # ok 437 write_default.0.31
7049 01:57:55.411408 # ok 438 write_valid.0.31
7050 01:57:55.414513 # ok 439 write_invalid.0.31
7051 01:57:55.417927 # ok 440 event_missing.0.31
7052 01:57:55.420933 # ok 441 event_spurious.0.31
7053 01:57:55.424266 # ok 442 get_value.0.30
7054 01:57:55.431264 # # 0.30 PCM_1_PB_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7055 01:57:55.431821 # not ok 443 name.0.30
7056 01:57:55.434622 # ok 444 write_default.0.30
7057 01:57:55.437373 # ok 445 write_valid.0.30
7058 01:57:55.437836 # ok 446 write_invalid.0.30
7059 01:57:55.441113 # ok 447 event_missing.0.30
7060 01:57:55.444056 # ok 448 event_spurious.0.30
7061 01:57:55.447377 # ok 449 get_value.0.29
7062 01:57:55.447838 # ok 450 name.0.29
7063 01:57:55.451309 # ok 451 write_default.0.29
7064 01:57:55.454317 # ok 452 write_valid.0.29
7065 01:57:55.457410 # ok 453 write_invalid.0.29
7066 01:57:55.457971 # ok 454 event_missing.0.29
7067 01:57:55.460803 # ok 455 event_spurious.0.29
7068 01:57:55.464039 # ok 456 get_value.0.28
7069 01:57:55.464595 # ok 457 name.0.28
7070 01:57:55.467346 # ok 458 write_default.0.28
7071 01:57:55.470951 # ok 459 write_valid.0.28
7072 01:57:55.474052 # ok 460 write_invalid.0.28
7073 01:57:55.477520 # ok 461 event_missing.0.28
7074 01:57:55.478042 # ok 462 event_spurious.0.28
7075 01:57:55.480587 # ok 463 get_value.0.27
7076 01:57:55.484687 # ok 464 name.0.27
7077 01:57:55.485238 # ok 465 write_default.0.27
7078 01:57:55.487122 # ok 466 write_valid.0.27
7079 01:57:55.490778 # ok 467 write_invalid.0.27
7080 01:57:55.493728 # ok 468 event_missing.0.27
7081 01:57:55.494208 # ok 469 event_spurious.0.27
7082 01:57:55.497165 # ok 470 get_value.0.26
7083 01:57:55.500640 # ok 471 name.0.26
7084 01:57:55.501193 # ok 472 write_default.0.26
7085 01:57:55.503826 # ok 473 write_valid.0.26
7086 01:57:55.507345 # ok 474 write_invalid.0.26
7087 01:57:55.510608 # ok 475 event_missing.0.26
7088 01:57:55.513940 # ok 476 event_spurious.0.26
7089 01:57:55.514509 # ok 477 get_value.0.25
7090 01:57:55.517533 # ok 478 name.0.25
7091 01:57:55.520305 # ok 479 write_default.0.25
7092 01:57:55.520731 # ok 480 write_valid.0.25
7093 01:57:55.524018 # ok 481 write_invalid.0.25
7094 01:57:55.527183 # ok 482 event_missing.0.25
7095 01:57:55.530522 # ok 483 event_spurious.0.25
7096 01:57:55.531044 # ok 484 get_value.0.24
7097 01:57:55.534098 # ok 485 name.0.24
7098 01:57:55.537536 # ok 486 write_default.0.24
7099 01:57:55.538112 # ok 487 write_valid.0.24
7100 01:57:55.540283 # ok 488 write_invalid.0.24
7101 01:57:55.543838 # ok 489 event_missing.0.24
7102 01:57:55.546827 # ok 490 event_spurious.0.24
7103 01:57:55.547303 # ok 491 get_value.0.23
7104 01:57:55.550333 # ok 492 name.0.23
7105 01:57:55.553904 # ok 493 write_default.0.23
7106 01:57:55.554456 # ok 494 write_valid.0.23
7107 01:57:55.556926 # ok 495 write_invalid.0.23
7108 01:57:55.560150 # ok 496 event_missing.0.23
7109 01:57:55.563820 # ok 497 event_spurious.0.23
7110 01:57:55.564374 # ok 498 get_value.0.22
7111 01:57:55.566859 # ok 499 name.0.22
7112 01:57:55.570397 # ok 500 write_default.0.22
7113 01:57:55.570944 # ok 501 write_valid.0.22
7114 01:57:55.573205 # ok 502 write_invalid.0.22
7115 01:57:55.576899 # ok 503 event_missing.0.22
7116 01:57:55.580037 # ok 504 event_spurious.0.22
7117 01:57:55.580587 # ok 505 get_value.0.21
7118 01:57:55.587148 # # 0.21 UL_MONO_1_CH1 ADDA_UL_CH2 is a writeable boolean but not a Switch
7119 01:57:55.590025 # not ok 506 name.0.21
7120 01:57:55.593424 # ok 507 write_default.0.21
7121 01:57:55.593909 # ok 508 write_valid.0.21
7122 01:57:55.596601 # ok 509 write_invalid.0.21
7123 01:57:55.600265 # ok 510 event_missing.0.21
7124 01:57:55.603979 # ok 511 event_spurious.0.21
7125 01:57:55.604583 # ok 512 get_value.0.20
7126 01:57:55.610396 # # 0.20 UL_MONO_1_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7127 01:57:55.613655 # not ok 513 name.0.20
7128 01:57:55.617102 # ok 514 write_default.0.20
7129 01:57:55.617696 # ok 515 write_valid.0.20
7130 01:57:55.620196 # ok 516 write_invalid.0.20
7131 01:57:55.623360 # ok 517 event_missing.0.20
7132 01:57:55.627338 # ok 518 event_spurious.0.20
7133 01:57:55.627955 # ok 519 get_value.0.19
7134 01:57:55.633532 # # 0.19 UL4_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
7135 01:57:55.637209 # not ok 520 name.0.19
7136 01:57:55.640292 # ok 521 write_default.0.19
7137 01:57:55.640841 # ok 522 write_valid.0.19
7138 01:57:55.643599 # ok 523 write_invalid.0.19
7139 01:57:55.646666 # ok 524 event_missing.0.19
7140 01:57:55.650026 # ok 525 event_spurious.0.19
7141 01:57:55.650487 # ok 526 get_value.0.18
7142 01:57:55.656624 # # 0.18 UL4_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7143 01:57:55.660203 # not ok 527 name.0.18
7144 01:57:55.660752 # ok 528 write_default.0.18
7145 01:57:55.663323 # ok 529 write_valid.0.18
7146 01:57:55.666717 # ok 530 write_invalid.0.18
7147 01:57:55.670268 # ok 531 event_missing.0.18
7148 01:57:55.670845 # ok 532 event_spurious.0.18
7149 01:57:55.673496 # ok 533 get_value.0.17
7150 01:57:55.680045 # # 0.17 UL3_CH2 I2S2_CH2 is a writeable boolean but not a Switch
7151 01:57:55.683385 # not ok 534 name.0.17
7152 01:57:55.683851 # ok 535 write_default.0.17
7153 01:57:55.686982 # ok 536 write_valid.0.17
7154 01:57:55.689969 # ok 537 write_invalid.0.17
7155 01:57:55.690434 # ok 538 event_missing.0.17
7156 01:57:55.693347 # ok 539 event_spurious.0.17
7157 01:57:55.696590 # ok 540 get_value.0.16
7158 01:57:55.703439 # # 0.16 UL3_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
7159 01:57:55.703999 # not ok 541 name.0.16
7160 01:57:55.706545 # ok 542 write_default.0.16
7161 01:57:55.709734 # ok 543 write_valid.0.16
7162 01:57:55.713353 # ok 544 write_invalid.0.16
7163 01:57:55.713828 # ok 545 event_missing.0.16
7164 01:57:55.716583 # ok 546 event_spurious.0.16
7165 01:57:55.720167 # ok 547 get_value.0.15
7166 01:57:55.726697 # # 0.15 UL3_CH1 I2S2_CH1 is a writeable boolean but not a Switch
7167 01:57:55.727251 # not ok 548 name.0.15
7168 01:57:55.729920 # ok 549 write_default.0.15
7169 01:57:55.732968 # ok 550 write_valid.0.15
7170 01:57:55.736283 # ok 551 write_invalid.0.15
7171 01:57:55.736748 # ok 552 event_missing.0.15
7172 01:57:55.739908 # ok 553 event_spurious.0.15
7173 01:57:55.743171 # ok 554 get_value.0.14
7174 01:57:55.749592 # # 0.14 UL3_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7175 01:57:55.753147 # not ok 555 name.0.14
7176 01:57:55.753774 # ok 556 write_default.0.14
7177 01:57:55.756307 # ok 557 write_valid.0.14
7178 01:57:55.759713 # ok 558 write_invalid.0.14
7179 01:57:55.763025 # ok 559 event_missing.0.14
7180 01:57:55.763497 # ok 560 event_spurious.0.14
7181 01:57:55.766464 # ok 561 get_value.0.13
7182 01:57:55.773322 # # 0.13 UL2_CH2 I2S2_CH2 is a writeable boolean but not a Switch
7183 01:57:55.776335 # not ok 562 name.0.13
7184 01:57:55.776892 # ok 563 write_default.0.13
7185 01:57:55.779743 # ok 564 write_valid.0.13
7186 01:57:55.782926 # ok 565 write_invalid.0.13
7187 01:57:55.786682 # ok 566 event_missing.0.13
7188 01:57:55.787428 # ok 567 event_spurious.0.13
7189 01:57:55.789417 # ok 568 get_value.0.12
7190 01:57:55.796151 # # 0.12 UL2_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
7191 01:57:55.799718 # not ok 569 name.0.12
7192 01:57:55.800270 # ok 570 write_default.0.12
7193 01:57:55.803104 # ok 571 write_valid.0.12
7194 01:57:55.805988 # ok 572 write_invalid.0.12
7195 01:57:55.809647 # ok 573 event_missing.0.12
7196 01:57:55.813042 # ok 574 event_spurious.0.12
7197 01:57:55.813733 # ok 575 get_value.0.11
7198 01:57:55.819398 # # 0.11 UL2_CH1 I2S2_CH1 is a writeable boolean but not a Switch
7199 01:57:55.822639 # not ok 576 name.0.11
7200 01:57:55.826245 # ok 577 write_default.0.11
7201 01:57:55.826801 # ok 578 write_valid.0.11
7202 01:57:55.829506 # ok 579 write_invalid.0.11
7203 01:57:55.832911 # ok 580 event_missing.0.11
7204 01:57:55.836356 # ok 581 event_spurious.0.11
7205 01:57:55.836915 # ok 582 get_value.0.10
7206 01:57:55.842577 # # 0.10 UL2_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7207 01:57:55.845860 # not ok 583 name.0.10
7208 01:57:55.849336 # ok 584 write_default.0.10
7209 01:57:55.850017 # ok 585 write_valid.0.10
7210 01:57:55.852336 # ok 586 write_invalid.0.10
7211 01:57:55.856240 # ok 587 event_missing.0.10
7212 01:57:55.859644 # ok 588 event_spurious.0.10
7213 01:57:55.860204 # ok 589 get_value.0.9
7214 01:57:55.866159 # # 0.9 UL1_CH2 I2S0_CH2 is a writeable boolean but not a Switch
7215 01:57:55.869342 # not ok 590 name.0.9
7216 01:57:55.872740 # ok 591 write_default.0.9
7217 01:57:55.873325 # ok 592 write_valid.0.9
7218 01:57:55.875750 # ok 593 write_invalid.0.9
7219 01:57:55.879143 # ok 594 event_missing.0.9
7220 01:57:55.882543 # ok 595 event_spurious.0.9
7221 01:57:55.883224 # ok 596 get_value.0.8
7222 01:57:55.889213 # # 0.8 UL1_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
7223 01:57:55.892668 # not ok 597 name.0.8
7224 01:57:55.893223 # ok 598 write_default.0.8
7225 01:57:55.895628 # ok 599 write_valid.0.8
7226 01:57:55.899070 # ok 600 write_invalid.0.8
7227 01:57:55.902575 # ok 601 event_missing.0.8
7228 01:57:55.903033 # ok 602 event_spurious.0.8
7229 01:57:55.906143 # ok 603 get_value.0.7
7230 01:57:55.912918 # # 0.7 UL1_CH1 I2S0_CH1 is a writeable boolean but not a Switch
7231 01:57:55.915785 # not ok 604 name.0.7
7232 01:57:55.916338 # ok 605 write_default.0.7
7233 01:57:55.919199 # ok 606 write_valid.0.7
7234 01:57:55.922561 # ok 607 write_invalid.0.7
7235 01:57:55.923119 # ok 608 event_missing.0.7
7236 01:57:55.925920 # ok 609 event_spurious.0.7
7237 01:57:55.928860 # ok 610 get_value.0.6
7238 01:57:55.935858 # # 0.6 UL1_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7239 01:57:55.936420 # not ok 611 name.0.6
7240 01:57:55.939116 # ok 612 write_default.0.6
7241 01:57:55.942419 # ok 613 write_valid.0.6
7242 01:57:55.945699 # ok 614 write_invalid.0.6
7243 01:57:55.946256 # ok 615 event_missing.0.6
7244 01:57:55.949074 # ok 616 event_spurious.0.6
7245 01:57:55.952302 # ok 617 get_value.0.5
7246 01:57:55.952856 # ok 618 name.0.5
7247 01:57:55.956038 # ok 619 write_default.0.5
7248 01:57:55.959396 # # No event generated for MTKAIF_DMIC
7249 01:57:55.962590 # # No event generated for MTKAIF_DMIC
7250 01:57:55.965605 # ok 620 write_valid.0.5
7251 01:57:55.968895 # ok 621 write_invalid.0.5
7252 01:57:55.972166 # not ok 622 event_missing.0.5
7253 01:57:55.972727 # ok 623 event_spurious.0.5
7254 01:57:55.975376 # ok 624 get_value.0.4
7255 01:57:55.978625 # ok 625 name.0.4
7256 01:57:55.979100 # ok 626 write_default.0.4
7257 01:57:55.982122 # # No event generated for I2S5_HD_Mux
7258 01:57:55.985370 # # No event generated for I2S5_HD_Mux
7259 01:57:55.988621 # ok 627 write_valid.0.4
7260 01:57:55.992085 # ok 628 write_invalid.0.4
7261 01:57:55.995083 # not ok 629 event_missing.0.4
7262 01:57:55.998769 # ok 630 event_spurious.0.4
7263 01:57:55.999231 # ok 631 get_value.0.3
7264 01:57:56.001948 # ok 632 name.0.3
7265 01:57:56.002381 # ok 633 write_default.0.3
7266 01:57:56.008950 # # No event generated for I2S3_HD_Mux
7267 01:57:56.011968 # # No event generated for I2S3_HD_Mux
7268 01:57:56.012384 # ok 634 write_valid.0.3
7269 01:57:56.015543 # ok 635 write_invalid.0.3
7270 01:57:56.018710 # not ok 636 event_missing.0.3
7271 01:57:56.021810 # ok 637 event_spurious.0.3
7272 01:57:56.022226 # ok 638 get_value.0.2
7273 01:57:56.025511 # ok 639 name.0.2
7274 01:57:56.028514 # ok 640 write_default.0.2
7275 01:57:56.032209 # # No event generated for I2S2_HD_Mux
7276 01:57:56.035185 # # No event generated for I2S2_HD_Mux
7277 01:57:56.035603 # ok 641 write_valid.0.2
7278 01:57:56.038524 # ok 642 write_invalid.0.2
7279 01:57:56.041706 # not ok 643 event_missing.0.2
7280 01:57:56.045026 # ok 644 event_spurious.0.2
7281 01:57:56.045473 # ok 645 get_value.0.1
7282 01:57:56.048221 # ok 646 name.0.1
7283 01:57:56.051461 # ok 647 write_default.0.1
7284 01:57:56.055164 # # No event generated for I2S1_HD_Mux
7285 01:57:56.058345 # # No event generated for I2S1_HD_Mux
7286 01:57:56.058762 # ok 648 write_valid.0.1
7287 01:57:56.061892 # ok 649 write_invalid.0.1
7288 01:57:56.065401 # not ok 650 event_missing.0.1
7289 01:57:56.068144 # ok 651 event_spurious.0.1
7290 01:57:56.068559 # ok 652 get_value.0.0
7291 01:57:56.071961 # ok 653 name.0.0
7292 01:57:56.072375 # ok 654 write_default.0.0
7293 01:57:56.078461 # # No event generated for I2S0_HD_Mux
7294 01:57:56.081806 # # No event generated for I2S0_HD_Mux
7295 01:57:56.082325 # ok 655 write_valid.0.0
7296 01:57:56.085327 # ok 656 write_invalid.0.0
7297 01:57:56.088035 # not ok 657 event_missing.0.0
7298 01:57:56.091502 # ok 658 event_spurious.0.0
7299 01:57:56.094993 # # Totals: pass:568 fail:87 xfail:0 xpass:0 skip:3 error:0
7300 01:57:56.098230 ok 1 selftests: alsa: mixer-test
7301 01:57:57.685893 alsa_mixer-test_get_value_0_93 pass
7302 01:57:57.689021 alsa_mixer-test_name_0_93 pass
7303 01:57:57.692170 alsa_mixer-test_write_default_0_93 pass
7304 01:57:57.696433 alsa_mixer-test_write_valid_0_93 pass
7305 01:57:57.702451 alsa_mixer-test_write_invalid_0_93 pass
7306 01:57:57.705881 alsa_mixer-test_event_missing_0_93 pass
7307 01:57:57.709047 alsa_mixer-test_event_spurious_0_93 pass
7308 01:57:57.712170 alsa_mixer-test_get_value_0_92 pass
7309 01:57:57.715460 alsa_mixer-test_name_0_92 pass
7310 01:57:57.718801 alsa_mixer-test_write_default_0_92 pass
7311 01:57:57.722593 alsa_mixer-test_write_valid_0_92 pass
7312 01:57:57.725789 alsa_mixer-test_write_invalid_0_92 pass
7313 01:57:57.729203 alsa_mixer-test_event_missing_0_92 pass
7314 01:57:57.732282 alsa_mixer-test_event_spurious_0_92 pass
7315 01:57:57.735641 alsa_mixer-test_get_value_0_91 pass
7316 01:57:57.739257 alsa_mixer-test_name_0_91 pass
7317 01:57:57.742506 alsa_mixer-test_write_default_0_91 pass
7318 01:57:57.745613 alsa_mixer-test_write_valid_0_91 pass
7319 01:57:57.749182 alsa_mixer-test_write_invalid_0_91 pass
7320 01:57:57.752397 alsa_mixer-test_event_missing_0_91 pass
7321 01:57:57.755656 alsa_mixer-test_event_spurious_0_91 pass
7322 01:57:57.758671 alsa_mixer-test_get_value_0_90 pass
7323 01:57:57.762180 alsa_mixer-test_name_0_90 pass
7324 01:57:57.765723 alsa_mixer-test_write_default_0_90 pass
7325 01:57:57.768637 alsa_mixer-test_write_valid_0_90 pass
7326 01:57:57.775193 alsa_mixer-test_write_invalid_0_90 pass
7327 01:57:57.778490 alsa_mixer-test_event_missing_0_90 pass
7328 01:57:57.782060 alsa_mixer-test_event_spurious_0_90 pass
7329 01:57:57.785550 alsa_mixer-test_get_value_0_89 pass
7330 01:57:57.788586 alsa_mixer-test_name_0_89 pass
7331 01:57:57.791682 alsa_mixer-test_write_default_0_89 pass
7332 01:57:57.795156 alsa_mixer-test_write_valid_0_89 pass
7333 01:57:57.798220 alsa_mixer-test_write_invalid_0_89 pass
7334 01:57:57.801620 alsa_mixer-test_event_missing_0_89 pass
7335 01:57:57.805044 alsa_mixer-test_event_spurious_0_89 pass
7336 01:57:57.808229 alsa_mixer-test_get_value_0_88 pass
7337 01:57:57.811789 alsa_mixer-test_name_0_88 pass
7338 01:57:57.815437 alsa_mixer-test_write_default_0_88 pass
7339 01:57:57.818765 alsa_mixer-test_write_valid_0_88 fail
7340 01:57:57.821667 alsa_mixer-test_write_invalid_0_88 pass
7341 01:57:57.825401 alsa_mixer-test_event_missing_0_88 pass
7342 01:57:57.831441 alsa_mixer-test_event_spurious_0_88 fail
7343 01:57:57.835100 alsa_mixer-test_get_value_0_87 pass
7344 01:57:57.835620 alsa_mixer-test_name_0_87 pass
7345 01:57:57.841849 alsa_mixer-test_write_default_0_87 pass
7346 01:57:57.845119 alsa_mixer-test_write_valid_0_87 pass
7347 01:57:57.848592 alsa_mixer-test_write_invalid_0_87 pass
7348 01:57:57.851496 alsa_mixer-test_event_missing_0_87 pass
7349 01:57:57.855289 alsa_mixer-test_event_spurious_0_87 pass
7350 01:57:57.858470 alsa_mixer-test_get_value_0_86 pass
7351 01:57:57.861351 alsa_mixer-test_name_0_86 pass
7352 01:57:57.865245 alsa_mixer-test_write_default_0_86 pass
7353 01:57:57.868008 alsa_mixer-test_write_valid_0_86 fail
7354 01:57:57.871792 alsa_mixer-test_write_invalid_0_86 pass
7355 01:57:57.875007 alsa_mixer-test_event_missing_0_86 pass
7356 01:57:57.878185 alsa_mixer-test_event_spurious_0_86 pass
7357 01:57:57.881570 alsa_mixer-test_get_value_0_85 pass
7358 01:57:57.884879 alsa_mixer-test_name_0_85 pass
7359 01:57:57.887984 alsa_mixer-test_write_default_0_85 pass
7360 01:57:57.891972 alsa_mixer-test_write_valid_0_85 fail
7361 01:57:57.897636 alsa_mixer-test_write_invalid_0_85 pass
7362 01:57:57.901013 alsa_mixer-test_event_missing_0_85 pass
7363 01:57:57.904951 alsa_mixer-test_event_spurious_0_85 pass
7364 01:57:57.908090 alsa_mixer-test_get_value_0_84 pass
7365 01:57:57.911471 alsa_mixer-test_name_0_84 pass
7366 01:57:57.914469 alsa_mixer-test_write_default_0_84 pass
7367 01:57:57.918189 alsa_mixer-test_write_valid_0_84 pass
7368 01:57:57.921322 alsa_mixer-test_write_invalid_0_84 pass
7369 01:57:57.924970 alsa_mixer-test_event_missing_0_84 pass
7370 01:57:57.927673 alsa_mixer-test_event_spurious_0_84 pass
7371 01:57:57.931441 alsa_mixer-test_get_value_0_83 pass
7372 01:57:57.934830 alsa_mixer-test_name_0_83 pass
7373 01:57:57.937952 alsa_mixer-test_write_default_0_83 pass
7374 01:57:57.941225 alsa_mixer-test_write_valid_0_83 pass
7375 01:57:57.944694 alsa_mixer-test_write_invalid_0_83 pass
7376 01:57:57.950806 alsa_mixer-test_event_missing_0_83 pass
7377 01:57:57.954517 alsa_mixer-test_event_spurious_0_83 pass
7378 01:57:57.957754 alsa_mixer-test_get_value_0_82 pass
7379 01:57:57.960961 alsa_mixer-test_name_0_82 pass
7380 01:57:57.963991 alsa_mixer-test_write_default_0_82 skip
7381 01:57:57.967275 alsa_mixer-test_write_valid_0_82 skip
7382 01:57:57.971194 alsa_mixer-test_write_invalid_0_82 skip
7383 01:57:57.974205 alsa_mixer-test_event_missing_0_82 pass
7384 01:57:57.977541 alsa_mixer-test_event_spurious_0_82 pass
7385 01:57:57.981080 alsa_mixer-test_get_value_0_81 pass
7386 01:57:57.984253 alsa_mixer-test_name_0_81 pass
7387 01:57:57.987374 alsa_mixer-test_write_default_0_81 pass
7388 01:57:57.991039 alsa_mixer-test_write_valid_0_81 pass
7389 01:57:57.994158 alsa_mixer-test_write_invalid_0_81 fail
7390 01:57:57.997332 alsa_mixer-test_event_missing_0_81 fail
7391 01:57:58.001002 alsa_mixer-test_event_spurious_0_81 pass
7392 01:57:58.004302 alsa_mixer-test_get_value_0_80 pass
7393 01:57:58.007466 alsa_mixer-test_name_0_80 pass
7394 01:57:58.010668 alsa_mixer-test_write_default_0_80 pass
7395 01:57:58.014020 alsa_mixer-test_write_valid_0_80 pass
7396 01:57:58.017416 alsa_mixer-test_write_invalid_0_80 pass
7397 01:57:58.020443 alsa_mixer-test_event_missing_0_80 pass
7398 01:57:58.027052 alsa_mixer-test_event_spurious_0_80 pass
7399 01:57:58.027552 alsa_mixer-test_get_value_0_79 fail
7400 01:57:58.030751 alsa_mixer-test_name_0_79 pass
7401 01:57:58.033808 alsa_mixer-test_write_default_0_79 fail
7402 01:57:58.037627 alsa_mixer-test_write_valid_0_79 fail
7403 01:57:58.040743 alsa_mixer-test_write_invalid_0_79 fail
7404 01:57:58.047520 alsa_mixer-test_event_missing_0_79 pass
7405 01:57:58.050611 alsa_mixer-test_event_spurious_0_79 pass
7406 01:57:58.054156 alsa_mixer-test_get_value_0_78 fail
7407 01:57:58.054672 alsa_mixer-test_name_0_78 pass
7408 01:57:58.060728 alsa_mixer-test_write_default_0_78 fail
7409 01:57:58.064307 alsa_mixer-test_write_valid_0_78 fail
7410 01:57:58.067374 alsa_mixer-test_write_invalid_0_78 fail
7411 01:57:58.070502 alsa_mixer-test_event_missing_0_78 pass
7412 01:57:58.073657 alsa_mixer-test_event_spurious_0_78 pass
7413 01:57:58.077096 alsa_mixer-test_get_value_0_77 fail
7414 01:57:58.080409 alsa_mixer-test_name_0_77 pass
7415 01:57:58.083590 alsa_mixer-test_write_default_0_77 fail
7416 01:57:58.086800 alsa_mixer-test_write_valid_0_77 fail
7417 01:57:58.090536 alsa_mixer-test_write_invalid_0_77 fail
7418 01:57:58.093651 alsa_mixer-test_event_missing_0_77 pass
7419 01:57:58.097777 alsa_mixer-test_event_spurious_0_77 pass
7420 01:57:58.100255 alsa_mixer-test_get_value_0_76 pass
7421 01:57:58.103976 alsa_mixer-test_name_0_76 fail
7422 01:57:58.107208 alsa_mixer-test_write_default_0_76 pass
7423 01:57:58.110341 alsa_mixer-test_write_valid_0_76 pass
7424 01:57:58.116855 alsa_mixer-test_write_invalid_0_76 pass
7425 01:57:58.120393 alsa_mixer-test_event_missing_0_76 pass
7426 01:57:58.123407 alsa_mixer-test_event_spurious_0_76 pass
7427 01:57:58.126789 alsa_mixer-test_get_value_0_75 pass
7428 01:57:58.130000 alsa_mixer-test_name_0_75 fail
7429 01:57:58.133378 alsa_mixer-test_write_default_0_75 pass
7430 01:57:58.136826 alsa_mixer-test_write_valid_0_75 pass
7431 01:57:58.140127 alsa_mixer-test_write_invalid_0_75 pass
7432 01:57:58.143383 alsa_mixer-test_event_missing_0_75 pass
7433 01:57:58.146729 alsa_mixer-test_event_spurious_0_75 pass
7434 01:57:58.150242 alsa_mixer-test_get_value_0_74 pass
7435 01:57:58.153753 alsa_mixer-test_name_0_74 fail
7436 01:57:58.156626 alsa_mixer-test_write_default_0_74 pass
7437 01:57:58.159865 alsa_mixer-test_write_valid_0_74 pass
7438 01:57:58.163146 alsa_mixer-test_write_invalid_0_74 pass
7439 01:57:58.166993 alsa_mixer-test_event_missing_0_74 pass
7440 01:57:58.173389 alsa_mixer-test_event_spurious_0_74 pass
7441 01:57:58.176702 alsa_mixer-test_get_value_0_73 pass
7442 01:57:58.177218 alsa_mixer-test_name_0_73 fail
7443 01:57:58.183420 alsa_mixer-test_write_default_0_73 pass
7444 01:57:58.186669 alsa_mixer-test_write_valid_0_73 pass
7445 01:57:58.189692 alsa_mixer-test_write_invalid_0_73 pass
7446 01:57:58.193252 alsa_mixer-test_event_missing_0_73 pass
7447 01:57:58.196466 alsa_mixer-test_event_spurious_0_73 pass
7448 01:57:58.199887 alsa_mixer-test_get_value_0_72 pass
7449 01:57:58.203082 alsa_mixer-test_name_0_72 fail
7450 01:57:58.207076 alsa_mixer-test_write_default_0_72 pass
7451 01:57:58.209664 alsa_mixer-test_write_valid_0_72 pass
7452 01:57:58.212888 alsa_mixer-test_write_invalid_0_72 pass
7453 01:57:58.216283 alsa_mixer-test_event_missing_0_72 pass
7454 01:57:58.219584 alsa_mixer-test_event_spurious_0_72 pass
7455 01:57:58.223127 alsa_mixer-test_get_value_0_71 pass
7456 01:57:58.226277 alsa_mixer-test_name_0_71 fail
7457 01:57:58.229628 alsa_mixer-test_write_default_0_71 pass
7458 01:57:58.232983 alsa_mixer-test_write_valid_0_71 pass
7459 01:57:58.239762 alsa_mixer-test_write_invalid_0_71 pass
7460 01:57:58.243161 alsa_mixer-test_event_missing_0_71 pass
7461 01:57:58.246118 alsa_mixer-test_event_spurious_0_71 pass
7462 01:57:58.249149 alsa_mixer-test_get_value_0_70 pass
7463 01:57:58.253405 alsa_mixer-test_name_0_70 fail
7464 01:57:58.256176 alsa_mixer-test_write_default_0_70 pass
7465 01:57:58.259578 alsa_mixer-test_write_valid_0_70 pass
7466 01:57:58.263083 alsa_mixer-test_write_invalid_0_70 pass
7467 01:57:58.266803 alsa_mixer-test_event_missing_0_70 pass
7468 01:57:58.269120 alsa_mixer-test_event_spurious_0_70 pass
7469 01:57:58.272563 alsa_mixer-test_get_value_0_69 pass
7470 01:57:58.275925 alsa_mixer-test_name_0_69 fail
7471 01:57:58.279452 alsa_mixer-test_write_default_0_69 pass
7472 01:57:58.282424 alsa_mixer-test_write_valid_0_69 pass
7473 01:57:58.285726 alsa_mixer-test_write_invalid_0_69 pass
7474 01:57:58.288921 alsa_mixer-test_event_missing_0_69 pass
7475 01:57:58.292311 alsa_mixer-test_event_spurious_0_69 pass
7476 01:57:58.296387 alsa_mixer-test_get_value_0_68 pass
7477 01:57:58.299139 alsa_mixer-test_name_0_68 fail
7478 01:57:58.302468 alsa_mixer-test_write_default_0_68 pass
7479 01:57:58.306166 alsa_mixer-test_write_valid_0_68 pass
7480 01:57:58.309374 alsa_mixer-test_write_invalid_0_68 pass
7481 01:57:58.312696 alsa_mixer-test_event_missing_0_68 pass
7482 01:57:58.318996 alsa_mixer-test_event_spurious_0_68 pass
7483 01:57:58.322455 alsa_mixer-test_get_value_0_67 pass
7484 01:57:58.322959 alsa_mixer-test_name_0_67 fail
7485 01:57:58.326194 alsa_mixer-test_write_default_0_67 pass
7486 01:57:58.328917 alsa_mixer-test_write_valid_0_67 pass
7487 01:57:58.335802 alsa_mixer-test_write_invalid_0_67 pass
7488 01:57:58.339548 alsa_mixer-test_event_missing_0_67 pass
7489 01:57:58.342078 alsa_mixer-test_event_spurious_0_67 pass
7490 01:57:58.345795 alsa_mixer-test_get_value_0_66 pass
7491 01:57:58.348867 alsa_mixer-test_name_0_66 fail
7492 01:57:58.352377 alsa_mixer-test_write_default_0_66 pass
7493 01:57:58.355651 alsa_mixer-test_write_valid_0_66 pass
7494 01:57:58.358653 alsa_mixer-test_write_invalid_0_66 pass
7495 01:57:58.365093 alsa_mixer-test_event_missing_0_66 pass
7496 01:57:58.368863 alsa_mixer-test_event_spurious_0_66 pass
7497 01:57:58.372146 alsa_mixer-test_get_value_0_65 pass
7498 01:57:58.375042 alsa_mixer-test_name_0_65 fail
7499 01:57:58.378543 alsa_mixer-test_write_default_0_65 pass
7500 01:57:58.381909 alsa_mixer-test_write_valid_0_65 pass
7501 01:57:58.384859 alsa_mixer-test_write_invalid_0_65 pass
7502 01:57:58.388081 alsa_mixer-test_event_missing_0_65 pass
7503 01:57:58.391447 alsa_mixer-test_event_spurious_0_65 pass
7504 01:57:58.398402 alsa_mixer-test_get_value_0_64 pass
7505 01:57:58.398862 alsa_mixer-test_name_0_64 fail
7506 01:57:58.405095 alsa_mixer-test_write_default_0_64 pass
7507 01:57:58.408521 alsa_mixer-test_write_valid_0_64 pass
7508 01:57:58.411654 alsa_mixer-test_write_invalid_0_64 pass
7509 01:57:58.414995 alsa_mixer-test_event_missing_0_64 pass
7510 01:57:58.418294 alsa_mixer-test_event_spurious_0_64 pass
7511 01:57:58.421535 alsa_mixer-test_get_value_0_63 pass
7512 01:57:58.424986 alsa_mixer-test_name_0_63 fail
7513 01:57:58.428262 alsa_mixer-test_write_default_0_63 pass
7514 01:57:58.435234 alsa_mixer-test_write_valid_0_63 pass
7515 01:57:58.438052 alsa_mixer-test_write_invalid_0_63 pass
7516 01:57:58.441292 alsa_mixer-test_event_missing_0_63 pass
7517 01:57:58.444683 alsa_mixer-test_event_spurious_0_63 pass
7518 01:57:58.448098 alsa_mixer-test_get_value_0_62 pass
7519 01:57:58.451117 alsa_mixer-test_name_0_62 fail
7520 01:57:58.454763 alsa_mixer-test_write_default_0_62 pass
7521 01:57:58.458529 alsa_mixer-test_write_valid_0_62 pass
7522 01:57:58.464720 alsa_mixer-test_write_invalid_0_62 pass
7523 01:57:58.468007 alsa_mixer-test_event_missing_0_62 pass
7524 01:57:58.471777 alsa_mixer-test_event_spurious_0_62 pass
7525 01:57:58.474786 alsa_mixer-test_get_value_0_61 pass
7526 01:57:58.478160 alsa_mixer-test_name_0_61 fail
7527 01:57:58.481250 alsa_mixer-test_write_default_0_61 pass
7528 01:57:58.484931 alsa_mixer-test_write_valid_0_61 pass
7529 01:57:58.488078 alsa_mixer-test_write_invalid_0_61 pass
7530 01:57:58.494481 alsa_mixer-test_event_missing_0_61 pass
7531 01:57:58.497970 alsa_mixer-test_event_spurious_0_61 pass
7532 01:57:58.500952 alsa_mixer-test_get_value_0_60 pass
7533 01:57:58.504416 alsa_mixer-test_name_0_60 fail
7534 01:57:58.507643 alsa_mixer-test_write_default_0_60 pass
7535 01:57:58.511066 alsa_mixer-test_write_valid_0_60 pass
7536 01:57:58.514102 alsa_mixer-test_write_invalid_0_60 pass
7537 01:57:58.517736 alsa_mixer-test_event_missing_0_60 pass
7538 01:57:58.524583 alsa_mixer-test_event_spurious_0_60 pass
7539 01:57:58.527860 alsa_mixer-test_get_value_0_59 pass
7540 01:57:58.530995 alsa_mixer-test_name_0_59 fail
7541 01:57:58.534360 alsa_mixer-test_write_default_0_59 pass
7542 01:57:58.537797 alsa_mixer-test_write_valid_0_59 pass
7543 01:57:58.540959 alsa_mixer-test_write_invalid_0_59 pass
7544 01:57:58.544030 alsa_mixer-test_event_missing_0_59 pass
7545 01:57:58.550884 alsa_mixer-test_event_spurious_0_59 pass
7546 01:57:58.554052 alsa_mixer-test_get_value_0_58 pass
7547 01:57:58.554508 alsa_mixer-test_name_0_58 fail
7548 01:57:58.560844 alsa_mixer-test_write_default_0_58 pass
7549 01:57:58.564604 alsa_mixer-test_write_valid_0_58 pass
7550 01:57:58.567288 alsa_mixer-test_write_invalid_0_58 pass
7551 01:57:58.570252 alsa_mixer-test_event_missing_0_58 pass
7552 01:57:58.573959 alsa_mixer-test_event_spurious_0_58 pass
7553 01:57:58.577396 alsa_mixer-test_get_value_0_57 pass
7554 01:57:58.580708 alsa_mixer-test_name_0_57 fail
7555 01:57:58.583783 alsa_mixer-test_write_default_0_57 pass
7556 01:57:58.587069 alsa_mixer-test_write_valid_0_57 pass
7557 01:57:58.590687 alsa_mixer-test_write_invalid_0_57 pass
7558 01:57:58.593373 alsa_mixer-test_event_missing_0_57 pass
7559 01:57:58.596876 alsa_mixer-test_event_spurious_0_57 pass
7560 01:57:58.600086 alsa_mixer-test_get_value_0_56 pass
7561 01:57:58.603439 alsa_mixer-test_name_0_56 fail
7562 01:57:58.606913 alsa_mixer-test_write_default_0_56 pass
7563 01:57:58.609939 alsa_mixer-test_write_valid_0_56 pass
7564 01:57:58.613454 alsa_mixer-test_write_invalid_0_56 pass
7565 01:57:58.616650 alsa_mixer-test_event_missing_0_56 pass
7566 01:57:58.623738 alsa_mixer-test_event_spurious_0_56 pass
7567 01:57:58.626669 alsa_mixer-test_get_value_0_55 pass
7568 01:57:58.627386 alsa_mixer-test_name_0_55 fail
7569 01:57:58.633485 alsa_mixer-test_write_default_0_55 pass
7570 01:57:58.636672 alsa_mixer-test_write_valid_0_55 pass
7571 01:57:58.639906 alsa_mixer-test_write_invalid_0_55 pass
7572 01:57:58.643777 alsa_mixer-test_event_missing_0_55 pass
7573 01:57:58.646605 alsa_mixer-test_event_spurious_0_55 pass
7574 01:57:58.650383 alsa_mixer-test_get_value_0_54 pass
7575 01:57:58.653513 alsa_mixer-test_name_0_54 fail
7576 01:57:58.656687 alsa_mixer-test_write_default_0_54 pass
7577 01:57:58.659879 alsa_mixer-test_write_valid_0_54 pass
7578 01:57:58.664110 alsa_mixer-test_write_invalid_0_54 pass
7579 01:57:58.666653 alsa_mixer-test_event_missing_0_54 pass
7580 01:57:58.669916 alsa_mixer-test_event_spurious_0_54 pass
7581 01:57:58.673711 alsa_mixer-test_get_value_0_53 pass
7582 01:57:58.676701 alsa_mixer-test_name_0_53 fail
7583 01:57:58.680376 alsa_mixer-test_write_default_0_53 pass
7584 01:57:58.683508 alsa_mixer-test_write_valid_0_53 pass
7585 01:57:58.690102 alsa_mixer-test_write_invalid_0_53 pass
7586 01:57:58.693886 alsa_mixer-test_event_missing_0_53 pass
7587 01:57:58.696869 alsa_mixer-test_event_spurious_0_53 pass
7588 01:57:58.700394 alsa_mixer-test_get_value_0_52 pass
7589 01:57:58.703290 alsa_mixer-test_name_0_52 fail
7590 01:57:58.706351 alsa_mixer-test_write_default_0_52 pass
7591 01:57:58.709880 alsa_mixer-test_write_valid_0_52 pass
7592 01:57:58.713035 alsa_mixer-test_write_invalid_0_52 pass
7593 01:57:58.716414 alsa_mixer-test_event_missing_0_52 pass
7594 01:57:58.719601 alsa_mixer-test_event_spurious_0_52 pass
7595 01:57:58.723325 alsa_mixer-test_get_value_0_51 pass
7596 01:57:58.726354 alsa_mixer-test_name_0_51 fail
7597 01:57:58.729778 alsa_mixer-test_write_default_0_51 pass
7598 01:57:58.733186 alsa_mixer-test_write_valid_0_51 pass
7599 01:57:58.736500 alsa_mixer-test_write_invalid_0_51 pass
7600 01:57:58.739910 alsa_mixer-test_event_missing_0_51 pass
7601 01:57:58.746186 alsa_mixer-test_event_spurious_0_51 pass
7602 01:57:58.749355 alsa_mixer-test_get_value_0_50 pass
7603 01:57:58.749775 alsa_mixer-test_name_0_50 fail
7604 01:57:58.753005 alsa_mixer-test_write_default_0_50 pass
7605 01:57:58.759697 alsa_mixer-test_write_valid_0_50 pass
7606 01:57:58.763055 alsa_mixer-test_write_invalid_0_50 pass
7607 01:57:58.766250 alsa_mixer-test_event_missing_0_50 pass
7608 01:57:58.769497 alsa_mixer-test_event_spurious_0_50 pass
7609 01:57:58.772904 alsa_mixer-test_get_value_0_49 pass
7610 01:57:58.776541 alsa_mixer-test_name_0_49 fail
7611 01:57:58.779598 alsa_mixer-test_write_default_0_49 pass
7612 01:57:58.783517 alsa_mixer-test_write_valid_0_49 pass
7613 01:57:58.786518 alsa_mixer-test_write_invalid_0_49 pass
7614 01:57:58.789547 alsa_mixer-test_event_missing_0_49 pass
7615 01:57:58.793308 alsa_mixer-test_event_spurious_0_49 pass
7616 01:57:58.796295 alsa_mixer-test_get_value_0_48 pass
7617 01:57:58.799576 alsa_mixer-test_name_0_48 fail
7618 01:57:58.803402 alsa_mixer-test_write_default_0_48 pass
7619 01:57:58.806257 alsa_mixer-test_write_valid_0_48 pass
7620 01:57:58.809765 alsa_mixer-test_write_invalid_0_48 pass
7621 01:57:58.816681 alsa_mixer-test_event_missing_0_48 pass
7622 01:57:58.819822 alsa_mixer-test_event_spurious_0_48 pass
7623 01:57:58.822901 alsa_mixer-test_get_value_0_47 pass
7624 01:57:58.827020 alsa_mixer-test_name_0_47 fail
7625 01:57:58.829440 alsa_mixer-test_write_default_0_47 pass
7626 01:57:58.832750 alsa_mixer-test_write_valid_0_47 pass
7627 01:57:58.836065 alsa_mixer-test_write_invalid_0_47 pass
7628 01:57:58.839257 alsa_mixer-test_event_missing_0_47 pass
7629 01:57:58.842902 alsa_mixer-test_event_spurious_0_47 pass
7630 01:57:58.846243 alsa_mixer-test_get_value_0_46 pass
7631 01:57:58.849459 alsa_mixer-test_name_0_46 fail
7632 01:57:58.852651 alsa_mixer-test_write_default_0_46 pass
7633 01:57:58.856123 alsa_mixer-test_write_valid_0_46 pass
7634 01:57:58.859598 alsa_mixer-test_write_invalid_0_46 pass
7635 01:57:58.863210 alsa_mixer-test_event_missing_0_46 pass
7636 01:57:58.869438 alsa_mixer-test_event_spurious_0_46 pass
7637 01:57:58.872975 alsa_mixer-test_get_value_0_45 pass
7638 01:57:58.873638 alsa_mixer-test_name_0_45 fail
7639 01:57:58.875900 alsa_mixer-test_write_default_0_45 pass
7640 01:57:58.882718 alsa_mixer-test_write_valid_0_45 pass
7641 01:57:58.885752 alsa_mixer-test_write_invalid_0_45 pass
7642 01:57:58.889290 alsa_mixer-test_event_missing_0_45 pass
7643 01:57:58.892666 alsa_mixer-test_event_spurious_0_45 pass
7644 01:57:58.895886 alsa_mixer-test_get_value_0_44 pass
7645 01:57:58.898819 alsa_mixer-test_name_0_44 fail
7646 01:57:58.902522 alsa_mixer-test_write_default_0_44 pass
7647 01:57:58.905457 alsa_mixer-test_write_valid_0_44 pass
7648 01:57:58.909430 alsa_mixer-test_write_invalid_0_44 pass
7649 01:57:58.912175 alsa_mixer-test_event_missing_0_44 pass
7650 01:57:58.916330 alsa_mixer-test_event_spurious_0_44 pass
7651 01:57:58.919277 alsa_mixer-test_get_value_0_43 pass
7652 01:57:58.922411 alsa_mixer-test_name_0_43 fail
7653 01:57:58.926056 alsa_mixer-test_write_default_0_43 pass
7654 01:57:58.929000 alsa_mixer-test_write_valid_0_43 pass
7655 01:57:58.932136 alsa_mixer-test_write_invalid_0_43 pass
7656 01:57:58.939118 alsa_mixer-test_event_missing_0_43 pass
7657 01:57:58.942504 alsa_mixer-test_event_spurious_0_43 pass
7658 01:57:58.945612 alsa_mixer-test_get_value_0_42 pass
7659 01:57:58.949315 alsa_mixer-test_name_0_42 fail
7660 01:57:58.952608 alsa_mixer-test_write_default_0_42 pass
7661 01:57:58.955937 alsa_mixer-test_write_valid_0_42 pass
7662 01:57:58.959145 alsa_mixer-test_write_invalid_0_42 pass
7663 01:57:58.962750 alsa_mixer-test_event_missing_0_42 pass
7664 01:57:58.965617 alsa_mixer-test_event_spurious_0_42 pass
7665 01:57:58.968771 alsa_mixer-test_get_value_0_41 pass
7666 01:57:58.972152 alsa_mixer-test_name_0_41 fail
7667 01:57:58.975477 alsa_mixer-test_write_default_0_41 pass
7668 01:57:58.978557 alsa_mixer-test_write_valid_0_41 pass
7669 01:57:58.982060 alsa_mixer-test_write_invalid_0_41 pass
7670 01:57:58.985159 alsa_mixer-test_event_missing_0_41 pass
7671 01:57:58.992143 alsa_mixer-test_event_spurious_0_41 pass
7672 01:57:58.995330 alsa_mixer-test_get_value_0_40 pass
7673 01:57:58.995790 alsa_mixer-test_name_0_40 fail
7674 01:57:59.002402 alsa_mixer-test_write_default_0_40 pass
7675 01:57:59.005284 alsa_mixer-test_write_valid_0_40 pass
7676 01:57:59.008610 alsa_mixer-test_write_invalid_0_40 pass
7677 01:57:59.012483 alsa_mixer-test_event_missing_0_40 pass
7678 01:57:59.015306 alsa_mixer-test_event_spurious_0_40 pass
7679 01:57:59.018478 alsa_mixer-test_get_value_0_39 pass
7680 01:57:59.021799 alsa_mixer-test_name_0_39 fail
7681 01:57:59.025823 alsa_mixer-test_write_default_0_39 pass
7682 01:57:59.028442 alsa_mixer-test_write_valid_0_39 pass
7683 01:57:59.032089 alsa_mixer-test_write_invalid_0_39 pass
7684 01:57:59.035558 alsa_mixer-test_event_missing_0_39 pass
7685 01:57:59.038453 alsa_mixer-test_event_spurious_0_39 pass
7686 01:57:59.042004 alsa_mixer-test_get_value_0_38 pass
7687 01:57:59.045057 alsa_mixer-test_name_0_38 fail
7688 01:57:59.048927 alsa_mixer-test_write_default_0_38 pass
7689 01:57:59.051774 alsa_mixer-test_write_valid_0_38 pass
7690 01:57:59.055265 alsa_mixer-test_write_invalid_0_38 pass
7691 01:57:59.061678 alsa_mixer-test_event_missing_0_38 pass
7692 01:57:59.065238 alsa_mixer-test_event_spurious_0_38 pass
7693 01:57:59.068382 alsa_mixer-test_get_value_0_37 pass
7694 01:57:59.068894 alsa_mixer-test_name_0_37 fail
7695 01:57:59.071529 alsa_mixer-test_write_default_0_37 pass
7696 01:57:59.074786 alsa_mixer-test_write_valid_0_37 pass
7697 01:57:59.082255 alsa_mixer-test_write_invalid_0_37 pass
7698 01:57:59.084864 alsa_mixer-test_event_missing_0_37 pass
7699 01:57:59.088547 alsa_mixer-test_event_spurious_0_37 pass
7700 01:57:59.091804 alsa_mixer-test_get_value_0_36 pass
7701 01:57:59.095266 alsa_mixer-test_name_0_36 fail
7702 01:57:59.097855 alsa_mixer-test_write_default_0_36 pass
7703 01:57:59.101666 alsa_mixer-test_write_valid_0_36 pass
7704 01:57:59.104940 alsa_mixer-test_write_invalid_0_36 pass
7705 01:57:59.108329 alsa_mixer-test_event_missing_0_36 pass
7706 01:57:59.111648 alsa_mixer-test_event_spurious_0_36 pass
7707 01:57:59.114489 alsa_mixer-test_get_value_0_35 pass
7708 01:57:59.118137 alsa_mixer-test_name_0_35 fail
7709 01:57:59.121326 alsa_mixer-test_write_default_0_35 pass
7710 01:57:59.124678 alsa_mixer-test_write_valid_0_35 pass
7711 01:57:59.128552 alsa_mixer-test_write_invalid_0_35 pass
7712 01:57:59.131611 alsa_mixer-test_event_missing_0_35 pass
7713 01:57:59.134937 alsa_mixer-test_event_spurious_0_35 pass
7714 01:57:59.137831 alsa_mixer-test_get_value_0_34 pass
7715 01:57:59.141630 alsa_mixer-test_name_0_34 fail
7716 01:57:59.144585 alsa_mixer-test_write_default_0_34 pass
7717 01:57:59.147502 alsa_mixer-test_write_valid_0_34 pass
7718 01:57:59.151448 alsa_mixer-test_write_invalid_0_34 pass
7719 01:57:59.154521 alsa_mixer-test_event_missing_0_34 pass
7720 01:57:59.157836 alsa_mixer-test_event_spurious_0_34 pass
7721 01:57:59.161086 alsa_mixer-test_get_value_0_33 pass
7722 01:57:59.164402 alsa_mixer-test_name_0_33 fail
7723 01:57:59.167897 alsa_mixer-test_write_default_0_33 pass
7724 01:57:59.171197 alsa_mixer-test_write_valid_0_33 pass
7725 01:57:59.174701 alsa_mixer-test_write_invalid_0_33 pass
7726 01:57:59.177784 alsa_mixer-test_event_missing_0_33 pass
7727 01:57:59.180896 alsa_mixer-test_event_spurious_0_33 pass
7728 01:57:59.184670 alsa_mixer-test_get_value_0_32 pass
7729 01:57:59.188041 alsa_mixer-test_name_0_32 fail
7730 01:57:59.190818 alsa_mixer-test_write_default_0_32 pass
7731 01:57:59.194813 alsa_mixer-test_write_valid_0_32 pass
7732 01:57:59.197324 alsa_mixer-test_write_invalid_0_32 pass
7733 01:57:59.200587 alsa_mixer-test_event_missing_0_32 pass
7734 01:57:59.204151 alsa_mixer-test_event_spurious_0_32 pass
7735 01:57:59.207893 alsa_mixer-test_get_value_0_31 pass
7736 01:57:59.210747 alsa_mixer-test_name_0_31 fail
7737 01:57:59.213959 alsa_mixer-test_write_default_0_31 pass
7738 01:57:59.217417 alsa_mixer-test_write_valid_0_31 pass
7739 01:57:59.220773 alsa_mixer-test_write_invalid_0_31 pass
7740 01:57:59.227463 alsa_mixer-test_event_missing_0_31 pass
7741 01:57:59.230572 alsa_mixer-test_event_spurious_0_31 pass
7742 01:57:59.234087 alsa_mixer-test_get_value_0_30 pass
7743 01:57:59.234539 alsa_mixer-test_name_0_30 fail
7744 01:57:59.240572 alsa_mixer-test_write_default_0_30 pass
7745 01:57:59.244240 alsa_mixer-test_write_valid_0_30 pass
7746 01:57:59.247094 alsa_mixer-test_write_invalid_0_30 pass
7747 01:57:59.250488 alsa_mixer-test_event_missing_0_30 pass
7748 01:57:59.253859 alsa_mixer-test_event_spurious_0_30 pass
7749 01:57:59.257133 alsa_mixer-test_get_value_0_29 pass
7750 01:57:59.260316 alsa_mixer-test_name_0_29 pass
7751 01:57:59.263549 alsa_mixer-test_write_default_0_29 pass
7752 01:57:59.266945 alsa_mixer-test_write_valid_0_29 pass
7753 01:57:59.270333 alsa_mixer-test_write_invalid_0_29 pass
7754 01:57:59.274050 alsa_mixer-test_event_missing_0_29 pass
7755 01:57:59.276635 alsa_mixer-test_event_spurious_0_29 pass
7756 01:57:59.280612 alsa_mixer-test_get_value_0_28 pass
7757 01:57:59.283357 alsa_mixer-test_name_0_28 pass
7758 01:57:59.286420 alsa_mixer-test_write_default_0_28 pass
7759 01:57:59.290140 alsa_mixer-test_write_valid_0_28 pass
7760 01:57:59.293896 alsa_mixer-test_write_invalid_0_28 pass
7761 01:57:59.296660 alsa_mixer-test_event_missing_0_28 pass
7762 01:57:59.299691 alsa_mixer-test_event_spurious_0_28 pass
7763 01:57:59.303054 alsa_mixer-test_get_value_0_27 pass
7764 01:57:59.306398 alsa_mixer-test_name_0_27 pass
7765 01:57:59.309751 alsa_mixer-test_write_default_0_27 pass
7766 01:57:59.313189 alsa_mixer-test_write_valid_0_27 pass
7767 01:57:59.316514 alsa_mixer-test_write_invalid_0_27 pass
7768 01:57:59.320302 alsa_mixer-test_event_missing_0_27 pass
7769 01:57:59.323001 alsa_mixer-test_event_spurious_0_27 pass
7770 01:57:59.326313 alsa_mixer-test_get_value_0_26 pass
7771 01:57:59.329745 alsa_mixer-test_name_0_26 pass
7772 01:57:59.333318 alsa_mixer-test_write_default_0_26 pass
7773 01:57:59.336634 alsa_mixer-test_write_valid_0_26 pass
7774 01:57:59.339722 alsa_mixer-test_write_invalid_0_26 pass
7775 01:57:59.343228 alsa_mixer-test_event_missing_0_26 pass
7776 01:57:59.349626 alsa_mixer-test_event_spurious_0_26 pass
7777 01:57:59.350094 alsa_mixer-test_get_value_0_25 pass
7778 01:57:59.352971 alsa_mixer-test_name_0_25 pass
7779 01:57:59.356036 alsa_mixer-test_write_default_0_25 pass
7780 01:57:59.359238 alsa_mixer-test_write_valid_0_25 pass
7781 01:57:59.362937 alsa_mixer-test_write_invalid_0_25 pass
7782 01:57:59.369447 alsa_mixer-test_event_missing_0_25 pass
7783 01:57:59.372942 alsa_mixer-test_event_spurious_0_25 pass
7784 01:57:59.376104 alsa_mixer-test_get_value_0_24 pass
7785 01:57:59.376667 alsa_mixer-test_name_0_24 pass
7786 01:57:59.383169 alsa_mixer-test_write_default_0_24 pass
7787 01:57:59.386291 alsa_mixer-test_write_valid_0_24 pass
7788 01:57:59.389720 alsa_mixer-test_write_invalid_0_24 pass
7789 01:57:59.393066 alsa_mixer-test_event_missing_0_24 pass
7790 01:57:59.396289 alsa_mixer-test_event_spurious_0_24 pass
7791 01:57:59.399054 alsa_mixer-test_get_value_0_23 pass
7792 01:57:59.402348 alsa_mixer-test_name_0_23 pass
7793 01:57:59.406002 alsa_mixer-test_write_default_0_23 pass
7794 01:57:59.409017 alsa_mixer-test_write_valid_0_23 pass
7795 01:57:59.412365 alsa_mixer-test_write_invalid_0_23 pass
7796 01:57:59.415576 alsa_mixer-test_event_missing_0_23 pass
7797 01:57:59.418687 alsa_mixer-test_event_spurious_0_23 pass
7798 01:57:59.422058 alsa_mixer-test_get_value_0_22 pass
7799 01:57:59.426184 alsa_mixer-test_name_0_22 pass
7800 01:57:59.429091 alsa_mixer-test_write_default_0_22 pass
7801 01:57:59.432528 alsa_mixer-test_write_valid_0_22 pass
7802 01:57:59.435349 alsa_mixer-test_write_invalid_0_22 pass
7803 01:57:59.438870 alsa_mixer-test_event_missing_0_22 pass
7804 01:57:59.442203 alsa_mixer-test_event_spurious_0_22 pass
7805 01:57:59.445472 alsa_mixer-test_get_value_0_21 pass
7806 01:57:59.448428 alsa_mixer-test_name_0_21 fail
7807 01:57:59.452001 alsa_mixer-test_write_default_0_21 pass
7808 01:57:59.455226 alsa_mixer-test_write_valid_0_21 pass
7809 01:57:59.458315 alsa_mixer-test_write_invalid_0_21 pass
7810 01:57:59.461842 alsa_mixer-test_event_missing_0_21 pass
7811 01:57:59.465170 alsa_mixer-test_event_spurious_0_21 pass
7812 01:57:59.468694 alsa_mixer-test_get_value_0_20 pass
7813 01:57:59.471831 alsa_mixer-test_name_0_20 fail
7814 01:57:59.475048 alsa_mixer-test_write_default_0_20 pass
7815 01:57:59.478570 alsa_mixer-test_write_valid_0_20 pass
7816 01:57:59.482173 alsa_mixer-test_write_invalid_0_20 pass
7817 01:57:59.485074 alsa_mixer-test_event_missing_0_20 pass
7818 01:57:59.491706 alsa_mixer-test_event_spurious_0_20 pass
7819 01:57:59.492261 alsa_mixer-test_get_value_0_19 pass
7820 01:57:59.494912 alsa_mixer-test_name_0_19 fail
7821 01:57:59.498103 alsa_mixer-test_write_default_0_19 pass
7822 01:57:59.501432 alsa_mixer-test_write_valid_0_19 pass
7823 01:57:59.508121 alsa_mixer-test_write_invalid_0_19 pass
7824 01:57:59.511844 alsa_mixer-test_event_missing_0_19 pass
7825 01:57:59.514976 alsa_mixer-test_event_spurious_0_19 pass
7826 01:57:59.518073 alsa_mixer-test_get_value_0_18 pass
7827 01:57:59.521221 alsa_mixer-test_name_0_18 fail
7828 01:57:59.525054 alsa_mixer-test_write_default_0_18 pass
7829 01:57:59.527937 alsa_mixer-test_write_valid_0_18 pass
7830 01:57:59.531831 alsa_mixer-test_write_invalid_0_18 pass
7831 01:57:59.534934 alsa_mixer-test_event_missing_0_18 pass
7832 01:57:59.538208 alsa_mixer-test_event_spurious_0_18 pass
7833 01:57:59.541416 alsa_mixer-test_get_value_0_17 pass
7834 01:57:59.545070 alsa_mixer-test_name_0_17 fail
7835 01:57:59.547916 alsa_mixer-test_write_default_0_17 pass
7836 01:57:59.551470 alsa_mixer-test_write_valid_0_17 pass
7837 01:57:59.554536 alsa_mixer-test_write_invalid_0_17 pass
7838 01:57:59.557878 alsa_mixer-test_event_missing_0_17 pass
7839 01:57:59.561189 alsa_mixer-test_event_spurious_0_17 pass
7840 01:57:59.564520 alsa_mixer-test_get_value_0_16 pass
7841 01:57:59.567924 alsa_mixer-test_name_0_16 fail
7842 01:57:59.571125 alsa_mixer-test_write_default_0_16 pass
7843 01:57:59.574203 alsa_mixer-test_write_valid_0_16 pass
7844 01:57:59.578404 alsa_mixer-test_write_invalid_0_16 pass
7845 01:57:59.580940 alsa_mixer-test_event_missing_0_16 pass
7846 01:57:59.583972 alsa_mixer-test_event_spurious_0_16 pass
7847 01:57:59.587457 alsa_mixer-test_get_value_0_15 pass
7848 01:57:59.590706 alsa_mixer-test_name_0_15 fail
7849 01:57:59.594228 alsa_mixer-test_write_default_0_15 pass
7850 01:57:59.597306 alsa_mixer-test_write_valid_0_15 pass
7851 01:57:59.600558 alsa_mixer-test_write_invalid_0_15 pass
7852 01:57:59.604159 alsa_mixer-test_event_missing_0_15 pass
7853 01:57:59.607590 alsa_mixer-test_event_spurious_0_15 pass
7854 01:57:59.610909 alsa_mixer-test_get_value_0_14 pass
7855 01:57:59.614172 alsa_mixer-test_name_0_14 fail
7856 01:57:59.617400 alsa_mixer-test_write_default_0_14 pass
7857 01:57:59.620595 alsa_mixer-test_write_valid_0_14 pass
7858 01:57:59.624189 alsa_mixer-test_write_invalid_0_14 pass
7859 01:57:59.627582 alsa_mixer-test_event_missing_0_14 pass
7860 01:57:59.634296 alsa_mixer-test_event_spurious_0_14 pass
7861 01:57:59.637807 alsa_mixer-test_get_value_0_13 pass
7862 01:57:59.638286 alsa_mixer-test_name_0_13 fail
7863 01:57:59.640915 alsa_mixer-test_write_default_0_13 pass
7864 01:57:59.647616 alsa_mixer-test_write_valid_0_13 pass
7865 01:57:59.651283 alsa_mixer-test_write_invalid_0_13 pass
7866 01:57:59.654127 alsa_mixer-test_event_missing_0_13 pass
7867 01:57:59.657565 alsa_mixer-test_event_spurious_0_13 pass
7868 01:57:59.660658 alsa_mixer-test_get_value_0_12 pass
7869 01:57:59.664060 alsa_mixer-test_name_0_12 fail
7870 01:57:59.667729 alsa_mixer-test_write_default_0_12 pass
7871 01:57:59.670591 alsa_mixer-test_write_valid_0_12 pass
7872 01:57:59.673937 alsa_mixer-test_write_invalid_0_12 pass
7873 01:57:59.677372 alsa_mixer-test_event_missing_0_12 pass
7874 01:57:59.681106 alsa_mixer-test_event_spurious_0_12 pass
7875 01:57:59.683964 alsa_mixer-test_get_value_0_11 pass
7876 01:57:59.687097 alsa_mixer-test_name_0_11 fail
7877 01:57:59.690489 alsa_mixer-test_write_default_0_11 pass
7878 01:57:59.694085 alsa_mixer-test_write_valid_0_11 pass
7879 01:57:59.700578 alsa_mixer-test_write_invalid_0_11 pass
7880 01:57:59.703797 alsa_mixer-test_event_missing_0_11 pass
7881 01:57:59.707728 alsa_mixer-test_event_spurious_0_11 pass
7882 01:57:59.710528 alsa_mixer-test_get_value_0_10 pass
7883 01:57:59.714237 alsa_mixer-test_name_0_10 fail
7884 01:57:59.717327 alsa_mixer-test_write_default_0_10 pass
7885 01:57:59.720682 alsa_mixer-test_write_valid_0_10 pass
7886 01:57:59.723934 alsa_mixer-test_write_invalid_0_10 pass
7887 01:57:59.726982 alsa_mixer-test_event_missing_0_10 pass
7888 01:57:59.730404 alsa_mixer-test_event_spurious_0_10 pass
7889 01:57:59.733801 alsa_mixer-test_get_value_0_9 pass
7890 01:57:59.736886 alsa_mixer-test_name_0_9 fail
7891 01:57:59.740458 alsa_mixer-test_write_default_0_9 pass
7892 01:57:59.743597 alsa_mixer-test_write_valid_0_9 pass
7893 01:57:59.747079 alsa_mixer-test_write_invalid_0_9 pass
7894 01:57:59.750114 alsa_mixer-test_event_missing_0_9 pass
7895 01:57:59.753861 alsa_mixer-test_event_spurious_0_9 pass
7896 01:57:59.756917 alsa_mixer-test_get_value_0_8 pass
7897 01:57:59.760117 alsa_mixer-test_name_0_8 fail
7898 01:57:59.763508 alsa_mixer-test_write_default_0_8 pass
7899 01:57:59.767056 alsa_mixer-test_write_valid_0_8 pass
7900 01:57:59.770141 alsa_mixer-test_write_invalid_0_8 pass
7901 01:57:59.773428 alsa_mixer-test_event_missing_0_8 pass
7902 01:57:59.776758 alsa_mixer-test_event_spurious_0_8 pass
7903 01:57:59.780309 alsa_mixer-test_get_value_0_7 pass
7904 01:57:59.783484 alsa_mixer-test_name_0_7 fail
7905 01:57:59.786670 alsa_mixer-test_write_default_0_7 pass
7906 01:57:59.789977 alsa_mixer-test_write_valid_0_7 pass
7907 01:57:59.793191 alsa_mixer-test_write_invalid_0_7 pass
7908 01:57:59.796339 alsa_mixer-test_event_missing_0_7 pass
7909 01:57:59.800045 alsa_mixer-test_event_spurious_0_7 pass
7910 01:57:59.803024 alsa_mixer-test_get_value_0_6 pass
7911 01:57:59.806429 alsa_mixer-test_name_0_6 fail
7912 01:57:59.809571 alsa_mixer-test_write_default_0_6 pass
7913 01:57:59.812769 alsa_mixer-test_write_valid_0_6 pass
7914 01:57:59.816212 alsa_mixer-test_write_invalid_0_6 pass
7915 01:57:59.819584 alsa_mixer-test_event_missing_0_6 pass
7916 01:57:59.822730 alsa_mixer-test_event_spurious_0_6 pass
7917 01:57:59.826285 alsa_mixer-test_get_value_0_5 pass
7918 01:57:59.829428 alsa_mixer-test_name_0_5 pass
7919 01:57:59.832815 alsa_mixer-test_write_default_0_5 pass
7920 01:57:59.836297 alsa_mixer-test_write_valid_0_5 pass
7921 01:57:59.840054 alsa_mixer-test_write_invalid_0_5 pass
7922 01:57:59.842861 alsa_mixer-test_event_missing_0_5 fail
7923 01:57:59.846277 alsa_mixer-test_event_spurious_0_5 pass
7924 01:57:59.849900 alsa_mixer-test_get_value_0_4 pass
7925 01:57:59.853166 alsa_mixer-test_name_0_4 pass
7926 01:57:59.856269 alsa_mixer-test_write_default_0_4 pass
7927 01:57:59.859601 alsa_mixer-test_write_valid_0_4 pass
7928 01:57:59.863530 alsa_mixer-test_write_invalid_0_4 pass
7929 01:57:59.866558 alsa_mixer-test_event_missing_0_4 fail
7930 01:57:59.869780 alsa_mixer-test_event_spurious_0_4 pass
7931 01:57:59.873042 alsa_mixer-test_get_value_0_3 pass
7932 01:57:59.876508 alsa_mixer-test_name_0_3 pass
7933 01:57:59.879767 alsa_mixer-test_write_default_0_3 pass
7934 01:57:59.882987 alsa_mixer-test_write_valid_0_3 pass
7935 01:57:59.886557 alsa_mixer-test_write_invalid_0_3 pass
7936 01:57:59.889567 alsa_mixer-test_event_missing_0_3 fail
7937 01:57:59.893335 alsa_mixer-test_event_spurious_0_3 pass
7938 01:57:59.896170 alsa_mixer-test_get_value_0_2 pass
7939 01:57:59.899474 alsa_mixer-test_name_0_2 pass
7940 01:57:59.902909 alsa_mixer-test_write_default_0_2 pass
7941 01:57:59.906213 alsa_mixer-test_write_valid_0_2 pass
7942 01:57:59.909377 alsa_mixer-test_write_invalid_0_2 pass
7943 01:57:59.912891 alsa_mixer-test_event_missing_0_2 fail
7944 01:57:59.916250 alsa_mixer-test_event_spurious_0_2 pass
7945 01:57:59.919327 alsa_mixer-test_get_value_0_1 pass
7946 01:57:59.922616 alsa_mixer-test_name_0_1 pass
7947 01:57:59.925938 alsa_mixer-test_write_default_0_1 pass
7948 01:57:59.929464 alsa_mixer-test_write_valid_0_1 pass
7949 01:57:59.932637 alsa_mixer-test_write_invalid_0_1 pass
7950 01:57:59.936320 alsa_mixer-test_event_missing_0_1 fail
7951 01:57:59.939185 alsa_mixer-test_event_spurious_0_1 pass
7952 01:57:59.943176 alsa_mixer-test_get_value_0_0 pass
7953 01:57:59.945998 alsa_mixer-test_name_0_0 pass
7954 01:57:59.949052 alsa_mixer-test_write_default_0_0 pass
7955 01:57:59.952228 alsa_mixer-test_write_valid_0_0 pass
7956 01:57:59.955692 alsa_mixer-test_write_invalid_0_0 pass
7957 01:57:59.959037 alsa_mixer-test_event_missing_0_0 fail
7958 01:57:59.962374 alsa_mixer-test_event_spurious_0_0 pass
7959 01:57:59.966106 alsa_mixer-test pass
7960 01:57:59.969084 + ../../utils/send-to-lava.sh ./output/result.txt
7961 01:57:59.975599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
7962 01:57:59.975893 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
7964 01:57:59.982036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_93 RESULT=pass>
7965 01:57:59.982288 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_93 RESULT=pass
7967 01:57:59.988579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_93 RESULT=pass>
7968 01:57:59.988831 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_93 RESULT=pass
7970 01:57:59.995234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_93 RESULT=pass>
7971 01:57:59.995484 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_93 RESULT=pass
7973 01:58:00.011615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_93 RESULT=pass>
7974 01:58:00.011870 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_93 RESULT=pass
7976 01:58:00.053559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_93 RESULT=pass>
7977 01:58:00.053827 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_93 RESULT=pass
7979 01:58:00.095578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_93 RESULT=pass>
7980 01:58:00.095851 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_93 RESULT=pass
7982 01:58:00.137032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_93 RESULT=pass>
7983 01:58:00.137786 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_93 RESULT=pass
7985 01:58:00.181222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_92 RESULT=pass>
7986 01:58:00.182026 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_92 RESULT=pass
7988 01:58:00.220366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_92 RESULT=pass>
7989 01:58:00.220711 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_92 RESULT=pass
7991 01:58:00.268944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_92 RESULT=pass>
7992 01:58:00.269279 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_92 RESULT=pass
7994 01:58:00.309551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_92 RESULT=pass>
7995 01:58:00.309885 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_92 RESULT=pass
7997 01:58:00.353518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_92 RESULT=pass>
7998 01:58:00.353853 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_92 RESULT=pass
8000 01:58:00.406071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_92 RESULT=pass>
8001 01:58:00.406767 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_92 RESULT=pass
8003 01:58:00.458218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_92 RESULT=pass>
8004 01:58:00.458921 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_92 RESULT=pass
8006 01:58:00.512493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_91 RESULT=pass>
8007 01:58:00.513174 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_91 RESULT=pass
8009 01:58:00.556464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_91 RESULT=pass>
8010 01:58:00.557140 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_91 RESULT=pass
8012 01:58:00.608088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_91 RESULT=pass>
8013 01:58:00.608770 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_91 RESULT=pass
8015 01:58:00.659339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_91 RESULT=pass>
8016 01:58:00.660010 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_91 RESULT=pass
8018 01:58:00.711919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_91 RESULT=pass>
8019 01:58:00.712617 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_91 RESULT=pass
8021 01:58:00.764147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_91 RESULT=pass>
8022 01:58:00.764823 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_91 RESULT=pass
8024 01:58:00.814514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_91 RESULT=pass>
8025 01:58:00.815239 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_91 RESULT=pass
8027 01:58:00.869030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_90 RESULT=pass>
8028 01:58:00.869861 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_90 RESULT=pass
8030 01:58:00.922314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_90 RESULT=pass>
8031 01:58:00.923079 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_90 RESULT=pass
8033 01:58:00.978157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_90 RESULT=pass>
8034 01:58:00.978440 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_90 RESULT=pass
8036 01:58:01.025253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_90 RESULT=pass>
8037 01:58:01.025990 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_90 RESULT=pass
8039 01:58:01.082772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_90 RESULT=pass>
8040 01:58:01.083485 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_90 RESULT=pass
8042 01:58:01.144154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_90 RESULT=pass>
8043 01:58:01.144850 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_90 RESULT=pass
8045 01:58:01.191214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_90 RESULT=pass>
8046 01:58:01.191897 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_90 RESULT=pass
8048 01:58:01.243172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_89 RESULT=pass>
8049 01:58:01.243862 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_89 RESULT=pass
8051 01:58:01.292607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_89 RESULT=pass>
8052 01:58:01.293339 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_89 RESULT=pass
8054 01:58:01.351593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_89 RESULT=pass>
8055 01:58:01.352354 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_89 RESULT=pass
8057 01:58:01.399827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_89 RESULT=pass>
8058 01:58:01.400581 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_89 RESULT=pass
8060 01:58:01.448303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_89 RESULT=pass>
8061 01:58:01.449053 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_89 RESULT=pass
8063 01:58:01.505206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_89 RESULT=pass>
8064 01:58:01.506109 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_89 RESULT=pass
8066 01:58:01.554444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_89 RESULT=pass>
8067 01:58:01.555123 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_89 RESULT=pass
8069 01:58:01.602257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_88 RESULT=pass>
8070 01:58:01.602937 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_88 RESULT=pass
8072 01:58:01.651077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_88 RESULT=pass>
8073 01:58:01.651759 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_88 RESULT=pass
8075 01:58:01.703997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_88 RESULT=pass>
8076 01:58:01.704844 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_88 RESULT=pass
8078 01:58:01.753298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_88 RESULT=fail>
8079 01:58:01.754015 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_88 RESULT=fail
8081 01:58:01.805941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_88 RESULT=pass>
8082 01:58:01.806670 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_88 RESULT=pass
8084 01:58:01.861673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_88 RESULT=pass>
8085 01:58:01.862453 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_88 RESULT=pass
8087 01:58:01.908076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_88 RESULT=fail>
8088 01:58:01.908338 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_88 RESULT=fail
8090 01:58:01.953732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_87 RESULT=pass>
8091 01:58:01.954091 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_87 RESULT=pass
8093 01:58:01.995996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_87 RESULT=pass>
8094 01:58:01.996565 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_87 RESULT=pass
8096 01:58:02.052200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_87 RESULT=pass>
8097 01:58:02.052458 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_87 RESULT=pass
8099 01:58:02.096685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_87 RESULT=pass>
8100 01:58:02.096958 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_87 RESULT=pass
8102 01:58:02.143114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_87 RESULT=pass>
8103 01:58:02.143394 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_87 RESULT=pass
8105 01:58:02.187271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_87 RESULT=pass>
8106 01:58:02.187524 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_87 RESULT=pass
8108 01:58:02.233750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_87 RESULT=pass>
8109 01:58:02.234127 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_87 RESULT=pass
8111 01:58:02.280944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_86 RESULT=pass>
8112 01:58:02.281671 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_86 RESULT=pass
8114 01:58:02.328007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_86 RESULT=pass>
8115 01:58:02.328717 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_86 RESULT=pass
8117 01:58:02.374988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_86 RESULT=pass>
8118 01:58:02.375270 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_86 RESULT=pass
8120 01:58:02.414664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_86 RESULT=fail>
8121 01:58:02.414928 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_86 RESULT=fail
8123 01:58:02.461019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_86 RESULT=pass>
8124 01:58:02.462273 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_86 RESULT=pass
8126 01:58:02.510388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_86 RESULT=pass>
8127 01:58:02.511104 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_86 RESULT=pass
8129 01:58:02.563011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_86 RESULT=pass>
8130 01:58:02.563718 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_86 RESULT=pass
8132 01:58:02.612269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_85 RESULT=pass>
8133 01:58:02.612990 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_85 RESULT=pass
8135 01:58:02.658879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_85 RESULT=pass>
8136 01:58:02.659592 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_85 RESULT=pass
8138 01:58:02.709739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_85 RESULT=pass>
8139 01:58:02.710067 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_85 RESULT=pass
8141 01:58:02.759355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_85 RESULT=fail>
8142 01:58:02.759687 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_85 RESULT=fail
8144 01:58:02.807791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_85 RESULT=pass>
8145 01:58:02.808585 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_85 RESULT=pass
8147 01:58:02.857866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_85 RESULT=pass>
8148 01:58:02.858606 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_85 RESULT=pass
8150 01:58:02.912747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_85 RESULT=pass>
8151 01:58:02.913615 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_85 RESULT=pass
8153 01:58:02.960600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_84 RESULT=pass>
8154 01:58:02.961358 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_84 RESULT=pass
8156 01:58:03.012245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_84 RESULT=pass>
8157 01:58:03.013024 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_84 RESULT=pass
8159 01:58:03.064659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_84 RESULT=pass>
8160 01:58:03.065367 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_84 RESULT=pass
8162 01:58:03.119411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_84 RESULT=pass>
8163 01:58:03.120110 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_84 RESULT=pass
8165 01:58:03.171188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_84 RESULT=pass>
8166 01:58:03.171875 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_84 RESULT=pass
8168 01:58:03.223773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_84 RESULT=pass>
8169 01:58:03.224467 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_84 RESULT=pass
8171 01:58:03.274830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_84 RESULT=pass>
8172 01:58:03.275519 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_84 RESULT=pass
8174 01:58:03.330671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_83 RESULT=pass>
8175 01:58:03.331412 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_83 RESULT=pass
8177 01:58:03.378650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_83 RESULT=pass>
8178 01:58:03.379327 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_83 RESULT=pass
8180 01:58:03.435277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_83 RESULT=pass>
8181 01:58:03.435963 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_83 RESULT=pass
8183 01:58:03.489077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_83 RESULT=pass>
8184 01:58:03.489822 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_83 RESULT=pass
8186 01:58:03.537000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_83 RESULT=pass>
8187 01:58:03.537745 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_83 RESULT=pass
8189 01:58:03.586309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_83 RESULT=pass>
8190 01:58:03.587004 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_83 RESULT=pass
8192 01:58:03.637671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_83 RESULT=pass>
8193 01:58:03.638368 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_83 RESULT=pass
8195 01:58:03.692885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_82 RESULT=pass>
8196 01:58:03.693669 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_82 RESULT=pass
8198 01:58:03.741340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_82 RESULT=pass>
8199 01:58:03.742014 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_82 RESULT=pass
8201 01:58:03.791001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_82 RESULT=skip>
8202 01:58:03.791351 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_82 RESULT=skip
8204 01:58:03.841382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_82 RESULT=skip>
8205 01:58:03.841692 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_82 RESULT=skip
8207 01:58:03.889639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_82 RESULT=skip>
8208 01:58:03.889958 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_82 RESULT=skip
8210 01:58:03.930750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_82 RESULT=pass>
8211 01:58:03.931012 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_82 RESULT=pass
8213 01:58:03.971412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_82 RESULT=pass>
8214 01:58:03.971734 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_82 RESULT=pass
8216 01:58:04.017138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_81 RESULT=pass>
8217 01:58:04.017450 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_81 RESULT=pass
8219 01:58:04.054684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_81 RESULT=pass>
8220 01:58:04.054944 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_81 RESULT=pass
8222 01:58:04.107277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_81 RESULT=pass>
8223 01:58:04.107532 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_81 RESULT=pass
8225 01:58:04.154155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_81 RESULT=pass>
8226 01:58:04.154429 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_81 RESULT=pass
8228 01:58:04.201639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_81 RESULT=fail>
8229 01:58:04.201958 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_81 RESULT=fail
8231 01:58:04.241839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_81 RESULT=fail>
8232 01:58:04.242594 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_81 RESULT=fail
8234 01:58:04.302932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_81 RESULT=pass>
8235 01:58:04.303688 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_81 RESULT=pass
8237 01:58:04.351929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_80 RESULT=pass>
8238 01:58:04.352191 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_80 RESULT=pass
8240 01:58:04.399369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_80 RESULT=pass>
8241 01:58:04.399748 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_80 RESULT=pass
8243 01:58:04.449399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_80 RESULT=pass>
8244 01:58:04.449749 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_80 RESULT=pass
8246 01:58:04.484074 <6>[ 38.071305] vaux18: disabling
8247 01:58:04.487472 <6>[ 38.074861] vio28: disabling
8248 01:58:04.510662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_80 RESULT=pass>
8249 01:58:04.510935 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_80 RESULT=pass
8251 01:58:04.553809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_80 RESULT=pass>
8252 01:58:04.554078 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_80 RESULT=pass
8254 01:58:04.594552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_80 RESULT=pass>
8255 01:58:04.594854 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_80 RESULT=pass
8257 01:58:04.639823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_80 RESULT=pass>
8258 01:58:04.640184 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_80 RESULT=pass
8260 01:58:04.681515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_79 RESULT=fail>
8261 01:58:04.681846 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_79 RESULT=fail
8263 01:58:04.725584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_79 RESULT=pass>
8264 01:58:04.726015 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_79 RESULT=pass
8266 01:58:04.774059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_79 RESULT=fail>
8267 01:58:04.774742 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_79 RESULT=fail
8269 01:58:04.823366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_79 RESULT=fail>
8270 01:58:04.824140 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_79 RESULT=fail
8272 01:58:04.881359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_79 RESULT=fail>
8273 01:58:04.882082 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_79 RESULT=fail
8275 01:58:04.934769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_79 RESULT=pass>
8276 01:58:04.935508 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_79 RESULT=pass
8278 01:58:04.986220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_79 RESULT=pass>
8279 01:58:04.987012 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_79 RESULT=pass
8281 01:58:05.039868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_78 RESULT=fail>
8282 01:58:05.040655 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_78 RESULT=fail
8284 01:58:05.089152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_78 RESULT=pass>
8285 01:58:05.089850 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_78 RESULT=pass
8287 01:58:05.142179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_78 RESULT=fail>
8288 01:58:05.142900 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_78 RESULT=fail
8290 01:58:05.191855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_78 RESULT=fail>
8291 01:58:05.192560 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_78 RESULT=fail
8293 01:58:05.245866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_78 RESULT=fail>
8294 01:58:05.246648 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_78 RESULT=fail
8296 01:58:05.298830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_78 RESULT=pass>
8297 01:58:05.299605 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_78 RESULT=pass
8299 01:58:05.349806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_78 RESULT=pass>
8300 01:58:05.350512 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_78 RESULT=pass
8302 01:58:05.400666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_77 RESULT=fail>
8303 01:58:05.401435 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_77 RESULT=fail
8305 01:58:05.452284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_77 RESULT=pass>
8306 01:58:05.452991 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_77 RESULT=pass
8308 01:58:05.506957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_77 RESULT=fail>
8309 01:58:05.507643 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_77 RESULT=fail
8311 01:58:05.557025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_77 RESULT=fail>
8312 01:58:05.557752 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_77 RESULT=fail
8314 01:58:05.612758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_77 RESULT=fail>
8315 01:58:05.613605 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_77 RESULT=fail
8317 01:58:05.664256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_77 RESULT=pass>
8318 01:58:05.664946 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_77 RESULT=pass
8320 01:58:05.715569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_77 RESULT=pass>
8321 01:58:05.716254 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_77 RESULT=pass
8323 01:58:05.764485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_76 RESULT=pass>
8324 01:58:05.765162 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_76 RESULT=pass
8326 01:58:05.811082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_76 RESULT=fail>
8327 01:58:05.811754 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_76 RESULT=fail
8329 01:58:05.868143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_76 RESULT=pass>
8330 01:58:05.868925 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_76 RESULT=pass
8332 01:58:05.915717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_76 RESULT=pass>
8333 01:58:05.916407 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_76 RESULT=pass
8335 01:58:05.963422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_76 RESULT=pass>
8336 01:58:05.964115 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_76 RESULT=pass
8338 01:58:06.010911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_76 RESULT=pass>
8339 01:58:06.011640 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_76 RESULT=pass
8341 01:58:06.061207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_76 RESULT=pass>
8342 01:58:06.062435 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_76 RESULT=pass
8344 01:58:06.111100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_75 RESULT=pass>
8345 01:58:06.111784 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_75 RESULT=pass
8347 01:58:06.154682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_75 RESULT=fail>
8348 01:58:06.155385 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_75 RESULT=fail
8350 01:58:06.208939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_75 RESULT=pass>
8351 01:58:06.209672 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_75 RESULT=pass
8353 01:58:06.261354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_75 RESULT=pass>
8354 01:58:06.262123 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_75 RESULT=pass
8356 01:58:06.308682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_75 RESULT=pass>
8357 01:58:06.309042 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_75 RESULT=pass
8359 01:58:06.360188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_75 RESULT=pass>
8360 01:58:06.360868 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_75 RESULT=pass
8362 01:58:06.416717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_75 RESULT=pass>
8363 01:58:06.417376 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_75 RESULT=pass
8365 01:58:06.465822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_74 RESULT=pass>
8366 01:58:06.466504 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_74 RESULT=pass
8368 01:58:06.511322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_74 RESULT=fail>
8369 01:58:06.511997 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_74 RESULT=fail
8371 01:58:06.562636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_74 RESULT=pass>
8372 01:58:06.563321 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_74 RESULT=pass
8374 01:58:06.610976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_74 RESULT=pass>
8375 01:58:06.611231 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_74 RESULT=pass
8377 01:58:06.654388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_74 RESULT=pass>
8378 01:58:06.654665 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_74 RESULT=pass
8380 01:58:06.698439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_74 RESULT=pass>
8381 01:58:06.698829 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_74 RESULT=pass
8383 01:58:06.745455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_74 RESULT=pass>
8384 01:58:06.746131 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_74 RESULT=pass
8386 01:58:06.792114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_73 RESULT=pass>
8387 01:58:06.792375 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_73 RESULT=pass
8389 01:58:06.834632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_73 RESULT=fail>
8390 01:58:06.835428 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_73 RESULT=fail
8392 01:58:06.887527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_73 RESULT=pass>
8393 01:58:06.888316 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_73 RESULT=pass
8395 01:58:06.937668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_73 RESULT=pass>
8396 01:58:06.938394 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_73 RESULT=pass
8398 01:58:06.989065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_73 RESULT=pass>
8399 01:58:06.989899 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_73 RESULT=pass
8401 01:58:07.037738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_73 RESULT=pass>
8402 01:58:07.038425 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_73 RESULT=pass
8404 01:58:07.086309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_73 RESULT=pass>
8405 01:58:07.086987 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_73 RESULT=pass
8407 01:58:07.135126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_72 RESULT=pass>
8408 01:58:07.135936 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_72 RESULT=pass
8410 01:58:07.185082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_72 RESULT=fail>
8411 01:58:07.185862 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_72 RESULT=fail
8413 01:58:07.243276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_72 RESULT=pass>
8414 01:58:07.244115 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_72 RESULT=pass
8416 01:58:07.297627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_72 RESULT=pass>
8417 01:58:07.298522 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_72 RESULT=pass
8419 01:58:07.343301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_72 RESULT=pass>
8420 01:58:07.344008 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_72 RESULT=pass
8422 01:58:07.392567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_72 RESULT=pass>
8423 01:58:07.393248 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_72 RESULT=pass
8425 01:58:07.443850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_72 RESULT=pass>
8426 01:58:07.444679 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_72 RESULT=pass
8428 01:58:07.493048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_71 RESULT=pass>
8429 01:58:07.494013 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_71 RESULT=pass
8431 01:58:07.535100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_71 RESULT=fail>
8432 01:58:07.535795 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_71 RESULT=fail
8434 01:58:07.583912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_71 RESULT=pass>
8435 01:58:07.584722 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_71 RESULT=pass
8437 01:58:07.633104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_71 RESULT=pass>
8438 01:58:07.633941 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_71 RESULT=pass
8440 01:58:07.683253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_71 RESULT=pass>
8441 01:58:07.684079 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_71 RESULT=pass
8443 01:58:07.734490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_71 RESULT=pass>
8444 01:58:07.735096 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_71 RESULT=pass
8446 01:58:07.785329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_71 RESULT=pass>
8447 01:58:07.785678 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_71 RESULT=pass
8449 01:58:07.828045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_70 RESULT=pass>
8450 01:58:07.828337 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_70 RESULT=pass
8452 01:58:07.871801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_70 RESULT=fail>
8453 01:58:07.872068 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_70 RESULT=fail
8455 01:58:07.919654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_70 RESULT=pass>
8456 01:58:07.920304 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_70 RESULT=pass
8458 01:58:07.968638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_70 RESULT=pass>
8459 01:58:07.969329 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_70 RESULT=pass
8461 01:58:08.021168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_70 RESULT=pass>
8462 01:58:08.021910 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_70 RESULT=pass
8464 01:58:08.077640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_70 RESULT=pass>
8465 01:58:08.078415 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_70 RESULT=pass
8467 01:58:08.124863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_70 RESULT=pass>
8468 01:58:08.125670 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_70 RESULT=pass
8470 01:58:08.176101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_69 RESULT=pass>
8471 01:58:08.176789 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_69 RESULT=pass
8473 01:58:08.231430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_69 RESULT=fail>
8474 01:58:08.232314 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_69 RESULT=fail
8476 01:58:08.284208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_69 RESULT=pass>
8477 01:58:08.284895 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_69 RESULT=pass
8479 01:58:08.340338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_69 RESULT=pass>
8480 01:58:08.341015 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_69 RESULT=pass
8482 01:58:08.389691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_69 RESULT=pass>
8483 01:58:08.390363 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_69 RESULT=pass
8485 01:58:08.440386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_69 RESULT=pass>
8486 01:58:08.440668 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_69 RESULT=pass
8488 01:58:08.492452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_69 RESULT=pass>
8489 01:58:08.493141 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_69 RESULT=pass
8491 01:58:08.540596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_68 RESULT=pass>
8492 01:58:08.541371 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_68 RESULT=pass
8494 01:58:08.588007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_68 RESULT=fail>
8495 01:58:08.588814 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_68 RESULT=fail
8497 01:58:08.646207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_68 RESULT=pass>
8498 01:58:08.647123 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_68 RESULT=pass
8500 01:58:08.698248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_68 RESULT=pass>
8501 01:58:08.699202 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_68 RESULT=pass
8503 01:58:08.750189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_68 RESULT=pass>
8504 01:58:08.751114 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_68 RESULT=pass
8506 01:58:08.800176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_68 RESULT=pass>
8507 01:58:08.800996 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_68 RESULT=pass
8509 01:58:08.851493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_68 RESULT=pass>
8510 01:58:08.852328 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_68 RESULT=pass
8512 01:58:08.905347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_67 RESULT=pass>
8513 01:58:08.906253 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_67 RESULT=pass
8515 01:58:08.949735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_67 RESULT=fail>
8516 01:58:08.950518 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_67 RESULT=fail
8518 01:58:09.007960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_67 RESULT=pass>
8519 01:58:09.008731 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_67 RESULT=pass
8521 01:58:09.057142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_67 RESULT=pass>
8522 01:58:09.057878 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_67 RESULT=pass
8524 01:58:09.110025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_67 RESULT=pass>
8525 01:58:09.110711 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_67 RESULT=pass
8527 01:58:09.162952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_67 RESULT=pass>
8528 01:58:09.163782 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_67 RESULT=pass
8530 01:58:09.216038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_67 RESULT=pass>
8531 01:58:09.216790 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_67 RESULT=pass
8533 01:58:09.263165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_66 RESULT=pass>
8534 01:58:09.263936 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_66 RESULT=pass
8536 01:58:09.311062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_66 RESULT=fail>
8537 01:58:09.311747 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_66 RESULT=fail
8539 01:58:09.370749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_66 RESULT=pass>
8540 01:58:09.371508 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_66 RESULT=pass
8542 01:58:09.422844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_66 RESULT=pass>
8543 01:58:09.423606 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_66 RESULT=pass
8545 01:58:09.473019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_66 RESULT=pass>
8546 01:58:09.473789 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_66 RESULT=pass
8548 01:58:09.526469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_66 RESULT=pass>
8549 01:58:09.527217 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_66 RESULT=pass
8551 01:58:09.577887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_66 RESULT=pass>
8552 01:58:09.578572 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_66 RESULT=pass
8554 01:58:09.628989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_65 RESULT=pass>
8555 01:58:09.629711 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_65 RESULT=pass
8557 01:58:09.675572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_65 RESULT=fail>
8558 01:58:09.676395 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_65 RESULT=fail
8560 01:58:09.724932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_65 RESULT=pass>
8561 01:58:09.725770 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_65 RESULT=pass
8563 01:58:09.771310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_65 RESULT=pass>
8564 01:58:09.772180 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_65 RESULT=pass
8566 01:58:09.820132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_65 RESULT=pass>
8567 01:58:09.820935 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_65 RESULT=pass
8569 01:58:09.868842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_65 RESULT=pass>
8570 01:58:09.869179 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_65 RESULT=pass
8572 01:58:09.911357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_65 RESULT=pass>
8573 01:58:09.911672 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_65 RESULT=pass
8575 01:58:09.954955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_64 RESULT=pass>
8576 01:58:09.955303 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_64 RESULT=pass
8578 01:58:09.992955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_64 RESULT=fail>
8579 01:58:09.993318 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_64 RESULT=fail
8581 01:58:10.036940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_64 RESULT=pass>
8582 01:58:10.037285 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_64 RESULT=pass
8584 01:58:10.074212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_64 RESULT=pass>
8585 01:58:10.074518 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_64 RESULT=pass
8587 01:58:10.119996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_64 RESULT=pass>
8588 01:58:10.120300 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_64 RESULT=pass
8590 01:58:10.159256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_64 RESULT=pass>
8591 01:58:10.159612 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_64 RESULT=pass
8593 01:58:10.204091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_64 RESULT=pass>
8594 01:58:10.204440 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_64 RESULT=pass
8596 01:58:10.248377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_63 RESULT=pass>
8597 01:58:10.248701 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_63 RESULT=pass
8599 01:58:10.290532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_63 RESULT=fail>
8600 01:58:10.290861 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_63 RESULT=fail
8602 01:58:10.340122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_63 RESULT=pass>
8603 01:58:10.340479 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_63 RESULT=pass
8605 01:58:10.381217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_63 RESULT=pass>
8606 01:58:10.381562 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_63 RESULT=pass
8608 01:58:10.420087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_63 RESULT=pass>
8609 01:58:10.420440 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_63 RESULT=pass
8611 01:58:10.455830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_63 RESULT=pass>
8612 01:58:10.456178 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_63 RESULT=pass
8614 01:58:10.494820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_63 RESULT=pass>
8615 01:58:10.495141 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_63 RESULT=pass
8617 01:58:10.533587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_62 RESULT=pass>
8618 01:58:10.533896 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_62 RESULT=pass
8620 01:58:10.576605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_62 RESULT=fail>
8621 01:58:10.576929 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_62 RESULT=fail
8623 01:58:10.621618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_62 RESULT=pass>
8624 01:58:10.621965 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_62 RESULT=pass
8626 01:58:10.664447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_62 RESULT=pass>
8627 01:58:10.664772 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_62 RESULT=pass
8629 01:58:10.708868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_62 RESULT=pass>
8630 01:58:10.709185 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_62 RESULT=pass
8632 01:58:10.752246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_62 RESULT=pass>
8633 01:58:10.752592 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_62 RESULT=pass
8635 01:58:10.799762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_62 RESULT=pass>
8636 01:58:10.800110 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_62 RESULT=pass
8638 01:58:10.838783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_61 RESULT=pass>
8639 01:58:10.839120 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_61 RESULT=pass
8641 01:58:10.872368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_61 RESULT=fail>
8642 01:58:10.872696 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_61 RESULT=fail
8644 01:58:10.915975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_61 RESULT=pass>
8645 01:58:10.916344 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_61 RESULT=pass
8647 01:58:10.960182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_61 RESULT=pass>
8648 01:58:10.960526 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_61 RESULT=pass
8650 01:58:11.000827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_61 RESULT=pass>
8651 01:58:11.001149 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_61 RESULT=pass
8653 01:58:11.040735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_61 RESULT=pass>
8654 01:58:11.041054 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_61 RESULT=pass
8656 01:58:11.080132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_61 RESULT=pass>
8657 01:58:11.080488 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_61 RESULT=pass
8659 01:58:11.124101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_60 RESULT=pass>
8660 01:58:11.124415 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_60 RESULT=pass
8662 01:58:11.157255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_60 RESULT=fail>
8663 01:58:11.157607 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_60 RESULT=fail
8665 01:58:11.200696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_60 RESULT=pass>
8666 01:58:11.201021 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_60 RESULT=pass
8668 01:58:11.239720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_60 RESULT=pass>
8669 01:58:11.240137 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_60 RESULT=pass
8671 01:58:11.277542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_60 RESULT=pass>
8672 01:58:11.277875 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_60 RESULT=pass
8674 01:58:11.318596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_60 RESULT=pass>
8675 01:58:11.318922 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_60 RESULT=pass
8677 01:58:11.357505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_60 RESULT=pass>
8678 01:58:11.357825 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_60 RESULT=pass
8680 01:58:11.395179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_59 RESULT=pass>
8681 01:58:11.395525 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_59 RESULT=pass
8683 01:58:11.434950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_59 RESULT=fail>
8684 01:58:11.435292 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_59 RESULT=fail
8686 01:58:11.489551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_59 RESULT=pass>
8687 01:58:11.489902 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_59 RESULT=pass
8689 01:58:11.527138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_59 RESULT=pass>
8690 01:58:11.527463 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_59 RESULT=pass
8692 01:58:11.565471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_59 RESULT=pass>
8693 01:58:11.565820 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_59 RESULT=pass
8695 01:58:11.605542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_59 RESULT=pass>
8696 01:58:11.605889 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_59 RESULT=pass
8698 01:58:11.649519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_59 RESULT=pass>
8699 01:58:11.649870 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_59 RESULT=pass
8701 01:58:11.695205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_58 RESULT=pass>
8702 01:58:11.695559 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_58 RESULT=pass
8704 01:58:11.733193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_58 RESULT=fail>
8705 01:58:11.733571 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_58 RESULT=fail
8707 01:58:11.773211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_58 RESULT=pass>
8708 01:58:11.773576 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_58 RESULT=pass
8710 01:58:11.810180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_58 RESULT=pass>
8711 01:58:11.810499 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_58 RESULT=pass
8713 01:58:11.849245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_58 RESULT=pass>
8714 01:58:11.849621 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_58 RESULT=pass
8716 01:58:11.891692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_58 RESULT=pass>
8717 01:58:11.892013 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_58 RESULT=pass
8719 01:58:11.932941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_58 RESULT=pass>
8720 01:58:11.933301 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_58 RESULT=pass
8722 01:58:11.972607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_57 RESULT=pass>
8723 01:58:11.972931 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_57 RESULT=pass
8725 01:58:12.006758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_57 RESULT=fail>
8726 01:58:12.007156 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_57 RESULT=fail
8728 01:58:12.049017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_57 RESULT=pass>
8729 01:58:12.049409 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_57 RESULT=pass
8731 01:58:12.086598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_57 RESULT=pass>
8732 01:58:12.086916 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_57 RESULT=pass
8734 01:58:12.123482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_57 RESULT=pass>
8735 01:58:12.123818 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_57 RESULT=pass
8737 01:58:12.157601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_57 RESULT=pass>
8738 01:58:12.157919 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_57 RESULT=pass
8740 01:58:12.192211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_57 RESULT=pass>
8741 01:58:12.192521 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_57 RESULT=pass
8743 01:58:12.227425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_56 RESULT=pass>
8744 01:58:12.227749 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_56 RESULT=pass
8746 01:58:12.261970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_56 RESULT=fail>
8747 01:58:12.262341 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_56 RESULT=fail
8749 01:58:12.301936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_56 RESULT=pass>
8750 01:58:12.302257 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_56 RESULT=pass
8752 01:58:12.338496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_56 RESULT=pass>
8753 01:58:12.338824 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_56 RESULT=pass
8755 01:58:12.379571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_56 RESULT=pass>
8756 01:58:12.379938 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_56 RESULT=pass
8758 01:58:12.417553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_56 RESULT=pass>
8759 01:58:12.417872 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_56 RESULT=pass
8761 01:58:12.454778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_56 RESULT=pass>
8762 01:58:12.455097 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_56 RESULT=pass
8764 01:58:12.491941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_55 RESULT=pass>
8765 01:58:12.492256 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_55 RESULT=pass
8767 01:58:12.527734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_55 RESULT=fail>
8768 01:58:12.528058 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_55 RESULT=fail
8770 01:58:12.576526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_55 RESULT=pass>
8771 01:58:12.576862 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_55 RESULT=pass
8773 01:58:12.616572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_55 RESULT=pass>
8774 01:58:12.616894 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_55 RESULT=pass
8776 01:58:12.655833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_55 RESULT=pass>
8777 01:58:12.656189 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_55 RESULT=pass
8779 01:58:12.697711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_55 RESULT=pass>
8780 01:58:12.698042 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_55 RESULT=pass
8782 01:58:12.739791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_55 RESULT=pass>
8783 01:58:12.740116 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_55 RESULT=pass
8785 01:58:12.779868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_54 RESULT=pass>
8786 01:58:12.780211 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_54 RESULT=pass
8788 01:58:12.820771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_54 RESULT=fail>
8789 01:58:12.821096 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_54 RESULT=fail
8791 01:58:12.864782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_54 RESULT=pass>
8792 01:58:12.865100 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_54 RESULT=pass
8794 01:58:12.903472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_54 RESULT=pass>
8795 01:58:12.903804 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_54 RESULT=pass
8797 01:58:12.954877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_54 RESULT=pass>
8798 01:58:12.955224 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_54 RESULT=pass
8800 01:58:12.994006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_54 RESULT=pass>
8801 01:58:12.994367 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_54 RESULT=pass
8803 01:58:13.034457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_54 RESULT=pass>
8804 01:58:13.034774 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_54 RESULT=pass
8806 01:58:13.077619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_53 RESULT=pass>
8807 01:58:13.077967 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_53 RESULT=pass
8809 01:58:13.113303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_53 RESULT=fail>
8810 01:58:13.113625 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_53 RESULT=fail
8812 01:58:13.162811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_53 RESULT=pass>
8813 01:58:13.163140 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_53 RESULT=pass
8815 01:58:13.202237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_53 RESULT=pass>
8816 01:58:13.202570 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_53 RESULT=pass
8818 01:58:13.242933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_53 RESULT=pass>
8819 01:58:13.243253 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_53 RESULT=pass
8821 01:58:13.282748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_53 RESULT=pass>
8822 01:58:13.283118 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_53 RESULT=pass
8824 01:58:13.325299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_53 RESULT=pass>
8825 01:58:13.325618 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_53 RESULT=pass
8827 01:58:13.372642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_52 RESULT=pass>
8828 01:58:13.373081 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_52 RESULT=pass
8830 01:58:13.407453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_52 RESULT=fail>
8831 01:58:13.407920 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_52 RESULT=fail
8833 01:58:13.448506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_52 RESULT=pass>
8834 01:58:13.448873 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_52 RESULT=pass
8836 01:58:13.487355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_52 RESULT=pass>
8837 01:58:13.487724 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_52 RESULT=pass
8839 01:58:13.529117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_52 RESULT=pass>
8840 01:58:13.529491 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_52 RESULT=pass
8842 01:58:13.569846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_52 RESULT=pass>
8843 01:58:13.570170 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_52 RESULT=pass
8845 01:58:13.611889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_52 RESULT=pass>
8846 01:58:13.612217 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_52 RESULT=pass
8848 01:58:13.651241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_51 RESULT=pass>
8849 01:58:13.651579 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_51 RESULT=pass
8851 01:58:13.697184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_51 RESULT=fail>
8852 01:58:13.697558 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_51 RESULT=fail
8854 01:58:13.743292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_51 RESULT=pass>
8855 01:58:13.743626 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_51 RESULT=pass
8857 01:58:13.788173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_51 RESULT=pass>
8858 01:58:13.788500 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_51 RESULT=pass
8860 01:58:13.829147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_51 RESULT=pass>
8861 01:58:13.829503 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_51 RESULT=pass
8863 01:58:13.873635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_51 RESULT=pass>
8864 01:58:13.873970 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_51 RESULT=pass
8866 01:58:13.914681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_51 RESULT=pass>
8867 01:58:13.915007 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_51 RESULT=pass
8869 01:58:13.955864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_50 RESULT=pass>
8870 01:58:13.956187 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_50 RESULT=pass
8872 01:58:13.993128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_50 RESULT=fail>
8873 01:58:13.993524 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_50 RESULT=fail
8875 01:58:14.036812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_50 RESULT=pass>
8876 01:58:14.037160 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_50 RESULT=pass
8878 01:58:14.078308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_50 RESULT=pass>
8879 01:58:14.078627 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_50 RESULT=pass
8881 01:58:14.119050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_50 RESULT=pass>
8882 01:58:14.119375 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_50 RESULT=pass
8884 01:58:14.160375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_50 RESULT=pass>
8885 01:58:14.160710 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_50 RESULT=pass
8887 01:58:14.200240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_50 RESULT=pass>
8888 01:58:14.200571 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_50 RESULT=pass
8890 01:58:14.243910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_49 RESULT=pass>
8891 01:58:14.244244 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_49 RESULT=pass
8893 01:58:14.282869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_49 RESULT=fail>
8894 01:58:14.283190 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_49 RESULT=fail
8896 01:58:14.328101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_49 RESULT=pass>
8897 01:58:14.328451 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_49 RESULT=pass
8899 01:58:14.370938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_49 RESULT=pass>
8900 01:58:14.371269 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_49 RESULT=pass
8902 01:58:14.414037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_49 RESULT=pass>
8903 01:58:14.414377 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_49 RESULT=pass
8905 01:58:14.459370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_49 RESULT=pass>
8906 01:58:14.459677 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_49 RESULT=pass
8908 01:58:14.503011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_49 RESULT=pass>
8909 01:58:14.503390 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_49 RESULT=pass
8911 01:58:14.547048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_48 RESULT=pass>
8912 01:58:14.547424 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_48 RESULT=pass
8914 01:58:14.588768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_48 RESULT=fail>
8915 01:58:14.589121 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_48 RESULT=fail
8917 01:58:14.637563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_48 RESULT=pass>
8918 01:58:14.637883 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_48 RESULT=pass
8920 01:58:14.677145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_48 RESULT=pass>
8921 01:58:14.677513 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_48 RESULT=pass
8923 01:58:14.721417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_48 RESULT=pass>
8924 01:58:14.721737 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_48 RESULT=pass
8926 01:58:14.763532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_48 RESULT=pass>
8927 01:58:14.763880 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_48 RESULT=pass
8929 01:58:14.811386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_48 RESULT=pass>
8930 01:58:14.811709 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_48 RESULT=pass
8932 01:58:14.853031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_47 RESULT=pass>
8933 01:58:14.853379 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_47 RESULT=pass
8935 01:58:14.901080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_47 RESULT=fail>
8936 01:58:14.901399 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_47 RESULT=fail
8938 01:58:14.945657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_47 RESULT=pass>
8939 01:58:14.946017 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_47 RESULT=pass
8941 01:58:14.987237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_47 RESULT=pass>
8942 01:58:14.987586 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_47 RESULT=pass
8944 01:58:15.044233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_47 RESULT=pass>
8945 01:58:15.044581 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_47 RESULT=pass
8947 01:58:15.098990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_47 RESULT=pass>
8948 01:58:15.099338 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_47 RESULT=pass
8950 01:58:15.140914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_47 RESULT=pass>
8951 01:58:15.141302 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_47 RESULT=pass
8953 01:58:15.182770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_46 RESULT=pass>
8954 01:58:15.183093 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_46 RESULT=pass
8956 01:58:15.223556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_46 RESULT=fail>
8957 01:58:15.223904 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_46 RESULT=fail
8959 01:58:15.279158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_46 RESULT=pass>
8960 01:58:15.279483 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_46 RESULT=pass
8962 01:58:15.324114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_46 RESULT=pass>
8963 01:58:15.324457 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_46 RESULT=pass
8965 01:58:15.365153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_46 RESULT=pass>
8966 01:58:15.365507 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_46 RESULT=pass
8968 01:58:15.406646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_46 RESULT=pass>
8969 01:58:15.406970 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_46 RESULT=pass
8971 01:58:15.458632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_46 RESULT=pass>
8972 01:58:15.458952 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_46 RESULT=pass
8974 01:58:15.509203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_45 RESULT=pass>
8975 01:58:15.509559 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_45 RESULT=pass
8977 01:58:15.555901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_45 RESULT=fail>
8978 01:58:15.556252 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_45 RESULT=fail
8980 01:58:15.605634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_45 RESULT=pass>
8981 01:58:15.605957 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_45 RESULT=pass
8983 01:58:15.645874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_45 RESULT=pass>
8984 01:58:15.646228 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_45 RESULT=pass
8986 01:58:15.688492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_45 RESULT=pass>
8987 01:58:15.688853 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_45 RESULT=pass
8989 01:58:15.729425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_45 RESULT=pass>
8990 01:58:15.729754 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_45 RESULT=pass
8992 01:58:15.768612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_45 RESULT=pass>
8993 01:58:15.768939 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_45 RESULT=pass
8995 01:58:15.814178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_44 RESULT=pass>
8996 01:58:15.814505 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_44 RESULT=pass
8998 01:58:15.850508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_44 RESULT=fail>
8999 01:58:15.850877 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_44 RESULT=fail
9001 01:58:15.892381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_44 RESULT=pass>
9002 01:58:15.892748 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_44 RESULT=pass
9004 01:58:15.934765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_44 RESULT=pass>
9005 01:58:15.935129 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_44 RESULT=pass
9007 01:58:15.976612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_44 RESULT=pass>
9008 01:58:15.976981 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_44 RESULT=pass
9010 01:58:16.016656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_44 RESULT=pass>
9011 01:58:16.017023 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_44 RESULT=pass
9013 01:58:16.060422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_44 RESULT=pass>
9014 01:58:16.060785 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_44 RESULT=pass
9016 01:58:16.105758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_43 RESULT=pass>
9017 01:58:16.106135 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_43 RESULT=pass
9019 01:58:16.145219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_43 RESULT=fail>
9020 01:58:16.145614 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_43 RESULT=fail
9022 01:58:16.192114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_43 RESULT=pass>
9023 01:58:16.192450 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_43 RESULT=pass
9025 01:58:16.235912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_43 RESULT=pass>
9026 01:58:16.236219 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_43 RESULT=pass
9028 01:58:16.275824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_43 RESULT=pass>
9029 01:58:16.276158 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_43 RESULT=pass
9031 01:58:16.314209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_43 RESULT=pass>
9032 01:58:16.314517 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_43 RESULT=pass
9034 01:58:16.354183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_43 RESULT=pass>
9035 01:58:16.354561 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_43 RESULT=pass
9037 01:58:16.395893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_42 RESULT=pass>
9038 01:58:16.396212 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_42 RESULT=pass
9040 01:58:16.437337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_42 RESULT=fail>
9041 01:58:16.437644 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_42 RESULT=fail
9043 01:58:16.487403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_42 RESULT=pass>
9044 01:58:16.487723 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_42 RESULT=pass
9046 01:58:16.528184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_42 RESULT=pass>
9047 01:58:16.528496 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_42 RESULT=pass
9049 01:58:16.568846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_42 RESULT=pass>
9050 01:58:16.569162 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_42 RESULT=pass
9052 01:58:16.608425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_42 RESULT=pass>
9053 01:58:16.608759 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_42 RESULT=pass
9055 01:58:16.648554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_42 RESULT=pass>
9056 01:58:16.648868 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_42 RESULT=pass
9058 01:58:16.687397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_41 RESULT=pass>
9059 01:58:16.687717 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_41 RESULT=pass
9061 01:58:16.722007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_41 RESULT=fail>
9062 01:58:16.722329 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_41 RESULT=fail
9064 01:58:16.763476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_41 RESULT=pass>
9065 01:58:16.763799 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_41 RESULT=pass
9067 01:58:16.799287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_41 RESULT=pass>
9068 01:58:16.799557 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_41 RESULT=pass
9070 01:58:16.843140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_41 RESULT=pass>
9071 01:58:16.843417 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_41 RESULT=pass
9073 01:58:16.886203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_41 RESULT=pass>
9074 01:58:16.886487 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_41 RESULT=pass
9076 01:58:16.927983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_41 RESULT=pass>
9077 01:58:16.928287 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_41 RESULT=pass
9079 01:58:16.968410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_40 RESULT=pass>
9080 01:58:16.968713 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_40 RESULT=pass
9082 01:58:17.013813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_40 RESULT=fail>
9083 01:58:17.014105 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_40 RESULT=fail
9085 01:58:17.069102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_40 RESULT=pass>
9086 01:58:17.069441 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_40 RESULT=pass
9088 01:58:17.126059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_40 RESULT=pass>
9089 01:58:17.126371 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_40 RESULT=pass
9091 01:58:17.179362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_40 RESULT=pass>
9092 01:58:17.179659 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_40 RESULT=pass
9094 01:58:17.229872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_40 RESULT=pass>
9095 01:58:17.230167 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_40 RESULT=pass
9097 01:58:17.288085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_40 RESULT=pass>
9098 01:58:17.288389 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_40 RESULT=pass
9100 01:58:17.345689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_39 RESULT=pass>
9101 01:58:17.345973 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_39 RESULT=pass
9103 01:58:17.395316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_39 RESULT=fail>
9104 01:58:17.395609 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_39 RESULT=fail
9106 01:58:17.454634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_39 RESULT=pass>
9107 01:58:17.454935 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_39 RESULT=pass
9109 01:58:17.510228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_39 RESULT=pass>
9110 01:58:17.510514 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_39 RESULT=pass
9112 01:58:17.563883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_39 RESULT=pass>
9113 01:58:17.564205 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_39 RESULT=pass
9115 01:58:17.623259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_39 RESULT=pass>
9116 01:58:17.623539 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_39 RESULT=pass
9118 01:58:17.680594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_39 RESULT=pass>
9119 01:58:17.680893 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_39 RESULT=pass
9121 01:58:17.727842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_38 RESULT=pass>
9122 01:58:17.728127 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_38 RESULT=pass
9124 01:58:17.778336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_38 RESULT=fail>
9125 01:58:17.778629 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_38 RESULT=fail
9127 01:58:17.825218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_38 RESULT=pass>
9128 01:58:17.825527 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_38 RESULT=pass
9130 01:58:17.871056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_38 RESULT=pass>
9131 01:58:17.871327 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_38 RESULT=pass
9133 01:58:17.915885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_38 RESULT=pass>
9134 01:58:17.916143 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_38 RESULT=pass
9136 01:58:17.954760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_38 RESULT=pass>
9137 01:58:17.955055 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_38 RESULT=pass
9139 01:58:17.995261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_38 RESULT=pass>
9140 01:58:17.995552 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_38 RESULT=pass
9142 01:58:18.048150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_37 RESULT=pass>
9143 01:58:18.048407 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_37 RESULT=pass
9145 01:58:18.101246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_37 RESULT=fail>
9146 01:58:18.101554 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_37 RESULT=fail
9148 01:58:18.150798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_37 RESULT=pass>
9149 01:58:18.151054 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_37 RESULT=pass
9151 01:58:18.195923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_37 RESULT=pass>
9152 01:58:18.196190 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_37 RESULT=pass
9154 01:58:18.250548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_37 RESULT=pass>
9155 01:58:18.250834 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_37 RESULT=pass
9157 01:58:18.289811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_37 RESULT=pass>
9158 01:58:18.290095 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_37 RESULT=pass
9160 01:58:18.326492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_37 RESULT=pass>
9161 01:58:18.326759 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_37 RESULT=pass
9163 01:58:18.366091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_36 RESULT=pass>
9164 01:58:18.366358 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_36 RESULT=pass
9166 01:58:18.404075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_36 RESULT=fail>
9167 01:58:18.404336 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_36 RESULT=fail
9169 01:58:18.444929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_36 RESULT=pass>
9170 01:58:18.445200 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_36 RESULT=pass
9172 01:58:18.489197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_36 RESULT=pass>
9173 01:58:18.489503 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_36 RESULT=pass
9175 01:58:18.529929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_36 RESULT=pass>
9176 01:58:18.530186 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_36 RESULT=pass
9178 01:58:18.568759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_36 RESULT=pass>
9179 01:58:18.569025 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_36 RESULT=pass
9181 01:58:18.613140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_36 RESULT=pass>
9182 01:58:18.613401 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_36 RESULT=pass
9184 01:58:18.656296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_35 RESULT=pass>
9185 01:58:18.656559 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_35 RESULT=pass
9187 01:58:18.692896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_35 RESULT=fail>
9188 01:58:18.693158 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_35 RESULT=fail
9190 01:58:18.739545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_35 RESULT=pass>
9191 01:58:18.739804 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_35 RESULT=pass
9193 01:58:18.778012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_35 RESULT=pass>
9194 01:58:18.778274 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_35 RESULT=pass
9196 01:58:18.818682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_35 RESULT=pass>
9197 01:58:18.818942 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_35 RESULT=pass
9199 01:58:18.858421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_35 RESULT=pass>
9200 01:58:18.858681 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_35 RESULT=pass
9202 01:58:18.898380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_35 RESULT=pass>
9203 01:58:18.898647 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_35 RESULT=pass
9205 01:58:18.941889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_34 RESULT=pass>
9206 01:58:18.942151 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_34 RESULT=pass
9208 01:58:18.981097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_34 RESULT=fail>
9209 01:58:18.981355 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_34 RESULT=fail
9211 01:58:19.029395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_34 RESULT=pass>
9212 01:58:19.029651 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_34 RESULT=pass
9214 01:58:19.070422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_34 RESULT=pass>
9215 01:58:19.070686 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_34 RESULT=pass
9217 01:58:19.110636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_34 RESULT=pass>
9218 01:58:19.110891 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_34 RESULT=pass
9220 01:58:19.153166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_34 RESULT=pass>
9221 01:58:19.153421 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_34 RESULT=pass
9223 01:58:19.191548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_34 RESULT=pass>
9224 01:58:19.191811 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_34 RESULT=pass
9226 01:58:19.235937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_33 RESULT=pass>
9227 01:58:19.236194 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_33 RESULT=pass
9229 01:58:19.274616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_33 RESULT=fail>
9230 01:58:19.274873 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_33 RESULT=fail
9232 01:58:19.318195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_33 RESULT=pass>
9233 01:58:19.318454 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_33 RESULT=pass
9235 01:58:19.361213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_33 RESULT=pass>
9236 01:58:19.361489 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_33 RESULT=pass
9238 01:58:19.411319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_33 RESULT=pass>
9239 01:58:19.411574 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_33 RESULT=pass
9241 01:58:19.452855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_33 RESULT=pass>
9242 01:58:19.453127 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_33 RESULT=pass
9244 01:58:19.496512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_33 RESULT=pass>
9245 01:58:19.496787 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_33 RESULT=pass
9247 01:58:19.541659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_32 RESULT=pass>
9248 01:58:19.541920 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_32 RESULT=pass
9250 01:58:19.582930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_32 RESULT=fail>
9251 01:58:19.583201 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_32 RESULT=fail
9253 01:58:19.628733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_32 RESULT=pass>
9254 01:58:19.629016 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_32 RESULT=pass
9256 01:58:19.670473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_32 RESULT=pass>
9257 01:58:19.670734 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_32 RESULT=pass
9259 01:58:19.709636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_32 RESULT=pass>
9260 01:58:19.709893 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_32 RESULT=pass
9262 01:58:19.749022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_32 RESULT=pass>
9263 01:58:19.749316 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_32 RESULT=pass
9265 01:58:19.788440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_32 RESULT=pass>
9266 01:58:19.788697 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_32 RESULT=pass
9268 01:58:19.832069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_31 RESULT=pass>
9269 01:58:19.832354 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_31 RESULT=pass
9271 01:58:19.873689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_31 RESULT=fail>
9272 01:58:19.873959 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_31 RESULT=fail
9274 01:58:19.919807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_31 RESULT=pass>
9275 01:58:19.920065 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_31 RESULT=pass
9277 01:58:19.959471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_31 RESULT=pass>
9278 01:58:19.959735 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_31 RESULT=pass
9280 01:58:20.000087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_31 RESULT=pass>
9281 01:58:20.000346 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_31 RESULT=pass
9283 01:58:20.042699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_31 RESULT=pass>
9284 01:58:20.042987 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_31 RESULT=pass
9286 01:58:20.080084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_31 RESULT=pass>
9287 01:58:20.080420 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_31 RESULT=pass
9289 01:58:20.121529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_30 RESULT=pass>
9290 01:58:20.121832 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_30 RESULT=pass
9292 01:58:20.158085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_30 RESULT=fail>
9293 01:58:20.158457 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_30 RESULT=fail
9295 01:58:20.201434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_30 RESULT=pass>
9296 01:58:20.201765 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_30 RESULT=pass
9298 01:58:20.246199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_30 RESULT=pass>
9299 01:58:20.246502 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_30 RESULT=pass
9301 01:58:20.284942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_30 RESULT=pass>
9302 01:58:20.285289 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_30 RESULT=pass
9304 01:58:20.325146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_30 RESULT=pass>
9305 01:58:20.325462 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_30 RESULT=pass
9307 01:58:20.362781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_30 RESULT=pass>
9308 01:58:20.363087 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_30 RESULT=pass
9310 01:58:20.401330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_29 RESULT=pass>
9311 01:58:20.401647 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_29 RESULT=pass
9313 01:58:20.439406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_29 RESULT=pass>
9314 01:58:20.439688 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_29 RESULT=pass
9316 01:58:20.482480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_29 RESULT=pass>
9317 01:58:20.482810 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_29 RESULT=pass
9319 01:58:20.529997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_29 RESULT=pass>
9320 01:58:20.530294 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_29 RESULT=pass
9322 01:58:20.566181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_29 RESULT=pass>
9323 01:58:20.566457 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_29 RESULT=pass
9325 01:58:20.606474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_29 RESULT=pass>
9326 01:58:20.606738 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_29 RESULT=pass
9328 01:58:20.646641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_29 RESULT=pass>
9329 01:58:20.646966 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_29 RESULT=pass
9331 01:58:20.681046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_28 RESULT=pass>
9332 01:58:20.681301 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_28 RESULT=pass
9334 01:58:20.714270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_28 RESULT=pass>
9335 01:58:20.714568 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_28 RESULT=pass
9337 01:58:20.753504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_28 RESULT=pass>
9338 01:58:20.753783 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_28 RESULT=pass
9340 01:58:20.789612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_28 RESULT=pass>
9341 01:58:20.789901 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_28 RESULT=pass
9343 01:58:20.828316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_28 RESULT=pass>
9344 01:58:20.828594 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_28 RESULT=pass
9346 01:58:20.865455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_28 RESULT=pass>
9347 01:58:20.865725 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_28 RESULT=pass
9349 01:58:20.913272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_28 RESULT=pass>
9350 01:58:20.913566 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_28 RESULT=pass
9352 01:58:20.957864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_27 RESULT=pass>
9353 01:58:20.958183 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_27 RESULT=pass
9355 01:58:20.995627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_27 RESULT=pass>
9356 01:58:20.995954 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_27 RESULT=pass
9358 01:58:21.037170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_27 RESULT=pass>
9359 01:58:21.037502 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_27 RESULT=pass
9361 01:58:21.076329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_27 RESULT=pass>
9362 01:58:21.076603 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_27 RESULT=pass
9364 01:58:21.117978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_27 RESULT=pass>
9365 01:58:21.118249 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_27 RESULT=pass
9367 01:58:21.157901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_27 RESULT=pass>
9368 01:58:21.158175 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_27 RESULT=pass
9370 01:58:21.198668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_27 RESULT=pass>
9371 01:58:21.198934 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_27 RESULT=pass
9373 01:58:21.236635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_26 RESULT=pass>
9374 01:58:21.236902 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_26 RESULT=pass
9376 01:58:21.273414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_26 RESULT=pass>
9377 01:58:21.273681 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_26 RESULT=pass
9379 01:58:21.315061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_26 RESULT=pass>
9380 01:58:21.315381 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_26 RESULT=pass
9382 01:58:21.353932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_26 RESULT=pass>
9383 01:58:21.354194 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_26 RESULT=pass
9385 01:58:21.398841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_26 RESULT=pass>
9386 01:58:21.399156 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_26 RESULT=pass
9388 01:58:21.441016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_26 RESULT=pass>
9389 01:58:21.441318 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_26 RESULT=pass
9391 01:58:21.478119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_26 RESULT=pass>
9392 01:58:21.478434 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_26 RESULT=pass
9394 01:58:21.517234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_25 RESULT=pass>
9395 01:58:21.517567 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_25 RESULT=pass
9397 01:58:21.551360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_25 RESULT=pass>
9398 01:58:21.551658 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_25 RESULT=pass
9400 01:58:21.592436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_25 RESULT=pass>
9401 01:58:21.592750 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_25 RESULT=pass
9403 01:58:21.632833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_25 RESULT=pass>
9404 01:58:21.633144 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_25 RESULT=pass
9406 01:58:21.673243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_25 RESULT=pass>
9407 01:58:21.673588 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_25 RESULT=pass
9409 01:58:21.714003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_25 RESULT=pass>
9410 01:58:21.714306 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_25 RESULT=pass
9412 01:58:21.756738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_25 RESULT=pass>
9413 01:58:21.757061 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_25 RESULT=pass
9415 01:58:21.800834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_24 RESULT=pass>
9416 01:58:21.801146 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_24 RESULT=pass
9418 01:58:21.834726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_24 RESULT=pass>
9419 01:58:21.835050 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_24 RESULT=pass
9421 01:58:21.879788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_24 RESULT=pass>
9422 01:58:21.880103 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_24 RESULT=pass
9424 01:58:21.918801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_24 RESULT=pass>
9425 01:58:21.919143 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_24 RESULT=pass
9427 01:58:21.963023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_24 RESULT=pass>
9428 01:58:21.963381 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_24 RESULT=pass
9430 01:58:22.007152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_24 RESULT=pass>
9431 01:58:22.007462 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_24 RESULT=pass
9433 01:58:22.047809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_24 RESULT=pass>
9434 01:58:22.048118 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_24 RESULT=pass
9436 01:58:22.089696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_23 RESULT=pass>
9437 01:58:22.090020 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_23 RESULT=pass
9439 01:58:22.128456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_23 RESULT=pass>
9440 01:58:22.128768 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_23 RESULT=pass
9442 01:58:22.175196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_23 RESULT=pass>
9443 01:58:22.175510 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_23 RESULT=pass
9445 01:58:22.214171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_23 RESULT=pass>
9446 01:58:22.214464 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_23 RESULT=pass
9448 01:58:22.254159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_23 RESULT=pass>
9449 01:58:22.254457 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_23 RESULT=pass
9451 01:58:22.295833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_23 RESULT=pass>
9452 01:58:22.296139 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_23 RESULT=pass
9454 01:58:22.339437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_23 RESULT=pass>
9455 01:58:22.339775 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_23 RESULT=pass
9457 01:58:22.378333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_22 RESULT=pass>
9458 01:58:22.378636 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_22 RESULT=pass
9460 01:58:22.416210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_22 RESULT=pass>
9461 01:58:22.416509 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_22 RESULT=pass
9463 01:58:22.458785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_22 RESULT=pass>
9464 01:58:22.459146 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_22 RESULT=pass
9466 01:58:22.493093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_22 RESULT=pass>
9467 01:58:22.493411 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_22 RESULT=pass
9469 01:58:22.526794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_22 RESULT=pass>
9470 01:58:22.527120 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_22 RESULT=pass
9472 01:58:22.564964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_22 RESULT=pass>
9473 01:58:22.565274 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_22 RESULT=pass
9475 01:58:22.600455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_22 RESULT=pass>
9476 01:58:22.600749 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_22 RESULT=pass
9478 01:58:22.638933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_21 RESULT=pass>
9479 01:58:22.639240 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_21 RESULT=pass
9481 01:58:22.679089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_21 RESULT=fail>
9482 01:58:22.679408 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_21 RESULT=fail
9484 01:58:22.720005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_21 RESULT=pass>
9485 01:58:22.720335 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_21 RESULT=pass
9487 01:58:22.759543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_21 RESULT=pass>
9488 01:58:22.759849 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_21 RESULT=pass
9490 01:58:22.803240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_21 RESULT=pass>
9491 01:58:22.803531 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_21 RESULT=pass
9493 01:58:22.840560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_21 RESULT=pass>
9494 01:58:22.840859 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_21 RESULT=pass
9496 01:58:22.878322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_21 RESULT=pass>
9497 01:58:22.878641 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_21 RESULT=pass
9499 01:58:22.915866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_20 RESULT=pass>
9500 01:58:22.916167 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_20 RESULT=pass
9502 01:58:22.954169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_20 RESULT=fail>
9503 01:58:22.954468 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_20 RESULT=fail
9505 01:58:22.996624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_20 RESULT=pass>
9506 01:58:22.996941 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_20 RESULT=pass
9508 01:58:23.037966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_20 RESULT=pass>
9509 01:58:23.038284 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_20 RESULT=pass
9511 01:58:23.075126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_20 RESULT=pass>
9512 01:58:23.075442 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_20 RESULT=pass
9514 01:58:23.112749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_20 RESULT=pass>
9515 01:58:23.113062 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_20 RESULT=pass
9517 01:58:23.149567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_20 RESULT=pass>
9518 01:58:23.149874 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_20 RESULT=pass
9520 01:58:23.186758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_19 RESULT=pass>
9521 01:58:23.187073 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_19 RESULT=pass
9523 01:58:23.222874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_19 RESULT=fail>
9524 01:58:23.223176 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_19 RESULT=fail
9526 01:58:23.263834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_19 RESULT=pass>
9527 01:58:23.264162 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_19 RESULT=pass
9529 01:58:23.301115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_19 RESULT=pass>
9530 01:58:23.301515 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_19 RESULT=pass
9532 01:58:23.342555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_19 RESULT=pass>
9533 01:58:23.342866 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_19 RESULT=pass
9535 01:58:23.384450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_19 RESULT=pass>
9536 01:58:23.384787 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_19 RESULT=pass
9538 01:58:23.428518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_19 RESULT=pass>
9539 01:58:23.428832 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_19 RESULT=pass
9541 01:58:23.471973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_18 RESULT=pass>
9542 01:58:23.472282 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_18 RESULT=pass
9544 01:58:23.509280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_18 RESULT=fail>
9545 01:58:23.509649 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_18 RESULT=fail
9547 01:58:23.548516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_18 RESULT=pass>
9548 01:58:23.548819 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_18 RESULT=pass
9550 01:58:23.588806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_18 RESULT=pass>
9551 01:58:23.589117 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_18 RESULT=pass
9553 01:58:23.627105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_18 RESULT=pass>
9554 01:58:23.627395 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_18 RESULT=pass
9556 01:58:23.665462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_18 RESULT=pass>
9557 01:58:23.665863 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_18 RESULT=pass
9559 01:58:23.708167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_18 RESULT=pass>
9560 01:58:23.708567 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_18 RESULT=pass
9562 01:58:23.749266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_17 RESULT=pass>
9563 01:58:23.749600 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_17 RESULT=pass
9565 01:58:23.782382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_17 RESULT=fail>
9566 01:58:23.782722 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_17 RESULT=fail
9568 01:58:23.821801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_17 RESULT=pass>
9569 01:58:23.822121 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_17 RESULT=pass
9571 01:58:23.856770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_17 RESULT=pass>
9572 01:58:23.857092 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_17 RESULT=pass
9574 01:58:23.893902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_17 RESULT=pass>
9575 01:58:23.894233 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_17 RESULT=pass
9577 01:58:23.937954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_17 RESULT=pass>
9578 01:58:23.938285 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_17 RESULT=pass
9580 01:58:23.978160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_17 RESULT=pass>
9581 01:58:23.978482 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_17 RESULT=pass
9583 01:58:24.017873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_16 RESULT=pass>
9584 01:58:24.018198 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_16 RESULT=pass
9586 01:58:24.054700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_16 RESULT=fail>
9587 01:58:24.055033 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_16 RESULT=fail
9589 01:58:24.096929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_16 RESULT=pass>
9590 01:58:24.097272 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_16 RESULT=pass
9592 01:58:24.136567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_16 RESULT=pass>
9593 01:58:24.136883 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_16 RESULT=pass
9595 01:58:24.249738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_16 RESULT=pass>
9596 01:58:24.250434 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_16 RESULT=pass
9598 01:58:24.294361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_16 RESULT=pass>
9599 01:58:24.294688 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_16 RESULT=pass
9601 01:58:24.336070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_16 RESULT=pass>
9602 01:58:24.336382 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_16 RESULT=pass
9604 01:58:24.377396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_15 RESULT=pass>
9605 01:58:24.377722 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_15 RESULT=pass
9607 01:58:24.412835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_15 RESULT=fail>
9608 01:58:24.413133 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_15 RESULT=fail
9610 01:58:24.456204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_15 RESULT=pass>
9611 01:58:24.456541 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_15 RESULT=pass
9613 01:58:24.497171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_15 RESULT=pass>
9614 01:58:24.497529 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_15 RESULT=pass
9616 01:58:24.539095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_15 RESULT=pass>
9617 01:58:24.539415 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_15 RESULT=pass
9619 01:58:24.578226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_15 RESULT=pass>
9620 01:58:24.578552 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_15 RESULT=pass
9622 01:58:24.620023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_15 RESULT=pass>
9623 01:58:24.620350 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_15 RESULT=pass
9625 01:58:24.663970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_14 RESULT=pass>
9626 01:58:24.664304 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_14 RESULT=pass
9628 01:58:24.700682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_14 RESULT=fail>
9629 01:58:24.701001 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_14 RESULT=fail
9631 01:58:24.741498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_14 RESULT=pass>
9632 01:58:24.741816 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_14 RESULT=pass
9634 01:58:24.780875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_14 RESULT=pass>
9635 01:58:24.781201 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_14 RESULT=pass
9637 01:58:24.822656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_14 RESULT=pass>
9638 01:58:24.822975 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_14 RESULT=pass
9640 01:58:24.862513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_14 RESULT=pass>
9641 01:58:24.862868 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_14 RESULT=pass
9643 01:58:24.901513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_14 RESULT=pass>
9644 01:58:24.901846 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_14 RESULT=pass
9646 01:58:24.939304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_13 RESULT=pass>
9647 01:58:24.939628 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_13 RESULT=pass
9649 01:58:24.980050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_13 RESULT=fail>
9650 01:58:24.980373 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_13 RESULT=fail
9652 01:58:25.025047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_13 RESULT=pass>
9653 01:58:25.025372 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_13 RESULT=pass
9655 01:58:25.062078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_13 RESULT=pass>
9656 01:58:25.062406 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_13 RESULT=pass
9658 01:58:25.105250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_13 RESULT=pass>
9659 01:58:25.105619 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_13 RESULT=pass
9661 01:58:25.149648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_13 RESULT=pass>
9662 01:58:25.150005 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_13 RESULT=pass
9664 01:58:25.192655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_13 RESULT=pass>
9665 01:58:25.192980 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_13 RESULT=pass
9667 01:58:25.237710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_12 RESULT=pass>
9668 01:58:25.238040 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_12 RESULT=pass
9670 01:58:25.275776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_12 RESULT=fail>
9671 01:58:25.276105 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_12 RESULT=fail
9673 01:58:25.319634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_12 RESULT=pass>
9674 01:58:25.319960 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_12 RESULT=pass
9676 01:58:25.356915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_12 RESULT=pass>
9677 01:58:25.357245 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_12 RESULT=pass
9679 01:58:25.398373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_12 RESULT=pass>
9680 01:58:25.398699 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_12 RESULT=pass
9682 01:58:25.438565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_12 RESULT=pass>
9683 01:58:25.438894 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_12 RESULT=pass
9685 01:58:25.477604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_12 RESULT=pass>
9686 01:58:25.477936 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_12 RESULT=pass
9688 01:58:25.518405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_11 RESULT=pass>
9689 01:58:25.518733 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_11 RESULT=pass
9691 01:58:25.552373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_11 RESULT=fail>
9692 01:58:25.552711 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_11 RESULT=fail
9694 01:58:25.591788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_11 RESULT=pass>
9695 01:58:25.592122 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_11 RESULT=pass
9697 01:58:25.629110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_11 RESULT=pass>
9698 01:58:25.629447 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_11 RESULT=pass
9700 01:58:25.670713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_11 RESULT=pass>
9701 01:58:25.671043 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_11 RESULT=pass
9703 01:58:25.710836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_11 RESULT=pass>
9704 01:58:25.711170 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_11 RESULT=pass
9706 01:58:25.750231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_11 RESULT=pass>
9707 01:58:25.750560 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_11 RESULT=pass
9709 01:58:25.790504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_10 RESULT=pass>
9710 01:58:25.790837 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_10 RESULT=pass
9712 01:58:25.833035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_10 RESULT=fail>
9713 01:58:25.833367 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_10 RESULT=fail
9715 01:58:25.881614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_10 RESULT=pass>
9716 01:58:25.881940 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_10 RESULT=pass
9718 01:58:25.921647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_10 RESULT=pass>
9719 01:58:25.921974 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_10 RESULT=pass
9721 01:58:25.964168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_10 RESULT=pass>
9722 01:58:25.964534 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_10 RESULT=pass
9724 01:58:26.006318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_10 RESULT=pass>
9725 01:58:26.006638 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_10 RESULT=pass
9727 01:58:26.050123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_10 RESULT=pass>
9728 01:58:26.050451 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_10 RESULT=pass
9730 01:58:26.091287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_9 RESULT=pass>
9731 01:58:26.091616 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_9 RESULT=pass
9733 01:58:26.130766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_9 RESULT=fail>
9734 01:58:26.131089 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_9 RESULT=fail
9736 01:58:26.176526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_9 RESULT=pass>
9737 01:58:26.176856 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_9 RESULT=pass
9739 01:58:26.220801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_9 RESULT=pass>
9740 01:58:26.221130 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_9 RESULT=pass
9742 01:58:26.259147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_9 RESULT=pass>
9743 01:58:26.259478 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_9 RESULT=pass
9745 01:58:26.298571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_9 RESULT=pass>
9746 01:58:26.298903 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_9 RESULT=pass
9748 01:58:26.339065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_9 RESULT=pass>
9749 01:58:26.339396 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_9 RESULT=pass
9751 01:58:26.378002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_8 RESULT=pass>
9752 01:58:26.378334 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_8 RESULT=pass
9754 01:58:26.415096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_8 RESULT=fail>
9755 01:58:26.415428 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_8 RESULT=fail
9757 01:58:26.461572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_8 RESULT=pass>
9758 01:58:26.461905 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_8 RESULT=pass
9760 01:58:26.505372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_8 RESULT=pass>
9761 01:58:26.505703 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_8 RESULT=pass
9763 01:58:26.548360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_8 RESULT=pass>
9764 01:58:26.548688 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_8 RESULT=pass
9766 01:58:26.589438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_8 RESULT=pass>
9767 01:58:26.589766 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_8 RESULT=pass
9769 01:58:26.630002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_8 RESULT=pass>
9770 01:58:26.630332 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_8 RESULT=pass
9772 01:58:26.672954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_7 RESULT=pass>
9773 01:58:26.673314 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_7 RESULT=pass
9775 01:58:26.711430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_7 RESULT=fail>
9776 01:58:26.711746 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_7 RESULT=fail
9778 01:58:26.755164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_7 RESULT=pass>
9779 01:58:26.755478 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_7 RESULT=pass
9781 01:58:26.794089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_7 RESULT=pass>
9782 01:58:26.794430 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_7 RESULT=pass
9784 01:58:26.834146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_7 RESULT=pass>
9785 01:58:26.834475 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_7 RESULT=pass
9787 01:58:26.874239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_7 RESULT=pass>
9788 01:58:26.874560 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_7 RESULT=pass
9790 01:58:26.919089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_7 RESULT=pass>
9791 01:58:26.919407 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_7 RESULT=pass
9793 01:58:26.955452 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_6 RESULT=pass
9795 01:58:26.958525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_6 RESULT=pass>
9796 01:58:26.993746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_6 RESULT=fail>
9797 01:58:26.994070 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_6 RESULT=fail
9799 01:58:27.040888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_6 RESULT=pass>
9800 01:58:27.041221 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_6 RESULT=pass
9802 01:58:27.080339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_6 RESULT=pass>
9803 01:58:27.080673 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_6 RESULT=pass
9805 01:58:27.123941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_6 RESULT=pass>
9806 01:58:27.124283 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_6 RESULT=pass
9808 01:58:27.166545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_6 RESULT=pass>
9809 01:58:27.166881 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_6 RESULT=pass
9811 01:58:27.207536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_6 RESULT=pass>
9812 01:58:27.207866 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_6 RESULT=pass
9814 01:58:27.245640 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_5 RESULT=pass
9816 01:58:27.248656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_5 RESULT=pass>
9817 01:58:27.287239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_5 RESULT=pass>
9818 01:58:27.287567 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_5 RESULT=pass
9820 01:58:27.336044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_5 RESULT=pass>
9821 01:58:27.336374 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_5 RESULT=pass
9823 01:58:27.377639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_5 RESULT=pass>
9824 01:58:27.377971 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_5 RESULT=pass
9826 01:58:27.422390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_5 RESULT=pass>
9827 01:58:27.422724 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_5 RESULT=pass
9829 01:58:27.466984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_5 RESULT=fail>
9830 01:58:27.467315 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_5 RESULT=fail
9832 01:58:27.511984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_5 RESULT=pass>
9833 01:58:27.512314 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_5 RESULT=pass
9835 01:58:27.552716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_4 RESULT=pass>
9836 01:58:27.553044 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_4 RESULT=pass
9838 01:58:27.590594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_4 RESULT=pass>
9839 01:58:27.590916 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_4 RESULT=pass
9841 01:58:27.634384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_4 RESULT=pass>
9842 01:58:27.634713 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_4 RESULT=pass
9844 01:58:27.674113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_4 RESULT=pass>
9845 01:58:27.674436 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_4 RESULT=pass
9847 01:58:27.715234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_4 RESULT=pass>
9848 01:58:27.715553 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_4 RESULT=pass
9850 01:58:27.753198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_4 RESULT=fail>
9851 01:58:27.753534 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_4 RESULT=fail
9853 01:58:27.792810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_4 RESULT=pass>
9854 01:58:27.793154 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_4 RESULT=pass
9856 01:58:27.834326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_3 RESULT=pass>
9857 01:58:27.834644 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_3 RESULT=pass
9859 01:58:27.871255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_3 RESULT=pass>
9860 01:58:27.871578 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_3 RESULT=pass
9862 01:58:27.912862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_3 RESULT=pass>
9863 01:58:27.913224 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_3 RESULT=pass
9865 01:58:27.953518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_3 RESULT=pass>
9866 01:58:27.953839 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_3 RESULT=pass
9868 01:58:27.992401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_3 RESULT=pass>
9869 01:58:27.992689 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_3 RESULT=pass
9871 01:58:28.034450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_3 RESULT=fail>
9872 01:58:28.034738 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_3 RESULT=fail
9874 01:58:28.074752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_3 RESULT=pass>
9875 01:58:28.075115 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_3 RESULT=pass
9877 01:58:28.111094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_2 RESULT=pass>
9878 01:58:28.111473 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_2 RESULT=pass
9880 01:58:28.145756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_2 RESULT=pass>
9881 01:58:28.146088 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_2 RESULT=pass
9883 01:58:28.193288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_2 RESULT=pass>
9884 01:58:28.193675 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_2 RESULT=pass
9886 01:58:28.237499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_2 RESULT=pass>
9887 01:58:28.237824 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_2 RESULT=pass
9889 01:58:28.284884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_2 RESULT=pass>
9890 01:58:28.285218 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_2 RESULT=pass
9892 01:58:28.321574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_2 RESULT=fail>
9893 01:58:28.321893 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_2 RESULT=fail
9895 01:58:28.365957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_2 RESULT=pass>
9896 01:58:28.366266 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_2 RESULT=pass
9898 01:58:28.411818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_1 RESULT=pass>
9899 01:58:28.412426 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_1 RESULT=pass
9901 01:58:28.459515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_1 RESULT=pass>
9902 01:58:28.460218 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_1 RESULT=pass
9904 01:58:28.506185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_1 RESULT=pass>
9905 01:58:28.506577 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_1 RESULT=pass
9907 01:58:28.543064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_1 RESULT=pass>
9908 01:58:28.543386 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_1 RESULT=pass
9910 01:58:28.584054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_1 RESULT=pass>
9911 01:58:28.584415 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_1 RESULT=pass
9913 01:58:28.625758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_1 RESULT=fail>
9914 01:58:28.626079 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_1 RESULT=fail
9916 01:58:28.665847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_1 RESULT=pass>
9917 01:58:28.666170 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_1 RESULT=pass
9919 01:58:28.709221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_0 RESULT=pass>
9920 01:58:28.709553 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_0 RESULT=pass
9922 01:58:28.752616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_0 RESULT=pass>
9923 01:58:28.752914 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_0 RESULT=pass
9925 01:58:28.803696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_0 RESULT=pass>
9926 01:58:28.804321 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_0 RESULT=pass
9928 01:58:28.854947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_0 RESULT=pass>
9929 01:58:28.855717 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_0 RESULT=pass
9931 01:58:28.905047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_0 RESULT=pass>
9932 01:58:28.905765 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_0 RESULT=pass
9934 01:58:28.956429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_0 RESULT=fail>
9935 01:58:28.957170 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_0 RESULT=fail
9937 01:58:29.010352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_0 RESULT=pass>
9938 01:58:29.011000 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_0 RESULT=pass
9940 01:58:29.050222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
9941 01:58:29.050322 + set +x
9942 01:58:29.050565 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
9944 01:58:29.057168 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 14479169_1.6.2.3.5>
9945 01:58:29.057440 Received signal: <ENDRUN> 1_kselftest-alsa 14479169_1.6.2.3.5
9946 01:58:29.057527 Ending use of test pattern.
9947 01:58:29.057599 Ending test lava.1_kselftest-alsa (14479169_1.6.2.3.5), duration 42.31
9949 01:58:29.060341 <LAVA_TEST_RUNNER EXIT>
9950 01:58:29.060618 ok: lava_test_shell seems to have completed
9951 01:58:29.064850 alsa_mixer-test: pass
alsa_mixer-test_event_missing_0_0: fail
alsa_mixer-test_event_missing_0_1: fail
alsa_mixer-test_event_missing_0_10: pass
alsa_mixer-test_event_missing_0_11: pass
alsa_mixer-test_event_missing_0_12: pass
alsa_mixer-test_event_missing_0_13: pass
alsa_mixer-test_event_missing_0_14: pass
alsa_mixer-test_event_missing_0_15: pass
alsa_mixer-test_event_missing_0_16: pass
alsa_mixer-test_event_missing_0_17: pass
alsa_mixer-test_event_missing_0_18: pass
alsa_mixer-test_event_missing_0_19: pass
alsa_mixer-test_event_missing_0_2: fail
alsa_mixer-test_event_missing_0_20: pass
alsa_mixer-test_event_missing_0_21: pass
alsa_mixer-test_event_missing_0_22: pass
alsa_mixer-test_event_missing_0_23: pass
alsa_mixer-test_event_missing_0_24: pass
alsa_mixer-test_event_missing_0_25: pass
alsa_mixer-test_event_missing_0_26: pass
alsa_mixer-test_event_missing_0_27: pass
alsa_mixer-test_event_missing_0_28: pass
alsa_mixer-test_event_missing_0_29: pass
alsa_mixer-test_event_missing_0_3: fail
alsa_mixer-test_event_missing_0_30: pass
alsa_mixer-test_event_missing_0_31: pass
alsa_mixer-test_event_missing_0_32: pass
alsa_mixer-test_event_missing_0_33: pass
alsa_mixer-test_event_missing_0_34: pass
alsa_mixer-test_event_missing_0_35: pass
alsa_mixer-test_event_missing_0_36: pass
alsa_mixer-test_event_missing_0_37: pass
alsa_mixer-test_event_missing_0_38: pass
alsa_mixer-test_event_missing_0_39: pass
alsa_mixer-test_event_missing_0_4: fail
alsa_mixer-test_event_missing_0_40: pass
alsa_mixer-test_event_missing_0_41: pass
alsa_mixer-test_event_missing_0_42: pass
alsa_mixer-test_event_missing_0_43: pass
alsa_mixer-test_event_missing_0_44: pass
alsa_mixer-test_event_missing_0_45: pass
alsa_mixer-test_event_missing_0_46: pass
alsa_mixer-test_event_missing_0_47: pass
alsa_mixer-test_event_missing_0_48: pass
alsa_mixer-test_event_missing_0_49: pass
alsa_mixer-test_event_missing_0_5: fail
alsa_mixer-test_event_missing_0_50: pass
alsa_mixer-test_event_missing_0_51: pass
alsa_mixer-test_event_missing_0_52: pass
alsa_mixer-test_event_missing_0_53: pass
alsa_mixer-test_event_missing_0_54: pass
alsa_mixer-test_event_missing_0_55: pass
alsa_mixer-test_event_missing_0_56: pass
alsa_mixer-test_event_missing_0_57: pass
alsa_mixer-test_event_missing_0_58: pass
alsa_mixer-test_event_missing_0_59: pass
alsa_mixer-test_event_missing_0_6: pass
alsa_mixer-test_event_missing_0_60: pass
alsa_mixer-test_event_missing_0_61: pass
alsa_mixer-test_event_missing_0_62: pass
alsa_mixer-test_event_missing_0_63: pass
alsa_mixer-test_event_missing_0_64: pass
alsa_mixer-test_event_missing_0_65: pass
alsa_mixer-test_event_missing_0_66: pass
alsa_mixer-test_event_missing_0_67: pass
alsa_mixer-test_event_missing_0_68: pass
alsa_mixer-test_event_missing_0_69: pass
alsa_mixer-test_event_missing_0_7: pass
alsa_mixer-test_event_missing_0_70: pass
alsa_mixer-test_event_missing_0_71: pass
alsa_mixer-test_event_missing_0_72: pass
alsa_mixer-test_event_missing_0_73: pass
alsa_mixer-test_event_missing_0_74: pass
alsa_mixer-test_event_missing_0_75: pass
alsa_mixer-test_event_missing_0_76: pass
alsa_mixer-test_event_missing_0_77: pass
alsa_mixer-test_event_missing_0_78: pass
alsa_mixer-test_event_missing_0_79: pass
alsa_mixer-test_event_missing_0_8: pass
alsa_mixer-test_event_missing_0_80: pass
alsa_mixer-test_event_missing_0_81: fail
alsa_mixer-test_event_missing_0_82: pass
alsa_mixer-test_event_missing_0_83: pass
alsa_mixer-test_event_missing_0_84: pass
alsa_mixer-test_event_missing_0_85: pass
alsa_mixer-test_event_missing_0_86: pass
alsa_mixer-test_event_missing_0_87: pass
alsa_mixer-test_event_missing_0_88: pass
alsa_mixer-test_event_missing_0_89: pass
alsa_mixer-test_event_missing_0_9: pass
alsa_mixer-test_event_missing_0_90: pass
alsa_mixer-test_event_missing_0_91: pass
alsa_mixer-test_event_missing_0_92: pass
alsa_mixer-test_event_missing_0_93: pass
alsa_mixer-test_event_spurious_0_0: pass
alsa_mixer-test_event_spurious_0_1: pass
alsa_mixer-test_event_spurious_0_10: pass
alsa_mixer-test_event_spurious_0_11: pass
alsa_mixer-test_event_spurious_0_12: pass
alsa_mixer-test_event_spurious_0_13: pass
alsa_mixer-test_event_spurious_0_14: pass
alsa_mixer-test_event_spurious_0_15: pass
alsa_mixer-test_event_spurious_0_16: pass
alsa_mixer-test_event_spurious_0_17: pass
alsa_mixer-test_event_spurious_0_18: pass
alsa_mixer-test_event_spurious_0_19: pass
alsa_mixer-test_event_spurious_0_2: pass
alsa_mixer-test_event_spurious_0_20: pass
alsa_mixer-test_event_spurious_0_21: pass
alsa_mixer-test_event_spurious_0_22: pass
alsa_mixer-test_event_spurious_0_23: pass
alsa_mixer-test_event_spurious_0_24: pass
alsa_mixer-test_event_spurious_0_25: pass
alsa_mixer-test_event_spurious_0_26: pass
alsa_mixer-test_event_spurious_0_27: pass
alsa_mixer-test_event_spurious_0_28: pass
alsa_mixer-test_event_spurious_0_29: pass
alsa_mixer-test_event_spurious_0_3: pass
alsa_mixer-test_event_spurious_0_30: pass
alsa_mixer-test_event_spurious_0_31: pass
alsa_mixer-test_event_spurious_0_32: pass
alsa_mixer-test_event_spurious_0_33: pass
alsa_mixer-test_event_spurious_0_34: pass
alsa_mixer-test_event_spurious_0_35: pass
alsa_mixer-test_event_spurious_0_36: pass
alsa_mixer-test_event_spurious_0_37: pass
alsa_mixer-test_event_spurious_0_38: pass
alsa_mixer-test_event_spurious_0_39: pass
alsa_mixer-test_event_spurious_0_4: pass
alsa_mixer-test_event_spurious_0_40: pass
alsa_mixer-test_event_spurious_0_41: pass
alsa_mixer-test_event_spurious_0_42: pass
alsa_mixer-test_event_spurious_0_43: pass
alsa_mixer-test_event_spurious_0_44: pass
alsa_mixer-test_event_spurious_0_45: pass
alsa_mixer-test_event_spurious_0_46: pass
alsa_mixer-test_event_spurious_0_47: pass
alsa_mixer-test_event_spurious_0_48: pass
alsa_mixer-test_event_spurious_0_49: pass
alsa_mixer-test_event_spurious_0_5: pass
alsa_mixer-test_event_spurious_0_50: pass
alsa_mixer-test_event_spurious_0_51: pass
alsa_mixer-test_event_spurious_0_52: pass
alsa_mixer-test_event_spurious_0_53: pass
alsa_mixer-test_event_spurious_0_54: pass
alsa_mixer-test_event_spurious_0_55: pass
alsa_mixer-test_event_spurious_0_56: pass
alsa_mixer-test_event_spurious_0_57: pass
alsa_mixer-test_event_spurious_0_58: pass
alsa_mixer-test_event_spurious_0_59: pass
alsa_mixer-test_event_spurious_0_6: pass
alsa_mixer-test_event_spurious_0_60: pass
alsa_mixer-test_event_spurious_0_61: pass
alsa_mixer-test_event_spurious_0_62: pass
alsa_mixer-test_event_spurious_0_63: pass
alsa_mixer-test_event_spurious_0_64: pass
alsa_mixer-test_event_spurious_0_65: pass
alsa_mixer-test_event_spurious_0_66: pass
alsa_mixer-test_event_spurious_0_67: pass
alsa_mixer-test_event_spurious_0_68: pass
alsa_mixer-test_event_spurious_0_69: pass
alsa_mixer-test_event_spurious_0_7: pass
alsa_mixer-test_event_spurious_0_70: pass
alsa_mixer-test_event_spurious_0_71: pass
alsa_mixer-test_event_spurious_0_72: pass
alsa_mixer-test_event_spurious_0_73: pass
alsa_mixer-test_event_spurious_0_74: pass
alsa_mixer-test_event_spurious_0_75: pass
alsa_mixer-test_event_spurious_0_76: pass
alsa_mixer-test_event_spurious_0_77: pass
alsa_mixer-test_event_spurious_0_78: pass
alsa_mixer-test_event_spurious_0_79: pass
alsa_mixer-test_event_spurious_0_8: pass
alsa_mixer-test_event_spurious_0_80: pass
alsa_mixer-test_event_spurious_0_81: pass
alsa_mixer-test_event_spurious_0_82: pass
alsa_mixer-test_event_spurious_0_83: pass
alsa_mixer-test_event_spurious_0_84: pass
alsa_mixer-test_event_spurious_0_85: pass
alsa_mixer-test_event_spurious_0_86: pass
alsa_mixer-test_event_spurious_0_87: pass
alsa_mixer-test_event_spurious_0_88: fail
alsa_mixer-test_event_spurious_0_89: pass
alsa_mixer-test_event_spurious_0_9: pass
alsa_mixer-test_event_spurious_0_90: pass
alsa_mixer-test_event_spurious_0_91: pass
alsa_mixer-test_event_spurious_0_92: pass
alsa_mixer-test_event_spurious_0_93: pass
alsa_mixer-test_get_value_0_0: pass
alsa_mixer-test_get_value_0_1: pass
alsa_mixer-test_get_value_0_10: pass
alsa_mixer-test_get_value_0_11: pass
alsa_mixer-test_get_value_0_12: pass
alsa_mixer-test_get_value_0_13: pass
alsa_mixer-test_get_value_0_14: pass
alsa_mixer-test_get_value_0_15: pass
alsa_mixer-test_get_value_0_16: pass
alsa_mixer-test_get_value_0_17: pass
alsa_mixer-test_get_value_0_18: pass
alsa_mixer-test_get_value_0_19: pass
alsa_mixer-test_get_value_0_2: pass
alsa_mixer-test_get_value_0_20: pass
alsa_mixer-test_get_value_0_21: pass
alsa_mixer-test_get_value_0_22: pass
alsa_mixer-test_get_value_0_23: pass
alsa_mixer-test_get_value_0_24: pass
alsa_mixer-test_get_value_0_25: pass
alsa_mixer-test_get_value_0_26: pass
alsa_mixer-test_get_value_0_27: pass
alsa_mixer-test_get_value_0_28: pass
alsa_mixer-test_get_value_0_29: pass
alsa_mixer-test_get_value_0_3: pass
alsa_mixer-test_get_value_0_30: pass
alsa_mixer-test_get_value_0_31: pass
alsa_mixer-test_get_value_0_32: pass
alsa_mixer-test_get_value_0_33: pass
alsa_mixer-test_get_value_0_34: pass
alsa_mixer-test_get_value_0_35: pass
alsa_mixer-test_get_value_0_36: pass
alsa_mixer-test_get_value_0_37: pass
alsa_mixer-test_get_value_0_38: pass
alsa_mixer-test_get_value_0_39: pass
alsa_mixer-test_get_value_0_4: pass
alsa_mixer-test_get_value_0_40: pass
alsa_mixer-test_get_value_0_41: pass
alsa_mixer-test_get_value_0_42: pass
alsa_mixer-test_get_value_0_43: pass
alsa_mixer-test_get_value_0_44: pass
alsa_mixer-test_get_value_0_45: pass
alsa_mixer-test_get_value_0_46: pass
alsa_mixer-test_get_value_0_47: pass
alsa_mixer-test_get_value_0_48: pass
alsa_mixer-test_get_value_0_49: pass
alsa_mixer-test_get_value_0_5: pass
alsa_mixer-test_get_value_0_50: pass
alsa_mixer-test_get_value_0_51: pass
alsa_mixer-test_get_value_0_52: pass
alsa_mixer-test_get_value_0_53: pass
alsa_mixer-test_get_value_0_54: pass
alsa_mixer-test_get_value_0_55: pass
alsa_mixer-test_get_value_0_56: pass
alsa_mixer-test_get_value_0_57: pass
alsa_mixer-test_get_value_0_58: pass
alsa_mixer-test_get_value_0_59: pass
alsa_mixer-test_get_value_0_6: pass
alsa_mixer-test_get_value_0_60: pass
alsa_mixer-test_get_value_0_61: pass
alsa_mixer-test_get_value_0_62: pass
alsa_mixer-test_get_value_0_63: pass
alsa_mixer-test_get_value_0_64: pass
alsa_mixer-test_get_value_0_65: pass
alsa_mixer-test_get_value_0_66: pass
alsa_mixer-test_get_value_0_67: pass
alsa_mixer-test_get_value_0_68: pass
alsa_mixer-test_get_value_0_69: pass
alsa_mixer-test_get_value_0_7: pass
alsa_mixer-test_get_value_0_70: pass
alsa_mixer-test_get_value_0_71: pass
alsa_mixer-test_get_value_0_72: pass
alsa_mixer-test_get_value_0_73: pass
alsa_mixer-test_get_value_0_74: pass
alsa_mixer-test_get_value_0_75: pass
alsa_mixer-test_get_value_0_76: pass
alsa_mixer-test_get_value_0_77: fail
alsa_mixer-test_get_value_0_78: fail
alsa_mixer-test_get_value_0_79: fail
alsa_mixer-test_get_value_0_8: pass
alsa_mixer-test_get_value_0_80: pass
alsa_mixer-test_get_value_0_81: pass
alsa_mixer-test_get_value_0_82: pass
alsa_mixer-test_get_value_0_83: pass
alsa_mixer-test_get_value_0_84: pass
alsa_mixer-test_get_value_0_85: pass
alsa_mixer-test_get_value_0_86: pass
alsa_mixer-test_get_value_0_87: pass
alsa_mixer-test_get_value_0_88: pass
alsa_mixer-test_get_value_0_89: pass
alsa_mixer-test_get_value_0_9: pass
alsa_mixer-test_get_value_0_90: pass
alsa_mixer-test_get_value_0_91: pass
alsa_mixer-test_get_value_0_92: pass
alsa_mixer-test_get_value_0_93: pass
alsa_mixer-test_name_0_0: pass
alsa_mixer-test_name_0_1: pass
alsa_mixer-test_name_0_10: fail
alsa_mixer-test_name_0_11: fail
alsa_mixer-test_name_0_12: fail
alsa_mixer-test_name_0_13: fail
alsa_mixer-test_name_0_14: fail
alsa_mixer-test_name_0_15: fail
alsa_mixer-test_name_0_16: fail
alsa_mixer-test_name_0_17: fail
alsa_mixer-test_name_0_18: fail
alsa_mixer-test_name_0_19: fail
alsa_mixer-test_name_0_2: pass
alsa_mixer-test_name_0_20: fail
alsa_mixer-test_name_0_21: fail
alsa_mixer-test_name_0_22: pass
alsa_mixer-test_name_0_23: pass
alsa_mixer-test_name_0_24: pass
alsa_mixer-test_name_0_25: pass
alsa_mixer-test_name_0_26: pass
alsa_mixer-test_name_0_27: pass
alsa_mixer-test_name_0_28: pass
alsa_mixer-test_name_0_29: pass
alsa_mixer-test_name_0_3: pass
alsa_mixer-test_name_0_30: fail
alsa_mixer-test_name_0_31: fail
alsa_mixer-test_name_0_32: fail
alsa_mixer-test_name_0_33: fail
alsa_mixer-test_name_0_34: fail
alsa_mixer-test_name_0_35: fail
alsa_mixer-test_name_0_36: fail
alsa_mixer-test_name_0_37: fail
alsa_mixer-test_name_0_38: fail
alsa_mixer-test_name_0_39: fail
alsa_mixer-test_name_0_4: pass
alsa_mixer-test_name_0_40: fail
alsa_mixer-test_name_0_41: fail
alsa_mixer-test_name_0_42: fail
alsa_mixer-test_name_0_43: fail
alsa_mixer-test_name_0_44: fail
alsa_mixer-test_name_0_45: fail
alsa_mixer-test_name_0_46: fail
alsa_mixer-test_name_0_47: fail
alsa_mixer-test_name_0_48: fail
alsa_mixer-test_name_0_49: fail
alsa_mixer-test_name_0_5: pass
alsa_mixer-test_name_0_50: fail
alsa_mixer-test_name_0_51: fail
alsa_mixer-test_name_0_52: fail
alsa_mixer-test_name_0_53: fail
alsa_mixer-test_name_0_54: fail
alsa_mixer-test_name_0_55: fail
alsa_mixer-test_name_0_56: fail
alsa_mixer-test_name_0_57: fail
alsa_mixer-test_name_0_58: fail
alsa_mixer-test_name_0_59: fail
alsa_mixer-test_name_0_6: fail
alsa_mixer-test_name_0_60: fail
alsa_mixer-test_name_0_61: fail
alsa_mixer-test_name_0_62: fail
alsa_mixer-test_name_0_63: fail
alsa_mixer-test_name_0_64: fail
alsa_mixer-test_name_0_65: fail
alsa_mixer-test_name_0_66: fail
alsa_mixer-test_name_0_67: fail
alsa_mixer-test_name_0_68: fail
alsa_mixer-test_name_0_69: fail
alsa_mixer-test_name_0_7: fail
alsa_mixer-test_name_0_70: fail
alsa_mixer-test_name_0_71: fail
alsa_mixer-test_name_0_72: fail
alsa_mixer-test_name_0_73: fail
alsa_mixer-test_name_0_74: fail
alsa_mixer-test_name_0_75: fail
alsa_mixer-test_name_0_76: fail
alsa_mixer-test_name_0_77: pass
alsa_mixer-test_name_0_78: pass
alsa_mixer-test_name_0_79: pass
alsa_mixer-test_name_0_8: fail
alsa_mixer-test_name_0_80: pass
alsa_mixer-test_name_0_81: pass
alsa_mixer-test_name_0_82: pass
alsa_mixer-test_name_0_83: pass
alsa_mixer-test_name_0_84: pass
alsa_mixer-test_name_0_85: pass
alsa_mixer-test_name_0_86: pass
alsa_mixer-test_name_0_87: pass
alsa_mixer-test_name_0_88: pass
alsa_mixer-test_name_0_89: pass
alsa_mixer-test_name_0_9: fail
alsa_mixer-test_name_0_90: pass
alsa_mixer-test_name_0_91: pass
alsa_mixer-test_name_0_92: pass
alsa_mixer-test_name_0_93: pass
alsa_mixer-test_write_default_0_0: pass
alsa_mixer-test_write_default_0_1: pass
alsa_mixer-test_write_default_0_10: pass
alsa_mixer-test_write_default_0_11: pass
alsa_mixer-test_write_default_0_12: pass
alsa_mixer-test_write_default_0_13: pass
alsa_mixer-test_write_default_0_14: pass
alsa_mixer-test_write_default_0_15: pass
alsa_mixer-test_write_default_0_16: pass
alsa_mixer-test_write_default_0_17: pass
alsa_mixer-test_write_default_0_18: pass
alsa_mixer-test_write_default_0_19: pass
alsa_mixer-test_write_default_0_2: pass
alsa_mixer-test_write_default_0_20: pass
alsa_mixer-test_write_default_0_21: pass
alsa_mixer-test_write_default_0_22: pass
alsa_mixer-test_write_default_0_23: pass
alsa_mixer-test_write_default_0_24: pass
alsa_mixer-test_write_default_0_25: pass
alsa_mixer-test_write_default_0_26: pass
alsa_mixer-test_write_default_0_27: pass
alsa_mixer-test_write_default_0_28: pass
alsa_mixer-test_write_default_0_29: pass
alsa_mixer-test_write_default_0_3: pass
alsa_mixer-test_write_default_0_30: pass
alsa_mixer-test_write_default_0_31: pass
alsa_mixer-test_write_default_0_32: pass
alsa_mixer-test_write_default_0_33: pass
alsa_mixer-test_write_default_0_34: pass
alsa_mixer-test_write_default_0_35: pass
alsa_mixer-test_write_default_0_36: pass
alsa_mixer-test_write_default_0_37: pass
alsa_mixer-test_write_default_0_38: pass
alsa_mixer-test_write_default_0_39: pass
alsa_mixer-test_write_default_0_4: pass
alsa_mixer-test_write_default_0_40: pass
alsa_mixer-test_write_default_0_41: pass
alsa_mixer-test_write_default_0_42: pass
alsa_mixer-test_write_default_0_43: pass
alsa_mixer-test_write_default_0_44: pass
alsa_mixer-test_write_default_0_45: pass
alsa_mixer-test_write_default_0_46: pass
alsa_mixer-test_write_default_0_47: pass
alsa_mixer-test_write_default_0_48: pass
alsa_mixer-test_write_default_0_49: pass
alsa_mixer-test_write_default_0_5: pass
alsa_mixer-test_write_default_0_50: pass
alsa_mixer-test_write_default_0_51: pass
alsa_mixer-test_write_default_0_52: pass
alsa_mixer-test_write_default_0_53: pass
alsa_mixer-test_write_default_0_54: pass
alsa_mixer-test_write_default_0_55: pass
alsa_mixer-test_write_default_0_56: pass
alsa_mixer-test_write_default_0_57: pass
alsa_mixer-test_write_default_0_58: pass
alsa_mixer-test_write_default_0_59: pass
alsa_mixer-test_write_default_0_6: pass
alsa_mixer-test_write_default_0_60: pass
alsa_mixer-test_write_default_0_61: pass
alsa_mixer-test_write_default_0_62: pass
alsa_mixer-test_write_default_0_63: pass
alsa_mixer-test_write_default_0_64: pass
alsa_mixer-test_write_default_0_65: pass
alsa_mixer-test_write_default_0_66: pass
alsa_mixer-test_write_default_0_67: pass
alsa_mixer-test_write_default_0_68: pass
alsa_mixer-test_write_default_0_69: pass
alsa_mixer-test_write_default_0_7: pass
alsa_mixer-test_write_default_0_70: pass
alsa_mixer-test_write_default_0_71: pass
alsa_mixer-test_write_default_0_72: pass
alsa_mixer-test_write_default_0_73: pass
alsa_mixer-test_write_default_0_74: pass
alsa_mixer-test_write_default_0_75: pass
alsa_mixer-test_write_default_0_76: pass
alsa_mixer-test_write_default_0_77: fail
alsa_mixer-test_write_default_0_78: fail
alsa_mixer-test_write_default_0_79: fail
alsa_mixer-test_write_default_0_8: pass
alsa_mixer-test_write_default_0_80: pass
alsa_mixer-test_write_default_0_81: pass
alsa_mixer-test_write_default_0_82: skip
alsa_mixer-test_write_default_0_83: pass
alsa_mixer-test_write_default_0_84: pass
alsa_mixer-test_write_default_0_85: pass
alsa_mixer-test_write_default_0_86: pass
alsa_mixer-test_write_default_0_87: pass
alsa_mixer-test_write_default_0_88: pass
alsa_mixer-test_write_default_0_89: pass
alsa_mixer-test_write_default_0_9: pass
alsa_mixer-test_write_default_0_90: pass
alsa_mixer-test_write_default_0_91: pass
alsa_mixer-test_write_default_0_92: pass
alsa_mixer-test_write_default_0_93: pass
alsa_mixer-test_write_invalid_0_0: pass
alsa_mixer-test_write_invalid_0_1: pass
alsa_mixer-test_write_invalid_0_10: pass
alsa_mixer-test_write_invalid_0_11: pass
alsa_mixer-test_write_invalid_0_12: pass
alsa_mixer-test_write_invalid_0_13: pass
alsa_mixer-test_write_invalid_0_14: pass
alsa_mixer-test_write_invalid_0_15: pass
alsa_mixer-test_write_invalid_0_16: pass
alsa_mixer-test_write_invalid_0_17: pass
alsa_mixer-test_write_invalid_0_18: pass
alsa_mixer-test_write_invalid_0_19: pass
alsa_mixer-test_write_invalid_0_2: pass
alsa_mixer-test_write_invalid_0_20: pass
alsa_mixer-test_write_invalid_0_21: pass
alsa_mixer-test_write_invalid_0_22: pass
alsa_mixer-test_write_invalid_0_23: pass
alsa_mixer-test_write_invalid_0_24: pass
alsa_mixer-test_write_invalid_0_25: pass
alsa_mixer-test_write_invalid_0_26: pass
alsa_mixer-test_write_invalid_0_27: pass
alsa_mixer-test_write_invalid_0_28: pass
alsa_mixer-test_write_invalid_0_29: pass
alsa_mixer-test_write_invalid_0_3: pass
alsa_mixer-test_write_invalid_0_30: pass
alsa_mixer-test_write_invalid_0_31: pass
alsa_mixer-test_write_invalid_0_32: pass
alsa_mixer-test_write_invalid_0_33: pass
alsa_mixer-test_write_invalid_0_34: pass
alsa_mixer-test_write_invalid_0_35: pass
alsa_mixer-test_write_invalid_0_36: pass
alsa_mixer-test_write_invalid_0_37: pass
alsa_mixer-test_write_invalid_0_38: pass
alsa_mixer-test_write_invalid_0_39: pass
alsa_mixer-test_write_invalid_0_4: pass
alsa_mixer-test_write_invalid_0_40: pass
alsa_mixer-test_write_invalid_0_41: pass
alsa_mixer-test_write_invalid_0_42: pass
alsa_mixer-test_write_invalid_0_43: pass
alsa_mixer-test_write_invalid_0_44: pass
alsa_mixer-test_write_invalid_0_45: pass
alsa_mixer-test_write_invalid_0_46: pass
alsa_mixer-test_write_invalid_0_47: pass
alsa_mixer-test_write_invalid_0_48: pass
alsa_mixer-test_write_invalid_0_49: pass
alsa_mixer-test_write_invalid_0_5: pass
alsa_mixer-test_write_invalid_0_50: pass
alsa_mixer-test_write_invalid_0_51: pass
alsa_mixer-test_write_invalid_0_52: pass
alsa_mixer-test_write_invalid_0_53: pass
alsa_mixer-test_write_invalid_0_54: pass
alsa_mixer-test_write_invalid_0_55: pass
alsa_mixer-test_write_invalid_0_56: pass
alsa_mixer-test_write_invalid_0_57: pass
alsa_mixer-test_write_invalid_0_58: pass
alsa_mixer-test_write_invalid_0_59: pass
alsa_mixer-test_write_invalid_0_6: pass
alsa_mixer-test_write_invalid_0_60: pass
alsa_mixer-test_write_invalid_0_61: pass
alsa_mixer-test_write_invalid_0_62: pass
alsa_mixer-test_write_invalid_0_63: pass
alsa_mixer-test_write_invalid_0_64: pass
alsa_mixer-test_write_invalid_0_65: pass
alsa_mixer-test_write_invalid_0_66: pass
alsa_mixer-test_write_invalid_0_67: pass
alsa_mixer-test_write_invalid_0_68: pass
alsa_mixer-test_write_invalid_0_69: pass
alsa_mixer-test_write_invalid_0_7: pass
alsa_mixer-test_write_invalid_0_70: pass
alsa_mixer-test_write_invalid_0_71: pass
alsa_mixer-test_write_invalid_0_72: pass
alsa_mixer-test_write_invalid_0_73: pass
alsa_mixer-test_write_invalid_0_74: pass
alsa_mixer-test_write_invalid_0_75: pass
alsa_mixer-test_write_invalid_0_76: pass
alsa_mixer-test_write_invalid_0_77: fail
alsa_mixer-test_write_invalid_0_78: fail
alsa_mixer-test_write_invalid_0_79: fail
alsa_mixer-test_write_invalid_0_8: pass
alsa_mixer-test_write_invalid_0_80: pass
alsa_mixer-test_write_invalid_0_81: fail
alsa_mixer-test_write_invalid_0_82: skip
alsa_mixer-test_write_invalid_0_83: pass
alsa_mixer-test_write_invalid_0_84: pass
alsa_mixer-test_write_invalid_0_85: pass
alsa_mixer-test_write_invalid_0_86: pass
alsa_mixer-test_write_invalid_0_87: pass
alsa_mixer-test_write_invalid_0_88: pass
alsa_mixer-test_write_invalid_0_89: pass
alsa_mixer-test_write_invalid_0_9: pass
alsa_mixer-test_write_invalid_0_90: pass
alsa_mixer-test_write_invalid_0_91: pass
alsa_mixer-test_write_invalid_0_92: pass
alsa_mixer-test_write_invalid_0_93: pass
alsa_mixer-test_write_valid_0_0: pass
alsa_mixer-test_write_valid_0_1: pass
alsa_mixer-test_write_valid_0_10: pass
alsa_mixer-test_write_valid_0_11: pass
alsa_mixer-test_write_valid_0_12: pass
alsa_mixer-test_write_valid_0_13: pass
alsa_mixer-test_write_valid_0_14: pass
alsa_mixer-test_write_valid_0_15: pass
alsa_mixer-test_write_valid_0_16: pass
alsa_mixer-test_write_valid_0_17: pass
alsa_mixer-test_write_valid_0_18: pass
alsa_mixer-test_write_valid_0_19: pass
alsa_mixer-test_write_valid_0_2: pass
alsa_mixer-test_write_valid_0_20: pass
alsa_mixer-test_write_valid_0_21: pass
alsa_mixer-test_write_valid_0_22: pass
alsa_mixer-test_write_valid_0_23: pass
alsa_mixer-test_write_valid_0_24: pass
alsa_mixer-test_write_valid_0_25: pass
alsa_mixer-test_write_valid_0_26: pass
alsa_mixer-test_write_valid_0_27: pass
alsa_mixer-test_write_valid_0_28: pass
alsa_mixer-test_write_valid_0_29: pass
alsa_mixer-test_write_valid_0_3: pass
alsa_mixer-test_write_valid_0_30: pass
alsa_mixer-test_write_valid_0_31: pass
alsa_mixer-test_write_valid_0_32: pass
alsa_mixer-test_write_valid_0_33: pass
alsa_mixer-test_write_valid_0_34: pass
alsa_mixer-test_write_valid_0_35: pass
alsa_mixer-test_write_valid_0_36: pass
alsa_mixer-test_write_valid_0_37: pass
alsa_mixer-test_write_valid_0_38: pass
alsa_mixer-test_write_valid_0_39: pass
alsa_mixer-test_write_valid_0_4: pass
alsa_mixer-test_write_valid_0_40: pass
alsa_mixer-test_write_valid_0_41: pass
alsa_mixer-test_write_valid_0_42: pass
alsa_mixer-test_write_valid_0_43: pass
alsa_mixer-test_write_valid_0_44: pass
alsa_mixer-test_write_valid_0_45: pass
alsa_mixer-test_write_valid_0_46: pass
alsa_mixer-test_write_valid_0_47: pass
alsa_mixer-test_write_valid_0_48: pass
alsa_mixer-test_write_valid_0_49: pass
alsa_mixer-test_write_valid_0_5: pass
alsa_mixer-test_write_valid_0_50: pass
alsa_mixer-test_write_valid_0_51: pass
alsa_mixer-test_write_valid_0_52: pass
alsa_mixer-test_write_valid_0_53: pass
alsa_mixer-test_write_valid_0_54: pass
alsa_mixer-test_write_valid_0_55: pass
alsa_mixer-test_write_valid_0_56: pass
alsa_mixer-test_write_valid_0_57: pass
alsa_mixer-test_write_valid_0_58: pass
alsa_mixer-test_write_valid_0_59: pass
alsa_mixer-test_write_valid_0_6: pass
alsa_mixer-test_write_valid_0_60: pass
alsa_mixer-test_write_valid_0_61: pass
alsa_mixer-test_write_valid_0_62: pass
alsa_mixer-test_write_valid_0_63: pass
alsa_mixer-test_write_valid_0_64: pass
alsa_mixer-test_write_valid_0_65: pass
alsa_mixer-test_write_valid_0_66: pass
alsa_mixer-test_write_valid_0_67: pass
alsa_mixer-test_write_valid_0_68: pass
alsa_mixer-test_write_valid_0_69: pass
alsa_mixer-test_write_valid_0_7: pass
alsa_mixer-test_write_valid_0_70: pass
alsa_mixer-test_write_valid_0_71: pass
alsa_mixer-test_write_valid_0_72: pass
alsa_mixer-test_write_valid_0_73: pass
alsa_mixer-test_write_valid_0_74: pass
alsa_mixer-test_write_valid_0_75: pass
alsa_mixer-test_write_valid_0_76: pass
alsa_mixer-test_write_valid_0_77: fail
alsa_mixer-test_write_valid_0_78: fail
alsa_mixer-test_write_valid_0_79: fail
alsa_mixer-test_write_valid_0_8: pass
alsa_mixer-test_write_valid_0_80: pass
alsa_mixer-test_write_valid_0_81: pass
alsa_mixer-test_write_valid_0_82: skip
alsa_mixer-test_write_valid_0_83: pass
alsa_mixer-test_write_valid_0_84: pass
alsa_mixer-test_write_valid_0_85: fail
alsa_mixer-test_write_valid_0_86: fail
alsa_mixer-test_write_valid_0_87: pass
alsa_mixer-test_write_valid_0_88: fail
alsa_mixer-test_write_valid_0_89: pass
alsa_mixer-test_write_valid_0_9: pass
alsa_mixer-test_write_valid_0_90: pass
alsa_mixer-test_write_valid_0_91: pass
alsa_mixer-test_write_valid_0_92: pass
alsa_mixer-test_write_valid_0_93: pass
shardfile-alsa: pass
9952 01:58:29.065290 end: 3.1 lava-test-shell (duration 00:00:43) [common]
9953 01:58:29.065412 end: 3 lava-test-retry (duration 00:00:43) [common]
9954 01:58:29.065528 start: 4 finalize (timeout 00:07:22) [common]
9955 01:58:29.065657 start: 4.1 power-off (timeout 00:00:30) [common]
9956 01:58:29.065891 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8183-kukui-jacuzzi-juniper-sku16-cbg-3', '--port=1', '--command=off']
9957 01:58:30.483316 >> Command sent successfully.
9958 01:58:30.486306 Returned 0 in 1 seconds
9959 01:58:30.586856 end: 4.1 power-off (duration 00:00:02) [common]
9961 01:58:30.587213 start: 4.2 read-feedback (timeout 00:07:21) [common]
9962 01:58:30.587519 Listened to connection for namespace 'common' for up to 1s
9963 01:58:31.588459 Finalising connection for namespace 'common'
9964 01:58:31.588683 Disconnecting from shell: Finalise
9965 01:58:31.588786 / #
9966 01:58:31.689140 end: 4.2 read-feedback (duration 00:00:01) [common]
9967 01:58:31.689379 end: 4 finalize (duration 00:00:03) [common]
9968 01:58:31.689514 Cleaning after the job
9969 01:58:31.689632 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14479169/tftp-deploy-fdqb7x23/ramdisk
9970 01:58:31.692102 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14479169/tftp-deploy-fdqb7x23/kernel
9971 01:58:31.703582 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14479169/tftp-deploy-fdqb7x23/dtb
9972 01:58:31.703819 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14479169/tftp-deploy-fdqb7x23/nfsrootfs
9973 01:58:31.769229 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14479169/tftp-deploy-fdqb7x23/modules
9974 01:58:31.775350 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14479169
9975 01:58:32.430577 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14479169
9976 01:58:32.430816 Job finished correctly