Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 37
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 25
1 00:21:08.152297 lava-dispatcher, installed at version: 2024.03
2 00:21:08.152516 start: 0 validate
3 00:21:08.152630 Start time: 2024-06-21 00:21:08.152624+00:00 (UTC)
4 00:21:08.152762 Using caching service: 'http://localhost/cache/?uri=%s'
5 00:21:08.152901 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 00:21:08.415510 Using caching service: 'http://localhost/cache/?uri=%s'
7 00:21:08.416224 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.94-cip23%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 00:21:08.678263 Using caching service: 'http://localhost/cache/?uri=%s'
9 00:21:08.679102 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.94-cip23%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 00:21:46.652730 Using caching service: 'http://localhost/cache/?uri=%s'
11 00:21:46.653668 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 00:21:47.162576 Using caching service: 'http://localhost/cache/?uri=%s'
13 00:21:47.163629 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.94-cip23%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 00:21:47.419252 validate duration: 39.27
16 00:21:47.419590 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 00:21:47.419720 start: 1.1 download-retry (timeout 00:10:00) [common]
18 00:21:47.419861 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 00:21:47.420061 Not decompressing ramdisk as can be used compressed.
20 00:21:47.420188 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 00:21:47.420304 saving as /var/lib/lava/dispatcher/tmp/14479179/tftp-deploy-4yfo8uu6/ramdisk/initrd.cpio.gz
22 00:21:47.420400 total size: 5628169 (5 MB)
23 00:21:51.427937 progress 0 % (0 MB)
24 00:21:51.433093 progress 5 % (0 MB)
25 00:21:51.434687 progress 10 % (0 MB)
26 00:21:51.436194 progress 15 % (0 MB)
27 00:21:51.437673 progress 20 % (1 MB)
28 00:21:51.439068 progress 25 % (1 MB)
29 00:21:51.440545 progress 30 % (1 MB)
30 00:21:51.442001 progress 35 % (1 MB)
31 00:21:51.443370 progress 40 % (2 MB)
32 00:21:51.444818 progress 45 % (2 MB)
33 00:21:51.446130 progress 50 % (2 MB)
34 00:21:51.447632 progress 55 % (2 MB)
35 00:21:51.449097 progress 60 % (3 MB)
36 00:21:51.450472 progress 65 % (3 MB)
37 00:21:51.451939 progress 70 % (3 MB)
38 00:21:51.453284 progress 75 % (4 MB)
39 00:21:51.454829 progress 80 % (4 MB)
40 00:21:51.456194 progress 85 % (4 MB)
41 00:21:51.457762 progress 90 % (4 MB)
42 00:21:51.459349 progress 95 % (5 MB)
43 00:21:51.460674 progress 100 % (5 MB)
44 00:21:51.460873 5 MB downloaded in 4.04 s (1.33 MB/s)
45 00:21:51.461011 end: 1.1.1 http-download (duration 00:00:04) [common]
47 00:21:51.461227 end: 1.1 download-retry (duration 00:00:04) [common]
48 00:21:51.461306 start: 1.2 download-retry (timeout 00:09:56) [common]
49 00:21:51.461380 start: 1.2.1 http-download (timeout 00:09:56) [common]
50 00:21:51.461509 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.94-cip23/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 00:21:51.461569 saving as /var/lib/lava/dispatcher/tmp/14479179/tftp-deploy-4yfo8uu6/kernel/Image
52 00:21:51.461621 total size: 54813184 (52 MB)
53 00:21:51.461675 No compression specified
54 00:21:51.720059 progress 0 % (0 MB)
55 00:21:51.770980 progress 5 % (2 MB)
56 00:21:51.789354 progress 10 % (5 MB)
57 00:21:51.802664 progress 15 % (7 MB)
58 00:21:51.816184 progress 20 % (10 MB)
59 00:21:51.830455 progress 25 % (13 MB)
60 00:21:51.843686 progress 30 % (15 MB)
61 00:21:51.857268 progress 35 % (18 MB)
62 00:21:51.870923 progress 40 % (20 MB)
63 00:21:51.884240 progress 45 % (23 MB)
64 00:21:51.897926 progress 50 % (26 MB)
65 00:21:51.911397 progress 55 % (28 MB)
66 00:21:51.924613 progress 60 % (31 MB)
67 00:21:51.938240 progress 65 % (34 MB)
68 00:21:51.951864 progress 70 % (36 MB)
69 00:21:51.965310 progress 75 % (39 MB)
70 00:21:51.978814 progress 80 % (41 MB)
71 00:21:51.991933 progress 85 % (44 MB)
72 00:21:52.005962 progress 90 % (47 MB)
73 00:21:52.019651 progress 95 % (49 MB)
74 00:21:52.032897 progress 100 % (52 MB)
75 00:21:52.033108 52 MB downloaded in 0.57 s (91.47 MB/s)
76 00:21:52.033251 end: 1.2.1 http-download (duration 00:00:01) [common]
78 00:21:52.033457 end: 1.2 download-retry (duration 00:00:01) [common]
79 00:21:52.033545 start: 1.3 download-retry (timeout 00:09:55) [common]
80 00:21:52.033662 start: 1.3.1 http-download (timeout 00:09:55) [common]
81 00:21:52.033805 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.94-cip23/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 00:21:52.033879 saving as /var/lib/lava/dispatcher/tmp/14479179/tftp-deploy-4yfo8uu6/dtb/mt8192-asurada-spherion-r0.dtb
83 00:21:52.033931 total size: 47258 (0 MB)
84 00:21:52.033983 No compression specified
85 00:21:52.035169 progress 69 % (0 MB)
86 00:21:52.035472 progress 100 % (0 MB)
87 00:21:52.035644 0 MB downloaded in 0.00 s (26.35 MB/s)
88 00:21:52.035756 end: 1.3.1 http-download (duration 00:00:00) [common]
90 00:21:52.035951 end: 1.3 download-retry (duration 00:00:00) [common]
91 00:21:52.036025 start: 1.4 download-retry (timeout 00:09:55) [common]
92 00:21:52.036098 start: 1.4.1 http-download (timeout 00:09:55) [common]
93 00:21:52.036210 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 00:21:52.036270 saving as /var/lib/lava/dispatcher/tmp/14479179/tftp-deploy-4yfo8uu6/nfsrootfs/full.rootfs.tar
95 00:21:52.036321 total size: 120894716 (115 MB)
96 00:21:52.036375 Using unxz to decompress xz
97 00:21:52.037560 progress 0 % (0 MB)
98 00:21:52.370147 progress 5 % (5 MB)
99 00:21:52.702769 progress 10 % (11 MB)
100 00:21:53.041430 progress 15 % (17 MB)
101 00:21:53.356748 progress 20 % (23 MB)
102 00:21:53.656930 progress 25 % (28 MB)
103 00:21:53.988240 progress 30 % (34 MB)
104 00:21:54.303869 progress 35 % (40 MB)
105 00:21:54.471103 progress 40 % (46 MB)
106 00:21:54.652946 progress 45 % (51 MB)
107 00:21:54.944711 progress 50 % (57 MB)
108 00:21:55.290447 progress 55 % (63 MB)
109 00:21:55.616761 progress 60 % (69 MB)
110 00:21:55.948143 progress 65 % (74 MB)
111 00:21:56.279361 progress 70 % (80 MB)
112 00:21:56.614143 progress 75 % (86 MB)
113 00:21:56.937517 progress 80 % (92 MB)
114 00:21:57.265179 progress 85 % (98 MB)
115 00:21:57.590305 progress 90 % (103 MB)
116 00:21:57.899507 progress 95 % (109 MB)
117 00:21:58.250640 progress 100 % (115 MB)
118 00:21:58.255911 115 MB downloaded in 6.22 s (18.54 MB/s)
119 00:21:58.256065 end: 1.4.1 http-download (duration 00:00:06) [common]
121 00:21:58.256273 end: 1.4 download-retry (duration 00:00:06) [common]
122 00:21:58.256350 start: 1.5 download-retry (timeout 00:09:49) [common]
123 00:21:58.256425 start: 1.5.1 http-download (timeout 00:09:49) [common]
124 00:21:58.256554 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.94-cip23/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 00:21:58.256614 saving as /var/lib/lava/dispatcher/tmp/14479179/tftp-deploy-4yfo8uu6/modules/modules.tar
126 00:21:58.256667 total size: 8618924 (8 MB)
127 00:21:58.256720 Using unxz to decompress xz
128 00:21:58.516011 progress 0 % (0 MB)
129 00:21:58.540457 progress 5 % (0 MB)
130 00:21:58.566917 progress 10 % (0 MB)
131 00:21:58.595179 progress 15 % (1 MB)
132 00:21:58.622863 progress 20 % (1 MB)
133 00:21:58.650580 progress 25 % (2 MB)
134 00:21:58.675337 progress 30 % (2 MB)
135 00:21:58.700304 progress 35 % (2 MB)
136 00:21:58.725843 progress 40 % (3 MB)
137 00:21:58.751771 progress 45 % (3 MB)
138 00:21:58.775659 progress 50 % (4 MB)
139 00:21:58.799713 progress 55 % (4 MB)
140 00:21:58.823886 progress 60 % (4 MB)
141 00:21:58.848276 progress 65 % (5 MB)
142 00:21:58.876338 progress 70 % (5 MB)
143 00:21:58.901369 progress 75 % (6 MB)
144 00:21:58.924480 progress 80 % (6 MB)
145 00:21:58.946991 progress 85 % (7 MB)
146 00:21:58.969486 progress 90 % (7 MB)
147 00:21:58.996849 progress 95 % (7 MB)
148 00:21:59.028403 progress 100 % (8 MB)
149 00:21:59.032923 8 MB downloaded in 0.78 s (10.59 MB/s)
150 00:21:59.033079 end: 1.5.1 http-download (duration 00:00:01) [common]
152 00:21:59.033286 end: 1.5 download-retry (duration 00:00:01) [common]
153 00:21:59.033364 start: 1.6 prepare-tftp-overlay (timeout 00:09:48) [common]
154 00:21:59.033439 start: 1.6.1 extract-nfsrootfs (timeout 00:09:48) [common]
155 00:22:02.572763 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14479179/extract-nfsrootfs-6gqy51jo
156 00:22:02.572942 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 00:22:02.573032 start: 1.6.2 lava-overlay (timeout 00:09:45) [common]
158 00:22:02.573192 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14479179/lava-overlay-gqg50zic
159 00:22:02.573309 makedir: /var/lib/lava/dispatcher/tmp/14479179/lava-overlay-gqg50zic/lava-14479179/bin
160 00:22:02.573398 makedir: /var/lib/lava/dispatcher/tmp/14479179/lava-overlay-gqg50zic/lava-14479179/tests
161 00:22:02.573484 makedir: /var/lib/lava/dispatcher/tmp/14479179/lava-overlay-gqg50zic/lava-14479179/results
162 00:22:02.573571 Creating /var/lib/lava/dispatcher/tmp/14479179/lava-overlay-gqg50zic/lava-14479179/bin/lava-add-keys
163 00:22:02.573707 Creating /var/lib/lava/dispatcher/tmp/14479179/lava-overlay-gqg50zic/lava-14479179/bin/lava-add-sources
164 00:22:02.573853 Creating /var/lib/lava/dispatcher/tmp/14479179/lava-overlay-gqg50zic/lava-14479179/bin/lava-background-process-start
165 00:22:02.573996 Creating /var/lib/lava/dispatcher/tmp/14479179/lava-overlay-gqg50zic/lava-14479179/bin/lava-background-process-stop
166 00:22:02.574152 Creating /var/lib/lava/dispatcher/tmp/14479179/lava-overlay-gqg50zic/lava-14479179/bin/lava-common-functions
167 00:22:02.574331 Creating /var/lib/lava/dispatcher/tmp/14479179/lava-overlay-gqg50zic/lava-14479179/bin/lava-echo-ipv4
168 00:22:02.574443 Creating /var/lib/lava/dispatcher/tmp/14479179/lava-overlay-gqg50zic/lava-14479179/bin/lava-install-packages
169 00:22:02.574554 Creating /var/lib/lava/dispatcher/tmp/14479179/lava-overlay-gqg50zic/lava-14479179/bin/lava-installed-packages
170 00:22:02.574663 Creating /var/lib/lava/dispatcher/tmp/14479179/lava-overlay-gqg50zic/lava-14479179/bin/lava-os-build
171 00:22:02.574778 Creating /var/lib/lava/dispatcher/tmp/14479179/lava-overlay-gqg50zic/lava-14479179/bin/lava-probe-channel
172 00:22:02.574887 Creating /var/lib/lava/dispatcher/tmp/14479179/lava-overlay-gqg50zic/lava-14479179/bin/lava-probe-ip
173 00:22:02.574996 Creating /var/lib/lava/dispatcher/tmp/14479179/lava-overlay-gqg50zic/lava-14479179/bin/lava-target-ip
174 00:22:02.575103 Creating /var/lib/lava/dispatcher/tmp/14479179/lava-overlay-gqg50zic/lava-14479179/bin/lava-target-mac
175 00:22:02.575210 Creating /var/lib/lava/dispatcher/tmp/14479179/lava-overlay-gqg50zic/lava-14479179/bin/lava-target-storage
176 00:22:02.575320 Creating /var/lib/lava/dispatcher/tmp/14479179/lava-overlay-gqg50zic/lava-14479179/bin/lava-test-case
177 00:22:02.575433 Creating /var/lib/lava/dispatcher/tmp/14479179/lava-overlay-gqg50zic/lava-14479179/bin/lava-test-event
178 00:22:02.575542 Creating /var/lib/lava/dispatcher/tmp/14479179/lava-overlay-gqg50zic/lava-14479179/bin/lava-test-feedback
179 00:22:02.575650 Creating /var/lib/lava/dispatcher/tmp/14479179/lava-overlay-gqg50zic/lava-14479179/bin/lava-test-raise
180 00:22:02.575756 Creating /var/lib/lava/dispatcher/tmp/14479179/lava-overlay-gqg50zic/lava-14479179/bin/lava-test-reference
181 00:22:02.575864 Creating /var/lib/lava/dispatcher/tmp/14479179/lava-overlay-gqg50zic/lava-14479179/bin/lava-test-runner
182 00:22:02.575975 Creating /var/lib/lava/dispatcher/tmp/14479179/lava-overlay-gqg50zic/lava-14479179/bin/lava-test-set
183 00:22:02.576081 Creating /var/lib/lava/dispatcher/tmp/14479179/lava-overlay-gqg50zic/lava-14479179/bin/lava-test-shell
184 00:22:02.576190 Updating /var/lib/lava/dispatcher/tmp/14479179/lava-overlay-gqg50zic/lava-14479179/bin/lava-add-keys (debian)
185 00:22:02.576323 Updating /var/lib/lava/dispatcher/tmp/14479179/lava-overlay-gqg50zic/lava-14479179/bin/lava-add-sources (debian)
186 00:22:02.576444 Updating /var/lib/lava/dispatcher/tmp/14479179/lava-overlay-gqg50zic/lava-14479179/bin/lava-install-packages (debian)
187 00:22:02.576564 Updating /var/lib/lava/dispatcher/tmp/14479179/lava-overlay-gqg50zic/lava-14479179/bin/lava-installed-packages (debian)
188 00:22:02.576683 Updating /var/lib/lava/dispatcher/tmp/14479179/lava-overlay-gqg50zic/lava-14479179/bin/lava-os-build (debian)
189 00:22:02.576788 Creating /var/lib/lava/dispatcher/tmp/14479179/lava-overlay-gqg50zic/lava-14479179/environment
190 00:22:02.576871 LAVA metadata
191 00:22:02.576934 - LAVA_JOB_ID=14479179
192 00:22:02.576990 - LAVA_DISPATCHER_IP=192.168.201.1
193 00:22:02.577080 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:45) [common]
194 00:22:02.577137 skipped lava-vland-overlay
195 00:22:02.577203 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 00:22:02.577273 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:45) [common]
197 00:22:02.577326 skipped lava-multinode-overlay
198 00:22:02.577390 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 00:22:02.577470 start: 1.6.2.3 test-definition (timeout 00:09:45) [common]
200 00:22:02.577531 Loading test definitions
201 00:22:02.577605 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:45) [common]
202 00:22:02.577662 Using /lava-14479179 at stage 0
203 00:22:02.577923 uuid=14479179_1.6.2.3.1 testdef=None
204 00:22:02.578002 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 00:22:02.578076 start: 1.6.2.3.2 test-overlay (timeout 00:09:45) [common]
206 00:22:02.578531 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 00:22:02.578726 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:45) [common]
209 00:22:02.579223 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 00:22:02.579429 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:45) [common]
212 00:22:02.579908 runner path: /var/lib/lava/dispatcher/tmp/14479179/lava-overlay-gqg50zic/lava-14479179/0/tests/0_timesync-off test_uuid 14479179_1.6.2.3.1
213 00:22:02.580052 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 00:22:02.580251 start: 1.6.2.3.5 git-repo-action (timeout 00:09:45) [common]
216 00:22:02.580313 Using /lava-14479179 at stage 0
217 00:22:02.580398 Fetching tests from https://github.com/kernelci/test-definitions.git
218 00:22:02.580472 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14479179/lava-overlay-gqg50zic/lava-14479179/0/tests/1_kselftest-alsa'
219 00:22:05.002262 Running '/usr/bin/git checkout kernelci.org
220 00:22:05.148741 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14479179/lava-overlay-gqg50zic/lava-14479179/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
221 00:22:05.149111 uuid=14479179_1.6.2.3.5 testdef=None
222 00:22:05.149213 end: 1.6.2.3.5 git-repo-action (duration 00:00:03) [common]
224 00:22:05.149410 start: 1.6.2.3.6 test-overlay (timeout 00:09:42) [common]
225 00:22:05.150053 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 00:22:05.150291 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:42) [common]
228 00:22:05.151159 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 00:22:05.151375 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:42) [common]
231 00:22:05.152211 runner path: /var/lib/lava/dispatcher/tmp/14479179/lava-overlay-gqg50zic/lava-14479179/0/tests/1_kselftest-alsa test_uuid 14479179_1.6.2.3.5
232 00:22:05.152294 BOARD='mt8192-asurada-spherion-r0'
233 00:22:05.152355 BRANCH='cip'
234 00:22:05.152409 SKIPFILE='/dev/null'
235 00:22:05.152461 SKIP_INSTALL='True'
236 00:22:05.152511 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.94-cip23/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 00:22:05.152563 TST_CASENAME=''
238 00:22:05.152614 TST_CMDFILES='alsa'
239 00:22:05.152792 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 00:22:05.152978 Creating lava-test-runner.conf files
242 00:22:05.153034 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14479179/lava-overlay-gqg50zic/lava-14479179/0 for stage 0
243 00:22:05.153116 - 0_timesync-off
244 00:22:05.153176 - 1_kselftest-alsa
245 00:22:05.153262 end: 1.6.2.3 test-definition (duration 00:00:03) [common]
246 00:22:05.153339 start: 1.6.2.4 compress-overlay (timeout 00:09:42) [common]
247 00:22:12.232304 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 00:22:12.232425 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:35) [common]
249 00:22:12.232507 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 00:22:12.232588 end: 1.6.2 lava-overlay (duration 00:00:10) [common]
251 00:22:12.232667 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:35) [common]
252 00:22:12.390428 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 00:22:12.390580 start: 1.6.4 extract-modules (timeout 00:09:35) [common]
254 00:22:12.390661 extracting modules file /var/lib/lava/dispatcher/tmp/14479179/tftp-deploy-4yfo8uu6/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14479179/extract-nfsrootfs-6gqy51jo
255 00:22:12.607823 extracting modules file /var/lib/lava/dispatcher/tmp/14479179/tftp-deploy-4yfo8uu6/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14479179/extract-overlay-ramdisk-knu21m1d/ramdisk
256 00:22:12.830478 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 00:22:12.830618 start: 1.6.5 apply-overlay-tftp (timeout 00:09:35) [common]
258 00:22:12.830694 [common] Applying overlay to NFS
259 00:22:12.830752 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14479179/compress-overlay-fuvghzxv/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14479179/extract-nfsrootfs-6gqy51jo
260 00:22:13.655912 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 00:22:13.656057 start: 1.6.6 configure-preseed-file (timeout 00:09:34) [common]
262 00:22:13.656141 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 00:22:13.656232 start: 1.6.7 compress-ramdisk (timeout 00:09:34) [common]
264 00:22:13.656303 Building ramdisk /var/lib/lava/dispatcher/tmp/14479179/extract-overlay-ramdisk-knu21m1d/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14479179/extract-overlay-ramdisk-knu21m1d/ramdisk
265 00:22:13.992504 >> 130487 blocks
266 00:22:16.020184 rename /var/lib/lava/dispatcher/tmp/14479179/extract-overlay-ramdisk-knu21m1d/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14479179/tftp-deploy-4yfo8uu6/ramdisk/ramdisk.cpio.gz
267 00:22:16.020360 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 00:22:16.020451 start: 1.6.8 prepare-kernel (timeout 00:09:31) [common]
269 00:22:16.020530 start: 1.6.8.1 prepare-fit (timeout 00:09:31) [common]
270 00:22:16.020608 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14479179/tftp-deploy-4yfo8uu6/kernel/Image']
271 00:22:29.186653 Returned 0 in 13 seconds
272 00:22:29.287492 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14479179/tftp-deploy-4yfo8uu6/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14479179/tftp-deploy-4yfo8uu6/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14479179/tftp-deploy-4yfo8uu6/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14479179/tftp-deploy-4yfo8uu6/kernel/image.itb
273 00:22:29.665033 output: FIT description: Kernel Image image with one or more FDT blobs
274 00:22:29.665171 output: Created: Fri Jun 21 01:22:29 2024
275 00:22:29.665233 output: Image 0 (kernel-1)
276 00:22:29.665288 output: Description:
277 00:22:29.665343 output: Created: Fri Jun 21 01:22:29 2024
278 00:22:29.665395 output: Type: Kernel Image
279 00:22:29.665445 output: Compression: lzma compressed
280 00:22:29.665499 output: Data Size: 13124896 Bytes = 12817.28 KiB = 12.52 MiB
281 00:22:29.665550 output: Architecture: AArch64
282 00:22:29.665599 output: OS: Linux
283 00:22:29.665648 output: Load Address: 0x00000000
284 00:22:29.665700 output: Entry Point: 0x00000000
285 00:22:29.665750 output: Hash algo: crc32
286 00:22:29.665805 output: Hash value: ab2f7826
287 00:22:29.665858 output: Image 1 (fdt-1)
288 00:22:29.665914 output: Description: mt8192-asurada-spherion-r0
289 00:22:29.665998 output: Created: Fri Jun 21 01:22:29 2024
290 00:22:29.666055 output: Type: Flat Device Tree
291 00:22:29.666111 output: Compression: uncompressed
292 00:22:29.666166 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
293 00:22:29.666248 output: Architecture: AArch64
294 00:22:29.666345 output: Hash algo: crc32
295 00:22:29.666397 output: Hash value: 0f8e4d2e
296 00:22:29.666451 output: Image 2 (ramdisk-1)
297 00:22:29.666502 output: Description: unavailable
298 00:22:29.666550 output: Created: Fri Jun 21 01:22:29 2024
299 00:22:29.666601 output: Type: RAMDisk Image
300 00:22:29.666670 output: Compression: uncompressed
301 00:22:29.666720 output: Data Size: 18745975 Bytes = 18306.62 KiB = 17.88 MiB
302 00:22:29.666768 output: Architecture: AArch64
303 00:22:29.666816 output: OS: Linux
304 00:22:29.666865 output: Load Address: unavailable
305 00:22:29.666913 output: Entry Point: unavailable
306 00:22:29.666960 output: Hash algo: crc32
307 00:22:29.667007 output: Hash value: d6e850d4
308 00:22:29.667054 output: Default Configuration: 'conf-1'
309 00:22:29.667101 output: Configuration 0 (conf-1)
310 00:22:29.667149 output: Description: mt8192-asurada-spherion-r0
311 00:22:29.667197 output: Kernel: kernel-1
312 00:22:29.667244 output: Init Ramdisk: ramdisk-1
313 00:22:29.667291 output: FDT: fdt-1
314 00:22:29.667339 output: Loadables: kernel-1
315 00:22:29.667386 output:
316 00:22:29.667525 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
317 00:22:29.667619 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
318 00:22:29.667710 end: 1.6 prepare-tftp-overlay (duration 00:00:31) [common]
319 00:22:29.667793 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:18) [common]
320 00:22:29.667858 No LXC device requested
321 00:22:29.667928 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 00:22:29.668005 start: 1.8 deploy-device-env (timeout 00:09:18) [common]
323 00:22:29.668074 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 00:22:29.668134 Checking files for TFTP limit of 4294967296 bytes.
325 00:22:29.668567 end: 1 tftp-deploy (duration 00:00:42) [common]
326 00:22:29.668669 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 00:22:29.668752 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 00:22:29.668859 substitutions:
329 00:22:29.668920 - {DTB}: 14479179/tftp-deploy-4yfo8uu6/dtb/mt8192-asurada-spherion-r0.dtb
330 00:22:29.668976 - {INITRD}: 14479179/tftp-deploy-4yfo8uu6/ramdisk/ramdisk.cpio.gz
331 00:22:29.669029 - {KERNEL}: 14479179/tftp-deploy-4yfo8uu6/kernel/Image
332 00:22:29.669080 - {LAVA_MAC}: None
333 00:22:29.669132 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14479179/extract-nfsrootfs-6gqy51jo
334 00:22:29.669182 - {NFS_SERVER_IP}: 192.168.201.1
335 00:22:29.669231 - {PRESEED_CONFIG}: None
336 00:22:29.669285 - {PRESEED_LOCAL}: None
337 00:22:29.669333 - {RAMDISK}: 14479179/tftp-deploy-4yfo8uu6/ramdisk/ramdisk.cpio.gz
338 00:22:29.669382 - {ROOT_PART}: None
339 00:22:29.669430 - {ROOT}: None
340 00:22:29.669479 - {SERVER_IP}: 192.168.201.1
341 00:22:29.669526 - {TEE}: None
342 00:22:29.669574 Parsed boot commands:
343 00:22:29.669622 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 00:22:29.669764 Parsed boot commands: tftpboot 192.168.201.1 14479179/tftp-deploy-4yfo8uu6/kernel/image.itb 14479179/tftp-deploy-4yfo8uu6/kernel/cmdline
345 00:22:29.669846 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 00:22:29.669944 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 00:22:29.670037 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 00:22:29.670115 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 00:22:29.670174 Not connected, no need to disconnect.
350 00:22:29.670267 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 00:22:29.670363 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 00:22:29.670424 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
353 00:22:29.673286 Setting prompt string to ['lava-test: # ']
354 00:22:29.673597 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 00:22:29.673693 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 00:22:29.673783 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 00:22:29.673914 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 00:22:29.674207 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-4', '--port=1', '--command=reboot']
359 00:22:38.855901 >> Command sent successfully.
360 00:22:38.872094 Returned 0 in 9 seconds
361 00:22:38.973308 end: 2.2.2.1 pdu-reboot (duration 00:00:09) [common]
363 00:22:38.974669 end: 2.2.2 reset-device (duration 00:00:09) [common]
364 00:22:38.975176 start: 2.2.3 depthcharge-start (timeout 00:04:51) [common]
365 00:22:38.975635 Setting prompt string to 'Starting depthcharge on Spherion...'
366 00:22:38.975977 Changing prompt to 'Starting depthcharge on Spherion...'
367 00:22:38.976317 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 00:22:38.978045 [Enter `^Ec?' for help]
369 00:22:40.131648 T_CASE_ID=UnbalancedStop/VideoRe
370 00:22:40.132162 F0: 102B 0000
371 00:22:40.132524
372 00:22:40.134812 F3: 1001 0000 [0200]
373 00:22:40.135269
374 00:22:40.135626 F3: 1001 0000
375 00:22:40.135962
376 00:22:40.136293 F7: 102D 0000
377 00:22:40.136615
378 00:22:40.137861 F1: 0000 0000
379 00:22:40.138357
380 00:22:40.138734 V0: 0000 0000 [0001]
381 00:22:40.139165
382 00:22:40.142018 00: 0007 8000
383 00:22:40.142621
384 00:22:40.142972 01: 0000 0000
385 00:22:40.143291
386 00:22:40.144911 BP: 0C00 0209 [0000]
387 00:22:40.145345
388 00:22:40.145669 G0: 1182 0000
389 00:22:40.145969
390 00:22:40.148214 EC: 0000 0021 [4000]
391 00:22:40.148866
392 00:22:40.149224 S7: 0000 0000 [0000]
393 00:22:40.149538
394 00:22:40.151575 CC: 0000 0000 [0001]
395 00:22:40.152110
396 00:22:40.152447 T0: 0000 0040 [010F]
397 00:22:40.152755
398 00:22:40.154323 Jump to BL
399 00:22:40.154753
400 00:22:40.178281
401 00:22:40.178796
402 00:22:40.188514 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
403 00:22:40.191776 ARM64: Exception handlers installed.
404 00:22:40.192230 ARM64: Testing exception
405 00:22:40.194771 ARM64: Done test exception
406 00:22:40.201892 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
407 00:22:40.211896 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
408 00:22:40.218436 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
409 00:22:40.229281 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
410 00:22:40.236124 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
411 00:22:40.246198 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
412 00:22:40.256101 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
413 00:22:40.262942 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
414 00:22:40.281301 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
415 00:22:40.284698 WDT: Last reset was cold boot
416 00:22:40.288091 SPI1(PAD0) initialized at 2873684 Hz
417 00:22:40.291739 SPI5(PAD0) initialized at 992727 Hz
418 00:22:40.294580 VBOOT: Loading verstage.
419 00:22:40.301200 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
420 00:22:40.305165 FMAP: Found "FLASH" version 1.1 at 0x20000.
421 00:22:40.307681 FMAP: base = 0x0 size = 0x800000 #areas = 25
422 00:22:40.310927 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
423 00:22:40.318726 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
424 00:22:40.325376 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
425 00:22:40.336508 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
426 00:22:40.337037
427 00:22:40.337370
428 00:22:40.346809 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
429 00:22:40.349604 ARM64: Exception handlers installed.
430 00:22:40.353109 ARM64: Testing exception
431 00:22:40.353631 ARM64: Done test exception
432 00:22:40.359967 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
433 00:22:40.363106 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
434 00:22:40.377754 Probing TPM: . done!
435 00:22:40.378341 TPM ready after 0 ms
436 00:22:40.384536 Connected to device vid:did:rid of 1ae0:0028:00
437 00:22:40.390929 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
438 00:22:40.430169 Initialized TPM device CR50 revision 0
439 00:22:40.441848 tlcl_send_startup: Startup return code is 0
440 00:22:40.442409 TPM: setup succeeded
441 00:22:40.452908 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
442 00:22:40.461862 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
443 00:22:40.471585 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
444 00:22:40.481205 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 00:22:40.484053 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
446 00:22:40.487111 in-header: 03 07 00 00 08 00 00 00
447 00:22:40.491264 in-data: aa e4 47 04 13 02 00 00
448 00:22:40.494514 Chrome EC: UHEPI supported
449 00:22:40.500949 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
450 00:22:40.504046 in-header: 03 a9 00 00 08 00 00 00
451 00:22:40.507312 in-data: 84 60 60 08 00 00 00 00
452 00:22:40.507949 Phase 1
453 00:22:40.510443 FMAP: area GBB found @ 3f5000 (12032 bytes)
454 00:22:40.517087 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
455 00:22:40.523875 VB2:vb2_check_recovery() Recovery was requested manually
456 00:22:40.530559 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
457 00:22:40.530994 Recovery requested (1009000e)
458 00:22:40.538965 TPM: Extending digest for VBOOT: boot mode into PCR 0
459 00:22:40.545182 tlcl_extend: response is 0
460 00:22:40.555207 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
461 00:22:40.558859 tlcl_extend: response is 0
462 00:22:40.565763 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
463 00:22:40.585976 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
464 00:22:40.592180 BS: bootblock times (exec / console): total (unknown) / 148 ms
465 00:22:40.592729
466 00:22:40.593068
467 00:22:40.602170 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
468 00:22:40.605724 ARM64: Exception handlers installed.
469 00:22:40.609063 ARM64: Testing exception
470 00:22:40.609576 ARM64: Done test exception
471 00:22:40.631448 pmic_efuse_setting: Set efuses in 11 msecs
472 00:22:40.634953 pmwrap_interface_init: Select PMIF_VLD_RDY
473 00:22:40.641077 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
474 00:22:40.644513 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
475 00:22:40.651351 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
476 00:22:40.654636 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
477 00:22:40.661254 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
478 00:22:40.664845 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
479 00:22:40.667720 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
480 00:22:40.674818 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
481 00:22:40.677823 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
482 00:22:40.685238 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
483 00:22:40.687891 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
484 00:22:40.691140 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
485 00:22:40.698257 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
486 00:22:40.704781 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
487 00:22:40.708414 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
488 00:22:40.715100 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
489 00:22:40.721239 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
490 00:22:40.724413 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
491 00:22:40.731508 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
492 00:22:40.737620 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
493 00:22:40.741328 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
494 00:22:40.748173 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
495 00:22:40.754502 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
496 00:22:40.758056 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
497 00:22:40.765033 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
498 00:22:40.771017 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
499 00:22:40.774445 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
500 00:22:40.781572 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
501 00:22:40.784512 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
502 00:22:40.791257 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
503 00:22:40.794807 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
504 00:22:40.801279 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
505 00:22:40.804511 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
506 00:22:40.811983 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
507 00:22:40.814624 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
508 00:22:40.821195 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
509 00:22:40.824816 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
510 00:22:40.832029 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
511 00:22:40.835217 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
512 00:22:40.838820 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
513 00:22:40.842201 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
514 00:22:40.848779 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
515 00:22:40.852019 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
516 00:22:40.855414 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
517 00:22:40.862004 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
518 00:22:40.865199 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
519 00:22:40.868794 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
520 00:22:40.871822 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
521 00:22:40.878854 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
522 00:22:40.882327 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
523 00:22:40.885154 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
524 00:22:40.895165 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
525 00:22:40.902200 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
526 00:22:40.905467 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
527 00:22:40.915632 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
528 00:22:40.922076 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
529 00:22:40.928863 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
530 00:22:40.931981 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
531 00:22:40.935586 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 00:22:40.943688 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x38
533 00:22:40.950722 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
534 00:22:40.954102 [RTC]rtc_osc_init,62: osc32con val = 0xde70
535 00:22:40.960186 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
536 00:22:40.968556 [RTC]rtc_get_frequency_meter,154: input=15, output=765
537 00:22:40.977526 [RTC]rtc_get_frequency_meter,154: input=23, output=950
538 00:22:40.987212 [RTC]rtc_get_frequency_meter,154: input=19, output=856
539 00:22:40.997122 [RTC]rtc_get_frequency_meter,154: input=17, output=811
540 00:22:41.006252 [RTC]rtc_get_frequency_meter,154: input=16, output=788
541 00:22:41.015944 [RTC]rtc_get_frequency_meter,154: input=16, output=788
542 00:22:41.025785 [RTC]rtc_get_frequency_meter,154: input=17, output=811
543 00:22:41.029104 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
544 00:22:41.036001 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
545 00:22:41.038968 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
546 00:22:41.042456 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
547 00:22:41.049523 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
548 00:22:41.052672 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
549 00:22:41.055712 ADC[4]: Raw value=670432 ID=5
550 00:22:41.056184 ADC[3]: Raw value=212549 ID=1
551 00:22:41.059037 RAM Code: 0x51
552 00:22:41.062278 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
553 00:22:41.069147 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
554 00:22:41.076140 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
555 00:22:41.082257 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
556 00:22:41.086664 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
557 00:22:41.089712 in-header: 03 07 00 00 08 00 00 00
558 00:22:41.092575 in-data: aa e4 47 04 13 02 00 00
559 00:22:41.095558 Chrome EC: UHEPI supported
560 00:22:41.102597 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
561 00:22:41.105749 in-header: 03 a9 00 00 08 00 00 00
562 00:22:41.109107 in-data: 84 60 60 08 00 00 00 00
563 00:22:41.112074 MRC: failed to locate region type 0.
564 00:22:41.116131 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
565 00:22:41.118869 DRAM-K: Running full calibration
566 00:22:41.125588 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
567 00:22:41.129316 header.status = 0x0
568 00:22:41.132442 header.version = 0x6 (expected: 0x6)
569 00:22:41.136121 header.size = 0xd00 (expected: 0xd00)
570 00:22:41.136653 header.flags = 0x0
571 00:22:41.142476 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
572 00:22:41.160386 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
573 00:22:41.167103 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
574 00:22:41.170372 dram_init: ddr_geometry: 0
575 00:22:41.173843 [EMI] MDL number = 0
576 00:22:41.174413 [EMI] Get MDL freq = 0
577 00:22:41.176944 dram_init: ddr_type: 0
578 00:22:41.177480 is_discrete_lpddr4: 1
579 00:22:41.180304 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
580 00:22:41.180750
581 00:22:41.181185
582 00:22:41.183644 [Bian_co] ETT version 0.0.0.1
583 00:22:41.190251 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
584 00:22:41.190798
585 00:22:41.193595 dramc_set_vcore_voltage set vcore to 650000
586 00:22:41.197009 Read voltage for 800, 4
587 00:22:41.197536 Vio18 = 0
588 00:22:41.197981 Vcore = 650000
589 00:22:41.198481 Vdram = 0
590 00:22:41.200019 Vddq = 0
591 00:22:41.200466 Vmddr = 0
592 00:22:41.203823 dram_init: config_dvfs: 1
593 00:22:41.206829 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
594 00:22:41.213822 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
595 00:22:41.216601 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
596 00:22:41.220055 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
597 00:22:41.223184 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
598 00:22:41.226571 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
599 00:22:41.230524 MEM_TYPE=3, freq_sel=18
600 00:22:41.233168 sv_algorithm_assistance_LP4_1600
601 00:22:41.236816 ============ PULL DRAM RESETB DOWN ============
602 00:22:41.243359 ========== PULL DRAM RESETB DOWN end =========
603 00:22:41.246675 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
604 00:22:41.250012 ===================================
605 00:22:41.253226 LPDDR4 DRAM CONFIGURATION
606 00:22:41.256585 ===================================
607 00:22:41.257112 EX_ROW_EN[0] = 0x0
608 00:22:41.259721 EX_ROW_EN[1] = 0x0
609 00:22:41.260259 LP4Y_EN = 0x0
610 00:22:41.263105 WORK_FSP = 0x0
611 00:22:41.263555 WL = 0x2
612 00:22:41.266866 RL = 0x2
613 00:22:41.267486 BL = 0x2
614 00:22:41.269582 RPST = 0x0
615 00:22:41.270029 RD_PRE = 0x0
616 00:22:41.273799 WR_PRE = 0x1
617 00:22:41.274378 WR_PST = 0x0
618 00:22:41.276269 DBI_WR = 0x0
619 00:22:41.276718 DBI_RD = 0x0
620 00:22:41.279859 OTF = 0x1
621 00:22:41.283328 ===================================
622 00:22:41.286752 ===================================
623 00:22:41.287199 ANA top config
624 00:22:41.289997 ===================================
625 00:22:41.293521 DLL_ASYNC_EN = 0
626 00:22:41.296354 ALL_SLAVE_EN = 1
627 00:22:41.299741 NEW_RANK_MODE = 1
628 00:22:41.300292 DLL_IDLE_MODE = 1
629 00:22:41.303257 LP45_APHY_COMB_EN = 1
630 00:22:41.306332 TX_ODT_DIS = 1
631 00:22:41.310256 NEW_8X_MODE = 1
632 00:22:41.313717 ===================================
633 00:22:41.316366 ===================================
634 00:22:41.320007 data_rate = 1600
635 00:22:41.320545 CKR = 1
636 00:22:41.323214 DQ_P2S_RATIO = 8
637 00:22:41.326779 ===================================
638 00:22:41.329894 CA_P2S_RATIO = 8
639 00:22:41.333209 DQ_CA_OPEN = 0
640 00:22:41.336547 DQ_SEMI_OPEN = 0
641 00:22:41.339575 CA_SEMI_OPEN = 0
642 00:22:41.340008 CA_FULL_RATE = 0
643 00:22:41.343372 DQ_CKDIV4_EN = 1
644 00:22:41.346663 CA_CKDIV4_EN = 1
645 00:22:41.350376 CA_PREDIV_EN = 0
646 00:22:41.353655 PH8_DLY = 0
647 00:22:41.356365 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
648 00:22:41.356796 DQ_AAMCK_DIV = 4
649 00:22:41.359750 CA_AAMCK_DIV = 4
650 00:22:41.363076 CA_ADMCK_DIV = 4
651 00:22:41.366613 DQ_TRACK_CA_EN = 0
652 00:22:41.369883 CA_PICK = 800
653 00:22:41.373363 CA_MCKIO = 800
654 00:22:41.373794 MCKIO_SEMI = 0
655 00:22:41.376846 PLL_FREQ = 3068
656 00:22:41.380513 DQ_UI_PI_RATIO = 32
657 00:22:41.383445 CA_UI_PI_RATIO = 0
658 00:22:41.386423 ===================================
659 00:22:41.390138 ===================================
660 00:22:41.393785 memory_type:LPDDR4
661 00:22:41.394391 GP_NUM : 10
662 00:22:41.396812 SRAM_EN : 1
663 00:22:41.399724 MD32_EN : 0
664 00:22:41.400156 ===================================
665 00:22:41.403512 [ANA_INIT] >>>>>>>>>>>>>>
666 00:22:41.406772 <<<<<< [CONFIGURE PHASE]: ANA_TX
667 00:22:41.410278 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
668 00:22:41.413523 ===================================
669 00:22:41.416804 data_rate = 1600,PCW = 0X7600
670 00:22:41.420151 ===================================
671 00:22:41.423484 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
672 00:22:41.429908 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
673 00:22:41.433640 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 00:22:41.440282 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
675 00:22:41.444209 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
676 00:22:41.446607 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
677 00:22:41.447059 [ANA_INIT] flow start
678 00:22:41.450008 [ANA_INIT] PLL >>>>>>>>
679 00:22:41.453893 [ANA_INIT] PLL <<<<<<<<
680 00:22:41.454462 [ANA_INIT] MIDPI >>>>>>>>
681 00:22:41.456550 [ANA_INIT] MIDPI <<<<<<<<
682 00:22:41.460118 [ANA_INIT] DLL >>>>>>>>
683 00:22:41.460715 [ANA_INIT] flow end
684 00:22:41.466497 ============ LP4 DIFF to SE enter ============
685 00:22:41.469990 ============ LP4 DIFF to SE exit ============
686 00:22:41.470506 [ANA_INIT] <<<<<<<<<<<<<
687 00:22:41.473233 [Flow] Enable top DCM control >>>>>
688 00:22:41.476725 [Flow] Enable top DCM control <<<<<
689 00:22:41.480311 Enable DLL master slave shuffle
690 00:22:41.486940 ==============================================================
691 00:22:41.490394 Gating Mode config
692 00:22:41.493374 ==============================================================
693 00:22:41.496919 Config description:
694 00:22:41.506833 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
695 00:22:41.513851 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
696 00:22:41.516553 SELPH_MODE 0: By rank 1: By Phase
697 00:22:41.523263 ==============================================================
698 00:22:41.526970 GAT_TRACK_EN = 1
699 00:22:41.530643 RX_GATING_MODE = 2
700 00:22:41.531158 RX_GATING_TRACK_MODE = 2
701 00:22:41.533465 SELPH_MODE = 1
702 00:22:41.537088 PICG_EARLY_EN = 1
703 00:22:41.540018 VALID_LAT_VALUE = 1
704 00:22:41.546836 ==============================================================
705 00:22:41.549903 Enter into Gating configuration >>>>
706 00:22:41.553621 Exit from Gating configuration <<<<
707 00:22:41.557137 Enter into DVFS_PRE_config >>>>>
708 00:22:41.566923 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
709 00:22:41.570411 Exit from DVFS_PRE_config <<<<<
710 00:22:41.573395 Enter into PICG configuration >>>>
711 00:22:41.576686 Exit from PICG configuration <<<<
712 00:22:41.579945 [RX_INPUT] configuration >>>>>
713 00:22:41.583383 [RX_INPUT] configuration <<<<<
714 00:22:41.586321 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
715 00:22:41.593369 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
716 00:22:41.600195 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
717 00:22:41.603345 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
718 00:22:41.610135 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
719 00:22:41.616787 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
720 00:22:41.619690 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
721 00:22:41.626386 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
722 00:22:41.629647 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
723 00:22:41.633281 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
724 00:22:41.636445 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
725 00:22:41.642988 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
726 00:22:41.646625 ===================================
727 00:22:41.647165 LPDDR4 DRAM CONFIGURATION
728 00:22:41.649887 ===================================
729 00:22:41.652931 EX_ROW_EN[0] = 0x0
730 00:22:41.656153 EX_ROW_EN[1] = 0x0
731 00:22:41.656680 LP4Y_EN = 0x0
732 00:22:41.659831 WORK_FSP = 0x0
733 00:22:41.660356 WL = 0x2
734 00:22:41.662928 RL = 0x2
735 00:22:41.663363 BL = 0x2
736 00:22:41.666337 RPST = 0x0
737 00:22:41.666850 RD_PRE = 0x0
738 00:22:41.669505 WR_PRE = 0x1
739 00:22:41.669934 WR_PST = 0x0
740 00:22:41.673042 DBI_WR = 0x0
741 00:22:41.673613 DBI_RD = 0x0
742 00:22:41.676564 OTF = 0x1
743 00:22:41.679736 ===================================
744 00:22:41.682797 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
745 00:22:41.686063 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
746 00:22:41.692964 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
747 00:22:41.696005 ===================================
748 00:22:41.696438 LPDDR4 DRAM CONFIGURATION
749 00:22:41.699539 ===================================
750 00:22:41.702680 EX_ROW_EN[0] = 0x10
751 00:22:41.706334 EX_ROW_EN[1] = 0x0
752 00:22:41.706874 LP4Y_EN = 0x0
753 00:22:41.709576 WORK_FSP = 0x0
754 00:22:41.710107 WL = 0x2
755 00:22:41.712844 RL = 0x2
756 00:22:41.713272 BL = 0x2
757 00:22:41.716215 RPST = 0x0
758 00:22:41.716646 RD_PRE = 0x0
759 00:22:41.719141 WR_PRE = 0x1
760 00:22:41.719575 WR_PST = 0x0
761 00:22:41.723319 DBI_WR = 0x0
762 00:22:41.723836 DBI_RD = 0x0
763 00:22:41.726156 OTF = 0x1
764 00:22:41.729357 ===================================
765 00:22:41.736145 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
766 00:22:41.739204 nWR fixed to 40
767 00:22:41.739730 [ModeRegInit_LP4] CH0 RK0
768 00:22:41.743062 [ModeRegInit_LP4] CH0 RK1
769 00:22:41.746467 [ModeRegInit_LP4] CH1 RK0
770 00:22:41.749064 [ModeRegInit_LP4] CH1 RK1
771 00:22:41.749500 match AC timing 12
772 00:22:41.753012 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
773 00:22:41.759450 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
774 00:22:41.762850 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
775 00:22:41.766014 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
776 00:22:41.772588 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
777 00:22:41.773118 [EMI DOE] emi_dcm 0
778 00:22:41.779129 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
779 00:22:41.779574 ==
780 00:22:41.782676 Dram Type= 6, Freq= 0, CH_0, rank 0
781 00:22:41.785968 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
782 00:22:41.786557 ==
783 00:22:41.789070 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
784 00:22:41.796094 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
785 00:22:41.805947 [CA 0] Center 37 (7~68) winsize 62
786 00:22:41.809284 [CA 1] Center 37 (6~68) winsize 63
787 00:22:41.812391 [CA 2] Center 35 (5~66) winsize 62
788 00:22:41.815794 [CA 3] Center 35 (5~66) winsize 62
789 00:22:41.819088 [CA 4] Center 34 (4~65) winsize 62
790 00:22:41.823141 [CA 5] Center 34 (4~65) winsize 62
791 00:22:41.823656
792 00:22:41.825638 [CmdBusTrainingLP45] Vref(ca) range 1: 34
793 00:22:41.826073
794 00:22:41.829242 [CATrainingPosCal] consider 1 rank data
795 00:22:41.832542 u2DelayCellTimex100 = 270/100 ps
796 00:22:41.836400 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
797 00:22:41.840265 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
798 00:22:41.842843 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
799 00:22:41.846753 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
800 00:22:41.852809 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
801 00:22:41.855994 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
802 00:22:41.856432
803 00:22:41.859497 CA PerBit enable=1, Macro0, CA PI delay=34
804 00:22:41.859934
805 00:22:41.862744 [CBTSetCACLKResult] CA Dly = 34
806 00:22:41.863180 CS Dly: 5 (0~36)
807 00:22:41.863521 ==
808 00:22:41.866443 Dram Type= 6, Freq= 0, CH_0, rank 1
809 00:22:41.872680 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
810 00:22:41.873121 ==
811 00:22:41.876146 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
812 00:22:41.882721 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
813 00:22:41.891530 [CA 0] Center 37 (7~68) winsize 62
814 00:22:41.894722 [CA 1] Center 37 (6~68) winsize 63
815 00:22:41.898429 [CA 2] Center 35 (4~66) winsize 63
816 00:22:41.901707 [CA 3] Center 34 (4~65) winsize 62
817 00:22:41.905768 [CA 4] Center 33 (3~64) winsize 62
818 00:22:41.908777 [CA 5] Center 33 (3~64) winsize 62
819 00:22:41.909300
820 00:22:41.911725 [CmdBusTrainingLP45] Vref(ca) range 1: 30
821 00:22:41.912203
822 00:22:41.915080 [CATrainingPosCal] consider 2 rank data
823 00:22:41.918330 u2DelayCellTimex100 = 270/100 ps
824 00:22:41.921441 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
825 00:22:41.924948 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
826 00:22:41.931807 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
827 00:22:41.934607 CA3 delay=35 (5~65),Diff = 1 PI (7 cell)
828 00:22:41.938719 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
829 00:22:41.941989 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
830 00:22:41.942588
831 00:22:41.944921 CA PerBit enable=1, Macro0, CA PI delay=34
832 00:22:41.945392
833 00:22:41.948255 [CBTSetCACLKResult] CA Dly = 34
834 00:22:41.948785 CS Dly: 6 (0~38)
835 00:22:41.949139
836 00:22:41.951600 ----->DramcWriteLeveling(PI) begin...
837 00:22:41.955134 ==
838 00:22:41.955662 Dram Type= 6, Freq= 0, CH_0, rank 0
839 00:22:41.961918 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
840 00:22:41.962525 ==
841 00:22:41.965747 Write leveling (Byte 0): 32 => 32
842 00:22:41.968432 Write leveling (Byte 1): 32 => 32
843 00:22:41.971551 DramcWriteLeveling(PI) end<-----
844 00:22:41.971991
845 00:22:41.972326 ==
846 00:22:41.975348 Dram Type= 6, Freq= 0, CH_0, rank 0
847 00:22:41.978362 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
848 00:22:41.978892 ==
849 00:22:41.981781 [Gating] SW mode calibration
850 00:22:41.988708 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
851 00:22:41.991412 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
852 00:22:41.998575 0 6 0 | B1->B0 | 3232 3030 | 0 1 | (0 0) (1 0)
853 00:22:42.001530 0 6 4 | B1->B0 | 2b2b 2424 | 1 0 | (1 0) (0 0)
854 00:22:42.004925 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 00:22:42.011449 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 00:22:42.014875 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 00:22:42.018105 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 00:22:42.024981 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 00:22:42.028213 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 00:22:42.031627 0 7 0 | B1->B0 | 2626 2b2b | 0 1 | (0 0) (0 0)
861 00:22:42.038352 0 7 4 | B1->B0 | 3838 4141 | 0 0 | (0 0) (0 0)
862 00:22:42.041676 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
863 00:22:42.044935 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
864 00:22:42.051439 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
865 00:22:42.054828 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
866 00:22:42.058482 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
867 00:22:42.065106 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
868 00:22:42.068305 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
869 00:22:42.071835 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
870 00:22:42.075224 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
871 00:22:42.081856 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
872 00:22:42.085371 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
873 00:22:42.088211 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
874 00:22:42.095082 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
875 00:22:42.098399 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 00:22:42.101387 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 00:22:42.109221 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 00:22:42.111975 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 00:22:42.114681 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 00:22:42.121873 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 00:22:42.125010 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 00:22:42.128217 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 00:22:42.134877 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 00:22:42.138166 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
885 00:22:42.142092 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
886 00:22:42.144901 Total UI for P1: 0, mck2ui 16
887 00:22:42.148766 best dqsien dly found for B0: ( 0, 10, 0)
888 00:22:42.151781 Total UI for P1: 0, mck2ui 16
889 00:22:42.155099 best dqsien dly found for B1: ( 0, 10, 0)
890 00:22:42.158638 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
891 00:22:42.161600 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
892 00:22:42.162037
893 00:22:42.164941 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
894 00:22:42.171857 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
895 00:22:42.172295 [Gating] SW calibration Done
896 00:22:42.172636 ==
897 00:22:42.174798 Dram Type= 6, Freq= 0, CH_0, rank 0
898 00:22:42.181797 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
899 00:22:42.182379 ==
900 00:22:42.182730 RX Vref Scan: 0
901 00:22:42.183047
902 00:22:42.185136 RX Vref 0 -> 0, step: 1
903 00:22:42.185656
904 00:22:42.188287 RX Delay -130 -> 252, step: 16
905 00:22:42.191931 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
906 00:22:42.195210 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
907 00:22:42.198545 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
908 00:22:42.205464 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
909 00:22:42.208377 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
910 00:22:42.211717 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
911 00:22:42.215396 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
912 00:22:42.217955 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
913 00:22:42.221953 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
914 00:22:42.228352 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
915 00:22:42.232089 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
916 00:22:42.235309 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
917 00:22:42.238553 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
918 00:22:42.241796 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
919 00:22:42.248646 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
920 00:22:42.252238 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
921 00:22:42.252643 ==
922 00:22:42.255033 Dram Type= 6, Freq= 0, CH_0, rank 0
923 00:22:42.258623 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
924 00:22:42.259046 ==
925 00:22:42.261812 DQS Delay:
926 00:22:42.262207 DQS0 = 0, DQS1 = 0
927 00:22:42.262574 DQM Delay:
928 00:22:42.264994 DQM0 = 82, DQM1 = 73
929 00:22:42.265390 DQ Delay:
930 00:22:42.268342 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
931 00:22:42.271678 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
932 00:22:42.275229 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
933 00:22:42.278263 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
934 00:22:42.278664
935 00:22:42.278974
936 00:22:42.279261 ==
937 00:22:42.281612 Dram Type= 6, Freq= 0, CH_0, rank 0
938 00:22:42.288486 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
939 00:22:42.288893 ==
940 00:22:42.289202
941 00:22:42.289486
942 00:22:42.289762 TX Vref Scan disable
943 00:22:42.291907 == TX Byte 0 ==
944 00:22:42.295009 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
945 00:22:42.301721 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
946 00:22:42.302123 == TX Byte 1 ==
947 00:22:42.305013 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
948 00:22:42.311916 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
949 00:22:42.312451 ==
950 00:22:42.315090 Dram Type= 6, Freq= 0, CH_0, rank 0
951 00:22:42.318339 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
952 00:22:42.318745 ==
953 00:22:42.330966 TX Vref=22, minBit 5, minWin=27, winSum=446
954 00:22:42.334352 TX Vref=24, minBit 5, minWin=27, winSum=451
955 00:22:42.337722 TX Vref=26, minBit 5, minWin=27, winSum=454
956 00:22:42.341477 TX Vref=28, minBit 4, minWin=28, winSum=459
957 00:22:42.344233 TX Vref=30, minBit 0, minWin=28, winSum=458
958 00:22:42.347851 TX Vref=32, minBit 0, minWin=28, winSum=453
959 00:22:42.354269 [TxChooseVref] Worse bit 4, Min win 28, Win sum 459, Final Vref 28
960 00:22:42.354802
961 00:22:42.357417 Final TX Range 1 Vref 28
962 00:22:42.357940
963 00:22:42.358332 ==
964 00:22:42.360727 Dram Type= 6, Freq= 0, CH_0, rank 0
965 00:22:42.363840 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
966 00:22:42.364299 ==
967 00:22:42.364644
968 00:22:42.367563
969 00:22:42.368083 TX Vref Scan disable
970 00:22:42.370725 == TX Byte 0 ==
971 00:22:42.374187 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
972 00:22:42.377390 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
973 00:22:42.380726 == TX Byte 1 ==
974 00:22:42.383991 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
975 00:22:42.387435 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
976 00:22:42.390603
977 00:22:42.391040 [DATLAT]
978 00:22:42.391382 Freq=800, CH0 RK0
979 00:22:42.391701
980 00:22:42.394478 DATLAT Default: 0xa
981 00:22:42.395006 0, 0xFFFF, sum = 0
982 00:22:42.397338 1, 0xFFFF, sum = 0
983 00:22:42.397873 2, 0xFFFF, sum = 0
984 00:22:42.400472 3, 0xFFFF, sum = 0
985 00:22:42.400941 4, 0xFFFF, sum = 0
986 00:22:42.403748 5, 0xFFFF, sum = 0
987 00:22:42.407471 6, 0xFFFF, sum = 0
988 00:22:42.407865 7, 0xFFFF, sum = 0
989 00:22:42.408200 8, 0x0, sum = 1
990 00:22:42.410795 9, 0x0, sum = 2
991 00:22:42.411236 10, 0x0, sum = 3
992 00:22:42.414386 11, 0x0, sum = 4
993 00:22:42.414906 best_step = 9
994 00:22:42.415248
995 00:22:42.415557 ==
996 00:22:42.417504 Dram Type= 6, Freq= 0, CH_0, rank 0
997 00:22:42.424013 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
998 00:22:42.424458 ==
999 00:22:42.424796 RX Vref Scan: 1
1000 00:22:42.425189
1001 00:22:42.427177 Set Vref Range= 32 -> 127
1002 00:22:42.427634
1003 00:22:42.430828 RX Vref 32 -> 127, step: 1
1004 00:22:42.431263
1005 00:22:42.433965 RX Delay -111 -> 252, step: 8
1006 00:22:42.434436
1007 00:22:42.434778 Set Vref, RX VrefLevel [Byte0]: 32
1008 00:22:42.437280 [Byte1]: 32
1009 00:22:42.441619
1010 00:22:42.442051 Set Vref, RX VrefLevel [Byte0]: 33
1011 00:22:42.445043 [Byte1]: 33
1012 00:22:42.449502
1013 00:22:42.450019 Set Vref, RX VrefLevel [Byte0]: 34
1014 00:22:42.452682 [Byte1]: 34
1015 00:22:42.457163
1016 00:22:42.457680 Set Vref, RX VrefLevel [Byte0]: 35
1017 00:22:42.460422 [Byte1]: 35
1018 00:22:42.464905
1019 00:22:42.465437 Set Vref, RX VrefLevel [Byte0]: 36
1020 00:22:42.468110 [Byte1]: 36
1021 00:22:42.471947
1022 00:22:42.472384 Set Vref, RX VrefLevel [Byte0]: 37
1023 00:22:42.475353 [Byte1]: 37
1024 00:22:42.479980
1025 00:22:42.480496 Set Vref, RX VrefLevel [Byte0]: 38
1026 00:22:42.483022 [Byte1]: 38
1027 00:22:42.487517
1028 00:22:42.488059 Set Vref, RX VrefLevel [Byte0]: 39
1029 00:22:42.490959 [Byte1]: 39
1030 00:22:42.495208
1031 00:22:42.495746 Set Vref, RX VrefLevel [Byte0]: 40
1032 00:22:42.498507 [Byte1]: 40
1033 00:22:42.503120
1034 00:22:42.503645 Set Vref, RX VrefLevel [Byte0]: 41
1035 00:22:42.506495 [Byte1]: 41
1036 00:22:42.510536
1037 00:22:42.510986 Set Vref, RX VrefLevel [Byte0]: 42
1038 00:22:42.514062 [Byte1]: 42
1039 00:22:42.518119
1040 00:22:42.518684 Set Vref, RX VrefLevel [Byte0]: 43
1041 00:22:42.521587 [Byte1]: 43
1042 00:22:42.525877
1043 00:22:42.526449 Set Vref, RX VrefLevel [Byte0]: 44
1044 00:22:42.529313 [Byte1]: 44
1045 00:22:42.533910
1046 00:22:42.534489 Set Vref, RX VrefLevel [Byte0]: 45
1047 00:22:42.537280 [Byte1]: 45
1048 00:22:42.541365
1049 00:22:42.541891 Set Vref, RX VrefLevel [Byte0]: 46
1050 00:22:42.545092 [Byte1]: 46
1051 00:22:42.548921
1052 00:22:42.549453 Set Vref, RX VrefLevel [Byte0]: 47
1053 00:22:42.552195 [Byte1]: 47
1054 00:22:42.556707
1055 00:22:42.557231 Set Vref, RX VrefLevel [Byte0]: 48
1056 00:22:42.560157 [Byte1]: 48
1057 00:22:42.564390
1058 00:22:42.564932 Set Vref, RX VrefLevel [Byte0]: 49
1059 00:22:42.567205 [Byte1]: 49
1060 00:22:42.571892
1061 00:22:42.572425 Set Vref, RX VrefLevel [Byte0]: 50
1062 00:22:42.575268 [Byte1]: 50
1063 00:22:42.579474
1064 00:22:42.579923 Set Vref, RX VrefLevel [Byte0]: 51
1065 00:22:42.582942 [Byte1]: 51
1066 00:22:42.587056
1067 00:22:42.587582 Set Vref, RX VrefLevel [Byte0]: 52
1068 00:22:42.590186 [Byte1]: 52
1069 00:22:42.594853
1070 00:22:42.595388 Set Vref, RX VrefLevel [Byte0]: 53
1071 00:22:42.597868 [Byte1]: 53
1072 00:22:42.602782
1073 00:22:42.603298 Set Vref, RX VrefLevel [Byte0]: 54
1074 00:22:42.605714 [Byte1]: 54
1075 00:22:42.610261
1076 00:22:42.610785 Set Vref, RX VrefLevel [Byte0]: 55
1077 00:22:42.613300 [Byte1]: 55
1078 00:22:42.617496
1079 00:22:42.618012 Set Vref, RX VrefLevel [Byte0]: 56
1080 00:22:42.620839 [Byte1]: 56
1081 00:22:42.625235
1082 00:22:42.625750 Set Vref, RX VrefLevel [Byte0]: 57
1083 00:22:42.628525 [Byte1]: 57
1084 00:22:42.632730
1085 00:22:42.633238 Set Vref, RX VrefLevel [Byte0]: 58
1086 00:22:42.636190 [Byte1]: 58
1087 00:22:42.640567
1088 00:22:42.640999 Set Vref, RX VrefLevel [Byte0]: 59
1089 00:22:42.643613 [Byte1]: 59
1090 00:22:42.648183
1091 00:22:42.648694 Set Vref, RX VrefLevel [Byte0]: 60
1092 00:22:42.651434 [Byte1]: 60
1093 00:22:42.655892
1094 00:22:42.656396 Set Vref, RX VrefLevel [Byte0]: 61
1095 00:22:42.659369 [Byte1]: 61
1096 00:22:42.663204
1097 00:22:42.663638 Set Vref, RX VrefLevel [Byte0]: 62
1098 00:22:42.666510 [Byte1]: 62
1099 00:22:42.670864
1100 00:22:42.671329 Set Vref, RX VrefLevel [Byte0]: 63
1101 00:22:42.674152 [Byte1]: 63
1102 00:22:42.678899
1103 00:22:42.679328 Set Vref, RX VrefLevel [Byte0]: 64
1104 00:22:42.681684 [Byte1]: 64
1105 00:22:42.686056
1106 00:22:42.686606 Set Vref, RX VrefLevel [Byte0]: 65
1107 00:22:42.689568 [Byte1]: 65
1108 00:22:42.694196
1109 00:22:42.694766 Set Vref, RX VrefLevel [Byte0]: 66
1110 00:22:42.697455 [Byte1]: 66
1111 00:22:42.701680
1112 00:22:42.702246 Set Vref, RX VrefLevel [Byte0]: 67
1113 00:22:42.704614 [Byte1]: 67
1114 00:22:42.708922
1115 00:22:42.709001 Set Vref, RX VrefLevel [Byte0]: 68
1116 00:22:42.711931 [Byte1]: 68
1117 00:22:42.716693
1118 00:22:42.716803 Set Vref, RX VrefLevel [Byte0]: 69
1119 00:22:42.719703 [Byte1]: 69
1120 00:22:42.724035
1121 00:22:42.724137 Set Vref, RX VrefLevel [Byte0]: 70
1122 00:22:42.727230 [Byte1]: 70
1123 00:22:42.731523
1124 00:22:42.731617 Set Vref, RX VrefLevel [Byte0]: 71
1125 00:22:42.734775 [Byte1]: 71
1126 00:22:42.739091
1127 00:22:42.739186 Set Vref, RX VrefLevel [Byte0]: 72
1128 00:22:42.742324 [Byte1]: 72
1129 00:22:42.746912
1130 00:22:42.746985 Set Vref, RX VrefLevel [Byte0]: 73
1131 00:22:42.750148 [Byte1]: 73
1132 00:22:42.754410
1133 00:22:42.754501 Set Vref, RX VrefLevel [Byte0]: 74
1134 00:22:42.757706 [Byte1]: 74
1135 00:22:42.762103
1136 00:22:42.762199 Final RX Vref Byte 0 = 52 to rank0
1137 00:22:42.765467 Final RX Vref Byte 1 = 56 to rank0
1138 00:22:42.768971 Final RX Vref Byte 0 = 52 to rank1
1139 00:22:42.772468 Final RX Vref Byte 1 = 56 to rank1==
1140 00:22:42.775543 Dram Type= 6, Freq= 0, CH_0, rank 0
1141 00:22:42.782073 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1142 00:22:42.782172 ==
1143 00:22:42.782308 DQS Delay:
1144 00:22:42.782367 DQS0 = 0, DQS1 = 0
1145 00:22:42.785559 DQM Delay:
1146 00:22:42.785627 DQM0 = 84, DQM1 = 74
1147 00:22:42.788612 DQ Delay:
1148 00:22:42.792415 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1149 00:22:42.792519 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =92
1150 00:22:42.795739 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1151 00:22:42.802093 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =84
1152 00:22:42.802191
1153 00:22:42.802295
1154 00:22:42.808550 [DQSOSCAuto] RK0, (LSB)MR18= 0x3b3b, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
1155 00:22:42.812043 CH0 RK0: MR19=606, MR18=3B3B
1156 00:22:42.818878 CH0_RK0: MR19=0x606, MR18=0x3B3B, DQSOSC=394, MR23=63, INC=95, DEC=63
1157 00:22:42.818976
1158 00:22:42.822414 ----->DramcWriteLeveling(PI) begin...
1159 00:22:42.822486 ==
1160 00:22:42.825873 Dram Type= 6, Freq= 0, CH_0, rank 1
1161 00:22:42.829219 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1162 00:22:42.829314 ==
1163 00:22:42.832596 Write leveling (Byte 0): 31 => 31
1164 00:22:42.835875 Write leveling (Byte 1): 30 => 30
1165 00:22:42.839038 DramcWriteLeveling(PI) end<-----
1166 00:22:42.839135
1167 00:22:42.839225 ==
1168 00:22:42.842177 Dram Type= 6, Freq= 0, CH_0, rank 1
1169 00:22:42.845745 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1170 00:22:42.845840 ==
1171 00:22:42.848889 [Gating] SW mode calibration
1172 00:22:42.855309 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1173 00:22:42.862056 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1174 00:22:42.865411 0 6 0 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 1)
1175 00:22:42.868762 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 00:22:42.875623 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 00:22:42.878790 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 00:22:42.882101 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 00:22:42.889148 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 00:22:42.892184 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 00:22:42.895615 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 00:22:42.902160 0 7 0 | B1->B0 | 2a2a 2a2a | 0 0 | (0 0) (0 0)
1183 00:22:42.905393 0 7 4 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1184 00:22:42.909140 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1185 00:22:42.915241 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1186 00:22:42.918851 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1187 00:22:42.921943 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1188 00:22:42.925820 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1189 00:22:42.932202 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1190 00:22:42.935562 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1191 00:22:42.938708 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1192 00:22:42.945280 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1193 00:22:42.949211 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1194 00:22:42.952443 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1195 00:22:42.959003 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1196 00:22:42.962496 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1197 00:22:42.965495 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1198 00:22:42.972208 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 00:22:42.975762 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 00:22:42.979369 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 00:22:42.986197 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 00:22:42.989297 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 00:22:42.992502 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 00:22:42.999053 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 00:22:43.002736 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1206 00:22:43.006313 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1207 00:22:43.009850 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1208 00:22:43.012662 Total UI for P1: 0, mck2ui 16
1209 00:22:43.016072 best dqsien dly found for B0: ( 0, 9, 30)
1210 00:22:43.019484 Total UI for P1: 0, mck2ui 16
1211 00:22:43.022697 best dqsien dly found for B1: ( 0, 10, 0)
1212 00:22:43.025842 best DQS0 dly(MCK, UI, PI) = (0, 9, 30)
1213 00:22:43.029546 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1214 00:22:43.033083
1215 00:22:43.036129 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 30)
1216 00:22:43.039558 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1217 00:22:43.042878 [Gating] SW calibration Done
1218 00:22:43.043314 ==
1219 00:22:43.045988 Dram Type= 6, Freq= 0, CH_0, rank 1
1220 00:22:43.049745 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1221 00:22:43.050301 ==
1222 00:22:43.050647 RX Vref Scan: 0
1223 00:22:43.050964
1224 00:22:43.052944 RX Vref 0 -> 0, step: 1
1225 00:22:43.053378
1226 00:22:43.097636 RX Delay -130 -> 252, step: 16
1227 00:22:43.098156 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1228 00:22:43.098556 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1229 00:22:43.099212 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1230 00:22:43.099560 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1231 00:22:43.099863 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1232 00:22:43.100160 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1233 00:22:43.100451 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1234 00:22:43.100736 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1235 00:22:43.101021 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1236 00:22:43.101303 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
1237 00:22:43.122044 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1238 00:22:43.122626 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1239 00:22:43.123313 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1240 00:22:43.123673 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1241 00:22:43.123991 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1242 00:22:43.124347 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1243 00:22:43.124657 ==
1244 00:22:43.125633 Dram Type= 6, Freq= 0, CH_0, rank 1
1245 00:22:43.129559 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1246 00:22:43.130080 ==
1247 00:22:43.130462 DQS Delay:
1248 00:22:43.132693 DQS0 = 0, DQS1 = 0
1249 00:22:43.133206 DQM Delay:
1250 00:22:43.133543 DQM0 = 83, DQM1 = 75
1251 00:22:43.136207 DQ Delay:
1252 00:22:43.139127 DQ0 =77, DQ1 =85, DQ2 =85, DQ3 =77
1253 00:22:43.142690 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1254 00:22:43.146110 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
1255 00:22:43.149183 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1256 00:22:43.149693
1257 00:22:43.150029
1258 00:22:43.150390 ==
1259 00:22:43.152443 Dram Type= 6, Freq= 0, CH_0, rank 1
1260 00:22:43.155815 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1261 00:22:43.156254 ==
1262 00:22:43.156596
1263 00:22:43.156912
1264 00:22:43.159386 TX Vref Scan disable
1265 00:22:43.159821 == TX Byte 0 ==
1266 00:22:43.165913 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1267 00:22:43.169434 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1268 00:22:43.169949 == TX Byte 1 ==
1269 00:22:43.175873 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1270 00:22:43.179030 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1271 00:22:43.179470 ==
1272 00:22:43.182703 Dram Type= 6, Freq= 0, CH_0, rank 1
1273 00:22:43.186059 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1274 00:22:43.186645 ==
1275 00:22:43.199444 TX Vref=22, minBit 7, minWin=27, winSum=448
1276 00:22:43.203238 TX Vref=24, minBit 0, minWin=28, winSum=451
1277 00:22:43.206447 TX Vref=26, minBit 0, minWin=28, winSum=454
1278 00:22:43.209833 TX Vref=28, minBit 4, minWin=28, winSum=460
1279 00:22:43.212786 TX Vref=30, minBit 4, minWin=28, winSum=459
1280 00:22:43.216388 TX Vref=32, minBit 0, minWin=28, winSum=455
1281 00:22:43.222892 [TxChooseVref] Worse bit 4, Min win 28, Win sum 460, Final Vref 28
1282 00:22:43.223377
1283 00:22:43.226493 Final TX Range 1 Vref 28
1284 00:22:43.226927
1285 00:22:43.227264 ==
1286 00:22:43.229564 Dram Type= 6, Freq= 0, CH_0, rank 1
1287 00:22:43.233566 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1288 00:22:43.234083 ==
1289 00:22:43.234465
1290 00:22:43.234776
1291 00:22:43.236619 TX Vref Scan disable
1292 00:22:43.240247 == TX Byte 0 ==
1293 00:22:43.242956 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1294 00:22:43.246627 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1295 00:22:43.250416 == TX Byte 1 ==
1296 00:22:43.253749 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1297 00:22:43.257105 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1298 00:22:43.257672
1299 00:22:43.260050 [DATLAT]
1300 00:22:43.260563 Freq=800, CH0 RK1
1301 00:22:43.260907
1302 00:22:43.263162 DATLAT Default: 0x9
1303 00:22:43.263597 0, 0xFFFF, sum = 0
1304 00:22:43.266626 1, 0xFFFF, sum = 0
1305 00:22:43.267068 2, 0xFFFF, sum = 0
1306 00:22:43.270163 3, 0xFFFF, sum = 0
1307 00:22:43.270641 4, 0xFFFF, sum = 0
1308 00:22:43.273401 5, 0xFFFF, sum = 0
1309 00:22:43.273841 6, 0xFFFF, sum = 0
1310 00:22:43.276717 7, 0xFFFF, sum = 0
1311 00:22:43.277161 8, 0x0, sum = 1
1312 00:22:43.279975 9, 0x0, sum = 2
1313 00:22:43.280416 10, 0x0, sum = 3
1314 00:22:43.283221 11, 0x0, sum = 4
1315 00:22:43.283661 best_step = 9
1316 00:22:43.283997
1317 00:22:43.284307 ==
1318 00:22:43.286765 Dram Type= 6, Freq= 0, CH_0, rank 1
1319 00:22:43.289702 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1320 00:22:43.293488 ==
1321 00:22:43.294001 RX Vref Scan: 0
1322 00:22:43.294387
1323 00:22:43.297042 RX Vref 0 -> 0, step: 1
1324 00:22:43.297560
1325 00:22:43.299991 RX Delay -95 -> 252, step: 8
1326 00:22:43.303078 iDelay=217, Bit 0, Center 80 (-39 ~ 200) 240
1327 00:22:43.306939 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240
1328 00:22:43.309996 iDelay=217, Bit 2, Center 84 (-31 ~ 200) 232
1329 00:22:43.316334 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
1330 00:22:43.320063 iDelay=217, Bit 4, Center 88 (-31 ~ 208) 240
1331 00:22:43.323573 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1332 00:22:43.326415 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1333 00:22:43.330104 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1334 00:22:43.336429 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
1335 00:22:43.339858 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1336 00:22:43.343208 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1337 00:22:43.346713 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224
1338 00:22:43.350004 iDelay=217, Bit 12, Center 80 (-31 ~ 192) 224
1339 00:22:43.356389 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1340 00:22:43.359671 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1341 00:22:43.362985 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1342 00:22:43.363425 ==
1343 00:22:43.366379 Dram Type= 6, Freq= 0, CH_0, rank 1
1344 00:22:43.369864 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1345 00:22:43.370532 ==
1346 00:22:43.373263 DQS Delay:
1347 00:22:43.373697 DQS0 = 0, DQS1 = 0
1348 00:22:43.376708 DQM Delay:
1349 00:22:43.377140 DQM0 = 86, DQM1 = 74
1350 00:22:43.377510 DQ Delay:
1351 00:22:43.379730 DQ0 =80, DQ1 =88, DQ2 =84, DQ3 =84
1352 00:22:43.383568 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1353 00:22:43.386578 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1354 00:22:43.389854 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
1355 00:22:43.390423
1356 00:22:43.390778
1357 00:22:43.399858 [DQSOSCAuto] RK1, (LSB)MR18= 0x5050, (MSB)MR19= 0x606, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
1358 00:22:43.403430 CH0 RK1: MR19=606, MR18=5050
1359 00:22:43.406624 CH0_RK1: MR19=0x606, MR18=0x5050, DQSOSC=389, MR23=63, INC=97, DEC=65
1360 00:22:43.409622 [RxdqsGatingPostProcess] freq 800
1361 00:22:43.416503 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1362 00:22:43.419591 Pre-setting of DQS Precalculation
1363 00:22:43.422953 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1364 00:22:43.423380 ==
1365 00:22:43.426396 Dram Type= 6, Freq= 0, CH_1, rank 0
1366 00:22:43.433251 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1367 00:22:43.433662 ==
1368 00:22:43.436576 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1369 00:22:43.443050 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1370 00:22:43.452014 [CA 0] Center 37 (6~68) winsize 63
1371 00:22:43.455454 [CA 1] Center 37 (6~68) winsize 63
1372 00:22:43.458585 [CA 2] Center 34 (4~65) winsize 62
1373 00:22:43.461959 [CA 3] Center 34 (4~65) winsize 62
1374 00:22:43.465338 [CA 4] Center 33 (3~64) winsize 62
1375 00:22:43.468795 [CA 5] Center 33 (3~64) winsize 62
1376 00:22:43.469106
1377 00:22:43.471832 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1378 00:22:43.472109
1379 00:22:43.475020 [CATrainingPosCal] consider 1 rank data
1380 00:22:43.479282 u2DelayCellTimex100 = 270/100 ps
1381 00:22:43.481718 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1382 00:22:43.485289 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1383 00:22:43.491870 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1384 00:22:43.495445 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1385 00:22:43.498675 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1386 00:22:43.502262 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1387 00:22:43.502432
1388 00:22:43.505544 CA PerBit enable=1, Macro0, CA PI delay=33
1389 00:22:43.505668
1390 00:22:43.508993 [CBTSetCACLKResult] CA Dly = 33
1391 00:22:43.509163 CS Dly: 5 (0~36)
1392 00:22:43.509252 ==
1393 00:22:43.512250 Dram Type= 6, Freq= 0, CH_1, rank 1
1394 00:22:43.518659 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1395 00:22:43.518855 ==
1396 00:22:43.522608 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1397 00:22:43.529148 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1398 00:22:43.538071 [CA 0] Center 36 (6~67) winsize 62
1399 00:22:43.541283 [CA 1] Center 37 (6~68) winsize 63
1400 00:22:43.544653 [CA 2] Center 34 (4~65) winsize 62
1401 00:22:43.548031 [CA 3] Center 34 (4~65) winsize 62
1402 00:22:43.551185 [CA 4] Center 33 (3~64) winsize 62
1403 00:22:43.554512 [CA 5] Center 33 (2~64) winsize 63
1404 00:22:43.554827
1405 00:22:43.558183 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1406 00:22:43.558599
1407 00:22:43.561541 [CATrainingPosCal] consider 2 rank data
1408 00:22:43.564515 u2DelayCellTimex100 = 270/100 ps
1409 00:22:43.567982 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1410 00:22:43.571039 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1411 00:22:43.578015 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1412 00:22:43.581231 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1413 00:22:43.585199 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1414 00:22:43.588092 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1415 00:22:43.588608
1416 00:22:43.591038 CA PerBit enable=1, Macro0, CA PI delay=33
1417 00:22:43.591470
1418 00:22:43.594877 [CBTSetCACLKResult] CA Dly = 33
1419 00:22:43.595391 CS Dly: 5 (0~36)
1420 00:22:43.595724
1421 00:22:43.597958 ----->DramcWriteLeveling(PI) begin...
1422 00:22:43.601254 ==
1423 00:22:43.604811 Dram Type= 6, Freq= 0, CH_1, rank 0
1424 00:22:43.608179 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1425 00:22:43.608699 ==
1426 00:22:43.611203 Write leveling (Byte 0): 24 => 24
1427 00:22:43.614686 Write leveling (Byte 1): 24 => 24
1428 00:22:43.617754 DramcWriteLeveling(PI) end<-----
1429 00:22:43.618283
1430 00:22:43.618621 ==
1431 00:22:43.621656 Dram Type= 6, Freq= 0, CH_1, rank 0
1432 00:22:43.624950 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1433 00:22:43.625432 ==
1434 00:22:43.628157 [Gating] SW mode calibration
1435 00:22:43.634425 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1436 00:22:43.638039 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1437 00:22:43.644361 0 6 0 | B1->B0 | 2f2f 2727 | 0 0 | (0 0) (1 0)
1438 00:22:43.648103 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1439 00:22:43.651500 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1440 00:22:43.658016 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1441 00:22:43.661755 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1442 00:22:43.665062 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1443 00:22:43.671512 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1444 00:22:43.674309 0 6 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1445 00:22:43.677983 0 7 0 | B1->B0 | 3030 4242 | 0 0 | (0 0) (0 0)
1446 00:22:43.684950 0 7 4 | B1->B0 | 4343 4646 | 1 0 | (0 0) (0 0)
1447 00:22:43.688186 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1448 00:22:43.691102 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1449 00:22:43.698094 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1450 00:22:43.701564 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1451 00:22:43.704847 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1452 00:22:43.711616 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1453 00:22:43.714689 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1454 00:22:43.718106 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1455 00:22:43.724719 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1456 00:22:43.728156 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1457 00:22:43.730905 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1458 00:22:43.734249 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1459 00:22:43.741176 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1460 00:22:43.744205 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1461 00:22:43.747523 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1462 00:22:43.754372 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1463 00:22:43.758611 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1464 00:22:43.761545 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1465 00:22:43.767794 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1466 00:22:43.771418 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1467 00:22:43.774337 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1468 00:22:43.781329 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1469 00:22:43.784756 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1470 00:22:43.787573 Total UI for P1: 0, mck2ui 16
1471 00:22:43.791174 best dqsien dly found for B0: ( 0, 9, 30)
1472 00:22:43.794515 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1473 00:22:43.797642 Total UI for P1: 0, mck2ui 16
1474 00:22:43.801466 best dqsien dly found for B1: ( 0, 10, 0)
1475 00:22:43.804452 best DQS0 dly(MCK, UI, PI) = (0, 9, 30)
1476 00:22:43.807647 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1477 00:22:43.808084
1478 00:22:43.814733 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 30)
1479 00:22:43.817505 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1480 00:22:43.817941 [Gating] SW calibration Done
1481 00:22:43.821009 ==
1482 00:22:43.821656 Dram Type= 6, Freq= 0, CH_1, rank 0
1483 00:22:43.827992 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1484 00:22:43.828468 ==
1485 00:22:43.828811 RX Vref Scan: 0
1486 00:22:43.829127
1487 00:22:43.831586 RX Vref 0 -> 0, step: 1
1488 00:22:43.832166
1489 00:22:43.834424 RX Delay -130 -> 252, step: 16
1490 00:22:43.837895 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1491 00:22:43.841269 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1492 00:22:43.844437 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1493 00:22:43.850834 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1494 00:22:43.854631 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1495 00:22:43.857590 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1496 00:22:43.860850 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1497 00:22:43.864628 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1498 00:22:43.870925 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1499 00:22:43.874508 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1500 00:22:43.877802 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1501 00:22:43.881257 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1502 00:22:43.885164 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1503 00:22:43.891540 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1504 00:22:43.894338 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1505 00:22:43.897683 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1506 00:22:43.898196 ==
1507 00:22:43.900960 Dram Type= 6, Freq= 0, CH_1, rank 0
1508 00:22:43.904783 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1509 00:22:43.905308 ==
1510 00:22:43.908182 DQS Delay:
1511 00:22:43.908674 DQS0 = 0, DQS1 = 0
1512 00:22:43.911232 DQM Delay:
1513 00:22:43.911745 DQM0 = 81, DQM1 = 73
1514 00:22:43.912089 DQ Delay:
1515 00:22:43.914653 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1516 00:22:43.917616 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1517 00:22:43.920958 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =61
1518 00:22:43.924918 DQ12 =85, DQ13 =85, DQ14 =77, DQ15 =85
1519 00:22:43.925433
1520 00:22:43.925771
1521 00:22:43.927616 ==
1522 00:22:43.931074 Dram Type= 6, Freq= 0, CH_1, rank 0
1523 00:22:43.934205 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1524 00:22:43.934674 ==
1525 00:22:43.935011
1526 00:22:43.935324
1527 00:22:43.937615 TX Vref Scan disable
1528 00:22:43.938051 == TX Byte 0 ==
1529 00:22:43.940921 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1530 00:22:43.947781 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1531 00:22:43.948303 == TX Byte 1 ==
1532 00:22:43.951004 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1533 00:22:43.958012 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1534 00:22:43.958592 ==
1535 00:22:43.961332 Dram Type= 6, Freq= 0, CH_1, rank 0
1536 00:22:43.964395 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1537 00:22:43.965075 ==
1538 00:22:43.977203 TX Vref=22, minBit 3, minWin=27, winSum=448
1539 00:22:43.980875 TX Vref=24, minBit 3, minWin=27, winSum=449
1540 00:22:43.984129 TX Vref=26, minBit 3, minWin=27, winSum=454
1541 00:22:43.987810 TX Vref=28, minBit 0, minWin=28, winSum=458
1542 00:22:43.990538 TX Vref=30, minBit 0, minWin=28, winSum=457
1543 00:22:43.997412 TX Vref=32, minBit 9, minWin=27, winSum=456
1544 00:22:44.000479 [TxChooseVref] Worse bit 0, Min win 28, Win sum 458, Final Vref 28
1545 00:22:44.001001
1546 00:22:44.003692 Final TX Range 1 Vref 28
1547 00:22:44.004166
1548 00:22:44.004503 ==
1549 00:22:44.007305 Dram Type= 6, Freq= 0, CH_1, rank 0
1550 00:22:44.011184 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1551 00:22:44.011703 ==
1552 00:22:44.012046
1553 00:22:44.013713
1554 00:22:44.014150 TX Vref Scan disable
1555 00:22:44.017432 == TX Byte 0 ==
1556 00:22:44.020242 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1557 00:22:44.027451 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1558 00:22:44.028039 == TX Byte 1 ==
1559 00:22:44.030327 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1560 00:22:44.037119 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1561 00:22:44.037621
1562 00:22:44.037959 [DATLAT]
1563 00:22:44.038310 Freq=800, CH1 RK0
1564 00:22:44.038620
1565 00:22:44.040561 DATLAT Default: 0xa
1566 00:22:44.041080 0, 0xFFFF, sum = 0
1567 00:22:44.043851 1, 0xFFFF, sum = 0
1568 00:22:44.044375 2, 0xFFFF, sum = 0
1569 00:22:44.047196 3, 0xFFFF, sum = 0
1570 00:22:44.047717 4, 0xFFFF, sum = 0
1571 00:22:44.050319 5, 0xFFFF, sum = 0
1572 00:22:44.054323 6, 0xFFFF, sum = 0
1573 00:22:44.054844 7, 0xFFFF, sum = 0
1574 00:22:44.055240 8, 0x0, sum = 1
1575 00:22:44.057304 9, 0x0, sum = 2
1576 00:22:44.057823 10, 0x0, sum = 3
1577 00:22:44.060440 11, 0x0, sum = 4
1578 00:22:44.060886 best_step = 9
1579 00:22:44.061228
1580 00:22:44.061541 ==
1581 00:22:44.063974 Dram Type= 6, Freq= 0, CH_1, rank 0
1582 00:22:44.070681 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1583 00:22:44.071302 ==
1584 00:22:44.071675 RX Vref Scan: 1
1585 00:22:44.071996
1586 00:22:44.074175 Set Vref Range= 32 -> 127
1587 00:22:44.074733
1588 00:22:44.077525 RX Vref 32 -> 127, step: 1
1589 00:22:44.078065
1590 00:22:44.078499 RX Delay -111 -> 252, step: 8
1591 00:22:44.080783
1592 00:22:44.081233 Set Vref, RX VrefLevel [Byte0]: 32
1593 00:22:44.083678 [Byte1]: 32
1594 00:22:44.088482
1595 00:22:44.088974 Set Vref, RX VrefLevel [Byte0]: 33
1596 00:22:44.091471 [Byte1]: 33
1597 00:22:44.096157
1598 00:22:44.096668 Set Vref, RX VrefLevel [Byte0]: 34
1599 00:22:44.099129 [Byte1]: 34
1600 00:22:44.104040
1601 00:22:44.104566 Set Vref, RX VrefLevel [Byte0]: 35
1602 00:22:44.106623 [Byte1]: 35
1603 00:22:44.111177
1604 00:22:44.111692 Set Vref, RX VrefLevel [Byte0]: 36
1605 00:22:44.114385 [Byte1]: 36
1606 00:22:44.118678
1607 00:22:44.119108 Set Vref, RX VrefLevel [Byte0]: 37
1608 00:22:44.122245 [Byte1]: 37
1609 00:22:44.126422
1610 00:22:44.126856 Set Vref, RX VrefLevel [Byte0]: 38
1611 00:22:44.129536 [Byte1]: 38
1612 00:22:44.134295
1613 00:22:44.134832 Set Vref, RX VrefLevel [Byte0]: 39
1614 00:22:44.137106 [Byte1]: 39
1615 00:22:44.142012
1616 00:22:44.142560 Set Vref, RX VrefLevel [Byte0]: 40
1617 00:22:44.145077 [Byte1]: 40
1618 00:22:44.149222
1619 00:22:44.149660 Set Vref, RX VrefLevel [Byte0]: 41
1620 00:22:44.152465 [Byte1]: 41
1621 00:22:44.156880
1622 00:22:44.157392 Set Vref, RX VrefLevel [Byte0]: 42
1623 00:22:44.160354 [Byte1]: 42
1624 00:22:44.165125
1625 00:22:44.165643 Set Vref, RX VrefLevel [Byte0]: 43
1626 00:22:44.167680 [Byte1]: 43
1627 00:22:44.172503
1628 00:22:44.173032 Set Vref, RX VrefLevel [Byte0]: 44
1629 00:22:44.175544 [Byte1]: 44
1630 00:22:44.179599
1631 00:22:44.180045 Set Vref, RX VrefLevel [Byte0]: 45
1632 00:22:44.182981 [Byte1]: 45
1633 00:22:44.187806
1634 00:22:44.188316 Set Vref, RX VrefLevel [Byte0]: 46
1635 00:22:44.190838 [Byte1]: 46
1636 00:22:44.195619
1637 00:22:44.196135 Set Vref, RX VrefLevel [Byte0]: 47
1638 00:22:44.198769 [Byte1]: 47
1639 00:22:44.203052
1640 00:22:44.203485 Set Vref, RX VrefLevel [Byte0]: 48
1641 00:22:44.206321 [Byte1]: 48
1642 00:22:44.210396
1643 00:22:44.210833 Set Vref, RX VrefLevel [Byte0]: 49
1644 00:22:44.214615 [Byte1]: 49
1645 00:22:44.218460
1646 00:22:44.218972 Set Vref, RX VrefLevel [Byte0]: 50
1647 00:22:44.221540 [Byte1]: 50
1648 00:22:44.225807
1649 00:22:44.226272 Set Vref, RX VrefLevel [Byte0]: 51
1650 00:22:44.229112 [Byte1]: 51
1651 00:22:44.233567
1652 00:22:44.234078 Set Vref, RX VrefLevel [Byte0]: 52
1653 00:22:44.236546 [Byte1]: 52
1654 00:22:44.241534
1655 00:22:44.241973 Set Vref, RX VrefLevel [Byte0]: 53
1656 00:22:44.244675 [Byte1]: 53
1657 00:22:44.248957
1658 00:22:44.249500 Set Vref, RX VrefLevel [Byte0]: 54
1659 00:22:44.251934 [Byte1]: 54
1660 00:22:44.256355
1661 00:22:44.256798 Set Vref, RX VrefLevel [Byte0]: 55
1662 00:22:44.259602 [Byte1]: 55
1663 00:22:44.263996
1664 00:22:44.264438 Set Vref, RX VrefLevel [Byte0]: 56
1665 00:22:44.267475 [Byte1]: 56
1666 00:22:44.271489
1667 00:22:44.271898 Set Vref, RX VrefLevel [Byte0]: 57
1668 00:22:44.275317 [Byte1]: 57
1669 00:22:44.279008
1670 00:22:44.279442 Set Vref, RX VrefLevel [Byte0]: 58
1671 00:22:44.282779 [Byte1]: 58
1672 00:22:44.287046
1673 00:22:44.287556 Set Vref, RX VrefLevel [Byte0]: 59
1674 00:22:44.290319 [Byte1]: 59
1675 00:22:44.294891
1676 00:22:44.295484 Set Vref, RX VrefLevel [Byte0]: 60
1677 00:22:44.297796 [Byte1]: 60
1678 00:22:44.302248
1679 00:22:44.302775 Set Vref, RX VrefLevel [Byte0]: 61
1680 00:22:44.305910 [Byte1]: 61
1681 00:22:44.310080
1682 00:22:44.310659 Set Vref, RX VrefLevel [Byte0]: 62
1683 00:22:44.313306 [Byte1]: 62
1684 00:22:44.318044
1685 00:22:44.318630 Set Vref, RX VrefLevel [Byte0]: 63
1686 00:22:44.321324 [Byte1]: 63
1687 00:22:44.325028
1688 00:22:44.325483 Set Vref, RX VrefLevel [Byte0]: 64
1689 00:22:44.328790 [Byte1]: 64
1690 00:22:44.332996
1691 00:22:44.333508 Set Vref, RX VrefLevel [Byte0]: 65
1692 00:22:44.336430 [Byte1]: 65
1693 00:22:44.341330
1694 00:22:44.341840 Set Vref, RX VrefLevel [Byte0]: 66
1695 00:22:44.343891 [Byte1]: 66
1696 00:22:44.348877
1697 00:22:44.349396 Set Vref, RX VrefLevel [Byte0]: 67
1698 00:22:44.351456 [Byte1]: 67
1699 00:22:44.355833
1700 00:22:44.356421 Set Vref, RX VrefLevel [Byte0]: 68
1701 00:22:44.359566 [Byte1]: 68
1702 00:22:44.363563
1703 00:22:44.364083 Set Vref, RX VrefLevel [Byte0]: 69
1704 00:22:44.366779 [Byte1]: 69
1705 00:22:44.370903
1706 00:22:44.371413 Set Vref, RX VrefLevel [Byte0]: 70
1707 00:22:44.374566 [Byte1]: 70
1708 00:22:44.378618
1709 00:22:44.379162 Set Vref, RX VrefLevel [Byte0]: 71
1710 00:22:44.382021 [Byte1]: 71
1711 00:22:44.386464
1712 00:22:44.386975 Set Vref, RX VrefLevel [Byte0]: 72
1713 00:22:44.389758 [Byte1]: 72
1714 00:22:44.394469
1715 00:22:44.394984 Set Vref, RX VrefLevel [Byte0]: 73
1716 00:22:44.397556 [Byte1]: 73
1717 00:22:44.401796
1718 00:22:44.402366 Set Vref, RX VrefLevel [Byte0]: 74
1719 00:22:44.404905 [Byte1]: 74
1720 00:22:44.410037
1721 00:22:44.410587 Set Vref, RX VrefLevel [Byte0]: 75
1722 00:22:44.412874 [Byte1]: 75
1723 00:22:44.417286
1724 00:22:44.417830 Set Vref, RX VrefLevel [Byte0]: 76
1725 00:22:44.420008 [Byte1]: 76
1726 00:22:44.424835
1727 00:22:44.425350 Set Vref, RX VrefLevel [Byte0]: 77
1728 00:22:44.427906 [Byte1]: 77
1729 00:22:44.432467
1730 00:22:44.432978 Set Vref, RX VrefLevel [Byte0]: 78
1731 00:22:44.435631 [Byte1]: 78
1732 00:22:44.440373
1733 00:22:44.440890 Final RX Vref Byte 0 = 59 to rank0
1734 00:22:44.443359 Final RX Vref Byte 1 = 54 to rank0
1735 00:22:44.446607 Final RX Vref Byte 0 = 59 to rank1
1736 00:22:44.450366 Final RX Vref Byte 1 = 54 to rank1==
1737 00:22:44.453357 Dram Type= 6, Freq= 0, CH_1, rank 0
1738 00:22:44.460701 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1739 00:22:44.461221 ==
1740 00:22:44.461561 DQS Delay:
1741 00:22:44.461878 DQS0 = 0, DQS1 = 0
1742 00:22:44.463386 DQM Delay:
1743 00:22:44.463822 DQM0 = 82, DQM1 = 74
1744 00:22:44.466689 DQ Delay:
1745 00:22:44.470070 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =80
1746 00:22:44.470634 DQ4 =80, DQ5 =96, DQ6 =88, DQ7 =76
1747 00:22:44.473361 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =68
1748 00:22:44.476731 DQ12 =80, DQ13 =84, DQ14 =80, DQ15 =84
1749 00:22:44.480016
1750 00:22:44.480468
1751 00:22:44.486809 [DQSOSCAuto] RK0, (LSB)MR18= 0x5959, (MSB)MR19= 0x606, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
1752 00:22:44.489859 CH1 RK0: MR19=606, MR18=5959
1753 00:22:44.497037 CH1_RK0: MR19=0x606, MR18=0x5959, DQSOSC=387, MR23=63, INC=98, DEC=65
1754 00:22:44.497474
1755 00:22:44.500129 ----->DramcWriteLeveling(PI) begin...
1756 00:22:44.500575 ==
1757 00:22:44.503042 Dram Type= 6, Freq= 0, CH_1, rank 1
1758 00:22:44.506911 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1759 00:22:44.507459 ==
1760 00:22:44.510299 Write leveling (Byte 0): 27 => 27
1761 00:22:44.512921 Write leveling (Byte 1): 22 => 22
1762 00:22:44.516792 DramcWriteLeveling(PI) end<-----
1763 00:22:44.517309
1764 00:22:44.517650 ==
1765 00:22:44.519699 Dram Type= 6, Freq= 0, CH_1, rank 1
1766 00:22:44.523059 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1767 00:22:44.523503 ==
1768 00:22:44.526541 [Gating] SW mode calibration
1769 00:22:44.533110 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1770 00:22:44.540066 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1771 00:22:44.543080 0 6 0 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
1772 00:22:44.546384 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1773 00:22:44.553399 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1774 00:22:44.556924 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1775 00:22:44.559884 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1776 00:22:44.566617 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1777 00:22:44.570123 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1778 00:22:44.573669 0 6 28 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
1779 00:22:44.579824 0 7 0 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
1780 00:22:44.583542 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1781 00:22:44.586939 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1782 00:22:44.593395 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1783 00:22:44.597011 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1784 00:22:44.599740 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1785 00:22:44.603390 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1786 00:22:44.609818 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1787 00:22:44.612897 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1788 00:22:44.616709 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1789 00:22:44.622969 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1790 00:22:44.626933 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1791 00:22:44.629734 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1792 00:22:44.636728 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1793 00:22:44.640309 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1794 00:22:44.643403 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1795 00:22:44.650099 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1796 00:22:44.653492 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1797 00:22:44.656284 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1798 00:22:44.663435 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1799 00:22:44.666626 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1800 00:22:44.670346 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1801 00:22:44.676412 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1802 00:22:44.679807 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1803 00:22:44.683183 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1804 00:22:44.686540 Total UI for P1: 0, mck2ui 16
1805 00:22:44.690235 best dqsien dly found for B0: ( 0, 9, 26)
1806 00:22:44.693174 Total UI for P1: 0, mck2ui 16
1807 00:22:44.696463 best dqsien dly found for B1: ( 0, 9, 28)
1808 00:22:44.700043 best DQS0 dly(MCK, UI, PI) = (0, 9, 26)
1809 00:22:44.703092 best DQS1 dly(MCK, UI, PI) = (0, 9, 28)
1810 00:22:44.703535
1811 00:22:44.706580 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 26)
1812 00:22:44.713366 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 28)
1813 00:22:44.713882 [Gating] SW calibration Done
1814 00:22:44.714366 ==
1815 00:22:44.716636 Dram Type= 6, Freq= 0, CH_1, rank 1
1816 00:22:44.722931 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1817 00:22:44.723374 ==
1818 00:22:44.723715 RX Vref Scan: 0
1819 00:22:44.724035
1820 00:22:44.726165 RX Vref 0 -> 0, step: 1
1821 00:22:44.726630
1822 00:22:44.730048 RX Delay -130 -> 252, step: 16
1823 00:22:44.733329 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1824 00:22:44.736934 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1825 00:22:44.739599 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1826 00:22:44.746564 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1827 00:22:44.749873 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1828 00:22:44.753243 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1829 00:22:44.756342 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1830 00:22:44.759574 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1831 00:22:44.766360 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1832 00:22:44.769767 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1833 00:22:44.773104 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1834 00:22:44.776407 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1835 00:22:44.779909 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1836 00:22:44.786667 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1837 00:22:44.790142 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1838 00:22:44.793022 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1839 00:22:44.793467 ==
1840 00:22:44.796697 Dram Type= 6, Freq= 0, CH_1, rank 1
1841 00:22:44.800153 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1842 00:22:44.800673 ==
1843 00:22:44.803382 DQS Delay:
1844 00:22:44.803898 DQS0 = 0, DQS1 = 0
1845 00:22:44.806559 DQM Delay:
1846 00:22:44.807029 DQM0 = 85, DQM1 = 72
1847 00:22:44.807370 DQ Delay:
1848 00:22:44.810511 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1849 00:22:44.813561 DQ4 =85, DQ5 =101, DQ6 =85, DQ7 =85
1850 00:22:44.816894 DQ8 =53, DQ9 =61, DQ10 =69, DQ11 =61
1851 00:22:44.820249 DQ12 =85, DQ13 =85, DQ14 =77, DQ15 =85
1852 00:22:44.820726
1853 00:22:44.821068
1854 00:22:44.821381 ==
1855 00:22:44.823094 Dram Type= 6, Freq= 0, CH_1, rank 1
1856 00:22:44.829823 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1857 00:22:44.830298 ==
1858 00:22:44.830646
1859 00:22:44.830960
1860 00:22:44.831262 TX Vref Scan disable
1861 00:22:44.833921 == TX Byte 0 ==
1862 00:22:44.837346 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1863 00:22:44.843996 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1864 00:22:44.844515 == TX Byte 1 ==
1865 00:22:44.847477 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
1866 00:22:44.853867 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
1867 00:22:44.854410 ==
1868 00:22:44.857167 Dram Type= 6, Freq= 0, CH_1, rank 1
1869 00:22:44.860612 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1870 00:22:44.861135 ==
1871 00:22:44.873181 TX Vref=22, minBit 0, minWin=27, winSum=451
1872 00:22:44.876522 TX Vref=24, minBit 0, minWin=27, winSum=454
1873 00:22:44.880139 TX Vref=26, minBit 3, minWin=28, winSum=458
1874 00:22:44.883506 TX Vref=28, minBit 3, minWin=28, winSum=461
1875 00:22:44.886772 TX Vref=30, minBit 7, minWin=28, winSum=458
1876 00:22:44.890234 TX Vref=32, minBit 0, minWin=28, winSum=454
1877 00:22:44.896556 [TxChooseVref] Worse bit 3, Min win 28, Win sum 461, Final Vref 28
1878 00:22:44.897166
1879 00:22:44.899972 Final TX Range 1 Vref 28
1880 00:22:44.900412
1881 00:22:44.900749 ==
1882 00:22:44.903706 Dram Type= 6, Freq= 0, CH_1, rank 1
1883 00:22:44.906775 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1884 00:22:44.907293 ==
1885 00:22:44.907637
1886 00:22:44.909755
1887 00:22:44.910189 TX Vref Scan disable
1888 00:22:44.913596 == TX Byte 0 ==
1889 00:22:44.916955 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1890 00:22:44.919690 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1891 00:22:44.923083 == TX Byte 1 ==
1892 00:22:44.926737 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
1893 00:22:44.930081 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
1894 00:22:44.933695
1895 00:22:44.934207 [DATLAT]
1896 00:22:44.934611 Freq=800, CH1 RK1
1897 00:22:44.934927
1898 00:22:44.936628 DATLAT Default: 0x9
1899 00:22:44.937066 0, 0xFFFF, sum = 0
1900 00:22:44.940507 1, 0xFFFF, sum = 0
1901 00:22:44.941022 2, 0xFFFF, sum = 0
1902 00:22:44.943690 3, 0xFFFF, sum = 0
1903 00:22:44.944213 4, 0xFFFF, sum = 0
1904 00:22:44.946610 5, 0xFFFF, sum = 0
1905 00:22:44.947051 6, 0xFFFF, sum = 0
1906 00:22:44.949878 7, 0xFFFF, sum = 0
1907 00:22:44.950369 8, 0x0, sum = 1
1908 00:22:44.953291 9, 0x0, sum = 2
1909 00:22:44.953733 10, 0x0, sum = 3
1910 00:22:44.956900 11, 0x0, sum = 4
1911 00:22:44.957450 best_step = 9
1912 00:22:44.957827
1913 00:22:44.958145 ==
1914 00:22:44.959944 Dram Type= 6, Freq= 0, CH_1, rank 1
1915 00:22:44.966967 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1916 00:22:44.967486 ==
1917 00:22:44.967828 RX Vref Scan: 0
1918 00:22:44.968142
1919 00:22:44.970360 RX Vref 0 -> 0, step: 1
1920 00:22:44.970798
1921 00:22:44.973579 RX Delay -111 -> 252, step: 8
1922 00:22:44.977234 iDelay=217, Bit 0, Center 88 (-23 ~ 200) 224
1923 00:22:44.980026 iDelay=217, Bit 1, Center 76 (-39 ~ 192) 232
1924 00:22:44.986450 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
1925 00:22:44.990020 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1926 00:22:44.993060 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
1927 00:22:44.996559 iDelay=217, Bit 5, Center 100 (-15 ~ 216) 232
1928 00:22:44.999955 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1929 00:22:45.006805 iDelay=217, Bit 7, Center 80 (-39 ~ 200) 240
1930 00:22:45.010417 iDelay=217, Bit 8, Center 60 (-55 ~ 176) 232
1931 00:22:45.013261 iDelay=217, Bit 9, Center 64 (-55 ~ 184) 240
1932 00:22:45.016919 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1933 00:22:45.020101 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
1934 00:22:45.026674 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1935 00:22:45.030288 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1936 00:22:45.033243 iDelay=217, Bit 14, Center 80 (-39 ~ 200) 240
1937 00:22:45.036814 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1938 00:22:45.037332 ==
1939 00:22:45.039713 Dram Type= 6, Freq= 0, CH_1, rank 1
1940 00:22:45.046705 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1941 00:22:45.047231 ==
1942 00:22:45.047571 DQS Delay:
1943 00:22:45.047887 DQS0 = 0, DQS1 = 0
1944 00:22:45.050258 DQM Delay:
1945 00:22:45.050775 DQM0 = 84, DQM1 = 75
1946 00:22:45.053874 DQ Delay:
1947 00:22:45.056852 DQ0 =88, DQ1 =76, DQ2 =76, DQ3 =80
1948 00:22:45.057364 DQ4 =84, DQ5 =100, DQ6 =92, DQ7 =80
1949 00:22:45.060574 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =68
1950 00:22:45.063954 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =84
1951 00:22:45.066477
1952 00:22:45.067124
1953 00:22:45.073277 [DQSOSCAuto] RK1, (LSB)MR18= 0x4545, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
1954 00:22:45.076389 CH1 RK1: MR19=606, MR18=4545
1955 00:22:45.083296 CH1_RK1: MR19=0x606, MR18=0x4545, DQSOSC=392, MR23=63, INC=96, DEC=64
1956 00:22:45.086611 [RxdqsGatingPostProcess] freq 800
1957 00:22:45.090201 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1958 00:22:45.093986 Pre-setting of DQS Precalculation
1959 00:22:45.096718 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1960 00:22:45.106796 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1961 00:22:45.113283 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1962 00:22:45.113722
1963 00:22:45.114060
1964 00:22:45.117245 [Calibration Summary] 1600 Mbps
1965 00:22:45.117797 CH 0, Rank 0
1966 00:22:45.119916 SW Impedance : PASS
1967 00:22:45.120284 DUTY Scan : NO K
1968 00:22:45.123441 ZQ Calibration : PASS
1969 00:22:45.127019 Jitter Meter : NO K
1970 00:22:45.127454 CBT Training : PASS
1971 00:22:45.130373 Write leveling : PASS
1972 00:22:45.133684 RX DQS gating : PASS
1973 00:22:45.134118 RX DQ/DQS(RDDQC) : PASS
1974 00:22:45.136844 TX DQ/DQS : PASS
1975 00:22:45.140527 RX DATLAT : PASS
1976 00:22:45.141040 RX DQ/DQS(Engine): PASS
1977 00:22:45.144182 TX OE : NO K
1978 00:22:45.144695 All Pass.
1979 00:22:45.145033
1980 00:22:45.146609 CH 0, Rank 1
1981 00:22:45.147041 SW Impedance : PASS
1982 00:22:45.150547 DUTY Scan : NO K
1983 00:22:45.153607 ZQ Calibration : PASS
1984 00:22:45.154117 Jitter Meter : NO K
1985 00:22:45.157029 CBT Training : PASS
1986 00:22:45.157542 Write leveling : PASS
1987 00:22:45.160577 RX DQS gating : PASS
1988 00:22:45.164263 RX DQ/DQS(RDDQC) : PASS
1989 00:22:45.164774 TX DQ/DQS : PASS
1990 00:22:45.166673 RX DATLAT : PASS
1991 00:22:45.170494 RX DQ/DQS(Engine): PASS
1992 00:22:45.170998 TX OE : NO K
1993 00:22:45.173560 All Pass.
1994 00:22:45.174002
1995 00:22:45.174392 CH 1, Rank 0
1996 00:22:45.177127 SW Impedance : PASS
1997 00:22:45.177563 DUTY Scan : NO K
1998 00:22:45.180072 ZQ Calibration : PASS
1999 00:22:45.183418 Jitter Meter : NO K
2000 00:22:45.183852 CBT Training : PASS
2001 00:22:45.186437 Write leveling : PASS
2002 00:22:45.190137 RX DQS gating : PASS
2003 00:22:45.190821 RX DQ/DQS(RDDQC) : PASS
2004 00:22:45.193265 TX DQ/DQS : PASS
2005 00:22:45.193784 RX DATLAT : PASS
2006 00:22:45.196606 RX DQ/DQS(Engine): PASS
2007 00:22:45.200259 TX OE : NO K
2008 00:22:45.200694 All Pass.
2009 00:22:45.201030
2010 00:22:45.201341 CH 1, Rank 1
2011 00:22:45.203288 SW Impedance : PASS
2012 00:22:45.207278 DUTY Scan : NO K
2013 00:22:45.207715 ZQ Calibration : PASS
2014 00:22:45.210613 Jitter Meter : NO K
2015 00:22:45.213577 CBT Training : PASS
2016 00:22:45.214092 Write leveling : PASS
2017 00:22:45.216569 RX DQS gating : PASS
2018 00:22:45.220067 RX DQ/DQS(RDDQC) : PASS
2019 00:22:45.220591 TX DQ/DQS : PASS
2020 00:22:45.223262 RX DATLAT : PASS
2021 00:22:45.226869 RX DQ/DQS(Engine): PASS
2022 00:22:45.227326 TX OE : NO K
2023 00:22:45.227820 All Pass.
2024 00:22:45.230245
2025 00:22:45.230686 DramC Write-DBI off
2026 00:22:45.233250 PER_BANK_REFRESH: Hybrid Mode
2027 00:22:45.233686 TX_TRACKING: ON
2028 00:22:45.237047 [GetDramInforAfterCalByMRR] Vendor 6.
2029 00:22:45.239911 [GetDramInforAfterCalByMRR] Revision 606.
2030 00:22:45.246897 [GetDramInforAfterCalByMRR] Revision 2 0.
2031 00:22:45.247419 MR0 0x3939
2032 00:22:45.247763 MR8 0x1111
2033 00:22:45.249981 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
2034 00:22:45.250443
2035 00:22:45.253752 MR0 0x3939
2036 00:22:45.254300 MR8 0x1111
2037 00:22:45.256980 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
2038 00:22:45.257497
2039 00:22:45.267273 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2040 00:22:45.270130 [FAST_K] Save calibration result to emmc
2041 00:22:45.273757 [FAST_K] Save calibration result to emmc
2042 00:22:45.276632 dram_init: config_dvfs: 1
2043 00:22:45.279939 dramc_set_vcore_voltage set vcore to 662500
2044 00:22:45.283064 Read voltage for 1200, 2
2045 00:22:45.283506 Vio18 = 0
2046 00:22:45.283846 Vcore = 662500
2047 00:22:45.286801 Vdram = 0
2048 00:22:45.287271 Vddq = 0
2049 00:22:45.287718 Vmddr = 0
2050 00:22:45.293146 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2051 00:22:45.296411 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2052 00:22:45.299934 MEM_TYPE=3, freq_sel=15
2053 00:22:45.303452 sv_algorithm_assistance_LP4_1600
2054 00:22:45.306808 ============ PULL DRAM RESETB DOWN ============
2055 00:22:45.309837 ========== PULL DRAM RESETB DOWN end =========
2056 00:22:45.317132 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2057 00:22:45.320719 ===================================
2058 00:22:45.321237 LPDDR4 DRAM CONFIGURATION
2059 00:22:45.323350 ===================================
2060 00:22:45.326612 EX_ROW_EN[0] = 0x0
2061 00:22:45.329944 EX_ROW_EN[1] = 0x0
2062 00:22:45.330499 LP4Y_EN = 0x0
2063 00:22:45.333413 WORK_FSP = 0x0
2064 00:22:45.333992 WL = 0x4
2065 00:22:45.336505 RL = 0x4
2066 00:22:45.337015 BL = 0x2
2067 00:22:45.339601 RPST = 0x0
2068 00:22:45.340153 RD_PRE = 0x0
2069 00:22:45.342941 WR_PRE = 0x1
2070 00:22:45.343373 WR_PST = 0x0
2071 00:22:45.346776 DBI_WR = 0x0
2072 00:22:45.347303 DBI_RD = 0x0
2073 00:22:45.349891 OTF = 0x1
2074 00:22:45.353752 ===================================
2075 00:22:45.356681 ===================================
2076 00:22:45.357197 ANA top config
2077 00:22:45.360305 ===================================
2078 00:22:45.363395 DLL_ASYNC_EN = 0
2079 00:22:45.366703 ALL_SLAVE_EN = 0
2080 00:22:45.367214 NEW_RANK_MODE = 1
2081 00:22:45.370185 DLL_IDLE_MODE = 1
2082 00:22:45.373425 LP45_APHY_COMB_EN = 1
2083 00:22:45.376341 TX_ODT_DIS = 1
2084 00:22:45.380115 NEW_8X_MODE = 1
2085 00:22:45.383026 ===================================
2086 00:22:45.386381 ===================================
2087 00:22:45.386896 data_rate = 2400
2088 00:22:45.390106 CKR = 1
2089 00:22:45.393642 DQ_P2S_RATIO = 8
2090 00:22:45.396610 ===================================
2091 00:22:45.399751 CA_P2S_RATIO = 8
2092 00:22:45.403584 DQ_CA_OPEN = 0
2093 00:22:45.406861 DQ_SEMI_OPEN = 0
2094 00:22:45.407381 CA_SEMI_OPEN = 0
2095 00:22:45.409808 CA_FULL_RATE = 0
2096 00:22:45.413204 DQ_CKDIV4_EN = 0
2097 00:22:45.416734 CA_CKDIV4_EN = 0
2098 00:22:45.419733 CA_PREDIV_EN = 0
2099 00:22:45.423158 PH8_DLY = 17
2100 00:22:45.423678 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2101 00:22:45.426509 DQ_AAMCK_DIV = 4
2102 00:22:45.430197 CA_AAMCK_DIV = 4
2103 00:22:45.433221 CA_ADMCK_DIV = 4
2104 00:22:45.436634 DQ_TRACK_CA_EN = 0
2105 00:22:45.440575 CA_PICK = 1200
2106 00:22:45.441091 CA_MCKIO = 1200
2107 00:22:45.443689 MCKIO_SEMI = 0
2108 00:22:45.447212 PLL_FREQ = 2366
2109 00:22:45.450280 DQ_UI_PI_RATIO = 32
2110 00:22:45.453563 CA_UI_PI_RATIO = 0
2111 00:22:45.456852 ===================================
2112 00:22:45.460164 ===================================
2113 00:22:45.463289 memory_type:LPDDR4
2114 00:22:45.463803 GP_NUM : 10
2115 00:22:45.467142 SRAM_EN : 1
2116 00:22:45.467657 MD32_EN : 0
2117 00:22:45.470237 ===================================
2118 00:22:45.473571 [ANA_INIT] >>>>>>>>>>>>>>
2119 00:22:45.476533 <<<<<< [CONFIGURE PHASE]: ANA_TX
2120 00:22:45.479779 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2121 00:22:45.483380 ===================================
2122 00:22:45.486544 data_rate = 2400,PCW = 0X5b00
2123 00:22:45.489882 ===================================
2124 00:22:45.493279 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2125 00:22:45.497137 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2126 00:22:45.503586 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2127 00:22:45.507002 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2128 00:22:45.509971 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2129 00:22:45.513453 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2130 00:22:45.516588 [ANA_INIT] flow start
2131 00:22:45.520572 [ANA_INIT] PLL >>>>>>>>
2132 00:22:45.521088 [ANA_INIT] PLL <<<<<<<<
2133 00:22:45.523415 [ANA_INIT] MIDPI >>>>>>>>
2134 00:22:45.526850 [ANA_INIT] MIDPI <<<<<<<<
2135 00:22:45.530073 [ANA_INIT] DLL >>>>>>>>
2136 00:22:45.530561 [ANA_INIT] DLL <<<<<<<<
2137 00:22:45.533430 [ANA_INIT] flow end
2138 00:22:45.536896 ============ LP4 DIFF to SE enter ============
2139 00:22:45.540045 ============ LP4 DIFF to SE exit ============
2140 00:22:45.543691 [ANA_INIT] <<<<<<<<<<<<<
2141 00:22:45.547045 [Flow] Enable top DCM control >>>>>
2142 00:22:45.550726 [Flow] Enable top DCM control <<<<<
2143 00:22:45.553220 Enable DLL master slave shuffle
2144 00:22:45.560129 ==============================================================
2145 00:22:45.560646 Gating Mode config
2146 00:22:45.566868 ==============================================================
2147 00:22:45.567389 Config description:
2148 00:22:45.576871 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2149 00:22:45.583850 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2150 00:22:45.590423 SELPH_MODE 0: By rank 1: By Phase
2151 00:22:45.593355 ==============================================================
2152 00:22:45.597031 GAT_TRACK_EN = 1
2153 00:22:45.600687 RX_GATING_MODE = 2
2154 00:22:45.603819 RX_GATING_TRACK_MODE = 2
2155 00:22:45.606944 SELPH_MODE = 1
2156 00:22:45.610408 PICG_EARLY_EN = 1
2157 00:22:45.613647 VALID_LAT_VALUE = 1
2158 00:22:45.616973 ==============================================================
2159 00:22:45.620471 Enter into Gating configuration >>>>
2160 00:22:45.623673 Exit from Gating configuration <<<<
2161 00:22:45.626410 Enter into DVFS_PRE_config >>>>>
2162 00:22:45.639862 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2163 00:22:45.643302 Exit from DVFS_PRE_config <<<<<
2164 00:22:45.643750 Enter into PICG configuration >>>>
2165 00:22:45.646328 Exit from PICG configuration <<<<
2166 00:22:45.650118 [RX_INPUT] configuration >>>>>
2167 00:22:45.653125 [RX_INPUT] configuration <<<<<
2168 00:22:45.659686 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2169 00:22:45.662971 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2170 00:22:45.669770 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2171 00:22:45.676231 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2172 00:22:45.683121 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2173 00:22:45.689464 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2174 00:22:45.692729 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2175 00:22:45.696103 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2176 00:22:45.699923 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2177 00:22:45.706619 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2178 00:22:45.709314 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2179 00:22:45.712614 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2180 00:22:45.716049 ===================================
2181 00:22:45.719297 LPDDR4 DRAM CONFIGURATION
2182 00:22:45.722921 ===================================
2183 00:22:45.726318 EX_ROW_EN[0] = 0x0
2184 00:22:45.726713 EX_ROW_EN[1] = 0x0
2185 00:22:45.729227 LP4Y_EN = 0x0
2186 00:22:45.729620 WORK_FSP = 0x0
2187 00:22:45.733423 WL = 0x4
2188 00:22:45.733814 RL = 0x4
2189 00:22:45.736558 BL = 0x2
2190 00:22:45.737299 RPST = 0x0
2191 00:22:45.739655 RD_PRE = 0x0
2192 00:22:45.740134 WR_PRE = 0x1
2193 00:22:45.742821 WR_PST = 0x0
2194 00:22:45.743214 DBI_WR = 0x0
2195 00:22:45.746305 DBI_RD = 0x0
2196 00:22:45.746810 OTF = 0x1
2197 00:22:45.749640 ===================================
2198 00:22:45.752670 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2199 00:22:45.759509 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2200 00:22:45.763140 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2201 00:22:45.766317 ===================================
2202 00:22:45.769371 LPDDR4 DRAM CONFIGURATION
2203 00:22:45.773244 ===================================
2204 00:22:45.773640 EX_ROW_EN[0] = 0x10
2205 00:22:45.776532 EX_ROW_EN[1] = 0x0
2206 00:22:45.776931 LP4Y_EN = 0x0
2207 00:22:45.779636 WORK_FSP = 0x0
2208 00:22:45.782782 WL = 0x4
2209 00:22:45.783176 RL = 0x4
2210 00:22:45.786550 BL = 0x2
2211 00:22:45.786945 RPST = 0x0
2212 00:22:45.789701 RD_PRE = 0x0
2213 00:22:45.790120 WR_PRE = 0x1
2214 00:22:45.793211 WR_PST = 0x0
2215 00:22:45.793690 DBI_WR = 0x0
2216 00:22:45.796144 DBI_RD = 0x0
2217 00:22:45.796708 OTF = 0x1
2218 00:22:45.799318 ===================================
2219 00:22:45.806255 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2220 00:22:45.806654 ==
2221 00:22:45.810147 Dram Type= 6, Freq= 0, CH_0, rank 0
2222 00:22:45.813100 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2223 00:22:45.813581 ==
2224 00:22:45.816309 [Duty_Offset_Calibration]
2225 00:22:45.819714 B0:0 B1:2 CA:1
2226 00:22:45.820229
2227 00:22:45.823229 [DutyScan_Calibration_Flow] k_type=0
2228 00:22:45.830807
2229 00:22:45.831330 ==CLK 0==
2230 00:22:45.834865 Final CLK duty delay cell = 0
2231 00:22:45.837980 [0] MAX Duty = 5093%(X100), DQS PI = 12
2232 00:22:45.841515 [0] MIN Duty = 4938%(X100), DQS PI = 54
2233 00:22:45.842102 [0] AVG Duty = 5015%(X100)
2234 00:22:45.844048
2235 00:22:45.847352 CH0 CLK Duty spec in!! Max-Min= 155%
2236 00:22:45.850673 [DutyScan_Calibration_Flow] ====Done====
2237 00:22:45.851185
2238 00:22:45.854165 [DutyScan_Calibration_Flow] k_type=1
2239 00:22:45.870088
2240 00:22:45.870200 ==DQS 0 ==
2241 00:22:45.872815 Final DQS duty delay cell = 0
2242 00:22:45.876459 [0] MAX Duty = 5125%(X100), DQS PI = 32
2243 00:22:45.879708 [0] MIN Duty = 5031%(X100), DQS PI = 4
2244 00:22:45.879804 [0] AVG Duty = 5078%(X100)
2245 00:22:45.882915
2246 00:22:45.882990 ==DQS 1 ==
2247 00:22:45.887044 Final DQS duty delay cell = 0
2248 00:22:45.889652 [0] MAX Duty = 5031%(X100), DQS PI = 54
2249 00:22:45.893021 [0] MIN Duty = 4875%(X100), DQS PI = 22
2250 00:22:45.896432 [0] AVG Duty = 4953%(X100)
2251 00:22:45.896575
2252 00:22:45.899549 CH0 DQS 0 Duty spec in!! Max-Min= 94%
2253 00:22:45.899730
2254 00:22:45.903439 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2255 00:22:45.906775 [DutyScan_Calibration_Flow] ====Done====
2256 00:22:45.906868
2257 00:22:45.909454 [DutyScan_Calibration_Flow] k_type=3
2258 00:22:45.927083
2259 00:22:45.927292 ==DQM 0 ==
2260 00:22:45.930570 Final DQM duty delay cell = 0
2261 00:22:45.933631 [0] MAX Duty = 5156%(X100), DQS PI = 22
2262 00:22:45.937624 [0] MIN Duty = 4969%(X100), DQS PI = 40
2263 00:22:45.940751 [0] AVG Duty = 5062%(X100)
2264 00:22:45.941030
2265 00:22:45.941245 ==DQM 1 ==
2266 00:22:45.943917 Final DQM duty delay cell = 4
2267 00:22:45.947078 [4] MAX Duty = 5187%(X100), DQS PI = 52
2268 00:22:45.950438 [4] MIN Duty = 5000%(X100), DQS PI = 18
2269 00:22:45.953886 [4] AVG Duty = 5093%(X100)
2270 00:22:45.954416
2271 00:22:45.957306 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2272 00:22:45.957819
2273 00:22:45.960484 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2274 00:22:45.963938 [DutyScan_Calibration_Flow] ====Done====
2275 00:22:45.964447
2276 00:22:45.967195 [DutyScan_Calibration_Flow] k_type=2
2277 00:22:45.982259
2278 00:22:45.982688 ==DQ 0 ==
2279 00:22:45.985414 Final DQ duty delay cell = -4
2280 00:22:45.989003 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2281 00:22:45.992156 [-4] MIN Duty = 4813%(X100), DQS PI = 44
2282 00:22:45.995499 [-4] AVG Duty = 4937%(X100)
2283 00:22:45.995900
2284 00:22:45.996303 ==DQ 1 ==
2285 00:22:45.999087 Final DQ duty delay cell = -4
2286 00:22:46.002328 [-4] MAX Duty = 5062%(X100), DQS PI = 6
2287 00:22:46.006071 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2288 00:22:46.009213 [-4] AVG Duty = 4984%(X100)
2289 00:22:46.009620
2290 00:22:46.012894 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2291 00:22:46.013391
2292 00:22:46.015948 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2293 00:22:46.019242 [DutyScan_Calibration_Flow] ====Done====
2294 00:22:46.019643 ==
2295 00:22:46.022156 Dram Type= 6, Freq= 0, CH_1, rank 0
2296 00:22:46.025531 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2297 00:22:46.025934 ==
2298 00:22:46.029136 [Duty_Offset_Calibration]
2299 00:22:46.029539 B0:0 B1:5 CA:-5
2300 00:22:46.029938
2301 00:22:46.032265 [DutyScan_Calibration_Flow] k_type=0
2302 00:22:46.042955
2303 00:22:46.043356 ==CLK 0==
2304 00:22:46.046330 Final CLK duty delay cell = 0
2305 00:22:46.050345 [0] MAX Duty = 5094%(X100), DQS PI = 24
2306 00:22:46.052813 [0] MIN Duty = 4907%(X100), DQS PI = 2
2307 00:22:46.053226 [0] AVG Duty = 5000%(X100)
2308 00:22:46.056335
2309 00:22:46.056793 CH1 CLK Duty spec in!! Max-Min= 187%
2310 00:22:46.063068 [DutyScan_Calibration_Flow] ====Done====
2311 00:22:46.063460
2312 00:22:46.065882 [DutyScan_Calibration_Flow] k_type=1
2313 00:22:46.081603
2314 00:22:46.082174 ==DQS 0 ==
2315 00:22:46.084986 Final DQS duty delay cell = 0
2316 00:22:46.088494 [0] MAX Duty = 5125%(X100), DQS PI = 16
2317 00:22:46.091056 [0] MIN Duty = 4875%(X100), DQS PI = 40
2318 00:22:46.094515 [0] AVG Duty = 5000%(X100)
2319 00:22:46.094952
2320 00:22:46.095252 ==DQS 1 ==
2321 00:22:46.097909 Final DQS duty delay cell = -4
2322 00:22:46.101248 [-4] MAX Duty = 5000%(X100), DQS PI = 18
2323 00:22:46.104779 [-4] MIN Duty = 4907%(X100), DQS PI = 56
2324 00:22:46.108091 [-4] AVG Duty = 4953%(X100)
2325 00:22:46.108638
2326 00:22:46.111373 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2327 00:22:46.111804
2328 00:22:46.114360 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2329 00:22:46.117857 [DutyScan_Calibration_Flow] ====Done====
2330 00:22:46.118406
2331 00:22:46.121169 [DutyScan_Calibration_Flow] k_type=3
2332 00:22:46.137069
2333 00:22:46.137588 ==DQM 0 ==
2334 00:22:46.139762 Final DQM duty delay cell = -4
2335 00:22:46.143378 [-4] MAX Duty = 5062%(X100), DQS PI = 30
2336 00:22:46.146921 [-4] MIN Duty = 4844%(X100), DQS PI = 42
2337 00:22:46.150011 [-4] AVG Duty = 4953%(X100)
2338 00:22:46.150570
2339 00:22:46.150913 ==DQM 1 ==
2340 00:22:46.153480 Final DQM duty delay cell = -4
2341 00:22:46.157008 [-4] MAX Duty = 5062%(X100), DQS PI = 4
2342 00:22:46.160101 [-4] MIN Duty = 4906%(X100), DQS PI = 44
2343 00:22:46.163609 [-4] AVG Duty = 4984%(X100)
2344 00:22:46.164196
2345 00:22:46.166643 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2346 00:22:46.167240
2347 00:22:46.170041 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2348 00:22:46.173544 [DutyScan_Calibration_Flow] ====Done====
2349 00:22:46.174064
2350 00:22:46.176490 [DutyScan_Calibration_Flow] k_type=2
2351 00:22:46.193915
2352 00:22:46.194523 ==DQ 0 ==
2353 00:22:46.197059 Final DQ duty delay cell = 0
2354 00:22:46.200677 [0] MAX Duty = 5062%(X100), DQS PI = 0
2355 00:22:46.203809 [0] MIN Duty = 4938%(X100), DQS PI = 44
2356 00:22:46.204252 [0] AVG Duty = 5000%(X100)
2357 00:22:46.204650
2358 00:22:46.206899 ==DQ 1 ==
2359 00:22:46.210516 Final DQ duty delay cell = 0
2360 00:22:46.214153 [0] MAX Duty = 5000%(X100), DQS PI = 6
2361 00:22:46.216887 [0] MIN Duty = 4876%(X100), DQS PI = 30
2362 00:22:46.217441 [0] AVG Duty = 4938%(X100)
2363 00:22:46.217789
2364 00:22:46.220164 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2365 00:22:46.220597
2366 00:22:46.223510 CH1 DQ 1 Duty spec in!! Max-Min= 124%
2367 00:22:46.230010 [DutyScan_Calibration_Flow] ====Done====
2368 00:22:46.233723 nWR fixed to 30
2369 00:22:46.234419 [ModeRegInit_LP4] CH0 RK0
2370 00:22:46.236815 [ModeRegInit_LP4] CH0 RK1
2371 00:22:46.240533 [ModeRegInit_LP4] CH1 RK0
2372 00:22:46.240922 [ModeRegInit_LP4] CH1 RK1
2373 00:22:46.243591 match AC timing 6
2374 00:22:46.246772 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2375 00:22:46.249896 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2376 00:22:46.256978 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2377 00:22:46.260369 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2378 00:22:46.266825 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2379 00:22:46.267188 ==
2380 00:22:46.270127 Dram Type= 6, Freq= 0, CH_0, rank 0
2381 00:22:46.273415 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2382 00:22:46.273777 ==
2383 00:22:46.279980 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2384 00:22:46.283428 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2385 00:22:46.293413 [CA 0] Center 39 (9~70) winsize 62
2386 00:22:46.296991 [CA 1] Center 39 (8~70) winsize 63
2387 00:22:46.300066 [CA 2] Center 36 (5~67) winsize 63
2388 00:22:46.303335 [CA 3] Center 35 (4~66) winsize 63
2389 00:22:46.306798 [CA 4] Center 34 (3~65) winsize 63
2390 00:22:46.310321 [CA 5] Center 33 (3~64) winsize 62
2391 00:22:46.310840
2392 00:22:46.313522 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2393 00:22:46.314031
2394 00:22:46.316835 [CATrainingPosCal] consider 1 rank data
2395 00:22:46.320431 u2DelayCellTimex100 = 270/100 ps
2396 00:22:46.323302 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2397 00:22:46.326610 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2398 00:22:46.333045 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2399 00:22:46.336593 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2400 00:22:46.340159 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2401 00:22:46.343292 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2402 00:22:46.343684
2403 00:22:46.346440 CA PerBit enable=1, Macro0, CA PI delay=33
2404 00:22:46.346831
2405 00:22:46.350472 [CBTSetCACLKResult] CA Dly = 33
2406 00:22:46.350859 CS Dly: 7 (0~38)
2407 00:22:46.353411 ==
2408 00:22:46.353804 Dram Type= 6, Freq= 0, CH_0, rank 1
2409 00:22:46.360239 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2410 00:22:46.360734 ==
2411 00:22:46.363656 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2412 00:22:46.370101 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
2413 00:22:46.379010 [CA 0] Center 39 (9~70) winsize 62
2414 00:22:46.382188 [CA 1] Center 38 (8~69) winsize 62
2415 00:22:46.385279 [CA 2] Center 35 (5~66) winsize 62
2416 00:22:46.388582 [CA 3] Center 35 (4~66) winsize 63
2417 00:22:46.392499 [CA 4] Center 33 (3~64) winsize 62
2418 00:22:46.395793 [CA 5] Center 33 (3~64) winsize 62
2419 00:22:46.396227
2420 00:22:46.398809 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2421 00:22:46.399333
2422 00:22:46.402808 [CATrainingPosCal] consider 2 rank data
2423 00:22:46.405698 u2DelayCellTimex100 = 270/100 ps
2424 00:22:46.409172 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2425 00:22:46.412094 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2426 00:22:46.418928 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2427 00:22:46.422591 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2428 00:22:46.425801 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2429 00:22:46.429420 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2430 00:22:46.429939
2431 00:22:46.432413 CA PerBit enable=1, Macro0, CA PI delay=33
2432 00:22:46.432931
2433 00:22:46.435349 [CBTSetCACLKResult] CA Dly = 33
2434 00:22:46.435882 CS Dly: 7 (0~39)
2435 00:22:46.436251
2436 00:22:46.438485 ----->DramcWriteLeveling(PI) begin...
2437 00:22:46.442000 ==
2438 00:22:46.442592 Dram Type= 6, Freq= 0, CH_0, rank 0
2439 00:22:46.448598 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2440 00:22:46.449229 ==
2441 00:22:46.451978 Write leveling (Byte 0): 27 => 27
2442 00:22:46.455509 Write leveling (Byte 1): 27 => 27
2443 00:22:46.458658 DramcWriteLeveling(PI) end<-----
2444 00:22:46.459048
2445 00:22:46.459351 ==
2446 00:22:46.461936 Dram Type= 6, Freq= 0, CH_0, rank 0
2447 00:22:46.465499 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2448 00:22:46.466050 ==
2449 00:22:46.469040 [Gating] SW mode calibration
2450 00:22:46.475785 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2451 00:22:46.478769 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2452 00:22:46.485621 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2453 00:22:46.489082 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2454 00:22:46.492161 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2455 00:22:46.499093 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2456 00:22:46.502209 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
2457 00:22:46.505782 0 11 20 | B1->B0 | 2d2d 2a2a | 1 1 | (1 0) (1 0)
2458 00:22:46.512200 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2459 00:22:46.515206 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2460 00:22:46.518853 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2461 00:22:46.526024 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2462 00:22:46.529338 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2463 00:22:46.532015 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2464 00:22:46.538951 0 12 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2465 00:22:46.542295 0 12 20 | B1->B0 | 3c3c 4242 | 1 0 | (0 0) (0 0)
2466 00:22:46.545650 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2467 00:22:46.552086 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2468 00:22:46.555332 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2469 00:22:46.558762 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2470 00:22:46.562618 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2471 00:22:46.568958 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2472 00:22:46.572155 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2473 00:22:46.575222 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2474 00:22:46.581848 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2475 00:22:46.585396 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2476 00:22:46.589149 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2477 00:22:46.595438 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2478 00:22:46.598697 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2479 00:22:46.602496 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2480 00:22:46.608627 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2481 00:22:46.611747 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2482 00:22:46.615330 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2483 00:22:46.621891 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2484 00:22:46.625122 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2485 00:22:46.628878 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2486 00:22:46.635969 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2487 00:22:46.638653 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2488 00:22:46.642349 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2489 00:22:46.648856 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2490 00:22:46.652166 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2491 00:22:46.655254 Total UI for P1: 0, mck2ui 16
2492 00:22:46.659502 best dqsien dly found for B0: ( 0, 15, 18)
2493 00:22:46.662360 Total UI for P1: 0, mck2ui 16
2494 00:22:46.665634 best dqsien dly found for B1: ( 0, 15, 20)
2495 00:22:46.668876 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2496 00:22:46.673137 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2497 00:22:46.673671
2498 00:22:46.675314 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2499 00:22:46.678949 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2500 00:22:46.682112 [Gating] SW calibration Done
2501 00:22:46.682594 ==
2502 00:22:46.685438 Dram Type= 6, Freq= 0, CH_0, rank 0
2503 00:22:46.688960 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2504 00:22:46.689447 ==
2505 00:22:46.692246 RX Vref Scan: 0
2506 00:22:46.692671
2507 00:22:46.695276 RX Vref 0 -> 0, step: 1
2508 00:22:46.695709
2509 00:22:46.696041 RX Delay -40 -> 252, step: 8
2510 00:22:46.702304 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2511 00:22:46.705855 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2512 00:22:46.708962 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2513 00:22:46.712339 iDelay=200, Bit 3, Center 111 (32 ~ 191) 160
2514 00:22:46.715640 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2515 00:22:46.722191 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2516 00:22:46.725597 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2517 00:22:46.728795 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2518 00:22:46.731786 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2519 00:22:46.735558 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2520 00:22:46.742246 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2521 00:22:46.745360 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2522 00:22:46.748707 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2523 00:22:46.752170 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2524 00:22:46.755228 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2525 00:22:46.762137 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2526 00:22:46.762662 ==
2527 00:22:46.765197 Dram Type= 6, Freq= 0, CH_0, rank 0
2528 00:22:46.768238 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2529 00:22:46.768758 ==
2530 00:22:46.769258 DQS Delay:
2531 00:22:46.771870 DQS0 = 0, DQS1 = 0
2532 00:22:46.772262 DQM Delay:
2533 00:22:46.775214 DQM0 = 115, DQM1 = 106
2534 00:22:46.775618 DQ Delay:
2535 00:22:46.778350 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =111
2536 00:22:46.781830 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2537 00:22:46.785589 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =99
2538 00:22:46.788795 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2539 00:22:46.789234
2540 00:22:46.789574
2541 00:22:46.789936 ==
2542 00:22:46.792061 Dram Type= 6, Freq= 0, CH_0, rank 0
2543 00:22:46.798527 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2544 00:22:46.798927 ==
2545 00:22:46.799232
2546 00:22:46.799513
2547 00:22:46.799810 TX Vref Scan disable
2548 00:22:46.802369 == TX Byte 0 ==
2549 00:22:46.805375 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2550 00:22:46.808626 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2551 00:22:46.812020 == TX Byte 1 ==
2552 00:22:46.815705 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2553 00:22:46.822338 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2554 00:22:46.822734 ==
2555 00:22:46.825338 Dram Type= 6, Freq= 0, CH_0, rank 0
2556 00:22:46.828683 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2557 00:22:46.829086 ==
2558 00:22:46.839666 TX Vref=22, minBit 10, minWin=25, winSum=419
2559 00:22:46.843031 TX Vref=24, minBit 13, minWin=25, winSum=423
2560 00:22:46.846331 TX Vref=26, minBit 8, minWin=26, winSum=434
2561 00:22:46.849964 TX Vref=28, minBit 9, minWin=26, winSum=438
2562 00:22:46.853706 TX Vref=30, minBit 10, minWin=26, winSum=435
2563 00:22:46.859797 TX Vref=32, minBit 5, minWin=26, winSum=436
2564 00:22:46.863533 [TxChooseVref] Worse bit 9, Min win 26, Win sum 438, Final Vref 28
2565 00:22:46.864019
2566 00:22:46.866321 Final TX Range 1 Vref 28
2567 00:22:46.866715
2568 00:22:46.867016 ==
2569 00:22:46.869951 Dram Type= 6, Freq= 0, CH_0, rank 0
2570 00:22:46.873391 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2571 00:22:46.876244 ==
2572 00:22:46.876684
2573 00:22:46.877017
2574 00:22:46.877303 TX Vref Scan disable
2575 00:22:46.879618 == TX Byte 0 ==
2576 00:22:46.883201 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2577 00:22:46.886508 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2578 00:22:46.889543 == TX Byte 1 ==
2579 00:22:46.892877 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2580 00:22:46.896591 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2581 00:22:46.900049
2582 00:22:46.900487 [DATLAT]
2583 00:22:46.900792 Freq=1200, CH0 RK0
2584 00:22:46.901077
2585 00:22:46.903073 DATLAT Default: 0xd
2586 00:22:46.903467 0, 0xFFFF, sum = 0
2587 00:22:46.906190 1, 0xFFFF, sum = 0
2588 00:22:46.906627 2, 0xFFFF, sum = 0
2589 00:22:46.909490 3, 0xFFFF, sum = 0
2590 00:22:46.909887 4, 0xFFFF, sum = 0
2591 00:22:46.913552 5, 0xFFFF, sum = 0
2592 00:22:46.916508 6, 0xFFFF, sum = 0
2593 00:22:46.916909 7, 0xFFFF, sum = 0
2594 00:22:46.919771 8, 0xFFFF, sum = 0
2595 00:22:46.920173 9, 0xFFFF, sum = 0
2596 00:22:46.923085 10, 0xFFFF, sum = 0
2597 00:22:46.923489 11, 0x0, sum = 1
2598 00:22:46.926385 12, 0x0, sum = 2
2599 00:22:46.926796 13, 0x0, sum = 3
2600 00:22:46.927111 14, 0x0, sum = 4
2601 00:22:46.929821 best_step = 12
2602 00:22:46.930238
2603 00:22:46.930554 ==
2604 00:22:46.933306 Dram Type= 6, Freq= 0, CH_0, rank 0
2605 00:22:46.936462 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2606 00:22:46.936956 ==
2607 00:22:46.939905 RX Vref Scan: 1
2608 00:22:46.940304
2609 00:22:46.943050 Set Vref Range= 32 -> 127
2610 00:22:46.943449
2611 00:22:46.943755 RX Vref 32 -> 127, step: 1
2612 00:22:46.944055
2613 00:22:46.946923 RX Delay -21 -> 252, step: 4
2614 00:22:46.947318
2615 00:22:46.949855 Set Vref, RX VrefLevel [Byte0]: 32
2616 00:22:46.953333 [Byte1]: 32
2617 00:22:46.956768
2618 00:22:46.957259 Set Vref, RX VrefLevel [Byte0]: 33
2619 00:22:46.960058 [Byte1]: 33
2620 00:22:46.964743
2621 00:22:46.965231 Set Vref, RX VrefLevel [Byte0]: 34
2622 00:22:46.968395 [Byte1]: 34
2623 00:22:46.972713
2624 00:22:46.973246 Set Vref, RX VrefLevel [Byte0]: 35
2625 00:22:46.976891 [Byte1]: 35
2626 00:22:46.980599
2627 00:22:46.981043 Set Vref, RX VrefLevel [Byte0]: 36
2628 00:22:46.983494 [Byte1]: 36
2629 00:22:46.988295
2630 00:22:46.988815 Set Vref, RX VrefLevel [Byte0]: 37
2631 00:22:46.991522 [Byte1]: 37
2632 00:22:46.996267
2633 00:22:46.996799 Set Vref, RX VrefLevel [Byte0]: 38
2634 00:22:47.000042 [Byte1]: 38
2635 00:22:47.004232
2636 00:22:47.004756 Set Vref, RX VrefLevel [Byte0]: 39
2637 00:22:47.007446 [Byte1]: 39
2638 00:22:47.012155
2639 00:22:47.012670 Set Vref, RX VrefLevel [Byte0]: 40
2640 00:22:47.015477 [Byte1]: 40
2641 00:22:47.021056
2642 00:22:47.021492 Set Vref, RX VrefLevel [Byte0]: 41
2643 00:22:47.023071 [Byte1]: 41
2644 00:22:47.027528
2645 00:22:47.028061 Set Vref, RX VrefLevel [Byte0]: 42
2646 00:22:47.031213 [Byte1]: 42
2647 00:22:47.035685
2648 00:22:47.036117 Set Vref, RX VrefLevel [Byte0]: 43
2649 00:22:47.038865 [Byte1]: 43
2650 00:22:47.043966
2651 00:22:47.044514 Set Vref, RX VrefLevel [Byte0]: 44
2652 00:22:47.047109 [Byte1]: 44
2653 00:22:47.051783
2654 00:22:47.052307 Set Vref, RX VrefLevel [Byte0]: 45
2655 00:22:47.055151 [Byte1]: 45
2656 00:22:47.059900
2657 00:22:47.060422 Set Vref, RX VrefLevel [Byte0]: 46
2658 00:22:47.063073 [Byte1]: 46
2659 00:22:47.067739
2660 00:22:47.068266 Set Vref, RX VrefLevel [Byte0]: 47
2661 00:22:47.070879 [Byte1]: 47
2662 00:22:47.075758
2663 00:22:47.076287 Set Vref, RX VrefLevel [Byte0]: 48
2664 00:22:47.078908 [Byte1]: 48
2665 00:22:47.083089
2666 00:22:47.083606 Set Vref, RX VrefLevel [Byte0]: 49
2667 00:22:47.087378 [Byte1]: 49
2668 00:22:47.091285
2669 00:22:47.091725 Set Vref, RX VrefLevel [Byte0]: 50
2670 00:22:47.094545 [Byte1]: 50
2671 00:22:47.099373
2672 00:22:47.099954 Set Vref, RX VrefLevel [Byte0]: 51
2673 00:22:47.102575 [Byte1]: 51
2674 00:22:47.107205
2675 00:22:47.107637 Set Vref, RX VrefLevel [Byte0]: 52
2676 00:22:47.110593 [Byte1]: 52
2677 00:22:47.114753
2678 00:22:47.115295 Set Vref, RX VrefLevel [Byte0]: 53
2679 00:22:47.118439 [Byte1]: 53
2680 00:22:47.122877
2681 00:22:47.123446 Set Vref, RX VrefLevel [Byte0]: 54
2682 00:22:47.126394 [Byte1]: 54
2683 00:22:47.130797
2684 00:22:47.131237 Set Vref, RX VrefLevel [Byte0]: 55
2685 00:22:47.134341 [Byte1]: 55
2686 00:22:47.138747
2687 00:22:47.139185 Set Vref, RX VrefLevel [Byte0]: 56
2688 00:22:47.142013 [Byte1]: 56
2689 00:22:47.146881
2690 00:22:47.147403 Set Vref, RX VrefLevel [Byte0]: 57
2691 00:22:47.150005 [Byte1]: 57
2692 00:22:47.154755
2693 00:22:47.155321 Set Vref, RX VrefLevel [Byte0]: 58
2694 00:22:47.157917 [Byte1]: 58
2695 00:22:47.162706
2696 00:22:47.163230 Set Vref, RX VrefLevel [Byte0]: 59
2697 00:22:47.166375 [Byte1]: 59
2698 00:22:47.170963
2699 00:22:47.171484 Set Vref, RX VrefLevel [Byte0]: 60
2700 00:22:47.173938 [Byte1]: 60
2701 00:22:47.178757
2702 00:22:47.179276 Set Vref, RX VrefLevel [Byte0]: 61
2703 00:22:47.181544 [Byte1]: 61
2704 00:22:47.186828
2705 00:22:47.187297 Set Vref, RX VrefLevel [Byte0]: 62
2706 00:22:47.189550 [Byte1]: 62
2707 00:22:47.194600
2708 00:22:47.195140 Set Vref, RX VrefLevel [Byte0]: 63
2709 00:22:47.198392 [Byte1]: 63
2710 00:22:47.202636
2711 00:22:47.203162 Set Vref, RX VrefLevel [Byte0]: 64
2712 00:22:47.205619 [Byte1]: 64
2713 00:22:47.209899
2714 00:22:47.210467 Set Vref, RX VrefLevel [Byte0]: 65
2715 00:22:47.213233 [Byte1]: 65
2716 00:22:47.218430
2717 00:22:47.218956 Set Vref, RX VrefLevel [Byte0]: 66
2718 00:22:47.221667 [Byte1]: 66
2719 00:22:47.226010
2720 00:22:47.226583 Set Vref, RX VrefLevel [Byte0]: 67
2721 00:22:47.229368 [Byte1]: 67
2722 00:22:47.234003
2723 00:22:47.234784 Final RX Vref Byte 0 = 47 to rank0
2724 00:22:47.237054 Final RX Vref Byte 1 = 45 to rank0
2725 00:22:47.241016 Final RX Vref Byte 0 = 47 to rank1
2726 00:22:47.243588 Final RX Vref Byte 1 = 45 to rank1==
2727 00:22:47.247477 Dram Type= 6, Freq= 0, CH_0, rank 0
2728 00:22:47.254314 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2729 00:22:47.254837 ==
2730 00:22:47.255177 DQS Delay:
2731 00:22:47.255488 DQS0 = 0, DQS1 = 0
2732 00:22:47.257485 DQM Delay:
2733 00:22:47.257933 DQM0 = 113, DQM1 = 104
2734 00:22:47.260596 DQ Delay:
2735 00:22:47.263597 DQ0 =110, DQ1 =114, DQ2 =112, DQ3 =108
2736 00:22:47.266994 DQ4 =118, DQ5 =104, DQ6 =124, DQ7 =120
2737 00:22:47.270815 DQ8 =94, DQ9 =86, DQ10 =106, DQ11 =96
2738 00:22:47.274424 DQ12 =110, DQ13 =112, DQ14 =118, DQ15 =114
2739 00:22:47.274945
2740 00:22:47.275278
2741 00:22:47.280647 [DQSOSCAuto] RK0, (LSB)MR18= 0xe0e, (MSB)MR19= 0x404, tDQSOscB0 = 404 ps tDQSOscB1 = 404 ps
2742 00:22:47.283629 CH0 RK0: MR19=404, MR18=E0E
2743 00:22:47.290442 CH0_RK0: MR19=0x404, MR18=0xE0E, DQSOSC=404, MR23=63, INC=40, DEC=26
2744 00:22:47.290967
2745 00:22:47.294239 ----->DramcWriteLeveling(PI) begin...
2746 00:22:47.294684 ==
2747 00:22:47.297447 Dram Type= 6, Freq= 0, CH_0, rank 1
2748 00:22:47.300578 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2749 00:22:47.301120 ==
2750 00:22:47.303800 Write leveling (Byte 0): 27 => 27
2751 00:22:47.307469 Write leveling (Byte 1): 25 => 25
2752 00:22:47.310990 DramcWriteLeveling(PI) end<-----
2753 00:22:47.311519
2754 00:22:47.311860 ==
2755 00:22:47.313776 Dram Type= 6, Freq= 0, CH_0, rank 1
2756 00:22:47.317181 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2757 00:22:47.320694 ==
2758 00:22:47.321221 [Gating] SW mode calibration
2759 00:22:47.327033 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2760 00:22:47.334189 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2761 00:22:47.337515 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2762 00:22:47.344118 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2763 00:22:47.347368 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2764 00:22:47.350673 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2765 00:22:47.356971 0 11 16 | B1->B0 | 3434 3232 | 1 1 | (1 0) (1 0)
2766 00:22:47.360104 0 11 20 | B1->B0 | 2c2c 2323 | 0 0 | (1 1) (0 0)
2767 00:22:47.364359 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2768 00:22:47.370499 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2769 00:22:47.373957 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2770 00:22:47.377100 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2771 00:22:47.383795 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2772 00:22:47.386864 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2773 00:22:47.390398 0 12 16 | B1->B0 | 2929 3939 | 0 0 | (0 0) (0 0)
2774 00:22:47.397151 0 12 20 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
2775 00:22:47.400773 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2776 00:22:47.403385 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2777 00:22:47.410582 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2778 00:22:47.413479 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2779 00:22:47.416711 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2780 00:22:47.420075 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2781 00:22:47.426776 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2782 00:22:47.430093 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2783 00:22:47.434203 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2784 00:22:47.440170 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2785 00:22:47.443583 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2786 00:22:47.446903 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2787 00:22:47.453663 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2788 00:22:47.457268 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2789 00:22:47.460012 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2790 00:22:47.467434 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2791 00:22:47.470680 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2792 00:22:47.473752 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2793 00:22:47.480648 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2794 00:22:47.484045 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2795 00:22:47.486904 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2796 00:22:47.493804 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2797 00:22:47.497575 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2798 00:22:47.500830 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2799 00:22:47.504539 Total UI for P1: 0, mck2ui 16
2800 00:22:47.507071 best dqsien dly found for B0: ( 0, 15, 16)
2801 00:22:47.510597 Total UI for P1: 0, mck2ui 16
2802 00:22:47.513904 best dqsien dly found for B1: ( 0, 15, 16)
2803 00:22:47.517269 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
2804 00:22:47.520831 best DQS1 dly(MCK, UI, PI) = (0, 15, 16)
2805 00:22:47.521512
2806 00:22:47.524394 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
2807 00:22:47.530538 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 16)
2808 00:22:47.530980 [Gating] SW calibration Done
2809 00:22:47.531327 ==
2810 00:22:47.533667 Dram Type= 6, Freq= 0, CH_0, rank 1
2811 00:22:47.540502 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2812 00:22:47.541078 ==
2813 00:22:47.541652 RX Vref Scan: 0
2814 00:22:47.542145
2815 00:22:47.543675 RX Vref 0 -> 0, step: 1
2816 00:22:47.544190
2817 00:22:47.547220 RX Delay -40 -> 252, step: 8
2818 00:22:47.550326 iDelay=200, Bit 0, Center 107 (32 ~ 183) 152
2819 00:22:47.553796 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2820 00:22:47.557322 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2821 00:22:47.560438 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2822 00:22:47.566941 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2823 00:22:47.570330 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2824 00:22:47.573611 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2825 00:22:47.577182 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2826 00:22:47.580508 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2827 00:22:47.587524 iDelay=200, Bit 9, Center 87 (16 ~ 159) 144
2828 00:22:47.590335 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2829 00:22:47.593801 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2830 00:22:47.596998 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2831 00:22:47.600595 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2832 00:22:47.607042 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2833 00:22:47.610146 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2834 00:22:47.610612 ==
2835 00:22:47.613571 Dram Type= 6, Freq= 0, CH_0, rank 1
2836 00:22:47.616717 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2837 00:22:47.617159 ==
2838 00:22:47.620672 DQS Delay:
2839 00:22:47.621185 DQS0 = 0, DQS1 = 0
2840 00:22:47.621533 DQM Delay:
2841 00:22:47.623810 DQM0 = 114, DQM1 = 105
2842 00:22:47.624330 DQ Delay:
2843 00:22:47.627136 DQ0 =107, DQ1 =115, DQ2 =115, DQ3 =111
2844 00:22:47.630168 DQ4 =115, DQ5 =107, DQ6 =119, DQ7 =123
2845 00:22:47.633836 DQ8 =91, DQ9 =87, DQ10 =107, DQ11 =99
2846 00:22:47.637452 DQ12 =115, DQ13 =111, DQ14 =119, DQ15 =115
2847 00:22:47.640616
2848 00:22:47.641131
2849 00:22:47.641468 ==
2850 00:22:47.643563 Dram Type= 6, Freq= 0, CH_0, rank 1
2851 00:22:47.647450 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2852 00:22:47.647971 ==
2853 00:22:47.648316
2854 00:22:47.648630
2855 00:22:47.650915 TX Vref Scan disable
2856 00:22:47.651383 == TX Byte 0 ==
2857 00:22:47.657352 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2858 00:22:47.660763 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2859 00:22:47.661284 == TX Byte 1 ==
2860 00:22:47.667006 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2861 00:22:47.670996 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2862 00:22:47.671527 ==
2863 00:22:47.673867 Dram Type= 6, Freq= 0, CH_0, rank 1
2864 00:22:47.676808 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2865 00:22:47.677253 ==
2866 00:22:47.689106 TX Vref=22, minBit 8, minWin=25, winSum=415
2867 00:22:47.692761 TX Vref=24, minBit 9, minWin=25, winSum=419
2868 00:22:47.696225 TX Vref=26, minBit 9, minWin=25, winSum=426
2869 00:22:47.699248 TX Vref=28, minBit 0, minWin=26, winSum=426
2870 00:22:47.702934 TX Vref=30, minBit 9, minWin=26, winSum=437
2871 00:22:47.705839 TX Vref=32, minBit 4, minWin=26, winSum=431
2872 00:22:47.712833 [TxChooseVref] Worse bit 9, Min win 26, Win sum 437, Final Vref 30
2873 00:22:47.713357
2874 00:22:47.716302 Final TX Range 1 Vref 30
2875 00:22:47.716819
2876 00:22:47.717161 ==
2877 00:22:47.719514 Dram Type= 6, Freq= 0, CH_0, rank 1
2878 00:22:47.722453 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2879 00:22:47.722901 ==
2880 00:22:47.723242
2881 00:22:47.725841
2882 00:22:47.726324 TX Vref Scan disable
2883 00:22:47.729150 == TX Byte 0 ==
2884 00:22:47.732620 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2885 00:22:47.736022 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2886 00:22:47.739241 == TX Byte 1 ==
2887 00:22:47.742595 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2888 00:22:47.746305 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2889 00:22:47.746876
2890 00:22:47.749481 [DATLAT]
2891 00:22:47.750001 Freq=1200, CH0 RK1
2892 00:22:47.750392
2893 00:22:47.752835 DATLAT Default: 0xc
2894 00:22:47.753361 0, 0xFFFF, sum = 0
2895 00:22:47.755603 1, 0xFFFF, sum = 0
2896 00:22:47.756074 2, 0xFFFF, sum = 0
2897 00:22:47.759154 3, 0xFFFF, sum = 0
2898 00:22:47.759601 4, 0xFFFF, sum = 0
2899 00:22:47.762603 5, 0xFFFF, sum = 0
2900 00:22:47.763047 6, 0xFFFF, sum = 0
2901 00:22:47.765926 7, 0xFFFF, sum = 0
2902 00:22:47.769389 8, 0xFFFF, sum = 0
2903 00:22:47.769936 9, 0xFFFF, sum = 0
2904 00:22:47.772198 10, 0xFFFF, sum = 0
2905 00:22:47.772645 11, 0x0, sum = 1
2906 00:22:47.775876 12, 0x0, sum = 2
2907 00:22:47.776415 13, 0x0, sum = 3
2908 00:22:47.776763 14, 0x0, sum = 4
2909 00:22:47.779687 best_step = 12
2910 00:22:47.780205
2911 00:22:47.780543 ==
2912 00:22:47.782430 Dram Type= 6, Freq= 0, CH_0, rank 1
2913 00:22:47.785968 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2914 00:22:47.786464 ==
2915 00:22:47.789161 RX Vref Scan: 0
2916 00:22:47.789592
2917 00:22:47.789930 RX Vref 0 -> 0, step: 1
2918 00:22:47.792204
2919 00:22:47.792638 RX Delay -29 -> 252, step: 4
2920 00:22:47.799540 iDelay=199, Bit 0, Center 110 (39 ~ 182) 144
2921 00:22:47.802990 iDelay=199, Bit 1, Center 116 (43 ~ 190) 148
2922 00:22:47.806465 iDelay=199, Bit 2, Center 112 (43 ~ 182) 140
2923 00:22:47.809765 iDelay=199, Bit 3, Center 108 (39 ~ 178) 140
2924 00:22:47.813280 iDelay=199, Bit 4, Center 118 (47 ~ 190) 144
2925 00:22:47.819850 iDelay=199, Bit 5, Center 106 (35 ~ 178) 144
2926 00:22:47.823029 iDelay=199, Bit 6, Center 124 (55 ~ 194) 140
2927 00:22:47.826401 iDelay=199, Bit 7, Center 124 (51 ~ 198) 148
2928 00:22:47.829997 iDelay=199, Bit 8, Center 92 (31 ~ 154) 124
2929 00:22:47.833018 iDelay=199, Bit 9, Center 88 (27 ~ 150) 124
2930 00:22:47.836527 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
2931 00:22:47.842826 iDelay=199, Bit 11, Center 96 (35 ~ 158) 124
2932 00:22:47.846167 iDelay=199, Bit 12, Center 110 (47 ~ 174) 128
2933 00:22:47.849406 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
2934 00:22:47.853102 iDelay=199, Bit 14, Center 114 (51 ~ 178) 128
2935 00:22:47.859956 iDelay=199, Bit 15, Center 114 (51 ~ 178) 128
2936 00:22:47.860484 ==
2937 00:22:47.863177 Dram Type= 6, Freq= 0, CH_0, rank 1
2938 00:22:47.866458 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2939 00:22:47.866902 ==
2940 00:22:47.867240 DQS Delay:
2941 00:22:47.869637 DQS0 = 0, DQS1 = 0
2942 00:22:47.870076 DQM Delay:
2943 00:22:47.873466 DQM0 = 114, DQM1 = 104
2944 00:22:47.873993 DQ Delay:
2945 00:22:47.876772 DQ0 =110, DQ1 =116, DQ2 =112, DQ3 =108
2946 00:22:47.879812 DQ4 =118, DQ5 =106, DQ6 =124, DQ7 =124
2947 00:22:47.883156 DQ8 =92, DQ9 =88, DQ10 =110, DQ11 =96
2948 00:22:47.886492 DQ12 =110, DQ13 =112, DQ14 =114, DQ15 =114
2949 00:22:47.886936
2950 00:22:47.887291
2951 00:22:47.896425 [DQSOSCAuto] RK1, (LSB)MR18= 0x1111, (MSB)MR19= 0x404, tDQSOscB0 = 403 ps tDQSOscB1 = 403 ps
2952 00:22:47.899460 CH0 RK1: MR19=404, MR18=1111
2953 00:22:47.903162 CH0_RK1: MR19=0x404, MR18=0x1111, DQSOSC=403, MR23=63, INC=40, DEC=26
2954 00:22:47.906525 [RxdqsGatingPostProcess] freq 1200
2955 00:22:47.913278 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2956 00:22:47.916725 Pre-setting of DQS Precalculation
2957 00:22:47.919756 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2958 00:22:47.920288 ==
2959 00:22:47.923268 Dram Type= 6, Freq= 0, CH_1, rank 0
2960 00:22:47.929907 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2961 00:22:47.930480 ==
2962 00:22:47.932972 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2963 00:22:47.939450 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2964 00:22:47.948528 [CA 0] Center 37 (7~68) winsize 62
2965 00:22:47.951647 [CA 1] Center 37 (7~68) winsize 62
2966 00:22:47.954948 [CA 2] Center 34 (4~65) winsize 62
2967 00:22:47.958365 [CA 3] Center 33 (3~64) winsize 62
2968 00:22:47.961646 [CA 4] Center 32 (2~63) winsize 62
2969 00:22:47.964692 [CA 5] Center 32 (2~63) winsize 62
2970 00:22:47.965133
2971 00:22:47.968299 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2972 00:22:47.968742
2973 00:22:47.971323 [CATrainingPosCal] consider 1 rank data
2974 00:22:47.974879 u2DelayCellTimex100 = 270/100 ps
2975 00:22:47.978686 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2976 00:22:47.981571 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2977 00:22:47.988099 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2978 00:22:47.991658 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2979 00:22:47.994803 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2980 00:22:47.998114 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2981 00:22:47.998630
2982 00:22:48.001732 CA PerBit enable=1, Macro0, CA PI delay=32
2983 00:22:48.002329
2984 00:22:48.004814 [CBTSetCACLKResult] CA Dly = 32
2985 00:22:48.005253 CS Dly: 6 (0~37)
2986 00:22:48.005594 ==
2987 00:22:48.007990 Dram Type= 6, Freq= 0, CH_1, rank 1
2988 00:22:48.014607 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2989 00:22:48.015055 ==
2990 00:22:48.018085 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2991 00:22:48.024605 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2992 00:22:48.033761 [CA 0] Center 37 (7~68) winsize 62
2993 00:22:48.036542 [CA 1] Center 37 (6~68) winsize 63
2994 00:22:48.040260 [CA 2] Center 34 (3~65) winsize 63
2995 00:22:48.043621 [CA 3] Center 33 (3~64) winsize 62
2996 00:22:48.046486 [CA 4] Center 32 (2~63) winsize 62
2997 00:22:48.049735 [CA 5] Center 32 (2~62) winsize 61
2998 00:22:48.050130
2999 00:22:48.053050 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3000 00:22:48.053444
3001 00:22:48.056463 [CATrainingPosCal] consider 2 rank data
3002 00:22:48.059814 u2DelayCellTimex100 = 270/100 ps
3003 00:22:48.063800 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
3004 00:22:48.066615 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
3005 00:22:48.073537 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
3006 00:22:48.076561 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
3007 00:22:48.079904 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
3008 00:22:48.083578 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
3009 00:22:48.084018
3010 00:22:48.086393 CA PerBit enable=1, Macro0, CA PI delay=32
3011 00:22:48.086838
3012 00:22:48.089742 [CBTSetCACLKResult] CA Dly = 32
3013 00:22:48.090398 CS Dly: 6 (0~38)
3014 00:22:48.090767
3015 00:22:48.093115 ----->DramcWriteLeveling(PI) begin...
3016 00:22:48.096462 ==
3017 00:22:48.099958 Dram Type= 6, Freq= 0, CH_1, rank 0
3018 00:22:48.103256 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3019 00:22:48.103663 ==
3020 00:22:48.106652 Write leveling (Byte 0): 21 => 21
3021 00:22:48.109778 Write leveling (Byte 1): 23 => 23
3022 00:22:48.113097 DramcWriteLeveling(PI) end<-----
3023 00:22:48.113492
3024 00:22:48.113800 ==
3025 00:22:48.116954 Dram Type= 6, Freq= 0, CH_1, rank 0
3026 00:22:48.119668 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3027 00:22:48.120204 ==
3028 00:22:48.123259 [Gating] SW mode calibration
3029 00:22:48.130285 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3030 00:22:48.133728 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3031 00:22:48.140265 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3032 00:22:48.143649 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3033 00:22:48.146892 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3034 00:22:48.153399 0 11 12 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
3035 00:22:48.156660 0 11 16 | B1->B0 | 3131 2424 | 0 0 | (0 0) (1 0)
3036 00:22:48.160504 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3037 00:22:48.166934 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3038 00:22:48.170399 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3039 00:22:48.173663 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3040 00:22:48.180168 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3041 00:22:48.183228 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3042 00:22:48.186671 0 12 12 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
3043 00:22:48.193498 0 12 16 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
3044 00:22:48.196703 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3045 00:22:48.200364 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3046 00:22:48.206677 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3047 00:22:48.210123 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3048 00:22:48.213428 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3049 00:22:48.217025 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3050 00:22:48.223474 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3051 00:22:48.226740 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3052 00:22:48.230274 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3053 00:22:48.236702 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3054 00:22:48.240446 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3055 00:22:48.243647 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3056 00:22:48.250453 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3057 00:22:48.253247 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3058 00:22:48.256781 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3059 00:22:48.263524 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3060 00:22:48.266615 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3061 00:22:48.269889 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3062 00:22:48.276586 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3063 00:22:48.281034 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3064 00:22:48.283245 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3065 00:22:48.289766 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3066 00:22:48.293331 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3067 00:22:48.296805 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3068 00:22:48.303448 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3069 00:22:48.303942 Total UI for P1: 0, mck2ui 16
3070 00:22:48.306848 best dqsien dly found for B0: ( 0, 15, 16)
3071 00:22:48.313267 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3072 00:22:48.316526 Total UI for P1: 0, mck2ui 16
3073 00:22:48.320045 best dqsien dly found for B1: ( 0, 15, 18)
3074 00:22:48.323399 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
3075 00:22:48.326761 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
3076 00:22:48.327201
3077 00:22:48.329829 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
3078 00:22:48.333227 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
3079 00:22:48.336787 [Gating] SW calibration Done
3080 00:22:48.337355 ==
3081 00:22:48.340042 Dram Type= 6, Freq= 0, CH_1, rank 0
3082 00:22:48.343164 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3083 00:22:48.343574 ==
3084 00:22:48.346665 RX Vref Scan: 0
3085 00:22:48.347060
3086 00:22:48.350183 RX Vref 0 -> 0, step: 1
3087 00:22:48.350606
3088 00:22:48.350916 RX Delay -40 -> 252, step: 8
3089 00:22:48.356580 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
3090 00:22:48.359917 iDelay=208, Bit 1, Center 107 (32 ~ 183) 152
3091 00:22:48.363571 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3092 00:22:48.367065 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3093 00:22:48.369894 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3094 00:22:48.377273 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3095 00:22:48.380319 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3096 00:22:48.383467 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3097 00:22:48.387238 iDelay=208, Bit 8, Center 87 (16 ~ 159) 144
3098 00:22:48.390276 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144
3099 00:22:48.393964 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3100 00:22:48.400004 iDelay=208, Bit 11, Center 103 (32 ~ 175) 144
3101 00:22:48.403445 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3102 00:22:48.406621 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3103 00:22:48.410106 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3104 00:22:48.416824 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3105 00:22:48.417342 ==
3106 00:22:48.420598 Dram Type= 6, Freq= 0, CH_1, rank 0
3107 00:22:48.423728 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3108 00:22:48.424300 ==
3109 00:22:48.424646 DQS Delay:
3110 00:22:48.426659 DQS0 = 0, DQS1 = 0
3111 00:22:48.427101 DQM Delay:
3112 00:22:48.430194 DQM0 = 116, DQM1 = 109
3113 00:22:48.430679 DQ Delay:
3114 00:22:48.433552 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3115 00:22:48.436944 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3116 00:22:48.440018 DQ8 =87, DQ9 =95, DQ10 =111, DQ11 =103
3117 00:22:48.443210 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3118 00:22:48.443649
3119 00:22:48.443984
3120 00:22:48.444293 ==
3121 00:22:48.446582 Dram Type= 6, Freq= 0, CH_1, rank 0
3122 00:22:48.453274 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3123 00:22:48.453796 ==
3124 00:22:48.454140
3125 00:22:48.454501
3126 00:22:48.454806 TX Vref Scan disable
3127 00:22:48.457152 == TX Byte 0 ==
3128 00:22:48.460866 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3129 00:22:48.464167 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3130 00:22:48.467674 == TX Byte 1 ==
3131 00:22:48.470174 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3132 00:22:48.474164 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3133 00:22:48.477468 ==
3134 00:22:48.480999 Dram Type= 6, Freq= 0, CH_1, rank 0
3135 00:22:48.483885 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3136 00:22:48.484332 ==
3137 00:22:48.494964 TX Vref=22, minBit 3, minWin=25, winSum=411
3138 00:22:48.498480 TX Vref=24, minBit 11, minWin=25, winSum=417
3139 00:22:48.501736 TX Vref=26, minBit 8, minWin=25, winSum=427
3140 00:22:48.504801 TX Vref=28, minBit 1, minWin=26, winSum=424
3141 00:22:48.508575 TX Vref=30, minBit 8, minWin=26, winSum=430
3142 00:22:48.515009 TX Vref=32, minBit 9, minWin=25, winSum=426
3143 00:22:48.518684 [TxChooseVref] Worse bit 8, Min win 26, Win sum 430, Final Vref 30
3144 00:22:48.519122
3145 00:22:48.521634 Final TX Range 1 Vref 30
3146 00:22:48.522070
3147 00:22:48.522450 ==
3148 00:22:48.524621 Dram Type= 6, Freq= 0, CH_1, rank 0
3149 00:22:48.528005 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3150 00:22:48.528448 ==
3151 00:22:48.531271
3152 00:22:48.531704
3153 00:22:48.532045 TX Vref Scan disable
3154 00:22:48.534866 == TX Byte 0 ==
3155 00:22:48.538118 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3156 00:22:48.541917 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3157 00:22:48.545194 == TX Byte 1 ==
3158 00:22:48.547719 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3159 00:22:48.551757 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3160 00:22:48.552194
3161 00:22:48.554669 [DATLAT]
3162 00:22:48.555103 Freq=1200, CH1 RK0
3163 00:22:48.555441
3164 00:22:48.558060 DATLAT Default: 0xd
3165 00:22:48.558533 0, 0xFFFF, sum = 0
3166 00:22:48.561334 1, 0xFFFF, sum = 0
3167 00:22:48.561779 2, 0xFFFF, sum = 0
3168 00:22:48.565219 3, 0xFFFF, sum = 0
3169 00:22:48.565754 4, 0xFFFF, sum = 0
3170 00:22:48.568277 5, 0xFFFF, sum = 0
3171 00:22:48.568717 6, 0xFFFF, sum = 0
3172 00:22:48.572097 7, 0xFFFF, sum = 0
3173 00:22:48.572640 8, 0xFFFF, sum = 0
3174 00:22:48.574694 9, 0xFFFF, sum = 0
3175 00:22:48.578061 10, 0xFFFF, sum = 0
3176 00:22:48.578542 11, 0x0, sum = 1
3177 00:22:48.578887 12, 0x0, sum = 2
3178 00:22:48.582184 13, 0x0, sum = 3
3179 00:22:48.582753 14, 0x0, sum = 4
3180 00:22:48.585107 best_step = 12
3181 00:22:48.585626
3182 00:22:48.585963 ==
3183 00:22:48.588430 Dram Type= 6, Freq= 0, CH_1, rank 0
3184 00:22:48.591474 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3185 00:22:48.591913 ==
3186 00:22:48.594879 RX Vref Scan: 1
3187 00:22:48.595317
3188 00:22:48.595651 Set Vref Range= 32 -> 127
3189 00:22:48.595967
3190 00:22:48.598404 RX Vref 32 -> 127, step: 1
3191 00:22:48.598841
3192 00:22:48.601444 RX Delay -29 -> 252, step: 4
3193 00:22:48.601895
3194 00:22:48.604682 Set Vref, RX VrefLevel [Byte0]: 32
3195 00:22:48.608297 [Byte1]: 32
3196 00:22:48.611150
3197 00:22:48.611585 Set Vref, RX VrefLevel [Byte0]: 33
3198 00:22:48.614951 [Byte1]: 33
3199 00:22:48.619184
3200 00:22:48.619617 Set Vref, RX VrefLevel [Byte0]: 34
3201 00:22:48.622362 [Byte1]: 34
3202 00:22:48.627051
3203 00:22:48.627487 Set Vref, RX VrefLevel [Byte0]: 35
3204 00:22:48.630405 [Byte1]: 35
3205 00:22:48.635541
3206 00:22:48.636053 Set Vref, RX VrefLevel [Byte0]: 36
3207 00:22:48.638758 [Byte1]: 36
3208 00:22:48.643119
3209 00:22:48.643590 Set Vref, RX VrefLevel [Byte0]: 37
3210 00:22:48.646543 [Byte1]: 37
3211 00:22:48.651423
3212 00:22:48.651938 Set Vref, RX VrefLevel [Byte0]: 38
3213 00:22:48.655011 [Byte1]: 38
3214 00:22:48.658855
3215 00:22:48.659295 Set Vref, RX VrefLevel [Byte0]: 39
3216 00:22:48.662032 [Byte1]: 39
3217 00:22:48.667266
3218 00:22:48.667697 Set Vref, RX VrefLevel [Byte0]: 40
3219 00:22:48.670313 [Byte1]: 40
3220 00:22:48.675019
3221 00:22:48.675456 Set Vref, RX VrefLevel [Byte0]: 41
3222 00:22:48.678202 [Byte1]: 41
3223 00:22:48.683417
3224 00:22:48.683938 Set Vref, RX VrefLevel [Byte0]: 42
3225 00:22:48.685920 [Byte1]: 42
3226 00:22:48.690830
3227 00:22:48.691353 Set Vref, RX VrefLevel [Byte0]: 43
3228 00:22:48.693963 [Byte1]: 43
3229 00:22:48.699172
3230 00:22:48.699697 Set Vref, RX VrefLevel [Byte0]: 44
3231 00:22:48.702367 [Byte1]: 44
3232 00:22:48.707137
3233 00:22:48.707660 Set Vref, RX VrefLevel [Byte0]: 45
3234 00:22:48.710305 [Byte1]: 45
3235 00:22:48.715055
3236 00:22:48.715579 Set Vref, RX VrefLevel [Byte0]: 46
3237 00:22:48.718421 [Byte1]: 46
3238 00:22:48.723221
3239 00:22:48.723744 Set Vref, RX VrefLevel [Byte0]: 47
3240 00:22:48.726028 [Byte1]: 47
3241 00:22:48.731018
3242 00:22:48.731536 Set Vref, RX VrefLevel [Byte0]: 48
3243 00:22:48.734297 [Byte1]: 48
3244 00:22:48.738769
3245 00:22:48.739386 Set Vref, RX VrefLevel [Byte0]: 49
3246 00:22:48.742182 [Byte1]: 49
3247 00:22:48.746589
3248 00:22:48.747028 Set Vref, RX VrefLevel [Byte0]: 50
3249 00:22:48.749664 [Byte1]: 50
3250 00:22:48.754590
3251 00:22:48.755115 Set Vref, RX VrefLevel [Byte0]: 51
3252 00:22:48.757820 [Byte1]: 51
3253 00:22:48.762566
3254 00:22:48.763080 Set Vref, RX VrefLevel [Byte0]: 52
3255 00:22:48.765973 [Byte1]: 52
3256 00:22:48.770548
3257 00:22:48.771068 Set Vref, RX VrefLevel [Byte0]: 53
3258 00:22:48.773832 [Byte1]: 53
3259 00:22:48.778631
3260 00:22:48.779230 Set Vref, RX VrefLevel [Byte0]: 54
3261 00:22:48.781668 [Byte1]: 54
3262 00:22:48.786778
3263 00:22:48.787290 Set Vref, RX VrefLevel [Byte0]: 55
3264 00:22:48.789967 [Byte1]: 55
3265 00:22:48.794606
3266 00:22:48.795047 Set Vref, RX VrefLevel [Byte0]: 56
3267 00:22:48.797753 [Byte1]: 56
3268 00:22:48.802942
3269 00:22:48.803471 Set Vref, RX VrefLevel [Byte0]: 57
3270 00:22:48.805355 [Byte1]: 57
3271 00:22:48.810417
3272 00:22:48.810934 Set Vref, RX VrefLevel [Byte0]: 58
3273 00:22:48.813895 [Byte1]: 58
3274 00:22:48.818357
3275 00:22:48.818872 Set Vref, RX VrefLevel [Byte0]: 59
3276 00:22:48.821666 [Byte1]: 59
3277 00:22:48.826367
3278 00:22:48.826880 Set Vref, RX VrefLevel [Byte0]: 60
3279 00:22:48.829732 [Byte1]: 60
3280 00:22:48.834388
3281 00:22:48.834909 Set Vref, RX VrefLevel [Byte0]: 61
3282 00:22:48.837448 [Byte1]: 61
3283 00:22:48.841922
3284 00:22:48.842395 Set Vref, RX VrefLevel [Byte0]: 62
3285 00:22:48.845358 [Byte1]: 62
3286 00:22:48.850117
3287 00:22:48.850685 Set Vref, RX VrefLevel [Byte0]: 63
3288 00:22:48.853463 [Byte1]: 63
3289 00:22:48.858266
3290 00:22:48.858802 Set Vref, RX VrefLevel [Byte0]: 64
3291 00:22:48.861541 [Byte1]: 64
3292 00:22:48.866200
3293 00:22:48.866771 Set Vref, RX VrefLevel [Byte0]: 65
3294 00:22:48.869427 [Byte1]: 65
3295 00:22:48.873924
3296 00:22:48.874493 Final RX Vref Byte 0 = 58 to rank0
3297 00:22:48.876986 Final RX Vref Byte 1 = 50 to rank0
3298 00:22:48.880659 Final RX Vref Byte 0 = 58 to rank1
3299 00:22:48.883811 Final RX Vref Byte 1 = 50 to rank1==
3300 00:22:48.887214 Dram Type= 6, Freq= 0, CH_1, rank 0
3301 00:22:48.893910 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3302 00:22:48.894381 ==
3303 00:22:48.894723 DQS Delay:
3304 00:22:48.895035 DQS0 = 0, DQS1 = 0
3305 00:22:48.897108 DQM Delay:
3306 00:22:48.897557 DQM0 = 115, DQM1 = 105
3307 00:22:48.900182 DQ Delay:
3308 00:22:48.903860 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114
3309 00:22:48.907425 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =114
3310 00:22:48.910414 DQ8 =86, DQ9 =94, DQ10 =108, DQ11 =98
3311 00:22:48.914101 DQ12 =114, DQ13 =116, DQ14 =114, DQ15 =114
3312 00:22:48.914681
3313 00:22:48.915030
3314 00:22:48.924077 [DQSOSCAuto] RK0, (LSB)MR18= 0x1717, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 401 ps
3315 00:22:48.924603 CH1 RK0: MR19=404, MR18=1717
3316 00:22:48.930154 CH1_RK0: MR19=0x404, MR18=0x1717, DQSOSC=401, MR23=63, INC=40, DEC=27
3317 00:22:48.930621
3318 00:22:48.933457 ----->DramcWriteLeveling(PI) begin...
3319 00:22:48.933900 ==
3320 00:22:48.936661 Dram Type= 6, Freq= 0, CH_1, rank 1
3321 00:22:48.943489 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3322 00:22:48.944015 ==
3323 00:22:48.946780 Write leveling (Byte 0): 19 => 19
3324 00:22:48.947291 Write leveling (Byte 1): 20 => 20
3325 00:22:48.949964 DramcWriteLeveling(PI) end<-----
3326 00:22:48.950518
3327 00:22:48.953265 ==
3328 00:22:48.953696 Dram Type= 6, Freq= 0, CH_1, rank 1
3329 00:22:48.959669 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3330 00:22:48.960171 ==
3331 00:22:48.963615 [Gating] SW mode calibration
3332 00:22:48.969790 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3333 00:22:48.973283 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3334 00:22:48.980147 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3335 00:22:48.982865 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3336 00:22:48.986322 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3337 00:22:48.992966 0 11 12 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
3338 00:22:48.996374 0 11 16 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
3339 00:22:48.999660 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3340 00:22:49.006285 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3341 00:22:49.009506 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3342 00:22:49.012805 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3343 00:22:49.019675 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3344 00:22:49.022852 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3345 00:22:49.026148 0 12 12 | B1->B0 | 2323 3d3d | 0 1 | (0 0) (0 0)
3346 00:22:49.032511 0 12 16 | B1->B0 | 3c3c 4646 | 0 0 | (1 1) (0 0)
3347 00:22:49.035785 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3348 00:22:49.039489 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3349 00:22:49.046372 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3350 00:22:49.049418 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3351 00:22:49.053020 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3352 00:22:49.059059 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3353 00:22:49.062356 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3354 00:22:49.066181 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3355 00:22:49.072655 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3356 00:22:49.075764 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3357 00:22:49.078951 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3358 00:22:49.085826 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3359 00:22:49.089152 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3360 00:22:49.092271 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3361 00:22:49.098669 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3362 00:22:49.102003 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3363 00:22:49.105700 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3364 00:22:49.112161 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3365 00:22:49.115351 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3366 00:22:49.119015 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3367 00:22:49.122248 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3368 00:22:49.128901 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3369 00:22:49.132175 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3370 00:22:49.138436 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3371 00:22:49.141541 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3372 00:22:49.145146 Total UI for P1: 0, mck2ui 16
3373 00:22:49.148818 best dqsien dly found for B0: ( 0, 15, 12)
3374 00:22:49.151863 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3375 00:22:49.155003 Total UI for P1: 0, mck2ui 16
3376 00:22:49.158404 best dqsien dly found for B1: ( 0, 15, 18)
3377 00:22:49.161644 best DQS0 dly(MCK, UI, PI) = (0, 15, 12)
3378 00:22:49.165131 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
3379 00:22:49.165639
3380 00:22:49.168328 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 12)
3381 00:22:49.175358 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
3382 00:22:49.175868 [Gating] SW calibration Done
3383 00:22:49.176205 ==
3384 00:22:49.178441 Dram Type= 6, Freq= 0, CH_1, rank 1
3385 00:22:49.185119 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3386 00:22:49.185629 ==
3387 00:22:49.185965 RX Vref Scan: 0
3388 00:22:49.186310
3389 00:22:49.188387 RX Vref 0 -> 0, step: 1
3390 00:22:49.188818
3391 00:22:49.191585 RX Delay -40 -> 252, step: 8
3392 00:22:49.194746 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3393 00:22:49.198293 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3394 00:22:49.201280 iDelay=200, Bit 2, Center 107 (32 ~ 183) 152
3395 00:22:49.207854 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3396 00:22:49.210999 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3397 00:22:49.214816 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3398 00:22:49.218020 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3399 00:22:49.221678 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3400 00:22:49.228667 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
3401 00:22:49.231069 iDelay=200, Bit 9, Center 87 (16 ~ 159) 144
3402 00:22:49.234565 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3403 00:22:49.237535 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
3404 00:22:49.241029 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3405 00:22:49.247685 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3406 00:22:49.251140 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3407 00:22:49.254443 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3408 00:22:49.254878 ==
3409 00:22:49.257701 Dram Type= 6, Freq= 0, CH_1, rank 1
3410 00:22:49.261130 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3411 00:22:49.261578 ==
3412 00:22:49.264903 DQS Delay:
3413 00:22:49.265436 DQS0 = 0, DQS1 = 0
3414 00:22:49.267963 DQM Delay:
3415 00:22:49.268390 DQM0 = 115, DQM1 = 104
3416 00:22:49.268722 DQ Delay:
3417 00:22:49.274459 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3418 00:22:49.277901 DQ4 =115, DQ5 =123, DQ6 =123, DQ7 =115
3419 00:22:49.281239 DQ8 =91, DQ9 =87, DQ10 =103, DQ11 =99
3420 00:22:49.284681 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =111
3421 00:22:49.285196
3422 00:22:49.285529
3423 00:22:49.285832 ==
3424 00:22:49.287861 Dram Type= 6, Freq= 0, CH_1, rank 1
3425 00:22:49.291307 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3426 00:22:49.291835 ==
3427 00:22:49.292172
3428 00:22:49.292478
3429 00:22:49.294949 TX Vref Scan disable
3430 00:22:49.298058 == TX Byte 0 ==
3431 00:22:49.300684 Update DQ dly =836 (3 ,1, 36) DQ OEN =(2 ,6)
3432 00:22:49.304137 Update DQM dly =836 (3 ,1, 36) DQM OEN =(2 ,6)
3433 00:22:49.307255 == TX Byte 1 ==
3434 00:22:49.310490 Update DQ dly =836 (3 ,1, 36) DQ OEN =(2 ,6)
3435 00:22:49.314465 Update DQM dly =836 (3 ,1, 36) DQM OEN =(2 ,6)
3436 00:22:49.314979 ==
3437 00:22:49.317270 Dram Type= 6, Freq= 0, CH_1, rank 1
3438 00:22:49.320458 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3439 00:22:49.323588 ==
3440 00:22:49.333709 TX Vref=22, minBit 9, minWin=25, winSum=422
3441 00:22:49.336835 TX Vref=24, minBit 0, minWin=26, winSum=427
3442 00:22:49.340590 TX Vref=26, minBit 9, minWin=26, winSum=435
3443 00:22:49.343819 TX Vref=28, minBit 3, minWin=26, winSum=434
3444 00:22:49.346890 TX Vref=30, minBit 9, minWin=26, winSum=438
3445 00:22:49.353788 TX Vref=32, minBit 9, minWin=26, winSum=436
3446 00:22:49.357183 [TxChooseVref] Worse bit 9, Min win 26, Win sum 438, Final Vref 30
3447 00:22:49.357717
3448 00:22:49.360042 Final TX Range 1 Vref 30
3449 00:22:49.360477
3450 00:22:49.360856 ==
3451 00:22:49.363503 Dram Type= 6, Freq= 0, CH_1, rank 1
3452 00:22:49.366998 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3453 00:22:49.369997 ==
3454 00:22:49.370488
3455 00:22:49.370825
3456 00:22:49.371134 TX Vref Scan disable
3457 00:22:49.373470 == TX Byte 0 ==
3458 00:22:49.377034 Update DQ dly =836 (3 ,1, 36) DQ OEN =(2 ,6)
3459 00:22:49.383732 Update DQM dly =836 (3 ,1, 36) DQM OEN =(2 ,6)
3460 00:22:49.384259 == TX Byte 1 ==
3461 00:22:49.386718 Update DQ dly =836 (3 ,1, 36) DQ OEN =(2 ,6)
3462 00:22:49.393649 Update DQM dly =836 (3 ,1, 36) DQM OEN =(2 ,6)
3463 00:22:49.394173
3464 00:22:49.394575 [DATLAT]
3465 00:22:49.394892 Freq=1200, CH1 RK1
3466 00:22:49.395194
3467 00:22:49.396832 DATLAT Default: 0xc
3468 00:22:49.397259 0, 0xFFFF, sum = 0
3469 00:22:49.399965 1, 0xFFFF, sum = 0
3470 00:22:49.403152 2, 0xFFFF, sum = 0
3471 00:22:49.403619 3, 0xFFFF, sum = 0
3472 00:22:49.406550 4, 0xFFFF, sum = 0
3473 00:22:49.406993 5, 0xFFFF, sum = 0
3474 00:22:49.409689 6, 0xFFFF, sum = 0
3475 00:22:49.410127 7, 0xFFFF, sum = 0
3476 00:22:49.413214 8, 0xFFFF, sum = 0
3477 00:22:49.413653 9, 0xFFFF, sum = 0
3478 00:22:49.416577 10, 0xFFFF, sum = 0
3479 00:22:49.417022 11, 0x0, sum = 1
3480 00:22:49.419479 12, 0x0, sum = 2
3481 00:22:49.419922 13, 0x0, sum = 3
3482 00:22:49.422829 14, 0x0, sum = 4
3483 00:22:49.423270 best_step = 12
3484 00:22:49.423605
3485 00:22:49.423918 ==
3486 00:22:49.426375 Dram Type= 6, Freq= 0, CH_1, rank 1
3487 00:22:49.429669 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3488 00:22:49.432962 ==
3489 00:22:49.433355 RX Vref Scan: 0
3490 00:22:49.433656
3491 00:22:49.436028 RX Vref 0 -> 0, step: 1
3492 00:22:49.436419
3493 00:22:49.439323 RX Delay -29 -> 252, step: 4
3494 00:22:49.442620 iDelay=199, Bit 0, Center 114 (43 ~ 186) 144
3495 00:22:49.446298 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3496 00:22:49.450041 iDelay=199, Bit 2, Center 108 (39 ~ 178) 140
3497 00:22:49.456431 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140
3498 00:22:49.459717 iDelay=199, Bit 4, Center 114 (43 ~ 186) 144
3499 00:22:49.462587 iDelay=199, Bit 5, Center 124 (51 ~ 198) 148
3500 00:22:49.465831 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
3501 00:22:49.469354 iDelay=199, Bit 7, Center 114 (43 ~ 186) 144
3502 00:22:49.475954 iDelay=199, Bit 8, Center 86 (19 ~ 154) 136
3503 00:22:49.479098 iDelay=199, Bit 9, Center 92 (27 ~ 158) 132
3504 00:22:49.482679 iDelay=199, Bit 10, Center 106 (39 ~ 174) 136
3505 00:22:49.485902 iDelay=199, Bit 11, Center 96 (31 ~ 162) 132
3506 00:22:49.489045 iDelay=199, Bit 12, Center 112 (43 ~ 182) 140
3507 00:22:49.495793 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
3508 00:22:49.499056 iDelay=199, Bit 14, Center 112 (43 ~ 182) 140
3509 00:22:49.502318 iDelay=199, Bit 15, Center 112 (47 ~ 178) 132
3510 00:22:49.502750 ==
3511 00:22:49.505831 Dram Type= 6, Freq= 0, CH_1, rank 1
3512 00:22:49.509244 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3513 00:22:49.512620 ==
3514 00:22:49.513072 DQS Delay:
3515 00:22:49.513424 DQS0 = 0, DQS1 = 0
3516 00:22:49.515840 DQM Delay:
3517 00:22:49.516355 DQM0 = 114, DQM1 = 103
3518 00:22:49.518868 DQ Delay:
3519 00:22:49.521986 DQ0 =114, DQ1 =110, DQ2 =108, DQ3 =112
3520 00:22:49.525397 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =114
3521 00:22:49.528979 DQ8 =86, DQ9 =92, DQ10 =106, DQ11 =96
3522 00:22:49.532194 DQ12 =112, DQ13 =112, DQ14 =112, DQ15 =112
3523 00:22:49.532637
3524 00:22:49.532977
3525 00:22:49.538586 [DQSOSCAuto] RK1, (LSB)MR18= 0xf0f, (MSB)MR19= 0x404, tDQSOscB0 = 404 ps tDQSOscB1 = 404 ps
3526 00:22:49.542887 CH1 RK1: MR19=404, MR18=F0F
3527 00:22:49.549423 CH1_RK1: MR19=0x404, MR18=0xF0F, DQSOSC=404, MR23=63, INC=40, DEC=26
3528 00:22:49.552076 [RxdqsGatingPostProcess] freq 1200
3529 00:22:49.558823 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3530 00:22:49.559346 Pre-setting of DQS Precalculation
3531 00:22:49.565620 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3532 00:22:49.572386 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3533 00:22:49.578579 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3534 00:22:49.579093
3535 00:22:49.579458
3536 00:22:49.582329 [Calibration Summary] 2400 Mbps
3537 00:22:49.585168 CH 0, Rank 0
3538 00:22:49.585684 SW Impedance : PASS
3539 00:22:49.588507 DUTY Scan : NO K
3540 00:22:49.591748 ZQ Calibration : PASS
3541 00:22:49.592217 Jitter Meter : NO K
3542 00:22:49.595313 CBT Training : PASS
3543 00:22:49.598614 Write leveling : PASS
3544 00:22:49.599050 RX DQS gating : PASS
3545 00:22:49.601835 RX DQ/DQS(RDDQC) : PASS
3546 00:22:49.602397 TX DQ/DQS : PASS
3547 00:22:49.605478 RX DATLAT : PASS
3548 00:22:49.608753 RX DQ/DQS(Engine): PASS
3549 00:22:49.609274 TX OE : NO K
3550 00:22:49.611559 All Pass.
3551 00:22:49.612006
3552 00:22:49.612357 CH 0, Rank 1
3553 00:22:49.614862 SW Impedance : PASS
3554 00:22:49.615298 DUTY Scan : NO K
3555 00:22:49.618061 ZQ Calibration : PASS
3556 00:22:49.621481 Jitter Meter : NO K
3557 00:22:49.621993 CBT Training : PASS
3558 00:22:49.625101 Write leveling : PASS
3559 00:22:49.628346 RX DQS gating : PASS
3560 00:22:49.628874 RX DQ/DQS(RDDQC) : PASS
3561 00:22:49.632124 TX DQ/DQS : PASS
3562 00:22:49.635061 RX DATLAT : PASS
3563 00:22:49.635500 RX DQ/DQS(Engine): PASS
3564 00:22:49.637985 TX OE : NO K
3565 00:22:49.638481 All Pass.
3566 00:22:49.638826
3567 00:22:49.641619 CH 1, Rank 0
3568 00:22:49.642136 SW Impedance : PASS
3569 00:22:49.644830 DUTY Scan : NO K
3570 00:22:49.648361 ZQ Calibration : PASS
3571 00:22:49.648874 Jitter Meter : NO K
3572 00:22:49.651426 CBT Training : PASS
3573 00:22:49.654852 Write leveling : PASS
3574 00:22:49.655373 RX DQS gating : PASS
3575 00:22:49.658329 RX DQ/DQS(RDDQC) : PASS
3576 00:22:49.658763 TX DQ/DQS : PASS
3577 00:22:49.661410 RX DATLAT : PASS
3578 00:22:49.665395 RX DQ/DQS(Engine): PASS
3579 00:22:49.665911 TX OE : NO K
3580 00:22:49.668384 All Pass.
3581 00:22:49.668893
3582 00:22:49.669234 CH 1, Rank 1
3583 00:22:49.671801 SW Impedance : PASS
3584 00:22:49.672320 DUTY Scan : NO K
3585 00:22:49.674817 ZQ Calibration : PASS
3586 00:22:49.678200 Jitter Meter : NO K
3587 00:22:49.678671 CBT Training : PASS
3588 00:22:49.681059 Write leveling : PASS
3589 00:22:49.684678 RX DQS gating : PASS
3590 00:22:49.685192 RX DQ/DQS(RDDQC) : PASS
3591 00:22:49.687723 TX DQ/DQS : PASS
3592 00:22:49.691089 RX DATLAT : PASS
3593 00:22:49.691526 RX DQ/DQS(Engine): PASS
3594 00:22:49.695073 TX OE : NO K
3595 00:22:49.695588 All Pass.
3596 00:22:49.695932
3597 00:22:49.698324 DramC Write-DBI off
3598 00:22:49.701073 PER_BANK_REFRESH: Hybrid Mode
3599 00:22:49.701592 TX_TRACKING: ON
3600 00:22:49.711063 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3601 00:22:49.715631 [FAST_K] Save calibration result to emmc
3602 00:22:49.717795 dramc_set_vcore_voltage set vcore to 650000
3603 00:22:49.721115 Read voltage for 600, 5
3604 00:22:49.721550 Vio18 = 0
3605 00:22:49.721886 Vcore = 650000
3606 00:22:49.724626 Vdram = 0
3607 00:22:49.725066 Vddq = 0
3608 00:22:49.725409 Vmddr = 0
3609 00:22:49.731077 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3610 00:22:49.734637 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3611 00:22:49.737402 MEM_TYPE=3, freq_sel=19
3612 00:22:49.741026 sv_algorithm_assistance_LP4_1600
3613 00:22:49.744369 ============ PULL DRAM RESETB DOWN ============
3614 00:22:49.747963 ========== PULL DRAM RESETB DOWN end =========
3615 00:22:49.754652 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3616 00:22:49.757897 ===================================
3617 00:22:49.760850 LPDDR4 DRAM CONFIGURATION
3618 00:22:49.764230 ===================================
3619 00:22:49.764669 EX_ROW_EN[0] = 0x0
3620 00:22:49.767489 EX_ROW_EN[1] = 0x0
3621 00:22:49.768012 LP4Y_EN = 0x0
3622 00:22:49.771182 WORK_FSP = 0x0
3623 00:22:49.771695 WL = 0x2
3624 00:22:49.774175 RL = 0x2
3625 00:22:49.774725 BL = 0x2
3626 00:22:49.777445 RPST = 0x0
3627 00:22:49.777966 RD_PRE = 0x0
3628 00:22:49.780911 WR_PRE = 0x1
3629 00:22:49.781447 WR_PST = 0x0
3630 00:22:49.784192 DBI_WR = 0x0
3631 00:22:49.784729 DBI_RD = 0x0
3632 00:22:49.787864 OTF = 0x1
3633 00:22:49.790799 ===================================
3634 00:22:49.794206 ===================================
3635 00:22:49.794789 ANA top config
3636 00:22:49.797503 ===================================
3637 00:22:49.801307 DLL_ASYNC_EN = 0
3638 00:22:49.804200 ALL_SLAVE_EN = 1
3639 00:22:49.807529 NEW_RANK_MODE = 1
3640 00:22:49.807983 DLL_IDLE_MODE = 1
3641 00:22:49.810300 LP45_APHY_COMB_EN = 1
3642 00:22:49.813995 TX_ODT_DIS = 1
3643 00:22:49.817802 NEW_8X_MODE = 1
3644 00:22:49.820955 ===================================
3645 00:22:49.824114 ===================================
3646 00:22:49.827364 data_rate = 1200
3647 00:22:49.827801 CKR = 1
3648 00:22:49.830373 DQ_P2S_RATIO = 8
3649 00:22:49.834119 ===================================
3650 00:22:49.837674 CA_P2S_RATIO = 8
3651 00:22:49.840730 DQ_CA_OPEN = 0
3652 00:22:49.843766 DQ_SEMI_OPEN = 0
3653 00:22:49.847312 CA_SEMI_OPEN = 0
3654 00:22:49.847832 CA_FULL_RATE = 0
3655 00:22:49.850823 DQ_CKDIV4_EN = 1
3656 00:22:49.854037 CA_CKDIV4_EN = 1
3657 00:22:49.857201 CA_PREDIV_EN = 0
3658 00:22:49.860562 PH8_DLY = 0
3659 00:22:49.863581 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3660 00:22:49.864021 DQ_AAMCK_DIV = 4
3661 00:22:49.867441 CA_AAMCK_DIV = 4
3662 00:22:49.870296 CA_ADMCK_DIV = 4
3663 00:22:49.873705 DQ_TRACK_CA_EN = 0
3664 00:22:49.877090 CA_PICK = 600
3665 00:22:49.880792 CA_MCKIO = 600
3666 00:22:49.883147 MCKIO_SEMI = 0
3667 00:22:49.883601 PLL_FREQ = 2288
3668 00:22:49.886557 DQ_UI_PI_RATIO = 32
3669 00:22:49.890087 CA_UI_PI_RATIO = 0
3670 00:22:49.893945 ===================================
3671 00:22:49.896817 ===================================
3672 00:22:49.900030 memory_type:LPDDR4
3673 00:22:49.900464 GP_NUM : 10
3674 00:22:49.903138 SRAM_EN : 1
3675 00:22:49.906504 MD32_EN : 0
3676 00:22:49.910083 ===================================
3677 00:22:49.910655 [ANA_INIT] >>>>>>>>>>>>>>
3678 00:22:49.913939 <<<<<< [CONFIGURE PHASE]: ANA_TX
3679 00:22:49.916625 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3680 00:22:49.920245 ===================================
3681 00:22:49.923714 data_rate = 1200,PCW = 0X5800
3682 00:22:49.926446 ===================================
3683 00:22:49.930641 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3684 00:22:49.936527 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3685 00:22:49.940229 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3686 00:22:49.947065 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3687 00:22:49.950352 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3688 00:22:49.953416 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3689 00:22:49.956539 [ANA_INIT] flow start
3690 00:22:49.956972 [ANA_INIT] PLL >>>>>>>>
3691 00:22:49.959771 [ANA_INIT] PLL <<<<<<<<
3692 00:22:49.963410 [ANA_INIT] MIDPI >>>>>>>>
3693 00:22:49.963848 [ANA_INIT] MIDPI <<<<<<<<
3694 00:22:49.966611 [ANA_INIT] DLL >>>>>>>>
3695 00:22:49.969592 [ANA_INIT] flow end
3696 00:22:49.973086 ============ LP4 DIFF to SE enter ============
3697 00:22:49.976478 ============ LP4 DIFF to SE exit ============
3698 00:22:49.979751 [ANA_INIT] <<<<<<<<<<<<<
3699 00:22:49.982997 [Flow] Enable top DCM control >>>>>
3700 00:22:49.986322 [Flow] Enable top DCM control <<<<<
3701 00:22:49.989721 Enable DLL master slave shuffle
3702 00:22:49.992872 ==============================================================
3703 00:22:49.996436 Gating Mode config
3704 00:22:50.003386 ==============================================================
3705 00:22:50.003897 Config description:
3706 00:22:50.012854 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3707 00:22:50.019360 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3708 00:22:50.022772 SELPH_MODE 0: By rank 1: By Phase
3709 00:22:50.029792 ==============================================================
3710 00:22:50.033075 GAT_TRACK_EN = 1
3711 00:22:50.036135 RX_GATING_MODE = 2
3712 00:22:50.039507 RX_GATING_TRACK_MODE = 2
3713 00:22:50.043203 SELPH_MODE = 1
3714 00:22:50.045891 PICG_EARLY_EN = 1
3715 00:22:50.049337 VALID_LAT_VALUE = 1
3716 00:22:50.052796 ==============================================================
3717 00:22:50.056013 Enter into Gating configuration >>>>
3718 00:22:50.059391 Exit from Gating configuration <<<<
3719 00:22:50.062770 Enter into DVFS_PRE_config >>>>>
3720 00:22:50.072899 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3721 00:22:50.075992 Exit from DVFS_PRE_config <<<<<
3722 00:22:50.079030 Enter into PICG configuration >>>>
3723 00:22:50.082857 Exit from PICG configuration <<<<
3724 00:22:50.085817 [RX_INPUT] configuration >>>>>
3725 00:22:50.089547 [RX_INPUT] configuration <<<<<
3726 00:22:50.095826 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3727 00:22:50.098894 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3728 00:22:50.105641 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3729 00:22:50.112172 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3730 00:22:50.118671 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3731 00:22:50.125870 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3732 00:22:50.129673 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3733 00:22:50.132305 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3734 00:22:50.135478 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3735 00:22:50.142817 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3736 00:22:50.145636 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3737 00:22:50.149083 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3738 00:22:50.152179 ===================================
3739 00:22:50.155443 LPDDR4 DRAM CONFIGURATION
3740 00:22:50.159090 ===================================
3741 00:22:50.159194 EX_ROW_EN[0] = 0x0
3742 00:22:50.162034 EX_ROW_EN[1] = 0x0
3743 00:22:50.162135 LP4Y_EN = 0x0
3744 00:22:50.165551 WORK_FSP = 0x0
3745 00:22:50.169063 WL = 0x2
3746 00:22:50.169237 RL = 0x2
3747 00:22:50.172382 BL = 0x2
3748 00:22:50.172571 RPST = 0x0
3749 00:22:50.175503 RD_PRE = 0x0
3750 00:22:50.175693 WR_PRE = 0x1
3751 00:22:50.178836 WR_PST = 0x0
3752 00:22:50.179079 DBI_WR = 0x0
3753 00:22:50.182458 DBI_RD = 0x0
3754 00:22:50.182680 OTF = 0x1
3755 00:22:50.185399 ===================================
3756 00:22:50.188814 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3757 00:22:50.195215 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3758 00:22:50.198745 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3759 00:22:50.202180 ===================================
3760 00:22:50.205604 LPDDR4 DRAM CONFIGURATION
3761 00:22:50.208759 ===================================
3762 00:22:50.209210 EX_ROW_EN[0] = 0x10
3763 00:22:50.211814 EX_ROW_EN[1] = 0x0
3764 00:22:50.212265 LP4Y_EN = 0x0
3765 00:22:50.215338 WORK_FSP = 0x0
3766 00:22:50.218940 WL = 0x2
3767 00:22:50.219378 RL = 0x2
3768 00:22:50.222335 BL = 0x2
3769 00:22:50.222767 RPST = 0x0
3770 00:22:50.225758 RD_PRE = 0x0
3771 00:22:50.226333 WR_PRE = 0x1
3772 00:22:50.228538 WR_PST = 0x0
3773 00:22:50.228975 DBI_WR = 0x0
3774 00:22:50.231966 DBI_RD = 0x0
3775 00:22:50.232501 OTF = 0x1
3776 00:22:50.235616 ===================================
3777 00:22:50.241786 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3778 00:22:50.246144 nWR fixed to 30
3779 00:22:50.249203 [ModeRegInit_LP4] CH0 RK0
3780 00:22:50.249730 [ModeRegInit_LP4] CH0 RK1
3781 00:22:50.252303 [ModeRegInit_LP4] CH1 RK0
3782 00:22:50.256046 [ModeRegInit_LP4] CH1 RK1
3783 00:22:50.256571 match AC timing 16
3784 00:22:50.262783 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3785 00:22:50.265800 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3786 00:22:50.269050 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3787 00:22:50.275727 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3788 00:22:50.279229 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3789 00:22:50.279775 ==
3790 00:22:50.282641 Dram Type= 6, Freq= 0, CH_0, rank 0
3791 00:22:50.286006 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3792 00:22:50.286585 ==
3793 00:22:50.292258 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3794 00:22:50.299096 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3795 00:22:50.302175 [CA 0] Center 35 (5~66) winsize 62
3796 00:22:50.305563 [CA 1] Center 35 (5~66) winsize 62
3797 00:22:50.308624 [CA 2] Center 34 (4~65) winsize 62
3798 00:22:50.312305 [CA 3] Center 34 (4~65) winsize 62
3799 00:22:50.315364 [CA 4] Center 33 (3~64) winsize 62
3800 00:22:50.318942 [CA 5] Center 33 (3~64) winsize 62
3801 00:22:50.319480
3802 00:22:50.322058 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3803 00:22:50.322639
3804 00:22:50.325609 [CATrainingPosCal] consider 1 rank data
3805 00:22:50.329027 u2DelayCellTimex100 = 270/100 ps
3806 00:22:50.332167 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3807 00:22:50.335238 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3808 00:22:50.338781 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3809 00:22:50.342083 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3810 00:22:50.344931 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3811 00:22:50.351875 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3812 00:22:50.352326
3813 00:22:50.355088 CA PerBit enable=1, Macro0, CA PI delay=33
3814 00:22:50.355604
3815 00:22:50.358406 [CBTSetCACLKResult] CA Dly = 33
3816 00:22:50.358922 CS Dly: 4 (0~35)
3817 00:22:50.359268 ==
3818 00:22:50.361951 Dram Type= 6, Freq= 0, CH_0, rank 1
3819 00:22:50.365378 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3820 00:22:50.368450 ==
3821 00:22:50.371528 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3822 00:22:50.378301 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3823 00:22:50.381491 [CA 0] Center 36 (6~66) winsize 61
3824 00:22:50.384864 [CA 1] Center 35 (5~66) winsize 62
3825 00:22:50.388149 [CA 2] Center 34 (4~65) winsize 62
3826 00:22:50.391501 [CA 3] Center 34 (4~65) winsize 62
3827 00:22:50.394909 [CA 4] Center 33 (3~64) winsize 62
3828 00:22:50.398114 [CA 5] Center 33 (3~64) winsize 62
3829 00:22:50.398660
3830 00:22:50.401999 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3831 00:22:50.402558
3832 00:22:50.404496 [CATrainingPosCal] consider 2 rank data
3833 00:22:50.407942 u2DelayCellTimex100 = 270/100 ps
3834 00:22:50.411992 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3835 00:22:50.414853 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3836 00:22:50.417889 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3837 00:22:50.424319 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3838 00:22:50.427738 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3839 00:22:50.430966 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3840 00:22:50.431357
3841 00:22:50.434301 CA PerBit enable=1, Macro0, CA PI delay=33
3842 00:22:50.434700
3843 00:22:50.437679 [CBTSetCACLKResult] CA Dly = 33
3844 00:22:50.438071 CS Dly: 5 (0~37)
3845 00:22:50.438460
3846 00:22:50.441312 ----->DramcWriteLeveling(PI) begin...
3847 00:22:50.444463 ==
3848 00:22:50.444940 Dram Type= 6, Freq= 0, CH_0, rank 0
3849 00:22:50.451111 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3850 00:22:50.451592 ==
3851 00:22:50.454671 Write leveling (Byte 0): 30 => 30
3852 00:22:50.457768 Write leveling (Byte 1): 29 => 29
3853 00:22:50.461109 DramcWriteLeveling(PI) end<-----
3854 00:22:50.461604
3855 00:22:50.462004 ==
3856 00:22:50.464716 Dram Type= 6, Freq= 0, CH_0, rank 0
3857 00:22:50.467874 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3858 00:22:50.468404 ==
3859 00:22:50.470801 [Gating] SW mode calibration
3860 00:22:50.477251 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3861 00:22:50.480712 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3862 00:22:50.487443 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3863 00:22:50.490980 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3864 00:22:50.493961 0 5 8 | B1->B0 | 3232 3131 | 1 1 | (1 0) (1 1)
3865 00:22:50.500691 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3866 00:22:50.503891 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3867 00:22:50.508011 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3868 00:22:50.514133 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3869 00:22:50.517511 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3870 00:22:50.520449 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3871 00:22:50.527218 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3872 00:22:50.530592 0 6 8 | B1->B0 | 2a2a 3434 | 1 0 | (0 0) (0 0)
3873 00:22:50.533870 0 6 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
3874 00:22:50.540892 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3875 00:22:50.543951 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3876 00:22:50.547568 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3877 00:22:50.553971 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3878 00:22:50.557135 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3879 00:22:50.560355 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3880 00:22:50.567167 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3881 00:22:50.570466 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3882 00:22:50.573794 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3883 00:22:50.580792 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3884 00:22:50.583720 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3885 00:22:50.586845 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3886 00:22:50.594079 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3887 00:22:50.596927 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3888 00:22:50.600229 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3889 00:22:50.606828 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3890 00:22:50.610576 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3891 00:22:50.613529 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3892 00:22:50.620032 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3893 00:22:50.623458 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3894 00:22:50.626770 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3895 00:22:50.633263 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3896 00:22:50.636720 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3897 00:22:50.640291 Total UI for P1: 0, mck2ui 16
3898 00:22:50.643954 best dqsien dly found for B0: ( 0, 9, 6)
3899 00:22:50.646823 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3900 00:22:50.650102 Total UI for P1: 0, mck2ui 16
3901 00:22:50.653999 best dqsien dly found for B1: ( 0, 9, 8)
3902 00:22:50.657077 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
3903 00:22:50.659948 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
3904 00:22:50.660427
3905 00:22:50.663363 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
3906 00:22:50.666535 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
3907 00:22:50.670439 [Gating] SW calibration Done
3908 00:22:50.670975 ==
3909 00:22:50.673650 Dram Type= 6, Freq= 0, CH_0, rank 0
3910 00:22:50.679976 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3911 00:22:50.680520 ==
3912 00:22:50.680966 RX Vref Scan: 0
3913 00:22:50.681377
3914 00:22:50.682857 RX Vref 0 -> 0, step: 1
3915 00:22:50.683308
3916 00:22:50.686332 RX Delay -230 -> 252, step: 16
3917 00:22:50.689819 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
3918 00:22:50.693465 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
3919 00:22:50.696819 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
3920 00:22:50.703569 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
3921 00:22:50.706565 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
3922 00:22:50.709817 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
3923 00:22:50.713051 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3924 00:22:50.720037 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
3925 00:22:50.723060 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3926 00:22:50.726324 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3927 00:22:50.730586 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
3928 00:22:50.733039 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3929 00:22:50.739664 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3930 00:22:50.742959 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3931 00:22:50.746285 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3932 00:22:50.749563 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3933 00:22:50.753035 ==
3934 00:22:50.756173 Dram Type= 6, Freq= 0, CH_0, rank 0
3935 00:22:50.759947 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3936 00:22:50.760485 ==
3937 00:22:50.760935 DQS Delay:
3938 00:22:50.762957 DQS0 = 0, DQS1 = 0
3939 00:22:50.763406 DQM Delay:
3940 00:22:50.766565 DQM0 = 41, DQM1 = 33
3941 00:22:50.767100 DQ Delay:
3942 00:22:50.769370 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =33
3943 00:22:50.772701 DQ4 =49, DQ5 =25, DQ6 =49, DQ7 =49
3944 00:22:50.775842 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
3945 00:22:50.779458 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3946 00:22:50.779993
3947 00:22:50.780439
3948 00:22:50.780852 ==
3949 00:22:50.782529 Dram Type= 6, Freq= 0, CH_0, rank 0
3950 00:22:50.786340 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3951 00:22:50.786883 ==
3952 00:22:50.787329
3953 00:22:50.787739
3954 00:22:50.789215 TX Vref Scan disable
3955 00:22:50.793286 == TX Byte 0 ==
3956 00:22:50.795958 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
3957 00:22:50.798994 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
3958 00:22:50.802417 == TX Byte 1 ==
3959 00:22:50.805788 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
3960 00:22:50.809520 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
3961 00:22:50.810066 ==
3962 00:22:50.812600 Dram Type= 6, Freq= 0, CH_0, rank 0
3963 00:22:50.818996 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3964 00:22:50.819518 ==
3965 00:22:50.819963
3966 00:22:50.820376
3967 00:22:50.820776 TX Vref Scan disable
3968 00:22:50.823225 == TX Byte 0 ==
3969 00:22:50.826705 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
3970 00:22:50.833224 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
3971 00:22:50.833748 == TX Byte 1 ==
3972 00:22:50.836722 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
3973 00:22:50.843263 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
3974 00:22:50.843800
3975 00:22:50.844247 [DATLAT]
3976 00:22:50.844666 Freq=600, CH0 RK0
3977 00:22:50.845071
3978 00:22:50.846313 DATLAT Default: 0x9
3979 00:22:50.846765 0, 0xFFFF, sum = 0
3980 00:22:50.849890 1, 0xFFFF, sum = 0
3981 00:22:50.850384 2, 0xFFFF, sum = 0
3982 00:22:50.852977 3, 0xFFFF, sum = 0
3983 00:22:50.856260 4, 0xFFFF, sum = 0
3984 00:22:50.856711 5, 0xFFFF, sum = 0
3985 00:22:50.860307 6, 0xFFFF, sum = 0
3986 00:22:50.860847 7, 0x0, sum = 1
3987 00:22:50.861299 8, 0x0, sum = 2
3988 00:22:50.862938 9, 0x0, sum = 3
3989 00:22:50.863390 10, 0x0, sum = 4
3990 00:22:50.866282 best_step = 8
3991 00:22:50.866757
3992 00:22:50.867199 ==
3993 00:22:50.869780 Dram Type= 6, Freq= 0, CH_0, rank 0
3994 00:22:50.873123 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3995 00:22:50.873667 ==
3996 00:22:50.876424 RX Vref Scan: 1
3997 00:22:50.876954
3998 00:22:50.877402 RX Vref 0 -> 0, step: 1
3999 00:22:50.877816
4000 00:22:50.879895 RX Delay -195 -> 252, step: 8
4001 00:22:50.880425
4002 00:22:50.882980 Set Vref, RX VrefLevel [Byte0]: 47
4003 00:22:50.886623 [Byte1]: 45
4004 00:22:50.890888
4005 00:22:50.891423 Final RX Vref Byte 0 = 47 to rank0
4006 00:22:50.893995 Final RX Vref Byte 1 = 45 to rank0
4007 00:22:50.896869 Final RX Vref Byte 0 = 47 to rank1
4008 00:22:50.900300 Final RX Vref Byte 1 = 45 to rank1==
4009 00:22:50.903205 Dram Type= 6, Freq= 0, CH_0, rank 0
4010 00:22:50.910441 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4011 00:22:50.910983 ==
4012 00:22:50.911431 DQS Delay:
4013 00:22:50.913555 DQS0 = 0, DQS1 = 0
4014 00:22:50.914001 DQM Delay:
4015 00:22:50.914504 DQM0 = 40, DQM1 = 31
4016 00:22:50.917056 DQ Delay:
4017 00:22:50.920283 DQ0 =36, DQ1 =40, DQ2 =36, DQ3 =36
4018 00:22:50.923257 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4019 00:22:50.926982 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =24
4020 00:22:50.930029 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =44
4021 00:22:50.930647
4022 00:22:50.931085
4023 00:22:50.936685 [DQSOSCAuto] RK0, (LSB)MR18= 0x5b5b, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
4024 00:22:50.940168 CH0 RK0: MR19=808, MR18=5B5B
4025 00:22:50.946881 CH0_RK0: MR19=0x808, MR18=0x5B5B, DQSOSC=392, MR23=63, INC=170, DEC=113
4026 00:22:50.947417
4027 00:22:50.949819 ----->DramcWriteLeveling(PI) begin...
4028 00:22:50.950403 ==
4029 00:22:50.953437 Dram Type= 6, Freq= 0, CH_0, rank 1
4030 00:22:50.956379 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4031 00:22:50.956830 ==
4032 00:22:50.959571 Write leveling (Byte 0): 30 => 30
4033 00:22:50.963285 Write leveling (Byte 1): 30 => 30
4034 00:22:50.966161 DramcWriteLeveling(PI) end<-----
4035 00:22:50.966654
4036 00:22:50.966998 ==
4037 00:22:50.969478 Dram Type= 6, Freq= 0, CH_0, rank 1
4038 00:22:50.973025 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4039 00:22:50.973461 ==
4040 00:22:50.976506 [Gating] SW mode calibration
4041 00:22:50.983068 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4042 00:22:50.989850 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4043 00:22:50.992798 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4044 00:22:50.999516 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4045 00:22:51.002891 0 5 8 | B1->B0 | 3232 3131 | 0 0 | (1 1) (0 0)
4046 00:22:51.006056 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4047 00:22:51.013329 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4048 00:22:51.015951 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4049 00:22:51.019094 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4050 00:22:51.025968 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4051 00:22:51.029541 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4052 00:22:51.033037 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4053 00:22:51.039217 0 6 8 | B1->B0 | 2727 3232 | 0 0 | (0 0) (1 1)
4054 00:22:51.042743 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4055 00:22:51.046314 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4056 00:22:51.053107 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4057 00:22:51.055976 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4058 00:22:51.059254 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4059 00:22:51.062542 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4060 00:22:51.069743 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4061 00:22:51.072464 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4062 00:22:51.075972 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 00:22:51.082337 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 00:22:51.085996 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 00:22:51.088835 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 00:22:51.095543 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 00:22:51.099181 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 00:22:51.102429 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 00:22:51.108847 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 00:22:51.112251 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 00:22:51.115433 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 00:22:51.121983 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 00:22:51.125740 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 00:22:51.128743 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 00:22:51.135369 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 00:22:51.138970 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4077 00:22:51.141899 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4078 00:22:51.149154 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4079 00:22:51.151995 Total UI for P1: 0, mck2ui 16
4080 00:22:51.155516 best dqsien dly found for B0: ( 0, 9, 8)
4081 00:22:51.156052 Total UI for P1: 0, mck2ui 16
4082 00:22:51.162366 best dqsien dly found for B1: ( 0, 9, 8)
4083 00:22:51.165278 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
4084 00:22:51.168708 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4085 00:22:51.169245
4086 00:22:51.172240 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
4087 00:22:51.175141 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4088 00:22:51.178830 [Gating] SW calibration Done
4089 00:22:51.179280 ==
4090 00:22:51.182037 Dram Type= 6, Freq= 0, CH_0, rank 1
4091 00:22:51.185055 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4092 00:22:51.185598 ==
4093 00:22:51.188200 RX Vref Scan: 0
4094 00:22:51.188644
4095 00:22:51.189085 RX Vref 0 -> 0, step: 1
4096 00:22:51.189509
4097 00:22:51.191471 RX Delay -230 -> 252, step: 16
4098 00:22:51.198927 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4099 00:22:51.201937 iDelay=218, Bit 1, Center 41 (-134 ~ 217) 352
4100 00:22:51.204705 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4101 00:22:51.208866 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4102 00:22:51.211739 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4103 00:22:51.218111 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4104 00:22:51.221675 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4105 00:22:51.225052 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4106 00:22:51.228241 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4107 00:22:51.234995 iDelay=218, Bit 9, Center 9 (-150 ~ 169) 320
4108 00:22:51.238300 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4109 00:22:51.241159 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4110 00:22:51.244805 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4111 00:22:51.247982 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4112 00:22:51.254909 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4113 00:22:51.258089 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4114 00:22:51.258654 ==
4115 00:22:51.261314 Dram Type= 6, Freq= 0, CH_0, rank 1
4116 00:22:51.264704 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4117 00:22:51.265140 ==
4118 00:22:51.267641 DQS Delay:
4119 00:22:51.268075 DQS0 = 0, DQS1 = 0
4120 00:22:51.271185 DQM Delay:
4121 00:22:51.271698 DQM0 = 40, DQM1 = 31
4122 00:22:51.272042 DQ Delay:
4123 00:22:51.274861 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4124 00:22:51.277797 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4125 00:22:51.281237 DQ8 =25, DQ9 =9, DQ10 =33, DQ11 =25
4126 00:22:51.284502 DQ12 =41, DQ13 =33, DQ14 =41, DQ15 =41
4127 00:22:51.285015
4128 00:22:51.285355
4129 00:22:51.285666 ==
4130 00:22:51.287807 Dram Type= 6, Freq= 0, CH_0, rank 1
4131 00:22:51.294586 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4132 00:22:51.295117 ==
4133 00:22:51.295547
4134 00:22:51.295871
4135 00:22:51.297816 TX Vref Scan disable
4136 00:22:51.298378 == TX Byte 0 ==
4137 00:22:51.300762 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4138 00:22:51.307441 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4139 00:22:51.307951 == TX Byte 1 ==
4140 00:22:51.311108 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4141 00:22:51.317575 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4142 00:22:51.318071 ==
4143 00:22:51.321193 Dram Type= 6, Freq= 0, CH_0, rank 1
4144 00:22:51.324363 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4145 00:22:51.324804 ==
4146 00:22:51.325144
4147 00:22:51.325455
4148 00:22:51.327180 TX Vref Scan disable
4149 00:22:51.331062 == TX Byte 0 ==
4150 00:22:51.334021 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4151 00:22:51.337180 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4152 00:22:51.340862 == TX Byte 1 ==
4153 00:22:51.343841 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4154 00:22:51.347519 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4155 00:22:51.348034
4156 00:22:51.351304 [DATLAT]
4157 00:22:51.351817 Freq=600, CH0 RK1
4158 00:22:51.352160
4159 00:22:51.354138 DATLAT Default: 0x8
4160 00:22:51.354710 0, 0xFFFF, sum = 0
4161 00:22:51.357674 1, 0xFFFF, sum = 0
4162 00:22:51.358192 2, 0xFFFF, sum = 0
4163 00:22:51.361050 3, 0xFFFF, sum = 0
4164 00:22:51.361566 4, 0xFFFF, sum = 0
4165 00:22:51.364188 5, 0xFFFF, sum = 0
4166 00:22:51.364716 6, 0xFFFF, sum = 0
4167 00:22:51.367426 7, 0x0, sum = 1
4168 00:22:51.367867 8, 0x0, sum = 2
4169 00:22:51.370417 9, 0x0, sum = 3
4170 00:22:51.370861 10, 0x0, sum = 4
4171 00:22:51.371206 best_step = 8
4172 00:22:51.373991
4173 00:22:51.374468 ==
4174 00:22:51.377515 Dram Type= 6, Freq= 0, CH_0, rank 1
4175 00:22:51.380326 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4176 00:22:51.380761 ==
4177 00:22:51.381216 RX Vref Scan: 0
4178 00:22:51.381682
4179 00:22:51.383657 RX Vref 0 -> 0, step: 1
4180 00:22:51.384090
4181 00:22:51.387193 RX Delay -195 -> 252, step: 8
4182 00:22:51.394373 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4183 00:22:51.397298 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4184 00:22:51.400890 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4185 00:22:51.403665 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4186 00:22:51.410305 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4187 00:22:51.413854 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4188 00:22:51.416940 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4189 00:22:51.420741 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4190 00:22:51.423524 iDelay=205, Bit 8, Center 20 (-131 ~ 172) 304
4191 00:22:51.430367 iDelay=205, Bit 9, Center 16 (-131 ~ 164) 296
4192 00:22:51.433763 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4193 00:22:51.436809 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4194 00:22:51.440256 iDelay=205, Bit 12, Center 40 (-107 ~ 188) 296
4195 00:22:51.447196 iDelay=205, Bit 13, Center 36 (-115 ~ 188) 304
4196 00:22:51.450647 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4197 00:22:51.453741 iDelay=205, Bit 15, Center 40 (-107 ~ 188) 296
4198 00:22:51.454306 ==
4199 00:22:51.457624 Dram Type= 6, Freq= 0, CH_0, rank 1
4200 00:22:51.460274 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4201 00:22:51.463712 ==
4202 00:22:51.464257 DQS Delay:
4203 00:22:51.464705 DQS0 = 0, DQS1 = 0
4204 00:22:51.466719 DQM Delay:
4205 00:22:51.467166 DQM0 = 40, DQM1 = 31
4206 00:22:51.470589 DQ Delay:
4207 00:22:51.471128 DQ0 =36, DQ1 =40, DQ2 =40, DQ3 =36
4208 00:22:51.473580 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4209 00:22:51.477115 DQ8 =20, DQ9 =16, DQ10 =32, DQ11 =24
4210 00:22:51.480378 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =40
4211 00:22:51.480912
4212 00:22:51.483137
4213 00:22:51.490414 [DQSOSCAuto] RK1, (LSB)MR18= 0x7474, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
4214 00:22:51.493583 CH0 RK1: MR19=808, MR18=7474
4215 00:22:51.500098 CH0_RK1: MR19=0x808, MR18=0x7474, DQSOSC=388, MR23=63, INC=174, DEC=116
4216 00:22:51.503420 [RxdqsGatingPostProcess] freq 600
4217 00:22:51.506548 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4218 00:22:51.509886 Pre-setting of DQS Precalculation
4219 00:22:51.517100 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4220 00:22:51.517637 ==
4221 00:22:51.519854 Dram Type= 6, Freq= 0, CH_1, rank 0
4222 00:22:51.523101 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4223 00:22:51.523646 ==
4224 00:22:51.530013 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4225 00:22:51.533268 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4226 00:22:51.536958 [CA 0] Center 35 (5~66) winsize 62
4227 00:22:51.540301 [CA 1] Center 34 (4~65) winsize 62
4228 00:22:51.543762 [CA 2] Center 33 (3~64) winsize 62
4229 00:22:51.547398 [CA 3] Center 33 (3~64) winsize 62
4230 00:22:51.550264 [CA 4] Center 33 (2~64) winsize 63
4231 00:22:51.553787 [CA 5] Center 33 (2~64) winsize 63
4232 00:22:51.554369
4233 00:22:51.557095 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4234 00:22:51.557542
4235 00:22:51.560539 [CATrainingPosCal] consider 1 rank data
4236 00:22:51.564095 u2DelayCellTimex100 = 270/100 ps
4237 00:22:51.567118 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4238 00:22:51.570358 CA1 delay=34 (4~65),Diff = 1 PI (9 cell)
4239 00:22:51.576826 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4240 00:22:51.580446 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4241 00:22:51.583482 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4242 00:22:51.587023 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4243 00:22:51.587558
4244 00:22:51.589925 CA PerBit enable=1, Macro0, CA PI delay=33
4245 00:22:51.590417
4246 00:22:51.593367 [CBTSetCACLKResult] CA Dly = 33
4247 00:22:51.593902 CS Dly: 4 (0~35)
4248 00:22:51.596480 ==
4249 00:22:51.600263 Dram Type= 6, Freq= 0, CH_1, rank 1
4250 00:22:51.603429 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4251 00:22:51.603969 ==
4252 00:22:51.606600 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4253 00:22:51.613011 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4254 00:22:51.617032 [CA 0] Center 35 (4~66) winsize 63
4255 00:22:51.620558 [CA 1] Center 34 (4~65) winsize 62
4256 00:22:51.623842 [CA 2] Center 33 (3~64) winsize 62
4257 00:22:51.627662 [CA 3] Center 33 (3~64) winsize 62
4258 00:22:51.630585 [CA 4] Center 32 (2~63) winsize 62
4259 00:22:51.633613 [CA 5] Center 33 (2~64) winsize 63
4260 00:22:51.634128
4261 00:22:51.637380 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4262 00:22:51.637893
4263 00:22:51.640017 [CATrainingPosCal] consider 2 rank data
4264 00:22:51.643863 u2DelayCellTimex100 = 270/100 ps
4265 00:22:51.646524 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4266 00:22:51.653225 CA1 delay=34 (4~65),Diff = 2 PI (19 cell)
4267 00:22:51.656661 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4268 00:22:51.659889 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4269 00:22:51.663509 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4270 00:22:51.666730 CA5 delay=33 (2~64),Diff = 1 PI (9 cell)
4271 00:22:51.667166
4272 00:22:51.669929 CA PerBit enable=1, Macro0, CA PI delay=32
4273 00:22:51.670403
4274 00:22:51.673314 [CBTSetCACLKResult] CA Dly = 32
4275 00:22:51.673763 CS Dly: 4 (0~36)
4276 00:22:51.676614
4277 00:22:51.680347 ----->DramcWriteLeveling(PI) begin...
4278 00:22:51.680890 ==
4279 00:22:51.683343 Dram Type= 6, Freq= 0, CH_1, rank 0
4280 00:22:51.686361 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4281 00:22:51.686817 ==
4282 00:22:51.690541 Write leveling (Byte 0): 29 => 29
4283 00:22:51.693254 Write leveling (Byte 1): 28 => 28
4284 00:22:51.696751 DramcWriteLeveling(PI) end<-----
4285 00:22:51.697213
4286 00:22:51.697772 ==
4287 00:22:51.699830 Dram Type= 6, Freq= 0, CH_1, rank 0
4288 00:22:51.702985 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4289 00:22:51.703432 ==
4290 00:22:51.706684 [Gating] SW mode calibration
4291 00:22:51.713542 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4292 00:22:51.719975 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4293 00:22:51.723240 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4294 00:22:51.726362 0 5 4 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
4295 00:22:51.733372 0 5 8 | B1->B0 | 2f2f 2828 | 0 0 | (1 1) (0 0)
4296 00:22:51.736408 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4297 00:22:51.739491 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4298 00:22:51.746353 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4299 00:22:51.749645 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4300 00:22:51.752843 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4301 00:22:51.756633 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4302 00:22:51.762932 0 6 4 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
4303 00:22:51.766188 0 6 8 | B1->B0 | 3636 4646 | 1 0 | (1 1) (0 0)
4304 00:22:51.769799 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4305 00:22:51.776309 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4306 00:22:51.779807 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4307 00:22:51.782853 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4308 00:22:51.789785 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4309 00:22:51.792763 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4310 00:22:51.795909 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4311 00:22:51.802714 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4312 00:22:51.806037 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4313 00:22:51.809361 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4314 00:22:51.815982 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4315 00:22:51.819497 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4316 00:22:51.822570 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4317 00:22:51.829377 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4318 00:22:51.833126 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4319 00:22:51.836010 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4320 00:22:51.843225 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4321 00:22:51.845937 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4322 00:22:51.849326 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4323 00:22:51.856168 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4324 00:22:51.859086 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4325 00:22:51.862559 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4326 00:22:51.869277 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4327 00:22:51.872692 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4328 00:22:51.875593 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4329 00:22:51.878585 Total UI for P1: 0, mck2ui 16
4330 00:22:51.882995 best dqsien dly found for B0: ( 0, 9, 6)
4331 00:22:51.885449 Total UI for P1: 0, mck2ui 16
4332 00:22:51.889036 best dqsien dly found for B1: ( 0, 9, 8)
4333 00:22:51.892174 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
4334 00:22:51.895584 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4335 00:22:51.896020
4336 00:22:51.898784 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
4337 00:22:51.905222 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4338 00:22:51.905725 [Gating] SW calibration Done
4339 00:22:51.906070 ==
4340 00:22:51.908390 Dram Type= 6, Freq= 0, CH_1, rank 0
4341 00:22:51.915110 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4342 00:22:51.915562 ==
4343 00:22:51.915903 RX Vref Scan: 0
4344 00:22:51.916219
4345 00:22:51.918807 RX Vref 0 -> 0, step: 1
4346 00:22:51.919244
4347 00:22:51.921998 RX Delay -230 -> 252, step: 16
4348 00:22:51.925108 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4349 00:22:51.929207 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4350 00:22:51.935256 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4351 00:22:51.938372 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4352 00:22:51.941653 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4353 00:22:51.945119 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4354 00:22:51.948167 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4355 00:22:51.955231 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4356 00:22:51.958803 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4357 00:22:51.962026 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4358 00:22:51.965227 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4359 00:22:51.971988 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4360 00:22:51.975047 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4361 00:22:51.978244 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4362 00:22:51.981407 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4363 00:22:51.988215 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4364 00:22:51.988737 ==
4365 00:22:51.991949 Dram Type= 6, Freq= 0, CH_1, rank 0
4366 00:22:51.994539 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4367 00:22:51.994984 ==
4368 00:22:51.995325 DQS Delay:
4369 00:22:51.998174 DQS0 = 0, DQS1 = 0
4370 00:22:51.998764 DQM Delay:
4371 00:22:52.001071 DQM0 = 39, DQM1 = 31
4372 00:22:52.001503 DQ Delay:
4373 00:22:52.004556 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4374 00:22:52.007466 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4375 00:22:52.011768 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4376 00:22:52.014486 DQ12 =33, DQ13 =49, DQ14 =33, DQ15 =49
4377 00:22:52.014961
4378 00:22:52.015297
4379 00:22:52.015722 ==
4380 00:22:52.017562 Dram Type= 6, Freq= 0, CH_1, rank 0
4381 00:22:52.020767 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4382 00:22:52.024120 ==
4383 00:22:52.024548
4384 00:22:52.024875
4385 00:22:52.025180 TX Vref Scan disable
4386 00:22:52.027679 == TX Byte 0 ==
4387 00:22:52.030695 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4388 00:22:52.034119 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4389 00:22:52.037302 == TX Byte 1 ==
4390 00:22:52.040867 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4391 00:22:52.043983 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4392 00:22:52.047177 ==
4393 00:22:52.051222 Dram Type= 6, Freq= 0, CH_1, rank 0
4394 00:22:52.054904 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4395 00:22:52.055292 ==
4396 00:22:52.055529
4397 00:22:52.055767
4398 00:22:52.058260 TX Vref Scan disable
4399 00:22:52.058736 == TX Byte 0 ==
4400 00:22:52.064202 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4401 00:22:52.067776 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4402 00:22:52.068167 == TX Byte 1 ==
4403 00:22:52.074010 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4404 00:22:52.077551 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4405 00:22:52.078064
4406 00:22:52.078542 [DATLAT]
4407 00:22:52.080922 Freq=600, CH1 RK0
4408 00:22:52.081353
4409 00:22:52.081685 DATLAT Default: 0x9
4410 00:22:52.084164 0, 0xFFFF, sum = 0
4411 00:22:52.084600 1, 0xFFFF, sum = 0
4412 00:22:52.087249 2, 0xFFFF, sum = 0
4413 00:22:52.087704 3, 0xFFFF, sum = 0
4414 00:22:52.091194 4, 0xFFFF, sum = 0
4415 00:22:52.094137 5, 0xFFFF, sum = 0
4416 00:22:52.094705 6, 0xFFFF, sum = 0
4417 00:22:52.095050 7, 0x0, sum = 1
4418 00:22:52.097182 8, 0x0, sum = 2
4419 00:22:52.097623 9, 0x0, sum = 3
4420 00:22:52.101202 10, 0x0, sum = 4
4421 00:22:52.101718 best_step = 8
4422 00:22:52.102054
4423 00:22:52.102418 ==
4424 00:22:52.103698 Dram Type= 6, Freq= 0, CH_1, rank 0
4425 00:22:52.110612 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4426 00:22:52.111051 ==
4427 00:22:52.111384 RX Vref Scan: 1
4428 00:22:52.111689
4429 00:22:52.114153 RX Vref 0 -> 0, step: 1
4430 00:22:52.114614
4431 00:22:52.117158 RX Delay -195 -> 252, step: 8
4432 00:22:52.117585
4433 00:22:52.120920 Set Vref, RX VrefLevel [Byte0]: 58
4434 00:22:52.124115 [Byte1]: 50
4435 00:22:52.124544
4436 00:22:52.127373 Final RX Vref Byte 0 = 58 to rank0
4437 00:22:52.130876 Final RX Vref Byte 1 = 50 to rank0
4438 00:22:52.134023 Final RX Vref Byte 0 = 58 to rank1
4439 00:22:52.137543 Final RX Vref Byte 1 = 50 to rank1==
4440 00:22:52.140679 Dram Type= 6, Freq= 0, CH_1, rank 0
4441 00:22:52.144077 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4442 00:22:52.144510 ==
4443 00:22:52.147216 DQS Delay:
4444 00:22:52.147724 DQS0 = 0, DQS1 = 0
4445 00:22:52.148062 DQM Delay:
4446 00:22:52.150585 DQM0 = 37, DQM1 = 29
4447 00:22:52.151020 DQ Delay:
4448 00:22:52.154025 DQ0 =44, DQ1 =32, DQ2 =28, DQ3 =36
4449 00:22:52.157130 DQ4 =36, DQ5 =44, DQ6 =44, DQ7 =36
4450 00:22:52.160583 DQ8 =12, DQ9 =20, DQ10 =32, DQ11 =20
4451 00:22:52.163670 DQ12 =36, DQ13 =40, DQ14 =36, DQ15 =40
4452 00:22:52.164102
4453 00:22:52.164493
4454 00:22:52.173677 [DQSOSCAuto] RK0, (LSB)MR18= 0x7676, (MSB)MR19= 0x808, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
4455 00:22:52.177118 CH1 RK0: MR19=808, MR18=7676
4456 00:22:52.180318 CH1_RK0: MR19=0x808, MR18=0x7676, DQSOSC=387, MR23=63, INC=175, DEC=116
4457 00:22:52.180841
4458 00:22:52.183578 ----->DramcWriteLeveling(PI) begin...
4459 00:22:52.187148 ==
4460 00:22:52.190339 Dram Type= 6, Freq= 0, CH_1, rank 1
4461 00:22:52.193353 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4462 00:22:52.193792 ==
4463 00:22:52.196994 Write leveling (Byte 0): 29 => 29
4464 00:22:52.200382 Write leveling (Byte 1): 26 => 26
4465 00:22:52.203728 DramcWriteLeveling(PI) end<-----
4466 00:22:52.204241
4467 00:22:52.204586 ==
4468 00:22:52.206969 Dram Type= 6, Freq= 0, CH_1, rank 1
4469 00:22:52.210279 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4470 00:22:52.210933 ==
4471 00:22:52.213402 [Gating] SW mode calibration
4472 00:22:52.220100 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4473 00:22:52.226615 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4474 00:22:52.230286 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4475 00:22:52.233561 0 5 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
4476 00:22:52.239929 0 5 8 | B1->B0 | 2f2f 2525 | 0 0 | (1 1) (0 0)
4477 00:22:52.243392 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4478 00:22:52.246883 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4479 00:22:52.253301 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4480 00:22:52.256612 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4481 00:22:52.260439 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4482 00:22:52.266465 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4483 00:22:52.269993 0 6 4 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
4484 00:22:52.273029 0 6 8 | B1->B0 | 3636 4545 | 0 0 | (0 0) (0 0)
4485 00:22:52.276524 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4486 00:22:52.282844 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4487 00:22:52.286292 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4488 00:22:52.289666 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4489 00:22:52.296790 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4490 00:22:52.300273 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4491 00:22:52.303526 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4492 00:22:52.309870 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 00:22:52.312710 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 00:22:52.316320 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 00:22:52.322837 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 00:22:52.326101 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 00:22:52.329673 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 00:22:52.336649 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 00:22:52.339738 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 00:22:52.342754 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 00:22:52.349892 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 00:22:52.353027 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 00:22:52.356108 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 00:22:52.362826 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 00:22:52.365997 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 00:22:52.369560 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 00:22:52.375995 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4508 00:22:52.379373 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4509 00:22:52.382788 Total UI for P1: 0, mck2ui 16
4510 00:22:52.386348 best dqsien dly found for B0: ( 0, 9, 4)
4511 00:22:52.388980 Total UI for P1: 0, mck2ui 16
4512 00:22:52.392576 best dqsien dly found for B1: ( 0, 9, 4)
4513 00:22:52.395733 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4514 00:22:52.398995 best DQS1 dly(MCK, UI, PI) = (0, 9, 4)
4515 00:22:52.399427
4516 00:22:52.402525 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4517 00:22:52.405638 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 4)
4518 00:22:52.408915 [Gating] SW calibration Done
4519 00:22:52.409347 ==
4520 00:22:52.412107 Dram Type= 6, Freq= 0, CH_1, rank 1
4521 00:22:52.415652 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4522 00:22:52.416084 ==
4523 00:22:52.419077 RX Vref Scan: 0
4524 00:22:52.419506
4525 00:22:52.422284 RX Vref 0 -> 0, step: 1
4526 00:22:52.422717
4527 00:22:52.425708 RX Delay -230 -> 252, step: 16
4528 00:22:52.428800 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4529 00:22:52.432401 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4530 00:22:52.435624 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4531 00:22:52.439183 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4532 00:22:52.445502 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4533 00:22:52.448986 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4534 00:22:52.452285 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4535 00:22:52.455324 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4536 00:22:52.462026 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4537 00:22:52.465597 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4538 00:22:52.468764 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4539 00:22:52.472095 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4540 00:22:52.478903 iDelay=218, Bit 12, Center 41 (-134 ~ 217) 352
4541 00:22:52.481770 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4542 00:22:52.485415 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4543 00:22:52.488457 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4544 00:22:52.488976 ==
4545 00:22:52.491696 Dram Type= 6, Freq= 0, CH_1, rank 1
4546 00:22:52.498574 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4547 00:22:52.499095 ==
4548 00:22:52.499438 DQS Delay:
4549 00:22:52.501518 DQS0 = 0, DQS1 = 0
4550 00:22:52.501951 DQM Delay:
4551 00:22:52.502317 DQM0 = 39, DQM1 = 33
4552 00:22:52.504789 DQ Delay:
4553 00:22:52.508520 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4554 00:22:52.511517 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33
4555 00:22:52.514840 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4556 00:22:52.518240 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41
4557 00:22:52.518818
4558 00:22:52.519161
4559 00:22:52.519476 ==
4560 00:22:52.521356 Dram Type= 6, Freq= 0, CH_1, rank 1
4561 00:22:52.524935 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4562 00:22:52.525376 ==
4563 00:22:52.525717
4564 00:22:52.526027
4565 00:22:52.527896 TX Vref Scan disable
4566 00:22:52.531715 == TX Byte 0 ==
4567 00:22:52.534878 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4568 00:22:52.538125 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4569 00:22:52.541820 == TX Byte 1 ==
4570 00:22:52.544720 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4571 00:22:52.548104 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4572 00:22:52.548622 ==
4573 00:22:52.551174 Dram Type= 6, Freq= 0, CH_1, rank 1
4574 00:22:52.554820 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4575 00:22:52.558335 ==
4576 00:22:52.558846
4577 00:22:52.559184
4578 00:22:52.559498 TX Vref Scan disable
4579 00:22:52.562177 == TX Byte 0 ==
4580 00:22:52.564746 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4581 00:22:52.571999 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4582 00:22:52.572517 == TX Byte 1 ==
4583 00:22:52.574865 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4584 00:22:52.581516 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4585 00:22:52.582033
4586 00:22:52.582444 [DATLAT]
4587 00:22:52.582774 Freq=600, CH1 RK1
4588 00:22:52.583082
4589 00:22:52.584753 DATLAT Default: 0x8
4590 00:22:52.585189 0, 0xFFFF, sum = 0
4591 00:22:52.588225 1, 0xFFFF, sum = 0
4592 00:22:52.591732 2, 0xFFFF, sum = 0
4593 00:22:52.592253 3, 0xFFFF, sum = 0
4594 00:22:52.594993 4, 0xFFFF, sum = 0
4595 00:22:52.595442 5, 0xFFFF, sum = 0
4596 00:22:52.598404 6, 0xFFFF, sum = 0
4597 00:22:52.598849 7, 0x0, sum = 1
4598 00:22:52.599194 8, 0x0, sum = 2
4599 00:22:52.601976 9, 0x0, sum = 3
4600 00:22:52.602534 10, 0x0, sum = 4
4601 00:22:52.604855 best_step = 8
4602 00:22:52.605414
4603 00:22:52.605758 ==
4604 00:22:52.608076 Dram Type= 6, Freq= 0, CH_1, rank 1
4605 00:22:52.611285 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4606 00:22:52.611724 ==
4607 00:22:52.614953 RX Vref Scan: 0
4608 00:22:52.615390
4609 00:22:52.615729 RX Vref 0 -> 0, step: 1
4610 00:22:52.616043
4611 00:22:52.617783 RX Delay -195 -> 252, step: 8
4612 00:22:52.625360 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4613 00:22:52.628752 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4614 00:22:52.631793 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4615 00:22:52.635078 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4616 00:22:52.642242 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4617 00:22:52.645131 iDelay=205, Bit 5, Center 44 (-115 ~ 204) 320
4618 00:22:52.649007 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4619 00:22:52.651987 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4620 00:22:52.655489 iDelay=205, Bit 8, Center 12 (-147 ~ 172) 320
4621 00:22:52.662240 iDelay=205, Bit 9, Center 16 (-147 ~ 180) 328
4622 00:22:52.665604 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4623 00:22:52.668754 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4624 00:22:52.672046 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4625 00:22:52.678552 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4626 00:22:52.681710 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4627 00:22:52.685172 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4628 00:22:52.685700 ==
4629 00:22:52.688328 Dram Type= 6, Freq= 0, CH_1, rank 1
4630 00:22:52.694889 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4631 00:22:52.695446 ==
4632 00:22:52.695793 DQS Delay:
4633 00:22:52.696107 DQS0 = 0, DQS1 = 0
4634 00:22:52.698348 DQM Delay:
4635 00:22:52.698916 DQM0 = 36, DQM1 = 28
4636 00:22:52.701960 DQ Delay:
4637 00:22:52.705124 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4638 00:22:52.705644 DQ4 =36, DQ5 =44, DQ6 =44, DQ7 =36
4639 00:22:52.707983 DQ8 =12, DQ9 =16, DQ10 =28, DQ11 =20
4640 00:22:52.714595 DQ12 =36, DQ13 =40, DQ14 =36, DQ15 =40
4641 00:22:52.715033
4642 00:22:52.715371
4643 00:22:52.721560 [DQSOSCAuto] RK1, (LSB)MR18= 0x6464, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
4644 00:22:52.725270 CH1 RK1: MR19=808, MR18=6464
4645 00:22:52.731703 CH1_RK1: MR19=0x808, MR18=0x6464, DQSOSC=391, MR23=63, INC=171, DEC=114
4646 00:22:52.734378 [RxdqsGatingPostProcess] freq 600
4647 00:22:52.737639 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4648 00:22:52.741080 Pre-setting of DQS Precalculation
4649 00:22:52.747639 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4650 00:22:52.754267 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4651 00:22:52.761574 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4652 00:22:52.762098
4653 00:22:52.762526
4654 00:22:52.764534 [Calibration Summary] 1200 Mbps
4655 00:22:52.765048 CH 0, Rank 0
4656 00:22:52.767633 SW Impedance : PASS
4657 00:22:52.771186 DUTY Scan : NO K
4658 00:22:52.771621 ZQ Calibration : PASS
4659 00:22:52.774804 Jitter Meter : NO K
4660 00:22:52.778027 CBT Training : PASS
4661 00:22:52.778579 Write leveling : PASS
4662 00:22:52.781221 RX DQS gating : PASS
4663 00:22:52.784564 RX DQ/DQS(RDDQC) : PASS
4664 00:22:52.785082 TX DQ/DQS : PASS
4665 00:22:52.788068 RX DATLAT : PASS
4666 00:22:52.791037 RX DQ/DQS(Engine): PASS
4667 00:22:52.791553 TX OE : NO K
4668 00:22:52.791940 All Pass.
4669 00:22:52.792256
4670 00:22:52.794431 CH 0, Rank 1
4671 00:22:52.797798 SW Impedance : PASS
4672 00:22:52.798376 DUTY Scan : NO K
4673 00:22:52.800945 ZQ Calibration : PASS
4674 00:22:52.801378 Jitter Meter : NO K
4675 00:22:52.804570 CBT Training : PASS
4676 00:22:52.807388 Write leveling : PASS
4677 00:22:52.807856 RX DQS gating : PASS
4678 00:22:52.810728 RX DQ/DQS(RDDQC) : PASS
4679 00:22:52.813836 TX DQ/DQS : PASS
4680 00:22:52.814305 RX DATLAT : PASS
4681 00:22:52.817694 RX DQ/DQS(Engine): PASS
4682 00:22:52.820761 TX OE : NO K
4683 00:22:52.821145 All Pass.
4684 00:22:52.821469
4685 00:22:52.821780 CH 1, Rank 0
4686 00:22:52.824243 SW Impedance : PASS
4687 00:22:52.827401 DUTY Scan : NO K
4688 00:22:52.827834 ZQ Calibration : PASS
4689 00:22:52.830933 Jitter Meter : NO K
4690 00:22:52.834505 CBT Training : PASS
4691 00:22:52.835215 Write leveling : PASS
4692 00:22:52.837650 RX DQS gating : PASS
4693 00:22:52.840876 RX DQ/DQS(RDDQC) : PASS
4694 00:22:52.841397 TX DQ/DQS : PASS
4695 00:22:52.844023 RX DATLAT : PASS
4696 00:22:52.844457 RX DQ/DQS(Engine): PASS
4697 00:22:52.847700 TX OE : NO K
4698 00:22:52.848137 All Pass.
4699 00:22:52.848477
4700 00:22:52.850573 CH 1, Rank 1
4701 00:22:52.851031 SW Impedance : PASS
4702 00:22:52.854589 DUTY Scan : NO K
4703 00:22:52.857160 ZQ Calibration : PASS
4704 00:22:52.857597 Jitter Meter : NO K
4705 00:22:52.860493 CBT Training : PASS
4706 00:22:52.863809 Write leveling : PASS
4707 00:22:52.864533 RX DQS gating : PASS
4708 00:22:52.867534 RX DQ/DQS(RDDQC) : PASS
4709 00:22:52.870600 TX DQ/DQS : PASS
4710 00:22:52.871038 RX DATLAT : PASS
4711 00:22:52.873534 RX DQ/DQS(Engine): PASS
4712 00:22:52.877172 TX OE : NO K
4713 00:22:52.877687 All Pass.
4714 00:22:52.878028
4715 00:22:52.881146 DramC Write-DBI off
4716 00:22:52.881988 PER_BANK_REFRESH: Hybrid Mode
4717 00:22:52.883910 TX_TRACKING: ON
4718 00:22:52.890619 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4719 00:22:52.893506 [FAST_K] Save calibration result to emmc
4720 00:22:52.900375 dramc_set_vcore_voltage set vcore to 662500
4721 00:22:52.900813 Read voltage for 933, 3
4722 00:22:52.904024 Vio18 = 0
4723 00:22:52.904462 Vcore = 662500
4724 00:22:52.904803 Vdram = 0
4725 00:22:52.906977 Vddq = 0
4726 00:22:52.907469 Vmddr = 0
4727 00:22:52.910424 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4728 00:22:52.916923 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4729 00:22:52.920304 MEM_TYPE=3, freq_sel=17
4730 00:22:52.923579 sv_algorithm_assistance_LP4_1600
4731 00:22:52.927065 ============ PULL DRAM RESETB DOWN ============
4732 00:22:52.930043 ========== PULL DRAM RESETB DOWN end =========
4733 00:22:52.933576 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4734 00:22:52.937121 ===================================
4735 00:22:52.940332 LPDDR4 DRAM CONFIGURATION
4736 00:22:52.943413 ===================================
4737 00:22:52.946807 EX_ROW_EN[0] = 0x0
4738 00:22:52.947298 EX_ROW_EN[1] = 0x0
4739 00:22:52.950158 LP4Y_EN = 0x0
4740 00:22:52.950646 WORK_FSP = 0x0
4741 00:22:52.953533 WL = 0x3
4742 00:22:52.954074 RL = 0x3
4743 00:22:52.956534 BL = 0x2
4744 00:22:52.956989 RPST = 0x0
4745 00:22:52.960172 RD_PRE = 0x0
4746 00:22:52.963384 WR_PRE = 0x1
4747 00:22:52.963937 WR_PST = 0x0
4748 00:22:52.966661 DBI_WR = 0x0
4749 00:22:52.967356 DBI_RD = 0x0
4750 00:22:52.969629 OTF = 0x1
4751 00:22:52.973002 ===================================
4752 00:22:52.976695 ===================================
4753 00:22:52.977129 ANA top config
4754 00:22:52.979904 ===================================
4755 00:22:52.983088 DLL_ASYNC_EN = 0
4756 00:22:52.986775 ALL_SLAVE_EN = 1
4757 00:22:52.987170 NEW_RANK_MODE = 1
4758 00:22:52.989643 DLL_IDLE_MODE = 1
4759 00:22:52.992775 LP45_APHY_COMB_EN = 1
4760 00:22:52.996737 TX_ODT_DIS = 1
4761 00:22:52.997138 NEW_8X_MODE = 1
4762 00:22:52.999716 ===================================
4763 00:22:53.002870 ===================================
4764 00:22:53.006324 data_rate = 1866
4765 00:22:53.009494 CKR = 1
4766 00:22:53.013040 DQ_P2S_RATIO = 8
4767 00:22:53.016828 ===================================
4768 00:22:53.019773 CA_P2S_RATIO = 8
4769 00:22:53.023688 DQ_CA_OPEN = 0
4770 00:22:53.024082 DQ_SEMI_OPEN = 0
4771 00:22:53.026293 CA_SEMI_OPEN = 0
4772 00:22:53.029325 CA_FULL_RATE = 0
4773 00:22:53.032900 DQ_CKDIV4_EN = 1
4774 00:22:53.036010 CA_CKDIV4_EN = 1
4775 00:22:53.039512 CA_PREDIV_EN = 0
4776 00:22:53.039949 PH8_DLY = 0
4777 00:22:53.043025 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4778 00:22:53.045997 DQ_AAMCK_DIV = 4
4779 00:22:53.049645 CA_AAMCK_DIV = 4
4780 00:22:53.053030 CA_ADMCK_DIV = 4
4781 00:22:53.056815 DQ_TRACK_CA_EN = 0
4782 00:22:53.057205 CA_PICK = 933
4783 00:22:53.059720 CA_MCKIO = 933
4784 00:22:53.063097 MCKIO_SEMI = 0
4785 00:22:53.066446 PLL_FREQ = 3732
4786 00:22:53.069638 DQ_UI_PI_RATIO = 32
4787 00:22:53.072699 CA_UI_PI_RATIO = 0
4788 00:22:53.076577 ===================================
4789 00:22:53.079719 ===================================
4790 00:22:53.080206 memory_type:LPDDR4
4791 00:22:53.083277 GP_NUM : 10
4792 00:22:53.086468 SRAM_EN : 1
4793 00:22:53.086992 MD32_EN : 0
4794 00:22:53.089686 ===================================
4795 00:22:53.092716 [ANA_INIT] >>>>>>>>>>>>>>
4796 00:22:53.095990 <<<<<< [CONFIGURE PHASE]: ANA_TX
4797 00:22:53.099330 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4798 00:22:53.102511 ===================================
4799 00:22:53.105873 data_rate = 1866,PCW = 0X8f00
4800 00:22:53.109751 ===================================
4801 00:22:53.112428 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4802 00:22:53.115946 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4803 00:22:53.122344 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4804 00:22:53.129545 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4805 00:22:53.132376 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4806 00:22:53.135338 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4807 00:22:53.135798 [ANA_INIT] flow start
4808 00:22:53.138982 [ANA_INIT] PLL >>>>>>>>
4809 00:22:53.141924 [ANA_INIT] PLL <<<<<<<<
4810 00:22:53.142412 [ANA_INIT] MIDPI >>>>>>>>
4811 00:22:53.145365 [ANA_INIT] MIDPI <<<<<<<<
4812 00:22:53.149019 [ANA_INIT] DLL >>>>>>>>
4813 00:22:53.149456 [ANA_INIT] flow end
4814 00:22:53.155489 ============ LP4 DIFF to SE enter ============
4815 00:22:53.158823 ============ LP4 DIFF to SE exit ============
4816 00:22:53.161848 [ANA_INIT] <<<<<<<<<<<<<
4817 00:22:53.165223 [Flow] Enable top DCM control >>>>>
4818 00:22:53.168667 [Flow] Enable top DCM control <<<<<
4819 00:22:53.169239 Enable DLL master slave shuffle
4820 00:22:53.175523 ==============================================================
4821 00:22:53.178459 Gating Mode config
4822 00:22:53.182037 ==============================================================
4823 00:22:53.185313 Config description:
4824 00:22:53.195237 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4825 00:22:53.202336 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4826 00:22:53.205287 SELPH_MODE 0: By rank 1: By Phase
4827 00:22:53.211719 ==============================================================
4828 00:22:53.214840 GAT_TRACK_EN = 1
4829 00:22:53.218640 RX_GATING_MODE = 2
4830 00:22:53.221971 RX_GATING_TRACK_MODE = 2
4831 00:22:53.224949 SELPH_MODE = 1
4832 00:22:53.225392 PICG_EARLY_EN = 1
4833 00:22:53.227942 VALID_LAT_VALUE = 1
4834 00:22:53.234609 ==============================================================
4835 00:22:53.237693 Enter into Gating configuration >>>>
4836 00:22:53.241783 Exit from Gating configuration <<<<
4837 00:22:53.244622 Enter into DVFS_PRE_config >>>>>
4838 00:22:53.254607 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4839 00:22:53.257979 Exit from DVFS_PRE_config <<<<<
4840 00:22:53.261148 Enter into PICG configuration >>>>
4841 00:22:53.264189 Exit from PICG configuration <<<<
4842 00:22:53.267566 [RX_INPUT] configuration >>>>>
4843 00:22:53.271199 [RX_INPUT] configuration <<<<<
4844 00:22:53.277762 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4845 00:22:53.281022 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4846 00:22:53.287570 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4847 00:22:53.294360 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4848 00:22:53.300851 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4849 00:22:53.307820 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4850 00:22:53.310890 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4851 00:22:53.313992 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4852 00:22:53.317294 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4853 00:22:53.324265 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4854 00:22:53.327619 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4855 00:22:53.330590 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4856 00:22:53.334631 ===================================
4857 00:22:53.337373 LPDDR4 DRAM CONFIGURATION
4858 00:22:53.340165 ===================================
4859 00:22:53.340604 EX_ROW_EN[0] = 0x0
4860 00:22:53.343418 EX_ROW_EN[1] = 0x0
4861 00:22:53.346793 LP4Y_EN = 0x0
4862 00:22:53.347249 WORK_FSP = 0x0
4863 00:22:53.349962 WL = 0x3
4864 00:22:53.350430 RL = 0x3
4865 00:22:53.353392 BL = 0x2
4866 00:22:53.353822 RPST = 0x0
4867 00:22:53.357082 RD_PRE = 0x0
4868 00:22:53.357516 WR_PRE = 0x1
4869 00:22:53.360181 WR_PST = 0x0
4870 00:22:53.360615 DBI_WR = 0x0
4871 00:22:53.363702 DBI_RD = 0x0
4872 00:22:53.364165 OTF = 0x1
4873 00:22:53.366529 ===================================
4874 00:22:53.370000 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4875 00:22:53.376695 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4876 00:22:53.380391 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4877 00:22:53.383117 ===================================
4878 00:22:53.386574 LPDDR4 DRAM CONFIGURATION
4879 00:22:53.389699 ===================================
4880 00:22:53.390139 EX_ROW_EN[0] = 0x10
4881 00:22:53.393534 EX_ROW_EN[1] = 0x0
4882 00:22:53.396443 LP4Y_EN = 0x0
4883 00:22:53.396881 WORK_FSP = 0x0
4884 00:22:53.399876 WL = 0x3
4885 00:22:53.400315 RL = 0x3
4886 00:22:53.402894 BL = 0x2
4887 00:22:53.403330 RPST = 0x0
4888 00:22:53.406580 RD_PRE = 0x0
4889 00:22:53.407022 WR_PRE = 0x1
4890 00:22:53.409575 WR_PST = 0x0
4891 00:22:53.410010 DBI_WR = 0x0
4892 00:22:53.413019 DBI_RD = 0x0
4893 00:22:53.413455 OTF = 0x1
4894 00:22:53.416108 ===================================
4895 00:22:53.422733 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4896 00:22:53.427194 nWR fixed to 30
4897 00:22:53.430703 [ModeRegInit_LP4] CH0 RK0
4898 00:22:53.431140 [ModeRegInit_LP4] CH0 RK1
4899 00:22:53.433652 [ModeRegInit_LP4] CH1 RK0
4900 00:22:53.437799 [ModeRegInit_LP4] CH1 RK1
4901 00:22:53.438360 match AC timing 8
4902 00:22:53.443932 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4903 00:22:53.447076 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4904 00:22:53.451096 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4905 00:22:53.457153 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4906 00:22:53.460555 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4907 00:22:53.460992 ==
4908 00:22:53.464229 Dram Type= 6, Freq= 0, CH_0, rank 0
4909 00:22:53.467161 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4910 00:22:53.467682 ==
4911 00:22:53.473936 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4912 00:22:53.480607 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4913 00:22:53.483584 [CA 0] Center 39 (8~70) winsize 63
4914 00:22:53.486963 [CA 1] Center 39 (8~70) winsize 63
4915 00:22:53.490643 [CA 2] Center 36 (6~67) winsize 62
4916 00:22:53.493810 [CA 3] Center 36 (6~66) winsize 61
4917 00:22:53.496866 [CA 4] Center 34 (4~65) winsize 62
4918 00:22:53.499971 [CA 5] Center 34 (4~65) winsize 62
4919 00:22:53.500409
4920 00:22:53.503407 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4921 00:22:53.503841
4922 00:22:53.506889 [CATrainingPosCal] consider 1 rank data
4923 00:22:53.510098 u2DelayCellTimex100 = 270/100 ps
4924 00:22:53.513490 CA0 delay=39 (8~70),Diff = 5 PI (31 cell)
4925 00:22:53.517021 CA1 delay=39 (8~70),Diff = 5 PI (31 cell)
4926 00:22:53.519937 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4927 00:22:53.523877 CA3 delay=36 (6~66),Diff = 2 PI (12 cell)
4928 00:22:53.526618 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4929 00:22:53.533555 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4930 00:22:53.533782
4931 00:22:53.536570 CA PerBit enable=1, Macro0, CA PI delay=34
4932 00:22:53.536748
4933 00:22:53.539722 [CBTSetCACLKResult] CA Dly = 34
4934 00:22:53.539900 CS Dly: 7 (0~38)
4935 00:22:53.540038 ==
4936 00:22:53.542937 Dram Type= 6, Freq= 0, CH_0, rank 1
4937 00:22:53.546442 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4938 00:22:53.549735 ==
4939 00:22:53.553305 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4940 00:22:53.560086 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4941 00:22:53.563198 [CA 0] Center 38 (8~69) winsize 62
4942 00:22:53.566540 [CA 1] Center 38 (7~69) winsize 63
4943 00:22:53.569589 [CA 2] Center 36 (5~67) winsize 63
4944 00:22:53.573256 [CA 3] Center 35 (5~66) winsize 62
4945 00:22:53.576146 [CA 4] Center 34 (4~64) winsize 61
4946 00:22:53.579871 [CA 5] Center 34 (4~65) winsize 62
4947 00:22:53.580147
4948 00:22:53.582755 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4949 00:22:53.583013
4950 00:22:53.586283 [CATrainingPosCal] consider 2 rank data
4951 00:22:53.589863 u2DelayCellTimex100 = 270/100 ps
4952 00:22:53.593169 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4953 00:22:53.596085 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4954 00:22:53.599960 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4955 00:22:53.606347 CA3 delay=36 (6~66),Diff = 2 PI (12 cell)
4956 00:22:53.609947 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
4957 00:22:53.613052 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4958 00:22:53.613569
4959 00:22:53.616161 CA PerBit enable=1, Macro0, CA PI delay=34
4960 00:22:53.616598
4961 00:22:53.619310 [CBTSetCACLKResult] CA Dly = 34
4962 00:22:53.619749 CS Dly: 7 (0~39)
4963 00:22:53.620089
4964 00:22:53.623053 ----->DramcWriteLeveling(PI) begin...
4965 00:22:53.623579 ==
4966 00:22:53.626742 Dram Type= 6, Freq= 0, CH_0, rank 0
4967 00:22:53.632977 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4968 00:22:53.633421 ==
4969 00:22:53.636367 Write leveling (Byte 0): 26 => 26
4970 00:22:53.639408 Write leveling (Byte 1): 25 => 25
4971 00:22:53.642536 DramcWriteLeveling(PI) end<-----
4972 00:22:53.642970
4973 00:22:53.643307 ==
4974 00:22:53.645638 Dram Type= 6, Freq= 0, CH_0, rank 0
4975 00:22:53.649515 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4976 00:22:53.649954 ==
4977 00:22:53.652482 [Gating] SW mode calibration
4978 00:22:53.659496 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4979 00:22:53.662556 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4980 00:22:53.669198 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4981 00:22:53.672816 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4982 00:22:53.675677 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4983 00:22:53.682618 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4984 00:22:53.686167 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4985 00:22:53.689210 0 10 20 | B1->B0 | 3434 3030 | 1 0 | (1 0) (1 0)
4986 00:22:53.695834 0 10 24 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
4987 00:22:53.699222 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4988 00:22:53.702660 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4989 00:22:53.709488 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4990 00:22:53.712734 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4991 00:22:53.716031 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4992 00:22:53.722031 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4993 00:22:53.725642 0 11 20 | B1->B0 | 2424 3030 | 0 0 | (0 0) (0 0)
4994 00:22:53.728916 0 11 24 | B1->B0 | 3939 4343 | 0 0 | (0 0) (0 0)
4995 00:22:53.735759 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4996 00:22:53.739006 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4997 00:22:53.742311 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4998 00:22:53.748738 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4999 00:22:53.751952 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5000 00:22:53.755276 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5001 00:22:53.762423 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5002 00:22:53.765624 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5003 00:22:53.769147 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5004 00:22:53.775332 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5005 00:22:53.779251 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5006 00:22:53.782300 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5007 00:22:53.788594 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5008 00:22:53.791869 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5009 00:22:53.794949 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5010 00:22:53.801582 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5011 00:22:53.804939 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5012 00:22:53.808388 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5013 00:22:53.815252 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5014 00:22:53.818056 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5015 00:22:53.821933 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5016 00:22:53.828600 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5017 00:22:53.831575 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5018 00:22:53.835019 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5019 00:22:53.838485 Total UI for P1: 0, mck2ui 16
5020 00:22:53.841421 best dqsien dly found for B0: ( 0, 14, 18)
5021 00:22:53.844873 Total UI for P1: 0, mck2ui 16
5022 00:22:53.848071 best dqsien dly found for B1: ( 0, 14, 18)
5023 00:22:53.852146 best DQS0 dly(MCK, UI, PI) = (0, 14, 18)
5024 00:22:53.855061 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5025 00:22:53.855495
5026 00:22:53.858143 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 18)
5027 00:22:53.865054 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5028 00:22:53.865575 [Gating] SW calibration Done
5029 00:22:53.867994 ==
5030 00:22:53.868427 Dram Type= 6, Freq= 0, CH_0, rank 0
5031 00:22:53.874365 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5032 00:22:53.874890 ==
5033 00:22:53.875239 RX Vref Scan: 0
5034 00:22:53.875549
5035 00:22:53.877650 RX Vref 0 -> 0, step: 1
5036 00:22:53.878083
5037 00:22:53.881276 RX Delay -80 -> 252, step: 8
5038 00:22:53.884194 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5039 00:22:53.887647 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5040 00:22:53.890798 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5041 00:22:53.897214 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5042 00:22:53.900940 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5043 00:22:53.904174 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5044 00:22:53.907334 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5045 00:22:53.910549 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5046 00:22:53.914429 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5047 00:22:53.920460 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5048 00:22:53.923957 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5049 00:22:53.926956 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5050 00:22:53.930418 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5051 00:22:53.934098 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5052 00:22:53.940605 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5053 00:22:53.943898 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5054 00:22:53.944414 ==
5055 00:22:53.946847 Dram Type= 6, Freq= 0, CH_0, rank 0
5056 00:22:53.950611 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5057 00:22:53.951129 ==
5058 00:22:53.954017 DQS Delay:
5059 00:22:53.954590 DQS0 = 0, DQS1 = 0
5060 00:22:53.954942 DQM Delay:
5061 00:22:53.957339 DQM0 = 98, DQM1 = 85
5062 00:22:53.957849 DQ Delay:
5063 00:22:53.961333 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =91
5064 00:22:53.963913 DQ4 =99, DQ5 =87, DQ6 =111, DQ7 =107
5065 00:22:53.967543 DQ8 =75, DQ9 =67, DQ10 =83, DQ11 =75
5066 00:22:53.970300 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5067 00:22:53.970750
5068 00:22:53.971087
5069 00:22:53.971395 ==
5070 00:22:53.973936 Dram Type= 6, Freq= 0, CH_0, rank 0
5071 00:22:53.980414 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5072 00:22:53.980852 ==
5073 00:22:53.981188
5074 00:22:53.981500
5075 00:22:53.981800 TX Vref Scan disable
5076 00:22:53.983399 == TX Byte 0 ==
5077 00:22:53.987475 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5078 00:22:53.990566 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5079 00:22:53.994202 == TX Byte 1 ==
5080 00:22:53.996995 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5081 00:22:54.003841 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5082 00:22:54.004358 ==
5083 00:22:54.006852 Dram Type= 6, Freq= 0, CH_0, rank 0
5084 00:22:54.010121 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5085 00:22:54.010612 ==
5086 00:22:54.010965
5087 00:22:54.011410
5088 00:22:54.013253 TX Vref Scan disable
5089 00:22:54.013685 == TX Byte 0 ==
5090 00:22:54.019910 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5091 00:22:54.023171 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5092 00:22:54.023608 == TX Byte 1 ==
5093 00:22:54.030159 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5094 00:22:54.033338 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5095 00:22:54.033865
5096 00:22:54.034209 [DATLAT]
5097 00:22:54.036769 Freq=933, CH0 RK0
5098 00:22:54.037457
5099 00:22:54.037824 DATLAT Default: 0xd
5100 00:22:54.040147 0, 0xFFFF, sum = 0
5101 00:22:54.040600 1, 0xFFFF, sum = 0
5102 00:22:54.043669 2, 0xFFFF, sum = 0
5103 00:22:54.044199 3, 0xFFFF, sum = 0
5104 00:22:54.046400 4, 0xFFFF, sum = 0
5105 00:22:54.049743 5, 0xFFFF, sum = 0
5106 00:22:54.050188 6, 0xFFFF, sum = 0
5107 00:22:54.053035 7, 0xFFFF, sum = 0
5108 00:22:54.053483 8, 0xFFFF, sum = 0
5109 00:22:54.056411 9, 0xFFFF, sum = 0
5110 00:22:54.056856 10, 0x0, sum = 1
5111 00:22:54.059870 11, 0x0, sum = 2
5112 00:22:54.060313 12, 0x0, sum = 3
5113 00:22:54.060663 13, 0x0, sum = 4
5114 00:22:54.062872 best_step = 11
5115 00:22:54.063308
5116 00:22:54.063648 ==
5117 00:22:54.066178 Dram Type= 6, Freq= 0, CH_0, rank 0
5118 00:22:54.069662 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5119 00:22:54.070196 ==
5120 00:22:54.073143 RX Vref Scan: 1
5121 00:22:54.073672
5122 00:22:54.076402 RX Vref 0 -> 0, step: 1
5123 00:22:54.076841
5124 00:22:54.077199 RX Delay -77 -> 252, step: 4
5125 00:22:54.077517
5126 00:22:54.079403 Set Vref, RX VrefLevel [Byte0]: 47
5127 00:22:54.082609 [Byte1]: 45
5128 00:22:54.087781
5129 00:22:54.088218 Final RX Vref Byte 0 = 47 to rank0
5130 00:22:54.090927 Final RX Vref Byte 1 = 45 to rank0
5131 00:22:54.094257 Final RX Vref Byte 0 = 47 to rank1
5132 00:22:54.097344 Final RX Vref Byte 1 = 45 to rank1==
5133 00:22:54.101133 Dram Type= 6, Freq= 0, CH_0, rank 0
5134 00:22:54.107466 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5135 00:22:54.108008 ==
5136 00:22:54.108358 DQS Delay:
5137 00:22:54.108675 DQS0 = 0, DQS1 = 0
5138 00:22:54.110790 DQM Delay:
5139 00:22:54.111231 DQM0 = 96, DQM1 = 86
5140 00:22:54.114154 DQ Delay:
5141 00:22:54.117535 DQ0 =92, DQ1 =98, DQ2 =94, DQ3 =90
5142 00:22:54.120922 DQ4 =100, DQ5 =90, DQ6 =104, DQ7 =104
5143 00:22:54.124188 DQ8 =76, DQ9 =70, DQ10 =86, DQ11 =80
5144 00:22:54.127214 DQ12 =94, DQ13 =92, DQ14 =98, DQ15 =96
5145 00:22:54.127650
5146 00:22:54.127988
5147 00:22:54.133673 [DQSOSCAuto] RK0, (LSB)MR18= 0x2525, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
5148 00:22:54.137179 CH0 RK0: MR19=505, MR18=2525
5149 00:22:54.144152 CH0_RK0: MR19=0x505, MR18=0x2525, DQSOSC=410, MR23=63, INC=64, DEC=42
5150 00:22:54.144678
5151 00:22:54.146892 ----->DramcWriteLeveling(PI) begin...
5152 00:22:54.147357 ==
5153 00:22:54.150397 Dram Type= 6, Freq= 0, CH_0, rank 1
5154 00:22:54.153618 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5155 00:22:54.154062 ==
5156 00:22:54.156852 Write leveling (Byte 0): 28 => 28
5157 00:22:54.160054 Write leveling (Byte 1): 28 => 28
5158 00:22:54.163519 DramcWriteLeveling(PI) end<-----
5159 00:22:54.163961
5160 00:22:54.164297 ==
5161 00:22:54.166817 Dram Type= 6, Freq= 0, CH_0, rank 1
5162 00:22:54.170052 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5163 00:22:54.173617 ==
5164 00:22:54.174053 [Gating] SW mode calibration
5165 00:22:54.183281 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5166 00:22:54.186759 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5167 00:22:54.190246 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5168 00:22:54.197031 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5169 00:22:54.199803 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5170 00:22:54.203436 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5171 00:22:54.209862 0 10 16 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
5172 00:22:54.213039 0 10 20 | B1->B0 | 3232 3030 | 0 0 | (1 0) (0 0)
5173 00:22:54.216830 0 10 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5174 00:22:54.222987 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5175 00:22:54.226099 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5176 00:22:54.229560 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5177 00:22:54.236190 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5178 00:22:54.239540 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5179 00:22:54.242793 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5180 00:22:54.249823 0 11 20 | B1->B0 | 2e2e 3939 | 0 0 | (0 0) (0 0)
5181 00:22:54.253030 0 11 24 | B1->B0 | 4444 4646 | 1 0 | (0 0) (0 0)
5182 00:22:54.256167 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5183 00:22:54.262933 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5184 00:22:54.265798 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5185 00:22:54.269801 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5186 00:22:54.276249 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5187 00:22:54.279887 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5188 00:22:54.282707 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5189 00:22:54.289662 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5190 00:22:54.292838 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 00:22:54.296183 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 00:22:54.302751 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 00:22:54.306107 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 00:22:54.309676 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 00:22:54.312829 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 00:22:54.319358 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 00:22:54.322792 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 00:22:54.326045 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 00:22:54.332861 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5200 00:22:54.335958 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 00:22:54.339402 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 00:22:54.346202 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5203 00:22:54.349187 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5204 00:22:54.353129 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5205 00:22:54.358901 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5206 00:22:54.362479 Total UI for P1: 0, mck2ui 16
5207 00:22:54.365729 best dqsien dly found for B0: ( 0, 14, 20)
5208 00:22:54.369430 Total UI for P1: 0, mck2ui 16
5209 00:22:54.372064 best dqsien dly found for B1: ( 0, 14, 20)
5210 00:22:54.375595 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
5211 00:22:54.378940 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5212 00:22:54.379461
5213 00:22:54.382526 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
5214 00:22:54.385627 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5215 00:22:54.389815 [Gating] SW calibration Done
5216 00:22:54.390377 ==
5217 00:22:54.392000 Dram Type= 6, Freq= 0, CH_0, rank 1
5218 00:22:54.395454 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5219 00:22:54.395984 ==
5220 00:22:54.398736 RX Vref Scan: 0
5221 00:22:54.399232
5222 00:22:54.401804 RX Vref 0 -> 0, step: 1
5223 00:22:54.402275
5224 00:22:54.402634 RX Delay -80 -> 252, step: 8
5225 00:22:54.408890 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5226 00:22:54.411866 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5227 00:22:54.415307 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5228 00:22:54.419024 iDelay=208, Bit 3, Center 91 (0 ~ 183) 184
5229 00:22:54.422275 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5230 00:22:54.425063 iDelay=208, Bit 5, Center 91 (-8 ~ 191) 200
5231 00:22:54.432193 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5232 00:22:54.435065 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5233 00:22:54.439030 iDelay=208, Bit 8, Center 75 (-16 ~ 167) 184
5234 00:22:54.441498 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5235 00:22:54.445414 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5236 00:22:54.451661 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5237 00:22:54.455195 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5238 00:22:54.458572 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5239 00:22:54.461854 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5240 00:22:54.465507 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5241 00:22:54.466025 ==
5242 00:22:54.468235 Dram Type= 6, Freq= 0, CH_0, rank 1
5243 00:22:54.474974 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5244 00:22:54.475505 ==
5245 00:22:54.475852 DQS Delay:
5246 00:22:54.478417 DQS0 = 0, DQS1 = 0
5247 00:22:54.478933 DQM Delay:
5248 00:22:54.479313 DQM0 = 96, DQM1 = 86
5249 00:22:54.481502 DQ Delay:
5250 00:22:54.485501 DQ0 =91, DQ1 =99, DQ2 =95, DQ3 =91
5251 00:22:54.488589 DQ4 =99, DQ5 =91, DQ6 =99, DQ7 =107
5252 00:22:54.491782 DQ8 =75, DQ9 =75, DQ10 =87, DQ11 =79
5253 00:22:54.495044 DQ12 =95, DQ13 =91, DQ14 =95, DQ15 =95
5254 00:22:54.495563
5255 00:22:54.495903
5256 00:22:54.496214 ==
5257 00:22:54.498138 Dram Type= 6, Freq= 0, CH_0, rank 1
5258 00:22:54.501299 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5259 00:22:54.501799 ==
5260 00:22:54.502146
5261 00:22:54.502521
5262 00:22:54.504606 TX Vref Scan disable
5263 00:22:54.505057 == TX Byte 0 ==
5264 00:22:54.511407 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5265 00:22:54.514772 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5266 00:22:54.515331 == TX Byte 1 ==
5267 00:22:54.521585 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5268 00:22:54.524357 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5269 00:22:54.524795 ==
5270 00:22:54.527743 Dram Type= 6, Freq= 0, CH_0, rank 1
5271 00:22:54.531026 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5272 00:22:54.531467 ==
5273 00:22:54.531808
5274 00:22:54.534806
5275 00:22:54.535239 TX Vref Scan disable
5276 00:22:54.537953 == TX Byte 0 ==
5277 00:22:54.541147 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5278 00:22:54.544700 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5279 00:22:54.547729 == TX Byte 1 ==
5280 00:22:54.551729 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5281 00:22:54.554674 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5282 00:22:54.555198
5283 00:22:54.557760 [DATLAT]
5284 00:22:54.558192 Freq=933, CH0 RK1
5285 00:22:54.558588
5286 00:22:54.561631 DATLAT Default: 0xb
5287 00:22:54.562173 0, 0xFFFF, sum = 0
5288 00:22:54.564825 1, 0xFFFF, sum = 0
5289 00:22:54.565349 2, 0xFFFF, sum = 0
5290 00:22:54.567597 3, 0xFFFF, sum = 0
5291 00:22:54.568040 4, 0xFFFF, sum = 0
5292 00:22:54.571044 5, 0xFFFF, sum = 0
5293 00:22:54.574184 6, 0xFFFF, sum = 0
5294 00:22:54.574671 7, 0xFFFF, sum = 0
5295 00:22:54.577721 8, 0xFFFF, sum = 0
5296 00:22:54.578306 9, 0xFFFF, sum = 0
5297 00:22:54.581000 10, 0x0, sum = 1
5298 00:22:54.581526 11, 0x0, sum = 2
5299 00:22:54.581876 12, 0x0, sum = 3
5300 00:22:54.584505 13, 0x0, sum = 4
5301 00:22:54.585036 best_step = 11
5302 00:22:54.585376
5303 00:22:54.587953 ==
5304 00:22:54.588467 Dram Type= 6, Freq= 0, CH_0, rank 1
5305 00:22:54.593957 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5306 00:22:54.594449 ==
5307 00:22:54.594798 RX Vref Scan: 0
5308 00:22:54.595115
5309 00:22:54.597577 RX Vref 0 -> 0, step: 1
5310 00:22:54.598091
5311 00:22:54.600628 RX Delay -77 -> 252, step: 4
5312 00:22:54.604469 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5313 00:22:54.610824 iDelay=203, Bit 1, Center 98 (3 ~ 194) 192
5314 00:22:54.613804 iDelay=203, Bit 2, Center 98 (7 ~ 190) 184
5315 00:22:54.617327 iDelay=203, Bit 3, Center 90 (-1 ~ 182) 184
5316 00:22:54.620228 iDelay=203, Bit 4, Center 102 (11 ~ 194) 184
5317 00:22:54.623812 iDelay=203, Bit 5, Center 90 (-1 ~ 182) 184
5318 00:22:54.630557 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5319 00:22:54.634036 iDelay=203, Bit 7, Center 106 (11 ~ 202) 192
5320 00:22:54.637165 iDelay=203, Bit 8, Center 74 (-13 ~ 162) 176
5321 00:22:54.640207 iDelay=203, Bit 9, Center 72 (-17 ~ 162) 180
5322 00:22:54.643619 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5323 00:22:54.649956 iDelay=203, Bit 11, Center 80 (-5 ~ 166) 172
5324 00:22:54.653866 iDelay=203, Bit 12, Center 94 (7 ~ 182) 176
5325 00:22:54.656965 iDelay=203, Bit 13, Center 90 (-1 ~ 182) 184
5326 00:22:54.660254 iDelay=203, Bit 14, Center 96 (7 ~ 186) 180
5327 00:22:54.663489 iDelay=203, Bit 15, Center 94 (3 ~ 186) 184
5328 00:22:54.663925 ==
5329 00:22:54.666951 Dram Type= 6, Freq= 0, CH_0, rank 1
5330 00:22:54.673582 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5331 00:22:54.674104 ==
5332 00:22:54.674487 DQS Delay:
5333 00:22:54.674804 DQS0 = 0, DQS1 = 0
5334 00:22:54.676711 DQM Delay:
5335 00:22:54.677141 DQM0 = 97, DQM1 = 86
5336 00:22:54.680193 DQ Delay:
5337 00:22:54.683713 DQ0 =92, DQ1 =98, DQ2 =98, DQ3 =90
5338 00:22:54.686940 DQ4 =102, DQ5 =90, DQ6 =104, DQ7 =106
5339 00:22:54.690313 DQ8 =74, DQ9 =72, DQ10 =88, DQ11 =80
5340 00:22:54.693566 DQ12 =94, DQ13 =90, DQ14 =96, DQ15 =94
5341 00:22:54.694081
5342 00:22:54.694478
5343 00:22:54.699924 [DQSOSCAuto] RK1, (LSB)MR18= 0x3636, (MSB)MR19= 0x505, tDQSOscB0 = 404 ps tDQSOscB1 = 404 ps
5344 00:22:54.704294 CH0 RK1: MR19=505, MR18=3636
5345 00:22:54.710307 CH0_RK1: MR19=0x505, MR18=0x3636, DQSOSC=404, MR23=63, INC=66, DEC=44
5346 00:22:54.712973 [RxdqsGatingPostProcess] freq 933
5347 00:22:54.717128 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5348 00:22:54.719760 Pre-setting of DQS Precalculation
5349 00:22:54.726476 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5350 00:22:54.726993 ==
5351 00:22:54.729886 Dram Type= 6, Freq= 0, CH_1, rank 0
5352 00:22:54.733402 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5353 00:22:54.733841 ==
5354 00:22:54.739848 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5355 00:22:54.746518 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
5356 00:22:54.749517 [CA 0] Center 37 (6~68) winsize 63
5357 00:22:54.753197 [CA 1] Center 37 (6~68) winsize 63
5358 00:22:54.756681 [CA 2] Center 34 (4~65) winsize 62
5359 00:22:54.760241 [CA 3] Center 34 (4~65) winsize 62
5360 00:22:54.763175 [CA 4] Center 32 (2~63) winsize 62
5361 00:22:54.763616 [CA 5] Center 33 (3~64) winsize 62
5362 00:22:54.766042
5363 00:22:54.769767 [CmdBusTrainingLP45] Vref(ca) range 1: 39
5364 00:22:54.770355
5365 00:22:54.773004 [CATrainingPosCal] consider 1 rank data
5366 00:22:54.776329 u2DelayCellTimex100 = 270/100 ps
5367 00:22:54.780115 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5368 00:22:54.782882 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5369 00:22:54.786468 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5370 00:22:54.789305 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5371 00:22:54.792496 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
5372 00:22:54.796192 CA5 delay=33 (3~64),Diff = 1 PI (6 cell)
5373 00:22:54.796625
5374 00:22:54.802671 CA PerBit enable=1, Macro0, CA PI delay=32
5375 00:22:54.803105
5376 00:22:54.803524 [CBTSetCACLKResult] CA Dly = 32
5377 00:22:54.805712 CS Dly: 5 (0~36)
5378 00:22:54.806138 ==
5379 00:22:54.809504 Dram Type= 6, Freq= 0, CH_1, rank 1
5380 00:22:54.812286 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5381 00:22:54.812591 ==
5382 00:22:54.819386 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5383 00:22:54.825797 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5384 00:22:54.829127 [CA 0] Center 37 (7~68) winsize 62
5385 00:22:54.832105 [CA 1] Center 37 (6~68) winsize 63
5386 00:22:54.835821 [CA 2] Center 34 (4~65) winsize 62
5387 00:22:54.838841 [CA 3] Center 34 (4~64) winsize 61
5388 00:22:54.842145 [CA 4] Center 33 (2~64) winsize 63
5389 00:22:54.845471 [CA 5] Center 33 (2~64) winsize 63
5390 00:22:54.845694
5391 00:22:54.848766 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5392 00:22:54.849188
5393 00:22:54.851904 [CATrainingPosCal] consider 2 rank data
5394 00:22:54.855778 u2DelayCellTimex100 = 270/100 ps
5395 00:22:54.858954 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5396 00:22:54.862486 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5397 00:22:54.865698 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5398 00:22:54.869218 CA3 delay=34 (4~64),Diff = 2 PI (12 cell)
5399 00:22:54.872083 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
5400 00:22:54.878871 CA5 delay=33 (3~64),Diff = 1 PI (6 cell)
5401 00:22:54.879311
5402 00:22:54.882087 CA PerBit enable=1, Macro0, CA PI delay=32
5403 00:22:54.882583
5404 00:22:54.885590 [CBTSetCACLKResult] CA Dly = 32
5405 00:22:54.886103 CS Dly: 5 (0~37)
5406 00:22:54.886508
5407 00:22:54.888708 ----->DramcWriteLeveling(PI) begin...
5408 00:22:54.889148 ==
5409 00:22:54.892511 Dram Type= 6, Freq= 0, CH_1, rank 0
5410 00:22:54.895235 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5411 00:22:54.898915 ==
5412 00:22:54.899422 Write leveling (Byte 0): 25 => 25
5413 00:22:54.902065 Write leveling (Byte 1): 25 => 25
5414 00:22:54.905417 DramcWriteLeveling(PI) end<-----
5415 00:22:54.905848
5416 00:22:54.906181 ==
5417 00:22:54.908392 Dram Type= 6, Freq= 0, CH_1, rank 0
5418 00:22:54.915169 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5419 00:22:54.915726 ==
5420 00:22:54.919033 [Gating] SW mode calibration
5421 00:22:54.925238 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5422 00:22:54.928959 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5423 00:22:54.935336 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5424 00:22:54.938938 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5425 00:22:54.942010 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5426 00:22:54.945383 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5427 00:22:54.952026 0 10 16 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
5428 00:22:54.955242 0 10 20 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
5429 00:22:54.958622 0 10 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5430 00:22:54.965226 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5431 00:22:54.969014 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5432 00:22:54.971918 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5433 00:22:54.978772 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5434 00:22:54.981759 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5435 00:22:54.985436 0 11 16 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
5436 00:22:54.991755 0 11 20 | B1->B0 | 2828 4242 | 1 0 | (0 0) (0 0)
5437 00:22:54.995315 0 11 24 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
5438 00:22:54.998370 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5439 00:22:55.004998 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5440 00:22:55.008133 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5441 00:22:55.011509 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5442 00:22:55.018049 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5443 00:22:55.021737 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5444 00:22:55.024987 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5445 00:22:55.031304 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5446 00:22:55.034898 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5447 00:22:55.038262 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5448 00:22:55.045119 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5449 00:22:55.048135 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5450 00:22:55.051170 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5451 00:22:55.058600 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5452 00:22:55.061746 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5453 00:22:55.064635 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5454 00:22:55.071902 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5455 00:22:55.075111 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5456 00:22:55.078016 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5457 00:22:55.084524 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5458 00:22:55.088099 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5459 00:22:55.091387 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5460 00:22:55.098520 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5461 00:22:55.099034 Total UI for P1: 0, mck2ui 16
5462 00:22:55.101695 best dqsien dly found for B0: ( 0, 14, 16)
5463 00:22:55.107791 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5464 00:22:55.111535 Total UI for P1: 0, mck2ui 16
5465 00:22:55.114806 best dqsien dly found for B1: ( 0, 14, 20)
5466 00:22:55.117754 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5467 00:22:55.121194 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5468 00:22:55.121627
5469 00:22:55.124457 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5470 00:22:55.127710 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5471 00:22:55.130962 [Gating] SW calibration Done
5472 00:22:55.131395 ==
5473 00:22:55.134586 Dram Type= 6, Freq= 0, CH_1, rank 0
5474 00:22:55.137475 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5475 00:22:55.137913 ==
5476 00:22:55.141355 RX Vref Scan: 0
5477 00:22:55.141870
5478 00:22:55.144325 RX Vref 0 -> 0, step: 1
5479 00:22:55.144856
5480 00:22:55.145196 RX Delay -80 -> 252, step: 8
5481 00:22:55.150896 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5482 00:22:55.154769 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5483 00:22:55.157898 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5484 00:22:55.161470 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5485 00:22:55.165036 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5486 00:22:55.171106 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5487 00:22:55.174273 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5488 00:22:55.177578 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5489 00:22:55.181390 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5490 00:22:55.184470 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5491 00:22:55.187718 iDelay=208, Bit 10, Center 87 (-16 ~ 191) 208
5492 00:22:55.194620 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5493 00:22:55.198000 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5494 00:22:55.201188 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5495 00:22:55.204044 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5496 00:22:55.208105 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5497 00:22:55.208622 ==
5498 00:22:55.210933 Dram Type= 6, Freq= 0, CH_1, rank 0
5499 00:22:55.217864 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5500 00:22:55.218418 ==
5501 00:22:55.218763 DQS Delay:
5502 00:22:55.220985 DQS0 = 0, DQS1 = 0
5503 00:22:55.221418 DQM Delay:
5504 00:22:55.221758 DQM0 = 95, DQM1 = 88
5505 00:22:55.224165 DQ Delay:
5506 00:22:55.227662 DQ0 =103, DQ1 =91, DQ2 =83, DQ3 =91
5507 00:22:55.230669 DQ4 =91, DQ5 =107, DQ6 =107, DQ7 =91
5508 00:22:55.233873 DQ8 =71, DQ9 =79, DQ10 =87, DQ11 =79
5509 00:22:55.237629 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =99
5510 00:22:55.238141
5511 00:22:55.238539
5512 00:22:55.238854 ==
5513 00:22:55.240611 Dram Type= 6, Freq= 0, CH_1, rank 0
5514 00:22:55.244279 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5515 00:22:55.244853 ==
5516 00:22:55.245201
5517 00:22:55.245512
5518 00:22:55.247162 TX Vref Scan disable
5519 00:22:55.250332 == TX Byte 0 ==
5520 00:22:55.253857 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5521 00:22:55.256847 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5522 00:22:55.260505 == TX Byte 1 ==
5523 00:22:55.263601 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5524 00:22:55.266893 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5525 00:22:55.267332 ==
5526 00:22:55.270317 Dram Type= 6, Freq= 0, CH_1, rank 0
5527 00:22:55.276948 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5528 00:22:55.277387 ==
5529 00:22:55.277729
5530 00:22:55.278041
5531 00:22:55.278403 TX Vref Scan disable
5532 00:22:55.280794 == TX Byte 0 ==
5533 00:22:55.283928 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5534 00:22:55.290858 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5535 00:22:55.291376 == TX Byte 1 ==
5536 00:22:55.293693 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5537 00:22:55.300368 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5538 00:22:55.300805
5539 00:22:55.301145 [DATLAT]
5540 00:22:55.301455 Freq=933, CH1 RK0
5541 00:22:55.301759
5542 00:22:55.303819 DATLAT Default: 0xd
5543 00:22:55.306706 0, 0xFFFF, sum = 0
5544 00:22:55.307104 1, 0xFFFF, sum = 0
5545 00:22:55.310059 2, 0xFFFF, sum = 0
5546 00:22:55.310498 3, 0xFFFF, sum = 0
5547 00:22:55.313462 4, 0xFFFF, sum = 0
5548 00:22:55.313859 5, 0xFFFF, sum = 0
5549 00:22:55.316999 6, 0xFFFF, sum = 0
5550 00:22:55.317487 7, 0xFFFF, sum = 0
5551 00:22:55.320060 8, 0xFFFF, sum = 0
5552 00:22:55.320457 9, 0xFFFF, sum = 0
5553 00:22:55.323516 10, 0x0, sum = 1
5554 00:22:55.323995 11, 0x0, sum = 2
5555 00:22:55.326820 12, 0x0, sum = 3
5556 00:22:55.327351 13, 0x0, sum = 4
5557 00:22:55.327771 best_step = 11
5558 00:22:55.329838
5559 00:22:55.330257 ==
5560 00:22:55.333548 Dram Type= 6, Freq= 0, CH_1, rank 0
5561 00:22:55.336570 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5562 00:22:55.336965 ==
5563 00:22:55.337270 RX Vref Scan: 1
5564 00:22:55.337558
5565 00:22:55.340011 RX Vref 0 -> 0, step: 1
5566 00:22:55.340404
5567 00:22:55.343155 RX Delay -69 -> 252, step: 4
5568 00:22:55.343548
5569 00:22:55.346517 Set Vref, RX VrefLevel [Byte0]: 58
5570 00:22:55.350299 [Byte1]: 50
5571 00:22:55.353065
5572 00:22:55.353455 Final RX Vref Byte 0 = 58 to rank0
5573 00:22:55.356663 Final RX Vref Byte 1 = 50 to rank0
5574 00:22:55.359902 Final RX Vref Byte 0 = 58 to rank1
5575 00:22:55.363611 Final RX Vref Byte 1 = 50 to rank1==
5576 00:22:55.366445 Dram Type= 6, Freq= 0, CH_1, rank 0
5577 00:22:55.372896 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5578 00:22:55.373294 ==
5579 00:22:55.373604 DQS Delay:
5580 00:22:55.376149 DQS0 = 0, DQS1 = 0
5581 00:22:55.376545 DQM Delay:
5582 00:22:55.376850 DQM0 = 94, DQM1 = 87
5583 00:22:55.379870 DQ Delay:
5584 00:22:55.382787 DQ0 =96, DQ1 =88, DQ2 =86, DQ3 =92
5585 00:22:55.386403 DQ4 =94, DQ5 =106, DQ6 =100, DQ7 =92
5586 00:22:55.389666 DQ8 =72, DQ9 =76, DQ10 =90, DQ11 =80
5587 00:22:55.393530 DQ12 =94, DQ13 =98, DQ14 =96, DQ15 =96
5588 00:22:55.393930
5589 00:22:55.394284
5590 00:22:55.399507 [DQSOSCAuto] RK0, (LSB)MR18= 0x3e3e, (MSB)MR19= 0x505, tDQSOscB0 = 402 ps tDQSOscB1 = 402 ps
5591 00:22:55.402724 CH1 RK0: MR19=505, MR18=3E3E
5592 00:22:55.409490 CH1_RK0: MR19=0x505, MR18=0x3E3E, DQSOSC=402, MR23=63, INC=67, DEC=44
5593 00:22:55.409886
5594 00:22:55.413003 ----->DramcWriteLeveling(PI) begin...
5595 00:22:55.413405 ==
5596 00:22:55.416485 Dram Type= 6, Freq= 0, CH_1, rank 1
5597 00:22:55.419586 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5598 00:22:55.420065 ==
5599 00:22:55.422795 Write leveling (Byte 0): 23 => 23
5600 00:22:55.426604 Write leveling (Byte 1): 22 => 22
5601 00:22:55.429681 DramcWriteLeveling(PI) end<-----
5602 00:22:55.430073
5603 00:22:55.430444 ==
5604 00:22:55.432648 Dram Type= 6, Freq= 0, CH_1, rank 1
5605 00:22:55.436611 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5606 00:22:55.437088 ==
5607 00:22:55.439381 [Gating] SW mode calibration
5608 00:22:55.446295 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5609 00:22:55.452751 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5610 00:22:55.456342 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5611 00:22:55.463287 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5612 00:22:55.466027 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5613 00:22:55.469099 0 10 12 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
5614 00:22:55.476193 0 10 16 | B1->B0 | 3434 2525 | 1 0 | (1 0) (0 0)
5615 00:22:55.479187 0 10 20 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
5616 00:22:55.482923 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5617 00:22:55.489001 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5618 00:22:55.492601 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5619 00:22:55.495710 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5620 00:22:55.499323 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5621 00:22:55.505764 0 11 12 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5622 00:22:55.509107 0 11 16 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (1 1)
5623 00:22:55.512358 0 11 20 | B1->B0 | 3333 4646 | 1 0 | (0 0) (0 0)
5624 00:22:55.519279 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5625 00:22:55.522457 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5626 00:22:55.525993 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5627 00:22:55.532138 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5628 00:22:55.535504 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5629 00:22:55.538845 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5630 00:22:55.545610 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5631 00:22:55.548924 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5632 00:22:55.552573 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 00:22:55.559076 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 00:22:55.562079 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 00:22:55.565439 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 00:22:55.573061 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 00:22:55.575776 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 00:22:55.578787 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 00:22:55.585357 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 00:22:55.588620 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 00:22:55.592163 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 00:22:55.598676 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 00:22:55.601762 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 00:22:55.605393 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 00:22:55.611660 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 00:22:55.615000 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5647 00:22:55.618660 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5648 00:22:55.621669 Total UI for P1: 0, mck2ui 16
5649 00:22:55.625076 best dqsien dly found for B0: ( 0, 14, 16)
5650 00:22:55.628179 Total UI for P1: 0, mck2ui 16
5651 00:22:55.631425 best dqsien dly found for B1: ( 0, 14, 16)
5652 00:22:55.635250 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5653 00:22:55.638341 best DQS1 dly(MCK, UI, PI) = (0, 14, 16)
5654 00:22:55.638777
5655 00:22:55.645117 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5656 00:22:55.648409 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 16)
5657 00:22:55.648958 [Gating] SW calibration Done
5658 00:22:55.651552 ==
5659 00:22:55.655558 Dram Type= 6, Freq= 0, CH_1, rank 1
5660 00:22:55.658684 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5661 00:22:55.659200 ==
5662 00:22:55.659541 RX Vref Scan: 0
5663 00:22:55.659853
5664 00:22:55.661666 RX Vref 0 -> 0, step: 1
5665 00:22:55.662100
5666 00:22:55.664755 RX Delay -80 -> 252, step: 8
5667 00:22:55.668703 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5668 00:22:55.672126 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5669 00:22:55.675137 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5670 00:22:55.681853 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5671 00:22:55.685023 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5672 00:22:55.688365 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5673 00:22:55.691521 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5674 00:22:55.695140 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5675 00:22:55.698616 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5676 00:22:55.704515 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5677 00:22:55.708662 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5678 00:22:55.711405 iDelay=208, Bit 11, Center 79 (-24 ~ 183) 208
5679 00:22:55.714647 iDelay=208, Bit 12, Center 95 (-8 ~ 199) 208
5680 00:22:55.718284 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5681 00:22:55.725075 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5682 00:22:55.728221 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5683 00:22:55.728659 ==
5684 00:22:55.731469 Dram Type= 6, Freq= 0, CH_1, rank 1
5685 00:22:55.734544 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5686 00:22:55.734979 ==
5687 00:22:55.737791 DQS Delay:
5688 00:22:55.738251 DQS0 = 0, DQS1 = 0
5689 00:22:55.738599 DQM Delay:
5690 00:22:55.741483 DQM0 = 95, DQM1 = 86
5691 00:22:55.742013 DQ Delay:
5692 00:22:55.744436 DQ0 =99, DQ1 =91, DQ2 =87, DQ3 =91
5693 00:22:55.747897 DQ4 =91, DQ5 =107, DQ6 =103, DQ7 =91
5694 00:22:55.751404 DQ8 =75, DQ9 =75, DQ10 =91, DQ11 =79
5695 00:22:55.755071 DQ12 =95, DQ13 =95, DQ14 =91, DQ15 =91
5696 00:22:55.755502
5697 00:22:55.755879
5698 00:22:55.756193 ==
5699 00:22:55.757754 Dram Type= 6, Freq= 0, CH_1, rank 1
5700 00:22:55.764467 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5701 00:22:55.764987 ==
5702 00:22:55.765333
5703 00:22:55.765687
5704 00:22:55.766032 TX Vref Scan disable
5705 00:22:55.767926 == TX Byte 0 ==
5706 00:22:55.771627 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5707 00:22:55.777982 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5708 00:22:55.778558 == TX Byte 1 ==
5709 00:22:55.781371 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5710 00:22:55.787913 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5711 00:22:55.788431 ==
5712 00:22:55.791051 Dram Type= 6, Freq= 0, CH_1, rank 1
5713 00:22:55.794762 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5714 00:22:55.795280 ==
5715 00:22:55.795623
5716 00:22:55.795935
5717 00:22:55.798309 TX Vref Scan disable
5718 00:22:55.798744 == TX Byte 0 ==
5719 00:22:55.804408 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5720 00:22:55.808108 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5721 00:22:55.808630 == TX Byte 1 ==
5722 00:22:55.814549 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5723 00:22:55.817739 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5724 00:22:55.818186
5725 00:22:55.818577 [DATLAT]
5726 00:22:55.821174 Freq=933, CH1 RK1
5727 00:22:55.821682
5728 00:22:55.822018 DATLAT Default: 0xb
5729 00:22:55.824180 0, 0xFFFF, sum = 0
5730 00:22:55.824616 1, 0xFFFF, sum = 0
5731 00:22:55.827563 2, 0xFFFF, sum = 0
5732 00:22:55.828016 3, 0xFFFF, sum = 0
5733 00:22:55.830733 4, 0xFFFF, sum = 0
5734 00:22:55.834373 5, 0xFFFF, sum = 0
5735 00:22:55.834825 6, 0xFFFF, sum = 0
5736 00:22:55.837327 7, 0xFFFF, sum = 0
5737 00:22:55.837779 8, 0xFFFF, sum = 0
5738 00:22:55.840797 9, 0xFFFF, sum = 0
5739 00:22:55.841247 10, 0x0, sum = 1
5740 00:22:55.844141 11, 0x0, sum = 2
5741 00:22:55.844594 12, 0x0, sum = 3
5742 00:22:55.845035 13, 0x0, sum = 4
5743 00:22:55.847309 best_step = 11
5744 00:22:55.847752
5745 00:22:55.848181 ==
5746 00:22:55.850616 Dram Type= 6, Freq= 0, CH_1, rank 1
5747 00:22:55.853715 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5748 00:22:55.854191 ==
5749 00:22:55.857663 RX Vref Scan: 0
5750 00:22:55.858197
5751 00:22:55.860463 RX Vref 0 -> 0, step: 1
5752 00:22:55.860909
5753 00:22:55.861345 RX Delay -69 -> 252, step: 4
5754 00:22:55.868387 iDelay=203, Bit 0, Center 98 (7 ~ 190) 184
5755 00:22:55.871758 iDelay=203, Bit 1, Center 92 (-1 ~ 186) 188
5756 00:22:55.874893 iDelay=203, Bit 2, Center 86 (-5 ~ 178) 184
5757 00:22:55.878539 iDelay=203, Bit 3, Center 92 (-1 ~ 186) 188
5758 00:22:55.881807 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5759 00:22:55.885037 iDelay=203, Bit 5, Center 106 (11 ~ 202) 192
5760 00:22:55.891882 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5761 00:22:55.895003 iDelay=203, Bit 7, Center 94 (-1 ~ 190) 192
5762 00:22:55.898175 iDelay=203, Bit 8, Center 74 (-17 ~ 166) 184
5763 00:22:55.901805 iDelay=203, Bit 9, Center 76 (-17 ~ 170) 188
5764 00:22:55.905036 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5765 00:22:55.911339 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5766 00:22:55.914669 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188
5767 00:22:55.917985 iDelay=203, Bit 13, Center 96 (7 ~ 186) 180
5768 00:22:55.921374 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5769 00:22:55.924847 iDelay=203, Bit 15, Center 94 (3 ~ 186) 184
5770 00:22:55.925363 ==
5771 00:22:55.928276 Dram Type= 6, Freq= 0, CH_1, rank 1
5772 00:22:55.934662 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5773 00:22:55.935179 ==
5774 00:22:55.935521 DQS Delay:
5775 00:22:55.937969 DQS0 = 0, DQS1 = 0
5776 00:22:55.938459 DQM Delay:
5777 00:22:55.938806 DQM0 = 96, DQM1 = 87
5778 00:22:55.941171 DQ Delay:
5779 00:22:55.944539 DQ0 =98, DQ1 =92, DQ2 =86, DQ3 =92
5780 00:22:55.948046 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =94
5781 00:22:55.951381 DQ8 =74, DQ9 =76, DQ10 =88, DQ11 =80
5782 00:22:55.954639 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =94
5783 00:22:55.955073
5784 00:22:55.955412
5785 00:22:55.961542 [DQSOSCAuto] RK1, (LSB)MR18= 0x2424, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
5786 00:22:55.964420 CH1 RK1: MR19=505, MR18=2424
5787 00:22:55.971616 CH1_RK1: MR19=0x505, MR18=0x2424, DQSOSC=410, MR23=63, INC=64, DEC=42
5788 00:22:55.974649 [RxdqsGatingPostProcess] freq 933
5789 00:22:55.978288 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5790 00:22:55.981179 Pre-setting of DQS Precalculation
5791 00:22:55.987678 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5792 00:22:55.994303 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5793 00:22:56.001258 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5794 00:22:56.001818
5795 00:22:56.002158
5796 00:22:56.003842 [Calibration Summary] 1866 Mbps
5797 00:22:56.007335 CH 0, Rank 0
5798 00:22:56.007851 SW Impedance : PASS
5799 00:22:56.010916 DUTY Scan : NO K
5800 00:22:56.014113 ZQ Calibration : PASS
5801 00:22:56.014598 Jitter Meter : NO K
5802 00:22:56.017422 CBT Training : PASS
5803 00:22:56.017961 Write leveling : PASS
5804 00:22:56.020687 RX DQS gating : PASS
5805 00:22:56.023769 RX DQ/DQS(RDDQC) : PASS
5806 00:22:56.024205 TX DQ/DQS : PASS
5807 00:22:56.027316 RX DATLAT : PASS
5808 00:22:56.030433 RX DQ/DQS(Engine): PASS
5809 00:22:56.030868 TX OE : NO K
5810 00:22:56.033979 All Pass.
5811 00:22:56.034479
5812 00:22:56.034824 CH 0, Rank 1
5813 00:22:56.037309 SW Impedance : PASS
5814 00:22:56.037805 DUTY Scan : NO K
5815 00:22:56.040276 ZQ Calibration : PASS
5816 00:22:56.043777 Jitter Meter : NO K
5817 00:22:56.044213 CBT Training : PASS
5818 00:22:56.047076 Write leveling : PASS
5819 00:22:56.050137 RX DQS gating : PASS
5820 00:22:56.050608 RX DQ/DQS(RDDQC) : PASS
5821 00:22:56.053720 TX DQ/DQS : PASS
5822 00:22:56.057033 RX DATLAT : PASS
5823 00:22:56.057551 RX DQ/DQS(Engine): PASS
5824 00:22:56.060418 TX OE : NO K
5825 00:22:56.060855 All Pass.
5826 00:22:56.061190
5827 00:22:56.063809 CH 1, Rank 0
5828 00:22:56.064329 SW Impedance : PASS
5829 00:22:56.067236 DUTY Scan : NO K
5830 00:22:56.070578 ZQ Calibration : PASS
5831 00:22:56.071091 Jitter Meter : NO K
5832 00:22:56.073872 CBT Training : PASS
5833 00:22:56.077356 Write leveling : PASS
5834 00:22:56.077871 RX DQS gating : PASS
5835 00:22:56.080286 RX DQ/DQS(RDDQC) : PASS
5836 00:22:56.080720 TX DQ/DQS : PASS
5837 00:22:56.083642 RX DATLAT : PASS
5838 00:22:56.087060 RX DQ/DQS(Engine): PASS
5839 00:22:56.087495 TX OE : NO K
5840 00:22:56.090276 All Pass.
5841 00:22:56.090711
5842 00:22:56.091051 CH 1, Rank 1
5843 00:22:56.094022 SW Impedance : PASS
5844 00:22:56.094638 DUTY Scan : NO K
5845 00:22:56.097011 ZQ Calibration : PASS
5846 00:22:56.099858 Jitter Meter : NO K
5847 00:22:56.100293 CBT Training : PASS
5848 00:22:56.103346 Write leveling : PASS
5849 00:22:56.107053 RX DQS gating : PASS
5850 00:22:56.107569 RX DQ/DQS(RDDQC) : PASS
5851 00:22:56.110067 TX DQ/DQS : PASS
5852 00:22:56.113536 RX DATLAT : PASS
5853 00:22:56.113973 RX DQ/DQS(Engine): PASS
5854 00:22:56.116600 TX OE : NO K
5855 00:22:56.117032 All Pass.
5856 00:22:56.117364
5857 00:22:56.119751 DramC Write-DBI off
5858 00:22:56.122967 PER_BANK_REFRESH: Hybrid Mode
5859 00:22:56.123403 TX_TRACKING: ON
5860 00:22:56.133251 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5861 00:22:56.136896 [FAST_K] Save calibration result to emmc
5862 00:22:56.139880 dramc_set_vcore_voltage set vcore to 650000
5863 00:22:56.142904 Read voltage for 400, 6
5864 00:22:56.143341 Vio18 = 0
5865 00:22:56.143677 Vcore = 650000
5866 00:22:56.146628 Vdram = 0
5867 00:22:56.147014 Vddq = 0
5868 00:22:56.147325 Vmddr = 0
5869 00:22:56.152817 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5870 00:22:56.156653 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5871 00:22:56.159536 MEM_TYPE=3, freq_sel=20
5872 00:22:56.163130 sv_algorithm_assistance_LP4_800
5873 00:22:56.166270 ============ PULL DRAM RESETB DOWN ============
5874 00:22:56.170001 ========== PULL DRAM RESETB DOWN end =========
5875 00:22:56.176587 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5876 00:22:56.179581 ===================================
5877 00:22:56.182574 LPDDR4 DRAM CONFIGURATION
5878 00:22:56.186259 ===================================
5879 00:22:56.186781 EX_ROW_EN[0] = 0x0
5880 00:22:56.189678 EX_ROW_EN[1] = 0x0
5881 00:22:56.190185 LP4Y_EN = 0x0
5882 00:22:56.193120 WORK_FSP = 0x0
5883 00:22:56.193631 WL = 0x2
5884 00:22:56.196209 RL = 0x2
5885 00:22:56.196642 BL = 0x2
5886 00:22:56.199241 RPST = 0x0
5887 00:22:56.199675 RD_PRE = 0x0
5888 00:22:56.202618 WR_PRE = 0x1
5889 00:22:56.203146 WR_PST = 0x0
5890 00:22:56.206042 DBI_WR = 0x0
5891 00:22:56.206503 DBI_RD = 0x0
5892 00:22:56.209346 OTF = 0x1
5893 00:22:56.212686 ===================================
5894 00:22:56.215725 ===================================
5895 00:22:56.216163 ANA top config
5896 00:22:56.219480 ===================================
5897 00:22:56.222566 DLL_ASYNC_EN = 0
5898 00:22:56.225763 ALL_SLAVE_EN = 1
5899 00:22:56.228875 NEW_RANK_MODE = 1
5900 00:22:56.232153 DLL_IDLE_MODE = 1
5901 00:22:56.232587 LP45_APHY_COMB_EN = 1
5902 00:22:56.235652 TX_ODT_DIS = 1
5903 00:22:56.239165 NEW_8X_MODE = 1
5904 00:22:56.242057 ===================================
5905 00:22:56.245626 ===================================
5906 00:22:56.248884 data_rate = 800
5907 00:22:56.252520 CKR = 1
5908 00:22:56.252971 DQ_P2S_RATIO = 4
5909 00:22:56.255203 ===================================
5910 00:22:56.258560 CA_P2S_RATIO = 4
5911 00:22:56.261879 DQ_CA_OPEN = 0
5912 00:22:56.265394 DQ_SEMI_OPEN = 1
5913 00:22:56.268682 CA_SEMI_OPEN = 1
5914 00:22:56.271634 CA_FULL_RATE = 0
5915 00:22:56.272073 DQ_CKDIV4_EN = 0
5916 00:22:56.275579 CA_CKDIV4_EN = 1
5917 00:22:56.278590 CA_PREDIV_EN = 0
5918 00:22:56.281916 PH8_DLY = 0
5919 00:22:56.285617 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5920 00:22:56.288570 DQ_AAMCK_DIV = 0
5921 00:22:56.288962 CA_AAMCK_DIV = 0
5922 00:22:56.291744 CA_ADMCK_DIV = 4
5923 00:22:56.294898 DQ_TRACK_CA_EN = 0
5924 00:22:56.298606 CA_PICK = 800
5925 00:22:56.301925 CA_MCKIO = 400
5926 00:22:56.305305 MCKIO_SEMI = 400
5927 00:22:56.308666 PLL_FREQ = 3016
5928 00:22:56.311806 DQ_UI_PI_RATIO = 32
5929 00:22:56.312318 CA_UI_PI_RATIO = 32
5930 00:22:56.314753 ===================================
5931 00:22:56.318184 ===================================
5932 00:22:56.321781 memory_type:LPDDR4
5933 00:22:56.324771 GP_NUM : 10
5934 00:22:56.325288 SRAM_EN : 1
5935 00:22:56.328416 MD32_EN : 0
5936 00:22:56.331329 ===================================
5937 00:22:56.334509 [ANA_INIT] >>>>>>>>>>>>>>
5938 00:22:56.338035 <<<<<< [CONFIGURE PHASE]: ANA_TX
5939 00:22:56.341326 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5940 00:22:56.344680 ===================================
5941 00:22:56.345200 data_rate = 800,PCW = 0X7400
5942 00:22:56.348170 ===================================
5943 00:22:56.351112 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5944 00:22:56.357905 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5945 00:22:56.370978 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5946 00:22:56.374089 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5947 00:22:56.377201 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5948 00:22:56.380765 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5949 00:22:56.384127 [ANA_INIT] flow start
5950 00:22:56.384639 [ANA_INIT] PLL >>>>>>>>
5951 00:22:56.387513 [ANA_INIT] PLL <<<<<<<<
5952 00:22:56.390527 [ANA_INIT] MIDPI >>>>>>>>
5953 00:22:56.393819 [ANA_INIT] MIDPI <<<<<<<<
5954 00:22:56.394369 [ANA_INIT] DLL >>>>>>>>
5955 00:22:56.397700 [ANA_INIT] flow end
5956 00:22:56.400713 ============ LP4 DIFF to SE enter ============
5957 00:22:56.403784 ============ LP4 DIFF to SE exit ============
5958 00:22:56.407251 [ANA_INIT] <<<<<<<<<<<<<
5959 00:22:56.410949 [Flow] Enable top DCM control >>>>>
5960 00:22:56.414190 [Flow] Enable top DCM control <<<<<
5961 00:22:56.416841 Enable DLL master slave shuffle
5962 00:22:56.423858 ==============================================================
5963 00:22:56.424296 Gating Mode config
5964 00:22:56.430805 ==============================================================
5965 00:22:56.431539 Config description:
5966 00:22:56.440154 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5967 00:22:56.446674 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5968 00:22:56.453501 SELPH_MODE 0: By rank 1: By Phase
5969 00:22:56.457386 ==============================================================
5970 00:22:56.460657 GAT_TRACK_EN = 0
5971 00:22:56.463620 RX_GATING_MODE = 2
5972 00:22:56.466931 RX_GATING_TRACK_MODE = 2
5973 00:22:56.470203 SELPH_MODE = 1
5974 00:22:56.473572 PICG_EARLY_EN = 1
5975 00:22:56.476441 VALID_LAT_VALUE = 1
5976 00:22:56.483788 ==============================================================
5977 00:22:56.486624 Enter into Gating configuration >>>>
5978 00:22:56.487061 Exit from Gating configuration <<<<
5979 00:22:56.490092 Enter into DVFS_PRE_config >>>>>
5980 00:22:56.503092 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5981 00:22:56.506238 Exit from DVFS_PRE_config <<<<<
5982 00:22:56.509446 Enter into PICG configuration >>>>
5983 00:22:56.513099 Exit from PICG configuration <<<<
5984 00:22:56.513659 [RX_INPUT] configuration >>>>>
5985 00:22:56.516074 [RX_INPUT] configuration <<<<<
5986 00:22:56.523092 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5987 00:22:56.526325 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5988 00:22:56.533366 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5989 00:22:56.539643 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5990 00:22:56.546289 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5991 00:22:56.552969 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5992 00:22:56.556273 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5993 00:22:56.559590 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5994 00:22:56.565951 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5995 00:22:56.569653 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5996 00:22:56.572780 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5997 00:22:56.578790 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5998 00:22:56.582492 ===================================
5999 00:22:56.582891 LPDDR4 DRAM CONFIGURATION
6000 00:22:56.586339 ===================================
6001 00:22:56.589132 EX_ROW_EN[0] = 0x0
6002 00:22:56.589629 EX_ROW_EN[1] = 0x0
6003 00:22:56.592255 LP4Y_EN = 0x0
6004 00:22:56.592648 WORK_FSP = 0x0
6005 00:22:56.595391 WL = 0x2
6006 00:22:56.599170 RL = 0x2
6007 00:22:56.599649 BL = 0x2
6008 00:22:56.602541 RPST = 0x0
6009 00:22:56.602983 RD_PRE = 0x0
6010 00:22:56.605850 WR_PRE = 0x1
6011 00:22:56.606332 WR_PST = 0x0
6012 00:22:56.608704 DBI_WR = 0x0
6013 00:22:56.609096 DBI_RD = 0x0
6014 00:22:56.612458 OTF = 0x1
6015 00:22:56.615216 ===================================
6016 00:22:56.618424 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6017 00:22:56.621928 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6018 00:22:56.625162 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6019 00:22:56.628758 ===================================
6020 00:22:56.631866 LPDDR4 DRAM CONFIGURATION
6021 00:22:56.635230 ===================================
6022 00:22:56.638586 EX_ROW_EN[0] = 0x10
6023 00:22:56.639108 EX_ROW_EN[1] = 0x0
6024 00:22:56.641821 LP4Y_EN = 0x0
6025 00:22:56.642282 WORK_FSP = 0x0
6026 00:22:56.645303 WL = 0x2
6027 00:22:56.645716 RL = 0x2
6028 00:22:56.648787 BL = 0x2
6029 00:22:56.652176 RPST = 0x0
6030 00:22:56.652575 RD_PRE = 0x0
6031 00:22:56.655528 WR_PRE = 0x1
6032 00:22:56.656011 WR_PST = 0x0
6033 00:22:56.658375 DBI_WR = 0x0
6034 00:22:56.658778 DBI_RD = 0x0
6035 00:22:56.661709 OTF = 0x1
6036 00:22:56.666108 ===================================
6037 00:22:56.671794 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6038 00:22:56.674939 nWR fixed to 30
6039 00:22:56.675502 [ModeRegInit_LP4] CH0 RK0
6040 00:22:56.678929 [ModeRegInit_LP4] CH0 RK1
6041 00:22:56.681680 [ModeRegInit_LP4] CH1 RK0
6042 00:22:56.682166 [ModeRegInit_LP4] CH1 RK1
6043 00:22:56.685114 match AC timing 18
6044 00:22:56.688571 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
6045 00:22:56.691424 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6046 00:22:56.698241 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6047 00:22:56.701479 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6048 00:22:56.708037 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6049 00:22:56.708446 ==
6050 00:22:56.711427 Dram Type= 6, Freq= 0, CH_0, rank 0
6051 00:22:56.715107 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6052 00:22:56.715512 ==
6053 00:22:56.721694 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6054 00:22:56.725239 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6055 00:22:56.728061 [CA 0] Center 36 (8~64) winsize 57
6056 00:22:56.731273 [CA 1] Center 36 (8~64) winsize 57
6057 00:22:56.734870 [CA 2] Center 36 (8~64) winsize 57
6058 00:22:56.738146 [CA 3] Center 36 (8~64) winsize 57
6059 00:22:56.741593 [CA 4] Center 36 (8~64) winsize 57
6060 00:22:56.744467 [CA 5] Center 36 (8~64) winsize 57
6061 00:22:56.744867
6062 00:22:56.748219 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6063 00:22:56.748614
6064 00:22:56.751038 [CATrainingPosCal] consider 1 rank data
6065 00:22:56.754420 u2DelayCellTimex100 = 270/100 ps
6066 00:22:56.758202 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6067 00:22:56.761143 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6068 00:22:56.768069 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6069 00:22:56.771263 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6070 00:22:56.774379 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6071 00:22:56.777928 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6072 00:22:56.778444
6073 00:22:56.781033 CA PerBit enable=1, Macro0, CA PI delay=36
6074 00:22:56.781425
6075 00:22:56.784688 [CBTSetCACLKResult] CA Dly = 36
6076 00:22:56.785160 CS Dly: 1 (0~32)
6077 00:22:56.785468 ==
6078 00:22:56.787973 Dram Type= 6, Freq= 0, CH_0, rank 1
6079 00:22:56.794261 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6080 00:22:56.794664 ==
6081 00:22:56.797708 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6082 00:22:56.804412 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6083 00:22:56.807799 [CA 0] Center 36 (8~64) winsize 57
6084 00:22:56.810714 [CA 1] Center 36 (8~64) winsize 57
6085 00:22:56.814061 [CA 2] Center 36 (8~64) winsize 57
6086 00:22:56.817922 [CA 3] Center 36 (8~64) winsize 57
6087 00:22:56.821126 [CA 4] Center 36 (8~64) winsize 57
6088 00:22:56.824446 [CA 5] Center 36 (8~64) winsize 57
6089 00:22:56.824852
6090 00:22:56.827927 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6091 00:22:56.828407
6092 00:22:56.830739 [CATrainingPosCal] consider 2 rank data
6093 00:22:56.834127 u2DelayCellTimex100 = 270/100 ps
6094 00:22:56.838120 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6095 00:22:56.840881 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6096 00:22:56.844026 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6097 00:22:56.847349 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6098 00:22:56.850668 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6099 00:22:56.857647 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6100 00:22:56.858131
6101 00:22:56.860603 CA PerBit enable=1, Macro0, CA PI delay=36
6102 00:22:56.861084
6103 00:22:56.863747 [CBTSetCACLKResult] CA Dly = 36
6104 00:22:56.864143 CS Dly: 1 (0~32)
6105 00:22:56.864447
6106 00:22:56.867274 ----->DramcWriteLeveling(PI) begin...
6107 00:22:56.867752 ==
6108 00:22:56.870688 Dram Type= 6, Freq= 0, CH_0, rank 0
6109 00:22:56.874558 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6110 00:22:56.877098 ==
6111 00:22:56.877494 Write leveling (Byte 0): 32 => 0
6112 00:22:56.880684 Write leveling (Byte 1): 32 => 0
6113 00:22:56.884459 DramcWriteLeveling(PI) end<-----
6114 00:22:56.884969
6115 00:22:56.885306 ==
6116 00:22:56.887113 Dram Type= 6, Freq= 0, CH_0, rank 0
6117 00:22:56.894136 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6118 00:22:56.894688 ==
6119 00:22:56.895031 [Gating] SW mode calibration
6120 00:22:56.903848 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6121 00:22:56.907089 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6122 00:22:56.910589 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6123 00:22:56.917361 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6124 00:22:56.921004 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6125 00:22:56.923553 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6126 00:22:56.930589 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6127 00:22:56.933872 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6128 00:22:56.937277 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6129 00:22:56.943292 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6130 00:22:56.947010 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6131 00:22:56.950140 Total UI for P1: 0, mck2ui 16
6132 00:22:56.953585 best dqsien dly found for B0: ( 0, 10, 16)
6133 00:22:56.956988 Total UI for P1: 0, mck2ui 16
6134 00:22:56.959901 best dqsien dly found for B1: ( 0, 10, 24)
6135 00:22:56.963259 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6136 00:22:56.966526 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6137 00:22:56.966962
6138 00:22:56.969803 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6139 00:22:56.976319 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6140 00:22:56.976755 [Gating] SW calibration Done
6141 00:22:56.979975 ==
6142 00:22:56.980417 Dram Type= 6, Freq= 0, CH_0, rank 0
6143 00:22:56.986647 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6144 00:22:56.987175 ==
6145 00:22:56.987520 RX Vref Scan: 0
6146 00:22:56.987833
6147 00:22:56.989759 RX Vref 0 -> 0, step: 1
6148 00:22:56.990190
6149 00:22:56.993037 RX Delay -410 -> 252, step: 16
6150 00:22:56.996202 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6151 00:22:57.000423 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6152 00:22:57.006143 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6153 00:22:57.009731 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6154 00:22:57.013384 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6155 00:22:57.016048 iDelay=230, Bit 5, Center -51 (-298 ~ 197) 496
6156 00:22:57.022860 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6157 00:22:57.026476 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6158 00:22:57.029790 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6159 00:22:57.032787 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6160 00:22:57.039602 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6161 00:22:57.042672 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6162 00:22:57.046355 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6163 00:22:57.053008 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6164 00:22:57.056165 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6165 00:22:57.059478 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6166 00:22:57.059911 ==
6167 00:22:57.062620 Dram Type= 6, Freq= 0, CH_0, rank 0
6168 00:22:57.066055 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6169 00:22:57.066621 ==
6170 00:22:57.069432 DQS Delay:
6171 00:22:57.069963 DQS0 = 51, DQS1 = 59
6172 00:22:57.072306 DQM Delay:
6173 00:22:57.072737 DQM0 = 12, DQM1 = 16
6174 00:22:57.076261 DQ Delay:
6175 00:22:57.076697 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6176 00:22:57.079077 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6177 00:22:57.082460 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6178 00:22:57.086000 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6179 00:22:57.086566
6180 00:22:57.086914
6181 00:22:57.087225 ==
6182 00:22:57.089257 Dram Type= 6, Freq= 0, CH_0, rank 0
6183 00:22:57.095832 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6184 00:22:57.096365 ==
6185 00:22:57.096712
6186 00:22:57.097023
6187 00:22:57.097322 TX Vref Scan disable
6188 00:22:57.099145 == TX Byte 0 ==
6189 00:22:57.102424 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6190 00:22:57.108973 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6191 00:22:57.109575 == TX Byte 1 ==
6192 00:22:57.112487 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6193 00:22:57.118924 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6194 00:22:57.119362 ==
6195 00:22:57.122720 Dram Type= 6, Freq= 0, CH_0, rank 0
6196 00:22:57.126056 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6197 00:22:57.126618 ==
6198 00:22:57.126959
6199 00:22:57.127267
6200 00:22:57.129009 TX Vref Scan disable
6201 00:22:57.129530 == TX Byte 0 ==
6202 00:22:57.132164 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6203 00:22:57.139184 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6204 00:22:57.139698 == TX Byte 1 ==
6205 00:22:57.142099 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6206 00:22:57.148901 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6207 00:22:57.149409
6208 00:22:57.149751 [DATLAT]
6209 00:22:57.150197 Freq=400, CH0 RK0
6210 00:22:57.152373
6211 00:22:57.153003 DATLAT Default: 0xf
6212 00:22:57.155628 0, 0xFFFF, sum = 0
6213 00:22:57.156093 1, 0xFFFF, sum = 0
6214 00:22:57.158709 2, 0xFFFF, sum = 0
6215 00:22:57.159151 3, 0xFFFF, sum = 0
6216 00:22:57.162264 4, 0xFFFF, sum = 0
6217 00:22:57.162708 5, 0xFFFF, sum = 0
6218 00:22:57.165430 6, 0xFFFF, sum = 0
6219 00:22:57.165877 7, 0xFFFF, sum = 0
6220 00:22:57.169005 8, 0xFFFF, sum = 0
6221 00:22:57.169552 9, 0xFFFF, sum = 0
6222 00:22:57.172502 10, 0xFFFF, sum = 0
6223 00:22:57.173032 11, 0xFFFF, sum = 0
6224 00:22:57.175248 12, 0x0, sum = 1
6225 00:22:57.175699 13, 0x0, sum = 2
6226 00:22:57.178459 14, 0x0, sum = 3
6227 00:22:57.178908 15, 0x0, sum = 4
6228 00:22:57.182030 best_step = 13
6229 00:22:57.182492
6230 00:22:57.182834 ==
6231 00:22:57.185941 Dram Type= 6, Freq= 0, CH_0, rank 0
6232 00:22:57.188712 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6233 00:22:57.189237 ==
6234 00:22:57.192439 RX Vref Scan: 1
6235 00:22:57.192981
6236 00:22:57.193324 RX Vref 0 -> 0, step: 1
6237 00:22:57.193639
6238 00:22:57.195442 RX Delay -359 -> 252, step: 8
6239 00:22:57.195883
6240 00:22:57.198513 Set Vref, RX VrefLevel [Byte0]: 47
6241 00:22:57.202014 [Byte1]: 45
6242 00:22:57.206310
6243 00:22:57.206831 Final RX Vref Byte 0 = 47 to rank0
6244 00:22:57.209772 Final RX Vref Byte 1 = 45 to rank0
6245 00:22:57.213170 Final RX Vref Byte 0 = 47 to rank1
6246 00:22:57.216655 Final RX Vref Byte 1 = 45 to rank1==
6247 00:22:57.219741 Dram Type= 6, Freq= 0, CH_0, rank 0
6248 00:22:57.226864 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6249 00:22:57.227390 ==
6250 00:22:57.227735 DQS Delay:
6251 00:22:57.229652 DQS0 = 52, DQS1 = 68
6252 00:22:57.230178 DQM Delay:
6253 00:22:57.230568 DQM0 = 9, DQM1 = 17
6254 00:22:57.232891 DQ Delay:
6255 00:22:57.236087 DQ0 =4, DQ1 =8, DQ2 =8, DQ3 =4
6256 00:22:57.236527 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6257 00:22:57.239495 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6258 00:22:57.242773 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =28
6259 00:22:57.243211
6260 00:22:57.245844
6261 00:22:57.252831 [DQSOSCAuto] RK0, (LSB)MR18= 0xb0b0, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
6262 00:22:57.255850 CH0 RK0: MR19=C0C, MR18=B0B0
6263 00:22:57.262937 CH0_RK0: MR19=0xC0C, MR18=0xB0B0, DQSOSC=387, MR23=63, INC=394, DEC=262
6264 00:22:57.263382 ==
6265 00:22:57.266199 Dram Type= 6, Freq= 0, CH_0, rank 1
6266 00:22:57.269725 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6267 00:22:57.270299 ==
6268 00:22:57.272965 [Gating] SW mode calibration
6269 00:22:57.279334 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6270 00:22:57.282558 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6271 00:22:57.288901 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6272 00:22:57.292694 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6273 00:22:57.296447 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6274 00:22:57.302536 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6275 00:22:57.306304 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6276 00:22:57.309775 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6277 00:22:57.315911 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6278 00:22:57.319687 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6279 00:22:57.322759 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6280 00:22:57.326370 Total UI for P1: 0, mck2ui 16
6281 00:22:57.329323 best dqsien dly found for B0: ( 0, 10, 16)
6282 00:22:57.332458 Total UI for P1: 0, mck2ui 16
6283 00:22:57.335658 best dqsien dly found for B1: ( 0, 10, 16)
6284 00:22:57.338897 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6285 00:22:57.342432 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6286 00:22:57.345774
6287 00:22:57.348815 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6288 00:22:57.352355 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6289 00:22:57.355593 [Gating] SW calibration Done
6290 00:22:57.356032 ==
6291 00:22:57.358859 Dram Type= 6, Freq= 0, CH_0, rank 1
6292 00:22:57.362050 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6293 00:22:57.362615 ==
6294 00:22:57.365744 RX Vref Scan: 0
6295 00:22:57.366317
6296 00:22:57.366665 RX Vref 0 -> 0, step: 1
6297 00:22:57.366986
6298 00:22:57.369157 RX Delay -410 -> 252, step: 16
6299 00:22:57.372479 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6300 00:22:57.378651 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6301 00:22:57.382000 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6302 00:22:57.385543 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6303 00:22:57.388816 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6304 00:22:57.395084 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6305 00:22:57.398513 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6306 00:22:57.402160 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6307 00:22:57.404898 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6308 00:22:57.411734 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6309 00:22:57.415260 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6310 00:22:57.418306 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6311 00:22:57.424865 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6312 00:22:57.428329 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6313 00:22:57.431922 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6314 00:22:57.435143 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6315 00:22:57.438012 ==
6316 00:22:57.438490 Dram Type= 6, Freq= 0, CH_0, rank 1
6317 00:22:57.445143 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6318 00:22:57.445672 ==
6319 00:22:57.446016 DQS Delay:
6320 00:22:57.448544 DQS0 = 43, DQS1 = 59
6321 00:22:57.449063 DQM Delay:
6322 00:22:57.451282 DQM0 = 7, DQM1 = 16
6323 00:22:57.451739 DQ Delay:
6324 00:22:57.455240 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6325 00:22:57.457668 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6326 00:22:57.461557 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6327 00:22:57.464604 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6328 00:22:57.465043
6329 00:22:57.465384
6330 00:22:57.465694 ==
6331 00:22:57.467674 Dram Type= 6, Freq= 0, CH_0, rank 1
6332 00:22:57.470917 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6333 00:22:57.471357 ==
6334 00:22:57.471698
6335 00:22:57.472010
6336 00:22:57.474472 TX Vref Scan disable
6337 00:22:57.475002 == TX Byte 0 ==
6338 00:22:57.481154 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6339 00:22:57.484839 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6340 00:22:57.485360 == TX Byte 1 ==
6341 00:22:57.488269 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6342 00:22:57.494676 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6343 00:22:57.495194 ==
6344 00:22:57.497477 Dram Type= 6, Freq= 0, CH_0, rank 1
6345 00:22:57.500877 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6346 00:22:57.501319 ==
6347 00:22:57.501659
6348 00:22:57.501975
6349 00:22:57.504115 TX Vref Scan disable
6350 00:22:57.504553 == TX Byte 0 ==
6351 00:22:57.510952 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6352 00:22:57.513861 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6353 00:22:57.514352 == TX Byte 1 ==
6354 00:22:57.520655 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6355 00:22:57.524201 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6356 00:22:57.524642
6357 00:22:57.524981 [DATLAT]
6358 00:22:57.527417 Freq=400, CH0 RK1
6359 00:22:57.527857
6360 00:22:57.528194 DATLAT Default: 0xd
6361 00:22:57.530504 0, 0xFFFF, sum = 0
6362 00:22:57.530948 1, 0xFFFF, sum = 0
6363 00:22:57.534131 2, 0xFFFF, sum = 0
6364 00:22:57.534690 3, 0xFFFF, sum = 0
6365 00:22:57.537098 4, 0xFFFF, sum = 0
6366 00:22:57.537705 5, 0xFFFF, sum = 0
6367 00:22:57.540664 6, 0xFFFF, sum = 0
6368 00:22:57.541186 7, 0xFFFF, sum = 0
6369 00:22:57.544413 8, 0xFFFF, sum = 0
6370 00:22:57.544860 9, 0xFFFF, sum = 0
6371 00:22:57.547406 10, 0xFFFF, sum = 0
6372 00:22:57.547848 11, 0xFFFF, sum = 0
6373 00:22:57.550629 12, 0x0, sum = 1
6374 00:22:57.551069 13, 0x0, sum = 2
6375 00:22:57.553910 14, 0x0, sum = 3
6376 00:22:57.554390 15, 0x0, sum = 4
6377 00:22:57.557281 best_step = 13
6378 00:22:57.557709
6379 00:22:57.558051 ==
6380 00:22:57.560389 Dram Type= 6, Freq= 0, CH_0, rank 1
6381 00:22:57.564042 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6382 00:22:57.564477 ==
6383 00:22:57.566948 RX Vref Scan: 0
6384 00:22:57.567383
6385 00:22:57.567721 RX Vref 0 -> 0, step: 1
6386 00:22:57.568036
6387 00:22:57.570486 RX Delay -359 -> 252, step: 8
6388 00:22:57.578759 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6389 00:22:57.581749 iDelay=217, Bit 1, Center -40 (-295 ~ 216) 512
6390 00:22:57.585211 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6391 00:22:57.589480 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6392 00:22:57.595848 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6393 00:22:57.598739 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6394 00:22:57.601985 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6395 00:22:57.605328 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6396 00:22:57.611914 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6397 00:22:57.615059 iDelay=217, Bit 9, Center -64 (-303 ~ 176) 480
6398 00:22:57.618126 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6399 00:22:57.625298 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6400 00:22:57.628569 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6401 00:22:57.631920 iDelay=217, Bit 13, Center -44 (-287 ~ 200) 488
6402 00:22:57.634842 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6403 00:22:57.642320 iDelay=217, Bit 15, Center -44 (-287 ~ 200) 488
6404 00:22:57.642838 ==
6405 00:22:57.645090 Dram Type= 6, Freq= 0, CH_0, rank 1
6406 00:22:57.647839 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6407 00:22:57.648282 ==
6408 00:22:57.648676 DQS Delay:
6409 00:22:57.651181 DQS0 = 52, DQS1 = 64
6410 00:22:57.651615 DQM Delay:
6411 00:22:57.654614 DQM0 = 9, DQM1 = 13
6412 00:22:57.655048 DQ Delay:
6413 00:22:57.658913 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =4
6414 00:22:57.661433 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6415 00:22:57.664786 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6416 00:22:57.667997 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6417 00:22:57.668518
6418 00:22:57.668855
6419 00:22:57.674762 [DQSOSCAuto] RK1, (LSB)MR18= 0xd5d5, (MSB)MR19= 0xc0c, tDQSOscB0 = 383 ps tDQSOscB1 = 383 ps
6420 00:22:57.677781 CH0 RK1: MR19=C0C, MR18=D5D5
6421 00:22:57.685136 CH0_RK1: MR19=0xC0C, MR18=0xD5D5, DQSOSC=383, MR23=63, INC=402, DEC=268
6422 00:22:57.688203 [RxdqsGatingPostProcess] freq 400
6423 00:22:57.694566 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6424 00:22:57.698304 Pre-setting of DQS Precalculation
6425 00:22:57.700859 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6426 00:22:57.701322 ==
6427 00:22:57.704539 Dram Type= 6, Freq= 0, CH_1, rank 0
6428 00:22:57.707813 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6429 00:22:57.708259 ==
6430 00:22:57.714329 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6431 00:22:57.720744 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6432 00:22:57.724311 [CA 0] Center 36 (8~64) winsize 57
6433 00:22:57.727316 [CA 1] Center 36 (8~64) winsize 57
6434 00:22:57.730671 [CA 2] Center 36 (8~64) winsize 57
6435 00:22:57.734277 [CA 3] Center 36 (8~64) winsize 57
6436 00:22:57.737506 [CA 4] Center 36 (8~64) winsize 57
6437 00:22:57.740662 [CA 5] Center 36 (8~64) winsize 57
6438 00:22:57.741095
6439 00:22:57.744307 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6440 00:22:57.744739
6441 00:22:57.747196 [CATrainingPosCal] consider 1 rank data
6442 00:22:57.750682 u2DelayCellTimex100 = 270/100 ps
6443 00:22:57.753962 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6444 00:22:57.756949 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6445 00:22:57.760529 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6446 00:22:57.763807 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6447 00:22:57.767589 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6448 00:22:57.770298 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6449 00:22:57.770690
6450 00:22:57.773655 CA PerBit enable=1, Macro0, CA PI delay=36
6451 00:22:57.774044
6452 00:22:57.777373 [CBTSetCACLKResult] CA Dly = 36
6453 00:22:57.780417 CS Dly: 1 (0~32)
6454 00:22:57.780805 ==
6455 00:22:57.783990 Dram Type= 6, Freq= 0, CH_1, rank 1
6456 00:22:57.787667 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6457 00:22:57.788109 ==
6458 00:22:57.793971 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6459 00:22:57.801140 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6460 00:22:57.803751 [CA 0] Center 36 (8~64) winsize 57
6461 00:22:57.804144 [CA 1] Center 36 (8~64) winsize 57
6462 00:22:57.807476 [CA 2] Center 36 (8~64) winsize 57
6463 00:22:57.810489 [CA 3] Center 36 (8~64) winsize 57
6464 00:22:57.813840 [CA 4] Center 36 (8~64) winsize 57
6465 00:22:57.817142 [CA 5] Center 36 (8~64) winsize 57
6466 00:22:57.817617
6467 00:22:57.820549 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6468 00:22:57.820947
6469 00:22:57.827375 [CATrainingPosCal] consider 2 rank data
6470 00:22:57.828121 u2DelayCellTimex100 = 270/100 ps
6471 00:22:57.833527 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6472 00:22:57.836770 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6473 00:22:57.840105 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6474 00:22:57.843398 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6475 00:22:57.846769 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6476 00:22:57.850015 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6477 00:22:57.850506
6478 00:22:57.853492 CA PerBit enable=1, Macro0, CA PI delay=36
6479 00:22:57.854004
6480 00:22:57.856597 [CBTSetCACLKResult] CA Dly = 36
6481 00:22:57.860247 CS Dly: 1 (0~32)
6482 00:22:57.860722
6483 00:22:57.863351 ----->DramcWriteLeveling(PI) begin...
6484 00:22:57.863798 ==
6485 00:22:57.866904 Dram Type= 6, Freq= 0, CH_1, rank 0
6486 00:22:57.870658 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6487 00:22:57.871177 ==
6488 00:22:57.873401 Write leveling (Byte 0): 32 => 0
6489 00:22:57.876937 Write leveling (Byte 1): 32 => 0
6490 00:22:57.880352 DramcWriteLeveling(PI) end<-----
6491 00:22:57.880797
6492 00:22:57.881132 ==
6493 00:22:57.883457 Dram Type= 6, Freq= 0, CH_1, rank 0
6494 00:22:57.886805 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6495 00:22:57.887339 ==
6496 00:22:57.890886 [Gating] SW mode calibration
6497 00:22:57.896687 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6498 00:22:57.903156 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6499 00:22:57.906888 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6500 00:22:57.910464 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6501 00:22:57.916556 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6502 00:22:57.919663 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6503 00:22:57.923222 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6504 00:22:57.929841 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6505 00:22:57.933186 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6506 00:22:57.936660 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6507 00:22:57.942881 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6508 00:22:57.943324 Total UI for P1: 0, mck2ui 16
6509 00:22:57.947046 best dqsien dly found for B0: ( 0, 10, 16)
6510 00:22:57.949528 Total UI for P1: 0, mck2ui 16
6511 00:22:57.953063 best dqsien dly found for B1: ( 0, 10, 16)
6512 00:22:57.959793 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6513 00:22:57.963372 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6514 00:22:57.963886
6515 00:22:57.966954 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6516 00:22:57.969924 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6517 00:22:57.972926 [Gating] SW calibration Done
6518 00:22:57.973363 ==
6519 00:22:57.976471 Dram Type= 6, Freq= 0, CH_1, rank 0
6520 00:22:57.979855 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6521 00:22:57.980376 ==
6522 00:22:57.982875 RX Vref Scan: 0
6523 00:22:57.983312
6524 00:22:57.983669 RX Vref 0 -> 0, step: 1
6525 00:22:57.983988
6526 00:22:57.986245 RX Delay -410 -> 252, step: 16
6527 00:22:57.992958 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6528 00:22:57.996306 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6529 00:22:57.999769 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6530 00:22:58.003133 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6531 00:22:58.009610 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6532 00:22:58.013508 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6533 00:22:58.016377 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6534 00:22:58.019466 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6535 00:22:58.026065 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6536 00:22:58.029344 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6537 00:22:58.032757 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6538 00:22:58.035892 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6539 00:22:58.042703 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6540 00:22:58.045764 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6541 00:22:58.049087 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6542 00:22:58.052731 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6543 00:22:58.053248 ==
6544 00:22:58.055631 Dram Type= 6, Freq= 0, CH_1, rank 0
6545 00:22:58.062387 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6546 00:22:58.062906 ==
6547 00:22:58.063254 DQS Delay:
6548 00:22:58.065803 DQS0 = 43, DQS1 = 59
6549 00:22:58.066291 DQM Delay:
6550 00:22:58.069198 DQM0 = 6, DQM1 = 15
6551 00:22:58.069631 DQ Delay:
6552 00:22:58.072331 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6553 00:22:58.075675 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6554 00:22:58.078861 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6555 00:22:58.082355 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =32
6556 00:22:58.082812
6557 00:22:58.083151
6558 00:22:58.083468 ==
6559 00:22:58.085788 Dram Type= 6, Freq= 0, CH_1, rank 0
6560 00:22:58.088424 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6561 00:22:58.088870 ==
6562 00:22:58.089292
6563 00:22:58.089622
6564 00:22:58.092039 TX Vref Scan disable
6565 00:22:58.092478 == TX Byte 0 ==
6566 00:22:58.099057 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6567 00:22:58.102153 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6568 00:22:58.102638 == TX Byte 1 ==
6569 00:22:58.108634 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6570 00:22:58.112200 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6571 00:22:58.112639 ==
6572 00:22:58.115665 Dram Type= 6, Freq= 0, CH_1, rank 0
6573 00:22:58.118621 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6574 00:22:58.119019 ==
6575 00:22:58.119330
6576 00:22:58.119616
6577 00:22:58.121632 TX Vref Scan disable
6578 00:22:58.125177 == TX Byte 0 ==
6579 00:22:58.128344 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6580 00:22:58.132058 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6581 00:22:58.135063 == TX Byte 1 ==
6582 00:22:58.138294 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6583 00:22:58.141500 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6584 00:22:58.141939
6585 00:22:58.142315 [DATLAT]
6586 00:22:58.145029 Freq=400, CH1 RK0
6587 00:22:58.145544
6588 00:22:58.145888 DATLAT Default: 0xf
6589 00:22:58.148222 0, 0xFFFF, sum = 0
6590 00:22:58.151834 1, 0xFFFF, sum = 0
6591 00:22:58.152282 2, 0xFFFF, sum = 0
6592 00:22:58.154768 3, 0xFFFF, sum = 0
6593 00:22:58.155214 4, 0xFFFF, sum = 0
6594 00:22:58.158324 5, 0xFFFF, sum = 0
6595 00:22:58.158859 6, 0xFFFF, sum = 0
6596 00:22:58.161306 7, 0xFFFF, sum = 0
6597 00:22:58.161750 8, 0xFFFF, sum = 0
6598 00:22:58.165006 9, 0xFFFF, sum = 0
6599 00:22:58.165525 10, 0xFFFF, sum = 0
6600 00:22:58.168728 11, 0xFFFF, sum = 0
6601 00:22:58.169250 12, 0x0, sum = 1
6602 00:22:58.171448 13, 0x0, sum = 2
6603 00:22:58.171896 14, 0x0, sum = 3
6604 00:22:58.175583 15, 0x0, sum = 4
6605 00:22:58.176150 best_step = 13
6606 00:22:58.176493
6607 00:22:58.176808 ==
6608 00:22:58.177993 Dram Type= 6, Freq= 0, CH_1, rank 0
6609 00:22:58.181550 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6610 00:22:58.184821 ==
6611 00:22:58.185336 RX Vref Scan: 1
6612 00:22:58.185693
6613 00:22:58.187964 RX Vref 0 -> 0, step: 1
6614 00:22:58.188547
6615 00:22:58.191132 RX Delay -359 -> 252, step: 8
6616 00:22:58.191569
6617 00:22:58.194448 Set Vref, RX VrefLevel [Byte0]: 58
6618 00:22:58.197983 [Byte1]: 50
6619 00:22:58.198452
6620 00:22:58.201479 Final RX Vref Byte 0 = 58 to rank0
6621 00:22:58.204335 Final RX Vref Byte 1 = 50 to rank0
6622 00:22:58.207781 Final RX Vref Byte 0 = 58 to rank1
6623 00:22:58.211107 Final RX Vref Byte 1 = 50 to rank1==
6624 00:22:58.214499 Dram Type= 6, Freq= 0, CH_1, rank 0
6625 00:22:58.217921 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6626 00:22:58.218402 ==
6627 00:22:58.221228 DQS Delay:
6628 00:22:58.221660 DQS0 = 52, DQS1 = 64
6629 00:22:58.224043 DQM Delay:
6630 00:22:58.224545 DQM0 = 10, DQM1 = 15
6631 00:22:58.227519 DQ Delay:
6632 00:22:58.227956 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6633 00:22:58.231370 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =8
6634 00:22:58.234333 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6635 00:22:58.237511 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6636 00:22:58.237948
6637 00:22:58.238319
6638 00:22:58.247039 [DQSOSCAuto] RK0, (LSB)MR18= 0xe9e9, (MSB)MR19= 0xc0c, tDQSOscB0 = 381 ps tDQSOscB1 = 381 ps
6639 00:22:58.250499 CH1 RK0: MR19=C0C, MR18=E9E9
6640 00:22:58.257465 CH1_RK0: MR19=0xC0C, MR18=0xE9E9, DQSOSC=381, MR23=63, INC=406, DEC=271
6641 00:22:58.257905 ==
6642 00:22:58.260977 Dram Type= 6, Freq= 0, CH_1, rank 1
6643 00:22:58.264174 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6644 00:22:58.264698 ==
6645 00:22:58.267507 [Gating] SW mode calibration
6646 00:22:58.274008 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6647 00:22:58.277837 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6648 00:22:58.283950 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6649 00:22:58.287054 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6650 00:22:58.290895 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6651 00:22:58.297131 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6652 00:22:58.300356 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6653 00:22:58.303607 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6654 00:22:58.309907 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6655 00:22:58.313698 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6656 00:22:58.316352 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6657 00:22:58.320544 Total UI for P1: 0, mck2ui 16
6658 00:22:58.323769 best dqsien dly found for B0: ( 0, 10, 16)
6659 00:22:58.326540 Total UI for P1: 0, mck2ui 16
6660 00:22:58.330185 best dqsien dly found for B1: ( 0, 10, 16)
6661 00:22:58.333389 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6662 00:22:58.339588 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6663 00:22:58.340120
6664 00:22:58.343097 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6665 00:22:58.346864 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6666 00:22:58.349931 [Gating] SW calibration Done
6667 00:22:58.350480 ==
6668 00:22:58.352972 Dram Type= 6, Freq= 0, CH_1, rank 1
6669 00:22:58.356555 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6670 00:22:58.357020 ==
6671 00:22:58.359697 RX Vref Scan: 0
6672 00:22:58.360168
6673 00:22:58.360533 RX Vref 0 -> 0, step: 1
6674 00:22:58.360872
6675 00:22:58.363026 RX Delay -410 -> 252, step: 16
6676 00:22:58.369814 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6677 00:22:58.373012 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6678 00:22:58.376371 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6679 00:22:58.379325 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6680 00:22:58.386592 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6681 00:22:58.389870 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6682 00:22:58.392856 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6683 00:22:58.396522 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6684 00:22:58.402681 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6685 00:22:58.405798 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6686 00:22:58.409065 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6687 00:22:58.412532 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6688 00:22:58.419199 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6689 00:22:58.423294 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6690 00:22:58.426554 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6691 00:22:58.429782 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6692 00:22:58.430464 ==
6693 00:22:58.433188 Dram Type= 6, Freq= 0, CH_1, rank 1
6694 00:22:58.439628 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6695 00:22:58.440142 ==
6696 00:22:58.440477 DQS Delay:
6697 00:22:58.442434 DQS0 = 43, DQS1 = 59
6698 00:22:58.442869 DQM Delay:
6699 00:22:58.446417 DQM0 = 10, DQM1 = 18
6700 00:22:58.446926 DQ Delay:
6701 00:22:58.449087 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6702 00:22:58.452247 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6703 00:22:58.452716 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6704 00:22:58.459071 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =24
6705 00:22:58.459504
6706 00:22:58.459841
6707 00:22:58.460153 ==
6708 00:22:58.462602 Dram Type= 6, Freq= 0, CH_1, rank 1
6709 00:22:58.466057 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6710 00:22:58.466521 ==
6711 00:22:58.466860
6712 00:22:58.467172
6713 00:22:58.469185 TX Vref Scan disable
6714 00:22:58.469696 == TX Byte 0 ==
6715 00:22:58.472329 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6716 00:22:58.479279 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6717 00:22:58.479793 == TX Byte 1 ==
6718 00:22:58.482484 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6719 00:22:58.488871 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6720 00:22:58.489390 ==
6721 00:22:58.492048 Dram Type= 6, Freq= 0, CH_1, rank 1
6722 00:22:58.495365 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6723 00:22:58.495885 ==
6724 00:22:58.496228
6725 00:22:58.496538
6726 00:22:58.498646 TX Vref Scan disable
6727 00:22:58.499161 == TX Byte 0 ==
6728 00:22:58.505357 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6729 00:22:58.508231 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6730 00:22:58.508745 == TX Byte 1 ==
6731 00:22:58.515224 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6732 00:22:58.518592 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6733 00:22:58.519109
6734 00:22:58.519452 [DATLAT]
6735 00:22:58.521607 Freq=400, CH1 RK1
6736 00:22:58.522041
6737 00:22:58.522432 DATLAT Default: 0xd
6738 00:22:58.525310 0, 0xFFFF, sum = 0
6739 00:22:58.525833 1, 0xFFFF, sum = 0
6740 00:22:58.528299 2, 0xFFFF, sum = 0
6741 00:22:58.528737 3, 0xFFFF, sum = 0
6742 00:22:58.531693 4, 0xFFFF, sum = 0
6743 00:22:58.532213 5, 0xFFFF, sum = 0
6744 00:22:58.535161 6, 0xFFFF, sum = 0
6745 00:22:58.535680 7, 0xFFFF, sum = 0
6746 00:22:58.538195 8, 0xFFFF, sum = 0
6747 00:22:58.538754 9, 0xFFFF, sum = 0
6748 00:22:58.541610 10, 0xFFFF, sum = 0
6749 00:22:58.545141 11, 0xFFFF, sum = 0
6750 00:22:58.545586 12, 0x0, sum = 1
6751 00:22:58.545931 13, 0x0, sum = 2
6752 00:22:58.548078 14, 0x0, sum = 3
6753 00:22:58.548521 15, 0x0, sum = 4
6754 00:22:58.551342 best_step = 13
6755 00:22:58.551771
6756 00:22:58.552104 ==
6757 00:22:58.554570 Dram Type= 6, Freq= 0, CH_1, rank 1
6758 00:22:58.557928 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6759 00:22:58.558428 ==
6760 00:22:58.560983 RX Vref Scan: 0
6761 00:22:58.561413
6762 00:22:58.561749 RX Vref 0 -> 0, step: 1
6763 00:22:58.564477
6764 00:22:58.564908 RX Delay -359 -> 252, step: 8
6765 00:22:58.573414 iDelay=225, Bit 0, Center -36 (-279 ~ 208) 488
6766 00:22:58.576724 iDelay=225, Bit 1, Center -44 (-287 ~ 200) 488
6767 00:22:58.579888 iDelay=225, Bit 2, Center -48 (-295 ~ 200) 496
6768 00:22:58.583179 iDelay=225, Bit 3, Center -40 (-287 ~ 208) 496
6769 00:22:58.590317 iDelay=225, Bit 4, Center -40 (-287 ~ 208) 496
6770 00:22:58.593247 iDelay=225, Bit 5, Center -24 (-271 ~ 224) 496
6771 00:22:58.596319 iDelay=225, Bit 6, Center -32 (-279 ~ 216) 496
6772 00:22:58.600108 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
6773 00:22:58.606377 iDelay=225, Bit 8, Center -64 (-311 ~ 184) 496
6774 00:22:58.609693 iDelay=225, Bit 9, Center -60 (-311 ~ 192) 504
6775 00:22:58.612808 iDelay=225, Bit 10, Center -48 (-295 ~ 200) 496
6776 00:22:58.619876 iDelay=225, Bit 11, Center -56 (-303 ~ 192) 496
6777 00:22:58.623031 iDelay=225, Bit 12, Center -40 (-287 ~ 208) 496
6778 00:22:58.626022 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
6779 00:22:58.629620 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
6780 00:22:58.636065 iDelay=225, Bit 15, Center -40 (-287 ~ 208) 496
6781 00:22:58.636580 ==
6782 00:22:58.639675 Dram Type= 6, Freq= 0, CH_1, rank 1
6783 00:22:58.642972 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6784 00:22:58.643504 ==
6785 00:22:58.643966 DQS Delay:
6786 00:22:58.646010 DQS0 = 48, DQS1 = 64
6787 00:22:58.646580 DQM Delay:
6788 00:22:58.649195 DQM0 = 10, DQM1 = 15
6789 00:22:58.649626 DQ Delay:
6790 00:22:58.653023 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6791 00:22:58.656090 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6792 00:22:58.659060 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6793 00:22:58.662321 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6794 00:22:58.662759
6795 00:22:58.663097
6796 00:22:58.669698 [DQSOSCAuto] RK1, (LSB)MR18= 0xbaba, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 386 ps
6797 00:22:58.672536 CH1 RK1: MR19=C0C, MR18=BABA
6798 00:22:58.679191 CH1_RK1: MR19=0xC0C, MR18=0xBABA, DQSOSC=386, MR23=63, INC=396, DEC=264
6799 00:22:58.682795 [RxdqsGatingPostProcess] freq 400
6800 00:22:58.689232 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6801 00:22:58.692847 Pre-setting of DQS Precalculation
6802 00:22:58.695803 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6803 00:22:58.702453 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6804 00:22:58.708721 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6805 00:22:58.709309
6806 00:22:58.709681
6807 00:22:58.712520 [Calibration Summary] 800 Mbps
6808 00:22:58.715857 CH 0, Rank 0
6809 00:22:58.716371 SW Impedance : PASS
6810 00:22:58.719187 DUTY Scan : NO K
6811 00:22:58.722350 ZQ Calibration : PASS
6812 00:22:58.722871 Jitter Meter : NO K
6813 00:22:58.725881 CBT Training : PASS
6814 00:22:58.728910 Write leveling : PASS
6815 00:22:58.729430 RX DQS gating : PASS
6816 00:22:58.732543 RX DQ/DQS(RDDQC) : PASS
6817 00:22:58.735964 TX DQ/DQS : PASS
6818 00:22:58.736482 RX DATLAT : PASS
6819 00:22:58.738847 RX DQ/DQS(Engine): PASS
6820 00:22:58.739359 TX OE : NO K
6821 00:22:58.742817 All Pass.
6822 00:22:58.743351
6823 00:22:58.743696 CH 0, Rank 1
6824 00:22:58.745306 SW Impedance : PASS
6825 00:22:58.745735 DUTY Scan : NO K
6826 00:22:58.748589 ZQ Calibration : PASS
6827 00:22:58.752142 Jitter Meter : NO K
6828 00:22:58.752658 CBT Training : PASS
6829 00:22:58.754866 Write leveling : NO K
6830 00:22:58.758328 RX DQS gating : PASS
6831 00:22:58.758767 RX DQ/DQS(RDDQC) : PASS
6832 00:22:58.762366 TX DQ/DQS : PASS
6833 00:22:58.765353 RX DATLAT : PASS
6834 00:22:58.765791 RX DQ/DQS(Engine): PASS
6835 00:22:58.768302 TX OE : NO K
6836 00:22:58.768740 All Pass.
6837 00:22:58.769074
6838 00:22:58.772207 CH 1, Rank 0
6839 00:22:58.772724 SW Impedance : PASS
6840 00:22:58.775362 DUTY Scan : NO K
6841 00:22:58.778600 ZQ Calibration : PASS
6842 00:22:58.779112 Jitter Meter : NO K
6843 00:22:58.782294 CBT Training : PASS
6844 00:22:58.785169 Write leveling : PASS
6845 00:22:58.785680 RX DQS gating : PASS
6846 00:22:58.788497 RX DQ/DQS(RDDQC) : PASS
6847 00:22:58.792066 TX DQ/DQS : PASS
6848 00:22:58.792585 RX DATLAT : PASS
6849 00:22:58.794962 RX DQ/DQS(Engine): PASS
6850 00:22:58.798876 TX OE : NO K
6851 00:22:58.799392 All Pass.
6852 00:22:58.799737
6853 00:22:58.800051 CH 1, Rank 1
6854 00:22:58.802010 SW Impedance : PASS
6855 00:22:58.805204 DUTY Scan : NO K
6856 00:22:58.805717 ZQ Calibration : PASS
6857 00:22:58.807983 Jitter Meter : NO K
6858 00:22:58.808418 CBT Training : PASS
6859 00:22:58.811636 Write leveling : NO K
6860 00:22:58.814831 RX DQS gating : PASS
6861 00:22:58.815347 RX DQ/DQS(RDDQC) : PASS
6862 00:22:58.818296 TX DQ/DQS : PASS
6863 00:22:58.821694 RX DATLAT : PASS
6864 00:22:58.822129 RX DQ/DQS(Engine): PASS
6865 00:22:58.824885 TX OE : NO K
6866 00:22:58.825395 All Pass.
6867 00:22:58.825731
6868 00:22:58.828188 DramC Write-DBI off
6869 00:22:58.831647 PER_BANK_REFRESH: Hybrid Mode
6870 00:22:58.832164 TX_TRACKING: ON
6871 00:22:58.841383 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6872 00:22:58.844641 [FAST_K] Save calibration result to emmc
6873 00:22:58.848598 dramc_set_vcore_voltage set vcore to 725000
6874 00:22:58.851192 Read voltage for 1600, 0
6875 00:22:58.851627 Vio18 = 0
6876 00:22:58.851962 Vcore = 725000
6877 00:22:58.854987 Vdram = 0
6878 00:22:58.855420 Vddq = 0
6879 00:22:58.855757 Vmddr = 0
6880 00:22:58.861081 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6881 00:22:58.864618 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6882 00:22:58.868328 MEM_TYPE=3, freq_sel=13
6883 00:22:58.871285 sv_algorithm_assistance_LP4_3733
6884 00:22:58.874273 ============ PULL DRAM RESETB DOWN ============
6885 00:22:58.881359 ========== PULL DRAM RESETB DOWN end =========
6886 00:22:58.884322 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6887 00:22:58.887568 ===================================
6888 00:22:58.891023 LPDDR4 DRAM CONFIGURATION
6889 00:22:58.894532 ===================================
6890 00:22:58.894969 EX_ROW_EN[0] = 0x0
6891 00:22:58.897859 EX_ROW_EN[1] = 0x0
6892 00:22:58.898362 LP4Y_EN = 0x0
6893 00:22:58.901163 WORK_FSP = 0x1
6894 00:22:58.901632 WL = 0x5
6895 00:22:58.904099 RL = 0x5
6896 00:22:58.904534 BL = 0x2
6897 00:22:58.907521 RPST = 0x0
6898 00:22:58.907955 RD_PRE = 0x0
6899 00:22:58.911272 WR_PRE = 0x1
6900 00:22:58.911709 WR_PST = 0x1
6901 00:22:58.913927 DBI_WR = 0x0
6902 00:22:58.917661 DBI_RD = 0x0
6903 00:22:58.918052 OTF = 0x1
6904 00:22:58.920651 ===================================
6905 00:22:58.924026 ===================================
6906 00:22:58.924515 ANA top config
6907 00:22:58.927594 ===================================
6908 00:22:58.930611 DLL_ASYNC_EN = 0
6909 00:22:58.934005 ALL_SLAVE_EN = 0
6910 00:22:58.937523 NEW_RANK_MODE = 1
6911 00:22:58.940785 DLL_IDLE_MODE = 1
6912 00:22:58.941175 LP45_APHY_COMB_EN = 1
6913 00:22:58.943948 TX_ODT_DIS = 0
6914 00:22:58.947246 NEW_8X_MODE = 1
6915 00:22:58.951115 ===================================
6916 00:22:58.953967 ===================================
6917 00:22:58.957127 data_rate = 3200
6918 00:22:58.960750 CKR = 1
6919 00:22:58.961144 DQ_P2S_RATIO = 8
6920 00:22:58.963706 ===================================
6921 00:22:58.967387 CA_P2S_RATIO = 8
6922 00:22:58.970381 DQ_CA_OPEN = 0
6923 00:22:58.973659 DQ_SEMI_OPEN = 0
6924 00:22:58.977032 CA_SEMI_OPEN = 0
6925 00:22:58.980709 CA_FULL_RATE = 0
6926 00:22:58.981105 DQ_CKDIV4_EN = 0
6927 00:22:58.983965 CA_CKDIV4_EN = 0
6928 00:22:58.987250 CA_PREDIV_EN = 0
6929 00:22:58.990754 PH8_DLY = 12
6930 00:22:58.994183 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6931 00:22:58.997502 DQ_AAMCK_DIV = 4
6932 00:22:58.997988 CA_AAMCK_DIV = 4
6933 00:22:59.001368 CA_ADMCK_DIV = 4
6934 00:22:59.004501 DQ_TRACK_CA_EN = 0
6935 00:22:59.007172 CA_PICK = 1600
6936 00:22:59.010500 CA_MCKIO = 1600
6937 00:22:59.013843 MCKIO_SEMI = 0
6938 00:22:59.017236 PLL_FREQ = 3068
6939 00:22:59.017884 DQ_UI_PI_RATIO = 32
6940 00:22:59.020557 CA_UI_PI_RATIO = 0
6941 00:22:59.023392 ===================================
6942 00:22:59.027103 ===================================
6943 00:22:59.030267 memory_type:LPDDR4
6944 00:22:59.033513 GP_NUM : 10
6945 00:22:59.033904 SRAM_EN : 1
6946 00:22:59.036885 MD32_EN : 0
6947 00:22:59.040198 ===================================
6948 00:22:59.044213 [ANA_INIT] >>>>>>>>>>>>>>
6949 00:22:59.044882 <<<<<< [CONFIGURE PHASE]: ANA_TX
6950 00:22:59.050397 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6951 00:22:59.050885 ===================================
6952 00:22:59.054009 data_rate = 3200,PCW = 0X7600
6953 00:22:59.057335 ===================================
6954 00:22:59.060584 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6955 00:22:59.066534 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6956 00:22:59.073637 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6957 00:22:59.076798 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6958 00:22:59.080210 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6959 00:22:59.083030 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6960 00:22:59.086407 [ANA_INIT] flow start
6961 00:22:59.086805 [ANA_INIT] PLL >>>>>>>>
6962 00:22:59.089695 [ANA_INIT] PLL <<<<<<<<
6963 00:22:59.093606 [ANA_INIT] MIDPI >>>>>>>>
6964 00:22:59.096936 [ANA_INIT] MIDPI <<<<<<<<
6965 00:22:59.097329 [ANA_INIT] DLL >>>>>>>>
6966 00:22:59.100098 [ANA_INIT] DLL <<<<<<<<
6967 00:22:59.100499 [ANA_INIT] flow end
6968 00:22:59.106688 ============ LP4 DIFF to SE enter ============
6969 00:22:59.110178 ============ LP4 DIFF to SE exit ============
6970 00:22:59.113139 [ANA_INIT] <<<<<<<<<<<<<
6971 00:22:59.116608 [Flow] Enable top DCM control >>>>>
6972 00:22:59.119777 [Flow] Enable top DCM control <<<<<
6973 00:22:59.120172 Enable DLL master slave shuffle
6974 00:22:59.126840 ==============================================================
6975 00:22:59.129611 Gating Mode config
6976 00:22:59.133161 ==============================================================
6977 00:22:59.136641 Config description:
6978 00:22:59.146554 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6979 00:22:59.153104 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6980 00:22:59.156822 SELPH_MODE 0: By rank 1: By Phase
6981 00:22:59.163171 ==============================================================
6982 00:22:59.166102 GAT_TRACK_EN = 1
6983 00:22:59.169598 RX_GATING_MODE = 2
6984 00:22:59.172606 RX_GATING_TRACK_MODE = 2
6985 00:22:59.176485 SELPH_MODE = 1
6986 00:22:59.179139 PICG_EARLY_EN = 1
6987 00:22:59.182685 VALID_LAT_VALUE = 1
6988 00:22:59.185798 ==============================================================
6989 00:22:59.189141 Enter into Gating configuration >>>>
6990 00:22:59.192713 Exit from Gating configuration <<<<
6991 00:22:59.196106 Enter into DVFS_PRE_config >>>>>
6992 00:22:59.205939 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6993 00:22:59.209167 Exit from DVFS_PRE_config <<<<<
6994 00:22:59.212481 Enter into PICG configuration >>>>
6995 00:22:59.215524 Exit from PICG configuration <<<<
6996 00:22:59.219082 [RX_INPUT] configuration >>>>>
6997 00:22:59.222586 [RX_INPUT] configuration <<<<<
6998 00:22:59.229225 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6999 00:22:59.232670 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7000 00:22:59.239019 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7001 00:22:59.245577 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7002 00:22:59.251756 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7003 00:22:59.258671 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7004 00:22:59.262053 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7005 00:22:59.265478 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7006 00:22:59.268752 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7007 00:22:59.275074 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7008 00:22:59.278380 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7009 00:22:59.282376 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7010 00:22:59.285345 ===================================
7011 00:22:59.288506 LPDDR4 DRAM CONFIGURATION
7012 00:22:59.291710 ===================================
7013 00:22:59.295354 EX_ROW_EN[0] = 0x0
7014 00:22:59.295862 EX_ROW_EN[1] = 0x0
7015 00:22:59.298179 LP4Y_EN = 0x0
7016 00:22:59.298641 WORK_FSP = 0x1
7017 00:22:59.301644 WL = 0x5
7018 00:22:59.302179 RL = 0x5
7019 00:22:59.305116 BL = 0x2
7020 00:22:59.305628 RPST = 0x0
7021 00:22:59.308152 RD_PRE = 0x0
7022 00:22:59.308585 WR_PRE = 0x1
7023 00:22:59.311346 WR_PST = 0x1
7024 00:22:59.311779 DBI_WR = 0x0
7025 00:22:59.314466 DBI_RD = 0x0
7026 00:22:59.314901 OTF = 0x1
7027 00:22:59.317866 ===================================
7028 00:22:59.324797 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7029 00:22:59.327731 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7030 00:22:59.331014 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7031 00:22:59.334413 ===================================
7032 00:22:59.337818 LPDDR4 DRAM CONFIGURATION
7033 00:22:59.341199 ===================================
7034 00:22:59.344300 EX_ROW_EN[0] = 0x10
7035 00:22:59.344738 EX_ROW_EN[1] = 0x0
7036 00:22:59.347451 LP4Y_EN = 0x0
7037 00:22:59.347888 WORK_FSP = 0x1
7038 00:22:59.351160 WL = 0x5
7039 00:22:59.351592 RL = 0x5
7040 00:22:59.353872 BL = 0x2
7041 00:22:59.354350 RPST = 0x0
7042 00:22:59.357303 RD_PRE = 0x0
7043 00:22:59.357733 WR_PRE = 0x1
7044 00:22:59.360728 WR_PST = 0x1
7045 00:22:59.361164 DBI_WR = 0x0
7046 00:22:59.363935 DBI_RD = 0x0
7047 00:22:59.364368 OTF = 0x1
7048 00:22:59.367392 ===================================
7049 00:22:59.374709 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7050 00:22:59.375224 ==
7051 00:22:59.377632 Dram Type= 6, Freq= 0, CH_0, rank 0
7052 00:22:59.384057 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7053 00:22:59.384562 ==
7054 00:22:59.384906 [Duty_Offset_Calibration]
7055 00:22:59.387335 B0:0 B1:2 CA:1
7056 00:22:59.387768
7057 00:22:59.390949 [DutyScan_Calibration_Flow] k_type=0
7058 00:22:59.400101
7059 00:22:59.400610 ==CLK 0==
7060 00:22:59.403155 Final CLK duty delay cell = 0
7061 00:22:59.407202 [0] MAX Duty = 5156%(X100), DQS PI = 22
7062 00:22:59.410303 [0] MIN Duty = 4938%(X100), DQS PI = 52
7063 00:22:59.410824 [0] AVG Duty = 5047%(X100)
7064 00:22:59.413124
7065 00:22:59.416748 CH0 CLK Duty spec in!! Max-Min= 218%
7066 00:22:59.420243 [DutyScan_Calibration_Flow] ====Done====
7067 00:22:59.420857
7068 00:22:59.423190 [DutyScan_Calibration_Flow] k_type=1
7069 00:22:59.440198
7070 00:22:59.440711 ==DQS 0 ==
7071 00:22:59.443136 Final DQS duty delay cell = 0
7072 00:22:59.446442 [0] MAX Duty = 5125%(X100), DQS PI = 2
7073 00:22:59.449646 [0] MIN Duty = 5031%(X100), DQS PI = 8
7074 00:22:59.453003 [0] AVG Duty = 5078%(X100)
7075 00:22:59.453502
7076 00:22:59.453847 ==DQS 1 ==
7077 00:22:59.456897 Final DQS duty delay cell = 0
7078 00:22:59.459756 [0] MAX Duty = 5031%(X100), DQS PI = 46
7079 00:22:59.463520 [0] MIN Duty = 4876%(X100), DQS PI = 16
7080 00:22:59.467205 [0] AVG Duty = 4953%(X100)
7081 00:22:59.467719
7082 00:22:59.469503 CH0 DQS 0 Duty spec in!! Max-Min= 94%
7083 00:22:59.469936
7084 00:22:59.473242 CH0 DQS 1 Duty spec in!! Max-Min= 155%
7085 00:22:59.476685 [DutyScan_Calibration_Flow] ====Done====
7086 00:22:59.477199
7087 00:22:59.480175 [DutyScan_Calibration_Flow] k_type=3
7088 00:22:59.497164
7089 00:22:59.497678 ==DQM 0 ==
7090 00:22:59.500365 Final DQM duty delay cell = 0
7091 00:22:59.503772 [0] MAX Duty = 5187%(X100), DQS PI = 24
7092 00:22:59.507089 [0] MIN Duty = 4907%(X100), DQS PI = 42
7093 00:22:59.510504 [0] AVG Duty = 5047%(X100)
7094 00:22:59.511032
7095 00:22:59.511374 ==DQM 1 ==
7096 00:22:59.513839 Final DQM duty delay cell = 0
7097 00:22:59.516855 [0] MAX Duty = 5031%(X100), DQS PI = 52
7098 00:22:59.520209 [0] MIN Duty = 4782%(X100), DQS PI = 14
7099 00:22:59.523547 [0] AVG Duty = 4906%(X100)
7100 00:22:59.524066
7101 00:22:59.526465 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7102 00:22:59.526901
7103 00:22:59.530137 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7104 00:22:59.533198 [DutyScan_Calibration_Flow] ====Done====
7105 00:22:59.533632
7106 00:22:59.536626 [DutyScan_Calibration_Flow] k_type=2
7107 00:22:59.553881
7108 00:22:59.554431 ==DQ 0 ==
7109 00:22:59.556696 Final DQ duty delay cell = 0
7110 00:22:59.560506 [0] MAX Duty = 5218%(X100), DQS PI = 18
7111 00:22:59.563524 [0] MIN Duty = 4938%(X100), DQS PI = 56
7112 00:22:59.564041 [0] AVG Duty = 5078%(X100)
7113 00:22:59.566801
7114 00:22:59.567309 ==DQ 1 ==
7115 00:22:59.569869 Final DQ duty delay cell = -4
7116 00:22:59.573276 [-4] MAX Duty = 5062%(X100), DQS PI = 4
7117 00:22:59.576663 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7118 00:22:59.580316 [-4] AVG Duty = 4953%(X100)
7119 00:22:59.580828
7120 00:22:59.583135 CH0 DQ 0 Duty spec in!! Max-Min= 280%
7121 00:22:59.583576
7122 00:22:59.587000 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7123 00:22:59.589989 [DutyScan_Calibration_Flow] ====Done====
7124 00:22:59.590456 ==
7125 00:22:59.592957 Dram Type= 6, Freq= 0, CH_1, rank 0
7126 00:22:59.597131 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7127 00:22:59.597665 ==
7128 00:22:59.599569 [Duty_Offset_Calibration]
7129 00:22:59.600005 B0:0 B1:5 CA:-5
7130 00:22:59.600341
7131 00:22:59.603774 [DutyScan_Calibration_Flow] k_type=0
7132 00:22:59.613992
7133 00:22:59.614549 ==CLK 0==
7134 00:22:59.617099 Final CLK duty delay cell = 0
7135 00:22:59.620656 [0] MAX Duty = 5156%(X100), DQS PI = 20
7136 00:22:59.624207 [0] MIN Duty = 4906%(X100), DQS PI = 50
7137 00:22:59.624721 [0] AVG Duty = 5031%(X100)
7138 00:22:59.627563
7139 00:22:59.630856 CH1 CLK Duty spec in!! Max-Min= 250%
7140 00:22:59.634207 [DutyScan_Calibration_Flow] ====Done====
7141 00:22:59.634895
7142 00:22:59.637594 [DutyScan_Calibration_Flow] k_type=1
7143 00:22:59.652893
7144 00:22:59.653426 ==DQS 0 ==
7145 00:22:59.656645 Final DQS duty delay cell = 0
7146 00:22:59.659520 [0] MAX Duty = 5156%(X100), DQS PI = 18
7147 00:22:59.662799 [0] MIN Duty = 4876%(X100), DQS PI = 42
7148 00:22:59.666443 [0] AVG Duty = 5016%(X100)
7149 00:22:59.666880
7150 00:22:59.667217 ==DQS 1 ==
7151 00:22:59.669373 Final DQS duty delay cell = -4
7152 00:22:59.673015 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7153 00:22:59.676368 [-4] MIN Duty = 4844%(X100), DQS PI = 38
7154 00:22:59.679598 [-4] AVG Duty = 4922%(X100)
7155 00:22:59.680116
7156 00:22:59.682508 CH1 DQS 0 Duty spec in!! Max-Min= 280%
7157 00:22:59.682947
7158 00:22:59.685761 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7159 00:22:59.689054 [DutyScan_Calibration_Flow] ====Done====
7160 00:22:59.689489
7161 00:22:59.693059 [DutyScan_Calibration_Flow] k_type=3
7162 00:22:59.708625
7163 00:22:59.709189 ==DQM 0 ==
7164 00:22:59.711863 Final DQM duty delay cell = -4
7165 00:22:59.715253 [-4] MAX Duty = 5093%(X100), DQS PI = 34
7166 00:22:59.718640 [-4] MIN Duty = 4782%(X100), DQS PI = 46
7167 00:22:59.722044 [-4] AVG Duty = 4937%(X100)
7168 00:22:59.722512
7169 00:22:59.722853 ==DQM 1 ==
7170 00:22:59.725172 Final DQM duty delay cell = -4
7171 00:22:59.728573 [-4] MAX Duty = 5031%(X100), DQS PI = 2
7172 00:22:59.731468 [-4] MIN Duty = 4907%(X100), DQS PI = 32
7173 00:22:59.734978 [-4] AVG Duty = 4969%(X100)
7174 00:22:59.735412
7175 00:22:59.738384 CH1 DQM 0 Duty spec in!! Max-Min= 311%
7176 00:22:59.738817
7177 00:22:59.741851 CH1 DQM 1 Duty spec in!! Max-Min= 124%
7178 00:22:59.745272 [DutyScan_Calibration_Flow] ====Done====
7179 00:22:59.745834
7180 00:22:59.748708 [DutyScan_Calibration_Flow] k_type=2
7181 00:22:59.766164
7182 00:22:59.766767 ==DQ 0 ==
7183 00:22:59.769282 Final DQ duty delay cell = 0
7184 00:22:59.773090 [0] MAX Duty = 5093%(X100), DQS PI = 34
7185 00:22:59.776008 [0] MIN Duty = 4938%(X100), DQS PI = 46
7186 00:22:59.776444 [0] AVG Duty = 5015%(X100)
7187 00:22:59.776786
7188 00:22:59.779684 ==DQ 1 ==
7189 00:22:59.783041 Final DQ duty delay cell = 0
7190 00:22:59.786365 [0] MAX Duty = 5062%(X100), DQS PI = 6
7191 00:22:59.789381 [0] MIN Duty = 4907%(X100), DQS PI = 14
7192 00:22:59.789817 [0] AVG Duty = 4984%(X100)
7193 00:22:59.790153
7194 00:22:59.792485 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7195 00:22:59.796125
7196 00:22:59.800093 CH1 DQ 1 Duty spec in!! Max-Min= 155%
7197 00:22:59.802797 [DutyScan_Calibration_Flow] ====Done====
7198 00:22:59.806587 nWR fixed to 30
7199 00:22:59.807137 [ModeRegInit_LP4] CH0 RK0
7200 00:22:59.809369 [ModeRegInit_LP4] CH0 RK1
7201 00:22:59.812546 [ModeRegInit_LP4] CH1 RK0
7202 00:22:59.815898 [ModeRegInit_LP4] CH1 RK1
7203 00:22:59.816332 match AC timing 4
7204 00:22:59.819049 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7205 00:22:59.825578 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7206 00:22:59.829382 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7207 00:22:59.835726 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7208 00:22:59.839447 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7209 00:22:59.839965 [MiockJmeterHQA]
7210 00:22:59.840307
7211 00:22:59.842453 [DramcMiockJmeter] u1RxGatingPI = 0
7212 00:22:59.846132 0 : 4252, 4027
7213 00:22:59.846691 4 : 4363, 4137
7214 00:22:59.847038 8 : 4253, 4026
7215 00:22:59.849199 12 : 4252, 4027
7216 00:22:59.849748 16 : 4252, 4027
7217 00:22:59.852378 20 : 4255, 4029
7218 00:22:59.852817 24 : 4253, 4026
7219 00:22:59.855653 28 : 4253, 4027
7220 00:22:59.856092 32 : 4366, 4139
7221 00:22:59.858605 36 : 4255, 4029
7222 00:22:59.859138 40 : 4254, 4029
7223 00:22:59.859485 44 : 4252, 4027
7224 00:22:59.862370 48 : 4255, 4029
7225 00:22:59.862820 52 : 4254, 4029
7226 00:22:59.865439 56 : 4360, 4137
7227 00:22:59.865884 60 : 4250, 4027
7228 00:22:59.868647 64 : 4250, 4027
7229 00:22:59.869114 68 : 4250, 4027
7230 00:22:59.872449 72 : 4252, 4029
7231 00:22:59.872997 76 : 4250, 4026
7232 00:22:59.873351 80 : 4250, 4027
7233 00:22:59.875388 84 : 4363, 4140
7234 00:22:59.875916 88 : 4250, 4027
7235 00:22:59.878805 92 : 4252, 4029
7236 00:22:59.879250 96 : 4250, 4026
7237 00:22:59.882373 100 : 4363, 1927
7238 00:22:59.882891 104 : 4250, 0
7239 00:22:59.885802 108 : 4252, 0
7240 00:22:59.886380 112 : 4250, 0
7241 00:22:59.886736 116 : 4252, 0
7242 00:22:59.888841 120 : 4361, 0
7243 00:22:59.889285 124 : 4360, 0
7244 00:22:59.889634 128 : 4254, 0
7245 00:22:59.892083 132 : 4250, 0
7246 00:22:59.892527 136 : 4361, 0
7247 00:22:59.895420 140 : 4361, 0
7248 00:22:59.895954 144 : 4249, 0
7249 00:22:59.896402 148 : 4361, 0
7250 00:22:59.898602 152 : 4250, 0
7251 00:22:59.899051 156 : 4250, 0
7252 00:22:59.902109 160 : 4250, 0
7253 00:22:59.902697 164 : 4250, 0
7254 00:22:59.903146 168 : 4252, 0
7255 00:22:59.904912 172 : 4360, 0
7256 00:22:59.905362 176 : 4250, 0
7257 00:22:59.908513 180 : 4250, 0
7258 00:22:59.908966 184 : 4361, 0
7259 00:22:59.909455 188 : 4361, 0
7260 00:22:59.911560 192 : 4363, 0
7261 00:22:59.912012 196 : 4250, 0
7262 00:22:59.915533 200 : 4250, 0
7263 00:22:59.915984 204 : 4250, 0
7264 00:22:59.916424 208 : 4250, 0
7265 00:22:59.918630 212 : 4250, 0
7266 00:22:59.919079 216 : 4250, 0
7267 00:22:59.921467 220 : 4252, 475
7268 00:22:59.921918 224 : 4250, 3992
7269 00:22:59.922483 228 : 4250, 4027
7270 00:22:59.924935 232 : 4250, 4026
7271 00:22:59.925384 236 : 4250, 4027
7272 00:22:59.928497 240 : 4250, 4026
7273 00:22:59.928940 244 : 4250, 4027
7274 00:22:59.931545 248 : 4250, 4027
7275 00:22:59.931995 252 : 4252, 4029
7276 00:22:59.935282 256 : 4250, 4027
7277 00:22:59.935844 260 : 4361, 4137
7278 00:22:59.938018 264 : 4361, 4138
7279 00:22:59.938508 268 : 4250, 4027
7280 00:22:59.941865 272 : 4363, 4140
7281 00:22:59.942434 276 : 4250, 4026
7282 00:22:59.945099 280 : 4250, 4027
7283 00:22:59.945620 284 : 4252, 4030
7284 00:22:59.945967 288 : 4252, 4029
7285 00:22:59.948774 292 : 4250, 4026
7286 00:22:59.949323 296 : 4253, 4029
7287 00:22:59.951720 300 : 4250, 4027
7288 00:22:59.952164 304 : 4252, 4029
7289 00:22:59.955051 308 : 4250, 4026
7290 00:22:59.955539 312 : 4361, 4137
7291 00:22:59.958537 316 : 4360, 4138
7292 00:22:59.959075 320 : 4250, 4027
7293 00:22:59.961146 324 : 4363, 4140
7294 00:22:59.961588 328 : 4250, 4026
7295 00:22:59.964903 332 : 4250, 4027
7296 00:22:59.965436 336 : 4249, 3904
7297 00:22:59.968328 340 : 4252, 1729
7298 00:22:59.968856
7299 00:22:59.969230 MIOCK jitter meter ch=0
7300 00:22:59.969550
7301 00:22:59.971557 1T = (340-100) = 240 dly cells
7302 00:22:59.977512 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 271/100 ps
7303 00:22:59.977924 ==
7304 00:22:59.981056 Dram Type= 6, Freq= 0, CH_0, rank 0
7305 00:22:59.984230 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7306 00:22:59.984751 ==
7307 00:22:59.990994 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7308 00:22:59.994458 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7309 00:22:59.997639 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7310 00:23:00.003925 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7311 00:23:00.013081 [CA 0] Center 41 (11~72) winsize 62
7312 00:23:00.016805 [CA 1] Center 41 (11~72) winsize 62
7313 00:23:00.019690 [CA 2] Center 37 (7~68) winsize 62
7314 00:23:00.023417 [CA 3] Center 37 (7~67) winsize 61
7315 00:23:00.026759 [CA 4] Center 35 (5~66) winsize 62
7316 00:23:00.030016 [CA 5] Center 35 (5~65) winsize 61
7317 00:23:00.030501
7318 00:23:00.033181 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7319 00:23:00.033625
7320 00:23:00.036707 [CATrainingPosCal] consider 1 rank data
7321 00:23:00.040276 u2DelayCellTimex100 = 271/100 ps
7322 00:23:00.043217 CA0 delay=41 (11~72),Diff = 6 PI (21 cell)
7323 00:23:00.049659 CA1 delay=41 (11~72),Diff = 6 PI (21 cell)
7324 00:23:00.053066 CA2 delay=37 (7~68),Diff = 2 PI (7 cell)
7325 00:23:00.056287 CA3 delay=37 (7~67),Diff = 2 PI (7 cell)
7326 00:23:00.059825 CA4 delay=35 (5~66),Diff = 0 PI (0 cell)
7327 00:23:00.063107 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7328 00:23:00.063544
7329 00:23:00.066831 CA PerBit enable=1, Macro0, CA PI delay=35
7330 00:23:00.067270
7331 00:23:00.069365 [CBTSetCACLKResult] CA Dly = 35
7332 00:23:00.073094 CS Dly: 11 (0~42)
7333 00:23:00.076305 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7334 00:23:00.079383 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7335 00:23:00.079797 ==
7336 00:23:00.082680 Dram Type= 6, Freq= 0, CH_0, rank 1
7337 00:23:00.086049 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7338 00:23:00.089388 ==
7339 00:23:00.092495 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7340 00:23:00.096102 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7341 00:23:00.102903 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7342 00:23:00.106543 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7343 00:23:00.115674 [CA 0] Center 42 (12~73) winsize 62
7344 00:23:00.119078 [CA 1] Center 42 (12~73) winsize 62
7345 00:23:00.122719 [CA 2] Center 38 (9~68) winsize 60
7346 00:23:00.125678 [CA 3] Center 38 (9~67) winsize 59
7347 00:23:00.129567 [CA 4] Center 36 (6~66) winsize 61
7348 00:23:00.132493 [CA 5] Center 36 (6~66) winsize 61
7349 00:23:00.132889
7350 00:23:00.135747 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7351 00:23:00.136139
7352 00:23:00.139003 [CATrainingPosCal] consider 2 rank data
7353 00:23:00.142435 u2DelayCellTimex100 = 271/100 ps
7354 00:23:00.145916 CA0 delay=42 (12~72),Diff = 7 PI (25 cell)
7355 00:23:00.152361 CA1 delay=42 (12~72),Diff = 7 PI (25 cell)
7356 00:23:00.155591 CA2 delay=38 (9~68),Diff = 3 PI (10 cell)
7357 00:23:00.158838 CA3 delay=38 (9~67),Diff = 3 PI (10 cell)
7358 00:23:00.162176 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7359 00:23:00.165986 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7360 00:23:00.166423
7361 00:23:00.169380 CA PerBit enable=1, Macro0, CA PI delay=35
7362 00:23:00.169849
7363 00:23:00.172296 [CBTSetCACLKResult] CA Dly = 35
7364 00:23:00.175736 CS Dly: 11 (0~42)
7365 00:23:00.178858 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7366 00:23:00.182137 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7367 00:23:00.182582
7368 00:23:00.185812 ----->DramcWriteLeveling(PI) begin...
7369 00:23:00.186395 ==
7370 00:23:00.188945 Dram Type= 6, Freq= 0, CH_0, rank 0
7371 00:23:00.195458 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7372 00:23:00.195883 ==
7373 00:23:00.198642 Write leveling (Byte 0): 27 => 27
7374 00:23:00.199033 Write leveling (Byte 1): 25 => 25
7375 00:23:00.201824 DramcWriteLeveling(PI) end<-----
7376 00:23:00.202272
7377 00:23:00.205300 ==
7378 00:23:00.205684 Dram Type= 6, Freq= 0, CH_0, rank 0
7379 00:23:00.211969 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7380 00:23:00.212360 ==
7381 00:23:00.215207 [Gating] SW mode calibration
7382 00:23:00.221923 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7383 00:23:00.225417 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7384 00:23:00.231524 0 12 0 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7385 00:23:00.235162 0 12 4 | B1->B0 | 2423 3434 | 1 0 | (0 0) (0 0)
7386 00:23:00.238303 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7387 00:23:00.245215 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7388 00:23:00.248207 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7389 00:23:00.251635 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7390 00:23:00.258426 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7391 00:23:00.261602 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7392 00:23:00.265683 0 13 0 | B1->B0 | 3434 2d2d | 1 1 | (1 0) (1 0)
7393 00:23:00.271352 0 13 4 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (1 0)
7394 00:23:00.274642 0 13 8 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
7395 00:23:00.278037 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7396 00:23:00.284667 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7397 00:23:00.288545 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7398 00:23:00.291147 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7399 00:23:00.297511 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7400 00:23:00.300954 0 14 0 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
7401 00:23:00.304370 0 14 4 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
7402 00:23:00.311027 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7403 00:23:00.314411 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7404 00:23:00.317890 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7405 00:23:00.324611 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7406 00:23:00.327888 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7407 00:23:00.330893 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7408 00:23:00.337683 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7409 00:23:00.341006 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7410 00:23:00.344170 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7411 00:23:00.350848 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7412 00:23:00.354199 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7413 00:23:00.357963 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7414 00:23:00.364163 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7415 00:23:00.367339 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7416 00:23:00.370566 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7417 00:23:00.377267 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7418 00:23:00.380699 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7419 00:23:00.384067 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7420 00:23:00.390400 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7421 00:23:00.393822 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7422 00:23:00.397251 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7423 00:23:00.403881 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7424 00:23:00.407353 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7425 00:23:00.410915 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7426 00:23:00.413582 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7427 00:23:00.417691 Total UI for P1: 0, mck2ui 16
7428 00:23:00.420200 best dqsien dly found for B0: ( 1, 1, 0)
7429 00:23:00.423395 Total UI for P1: 0, mck2ui 16
7430 00:23:00.426897 best dqsien dly found for B1: ( 1, 1, 2)
7431 00:23:00.430298 best DQS0 dly(MCK, UI, PI) = (1, 1, 0)
7432 00:23:00.433455 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
7433 00:23:00.436862
7434 00:23:00.440143 best DQS0 P1 dly(MCK, UI, PI) = (1, 5, 0)
7435 00:23:00.443557 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
7436 00:23:00.446656 [Gating] SW calibration Done
7437 00:23:00.447093 ==
7438 00:23:00.449873 Dram Type= 6, Freq= 0, CH_0, rank 0
7439 00:23:00.453225 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7440 00:23:00.453664 ==
7441 00:23:00.454068 RX Vref Scan: 0
7442 00:23:00.454579
7443 00:23:00.456592 RX Vref 0 -> 0, step: 1
7444 00:23:00.457024
7445 00:23:00.460528 RX Delay 0 -> 252, step: 8
7446 00:23:00.463274 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
7447 00:23:00.466996 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7448 00:23:00.469980 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7449 00:23:00.477283 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7450 00:23:00.480239 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7451 00:23:00.483688 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7452 00:23:00.486280 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7453 00:23:00.489921 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7454 00:23:00.496692 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
7455 00:23:00.499878 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7456 00:23:00.503193 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7457 00:23:00.506679 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7458 00:23:00.513179 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7459 00:23:00.516482 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7460 00:23:00.519726 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7461 00:23:00.523554 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7462 00:23:00.524010 ==
7463 00:23:00.526091 Dram Type= 6, Freq= 0, CH_0, rank 0
7464 00:23:00.532854 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7465 00:23:00.533295 ==
7466 00:23:00.533634 DQS Delay:
7467 00:23:00.533946 DQS0 = 0, DQS1 = 0
7468 00:23:00.536004 DQM Delay:
7469 00:23:00.536434 DQM0 = 131, DQM1 = 124
7470 00:23:00.539395 DQ Delay:
7471 00:23:00.542676 DQ0 =131, DQ1 =131, DQ2 =127, DQ3 =127
7472 00:23:00.545983 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7473 00:23:00.549153 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
7474 00:23:00.552505 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7475 00:23:00.552731
7476 00:23:00.552907
7477 00:23:00.553066 ==
7478 00:23:00.555879 Dram Type= 6, Freq= 0, CH_0, rank 0
7479 00:23:00.559481 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7480 00:23:00.562421 ==
7481 00:23:00.562712
7482 00:23:00.562901
7483 00:23:00.563064 TX Vref Scan disable
7484 00:23:00.565896 == TX Byte 0 ==
7485 00:23:00.569415 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7486 00:23:00.572664 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7487 00:23:00.576106 == TX Byte 1 ==
7488 00:23:00.579557 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
7489 00:23:00.582421 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
7490 00:23:00.582783 ==
7491 00:23:00.585744 Dram Type= 6, Freq= 0, CH_0, rank 0
7492 00:23:00.592530 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7493 00:23:00.592898 ==
7494 00:23:00.604105
7495 00:23:00.607551 TX Vref early break, caculate TX vref
7496 00:23:00.611127 TX Vref=16, minBit 8, minWin=22, winSum=375
7497 00:23:00.614347 TX Vref=18, minBit 9, minWin=22, winSum=379
7498 00:23:00.617616 TX Vref=20, minBit 8, minWin=23, winSum=391
7499 00:23:00.620985 TX Vref=22, minBit 9, minWin=23, winSum=397
7500 00:23:00.624526 TX Vref=24, minBit 8, minWin=24, winSum=405
7501 00:23:00.631099 TX Vref=26, minBit 8, minWin=25, winSum=415
7502 00:23:00.634453 TX Vref=28, minBit 0, minWin=25, winSum=419
7503 00:23:00.637879 TX Vref=30, minBit 1, minWin=25, winSum=412
7504 00:23:00.641091 TX Vref=32, minBit 8, minWin=24, winSum=404
7505 00:23:00.644182 TX Vref=34, minBit 8, minWin=23, winSum=394
7506 00:23:00.651020 [TxChooseVref] Worse bit 0, Min win 25, Win sum 419, Final Vref 28
7507 00:23:00.651464
7508 00:23:00.654023 Final TX Range 0 Vref 28
7509 00:23:00.654565
7510 00:23:00.655079 ==
7511 00:23:00.657122 Dram Type= 6, Freq= 0, CH_0, rank 0
7512 00:23:00.660540 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7513 00:23:00.660981 ==
7514 00:23:00.661508
7515 00:23:00.661837
7516 00:23:00.663847 TX Vref Scan disable
7517 00:23:00.670298 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7518 00:23:00.670741 == TX Byte 0 ==
7519 00:23:00.673554 u2DelayCellOfst[0]=10 cells (3 PI)
7520 00:23:00.677330 u2DelayCellOfst[1]=18 cells (5 PI)
7521 00:23:00.680792 u2DelayCellOfst[2]=14 cells (4 PI)
7522 00:23:00.683967 u2DelayCellOfst[3]=10 cells (3 PI)
7523 00:23:00.687008 u2DelayCellOfst[4]=7 cells (2 PI)
7524 00:23:00.690835 u2DelayCellOfst[5]=0 cells (0 PI)
7525 00:23:00.694056 u2DelayCellOfst[6]=18 cells (5 PI)
7526 00:23:00.697250 u2DelayCellOfst[7]=18 cells (5 PI)
7527 00:23:00.700348 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7528 00:23:00.704027 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7529 00:23:00.707047 == TX Byte 1 ==
7530 00:23:00.707409 u2DelayCellOfst[8]=3 cells (1 PI)
7531 00:23:00.710137 u2DelayCellOfst[9]=0 cells (0 PI)
7532 00:23:00.713747 u2DelayCellOfst[10]=10 cells (3 PI)
7533 00:23:00.717150 u2DelayCellOfst[11]=3 cells (1 PI)
7534 00:23:00.720222 u2DelayCellOfst[12]=14 cells (4 PI)
7535 00:23:00.723614 u2DelayCellOfst[13]=18 cells (5 PI)
7536 00:23:00.726888 u2DelayCellOfst[14]=18 cells (5 PI)
7537 00:23:00.729994 u2DelayCellOfst[15]=14 cells (4 PI)
7538 00:23:00.733222 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
7539 00:23:00.739975 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
7540 00:23:00.740313 DramC Write-DBI on
7541 00:23:00.740519 ==
7542 00:23:00.743335 Dram Type= 6, Freq= 0, CH_0, rank 0
7543 00:23:00.749908 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7544 00:23:00.750271 ==
7545 00:23:00.750500
7546 00:23:00.750700
7547 00:23:00.750881 TX Vref Scan disable
7548 00:23:00.753287 == TX Byte 0 ==
7549 00:23:00.757101 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
7550 00:23:00.760315 == TX Byte 1 ==
7551 00:23:00.763556 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
7552 00:23:00.767499 DramC Write-DBI off
7553 00:23:00.767882
7554 00:23:00.768151 [DATLAT]
7555 00:23:00.768403 Freq=1600, CH0 RK0
7556 00:23:00.768640
7557 00:23:00.770387 DATLAT Default: 0xf
7558 00:23:00.773800 0, 0xFFFF, sum = 0
7559 00:23:00.774374 1, 0xFFFF, sum = 0
7560 00:23:00.776722 2, 0xFFFF, sum = 0
7561 00:23:00.777309 3, 0xFFFF, sum = 0
7562 00:23:00.780156 4, 0xFFFF, sum = 0
7563 00:23:00.780860 5, 0xFFFF, sum = 0
7564 00:23:00.783794 6, 0xFFFF, sum = 0
7565 00:23:00.784353 7, 0xFFFF, sum = 0
7566 00:23:00.786671 8, 0xFFFF, sum = 0
7567 00:23:00.787323 9, 0xFFFF, sum = 0
7568 00:23:00.789933 10, 0xFFFF, sum = 0
7569 00:23:00.790587 11, 0xFFFF, sum = 0
7570 00:23:00.793579 12, 0xFFF, sum = 0
7571 00:23:00.794256 13, 0x0, sum = 1
7572 00:23:00.796419 14, 0x0, sum = 2
7573 00:23:00.797015 15, 0x0, sum = 3
7574 00:23:00.799808 16, 0x0, sum = 4
7575 00:23:00.800395 best_step = 14
7576 00:23:00.800887
7577 00:23:00.801355 ==
7578 00:23:00.803181 Dram Type= 6, Freq= 0, CH_0, rank 0
7579 00:23:00.809483 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7580 00:23:00.809925 ==
7581 00:23:00.810318 RX Vref Scan: 1
7582 00:23:00.810660
7583 00:23:00.812799 Set Vref Range= 24 -> 127
7584 00:23:00.813192
7585 00:23:00.816611 RX Vref 24 -> 127, step: 1
7586 00:23:00.817093
7587 00:23:00.817405 RX Delay 11 -> 252, step: 4
7588 00:23:00.817689
7589 00:23:00.819654 Set Vref, RX VrefLevel [Byte0]: 24
7590 00:23:00.822798 [Byte1]: 24
7591 00:23:00.827091
7592 00:23:00.827586 Set Vref, RX VrefLevel [Byte0]: 25
7593 00:23:00.830505 [Byte1]: 25
7594 00:23:00.834447
7595 00:23:00.834842 Set Vref, RX VrefLevel [Byte0]: 26
7596 00:23:00.838540 [Byte1]: 26
7597 00:23:00.842288
7598 00:23:00.843031 Set Vref, RX VrefLevel [Byte0]: 27
7599 00:23:00.845794 [Byte1]: 27
7600 00:23:00.850049
7601 00:23:00.850593 Set Vref, RX VrefLevel [Byte0]: 28
7602 00:23:00.852984 [Byte1]: 28
7603 00:23:00.857256
7604 00:23:00.857728 Set Vref, RX VrefLevel [Byte0]: 29
7605 00:23:00.861063 [Byte1]: 29
7606 00:23:00.865201
7607 00:23:00.865589 Set Vref, RX VrefLevel [Byte0]: 30
7608 00:23:00.868468 [Byte1]: 30
7609 00:23:00.872702
7610 00:23:00.872929 Set Vref, RX VrefLevel [Byte0]: 31
7611 00:23:00.875804 [Byte1]: 31
7612 00:23:00.880093
7613 00:23:00.880301 Set Vref, RX VrefLevel [Byte0]: 32
7614 00:23:00.884037 [Byte1]: 32
7615 00:23:00.887619
7616 00:23:00.887827 Set Vref, RX VrefLevel [Byte0]: 33
7617 00:23:00.891141 [Byte1]: 33
7618 00:23:00.895489
7619 00:23:00.898886 Set Vref, RX VrefLevel [Byte0]: 34
7620 00:23:00.901923 [Byte1]: 34
7621 00:23:00.902205
7622 00:23:00.905210 Set Vref, RX VrefLevel [Byte0]: 35
7623 00:23:00.908627 [Byte1]: 35
7624 00:23:00.909012
7625 00:23:00.912003 Set Vref, RX VrefLevel [Byte0]: 36
7626 00:23:00.915937 [Byte1]: 36
7627 00:23:00.918692
7628 00:23:00.919138 Set Vref, RX VrefLevel [Byte0]: 37
7629 00:23:00.921458 [Byte1]: 37
7630 00:23:00.925917
7631 00:23:00.926405 Set Vref, RX VrefLevel [Byte0]: 38
7632 00:23:00.929384 [Byte1]: 38
7633 00:23:00.933636
7634 00:23:00.934038 Set Vref, RX VrefLevel [Byte0]: 39
7635 00:23:00.936800 [Byte1]: 39
7636 00:23:00.940928
7637 00:23:00.941215 Set Vref, RX VrefLevel [Byte0]: 40
7638 00:23:00.944409 [Byte1]: 40
7639 00:23:00.949028
7640 00:23:00.949401 Set Vref, RX VrefLevel [Byte0]: 41
7641 00:23:00.952004 [Byte1]: 41
7642 00:23:00.956389
7643 00:23:00.956677 Set Vref, RX VrefLevel [Byte0]: 42
7644 00:23:00.959970 [Byte1]: 42
7645 00:23:00.963745
7646 00:23:00.964178 Set Vref, RX VrefLevel [Byte0]: 43
7647 00:23:00.967095 [Byte1]: 43
7648 00:23:00.971996
7649 00:23:00.972457 Set Vref, RX VrefLevel [Byte0]: 44
7650 00:23:00.974997 [Byte1]: 44
7651 00:23:00.979358
7652 00:23:00.979821 Set Vref, RX VrefLevel [Byte0]: 45
7653 00:23:00.982304 [Byte1]: 45
7654 00:23:00.986859
7655 00:23:00.987301 Set Vref, RX VrefLevel [Byte0]: 46
7656 00:23:00.990144 [Byte1]: 46
7657 00:23:00.994490
7658 00:23:00.994950 Set Vref, RX VrefLevel [Byte0]: 47
7659 00:23:00.997779 [Byte1]: 47
7660 00:23:01.001820
7661 00:23:01.002245 Set Vref, RX VrefLevel [Byte0]: 48
7662 00:23:01.005071 [Byte1]: 48
7663 00:23:01.009919
7664 00:23:01.010134 Set Vref, RX VrefLevel [Byte0]: 49
7665 00:23:01.012921 [Byte1]: 49
7666 00:23:01.017524
7667 00:23:01.017815 Set Vref, RX VrefLevel [Byte0]: 50
7668 00:23:01.020487 [Byte1]: 50
7669 00:23:01.025179
7670 00:23:01.025592 Set Vref, RX VrefLevel [Byte0]: 51
7671 00:23:01.028596 [Byte1]: 51
7672 00:23:01.032595
7673 00:23:01.033121 Set Vref, RX VrefLevel [Byte0]: 52
7674 00:23:01.035710 [Byte1]: 52
7675 00:23:01.040292
7676 00:23:01.040816 Set Vref, RX VrefLevel [Byte0]: 53
7677 00:23:01.043956 [Byte1]: 53
7678 00:23:01.048395
7679 00:23:01.048948 Set Vref, RX VrefLevel [Byte0]: 54
7680 00:23:01.050914 [Byte1]: 54
7681 00:23:01.055200
7682 00:23:01.055642 Set Vref, RX VrefLevel [Byte0]: 55
7683 00:23:01.058457 [Byte1]: 55
7684 00:23:01.063096
7685 00:23:01.063538 Set Vref, RX VrefLevel [Byte0]: 56
7686 00:23:01.065991 [Byte1]: 56
7687 00:23:01.070522
7688 00:23:01.070968 Set Vref, RX VrefLevel [Byte0]: 57
7689 00:23:01.074126 [Byte1]: 57
7690 00:23:01.077962
7691 00:23:01.078295 Set Vref, RX VrefLevel [Byte0]: 58
7692 00:23:01.081235 [Byte1]: 58
7693 00:23:01.085567
7694 00:23:01.085852 Set Vref, RX VrefLevel [Byte0]: 59
7695 00:23:01.088647 [Byte1]: 59
7696 00:23:01.093554
7697 00:23:01.093840 Set Vref, RX VrefLevel [Byte0]: 60
7698 00:23:01.096514 [Byte1]: 60
7699 00:23:01.100558
7700 00:23:01.100843 Set Vref, RX VrefLevel [Byte0]: 61
7701 00:23:01.104247 [Byte1]: 61
7702 00:23:01.108497
7703 00:23:01.108796 Set Vref, RX VrefLevel [Byte0]: 62
7704 00:23:01.111573 [Byte1]: 62
7705 00:23:01.116233
7706 00:23:01.116570 Set Vref, RX VrefLevel [Byte0]: 63
7707 00:23:01.119629 [Byte1]: 63
7708 00:23:01.123764
7709 00:23:01.124181 Set Vref, RX VrefLevel [Byte0]: 64
7710 00:23:01.127245 [Byte1]: 64
7711 00:23:01.131393
7712 00:23:01.131797 Set Vref, RX VrefLevel [Byte0]: 65
7713 00:23:01.134740 [Byte1]: 65
7714 00:23:01.139199
7715 00:23:01.139605 Set Vref, RX VrefLevel [Byte0]: 66
7716 00:23:01.142277 [Byte1]: 66
7717 00:23:01.146853
7718 00:23:01.147211 Set Vref, RX VrefLevel [Byte0]: 67
7719 00:23:01.149860 [Byte1]: 67
7720 00:23:01.154206
7721 00:23:01.154432 Set Vref, RX VrefLevel [Byte0]: 68
7722 00:23:01.157564 [Byte1]: 68
7723 00:23:01.161846
7724 00:23:01.162136 Set Vref, RX VrefLevel [Byte0]: 69
7725 00:23:01.164900 [Byte1]: 69
7726 00:23:01.169902
7727 00:23:01.170190 Set Vref, RX VrefLevel [Byte0]: 70
7728 00:23:01.172559 [Byte1]: 70
7729 00:23:01.177371
7730 00:23:01.177583 Set Vref, RX VrefLevel [Byte0]: 71
7731 00:23:01.180555 [Byte1]: 71
7732 00:23:01.184745
7733 00:23:01.185116 Set Vref, RX VrefLevel [Byte0]: 72
7734 00:23:01.188362 [Byte1]: 72
7735 00:23:01.192352
7736 00:23:01.192706 Set Vref, RX VrefLevel [Byte0]: 73
7737 00:23:01.195508 [Byte1]: 73
7738 00:23:01.199770
7739 00:23:01.200106 Final RX Vref Byte 0 = 54 to rank0
7740 00:23:01.203046 Final RX Vref Byte 1 = 55 to rank0
7741 00:23:01.206684 Final RX Vref Byte 0 = 54 to rank1
7742 00:23:01.209332 Final RX Vref Byte 1 = 55 to rank1==
7743 00:23:01.212895 Dram Type= 6, Freq= 0, CH_0, rank 0
7744 00:23:01.219703 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7745 00:23:01.219952 ==
7746 00:23:01.220142 DQS Delay:
7747 00:23:01.223043 DQS0 = 0, DQS1 = 0
7748 00:23:01.223285 DQM Delay:
7749 00:23:01.223474 DQM0 = 126, DQM1 = 121
7750 00:23:01.226491 DQ Delay:
7751 00:23:01.230035 DQ0 =122, DQ1 =128, DQ2 =124, DQ3 =122
7752 00:23:01.233003 DQ4 =130, DQ5 =116, DQ6 =138, DQ7 =134
7753 00:23:01.236312 DQ8 =112, DQ9 =104, DQ10 =120, DQ11 =112
7754 00:23:01.239889 DQ12 =126, DQ13 =126, DQ14 =136, DQ15 =134
7755 00:23:01.240213
7756 00:23:01.240412
7757 00:23:01.240591
7758 00:23:01.243237 [DramC_TX_OE_Calibration] TA2
7759 00:23:01.246346 Original DQ_B0 (3 6) =30, OEN = 27
7760 00:23:01.249726 Original DQ_B1 (3 6) =30, OEN = 27
7761 00:23:01.253147 24, 0x0, End_B0=24 End_B1=24
7762 00:23:01.253519 25, 0x0, End_B0=25 End_B1=25
7763 00:23:01.256222 26, 0x0, End_B0=26 End_B1=26
7764 00:23:01.259209 27, 0x0, End_B0=27 End_B1=27
7765 00:23:01.262884 28, 0x0, End_B0=28 End_B1=28
7766 00:23:01.265883 29, 0x0, End_B0=29 End_B1=29
7767 00:23:01.266208 30, 0x0, End_B0=30 End_B1=30
7768 00:23:01.269063 31, 0x4141, End_B0=30 End_B1=30
7769 00:23:01.272773 Byte0 end_step=30 best_step=27
7770 00:23:01.275973 Byte1 end_step=30 best_step=27
7771 00:23:01.279458 Byte0 TX OE(2T, 0.5T) = (3, 3)
7772 00:23:01.282694 Byte1 TX OE(2T, 0.5T) = (3, 3)
7773 00:23:01.283052
7774 00:23:01.283255
7775 00:23:01.289042 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d1d, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
7776 00:23:01.292904 CH0 RK0: MR19=303, MR18=1D1D
7777 00:23:01.299597 CH0_RK0: MR19=0x303, MR18=0x1D1D, DQSOSC=395, MR23=63, INC=23, DEC=15
7778 00:23:01.299991
7779 00:23:01.302695 ----->DramcWriteLeveling(PI) begin...
7780 00:23:01.303202 ==
7781 00:23:01.305816 Dram Type= 6, Freq= 0, CH_0, rank 1
7782 00:23:01.309305 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7783 00:23:01.309742 ==
7784 00:23:01.312621 Write leveling (Byte 0): 29 => 29
7785 00:23:01.315944 Write leveling (Byte 1): 26 => 26
7786 00:23:01.319548 DramcWriteLeveling(PI) end<-----
7787 00:23:01.320106
7788 00:23:01.320597 ==
7789 00:23:01.322801 Dram Type= 6, Freq= 0, CH_0, rank 1
7790 00:23:01.326567 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7791 00:23:01.327129 ==
7792 00:23:01.329693 [Gating] SW mode calibration
7793 00:23:01.335897 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7794 00:23:01.342386 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7795 00:23:01.345567 0 12 0 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
7796 00:23:01.352196 0 12 4 | B1->B0 | 2828 3434 | 1 1 | (0 0) (1 1)
7797 00:23:01.355669 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7798 00:23:01.358906 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7799 00:23:01.362497 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7800 00:23:01.368971 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7801 00:23:01.372063 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7802 00:23:01.375464 0 12 28 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
7803 00:23:01.382052 0 13 0 | B1->B0 | 3434 2a2a | 1 1 | (1 0) (1 0)
7804 00:23:01.385094 0 13 4 | B1->B0 | 2f2f 2323 | 0 0 | (1 0) (0 0)
7805 00:23:01.388460 0 13 8 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
7806 00:23:01.396089 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7807 00:23:01.398428 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7808 00:23:01.401919 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7809 00:23:01.408464 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7810 00:23:01.411951 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7811 00:23:01.415822 0 14 0 | B1->B0 | 2323 3e3e | 0 1 | (0 0) (0 0)
7812 00:23:01.422153 0 14 4 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
7813 00:23:01.425753 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7814 00:23:01.428717 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7815 00:23:01.435146 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7816 00:23:01.438705 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7817 00:23:01.442742 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7818 00:23:01.448588 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7819 00:23:01.451995 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7820 00:23:01.455613 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7821 00:23:01.462084 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7822 00:23:01.465158 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7823 00:23:01.468501 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7824 00:23:01.474974 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7825 00:23:01.478553 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7826 00:23:01.481730 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7827 00:23:01.488051 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7828 00:23:01.491412 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7829 00:23:01.495234 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7830 00:23:01.501690 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7831 00:23:01.504962 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7832 00:23:01.508069 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7833 00:23:01.515181 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7834 00:23:01.517894 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7835 00:23:01.521366 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7836 00:23:01.524857 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7837 00:23:01.527939 Total UI for P1: 0, mck2ui 16
7838 00:23:01.530990 best dqsien dly found for B0: ( 1, 0, 28)
7839 00:23:01.537807 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7840 00:23:01.541018 Total UI for P1: 0, mck2ui 16
7841 00:23:01.544979 best dqsien dly found for B1: ( 1, 1, 4)
7842 00:23:01.547770 best DQS0 dly(MCK, UI, PI) = (1, 0, 28)
7843 00:23:01.551311 best DQS1 dly(MCK, UI, PI) = (1, 1, 4)
7844 00:23:01.551461
7845 00:23:01.554449 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 28)
7846 00:23:01.557836 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4)
7847 00:23:01.561206 [Gating] SW calibration Done
7848 00:23:01.561366 ==
7849 00:23:01.564850 Dram Type= 6, Freq= 0, CH_0, rank 1
7850 00:23:01.568092 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7851 00:23:01.568277 ==
7852 00:23:01.571533 RX Vref Scan: 0
7853 00:23:01.571677
7854 00:23:01.571773 RX Vref 0 -> 0, step: 1
7855 00:23:01.574262
7856 00:23:01.574423 RX Delay 0 -> 252, step: 8
7857 00:23:01.578040 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7858 00:23:01.584467 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7859 00:23:01.588179 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7860 00:23:01.591032 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7861 00:23:01.594446 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7862 00:23:01.597578 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7863 00:23:01.604157 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7864 00:23:01.607663 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
7865 00:23:01.610995 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7866 00:23:01.614036 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7867 00:23:01.617659 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7868 00:23:01.624303 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7869 00:23:01.628118 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7870 00:23:01.630761 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7871 00:23:01.634257 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7872 00:23:01.641438 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7873 00:23:01.641957 ==
7874 00:23:01.644601 Dram Type= 6, Freq= 0, CH_0, rank 1
7875 00:23:01.647890 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7876 00:23:01.648401 ==
7877 00:23:01.648747 DQS Delay:
7878 00:23:01.651088 DQS0 = 0, DQS1 = 0
7879 00:23:01.651524 DQM Delay:
7880 00:23:01.654249 DQM0 = 131, DQM1 = 124
7881 00:23:01.654925 DQ Delay:
7882 00:23:01.657447 DQ0 =127, DQ1 =131, DQ2 =131, DQ3 =127
7883 00:23:01.661071 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =143
7884 00:23:01.664114 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =119
7885 00:23:01.668235 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =131
7886 00:23:01.668672
7887 00:23:01.669009
7888 00:23:01.671094 ==
7889 00:23:01.674621 Dram Type= 6, Freq= 0, CH_0, rank 1
7890 00:23:01.677865 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7891 00:23:01.678451 ==
7892 00:23:01.678804
7893 00:23:01.679118
7894 00:23:01.680774 TX Vref Scan disable
7895 00:23:01.681209 == TX Byte 0 ==
7896 00:23:01.684371 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7897 00:23:01.690947 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7898 00:23:01.691387 == TX Byte 1 ==
7899 00:23:01.694235 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7900 00:23:01.700696 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7901 00:23:01.701216 ==
7902 00:23:01.704389 Dram Type= 6, Freq= 0, CH_0, rank 1
7903 00:23:01.707505 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7904 00:23:01.707949 ==
7905 00:23:01.722061
7906 00:23:01.725015 TX Vref early break, caculate TX vref
7907 00:23:01.728421 TX Vref=16, minBit 9, minWin=21, winSum=370
7908 00:23:01.731216 TX Vref=18, minBit 8, minWin=22, winSum=375
7909 00:23:01.734711 TX Vref=20, minBit 9, minWin=23, winSum=390
7910 00:23:01.738320 TX Vref=22, minBit 1, minWin=23, winSum=394
7911 00:23:01.741251 TX Vref=24, minBit 8, minWin=24, winSum=405
7912 00:23:01.748149 TX Vref=26, minBit 8, minWin=24, winSum=411
7913 00:23:01.751374 TX Vref=28, minBit 8, minWin=24, winSum=413
7914 00:23:01.754558 TX Vref=30, minBit 1, minWin=25, winSum=411
7915 00:23:01.757870 TX Vref=32, minBit 7, minWin=24, winSum=407
7916 00:23:01.761207 TX Vref=34, minBit 8, minWin=23, winSum=394
7917 00:23:01.764615 TX Vref=36, minBit 8, minWin=22, winSum=391
7918 00:23:01.771134 [TxChooseVref] Worse bit 1, Min win 25, Win sum 411, Final Vref 30
7919 00:23:01.771576
7920 00:23:01.774430 Final TX Range 0 Vref 30
7921 00:23:01.774872
7922 00:23:01.775208 ==
7923 00:23:01.777749 Dram Type= 6, Freq= 0, CH_0, rank 1
7924 00:23:01.781389 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7925 00:23:01.781835 ==
7926 00:23:01.782177
7927 00:23:01.784518
7928 00:23:01.784949 TX Vref Scan disable
7929 00:23:01.791037 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7930 00:23:01.791511 == TX Byte 0 ==
7931 00:23:01.794683 u2DelayCellOfst[0]=10 cells (3 PI)
7932 00:23:01.797661 u2DelayCellOfst[1]=18 cells (5 PI)
7933 00:23:01.801948 u2DelayCellOfst[2]=10 cells (3 PI)
7934 00:23:01.805117 u2DelayCellOfst[3]=10 cells (3 PI)
7935 00:23:01.808004 u2DelayCellOfst[4]=10 cells (3 PI)
7936 00:23:01.811364 u2DelayCellOfst[5]=0 cells (0 PI)
7937 00:23:01.814580 u2DelayCellOfst[6]=21 cells (6 PI)
7938 00:23:01.818011 u2DelayCellOfst[7]=18 cells (5 PI)
7939 00:23:01.821532 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7940 00:23:01.824842 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7941 00:23:01.827524 == TX Byte 1 ==
7942 00:23:01.831205 u2DelayCellOfst[8]=0 cells (0 PI)
7943 00:23:01.834362 u2DelayCellOfst[9]=0 cells (0 PI)
7944 00:23:01.837890 u2DelayCellOfst[10]=10 cells (3 PI)
7945 00:23:01.838467 u2DelayCellOfst[11]=3 cells (1 PI)
7946 00:23:01.841062 u2DelayCellOfst[12]=14 cells (4 PI)
7947 00:23:01.844258 u2DelayCellOfst[13]=14 cells (4 PI)
7948 00:23:01.847451 u2DelayCellOfst[14]=14 cells (4 PI)
7949 00:23:01.850924 u2DelayCellOfst[15]=14 cells (4 PI)
7950 00:23:01.857703 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
7951 00:23:01.860925 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7952 00:23:01.861381 DramC Write-DBI on
7953 00:23:01.864262 ==
7954 00:23:01.864714 Dram Type= 6, Freq= 0, CH_0, rank 1
7955 00:23:01.870550 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7956 00:23:01.870990 ==
7957 00:23:01.871327
7958 00:23:01.871638
7959 00:23:01.874258 TX Vref Scan disable
7960 00:23:01.874697 == TX Byte 0 ==
7961 00:23:01.880469 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7962 00:23:01.880909 == TX Byte 1 ==
7963 00:23:01.883988 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
7964 00:23:01.887273 DramC Write-DBI off
7965 00:23:01.887797
7966 00:23:01.888138 [DATLAT]
7967 00:23:01.890590 Freq=1600, CH0 RK1
7968 00:23:01.891137
7969 00:23:01.891643 DATLAT Default: 0xe
7970 00:23:01.893917 0, 0xFFFF, sum = 0
7971 00:23:01.894419 1, 0xFFFF, sum = 0
7972 00:23:01.897454 2, 0xFFFF, sum = 0
7973 00:23:01.897980 3, 0xFFFF, sum = 0
7974 00:23:01.900615 4, 0xFFFF, sum = 0
7975 00:23:01.901147 5, 0xFFFF, sum = 0
7976 00:23:01.904115 6, 0xFFFF, sum = 0
7977 00:23:01.904650 7, 0xFFFF, sum = 0
7978 00:23:01.907761 8, 0xFFFF, sum = 0
7979 00:23:01.910575 9, 0xFFFF, sum = 0
7980 00:23:01.911019 10, 0xFFFF, sum = 0
7981 00:23:01.913945 11, 0xFFFF, sum = 0
7982 00:23:01.914420 12, 0x8FFF, sum = 0
7983 00:23:01.916968 13, 0x0, sum = 1
7984 00:23:01.917510 14, 0x0, sum = 2
7985 00:23:01.919962 15, 0x0, sum = 3
7986 00:23:01.920406 16, 0x0, sum = 4
7987 00:23:01.920753 best_step = 14
7988 00:23:01.923203
7989 00:23:01.923638 ==
7990 00:23:01.926737 Dram Type= 6, Freq= 0, CH_0, rank 1
7991 00:23:01.930855 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7992 00:23:01.931373 ==
7993 00:23:01.931734 RX Vref Scan: 0
7994 00:23:01.932061
7995 00:23:01.933302 RX Vref 0 -> 0, step: 1
7996 00:23:01.933741
7997 00:23:01.937025 RX Delay 11 -> 252, step: 4
7998 00:23:01.940543 iDelay=195, Bit 0, Center 122 (67 ~ 178) 112
7999 00:23:01.943426 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
8000 00:23:01.950472 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
8001 00:23:01.953943 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8002 00:23:01.956964 iDelay=195, Bit 4, Center 132 (79 ~ 186) 108
8003 00:23:01.960223 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8004 00:23:01.963308 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8005 00:23:01.969811 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
8006 00:23:01.973389 iDelay=195, Bit 8, Center 108 (55 ~ 162) 108
8007 00:23:01.976809 iDelay=195, Bit 9, Center 106 (51 ~ 162) 112
8008 00:23:01.979922 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
8009 00:23:01.983412 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
8010 00:23:01.990286 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
8011 00:23:01.993445 iDelay=195, Bit 13, Center 128 (75 ~ 182) 108
8012 00:23:01.996654 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
8013 00:23:02.000224 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8014 00:23:02.000753 ==
8015 00:23:02.003047 Dram Type= 6, Freq= 0, CH_0, rank 1
8016 00:23:02.010099 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8017 00:23:02.010655 ==
8018 00:23:02.011002 DQS Delay:
8019 00:23:02.012961 DQS0 = 0, DQS1 = 0
8020 00:23:02.013434 DQM Delay:
8021 00:23:02.016971 DQM0 = 128, DQM1 = 120
8022 00:23:02.017410 DQ Delay:
8023 00:23:02.020224 DQ0 =122, DQ1 =130, DQ2 =126, DQ3 =124
8024 00:23:02.023139 DQ4 =132, DQ5 =120, DQ6 =138, DQ7 =138
8025 00:23:02.026361 DQ8 =108, DQ9 =106, DQ10 =122, DQ11 =112
8026 00:23:02.029706 DQ12 =126, DQ13 =128, DQ14 =132, DQ15 =132
8027 00:23:02.030144
8028 00:23:02.030521
8029 00:23:02.030837
8030 00:23:02.033063 [DramC_TX_OE_Calibration] TA2
8031 00:23:02.036797 Original DQ_B0 (3 6) =30, OEN = 27
8032 00:23:02.039793 Original DQ_B1 (3 6) =30, OEN = 27
8033 00:23:02.043270 24, 0x0, End_B0=24 End_B1=24
8034 00:23:02.046824 25, 0x0, End_B0=25 End_B1=25
8035 00:23:02.047348 26, 0x0, End_B0=26 End_B1=26
8036 00:23:02.049870 27, 0x0, End_B0=27 End_B1=27
8037 00:23:02.053120 28, 0x0, End_B0=28 End_B1=28
8038 00:23:02.056528 29, 0x0, End_B0=29 End_B1=29
8039 00:23:02.056979 30, 0x0, End_B0=30 End_B1=30
8040 00:23:02.059557 31, 0x4141, End_B0=30 End_B1=30
8041 00:23:02.063534 Byte0 end_step=30 best_step=27
8042 00:23:02.066267 Byte1 end_step=30 best_step=27
8043 00:23:02.069597 Byte0 TX OE(2T, 0.5T) = (3, 3)
8044 00:23:02.072877 Byte1 TX OE(2T, 0.5T) = (3, 3)
8045 00:23:02.073427
8046 00:23:02.073770
8047 00:23:02.079568 [DQSOSCAuto] RK1, (LSB)MR18= 0x2424, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
8048 00:23:02.082967 CH0 RK1: MR19=303, MR18=2424
8049 00:23:02.089780 CH0_RK1: MR19=0x303, MR18=0x2424, DQSOSC=391, MR23=63, INC=24, DEC=16
8050 00:23:02.092739 [RxdqsGatingPostProcess] freq 1600
8051 00:23:02.096729 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8052 00:23:02.099834 Pre-setting of DQS Precalculation
8053 00:23:02.106186 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8054 00:23:02.106744 ==
8055 00:23:02.109112 Dram Type= 6, Freq= 0, CH_1, rank 0
8056 00:23:02.112558 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8057 00:23:02.113097 ==
8058 00:23:02.119112 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8059 00:23:02.122722 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8060 00:23:02.125871 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8061 00:23:02.132989 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8062 00:23:02.141556 [CA 0] Center 41 (11~71) winsize 61
8063 00:23:02.144316 [CA 1] Center 40 (10~70) winsize 61
8064 00:23:02.147937 [CA 2] Center 36 (7~66) winsize 60
8065 00:23:02.151142 [CA 3] Center 35 (6~65) winsize 60
8066 00:23:02.154253 [CA 4] Center 33 (4~63) winsize 60
8067 00:23:02.157738 [CA 5] Center 33 (4~63) winsize 60
8068 00:23:02.158302
8069 00:23:02.160934 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8070 00:23:02.161366
8071 00:23:02.167236 [CATrainingPosCal] consider 1 rank data
8072 00:23:02.167669 u2DelayCellTimex100 = 271/100 ps
8073 00:23:02.174132 CA0 delay=41 (11~71),Diff = 8 PI (28 cell)
8074 00:23:02.177464 CA1 delay=40 (10~70),Diff = 7 PI (25 cell)
8075 00:23:02.180701 CA2 delay=36 (7~66),Diff = 3 PI (10 cell)
8076 00:23:02.183927 CA3 delay=35 (6~65),Diff = 2 PI (7 cell)
8077 00:23:02.187791 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
8078 00:23:02.190402 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
8079 00:23:02.190849
8080 00:23:02.193692 CA PerBit enable=1, Macro0, CA PI delay=33
8081 00:23:02.194122
8082 00:23:02.197488 [CBTSetCACLKResult] CA Dly = 33
8083 00:23:02.201107 CS Dly: 8 (0~39)
8084 00:23:02.203849 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8085 00:23:02.207439 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8086 00:23:02.207959 ==
8087 00:23:02.210425 Dram Type= 6, Freq= 0, CH_1, rank 1
8088 00:23:02.217051 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8089 00:23:02.217558 ==
8090 00:23:02.220416 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8091 00:23:02.223671 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8092 00:23:02.230851 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8093 00:23:02.237108 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8094 00:23:02.243661 [CA 0] Center 40 (10~70) winsize 61
8095 00:23:02.246993 [CA 1] Center 39 (9~70) winsize 62
8096 00:23:02.249933 [CA 2] Center 35 (6~65) winsize 60
8097 00:23:02.253495 [CA 3] Center 35 (6~65) winsize 60
8098 00:23:02.256816 [CA 4] Center 33 (4~63) winsize 60
8099 00:23:02.259597 [CA 5] Center 33 (3~63) winsize 61
8100 00:23:02.260036
8101 00:23:02.262915 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8102 00:23:02.263343
8103 00:23:02.266449 [CATrainingPosCal] consider 2 rank data
8104 00:23:02.270037 u2DelayCellTimex100 = 271/100 ps
8105 00:23:02.276613 CA0 delay=40 (11~70),Diff = 7 PI (25 cell)
8106 00:23:02.279949 CA1 delay=40 (10~70),Diff = 7 PI (25 cell)
8107 00:23:02.282990 CA2 delay=36 (7~65),Diff = 3 PI (10 cell)
8108 00:23:02.286387 CA3 delay=35 (6~65),Diff = 2 PI (7 cell)
8109 00:23:02.289605 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
8110 00:23:02.292760 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
8111 00:23:02.293190
8112 00:23:02.296311 CA PerBit enable=1, Macro0, CA PI delay=33
8113 00:23:02.296740
8114 00:23:02.299549 [CBTSetCACLKResult] CA Dly = 33
8115 00:23:02.302668 CS Dly: 9 (0~41)
8116 00:23:02.306125 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8117 00:23:02.310283 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8118 00:23:02.310801
8119 00:23:02.313746 ----->DramcWriteLeveling(PI) begin...
8120 00:23:02.314307 ==
8121 00:23:02.316133 Dram Type= 6, Freq= 0, CH_1, rank 0
8122 00:23:02.322800 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8123 00:23:02.323322 ==
8124 00:23:02.325916 Write leveling (Byte 0): 21 => 21
8125 00:23:02.326387 Write leveling (Byte 1): 20 => 20
8126 00:23:02.329750 DramcWriteLeveling(PI) end<-----
8127 00:23:02.330317
8128 00:23:02.332442 ==
8129 00:23:02.332875 Dram Type= 6, Freq= 0, CH_1, rank 0
8130 00:23:02.339780 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8131 00:23:02.340300 ==
8132 00:23:02.342555 [Gating] SW mode calibration
8133 00:23:02.349300 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8134 00:23:02.352821 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8135 00:23:02.359798 0 12 0 | B1->B0 | 302f 3434 | 1 1 | (0 0) (1 1)
8136 00:23:02.362543 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8137 00:23:02.366305 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8138 00:23:02.372756 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8139 00:23:02.376216 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8140 00:23:02.379455 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8141 00:23:02.385844 0 12 24 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
8142 00:23:02.389205 0 12 28 | B1->B0 | 3434 2727 | 1 1 | (1 1) (1 0)
8143 00:23:02.392521 0 13 0 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (1 0)
8144 00:23:02.399310 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8145 00:23:02.402394 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8146 00:23:02.406059 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8147 00:23:02.412261 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8148 00:23:02.416017 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8149 00:23:02.419343 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8150 00:23:02.425997 0 13 28 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
8151 00:23:02.429401 0 14 0 | B1->B0 | 3f3f 4646 | 0 0 | (1 1) (0 0)
8152 00:23:02.432445 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8153 00:23:02.435553 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8154 00:23:02.442397 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8155 00:23:02.445281 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8156 00:23:02.448899 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8157 00:23:02.455622 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8158 00:23:02.458557 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8159 00:23:02.462078 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8160 00:23:02.468681 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8161 00:23:02.472287 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8162 00:23:02.475190 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8163 00:23:02.482393 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8164 00:23:02.485866 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8165 00:23:02.488412 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8166 00:23:02.494946 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8167 00:23:02.499225 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8168 00:23:02.501550 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8169 00:23:02.508708 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8170 00:23:02.511481 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8171 00:23:02.514776 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8172 00:23:02.521514 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8173 00:23:02.524704 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8174 00:23:02.528716 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8175 00:23:02.534859 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8176 00:23:02.538551 Total UI for P1: 0, mck2ui 16
8177 00:23:02.541185 best dqsien dly found for B0: ( 1, 0, 26)
8178 00:23:02.544486 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8179 00:23:02.547900 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8180 00:23:02.551511 Total UI for P1: 0, mck2ui 16
8181 00:23:02.554719 best dqsien dly found for B1: ( 1, 1, 0)
8182 00:23:02.557965 best DQS0 dly(MCK, UI, PI) = (1, 0, 26)
8183 00:23:02.561317 best DQS1 dly(MCK, UI, PI) = (1, 1, 0)
8184 00:23:02.561933
8185 00:23:02.567881 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 26)
8186 00:23:02.570993 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 0)
8187 00:23:02.571715 [Gating] SW calibration Done
8188 00:23:02.574525 ==
8189 00:23:02.577679 Dram Type= 6, Freq= 0, CH_1, rank 0
8190 00:23:02.581321 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8191 00:23:02.581754 ==
8192 00:23:02.582070 RX Vref Scan: 0
8193 00:23:02.582412
8194 00:23:02.584236 RX Vref 0 -> 0, step: 1
8195 00:23:02.584632
8196 00:23:02.587635 RX Delay 0 -> 252, step: 8
8197 00:23:02.590740 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8198 00:23:02.594371 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8199 00:23:02.597609 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8200 00:23:02.604479 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8201 00:23:02.607876 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8202 00:23:02.611184 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8203 00:23:02.614329 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8204 00:23:02.617492 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8205 00:23:02.623955 iDelay=200, Bit 8, Center 103 (48 ~ 159) 112
8206 00:23:02.627422 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8207 00:23:02.631103 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8208 00:23:02.634003 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8209 00:23:02.637795 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8210 00:23:02.644581 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8211 00:23:02.647875 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8212 00:23:02.650713 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8213 00:23:02.651213 ==
8214 00:23:02.654020 Dram Type= 6, Freq= 0, CH_1, rank 0
8215 00:23:02.657281 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8216 00:23:02.660563 ==
8217 00:23:02.660953 DQS Delay:
8218 00:23:02.661379 DQS0 = 0, DQS1 = 0
8219 00:23:02.664347 DQM Delay:
8220 00:23:02.664782 DQM0 = 130, DQM1 = 125
8221 00:23:02.667600 DQ Delay:
8222 00:23:02.670770 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8223 00:23:02.674269 DQ4 =127, DQ5 =139, DQ6 =135, DQ7 =127
8224 00:23:02.677842 DQ8 =103, DQ9 =115, DQ10 =127, DQ11 =115
8225 00:23:02.680633 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8226 00:23:02.681067
8227 00:23:02.681408
8228 00:23:02.681797 ==
8229 00:23:02.684051 Dram Type= 6, Freq= 0, CH_1, rank 0
8230 00:23:02.687451 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8231 00:23:02.687973 ==
8232 00:23:02.690658
8233 00:23:02.691086
8234 00:23:02.691421 TX Vref Scan disable
8235 00:23:02.693975 == TX Byte 0 ==
8236 00:23:02.697818 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8237 00:23:02.700643 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8238 00:23:02.703804 == TX Byte 1 ==
8239 00:23:02.707290 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8240 00:23:02.710454 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8241 00:23:02.710940 ==
8242 00:23:02.713804 Dram Type= 6, Freq= 0, CH_1, rank 0
8243 00:23:02.720135 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8244 00:23:02.720653 ==
8245 00:23:02.731879
8246 00:23:02.735195 TX Vref early break, caculate TX vref
8247 00:23:02.738263 TX Vref=16, minBit 0, minWin=21, winSum=372
8248 00:23:02.741612 TX Vref=18, minBit 1, minWin=22, winSum=379
8249 00:23:02.744691 TX Vref=20, minBit 3, minWin=22, winSum=391
8250 00:23:02.748291 TX Vref=22, minBit 3, minWin=23, winSum=396
8251 00:23:02.751662 TX Vref=24, minBit 1, minWin=24, winSum=404
8252 00:23:02.758024 TX Vref=26, minBit 1, minWin=24, winSum=414
8253 00:23:02.761280 TX Vref=28, minBit 3, minWin=24, winSum=417
8254 00:23:02.764549 TX Vref=30, minBit 3, minWin=23, winSum=411
8255 00:23:02.767854 TX Vref=32, minBit 1, minWin=24, winSum=399
8256 00:23:02.771436 TX Vref=34, minBit 3, minWin=23, winSum=395
8257 00:23:02.778382 [TxChooseVref] Worse bit 3, Min win 24, Win sum 417, Final Vref 28
8258 00:23:02.779007
8259 00:23:02.781476 Final TX Range 0 Vref 28
8260 00:23:02.781986
8261 00:23:02.782376 ==
8262 00:23:02.785620 Dram Type= 6, Freq= 0, CH_1, rank 0
8263 00:23:02.788816 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8264 00:23:02.789332 ==
8265 00:23:02.789672
8266 00:23:02.789980
8267 00:23:02.791478 TX Vref Scan disable
8268 00:23:02.797857 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8269 00:23:02.798350 == TX Byte 0 ==
8270 00:23:02.801362 u2DelayCellOfst[0]=18 cells (5 PI)
8271 00:23:02.805173 u2DelayCellOfst[1]=10 cells (3 PI)
8272 00:23:02.808011 u2DelayCellOfst[2]=0 cells (0 PI)
8273 00:23:02.811016 u2DelayCellOfst[3]=7 cells (2 PI)
8274 00:23:02.814790 u2DelayCellOfst[4]=7 cells (2 PI)
8275 00:23:02.818156 u2DelayCellOfst[5]=18 cells (5 PI)
8276 00:23:02.818619 u2DelayCellOfst[6]=18 cells (5 PI)
8277 00:23:02.821434 u2DelayCellOfst[7]=7 cells (2 PI)
8278 00:23:02.828275 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8279 00:23:02.831106 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8280 00:23:02.831624 == TX Byte 1 ==
8281 00:23:02.834271 u2DelayCellOfst[8]=0 cells (0 PI)
8282 00:23:02.837628 u2DelayCellOfst[9]=7 cells (2 PI)
8283 00:23:02.841457 u2DelayCellOfst[10]=10 cells (3 PI)
8284 00:23:02.844501 u2DelayCellOfst[11]=3 cells (1 PI)
8285 00:23:02.847640 u2DelayCellOfst[12]=18 cells (5 PI)
8286 00:23:02.850783 u2DelayCellOfst[13]=18 cells (5 PI)
8287 00:23:02.854149 u2DelayCellOfst[14]=18 cells (5 PI)
8288 00:23:02.857808 u2DelayCellOfst[15]=18 cells (5 PI)
8289 00:23:02.861322 Update DQ dly =971 (3 ,6, 11) DQ OEN =(3 ,3)
8290 00:23:02.867692 Update DQM dly =973 (3 ,6, 13) DQM OEN =(3 ,3)
8291 00:23:02.868134 DramC Write-DBI on
8292 00:23:02.868533 ==
8293 00:23:02.870759 Dram Type= 6, Freq= 0, CH_1, rank 0
8294 00:23:02.874030 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8295 00:23:02.874504 ==
8296 00:23:02.877257
8297 00:23:02.877776
8298 00:23:02.878248 TX Vref Scan disable
8299 00:23:02.880585 == TX Byte 0 ==
8300 00:23:02.883832 Update DQM dly =717 (2 ,6, 13) DQM OEN =(3 ,3)
8301 00:23:02.887765 == TX Byte 1 ==
8302 00:23:02.890618 Update DQM dly =715 (2 ,6, 11) DQM OEN =(3 ,3)
8303 00:23:02.894067 DramC Write-DBI off
8304 00:23:02.894539
8305 00:23:02.895006 [DATLAT]
8306 00:23:02.895342 Freq=1600, CH1 RK0
8307 00:23:02.895654
8308 00:23:02.897503 DATLAT Default: 0xf
8309 00:23:02.898014 0, 0xFFFF, sum = 0
8310 00:23:02.901039 1, 0xFFFF, sum = 0
8311 00:23:02.901508 2, 0xFFFF, sum = 0
8312 00:23:02.904225 3, 0xFFFF, sum = 0
8313 00:23:02.907140 4, 0xFFFF, sum = 0
8314 00:23:02.907740 5, 0xFFFF, sum = 0
8315 00:23:02.910312 6, 0xFFFF, sum = 0
8316 00:23:02.910755 7, 0xFFFF, sum = 0
8317 00:23:02.913634 8, 0xFFFF, sum = 0
8318 00:23:02.914073 9, 0xFFFF, sum = 0
8319 00:23:02.916913 10, 0xFFFF, sum = 0
8320 00:23:02.917368 11, 0xFFFF, sum = 0
8321 00:23:02.920834 12, 0xFFF, sum = 0
8322 00:23:02.921312 13, 0x0, sum = 1
8323 00:23:02.924072 14, 0x0, sum = 2
8324 00:23:02.924553 15, 0x0, sum = 3
8325 00:23:02.926850 16, 0x0, sum = 4
8326 00:23:02.927263 best_step = 14
8327 00:23:02.927566
8328 00:23:02.927847 ==
8329 00:23:02.930447 Dram Type= 6, Freq= 0, CH_1, rank 0
8330 00:23:02.933447 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8331 00:23:02.937169 ==
8332 00:23:02.937652 RX Vref Scan: 1
8333 00:23:02.937964
8334 00:23:02.940441 Set Vref Range= 24 -> 127
8335 00:23:02.940909
8336 00:23:02.943436 RX Vref 24 -> 127, step: 1
8337 00:23:02.943906
8338 00:23:02.944212 RX Delay 3 -> 252, step: 4
8339 00:23:02.944502
8340 00:23:02.946747 Set Vref, RX VrefLevel [Byte0]: 24
8341 00:23:02.949840 [Byte1]: 24
8342 00:23:02.954062
8343 00:23:02.954607 Set Vref, RX VrefLevel [Byte0]: 25
8344 00:23:02.957369 [Byte1]: 25
8345 00:23:02.961290
8346 00:23:02.961681 Set Vref, RX VrefLevel [Byte0]: 26
8347 00:23:02.964720 [Byte1]: 26
8348 00:23:02.968997
8349 00:23:02.969467 Set Vref, RX VrefLevel [Byte0]: 27
8350 00:23:02.972372 [Byte1]: 27
8351 00:23:02.976841
8352 00:23:02.977323 Set Vref, RX VrefLevel [Byte0]: 28
8353 00:23:02.980242 [Byte1]: 28
8354 00:23:02.984398
8355 00:23:02.984827 Set Vref, RX VrefLevel [Byte0]: 29
8356 00:23:02.987796 [Byte1]: 29
8357 00:23:02.992079
8358 00:23:02.992469 Set Vref, RX VrefLevel [Byte0]: 30
8359 00:23:02.995450 [Byte1]: 30
8360 00:23:02.999743
8361 00:23:03.000139 Set Vref, RX VrefLevel [Byte0]: 31
8362 00:23:03.003071 [Byte1]: 31
8363 00:23:03.007258
8364 00:23:03.007647 Set Vref, RX VrefLevel [Byte0]: 32
8365 00:23:03.010498 [Byte1]: 32
8366 00:23:03.014844
8367 00:23:03.015240 Set Vref, RX VrefLevel [Byte0]: 33
8368 00:23:03.018597 [Byte1]: 33
8369 00:23:03.022669
8370 00:23:03.023061 Set Vref, RX VrefLevel [Byte0]: 34
8371 00:23:03.025820 [Byte1]: 34
8372 00:23:03.030780
8373 00:23:03.031167 Set Vref, RX VrefLevel [Byte0]: 35
8374 00:23:03.033710 [Byte1]: 35
8375 00:23:03.038092
8376 00:23:03.038579 Set Vref, RX VrefLevel [Byte0]: 36
8377 00:23:03.041260 [Byte1]: 36
8378 00:23:03.045403
8379 00:23:03.045791 Set Vref, RX VrefLevel [Byte0]: 37
8380 00:23:03.049253 [Byte1]: 37
8381 00:23:03.053672
8382 00:23:03.054140 Set Vref, RX VrefLevel [Byte0]: 38
8383 00:23:03.057488 [Byte1]: 38
8384 00:23:03.061134
8385 00:23:03.061673 Set Vref, RX VrefLevel [Byte0]: 39
8386 00:23:03.064188 [Byte1]: 39
8387 00:23:03.068791
8388 00:23:03.069179 Set Vref, RX VrefLevel [Byte0]: 40
8389 00:23:03.072063 [Byte1]: 40
8390 00:23:03.076279
8391 00:23:03.076706 Set Vref, RX VrefLevel [Byte0]: 41
8392 00:23:03.079267 [Byte1]: 41
8393 00:23:03.084248
8394 00:23:03.084692 Set Vref, RX VrefLevel [Byte0]: 42
8395 00:23:03.087072 [Byte1]: 42
8396 00:23:03.091837
8397 00:23:03.092261 Set Vref, RX VrefLevel [Byte0]: 43
8398 00:23:03.095269 [Byte1]: 43
8399 00:23:03.099032
8400 00:23:03.099544 Set Vref, RX VrefLevel [Byte0]: 44
8401 00:23:03.102762 [Byte1]: 44
8402 00:23:03.107087
8403 00:23:03.107604 Set Vref, RX VrefLevel [Byte0]: 45
8404 00:23:03.110078 [Byte1]: 45
8405 00:23:03.115377
8406 00:23:03.115919 Set Vref, RX VrefLevel [Byte0]: 46
8407 00:23:03.117927 [Byte1]: 46
8408 00:23:03.122637
8409 00:23:03.123148 Set Vref, RX VrefLevel [Byte0]: 47
8410 00:23:03.125448 [Byte1]: 47
8411 00:23:03.129790
8412 00:23:03.130320 Set Vref, RX VrefLevel [Byte0]: 48
8413 00:23:03.133378 [Byte1]: 48
8414 00:23:03.137689
8415 00:23:03.138116 Set Vref, RX VrefLevel [Byte0]: 49
8416 00:23:03.141093 [Byte1]: 49
8417 00:23:03.145167
8418 00:23:03.145854 Set Vref, RX VrefLevel [Byte0]: 50
8419 00:23:03.148672 [Byte1]: 50
8420 00:23:03.153179
8421 00:23:03.153716 Set Vref, RX VrefLevel [Byte0]: 51
8422 00:23:03.156519 [Byte1]: 51
8423 00:23:03.160730
8424 00:23:03.161240 Set Vref, RX VrefLevel [Byte0]: 52
8425 00:23:03.163708 [Byte1]: 52
8426 00:23:03.168047
8427 00:23:03.168477 Set Vref, RX VrefLevel [Byte0]: 53
8428 00:23:03.172451 [Byte1]: 53
8429 00:23:03.175887
8430 00:23:03.176399 Set Vref, RX VrefLevel [Byte0]: 54
8431 00:23:03.179783 [Byte1]: 54
8432 00:23:03.183965
8433 00:23:03.184606 Set Vref, RX VrefLevel [Byte0]: 55
8434 00:23:03.186852 [Byte1]: 55
8435 00:23:03.191219
8436 00:23:03.191653 Set Vref, RX VrefLevel [Byte0]: 56
8437 00:23:03.194281 [Byte1]: 56
8438 00:23:03.198576
8439 00:23:03.199005 Set Vref, RX VrefLevel [Byte0]: 57
8440 00:23:03.201896 [Byte1]: 57
8441 00:23:03.206309
8442 00:23:03.206735 Set Vref, RX VrefLevel [Byte0]: 58
8443 00:23:03.209617 [Byte1]: 58
8444 00:23:03.214028
8445 00:23:03.214503 Set Vref, RX VrefLevel [Byte0]: 59
8446 00:23:03.216937 [Byte1]: 59
8447 00:23:03.221890
8448 00:23:03.222322 Set Vref, RX VrefLevel [Byte0]: 60
8449 00:23:03.224609 [Byte1]: 60
8450 00:23:03.229113
8451 00:23:03.229602 Set Vref, RX VrefLevel [Byte0]: 61
8452 00:23:03.232478 [Byte1]: 61
8453 00:23:03.236872
8454 00:23:03.237261 Set Vref, RX VrefLevel [Byte0]: 62
8455 00:23:03.240373 [Byte1]: 62
8456 00:23:03.244812
8457 00:23:03.245283 Set Vref, RX VrefLevel [Byte0]: 63
8458 00:23:03.247949 [Byte1]: 63
8459 00:23:03.252410
8460 00:23:03.252796 Set Vref, RX VrefLevel [Byte0]: 64
8461 00:23:03.255630 [Byte1]: 64
8462 00:23:03.259957
8463 00:23:03.260385 Set Vref, RX VrefLevel [Byte0]: 65
8464 00:23:03.263290 [Byte1]: 65
8465 00:23:03.267885
8466 00:23:03.268315 Set Vref, RX VrefLevel [Byte0]: 66
8467 00:23:03.271011 [Byte1]: 66
8468 00:23:03.275215
8469 00:23:03.275641 Set Vref, RX VrefLevel [Byte0]: 67
8470 00:23:03.278390 [Byte1]: 67
8471 00:23:03.283163
8472 00:23:03.283674 Set Vref, RX VrefLevel [Byte0]: 68
8473 00:23:03.286688 [Byte1]: 68
8474 00:23:03.290653
8475 00:23:03.291159 Set Vref, RX VrefLevel [Byte0]: 69
8476 00:23:03.294199 [Byte1]: 69
8477 00:23:03.298569
8478 00:23:03.299078 Set Vref, RX VrefLevel [Byte0]: 70
8479 00:23:03.301450 [Byte1]: 70
8480 00:23:03.306200
8481 00:23:03.306746 Set Vref, RX VrefLevel [Byte0]: 71
8482 00:23:03.309226 [Byte1]: 71
8483 00:23:03.313611
8484 00:23:03.314046 Set Vref, RX VrefLevel [Byte0]: 72
8485 00:23:03.316659 [Byte1]: 72
8486 00:23:03.320952
8487 00:23:03.321492 Set Vref, RX VrefLevel [Byte0]: 73
8488 00:23:03.324345 [Byte1]: 73
8489 00:23:03.328985
8490 00:23:03.329412 Set Vref, RX VrefLevel [Byte0]: 74
8491 00:23:03.331902 [Byte1]: 74
8492 00:23:03.336238
8493 00:23:03.336673 Set Vref, RX VrefLevel [Byte0]: 75
8494 00:23:03.339980 [Byte1]: 75
8495 00:23:03.344103
8496 00:23:03.344613 Set Vref, RX VrefLevel [Byte0]: 76
8497 00:23:03.347757 [Byte1]: 76
8498 00:23:03.352349
8499 00:23:03.352864 Set Vref, RX VrefLevel [Byte0]: 77
8500 00:23:03.355165 [Byte1]: 77
8501 00:23:03.359573
8502 00:23:03.360006 Set Vref, RX VrefLevel [Byte0]: 78
8503 00:23:03.362533 [Byte1]: 78
8504 00:23:03.367280
8505 00:23:03.367715 Final RX Vref Byte 0 = 62 to rank0
8506 00:23:03.370287 Final RX Vref Byte 1 = 55 to rank0
8507 00:23:03.373726 Final RX Vref Byte 0 = 62 to rank1
8508 00:23:03.377169 Final RX Vref Byte 1 = 55 to rank1==
8509 00:23:03.380427 Dram Type= 6, Freq= 0, CH_1, rank 0
8510 00:23:03.387021 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8511 00:23:03.387656 ==
8512 00:23:03.388183 DQS Delay:
8513 00:23:03.388655 DQS0 = 0, DQS1 = 0
8514 00:23:03.390185 DQM Delay:
8515 00:23:03.390663 DQM0 = 128, DQM1 = 124
8516 00:23:03.393574 DQ Delay:
8517 00:23:03.397233 DQ0 =132, DQ1 =124, DQ2 =116, DQ3 =126
8518 00:23:03.400481 DQ4 =128, DQ5 =138, DQ6 =138, DQ7 =126
8519 00:23:03.403514 DQ8 =106, DQ9 =114, DQ10 =126, DQ11 =114
8520 00:23:03.406857 DQ12 =130, DQ13 =134, DQ14 =134, DQ15 =134
8521 00:23:03.407291
8522 00:23:03.407625
8523 00:23:03.407930
8524 00:23:03.410115 [DramC_TX_OE_Calibration] TA2
8525 00:23:03.413644 Original DQ_B0 (3 6) =30, OEN = 27
8526 00:23:03.416667 Original DQ_B1 (3 6) =30, OEN = 27
8527 00:23:03.420208 24, 0x0, End_B0=24 End_B1=24
8528 00:23:03.420647 25, 0x0, End_B0=25 End_B1=25
8529 00:23:03.423519 26, 0x0, End_B0=26 End_B1=26
8530 00:23:03.426539 27, 0x0, End_B0=27 End_B1=27
8531 00:23:03.430090 28, 0x0, End_B0=28 End_B1=28
8532 00:23:03.433675 29, 0x0, End_B0=29 End_B1=29
8533 00:23:03.434194 30, 0x0, End_B0=30 End_B1=30
8534 00:23:03.436518 31, 0x4141, End_B0=30 End_B1=30
8535 00:23:03.440166 Byte0 end_step=30 best_step=27
8536 00:23:03.443400 Byte1 end_step=30 best_step=27
8537 00:23:03.446810 Byte0 TX OE(2T, 0.5T) = (3, 3)
8538 00:23:03.450109 Byte1 TX OE(2T, 0.5T) = (3, 3)
8539 00:23:03.450675
8540 00:23:03.451088
8541 00:23:03.456716 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c2c, (MSB)MR19= 0x303, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
8542 00:23:03.459964 CH1 RK0: MR19=303, MR18=2C2C
8543 00:23:03.466420 CH1_RK0: MR19=0x303, MR18=0x2C2C, DQSOSC=387, MR23=63, INC=24, DEC=16
8544 00:23:03.467100
8545 00:23:03.469714 ----->DramcWriteLeveling(PI) begin...
8546 00:23:03.470153 ==
8547 00:23:03.473082 Dram Type= 6, Freq= 0, CH_1, rank 1
8548 00:23:03.476387 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8549 00:23:03.476836 ==
8550 00:23:03.479910 Write leveling (Byte 0): 23 => 23
8551 00:23:03.483092 Write leveling (Byte 1): 20 => 20
8552 00:23:03.486613 DramcWriteLeveling(PI) end<-----
8553 00:23:03.487142
8554 00:23:03.487579 ==
8555 00:23:03.489646 Dram Type= 6, Freq= 0, CH_1, rank 1
8556 00:23:03.493602 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8557 00:23:03.494179 ==
8558 00:23:03.496416 [Gating] SW mode calibration
8559 00:23:03.502892 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8560 00:23:03.509663 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8561 00:23:03.513343 0 12 0 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
8562 00:23:03.519753 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8563 00:23:03.523221 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8564 00:23:03.526357 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8565 00:23:03.530113 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8566 00:23:03.536158 0 12 20 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
8567 00:23:03.539535 0 12 24 | B1->B0 | 3434 2525 | 1 0 | (1 1) (1 0)
8568 00:23:03.542819 0 12 28 | B1->B0 | 3434 2323 | 0 0 | (1 0) (0 0)
8569 00:23:03.549542 0 13 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8570 00:23:03.552819 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8571 00:23:03.555831 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8572 00:23:03.562509 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8573 00:23:03.565831 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8574 00:23:03.568976 0 13 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8575 00:23:03.576042 0 13 24 | B1->B0 | 2323 4040 | 0 1 | (0 0) (0 0)
8576 00:23:03.579052 0 13 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8577 00:23:03.582326 0 14 0 | B1->B0 | 403f 4646 | 1 0 | (0 0) (0 0)
8578 00:23:03.589395 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8579 00:23:03.592597 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8580 00:23:03.595821 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8581 00:23:03.602957 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8582 00:23:03.605758 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8583 00:23:03.609083 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8584 00:23:03.615477 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8585 00:23:03.618861 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8586 00:23:03.622153 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8587 00:23:03.629059 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8588 00:23:03.632332 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8589 00:23:03.635989 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8590 00:23:03.642109 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8591 00:23:03.645198 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8592 00:23:03.648690 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8593 00:23:03.655220 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8594 00:23:03.658525 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8595 00:23:03.661973 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8596 00:23:03.668372 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8597 00:23:03.671651 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8598 00:23:03.675118 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8599 00:23:03.681881 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8600 00:23:03.685379 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8601 00:23:03.688338 Total UI for P1: 0, mck2ui 16
8602 00:23:03.691695 best dqsien dly found for B0: ( 1, 0, 22)
8603 00:23:03.695040 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8604 00:23:03.698317 Total UI for P1: 0, mck2ui 16
8605 00:23:03.701738 best dqsien dly found for B1: ( 1, 0, 28)
8606 00:23:03.705070 best DQS0 dly(MCK, UI, PI) = (1, 0, 22)
8607 00:23:03.708587 best DQS1 dly(MCK, UI, PI) = (1, 0, 28)
8608 00:23:03.708978
8609 00:23:03.711737 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 22)
8610 00:23:03.718060 best DQS1 P1 dly(MCK, UI, PI) = (1, 4, 28)
8611 00:23:03.718556 [Gating] SW calibration Done
8612 00:23:03.721534 ==
8613 00:23:03.721926 Dram Type= 6, Freq= 0, CH_1, rank 1
8614 00:23:03.727995 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8615 00:23:03.728388 ==
8616 00:23:03.728691 RX Vref Scan: 0
8617 00:23:03.728973
8618 00:23:03.731798 RX Vref 0 -> 0, step: 1
8619 00:23:03.732187
8620 00:23:03.734662 RX Delay 0 -> 252, step: 8
8621 00:23:03.738489 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8622 00:23:03.741576 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8623 00:23:03.744551 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8624 00:23:03.751278 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8625 00:23:03.755128 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8626 00:23:03.758404 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8627 00:23:03.761095 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8628 00:23:03.764412 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8629 00:23:03.771103 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8630 00:23:03.774437 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8631 00:23:03.777532 iDelay=200, Bit 10, Center 127 (64 ~ 191) 128
8632 00:23:03.781324 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8633 00:23:03.784442 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8634 00:23:03.790920 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8635 00:23:03.794390 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8636 00:23:03.797852 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8637 00:23:03.798281 ==
8638 00:23:03.801370 Dram Type= 6, Freq= 0, CH_1, rank 1
8639 00:23:03.804295 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8640 00:23:03.808092 ==
8641 00:23:03.808493 DQS Delay:
8642 00:23:03.808808 DQS0 = 0, DQS1 = 0
8643 00:23:03.810812 DQM Delay:
8644 00:23:03.811195 DQM0 = 130, DQM1 = 125
8645 00:23:03.814083 DQ Delay:
8646 00:23:03.817572 DQ0 =131, DQ1 =123, DQ2 =119, DQ3 =131
8647 00:23:03.820724 DQ4 =127, DQ5 =143, DQ6 =139, DQ7 =131
8648 00:23:03.824469 DQ8 =107, DQ9 =115, DQ10 =127, DQ11 =115
8649 00:23:03.827925 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =131
8650 00:23:03.828404
8651 00:23:03.828710
8652 00:23:03.828989 ==
8653 00:23:03.830721 Dram Type= 6, Freq= 0, CH_1, rank 1
8654 00:23:03.834027 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8655 00:23:03.834455 ==
8656 00:23:03.834760
8657 00:23:03.837462
8658 00:23:03.837883 TX Vref Scan disable
8659 00:23:03.841042 == TX Byte 0 ==
8660 00:23:03.844624 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8661 00:23:03.847639 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8662 00:23:03.851142 == TX Byte 1 ==
8663 00:23:03.854116 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8664 00:23:03.857919 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8665 00:23:03.858502 ==
8666 00:23:03.860650 Dram Type= 6, Freq= 0, CH_1, rank 1
8667 00:23:03.867066 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8668 00:23:03.867539 ==
8669 00:23:03.878895
8670 00:23:03.882200 TX Vref early break, caculate TX vref
8671 00:23:03.885266 TX Vref=16, minBit 0, minWin=23, winSum=386
8672 00:23:03.888990 TX Vref=18, minBit 5, minWin=22, winSum=392
8673 00:23:03.892078 TX Vref=20, minBit 0, minWin=23, winSum=395
8674 00:23:03.895626 TX Vref=22, minBit 1, minWin=24, winSum=405
8675 00:23:03.898554 TX Vref=24, minBit 0, minWin=25, winSum=416
8676 00:23:03.905256 TX Vref=26, minBit 2, minWin=24, winSum=417
8677 00:23:03.908359 TX Vref=28, minBit 0, minWin=24, winSum=421
8678 00:23:03.912232 TX Vref=30, minBit 0, minWin=24, winSum=417
8679 00:23:03.915758 TX Vref=32, minBit 0, minWin=24, winSum=409
8680 00:23:03.918458 TX Vref=34, minBit 0, minWin=22, winSum=395
8681 00:23:03.925233 [TxChooseVref] Worse bit 0, Min win 25, Win sum 416, Final Vref 24
8682 00:23:03.925754
8683 00:23:03.928313 Final TX Range 0 Vref 24
8684 00:23:03.928744
8685 00:23:03.929146 ==
8686 00:23:03.931752 Dram Type= 6, Freq= 0, CH_1, rank 1
8687 00:23:03.935224 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8688 00:23:03.935662 ==
8689 00:23:03.936002
8690 00:23:03.936313
8691 00:23:03.938182 TX Vref Scan disable
8692 00:23:03.945242 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8693 00:23:03.945765 == TX Byte 0 ==
8694 00:23:03.948143 u2DelayCellOfst[0]=18 cells (5 PI)
8695 00:23:03.951889 u2DelayCellOfst[1]=10 cells (3 PI)
8696 00:23:03.955096 u2DelayCellOfst[2]=0 cells (0 PI)
8697 00:23:03.958452 u2DelayCellOfst[3]=7 cells (2 PI)
8698 00:23:03.961511 u2DelayCellOfst[4]=10 cells (3 PI)
8699 00:23:03.964995 u2DelayCellOfst[5]=18 cells (5 PI)
8700 00:23:03.967998 u2DelayCellOfst[6]=18 cells (5 PI)
8701 00:23:03.971477 u2DelayCellOfst[7]=7 cells (2 PI)
8702 00:23:03.975051 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8703 00:23:03.978152 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8704 00:23:03.981587 == TX Byte 1 ==
8705 00:23:03.982110 u2DelayCellOfst[8]=0 cells (0 PI)
8706 00:23:03.984523 u2DelayCellOfst[9]=3 cells (1 PI)
8707 00:23:03.988182 u2DelayCellOfst[10]=10 cells (3 PI)
8708 00:23:03.991447 u2DelayCellOfst[11]=3 cells (1 PI)
8709 00:23:03.994632 u2DelayCellOfst[12]=14 cells (4 PI)
8710 00:23:03.998274 u2DelayCellOfst[13]=18 cells (5 PI)
8711 00:23:04.001212 u2DelayCellOfst[14]=14 cells (4 PI)
8712 00:23:04.004512 u2DelayCellOfst[15]=14 cells (4 PI)
8713 00:23:04.007644 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8714 00:23:04.014209 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8715 00:23:04.014756 DramC Write-DBI on
8716 00:23:04.015098 ==
8717 00:23:04.017706 Dram Type= 6, Freq= 0, CH_1, rank 1
8718 00:23:04.024160 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8719 00:23:04.024713 ==
8720 00:23:04.025194
8721 00:23:04.025652
8722 00:23:04.026102 TX Vref Scan disable
8723 00:23:04.027794 == TX Byte 0 ==
8724 00:23:04.031441 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8725 00:23:04.034795 == TX Byte 1 ==
8726 00:23:04.038345 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8727 00:23:04.041250 DramC Write-DBI off
8728 00:23:04.041680
8729 00:23:04.042012 [DATLAT]
8730 00:23:04.042377 Freq=1600, CH1 RK1
8731 00:23:04.042690
8732 00:23:04.044742 DATLAT Default: 0xe
8733 00:23:04.045175 0, 0xFFFF, sum = 0
8734 00:23:04.048227 1, 0xFFFF, sum = 0
8735 00:23:04.048755 2, 0xFFFF, sum = 0
8736 00:23:04.051514 3, 0xFFFF, sum = 0
8737 00:23:04.054692 4, 0xFFFF, sum = 0
8738 00:23:04.055136 5, 0xFFFF, sum = 0
8739 00:23:04.058303 6, 0xFFFF, sum = 0
8740 00:23:04.058800 7, 0xFFFF, sum = 0
8741 00:23:04.061509 8, 0xFFFF, sum = 0
8742 00:23:04.062043 9, 0xFFFF, sum = 0
8743 00:23:04.064573 10, 0xFFFF, sum = 0
8744 00:23:04.065080 11, 0xFFFF, sum = 0
8745 00:23:04.068195 12, 0xF7F, sum = 0
8746 00:23:04.068669 13, 0x0, sum = 1
8747 00:23:04.071271 14, 0x0, sum = 2
8748 00:23:04.071717 15, 0x0, sum = 3
8749 00:23:04.074772 16, 0x0, sum = 4
8750 00:23:04.075216 best_step = 14
8751 00:23:04.075554
8752 00:23:04.075866 ==
8753 00:23:04.077880 Dram Type= 6, Freq= 0, CH_1, rank 1
8754 00:23:04.081532 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8755 00:23:04.084823 ==
8756 00:23:04.085346 RX Vref Scan: 0
8757 00:23:04.085690
8758 00:23:04.087780 RX Vref 0 -> 0, step: 1
8759 00:23:04.088299
8760 00:23:04.088644 RX Delay 3 -> 252, step: 4
8761 00:23:04.094924 iDelay=195, Bit 0, Center 128 (75 ~ 182) 108
8762 00:23:04.098730 iDelay=195, Bit 1, Center 122 (67 ~ 178) 112
8763 00:23:04.101629 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8764 00:23:04.105171 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8765 00:23:04.108293 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8766 00:23:04.114844 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8767 00:23:04.118031 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8768 00:23:04.121460 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8769 00:23:04.125191 iDelay=195, Bit 8, Center 104 (47 ~ 162) 116
8770 00:23:04.128296 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8771 00:23:04.135039 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116
8772 00:23:04.138416 iDelay=195, Bit 11, Center 112 (55 ~ 170) 116
8773 00:23:04.141877 iDelay=195, Bit 12, Center 130 (71 ~ 190) 120
8774 00:23:04.145360 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8775 00:23:04.151307 iDelay=195, Bit 14, Center 132 (75 ~ 190) 116
8776 00:23:04.154550 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8777 00:23:04.154994 ==
8778 00:23:04.158102 Dram Type= 6, Freq= 0, CH_1, rank 1
8779 00:23:04.161384 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8780 00:23:04.161828 ==
8781 00:23:04.164639 DQS Delay:
8782 00:23:04.165221 DQS0 = 0, DQS1 = 0
8783 00:23:04.165569 DQM Delay:
8784 00:23:04.167696 DQM0 = 127, DQM1 = 122
8785 00:23:04.168133 DQ Delay:
8786 00:23:04.171109 DQ0 =128, DQ1 =122, DQ2 =116, DQ3 =124
8787 00:23:04.174560 DQ4 =126, DQ5 =138, DQ6 =136, DQ7 =126
8788 00:23:04.177670 DQ8 =104, DQ9 =110, DQ10 =124, DQ11 =112
8789 00:23:04.184734 DQ12 =130, DQ13 =132, DQ14 =132, DQ15 =132
8790 00:23:04.185253
8791 00:23:04.185592
8792 00:23:04.185903
8793 00:23:04.188135 [DramC_TX_OE_Calibration] TA2
8794 00:23:04.188654 Original DQ_B0 (3 6) =30, OEN = 27
8795 00:23:04.191407 Original DQ_B1 (3 6) =30, OEN = 27
8796 00:23:04.194974 24, 0x0, End_B0=24 End_B1=24
8797 00:23:04.197973 25, 0x0, End_B0=25 End_B1=25
8798 00:23:04.201638 26, 0x0, End_B0=26 End_B1=26
8799 00:23:04.204352 27, 0x0, End_B0=27 End_B1=27
8800 00:23:04.204810 28, 0x0, End_B0=28 End_B1=28
8801 00:23:04.207848 29, 0x0, End_B0=29 End_B1=29
8802 00:23:04.211080 30, 0x0, End_B0=30 End_B1=30
8803 00:23:04.214532 31, 0x4141, End_B0=30 End_B1=30
8804 00:23:04.217965 Byte0 end_step=30 best_step=27
8805 00:23:04.218561 Byte1 end_step=30 best_step=27
8806 00:23:04.221142 Byte0 TX OE(2T, 0.5T) = (3, 3)
8807 00:23:04.224393 Byte1 TX OE(2T, 0.5T) = (3, 3)
8808 00:23:04.224925
8809 00:23:04.225268
8810 00:23:04.234045 [DQSOSCAuto] RK1, (LSB)MR18= 0x2121, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
8811 00:23:04.234606 CH1 RK1: MR19=303, MR18=2121
8812 00:23:04.241020 CH1_RK1: MR19=0x303, MR18=0x2121, DQSOSC=393, MR23=63, INC=23, DEC=15
8813 00:23:04.244803 [RxdqsGatingPostProcess] freq 1600
8814 00:23:04.251143 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8815 00:23:04.254680 Pre-setting of DQS Precalculation
8816 00:23:04.257245 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8817 00:23:04.264018 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8818 00:23:04.273947 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8819 00:23:04.274425
8820 00:23:04.274769
8821 00:23:04.277518 [Calibration Summary] 3200 Mbps
8822 00:23:04.277961 CH 0, Rank 0
8823 00:23:04.280802 SW Impedance : PASS
8824 00:23:04.281242 DUTY Scan : NO K
8825 00:23:04.284110 ZQ Calibration : PASS
8826 00:23:04.287430 Jitter Meter : NO K
8827 00:23:04.287950 CBT Training : PASS
8828 00:23:04.290961 Write leveling : PASS
8829 00:23:04.294031 RX DQS gating : PASS
8830 00:23:04.294590 RX DQ/DQS(RDDQC) : PASS
8831 00:23:04.297121 TX DQ/DQS : PASS
8832 00:23:04.297559 RX DATLAT : PASS
8833 00:23:04.300609 RX DQ/DQS(Engine): PASS
8834 00:23:04.304102 TX OE : PASS
8835 00:23:04.304620 All Pass.
8836 00:23:04.304962
8837 00:23:04.305276 CH 0, Rank 1
8838 00:23:04.307464 SW Impedance : PASS
8839 00:23:04.311080 DUTY Scan : NO K
8840 00:23:04.311593 ZQ Calibration : PASS
8841 00:23:04.314121 Jitter Meter : NO K
8842 00:23:04.317339 CBT Training : PASS
8843 00:23:04.317872 Write leveling : PASS
8844 00:23:04.320351 RX DQS gating : PASS
8845 00:23:04.324242 RX DQ/DQS(RDDQC) : PASS
8846 00:23:04.324756 TX DQ/DQS : PASS
8847 00:23:04.326923 RX DATLAT : PASS
8848 00:23:04.330269 RX DQ/DQS(Engine): PASS
8849 00:23:04.330710 TX OE : PASS
8850 00:23:04.333905 All Pass.
8851 00:23:04.334478
8852 00:23:04.334823 CH 1, Rank 0
8853 00:23:04.336923 SW Impedance : PASS
8854 00:23:04.337361 DUTY Scan : NO K
8855 00:23:04.340482 ZQ Calibration : PASS
8856 00:23:04.343833 Jitter Meter : NO K
8857 00:23:04.344353 CBT Training : PASS
8858 00:23:04.347119 Write leveling : PASS
8859 00:23:04.350093 RX DQS gating : PASS
8860 00:23:04.350567 RX DQ/DQS(RDDQC) : PASS
8861 00:23:04.353694 TX DQ/DQS : PASS
8862 00:23:04.354247 RX DATLAT : PASS
8863 00:23:04.357444 RX DQ/DQS(Engine): PASS
8864 00:23:04.360259 TX OE : PASS
8865 00:23:04.360783 All Pass.
8866 00:23:04.361126
8867 00:23:04.361443 CH 1, Rank 1
8868 00:23:04.363366 SW Impedance : PASS
8869 00:23:04.366921 DUTY Scan : NO K
8870 00:23:04.367362 ZQ Calibration : PASS
8871 00:23:04.370557 Jitter Meter : NO K
8872 00:23:04.373841 CBT Training : PASS
8873 00:23:04.374352 Write leveling : PASS
8874 00:23:04.377456 RX DQS gating : PASS
8875 00:23:04.380559 RX DQ/DQS(RDDQC) : PASS
8876 00:23:04.381092 TX DQ/DQS : PASS
8877 00:23:04.383828 RX DATLAT : PASS
8878 00:23:04.387311 RX DQ/DQS(Engine): PASS
8879 00:23:04.387760 TX OE : PASS
8880 00:23:04.390325 All Pass.
8881 00:23:04.390769
8882 00:23:04.391206 DramC Write-DBI on
8883 00:23:04.393419 PER_BANK_REFRESH: Hybrid Mode
8884 00:23:04.393865 TX_TRACKING: ON
8885 00:23:04.403649 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8886 00:23:04.410149 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8887 00:23:04.420130 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8888 00:23:04.423889 [FAST_K] Save calibration result to emmc
8889 00:23:04.427150 sync common calibartion params.
8890 00:23:04.427684 sync cbt_mode0:0, 1:0
8891 00:23:04.430320 dram_init: ddr_geometry: 0
8892 00:23:04.433679 dram_init: ddr_geometry: 0
8893 00:23:04.434265 dram_init: ddr_geometry: 0
8894 00:23:04.437050 0:dram_rank_size:80000000
8895 00:23:04.440052 1:dram_rank_size:80000000
8896 00:23:04.443502 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8897 00:23:04.447104 DFS_SHUFFLE_HW_MODE: ON
8898 00:23:04.450078 dramc_set_vcore_voltage set vcore to 725000
8899 00:23:04.453157 Read voltage for 1600, 0
8900 00:23:04.453693 Vio18 = 0
8901 00:23:04.456476 Vcore = 725000
8902 00:23:04.457003 Vdram = 0
8903 00:23:04.457448 Vddq = 0
8904 00:23:04.457860 Vmddr = 0
8905 00:23:04.459666 switch to 3200 Mbps bootup
8906 00:23:04.463434 [DramcRunTimeConfig]
8907 00:23:04.463965 PHYPLL
8908 00:23:04.466202 DPM_CONTROL_AFTERK: ON
8909 00:23:04.466698 PER_BANK_REFRESH: ON
8910 00:23:04.469462 REFRESH_OVERHEAD_REDUCTION: ON
8911 00:23:04.473087 CMD_PICG_NEW_MODE: OFF
8912 00:23:04.473536 XRTWTW_NEW_MODE: ON
8913 00:23:04.476617 XRTRTR_NEW_MODE: ON
8914 00:23:04.477150 TX_TRACKING: ON
8915 00:23:04.479657 RDSEL_TRACKING: OFF
8916 00:23:04.482795 DQS Precalculation for DVFS: ON
8917 00:23:04.483301 RX_TRACKING: OFF
8918 00:23:04.485988 HW_GATING DBG: ON
8919 00:23:04.486494 ZQCS_ENABLE_LP4: ON
8920 00:23:04.490023 RX_PICG_NEW_MODE: ON
8921 00:23:04.490627 TX_PICG_NEW_MODE: ON
8922 00:23:04.493211 ENABLE_RX_DCM_DPHY: ON
8923 00:23:04.496040 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8924 00:23:04.499497 DUMMY_READ_FOR_TRACKING: OFF
8925 00:23:04.499949 !!! SPM_CONTROL_AFTERK: OFF
8926 00:23:04.502932 !!! SPM could not control APHY
8927 00:23:04.506163 IMPEDANCE_TRACKING: ON
8928 00:23:04.506733 TEMP_SENSOR: ON
8929 00:23:04.509394 HW_SAVE_FOR_SR: OFF
8930 00:23:04.513071 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8931 00:23:04.515959 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8932 00:23:04.516412 Read ODT Tracking: ON
8933 00:23:04.519212 Refresh Rate DeBounce: ON
8934 00:23:04.522586 DFS_NO_QUEUE_FLUSH: ON
8935 00:23:04.525851 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8936 00:23:04.526415 ENABLE_DFS_RUNTIME_MRW: OFF
8937 00:23:04.529251 DDR_RESERVE_NEW_MODE: ON
8938 00:23:04.532853 MR_CBT_SWITCH_FREQ: ON
8939 00:23:04.533390 =========================
8940 00:23:04.553444 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8941 00:23:04.556049 dram_init: ddr_geometry: 0
8942 00:23:04.574103 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8943 00:23:04.577325 dram_init: dram init end (result: 0)
8944 00:23:04.584065 DRAM-K: Full calibration passed in 23452 msecs
8945 00:23:04.587115 MRC: failed to locate region type 0.
8946 00:23:04.587566 DRAM rank0 size:0x80000000,
8947 00:23:04.590331 DRAM rank1 size=0x80000000
8948 00:23:04.600819 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8949 00:23:04.606944 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8950 00:23:04.613856 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8951 00:23:04.620788 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8952 00:23:04.623577 DRAM rank0 size:0x80000000,
8953 00:23:04.626961 DRAM rank1 size=0x80000000
8954 00:23:04.627397 CBMEM:
8955 00:23:04.630447 IMD: root @ 0xfffff000 254 entries.
8956 00:23:04.634292 IMD: root @ 0xffffec00 62 entries.
8957 00:23:04.636963 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8958 00:23:04.640357 WARNING: RO_VPD is uninitialized or empty.
8959 00:23:04.646859 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8960 00:23:04.654008 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8961 00:23:04.666428 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
8962 00:23:04.677744 BS: romstage times (exec / console): total (unknown) / 22982 ms
8963 00:23:04.678392
8964 00:23:04.678837
8965 00:23:04.687770 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8966 00:23:04.690791 ARM64: Exception handlers installed.
8967 00:23:04.694448 ARM64: Testing exception
8968 00:23:04.697486 ARM64: Done test exception
8969 00:23:04.697943 Enumerating buses...
8970 00:23:04.701106 Show all devs... Before device enumeration.
8971 00:23:04.704024 Root Device: enabled 1
8972 00:23:04.707686 CPU_CLUSTER: 0: enabled 1
8973 00:23:04.708215 CPU: 00: enabled 1
8974 00:23:04.711063 Compare with tree...
8975 00:23:04.711642 Root Device: enabled 1
8976 00:23:04.714379 CPU_CLUSTER: 0: enabled 1
8977 00:23:04.718301 CPU: 00: enabled 1
8978 00:23:04.718823 Root Device scanning...
8979 00:23:04.720806 scan_static_bus for Root Device
8980 00:23:04.724143 CPU_CLUSTER: 0 enabled
8981 00:23:04.727223 scan_static_bus for Root Device done
8982 00:23:04.730680 scan_bus: bus Root Device finished in 8 msecs
8983 00:23:04.731121 done
8984 00:23:04.737454 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8985 00:23:04.740829 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8986 00:23:04.747447 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8987 00:23:04.750816 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8988 00:23:04.753700 Allocating resources...
8989 00:23:04.758076 Reading resources...
8990 00:23:04.760762 Root Device read_resources bus 0 link: 0
8991 00:23:04.761290 DRAM rank0 size:0x80000000,
8992 00:23:04.764066 DRAM rank1 size=0x80000000
8993 00:23:04.767274 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8994 00:23:04.770354 CPU: 00 missing read_resources
8995 00:23:04.773513 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8996 00:23:04.780756 Root Device read_resources bus 0 link: 0 done
8997 00:23:04.781285 Done reading resources.
8998 00:23:04.787160 Show resources in subtree (Root Device)...After reading.
8999 00:23:04.790810 Root Device child on link 0 CPU_CLUSTER: 0
9000 00:23:04.793722 CPU_CLUSTER: 0 child on link 0 CPU: 00
9001 00:23:04.803614 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
9002 00:23:04.804060 CPU: 00
9003 00:23:04.806826 Root Device assign_resources, bus 0 link: 0
9004 00:23:04.810366 CPU_CLUSTER: 0 missing set_resources
9005 00:23:04.816789 Root Device assign_resources, bus 0 link: 0 done
9006 00:23:04.817298 Done setting resources.
9007 00:23:04.823311 Show resources in subtree (Root Device)...After assigning values.
9008 00:23:04.826808 Root Device child on link 0 CPU_CLUSTER: 0
9009 00:23:04.830115 CPU_CLUSTER: 0 child on link 0 CPU: 00
9010 00:23:04.839941 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
9011 00:23:04.840455 CPU: 00
9012 00:23:04.843781 Done allocating resources.
9013 00:23:04.846583 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9014 00:23:04.850123 Enabling resources...
9015 00:23:04.850686 done.
9016 00:23:04.856798 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9017 00:23:04.857314 Initializing devices...
9018 00:23:04.859847 Root Device init
9019 00:23:04.860479 init hardware done!
9020 00:23:04.863636 0x00000018: ctrlr->caps
9021 00:23:04.866622 52.000 MHz: ctrlr->f_max
9022 00:23:04.867147 0.400 MHz: ctrlr->f_min
9023 00:23:04.869899 0x40ff8080: ctrlr->voltages
9024 00:23:04.870493 sclk: 390625
9025 00:23:04.873188 Bus Width = 1
9026 00:23:04.873559 sclk: 390625
9027 00:23:04.876297 Bus Width = 1
9028 00:23:04.876731 Early init status = 3
9029 00:23:04.882887 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9030 00:23:04.886383 in-header: 03 fc 00 00 01 00 00 00
9031 00:23:04.886832 in-data: 00
9032 00:23:04.892715 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9033 00:23:04.896334 in-header: 03 fd 00 00 00 00 00 00
9034 00:23:04.899542 in-data:
9035 00:23:04.902930 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9036 00:23:04.906658 in-header: 03 fc 00 00 01 00 00 00
9037 00:23:04.909876 in-data: 00
9038 00:23:04.912670 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9039 00:23:04.917530 in-header: 03 fd 00 00 00 00 00 00
9040 00:23:04.921081 in-data:
9041 00:23:04.924477 [SSUSB] Setting up USB HOST controller...
9042 00:23:04.927923 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9043 00:23:04.931107 [SSUSB] phy power-on done.
9044 00:23:04.934164 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9045 00:23:04.941520 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9046 00:23:04.944174 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9047 00:23:04.950913 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9048 00:23:04.957365 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9049 00:23:04.964210 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9050 00:23:04.971245 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9051 00:23:04.977347 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9052 00:23:04.980861 SPM: binary array size = 0x9dc
9053 00:23:04.984417 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9054 00:23:04.990737 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9055 00:23:04.997547 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9056 00:23:05.004021 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9057 00:23:05.007135 configure_display: Starting display init
9058 00:23:05.041113 anx7625_power_on_init: Init interface.
9059 00:23:05.044129 anx7625_disable_pd_protocol: Disabled PD feature.
9060 00:23:05.047179 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9061 00:23:05.075863 anx7625_start_dp_work: Secure OCM version=00
9062 00:23:05.078392 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9063 00:23:05.093786 sp_tx_get_edid_block: EDID Block = 1
9064 00:23:05.196124 Extracted contents:
9065 00:23:05.199256 header: 00 ff ff ff ff ff ff 00
9066 00:23:05.202588 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9067 00:23:05.206132 version: 01 04
9068 00:23:05.209415 basic params: 95 1f 11 78 0a
9069 00:23:05.212871 chroma info: 76 90 94 55 54 90 27 21 50 54
9070 00:23:05.216467 established: 00 00 00
9071 00:23:05.219388 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9072 00:23:05.226366 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9073 00:23:05.232656 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9074 00:23:05.239336 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9075 00:23:05.246604 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9076 00:23:05.249476 extensions: 00
9077 00:23:05.249987 checksum: fb
9078 00:23:05.250372
9079 00:23:05.252322 Manufacturer: IVO Model 57d Serial Number 0
9080 00:23:05.256139 Made week 0 of 2020
9081 00:23:05.256681 EDID version: 1.4
9082 00:23:05.259784 Digital display
9083 00:23:05.262515 6 bits per primary color channel
9084 00:23:05.263055 DisplayPort interface
9085 00:23:05.265983 Maximum image size: 31 cm x 17 cm
9086 00:23:05.269120 Gamma: 220%
9087 00:23:05.269635 Check DPMS levels
9088 00:23:05.272780 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9089 00:23:05.275662 First detailed timing is preferred timing
9090 00:23:05.279106 Established timings supported:
9091 00:23:05.282541 Standard timings supported:
9092 00:23:05.283082 Detailed timings
9093 00:23:05.289313 Hex of detail: 383680a07038204018303c0035ae10000019
9094 00:23:05.292455 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9095 00:23:05.299215 0780 0798 07c8 0820 hborder 0
9096 00:23:05.302177 0438 043b 0447 0458 vborder 0
9097 00:23:05.306420 -hsync -vsync
9098 00:23:05.306940 Did detailed timing
9099 00:23:05.309102 Hex of detail: 000000000000000000000000000000000000
9100 00:23:05.312539 Manufacturer-specified data, tag 0
9101 00:23:05.319047 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9102 00:23:05.319494 ASCII string: InfoVision
9103 00:23:05.325549 Hex of detail: 000000fe00523134304e574635205248200a
9104 00:23:05.329450 ASCII string: R140NWF5 RH
9105 00:23:05.329965 Checksum
9106 00:23:05.330360 Checksum: 0xfb (valid)
9107 00:23:05.335404 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9108 00:23:05.339048 DSI data_rate: 832800000 bps
9109 00:23:05.341989 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9110 00:23:05.349166 anx7625_parse_edid: pixelclock(138800).
9111 00:23:05.352379 hactive(1920), hsync(48), hfp(24), hbp(88)
9112 00:23:05.355616 vactive(1080), vsync(12), vfp(3), vbp(17)
9113 00:23:05.358682 anx7625_dsi_config: config dsi.
9114 00:23:05.365435 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9115 00:23:05.378008 anx7625_dsi_config: success to config DSI
9116 00:23:05.381732 anx7625_dp_start: MIPI phy setup OK.
9117 00:23:05.385082 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9118 00:23:05.388673 mtk_ddp_mode_set invalid vrefresh 60
9119 00:23:05.391551 main_disp_path_setup
9120 00:23:05.392079 ovl_layer_smi_id_en
9121 00:23:05.394440 ovl_layer_smi_id_en
9122 00:23:05.394883 ccorr_config
9123 00:23:05.395231 aal_config
9124 00:23:05.397908 gamma_config
9125 00:23:05.398478 postmask_config
9126 00:23:05.401156 dither_config
9127 00:23:05.405102 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9128 00:23:05.412005 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9129 00:23:05.414758 Root Device init finished in 551 msecs
9130 00:23:05.415294 CPU_CLUSTER: 0 init
9131 00:23:05.424497 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9132 00:23:05.427985 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9133 00:23:05.431218 APU_MBOX 0x190000b0 = 0x10001
9134 00:23:05.434863 APU_MBOX 0x190001b0 = 0x10001
9135 00:23:05.438315 APU_MBOX 0x190005b0 = 0x10001
9136 00:23:05.441534 APU_MBOX 0x190006b0 = 0x10001
9137 00:23:05.444680 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9138 00:23:05.457298 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9139 00:23:05.469717 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9140 00:23:05.476090 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9141 00:23:05.487958 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9142 00:23:05.496848 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9143 00:23:05.500168 CPU_CLUSTER: 0 init finished in 81 msecs
9144 00:23:05.503569 Devices initialized
9145 00:23:05.506921 Show all devs... After init.
9146 00:23:05.507388 Root Device: enabled 1
9147 00:23:05.510024 CPU_CLUSTER: 0: enabled 1
9148 00:23:05.513360 CPU: 00: enabled 1
9149 00:23:05.516660 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9150 00:23:05.519828 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9151 00:23:05.523479 ELOG: NV offset 0x57f000 size 0x1000
9152 00:23:05.530168 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9153 00:23:05.536583 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9154 00:23:05.539786 ELOG: Event(17) added with size 13 at 2024-06-21 00:23:05 UTC
9155 00:23:05.543163 out: cmd=0x121: 03 db 21 01 00 00 00 00
9156 00:23:05.546762 in-header: 03 00 00 00 2c 00 00 00
9157 00:23:05.559765 in-data: 42 6d 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9158 00:23:05.566938 ELOG: Event(A1) added with size 10 at 2024-06-21 00:23:05 UTC
9159 00:23:05.573182 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9160 00:23:05.579810 ELOG: Event(A0) added with size 9 at 2024-06-21 00:23:05 UTC
9161 00:23:05.583539 elog_add_boot_reason: Logged dev mode boot
9162 00:23:05.586768 BS: BS_POST_DEVICE entry times (exec / console): 1 / 64 ms
9163 00:23:05.590396 Finalize devices...
9164 00:23:05.590910 Devices finalized
9165 00:23:05.596841 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9166 00:23:05.599878 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9167 00:23:05.603523 in-header: 03 07 00 00 08 00 00 00
9168 00:23:05.606688 in-data: aa e4 47 04 13 02 00 00
9169 00:23:05.609864 Chrome EC: UHEPI supported
9170 00:23:05.616655 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9171 00:23:05.619706 in-header: 03 a9 00 00 08 00 00 00
9172 00:23:05.622856 in-data: 84 60 60 08 00 00 00 00
9173 00:23:05.626472 ELOG: Event(91) added with size 10 at 2024-06-21 00:23:05 UTC
9174 00:23:05.633533 Chrome EC: clear events_b mask to 0x0000000020004000
9175 00:23:05.640279 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9176 00:23:05.643915 in-header: 03 fd 00 00 00 00 00 00
9177 00:23:05.644443 in-data:
9178 00:23:05.650205 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9179 00:23:05.654120 Writing coreboot table at 0xffe64000
9180 00:23:05.656739 0. 000000000010a000-0000000000113fff: RAMSTAGE
9181 00:23:05.660209 1. 0000000040000000-00000000400fffff: RAM
9182 00:23:05.663544 2. 0000000040100000-000000004032afff: RAMSTAGE
9183 00:23:05.670406 3. 000000004032b000-00000000545fffff: RAM
9184 00:23:05.673516 4. 0000000054600000-000000005465ffff: BL31
9185 00:23:05.677010 5. 0000000054660000-00000000ffe63fff: RAM
9186 00:23:05.680289 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9187 00:23:05.687196 7. 0000000100000000-000000013fffffff: RAM
9188 00:23:05.687712 Passing 5 GPIOs to payload:
9189 00:23:05.693798 NAME | PORT | POLARITY | VALUE
9190 00:23:05.696813 EC in RW | 0x000000aa | low | undefined
9191 00:23:05.703710 EC interrupt | 0x00000005 | low | undefined
9192 00:23:05.706852 TPM interrupt | 0x000000ab | high | undefined
9193 00:23:05.710179 SD card detect | 0x00000011 | high | undefined
9194 00:23:05.716668 speaker enable | 0x00000093 | high | undefined
9195 00:23:05.719979 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9196 00:23:05.723005 in-header: 03 f8 00 00 02 00 00 00
9197 00:23:05.723438 in-data: 03 00
9198 00:23:05.726850 ADC[4]: Raw value=669327 ID=5
9199 00:23:05.729491 ADC[3]: Raw value=212549 ID=1
9200 00:23:05.729922 RAM Code: 0x51
9201 00:23:05.732861 ADC[6]: Raw value=74778 ID=0
9202 00:23:05.736730 ADC[5]: Raw value=211812 ID=1
9203 00:23:05.737202 SKU Code: 0x1
9204 00:23:05.743058 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 1c38
9205 00:23:05.746483 coreboot table: 964 bytes.
9206 00:23:05.750082 IMD ROOT 0. 0xfffff000 0x00001000
9207 00:23:05.753177 IMD SMALL 1. 0xffffe000 0x00001000
9208 00:23:05.756162 RO MCACHE 2. 0xffffc000 0x00001104
9209 00:23:05.760058 CONSOLE 3. 0xfff7c000 0x00080000
9210 00:23:05.763641 FMAP 4. 0xfff7b000 0x00000452
9211 00:23:05.766664 TIME STAMP 5. 0xfff7a000 0x00000910
9212 00:23:05.769779 VBOOT WORK 6. 0xfff66000 0x00014000
9213 00:23:05.772953 RAMOOPS 7. 0xffe66000 0x00100000
9214 00:23:05.776229 COREBOOT 8. 0xffe64000 0x00002000
9215 00:23:05.776670 IMD small region:
9216 00:23:05.779892 IMD ROOT 0. 0xffffec00 0x00000400
9217 00:23:05.783120 VPD 1. 0xffffeb80 0x0000006c
9218 00:23:05.786193 MMC STATUS 2. 0xffffeb60 0x00000004
9219 00:23:05.793262 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9220 00:23:05.799250 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9221 00:23:05.838777 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9222 00:23:05.842190 Checking segment from ROM address 0x40100000
9223 00:23:05.845607 Checking segment from ROM address 0x4010001c
9224 00:23:05.852212 Loading segment from ROM address 0x40100000
9225 00:23:05.852732 code (compression=0)
9226 00:23:05.862248 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9227 00:23:05.868734 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9228 00:23:05.869255 it's not compressed!
9229 00:23:05.875124 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9230 00:23:05.881935 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9231 00:23:05.899152 Loading segment from ROM address 0x4010001c
9232 00:23:05.899670 Entry Point 0x80000000
9233 00:23:05.903009 Loaded segments
9234 00:23:05.906444 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9235 00:23:05.912918 Jumping to boot code at 0x80000000(0xffe64000)
9236 00:23:05.919488 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9237 00:23:05.925817 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9238 00:23:05.933598 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9239 00:23:05.937278 Checking segment from ROM address 0x40100000
9240 00:23:05.940287 Checking segment from ROM address 0x4010001c
9241 00:23:05.947080 Loading segment from ROM address 0x40100000
9242 00:23:05.947600 code (compression=1)
9243 00:23:05.953953 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9244 00:23:05.963685 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9245 00:23:05.964209 using LZMA
9246 00:23:05.971901 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9247 00:23:05.978835 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9248 00:23:05.982738 Loading segment from ROM address 0x4010001c
9249 00:23:05.983185 Entry Point 0x54601000
9250 00:23:05.985205 Loaded segments
9251 00:23:05.988604 NOTICE: MT8192 bl31_setup
9252 00:23:05.996064 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9253 00:23:05.999177 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9254 00:23:06.002360 WARNING: region 0:
9255 00:23:06.005649 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9256 00:23:06.006089 WARNING: region 1:
9257 00:23:06.012266 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9258 00:23:06.015392 WARNING: region 2:
9259 00:23:06.018959 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9260 00:23:06.022098 WARNING: region 3:
9261 00:23:06.025579 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9262 00:23:06.029222 WARNING: region 4:
9263 00:23:06.035364 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9264 00:23:06.035915 WARNING: region 5:
9265 00:23:06.038768 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9266 00:23:06.042502 WARNING: region 6:
9267 00:23:06.045491 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9268 00:23:06.049085 WARNING: region 7:
9269 00:23:06.052305 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9270 00:23:06.058486 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9271 00:23:06.062141 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9272 00:23:06.065193 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9273 00:23:06.072402 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9274 00:23:06.075920 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9275 00:23:06.078768 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9276 00:23:06.085425 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9277 00:23:06.088273 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9278 00:23:06.095468 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9279 00:23:06.098523 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9280 00:23:06.101911 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9281 00:23:06.108749 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9282 00:23:06.111658 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9283 00:23:06.118556 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9284 00:23:06.121652 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9285 00:23:06.124661 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9286 00:23:06.131462 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9287 00:23:06.134778 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9288 00:23:06.138148 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9289 00:23:06.145258 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9290 00:23:06.148316 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9291 00:23:06.155176 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9292 00:23:06.157972 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9293 00:23:06.161386 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9294 00:23:06.168109 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9295 00:23:06.171290 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9296 00:23:06.178448 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9297 00:23:06.181244 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9298 00:23:06.185028 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9299 00:23:06.191485 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9300 00:23:06.194687 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9301 00:23:06.201091 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9302 00:23:06.204513 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9303 00:23:06.207749 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9304 00:23:06.211020 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9305 00:23:06.217599 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9306 00:23:06.221335 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9307 00:23:06.224560 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9308 00:23:06.227522 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9309 00:23:06.234480 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9310 00:23:06.237836 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9311 00:23:06.241016 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9312 00:23:06.244968 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9313 00:23:06.251072 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9314 00:23:06.254333 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9315 00:23:06.257695 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9316 00:23:06.260738 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9317 00:23:06.267788 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9318 00:23:06.271065 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9319 00:23:06.277605 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9320 00:23:06.280985 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9321 00:23:06.284040 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9322 00:23:06.291202 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9323 00:23:06.293879 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9324 00:23:06.300724 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9325 00:23:06.304265 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9326 00:23:06.310815 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9327 00:23:06.313918 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9328 00:23:06.317148 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9329 00:23:06.324108 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9330 00:23:06.327580 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9331 00:23:06.334101 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9332 00:23:06.337222 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9333 00:23:06.343856 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9334 00:23:06.347249 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9335 00:23:06.353871 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9336 00:23:06.357375 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9337 00:23:06.360930 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9338 00:23:06.367388 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9339 00:23:06.370730 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9340 00:23:06.377732 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9341 00:23:06.380510 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9342 00:23:06.384024 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9343 00:23:06.390547 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9344 00:23:06.394484 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9345 00:23:06.400571 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9346 00:23:06.403790 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9347 00:23:06.410810 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9348 00:23:06.414751 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9349 00:23:06.420673 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9350 00:23:06.424014 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9351 00:23:06.427217 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9352 00:23:06.434199 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9353 00:23:06.437379 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9354 00:23:06.443852 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9355 00:23:06.447161 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9356 00:23:06.453877 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9357 00:23:06.457398 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9358 00:23:06.460595 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9359 00:23:06.467542 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9360 00:23:06.470330 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9361 00:23:06.477081 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9362 00:23:06.480011 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9363 00:23:06.486848 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9364 00:23:06.490121 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9365 00:23:06.496772 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9366 00:23:06.500229 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9367 00:23:06.503711 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9368 00:23:06.507150 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9369 00:23:06.513629 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9370 00:23:06.516855 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9371 00:23:06.520106 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9372 00:23:06.526791 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9373 00:23:06.529887 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9374 00:23:06.536533 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9375 00:23:06.540113 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9376 00:23:06.543181 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9377 00:23:06.550599 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9378 00:23:06.553376 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9379 00:23:06.559789 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9380 00:23:06.563729 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9381 00:23:06.566822 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9382 00:23:06.573854 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9383 00:23:06.576337 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9384 00:23:06.583267 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9385 00:23:06.586184 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9386 00:23:06.589905 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9387 00:23:06.592951 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9388 00:23:06.599847 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9389 00:23:06.602840 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9390 00:23:06.606663 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9391 00:23:06.613090 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9392 00:23:06.617015 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9393 00:23:06.619736 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9394 00:23:06.622937 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9395 00:23:06.629688 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9396 00:23:06.632904 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9397 00:23:06.639746 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9398 00:23:06.642995 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9399 00:23:06.646698 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9400 00:23:06.653115 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9401 00:23:06.656327 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9402 00:23:06.663425 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9403 00:23:06.666169 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9404 00:23:06.669748 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9405 00:23:06.676060 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9406 00:23:06.679432 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9407 00:23:06.682850 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9408 00:23:06.689266 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9409 00:23:06.692868 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9410 00:23:06.699743 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9411 00:23:06.702818 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9412 00:23:06.706478 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9413 00:23:06.713240 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9414 00:23:06.716606 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9415 00:23:06.722882 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9416 00:23:06.726574 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9417 00:23:06.730004 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9418 00:23:06.736273 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9419 00:23:06.739770 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9420 00:23:06.746498 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9421 00:23:06.749661 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9422 00:23:06.753134 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9423 00:23:06.759542 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9424 00:23:06.762921 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9425 00:23:06.766352 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9426 00:23:06.773011 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9427 00:23:06.776372 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9428 00:23:06.782850 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9429 00:23:06.786340 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9430 00:23:06.790186 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9431 00:23:06.796218 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9432 00:23:06.799603 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9433 00:23:06.806400 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9434 00:23:06.809715 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9435 00:23:06.813053 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9436 00:23:06.819126 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9437 00:23:06.822848 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9438 00:23:06.826417 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9439 00:23:06.832776 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9440 00:23:06.836201 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9441 00:23:06.842574 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9442 00:23:06.845957 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9443 00:23:06.849657 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9444 00:23:06.856163 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9445 00:23:06.859283 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9446 00:23:06.866459 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9447 00:23:06.869508 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9448 00:23:06.873111 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9449 00:23:06.880145 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9450 00:23:06.882477 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9451 00:23:06.886402 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9452 00:23:06.892954 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9453 00:23:06.896214 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9454 00:23:06.902535 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9455 00:23:06.905856 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9456 00:23:06.908769 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9457 00:23:06.915438 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9458 00:23:06.918977 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9459 00:23:06.925429 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9460 00:23:06.929157 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9461 00:23:06.935948 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9462 00:23:06.938912 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9463 00:23:06.942560 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9464 00:23:06.948960 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9465 00:23:06.952625 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9466 00:23:06.959498 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9467 00:23:06.962458 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9468 00:23:06.965485 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9469 00:23:06.972143 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9470 00:23:06.975386 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9471 00:23:06.981974 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9472 00:23:06.985531 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9473 00:23:06.992003 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9474 00:23:06.995497 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9475 00:23:06.998755 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9476 00:23:07.005615 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9477 00:23:07.009094 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9478 00:23:07.015189 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9479 00:23:07.018353 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9480 00:23:07.025395 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9481 00:23:07.028395 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9482 00:23:07.031839 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9483 00:23:07.038855 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9484 00:23:07.042137 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9485 00:23:07.048539 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9486 00:23:07.052052 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9487 00:23:07.055952 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9488 00:23:07.062351 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9489 00:23:07.065242 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9490 00:23:07.072420 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9491 00:23:07.075652 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9492 00:23:07.078703 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9493 00:23:07.085133 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9494 00:23:07.088754 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9495 00:23:07.095354 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9496 00:23:07.098553 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9497 00:23:07.105948 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9498 00:23:07.108636 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9499 00:23:07.111713 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9500 00:23:07.114935 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9501 00:23:07.121717 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9502 00:23:07.125116 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9503 00:23:07.128746 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9504 00:23:07.132093 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9505 00:23:07.138495 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9506 00:23:07.141625 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9507 00:23:07.148314 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9508 00:23:07.151894 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9509 00:23:07.154846 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9510 00:23:07.161810 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9511 00:23:07.165088 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9512 00:23:07.168663 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9513 00:23:07.174909 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9514 00:23:07.178366 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9515 00:23:07.181767 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9516 00:23:07.188475 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9517 00:23:07.191524 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9518 00:23:07.195147 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9519 00:23:07.201649 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9520 00:23:07.204825 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9521 00:23:07.212150 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9522 00:23:07.214920 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9523 00:23:07.218623 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9524 00:23:07.224972 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9525 00:23:07.228126 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9526 00:23:07.231670 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9527 00:23:07.237902 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9528 00:23:07.242256 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9529 00:23:07.244989 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9530 00:23:07.251455 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9531 00:23:07.254810 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9532 00:23:07.262012 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9533 00:23:07.264901 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9534 00:23:07.267965 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9535 00:23:07.274633 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9536 00:23:07.277824 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9537 00:23:07.281934 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9538 00:23:07.288322 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9539 00:23:07.291535 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9540 00:23:07.294406 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9541 00:23:07.298046 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9542 00:23:07.304848 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9543 00:23:07.308383 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9544 00:23:07.311344 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9545 00:23:07.314886 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9546 00:23:07.321679 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9547 00:23:07.324534 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9548 00:23:07.327851 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9549 00:23:07.331251 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9550 00:23:07.337933 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9551 00:23:07.341230 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9552 00:23:07.345111 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9553 00:23:07.350956 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9554 00:23:07.355136 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9555 00:23:07.361352 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9556 00:23:07.364719 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9557 00:23:07.368105 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9558 00:23:07.375080 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9559 00:23:07.377738 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9560 00:23:07.384424 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9561 00:23:07.387737 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9562 00:23:07.391563 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9563 00:23:07.397922 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9564 00:23:07.401215 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9565 00:23:07.407525 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9566 00:23:07.411080 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9567 00:23:07.414354 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9568 00:23:07.421565 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9569 00:23:07.424508 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9570 00:23:07.430958 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9571 00:23:07.434280 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9572 00:23:07.437530 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9573 00:23:07.445015 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9574 00:23:07.447908 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9575 00:23:07.454357 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9576 00:23:07.457604 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9577 00:23:07.461263 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9578 00:23:07.467743 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9579 00:23:07.471278 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9580 00:23:07.477900 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9581 00:23:07.481178 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9582 00:23:07.487427 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9583 00:23:07.490892 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9584 00:23:07.494157 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9585 00:23:07.501035 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9586 00:23:07.504342 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9587 00:23:07.507806 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9588 00:23:07.514294 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9589 00:23:07.517747 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9590 00:23:07.524459 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9591 00:23:07.527943 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9592 00:23:07.530843 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9593 00:23:07.537473 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9594 00:23:07.540950 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9595 00:23:07.547221 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9596 00:23:07.550820 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9597 00:23:07.557437 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9598 00:23:07.560708 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9599 00:23:07.564011 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9600 00:23:07.570707 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9601 00:23:07.574131 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9602 00:23:07.580633 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9603 00:23:07.583768 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9604 00:23:07.590295 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9605 00:23:07.594071 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9606 00:23:07.596922 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9607 00:23:07.603263 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9608 00:23:07.606886 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9609 00:23:07.613279 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9610 00:23:07.616896 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9611 00:23:07.620158 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9612 00:23:07.627180 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9613 00:23:07.629788 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9614 00:23:07.636439 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9615 00:23:07.639916 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9616 00:23:07.643398 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9617 00:23:07.649823 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9618 00:23:07.653548 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9619 00:23:07.660124 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9620 00:23:07.663134 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9621 00:23:07.669794 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9622 00:23:07.673402 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9623 00:23:07.676288 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9624 00:23:07.683157 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9625 00:23:07.686409 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9626 00:23:07.693357 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9627 00:23:07.696869 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9628 00:23:07.699697 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9629 00:23:07.706572 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9630 00:23:07.709581 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9631 00:23:07.717255 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9632 00:23:07.719645 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9633 00:23:07.726313 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9634 00:23:07.730019 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9635 00:23:07.733181 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9636 00:23:07.739383 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9637 00:23:07.742834 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9638 00:23:07.750294 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9639 00:23:07.752835 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9640 00:23:07.759879 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9641 00:23:07.762887 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9642 00:23:07.769796 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9643 00:23:07.772991 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9644 00:23:07.776311 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9645 00:23:07.782811 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9646 00:23:07.786092 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9647 00:23:07.792734 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9648 00:23:07.796332 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9649 00:23:07.802533 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9650 00:23:07.806482 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9651 00:23:07.809497 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9652 00:23:07.816124 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9653 00:23:07.819388 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9654 00:23:07.826053 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9655 00:23:07.829594 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9656 00:23:07.835491 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9657 00:23:07.839317 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9658 00:23:07.845798 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9659 00:23:07.848984 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9660 00:23:07.852291 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9661 00:23:07.858890 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9662 00:23:07.862184 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9663 00:23:07.868912 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9664 00:23:07.872580 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9665 00:23:07.878919 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9666 00:23:07.882765 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9667 00:23:07.885819 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9668 00:23:07.892400 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9669 00:23:07.895668 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9670 00:23:07.902630 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9671 00:23:07.905310 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9672 00:23:07.908917 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9673 00:23:07.915483 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9674 00:23:07.918677 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9675 00:23:07.925756 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9676 00:23:07.928724 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9677 00:23:07.935163 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9678 00:23:07.938410 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9679 00:23:07.945152 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9680 00:23:07.948739 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9681 00:23:07.955402 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9682 00:23:07.959231 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9683 00:23:07.965073 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9684 00:23:07.968950 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9685 00:23:07.975486 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9686 00:23:07.978672 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9687 00:23:07.985047 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9688 00:23:07.988351 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9689 00:23:07.991793 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9690 00:23:07.998763 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9691 00:23:08.001849 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9692 00:23:08.008785 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9693 00:23:08.011974 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9694 00:23:08.018504 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9695 00:23:08.022010 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9696 00:23:08.028145 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9697 00:23:08.031680 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9698 00:23:08.038793 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9699 00:23:08.041538 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9700 00:23:08.048357 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9701 00:23:08.051934 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9702 00:23:08.058674 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9703 00:23:08.061809 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9704 00:23:08.068300 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9705 00:23:08.068756 INFO: [APUAPC] vio 0
9706 00:23:08.075395 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9707 00:23:08.078888 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9708 00:23:08.082148 INFO: [APUAPC] D0_APC_0: 0x400510
9709 00:23:08.085758 INFO: [APUAPC] D0_APC_1: 0x0
9710 00:23:08.088627 INFO: [APUAPC] D0_APC_2: 0x1540
9711 00:23:08.091954 INFO: [APUAPC] D0_APC_3: 0x0
9712 00:23:08.095581 INFO: [APUAPC] D1_APC_0: 0xffffffff
9713 00:23:08.098714 INFO: [APUAPC] D1_APC_1: 0xffffffff
9714 00:23:08.102023 INFO: [APUAPC] D1_APC_2: 0x3fffff
9715 00:23:08.105679 INFO: [APUAPC] D1_APC_3: 0x0
9716 00:23:08.108608 INFO: [APUAPC] D2_APC_0: 0xffffffff
9717 00:23:08.112217 INFO: [APUAPC] D2_APC_1: 0xffffffff
9718 00:23:08.115770 INFO: [APUAPC] D2_APC_2: 0x3fffff
9719 00:23:08.118780 INFO: [APUAPC] D2_APC_3: 0x0
9720 00:23:08.121873 INFO: [APUAPC] D3_APC_0: 0xffffffff
9721 00:23:08.125204 INFO: [APUAPC] D3_APC_1: 0xffffffff
9722 00:23:08.128328 INFO: [APUAPC] D3_APC_2: 0x3fffff
9723 00:23:08.132762 INFO: [APUAPC] D3_APC_3: 0x0
9724 00:23:08.136017 INFO: [APUAPC] D4_APC_0: 0xffffffff
9725 00:23:08.138517 INFO: [APUAPC] D4_APC_1: 0xffffffff
9726 00:23:08.142058 INFO: [APUAPC] D4_APC_2: 0x3fffff
9727 00:23:08.142554 INFO: [APUAPC] D4_APC_3: 0x0
9728 00:23:08.145067 INFO: [APUAPC] D5_APC_0: 0xffffffff
9729 00:23:08.151758 INFO: [APUAPC] D5_APC_1: 0xffffffff
9730 00:23:08.152293 INFO: [APUAPC] D5_APC_2: 0x3fffff
9731 00:23:08.155090 INFO: [APUAPC] D5_APC_3: 0x0
9732 00:23:08.158284 INFO: [APUAPC] D6_APC_0: 0xffffffff
9733 00:23:08.161731 INFO: [APUAPC] D6_APC_1: 0xffffffff
9734 00:23:08.165078 INFO: [APUAPC] D6_APC_2: 0x3fffff
9735 00:23:08.168619 INFO: [APUAPC] D6_APC_3: 0x0
9736 00:23:08.171739 INFO: [APUAPC] D7_APC_0: 0xffffffff
9737 00:23:08.175255 INFO: [APUAPC] D7_APC_1: 0xffffffff
9738 00:23:08.178160 INFO: [APUAPC] D7_APC_2: 0x3fffff
9739 00:23:08.181760 INFO: [APUAPC] D7_APC_3: 0x0
9740 00:23:08.184832 INFO: [APUAPC] D8_APC_0: 0xffffffff
9741 00:23:08.188495 INFO: [APUAPC] D8_APC_1: 0xffffffff
9742 00:23:08.191694 INFO: [APUAPC] D8_APC_2: 0x3fffff
9743 00:23:08.195027 INFO: [APUAPC] D8_APC_3: 0x0
9744 00:23:08.198402 INFO: [APUAPC] D9_APC_0: 0xffffffff
9745 00:23:08.201470 INFO: [APUAPC] D9_APC_1: 0xffffffff
9746 00:23:08.204605 INFO: [APUAPC] D9_APC_2: 0x3fffff
9747 00:23:08.207953 INFO: [APUAPC] D9_APC_3: 0x0
9748 00:23:08.211429 INFO: [APUAPC] D10_APC_0: 0xffffffff
9749 00:23:08.214833 INFO: [APUAPC] D10_APC_1: 0xffffffff
9750 00:23:08.218086 INFO: [APUAPC] D10_APC_2: 0x3fffff
9751 00:23:08.221165 INFO: [APUAPC] D10_APC_3: 0x0
9752 00:23:08.224577 INFO: [APUAPC] D11_APC_0: 0xffffffff
9753 00:23:08.228257 INFO: [APUAPC] D11_APC_1: 0xffffffff
9754 00:23:08.231876 INFO: [APUAPC] D11_APC_2: 0x3fffff
9755 00:23:08.234864 INFO: [APUAPC] D11_APC_3: 0x0
9756 00:23:08.237971 INFO: [APUAPC] D12_APC_0: 0xffffffff
9757 00:23:08.241099 INFO: [APUAPC] D12_APC_1: 0xffffffff
9758 00:23:08.245443 INFO: [APUAPC] D12_APC_2: 0x3fffff
9759 00:23:08.248149 INFO: [APUAPC] D12_APC_3: 0x0
9760 00:23:08.251715 INFO: [APUAPC] D13_APC_0: 0xffffffff
9761 00:23:08.254639 INFO: [APUAPC] D13_APC_1: 0xffffffff
9762 00:23:08.257828 INFO: [APUAPC] D13_APC_2: 0x3fffff
9763 00:23:08.261294 INFO: [APUAPC] D13_APC_3: 0x0
9764 00:23:08.264555 INFO: [APUAPC] D14_APC_0: 0xffffffff
9765 00:23:08.268276 INFO: [APUAPC] D14_APC_1: 0xffffffff
9766 00:23:08.271071 INFO: [APUAPC] D14_APC_2: 0x3fffff
9767 00:23:08.274402 INFO: [APUAPC] D14_APC_3: 0x0
9768 00:23:08.277781 INFO: [APUAPC] D15_APC_0: 0xffffffff
9769 00:23:08.281142 INFO: [APUAPC] D15_APC_1: 0xffffffff
9770 00:23:08.284569 INFO: [APUAPC] D15_APC_2: 0x3fffff
9771 00:23:08.287857 INFO: [APUAPC] D15_APC_3: 0x0
9772 00:23:08.290893 INFO: [APUAPC] APC_CON: 0x4
9773 00:23:08.294402 INFO: [NOCDAPC] D0_APC_0: 0x0
9774 00:23:08.297949 INFO: [NOCDAPC] D0_APC_1: 0x0
9775 00:23:08.301111 INFO: [NOCDAPC] D1_APC_0: 0x0
9776 00:23:08.304282 INFO: [NOCDAPC] D1_APC_1: 0xfff
9777 00:23:08.304725 INFO: [NOCDAPC] D2_APC_0: 0x0
9778 00:23:08.307828 INFO: [NOCDAPC] D2_APC_1: 0xfff
9779 00:23:08.310909 INFO: [NOCDAPC] D3_APC_0: 0x0
9780 00:23:08.314277 INFO: [NOCDAPC] D3_APC_1: 0xfff
9781 00:23:08.317564 INFO: [NOCDAPC] D4_APC_0: 0x0
9782 00:23:08.321302 INFO: [NOCDAPC] D4_APC_1: 0xfff
9783 00:23:08.324430 INFO: [NOCDAPC] D5_APC_0: 0x0
9784 00:23:08.327622 INFO: [NOCDAPC] D5_APC_1: 0xfff
9785 00:23:08.331019 INFO: [NOCDAPC] D6_APC_0: 0x0
9786 00:23:08.334444 INFO: [NOCDAPC] D6_APC_1: 0xfff
9787 00:23:08.337813 INFO: [NOCDAPC] D7_APC_0: 0x0
9788 00:23:08.338291 INFO: [NOCDAPC] D7_APC_1: 0xfff
9789 00:23:08.340844 INFO: [NOCDAPC] D8_APC_0: 0x0
9790 00:23:08.344485 INFO: [NOCDAPC] D8_APC_1: 0xfff
9791 00:23:08.347171 INFO: [NOCDAPC] D9_APC_0: 0x0
9792 00:23:08.350519 INFO: [NOCDAPC] D9_APC_1: 0xfff
9793 00:23:08.354029 INFO: [NOCDAPC] D10_APC_0: 0x0
9794 00:23:08.358245 INFO: [NOCDAPC] D10_APC_1: 0xfff
9795 00:23:08.360762 INFO: [NOCDAPC] D11_APC_0: 0x0
9796 00:23:08.364430 INFO: [NOCDAPC] D11_APC_1: 0xfff
9797 00:23:08.371452 INFO: [NOCDAPC] D12_APC_0: 0x0
9798 00:23:08.371615 INFO: [NOCDAPC] D12_APC_1: 0xfff
9799 00:23:08.374255 INFO: [NOCDAPC] D13_APC_0: 0x0
9800 00:23:08.377202 INFO: [NOCDAPC] D13_APC_1: 0xfff
9801 00:23:08.377344 INFO: [NOCDAPC] D14_APC_0: 0x0
9802 00:23:08.380698 INFO: [NOCDAPC] D14_APC_1: 0xfff
9803 00:23:08.384650 INFO: [NOCDAPC] D15_APC_0: 0x0
9804 00:23:08.387406 INFO: [NOCDAPC] D15_APC_1: 0xfff
9805 00:23:08.390954 INFO: [NOCDAPC] APC_CON: 0x4
9806 00:23:08.393788 INFO: [APUAPC] set_apusys_apc done
9807 00:23:08.397549 INFO: [DEVAPC] devapc_init done
9808 00:23:08.400673 INFO: GICv3 without legacy support detected.
9809 00:23:08.407638 INFO: ARM GICv3 driver initialized in EL3
9810 00:23:08.410542 INFO: Maximum SPI INTID supported: 639
9811 00:23:08.414164 INFO: BL31: Initializing runtime services
9812 00:23:08.420805 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9813 00:23:08.421414 INFO: SPM: enable CPC mode
9814 00:23:08.427383 INFO: mcdi ready for mcusys-off-idle and system suspend
9815 00:23:08.430929 INFO: BL31: Preparing for EL3 exit to normal world
9816 00:23:08.437314 INFO: Entry point address = 0x80000000
9817 00:23:08.437843 INFO: SPSR = 0x8
9818 00:23:08.443418
9819 00:23:08.443929
9820 00:23:08.444270
9821 00:23:08.446600 Starting depthcharge on Spherion...
9822 00:23:08.447041
9823 00:23:08.447389 Wipe memory regions:
9824 00:23:08.447711
9825 00:23:08.450147 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
9826 00:23:08.450723 start: 2.2.4 bootloader-commands (timeout 00:04:21) [common]
9827 00:23:08.451147 Setting prompt string to ['asurada:']
9828 00:23:08.451552 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:21)
9829 00:23:08.452210 [0x00000040000000, 0x00000054600000)
9830 00:23:08.572197
9831 00:23:08.572720 [0x00000054660000, 0x00000080000000)
9832 00:23:08.832794
9833 00:23:08.833408 [0x000000821a7280, 0x000000ffe64000)
9834 00:23:09.577970
9835 00:23:09.578530 [0x00000100000000, 0x00000140000000)
9836 00:23:09.959029
9837 00:23:09.962379 Initializing XHCI USB controller at 0x11200000.
9838 00:23:11.000779
9839 00:23:11.003943 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9840 00:23:11.004386
9841 00:23:11.004731
9842 00:23:11.005468 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9844 00:23:11.106960 asurada: tftpboot 192.168.201.1 14479179/tftp-deploy-4yfo8uu6/kernel/image.itb 14479179/tftp-deploy-4yfo8uu6/kernel/cmdline
9845 00:23:11.107790 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9846 00:23:11.108206 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:19)
9847 00:23:11.112856 tftpboot 192.168.201.1 14479179/tftp-deploy-4yfo8uu6/kernel/image.itp-deploy-4yfo8uu6/kernel/cmdline
9848 00:23:11.113300
9849 00:23:11.113640 Waiting for link
9850 00:23:11.270599
9851 00:23:11.271132 R8152: Initializing
9852 00:23:11.271485
9853 00:23:11.274838 Version 9 (ocp_data = 6010)
9854 00:23:11.275353
9855 00:23:11.277319 R8152: Done initializing
9856 00:23:11.277829
9857 00:23:11.278175 Adding net device
9858 00:23:13.288234
9859 00:23:13.288765 done.
9860 00:23:13.289115
9861 00:23:13.289433 MAC: 00:e0:4c:68:03:bd
9862 00:23:13.289737
9863 00:23:13.291600 Sending DHCP discover... done.
9864 00:23:13.292033
9865 00:23:13.294446 Waiting for reply... done.
9866 00:23:13.294883
9867 00:23:13.298130 Sending DHCP request... done.
9868 00:23:13.298602
9869 00:23:13.298942 Waiting for reply... done.
9870 00:23:13.301491
9871 00:23:13.301918 My ip is 192.168.201.16
9872 00:23:13.302307
9873 00:23:13.304572 The DHCP server ip is 192.168.201.1
9874 00:23:13.305005
9875 00:23:13.307707 TFTP server IP predefined by user: 192.168.201.1
9876 00:23:13.308206
9877 00:23:13.314766 Bootfile predefined by user: 14479179/tftp-deploy-4yfo8uu6/kernel/image.itb
9878 00:23:13.315266
9879 00:23:13.317608 Sending tftp read request... done.
9880 00:23:13.318148
9881 00:23:13.327739 Waiting for the transfer...
9882 00:23:13.328299
9883 00:23:13.622138 00000000 ################################################################
9884 00:23:13.622289
9885 00:23:13.872596 00080000 ################################################################
9886 00:23:13.872751
9887 00:23:14.135710 00100000 ################################################################
9888 00:23:14.135834
9889 00:23:14.393923 00180000 ################################################################
9890 00:23:14.394055
9891 00:23:14.677236 00200000 ################################################################
9892 00:23:14.677360
9893 00:23:14.935441 00280000 ################################################################
9894 00:23:14.935567
9895 00:23:15.185219 00300000 ################################################################
9896 00:23:15.185368
9897 00:23:15.455924 00380000 ################################################################
9898 00:23:15.456078
9899 00:23:15.722707 00400000 ################################################################
9900 00:23:15.722850
9901 00:23:15.985014 00480000 ################################################################
9902 00:23:15.985164
9903 00:23:16.245166 00500000 ################################################################
9904 00:23:16.245315
9905 00:23:16.511589 00580000 ################################################################
9906 00:23:16.511744
9907 00:23:16.779068 00600000 ################################################################
9908 00:23:16.779193
9909 00:23:17.048687 00680000 ################################################################
9910 00:23:17.048816
9911 00:23:17.300774 00700000 ################################################################
9912 00:23:17.300901
9913 00:23:17.565044 00780000 ################################################################
9914 00:23:17.565174
9915 00:23:17.825986 00800000 ################################################################
9916 00:23:17.826111
9917 00:23:18.110964 00880000 ################################################################
9918 00:23:18.111089
9919 00:23:18.391321 00900000 ################################################################
9920 00:23:18.391447
9921 00:23:18.671526 00980000 ################################################################
9922 00:23:18.671679
9923 00:23:18.921971 00a00000 ################################################################
9924 00:23:18.922114
9925 00:23:19.174891 00a80000 ################################################################
9926 00:23:19.175017
9927 00:23:19.440100 00b00000 ################################################################
9928 00:23:19.440222
9929 00:23:19.689725 00b80000 ################################################################
9930 00:23:19.689875
9931 00:23:19.955409 00c00000 ################################################################
9932 00:23:19.955528
9933 00:23:20.248162 00c80000 ################################################################
9934 00:23:20.248287
9935 00:23:20.526965 00d00000 ################################################################
9936 00:23:20.527108
9937 00:23:20.792438 00d80000 ################################################################
9938 00:23:20.792599
9939 00:23:21.062125 00e00000 ################################################################
9940 00:23:21.062281
9941 00:23:21.322536 00e80000 ################################################################
9942 00:23:21.322680
9943 00:23:21.600406 00f00000 ################################################################
9944 00:23:21.600555
9945 00:23:21.874674 00f80000 ################################################################
9946 00:23:21.874832
9947 00:23:22.137472 01000000 ################################################################
9948 00:23:22.137640
9949 00:23:22.417026 01080000 ################################################################
9950 00:23:22.417148
9951 00:23:22.686832 01100000 ################################################################
9952 00:23:22.686975
9953 00:23:22.952628 01180000 ################################################################
9954 00:23:22.952778
9955 00:23:23.201223 01200000 ################################################################
9956 00:23:23.201386
9957 00:23:23.457166 01280000 ################################################################
9958 00:23:23.457313
9959 00:23:23.725615 01300000 ################################################################
9960 00:23:23.725758
9961 00:23:23.975685 01380000 ################################################################
9962 00:23:23.975803
9963 00:23:24.245693 01400000 ################################################################
9964 00:23:24.245814
9965 00:23:24.518478 01480000 ################################################################
9966 00:23:24.518608
9967 00:23:24.801668 01500000 ################################################################
9968 00:23:24.801810
9969 00:23:25.090167 01580000 ################################################################
9970 00:23:25.090306
9971 00:23:25.384881 01600000 ################################################################
9972 00:23:25.385001
9973 00:23:25.659687 01680000 ################################################################
9974 00:23:25.659818
9975 00:23:25.955796 01700000 ################################################################
9976 00:23:25.955918
9977 00:23:26.224501 01780000 ################################################################
9978 00:23:26.224627
9979 00:23:26.475963 01800000 ################################################################
9980 00:23:26.476088
9981 00:23:26.754392 01880000 ################################################################
9982 00:23:26.754523
9983 00:23:27.017954 01900000 ################################################################
9984 00:23:27.018078
9985 00:23:27.302352 01980000 ################################################################
9986 00:23:27.302477
9987 00:23:27.599328 01a00000 ################################################################
9988 00:23:27.599453
9989 00:23:27.870734 01a80000 ################################################################
9990 00:23:27.870864
9991 00:23:28.141685 01b00000 ################################################################
9992 00:23:28.141819
9993 00:23:28.406247 01b80000 ################################################################
9994 00:23:28.406393
9995 00:23:28.683420 01c00000 ################################################################
9996 00:23:28.683547
9997 00:23:28.941416 01c80000 ################################################################
9998 00:23:28.941540
9999 00:23:29.213099 01d00000 ################################################################
10000 00:23:29.213227
10001 00:23:29.465475 01d80000 ################################################################
10002 00:23:29.465602
10003 00:23:29.696488 01e00000 ######################################################### done.
10004 00:23:29.696605
10005 00:23:29.699649 The bootfile was 31920154 bytes long.
10006 00:23:29.699727
10007 00:23:29.703207 Sending tftp read request... done.
10008 00:23:29.703291
10009 00:23:29.706510 Waiting for the transfer...
10010 00:23:29.706600
10011 00:23:29.706706 00000000 # done.
10012 00:23:29.709618
10013 00:23:29.716820 Command line loaded dynamically from TFTP file: 14479179/tftp-deploy-4yfo8uu6/kernel/cmdline
10014 00:23:29.716992
10015 00:23:29.739798 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14479179/extract-nfsrootfs-6gqy51jo,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10016 00:23:29.740041
10017 00:23:29.740175 Loading FIT.
10018 00:23:29.740291
10019 00:23:29.743173 Image ramdisk-1 has 18745975 bytes.
10020 00:23:29.743425
10021 00:23:29.746400 Image fdt-1 has 47258 bytes.
10022 00:23:29.746616
10023 00:23:29.749673 Image kernel-1 has 13124896 bytes.
10024 00:23:29.749882
10025 00:23:29.756576 Compat preference: google,spherion-rev3-sku1 google,spherion-rev3 google,spherion-sku1 google,spherion
10026 00:23:29.757003
10027 00:23:29.776400 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 (match) google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10028 00:23:29.776914
10029 00:23:29.779530 Choosing best match conf-1 for compat google,spherion-rev3.
10030 00:23:29.784776
10031 00:23:29.789208 Connected to device vid:did:rid of 1ae0:0028:00
10032 00:23:29.796334
10033 00:23:29.799427 tpm_get_response: command 0x17b, return code 0x0
10034 00:23:29.799866
10035 00:23:29.803069 ec_init: CrosEC protocol v3 supported (256, 248)
10036 00:23:29.806870
10037 00:23:29.810695 tpm_cleanup: add release locality here.
10038 00:23:29.811142
10039 00:23:29.811577 Shutting down all USB controllers.
10040 00:23:29.813581
10041 00:23:29.814041 Removing current net device
10042 00:23:29.814526
10043 00:23:29.820718 Exiting depthcharge with code 4 at timestamp: 49638533
10044 00:23:29.821250
10045 00:23:29.824044 LZMA decompressing kernel-1 to 0x821a6718
10046 00:23:29.824579
10047 00:23:29.827687 LZMA decompressing kernel-1 to 0x40000000
10048 00:23:31.442765
10049 00:23:31.443284 jumping to kernel
10050 00:23:31.445090 end: 2.2.4 bootloader-commands (duration 00:00:23) [common]
10051 00:23:31.445638 start: 2.2.5 auto-login-action (timeout 00:03:58) [common]
10052 00:23:31.446059 Setting prompt string to ['Linux version [0-9]']
10053 00:23:31.446565 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10054 00:23:31.447070 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10055 00:23:31.493741
10056 00:23:31.496699 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10057 00:23:31.500436 start: 2.2.5.1 login-action (timeout 00:03:58) [common]
10058 00:23:31.501055 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10059 00:23:31.501492 Setting prompt string to []
10060 00:23:31.502002 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10061 00:23:31.502591 Using line separator: #'\n'#
10062 00:23:31.502990 No login prompt set.
10063 00:23:31.503443 Parsing kernel messages
10064 00:23:31.503831 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10065 00:23:31.504450 [login-action] Waiting for messages, (timeout 00:03:58)
10066 00:23:31.504871 Waiting using forced prompt support (timeout 00:01:59)
10067 00:23:31.519472 [ 0.000000] Linux version 6.1.94-cip23 (KernelCI@build-j239242-arm64-gcc-10-defconfig-arm64-chromebook-c5lwc) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Jun 21 00:04:56 UTC 2024
10068 00:23:31.522871 [ 0.000000] random: crng init done
10069 00:23:31.529657 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10070 00:23:31.532695 [ 0.000000] efi: UEFI not found.
10071 00:23:31.539517 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10072 00:23:31.546021 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10073 00:23:31.556093 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10074 00:23:31.566010 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10075 00:23:31.572944 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10076 00:23:31.579237 [ 0.000000] printk: bootconsole [mtk8250] enabled
10077 00:23:31.585790 [ 0.000000] NUMA: No NUMA configuration found
10078 00:23:31.592538 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10079 00:23:31.596028 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d5a00-0x13f7d7fff]
10080 00:23:31.598839 [ 0.000000] Zone ranges:
10081 00:23:31.606053 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10082 00:23:31.609424 [ 0.000000] DMA32 empty
10083 00:23:31.615845 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10084 00:23:31.619153 [ 0.000000] Movable zone start for each node
10085 00:23:31.622199 [ 0.000000] Early memory node ranges
10086 00:23:31.628696 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10087 00:23:31.635761 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10088 00:23:31.642200 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10089 00:23:31.648769 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10090 00:23:31.652198 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10091 00:23:31.661810 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10092 00:23:31.691552 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10093 00:23:31.698333 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10094 00:23:31.704104 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10095 00:23:31.707754 [ 0.000000] psci: probing for conduit method from DT.
10096 00:23:31.714039 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10097 00:23:31.717601 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10098 00:23:31.724126 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10099 00:23:31.727510 [ 0.000000] psci: SMC Calling Convention v1.2
10100 00:23:31.734209 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10101 00:23:31.737348 [ 0.000000] Detected VIPT I-cache on CPU0
10102 00:23:31.743711 [ 0.000000] CPU features: detected: GIC system register CPU interface
10103 00:23:31.750611 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10104 00:23:31.756768 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10105 00:23:31.763474 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10106 00:23:31.773987 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10107 00:23:31.780350 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10108 00:23:31.783269 [ 0.000000] alternatives: applying boot alternatives
10109 00:23:31.791119 [ 0.000000] Fallback order for Node 0: 0
10110 00:23:31.796837 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10111 00:23:31.800418 [ 0.000000] Policy zone: Normal
10112 00:23:31.823327 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14479179/extract-nfsrootfs-6gqy51jo,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10113 00:23:31.833111 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10114 00:23:31.842943 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10115 00:23:31.852886 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10116 00:23:31.855963 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10117 00:23:31.862737 <6>[ 0.000000] software IO TLB: area num 8.
10118 00:23:31.918338 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10119 00:23:31.998863 <6>[ 0.000000] Memory: 3831344K/4191232K available (18112K kernel code, 4120K rwdata, 22648K rodata, 8512K init, 616K bss, 327120K reserved, 32768K cma-reserved)
10120 00:23:32.005228 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10121 00:23:32.012400 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10122 00:23:32.014714 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10123 00:23:32.021527 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10124 00:23:32.028224 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10125 00:23:32.031440 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10126 00:23:32.041756 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10127 00:23:32.047870 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10128 00:23:32.054329 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10129 00:23:32.061450 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10130 00:23:32.064230 <6>[ 0.000000] GICv3: 608 SPIs implemented
10131 00:23:32.067843 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10132 00:23:32.074091 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10133 00:23:32.077733 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10134 00:23:32.084984 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10135 00:23:32.097644 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10136 00:23:32.110550 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10137 00:23:32.117623 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10138 00:23:32.125150 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10139 00:23:32.137898 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10140 00:23:32.144718 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10141 00:23:32.151226 <6>[ 0.009173] Console: colour dummy device 80x25
10142 00:23:32.161507 <6>[ 0.013901] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10143 00:23:32.168640 <6>[ 0.024342] pid_max: default: 32768 minimum: 301
10144 00:23:32.171246 <6>[ 0.029208] LSM: Security Framework initializing
10145 00:23:32.177839 <6>[ 0.034120] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10146 00:23:32.187697 <6>[ 0.041728] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10147 00:23:32.194418 <6>[ 0.050998] cblist_init_generic: Setting adjustable number of callback queues.
10148 00:23:32.201393 <6>[ 0.058441] cblist_init_generic: Setting shift to 3 and lim to 1.
10149 00:23:32.210934 <6>[ 0.064779] cblist_init_generic: Setting adjustable number of callback queues.
10150 00:23:32.214326 <6>[ 0.072252] cblist_init_generic: Setting shift to 3 and lim to 1.
10151 00:23:32.220602 <6>[ 0.078693] rcu: Hierarchical SRCU implementation.
10152 00:23:32.227691 <6>[ 0.083709] rcu: Max phase no-delay instances is 1000.
10153 00:23:32.234312 <6>[ 0.090745] EFI services will not be available.
10154 00:23:32.237782 <6>[ 0.095700] smp: Bringing up secondary CPUs ...
10155 00:23:32.245074 <6>[ 0.100745] Detected VIPT I-cache on CPU1
10156 00:23:32.251857 <6>[ 0.100815] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10157 00:23:32.258731 <6>[ 0.100845] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10158 00:23:32.261821 <6>[ 0.101175] Detected VIPT I-cache on CPU2
10159 00:23:32.271639 <6>[ 0.101221] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10160 00:23:32.278121 <6>[ 0.101237] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10161 00:23:32.281552 <6>[ 0.101490] Detected VIPT I-cache on CPU3
10162 00:23:32.288490 <6>[ 0.101536] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10163 00:23:32.294687 <6>[ 0.101550] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10164 00:23:32.301592 <6>[ 0.101854] CPU features: detected: Spectre-v4
10165 00:23:32.304939 <6>[ 0.101860] CPU features: detected: Spectre-BHB
10166 00:23:32.308693 <6>[ 0.101866] Detected PIPT I-cache on CPU4
10167 00:23:32.315256 <6>[ 0.101923] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10168 00:23:32.321460 <6>[ 0.101939] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10169 00:23:32.327952 <6>[ 0.102226] Detected PIPT I-cache on CPU5
10170 00:23:32.334639 <6>[ 0.102289] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10171 00:23:32.341003 <6>[ 0.102305] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10172 00:23:32.344369 <6>[ 0.102588] Detected PIPT I-cache on CPU6
10173 00:23:32.351034 <6>[ 0.102650] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10174 00:23:32.357695 <6>[ 0.102666] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10175 00:23:32.364066 <6>[ 0.102967] Detected PIPT I-cache on CPU7
10176 00:23:32.370791 <6>[ 0.103031] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10177 00:23:32.377412 <6>[ 0.103047] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10178 00:23:32.380890 <6>[ 0.103094] smp: Brought up 1 node, 8 CPUs
10179 00:23:32.387494 <6>[ 0.244481] SMP: Total of 8 processors activated.
10180 00:23:32.390583 <6>[ 0.249433] CPU features: detected: 32-bit EL0 Support
10181 00:23:32.401005 <6>[ 0.254829] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10182 00:23:32.407207 <6>[ 0.263630] CPU features: detected: Common not Private translations
10183 00:23:32.414073 <6>[ 0.270146] CPU features: detected: CRC32 instructions
10184 00:23:32.417143 <6>[ 0.275497] CPU features: detected: RCpc load-acquire (LDAPR)
10185 00:23:32.424257 <6>[ 0.281458] CPU features: detected: LSE atomic instructions
10186 00:23:32.430252 <6>[ 0.287275] CPU features: detected: Privileged Access Never
10187 00:23:32.436925 <6>[ 0.293055] CPU features: detected: RAS Extension Support
10188 00:23:32.443623 <6>[ 0.298664] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10189 00:23:32.447010 <6>[ 0.305883] CPU: All CPU(s) started at EL2
10190 00:23:32.453386 <6>[ 0.310226] alternatives: applying system-wide alternatives
10191 00:23:32.462181 <6>[ 0.320263] devtmpfs: initialized
10192 00:23:32.477191 <6>[ 0.328503] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10193 00:23:32.483751 <6>[ 0.338462] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10194 00:23:32.490588 <6>[ 0.346722] pinctrl core: initialized pinctrl subsystem
10195 00:23:32.494435 <6>[ 0.353395] DMI not present or invalid.
10196 00:23:32.500249 <6>[ 0.357798] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10197 00:23:32.510578 <6>[ 0.364579] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
10198 00:23:32.516900 <6>[ 0.372022] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10199 00:23:32.526594 <6>[ 0.380117] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10200 00:23:32.530057 <6>[ 0.388272] audit: initializing netlink subsys (disabled)
10201 00:23:32.540151 <5>[ 0.393965] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10202 00:23:32.546741 <6>[ 0.394672] thermal_sys: Registered thermal governor 'step_wise'
10203 00:23:32.553528 <6>[ 0.401933] thermal_sys: Registered thermal governor 'power_allocator'
10204 00:23:32.556753 <6>[ 0.408187] cpuidle: using governor menu
10205 00:23:32.562836 <6>[ 0.419142] NET: Registered PF_QIPCRTR protocol family
10206 00:23:32.569511 <6>[ 0.424627] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10207 00:23:32.572744 <6>[ 0.431728] ASID allocator initialised with 32768 entries
10208 00:23:32.579952 <6>[ 0.438285] Serial: AMBA PL011 UART driver
10209 00:23:32.589253 <4>[ 0.447124] Trying to register duplicate clock ID: 134
10210 00:23:32.647232 <6>[ 0.508543] KASLR enabled
10211 00:23:32.661569 <6>[ 0.516261] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10212 00:23:32.668196 <6>[ 0.523273] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10213 00:23:32.674627 <6>[ 0.529765] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10214 00:23:32.682082 <6>[ 0.536770] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10215 00:23:32.688229 <6>[ 0.543257] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10216 00:23:32.694581 <6>[ 0.550263] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10217 00:23:32.701067 <6>[ 0.556750] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10218 00:23:32.707622 <6>[ 0.563752] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10219 00:23:32.710759 <6>[ 0.571250] ACPI: Interpreter disabled.
10220 00:23:32.719981 <6>[ 0.577664] iommu: Default domain type: Translated
10221 00:23:32.726087 <6>[ 0.582776] iommu: DMA domain TLB invalidation policy: strict mode
10222 00:23:32.729475 <5>[ 0.589438] SCSI subsystem initialized
10223 00:23:32.736540 <6>[ 0.593604] usbcore: registered new interface driver usbfs
10224 00:23:32.742810 <6>[ 0.599337] usbcore: registered new interface driver hub
10225 00:23:32.746046 <6>[ 0.604889] usbcore: registered new device driver usb
10226 00:23:32.752893 <6>[ 0.610979] pps_core: LinuxPPS API ver. 1 registered
10227 00:23:32.762797 <6>[ 0.616173] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10228 00:23:32.766406 <6>[ 0.625517] PTP clock support registered
10229 00:23:32.769811 <6>[ 0.629759] EDAC MC: Ver: 3.0.0
10230 00:23:32.777143 <6>[ 0.634899] FPGA manager framework
10231 00:23:32.783974 <6>[ 0.638585] Advanced Linux Sound Architecture Driver Initialized.
10232 00:23:32.787562 <6>[ 0.645354] vgaarb: loaded
10233 00:23:32.793822 <6>[ 0.648517] clocksource: Switched to clocksource arch_sys_counter
10234 00:23:32.797381 <5>[ 0.654952] VFS: Disk quotas dquot_6.6.0
10235 00:23:32.803722 <6>[ 0.659139] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10236 00:23:32.807157 <6>[ 0.666318] pnp: PnP ACPI: disabled
10237 00:23:32.815054 <6>[ 0.672980] NET: Registered PF_INET protocol family
10238 00:23:32.821740 <6>[ 0.678357] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
10239 00:23:32.833867 <6>[ 0.688376] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
10240 00:23:32.843870 <6>[ 0.697154] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10241 00:23:32.850440 <6>[ 0.705119] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
10242 00:23:32.856923 <6>[ 0.713523] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
10243 00:23:32.867330 <6>[ 0.722178] TCP: Hash tables configured (established 32768 bind 32768)
10244 00:23:32.874604 <6>[ 0.729034] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
10245 00:23:32.880934 <6>[ 0.736053] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
10246 00:23:32.887552 <6>[ 0.743575] NET: Registered PF_UNIX/PF_LOCAL protocol family
10247 00:23:32.894447 <6>[ 0.749689] RPC: Registered named UNIX socket transport module.
10248 00:23:32.897593 <6>[ 0.755842] RPC: Registered udp transport module.
10249 00:23:32.904051 <6>[ 0.760775] RPC: Registered tcp transport module.
10250 00:23:32.910686 <6>[ 0.765708] RPC: Registered tcp NFSv4.1 backchannel transport module.
10251 00:23:32.913699 <6>[ 0.772373] PCI: CLS 0 bytes, default 64
10252 00:23:32.917060 <6>[ 0.776677] Unpacking initramfs...
10253 00:23:32.934667 <6>[ 0.789116] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10254 00:23:32.944773 <6>[ 0.797753] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10255 00:23:32.947635 <6>[ 0.806584] kvm [1]: IPA Size Limit: 40 bits
10256 00:23:32.954540 <6>[ 0.811115] kvm [1]: GICv3: no GICV resource entry
10257 00:23:32.957803 <6>[ 0.816136] kvm [1]: disabling GICv2 emulation
10258 00:23:32.963998 <6>[ 0.820822] kvm [1]: GIC system register CPU interface enabled
10259 00:23:32.967384 <6>[ 0.826983] kvm [1]: vgic interrupt IRQ18
10260 00:23:32.973876 <6>[ 0.831339] kvm [1]: VHE mode initialized successfully
10261 00:23:32.980878 <5>[ 0.837728] Initialise system trusted keyrings
10262 00:23:32.987163 <6>[ 0.842562] workingset: timestamp_bits=42 max_order=20 bucket_order=0
10263 00:23:32.995125 <6>[ 0.852535] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10264 00:23:33.001654 <5>[ 0.858984] NFS: Registering the id_resolver key type
10265 00:23:33.004585 <5>[ 0.864295] Key type id_resolver registered
10266 00:23:33.011094 <5>[ 0.868711] Key type id_legacy registered
10267 00:23:33.017554 <6>[ 0.872987] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10268 00:23:33.024188 <6>[ 0.879912] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10269 00:23:33.031209 <6>[ 0.887670] 9p: Installing v9fs 9p2000 file system support
10270 00:23:33.066661 <5>[ 0.924722] Key type asymmetric registered
10271 00:23:33.069880 <5>[ 0.929053] Asymmetric key parser 'x509' registered
10272 00:23:33.079966 <6>[ 0.934186] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10273 00:23:33.083720 <6>[ 0.941804] io scheduler mq-deadline registered
10274 00:23:33.086734 <6>[ 0.946563] io scheduler kyber registered
10275 00:23:33.105807 <6>[ 0.963602] EINJ: ACPI disabled.
10276 00:23:33.138986 <4>[ 0.990127] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10277 00:23:33.148523 <4>[ 1.000763] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10278 00:23:33.164125 <6>[ 1.022024] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10279 00:23:33.172390 <6>[ 1.030079] printk: console [ttyS0] disabled
10280 00:23:33.200554 <6>[ 1.054702] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10281 00:23:33.206810 <6>[ 1.064194] printk: console [ttyS0] enabled
10282 00:23:33.209931 <6>[ 1.064194] printk: console [ttyS0] enabled
10283 00:23:33.216535 <6>[ 1.073093] printk: bootconsole [mtk8250] disabled
10284 00:23:33.219940 <6>[ 1.073093] printk: bootconsole [mtk8250] disabled
10285 00:23:33.226560 <6>[ 1.084387] SuperH (H)SCI(F) driver initialized
10286 00:23:33.230088 <6>[ 1.089667] msm_serial: driver initialized
10287 00:23:33.244090 <6>[ 1.098674] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10288 00:23:33.254319 <6>[ 1.107223] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10289 00:23:33.260825 <6>[ 1.115765] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10290 00:23:33.270621 <6>[ 1.124393] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10291 00:23:33.280915 <6>[ 1.133099] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10292 00:23:33.287183 <6>[ 1.141815] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10293 00:23:33.297086 <6>[ 1.150365] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10294 00:23:33.303909 <6>[ 1.159171] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10295 00:23:33.313601 <6>[ 1.167714] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10296 00:23:33.325110 <6>[ 1.183352] loop: module loaded
10297 00:23:33.332219 <6>[ 1.189321] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10298 00:23:33.355079 <4>[ 1.212790] mtk-pmic-keys: Failed to locate of_node [id: -1]
10299 00:23:33.361826 <6>[ 1.219591] megasas: 07.719.03.00-rc1
10300 00:23:33.371579 <6>[ 1.229510] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10301 00:23:33.378171 <6>[ 1.235897] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10302 00:23:33.395112 <6>[ 1.252559] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10303 00:23:33.451135 <6>[ 1.302375] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10304 00:23:33.707153 <6>[ 1.565470] Freeing initrd memory: 18300K
10305 00:23:33.718468 <6>[ 1.577004] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10306 00:23:33.729491 <6>[ 1.587968] tun: Universal TUN/TAP device driver, 1.6
10307 00:23:33.733176 <6>[ 1.594030] thunder_xcv, ver 1.0
10308 00:23:33.736279 <6>[ 1.597538] thunder_bgx, ver 1.0
10309 00:23:33.739541 <6>[ 1.601038] nicpf, ver 1.0
10310 00:23:33.750076 <6>[ 1.605051] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10311 00:23:33.753496 <6>[ 1.612527] hns3: Copyright (c) 2017 Huawei Corporation.
10312 00:23:33.756685 <6>[ 1.618120] hclge is initializing
10313 00:23:33.763501 <6>[ 1.621701] e1000: Intel(R) PRO/1000 Network Driver
10314 00:23:33.770246 <6>[ 1.626831] e1000: Copyright (c) 1999-2006 Intel Corporation.
10315 00:23:33.773794 <6>[ 1.632844] e1000e: Intel(R) PRO/1000 Network Driver
10316 00:23:33.780606 <6>[ 1.638059] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10317 00:23:33.787195 <6>[ 1.644246] igb: Intel(R) Gigabit Ethernet Network Driver
10318 00:23:33.793518 <6>[ 1.649897] igb: Copyright (c) 2007-2014 Intel Corporation.
10319 00:23:33.800435 <6>[ 1.655732] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10320 00:23:33.806460 <6>[ 1.662250] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10321 00:23:33.810858 <6>[ 1.668718] sky2: driver version 1.30
10322 00:23:33.817032 <6>[ 1.673643] usbcore: registered new device driver r8152-cfgselector
10323 00:23:33.823892 <6>[ 1.680181] usbcore: registered new interface driver r8152
10324 00:23:33.827138 <6>[ 1.685994] VFIO - User Level meta-driver version: 0.3
10325 00:23:33.836087 <6>[ 1.694204] usbcore: registered new interface driver usb-storage
10326 00:23:33.842721 <6>[ 1.700653] usbcore: registered new device driver onboard-usb-hub
10327 00:23:33.851898 <6>[ 1.709828] mt6397-rtc mt6359-rtc: registered as rtc0
10328 00:23:33.861920 <6>[ 1.715311] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-21T00:23:34 UTC (1718929414)
10329 00:23:33.865206 <6>[ 1.724936] i2c_dev: i2c /dev entries driver
10330 00:23:33.878755 <4>[ 1.736955] cpu cpu0: supply cpu not found, using dummy regulator
10331 00:23:33.885954 <4>[ 1.743385] cpu cpu1: supply cpu not found, using dummy regulator
10332 00:23:33.892434 <4>[ 1.749786] cpu cpu2: supply cpu not found, using dummy regulator
10333 00:23:33.899332 <4>[ 1.756194] cpu cpu3: supply cpu not found, using dummy regulator
10334 00:23:33.905554 <4>[ 1.762606] cpu cpu4: supply cpu not found, using dummy regulator
10335 00:23:33.911857 <4>[ 1.769001] cpu cpu5: supply cpu not found, using dummy regulator
10336 00:23:33.918607 <4>[ 1.775401] cpu cpu6: supply cpu not found, using dummy regulator
10337 00:23:33.925363 <4>[ 1.781796] cpu cpu7: supply cpu not found, using dummy regulator
10338 00:23:33.945385 <6>[ 1.803429] cpu cpu0: EM: created perf domain
10339 00:23:33.948645 <6>[ 1.808336] cpu cpu4: EM: created perf domain
10340 00:23:33.956323 <6>[ 1.813857] sdhci: Secure Digital Host Controller Interface driver
10341 00:23:33.962341 <6>[ 1.820289] sdhci: Copyright(c) Pierre Ossman
10342 00:23:33.969009 <6>[ 1.825200] Synopsys Designware Multimedia Card Interface Driver
10343 00:23:33.976088 <6>[ 1.831783] sdhci-pltfm: SDHCI platform and OF driver helper
10344 00:23:33.979309 <6>[ 1.831867] mmc0: CQHCI version 5.10
10345 00:23:33.985788 <6>[ 1.841755] ledtrig-cpu: registered to indicate activity on CPUs
10346 00:23:33.992264 <6>[ 1.848701] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10347 00:23:33.999464 <6>[ 1.855714] usbcore: registered new interface driver usbhid
10348 00:23:34.003409 <6>[ 1.861536] usbhid: USB HID core driver
10349 00:23:34.009025 <6>[ 1.865738] spi_master spi0: will run message pump with realtime priority
10350 00:23:34.051390 <6>[ 1.903037] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10351 00:23:34.070610 <6>[ 1.918297] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10352 00:23:34.077764 <6>[ 1.933023] cros-ec-spi spi0.0: Chrome EC device registered
10353 00:23:34.080731 <6>[ 1.933095] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x15c14
10354 00:23:34.090869 <6>[ 1.948947] mmc0: Command Queue Engine enabled
10355 00:23:34.101153 <6>[ 1.950558] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10356 00:23:34.107628 <6>[ 1.953664] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10357 00:23:34.111320 <6>[ 1.963857] NET: Registered PF_PACKET protocol family
10358 00:23:34.117583 <6>[ 1.970169] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10359 00:23:34.121212 <6>[ 1.974941] 9pnet: Installing 9P2000 support
10360 00:23:34.127260 <6>[ 1.984015] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10361 00:23:34.130854 <5>[ 1.984203] Key type dns_resolver registered
10362 00:23:34.137278 <6>[ 1.991405] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10363 00:23:34.140960 <6>[ 1.994983] registered taskstats version 1
10364 00:23:34.147146 <6>[ 2.000450] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10365 00:23:34.150708 <5>[ 2.004194] Loading compiled-in X.509 certificates
10366 00:23:34.157003 <6>[ 2.009997] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10367 00:23:34.178419 <4>[ 2.029671] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10368 00:23:34.187990 <4>[ 2.040348] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10369 00:23:34.202059 <6>[ 2.059927] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10370 00:23:34.209266 <6>[ 2.066695] xhci-mtk 11200000.usb: xHCI Host Controller
10371 00:23:34.215043 <6>[ 2.072203] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10372 00:23:34.225244 <6>[ 2.080109] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10373 00:23:34.232386 <6>[ 2.089544] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10374 00:23:34.238899 <6>[ 2.095732] xhci-mtk 11200000.usb: xHCI Host Controller
10375 00:23:34.245435 <6>[ 2.101254] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10376 00:23:34.251707 <6>[ 2.108913] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10377 00:23:34.259666 <6>[ 2.116765] hub 1-0:1.0: USB hub found
10378 00:23:34.262202 <6>[ 2.120802] hub 1-0:1.0: 1 port detected
10379 00:23:34.268639 <6>[ 2.125097] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10380 00:23:34.275881 <6>[ 2.133916] hub 2-0:1.0: USB hub found
10381 00:23:34.279135 <6>[ 2.137944] hub 2-0:1.0: 1 port detected
10382 00:23:34.287361 <6>[ 2.145685] mtk-msdc 11f70000.mmc: Got CD GPIO
10383 00:23:34.299997 <6>[ 2.154371] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10384 00:23:34.310304 <6>[ 2.162755] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10385 00:23:34.317090 <6>[ 2.171097] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10386 00:23:34.326450 <6>[ 2.179437] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10387 00:23:34.333079 <6>[ 2.187776] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10388 00:23:34.342944 <6>[ 2.196115] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10389 00:23:34.349437 <6>[ 2.204453] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10390 00:23:34.359333 <6>[ 2.212790] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10391 00:23:34.366663 <6>[ 2.221130] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10392 00:23:34.376018 <6>[ 2.229474] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10393 00:23:34.382362 <6>[ 2.237811] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10394 00:23:34.392657 <6>[ 2.246154] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10395 00:23:34.399331 <6>[ 2.254491] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10396 00:23:34.409613 <6>[ 2.262828] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10397 00:23:34.416055 <6>[ 2.271166] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10398 00:23:34.422799 <6>[ 2.279857] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10399 00:23:34.429332 <6>[ 2.286988] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10400 00:23:34.435546 <6>[ 2.293784] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10401 00:23:34.445913 <6>[ 2.300530] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10402 00:23:34.452290 <6>[ 2.307430] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10403 00:23:34.458888 <6>[ 2.314326] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10404 00:23:34.469032 <6>[ 2.323458] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10405 00:23:34.479027 <6>[ 2.332584] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10406 00:23:34.488411 <6>[ 2.341876] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10407 00:23:34.498722 <6>[ 2.351343] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10408 00:23:34.509274 <6>[ 2.360811] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10409 00:23:34.514957 <6>[ 2.369934] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10410 00:23:34.525185 <6>[ 2.379400] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10411 00:23:34.534992 <6>[ 2.388521] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10412 00:23:34.544535 <6>[ 2.397816] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10413 00:23:34.554628 <6>[ 2.407974] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10414 00:23:34.564979 <6>[ 2.419589] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10415 00:23:34.572284 <6>[ 2.430669] Trying to probe devices needed for running init ...
10416 00:23:34.582778 <3>[ 2.437871] mt8192-audio 11210000.syscon:mt8192-afe-pcm: could not get audiosys reset:-517
10417 00:23:34.690396 <6>[ 2.544786] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10418 00:23:34.844877 <6>[ 2.702685] hub 1-1:1.0: USB hub found
10419 00:23:34.848078 <6>[ 2.707209] hub 1-1:1.0: 4 ports detected
10420 00:23:34.860074 <6>[ 2.717941] hub 1-1:1.0: USB hub found
10421 00:23:34.863199 <6>[ 2.722370] hub 1-1:1.0: 4 ports detected
10422 00:23:34.970394 <6>[ 2.825036] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10423 00:23:34.995556 <6>[ 2.853753] hub 2-1:1.0: USB hub found
10424 00:23:34.998978 <6>[ 2.858219] hub 2-1:1.0: 3 ports detected
10425 00:23:35.009405 <6>[ 2.867583] hub 2-1:1.0: USB hub found
10426 00:23:35.012344 <6>[ 2.871997] hub 2-1:1.0: 3 ports detected
10427 00:23:35.185775 <6>[ 3.040787] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10428 00:23:35.318130 <6>[ 3.176387] hub 1-1.4:1.0: USB hub found
10429 00:23:35.321401 <6>[ 3.181054] hub 1-1.4:1.0: 2 ports detected
10430 00:23:35.334287 <6>[ 3.192065] hub 1-1.4:1.0: USB hub found
10431 00:23:35.336820 <6>[ 3.196635] hub 1-1.4:1.0: 2 ports detected
10432 00:23:35.398094 <6>[ 3.253020] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10433 00:23:35.506697 <6>[ 3.361463] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10434 00:23:35.542480 <4>[ 3.397257] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10435 00:23:35.552343 <4>[ 3.406380] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10436 00:23:35.592194 <6>[ 3.450298] r8152 2-1.3:1.0 eth0: v1.12.13
10437 00:23:35.633589 <6>[ 3.488637] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10438 00:23:35.825783 <6>[ 3.680672] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10439 00:23:37.174703 <6>[ 5.033297] r8152 2-1.3:1.0 eth0: carrier on
10440 00:23:39.718005 <5>[ 5.064643] Sending DHCP requests .., OK
10441 00:23:39.724198 <6>[ 7.580982] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.16
10442 00:23:39.728171 <6>[ 7.589273] IP-Config: Complete:
10443 00:23:39.741397 <6>[ 7.592772] device=eth0, hwaddr=00:e0:4c:68:03:bd, ipaddr=192.168.201.16, mask=255.255.255.0, gw=192.168.201.1
10444 00:23:39.747566 <6>[ 7.603480] host=mt8192-asurada-spherion-r0-cbg-4, domain=lava-rack, nis-domain=(none)
10445 00:23:39.754494 <6>[ 7.612098] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10446 00:23:39.761142 <6>[ 7.612107] nameserver0=192.168.201.1
10447 00:23:39.764447 <6>[ 7.624267] clk: Disabling unused clocks
10448 00:23:39.767958 <6>[ 7.629783] ALSA device list:
10449 00:23:39.774660 <6>[ 7.633039] No soundcards found.
10450 00:23:39.781771 <6>[ 7.640205] Freeing unused kernel memory: 8512K
10451 00:23:39.784993 <6>[ 7.645174] Run /init as init process
10452 00:23:39.794069 Loading, please wait...
10453 00:23:39.820523 Starting systemd-udevd version 252.22-1~deb12u1
10454 00:23:40.029420 <6>[ 7.884936] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10455 00:23:40.043429 <6>[ 7.898871] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10456 00:23:40.050156 <6>[ 7.899344] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10457 00:23:40.056559 <6>[ 7.902935] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10458 00:23:40.066691 <6>[ 7.907063] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10459 00:23:40.070177 <6>[ 7.907353] mc: Linux media interface: v0.10
10460 00:23:40.079890 <6>[ 7.914862] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10461 00:23:40.089513 <4>[ 7.922296] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10462 00:23:40.096472 <4>[ 7.924022] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10463 00:23:40.099381 <6>[ 7.928714] remoteproc remoteproc0: scp is available
10464 00:23:40.106695 <6>[ 7.928851] remoteproc remoteproc0: powering up scp
10465 00:23:40.112969 <6>[ 7.928859] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10466 00:23:40.120040 <6>[ 7.928889] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10467 00:23:40.129482 <6>[ 7.929767] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10468 00:23:40.135843 <4>[ 7.930462] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10469 00:23:40.145694 <6>[ 7.934802] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10470 00:23:40.149184 <6>[ 7.965682] videodev: Linux video capture interface: v2.00
10471 00:23:40.159185 <3>[ 7.967322] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10472 00:23:40.165844 <3>[ 7.967330] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10473 00:23:40.176020 <3>[ 7.967333] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10474 00:23:40.183070 <6>[ 7.969815] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10475 00:23:40.189579 <6>[ 7.973079] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10476 00:23:40.199762 <3>[ 7.976652] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10477 00:23:40.206887 <3>[ 7.976681] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10478 00:23:40.216096 <3>[ 7.976694] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10479 00:23:40.222376 <3>[ 7.976711] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10480 00:23:40.232238 <3>[ 7.976721] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10481 00:23:40.239234 <3>[ 7.978570] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10482 00:23:40.245364 <6>[ 7.983982] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10483 00:23:40.256085 <6>[ 7.983987] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10484 00:23:40.262725 <6>[ 7.983992] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10485 00:23:40.272990 <6>[ 7.992455] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10486 00:23:40.279131 <3>[ 7.993246] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10487 00:23:40.289618 <4>[ 8.014544] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10488 00:23:40.293126 <4>[ 8.014544] Fallback method does not support PEC.
10489 00:23:40.303208 <3>[ 8.022200] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10490 00:23:40.309179 <6>[ 8.042216] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10491 00:23:40.319200 <3>[ 8.046282] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10492 00:23:40.325644 <6>[ 8.054613] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10493 00:23:40.332187 <3>[ 8.062341] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10494 00:23:40.342075 <6>[ 8.067445] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10495 00:23:40.345465 <6>[ 8.067449] pci_bus 0000:00: root bus resource [bus 00-ff]
10496 00:23:40.352156 <6>[ 8.067453] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10497 00:23:40.362052 <6>[ 8.067455] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10498 00:23:40.368421 <6>[ 8.067481] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10499 00:23:40.378522 <6>[ 8.067493] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10500 00:23:40.381475 <6>[ 8.067558] pci 0000:00:00.0: supports D1 D2
10501 00:23:40.388376 <6>[ 8.067561] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10502 00:23:40.398261 <6>[ 8.068376] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10503 00:23:40.401554 <6>[ 8.068446] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10504 00:23:40.411859 <6>[ 8.068470] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10505 00:23:40.418476 <6>[ 8.068485] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10506 00:23:40.424752 <6>[ 8.068500] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10507 00:23:40.431050 <6>[ 8.068608] pci 0000:01:00.0: supports D1 D2
10508 00:23:40.438303 <6>[ 8.068610] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10509 00:23:40.444497 <6>[ 8.070390] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10510 00:23:40.454352 <3>[ 8.078553] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10511 00:23:40.461315 <6>[ 8.080610] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10512 00:23:40.467287 <6>[ 8.080633] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10513 00:23:40.477716 <6>[ 8.080635] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10514 00:23:40.484369 <6>[ 8.080643] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10515 00:23:40.491075 <6>[ 8.080656] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10516 00:23:40.500589 <6>[ 8.080669] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10517 00:23:40.504148 <6>[ 8.080680] pci 0000:00:00.0: PCI bridge to [bus 01]
10518 00:23:40.513904 <6>[ 8.080685] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10519 00:23:40.520813 <6>[ 8.080773] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10520 00:23:40.527166 <6>[ 8.081188] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10521 00:23:40.530310 <6>[ 8.081762] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10522 00:23:40.537553 <6>[ 8.086772] remoteproc remoteproc0: remote processor scp is now up
10523 00:23:40.547044 <3>[ 8.094745] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10524 00:23:40.553826 <3>[ 8.094850] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10525 00:23:40.563550 <6>[ 8.106076] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10526 00:23:40.573911 <3>[ 8.110605] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10527 00:23:40.580335 <3>[ 8.110608] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10528 00:23:40.589822 <3>[ 8.110639] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10529 00:23:40.600048 <6>[ 8.118921] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10530 00:23:40.606325 <3>[ 8.124834] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10531 00:23:40.632214 <6>[ 8.487378] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10532 00:23:40.635759 <6>[ 8.490721] Bluetooth: Core ver 2.22
10533 00:23:40.642452 <6>[ 8.499710] NET: Registered PF_BLUETOOTH protocol family
10534 00:23:40.648295 <5>[ 8.501848] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10535 00:23:40.658442 <6>[ 8.503883] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10536 00:23:40.665408 <6>[ 8.504075] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10537 00:23:40.671968 <6>[ 8.505276] Bluetooth: HCI device and connection manager initialized
10538 00:23:40.674931 <6>[ 8.505297] Bluetooth: HCI socket layer initialized
10539 00:23:40.688205 <6>[ 8.505521] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10540 00:23:40.694976 <6>[ 8.505761] usbcore: registered new interface driver uvcvideo
10541 00:23:40.701657 <5>[ 8.531370] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10542 00:23:40.707954 <6>[ 8.535154] Bluetooth: L2CAP socket layer initialized
10543 00:23:40.711525 <6>[ 8.535175] Bluetooth: SCO socket layer initialized
10544 00:23:40.718307 <6>[ 8.536369] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10545 00:23:40.728195 <5>[ 8.540569] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10546 00:23:40.734739 <4>[ 8.590896] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10547 00:23:40.741364 <6>[ 8.591320] usbcore: registered new interface driver btusb
10548 00:23:40.750990 <4>[ 8.592006] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10549 00:23:40.757646 <3>[ 8.592011] Bluetooth: hci0: Failed to load firmware file (-2)
10550 00:23:40.764539 <3>[ 8.592013] Bluetooth: hci0: Failed to set up firmware (-2)
10551 00:23:40.774309 <4>[ 8.592014] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10552 00:23:40.780609 <6>[ 8.599772] cfg80211: failed to load regulatory.db
10553 00:23:40.816654 <6>[ 8.671829] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10554 00:23:40.823058 <6>[ 8.679408] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10555 00:23:40.847015 <6>[ 8.706060] mt7921e 0000:01:00.0: ASIC revision: 79610010
10556 00:23:40.948941 <6>[ 8.803859] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10557 00:23:40.951766 <6>[ 8.803859]
10558 00:23:40.955289 Begin: Loading essential drivers ... done.
10559 00:23:40.958272 Begin: Running /scripts/init-premount ... done.
10560 00:23:40.964887 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10561 00:23:40.974776 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10562 00:23:40.978029 Device /sys/class/net/eth0 found
10563 00:23:40.978638 done.
10564 00:23:40.984568 Begin: Waiting up to 180 secs for any network device to become available ... done.
10565 00:23:41.034061 IP-Config: eth0 hardware address 00:e0:4c:68:03:bd mtu 1500 DHCP
10566 00:23:41.040320 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10567 00:23:41.047467 address: 192.168.201.16 broadcast: 192.168.201.255 netmask: 255.255.255.0
10568 00:23:41.054205 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10569 00:23:41.060731 host : mt8192-asurada-spherion-r0-cbg-4
10570 00:23:41.067250 domain : lava-rack
10571 00:23:41.069937 rootserver: 192.168.201.1 rootpath:
10572 00:23:41.070475 filename :
10573 00:23:41.083444 done.
10574 00:23:41.090017 Begin: Running /scripts/nfs-bottom ... done.
10575 00:23:41.105052 Begin: Running /scripts/init-bottom ... done.
10576 00:23:41.218604 <6>[ 9.074246] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10577 00:23:42.435323 <6>[ 10.294048] NET: Registered PF_INET6 protocol family
10578 00:23:42.442592 <6>[ 10.301410] Segment Routing with IPv6
10579 00:23:42.445576 <6>[ 10.305404] In-situ OAM (IOAM) with IPv6
10580 00:23:42.614654 <30>[ 10.447277] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10581 00:23:42.621315 <30>[ 10.480426] systemd[1]: Detected architecture arm64.
10582 00:23:42.630677
10583 00:23:42.634044 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10584 00:23:42.634617
10585 00:23:42.663588 <30>[ 10.522520] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10586 00:23:43.694904 <30>[ 11.551132] systemd[1]: Queued start job for default target graphical.target.
10587 00:23:43.741839 <30>[ 11.597966] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10588 00:23:43.749080 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10589 00:23:43.770514 <30>[ 11.626597] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10590 00:23:43.780747 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10591 00:23:43.798819 <30>[ 11.654540] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10592 00:23:43.808847 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10593 00:23:43.826395 <30>[ 11.682168] systemd[1]: Created slice user.slice - User and Session Slice.
10594 00:23:43.832498 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10595 00:23:43.857197 <30>[ 11.709664] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10596 00:23:43.866908 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10597 00:23:43.884620 <30>[ 11.737050] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10598 00:23:43.891391 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10599 00:23:43.919471 <30>[ 11.765477] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10600 00:23:43.929626 <30>[ 11.785371] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10601 00:23:43.936161 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10602 00:23:43.953306 <30>[ 11.809213] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10603 00:23:43.963121 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10604 00:23:43.981867 <30>[ 11.837339] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10605 00:23:43.991186 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10606 00:23:44.005580 <30>[ 11.864919] systemd[1]: Reached target paths.target - Path Units.
10607 00:23:44.015791 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10608 00:23:44.033561 <30>[ 11.889283] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10609 00:23:44.040161 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10610 00:23:44.053730 <30>[ 11.912800] systemd[1]: Reached target slices.target - Slice Units.
10611 00:23:44.063714 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10612 00:23:44.078296 <30>[ 11.937302] systemd[1]: Reached target swap.target - Swaps.
10613 00:23:44.084594 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10614 00:23:44.105697 <30>[ 11.961320] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10615 00:23:44.115105 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10616 00:23:44.134097 <30>[ 11.989776] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10617 00:23:44.143610 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10618 00:23:44.164325 <30>[ 12.020357] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10619 00:23:44.174795 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10620 00:23:44.190562 <30>[ 12.046378] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10621 00:23:44.200048 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10622 00:23:44.217668 <30>[ 12.073542] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10623 00:23:44.224378 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10624 00:23:44.242648 <30>[ 12.098470] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10625 00:23:44.252252 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10626 00:23:44.271631 <30>[ 12.127500] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10627 00:23:44.281341 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10628 00:23:44.297379 <30>[ 12.153290] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10629 00:23:44.307497 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10630 00:23:44.349272 <30>[ 12.204927] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10631 00:23:44.355655 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10632 00:23:44.376969 <30>[ 12.233406] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10633 00:23:44.383330 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10634 00:23:44.453113 <30>[ 12.309179] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10635 00:23:44.459363 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10636 00:23:44.488111 <30>[ 12.337513] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10637 00:23:44.503011 <30>[ 12.359269] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10638 00:23:44.513024 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10639 00:23:44.534275 <30>[ 12.390377] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10640 00:23:44.540735 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10641 00:23:44.565226 <30>[ 12.420815] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10642 00:23:44.571400 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10643 00:23:44.594214 <30>[ 12.450368] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10644 00:23:44.608086 Starting [0;1;39mmodprobe@drm.service<6>[ 12.461397] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10645 00:23:44.610617 [0m - Load Kernel Module drm...
10646 00:23:44.665191 <30>[ 12.521394] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10647 00:23:44.675158 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10648 00:23:44.698518 <30>[ 12.554485] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10649 00:23:44.705048 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10650 00:23:44.728835 <30>[ 12.584999] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10651 00:23:44.735595 Starting [0;1;39mmodpr<6>[ 12.595290] fuse: init (API version 7.37)
10652 00:23:44.738704 obe@loop.ser…e[0m - Load Kernel Module loop...
10653 00:23:44.809549 <30>[ 12.665482] systemd[1]: Starting systemd-journald.service - Journal Service...
10654 00:23:44.816144 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10655 00:23:44.841560 <30>[ 12.697679] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10656 00:23:44.848181 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10657 00:23:44.876830 <30>[ 12.729239] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10658 00:23:44.882812 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10659 00:23:44.907257 <30>[ 12.763649] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10660 00:23:44.917633 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10661 00:23:44.938890 <30>[ 12.794507] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10662 00:23:44.945073 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10663 00:23:44.971915 <30>[ 12.828149] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10664 00:23:44.978760 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10665 00:23:44.997125 <30>[ 12.853272] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10666 00:23:45.003569 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10667 00:23:45.021246 <30>[ 12.877277] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10668 00:23:45.034975 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m<3>[ 12.890711] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10669 00:23:45.038560 - Kernel Debug File System.
10670 00:23:45.058714 <30>[ 12.914318] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10671 00:23:45.069043 <3>[ 12.921941] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10672 00:23:45.075365 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10673 00:23:45.095341 <30>[ 12.950223] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10674 00:23:45.101005 <30>[ 12.958379] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10675 00:23:45.117941 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - <3>[ 12.971887] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10676 00:23:45.121738 Load Kernel Module configfs.
10677 00:23:45.138529 <30>[ 12.993907] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10678 00:23:45.145665 <30>[ 13.001772] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10679 00:23:45.154935 <3>[ 13.001802] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10680 00:23:45.161877 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10681 00:23:45.182362 <30>[ 13.037992] systemd[1]: modprobe@drm.service: Deactivated successfully.
10682 00:23:45.189289 <3>[ 13.039603] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10683 00:23:45.195183 <30>[ 13.045555] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10684 00:23:45.205665 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10685 00:23:45.216318 <3>[ 13.072163] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10686 00:23:45.226803 <30>[ 13.082697] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10687 00:23:45.236903 <30>[ 13.092342] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10688 00:23:45.246885 [[0;32m OK [<3>[ 13.102421] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10689 00:23:45.254197 0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10690 00:23:45.274351 <30>[ 13.130042] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10691 00:23:45.280978 <3>[ 13.133723] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10692 00:23:45.290865 <30>[ 13.137902] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10693 00:23:45.297213 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10694 00:23:45.311690 <3>[ 13.167668] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10695 00:23:45.321536 <30>[ 13.177659] systemd[1]: modprobe@loop.service: Deactivated successfully.
10696 00:23:45.328189 <30>[ 13.185024] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
10697 00:23:45.337997 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10698 00:23:45.354116 <30>[ 13.209677] systemd[1]: Finished systemd-modules-load.service - Load Kernel Modules.
10699 00:23:45.360489 <3>[ 13.211414] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10700 00:23:45.371009 <3>[ 13.212140] power_supply sbs-5-000b: driver failed to report `capacity' property: -6
10701 00:23:45.387229 <4>[ 13.212152] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10702 00:23:45.393809 <3>[ 13.212156] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -6
10703 00:23:45.403663 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10704 00:23:45.426073 <30>[ 13.278653] systemd[1]: Finished systemd-network-generator.service - Generate network units from Kernel command line.
10705 00:23:45.432513 <3>[ 13.280639] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10706 00:23:45.442692 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10707 00:23:45.462599 <30>[ 13.317758] systemd[1]: Finished systemd-remount-fs.service - Remount Root and Kernel File Systems.
10708 00:23:45.472371 <3>[ 13.320341] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10709 00:23:45.478974 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10710 00:23:45.497448 <30>[ 13.353484] systemd[1]: Finished systemd-udev-trigger.service - Coldplug All udev Devices.
10711 00:23:45.507683 <3>[ 13.356018] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10712 00:23:45.514031 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10713 00:23:45.534859 <30>[ 13.390491] systemd[1]: Reached target network-pre.target - Preparation for Network.
10714 00:23:45.544541 <3>[ 13.392382] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10715 00:23:45.551034 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10716 00:23:45.574316 <3>[ 13.430149] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10717 00:23:45.593474 <30>[ 13.449090] systemd[1]: Mounting sys-fs-fuse-connections.mount - FUSE Control File System...
10718 00:23:45.600072 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10719 00:23:45.629894 <30>[ 13.486014] systemd[1]: Mounting sys-kernel-config.mount - Kernel Configuration File System...
10720 00:23:45.637128 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10721 00:23:45.660741 <30>[ 13.512899] systemd[1]: systemd-firstboot.service - First Boot Wizard was skipped because of an unmet condition check (ConditionFirstBoot=yes).
10722 00:23:45.677354 <30>[ 13.526569] systemd[1]: systemd-pstore.service - Platform Persistent Storage Archival was skipped because of an unmet condition check (ConditionDirectoryNotEmpty=/sys/fs/pstore).
10723 00:23:45.725551 <30>[ 13.581581] systemd[1]: Starting systemd-random-seed.service - Load/Save Random Seed...
10724 00:23:45.731886 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10725 00:23:45.759577 <30>[ 13.612595] systemd[1]: systemd-repart.service - Repartition Root Disk was skipped because no trigger condition checks were met.
10726 00:23:45.774249 <30>[ 13.630094] systemd[1]: Starting systemd-sysctl.service - Apply Kernel Variables...
10727 00:23:45.780604 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10728 00:23:45.808010 <30>[ 13.664278] systemd[1]: Starting systemd-sysusers.service - Create System Users...
10729 00:23:45.814519 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10730 00:23:45.844519 <30>[ 13.700138] systemd[1]: Started systemd-journald.service - Journal Service.
10731 00:23:45.850519 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10732 00:23:45.878303 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10733 00:23:45.901653 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10734 00:23:45.926111 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10735 00:23:45.946478 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10736 00:23:45.966378 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10737 00:23:46.034670 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10738 00:23:46.060760 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10739 00:23:46.094897 <46>[ 13.950883] systemd-journald[299]: Received client request to flush runtime journal.
10740 00:23:46.150104 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10741 00:23:46.173679 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10742 00:23:46.193234 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10743 00:23:46.901801 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10744 00:23:47.528401 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10745 00:23:47.570048 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10746 00:23:47.643452 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10747 00:23:47.692007 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10748 00:23:47.754432 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10749 00:23:48.047832 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10750 00:23:48.102598 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10751 00:23:48.109057 <6>[ 15.968909] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10752 00:23:48.144122 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10753 00:23:48.172045 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10754 00:23:48.217867 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10755 00:23:48.242102 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10756 00:23:48.313805 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10757 00:23:48.389292 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10758 00:23:48.405160 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10759 00:23:48.481597 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10760 00:23:48.529901 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10761 00:23:48.554370 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10762 00:23:48.610190 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10763 00:23:48.679880 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10764 00:23:48.697387 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10765 00:23:48.717030 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10766 00:23:48.732686 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10767 00:23:48.758012 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
10768 00:23:48.780599 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
10769 00:23:48.796498 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
10770 00:23:48.816837 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
10771 00:23:48.836581 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10772 00:23:48.852599 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10773 00:23:48.870198 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10774 00:23:48.888377 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10775 00:23:48.904195 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10776 00:23:48.950188 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10777 00:23:48.984417 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
10778 00:23:49.065222 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10779 00:23:49.090972 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
10780 00:23:49.142793 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
10781 00:23:49.198820 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
10782 00:23:49.247382 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
10783 00:23:49.265137 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
10784 00:23:49.290463 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
10785 00:23:49.408378 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
10786 00:23:49.426777 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
10787 00:23:49.446824 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
10788 00:23:49.465762 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
10789 00:23:49.504936 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
10790 00:23:49.574226 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
10791 00:23:49.666561
10792 00:23:49.669801 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
10793 00:23:49.670287
10794 00:23:49.672716 debian-bookworm-arm64 login: root (automatic login)
10795 00:23:49.673152
10796 00:23:49.952923 Linux debian-bookworm-arm64 6.1.94-cip23 #1 SMP PREEMPT Fri Jun 21 00:04:56 UTC 2024 aarch64
10797 00:23:49.953051
10798 00:23:49.959838 The programs included with the Debian GNU/Linux system are free software;
10799 00:23:49.966326 the exact distribution terms for each program are described in the
10800 00:23:49.969246 individual files in /usr/share/doc/*/copyright.
10801 00:23:49.969341
10802 00:23:49.975941 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10803 00:23:49.979325 permitted by applicable law.
10804 00:23:50.940855 Matched prompt #10: / #
10806 00:23:50.941110 Setting prompt string to ['/ #']
10807 00:23:50.941229 end: 2.2.5.1 login-action (duration 00:00:19) [common]
10809 00:23:50.941402 end: 2.2.5 auto-login-action (duration 00:00:19) [common]
10810 00:23:50.941483 start: 2.2.6 expect-shell-connection (timeout 00:03:39) [common]
10811 00:23:50.941548 Setting prompt string to ['/ #']
10812 00:23:50.941604 Forcing a shell prompt, looking for ['/ #']
10814 00:23:50.991851 / #
10815 00:23:50.992237 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10816 00:23:50.992426 Waiting using forced prompt support (timeout 00:02:30)
10817 00:23:50.997811
10818 00:23:50.998621 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10819 00:23:50.999133 start: 2.2.7 export-device-env (timeout 00:03:39) [common]
10821 00:23:51.100285 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14479179/extract-nfsrootfs-6gqy51jo'
10822 00:23:51.106796 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14479179/extract-nfsrootfs-6gqy51jo'
10824 00:23:51.208304 / # export NFS_SERVER_IP='192.168.201.1'
10825 00:23:51.215035 export NFS_SERVER_IP='192.168.201.1'
10826 00:23:51.215921 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10827 00:23:51.216458 end: 2.2 depthcharge-retry (duration 00:01:22) [common]
10828 00:23:51.216962 end: 2 depthcharge-action (duration 00:01:22) [common]
10829 00:23:51.217431 start: 3 lava-test-retry (timeout 00:07:56) [common]
10830 00:23:51.217894 start: 3.1 lava-test-shell (timeout 00:07:56) [common]
10831 00:23:51.218326 Using namespace: common
10833 00:23:51.319484 / # #
10834 00:23:51.320156 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10835 00:23:51.325883 #
10836 00:23:51.326734 Using /lava-14479179
10838 00:23:51.427894 / # export SHELL=/bin/bash
10839 00:23:51.434298 export SHELL=/bin/bash
10841 00:23:51.536206 / # . /lava-14479179/environment
10842 00:23:51.542965 . /lava-14479179/environment
10844 00:23:51.650447 / # /lava-14479179/bin/lava-test-runner /lava-14479179/0
10845 00:23:51.651143 Test shell timeout: 10s (minimum of the action and connection timeout)
10846 00:23:51.657048 /lava-14479179/bin/lava-test-runner /lava-14479179/0
10847 00:23:51.900531 + export TESTRUN_ID=0_timesync-off
10848 00:23:51.903971 + TESTRUN_ID=0_timesync-off
10849 00:23:51.907163 + cd /lava-14479179/0/tests/0_timesync-off
10850 00:23:51.910541 ++ cat uuid
10851 00:23:51.914615 + UUID=14479179_1.6.2.3.1
10852 00:23:51.915058 + set +x
10853 00:23:51.921483 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14479179_1.6.2.3.1>
10854 00:23:51.922197 Received signal: <STARTRUN> 0_timesync-off 14479179_1.6.2.3.1
10855 00:23:51.922587 Starting test lava.0_timesync-off (14479179_1.6.2.3.1)
10856 00:23:51.923009 Skipping test definition patterns.
10857 00:23:51.924630 + systemctl stop systemd-timesyncd
10858 00:23:51.981727 + set +x
10859 00:23:51.984484 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14479179_1.6.2.3.1>
10860 00:23:51.985169 Received signal: <ENDRUN> 0_timesync-off 14479179_1.6.2.3.1
10861 00:23:51.985594 Ending use of test pattern.
10862 00:23:51.985917 Ending test lava.0_timesync-off (14479179_1.6.2.3.1), duration 0.06
10864 00:23:52.056537 + export TESTRUN_ID=1_kselftest-alsa
10865 00:23:52.059811 + TESTRUN_ID=1_kselftest-alsa
10866 00:23:52.062859 + cd /lava-14479179/0/tests/1_kselftest-alsa
10867 00:23:52.066073 ++ cat uuid
10868 00:23:52.070877 + UUID=14479179_1.6.2.3.5
10869 00:23:52.070955 + set +x
10870 00:23:52.077114 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 14479179_1.6.2.3.5>
10871 00:23:52.077360 Received signal: <STARTRUN> 1_kselftest-alsa 14479179_1.6.2.3.5
10872 00:23:52.077426 Starting test lava.1_kselftest-alsa (14479179_1.6.2.3.5)
10873 00:23:52.077501 Skipping test definition patterns.
10874 00:23:52.080481 + cd ./automated/linux/kselftest/
10875 00:23:52.106933 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.94-cip23/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
10876 00:23:52.131912 INFO: install_deps skipped
10877 00:23:52.619133 --2024-06-21 00:23:53-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.94-cip23/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
10878 00:23:52.625824 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
10879 00:23:52.752863 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
10880 00:23:52.877518 HTTP request sent, awaiting response... 200 OK
10881 00:23:52.881221 Length: 1642760 (1.6M) [application/octet-stream]
10882 00:23:52.884854 Saving to: 'kselftest_armhf.tar.gz'
10883 00:23:52.885376
10884 00:23:52.885725
10885 00:23:53.127612 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
10886 00:23:53.376688 kselftest_armhf.tar 2%[ ] 47.81K 192KB/s
10887 00:23:53.672549 kselftest_armhf.tar 13%[=> ] 214.67K 431KB/s
10888 00:23:53.799570 kselftest_armhf.tar 52%[=========> ] 838.27K 1.03MB/s
10889 00:23:53.806351 kselftest_armhf.tar 100%[===================>] 1.57M 1.70MB/s in 0.9s
10890 00:23:53.806927
10891 00:23:53.955964 2024-06-21 00:23:54 (1.70 MB/s) - 'kselftest_armhf.tar.gz' saved [1642760/1642760]
10892 00:23:53.956515
10893 00:23:58.344825 skiplist:
10894 00:23:58.348038 ========================================
10895 00:23:58.351396 ========================================
10896 00:23:58.392266 alsa:mixer-test
10897 00:23:58.411783 ============== Tests to run ===============
10898 00:23:58.411890 alsa:mixer-test
10899 00:23:58.415384 ===========End Tests to run ===============
10900 00:23:58.419197 shardfile-alsa pass
10901 00:23:58.516163 <12>[ 26.377175] kselftest: Running tests in alsa
10902 00:23:58.526729 TAP version 13
10903 00:23:58.541410 1..1
10904 00:23:58.556191 # selftests: alsa: mixer-test
10905 00:23:59.059602 # TAP version 13
10906 00:23:59.060115 # 1..0
10907 00:23:59.066121 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:0 error:0
10908 00:23:59.069427 ok 1 selftests: alsa: mixer-test
10909 00:24:00.568697 alsa_mixer-test pass
10910 00:24:00.650008 + ../../utils/send-to-lava.sh ./output/result.txt
10911 00:24:00.711769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
10912 00:24:00.712513 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
10914 00:24:00.757326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
10915 00:24:00.757790 + set +x
10916 00:24:00.758466 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
10918 00:24:00.763640 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 14479179_1.6.2.3.5>
10919 00:24:00.764325 Received signal: <ENDRUN> 1_kselftest-alsa 14479179_1.6.2.3.5
10920 00:24:00.764703 Ending use of test pattern.
10921 00:24:00.765030 Ending test lava.1_kselftest-alsa (14479179_1.6.2.3.5), duration 8.69
10923 00:24:00.767325 <LAVA_TEST_RUNNER EXIT>
10924 00:24:00.768000 ok: lava_test_shell seems to have completed
10925 00:24:00.768516 alsa_mixer-test: pass
shardfile-alsa: pass
10926 00:24:00.768960 end: 3.1 lava-test-shell (duration 00:00:10) [common]
10927 00:24:00.769526 end: 3 lava-test-retry (duration 00:00:10) [common]
10928 00:24:00.770006 start: 4 finalize (timeout 00:07:47) [common]
10929 00:24:00.770553 start: 4.1 power-off (timeout 00:00:30) [common]
10930 00:24:00.771398 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-4', '--port=1', '--command=off']
10931 00:24:02.894954 >> Command sent successfully.
10932 00:24:02.901467 Returned 0 in 2 seconds
10933 00:24:03.002459 end: 4.1 power-off (duration 00:00:02) [common]
10935 00:24:03.003918 start: 4.2 read-feedback (timeout 00:07:44) [common]
10936 00:24:03.005108 Listened to connection for namespace 'common' for up to 1s
10937 00:24:04.005818 Finalising connection for namespace 'common'
10938 00:24:04.006542 Disconnecting from shell: Finalise
10939 00:24:04.006972 / #
10940 00:24:04.107978 end: 4.2 read-feedback (duration 00:00:01) [common]
10941 00:24:04.108670 end: 4 finalize (duration 00:00:03) [common]
10942 00:24:04.109283 Cleaning after the job
10943 00:24:04.109827 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14479179/tftp-deploy-4yfo8uu6/ramdisk
10944 00:24:04.120081 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14479179/tftp-deploy-4yfo8uu6/kernel
10945 00:24:04.154529 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14479179/tftp-deploy-4yfo8uu6/dtb
10946 00:24:04.154841 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14479179/tftp-deploy-4yfo8uu6/nfsrootfs
10947 00:24:04.217972 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14479179/tftp-deploy-4yfo8uu6/modules
10948 00:24:04.223262 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14479179
10949 00:24:04.746393 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14479179
10950 00:24:04.746580 Job finished correctly