Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 32
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 25
1 00:21:16.011430 lava-dispatcher, installed at version: 2024.03
2 00:21:16.011659 start: 0 validate
3 00:21:16.011800 Start time: 2024-06-21 00:21:16.011793+00:00 (UTC)
4 00:21:16.011936 Using caching service: 'http://localhost/cache/?uri=%s'
5 00:21:16.012069 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 00:21:16.270418 Using caching service: 'http://localhost/cache/?uri=%s'
7 00:21:16.270583 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.94-cip23%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 00:21:16.519808 Using caching service: 'http://localhost/cache/?uri=%s'
9 00:21:16.520047 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.94-cip23%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 00:21:59.522831 Using caching service: 'http://localhost/cache/?uri=%s'
11 00:21:59.523434 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 00:22:00.034600 Using caching service: 'http://localhost/cache/?uri=%s'
13 00:22:00.035311 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.94-cip23%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 00:22:00.297317 validate duration: 44.29
16 00:22:00.298665 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 00:22:00.299241 start: 1.1 download-retry (timeout 00:10:00) [common]
18 00:22:00.299722 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 00:22:00.300333 Not decompressing ramdisk as can be used compressed.
20 00:22:00.300797 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 00:22:00.301172 saving as /var/lib/lava/dispatcher/tmp/14479184/tftp-deploy-8149qxkr/ramdisk/initrd.cpio.gz
22 00:22:00.301536 total size: 5628169 (5 MB)
23 00:22:02.590631 progress 0 % (0 MB)
24 00:22:02.600330 progress 5 % (0 MB)
25 00:22:02.609578 progress 10 % (0 MB)
26 00:22:02.617410 progress 15 % (0 MB)
27 00:22:02.623009 progress 20 % (1 MB)
28 00:22:02.627050 progress 25 % (1 MB)
29 00:22:02.630601 progress 30 % (1 MB)
30 00:22:02.633761 progress 35 % (1 MB)
31 00:22:02.636278 progress 40 % (2 MB)
32 00:22:02.639198 progress 45 % (2 MB)
33 00:22:02.641509 progress 50 % (2 MB)
34 00:22:02.643848 progress 55 % (2 MB)
35 00:22:02.646006 progress 60 % (3 MB)
36 00:22:02.647918 progress 65 % (3 MB)
37 00:22:02.649864 progress 70 % (3 MB)
38 00:22:02.651556 progress 75 % (4 MB)
39 00:22:02.653352 progress 80 % (4 MB)
40 00:22:02.654878 progress 85 % (4 MB)
41 00:22:02.656596 progress 90 % (4 MB)
42 00:22:02.658286 progress 95 % (5 MB)
43 00:22:02.659688 progress 100 % (5 MB)
44 00:22:02.659910 5 MB downloaded in 2.36 s (2.28 MB/s)
45 00:22:02.660070 end: 1.1.1 http-download (duration 00:00:02) [common]
47 00:22:02.660317 end: 1.1 download-retry (duration 00:00:02) [common]
48 00:22:02.660443 start: 1.2 download-retry (timeout 00:09:58) [common]
49 00:22:02.660532 start: 1.2.1 http-download (timeout 00:09:58) [common]
50 00:22:02.660668 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.94-cip23/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 00:22:02.660737 saving as /var/lib/lava/dispatcher/tmp/14479184/tftp-deploy-8149qxkr/kernel/Image
52 00:22:02.660799 total size: 54813184 (52 MB)
53 00:22:02.660862 No compression specified
54 00:22:02.661994 progress 0 % (0 MB)
55 00:22:02.675678 progress 5 % (2 MB)
56 00:22:02.689564 progress 10 % (5 MB)
57 00:22:02.703034 progress 15 % (7 MB)
58 00:22:02.716810 progress 20 % (10 MB)
59 00:22:02.730859 progress 25 % (13 MB)
60 00:22:02.745230 progress 30 % (15 MB)
61 00:22:02.759841 progress 35 % (18 MB)
62 00:22:02.773922 progress 40 % (20 MB)
63 00:22:02.788870 progress 45 % (23 MB)
64 00:22:02.803286 progress 50 % (26 MB)
65 00:22:02.818278 progress 55 % (28 MB)
66 00:22:02.833094 progress 60 % (31 MB)
67 00:22:02.848292 progress 65 % (34 MB)
68 00:22:02.862956 progress 70 % (36 MB)
69 00:22:02.877691 progress 75 % (39 MB)
70 00:22:02.892356 progress 80 % (41 MB)
71 00:22:02.906656 progress 85 % (44 MB)
72 00:22:02.921224 progress 90 % (47 MB)
73 00:22:02.935883 progress 95 % (49 MB)
74 00:22:02.950233 progress 100 % (52 MB)
75 00:22:02.950499 52 MB downloaded in 0.29 s (180.44 MB/s)
76 00:22:02.950659 end: 1.2.1 http-download (duration 00:00:00) [common]
78 00:22:02.950980 end: 1.2 download-retry (duration 00:00:00) [common]
79 00:22:02.951130 start: 1.3 download-retry (timeout 00:09:57) [common]
80 00:22:02.951246 start: 1.3.1 http-download (timeout 00:09:57) [common]
81 00:22:02.951416 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.94-cip23/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 00:22:02.951487 saving as /var/lib/lava/dispatcher/tmp/14479184/tftp-deploy-8149qxkr/dtb/mt8192-asurada-spherion-r0.dtb
83 00:22:02.951562 total size: 47258 (0 MB)
84 00:22:02.951622 No compression specified
85 00:22:02.952902 progress 69 % (0 MB)
86 00:22:02.953214 progress 100 % (0 MB)
87 00:22:02.953372 0 MB downloaded in 0.00 s (24.95 MB/s)
88 00:22:02.953526 end: 1.3.1 http-download (duration 00:00:00) [common]
90 00:22:02.953758 end: 1.3 download-retry (duration 00:00:00) [common]
91 00:22:02.953844 start: 1.4 download-retry (timeout 00:09:57) [common]
92 00:22:02.953927 start: 1.4.1 http-download (timeout 00:09:57) [common]
93 00:22:02.954042 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 00:22:02.954110 saving as /var/lib/lava/dispatcher/tmp/14479184/tftp-deploy-8149qxkr/nfsrootfs/full.rootfs.tar
95 00:22:02.954210 total size: 120894716 (115 MB)
96 00:22:02.954290 Using unxz to decompress xz
97 00:22:02.958348 progress 0 % (0 MB)
98 00:22:03.309925 progress 5 % (5 MB)
99 00:22:03.670834 progress 10 % (11 MB)
100 00:22:04.027891 progress 15 % (17 MB)
101 00:22:04.361957 progress 20 % (23 MB)
102 00:22:04.657094 progress 25 % (28 MB)
103 00:22:05.018327 progress 30 % (34 MB)
104 00:22:05.362474 progress 35 % (40 MB)
105 00:22:05.530662 progress 40 % (46 MB)
106 00:22:05.711811 progress 45 % (51 MB)
107 00:22:06.026690 progress 50 % (57 MB)
108 00:22:06.407156 progress 55 % (63 MB)
109 00:22:06.762461 progress 60 % (69 MB)
110 00:22:07.107618 progress 65 % (74 MB)
111 00:22:07.465404 progress 70 % (80 MB)
112 00:22:07.841494 progress 75 % (86 MB)
113 00:22:08.197701 progress 80 % (92 MB)
114 00:22:08.571359 progress 85 % (98 MB)
115 00:22:08.934788 progress 90 % (103 MB)
116 00:22:09.269126 progress 95 % (109 MB)
117 00:22:09.645604 progress 100 % (115 MB)
118 00:22:09.651414 115 MB downloaded in 6.70 s (17.22 MB/s)
119 00:22:09.651701 end: 1.4.1 http-download (duration 00:00:07) [common]
121 00:22:09.651994 end: 1.4 download-retry (duration 00:00:07) [common]
122 00:22:09.652150 start: 1.5 download-retry (timeout 00:09:51) [common]
123 00:22:09.652340 start: 1.5.1 http-download (timeout 00:09:51) [common]
124 00:22:09.652582 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.94-cip23/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 00:22:09.652685 saving as /var/lib/lava/dispatcher/tmp/14479184/tftp-deploy-8149qxkr/modules/modules.tar
126 00:22:09.652777 total size: 8618924 (8 MB)
127 00:22:09.652900 Using unxz to decompress xz
128 00:22:09.656807 progress 0 % (0 MB)
129 00:22:09.677264 progress 5 % (0 MB)
130 00:22:09.702934 progress 10 % (0 MB)
131 00:22:09.729929 progress 15 % (1 MB)
132 00:22:09.815766 progress 20 % (1 MB)
133 00:22:09.848970 progress 25 % (2 MB)
134 00:22:09.874708 progress 30 % (2 MB)
135 00:22:09.902650 progress 35 % (2 MB)
136 00:22:09.929749 progress 40 % (3 MB)
137 00:22:09.956351 progress 45 % (3 MB)
138 00:22:09.983012 progress 50 % (4 MB)
139 00:22:10.009207 progress 55 % (4 MB)
140 00:22:10.034672 progress 60 % (4 MB)
141 00:22:10.061164 progress 65 % (5 MB)
142 00:22:10.091621 progress 70 % (5 MB)
143 00:22:10.118407 progress 75 % (6 MB)
144 00:22:10.143309 progress 80 % (6 MB)
145 00:22:10.167801 progress 85 % (7 MB)
146 00:22:10.192152 progress 90 % (7 MB)
147 00:22:10.221944 progress 95 % (7 MB)
148 00:22:10.253934 progress 100 % (8 MB)
149 00:22:10.258715 8 MB downloaded in 0.61 s (13.57 MB/s)
150 00:22:10.258980 end: 1.5.1 http-download (duration 00:00:01) [common]
152 00:22:10.259255 end: 1.5 download-retry (duration 00:00:01) [common]
153 00:22:10.259349 start: 1.6 prepare-tftp-overlay (timeout 00:09:50) [common]
154 00:22:10.259445 start: 1.6.1 extract-nfsrootfs (timeout 00:09:50) [common]
155 00:22:13.862044 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14479184/extract-nfsrootfs-yktrmthu
156 00:22:13.862262 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 00:22:13.862368 start: 1.6.2 lava-overlay (timeout 00:09:46) [common]
158 00:22:13.862538 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14479184/lava-overlay-6hikqjj8
159 00:22:13.862678 makedir: /var/lib/lava/dispatcher/tmp/14479184/lava-overlay-6hikqjj8/lava-14479184/bin
160 00:22:13.862786 makedir: /var/lib/lava/dispatcher/tmp/14479184/lava-overlay-6hikqjj8/lava-14479184/tests
161 00:22:13.862887 makedir: /var/lib/lava/dispatcher/tmp/14479184/lava-overlay-6hikqjj8/lava-14479184/results
162 00:22:13.862991 Creating /var/lib/lava/dispatcher/tmp/14479184/lava-overlay-6hikqjj8/lava-14479184/bin/lava-add-keys
163 00:22:13.863136 Creating /var/lib/lava/dispatcher/tmp/14479184/lava-overlay-6hikqjj8/lava-14479184/bin/lava-add-sources
164 00:22:13.863267 Creating /var/lib/lava/dispatcher/tmp/14479184/lava-overlay-6hikqjj8/lava-14479184/bin/lava-background-process-start
165 00:22:13.863397 Creating /var/lib/lava/dispatcher/tmp/14479184/lava-overlay-6hikqjj8/lava-14479184/bin/lava-background-process-stop
166 00:22:13.863529 Creating /var/lib/lava/dispatcher/tmp/14479184/lava-overlay-6hikqjj8/lava-14479184/bin/lava-common-functions
167 00:22:13.863657 Creating /var/lib/lava/dispatcher/tmp/14479184/lava-overlay-6hikqjj8/lava-14479184/bin/lava-echo-ipv4
168 00:22:13.863786 Creating /var/lib/lava/dispatcher/tmp/14479184/lava-overlay-6hikqjj8/lava-14479184/bin/lava-install-packages
169 00:22:13.863914 Creating /var/lib/lava/dispatcher/tmp/14479184/lava-overlay-6hikqjj8/lava-14479184/bin/lava-installed-packages
170 00:22:13.864042 Creating /var/lib/lava/dispatcher/tmp/14479184/lava-overlay-6hikqjj8/lava-14479184/bin/lava-os-build
171 00:22:13.864170 Creating /var/lib/lava/dispatcher/tmp/14479184/lava-overlay-6hikqjj8/lava-14479184/bin/lava-probe-channel
172 00:22:13.864297 Creating /var/lib/lava/dispatcher/tmp/14479184/lava-overlay-6hikqjj8/lava-14479184/bin/lava-probe-ip
173 00:22:13.864424 Creating /var/lib/lava/dispatcher/tmp/14479184/lava-overlay-6hikqjj8/lava-14479184/bin/lava-target-ip
174 00:22:13.864551 Creating /var/lib/lava/dispatcher/tmp/14479184/lava-overlay-6hikqjj8/lava-14479184/bin/lava-target-mac
175 00:22:13.864676 Creating /var/lib/lava/dispatcher/tmp/14479184/lava-overlay-6hikqjj8/lava-14479184/bin/lava-target-storage
176 00:22:13.864814 Creating /var/lib/lava/dispatcher/tmp/14479184/lava-overlay-6hikqjj8/lava-14479184/bin/lava-test-case
177 00:22:13.864943 Creating /var/lib/lava/dispatcher/tmp/14479184/lava-overlay-6hikqjj8/lava-14479184/bin/lava-test-event
178 00:22:13.865070 Creating /var/lib/lava/dispatcher/tmp/14479184/lava-overlay-6hikqjj8/lava-14479184/bin/lava-test-feedback
179 00:22:13.865197 Creating /var/lib/lava/dispatcher/tmp/14479184/lava-overlay-6hikqjj8/lava-14479184/bin/lava-test-raise
180 00:22:13.865323 Creating /var/lib/lava/dispatcher/tmp/14479184/lava-overlay-6hikqjj8/lava-14479184/bin/lava-test-reference
181 00:22:13.865449 Creating /var/lib/lava/dispatcher/tmp/14479184/lava-overlay-6hikqjj8/lava-14479184/bin/lava-test-runner
182 00:22:13.865576 Creating /var/lib/lava/dispatcher/tmp/14479184/lava-overlay-6hikqjj8/lava-14479184/bin/lava-test-set
183 00:22:13.865705 Creating /var/lib/lava/dispatcher/tmp/14479184/lava-overlay-6hikqjj8/lava-14479184/bin/lava-test-shell
184 00:22:13.865834 Updating /var/lib/lava/dispatcher/tmp/14479184/lava-overlay-6hikqjj8/lava-14479184/bin/lava-add-keys (debian)
185 00:22:13.865988 Updating /var/lib/lava/dispatcher/tmp/14479184/lava-overlay-6hikqjj8/lava-14479184/bin/lava-add-sources (debian)
186 00:22:13.866137 Updating /var/lib/lava/dispatcher/tmp/14479184/lava-overlay-6hikqjj8/lava-14479184/bin/lava-install-packages (debian)
187 00:22:13.866543 Updating /var/lib/lava/dispatcher/tmp/14479184/lava-overlay-6hikqjj8/lava-14479184/bin/lava-installed-packages (debian)
188 00:22:13.866700 Updating /var/lib/lava/dispatcher/tmp/14479184/lava-overlay-6hikqjj8/lava-14479184/bin/lava-os-build (debian)
189 00:22:13.866827 Creating /var/lib/lava/dispatcher/tmp/14479184/lava-overlay-6hikqjj8/lava-14479184/environment
190 00:22:13.866935 LAVA metadata
191 00:22:13.867006 - LAVA_JOB_ID=14479184
192 00:22:13.867072 - LAVA_DISPATCHER_IP=192.168.201.1
193 00:22:13.867180 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:46) [common]
194 00:22:13.867251 skipped lava-vland-overlay
195 00:22:13.867329 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 00:22:13.867410 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:46) [common]
197 00:22:13.867473 skipped lava-multinode-overlay
198 00:22:13.867547 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 00:22:13.867627 start: 1.6.2.3 test-definition (timeout 00:09:46) [common]
200 00:22:13.867703 Loading test definitions
201 00:22:13.867795 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:46) [common]
202 00:22:13.867868 Using /lava-14479184 at stage 0
203 00:22:13.868156 uuid=14479184_1.6.2.3.1 testdef=None
204 00:22:13.868247 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 00:22:13.868334 start: 1.6.2.3.2 test-overlay (timeout 00:09:46) [common]
206 00:22:13.868803 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 00:22:13.869030 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:46) [common]
209 00:22:13.869595 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 00:22:13.869829 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:46) [common]
212 00:22:13.870386 runner path: /var/lib/lava/dispatcher/tmp/14479184/lava-overlay-6hikqjj8/lava-14479184/0/tests/0_timesync-off test_uuid 14479184_1.6.2.3.1
213 00:22:13.870550 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 00:22:13.870779 start: 1.6.2.3.5 git-repo-action (timeout 00:09:46) [common]
216 00:22:13.870854 Using /lava-14479184 at stage 0
217 00:22:13.870956 Fetching tests from https://github.com/kernelci/test-definitions.git
218 00:22:13.871046 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14479184/lava-overlay-6hikqjj8/lava-14479184/0/tests/1_kselftest-arm64'
219 00:22:17.188923 Running '/usr/bin/git checkout kernelci.org
220 00:22:17.303222 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14479184/lava-overlay-6hikqjj8/lava-14479184/0/tests/1_kselftest-arm64/automated/linux/kselftest/kselftest.yaml
221 00:22:17.303962 uuid=14479184_1.6.2.3.5 testdef=None
222 00:22:17.304121 end: 1.6.2.3.5 git-repo-action (duration 00:00:03) [common]
224 00:22:17.304374 start: 1.6.2.3.6 test-overlay (timeout 00:09:43) [common]
225 00:22:17.305122 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 00:22:17.305364 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:43) [common]
228 00:22:17.306381 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 00:22:17.306626 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:43) [common]
231 00:22:17.307556 runner path: /var/lib/lava/dispatcher/tmp/14479184/lava-overlay-6hikqjj8/lava-14479184/0/tests/1_kselftest-arm64 test_uuid 14479184_1.6.2.3.5
232 00:22:17.307648 BOARD='mt8192-asurada-spherion-r0'
233 00:22:17.307713 BRANCH='cip'
234 00:22:17.307772 SKIPFILE='/dev/null'
235 00:22:17.307831 SKIP_INSTALL='True'
236 00:22:17.307887 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.94-cip23/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 00:22:17.307955 TST_CASENAME=''
238 00:22:17.308015 TST_CMDFILES='arm64'
239 00:22:17.308156 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 00:22:17.308361 Creating lava-test-runner.conf files
242 00:22:17.308426 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14479184/lava-overlay-6hikqjj8/lava-14479184/0 for stage 0
243 00:22:17.308520 - 0_timesync-off
244 00:22:17.308593 - 1_kselftest-arm64
245 00:22:17.308693 end: 1.6.2.3 test-definition (duration 00:00:03) [common]
246 00:22:17.308782 start: 1.6.2.4 compress-overlay (timeout 00:09:43) [common]
247 00:22:24.867993 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 00:22:24.868146 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:35) [common]
249 00:22:24.868242 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 00:22:24.868342 end: 1.6.2 lava-overlay (duration 00:00:11) [common]
251 00:22:24.868458 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:35) [common]
252 00:22:25.035492 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 00:22:25.035876 start: 1.6.4 extract-modules (timeout 00:09:35) [common]
254 00:22:25.035993 extracting modules file /var/lib/lava/dispatcher/tmp/14479184/tftp-deploy-8149qxkr/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14479184/extract-nfsrootfs-yktrmthu
255 00:22:25.264656 extracting modules file /var/lib/lava/dispatcher/tmp/14479184/tftp-deploy-8149qxkr/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14479184/extract-overlay-ramdisk-n8ng291r/ramdisk
256 00:22:25.501191 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 00:22:25.501388 start: 1.6.5 apply-overlay-tftp (timeout 00:09:35) [common]
258 00:22:25.501492 [common] Applying overlay to NFS
259 00:22:25.501564 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14479184/compress-overlay-1hupj1ts/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14479184/extract-nfsrootfs-yktrmthu
260 00:22:26.439755 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 00:22:26.439929 start: 1.6.6 configure-preseed-file (timeout 00:09:34) [common]
262 00:22:26.440024 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 00:22:26.440111 start: 1.6.7 compress-ramdisk (timeout 00:09:34) [common]
264 00:22:26.440195 Building ramdisk /var/lib/lava/dispatcher/tmp/14479184/extract-overlay-ramdisk-n8ng291r/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14479184/extract-overlay-ramdisk-n8ng291r/ramdisk
265 00:22:27.099836 >> 130487 blocks
266 00:22:29.152547 rename /var/lib/lava/dispatcher/tmp/14479184/extract-overlay-ramdisk-n8ng291r/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14479184/tftp-deploy-8149qxkr/ramdisk/ramdisk.cpio.gz
267 00:22:29.153005 end: 1.6.7 compress-ramdisk (duration 00:00:03) [common]
268 00:22:29.153134 start: 1.6.8 prepare-kernel (timeout 00:09:31) [common]
269 00:22:29.153241 start: 1.6.8.1 prepare-fit (timeout 00:09:31) [common]
270 00:22:29.153349 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14479184/tftp-deploy-8149qxkr/kernel/Image']
271 00:22:43.616389 Returned 0 in 14 seconds
272 00:22:43.717022 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14479184/tftp-deploy-8149qxkr/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14479184/tftp-deploy-8149qxkr/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14479184/tftp-deploy-8149qxkr/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14479184/tftp-deploy-8149qxkr/kernel/image.itb
273 00:22:44.095221 output: FIT description: Kernel Image image with one or more FDT blobs
274 00:22:44.095885 output: Created: Fri Jun 21 01:22:44 2024
275 00:22:44.096067 output: Image 0 (kernel-1)
276 00:22:44.096229 output: Description:
277 00:22:44.096386 output: Created: Fri Jun 21 01:22:44 2024
278 00:22:44.096539 output: Type: Kernel Image
279 00:22:44.096720 output: Compression: lzma compressed
280 00:22:44.096866 output: Data Size: 13124896 Bytes = 12817.28 KiB = 12.52 MiB
281 00:22:44.097013 output: Architecture: AArch64
282 00:22:44.097156 output: OS: Linux
283 00:22:44.097296 output: Load Address: 0x00000000
284 00:22:44.097434 output: Entry Point: 0x00000000
285 00:22:44.097571 output: Hash algo: crc32
286 00:22:44.097707 output: Hash value: ab2f7826
287 00:22:44.097899 output: Image 1 (fdt-1)
288 00:22:44.098065 output: Description: mt8192-asurada-spherion-r0
289 00:22:44.098237 output: Created: Fri Jun 21 01:22:44 2024
290 00:22:44.098410 output: Type: Flat Device Tree
291 00:22:44.098549 output: Compression: uncompressed
292 00:22:44.098685 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
293 00:22:44.098861 output: Architecture: AArch64
294 00:22:44.099013 output: Hash algo: crc32
295 00:22:44.099151 output: Hash value: 0f8e4d2e
296 00:22:44.099330 output: Image 2 (ramdisk-1)
297 00:22:44.099483 output: Description: unavailable
298 00:22:44.099623 output: Created: Fri Jun 21 01:22:44 2024
299 00:22:44.099763 output: Type: RAMDisk Image
300 00:22:44.099904 output: Compression: Unknown Compression
301 00:22:44.100044 output: Data Size: 18747860 Bytes = 18308.46 KiB = 17.88 MiB
302 00:22:44.100197 output: Architecture: AArch64
303 00:22:44.100342 output: OS: Linux
304 00:22:44.100484 output: Load Address: unavailable
305 00:22:44.100623 output: Entry Point: unavailable
306 00:22:44.100764 output: Hash algo: crc32
307 00:22:44.100904 output: Hash value: 26c10f58
308 00:22:44.101044 output: Default Configuration: 'conf-1'
309 00:22:44.101184 output: Configuration 0 (conf-1)
310 00:22:44.101324 output: Description: mt8192-asurada-spherion-r0
311 00:22:44.101464 output: Kernel: kernel-1
312 00:22:44.101604 output: Init Ramdisk: ramdisk-1
313 00:22:44.101745 output: FDT: fdt-1
314 00:22:44.101884 output: Loadables: kernel-1
315 00:22:44.102021 output:
316 00:22:44.102425 end: 1.6.8.1 prepare-fit (duration 00:00:15) [common]
317 00:22:44.102649 end: 1.6.8 prepare-kernel (duration 00:00:15) [common]
318 00:22:44.102899 end: 1.6 prepare-tftp-overlay (duration 00:00:34) [common]
319 00:22:44.103117 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:16) [common]
320 00:22:44.103295 No LXC device requested
321 00:22:44.103510 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 00:22:44.103710 start: 1.8 deploy-device-env (timeout 00:09:16) [common]
323 00:22:44.103894 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 00:22:44.104056 Checking files for TFTP limit of 4294967296 bytes.
325 00:22:44.105139 end: 1 tftp-deploy (duration 00:00:44) [common]
326 00:22:44.105370 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 00:22:44.105577 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 00:22:44.105854 substitutions:
329 00:22:44.106014 - {DTB}: 14479184/tftp-deploy-8149qxkr/dtb/mt8192-asurada-spherion-r0.dtb
330 00:22:44.106179 - {INITRD}: 14479184/tftp-deploy-8149qxkr/ramdisk/ramdisk.cpio.gz
331 00:22:44.106375 - {KERNEL}: 14479184/tftp-deploy-8149qxkr/kernel/Image
332 00:22:44.106520 - {LAVA_MAC}: None
333 00:22:44.106694 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14479184/extract-nfsrootfs-yktrmthu
334 00:22:44.106837 - {NFS_SERVER_IP}: 192.168.201.1
335 00:22:44.106979 - {PRESEED_CONFIG}: None
336 00:22:44.107119 - {PRESEED_LOCAL}: None
337 00:22:44.107257 - {RAMDISK}: 14479184/tftp-deploy-8149qxkr/ramdisk/ramdisk.cpio.gz
338 00:22:44.107444 - {ROOT_PART}: None
339 00:22:44.107642 - {ROOT}: None
340 00:22:44.107784 - {SERVER_IP}: 192.168.201.1
341 00:22:44.107926 - {TEE}: None
342 00:22:44.108067 Parsed boot commands:
343 00:22:44.108221 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 00:22:44.108601 Parsed boot commands: tftpboot 192.168.201.1 14479184/tftp-deploy-8149qxkr/kernel/image.itb 14479184/tftp-deploy-8149qxkr/kernel/cmdline
345 00:22:44.108801 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 00:22:44.108992 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 00:22:44.109199 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 00:22:44.109428 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 00:22:44.109672 Not connected, no need to disconnect.
350 00:22:44.109965 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 00:22:44.110168 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 00:22:44.110350 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-9'
353 00:22:44.115293 Setting prompt string to ['lava-test: # ']
354 00:22:44.116011 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 00:22:44.116251 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 00:22:44.116563 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 00:22:44.116768 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 00:22:44.117181 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-9']
359 00:22:58.142092 Returned 0 in 14 seconds
360 00:22:58.243162 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
362 00:22:58.244739 end: 2.2.2 reset-device (duration 00:00:14) [common]
363 00:22:58.245320 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
364 00:22:58.245847 Setting prompt string to 'Starting depthcharge on Spherion...'
365 00:22:58.246286 Changing prompt to 'Starting depthcharge on Spherion...'
366 00:22:58.246718 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
367 00:22:58.248963 [Enter `^Ec?' for help]
368 00:22:58.249405
369 00:22:58.249855 F0: 102B 0000
370 00:22:58.250308
371 00:22:58.250659 F3: 1001 0000 [0200]
372 00:22:58.251181
373 00:22:58.251631 F3: 1001 0000
374 00:22:58.251954
375 00:22:58.252432 F7: 102D 0000
376 00:22:58.252836
377 00:22:58.253134 F1: 0000 0000
378 00:22:58.253524
379 00:22:58.253815 V0: 0000 0000 [0001]
380 00:22:58.254307
381 00:22:58.254668 00: 0007 8000
382 00:22:58.254986
383 00:22:58.255290 01: 0000 0000
384 00:22:58.255582
385 00:22:58.255881 BP: 0C00 0209 [0000]
386 00:22:58.256166
387 00:22:58.256440 G0: 1182 0000
388 00:22:58.256792
389 00:22:58.257083 EC: 0000 0021 [4000]
390 00:22:58.257387
391 00:22:58.257663 S7: 0000 0000 [0000]
392 00:22:58.257976
393 00:22:58.258283 CC: 0000 0000 [0001]
394 00:22:58.258604
395 00:22:58.258882 T0: 0000 0040 [010F]
396 00:22:58.259190
397 00:22:58.259466 Jump to BL
398 00:22:58.259759
399 00:22:58.260039
400 00:22:58.260330
401 00:22:58.260610 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
402 00:22:58.260915 ARM64: Exception handlers installed.
403 00:22:58.261207 ARM64: Testing exception
404 00:22:58.261482 ARM64: Done test exception
405 00:22:58.261783 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
406 00:22:58.262094 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
407 00:22:58.262455 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
408 00:22:58.262739 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
409 00:22:58.263057 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
410 00:22:58.263339 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
411 00:22:58.263647 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
412 00:22:58.263932 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
413 00:22:58.264246 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
414 00:22:58.264529 WDT: Last reset was cold boot
415 00:22:58.264827 SPI1(PAD0) initialized at 2873684 Hz
416 00:22:58.265105 SPI5(PAD0) initialized at 992727 Hz
417 00:22:58.265448 VBOOT: Loading verstage.
418 00:22:58.265728 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
419 00:22:58.266030 FMAP: Found "FLASH" version 1.1 at 0x20000.
420 00:22:58.266406 FMAP: base = 0x0 size = 0x800000 #areas = 25
421 00:22:58.266713 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
422 00:22:58.266998 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
423 00:22:58.267296 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
424 00:22:58.267580 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
425 00:22:58.267855
426 00:22:58.268155
427 00:22:58.268473 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
428 00:22:58.268790 ARM64: Exception handlers installed.
429 00:22:58.269074 ARM64: Testing exception
430 00:22:58.269379 ARM64: Done test exception
431 00:22:58.269656 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
432 00:22:58.269966 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
433 00:22:58.270275 Probing TPM: . done!
434 00:22:58.270599 TPM ready after 0 ms
435 00:22:58.270820 Connected to device vid:did:rid of 1ae0:0028:00
436 00:22:58.271034 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
437 00:22:58.271241 Initialized TPM device CR50 revision 0
438 00:22:58.271438 tlcl_send_startup: Startup return code is 0
439 00:22:58.271657 TPM: setup succeeded
440 00:22:58.271881 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
441 00:22:58.272080 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
442 00:22:58.272292 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
443 00:22:58.272495 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
444 00:22:58.272688 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
445 00:22:58.272895 in-header: 03 07 00 00 08 00 00 00
446 00:22:58.273098 in-data: aa e4 47 04 13 02 00 00
447 00:22:58.273292 Chrome EC: UHEPI supported
448 00:22:58.273500 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
449 00:22:58.273706 in-header: 03 a9 00 00 08 00 00 00
450 00:22:58.273901 in-data: 84 60 60 08 00 00 00 00
451 00:22:58.274095 Phase 1
452 00:22:58.274355 FMAP: area GBB found @ 3f5000 (12032 bytes)
453 00:22:58.274559 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
454 00:22:58.274772 VB2:vb2_check_recovery() Recovery was requested manually
455 00:22:58.274975 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
456 00:22:58.275174 Recovery requested (1009000e)
457 00:22:58.275386 TPM: Extending digest for VBOOT: boot mode into PCR 0
458 00:22:58.275539 tlcl_extend: response is 0
459 00:22:58.275687 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
460 00:22:58.275836 tlcl_extend: response is 0
461 00:22:58.275993 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
462 00:22:58.276146 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
463 00:22:58.276294 BS: bootblock times (exec / console): total (unknown) / 148 ms
464 00:22:58.276441
465 00:22:58.276599
466 00:22:58.276748 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
467 00:22:58.276898 ARM64: Exception handlers installed.
468 00:22:58.277044 ARM64: Testing exception
469 00:22:58.277213 ARM64: Done test exception
470 00:22:58.277361 pmic_efuse_setting: Set efuses in 11 msecs
471 00:22:58.277508 pmwrap_interface_init: Select PMIF_VLD_RDY
472 00:22:58.277654 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
473 00:22:58.278075 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
474 00:22:58.278267 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
475 00:22:58.278440 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
476 00:22:58.278592 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
477 00:22:58.278740 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
478 00:22:58.278888 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
479 00:22:58.279078 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
480 00:22:58.279281 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
481 00:22:58.279434 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
482 00:22:58.279603 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
483 00:22:58.279785 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
484 00:22:58.279956 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
485 00:22:58.280107 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
486 00:22:58.280349 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
487 00:22:58.280561 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
488 00:22:58.280754 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
489 00:22:58.280942 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
490 00:22:58.281128 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
491 00:22:58.281313 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
492 00:22:58.281439 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
493 00:22:58.281560 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
494 00:22:58.281680 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
495 00:22:58.281849 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
496 00:22:58.282044 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
497 00:22:58.282231 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
498 00:22:58.282368 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
499 00:22:58.282502 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
500 00:22:58.282626 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
501 00:22:58.282743 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
502 00:22:58.282861 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
503 00:22:58.283004 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
504 00:22:58.283146 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
505 00:22:58.283271 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
506 00:22:58.283436 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
507 00:22:58.283558 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
508 00:22:58.283686 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
509 00:22:58.283809 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
510 00:22:58.283928 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
511 00:22:58.284046 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
512 00:22:58.284165 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
513 00:22:58.284296 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
514 00:22:58.284417 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
515 00:22:58.284534 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
516 00:22:58.284652 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
517 00:22:58.284769 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
518 00:22:58.284929 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
519 00:22:58.285115 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
520 00:22:58.285299 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
521 00:22:58.285442 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
522 00:22:58.285545 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
523 00:22:58.285644 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
524 00:22:58.285745 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
525 00:22:58.285845 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
526 00:22:58.285945 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
527 00:22:58.286114 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
528 00:22:58.286277 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
529 00:22:58.286383 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
530 00:22:58.286485 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
531 00:22:58.286593 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x2b
532 00:22:58.286697 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
533 00:22:58.286802 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
534 00:22:58.286901 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
535 00:22:58.287000 [RTC]rtc_get_frequency_meter,154: input=15, output=835
536 00:22:58.287099 [RTC]rtc_get_frequency_meter,154: input=7, output=709
537 00:22:58.287210 [RTC]rtc_get_frequency_meter,154: input=11, output=773
538 00:22:58.287311 [RTC]rtc_get_frequency_meter,154: input=13, output=804
539 00:22:58.287411 [RTC]rtc_get_frequency_meter,154: input=12, output=788
540 00:22:58.287509 [RTC]rtc_get_frequency_meter,154: input=12, output=789
541 00:22:58.287607 [RTC]rtc_get_frequency_meter,154: input=13, output=805
542 00:22:58.287704 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
543 00:22:58.288038 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
544 00:22:58.288150 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
545 00:22:58.288251 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
546 00:22:58.288358 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
547 00:22:58.288461 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
548 00:22:58.288559 ADC[4]: Raw value=904509 ID=7
549 00:22:58.288659 ADC[3]: Raw value=213652 ID=1
550 00:22:58.288757 RAM Code: 0x71
551 00:22:58.288855 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
552 00:22:58.288988 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
553 00:22:58.289148 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
554 00:22:58.289305 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
555 00:22:58.289460 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
556 00:22:58.289580 in-header: 03 07 00 00 08 00 00 00
557 00:22:58.289680 in-data: aa e4 47 04 13 02 00 00
558 00:22:58.289778 Chrome EC: UHEPI supported
559 00:22:58.289877 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
560 00:22:58.289977 in-header: 03 a9 00 00 08 00 00 00
561 00:22:58.290075 in-data: 84 60 60 08 00 00 00 00
562 00:22:58.290232 MRC: failed to locate region type 0.
563 00:22:58.290349 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
564 00:22:58.290435 DRAM-K: Running full calibration
565 00:22:58.290519 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
566 00:22:58.290604 header.status = 0x0
567 00:22:58.290689 header.version = 0x6 (expected: 0x6)
568 00:22:58.290781 header.size = 0xd00 (expected: 0xd00)
569 00:22:58.290866 header.flags = 0x0
570 00:22:58.290951 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
571 00:22:58.291036 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
572 00:22:58.291121 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
573 00:22:58.291206 dram_init: ddr_geometry: 2
574 00:22:58.291301 [EMI] MDL number = 2
575 00:22:58.291418 [EMI] Get MDL freq = 0
576 00:22:58.291505 dram_init: ddr_type: 0
577 00:22:58.291589 is_discrete_lpddr4: 1
578 00:22:58.291673 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
579 00:22:58.291758
580 00:22:58.291842
581 00:22:58.291933 [Bian_co] ETT version 0.0.0.1
582 00:22:58.292019 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
583 00:22:58.292125
584 00:22:58.292211 dramc_set_vcore_voltage set vcore to 650000
585 00:22:58.292297 Read voltage for 800, 4
586 00:22:58.292382 Vio18 = 0
587 00:22:58.292478 Vcore = 650000
588 00:22:58.292564 Vdram = 0
589 00:22:58.292648 Vddq = 0
590 00:22:58.292732 Vmddr = 0
591 00:22:58.292816 dram_init: config_dvfs: 1
592 00:22:58.292901 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
593 00:22:58.292986 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
594 00:22:58.293081 [SwImpedanceCal] DRVP=8, DRVN=15, ODTN=9
595 00:22:58.293167 freq_region=0, Reg: DRVP=8, DRVN=15, ODTN=9
596 00:22:58.293253 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
597 00:22:58.293338 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
598 00:22:58.293422 MEM_TYPE=3, freq_sel=18
599 00:22:58.293507 sv_algorithm_assistance_LP4_1600
600 00:22:58.293591 ============ PULL DRAM RESETB DOWN ============
601 00:22:58.293693 ========== PULL DRAM RESETB DOWN end =========
602 00:22:58.293782 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
603 00:22:58.293868 ===================================
604 00:22:58.293953 LPDDR4 DRAM CONFIGURATION
605 00:22:58.294038 ===================================
606 00:22:58.294123 EX_ROW_EN[0] = 0x0
607 00:22:58.294225 EX_ROW_EN[1] = 0x0
608 00:22:58.294312 LP4Y_EN = 0x0
609 00:22:58.294397 WORK_FSP = 0x0
610 00:22:58.294481 WL = 0x2
611 00:22:58.294565 RL = 0x2
612 00:22:58.294649 BL = 0x2
613 00:22:58.294733 RPST = 0x0
614 00:22:58.294825 RD_PRE = 0x0
615 00:22:58.294909 WR_PRE = 0x1
616 00:22:58.294993 WR_PST = 0x0
617 00:22:58.295076 DBI_WR = 0x0
618 00:22:58.295160 DBI_RD = 0x0
619 00:22:58.295244 OTF = 0x1
620 00:22:58.295345 ===================================
621 00:22:58.295420 ===================================
622 00:22:58.295494 ANA top config
623 00:22:58.295568 ===================================
624 00:22:58.295642 DLL_ASYNC_EN = 0
625 00:22:58.295715 ALL_SLAVE_EN = 1
626 00:22:58.295789 NEW_RANK_MODE = 1
627 00:22:58.295864 DLL_IDLE_MODE = 1
628 00:22:58.295947 LP45_APHY_COMB_EN = 1
629 00:22:58.296021 TX_ODT_DIS = 1
630 00:22:58.296096 NEW_8X_MODE = 1
631 00:22:58.296170 ===================================
632 00:22:58.296244 ===================================
633 00:22:58.296318 data_rate = 1600
634 00:22:58.296392 CKR = 1
635 00:22:58.296466 DQ_P2S_RATIO = 8
636 00:22:58.296547 ===================================
637 00:22:58.296621 CA_P2S_RATIO = 8
638 00:22:58.296695 DQ_CA_OPEN = 0
639 00:22:58.296769 DQ_SEMI_OPEN = 0
640 00:22:58.296843 CA_SEMI_OPEN = 0
641 00:22:58.296916 CA_FULL_RATE = 0
642 00:22:58.296990 DQ_CKDIV4_EN = 1
643 00:22:58.297070 CA_CKDIV4_EN = 1
644 00:22:58.297144 CA_PREDIV_EN = 0
645 00:22:58.297218 PH8_DLY = 0
646 00:22:58.297292 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
647 00:22:58.297366 DQ_AAMCK_DIV = 4
648 00:22:58.297439 CA_AAMCK_DIV = 4
649 00:22:58.297513 CA_ADMCK_DIV = 4
650 00:22:58.297587 DQ_TRACK_CA_EN = 0
651 00:22:58.297667 CA_PICK = 800
652 00:22:58.297742 CA_MCKIO = 800
653 00:22:58.297816 MCKIO_SEMI = 0
654 00:22:58.297889 PLL_FREQ = 3068
655 00:22:58.297963 DQ_UI_PI_RATIO = 32
656 00:22:58.298037 CA_UI_PI_RATIO = 0
657 00:22:58.298110 ===================================
658 00:22:58.298196 ===================================
659 00:22:58.298279 memory_type:LPDDR4
660 00:22:58.298353 GP_NUM : 10
661 00:22:58.298425 SRAM_EN : 1
662 00:22:58.298477 MD32_EN : 0
663 00:22:58.298754 ===================================
664 00:22:58.298833 [ANA_INIT] >>>>>>>>>>>>>>
665 00:22:58.298888 <<<<<< [CONFIGURE PHASE]: ANA_TX
666 00:22:58.298944 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
667 00:22:58.298997 ===================================
668 00:22:58.299051 data_rate = 1600,PCW = 0X7600
669 00:22:58.299104 ===================================
670 00:22:58.299157 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
671 00:22:58.299211 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
672 00:22:58.299264 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
673 00:22:58.299319 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
674 00:22:58.299376 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
675 00:22:58.299447 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
676 00:22:58.299514 [ANA_INIT] flow start
677 00:22:58.299566 [ANA_INIT] PLL >>>>>>>>
678 00:22:58.299619 [ANA_INIT] PLL <<<<<<<<
679 00:22:58.299672 [ANA_INIT] MIDPI >>>>>>>>
680 00:22:58.299724 [ANA_INIT] MIDPI <<<<<<<<
681 00:22:58.299776 [ANA_INIT] DLL >>>>>>>>
682 00:22:58.299828 [ANA_INIT] flow end
683 00:22:58.299888 ============ LP4 DIFF to SE enter ============
684 00:22:58.299942 ============ LP4 DIFF to SE exit ============
685 00:22:58.300011 [ANA_INIT] <<<<<<<<<<<<<
686 00:22:58.300078 [Flow] Enable top DCM control >>>>>
687 00:22:58.300150 [Flow] Enable top DCM control <<<<<
688 00:22:58.300235 Enable DLL master slave shuffle
689 00:22:58.300319 ==============================================================
690 00:22:58.300390 Gating Mode config
691 00:22:58.300462 ==============================================================
692 00:22:58.300547 Config description:
693 00:22:58.300601 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
694 00:22:58.300657 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
695 00:22:58.300712 SELPH_MODE 0: By rank 1: By Phase
696 00:22:58.300766 ==============================================================
697 00:22:58.300821 GAT_TRACK_EN = 1
698 00:22:58.300875 RX_GATING_MODE = 2
699 00:22:58.300934 RX_GATING_TRACK_MODE = 2
700 00:22:58.300989 SELPH_MODE = 1
701 00:22:58.301042 PICG_EARLY_EN = 1
702 00:22:58.301096 VALID_LAT_VALUE = 1
703 00:22:58.301150 ==============================================================
704 00:22:58.301204 Enter into Gating configuration >>>>
705 00:22:58.301258 Exit from Gating configuration <<<<
706 00:22:58.301312 Enter into DVFS_PRE_config >>>>>
707 00:22:58.301366 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
708 00:22:58.301425 Exit from DVFS_PRE_config <<<<<
709 00:22:58.301487 Enter into PICG configuration >>>>
710 00:22:58.301541 Exit from PICG configuration <<<<
711 00:22:58.301595 [RX_INPUT] configuration >>>>>
712 00:22:58.301649 [RX_INPUT] configuration <<<<<
713 00:22:58.301702 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
714 00:22:58.301757 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
715 00:22:58.301810 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
716 00:22:58.301866 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
717 00:22:58.301919 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
718 00:22:58.301978 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
719 00:22:58.302064 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
720 00:22:58.302150 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
721 00:22:58.302236 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
722 00:22:58.302290 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
723 00:22:58.302343 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
724 00:22:58.302396 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
725 00:22:58.302449 ===================================
726 00:22:58.302508 LPDDR4 DRAM CONFIGURATION
727 00:22:58.302561 ===================================
728 00:22:58.302614 EX_ROW_EN[0] = 0x0
729 00:22:58.302667 EX_ROW_EN[1] = 0x0
730 00:22:58.302720 LP4Y_EN = 0x0
731 00:22:58.302772 WORK_FSP = 0x0
732 00:22:58.302825 WL = 0x2
733 00:22:58.302877 RL = 0x2
734 00:22:58.302929 BL = 0x2
735 00:22:58.302982 RPST = 0x0
736 00:22:58.303039 RD_PRE = 0x0
737 00:22:58.303092 WR_PRE = 0x1
738 00:22:58.303144 WR_PST = 0x0
739 00:22:58.303197 DBI_WR = 0x0
740 00:22:58.303249 DBI_RD = 0x0
741 00:22:58.303301 OTF = 0x1
742 00:22:58.303354 ===================================
743 00:22:58.303407 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
744 00:22:58.303460 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
745 00:22:58.303512 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
746 00:22:58.303572 ===================================
747 00:22:58.303625 LPDDR4 DRAM CONFIGURATION
748 00:22:58.303678 ===================================
749 00:22:58.303731 EX_ROW_EN[0] = 0x10
750 00:22:58.303784 EX_ROW_EN[1] = 0x0
751 00:22:58.303836 LP4Y_EN = 0x0
752 00:22:58.303888 WORK_FSP = 0x0
753 00:22:58.303941 WL = 0x2
754 00:22:58.303993 RL = 0x2
755 00:22:58.304045 BL = 0x2
756 00:22:58.304104 RPST = 0x0
757 00:22:58.304157 RD_PRE = 0x0
758 00:22:58.304210 WR_PRE = 0x1
759 00:22:58.304262 WR_PST = 0x0
760 00:22:58.304314 DBI_WR = 0x0
761 00:22:58.304366 DBI_RD = 0x0
762 00:22:58.304418 OTF = 0x1
763 00:22:58.304471 ===================================
764 00:22:58.304524 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
765 00:22:58.304577 nWR fixed to 40
766 00:22:58.304637 [ModeRegInit_LP4] CH0 RK0
767 00:22:58.304691 [ModeRegInit_LP4] CH0 RK1
768 00:22:58.304743 [ModeRegInit_LP4] CH1 RK0
769 00:22:58.304796 [ModeRegInit_LP4] CH1 RK1
770 00:22:58.304848 match AC timing 13
771 00:22:58.305093 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
772 00:22:58.305160 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
773 00:22:58.305216 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
774 00:22:58.305270 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
775 00:22:58.305323 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
776 00:22:58.305376 [EMI DOE] emi_dcm 0
777 00:22:58.305429 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
778 00:22:58.305482 ==
779 00:22:58.305535 Dram Type= 6, Freq= 0, CH_0, rank 0
780 00:22:58.305588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 00:22:58.305645 ==
782 00:22:58.305726 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
783 00:22:58.305782 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
784 00:22:58.305836 [CA 0] Center 37 (7~68) winsize 62
785 00:22:58.305889 [CA 1] Center 37 (6~68) winsize 63
786 00:22:58.305942 [CA 2] Center 34 (4~65) winsize 62
787 00:22:58.305996 [CA 3] Center 34 (4~65) winsize 62
788 00:22:58.306048 [CA 4] Center 33 (3~64) winsize 62
789 00:22:58.306101 [CA 5] Center 33 (3~64) winsize 62
790 00:22:58.306153
791 00:22:58.306253 [CmdBusTrainingLP45] Vref(ca) range 1: 34
792 00:22:58.306308
793 00:22:58.306360 [CATrainingPosCal] consider 1 rank data
794 00:22:58.306413 u2DelayCellTimex100 = 270/100 ps
795 00:22:58.306465 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
796 00:22:58.306519 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
797 00:22:58.306572 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
798 00:22:58.306625 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
799 00:22:58.306679 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
800 00:22:58.306738 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
801 00:22:58.306798
802 00:22:58.306852 CA PerBit enable=1, Macro0, CA PI delay=33
803 00:22:58.306905
804 00:22:58.306958 [CBTSetCACLKResult] CA Dly = 33
805 00:22:58.307011 CS Dly: 6 (0~37)
806 00:22:58.307064 ==
807 00:22:58.307117 Dram Type= 6, Freq= 0, CH_0, rank 1
808 00:22:58.307170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
809 00:22:58.307226 ==
810 00:22:58.307281 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
811 00:22:58.307334 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
812 00:22:58.307387 [CA 0] Center 37 (6~68) winsize 63
813 00:22:58.307440 [CA 1] Center 37 (7~68) winsize 62
814 00:22:58.307492 [CA 2] Center 34 (4~65) winsize 62
815 00:22:58.307545 [CA 3] Center 34 (4~65) winsize 62
816 00:22:58.307597 [CA 4] Center 33 (3~64) winsize 62
817 00:22:58.307649 [CA 5] Center 33 (3~64) winsize 62
818 00:22:58.307702
819 00:22:58.307758 [CmdBusTrainingLP45] Vref(ca) range 1: 34
820 00:22:58.307812
821 00:22:58.307865 [CATrainingPosCal] consider 2 rank data
822 00:22:58.307918 u2DelayCellTimex100 = 270/100 ps
823 00:22:58.307970 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
824 00:22:58.308023 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
825 00:22:58.308076 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
826 00:22:58.308129 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
827 00:22:58.308182 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
828 00:22:58.308235 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
829 00:22:58.308292
830 00:22:58.308345 CA PerBit enable=1, Macro0, CA PI delay=33
831 00:22:58.308398
832 00:22:58.308451 [CBTSetCACLKResult] CA Dly = 33
833 00:22:58.308504 CS Dly: 6 (0~38)
834 00:22:58.308557
835 00:22:58.308609 ----->DramcWriteLeveling(PI) begin...
836 00:22:58.308666 ==
837 00:22:58.308719 Dram Type= 6, Freq= 0, CH_0, rank 0
838 00:22:58.308772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
839 00:22:58.308832 ==
840 00:22:58.308885 Write leveling (Byte 0): 31 => 31
841 00:22:58.308938 Write leveling (Byte 1): 30 => 30
842 00:22:58.308991 DramcWriteLeveling(PI) end<-----
843 00:22:58.309043
844 00:22:58.309095 ==
845 00:22:58.309147 Dram Type= 6, Freq= 0, CH_0, rank 0
846 00:22:58.309200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
847 00:22:58.309254 ==
848 00:22:58.309307 [Gating] SW mode calibration
849 00:22:58.309365 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
850 00:22:58.309419 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
851 00:22:58.309472 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
852 00:22:58.309525 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
853 00:22:58.309578 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
854 00:22:58.309631 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 00:22:58.309684 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 00:22:58.309737 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 00:22:58.309790 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 00:22:58.309843 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 00:22:58.309929 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 00:22:58.310012 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 00:22:58.310095 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 00:22:58.310199 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 00:22:58.310269 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 00:22:58.310323 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 00:22:58.310379 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 00:22:58.310433 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 00:22:58.310487 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 00:22:58.310540 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
869 00:22:58.310593 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
870 00:22:58.310646 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
871 00:22:58.310698 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 00:22:58.310751 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 00:22:58.310803 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 00:22:58.310856 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 00:22:58.310915 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 00:22:58.310968 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 00:22:58.311021 0 9 8 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (0 0)
878 00:22:58.311073 0 9 12 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)
879 00:22:58.311319 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
880 00:22:58.311378 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
881 00:22:58.311467 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 00:22:58.311521 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 00:22:58.311574 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 00:22:58.311628 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
885 00:22:58.311680 0 10 8 | B1->B0 | 3333 2727 | 1 0 | (1 0) (0 0)
886 00:22:58.311733 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
887 00:22:58.311786 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
888 00:22:58.311839 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 00:22:58.311892 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 00:22:58.311945 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 00:22:58.312003 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 00:22:58.312079 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 00:22:58.312134 0 11 8 | B1->B0 | 2424 3838 | 0 1 | (0 0) (0 0)
894 00:22:58.312218 0 11 12 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
895 00:22:58.312304 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
896 00:22:58.312371 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
897 00:22:58.312423 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 00:22:58.312480 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 00:22:58.312534 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 00:22:58.312615 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
901 00:22:58.312667 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
902 00:22:58.312720 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 00:22:58.312772 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 00:22:58.312825 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 00:22:58.312878 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 00:22:58.312931 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 00:22:58.312983 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 00:22:58.313041 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 00:22:58.313095 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 00:22:58.313147 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 00:22:58.313200 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 00:22:58.313256 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 00:22:58.313310 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 00:22:58.313363 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 00:22:58.313416 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 00:22:58.313468 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 00:22:58.313525 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
918 00:22:58.313579 Total UI for P1: 0, mck2ui 16
919 00:22:58.313633 best dqsien dly found for B0: ( 0, 14, 6)
920 00:22:58.313686 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
921 00:22:58.313739 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
922 00:22:58.313792 Total UI for P1: 0, mck2ui 16
923 00:22:58.313845 best dqsien dly found for B1: ( 0, 14, 10)
924 00:22:58.313916 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
925 00:22:58.313970 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
926 00:22:58.314024
927 00:22:58.314116 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
928 00:22:58.314217 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
929 00:22:58.314273 [Gating] SW calibration Done
930 00:22:58.314326 ==
931 00:22:58.314379 Dram Type= 6, Freq= 0, CH_0, rank 0
932 00:22:58.314433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
933 00:22:58.314487 ==
934 00:22:58.314540 RX Vref Scan: 0
935 00:22:58.314598
936 00:22:58.314650 RX Vref 0 -> 0, step: 1
937 00:22:58.314703
938 00:22:58.314755 RX Delay -130 -> 252, step: 16
939 00:22:58.314808 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
940 00:22:58.314861 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
941 00:22:58.314914 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
942 00:22:58.314966 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
943 00:22:58.315019 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
944 00:22:58.315074 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
945 00:22:58.315129 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
946 00:22:58.315182 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
947 00:22:58.315235 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
948 00:22:58.315288 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
949 00:22:58.315340 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
950 00:22:58.315393 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
951 00:22:58.315446 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
952 00:22:58.315499 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
953 00:22:58.315551 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
954 00:22:58.315607 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
955 00:22:58.315661 ==
956 00:22:58.315714 Dram Type= 6, Freq= 0, CH_0, rank 0
957 00:22:58.315767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
958 00:22:58.315820 ==
959 00:22:58.315873 DQS Delay:
960 00:22:58.315925 DQS0 = 0, DQS1 = 0
961 00:22:58.315978 DQM Delay:
962 00:22:58.316030 DQM0 = 87, DQM1 = 71
963 00:22:58.316126 DQ Delay:
964 00:22:58.316192 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
965 00:22:58.316246 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =101
966 00:22:58.316299 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
967 00:22:58.316352 DQ12 =69, DQ13 =77, DQ14 =85, DQ15 =77
968 00:22:58.316404
969 00:22:58.316457
970 00:22:58.316509 ==
971 00:22:58.316562 Dram Type= 6, Freq= 0, CH_0, rank 0
972 00:22:58.316615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
973 00:22:58.316689 ==
974 00:22:58.316744
975 00:22:58.316797
976 00:22:58.316849 TX Vref Scan disable
977 00:22:58.316902 == TX Byte 0 ==
978 00:22:58.316955 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
979 00:22:58.317010 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
980 00:22:58.317063 == TX Byte 1 ==
981 00:22:58.317116 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
982 00:22:58.317174 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
983 00:22:58.317239 ==
984 00:22:58.317293 Dram Type= 6, Freq= 0, CH_0, rank 0
985 00:22:58.317346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
986 00:22:58.317399 ==
987 00:22:58.317644 TX Vref=22, minBit 4, minWin=27, winSum=443
988 00:22:58.317720 TX Vref=24, minBit 5, minWin=27, winSum=445
989 00:22:58.317780 TX Vref=26, minBit 5, minWin=27, winSum=446
990 00:22:58.317834 TX Vref=28, minBit 4, minWin=27, winSum=446
991 00:22:58.317888 TX Vref=30, minBit 1, minWin=28, winSum=451
992 00:22:58.317941 TX Vref=32, minBit 10, minWin=27, winSum=447
993 00:22:58.318013 [TxChooseVref] Worse bit 1, Min win 28, Win sum 451, Final Vref 30
994 00:22:58.318068
995 00:22:58.318132 Final TX Range 1 Vref 30
996 00:22:58.318232
997 00:22:58.318297 ==
998 00:22:58.318352 Dram Type= 6, Freq= 0, CH_0, rank 0
999 00:22:58.318406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1000 00:22:58.318460 ==
1001 00:22:58.318513
1002 00:22:58.318566
1003 00:22:58.318618 TX Vref Scan disable
1004 00:22:58.318672 == TX Byte 0 ==
1005 00:22:58.318725 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1006 00:22:58.318800 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1007 00:22:58.318856 == TX Byte 1 ==
1008 00:22:58.318909 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1009 00:22:58.318963 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1010 00:22:58.319016
1011 00:22:58.319069 [DATLAT]
1012 00:22:58.319123 Freq=800, CH0 RK0
1013 00:22:58.319176
1014 00:22:58.319229 DATLAT Default: 0xa
1015 00:22:58.319291 0, 0xFFFF, sum = 0
1016 00:22:58.319354 1, 0xFFFF, sum = 0
1017 00:22:58.319409 2, 0xFFFF, sum = 0
1018 00:22:58.319462 3, 0xFFFF, sum = 0
1019 00:22:58.319516 4, 0xFFFF, sum = 0
1020 00:22:58.319570 5, 0xFFFF, sum = 0
1021 00:22:58.319623 6, 0xFFFF, sum = 0
1022 00:22:58.319676 7, 0xFFFF, sum = 0
1023 00:22:58.319729 8, 0xFFFF, sum = 0
1024 00:22:58.319783 9, 0x0, sum = 1
1025 00:22:58.319857 10, 0x0, sum = 2
1026 00:22:58.319919 11, 0x0, sum = 3
1027 00:22:58.319974 12, 0x0, sum = 4
1028 00:22:58.320047 best_step = 10
1029 00:22:58.320134
1030 00:22:58.320224 ==
1031 00:22:58.320282 Dram Type= 6, Freq= 0, CH_0, rank 0
1032 00:22:58.320338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1033 00:22:58.320414 ==
1034 00:22:58.320468 RX Vref Scan: 1
1035 00:22:58.320520
1036 00:22:58.320572 Set Vref Range= 32 -> 127
1037 00:22:58.320625
1038 00:22:58.320676 RX Vref 32 -> 127, step: 1
1039 00:22:58.320728
1040 00:22:58.320780 RX Delay -111 -> 252, step: 8
1041 00:22:58.320832
1042 00:22:58.320897 Set Vref, RX VrefLevel [Byte0]: 32
1043 00:22:58.320955 [Byte1]: 32
1044 00:22:58.321007
1045 00:22:58.321059 Set Vref, RX VrefLevel [Byte0]: 33
1046 00:22:58.321111 [Byte1]: 33
1047 00:22:58.321164
1048 00:22:58.321215 Set Vref, RX VrefLevel [Byte0]: 34
1049 00:22:58.321267 [Byte1]: 34
1050 00:22:58.321320
1051 00:22:58.321371 Set Vref, RX VrefLevel [Byte0]: 35
1052 00:22:58.321442 [Byte1]: 35
1053 00:22:58.321497
1054 00:22:58.321549 Set Vref, RX VrefLevel [Byte0]: 36
1055 00:22:58.321602 [Byte1]: 36
1056 00:22:58.321654
1057 00:22:58.321706 Set Vref, RX VrefLevel [Byte0]: 37
1058 00:22:58.321758 [Byte1]: 37
1059 00:22:58.321809
1060 00:22:58.321861 Set Vref, RX VrefLevel [Byte0]: 38
1061 00:22:58.321912 [Byte1]: 38
1062 00:22:58.321985
1063 00:22:58.322038 Set Vref, RX VrefLevel [Byte0]: 39
1064 00:22:58.322090 [Byte1]: 39
1065 00:22:58.322142
1066 00:22:58.322232 Set Vref, RX VrefLevel [Byte0]: 40
1067 00:22:58.322285 [Byte1]: 40
1068 00:22:58.322337
1069 00:22:58.322389 Set Vref, RX VrefLevel [Byte0]: 41
1070 00:22:58.322440 [Byte1]: 41
1071 00:22:58.322514
1072 00:22:58.322567 Set Vref, RX VrefLevel [Byte0]: 42
1073 00:22:58.322619 [Byte1]: 42
1074 00:22:58.322672
1075 00:22:58.322723 Set Vref, RX VrefLevel [Byte0]: 43
1076 00:22:58.322776 [Byte1]: 43
1077 00:22:58.322828
1078 00:22:58.322879 Set Vref, RX VrefLevel [Byte0]: 44
1079 00:22:58.322931 [Byte1]: 44
1080 00:22:58.322992
1081 00:22:58.323052 Set Vref, RX VrefLevel [Byte0]: 45
1082 00:22:58.323104 [Byte1]: 45
1083 00:22:58.323156
1084 00:22:58.323208 Set Vref, RX VrefLevel [Byte0]: 46
1085 00:22:58.323259 [Byte1]: 46
1086 00:22:58.323311
1087 00:22:58.323364 Set Vref, RX VrefLevel [Byte0]: 47
1088 00:22:58.323415 [Byte1]: 47
1089 00:22:58.323467
1090 00:22:58.323532 Set Vref, RX VrefLevel [Byte0]: 48
1091 00:22:58.323588 [Byte1]: 48
1092 00:22:58.323640
1093 00:22:58.323692 Set Vref, RX VrefLevel [Byte0]: 49
1094 00:22:58.323744 [Byte1]: 49
1095 00:22:58.323795
1096 00:22:58.323847 Set Vref, RX VrefLevel [Byte0]: 50
1097 00:22:58.323898 [Byte1]: 50
1098 00:22:58.323950
1099 00:22:58.324001 Set Vref, RX VrefLevel [Byte0]: 51
1100 00:22:58.324091 [Byte1]: 51
1101 00:22:58.324192
1102 00:22:58.324244 Set Vref, RX VrefLevel [Byte0]: 52
1103 00:22:58.324296 [Byte1]: 52
1104 00:22:58.324348
1105 00:22:58.324399 Set Vref, RX VrefLevel [Byte0]: 53
1106 00:22:58.324451 [Byte1]: 53
1107 00:22:58.324502
1108 00:22:58.324553 Set Vref, RX VrefLevel [Byte0]: 54
1109 00:22:58.324610 [Byte1]: 54
1110 00:22:58.324663
1111 00:22:58.324714 Set Vref, RX VrefLevel [Byte0]: 55
1112 00:22:58.324766 [Byte1]: 55
1113 00:22:58.324818
1114 00:22:58.324869 Set Vref, RX VrefLevel [Byte0]: 56
1115 00:22:58.324921 [Byte1]: 56
1116 00:22:58.324972
1117 00:22:58.325024 Set Vref, RX VrefLevel [Byte0]: 57
1118 00:22:58.325076 [Byte1]: 57
1119 00:22:58.325127
1120 00:22:58.325182 Set Vref, RX VrefLevel [Byte0]: 58
1121 00:22:58.325236 [Byte1]: 58
1122 00:22:58.325288
1123 00:22:58.325339 Set Vref, RX VrefLevel [Byte0]: 59
1124 00:22:58.325391 [Byte1]: 59
1125 00:22:58.325443
1126 00:22:58.325494 Set Vref, RX VrefLevel [Byte0]: 60
1127 00:22:58.325545 [Byte1]: 60
1128 00:22:58.325596
1129 00:22:58.325647 Set Vref, RX VrefLevel [Byte0]: 61
1130 00:22:58.325699 [Byte1]: 61
1131 00:22:58.325753
1132 00:22:58.325806 Set Vref, RX VrefLevel [Byte0]: 62
1133 00:22:58.325858 [Byte1]: 62
1134 00:22:58.325910
1135 00:22:58.325961 Set Vref, RX VrefLevel [Byte0]: 63
1136 00:22:58.326013 [Byte1]: 63
1137 00:22:58.326106
1138 00:22:58.326235 Set Vref, RX VrefLevel [Byte0]: 64
1139 00:22:58.326292 [Byte1]: 64
1140 00:22:58.326353
1141 00:22:58.326406 Set Vref, RX VrefLevel [Byte0]: 65
1142 00:22:58.326459 [Byte1]: 65
1143 00:22:58.326512
1144 00:22:58.326564 Set Vref, RX VrefLevel [Byte0]: 66
1145 00:22:58.326616 [Byte1]: 66
1146 00:22:58.326669
1147 00:22:58.326721 Set Vref, RX VrefLevel [Byte0]: 67
1148 00:22:58.326773 [Byte1]: 67
1149 00:22:58.326825
1150 00:22:58.326876 Set Vref, RX VrefLevel [Byte0]: 68
1151 00:22:58.326935 [Byte1]: 68
1152 00:22:58.326988
1153 00:22:58.327040 Set Vref, RX VrefLevel [Byte0]: 69
1154 00:22:58.327283 [Byte1]: 69
1155 00:22:58.327341
1156 00:22:58.327394 Set Vref, RX VrefLevel [Byte0]: 70
1157 00:22:58.327447 [Byte1]: 70
1158 00:22:58.327506
1159 00:22:58.327559 Set Vref, RX VrefLevel [Byte0]: 71
1160 00:22:58.327612 [Byte1]: 71
1161 00:22:58.327664
1162 00:22:58.327716 Set Vref, RX VrefLevel [Byte0]: 72
1163 00:22:58.327768 [Byte1]: 72
1164 00:22:58.327820
1165 00:22:58.327871 Set Vref, RX VrefLevel [Byte0]: 73
1166 00:22:58.327923 [Byte1]: 73
1167 00:22:58.327975
1168 00:22:58.328026 Set Vref, RX VrefLevel [Byte0]: 74
1169 00:22:58.328084 [Byte1]: 74
1170 00:22:58.328137
1171 00:22:58.328188 Set Vref, RX VrefLevel [Byte0]: 75
1172 00:22:58.328240 [Byte1]: 75
1173 00:22:58.328292
1174 00:22:58.328344 Set Vref, RX VrefLevel [Byte0]: 76
1175 00:22:58.328396 [Byte1]: 76
1176 00:22:58.328448
1177 00:22:58.328499 Set Vref, RX VrefLevel [Byte0]: 77
1178 00:22:58.328551 [Byte1]: 77
1179 00:22:58.328603
1180 00:22:58.328658 Set Vref, RX VrefLevel [Byte0]: 78
1181 00:22:58.328711 [Byte1]: 78
1182 00:22:58.328763
1183 00:22:58.328815 Set Vref, RX VrefLevel [Byte0]: 79
1184 00:22:58.328867 [Byte1]: 79
1185 00:22:58.328919
1186 00:22:58.328971 Set Vref, RX VrefLevel [Byte0]: 80
1187 00:22:58.329023 [Byte1]: 80
1188 00:22:58.329074
1189 00:22:58.329126 Set Vref, RX VrefLevel [Byte0]: 81
1190 00:22:58.329178 [Byte1]: 81
1191 00:22:58.329234
1192 00:22:58.329287 Final RX Vref Byte 0 = 66 to rank0
1193 00:22:58.329339 Final RX Vref Byte 1 = 52 to rank0
1194 00:22:58.329391 Final RX Vref Byte 0 = 66 to rank1
1195 00:22:58.329443 Final RX Vref Byte 1 = 52 to rank1==
1196 00:22:58.329496 Dram Type= 6, Freq= 0, CH_0, rank 0
1197 00:22:58.329548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1198 00:22:58.329601 ==
1199 00:22:58.329652 DQS Delay:
1200 00:22:58.329704 DQS0 = 0, DQS1 = 0
1201 00:22:58.329756 DQM Delay:
1202 00:22:58.329808 DQM0 = 87, DQM1 = 76
1203 00:22:58.329865 DQ Delay:
1204 00:22:58.329918 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =84
1205 00:22:58.329970 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1206 00:22:58.330022 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1207 00:22:58.330111 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1208 00:22:58.330218
1209 00:22:58.330274
1210 00:22:58.330327 [DQSOSCAuto] RK0, (LSB)MR18= 0x4526, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 392 ps
1211 00:22:58.330380 CH0 RK0: MR19=606, MR18=4526
1212 00:22:58.330441 CH0_RK0: MR19=0x606, MR18=0x4526, DQSOSC=392, MR23=63, INC=96, DEC=64
1213 00:22:58.330495
1214 00:22:58.330547 ----->DramcWriteLeveling(PI) begin...
1215 00:22:58.330601 ==
1216 00:22:58.330653 Dram Type= 6, Freq= 0, CH_0, rank 1
1217 00:22:58.330705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1218 00:22:58.330758 ==
1219 00:22:58.330810 Write leveling (Byte 0): 31 => 31
1220 00:22:58.330863 Write leveling (Byte 1): 31 => 31
1221 00:22:58.330915 DramcWriteLeveling(PI) end<-----
1222 00:22:58.330967
1223 00:22:58.331024 ==
1224 00:22:58.331076 Dram Type= 6, Freq= 0, CH_0, rank 1
1225 00:22:58.331128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1226 00:22:58.331181 ==
1227 00:22:58.331233 [Gating] SW mode calibration
1228 00:22:58.331284 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1229 00:22:58.331337 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1230 00:22:58.331389 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1231 00:22:58.331442 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1232 00:22:58.331494 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1233 00:22:58.331547 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 00:22:58.331604 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 00:22:58.331655 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 00:22:58.331707 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 00:22:58.331759 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 00:22:58.331810 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 00:22:58.331862 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 00:22:58.331914 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 00:22:58.331966 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 00:22:58.332018 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 00:22:58.332069 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 00:22:58.332124 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 00:22:58.332178 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 00:22:58.332230 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1247 00:22:58.332281 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1248 00:22:58.332333 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1249 00:22:58.332384 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 00:22:58.332436 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 00:22:58.332487 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 00:22:58.332540 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 00:22:58.332592 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 00:22:58.332644 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1255 00:22:58.332701 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 00:22:58.332754 0 9 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
1257 00:22:58.332806 0 9 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1258 00:22:58.332858 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1259 00:22:58.332909 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1260 00:22:58.332962 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1261 00:22:58.333013 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1262 00:22:58.333065 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1263 00:22:58.333117 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1264 00:22:58.333169 0 10 8 | B1->B0 | 3131 2727 | 1 0 | (1 0) (1 0)
1265 00:22:58.333227 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1266 00:22:58.333280 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1267 00:22:58.333333 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1268 00:22:58.333574 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1269 00:22:58.333634 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1270 00:22:58.333687 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1271 00:22:58.333745 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1272 00:22:58.333798 0 11 8 | B1->B0 | 2c2c 3d3d | 0 0 | (0 0) (0 0)
1273 00:22:58.333851 0 11 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
1274 00:22:58.333904 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1275 00:22:58.333956 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1276 00:22:58.334008 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1277 00:22:58.334078 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1278 00:22:58.334132 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1279 00:22:58.334208 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1280 00:22:58.334265 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1281 00:22:58.334318 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 00:22:58.334370 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 00:22:58.334422 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 00:22:58.334474 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1285 00:22:58.334526 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1286 00:22:58.334579 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1287 00:22:58.334631 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1288 00:22:58.334682 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1289 00:22:58.334734 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1290 00:22:58.334790 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1291 00:22:58.334843 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1292 00:22:58.334895 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1293 00:22:58.334947 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1294 00:22:58.334999 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1295 00:22:58.335051 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1296 00:22:58.335102 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1297 00:22:58.335154 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1298 00:22:58.335206 Total UI for P1: 0, mck2ui 16
1299 00:22:58.335259 best dqsien dly found for B0: ( 0, 14, 8)
1300 00:22:58.335316 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1301 00:22:58.335391 Total UI for P1: 0, mck2ui 16
1302 00:22:58.335450 best dqsien dly found for B1: ( 0, 14, 12)
1303 00:22:58.335503 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1304 00:22:58.335556 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
1305 00:22:58.335608
1306 00:22:58.335659 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1307 00:22:58.335712 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
1308 00:22:58.335763 [Gating] SW calibration Done
1309 00:22:58.335816 ==
1310 00:22:58.335873 Dram Type= 6, Freq= 0, CH_0, rank 1
1311 00:22:58.335926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1312 00:22:58.335979 ==
1313 00:22:58.336031 RX Vref Scan: 0
1314 00:22:58.336083
1315 00:22:58.336135 RX Vref 0 -> 0, step: 1
1316 00:22:58.336187
1317 00:22:58.336238 RX Delay -130 -> 252, step: 16
1318 00:22:58.336290 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1319 00:22:58.336342 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1320 00:22:58.336399 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1321 00:22:58.336451 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1322 00:22:58.336504 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1323 00:22:58.336556 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1324 00:22:58.336607 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1325 00:22:58.336658 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1326 00:22:58.336710 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1327 00:22:58.336761 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1328 00:22:58.336813 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1329 00:22:58.336865 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1330 00:22:58.336923 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1331 00:22:58.336975 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1332 00:22:58.337027 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1333 00:22:58.337080 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1334 00:22:58.337132 ==
1335 00:22:58.337185 Dram Type= 6, Freq= 0, CH_0, rank 1
1336 00:22:58.337237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1337 00:22:58.337290 ==
1338 00:22:58.337342 DQS Delay:
1339 00:22:58.337394 DQS0 = 0, DQS1 = 0
1340 00:22:58.337451 DQM Delay:
1341 00:22:58.337503 DQM0 = 85, DQM1 = 77
1342 00:22:58.337555 DQ Delay:
1343 00:22:58.337607 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1344 00:22:58.337659 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1345 00:22:58.337711 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1346 00:22:58.337763 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1347 00:22:58.337815
1348 00:22:58.337867
1349 00:22:58.337918 ==
1350 00:22:58.337976 Dram Type= 6, Freq= 0, CH_0, rank 1
1351 00:22:58.338029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1352 00:22:58.338082 ==
1353 00:22:58.338134
1354 00:22:58.338228
1355 00:22:58.338281 TX Vref Scan disable
1356 00:22:58.338333 == TX Byte 0 ==
1357 00:22:58.338389 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1358 00:22:58.338445 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1359 00:22:58.338520 == TX Byte 1 ==
1360 00:22:58.338575 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1361 00:22:58.338627 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1362 00:22:58.338679 ==
1363 00:22:58.338731 Dram Type= 6, Freq= 0, CH_0, rank 1
1364 00:22:58.338783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1365 00:22:58.338836 ==
1366 00:22:58.338887 TX Vref=22, minBit 3, minWin=27, winSum=445
1367 00:22:58.338940 TX Vref=24, minBit 8, minWin=27, winSum=447
1368 00:22:58.339030 TX Vref=26, minBit 9, minWin=27, winSum=448
1369 00:22:58.339087 TX Vref=28, minBit 9, minWin=27, winSum=449
1370 00:22:58.339139 TX Vref=30, minBit 9, minWin=27, winSum=448
1371 00:22:58.339192 TX Vref=32, minBit 9, minWin=27, winSum=448
1372 00:22:58.339244 [TxChooseVref] Worse bit 9, Min win 27, Win sum 449, Final Vref 28
1373 00:22:58.339296
1374 00:22:58.339348 Final TX Range 1 Vref 28
1375 00:22:58.339400
1376 00:22:58.339451 ==
1377 00:22:58.339502 Dram Type= 6, Freq= 0, CH_0, rank 1
1378 00:22:58.339574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1379 00:22:58.339629 ==
1380 00:22:58.339681
1381 00:22:58.339732
1382 00:22:58.339783 TX Vref Scan disable
1383 00:22:58.339835 == TX Byte 0 ==
1384 00:22:58.340113 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1385 00:22:58.340263 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1386 00:22:58.340370 == TX Byte 1 ==
1387 00:22:58.340475 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1388 00:22:58.340580 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1389 00:22:58.340674
1390 00:22:58.340756 [DATLAT]
1391 00:22:58.340838 Freq=800, CH0 RK1
1392 00:22:58.340919
1393 00:22:58.341014 DATLAT Default: 0xa
1394 00:22:58.341098 0, 0xFFFF, sum = 0
1395 00:22:58.341183 1, 0xFFFF, sum = 0
1396 00:22:58.341240 2, 0xFFFF, sum = 0
1397 00:22:58.341294 3, 0xFFFF, sum = 0
1398 00:22:58.341347 4, 0xFFFF, sum = 0
1399 00:22:58.341399 5, 0xFFFF, sum = 0
1400 00:22:58.341451 6, 0xFFFF, sum = 0
1401 00:22:58.341503 7, 0xFFFF, sum = 0
1402 00:22:58.341556 8, 0xFFFF, sum = 0
1403 00:22:58.341609 9, 0x0, sum = 1
1404 00:22:58.341662 10, 0x0, sum = 2
1405 00:22:58.341714 11, 0x0, sum = 3
1406 00:22:58.341771 12, 0x0, sum = 4
1407 00:22:58.341824 best_step = 10
1408 00:22:58.341875
1409 00:22:58.341927 ==
1410 00:22:58.341978 Dram Type= 6, Freq= 0, CH_0, rank 1
1411 00:22:58.342030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1412 00:22:58.342083 ==
1413 00:22:58.342135 RX Vref Scan: 0
1414 00:22:58.342229
1415 00:22:58.342303 RX Vref 0 -> 0, step: 1
1416 00:22:58.342365
1417 00:22:58.342419 RX Delay -111 -> 252, step: 8
1418 00:22:58.342472 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1419 00:22:58.342524 iDelay=217, Bit 1, Center 92 (-23 ~ 208) 232
1420 00:22:58.342576 iDelay=217, Bit 2, Center 80 (-31 ~ 192) 224
1421 00:22:58.342627 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
1422 00:22:58.342679 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
1423 00:22:58.342731 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1424 00:22:58.342782 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1425 00:22:58.342833 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1426 00:22:58.342885 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
1427 00:22:58.342942 iDelay=217, Bit 9, Center 64 (-47 ~ 176) 224
1428 00:22:58.342995 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1429 00:22:58.343046 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
1430 00:22:58.343098 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1431 00:22:58.343149 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1432 00:22:58.343201 iDelay=217, Bit 14, Center 88 (-23 ~ 200) 224
1433 00:22:58.343252 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1434 00:22:58.343303 ==
1435 00:22:58.343355 Dram Type= 6, Freq= 0, CH_0, rank 1
1436 00:22:58.343407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1437 00:22:58.343459 ==
1438 00:22:58.343516 DQS Delay:
1439 00:22:58.343569 DQS0 = 0, DQS1 = 0
1440 00:22:58.343621 DQM Delay:
1441 00:22:58.343673 DQM0 = 86, DQM1 = 77
1442 00:22:58.343725 DQ Delay:
1443 00:22:58.343776 DQ0 =84, DQ1 =92, DQ2 =80, DQ3 =84
1444 00:22:58.343829 DQ4 =84, DQ5 =76, DQ6 =92, DQ7 =96
1445 00:22:58.343882 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1446 00:22:58.343933 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =84
1447 00:22:58.343984
1448 00:22:58.344035
1449 00:22:58.344092 [DQSOSCAuto] RK1, (LSB)MR18= 0x450c, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
1450 00:22:58.344146 CH0 RK1: MR19=606, MR18=450C
1451 00:22:58.344198 CH0_RK1: MR19=0x606, MR18=0x450C, DQSOSC=392, MR23=63, INC=96, DEC=64
1452 00:22:58.344250 [RxdqsGatingPostProcess] freq 800
1453 00:22:58.344302 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1454 00:22:58.344353 Pre-setting of DQS Precalculation
1455 00:22:58.344404 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1456 00:22:58.344456 ==
1457 00:22:58.344508 Dram Type= 6, Freq= 0, CH_1, rank 0
1458 00:22:58.344559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1459 00:22:58.344611 ==
1460 00:22:58.344668 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1461 00:22:58.344722 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1462 00:22:58.344774 [CA 0] Center 36 (6~67) winsize 62
1463 00:22:58.344826 [CA 1] Center 36 (6~67) winsize 62
1464 00:22:58.344877 [CA 2] Center 34 (4~65) winsize 62
1465 00:22:58.344929 [CA 3] Center 34 (3~65) winsize 63
1466 00:22:58.344980 [CA 4] Center 34 (4~65) winsize 62
1467 00:22:58.345032 [CA 5] Center 34 (3~65) winsize 63
1468 00:22:58.345083
1469 00:22:58.345134 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1470 00:22:58.345185
1471 00:22:58.345241 [CATrainingPosCal] consider 1 rank data
1472 00:22:58.345308 u2DelayCellTimex100 = 270/100 ps
1473 00:22:58.345365 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1474 00:22:58.345418 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1475 00:22:58.345469 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1476 00:22:58.345521 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1477 00:22:58.345571 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1478 00:22:58.345622 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1479 00:22:58.345673
1480 00:22:58.345725 CA PerBit enable=1, Macro0, CA PI delay=34
1481 00:22:58.345776
1482 00:22:58.345836 [CBTSetCACLKResult] CA Dly = 34
1483 00:22:58.345889 CS Dly: 5 (0~36)
1484 00:22:58.345941 ==
1485 00:22:58.345993 Dram Type= 6, Freq= 0, CH_1, rank 1
1486 00:22:58.346045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1487 00:22:58.346097 ==
1488 00:22:58.346149 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1489 00:22:58.346213 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1490 00:22:58.346265 [CA 0] Center 37 (7~67) winsize 61
1491 00:22:58.346317 [CA 1] Center 37 (6~68) winsize 63
1492 00:22:58.346369 [CA 2] Center 34 (4~65) winsize 62
1493 00:22:58.346425 [CA 3] Center 34 (3~65) winsize 63
1494 00:22:58.346477 [CA 4] Center 34 (4~65) winsize 62
1495 00:22:58.346528 [CA 5] Center 33 (3~64) winsize 62
1496 00:22:58.346579
1497 00:22:58.346630 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1498 00:22:58.346682
1499 00:22:58.346732 [CATrainingPosCal] consider 2 rank data
1500 00:22:58.346784 u2DelayCellTimex100 = 270/100 ps
1501 00:22:58.346835 CA0 delay=37 (7~67),Diff = 4 PI (28 cell)
1502 00:22:58.346887 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1503 00:22:58.346939 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1504 00:22:58.346996 CA3 delay=34 (3~65),Diff = 1 PI (7 cell)
1505 00:22:58.347047 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1506 00:22:58.347099 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1507 00:22:58.347150
1508 00:22:58.347201 CA PerBit enable=1, Macro0, CA PI delay=33
1509 00:22:58.347252
1510 00:22:58.347303 [CBTSetCACLKResult] CA Dly = 33
1511 00:22:58.347354 CS Dly: 6 (0~38)
1512 00:22:58.347406
1513 00:22:58.347456 ----->DramcWriteLeveling(PI) begin...
1514 00:22:58.347509 ==
1515 00:22:58.347566 Dram Type= 6, Freq= 0, CH_1, rank 0
1516 00:22:58.347807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1517 00:22:58.347867 ==
1518 00:22:58.347920 Write leveling (Byte 0): 24 => 24
1519 00:22:58.347971 Write leveling (Byte 1): 30 => 30
1520 00:22:58.348023 DramcWriteLeveling(PI) end<-----
1521 00:22:58.348074
1522 00:22:58.348132 ==
1523 00:22:58.348185 Dram Type= 6, Freq= 0, CH_1, rank 0
1524 00:22:58.348237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1525 00:22:58.348290 ==
1526 00:22:58.348341 [Gating] SW mode calibration
1527 00:22:58.348393 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1528 00:22:58.348445 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1529 00:22:58.348497 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1530 00:22:58.348549 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1531 00:22:58.348601 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1532 00:22:58.348653 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 00:22:58.348712 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 00:22:58.348765 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 00:22:58.348832 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 00:22:58.348888 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 00:22:58.348940 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 00:22:58.348993 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 00:22:58.349044 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 00:22:58.349095 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 00:22:58.349147 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 00:22:58.349198 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 00:22:58.349254 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 00:22:58.349307 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 00:22:58.349359 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1546 00:22:58.349410 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1547 00:22:58.349461 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1548 00:22:58.349512 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 00:22:58.349563 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 00:22:58.349614 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 00:22:58.349665 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 00:22:58.349716 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 00:22:58.349767 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 00:22:58.349819 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
1555 00:22:58.349903 0 9 8 | B1->B0 | 2f2f 2f2f | 1 0 | (1 1) (0 0)
1556 00:22:58.349994 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1557 00:22:58.350083 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1558 00:22:58.350170 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1559 00:22:58.350227 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1560 00:22:58.350280 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1561 00:22:58.350331 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1562 00:22:58.350383 0 10 4 | B1->B0 | 3131 3333 | 1 0 | (1 0) (0 1)
1563 00:22:58.350442 0 10 8 | B1->B0 | 2525 2a2a | 0 0 | (0 0) (0 0)
1564 00:22:58.350494 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1565 00:22:58.350546 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1566 00:22:58.350598 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1567 00:22:58.350649 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1568 00:22:58.350700 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1569 00:22:58.350751 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1570 00:22:58.350803 0 11 4 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
1571 00:22:58.350854 0 11 8 | B1->B0 | 3939 403f | 0 1 | (1 1) (0 0)
1572 00:22:58.350906 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1573 00:22:58.350957 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1574 00:22:58.351016 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1575 00:22:58.351068 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1576 00:22:58.351119 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1577 00:22:58.351170 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1578 00:22:58.351222 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1579 00:22:58.351273 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1580 00:22:58.351324 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 00:22:58.351375 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 00:22:58.351426 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1583 00:22:58.351477 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1584 00:22:58.351529 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1585 00:22:58.351586 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1586 00:22:58.351639 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1587 00:22:58.351691 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1588 00:22:58.351743 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1589 00:22:58.351794 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1590 00:22:58.351847 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1591 00:22:58.351918 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1592 00:22:58.351974 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1593 00:22:58.352026 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1594 00:22:58.352078 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1595 00:22:58.352133 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1596 00:22:58.352188 Total UI for P1: 0, mck2ui 16
1597 00:22:58.352240 best dqsien dly found for B0: ( 0, 14, 4)
1598 00:22:58.352292 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1599 00:22:58.352344 Total UI for P1: 0, mck2ui 16
1600 00:22:58.352396 best dqsien dly found for B1: ( 0, 14, 6)
1601 00:22:58.352448 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1602 00:22:58.352499 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1603 00:22:58.352550
1604 00:22:58.352792 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1605 00:22:58.352850 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1606 00:22:58.352902 [Gating] SW calibration Done
1607 00:22:58.352954 ==
1608 00:22:58.353006 Dram Type= 6, Freq= 0, CH_1, rank 0
1609 00:22:58.353058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1610 00:22:58.353110 ==
1611 00:22:58.353161 RX Vref Scan: 0
1612 00:22:58.353212
1613 00:22:58.353263 RX Vref 0 -> 0, step: 1
1614 00:22:58.353321
1615 00:22:58.353373 RX Delay -130 -> 252, step: 16
1616 00:22:58.353425 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1617 00:22:58.353476 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1618 00:22:58.353528 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1619 00:22:58.353584 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1620 00:22:58.353638 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1621 00:22:58.353689 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1622 00:22:58.353741 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1623 00:22:58.353793 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1624 00:22:58.353845 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1625 00:22:58.353902 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1626 00:22:58.353955 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1627 00:22:58.354007 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1628 00:22:58.354059 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1629 00:22:58.354111 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1630 00:22:58.354168 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1631 00:22:58.354260 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1632 00:22:58.354311 ==
1633 00:22:58.354363 Dram Type= 6, Freq= 0, CH_1, rank 0
1634 00:22:58.354416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1635 00:22:58.354499 ==
1636 00:22:58.354579 DQS Delay:
1637 00:22:58.354660 DQS0 = 0, DQS1 = 0
1638 00:22:58.354740 DQM Delay:
1639 00:22:58.354821 DQM0 = 89, DQM1 = 78
1640 00:22:58.354901 DQ Delay:
1641 00:22:58.354981 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1642 00:22:58.355066 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1643 00:22:58.355147 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1644 00:22:58.355228 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1645 00:22:58.355307
1646 00:22:58.355387
1647 00:22:58.355466 ==
1648 00:22:58.355559 Dram Type= 6, Freq= 0, CH_1, rank 0
1649 00:22:58.355645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1650 00:22:58.355726 ==
1651 00:22:58.355806
1652 00:22:58.355886
1653 00:22:58.355966 TX Vref Scan disable
1654 00:22:58.356046 == TX Byte 0 ==
1655 00:22:58.356127 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1656 00:22:58.356198 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1657 00:22:58.356252 == TX Byte 1 ==
1658 00:22:58.356304 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1659 00:22:58.356356 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1660 00:22:58.356408 ==
1661 00:22:58.356459 Dram Type= 6, Freq= 0, CH_1, rank 0
1662 00:22:58.356511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1663 00:22:58.356563 ==
1664 00:22:58.356618 TX Vref=22, minBit 11, minWin=26, winSum=434
1665 00:22:58.356703 TX Vref=24, minBit 3, minWin=26, winSum=438
1666 00:22:58.356789 TX Vref=26, minBit 0, minWin=27, winSum=442
1667 00:22:58.356871 TX Vref=28, minBit 0, minWin=27, winSum=447
1668 00:22:58.356931 TX Vref=30, minBit 0, minWin=27, winSum=441
1669 00:22:58.356984 TX Vref=32, minBit 0, minWin=27, winSum=442
1670 00:22:58.357035 [TxChooseVref] Worse bit 0, Min win 27, Win sum 447, Final Vref 28
1671 00:22:58.357087
1672 00:22:58.357138 Final TX Range 1 Vref 28
1673 00:22:58.357190
1674 00:22:58.357241 ==
1675 00:22:58.357299 Dram Type= 6, Freq= 0, CH_1, rank 0
1676 00:22:58.357350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1677 00:22:58.357403 ==
1678 00:22:58.357454
1679 00:22:58.357504
1680 00:22:58.357556 TX Vref Scan disable
1681 00:22:58.357607 == TX Byte 0 ==
1682 00:22:58.357658 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1683 00:22:58.357710 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1684 00:22:58.357762 == TX Byte 1 ==
1685 00:22:58.357813 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1686 00:22:58.357869 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1687 00:22:58.357922
1688 00:22:58.357972 [DATLAT]
1689 00:22:58.358023 Freq=800, CH1 RK0
1690 00:22:58.358074
1691 00:22:58.358125 DATLAT Default: 0xa
1692 00:22:58.358184 0, 0xFFFF, sum = 0
1693 00:22:58.358238 1, 0xFFFF, sum = 0
1694 00:22:58.358290 2, 0xFFFF, sum = 0
1695 00:22:58.358343 3, 0xFFFF, sum = 0
1696 00:22:58.358395 4, 0xFFFF, sum = 0
1697 00:22:58.358454 5, 0xFFFF, sum = 0
1698 00:22:58.358507 6, 0xFFFF, sum = 0
1699 00:22:58.358560 7, 0xFFFF, sum = 0
1700 00:22:58.358612 8, 0xFFFF, sum = 0
1701 00:22:58.358664 9, 0x0, sum = 1
1702 00:22:58.358716 10, 0x0, sum = 2
1703 00:22:58.358769 11, 0x0, sum = 3
1704 00:22:58.358826 12, 0x0, sum = 4
1705 00:22:58.358893 best_step = 10
1706 00:22:58.358951
1707 00:22:58.359007 ==
1708 00:22:58.359060 Dram Type= 6, Freq= 0, CH_1, rank 0
1709 00:22:58.359113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1710 00:22:58.359192 ==
1711 00:22:58.359246 RX Vref Scan: 1
1712 00:22:58.359299
1713 00:22:58.359351 Set Vref Range= 32 -> 127
1714 00:22:58.359403
1715 00:22:58.359454 RX Vref 32 -> 127, step: 1
1716 00:22:58.359506
1717 00:22:58.359556 RX Delay -95 -> 252, step: 8
1718 00:22:58.359613
1719 00:22:58.359665 Set Vref, RX VrefLevel [Byte0]: 32
1720 00:22:58.359717 [Byte1]: 32
1721 00:22:58.359768
1722 00:22:58.359820 Set Vref, RX VrefLevel [Byte0]: 33
1723 00:22:58.359871 [Byte1]: 33
1724 00:22:58.359923
1725 00:22:58.359974 Set Vref, RX VrefLevel [Byte0]: 34
1726 00:22:58.360025 [Byte1]: 34
1727 00:22:58.360077
1728 00:22:58.360128 Set Vref, RX VrefLevel [Byte0]: 35
1729 00:22:58.360183 [Byte1]: 35
1730 00:22:58.360236
1731 00:22:58.360287 Set Vref, RX VrefLevel [Byte0]: 36
1732 00:22:58.360339 [Byte1]: 36
1733 00:22:58.360391
1734 00:22:58.360442 Set Vref, RX VrefLevel [Byte0]: 37
1735 00:22:58.360494 [Byte1]: 37
1736 00:22:58.360545
1737 00:22:58.360596 Set Vref, RX VrefLevel [Byte0]: 38
1738 00:22:58.360648 [Byte1]: 38
1739 00:22:58.360699
1740 00:22:58.360750 Set Vref, RX VrefLevel [Byte0]: 39
1741 00:22:58.360807 [Byte1]: 39
1742 00:22:58.360858
1743 00:22:58.360909 Set Vref, RX VrefLevel [Byte0]: 40
1744 00:22:58.360967 [Byte1]: 40
1745 00:22:58.361020
1746 00:22:58.361071 Set Vref, RX VrefLevel [Byte0]: 41
1747 00:22:58.361123 [Byte1]: 41
1748 00:22:58.361183
1749 00:22:58.361237 Set Vref, RX VrefLevel [Byte0]: 42
1750 00:22:58.361289 [Byte1]: 42
1751 00:22:58.361344
1752 00:22:58.361397 Set Vref, RX VrefLevel [Byte0]: 43
1753 00:22:58.361449 [Byte1]: 43
1754 00:22:58.361501
1755 00:22:58.361553 Set Vref, RX VrefLevel [Byte0]: 44
1756 00:22:58.361624 [Byte1]: 44
1757 00:22:58.361680
1758 00:22:58.361732 Set Vref, RX VrefLevel [Byte0]: 45
1759 00:22:58.361981 [Byte1]: 45
1760 00:22:58.362043
1761 00:22:58.362096 Set Vref, RX VrefLevel [Byte0]: 46
1762 00:22:58.362148 [Byte1]: 46
1763 00:22:58.362244
1764 00:22:58.362297 Set Vref, RX VrefLevel [Byte0]: 47
1765 00:22:58.362349 [Byte1]: 47
1766 00:22:58.362438
1767 00:22:58.362493 Set Vref, RX VrefLevel [Byte0]: 48
1768 00:22:58.362546 [Byte1]: 48
1769 00:22:58.362597
1770 00:22:58.362649 Set Vref, RX VrefLevel [Byte0]: 49
1771 00:22:58.362701 [Byte1]: 49
1772 00:22:58.362752
1773 00:22:58.362803 Set Vref, RX VrefLevel [Byte0]: 50
1774 00:22:58.362855 [Byte1]: 50
1775 00:22:58.362906
1776 00:22:58.362957 Set Vref, RX VrefLevel [Byte0]: 51
1777 00:22:58.363008 [Byte1]: 51
1778 00:22:58.363059
1779 00:22:58.363110 Set Vref, RX VrefLevel [Byte0]: 52
1780 00:22:58.363162 [Byte1]: 52
1781 00:22:58.363213
1782 00:22:58.363267 Set Vref, RX VrefLevel [Byte0]: 53
1783 00:22:58.363321 [Byte1]: 53
1784 00:22:58.363373
1785 00:22:58.363424 Set Vref, RX VrefLevel [Byte0]: 54
1786 00:22:58.363475 [Byte1]: 54
1787 00:22:58.363526
1788 00:22:58.363577 Set Vref, RX VrefLevel [Byte0]: 55
1789 00:22:58.363628 [Byte1]: 55
1790 00:22:58.363679
1791 00:22:58.363730 Set Vref, RX VrefLevel [Byte0]: 56
1792 00:22:58.363780 [Byte1]: 56
1793 00:22:58.363832
1794 00:22:58.363889 Set Vref, RX VrefLevel [Byte0]: 57
1795 00:22:58.363941 [Byte1]: 57
1796 00:22:58.363993
1797 00:22:58.364044 Set Vref, RX VrefLevel [Byte0]: 58
1798 00:22:58.364097 [Byte1]: 58
1799 00:22:58.364148
1800 00:22:58.364199 Set Vref, RX VrefLevel [Byte0]: 59
1801 00:22:58.364250 [Byte1]: 59
1802 00:22:58.364302
1803 00:22:58.364352 Set Vref, RX VrefLevel [Byte0]: 60
1804 00:22:58.364403 [Byte1]: 60
1805 00:22:58.364461
1806 00:22:58.364513 Set Vref, RX VrefLevel [Byte0]: 61
1807 00:22:58.364564 [Byte1]: 61
1808 00:22:58.364615
1809 00:22:58.364666 Set Vref, RX VrefLevel [Byte0]: 62
1810 00:22:58.364717 [Byte1]: 62
1811 00:22:58.364768
1812 00:22:58.364819 Set Vref, RX VrefLevel [Byte0]: 63
1813 00:22:58.364870 [Byte1]: 63
1814 00:22:58.364921
1815 00:22:58.364972 Set Vref, RX VrefLevel [Byte0]: 64
1816 00:22:58.365027 [Byte1]: 64
1817 00:22:58.365080
1818 00:22:58.365130 Set Vref, RX VrefLevel [Byte0]: 65
1819 00:22:58.365182 [Byte1]: 65
1820 00:22:58.365233
1821 00:22:58.365288 Set Vref, RX VrefLevel [Byte0]: 66
1822 00:22:58.365356 [Byte1]: 66
1823 00:22:58.365409
1824 00:22:58.365460 Set Vref, RX VrefLevel [Byte0]: 67
1825 00:22:58.365512 [Byte1]: 67
1826 00:22:58.365563
1827 00:22:58.365619 Set Vref, RX VrefLevel [Byte0]: 68
1828 00:22:58.365672 [Byte1]: 68
1829 00:22:58.365724
1830 00:22:58.365774 Set Vref, RX VrefLevel [Byte0]: 69
1831 00:22:58.365825 [Byte1]: 69
1832 00:22:58.365876
1833 00:22:58.365927 Set Vref, RX VrefLevel [Byte0]: 70
1834 00:22:58.365979 [Byte1]: 70
1835 00:22:58.366030
1836 00:22:58.366081 Set Vref, RX VrefLevel [Byte0]: 71
1837 00:22:58.366132 [Byte1]: 71
1838 00:22:58.366216
1839 00:22:58.366283 Set Vref, RX VrefLevel [Byte0]: 72
1840 00:22:58.366336 [Byte1]: 72
1841 00:22:58.366387
1842 00:22:58.366437 Set Vref, RX VrefLevel [Byte0]: 73
1843 00:22:58.366489 [Byte1]: 73
1844 00:22:58.366540
1845 00:22:58.366591 Set Vref, RX VrefLevel [Byte0]: 74
1846 00:22:58.366642 [Byte1]: 74
1847 00:22:58.366693
1848 00:22:58.366746 Set Vref, RX VrefLevel [Byte0]: 75
1849 00:22:58.366801 [Byte1]: 75
1850 00:22:58.366852
1851 00:22:58.366903 Set Vref, RX VrefLevel [Byte0]: 76
1852 00:22:58.366954 [Byte1]: 76
1853 00:22:58.367005
1854 00:22:58.367056 Final RX Vref Byte 0 = 58 to rank0
1855 00:22:58.367109 Final RX Vref Byte 1 = 64 to rank0
1856 00:22:58.367160 Final RX Vref Byte 0 = 58 to rank1
1857 00:22:58.367212 Final RX Vref Byte 1 = 64 to rank1==
1858 00:22:58.367263 Dram Type= 6, Freq= 0, CH_1, rank 0
1859 00:22:58.367315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1860 00:22:58.367372 ==
1861 00:22:58.367424 DQS Delay:
1862 00:22:58.367475 DQS0 = 0, DQS1 = 0
1863 00:22:58.367526 DQM Delay:
1864 00:22:58.367577 DQM0 = 86, DQM1 = 79
1865 00:22:58.367629 DQ Delay:
1866 00:22:58.367680 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1867 00:22:58.367731 DQ4 =80, DQ5 =100, DQ6 =96, DQ7 =80
1868 00:22:58.367782 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1869 00:22:58.367833 DQ12 =88, DQ13 =84, DQ14 =88, DQ15 =88
1870 00:22:58.367884
1871 00:22:58.367941
1872 00:22:58.367992 [DQSOSCAuto] RK0, (LSB)MR18= 0x311d, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
1873 00:22:58.368045 CH1 RK0: MR19=606, MR18=311D
1874 00:22:58.368097 CH1_RK0: MR19=0x606, MR18=0x311D, DQSOSC=397, MR23=63, INC=93, DEC=62
1875 00:22:58.368148
1876 00:22:58.368199 ----->DramcWriteLeveling(PI) begin...
1877 00:22:58.368251 ==
1878 00:22:58.368303 Dram Type= 6, Freq= 0, CH_1, rank 1
1879 00:22:58.368354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1880 00:22:58.368406 ==
1881 00:22:58.368484 Write leveling (Byte 0): 29 => 29
1882 00:22:58.368540 Write leveling (Byte 1): 31 => 31
1883 00:22:58.368593 DramcWriteLeveling(PI) end<-----
1884 00:22:58.368645
1885 00:22:58.368696 ==
1886 00:22:58.368747 Dram Type= 6, Freq= 0, CH_1, rank 1
1887 00:22:58.368799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1888 00:22:58.368851 ==
1889 00:22:58.368902 [Gating] SW mode calibration
1890 00:22:58.368982 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1891 00:22:58.369037 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1892 00:22:58.369096 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1893 00:22:58.369150 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1894 00:22:58.369202 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1895 00:22:58.369253 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 00:22:58.369305 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 00:22:58.369357 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 00:22:58.369408 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 00:22:58.369459 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 00:22:58.369511 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 00:22:58.369562 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 00:22:58.369803 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 00:22:58.369863 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 00:22:58.369916 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 00:22:58.369968 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 00:22:58.370020 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 00:22:58.370071 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 00:22:58.370123 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 00:22:58.370181 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1910 00:22:58.370282 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1911 00:22:58.370335 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1912 00:22:58.370386 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1913 00:22:58.370438 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1914 00:22:58.370490 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1915 00:22:58.370542 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1916 00:22:58.370594 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1917 00:22:58.370646 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1918 00:22:58.370698 0 9 8 | B1->B0 | 3232 2b2b | 0 0 | (0 0) (0 0)
1919 00:22:58.370750 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1920 00:22:58.370808 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1921 00:22:58.370860 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1922 00:22:58.370912 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1923 00:22:58.370964 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1924 00:22:58.371016 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1925 00:22:58.371067 0 10 4 | B1->B0 | 3030 3333 | 0 0 | (0 0) (0 0)
1926 00:22:58.371118 0 10 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (1 1)
1927 00:22:58.371170 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1928 00:22:58.371221 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1929 00:22:58.371273 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1930 00:22:58.371324 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1931 00:22:58.371382 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1932 00:22:58.371451 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1933 00:22:58.371507 0 11 4 | B1->B0 | 2727 2626 | 0 0 | (1 1) (1 1)
1934 00:22:58.371559 0 11 8 | B1->B0 | 3f3f 3838 | 0 0 | (0 0) (0 0)
1935 00:22:58.371611 0 11 12 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
1936 00:22:58.371663 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1937 00:22:58.371715 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1938 00:22:58.371767 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1939 00:22:58.371819 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1940 00:22:58.371870 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1941 00:22:58.371928 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1942 00:22:58.371981 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1943 00:22:58.372033 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1944 00:22:58.372085 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1945 00:22:58.372136 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1946 00:22:58.372188 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1947 00:22:58.372239 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1948 00:22:58.372290 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1949 00:22:58.372342 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1950 00:22:58.372394 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1951 00:22:58.372445 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1952 00:22:58.372497 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1953 00:22:58.372548 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1954 00:22:58.372599 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1955 00:22:58.372654 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1956 00:22:58.372708 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1957 00:22:58.372759 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1958 00:22:58.372810 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1959 00:22:58.372862 Total UI for P1: 0, mck2ui 16
1960 00:22:58.372914 best dqsien dly found for B1: ( 0, 14, 4)
1961 00:22:58.372965 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1962 00:22:58.373017 Total UI for P1: 0, mck2ui 16
1963 00:22:58.373069 best dqsien dly found for B0: ( 0, 14, 6)
1964 00:22:58.373120 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1965 00:22:58.373171 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1966 00:22:58.373223
1967 00:22:58.373278 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1968 00:22:58.373332 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1969 00:22:58.373383 [Gating] SW calibration Done
1970 00:22:58.373434 ==
1971 00:22:58.373486 Dram Type= 6, Freq= 0, CH_1, rank 1
1972 00:22:58.373538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1973 00:22:58.373599 ==
1974 00:22:58.373653 RX Vref Scan: 0
1975 00:22:58.373705
1976 00:22:58.373756 RX Vref 0 -> 0, step: 1
1977 00:22:58.373808
1978 00:22:58.373863 RX Delay -130 -> 252, step: 16
1979 00:22:58.373917 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1980 00:22:58.373968 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1981 00:22:58.374020 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1982 00:22:58.374071 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1983 00:22:58.374122 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1984 00:22:58.374180 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1985 00:22:58.374270 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1986 00:22:58.500578 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1987 00:22:58.501089 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1988 00:22:58.501444 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1989 00:22:58.501753 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1990 00:22:58.502138 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1991 00:22:58.502485 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1992 00:22:58.502798 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1993 00:22:58.503455 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1994 00:22:58.503794 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1995 00:22:58.504091 ==
1996 00:22:58.504370 Dram Type= 6, Freq= 0, CH_1, rank 1
1997 00:22:58.504674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1998 00:22:58.504952 ==
1999 00:22:58.505256 DQS Delay:
2000 00:22:58.505531 DQS0 = 0, DQS1 = 0
2001 00:22:58.505828 DQM Delay:
2002 00:22:58.506145 DQM0 = 87, DQM1 = 79
2003 00:22:58.506521 DQ Delay:
2004 00:22:58.506797 DQ0 =93, DQ1 =77, DQ2 =69, DQ3 =85
2005 00:22:58.507098 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
2006 00:22:58.507372 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
2007 00:22:58.507673 DQ12 =93, DQ13 =85, DQ14 =85, DQ15 =85
2008 00:22:58.507947
2009 00:22:58.508234
2010 00:22:58.508507 ==
2011 00:22:58.508780 Dram Type= 6, Freq= 0, CH_1, rank 1
2012 00:22:58.509070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2013 00:22:58.509341 ==
2014 00:22:58.509640
2015 00:22:58.509905
2016 00:22:58.510291 TX Vref Scan disable
2017 00:22:58.510577 == TX Byte 0 ==
2018 00:22:58.510879 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
2019 00:22:58.511156 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2020 00:22:58.511458 == TX Byte 1 ==
2021 00:22:58.511730 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
2022 00:22:58.512032 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2023 00:22:58.512305 ==
2024 00:22:58.512593 Dram Type= 6, Freq= 0, CH_1, rank 1
2025 00:22:58.512865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2026 00:22:58.513133 ==
2027 00:22:58.513425 TX Vref=22, minBit 8, minWin=26, winSum=443
2028 00:22:58.513698 TX Vref=24, minBit 8, minWin=26, winSum=447
2029 00:22:58.514005 TX Vref=26, minBit 8, minWin=27, winSum=450
2030 00:22:58.514318 TX Vref=28, minBit 8, minWin=27, winSum=450
2031 00:22:58.514628 TX Vref=30, minBit 8, minWin=27, winSum=448
2032 00:22:58.514904 TX Vref=32, minBit 0, minWin=28, winSum=453
2033 00:22:58.515205 [TxChooseVref] Worse bit 0, Min win 28, Win sum 453, Final Vref 32
2034 00:22:58.515480
2035 00:22:58.515766 Final TX Range 1 Vref 32
2036 00:22:58.516042
2037 00:22:58.516323 ==
2038 00:22:58.516599 Dram Type= 6, Freq= 0, CH_1, rank 1
2039 00:22:58.516867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2040 00:22:58.517161 ==
2041 00:22:58.517425
2042 00:22:58.517717
2043 00:22:58.518003 TX Vref Scan disable
2044 00:22:58.518416 == TX Byte 0 ==
2045 00:22:58.518700 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
2046 00:22:58.519003 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2047 00:22:58.519277 == TX Byte 1 ==
2048 00:22:58.519564 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
2049 00:22:58.519838 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2050 00:22:58.520107
2051 00:22:58.520404 [DATLAT]
2052 00:22:58.520597 Freq=800, CH1 RK1
2053 00:22:58.520786
2054 00:22:58.521025 DATLAT Default: 0xa
2055 00:22:58.521226 0, 0xFFFF, sum = 0
2056 00:22:58.521422 1, 0xFFFF, sum = 0
2057 00:22:58.521644 2, 0xFFFF, sum = 0
2058 00:22:58.521837 3, 0xFFFF, sum = 0
2059 00:22:58.522029 4, 0xFFFF, sum = 0
2060 00:22:58.522290 5, 0xFFFF, sum = 0
2061 00:22:58.522491 6, 0xFFFF, sum = 0
2062 00:22:58.522687 7, 0xFFFF, sum = 0
2063 00:22:58.522904 8, 0xFFFF, sum = 0
2064 00:22:58.523101 9, 0x0, sum = 1
2065 00:22:58.523295 10, 0x0, sum = 2
2066 00:22:58.523512 11, 0x0, sum = 3
2067 00:22:58.523710 12, 0x0, sum = 4
2068 00:22:58.523900 best_step = 10
2069 00:22:58.524105
2070 00:22:58.524298 ==
2071 00:22:58.524488 Dram Type= 6, Freq= 0, CH_1, rank 1
2072 00:22:58.524684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2073 00:22:58.524898 ==
2074 00:22:58.525088 RX Vref Scan: 0
2075 00:22:58.525277
2076 00:22:58.525468 RX Vref 0 -> 0, step: 1
2077 00:22:58.525613
2078 00:22:58.525755 RX Delay -95 -> 252, step: 8
2079 00:22:58.525897 iDelay=217, Bit 0, Center 92 (-23 ~ 208) 232
2080 00:22:58.526072 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2081 00:22:58.526273 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
2082 00:22:58.526424 iDelay=217, Bit 3, Center 84 (-23 ~ 192) 216
2083 00:22:58.526570 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2084 00:22:58.526735 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2085 00:22:58.526894 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2086 00:22:58.527038 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2087 00:22:58.527182 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2088 00:22:58.527344 iDelay=217, Bit 9, Center 72 (-39 ~ 184) 224
2089 00:22:58.527488 iDelay=217, Bit 10, Center 80 (-39 ~ 200) 240
2090 00:22:58.527632 iDelay=217, Bit 11, Center 72 (-39 ~ 184) 224
2091 00:22:58.527774 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
2092 00:22:58.527934 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2093 00:22:58.528081 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2094 00:22:58.528224 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2095 00:22:58.528365 ==
2096 00:22:58.528518 Dram Type= 6, Freq= 0, CH_1, rank 1
2097 00:22:58.528665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2098 00:22:58.528809 ==
2099 00:22:58.528952 DQS Delay:
2100 00:22:58.529095 DQS0 = 0, DQS1 = 0
2101 00:22:58.529249 DQM Delay:
2102 00:22:58.529391 DQM0 = 87, DQM1 = 79
2103 00:22:58.529537 DQ Delay:
2104 00:22:58.529684 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
2105 00:22:58.529843 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2106 00:22:58.529989 DQ8 =68, DQ9 =72, DQ10 =80, DQ11 =72
2107 00:22:58.530134 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
2108 00:22:58.530317
2109 00:22:58.530457
2110 00:22:58.530573 [DQSOSCAuto] RK1, (LSB)MR18= 0x1a13, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
2111 00:22:58.530691 CH1 RK1: MR19=606, MR18=1A13
2112 00:22:58.530809 CH1_RK1: MR19=0x606, MR18=0x1A13, DQSOSC=403, MR23=63, INC=90, DEC=60
2113 00:22:58.530983 [RxdqsGatingPostProcess] freq 800
2114 00:22:58.531173 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2115 00:22:58.531297 Pre-setting of DQS Precalculation
2116 00:22:58.531414 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2117 00:22:58.531533 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2118 00:22:58.531665 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2119 00:22:58.531782
2120 00:22:58.531898
2121 00:22:58.532013 [Calibration Summary] 1600 Mbps
2122 00:22:58.532128 CH 0, Rank 0
2123 00:22:58.532260 SW Impedance : PASS
2124 00:22:58.532378 DUTY Scan : NO K
2125 00:22:58.532495 ZQ Calibration : PASS
2126 00:22:58.532609 Jitter Meter : NO K
2127 00:22:58.532725 CBT Training : PASS
2128 00:22:58.532860 Write leveling : PASS
2129 00:22:58.532978 RX DQS gating : PASS
2130 00:22:58.533094 RX DQ/DQS(RDDQC) : PASS
2131 00:22:58.533211 TX DQ/DQS : PASS
2132 00:22:58.533327 RX DATLAT : PASS
2133 00:22:58.533497 RX DQ/DQS(Engine): PASS
2134 00:22:58.533619 TX OE : NO K
2135 00:22:58.533737 All Pass.
2136 00:22:58.533853
2137 00:22:58.533996 CH 0, Rank 1
2138 00:22:58.534460 SW Impedance : PASS
2139 00:22:58.534654 DUTY Scan : NO K
2140 00:22:58.534796 ZQ Calibration : PASS
2141 00:22:58.534982 Jitter Meter : NO K
2142 00:22:58.535180 CBT Training : PASS
2143 00:22:58.535309 Write leveling : PASS
2144 00:22:58.535427 RX DQS gating : PASS
2145 00:22:58.535525 RX DQ/DQS(RDDQC) : PASS
2146 00:22:58.535622 TX DQ/DQS : PASS
2147 00:22:58.535756 RX DATLAT : PASS
2148 00:22:58.535858 RX DQ/DQS(Engine): PASS
2149 00:22:58.535955 TX OE : NO K
2150 00:22:58.536052 All Pass.
2151 00:22:58.536153
2152 00:22:58.536276 CH 1, Rank 0
2153 00:22:58.536380 SW Impedance : PASS
2154 00:22:58.536477 DUTY Scan : NO K
2155 00:22:58.536575 ZQ Calibration : PASS
2156 00:22:58.536672 Jitter Meter : NO K
2157 00:22:58.536781 CBT Training : PASS
2158 00:22:58.536897 Write leveling : PASS
2159 00:22:58.536994 RX DQS gating : PASS
2160 00:22:58.537092 RX DQ/DQS(RDDQC) : PASS
2161 00:22:58.537187 TX DQ/DQS : PASS
2162 00:22:58.537284 RX DATLAT : PASS
2163 00:22:58.537419 RX DQ/DQS(Engine): PASS
2164 00:22:58.537519 TX OE : NO K
2165 00:22:58.537617 All Pass.
2166 00:22:58.537713
2167 00:22:58.537809 CH 1, Rank 1
2168 00:22:58.537940 SW Impedance : PASS
2169 00:22:58.538042 DUTY Scan : NO K
2170 00:22:58.538139 ZQ Calibration : PASS
2171 00:22:58.538251 Jitter Meter : NO K
2172 00:22:58.538350 CBT Training : PASS
2173 00:22:58.538482 Write leveling : PASS
2174 00:22:58.538584 RX DQS gating : PASS
2175 00:22:58.538682 RX DQ/DQS(RDDQC) : PASS
2176 00:22:58.538783 TX DQ/DQS : PASS
2177 00:22:58.538888 RX DATLAT : PASS
2178 00:22:58.539013 RX DQ/DQS(Engine): PASS
2179 00:22:58.539116 TX OE : NO K
2180 00:22:58.539215 All Pass.
2181 00:22:58.539312
2182 00:22:58.539408 DramC Write-DBI off
2183 00:22:58.539523 PER_BANK_REFRESH: Hybrid Mode
2184 00:22:58.539637 TX_TRACKING: ON
2185 00:22:58.539736 [GetDramInforAfterCalByMRR] Vendor 6.
2186 00:22:58.539833 [GetDramInforAfterCalByMRR] Revision 606.
2187 00:22:58.539930 [GetDramInforAfterCalByMRR] Revision 2 0.
2188 00:22:58.540027 MR0 0x3b3b
2189 00:22:58.540161 MR8 0x5151
2190 00:22:58.540259 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2191 00:22:58.540368
2192 00:22:58.540451 MR0 0x3b3b
2193 00:22:58.540534 MR8 0x5151
2194 00:22:58.540646 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2195 00:22:58.540735
2196 00:22:58.540861 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2197 00:22:58.541010 [FAST_K] Save calibration result to emmc
2198 00:22:58.541102 [FAST_K] Save calibration result to emmc
2199 00:22:58.541221 dram_init: config_dvfs: 1
2200 00:22:58.541309 dramc_set_vcore_voltage set vcore to 662500
2201 00:22:58.541394 Read voltage for 1200, 2
2202 00:22:58.541479 Vio18 = 0
2203 00:22:58.541564 Vcore = 662500
2204 00:22:58.541649 Vdram = 0
2205 00:22:58.541759 Vddq = 0
2206 00:22:58.541843 Vmddr = 0
2207 00:22:58.541926 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2208 00:22:58.542011 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2209 00:22:58.542094 MEM_TYPE=3, freq_sel=15
2210 00:22:58.542190 sv_algorithm_assistance_LP4_1600
2211 00:22:58.542305 ============ PULL DRAM RESETB DOWN ============
2212 00:22:58.542392 ========== PULL DRAM RESETB DOWN end =========
2213 00:22:58.542476 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2214 00:22:58.542560 ===================================
2215 00:22:58.542644 LPDDR4 DRAM CONFIGURATION
2216 00:22:58.542729 ===================================
2217 00:22:58.542846 EX_ROW_EN[0] = 0x0
2218 00:22:58.542933 EX_ROW_EN[1] = 0x0
2219 00:22:58.543016 LP4Y_EN = 0x0
2220 00:22:58.543099 WORK_FSP = 0x0
2221 00:22:58.543182 WL = 0x4
2222 00:22:58.543266 RL = 0x4
2223 00:22:58.543378 BL = 0x2
2224 00:22:58.543463 RPST = 0x0
2225 00:22:58.543547 RD_PRE = 0x0
2226 00:22:58.543630 WR_PRE = 0x1
2227 00:22:58.543713 WR_PST = 0x0
2228 00:22:58.543796 DBI_WR = 0x0
2229 00:22:58.543912 DBI_RD = 0x0
2230 00:22:58.543999 OTF = 0x1
2231 00:22:58.544082 ===================================
2232 00:22:58.544167 ===================================
2233 00:22:58.544252 ANA top config
2234 00:22:58.544335 ===================================
2235 00:22:58.544453 DLL_ASYNC_EN = 0
2236 00:22:58.544540 ALL_SLAVE_EN = 0
2237 00:22:58.544624 NEW_RANK_MODE = 1
2238 00:22:58.544709 DLL_IDLE_MODE = 1
2239 00:22:58.544793 LP45_APHY_COMB_EN = 1
2240 00:22:58.544877 TX_ODT_DIS = 1
2241 00:22:58.544994 NEW_8X_MODE = 1
2242 00:22:58.545082 ===================================
2243 00:22:58.545168 ===================================
2244 00:22:58.545254 data_rate = 2400
2245 00:22:58.545348 CKR = 1
2246 00:22:58.545422 DQ_P2S_RATIO = 8
2247 00:22:58.545525 ===================================
2248 00:22:58.545601 CA_P2S_RATIO = 8
2249 00:22:58.545675 DQ_CA_OPEN = 0
2250 00:22:58.545749 DQ_SEMI_OPEN = 0
2251 00:22:58.545822 CA_SEMI_OPEN = 0
2252 00:22:58.545895 CA_FULL_RATE = 0
2253 00:22:58.545975 DQ_CKDIV4_EN = 0
2254 00:22:58.546101 CA_CKDIV4_EN = 0
2255 00:22:58.546213 CA_PREDIV_EN = 0
2256 00:22:58.546289 PH8_DLY = 17
2257 00:22:58.546363 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2258 00:22:58.546436 DQ_AAMCK_DIV = 4
2259 00:22:58.546525 CA_AAMCK_DIV = 4
2260 00:22:58.546607 CA_ADMCK_DIV = 4
2261 00:22:58.546680 DQ_TRACK_CA_EN = 0
2262 00:22:58.546753 CA_PICK = 1200
2263 00:22:58.546826 CA_MCKIO = 1200
2264 00:22:58.546900 MCKIO_SEMI = 0
2265 00:22:58.546973 PLL_FREQ = 2366
2266 00:22:58.547064 DQ_UI_PI_RATIO = 32
2267 00:22:58.547142 CA_UI_PI_RATIO = 0
2268 00:22:58.547216 ===================================
2269 00:22:58.547289 ===================================
2270 00:22:58.547362 memory_type:LPDDR4
2271 00:22:58.547435 GP_NUM : 10
2272 00:22:58.547508 SRAM_EN : 1
2273 00:22:58.547596 MD32_EN : 0
2274 00:22:58.547678 ===================================
2275 00:22:58.547753 [ANA_INIT] >>>>>>>>>>>>>>
2276 00:22:58.547827 <<<<<< [CONFIGURE PHASE]: ANA_TX
2277 00:22:58.547900 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2278 00:22:58.547973 ===================================
2279 00:22:58.548046 data_rate = 2400,PCW = 0X5b00
2280 00:22:58.548138 ===================================
2281 00:22:58.548216 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2282 00:22:58.548290 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2283 00:22:58.548575 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2284 00:22:58.548679 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2285 00:22:58.548761 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2286 00:22:58.548835 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2287 00:22:58.548909 [ANA_INIT] flow start
2288 00:22:58.548983 [ANA_INIT] PLL >>>>>>>>
2289 00:22:58.549056 [ANA_INIT] PLL <<<<<<<<
2290 00:22:58.549129 [ANA_INIT] MIDPI >>>>>>>>
2291 00:22:58.549222 [ANA_INIT] MIDPI <<<<<<<<
2292 00:22:58.549299 [ANA_INIT] DLL >>>>>>>>
2293 00:22:58.549372 [ANA_INIT] DLL <<<<<<<<
2294 00:22:58.549445 [ANA_INIT] flow end
2295 00:22:58.549517 ============ LP4 DIFF to SE enter ============
2296 00:22:58.549591 ============ LP4 DIFF to SE exit ============
2297 00:22:58.549664 [ANA_INIT] <<<<<<<<<<<<<
2298 00:22:58.549755 [Flow] Enable top DCM control >>>>>
2299 00:22:58.549834 [Flow] Enable top DCM control <<<<<
2300 00:22:58.549908 Enable DLL master slave shuffle
2301 00:22:58.549982 ==============================================================
2302 00:22:58.550056 Gating Mode config
2303 00:22:58.550130 ==============================================================
2304 00:22:58.550218 Config description:
2305 00:22:58.550325 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2306 00:22:58.550414 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2307 00:22:58.550480 SELPH_MODE 0: By rank 1: By Phase
2308 00:22:58.550547 ==============================================================
2309 00:22:58.550613 GAT_TRACK_EN = 1
2310 00:22:58.550678 RX_GATING_MODE = 2
2311 00:22:58.550743 RX_GATING_TRACK_MODE = 2
2312 00:22:58.550832 SELPH_MODE = 1
2313 00:22:58.550902 PICG_EARLY_EN = 1
2314 00:22:58.550967 VALID_LAT_VALUE = 1
2315 00:22:58.551032 ==============================================================
2316 00:22:58.551098 Enter into Gating configuration >>>>
2317 00:22:58.551163 Exit from Gating configuration <<<<
2318 00:22:58.551229 Enter into DVFS_PRE_config >>>>>
2319 00:22:58.551294 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2320 00:22:58.551389 Exit from DVFS_PRE_config <<<<<
2321 00:22:58.551456 Enter into PICG configuration >>>>
2322 00:22:58.551522 Exit from PICG configuration <<<<
2323 00:22:58.551587 [RX_INPUT] configuration >>>>>
2324 00:22:58.551653 [RX_INPUT] configuration <<<<<
2325 00:22:58.551718 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2326 00:22:58.551784 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2327 00:22:58.551854 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2328 00:22:58.551939 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2329 00:22:58.552005 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2330 00:22:58.552071 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2331 00:22:58.552136 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2332 00:22:58.552202 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2333 00:22:58.552268 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2334 00:22:58.552333 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2335 00:22:58.552414 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2336 00:22:58.552484 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2337 00:22:58.552550 ===================================
2338 00:22:58.552615 LPDDR4 DRAM CONFIGURATION
2339 00:22:58.552680 ===================================
2340 00:22:58.552746 EX_ROW_EN[0] = 0x0
2341 00:22:58.552811 EX_ROW_EN[1] = 0x0
2342 00:22:58.552876 LP4Y_EN = 0x0
2343 00:22:58.552963 WORK_FSP = 0x0
2344 00:22:58.553031 WL = 0x4
2345 00:22:58.553096 RL = 0x4
2346 00:22:58.553162 BL = 0x2
2347 00:22:58.553226 RPST = 0x0
2348 00:22:58.553290 RD_PRE = 0x0
2349 00:22:58.553355 WR_PRE = 0x1
2350 00:22:58.553419 WR_PST = 0x0
2351 00:22:58.553507 DBI_WR = 0x0
2352 00:22:58.553575 DBI_RD = 0x0
2353 00:22:58.553640 OTF = 0x1
2354 00:22:58.553706 ===================================
2355 00:22:58.553771 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2356 00:22:58.553837 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2357 00:22:58.553902 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2358 00:22:58.553968 ===================================
2359 00:22:58.554084 LPDDR4 DRAM CONFIGURATION
2360 00:22:58.554189 ===================================
2361 00:22:58.554258 EX_ROW_EN[0] = 0x10
2362 00:22:58.554324 EX_ROW_EN[1] = 0x0
2363 00:22:58.554389 LP4Y_EN = 0x0
2364 00:22:58.554454 WORK_FSP = 0x0
2365 00:22:58.554534 WL = 0x4
2366 00:22:58.554605 RL = 0x4
2367 00:22:58.554669 BL = 0x2
2368 00:22:58.554733 RPST = 0x0
2369 00:22:58.554796 RD_PRE = 0x0
2370 00:22:58.554861 WR_PRE = 0x1
2371 00:22:58.554925 WR_PST = 0x0
2372 00:22:58.554988 DBI_WR = 0x0
2373 00:22:58.555069 DBI_RD = 0x0
2374 00:22:58.555138 OTF = 0x1
2375 00:22:58.555203 ===================================
2376 00:22:58.555269 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2377 00:22:58.555345 ==
2378 00:22:58.555403 Dram Type= 6, Freq= 0, CH_0, rank 0
2379 00:22:58.555462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2380 00:22:58.555521 ==
2381 00:22:58.555591 [Duty_Offset_Calibration]
2382 00:22:58.555657 B0:1 B1:-1 CA:0
2383 00:22:58.555716
2384 00:22:58.555774 [DutyScan_Calibration_Flow] k_type=0
2385 00:22:58.555833
2386 00:22:58.555890 ==CLK 0==
2387 00:22:58.555959 Final CLK duty delay cell = 0
2388 00:22:58.556019 [0] MAX Duty = 5125%(X100), DQS PI = 24
2389 00:22:58.556078 [0] MIN Duty = 4875%(X100), DQS PI = 8
2390 00:22:58.556161 [0] AVG Duty = 5000%(X100)
2391 00:22:58.556221
2392 00:22:58.556280 CH0 CLK Duty spec in!! Max-Min= 250%
2393 00:22:58.556340 [DutyScan_Calibration_Flow] ====Done====
2394 00:22:58.556398
2395 00:22:58.556455 [DutyScan_Calibration_Flow] k_type=1
2396 00:22:58.556513
2397 00:22:58.556570 ==DQS 0 ==
2398 00:22:58.556640 Final DQS duty delay cell = -4
2399 00:22:58.556905 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2400 00:22:58.556971 [-4] MIN Duty = 4875%(X100), DQS PI = 46
2401 00:22:58.557030 [-4] AVG Duty = 4968%(X100)
2402 00:22:58.557088
2403 00:22:58.557146 ==DQS 1 ==
2404 00:22:58.557229 Final DQS duty delay cell = 0
2405 00:22:58.557290 [0] MAX Duty = 5124%(X100), DQS PI = 4
2406 00:22:58.557349 [0] MIN Duty = 5000%(X100), DQS PI = 22
2407 00:22:58.557408 [0] AVG Duty = 5062%(X100)
2408 00:22:58.557465
2409 00:22:58.557524 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2410 00:22:58.557582
2411 00:22:58.557639 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2412 00:22:58.557706 [DutyScan_Calibration_Flow] ====Done====
2413 00:22:58.557775
2414 00:22:58.557833 [DutyScan_Calibration_Flow] k_type=3
2415 00:22:58.557891
2416 00:22:58.557948 ==DQM 0 ==
2417 00:22:58.558006 Final DQM duty delay cell = 0
2418 00:22:58.558065 [0] MAX Duty = 5062%(X100), DQS PI = 20
2419 00:22:58.558123 [0] MIN Duty = 4844%(X100), DQS PI = 8
2420 00:22:58.558193 [0] AVG Duty = 4953%(X100)
2421 00:22:58.558276
2422 00:22:58.558337 ==DQM 1 ==
2423 00:22:58.558397 Final DQM duty delay cell = 4
2424 00:22:58.558455 [4] MAX Duty = 5187%(X100), DQS PI = 56
2425 00:22:58.558514 [4] MIN Duty = 4969%(X100), DQS PI = 24
2426 00:22:58.558571 [4] AVG Duty = 5078%(X100)
2427 00:22:58.558629
2428 00:22:58.558686 CH0 DQM 0 Duty spec in!! Max-Min= 218%
2429 00:22:58.558743
2430 00:22:58.558823 CH0 DQM 1 Duty spec in!! Max-Min= 218%
2431 00:22:58.558883 [DutyScan_Calibration_Flow] ====Done====
2432 00:22:58.558940
2433 00:22:58.558998 [DutyScan_Calibration_Flow] k_type=2
2434 00:22:58.559055
2435 00:22:58.559113 ==DQ 0 ==
2436 00:22:58.559170 Final DQ duty delay cell = 0
2437 00:22:58.559229 [0] MAX Duty = 5125%(X100), DQS PI = 22
2438 00:22:58.559304 [0] MIN Duty = 5000%(X100), DQS PI = 0
2439 00:22:58.559366 [0] AVG Duty = 5062%(X100)
2440 00:22:58.559424
2441 00:22:58.559482 ==DQ 1 ==
2442 00:22:58.559540 Final DQ duty delay cell = -4
2443 00:22:58.559599 [-4] MAX Duty = 4969%(X100), DQS PI = 54
2444 00:22:58.559657 [-4] MIN Duty = 4876%(X100), DQS PI = 16
2445 00:22:58.559715 [-4] AVG Duty = 4922%(X100)
2446 00:22:58.559774
2447 00:22:58.559856 CH0 DQ 0 Duty spec in!! Max-Min= 125%
2448 00:22:58.559917
2449 00:22:58.559975 CH0 DQ 1 Duty spec in!! Max-Min= 93%
2450 00:22:58.560033 [DutyScan_Calibration_Flow] ====Done====
2451 00:22:58.560091 ==
2452 00:22:58.560149 Dram Type= 6, Freq= 0, CH_1, rank 0
2453 00:22:58.560206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2454 00:22:58.560265 ==
2455 00:22:58.560322 [Duty_Offset_Calibration]
2456 00:22:58.560408 B0:-1 B1:1 CA:1
2457 00:22:58.560462
2458 00:22:58.560515 [DutyScan_Calibration_Flow] k_type=0
2459 00:22:58.560568
2460 00:22:58.560620 ==CLK 0==
2461 00:22:58.560673 Final CLK duty delay cell = 0
2462 00:22:58.560727 [0] MAX Duty = 5156%(X100), DQS PI = 22
2463 00:22:58.560780 [0] MIN Duty = 4969%(X100), DQS PI = 60
2464 00:22:58.560833 [0] AVG Duty = 5062%(X100)
2465 00:22:58.560885
2466 00:22:58.560937 CH1 CLK Duty spec in!! Max-Min= 187%
2467 00:22:58.560991 [DutyScan_Calibration_Flow] ====Done====
2468 00:22:58.561043
2469 00:22:58.561096 [DutyScan_Calibration_Flow] k_type=1
2470 00:22:58.561148
2471 00:22:58.561200 ==DQS 0 ==
2472 00:22:58.561253 Final DQS duty delay cell = 0
2473 00:22:58.561307 [0] MAX Duty = 5125%(X100), DQS PI = 48
2474 00:22:58.561360 [0] MIN Duty = 4875%(X100), DQS PI = 6
2475 00:22:58.561413 [0] AVG Duty = 5000%(X100)
2476 00:22:58.561470
2477 00:22:58.561535 ==DQS 1 ==
2478 00:22:58.561588 Final DQS duty delay cell = 0
2479 00:22:58.561641 [0] MAX Duty = 5094%(X100), DQS PI = 12
2480 00:22:58.561694 [0] MIN Duty = 4969%(X100), DQS PI = 0
2481 00:22:58.561747 [0] AVG Duty = 5031%(X100)
2482 00:22:58.561800
2483 00:22:58.561852 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2484 00:22:58.561905
2485 00:22:58.561957 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2486 00:22:58.562026 [DutyScan_Calibration_Flow] ====Done====
2487 00:22:58.562111
2488 00:22:58.562194 [DutyScan_Calibration_Flow] k_type=3
2489 00:22:58.562251
2490 00:22:58.562304 ==DQM 0 ==
2491 00:22:58.562356 Final DQM duty delay cell = -4
2492 00:22:58.562410 [-4] MAX Duty = 5031%(X100), DQS PI = 16
2493 00:22:58.562464 [-4] MIN Duty = 4876%(X100), DQS PI = 4
2494 00:22:58.562516 [-4] AVG Duty = 4953%(X100)
2495 00:22:58.562588
2496 00:22:58.562642 ==DQM 1 ==
2497 00:22:58.562696 Final DQM duty delay cell = 0
2498 00:22:58.562749 [0] MAX Duty = 5156%(X100), DQS PI = 4
2499 00:22:58.562802 [0] MIN Duty = 4969%(X100), DQS PI = 28
2500 00:22:58.562854 [0] AVG Duty = 5062%(X100)
2501 00:22:58.562906
2502 00:22:58.562959 CH1 DQM 0 Duty spec in!! Max-Min= 155%
2503 00:22:58.563011
2504 00:22:58.563080 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2505 00:22:58.563137 [DutyScan_Calibration_Flow] ====Done====
2506 00:22:58.563190
2507 00:22:58.563242 [DutyScan_Calibration_Flow] k_type=2
2508 00:22:58.563295
2509 00:22:58.563347 ==DQ 0 ==
2510 00:22:58.563400 Final DQ duty delay cell = 0
2511 00:22:58.563453 [0] MAX Duty = 5187%(X100), DQS PI = 30
2512 00:22:58.563506 [0] MIN Duty = 4907%(X100), DQS PI = 6
2513 00:22:58.563559 [0] AVG Duty = 5047%(X100)
2514 00:22:58.563632
2515 00:22:58.563686 ==DQ 1 ==
2516 00:22:58.563739 Final DQ duty delay cell = 0
2517 00:22:58.563793 [0] MAX Duty = 5124%(X100), DQS PI = 10
2518 00:22:58.563846 [0] MIN Duty = 4969%(X100), DQS PI = 34
2519 00:22:58.563898 [0] AVG Duty = 5046%(X100)
2520 00:22:58.563950
2521 00:22:58.564002 CH1 DQ 0 Duty spec in!! Max-Min= 280%
2522 00:22:58.564054
2523 00:22:58.564117 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2524 00:22:58.564178 [DutyScan_Calibration_Flow] ====Done====
2525 00:22:58.564231 nWR fixed to 30
2526 00:22:58.564285 [ModeRegInit_LP4] CH0 RK0
2527 00:22:58.564338 [ModeRegInit_LP4] CH0 RK1
2528 00:22:58.564390 [ModeRegInit_LP4] CH1 RK0
2529 00:22:58.564443 [ModeRegInit_LP4] CH1 RK1
2530 00:22:58.564496 match AC timing 7
2531 00:22:58.564549 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2532 00:22:58.564603 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2533 00:22:58.564676 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2534 00:22:58.564731 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2535 00:22:58.564785 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2536 00:22:58.564838 ==
2537 00:22:58.564891 Dram Type= 6, Freq= 0, CH_0, rank 0
2538 00:22:58.564944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2539 00:22:58.564997 ==
2540 00:22:58.565050 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2541 00:22:58.565103 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2542 00:22:58.565167 [CA 0] Center 39 (9~70) winsize 62
2543 00:22:58.565227 [CA 1] Center 38 (8~69) winsize 62
2544 00:22:58.565281 [CA 2] Center 35 (5~66) winsize 62
2545 00:22:58.565334 [CA 3] Center 35 (5~65) winsize 61
2546 00:22:58.565399 [CA 4] Center 33 (3~63) winsize 61
2547 00:22:58.565450 [CA 5] Center 33 (3~63) winsize 61
2548 00:22:58.565501
2549 00:22:58.565552 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2550 00:22:58.565604
2551 00:22:58.565656 [CATrainingPosCal] consider 1 rank data
2552 00:22:58.565923 u2DelayCellTimex100 = 270/100 ps
2553 00:22:58.565986 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2554 00:22:58.566040 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2555 00:22:58.566093 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2556 00:22:58.566145 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2557 00:22:58.566253 CA4 delay=33 (3~63),Diff = 0 PI (0 cell)
2558 00:22:58.566309 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2559 00:22:58.566361
2560 00:22:58.566429 CA PerBit enable=1, Macro0, CA PI delay=33
2561 00:22:58.566494
2562 00:22:58.566546 [CBTSetCACLKResult] CA Dly = 33
2563 00:22:58.566597 CS Dly: 8 (0~39)
2564 00:22:58.566649 ==
2565 00:22:58.566701 Dram Type= 6, Freq= 0, CH_0, rank 1
2566 00:22:58.566756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2567 00:22:58.566823 ==
2568 00:22:58.566875 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2569 00:22:58.566928 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2570 00:22:58.566982 [CA 0] Center 39 (8~70) winsize 63
2571 00:22:58.567034 [CA 1] Center 39 (9~70) winsize 62
2572 00:22:58.567086 [CA 2] Center 35 (5~66) winsize 62
2573 00:22:58.567137 [CA 3] Center 34 (4~65) winsize 62
2574 00:22:58.567189 [CA 4] Center 33 (3~63) winsize 61
2575 00:22:58.567240 [CA 5] Center 33 (3~63) winsize 61
2576 00:22:58.567311
2577 00:22:58.567365 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2578 00:22:58.567417
2579 00:22:58.567468 [CATrainingPosCal] consider 2 rank data
2580 00:22:58.567520 u2DelayCellTimex100 = 270/100 ps
2581 00:22:58.567571 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2582 00:22:58.567623 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2583 00:22:58.567674 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2584 00:22:58.567725 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2585 00:22:58.567784 CA4 delay=33 (3~63),Diff = 0 PI (0 cell)
2586 00:22:58.567845 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2587 00:22:58.567897
2588 00:22:58.567948 CA PerBit enable=1, Macro0, CA PI delay=33
2589 00:22:58.568000
2590 00:22:58.568051 [CBTSetCACLKResult] CA Dly = 33
2591 00:22:58.568103 CS Dly: 8 (0~40)
2592 00:22:58.568155
2593 00:22:58.568207 ----->DramcWriteLeveling(PI) begin...
2594 00:22:58.568260 ==
2595 00:22:58.568325 Dram Type= 6, Freq= 0, CH_0, rank 0
2596 00:22:58.568381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2597 00:22:58.568440 ==
2598 00:22:58.568493 Write leveling (Byte 0): 34 => 34
2599 00:22:58.568545 Write leveling (Byte 1): 30 => 30
2600 00:22:58.568597 DramcWriteLeveling(PI) end<-----
2601 00:22:58.568649
2602 00:22:58.568700 ==
2603 00:22:58.568752 Dram Type= 6, Freq= 0, CH_0, rank 0
2604 00:22:58.568803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2605 00:22:58.568869 ==
2606 00:22:58.568925 [Gating] SW mode calibration
2607 00:22:58.568977 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2608 00:22:58.569030 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2609 00:22:58.569082 0 15 0 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
2610 00:22:58.569135 0 15 4 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
2611 00:22:58.569187 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2612 00:22:58.569238 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2613 00:22:58.569290 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2614 00:22:58.569341 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2615 00:22:58.569415 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2616 00:22:58.569469 0 15 28 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (1 0)
2617 00:22:58.569520 1 0 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
2618 00:22:58.569573 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2619 00:22:58.569624 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2620 00:22:58.569676 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2621 00:22:58.569728 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2622 00:22:58.569779 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2623 00:22:58.569830 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2624 00:22:58.569882 1 0 28 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
2625 00:22:58.569953 1 1 0 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
2626 00:22:58.570006 1 1 4 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
2627 00:22:58.570058 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2628 00:22:58.570109 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2629 00:22:58.570167 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2630 00:22:58.570221 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2631 00:22:58.570273 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2632 00:22:58.570324 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2633 00:22:58.570376 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2634 00:22:58.570450 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2635 00:22:58.570507 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2636 00:22:58.570559 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2637 00:22:58.570611 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2638 00:22:58.570663 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2639 00:22:58.570715 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2640 00:22:58.570766 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2641 00:22:58.570817 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2642 00:22:58.570869 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2643 00:22:58.570921 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2644 00:22:58.570994 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2645 00:22:58.571048 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2646 00:22:58.571100 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2647 00:22:58.571152 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2648 00:22:58.571204 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
2649 00:22:58.571256 Total UI for P1: 0, mck2ui 16
2650 00:22:58.571308 best dqsien dly found for B0: ( 1, 3, 26)
2651 00:22:58.571360 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2652 00:22:58.571412 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2653 00:22:58.571474 Total UI for P1: 0, mck2ui 16
2654 00:22:58.571533 best dqsien dly found for B1: ( 1, 4, 0)
2655 00:22:58.571778 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2656 00:22:58.571836 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2657 00:22:58.571889
2658 00:22:58.571940 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2659 00:22:58.572006 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2660 00:22:58.572062 [Gating] SW calibration Done
2661 00:22:58.572115 ==
2662 00:22:58.572167 Dram Type= 6, Freq= 0, CH_0, rank 0
2663 00:22:58.572219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2664 00:22:58.572271 ==
2665 00:22:58.572323 RX Vref Scan: 0
2666 00:22:58.572375
2667 00:22:58.572425 RX Vref 0 -> 0, step: 1
2668 00:22:58.572477
2669 00:22:58.572543 RX Delay -40 -> 252, step: 8
2670 00:22:58.572598 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2671 00:22:58.572650 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2672 00:22:58.572702 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2673 00:22:58.572754 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2674 00:22:58.572806 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2675 00:22:58.572857 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2676 00:22:58.572909 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2677 00:22:58.572961 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2678 00:22:58.573012 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2679 00:22:58.573084 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2680 00:22:58.573138 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2681 00:22:58.573190 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2682 00:22:58.573242 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2683 00:22:58.573293 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2684 00:22:58.573345 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2685 00:22:58.573397 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2686 00:22:58.573448 ==
2687 00:22:58.573500 Dram Type= 6, Freq= 0, CH_0, rank 0
2688 00:22:58.573573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2689 00:22:58.573629 ==
2690 00:22:58.573681 DQS Delay:
2691 00:22:58.573732 DQS0 = 0, DQS1 = 0
2692 00:22:58.573784 DQM Delay:
2693 00:22:58.573835 DQM0 = 119, DQM1 = 106
2694 00:22:58.573887 DQ Delay:
2695 00:22:58.573938 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2696 00:22:58.573989 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2697 00:22:58.574041 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2698 00:22:58.574119 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2699 00:22:58.574220
2700 00:22:58.574286
2701 00:22:58.574338 ==
2702 00:22:58.574390 Dram Type= 6, Freq= 0, CH_0, rank 0
2703 00:22:58.574442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2704 00:22:58.574494 ==
2705 00:22:58.574546
2706 00:22:58.574597
2707 00:22:58.574667 TX Vref Scan disable
2708 00:22:58.574721 == TX Byte 0 ==
2709 00:22:58.574773 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2710 00:22:58.574825 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2711 00:22:58.574876 == TX Byte 1 ==
2712 00:22:58.574927 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2713 00:22:58.574980 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2714 00:22:58.575032 ==
2715 00:22:58.575083 Dram Type= 6, Freq= 0, CH_0, rank 0
2716 00:22:58.575144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2717 00:22:58.575205 ==
2718 00:22:58.575257 TX Vref=22, minBit 1, minWin=25, winSum=412
2719 00:22:58.575309 TX Vref=24, minBit 10, minWin=25, winSum=421
2720 00:22:58.575361 TX Vref=26, minBit 1, minWin=26, winSum=422
2721 00:22:58.575413 TX Vref=28, minBit 1, minWin=26, winSum=427
2722 00:22:58.575466 TX Vref=30, minBit 3, minWin=26, winSum=426
2723 00:22:58.575518 TX Vref=32, minBit 0, minWin=26, winSum=429
2724 00:22:58.575570 [TxChooseVref] Worse bit 0, Min win 26, Win sum 429, Final Vref 32
2725 00:22:58.575621
2726 00:22:58.575690 Final TX Range 1 Vref 32
2727 00:22:58.575746
2728 00:22:58.575797 ==
2729 00:22:58.575849 Dram Type= 6, Freq= 0, CH_0, rank 0
2730 00:22:58.575901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2731 00:22:58.575952 ==
2732 00:22:58.576003
2733 00:22:58.576055
2734 00:22:58.576106 TX Vref Scan disable
2735 00:22:58.576158 == TX Byte 0 ==
2736 00:22:58.576224 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2737 00:22:58.576279 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2738 00:22:58.576331 == TX Byte 1 ==
2739 00:22:58.576383 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2740 00:22:58.576435 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2741 00:22:58.576486
2742 00:22:58.576537 [DATLAT]
2743 00:22:58.576588 Freq=1200, CH0 RK0
2744 00:22:58.576640
2745 00:22:58.576692 DATLAT Default: 0xd
2746 00:22:58.576763 0, 0xFFFF, sum = 0
2747 00:22:58.576819 1, 0xFFFF, sum = 0
2748 00:22:58.576873 2, 0xFFFF, sum = 0
2749 00:22:58.576925 3, 0xFFFF, sum = 0
2750 00:22:58.576977 4, 0xFFFF, sum = 0
2751 00:22:58.577029 5, 0xFFFF, sum = 0
2752 00:22:58.577081 6, 0xFFFF, sum = 0
2753 00:22:58.577134 7, 0xFFFF, sum = 0
2754 00:22:58.577186 8, 0xFFFF, sum = 0
2755 00:22:58.577241 9, 0xFFFF, sum = 0
2756 00:22:58.577309 10, 0xFFFF, sum = 0
2757 00:22:58.577363 11, 0xFFFF, sum = 0
2758 00:22:58.577415 12, 0x0, sum = 1
2759 00:22:58.577467 13, 0x0, sum = 2
2760 00:22:58.577519 14, 0x0, sum = 3
2761 00:22:58.577571 15, 0x0, sum = 4
2762 00:22:58.577624 best_step = 13
2763 00:22:58.577675
2764 00:22:58.577727 ==
2765 00:22:58.577792 Dram Type= 6, Freq= 0, CH_0, rank 0
2766 00:22:58.577849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2767 00:22:58.577901 ==
2768 00:22:58.577953 RX Vref Scan: 1
2769 00:22:58.578005
2770 00:22:58.578056 Set Vref Range= 32 -> 127
2771 00:22:58.578107
2772 00:22:58.578159 RX Vref 32 -> 127, step: 1
2773 00:22:58.578251
2774 00:22:58.578313 RX Delay -21 -> 252, step: 4
2775 00:22:58.578371
2776 00:22:58.578423 Set Vref, RX VrefLevel [Byte0]: 32
2777 00:22:58.578475 [Byte1]: 32
2778 00:22:58.578527
2779 00:22:58.578578 Set Vref, RX VrefLevel [Byte0]: 33
2780 00:22:58.578630 [Byte1]: 33
2781 00:22:58.578681
2782 00:22:58.578732 Set Vref, RX VrefLevel [Byte0]: 34
2783 00:22:58.578784 [Byte1]: 34
2784 00:22:58.578849
2785 00:22:58.578904 Set Vref, RX VrefLevel [Byte0]: 35
2786 00:22:58.578956 [Byte1]: 35
2787 00:22:58.579008
2788 00:22:58.579058 Set Vref, RX VrefLevel [Byte0]: 36
2789 00:22:58.579110 [Byte1]: 36
2790 00:22:58.579161
2791 00:22:58.579212 Set Vref, RX VrefLevel [Byte0]: 37
2792 00:22:58.579264 [Byte1]: 37
2793 00:22:58.579315
2794 00:22:58.579386 Set Vref, RX VrefLevel [Byte0]: 38
2795 00:22:58.579440 [Byte1]: 38
2796 00:22:58.579493
2797 00:22:58.579544 Set Vref, RX VrefLevel [Byte0]: 39
2798 00:22:58.579595 [Byte1]: 39
2799 00:22:58.579647
2800 00:22:58.579697 Set Vref, RX VrefLevel [Byte0]: 40
2801 00:22:58.579748 [Byte1]: 40
2802 00:22:58.579800
2803 00:22:58.579851 Set Vref, RX VrefLevel [Byte0]: 41
2804 00:22:58.579923 [Byte1]: 41
2805 00:22:58.579976
2806 00:22:58.580028 Set Vref, RX VrefLevel [Byte0]: 42
2807 00:22:58.580080 [Byte1]: 42
2808 00:22:58.580132
2809 00:22:58.580183 Set Vref, RX VrefLevel [Byte0]: 43
2810 00:22:58.580435 [Byte1]: 43
2811 00:22:58.580495
2812 00:22:58.580548 Set Vref, RX VrefLevel [Byte0]: 44
2813 00:22:58.580601 [Byte1]: 44
2814 00:22:58.580653
2815 00:22:58.580705 Set Vref, RX VrefLevel [Byte0]: 45
2816 00:22:58.580757 [Byte1]: 45
2817 00:22:58.580808
2818 00:22:58.580860 Set Vref, RX VrefLevel [Byte0]: 46
2819 00:22:58.580911 [Byte1]: 46
2820 00:22:58.580984
2821 00:22:58.581037 Set Vref, RX VrefLevel [Byte0]: 47
2822 00:22:58.581089 [Byte1]: 47
2823 00:22:58.581140
2824 00:22:58.581192 Set Vref, RX VrefLevel [Byte0]: 48
2825 00:22:58.581244 [Byte1]: 48
2826 00:22:58.581295
2827 00:22:58.581346 Set Vref, RX VrefLevel [Byte0]: 49
2828 00:22:58.581398 [Byte1]: 49
2829 00:22:58.581451
2830 00:22:58.581517 Set Vref, RX VrefLevel [Byte0]: 50
2831 00:22:58.581570 [Byte1]: 50
2832 00:22:58.581621
2833 00:22:58.581672 Set Vref, RX VrefLevel [Byte0]: 51
2834 00:22:58.581724 [Byte1]: 51
2835 00:22:58.581775
2836 00:22:58.581826 Set Vref, RX VrefLevel [Byte0]: 52
2837 00:22:58.581877 [Byte1]: 52
2838 00:22:58.581928
2839 00:22:58.581993 Set Vref, RX VrefLevel [Byte0]: 53
2840 00:22:58.582077 [Byte1]: 53
2841 00:22:58.582157
2842 00:22:58.582279 Set Vref, RX VrefLevel [Byte0]: 54
2843 00:22:58.582361 [Byte1]: 54
2844 00:22:58.582441
2845 00:22:58.582532 Set Vref, RX VrefLevel [Byte0]: 55
2846 00:22:58.582614 [Byte1]: 55
2847 00:22:58.582694
2848 00:22:58.582774 Set Vref, RX VrefLevel [Byte0]: 56
2849 00:22:58.582855 [Byte1]: 56
2850 00:22:58.582935
2851 00:22:58.583023 Set Vref, RX VrefLevel [Byte0]: 57
2852 00:22:58.583081 [Byte1]: 57
2853 00:22:58.583134
2854 00:22:58.583185 Set Vref, RX VrefLevel [Byte0]: 58
2855 00:22:58.583237 [Byte1]: 58
2856 00:22:58.583288
2857 00:22:58.583339 Set Vref, RX VrefLevel [Byte0]: 59
2858 00:22:58.583391 [Byte1]: 59
2859 00:22:58.583442
2860 00:22:58.583493 Set Vref, RX VrefLevel [Byte0]: 60
2861 00:22:58.583569 [Byte1]: 60
2862 00:22:58.583624
2863 00:22:58.583676 Set Vref, RX VrefLevel [Byte0]: 61
2864 00:22:58.583727 [Byte1]: 61
2865 00:22:58.583779
2866 00:22:58.583830 Set Vref, RX VrefLevel [Byte0]: 62
2867 00:22:58.583882 [Byte1]: 62
2868 00:22:58.583933
2869 00:22:58.583984 Set Vref, RX VrefLevel [Byte0]: 63
2870 00:22:58.584036 [Byte1]: 63
2871 00:22:58.584093
2872 00:22:58.584145 Set Vref, RX VrefLevel [Byte0]: 64
2873 00:22:58.584196 [Byte1]: 64
2874 00:22:58.584247
2875 00:22:58.584299 Set Vref, RX VrefLevel [Byte0]: 65
2876 00:22:58.584350 [Byte1]: 65
2877 00:22:58.584401
2878 00:22:58.584452 Set Vref, RX VrefLevel [Byte0]: 66
2879 00:22:58.584504 [Byte1]: 66
2880 00:22:58.584555
2881 00:22:58.584606 Set Vref, RX VrefLevel [Byte0]: 67
2882 00:22:58.584663 [Byte1]: 67
2883 00:22:58.584716
2884 00:22:58.584767 Set Vref, RX VrefLevel [Byte0]: 68
2885 00:22:58.584819 [Byte1]: 68
2886 00:22:58.584870
2887 00:22:58.584921 Set Vref, RX VrefLevel [Byte0]: 69
2888 00:22:58.584973 [Byte1]: 69
2889 00:22:58.585024
2890 00:22:58.585075 Set Vref, RX VrefLevel [Byte0]: 70
2891 00:22:58.585126 [Byte1]: 70
2892 00:22:58.585177
2893 00:22:58.585235 Set Vref, RX VrefLevel [Byte0]: 71
2894 00:22:58.585288 [Byte1]: 71
2895 00:22:58.585339
2896 00:22:58.585390 Set Vref, RX VrefLevel [Byte0]: 72
2897 00:22:58.585442 [Byte1]: 72
2898 00:22:58.585493
2899 00:22:58.585544 Set Vref, RX VrefLevel [Byte0]: 73
2900 00:22:58.585595 [Byte1]: 73
2901 00:22:58.585646
2902 00:22:58.585697 Set Vref, RX VrefLevel [Byte0]: 74
2903 00:22:58.585748 [Byte1]: 74
2904 00:22:58.585807
2905 00:22:58.585859 Set Vref, RX VrefLevel [Byte0]: 75
2906 00:22:58.585912 [Byte1]: 75
2907 00:22:58.585963
2908 00:22:58.586015 Set Vref, RX VrefLevel [Byte0]: 76
2909 00:22:58.586066 [Byte1]: 76
2910 00:22:58.586117
2911 00:22:58.586197 Final RX Vref Byte 0 = 61 to rank0
2912 00:22:58.586265 Final RX Vref Byte 1 = 49 to rank0
2913 00:22:58.586317 Final RX Vref Byte 0 = 61 to rank1
2914 00:22:58.586375 Final RX Vref Byte 1 = 49 to rank1==
2915 00:22:58.586429 Dram Type= 6, Freq= 0, CH_0, rank 0
2916 00:22:58.586480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2917 00:22:58.586533 ==
2918 00:22:58.586585 DQS Delay:
2919 00:22:58.586637 DQS0 = 0, DQS1 = 0
2920 00:22:58.586688 DQM Delay:
2921 00:22:58.586740 DQM0 = 119, DQM1 = 106
2922 00:22:58.586792 DQ Delay:
2923 00:22:58.586844 DQ0 =116, DQ1 =120, DQ2 =116, DQ3 =116
2924 00:22:58.586895 DQ4 =120, DQ5 =114, DQ6 =124, DQ7 =126
2925 00:22:58.586981 DQ8 =96, DQ9 =92, DQ10 =108, DQ11 =100
2926 00:22:58.587061 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =114
2927 00:22:58.587116
2928 00:22:58.587168
2929 00:22:58.587220 [DQSOSCAuto] RK0, (LSB)MR18= 0x12fd, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 403 ps
2930 00:22:58.587273 CH0 RK0: MR19=403, MR18=12FD
2931 00:22:58.587325 CH0_RK0: MR19=0x403, MR18=0x12FD, DQSOSC=403, MR23=63, INC=40, DEC=26
2932 00:22:58.587377
2933 00:22:58.587428 ----->DramcWriteLeveling(PI) begin...
2934 00:22:58.587486 ==
2935 00:22:58.587539 Dram Type= 6, Freq= 0, CH_0, rank 1
2936 00:22:58.587591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2937 00:22:58.587644 ==
2938 00:22:58.587696 Write leveling (Byte 0): 32 => 32
2939 00:22:58.587748 Write leveling (Byte 1): 30 => 30
2940 00:22:58.587799 DramcWriteLeveling(PI) end<-----
2941 00:22:58.587851
2942 00:22:58.587902 ==
2943 00:22:58.587954 Dram Type= 6, Freq= 0, CH_0, rank 1
2944 00:22:58.588005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2945 00:22:58.588064 ==
2946 00:22:58.588117 [Gating] SW mode calibration
2947 00:22:58.588168 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2948 00:22:58.588220 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2949 00:22:58.588272 0 15 0 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
2950 00:22:58.588323 0 15 4 | B1->B0 | 3130 3434 | 1 1 | (0 0) (1 1)
2951 00:22:58.588375 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2952 00:22:58.588426 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2953 00:22:58.588479 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2954 00:22:58.588530 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2955 00:22:58.588581 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2956 00:22:58.588831 0 15 28 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2957 00:22:58.588894 1 0 0 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
2958 00:22:58.588947 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2959 00:22:58.589000 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2960 00:22:58.589052 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2961 00:22:58.589104 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2962 00:22:58.589155 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2963 00:22:58.589214 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2964 00:22:58.589266 1 0 28 | B1->B0 | 2525 3636 | 1 0 | (0 0) (0 0)
2965 00:22:58.589318 1 1 0 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
2966 00:22:58.589369 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2967 00:22:58.589421 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2968 00:22:58.589472 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2969 00:22:58.589524 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2970 00:22:58.589576 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2971 00:22:58.589628 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2972 00:22:58.589680 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2973 00:22:58.589736 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2974 00:22:58.589788 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2975 00:22:58.589839 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2976 00:22:58.589891 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2977 00:22:58.589943 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2978 00:22:58.589994 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2979 00:22:58.590046 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2980 00:22:58.590097 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2981 00:22:58.590148 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2982 00:22:58.590247 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2983 00:22:58.590299 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2984 00:22:58.590358 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2985 00:22:58.590410 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2986 00:22:58.590462 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2987 00:22:58.590513 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2988 00:22:58.590565 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2989 00:22:58.590616 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2990 00:22:58.590667 Total UI for P1: 0, mck2ui 16
2991 00:22:58.590719 best dqsien dly found for B0: ( 1, 3, 28)
2992 00:22:58.590771 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2993 00:22:58.590823 Total UI for P1: 0, mck2ui 16
2994 00:22:58.590875 best dqsien dly found for B1: ( 1, 4, 0)
2995 00:22:58.590933 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2996 00:22:58.590985 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2997 00:22:58.591037
2998 00:22:58.591088 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2999 00:22:58.591140 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
3000 00:22:58.591191 [Gating] SW calibration Done
3001 00:22:58.591243 ==
3002 00:22:58.591294 Dram Type= 6, Freq= 0, CH_0, rank 1
3003 00:22:58.591346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3004 00:22:58.591399 ==
3005 00:22:58.591450 RX Vref Scan: 0
3006 00:22:58.591507
3007 00:22:58.799758 RX Vref 0 -> 0, step: 1
3008 00:22:58.800258
3009 00:22:58.800612 RX Delay -40 -> 252, step: 8
3010 00:22:58.800943 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
3011 00:22:58.801431 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
3012 00:22:58.801806 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
3013 00:22:58.802102 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3014 00:22:58.802463 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3015 00:22:58.802754 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
3016 00:22:58.803070 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3017 00:22:58.803350 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
3018 00:22:58.803794 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3019 00:22:58.804286 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3020 00:22:58.804698 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3021 00:22:58.805190 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3022 00:22:58.805592 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3023 00:22:58.806101 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3024 00:22:58.806618 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3025 00:22:58.807124 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3026 00:22:58.807603 ==
3027 00:22:58.808133 Dram Type= 6, Freq= 0, CH_0, rank 1
3028 00:22:58.808633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3029 00:22:58.809081 ==
3030 00:22:58.809509 DQS Delay:
3031 00:22:58.809841 DQS0 = 0, DQS1 = 0
3032 00:22:58.810303 DQM Delay:
3033 00:22:58.810599 DQM0 = 116, DQM1 = 108
3034 00:22:58.810898 DQ Delay:
3035 00:22:58.811178 DQ0 =111, DQ1 =123, DQ2 =111, DQ3 =115
3036 00:22:58.811472 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
3037 00:22:58.811752 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
3038 00:22:58.812019 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =111
3039 00:22:58.812310
3040 00:22:58.812574
3041 00:22:58.812866 ==
3042 00:22:58.813222 Dram Type= 6, Freq= 0, CH_0, rank 1
3043 00:22:58.813628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3044 00:22:58.813924 ==
3045 00:22:58.814366
3046 00:22:58.814738
3047 00:22:58.815025 TX Vref Scan disable
3048 00:22:58.815392 == TX Byte 0 ==
3049 00:22:58.815594 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3050 00:22:58.815837 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3051 00:22:58.816045 == TX Byte 1 ==
3052 00:22:58.816240 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3053 00:22:58.816524 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3054 00:22:58.816736 ==
3055 00:22:58.816981 Dram Type= 6, Freq= 0, CH_0, rank 1
3056 00:22:58.817289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3057 00:22:58.817618 ==
3058 00:22:58.817828 TX Vref=22, minBit 5, minWin=25, winSum=419
3059 00:22:58.818024 TX Vref=24, minBit 1, minWin=26, winSum=426
3060 00:22:58.818340 TX Vref=26, minBit 1, minWin=26, winSum=430
3061 00:22:58.818539 TX Vref=28, minBit 3, minWin=26, winSum=431
3062 00:22:58.818807 TX Vref=30, minBit 10, minWin=26, winSum=433
3063 00:22:58.819012 TX Vref=32, minBit 1, minWin=26, winSum=430
3064 00:22:58.819538 [TxChooseVref] Worse bit 10, Min win 26, Win sum 433, Final Vref 30
3065 00:22:58.819767
3066 00:22:58.820029 Final TX Range 1 Vref 30
3067 00:22:58.820231
3068 00:22:58.820461 ==
3069 00:22:58.820616 Dram Type= 6, Freq= 0, CH_0, rank 1
3070 00:22:58.820761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3071 00:22:58.820906 ==
3072 00:22:58.821148
3073 00:22:58.821371
3074 00:22:58.821612 TX Vref Scan disable
3075 00:22:58.821767 == TX Byte 0 ==
3076 00:22:58.821914 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3077 00:22:58.822073 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3078 00:22:58.822292 == TX Byte 1 ==
3079 00:22:58.822442 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3080 00:22:58.822588 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3081 00:22:58.822789
3082 00:22:58.822938 [DATLAT]
3083 00:22:58.823083 Freq=1200, CH0 RK1
3084 00:22:58.823283
3085 00:22:58.823432 DATLAT Default: 0xd
3086 00:22:58.823578 0, 0xFFFF, sum = 0
3087 00:22:58.823743 1, 0xFFFF, sum = 0
3088 00:22:58.823923 2, 0xFFFF, sum = 0
3089 00:22:58.824071 3, 0xFFFF, sum = 0
3090 00:22:58.824217 4, 0xFFFF, sum = 0
3091 00:22:58.824420 5, 0xFFFF, sum = 0
3092 00:22:58.824573 6, 0xFFFF, sum = 0
3093 00:22:58.824721 7, 0xFFFF, sum = 0
3094 00:22:58.824903 8, 0xFFFF, sum = 0
3095 00:22:58.825061 9, 0xFFFF, sum = 0
3096 00:22:58.825207 10, 0xFFFF, sum = 0
3097 00:22:58.825363 11, 0xFFFF, sum = 0
3098 00:22:58.825527 12, 0x0, sum = 1
3099 00:22:58.825650 13, 0x0, sum = 2
3100 00:22:58.825769 14, 0x0, sum = 3
3101 00:22:58.825885 15, 0x0, sum = 4
3102 00:22:58.826036 best_step = 13
3103 00:22:58.826220
3104 00:22:58.826340 ==
3105 00:22:58.826457 Dram Type= 6, Freq= 0, CH_0, rank 1
3106 00:22:58.826655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3107 00:22:58.826823 ==
3108 00:22:58.826945 RX Vref Scan: 0
3109 00:22:58.827093
3110 00:22:58.827217 RX Vref 0 -> 0, step: 1
3111 00:22:58.827334
3112 00:22:58.827449 RX Delay -21 -> 252, step: 4
3113 00:22:58.827567 iDelay=199, Bit 0, Center 114 (47 ~ 182) 136
3114 00:22:58.827730 iDelay=199, Bit 1, Center 118 (47 ~ 190) 144
3115 00:22:58.827851 iDelay=199, Bit 2, Center 110 (43 ~ 178) 136
3116 00:22:58.827969 iDelay=199, Bit 3, Center 114 (43 ~ 186) 144
3117 00:22:58.828086 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3118 00:22:58.828237 iDelay=199, Bit 5, Center 110 (43 ~ 178) 136
3119 00:22:58.828361 iDelay=199, Bit 6, Center 126 (55 ~ 198) 144
3120 00:22:58.828478 iDelay=199, Bit 7, Center 124 (55 ~ 194) 140
3121 00:22:58.828595 iDelay=199, Bit 8, Center 96 (27 ~ 166) 140
3122 00:22:58.828719 iDelay=199, Bit 9, Center 94 (27 ~ 162) 136
3123 00:22:58.828868 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3124 00:22:58.828985 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3125 00:22:58.829103 iDelay=199, Bit 12, Center 112 (47 ~ 178) 132
3126 00:22:58.829218 iDelay=199, Bit 13, Center 114 (47 ~ 182) 136
3127 00:22:58.829381 iDelay=199, Bit 14, Center 118 (55 ~ 182) 128
3128 00:22:58.829502 iDelay=199, Bit 15, Center 116 (51 ~ 182) 132
3129 00:22:58.829619 ==
3130 00:22:58.829736 Dram Type= 6, Freq= 0, CH_0, rank 1
3131 00:22:58.829888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3132 00:22:58.830075 ==
3133 00:22:58.830249 DQS Delay:
3134 00:22:58.830416 DQS0 = 0, DQS1 = 0
3135 00:22:58.830524 DQM Delay:
3136 00:22:58.830623 DQM0 = 116, DQM1 = 107
3137 00:22:58.830721 DQ Delay:
3138 00:22:58.830818 DQ0 =114, DQ1 =118, DQ2 =110, DQ3 =114
3139 00:22:58.830928 DQ4 =116, DQ5 =110, DQ6 =126, DQ7 =124
3140 00:22:58.831046 DQ8 =96, DQ9 =94, DQ10 =110, DQ11 =100
3141 00:22:58.831145 DQ12 =112, DQ13 =114, DQ14 =118, DQ15 =116
3142 00:22:58.831242
3143 00:22:58.831338
3144 00:22:58.831434 [DQSOSCAuto] RK1, (LSB)MR18= 0xfe9, (MSB)MR19= 0x403, tDQSOscB0 = 419 ps tDQSOscB1 = 404 ps
3145 00:22:58.831573 CH0 RK1: MR19=403, MR18=FE9
3146 00:22:58.831675 CH0_RK1: MR19=0x403, MR18=0xFE9, DQSOSC=404, MR23=63, INC=40, DEC=26
3147 00:22:58.831774 [RxdqsGatingPostProcess] freq 1200
3148 00:22:58.831871 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3149 00:22:58.831969 best DQS0 dly(2T, 0.5T) = (0, 11)
3150 00:22:58.832105 best DQS1 dly(2T, 0.5T) = (0, 12)
3151 00:22:58.832206 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3152 00:22:58.832305 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3153 00:22:58.832403 best DQS0 dly(2T, 0.5T) = (0, 11)
3154 00:22:58.832499 best DQS1 dly(2T, 0.5T) = (0, 12)
3155 00:22:58.832635 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3156 00:22:58.832735 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3157 00:22:58.832832 Pre-setting of DQS Precalculation
3158 00:22:58.832930 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3159 00:22:58.833029 ==
3160 00:22:58.833167 Dram Type= 6, Freq= 0, CH_1, rank 0
3161 00:22:58.833268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3162 00:22:58.833366 ==
3163 00:22:58.833458 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3164 00:22:58.833511 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3165 00:22:58.833564 [CA 0] Center 37 (7~67) winsize 61
3166 00:22:58.833667 [CA 1] Center 37 (7~68) winsize 62
3167 00:22:58.833739 [CA 2] Center 34 (4~64) winsize 61
3168 00:22:58.833792 [CA 3] Center 33 (3~64) winsize 62
3169 00:22:58.833857 [CA 4] Center 34 (4~64) winsize 61
3170 00:22:58.833910 [CA 5] Center 33 (3~64) winsize 62
3171 00:22:58.833962
3172 00:22:58.834014 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3173 00:22:58.834067
3174 00:22:58.834121 [CATrainingPosCal] consider 1 rank data
3175 00:22:58.834252 u2DelayCellTimex100 = 270/100 ps
3176 00:22:58.834320 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3177 00:22:58.834373 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3178 00:22:58.834425 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3179 00:22:58.834477 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3180 00:22:58.834530 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3181 00:22:58.834581 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3182 00:22:58.834639
3183 00:22:58.834702 CA PerBit enable=1, Macro0, CA PI delay=33
3184 00:22:58.834755
3185 00:22:58.834806 [CBTSetCACLKResult] CA Dly = 33
3186 00:22:58.834858 CS Dly: 5 (0~36)
3187 00:22:58.834910 ==
3188 00:22:58.834962 Dram Type= 6, Freq= 0, CH_1, rank 1
3189 00:22:58.835014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3190 00:22:58.835066 ==
3191 00:22:58.835118 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3192 00:22:58.835184 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3193 00:22:58.835241 [CA 0] Center 37 (7~68) winsize 62
3194 00:22:58.835293 [CA 1] Center 37 (7~68) winsize 62
3195 00:22:58.835345 [CA 2] Center 34 (3~65) winsize 63
3196 00:22:58.835397 [CA 3] Center 33 (3~64) winsize 62
3197 00:22:58.835449 [CA 4] Center 34 (3~65) winsize 63
3198 00:22:58.835721 [CA 5] Center 33 (3~64) winsize 62
3199 00:22:58.835827
3200 00:22:58.835928 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3201 00:22:58.835982
3202 00:22:58.836049 [CATrainingPosCal] consider 2 rank data
3203 00:22:58.836119 u2DelayCellTimex100 = 270/100 ps
3204 00:22:58.836204 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3205 00:22:58.836276 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3206 00:22:58.836331 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3207 00:22:58.836385 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3208 00:22:58.836438 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3209 00:22:58.836490 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3210 00:22:58.836543
3211 00:22:58.836609 CA PerBit enable=1, Macro0, CA PI delay=33
3212 00:22:58.836662
3213 00:22:58.836714 [CBTSetCACLKResult] CA Dly = 33
3214 00:22:58.836787 CS Dly: 7 (0~40)
3215 00:22:58.836840
3216 00:22:58.836893 ----->DramcWriteLeveling(PI) begin...
3217 00:22:58.836968 ==
3218 00:22:58.837053 Dram Type= 6, Freq= 0, CH_1, rank 0
3219 00:22:58.837107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3220 00:22:58.837161 ==
3221 00:22:58.837226 Write leveling (Byte 0): 23 => 23
3222 00:22:58.837300 Write leveling (Byte 1): 27 => 27
3223 00:22:58.837355 DramcWriteLeveling(PI) end<-----
3224 00:22:58.837407
3225 00:22:58.837459 ==
3226 00:22:58.837512 Dram Type= 6, Freq= 0, CH_1, rank 0
3227 00:22:58.837564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3228 00:22:58.837617 ==
3229 00:22:58.837669 [Gating] SW mode calibration
3230 00:22:58.837721 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3231 00:22:58.837779 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3232 00:22:58.837846 0 15 0 | B1->B0 | 3131 3434 | 1 1 | (0 0) (1 1)
3233 00:22:58.837899 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3234 00:22:58.837952 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3235 00:22:58.838005 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3236 00:22:58.838057 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3237 00:22:58.838109 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3238 00:22:58.838185 0 15 24 | B1->B0 | 3434 2f2f | 0 0 | (0 0) (0 1)
3239 00:22:58.838253 0 15 28 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
3240 00:22:58.838319 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3241 00:22:58.838375 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3242 00:22:58.838429 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3243 00:22:58.838481 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3244 00:22:58.838533 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3245 00:22:58.838585 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3246 00:22:58.838637 1 0 24 | B1->B0 | 2424 3939 | 0 1 | (0 0) (0 0)
3247 00:22:58.838689 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3248 00:22:58.838741 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3249 00:22:58.838793 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3250 00:22:58.838865 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3251 00:22:58.838919 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3252 00:22:58.838972 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3253 00:22:58.839025 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3254 00:22:58.839077 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3255 00:22:58.839129 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3256 00:22:58.839181 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3257 00:22:58.839233 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3258 00:22:58.839285 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3259 00:22:58.839337 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3260 00:22:58.839410 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3261 00:22:58.839463 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3262 00:22:58.839516 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3263 00:22:58.839568 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3264 00:22:58.839620 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3265 00:22:58.839672 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3266 00:22:58.839723 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3267 00:22:58.839776 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3268 00:22:58.839827 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3269 00:22:58.839892 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3270 00:22:58.839949 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3271 00:22:58.840001 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3272 00:22:58.840053 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3273 00:22:58.840104 Total UI for P1: 0, mck2ui 16
3274 00:22:58.840157 best dqsien dly found for B0: ( 1, 3, 26)
3275 00:22:58.840210 Total UI for P1: 0, mck2ui 16
3276 00:22:58.840262 best dqsien dly found for B1: ( 1, 3, 26)
3277 00:22:58.840314 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3278 00:22:58.840366 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3279 00:22:58.840439
3280 00:22:58.840493 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3281 00:22:58.840544 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3282 00:22:58.840597 [Gating] SW calibration Done
3283 00:22:58.840649 ==
3284 00:22:58.840701 Dram Type= 6, Freq= 0, CH_1, rank 0
3285 00:22:58.840754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3286 00:22:58.840806 ==
3287 00:22:58.840859 RX Vref Scan: 0
3288 00:22:58.840925
3289 00:22:58.840980 RX Vref 0 -> 0, step: 1
3290 00:22:58.841032
3291 00:22:58.841083 RX Delay -40 -> 252, step: 8
3292 00:22:58.841135 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3293 00:22:58.841187 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3294 00:22:58.841239 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3295 00:22:58.841291 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3296 00:22:58.841343 iDelay=208, Bit 4, Center 115 (48 ~ 183) 136
3297 00:22:58.841395 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3298 00:22:58.841468 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3299 00:22:58.841522 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3300 00:22:58.841575 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3301 00:22:58.841627 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3302 00:22:58.841877 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3303 00:22:58.841938 iDelay=208, Bit 11, Center 95 (24 ~ 167) 144
3304 00:22:58.842038 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3305 00:22:58.842122 iDelay=208, Bit 13, Center 115 (40 ~ 191) 152
3306 00:22:58.842229 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3307 00:22:58.842283 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3308 00:22:58.842336 ==
3309 00:22:58.842389 Dram Type= 6, Freq= 0, CH_1, rank 0
3310 00:22:58.842441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3311 00:22:58.842498 ==
3312 00:22:58.842564 DQS Delay:
3313 00:22:58.842674 DQS0 = 0, DQS1 = 0
3314 00:22:58.842741 DQM Delay:
3315 00:22:58.842793 DQM0 = 118, DQM1 = 108
3316 00:22:58.842845 DQ Delay:
3317 00:22:58.842897 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =115
3318 00:22:58.842949 DQ4 =115, DQ5 =131, DQ6 =123, DQ7 =115
3319 00:22:58.843000 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =95
3320 00:22:58.843073 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =119
3321 00:22:58.843127
3322 00:22:58.843179
3323 00:22:58.843230 ==
3324 00:22:58.843283 Dram Type= 6, Freq= 0, CH_1, rank 0
3325 00:22:58.843335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3326 00:22:58.843388 ==
3327 00:22:58.843440
3328 00:22:58.843491
3329 00:22:58.843554 TX Vref Scan disable
3330 00:22:58.843611 == TX Byte 0 ==
3331 00:22:58.843664 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3332 00:22:58.843716 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3333 00:22:58.843769 == TX Byte 1 ==
3334 00:22:58.843821 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3335 00:22:58.843873 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3336 00:22:58.843926 ==
3337 00:22:58.843978 Dram Type= 6, Freq= 0, CH_1, rank 0
3338 00:22:58.844029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3339 00:22:58.844089 ==
3340 00:22:58.844151 TX Vref=22, minBit 10, minWin=24, winSum=414
3341 00:22:58.844205 TX Vref=24, minBit 11, minWin=24, winSum=420
3342 00:22:58.844258 TX Vref=26, minBit 8, minWin=25, winSum=423
3343 00:22:58.844311 TX Vref=28, minBit 8, minWin=26, winSum=429
3344 00:22:58.844364 TX Vref=30, minBit 9, minWin=25, winSum=429
3345 00:22:58.844416 TX Vref=32, minBit 9, minWin=25, winSum=423
3346 00:22:58.844468 [TxChooseVref] Worse bit 8, Min win 26, Win sum 429, Final Vref 28
3347 00:22:58.844520
3348 00:22:58.844572 Final TX Range 1 Vref 28
3349 00:22:58.844646
3350 00:22:58.844724 ==
3351 00:22:58.844790 Dram Type= 6, Freq= 0, CH_1, rank 0
3352 00:22:58.844843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3353 00:22:58.844896 ==
3354 00:22:58.844947
3355 00:22:58.844998
3356 00:22:58.845050 TX Vref Scan disable
3357 00:22:58.845108 == TX Byte 0 ==
3358 00:22:58.845171 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3359 00:22:58.845224 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3360 00:22:58.845276 == TX Byte 1 ==
3361 00:22:58.845328 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3362 00:22:58.845380 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3363 00:22:58.845433
3364 00:22:58.845484 [DATLAT]
3365 00:22:58.845535 Freq=1200, CH1 RK0
3366 00:22:58.845586
3367 00:22:58.845647 DATLAT Default: 0xd
3368 00:22:58.845705 0, 0xFFFF, sum = 0
3369 00:22:58.845759 1, 0xFFFF, sum = 0
3370 00:22:58.845811 2, 0xFFFF, sum = 0
3371 00:22:58.845863 3, 0xFFFF, sum = 0
3372 00:22:58.845915 4, 0xFFFF, sum = 0
3373 00:22:58.845968 5, 0xFFFF, sum = 0
3374 00:22:58.846020 6, 0xFFFF, sum = 0
3375 00:22:58.846072 7, 0xFFFF, sum = 0
3376 00:22:58.846124 8, 0xFFFF, sum = 0
3377 00:22:58.846200 9, 0xFFFF, sum = 0
3378 00:22:58.846300 10, 0xFFFF, sum = 0
3379 00:22:58.846396 11, 0xFFFF, sum = 0
3380 00:22:58.846448 12, 0x0, sum = 1
3381 00:22:58.846500 13, 0x0, sum = 2
3382 00:22:58.846553 14, 0x0, sum = 3
3383 00:22:58.846606 15, 0x0, sum = 4
3384 00:22:58.846658 best_step = 13
3385 00:22:58.846729
3386 00:22:58.846805 ==
3387 00:22:58.846873 Dram Type= 6, Freq= 0, CH_1, rank 0
3388 00:22:58.846944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3389 00:22:58.846998 ==
3390 00:22:58.847051 RX Vref Scan: 1
3391 00:22:58.847103
3392 00:22:58.847155 Set Vref Range= 32 -> 127
3393 00:22:58.847239
3394 00:22:58.847330 RX Vref 32 -> 127, step: 1
3395 00:22:58.847416
3396 00:22:58.847505 RX Delay -21 -> 252, step: 4
3397 00:22:58.847587
3398 00:22:58.847668 Set Vref, RX VrefLevel [Byte0]: 32
3399 00:22:58.847749 [Byte1]: 32
3400 00:22:58.847840
3401 00:22:58.847921 Set Vref, RX VrefLevel [Byte0]: 33
3402 00:22:58.848003 [Byte1]: 33
3403 00:22:58.848083
3404 00:22:58.848163 Set Vref, RX VrefLevel [Byte0]: 34
3405 00:22:58.848244 [Byte1]: 34
3406 00:22:58.848330
3407 00:22:58.848384 Set Vref, RX VrefLevel [Byte0]: 35
3408 00:22:58.848437 [Byte1]: 35
3409 00:22:58.848489
3410 00:22:58.848540 Set Vref, RX VrefLevel [Byte0]: 36
3411 00:22:58.848592 [Byte1]: 36
3412 00:22:58.848643
3413 00:22:58.848695 Set Vref, RX VrefLevel [Byte0]: 37
3414 00:22:58.848746 [Byte1]: 37
3415 00:22:58.848797
3416 00:22:58.848870 Set Vref, RX VrefLevel [Byte0]: 38
3417 00:22:58.848925 [Byte1]: 38
3418 00:22:58.848977
3419 00:22:58.849027 Set Vref, RX VrefLevel [Byte0]: 39
3420 00:22:58.849079 [Byte1]: 39
3421 00:22:58.849130
3422 00:22:58.849181 Set Vref, RX VrefLevel [Byte0]: 40
3423 00:22:58.849234 [Byte1]: 40
3424 00:22:58.849330
3425 00:22:58.849414 Set Vref, RX VrefLevel [Byte0]: 41
3426 00:22:58.849467 [Byte1]: 41
3427 00:22:58.849519
3428 00:22:58.849570 Set Vref, RX VrefLevel [Byte0]: 42
3429 00:22:58.849621 [Byte1]: 42
3430 00:22:58.849672
3431 00:22:58.849723 Set Vref, RX VrefLevel [Byte0]: 43
3432 00:22:58.849819 [Byte1]: 43
3433 00:22:58.849897
3434 00:22:58.849953 Set Vref, RX VrefLevel [Byte0]: 44
3435 00:22:58.850005 [Byte1]: 44
3436 00:22:58.850056
3437 00:22:58.850107 Set Vref, RX VrefLevel [Byte0]: 45
3438 00:22:58.850158 [Byte1]: 45
3439 00:22:58.850247
3440 00:22:58.850298 Set Vref, RX VrefLevel [Byte0]: 46
3441 00:22:58.850349 [Byte1]: 46
3442 00:22:58.850414
3443 00:22:58.850469 Set Vref, RX VrefLevel [Byte0]: 47
3444 00:22:58.850521 [Byte1]: 47
3445 00:22:58.850572
3446 00:22:58.850624 Set Vref, RX VrefLevel [Byte0]: 48
3447 00:22:58.850675 [Byte1]: 48
3448 00:22:58.850728
3449 00:22:58.850779 Set Vref, RX VrefLevel [Byte0]: 49
3450 00:22:58.850831 [Byte1]: 49
3451 00:22:58.850881
3452 00:22:58.850932 Set Vref, RX VrefLevel [Byte0]: 50
3453 00:22:58.850984 [Byte1]: 50
3454 00:22:58.851036
3455 00:22:58.851086 Set Vref, RX VrefLevel [Byte0]: 51
3456 00:22:58.851138 [Byte1]: 51
3457 00:22:58.851189
3458 00:22:58.851240 Set Vref, RX VrefLevel [Byte0]: 52
3459 00:22:58.851312 [Byte1]: 52
3460 00:22:58.851365
3461 00:22:58.851421 Set Vref, RX VrefLevel [Byte0]: 53
3462 00:22:58.851574 [Byte1]: 53
3463 00:22:58.851689
3464 00:22:58.851773 Set Vref, RX VrefLevel [Byte0]: 54
3465 00:22:58.851888 [Byte1]: 54
3466 00:22:58.851944
3467 00:22:58.852197 Set Vref, RX VrefLevel [Byte0]: 55
3468 00:22:58.852257 [Byte1]: 55
3469 00:22:58.852311
3470 00:22:58.852384 Set Vref, RX VrefLevel [Byte0]: 56
3471 00:22:58.852440 [Byte1]: 56
3472 00:22:58.852492
3473 00:22:58.852544 Set Vref, RX VrefLevel [Byte0]: 57
3474 00:22:58.852597 [Byte1]: 57
3475 00:22:58.852648
3476 00:22:58.852699 Set Vref, RX VrefLevel [Byte0]: 58
3477 00:22:58.852751 [Byte1]: 58
3478 00:22:58.852802
3479 00:22:58.852877 Set Vref, RX VrefLevel [Byte0]: 59
3480 00:22:58.852953 [Byte1]: 59
3481 00:22:58.853006
3482 00:22:58.853057 Set Vref, RX VrefLevel [Byte0]: 60
3483 00:22:58.853109 [Byte1]: 60
3484 00:22:58.853161
3485 00:22:58.853212 Set Vref, RX VrefLevel [Byte0]: 61
3486 00:22:58.853263 [Byte1]: 61
3487 00:22:58.853314
3488 00:22:58.853365 Set Vref, RX VrefLevel [Byte0]: 62
3489 00:22:58.853432 [Byte1]: 62
3490 00:22:58.853488
3491 00:22:58.853539 Set Vref, RX VrefLevel [Byte0]: 63
3492 00:22:58.853591 [Byte1]: 63
3493 00:22:58.853643
3494 00:22:58.853694 Set Vref, RX VrefLevel [Byte0]: 64
3495 00:22:58.853745 [Byte1]: 64
3496 00:22:58.853805
3497 00:22:58.853892 Set Vref, RX VrefLevel [Byte0]: 65
3498 00:22:58.853997 [Byte1]: 65
3499 00:22:58.854080
3500 00:22:58.854193 Set Vref, RX VrefLevel [Byte0]: 66
3501 00:22:58.854264 [Byte1]: 66
3502 00:22:58.854317
3503 00:22:58.854369 Set Vref, RX VrefLevel [Byte0]: 67
3504 00:22:58.854421 [Byte1]: 67
3505 00:22:58.854487
3506 00:22:58.854541 Set Vref, RX VrefLevel [Byte0]: 68
3507 00:22:58.854594 [Byte1]: 68
3508 00:22:58.854646
3509 00:22:58.854697 Final RX Vref Byte 0 = 48 to rank0
3510 00:22:58.854749 Final RX Vref Byte 1 = 54 to rank0
3511 00:22:58.854802 Final RX Vref Byte 0 = 48 to rank1
3512 00:22:58.854853 Final RX Vref Byte 1 = 54 to rank1==
3513 00:22:58.854905 Dram Type= 6, Freq= 0, CH_1, rank 0
3514 00:22:58.854962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3515 00:22:58.855037 ==
3516 00:22:58.855091 DQS Delay:
3517 00:22:58.855143 DQS0 = 0, DQS1 = 0
3518 00:22:58.855195 DQM Delay:
3519 00:22:58.855247 DQM0 = 116, DQM1 = 110
3520 00:22:58.855299 DQ Delay:
3521 00:22:58.855351 DQ0 =118, DQ1 =110, DQ2 =108, DQ3 =112
3522 00:22:58.855403 DQ4 =114, DQ5 =126, DQ6 =126, DQ7 =114
3523 00:22:58.855454 DQ8 =98, DQ9 =102, DQ10 =112, DQ11 =100
3524 00:22:58.855510 DQ12 =118, DQ13 =118, DQ14 =120, DQ15 =118
3525 00:22:58.855575
3526 00:22:58.855627
3527 00:22:58.855678 [DQSOSCAuto] RK0, (LSB)MR18= 0x4f7, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 408 ps
3528 00:22:58.855732 CH1 RK0: MR19=403, MR18=4F7
3529 00:22:58.855799 CH1_RK0: MR19=0x403, MR18=0x4F7, DQSOSC=408, MR23=63, INC=39, DEC=26
3530 00:22:58.855852
3531 00:22:58.855905 ----->DramcWriteLeveling(PI) begin...
3532 00:22:58.855959 ==
3533 00:22:58.856011 Dram Type= 6, Freq= 0, CH_1, rank 1
3534 00:22:58.856085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3535 00:22:58.856140 ==
3536 00:22:58.856193 Write leveling (Byte 0): 26 => 26
3537 00:22:58.856246 Write leveling (Byte 1): 27 => 27
3538 00:22:58.856299 DramcWriteLeveling(PI) end<-----
3539 00:22:58.856351
3540 00:22:58.856403 ==
3541 00:22:58.856455 Dram Type= 6, Freq= 0, CH_1, rank 1
3542 00:22:58.856507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3543 00:22:58.856574 ==
3544 00:22:58.856630 [Gating] SW mode calibration
3545 00:22:58.856683 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3546 00:22:58.856736 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3547 00:22:58.856789 0 15 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3548 00:22:58.856842 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3549 00:22:58.856895 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3550 00:22:58.856948 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3551 00:22:58.857000 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3552 00:22:58.857053 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3553 00:22:58.857120 0 15 24 | B1->B0 | 3232 3434 | 0 0 | (0 1) (0 0)
3554 00:22:58.857176 0 15 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 0)
3555 00:22:58.857229 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3556 00:22:58.857282 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3557 00:22:58.857335 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3558 00:22:58.857387 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3559 00:22:58.857440 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3560 00:22:58.857492 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3561 00:22:58.857544 1 0 24 | B1->B0 | 403f 2b2b | 1 0 | (0 0) (0 0)
3562 00:22:58.857597 1 0 28 | B1->B0 | 4646 4545 | 0 1 | (0 0) (0 0)
3563 00:22:58.857692 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3564 00:22:58.857776 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3565 00:22:58.857859 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3566 00:22:58.857942 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3567 00:22:58.858036 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3568 00:22:58.858125 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3569 00:22:58.858205 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3570 00:22:58.858261 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3571 00:22:58.858314 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3572 00:22:58.858368 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3573 00:22:58.858421 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3574 00:22:58.858474 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3575 00:22:58.858526 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3576 00:22:58.858579 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3577 00:22:58.858636 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3578 00:22:58.858703 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3579 00:22:58.858757 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3580 00:22:58.858810 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3581 00:22:58.858863 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3582 00:22:58.858916 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3583 00:22:58.859174 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3584 00:22:58.859235 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3585 00:22:58.859297 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3586 00:22:58.859352 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3587 00:22:58.859507 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3588 00:22:58.859628 Total UI for P1: 0, mck2ui 16
3589 00:22:58.859713 best dqsien dly found for B0: ( 1, 3, 26)
3590 00:22:58.859771 Total UI for P1: 0, mck2ui 16
3591 00:22:58.859825 best dqsien dly found for B1: ( 1, 3, 26)
3592 00:22:58.859879 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3593 00:22:58.859934 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3594 00:22:58.859987
3595 00:22:58.860040 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3596 00:22:58.860094 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3597 00:22:58.860147 [Gating] SW calibration Done
3598 00:22:58.860204 ==
3599 00:22:58.860258 Dram Type= 6, Freq= 0, CH_1, rank 1
3600 00:22:58.860311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3601 00:22:58.860364 ==
3602 00:22:58.860417 RX Vref Scan: 0
3603 00:22:58.860471
3604 00:22:58.860523 RX Vref 0 -> 0, step: 1
3605 00:22:58.860576
3606 00:22:58.860627 RX Delay -40 -> 252, step: 8
3607 00:22:58.860680 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3608 00:22:58.860733 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3609 00:22:58.860790 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3610 00:22:58.860843 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3611 00:22:58.860895 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3612 00:22:58.860947 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3613 00:22:58.861000 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3614 00:22:58.861052 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3615 00:22:58.861104 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3616 00:22:58.861157 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3617 00:22:58.861209 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3618 00:22:58.861261 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
3619 00:22:58.861317 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3620 00:22:58.861371 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3621 00:22:58.861424 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3622 00:22:58.861476 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3623 00:22:58.861528 ==
3624 00:22:58.861580 Dram Type= 6, Freq= 0, CH_1, rank 1
3625 00:22:58.861633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3626 00:22:58.861686 ==
3627 00:22:58.861739 DQS Delay:
3628 00:22:58.861790 DQS0 = 0, DQS1 = 0
3629 00:22:58.861843 DQM Delay:
3630 00:22:58.861926 DQM0 = 116, DQM1 = 110
3631 00:22:58.862008 DQ Delay:
3632 00:22:58.862090 DQ0 =119, DQ1 =111, DQ2 =107, DQ3 =111
3633 00:22:58.862181 DQ4 =115, DQ5 =123, DQ6 =127, DQ7 =115
3634 00:22:58.862239 DQ8 =95, DQ9 =103, DQ10 =111, DQ11 =99
3635 00:22:58.862293 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3636 00:22:58.862345
3637 00:22:58.862398
3638 00:22:58.862456 ==
3639 00:22:58.862510 Dram Type= 6, Freq= 0, CH_1, rank 1
3640 00:22:58.862562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3641 00:22:58.862615 ==
3642 00:22:58.862668
3643 00:22:58.862721
3644 00:22:58.862773 TX Vref Scan disable
3645 00:22:58.862825 == TX Byte 0 ==
3646 00:22:58.862878 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3647 00:22:58.862930 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3648 00:22:58.862988 == TX Byte 1 ==
3649 00:22:58.863041 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3650 00:22:58.863100 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3651 00:22:58.863153 ==
3652 00:22:58.863206 Dram Type= 6, Freq= 0, CH_1, rank 1
3653 00:22:58.863258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3654 00:22:58.863312 ==
3655 00:22:58.863364 TX Vref=22, minBit 9, minWin=25, winSum=419
3656 00:22:58.863418 TX Vref=24, minBit 2, minWin=26, winSum=425
3657 00:22:58.863470 TX Vref=26, minBit 9, minWin=26, winSum=430
3658 00:22:58.863527 TX Vref=28, minBit 9, minWin=26, winSum=430
3659 00:22:58.863581 TX Vref=30, minBit 9, minWin=26, winSum=429
3660 00:22:58.863634 TX Vref=32, minBit 8, minWin=26, winSum=428
3661 00:22:58.863687 [TxChooseVref] Worse bit 9, Min win 26, Win sum 430, Final Vref 26
3662 00:22:58.863740
3663 00:22:58.863792 Final TX Range 1 Vref 26
3664 00:22:58.863845
3665 00:22:58.863897 ==
3666 00:22:58.863954 Dram Type= 6, Freq= 0, CH_1, rank 1
3667 00:22:58.864007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3668 00:22:58.864059 ==
3669 00:22:58.864119
3670 00:22:58.864171
3671 00:22:58.864223 TX Vref Scan disable
3672 00:22:58.864275 == TX Byte 0 ==
3673 00:22:58.864328 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3674 00:22:58.864380 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3675 00:22:58.864433 == TX Byte 1 ==
3676 00:22:58.864485 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3677 00:22:58.864537 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3678 00:22:58.864589
3679 00:22:58.864650 [DATLAT]
3680 00:22:58.864733 Freq=1200, CH1 RK1
3681 00:22:58.864815
3682 00:22:58.864896 DATLAT Default: 0xd
3683 00:22:58.864981 0, 0xFFFF, sum = 0
3684 00:22:58.865065 1, 0xFFFF, sum = 0
3685 00:22:58.865150 2, 0xFFFF, sum = 0
3686 00:22:58.865223 3, 0xFFFF, sum = 0
3687 00:22:58.865278 4, 0xFFFF, sum = 0
3688 00:22:58.865332 5, 0xFFFF, sum = 0
3689 00:22:58.865384 6, 0xFFFF, sum = 0
3690 00:22:58.865438 7, 0xFFFF, sum = 0
3691 00:22:58.865491 8, 0xFFFF, sum = 0
3692 00:22:58.865544 9, 0xFFFF, sum = 0
3693 00:22:58.865598 10, 0xFFFF, sum = 0
3694 00:22:58.865651 11, 0xFFFF, sum = 0
3695 00:22:58.865705 12, 0x0, sum = 1
3696 00:22:58.865761 13, 0x0, sum = 2
3697 00:22:58.865843 14, 0x0, sum = 3
3698 00:22:58.865946 15, 0x0, sum = 4
3699 00:22:58.866035 best_step = 13
3700 00:22:58.866126
3701 00:22:58.866225 ==
3702 00:22:58.866315 Dram Type= 6, Freq= 0, CH_1, rank 1
3703 00:22:58.866402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3704 00:22:58.866485 ==
3705 00:22:58.866568 RX Vref Scan: 0
3706 00:22:58.866650
3707 00:22:58.866732 RX Vref 0 -> 0, step: 1
3708 00:22:58.866814
3709 00:22:58.866899 RX Delay -21 -> 252, step: 4
3710 00:22:58.866982 iDelay=199, Bit 0, Center 120 (55 ~ 186) 132
3711 00:22:58.867065 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3712 00:22:58.867148 iDelay=199, Bit 2, Center 106 (43 ~ 170) 128
3713 00:22:58.867231 iDelay=199, Bit 3, Center 114 (51 ~ 178) 128
3714 00:22:58.867313 iDelay=199, Bit 4, Center 114 (47 ~ 182) 136
3715 00:22:58.867384 iDelay=199, Bit 5, Center 126 (59 ~ 194) 136
3716 00:22:58.867439 iDelay=199, Bit 6, Center 130 (63 ~ 198) 136
3717 00:22:58.867525 iDelay=199, Bit 7, Center 116 (51 ~ 182) 132
3718 00:22:58.867607 iDelay=199, Bit 8, Center 98 (31 ~ 166) 136
3719 00:22:58.867690 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3720 00:22:58.867773 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3721 00:22:58.868053 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3722 00:22:58.868116 iDelay=199, Bit 12, Center 118 (51 ~ 186) 136
3723 00:22:58.868172 iDelay=199, Bit 13, Center 118 (51 ~ 186) 136
3724 00:22:58.868225 iDelay=199, Bit 14, Center 118 (51 ~ 186) 136
3725 00:22:58.868278 iDelay=199, Bit 15, Center 118 (51 ~ 186) 136
3726 00:22:58.868332 ==
3727 00:22:58.868404 Dram Type= 6, Freq= 0, CH_1, rank 1
3728 00:22:58.868487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3729 00:22:58.868570 ==
3730 00:22:58.868652 DQS Delay:
3731 00:22:58.868734 DQS0 = 0, DQS1 = 0
3732 00:22:58.868816 DQM Delay:
3733 00:22:58.868899 DQM0 = 117, DQM1 = 110
3734 00:22:58.868993 DQ Delay:
3735 00:22:58.869077 DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =114
3736 00:22:58.869160 DQ4 =114, DQ5 =126, DQ6 =130, DQ7 =116
3737 00:22:58.869243 DQ8 =98, DQ9 =100, DQ10 =110, DQ11 =100
3738 00:22:58.869325 DQ12 =118, DQ13 =118, DQ14 =118, DQ15 =118
3739 00:22:58.869407
3740 00:22:58.869495
3741 00:22:58.869551 [DQSOSCAuto] RK1, (LSB)MR18= 0xf6f1, (MSB)MR19= 0x303, tDQSOscB0 = 416 ps tDQSOscB1 = 414 ps
3742 00:22:58.869606 CH1 RK1: MR19=303, MR18=F6F1
3743 00:22:58.869660 CH1_RK1: MR19=0x303, MR18=0xF6F1, DQSOSC=414, MR23=63, INC=38, DEC=25
3744 00:22:58.869713 [RxdqsGatingPostProcess] freq 1200
3745 00:22:58.869766 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3746 00:22:58.869819 best DQS0 dly(2T, 0.5T) = (0, 11)
3747 00:22:58.869872 best DQS1 dly(2T, 0.5T) = (0, 11)
3748 00:22:58.869924 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3749 00:22:58.869991 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3750 00:22:58.870077 best DQS0 dly(2T, 0.5T) = (0, 11)
3751 00:22:58.870171 best DQS1 dly(2T, 0.5T) = (0, 11)
3752 00:22:58.870229 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3753 00:22:58.870283 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3754 00:22:58.870336 Pre-setting of DQS Precalculation
3755 00:22:58.870389 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3756 00:22:58.870442 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3757 00:22:58.870510 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3758 00:22:58.870567
3759 00:22:58.870620
3760 00:22:58.870672 [Calibration Summary] 2400 Mbps
3761 00:22:58.870737 CH 0, Rank 0
3762 00:22:58.870897 SW Impedance : PASS
3763 00:22:58.871002 DUTY Scan : NO K
3764 00:22:58.871074 ZQ Calibration : PASS
3765 00:22:58.871132 Jitter Meter : NO K
3766 00:22:58.871186 CBT Training : PASS
3767 00:22:58.871240 Write leveling : PASS
3768 00:22:58.871293 RX DQS gating : PASS
3769 00:22:58.871346 RX DQ/DQS(RDDQC) : PASS
3770 00:22:58.871399 TX DQ/DQS : PASS
3771 00:22:58.871451 RX DATLAT : PASS
3772 00:22:58.871504 RX DQ/DQS(Engine): PASS
3773 00:22:58.871577 TX OE : NO K
3774 00:22:58.871633 All Pass.
3775 00:22:58.871687
3776 00:22:58.871740 CH 0, Rank 1
3777 00:22:58.871793 SW Impedance : PASS
3778 00:22:58.871846 DUTY Scan : NO K
3779 00:22:58.871898 ZQ Calibration : PASS
3780 00:22:58.871951 Jitter Meter : NO K
3781 00:22:58.872003 CBT Training : PASS
3782 00:22:58.872063 Write leveling : PASS
3783 00:22:58.872126 RX DQS gating : PASS
3784 00:22:58.872179 RX DQ/DQS(RDDQC) : PASS
3785 00:22:58.872232 TX DQ/DQS : PASS
3786 00:22:58.872284 RX DATLAT : PASS
3787 00:22:58.872336 RX DQ/DQS(Engine): PASS
3788 00:22:58.872388 TX OE : NO K
3789 00:22:58.872441 All Pass.
3790 00:22:58.872493
3791 00:22:58.872545 CH 1, Rank 0
3792 00:22:58.872601 SW Impedance : PASS
3793 00:22:58.872667 DUTY Scan : NO K
3794 00:22:58.872721 ZQ Calibration : PASS
3795 00:22:58.872773 Jitter Meter : NO K
3796 00:22:58.872826 CBT Training : PASS
3797 00:22:58.872878 Write leveling : PASS
3798 00:22:58.872931 RX DQS gating : PASS
3799 00:22:58.872983 RX DQ/DQS(RDDQC) : PASS
3800 00:22:58.873035 TX DQ/DQS : PASS
3801 00:22:58.873088 RX DATLAT : PASS
3802 00:22:58.873168 RX DQ/DQS(Engine): PASS
3803 00:22:58.873234 TX OE : NO K
3804 00:22:58.873288 All Pass.
3805 00:22:58.873341
3806 00:22:58.873393 CH 1, Rank 1
3807 00:22:58.873446 SW Impedance : PASS
3808 00:22:58.873509 DUTY Scan : NO K
3809 00:22:58.873682 ZQ Calibration : PASS
3810 00:22:58.873789 Jitter Meter : NO K
3811 00:22:58.873880 CBT Training : PASS
3812 00:22:58.873966 Write leveling : PASS
3813 00:22:58.874051 RX DQS gating : PASS
3814 00:22:58.874134 RX DQ/DQS(RDDQC) : PASS
3815 00:22:58.874211 TX DQ/DQS : PASS
3816 00:22:58.874267 RX DATLAT : PASS
3817 00:22:58.874321 RX DQ/DQS(Engine): PASS
3818 00:22:58.874373 TX OE : NO K
3819 00:22:58.874426 All Pass.
3820 00:22:58.874478
3821 00:22:58.874530 DramC Write-DBI off
3822 00:22:58.874583 PER_BANK_REFRESH: Hybrid Mode
3823 00:22:58.874636 TX_TRACKING: ON
3824 00:22:58.874689 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3825 00:22:58.874750 [FAST_K] Save calibration result to emmc
3826 00:22:58.874804 dramc_set_vcore_voltage set vcore to 650000
3827 00:22:58.874857 Read voltage for 600, 5
3828 00:22:58.874910 Vio18 = 0
3829 00:22:58.874962 Vcore = 650000
3830 00:22:58.875015 Vdram = 0
3831 00:22:58.875067 Vddq = 0
3832 00:22:58.875119 Vmddr = 0
3833 00:22:58.875172 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3834 00:22:58.875225 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3835 00:22:58.875284 MEM_TYPE=3, freq_sel=19
3836 00:22:58.875338 sv_algorithm_assistance_LP4_1600
3837 00:22:58.875390 ============ PULL DRAM RESETB DOWN ============
3838 00:22:58.875453 ========== PULL DRAM RESETB DOWN end =========
3839 00:22:58.875507 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3840 00:22:58.875561 ===================================
3841 00:22:58.875614 LPDDR4 DRAM CONFIGURATION
3842 00:22:58.875667 ===================================
3843 00:22:58.875720 EX_ROW_EN[0] = 0x0
3844 00:22:58.875773 EX_ROW_EN[1] = 0x0
3845 00:22:58.875832 LP4Y_EN = 0x0
3846 00:22:58.875887 WORK_FSP = 0x0
3847 00:22:58.875940 WL = 0x2
3848 00:22:58.875993 RL = 0x2
3849 00:22:58.876045 BL = 0x2
3850 00:22:58.876098 RPST = 0x0
3851 00:22:58.876151 RD_PRE = 0x0
3852 00:22:58.876203 WR_PRE = 0x1
3853 00:22:58.876256 WR_PST = 0x0
3854 00:22:58.876308 DBI_WR = 0x0
3855 00:22:58.876364 DBI_RD = 0x0
3856 00:22:58.876417 OTF = 0x1
3857 00:22:58.876471 ===================================
3858 00:22:58.876523 ===================================
3859 00:22:58.876576 ANA top config
3860 00:22:58.876628 ===================================
3861 00:22:58.876680 DLL_ASYNC_EN = 0
3862 00:22:58.876733 ALL_SLAVE_EN = 1
3863 00:22:58.876786 NEW_RANK_MODE = 1
3864 00:22:58.876839 DLL_IDLE_MODE = 1
3865 00:22:58.876892 LP45_APHY_COMB_EN = 1
3866 00:22:58.877160 TX_ODT_DIS = 1
3867 00:22:58.877249 NEW_8X_MODE = 1
3868 00:22:58.877334 ===================================
3869 00:22:58.877418 ===================================
3870 00:22:58.877493 data_rate = 1200
3871 00:22:58.877549 CKR = 1
3872 00:22:58.877602 DQ_P2S_RATIO = 8
3873 00:22:58.877656 ===================================
3874 00:22:58.877709 CA_P2S_RATIO = 8
3875 00:22:58.877761 DQ_CA_OPEN = 0
3876 00:22:58.877814 DQ_SEMI_OPEN = 0
3877 00:22:58.877867 CA_SEMI_OPEN = 0
3878 00:22:58.877919 CA_FULL_RATE = 0
3879 00:22:58.877971 DQ_CKDIV4_EN = 1
3880 00:22:58.878028 CA_CKDIV4_EN = 1
3881 00:22:58.878112 CA_PREDIV_EN = 0
3882 00:22:58.878197 PH8_DLY = 0
3883 00:22:58.878252 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3884 00:22:58.878305 DQ_AAMCK_DIV = 4
3885 00:22:58.878358 CA_AAMCK_DIV = 4
3886 00:22:58.878410 CA_ADMCK_DIV = 4
3887 00:22:58.878463 DQ_TRACK_CA_EN = 0
3888 00:22:58.878516 CA_PICK = 600
3889 00:22:58.878573 CA_MCKIO = 600
3890 00:22:58.878628 MCKIO_SEMI = 0
3891 00:22:58.878681 PLL_FREQ = 2288
3892 00:22:58.878733 DQ_UI_PI_RATIO = 32
3893 00:22:58.878786 CA_UI_PI_RATIO = 0
3894 00:22:58.878839 ===================================
3895 00:22:58.878891 ===================================
3896 00:22:58.878944 memory_type:LPDDR4
3897 00:22:58.878997 GP_NUM : 10
3898 00:22:58.879049 SRAM_EN : 1
3899 00:22:58.879101 MD32_EN : 0
3900 00:22:58.879160 ===================================
3901 00:22:58.879214 [ANA_INIT] >>>>>>>>>>>>>>
3902 00:22:58.879266 <<<<<< [CONFIGURE PHASE]: ANA_TX
3903 00:22:58.879320 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3904 00:22:58.879373 ===================================
3905 00:22:58.879426 data_rate = 1200,PCW = 0X5800
3906 00:22:58.879479 ===================================
3907 00:22:58.879532 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3908 00:22:58.879584 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3909 00:22:58.879637 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3910 00:22:58.879690 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3911 00:22:58.879748 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3912 00:22:58.879802 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3913 00:22:58.879859 [ANA_INIT] flow start
3914 00:22:58.879911 [ANA_INIT] PLL >>>>>>>>
3915 00:22:58.879964 [ANA_INIT] PLL <<<<<<<<
3916 00:22:58.880017 [ANA_INIT] MIDPI >>>>>>>>
3917 00:22:58.880069 [ANA_INIT] MIDPI <<<<<<<<
3918 00:22:58.880121 [ANA_INIT] DLL >>>>>>>>
3919 00:22:58.880173 [ANA_INIT] flow end
3920 00:22:58.880330 ============ LP4 DIFF to SE enter ============
3921 00:22:58.880450 ============ LP4 DIFF to SE exit ============
3922 00:22:58.880533 [ANA_INIT] <<<<<<<<<<<<<
3923 00:22:58.880621 [Flow] Enable top DCM control >>>>>
3924 00:22:58.880706 [Flow] Enable top DCM control <<<<<
3925 00:22:58.880794 Enable DLL master slave shuffle
3926 00:22:58.880894 ==============================================================
3927 00:22:58.880981 Gating Mode config
3928 00:22:58.886005 ==============================================================
3929 00:22:58.888769 Config description:
3930 00:22:58.899119 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3931 00:22:58.905399 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3932 00:22:58.908979 SELPH_MODE 0: By rank 1: By Phase
3933 00:22:58.915435 ==============================================================
3934 00:22:58.918500 GAT_TRACK_EN = 1
3935 00:22:58.918592 RX_GATING_MODE = 2
3936 00:22:58.922177 RX_GATING_TRACK_MODE = 2
3937 00:22:58.925156 SELPH_MODE = 1
3938 00:22:58.928590 PICG_EARLY_EN = 1
3939 00:22:58.932198 VALID_LAT_VALUE = 1
3940 00:22:58.938292 ==============================================================
3941 00:22:58.941820 Enter into Gating configuration >>>>
3942 00:22:58.944835 Exit from Gating configuration <<<<
3943 00:22:58.948515 Enter into DVFS_PRE_config >>>>>
3944 00:22:58.958508 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3945 00:22:58.962048 Exit from DVFS_PRE_config <<<<<
3946 00:22:58.965029 Enter into PICG configuration >>>>
3947 00:22:58.968629 Exit from PICG configuration <<<<
3948 00:22:58.971519 [RX_INPUT] configuration >>>>>
3949 00:22:58.974968 [RX_INPUT] configuration <<<<<
3950 00:22:58.978193 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3951 00:22:58.984672 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3952 00:22:58.991225 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3953 00:22:58.998408 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3954 00:22:59.001414 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3955 00:22:59.007839 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3956 00:22:59.011034 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3957 00:22:59.017695 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3958 00:22:59.021087 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3959 00:22:59.024573 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3960 00:22:59.027729 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3961 00:22:59.034128 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3962 00:22:59.037753 ===================================
3963 00:22:59.040894 LPDDR4 DRAM CONFIGURATION
3964 00:22:59.043922 ===================================
3965 00:22:59.044031 EX_ROW_EN[0] = 0x0
3966 00:22:59.047549 EX_ROW_EN[1] = 0x0
3967 00:22:59.047622 LP4Y_EN = 0x0
3968 00:22:59.050454 WORK_FSP = 0x0
3969 00:22:59.050526 WL = 0x2
3970 00:22:59.054282 RL = 0x2
3971 00:22:59.054439 BL = 0x2
3972 00:22:59.057318 RPST = 0x0
3973 00:22:59.057386 RD_PRE = 0x0
3974 00:22:59.060817 WR_PRE = 0x1
3975 00:22:59.060913 WR_PST = 0x0
3976 00:22:59.063717 DBI_WR = 0x0
3977 00:22:59.066963 DBI_RD = 0x0
3978 00:22:59.067095 OTF = 0x1
3979 00:22:59.070471 ===================================
3980 00:22:59.073526 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3981 00:22:59.077136 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3982 00:22:59.083699 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3983 00:22:59.087052 ===================================
3984 00:22:59.090186 LPDDR4 DRAM CONFIGURATION
3985 00:22:59.093687 ===================================
3986 00:22:59.093761 EX_ROW_EN[0] = 0x10
3987 00:22:59.097110 EX_ROW_EN[1] = 0x0
3988 00:22:59.097184 LP4Y_EN = 0x0
3989 00:22:59.100055 WORK_FSP = 0x0
3990 00:22:59.100131 WL = 0x2
3991 00:22:59.103801 RL = 0x2
3992 00:22:59.103874 BL = 0x2
3993 00:22:59.106814 RPST = 0x0
3994 00:22:59.106916 RD_PRE = 0x0
3995 00:22:59.110165 WR_PRE = 0x1
3996 00:22:59.110253 WR_PST = 0x0
3997 00:22:59.113637 DBI_WR = 0x0
3998 00:22:59.116546 DBI_RD = 0x0
3999 00:22:59.116619 OTF = 0x1
4000 00:22:59.119840 ===================================
4001 00:22:59.126432 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4002 00:22:59.129899 nWR fixed to 30
4003 00:22:59.133261 [ModeRegInit_LP4] CH0 RK0
4004 00:22:59.133344 [ModeRegInit_LP4] CH0 RK1
4005 00:22:59.136651 [ModeRegInit_LP4] CH1 RK0
4006 00:22:59.140226 [ModeRegInit_LP4] CH1 RK1
4007 00:22:59.140308 match AC timing 17
4008 00:22:59.146458 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
4009 00:22:59.149888 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4010 00:22:59.153449 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
4011 00:22:59.160092 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
4012 00:22:59.163018 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
4013 00:22:59.163102 ==
4014 00:22:59.166780 Dram Type= 6, Freq= 0, CH_0, rank 0
4015 00:22:59.170134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4016 00:22:59.170240 ==
4017 00:22:59.176696 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4018 00:22:59.183420 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4019 00:22:59.186572 [CA 0] Center 36 (6~66) winsize 61
4020 00:22:59.189459 [CA 1] Center 36 (6~66) winsize 61
4021 00:22:59.193130 [CA 2] Center 34 (4~65) winsize 62
4022 00:22:59.196607 [CA 3] Center 34 (4~65) winsize 62
4023 00:22:59.199665 [CA 4] Center 33 (3~64) winsize 62
4024 00:22:59.202730 [CA 5] Center 33 (2~64) winsize 63
4025 00:22:59.202802
4026 00:22:59.206298 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4027 00:22:59.206373
4028 00:22:59.209598 [CATrainingPosCal] consider 1 rank data
4029 00:22:59.212714 u2DelayCellTimex100 = 270/100 ps
4030 00:22:59.216397 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4031 00:22:59.219414 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4032 00:22:59.222519 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4033 00:22:59.226274 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4034 00:22:59.232686 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4035 00:22:59.236101 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4036 00:22:59.236208
4037 00:22:59.239373 CA PerBit enable=1, Macro0, CA PI delay=33
4038 00:22:59.239449
4039 00:22:59.242704 [CBTSetCACLKResult] CA Dly = 33
4040 00:22:59.242779 CS Dly: 6 (0~37)
4041 00:22:59.242840 ==
4042 00:22:59.245694 Dram Type= 6, Freq= 0, CH_0, rank 1
4043 00:22:59.252552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4044 00:22:59.252643 ==
4045 00:22:59.255519 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4046 00:22:59.262425 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4047 00:22:59.265387 [CA 0] Center 35 (5~66) winsize 62
4048 00:22:59.269126 [CA 1] Center 36 (6~66) winsize 61
4049 00:22:59.272107 [CA 2] Center 33 (3~64) winsize 62
4050 00:22:59.275657 [CA 3] Center 33 (3~64) winsize 62
4051 00:22:59.278595 [CA 4] Center 33 (3~64) winsize 62
4052 00:22:59.281648 [CA 5] Center 33 (2~64) winsize 63
4053 00:22:59.281724
4054 00:22:59.285239 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4055 00:22:59.285327
4056 00:22:59.288300 [CATrainingPosCal] consider 2 rank data
4057 00:22:59.292188 u2DelayCellTimex100 = 270/100 ps
4058 00:22:59.298041 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4059 00:22:59.301922 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4060 00:22:59.305052 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4061 00:22:59.308205 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4062 00:22:59.311586 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4063 00:22:59.314664 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4064 00:22:59.314759
4065 00:22:59.318476 CA PerBit enable=1, Macro0, CA PI delay=33
4066 00:22:59.318559
4067 00:22:59.321538 [CBTSetCACLKResult] CA Dly = 33
4068 00:22:59.324989 CS Dly: 6 (0~37)
4069 00:22:59.325071
4070 00:22:59.328239 ----->DramcWriteLeveling(PI) begin...
4071 00:22:59.328334 ==
4072 00:22:59.331708 Dram Type= 6, Freq= 0, CH_0, rank 0
4073 00:22:59.334862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4074 00:22:59.334958 ==
4075 00:22:59.337887 Write leveling (Byte 0): 32 => 32
4076 00:22:59.341196 Write leveling (Byte 1): 31 => 31
4077 00:22:59.344867 DramcWriteLeveling(PI) end<-----
4078 00:22:59.345072
4079 00:22:59.345233 ==
4080 00:22:59.347918 Dram Type= 6, Freq= 0, CH_0, rank 0
4081 00:22:59.351461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4082 00:22:59.351690 ==
4083 00:22:59.354349 [Gating] SW mode calibration
4084 00:22:59.361130 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4085 00:22:59.368068 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4086 00:22:59.371069 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4087 00:22:59.374455 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4088 00:22:59.381085 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4089 00:22:59.384707 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (0 1)
4090 00:22:59.387541 0 9 16 | B1->B0 | 2f2f 2929 | 0 0 | (0 0) (0 0)
4091 00:22:59.394408 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4092 00:22:59.397335 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4093 00:22:59.400960 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4094 00:22:59.407738 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4095 00:22:59.410778 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4096 00:22:59.413754 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4097 00:22:59.420834 0 10 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4098 00:22:59.423616 0 10 16 | B1->B0 | 3636 4242 | 0 0 | (1 1) (0 0)
4099 00:22:59.427056 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4100 00:22:59.433817 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4101 00:22:59.437016 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4102 00:22:59.440042 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4103 00:22:59.446992 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4104 00:22:59.449914 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4105 00:22:59.453609 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4106 00:22:59.460269 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4107 00:22:59.463150 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4108 00:22:59.466765 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4109 00:22:59.473353 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4110 00:22:59.476384 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4111 00:22:59.479874 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4112 00:22:59.486393 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4113 00:22:59.489802 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4114 00:22:59.492874 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4115 00:22:59.499352 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4116 00:22:59.502957 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4117 00:22:59.506020 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4118 00:22:59.512560 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4119 00:22:59.516130 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4120 00:22:59.519298 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4121 00:22:59.525698 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4122 00:22:59.529291 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4123 00:22:59.532930 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4124 00:22:59.535906 Total UI for P1: 0, mck2ui 16
4125 00:22:59.539195 best dqsien dly found for B0: ( 0, 13, 14)
4126 00:22:59.542591 Total UI for P1: 0, mck2ui 16
4127 00:22:59.546215 best dqsien dly found for B1: ( 0, 13, 16)
4128 00:22:59.549090 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4129 00:22:59.552448 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4130 00:22:59.556203
4131 00:22:59.559100 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4132 00:22:59.562300 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4133 00:22:59.565685 [Gating] SW calibration Done
4134 00:22:59.565797 ==
4135 00:22:59.569441 Dram Type= 6, Freq= 0, CH_0, rank 0
4136 00:22:59.572387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4137 00:22:59.572511 ==
4138 00:22:59.572607 RX Vref Scan: 0
4139 00:22:59.575883
4140 00:22:59.576019 RX Vref 0 -> 0, step: 1
4141 00:22:59.576125
4142 00:22:59.579433 RX Delay -230 -> 252, step: 16
4143 00:22:59.582531 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4144 00:22:59.589294 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4145 00:22:59.592445 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4146 00:22:59.595508 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4147 00:22:59.599192 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4148 00:22:59.602217 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4149 00:22:59.609243 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4150 00:22:59.612497 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4151 00:22:59.615528 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4152 00:22:59.619443 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4153 00:22:59.625966 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4154 00:22:59.628770 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4155 00:22:59.632450 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4156 00:22:59.635567 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4157 00:22:59.642220 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4158 00:22:59.645377 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4159 00:22:59.645821 ==
4160 00:22:59.648895 Dram Type= 6, Freq= 0, CH_0, rank 0
4161 00:22:59.652043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4162 00:22:59.652471 ==
4163 00:22:59.655314 DQS Delay:
4164 00:22:59.655747 DQS0 = 0, DQS1 = 0
4165 00:22:59.656106 DQM Delay:
4166 00:22:59.658841 DQM0 = 41, DQM1 = 31
4167 00:22:59.659275 DQ Delay:
4168 00:22:59.661791 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4169 00:22:59.665364 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4170 00:22:59.669107 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4171 00:22:59.671683 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4172 00:22:59.672112
4173 00:22:59.672446
4174 00:22:59.672758 ==
4175 00:22:59.675318 Dram Type= 6, Freq= 0, CH_0, rank 0
4176 00:22:59.681836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4177 00:22:59.682322 ==
4178 00:22:59.682664
4179 00:22:59.682971
4180 00:22:59.684825 TX Vref Scan disable
4181 00:22:59.685251 == TX Byte 0 ==
4182 00:22:59.687967 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4183 00:22:59.695021 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4184 00:22:59.695538 == TX Byte 1 ==
4185 00:22:59.700999 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4186 00:22:59.704674 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4187 00:22:59.705098 ==
4188 00:22:59.707843 Dram Type= 6, Freq= 0, CH_0, rank 0
4189 00:22:59.711493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4190 00:22:59.711944 ==
4191 00:22:59.712363
4192 00:22:59.712685
4193 00:22:59.714511 TX Vref Scan disable
4194 00:22:59.717479 == TX Byte 0 ==
4195 00:22:59.721123 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4196 00:22:59.724440 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4197 00:22:59.727638 == TX Byte 1 ==
4198 00:22:59.730869 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4199 00:22:59.734159 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4200 00:22:59.734618
4201 00:22:59.737579 [DATLAT]
4202 00:22:59.738044 Freq=600, CH0 RK0
4203 00:22:59.738518
4204 00:22:59.740809 DATLAT Default: 0x9
4205 00:22:59.741246 0, 0xFFFF, sum = 0
4206 00:22:59.743835 1, 0xFFFF, sum = 0
4207 00:22:59.744288 2, 0xFFFF, sum = 0
4208 00:22:59.747511 3, 0xFFFF, sum = 0
4209 00:22:59.747963 4, 0xFFFF, sum = 0
4210 00:22:59.750559 5, 0xFFFF, sum = 0
4211 00:22:59.754116 6, 0xFFFF, sum = 0
4212 00:22:59.754592 7, 0xFFFF, sum = 0
4213 00:22:59.754953 8, 0x0, sum = 1
4214 00:22:59.757062 9, 0x0, sum = 2
4215 00:22:59.757492 10, 0x0, sum = 3
4216 00:22:59.760756 11, 0x0, sum = 4
4217 00:22:59.761262 best_step = 9
4218 00:22:59.761596
4219 00:22:59.761922 ==
4220 00:22:59.763594 Dram Type= 6, Freq= 0, CH_0, rank 0
4221 00:22:59.770419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4222 00:22:59.770868 ==
4223 00:22:59.771208 RX Vref Scan: 1
4224 00:22:59.771531
4225 00:22:59.773955 RX Vref 0 -> 0, step: 1
4226 00:22:59.774446
4227 00:22:59.776862 RX Delay -195 -> 252, step: 8
4228 00:22:59.777303
4229 00:22:59.780597 Set Vref, RX VrefLevel [Byte0]: 61
4230 00:22:59.783694 [Byte1]: 49
4231 00:22:59.784279
4232 00:22:59.787041 Final RX Vref Byte 0 = 61 to rank0
4233 00:22:59.790368 Final RX Vref Byte 1 = 49 to rank0
4234 00:22:59.793647 Final RX Vref Byte 0 = 61 to rank1
4235 00:22:59.796976 Final RX Vref Byte 1 = 49 to rank1==
4236 00:22:59.799979 Dram Type= 6, Freq= 0, CH_0, rank 0
4237 00:22:59.803760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4238 00:22:59.804205 ==
4239 00:22:59.806712 DQS Delay:
4240 00:22:59.807150 DQS0 = 0, DQS1 = 0
4241 00:22:59.809820 DQM Delay:
4242 00:22:59.810304 DQM0 = 44, DQM1 = 32
4243 00:22:59.810662 DQ Delay:
4244 00:22:59.813551 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4245 00:22:59.816419 DQ4 =44, DQ5 =36, DQ6 =52, DQ7 =52
4246 00:22:59.820196 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =24
4247 00:22:59.823149 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =40
4248 00:22:59.823586
4249 00:22:59.823922
4250 00:22:59.833134 [DQSOSCAuto] RK0, (LSB)MR18= 0x6c44, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 389 ps
4251 00:22:59.836665 CH0 RK0: MR19=808, MR18=6C44
4252 00:22:59.843275 CH0_RK0: MR19=0x808, MR18=0x6C44, DQSOSC=389, MR23=63, INC=173, DEC=115
4253 00:22:59.843718
4254 00:22:59.846654 ----->DramcWriteLeveling(PI) begin...
4255 00:22:59.847087 ==
4256 00:22:59.849506 Dram Type= 6, Freq= 0, CH_0, rank 1
4257 00:22:59.852878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4258 00:22:59.853320 ==
4259 00:22:59.856406 Write leveling (Byte 0): 34 => 34
4260 00:22:59.859417 Write leveling (Byte 1): 33 => 33
4261 00:22:59.862902 DramcWriteLeveling(PI) end<-----
4262 00:22:59.863326
4263 00:22:59.863680 ==
4264 00:22:59.866331 Dram Type= 6, Freq= 0, CH_0, rank 1
4265 00:22:59.869537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4266 00:22:59.870002 ==
4267 00:22:59.872770 [Gating] SW mode calibration
4268 00:22:59.879609 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4269 00:22:59.885739 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4270 00:22:59.889447 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4271 00:22:59.892633 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4272 00:22:59.899256 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4273 00:22:59.902524 0 9 12 | B1->B0 | 3333 3232 | 1 0 | (1 1) (0 0)
4274 00:22:59.906146 0 9 16 | B1->B0 | 2f2f 2a2a | 1 0 | (1 0) (0 0)
4275 00:22:59.912200 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4276 00:22:59.915863 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4277 00:22:59.918853 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4278 00:22:59.925565 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4279 00:22:59.929383 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4280 00:22:59.932222 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4281 00:22:59.938796 0 10 12 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
4282 00:22:59.942614 0 10 16 | B1->B0 | 3737 4242 | 0 0 | (0 0) (0 0)
4283 00:22:59.945534 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4284 00:22:59.952158 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4285 00:22:59.955884 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4286 00:22:59.958954 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4287 00:22:59.965682 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4288 00:22:59.968613 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4289 00:22:59.971781 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4290 00:22:59.978290 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4291 00:22:59.981751 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4292 00:22:59.985264 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4293 00:22:59.991430 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4294 00:22:59.994853 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4295 00:22:59.998599 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4296 00:23:00.004690 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4297 00:23:00.008549 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4298 00:23:00.011578 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4299 00:23:00.018027 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4300 00:23:00.021044 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4301 00:23:00.024672 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4302 00:23:00.031372 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4303 00:23:00.034326 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4304 00:23:00.037590 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4305 00:23:00.044427 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4306 00:23:00.047499 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4307 00:23:00.051220 Total UI for P1: 0, mck2ui 16
4308 00:23:00.054207 best dqsien dly found for B0: ( 0, 13, 12)
4309 00:23:00.057903 Total UI for P1: 0, mck2ui 16
4310 00:23:00.060844 best dqsien dly found for B1: ( 0, 13, 12)
4311 00:23:00.064000 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4312 00:23:00.067705 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4313 00:23:00.068150
4314 00:23:00.070756 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4315 00:23:00.077395 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4316 00:23:00.077840 [Gating] SW calibration Done
4317 00:23:00.078213 ==
4318 00:23:00.080488 Dram Type= 6, Freq= 0, CH_0, rank 1
4319 00:23:00.086990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4320 00:23:00.087444 ==
4321 00:23:00.087803 RX Vref Scan: 0
4322 00:23:00.088120
4323 00:23:00.090481 RX Vref 0 -> 0, step: 1
4324 00:23:00.091003
4325 00:23:00.094050 RX Delay -230 -> 252, step: 16
4326 00:23:00.096975 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4327 00:23:00.100380 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4328 00:23:00.106881 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4329 00:23:00.110243 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4330 00:23:00.113495 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4331 00:23:00.116896 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4332 00:23:00.119830 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4333 00:23:00.126624 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4334 00:23:00.129579 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4335 00:23:00.133335 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4336 00:23:00.136328 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4337 00:23:00.143171 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4338 00:23:00.146516 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4339 00:23:00.149479 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4340 00:23:00.153242 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4341 00:23:00.159274 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4342 00:23:00.159709 ==
4343 00:23:00.162885 Dram Type= 6, Freq= 0, CH_0, rank 1
4344 00:23:00.165853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4345 00:23:00.166375 ==
4346 00:23:00.166874 DQS Delay:
4347 00:23:00.169943 DQS0 = 0, DQS1 = 0
4348 00:23:00.170577 DQM Delay:
4349 00:23:00.172410 DQM0 = 44, DQM1 = 39
4350 00:23:00.172717 DQ Delay:
4351 00:23:00.175990 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =41
4352 00:23:00.179065 DQ4 =41, DQ5 =41, DQ6 =49, DQ7 =49
4353 00:23:00.182668 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =33
4354 00:23:00.185766 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =41
4355 00:23:00.186069
4356 00:23:00.186446
4357 00:23:00.186749 ==
4358 00:23:00.188889 Dram Type= 6, Freq= 0, CH_0, rank 1
4359 00:23:00.195934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4360 00:23:00.196207 ==
4361 00:23:00.196527
4362 00:23:00.196821
4363 00:23:00.197089 TX Vref Scan disable
4364 00:23:00.199291 == TX Byte 0 ==
4365 00:23:00.202348 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4366 00:23:00.208603 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4367 00:23:00.208910 == TX Byte 1 ==
4368 00:23:00.212267 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4369 00:23:00.218991 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4370 00:23:00.219244 ==
4371 00:23:00.222383 Dram Type= 6, Freq= 0, CH_0, rank 1
4372 00:23:00.225231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4373 00:23:00.225493 ==
4374 00:23:00.225766
4375 00:23:00.226023
4376 00:23:00.228620 TX Vref Scan disable
4377 00:23:00.231908 == TX Byte 0 ==
4378 00:23:00.235234 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4379 00:23:00.238381 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4380 00:23:00.241803 == TX Byte 1 ==
4381 00:23:00.244797 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4382 00:23:00.248479 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4383 00:23:00.248779
4384 00:23:00.249032 [DATLAT]
4385 00:23:00.251571 Freq=600, CH0 RK1
4386 00:23:00.251798
4387 00:23:00.254908 DATLAT Default: 0x9
4388 00:23:00.255134 0, 0xFFFF, sum = 0
4389 00:23:00.258546 1, 0xFFFF, sum = 0
4390 00:23:00.258942 2, 0xFFFF, sum = 0
4391 00:23:00.261450 3, 0xFFFF, sum = 0
4392 00:23:00.261694 4, 0xFFFF, sum = 0
4393 00:23:00.264640 5, 0xFFFF, sum = 0
4394 00:23:00.264948 6, 0xFFFF, sum = 0
4395 00:23:00.268510 7, 0xFFFF, sum = 0
4396 00:23:00.268818 8, 0x0, sum = 1
4397 00:23:00.271511 9, 0x0, sum = 2
4398 00:23:00.271739 10, 0x0, sum = 3
4399 00:23:00.275104 11, 0x0, sum = 4
4400 00:23:00.275338 best_step = 9
4401 00:23:00.275515
4402 00:23:00.275720 ==
4403 00:23:00.278111 Dram Type= 6, Freq= 0, CH_0, rank 1
4404 00:23:00.281866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4405 00:23:00.282192 ==
4406 00:23:00.284917 RX Vref Scan: 0
4407 00:23:00.285212
4408 00:23:00.288049 RX Vref 0 -> 0, step: 1
4409 00:23:00.288273
4410 00:23:00.288450 RX Delay -179 -> 252, step: 8
4411 00:23:00.295876 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4412 00:23:00.299333 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4413 00:23:00.303017 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4414 00:23:00.306004 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4415 00:23:00.312710 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4416 00:23:00.315779 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4417 00:23:00.319313 iDelay=205, Bit 6, Center 52 (-99 ~ 204) 304
4418 00:23:00.322356 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4419 00:23:00.329018 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4420 00:23:00.332420 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4421 00:23:00.335509 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4422 00:23:00.339319 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4423 00:23:00.345889 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4424 00:23:00.348914 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4425 00:23:00.352140 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4426 00:23:00.355685 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4427 00:23:00.356108 ==
4428 00:23:00.358504 Dram Type= 6, Freq= 0, CH_0, rank 1
4429 00:23:00.365364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4430 00:23:00.365798 ==
4431 00:23:00.366189 DQS Delay:
4432 00:23:00.368825 DQS0 = 0, DQS1 = 0
4433 00:23:00.369249 DQM Delay:
4434 00:23:00.369601 DQM0 = 42, DQM1 = 37
4435 00:23:00.371655 DQ Delay:
4436 00:23:00.374989 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =40
4437 00:23:00.378748 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =48
4438 00:23:00.381773 DQ8 =28, DQ9 =20, DQ10 =40, DQ11 =28
4439 00:23:00.384995 DQ12 =44, DQ13 =44, DQ14 =48, DQ15 =44
4440 00:23:00.385615
4441 00:23:00.386199
4442 00:23:00.391502 [DQSOSCAuto] RK1, (LSB)MR18= 0x6113, (MSB)MR19= 0x808, tDQSOscB0 = 406 ps tDQSOscB1 = 391 ps
4443 00:23:00.394698 CH0 RK1: MR19=808, MR18=6113
4444 00:23:00.401077 CH0_RK1: MR19=0x808, MR18=0x6113, DQSOSC=391, MR23=63, INC=171, DEC=114
4445 00:23:00.404652 [RxdqsGatingPostProcess] freq 600
4446 00:23:00.411269 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4447 00:23:00.411852 Pre-setting of DQS Precalculation
4448 00:23:00.417953 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4449 00:23:00.418520 ==
4450 00:23:00.421002 Dram Type= 6, Freq= 0, CH_1, rank 0
4451 00:23:00.424770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4452 00:23:00.425315 ==
4453 00:23:00.431402 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4454 00:23:00.437957 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4455 00:23:00.441051 [CA 0] Center 35 (5~66) winsize 62
4456 00:23:00.444167 [CA 1] Center 35 (5~66) winsize 62
4457 00:23:00.447564 [CA 2] Center 34 (4~65) winsize 62
4458 00:23:00.451038 [CA 3] Center 33 (3~64) winsize 62
4459 00:23:00.453922 [CA 4] Center 34 (4~65) winsize 62
4460 00:23:00.457496 [CA 5] Center 33 (3~64) winsize 62
4461 00:23:00.458080
4462 00:23:00.460810 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4463 00:23:00.461245
4464 00:23:00.464424 [CATrainingPosCal] consider 1 rank data
4465 00:23:00.467213 u2DelayCellTimex100 = 270/100 ps
4466 00:23:00.470673 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4467 00:23:00.473874 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4468 00:23:00.476967 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4469 00:23:00.480039 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4470 00:23:00.483583 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4471 00:23:00.490059 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4472 00:23:00.490200
4473 00:23:00.492961 CA PerBit enable=1, Macro0, CA PI delay=33
4474 00:23:00.493045
4475 00:23:00.496741 [CBTSetCACLKResult] CA Dly = 33
4476 00:23:00.496824 CS Dly: 5 (0~36)
4477 00:23:00.496895 ==
4478 00:23:00.499773 Dram Type= 6, Freq= 0, CH_1, rank 1
4479 00:23:00.506129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4480 00:23:00.506255 ==
4481 00:23:00.509618 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4482 00:23:00.515940 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4483 00:23:00.519626 [CA 0] Center 35 (5~66) winsize 62
4484 00:23:00.522625 [CA 1] Center 36 (6~66) winsize 61
4485 00:23:00.525745 [CA 2] Center 34 (4~65) winsize 62
4486 00:23:00.529383 [CA 3] Center 34 (3~65) winsize 63
4487 00:23:00.532382 [CA 4] Center 34 (4~65) winsize 62
4488 00:23:00.535962 [CA 5] Center 34 (3~65) winsize 63
4489 00:23:00.536045
4490 00:23:00.539146 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4491 00:23:00.539229
4492 00:23:00.542729 [CATrainingPosCal] consider 2 rank data
4493 00:23:00.545763 u2DelayCellTimex100 = 270/100 ps
4494 00:23:00.549479 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4495 00:23:00.555799 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4496 00:23:00.558787 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4497 00:23:00.562385 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4498 00:23:00.565353 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4499 00:23:00.568498 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4500 00:23:00.568590
4501 00:23:00.572119 CA PerBit enable=1, Macro0, CA PI delay=33
4502 00:23:00.572203
4503 00:23:00.575110 [CBTSetCACLKResult] CA Dly = 33
4504 00:23:00.578501 CS Dly: 5 (0~37)
4505 00:23:00.578584
4506 00:23:00.581744 ----->DramcWriteLeveling(PI) begin...
4507 00:23:00.581829 ==
4508 00:23:00.585123 Dram Type= 6, Freq= 0, CH_1, rank 0
4509 00:23:00.588178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4510 00:23:00.588294 ==
4511 00:23:00.591842 Write leveling (Byte 0): 30 => 30
4512 00:23:00.594767 Write leveling (Byte 1): 32 => 32
4513 00:23:00.598577 DramcWriteLeveling(PI) end<-----
4514 00:23:00.598660
4515 00:23:00.598725 ==
4516 00:23:00.601534 Dram Type= 6, Freq= 0, CH_1, rank 0
4517 00:23:00.605129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4518 00:23:00.605213 ==
4519 00:23:00.608170 [Gating] SW mode calibration
4520 00:23:00.614813 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4521 00:23:00.621885 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4522 00:23:00.624633 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4523 00:23:00.627827 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4524 00:23:00.634648 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4525 00:23:00.638206 0 9 12 | B1->B0 | 3131 2e2e | 1 1 | (1 1) (1 0)
4526 00:23:00.640929 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4527 00:23:00.648083 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4528 00:23:00.651115 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4529 00:23:00.654706 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4530 00:23:00.661169 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4531 00:23:00.664163 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4532 00:23:00.667254 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4533 00:23:00.674301 0 10 12 | B1->B0 | 3232 3838 | 0 0 | (0 0) (0 0)
4534 00:23:00.677390 0 10 16 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
4535 00:23:00.680546 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4536 00:23:00.687501 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4537 00:23:00.690773 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4538 00:23:00.693776 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4539 00:23:00.700527 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4540 00:23:00.704106 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4541 00:23:00.707182 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4542 00:23:00.713799 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4543 00:23:00.717036 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4544 00:23:00.719908 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4545 00:23:00.726598 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4546 00:23:00.730194 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4547 00:23:00.733170 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4548 00:23:00.740018 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4549 00:23:00.743452 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4550 00:23:00.746568 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4551 00:23:00.753556 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4552 00:23:00.756347 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4553 00:23:00.760256 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4554 00:23:00.766326 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4555 00:23:00.769960 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4556 00:23:00.773461 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4557 00:23:00.779419 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4558 00:23:00.782973 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4559 00:23:00.786109 Total UI for P1: 0, mck2ui 16
4560 00:23:00.789616 best dqsien dly found for B0: ( 0, 13, 12)
4561 00:23:00.792645 Total UI for P1: 0, mck2ui 16
4562 00:23:00.795982 best dqsien dly found for B1: ( 0, 13, 14)
4563 00:23:00.799175 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4564 00:23:00.802756 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4565 00:23:00.802839
4566 00:23:00.805760 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4567 00:23:00.812704 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4568 00:23:00.812786 [Gating] SW calibration Done
4569 00:23:00.812851 ==
4570 00:23:00.815693 Dram Type= 6, Freq= 0, CH_1, rank 0
4571 00:23:00.822477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4572 00:23:00.822562 ==
4573 00:23:00.822628 RX Vref Scan: 0
4574 00:23:00.822690
4575 00:23:00.825473 RX Vref 0 -> 0, step: 1
4576 00:23:00.825543
4577 00:23:00.829110 RX Delay -230 -> 252, step: 16
4578 00:23:00.832787 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4579 00:23:00.835729 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4580 00:23:00.841961 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4581 00:23:00.845517 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4582 00:23:00.848689 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4583 00:23:00.852125 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4584 00:23:00.858528 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4585 00:23:00.861916 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4586 00:23:00.865306 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4587 00:23:00.868273 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4588 00:23:00.871638 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4589 00:23:00.878643 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4590 00:23:00.881650 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4591 00:23:00.884575 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4592 00:23:00.888019 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4593 00:23:00.894945 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4594 00:23:00.895037 ==
4595 00:23:00.898108 Dram Type= 6, Freq= 0, CH_1, rank 0
4596 00:23:00.901651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4597 00:23:00.901755 ==
4598 00:23:00.901852 DQS Delay:
4599 00:23:00.904504 DQS0 = 0, DQS1 = 0
4600 00:23:00.904608 DQM Delay:
4601 00:23:00.908356 DQM0 = 47, DQM1 = 38
4602 00:23:00.908461 DQ Delay:
4603 00:23:00.911930 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =41
4604 00:23:00.914506 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4605 00:23:00.918144 DQ8 =17, DQ9 =25, DQ10 =41, DQ11 =25
4606 00:23:00.921151 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4607 00:23:00.921257
4608 00:23:00.921345
4609 00:23:00.921447 ==
4610 00:23:00.924602 Dram Type= 6, Freq= 0, CH_1, rank 0
4611 00:23:00.930763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4612 00:23:00.930900 ==
4613 00:23:00.931003
4614 00:23:00.931104
4615 00:23:00.931203 TX Vref Scan disable
4616 00:23:00.934579 == TX Byte 0 ==
4617 00:23:00.938003 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4618 00:23:00.944763 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4619 00:23:00.944876 == TX Byte 1 ==
4620 00:23:00.947863 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4621 00:23:00.954385 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4622 00:23:00.954505 ==
4623 00:23:00.957816 Dram Type= 6, Freq= 0, CH_1, rank 0
4624 00:23:00.960789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4625 00:23:00.960899 ==
4626 00:23:00.961005
4627 00:23:00.961108
4628 00:23:00.964295 TX Vref Scan disable
4629 00:23:00.967230 == TX Byte 0 ==
4630 00:23:00.970705 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4631 00:23:00.974187 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4632 00:23:00.977701 == TX Byte 1 ==
4633 00:23:00.980740 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4634 00:23:00.984091 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4635 00:23:00.984202
4636 00:23:00.984305 [DATLAT]
4637 00:23:00.986990 Freq=600, CH1 RK0
4638 00:23:00.987105
4639 00:23:00.990418 DATLAT Default: 0x9
4640 00:23:00.990543 0, 0xFFFF, sum = 0
4641 00:23:00.993759 1, 0xFFFF, sum = 0
4642 00:23:00.993869 2, 0xFFFF, sum = 0
4643 00:23:00.997450 3, 0xFFFF, sum = 0
4644 00:23:00.997562 4, 0xFFFF, sum = 0
4645 00:23:01.000602 5, 0xFFFF, sum = 0
4646 00:23:01.000711 6, 0xFFFF, sum = 0
4647 00:23:01.003711 7, 0xFFFF, sum = 0
4648 00:23:01.003832 8, 0x0, sum = 1
4649 00:23:01.006815 9, 0x0, sum = 2
4650 00:23:01.006923 10, 0x0, sum = 3
4651 00:23:01.010541 11, 0x0, sum = 4
4652 00:23:01.010649 best_step = 9
4653 00:23:01.010757
4654 00:23:01.010851 ==
4655 00:23:01.013707 Dram Type= 6, Freq= 0, CH_1, rank 0
4656 00:23:01.016945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4657 00:23:01.019927 ==
4658 00:23:01.020034 RX Vref Scan: 1
4659 00:23:01.020142
4660 00:23:01.023600 RX Vref 0 -> 0, step: 1
4661 00:23:01.023706
4662 00:23:01.026562 RX Delay -195 -> 252, step: 8
4663 00:23:01.026668
4664 00:23:01.030242 Set Vref, RX VrefLevel [Byte0]: 48
4665 00:23:01.033255 [Byte1]: 54
4666 00:23:01.033363
4667 00:23:01.036680 Final RX Vref Byte 0 = 48 to rank0
4668 00:23:01.039786 Final RX Vref Byte 1 = 54 to rank0
4669 00:23:01.043419 Final RX Vref Byte 0 = 48 to rank1
4670 00:23:01.046582 Final RX Vref Byte 1 = 54 to rank1==
4671 00:23:01.049378 Dram Type= 6, Freq= 0, CH_1, rank 0
4672 00:23:01.053384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4673 00:23:01.053487 ==
4674 00:23:01.056401 DQS Delay:
4675 00:23:01.056510 DQS0 = 0, DQS1 = 0
4676 00:23:01.056594 DQM Delay:
4677 00:23:01.059703 DQM0 = 48, DQM1 = 37
4678 00:23:01.059809 DQ Delay:
4679 00:23:01.063269 DQ0 =56, DQ1 =44, DQ2 =40, DQ3 =44
4680 00:23:01.066299 DQ4 =44, DQ5 =56, DQ6 =56, DQ7 =44
4681 00:23:01.069831 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4682 00:23:01.072880 DQ12 =48, DQ13 =44, DQ14 =44, DQ15 =48
4683 00:23:01.073022
4684 00:23:01.073133
4685 00:23:01.083292 [DQSOSCAuto] RK0, (LSB)MR18= 0x4e33, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 395 ps
4686 00:23:01.083566 CH1 RK0: MR19=808, MR18=4E33
4687 00:23:01.089508 CH1_RK0: MR19=0x808, MR18=0x4E33, DQSOSC=395, MR23=63, INC=168, DEC=112
4688 00:23:01.089726
4689 00:23:01.093012 ----->DramcWriteLeveling(PI) begin...
4690 00:23:01.096126 ==
4691 00:23:01.099489 Dram Type= 6, Freq= 0, CH_1, rank 1
4692 00:23:01.103322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4693 00:23:01.103756 ==
4694 00:23:01.106494 Write leveling (Byte 0): 30 => 30
4695 00:23:01.109863 Write leveling (Byte 1): 30 => 30
4696 00:23:01.112877 DramcWriteLeveling(PI) end<-----
4697 00:23:01.113305
4698 00:23:01.113640 ==
4699 00:23:01.116538 Dram Type= 6, Freq= 0, CH_1, rank 1
4700 00:23:01.119780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4701 00:23:01.120211 ==
4702 00:23:01.123039 [Gating] SW mode calibration
4703 00:23:01.129498 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4704 00:23:01.136223 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4705 00:23:01.139077 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4706 00:23:01.142796 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4707 00:23:01.148852 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4708 00:23:01.152538 0 9 12 | B1->B0 | 2f2f 3232 | 0 1 | (0 0) (1 0)
4709 00:23:01.155497 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4710 00:23:01.162119 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4711 00:23:01.165458 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4712 00:23:01.168886 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4713 00:23:01.175424 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4714 00:23:01.178916 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4715 00:23:01.182358 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4716 00:23:01.188680 0 10 12 | B1->B0 | 3636 2b2b | 0 0 | (1 1) (0 0)
4717 00:23:01.192399 0 10 16 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
4718 00:23:01.195366 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4719 00:23:01.202318 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4720 00:23:01.205241 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4721 00:23:01.208744 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4722 00:23:01.215178 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4723 00:23:01.218102 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4724 00:23:01.221542 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4725 00:23:01.228095 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4726 00:23:01.231595 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4727 00:23:01.234994 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4728 00:23:01.237907 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4729 00:23:01.244691 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4730 00:23:01.247818 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4731 00:23:01.251680 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4732 00:23:01.257715 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4733 00:23:01.261461 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4734 00:23:01.267975 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4735 00:23:01.270983 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4736 00:23:01.274293 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4737 00:23:01.280830 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4738 00:23:01.284381 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4739 00:23:01.287369 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4740 00:23:01.294315 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4741 00:23:01.297449 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4742 00:23:01.300922 Total UI for P1: 0, mck2ui 16
4743 00:23:01.304513 best dqsien dly found for B0: ( 0, 13, 14)
4744 00:23:01.307774 Total UI for P1: 0, mck2ui 16
4745 00:23:01.310975 best dqsien dly found for B1: ( 0, 13, 14)
4746 00:23:01.314594 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4747 00:23:01.317340 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4748 00:23:01.317934
4749 00:23:01.321007 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4750 00:23:01.323996 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4751 00:23:01.327584 [Gating] SW calibration Done
4752 00:23:01.328025 ==
4753 00:23:01.330618 Dram Type= 6, Freq= 0, CH_1, rank 1
4754 00:23:01.334050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4755 00:23:01.337165 ==
4756 00:23:01.337695 RX Vref Scan: 0
4757 00:23:01.338204
4758 00:23:01.340847 RX Vref 0 -> 0, step: 1
4759 00:23:01.341372
4760 00:23:01.344314 RX Delay -230 -> 252, step: 16
4761 00:23:01.347000 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4762 00:23:01.350442 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4763 00:23:01.354134 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4764 00:23:01.357382 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4765 00:23:01.364194 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4766 00:23:01.367194 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4767 00:23:01.370150 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4768 00:23:01.373861 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4769 00:23:01.380179 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4770 00:23:01.383545 iDelay=218, Bit 9, Center 33 (-134 ~ 201) 336
4771 00:23:01.387269 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4772 00:23:01.390243 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4773 00:23:01.396935 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4774 00:23:01.400394 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4775 00:23:01.403394 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4776 00:23:01.407103 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4777 00:23:01.407778 ==
4778 00:23:01.409971 Dram Type= 6, Freq= 0, CH_1, rank 1
4779 00:23:01.417095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4780 00:23:01.417611 ==
4781 00:23:01.417948 DQS Delay:
4782 00:23:01.420019 DQS0 = 0, DQS1 = 0
4783 00:23:01.420477 DQM Delay:
4784 00:23:01.421007 DQM0 = 43, DQM1 = 40
4785 00:23:01.423519 DQ Delay:
4786 00:23:01.426524 DQ0 =49, DQ1 =41, DQ2 =25, DQ3 =41
4787 00:23:01.429958 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =41
4788 00:23:01.432940 DQ8 =25, DQ9 =33, DQ10 =33, DQ11 =33
4789 00:23:01.436570 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4790 00:23:01.437219
4791 00:23:01.437710
4792 00:23:01.438226 ==
4793 00:23:01.439585 Dram Type= 6, Freq= 0, CH_1, rank 1
4794 00:23:01.443365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4795 00:23:01.443940 ==
4796 00:23:01.444428
4797 00:23:01.444997
4798 00:23:01.446322 TX Vref Scan disable
4799 00:23:01.449401 == TX Byte 0 ==
4800 00:23:01.452991 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4801 00:23:01.456466 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4802 00:23:01.459400 == TX Byte 1 ==
4803 00:23:01.462622 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4804 00:23:01.465836 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4805 00:23:01.466406 ==
4806 00:23:01.469398 Dram Type= 6, Freq= 0, CH_1, rank 1
4807 00:23:01.476050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4808 00:23:01.476650 ==
4809 00:23:01.477145
4810 00:23:01.477584
4811 00:23:01.477896 TX Vref Scan disable
4812 00:23:01.480259 == TX Byte 0 ==
4813 00:23:01.483183 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4814 00:23:01.490066 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4815 00:23:01.490621 == TX Byte 1 ==
4816 00:23:01.493646 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4817 00:23:01.499647 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4818 00:23:01.500237
4819 00:23:01.500749 [DATLAT]
4820 00:23:01.501226 Freq=600, CH1 RK1
4821 00:23:01.501747
4822 00:23:01.503114 DATLAT Default: 0x9
4823 00:23:01.506462 0, 0xFFFF, sum = 0
4824 00:23:01.506902 1, 0xFFFF, sum = 0
4825 00:23:01.509395 2, 0xFFFF, sum = 0
4826 00:23:01.509828 3, 0xFFFF, sum = 0
4827 00:23:01.512970 4, 0xFFFF, sum = 0
4828 00:23:01.513558 5, 0xFFFF, sum = 0
4829 00:23:01.516152 6, 0xFFFF, sum = 0
4830 00:23:01.516582 7, 0xFFFF, sum = 0
4831 00:23:01.519914 8, 0x0, sum = 1
4832 00:23:01.520356 9, 0x0, sum = 2
4833 00:23:01.522771 10, 0x0, sum = 3
4834 00:23:01.523230 11, 0x0, sum = 4
4835 00:23:01.523575 best_step = 9
4836 00:23:01.523910
4837 00:23:01.526406 ==
4838 00:23:01.529558 Dram Type= 6, Freq= 0, CH_1, rank 1
4839 00:23:01.532635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4840 00:23:01.533094 ==
4841 00:23:01.533430 RX Vref Scan: 0
4842 00:23:01.533748
4843 00:23:01.535995 RX Vref 0 -> 0, step: 1
4844 00:23:01.536426
4845 00:23:01.539566 RX Delay -179 -> 252, step: 8
4846 00:23:01.545600 iDelay=213, Bit 0, Center 48 (-99 ~ 196) 296
4847 00:23:01.549263 iDelay=213, Bit 1, Center 40 (-107 ~ 188) 296
4848 00:23:01.552313 iDelay=213, Bit 2, Center 32 (-115 ~ 180) 296
4849 00:23:01.555788 iDelay=213, Bit 3, Center 44 (-99 ~ 188) 288
4850 00:23:01.559398 iDelay=213, Bit 4, Center 44 (-107 ~ 196) 304
4851 00:23:01.565946 iDelay=213, Bit 5, Center 56 (-91 ~ 204) 296
4852 00:23:01.568848 iDelay=213, Bit 6, Center 60 (-91 ~ 212) 304
4853 00:23:01.572251 iDelay=213, Bit 7, Center 44 (-107 ~ 196) 304
4854 00:23:01.575704 iDelay=213, Bit 8, Center 24 (-131 ~ 180) 312
4855 00:23:01.582071 iDelay=213, Bit 9, Center 24 (-131 ~ 180) 312
4856 00:23:01.585880 iDelay=213, Bit 10, Center 36 (-115 ~ 188) 304
4857 00:23:01.588895 iDelay=213, Bit 11, Center 28 (-123 ~ 180) 304
4858 00:23:01.592398 iDelay=213, Bit 12, Center 48 (-107 ~ 204) 312
4859 00:23:01.598798 iDelay=213, Bit 13, Center 44 (-107 ~ 196) 304
4860 00:23:01.601883 iDelay=213, Bit 14, Center 40 (-115 ~ 196) 312
4861 00:23:01.605597 iDelay=213, Bit 15, Center 48 (-107 ~ 204) 312
4862 00:23:01.606057 ==
4863 00:23:01.608432 Dram Type= 6, Freq= 0, CH_1, rank 1
4864 00:23:01.611819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4865 00:23:01.612383 ==
4866 00:23:01.615210 DQS Delay:
4867 00:23:01.615807 DQS0 = 0, DQS1 = 0
4868 00:23:01.618639 DQM Delay:
4869 00:23:01.619201 DQM0 = 46, DQM1 = 36
4870 00:23:01.619677 DQ Delay:
4871 00:23:01.622202 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =44
4872 00:23:01.625028 DQ4 =44, DQ5 =56, DQ6 =60, DQ7 =44
4873 00:23:01.628699 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =28
4874 00:23:01.631672 DQ12 =48, DQ13 =44, DQ14 =40, DQ15 =48
4875 00:23:01.632261
4876 00:23:01.632782
4877 00:23:01.642205 [DQSOSCAuto] RK1, (LSB)MR18= 0x2e24, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 401 ps
4878 00:23:01.645060 CH1 RK1: MR19=808, MR18=2E24
4879 00:23:01.652095 CH1_RK1: MR19=0x808, MR18=0x2E24, DQSOSC=401, MR23=63, INC=163, DEC=108
4880 00:23:01.655165 [RxdqsGatingPostProcess] freq 600
4881 00:23:01.658221 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4882 00:23:01.661757 Pre-setting of DQS Precalculation
4883 00:23:01.668455 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4884 00:23:01.674702 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4885 00:23:01.681425 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4886 00:23:01.682037
4887 00:23:01.682619
4888 00:23:01.684735 [Calibration Summary] 1200 Mbps
4889 00:23:01.685276 CH 0, Rank 0
4890 00:23:01.687717 SW Impedance : PASS
4891 00:23:01.691223 DUTY Scan : NO K
4892 00:23:01.691755 ZQ Calibration : PASS
4893 00:23:01.694271 Jitter Meter : NO K
4894 00:23:01.697718 CBT Training : PASS
4895 00:23:01.698149 Write leveling : PASS
4896 00:23:01.701308 RX DQS gating : PASS
4897 00:23:01.701892 RX DQ/DQS(RDDQC) : PASS
4898 00:23:01.704342 TX DQ/DQS : PASS
4899 00:23:01.707942 RX DATLAT : PASS
4900 00:23:01.708366 RX DQ/DQS(Engine): PASS
4901 00:23:01.710797 TX OE : NO K
4902 00:23:01.711279 All Pass.
4903 00:23:01.711780
4904 00:23:01.714090 CH 0, Rank 1
4905 00:23:01.714744 SW Impedance : PASS
4906 00:23:01.717743 DUTY Scan : NO K
4907 00:23:01.720532 ZQ Calibration : PASS
4908 00:23:01.720959 Jitter Meter : NO K
4909 00:23:01.723966 CBT Training : PASS
4910 00:23:01.727519 Write leveling : PASS
4911 00:23:01.727945 RX DQS gating : PASS
4912 00:23:01.730623 RX DQ/DQS(RDDQC) : PASS
4913 00:23:01.734341 TX DQ/DQS : PASS
4914 00:23:01.734775 RX DATLAT : PASS
4915 00:23:01.737171 RX DQ/DQS(Engine): PASS
4916 00:23:01.740514 TX OE : NO K
4917 00:23:01.740942 All Pass.
4918 00:23:01.741277
4919 00:23:01.741656 CH 1, Rank 0
4920 00:23:01.743768 SW Impedance : PASS
4921 00:23:01.747447 DUTY Scan : NO K
4922 00:23:01.747873 ZQ Calibration : PASS
4923 00:23:01.750645 Jitter Meter : NO K
4924 00:23:01.753921 CBT Training : PASS
4925 00:23:01.754387 Write leveling : PASS
4926 00:23:01.757090 RX DQS gating : PASS
4927 00:23:01.760321 RX DQ/DQS(RDDQC) : PASS
4928 00:23:01.760748 TX DQ/DQS : PASS
4929 00:23:01.763874 RX DATLAT : PASS
4930 00:23:01.764300 RX DQ/DQS(Engine): PASS
4931 00:23:01.767522 TX OE : NO K
4932 00:23:01.767952 All Pass.
4933 00:23:01.768289
4934 00:23:01.770482 CH 1, Rank 1
4935 00:23:01.773522 SW Impedance : PASS
4936 00:23:01.773949 DUTY Scan : NO K
4937 00:23:01.777178 ZQ Calibration : PASS
4938 00:23:01.777602 Jitter Meter : NO K
4939 00:23:01.780245 CBT Training : PASS
4940 00:23:01.783249 Write leveling : PASS
4941 00:23:01.783675 RX DQS gating : PASS
4942 00:23:01.786723 RX DQ/DQS(RDDQC) : PASS
4943 00:23:01.790427 TX DQ/DQS : PASS
4944 00:23:01.790854 RX DATLAT : PASS
4945 00:23:01.793413 RX DQ/DQS(Engine): PASS
4946 00:23:01.796903 TX OE : NO K
4947 00:23:01.797522 All Pass.
4948 00:23:01.797961
4949 00:23:01.799958 DramC Write-DBI off
4950 00:23:01.800552 PER_BANK_REFRESH: Hybrid Mode
4951 00:23:01.803385 TX_TRACKING: ON
4952 00:23:01.813314 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4953 00:23:01.816477 [FAST_K] Save calibration result to emmc
4954 00:23:01.819830 dramc_set_vcore_voltage set vcore to 662500
4955 00:23:01.820260 Read voltage for 933, 3
4956 00:23:01.822862 Vio18 = 0
4957 00:23:01.823356 Vcore = 662500
4958 00:23:01.823699 Vdram = 0
4959 00:23:01.826275 Vddq = 0
4960 00:23:01.826703 Vmddr = 0
4961 00:23:01.833075 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4962 00:23:01.836886 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4963 00:23:01.839766 MEM_TYPE=3, freq_sel=17
4964 00:23:01.842667 sv_algorithm_assistance_LP4_1600
4965 00:23:01.845951 ============ PULL DRAM RESETB DOWN ============
4966 00:23:01.849294 ========== PULL DRAM RESETB DOWN end =========
4967 00:23:01.856317 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4968 00:23:01.859386 ===================================
4969 00:23:01.859812 LPDDR4 DRAM CONFIGURATION
4970 00:23:01.862326 ===================================
4971 00:23:01.866055 EX_ROW_EN[0] = 0x0
4972 00:23:01.869186 EX_ROW_EN[1] = 0x0
4973 00:23:01.869615 LP4Y_EN = 0x0
4974 00:23:01.872280 WORK_FSP = 0x0
4975 00:23:01.872706 WL = 0x3
4976 00:23:01.875916 RL = 0x3
4977 00:23:01.876341 BL = 0x2
4978 00:23:01.878795 RPST = 0x0
4979 00:23:01.879229 RD_PRE = 0x0
4980 00:23:01.891947 WR_PRE = 0x1
4981 00:23:01.892728 WR_PST = 0x0
4982 00:23:01.893314 DBI_WR = 0x0
4983 00:23:01.893882 DBI_RD = 0x0
4984 00:23:01.894465 OTF = 0x1
4985 00:23:01.895407 ===================================
4986 00:23:01.895923 ===================================
4987 00:23:01.896272 ANA top config
4988 00:23:01.899031 ===================================
4989 00:23:01.901933 DLL_ASYNC_EN = 0
4990 00:23:01.905304 ALL_SLAVE_EN = 1
4991 00:23:01.908828 NEW_RANK_MODE = 1
4992 00:23:01.909262 DLL_IDLE_MODE = 1
4993 00:23:01.911617 LP45_APHY_COMB_EN = 1
4994 00:23:01.914901 TX_ODT_DIS = 1
4995 00:23:01.918232 NEW_8X_MODE = 1
4996 00:23:01.921904 ===================================
4997 00:23:01.924696 ===================================
4998 00:23:01.928416 data_rate = 1866
4999 00:23:01.931387 CKR = 1
5000 00:23:01.931960 DQ_P2S_RATIO = 8
5001 00:23:01.934657 ===================================
5002 00:23:01.938220 CA_P2S_RATIO = 8
5003 00:23:01.941436 DQ_CA_OPEN = 0
5004 00:23:01.944626 DQ_SEMI_OPEN = 0
5005 00:23:01.947956 CA_SEMI_OPEN = 0
5006 00:23:01.951423 CA_FULL_RATE = 0
5007 00:23:01.951950 DQ_CKDIV4_EN = 1
5008 00:23:01.954920 CA_CKDIV4_EN = 1
5009 00:23:01.957735 CA_PREDIV_EN = 0
5010 00:23:01.961121 PH8_DLY = 0
5011 00:23:01.964607 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
5012 00:23:01.968168 DQ_AAMCK_DIV = 4
5013 00:23:01.968681 CA_AAMCK_DIV = 4
5014 00:23:01.971257 CA_ADMCK_DIV = 4
5015 00:23:01.974346 DQ_TRACK_CA_EN = 0
5016 00:23:01.978028 CA_PICK = 933
5017 00:23:01.980955 CA_MCKIO = 933
5018 00:23:01.984512 MCKIO_SEMI = 0
5019 00:23:01.987455 PLL_FREQ = 3732
5020 00:23:01.987902 DQ_UI_PI_RATIO = 32
5021 00:23:01.991137 CA_UI_PI_RATIO = 0
5022 00:23:01.994704 ===================================
5023 00:23:01.997687 ===================================
5024 00:23:02.000942 memory_type:LPDDR4
5025 00:23:02.004479 GP_NUM : 10
5026 00:23:02.004906 SRAM_EN : 1
5027 00:23:02.007543 MD32_EN : 0
5028 00:23:02.011023 ===================================
5029 00:23:02.014616 [ANA_INIT] >>>>>>>>>>>>>>
5030 00:23:02.015041 <<<<<< [CONFIGURE PHASE]: ANA_TX
5031 00:23:02.017592 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5032 00:23:02.020925 ===================================
5033 00:23:02.024319 data_rate = 1866,PCW = 0X8f00
5034 00:23:02.027687 ===================================
5035 00:23:02.030567 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5036 00:23:02.037015 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5037 00:23:02.043709 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5038 00:23:02.047331 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5039 00:23:02.050379 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5040 00:23:02.053745 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5041 00:23:02.056864 [ANA_INIT] flow start
5042 00:23:02.057351 [ANA_INIT] PLL >>>>>>>>
5043 00:23:02.060203 [ANA_INIT] PLL <<<<<<<<
5044 00:23:02.063613 [ANA_INIT] MIDPI >>>>>>>>
5045 00:23:02.066911 [ANA_INIT] MIDPI <<<<<<<<
5046 00:23:02.067291 [ANA_INIT] DLL >>>>>>>>
5047 00:23:02.069810 [ANA_INIT] flow end
5048 00:23:02.073613 ============ LP4 DIFF to SE enter ============
5049 00:23:02.076667 ============ LP4 DIFF to SE exit ============
5050 00:23:02.079749 [ANA_INIT] <<<<<<<<<<<<<
5051 00:23:02.083313 [Flow] Enable top DCM control >>>>>
5052 00:23:02.086310 [Flow] Enable top DCM control <<<<<
5053 00:23:02.089819 Enable DLL master slave shuffle
5054 00:23:02.096415 ==============================================================
5055 00:23:02.096861 Gating Mode config
5056 00:23:02.103028 ==============================================================
5057 00:23:02.106086 Config description:
5058 00:23:02.112617 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5059 00:23:02.119857 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5060 00:23:02.126404 SELPH_MODE 0: By rank 1: By Phase
5061 00:23:02.132474 ==============================================================
5062 00:23:02.132900 GAT_TRACK_EN = 1
5063 00:23:02.136165 RX_GATING_MODE = 2
5064 00:23:02.139367 RX_GATING_TRACK_MODE = 2
5065 00:23:02.142545 SELPH_MODE = 1
5066 00:23:02.146016 PICG_EARLY_EN = 1
5067 00:23:02.149591 VALID_LAT_VALUE = 1
5068 00:23:02.155714 ==============================================================
5069 00:23:02.159251 Enter into Gating configuration >>>>
5070 00:23:02.162263 Exit from Gating configuration <<<<
5071 00:23:02.165166 Enter into DVFS_PRE_config >>>>>
5072 00:23:02.175120 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5073 00:23:02.178522 Exit from DVFS_PRE_config <<<<<
5074 00:23:02.181971 Enter into PICG configuration >>>>
5075 00:23:02.185215 Exit from PICG configuration <<<<
5076 00:23:02.188334 [RX_INPUT] configuration >>>>>
5077 00:23:02.192053 [RX_INPUT] configuration <<<<<
5078 00:23:02.194846 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5079 00:23:02.201504 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5080 00:23:02.208123 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5081 00:23:02.214638 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5082 00:23:02.218157 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5083 00:23:02.224391 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5084 00:23:02.231407 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5085 00:23:02.234291 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5086 00:23:02.238011 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5087 00:23:02.241066 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5088 00:23:02.247746 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5089 00:23:02.250980 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5090 00:23:02.254743 ===================================
5091 00:23:02.257632 LPDDR4 DRAM CONFIGURATION
5092 00:23:02.260896 ===================================
5093 00:23:02.261315 EX_ROW_EN[0] = 0x0
5094 00:23:02.264402 EX_ROW_EN[1] = 0x0
5095 00:23:02.264818 LP4Y_EN = 0x0
5096 00:23:02.267415 WORK_FSP = 0x0
5097 00:23:02.267835 WL = 0x3
5098 00:23:02.270467 RL = 0x3
5099 00:23:02.270898 BL = 0x2
5100 00:23:02.273992 RPST = 0x0
5101 00:23:02.277349 RD_PRE = 0x0
5102 00:23:02.277764 WR_PRE = 0x1
5103 00:23:02.280564 WR_PST = 0x0
5104 00:23:02.281013 DBI_WR = 0x0
5105 00:23:02.284231 DBI_RD = 0x0
5106 00:23:02.284685 OTF = 0x1
5107 00:23:02.287293 ===================================
5108 00:23:02.290923 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5109 00:23:02.297056 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5110 00:23:02.300411 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5111 00:23:02.303911 ===================================
5112 00:23:02.307276 LPDDR4 DRAM CONFIGURATION
5113 00:23:02.310445 ===================================
5114 00:23:02.310866 EX_ROW_EN[0] = 0x10
5115 00:23:02.313525 EX_ROW_EN[1] = 0x0
5116 00:23:02.313945 LP4Y_EN = 0x0
5117 00:23:02.317055 WORK_FSP = 0x0
5118 00:23:02.317609 WL = 0x3
5119 00:23:02.320219 RL = 0x3
5120 00:23:02.320705 BL = 0x2
5121 00:23:02.323473 RPST = 0x0
5122 00:23:02.327183 RD_PRE = 0x0
5123 00:23:02.327658 WR_PRE = 0x1
5124 00:23:02.330317 WR_PST = 0x0
5125 00:23:02.330768 DBI_WR = 0x0
5126 00:23:02.333611 DBI_RD = 0x0
5127 00:23:02.334109 OTF = 0x1
5128 00:23:02.336594 ===================================
5129 00:23:02.343258 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5130 00:23:02.346870 nWR fixed to 30
5131 00:23:02.350225 [ModeRegInit_LP4] CH0 RK0
5132 00:23:02.350671 [ModeRegInit_LP4] CH0 RK1
5133 00:23:02.353753 [ModeRegInit_LP4] CH1 RK0
5134 00:23:02.357019 [ModeRegInit_LP4] CH1 RK1
5135 00:23:02.357528 match AC timing 9
5136 00:23:02.363926 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5137 00:23:02.366718 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5138 00:23:02.370567 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5139 00:23:02.376645 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5140 00:23:02.380505 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5141 00:23:02.380950 ==
5142 00:23:02.383189 Dram Type= 6, Freq= 0, CH_0, rank 0
5143 00:23:02.386692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5144 00:23:02.387137 ==
5145 00:23:02.393363 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5146 00:23:02.400228 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5147 00:23:02.403159 [CA 0] Center 37 (7~68) winsize 62
5148 00:23:02.406666 [CA 1] Center 37 (7~68) winsize 62
5149 00:23:02.409898 [CA 2] Center 34 (4~65) winsize 62
5150 00:23:02.412935 [CA 3] Center 35 (5~65) winsize 61
5151 00:23:02.416548 [CA 4] Center 33 (3~64) winsize 62
5152 00:23:02.419525 [CA 5] Center 33 (3~63) winsize 61
5153 00:23:02.419985
5154 00:23:02.423313 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5155 00:23:02.423780
5156 00:23:02.426226 [CATrainingPosCal] consider 1 rank data
5157 00:23:02.429622 u2DelayCellTimex100 = 270/100 ps
5158 00:23:02.432949 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5159 00:23:02.435958 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5160 00:23:02.439845 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5161 00:23:02.443139 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5162 00:23:02.449650 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5163 00:23:02.452682 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5164 00:23:02.453150
5165 00:23:02.456263 CA PerBit enable=1, Macro0, CA PI delay=33
5166 00:23:02.456729
5167 00:23:02.459250 [CBTSetCACLKResult] CA Dly = 33
5168 00:23:02.459844 CS Dly: 7 (0~38)
5169 00:23:02.460359 ==
5170 00:23:02.462610 Dram Type= 6, Freq= 0, CH_0, rank 1
5171 00:23:02.469023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5172 00:23:02.469595 ==
5173 00:23:02.472700 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5174 00:23:02.478868 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5175 00:23:02.482120 [CA 0] Center 37 (7~68) winsize 62
5176 00:23:02.485409 [CA 1] Center 37 (7~68) winsize 62
5177 00:23:02.488618 [CA 2] Center 34 (4~65) winsize 62
5178 00:23:02.492177 [CA 3] Center 34 (4~65) winsize 62
5179 00:23:02.495392 [CA 4] Center 33 (3~64) winsize 62
5180 00:23:02.498850 [CA 5] Center 32 (2~63) winsize 62
5181 00:23:02.499295
5182 00:23:02.501953 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5183 00:23:02.502457
5184 00:23:02.505563 [CATrainingPosCal] consider 2 rank data
5185 00:23:02.508629 u2DelayCellTimex100 = 270/100 ps
5186 00:23:02.511694 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5187 00:23:02.518540 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5188 00:23:02.521600 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5189 00:23:02.525204 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5190 00:23:02.528270 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5191 00:23:02.531702 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5192 00:23:02.532287
5193 00:23:02.534678 CA PerBit enable=1, Macro0, CA PI delay=33
5194 00:23:02.535297
5195 00:23:02.538313 [CBTSetCACLKResult] CA Dly = 33
5196 00:23:02.541364 CS Dly: 7 (0~39)
5197 00:23:02.541941
5198 00:23:02.544712 ----->DramcWriteLeveling(PI) begin...
5199 00:23:02.545277 ==
5200 00:23:02.547817 Dram Type= 6, Freq= 0, CH_0, rank 0
5201 00:23:02.551263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5202 00:23:02.551941 ==
5203 00:23:02.554365 Write leveling (Byte 0): 31 => 31
5204 00:23:02.557781 Write leveling (Byte 1): 30 => 30
5205 00:23:02.561603 DramcWriteLeveling(PI) end<-----
5206 00:23:02.562269
5207 00:23:02.562652 ==
5208 00:23:02.564417 Dram Type= 6, Freq= 0, CH_0, rank 0
5209 00:23:02.567737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5210 00:23:02.568316 ==
5211 00:23:02.571195 [Gating] SW mode calibration
5212 00:23:02.577765 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5213 00:23:02.584149 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5214 00:23:02.587866 0 14 0 | B1->B0 | 2323 3030 | 0 1 | (0 0) (0 0)
5215 00:23:02.594314 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5216 00:23:02.597700 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5217 00:23:02.600945 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5218 00:23:02.607442 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5219 00:23:02.610668 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5220 00:23:02.613650 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5221 00:23:02.620169 0 14 28 | B1->B0 | 3434 2d2d | 1 0 | (1 0) (0 1)
5222 00:23:02.623678 0 15 0 | B1->B0 | 3333 2323 | 0 0 | (1 0) (0 0)
5223 00:23:02.626821 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5224 00:23:02.633449 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5225 00:23:02.637089 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5226 00:23:02.640001 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5227 00:23:02.647113 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5228 00:23:02.650437 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5229 00:23:02.653607 0 15 28 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
5230 00:23:02.660081 1 0 0 | B1->B0 | 3131 4545 | 0 0 | (0 0) (0 0)
5231 00:23:02.663218 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5232 00:23:02.666853 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5233 00:23:02.673034 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5234 00:23:02.676147 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5235 00:23:02.679894 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5236 00:23:02.686715 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5237 00:23:02.689576 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5238 00:23:02.693159 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5239 00:23:02.699687 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5240 00:23:02.703057 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5241 00:23:02.705996 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5242 00:23:02.712992 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5243 00:23:02.716293 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5244 00:23:02.719276 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5245 00:23:02.722898 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5246 00:23:02.729420 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5247 00:23:02.732684 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5248 00:23:02.735916 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5249 00:23:02.742484 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5250 00:23:02.745329 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5251 00:23:02.749121 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5252 00:23:02.755893 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5253 00:23:02.758915 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5254 00:23:02.762748 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5255 00:23:02.768960 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5256 00:23:02.772014 Total UI for P1: 0, mck2ui 16
5257 00:23:02.775213 best dqsien dly found for B0: ( 1, 2, 30)
5258 00:23:02.778307 Total UI for P1: 0, mck2ui 16
5259 00:23:02.782045 best dqsien dly found for B1: ( 1, 3, 0)
5260 00:23:02.785080 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5261 00:23:02.788685 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5262 00:23:02.788765
5263 00:23:02.791739 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5264 00:23:02.795131 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5265 00:23:02.798307 [Gating] SW calibration Done
5266 00:23:02.798447 ==
5267 00:23:02.801622 Dram Type= 6, Freq= 0, CH_0, rank 0
5268 00:23:02.805017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5269 00:23:02.805101 ==
5270 00:23:02.808097 RX Vref Scan: 0
5271 00:23:02.808170
5272 00:23:02.811818 RX Vref 0 -> 0, step: 1
5273 00:23:02.811895
5274 00:23:02.811958 RX Delay -80 -> 252, step: 8
5275 00:23:02.818522 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5276 00:23:02.821534 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5277 00:23:02.824661 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5278 00:23:02.828114 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5279 00:23:02.831360 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5280 00:23:02.834419 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5281 00:23:02.841234 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5282 00:23:02.844985 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5283 00:23:02.847692 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5284 00:23:02.851507 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5285 00:23:02.854371 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5286 00:23:02.860856 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5287 00:23:02.864623 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5288 00:23:02.867558 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5289 00:23:02.871070 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5290 00:23:02.874187 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5291 00:23:02.877796 ==
5292 00:23:02.880818 Dram Type= 6, Freq= 0, CH_0, rank 0
5293 00:23:02.884003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5294 00:23:02.884163 ==
5295 00:23:02.884284 DQS Delay:
5296 00:23:02.887410 DQS0 = 0, DQS1 = 0
5297 00:23:02.887584 DQM Delay:
5298 00:23:02.890572 DQM0 = 96, DQM1 = 86
5299 00:23:02.890776 DQ Delay:
5300 00:23:02.894377 DQ0 =99, DQ1 =99, DQ2 =91, DQ3 =91
5301 00:23:02.897541 DQ4 =99, DQ5 =83, DQ6 =103, DQ7 =107
5302 00:23:02.900655 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79
5303 00:23:02.904314 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5304 00:23:02.904618
5305 00:23:02.904853
5306 00:23:02.905073 ==
5307 00:23:02.907447 Dram Type= 6, Freq= 0, CH_0, rank 0
5308 00:23:02.910964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5309 00:23:02.911445 ==
5310 00:23:02.911946
5311 00:23:02.912329
5312 00:23:02.913420 TX Vref Scan disable
5313 00:23:02.916768 == TX Byte 0 ==
5314 00:23:02.920069 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5315 00:23:02.923627 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5316 00:23:02.926634 == TX Byte 1 ==
5317 00:23:02.930092 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5318 00:23:02.933279 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5319 00:23:02.933368 ==
5320 00:23:02.936755 Dram Type= 6, Freq= 0, CH_0, rank 0
5321 00:23:02.943298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5322 00:23:02.943382 ==
5323 00:23:02.943447
5324 00:23:02.943507
5325 00:23:02.943565 TX Vref Scan disable
5326 00:23:02.947764 == TX Byte 0 ==
5327 00:23:02.950821 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5328 00:23:02.957285 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5329 00:23:02.957381 == TX Byte 1 ==
5330 00:23:02.960914 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5331 00:23:02.967066 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5332 00:23:02.967181
5333 00:23:02.967270 [DATLAT]
5334 00:23:02.967351 Freq=933, CH0 RK0
5335 00:23:02.967429
5336 00:23:02.970778 DATLAT Default: 0xd
5337 00:23:02.970902 0, 0xFFFF, sum = 0
5338 00:23:02.974228 1, 0xFFFF, sum = 0
5339 00:23:02.977330 2, 0xFFFF, sum = 0
5340 00:23:02.977469 3, 0xFFFF, sum = 0
5341 00:23:02.980939 4, 0xFFFF, sum = 0
5342 00:23:02.981096 5, 0xFFFF, sum = 0
5343 00:23:02.984022 6, 0xFFFF, sum = 0
5344 00:23:02.984177 7, 0xFFFF, sum = 0
5345 00:23:02.987638 8, 0xFFFF, sum = 0
5346 00:23:02.987816 9, 0xFFFF, sum = 0
5347 00:23:02.990701 10, 0x0, sum = 1
5348 00:23:02.990909 11, 0x0, sum = 2
5349 00:23:02.994154 12, 0x0, sum = 3
5350 00:23:02.994261 13, 0x0, sum = 4
5351 00:23:02.994327 best_step = 11
5352 00:23:02.997306
5353 00:23:02.997388 ==
5354 00:23:03.000213 Dram Type= 6, Freq= 0, CH_0, rank 0
5355 00:23:03.003294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5356 00:23:03.003379 ==
5357 00:23:03.003443 RX Vref Scan: 1
5358 00:23:03.003503
5359 00:23:03.007131 RX Vref 0 -> 0, step: 1
5360 00:23:03.007214
5361 00:23:03.010045 RX Delay -61 -> 252, step: 4
5362 00:23:03.010127
5363 00:23:03.013590 Set Vref, RX VrefLevel [Byte0]: 61
5364 00:23:03.016658 [Byte1]: 49
5365 00:23:03.020464
5366 00:23:03.020546 Final RX Vref Byte 0 = 61 to rank0
5367 00:23:03.023390 Final RX Vref Byte 1 = 49 to rank0
5368 00:23:03.026386 Final RX Vref Byte 0 = 61 to rank1
5369 00:23:03.029978 Final RX Vref Byte 1 = 49 to rank1==
5370 00:23:03.032892 Dram Type= 6, Freq= 0, CH_0, rank 0
5371 00:23:03.039566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5372 00:23:03.039648 ==
5373 00:23:03.039714 DQS Delay:
5374 00:23:03.043059 DQS0 = 0, DQS1 = 0
5375 00:23:03.043140 DQM Delay:
5376 00:23:03.043205 DQM0 = 96, DQM1 = 84
5377 00:23:03.045990 DQ Delay:
5378 00:23:03.049745 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =94
5379 00:23:03.052785 DQ4 =96, DQ5 =88, DQ6 =108, DQ7 =106
5380 00:23:03.055908 DQ8 =76, DQ9 =74, DQ10 =84, DQ11 =78
5381 00:23:03.059465 DQ12 =88, DQ13 =88, DQ14 =94, DQ15 =90
5382 00:23:03.059547
5383 00:23:03.059610
5384 00:23:03.066100 [DQSOSCAuto] RK0, (LSB)MR18= 0x2d14, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 407 ps
5385 00:23:03.069333 CH0 RK0: MR19=505, MR18=2D14
5386 00:23:03.075780 CH0_RK0: MR19=0x505, MR18=0x2D14, DQSOSC=407, MR23=63, INC=65, DEC=43
5387 00:23:03.075862
5388 00:23:03.079246 ----->DramcWriteLeveling(PI) begin...
5389 00:23:03.079329 ==
5390 00:23:03.082415 Dram Type= 6, Freq= 0, CH_0, rank 1
5391 00:23:03.085532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5392 00:23:03.085615 ==
5393 00:23:03.089285 Write leveling (Byte 0): 34 => 34
5394 00:23:03.092211 Write leveling (Byte 1): 29 => 29
5395 00:23:03.095393 DramcWriteLeveling(PI) end<-----
5396 00:23:03.095475
5397 00:23:03.095538 ==
5398 00:23:03.099134 Dram Type= 6, Freq= 0, CH_0, rank 1
5399 00:23:03.105142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5400 00:23:03.105272 ==
5401 00:23:03.108937 [Gating] SW mode calibration
5402 00:23:03.115197 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5403 00:23:03.118935 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5404 00:23:03.125035 0 14 0 | B1->B0 | 2b2b 3434 | 0 1 | (1 1) (1 1)
5405 00:23:03.128679 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5406 00:23:03.131693 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5407 00:23:03.138428 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5408 00:23:03.142092 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5409 00:23:03.145155 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5410 00:23:03.151506 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5411 00:23:03.155203 0 14 28 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 1)
5412 00:23:03.158327 0 15 0 | B1->B0 | 2e2e 2b2b | 0 0 | (0 1) (0 0)
5413 00:23:03.164671 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5414 00:23:03.167953 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5415 00:23:03.171336 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5416 00:23:03.178035 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5417 00:23:03.181378 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5418 00:23:03.184480 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5419 00:23:03.190921 0 15 28 | B1->B0 | 2525 3636 | 0 0 | (0 0) (0 0)
5420 00:23:03.194128 1 0 0 | B1->B0 | 3b3b 4545 | 0 0 | (0 0) (0 0)
5421 00:23:03.197366 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5422 00:23:03.204214 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5423 00:23:03.207303 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5424 00:23:03.210998 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5425 00:23:03.217298 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5426 00:23:03.220498 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5427 00:23:03.224146 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5428 00:23:03.230278 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5429 00:23:03.233868 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5430 00:23:03.236877 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5431 00:23:03.243891 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5432 00:23:03.246737 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5433 00:23:03.249995 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5434 00:23:03.256869 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5435 00:23:03.260006 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5436 00:23:03.263526 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5437 00:23:03.269775 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5438 00:23:03.273213 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5439 00:23:03.276782 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5440 00:23:03.282990 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5441 00:23:03.286645 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5442 00:23:03.289504 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5443 00:23:03.296338 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5444 00:23:03.299360 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5445 00:23:03.302859 Total UI for P1: 0, mck2ui 16
5446 00:23:03.306006 best dqsien dly found for B0: ( 1, 2, 30)
5447 00:23:03.309474 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5448 00:23:03.312811 Total UI for P1: 0, mck2ui 16
5449 00:23:03.315926 best dqsien dly found for B1: ( 1, 3, 0)
5450 00:23:03.319486 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5451 00:23:03.322601 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5452 00:23:03.322674
5453 00:23:03.329396 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5454 00:23:03.332544 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5455 00:23:03.332632 [Gating] SW calibration Done
5456 00:23:03.336168 ==
5457 00:23:03.339230 Dram Type= 6, Freq= 0, CH_0, rank 1
5458 00:23:03.342368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5459 00:23:03.342445 ==
5460 00:23:03.342508 RX Vref Scan: 0
5461 00:23:03.342568
5462 00:23:03.345935 RX Vref 0 -> 0, step: 1
5463 00:23:03.346010
5464 00:23:03.349107 RX Delay -80 -> 252, step: 8
5465 00:23:03.352900 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5466 00:23:03.355879 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5467 00:23:03.358888 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5468 00:23:03.365522 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5469 00:23:03.368922 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5470 00:23:03.372433 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5471 00:23:03.375668 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5472 00:23:03.379130 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5473 00:23:03.382121 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5474 00:23:03.388923 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5475 00:23:03.391951 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5476 00:23:03.395273 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5477 00:23:03.398874 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5478 00:23:03.405541 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5479 00:23:03.408653 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5480 00:23:03.412263 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5481 00:23:03.412716 ==
5482 00:23:03.415437 Dram Type= 6, Freq= 0, CH_0, rank 1
5483 00:23:03.418660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5484 00:23:03.419099 ==
5485 00:23:03.422196 DQS Delay:
5486 00:23:03.422624 DQS0 = 0, DQS1 = 0
5487 00:23:03.422986 DQM Delay:
5488 00:23:03.425498 DQM0 = 97, DQM1 = 87
5489 00:23:03.426071 DQ Delay:
5490 00:23:03.428599 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =91
5491 00:23:03.431751 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5492 00:23:03.435379 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =79
5493 00:23:03.438453 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =91
5494 00:23:03.438877
5495 00:23:03.439207
5496 00:23:03.439515 ==
5497 00:23:03.441857 Dram Type= 6, Freq= 0, CH_0, rank 1
5498 00:23:03.448485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5499 00:23:03.448910 ==
5500 00:23:03.449242
5501 00:23:03.449552
5502 00:23:03.451682 TX Vref Scan disable
5503 00:23:03.452105 == TX Byte 0 ==
5504 00:23:03.455382 Update DQ dly =719 (2 ,6, 15) DQ OEN =(2 ,3)
5505 00:23:03.461412 Update DQM dly =719 (2 ,6, 15) DQM OEN =(2 ,3)
5506 00:23:03.461839 == TX Byte 1 ==
5507 00:23:03.464916 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5508 00:23:03.471641 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5509 00:23:03.472069 ==
5510 00:23:03.474747 Dram Type= 6, Freq= 0, CH_0, rank 1
5511 00:23:03.478266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5512 00:23:03.478708 ==
5513 00:23:03.479061
5514 00:23:03.479601
5515 00:23:03.481213 TX Vref Scan disable
5516 00:23:03.484744 == TX Byte 0 ==
5517 00:23:03.487873 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5518 00:23:03.491472 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5519 00:23:03.494817 == TX Byte 1 ==
5520 00:23:03.497924 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5521 00:23:03.500977 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5522 00:23:03.501452
5523 00:23:03.504437 [DATLAT]
5524 00:23:03.504857 Freq=933, CH0 RK1
5525 00:23:03.505188
5526 00:23:03.507387 DATLAT Default: 0xb
5527 00:23:03.507940 0, 0xFFFF, sum = 0
5528 00:23:03.511025 1, 0xFFFF, sum = 0
5529 00:23:03.511452 2, 0xFFFF, sum = 0
5530 00:23:03.514281 3, 0xFFFF, sum = 0
5531 00:23:03.514710 4, 0xFFFF, sum = 0
5532 00:23:03.517479 5, 0xFFFF, sum = 0
5533 00:23:03.518076 6, 0xFFFF, sum = 0
5534 00:23:03.520894 7, 0xFFFF, sum = 0
5535 00:23:03.521318 8, 0xFFFF, sum = 0
5536 00:23:03.523886 9, 0xFFFF, sum = 0
5537 00:23:03.524316 10, 0x0, sum = 1
5538 00:23:03.527202 11, 0x0, sum = 2
5539 00:23:03.527628 12, 0x0, sum = 3
5540 00:23:03.530799 13, 0x0, sum = 4
5541 00:23:03.531228 best_step = 11
5542 00:23:03.531638
5543 00:23:03.531958 ==
5544 00:23:03.533748 Dram Type= 6, Freq= 0, CH_0, rank 1
5545 00:23:03.540597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5546 00:23:03.541023 ==
5547 00:23:03.541356 RX Vref Scan: 0
5548 00:23:03.541750
5549 00:23:03.543581 RX Vref 0 -> 0, step: 1
5550 00:23:03.544152
5551 00:23:03.547267 RX Delay -61 -> 252, step: 4
5552 00:23:03.550350 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5553 00:23:03.556897 iDelay=203, Bit 1, Center 96 (-1 ~ 194) 196
5554 00:23:03.560495 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5555 00:23:03.563323 iDelay=203, Bit 3, Center 92 (-5 ~ 190) 196
5556 00:23:03.567128 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5557 00:23:03.570000 iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192
5558 00:23:03.573638 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
5559 00:23:03.580297 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5560 00:23:03.583428 iDelay=203, Bit 8, Center 78 (-13 ~ 170) 184
5561 00:23:03.586391 iDelay=203, Bit 9, Center 74 (-17 ~ 166) 184
5562 00:23:03.589888 iDelay=203, Bit 10, Center 86 (-9 ~ 182) 192
5563 00:23:03.593008 iDelay=203, Bit 11, Center 78 (-13 ~ 170) 184
5564 00:23:03.599924 iDelay=203, Bit 12, Center 92 (-1 ~ 186) 188
5565 00:23:03.603450 iDelay=203, Bit 13, Center 92 (-1 ~ 186) 188
5566 00:23:03.606335 iDelay=203, Bit 14, Center 94 (3 ~ 186) 184
5567 00:23:03.609672 iDelay=203, Bit 15, Center 92 (-1 ~ 186) 188
5568 00:23:03.610094 ==
5569 00:23:03.612808 Dram Type= 6, Freq= 0, CH_0, rank 1
5570 00:23:03.619822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5571 00:23:03.620246 ==
5572 00:23:03.620575 DQS Delay:
5573 00:23:03.622583 DQS0 = 0, DQS1 = 0
5574 00:23:03.623002 DQM Delay:
5575 00:23:03.623333 DQM0 = 94, DQM1 = 85
5576 00:23:03.626527 DQ Delay:
5577 00:23:03.629375 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =92
5578 00:23:03.632972 DQ4 =96, DQ5 =86, DQ6 =104, DQ7 =104
5579 00:23:03.635792 DQ8 =78, DQ9 =74, DQ10 =86, DQ11 =78
5580 00:23:03.639408 DQ12 =92, DQ13 =92, DQ14 =94, DQ15 =92
5581 00:23:03.639892
5582 00:23:03.640237
5583 00:23:03.646022 [DQSOSCAuto] RK1, (LSB)MR18= 0x26f6, (MSB)MR19= 0x504, tDQSOscB0 = 425 ps tDQSOscB1 = 409 ps
5584 00:23:03.649354 CH0 RK1: MR19=504, MR18=26F6
5585 00:23:03.655757 CH0_RK1: MR19=0x504, MR18=0x26F6, DQSOSC=409, MR23=63, INC=64, DEC=43
5586 00:23:03.659138 [RxdqsGatingPostProcess] freq 933
5587 00:23:03.665528 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5588 00:23:03.665959 best DQS0 dly(2T, 0.5T) = (0, 10)
5589 00:23:03.669147 best DQS1 dly(2T, 0.5T) = (0, 11)
5590 00:23:03.672097 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5591 00:23:03.675694 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5592 00:23:03.679087 best DQS0 dly(2T, 0.5T) = (0, 10)
5593 00:23:03.681914 best DQS1 dly(2T, 0.5T) = (0, 11)
5594 00:23:03.685526 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5595 00:23:03.688451 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5596 00:23:03.691688 Pre-setting of DQS Precalculation
5597 00:23:03.698436 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5598 00:23:03.698872 ==
5599 00:23:03.701602 Dram Type= 6, Freq= 0, CH_1, rank 0
5600 00:23:03.705040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5601 00:23:03.705512 ==
5602 00:23:03.711815 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5603 00:23:03.715054 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5604 00:23:03.719178 [CA 0] Center 36 (6~67) winsize 62
5605 00:23:03.722202 [CA 1] Center 36 (6~67) winsize 62
5606 00:23:03.725969 [CA 2] Center 34 (4~64) winsize 61
5607 00:23:03.728663 [CA 3] Center 33 (3~64) winsize 62
5608 00:23:03.732203 [CA 4] Center 34 (4~64) winsize 61
5609 00:23:03.735383 [CA 5] Center 33 (3~64) winsize 62
5610 00:23:03.735823
5611 00:23:03.738776 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5612 00:23:03.739236
5613 00:23:03.742258 [CATrainingPosCal] consider 1 rank data
5614 00:23:03.745261 u2DelayCellTimex100 = 270/100 ps
5615 00:23:03.748917 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5616 00:23:03.755224 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5617 00:23:03.758534 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5618 00:23:03.762291 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5619 00:23:03.765190 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5620 00:23:03.768480 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5621 00:23:03.769055
5622 00:23:03.771538 CA PerBit enable=1, Macro0, CA PI delay=33
5623 00:23:03.772085
5624 00:23:03.775252 [CBTSetCACLKResult] CA Dly = 33
5625 00:23:03.778649 CS Dly: 5 (0~36)
5626 00:23:03.779176 ==
5627 00:23:03.781503 Dram Type= 6, Freq= 0, CH_1, rank 1
5628 00:23:03.784776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5629 00:23:03.785202 ==
5630 00:23:03.791435 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5631 00:23:03.794410 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5632 00:23:03.798794 [CA 0] Center 36 (6~67) winsize 62
5633 00:23:03.802521 [CA 1] Center 36 (6~67) winsize 62
5634 00:23:03.805375 [CA 2] Center 34 (4~65) winsize 62
5635 00:23:03.809119 [CA 3] Center 33 (3~64) winsize 62
5636 00:23:03.811903 [CA 4] Center 34 (4~65) winsize 62
5637 00:23:03.815592 [CA 5] Center 33 (3~64) winsize 62
5638 00:23:03.816211
5639 00:23:03.819029 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5640 00:23:03.819698
5641 00:23:03.821970 [CATrainingPosCal] consider 2 rank data
5642 00:23:03.825616 u2DelayCellTimex100 = 270/100 ps
5643 00:23:03.828735 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5644 00:23:03.835329 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5645 00:23:03.838843 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5646 00:23:03.842292 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5647 00:23:03.845586 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5648 00:23:03.848585 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5649 00:23:03.849048
5650 00:23:03.852053 CA PerBit enable=1, Macro0, CA PI delay=33
5651 00:23:03.852643
5652 00:23:03.854954 [CBTSetCACLKResult] CA Dly = 33
5653 00:23:03.858732 CS Dly: 6 (0~39)
5654 00:23:03.859306
5655 00:23:03.861840 ----->DramcWriteLeveling(PI) begin...
5656 00:23:03.862348 ==
5657 00:23:03.865290 Dram Type= 6, Freq= 0, CH_1, rank 0
5658 00:23:03.868477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5659 00:23:03.868907 ==
5660 00:23:03.871371 Write leveling (Byte 0): 25 => 25
5661 00:23:03.875010 Write leveling (Byte 1): 26 => 26
5662 00:23:03.877874 DramcWriteLeveling(PI) end<-----
5663 00:23:03.878513
5664 00:23:03.879016 ==
5665 00:23:03.881395 Dram Type= 6, Freq= 0, CH_1, rank 0
5666 00:23:03.884629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5667 00:23:03.885087 ==
5668 00:23:03.888089 [Gating] SW mode calibration
5669 00:23:03.894845 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5670 00:23:03.901654 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5671 00:23:03.904709 0 14 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
5672 00:23:03.907834 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5673 00:23:03.914458 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5674 00:23:03.917579 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5675 00:23:03.921073 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5676 00:23:03.927377 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5677 00:23:03.931311 0 14 24 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 0)
5678 00:23:03.934311 0 14 28 | B1->B0 | 2a2a 2626 | 0 0 | (1 0) (1 0)
5679 00:23:03.940802 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5680 00:23:03.944495 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5681 00:23:03.947540 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5682 00:23:03.954258 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5683 00:23:03.957395 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5684 00:23:03.960595 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5685 00:23:03.967426 0 15 24 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
5686 00:23:03.970424 0 15 28 | B1->B0 | 3030 3636 | 0 0 | (0 0) (0 0)
5687 00:23:03.974124 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5688 00:23:03.980244 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5689 00:23:03.983713 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5690 00:23:03.986916 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5691 00:23:03.993679 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5692 00:23:03.996919 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5693 00:23:04.000370 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5694 00:23:04.006788 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5695 00:23:04.010273 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5696 00:23:04.013408 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5697 00:23:04.020231 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5698 00:23:04.023145 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5699 00:23:04.026764 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5700 00:23:04.033196 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5701 00:23:04.036365 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5702 00:23:04.040041 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5703 00:23:04.046637 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5704 00:23:04.049634 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5705 00:23:04.053327 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5706 00:23:04.059865 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5707 00:23:04.062744 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5708 00:23:04.066248 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5709 00:23:04.073060 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5710 00:23:04.076200 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5711 00:23:04.079794 Total UI for P1: 0, mck2ui 16
5712 00:23:04.082750 best dqsien dly found for B0: ( 1, 2, 26)
5713 00:23:04.085870 Total UI for P1: 0, mck2ui 16
5714 00:23:04.089350 best dqsien dly found for B1: ( 1, 2, 26)
5715 00:23:04.092811 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5716 00:23:04.095760 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5717 00:23:04.096262
5718 00:23:04.099176 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5719 00:23:04.102648 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5720 00:23:04.105388 [Gating] SW calibration Done
5721 00:23:04.105814 ==
5722 00:23:04.108719 Dram Type= 6, Freq= 0, CH_1, rank 0
5723 00:23:04.115789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5724 00:23:04.116221 ==
5725 00:23:04.116554 RX Vref Scan: 0
5726 00:23:04.116868
5727 00:23:04.118929 RX Vref 0 -> 0, step: 1
5728 00:23:04.119354
5729 00:23:04.122067 RX Delay -80 -> 252, step: 8
5730 00:23:04.125488 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5731 00:23:04.128525 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5732 00:23:04.132184 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5733 00:23:04.135684 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5734 00:23:04.141975 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5735 00:23:04.145122 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5736 00:23:04.148622 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5737 00:23:04.151848 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5738 00:23:04.154979 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5739 00:23:04.161428 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5740 00:23:04.164640 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5741 00:23:04.168014 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5742 00:23:04.171437 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5743 00:23:04.174277 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5744 00:23:04.177620 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5745 00:23:04.184252 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5746 00:23:04.184733 ==
5747 00:23:04.188137 Dram Type= 6, Freq= 0, CH_1, rank 0
5748 00:23:04.191012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5749 00:23:04.191389 ==
5750 00:23:04.191736 DQS Delay:
5751 00:23:04.194532 DQS0 = 0, DQS1 = 0
5752 00:23:04.194987 DQM Delay:
5753 00:23:04.197873 DQM0 = 100, DQM1 = 92
5754 00:23:04.198366 DQ Delay:
5755 00:23:04.201334 DQ0 =103, DQ1 =95, DQ2 =95, DQ3 =95
5756 00:23:04.204462 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5757 00:23:04.207524 DQ8 =83, DQ9 =83, DQ10 =91, DQ11 =83
5758 00:23:04.211381 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5759 00:23:04.211807
5760 00:23:04.212164
5761 00:23:04.212545 ==
5762 00:23:04.214644 Dram Type= 6, Freq= 0, CH_1, rank 0
5763 00:23:04.220426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5764 00:23:04.220889 ==
5765 00:23:04.221242
5766 00:23:04.221555
5767 00:23:04.221874 TX Vref Scan disable
5768 00:23:04.224571 == TX Byte 0 ==
5769 00:23:04.227662 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5770 00:23:04.233976 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5771 00:23:04.234485 == TX Byte 1 ==
5772 00:23:04.237142 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5773 00:23:04.243738 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5774 00:23:04.244213 ==
5775 00:23:04.247174 Dram Type= 6, Freq= 0, CH_1, rank 0
5776 00:23:04.250695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5777 00:23:04.251124 ==
5778 00:23:04.251477
5779 00:23:04.251903
5780 00:23:04.253579 TX Vref Scan disable
5781 00:23:04.254019 == TX Byte 0 ==
5782 00:23:04.260289 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5783 00:23:04.263448 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5784 00:23:04.266890 == TX Byte 1 ==
5785 00:23:04.270399 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5786 00:23:04.273687 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5787 00:23:04.274148
5788 00:23:04.274633 [DATLAT]
5789 00:23:04.276670 Freq=933, CH1 RK0
5790 00:23:04.277129
5791 00:23:04.280271 DATLAT Default: 0xd
5792 00:23:04.280877 0, 0xFFFF, sum = 0
5793 00:23:04.283712 1, 0xFFFF, sum = 0
5794 00:23:04.284183 2, 0xFFFF, sum = 0
5795 00:23:04.286926 3, 0xFFFF, sum = 0
5796 00:23:04.287373 4, 0xFFFF, sum = 0
5797 00:23:04.290204 5, 0xFFFF, sum = 0
5798 00:23:04.290665 6, 0xFFFF, sum = 0
5799 00:23:04.293389 7, 0xFFFF, sum = 0
5800 00:23:04.293838 8, 0xFFFF, sum = 0
5801 00:23:04.296523 9, 0xFFFF, sum = 0
5802 00:23:04.296956 10, 0x0, sum = 1
5803 00:23:04.300167 11, 0x0, sum = 2
5804 00:23:04.300621 12, 0x0, sum = 3
5805 00:23:04.303279 13, 0x0, sum = 4
5806 00:23:04.303714 best_step = 11
5807 00:23:04.304239
5808 00:23:04.304613 ==
5809 00:23:04.306575 Dram Type= 6, Freq= 0, CH_1, rank 0
5810 00:23:04.310216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5811 00:23:04.313324 ==
5812 00:23:04.313784 RX Vref Scan: 1
5813 00:23:04.314349
5814 00:23:04.316293 RX Vref 0 -> 0, step: 1
5815 00:23:04.316731
5816 00:23:04.319834 RX Delay -61 -> 252, step: 4
5817 00:23:04.320274
5818 00:23:04.323269 Set Vref, RX VrefLevel [Byte0]: 48
5819 00:23:04.326224 [Byte1]: 54
5820 00:23:04.326625
5821 00:23:04.329252 Final RX Vref Byte 0 = 48 to rank0
5822 00:23:04.332876 Final RX Vref Byte 1 = 54 to rank0
5823 00:23:04.336443 Final RX Vref Byte 0 = 48 to rank1
5824 00:23:04.339594 Final RX Vref Byte 1 = 54 to rank1==
5825 00:23:04.342616 Dram Type= 6, Freq= 0, CH_1, rank 0
5826 00:23:04.346006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5827 00:23:04.346511 ==
5828 00:23:04.349456 DQS Delay:
5829 00:23:04.349946 DQS0 = 0, DQS1 = 0
5830 00:23:04.350464 DQM Delay:
5831 00:23:04.352313 DQM0 = 101, DQM1 = 94
5832 00:23:04.352852 DQ Delay:
5833 00:23:04.355674 DQ0 =106, DQ1 =96, DQ2 =94, DQ3 =98
5834 00:23:04.359393 DQ4 =100, DQ5 =112, DQ6 =108, DQ7 =98
5835 00:23:04.362327 DQ8 =82, DQ9 =86, DQ10 =92, DQ11 =84
5836 00:23:04.365369 DQ12 =102, DQ13 =100, DQ14 =102, DQ15 =106
5837 00:23:04.369097
5838 00:23:04.369518
5839 00:23:04.375714 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f0e, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 412 ps
5840 00:23:04.379156 CH1 RK0: MR19=505, MR18=1F0E
5841 00:23:04.385686 CH1_RK0: MR19=0x505, MR18=0x1F0E, DQSOSC=412, MR23=63, INC=63, DEC=42
5842 00:23:04.386114
5843 00:23:04.388634 ----->DramcWriteLeveling(PI) begin...
5844 00:23:04.389064 ==
5845 00:23:04.392151 Dram Type= 6, Freq= 0, CH_1, rank 1
5846 00:23:04.395604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5847 00:23:04.396036 ==
5848 00:23:04.398496 Write leveling (Byte 0): 27 => 27
5849 00:23:04.401789 Write leveling (Byte 1): 30 => 30
5850 00:23:04.405444 DramcWriteLeveling(PI) end<-----
5851 00:23:04.405871
5852 00:23:04.406243 ==
5853 00:23:04.408311 Dram Type= 6, Freq= 0, CH_1, rank 1
5854 00:23:04.411735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5855 00:23:04.412165 ==
5856 00:23:04.415005 [Gating] SW mode calibration
5857 00:23:04.421742 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5858 00:23:04.428766 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5859 00:23:04.431597 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5860 00:23:04.438247 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5861 00:23:04.441784 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5862 00:23:04.444695 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5863 00:23:04.451500 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5864 00:23:04.454589 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5865 00:23:04.457986 0 14 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5866 00:23:04.464567 0 14 28 | B1->B0 | 2929 2d2d | 0 0 | (1 1) (1 0)
5867 00:23:04.468142 0 15 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5868 00:23:04.471198 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5869 00:23:04.477768 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5870 00:23:04.480924 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5871 00:23:04.484188 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5872 00:23:04.491074 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5873 00:23:04.494206 0 15 24 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
5874 00:23:04.497629 0 15 28 | B1->B0 | 3b3b 3535 | 0 0 | (1 1) (1 1)
5875 00:23:04.500725 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5876 00:23:04.507399 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5877 00:23:04.510824 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5878 00:23:04.514563 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5879 00:23:04.520874 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5880 00:23:04.524168 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5881 00:23:04.527328 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5882 00:23:04.534264 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5883 00:23:04.537543 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5884 00:23:04.544022 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5885 00:23:04.547121 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5886 00:23:04.550728 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5887 00:23:04.553559 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5888 00:23:04.560150 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5889 00:23:04.563862 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5890 00:23:04.569922 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5891 00:23:04.573241 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5892 00:23:04.576229 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5893 00:23:04.583439 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5894 00:23:04.586750 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5895 00:23:04.589782 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5896 00:23:04.596415 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5897 00:23:04.599540 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5898 00:23:04.602892 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5899 00:23:04.606573 Total UI for P1: 0, mck2ui 16
5900 00:23:04.609566 best dqsien dly found for B1: ( 1, 2, 24)
5901 00:23:04.613002 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5902 00:23:04.616407 Total UI for P1: 0, mck2ui 16
5903 00:23:04.619726 best dqsien dly found for B0: ( 1, 2, 26)
5904 00:23:04.626485 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5905 00:23:04.629864 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5906 00:23:04.630340
5907 00:23:04.633265 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5908 00:23:04.636371 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5909 00:23:04.639206 [Gating] SW calibration Done
5910 00:23:04.639640 ==
5911 00:23:04.642491 Dram Type= 6, Freq= 0, CH_1, rank 1
5912 00:23:04.646037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5913 00:23:04.646530 ==
5914 00:23:04.649526 RX Vref Scan: 0
5915 00:23:04.649967
5916 00:23:04.650335 RX Vref 0 -> 0, step: 1
5917 00:23:04.650673
5918 00:23:04.652694 RX Delay -80 -> 252, step: 8
5919 00:23:04.655611 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5920 00:23:04.662342 iDelay=208, Bit 1, Center 91 (0 ~ 183) 184
5921 00:23:04.665841 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5922 00:23:04.668897 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5923 00:23:04.672613 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5924 00:23:04.675437 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5925 00:23:04.679203 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5926 00:23:04.685383 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5927 00:23:04.689147 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5928 00:23:04.692199 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5929 00:23:04.695445 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5930 00:23:04.698597 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5931 00:23:04.705191 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5932 00:23:04.708772 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5933 00:23:04.711836 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5934 00:23:04.715501 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5935 00:23:04.715950 ==
5936 00:23:04.718408 Dram Type= 6, Freq= 0, CH_1, rank 1
5937 00:23:04.722012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5938 00:23:04.722490 ==
5939 00:23:04.725290 DQS Delay:
5940 00:23:04.725906 DQS0 = 0, DQS1 = 0
5941 00:23:04.728678 DQM Delay:
5942 00:23:04.729245 DQM0 = 99, DQM1 = 90
5943 00:23:04.729696 DQ Delay:
5944 00:23:04.731715 DQ0 =103, DQ1 =91, DQ2 =91, DQ3 =99
5945 00:23:04.735352 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5946 00:23:04.738216 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5947 00:23:04.741570 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =99
5948 00:23:04.745180
5949 00:23:04.745630
5950 00:23:04.746064 ==
5951 00:23:04.748575 Dram Type= 6, Freq= 0, CH_1, rank 1
5952 00:23:04.751380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5953 00:23:04.751819 ==
5954 00:23:04.752152
5955 00:23:04.752492
5956 00:23:04.754668 TX Vref Scan disable
5957 00:23:04.755102 == TX Byte 0 ==
5958 00:23:04.761451 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5959 00:23:04.764500 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5960 00:23:04.765114 == TX Byte 1 ==
5961 00:23:04.771325 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5962 00:23:04.774792 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5963 00:23:04.775223 ==
5964 00:23:04.777913 Dram Type= 6, Freq= 0, CH_1, rank 1
5965 00:23:04.780933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5966 00:23:04.781450 ==
5967 00:23:04.781824
5968 00:23:04.782135
5969 00:23:04.784420 TX Vref Scan disable
5970 00:23:04.787559 == TX Byte 0 ==
5971 00:23:04.791200 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5972 00:23:04.794217 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5973 00:23:04.798014 == TX Byte 1 ==
5974 00:23:04.800705 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5975 00:23:04.804027 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5976 00:23:04.807506
5977 00:23:04.807950 [DATLAT]
5978 00:23:04.808280 Freq=933, CH1 RK1
5979 00:23:04.808765
5980 00:23:04.810835 DATLAT Default: 0xb
5981 00:23:04.811270 0, 0xFFFF, sum = 0
5982 00:23:04.814288 1, 0xFFFF, sum = 0
5983 00:23:04.814752 2, 0xFFFF, sum = 0
5984 00:23:04.817114 3, 0xFFFF, sum = 0
5985 00:23:04.817559 4, 0xFFFF, sum = 0
5986 00:23:04.821217 5, 0xFFFF, sum = 0
5987 00:23:04.824339 6, 0xFFFF, sum = 0
5988 00:23:04.824775 7, 0xFFFF, sum = 0
5989 00:23:04.827277 8, 0xFFFF, sum = 0
5990 00:23:04.827705 9, 0xFFFF, sum = 0
5991 00:23:04.830716 10, 0x0, sum = 1
5992 00:23:04.831160 11, 0x0, sum = 2
5993 00:23:04.831509 12, 0x0, sum = 3
5994 00:23:04.833899 13, 0x0, sum = 4
5995 00:23:04.834511 best_step = 11
5996 00:23:04.834968
5997 00:23:04.837354 ==
5998 00:23:04.837928 Dram Type= 6, Freq= 0, CH_1, rank 1
5999 00:23:04.844088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6000 00:23:04.844541 ==
6001 00:23:04.844873 RX Vref Scan: 0
6002 00:23:04.845285
6003 00:23:04.847306 RX Vref 0 -> 0, step: 1
6004 00:23:04.847734
6005 00:23:04.850278 RX Delay -61 -> 252, step: 4
6006 00:23:04.857336 iDelay=207, Bit 0, Center 106 (19 ~ 194) 176
6007 00:23:04.860159 iDelay=207, Bit 1, Center 94 (7 ~ 182) 176
6008 00:23:04.863707 iDelay=207, Bit 2, Center 88 (-1 ~ 178) 180
6009 00:23:04.866870 iDelay=207, Bit 3, Center 98 (15 ~ 182) 168
6010 00:23:04.870479 iDelay=207, Bit 4, Center 98 (7 ~ 190) 184
6011 00:23:04.873465 iDelay=207, Bit 5, Center 110 (23 ~ 198) 176
6012 00:23:04.880094 iDelay=207, Bit 6, Center 114 (23 ~ 206) 184
6013 00:23:04.883670 iDelay=207, Bit 7, Center 98 (7 ~ 190) 184
6014 00:23:04.886659 iDelay=207, Bit 8, Center 82 (-9 ~ 174) 184
6015 00:23:04.889695 iDelay=207, Bit 9, Center 84 (-5 ~ 174) 180
6016 00:23:04.893234 iDelay=207, Bit 10, Center 92 (-1 ~ 186) 188
6017 00:23:04.899761 iDelay=207, Bit 11, Center 82 (-9 ~ 174) 184
6018 00:23:04.903526 iDelay=207, Bit 12, Center 100 (7 ~ 194) 188
6019 00:23:04.906502 iDelay=207, Bit 13, Center 100 (7 ~ 194) 188
6020 00:23:04.909583 iDelay=207, Bit 14, Center 98 (7 ~ 190) 184
6021 00:23:04.913021 iDelay=207, Bit 15, Center 102 (11 ~ 194) 184
6022 00:23:04.913572 ==
6023 00:23:04.916650 Dram Type= 6, Freq= 0, CH_1, rank 1
6024 00:23:04.922765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6025 00:23:04.923269 ==
6026 00:23:04.923610 DQS Delay:
6027 00:23:04.926408 DQS0 = 0, DQS1 = 0
6028 00:23:04.926839 DQM Delay:
6029 00:23:04.927220 DQM0 = 100, DQM1 = 92
6030 00:23:04.929531 DQ Delay:
6031 00:23:04.932835 DQ0 =106, DQ1 =94, DQ2 =88, DQ3 =98
6032 00:23:04.936158 DQ4 =98, DQ5 =110, DQ6 =114, DQ7 =98
6033 00:23:04.939525 DQ8 =82, DQ9 =84, DQ10 =92, DQ11 =82
6034 00:23:04.942874 DQ12 =100, DQ13 =100, DQ14 =98, DQ15 =102
6035 00:23:04.943379
6036 00:23:04.943723
6037 00:23:04.949266 [DQSOSCAuto] RK1, (LSB)MR18= 0xb05, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 418 ps
6038 00:23:04.952917 CH1 RK1: MR19=505, MR18=B05
6039 00:23:04.959291 CH1_RK1: MR19=0x505, MR18=0xB05, DQSOSC=418, MR23=63, INC=62, DEC=41
6040 00:23:04.962397 [RxdqsGatingPostProcess] freq 933
6041 00:23:04.969001 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6042 00:23:04.969541 best DQS0 dly(2T, 0.5T) = (0, 10)
6043 00:23:04.972383 best DQS1 dly(2T, 0.5T) = (0, 10)
6044 00:23:04.975955 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6045 00:23:04.979021 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6046 00:23:04.982638 best DQS0 dly(2T, 0.5T) = (0, 10)
6047 00:23:04.985730 best DQS1 dly(2T, 0.5T) = (0, 10)
6048 00:23:04.989419 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6049 00:23:04.992330 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6050 00:23:04.995454 Pre-setting of DQS Precalculation
6051 00:23:05.002407 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6052 00:23:05.009053 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6053 00:23:05.015276 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6054 00:23:05.015994
6055 00:23:05.016590
6056 00:23:05.018578 [Calibration Summary] 1866 Mbps
6057 00:23:05.019089 CH 0, Rank 0
6058 00:23:05.022285 SW Impedance : PASS
6059 00:23:05.025093 DUTY Scan : NO K
6060 00:23:05.025633 ZQ Calibration : PASS
6061 00:23:05.028255 Jitter Meter : NO K
6062 00:23:05.031958 CBT Training : PASS
6063 00:23:05.032520 Write leveling : PASS
6064 00:23:05.035415 RX DQS gating : PASS
6065 00:23:05.035976 RX DQ/DQS(RDDQC) : PASS
6066 00:23:05.038281 TX DQ/DQS : PASS
6067 00:23:05.041691 RX DATLAT : PASS
6068 00:23:05.042479 RX DQ/DQS(Engine): PASS
6069 00:23:05.045127 TX OE : NO K
6070 00:23:05.045653 All Pass.
6071 00:23:05.046128
6072 00:23:05.048201 CH 0, Rank 1
6073 00:23:05.048637 SW Impedance : PASS
6074 00:23:05.051756 DUTY Scan : NO K
6075 00:23:05.055133 ZQ Calibration : PASS
6076 00:23:05.055595 Jitter Meter : NO K
6077 00:23:05.058247 CBT Training : PASS
6078 00:23:05.061866 Write leveling : PASS
6079 00:23:05.062510 RX DQS gating : PASS
6080 00:23:05.064979 RX DQ/DQS(RDDQC) : PASS
6081 00:23:05.068186 TX DQ/DQS : PASS
6082 00:23:05.068622 RX DATLAT : PASS
6083 00:23:05.071531 RX DQ/DQS(Engine): PASS
6084 00:23:05.074709 TX OE : NO K
6085 00:23:05.075287 All Pass.
6086 00:23:05.075791
6087 00:23:05.076246 CH 1, Rank 0
6088 00:23:05.078203 SW Impedance : PASS
6089 00:23:05.081800 DUTY Scan : NO K
6090 00:23:05.082263 ZQ Calibration : PASS
6091 00:23:05.084610 Jitter Meter : NO K
6092 00:23:05.088079 CBT Training : PASS
6093 00:23:05.088495 Write leveling : PASS
6094 00:23:05.091724 RX DQS gating : PASS
6095 00:23:05.094796 RX DQ/DQS(RDDQC) : PASS
6096 00:23:05.095213 TX DQ/DQS : PASS
6097 00:23:05.098401 RX DATLAT : PASS
6098 00:23:05.098819 RX DQ/DQS(Engine): PASS
6099 00:23:05.101486 TX OE : NO K
6100 00:23:05.102006 All Pass.
6101 00:23:05.102499
6102 00:23:05.104439 CH 1, Rank 1
6103 00:23:05.108083 SW Impedance : PASS
6104 00:23:05.108722 DUTY Scan : NO K
6105 00:23:05.111367 ZQ Calibration : PASS
6106 00:23:05.112032 Jitter Meter : NO K
6107 00:23:05.114713 CBT Training : PASS
6108 00:23:05.118015 Write leveling : PASS
6109 00:23:05.118504 RX DQS gating : PASS
6110 00:23:05.121525 RX DQ/DQS(RDDQC) : PASS
6111 00:23:05.124484 TX DQ/DQS : PASS
6112 00:23:05.124937 RX DATLAT : PASS
6113 00:23:05.128087 RX DQ/DQS(Engine): PASS
6114 00:23:05.131205 TX OE : NO K
6115 00:23:05.131624 All Pass.
6116 00:23:05.131950
6117 00:23:05.134147 DramC Write-DBI off
6118 00:23:05.134669 PER_BANK_REFRESH: Hybrid Mode
6119 00:23:05.137945 TX_TRACKING: ON
6120 00:23:05.147885 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6121 00:23:05.150863 [FAST_K] Save calibration result to emmc
6122 00:23:05.153960 dramc_set_vcore_voltage set vcore to 650000
6123 00:23:05.154493 Read voltage for 400, 6
6124 00:23:05.157670 Vio18 = 0
6125 00:23:05.158129 Vcore = 650000
6126 00:23:05.158520 Vdram = 0
6127 00:23:05.161008 Vddq = 0
6128 00:23:05.161422 Vmddr = 0
6129 00:23:05.167389 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6130 00:23:05.170790 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6131 00:23:05.174029 MEM_TYPE=3, freq_sel=20
6132 00:23:05.177024 sv_algorithm_assistance_LP4_800
6133 00:23:05.180751 ============ PULL DRAM RESETB DOWN ============
6134 00:23:05.183898 ========== PULL DRAM RESETB DOWN end =========
6135 00:23:05.190681 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6136 00:23:05.193800 ===================================
6137 00:23:05.194357 LPDDR4 DRAM CONFIGURATION
6138 00:23:05.196828 ===================================
6139 00:23:05.200175 EX_ROW_EN[0] = 0x0
6140 00:23:05.203275 EX_ROW_EN[1] = 0x0
6141 00:23:05.203764 LP4Y_EN = 0x0
6142 00:23:05.206967 WORK_FSP = 0x0
6143 00:23:05.207489 WL = 0x2
6144 00:23:05.209907 RL = 0x2
6145 00:23:05.210394 BL = 0x2
6146 00:23:05.213603 RPST = 0x0
6147 00:23:05.214045 RD_PRE = 0x0
6148 00:23:05.216622 WR_PRE = 0x1
6149 00:23:05.217113 WR_PST = 0x0
6150 00:23:05.220168 DBI_WR = 0x0
6151 00:23:05.220847 DBI_RD = 0x0
6152 00:23:05.223459 OTF = 0x1
6153 00:23:05.226645 ===================================
6154 00:23:05.230128 ===================================
6155 00:23:05.230589 ANA top config
6156 00:23:05.233150 ===================================
6157 00:23:05.236885 DLL_ASYNC_EN = 0
6158 00:23:05.239858 ALL_SLAVE_EN = 1
6159 00:23:05.242800 NEW_RANK_MODE = 1
6160 00:23:05.243264 DLL_IDLE_MODE = 1
6161 00:23:05.246448 LP45_APHY_COMB_EN = 1
6162 00:23:05.249546 TX_ODT_DIS = 1
6163 00:23:05.253094 NEW_8X_MODE = 1
6164 00:23:05.255981 ===================================
6165 00:23:05.259801 ===================================
6166 00:23:05.262639 data_rate = 800
6167 00:23:05.265814 CKR = 1
6168 00:23:05.266449 DQ_P2S_RATIO = 4
6169 00:23:05.269117 ===================================
6170 00:23:05.272646 CA_P2S_RATIO = 4
6171 00:23:05.276198 DQ_CA_OPEN = 0
6172 00:23:05.279037 DQ_SEMI_OPEN = 1
6173 00:23:05.282820 CA_SEMI_OPEN = 1
6174 00:23:05.286204 CA_FULL_RATE = 0
6175 00:23:05.286749 DQ_CKDIV4_EN = 0
6176 00:23:05.289188 CA_CKDIV4_EN = 1
6177 00:23:05.292763 CA_PREDIV_EN = 0
6178 00:23:05.295880 PH8_DLY = 0
6179 00:23:05.299199 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6180 00:23:05.302624 DQ_AAMCK_DIV = 0
6181 00:23:05.303062 CA_AAMCK_DIV = 0
6182 00:23:05.305673 CA_ADMCK_DIV = 4
6183 00:23:05.309205 DQ_TRACK_CA_EN = 0
6184 00:23:05.311703 CA_PICK = 800
6185 00:23:05.315514 CA_MCKIO = 400
6186 00:23:05.318650 MCKIO_SEMI = 400
6187 00:23:05.322363 PLL_FREQ = 3016
6188 00:23:05.325231 DQ_UI_PI_RATIO = 32
6189 00:23:05.325695 CA_UI_PI_RATIO = 32
6190 00:23:05.328904 ===================================
6191 00:23:05.331888 ===================================
6192 00:23:05.335416 memory_type:LPDDR4
6193 00:23:05.338463 GP_NUM : 10
6194 00:23:05.338890 SRAM_EN : 1
6195 00:23:05.341513 MD32_EN : 0
6196 00:23:05.345135 ===================================
6197 00:23:05.348393 [ANA_INIT] >>>>>>>>>>>>>>
6198 00:23:05.352009 <<<<<< [CONFIGURE PHASE]: ANA_TX
6199 00:23:05.354765 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6200 00:23:05.358286 ===================================
6201 00:23:05.358712 data_rate = 800,PCW = 0X7400
6202 00:23:05.361740 ===================================
6203 00:23:05.364897 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6204 00:23:05.371686 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6205 00:23:05.384660 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6206 00:23:05.387581 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6207 00:23:05.391143 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6208 00:23:05.394425 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6209 00:23:05.397576 [ANA_INIT] flow start
6210 00:23:05.398113 [ANA_INIT] PLL >>>>>>>>
6211 00:23:05.400671 [ANA_INIT] PLL <<<<<<<<
6212 00:23:05.404142 [ANA_INIT] MIDPI >>>>>>>>
6213 00:23:05.407047 [ANA_INIT] MIDPI <<<<<<<<
6214 00:23:05.407481 [ANA_INIT] DLL >>>>>>>>
6215 00:23:05.410688 [ANA_INIT] flow end
6216 00:23:05.414133 ============ LP4 DIFF to SE enter ============
6217 00:23:05.417267 ============ LP4 DIFF to SE exit ============
6218 00:23:05.420411 [ANA_INIT] <<<<<<<<<<<<<
6219 00:23:05.423804 [Flow] Enable top DCM control >>>>>
6220 00:23:05.426946 [Flow] Enable top DCM control <<<<<
6221 00:23:05.430156 Enable DLL master slave shuffle
6222 00:23:05.437115 ==============================================================
6223 00:23:05.437539 Gating Mode config
6224 00:23:05.443938 ==============================================================
6225 00:23:05.444357 Config description:
6226 00:23:05.453600 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6227 00:23:05.460299 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6228 00:23:05.466381 SELPH_MODE 0: By rank 1: By Phase
6229 00:23:05.473376 ==============================================================
6230 00:23:05.473877 GAT_TRACK_EN = 0
6231 00:23:05.476455 RX_GATING_MODE = 2
6232 00:23:05.479729 RX_GATING_TRACK_MODE = 2
6233 00:23:05.483498 SELPH_MODE = 1
6234 00:23:05.486415 PICG_EARLY_EN = 1
6235 00:23:05.489966 VALID_LAT_VALUE = 1
6236 00:23:05.496462 ==============================================================
6237 00:23:05.499523 Enter into Gating configuration >>>>
6238 00:23:05.503093 Exit from Gating configuration <<<<
6239 00:23:05.506025 Enter into DVFS_PRE_config >>>>>
6240 00:23:05.515863 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6241 00:23:05.519412 Exit from DVFS_PRE_config <<<<<
6242 00:23:05.522428 Enter into PICG configuration >>>>
6243 00:23:05.525751 Exit from PICG configuration <<<<
6244 00:23:05.528962 [RX_INPUT] configuration >>>>>
6245 00:23:05.532452 [RX_INPUT] configuration <<<<<
6246 00:23:05.535707 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6247 00:23:05.542519 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6248 00:23:05.549115 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6249 00:23:05.552715 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6250 00:23:05.558744 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6251 00:23:05.565424 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6252 00:23:05.568973 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6253 00:23:05.575921 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6254 00:23:05.578788 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6255 00:23:05.581975 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6256 00:23:05.585567 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6257 00:23:05.592104 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6258 00:23:05.595510 ===================================
6259 00:23:05.595929 LPDDR4 DRAM CONFIGURATION
6260 00:23:05.598460 ===================================
6261 00:23:05.601423 EX_ROW_EN[0] = 0x0
6262 00:23:05.605114 EX_ROW_EN[1] = 0x0
6263 00:23:05.605572 LP4Y_EN = 0x0
6264 00:23:05.608610 WORK_FSP = 0x0
6265 00:23:05.609034 WL = 0x2
6266 00:23:05.611689 RL = 0x2
6267 00:23:05.612128 BL = 0x2
6268 00:23:05.615063 RPST = 0x0
6269 00:23:05.615576 RD_PRE = 0x0
6270 00:23:05.618049 WR_PRE = 0x1
6271 00:23:05.618507 WR_PST = 0x0
6272 00:23:05.621238 DBI_WR = 0x0
6273 00:23:05.621668 DBI_RD = 0x0
6274 00:23:05.624927 OTF = 0x1
6275 00:23:05.628462 ===================================
6276 00:23:05.631262 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6277 00:23:05.634994 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6278 00:23:05.641158 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6279 00:23:05.644857 ===================================
6280 00:23:05.647746 LPDDR4 DRAM CONFIGURATION
6281 00:23:05.651218 ===================================
6282 00:23:05.651616 EX_ROW_EN[0] = 0x10
6283 00:23:05.654660 EX_ROW_EN[1] = 0x0
6284 00:23:05.655087 LP4Y_EN = 0x0
6285 00:23:05.657836 WORK_FSP = 0x0
6286 00:23:05.658308 WL = 0x2
6287 00:23:05.661132 RL = 0x2
6288 00:23:05.661561 BL = 0x2
6289 00:23:05.664370 RPST = 0x0
6290 00:23:05.664792 RD_PRE = 0x0
6291 00:23:05.667731 WR_PRE = 0x1
6292 00:23:05.668152 WR_PST = 0x0
6293 00:23:05.671010 DBI_WR = 0x0
6294 00:23:05.671430 DBI_RD = 0x0
6295 00:23:05.674539 OTF = 0x1
6296 00:23:05.678018 ===================================
6297 00:23:05.684029 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6298 00:23:05.687585 nWR fixed to 30
6299 00:23:05.690879 [ModeRegInit_LP4] CH0 RK0
6300 00:23:05.691420 [ModeRegInit_LP4] CH0 RK1
6301 00:23:05.694349 [ModeRegInit_LP4] CH1 RK0
6302 00:23:05.697855 [ModeRegInit_LP4] CH1 RK1
6303 00:23:05.698325 match AC timing 19
6304 00:23:05.704452 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6305 00:23:05.707296 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6306 00:23:05.710438 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6307 00:23:05.717628 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6308 00:23:05.720446 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6309 00:23:05.720870 ==
6310 00:23:05.723913 Dram Type= 6, Freq= 0, CH_0, rank 0
6311 00:23:05.726751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6312 00:23:05.727353 ==
6313 00:23:05.733905 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6314 00:23:05.740404 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6315 00:23:05.743541 [CA 0] Center 36 (8~64) winsize 57
6316 00:23:05.747181 [CA 1] Center 36 (8~64) winsize 57
6317 00:23:05.750154 [CA 2] Center 36 (8~64) winsize 57
6318 00:23:05.753209 [CA 3] Center 36 (8~64) winsize 57
6319 00:23:05.756768 [CA 4] Center 36 (8~64) winsize 57
6320 00:23:05.759815 [CA 5] Center 36 (8~64) winsize 57
6321 00:23:05.760242
6322 00:23:05.763425 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6323 00:23:05.763879
6324 00:23:05.766932 [CATrainingPosCal] consider 1 rank data
6325 00:23:05.769829 u2DelayCellTimex100 = 270/100 ps
6326 00:23:05.773460 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6327 00:23:05.776770 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6328 00:23:05.779760 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6329 00:23:05.783512 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6330 00:23:05.786351 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6331 00:23:05.789810 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6332 00:23:05.790296
6333 00:23:05.796070 CA PerBit enable=1, Macro0, CA PI delay=36
6334 00:23:05.796491
6335 00:23:05.796819 [CBTSetCACLKResult] CA Dly = 36
6336 00:23:05.799586 CS Dly: 1 (0~32)
6337 00:23:05.800006 ==
6338 00:23:05.802844 Dram Type= 6, Freq= 0, CH_0, rank 1
6339 00:23:05.806281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6340 00:23:05.806706 ==
6341 00:23:05.812904 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6342 00:23:05.819584 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6343 00:23:05.822629 [CA 0] Center 36 (8~64) winsize 57
6344 00:23:05.826056 [CA 1] Center 36 (8~64) winsize 57
6345 00:23:05.829102 [CA 2] Center 36 (8~64) winsize 57
6346 00:23:05.832672 [CA 3] Center 36 (8~64) winsize 57
6347 00:23:05.833104 [CA 4] Center 36 (8~64) winsize 57
6348 00:23:05.836363 [CA 5] Center 36 (8~64) winsize 57
6349 00:23:05.836792
6350 00:23:05.842338 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6351 00:23:05.842769
6352 00:23:05.846102 [CATrainingPosCal] consider 2 rank data
6353 00:23:05.849013 u2DelayCellTimex100 = 270/100 ps
6354 00:23:05.852605 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6355 00:23:05.855638 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6356 00:23:05.859265 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6357 00:23:05.862349 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6358 00:23:05.865254 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6359 00:23:05.868715 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6360 00:23:05.869300
6361 00:23:05.872258 CA PerBit enable=1, Macro0, CA PI delay=36
6362 00:23:05.872812
6363 00:23:05.875403 [CBTSetCACLKResult] CA Dly = 36
6364 00:23:05.879072 CS Dly: 1 (0~32)
6365 00:23:05.879676
6366 00:23:05.881897 ----->DramcWriteLeveling(PI) begin...
6367 00:23:05.882514 ==
6368 00:23:05.885523 Dram Type= 6, Freq= 0, CH_0, rank 0
6369 00:23:05.888758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6370 00:23:05.889338 ==
6371 00:23:05.892118 Write leveling (Byte 0): 40 => 8
6372 00:23:05.895303 Write leveling (Byte 1): 32 => 0
6373 00:23:05.898195 DramcWriteLeveling(PI) end<-----
6374 00:23:05.898837
6375 00:23:05.899369 ==
6376 00:23:05.901523 Dram Type= 6, Freq= 0, CH_0, rank 0
6377 00:23:05.904896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6378 00:23:05.905492 ==
6379 00:23:05.908565 [Gating] SW mode calibration
6380 00:23:05.914611 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6381 00:23:05.921341 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6382 00:23:05.925009 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6383 00:23:05.930911 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6384 00:23:05.934596 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6385 00:23:05.938108 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6386 00:23:05.944647 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6387 00:23:05.947460 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6388 00:23:05.950962 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6389 00:23:05.957382 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6390 00:23:05.960942 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6391 00:23:05.963968 Total UI for P1: 0, mck2ui 16
6392 00:23:05.967531 best dqsien dly found for B0: ( 0, 14, 24)
6393 00:23:05.970444 Total UI for P1: 0, mck2ui 16
6394 00:23:05.973930 best dqsien dly found for B1: ( 0, 14, 24)
6395 00:23:05.976943 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6396 00:23:05.980592 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6397 00:23:05.981179
6398 00:23:05.984124 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6399 00:23:05.990690 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6400 00:23:05.991177 [Gating] SW calibration Done
6401 00:23:05.991583 ==
6402 00:23:05.993599 Dram Type= 6, Freq= 0, CH_0, rank 0
6403 00:23:06.000475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6404 00:23:06.000978 ==
6405 00:23:06.001394 RX Vref Scan: 0
6406 00:23:06.001769
6407 00:23:06.003289 RX Vref 0 -> 0, step: 1
6408 00:23:06.003797
6409 00:23:06.006880 RX Delay -410 -> 252, step: 16
6410 00:23:06.010092 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6411 00:23:06.013418 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6412 00:23:06.019896 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6413 00:23:06.023194 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6414 00:23:06.026773 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6415 00:23:06.030114 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6416 00:23:06.036547 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6417 00:23:06.039915 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6418 00:23:06.042848 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6419 00:23:06.046788 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6420 00:23:06.052852 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6421 00:23:06.056054 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6422 00:23:06.059540 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6423 00:23:06.066442 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6424 00:23:06.069219 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6425 00:23:06.072786 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6426 00:23:06.073225 ==
6427 00:23:06.075886 Dram Type= 6, Freq= 0, CH_0, rank 0
6428 00:23:06.082202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6429 00:23:06.082637 ==
6430 00:23:06.082972 DQS Delay:
6431 00:23:06.085978 DQS0 = 43, DQS1 = 59
6432 00:23:06.086476 DQM Delay:
6433 00:23:06.086813 DQM0 = 10, DQM1 = 11
6434 00:23:06.088899 DQ Delay:
6435 00:23:06.091928 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6436 00:23:06.092012 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6437 00:23:06.094972 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6438 00:23:06.098442 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6439 00:23:06.098525
6440 00:23:06.101512
6441 00:23:06.101594 ==
6442 00:23:06.105115 Dram Type= 6, Freq= 0, CH_0, rank 0
6443 00:23:06.108530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6444 00:23:06.108614 ==
6445 00:23:06.108679
6446 00:23:06.108739
6447 00:23:06.111658 TX Vref Scan disable
6448 00:23:06.111742 == TX Byte 0 ==
6449 00:23:06.115306 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6450 00:23:06.121735 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6451 00:23:06.121819 == TX Byte 1 ==
6452 00:23:06.125103 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6453 00:23:06.131377 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6454 00:23:06.131460 ==
6455 00:23:06.135007 Dram Type= 6, Freq= 0, CH_0, rank 0
6456 00:23:06.138080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6457 00:23:06.138191 ==
6458 00:23:06.138259
6459 00:23:06.138319
6460 00:23:06.141063 TX Vref Scan disable
6461 00:23:06.141146 == TX Byte 0 ==
6462 00:23:06.147915 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6463 00:23:06.151445 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6464 00:23:06.151528 == TX Byte 1 ==
6465 00:23:06.157737 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6466 00:23:06.161412 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6467 00:23:06.161495
6468 00:23:06.161560 [DATLAT]
6469 00:23:06.164406 Freq=400, CH0 RK0
6470 00:23:06.164489
6471 00:23:06.164554 DATLAT Default: 0xf
6472 00:23:06.167461 0, 0xFFFF, sum = 0
6473 00:23:06.167573 1, 0xFFFF, sum = 0
6474 00:23:06.170958 2, 0xFFFF, sum = 0
6475 00:23:06.171042 3, 0xFFFF, sum = 0
6476 00:23:06.174482 4, 0xFFFF, sum = 0
6477 00:23:06.174567 5, 0xFFFF, sum = 0
6478 00:23:06.177140 6, 0xFFFF, sum = 0
6479 00:23:06.180911 7, 0xFFFF, sum = 0
6480 00:23:06.180996 8, 0xFFFF, sum = 0
6481 00:23:06.184341 9, 0xFFFF, sum = 0
6482 00:23:06.184425 10, 0xFFFF, sum = 0
6483 00:23:06.187247 11, 0xFFFF, sum = 0
6484 00:23:06.187334 12, 0xFFFF, sum = 0
6485 00:23:06.190700 13, 0x0, sum = 1
6486 00:23:06.190785 14, 0x0, sum = 2
6487 00:23:06.193767 15, 0x0, sum = 3
6488 00:23:06.193849 16, 0x0, sum = 4
6489 00:23:06.197219 best_step = 14
6490 00:23:06.197300
6491 00:23:06.197386 ==
6492 00:23:06.200882 Dram Type= 6, Freq= 0, CH_0, rank 0
6493 00:23:06.203664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6494 00:23:06.203746 ==
6495 00:23:06.203817 RX Vref Scan: 1
6496 00:23:06.203877
6497 00:23:06.207308 RX Vref 0 -> 0, step: 1
6498 00:23:06.207401
6499 00:23:06.210690 RX Delay -359 -> 252, step: 8
6500 00:23:06.210772
6501 00:23:06.213878 Set Vref, RX VrefLevel [Byte0]: 61
6502 00:23:06.216842 [Byte1]: 49
6503 00:23:06.221167
6504 00:23:06.221255 Final RX Vref Byte 0 = 61 to rank0
6505 00:23:06.224742 Final RX Vref Byte 1 = 49 to rank0
6506 00:23:06.227838 Final RX Vref Byte 0 = 61 to rank1
6507 00:23:06.230723 Final RX Vref Byte 1 = 49 to rank1==
6508 00:23:06.234170 Dram Type= 6, Freq= 0, CH_0, rank 0
6509 00:23:06.240879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6510 00:23:06.241005 ==
6511 00:23:06.241103 DQS Delay:
6512 00:23:06.244217 DQS0 = 48, DQS1 = 60
6513 00:23:06.244385 DQM Delay:
6514 00:23:06.247606 DQM0 = 11, DQM1 = 12
6515 00:23:06.247744 DQ Delay:
6516 00:23:06.250803 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6517 00:23:06.254382 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6518 00:23:06.257544 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6519 00:23:06.260580 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6520 00:23:06.260785
6521 00:23:06.260944
6522 00:23:06.267364 [DQSOSCAuto] RK0, (LSB)MR18= 0xbe81, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 386 ps
6523 00:23:06.270986 CH0 RK0: MR19=C0C, MR18=BE81
6524 00:23:06.277247 CH0_RK0: MR19=0xC0C, MR18=0xBE81, DQSOSC=386, MR23=63, INC=396, DEC=264
6525 00:23:06.277721 ==
6526 00:23:06.280793 Dram Type= 6, Freq= 0, CH_0, rank 1
6527 00:23:06.283945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6528 00:23:06.284378 ==
6529 00:23:06.287662 [Gating] SW mode calibration
6530 00:23:06.293568 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6531 00:23:06.300127 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6532 00:23:06.303362 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6533 00:23:06.310040 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6534 00:23:06.313485 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6535 00:23:06.316629 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6536 00:23:06.323330 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6537 00:23:06.326265 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6538 00:23:06.330087 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6539 00:23:06.336789 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6540 00:23:06.339731 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6541 00:23:06.342768 Total UI for P1: 0, mck2ui 16
6542 00:23:06.346069 best dqsien dly found for B0: ( 0, 14, 24)
6543 00:23:06.349459 Total UI for P1: 0, mck2ui 16
6544 00:23:06.353233 best dqsien dly found for B1: ( 0, 14, 24)
6545 00:23:06.355979 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6546 00:23:06.359545 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6547 00:23:06.360311
6548 00:23:06.362737 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6549 00:23:06.365938 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6550 00:23:06.369755 [Gating] SW calibration Done
6551 00:23:06.370238 ==
6552 00:23:06.372709 Dram Type= 6, Freq= 0, CH_0, rank 1
6553 00:23:06.376393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6554 00:23:06.379547 ==
6555 00:23:06.380004 RX Vref Scan: 0
6556 00:23:06.380461
6557 00:23:06.382551 RX Vref 0 -> 0, step: 1
6558 00:23:06.382985
6559 00:23:06.385732 RX Delay -410 -> 252, step: 16
6560 00:23:06.389284 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6561 00:23:06.392732 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6562 00:23:06.395906 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6563 00:23:06.402585 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6564 00:23:06.405429 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6565 00:23:06.408868 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6566 00:23:06.412388 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6567 00:23:06.418738 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6568 00:23:06.422025 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6569 00:23:06.425300 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6570 00:23:06.428561 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6571 00:23:06.435665 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6572 00:23:06.438669 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6573 00:23:06.441574 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6574 00:23:06.448294 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6575 00:23:06.451733 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6576 00:23:06.452156 ==
6577 00:23:06.455084 Dram Type= 6, Freq= 0, CH_0, rank 1
6578 00:23:06.458308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6579 00:23:06.458791 ==
6580 00:23:06.461591 DQS Delay:
6581 00:23:06.462011 DQS0 = 43, DQS1 = 59
6582 00:23:06.465289 DQM Delay:
6583 00:23:06.465708 DQM0 = 10, DQM1 = 16
6584 00:23:06.466039 DQ Delay:
6585 00:23:06.468328 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6586 00:23:06.471677 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6587 00:23:06.475215 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6588 00:23:06.478571 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6589 00:23:06.478991
6590 00:23:06.479413
6591 00:23:06.479831 ==
6592 00:23:06.481710 Dram Type= 6, Freq= 0, CH_0, rank 1
6593 00:23:06.488454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6594 00:23:06.488912 ==
6595 00:23:06.489244
6596 00:23:06.489580
6597 00:23:06.489909 TX Vref Scan disable
6598 00:23:06.491462 == TX Byte 0 ==
6599 00:23:06.494520 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6600 00:23:06.498210 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6601 00:23:06.501328 == TX Byte 1 ==
6602 00:23:06.504820 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6603 00:23:06.507921 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6604 00:23:06.508397 ==
6605 00:23:06.511300 Dram Type= 6, Freq= 0, CH_0, rank 1
6606 00:23:06.517896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6607 00:23:06.518407 ==
6608 00:23:06.518860
6609 00:23:06.519270
6610 00:23:06.519684 TX Vref Scan disable
6611 00:23:06.521361 == TX Byte 0 ==
6612 00:23:06.524302 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6613 00:23:06.527977 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6614 00:23:06.530670 == TX Byte 1 ==
6615 00:23:06.534229 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6616 00:23:06.537742 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6617 00:23:06.538234
6618 00:23:06.540833 [DATLAT]
6619 00:23:06.541265 Freq=400, CH0 RK1
6620 00:23:06.541713
6621 00:23:06.544144 DATLAT Default: 0xe
6622 00:23:06.544601 0, 0xFFFF, sum = 0
6623 00:23:06.547361 1, 0xFFFF, sum = 0
6624 00:23:06.547816 2, 0xFFFF, sum = 0
6625 00:23:06.551013 3, 0xFFFF, sum = 0
6626 00:23:06.551519 4, 0xFFFF, sum = 0
6627 00:23:06.554047 5, 0xFFFF, sum = 0
6628 00:23:06.554516 6, 0xFFFF, sum = 0
6629 00:23:06.557354 7, 0xFFFF, sum = 0
6630 00:23:06.560483 8, 0xFFFF, sum = 0
6631 00:23:06.560908 9, 0xFFFF, sum = 0
6632 00:23:06.563694 10, 0xFFFF, sum = 0
6633 00:23:06.564252 11, 0xFFFF, sum = 0
6634 00:23:06.567322 12, 0xFFFF, sum = 0
6635 00:23:06.567773 13, 0x0, sum = 1
6636 00:23:06.570774 14, 0x0, sum = 2
6637 00:23:06.571197 15, 0x0, sum = 3
6638 00:23:06.573966 16, 0x0, sum = 4
6639 00:23:06.574425 best_step = 14
6640 00:23:06.574754
6641 00:23:06.575071 ==
6642 00:23:06.576966 Dram Type= 6, Freq= 0, CH_0, rank 1
6643 00:23:06.580617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6644 00:23:06.581036 ==
6645 00:23:06.583522 RX Vref Scan: 0
6646 00:23:06.583964
6647 00:23:06.586614 RX Vref 0 -> 0, step: 1
6648 00:23:06.587031
6649 00:23:06.589897 RX Delay -359 -> 252, step: 8
6650 00:23:06.596816 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6651 00:23:06.599923 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6652 00:23:06.603499 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6653 00:23:06.606481 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6654 00:23:06.613045 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6655 00:23:06.616624 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6656 00:23:06.619572 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6657 00:23:06.623168 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6658 00:23:06.629780 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6659 00:23:06.633265 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6660 00:23:06.636411 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6661 00:23:06.639413 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6662 00:23:06.646197 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6663 00:23:06.649587 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6664 00:23:06.652626 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6665 00:23:06.659334 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6666 00:23:06.659756 ==
6667 00:23:06.662781 Dram Type= 6, Freq= 0, CH_0, rank 1
6668 00:23:06.665671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6669 00:23:06.666092 ==
6670 00:23:06.666484 DQS Delay:
6671 00:23:06.668800 DQS0 = 44, DQS1 = 60
6672 00:23:06.669228 DQM Delay:
6673 00:23:06.672126 DQM0 = 8, DQM1 = 13
6674 00:23:06.672542 DQ Delay:
6675 00:23:06.675696 DQ0 =4, DQ1 =12, DQ2 =4, DQ3 =4
6676 00:23:06.678738 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6677 00:23:06.682282 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6678 00:23:06.685311 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6679 00:23:06.685727
6680 00:23:06.686052
6681 00:23:06.692578 [DQSOSCAuto] RK1, (LSB)MR18= 0xb642, (MSB)MR19= 0xc0c, tDQSOscB0 = 401 ps tDQSOscB1 = 387 ps
6682 00:23:06.695548 CH0 RK1: MR19=C0C, MR18=B642
6683 00:23:06.702424 CH0_RK1: MR19=0xC0C, MR18=0xB642, DQSOSC=387, MR23=63, INC=394, DEC=262
6684 00:23:06.705641 [RxdqsGatingPostProcess] freq 400
6685 00:23:06.712261 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6686 00:23:06.712680 best DQS0 dly(2T, 0.5T) = (0, 10)
6687 00:23:06.715178 best DQS1 dly(2T, 0.5T) = (0, 10)
6688 00:23:06.718770 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6689 00:23:06.721932 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6690 00:23:06.725603 best DQS0 dly(2T, 0.5T) = (0, 10)
6691 00:23:06.728551 best DQS1 dly(2T, 0.5T) = (0, 10)
6692 00:23:06.732252 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6693 00:23:06.735237 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6694 00:23:06.738274 Pre-setting of DQS Precalculation
6695 00:23:06.745028 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6696 00:23:06.745507 ==
6697 00:23:06.748555 Dram Type= 6, Freq= 0, CH_1, rank 0
6698 00:23:06.751524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6699 00:23:06.751986 ==
6700 00:23:06.758076 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6701 00:23:06.761637 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6702 00:23:06.764579 [CA 0] Center 36 (8~64) winsize 57
6703 00:23:06.768074 [CA 1] Center 36 (8~64) winsize 57
6704 00:23:06.771380 [CA 2] Center 36 (8~64) winsize 57
6705 00:23:06.775062 [CA 3] Center 36 (8~64) winsize 57
6706 00:23:06.777942 [CA 4] Center 36 (8~64) winsize 57
6707 00:23:06.781479 [CA 5] Center 36 (8~64) winsize 57
6708 00:23:06.781906
6709 00:23:06.784790 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6710 00:23:06.785312
6711 00:23:06.787896 [CATrainingPosCal] consider 1 rank data
6712 00:23:06.791497 u2DelayCellTimex100 = 270/100 ps
6713 00:23:06.794531 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6714 00:23:06.798186 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6715 00:23:06.804499 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6716 00:23:06.808165 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6717 00:23:06.810858 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6718 00:23:06.814359 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6719 00:23:06.814784
6720 00:23:06.818013 CA PerBit enable=1, Macro0, CA PI delay=36
6721 00:23:06.818477
6722 00:23:06.820857 [CBTSetCACLKResult] CA Dly = 36
6723 00:23:06.821294 CS Dly: 1 (0~32)
6724 00:23:06.824547 ==
6725 00:23:06.824982 Dram Type= 6, Freq= 0, CH_1, rank 1
6726 00:23:06.830553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6727 00:23:06.830993 ==
6728 00:23:06.834124 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6729 00:23:06.840894 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6730 00:23:06.844480 [CA 0] Center 36 (8~64) winsize 57
6731 00:23:06.847499 [CA 1] Center 36 (8~64) winsize 57
6732 00:23:06.851093 [CA 2] Center 36 (8~64) winsize 57
6733 00:23:06.854344 [CA 3] Center 36 (8~64) winsize 57
6734 00:23:06.857673 [CA 4] Center 36 (8~64) winsize 57
6735 00:23:06.860647 [CA 5] Center 36 (8~64) winsize 57
6736 00:23:06.861086
6737 00:23:06.864248 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6738 00:23:06.864695
6739 00:23:06.867372 [CATrainingPosCal] consider 2 rank data
6740 00:23:06.870297 u2DelayCellTimex100 = 270/100 ps
6741 00:23:06.874138 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6742 00:23:06.877099 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6743 00:23:06.880649 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6744 00:23:06.884164 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6745 00:23:06.890424 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6746 00:23:06.893776 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6747 00:23:06.894234
6748 00:23:06.897113 CA PerBit enable=1, Macro0, CA PI delay=36
6749 00:23:06.897875
6750 00:23:06.899901 [CBTSetCACLKResult] CA Dly = 36
6751 00:23:06.900433 CS Dly: 1 (0~32)
6752 00:23:06.900867
6753 00:23:06.903548 ----->DramcWriteLeveling(PI) begin...
6754 00:23:06.904186 ==
6755 00:23:06.906955 Dram Type= 6, Freq= 0, CH_1, rank 0
6756 00:23:06.913651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6757 00:23:06.914148 ==
6758 00:23:06.916411 Write leveling (Byte 0): 40 => 8
6759 00:23:06.919903 Write leveling (Byte 1): 32 => 0
6760 00:23:06.920360 DramcWriteLeveling(PI) end<-----
6761 00:23:06.923319
6762 00:23:06.923752 ==
6763 00:23:06.926703 Dram Type= 6, Freq= 0, CH_1, rank 0
6764 00:23:06.929684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6765 00:23:06.930106 ==
6766 00:23:06.933306 [Gating] SW mode calibration
6767 00:23:06.940013 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6768 00:23:06.942966 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6769 00:23:06.949651 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6770 00:23:06.952743 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6771 00:23:06.956410 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6772 00:23:06.962756 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6773 00:23:06.966335 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6774 00:23:06.969464 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6775 00:23:06.976265 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6776 00:23:06.979129 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6777 00:23:06.982955 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6778 00:23:06.986037 Total UI for P1: 0, mck2ui 16
6779 00:23:06.989349 best dqsien dly found for B0: ( 0, 14, 24)
6780 00:23:06.992871 Total UI for P1: 0, mck2ui 16
6781 00:23:06.995642 best dqsien dly found for B1: ( 0, 14, 24)
6782 00:23:06.999193 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6783 00:23:07.005951 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6784 00:23:07.006563
6785 00:23:07.008683 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6786 00:23:07.011983 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6787 00:23:07.015383 [Gating] SW calibration Done
6788 00:23:07.015806 ==
6789 00:23:07.018688 Dram Type= 6, Freq= 0, CH_1, rank 0
6790 00:23:07.022281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6791 00:23:07.022708 ==
6792 00:23:07.025247 RX Vref Scan: 0
6793 00:23:07.025671
6794 00:23:07.026000 RX Vref 0 -> 0, step: 1
6795 00:23:07.026434
6796 00:23:07.028870 RX Delay -410 -> 252, step: 16
6797 00:23:07.035435 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6798 00:23:07.038588 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6799 00:23:07.041896 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6800 00:23:07.045419 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6801 00:23:07.051856 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6802 00:23:07.054903 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6803 00:23:07.058092 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6804 00:23:07.061260 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6805 00:23:07.068028 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6806 00:23:07.071596 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6807 00:23:07.074455 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6808 00:23:07.078217 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6809 00:23:07.085014 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6810 00:23:07.087923 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6811 00:23:07.091057 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6812 00:23:07.097779 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6813 00:23:07.098360 ==
6814 00:23:07.101101 Dram Type= 6, Freq= 0, CH_1, rank 0
6815 00:23:07.104559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6816 00:23:07.104984 ==
6817 00:23:07.105338 DQS Delay:
6818 00:23:07.107434 DQS0 = 43, DQS1 = 51
6819 00:23:07.107855 DQM Delay:
6820 00:23:07.111209 DQM0 = 12, DQM1 = 14
6821 00:23:07.111629 DQ Delay:
6822 00:23:07.114192 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6823 00:23:07.117690 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6824 00:23:07.120541 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6825 00:23:07.124009 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6826 00:23:07.124435
6827 00:23:07.124764
6828 00:23:07.125072 ==
6829 00:23:07.127548 Dram Type= 6, Freq= 0, CH_1, rank 0
6830 00:23:07.130800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6831 00:23:07.131223 ==
6832 00:23:07.131637
6833 00:23:07.131956
6834 00:23:07.134022 TX Vref Scan disable
6835 00:23:07.134469 == TX Byte 0 ==
6836 00:23:07.140366 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6837 00:23:07.143673 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6838 00:23:07.144116 == TX Byte 1 ==
6839 00:23:07.150775 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6840 00:23:07.153825 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6841 00:23:07.154355 ==
6842 00:23:07.157287 Dram Type= 6, Freq= 0, CH_1, rank 0
6843 00:23:07.160312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6844 00:23:07.160762 ==
6845 00:23:07.161207
6846 00:23:07.164087
6847 00:23:07.164524 TX Vref Scan disable
6848 00:23:07.167079 == TX Byte 0 ==
6849 00:23:07.170624 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6850 00:23:07.173455 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6851 00:23:07.177057 == TX Byte 1 ==
6852 00:23:07.179959 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6853 00:23:07.183873 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6854 00:23:07.184428
6855 00:23:07.186743 [DATLAT]
6856 00:23:07.187180 Freq=400, CH1 RK0
6857 00:23:07.187632
6858 00:23:07.189716 DATLAT Default: 0xf
6859 00:23:07.190153 0, 0xFFFF, sum = 0
6860 00:23:07.193341 1, 0xFFFF, sum = 0
6861 00:23:07.193787 2, 0xFFFF, sum = 0
6862 00:23:07.196399 3, 0xFFFF, sum = 0
6863 00:23:07.196846 4, 0xFFFF, sum = 0
6864 00:23:07.199999 5, 0xFFFF, sum = 0
6865 00:23:07.200458 6, 0xFFFF, sum = 0
6866 00:23:07.203445 7, 0xFFFF, sum = 0
6867 00:23:07.203894 8, 0xFFFF, sum = 0
6868 00:23:07.206602 9, 0xFFFF, sum = 0
6869 00:23:07.207027 10, 0xFFFF, sum = 0
6870 00:23:07.209476 11, 0xFFFF, sum = 0
6871 00:23:07.212836 12, 0xFFFF, sum = 0
6872 00:23:07.213263 13, 0x0, sum = 1
6873 00:23:07.213604 14, 0x0, sum = 2
6874 00:23:07.216560 15, 0x0, sum = 3
6875 00:23:07.216988 16, 0x0, sum = 4
6876 00:23:07.219997 best_step = 14
6877 00:23:07.220419
6878 00:23:07.221010 ==
6879 00:23:07.222902 Dram Type= 6, Freq= 0, CH_1, rank 0
6880 00:23:07.226455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6881 00:23:07.226969 ==
6882 00:23:07.229457 RX Vref Scan: 1
6883 00:23:07.229880
6884 00:23:07.230237 RX Vref 0 -> 0, step: 1
6885 00:23:07.230557
6886 00:23:07.233083 RX Delay -343 -> 252, step: 8
6887 00:23:07.233504
6888 00:23:07.236245 Set Vref, RX VrefLevel [Byte0]: 48
6889 00:23:07.239774 [Byte1]: 54
6890 00:23:07.244691
6891 00:23:07.245137 Final RX Vref Byte 0 = 48 to rank0
6892 00:23:07.247904 Final RX Vref Byte 1 = 54 to rank0
6893 00:23:07.250521 Final RX Vref Byte 0 = 48 to rank1
6894 00:23:07.254074 Final RX Vref Byte 1 = 54 to rank1==
6895 00:23:07.257273 Dram Type= 6, Freq= 0, CH_1, rank 0
6896 00:23:07.263926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6897 00:23:07.264413 ==
6898 00:23:07.264916 DQS Delay:
6899 00:23:07.267543 DQS0 = 44, DQS1 = 56
6900 00:23:07.267972 DQM Delay:
6901 00:23:07.270439 DQM0 = 9, DQM1 = 12
6902 00:23:07.270866 DQ Delay:
6903 00:23:07.273902 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6904 00:23:07.276895 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6905 00:23:07.277320 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6906 00:23:07.284097 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =20
6907 00:23:07.284539
6908 00:23:07.284988
6909 00:23:07.290828 [DQSOSCAuto] RK0, (LSB)MR18= 0x976e, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 390 ps
6910 00:23:07.293897 CH1 RK0: MR19=C0C, MR18=976E
6911 00:23:07.300535 CH1_RK0: MR19=0xC0C, MR18=0x976E, DQSOSC=390, MR23=63, INC=388, DEC=258
6912 00:23:07.300978 ==
6913 00:23:07.303677 Dram Type= 6, Freq= 0, CH_1, rank 1
6914 00:23:07.307195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6915 00:23:07.307641 ==
6916 00:23:07.310455 [Gating] SW mode calibration
6917 00:23:07.317088 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6918 00:23:07.323659 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6919 00:23:07.326588 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6920 00:23:07.330124 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6921 00:23:07.336338 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6922 00:23:07.339910 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6923 00:23:07.343678 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6924 00:23:07.350150 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6925 00:23:07.353022 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6926 00:23:07.356234 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6927 00:23:07.363059 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6928 00:23:07.366068 Total UI for P1: 0, mck2ui 16
6929 00:23:07.369736 best dqsien dly found for B0: ( 0, 14, 24)
6930 00:23:07.370220 Total UI for P1: 0, mck2ui 16
6931 00:23:07.375894 best dqsien dly found for B1: ( 0, 14, 24)
6932 00:23:07.379739 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6933 00:23:07.382571 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6934 00:23:07.383002
6935 00:23:07.386060 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6936 00:23:07.389140 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6937 00:23:07.392711 [Gating] SW calibration Done
6938 00:23:07.393138 ==
6939 00:23:07.395962 Dram Type= 6, Freq= 0, CH_1, rank 1
6940 00:23:07.398878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6941 00:23:07.399495 ==
6942 00:23:07.402106 RX Vref Scan: 0
6943 00:23:07.402548
6944 00:23:07.405785 RX Vref 0 -> 0, step: 1
6945 00:23:07.406254
6946 00:23:07.406595 RX Delay -410 -> 252, step: 16
6947 00:23:07.412293 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6948 00:23:07.415818 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6949 00:23:07.419085 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6950 00:23:07.425319 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6951 00:23:07.428732 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6952 00:23:07.432152 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6953 00:23:07.435767 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6954 00:23:07.442219 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6955 00:23:07.445076 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6956 00:23:07.448648 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6957 00:23:07.451585 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6958 00:23:07.458608 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6959 00:23:07.461669 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6960 00:23:07.464950 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6961 00:23:07.467799 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6962 00:23:07.474929 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6963 00:23:07.475115 ==
6964 00:23:07.478667 Dram Type= 6, Freq= 0, CH_1, rank 1
6965 00:23:07.481447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6966 00:23:07.481603 ==
6967 00:23:07.481709 DQS Delay:
6968 00:23:07.484305 DQS0 = 51, DQS1 = 51
6969 00:23:07.484435 DQM Delay:
6970 00:23:07.488013 DQM0 = 19, DQM1 = 14
6971 00:23:07.488124 DQ Delay:
6972 00:23:07.491065 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6973 00:23:07.494047 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6974 00:23:07.497954 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6975 00:23:07.500902 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6976 00:23:07.500982
6977 00:23:07.501052
6978 00:23:07.501114 ==
6979 00:23:07.504515 Dram Type= 6, Freq= 0, CH_1, rank 1
6980 00:23:07.507539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6981 00:23:07.510597 ==
6982 00:23:07.510714
6983 00:23:07.510809
6984 00:23:07.510900 TX Vref Scan disable
6985 00:23:07.514239 == TX Byte 0 ==
6986 00:23:07.517595 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6987 00:23:07.521364 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6988 00:23:07.524406 == TX Byte 1 ==
6989 00:23:07.527647 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6990 00:23:07.531246 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6991 00:23:07.531707 ==
6992 00:23:07.533970 Dram Type= 6, Freq= 0, CH_1, rank 1
6993 00:23:07.540542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6994 00:23:07.540977 ==
6995 00:23:07.541311
6996 00:23:07.541623
6997 00:23:07.541923 TX Vref Scan disable
6998 00:23:07.544449 == TX Byte 0 ==
6999 00:23:07.547233 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
7000 00:23:07.550816 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
7001 00:23:07.553980 == TX Byte 1 ==
7002 00:23:07.557565 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
7003 00:23:07.560388 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
7004 00:23:07.560815
7005 00:23:07.563900 [DATLAT]
7006 00:23:07.564447 Freq=400, CH1 RK1
7007 00:23:07.564800
7008 00:23:07.567376 DATLAT Default: 0xe
7009 00:23:07.567803 0, 0xFFFF, sum = 0
7010 00:23:07.570705 1, 0xFFFF, sum = 0
7011 00:23:07.571140 2, 0xFFFF, sum = 0
7012 00:23:07.573607 3, 0xFFFF, sum = 0
7013 00:23:07.574063 4, 0xFFFF, sum = 0
7014 00:23:07.577160 5, 0xFFFF, sum = 0
7015 00:23:07.577622 6, 0xFFFF, sum = 0
7016 00:23:07.580809 7, 0xFFFF, sum = 0
7017 00:23:07.581307 8, 0xFFFF, sum = 0
7018 00:23:07.583702 9, 0xFFFF, sum = 0
7019 00:23:07.586693 10, 0xFFFF, sum = 0
7020 00:23:07.587155 11, 0xFFFF, sum = 0
7021 00:23:07.590267 12, 0xFFFF, sum = 0
7022 00:23:07.590730 13, 0x0, sum = 1
7023 00:23:07.593263 14, 0x0, sum = 2
7024 00:23:07.593687 15, 0x0, sum = 3
7025 00:23:07.596723 16, 0x0, sum = 4
7026 00:23:07.597149 best_step = 14
7027 00:23:07.597516
7028 00:23:07.597864 ==
7029 00:23:07.599725 Dram Type= 6, Freq= 0, CH_1, rank 1
7030 00:23:07.603580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7031 00:23:07.604005 ==
7032 00:23:07.606490 RX Vref Scan: 0
7033 00:23:07.606787
7034 00:23:07.609899 RX Vref 0 -> 0, step: 1
7035 00:23:07.610287
7036 00:23:07.610547 RX Delay -343 -> 252, step: 8
7037 00:23:07.618722 iDelay=225, Bit 0, Center -32 (-271 ~ 208) 480
7038 00:23:07.621792 iDelay=225, Bit 1, Center -40 (-279 ~ 200) 480
7039 00:23:07.625349 iDelay=225, Bit 2, Center -48 (-287 ~ 192) 480
7040 00:23:07.631696 iDelay=225, Bit 3, Center -36 (-271 ~ 200) 472
7041 00:23:07.634759 iDelay=225, Bit 4, Center -36 (-279 ~ 208) 488
7042 00:23:07.638423 iDelay=225, Bit 5, Center -24 (-263 ~ 216) 480
7043 00:23:07.641812 iDelay=225, Bit 6, Center -24 (-271 ~ 224) 496
7044 00:23:07.648169 iDelay=225, Bit 7, Center -36 (-279 ~ 208) 488
7045 00:23:07.651772 iDelay=225, Bit 8, Center -56 (-303 ~ 192) 496
7046 00:23:07.654724 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
7047 00:23:07.657783 iDelay=225, Bit 10, Center -44 (-295 ~ 208) 504
7048 00:23:07.664377 iDelay=225, Bit 11, Center -52 (-295 ~ 192) 488
7049 00:23:07.667808 iDelay=225, Bit 12, Center -36 (-287 ~ 216) 504
7050 00:23:07.671366 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
7051 00:23:07.674759 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
7052 00:23:07.681007 iDelay=225, Bit 15, Center -36 (-287 ~ 216) 504
7053 00:23:07.681127 ==
7054 00:23:07.684473 Dram Type= 6, Freq= 0, CH_1, rank 1
7055 00:23:07.688229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7056 00:23:07.688384 ==
7057 00:23:07.688486 DQS Delay:
7058 00:23:07.691274 DQS0 = 48, DQS1 = 56
7059 00:23:07.691421 DQM Delay:
7060 00:23:07.694194 DQM0 = 13, DQM1 = 11
7061 00:23:07.694341 DQ Delay:
7062 00:23:07.697576 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
7063 00:23:07.701091 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =12
7064 00:23:07.704293 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
7065 00:23:07.707230 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
7066 00:23:07.707458
7067 00:23:07.707635
7068 00:23:07.717887 [DQSOSCAuto] RK1, (LSB)MR18= 0x6b5a, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
7069 00:23:07.718438 CH1 RK1: MR19=C0C, MR18=6B5A
7070 00:23:07.724408 CH1_RK1: MR19=0xC0C, MR18=0x6B5A, DQSOSC=396, MR23=63, INC=376, DEC=251
7071 00:23:07.727443 [RxdqsGatingPostProcess] freq 400
7072 00:23:07.734445 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7073 00:23:07.737831 best DQS0 dly(2T, 0.5T) = (0, 10)
7074 00:23:07.740692 best DQS1 dly(2T, 0.5T) = (0, 10)
7075 00:23:07.743970 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7076 00:23:07.746993 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7077 00:23:07.750718 best DQS0 dly(2T, 0.5T) = (0, 10)
7078 00:23:07.753729 best DQS1 dly(2T, 0.5T) = (0, 10)
7079 00:23:07.756903 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7080 00:23:07.760612 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7081 00:23:07.761037 Pre-setting of DQS Precalculation
7082 00:23:07.766810 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7083 00:23:07.773640 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7084 00:23:07.780525 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7085 00:23:07.781081
7086 00:23:07.781569
7087 00:23:07.783569 [Calibration Summary] 800 Mbps
7088 00:23:07.786980 CH 0, Rank 0
7089 00:23:07.787421 SW Impedance : PASS
7090 00:23:07.790366 DUTY Scan : NO K
7091 00:23:07.793767 ZQ Calibration : PASS
7092 00:23:07.794322 Jitter Meter : NO K
7093 00:23:07.796826 CBT Training : PASS
7094 00:23:07.800463 Write leveling : PASS
7095 00:23:07.800900 RX DQS gating : PASS
7096 00:23:07.803480 RX DQ/DQS(RDDQC) : PASS
7097 00:23:07.803906 TX DQ/DQS : PASS
7098 00:23:07.806932 RX DATLAT : PASS
7099 00:23:07.810361 RX DQ/DQS(Engine): PASS
7100 00:23:07.810995 TX OE : NO K
7101 00:23:07.813306 All Pass.
7102 00:23:07.813780
7103 00:23:07.814157 CH 0, Rank 1
7104 00:23:07.816673 SW Impedance : PASS
7105 00:23:07.817150 DUTY Scan : NO K
7106 00:23:07.820353 ZQ Calibration : PASS
7107 00:23:07.823430 Jitter Meter : NO K
7108 00:23:07.824049 CBT Training : PASS
7109 00:23:07.826992 Write leveling : NO K
7110 00:23:07.829950 RX DQS gating : PASS
7111 00:23:07.830426 RX DQ/DQS(RDDQC) : PASS
7112 00:23:07.833153 TX DQ/DQS : PASS
7113 00:23:07.836687 RX DATLAT : PASS
7114 00:23:07.837119 RX DQ/DQS(Engine): PASS
7115 00:23:07.839731 TX OE : NO K
7116 00:23:07.840157 All Pass.
7117 00:23:07.840501
7118 00:23:07.843588 CH 1, Rank 0
7119 00:23:07.844025 SW Impedance : PASS
7120 00:23:07.846556 DUTY Scan : NO K
7121 00:23:07.849565 ZQ Calibration : PASS
7122 00:23:07.849990 Jitter Meter : NO K
7123 00:23:07.853192 CBT Training : PASS
7124 00:23:07.856431 Write leveling : PASS
7125 00:23:07.856974 RX DQS gating : PASS
7126 00:23:07.859884 RX DQ/DQS(RDDQC) : PASS
7127 00:23:07.862963 TX DQ/DQS : PASS
7128 00:23:07.863399 RX DATLAT : PASS
7129 00:23:07.866015 RX DQ/DQS(Engine): PASS
7130 00:23:07.866545 TX OE : NO K
7131 00:23:07.869570 All Pass.
7132 00:23:07.870005
7133 00:23:07.870505 CH 1, Rank 1
7134 00:23:07.872742 SW Impedance : PASS
7135 00:23:07.873267 DUTY Scan : NO K
7136 00:23:07.876228 ZQ Calibration : PASS
7137 00:23:07.879278 Jitter Meter : NO K
7138 00:23:07.879715 CBT Training : PASS
7139 00:23:07.882991 Write leveling : NO K
7140 00:23:07.885848 RX DQS gating : PASS
7141 00:23:07.886311 RX DQ/DQS(RDDQC) : PASS
7142 00:23:07.889613 TX DQ/DQS : PASS
7143 00:23:07.892584 RX DATLAT : PASS
7144 00:23:07.893184 RX DQ/DQS(Engine): PASS
7145 00:23:07.896329 TX OE : NO K
7146 00:23:07.896751 All Pass.
7147 00:23:07.897183
7148 00:23:07.899143 DramC Write-DBI off
7149 00:23:07.902638 PER_BANK_REFRESH: Hybrid Mode
7150 00:23:07.903093 TX_TRACKING: ON
7151 00:23:07.912542 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7152 00:23:07.915997 [FAST_K] Save calibration result to emmc
7153 00:23:07.919500 dramc_set_vcore_voltage set vcore to 725000
7154 00:23:07.922698 Read voltage for 1600, 0
7155 00:23:07.923231 Vio18 = 0
7156 00:23:07.923570 Vcore = 725000
7157 00:23:07.925981 Vdram = 0
7158 00:23:07.926454 Vddq = 0
7159 00:23:07.926791 Vmddr = 0
7160 00:23:07.932523 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7161 00:23:07.935529 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7162 00:23:07.939039 MEM_TYPE=3, freq_sel=13
7163 00:23:07.942113 sv_algorithm_assistance_LP4_3733
7164 00:23:07.945585 ============ PULL DRAM RESETB DOWN ============
7165 00:23:07.952211 ========== PULL DRAM RESETB DOWN end =========
7166 00:23:07.955154 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7167 00:23:07.958855 ===================================
7168 00:23:07.961979 LPDDR4 DRAM CONFIGURATION
7169 00:23:07.965133 ===================================
7170 00:23:07.965568 EX_ROW_EN[0] = 0x0
7171 00:23:07.968729 EX_ROW_EN[1] = 0x0
7172 00:23:07.969163 LP4Y_EN = 0x0
7173 00:23:07.971780 WORK_FSP = 0x1
7174 00:23:07.972210 WL = 0x5
7175 00:23:07.975353 RL = 0x5
7176 00:23:07.975813 BL = 0x2
7177 00:23:07.978506 RPST = 0x0
7178 00:23:07.982194 RD_PRE = 0x0
7179 00:23:07.982740 WR_PRE = 0x1
7180 00:23:07.984872 WR_PST = 0x1
7181 00:23:07.985304 DBI_WR = 0x0
7182 00:23:07.988657 DBI_RD = 0x0
7183 00:23:07.989178 OTF = 0x1
7184 00:23:07.991508 ===================================
7185 00:23:07.995037 ===================================
7186 00:23:07.998667 ANA top config
7187 00:23:08.001863 ===================================
7188 00:23:08.002338 DLL_ASYNC_EN = 0
7189 00:23:08.004842 ALL_SLAVE_EN = 0
7190 00:23:08.008616 NEW_RANK_MODE = 1
7191 00:23:08.011728 DLL_IDLE_MODE = 1
7192 00:23:08.012249 LP45_APHY_COMB_EN = 1
7193 00:23:08.014785 TX_ODT_DIS = 0
7194 00:23:08.018465 NEW_8X_MODE = 1
7195 00:23:08.021487 ===================================
7196 00:23:08.025122 ===================================
7197 00:23:08.028339 data_rate = 3200
7198 00:23:08.031327 CKR = 1
7199 00:23:08.034649 DQ_P2S_RATIO = 8
7200 00:23:08.037811 ===================================
7201 00:23:08.038288 CA_P2S_RATIO = 8
7202 00:23:08.040891 DQ_CA_OPEN = 0
7203 00:23:08.044454 DQ_SEMI_OPEN = 0
7204 00:23:08.047541 CA_SEMI_OPEN = 0
7205 00:23:08.051190 CA_FULL_RATE = 0
7206 00:23:08.054377 DQ_CKDIV4_EN = 0
7207 00:23:08.054817 CA_CKDIV4_EN = 0
7208 00:23:08.057438 CA_PREDIV_EN = 0
7209 00:23:08.060919 PH8_DLY = 12
7210 00:23:08.063948 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7211 00:23:08.067494 DQ_AAMCK_DIV = 4
7212 00:23:08.070519 CA_AAMCK_DIV = 4
7213 00:23:08.070962 CA_ADMCK_DIV = 4
7214 00:23:08.074474 DQ_TRACK_CA_EN = 0
7215 00:23:08.077404 CA_PICK = 1600
7216 00:23:08.081108 CA_MCKIO = 1600
7217 00:23:08.084054 MCKIO_SEMI = 0
7218 00:23:08.087253 PLL_FREQ = 3068
7219 00:23:08.090696 DQ_UI_PI_RATIO = 32
7220 00:23:08.094130 CA_UI_PI_RATIO = 0
7221 00:23:08.097368 ===================================
7222 00:23:08.100700 ===================================
7223 00:23:08.101236 memory_type:LPDDR4
7224 00:23:08.104172 GP_NUM : 10
7225 00:23:08.106979 SRAM_EN : 1
7226 00:23:08.107422 MD32_EN : 0
7227 00:23:08.110437 ===================================
7228 00:23:08.113886 [ANA_INIT] >>>>>>>>>>>>>>
7229 00:23:08.116821 <<<<<< [CONFIGURE PHASE]: ANA_TX
7230 00:23:08.120427 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7231 00:23:08.123739 ===================================
7232 00:23:08.127106 data_rate = 3200,PCW = 0X7600
7233 00:23:08.130046 ===================================
7234 00:23:08.133549 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7235 00:23:08.137051 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7236 00:23:08.143468 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7237 00:23:08.146482 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7238 00:23:08.149712 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7239 00:23:08.153369 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7240 00:23:08.156874 [ANA_INIT] flow start
7241 00:23:08.160186 [ANA_INIT] PLL >>>>>>>>
7242 00:23:08.160645 [ANA_INIT] PLL <<<<<<<<
7243 00:23:08.163383 [ANA_INIT] MIDPI >>>>>>>>
7244 00:23:08.166374 [ANA_INIT] MIDPI <<<<<<<<
7245 00:23:08.169973 [ANA_INIT] DLL >>>>>>>>
7246 00:23:08.170594 [ANA_INIT] DLL <<<<<<<<
7247 00:23:08.172993 [ANA_INIT] flow end
7248 00:23:08.176701 ============ LP4 DIFF to SE enter ============
7249 00:23:08.179851 ============ LP4 DIFF to SE exit ============
7250 00:23:08.183289 [ANA_INIT] <<<<<<<<<<<<<
7251 00:23:08.186234 [Flow] Enable top DCM control >>>>>
7252 00:23:08.189370 [Flow] Enable top DCM control <<<<<
7253 00:23:08.192880 Enable DLL master slave shuffle
7254 00:23:08.199441 ==============================================================
7255 00:23:08.200028 Gating Mode config
7256 00:23:08.205961 ==============================================================
7257 00:23:08.206510 Config description:
7258 00:23:08.215688 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7259 00:23:08.222849 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7260 00:23:08.228924 SELPH_MODE 0: By rank 1: By Phase
7261 00:23:08.235252 ==============================================================
7262 00:23:08.235686 GAT_TRACK_EN = 1
7263 00:23:08.238686 RX_GATING_MODE = 2
7264 00:23:08.242257 RX_GATING_TRACK_MODE = 2
7265 00:23:08.245237 SELPH_MODE = 1
7266 00:23:08.248765 PICG_EARLY_EN = 1
7267 00:23:08.251808 VALID_LAT_VALUE = 1
7268 00:23:08.258612 ==============================================================
7269 00:23:08.261707 Enter into Gating configuration >>>>
7270 00:23:08.265116 Exit from Gating configuration <<<<
7271 00:23:08.268300 Enter into DVFS_PRE_config >>>>>
7272 00:23:08.278401 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7273 00:23:08.281841 Exit from DVFS_PRE_config <<<<<
7274 00:23:08.284734 Enter into PICG configuration >>>>
7275 00:23:08.287925 Exit from PICG configuration <<<<
7276 00:23:08.291586 [RX_INPUT] configuration >>>>>
7277 00:23:08.295006 [RX_INPUT] configuration <<<<<
7278 00:23:08.298152 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7279 00:23:08.304734 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7280 00:23:08.311367 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7281 00:23:08.318046 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7282 00:23:08.321501 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7283 00:23:08.327644 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7284 00:23:08.330935 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7285 00:23:08.337530 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7286 00:23:08.340911 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7287 00:23:08.344409 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7288 00:23:08.347199 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7289 00:23:08.353933 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7290 00:23:08.357478 ===================================
7291 00:23:08.360376 LPDDR4 DRAM CONFIGURATION
7292 00:23:08.364182 ===================================
7293 00:23:08.364605 EX_ROW_EN[0] = 0x0
7294 00:23:08.367147 EX_ROW_EN[1] = 0x0
7295 00:23:08.367654 LP4Y_EN = 0x0
7296 00:23:08.370678 WORK_FSP = 0x1
7297 00:23:08.371106 WL = 0x5
7298 00:23:08.373967 RL = 0x5
7299 00:23:08.374540 BL = 0x2
7300 00:23:08.377277 RPST = 0x0
7301 00:23:08.377692 RD_PRE = 0x0
7302 00:23:08.380259 WR_PRE = 0x1
7303 00:23:08.380675 WR_PST = 0x1
7304 00:23:08.383805 DBI_WR = 0x0
7305 00:23:08.384242 DBI_RD = 0x0
7306 00:23:08.387026 OTF = 0x1
7307 00:23:08.390499 ===================================
7308 00:23:08.393628 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7309 00:23:08.396863 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7310 00:23:08.403248 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7311 00:23:08.406861 ===================================
7312 00:23:08.409776 LPDDR4 DRAM CONFIGURATION
7313 00:23:08.413572 ===================================
7314 00:23:08.413989 EX_ROW_EN[0] = 0x10
7315 00:23:08.416430 EX_ROW_EN[1] = 0x0
7316 00:23:08.416848 LP4Y_EN = 0x0
7317 00:23:08.419852 WORK_FSP = 0x1
7318 00:23:08.420317 WL = 0x5
7319 00:23:08.423264 RL = 0x5
7320 00:23:08.423668 BL = 0x2
7321 00:23:08.426786 RPST = 0x0
7322 00:23:08.427269 RD_PRE = 0x0
7323 00:23:08.430402 WR_PRE = 0x1
7324 00:23:08.430862 WR_PST = 0x1
7325 00:23:08.433050 DBI_WR = 0x0
7326 00:23:08.436554 DBI_RD = 0x0
7327 00:23:08.436998 OTF = 0x1
7328 00:23:08.439595 ===================================
7329 00:23:08.446345 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7330 00:23:08.446770 ==
7331 00:23:08.449718 Dram Type= 6, Freq= 0, CH_0, rank 0
7332 00:23:08.453249 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7333 00:23:08.453692 ==
7334 00:23:08.456267 [Duty_Offset_Calibration]
7335 00:23:08.459801 B0:1 B1:-1 CA:0
7336 00:23:08.460250
7337 00:23:08.462790 [DutyScan_Calibration_Flow] k_type=0
7338 00:23:08.471194
7339 00:23:08.471613 ==CLK 0==
7340 00:23:08.474320 Final CLK duty delay cell = 0
7341 00:23:08.478008 [0] MAX Duty = 5093%(X100), DQS PI = 16
7342 00:23:08.480979 [0] MIN Duty = 4907%(X100), DQS PI = 6
7343 00:23:08.481437 [0] AVG Duty = 5000%(X100)
7344 00:23:08.484530
7345 00:23:08.488064 CH0 CLK Duty spec in!! Max-Min= 186%
7346 00:23:08.491094 [DutyScan_Calibration_Flow] ====Done====
7347 00:23:08.491537
7348 00:23:08.494672 [DutyScan_Calibration_Flow] k_type=1
7349 00:23:08.510299
7350 00:23:08.510722 ==DQS 0 ==
7351 00:23:08.513540 Final DQS duty delay cell = -4
7352 00:23:08.517126 [-4] MAX Duty = 5000%(X100), DQS PI = 20
7353 00:23:08.520402 [-4] MIN Duty = 4844%(X100), DQS PI = 48
7354 00:23:08.523407 [-4] AVG Duty = 4922%(X100)
7355 00:23:08.523847
7356 00:23:08.524177 ==DQS 1 ==
7357 00:23:08.526723 Final DQS duty delay cell = 0
7358 00:23:08.529902 [0] MAX Duty = 5156%(X100), DQS PI = 0
7359 00:23:08.533470 [0] MIN Duty = 5000%(X100), DQS PI = 18
7360 00:23:08.536741 [0] AVG Duty = 5078%(X100)
7361 00:23:08.537206
7362 00:23:08.540284 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7363 00:23:08.540781
7364 00:23:08.543096 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7365 00:23:08.546862 [DutyScan_Calibration_Flow] ====Done====
7366 00:23:08.547280
7367 00:23:08.549796 [DutyScan_Calibration_Flow] k_type=3
7368 00:23:08.567430
7369 00:23:08.567680 ==DQM 0 ==
7370 00:23:08.570879 Final DQM duty delay cell = 0
7371 00:23:08.574017 [0] MAX Duty = 5124%(X100), DQS PI = 22
7372 00:23:08.577606 [0] MIN Duty = 4907%(X100), DQS PI = 10
7373 00:23:08.580653 [0] AVG Duty = 5015%(X100)
7374 00:23:08.580892
7375 00:23:08.581086 ==DQM 1 ==
7376 00:23:08.584320 Final DQM duty delay cell = 0
7377 00:23:08.587184 [0] MAX Duty = 5000%(X100), DQS PI = 6
7378 00:23:08.590772 [0] MIN Duty = 4782%(X100), DQS PI = 20
7379 00:23:08.593770 [0] AVG Duty = 4891%(X100)
7380 00:23:08.594008
7381 00:23:08.597456 CH0 DQM 0 Duty spec in!! Max-Min= 217%
7382 00:23:08.597680
7383 00:23:08.600401 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7384 00:23:08.604002 [DutyScan_Calibration_Flow] ====Done====
7385 00:23:08.604323
7386 00:23:08.606900 [DutyScan_Calibration_Flow] k_type=2
7387 00:23:08.623904
7388 00:23:08.624207 ==DQ 0 ==
7389 00:23:08.627534 Final DQ duty delay cell = -4
7390 00:23:08.630678 [-4] MAX Duty = 5031%(X100), DQS PI = 26
7391 00:23:08.634375 [-4] MIN Duty = 4876%(X100), DQS PI = 50
7392 00:23:08.637581 [-4] AVG Duty = 4953%(X100)
7393 00:23:08.638096
7394 00:23:08.638544 ==DQ 1 ==
7395 00:23:08.640438 Final DQ duty delay cell = 0
7396 00:23:08.644084 [0] MAX Duty = 5125%(X100), DQS PI = 2
7397 00:23:08.647018 [0] MIN Duty = 5000%(X100), DQS PI = 34
7398 00:23:08.650627 [0] AVG Duty = 5062%(X100)
7399 00:23:08.651216
7400 00:23:08.653862 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7401 00:23:08.654533
7402 00:23:08.656912 CH0 DQ 1 Duty spec in!! Max-Min= 125%
7403 00:23:08.660263 [DutyScan_Calibration_Flow] ====Done====
7404 00:23:08.660720 ==
7405 00:23:08.663785 Dram Type= 6, Freq= 0, CH_1, rank 0
7406 00:23:08.666705 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7407 00:23:08.667129 ==
7408 00:23:08.670309 [Duty_Offset_Calibration]
7409 00:23:08.670806 B0:-1 B1:1 CA:2
7410 00:23:08.671157
7411 00:23:08.673412 [DutyScan_Calibration_Flow] k_type=0
7412 00:23:08.684765
7413 00:23:08.685178 ==CLK 0==
7414 00:23:08.687834 Final CLK duty delay cell = 0
7415 00:23:08.691451 [0] MAX Duty = 5187%(X100), DQS PI = 24
7416 00:23:08.694323 [0] MIN Duty = 4969%(X100), DQS PI = 62
7417 00:23:08.697879 [0] AVG Duty = 5078%(X100)
7418 00:23:08.698336
7419 00:23:08.700895 CH1 CLK Duty spec in!! Max-Min= 218%
7420 00:23:08.704500 [DutyScan_Calibration_Flow] ====Done====
7421 00:23:08.705062
7422 00:23:08.707705 [DutyScan_Calibration_Flow] k_type=1
7423 00:23:08.724371
7424 00:23:08.724790 ==DQS 0 ==
7425 00:23:08.728060 Final DQS duty delay cell = 0
7426 00:23:08.731061 [0] MAX Duty = 5124%(X100), DQS PI = 18
7427 00:23:08.734646 [0] MIN Duty = 4907%(X100), DQS PI = 8
7428 00:23:08.737824 [0] AVG Duty = 5015%(X100)
7429 00:23:08.738471
7430 00:23:08.738849 ==DQS 1 ==
7431 00:23:08.741182 Final DQS duty delay cell = 0
7432 00:23:08.743977 [0] MAX Duty = 5093%(X100), DQS PI = 26
7433 00:23:08.747772 [0] MIN Duty = 4969%(X100), DQS PI = 54
7434 00:23:08.750800 [0] AVG Duty = 5031%(X100)
7435 00:23:08.751313
7436 00:23:08.754041 CH1 DQS 0 Duty spec in!! Max-Min= 217%
7437 00:23:08.754523
7438 00:23:08.757318 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7439 00:23:08.760589 [DutyScan_Calibration_Flow] ====Done====
7440 00:23:08.761207
7441 00:23:08.764115 [DutyScan_Calibration_Flow] k_type=3
7442 00:23:08.781176
7443 00:23:08.781604 ==DQM 0 ==
7444 00:23:08.784899 Final DQM duty delay cell = 0
7445 00:23:08.787892 [0] MAX Duty = 5218%(X100), DQS PI = 18
7446 00:23:08.790956 [0] MIN Duty = 5031%(X100), DQS PI = 8
7447 00:23:08.794509 [0] AVG Duty = 5124%(X100)
7448 00:23:08.794944
7449 00:23:08.795279 ==DQM 1 ==
7450 00:23:08.798069 Final DQM duty delay cell = 0
7451 00:23:08.801130 [0] MAX Duty = 5125%(X100), DQS PI = 2
7452 00:23:08.804043 [0] MIN Duty = 4938%(X100), DQS PI = 34
7453 00:23:08.807677 [0] AVG Duty = 5031%(X100)
7454 00:23:08.808093
7455 00:23:08.810910 CH1 DQM 0 Duty spec in!! Max-Min= 187%
7456 00:23:08.811363
7457 00:23:08.814432 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7458 00:23:08.817305 [DutyScan_Calibration_Flow] ====Done====
7459 00:23:08.817833
7460 00:23:08.820656 [DutyScan_Calibration_Flow] k_type=2
7461 00:23:08.837677
7462 00:23:08.837784 ==DQ 0 ==
7463 00:23:08.840875 Final DQ duty delay cell = 0
7464 00:23:08.844489 [0] MAX Duty = 5156%(X100), DQS PI = 28
7465 00:23:08.847424 [0] MIN Duty = 4906%(X100), DQS PI = 10
7466 00:23:08.850989 [0] AVG Duty = 5031%(X100)
7467 00:23:08.851100
7468 00:23:08.851206 ==DQ 1 ==
7469 00:23:08.854399 Final DQ duty delay cell = 0
7470 00:23:08.857539 [0] MAX Duty = 5125%(X100), DQS PI = 8
7471 00:23:08.861077 [0] MIN Duty = 4969%(X100), DQS PI = 34
7472 00:23:08.861161 [0] AVG Duty = 5047%(X100)
7473 00:23:08.861230
7474 00:23:08.867535 CH1 DQ 0 Duty spec in!! Max-Min= 250%
7475 00:23:08.867643
7476 00:23:08.870696 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7477 00:23:08.874183 [DutyScan_Calibration_Flow] ====Done====
7478 00:23:08.877264 nWR fixed to 30
7479 00:23:08.877364 [ModeRegInit_LP4] CH0 RK0
7480 00:23:08.880676 [ModeRegInit_LP4] CH0 RK1
7481 00:23:08.883835 [ModeRegInit_LP4] CH1 RK0
7482 00:23:08.886969 [ModeRegInit_LP4] CH1 RK1
7483 00:23:08.887082 match AC timing 5
7484 00:23:08.894015 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7485 00:23:08.897278 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7486 00:23:08.900522 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7487 00:23:08.907381 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7488 00:23:08.910312 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7489 00:23:08.910384 [MiockJmeterHQA]
7490 00:23:08.910445
7491 00:23:08.913380 [DramcMiockJmeter] u1RxGatingPI = 0
7492 00:23:08.916924 0 : 4365, 4138
7493 00:23:08.917024 4 : 4253, 4026
7494 00:23:08.919924 8 : 4363, 4137
7495 00:23:08.920024 12 : 4363, 4137
7496 00:23:08.923620 16 : 4363, 4138
7497 00:23:08.923720 20 : 4363, 4137
7498 00:23:08.923813 24 : 4252, 4027
7499 00:23:08.926519 28 : 4252, 4027
7500 00:23:08.926615 32 : 4253, 4026
7501 00:23:08.929681 36 : 4255, 4029
7502 00:23:08.929786 40 : 4363, 4137
7503 00:23:08.933415 44 : 4253, 4027
7504 00:23:08.933508 48 : 4253, 4026
7505 00:23:08.936296 52 : 4253, 4027
7506 00:23:08.936398 56 : 4254, 4029
7507 00:23:08.936490 60 : 4253, 4026
7508 00:23:08.939446 64 : 4363, 4140
7509 00:23:08.939544 68 : 4363, 4138
7510 00:23:08.943091 72 : 4252, 4029
7511 00:23:08.943193 76 : 4250, 4027
7512 00:23:08.946570 80 : 4250, 4027
7513 00:23:08.946674 84 : 4250, 4026
7514 00:23:08.949497 88 : 4255, 4029
7515 00:23:08.949599 92 : 4360, 269
7516 00:23:08.949689 96 : 4253, 0
7517 00:23:08.953106 100 : 4252, 0
7518 00:23:08.953205 104 : 4361, 0
7519 00:23:08.955888 108 : 4250, 0
7520 00:23:08.955986 112 : 4250, 0
7521 00:23:08.956078 116 : 4250, 0
7522 00:23:08.959395 120 : 4250, 0
7523 00:23:08.959468 124 : 4251, 0
7524 00:23:08.963117 128 : 4250, 0
7525 00:23:08.963192 132 : 4250, 0
7526 00:23:08.963254 136 : 4252, 0
7527 00:23:08.966050 140 : 4361, 0
7528 00:23:08.966151 144 : 4360, 0
7529 00:23:08.966242 148 : 4363, 0
7530 00:23:08.969481 152 : 4252, 0
7531 00:23:08.969577 156 : 4250, 0
7532 00:23:08.972572 160 : 4250, 0
7533 00:23:08.972666 164 : 4250, 0
7534 00:23:08.972756 168 : 4250, 0
7535 00:23:08.976156 172 : 4250, 0
7536 00:23:08.976255 176 : 4252, 0
7537 00:23:08.979312 180 : 4250, 0
7538 00:23:08.979382 184 : 4250, 0
7539 00:23:08.979443 188 : 4252, 0
7540 00:23:08.982537 192 : 4361, 0
7541 00:23:08.982634 196 : 4360, 0
7542 00:23:08.985910 200 : 4363, 0
7543 00:23:08.986009 204 : 4250, 0
7544 00:23:08.986098 208 : 4361, 0
7545 00:23:08.988852 212 : 4250, 0
7546 00:23:08.988952 216 : 4249, 0
7547 00:23:08.992600 220 : 4250, 0
7548 00:23:08.992696 224 : 4250, 84
7549 00:23:08.992784 228 : 4252, 3303
7550 00:23:08.995506 232 : 4250, 4027
7551 00:23:08.995572 236 : 4250, 4027
7552 00:23:08.998811 240 : 4250, 4026
7553 00:23:08.998882 244 : 4361, 4137
7554 00:23:09.002111 248 : 4250, 4027
7555 00:23:09.002238 252 : 4250, 4027
7556 00:23:09.005291 256 : 4360, 4138
7557 00:23:09.005388 260 : 4250, 4026
7558 00:23:09.008643 264 : 4252, 4027
7559 00:23:09.008738 268 : 4363, 4140
7560 00:23:09.011927 272 : 4250, 4027
7561 00:23:09.012024 276 : 4250, 4026
7562 00:23:09.015310 280 : 4250, 4027
7563 00:23:09.015413 284 : 4252, 4030
7564 00:23:09.018479 288 : 4250, 4027
7565 00:23:09.018582 292 : 4250, 4026
7566 00:23:09.018674 296 : 4361, 4137
7567 00:23:09.022256 300 : 4250, 4026
7568 00:23:09.022334 304 : 4250, 4027
7569 00:23:09.025206 308 : 4360, 4137
7570 00:23:09.025306 312 : 4250, 4026
7571 00:23:09.028615 316 : 4253, 4029
7572 00:23:09.028736 320 : 4363, 4139
7573 00:23:09.031846 324 : 4250, 4027
7574 00:23:09.031924 328 : 4252, 4029
7575 00:23:09.034892 332 : 4250, 4027
7576 00:23:09.034989 336 : 4252, 3912
7577 00:23:09.038576 340 : 4250, 2175
7578 00:23:09.038653 344 : 4250, 55
7579 00:23:09.038717
7580 00:23:09.041519 MIOCK jitter meter ch=0
7581 00:23:09.041620
7582 00:23:09.045248 1T = (344-92) = 252 dly cells
7583 00:23:09.048223 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7584 00:23:09.048300 ==
7585 00:23:09.051877 Dram Type= 6, Freq= 0, CH_0, rank 0
7586 00:23:09.058408 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7587 00:23:09.058486 ==
7588 00:23:09.061313 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7589 00:23:09.067925 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7590 00:23:09.071515 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7591 00:23:09.077703 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7592 00:23:09.085943 [CA 0] Center 43 (13~74) winsize 62
7593 00:23:09.089327 [CA 1] Center 43 (13~74) winsize 62
7594 00:23:09.092526 [CA 2] Center 39 (9~69) winsize 61
7595 00:23:09.096102 [CA 3] Center 39 (9~69) winsize 61
7596 00:23:09.099618 [CA 4] Center 37 (8~66) winsize 59
7597 00:23:09.102687 [CA 5] Center 36 (7~66) winsize 60
7598 00:23:09.102778
7599 00:23:09.106354 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7600 00:23:09.106431
7601 00:23:09.109542 [CATrainingPosCal] consider 1 rank data
7602 00:23:09.113136 u2DelayCellTimex100 = 258/100 ps
7603 00:23:09.116126 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7604 00:23:09.122885 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7605 00:23:09.125644 CA2 delay=39 (9~69),Diff = 3 PI (11 cell)
7606 00:23:09.129247 CA3 delay=39 (9~69),Diff = 3 PI (11 cell)
7607 00:23:09.132260 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7608 00:23:09.135977 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7609 00:23:09.136079
7610 00:23:09.139121 CA PerBit enable=1, Macro0, CA PI delay=36
7611 00:23:09.139217
7612 00:23:09.142555 [CBTSetCACLKResult] CA Dly = 36
7613 00:23:09.145775 CS Dly: 12 (0~43)
7614 00:23:09.148938 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7615 00:23:09.152491 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7616 00:23:09.152589 ==
7617 00:23:09.155344 Dram Type= 6, Freq= 0, CH_0, rank 1
7618 00:23:09.162017 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7619 00:23:09.162136 ==
7620 00:23:09.165607 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7621 00:23:09.172188 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7622 00:23:09.175328 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7623 00:23:09.181810 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7624 00:23:09.189694 [CA 0] Center 42 (12~73) winsize 62
7625 00:23:09.192620 [CA 1] Center 43 (13~73) winsize 61
7626 00:23:09.196049 [CA 2] Center 37 (8~67) winsize 60
7627 00:23:09.199388 [CA 3] Center 37 (7~67) winsize 61
7628 00:23:09.202797 [CA 4] Center 36 (6~66) winsize 61
7629 00:23:09.205944 [CA 5] Center 35 (5~65) winsize 61
7630 00:23:09.206018
7631 00:23:09.209481 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7632 00:23:09.209576
7633 00:23:09.212459 [CATrainingPosCal] consider 2 rank data
7634 00:23:09.216160 u2DelayCellTimex100 = 258/100 ps
7635 00:23:09.222581 CA0 delay=43 (13~73),Diff = 7 PI (26 cell)
7636 00:23:09.225577 CA1 delay=43 (13~73),Diff = 7 PI (26 cell)
7637 00:23:09.229183 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
7638 00:23:09.232360 CA3 delay=38 (9~67),Diff = 2 PI (7 cell)
7639 00:23:09.235881 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7640 00:23:09.238882 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7641 00:23:09.238980
7642 00:23:09.242578 CA PerBit enable=1, Macro0, CA PI delay=36
7643 00:23:09.242655
7644 00:23:09.245915 [CBTSetCACLKResult] CA Dly = 36
7645 00:23:09.249104 CS Dly: 12 (0~44)
7646 00:23:09.252214 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7647 00:23:09.255557 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7648 00:23:09.255654
7649 00:23:09.258699 ----->DramcWriteLeveling(PI) begin...
7650 00:23:09.258772 ==
7651 00:23:09.261911 Dram Type= 6, Freq= 0, CH_0, rank 0
7652 00:23:09.268515 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7653 00:23:09.268613 ==
7654 00:23:09.272181 Write leveling (Byte 0): 38 => 38
7655 00:23:09.275202 Write leveling (Byte 1): 26 => 26
7656 00:23:09.275306 DramcWriteLeveling(PI) end<-----
7657 00:23:09.278796
7658 00:23:09.278896 ==
7659 00:23:09.282333 Dram Type= 6, Freq= 0, CH_0, rank 0
7660 00:23:09.285273 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7661 00:23:09.285344 ==
7662 00:23:09.288805 [Gating] SW mode calibration
7663 00:23:09.295082 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7664 00:23:09.298057 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7665 00:23:09.305160 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7666 00:23:09.308341 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7667 00:23:09.311419 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7668 00:23:09.318028 1 4 12 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (1 1)
7669 00:23:09.321649 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7670 00:23:09.324699 1 4 20 | B1->B0 | 2423 3434 | 1 1 | (0 0) (1 1)
7671 00:23:09.331378 1 4 24 | B1->B0 | 3130 3434 | 1 1 | (1 1) (1 1)
7672 00:23:09.334960 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7673 00:23:09.338061 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7674 00:23:09.344586 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7675 00:23:09.348214 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7676 00:23:09.351367 1 5 12 | B1->B0 | 3434 2929 | 1 0 | (1 1) (1 0)
7677 00:23:09.357848 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7678 00:23:09.361699 1 5 20 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7679 00:23:09.364574 1 5 24 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
7680 00:23:09.370915 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7681 00:23:09.374461 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7682 00:23:09.377600 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7683 00:23:09.384276 1 6 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7684 00:23:09.387406 1 6 12 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (0 0)
7685 00:23:09.390785 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7686 00:23:09.397335 1 6 20 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
7687 00:23:09.400561 1 6 24 | B1->B0 | 3e3e 4646 | 1 0 | (0 0) (0 0)
7688 00:23:09.404250 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7689 00:23:09.410808 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7690 00:23:09.414153 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7691 00:23:09.417679 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7692 00:23:09.423661 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7693 00:23:09.427415 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7694 00:23:09.430422 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7695 00:23:09.436869 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7696 00:23:09.439951 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7697 00:23:09.443651 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7698 00:23:09.450233 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7699 00:23:09.453148 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7700 00:23:09.456847 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7701 00:23:09.463410 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7702 00:23:09.466509 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7703 00:23:09.470053 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7704 00:23:09.476188 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7705 00:23:09.479594 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7706 00:23:09.482987 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7707 00:23:09.489843 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7708 00:23:09.492825 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7709 00:23:09.496443 Total UI for P1: 0, mck2ui 16
7710 00:23:09.499351 best dqsien dly found for B0: ( 1, 9, 8)
7711 00:23:09.502719 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7712 00:23:09.509486 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7713 00:23:09.512615 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7714 00:23:09.516376 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7715 00:23:09.519283 Total UI for P1: 0, mck2ui 16
7716 00:23:09.522672 best dqsien dly found for B1: ( 1, 9, 22)
7717 00:23:09.525998 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
7718 00:23:09.529146 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7719 00:23:09.532891
7720 00:23:09.535735 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
7721 00:23:09.539519 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7722 00:23:09.542414 [Gating] SW calibration Done
7723 00:23:09.542512 ==
7724 00:23:09.545614 Dram Type= 6, Freq= 0, CH_0, rank 0
7725 00:23:09.549123 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7726 00:23:09.549222 ==
7727 00:23:09.549310 RX Vref Scan: 0
7728 00:23:09.549397
7729 00:23:09.552767 RX Vref 0 -> 0, step: 1
7730 00:23:09.552861
7731 00:23:09.555723 RX Delay 0 -> 252, step: 8
7732 00:23:09.558868 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7733 00:23:09.562446 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7734 00:23:09.569049 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7735 00:23:09.572828 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
7736 00:23:09.575942 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7737 00:23:09.579040 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
7738 00:23:09.582518 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7739 00:23:09.588843 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7740 00:23:09.592154 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7741 00:23:09.595660 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7742 00:23:09.598544 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7743 00:23:09.602450 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7744 00:23:09.608869 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7745 00:23:09.611858 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7746 00:23:09.615456 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7747 00:23:09.618556 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7748 00:23:09.618631 ==
7749 00:23:09.621843 Dram Type= 6, Freq= 0, CH_0, rank 0
7750 00:23:09.628439 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7751 00:23:09.628517 ==
7752 00:23:09.628580 DQS Delay:
7753 00:23:09.632026 DQS0 = 0, DQS1 = 0
7754 00:23:09.632106 DQM Delay:
7755 00:23:09.635023 DQM0 = 137, DQM1 = 126
7756 00:23:09.635104 DQ Delay:
7757 00:23:09.638193 DQ0 =135, DQ1 =139, DQ2 =131, DQ3 =135
7758 00:23:09.641785 DQ4 =139, DQ5 =127, DQ6 =147, DQ7 =147
7759 00:23:09.644620 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =119
7760 00:23:09.648447 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =131
7761 00:23:09.648518
7762 00:23:09.648582
7763 00:23:09.648639 ==
7764 00:23:09.651315 Dram Type= 6, Freq= 0, CH_0, rank 0
7765 00:23:09.658077 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7766 00:23:09.658198 ==
7767 00:23:09.658263
7768 00:23:09.658323
7769 00:23:09.658380 TX Vref Scan disable
7770 00:23:09.661754 == TX Byte 0 ==
7771 00:23:09.664646 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
7772 00:23:09.671383 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7773 00:23:09.671460 == TX Byte 1 ==
7774 00:23:09.674379 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7775 00:23:09.681120 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7776 00:23:09.681192 ==
7777 00:23:09.684853 Dram Type= 6, Freq= 0, CH_0, rank 0
7778 00:23:09.687795 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7779 00:23:09.687864 ==
7780 00:23:09.701415
7781 00:23:09.704743 TX Vref early break, caculate TX vref
7782 00:23:09.708278 TX Vref=16, minBit 14, minWin=21, winSum=367
7783 00:23:09.711347 TX Vref=18, minBit 3, minWin=23, winSum=379
7784 00:23:09.714832 TX Vref=20, minBit 1, minWin=23, winSum=389
7785 00:23:09.717969 TX Vref=22, minBit 1, minWin=24, winSum=397
7786 00:23:09.721617 TX Vref=24, minBit 3, minWin=24, winSum=404
7787 00:23:09.727896 TX Vref=26, minBit 1, minWin=25, winSum=416
7788 00:23:09.730870 TX Vref=28, minBit 4, minWin=24, winSum=419
7789 00:23:09.734382 TX Vref=30, minBit 0, minWin=24, winSum=410
7790 00:23:09.737891 TX Vref=32, minBit 0, minWin=24, winSum=403
7791 00:23:09.740700 TX Vref=34, minBit 0, minWin=23, winSum=394
7792 00:23:09.747524 [TxChooseVref] Worse bit 1, Min win 25, Win sum 416, Final Vref 26
7793 00:23:09.747636
7794 00:23:09.750761 Final TX Range 0 Vref 26
7795 00:23:09.750863
7796 00:23:09.750955 ==
7797 00:23:09.753834 Dram Type= 6, Freq= 0, CH_0, rank 0
7798 00:23:09.757108 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7799 00:23:09.757203 ==
7800 00:23:09.757265
7801 00:23:09.760766
7802 00:23:09.760864 TX Vref Scan disable
7803 00:23:09.767358 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7804 00:23:09.767459 == TX Byte 0 ==
7805 00:23:09.770447 u2DelayCellOfst[0]=11 cells (3 PI)
7806 00:23:09.773911 u2DelayCellOfst[1]=15 cells (4 PI)
7807 00:23:09.777118 u2DelayCellOfst[2]=11 cells (3 PI)
7808 00:23:09.780531 u2DelayCellOfst[3]=11 cells (3 PI)
7809 00:23:09.783693 u2DelayCellOfst[4]=7 cells (2 PI)
7810 00:23:09.786704 u2DelayCellOfst[5]=0 cells (0 PI)
7811 00:23:09.790414 u2DelayCellOfst[6]=18 cells (5 PI)
7812 00:23:09.793494 u2DelayCellOfst[7]=15 cells (4 PI)
7813 00:23:09.797109 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7814 00:23:09.800180 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7815 00:23:09.803619 == TX Byte 1 ==
7816 00:23:09.806985 u2DelayCellOfst[8]=0 cells (0 PI)
7817 00:23:09.809998 u2DelayCellOfst[9]=3 cells (1 PI)
7818 00:23:09.813305 u2DelayCellOfst[10]=7 cells (2 PI)
7819 00:23:09.816768 u2DelayCellOfst[11]=3 cells (1 PI)
7820 00:23:09.820395 u2DelayCellOfst[12]=11 cells (3 PI)
7821 00:23:09.823385 u2DelayCellOfst[13]=11 cells (3 PI)
7822 00:23:09.823490 u2DelayCellOfst[14]=15 cells (4 PI)
7823 00:23:09.826629 u2DelayCellOfst[15]=11 cells (3 PI)
7824 00:23:09.832971 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7825 00:23:09.836637 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7826 00:23:09.839588 DramC Write-DBI on
7827 00:23:09.839689 ==
7828 00:23:09.842952 Dram Type= 6, Freq= 0, CH_0, rank 0
7829 00:23:09.846747 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7830 00:23:09.846848 ==
7831 00:23:09.846940
7832 00:23:09.847030
7833 00:23:09.849667 TX Vref Scan disable
7834 00:23:09.849759 == TX Byte 0 ==
7835 00:23:09.856121 Update DQM dly =738 (2 ,6, 34) DQM OEN =(3 ,3)
7836 00:23:09.856229 == TX Byte 1 ==
7837 00:23:09.859646 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
7838 00:23:09.862540 DramC Write-DBI off
7839 00:23:09.862650
7840 00:23:09.862741 [DATLAT]
7841 00:23:09.866049 Freq=1600, CH0 RK0
7842 00:23:09.866144
7843 00:23:09.866270 DATLAT Default: 0xf
7844 00:23:09.869114 0, 0xFFFF, sum = 0
7845 00:23:09.872468 1, 0xFFFF, sum = 0
7846 00:23:09.872573 2, 0xFFFF, sum = 0
7847 00:23:09.875690 3, 0xFFFF, sum = 0
7848 00:23:09.875798 4, 0xFFFF, sum = 0
7849 00:23:09.878945 5, 0xFFFF, sum = 0
7850 00:23:09.879054 6, 0xFFFF, sum = 0
7851 00:23:09.882581 7, 0xFFFF, sum = 0
7852 00:23:09.882687 8, 0xFFFF, sum = 0
7853 00:23:09.885657 9, 0xFFFF, sum = 0
7854 00:23:09.885756 10, 0xFFFF, sum = 0
7855 00:23:09.888924 11, 0xFFFF, sum = 0
7856 00:23:09.889022 12, 0xFFFF, sum = 0
7857 00:23:09.892512 13, 0xFFFF, sum = 0
7858 00:23:09.892611 14, 0x0, sum = 1
7859 00:23:09.895437 15, 0x0, sum = 2
7860 00:23:09.895533 16, 0x0, sum = 3
7861 00:23:09.898597 17, 0x0, sum = 4
7862 00:23:09.898667 best_step = 15
7863 00:23:09.898726
7864 00:23:09.898810 ==
7865 00:23:09.902168 Dram Type= 6, Freq= 0, CH_0, rank 0
7866 00:23:09.908878 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7867 00:23:09.908979 ==
7868 00:23:09.909067 RX Vref Scan: 1
7869 00:23:09.909154
7870 00:23:09.912321 Set Vref Range= 24 -> 127
7871 00:23:09.912415
7872 00:23:09.915684 RX Vref 24 -> 127, step: 1
7873 00:23:09.915755
7874 00:23:09.918640 RX Delay 11 -> 252, step: 4
7875 00:23:09.918740
7876 00:23:09.921916 Set Vref, RX VrefLevel [Byte0]: 24
7877 00:23:09.925328 [Byte1]: 24
7878 00:23:09.925427
7879 00:23:09.928289 Set Vref, RX VrefLevel [Byte0]: 25
7880 00:23:09.931888 [Byte1]: 25
7881 00:23:09.932012
7882 00:23:09.934868 Set Vref, RX VrefLevel [Byte0]: 26
7883 00:23:09.938473 [Byte1]: 26
7884 00:23:09.941543
7885 00:23:09.941612 Set Vref, RX VrefLevel [Byte0]: 27
7886 00:23:09.945024 [Byte1]: 27
7887 00:23:09.949137
7888 00:23:09.949222 Set Vref, RX VrefLevel [Byte0]: 28
7889 00:23:09.952833 [Byte1]: 28
7890 00:23:09.957263
7891 00:23:09.957358 Set Vref, RX VrefLevel [Byte0]: 29
7892 00:23:09.960148 [Byte1]: 29
7893 00:23:09.964439
7894 00:23:09.964548 Set Vref, RX VrefLevel [Byte0]: 30
7895 00:23:09.967483 [Byte1]: 30
7896 00:23:09.972230
7897 00:23:09.972305 Set Vref, RX VrefLevel [Byte0]: 31
7898 00:23:09.975613 [Byte1]: 31
7899 00:23:09.979755
7900 00:23:09.979860 Set Vref, RX VrefLevel [Byte0]: 32
7901 00:23:09.982870 [Byte1]: 32
7902 00:23:09.987314
7903 00:23:09.987416 Set Vref, RX VrefLevel [Byte0]: 33
7904 00:23:09.990616 [Byte1]: 33
7905 00:23:09.995345
7906 00:23:09.995432 Set Vref, RX VrefLevel [Byte0]: 34
7907 00:23:09.998510 [Byte1]: 34
7908 00:23:10.002557
7909 00:23:10.002655 Set Vref, RX VrefLevel [Byte0]: 35
7910 00:23:10.005597 [Byte1]: 35
7911 00:23:10.010387
7912 00:23:10.010461 Set Vref, RX VrefLevel [Byte0]: 36
7913 00:23:10.013404 [Byte1]: 36
7914 00:23:10.018095
7915 00:23:10.018243 Set Vref, RX VrefLevel [Byte0]: 37
7916 00:23:10.020811 [Byte1]: 37
7917 00:23:10.025604
7918 00:23:10.025707 Set Vref, RX VrefLevel [Byte0]: 38
7919 00:23:10.028455 [Byte1]: 38
7920 00:23:10.032835
7921 00:23:10.032945 Set Vref, RX VrefLevel [Byte0]: 39
7922 00:23:10.036504 [Byte1]: 39
7923 00:23:10.040753
7924 00:23:10.040854 Set Vref, RX VrefLevel [Byte0]: 40
7925 00:23:10.043662 [Byte1]: 40
7926 00:23:10.047973
7927 00:23:10.048073 Set Vref, RX VrefLevel [Byte0]: 41
7928 00:23:10.051381 [Byte1]: 41
7929 00:23:10.055505
7930 00:23:10.055604 Set Vref, RX VrefLevel [Byte0]: 42
7931 00:23:10.059184 [Byte1]: 42
7932 00:23:10.063491
7933 00:23:10.063592 Set Vref, RX VrefLevel [Byte0]: 43
7934 00:23:10.066623 [Byte1]: 43
7935 00:23:10.070906
7936 00:23:10.071006 Set Vref, RX VrefLevel [Byte0]: 44
7937 00:23:10.074078 [Byte1]: 44
7938 00:23:10.078720
7939 00:23:10.078821 Set Vref, RX VrefLevel [Byte0]: 45
7940 00:23:10.081656 [Byte1]: 45
7941 00:23:10.086420
7942 00:23:10.086499 Set Vref, RX VrefLevel [Byte0]: 46
7943 00:23:10.089430 [Byte1]: 46
7944 00:23:10.093792
7945 00:23:10.093867 Set Vref, RX VrefLevel [Byte0]: 47
7946 00:23:10.097044 [Byte1]: 47
7947 00:23:10.101336
7948 00:23:10.101438 Set Vref, RX VrefLevel [Byte0]: 48
7949 00:23:10.104926 [Byte1]: 48
7950 00:23:10.109290
7951 00:23:10.109366 Set Vref, RX VrefLevel [Byte0]: 49
7952 00:23:10.112451 [Byte1]: 49
7953 00:23:10.116815
7954 00:23:10.116920 Set Vref, RX VrefLevel [Byte0]: 50
7955 00:23:10.119744 [Byte1]: 50
7956 00:23:10.124321
7957 00:23:10.124422 Set Vref, RX VrefLevel [Byte0]: 51
7958 00:23:10.127618 [Byte1]: 51
7959 00:23:10.132315
7960 00:23:10.132423 Set Vref, RX VrefLevel [Byte0]: 52
7961 00:23:10.135227 [Byte1]: 52
7962 00:23:10.139824
7963 00:23:10.139925 Set Vref, RX VrefLevel [Byte0]: 53
7964 00:23:10.142966 [Byte1]: 53
7965 00:23:10.146887
7966 00:23:10.146989 Set Vref, RX VrefLevel [Byte0]: 54
7967 00:23:10.150357 [Byte1]: 54
7968 00:23:10.154765
7969 00:23:10.154870 Set Vref, RX VrefLevel [Byte0]: 55
7970 00:23:10.157871 [Byte1]: 55
7971 00:23:10.162108
7972 00:23:10.162246 Set Vref, RX VrefLevel [Byte0]: 56
7973 00:23:10.165808 [Byte1]: 56
7974 00:23:10.170037
7975 00:23:10.170137 Set Vref, RX VrefLevel [Byte0]: 57
7976 00:23:10.173140 [Byte1]: 57
7977 00:23:10.177463
7978 00:23:10.177566 Set Vref, RX VrefLevel [Byte0]: 58
7979 00:23:10.180988 [Byte1]: 58
7980 00:23:10.185174
7981 00:23:10.185276 Set Vref, RX VrefLevel [Byte0]: 59
7982 00:23:10.188840 [Byte1]: 59
7983 00:23:10.192972
7984 00:23:10.193073 Set Vref, RX VrefLevel [Byte0]: 60
7985 00:23:10.196047 [Byte1]: 60
7986 00:23:10.200271
7987 00:23:10.200398 Set Vref, RX VrefLevel [Byte0]: 61
7988 00:23:10.203543 [Byte1]: 61
7989 00:23:10.207926
7990 00:23:10.208033 Set Vref, RX VrefLevel [Byte0]: 62
7991 00:23:10.211168 [Byte1]: 62
7992 00:23:10.215546
7993 00:23:10.215647 Set Vref, RX VrefLevel [Byte0]: 63
7994 00:23:10.219192 [Byte1]: 63
7995 00:23:10.223071
7996 00:23:10.223150 Set Vref, RX VrefLevel [Byte0]: 64
7997 00:23:10.226766 [Byte1]: 64
7998 00:23:10.230767
7999 00:23:10.230879 Set Vref, RX VrefLevel [Byte0]: 65
8000 00:23:10.234258 [Byte1]: 65
8001 00:23:10.238424
8002 00:23:10.238498 Set Vref, RX VrefLevel [Byte0]: 66
8003 00:23:10.242125 [Byte1]: 66
8004 00:23:10.246134
8005 00:23:10.246254 Set Vref, RX VrefLevel [Byte0]: 67
8006 00:23:10.249199 [Byte1]: 67
8007 00:23:10.253603
8008 00:23:10.253707 Set Vref, RX VrefLevel [Byte0]: 68
8009 00:23:10.256940 [Byte1]: 68
8010 00:23:10.261093
8011 00:23:10.261195 Set Vref, RX VrefLevel [Byte0]: 69
8012 00:23:10.264589 [Byte1]: 69
8013 00:23:10.268969
8014 00:23:10.269070 Set Vref, RX VrefLevel [Byte0]: 70
8015 00:23:10.272460 [Byte1]: 70
8016 00:23:10.276923
8017 00:23:10.277020 Set Vref, RX VrefLevel [Byte0]: 71
8018 00:23:10.279961 [Byte1]: 71
8019 00:23:10.284304
8020 00:23:10.284402 Set Vref, RX VrefLevel [Byte0]: 72
8021 00:23:10.287337 [Byte1]: 72
8022 00:23:10.292089
8023 00:23:10.292164 Set Vref, RX VrefLevel [Byte0]: 73
8024 00:23:10.295111 [Byte1]: 73
8025 00:23:10.299378
8026 00:23:10.299481 Set Vref, RX VrefLevel [Byte0]: 74
8027 00:23:10.303156 [Byte1]: 74
8028 00:23:10.307037
8029 00:23:10.307123 Set Vref, RX VrefLevel [Byte0]: 75
8030 00:23:10.310498 [Byte1]: 75
8031 00:23:10.314500
8032 00:23:10.314577 Set Vref, RX VrefLevel [Byte0]: 76
8033 00:23:10.317574 [Byte1]: 76
8034 00:23:10.322441
8035 00:23:10.322516 Set Vref, RX VrefLevel [Byte0]: 77
8036 00:23:10.325290 [Byte1]: 77
8037 00:23:10.329880
8038 00:23:10.329991 Set Vref, RX VrefLevel [Byte0]: 78
8039 00:23:10.333338 [Byte1]: 78
8040 00:23:10.337859
8041 00:23:10.337985 Final RX Vref Byte 0 = 66 to rank0
8042 00:23:10.340689 Final RX Vref Byte 1 = 59 to rank0
8043 00:23:10.343916 Final RX Vref Byte 0 = 66 to rank1
8044 00:23:10.347428 Final RX Vref Byte 1 = 59 to rank1==
8045 00:23:10.350381 Dram Type= 6, Freq= 0, CH_0, rank 0
8046 00:23:10.357580 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8047 00:23:10.357694 ==
8048 00:23:10.357788 DQS Delay:
8049 00:23:10.360382 DQS0 = 0, DQS1 = 0
8050 00:23:10.360479 DQM Delay:
8051 00:23:10.360572 DQM0 = 133, DQM1 = 122
8052 00:23:10.363993 DQ Delay:
8053 00:23:10.367290 DQ0 =130, DQ1 =136, DQ2 =132, DQ3 =132
8054 00:23:10.370549 DQ4 =134, DQ5 =120, DQ6 =140, DQ7 =142
8055 00:23:10.373989 DQ8 =112, DQ9 =112, DQ10 =124, DQ11 =118
8056 00:23:10.376895 DQ12 =128, DQ13 =126, DQ14 =134, DQ15 =128
8057 00:23:10.376996
8058 00:23:10.377085
8059 00:23:10.377173
8060 00:23:10.380549 [DramC_TX_OE_Calibration] TA2
8061 00:23:10.383596 Original DQ_B0 (3 6) =30, OEN = 27
8062 00:23:10.387301 Original DQ_B1 (3 6) =30, OEN = 27
8063 00:23:10.390386 24, 0x0, End_B0=24 End_B1=24
8064 00:23:10.390498 25, 0x0, End_B0=25 End_B1=25
8065 00:23:10.393789 26, 0x0, End_B0=26 End_B1=26
8066 00:23:10.396616 27, 0x0, End_B0=27 End_B1=27
8067 00:23:10.400464 28, 0x0, End_B0=28 End_B1=28
8068 00:23:10.403335 29, 0x0, End_B0=29 End_B1=29
8069 00:23:10.403434 30, 0x0, End_B0=30 End_B1=30
8070 00:23:10.406589 31, 0x4141, End_B0=30 End_B1=30
8071 00:23:10.410093 Byte0 end_step=30 best_step=27
8072 00:23:10.413249 Byte1 end_step=30 best_step=27
8073 00:23:10.416593 Byte0 TX OE(2T, 0.5T) = (3, 3)
8074 00:23:10.420151 Byte1 TX OE(2T, 0.5T) = (3, 3)
8075 00:23:10.420249
8076 00:23:10.420338
8077 00:23:10.426207 [DQSOSCAuto] RK0, (LSB)MR18= 0x2112, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 393 ps
8078 00:23:10.429835 CH0 RK0: MR19=303, MR18=2112
8079 00:23:10.436540 CH0_RK0: MR19=0x303, MR18=0x2112, DQSOSC=393, MR23=63, INC=23, DEC=15
8080 00:23:10.436684
8081 00:23:10.439658 ----->DramcWriteLeveling(PI) begin...
8082 00:23:10.439751 ==
8083 00:23:10.443113 Dram Type= 6, Freq= 0, CH_0, rank 1
8084 00:23:10.446139 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8085 00:23:10.446278 ==
8086 00:23:10.449321 Write leveling (Byte 0): 36 => 36
8087 00:23:10.452658 Write leveling (Byte 1): 29 => 29
8088 00:23:10.455651 DramcWriteLeveling(PI) end<-----
8089 00:23:10.455749
8090 00:23:10.455841 ==
8091 00:23:10.459471 Dram Type= 6, Freq= 0, CH_0, rank 1
8092 00:23:10.465802 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8093 00:23:10.465914 ==
8094 00:23:10.466015 [Gating] SW mode calibration
8095 00:23:10.475749 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8096 00:23:10.479196 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8097 00:23:10.485573 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8098 00:23:10.489345 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8099 00:23:10.492284 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8100 00:23:10.498840 1 4 12 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
8101 00:23:10.501983 1 4 16 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 1)
8102 00:23:10.505623 1 4 20 | B1->B0 | 2727 3434 | 1 1 | (0 0) (1 1)
8103 00:23:10.512381 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8104 00:23:10.515446 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8105 00:23:10.518415 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8106 00:23:10.524988 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8107 00:23:10.528176 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8108 00:23:10.531749 1 5 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8109 00:23:10.538471 1 5 16 | B1->B0 | 3434 2727 | 1 0 | (1 0) (0 0)
8110 00:23:10.541594 1 5 20 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
8111 00:23:10.545160 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8112 00:23:10.551400 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8113 00:23:10.554978 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8114 00:23:10.558251 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8115 00:23:10.564401 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8116 00:23:10.568139 1 6 12 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
8117 00:23:10.571251 1 6 16 | B1->B0 | 2525 4343 | 0 0 | (0 0) (1 1)
8118 00:23:10.577755 1 6 20 | B1->B0 | 3c3c 4646 | 1 0 | (0 0) (0 0)
8119 00:23:10.581475 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8120 00:23:10.584208 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8121 00:23:10.587891 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8122 00:23:10.594501 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8123 00:23:10.597722 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8124 00:23:10.601266 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8125 00:23:10.607704 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8126 00:23:10.610887 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8127 00:23:10.614121 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8128 00:23:10.620859 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8129 00:23:10.624504 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8130 00:23:10.627578 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8131 00:23:10.634054 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8132 00:23:10.637405 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8133 00:23:10.640522 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8134 00:23:10.647220 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8135 00:23:10.650770 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8136 00:23:10.653651 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8137 00:23:10.660228 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8138 00:23:10.663871 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8139 00:23:10.666873 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8140 00:23:10.673501 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8141 00:23:10.676686 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8142 00:23:10.679933 Total UI for P1: 0, mck2ui 16
8143 00:23:10.683589 best dqsien dly found for B0: ( 1, 9, 10)
8144 00:23:10.686477 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8145 00:23:10.689944 Total UI for P1: 0, mck2ui 16
8146 00:23:10.693301 best dqsien dly found for B1: ( 1, 9, 16)
8147 00:23:10.696394 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8148 00:23:10.702913 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8149 00:23:10.703017
8150 00:23:10.706499 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8151 00:23:10.709554 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8152 00:23:10.712948 [Gating] SW calibration Done
8153 00:23:10.713047 ==
8154 00:23:10.716195 Dram Type= 6, Freq= 0, CH_0, rank 1
8155 00:23:10.719852 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8156 00:23:10.719952 ==
8157 00:23:10.722986 RX Vref Scan: 0
8158 00:23:10.723058
8159 00:23:10.723123 RX Vref 0 -> 0, step: 1
8160 00:23:10.723216
8161 00:23:10.726610 RX Delay 0 -> 252, step: 8
8162 00:23:10.729605 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8163 00:23:10.735876 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8164 00:23:10.739367 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8165 00:23:10.742752 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8166 00:23:10.746225 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8167 00:23:10.749355 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8168 00:23:10.755933 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8169 00:23:10.759481 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8170 00:23:10.762349 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8171 00:23:10.765663 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8172 00:23:10.768846 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8173 00:23:10.775523 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8174 00:23:10.779132 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8175 00:23:10.782040 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8176 00:23:10.785602 iDelay=200, Bit 14, Center 143 (88 ~ 199) 112
8177 00:23:10.792075 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8178 00:23:10.792175 ==
8179 00:23:10.795152 Dram Type= 6, Freq= 0, CH_0, rank 1
8180 00:23:10.798687 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8181 00:23:10.798794 ==
8182 00:23:10.798886 DQS Delay:
8183 00:23:10.802438 DQS0 = 0, DQS1 = 0
8184 00:23:10.802538 DQM Delay:
8185 00:23:10.805373 DQM0 = 132, DQM1 = 129
8186 00:23:10.805446 DQ Delay:
8187 00:23:10.808597 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
8188 00:23:10.812313 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8189 00:23:10.814994 DQ8 =119, DQ9 =115, DQ10 =131, DQ11 =123
8190 00:23:10.818630 DQ12 =131, DQ13 =135, DQ14 =143, DQ15 =135
8191 00:23:10.818729
8192 00:23:10.818820
8193 00:23:10.822147 ==
8194 00:23:10.825399 Dram Type= 6, Freq= 0, CH_0, rank 1
8195 00:23:10.828369 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8196 00:23:10.828473 ==
8197 00:23:10.828567
8198 00:23:10.828652
8199 00:23:10.831466 TX Vref Scan disable
8200 00:23:10.831560 == TX Byte 0 ==
8201 00:23:10.838110 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8202 00:23:10.841836 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8203 00:23:10.841947 == TX Byte 1 ==
8204 00:23:10.848289 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8205 00:23:10.851663 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8206 00:23:10.851762 ==
8207 00:23:10.855212 Dram Type= 6, Freq= 0, CH_0, rank 1
8208 00:23:10.858387 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8209 00:23:10.858487 ==
8210 00:23:10.871151
8211 00:23:10.874084 TX Vref early break, caculate TX vref
8212 00:23:10.877335 TX Vref=16, minBit 2, minWin=22, winSum=379
8213 00:23:10.880803 TX Vref=18, minBit 0, minWin=23, winSum=384
8214 00:23:10.884467 TX Vref=20, minBit 0, minWin=23, winSum=398
8215 00:23:10.887328 TX Vref=22, minBit 1, minWin=23, winSum=399
8216 00:23:10.890853 TX Vref=24, minBit 3, minWin=24, winSum=415
8217 00:23:10.897534 TX Vref=26, minBit 0, minWin=25, winSum=421
8218 00:23:10.900818 TX Vref=28, minBit 1, minWin=24, winSum=413
8219 00:23:10.903960 TX Vref=30, minBit 0, minWin=24, winSum=410
8220 00:23:10.907517 TX Vref=32, minBit 0, minWin=24, winSum=396
8221 00:23:10.914017 [TxChooseVref] Worse bit 0, Min win 25, Win sum 421, Final Vref 26
8222 00:23:10.914121
8223 00:23:10.917075 Final TX Range 0 Vref 26
8224 00:23:10.917153
8225 00:23:10.917216 ==
8226 00:23:10.920678 Dram Type= 6, Freq= 0, CH_0, rank 1
8227 00:23:10.923629 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8228 00:23:10.923746 ==
8229 00:23:10.923853
8230 00:23:10.923939
8231 00:23:10.926969 TX Vref Scan disable
8232 00:23:10.933547 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8233 00:23:10.933657 == TX Byte 0 ==
8234 00:23:10.936633 u2DelayCellOfst[0]=15 cells (4 PI)
8235 00:23:10.940105 u2DelayCellOfst[1]=18 cells (5 PI)
8236 00:23:10.943135 u2DelayCellOfst[2]=15 cells (4 PI)
8237 00:23:10.946799 u2DelayCellOfst[3]=18 cells (5 PI)
8238 00:23:10.949953 u2DelayCellOfst[4]=11 cells (3 PI)
8239 00:23:10.953598 u2DelayCellOfst[5]=0 cells (0 PI)
8240 00:23:10.956555 u2DelayCellOfst[6]=18 cells (5 PI)
8241 00:23:10.960080 u2DelayCellOfst[7]=22 cells (6 PI)
8242 00:23:10.963330 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8243 00:23:10.966399 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8244 00:23:10.969678 == TX Byte 1 ==
8245 00:23:10.973075 u2DelayCellOfst[8]=0 cells (0 PI)
8246 00:23:10.973180 u2DelayCellOfst[9]=3 cells (1 PI)
8247 00:23:10.975976 u2DelayCellOfst[10]=7 cells (2 PI)
8248 00:23:10.979566 u2DelayCellOfst[11]=3 cells (1 PI)
8249 00:23:10.983215 u2DelayCellOfst[12]=15 cells (4 PI)
8250 00:23:10.986353 u2DelayCellOfst[13]=15 cells (4 PI)
8251 00:23:10.989348 u2DelayCellOfst[14]=18 cells (5 PI)
8252 00:23:10.992717 u2DelayCellOfst[15]=11 cells (3 PI)
8253 00:23:10.996317 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8254 00:23:11.002941 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8255 00:23:11.003025 DramC Write-DBI on
8256 00:23:11.003122 ==
8257 00:23:11.005863 Dram Type= 6, Freq= 0, CH_0, rank 1
8258 00:23:11.012511 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8259 00:23:11.012618 ==
8260 00:23:11.012753
8261 00:23:11.012895
8262 00:23:11.012986 TX Vref Scan disable
8263 00:23:11.016533 == TX Byte 0 ==
8264 00:23:11.020162 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8265 00:23:11.023064 == TX Byte 1 ==
8266 00:23:11.026781 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8267 00:23:11.029845 DramC Write-DBI off
8268 00:23:11.029942
8269 00:23:11.030037 [DATLAT]
8270 00:23:11.030124 Freq=1600, CH0 RK1
8271 00:23:11.030242
8272 00:23:11.033364 DATLAT Default: 0xf
8273 00:23:11.033495 0, 0xFFFF, sum = 0
8274 00:23:11.036350 1, 0xFFFF, sum = 0
8275 00:23:11.039856 2, 0xFFFF, sum = 0
8276 00:23:11.039958 3, 0xFFFF, sum = 0
8277 00:23:11.043249 4, 0xFFFF, sum = 0
8278 00:23:11.043351 5, 0xFFFF, sum = 0
8279 00:23:11.046400 6, 0xFFFF, sum = 0
8280 00:23:11.046473 7, 0xFFFF, sum = 0
8281 00:23:11.049526 8, 0xFFFF, sum = 0
8282 00:23:11.049628 9, 0xFFFF, sum = 0
8283 00:23:11.053165 10, 0xFFFF, sum = 0
8284 00:23:11.053279 11, 0xFFFF, sum = 0
8285 00:23:11.056067 12, 0xFFFF, sum = 0
8286 00:23:11.056176 13, 0xFFFF, sum = 0
8287 00:23:11.059531 14, 0x0, sum = 1
8288 00:23:11.059634 15, 0x0, sum = 2
8289 00:23:11.062682 16, 0x0, sum = 3
8290 00:23:11.062780 17, 0x0, sum = 4
8291 00:23:11.066124 best_step = 15
8292 00:23:11.066217
8293 00:23:11.066281 ==
8294 00:23:11.069232 Dram Type= 6, Freq= 0, CH_0, rank 1
8295 00:23:11.072692 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8296 00:23:11.072791 ==
8297 00:23:11.076266 RX Vref Scan: 0
8298 00:23:11.076350
8299 00:23:11.076417 RX Vref 0 -> 0, step: 1
8300 00:23:11.076489
8301 00:23:11.079113 RX Delay 11 -> 252, step: 4
8302 00:23:11.085898 iDelay=195, Bit 0, Center 128 (79 ~ 178) 100
8303 00:23:11.089068 iDelay=195, Bit 1, Center 134 (83 ~ 186) 104
8304 00:23:11.092164 iDelay=195, Bit 2, Center 124 (71 ~ 178) 108
8305 00:23:11.095484 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
8306 00:23:11.099048 iDelay=195, Bit 4, Center 132 (79 ~ 186) 108
8307 00:23:11.105709 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8308 00:23:11.108902 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8309 00:23:11.112312 iDelay=195, Bit 7, Center 138 (87 ~ 190) 104
8310 00:23:11.115370 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8311 00:23:11.118957 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8312 00:23:11.125349 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8313 00:23:11.128846 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8314 00:23:11.131879 iDelay=195, Bit 12, Center 130 (79 ~ 182) 104
8315 00:23:11.134953 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8316 00:23:11.141546 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8317 00:23:11.145103 iDelay=195, Bit 15, Center 134 (83 ~ 186) 104
8318 00:23:11.145197 ==
8319 00:23:11.148351 Dram Type= 6, Freq= 0, CH_0, rank 1
8320 00:23:11.151950 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8321 00:23:11.152062 ==
8322 00:23:11.154776 DQS Delay:
8323 00:23:11.154877 DQS0 = 0, DQS1 = 0
8324 00:23:11.154980 DQM Delay:
8325 00:23:11.158096 DQM0 = 130, DQM1 = 126
8326 00:23:11.158215 DQ Delay:
8327 00:23:11.161619 DQ0 =128, DQ1 =134, DQ2 =124, DQ3 =126
8328 00:23:11.164711 DQ4 =132, DQ5 =120, DQ6 =138, DQ7 =138
8329 00:23:11.168575 DQ8 =116, DQ9 =112, DQ10 =128, DQ11 =120
8330 00:23:11.174579 DQ12 =130, DQ13 =132, DQ14 =136, DQ15 =134
8331 00:23:11.174657
8332 00:23:11.174719
8333 00:23:11.174778
8334 00:23:11.178132 [DramC_TX_OE_Calibration] TA2
8335 00:23:11.181258 Original DQ_B0 (3 6) =30, OEN = 27
8336 00:23:11.181336 Original DQ_B1 (3 6) =30, OEN = 27
8337 00:23:11.184813 24, 0x0, End_B0=24 End_B1=24
8338 00:23:11.188244 25, 0x0, End_B0=25 End_B1=25
8339 00:23:11.191587 26, 0x0, End_B0=26 End_B1=26
8340 00:23:11.194955 27, 0x0, End_B0=27 End_B1=27
8341 00:23:11.195039 28, 0x0, End_B0=28 End_B1=28
8342 00:23:11.197860 29, 0x0, End_B0=29 End_B1=29
8343 00:23:11.201446 30, 0x0, End_B0=30 End_B1=30
8344 00:23:11.204491 31, 0x4545, End_B0=30 End_B1=30
8345 00:23:11.207790 Byte0 end_step=30 best_step=27
8346 00:23:11.211224 Byte1 end_step=30 best_step=27
8347 00:23:11.211307 Byte0 TX OE(2T, 0.5T) = (3, 3)
8348 00:23:11.214534 Byte1 TX OE(2T, 0.5T) = (3, 3)
8349 00:23:11.214616
8350 00:23:11.214710
8351 00:23:11.224505 [DQSOSCAuto] RK1, (LSB)MR18= 0x2104, (MSB)MR19= 0x303, tDQSOscB0 = 408 ps tDQSOscB1 = 393 ps
8352 00:23:11.227703 CH0 RK1: MR19=303, MR18=2104
8353 00:23:11.231236 CH0_RK1: MR19=0x303, MR18=0x2104, DQSOSC=393, MR23=63, INC=23, DEC=15
8354 00:23:11.234180 [RxdqsGatingPostProcess] freq 1600
8355 00:23:11.240943 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8356 00:23:11.244367 best DQS0 dly(2T, 0.5T) = (1, 1)
8357 00:23:11.247567 best DQS1 dly(2T, 0.5T) = (1, 1)
8358 00:23:11.250548 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8359 00:23:11.254166 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8360 00:23:11.257406 best DQS0 dly(2T, 0.5T) = (1, 1)
8361 00:23:11.260378 best DQS1 dly(2T, 0.5T) = (1, 1)
8362 00:23:11.264012 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8363 00:23:11.264090 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8364 00:23:11.267002 Pre-setting of DQS Precalculation
8365 00:23:11.273929 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8366 00:23:11.274007 ==
8367 00:23:11.277100 Dram Type= 6, Freq= 0, CH_1, rank 0
8368 00:23:11.280138 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8369 00:23:11.280209 ==
8370 00:23:11.287029 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8371 00:23:11.289949 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8372 00:23:11.296592 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8373 00:23:11.300166 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8374 00:23:11.309900 [CA 0] Center 42 (13~72) winsize 60
8375 00:23:11.312957 [CA 1] Center 42 (13~72) winsize 60
8376 00:23:11.316529 [CA 2] Center 38 (9~67) winsize 59
8377 00:23:11.319712 [CA 3] Center 36 (7~66) winsize 60
8378 00:23:11.323069 [CA 4] Center 37 (8~67) winsize 60
8379 00:23:11.326276 [CA 5] Center 37 (8~67) winsize 60
8380 00:23:11.326359
8381 00:23:11.329478 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8382 00:23:11.329561
8383 00:23:11.336106 [CATrainingPosCal] consider 1 rank data
8384 00:23:11.336190 u2DelayCellTimex100 = 258/100 ps
8385 00:23:11.342929 CA0 delay=42 (13~72),Diff = 6 PI (22 cell)
8386 00:23:11.345878 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8387 00:23:11.349336 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8388 00:23:11.353017 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8389 00:23:11.356090 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8390 00:23:11.359185 CA5 delay=37 (8~67),Diff = 1 PI (3 cell)
8391 00:23:11.359267
8392 00:23:11.363020 CA PerBit enable=1, Macro0, CA PI delay=36
8393 00:23:11.363096
8394 00:23:11.365909 [CBTSetCACLKResult] CA Dly = 36
8395 00:23:11.369148 CS Dly: 9 (0~40)
8396 00:23:11.372806 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8397 00:23:11.375680 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8398 00:23:11.375759 ==
8399 00:23:11.379258 Dram Type= 6, Freq= 0, CH_1, rank 1
8400 00:23:11.385673 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8401 00:23:11.385758 ==
8402 00:23:11.389113 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8403 00:23:11.395768 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8404 00:23:11.398730 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8405 00:23:11.405024 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8406 00:23:11.412954 [CA 0] Center 42 (13~72) winsize 60
8407 00:23:11.416534 [CA 1] Center 42 (12~72) winsize 61
8408 00:23:11.419708 [CA 2] Center 37 (8~67) winsize 60
8409 00:23:11.422689 [CA 3] Center 37 (8~66) winsize 59
8410 00:23:11.426434 [CA 4] Center 37 (8~67) winsize 60
8411 00:23:11.429431 [CA 5] Center 36 (7~66) winsize 60
8412 00:23:11.429506
8413 00:23:11.432832 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8414 00:23:11.432957
8415 00:23:11.435993 [CATrainingPosCal] consider 2 rank data
8416 00:23:11.439633 u2DelayCellTimex100 = 258/100 ps
8417 00:23:11.445916 CA0 delay=42 (13~72),Diff = 5 PI (18 cell)
8418 00:23:11.449177 CA1 delay=42 (13~72),Diff = 5 PI (18 cell)
8419 00:23:11.452522 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8420 00:23:11.455747 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8421 00:23:11.459282 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8422 00:23:11.462791 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8423 00:23:11.462892
8424 00:23:11.465871 CA PerBit enable=1, Macro0, CA PI delay=37
8425 00:23:11.465970
8426 00:23:11.468889 [CBTSetCACLKResult] CA Dly = 37
8427 00:23:11.472617 CS Dly: 10 (0~43)
8428 00:23:11.475690 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8429 00:23:11.479206 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8430 00:23:11.479292
8431 00:23:11.482246 ----->DramcWriteLeveling(PI) begin...
8432 00:23:11.482333 ==
8433 00:23:11.485764 Dram Type= 6, Freq= 0, CH_1, rank 0
8434 00:23:11.492114 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8435 00:23:11.492190 ==
8436 00:23:11.495210 Write leveling (Byte 0): 24 => 24
8437 00:23:11.498502 Write leveling (Byte 1): 27 => 27
8438 00:23:11.498575 DramcWriteLeveling(PI) end<-----
8439 00:23:11.498642
8440 00:23:11.502084 ==
8441 00:23:11.505594 Dram Type= 6, Freq= 0, CH_1, rank 0
8442 00:23:11.508631 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8443 00:23:11.508702 ==
8444 00:23:11.512209 [Gating] SW mode calibration
8445 00:23:11.519024 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8446 00:23:11.521968 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8447 00:23:11.528535 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8448 00:23:11.532092 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8449 00:23:11.535101 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8450 00:23:11.541679 1 4 12 | B1->B0 | 302f 3131 | 1 1 | (0 0) (1 1)
8451 00:23:11.545225 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8452 00:23:11.548312 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8453 00:23:11.554863 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8454 00:23:11.558551 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8455 00:23:11.561384 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8456 00:23:11.568043 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8457 00:23:11.571514 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8458 00:23:11.574800 1 5 12 | B1->B0 | 2b2b 2323 | 0 0 | (0 1) (0 0)
8459 00:23:11.580998 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8460 00:23:11.584539 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8461 00:23:11.587671 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8462 00:23:11.594400 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8463 00:23:11.597745 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8464 00:23:11.601270 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8465 00:23:11.607624 1 6 8 | B1->B0 | 2525 3131 | 1 0 | (0 0) (0 0)
8466 00:23:11.610639 1 6 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
8467 00:23:11.614113 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8468 00:23:11.621022 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8469 00:23:11.624071 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8470 00:23:11.627548 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8471 00:23:11.633593 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8472 00:23:11.637207 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8473 00:23:11.640147 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8474 00:23:11.647419 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8475 00:23:11.650355 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8476 00:23:11.653398 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8477 00:23:11.660026 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8478 00:23:11.663512 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8479 00:23:11.666562 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8480 00:23:11.673211 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8481 00:23:11.676795 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8482 00:23:11.679771 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8483 00:23:11.686564 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8484 00:23:11.689996 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8485 00:23:11.693371 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8486 00:23:11.699812 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8487 00:23:11.703199 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8488 00:23:11.706479 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8489 00:23:11.713236 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8490 00:23:11.716250 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8491 00:23:11.719463 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8492 00:23:11.723151 Total UI for P1: 0, mck2ui 16
8493 00:23:11.726190 best dqsien dly found for B0: ( 1, 9, 10)
8494 00:23:11.733010 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8495 00:23:11.736058 Total UI for P1: 0, mck2ui 16
8496 00:23:11.739569 best dqsien dly found for B1: ( 1, 9, 14)
8497 00:23:11.742561 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8498 00:23:11.746251 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8499 00:23:11.746334
8500 00:23:11.749131 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8501 00:23:11.752768 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8502 00:23:11.755717 [Gating] SW calibration Done
8503 00:23:11.755799 ==
8504 00:23:11.759386 Dram Type= 6, Freq= 0, CH_1, rank 0
8505 00:23:11.762321 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8506 00:23:11.762407 ==
8507 00:23:11.765773 RX Vref Scan: 0
8508 00:23:11.765902
8509 00:23:11.768763 RX Vref 0 -> 0, step: 1
8510 00:23:11.768847
8511 00:23:11.768944 RX Delay 0 -> 252, step: 8
8512 00:23:11.775554 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8513 00:23:11.778999 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8514 00:23:11.782087 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8515 00:23:11.785816 iDelay=208, Bit 3, Center 139 (88 ~ 191) 104
8516 00:23:11.788867 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8517 00:23:11.795662 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8518 00:23:11.798689 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8519 00:23:11.801824 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8520 00:23:11.804998 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8521 00:23:11.808482 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8522 00:23:11.815086 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8523 00:23:11.818591 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8524 00:23:11.821894 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8525 00:23:11.825027 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8526 00:23:11.831354 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8527 00:23:11.834962 iDelay=208, Bit 15, Center 139 (88 ~ 191) 104
8528 00:23:11.835044 ==
8529 00:23:11.838094 Dram Type= 6, Freq= 0, CH_1, rank 0
8530 00:23:11.841866 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8531 00:23:11.841940 ==
8532 00:23:11.844721 DQS Delay:
8533 00:23:11.844792 DQS0 = 0, DQS1 = 0
8534 00:23:11.844852 DQM Delay:
8535 00:23:11.847736 DQM0 = 138, DQM1 = 130
8536 00:23:11.847807 DQ Delay:
8537 00:23:11.851353 DQ0 =143, DQ1 =131, DQ2 =127, DQ3 =139
8538 00:23:11.855005 DQ4 =135, DQ5 =151, DQ6 =147, DQ7 =135
8539 00:23:11.861542 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =123
8540 00:23:11.864566 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =139
8541 00:23:11.864642
8542 00:23:11.864706
8543 00:23:11.864764 ==
8544 00:23:11.867624 Dram Type= 6, Freq= 0, CH_1, rank 0
8545 00:23:11.871365 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8546 00:23:11.871440 ==
8547 00:23:11.871503
8548 00:23:11.871559
8549 00:23:11.874327 TX Vref Scan disable
8550 00:23:11.877345 == TX Byte 0 ==
8551 00:23:11.881026 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8552 00:23:11.883952 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8553 00:23:11.887689 == TX Byte 1 ==
8554 00:23:11.890602 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8555 00:23:11.894365 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8556 00:23:11.894435 ==
8557 00:23:11.897479 Dram Type= 6, Freq= 0, CH_1, rank 0
8558 00:23:11.903516 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8559 00:23:11.903589 ==
8560 00:23:11.913832
8561 00:23:11.917377 TX Vref early break, caculate TX vref
8562 00:23:11.920545 TX Vref=16, minBit 0, minWin=22, winSum=375
8563 00:23:11.923779 TX Vref=18, minBit 5, minWin=22, winSum=385
8564 00:23:11.927282 TX Vref=20, minBit 0, minWin=23, winSum=393
8565 00:23:11.930137 TX Vref=22, minBit 0, minWin=24, winSum=407
8566 00:23:11.933502 TX Vref=24, minBit 0, minWin=24, winSum=416
8567 00:23:11.940076 TX Vref=26, minBit 0, minWin=25, winSum=421
8568 00:23:11.943589 TX Vref=28, minBit 1, minWin=26, winSum=425
8569 00:23:11.947001 TX Vref=30, minBit 5, minWin=25, winSum=415
8570 00:23:11.949916 TX Vref=32, minBit 5, minWin=23, winSum=402
8571 00:23:11.956943 [TxChooseVref] Worse bit 1, Min win 26, Win sum 425, Final Vref 28
8572 00:23:11.957020
8573 00:23:11.960013 Final TX Range 0 Vref 28
8574 00:23:11.960088
8575 00:23:11.960149 ==
8576 00:23:11.963696 Dram Type= 6, Freq= 0, CH_1, rank 0
8577 00:23:11.966510 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8578 00:23:11.966598 ==
8579 00:23:11.966675
8580 00:23:11.966767
8581 00:23:11.970299 TX Vref Scan disable
8582 00:23:11.976547 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8583 00:23:11.976621 == TX Byte 0 ==
8584 00:23:11.980094 u2DelayCellOfst[0]=18 cells (5 PI)
8585 00:23:11.983069 u2DelayCellOfst[1]=11 cells (3 PI)
8586 00:23:11.986694 u2DelayCellOfst[2]=0 cells (0 PI)
8587 00:23:11.989635 u2DelayCellOfst[3]=3 cells (1 PI)
8588 00:23:11.993364 u2DelayCellOfst[4]=7 cells (2 PI)
8589 00:23:11.996567 u2DelayCellOfst[5]=22 cells (6 PI)
8590 00:23:11.999522 u2DelayCellOfst[6]=18 cells (5 PI)
8591 00:23:11.999601 u2DelayCellOfst[7]=3 cells (1 PI)
8592 00:23:12.006204 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8593 00:23:12.009804 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8594 00:23:12.009904 == TX Byte 1 ==
8595 00:23:12.012570 u2DelayCellOfst[8]=0 cells (0 PI)
8596 00:23:12.016215 u2DelayCellOfst[9]=3 cells (1 PI)
8597 00:23:12.019178 u2DelayCellOfst[10]=11 cells (3 PI)
8598 00:23:12.022857 u2DelayCellOfst[11]=7 cells (2 PI)
8599 00:23:12.025828 u2DelayCellOfst[12]=15 cells (4 PI)
8600 00:23:12.029239 u2DelayCellOfst[13]=18 cells (5 PI)
8601 00:23:12.032529 u2DelayCellOfst[14]=18 cells (5 PI)
8602 00:23:12.035880 u2DelayCellOfst[15]=18 cells (5 PI)
8603 00:23:12.038972 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8604 00:23:12.045833 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8605 00:23:12.045949 DramC Write-DBI on
8606 00:23:12.046060 ==
8607 00:23:12.048849 Dram Type= 6, Freq= 0, CH_1, rank 0
8608 00:23:12.055677 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8609 00:23:12.055760 ==
8610 00:23:12.055860
8611 00:23:12.055919
8612 00:23:12.055977 TX Vref Scan disable
8613 00:23:12.059738 == TX Byte 0 ==
8614 00:23:12.062470 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8615 00:23:12.066264 == TX Byte 1 ==
8616 00:23:12.069102 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8617 00:23:12.072804 DramC Write-DBI off
8618 00:23:12.072886
8619 00:23:12.072983 [DATLAT]
8620 00:23:12.073076 Freq=1600, CH1 RK0
8621 00:23:12.073152
8622 00:23:12.076013 DATLAT Default: 0xf
8623 00:23:12.078934 0, 0xFFFF, sum = 0
8624 00:23:12.079018 1, 0xFFFF, sum = 0
8625 00:23:12.082072 2, 0xFFFF, sum = 0
8626 00:23:12.082157 3, 0xFFFF, sum = 0
8627 00:23:12.085704 4, 0xFFFF, sum = 0
8628 00:23:12.085788 5, 0xFFFF, sum = 0
8629 00:23:12.088928 6, 0xFFFF, sum = 0
8630 00:23:12.089011 7, 0xFFFF, sum = 0
8631 00:23:12.092022 8, 0xFFFF, sum = 0
8632 00:23:12.092109 9, 0xFFFF, sum = 0
8633 00:23:12.095503 10, 0xFFFF, sum = 0
8634 00:23:12.095603 11, 0xFFFF, sum = 0
8635 00:23:12.099092 12, 0xFFFF, sum = 0
8636 00:23:12.099175 13, 0xFFFF, sum = 0
8637 00:23:12.102129 14, 0x0, sum = 1
8638 00:23:12.102241 15, 0x0, sum = 2
8639 00:23:12.105246 16, 0x0, sum = 3
8640 00:23:12.105329 17, 0x0, sum = 4
8641 00:23:12.108940 best_step = 15
8642 00:23:12.109027
8643 00:23:12.109119 ==
8644 00:23:12.112115 Dram Type= 6, Freq= 0, CH_1, rank 0
8645 00:23:12.115325 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8646 00:23:12.115408 ==
8647 00:23:12.118832 RX Vref Scan: 1
8648 00:23:12.118914
8649 00:23:12.118978 Set Vref Range= 24 -> 127
8650 00:23:12.119038
8651 00:23:12.121848 RX Vref 24 -> 127, step: 1
8652 00:23:12.121929
8653 00:23:12.125371 RX Delay 19 -> 252, step: 4
8654 00:23:12.125452
8655 00:23:12.128490 Set Vref, RX VrefLevel [Byte0]: 24
8656 00:23:12.131927 [Byte1]: 24
8657 00:23:12.132009
8658 00:23:12.134973 Set Vref, RX VrefLevel [Byte0]: 25
8659 00:23:12.138381 [Byte1]: 25
8660 00:23:12.142056
8661 00:23:12.142185 Set Vref, RX VrefLevel [Byte0]: 26
8662 00:23:12.145507 [Byte1]: 26
8663 00:23:12.149966
8664 00:23:12.150074 Set Vref, RX VrefLevel [Byte0]: 27
8665 00:23:12.152768 [Byte1]: 27
8666 00:23:12.157370
8667 00:23:12.157451 Set Vref, RX VrefLevel [Byte0]: 28
8668 00:23:12.160523 [Byte1]: 28
8669 00:23:12.164990
8670 00:23:12.165072 Set Vref, RX VrefLevel [Byte0]: 29
8671 00:23:12.168085 [Byte1]: 29
8672 00:23:12.172480
8673 00:23:12.172583 Set Vref, RX VrefLevel [Byte0]: 30
8674 00:23:12.175420 [Byte1]: 30
8675 00:23:12.179809
8676 00:23:12.179893 Set Vref, RX VrefLevel [Byte0]: 31
8677 00:23:12.183489 [Byte1]: 31
8678 00:23:12.187631
8679 00:23:12.187705 Set Vref, RX VrefLevel [Byte0]: 32
8680 00:23:12.190702 [Byte1]: 32
8681 00:23:12.194848
8682 00:23:12.194924 Set Vref, RX VrefLevel [Byte0]: 33
8683 00:23:12.198335 [Byte1]: 33
8684 00:23:12.202737
8685 00:23:12.202821 Set Vref, RX VrefLevel [Byte0]: 34
8686 00:23:12.205676 [Byte1]: 34
8687 00:23:12.210506
8688 00:23:12.210588 Set Vref, RX VrefLevel [Byte0]: 35
8689 00:23:12.213669 [Byte1]: 35
8690 00:23:12.217827
8691 00:23:12.217909 Set Vref, RX VrefLevel [Byte0]: 36
8692 00:23:12.221255 [Byte1]: 36
8693 00:23:12.225459
8694 00:23:12.225542 Set Vref, RX VrefLevel [Byte0]: 37
8695 00:23:12.228384 [Byte1]: 37
8696 00:23:12.233043
8697 00:23:12.233123 Set Vref, RX VrefLevel [Byte0]: 38
8698 00:23:12.235842 [Byte1]: 38
8699 00:23:12.240185
8700 00:23:12.240293 Set Vref, RX VrefLevel [Byte0]: 39
8701 00:23:12.243925 [Byte1]: 39
8702 00:23:12.248328
8703 00:23:12.248415 Set Vref, RX VrefLevel [Byte0]: 40
8704 00:23:12.251042 [Byte1]: 40
8705 00:23:12.255517
8706 00:23:12.255602 Set Vref, RX VrefLevel [Byte0]: 41
8707 00:23:12.259076 [Byte1]: 41
8708 00:23:12.263238
8709 00:23:12.263312 Set Vref, RX VrefLevel [Byte0]: 42
8710 00:23:12.266417 [Byte1]: 42
8711 00:23:12.270918
8712 00:23:12.270994 Set Vref, RX VrefLevel [Byte0]: 43
8713 00:23:12.274171 [Byte1]: 43
8714 00:23:12.278669
8715 00:23:12.278761 Set Vref, RX VrefLevel [Byte0]: 44
8716 00:23:12.281494 [Byte1]: 44
8717 00:23:12.285729
8718 00:23:12.285821 Set Vref, RX VrefLevel [Byte0]: 45
8719 00:23:12.289295 [Byte1]: 45
8720 00:23:12.293743
8721 00:23:12.293819 Set Vref, RX VrefLevel [Byte0]: 46
8722 00:23:12.296716 [Byte1]: 46
8723 00:23:12.301045
8724 00:23:12.301118 Set Vref, RX VrefLevel [Byte0]: 47
8725 00:23:12.304472 [Byte1]: 47
8726 00:23:12.309077
8727 00:23:12.309152 Set Vref, RX VrefLevel [Byte0]: 48
8728 00:23:12.311934 [Byte1]: 48
8729 00:23:12.316078
8730 00:23:12.316150 Set Vref, RX VrefLevel [Byte0]: 49
8731 00:23:12.319263 [Byte1]: 49
8732 00:23:12.323686
8733 00:23:12.323763 Set Vref, RX VrefLevel [Byte0]: 50
8734 00:23:12.327228 [Byte1]: 50
8735 00:23:12.331392
8736 00:23:12.331466 Set Vref, RX VrefLevel [Byte0]: 51
8737 00:23:12.334481 [Byte1]: 51
8738 00:23:12.339088
8739 00:23:12.339165 Set Vref, RX VrefLevel [Byte0]: 52
8740 00:23:12.342089 [Byte1]: 52
8741 00:23:12.346285
8742 00:23:12.346364 Set Vref, RX VrefLevel [Byte0]: 53
8743 00:23:12.350021 [Byte1]: 53
8744 00:23:12.354038
8745 00:23:12.354151 Set Vref, RX VrefLevel [Byte0]: 54
8746 00:23:12.357541 [Byte1]: 54
8747 00:23:12.361587
8748 00:23:12.361670 Set Vref, RX VrefLevel [Byte0]: 55
8749 00:23:12.365190 [Byte1]: 55
8750 00:23:12.369260
8751 00:23:12.369343 Set Vref, RX VrefLevel [Byte0]: 56
8752 00:23:12.372943 [Byte1]: 56
8753 00:23:12.376938
8754 00:23:12.377035 Set Vref, RX VrefLevel [Byte0]: 57
8755 00:23:12.380341 [Byte1]: 57
8756 00:23:12.384309
8757 00:23:12.384392 Set Vref, RX VrefLevel [Byte0]: 58
8758 00:23:12.387773 [Byte1]: 58
8759 00:23:12.391942
8760 00:23:12.392026 Set Vref, RX VrefLevel [Byte0]: 59
8761 00:23:12.394918 [Byte1]: 59
8762 00:23:12.399234
8763 00:23:12.399317 Set Vref, RX VrefLevel [Byte0]: 60
8764 00:23:12.402741 [Byte1]: 60
8765 00:23:12.406999
8766 00:23:12.407082 Set Vref, RX VrefLevel [Byte0]: 61
8767 00:23:12.410707 [Byte1]: 61
8768 00:23:12.414412
8769 00:23:12.414494 Set Vref, RX VrefLevel [Byte0]: 62
8770 00:23:12.418044 [Byte1]: 62
8771 00:23:12.422363
8772 00:23:12.422445 Set Vref, RX VrefLevel [Byte0]: 63
8773 00:23:12.425246 [Byte1]: 63
8774 00:23:12.429838
8775 00:23:12.429921 Set Vref, RX VrefLevel [Byte0]: 64
8776 00:23:12.433361 [Byte1]: 64
8777 00:23:12.437574
8778 00:23:12.437658 Set Vref, RX VrefLevel [Byte0]: 65
8779 00:23:12.440430 [Byte1]: 65
8780 00:23:12.445035
8781 00:23:12.445118 Set Vref, RX VrefLevel [Byte0]: 66
8782 00:23:12.448117 [Byte1]: 66
8783 00:23:12.452505
8784 00:23:12.452588 Set Vref, RX VrefLevel [Byte0]: 67
8785 00:23:12.456035 [Byte1]: 67
8786 00:23:12.459961
8787 00:23:12.460043 Set Vref, RX VrefLevel [Byte0]: 68
8788 00:23:12.463112 [Byte1]: 68
8789 00:23:12.467462
8790 00:23:12.467545 Set Vref, RX VrefLevel [Byte0]: 69
8791 00:23:12.470929 [Byte1]: 69
8792 00:23:12.474844
8793 00:23:12.474930 Set Vref, RX VrefLevel [Byte0]: 70
8794 00:23:12.478596 [Byte1]: 70
8795 00:23:12.482705
8796 00:23:12.482778 Set Vref, RX VrefLevel [Byte0]: 71
8797 00:23:12.486003 [Byte1]: 71
8798 00:23:12.490194
8799 00:23:12.490281 Set Vref, RX VrefLevel [Byte0]: 72
8800 00:23:12.493626 [Byte1]: 72
8801 00:23:12.498198
8802 00:23:12.498291 Set Vref, RX VrefLevel [Byte0]: 73
8803 00:23:12.501121 [Byte1]: 73
8804 00:23:12.505530
8805 00:23:12.505605 Final RX Vref Byte 0 = 53 to rank0
8806 00:23:12.508489 Final RX Vref Byte 1 = 60 to rank0
8807 00:23:12.512096 Final RX Vref Byte 0 = 53 to rank1
8808 00:23:12.515149 Final RX Vref Byte 1 = 60 to rank1==
8809 00:23:12.518752 Dram Type= 6, Freq= 0, CH_1, rank 0
8810 00:23:12.524919 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8811 00:23:12.525003 ==
8812 00:23:12.525069 DQS Delay:
8813 00:23:12.528507 DQS0 = 0, DQS1 = 0
8814 00:23:12.528590 DQM Delay:
8815 00:23:12.528654 DQM0 = 135, DQM1 = 129
8816 00:23:12.531573 DQ Delay:
8817 00:23:12.534930 DQ0 =142, DQ1 =128, DQ2 =124, DQ3 =132
8818 00:23:12.538426 DQ4 =132, DQ5 =148, DQ6 =144, DQ7 =130
8819 00:23:12.541922 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =120
8820 00:23:12.545010 DQ12 =138, DQ13 =138, DQ14 =138, DQ15 =138
8821 00:23:12.545094
8822 00:23:12.545158
8823 00:23:12.545219
8824 00:23:12.548456 [DramC_TX_OE_Calibration] TA2
8825 00:23:12.551844 Original DQ_B0 (3 6) =30, OEN = 27
8826 00:23:12.555077 Original DQ_B1 (3 6) =30, OEN = 27
8827 00:23:12.558674 24, 0x0, End_B0=24 End_B1=24
8828 00:23:12.558752 25, 0x0, End_B0=25 End_B1=25
8829 00:23:12.561598 26, 0x0, End_B0=26 End_B1=26
8830 00:23:12.565034 27, 0x0, End_B0=27 End_B1=27
8831 00:23:12.568135 28, 0x0, End_B0=28 End_B1=28
8832 00:23:12.571821 29, 0x0, End_B0=29 End_B1=29
8833 00:23:12.571899 30, 0x0, End_B0=30 End_B1=30
8834 00:23:12.574846 31, 0x4141, End_B0=30 End_B1=30
8835 00:23:12.578255 Byte0 end_step=30 best_step=27
8836 00:23:12.581457 Byte1 end_step=30 best_step=27
8837 00:23:12.585041 Byte0 TX OE(2T, 0.5T) = (3, 3)
8838 00:23:12.588196 Byte1 TX OE(2T, 0.5T) = (3, 3)
8839 00:23:12.588281
8840 00:23:12.588349
8841 00:23:12.594529 [DQSOSCAuto] RK0, (LSB)MR18= 0x180e, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
8842 00:23:12.597512 CH1 RK0: MR19=303, MR18=180E
8843 00:23:12.604300 CH1_RK0: MR19=0x303, MR18=0x180E, DQSOSC=397, MR23=63, INC=23, DEC=15
8844 00:23:12.604377
8845 00:23:12.607529 ----->DramcWriteLeveling(PI) begin...
8846 00:23:12.607609 ==
8847 00:23:12.611149 Dram Type= 6, Freq= 0, CH_1, rank 1
8848 00:23:12.614116 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8849 00:23:12.614230 ==
8850 00:23:12.617270 Write leveling (Byte 0): 24 => 24
8851 00:23:12.620911 Write leveling (Byte 1): 27 => 27
8852 00:23:12.623833 DramcWriteLeveling(PI) end<-----
8853 00:23:12.623906
8854 00:23:12.623966 ==
8855 00:23:12.627496 Dram Type= 6, Freq= 0, CH_1, rank 1
8856 00:23:12.634039 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8857 00:23:12.634118 ==
8858 00:23:12.634253 [Gating] SW mode calibration
8859 00:23:12.644074 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8860 00:23:12.647059 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8861 00:23:12.650532 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8862 00:23:12.656932 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8863 00:23:12.660752 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8864 00:23:12.663587 1 4 12 | B1->B0 | 3434 2424 | 1 1 | (1 1) (1 1)
8865 00:23:12.670290 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8866 00:23:12.673317 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8867 00:23:12.677011 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8868 00:23:12.683352 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8869 00:23:12.686678 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8870 00:23:12.690075 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8871 00:23:12.696522 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8872 00:23:12.700285 1 5 12 | B1->B0 | 2525 3434 | 0 0 | (1 0) (0 1)
8873 00:23:12.703444 1 5 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8874 00:23:12.709802 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8875 00:23:12.713113 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8876 00:23:12.716339 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8877 00:23:12.723045 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8878 00:23:12.726118 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8879 00:23:12.729960 1 6 8 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
8880 00:23:12.735966 1 6 12 | B1->B0 | 4646 2323 | 0 0 | (0 0) (0 0)
8881 00:23:12.739617 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8882 00:23:12.742580 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8883 00:23:12.749043 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8884 00:23:12.752597 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8885 00:23:12.755997 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8886 00:23:12.762694 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8887 00:23:12.765668 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8888 00:23:12.772221 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8889 00:23:12.775111 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8890 00:23:12.778838 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8891 00:23:12.785409 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8892 00:23:12.788427 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8893 00:23:12.791572 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8894 00:23:12.798406 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8895 00:23:12.801478 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8896 00:23:12.805170 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8897 00:23:12.811214 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8898 00:23:12.814687 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8899 00:23:12.818320 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8900 00:23:12.824284 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8901 00:23:12.827651 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8902 00:23:12.831153 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8903 00:23:12.838027 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8904 00:23:12.840947 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8905 00:23:12.844613 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8906 00:23:12.848069 Total UI for P1: 0, mck2ui 16
8907 00:23:12.851005 best dqsien dly found for B0: ( 1, 9, 10)
8908 00:23:12.854611 Total UI for P1: 0, mck2ui 16
8909 00:23:12.857603 best dqsien dly found for B1: ( 1, 9, 10)
8910 00:23:12.860988 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8911 00:23:12.864032 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8912 00:23:12.864108
8913 00:23:12.870715 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8914 00:23:12.874152 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8915 00:23:12.877313 [Gating] SW calibration Done
8916 00:23:12.877396 ==
8917 00:23:12.880227 Dram Type= 6, Freq= 0, CH_1, rank 1
8918 00:23:12.883996 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8919 00:23:12.884079 ==
8920 00:23:12.884145 RX Vref Scan: 0
8921 00:23:12.887159
8922 00:23:12.887242 RX Vref 0 -> 0, step: 1
8923 00:23:12.887307
8924 00:23:12.890578 RX Delay 0 -> 252, step: 8
8925 00:23:12.893701 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8926 00:23:12.896667 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8927 00:23:12.903289 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8928 00:23:12.906898 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8929 00:23:12.910171 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8930 00:23:12.913528 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8931 00:23:12.916736 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8932 00:23:12.923199 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8933 00:23:12.926358 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8934 00:23:12.929783 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8935 00:23:12.933140 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8936 00:23:12.936783 iDelay=208, Bit 11, Center 123 (64 ~ 183) 120
8937 00:23:12.943357 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8938 00:23:12.946546 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8939 00:23:12.949598 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8940 00:23:12.953083 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8941 00:23:12.956550 ==
8942 00:23:12.956644 Dram Type= 6, Freq= 0, CH_1, rank 1
8943 00:23:12.963120 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8944 00:23:12.963203 ==
8945 00:23:12.963270 DQS Delay:
8946 00:23:12.965992 DQS0 = 0, DQS1 = 0
8947 00:23:12.966100 DQM Delay:
8948 00:23:12.969437 DQM0 = 136, DQM1 = 130
8949 00:23:12.969519 DQ Delay:
8950 00:23:12.973024 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8951 00:23:12.975957 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8952 00:23:12.979429 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8953 00:23:12.983029 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =139
8954 00:23:12.983111
8955 00:23:12.983176
8956 00:23:12.983236 ==
8957 00:23:12.986092 Dram Type= 6, Freq= 0, CH_1, rank 1
8958 00:23:12.992613 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8959 00:23:12.992698 ==
8960 00:23:12.992801
8961 00:23:12.992862
8962 00:23:12.992920 TX Vref Scan disable
8963 00:23:12.996255 == TX Byte 0 ==
8964 00:23:12.999257 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8965 00:23:13.005968 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8966 00:23:13.006052 == TX Byte 1 ==
8967 00:23:13.009606 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8968 00:23:13.016199 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8969 00:23:13.016282 ==
8970 00:23:13.018997 Dram Type= 6, Freq= 0, CH_1, rank 1
8971 00:23:13.022131 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8972 00:23:13.022242 ==
8973 00:23:13.035406
8974 00:23:13.038538 TX Vref early break, caculate TX vref
8975 00:23:13.042047 TX Vref=16, minBit 0, minWin=23, winSum=383
8976 00:23:13.044935 TX Vref=18, minBit 0, minWin=23, winSum=388
8977 00:23:13.048255 TX Vref=20, minBit 1, minWin=24, winSum=402
8978 00:23:13.051461 TX Vref=22, minBit 1, minWin=24, winSum=410
8979 00:23:13.054620 TX Vref=24, minBit 1, minWin=25, winSum=420
8980 00:23:13.061758 TX Vref=26, minBit 0, minWin=25, winSum=427
8981 00:23:13.064930 TX Vref=28, minBit 0, minWin=25, winSum=423
8982 00:23:13.067910 TX Vref=30, minBit 0, minWin=23, winSum=419
8983 00:23:13.071487 TX Vref=32, minBit 0, minWin=23, winSum=408
8984 00:23:13.074680 TX Vref=34, minBit 0, minWin=24, winSum=399
8985 00:23:13.081182 [TxChooseVref] Worse bit 0, Min win 25, Win sum 427, Final Vref 26
8986 00:23:13.081266
8987 00:23:13.084675 Final TX Range 0 Vref 26
8988 00:23:13.084759
8989 00:23:13.084824 ==
8990 00:23:13.088278 Dram Type= 6, Freq= 0, CH_1, rank 1
8991 00:23:13.091185 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8992 00:23:13.091268 ==
8993 00:23:13.091333
8994 00:23:13.091393
8995 00:23:13.094799 TX Vref Scan disable
8996 00:23:13.101521 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8997 00:23:13.101604 == TX Byte 0 ==
8998 00:23:13.104511 u2DelayCellOfst[0]=26 cells (7 PI)
8999 00:23:13.107605 u2DelayCellOfst[1]=15 cells (4 PI)
9000 00:23:13.110768 u2DelayCellOfst[2]=0 cells (0 PI)
9001 00:23:13.114309 u2DelayCellOfst[3]=7 cells (2 PI)
9002 00:23:13.117915 u2DelayCellOfst[4]=11 cells (3 PI)
9003 00:23:13.121122 u2DelayCellOfst[5]=26 cells (7 PI)
9004 00:23:13.124085 u2DelayCellOfst[6]=26 cells (7 PI)
9005 00:23:13.127268 u2DelayCellOfst[7]=7 cells (2 PI)
9006 00:23:13.130655 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
9007 00:23:13.133905 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
9008 00:23:13.137412 == TX Byte 1 ==
9009 00:23:13.140699 u2DelayCellOfst[8]=0 cells (0 PI)
9010 00:23:13.140782 u2DelayCellOfst[9]=7 cells (2 PI)
9011 00:23:13.144327 u2DelayCellOfst[10]=15 cells (4 PI)
9012 00:23:13.147126 u2DelayCellOfst[11]=7 cells (2 PI)
9013 00:23:13.150740 u2DelayCellOfst[12]=15 cells (4 PI)
9014 00:23:13.153888 u2DelayCellOfst[13]=18 cells (5 PI)
9015 00:23:13.157330 u2DelayCellOfst[14]=22 cells (6 PI)
9016 00:23:13.160228 u2DelayCellOfst[15]=18 cells (5 PI)
9017 00:23:13.166897 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
9018 00:23:13.170172 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
9019 00:23:13.170269 DramC Write-DBI on
9020 00:23:13.170335 ==
9021 00:23:13.173348 Dram Type= 6, Freq= 0, CH_1, rank 1
9022 00:23:13.180451 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9023 00:23:13.180535 ==
9024 00:23:13.180599
9025 00:23:13.180659
9026 00:23:13.180718 TX Vref Scan disable
9027 00:23:13.184225 == TX Byte 0 ==
9028 00:23:13.187701 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
9029 00:23:13.190617 == TX Byte 1 ==
9030 00:23:13.194336 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
9031 00:23:13.197237 DramC Write-DBI off
9032 00:23:13.197319
9033 00:23:13.197384 [DATLAT]
9034 00:23:13.197444 Freq=1600, CH1 RK1
9035 00:23:13.197503
9036 00:23:13.201098 DATLAT Default: 0xf
9037 00:23:13.204043 0, 0xFFFF, sum = 0
9038 00:23:13.204129 1, 0xFFFF, sum = 0
9039 00:23:13.207681 2, 0xFFFF, sum = 0
9040 00:23:13.207765 3, 0xFFFF, sum = 0
9041 00:23:13.210795 4, 0xFFFF, sum = 0
9042 00:23:13.210882 5, 0xFFFF, sum = 0
9043 00:23:13.213862 6, 0xFFFF, sum = 0
9044 00:23:13.213946 7, 0xFFFF, sum = 0
9045 00:23:13.217123 8, 0xFFFF, sum = 0
9046 00:23:13.217207 9, 0xFFFF, sum = 0
9047 00:23:13.220590 10, 0xFFFF, sum = 0
9048 00:23:13.220673 11, 0xFFFF, sum = 0
9049 00:23:13.223949 12, 0xFFFF, sum = 0
9050 00:23:13.224033 13, 0xFFFF, sum = 0
9051 00:23:13.226904 14, 0x0, sum = 1
9052 00:23:13.226988 15, 0x0, sum = 2
9053 00:23:13.230623 16, 0x0, sum = 3
9054 00:23:13.230706 17, 0x0, sum = 4
9055 00:23:13.233521 best_step = 15
9056 00:23:13.233603
9057 00:23:13.233667 ==
9058 00:23:13.236935 Dram Type= 6, Freq= 0, CH_1, rank 1
9059 00:23:13.240225 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9060 00:23:13.240309 ==
9061 00:23:13.243812 RX Vref Scan: 0
9062 00:23:13.243896
9063 00:23:13.243964 RX Vref 0 -> 0, step: 1
9064 00:23:13.244025
9065 00:23:13.247087 RX Delay 11 -> 252, step: 4
9066 00:23:13.253459 iDelay=203, Bit 0, Center 138 (87 ~ 190) 104
9067 00:23:13.256600 iDelay=203, Bit 1, Center 128 (75 ~ 182) 108
9068 00:23:13.260179 iDelay=203, Bit 2, Center 122 (67 ~ 178) 112
9069 00:23:13.263425 iDelay=203, Bit 3, Center 130 (79 ~ 182) 104
9070 00:23:13.266930 iDelay=203, Bit 4, Center 134 (79 ~ 190) 112
9071 00:23:13.273333 iDelay=203, Bit 5, Center 144 (95 ~ 194) 100
9072 00:23:13.276409 iDelay=203, Bit 6, Center 146 (91 ~ 202) 112
9073 00:23:13.279612 iDelay=203, Bit 7, Center 130 (79 ~ 182) 104
9074 00:23:13.283110 iDelay=203, Bit 8, Center 112 (55 ~ 170) 116
9075 00:23:13.289353 iDelay=203, Bit 9, Center 116 (63 ~ 170) 108
9076 00:23:13.292515 iDelay=203, Bit 10, Center 128 (75 ~ 182) 108
9077 00:23:13.295931 iDelay=203, Bit 11, Center 116 (63 ~ 170) 108
9078 00:23:13.299579 iDelay=203, Bit 12, Center 136 (83 ~ 190) 108
9079 00:23:13.302579 iDelay=203, Bit 13, Center 134 (79 ~ 190) 112
9080 00:23:13.309018 iDelay=203, Bit 14, Center 132 (75 ~ 190) 116
9081 00:23:13.312828 iDelay=203, Bit 15, Center 138 (83 ~ 194) 112
9082 00:23:13.312911 ==
9083 00:23:13.315817 Dram Type= 6, Freq= 0, CH_1, rank 1
9084 00:23:13.319411 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9085 00:23:13.319494 ==
9086 00:23:13.322371 DQS Delay:
9087 00:23:13.322453 DQS0 = 0, DQS1 = 0
9088 00:23:13.322553 DQM Delay:
9089 00:23:13.326095 DQM0 = 134, DQM1 = 126
9090 00:23:13.326234 DQ Delay:
9091 00:23:13.329209 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =130
9092 00:23:13.332266 DQ4 =134, DQ5 =144, DQ6 =146, DQ7 =130
9093 00:23:13.339061 DQ8 =112, DQ9 =116, DQ10 =128, DQ11 =116
9094 00:23:13.341944 DQ12 =136, DQ13 =134, DQ14 =132, DQ15 =138
9095 00:23:13.342048
9096 00:23:13.342139
9097 00:23:13.342243
9098 00:23:13.345365 [DramC_TX_OE_Calibration] TA2
9099 00:23:13.348785 Original DQ_B0 (3 6) =30, OEN = 27
9100 00:23:13.352000 Original DQ_B1 (3 6) =30, OEN = 27
9101 00:23:13.352079 24, 0x0, End_B0=24 End_B1=24
9102 00:23:13.355444 25, 0x0, End_B0=25 End_B1=25
9103 00:23:13.358947 26, 0x0, End_B0=26 End_B1=26
9104 00:23:13.362082 27, 0x0, End_B0=27 End_B1=27
9105 00:23:13.365158 28, 0x0, End_B0=28 End_B1=28
9106 00:23:13.365243 29, 0x0, End_B0=29 End_B1=29
9107 00:23:13.368781 30, 0x0, End_B0=30 End_B1=30
9108 00:23:13.372346 31, 0x4545, End_B0=30 End_B1=30
9109 00:23:13.375346 Byte0 end_step=30 best_step=27
9110 00:23:13.378348 Byte1 end_step=30 best_step=27
9111 00:23:13.381936 Byte0 TX OE(2T, 0.5T) = (3, 3)
9112 00:23:13.382019 Byte1 TX OE(2T, 0.5T) = (3, 3)
9113 00:23:13.382084
9114 00:23:13.382144
9115 00:23:13.391600 [DQSOSCAuto] RK1, (LSB)MR18= 0xd0a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 403 ps
9116 00:23:13.394769 CH1 RK1: MR19=303, MR18=D0A
9117 00:23:13.398014 CH1_RK1: MR19=0x303, MR18=0xD0A, DQSOSC=403, MR23=63, INC=22, DEC=15
9118 00:23:13.401247 [RxdqsGatingPostProcess] freq 1600
9119 00:23:13.407802 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9120 00:23:13.411519 best DQS0 dly(2T, 0.5T) = (1, 1)
9121 00:23:13.414729 best DQS1 dly(2T, 0.5T) = (1, 1)
9122 00:23:13.417674 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9123 00:23:13.421376 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9124 00:23:13.424445 best DQS0 dly(2T, 0.5T) = (1, 1)
9125 00:23:13.427553 best DQS1 dly(2T, 0.5T) = (1, 1)
9126 00:23:13.431241 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9127 00:23:13.434261 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9128 00:23:13.437437 Pre-setting of DQS Precalculation
9129 00:23:13.441066 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9130 00:23:13.447735 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9131 00:23:13.454055 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9132 00:23:13.454193
9133 00:23:13.457498
9134 00:23:13.457604 [Calibration Summary] 3200 Mbps
9135 00:23:13.460426 CH 0, Rank 0
9136 00:23:13.460503 SW Impedance : PASS
9137 00:23:13.464153 DUTY Scan : NO K
9138 00:23:13.467502 ZQ Calibration : PASS
9139 00:23:13.467608 Jitter Meter : NO K
9140 00:23:13.470421 CBT Training : PASS
9141 00:23:13.473908 Write leveling : PASS
9142 00:23:13.474012 RX DQS gating : PASS
9143 00:23:13.477444 RX DQ/DQS(RDDQC) : PASS
9144 00:23:13.480555 TX DQ/DQS : PASS
9145 00:23:13.480664 RX DATLAT : PASS
9146 00:23:13.484176 RX DQ/DQS(Engine): PASS
9147 00:23:13.487223 TX OE : PASS
9148 00:23:13.487328 All Pass.
9149 00:23:13.487427
9150 00:23:13.487517 CH 0, Rank 1
9151 00:23:13.490770 SW Impedance : PASS
9152 00:23:13.493644 DUTY Scan : NO K
9153 00:23:13.493746 ZQ Calibration : PASS
9154 00:23:13.497401 Jitter Meter : NO K
9155 00:23:13.497475 CBT Training : PASS
9156 00:23:13.500311 Write leveling : PASS
9157 00:23:13.503469 RX DQS gating : PASS
9158 00:23:13.503547 RX DQ/DQS(RDDQC) : PASS
9159 00:23:13.506913 TX DQ/DQS : PASS
9160 00:23:13.510338 RX DATLAT : PASS
9161 00:23:13.510416 RX DQ/DQS(Engine): PASS
9162 00:23:13.513803 TX OE : PASS
9163 00:23:13.513903 All Pass.
9164 00:23:13.513999
9165 00:23:13.516599 CH 1, Rank 0
9166 00:23:13.516696 SW Impedance : PASS
9167 00:23:13.519973 DUTY Scan : NO K
9168 00:23:13.523334 ZQ Calibration : PASS
9169 00:23:13.523419 Jitter Meter : NO K
9170 00:23:13.526781 CBT Training : PASS
9171 00:23:13.529761 Write leveling : PASS
9172 00:23:13.529847 RX DQS gating : PASS
9173 00:23:13.533443 RX DQ/DQS(RDDQC) : PASS
9174 00:23:13.536549 TX DQ/DQS : PASS
9175 00:23:13.536633 RX DATLAT : PASS
9176 00:23:13.539652 RX DQ/DQS(Engine): PASS
9177 00:23:13.543200 TX OE : PASS
9178 00:23:13.543297 All Pass.
9179 00:23:13.543362
9180 00:23:13.543424 CH 1, Rank 1
9181 00:23:13.546278 SW Impedance : PASS
9182 00:23:13.549885 DUTY Scan : NO K
9183 00:23:13.549968 ZQ Calibration : PASS
9184 00:23:13.553071 Jitter Meter : NO K
9185 00:23:13.556503 CBT Training : PASS
9186 00:23:13.556595 Write leveling : PASS
9187 00:23:13.560058 RX DQS gating : PASS
9188 00:23:13.562881 RX DQ/DQS(RDDQC) : PASS
9189 00:23:13.562964 TX DQ/DQS : PASS
9190 00:23:13.566600 RX DATLAT : PASS
9191 00:23:13.569357 RX DQ/DQS(Engine): PASS
9192 00:23:13.569439 TX OE : PASS
9193 00:23:13.569505 All Pass.
9194 00:23:13.572849
9195 00:23:13.572931 DramC Write-DBI on
9196 00:23:13.576003 PER_BANK_REFRESH: Hybrid Mode
9197 00:23:13.576085 TX_TRACKING: ON
9198 00:23:13.586157 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9199 00:23:13.592898 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9200 00:23:13.602461 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9201 00:23:13.606080 [FAST_K] Save calibration result to emmc
9202 00:23:13.608841 sync common calibartion params.
9203 00:23:13.608924 sync cbt_mode0:1, 1:1
9204 00:23:13.612388 dram_init: ddr_geometry: 2
9205 00:23:13.615756 dram_init: ddr_geometry: 2
9206 00:23:13.615870 dram_init: ddr_geometry: 2
9207 00:23:13.618841 0:dram_rank_size:100000000
9208 00:23:13.622611 1:dram_rank_size:100000000
9209 00:23:13.628572 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9210 00:23:13.628658 DFS_SHUFFLE_HW_MODE: ON
9211 00:23:13.631915 dramc_set_vcore_voltage set vcore to 725000
9212 00:23:13.635532 Read voltage for 1600, 0
9213 00:23:13.635616 Vio18 = 0
9214 00:23:13.639039 Vcore = 725000
9215 00:23:13.639121 Vdram = 0
9216 00:23:13.639186 Vddq = 0
9217 00:23:13.642022 Vmddr = 0
9218 00:23:13.642104 switch to 3200 Mbps bootup
9219 00:23:13.645589 [DramcRunTimeConfig]
9220 00:23:13.645672 PHYPLL
9221 00:23:13.648684 DPM_CONTROL_AFTERK: ON
9222 00:23:13.648767 PER_BANK_REFRESH: ON
9223 00:23:13.651784 REFRESH_OVERHEAD_REDUCTION: ON
9224 00:23:13.655422 CMD_PICG_NEW_MODE: OFF
9225 00:23:13.655505 XRTWTW_NEW_MODE: ON
9226 00:23:13.658379 XRTRTR_NEW_MODE: ON
9227 00:23:13.658461 TX_TRACKING: ON
9228 00:23:13.661896 RDSEL_TRACKING: OFF
9229 00:23:13.664992 DQS Precalculation for DVFS: ON
9230 00:23:13.665075 RX_TRACKING: OFF
9231 00:23:13.668318 HW_GATING DBG: ON
9232 00:23:13.668464 ZQCS_ENABLE_LP4: ON
9233 00:23:13.671943 RX_PICG_NEW_MODE: ON
9234 00:23:13.672041 TX_PICG_NEW_MODE: ON
9235 00:23:13.674776 ENABLE_RX_DCM_DPHY: ON
9236 00:23:13.678543 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9237 00:23:13.681494 DUMMY_READ_FOR_TRACKING: OFF
9238 00:23:13.685072 !!! SPM_CONTROL_AFTERK: OFF
9239 00:23:13.685163 !!! SPM could not control APHY
9240 00:23:13.688366 IMPEDANCE_TRACKING: ON
9241 00:23:13.688449 TEMP_SENSOR: ON
9242 00:23:13.691373 HW_SAVE_FOR_SR: OFF
9243 00:23:13.694964 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9244 00:23:13.697889 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9245 00:23:13.701457 Read ODT Tracking: ON
9246 00:23:13.701539 Refresh Rate DeBounce: ON
9247 00:23:13.704630 DFS_NO_QUEUE_FLUSH: ON
9248 00:23:13.707822 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9249 00:23:13.711262 ENABLE_DFS_RUNTIME_MRW: OFF
9250 00:23:13.711348 DDR_RESERVE_NEW_MODE: ON
9251 00:23:13.714769 MR_CBT_SWITCH_FREQ: ON
9252 00:23:13.717780 =========================
9253 00:23:13.735831 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9254 00:23:13.738896 dram_init: ddr_geometry: 2
9255 00:23:13.757316 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9256 00:23:13.760442 dram_init: dram init end (result: 0)
9257 00:23:13.767029 DRAM-K: Full calibration passed in 24609 msecs
9258 00:23:13.770680 MRC: failed to locate region type 0.
9259 00:23:13.770764 DRAM rank0 size:0x100000000,
9260 00:23:13.773998 DRAM rank1 size=0x100000000
9261 00:23:13.783361 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9262 00:23:13.790099 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9263 00:23:13.796800 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9264 00:23:13.806352 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9265 00:23:13.806436 DRAM rank0 size:0x100000000,
9266 00:23:13.809922 DRAM rank1 size=0x100000000
9267 00:23:13.810005 CBMEM:
9268 00:23:13.812893 IMD: root @ 0xfffff000 254 entries.
9269 00:23:13.816419 IMD: root @ 0xffffec00 62 entries.
9270 00:23:13.819931 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9271 00:23:13.826013 WARNING: RO_VPD is uninitialized or empty.
9272 00:23:13.829549 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9273 00:23:13.837198 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9274 00:23:13.849945 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9275 00:23:13.861658 BS: romstage times (exec / console): total (unknown) / 24106 ms
9276 00:23:13.861745
9277 00:23:13.861810
9278 00:23:13.871308 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9279 00:23:13.875062 ARM64: Exception handlers installed.
9280 00:23:13.878003 ARM64: Testing exception
9281 00:23:13.881394 ARM64: Done test exception
9282 00:23:13.881476 Enumerating buses...
9283 00:23:13.884520 Show all devs... Before device enumeration.
9284 00:23:13.887988 Root Device: enabled 1
9285 00:23:13.891150 CPU_CLUSTER: 0: enabled 1
9286 00:23:13.891233 CPU: 00: enabled 1
9287 00:23:13.894321 Compare with tree...
9288 00:23:13.894404 Root Device: enabled 1
9289 00:23:13.897951 CPU_CLUSTER: 0: enabled 1
9290 00:23:13.900960 CPU: 00: enabled 1
9291 00:23:13.901043 Root Device scanning...
9292 00:23:13.904598 scan_static_bus for Root Device
9293 00:23:13.907513 CPU_CLUSTER: 0 enabled
9294 00:23:13.910884 scan_static_bus for Root Device done
9295 00:23:13.914208 scan_bus: bus Root Device finished in 8 msecs
9296 00:23:13.914317 done
9297 00:23:13.920899 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9298 00:23:13.924644 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9299 00:23:13.931169 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9300 00:23:13.934114 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9301 00:23:13.937773 Allocating resources...
9302 00:23:13.940899 Reading resources...
9303 00:23:13.944407 Root Device read_resources bus 0 link: 0
9304 00:23:13.947403 DRAM rank0 size:0x100000000,
9305 00:23:13.947480 DRAM rank1 size=0x100000000
9306 00:23:13.950613 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9307 00:23:13.954022 CPU: 00 missing read_resources
9308 00:23:13.960528 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9309 00:23:13.963497 Root Device read_resources bus 0 link: 0 done
9310 00:23:13.967288 Done reading resources.
9311 00:23:13.970338 Show resources in subtree (Root Device)...After reading.
9312 00:23:13.973597 Root Device child on link 0 CPU_CLUSTER: 0
9313 00:23:13.977198 CPU_CLUSTER: 0 child on link 0 CPU: 00
9314 00:23:13.986900 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9315 00:23:13.986984 CPU: 00
9316 00:23:13.990419 Root Device assign_resources, bus 0 link: 0
9317 00:23:13.993224 CPU_CLUSTER: 0 missing set_resources
9318 00:23:14.000179 Root Device assign_resources, bus 0 link: 0 done
9319 00:23:14.000263 Done setting resources.
9320 00:23:14.006760 Show resources in subtree (Root Device)...After assigning values.
9321 00:23:14.009730 Root Device child on link 0 CPU_CLUSTER: 0
9322 00:23:14.013439 CPU_CLUSTER: 0 child on link 0 CPU: 00
9323 00:23:14.023284 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9324 00:23:14.023368 CPU: 00
9325 00:23:14.026781 Done allocating resources.
9326 00:23:14.033215 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9327 00:23:14.033299 Enabling resources...
9328 00:23:14.036206 done.
9329 00:23:14.039795 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9330 00:23:14.042835 Initializing devices...
9331 00:23:14.042919 Root Device init
9332 00:23:14.046634 init hardware done!
9333 00:23:14.046716 0x00000018: ctrlr->caps
9334 00:23:14.049663 52.000 MHz: ctrlr->f_max
9335 00:23:14.052623 0.400 MHz: ctrlr->f_min
9336 00:23:14.052708 0x40ff8080: ctrlr->voltages
9337 00:23:14.056112 sclk: 390625
9338 00:23:14.056194 Bus Width = 1
9339 00:23:14.059382 sclk: 390625
9340 00:23:14.059465 Bus Width = 1
9341 00:23:14.062806 Early init status = 3
9342 00:23:14.065881 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9343 00:23:14.069438 in-header: 03 fc 00 00 01 00 00 00
9344 00:23:14.072344 in-data: 00
9345 00:23:14.075759 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9346 00:23:14.080006 in-header: 03 fd 00 00 00 00 00 00
9347 00:23:14.083636 in-data:
9348 00:23:14.086699 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9349 00:23:14.090947 in-header: 03 fc 00 00 01 00 00 00
9350 00:23:14.094318 in-data: 00
9351 00:23:14.097277 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9352 00:23:14.102696 in-header: 03 fd 00 00 00 00 00 00
9353 00:23:14.106329 in-data:
9354 00:23:14.109285 [SSUSB] Setting up USB HOST controller...
9355 00:23:14.112419 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9356 00:23:14.116115 [SSUSB] phy power-on done.
9357 00:23:14.119145 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9358 00:23:14.125801 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9359 00:23:14.128753 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9360 00:23:14.135723 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9361 00:23:14.141936 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9362 00:23:14.148928 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9363 00:23:14.155705 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9364 00:23:14.161868 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9365 00:23:14.165254 SPM: binary array size = 0x9dc
9366 00:23:14.168502 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9367 00:23:14.175384 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9368 00:23:14.182224 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9369 00:23:14.188555 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9370 00:23:14.191498 configure_display: Starting display init
9371 00:23:14.226298 anx7625_power_on_init: Init interface.
9372 00:23:14.229220 anx7625_disable_pd_protocol: Disabled PD feature.
9373 00:23:14.232260 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9374 00:23:14.260622 anx7625_start_dp_work: Secure OCM version=00
9375 00:23:14.263772 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9376 00:23:14.278464 sp_tx_get_edid_block: EDID Block = 1
9377 00:23:14.381182 Extracted contents:
9378 00:23:14.384373 header: 00 ff ff ff ff ff ff 00
9379 00:23:14.387796 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9380 00:23:14.390677 version: 01 04
9381 00:23:14.394120 basic params: 95 1f 11 78 0a
9382 00:23:14.397255 chroma info: 76 90 94 55 54 90 27 21 50 54
9383 00:23:14.400777 established: 00 00 00
9384 00:23:14.407541 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9385 00:23:14.413701 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9386 00:23:14.417040 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9387 00:23:14.423750 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9388 00:23:14.430326 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9389 00:23:14.433519 extensions: 00
9390 00:23:14.433598 checksum: fb
9391 00:23:14.433662
9392 00:23:14.440189 Manufacturer: IVO Model 57d Serial Number 0
9393 00:23:14.440274 Made week 0 of 2020
9394 00:23:14.443199 EDID version: 1.4
9395 00:23:14.443274 Digital display
9396 00:23:14.446944 6 bits per primary color channel
9397 00:23:14.449969 DisplayPort interface
9398 00:23:14.450068 Maximum image size: 31 cm x 17 cm
9399 00:23:14.452993 Gamma: 220%
9400 00:23:14.453065 Check DPMS levels
9401 00:23:14.460235 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9402 00:23:14.463122 First detailed timing is preferred timing
9403 00:23:14.466589 Established timings supported:
9404 00:23:14.466662 Standard timings supported:
9405 00:23:14.469978 Detailed timings
9406 00:23:14.473364 Hex of detail: 383680a07038204018303c0035ae10000019
9407 00:23:14.479192 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9408 00:23:14.482846 0780 0798 07c8 0820 hborder 0
9409 00:23:14.485897 0438 043b 0447 0458 vborder 0
9410 00:23:14.489443 -hsync -vsync
9411 00:23:14.489516 Did detailed timing
9412 00:23:14.495934 Hex of detail: 000000000000000000000000000000000000
9413 00:23:14.499425 Manufacturer-specified data, tag 0
9414 00:23:14.502378 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9415 00:23:14.505365 ASCII string: InfoVision
9416 00:23:14.509166 Hex of detail: 000000fe00523134304e574635205248200a
9417 00:23:14.512093 ASCII string: R140NWF5 RH
9418 00:23:14.512168 Checksum
9419 00:23:14.515336 Checksum: 0xfb (valid)
9420 00:23:14.518718 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9421 00:23:14.522312 DSI data_rate: 832800000 bps
9422 00:23:14.528949 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9423 00:23:14.531819 anx7625_parse_edid: pixelclock(138800).
9424 00:23:14.535399 hactive(1920), hsync(48), hfp(24), hbp(88)
9425 00:23:14.538617 vactive(1080), vsync(12), vfp(3), vbp(17)
9426 00:23:14.541875 anx7625_dsi_config: config dsi.
9427 00:23:14.548782 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9428 00:23:14.562937 anx7625_dsi_config: success to config DSI
9429 00:23:14.566449 anx7625_dp_start: MIPI phy setup OK.
9430 00:23:14.569514 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9431 00:23:14.573105 mtk_ddp_mode_set invalid vrefresh 60
9432 00:23:14.576170 main_disp_path_setup
9433 00:23:14.576243 ovl_layer_smi_id_en
9434 00:23:14.579375 ovl_layer_smi_id_en
9435 00:23:14.579463 ccorr_config
9436 00:23:14.579528 aal_config
9437 00:23:14.582747 gamma_config
9438 00:23:14.582821 postmask_config
9439 00:23:14.585982 dither_config
9440 00:23:14.589636 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9441 00:23:14.595765 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9442 00:23:14.599327 Root Device init finished in 552 msecs
9443 00:23:14.602606 CPU_CLUSTER: 0 init
9444 00:23:14.609185 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9445 00:23:14.615764 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9446 00:23:14.615862 APU_MBOX 0x190000b0 = 0x10001
9447 00:23:14.618699 APU_MBOX 0x190001b0 = 0x10001
9448 00:23:14.622357 APU_MBOX 0x190005b0 = 0x10001
9449 00:23:14.625289 APU_MBOX 0x190006b0 = 0x10001
9450 00:23:14.632353 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9451 00:23:14.641989 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9452 00:23:14.654090 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9453 00:23:14.660806 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9454 00:23:14.672420 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9455 00:23:14.681476 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9456 00:23:14.685109 CPU_CLUSTER: 0 init finished in 81 msecs
9457 00:23:14.688761 Devices initialized
9458 00:23:14.691590 Show all devs... After init.
9459 00:23:14.691692 Root Device: enabled 1
9460 00:23:14.694935 CPU_CLUSTER: 0: enabled 1
9461 00:23:14.698488 CPU: 00: enabled 1
9462 00:23:14.701526 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9463 00:23:14.704606 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9464 00:23:14.708146 ELOG: NV offset 0x57f000 size 0x1000
9465 00:23:14.714921 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9466 00:23:14.721563 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9467 00:23:14.724633 ELOG: Event(17) added with size 13 at 2024-06-21 00:23:14 UTC
9468 00:23:14.731169 out: cmd=0x121: 03 db 21 01 00 00 00 00
9469 00:23:14.734536 in-header: 03 4c 00 00 2c 00 00 00
9470 00:23:14.747846 in-data: f1 72 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9471 00:23:14.751323 ELOG: Event(A1) added with size 10 at 2024-06-21 00:23:14 UTC
9472 00:23:14.758021 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9473 00:23:14.764408 ELOG: Event(A0) added with size 9 at 2024-06-21 00:23:14 UTC
9474 00:23:14.767305 elog_add_boot_reason: Logged dev mode boot
9475 00:23:14.774255 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9476 00:23:14.774339 Finalize devices...
9477 00:23:14.777270 Devices finalized
9478 00:23:14.780389 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9479 00:23:14.783973 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9480 00:23:14.786888 in-header: 03 07 00 00 08 00 00 00
9481 00:23:14.790385 in-data: aa e4 47 04 13 02 00 00
9482 00:23:14.794189 Chrome EC: UHEPI supported
9483 00:23:14.800481 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9484 00:23:14.804016 in-header: 03 a9 00 00 08 00 00 00
9485 00:23:14.806999 in-data: 84 60 60 08 00 00 00 00
9486 00:23:14.813688 ELOG: Event(91) added with size 10 at 2024-06-21 00:23:14 UTC
9487 00:23:14.816955 Chrome EC: clear events_b mask to 0x0000000020004000
9488 00:23:14.823545 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9489 00:23:14.828592 in-header: 03 fd 00 00 00 00 00 00
9490 00:23:14.832437 in-data:
9491 00:23:14.835426 BS: BS_WRITE_TABLES entry times (exec / console): 3 / 46 ms
9492 00:23:14.838590 Writing coreboot table at 0xffe64000
9493 00:23:14.845194 0. 000000000010a000-0000000000113fff: RAMSTAGE
9494 00:23:14.848208 1. 0000000040000000-00000000400fffff: RAM
9495 00:23:14.852040 2. 0000000040100000-000000004032afff: RAMSTAGE
9496 00:23:14.854932 3. 000000004032b000-00000000545fffff: RAM
9497 00:23:14.858381 4. 0000000054600000-000000005465ffff: BL31
9498 00:23:14.861734 5. 0000000054660000-00000000ffe63fff: RAM
9499 00:23:14.868444 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9500 00:23:14.871259 7. 0000000100000000-000000023fffffff: RAM
9501 00:23:14.874778 Passing 5 GPIOs to payload:
9502 00:23:14.878182 NAME | PORT | POLARITY | VALUE
9503 00:23:14.884764 EC in RW | 0x000000aa | low | undefined
9504 00:23:14.887785 EC interrupt | 0x00000005 | low | undefined
9505 00:23:14.894293 TPM interrupt | 0x000000ab | high | undefined
9506 00:23:14.898037 SD card detect | 0x00000011 | high | undefined
9507 00:23:14.904577 speaker enable | 0x00000093 | high | undefined
9508 00:23:14.907911 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9509 00:23:14.911203 in-header: 03 f9 00 00 02 00 00 00
9510 00:23:14.911285 in-data: 02 00
9511 00:23:14.914276 ADC[4]: Raw value=902661 ID=7
9512 00:23:14.917341 ADC[3]: Raw value=212912 ID=1
9513 00:23:14.917417 RAM Code: 0x71
9514 00:23:14.921088 ADC[6]: Raw value=75036 ID=0
9515 00:23:14.924202 ADC[5]: Raw value=212543 ID=1
9516 00:23:14.924287 SKU Code: 0x1
9517 00:23:14.930822 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 9094
9518 00:23:14.934195 coreboot table: 964 bytes.
9519 00:23:14.937392 IMD ROOT 0. 0xfffff000 0x00001000
9520 00:23:14.940452 IMD SMALL 1. 0xffffe000 0x00001000
9521 00:23:14.943962 RO MCACHE 2. 0xffffc000 0x00001104
9522 00:23:14.947174 CONSOLE 3. 0xfff7c000 0x00080000
9523 00:23:14.950723 FMAP 4. 0xfff7b000 0x00000452
9524 00:23:14.953849 TIME STAMP 5. 0xfff7a000 0x00000910
9525 00:23:14.956843 VBOOT WORK 6. 0xfff66000 0x00014000
9526 00:23:14.960237 RAMOOPS 7. 0xffe66000 0x00100000
9527 00:23:14.963839 COREBOOT 8. 0xffe64000 0x00002000
9528 00:23:14.963944 IMD small region:
9529 00:23:14.966743 IMD ROOT 0. 0xffffec00 0x00000400
9530 00:23:14.970433 VPD 1. 0xffffeb80 0x0000006c
9531 00:23:14.973435 MMC STATUS 2. 0xffffeb60 0x00000004
9532 00:23:14.980175 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9533 00:23:14.986468 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9534 00:23:15.025987 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9535 00:23:15.029139 Checking segment from ROM address 0x40100000
9536 00:23:15.035676 Checking segment from ROM address 0x4010001c
9537 00:23:15.038613 Loading segment from ROM address 0x40100000
9538 00:23:15.038702 code (compression=0)
9539 00:23:15.048989 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9540 00:23:15.055479 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9541 00:23:15.055566 it's not compressed!
9542 00:23:15.062138 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9543 00:23:15.068458 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9544 00:23:15.086027 Loading segment from ROM address 0x4010001c
9545 00:23:15.086121 Entry Point 0x80000000
9546 00:23:15.089598 Loaded segments
9547 00:23:15.092658 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9548 00:23:15.099409 Jumping to boot code at 0x80000000(0xffe64000)
9549 00:23:15.106022 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9550 00:23:15.112726 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9551 00:23:15.120665 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9552 00:23:15.124146 Checking segment from ROM address 0x40100000
9553 00:23:15.127339 Checking segment from ROM address 0x4010001c
9554 00:23:15.134104 Loading segment from ROM address 0x40100000
9555 00:23:15.134220 code (compression=1)
9556 00:23:15.140251 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9557 00:23:15.150649 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9558 00:23:15.150729 using LZMA
9559 00:23:15.159267 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9560 00:23:15.165806 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9561 00:23:15.169105 Loading segment from ROM address 0x4010001c
9562 00:23:15.169177 Entry Point 0x54601000
9563 00:23:15.172155 Loaded segments
9564 00:23:15.175341 NOTICE: MT8192 bl31_setup
9565 00:23:15.182562 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9566 00:23:15.185741 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9567 00:23:15.189107 WARNING: region 0:
9568 00:23:15.192330 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9569 00:23:15.192411 WARNING: region 1:
9570 00:23:15.199292 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9571 00:23:15.202705 WARNING: region 2:
9572 00:23:15.205567 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9573 00:23:15.209326 WARNING: region 3:
9574 00:23:15.212601 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9575 00:23:15.215491 WARNING: region 4:
9576 00:23:15.222699 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9577 00:23:15.222781 WARNING: region 5:
9578 00:23:15.225922 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9579 00:23:15.228881 WARNING: region 6:
9580 00:23:15.232222 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9581 00:23:15.235626 WARNING: region 7:
9582 00:23:15.238651 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9583 00:23:15.245331 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9584 00:23:15.249083 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9585 00:23:15.255681 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9586 00:23:15.258595 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9587 00:23:15.261738 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9588 00:23:15.268426 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9589 00:23:15.272011 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9590 00:23:15.274934 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9591 00:23:15.281466 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9592 00:23:15.285137 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9593 00:23:15.291517 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9594 00:23:15.294938 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9595 00:23:15.298215 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9596 00:23:15.304424 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9597 00:23:15.307983 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9598 00:23:15.311118 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9599 00:23:15.317972 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9600 00:23:15.321234 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9601 00:23:15.327802 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9602 00:23:15.331043 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9603 00:23:15.334753 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9604 00:23:15.340851 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9605 00:23:15.344070 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9606 00:23:15.351115 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9607 00:23:15.354063 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9608 00:23:15.357701 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9609 00:23:15.364352 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9610 00:23:15.367280 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9611 00:23:15.373996 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9612 00:23:15.377477 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9613 00:23:15.383585 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9614 00:23:15.387387 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9615 00:23:15.390521 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9616 00:23:15.393913 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9617 00:23:15.400437 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9618 00:23:15.404034 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9619 00:23:15.407024 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9620 00:23:15.409939 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9621 00:23:15.416895 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9622 00:23:15.420609 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9623 00:23:15.423480 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9624 00:23:15.426810 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9625 00:23:15.433194 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9626 00:23:15.436707 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9627 00:23:15.439662 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9628 00:23:15.446497 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9629 00:23:15.449971 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9630 00:23:15.453150 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9631 00:23:15.460095 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9632 00:23:15.463092 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9633 00:23:15.466810 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9634 00:23:15.472860 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9635 00:23:15.476501 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9636 00:23:15.483053 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9637 00:23:15.486097 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9638 00:23:15.492645 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9639 00:23:15.495817 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9640 00:23:15.502778 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9641 00:23:15.505825 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9642 00:23:15.509387 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9643 00:23:15.515996 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9644 00:23:15.519154 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9645 00:23:15.525975 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9646 00:23:15.528872 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9647 00:23:15.535497 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9648 00:23:15.538978 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9649 00:23:15.545764 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9650 00:23:15.548690 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9651 00:23:15.554972 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9652 00:23:15.558548 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9653 00:23:15.562046 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9654 00:23:15.568495 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9655 00:23:15.571571 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9656 00:23:15.578136 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9657 00:23:15.581967 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9658 00:23:15.588333 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9659 00:23:15.591867 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9660 00:23:15.597863 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9661 00:23:15.601517 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9662 00:23:15.605009 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9663 00:23:15.610976 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9664 00:23:15.614615 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9665 00:23:15.621243 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9666 00:23:15.624565 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9667 00:23:15.631353 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9668 00:23:15.634262 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9669 00:23:15.641063 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9670 00:23:15.644072 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9671 00:23:15.647485 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9672 00:23:15.654272 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9673 00:23:15.657487 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9674 00:23:15.663954 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9675 00:23:15.667159 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9676 00:23:15.673554 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9677 00:23:15.677077 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9678 00:23:15.683905 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9679 00:23:15.687074 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9680 00:23:15.690711 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9681 00:23:15.693596 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9682 00:23:15.700580 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9683 00:23:15.703688 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9684 00:23:15.706778 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9685 00:23:15.713237 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9686 00:23:15.716898 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9687 00:23:15.723754 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9688 00:23:15.726778 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9689 00:23:15.729909 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9690 00:23:15.736665 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9691 00:23:15.739588 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9692 00:23:15.746255 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9693 00:23:15.749912 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9694 00:23:15.752800 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9695 00:23:15.759355 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9696 00:23:15.763058 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9697 00:23:15.769516 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9698 00:23:15.772912 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9699 00:23:15.776333 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9700 00:23:15.782425 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9701 00:23:15.785877 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9702 00:23:15.788987 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9703 00:23:15.795762 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9704 00:23:15.798772 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9705 00:23:15.802275 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9706 00:23:15.805393 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9707 00:23:15.812220 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9708 00:23:15.815358 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9709 00:23:15.822064 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9710 00:23:15.825190 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9711 00:23:15.828899 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9712 00:23:15.835290 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9713 00:23:15.838600 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9714 00:23:15.845179 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9715 00:23:15.848657 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9716 00:23:15.851655 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9717 00:23:15.858748 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9718 00:23:15.861665 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9719 00:23:15.868545 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9720 00:23:15.871446 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9721 00:23:15.875053 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9722 00:23:15.881451 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9723 00:23:15.884921 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9724 00:23:15.891567 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9725 00:23:15.894621 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9726 00:23:15.898063 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9727 00:23:15.904383 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9728 00:23:15.908034 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9729 00:23:15.914575 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9730 00:23:15.918012 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9731 00:23:15.921254 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9732 00:23:15.927887 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9733 00:23:15.930958 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9734 00:23:15.937619 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9735 00:23:15.940610 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9736 00:23:15.944384 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9737 00:23:15.950822 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9738 00:23:15.954054 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9739 00:23:15.960364 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9740 00:23:15.964104 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9741 00:23:15.967295 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9742 00:23:15.973987 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9743 00:23:15.977025 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9744 00:23:15.983583 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9745 00:23:15.986883 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9746 00:23:15.990174 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9747 00:23:15.996866 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9748 00:23:16.000064 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9749 00:23:16.006698 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9750 00:23:16.009781 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9751 00:23:16.012900 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9752 00:23:16.019735 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9753 00:23:16.023240 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9754 00:23:16.029752 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9755 00:23:16.032788 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9756 00:23:16.036189 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9757 00:23:16.043017 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9758 00:23:16.046050 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9759 00:23:16.052731 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9760 00:23:16.056233 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9761 00:23:16.059298 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9762 00:23:16.066103 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9763 00:23:16.069740 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9764 00:23:16.075652 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9765 00:23:16.079331 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9766 00:23:16.082418 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9767 00:23:16.088834 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9768 00:23:16.092625 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9769 00:23:16.099289 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9770 00:23:16.102377 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9771 00:23:16.105381 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9772 00:23:16.112485 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9773 00:23:16.115280 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9774 00:23:16.122179 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9775 00:23:16.125209 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9776 00:23:16.131714 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9777 00:23:16.135177 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9778 00:23:16.138701 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9779 00:23:16.145077 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9780 00:23:16.148153 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9781 00:23:16.154836 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9782 00:23:16.158490 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9783 00:23:16.164659 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9784 00:23:16.168060 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9785 00:23:16.171491 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9786 00:23:16.178178 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9787 00:23:16.181299 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9788 00:23:16.187910 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9789 00:23:16.190955 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9790 00:23:16.197672 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9791 00:23:16.201356 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9792 00:23:16.204360 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9793 00:23:16.211142 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9794 00:23:16.214081 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9795 00:23:16.220631 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9796 00:23:16.224077 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9797 00:23:16.230581 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9798 00:23:16.234210 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9799 00:23:16.237653 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9800 00:23:16.244007 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9801 00:23:16.247420 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9802 00:23:16.254122 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9803 00:23:16.257207 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9804 00:23:16.264016 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9805 00:23:16.267093 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9806 00:23:16.270086 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9807 00:23:16.276811 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9808 00:23:16.280713 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9809 00:23:16.286772 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9810 00:23:16.289872 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9811 00:23:16.296480 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9812 00:23:16.300100 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9813 00:23:16.303154 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9814 00:23:16.306285 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9815 00:23:16.309874 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9816 00:23:16.316577 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9817 00:23:16.319378 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9818 00:23:16.326027 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9819 00:23:16.329216 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9820 00:23:16.332540 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9821 00:23:16.339383 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9822 00:23:16.342998 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9823 00:23:16.345922 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9824 00:23:16.352636 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9825 00:23:16.356336 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9826 00:23:16.359404 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9827 00:23:16.365726 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9828 00:23:16.369223 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9829 00:23:16.376022 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9830 00:23:16.379042 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9831 00:23:16.382777 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9832 00:23:16.388989 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9833 00:23:16.392560 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9834 00:23:16.399038 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9835 00:23:16.402310 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9836 00:23:16.405438 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9837 00:23:16.412326 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9838 00:23:16.415407 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9839 00:23:16.418436 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9840 00:23:16.425125 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9841 00:23:16.428603 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9842 00:23:16.432030 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9843 00:23:16.438077 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9844 00:23:16.441523 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9845 00:23:16.447965 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9846 00:23:16.451582 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9847 00:23:16.454481 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9848 00:23:16.461128 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9849 00:23:16.464578 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9850 00:23:16.471530 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9851 00:23:16.474595 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9852 00:23:16.477596 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9853 00:23:16.480718 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9854 00:23:16.487523 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9855 00:23:16.490617 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9856 00:23:16.494265 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9857 00:23:16.497317 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9858 00:23:16.504105 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9859 00:23:16.507087 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9860 00:23:16.510587 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9861 00:23:16.513467 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9862 00:23:16.520404 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9863 00:23:16.523543 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9864 00:23:16.527069 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9865 00:23:16.533733 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9866 00:23:16.536824 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9867 00:23:16.543535 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9868 00:23:16.546577 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9869 00:23:16.549821 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9870 00:23:16.556762 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9871 00:23:16.559785 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9872 00:23:16.566832 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9873 00:23:16.569876 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9874 00:23:16.573268 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9875 00:23:16.579608 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9876 00:23:16.582856 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9877 00:23:16.589485 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9878 00:23:16.592600 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9879 00:23:16.599676 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9880 00:23:16.602866 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9881 00:23:16.606380 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9882 00:23:16.612621 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9883 00:23:16.616208 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9884 00:23:16.622902 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9885 00:23:16.626047 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9886 00:23:16.632298 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9887 00:23:16.636110 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9888 00:23:16.639091 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9889 00:23:16.645919 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9890 00:23:16.648866 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9891 00:23:16.655971 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9892 00:23:16.659378 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9893 00:23:16.662154 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9894 00:23:16.668901 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9895 00:23:16.672064 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9896 00:23:16.678729 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9897 00:23:16.682093 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9898 00:23:16.685336 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9899 00:23:16.692088 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9900 00:23:16.695005 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9901 00:23:16.701603 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9902 00:23:16.705346 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9903 00:23:16.711872 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9904 00:23:16.714838 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9905 00:23:16.718597 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9906 00:23:16.725133 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9907 00:23:16.728619 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9908 00:23:16.735174 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9909 00:23:16.738362 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9910 00:23:16.741780 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9911 00:23:16.748349 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9912 00:23:16.751326 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9913 00:23:16.758038 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9914 00:23:16.761059 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9915 00:23:16.767768 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9916 00:23:16.771001 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9917 00:23:16.774181 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9918 00:23:16.781300 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9919 00:23:16.784411 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9920 00:23:16.791063 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9921 00:23:16.794222 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9922 00:23:16.797838 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9923 00:23:16.803982 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9924 00:23:16.807579 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9925 00:23:16.814380 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9926 00:23:16.817458 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9927 00:23:16.823896 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9928 00:23:16.827297 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9929 00:23:16.830624 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9930 00:23:16.837405 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9931 00:23:16.840383 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9932 00:23:16.846925 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9933 00:23:16.850250 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9934 00:23:16.853789 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9935 00:23:16.860479 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9936 00:23:16.863420 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9937 00:23:16.870053 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9938 00:23:16.873580 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9939 00:23:16.880364 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9940 00:23:16.883762 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9941 00:23:16.889954 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9942 00:23:16.893042 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9943 00:23:16.896639 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9944 00:23:16.903376 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9945 00:23:16.906448 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9946 00:23:16.913146 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9947 00:23:16.916134 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9948 00:23:16.922867 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9949 00:23:16.926605 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9950 00:23:16.932940 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9951 00:23:16.936226 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9952 00:23:16.939261 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9953 00:23:16.946531 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9954 00:23:16.949606 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9955 00:23:16.955705 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9956 00:23:16.959452 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9957 00:23:16.965893 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9958 00:23:16.969004 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9959 00:23:16.975547 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9960 00:23:16.979063 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9961 00:23:16.982089 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9962 00:23:16.988517 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9963 00:23:16.992006 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9964 00:23:16.999121 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9965 00:23:17.002240 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9966 00:23:17.008481 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9967 00:23:17.011779 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9968 00:23:17.015474 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9969 00:23:17.021642 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9970 00:23:17.025317 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9971 00:23:17.031894 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9972 00:23:17.034978 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9973 00:23:17.041216 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9974 00:23:17.044941 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9975 00:23:17.051506 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9976 00:23:17.054574 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9977 00:23:17.058305 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9978 00:23:17.064720 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9979 00:23:17.067959 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9980 00:23:17.074248 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9981 00:23:17.077999 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9982 00:23:17.084489 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9983 00:23:17.087421 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9984 00:23:17.094096 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9985 00:23:17.097524 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9986 00:23:17.100883 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9987 00:23:17.107852 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9988 00:23:17.111010 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9989 00:23:17.117587 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9990 00:23:17.120712 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9991 00:23:17.127284 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9992 00:23:17.130382 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9993 00:23:17.136875 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9994 00:23:17.140416 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9995 00:23:17.146887 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9996 00:23:17.150070 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9997 00:23:17.156687 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9998 00:23:17.160346 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9999 00:23:17.167085 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
10000 00:23:17.170053 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
10001 00:23:17.176615 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
10002 00:23:17.179986 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
10003 00:23:17.186297 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
10004 00:23:17.190120 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
10005 00:23:17.196570 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
10006 00:23:17.199495 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
10007 00:23:17.206604 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
10008 00:23:17.209385 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
10009 00:23:17.216357 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
10010 00:23:17.219924 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
10011 00:23:17.226261 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
10012 00:23:17.229399 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
10013 00:23:17.235993 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
10014 00:23:17.239177 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
10015 00:23:17.245736 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
10016 00:23:17.249151 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
10017 00:23:17.255604 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
10018 00:23:17.255728 INFO: [APUAPC] vio 0
10019 00:23:17.262842 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
10020 00:23:17.265882 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
10021 00:23:17.268914 INFO: [APUAPC] D0_APC_0: 0x400510
10022 00:23:17.272442 INFO: [APUAPC] D0_APC_1: 0x0
10023 00:23:17.275525 INFO: [APUAPC] D0_APC_2: 0x1540
10024 00:23:17.279220 INFO: [APUAPC] D0_APC_3: 0x0
10025 00:23:17.282229 INFO: [APUAPC] D1_APC_0: 0xffffffff
10026 00:23:17.285869 INFO: [APUAPC] D1_APC_1: 0xffffffff
10027 00:23:17.288738 INFO: [APUAPC] D1_APC_2: 0x3fffff
10028 00:23:17.292336 INFO: [APUAPC] D1_APC_3: 0x0
10029 00:23:17.295514 INFO: [APUAPC] D2_APC_0: 0xffffffff
10030 00:23:17.298880 INFO: [APUAPC] D2_APC_1: 0xffffffff
10031 00:23:17.301947 INFO: [APUAPC] D2_APC_2: 0x3fffff
10032 00:23:17.305238 INFO: [APUAPC] D2_APC_3: 0x0
10033 00:23:17.309054 INFO: [APUAPC] D3_APC_0: 0xffffffff
10034 00:23:17.311874 INFO: [APUAPC] D3_APC_1: 0xffffffff
10035 00:23:17.315504 INFO: [APUAPC] D3_APC_2: 0x3fffff
10036 00:23:17.318811 INFO: [APUAPC] D3_APC_3: 0x0
10037 00:23:17.321943 INFO: [APUAPC] D4_APC_0: 0xffffffff
10038 00:23:17.325440 INFO: [APUAPC] D4_APC_1: 0xffffffff
10039 00:23:17.328544 INFO: [APUAPC] D4_APC_2: 0x3fffff
10040 00:23:17.331997 INFO: [APUAPC] D4_APC_3: 0x0
10041 00:23:17.335187 INFO: [APUAPC] D5_APC_0: 0xffffffff
10042 00:23:17.338760 INFO: [APUAPC] D5_APC_1: 0xffffffff
10043 00:23:17.342030 INFO: [APUAPC] D5_APC_2: 0x3fffff
10044 00:23:17.342136 INFO: [APUAPC] D5_APC_3: 0x0
10045 00:23:17.345017 INFO: [APUAPC] D6_APC_0: 0xffffffff
10046 00:23:17.351717 INFO: [APUAPC] D6_APC_1: 0xffffffff
10047 00:23:17.355200 INFO: [APUAPC] D6_APC_2: 0x3fffff
10048 00:23:17.355282 INFO: [APUAPC] D6_APC_3: 0x0
10049 00:23:17.358122 INFO: [APUAPC] D7_APC_0: 0xffffffff
10050 00:23:17.361879 INFO: [APUAPC] D7_APC_1: 0xffffffff
10051 00:23:17.364849 INFO: [APUAPC] D7_APC_2: 0x3fffff
10052 00:23:17.368494 INFO: [APUAPC] D7_APC_3: 0x0
10053 00:23:17.371505 INFO: [APUAPC] D8_APC_0: 0xffffffff
10054 00:23:17.375092 INFO: [APUAPC] D8_APC_1: 0xffffffff
10055 00:23:17.378411 INFO: [APUAPC] D8_APC_2: 0x3fffff
10056 00:23:17.381469 INFO: [APUAPC] D8_APC_3: 0x0
10057 00:23:17.385172 INFO: [APUAPC] D9_APC_0: 0xffffffff
10058 00:23:17.388260 INFO: [APUAPC] D9_APC_1: 0xffffffff
10059 00:23:17.391282 INFO: [APUAPC] D9_APC_2: 0x3fffff
10060 00:23:17.394923 INFO: [APUAPC] D9_APC_3: 0x0
10061 00:23:17.397792 INFO: [APUAPC] D10_APC_0: 0xffffffff
10062 00:23:17.401290 INFO: [APUAPC] D10_APC_1: 0xffffffff
10063 00:23:17.404576 INFO: [APUAPC] D10_APC_2: 0x3fffff
10064 00:23:17.408093 INFO: [APUAPC] D10_APC_3: 0x0
10065 00:23:17.411021 INFO: [APUAPC] D11_APC_0: 0xffffffff
10066 00:23:17.414798 INFO: [APUAPC] D11_APC_1: 0xffffffff
10067 00:23:17.417947 INFO: [APUAPC] D11_APC_2: 0x3fffff
10068 00:23:17.420952 INFO: [APUAPC] D11_APC_3: 0x0
10069 00:23:17.424659 INFO: [APUAPC] D12_APC_0: 0xffffffff
10070 00:23:17.428025 INFO: [APUAPC] D12_APC_1: 0xffffffff
10071 00:23:17.431013 INFO: [APUAPC] D12_APC_2: 0x3fffff
10072 00:23:17.434325 INFO: [APUAPC] D12_APC_3: 0x0
10073 00:23:17.437571 INFO: [APUAPC] D13_APC_0: 0xffffffff
10074 00:23:17.440976 INFO: [APUAPC] D13_APC_1: 0xffffffff
10075 00:23:17.444561 INFO: [APUAPC] D13_APC_2: 0x3fffff
10076 00:23:17.447429 INFO: [APUAPC] D13_APC_3: 0x0
10077 00:23:17.450897 INFO: [APUAPC] D14_APC_0: 0xffffffff
10078 00:23:17.457618 INFO: [APUAPC] D14_APC_1: 0xffffffff
10079 00:23:17.461272 INFO: [APUAPC] D14_APC_2: 0x3fffff
10080 00:23:17.461376 INFO: [APUAPC] D14_APC_3: 0x0
10081 00:23:17.464066 INFO: [APUAPC] D15_APC_0: 0xffffffff
10082 00:23:17.470761 INFO: [APUAPC] D15_APC_1: 0xffffffff
10083 00:23:17.473885 INFO: [APUAPC] D15_APC_2: 0x3fffff
10084 00:23:17.473957 INFO: [APUAPC] D15_APC_3: 0x0
10085 00:23:17.477519 INFO: [APUAPC] APC_CON: 0x4
10086 00:23:17.480797 INFO: [NOCDAPC] D0_APC_0: 0x0
10087 00:23:17.484377 INFO: [NOCDAPC] D0_APC_1: 0x0
10088 00:23:17.487241 INFO: [NOCDAPC] D1_APC_0: 0x0
10089 00:23:17.490713 INFO: [NOCDAPC] D1_APC_1: 0xfff
10090 00:23:17.493746 INFO: [NOCDAPC] D2_APC_0: 0x0
10091 00:23:17.497421 INFO: [NOCDAPC] D2_APC_1: 0xfff
10092 00:23:17.500923 INFO: [NOCDAPC] D3_APC_0: 0x0
10093 00:23:17.501040 INFO: [NOCDAPC] D3_APC_1: 0xfff
10094 00:23:17.503641 INFO: [NOCDAPC] D4_APC_0: 0x0
10095 00:23:17.507312 INFO: [NOCDAPC] D4_APC_1: 0xfff
10096 00:23:17.510424 INFO: [NOCDAPC] D5_APC_0: 0x0
10097 00:23:17.514131 INFO: [NOCDAPC] D5_APC_1: 0xfff
10098 00:23:17.517326 INFO: [NOCDAPC] D6_APC_0: 0x0
10099 00:23:17.520260 INFO: [NOCDAPC] D6_APC_1: 0xfff
10100 00:23:17.523576 INFO: [NOCDAPC] D7_APC_0: 0x0
10101 00:23:17.526912 INFO: [NOCDAPC] D7_APC_1: 0xfff
10102 00:23:17.530273 INFO: [NOCDAPC] D8_APC_0: 0x0
10103 00:23:17.533385 INFO: [NOCDAPC] D8_APC_1: 0xfff
10104 00:23:17.537196 INFO: [NOCDAPC] D9_APC_0: 0x0
10105 00:23:17.537275 INFO: [NOCDAPC] D9_APC_1: 0xfff
10106 00:23:17.540468 INFO: [NOCDAPC] D10_APC_0: 0x0
10107 00:23:17.543439 INFO: [NOCDAPC] D10_APC_1: 0xfff
10108 00:23:17.546928 INFO: [NOCDAPC] D11_APC_0: 0x0
10109 00:23:17.550006 INFO: [NOCDAPC] D11_APC_1: 0xfff
10110 00:23:17.553517 INFO: [NOCDAPC] D12_APC_0: 0x0
10111 00:23:17.556962 INFO: [NOCDAPC] D12_APC_1: 0xfff
10112 00:23:17.559995 INFO: [NOCDAPC] D13_APC_0: 0x0
10113 00:23:17.563847 INFO: [NOCDAPC] D13_APC_1: 0xfff
10114 00:23:17.566666 INFO: [NOCDAPC] D14_APC_0: 0x0
10115 00:23:17.570125 INFO: [NOCDAPC] D14_APC_1: 0xfff
10116 00:23:17.573319 INFO: [NOCDAPC] D15_APC_0: 0x0
10117 00:23:17.576435 INFO: [NOCDAPC] D15_APC_1: 0xfff
10118 00:23:17.580072 INFO: [NOCDAPC] APC_CON: 0x4
10119 00:23:17.583020 INFO: [APUAPC] set_apusys_apc done
10120 00:23:17.586637 INFO: [DEVAPC] devapc_init done
10121 00:23:17.589700 INFO: GICv3 without legacy support detected.
10122 00:23:17.592748 INFO: ARM GICv3 driver initialized in EL3
10123 00:23:17.596423 INFO: Maximum SPI INTID supported: 639
10124 00:23:17.599392 INFO: BL31: Initializing runtime services
10125 00:23:17.606396 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10126 00:23:17.609422 INFO: SPM: enable CPC mode
10127 00:23:17.613047 INFO: mcdi ready for mcusys-off-idle and system suspend
10128 00:23:17.619679 INFO: BL31: Preparing for EL3 exit to normal world
10129 00:23:17.622865 INFO: Entry point address = 0x80000000
10130 00:23:17.625845 INFO: SPSR = 0x8
10131 00:23:17.630662
10132 00:23:17.630736
10133 00:23:17.630797
10134 00:23:17.634146 Starting depthcharge on Spherion...
10135 00:23:17.634236
10136 00:23:17.634296 Wipe memory regions:
10137 00:23:17.634352
10138 00:23:17.634965 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
10139 00:23:17.635092 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
10140 00:23:17.635203 Setting prompt string to ['asurada:']
10141 00:23:17.635320 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
10142 00:23:17.637274 [0x00000040000000, 0x00000054600000)
10143 00:23:17.759325
10144 00:23:17.759465 [0x00000054660000, 0x00000080000000)
10145 00:23:18.019952
10146 00:23:18.020091 [0x000000821a7280, 0x000000ffe64000)
10147 00:23:18.765112
10148 00:23:18.765285 [0x00000100000000, 0x00000240000000)
10149 00:23:20.654911
10150 00:23:20.658068 Initializing XHCI USB controller at 0x11200000.
10151 00:23:21.696515
10152 00:23:21.699869 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10153 00:23:21.699977
10154 00:23:21.700068
10155 00:23:21.700389 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10157 00:23:21.800772 asurada: tftpboot 192.168.201.1 14479184/tftp-deploy-8149qxkr/kernel/image.itb 14479184/tftp-deploy-8149qxkr/kernel/cmdline
10158 00:23:21.801002 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10159 00:23:21.801124 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:22)
10160 00:23:21.805769 tftpboot 192.168.201.1 14479184/tftp-deploy-8149qxkr/kernel/image.ittp-deploy-8149qxkr/kernel/cmdline
10161 00:23:21.805881
10162 00:23:21.805976 Waiting for link
10163 00:23:21.963431
10164 00:23:21.963596 R8152: Initializing
10165 00:23:21.963675
10166 00:23:21.966973 Version 6 (ocp_data = 5c30)
10167 00:23:21.967043
10168 00:23:21.970002 R8152: Done initializing
10169 00:23:21.970113
10170 00:23:21.970215 Adding net device
10171 00:23:23.843111
10172 00:23:23.843271 done.
10173 00:23:23.843369
10174 00:23:23.843468 MAC: 00:e0:4c:68:02:81
10175 00:23:23.843558
10176 00:23:23.846026 Sending DHCP discover... done.
10177 00:23:23.846129
10178 00:23:34.227627 Waiting for reply... R8152: Bulk read error 0xffffffbf
10179 00:23:34.228393
10180 00:23:34.230723 Receive failed.
10181 00:23:34.231228
10182 00:23:34.231898 done.
10183 00:23:34.232390
10184 00:23:34.234011 Sending DHCP request... done.
10185 00:23:34.234612
10186 00:23:34.237147 Waiting for reply... done.
10187 00:23:34.237606
10188 00:23:34.240456 My ip is 192.168.201.14
10189 00:23:34.240913
10190 00:23:34.243627 The DHCP server ip is 192.168.201.1
10191 00:23:34.244095
10192 00:23:34.247192 TFTP server IP predefined by user: 192.168.201.1
10193 00:23:34.247659
10194 00:23:34.253502 Bootfile predefined by user: 14479184/tftp-deploy-8149qxkr/kernel/image.itb
10195 00:23:34.254269
10196 00:23:34.257182 Sending tftp read request... done.
10197 00:23:34.257965
10198 00:23:34.265330 Waiting for the transfer...
10199 00:23:34.265747
10200 00:23:34.954071 00000000 ################################################################
10201 00:23:34.954614
10202 00:23:35.645998 00080000 ################################################################
10203 00:23:35.646556
10204 00:23:36.336455 00100000 ################################################################
10205 00:23:36.337107
10206 00:23:36.996706 00180000 ################################################################
10207 00:23:36.996922
10208 00:23:37.678828 00200000 ################################################################
10209 00:23:37.679376
10210 00:23:38.392954 00280000 ################################################################
10211 00:23:38.393588
10212 00:23:39.097668 00300000 ################################################################
10213 00:23:39.098270
10214 00:23:39.805101 00380000 ################################################################
10215 00:23:39.805714
10216 00:23:40.464106 00400000 ################################################################
10217 00:23:40.464673
10218 00:23:41.116681 00480000 ################################################################
10219 00:23:41.116854
10220 00:23:41.749942 00500000 ################################################################
10221 00:23:41.750492
10222 00:23:42.431204 00580000 ################################################################
10223 00:23:42.431738
10224 00:23:43.104659 00600000 ################################################################
10225 00:23:43.105165
10226 00:23:43.741132 00680000 ################################################################
10227 00:23:43.741801
10228 00:23:44.407497 00700000 ################################################################
10229 00:23:44.408186
10230 00:23:44.995077 00780000 ################################################################
10231 00:23:44.995210
10232 00:23:45.555884 00800000 ################################################################
10233 00:23:45.556053
10234 00:23:46.098994 00880000 ################################################################
10235 00:23:46.099144
10236 00:23:46.645950 00900000 ################################################################
10237 00:23:46.646149
10238 00:23:47.265230 00980000 ################################################################
10239 00:23:47.265737
10240 00:23:47.917731 00a00000 ################################################################
10241 00:23:47.917900
10242 00:23:48.505034 00a80000 ################################################################
10243 00:23:48.505171
10244 00:23:49.200486 00b00000 ################################################################
10245 00:23:49.200621
10246 00:23:49.892285 00b80000 ################################################################
10247 00:23:49.892807
10248 00:23:50.545910 00c00000 ################################################################
10249 00:23:50.546080
10250 00:23:51.135334 00c80000 ################################################################
10251 00:23:51.135499
10252 00:23:51.813605 00d00000 ################################################################
10253 00:23:51.814366
10254 00:23:52.517066 00d80000 ################################################################
10255 00:23:52.517221
10256 00:23:53.216438 00e00000 ################################################################
10257 00:23:53.216577
10258 00:23:53.803235 00e80000 ################################################################
10259 00:23:53.803380
10260 00:23:54.365968 00f00000 ################################################################
10261 00:23:54.366119
10262 00:23:54.932246 00f80000 ################################################################
10263 00:23:54.932398
10264 00:23:55.472609 01000000 ################################################################
10265 00:23:55.472760
10266 00:23:56.060121 01080000 ################################################################
10267 00:23:56.060265
10268 00:23:56.655847 01100000 ################################################################
10269 00:23:56.655996
10270 00:23:57.215395 01180000 ################################################################
10271 00:23:57.215545
10272 00:23:57.769227 01200000 ################################################################
10273 00:23:57.769373
10274 00:23:58.361235 01280000 ################################################################
10275 00:23:58.361409
10276 00:23:58.945957 01300000 ################################################################
10277 00:23:58.946096
10278 00:23:59.527225 01380000 ################################################################
10279 00:23:59.527391
10280 00:24:00.154210 01400000 ################################################################
10281 00:24:00.154373
10282 00:24:00.816109 01480000 ################################################################
10283 00:24:00.816260
10284 00:24:01.433988 01500000 ################################################################
10285 00:24:01.434147
10286 00:24:02.066828 01580000 ################################################################
10287 00:24:02.066978
10288 00:24:02.671268 01600000 ################################################################
10289 00:24:02.671412
10290 00:24:03.278516 01680000 ################################################################
10291 00:24:03.278666
10292 00:24:03.826884 01700000 ################################################################
10293 00:24:03.827039
10294 00:24:04.433572 01780000 ################################################################
10295 00:24:04.433722
10296 00:24:05.043496 01800000 ################################################################
10297 00:24:05.043652
10298 00:24:05.667658 01880000 ################################################################
10299 00:24:05.668171
10300 00:24:06.244305 01900000 ################################################################
10301 00:24:06.244455
10302 00:24:06.887805 01980000 ################################################################
10303 00:24:06.888401
10304 00:24:07.536731 01a00000 ################################################################
10305 00:24:07.536877
10306 00:24:08.198877 01a80000 ################################################################
10307 00:24:08.199438
10308 00:24:08.883745 01b00000 ################################################################
10309 00:24:08.884261
10310 00:24:09.570648 01b80000 ################################################################
10311 00:24:09.571190
10312 00:24:10.224250 01c00000 ################################################################
10313 00:24:10.224395
10314 00:24:10.912181 01c80000 ################################################################
10315 00:24:10.912706
10316 00:24:11.614860 01d00000 ################################################################
10317 00:24:11.615384
10318 00:24:12.308801 01d80000 ################################################################
10319 00:24:12.308953
10320 00:24:12.812337 01e00000 ######################################################### done.
10321 00:24:12.812488
10322 00:24:12.815882 The bootfile was 31922046 bytes long.
10323 00:24:12.815975
10324 00:24:12.819748 Sending tftp read request... done.
10325 00:24:12.819837
10326 00:24:12.819905 Waiting for the transfer...
10327 00:24:12.819968
10328 00:24:12.822426 00000000 # done.
10329 00:24:12.822512
10330 00:24:12.829289 Command line loaded dynamically from TFTP file: 14479184/tftp-deploy-8149qxkr/kernel/cmdline
10331 00:24:12.829379
10332 00:24:12.852108 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14479184/extract-nfsrootfs-yktrmthu,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10333 00:24:12.852255
10334 00:24:12.852352 Loading FIT.
10335 00:24:12.852441
10336 00:24:12.855319 Image ramdisk-1 has 18747860 bytes.
10337 00:24:12.855403
10338 00:24:12.858804 Image fdt-1 has 47258 bytes.
10339 00:24:12.858889
10340 00:24:12.861765 Image kernel-1 has 13124896 bytes.
10341 00:24:12.861874
10342 00:24:12.872011 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10343 00:24:12.872101
10344 00:24:12.888230 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10345 00:24:12.888375
10346 00:24:12.894756 Choosing best match conf-1 for compat google,spherion-rev2.
10347 00:24:12.898415
10348 00:24:12.902602 Connected to device vid:did:rid of 1ae0:0028:00
10349 00:24:12.909782
10350 00:24:12.913188 tpm_get_response: command 0x17b, return code 0x0
10351 00:24:12.913284
10352 00:24:12.916158 ec_init: CrosEC protocol v3 supported (256, 248)
10353 00:24:12.920261
10354 00:24:12.923738 tpm_cleanup: add release locality here.
10355 00:24:12.923849
10356 00:24:12.923943 Shutting down all USB controllers.
10357 00:24:12.926762
10358 00:24:12.926846 Removing current net device
10359 00:24:12.926911
10360 00:24:12.933597 Exiting depthcharge with code 4 at timestamp: 84729261
10361 00:24:12.933681
10362 00:24:12.937011 LZMA decompressing kernel-1 to 0x821a6718
10363 00:24:12.937095
10364 00:24:12.940200 LZMA decompressing kernel-1 to 0x40000000
10365 00:24:14.556350
10366 00:24:14.556956 jumping to kernel
10367 00:24:14.559242 end: 2.2.4 bootloader-commands (duration 00:00:57) [common]
10368 00:24:14.559767 start: 2.2.5 auto-login-action (timeout 00:03:30) [common]
10369 00:24:14.560220 Setting prompt string to ['Linux version [0-9]']
10370 00:24:14.560575 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10371 00:24:14.560922 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10372 00:24:14.638115
10373 00:24:14.641859 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10374 00:24:14.645662 start: 2.2.5.1 login-action (timeout 00:03:29) [common]
10375 00:24:14.646259 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10376 00:24:14.646675 Setting prompt string to []
10377 00:24:14.647089 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10378 00:24:14.647462 Using line separator: #'\n'#
10379 00:24:14.647768 No login prompt set.
10380 00:24:14.648224 Parsing kernel messages
10381 00:24:14.648753 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10382 00:24:14.649685 [login-action] Waiting for messages, (timeout 00:03:29)
10383 00:24:14.650196 Waiting using forced prompt support (timeout 00:01:45)
10384 00:24:14.665125 [ 0.000000] Linux version 6.1.94-cip23 (KernelCI@build-j239242-arm64-gcc-10-defconfig-arm64-chromebook-c5lwc) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Jun 21 00:04:56 UTC 2024
10385 00:24:14.667698 [ 0.000000] random: crng init done
10386 00:24:14.674424 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10387 00:24:14.678019 [ 0.000000] efi: UEFI not found.
10388 00:24:14.684553 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10389 00:24:14.694260 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10390 00:24:14.700876 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10391 00:24:14.710598 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10392 00:24:14.717409 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10393 00:24:14.723491 [ 0.000000] printk: bootconsole [mtk8250] enabled
10394 00:24:14.730427 [ 0.000000] NUMA: No NUMA configuration found
10395 00:24:14.736628 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10396 00:24:14.743754 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10397 00:24:14.744334 [ 0.000000] Zone ranges:
10398 00:24:14.749962 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10399 00:24:14.753729 [ 0.000000] DMA32 empty
10400 00:24:14.759748 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10401 00:24:14.762989 [ 0.000000] Movable zone start for each node
10402 00:24:14.766416 [ 0.000000] Early memory node ranges
10403 00:24:14.773102 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10404 00:24:14.779856 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10405 00:24:14.786391 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10406 00:24:14.793085 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10407 00:24:14.799637 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10408 00:24:14.806340 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10409 00:24:14.862814 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10410 00:24:14.869198 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10411 00:24:14.875950 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10412 00:24:14.879743 [ 0.000000] psci: probing for conduit method from DT.
10413 00:24:14.886366 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10414 00:24:14.889227 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10415 00:24:14.896025 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10416 00:24:14.898686 [ 0.000000] psci: SMC Calling Convention v1.2
10417 00:24:14.905512 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10418 00:24:14.909003 [ 0.000000] Detected VIPT I-cache on CPU0
10419 00:24:14.915381 [ 0.000000] CPU features: detected: GIC system register CPU interface
10420 00:24:14.921925 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10421 00:24:14.928305 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10422 00:24:14.935149 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10423 00:24:14.945064 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10424 00:24:14.951805 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10425 00:24:14.954779 [ 0.000000] alternatives: applying boot alternatives
10426 00:24:14.962256 [ 0.000000] Fallback order for Node 0: 0
10427 00:24:14.968103 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10428 00:24:14.971518 [ 0.000000] Policy zone: Normal
10429 00:24:14.994787 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14479184/extract-nfsrootfs-yktrmthu,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10430 00:24:15.004931 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10431 00:24:15.016057 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10432 00:24:15.025918 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10433 00:24:15.032616 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10434 00:24:15.035763 <6>[ 0.000000] software IO TLB: area num 8.
10435 00:24:15.091480 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10436 00:24:15.241214 <6>[ 0.000000] Memory: 7945752K/8385536K available (18112K kernel code, 4120K rwdata, 22648K rodata, 8512K init, 616K bss, 407016K reserved, 32768K cma-reserved)
10437 00:24:15.247688 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10438 00:24:15.253791 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10439 00:24:15.256988 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10440 00:24:15.263481 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10441 00:24:15.270401 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10442 00:24:15.276991 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10443 00:24:15.283802 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10444 00:24:15.290249 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10445 00:24:15.296670 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10446 00:24:15.303143 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10447 00:24:15.306434 <6>[ 0.000000] GICv3: 608 SPIs implemented
10448 00:24:15.310326 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10449 00:24:15.316223 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10450 00:24:15.319661 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10451 00:24:15.326440 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10452 00:24:15.339441 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10453 00:24:15.352588 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10454 00:24:15.359425 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10455 00:24:15.367173 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10456 00:24:15.380365 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10457 00:24:15.387383 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10458 00:24:15.393721 <6>[ 0.009178] Console: colour dummy device 80x25
10459 00:24:15.403812 <6>[ 0.013907] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10460 00:24:15.410492 <6>[ 0.024349] pid_max: default: 32768 minimum: 301
10461 00:24:15.413790 <6>[ 0.029221] LSM: Security Framework initializing
10462 00:24:15.419939 <6>[ 0.034159] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10463 00:24:15.430329 <6>[ 0.042019] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10464 00:24:15.440008 <6>[ 0.051430] cblist_init_generic: Setting adjustable number of callback queues.
10465 00:24:15.443735 <6>[ 0.058871] cblist_init_generic: Setting shift to 3 and lim to 1.
10466 00:24:15.453053 <6>[ 0.065248] cblist_init_generic: Setting adjustable number of callback queues.
10467 00:24:15.459914 <6>[ 0.072676] cblist_init_generic: Setting shift to 3 and lim to 1.
10468 00:24:15.463326 <6>[ 0.079077] rcu: Hierarchical SRCU implementation.
10469 00:24:15.469771 <6>[ 0.084124] rcu: Max phase no-delay instances is 1000.
10470 00:24:15.476572 <6>[ 0.091190] EFI services will not be available.
10471 00:24:15.479843 <6>[ 0.096148] smp: Bringing up secondary CPUs ...
10472 00:24:15.488280 <6>[ 0.101198] Detected VIPT I-cache on CPU1
10473 00:24:15.494878 <6>[ 0.101269] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10474 00:24:15.501290 <6>[ 0.101299] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10475 00:24:15.504579 <6>[ 0.101630] Detected VIPT I-cache on CPU2
10476 00:24:15.514503 <6>[ 0.101678] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10477 00:24:15.520820 <6>[ 0.101694] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10478 00:24:15.524538 <6>[ 0.101952] Detected VIPT I-cache on CPU3
10479 00:24:15.530726 <6>[ 0.101998] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10480 00:24:15.537253 <6>[ 0.102012] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10481 00:24:15.540809 <6>[ 0.102313] CPU features: detected: Spectre-v4
10482 00:24:15.547223 <6>[ 0.102320] CPU features: detected: Spectre-BHB
10483 00:24:15.550534 <6>[ 0.102324] Detected PIPT I-cache on CPU4
10484 00:24:15.557734 <6>[ 0.102382] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10485 00:24:15.564084 <6>[ 0.102398] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10486 00:24:15.570509 <6>[ 0.102688] Detected PIPT I-cache on CPU5
10487 00:24:15.577613 <6>[ 0.102750] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10488 00:24:15.583664 <6>[ 0.102766] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10489 00:24:15.587362 <6>[ 0.103047] Detected PIPT I-cache on CPU6
10490 00:24:15.593903 <6>[ 0.103111] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10491 00:24:15.603395 <6>[ 0.103127] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10492 00:24:15.606542 <6>[ 0.103422] Detected PIPT I-cache on CPU7
10493 00:24:15.613469 <6>[ 0.103487] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10494 00:24:15.619934 <6>[ 0.103503] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10495 00:24:15.623975 <6>[ 0.103550] smp: Brought up 1 node, 8 CPUs
10496 00:24:15.629484 <6>[ 0.244925] SMP: Total of 8 processors activated.
10497 00:24:15.636306 <6>[ 0.249847] CPU features: detected: 32-bit EL0 Support
10498 00:24:15.642874 <6>[ 0.255244] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10499 00:24:15.649190 <6>[ 0.264099] CPU features: detected: Common not Private translations
10500 00:24:15.656205 <6>[ 0.270575] CPU features: detected: CRC32 instructions
10501 00:24:15.662818 <6>[ 0.275927] CPU features: detected: RCpc load-acquire (LDAPR)
10502 00:24:15.665718 <6>[ 0.281924] CPU features: detected: LSE atomic instructions
10503 00:24:15.672436 <6>[ 0.287706] CPU features: detected: Privileged Access Never
10504 00:24:15.679592 <6>[ 0.293485] CPU features: detected: RAS Extension Support
10505 00:24:15.685933 <6>[ 0.299094] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10506 00:24:15.689194 <6>[ 0.306356] CPU: All CPU(s) started at EL2
10507 00:24:15.695274 <6>[ 0.310673] alternatives: applying system-wide alternatives
10508 00:24:15.706270 <6>[ 0.321567] devtmpfs: initialized
10509 00:24:15.718229 <6>[ 0.330533] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10510 00:24:15.728409 <6>[ 0.340489] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10511 00:24:15.734526 <6>[ 0.348509] pinctrl core: initialized pinctrl subsystem
10512 00:24:15.738261 <6>[ 0.355179] DMI not present or invalid.
10513 00:24:15.744608 <6>[ 0.359588] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10514 00:24:15.754463 <6>[ 0.366454] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10515 00:24:15.761225 <6>[ 0.374022] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10516 00:24:15.771173 <6>[ 0.382238] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10517 00:24:15.774264 <6>[ 0.390481] audit: initializing netlink subsys (disabled)
10518 00:24:15.784574 <5>[ 0.396173] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10519 00:24:15.791066 <6>[ 0.396889] thermal_sys: Registered thermal governor 'step_wise'
10520 00:24:15.797787 <6>[ 0.404139] thermal_sys: Registered thermal governor 'power_allocator'
10521 00:24:15.800710 <6>[ 0.410391] cpuidle: using governor menu
10522 00:24:15.807369 <6>[ 0.421353] NET: Registered PF_QIPCRTR protocol family
10523 00:24:15.813795 <6>[ 0.426840] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10524 00:24:15.820088 <6>[ 0.433944] ASID allocator initialised with 32768 entries
10525 00:24:15.823707 <6>[ 0.440517] Serial: AMBA PL011 UART driver
10526 00:24:15.833821 <4>[ 0.449343] Trying to register duplicate clock ID: 134
10527 00:24:15.893908 <6>[ 0.512372] KASLR enabled
10528 00:24:15.907846 <6>[ 0.520075] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10529 00:24:15.915129 <6>[ 0.527087] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10530 00:24:15.921181 <6>[ 0.533574] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10531 00:24:15.927573 <6>[ 0.540578] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10532 00:24:15.934293 <6>[ 0.547066] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10533 00:24:15.940885 <6>[ 0.554071] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10534 00:24:15.947548 <6>[ 0.560558] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10535 00:24:15.954336 <6>[ 0.567562] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10536 00:24:15.957170 <6>[ 0.575017] ACPI: Interpreter disabled.
10537 00:24:15.966094 <6>[ 0.581436] iommu: Default domain type: Translated
10538 00:24:15.972804 <6>[ 0.586589] iommu: DMA domain TLB invalidation policy: strict mode
10539 00:24:15.976133 <5>[ 0.593248] SCSI subsystem initialized
10540 00:24:15.982344 <6>[ 0.597494] usbcore: registered new interface driver usbfs
10541 00:24:15.989149 <6>[ 0.603225] usbcore: registered new interface driver hub
10542 00:24:15.992450 <6>[ 0.608779] usbcore: registered new device driver usb
10543 00:24:15.999671 <6>[ 0.614895] pps_core: LinuxPPS API ver. 1 registered
10544 00:24:16.009494 <6>[ 0.620091] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10545 00:24:16.012620 <6>[ 0.629434] PTP clock support registered
10546 00:24:16.016088 <6>[ 0.633674] EDAC MC: Ver: 3.0.0
10547 00:24:16.023483 <6>[ 0.638861] FPGA manager framework
10548 00:24:16.030220 <6>[ 0.642539] Advanced Linux Sound Architecture Driver Initialized.
10549 00:24:16.033497 <6>[ 0.649322] vgaarb: loaded
10550 00:24:16.039703 <6>[ 0.652482] clocksource: Switched to clocksource arch_sys_counter
10551 00:24:16.042935 <5>[ 0.658907] VFS: Disk quotas dquot_6.6.0
10552 00:24:16.049689 <6>[ 0.663091] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10553 00:24:16.053089 <6>[ 0.670284] pnp: PnP ACPI: disabled
10554 00:24:16.061146 <6>[ 0.676942] NET: Registered PF_INET protocol family
10555 00:24:16.071416 <6>[ 0.682530] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10556 00:24:16.082925 <6>[ 0.694885] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10557 00:24:16.092679 <6>[ 0.703703] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10558 00:24:16.099020 <6>[ 0.711672] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10559 00:24:16.108913 <6>[ 0.720374] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10560 00:24:16.115423 <6>[ 0.730122] TCP: Hash tables configured (established 65536 bind 65536)
10561 00:24:16.122237 <6>[ 0.736990] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10562 00:24:16.131977 <6>[ 0.744191] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10563 00:24:16.138632 <6>[ 0.751898] NET: Registered PF_UNIX/PF_LOCAL protocol family
10564 00:24:16.145488 <6>[ 0.758043] RPC: Registered named UNIX socket transport module.
10565 00:24:16.148184 <6>[ 0.764198] RPC: Registered udp transport module.
10566 00:24:16.155069 <6>[ 0.769133] RPC: Registered tcp transport module.
10567 00:24:16.161777 <6>[ 0.774067] RPC: Registered tcp NFSv4.1 backchannel transport module.
10568 00:24:16.164718 <6>[ 0.780732] PCI: CLS 0 bytes, default 64
10569 00:24:16.168222 <6>[ 0.785100] Unpacking initramfs...
10570 00:24:16.178156 <6>[ 0.788833] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10571 00:24:16.185065 <6>[ 0.797473] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10572 00:24:16.191154 <6>[ 0.806324] kvm [1]: IPA Size Limit: 40 bits
10573 00:24:16.194542 <6>[ 0.810853] kvm [1]: GICv3: no GICV resource entry
10574 00:24:16.201056 <6>[ 0.815875] kvm [1]: disabling GICv2 emulation
10575 00:24:16.207393 <6>[ 0.820564] kvm [1]: GIC system register CPU interface enabled
10576 00:24:16.210839 <6>[ 0.826724] kvm [1]: vgic interrupt IRQ18
10577 00:24:16.217502 <6>[ 0.832546] kvm [1]: VHE mode initialized successfully
10578 00:24:16.224183 <5>[ 0.838931] Initialise system trusted keyrings
10579 00:24:16.230672 <6>[ 0.843728] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10580 00:24:16.238279 <6>[ 0.853763] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10581 00:24:16.245147 <5>[ 0.860095] NFS: Registering the id_resolver key type
10582 00:24:16.248224 <5>[ 0.865397] Key type id_resolver registered
10583 00:24:16.254857 <5>[ 0.869813] Key type id_legacy registered
10584 00:24:16.261548 <6>[ 0.874091] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10585 00:24:16.267958 <6>[ 0.881013] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10586 00:24:16.274248 <6>[ 0.888719] 9p: Installing v9fs 9p2000 file system support
10587 00:24:16.310349 <5>[ 0.926041] Key type asymmetric registered
10588 00:24:16.313985 <5>[ 0.930369] Asymmetric key parser 'x509' registered
10589 00:24:16.323570 <6>[ 0.935503] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10590 00:24:16.327776 <6>[ 0.943116] io scheduler mq-deadline registered
10591 00:24:16.330276 <6>[ 0.947876] io scheduler kyber registered
10592 00:24:16.349559 <6>[ 0.965028] EINJ: ACPI disabled.
10593 00:24:16.382799 <4>[ 0.991456] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10594 00:24:16.392195 <4>[ 1.002083] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10595 00:24:16.407681 <6>[ 1.022838] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10596 00:24:16.415086 <6>[ 1.030752] printk: console [ttyS0] disabled
10597 00:24:16.443488 <6>[ 1.055379] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10598 00:24:16.450229 <6>[ 1.064848] printk: console [ttyS0] enabled
10599 00:24:16.453019 <6>[ 1.064848] printk: console [ttyS0] enabled
10600 00:24:16.459887 <6>[ 1.073744] printk: bootconsole [mtk8250] disabled
10601 00:24:16.462988 <6>[ 1.073744] printk: bootconsole [mtk8250] disabled
10602 00:24:16.469678 <6>[ 1.084790] SuperH (H)SCI(F) driver initialized
10603 00:24:16.472659 <6>[ 1.090057] msm_serial: driver initialized
10604 00:24:16.486894 <6>[ 1.098890] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10605 00:24:16.497100 <6>[ 1.107435] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10606 00:24:16.503325 <6>[ 1.115977] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10607 00:24:16.513350 <6>[ 1.124603] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10608 00:24:16.523333 <6>[ 1.133309] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10609 00:24:16.529492 <6>[ 1.142022] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10610 00:24:16.539533 <6>[ 1.150564] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10611 00:24:16.545954 <6>[ 1.159364] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10612 00:24:16.556513 <6>[ 1.167907] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10613 00:24:16.567968 <6>[ 1.183395] loop: module loaded
10614 00:24:16.574802 <6>[ 1.189335] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10615 00:24:16.596650 <4>[ 1.212117] mtk-pmic-keys: Failed to locate of_node [id: -1]
10616 00:24:16.603397 <6>[ 1.218907] megasas: 07.719.03.00-rc1
10617 00:24:16.613572 <6>[ 1.228588] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10618 00:24:16.620194 <6>[ 1.235883] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10619 00:24:16.636626 <6>[ 1.252205] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10620 00:24:16.696457 <6>[ 1.305413] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10621 00:24:16.965079 <6>[ 1.580436] Freeing initrd memory: 18304K
10622 00:24:16.976487 <6>[ 1.592091] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10623 00:24:16.987842 <6>[ 1.602988] tun: Universal TUN/TAP device driver, 1.6
10624 00:24:16.990748 <6>[ 1.609065] thunder_xcv, ver 1.0
10625 00:24:16.993946 <6>[ 1.612568] thunder_bgx, ver 1.0
10626 00:24:16.997390 <6>[ 1.616059] nicpf, ver 1.0
10627 00:24:17.008116 <6>[ 1.620087] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10628 00:24:17.011606 <6>[ 1.627563] hns3: Copyright (c) 2017 Huawei Corporation.
10629 00:24:17.014534 <6>[ 1.633148] hclge is initializing
10630 00:24:17.021133 <6>[ 1.636726] e1000: Intel(R) PRO/1000 Network Driver
10631 00:24:17.027724 <6>[ 1.641855] e1000: Copyright (c) 1999-2006 Intel Corporation.
10632 00:24:17.031372 <6>[ 1.647866] e1000e: Intel(R) PRO/1000 Network Driver
10633 00:24:17.037743 <6>[ 1.653082] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10634 00:24:17.044315 <6>[ 1.659267] igb: Intel(R) Gigabit Ethernet Network Driver
10635 00:24:17.051192 <6>[ 1.664917] igb: Copyright (c) 2007-2014 Intel Corporation.
10636 00:24:17.057535 <6>[ 1.670756] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10637 00:24:17.064296 <6>[ 1.677274] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10638 00:24:17.067676 <6>[ 1.683730] sky2: driver version 1.30
10639 00:24:17.074322 <6>[ 1.688659] usbcore: registered new device driver r8152-cfgselector
10640 00:24:17.080950 <6>[ 1.695193] usbcore: registered new interface driver r8152
10641 00:24:17.087164 <6>[ 1.701010] VFIO - User Level meta-driver version: 0.3
10642 00:24:17.093954 <6>[ 1.709239] usbcore: registered new interface driver usb-storage
10643 00:24:17.100266 <6>[ 1.715678] usbcore: registered new device driver onboard-usb-hub
10644 00:24:17.109185 <6>[ 1.724767] mt6397-rtc mt6359-rtc: registered as rtc0
10645 00:24:17.119301 <6>[ 1.730233] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-21T00:24:17 UTC (1718929457)
10646 00:24:17.122525 <6>[ 1.739789] i2c_dev: i2c /dev entries driver
10647 00:24:17.136722 <4>[ 1.751781] cpu cpu0: supply cpu not found, using dummy regulator
10648 00:24:17.143510 <4>[ 1.758218] cpu cpu1: supply cpu not found, using dummy regulator
10649 00:24:17.149987 <4>[ 1.764622] cpu cpu2: supply cpu not found, using dummy regulator
10650 00:24:17.156191 <4>[ 1.771027] cpu cpu3: supply cpu not found, using dummy regulator
10651 00:24:17.163232 <4>[ 1.777430] cpu cpu4: supply cpu not found, using dummy regulator
10652 00:24:17.169318 <4>[ 1.783828] cpu cpu5: supply cpu not found, using dummy regulator
10653 00:24:17.175966 <4>[ 1.790236] cpu cpu6: supply cpu not found, using dummy regulator
10654 00:24:17.182663 <4>[ 1.796633] cpu cpu7: supply cpu not found, using dummy regulator
10655 00:24:17.201714 <6>[ 1.817258] cpu cpu0: EM: created perf domain
10656 00:24:17.205232 <6>[ 1.822171] cpu cpu4: EM: created perf domain
10657 00:24:17.212460 <6>[ 1.827754] sdhci: Secure Digital Host Controller Interface driver
10658 00:24:17.219086 <6>[ 1.834186] sdhci: Copyright(c) Pierre Ossman
10659 00:24:17.225317 <6>[ 1.839136] Synopsys Designware Multimedia Card Interface Driver
10660 00:24:17.232232 <6>[ 1.845761] sdhci-pltfm: SDHCI platform and OF driver helper
10661 00:24:17.235752 <6>[ 1.845774] mmc0: CQHCI version 5.10
10662 00:24:17.242139 <6>[ 1.855709] ledtrig-cpu: registered to indicate activity on CPUs
10663 00:24:17.248677 <6>[ 1.862599] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10664 00:24:17.255499 <6>[ 1.869643] usbcore: registered new interface driver usbhid
10665 00:24:17.258850 <6>[ 1.875465] usbhid: USB HID core driver
10666 00:24:17.265311 <6>[ 1.879672] spi_master spi0: will run message pump with realtime priority
10667 00:24:17.310650 <6>[ 1.919393] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10668 00:24:17.329704 <6>[ 1.935390] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10669 00:24:17.333306 <6>[ 1.945614] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x17814
10670 00:24:17.339971 <6>[ 1.955752] cros-ec-spi spi0.0: Chrome EC device registered
10671 00:24:17.347477 <6>[ 1.961742] mmc0: Command Queue Engine enabled
10672 00:24:17.354109 <6>[ 1.966475] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10673 00:24:17.357008 <6>[ 1.973999] mmcblk0: mmc0:0001 DA4128 116 GiB
10674 00:24:17.367691 <6>[ 1.983279] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10675 00:24:17.375557 <6>[ 1.990763] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10676 00:24:17.385406 <6>[ 1.995123] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10677 00:24:17.388743 <6>[ 1.996709] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10678 00:24:17.394910 <6>[ 2.006585] NET: Registered PF_PACKET protocol family
10679 00:24:17.402124 <6>[ 2.011191] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10680 00:24:17.405391 <6>[ 2.015895] 9pnet: Installing 9P2000 support
10681 00:24:17.411389 <5>[ 2.026904] Key type dns_resolver registered
10682 00:24:17.414842 <6>[ 2.031865] registered taskstats version 1
10683 00:24:17.421947 <5>[ 2.036245] Loading compiled-in X.509 certificates
10684 00:24:17.450292 <4>[ 2.059154] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10685 00:24:17.459718 <4>[ 2.069917] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10686 00:24:17.475372 <6>[ 2.091087] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10687 00:24:17.482925 <6>[ 2.097986] xhci-mtk 11200000.usb: xHCI Host Controller
10688 00:24:17.489198 <6>[ 2.103493] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10689 00:24:17.499481 <6>[ 2.111368] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10690 00:24:17.505863 <6>[ 2.120798] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10691 00:24:17.512815 <6>[ 2.127015] xhci-mtk 11200000.usb: xHCI Host Controller
10692 00:24:17.518962 <6>[ 2.132514] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10693 00:24:17.526230 <6>[ 2.140170] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10694 00:24:17.532499 <6>[ 2.147984] hub 1-0:1.0: USB hub found
10695 00:24:17.535956 <6>[ 2.152007] hub 1-0:1.0: 1 port detected
10696 00:24:17.545480 <6>[ 2.156289] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10697 00:24:17.549292 <6>[ 2.165019] hub 2-0:1.0: USB hub found
10698 00:24:17.552069 <6>[ 2.169049] hub 2-0:1.0: 1 port detected
10699 00:24:17.560858 <6>[ 2.176277] mtk-msdc 11f70000.mmc: Got CD GPIO
10700 00:24:17.577398 <6>[ 2.189774] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10701 00:24:17.587697 <6>[ 2.198242] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10702 00:24:17.594622 <6>[ 2.206585] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10703 00:24:17.603971 <6>[ 2.214938] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10704 00:24:17.610510 <6>[ 2.223281] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10705 00:24:17.620792 <6>[ 2.231630] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10706 00:24:17.627264 <6>[ 2.239967] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10707 00:24:17.637117 <6>[ 2.248316] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10708 00:24:17.643573 <6>[ 2.256655] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10709 00:24:17.653656 <6>[ 2.265004] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10710 00:24:17.661018 <6>[ 2.273342] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10711 00:24:17.670035 <6>[ 2.281696] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10712 00:24:17.677063 <6>[ 2.290036] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10713 00:24:17.686955 <6>[ 2.298386] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10714 00:24:17.693887 <6>[ 2.306724] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10715 00:24:17.700106 <6>[ 2.315416] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10716 00:24:17.706786 <6>[ 2.322564] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10717 00:24:17.713952 <6>[ 2.329357] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10718 00:24:17.723805 <6>[ 2.336134] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10719 00:24:17.730368 <6>[ 2.343058] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10720 00:24:17.737060 <6>[ 2.349936] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10721 00:24:17.746808 <6>[ 2.359066] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10722 00:24:17.757127 <6>[ 2.368185] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10723 00:24:17.766955 <6>[ 2.377480] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10724 00:24:17.776741 <6>[ 2.386947] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10725 00:24:17.786323 <6>[ 2.396417] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10726 00:24:17.793205 <6>[ 2.405538] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10727 00:24:17.803116 <6>[ 2.415004] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10728 00:24:17.813219 <6>[ 2.424123] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10729 00:24:17.822872 <6>[ 2.433419] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10730 00:24:17.832672 <6>[ 2.443610] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10731 00:24:17.842843 <6>[ 2.455139] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10732 00:24:17.850555 <6>[ 2.466160] Trying to probe devices needed for running init ...
10733 00:24:17.861172 <3>[ 2.473471] mt8192-audio 11210000.syscon:mt8192-afe-pcm: could not get audiosys reset:-517
10734 00:24:17.968620 <6>[ 2.580832] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10735 00:24:18.126639 <6>[ 2.742357] hub 1-1:1.0: USB hub found
10736 00:24:18.130224 <6>[ 2.746861] hub 1-1:1.0: 4 ports detected
10737 00:24:18.140856 <6>[ 2.756521] hub 1-1:1.0: USB hub found
10738 00:24:18.144133 <6>[ 2.760918] hub 1-1:1.0: 4 ports detected
10739 00:24:18.252867 <6>[ 2.864911] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10740 00:24:18.278590 <6>[ 2.893926] hub 2-1:1.0: USB hub found
10741 00:24:18.281432 <6>[ 2.898387] hub 2-1:1.0: 3 ports detected
10742 00:24:18.292501 <6>[ 2.908224] hub 2-1:1.0: USB hub found
10743 00:24:18.295469 <6>[ 2.912724] hub 2-1:1.0: 3 ports detected
10744 00:24:18.468475 <6>[ 3.080802] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10745 00:24:18.601234 <6>[ 3.216770] hub 1-1.4:1.0: USB hub found
10746 00:24:18.604609 <6>[ 3.221399] hub 1-1.4:1.0: 2 ports detected
10747 00:24:18.616514 <6>[ 3.232080] hub 1-1.4:1.0: USB hub found
10748 00:24:18.619776 <6>[ 3.236650] hub 1-1.4:1.0: 2 ports detected
10749 00:24:18.680560 <6>[ 3.292924] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10750 00:24:18.788729 <6>[ 3.401432] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10751 00:24:18.825465 <4>[ 3.437841] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10752 00:24:18.835186 <4>[ 3.446962] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10753 00:24:18.870521 <6>[ 3.486380] r8152 2-1.3:1.0 eth0: v1.12.13
10754 00:24:18.916457 <6>[ 3.528722] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10755 00:24:19.112089 <6>[ 3.724861] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10756 00:24:20.558434 <6>[ 5.174264] r8152 2-1.3:1.0 eth0: carrier on
10757 00:24:22.843904 <5>[ 5.196600] Sending DHCP requests .., OK
10758 00:24:22.850704 <6>[ 7.464937] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10759 00:24:22.854124 <6>[ 7.473235] IP-Config: Complete:
10760 00:24:22.867917 <6>[ 7.476730] device=eth0, hwaddr=00:e0:4c:68:02:81, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10761 00:24:22.873929 <6>[ 7.487451] host=mt8192-asurada-spherion-r0-cbg-9, domain=lava-rack, nis-domain=(none)
10762 00:24:22.880460 <6>[ 7.496070] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10763 00:24:22.887226 <6>[ 7.496079] nameserver0=192.168.201.1
10764 00:24:22.890908 <6>[ 7.508247] clk: Disabling unused clocks
10765 00:24:22.894287 <6>[ 7.513712] ALSA device list:
10766 00:24:22.900837 <6>[ 7.517016] No soundcards found.
10767 00:24:22.908274 <6>[ 7.524645] Freeing unused kernel memory: 8512K
10768 00:24:22.911724 <6>[ 7.529649] Run /init as init process
10769 00:24:22.922089 Loading, please wait...
10770 00:24:22.949691 Starting systemd-udevd version 252.22-1~deb12u1
10771 00:24:23.193499 <6>[ 7.806272] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10772 00:24:23.209053 <6>[ 7.825268] remoteproc remoteproc0: scp is available
10773 00:24:23.215655 <6>[ 7.825865] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10774 00:24:23.225280 <6>[ 7.825909] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10775 00:24:23.232046 <6>[ 7.828682] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10776 00:24:23.242032 <6>[ 7.828687] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10777 00:24:23.248598 <4>[ 7.828795] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10778 00:24:23.258427 <6>[ 7.829307] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10779 00:24:23.264939 <6>[ 7.829310] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10780 00:24:23.275269 <6>[ 7.829551] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10781 00:24:23.281547 <6>[ 7.829563] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10782 00:24:23.288410 <6>[ 7.829578] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10783 00:24:23.297988 <6>[ 7.829585] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10784 00:24:23.304842 <6>[ 7.832432] remoteproc remoteproc0: powering up scp
10785 00:24:23.311512 <6>[ 7.838921] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10786 00:24:23.320970 <3>[ 7.841677] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10787 00:24:23.327649 <3>[ 7.841701] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10788 00:24:23.338138 <3>[ 7.841712] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10789 00:24:23.343994 <6>[ 7.846170] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10790 00:24:23.350802 <6>[ 7.846205] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10791 00:24:23.357160 <3>[ 7.846401] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10792 00:24:23.367580 <6>[ 7.854263] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10793 00:24:23.377050 <3>[ 7.862140] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10794 00:24:23.383584 <4>[ 7.920655] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10795 00:24:23.389980 <3>[ 7.925072] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10796 00:24:23.397524 <4>[ 7.936119] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10797 00:24:23.406752 <3>[ 7.941923] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10798 00:24:23.410296 <6>[ 7.960126] mc: Linux media interface: v0.10
10799 00:24:23.420235 <3>[ 7.966513] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10800 00:24:23.426687 <6>[ 7.972447] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10801 00:24:23.433370 <6>[ 7.972448] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10802 00:24:23.443263 <3>[ 7.985815] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10803 00:24:23.450244 <6>[ 7.988933] remoteproc remoteproc0: remote processor scp is now up
10804 00:24:23.456527 <6>[ 7.994605] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10805 00:24:23.462924 <6>[ 7.994620] pci_bus 0000:00: root bus resource [bus 00-ff]
10806 00:24:23.469676 <6>[ 7.994631] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10807 00:24:23.479265 <6>[ 7.994638] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10808 00:24:23.486799 <6>[ 7.994727] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10809 00:24:23.493383 <6>[ 7.994760] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10810 00:24:23.496733 <6>[ 7.994876] pci 0000:00:00.0: supports D1 D2
10811 00:24:23.503360 <6>[ 7.994880] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10812 00:24:23.513188 <6>[ 7.996929] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10813 00:24:23.520934 <6>[ 7.997509] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10814 00:24:23.527103 <3>[ 7.998659] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10815 00:24:23.534047 <3>[ 7.998670] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10816 00:24:23.543504 <3>[ 7.998676] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10817 00:24:23.550328 <3>[ 7.998748] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10818 00:24:23.560018 <3>[ 7.998752] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10819 00:24:23.567062 <3>[ 7.998755] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10820 00:24:23.577052 <3>[ 7.998762] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10821 00:24:23.583091 <3>[ 7.998765] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10822 00:24:23.589846 <3>[ 7.998784] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10823 00:24:23.599551 <6>[ 8.003801] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10824 00:24:23.606239 <6>[ 8.006305] videodev: Linux video capture interface: v2.00
10825 00:24:23.612810 <6>[ 8.012673] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10826 00:24:23.619308 <6>[ 8.034199] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10827 00:24:23.629560 <6>[ 8.040513] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10828 00:24:23.636047 <6>[ 8.051316] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10829 00:24:23.643027 <6>[ 8.056074] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10830 00:24:23.652620 <4>[ 8.068752] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10831 00:24:23.655743 <4>[ 8.068752] Fallback method does not support PEC.
10832 00:24:23.662452 <6>[ 8.070685] pci 0000:01:00.0: supports D1 D2
10833 00:24:23.673186 <6>[ 8.081454] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10834 00:24:23.678809 <6>[ 8.083174] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10835 00:24:23.685381 <6>[ 8.092721] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10836 00:24:23.692252 <3>[ 8.109163] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10837 00:24:23.702395 <6>[ 8.109226] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10838 00:24:23.712076 <6>[ 8.109527] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10839 00:24:23.722231 <6>[ 8.114132] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10840 00:24:23.724978 <6>[ 8.134390] Bluetooth: Core ver 2.22
10841 00:24:23.731930 <6>[ 8.139993] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10842 00:24:23.741502 <3>[ 8.143440] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10843 00:24:23.748354 <6>[ 8.148150] NET: Registered PF_BLUETOOTH protocol family
10844 00:24:23.755078 <6>[ 8.156157] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10845 00:24:23.761303 <6>[ 8.164224] Bluetooth: HCI device and connection manager initialized
10846 00:24:23.768471 <6>[ 8.164238] Bluetooth: HCI socket layer initialized
10847 00:24:23.774839 <6>[ 8.172314] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10848 00:24:23.781505 <6>[ 8.173859] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10849 00:24:23.794606 <6>[ 8.175104] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10850 00:24:23.801478 <6>[ 8.175208] usbcore: registered new interface driver uvcvideo
10851 00:24:23.805156 <6>[ 8.180381] Bluetooth: L2CAP socket layer initialized
10852 00:24:23.814620 <6>[ 8.188467] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10853 00:24:23.818111 <6>[ 8.196553] Bluetooth: SCO socket layer initialized
10854 00:24:23.824840 <6>[ 8.204620] pci 0000:00:00.0: PCI bridge to [bus 01]
10855 00:24:23.830828 <6>[ 8.213770] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10856 00:24:23.837922 <6>[ 8.220337] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10857 00:24:23.844775 <6>[ 8.265478] usbcore: registered new interface driver btusb
10858 00:24:23.854016 <4>[ 8.266599] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10859 00:24:23.860777 <3>[ 8.266606] Bluetooth: hci0: Failed to load firmware file (-2)
10860 00:24:23.867062 <3>[ 8.266607] Bluetooth: hci0: Failed to set up firmware (-2)
10861 00:24:23.877013 <4>[ 8.266610] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10862 00:24:23.883662 <6>[ 8.278754] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10863 00:24:23.890150 <6>[ 8.505038] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10864 00:24:23.896845 <6>[ 8.511462] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10865 00:24:23.911851 <5>[ 8.524941] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10866 00:24:23.932119 <5>[ 8.545146] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10867 00:24:23.938660 <5>[ 8.552544] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10868 00:24:23.948720 <4>[ 8.561001] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10869 00:24:23.954703 <6>[ 8.569900] cfg80211: failed to load regulatory.db
10870 00:24:24.001244 <6>[ 8.614699] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10871 00:24:24.007989 <6>[ 8.622211] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10872 00:24:24.031927 <6>[ 8.648972] mt7921e 0000:01:00.0: ASIC revision: 79610010
10873 00:24:24.135402 <6>[ 8.748451] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10874 00:24:24.138452 <6>[ 8.748451]
10875 00:24:24.153265 Begin: Loading essential drivers ... done.
10876 00:24:24.156863 Begin: Running /scripts/init-premount ... done.
10877 00:24:24.163254 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10878 00:24:24.172976 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10879 00:24:24.176400 Device /sys/class/net/eth0 found
10880 00:24:24.176820 done.
10881 00:24:24.200283 Begin: Waiting up to 180 secs for any network device to become available ... done.
10882 00:24:24.264288 IP-Config: eth0 hardware address 00:e0:4c:68:02:81 mtu 1500 DHCP
10883 00:24:24.272158 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10884 00:24:24.279147 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10885 00:24:24.286049 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10886 00:24:24.292826 host : mt8192-asurada-spherion-r0-cbg-9
10887 00:24:24.298924 domain : lava-rack
10888 00:24:24.301823 rootserver: 192.168.201.1 rootpath:
10889 00:24:24.305296 filename :
10890 00:24:24.402019 <6>[ 9.015712] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10891 00:24:24.449355 done.
10892 00:24:24.457499 Begin: Running /scripts/nfs-bottom ... done.
10893 00:24:24.473635 Begin: Running /scripts/init-bottom ... done.
10894 00:24:25.853665 <6>[ 10.470654] NET: Registered PF_INET6 protocol family
10895 00:24:25.861375 <6>[ 10.478298] Segment Routing with IPv6
10896 00:24:25.864602 <6>[ 10.482300] In-situ OAM (IOAM) with IPv6
10897 00:24:26.044541 <30>[ 10.634102] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10898 00:24:26.050712 <30>[ 10.667243] systemd[1]: Detected architecture arm64.
10899 00:24:26.061819
10900 00:24:26.064819 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10901 00:24:26.065293
10902 00:24:26.094676 <30>[ 10.711164] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10903 00:24:27.319021 <30>[ 11.932679] systemd[1]: Queued start job for default target graphical.target.
10904 00:24:27.364226 <30>[ 11.977733] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10905 00:24:27.370668 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10906 00:24:27.393431 <30>[ 12.006629] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10907 00:24:27.403416 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10908 00:24:27.421480 <30>[ 12.034527] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10909 00:24:27.431001 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10910 00:24:27.449592 <30>[ 12.062968] systemd[1]: Created slice user.slice - User and Session Slice.
10911 00:24:27.456018 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10912 00:24:27.479135 <30>[ 12.089554] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10913 00:24:27.489193 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10914 00:24:27.506890 <30>[ 12.117121] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10915 00:24:27.513626 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10916 00:24:27.541856 <30>[ 12.145405] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10917 00:24:27.551825 <30>[ 12.165313] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10918 00:24:27.558267 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10919 00:24:27.575666 <30>[ 12.189204] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10920 00:24:27.585595 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10921 00:24:27.603345 <30>[ 12.216858] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10922 00:24:27.613157 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10923 00:24:27.628445 <30>[ 12.245346] systemd[1]: Reached target paths.target - Path Units.
10924 00:24:27.638462 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10925 00:24:27.655897 <30>[ 12.269283] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10926 00:24:27.662475 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10927 00:24:27.675826 <30>[ 12.292762] systemd[1]: Reached target slices.target - Slice Units.
10928 00:24:27.686455 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10929 00:24:27.700526 <30>[ 12.317292] systemd[1]: Reached target swap.target - Swaps.
10930 00:24:27.707368 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10931 00:24:27.728013 <30>[ 12.341572] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10932 00:24:27.737894 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10933 00:24:27.756385 <30>[ 12.369781] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10934 00:24:27.766118 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10935 00:24:27.786893 <30>[ 12.400375] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10936 00:24:27.796816 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10937 00:24:27.812955 <30>[ 12.426436] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10938 00:24:27.822672 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10939 00:24:27.840216 <30>[ 12.453489] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10940 00:24:27.846722 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10941 00:24:27.864941 <30>[ 12.478412] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10942 00:24:27.874903 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10943 00:24:27.894441 <30>[ 12.508165] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10944 00:24:27.903873 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10945 00:24:27.919918 <30>[ 12.533253] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10946 00:24:27.929481 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10947 00:24:27.979411 <30>[ 12.593277] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10948 00:24:27.985984 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10949 00:24:28.005985 <30>[ 12.619310] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10950 00:24:28.012432 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10951 00:24:28.035065 <30>[ 12.648667] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10952 00:24:28.041643 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10953 00:24:28.065853 <30>[ 12.673275] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10954 00:24:28.081687 <30>[ 12.695569] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10955 00:24:28.092618 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10956 00:24:28.117126 <30>[ 12.730657] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10957 00:24:28.123515 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10958 00:24:28.149307 <30>[ 12.762271] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10959 00:24:28.158222 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10960 00:24:28.180905 <30>[ 12.794657] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10961 00:24:28.187197 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10962 00:24:28.197506 <6>[ 12.810694] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10963 00:24:28.235866 <30>[ 12.849769] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10964 00:24:28.246541 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10965 00:24:28.269352 <30>[ 12.882691] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10966 00:24:28.275607 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10967 00:24:28.300696 <30>[ 12.914538] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10968 00:24:28.311142 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kern<6>[ 12.927751] fuse: init (API version 7.37)
10969 00:24:28.314421 el Module loop...
10970 00:24:28.376439 <30>[ 12.989697] systemd[1]: Starting systemd-journald.service - Journal Service...
10971 00:24:28.382626 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10972 00:24:28.417904 <30>[ 13.031275] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10973 00:24:28.423902 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10974 00:24:28.487363 <30>[ 13.097558] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10975 00:24:28.493998 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10976 00:24:28.515966 <30>[ 13.129440] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10977 00:24:28.525319 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10978 00:24:28.548060 <30>[ 13.161657] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10979 00:24:28.555143 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10980 00:24:28.581809 <30>[ 13.195260] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10981 00:24:28.588806 <3>[ 13.200172] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10982 00:24:28.598281 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10983 00:24:28.616044 <30>[ 13.229206] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10984 00:24:28.622995 <3>[ 13.234105] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10985 00:24:28.632347 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10986 00:24:28.651954 <30>[ 13.265051] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10987 00:24:28.661699 [[0;32m OK [0m] Mounted [0;<3>[ 13.275138] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10988 00:24:28.668064 1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10989 00:24:28.687614 <30>[ 13.301247] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10990 00:24:28.698008 <3>[ 13.304952] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10991 00:24:28.704460 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10992 00:24:28.723767 <30>[ 13.337547] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10993 00:24:28.730314 <3>[ 13.339636] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10994 00:24:28.740945 <30>[ 13.345486] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10995 00:24:28.747242 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10996 00:24:28.761576 <3>[ 13.374767] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10997 00:24:28.771332 <30>[ 13.384908] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10998 00:24:28.778219 <30>[ 13.392602] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10999 00:24:28.791815 [[0;32m OK [0m] Finished [0;1;39mmodprobe@d<3>[ 13.405171] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11000 00:24:28.794858 m_mod.s…e[0m - Load Kernel Module dm_mod.
11001 00:24:28.813634 <30>[ 13.429772] systemd[1]: modprobe@drm.service: Deactivated successfully.
11002 00:24:28.824249 <30>[ 13.437461] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
11003 00:24:28.830792 <3>[ 13.438386] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11004 00:24:28.840474 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
11005 00:24:28.861247 <30>[ 13.474635] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
11006 00:24:28.867821 <3>[ 13.475415] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11007 00:24:28.877764 <30>[ 13.482732] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
11008 00:24:28.887501 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
11009 00:24:28.902187 <3>[ 13.515875] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11010 00:24:28.912720 <30>[ 13.526573] systemd[1]: modprobe@fuse.service: Deactivated successfully.
11011 00:24:28.919677 <30>[ 13.534345] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
11012 00:24:28.929788 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
11013 00:24:28.949143 <30>[ 13.561991] systemd[1]: modprobe@loop.service: Deactivated successfully.
11014 00:24:28.955620 <30>[ 13.569852] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
11015 00:24:28.965368 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
11016 00:24:28.986959 <4>[ 13.593845] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
11017 00:24:28.996717 <3>[ 13.609504] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
11018 00:24:29.003490 <30>[ 13.610199] systemd[1]: Started systemd-journald.service - Journal Service.
11019 00:24:29.010309 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
11020 00:24:29.036338 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
11021 00:24:29.056593 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
11022 00:24:29.076867 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
11023 00:24:29.096660 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
11024 00:24:29.117905 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
11025 00:24:29.175581 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
11026 00:24:29.197730 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
11027 00:24:29.220651 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
11028 00:24:29.243556 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
11029 00:24:29.269450 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
11030 00:24:29.297619 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
11031 00:24:29.311869 <46>[ 13.925203] systemd-journald[308]: Received client request to flush runtime journal.
11032 00:24:29.337587 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
11033 00:24:29.357193 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
11034 00:24:29.380364 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
11035 00:24:29.404574 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
11036 00:24:29.836455 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
11037 00:24:29.891895 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
11038 00:24:30.744539 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
11039 00:24:30.798155 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
11040 00:24:30.819847 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
11041 00:24:30.839260 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
11042 00:24:30.891652 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
11043 00:24:30.916970 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
11044 00:24:31.175300 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11045 00:24:31.233532 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11046 00:24:31.291448 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11047 00:24:31.585409 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11048 00:24:31.615016 <6>[ 16.232795] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11049 00:24:31.640951 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11050 00:24:31.708986 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11051 00:24:31.786855 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11052 00:24:31.806097 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11053 00:24:31.829256 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11054 00:24:31.895861 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11055 00:24:31.926444 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11056 00:24:31.952550 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11057 00:24:31.972213 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11058 00:24:31.992312 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11059 00:24:32.021375 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11060 00:24:32.050360 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11061 00:24:32.116701 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11062 00:24:32.139585 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11063 00:24:32.160420 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11064 00:24:32.178722 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11065 00:24:32.203343 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11066 00:24:32.223218 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11067 00:24:32.239772 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11068 00:24:32.264203 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11069 00:24:32.288140 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11070 00:24:32.307687 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11071 00:24:32.326195 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11072 00:24:32.343016 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11073 00:24:32.349670 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11074 00:24:32.397842 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11075 00:24:32.456919 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11076 00:24:32.557177 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11077 00:24:32.582519 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11078 00:24:32.648167 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11079 00:24:32.704156 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11080 00:24:32.735643 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11081 00:24:32.759967 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11082 00:24:32.843722 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11083 00:24:32.885156 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11084 00:24:32.905939 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11085 00:24:32.924621 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11086 00:24:32.943728 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11087 00:24:32.989016 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11088 00:24:33.044533 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11089 00:24:33.131431
11090 00:24:33.134269 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11091 00:24:33.134698
11092 00:24:33.137884 debian-bookworm-arm64 login: root (automatic login)
11093 00:24:33.138456
11094 00:24:33.466259 Linux debian-bookworm-arm64 6.1.94-cip23 #1 SMP PREEMPT Fri Jun 21 00:04:56 UTC 2024 aarch64
11095 00:24:33.466844
11096 00:24:33.472851 The programs included with the Debian GNU/Linux system are free software;
11097 00:24:33.479818 the exact distribution terms for each program are described in the
11098 00:24:33.483039 individual files in /usr/share/doc/*/copyright.
11099 00:24:33.483621
11100 00:24:33.489956 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11101 00:24:33.492963 permitted by applicable law.
11102 00:24:34.663646 Matched prompt #10: / #
11104 00:24:34.665002 Setting prompt string to ['/ #']
11105 00:24:34.665541 end: 2.2.5.1 login-action (duration 00:00:20) [common]
11107 00:24:34.666785 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
11108 00:24:34.667327 start: 2.2.6 expect-shell-connection (timeout 00:03:09) [common]
11109 00:24:34.667778 Setting prompt string to ['/ #']
11110 00:24:34.668158 Forcing a shell prompt, looking for ['/ #']
11112 00:24:34.719156 / #
11113 00:24:34.719861 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11114 00:24:34.720357 Waiting using forced prompt support (timeout 00:02:30)
11115 00:24:34.725503
11116 00:24:34.726436 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11117 00:24:34.727156 start: 2.2.7 export-device-env (timeout 00:03:09) [common]
11119 00:24:34.828486 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14479184/extract-nfsrootfs-yktrmthu'
11120 00:24:34.835059 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14479184/extract-nfsrootfs-yktrmthu'
11122 00:24:34.937240 / # export NFS_SERVER_IP='192.168.201.1'
11123 00:24:34.943908 export NFS_SERVER_IP='192.168.201.1'
11124 00:24:34.944860 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11125 00:24:34.945379 end: 2.2 depthcharge-retry (duration 00:01:51) [common]
11126 00:24:34.945883 end: 2 depthcharge-action (duration 00:01:51) [common]
11127 00:24:34.946448 start: 3 lava-test-retry (timeout 00:07:25) [common]
11128 00:24:34.947184 start: 3.1 lava-test-shell (timeout 00:07:25) [common]
11129 00:24:34.947903 Using namespace: common
11131 00:24:35.049411 / # #
11132 00:24:35.050209 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11133 00:24:35.056086 #
11134 00:24:35.056953 Using /lava-14479184
11136 00:24:35.158352 / # export SHELL=/bin/bash
11137 00:24:35.165350 export SHELL=/bin/bash
11139 00:24:35.267123 / # . /lava-14479184/environment
11140 00:24:35.273235 . /lava-14479184/environment
11142 00:24:35.381089 / # /lava-14479184/bin/lava-test-runner /lava-14479184/0
11143 00:24:35.381711 Test shell timeout: 10s (minimum of the action and connection timeout)
11144 00:24:35.387962 /lava-14479184/bin/lava-test-runner /lava-14479184/0
11145 00:24:35.708524 + export TESTRUN_ID=0_timesync-off
11146 00:24:35.711793 + TESTRUN_ID=0_timesync-off
11147 00:24:35.714839 + cd /lava-14479184/0/tests/0_timesync-off
11148 00:24:35.718447 ++ cat uuid
11149 00:24:35.727051 + UUID=14479184_1.6.2.3.1
11150 00:24:35.727157 + set +x
11151 00:24:35.733857 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14479184_1.6.2.3.1>
11152 00:24:35.734141 Received signal: <STARTRUN> 0_timesync-off 14479184_1.6.2.3.1
11153 00:24:35.734278 Starting test lava.0_timesync-off (14479184_1.6.2.3.1)
11154 00:24:35.734387 Skipping test definition patterns.
11155 00:24:35.737068 + systemctl stop systemd-timesyncd
11156 00:24:35.819516 + set +x
11157 00:24:35.822327 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14479184_1.6.2.3.1>
11158 00:24:35.823009 Received signal: <ENDRUN> 0_timesync-off 14479184_1.6.2.3.1
11159 00:24:35.823419 Ending use of test pattern.
11160 00:24:35.823759 Ending test lava.0_timesync-off (14479184_1.6.2.3.1), duration 0.09
11162 00:24:35.919322 + export TESTRUN_ID=1_kselftest-arm64
11163 00:24:35.919468 + TESTRUN_ID=1_kselftest-arm64
11164 00:24:35.925311 + cd /lava-14479184/0/tests/1_kselftest-arm64
11165 00:24:35.925403 ++ cat uuid
11166 00:24:35.933105 + UUID=14479184_1.6.2.3.5
11167 00:24:35.933196 + set +x
11168 00:24:35.939475 <LAVA_SIGNAL_STARTRUN 1_kselftest-arm64 14479184_1.6.2.3.5>
11169 00:24:35.939739 Received signal: <STARTRUN> 1_kselftest-arm64 14479184_1.6.2.3.5
11170 00:24:35.939814 Starting test lava.1_kselftest-arm64 (14479184_1.6.2.3.5)
11171 00:24:35.939896 Skipping test definition patterns.
11172 00:24:35.942863 + cd ./automated/linux/kselftest/
11173 00:24:35.969656 + ./kselftest.sh -c arm64 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.94-cip23/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11174 00:24:36.018767 INFO: install_deps skipped
11175 00:24:36.531415 --2024-06-21 00:24:36-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.94-cip23/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11176 00:24:36.547994 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11177 00:24:36.674249 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11178 00:24:36.799232 HTTP request sent, awaiting response... 200 OK
11179 00:24:36.802110 Length: 1642760 (1.6M) [application/octet-stream]
11180 00:24:36.805876 Saving to: 'kselftest_armhf.tar.gz'
11181 00:24:36.806509
11182 00:24:36.806881
11183 00:24:37.049623 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
11184 00:24:37.299187 kselftest_armhf.tar 2%[ ] 47.81K 191KB/s
11185 00:24:37.721486 kselftest_armhf.tar 13%[=> ] 214.67K 429KB/s
11186 00:24:37.728206 kselftest_armhf.tar 51%[=========> ] 823.64K 893KB/s
11187 00:24:37.734603 kselftest_armhf.tar 100%[===================>] 1.57M 1.68MB/s in 0.9s
11188 00:24:37.734709
11189 00:24:37.879658 2024-06-21 00:24:38 (1.68 MB/s) - 'kselftest_armhf.tar.gz' saved [1642760/1642760]
11190 00:24:37.879807
11191 00:24:42.131941 skiplist:
11192 00:24:42.134991 ========================================
11193 00:24:42.138454 ========================================
11194 00:24:42.186039 arm64:tags_test
11195 00:24:42.189424 arm64:run_tags_test.sh
11196 00:24:42.189528 arm64:fake_sigreturn_bad_magic
11197 00:24:42.192842 arm64:fake_sigreturn_bad_size
11198 00:24:42.196364 arm64:fake_sigreturn_bad_size_for_magic0
11199 00:24:42.199044 arm64:fake_sigreturn_duplicated_fpsimd
11200 00:24:42.202601 arm64:fake_sigreturn_misaligned_sp
11201 00:24:42.205654 arm64:fake_sigreturn_missing_fpsimd
11202 00:24:42.209114 arm64:fake_sigreturn_sme_change_vl
11203 00:24:42.212473 arm64:fake_sigreturn_sve_change_vl
11204 00:24:42.215645 arm64:mangle_pstate_invalid_compat_toggle
11205 00:24:42.218999 arm64:mangle_pstate_invalid_daif_bits
11206 00:24:42.222269 arm64:mangle_pstate_invalid_mode_el1h
11207 00:24:42.225440 arm64:mangle_pstate_invalid_mode_el1t
11208 00:24:42.229157 arm64:mangle_pstate_invalid_mode_el2h
11209 00:24:42.232269 arm64:mangle_pstate_invalid_mode_el2t
11210 00:24:42.235364 arm64:mangle_pstate_invalid_mode_el3h
11211 00:24:42.241995 arm64:mangle_pstate_invalid_mode_el3t
11212 00:24:42.242079 arm64:sme_trap_no_sm
11213 00:24:42.245434 arm64:sme_trap_non_streaming
11214 00:24:42.245523 arm64:sme_trap_za
11215 00:24:42.248973 arm64:sme_vl
11216 00:24:42.249056 arm64:ssve_regs
11217 00:24:42.251809 arm64:sve_regs
11218 00:24:42.251891 arm64:sve_vl
11219 00:24:42.251956 arm64:za_no_regs
11220 00:24:42.255181 arm64:za_regs
11221 00:24:42.255263 arm64:pac
11222 00:24:42.258319 arm64:fp-stress
11223 00:24:42.258402 arm64:sve-ptrace
11224 00:24:42.261895 arm64:sve-probe-vls
11225 00:24:42.261977 arm64:vec-syscfg
11226 00:24:42.262042 arm64:za-fork
11227 00:24:42.264886 arm64:za-ptrace
11228 00:24:42.268580 arm64:check_buffer_fill
11229 00:24:42.268662 arm64:check_child_memory
11230 00:24:42.271489 arm64:check_gcr_el1_cswitch
11231 00:24:42.274918 arm64:check_ksm_options
11232 00:24:42.275010 arm64:check_mmap_options
11233 00:24:42.278382 arm64:check_prctl
11234 00:24:42.281418 arm64:check_tags_inclusion
11235 00:24:42.281500 arm64:check_user_mem
11236 00:24:42.285136 arm64:btitest
11237 00:24:42.285219 arm64:nobtitest
11238 00:24:42.285283 arm64:hwcap
11239 00:24:42.288073 arm64:ptrace
11240 00:24:42.288155 arm64:syscall-abi
11241 00:24:42.291322 arm64:tpidr2
11242 00:24:42.294818 ============== Tests to run ===============
11243 00:24:42.294928 arm64:tags_test
11244 00:24:42.297880 arm64:run_tags_test.sh
11245 00:24:42.301236 arm64:fake_sigreturn_bad_magic
11246 00:24:42.304607 arm64:fake_sigreturn_bad_size
11247 00:24:42.308124 arm64:fake_sigreturn_bad_size_for_magic0
11248 00:24:42.311654 arm64:fake_sigreturn_duplicated_fpsimd
11249 00:24:42.314600 arm64:fake_sigreturn_misaligned_sp
11250 00:24:42.318248 arm64:fake_sigreturn_missing_fpsimd
11251 00:24:42.321041 arm64:fake_sigreturn_sme_change_vl
11252 00:24:42.324491 arm64:fake_sigreturn_sve_change_vl
11253 00:24:42.327854 arm64:mangle_pstate_invalid_compat_toggle
11254 00:24:42.330854 arm64:mangle_pstate_invalid_daif_bits
11255 00:24:42.334627 arm64:mangle_pstate_invalid_mode_el1h
11256 00:24:42.337756 arm64:mangle_pstate_invalid_mode_el1t
11257 00:24:42.340775 arm64:mangle_pstate_invalid_mode_el2h
11258 00:24:42.344406 arm64:mangle_pstate_invalid_mode_el2t
11259 00:24:42.347213 arm64:mangle_pstate_invalid_mode_el3h
11260 00:24:42.351145 arm64:mangle_pstate_invalid_mode_el3t
11261 00:24:42.351236 arm64:sme_trap_no_sm
11262 00:24:42.354005 arm64:sme_trap_non_streaming
11263 00:24:42.357311 arm64:sme_trap_za
11264 00:24:42.357394 arm64:sme_vl
11265 00:24:42.360977 arm64:ssve_regs
11266 00:24:42.361059 arm64:sve_regs
11267 00:24:42.361123 arm64:sve_vl
11268 00:24:42.364270 arm64:za_no_regs
11269 00:24:42.364354 arm64:za_regs
11270 00:24:42.364420 arm64:pac
11271 00:24:42.367309 arm64:fp-stress
11272 00:24:42.367393 arm64:sve-ptrace
11273 00:24:42.370937 arm64:sve-probe-vls
11274 00:24:42.371022 arm64:vec-syscfg
11275 00:24:42.374045 arm64:za-fork
11276 00:24:42.374154 arm64:za-ptrace
11277 00:24:42.377557 arm64:check_buffer_fill
11278 00:24:42.380426 arm64:check_child_memory
11279 00:24:42.380508 arm64:check_gcr_el1_cswitch
11280 00:24:42.383814 arm64:check_ksm_options
11281 00:24:42.387125 arm64:check_mmap_options
11282 00:24:42.387218 arm64:check_prctl
11283 00:24:42.390721 arm64:check_tags_inclusion
11284 00:24:42.393571 arm64:check_user_mem
11285 00:24:42.393658 arm64:btitest
11286 00:24:42.393724 arm64:nobtitest
11287 00:24:42.396947 arm64:hwcap
11288 00:24:42.397048 arm64:ptrace
11289 00:24:42.400234 arm64:syscall-abi
11290 00:24:42.400333 arm64:tpidr2
11291 00:24:42.403292 ===========End Tests to run ===============
11292 00:24:42.406771 shardfile-arm64 pass
11293 00:24:42.634964 <12>[ 27.254018] kselftest: Running tests in arm64
11294 00:24:42.645309 TAP version 13
11295 00:24:42.661579 1..48
11296 00:24:42.682911 # selftests: arm64: tags_test
11297 00:24:43.142671 ok 1 selftests: arm64: tags_test
11298 00:24:43.158085 # selftests: arm64: run_tags_test.sh
11299 00:24:43.208831 # --------------------
11300 00:24:43.212326 # running tags test
11301 00:24:43.212421 # --------------------
11302 00:24:43.215560 # [PASS]
11303 00:24:43.218858 ok 2 selftests: arm64: run_tags_test.sh
11304 00:24:43.232282 # selftests: arm64: fake_sigreturn_bad_magic
11305 00:24:43.292035 # Registered handlers for all signals.
11306 00:24:43.292197 # Detected MINSTKSIGSZ:4720
11307 00:24:43.295025 # Testcase initialized.
11308 00:24:43.298453 # uc context validated.
11309 00:24:43.301690 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11310 00:24:43.305275 # Handled SIG_COPYCTX
11311 00:24:43.305397 # Available space:3568
11312 00:24:43.311466 # Using badly built context - ERR: BAD MAGIC !
11313 00:24:43.318203 # SIG_OK -- SP:0xFFFFC2760060 si_addr@:0xffffc2760060 si_code:2 token@:0xffffc275ee00 offset:-4704
11314 00:24:43.321430 # ==>> completed. PASS(1)
11315 00:24:43.328025 # # FAKE_SIGRETURN_BAD_MAGIC :: Trigger a sigreturn with a sigframe with a bad magic
11316 00:24:43.334864 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFC275EE00
11317 00:24:43.341294 ok 3 selftests: arm64: fake_sigreturn_bad_magic
11318 00:24:43.344793 # selftests: arm64: fake_sigreturn_bad_size
11319 00:24:43.388322 # Registered handlers for all signals.
11320 00:24:43.388468 # Detected MINSTKSIGSZ:4720
11321 00:24:43.391875 # Testcase initialized.
11322 00:24:43.394709 # uc context validated.
11323 00:24:43.398114 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11324 00:24:43.401649 # Handled SIG_COPYCTX
11325 00:24:43.401734 # Available space:3568
11326 00:24:43.404568 # uc context validated.
11327 00:24:43.411323 # Using badly built context - ERR: Bad size for esr_context
11328 00:24:43.417983 # SIG_OK -- SP:0xFFFFCDBC2D20 si_addr@:0xffffcdbc2d20 si_code:2 token@:0xffffcdbc1ac0 offset:-4704
11329 00:24:43.421281 # ==>> completed. PASS(1)
11330 00:24:43.427642 # # FAKE_SIGRETURN_BAD_SIZE :: Triggers a sigreturn with a overrun __reserved area
11331 00:24:43.434641 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFCDBC1AC0
11332 00:24:43.437655 ok 4 selftests: arm64: fake_sigreturn_bad_size
11333 00:24:43.444069 # selftests: arm64: fake_sigreturn_bad_size_for_magic0
11334 00:24:43.462007 # Registered handlers for all signals.
11335 00:24:43.462130 # Detected MINSTKSIGSZ:4720
11336 00:24:43.465444 # Testcase initialized.
11337 00:24:43.468483 # uc context validated.
11338 00:24:43.472115 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11339 00:24:43.475017 # Handled SIG_COPYCTX
11340 00:24:43.475103 # Available space:3568
11341 00:24:43.481973 # Using badly built context - ERR: Bad size for terminator
11342 00:24:43.491716 # SIG_OK -- SP:0xFFFFC3824E60 si_addr@:0xffffc3824e60 si_code:2 token@:0xffffc3823c00 offset:-4704
11343 00:24:43.491811 # ==>> completed. PASS(1)
11344 00:24:43.501500 # # FAKE_SIGRETURN_BAD_SIZE_FOR_TERMINATOR :: Trigger a sigreturn using non-zero size terminator
11345 00:24:43.508211 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFC3823C00
11346 00:24:43.511726 ok 5 selftests: arm64: fake_sigreturn_bad_size_for_magic0
11347 00:24:43.518316 # selftests: arm64: fake_sigreturn_duplicated_fpsimd
11348 00:24:43.544846 # Registered handlers for all signals.
11349 00:24:43.544996 # Detected MINSTKSIGSZ:4720
11350 00:24:43.548442 # Testcase initialized.
11351 00:24:43.551696 # uc context validated.
11352 00:24:43.554713 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11353 00:24:43.558321 # Handled SIG_COPYCTX
11354 00:24:43.558404 # Available space:3568
11355 00:24:43.564964 # Using badly built context - ERR: Multiple FPSIMD_MAGIC
11356 00:24:43.574389 # SIG_OK -- SP:0xFFFFDE440080 si_addr@:0xffffde440080 si_code:2 token@:0xffffde43ee20 offset:-4704
11357 00:24:43.574485 # ==>> completed. PASS(1)
11358 00:24:43.584302 # # FAKE_SIGRETURN_DUPLICATED_FPSIMD :: Triggers a sigreturn including two fpsimd_context
11359 00:24:43.591403 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFDE43EE20
11360 00:24:43.594798 ok 6 selftests: arm64: fake_sigreturn_duplicated_fpsimd
11361 00:24:43.597757 # selftests: arm64: fake_sigreturn_misaligned_sp
11362 00:24:43.635201 # Registered handlers for all signals.
11363 00:24:43.635335 # Detected MINSTKSIGSZ:4720
11364 00:24:43.638383 # Testcase initialized.
11365 00:24:43.641443 # uc context validated.
11366 00:24:43.645001 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11367 00:24:43.648417 # Handled SIG_COPYCTX
11368 00:24:43.654646 # SIG_OK -- SP:0xFFFFF81C7B13 si_addr@:0xfffff81c7b13 si_code:2 token@:0xfffff81c7b13 offset:0
11369 00:24:43.657833 # ==>> completed. PASS(1)
11370 00:24:43.664861 # # FAKE_SIGRETURN_MISALIGNED_SP :: Triggers a sigreturn with a misaligned sigframe
11371 00:24:43.671702 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFF81C7B13
11372 00:24:43.677955 ok 7 selftests: arm64: fake_sigreturn_misaligned_sp
11373 00:24:43.681299 # selftests: arm64: fake_sigreturn_missing_fpsimd
11374 00:24:43.719937 # Registered handlers for all signals.
11375 00:24:43.720067 # Detected MINSTKSIGSZ:4720
11376 00:24:43.723441 # Testcase initialized.
11377 00:24:43.726813 # uc context validated.
11378 00:24:43.730049 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11379 00:24:43.733343 # Handled SIG_COPYCTX
11380 00:24:43.736605 # Mangling template header. Spare space:4096
11381 00:24:43.740209 # Using badly built context - ERR: Missing FPSIMD
11382 00:24:43.749601 # SIG_OK -- SP:0xFFFFC8273B20 si_addr@:0xffffc8273b20 si_code:2 token@:0xffffc82728c0 offset:-4704
11383 00:24:43.752931 # ==>> completed. PASS(1)
11384 00:24:43.759629 # # FAKE_SIGRETURN_MISSING_FPSIMD :: Triggers a sigreturn with a missing fpsimd_context
11385 00:24:43.766467 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFC82728C0
11386 00:24:43.769337 ok 8 selftests: arm64: fake_sigreturn_missing_fpsimd
11387 00:24:43.776151 # selftests: arm64: fake_sigreturn_sme_change_vl
11388 00:24:43.815452 # Registered handlers for all signals.
11389 00:24:43.815588 # Detected MINSTKSIGSZ:4720
11390 00:24:43.818557 # ==>> completed. SKIP.
11391 00:24:43.824962 # # FAKE_SIGRETURN_SSVE_CHANGE :: Attempt to change Streaming SVE VL
11392 00:24:43.828653 ok 9 selftests: arm64: fake_sigreturn_sme_change_vl # SKIP
11393 00:24:43.835602 # selftests: arm64: fake_sigreturn_sve_change_vl
11394 00:24:43.899693 # Registered handlers for all signals.
11395 00:24:43.899840 # Detected MINSTKSIGSZ:4720
11396 00:24:43.903029 # ==>> completed. SKIP.
11397 00:24:43.910242 # # FAKE_SIGRETURN_SVE_CHANGE :: Attempt to change SVE VL
11398 00:24:43.913096 ok 10 selftests: arm64: fake_sigreturn_sve_change_vl # SKIP
11399 00:24:43.928419 # selftests: arm64: mangle_pstate_invalid_compat_toggle
11400 00:24:43.991482 # Registered handlers for all signals.
11401 00:24:43.991631 # Detected MINSTKSIGSZ:4720
11402 00:24:43.994701 # Testcase initialized.
11403 00:24:43.998363 # uc context validated.
11404 00:24:43.998445 # Handled SIG_TRIG
11405 00:24:44.008331 # SIG_OK -- SP:0xFFFFCB7D6150 si_addr@:0xffffcb7d6150 si_code:2 token@:(nil) offset:-281474095735120
11406 00:24:44.011211 # ==>> completed. PASS(1)
11407 00:24:44.017636 # # MANGLE_PSTATE_INVALID_STATE_TOGGLE :: Mangling uc_mcontext with INVALID STATE_TOGGLE
11408 00:24:44.024979 ok 11 selftests: arm64: mangle_pstate_invalid_compat_toggle
11409 00:24:44.027738 # selftests: arm64: mangle_pstate_invalid_daif_bits
11410 00:24:44.071500 # Registered handlers for all signals.
11411 00:24:44.071641 # Detected MINSTKSIGSZ:4720
11412 00:24:44.074996 # Testcase initialized.
11413 00:24:44.078465 # uc context validated.
11414 00:24:44.078561 # Handled SIG_TRIG
11415 00:24:44.088245 # SIG_OK -- SP:0xFFFFCC54AF20 si_addr@:0xffffcc54af20 si_code:2 token@:(nil) offset:-281474109845280
11416 00:24:44.091539 # ==>> completed. PASS(1)
11417 00:24:44.098486 # # MANGLE_PSTATE_INVALID_DAIF_BITS :: Mangling uc_mcontext with INVALID DAIF_BITS
11418 00:24:44.101352 ok 12 selftests: arm64: mangle_pstate_invalid_daif_bits
11419 00:24:44.107772 # selftests: arm64: mangle_pstate_invalid_mode_el1h
11420 00:24:44.147434 # Registered handlers for all signals.
11421 00:24:44.147572 # Detected MINSTKSIGSZ:4720
11422 00:24:44.150614 # Testcase initialized.
11423 00:24:44.153961 # uc context validated.
11424 00:24:44.154069 # Handled SIG_TRIG
11425 00:24:44.163310 # SIG_OK -- SP:0xFFFFF3B50C90 si_addr@:0xfffff3b50c90 si_code:2 token@:(nil) offset:-281474770472080
11426 00:24:44.166721 # ==>> completed. PASS(1)
11427 00:24:44.173257 # # MANGLE_PSTATE_INVALID_MODE_EL1h :: Mangling uc_mcontext INVALID MODE EL1h
11428 00:24:44.176791 ok 13 selftests: arm64: mangle_pstate_invalid_mode_el1h
11429 00:24:44.183048 # selftests: arm64: mangle_pstate_invalid_mode_el1t
11430 00:24:44.223325 # Registered handlers for all signals.
11431 00:24:44.223458 # Detected MINSTKSIGSZ:4720
11432 00:24:44.226677 # Testcase initialized.
11433 00:24:44.230346 # uc context validated.
11434 00:24:44.230430 # Handled SIG_TRIG
11435 00:24:44.239940 # SIG_OK -- SP:0xFFFFFB618AC0 si_addr@:0xfffffb618ac0 si_code:2 token@:(nil) offset:-281474899217088
11436 00:24:44.243051 # ==>> completed. PASS(1)
11437 00:24:44.249824 # # MANGLE_PSTATE_INVALID_MODE_EL1t :: Mangling uc_mcontext INVALID MODE EL1t
11438 00:24:44.253055 ok 14 selftests: arm64: mangle_pstate_invalid_mode_el1t
11439 00:24:44.259490 # selftests: arm64: mangle_pstate_invalid_mode_el2h
11440 00:24:44.300024 # Registered handlers for all signals.
11441 00:24:44.300151 # Detected MINSTKSIGSZ:4720
11442 00:24:44.303344 # Testcase initialized.
11443 00:24:44.306774 # uc context validated.
11444 00:24:44.306857 # Handled SIG_TRIG
11445 00:24:44.316819 # SIG_OK -- SP:0xFFFFE2C48900 si_addr@:0xffffe2c48900 si_code:2 token@:(nil) offset:-281474486274304
11446 00:24:44.319932 # ==>> completed. PASS(1)
11447 00:24:44.326381 # # MANGLE_PSTATE_INVALID_MODE_EL2h :: Mangling uc_mcontext INVALID MODE EL2h
11448 00:24:44.329819 ok 15 selftests: arm64: mangle_pstate_invalid_mode_el2h
11449 00:24:44.336596 # selftests: arm64: mangle_pstate_invalid_mode_el2t
11450 00:24:44.392403 # Registered handlers for all signals.
11451 00:24:44.392537 # Detected MINSTKSIGSZ:4720
11452 00:24:44.395621 # Testcase initialized.
11453 00:24:44.399175 # uc context validated.
11454 00:24:44.399259 # Handled SIG_TRIG
11455 00:24:44.408784 # SIG_OK -- SP:0xFFFFDE0FBCA0 si_addr@:0xffffde0fbca0 si_code:2 token@:(nil) offset:-281474407316640
11456 00:24:44.412202 # ==>> completed. PASS(1)
11457 00:24:44.418593 # # MANGLE_PSTATE_INVALID_MODE_EL2t :: Mangling uc_mcontext INVALID MODE EL2t
11458 00:24:44.422418 ok 16 selftests: arm64: mangle_pstate_invalid_mode_el2t
11459 00:24:44.428329 # selftests: arm64: mangle_pstate_invalid_mode_el3h
11460 00:24:44.486243 # Registered handlers for all signals.
11461 00:24:44.486388 # Detected MINSTKSIGSZ:4720
11462 00:24:44.489828 # Testcase initialized.
11463 00:24:44.493378 # uc context validated.
11464 00:24:44.493481 # Handled SIG_TRIG
11465 00:24:44.502829 # SIG_OK -- SP:0xFFFFF4A06F10 si_addr@:0xfffff4a06f10 si_code:2 token@:(nil) offset:-281474785898256
11466 00:24:44.506065 # ==>> completed. PASS(1)
11467 00:24:44.512826 # # MANGLE_PSTATE_INVALID_MODE_EL3h :: Mangling uc_mcontext INVALID MODE EL3h
11468 00:24:44.516211 ok 17 selftests: arm64: mangle_pstate_invalid_mode_el3h
11469 00:24:44.523071 # selftests: arm64: mangle_pstate_invalid_mode_el3t
11470 00:24:44.565974 # Registered handlers for all signals.
11471 00:24:44.566117 # Detected MINSTKSIGSZ:4720
11472 00:24:44.569252 # Testcase initialized.
11473 00:24:44.572533 # uc context validated.
11474 00:24:44.572616 # Handled SIG_TRIG
11475 00:24:44.582144 # SIG_OK -- SP:0xFFFFE6F138B0 si_addr@:0xffffe6f138b0 si_code:2 token@:(nil) offset:-281474556311728
11476 00:24:44.585567 # ==>> completed. PASS(1)
11477 00:24:44.592322 # # MANGLE_PSTATE_INVALID_MODE_EL3t :: Mangling uc_mcontext INVALID MODE EL3t
11478 00:24:44.595484 ok 18 selftests: arm64: mangle_pstate_invalid_mode_el3t
11479 00:24:44.598821 # selftests: arm64: sme_trap_no_sm
11480 00:24:44.643707 # Registered handlers for all signals.
11481 00:24:44.643839 # Detected MINSTKSIGSZ:4720
11482 00:24:44.647190 # ==>> completed. SKIP.
11483 00:24:44.656984 # # SME trap without SM :: Check that we get a SIGILL if we use streaming mode without enabling it
11484 00:24:44.660240 ok 19 selftests: arm64: sme_trap_no_sm # SKIP
11485 00:24:44.666677 # selftests: arm64: sme_trap_non_streaming
11486 00:24:44.733590 # Registered handlers for all signals.
11487 00:24:44.733757 # Detected MINSTKSIGSZ:4720
11488 00:24:44.736935 # ==>> completed. SKIP.
11489 00:24:44.746988 # # SME SM trap unsupported instruction :: Check that we get a SIGILL if we use an unsupported instruction in streaming mode
11490 00:24:44.753131 ok 20 selftests: arm64: sme_trap_non_streaming # SKIP
11491 00:24:44.756332 # selftests: arm64: sme_trap_za
11492 00:24:44.806780 # Registered handlers for all signals.
11493 00:24:44.806907 # Detected MINSTKSIGSZ:4720
11494 00:24:44.809987 # Testcase initialized.
11495 00:24:44.819909 # SIG_OK -- SP:0xFFFFC5B134A0 si_addr@:0xaaaae92a2510 si_code:1 token@:(nil) offset:-187651033015568
11496 00:24:44.820023 # ==>> completed. PASS(1)
11497 00:24:44.829650 # # SME ZA trap :: Check that we get a SIGILL if we access ZA without enabling
11498 00:24:44.833214 ok 21 selftests: arm64: sme_trap_za
11499 00:24:44.833327 # selftests: arm64: sme_vl
11500 00:24:44.886595 # Registered handlers for all signals.
11501 00:24:44.886714 # Detected MINSTKSIGSZ:4720
11502 00:24:44.890423 # ==>> completed. SKIP.
11503 00:24:44.896648 # # SME VL :: Check that we get the right SME VL reported
11504 00:24:44.899916 ok 22 selftests: arm64: sme_vl # SKIP
11505 00:24:44.903168 # selftests: arm64: ssve_regs
11506 00:24:44.974459 # Registered handlers for all signals.
11507 00:24:44.974586 # Detected MINSTKSIGSZ:4720
11508 00:24:44.977370 # ==>> completed. SKIP.
11509 00:24:44.983909 # # Streaming SVE registers :: Check that we get the right Streaming SVE registers reported
11510 00:24:44.990593 ok 23 selftests: arm64: ssve_regs # SKIP
11511 00:24:44.993996 # selftests: arm64: sve_regs
11512 00:24:45.062670 # Registered handlers for all signals.
11513 00:24:45.062794 # Detected MINSTKSIGSZ:4720
11514 00:24:45.065620 # ==>> completed. SKIP.
11515 00:24:45.072059 # # SVE registers :: Check that we get the right SVE registers reported
11516 00:24:45.075406 ok 24 selftests: arm64: sve_regs # SKIP
11517 00:24:45.084095 # selftests: arm64: sve_vl
11518 00:24:45.156138 # Registered handlers for all signals.
11519 00:24:45.156273 # Detected MINSTKSIGSZ:4720
11520 00:24:45.159360 # ==>> completed. SKIP.
11521 00:24:45.166079 # # SVE VL :: Check that we get the right SVE VL reported
11522 00:24:45.169475 ok 25 selftests: arm64: sve_vl # SKIP
11523 00:24:45.173251 # selftests: arm64: za_no_regs
11524 00:24:45.236879 # Registered handlers for all signals.
11525 00:24:45.236984 # Detected MINSTKSIGSZ:4720
11526 00:24:45.239955 # ==>> completed. SKIP.
11527 00:24:45.247006 # # ZA registers - ZA disabled :: Check ZA context with ZA disabled
11528 00:24:45.249977 ok 26 selftests: arm64: za_no_regs # SKIP
11529 00:24:45.255396 # selftests: arm64: za_regs
11530 00:24:45.321940 # Registered handlers for all signals.
11531 00:24:45.322070 # Detected MINSTKSIGSZ:4720
11532 00:24:45.325187 # ==>> completed. SKIP.
11533 00:24:45.331725 # # ZA register :: Check that we get the right ZA registers reported
11534 00:24:45.334995 ok 27 selftests: arm64: za_regs # SKIP
11535 00:24:45.340191 # selftests: arm64: pac
11536 00:24:45.408785 # TAP version 13
11537 00:24:45.408889 # 1..7
11538 00:24:45.412390 # # Starting 7 tests from 1 test cases.
11539 00:24:45.415433 # # RUN global.corrupt_pac ...
11540 00:24:45.418268 # # SKIP PAUTH not enabled
11541 00:24:45.421725 # # OK global.corrupt_pac
11542 00:24:45.425109 # ok 1 # SKIP PAUTH not enabled
11543 00:24:45.431513 # # RUN global.pac_instructions_not_nop ...
11544 00:24:45.435152 # # SKIP PAUTH not enabled
11545 00:24:45.438028 # # OK global.pac_instructions_not_nop
11546 00:24:45.441453 # ok 2 # SKIP PAUTH not enabled
11547 00:24:45.447946 # # RUN global.pac_instructions_not_nop_generic ...
11548 00:24:45.451528 # # SKIP Generic PAUTH not enabled
11549 00:24:45.454957 # # OK global.pac_instructions_not_nop_generic
11550 00:24:45.461182 # ok 3 # SKIP Generic PAUTH not enabled
11551 00:24:45.464976 # # RUN global.single_thread_different_keys ...
11552 00:24:45.468106 # # SKIP PAUTH not enabled
11553 00:24:45.474711 # # OK global.single_thread_different_keys
11554 00:24:45.474795 # ok 4 # SKIP PAUTH not enabled
11555 00:24:45.481052 # # RUN global.exec_changed_keys ...
11556 00:24:45.484433 # # SKIP PAUTH not enabled
11557 00:24:45.487612 # # OK global.exec_changed_keys
11558 00:24:45.490867 # ok 5 # SKIP PAUTH not enabled
11559 00:24:45.494224 # # RUN global.context_switch_keep_keys ...
11560 00:24:45.497498 # # SKIP PAUTH not enabled
11561 00:24:45.504383 # # OK global.context_switch_keep_keys
11562 00:24:45.507881 # ok 6 # SKIP PAUTH not enabled
11563 00:24:45.510651 # # RUN global.context_switch_keep_keys_generic ...
11564 00:24:45.513881 # # SKIP Generic PAUTH not enabled
11565 00:24:45.520994 # # OK global.context_switch_keep_keys_generic
11566 00:24:45.524016 # ok 7 # SKIP Generic PAUTH not enabled
11567 00:24:45.527329 # # PASSED: 7 / 7 tests passed.
11568 00:24:45.530456 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:7 error:0
11569 00:24:45.534054 ok 28 selftests: arm64: pac
11570 00:24:45.537058 # selftests: arm64: fp-stress
11571 00:24:53.353105 <6>[ 37.976655] vpu: disabling
11572 00:24:53.357428 <6>[ 37.980920] vproc2: disabling
11573 00:24:53.360700 <6>[ 37.984182] vproc1: disabling
11574 00:24:53.364219 <6>[ 37.987456] vaud18: disabling
11575 00:24:53.370820 <6>[ 37.990890] vsram_others: disabling
11576 00:24:53.374106 <6>[ 37.994780] va09: disabling
11577 00:24:53.377326 <6>[ 37.997894] vsram_md: disabling
11578 00:24:53.380948 <6>[ 38.001406] Vgpu: disabling
11579 00:24:55.483600 # TAP version 13
11580 00:24:55.483792 # 1..16
11581 00:24:55.486491 # # 8 CPUs, 0 SVE VLs, 0 SME VLs
11582 00:24:55.490416 # # Will run for 10s
11583 00:24:55.490528 # # Started FPSIMD-0-0
11584 00:24:55.493469 # # Started FPSIMD-0-1
11585 00:24:55.496449 # # Started FPSIMD-1-0
11586 00:24:55.496561 # # Started FPSIMD-1-1
11587 00:24:55.499734 # # Started FPSIMD-2-0
11588 00:24:55.502975 # # Started FPSIMD-2-1
11589 00:24:55.503088 # # Started FPSIMD-3-0
11590 00:24:55.506549 # # Started FPSIMD-3-1
11591 00:24:55.506660 # # Started FPSIMD-4-0
11592 00:24:55.509508 # # Started FPSIMD-4-1
11593 00:24:55.513084 # # Started FPSIMD-5-0
11594 00:24:55.513196 # # Started FPSIMD-5-1
11595 00:24:55.516411 # # Started FPSIMD-6-0
11596 00:24:55.519547 # # Started FPSIMD-6-1
11597 00:24:55.519659 # # Started FPSIMD-7-0
11598 00:24:55.522898 # # Started FPSIMD-7-1
11599 00:24:55.526396 # # FPSIMD-0-0: Vector length: 128 bits
11600 00:24:55.529359 # # FPSIMD-0-0: PID: 1169
11601 00:24:55.532687 # # FPSIMD-2-1: Vector length: 128 bits
11602 00:24:55.532798 # # FPSIMD-2-1: PID: 1174
11603 00:24:55.539647 # # FPSIMD-1-1: Vector length: 128 bits
11604 00:24:55.539761 # # FPSIMD-1-1: PID: 1172
11605 00:24:55.542535 # # FPSIMD-1-0: Vector length: 128 bits
11606 00:24:55.546009 # # FPSIMD-1-0: PID: 1171
11607 00:24:55.549394 # # FPSIMD-0-1: Vector length: 128 bits
11608 00:24:55.552618 # # FPSIMD-0-1: PID: 1170
11609 00:24:55.555746 # # FPSIMD-7-1: Vector length: 128 bits
11610 00:24:55.559679 # # FPSIMD-7-1: PID: 1184
11611 00:24:55.562943 # # FPSIMD-6-1: Vector length: 128 bits
11612 00:24:55.563055 # # FPSIMD-6-1: PID: 1182
11613 00:24:55.565648 # # FPSIMD-2-0: Vector length: 128 bits
11614 00:24:55.569235 # # FPSIMD-2-0: PID: 1173
11615 00:24:55.572449 # # FPSIMD-3-0: Vector length: 128 bits
11616 00:24:55.575662 # # FPSIMD-3-0: PID: 1175
11617 00:24:55.579071 # # FPSIMD-4-0: Vector length: 128 bits
11618 00:24:55.582637 # # FPSIMD-4-0: PID: 1177
11619 00:24:55.585637 # # FPSIMD-5-1: Vector length: 128 bits
11620 00:24:55.588747 # # FPSIMD-5-1: PID: 1180
11621 00:24:55.591992 # # FPSIMD-7-0: Vector length: 128 bits
11622 00:24:55.592111 # # FPSIMD-7-0: PID: 1183
11623 00:24:55.595291 # # FPSIMD-3-1: Vector length: 128 bits
11624 00:24:55.598855 # # FPSIMD-3-1: PID: 1176
11625 00:24:55.601867 # # FPSIMD-4-1: Vector length: 128 bits
11626 00:24:55.605619 # # FPSIMD-4-1: PID: 1178
11627 00:24:55.608831 # # FPSIMD-6-0: Vector length: 128 bits
11628 00:24:55.612043 # # FPSIMD-6-0: PID: 1181
11629 00:24:55.615295 # # FPSIMD-5-0: Vector length: 128 bits
11630 00:24:55.618503 # # FPSIMD-5-0: PID: 1179
11631 00:24:55.618618 # # Finishing up...
11632 00:24:55.625188 # # FPSIMD-1-0: Terminated by signal 15, no error, iterations=941846, signals=10
11633 00:24:55.632134 # # FPSIMD-3-1: Terminated by signal 15, no error, iterations=951818, signals=10
11634 00:24:55.641537 # # FPSIMD-1-1: Terminated by signal 15, no error, iterations=1574615, signals=10
11635 00:24:55.648152 # # FPSIMD-4-0: Terminated by signal 15, no error, iterations=1613387, signals=10
11636 00:24:55.654703 # # FPSIMD-4-1: Terminated by signal 15, no error, iterations=1125070, signals=10
11637 00:24:55.661849 # # FPSIMD-5-1: Terminated by signal 15, no error, iterations=1236827, signals=10
11638 00:24:55.668384 # # FPSIMD-2-1: Terminated by signal 15, no error, iterations=1600995, signals=10
11639 00:24:55.671409 # ok 1 FPSIMD-0-0
11640 00:24:55.671522 # ok 2 FPSIMD-0-1
11641 00:24:55.674777 # ok 3 FPSIMD-1-0
11642 00:24:55.674886 # ok 4 FPSIMD-1-1
11643 00:24:55.678119 # ok 5 FPSIMD-2-0
11644 00:24:55.678267 # ok 6 FPSIMD-2-1
11645 00:24:55.680998 # ok 7 FPSIMD-3-0
11646 00:24:55.681107 # ok 8 FPSIMD-3-1
11647 00:24:55.684514 # ok 9 FPSIMD-4-0
11648 00:24:55.684616 # ok 10 FPSIMD-4-1
11649 00:24:55.688008 # ok 11 FPSIMD-5-0
11650 00:24:55.688118 # ok 12 FPSIMD-5-1
11651 00:24:55.691242 # ok 13 FPSIMD-6-0
11652 00:24:55.691350 # ok 14 FPSIMD-6-1
11653 00:24:55.694574 # ok 15 FPSIMD-7-0
11654 00:24:55.694683 # ok 16 FPSIMD-7-1
11655 00:24:55.704196 # # FPSIMD-0-1: Terminated by signal 15, no error, iterations=1077684, signals=9
11656 00:24:55.710962 # # FPSIMD-7-0: Terminated by signal 15, no error, iterations=1158110, signals=10
11657 00:24:55.717657 # # FPSIMD-6-1: Terminated by signal 15, no error, iterations=1095631, signals=10
11658 00:24:55.724111 # # FPSIMD-3-0: Terminated by signal 15, no error, iterations=900172, signals=10
11659 00:24:55.730820 # # FPSIMD-6-0: Terminated by signal 15, no error, iterations=2047098, signals=10
11660 00:24:55.740654 # # FPSIMD-2-0: Terminated by signal 15, no error, iterations=1065734, signals=10
11661 00:24:55.746937 # # FPSIMD-0-0: Terminated by signal 15, no error, iterations=950777, signals=9
11662 00:24:55.753703 # # FPSIMD-7-1: Terminated by signal 15, no error, iterations=875150, signals=10
11663 00:24:55.760183 # # FPSIMD-5-0: Terminated by signal 15, no error, iterations=963454, signals=10
11664 00:24:55.766985 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:0 error:0
11665 00:24:55.767104 ok 29 selftests: arm64: fp-stress
11666 00:24:55.770125 # selftests: arm64: sve-ptrace
11667 00:24:55.773874 # TAP version 13
11668 00:24:55.773985 # 1..4104
11669 00:24:55.777106 # ok 2 # SKIP SVE not available
11670 00:24:55.779997 # # Planned tests != run tests (4104 != 1)
11671 00:24:55.786522 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11672 00:24:55.790044 ok 30 selftests: arm64: sve-ptrace # SKIP
11673 00:24:55.793459 # selftests: arm64: sve-probe-vls
11674 00:24:55.793567 # TAP version 13
11675 00:24:55.793662 # 1..2
11676 00:24:55.796405 # ok 2 # SKIP SVE not available
11677 00:24:55.799742 # # Planned tests != run tests (2 != 1)
11678 00:24:55.806596 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11679 00:24:55.809850 ok 31 selftests: arm64: sve-probe-vls # SKIP
11680 00:24:55.813122 # selftests: arm64: vec-syscfg
11681 00:24:55.813234 # TAP version 13
11682 00:24:55.816442 # 1..20
11683 00:24:55.816551 # ok 1 # SKIP SVE not supported
11684 00:24:55.819935 # ok 2 # SKIP SVE not supported
11685 00:24:55.822968 # ok 3 # SKIP SVE not supported
11686 00:24:55.826462 # ok 4 # SKIP SVE not supported
11687 00:24:55.829957 # ok 5 # SKIP SVE not supported
11688 00:24:55.832829 # ok 6 # SKIP SVE not supported
11689 00:24:55.835958 # ok 7 # SKIP SVE not supported
11690 00:24:55.839611 # ok 8 # SKIP SVE not supported
11691 00:24:55.839719 # ok 9 # SKIP SVE not supported
11692 00:24:55.842673 # ok 10 # SKIP SVE not supported
11693 00:24:55.845872 # ok 11 # SKIP SME not supported
11694 00:24:55.849154 # ok 12 # SKIP SME not supported
11695 00:24:55.852646 # ok 13 # SKIP SME not supported
11696 00:24:55.855696 # ok 14 # SKIP SME not supported
11697 00:24:55.859066 # ok 15 # SKIP SME not supported
11698 00:24:55.862987 # ok 16 # SKIP SME not supported
11699 00:24:55.866029 # ok 17 # SKIP SME not supported
11700 00:24:55.866137 # ok 18 # SKIP SME not supported
11701 00:24:55.869125 # ok 19 # SKIP SME not supported
11702 00:24:55.872452 # ok 20 # SKIP SME not supported
11703 00:24:55.879046 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:20 error:0
11704 00:24:55.882228 ok 32 selftests: arm64: vec-syscfg
11705 00:24:55.885606 # selftests: arm64: za-fork
11706 00:24:55.885714 # TAP version 13
11707 00:24:55.885809 # 1..1
11708 00:24:55.889207 # # PID: 1261
11709 00:24:55.889316 # # SME support not present
11710 00:24:55.892123 # ok 0 skipped
11711 00:24:55.895225 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11712 00:24:55.898886 ok 33 selftests: arm64: za-fork
11713 00:24:55.902448 # selftests: arm64: za-ptrace
11714 00:24:55.936274 # TAP version 13
11715 00:24:55.936397 # 1..1
11716 00:24:55.939755 # ok 2 # SKIP SME not available
11717 00:24:55.945998 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11718 00:24:55.949200 ok 34 selftests: arm64: za-ptrace # SKIP
11719 00:24:55.960664 # selftests: arm64: check_buffer_fill
11720 00:24:56.037266 # # SKIP: MTE features unavailable
11721 00:24:56.046792 ok 35 selftests: arm64: check_buffer_fill # SKIP
11722 00:24:56.062602 # selftests: arm64: check_child_memory
11723 00:24:56.123873 # # SKIP: MTE features unavailable
11724 00:24:56.132016 ok 36 selftests: arm64: check_child_memory # SKIP
11725 00:24:56.148875 # selftests: arm64: check_gcr_el1_cswitch
11726 00:24:56.208056 # # SKIP: MTE features unavailable
11727 00:24:56.215464 ok 37 selftests: arm64: check_gcr_el1_cswitch # SKIP
11728 00:24:56.233135 # selftests: arm64: check_ksm_options
11729 00:24:56.295841 # # SKIP: MTE features unavailable
11730 00:24:56.304360 ok 38 selftests: arm64: check_ksm_options # SKIP
11731 00:24:56.323178 # selftests: arm64: check_mmap_options
11732 00:24:56.397066 # # SKIP: MTE features unavailable
11733 00:24:56.404787 ok 39 selftests: arm64: check_mmap_options # SKIP
11734 00:24:56.420624 # selftests: arm64: check_prctl
11735 00:24:56.482728 # TAP version 13
11736 00:24:56.482838 # 1..5
11737 00:24:56.485582 # ok 1 check_basic_read
11738 00:24:56.485665 # ok 2 NONE
11739 00:24:56.488997 # ok 3 # SKIP SYNC
11740 00:24:56.489080 # ok 4 # SKIP ASYNC
11741 00:24:56.492624 # ok 5 # SKIP SYNC+ASYNC
11742 00:24:56.495545 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:3 error:0
11743 00:24:56.498683 ok 40 selftests: arm64: check_prctl
11744 00:24:56.508235 # selftests: arm64: check_tags_inclusion
11745 00:24:56.577783 # # SKIP: MTE features unavailable
11746 00:24:56.585279 ok 41 selftests: arm64: check_tags_inclusion # SKIP
11747 00:24:56.599469 # selftests: arm64: check_user_mem
11748 00:24:56.661991 # # SKIP: MTE features unavailable
11749 00:24:56.669258 ok 42 selftests: arm64: check_user_mem # SKIP
11750 00:24:56.684873 # selftests: arm64: btitest
11751 00:24:56.756673 # TAP version 13
11752 00:24:56.756822 # 1..18
11753 00:24:56.760137 # # HWCAP_PACA not present
11754 00:24:56.763190 # # HWCAP2_BTI not present
11755 00:24:56.763300 # # Test binary built for BTI
11756 00:24:56.769714 # ok 1 nohint_func/call_using_br_x0 # SKIP
11757 00:24:56.773405 # ok 1 nohint_func/call_using_br_x16 # SKIP
11758 00:24:56.776559 # ok 1 nohint_func/call_using_blr # SKIP
11759 00:24:56.779871 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11760 00:24:56.782940 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11761 00:24:56.789928 # ok 1 bti_none_func/call_using_blr # SKIP
11762 00:24:56.793051 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11763 00:24:56.795966 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11764 00:24:56.799358 # ok 1 bti_c_func/call_using_blr # SKIP
11765 00:24:56.802897 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11766 00:24:56.806089 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11767 00:24:56.809535 # ok 1 bti_j_func/call_using_blr # SKIP
11768 00:24:56.812378 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11769 00:24:56.819091 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11770 00:24:56.822344 # ok 1 bti_jc_func/call_using_blr # SKIP
11771 00:24:56.825969 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11772 00:24:56.829344 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11773 00:24:56.832182 # ok 1 paciasp_func/call_using_blr # SKIP
11774 00:24:56.839090 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11775 00:24:56.842086 # # WARNING - EXPECTED TEST COUNT WRONG
11776 00:24:56.845160 ok 43 selftests: arm64: btitest
11777 00:24:56.848708 # selftests: arm64: nobtitest
11778 00:24:56.864233 # TAP version 13
11779 00:24:56.864315 # 1..18
11780 00:24:56.867683 # # HWCAP_PACA not present
11781 00:24:56.870670 # # HWCAP2_BTI not present
11782 00:24:56.874176 # # Test binary not built for BTI
11783 00:24:56.877629 # ok 1 nohint_func/call_using_br_x0 # SKIP
11784 00:24:56.880656 # ok 1 nohint_func/call_using_br_x16 # SKIP
11785 00:24:56.884159 # ok 1 nohint_func/call_using_blr # SKIP
11786 00:24:56.887581 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11787 00:24:56.890891 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11788 00:24:56.897273 # ok 1 bti_none_func/call_using_blr # SKIP
11789 00:24:56.900490 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11790 00:24:56.903846 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11791 00:24:56.906833 # ok 1 bti_c_func/call_using_blr # SKIP
11792 00:24:56.910301 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11793 00:24:56.913778 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11794 00:24:56.916956 # ok 1 bti_j_func/call_using_blr # SKIP
11795 00:24:56.923919 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11796 00:24:56.926948 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11797 00:24:56.930347 # ok 1 bti_jc_func/call_using_blr # SKIP
11798 00:24:56.933261 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11799 00:24:56.936776 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11800 00:24:56.940317 # ok 1 paciasp_func/call_using_blr # SKIP
11801 00:24:56.946483 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11802 00:24:56.950410 # # WARNING - EXPECTED TEST COUNT WRONG
11803 00:24:56.953032 ok 44 selftests: arm64: nobtitest
11804 00:24:56.956703 # selftests: arm64: hwcap
11805 00:24:56.967563 # TAP version 13
11806 00:24:56.967646 # 1..28
11807 00:24:56.970823 # ok 1 cpuinfo_match_RNG
11808 00:24:56.973893 # # SIGILL reported for RNG
11809 00:24:56.973974 # ok 2 # SKIP sigill_RNG
11810 00:24:56.977324 # ok 3 cpuinfo_match_SME
11811 00:24:56.980638 # ok 4 sigill_SME
11812 00:24:56.980719 # ok 5 cpuinfo_match_SVE
11813 00:24:56.983829 # ok 6 sigill_SVE
11814 00:24:56.983911 # ok 7 cpuinfo_match_SVE 2
11815 00:24:56.987144 # # SIGILL reported for SVE 2
11816 00:24:56.990724 # ok 8 # SKIP sigill_SVE 2
11817 00:24:56.994096 # ok 9 cpuinfo_match_SVE AES
11818 00:24:56.997090 # # SIGILL reported for SVE AES
11819 00:24:57.000457 # ok 10 # SKIP sigill_SVE AES
11820 00:24:57.000539 # ok 11 cpuinfo_match_SVE2 PMULL
11821 00:24:57.003440 # # SIGILL reported for SVE2 PMULL
11822 00:24:57.006875 # ok 12 # SKIP sigill_SVE2 PMULL
11823 00:24:57.010474 # ok 13 cpuinfo_match_SVE2 BITPERM
11824 00:24:57.013723 # # SIGILL reported for SVE2 BITPERM
11825 00:24:57.016671 # ok 14 # SKIP sigill_SVE2 BITPERM
11826 00:24:57.020089 # ok 15 cpuinfo_match_SVE2 SHA3
11827 00:24:57.023154 # # SIGILL reported for SVE2 SHA3
11828 00:24:57.027006 # ok 16 # SKIP sigill_SVE2 SHA3
11829 00:24:57.029823 # ok 17 cpuinfo_match_SVE2 SM4
11830 00:24:57.033456 # # SIGILL reported for SVE2 SM4
11831 00:24:57.033537 # ok 18 # SKIP sigill_SVE2 SM4
11832 00:24:57.036156 # ok 19 cpuinfo_match_SVE2 I8MM
11833 00:24:57.039656 # # SIGILL reported for SVE2 I8MM
11834 00:24:57.043078 # ok 20 # SKIP sigill_SVE2 I8MM
11835 00:24:57.046058 # ok 21 cpuinfo_match_SVE2 F32MM
11836 00:24:57.049479 # # SIGILL reported for SVE2 F32MM
11837 00:24:57.053115 # ok 22 # SKIP sigill_SVE2 F32MM
11838 00:24:57.056102 # ok 23 cpuinfo_match_SVE2 F64MM
11839 00:24:57.059547 # # SIGILL reported for SVE2 F64MM
11840 00:24:57.062652 # ok 24 # SKIP sigill_SVE2 F64MM
11841 00:24:57.062733 # ok 25 cpuinfo_match_SVE2 BF16
11842 00:24:57.066246 # # SIGILL reported for SVE2 BF16
11843 00:24:57.069286 # ok 26 # SKIP sigill_SVE2 BF16
11844 00:24:57.072474 # ok 27 cpuinfo_match_SVE2 EBF16
11845 00:24:57.076159 # ok 28 # SKIP sigill_SVE2 EBF16
11846 00:24:57.082575 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:12 error:0
11847 00:24:57.082657 ok 45 selftests: arm64: hwcap
11848 00:24:57.085618 # selftests: arm64: ptrace
11849 00:24:57.088921 # TAP version 13
11850 00:24:57.089003 # 1..7
11851 00:24:57.092468 # # Parent is 1503, child is 1504
11852 00:24:57.092588 # ok 1 read_tpidr_one
11853 00:24:57.095629 # ok 2 write_tpidr_one
11854 00:24:57.098853 # ok 3 verify_tpidr_one
11855 00:24:57.098935 # ok 4 count_tpidrs
11856 00:24:57.102377 # ok 5 tpidr2_write
11857 00:24:57.102458 # ok 6 tpidr2_read
11858 00:24:57.105487 # ok 7 write_tpidr_only
11859 00:24:57.111997 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
11860 00:24:57.112079 ok 46 selftests: arm64: ptrace
11861 00:24:57.115190 # selftests: arm64: syscall-abi
11862 00:24:57.141777 # TAP version 13
11863 00:24:57.141859 # 1..2
11864 00:24:57.144944 # ok 1 getpid() FPSIMD
11865 00:24:57.147973 # ok 2 sched_yield() FPSIMD
11866 00:24:57.151401 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:0 error:0
11867 00:24:57.154574 ok 47 selftests: arm64: syscall-abi
11868 00:24:57.160129 # selftests: arm64: tpidr2
11869 00:24:57.223058 # TAP version 13
11870 00:24:57.223153 # 1..5
11871 00:24:57.226377 # # PID: 1540
11872 00:24:57.226460 # # SME support not present
11873 00:24:57.229506 # ok 0 skipped, TPIDR2 not supported
11874 00:24:57.232734 # ok 1 skipped, TPIDR2 not supported
11875 00:24:57.235980 # ok 2 skipped, TPIDR2 not supported
11876 00:24:57.239463 # ok 3 skipped, TPIDR2 not supported
11877 00:24:57.242852 # ok 4 skipped, TPIDR2 not supported
11878 00:24:57.249591 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
11879 00:24:57.252504 ok 48 selftests: arm64: tpidr2
11880 00:24:58.770578 arm64_tags_test pass
11881 00:24:58.774079 arm64_run_tags_test_sh pass
11882 00:24:58.777074 arm64_fake_sigreturn_bad_magic pass
11883 00:24:58.780430 arm64_fake_sigreturn_bad_size pass
11884 00:24:58.784080 arm64_fake_sigreturn_bad_size_for_magic0 pass
11885 00:24:58.787072 arm64_fake_sigreturn_duplicated_fpsimd pass
11886 00:24:58.790467 arm64_fake_sigreturn_misaligned_sp pass
11887 00:24:58.793480 arm64_fake_sigreturn_missing_fpsimd pass
11888 00:24:58.797093 arm64_fake_sigreturn_sme_change_vl skip
11889 00:24:58.803451 arm64_fake_sigreturn_sve_change_vl skip
11890 00:24:58.806870 arm64_mangle_pstate_invalid_compat_toggle pass
11891 00:24:58.809969 arm64_mangle_pstate_invalid_daif_bits pass
11892 00:24:58.813539 arm64_mangle_pstate_invalid_mode_el1h pass
11893 00:24:58.816585 arm64_mangle_pstate_invalid_mode_el1t pass
11894 00:24:58.820430 arm64_mangle_pstate_invalid_mode_el2h pass
11895 00:24:58.826581 arm64_mangle_pstate_invalid_mode_el2t pass
11896 00:24:58.829948 arm64_mangle_pstate_invalid_mode_el3h pass
11897 00:24:58.833337 arm64_mangle_pstate_invalid_mode_el3t pass
11898 00:24:58.836346 arm64_sme_trap_no_sm skip
11899 00:24:58.839705 arm64_sme_trap_non_streaming skip
11900 00:24:58.839812 arm64_sme_trap_za pass
11901 00:24:58.843584 arm64_sme_vl skip
11902 00:24:58.843669 arm64_ssve_regs skip
11903 00:24:58.846928 arm64_sve_regs skip
11904 00:24:58.847010 arm64_sve_vl skip
11905 00:24:58.849949 arm64_za_no_regs skip
11906 00:24:58.853633 arm64_za_regs skip
11907 00:24:58.853716 arm64_pac_PAUTH_not_enabled skip
11908 00:24:58.856539 arm64_pac_PAUTH_not_enabled_dup2 skip
11909 00:24:58.863396 arm64_pac_Generic_PAUTH_not_enabled skip
11910 00:24:58.866349 arm64_pac_PAUTH_not_enabled_dup3 skip
11911 00:24:58.869588 arm64_pac_PAUTH_not_enabled_dup4 skip
11912 00:24:58.872811 arm64_pac_PAUTH_not_enabled_dup5 skip
11913 00:24:58.876242 arm64_pac_Generic_PAUTH_not_enabled_dup2 skip
11914 00:24:58.876325 arm64_pac pass
11915 00:24:58.879413 arm64_fp-stress_FPSIMD-0-0 pass
11916 00:24:58.883343 arm64_fp-stress_FPSIMD-0-1 pass
11917 00:24:58.886387 arm64_fp-stress_FPSIMD-1-0 pass
11918 00:24:58.889324 arm64_fp-stress_FPSIMD-1-1 pass
11919 00:24:58.892994 arm64_fp-stress_FPSIMD-2-0 pass
11920 00:24:58.893076 arm64_fp-stress_FPSIMD-2-1 pass
11921 00:24:58.896032 arm64_fp-stress_FPSIMD-3-0 pass
11922 00:24:58.899523 arm64_fp-stress_FPSIMD-3-1 pass
11923 00:24:58.902965 arm64_fp-stress_FPSIMD-4-0 pass
11924 00:24:58.906027 arm64_fp-stress_FPSIMD-4-1 pass
11925 00:24:58.909066 arm64_fp-stress_FPSIMD-5-0 pass
11926 00:24:58.912355 arm64_fp-stress_FPSIMD-5-1 pass
11927 00:24:58.915822 arm64_fp-stress_FPSIMD-6-0 pass
11928 00:24:58.915904 arm64_fp-stress_FPSIMD-6-1 pass
11929 00:24:58.919087 arm64_fp-stress_FPSIMD-7-0 pass
11930 00:24:58.922623 arm64_fp-stress_FPSIMD-7-1 pass
11931 00:24:58.925762 arm64_fp-stress pass
11932 00:24:58.929432 arm64_sve-ptrace_SVE_not_available skip
11933 00:24:58.929515 arm64_sve-ptrace skip
11934 00:24:58.935809 arm64_sve-probe-vls_SVE_not_available skip
11935 00:24:58.935893 arm64_sve-probe-vls skip
11936 00:24:58.939161 arm64_vec-syscfg_SVE_not_supported skip
11937 00:24:58.945504 arm64_vec-syscfg_SVE_not_supported_dup2 skip
11938 00:24:58.948820 arm64_vec-syscfg_SVE_not_supported_dup3 skip
11939 00:24:58.951936 arm64_vec-syscfg_SVE_not_supported_dup4 skip
11940 00:24:58.955689 arm64_vec-syscfg_SVE_not_supported_dup5 skip
11941 00:24:58.958682 arm64_vec-syscfg_SVE_not_supported_dup6 skip
11942 00:24:58.965339 arm64_vec-syscfg_SVE_not_supported_dup7 skip
11943 00:24:58.968730 arm64_vec-syscfg_SVE_not_supported_dup8 skip
11944 00:24:58.971972 arm64_vec-syscfg_SVE_not_supported_dup9 skip
11945 00:24:58.975237 arm64_vec-syscfg_SVE_not_supported_dup10 skip
11946 00:24:58.978657 arm64_vec-syscfg_SME_not_supported skip
11947 00:24:58.985405 arm64_vec-syscfg_SME_not_supported_dup2 skip
11948 00:24:58.988762 arm64_vec-syscfg_SME_not_supported_dup3 skip
11949 00:24:58.992120 arm64_vec-syscfg_SME_not_supported_dup4 skip
11950 00:24:58.994972 arm64_vec-syscfg_SME_not_supported_dup5 skip
11951 00:24:58.998143 arm64_vec-syscfg_SME_not_supported_dup6 skip
11952 00:24:59.004977 arm64_vec-syscfg_SME_not_supported_dup7 skip
11953 00:24:59.007960 arm64_vec-syscfg_SME_not_supported_dup8 skip
11954 00:24:59.011572 arm64_vec-syscfg_SME_not_supported_dup9 skip
11955 00:24:59.014946 arm64_vec-syscfg_SME_not_supported_dup10 skip
11956 00:24:59.018015 arm64_vec-syscfg pass
11957 00:24:59.021653 arm64_za-fork_skipped pass
11958 00:24:59.021734 arm64_za-fork pass
11959 00:24:59.024527 arm64_za-ptrace_SME_not_available skip
11960 00:24:59.027884 arm64_za-ptrace skip
11961 00:24:59.031575 arm64_check_buffer_fill skip
11962 00:24:59.031657 arm64_check_child_memory skip
11963 00:24:59.034471 arm64_check_gcr_el1_cswitch skip
11964 00:24:59.037901 arm64_check_ksm_options skip
11965 00:24:59.041024 arm64_check_mmap_options skip
11966 00:24:59.044609 arm64_check_prctl_check_basic_read pass
11967 00:24:59.048068 arm64_check_prctl_NONE pass
11968 00:24:59.048151 arm64_check_prctl_SYNC skip
11969 00:24:59.050746 arm64_check_prctl_ASYNC skip
11970 00:24:59.054424 arm64_check_prctl_SYNC_ASYNC skip
11971 00:24:59.057888 arm64_check_prctl pass
11972 00:24:59.060943 arm64_check_tags_inclusion skip
11973 00:24:59.061029 arm64_check_user_mem skip
11974 00:24:59.067792 arm64_btitest_nohint_func_call_using_br_x0 skip
11975 00:24:59.070776 arm64_btitest_nohint_func_call_using_br_x16 skip
11976 00:24:59.074437 arm64_btitest_nohint_func_call_using_blr skip
11977 00:24:59.080854 arm64_btitest_bti_none_func_call_using_br_x0 skip
11978 00:24:59.084144 arm64_btitest_bti_none_func_call_using_br_x16 skip
11979 00:24:59.087204 arm64_btitest_bti_none_func_call_using_blr skip
11980 00:24:59.094214 arm64_btitest_bti_c_func_call_using_br_x0 skip
11981 00:24:59.097092 arm64_btitest_bti_c_func_call_using_br_x16 skip
11982 00:24:59.100653 arm64_btitest_bti_c_func_call_using_blr skip
11983 00:24:59.103934 arm64_btitest_bti_j_func_call_using_br_x0 skip
11984 00:24:59.110298 arm64_btitest_bti_j_func_call_using_br_x16 skip
11985 00:24:59.113790 arm64_btitest_bti_j_func_call_using_blr skip
11986 00:24:59.116736 arm64_btitest_bti_jc_func_call_using_br_x0 skip
11987 00:24:59.120156 arm64_btitest_bti_jc_func_call_using_br_x16 skip
11988 00:24:59.126946 arm64_btitest_bti_jc_func_call_using_blr skip
11989 00:24:59.130344 arm64_btitest_paciasp_func_call_using_br_x0 skip
11990 00:24:59.133659 arm64_btitest_paciasp_func_call_using_br_x16 skip
11991 00:24:59.140596 arm64_btitest_paciasp_func_call_using_blr skip
11992 00:24:59.140681 arm64_btitest pass
11993 00:24:59.143565 arm64_nobtitest_nohint_func_call_using_br_x0 skip
11994 00:24:59.149778 arm64_nobtitest_nohint_func_call_using_br_x16 skip
11995 00:24:59.153441 arm64_nobtitest_nohint_func_call_using_blr skip
11996 00:24:59.157030 arm64_nobtitest_bti_none_func_call_using_br_x0 skip
11997 00:24:59.163278 arm64_nobtitest_bti_none_func_call_using_br_x16 skip
11998 00:24:59.166547 arm64_nobtitest_bti_none_func_call_using_blr skip
11999 00:24:59.172849 arm64_nobtitest_bti_c_func_call_using_br_x0 skip
12000 00:24:59.176147 arm64_nobtitest_bti_c_func_call_using_br_x16 skip
12001 00:24:59.180076 arm64_nobtitest_bti_c_func_call_using_blr skip
12002 00:24:59.182934 arm64_nobtitest_bti_j_func_call_using_br_x0 skip
12003 00:24:59.189359 arm64_nobtitest_bti_j_func_call_using_br_x16 skip
12004 00:24:59.192795 arm64_nobtitest_bti_j_func_call_using_blr skip
12005 00:24:59.196408 arm64_nobtitest_bti_jc_func_call_using_br_x0 skip
12006 00:24:59.202871 arm64_nobtitest_bti_jc_func_call_using_br_x16 skip
12007 00:24:59.205923 arm64_nobtitest_bti_jc_func_call_using_blr skip
12008 00:24:59.209558 arm64_nobtitest_paciasp_func_call_using_br_x0 skip
12009 00:24:59.215930 arm64_nobtitest_paciasp_func_call_using_br_x16 skip
12010 00:24:59.219126 arm64_nobtitest_paciasp_func_call_using_blr skip
12011 00:24:59.222935 arm64_nobtitest pass
12012 00:24:59.225962 arm64_hwcap_cpuinfo_match_RNG pass
12013 00:24:59.226044 arm64_hwcap_sigill_RNG skip
12014 00:24:59.229299 arm64_hwcap_cpuinfo_match_SME pass
12015 00:24:59.232474 arm64_hwcap_sigill_SME pass
12016 00:24:59.235687 arm64_hwcap_cpuinfo_match_SVE pass
12017 00:24:59.238860 arm64_hwcap_sigill_SVE pass
12018 00:24:59.242306 arm64_hwcap_cpuinfo_match_SVE_2 pass
12019 00:24:59.245851 arm64_hwcap_sigill_SVE_2 skip
12020 00:24:59.248669 arm64_hwcap_cpuinfo_match_SVE_AES pass
12021 00:24:59.252554 arm64_hwcap_sigill_SVE_AES skip
12022 00:24:59.255319 arm64_hwcap_cpuinfo_match_SVE2_PMULL pass
12023 00:24:59.258737 arm64_hwcap_sigill_SVE2_PMULL skip
12024 00:24:59.262430 arm64_hwcap_cpuinfo_match_SVE2_BITPERM pass
12025 00:24:59.265261 arm64_hwcap_sigill_SVE2_BITPERM skip
12026 00:24:59.268421 arm64_hwcap_cpuinfo_match_SVE2_SHA3 pass
12027 00:24:59.272283 arm64_hwcap_sigill_SVE2_SHA3 skip
12028 00:24:59.275066 arm64_hwcap_cpuinfo_match_SVE2_SM4 pass
12029 00:24:59.278929 arm64_hwcap_sigill_SVE2_SM4 skip
12030 00:24:59.281832 arm64_hwcap_cpuinfo_match_SVE2_I8MM pass
12031 00:24:59.285114 arm64_hwcap_sigill_SVE2_I8MM skip
12032 00:24:59.288312 arm64_hwcap_cpuinfo_match_SVE2_F32MM pass
12033 00:24:59.291817 arm64_hwcap_sigill_SVE2_F32MM skip
12034 00:24:59.295546 arm64_hwcap_cpuinfo_match_SVE2_F64MM pass
12035 00:24:59.298367 arm64_hwcap_sigill_SVE2_F64MM skip
12036 00:24:59.301401 arm64_hwcap_cpuinfo_match_SVE2_BF16 pass
12037 00:24:59.305022 arm64_hwcap_sigill_SVE2_BF16 skip
12038 00:24:59.308641 arm64_hwcap_cpuinfo_match_SVE2_EBF16 pass
12039 00:24:59.312010 arm64_hwcap_sigill_SVE2_EBF16 skip
12040 00:24:59.314798 arm64_hwcap pass
12041 00:24:59.318184 arm64_ptrace_read_tpidr_one pass
12042 00:24:59.318284 arm64_ptrace_write_tpidr_one pass
12043 00:24:59.321156 arm64_ptrace_verify_tpidr_one pass
12044 00:24:59.325045 arm64_ptrace_count_tpidrs pass
12045 00:24:59.327994 arm64_ptrace_tpidr2_write pass
12046 00:24:59.331580 arm64_ptrace_tpidr2_read pass
12047 00:24:59.334654 arm64_ptrace_write_tpidr_only pass
12048 00:24:59.334736 arm64_ptrace pass
12049 00:24:59.338082 arm64_syscall-abi_getpid_FPSIMD pass
12050 00:24:59.341175 arm64_syscall-abi_sched_yield_FPSIMD pass
12051 00:24:59.344368 arm64_syscall-abi pass
12052 00:24:59.347672 arm64_tpidr2_skipped_TPIDR2_not_supported pass
12053 00:24:59.354341 arm64_tpidr2_skipped_TPIDR2_not_supported_dup2 pass
12054 00:24:59.357547 arm64_tpidr2_skipped_TPIDR2_not_supported_dup3 pass
12055 00:24:59.364921 arm64_tpidr2_skipped_TPIDR2_not_supported_dup4 pass
12056 00:24:59.367510 arm64_tpidr2_skipped_TPIDR2_not_supported_dup5 pass
12057 00:24:59.367872 arm64_tpidr2 pass
12058 00:24:59.374418 + ../../utils/send-to-lava.sh ./output/result.txt
12059 00:24:59.377343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-arm64 RESULT=pass>
12060 00:24:59.377780 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-arm64 RESULT=pass
12062 00:24:59.384118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tags_test RESULT=pass>
12063 00:24:59.384524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tags_test RESULT=pass
12065 00:24:59.390649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass>
12066 00:24:59.391052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass
12068 00:24:59.397470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass>
12069 00:24:59.397763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass
12071 00:24:59.417647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass>
12072 00:24:59.417921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass
12074 00:24:59.477057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass>
12075 00:24:59.477369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass
12077 00:24:59.536800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass>
12078 00:24:59.537090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass
12080 00:24:59.592244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass>
12081 00:24:59.592528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass
12083 00:24:59.646860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass>
12084 00:24:59.647130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass
12086 00:24:59.698349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip>
12087 00:24:59.698621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip
12089 00:24:59.754100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip>
12090 00:24:59.754472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip
12092 00:24:59.810524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass>
12093 00:24:59.810789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass
12095 00:24:59.866940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass>
12096 00:24:59.867222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass
12098 00:24:59.925743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass>
12099 00:24:59.926008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass
12101 00:24:59.986015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass>
12102 00:24:59.986301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass
12104 00:25:00.042960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass>
12105 00:25:00.043230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass
12107 00:25:00.104626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass>
12108 00:25:00.104927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass
12110 00:25:00.161680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass>
12111 00:25:00.161954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass
12113 00:25:00.222000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass>
12114 00:25:00.222275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass
12116 00:25:00.277336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip>
12117 00:25:00.277614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip
12119 00:25:00.340627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip
12121 00:25:00.343837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip>
12122 00:25:00.396419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_za RESULT=pass>
12123 00:25:00.396699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_za RESULT=pass
12125 00:25:00.460686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_vl RESULT=skip>
12126 00:25:00.460966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_vl RESULT=skip
12128 00:25:00.519680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ssve_regs RESULT=skip>
12129 00:25:00.520109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ssve_regs RESULT=skip
12131 00:25:00.578743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_regs RESULT=skip>
12132 00:25:00.579042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_regs RESULT=skip
12134 00:25:00.640235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_vl RESULT=skip>
12135 00:25:00.640532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_vl RESULT=skip
12137 00:25:00.700640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_no_regs RESULT=skip>
12138 00:25:00.700921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_no_regs RESULT=skip
12140 00:25:00.760061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_regs RESULT=skip>
12141 00:25:00.760343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_regs RESULT=skip
12143 00:25:00.811580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
12145 00:25:00.814787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
12146 00:25:00.870881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup2 RESULT=skip>
12147 00:25:00.871181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup2 RESULT=skip
12149 00:25:00.926328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip>
12150 00:25:00.926609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip
12152 00:25:00.983363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup3 RESULT=skip>
12153 00:25:00.983641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup3 RESULT=skip
12155 00:25:01.038760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup4 RESULT=skip>
12156 00:25:01.039034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup4 RESULT=skip
12158 00:25:01.091246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup5 RESULT=skip>
12159 00:25:01.091526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup5 RESULT=skip
12161 00:25:01.149824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled_dup2 RESULT=skip>
12162 00:25:01.150112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled_dup2 RESULT=skip
12164 00:25:01.205885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac RESULT=pass>
12165 00:25:01.206191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac RESULT=pass
12167 00:25:01.266617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass>
12168 00:25:01.266901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass
12170 00:25:01.327536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass>
12171 00:25:01.327888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass
12173 00:25:01.389439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass>
12174 00:25:01.389724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass
12176 00:25:01.443195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass
12178 00:25:01.445915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass>
12179 00:25:01.502052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass>
12180 00:25:01.502404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass
12182 00:25:01.560024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass>
12183 00:25:01.560347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass
12185 00:25:01.615286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass>
12186 00:25:01.615605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass
12188 00:25:01.673648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass>
12189 00:25:01.673994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass
12191 00:25:01.725610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass>
12192 00:25:01.725931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass
12194 00:25:01.777254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass>
12195 00:25:01.777604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass
12197 00:25:01.834149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass>
12198 00:25:01.834495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass
12200 00:25:01.888974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass>
12201 00:25:01.889296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass
12203 00:25:01.949436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass>
12204 00:25:01.949768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass
12206 00:25:02.009284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass>
12207 00:25:02.009612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass
12209 00:25:02.061233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass>
12210 00:25:02.061560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass
12212 00:25:02.122351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass>
12213 00:25:02.122680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass
12215 00:25:02.181831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress RESULT=pass>
12216 00:25:02.182157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress RESULT=pass
12218 00:25:02.243959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_not_available RESULT=skip>
12219 00:25:02.244288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_not_available RESULT=skip
12221 00:25:02.298490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace RESULT=skip>
12222 00:25:02.298820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace RESULT=skip
12224 00:25:02.357756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_SVE_not_available RESULT=skip>
12225 00:25:02.358088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_SVE_not_available RESULT=skip
12227 00:25:02.414608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip>
12228 00:25:02.414982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip
12230 00:25:02.476498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12231 00:25:02.476830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12233 00:25:02.535144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup2 RESULT=skip>
12234 00:25:02.535524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup2 RESULT=skip
12236 00:25:02.588865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup3 RESULT=skip>
12237 00:25:02.589244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup3 RESULT=skip
12239 00:25:02.645243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup4 RESULT=skip>
12240 00:25:02.645624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup4 RESULT=skip
12242 00:25:02.706807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup5 RESULT=skip>
12243 00:25:02.707202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup5 RESULT=skip
12245 00:25:02.763689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup6 RESULT=skip>
12246 00:25:02.764049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup6 RESULT=skip
12248 00:25:02.818353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup7 RESULT=skip>
12249 00:25:02.818678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup7 RESULT=skip
12251 00:25:02.873196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup8 RESULT=skip>
12252 00:25:02.873561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup8 RESULT=skip
12254 00:25:02.922187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup9 RESULT=skip>
12255 00:25:02.922537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup9 RESULT=skip
12257 00:25:02.977678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup10 RESULT=skip>
12258 00:25:02.978039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup10 RESULT=skip
12260 00:25:03.033876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12261 00:25:03.034255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12263 00:25:03.084220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup2 RESULT=skip>
12264 00:25:03.084634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup2 RESULT=skip
12266 00:25:03.142926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup3 RESULT=skip>
12267 00:25:03.143304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup3 RESULT=skip
12269 00:25:03.200655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup4 RESULT=skip>
12270 00:25:03.201035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup4 RESULT=skip
12272 00:25:03.254258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup5 RESULT=skip>
12273 00:25:03.254634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup5 RESULT=skip
12275 00:25:03.311551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup6 RESULT=skip>
12276 00:25:03.311926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup6 RESULT=skip
12278 00:25:03.368073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup7 RESULT=skip>
12279 00:25:03.368453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup7 RESULT=skip
12281 00:25:03.424981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup8 RESULT=skip>
12282 00:25:03.425357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup8 RESULT=skip
12284 00:25:03.483007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup9 RESULT=skip>
12285 00:25:03.483385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup9 RESULT=skip
12287 00:25:03.542480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup10 RESULT=skip>
12288 00:25:03.542861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup10 RESULT=skip
12290 00:25:03.597841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg RESULT=pass>
12291 00:25:03.598229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg RESULT=pass
12293 00:25:03.655779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass>
12294 00:25:03.656162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass
12296 00:25:03.711137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork RESULT=pass>
12297 00:25:03.711513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork RESULT=pass
12299 00:25:03.764765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_SME_not_available RESULT=skip>
12300 00:25:03.765143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_SME_not_available RESULT=skip
12302 00:25:03.817593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace RESULT=skip>
12303 00:25:03.817969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace RESULT=skip
12305 00:25:03.876137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip>
12306 00:25:03.876513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip
12308 00:25:03.930222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory RESULT=skip>
12309 00:25:03.930599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory RESULT=skip
12311 00:25:03.987220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip
12313 00:25:03.990595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip>
12314 00:25:04.039864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_ksm_options RESULT=skip>
12315 00:25:04.040186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_ksm_options RESULT=skip
12317 00:25:04.092555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options RESULT=skip>
12318 00:25:04.092904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options RESULT=skip
12320 00:25:04.151311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass>
12321 00:25:04.151634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass
12323 00:25:04.204992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass>
12324 00:25:04.205318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass
12326 00:25:04.258376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=skip>
12327 00:25:04.258736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=skip
12329 00:25:04.317377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=skip>
12330 00:25:04.317707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=skip
12332 00:25:04.374703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=skip
12334 00:25:04.377931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=skip>
12335 00:25:04.430459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl RESULT=pass>
12336 00:25:04.430788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl RESULT=pass
12338 00:25:04.489431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip>
12339 00:25:04.489761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip
12341 00:25:04.549174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem RESULT=skip>
12342 00:25:04.549516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem RESULT=skip
12344 00:25:04.602396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip>
12345 00:25:04.602727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip
12347 00:25:04.664856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip>
12348 00:25:04.665187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip
12350 00:25:04.725521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip>
12351 00:25:04.725851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip
12353 00:25:04.783269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip>
12354 00:25:04.783598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip
12356 00:25:04.843208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip>
12357 00:25:04.843540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip
12359 00:25:04.898254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip>
12360 00:25:04.898583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip
12362 00:25:04.958157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip>
12363 00:25:04.958530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip
12365 00:25:05.015052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip>
12366 00:25:05.015386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip
12368 00:25:05.066624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip>
12369 00:25:05.066958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip
12371 00:25:05.117863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip>
12372 00:25:05.118218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip
12374 00:25:05.173332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip>
12375 00:25:05.173666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip
12377 00:25:05.231329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip>
12378 00:25:05.231662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip
12380 00:25:05.290356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12381 00:25:05.290696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip
12383 00:25:05.345581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12384 00:25:05.345922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip
12386 00:25:05.405210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip>
12387 00:25:05.405569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip
12389 00:25:05.456760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip>
12390 00:25:05.457094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip
12392 00:25:05.511681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip>
12393 00:25:05.512004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip
12395 00:25:05.567025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip>
12396 00:25:05.567357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip
12398 00:25:05.615052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest RESULT=pass>
12399 00:25:05.615390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest RESULT=pass
12401 00:25:05.674512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip>
12402 00:25:05.674839 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip
12404 00:25:05.735968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip>
12405 00:25:05.736310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip
12407 00:25:05.796098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip>
12408 00:25:05.796428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip
12410 00:25:05.850664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip>
12411 00:25:05.850990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip
12413 00:25:05.901625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip>
12414 00:25:05.901949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip
12416 00:25:05.958346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip>
12417 00:25:05.958673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip
12419 00:25:06.008423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip>
12420 00:25:06.008756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip
12422 00:25:06.060555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip>
12423 00:25:06.060890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip
12425 00:25:06.119761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip>
12426 00:25:06.120094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip
12428 00:25:06.173780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip>
12429 00:25:06.174145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip
12431 00:25:06.227866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip>
12432 00:25:06.228195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip
12434 00:25:06.280665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip>
12435 00:25:06.280993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip
12437 00:25:06.337223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12438 00:25:06.337558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip
12440 00:25:06.396272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12441 00:25:06.396598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip
12443 00:25:06.454045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip>
12444 00:25:06.454413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip
12446 00:25:06.510506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip>
12447 00:25:06.510849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip
12449 00:25:06.566956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip>
12450 00:25:06.567288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip
12452 00:25:06.620770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip>
12453 00:25:06.621094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip
12455 00:25:06.672172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest RESULT=pass>
12456 00:25:06.672515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest RESULT=pass
12458 00:25:06.731269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass>
12459 00:25:06.731590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass
12461 00:25:06.783751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=skip>
12462 00:25:06.784073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=skip
12464 00:25:06.847932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass>
12465 00:25:06.848266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass
12467 00:25:06.899914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass>
12468 00:25:06.900243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass
12470 00:25:06.960862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass>
12471 00:25:06.961188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass
12473 00:25:07.015366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass>
12474 00:25:07.015697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass
12476 00:25:07.078051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass>
12477 00:25:07.078448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass
12479 00:25:07.128125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=skip>
12480 00:25:07.128455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=skip
12482 00:25:07.185269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass>
12483 00:25:07.185595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass
12485 00:25:07.243310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=skip>
12486 00:25:07.243630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=skip
12488 00:25:07.300349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass>
12489 00:25:07.300685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass
12491 00:25:07.360333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=skip>
12492 00:25:07.360662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=skip
12494 00:25:07.418070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass>
12495 00:25:07.418444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass
12497 00:25:07.477501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=skip>
12498 00:25:07.477828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=skip
12500 00:25:07.531636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass>
12501 00:25:07.531961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass
12503 00:25:07.588673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=skip>
12504 00:25:07.588998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=skip
12506 00:25:07.648484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass>
12507 00:25:07.648810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass
12509 00:25:07.704822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=skip
12511 00:25:07.707585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=skip>
12512 00:25:07.766381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass>
12513 00:25:07.766712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass
12515 00:25:07.815761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=skip
12517 00:25:07.818559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=skip>
12518 00:25:07.875861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass>
12519 00:25:07.876192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass
12521 00:25:07.932002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=skip>
12522 00:25:07.932330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=skip
12524 00:25:07.991941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass>
12525 00:25:07.992278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass
12527 00:25:08.048943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=skip>
12528 00:25:08.049281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=skip
12530 00:25:08.107551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass>
12531 00:25:08.107893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass
12533 00:25:08.164207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=skip
12535 00:25:08.167646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=skip>
12536 00:25:08.225209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass>
12537 00:25:08.225538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass
12539 00:25:08.286435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip>
12540 00:25:08.286766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip
12542 00:25:08.340538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap RESULT=pass>
12543 00:25:08.340867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap RESULT=pass
12545 00:25:08.398987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass
12547 00:25:08.402121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass>
12548 00:25:08.453780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass
12550 00:25:08.457175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass>
12551 00:25:08.513179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass>
12552 00:25:08.513505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass
12554 00:25:08.570829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass
12556 00:25:08.573807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass>
12557 00:25:08.627081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass>
12558 00:25:08.627423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass
12560 00:25:08.684895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass>
12561 00:25:08.685205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass
12563 00:25:08.738804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass>
12564 00:25:08.739115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass
12566 00:25:08.786304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace RESULT=pass>
12567 00:25:08.786639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace RESULT=pass
12569 00:25:08.846700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass>
12570 00:25:08.847032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass
12572 00:25:08.900471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass>
12573 00:25:08.900798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass
12575 00:25:08.952470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi RESULT=pass>
12576 00:25:08.952835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi RESULT=pass
12578 00:25:09.013448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12579 00:25:09.013783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12581 00:25:09.071740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup2 RESULT=pass>
12582 00:25:09.072073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup2 RESULT=pass
12584 00:25:09.128885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup3 RESULT=pass>
12585 00:25:09.129220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup3 RESULT=pass
12587 00:25:09.179022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup4 RESULT=pass>
12588 00:25:09.179361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup4 RESULT=pass
12590 00:25:09.234708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup5 RESULT=pass>
12591 00:25:09.235044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup5 RESULT=pass
12593 00:25:09.292755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2 RESULT=pass>
12594 00:25:09.292911 + set +x
12595 00:25:09.293184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2 RESULT=pass
12597 00:25:09.299428 <LAVA_SIGNAL_ENDRUN 1_kselftest-arm64 14479184_1.6.2.3.5>
12598 00:25:09.299692 Received signal: <ENDRUN> 1_kselftest-arm64 14479184_1.6.2.3.5
12599 00:25:09.299776 Ending use of test pattern.
12600 00:25:09.299854 Ending test lava.1_kselftest-arm64 (14479184_1.6.2.3.5), duration 33.36
12602 00:25:09.302614 <LAVA_TEST_RUNNER EXIT>
12603 00:25:09.302874 ok: lava_test_shell seems to have completed
12604 00:25:09.303972 arm64_btitest: pass
arm64_btitest_bti_c_func_call_using_blr: skip
arm64_btitest_bti_c_func_call_using_br_x0: skip
arm64_btitest_bti_c_func_call_using_br_x16: skip
arm64_btitest_bti_j_func_call_using_blr: skip
arm64_btitest_bti_j_func_call_using_br_x0: skip
arm64_btitest_bti_j_func_call_using_br_x16: skip
arm64_btitest_bti_jc_func_call_using_blr: skip
arm64_btitest_bti_jc_func_call_using_br_x0: skip
arm64_btitest_bti_jc_func_call_using_br_x16: skip
arm64_btitest_bti_none_func_call_using_blr: skip
arm64_btitest_bti_none_func_call_using_br_x0: skip
arm64_btitest_bti_none_func_call_using_br_x16: skip
arm64_btitest_nohint_func_call_using_blr: skip
arm64_btitest_nohint_func_call_using_br_x0: skip
arm64_btitest_nohint_func_call_using_br_x16: skip
arm64_btitest_paciasp_func_call_using_blr: skip
arm64_btitest_paciasp_func_call_using_br_x0: skip
arm64_btitest_paciasp_func_call_using_br_x16: skip
arm64_check_buffer_fill: skip
arm64_check_child_memory: skip
arm64_check_gcr_el1_cswitch: skip
arm64_check_ksm_options: skip
arm64_check_mmap_options: skip
arm64_check_prctl: pass
arm64_check_prctl_ASYNC: skip
arm64_check_prctl_NONE: pass
arm64_check_prctl_SYNC: skip
arm64_check_prctl_SYNC_ASYNC: skip
arm64_check_prctl_check_basic_read: pass
arm64_check_tags_inclusion: skip
arm64_check_user_mem: skip
arm64_fake_sigreturn_bad_magic: pass
arm64_fake_sigreturn_bad_size: pass
arm64_fake_sigreturn_bad_size_for_magic0: pass
arm64_fake_sigreturn_duplicated_fpsimd: pass
arm64_fake_sigreturn_misaligned_sp: pass
arm64_fake_sigreturn_missing_fpsimd: pass
arm64_fake_sigreturn_sme_change_vl: skip
arm64_fake_sigreturn_sve_change_vl: skip
arm64_fp-stress: pass
arm64_fp-stress_FPSIMD-0-0: pass
arm64_fp-stress_FPSIMD-0-1: pass
arm64_fp-stress_FPSIMD-1-0: pass
arm64_fp-stress_FPSIMD-1-1: pass
arm64_fp-stress_FPSIMD-2-0: pass
arm64_fp-stress_FPSIMD-2-1: pass
arm64_fp-stress_FPSIMD-3-0: pass
arm64_fp-stress_FPSIMD-3-1: pass
arm64_fp-stress_FPSIMD-4-0: pass
arm64_fp-stress_FPSIMD-4-1: pass
arm64_fp-stress_FPSIMD-5-0: pass
arm64_fp-stress_FPSIMD-5-1: pass
arm64_fp-stress_FPSIMD-6-0: pass
arm64_fp-stress_FPSIMD-6-1: pass
arm64_fp-stress_FPSIMD-7-0: pass
arm64_fp-stress_FPSIMD-7-1: pass
arm64_hwcap: pass
arm64_hwcap_cpuinfo_match_RNG: pass
arm64_hwcap_cpuinfo_match_SME: pass
arm64_hwcap_cpuinfo_match_SVE: pass
arm64_hwcap_cpuinfo_match_SVE2_BF16: pass
arm64_hwcap_cpuinfo_match_SVE2_BITPERM: pass
arm64_hwcap_cpuinfo_match_SVE2_EBF16: pass
arm64_hwcap_cpuinfo_match_SVE2_F32MM: pass
arm64_hwcap_cpuinfo_match_SVE2_F64MM: pass
arm64_hwcap_cpuinfo_match_SVE2_I8MM: pass
arm64_hwcap_cpuinfo_match_SVE2_PMULL: pass
arm64_hwcap_cpuinfo_match_SVE2_SHA3: pass
arm64_hwcap_cpuinfo_match_SVE2_SM4: pass
arm64_hwcap_cpuinfo_match_SVE_2: pass
arm64_hwcap_cpuinfo_match_SVE_AES: pass
arm64_hwcap_sigill_RNG: skip
arm64_hwcap_sigill_SME: pass
arm64_hwcap_sigill_SVE: pass
arm64_hwcap_sigill_SVE2_BF16: skip
arm64_hwcap_sigill_SVE2_BITPERM: skip
arm64_hwcap_sigill_SVE2_EBF16: skip
arm64_hwcap_sigill_SVE2_F32MM: skip
arm64_hwcap_sigill_SVE2_F64MM: skip
arm64_hwcap_sigill_SVE2_I8MM: skip
arm64_hwcap_sigill_SVE2_PMULL: skip
arm64_hwcap_sigill_SVE2_SHA3: skip
arm64_hwcap_sigill_SVE2_SM4: skip
arm64_hwcap_sigill_SVE_2: skip
arm64_hwcap_sigill_SVE_AES: skip
arm64_mangle_pstate_invalid_compat_toggle: pass
arm64_mangle_pstate_invalid_daif_bits: pass
arm64_mangle_pstate_invalid_mode_el1h: pass
arm64_mangle_pstate_invalid_mode_el1t: pass
arm64_mangle_pstate_invalid_mode_el2h: pass
arm64_mangle_pstate_invalid_mode_el2t: pass
arm64_mangle_pstate_invalid_mode_el3h: pass
arm64_mangle_pstate_invalid_mode_el3t: pass
arm64_nobtitest: pass
arm64_nobtitest_bti_c_func_call_using_blr: skip
arm64_nobtitest_bti_c_func_call_using_br_x0: skip
arm64_nobtitest_bti_c_func_call_using_br_x16: skip
arm64_nobtitest_bti_j_func_call_using_blr: skip
arm64_nobtitest_bti_j_func_call_using_br_x0: skip
arm64_nobtitest_bti_j_func_call_using_br_x16: skip
arm64_nobtitest_bti_jc_func_call_using_blr: skip
arm64_nobtitest_bti_jc_func_call_using_br_x0: skip
arm64_nobtitest_bti_jc_func_call_using_br_x16: skip
arm64_nobtitest_bti_none_func_call_using_blr: skip
arm64_nobtitest_bti_none_func_call_using_br_x0: skip
arm64_nobtitest_bti_none_func_call_using_br_x16: skip
arm64_nobtitest_nohint_func_call_using_blr: skip
arm64_nobtitest_nohint_func_call_using_br_x0: skip
arm64_nobtitest_nohint_func_call_using_br_x16: skip
arm64_nobtitest_paciasp_func_call_using_blr: skip
arm64_nobtitest_paciasp_func_call_using_br_x0: skip
arm64_nobtitest_paciasp_func_call_using_br_x16: skip
arm64_pac: pass
arm64_pac_Generic_PAUTH_not_enabled: skip
arm64_pac_Generic_PAUTH_not_enabled_dup2: skip
arm64_pac_PAUTH_not_enabled: skip
arm64_pac_PAUTH_not_enabled_dup2: skip
arm64_pac_PAUTH_not_enabled_dup3: skip
arm64_pac_PAUTH_not_enabled_dup4: skip
arm64_pac_PAUTH_not_enabled_dup5: skip
arm64_ptrace: pass
arm64_ptrace_count_tpidrs: pass
arm64_ptrace_read_tpidr_one: pass
arm64_ptrace_tpidr2_read: pass
arm64_ptrace_tpidr2_write: pass
arm64_ptrace_verify_tpidr_one: pass
arm64_ptrace_write_tpidr_one: pass
arm64_ptrace_write_tpidr_only: pass
arm64_run_tags_test_sh: pass
arm64_sme_trap_no_sm: skip
arm64_sme_trap_non_streaming: skip
arm64_sme_trap_za: pass
arm64_sme_vl: skip
arm64_ssve_regs: skip
arm64_sve-probe-vls: skip
arm64_sve-probe-vls_SVE_not_available: skip
arm64_sve-ptrace: skip
arm64_sve-ptrace_SVE_not_available: skip
arm64_sve_regs: skip
arm64_sve_vl: skip
arm64_syscall-abi: pass
arm64_syscall-abi_getpid_FPSIMD: pass
arm64_syscall-abi_sched_yield_FPSIMD: pass
arm64_tags_test: pass
arm64_tpidr2: pass
arm64_tpidr2_skipped_TPIDR2_not_supported: pass
arm64_tpidr2_skipped_TPIDR2_not_supported_dup2: pass
arm64_tpidr2_skipped_TPIDR2_not_supported_dup3: pass
arm64_tpidr2_skipped_TPIDR2_not_supported_dup4: pass
arm64_tpidr2_skipped_TPIDR2_not_supported_dup5: pass
arm64_vec-syscfg: pass
arm64_vec-syscfg_SME_not_supported: skip
arm64_vec-syscfg_SME_not_supported_dup10: skip
arm64_vec-syscfg_SME_not_supported_dup2: skip
arm64_vec-syscfg_SME_not_supported_dup3: skip
arm64_vec-syscfg_SME_not_supported_dup4: skip
arm64_vec-syscfg_SME_not_supported_dup5: skip
arm64_vec-syscfg_SME_not_supported_dup6: skip
arm64_vec-syscfg_SME_not_supported_dup7: skip
arm64_vec-syscfg_SME_not_supported_dup8: skip
arm64_vec-syscfg_SME_not_supported_dup9: skip
arm64_vec-syscfg_SVE_not_supported: skip
arm64_vec-syscfg_SVE_not_supported_dup10: skip
arm64_vec-syscfg_SVE_not_supported_dup2: skip
arm64_vec-syscfg_SVE_not_supported_dup3: skip
arm64_vec-syscfg_SVE_not_supported_dup4: skip
arm64_vec-syscfg_SVE_not_supported_dup5: skip
arm64_vec-syscfg_SVE_not_supported_dup6: skip
arm64_vec-syscfg_SVE_not_supported_dup7: skip
arm64_vec-syscfg_SVE_not_supported_dup8: skip
arm64_vec-syscfg_SVE_not_supported_dup9: skip
arm64_za-fork: pass
arm64_za-fork_skipped: pass
arm64_za-ptrace: skip
arm64_za-ptrace_SME_not_available: skip
arm64_za_no_regs: skip
arm64_za_regs: skip
shardfile-arm64: pass
12605 00:25:09.304141 end: 3.1 lava-test-shell (duration 00:00:34) [common]
12606 00:25:09.304242 end: 3 lava-test-retry (duration 00:00:34) [common]
12607 00:25:09.304350 start: 4 finalize (timeout 00:06:51) [common]
12608 00:25:09.304456 start: 4.1 power-off (timeout 00:00:30) [common]
12609 00:25:09.304622 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-9', '--port=1', '--command=off']
12610 00:25:09.503823 >> Command sent successfully.
12611 00:25:09.506087 Returned 0 in 0 seconds
12612 00:25:09.606535 end: 4.1 power-off (duration 00:00:00) [common]
12614 00:25:09.606907 start: 4.2 read-feedback (timeout 00:06:51) [common]
12615 00:25:09.607211 Listened to connection for namespace 'common' for up to 1s
12616 00:25:10.608219 Finalising connection for namespace 'common'
12617 00:25:10.608413 Disconnecting from shell: Finalise
12618 00:25:10.608511 / #
12619 00:25:10.708878 end: 4.2 read-feedback (duration 00:00:01) [common]
12620 00:25:10.709088 end: 4 finalize (duration 00:00:01) [common]
12621 00:25:10.709254 Cleaning after the job
12622 00:25:10.709392 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14479184/tftp-deploy-8149qxkr/ramdisk
12623 00:25:10.712202 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14479184/tftp-deploy-8149qxkr/kernel
12624 00:25:10.723422 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14479184/tftp-deploy-8149qxkr/dtb
12625 00:25:10.723649 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14479184/tftp-deploy-8149qxkr/nfsrootfs
12626 00:25:10.781159 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14479184/tftp-deploy-8149qxkr/modules
12627 00:25:10.786320 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14479184
12628 00:25:11.346550 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14479184
12629 00:25:11.346741 Job finished correctly