Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 21
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
1 00:23:44.922032 lava-dispatcher, installed at version: 2024.03
2 00:23:44.922235 start: 0 validate
3 00:23:44.922344 Start time: 2024-06-21 00:23:44.922337+00:00 (UTC)
4 00:23:44.922467 Using caching service: 'http://localhost/cache/?uri=%s'
5 00:23:44.922604 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 00:23:45.182774 Using caching service: 'http://localhost/cache/?uri=%s'
7 00:23:45.182980 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.94-cip23%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 00:23:45.441977 Using caching service: 'http://localhost/cache/?uri=%s'
9 00:23:45.442736 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.94-cip23%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 00:23:45.696877 Using caching service: 'http://localhost/cache/?uri=%s'
11 00:23:45.697485 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 00:23:45.957084 Using caching service: 'http://localhost/cache/?uri=%s'
13 00:23:45.957732 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.94-cip23%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 00:23:46.217384 validate duration: 1.30
16 00:23:46.217710 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 00:23:46.217840 start: 1.1 download-retry (timeout 00:10:00) [common]
18 00:23:46.217960 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 00:23:46.218171 Not decompressing ramdisk as can be used compressed.
20 00:23:46.218279 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 00:23:46.218376 saving as /var/lib/lava/dispatcher/tmp/14479188/tftp-deploy-57w3ztgi/ramdisk/initrd.cpio.gz
22 00:23:46.218434 total size: 5628169 (5 MB)
23 00:23:46.219415 progress 0 % (0 MB)
24 00:23:46.221110 progress 5 % (0 MB)
25 00:23:46.222747 progress 10 % (0 MB)
26 00:23:46.224163 progress 15 % (0 MB)
27 00:23:46.225800 progress 20 % (1 MB)
28 00:23:46.227276 progress 25 % (1 MB)
29 00:23:46.228959 progress 30 % (1 MB)
30 00:23:46.230586 progress 35 % (1 MB)
31 00:23:46.232079 progress 40 % (2 MB)
32 00:23:46.233661 progress 45 % (2 MB)
33 00:23:46.235040 progress 50 % (2 MB)
34 00:23:46.236563 progress 55 % (2 MB)
35 00:23:46.238149 progress 60 % (3 MB)
36 00:23:46.239515 progress 65 % (3 MB)
37 00:23:46.241120 progress 70 % (3 MB)
38 00:23:46.242486 progress 75 % (4 MB)
39 00:23:46.244106 progress 80 % (4 MB)
40 00:23:46.245632 progress 85 % (4 MB)
41 00:23:46.247192 progress 90 % (4 MB)
42 00:23:46.248933 progress 95 % (5 MB)
43 00:23:46.250467 progress 100 % (5 MB)
44 00:23:46.250758 5 MB downloaded in 0.03 s (166.10 MB/s)
45 00:23:46.250970 end: 1.1.1 http-download (duration 00:00:00) [common]
47 00:23:46.251399 end: 1.1 download-retry (duration 00:00:00) [common]
48 00:23:46.251539 start: 1.2 download-retry (timeout 00:10:00) [common]
49 00:23:46.251672 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 00:23:46.251887 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.94-cip23/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 00:23:46.252000 saving as /var/lib/lava/dispatcher/tmp/14479188/tftp-deploy-57w3ztgi/kernel/Image
52 00:23:46.252124 total size: 54813184 (52 MB)
53 00:23:46.252255 No compression specified
54 00:23:46.253609 progress 0 % (0 MB)
55 00:23:46.268422 progress 5 % (2 MB)
56 00:23:46.284470 progress 10 % (5 MB)
57 00:23:46.299115 progress 15 % (7 MB)
58 00:23:46.313539 progress 20 % (10 MB)
59 00:23:46.327384 progress 25 % (13 MB)
60 00:23:46.341105 progress 30 % (15 MB)
61 00:23:46.354926 progress 35 % (18 MB)
62 00:23:46.368608 progress 40 % (20 MB)
63 00:23:46.382216 progress 45 % (23 MB)
64 00:23:46.396061 progress 50 % (26 MB)
65 00:23:46.409850 progress 55 % (28 MB)
66 00:23:46.423483 progress 60 % (31 MB)
67 00:23:46.437356 progress 65 % (34 MB)
68 00:23:46.450844 progress 70 % (36 MB)
69 00:23:46.464634 progress 75 % (39 MB)
70 00:23:46.478396 progress 80 % (41 MB)
71 00:23:46.492084 progress 85 % (44 MB)
72 00:23:46.505794 progress 90 % (47 MB)
73 00:23:46.519439 progress 95 % (49 MB)
74 00:23:46.532853 progress 100 % (52 MB)
75 00:23:46.533096 52 MB downloaded in 0.28 s (186.05 MB/s)
76 00:23:46.533247 end: 1.2.1 http-download (duration 00:00:00) [common]
78 00:23:46.533455 end: 1.2 download-retry (duration 00:00:00) [common]
79 00:23:46.533537 start: 1.3 download-retry (timeout 00:10:00) [common]
80 00:23:46.533612 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 00:23:46.533745 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.94-cip23/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 00:23:46.533806 saving as /var/lib/lava/dispatcher/tmp/14479188/tftp-deploy-57w3ztgi/dtb/mt8192-asurada-spherion-r0.dtb
83 00:23:46.533859 total size: 47258 (0 MB)
84 00:23:46.533912 No compression specified
85 00:23:46.535023 progress 69 % (0 MB)
86 00:23:46.535287 progress 100 % (0 MB)
87 00:23:46.535437 0 MB downloaded in 0.00 s (28.62 MB/s)
88 00:23:46.535562 end: 1.3.1 http-download (duration 00:00:00) [common]
90 00:23:46.535811 end: 1.3 download-retry (duration 00:00:00) [common]
91 00:23:46.535918 start: 1.4 download-retry (timeout 00:10:00) [common]
92 00:23:46.536003 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 00:23:46.536110 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 00:23:46.536171 saving as /var/lib/lava/dispatcher/tmp/14479188/tftp-deploy-57w3ztgi/nfsrootfs/full.rootfs.tar
95 00:23:46.536225 total size: 120894716 (115 MB)
96 00:23:46.536279 Using unxz to decompress xz
97 00:23:46.537483 progress 0 % (0 MB)
98 00:23:46.881665 progress 5 % (5 MB)
99 00:23:47.234650 progress 10 % (11 MB)
100 00:23:47.594697 progress 15 % (17 MB)
101 00:23:47.934449 progress 20 % (23 MB)
102 00:23:48.237325 progress 25 % (28 MB)
103 00:23:48.592417 progress 30 % (34 MB)
104 00:23:48.920521 progress 35 % (40 MB)
105 00:23:49.092817 progress 40 % (46 MB)
106 00:23:49.282888 progress 45 % (51 MB)
107 00:23:49.591363 progress 50 % (57 MB)
108 00:23:49.948436 progress 55 % (63 MB)
109 00:23:50.287447 progress 60 % (69 MB)
110 00:23:50.630408 progress 65 % (74 MB)
111 00:23:50.974958 progress 70 % (80 MB)
112 00:23:51.334308 progress 75 % (86 MB)
113 00:23:51.681376 progress 80 % (92 MB)
114 00:23:52.034811 progress 85 % (98 MB)
115 00:23:52.393647 progress 90 % (103 MB)
116 00:23:52.735994 progress 95 % (109 MB)
117 00:23:53.106618 progress 100 % (115 MB)
118 00:23:53.112166 115 MB downloaded in 6.58 s (17.53 MB/s)
119 00:23:53.112330 end: 1.4.1 http-download (duration 00:00:07) [common]
121 00:23:53.112539 end: 1.4 download-retry (duration 00:00:07) [common]
122 00:23:53.112618 start: 1.5 download-retry (timeout 00:09:53) [common]
123 00:23:53.112694 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 00:23:53.112862 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.94-cip23/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 00:23:53.112923 saving as /var/lib/lava/dispatcher/tmp/14479188/tftp-deploy-57w3ztgi/modules/modules.tar
126 00:23:53.112977 total size: 8618924 (8 MB)
127 00:23:53.113032 Using unxz to decompress xz
128 00:23:53.114342 progress 0 % (0 MB)
129 00:23:53.133392 progress 5 % (0 MB)
130 00:23:53.156978 progress 10 % (0 MB)
131 00:23:53.181760 progress 15 % (1 MB)
132 00:23:53.206873 progress 20 % (1 MB)
133 00:23:53.231595 progress 25 % (2 MB)
134 00:23:53.255346 progress 30 % (2 MB)
135 00:23:53.279927 progress 35 % (2 MB)
136 00:23:53.304956 progress 40 % (3 MB)
137 00:23:53.330219 progress 45 % (3 MB)
138 00:23:53.354676 progress 50 % (4 MB)
139 00:23:53.379765 progress 55 % (4 MB)
140 00:23:53.404888 progress 60 % (4 MB)
141 00:23:53.427898 progress 65 % (5 MB)
142 00:23:53.454728 progress 70 % (5 MB)
143 00:23:53.478640 progress 75 % (6 MB)
144 00:23:53.502812 progress 80 % (6 MB)
145 00:23:53.525921 progress 85 % (7 MB)
146 00:23:53.549313 progress 90 % (7 MB)
147 00:23:53.575358 progress 95 % (7 MB)
148 00:23:53.603442 progress 100 % (8 MB)
149 00:23:53.607908 8 MB downloaded in 0.49 s (16.61 MB/s)
150 00:23:53.608125 end: 1.5.1 http-download (duration 00:00:00) [common]
152 00:23:53.608475 end: 1.5 download-retry (duration 00:00:00) [common]
153 00:23:53.608598 start: 1.6 prepare-tftp-overlay (timeout 00:09:53) [common]
154 00:23:53.608744 start: 1.6.1 extract-nfsrootfs (timeout 00:09:53) [common]
155 00:23:57.190634 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14479188/extract-nfsrootfs-0_775cf7
156 00:23:57.190888 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 00:23:57.190986 start: 1.6.2 lava-overlay (timeout 00:09:49) [common]
158 00:23:57.191196 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14479188/lava-overlay-eftn43m8
159 00:23:57.191318 makedir: /var/lib/lava/dispatcher/tmp/14479188/lava-overlay-eftn43m8/lava-14479188/bin
160 00:23:57.191422 makedir: /var/lib/lava/dispatcher/tmp/14479188/lava-overlay-eftn43m8/lava-14479188/tests
161 00:23:57.191516 makedir: /var/lib/lava/dispatcher/tmp/14479188/lava-overlay-eftn43m8/lava-14479188/results
162 00:23:57.191607 Creating /var/lib/lava/dispatcher/tmp/14479188/lava-overlay-eftn43m8/lava-14479188/bin/lava-add-keys
163 00:23:57.191755 Creating /var/lib/lava/dispatcher/tmp/14479188/lava-overlay-eftn43m8/lava-14479188/bin/lava-add-sources
164 00:23:57.191884 Creating /var/lib/lava/dispatcher/tmp/14479188/lava-overlay-eftn43m8/lava-14479188/bin/lava-background-process-start
165 00:23:57.192019 Creating /var/lib/lava/dispatcher/tmp/14479188/lava-overlay-eftn43m8/lava-14479188/bin/lava-background-process-stop
166 00:23:57.192173 Creating /var/lib/lava/dispatcher/tmp/14479188/lava-overlay-eftn43m8/lava-14479188/bin/lava-common-functions
167 00:23:57.192299 Creating /var/lib/lava/dispatcher/tmp/14479188/lava-overlay-eftn43m8/lava-14479188/bin/lava-echo-ipv4
168 00:23:57.192420 Creating /var/lib/lava/dispatcher/tmp/14479188/lava-overlay-eftn43m8/lava-14479188/bin/lava-install-packages
169 00:23:57.192565 Creating /var/lib/lava/dispatcher/tmp/14479188/lava-overlay-eftn43m8/lava-14479188/bin/lava-installed-packages
170 00:23:57.192686 Creating /var/lib/lava/dispatcher/tmp/14479188/lava-overlay-eftn43m8/lava-14479188/bin/lava-os-build
171 00:23:57.192844 Creating /var/lib/lava/dispatcher/tmp/14479188/lava-overlay-eftn43m8/lava-14479188/bin/lava-probe-channel
172 00:23:57.192960 Creating /var/lib/lava/dispatcher/tmp/14479188/lava-overlay-eftn43m8/lava-14479188/bin/lava-probe-ip
173 00:23:57.193125 Creating /var/lib/lava/dispatcher/tmp/14479188/lava-overlay-eftn43m8/lava-14479188/bin/lava-target-ip
174 00:23:57.193258 Creating /var/lib/lava/dispatcher/tmp/14479188/lava-overlay-eftn43m8/lava-14479188/bin/lava-target-mac
175 00:23:57.193439 Creating /var/lib/lava/dispatcher/tmp/14479188/lava-overlay-eftn43m8/lava-14479188/bin/lava-target-storage
176 00:23:57.193561 Creating /var/lib/lava/dispatcher/tmp/14479188/lava-overlay-eftn43m8/lava-14479188/bin/lava-test-case
177 00:23:57.193681 Creating /var/lib/lava/dispatcher/tmp/14479188/lava-overlay-eftn43m8/lava-14479188/bin/lava-test-event
178 00:23:57.193795 Creating /var/lib/lava/dispatcher/tmp/14479188/lava-overlay-eftn43m8/lava-14479188/bin/lava-test-feedback
179 00:23:57.193941 Creating /var/lib/lava/dispatcher/tmp/14479188/lava-overlay-eftn43m8/lava-14479188/bin/lava-test-raise
180 00:23:57.194055 Creating /var/lib/lava/dispatcher/tmp/14479188/lava-overlay-eftn43m8/lava-14479188/bin/lava-test-reference
181 00:23:57.194176 Creating /var/lib/lava/dispatcher/tmp/14479188/lava-overlay-eftn43m8/lava-14479188/bin/lava-test-runner
182 00:23:57.194293 Creating /var/lib/lava/dispatcher/tmp/14479188/lava-overlay-eftn43m8/lava-14479188/bin/lava-test-set
183 00:23:57.194409 Creating /var/lib/lava/dispatcher/tmp/14479188/lava-overlay-eftn43m8/lava-14479188/bin/lava-test-shell
184 00:23:57.194524 Updating /var/lib/lava/dispatcher/tmp/14479188/lava-overlay-eftn43m8/lava-14479188/bin/lava-add-keys (debian)
185 00:23:57.199968 Updating /var/lib/lava/dispatcher/tmp/14479188/lava-overlay-eftn43m8/lava-14479188/bin/lava-add-sources (debian)
186 00:23:57.200110 Updating /var/lib/lava/dispatcher/tmp/14479188/lava-overlay-eftn43m8/lava-14479188/bin/lava-install-packages (debian)
187 00:23:57.200243 Updating /var/lib/lava/dispatcher/tmp/14479188/lava-overlay-eftn43m8/lava-14479188/bin/lava-installed-packages (debian)
188 00:23:57.200374 Updating /var/lib/lava/dispatcher/tmp/14479188/lava-overlay-eftn43m8/lava-14479188/bin/lava-os-build (debian)
189 00:23:57.200489 Creating /var/lib/lava/dispatcher/tmp/14479188/lava-overlay-eftn43m8/lava-14479188/environment
190 00:23:57.200583 LAVA metadata
191 00:23:57.200653 - LAVA_JOB_ID=14479188
192 00:23:57.200741 - LAVA_DISPATCHER_IP=192.168.201.1
193 00:23:57.200863 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:49) [common]
194 00:23:57.200923 skipped lava-vland-overlay
195 00:23:57.200991 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 00:23:57.201063 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:49) [common]
197 00:23:57.201120 skipped lava-multinode-overlay
198 00:23:57.201185 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 00:23:57.201263 start: 1.6.2.3 test-definition (timeout 00:09:49) [common]
200 00:23:57.201327 Loading test definitions
201 00:23:57.201406 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:49) [common]
202 00:23:57.201503 Using /lava-14479188 at stage 0
203 00:23:57.201787 uuid=14479188_1.6.2.3.1 testdef=None
204 00:23:57.201870 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 00:23:57.201945 start: 1.6.2.3.2 test-overlay (timeout 00:09:49) [common]
206 00:23:57.202347 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 00:23:57.202557 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:49) [common]
209 00:23:57.204319 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 00:23:57.204529 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:49) [common]
212 00:23:57.205071 runner path: /var/lib/lava/dispatcher/tmp/14479188/lava-overlay-eftn43m8/lava-14479188/0/tests/0_timesync-off test_uuid 14479188_1.6.2.3.1
213 00:23:57.205220 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 00:23:57.205429 start: 1.6.2.3.5 git-repo-action (timeout 00:09:49) [common]
216 00:23:57.205494 Using /lava-14479188 at stage 0
217 00:23:57.205581 Fetching tests from https://github.com/kernelci/test-definitions.git
218 00:23:57.205655 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14479188/lava-overlay-eftn43m8/lava-14479188/0/tests/1_kselftest-dt'
219 00:23:59.960290 Running '/usr/bin/git checkout kernelci.org
220 00:24:00.110165 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14479188/lava-overlay-eftn43m8/lava-14479188/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
221 00:24:00.110533 uuid=14479188_1.6.2.3.5 testdef=None
222 00:24:00.110640 end: 1.6.2.3.5 git-repo-action (duration 00:00:03) [common]
224 00:24:00.110836 start: 1.6.2.3.6 test-overlay (timeout 00:09:46) [common]
225 00:24:00.111515 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 00:24:00.111720 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:46) [common]
228 00:24:00.112611 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 00:24:00.112896 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:46) [common]
231 00:24:00.113813 runner path: /var/lib/lava/dispatcher/tmp/14479188/lava-overlay-eftn43m8/lava-14479188/0/tests/1_kselftest-dt test_uuid 14479188_1.6.2.3.5
232 00:24:00.113898 BOARD='mt8192-asurada-spherion-r0'
233 00:24:00.113959 BRANCH='cip'
234 00:24:00.114012 SKIPFILE='/dev/null'
235 00:24:00.114063 SKIP_INSTALL='True'
236 00:24:00.114114 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.94-cip23/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 00:24:00.114165 TST_CASENAME=''
238 00:24:00.114216 TST_CMDFILES='dt'
239 00:24:00.114351 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 00:24:00.114529 Creating lava-test-runner.conf files
242 00:24:00.114584 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14479188/lava-overlay-eftn43m8/lava-14479188/0 for stage 0
243 00:24:00.114667 - 0_timesync-off
244 00:24:00.114727 - 1_kselftest-dt
245 00:24:00.114814 end: 1.6.2.3 test-definition (duration 00:00:03) [common]
246 00:24:00.114892 start: 1.6.2.4 compress-overlay (timeout 00:09:46) [common]
247 00:24:07.478128 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 00:24:07.478261 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:39) [common]
249 00:24:07.478345 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 00:24:07.478427 end: 1.6.2 lava-overlay (duration 00:00:10) [common]
251 00:24:07.478508 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:39) [common]
252 00:24:07.637744 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 00:24:07.637879 start: 1.6.4 extract-modules (timeout 00:09:39) [common]
254 00:24:07.637959 extracting modules file /var/lib/lava/dispatcher/tmp/14479188/tftp-deploy-57w3ztgi/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14479188/extract-nfsrootfs-0_775cf7
255 00:24:07.876329 extracting modules file /var/lib/lava/dispatcher/tmp/14479188/tftp-deploy-57w3ztgi/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14479188/extract-overlay-ramdisk-vzg4nzpm/ramdisk
256 00:24:08.101491 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 00:24:08.101633 start: 1.6.5 apply-overlay-tftp (timeout 00:09:38) [common]
258 00:24:08.101714 [common] Applying overlay to NFS
259 00:24:08.101774 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14479188/compress-overlay-6y8sbzz3/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14479188/extract-nfsrootfs-0_775cf7
260 00:24:08.955821 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 00:24:08.955962 start: 1.6.6 configure-preseed-file (timeout 00:09:37) [common]
262 00:24:08.956051 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 00:24:08.956162 start: 1.6.7 compress-ramdisk (timeout 00:09:37) [common]
264 00:24:08.956233 Building ramdisk /var/lib/lava/dispatcher/tmp/14479188/extract-overlay-ramdisk-vzg4nzpm/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14479188/extract-overlay-ramdisk-vzg4nzpm/ramdisk
265 00:24:09.320926 >> 130487 blocks
266 00:24:11.358902 rename /var/lib/lava/dispatcher/tmp/14479188/extract-overlay-ramdisk-vzg4nzpm/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14479188/tftp-deploy-57w3ztgi/ramdisk/ramdisk.cpio.gz
267 00:24:11.359137 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 00:24:11.359270 start: 1.6.8 prepare-kernel (timeout 00:09:35) [common]
269 00:24:11.359384 start: 1.6.8.1 prepare-fit (timeout 00:09:35) [common]
270 00:24:11.359497 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14479188/tftp-deploy-57w3ztgi/kernel/Image']
271 00:24:25.716205 Returned 0 in 14 seconds
272 00:24:25.816710 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14479188/tftp-deploy-57w3ztgi/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14479188/tftp-deploy-57w3ztgi/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14479188/tftp-deploy-57w3ztgi/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14479188/tftp-deploy-57w3ztgi/kernel/image.itb
273 00:24:26.199119 output: FIT description: Kernel Image image with one or more FDT blobs
274 00:24:26.199256 output: Created: Fri Jun 21 01:24:26 2024
275 00:24:26.199329 output: Image 0 (kernel-1)
276 00:24:26.199390 output: Description:
277 00:24:26.199453 output: Created: Fri Jun 21 01:24:26 2024
278 00:24:26.199515 output: Type: Kernel Image
279 00:24:26.199574 output: Compression: lzma compressed
280 00:24:26.199637 output: Data Size: 13124896 Bytes = 12817.28 KiB = 12.52 MiB
281 00:24:26.199696 output: Architecture: AArch64
282 00:24:26.199754 output: OS: Linux
283 00:24:26.199813 output: Load Address: 0x00000000
284 00:24:26.199869 output: Entry Point: 0x00000000
285 00:24:26.199924 output: Hash algo: crc32
286 00:24:26.199979 output: Hash value: ab2f7826
287 00:24:26.200032 output: Image 1 (fdt-1)
288 00:24:26.200085 output: Description: mt8192-asurada-spherion-r0
289 00:24:26.200138 output: Created: Fri Jun 21 01:24:26 2024
290 00:24:26.200191 output: Type: Flat Device Tree
291 00:24:26.200241 output: Compression: uncompressed
292 00:24:26.200290 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
293 00:24:26.200341 output: Architecture: AArch64
294 00:24:26.200393 output: Hash algo: crc32
295 00:24:26.200442 output: Hash value: 0f8e4d2e
296 00:24:26.200492 output: Image 2 (ramdisk-1)
297 00:24:26.200542 output: Description: unavailable
298 00:24:26.200591 output: Created: Fri Jun 21 01:24:26 2024
299 00:24:26.200641 output: Type: RAMDisk Image
300 00:24:26.200695 output: Compression: uncompressed
301 00:24:26.200778 output: Data Size: 18746529 Bytes = 18307.16 KiB = 17.88 MiB
302 00:24:26.200828 output: Architecture: AArch64
303 00:24:26.200877 output: OS: Linux
304 00:24:26.200926 output: Load Address: unavailable
305 00:24:26.200975 output: Entry Point: unavailable
306 00:24:26.201023 output: Hash algo: crc32
307 00:24:26.201071 output: Hash value: 75641833
308 00:24:26.201120 output: Default Configuration: 'conf-1'
309 00:24:26.201168 output: Configuration 0 (conf-1)
310 00:24:26.201217 output: Description: mt8192-asurada-spherion-r0
311 00:24:26.201266 output: Kernel: kernel-1
312 00:24:26.201314 output: Init Ramdisk: ramdisk-1
313 00:24:26.201363 output: FDT: fdt-1
314 00:24:26.201411 output: Loadables: kernel-1
315 00:24:26.201488 output:
316 00:24:26.201630 end: 1.6.8.1 prepare-fit (duration 00:00:15) [common]
317 00:24:26.201722 end: 1.6.8 prepare-kernel (duration 00:00:15) [common]
318 00:24:26.201818 end: 1.6 prepare-tftp-overlay (duration 00:00:33) [common]
319 00:24:26.201905 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:20) [common]
320 00:24:26.201972 No LXC device requested
321 00:24:26.202043 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 00:24:26.202118 start: 1.8 deploy-device-env (timeout 00:09:20) [common]
323 00:24:26.202188 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 00:24:26.202250 Checking files for TFTP limit of 4294967296 bytes.
325 00:24:26.202716 end: 1 tftp-deploy (duration 00:00:40) [common]
326 00:24:26.202818 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 00:24:26.202930 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 00:24:26.203046 substitutions:
329 00:24:26.203110 - {DTB}: 14479188/tftp-deploy-57w3ztgi/dtb/mt8192-asurada-spherion-r0.dtb
330 00:24:26.203170 - {INITRD}: 14479188/tftp-deploy-57w3ztgi/ramdisk/ramdisk.cpio.gz
331 00:24:26.203226 - {KERNEL}: 14479188/tftp-deploy-57w3ztgi/kernel/Image
332 00:24:26.203282 - {LAVA_MAC}: None
333 00:24:26.203334 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14479188/extract-nfsrootfs-0_775cf7
334 00:24:26.203389 - {NFS_SERVER_IP}: 192.168.201.1
335 00:24:26.203440 - {PRESEED_CONFIG}: None
336 00:24:26.203498 - {PRESEED_LOCAL}: None
337 00:24:26.203551 - {RAMDISK}: 14479188/tftp-deploy-57w3ztgi/ramdisk/ramdisk.cpio.gz
338 00:24:26.203602 - {ROOT_PART}: None
339 00:24:26.203651 - {ROOT}: None
340 00:24:26.203701 - {SERVER_IP}: 192.168.201.1
341 00:24:26.203749 - {TEE}: None
342 00:24:26.203799 Parsed boot commands:
343 00:24:26.203847 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 00:24:26.204006 Parsed boot commands: tftpboot 192.168.201.1 14479188/tftp-deploy-57w3ztgi/kernel/image.itb 14479188/tftp-deploy-57w3ztgi/kernel/cmdline
345 00:24:26.204089 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 00:24:26.204166 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 00:24:26.204250 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 00:24:26.204327 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 00:24:26.204389 Not connected, no need to disconnect.
350 00:24:26.204457 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 00:24:26.204530 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 00:24:26.204590 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-1'
353 00:24:26.207938 Setting prompt string to ['lava-test: # ']
354 00:24:26.208257 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 00:24:26.208358 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 00:24:26.208454 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 00:24:26.208540 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 00:24:26.208743 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-1', '--port=1', '--command=reboot']
359 00:24:35.295380 >> Command sent successfully.
360 00:24:35.298439 Returned 0 in 9 seconds
361 00:24:35.398774 end: 2.2.2.1 pdu-reboot (duration 00:00:09) [common]
363 00:24:35.399044 end: 2.2.2 reset-device (duration 00:00:09) [common]
364 00:24:35.399145 start: 2.2.3 depthcharge-start (timeout 00:04:51) [common]
365 00:24:35.399231 Setting prompt string to 'Starting depthcharge on Spherion...'
366 00:24:35.399291 Changing prompt to 'Starting depthcharge on Spherion...'
367 00:24:35.399355 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 00:24:35.399713 [Enter `^Ec?' for help]
369 00:24:36.506826
370 00:24:36.506939
371 00:24:36.507002 F0: 102B 0000
372 00:24:36.507064
373 00:24:36.507121 F3: 1001 0000 [0200]
374 00:24:36.510200
375 00:24:36.510274 F3: 1001 0000
376 00:24:36.510336
377 00:24:36.510395 F7: 102D 0000
378 00:24:36.510451
379 00:24:36.513316 F1: 0000 0000
380 00:24:36.513397
381 00:24:36.513460 V0: 0000 0000 [0001]
382 00:24:36.513516
383 00:24:36.516568 00: 0007 8000
384 00:24:36.516645
385 00:24:36.516711 01: 0000 0000
386 00:24:36.516801
387 00:24:36.519667 BP: 0C00 0209 [0000]
388 00:24:36.519771
389 00:24:36.519861 G0: 1182 0000
390 00:24:36.519946
391 00:24:36.523327 EC: 0000 0021 [4000]
392 00:24:36.523403
393 00:24:36.523461 S7: 0000 0000 [0000]
394 00:24:36.523515
395 00:24:36.526367 CC: 0000 0000 [0001]
396 00:24:36.526442
397 00:24:36.526500 T0: 0000 0040 [010F]
398 00:24:36.526555
399 00:24:36.529906 Jump to BL
400 00:24:36.529981
401 00:24:36.553279
402 00:24:36.553356
403 00:24:36.563369 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
404 00:24:36.566495 ARM64: Exception handlers installed.
405 00:24:36.566572 ARM64: Testing exception
406 00:24:36.570145 ARM64: Done test exception
407 00:24:36.576400 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
408 00:24:36.586980 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
409 00:24:36.593362 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
410 00:24:36.604579 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
411 00:24:36.610877 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
412 00:24:36.618666 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
413 00:24:36.631241 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
414 00:24:36.638326 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
415 00:24:36.657562 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
416 00:24:36.661238 WDT: Last reset was cold boot
417 00:24:36.665118 SPI1(PAD0) initialized at 2873684 Hz
418 00:24:36.668781 SPI5(PAD0) initialized at 992727 Hz
419 00:24:36.668862 VBOOT: Loading verstage.
420 00:24:36.675772 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
421 00:24:36.678853 FMAP: Found "FLASH" version 1.1 at 0x20000.
422 00:24:36.682358 FMAP: base = 0x0 size = 0x800000 #areas = 25
423 00:24:36.688933 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
424 00:24:36.695948 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
425 00:24:36.702519 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
426 00:24:36.711253 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
427 00:24:36.711334
428 00:24:36.711393
429 00:24:36.721431 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
430 00:24:36.724647 ARM64: Exception handlers installed.
431 00:24:36.727954 ARM64: Testing exception
432 00:24:36.728031 ARM64: Done test exception
433 00:24:36.735470 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
434 00:24:36.738999 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
435 00:24:36.753234 Probing TPM: . done!
436 00:24:36.753312 TPM ready after 0 ms
437 00:24:36.760051 Connected to device vid:did:rid of 1ae0:0028:00
438 00:24:36.767003 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
439 00:24:36.807229 Initialized TPM device CR50 revision 0
440 00:24:36.821690 tlcl_send_startup: Startup return code is 0
441 00:24:36.821769 TPM: setup succeeded
442 00:24:36.836835 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
443 00:24:36.844300 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
444 00:24:36.853490 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
445 00:24:36.862417 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
446 00:24:36.865514 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
447 00:24:36.869050 in-header: 03 07 00 00 08 00 00 00
448 00:24:36.872170 in-data: aa e4 47 04 13 02 00 00
449 00:24:36.875825 Chrome EC: UHEPI supported
450 00:24:36.882449 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
451 00:24:36.885444 in-header: 03 a9 00 00 08 00 00 00
452 00:24:36.889025 in-data: 84 60 60 08 00 00 00 00
453 00:24:36.889126 Phase 1
454 00:24:36.892579 FMAP: area GBB found @ 3f5000 (12032 bytes)
455 00:24:36.899364 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
456 00:24:36.905840 VB2:vb2_check_recovery() Recovery was requested manually
457 00:24:36.908877 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
458 00:24:36.912577 Recovery requested (1009000e)
459 00:24:36.920564 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 00:24:36.926005 tlcl_extend: response is 0
461 00:24:36.935842 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 00:24:36.939585 tlcl_extend: response is 0
463 00:24:36.946399 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 00:24:36.966708 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 00:24:36.973673 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 00:24:36.973750
467 00:24:36.973809
468 00:24:36.984020 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 00:24:36.987046 ARM64: Exception handlers installed.
470 00:24:36.990040 ARM64: Testing exception
471 00:24:36.990117 ARM64: Done test exception
472 00:24:37.012394 pmic_efuse_setting: Set efuses in 11 msecs
473 00:24:37.016001 pmwrap_interface_init: Select PMIF_VLD_RDY
474 00:24:37.022406 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 00:24:37.025952 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 00:24:37.032848 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 00:24:37.036177 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 00:24:37.042774 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 00:24:37.046023 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 00:24:37.049569 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 00:24:37.055950 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 00:24:37.059360 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 00:24:37.065995 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 00:24:37.069207 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 00:24:37.072649 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 00:24:37.079220 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 00:24:37.085998 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 00:24:37.089646 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 00:24:37.096135 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 00:24:37.102931 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 00:24:37.105985 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 00:24:37.113029 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 00:24:37.119620 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 00:24:37.123203 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 00:24:37.129399 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 00:24:37.136021 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 00:24:37.139773 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 00:24:37.146423 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 00:24:37.153151 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 00:24:37.156091 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 00:24:37.163119 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 00:24:37.166349 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 00:24:37.170141 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 00:24:37.176265 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 00:24:37.182936 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 00:24:37.186324 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 00:24:37.193288 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 00:24:37.196382 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 00:24:37.202815 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 00:24:37.206755 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 00:24:37.210356 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 00:24:37.216968 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 00:24:37.220559 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 00:24:37.223521 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 00:24:37.230257 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 00:24:37.233886 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 00:24:37.237573 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 00:24:37.240873 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 00:24:37.247588 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 00:24:37.250523 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 00:24:37.253978 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 00:24:37.260975 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 00:24:37.263784 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 00:24:37.267274 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 00:24:37.274155 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
526 00:24:37.283919 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 00:24:37.287768 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 00:24:37.294923 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 00:24:37.306312 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 00:24:37.309948 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 00:24:37.313623 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 00:24:37.317030 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 00:24:37.325955 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x27
534 00:24:37.329626 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 00:24:37.338045 [RTC]rtc_osc_init,62: osc32con val = 0xde70
536 00:24:37.341173 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 00:24:37.350176 [RTC]rtc_get_frequency_meter,154: input=15, output=774
538 00:24:37.359883 [RTC]rtc_get_frequency_meter,154: input=23, output=958
539 00:24:37.369107 [RTC]rtc_get_frequency_meter,154: input=19, output=866
540 00:24:37.377982 [RTC]rtc_get_frequency_meter,154: input=17, output=819
541 00:24:37.388936 [RTC]rtc_get_frequency_meter,154: input=16, output=795
542 00:24:37.392250 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
543 00:24:37.396322 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
544 00:24:37.400211 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
545 00:24:37.403914 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
546 00:24:37.407563 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
547 00:24:37.411624 ADC[4]: Raw value=903245 ID=7
548 00:24:37.415437 ADC[3]: Raw value=213179 ID=1
549 00:24:37.415513 RAM Code: 0x71
550 00:24:37.422777 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
551 00:24:37.426136 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
552 00:24:37.434069 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
553 00:24:37.441191 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
554 00:24:37.444901 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
555 00:24:37.448750 in-header: 03 07 00 00 08 00 00 00
556 00:24:37.452343 in-data: aa e4 47 04 13 02 00 00
557 00:24:37.452419 Chrome EC: UHEPI supported
558 00:24:37.459783 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
559 00:24:37.463430 in-header: 03 a9 00 00 08 00 00 00
560 00:24:37.467547 in-data: 84 60 60 08 00 00 00 00
561 00:24:37.471121 MRC: failed to locate region type 0.
562 00:24:37.474998 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
563 00:24:37.478842 DRAM-K: Running full calibration
564 00:24:37.486441 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
565 00:24:37.486519 header.status = 0x0
566 00:24:37.490161 header.version = 0x6 (expected: 0x6)
567 00:24:37.493599 header.size = 0xd00 (expected: 0xd00)
568 00:24:37.497542 header.flags = 0x0
569 00:24:37.501263 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
570 00:24:37.520595 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
571 00:24:37.528362 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
572 00:24:37.528441 dram_init: ddr_geometry: 2
573 00:24:37.531805 [EMI] MDL number = 2
574 00:24:37.535743 [EMI] Get MDL freq = 0
575 00:24:37.535821 dram_init: ddr_type: 0
576 00:24:37.539500 is_discrete_lpddr4: 1
577 00:24:37.539581 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
578 00:24:37.539643
579 00:24:37.539702
580 00:24:37.543408 [Bian_co] ETT version 0.0.0.1
581 00:24:37.547068 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
582 00:24:37.551244
583 00:24:37.551321 dramc_set_vcore_voltage set vcore to 650000
584 00:24:37.554857 Read voltage for 800, 4
585 00:24:37.554934 Vio18 = 0
586 00:24:37.558249 Vcore = 650000
587 00:24:37.558326 Vdram = 0
588 00:24:37.558386 Vddq = 0
589 00:24:37.558448 Vmddr = 0
590 00:24:37.562352 dram_init: config_dvfs: 1
591 00:24:37.565837 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
592 00:24:37.573126 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
593 00:24:37.576855 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=9
594 00:24:37.580111 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=9
595 00:24:37.584321 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
596 00:24:37.587847 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
597 00:24:37.591735 MEM_TYPE=3, freq_sel=18
598 00:24:37.591811 sv_algorithm_assistance_LP4_1600
599 00:24:37.598949 ============ PULL DRAM RESETB DOWN ============
600 00:24:37.603537 ========== PULL DRAM RESETB DOWN end =========
601 00:24:37.607178 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
602 00:24:37.610257 ===================================
603 00:24:37.610334 LPDDR4 DRAM CONFIGURATION
604 00:24:37.613877 ===================================
605 00:24:37.617100 EX_ROW_EN[0] = 0x0
606 00:24:37.620571 EX_ROW_EN[1] = 0x0
607 00:24:37.620687 LP4Y_EN = 0x0
608 00:24:37.623769 WORK_FSP = 0x0
609 00:24:37.623845 WL = 0x2
610 00:24:37.627215 RL = 0x2
611 00:24:37.627292 BL = 0x2
612 00:24:37.630246 RPST = 0x0
613 00:24:37.630322 RD_PRE = 0x0
614 00:24:37.633886 WR_PRE = 0x1
615 00:24:37.633962 WR_PST = 0x0
616 00:24:37.636971 DBI_WR = 0x0
617 00:24:37.637049 DBI_RD = 0x0
618 00:24:37.640507 OTF = 0x1
619 00:24:37.643348 ===================================
620 00:24:37.646775 ===================================
621 00:24:37.646853 ANA top config
622 00:24:37.650269 ===================================
623 00:24:37.653687 DLL_ASYNC_EN = 0
624 00:24:37.656678 ALL_SLAVE_EN = 1
625 00:24:37.660096 NEW_RANK_MODE = 1
626 00:24:37.660174 DLL_IDLE_MODE = 1
627 00:24:37.663776 LP45_APHY_COMB_EN = 1
628 00:24:37.666757 TX_ODT_DIS = 1
629 00:24:37.670327 NEW_8X_MODE = 1
630 00:24:37.673384 ===================================
631 00:24:37.677243 ===================================
632 00:24:37.677321 data_rate = 1600
633 00:24:37.680340 CKR = 1
634 00:24:37.683919 DQ_P2S_RATIO = 8
635 00:24:37.686860 ===================================
636 00:24:37.690412 CA_P2S_RATIO = 8
637 00:24:37.693864 DQ_CA_OPEN = 0
638 00:24:37.696969 DQ_SEMI_OPEN = 0
639 00:24:37.697047 CA_SEMI_OPEN = 0
640 00:24:37.700589 CA_FULL_RATE = 0
641 00:24:37.703785 DQ_CKDIV4_EN = 1
642 00:24:37.707105 CA_CKDIV4_EN = 1
643 00:24:37.710271 CA_PREDIV_EN = 0
644 00:24:37.713813 PH8_DLY = 0
645 00:24:37.713890 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
646 00:24:37.717329 DQ_AAMCK_DIV = 4
647 00:24:37.720197 CA_AAMCK_DIV = 4
648 00:24:37.723859 CA_ADMCK_DIV = 4
649 00:24:37.727346 DQ_TRACK_CA_EN = 0
650 00:24:37.730183 CA_PICK = 800
651 00:24:37.730254 CA_MCKIO = 800
652 00:24:37.734096 MCKIO_SEMI = 0
653 00:24:37.736995 PLL_FREQ = 3068
654 00:24:37.740300 DQ_UI_PI_RATIO = 32
655 00:24:37.743872 CA_UI_PI_RATIO = 0
656 00:24:37.746958 ===================================
657 00:24:37.750556 ===================================
658 00:24:37.750654 memory_type:LPDDR4
659 00:24:37.753708 GP_NUM : 10
660 00:24:37.757167 SRAM_EN : 1
661 00:24:37.757244 MD32_EN : 0
662 00:24:37.760808 ===================================
663 00:24:37.764152 [ANA_INIT] >>>>>>>>>>>>>>
664 00:24:37.767215 <<<<<< [CONFIGURE PHASE]: ANA_TX
665 00:24:37.770968 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
666 00:24:37.773879 ===================================
667 00:24:37.777511 data_rate = 1600,PCW = 0X7600
668 00:24:37.780533 ===================================
669 00:24:37.784143 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
670 00:24:37.787685 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
671 00:24:37.794245 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
672 00:24:37.797197 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
673 00:24:37.800748 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
674 00:24:37.803997 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
675 00:24:37.807608 [ANA_INIT] flow start
676 00:24:37.810728 [ANA_INIT] PLL >>>>>>>>
677 00:24:37.810806 [ANA_INIT] PLL <<<<<<<<
678 00:24:37.813899 [ANA_INIT] MIDPI >>>>>>>>
679 00:24:37.817377 [ANA_INIT] MIDPI <<<<<<<<
680 00:24:37.817454 [ANA_INIT] DLL >>>>>>>>
681 00:24:37.821046 [ANA_INIT] flow end
682 00:24:37.824465 ============ LP4 DIFF to SE enter ============
683 00:24:37.830854 ============ LP4 DIFF to SE exit ============
684 00:24:37.830932 [ANA_INIT] <<<<<<<<<<<<<
685 00:24:37.834124 [Flow] Enable top DCM control >>>>>
686 00:24:37.837583 [Flow] Enable top DCM control <<<<<
687 00:24:37.840932 Enable DLL master slave shuffle
688 00:24:37.847573 ==============================================================
689 00:24:37.847651 Gating Mode config
690 00:24:37.854086 ==============================================================
691 00:24:37.857830 Config description:
692 00:24:37.864268 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
693 00:24:37.871042 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
694 00:24:37.877721 SELPH_MODE 0: By rank 1: By Phase
695 00:24:37.881172 ==============================================================
696 00:24:37.884063 GAT_TRACK_EN = 1
697 00:24:37.887614 RX_GATING_MODE = 2
698 00:24:37.890725 RX_GATING_TRACK_MODE = 2
699 00:24:37.894066 SELPH_MODE = 1
700 00:24:37.897640 PICG_EARLY_EN = 1
701 00:24:37.901033 VALID_LAT_VALUE = 1
702 00:24:37.907580 ==============================================================
703 00:24:37.910596 Enter into Gating configuration >>>>
704 00:24:37.914296 Exit from Gating configuration <<<<
705 00:24:37.917258 Enter into DVFS_PRE_config >>>>>
706 00:24:37.927527 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
707 00:24:37.930924 Exit from DVFS_PRE_config <<<<<
708 00:24:37.933924 Enter into PICG configuration >>>>
709 00:24:37.937599 Exit from PICG configuration <<<<
710 00:24:37.937677 [RX_INPUT] configuration >>>>>
711 00:24:37.940557 [RX_INPUT] configuration <<<<<
712 00:24:37.947211 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
713 00:24:37.950908 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
714 00:24:37.957433 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
715 00:24:37.964310 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
716 00:24:37.970936 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
717 00:24:37.977625 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
718 00:24:37.981220 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
719 00:24:37.984262 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
720 00:24:37.987691 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
721 00:24:37.994288 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
722 00:24:37.997909 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
723 00:24:38.001506 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
724 00:24:38.004549 ===================================
725 00:24:38.007997 LPDDR4 DRAM CONFIGURATION
726 00:24:38.011052 ===================================
727 00:24:38.014472 EX_ROW_EN[0] = 0x0
728 00:24:38.014549 EX_ROW_EN[1] = 0x0
729 00:24:38.018121 LP4Y_EN = 0x0
730 00:24:38.018197 WORK_FSP = 0x0
731 00:24:38.021007 WL = 0x2
732 00:24:38.021084 RL = 0x2
733 00:24:38.024579 BL = 0x2
734 00:24:38.024656 RPST = 0x0
735 00:24:38.027628 RD_PRE = 0x0
736 00:24:38.027705 WR_PRE = 0x1
737 00:24:38.031185 WR_PST = 0x0
738 00:24:38.031262 DBI_WR = 0x0
739 00:24:38.034549 DBI_RD = 0x0
740 00:24:38.034625 OTF = 0x1
741 00:24:38.037915 ===================================
742 00:24:38.041416 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
743 00:24:38.048107 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
744 00:24:38.051152 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
745 00:24:38.054737 ===================================
746 00:24:38.058270 LPDDR4 DRAM CONFIGURATION
747 00:24:38.062015 ===================================
748 00:24:38.062093 EX_ROW_EN[0] = 0x10
749 00:24:38.066328 EX_ROW_EN[1] = 0x0
750 00:24:38.066405 LP4Y_EN = 0x0
751 00:24:38.070064 WORK_FSP = 0x0
752 00:24:38.070141 WL = 0x2
753 00:24:38.070201 RL = 0x2
754 00:24:38.073569 BL = 0x2
755 00:24:38.073646 RPST = 0x0
756 00:24:38.077558 RD_PRE = 0x0
757 00:24:38.077635 WR_PRE = 0x1
758 00:24:38.081175 WR_PST = 0x0
759 00:24:38.081253 DBI_WR = 0x0
760 00:24:38.084675 DBI_RD = 0x0
761 00:24:38.084797 OTF = 0x1
762 00:24:38.088553 ===================================
763 00:24:38.096058 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
764 00:24:38.099425 nWR fixed to 40
765 00:24:38.099503 [ModeRegInit_LP4] CH0 RK0
766 00:24:38.102955 [ModeRegInit_LP4] CH0 RK1
767 00:24:38.105970 [ModeRegInit_LP4] CH1 RK0
768 00:24:38.106047 [ModeRegInit_LP4] CH1 RK1
769 00:24:38.109225 match AC timing 13
770 00:24:38.112447 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
771 00:24:38.115908 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
772 00:24:38.122480 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
773 00:24:38.125926 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
774 00:24:38.132598 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
775 00:24:38.132691 [EMI DOE] emi_dcm 0
776 00:24:38.139083 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
777 00:24:38.139160 ==
778 00:24:38.142800 Dram Type= 6, Freq= 0, CH_0, rank 0
779 00:24:38.145882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
780 00:24:38.145960 ==
781 00:24:38.149434 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
782 00:24:38.156187 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
783 00:24:38.165769 [CA 0] Center 38 (7~69) winsize 63
784 00:24:38.169461 [CA 1] Center 38 (7~69) winsize 63
785 00:24:38.172560 [CA 2] Center 35 (5~66) winsize 62
786 00:24:38.175989 [CA 3] Center 35 (4~66) winsize 63
787 00:24:38.179392 [CA 4] Center 35 (5~65) winsize 61
788 00:24:38.182773 [CA 5] Center 34 (3~65) winsize 63
789 00:24:38.182849
790 00:24:38.185947 [CmdBusTrainingLP45] Vref(ca) range 1: 34
791 00:24:38.186024
792 00:24:38.189446 [CATrainingPosCal] consider 1 rank data
793 00:24:38.192603 u2DelayCellTimex100 = 270/100 ps
794 00:24:38.195986 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
795 00:24:38.199300 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
796 00:24:38.206473 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
797 00:24:38.206551 CA3 delay=35 (4~66),Diff = 1 PI (7 cell)
798 00:24:38.210344 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
799 00:24:38.217018 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
800 00:24:38.217096
801 00:24:38.219963 CA PerBit enable=1, Macro0, CA PI delay=34
802 00:24:38.220040
803 00:24:38.223519 [CBTSetCACLKResult] CA Dly = 34
804 00:24:38.223596 CS Dly: 5 (0~36)
805 00:24:38.223655 ==
806 00:24:38.226552 Dram Type= 6, Freq= 0, CH_0, rank 1
807 00:24:38.230250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
808 00:24:38.230328 ==
809 00:24:38.236831 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
810 00:24:38.243874 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
811 00:24:38.252409 [CA 0] Center 38 (7~69) winsize 63
812 00:24:38.255471 [CA 1] Center 38 (7~69) winsize 63
813 00:24:38.258936 [CA 2] Center 36 (6~67) winsize 62
814 00:24:38.262650 [CA 3] Center 36 (5~67) winsize 63
815 00:24:38.265740 [CA 4] Center 35 (5~66) winsize 62
816 00:24:38.269294 [CA 5] Center 34 (4~65) winsize 62
817 00:24:38.269371
818 00:24:38.272361 [CmdBusTrainingLP45] Vref(ca) range 1: 34
819 00:24:38.272437
820 00:24:38.275851 [CATrainingPosCal] consider 2 rank data
821 00:24:38.279155 u2DelayCellTimex100 = 270/100 ps
822 00:24:38.282400 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
823 00:24:38.285844 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
824 00:24:38.292537 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
825 00:24:38.295588 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
826 00:24:38.299089 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
827 00:24:38.302740 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
828 00:24:38.302817
829 00:24:38.305778 CA PerBit enable=1, Macro0, CA PI delay=34
830 00:24:38.305855
831 00:24:38.309289 [CBTSetCACLKResult] CA Dly = 34
832 00:24:38.309366 CS Dly: 6 (0~38)
833 00:24:38.309425
834 00:24:38.312577 ----->DramcWriteLeveling(PI) begin...
835 00:24:38.312655 ==
836 00:24:38.315808 Dram Type= 6, Freq= 0, CH_0, rank 0
837 00:24:38.322463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
838 00:24:38.322540 ==
839 00:24:38.325608 Write leveling (Byte 0): 30 => 30
840 00:24:38.329071 Write leveling (Byte 1): 28 => 28
841 00:24:38.329149 DramcWriteLeveling(PI) end<-----
842 00:24:38.332585
843 00:24:38.332662 ==
844 00:24:38.336193 Dram Type= 6, Freq= 0, CH_0, rank 0
845 00:24:38.339255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
846 00:24:38.339332 ==
847 00:24:38.342723 [Gating] SW mode calibration
848 00:24:38.349168 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
849 00:24:38.352636 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
850 00:24:38.359224 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
851 00:24:38.362889 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
852 00:24:38.365905 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
853 00:24:38.372595 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
854 00:24:38.376078 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 00:24:38.379233 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 00:24:38.386029 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 00:24:38.389313 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 00:24:38.392856 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 00:24:38.396141 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 00:24:38.402964 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 00:24:38.405977 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 00:24:38.409430 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 00:24:38.416064 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 00:24:38.419402 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 00:24:38.422825 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 00:24:38.429472 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
867 00:24:38.433288 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
868 00:24:38.436436 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
869 00:24:38.442980 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 00:24:38.446621 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 00:24:38.449953 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 00:24:38.456331 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 00:24:38.459938 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 00:24:38.463136 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 00:24:38.466704 0 9 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
876 00:24:38.473317 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
877 00:24:38.476349 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
878 00:24:38.479831 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
879 00:24:38.486517 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
880 00:24:38.489866 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
881 00:24:38.493313 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 00:24:38.499744 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
883 00:24:38.502996 0 10 4 | B1->B0 | 3434 3030 | 1 0 | (1 1) (1 1)
884 00:24:38.506686 0 10 8 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
885 00:24:38.513271 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
886 00:24:38.516879 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
887 00:24:38.519975 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
888 00:24:38.527010 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 00:24:38.530292 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 00:24:38.533182 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 00:24:38.536593 0 11 4 | B1->B0 | 2323 3333 | 0 1 | (0 0) (0 0)
892 00:24:38.543348 0 11 8 | B1->B0 | 2a2a 4646 | 1 0 | (0 0) (0 0)
893 00:24:38.546831 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
894 00:24:38.549780 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
895 00:24:38.556738 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
896 00:24:38.560207 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
897 00:24:38.563316 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 00:24:38.570317 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 00:24:38.573409 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
900 00:24:38.576803 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
901 00:24:38.583399 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 00:24:38.586918 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 00:24:38.590427 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 00:24:38.596966 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 00:24:38.600088 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 00:24:38.603463 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 00:24:38.606985 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 00:24:38.613310 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 00:24:38.616769 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 00:24:38.620327 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 00:24:38.626935 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 00:24:38.630330 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 00:24:38.633689 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 00:24:38.640344 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 00:24:38.643710 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
916 00:24:38.647271 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
917 00:24:38.651043 Total UI for P1: 0, mck2ui 16
918 00:24:38.653899 best dqsien dly found for B0: ( 0, 14, 4)
919 00:24:38.657476 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
920 00:24:38.660980 Total UI for P1: 0, mck2ui 16
921 00:24:38.663975 best dqsien dly found for B1: ( 0, 14, 8)
922 00:24:38.667542 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
923 00:24:38.670875 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
924 00:24:38.670969
925 00:24:38.677787 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
926 00:24:38.681299 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
927 00:24:38.681376 [Gating] SW calibration Done
928 00:24:38.684645 ==
929 00:24:38.687642 Dram Type= 6, Freq= 0, CH_0, rank 0
930 00:24:38.691331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
931 00:24:38.691425 ==
932 00:24:38.691516 RX Vref Scan: 0
933 00:24:38.691599
934 00:24:38.694458 RX Vref 0 -> 0, step: 1
935 00:24:38.694548
936 00:24:38.697852 RX Delay -130 -> 252, step: 16
937 00:24:38.701017 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
938 00:24:38.704312 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
939 00:24:38.710988 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
940 00:24:38.714398 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
941 00:24:38.717597 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
942 00:24:38.721136 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
943 00:24:38.724185 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
944 00:24:38.731398 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
945 00:24:38.734357 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
946 00:24:38.738080 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
947 00:24:38.741108 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
948 00:24:38.744561 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
949 00:24:38.751238 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
950 00:24:38.754586 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
951 00:24:38.758064 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
952 00:24:38.761201 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
953 00:24:38.761301 ==
954 00:24:38.764682 Dram Type= 6, Freq= 0, CH_0, rank 0
955 00:24:38.767560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
956 00:24:38.771132 ==
957 00:24:38.771229 DQS Delay:
958 00:24:38.771324 DQS0 = 0, DQS1 = 0
959 00:24:38.774261 DQM Delay:
960 00:24:38.774361 DQM0 = 89, DQM1 = 79
961 00:24:38.777772 DQ Delay:
962 00:24:38.777864 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
963 00:24:38.781414 DQ4 =85, DQ5 =77, DQ6 =101, DQ7 =101
964 00:24:38.784514 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
965 00:24:38.787724 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =85
966 00:24:38.787824
967 00:24:38.791152
968 00:24:38.791253 ==
969 00:24:38.794662 Dram Type= 6, Freq= 0, CH_0, rank 0
970 00:24:38.797771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
971 00:24:38.797849 ==
972 00:24:38.797908
973 00:24:38.797962
974 00:24:38.801431 TX Vref Scan disable
975 00:24:38.801513 == TX Byte 0 ==
976 00:24:38.807874 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
977 00:24:38.811270 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
978 00:24:38.811378 == TX Byte 1 ==
979 00:24:38.818003 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
980 00:24:38.821439 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
981 00:24:38.821515 ==
982 00:24:38.825071 Dram Type= 6, Freq= 0, CH_0, rank 0
983 00:24:38.828159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
984 00:24:38.828265 ==
985 00:24:38.841359 TX Vref=22, minBit 6, minWin=27, winSum=445
986 00:24:38.844889 TX Vref=24, minBit 8, minWin=27, winSum=446
987 00:24:38.848228 TX Vref=26, minBit 4, minWin=28, winSum=454
988 00:24:38.851657 TX Vref=28, minBit 8, minWin=27, winSum=455
989 00:24:38.854933 TX Vref=30, minBit 8, minWin=28, winSum=459
990 00:24:38.858422 TX Vref=32, minBit 1, minWin=28, winSum=455
991 00:24:38.865182 [TxChooseVref] Worse bit 8, Min win 28, Win sum 459, Final Vref 30
992 00:24:38.865252
993 00:24:38.868095 Final TX Range 1 Vref 30
994 00:24:38.868184
995 00:24:38.868271 ==
996 00:24:38.871472 Dram Type= 6, Freq= 0, CH_0, rank 0
997 00:24:38.874802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
998 00:24:38.874893 ==
999 00:24:38.874975
1000 00:24:38.875062
1001 00:24:38.878316 TX Vref Scan disable
1002 00:24:38.881875 == TX Byte 0 ==
1003 00:24:38.884878 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1004 00:24:38.888520 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1005 00:24:38.891929 == TX Byte 1 ==
1006 00:24:38.894861 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1007 00:24:38.898460 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1008 00:24:38.898549
1009 00:24:38.902154 [DATLAT]
1010 00:24:38.902245 Freq=800, CH0 RK0
1011 00:24:38.902326
1012 00:24:38.905220 DATLAT Default: 0xa
1013 00:24:38.905294 0, 0xFFFF, sum = 0
1014 00:24:38.908170 1, 0xFFFF, sum = 0
1015 00:24:38.908266 2, 0xFFFF, sum = 0
1016 00:24:38.911815 3, 0xFFFF, sum = 0
1017 00:24:38.911906 4, 0xFFFF, sum = 0
1018 00:24:38.915338 5, 0xFFFF, sum = 0
1019 00:24:38.915406 6, 0xFFFF, sum = 0
1020 00:24:38.918399 7, 0xFFFF, sum = 0
1021 00:24:38.918479 8, 0xFFFF, sum = 0
1022 00:24:38.921804 9, 0x0, sum = 1
1023 00:24:38.921899 10, 0x0, sum = 2
1024 00:24:38.925237 11, 0x0, sum = 3
1025 00:24:38.925304 12, 0x0, sum = 4
1026 00:24:38.928614 best_step = 10
1027 00:24:38.928701
1028 00:24:38.928765 ==
1029 00:24:38.931883 Dram Type= 6, Freq= 0, CH_0, rank 0
1030 00:24:38.935279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1031 00:24:38.935349 ==
1032 00:24:38.935405 RX Vref Scan: 1
1033 00:24:38.938745
1034 00:24:38.938834 Set Vref Range= 32 -> 127
1035 00:24:38.938923
1036 00:24:38.942250 RX Vref 32 -> 127, step: 1
1037 00:24:38.942315
1038 00:24:38.945380 RX Delay -95 -> 252, step: 8
1039 00:24:38.945445
1040 00:24:38.948913 Set Vref, RX VrefLevel [Byte0]: 32
1041 00:24:38.951968 [Byte1]: 32
1042 00:24:38.952033
1043 00:24:38.955772 Set Vref, RX VrefLevel [Byte0]: 33
1044 00:24:38.958875 [Byte1]: 33
1045 00:24:38.958966
1046 00:24:38.962163 Set Vref, RX VrefLevel [Byte0]: 34
1047 00:24:38.965800 [Byte1]: 34
1048 00:24:38.969569
1049 00:24:38.969658 Set Vref, RX VrefLevel [Byte0]: 35
1050 00:24:38.972561 [Byte1]: 35
1051 00:24:38.976677
1052 00:24:38.976807 Set Vref, RX VrefLevel [Byte0]: 36
1053 00:24:38.980314 [Byte1]: 36
1054 00:24:38.984396
1055 00:24:38.984492 Set Vref, RX VrefLevel [Byte0]: 37
1056 00:24:38.987818 [Byte1]: 37
1057 00:24:38.992531
1058 00:24:38.992626 Set Vref, RX VrefLevel [Byte0]: 38
1059 00:24:38.995305 [Byte1]: 38
1060 00:24:38.999847
1061 00:24:38.999936 Set Vref, RX VrefLevel [Byte0]: 39
1062 00:24:39.003027 [Byte1]: 39
1063 00:24:39.007026
1064 00:24:39.007123 Set Vref, RX VrefLevel [Byte0]: 40
1065 00:24:39.010512 [Byte1]: 40
1066 00:24:39.015192
1067 00:24:39.015282 Set Vref, RX VrefLevel [Byte0]: 41
1068 00:24:39.018238 [Byte1]: 41
1069 00:24:39.022648
1070 00:24:39.022712 Set Vref, RX VrefLevel [Byte0]: 42
1071 00:24:39.025876 [Byte1]: 42
1072 00:24:39.029861
1073 00:24:39.029931 Set Vref, RX VrefLevel [Byte0]: 43
1074 00:24:39.033102 [Byte1]: 43
1075 00:24:39.037703
1076 00:24:39.037794 Set Vref, RX VrefLevel [Byte0]: 44
1077 00:24:39.040929 [Byte1]: 44
1078 00:24:39.045303
1079 00:24:39.045372 Set Vref, RX VrefLevel [Byte0]: 45
1080 00:24:39.048337 [Byte1]: 45
1081 00:24:39.052876
1082 00:24:39.052956 Set Vref, RX VrefLevel [Byte0]: 46
1083 00:24:39.055959 [Byte1]: 46
1084 00:24:39.060525
1085 00:24:39.060606 Set Vref, RX VrefLevel [Byte0]: 47
1086 00:24:39.063880 [Byte1]: 47
1087 00:24:39.068154
1088 00:24:39.068243 Set Vref, RX VrefLevel [Byte0]: 48
1089 00:24:39.071199 [Byte1]: 48
1090 00:24:39.075696
1091 00:24:39.075792 Set Vref, RX VrefLevel [Byte0]: 49
1092 00:24:39.079060 [Byte1]: 49
1093 00:24:39.083259
1094 00:24:39.083349 Set Vref, RX VrefLevel [Byte0]: 50
1095 00:24:39.086316 [Byte1]: 50
1096 00:24:39.091013
1097 00:24:39.091079 Set Vref, RX VrefLevel [Byte0]: 51
1098 00:24:39.094092 [Byte1]: 51
1099 00:24:39.098446
1100 00:24:39.098542 Set Vref, RX VrefLevel [Byte0]: 52
1101 00:24:39.101546 [Byte1]: 52
1102 00:24:39.105857
1103 00:24:39.105952 Set Vref, RX VrefLevel [Byte0]: 53
1104 00:24:39.109208 [Byte1]: 53
1105 00:24:39.113954
1106 00:24:39.114046 Set Vref, RX VrefLevel [Byte0]: 54
1107 00:24:39.116871 [Byte1]: 54
1108 00:24:39.121127
1109 00:24:39.121190 Set Vref, RX VrefLevel [Byte0]: 55
1110 00:24:39.124545 [Byte1]: 55
1111 00:24:39.128884
1112 00:24:39.128964 Set Vref, RX VrefLevel [Byte0]: 56
1113 00:24:39.131993 [Byte1]: 56
1114 00:24:39.136461
1115 00:24:39.136557 Set Vref, RX VrefLevel [Byte0]: 57
1116 00:24:39.139496 [Byte1]: 57
1117 00:24:39.143918
1118 00:24:39.144009 Set Vref, RX VrefLevel [Byte0]: 58
1119 00:24:39.147363 [Byte1]: 58
1120 00:24:39.151477
1121 00:24:39.151550 Set Vref, RX VrefLevel [Byte0]: 59
1122 00:24:39.155096 [Byte1]: 59
1123 00:24:39.159265
1124 00:24:39.159355 Set Vref, RX VrefLevel [Byte0]: 60
1125 00:24:39.162228 [Byte1]: 60
1126 00:24:39.166732
1127 00:24:39.166821 Set Vref, RX VrefLevel [Byte0]: 61
1128 00:24:39.170000 [Byte1]: 61
1129 00:24:39.174466
1130 00:24:39.174559 Set Vref, RX VrefLevel [Byte0]: 62
1131 00:24:39.177944 [Byte1]: 62
1132 00:24:39.181852
1133 00:24:39.181932 Set Vref, RX VrefLevel [Byte0]: 63
1134 00:24:39.185243 [Byte1]: 63
1135 00:24:39.189654
1136 00:24:39.189730 Set Vref, RX VrefLevel [Byte0]: 64
1137 00:24:39.193151 [Byte1]: 64
1138 00:24:39.197256
1139 00:24:39.197333 Set Vref, RX VrefLevel [Byte0]: 65
1140 00:24:39.200227 [Byte1]: 65
1141 00:24:39.204788
1142 00:24:39.204864 Set Vref, RX VrefLevel [Byte0]: 66
1143 00:24:39.207876 [Byte1]: 66
1144 00:24:39.212384
1145 00:24:39.212462 Set Vref, RX VrefLevel [Byte0]: 67
1146 00:24:39.215997 [Byte1]: 67
1147 00:24:39.220108
1148 00:24:39.220184 Set Vref, RX VrefLevel [Byte0]: 68
1149 00:24:39.226357 [Byte1]: 68
1150 00:24:39.226433
1151 00:24:39.229703 Set Vref, RX VrefLevel [Byte0]: 69
1152 00:24:39.233330 [Byte1]: 69
1153 00:24:39.233407
1154 00:24:39.236595 Set Vref, RX VrefLevel [Byte0]: 70
1155 00:24:39.239867 [Byte1]: 70
1156 00:24:39.239943
1157 00:24:39.243180 Set Vref, RX VrefLevel [Byte0]: 71
1158 00:24:39.246704 [Byte1]: 71
1159 00:24:39.250308
1160 00:24:39.250384 Set Vref, RX VrefLevel [Byte0]: 72
1161 00:24:39.253731 [Byte1]: 72
1162 00:24:39.257815
1163 00:24:39.257890 Set Vref, RX VrefLevel [Byte0]: 73
1164 00:24:39.261215 [Byte1]: 73
1165 00:24:39.265345
1166 00:24:39.265420 Set Vref, RX VrefLevel [Byte0]: 74
1167 00:24:39.268665 [Byte1]: 74
1168 00:24:39.273266
1169 00:24:39.273342 Set Vref, RX VrefLevel [Byte0]: 75
1170 00:24:39.276463 [Byte1]: 75
1171 00:24:39.280638
1172 00:24:39.280753 Final RX Vref Byte 0 = 62 to rank0
1173 00:24:39.284099 Final RX Vref Byte 1 = 54 to rank0
1174 00:24:39.287519 Final RX Vref Byte 0 = 62 to rank1
1175 00:24:39.290618 Final RX Vref Byte 1 = 54 to rank1==
1176 00:24:39.294286 Dram Type= 6, Freq= 0, CH_0, rank 0
1177 00:24:39.300589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1178 00:24:39.300665 ==
1179 00:24:39.300769 DQS Delay:
1180 00:24:39.300826 DQS0 = 0, DQS1 = 0
1181 00:24:39.304200 DQM Delay:
1182 00:24:39.304276 DQM0 = 93, DQM1 = 81
1183 00:24:39.307254 DQ Delay:
1184 00:24:39.310814 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1185 00:24:39.314019 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1186 00:24:39.317522 DQ8 =76, DQ9 =68, DQ10 =80, DQ11 =76
1187 00:24:39.320562 DQ12 =88, DQ13 =84, DQ14 =92, DQ15 =88
1188 00:24:39.320637
1189 00:24:39.320696
1190 00:24:39.327687 [DQSOSCAuto] RK0, (LSB)MR18= 0x403b, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
1191 00:24:39.330666 CH0 RK0: MR19=606, MR18=403B
1192 00:24:39.337364 CH0_RK0: MR19=0x606, MR18=0x403B, DQSOSC=393, MR23=63, INC=95, DEC=63
1193 00:24:39.337442
1194 00:24:39.340952 ----->DramcWriteLeveling(PI) begin...
1195 00:24:39.341030 ==
1196 00:24:39.344405 Dram Type= 6, Freq= 0, CH_0, rank 1
1197 00:24:39.347303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1198 00:24:39.347380 ==
1199 00:24:39.350867 Write leveling (Byte 0): 31 => 31
1200 00:24:39.354366 Write leveling (Byte 1): 29 => 29
1201 00:24:39.357503 DramcWriteLeveling(PI) end<-----
1202 00:24:39.357580
1203 00:24:39.357640 ==
1204 00:24:39.360877 Dram Type= 6, Freq= 0, CH_0, rank 1
1205 00:24:39.364176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1206 00:24:39.364254 ==
1207 00:24:39.367247 [Gating] SW mode calibration
1208 00:24:39.374289 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1209 00:24:39.380876 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1210 00:24:39.384292 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1211 00:24:39.387535 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1212 00:24:39.394055 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1213 00:24:39.397533 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 00:24:39.400948 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 00:24:39.407637 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 00:24:39.410911 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 00:24:39.414034 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 00:24:39.420915 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 00:24:39.424042 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 00:24:39.468326 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 00:24:39.468587 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 00:24:39.468660 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 00:24:39.468741 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 00:24:39.469361 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 00:24:39.469620 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 00:24:39.469684 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 00:24:39.469751 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1228 00:24:39.469808 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 00:24:39.469871 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 00:24:39.479425 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 00:24:39.479779 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 00:24:39.479856 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 00:24:39.486177 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 00:24:39.489719 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 00:24:39.492482 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1236 00:24:39.499250 0 9 8 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
1237 00:24:39.502882 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1238 00:24:39.505852 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1239 00:24:39.512941 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1240 00:24:39.516367 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1241 00:24:39.519243 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1242 00:24:39.526150 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1243 00:24:39.529345 0 10 4 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (1 0)
1244 00:24:39.532932 0 10 8 | B1->B0 | 2929 2323 | 0 0 | (1 1) (0 0)
1245 00:24:39.539334 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 00:24:39.542857 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 00:24:39.546533 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 00:24:39.549641 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 00:24:39.556169 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 00:24:39.559788 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 00:24:39.563163 0 11 4 | B1->B0 | 2929 3737 | 0 0 | (0 0) (1 1)
1252 00:24:39.569513 0 11 8 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
1253 00:24:39.572972 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1254 00:24:39.576211 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1255 00:24:39.582987 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1256 00:24:39.586345 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1257 00:24:39.589872 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1258 00:24:39.596673 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1259 00:24:39.599491 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1260 00:24:39.603188 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1261 00:24:39.609502 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1262 00:24:39.613010 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1263 00:24:39.616527 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1264 00:24:39.622884 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1265 00:24:39.626351 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 00:24:39.629640 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 00:24:39.633061 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 00:24:39.639677 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 00:24:39.643250 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 00:24:39.646320 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 00:24:39.653405 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 00:24:39.656435 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 00:24:39.660033 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 00:24:39.666439 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 00:24:39.669681 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1276 00:24:39.673107 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1277 00:24:39.676233 Total UI for P1: 0, mck2ui 16
1278 00:24:39.679624 best dqsien dly found for B0: ( 0, 14, 4)
1279 00:24:39.683020 Total UI for P1: 0, mck2ui 16
1280 00:24:39.686281 best dqsien dly found for B1: ( 0, 14, 4)
1281 00:24:39.689799 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1282 00:24:39.693220 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1283 00:24:39.693297
1284 00:24:39.696621 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1285 00:24:39.703134 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1286 00:24:39.703212 [Gating] SW calibration Done
1287 00:24:39.703272 ==
1288 00:24:39.706674 Dram Type= 6, Freq= 0, CH_0, rank 1
1289 00:24:39.713101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1290 00:24:39.713179 ==
1291 00:24:39.713239 RX Vref Scan: 0
1292 00:24:39.713295
1293 00:24:39.716640 RX Vref 0 -> 0, step: 1
1294 00:24:39.716945
1295 00:24:39.720176 RX Delay -130 -> 252, step: 16
1296 00:24:39.723267 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1297 00:24:39.726803 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1298 00:24:39.730080 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1299 00:24:39.736976 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1300 00:24:39.740291 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1301 00:24:39.743343 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1302 00:24:39.746833 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1303 00:24:39.749975 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1304 00:24:39.753447 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1305 00:24:39.760094 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
1306 00:24:39.763714 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1307 00:24:39.766616 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1308 00:24:39.770214 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1309 00:24:39.776619 iDelay=222, Bit 13, Center 77 (-34 ~ 189) 224
1310 00:24:39.779682 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1311 00:24:39.783321 iDelay=222, Bit 15, Center 77 (-34 ~ 189) 224
1312 00:24:39.783436 ==
1313 00:24:39.786691 Dram Type= 6, Freq= 0, CH_0, rank 1
1314 00:24:39.790246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1315 00:24:39.790355 ==
1316 00:24:39.793290 DQS Delay:
1317 00:24:39.793384 DQS0 = 0, DQS1 = 0
1318 00:24:39.796475 DQM Delay:
1319 00:24:39.796585 DQM0 = 88, DQM1 = 78
1320 00:24:39.796673 DQ Delay:
1321 00:24:39.799940 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =77
1322 00:24:39.803450 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =101
1323 00:24:39.806469 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
1324 00:24:39.809956 DQ12 =85, DQ13 =77, DQ14 =85, DQ15 =77
1325 00:24:39.810048
1326 00:24:39.810138
1327 00:24:39.813045 ==
1328 00:24:39.813122 Dram Type= 6, Freq= 0, CH_0, rank 1
1329 00:24:39.819672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1330 00:24:39.819780 ==
1331 00:24:39.819849
1332 00:24:39.819906
1333 00:24:39.823247 TX Vref Scan disable
1334 00:24:39.823346 == TX Byte 0 ==
1335 00:24:39.826786 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1336 00:24:39.833043 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1337 00:24:39.833117 == TX Byte 1 ==
1338 00:24:39.836790 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1339 00:24:39.843202 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1340 00:24:39.843281 ==
1341 00:24:39.846896 Dram Type= 6, Freq= 0, CH_0, rank 1
1342 00:24:39.849962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1343 00:24:39.850105 ==
1344 00:24:39.863148 TX Vref=22, minBit 8, minWin=27, winSum=447
1345 00:24:39.866615 TX Vref=24, minBit 8, minWin=27, winSum=447
1346 00:24:39.869917 TX Vref=26, minBit 8, minWin=27, winSum=453
1347 00:24:39.873046 TX Vref=28, minBit 8, minWin=27, winSum=454
1348 00:24:39.876627 TX Vref=30, minBit 8, minWin=27, winSum=456
1349 00:24:39.879646 TX Vref=32, minBit 8, minWin=28, winSum=457
1350 00:24:39.886344 [TxChooseVref] Worse bit 8, Min win 28, Win sum 457, Final Vref 32
1351 00:24:39.886431
1352 00:24:39.890107 Final TX Range 1 Vref 32
1353 00:24:39.890189
1354 00:24:39.890278 ==
1355 00:24:39.893282 Dram Type= 6, Freq= 0, CH_0, rank 1
1356 00:24:39.896888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1357 00:24:39.896996 ==
1358 00:24:39.897094
1359 00:24:39.897186
1360 00:24:39.900024 TX Vref Scan disable
1361 00:24:39.903227 == TX Byte 0 ==
1362 00:24:39.906642 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1363 00:24:39.910247 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1364 00:24:39.913348 == TX Byte 1 ==
1365 00:24:39.916523 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1366 00:24:39.920061 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1367 00:24:39.920141
1368 00:24:39.923644 [DATLAT]
1369 00:24:39.923722 Freq=800, CH0 RK1
1370 00:24:39.923783
1371 00:24:39.926579 DATLAT Default: 0xa
1372 00:24:39.926657 0, 0xFFFF, sum = 0
1373 00:24:39.930328 1, 0xFFFF, sum = 0
1374 00:24:39.930412 2, 0xFFFF, sum = 0
1375 00:24:39.933374 3, 0xFFFF, sum = 0
1376 00:24:39.933459 4, 0xFFFF, sum = 0
1377 00:24:39.937032 5, 0xFFFF, sum = 0
1378 00:24:39.937120 6, 0xFFFF, sum = 0
1379 00:24:39.939956 7, 0xFFFF, sum = 0
1380 00:24:39.940041 8, 0xFFFF, sum = 0
1381 00:24:39.943343 9, 0x0, sum = 1
1382 00:24:39.943429 10, 0x0, sum = 2
1383 00:24:39.946942 11, 0x0, sum = 3
1384 00:24:39.947022 12, 0x0, sum = 4
1385 00:24:39.949835 best_step = 10
1386 00:24:39.949925
1387 00:24:39.949993 ==
1388 00:24:39.953550 Dram Type= 6, Freq= 0, CH_0, rank 1
1389 00:24:39.956620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1390 00:24:39.956698 ==
1391 00:24:39.960253 RX Vref Scan: 0
1392 00:24:39.960330
1393 00:24:39.960390 RX Vref 0 -> 0, step: 1
1394 00:24:39.960446
1395 00:24:39.963852 RX Delay -79 -> 252, step: 8
1396 00:24:39.970420 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1397 00:24:39.973488 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1398 00:24:39.977147 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1399 00:24:39.980334 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1400 00:24:39.983487 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1401 00:24:39.986968 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1402 00:24:39.993872 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1403 00:24:39.997308 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1404 00:24:40.000130 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1405 00:24:40.003706 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1406 00:24:40.007318 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1407 00:24:40.013653 iDelay=209, Bit 11, Center 80 (-23 ~ 184) 208
1408 00:24:40.017008 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
1409 00:24:40.020346 iDelay=209, Bit 13, Center 88 (-15 ~ 192) 208
1410 00:24:40.024005 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1411 00:24:40.027459 iDelay=209, Bit 15, Center 88 (-15 ~ 192) 208
1412 00:24:40.030563 ==
1413 00:24:40.030639 Dram Type= 6, Freq= 0, CH_0, rank 1
1414 00:24:40.036879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1415 00:24:40.037001 ==
1416 00:24:40.037087 DQS Delay:
1417 00:24:40.040595 DQS0 = 0, DQS1 = 0
1418 00:24:40.040672 DQM Delay:
1419 00:24:40.043716 DQM0 = 90, DQM1 = 83
1420 00:24:40.043793 DQ Delay:
1421 00:24:40.047112 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =84
1422 00:24:40.050294 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1423 00:24:40.053766 DQ8 =76, DQ9 =68, DQ10 =84, DQ11 =80
1424 00:24:40.057477 DQ12 =88, DQ13 =88, DQ14 =92, DQ15 =88
1425 00:24:40.057553
1426 00:24:40.057612
1427 00:24:40.064017 [DQSOSCAuto] RK1, (LSB)MR18= 0x441e, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 392 ps
1428 00:24:40.067033 CH0 RK1: MR19=606, MR18=441E
1429 00:24:40.073772 CH0_RK1: MR19=0x606, MR18=0x441E, DQSOSC=392, MR23=63, INC=96, DEC=64
1430 00:24:40.077283 [RxdqsGatingPostProcess] freq 800
1431 00:24:40.080888 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1432 00:24:40.083809 Pre-setting of DQS Precalculation
1433 00:24:40.090900 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1434 00:24:40.090977 ==
1435 00:24:40.094062 Dram Type= 6, Freq= 0, CH_1, rank 0
1436 00:24:40.097031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1437 00:24:40.097108 ==
1438 00:24:40.103746 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1439 00:24:40.110545 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1440 00:24:40.118109 [CA 0] Center 36 (6~67) winsize 62
1441 00:24:40.121527 [CA 1] Center 37 (6~68) winsize 63
1442 00:24:40.125008 [CA 2] Center 34 (4~65) winsize 62
1443 00:24:40.128378 [CA 3] Center 34 (3~65) winsize 63
1444 00:24:40.131551 [CA 4] Center 34 (4~65) winsize 62
1445 00:24:40.135029 [CA 5] Center 34 (3~65) winsize 63
1446 00:24:40.135106
1447 00:24:40.138162 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1448 00:24:40.138238
1449 00:24:40.141754 [CATrainingPosCal] consider 1 rank data
1450 00:24:40.145219 u2DelayCellTimex100 = 270/100 ps
1451 00:24:40.148252 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1452 00:24:40.151672 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1453 00:24:40.154885 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1454 00:24:40.161824 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1455 00:24:40.164915 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1456 00:24:40.168429 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1457 00:24:40.168505
1458 00:24:40.171930 CA PerBit enable=1, Macro0, CA PI delay=34
1459 00:24:40.172007
1460 00:24:40.175020 [CBTSetCACLKResult] CA Dly = 34
1461 00:24:40.175096 CS Dly: 5 (0~36)
1462 00:24:40.175155 ==
1463 00:24:40.178477 Dram Type= 6, Freq= 0, CH_1, rank 1
1464 00:24:40.185166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1465 00:24:40.185243 ==
1466 00:24:40.188252 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1467 00:24:40.195379 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1468 00:24:40.204800 [CA 0] Center 36 (6~67) winsize 62
1469 00:24:40.207691 [CA 1] Center 37 (6~68) winsize 63
1470 00:24:40.211272 [CA 2] Center 35 (4~66) winsize 63
1471 00:24:40.214209 [CA 3] Center 34 (4~65) winsize 62
1472 00:24:40.217553 [CA 4] Center 34 (4~65) winsize 62
1473 00:24:40.221006 [CA 5] Center 34 (4~65) winsize 62
1474 00:24:40.221082
1475 00:24:40.224335 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1476 00:24:40.224411
1477 00:24:40.227525 [CATrainingPosCal] consider 2 rank data
1478 00:24:40.231002 u2DelayCellTimex100 = 270/100 ps
1479 00:24:40.234234 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1480 00:24:40.237555 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1481 00:24:40.244402 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1482 00:24:40.247601 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1483 00:24:40.250915 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1484 00:24:40.254561 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1485 00:24:40.254637
1486 00:24:40.257947 CA PerBit enable=1, Macro0, CA PI delay=34
1487 00:24:40.258023
1488 00:24:40.261383 [CBTSetCACLKResult] CA Dly = 34
1489 00:24:40.261461 CS Dly: 6 (0~38)
1490 00:24:40.261521
1491 00:24:40.264664 ----->DramcWriteLeveling(PI) begin...
1492 00:24:40.264747 ==
1493 00:24:40.267675 Dram Type= 6, Freq= 0, CH_1, rank 0
1494 00:24:40.274502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1495 00:24:40.274578 ==
1496 00:24:40.277933 Write leveling (Byte 0): 26 => 26
1497 00:24:40.281025 Write leveling (Byte 1): 30 => 30
1498 00:24:40.281100 DramcWriteLeveling(PI) end<-----
1499 00:24:40.284519
1500 00:24:40.284594 ==
1501 00:24:40.287566 Dram Type= 6, Freq= 0, CH_1, rank 0
1502 00:24:40.291107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1503 00:24:40.291183 ==
1504 00:24:40.294733 [Gating] SW mode calibration
1505 00:24:40.301333 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1506 00:24:40.304521 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1507 00:24:40.310986 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1508 00:24:40.314532 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1509 00:24:40.317994 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 00:24:40.324312 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 00:24:40.328015 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 00:24:40.331217 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 00:24:40.337916 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 00:24:40.341394 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 00:24:40.344612 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 00:24:40.350970 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 00:24:40.354665 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 00:24:40.357984 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 00:24:40.361410 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 00:24:40.367940 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 00:24:40.371170 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 00:24:40.374904 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1523 00:24:40.381386 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1524 00:24:40.384960 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1525 00:24:40.388506 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1526 00:24:40.395235 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 00:24:40.398201 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 00:24:40.401906 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 00:24:40.407992 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 00:24:40.411554 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 00:24:40.415107 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 00:24:40.421533 0 9 4 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
1533 00:24:40.424952 0 9 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1534 00:24:40.428306 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1535 00:24:40.431580 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1536 00:24:40.438543 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1537 00:24:40.442067 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1538 00:24:40.444971 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1539 00:24:40.451833 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1540 00:24:40.455390 0 10 4 | B1->B0 | 2f2f 2e2e | 0 0 | (0 0) (0 0)
1541 00:24:40.458481 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 00:24:40.465072 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 00:24:40.468579 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 00:24:40.472046 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 00:24:40.478642 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 00:24:40.482175 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 00:24:40.485371 0 11 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1548 00:24:40.488643 0 11 4 | B1->B0 | 3131 3d3d | 1 0 | (0 0) (0 0)
1549 00:24:40.495390 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1550 00:24:40.498826 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1551 00:24:40.501856 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1552 00:24:40.508553 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1553 00:24:40.512120 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1554 00:24:40.515163 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1555 00:24:40.521713 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1556 00:24:40.525270 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1557 00:24:40.528710 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1558 00:24:40.535707 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1559 00:24:40.538790 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1560 00:24:40.542139 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1561 00:24:40.548889 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1562 00:24:40.551852 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 00:24:40.555314 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 00:24:40.562210 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 00:24:40.565301 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 00:24:40.568675 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 00:24:40.575423 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 00:24:40.578821 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 00:24:40.582048 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 00:24:40.585197 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 00:24:40.591880 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 00:24:40.595219 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1573 00:24:40.598934 Total UI for P1: 0, mck2ui 16
1574 00:24:40.601850 best dqsien dly found for B0: ( 0, 14, 2)
1575 00:24:40.605355 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1576 00:24:40.608575 Total UI for P1: 0, mck2ui 16
1577 00:24:40.612265 best dqsien dly found for B1: ( 0, 14, 4)
1578 00:24:40.615711 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1579 00:24:40.618825 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1580 00:24:40.618902
1581 00:24:40.625342 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1582 00:24:40.628960 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1583 00:24:40.629037 [Gating] SW calibration Done
1584 00:24:40.632324 ==
1585 00:24:40.632401 Dram Type= 6, Freq= 0, CH_1, rank 0
1586 00:24:40.639243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1587 00:24:40.639321 ==
1588 00:24:40.639381 RX Vref Scan: 0
1589 00:24:40.639436
1590 00:24:40.642231 RX Vref 0 -> 0, step: 1
1591 00:24:40.642317
1592 00:24:40.645802 RX Delay -130 -> 252, step: 16
1593 00:24:40.648880 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1594 00:24:40.652415 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1595 00:24:40.655760 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1596 00:24:40.662251 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1597 00:24:40.665595 iDelay=222, Bit 4, Center 77 (-34 ~ 189) 224
1598 00:24:40.669002 iDelay=222, Bit 5, Center 101 (-2 ~ 205) 208
1599 00:24:40.672084 iDelay=222, Bit 6, Center 109 (-2 ~ 221) 224
1600 00:24:40.675621 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1601 00:24:40.682361 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1602 00:24:40.685523 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1603 00:24:40.689036 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1604 00:24:40.692046 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1605 00:24:40.695313 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1606 00:24:40.701829 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1607 00:24:40.705290 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1608 00:24:40.708517 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1609 00:24:40.708594 ==
1610 00:24:40.712053 Dram Type= 6, Freq= 0, CH_1, rank 0
1611 00:24:40.714996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1612 00:24:40.718783 ==
1613 00:24:40.718860 DQS Delay:
1614 00:24:40.718919 DQS0 = 0, DQS1 = 0
1615 00:24:40.721730 DQM Delay:
1616 00:24:40.721807 DQM0 = 89, DQM1 = 80
1617 00:24:40.725337 DQ Delay:
1618 00:24:40.725414 DQ0 =101, DQ1 =77, DQ2 =77, DQ3 =85
1619 00:24:40.728941 DQ4 =77, DQ5 =101, DQ6 =109, DQ7 =85
1620 00:24:40.732150 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1621 00:24:40.738705 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1622 00:24:40.738783
1623 00:24:40.738861
1624 00:24:40.738933 ==
1625 00:24:40.741842 Dram Type= 6, Freq= 0, CH_1, rank 0
1626 00:24:40.745368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1627 00:24:40.745447 ==
1628 00:24:40.745525
1629 00:24:40.745597
1630 00:24:40.748299 TX Vref Scan disable
1631 00:24:40.748378 == TX Byte 0 ==
1632 00:24:40.755070 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1633 00:24:40.758840 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1634 00:24:40.758928 == TX Byte 1 ==
1635 00:24:40.765138 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1636 00:24:40.768583 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1637 00:24:40.768672 ==
1638 00:24:40.771762 Dram Type= 6, Freq= 0, CH_1, rank 0
1639 00:24:40.775269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1640 00:24:40.775350 ==
1641 00:24:40.789229 TX Vref=22, minBit 8, minWin=27, winSum=451
1642 00:24:40.792337 TX Vref=24, minBit 15, minWin=27, winSum=454
1643 00:24:40.795794 TX Vref=26, minBit 15, minWin=27, winSum=454
1644 00:24:40.799313 TX Vref=28, minBit 15, minWin=27, winSum=456
1645 00:24:40.802379 TX Vref=30, minBit 15, minWin=27, winSum=459
1646 00:24:40.809101 TX Vref=32, minBit 12, minWin=27, winSum=458
1647 00:24:40.812859 [TxChooseVref] Worse bit 15, Min win 27, Win sum 459, Final Vref 30
1648 00:24:40.812939
1649 00:24:40.815987 Final TX Range 1 Vref 30
1650 00:24:40.816066
1651 00:24:40.816143 ==
1652 00:24:40.819069 Dram Type= 6, Freq= 0, CH_1, rank 0
1653 00:24:40.822432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1654 00:24:40.825754 ==
1655 00:24:40.825833
1656 00:24:40.825910
1657 00:24:40.825981 TX Vref Scan disable
1658 00:24:40.829233 == TX Byte 0 ==
1659 00:24:40.832734 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1660 00:24:40.836130 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1661 00:24:40.839460 == TX Byte 1 ==
1662 00:24:40.842955 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1663 00:24:40.846115 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1664 00:24:40.849646
1665 00:24:40.849735 [DATLAT]
1666 00:24:40.849836 Freq=800, CH1 RK0
1667 00:24:40.849936
1668 00:24:40.852986 DATLAT Default: 0xa
1669 00:24:40.853073 0, 0xFFFF, sum = 0
1670 00:24:40.856490 1, 0xFFFF, sum = 0
1671 00:24:40.856576 2, 0xFFFF, sum = 0
1672 00:24:40.859395 3, 0xFFFF, sum = 0
1673 00:24:40.859480 4, 0xFFFF, sum = 0
1674 00:24:40.862961 5, 0xFFFF, sum = 0
1675 00:24:40.866099 6, 0xFFFF, sum = 0
1676 00:24:40.866183 7, 0xFFFF, sum = 0
1677 00:24:40.869811 8, 0xFFFF, sum = 0
1678 00:24:40.869896 9, 0x0, sum = 1
1679 00:24:40.869962 10, 0x0, sum = 2
1680 00:24:40.872896 11, 0x0, sum = 3
1681 00:24:40.872980 12, 0x0, sum = 4
1682 00:24:40.876254 best_step = 10
1683 00:24:40.876361
1684 00:24:40.876454 ==
1685 00:24:40.879806 Dram Type= 6, Freq= 0, CH_1, rank 0
1686 00:24:40.882820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1687 00:24:40.882909 ==
1688 00:24:40.886272 RX Vref Scan: 1
1689 00:24:40.886361
1690 00:24:40.886430 Set Vref Range= 32 -> 127
1691 00:24:40.886495
1692 00:24:40.889687 RX Vref 32 -> 127, step: 1
1693 00:24:40.889787
1694 00:24:40.892662 RX Delay -95 -> 252, step: 8
1695 00:24:40.892786
1696 00:24:40.896153 Set Vref, RX VrefLevel [Byte0]: 32
1697 00:24:40.899783 [Byte1]: 32
1698 00:24:40.899897
1699 00:24:40.902890 Set Vref, RX VrefLevel [Byte0]: 33
1700 00:24:40.906089 [Byte1]: 33
1701 00:24:40.909772
1702 00:24:40.909898 Set Vref, RX VrefLevel [Byte0]: 34
1703 00:24:40.913097 [Byte1]: 34
1704 00:24:40.917558
1705 00:24:40.917726 Set Vref, RX VrefLevel [Byte0]: 35
1706 00:24:40.920505 [Byte1]: 35
1707 00:24:40.925027
1708 00:24:40.925156 Set Vref, RX VrefLevel [Byte0]: 36
1709 00:24:40.928329 [Byte1]: 36
1710 00:24:40.932564
1711 00:24:40.932746 Set Vref, RX VrefLevel [Byte0]: 37
1712 00:24:40.935827 [Byte1]: 37
1713 00:24:40.940513
1714 00:24:40.940674 Set Vref, RX VrefLevel [Byte0]: 38
1715 00:24:40.943361 [Byte1]: 38
1716 00:24:40.947851
1717 00:24:40.947961 Set Vref, RX VrefLevel [Byte0]: 39
1718 00:24:40.951093 [Byte1]: 39
1719 00:24:40.955145
1720 00:24:40.955255 Set Vref, RX VrefLevel [Byte0]: 40
1721 00:24:40.958540 [Byte1]: 40
1722 00:24:40.963229
1723 00:24:40.963306 Set Vref, RX VrefLevel [Byte0]: 41
1724 00:24:40.966224 [Byte1]: 41
1725 00:24:40.970746
1726 00:24:40.970831 Set Vref, RX VrefLevel [Byte0]: 42
1727 00:24:40.974150 [Byte1]: 42
1728 00:24:40.978183
1729 00:24:40.978259 Set Vref, RX VrefLevel [Byte0]: 43
1730 00:24:40.981299 [Byte1]: 43
1731 00:24:40.985712
1732 00:24:40.985839 Set Vref, RX VrefLevel [Byte0]: 44
1733 00:24:40.988965 [Byte1]: 44
1734 00:24:40.993397
1735 00:24:40.993527 Set Vref, RX VrefLevel [Byte0]: 45
1736 00:24:40.996714 [Byte1]: 45
1737 00:24:41.000904
1738 00:24:41.001042 Set Vref, RX VrefLevel [Byte0]: 46
1739 00:24:41.004256 [Byte1]: 46
1740 00:24:41.008649
1741 00:24:41.008832 Set Vref, RX VrefLevel [Byte0]: 47
1742 00:24:41.011788 [Byte1]: 47
1743 00:24:41.016333
1744 00:24:41.016434 Set Vref, RX VrefLevel [Byte0]: 48
1745 00:24:41.019291 [Byte1]: 48
1746 00:24:41.023493
1747 00:24:41.023624 Set Vref, RX VrefLevel [Byte0]: 49
1748 00:24:41.027011 [Byte1]: 49
1749 00:24:41.031268
1750 00:24:41.031364 Set Vref, RX VrefLevel [Byte0]: 50
1751 00:24:41.034524 [Byte1]: 50
1752 00:24:41.038964
1753 00:24:41.039072 Set Vref, RX VrefLevel [Byte0]: 51
1754 00:24:41.042077 [Byte1]: 51
1755 00:24:41.046520
1756 00:24:41.046618 Set Vref, RX VrefLevel [Byte0]: 52
1757 00:24:41.049743 [Byte1]: 52
1758 00:24:41.054031
1759 00:24:41.054137 Set Vref, RX VrefLevel [Byte0]: 53
1760 00:24:41.057484 [Byte1]: 53
1761 00:24:41.061727
1762 00:24:41.061841 Set Vref, RX VrefLevel [Byte0]: 54
1763 00:24:41.065259 [Byte1]: 54
1764 00:24:41.069372
1765 00:24:41.069500 Set Vref, RX VrefLevel [Byte0]: 55
1766 00:24:41.072914 [Byte1]: 55
1767 00:24:41.076849
1768 00:24:41.076992 Set Vref, RX VrefLevel [Byte0]: 56
1769 00:24:41.080245 [Byte1]: 56
1770 00:24:41.084515
1771 00:24:41.084766 Set Vref, RX VrefLevel [Byte0]: 57
1772 00:24:41.087882 [Byte1]: 57
1773 00:24:41.092443
1774 00:24:41.092750 Set Vref, RX VrefLevel [Byte0]: 58
1775 00:24:41.095466 [Byte1]: 58
1776 00:24:41.099762
1777 00:24:41.100046 Set Vref, RX VrefLevel [Byte0]: 59
1778 00:24:41.103256 [Byte1]: 59
1779 00:24:41.107460
1780 00:24:41.107748 Set Vref, RX VrefLevel [Byte0]: 60
1781 00:24:41.111122 [Byte1]: 60
1782 00:24:41.115049
1783 00:24:41.115273 Set Vref, RX VrefLevel [Byte0]: 61
1784 00:24:41.118629 [Byte1]: 61
1785 00:24:41.122386
1786 00:24:41.122594 Set Vref, RX VrefLevel [Byte0]: 62
1787 00:24:41.125939 [Byte1]: 62
1788 00:24:41.129980
1789 00:24:41.130076 Set Vref, RX VrefLevel [Byte0]: 63
1790 00:24:41.133583 [Byte1]: 63
1791 00:24:41.137621
1792 00:24:41.137727 Set Vref, RX VrefLevel [Byte0]: 64
1793 00:24:41.141103 [Byte1]: 64
1794 00:24:41.145447
1795 00:24:41.145531 Set Vref, RX VrefLevel [Byte0]: 65
1796 00:24:41.148882 [Byte1]: 65
1797 00:24:41.152895
1798 00:24:41.152966 Set Vref, RX VrefLevel [Byte0]: 66
1799 00:24:41.156144 [Byte1]: 66
1800 00:24:41.160391
1801 00:24:41.160488 Set Vref, RX VrefLevel [Byte0]: 67
1802 00:24:41.163829 [Byte1]: 67
1803 00:24:41.167940
1804 00:24:41.168033 Set Vref, RX VrefLevel [Byte0]: 68
1805 00:24:41.171597 [Byte1]: 68
1806 00:24:41.175584
1807 00:24:41.175709 Set Vref, RX VrefLevel [Byte0]: 69
1808 00:24:41.178909 [Byte1]: 69
1809 00:24:41.183246
1810 00:24:41.183338 Set Vref, RX VrefLevel [Byte0]: 70
1811 00:24:41.186336 [Byte1]: 70
1812 00:24:41.190986
1813 00:24:41.191082 Set Vref, RX VrefLevel [Byte0]: 71
1814 00:24:41.194497 [Byte1]: 71
1815 00:24:41.198500
1816 00:24:41.198584 Set Vref, RX VrefLevel [Byte0]: 72
1817 00:24:41.201829 [Byte1]: 72
1818 00:24:41.206277
1819 00:24:41.206367 Set Vref, RX VrefLevel [Byte0]: 73
1820 00:24:41.209268 [Byte1]: 73
1821 00:24:41.213825
1822 00:24:41.213891 Set Vref, RX VrefLevel [Byte0]: 74
1823 00:24:41.216976 [Byte1]: 74
1824 00:24:41.221383
1825 00:24:41.221451 Set Vref, RX VrefLevel [Byte0]: 75
1826 00:24:41.224563 [Byte1]: 75
1827 00:24:41.228952
1828 00:24:41.229018 Set Vref, RX VrefLevel [Byte0]: 76
1829 00:24:41.232015 [Byte1]: 76
1830 00:24:41.236583
1831 00:24:41.236675 Set Vref, RX VrefLevel [Byte0]: 77
1832 00:24:41.239792 [Byte1]: 77
1833 00:24:41.243926
1834 00:24:41.243995 Set Vref, RX VrefLevel [Byte0]: 78
1835 00:24:41.247296 [Byte1]: 78
1836 00:24:41.251613
1837 00:24:41.251679 Set Vref, RX VrefLevel [Byte0]: 79
1838 00:24:41.254827 [Byte1]: 79
1839 00:24:41.259304
1840 00:24:41.259370 Set Vref, RX VrefLevel [Byte0]: 80
1841 00:24:41.262412 [Byte1]: 80
1842 00:24:41.266580
1843 00:24:41.266652 Final RX Vref Byte 0 = 52 to rank0
1844 00:24:41.270048 Final RX Vref Byte 1 = 64 to rank0
1845 00:24:41.273453 Final RX Vref Byte 0 = 52 to rank1
1846 00:24:41.276886 Final RX Vref Byte 1 = 64 to rank1==
1847 00:24:41.280168 Dram Type= 6, Freq= 0, CH_1, rank 0
1848 00:24:41.287049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1849 00:24:41.287148 ==
1850 00:24:41.287233 DQS Delay:
1851 00:24:41.287320 DQS0 = 0, DQS1 = 0
1852 00:24:41.290551 DQM Delay:
1853 00:24:41.290614 DQM0 = 92, DQM1 = 81
1854 00:24:41.293617 DQ Delay:
1855 00:24:41.297159 DQ0 =92, DQ1 =88, DQ2 =84, DQ3 =88
1856 00:24:41.300275 DQ4 =92, DQ5 =104, DQ6 =100, DQ7 =88
1857 00:24:41.300338 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =72
1858 00:24:41.307180 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
1859 00:24:41.307244
1860 00:24:41.307304
1861 00:24:41.313897 [DQSOSCAuto] RK0, (LSB)MR18= 0x324f, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
1862 00:24:41.316930 CH1 RK0: MR19=606, MR18=324F
1863 00:24:41.323526 CH1_RK0: MR19=0x606, MR18=0x324F, DQSOSC=390, MR23=63, INC=97, DEC=64
1864 00:24:41.323600
1865 00:24:41.327007 ----->DramcWriteLeveling(PI) begin...
1866 00:24:41.327075 ==
1867 00:24:41.330536 Dram Type= 6, Freq= 0, CH_1, rank 1
1868 00:24:41.333783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1869 00:24:41.333880 ==
1870 00:24:41.337252 Write leveling (Byte 0): 27 => 27
1871 00:24:41.340287 Write leveling (Byte 1): 28 => 28
1872 00:24:41.343902 DramcWriteLeveling(PI) end<-----
1873 00:24:41.343966
1874 00:24:41.344023 ==
1875 00:24:41.346888 Dram Type= 6, Freq= 0, CH_1, rank 1
1876 00:24:41.350403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1877 00:24:41.350471 ==
1878 00:24:41.353943 [Gating] SW mode calibration
1879 00:24:41.360648 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1880 00:24:41.367392 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1881 00:24:41.371016 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1882 00:24:41.373905 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1883 00:24:41.380584 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1884 00:24:41.384220 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 00:24:41.387329 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 00:24:41.394574 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 00:24:41.397476 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 00:24:41.400943 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 00:24:41.404167 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 00:24:41.411406 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 00:24:41.414590 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 00:24:41.417563 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 00:24:41.424696 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 00:24:41.427878 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 00:24:41.431170 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 00:24:41.437845 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 00:24:41.441201 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 00:24:41.444840 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1899 00:24:41.451141 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1900 00:24:41.454649 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 00:24:41.458357 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 00:24:41.464663 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 00:24:41.468363 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 00:24:41.471552 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 00:24:41.477991 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 00:24:41.481630 0 9 4 | B1->B0 | 2727 2424 | 1 1 | (0 0) (0 0)
1907 00:24:41.484856 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1908 00:24:41.488080 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1909 00:24:41.495121 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1910 00:24:41.498008 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1911 00:24:41.501338 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1912 00:24:41.507912 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1913 00:24:41.511479 0 10 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1914 00:24:41.514943 0 10 4 | B1->B0 | 2f2f 2f2f | 0 1 | (0 0) (1 0)
1915 00:24:41.521678 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1916 00:24:41.525172 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1917 00:24:41.528653 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1918 00:24:41.535625 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1919 00:24:41.538276 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1920 00:24:41.541250 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1921 00:24:41.548283 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1922 00:24:41.551806 0 11 4 | B1->B0 | 3434 3333 | 0 0 | (0 0) (0 0)
1923 00:24:41.555219 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1924 00:24:41.558427 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1925 00:24:41.565165 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1926 00:24:41.568410 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1927 00:24:41.571899 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1928 00:24:41.578061 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1929 00:24:41.581649 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1930 00:24:41.585194 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1931 00:24:41.591666 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 00:24:41.595126 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 00:24:41.598086 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 00:24:41.604955 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 00:24:41.608371 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 00:24:41.611562 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 00:24:41.618108 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 00:24:41.621549 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 00:24:41.624799 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1940 00:24:41.631557 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1941 00:24:41.635088 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1942 00:24:41.638633 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1943 00:24:41.645096 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1944 00:24:41.648150 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1945 00:24:41.652115 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1946 00:24:41.654860 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1947 00:24:41.661646 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1948 00:24:41.665616 Total UI for P1: 0, mck2ui 16
1949 00:24:41.668696 best dqsien dly found for B0: ( 0, 14, 2)
1950 00:24:41.671764 Total UI for P1: 0, mck2ui 16
1951 00:24:41.675240 best dqsien dly found for B1: ( 0, 14, 4)
1952 00:24:41.678527 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1953 00:24:41.681663 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1954 00:24:41.682169
1955 00:24:41.685265 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1956 00:24:41.688336 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1957 00:24:41.691995 [Gating] SW calibration Done
1958 00:24:41.692448 ==
1959 00:24:41.695295 Dram Type= 6, Freq= 0, CH_1, rank 1
1960 00:24:41.698594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1961 00:24:41.699117 ==
1962 00:24:41.702089 RX Vref Scan: 0
1963 00:24:41.702515
1964 00:24:41.702844 RX Vref 0 -> 0, step: 1
1965 00:24:41.703153
1966 00:24:41.705101 RX Delay -130 -> 252, step: 16
1967 00:24:41.708561 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1968 00:24:41.715369 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1969 00:24:41.718831 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1970 00:24:41.722419 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1971 00:24:41.725408 iDelay=206, Bit 4, Center 85 (-18 ~ 189) 208
1972 00:24:41.728764 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1973 00:24:41.735204 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1974 00:24:41.738913 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1975 00:24:41.742063 iDelay=206, Bit 8, Center 69 (-34 ~ 173) 208
1976 00:24:41.745557 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1977 00:24:41.748796 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1978 00:24:41.755175 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1979 00:24:41.758983 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1980 00:24:41.761827 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1981 00:24:41.765673 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1982 00:24:41.768851 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1983 00:24:41.769362 ==
1984 00:24:41.772323 Dram Type= 6, Freq= 0, CH_1, rank 1
1985 00:24:41.778967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1986 00:24:41.779507 ==
1987 00:24:41.779893 DQS Delay:
1988 00:24:41.782386 DQS0 = 0, DQS1 = 0
1989 00:24:41.782894 DQM Delay:
1990 00:24:41.783229 DQM0 = 85, DQM1 = 81
1991 00:24:41.785759 DQ Delay:
1992 00:24:41.788852 DQ0 =93, DQ1 =77, DQ2 =77, DQ3 =85
1993 00:24:41.791789 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77
1994 00:24:41.795500 DQ8 =69, DQ9 =77, DQ10 =85, DQ11 =77
1995 00:24:41.798883 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1996 00:24:41.799311
1997 00:24:41.799645
1998 00:24:41.799949 ==
1999 00:24:41.801770 Dram Type= 6, Freq= 0, CH_1, rank 1
2000 00:24:41.805551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2001 00:24:41.805977 ==
2002 00:24:41.806307
2003 00:24:41.806639
2004 00:24:41.808584 TX Vref Scan disable
2005 00:24:41.809199 == TX Byte 0 ==
2006 00:24:41.815932 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2007 00:24:41.819298 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2008 00:24:41.819815 == TX Byte 1 ==
2009 00:24:41.825667 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2010 00:24:41.829399 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2011 00:24:41.829913 ==
2012 00:24:41.832299 Dram Type= 6, Freq= 0, CH_1, rank 1
2013 00:24:41.835749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2014 00:24:41.836263 ==
2015 00:24:41.849229 TX Vref=22, minBit 13, minWin=27, winSum=451
2016 00:24:41.852630 TX Vref=24, minBit 13, minWin=27, winSum=455
2017 00:24:41.856429 TX Vref=26, minBit 13, minWin=27, winSum=454
2018 00:24:41.859185 TX Vref=28, minBit 11, minWin=28, winSum=462
2019 00:24:41.862969 TX Vref=30, minBit 8, minWin=28, winSum=460
2020 00:24:41.869455 TX Vref=32, minBit 15, minWin=27, winSum=458
2021 00:24:41.872863 [TxChooseVref] Worse bit 11, Min win 28, Win sum 462, Final Vref 28
2022 00:24:41.873375
2023 00:24:41.876595 Final TX Range 1 Vref 28
2024 00:24:41.877150
2025 00:24:41.877487 ==
2026 00:24:41.879529 Dram Type= 6, Freq= 0, CH_1, rank 1
2027 00:24:41.882430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2028 00:24:41.886139 ==
2029 00:24:41.886749
2030 00:24:41.887212
2031 00:24:41.887534 TX Vref Scan disable
2032 00:24:41.889502 == TX Byte 0 ==
2033 00:24:41.893008 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2034 00:24:41.896398 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2035 00:24:41.899853 == TX Byte 1 ==
2036 00:24:41.903325 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2037 00:24:41.906702 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2038 00:24:41.910048
2039 00:24:41.910557 [DATLAT]
2040 00:24:41.910894 Freq=800, CH1 RK1
2041 00:24:41.911229
2042 00:24:41.912879 DATLAT Default: 0xa
2043 00:24:41.913389 0, 0xFFFF, sum = 0
2044 00:24:41.916734 1, 0xFFFF, sum = 0
2045 00:24:41.917349 2, 0xFFFF, sum = 0
2046 00:24:41.919995 3, 0xFFFF, sum = 0
2047 00:24:41.920542 4, 0xFFFF, sum = 0
2048 00:24:41.923663 5, 0xFFFF, sum = 0
2049 00:24:41.924178 6, 0xFFFF, sum = 0
2050 00:24:41.926317 7, 0xFFFF, sum = 0
2051 00:24:41.929982 8, 0xFFFF, sum = 0
2052 00:24:41.930499 9, 0x0, sum = 1
2053 00:24:41.930843 10, 0x0, sum = 2
2054 00:24:41.932859 11, 0x0, sum = 3
2055 00:24:41.933294 12, 0x0, sum = 4
2056 00:24:41.936763 best_step = 10
2057 00:24:41.937268
2058 00:24:41.937598 ==
2059 00:24:41.939726 Dram Type= 6, Freq= 0, CH_1, rank 1
2060 00:24:41.943013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2061 00:24:41.943447 ==
2062 00:24:41.946573 RX Vref Scan: 0
2063 00:24:41.947075
2064 00:24:41.947405 RX Vref 0 -> 0, step: 1
2065 00:24:41.947713
2066 00:24:41.949791 RX Delay -79 -> 252, step: 8
2067 00:24:41.956360 iDelay=209, Bit 0, Center 96 (-7 ~ 200) 208
2068 00:24:41.960198 iDelay=209, Bit 1, Center 88 (-15 ~ 192) 208
2069 00:24:41.962992 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2070 00:24:41.966602 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2071 00:24:41.969862 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
2072 00:24:41.976372 iDelay=209, Bit 5, Center 100 (-7 ~ 208) 216
2073 00:24:41.979877 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2074 00:24:41.983184 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2075 00:24:41.986303 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2076 00:24:41.989904 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2077 00:24:41.993205 iDelay=209, Bit 10, Center 88 (-23 ~ 200) 224
2078 00:24:41.999911 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2079 00:24:42.003332 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2080 00:24:42.006695 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2081 00:24:42.009669 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2082 00:24:42.013175 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2083 00:24:42.016191 ==
2084 00:24:42.019777 Dram Type= 6, Freq= 0, CH_1, rank 1
2085 00:24:42.023001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2086 00:24:42.023437 ==
2087 00:24:42.023776 DQS Delay:
2088 00:24:42.026658 DQS0 = 0, DQS1 = 0
2089 00:24:42.027089 DQM Delay:
2090 00:24:42.029832 DQM0 = 91, DQM1 = 83
2091 00:24:42.030271 DQ Delay:
2092 00:24:42.033032 DQ0 =96, DQ1 =88, DQ2 =80, DQ3 =88
2093 00:24:42.036674 DQ4 =92, DQ5 =100, DQ6 =96, DQ7 =88
2094 00:24:42.039799 DQ8 =68, DQ9 =72, DQ10 =88, DQ11 =80
2095 00:24:42.043315 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
2096 00:24:42.043720
2097 00:24:42.044027
2098 00:24:42.050031 [DQSOSCAuto] RK1, (LSB)MR18= 0x3b12, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
2099 00:24:42.053591 CH1 RK1: MR19=606, MR18=3B12
2100 00:24:42.059803 CH1_RK1: MR19=0x606, MR18=0x3B12, DQSOSC=394, MR23=63, INC=95, DEC=63
2101 00:24:42.063317 [RxdqsGatingPostProcess] freq 800
2102 00:24:42.067204 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2103 00:24:42.070256 Pre-setting of DQS Precalculation
2104 00:24:42.076913 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2105 00:24:42.083146 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2106 00:24:42.089977 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2107 00:24:42.090485
2108 00:24:42.090975
2109 00:24:42.093401 [Calibration Summary] 1600 Mbps
2110 00:24:42.096556 CH 0, Rank 0
2111 00:24:42.097141 SW Impedance : PASS
2112 00:24:42.099997 DUTY Scan : NO K
2113 00:24:42.100525 ZQ Calibration : PASS
2114 00:24:42.103690 Jitter Meter : NO K
2115 00:24:42.106502 CBT Training : PASS
2116 00:24:42.106952 Write leveling : PASS
2117 00:24:42.109898 RX DQS gating : PASS
2118 00:24:42.113364 RX DQ/DQS(RDDQC) : PASS
2119 00:24:42.113919 TX DQ/DQS : PASS
2120 00:24:42.116932 RX DATLAT : PASS
2121 00:24:42.120079 RX DQ/DQS(Engine): PASS
2122 00:24:42.120592 TX OE : NO K
2123 00:24:42.123497 All Pass.
2124 00:24:42.124011
2125 00:24:42.124352 CH 0, Rank 1
2126 00:24:42.126328 SW Impedance : PASS
2127 00:24:42.126766 DUTY Scan : NO K
2128 00:24:42.129885 ZQ Calibration : PASS
2129 00:24:42.133403 Jitter Meter : NO K
2130 00:24:42.133920 CBT Training : PASS
2131 00:24:42.136367 Write leveling : PASS
2132 00:24:42.139805 RX DQS gating : PASS
2133 00:24:42.140344 RX DQ/DQS(RDDQC) : PASS
2134 00:24:42.143395 TX DQ/DQS : PASS
2135 00:24:42.143912 RX DATLAT : PASS
2136 00:24:42.146412 RX DQ/DQS(Engine): PASS
2137 00:24:42.150224 TX OE : NO K
2138 00:24:42.150659 All Pass.
2139 00:24:42.150998
2140 00:24:42.151304 CH 1, Rank 0
2141 00:24:42.153240 SW Impedance : PASS
2142 00:24:42.156506 DUTY Scan : NO K
2143 00:24:42.157054 ZQ Calibration : PASS
2144 00:24:42.160119 Jitter Meter : NO K
2145 00:24:42.162941 CBT Training : PASS
2146 00:24:42.163513 Write leveling : PASS
2147 00:24:42.166687 RX DQS gating : PASS
2148 00:24:42.169975 RX DQ/DQS(RDDQC) : PASS
2149 00:24:42.170484 TX DQ/DQS : PASS
2150 00:24:42.173380 RX DATLAT : PASS
2151 00:24:42.176783 RX DQ/DQS(Engine): PASS
2152 00:24:42.177304 TX OE : NO K
2153 00:24:42.179503 All Pass.
2154 00:24:42.179934
2155 00:24:42.180269 CH 1, Rank 1
2156 00:24:42.183381 SW Impedance : PASS
2157 00:24:42.183898 DUTY Scan : NO K
2158 00:24:42.186698 ZQ Calibration : PASS
2159 00:24:42.189215 Jitter Meter : NO K
2160 00:24:42.189665 CBT Training : PASS
2161 00:24:42.192814 Write leveling : PASS
2162 00:24:42.196273 RX DQS gating : PASS
2163 00:24:42.196824 RX DQ/DQS(RDDQC) : PASS
2164 00:24:42.200144 TX DQ/DQS : PASS
2165 00:24:42.200662 RX DATLAT : PASS
2166 00:24:42.202790 RX DQ/DQS(Engine): PASS
2167 00:24:42.206541 TX OE : NO K
2168 00:24:42.207053 All Pass.
2169 00:24:42.207390
2170 00:24:42.209264 DramC Write-DBI off
2171 00:24:42.209701 PER_BANK_REFRESH: Hybrid Mode
2172 00:24:42.212801 TX_TRACKING: ON
2173 00:24:42.216295 [GetDramInforAfterCalByMRR] Vendor 6.
2174 00:24:42.219985 [GetDramInforAfterCalByMRR] Revision 606.
2175 00:24:42.223248 [GetDramInforAfterCalByMRR] Revision 2 0.
2176 00:24:42.223767 MR0 0x3b3b
2177 00:24:42.226257 MR8 0x5151
2178 00:24:42.229932 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2179 00:24:42.230442
2180 00:24:42.230781 MR0 0x3b3b
2181 00:24:42.231094 MR8 0x5151
2182 00:24:42.236397 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2183 00:24:42.236864
2184 00:24:42.243053 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2185 00:24:42.246424 [FAST_K] Save calibration result to emmc
2186 00:24:42.249617 [FAST_K] Save calibration result to emmc
2187 00:24:42.253341 dram_init: config_dvfs: 1
2188 00:24:42.256389 dramc_set_vcore_voltage set vcore to 662500
2189 00:24:42.260355 Read voltage for 1200, 2
2190 00:24:42.260919 Vio18 = 0
2191 00:24:42.263371 Vcore = 662500
2192 00:24:42.263890 Vdram = 0
2193 00:24:42.264230 Vddq = 0
2194 00:24:42.264545 Vmddr = 0
2195 00:24:42.270383 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2196 00:24:42.276847 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2197 00:24:42.277373 MEM_TYPE=3, freq_sel=15
2198 00:24:42.279837 sv_algorithm_assistance_LP4_1600
2199 00:24:42.283610 ============ PULL DRAM RESETB DOWN ============
2200 00:24:42.290101 ========== PULL DRAM RESETB DOWN end =========
2201 00:24:42.293526 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2202 00:24:42.296806 ===================================
2203 00:24:42.300432 LPDDR4 DRAM CONFIGURATION
2204 00:24:42.303089 ===================================
2205 00:24:42.303527 EX_ROW_EN[0] = 0x0
2206 00:24:42.306931 EX_ROW_EN[1] = 0x0
2207 00:24:42.307446 LP4Y_EN = 0x0
2208 00:24:42.310196 WORK_FSP = 0x0
2209 00:24:42.310693 WL = 0x4
2210 00:24:42.313299 RL = 0x4
2211 00:24:42.313734 BL = 0x2
2212 00:24:42.317155 RPST = 0x0
2213 00:24:42.317672 RD_PRE = 0x0
2214 00:24:42.320141 WR_PRE = 0x1
2215 00:24:42.323141 WR_PST = 0x0
2216 00:24:42.323578 DBI_WR = 0x0
2217 00:24:42.326643 DBI_RD = 0x0
2218 00:24:42.327075 OTF = 0x1
2219 00:24:42.330360 ===================================
2220 00:24:42.333350 ===================================
2221 00:24:42.333788 ANA top config
2222 00:24:42.336675 ===================================
2223 00:24:42.339753 DLL_ASYNC_EN = 0
2224 00:24:42.343473 ALL_SLAVE_EN = 0
2225 00:24:42.346727 NEW_RANK_MODE = 1
2226 00:24:42.350354 DLL_IDLE_MODE = 1
2227 00:24:42.350827 LP45_APHY_COMB_EN = 1
2228 00:24:42.353640 TX_ODT_DIS = 1
2229 00:24:42.356957 NEW_8X_MODE = 1
2230 00:24:42.360429 ===================================
2231 00:24:42.363087 ===================================
2232 00:24:42.366883 data_rate = 2400
2233 00:24:42.369976 CKR = 1
2234 00:24:42.370369 DQ_P2S_RATIO = 8
2235 00:24:42.373432 ===================================
2236 00:24:42.377125 CA_P2S_RATIO = 8
2237 00:24:42.379814 DQ_CA_OPEN = 0
2238 00:24:42.383593 DQ_SEMI_OPEN = 0
2239 00:24:42.386952 CA_SEMI_OPEN = 0
2240 00:24:42.387348 CA_FULL_RATE = 0
2241 00:24:42.390410 DQ_CKDIV4_EN = 0
2242 00:24:42.393366 CA_CKDIV4_EN = 0
2243 00:24:42.397102 CA_PREDIV_EN = 0
2244 00:24:42.400287 PH8_DLY = 17
2245 00:24:42.403575 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2246 00:24:42.404051 DQ_AAMCK_DIV = 4
2247 00:24:42.407289 CA_AAMCK_DIV = 4
2248 00:24:42.410332 CA_ADMCK_DIV = 4
2249 00:24:42.413599 DQ_TRACK_CA_EN = 0
2250 00:24:42.417454 CA_PICK = 1200
2251 00:24:42.420100 CA_MCKIO = 1200
2252 00:24:42.423585 MCKIO_SEMI = 0
2253 00:24:42.424059 PLL_FREQ = 2366
2254 00:24:42.426811 DQ_UI_PI_RATIO = 32
2255 00:24:42.430301 CA_UI_PI_RATIO = 0
2256 00:24:42.433921 ===================================
2257 00:24:42.437316 ===================================
2258 00:24:42.439864 memory_type:LPDDR4
2259 00:24:42.440261 GP_NUM : 10
2260 00:24:42.443412 SRAM_EN : 1
2261 00:24:42.447141 MD32_EN : 0
2262 00:24:42.450005 ===================================
2263 00:24:42.450407 [ANA_INIT] >>>>>>>>>>>>>>
2264 00:24:42.453408 <<<<<< [CONFIGURE PHASE]: ANA_TX
2265 00:24:42.456795 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2266 00:24:42.460381 ===================================
2267 00:24:42.463546 data_rate = 2400,PCW = 0X5b00
2268 00:24:42.466455 ===================================
2269 00:24:42.470511 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2270 00:24:42.477064 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2271 00:24:42.480525 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2272 00:24:42.487179 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2273 00:24:42.490773 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2274 00:24:42.493586 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2275 00:24:42.493989 [ANA_INIT] flow start
2276 00:24:42.496967 [ANA_INIT] PLL >>>>>>>>
2277 00:24:42.500518 [ANA_INIT] PLL <<<<<<<<
2278 00:24:42.501038 [ANA_INIT] MIDPI >>>>>>>>
2279 00:24:42.503216 [ANA_INIT] MIDPI <<<<<<<<
2280 00:24:42.506782 [ANA_INIT] DLL >>>>>>>>
2281 00:24:42.510418 [ANA_INIT] DLL <<<<<<<<
2282 00:24:42.510850 [ANA_INIT] flow end
2283 00:24:42.513811 ============ LP4 DIFF to SE enter ============
2284 00:24:42.519963 ============ LP4 DIFF to SE exit ============
2285 00:24:42.520361 [ANA_INIT] <<<<<<<<<<<<<
2286 00:24:42.523883 [Flow] Enable top DCM control >>>>>
2287 00:24:42.526683 [Flow] Enable top DCM control <<<<<
2288 00:24:42.530363 Enable DLL master slave shuffle
2289 00:24:42.536808 ==============================================================
2290 00:24:42.537272 Gating Mode config
2291 00:24:42.543630 ==============================================================
2292 00:24:42.547254 Config description:
2293 00:24:42.553663 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2294 00:24:42.560497 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2295 00:24:42.566965 SELPH_MODE 0: By rank 1: By Phase
2296 00:24:42.574171 ==============================================================
2297 00:24:42.574735 GAT_TRACK_EN = 1
2298 00:24:42.577281 RX_GATING_MODE = 2
2299 00:24:42.580329 RX_GATING_TRACK_MODE = 2
2300 00:24:42.583757 SELPH_MODE = 1
2301 00:24:42.587171 PICG_EARLY_EN = 1
2302 00:24:42.590229 VALID_LAT_VALUE = 1
2303 00:24:42.597296 ==============================================================
2304 00:24:42.600303 Enter into Gating configuration >>>>
2305 00:24:42.603982 Exit from Gating configuration <<<<
2306 00:24:42.607045 Enter into DVFS_PRE_config >>>>>
2307 00:24:42.617039 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2308 00:24:42.620761 Exit from DVFS_PRE_config <<<<<
2309 00:24:42.623886 Enter into PICG configuration >>>>
2310 00:24:42.626974 Exit from PICG configuration <<<<
2311 00:24:42.627372 [RX_INPUT] configuration >>>>>
2312 00:24:42.630618 [RX_INPUT] configuration <<<<<
2313 00:24:42.637529 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2314 00:24:42.640339 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2315 00:24:42.647453 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2316 00:24:42.653847 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2317 00:24:42.660734 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2318 00:24:42.667578 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2319 00:24:42.670793 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2320 00:24:42.674174 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2321 00:24:42.677528 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2322 00:24:42.683807 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2323 00:24:42.687270 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2324 00:24:42.690559 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2325 00:24:42.693906 ===================================
2326 00:24:42.697336 LPDDR4 DRAM CONFIGURATION
2327 00:24:42.700361 ===================================
2328 00:24:42.703992 EX_ROW_EN[0] = 0x0
2329 00:24:42.704424 EX_ROW_EN[1] = 0x0
2330 00:24:42.707505 LP4Y_EN = 0x0
2331 00:24:42.707974 WORK_FSP = 0x0
2332 00:24:42.710637 WL = 0x4
2333 00:24:42.711031 RL = 0x4
2334 00:24:42.713750 BL = 0x2
2335 00:24:42.714164 RPST = 0x0
2336 00:24:42.717397 RD_PRE = 0x0
2337 00:24:42.717862 WR_PRE = 0x1
2338 00:24:42.720778 WR_PST = 0x0
2339 00:24:42.721251 DBI_WR = 0x0
2340 00:24:42.723875 DBI_RD = 0x0
2341 00:24:42.724266 OTF = 0x1
2342 00:24:42.727541 ===================================
2343 00:24:42.730967 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2344 00:24:42.737548 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2345 00:24:42.740668 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2346 00:24:42.744369 ===================================
2347 00:24:42.747843 LPDDR4 DRAM CONFIGURATION
2348 00:24:42.750720 ===================================
2349 00:24:42.751132 EX_ROW_EN[0] = 0x10
2350 00:24:42.754266 EX_ROW_EN[1] = 0x0
2351 00:24:42.754660 LP4Y_EN = 0x0
2352 00:24:42.757661 WORK_FSP = 0x0
2353 00:24:42.760729 WL = 0x4
2354 00:24:42.761128 RL = 0x4
2355 00:24:42.764175 BL = 0x2
2356 00:24:42.764567 RPST = 0x0
2357 00:24:42.768046 RD_PRE = 0x0
2358 00:24:42.768487 WR_PRE = 0x1
2359 00:24:42.771223 WR_PST = 0x0
2360 00:24:42.771697 DBI_WR = 0x0
2361 00:24:42.774444 DBI_RD = 0x0
2362 00:24:42.774898 OTF = 0x1
2363 00:24:42.777515 ===================================
2364 00:24:42.784200 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2365 00:24:42.784644 ==
2366 00:24:42.787865 Dram Type= 6, Freq= 0, CH_0, rank 0
2367 00:24:42.790836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2368 00:24:42.791234 ==
2369 00:24:42.794259 [Duty_Offset_Calibration]
2370 00:24:42.797417 B0:2 B1:0 CA:1
2371 00:24:42.797989
2372 00:24:42.800677 [DutyScan_Calibration_Flow] k_type=0
2373 00:24:42.807784
2374 00:24:42.808342 ==CLK 0==
2375 00:24:42.811078 Final CLK duty delay cell = -4
2376 00:24:42.814549 [-4] MAX Duty = 5031%(X100), DQS PI = 26
2377 00:24:42.818126 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2378 00:24:42.821158 [-4] AVG Duty = 4953%(X100)
2379 00:24:42.821586
2380 00:24:42.824597 CH0 CLK Duty spec in!! Max-Min= 156%
2381 00:24:42.827932 [DutyScan_Calibration_Flow] ====Done====
2382 00:24:42.828141
2383 00:24:42.831146 [DutyScan_Calibration_Flow] k_type=1
2384 00:24:42.847009
2385 00:24:42.847447 ==DQS 0 ==
2386 00:24:42.850058 Final DQS duty delay cell = 0
2387 00:24:42.853174 [0] MAX Duty = 5187%(X100), DQS PI = 30
2388 00:24:42.856948 [0] MIN Duty = 4938%(X100), DQS PI = 0
2389 00:24:42.857448 [0] AVG Duty = 5062%(X100)
2390 00:24:42.860163
2391 00:24:42.860631 ==DQS 1 ==
2392 00:24:42.863157 Final DQS duty delay cell = -4
2393 00:24:42.866850 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2394 00:24:42.870009 [-4] MIN Duty = 4938%(X100), DQS PI = 6
2395 00:24:42.873599 [-4] AVG Duty = 5031%(X100)
2396 00:24:42.873997
2397 00:24:42.877112 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2398 00:24:42.877584
2399 00:24:42.880253 CH0 DQS 1 Duty spec in!! Max-Min= 186%
2400 00:24:42.883889 [DutyScan_Calibration_Flow] ====Done====
2401 00:24:42.884329
2402 00:24:42.886908 [DutyScan_Calibration_Flow] k_type=3
2403 00:24:42.903757
2404 00:24:42.904266 ==DQM 0 ==
2405 00:24:42.906700 Final DQM duty delay cell = 0
2406 00:24:42.910044 [0] MAX Duty = 5062%(X100), DQS PI = 24
2407 00:24:42.913683 [0] MIN Duty = 4813%(X100), DQS PI = 0
2408 00:24:42.914100 [0] AVG Duty = 4937%(X100)
2409 00:24:42.916821
2410 00:24:42.917209 ==DQM 1 ==
2411 00:24:42.920364 Final DQM duty delay cell = 0
2412 00:24:42.923548 [0] MAX Duty = 5187%(X100), DQS PI = 48
2413 00:24:42.926954 [0] MIN Duty = 4969%(X100), DQS PI = 24
2414 00:24:42.927355 [0] AVG Duty = 5078%(X100)
2415 00:24:42.930027
2416 00:24:42.933497 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2417 00:24:42.933891
2418 00:24:42.937058 CH0 DQM 1 Duty spec in!! Max-Min= 218%
2419 00:24:42.940544 [DutyScan_Calibration_Flow] ====Done====
2420 00:24:42.941044
2421 00:24:42.943664 [DutyScan_Calibration_Flow] k_type=2
2422 00:24:42.960888
2423 00:24:42.961327 ==DQ 0 ==
2424 00:24:42.964271 Final DQ duty delay cell = 0
2425 00:24:42.967435 [0] MAX Duty = 5156%(X100), DQS PI = 34
2426 00:24:42.971518 [0] MIN Duty = 5000%(X100), DQS PI = 0
2427 00:24:42.972000 [0] AVG Duty = 5078%(X100)
2428 00:24:42.972309
2429 00:24:42.974550 ==DQ 1 ==
2430 00:24:42.977518 Final DQ duty delay cell = 4
2431 00:24:42.980851 [4] MAX Duty = 5093%(X100), DQS PI = 4
2432 00:24:42.984534 [4] MIN Duty = 5031%(X100), DQS PI = 0
2433 00:24:42.985022 [4] AVG Duty = 5062%(X100)
2434 00:24:42.985383
2435 00:24:42.987599 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2436 00:24:42.987987
2437 00:24:42.990986 CH0 DQ 1 Duty spec in!! Max-Min= 62%
2438 00:24:42.993982 [DutyScan_Calibration_Flow] ====Done====
2439 00:24:42.997621 ==
2440 00:24:43.001147 Dram Type= 6, Freq= 0, CH_1, rank 0
2441 00:24:43.004510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2442 00:24:43.005040 ==
2443 00:24:43.008218 [Duty_Offset_Calibration]
2444 00:24:43.008701 B0:0 B1:-1 CA:2
2445 00:24:43.009067
2446 00:24:43.010816 [DutyScan_Calibration_Flow] k_type=0
2447 00:24:43.020548
2448 00:24:43.021129 ==CLK 0==
2449 00:24:43.024025 Final CLK duty delay cell = 0
2450 00:24:43.027034 [0] MAX Duty = 5156%(X100), DQS PI = 8
2451 00:24:43.030489 [0] MIN Duty = 4938%(X100), DQS PI = 44
2452 00:24:43.030928 [0] AVG Duty = 5047%(X100)
2453 00:24:43.034013
2454 00:24:43.034586 CH1 CLK Duty spec in!! Max-Min= 218%
2455 00:24:43.040246 [DutyScan_Calibration_Flow] ====Done====
2456 00:24:43.040843
2457 00:24:43.043571 [DutyScan_Calibration_Flow] k_type=1
2458 00:24:43.060123
2459 00:24:43.060539 ==DQS 0 ==
2460 00:24:43.062938 Final DQS duty delay cell = 0
2461 00:24:43.066407 [0] MAX Duty = 5093%(X100), DQS PI = 22
2462 00:24:43.069813 [0] MIN Duty = 4969%(X100), DQS PI = 0
2463 00:24:43.070210 [0] AVG Duty = 5031%(X100)
2464 00:24:43.073296
2465 00:24:43.073689 ==DQS 1 ==
2466 00:24:43.076336 Final DQS duty delay cell = 0
2467 00:24:43.080112 [0] MAX Duty = 5156%(X100), DQS PI = 0
2468 00:24:43.083196 [0] MIN Duty = 4844%(X100), DQS PI = 36
2469 00:24:43.083590 [0] AVG Duty = 5000%(X100)
2470 00:24:43.087159
2471 00:24:43.090124 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2472 00:24:43.090607
2473 00:24:43.093502 CH1 DQS 1 Duty spec in!! Max-Min= 312%
2474 00:24:43.096770 [DutyScan_Calibration_Flow] ====Done====
2475 00:24:43.097181
2476 00:24:43.100118 [DutyScan_Calibration_Flow] k_type=3
2477 00:24:43.116248
2478 00:24:43.116745 ==DQM 0 ==
2479 00:24:43.119937 Final DQM duty delay cell = 4
2480 00:24:43.123196 [4] MAX Duty = 5093%(X100), DQS PI = 22
2481 00:24:43.126280 [4] MIN Duty = 4938%(X100), DQS PI = 30
2482 00:24:43.126711 [4] AVG Duty = 5015%(X100)
2483 00:24:43.129641
2484 00:24:43.130029 ==DQM 1 ==
2485 00:24:43.133284 Final DQM duty delay cell = -4
2486 00:24:43.136426 [-4] MAX Duty = 5000%(X100), DQS PI = 62
2487 00:24:43.140032 [-4] MIN Duty = 4720%(X100), DQS PI = 36
2488 00:24:43.143672 [-4] AVG Duty = 4860%(X100)
2489 00:24:43.144177
2490 00:24:43.147387 CH1 DQM 0 Duty spec in!! Max-Min= 155%
2491 00:24:43.147867
2492 00:24:43.149781 CH1 DQM 1 Duty spec in!! Max-Min= 280%
2493 00:24:43.153349 [DutyScan_Calibration_Flow] ====Done====
2494 00:24:43.153744
2495 00:24:43.156601 [DutyScan_Calibration_Flow] k_type=2
2496 00:24:43.173789
2497 00:24:43.174267 ==DQ 0 ==
2498 00:24:43.176848 Final DQ duty delay cell = 0
2499 00:24:43.179675 [0] MAX Duty = 5062%(X100), DQS PI = 20
2500 00:24:43.183512 [0] MIN Duty = 4938%(X100), DQS PI = 0
2501 00:24:43.184002 [0] AVG Duty = 5000%(X100)
2502 00:24:43.186971
2503 00:24:43.187462 ==DQ 1 ==
2504 00:24:43.190006 Final DQ duty delay cell = 0
2505 00:24:43.193684 [0] MAX Duty = 5031%(X100), DQS PI = 2
2506 00:24:43.196829 [0] MIN Duty = 4813%(X100), DQS PI = 34
2507 00:24:43.197477 [0] AVG Duty = 4922%(X100)
2508 00:24:43.197901
2509 00:24:43.199909 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2510 00:24:43.200302
2511 00:24:43.203183 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2512 00:24:43.210004 [DutyScan_Calibration_Flow] ====Done====
2513 00:24:43.213248 nWR fixed to 30
2514 00:24:43.213646 [ModeRegInit_LP4] CH0 RK0
2515 00:24:43.216405 [ModeRegInit_LP4] CH0 RK1
2516 00:24:43.220148 [ModeRegInit_LP4] CH1 RK0
2517 00:24:43.220637 [ModeRegInit_LP4] CH1 RK1
2518 00:24:43.223261 match AC timing 7
2519 00:24:43.226552 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2520 00:24:43.230421 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2521 00:24:43.236489 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2522 00:24:43.240242 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2523 00:24:43.246491 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2524 00:24:43.246944 ==
2525 00:24:43.249906 Dram Type= 6, Freq= 0, CH_0, rank 0
2526 00:24:43.253522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2527 00:24:43.254010 ==
2528 00:24:43.260250 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2529 00:24:43.263296 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2530 00:24:43.273059 [CA 0] Center 38 (8~69) winsize 62
2531 00:24:43.276617 [CA 1] Center 38 (8~69) winsize 62
2532 00:24:43.279683 [CA 2] Center 35 (5~66) winsize 62
2533 00:24:43.283306 [CA 3] Center 35 (4~66) winsize 63
2534 00:24:43.286778 [CA 4] Center 34 (4~65) winsize 62
2535 00:24:43.289890 [CA 5] Center 33 (3~63) winsize 61
2536 00:24:43.290475
2537 00:24:43.293324 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2538 00:24:43.293775
2539 00:24:43.296459 [CATrainingPosCal] consider 1 rank data
2540 00:24:43.299906 u2DelayCellTimex100 = 270/100 ps
2541 00:24:43.302936 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2542 00:24:43.306563 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2543 00:24:43.313219 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2544 00:24:43.316340 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2545 00:24:43.320147 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2546 00:24:43.323357 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2547 00:24:43.323811
2548 00:24:43.326609 CA PerBit enable=1, Macro0, CA PI delay=33
2549 00:24:43.327082
2550 00:24:43.330125 [CBTSetCACLKResult] CA Dly = 33
2551 00:24:43.330525 CS Dly: 6 (0~37)
2552 00:24:43.330833 ==
2553 00:24:43.333207 Dram Type= 6, Freq= 0, CH_0, rank 1
2554 00:24:43.340079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2555 00:24:43.340559 ==
2556 00:24:43.343207 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2557 00:24:43.350009 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2558 00:24:43.359361 [CA 0] Center 39 (8~70) winsize 63
2559 00:24:43.362111 [CA 1] Center 38 (8~69) winsize 62
2560 00:24:43.365729 [CA 2] Center 35 (5~66) winsize 62
2561 00:24:43.369284 [CA 3] Center 35 (5~66) winsize 62
2562 00:24:43.372042 [CA 4] Center 34 (4~65) winsize 62
2563 00:24:43.375499 [CA 5] Center 34 (4~64) winsize 61
2564 00:24:43.375900
2565 00:24:43.379185 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2566 00:24:43.379580
2567 00:24:43.382291 [CATrainingPosCal] consider 2 rank data
2568 00:24:43.385572 u2DelayCellTimex100 = 270/100 ps
2569 00:24:43.389015 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2570 00:24:43.392499 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2571 00:24:43.395376 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2572 00:24:43.402168 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2573 00:24:43.405644 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2574 00:24:43.408895 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2575 00:24:43.409297
2576 00:24:43.412118 CA PerBit enable=1, Macro0, CA PI delay=33
2577 00:24:43.412513
2578 00:24:43.415602 [CBTSetCACLKResult] CA Dly = 33
2579 00:24:43.416088 CS Dly: 7 (0~39)
2580 00:24:43.416400
2581 00:24:43.418898 ----->DramcWriteLeveling(PI) begin...
2582 00:24:43.419379 ==
2583 00:24:43.421983 Dram Type= 6, Freq= 0, CH_0, rank 0
2584 00:24:43.429054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2585 00:24:43.429523 ==
2586 00:24:43.432402 Write leveling (Byte 0): 33 => 33
2587 00:24:43.435473 Write leveling (Byte 1): 31 => 31
2588 00:24:43.435931 DramcWriteLeveling(PI) end<-----
2589 00:24:43.439108
2590 00:24:43.439501 ==
2591 00:24:43.442311 Dram Type= 6, Freq= 0, CH_0, rank 0
2592 00:24:43.445728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2593 00:24:43.446127 ==
2594 00:24:43.448809 [Gating] SW mode calibration
2595 00:24:43.455411 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2596 00:24:43.458890 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2597 00:24:43.465984 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2598 00:24:43.469220 0 15 4 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
2599 00:24:43.472141 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2600 00:24:43.479210 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2601 00:24:43.482221 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2602 00:24:43.485265 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2603 00:24:43.492481 0 15 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
2604 00:24:43.495762 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
2605 00:24:43.498611 1 0 0 | B1->B0 | 2e2e 2323 | 0 0 | (1 0) (0 0)
2606 00:24:43.505715 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2607 00:24:43.509269 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2608 00:24:43.512425 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2609 00:24:43.519094 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2610 00:24:43.522845 1 0 20 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
2611 00:24:43.526302 1 0 24 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
2612 00:24:43.529233 1 0 28 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
2613 00:24:43.535608 1 1 0 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
2614 00:24:43.539132 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2615 00:24:43.542335 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2616 00:24:43.549211 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2617 00:24:43.552285 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2618 00:24:43.555835 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2619 00:24:43.562654 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2620 00:24:43.565956 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2621 00:24:43.569050 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2622 00:24:43.575458 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2623 00:24:43.579103 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 00:24:43.582281 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 00:24:43.588806 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 00:24:43.592329 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 00:24:43.595762 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2628 00:24:43.602212 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2629 00:24:43.605478 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2630 00:24:43.609688 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2631 00:24:43.612432 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2632 00:24:43.619326 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2633 00:24:43.622629 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2634 00:24:43.625913 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2635 00:24:43.632367 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2636 00:24:43.635735 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2637 00:24:43.639090 Total UI for P1: 0, mck2ui 16
2638 00:24:43.642410 best dqsien dly found for B0: ( 1, 3, 26)
2639 00:24:43.645981 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2640 00:24:43.652682 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2641 00:24:43.653300 Total UI for P1: 0, mck2ui 16
2642 00:24:43.659149 best dqsien dly found for B1: ( 1, 3, 30)
2643 00:24:43.662738 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2644 00:24:43.665741 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2645 00:24:43.666279
2646 00:24:43.669150 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2647 00:24:43.672648 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2648 00:24:43.675874 [Gating] SW calibration Done
2649 00:24:43.676365 ==
2650 00:24:43.679532 Dram Type= 6, Freq= 0, CH_0, rank 0
2651 00:24:43.682494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2652 00:24:43.683085 ==
2653 00:24:43.685899 RX Vref Scan: 0
2654 00:24:43.686456
2655 00:24:43.686966 RX Vref 0 -> 0, step: 1
2656 00:24:43.687443
2657 00:24:43.689539 RX Delay -40 -> 252, step: 8
2658 00:24:43.692559 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
2659 00:24:43.696096 iDelay=208, Bit 1, Center 127 (56 ~ 199) 144
2660 00:24:43.702511 iDelay=208, Bit 2, Center 119 (48 ~ 191) 144
2661 00:24:43.706041 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
2662 00:24:43.709069 iDelay=208, Bit 4, Center 127 (56 ~ 199) 144
2663 00:24:43.712426 iDelay=208, Bit 5, Center 115 (48 ~ 183) 136
2664 00:24:43.715773 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
2665 00:24:43.722460 iDelay=208, Bit 7, Center 127 (56 ~ 199) 144
2666 00:24:43.725956 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
2667 00:24:43.729121 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
2668 00:24:43.732941 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
2669 00:24:43.736191 iDelay=208, Bit 11, Center 107 (40 ~ 175) 136
2670 00:24:43.742695 iDelay=208, Bit 12, Center 115 (48 ~ 183) 136
2671 00:24:43.745857 iDelay=208, Bit 13, Center 115 (48 ~ 183) 136
2672 00:24:43.749508 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
2673 00:24:43.752646 iDelay=208, Bit 15, Center 115 (48 ~ 183) 136
2674 00:24:43.752951 ==
2675 00:24:43.755994 Dram Type= 6, Freq= 0, CH_0, rank 0
2676 00:24:43.759381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2677 00:24:43.762340 ==
2678 00:24:43.762450 DQS Delay:
2679 00:24:43.762540 DQS0 = 0, DQS1 = 0
2680 00:24:43.765828 DQM Delay:
2681 00:24:43.765928 DQM0 = 123, DQM1 = 110
2682 00:24:43.769273 DQ Delay:
2683 00:24:43.772932 DQ0 =123, DQ1 =127, DQ2 =119, DQ3 =119
2684 00:24:43.775835 DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =127
2685 00:24:43.779385 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2686 00:24:43.782707 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2687 00:24:43.782811
2688 00:24:43.782898
2689 00:24:43.782993 ==
2690 00:24:43.786240 Dram Type= 6, Freq= 0, CH_0, rank 0
2691 00:24:43.789561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2692 00:24:43.789697 ==
2693 00:24:43.789800
2694 00:24:43.789911
2695 00:24:43.792639 TX Vref Scan disable
2696 00:24:43.796139 == TX Byte 0 ==
2697 00:24:43.799570 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2698 00:24:43.802780 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2699 00:24:43.805814 == TX Byte 1 ==
2700 00:24:43.809438 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2701 00:24:43.812422 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2702 00:24:43.812589 ==
2703 00:24:43.815984 Dram Type= 6, Freq= 0, CH_0, rank 0
2704 00:24:43.819555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2705 00:24:43.822325 ==
2706 00:24:43.832654 TX Vref=22, minBit 3, minWin=24, winSum=414
2707 00:24:43.836486 TX Vref=24, minBit 0, minWin=25, winSum=414
2708 00:24:43.839467 TX Vref=26, minBit 0, minWin=25, winSum=417
2709 00:24:43.843175 TX Vref=28, minBit 0, minWin=26, winSum=426
2710 00:24:43.846582 TX Vref=30, minBit 0, minWin=26, winSum=423
2711 00:24:43.849953 TX Vref=32, minBit 1, minWin=25, winSum=422
2712 00:24:43.856398 [TxChooseVref] Worse bit 0, Min win 26, Win sum 426, Final Vref 28
2713 00:24:43.857017
2714 00:24:43.859914 Final TX Range 1 Vref 28
2715 00:24:43.860319
2716 00:24:43.860622 ==
2717 00:24:43.863190 Dram Type= 6, Freq= 0, CH_0, rank 0
2718 00:24:43.866788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2719 00:24:43.867194 ==
2720 00:24:43.867546
2721 00:24:43.867926
2722 00:24:43.869811 TX Vref Scan disable
2723 00:24:43.873422 == TX Byte 0 ==
2724 00:24:43.876612 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2725 00:24:43.880062 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2726 00:24:43.883595 == TX Byte 1 ==
2727 00:24:43.886493 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2728 00:24:43.890132 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2729 00:24:43.890398
2730 00:24:43.893081 [DATLAT]
2731 00:24:43.893464 Freq=1200, CH0 RK0
2732 00:24:43.893847
2733 00:24:43.896422 DATLAT Default: 0xd
2734 00:24:43.896684 0, 0xFFFF, sum = 0
2735 00:24:43.899734 1, 0xFFFF, sum = 0
2736 00:24:43.899905 2, 0xFFFF, sum = 0
2737 00:24:43.903120 3, 0xFFFF, sum = 0
2738 00:24:43.903292 4, 0xFFFF, sum = 0
2739 00:24:43.906607 5, 0xFFFF, sum = 0
2740 00:24:43.906780 6, 0xFFFF, sum = 0
2741 00:24:43.909746 7, 0xFFFF, sum = 0
2742 00:24:43.909919 8, 0xFFFF, sum = 0
2743 00:24:43.913095 9, 0xFFFF, sum = 0
2744 00:24:43.913268 10, 0xFFFF, sum = 0
2745 00:24:43.916884 11, 0xFFFF, sum = 0
2746 00:24:43.917126 12, 0x0, sum = 1
2747 00:24:43.919886 13, 0x0, sum = 2
2748 00:24:43.920072 14, 0x0, sum = 3
2749 00:24:43.922946 15, 0x0, sum = 4
2750 00:24:43.923118 best_step = 13
2751 00:24:43.923250
2752 00:24:43.923371 ==
2753 00:24:43.926583 Dram Type= 6, Freq= 0, CH_0, rank 0
2754 00:24:43.933093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2755 00:24:43.933378 ==
2756 00:24:43.933569 RX Vref Scan: 1
2757 00:24:43.933755
2758 00:24:43.936905 Set Vref Range= 32 -> 127
2759 00:24:43.937317
2760 00:24:43.939898 RX Vref 32 -> 127, step: 1
2761 00:24:43.940294
2762 00:24:43.943404 RX Delay -13 -> 252, step: 4
2763 00:24:43.943813
2764 00:24:43.946669 Set Vref, RX VrefLevel [Byte0]: 32
2765 00:24:43.947080 [Byte1]: 32
2766 00:24:43.951637
2767 00:24:43.952081 Set Vref, RX VrefLevel [Byte0]: 33
2768 00:24:43.954502 [Byte1]: 33
2769 00:24:43.959246
2770 00:24:43.959638 Set Vref, RX VrefLevel [Byte0]: 34
2771 00:24:43.962592 [Byte1]: 34
2772 00:24:43.967160
2773 00:24:43.967552 Set Vref, RX VrefLevel [Byte0]: 35
2774 00:24:43.970990 [Byte1]: 35
2775 00:24:43.975352
2776 00:24:43.975749 Set Vref, RX VrefLevel [Byte0]: 36
2777 00:24:43.978420 [Byte1]: 36
2778 00:24:43.982909
2779 00:24:43.983303 Set Vref, RX VrefLevel [Byte0]: 37
2780 00:24:43.986359 [Byte1]: 37
2781 00:24:43.991091
2782 00:24:43.991486 Set Vref, RX VrefLevel [Byte0]: 38
2783 00:24:43.994211 [Byte1]: 38
2784 00:24:43.998570
2785 00:24:43.999148 Set Vref, RX VrefLevel [Byte0]: 39
2786 00:24:44.002122 [Byte1]: 39
2787 00:24:44.006479
2788 00:24:44.007005 Set Vref, RX VrefLevel [Byte0]: 40
2789 00:24:44.010374 [Byte1]: 40
2790 00:24:44.014503
2791 00:24:44.014902 Set Vref, RX VrefLevel [Byte0]: 41
2792 00:24:44.018116 [Byte1]: 41
2793 00:24:44.022741
2794 00:24:44.023239 Set Vref, RX VrefLevel [Byte0]: 42
2795 00:24:44.026010 [Byte1]: 42
2796 00:24:44.030348
2797 00:24:44.030745 Set Vref, RX VrefLevel [Byte0]: 43
2798 00:24:44.033612 [Byte1]: 43
2799 00:24:44.038283
2800 00:24:44.038682 Set Vref, RX VrefLevel [Byte0]: 44
2801 00:24:44.041314 [Byte1]: 44
2802 00:24:44.046228
2803 00:24:44.046684 Set Vref, RX VrefLevel [Byte0]: 45
2804 00:24:44.049519 [Byte1]: 45
2805 00:24:44.054144
2806 00:24:44.054537 Set Vref, RX VrefLevel [Byte0]: 46
2807 00:24:44.057130 [Byte1]: 46
2808 00:24:44.061807
2809 00:24:44.062202 Set Vref, RX VrefLevel [Byte0]: 47
2810 00:24:44.064990 [Byte1]: 47
2811 00:24:44.070152
2812 00:24:44.070625 Set Vref, RX VrefLevel [Byte0]: 48
2813 00:24:44.073202 [Byte1]: 48
2814 00:24:44.078013
2815 00:24:44.078745 Set Vref, RX VrefLevel [Byte0]: 49
2816 00:24:44.080918 [Byte1]: 49
2817 00:24:44.085280
2818 00:24:44.085715 Set Vref, RX VrefLevel [Byte0]: 50
2819 00:24:44.088624 [Byte1]: 50
2820 00:24:44.093116
2821 00:24:44.093504 Set Vref, RX VrefLevel [Byte0]: 51
2822 00:24:44.096924 [Byte1]: 51
2823 00:24:44.101286
2824 00:24:44.101674 Set Vref, RX VrefLevel [Byte0]: 52
2825 00:24:44.104417 [Byte1]: 52
2826 00:24:44.109051
2827 00:24:44.109723 Set Vref, RX VrefLevel [Byte0]: 53
2828 00:24:44.112162 [Byte1]: 53
2829 00:24:44.117268
2830 00:24:44.117654 Set Vref, RX VrefLevel [Byte0]: 54
2831 00:24:44.120315 [Byte1]: 54
2832 00:24:44.124819
2833 00:24:44.125206 Set Vref, RX VrefLevel [Byte0]: 55
2834 00:24:44.128414 [Byte1]: 55
2835 00:24:44.133035
2836 00:24:44.133496 Set Vref, RX VrefLevel [Byte0]: 56
2837 00:24:44.136298 [Byte1]: 56
2838 00:24:44.140933
2839 00:24:44.141376 Set Vref, RX VrefLevel [Byte0]: 57
2840 00:24:44.144394 [Byte1]: 57
2841 00:24:44.148962
2842 00:24:44.149439 Set Vref, RX VrefLevel [Byte0]: 58
2843 00:24:44.151815 [Byte1]: 58
2844 00:24:44.156576
2845 00:24:44.157011 Set Vref, RX VrefLevel [Byte0]: 59
2846 00:24:44.159664 [Byte1]: 59
2847 00:24:44.164363
2848 00:24:44.164854 Set Vref, RX VrefLevel [Byte0]: 60
2849 00:24:44.167522 [Byte1]: 60
2850 00:24:44.172415
2851 00:24:44.172932 Set Vref, RX VrefLevel [Byte0]: 61
2852 00:24:44.175484 [Byte1]: 61
2853 00:24:44.180453
2854 00:24:44.180951 Set Vref, RX VrefLevel [Byte0]: 62
2855 00:24:44.183494 [Byte1]: 62
2856 00:24:44.188140
2857 00:24:44.188614 Set Vref, RX VrefLevel [Byte0]: 63
2858 00:24:44.191494 [Byte1]: 63
2859 00:24:44.195928
2860 00:24:44.196316 Set Vref, RX VrefLevel [Byte0]: 64
2861 00:24:44.199474 [Byte1]: 64
2862 00:24:44.203694
2863 00:24:44.204080 Set Vref, RX VrefLevel [Byte0]: 65
2864 00:24:44.207187 [Byte1]: 65
2865 00:24:44.211977
2866 00:24:44.212449 Set Vref, RX VrefLevel [Byte0]: 66
2867 00:24:44.214929 [Byte1]: 66
2868 00:24:44.219500
2869 00:24:44.219940 Set Vref, RX VrefLevel [Byte0]: 67
2870 00:24:44.223046 [Byte1]: 67
2871 00:24:44.227677
2872 00:24:44.228067 Set Vref, RX VrefLevel [Byte0]: 68
2873 00:24:44.230724 [Byte1]: 68
2874 00:24:44.235373
2875 00:24:44.235844 Set Vref, RX VrefLevel [Byte0]: 69
2876 00:24:44.238837 [Byte1]: 69
2877 00:24:44.243755
2878 00:24:44.244225 Set Vref, RX VrefLevel [Byte0]: 70
2879 00:24:44.246294 [Byte1]: 70
2880 00:24:44.251398
2881 00:24:44.251874 Set Vref, RX VrefLevel [Byte0]: 71
2882 00:24:44.254766 [Byte1]: 71
2883 00:24:44.259238
2884 00:24:44.259632 Final RX Vref Byte 0 = 59 to rank0
2885 00:24:44.262671 Final RX Vref Byte 1 = 49 to rank0
2886 00:24:44.265600 Final RX Vref Byte 0 = 59 to rank1
2887 00:24:44.269461 Final RX Vref Byte 1 = 49 to rank1==
2888 00:24:44.272437 Dram Type= 6, Freq= 0, CH_0, rank 0
2889 00:24:44.275888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2890 00:24:44.279057 ==
2891 00:24:44.279517 DQS Delay:
2892 00:24:44.279822 DQS0 = 0, DQS1 = 0
2893 00:24:44.282264 DQM Delay:
2894 00:24:44.282654 DQM0 = 123, DQM1 = 109
2895 00:24:44.285913 DQ Delay:
2896 00:24:44.289323 DQ0 =122, DQ1 =122, DQ2 =120, DQ3 =120
2897 00:24:44.292516 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2898 00:24:44.295780 DQ8 =102, DQ9 =94, DQ10 =110, DQ11 =106
2899 00:24:44.299527 DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =116
2900 00:24:44.299993
2901 00:24:44.300298
2902 00:24:44.306660 [DQSOSCAuto] RK0, (LSB)MR18= 0xd0a, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 405 ps
2903 00:24:44.309444 CH0 RK0: MR19=404, MR18=D0A
2904 00:24:44.316225 CH0_RK0: MR19=0x404, MR18=0xD0A, DQSOSC=405, MR23=63, INC=39, DEC=26
2905 00:24:44.316619
2906 00:24:44.319386 ----->DramcWriteLeveling(PI) begin...
2907 00:24:44.319779 ==
2908 00:24:44.322850 Dram Type= 6, Freq= 0, CH_0, rank 1
2909 00:24:44.326470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2910 00:24:44.326859 ==
2911 00:24:44.329380 Write leveling (Byte 0): 35 => 35
2912 00:24:44.333129 Write leveling (Byte 1): 30 => 30
2913 00:24:44.336088 DramcWriteLeveling(PI) end<-----
2914 00:24:44.336474
2915 00:24:44.336810 ==
2916 00:24:44.339200 Dram Type= 6, Freq= 0, CH_0, rank 1
2917 00:24:44.342823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2918 00:24:44.345815 ==
2919 00:24:44.346203 [Gating] SW mode calibration
2920 00:24:44.352833 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2921 00:24:44.359525 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2922 00:24:44.363234 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2923 00:24:44.369751 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2924 00:24:44.372925 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2925 00:24:44.376610 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2926 00:24:44.383092 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2927 00:24:44.386510 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2928 00:24:44.389364 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2929 00:24:44.396077 0 15 28 | B1->B0 | 2e2e 2c2c | 0 0 | (0 1) (1 0)
2930 00:24:44.399545 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
2931 00:24:44.402819 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2932 00:24:44.406140 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2933 00:24:44.412580 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2934 00:24:44.416055 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2935 00:24:44.419662 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2936 00:24:44.426084 1 0 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
2937 00:24:44.429097 1 0 28 | B1->B0 | 3d3d 4141 | 1 0 | (0 0) (0 0)
2938 00:24:44.432878 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2939 00:24:44.439627 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2940 00:24:44.443275 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2941 00:24:44.446292 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2942 00:24:44.452660 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2943 00:24:44.456208 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2944 00:24:44.459963 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2945 00:24:44.466446 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2946 00:24:44.469379 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2947 00:24:44.472685 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2948 00:24:44.480034 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2949 00:24:44.483124 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2950 00:24:44.486607 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2951 00:24:44.489604 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2952 00:24:44.496532 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2953 00:24:44.499845 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2954 00:24:44.503084 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2955 00:24:44.509754 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2956 00:24:44.512780 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2957 00:24:44.516337 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2958 00:24:44.523149 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2959 00:24:44.526362 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2960 00:24:44.529877 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2961 00:24:44.536325 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2962 00:24:44.540024 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2963 00:24:44.543270 Total UI for P1: 0, mck2ui 16
2964 00:24:44.546582 best dqsien dly found for B0: ( 1, 3, 28)
2965 00:24:44.550277 Total UI for P1: 0, mck2ui 16
2966 00:24:44.553399 best dqsien dly found for B1: ( 1, 3, 28)
2967 00:24:44.556422 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2968 00:24:44.559988 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2969 00:24:44.560379
2970 00:24:44.563473 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2971 00:24:44.566444 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2972 00:24:44.569888 [Gating] SW calibration Done
2973 00:24:44.570278 ==
2974 00:24:44.573391 Dram Type= 6, Freq= 0, CH_0, rank 1
2975 00:24:44.576248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2976 00:24:44.576636 ==
2977 00:24:44.579935 RX Vref Scan: 0
2978 00:24:44.580321
2979 00:24:44.580620 RX Vref 0 -> 0, step: 1
2980 00:24:44.583273
2981 00:24:44.583660 RX Delay -40 -> 252, step: 8
2982 00:24:44.589832 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2983 00:24:44.593449 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2984 00:24:44.596531 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2985 00:24:44.600138 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2986 00:24:44.603263 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2987 00:24:44.606674 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2988 00:24:44.613413 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2989 00:24:44.616770 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2990 00:24:44.620276 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2991 00:24:44.623348 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2992 00:24:44.627596 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2993 00:24:44.633203 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2994 00:24:44.636418 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2995 00:24:44.639839 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2996 00:24:44.643276 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2997 00:24:44.646388 iDelay=200, Bit 15, Center 111 (48 ~ 175) 128
2998 00:24:44.650117 ==
2999 00:24:44.653072 Dram Type= 6, Freq= 0, CH_0, rank 1
3000 00:24:44.656596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3001 00:24:44.657073 ==
3002 00:24:44.657373 DQS Delay:
3003 00:24:44.659739 DQS0 = 0, DQS1 = 0
3004 00:24:44.660104 DQM Delay:
3005 00:24:44.663213 DQM0 = 120, DQM1 = 108
3006 00:24:44.663672 DQ Delay:
3007 00:24:44.666711 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
3008 00:24:44.669825 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
3009 00:24:44.673306 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
3010 00:24:44.677036 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
3011 00:24:44.677514
3012 00:24:44.677966
3013 00:24:44.678412 ==
3014 00:24:44.679897 Dram Type= 6, Freq= 0, CH_0, rank 1
3015 00:24:44.686712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3016 00:24:44.687195 ==
3017 00:24:44.687502
3018 00:24:44.687900
3019 00:24:44.688285 TX Vref Scan disable
3020 00:24:44.690080 == TX Byte 0 ==
3021 00:24:44.693430 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
3022 00:24:44.697358 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
3023 00:24:44.700035 == TX Byte 1 ==
3024 00:24:44.703567 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3025 00:24:44.706751 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3026 00:24:44.710139 ==
3027 00:24:44.713142 Dram Type= 6, Freq= 0, CH_0, rank 1
3028 00:24:44.716542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3029 00:24:44.717128 ==
3030 00:24:44.728412 TX Vref=22, minBit 1, minWin=24, winSum=411
3031 00:24:44.731463 TX Vref=24, minBit 1, minWin=24, winSum=416
3032 00:24:44.735038 TX Vref=26, minBit 1, minWin=24, winSum=423
3033 00:24:44.738389 TX Vref=28, minBit 2, minWin=25, winSum=422
3034 00:24:44.741771 TX Vref=30, minBit 3, minWin=25, winSum=429
3035 00:24:44.744889 TX Vref=32, minBit 2, minWin=25, winSum=423
3036 00:24:44.751830 [TxChooseVref] Worse bit 3, Min win 25, Win sum 429, Final Vref 30
3037 00:24:44.752397
3038 00:24:44.755106 Final TX Range 1 Vref 30
3039 00:24:44.755582
3040 00:24:44.756002 ==
3041 00:24:44.758406 Dram Type= 6, Freq= 0, CH_0, rank 1
3042 00:24:44.762393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3043 00:24:44.762872 ==
3044 00:24:44.763180
3045 00:24:44.763454
3046 00:24:44.765237 TX Vref Scan disable
3047 00:24:44.768753 == TX Byte 0 ==
3048 00:24:44.772647 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
3049 00:24:44.775403 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
3050 00:24:44.779365 == TX Byte 1 ==
3051 00:24:44.781921 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3052 00:24:44.785158 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3053 00:24:44.785675
3054 00:24:44.788655 [DATLAT]
3055 00:24:44.789201 Freq=1200, CH0 RK1
3056 00:24:44.789579
3057 00:24:44.792038 DATLAT Default: 0xd
3058 00:24:44.792579 0, 0xFFFF, sum = 0
3059 00:24:44.795508 1, 0xFFFF, sum = 0
3060 00:24:44.796037 2, 0xFFFF, sum = 0
3061 00:24:44.798756 3, 0xFFFF, sum = 0
3062 00:24:44.799341 4, 0xFFFF, sum = 0
3063 00:24:44.801804 5, 0xFFFF, sum = 0
3064 00:24:44.802387 6, 0xFFFF, sum = 0
3065 00:24:44.805028 7, 0xFFFF, sum = 0
3066 00:24:44.805446 8, 0xFFFF, sum = 0
3067 00:24:44.808447 9, 0xFFFF, sum = 0
3068 00:24:44.808889 10, 0xFFFF, sum = 0
3069 00:24:44.811904 11, 0xFFFF, sum = 0
3070 00:24:44.812307 12, 0x0, sum = 1
3071 00:24:44.815552 13, 0x0, sum = 2
3072 00:24:44.816098 14, 0x0, sum = 3
3073 00:24:44.818594 15, 0x0, sum = 4
3074 00:24:44.819010 best_step = 13
3075 00:24:44.819377
3076 00:24:44.819662 ==
3077 00:24:44.821789 Dram Type= 6, Freq= 0, CH_0, rank 1
3078 00:24:44.828484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3079 00:24:44.828584 ==
3080 00:24:44.828677 RX Vref Scan: 0
3081 00:24:44.828800
3082 00:24:44.831710 RX Vref 0 -> 0, step: 1
3083 00:24:44.831777
3084 00:24:44.835214 RX Delay -21 -> 252, step: 4
3085 00:24:44.838366 iDelay=195, Bit 0, Center 116 (51 ~ 182) 132
3086 00:24:44.841697 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3087 00:24:44.844983 iDelay=195, Bit 2, Center 116 (51 ~ 182) 132
3088 00:24:44.852133 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3089 00:24:44.855428 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3090 00:24:44.858834 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3091 00:24:44.861878 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3092 00:24:44.865501 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3093 00:24:44.872230 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3094 00:24:44.875726 iDelay=195, Bit 9, Center 94 (31 ~ 158) 128
3095 00:24:44.879050 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3096 00:24:44.882615 iDelay=195, Bit 11, Center 104 (43 ~ 166) 124
3097 00:24:44.885570 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3098 00:24:44.892131 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3099 00:24:44.895763 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3100 00:24:44.899334 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3101 00:24:44.899734 ==
3102 00:24:44.902343 Dram Type= 6, Freq= 0, CH_0, rank 1
3103 00:24:44.905949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3104 00:24:44.906344 ==
3105 00:24:44.909025 DQS Delay:
3106 00:24:44.909415 DQS0 = 0, DQS1 = 0
3107 00:24:44.909716 DQM Delay:
3108 00:24:44.912696 DQM0 = 119, DQM1 = 107
3109 00:24:44.913139 DQ Delay:
3110 00:24:44.916289 DQ0 =116, DQ1 =122, DQ2 =116, DQ3 =112
3111 00:24:44.919442 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =126
3112 00:24:44.926002 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =104
3113 00:24:44.929354 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
3114 00:24:44.929749
3115 00:24:44.930060
3116 00:24:44.936218 [DQSOSCAuto] RK1, (LSB)MR18= 0x11f8, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 403 ps
3117 00:24:44.939616 CH0 RK1: MR19=403, MR18=11F8
3118 00:24:44.946047 CH0_RK1: MR19=0x403, MR18=0x11F8, DQSOSC=403, MR23=63, INC=40, DEC=26
3119 00:24:44.949183 [RxdqsGatingPostProcess] freq 1200
3120 00:24:44.952579 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3121 00:24:44.955750 best DQS0 dly(2T, 0.5T) = (0, 11)
3122 00:24:44.959385 best DQS1 dly(2T, 0.5T) = (0, 11)
3123 00:24:44.962753 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3124 00:24:44.965981 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3125 00:24:44.969263 best DQS0 dly(2T, 0.5T) = (0, 11)
3126 00:24:44.972769 best DQS1 dly(2T, 0.5T) = (0, 11)
3127 00:24:44.975841 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3128 00:24:44.979079 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3129 00:24:44.982440 Pre-setting of DQS Precalculation
3130 00:24:44.986156 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3131 00:24:44.986691 ==
3132 00:24:44.989309 Dram Type= 6, Freq= 0, CH_1, rank 0
3133 00:24:44.996003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3134 00:24:44.996476 ==
3135 00:24:44.999003 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3136 00:24:45.005897 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3137 00:24:45.014868 [CA 0] Center 37 (7~68) winsize 62
3138 00:24:45.018062 [CA 1] Center 37 (7~68) winsize 62
3139 00:24:45.021077 [CA 2] Center 35 (5~65) winsize 61
3140 00:24:45.024680 [CA 3] Center 34 (4~65) winsize 62
3141 00:24:45.028219 [CA 4] Center 34 (3~65) winsize 63
3142 00:24:45.031414 [CA 5] Center 33 (3~64) winsize 62
3143 00:24:45.031899
3144 00:24:45.034880 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3145 00:24:45.035365
3146 00:24:45.038116 [CATrainingPosCal] consider 1 rank data
3147 00:24:45.041157 u2DelayCellTimex100 = 270/100 ps
3148 00:24:45.044573 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3149 00:24:45.048400 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3150 00:24:45.054747 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3151 00:24:45.057654 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3152 00:24:45.061069 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
3153 00:24:45.064852 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3154 00:24:45.065335
3155 00:24:45.067998 CA PerBit enable=1, Macro0, CA PI delay=33
3156 00:24:45.068484
3157 00:24:45.071168 [CBTSetCACLKResult] CA Dly = 33
3158 00:24:45.071656 CS Dly: 5 (0~36)
3159 00:24:45.074518 ==
3160 00:24:45.075020 Dram Type= 6, Freq= 0, CH_1, rank 1
3161 00:24:45.081191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3162 00:24:45.081678 ==
3163 00:24:45.084232 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3164 00:24:45.091028 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3165 00:24:45.100499 [CA 0] Center 38 (8~68) winsize 61
3166 00:24:45.103642 [CA 1] Center 38 (7~69) winsize 63
3167 00:24:45.107396 [CA 2] Center 35 (5~66) winsize 62
3168 00:24:45.110174 [CA 3] Center 35 (5~65) winsize 61
3169 00:24:45.113640 [CA 4] Center 35 (5~65) winsize 61
3170 00:24:45.116742 [CA 5] Center 34 (4~64) winsize 61
3171 00:24:45.117137
3172 00:24:45.120537 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3173 00:24:45.121058
3174 00:24:45.123693 [CATrainingPosCal] consider 2 rank data
3175 00:24:45.127104 u2DelayCellTimex100 = 270/100 ps
3176 00:24:45.129997 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3177 00:24:45.133650 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3178 00:24:45.140038 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3179 00:24:45.143557 CA3 delay=35 (5~65),Diff = 1 PI (4 cell)
3180 00:24:45.146864 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
3181 00:24:45.149877 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3182 00:24:45.150266
3183 00:24:45.153583 CA PerBit enable=1, Macro0, CA PI delay=34
3184 00:24:45.154029
3185 00:24:45.156515 [CBTSetCACLKResult] CA Dly = 34
3186 00:24:45.156928 CS Dly: 6 (0~39)
3187 00:24:45.157237
3188 00:24:45.160078 ----->DramcWriteLeveling(PI) begin...
3189 00:24:45.163256 ==
3190 00:24:45.166624 Dram Type= 6, Freq= 0, CH_1, rank 0
3191 00:24:45.169958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3192 00:24:45.170352 ==
3193 00:24:45.173658 Write leveling (Byte 0): 26 => 26
3194 00:24:45.176577 Write leveling (Byte 1): 28 => 28
3195 00:24:45.180075 DramcWriteLeveling(PI) end<-----
3196 00:24:45.180489
3197 00:24:45.180838 ==
3198 00:24:45.183465 Dram Type= 6, Freq= 0, CH_1, rank 0
3199 00:24:45.186746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3200 00:24:45.187155 ==
3201 00:24:45.190509 [Gating] SW mode calibration
3202 00:24:45.196853 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3203 00:24:45.203078 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3204 00:24:45.206495 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3205 00:24:45.209756 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3206 00:24:45.213288 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3207 00:24:45.220052 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3208 00:24:45.223390 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3209 00:24:45.226670 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3210 00:24:45.233555 0 15 24 | B1->B0 | 2626 2323 | 0 0 | (0 0) (1 0)
3211 00:24:45.236733 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3212 00:24:45.239697 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3213 00:24:45.246626 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3214 00:24:45.249432 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3215 00:24:45.253554 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3216 00:24:45.259626 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3217 00:24:45.263172 1 0 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3218 00:24:45.266196 1 0 24 | B1->B0 | 4343 4545 | 0 0 | (0 0) (0 0)
3219 00:24:45.273168 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3220 00:24:45.276840 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3221 00:24:45.279607 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3222 00:24:45.286382 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3223 00:24:45.290052 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3224 00:24:45.293309 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3225 00:24:45.299707 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3226 00:24:45.303373 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3227 00:24:45.306349 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3228 00:24:45.313186 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3229 00:24:45.316212 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3230 00:24:45.319870 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3231 00:24:45.326454 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3232 00:24:45.329906 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3233 00:24:45.333193 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3234 00:24:45.336563 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3235 00:24:45.342852 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3236 00:24:45.346941 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3237 00:24:45.349602 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3238 00:24:45.356191 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3239 00:24:45.359383 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3240 00:24:45.363076 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3241 00:24:45.369704 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3242 00:24:45.372661 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3243 00:24:45.376743 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3244 00:24:45.379638 Total UI for P1: 0, mck2ui 16
3245 00:24:45.383189 best dqsien dly found for B0: ( 1, 3, 24)
3246 00:24:45.390134 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3247 00:24:45.390623 Total UI for P1: 0, mck2ui 16
3248 00:24:45.396084 best dqsien dly found for B1: ( 1, 3, 26)
3249 00:24:45.399446 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3250 00:24:45.403059 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3251 00:24:45.403537
3252 00:24:45.406087 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3253 00:24:45.409371 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3254 00:24:45.412793 [Gating] SW calibration Done
3255 00:24:45.413184 ==
3256 00:24:45.415916 Dram Type= 6, Freq= 0, CH_1, rank 0
3257 00:24:45.419513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3258 00:24:45.419905 ==
3259 00:24:45.422561 RX Vref Scan: 0
3260 00:24:45.422948
3261 00:24:45.423245 RX Vref 0 -> 0, step: 1
3262 00:24:45.423522
3263 00:24:45.426157 RX Delay -40 -> 252, step: 8
3264 00:24:45.432569 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3265 00:24:45.436145 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3266 00:24:45.438997 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3267 00:24:45.442566 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3268 00:24:45.446113 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3269 00:24:45.449019 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3270 00:24:45.455567 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3271 00:24:45.458776 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3272 00:24:45.462313 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3273 00:24:45.465899 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3274 00:24:45.469579 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3275 00:24:45.475948 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3276 00:24:45.479404 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3277 00:24:45.482688 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3278 00:24:45.485453 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3279 00:24:45.489241 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3280 00:24:45.492790 ==
3281 00:24:45.495493 Dram Type= 6, Freq= 0, CH_1, rank 0
3282 00:24:45.499457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3283 00:24:45.499951 ==
3284 00:24:45.500260 DQS Delay:
3285 00:24:45.502450 DQS0 = 0, DQS1 = 0
3286 00:24:45.502944 DQM Delay:
3287 00:24:45.505604 DQM0 = 120, DQM1 = 112
3288 00:24:45.505996 DQ Delay:
3289 00:24:45.509266 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =123
3290 00:24:45.512335 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =119
3291 00:24:45.515983 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3292 00:24:45.519425 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3293 00:24:45.519904
3294 00:24:45.520208
3295 00:24:45.520486 ==
3296 00:24:45.522426 Dram Type= 6, Freq= 0, CH_1, rank 0
3297 00:24:45.528915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3298 00:24:45.529368 ==
3299 00:24:45.529678
3300 00:24:45.529956
3301 00:24:45.530223 TX Vref Scan disable
3302 00:24:45.532390 == TX Byte 0 ==
3303 00:24:45.536215 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3304 00:24:45.543021 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3305 00:24:45.543509 == TX Byte 1 ==
3306 00:24:45.546399 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3307 00:24:45.552324 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3308 00:24:45.552747 ==
3309 00:24:45.556012 Dram Type= 6, Freq= 0, CH_1, rank 0
3310 00:24:45.558961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3311 00:24:45.559357 ==
3312 00:24:45.570704 TX Vref=22, minBit 1, minWin=24, winSum=406
3313 00:24:45.573543 TX Vref=24, minBit 3, minWin=25, winSum=410
3314 00:24:45.576838 TX Vref=26, minBit 3, minWin=25, winSum=414
3315 00:24:45.580298 TX Vref=28, minBit 8, minWin=25, winSum=421
3316 00:24:45.583492 TX Vref=30, minBit 11, minWin=25, winSum=422
3317 00:24:45.589980 TX Vref=32, minBit 9, minWin=25, winSum=424
3318 00:24:45.593668 [TxChooseVref] Worse bit 9, Min win 25, Win sum 424, Final Vref 32
3319 00:24:45.594154
3320 00:24:45.597348 Final TX Range 1 Vref 32
3321 00:24:45.597830
3322 00:24:45.598131 ==
3323 00:24:45.600362 Dram Type= 6, Freq= 0, CH_1, rank 0
3324 00:24:45.604005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3325 00:24:45.604491 ==
3326 00:24:45.606593
3327 00:24:45.606993
3328 00:24:45.607296 TX Vref Scan disable
3329 00:24:45.609781 == TX Byte 0 ==
3330 00:24:45.613469 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3331 00:24:45.616887 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3332 00:24:45.620147 == TX Byte 1 ==
3333 00:24:45.623472 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3334 00:24:45.626932 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3335 00:24:45.630090
3336 00:24:45.630568 [DATLAT]
3337 00:24:45.630876 Freq=1200, CH1 RK0
3338 00:24:45.631163
3339 00:24:45.633315 DATLAT Default: 0xd
3340 00:24:45.633711 0, 0xFFFF, sum = 0
3341 00:24:45.636674 1, 0xFFFF, sum = 0
3342 00:24:45.637141 2, 0xFFFF, sum = 0
3343 00:24:45.639866 3, 0xFFFF, sum = 0
3344 00:24:45.640351 4, 0xFFFF, sum = 0
3345 00:24:45.643631 5, 0xFFFF, sum = 0
3346 00:24:45.647198 6, 0xFFFF, sum = 0
3347 00:24:45.647725 7, 0xFFFF, sum = 0
3348 00:24:45.649837 8, 0xFFFF, sum = 0
3349 00:24:45.650249 9, 0xFFFF, sum = 0
3350 00:24:45.653198 10, 0xFFFF, sum = 0
3351 00:24:45.653597 11, 0xFFFF, sum = 0
3352 00:24:45.656532 12, 0x0, sum = 1
3353 00:24:45.656964 13, 0x0, sum = 2
3354 00:24:45.659640 14, 0x0, sum = 3
3355 00:24:45.660046 15, 0x0, sum = 4
3356 00:24:45.660360 best_step = 13
3357 00:24:45.663467
3358 00:24:45.663859 ==
3359 00:24:45.666588 Dram Type= 6, Freq= 0, CH_1, rank 0
3360 00:24:45.669651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3361 00:24:45.670142 ==
3362 00:24:45.670453 RX Vref Scan: 1
3363 00:24:45.670733
3364 00:24:45.673084 Set Vref Range= 32 -> 127
3365 00:24:45.673475
3366 00:24:45.676651 RX Vref 32 -> 127, step: 1
3367 00:24:45.677157
3368 00:24:45.680010 RX Delay -13 -> 252, step: 4
3369 00:24:45.680486
3370 00:24:45.682935 Set Vref, RX VrefLevel [Byte0]: 32
3371 00:24:45.686348 [Byte1]: 32
3372 00:24:45.686738
3373 00:24:45.689749 Set Vref, RX VrefLevel [Byte0]: 33
3374 00:24:45.693004 [Byte1]: 33
3375 00:24:45.696279
3376 00:24:45.696665 Set Vref, RX VrefLevel [Byte0]: 34
3377 00:24:45.699605 [Byte1]: 34
3378 00:24:45.704223
3379 00:24:45.704612 Set Vref, RX VrefLevel [Byte0]: 35
3380 00:24:45.707194 [Byte1]: 35
3381 00:24:45.711906
3382 00:24:45.712379 Set Vref, RX VrefLevel [Byte0]: 36
3383 00:24:45.715579 [Byte1]: 36
3384 00:24:45.720061
3385 00:24:45.720446 Set Vref, RX VrefLevel [Byte0]: 37
3386 00:24:45.723158 [Byte1]: 37
3387 00:24:45.728070
3388 00:24:45.728544 Set Vref, RX VrefLevel [Byte0]: 38
3389 00:24:45.731484 [Byte1]: 38
3390 00:24:45.735981
3391 00:24:45.736375 Set Vref, RX VrefLevel [Byte0]: 39
3392 00:24:45.738976 [Byte1]: 39
3393 00:24:45.743310
3394 00:24:45.743747 Set Vref, RX VrefLevel [Byte0]: 40
3395 00:24:45.747225 [Byte1]: 40
3396 00:24:45.751464
3397 00:24:45.751861 Set Vref, RX VrefLevel [Byte0]: 41
3398 00:24:45.755010 [Byte1]: 41
3399 00:24:45.759735
3400 00:24:45.760127 Set Vref, RX VrefLevel [Byte0]: 42
3401 00:24:45.762727 [Byte1]: 42
3402 00:24:45.767287
3403 00:24:45.767763 Set Vref, RX VrefLevel [Byte0]: 43
3404 00:24:45.770983 [Byte1]: 43
3405 00:24:45.775531
3406 00:24:45.776015 Set Vref, RX VrefLevel [Byte0]: 44
3407 00:24:45.778657 [Byte1]: 44
3408 00:24:45.783342
3409 00:24:45.783805 Set Vref, RX VrefLevel [Byte0]: 45
3410 00:24:45.786157 [Byte1]: 45
3411 00:24:45.791124
3412 00:24:45.791599 Set Vref, RX VrefLevel [Byte0]: 46
3413 00:24:45.794580 [Byte1]: 46
3414 00:24:45.798654
3415 00:24:45.799119 Set Vref, RX VrefLevel [Byte0]: 47
3416 00:24:45.802330 [Byte1]: 47
3417 00:24:45.806773
3418 00:24:45.807162 Set Vref, RX VrefLevel [Byte0]: 48
3419 00:24:45.809855 [Byte1]: 48
3420 00:24:45.814460
3421 00:24:45.814905 Set Vref, RX VrefLevel [Byte0]: 49
3422 00:24:45.818063 [Byte1]: 49
3423 00:24:45.823158
3424 00:24:45.823627 Set Vref, RX VrefLevel [Byte0]: 50
3425 00:24:45.825721 [Byte1]: 50
3426 00:24:45.830569
3427 00:24:45.831066 Set Vref, RX VrefLevel [Byte0]: 51
3428 00:24:45.834189 [Byte1]: 51
3429 00:24:45.838516
3430 00:24:45.838960 Set Vref, RX VrefLevel [Byte0]: 52
3431 00:24:45.841499 [Byte1]: 52
3432 00:24:45.846007
3433 00:24:45.846396 Set Vref, RX VrefLevel [Byte0]: 53
3434 00:24:45.849365 [Byte1]: 53
3435 00:24:45.853710
3436 00:24:45.854101 Set Vref, RX VrefLevel [Byte0]: 54
3437 00:24:45.857026 [Byte1]: 54
3438 00:24:45.861667
3439 00:24:45.862085 Set Vref, RX VrefLevel [Byte0]: 55
3440 00:24:45.865171 [Byte1]: 55
3441 00:24:45.870074
3442 00:24:45.870466 Set Vref, RX VrefLevel [Byte0]: 56
3443 00:24:45.872917 [Byte1]: 56
3444 00:24:45.877970
3445 00:24:45.878459 Set Vref, RX VrefLevel [Byte0]: 57
3446 00:24:45.881392 [Byte1]: 57
3447 00:24:45.885703
3448 00:24:45.886100 Set Vref, RX VrefLevel [Byte0]: 58
3449 00:24:45.889172 [Byte1]: 58
3450 00:24:45.893300
3451 00:24:45.893747 Set Vref, RX VrefLevel [Byte0]: 59
3452 00:24:45.896936 [Byte1]: 59
3453 00:24:45.901275
3454 00:24:45.901672 Set Vref, RX VrefLevel [Byte0]: 60
3455 00:24:45.904611 [Byte1]: 60
3456 00:24:45.909091
3457 00:24:45.909490 Set Vref, RX VrefLevel [Byte0]: 61
3458 00:24:45.912798 [Byte1]: 61
3459 00:24:45.917236
3460 00:24:45.917644 Set Vref, RX VrefLevel [Byte0]: 62
3461 00:24:45.920479 [Byte1]: 62
3462 00:24:45.925019
3463 00:24:45.925563 Set Vref, RX VrefLevel [Byte0]: 63
3464 00:24:45.928766 [Byte1]: 63
3465 00:24:45.933137
3466 00:24:45.933535 Set Vref, RX VrefLevel [Byte0]: 64
3467 00:24:45.936298 [Byte1]: 64
3468 00:24:45.941275
3469 00:24:45.941765 Set Vref, RX VrefLevel [Byte0]: 65
3470 00:24:45.944112 [Byte1]: 65
3471 00:24:45.948817
3472 00:24:45.949285 Set Vref, RX VrefLevel [Byte0]: 66
3473 00:24:45.952216 [Byte1]: 66
3474 00:24:45.956610
3475 00:24:45.957036 Set Vref, RX VrefLevel [Byte0]: 67
3476 00:24:45.959770 [Byte1]: 67
3477 00:24:45.964341
3478 00:24:45.964768 Final RX Vref Byte 0 = 52 to rank0
3479 00:24:45.967755 Final RX Vref Byte 1 = 50 to rank0
3480 00:24:45.971011 Final RX Vref Byte 0 = 52 to rank1
3481 00:24:45.974522 Final RX Vref Byte 1 = 50 to rank1==
3482 00:24:45.977748 Dram Type= 6, Freq= 0, CH_1, rank 0
3483 00:24:45.984901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3484 00:24:45.985354 ==
3485 00:24:45.985735 DQS Delay:
3486 00:24:45.986033 DQS0 = 0, DQS1 = 0
3487 00:24:45.987819 DQM Delay:
3488 00:24:45.988253 DQM0 = 119, DQM1 = 111
3489 00:24:45.991194 DQ Delay:
3490 00:24:45.994336 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =120
3491 00:24:45.997979 DQ4 =118, DQ5 =126, DQ6 =130, DQ7 =118
3492 00:24:46.001552 DQ8 =100, DQ9 =100, DQ10 =114, DQ11 =104
3493 00:24:46.004519 DQ12 =122, DQ13 =116, DQ14 =118, DQ15 =116
3494 00:24:46.005046
3495 00:24:46.005365
3496 00:24:46.014509 [DQSOSCAuto] RK0, (LSB)MR18= 0x71a, (MSB)MR19= 0x404, tDQSOscB0 = 400 ps tDQSOscB1 = 407 ps
3497 00:24:46.014987 CH1 RK0: MR19=404, MR18=71A
3498 00:24:46.020766 CH1_RK0: MR19=0x404, MR18=0x71A, DQSOSC=400, MR23=63, INC=40, DEC=27
3499 00:24:46.021169
3500 00:24:46.024654 ----->DramcWriteLeveling(PI) begin...
3501 00:24:46.025187 ==
3502 00:24:46.027960 Dram Type= 6, Freq= 0, CH_1, rank 1
3503 00:24:46.031080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3504 00:24:46.034112 ==
3505 00:24:46.034508 Write leveling (Byte 0): 26 => 26
3506 00:24:46.037603 Write leveling (Byte 1): 29 => 29
3507 00:24:46.040581 DramcWriteLeveling(PI) end<-----
3508 00:24:46.040992
3509 00:24:46.041297 ==
3510 00:24:46.044200 Dram Type= 6, Freq= 0, CH_1, rank 1
3511 00:24:46.051300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3512 00:24:46.051787 ==
3513 00:24:46.052101 [Gating] SW mode calibration
3514 00:24:46.060772 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3515 00:24:46.064090 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3516 00:24:46.071080 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3517 00:24:46.074053 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3518 00:24:46.077333 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3519 00:24:46.080621 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3520 00:24:46.087496 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3521 00:24:46.091206 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3522 00:24:46.094649 0 15 24 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 0)
3523 00:24:46.101156 0 15 28 | B1->B0 | 2323 2828 | 0 0 | (1 0) (1 0)
3524 00:24:46.104427 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3525 00:24:46.107982 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3526 00:24:46.114712 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3527 00:24:46.117845 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3528 00:24:46.121389 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3529 00:24:46.128110 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3530 00:24:46.131344 1 0 24 | B1->B0 | 3a3a 2b2b | 0 0 | (0 0) (0 0)
3531 00:24:46.134107 1 0 28 | B1->B0 | 4646 3a3a | 0 1 | (0 0) (0 0)
3532 00:24:46.141286 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3533 00:24:46.144905 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3534 00:24:46.148055 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3535 00:24:46.154693 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3536 00:24:46.157867 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3537 00:24:46.160987 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3538 00:24:46.164268 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3539 00:24:46.171084 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3540 00:24:46.174305 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3541 00:24:46.177844 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3542 00:24:46.184211 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3543 00:24:46.187581 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3544 00:24:46.190977 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3545 00:24:46.197499 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3546 00:24:46.200728 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3547 00:24:46.204049 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3548 00:24:46.210715 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3549 00:24:46.214079 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3550 00:24:46.217366 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3551 00:24:46.224034 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3552 00:24:46.227549 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3553 00:24:46.230578 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3554 00:24:46.237228 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3555 00:24:46.240767 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3556 00:24:46.244562 Total UI for P1: 0, mck2ui 16
3557 00:24:46.247541 best dqsien dly found for B1: ( 1, 3, 24)
3558 00:24:46.250901 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3559 00:24:46.254708 Total UI for P1: 0, mck2ui 16
3560 00:24:46.257459 best dqsien dly found for B0: ( 1, 3, 26)
3561 00:24:46.261044 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3562 00:24:46.264243 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3563 00:24:46.264635
3564 00:24:46.267785 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3565 00:24:46.274581 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3566 00:24:46.275029 [Gating] SW calibration Done
3567 00:24:46.275346 ==
3568 00:24:46.277772 Dram Type= 6, Freq= 0, CH_1, rank 1
3569 00:24:46.284141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3570 00:24:46.284544 ==
3571 00:24:46.284888 RX Vref Scan: 0
3572 00:24:46.285176
3573 00:24:46.287693 RX Vref 0 -> 0, step: 1
3574 00:24:46.288084
3575 00:24:46.290822 RX Delay -40 -> 252, step: 8
3576 00:24:46.294187 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3577 00:24:46.297592 iDelay=200, Bit 1, Center 111 (48 ~ 175) 128
3578 00:24:46.301263 iDelay=200, Bit 2, Center 107 (48 ~ 167) 120
3579 00:24:46.304352 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3580 00:24:46.310960 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
3581 00:24:46.314493 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3582 00:24:46.317440 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3583 00:24:46.321067 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3584 00:24:46.324465 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3585 00:24:46.330766 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3586 00:24:46.334146 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3587 00:24:46.337438 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3588 00:24:46.341282 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3589 00:24:46.344347 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3590 00:24:46.350867 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3591 00:24:46.354615 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3592 00:24:46.355140 ==
3593 00:24:46.357312 Dram Type= 6, Freq= 0, CH_1, rank 1
3594 00:24:46.360842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3595 00:24:46.361239 ==
3596 00:24:46.363935 DQS Delay:
3597 00:24:46.364324 DQS0 = 0, DQS1 = 0
3598 00:24:46.364665 DQM Delay:
3599 00:24:46.367818 DQM0 = 119, DQM1 = 112
3600 00:24:46.368391 DQ Delay:
3601 00:24:46.370501 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =119
3602 00:24:46.374093 DQ4 =123, DQ5 =131, DQ6 =127, DQ7 =115
3603 00:24:46.380614 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3604 00:24:46.384204 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3605 00:24:46.384768
3606 00:24:46.385132
3607 00:24:46.385422 ==
3608 00:24:46.387415 Dram Type= 6, Freq= 0, CH_1, rank 1
3609 00:24:46.390724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3610 00:24:46.391220 ==
3611 00:24:46.391669
3612 00:24:46.391962
3613 00:24:46.394128 TX Vref Scan disable
3614 00:24:46.394517 == TX Byte 0 ==
3615 00:24:46.400655 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3616 00:24:46.403712 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3617 00:24:46.404295 == TX Byte 1 ==
3618 00:24:46.410245 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3619 00:24:46.414141 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3620 00:24:46.414575 ==
3621 00:24:46.416981 Dram Type= 6, Freq= 0, CH_1, rank 1
3622 00:24:46.420356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3623 00:24:46.420895 ==
3624 00:24:46.433251 TX Vref=22, minBit 1, minWin=25, winSum=419
3625 00:24:46.436762 TX Vref=24, minBit 1, minWin=25, winSum=415
3626 00:24:46.440178 TX Vref=26, minBit 9, minWin=25, winSum=425
3627 00:24:46.443747 TX Vref=28, minBit 11, minWin=25, winSum=425
3628 00:24:46.446676 TX Vref=30, minBit 8, minWin=26, winSum=430
3629 00:24:46.453069 TX Vref=32, minBit 9, minWin=25, winSum=427
3630 00:24:46.456677 [TxChooseVref] Worse bit 8, Min win 26, Win sum 430, Final Vref 30
3631 00:24:46.456917
3632 00:24:46.459765 Final TX Range 1 Vref 30
3633 00:24:46.459944
3634 00:24:46.460077 ==
3635 00:24:46.462794 Dram Type= 6, Freq= 0, CH_1, rank 1
3636 00:24:46.466495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3637 00:24:46.466653 ==
3638 00:24:46.469494
3639 00:24:46.469624
3640 00:24:46.469720 TX Vref Scan disable
3641 00:24:46.473109 == TX Byte 0 ==
3642 00:24:46.476199 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3643 00:24:46.479505 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3644 00:24:46.482593 == TX Byte 1 ==
3645 00:24:46.486111 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3646 00:24:46.489446 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3647 00:24:46.492761
3648 00:24:46.492908 [DATLAT]
3649 00:24:46.492981 Freq=1200, CH1 RK1
3650 00:24:46.493048
3651 00:24:46.496881 DATLAT Default: 0xd
3652 00:24:46.497030 0, 0xFFFF, sum = 0
3653 00:24:46.499534 1, 0xFFFF, sum = 0
3654 00:24:46.499644 2, 0xFFFF, sum = 0
3655 00:24:46.503247 3, 0xFFFF, sum = 0
3656 00:24:46.506681 4, 0xFFFF, sum = 0
3657 00:24:46.506835 5, 0xFFFF, sum = 0
3658 00:24:46.509472 6, 0xFFFF, sum = 0
3659 00:24:46.509590 7, 0xFFFF, sum = 0
3660 00:24:46.513195 8, 0xFFFF, sum = 0
3661 00:24:46.513342 9, 0xFFFF, sum = 0
3662 00:24:46.515930 10, 0xFFFF, sum = 0
3663 00:24:46.516063 11, 0xFFFF, sum = 0
3664 00:24:46.519528 12, 0x0, sum = 1
3665 00:24:46.519696 13, 0x0, sum = 2
3666 00:24:46.523448 14, 0x0, sum = 3
3667 00:24:46.523626 15, 0x0, sum = 4
3668 00:24:46.523722 best_step = 13
3669 00:24:46.526318
3670 00:24:46.526491 ==
3671 00:24:46.529885 Dram Type= 6, Freq= 0, CH_1, rank 1
3672 00:24:46.532640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3673 00:24:46.532840 ==
3674 00:24:46.532988 RX Vref Scan: 0
3675 00:24:46.533085
3676 00:24:46.536235 RX Vref 0 -> 0, step: 1
3677 00:24:46.536377
3678 00:24:46.539329 RX Delay -13 -> 252, step: 4
3679 00:24:46.543412 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3680 00:24:46.549885 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3681 00:24:46.552925 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3682 00:24:46.556321 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3683 00:24:46.559815 iDelay=195, Bit 4, Center 122 (63 ~ 182) 120
3684 00:24:46.562785 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3685 00:24:46.569721 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3686 00:24:46.573168 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3687 00:24:46.576394 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3688 00:24:46.579718 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3689 00:24:46.583305 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3690 00:24:46.589572 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3691 00:24:46.592891 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3692 00:24:46.596236 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3693 00:24:46.599944 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3694 00:24:46.602956 iDelay=195, Bit 15, Center 122 (59 ~ 186) 128
3695 00:24:46.606452 ==
3696 00:24:46.606932 Dram Type= 6, Freq= 0, CH_1, rank 1
3697 00:24:46.612422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3698 00:24:46.612850 ==
3699 00:24:46.613162 DQS Delay:
3700 00:24:46.616299 DQS0 = 0, DQS1 = 0
3701 00:24:46.616694 DQM Delay:
3702 00:24:46.619224 DQM0 = 119, DQM1 = 113
3703 00:24:46.619618 DQ Delay:
3704 00:24:46.622867 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =118
3705 00:24:46.626077 DQ4 =122, DQ5 =130, DQ6 =126, DQ7 =116
3706 00:24:46.629685 DQ8 =98, DQ9 =102, DQ10 =114, DQ11 =106
3707 00:24:46.632800 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =122
3708 00:24:46.633274
3709 00:24:46.633580
3710 00:24:46.642718 [DQSOSCAuto] RK1, (LSB)MR18= 0x7ec, (MSB)MR19= 0x403, tDQSOscB0 = 418 ps tDQSOscB1 = 407 ps
3711 00:24:46.643198 CH1 RK1: MR19=403, MR18=7EC
3712 00:24:46.649718 CH1_RK1: MR19=0x403, MR18=0x7EC, DQSOSC=407, MR23=63, INC=39, DEC=26
3713 00:24:46.652773 [RxdqsGatingPostProcess] freq 1200
3714 00:24:46.659582 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3715 00:24:46.662881 best DQS0 dly(2T, 0.5T) = (0, 11)
3716 00:24:46.666676 best DQS1 dly(2T, 0.5T) = (0, 11)
3717 00:24:46.669426 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3718 00:24:46.673404 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3719 00:24:46.676361 best DQS0 dly(2T, 0.5T) = (0, 11)
3720 00:24:46.676879 best DQS1 dly(2T, 0.5T) = (0, 11)
3721 00:24:46.679489 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3722 00:24:46.683003 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3723 00:24:46.686536 Pre-setting of DQS Precalculation
3724 00:24:46.692812 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3725 00:24:46.699918 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3726 00:24:46.706086 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3727 00:24:46.706579
3728 00:24:46.706890
3729 00:24:46.709102 [Calibration Summary] 2400 Mbps
3730 00:24:46.712339 CH 0, Rank 0
3731 00:24:46.712874 SW Impedance : PASS
3732 00:24:46.716070 DUTY Scan : NO K
3733 00:24:46.716547 ZQ Calibration : PASS
3734 00:24:46.719219 Jitter Meter : NO K
3735 00:24:46.722224 CBT Training : PASS
3736 00:24:46.722619 Write leveling : PASS
3737 00:24:46.726126 RX DQS gating : PASS
3738 00:24:46.729396 RX DQ/DQS(RDDQC) : PASS
3739 00:24:46.729791 TX DQ/DQS : PASS
3740 00:24:46.732287 RX DATLAT : PASS
3741 00:24:46.735959 RX DQ/DQS(Engine): PASS
3742 00:24:46.736351 TX OE : NO K
3743 00:24:46.739114 All Pass.
3744 00:24:46.739585
3745 00:24:46.739889 CH 0, Rank 1
3746 00:24:46.742425 SW Impedance : PASS
3747 00:24:46.742823 DUTY Scan : NO K
3748 00:24:46.746154 ZQ Calibration : PASS
3749 00:24:46.748953 Jitter Meter : NO K
3750 00:24:46.749350 CBT Training : PASS
3751 00:24:46.752514 Write leveling : PASS
3752 00:24:46.753019 RX DQS gating : PASS
3753 00:24:46.756280 RX DQ/DQS(RDDQC) : PASS
3754 00:24:46.759691 TX DQ/DQS : PASS
3755 00:24:46.760201 RX DATLAT : PASS
3756 00:24:46.762329 RX DQ/DQS(Engine): PASS
3757 00:24:46.765685 TX OE : NO K
3758 00:24:46.766079 All Pass.
3759 00:24:46.766463
3760 00:24:46.766754 CH 1, Rank 0
3761 00:24:46.769146 SW Impedance : PASS
3762 00:24:46.772933 DUTY Scan : NO K
3763 00:24:46.773330 ZQ Calibration : PASS
3764 00:24:46.776007 Jitter Meter : NO K
3765 00:24:46.779334 CBT Training : PASS
3766 00:24:46.779728 Write leveling : PASS
3767 00:24:46.782762 RX DQS gating : PASS
3768 00:24:46.786168 RX DQ/DQS(RDDQC) : PASS
3769 00:24:46.786640 TX DQ/DQS : PASS
3770 00:24:46.788853 RX DATLAT : PASS
3771 00:24:46.792547 RX DQ/DQS(Engine): PASS
3772 00:24:46.793062 TX OE : NO K
3773 00:24:46.795439 All Pass.
3774 00:24:46.795828
3775 00:24:46.796134 CH 1, Rank 1
3776 00:24:46.799196 SW Impedance : PASS
3777 00:24:46.799669 DUTY Scan : NO K
3778 00:24:46.802609 ZQ Calibration : PASS
3779 00:24:46.805544 Jitter Meter : NO K
3780 00:24:46.805938 CBT Training : PASS
3781 00:24:46.809119 Write leveling : PASS
3782 00:24:46.809591 RX DQS gating : PASS
3783 00:24:46.812094 RX DQ/DQS(RDDQC) : PASS
3784 00:24:46.815900 TX DQ/DQS : PASS
3785 00:24:46.816376 RX DATLAT : PASS
3786 00:24:46.819423 RX DQ/DQS(Engine): PASS
3787 00:24:46.822053 TX OE : NO K
3788 00:24:46.822452 All Pass.
3789 00:24:46.822763
3790 00:24:46.826031 DramC Write-DBI off
3791 00:24:46.826548 PER_BANK_REFRESH: Hybrid Mode
3792 00:24:46.828731 TX_TRACKING: ON
3793 00:24:46.839071 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3794 00:24:46.842138 [FAST_K] Save calibration result to emmc
3795 00:24:46.845353 dramc_set_vcore_voltage set vcore to 650000
3796 00:24:46.845871 Read voltage for 600, 5
3797 00:24:46.848605 Vio18 = 0
3798 00:24:46.849027 Vcore = 650000
3799 00:24:46.849338 Vdram = 0
3800 00:24:46.852302 Vddq = 0
3801 00:24:46.852691 Vmddr = 0
3802 00:24:46.855282 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3803 00:24:46.862405 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3804 00:24:46.865236 MEM_TYPE=3, freq_sel=19
3805 00:24:46.868858 sv_algorithm_assistance_LP4_1600
3806 00:24:46.872164 ============ PULL DRAM RESETB DOWN ============
3807 00:24:46.875534 ========== PULL DRAM RESETB DOWN end =========
3808 00:24:46.879429 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3809 00:24:46.882746 ===================================
3810 00:24:46.885638 LPDDR4 DRAM CONFIGURATION
3811 00:24:46.889264 ===================================
3812 00:24:46.892524 EX_ROW_EN[0] = 0x0
3813 00:24:46.893035 EX_ROW_EN[1] = 0x0
3814 00:24:46.896028 LP4Y_EN = 0x0
3815 00:24:46.896496 WORK_FSP = 0x0
3816 00:24:46.899171 WL = 0x2
3817 00:24:46.899644 RL = 0x2
3818 00:24:46.902677 BL = 0x2
3819 00:24:46.903151 RPST = 0x0
3820 00:24:46.905565 RD_PRE = 0x0
3821 00:24:46.906040 WR_PRE = 0x1
3822 00:24:46.908989 WR_PST = 0x0
3823 00:24:46.911826 DBI_WR = 0x0
3824 00:24:46.912402 DBI_RD = 0x0
3825 00:24:46.915917 OTF = 0x1
3826 00:24:46.918829 ===================================
3827 00:24:46.922450 ===================================
3828 00:24:46.922847 ANA top config
3829 00:24:46.925596 ===================================
3830 00:24:46.928608 DLL_ASYNC_EN = 0
3831 00:24:46.932098 ALL_SLAVE_EN = 1
3832 00:24:46.932570 NEW_RANK_MODE = 1
3833 00:24:46.935150 DLL_IDLE_MODE = 1
3834 00:24:46.939158 LP45_APHY_COMB_EN = 1
3835 00:24:46.941951 TX_ODT_DIS = 1
3836 00:24:46.942346 NEW_8X_MODE = 1
3837 00:24:46.945073 ===================================
3838 00:24:46.948816 ===================================
3839 00:24:46.952099 data_rate = 1200
3840 00:24:46.955156 CKR = 1
3841 00:24:46.958588 DQ_P2S_RATIO = 8
3842 00:24:46.962130 ===================================
3843 00:24:46.965184 CA_P2S_RATIO = 8
3844 00:24:46.968477 DQ_CA_OPEN = 0
3845 00:24:46.968954 DQ_SEMI_OPEN = 0
3846 00:24:46.972076 CA_SEMI_OPEN = 0
3847 00:24:46.975413 CA_FULL_RATE = 0
3848 00:24:46.978611 DQ_CKDIV4_EN = 1
3849 00:24:46.982160 CA_CKDIV4_EN = 1
3850 00:24:46.985470 CA_PREDIV_EN = 0
3851 00:24:46.985940 PH8_DLY = 0
3852 00:24:46.988370 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3853 00:24:46.992016 DQ_AAMCK_DIV = 4
3854 00:24:46.995616 CA_AAMCK_DIV = 4
3855 00:24:46.998585 CA_ADMCK_DIV = 4
3856 00:24:47.001737 DQ_TRACK_CA_EN = 0
3857 00:24:47.002209 CA_PICK = 600
3858 00:24:47.005251 CA_MCKIO = 600
3859 00:24:47.008646 MCKIO_SEMI = 0
3860 00:24:47.011701 PLL_FREQ = 2288
3861 00:24:47.014961 DQ_UI_PI_RATIO = 32
3862 00:24:47.017987 CA_UI_PI_RATIO = 0
3863 00:24:47.021695 ===================================
3864 00:24:47.025054 ===================================
3865 00:24:47.028506 memory_type:LPDDR4
3866 00:24:47.029035 GP_NUM : 10
3867 00:24:47.031828 SRAM_EN : 1
3868 00:24:47.032304 MD32_EN : 0
3869 00:24:47.035197 ===================================
3870 00:24:47.038242 [ANA_INIT] >>>>>>>>>>>>>>
3871 00:24:47.041529 <<<<<< [CONFIGURE PHASE]: ANA_TX
3872 00:24:47.044954 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3873 00:24:47.048061 ===================================
3874 00:24:47.051645 data_rate = 1200,PCW = 0X5800
3875 00:24:47.055344 ===================================
3876 00:24:47.057795 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3877 00:24:47.061711 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3878 00:24:47.068134 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3879 00:24:47.071621 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3880 00:24:47.074901 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3881 00:24:47.081595 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3882 00:24:47.082070 [ANA_INIT] flow start
3883 00:24:47.085282 [ANA_INIT] PLL >>>>>>>>
3884 00:24:47.085753 [ANA_INIT] PLL <<<<<<<<
3885 00:24:47.088091 [ANA_INIT] MIDPI >>>>>>>>
3886 00:24:47.091474 [ANA_INIT] MIDPI <<<<<<<<
3887 00:24:47.095209 [ANA_INIT] DLL >>>>>>>>
3888 00:24:47.095684 [ANA_INIT] flow end
3889 00:24:47.098479 ============ LP4 DIFF to SE enter ============
3890 00:24:47.104856 ============ LP4 DIFF to SE exit ============
3891 00:24:47.105348 [ANA_INIT] <<<<<<<<<<<<<
3892 00:24:47.108405 [Flow] Enable top DCM control >>>>>
3893 00:24:47.111526 [Flow] Enable top DCM control <<<<<
3894 00:24:47.114409 Enable DLL master slave shuffle
3895 00:24:47.121174 ==============================================================
3896 00:24:47.121573 Gating Mode config
3897 00:24:47.127948 ==============================================================
3898 00:24:47.131547 Config description:
3899 00:24:47.141667 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3900 00:24:47.148082 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3901 00:24:47.151463 SELPH_MODE 0: By rank 1: By Phase
3902 00:24:47.157699 ==============================================================
3903 00:24:47.161130 GAT_TRACK_EN = 1
3904 00:24:47.161522 RX_GATING_MODE = 2
3905 00:24:47.164734 RX_GATING_TRACK_MODE = 2
3906 00:24:47.168348 SELPH_MODE = 1
3907 00:24:47.171799 PICG_EARLY_EN = 1
3908 00:24:47.174422 VALID_LAT_VALUE = 1
3909 00:24:47.181516 ==============================================================
3910 00:24:47.184836 Enter into Gating configuration >>>>
3911 00:24:47.187736 Exit from Gating configuration <<<<
3912 00:24:47.190779 Enter into DVFS_PRE_config >>>>>
3913 00:24:47.201676 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3914 00:24:47.204825 Exit from DVFS_PRE_config <<<<<
3915 00:24:47.207955 Enter into PICG configuration >>>>
3916 00:24:47.211045 Exit from PICG configuration <<<<
3917 00:24:47.214066 [RX_INPUT] configuration >>>>>
3918 00:24:47.217490 [RX_INPUT] configuration <<<<<
3919 00:24:47.221277 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3920 00:24:47.227837 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3921 00:24:47.234332 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3922 00:24:47.237291 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3923 00:24:47.244436 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3924 00:24:47.250912 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3925 00:24:47.253814 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3926 00:24:47.260696 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3927 00:24:47.263860 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3928 00:24:47.267364 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3929 00:24:47.270645 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3930 00:24:47.277167 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3931 00:24:47.280448 ===================================
3932 00:24:47.281080 LPDDR4 DRAM CONFIGURATION
3933 00:24:47.284072 ===================================
3934 00:24:47.287376 EX_ROW_EN[0] = 0x0
3935 00:24:47.290507 EX_ROW_EN[1] = 0x0
3936 00:24:47.290898 LP4Y_EN = 0x0
3937 00:24:47.293929 WORK_FSP = 0x0
3938 00:24:47.294318 WL = 0x2
3939 00:24:47.297528 RL = 0x2
3940 00:24:47.297917 BL = 0x2
3941 00:24:47.300640 RPST = 0x0
3942 00:24:47.301062 RD_PRE = 0x0
3943 00:24:47.304337 WR_PRE = 0x1
3944 00:24:47.304784 WR_PST = 0x0
3945 00:24:47.307320 DBI_WR = 0x0
3946 00:24:47.307711 DBI_RD = 0x0
3947 00:24:47.310351 OTF = 0x1
3948 00:24:47.313910 ===================================
3949 00:24:47.317410 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3950 00:24:47.320566 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3951 00:24:47.327930 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3952 00:24:47.330966 ===================================
3953 00:24:47.331442 LPDDR4 DRAM CONFIGURATION
3954 00:24:47.334077 ===================================
3955 00:24:47.337362 EX_ROW_EN[0] = 0x10
3956 00:24:47.337755 EX_ROW_EN[1] = 0x0
3957 00:24:47.340742 LP4Y_EN = 0x0
3958 00:24:47.344186 WORK_FSP = 0x0
3959 00:24:47.344657 WL = 0x2
3960 00:24:47.347193 RL = 0x2
3961 00:24:47.347667 BL = 0x2
3962 00:24:47.350975 RPST = 0x0
3963 00:24:47.351444 RD_PRE = 0x0
3964 00:24:47.353960 WR_PRE = 0x1
3965 00:24:47.354430 WR_PST = 0x0
3966 00:24:47.357329 DBI_WR = 0x0
3967 00:24:47.357719 DBI_RD = 0x0
3968 00:24:47.360396 OTF = 0x1
3969 00:24:47.364356 ===================================
3970 00:24:47.367267 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3971 00:24:47.373127 nWR fixed to 30
3972 00:24:47.376221 [ModeRegInit_LP4] CH0 RK0
3973 00:24:47.376610 [ModeRegInit_LP4] CH0 RK1
3974 00:24:47.380059 [ModeRegInit_LP4] CH1 RK0
3975 00:24:47.383324 [ModeRegInit_LP4] CH1 RK1
3976 00:24:47.383799 match AC timing 17
3977 00:24:47.389447 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3978 00:24:47.393265 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3979 00:24:47.396220 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3980 00:24:47.402774 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3981 00:24:47.406126 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3982 00:24:47.406598 ==
3983 00:24:47.409236 Dram Type= 6, Freq= 0, CH_0, rank 0
3984 00:24:47.412924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3985 00:24:47.413405 ==
3986 00:24:47.419288 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3987 00:24:47.426353 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3988 00:24:47.428905 [CA 0] Center 36 (6~67) winsize 62
3989 00:24:47.432511 [CA 1] Center 36 (6~67) winsize 62
3990 00:24:47.435850 [CA 2] Center 34 (4~65) winsize 62
3991 00:24:47.439799 [CA 3] Center 34 (3~65) winsize 63
3992 00:24:47.442424 [CA 4] Center 34 (3~65) winsize 63
3993 00:24:47.446000 [CA 5] Center 33 (2~64) winsize 63
3994 00:24:47.446471
3995 00:24:47.449005 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3996 00:24:47.449447
3997 00:24:47.452464 [CATrainingPosCal] consider 1 rank data
3998 00:24:47.455799 u2DelayCellTimex100 = 270/100 ps
3999 00:24:47.459161 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
4000 00:24:47.462640 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
4001 00:24:47.466254 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4002 00:24:47.469406 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4003 00:24:47.472985 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4004 00:24:47.478764 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4005 00:24:47.479226
4006 00:24:47.482094 CA PerBit enable=1, Macro0, CA PI delay=33
4007 00:24:47.482486
4008 00:24:47.485298 [CBTSetCACLKResult] CA Dly = 33
4009 00:24:47.485687 CS Dly: 4 (0~35)
4010 00:24:47.485990 ==
4011 00:24:47.488743 Dram Type= 6, Freq= 0, CH_0, rank 1
4012 00:24:47.492309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4013 00:24:47.496029 ==
4014 00:24:47.499109 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4015 00:24:47.505253 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4016 00:24:47.509373 [CA 0] Center 36 (6~67) winsize 62
4017 00:24:47.512151 [CA 1] Center 36 (6~67) winsize 62
4018 00:24:47.515304 [CA 2] Center 35 (4~66) winsize 63
4019 00:24:47.519135 [CA 3] Center 34 (4~65) winsize 62
4020 00:24:47.522387 [CA 4] Center 34 (3~65) winsize 63
4021 00:24:47.525277 [CA 5] Center 33 (3~64) winsize 62
4022 00:24:47.525670
4023 00:24:47.529147 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4024 00:24:47.529621
4025 00:24:47.532029 [CATrainingPosCal] consider 2 rank data
4026 00:24:47.535684 u2DelayCellTimex100 = 270/100 ps
4027 00:24:47.538939 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
4028 00:24:47.542192 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
4029 00:24:47.545134 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4030 00:24:47.548559 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4031 00:24:47.555206 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4032 00:24:47.558520 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4033 00:24:47.558918
4034 00:24:47.562349 CA PerBit enable=1, Macro0, CA PI delay=33
4035 00:24:47.562829
4036 00:24:47.565470 [CBTSetCACLKResult] CA Dly = 33
4037 00:24:47.565866 CS Dly: 5 (0~37)
4038 00:24:47.566171
4039 00:24:47.569160 ----->DramcWriteLeveling(PI) begin...
4040 00:24:47.569638 ==
4041 00:24:47.572108 Dram Type= 6, Freq= 0, CH_0, rank 0
4042 00:24:47.578826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4043 00:24:47.579305 ==
4044 00:24:47.582369 Write leveling (Byte 0): 33 => 33
4045 00:24:47.585605 Write leveling (Byte 1): 33 => 33
4046 00:24:47.586079 DramcWriteLeveling(PI) end<-----
4047 00:24:47.586389
4048 00:24:47.588862 ==
4049 00:24:47.591643 Dram Type= 6, Freq= 0, CH_0, rank 0
4050 00:24:47.595359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4051 00:24:47.595833 ==
4052 00:24:47.598718 [Gating] SW mode calibration
4053 00:24:47.605620 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4054 00:24:47.608632 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4055 00:24:47.615174 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4056 00:24:47.618257 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4057 00:24:47.621431 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4058 00:24:47.628472 0 9 12 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (1 0)
4059 00:24:47.631395 0 9 16 | B1->B0 | 2a2a 2323 | 0 0 | (1 1) (0 0)
4060 00:24:47.634998 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4061 00:24:47.641632 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4062 00:24:47.645237 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4063 00:24:47.648115 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4064 00:24:47.654656 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4065 00:24:47.658503 0 10 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
4066 00:24:47.661357 0 10 12 | B1->B0 | 2727 3838 | 1 0 | (0 0) (1 1)
4067 00:24:47.668145 0 10 16 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
4068 00:24:47.671530 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4069 00:24:47.675225 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4070 00:24:47.678395 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4071 00:24:47.685381 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4072 00:24:47.688142 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4073 00:24:47.691608 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4074 00:24:47.698209 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4075 00:24:47.701700 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 00:24:47.704827 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4077 00:24:47.711683 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4078 00:24:47.714854 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4079 00:24:47.717992 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4080 00:24:47.724742 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4081 00:24:47.728082 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4082 00:24:47.731315 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4083 00:24:47.737962 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4084 00:24:47.741144 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4085 00:24:47.744661 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4086 00:24:47.751299 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4087 00:24:47.754337 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4088 00:24:47.757927 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4089 00:24:47.764615 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4090 00:24:47.767592 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4091 00:24:47.770975 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4092 00:24:47.774356 Total UI for P1: 0, mck2ui 16
4093 00:24:47.778112 best dqsien dly found for B0: ( 0, 13, 14)
4094 00:24:47.780913 Total UI for P1: 0, mck2ui 16
4095 00:24:47.784071 best dqsien dly found for B1: ( 0, 13, 14)
4096 00:24:47.787602 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4097 00:24:47.790983 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4098 00:24:47.791458
4099 00:24:47.797797 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4100 00:24:47.801279 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4101 00:24:47.801754 [Gating] SW calibration Done
4102 00:24:47.804536 ==
4103 00:24:47.807912 Dram Type= 6, Freq= 0, CH_0, rank 0
4104 00:24:47.811003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4105 00:24:47.811404 ==
4106 00:24:47.811712 RX Vref Scan: 0
4107 00:24:47.811999
4108 00:24:47.814500 RX Vref 0 -> 0, step: 1
4109 00:24:47.814893
4110 00:24:47.817402 RX Delay -230 -> 252, step: 16
4111 00:24:47.821186 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4112 00:24:47.824167 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4113 00:24:47.830757 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4114 00:24:47.834138 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4115 00:24:47.837468 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4116 00:24:47.840919 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4117 00:24:47.844200 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4118 00:24:47.850733 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4119 00:24:47.854264 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4120 00:24:47.857773 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4121 00:24:47.860812 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4122 00:24:47.867692 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4123 00:24:47.870911 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4124 00:24:47.874141 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4125 00:24:47.877674 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4126 00:24:47.883967 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4127 00:24:47.884431 ==
4128 00:24:47.887826 Dram Type= 6, Freq= 0, CH_0, rank 0
4129 00:24:47.890836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4130 00:24:47.891236 ==
4131 00:24:47.891546 DQS Delay:
4132 00:24:47.894553 DQS0 = 0, DQS1 = 0
4133 00:24:47.895026 DQM Delay:
4134 00:24:47.897676 DQM0 = 48, DQM1 = 39
4135 00:24:47.898155 DQ Delay:
4136 00:24:47.900952 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =41
4137 00:24:47.904042 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4138 00:24:47.907370 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =25
4139 00:24:47.910965 DQ12 =41, DQ13 =41, DQ14 =57, DQ15 =49
4140 00:24:47.911441
4141 00:24:47.911752
4142 00:24:47.912035 ==
4143 00:24:47.914337 Dram Type= 6, Freq= 0, CH_0, rank 0
4144 00:24:47.917217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4145 00:24:47.917765 ==
4146 00:24:47.918236
4147 00:24:47.920364
4148 00:24:47.920901 TX Vref Scan disable
4149 00:24:47.924794 == TX Byte 0 ==
4150 00:24:47.927612 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4151 00:24:47.930592 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4152 00:24:47.934146 == TX Byte 1 ==
4153 00:24:47.937145 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4154 00:24:47.940413 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4155 00:24:47.940802 ==
4156 00:24:47.943593 Dram Type= 6, Freq= 0, CH_0, rank 0
4157 00:24:47.950315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4158 00:24:47.950852 ==
4159 00:24:47.951202
4160 00:24:47.951481
4161 00:24:47.951748 TX Vref Scan disable
4162 00:24:47.954973 == TX Byte 0 ==
4163 00:24:47.958403 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4164 00:24:47.964806 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4165 00:24:47.965338 == TX Byte 1 ==
4166 00:24:47.968246 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4167 00:24:47.974799 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4168 00:24:47.975221
4169 00:24:47.975545 [DATLAT]
4170 00:24:47.975854 Freq=600, CH0 RK0
4171 00:24:47.976144
4172 00:24:47.978181 DATLAT Default: 0x9
4173 00:24:47.978586 0, 0xFFFF, sum = 0
4174 00:24:47.981693 1, 0xFFFF, sum = 0
4175 00:24:47.982246 2, 0xFFFF, sum = 0
4176 00:24:47.984678 3, 0xFFFF, sum = 0
4177 00:24:47.988035 4, 0xFFFF, sum = 0
4178 00:24:47.988449 5, 0xFFFF, sum = 0
4179 00:24:47.991605 6, 0xFFFF, sum = 0
4180 00:24:47.992092 7, 0xFFFF, sum = 0
4181 00:24:47.994972 8, 0x0, sum = 1
4182 00:24:47.995392 9, 0x0, sum = 2
4183 00:24:47.995706 10, 0x0, sum = 3
4184 00:24:47.998339 11, 0x0, sum = 4
4185 00:24:47.998893 best_step = 9
4186 00:24:47.999351
4187 00:24:47.999783 ==
4188 00:24:48.001627 Dram Type= 6, Freq= 0, CH_0, rank 0
4189 00:24:48.007906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4190 00:24:48.008477 ==
4191 00:24:48.009038 RX Vref Scan: 1
4192 00:24:48.009428
4193 00:24:48.011382 RX Vref 0 -> 0, step: 1
4194 00:24:48.011870
4195 00:24:48.015021 RX Delay -179 -> 252, step: 8
4196 00:24:48.015511
4197 00:24:48.018222 Set Vref, RX VrefLevel [Byte0]: 59
4198 00:24:48.021218 [Byte1]: 49
4199 00:24:48.021592
4200 00:24:48.024420 Final RX Vref Byte 0 = 59 to rank0
4201 00:24:48.028037 Final RX Vref Byte 1 = 49 to rank0
4202 00:24:48.031105 Final RX Vref Byte 0 = 59 to rank1
4203 00:24:48.034772 Final RX Vref Byte 1 = 49 to rank1==
4204 00:24:48.037580 Dram Type= 6, Freq= 0, CH_0, rank 0
4205 00:24:48.041180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4206 00:24:48.041523 ==
4207 00:24:48.044556 DQS Delay:
4208 00:24:48.044978 DQS0 = 0, DQS1 = 0
4209 00:24:48.045265 DQM Delay:
4210 00:24:48.048118 DQM0 = 50, DQM1 = 37
4211 00:24:48.048580 DQ Delay:
4212 00:24:48.051065 DQ0 =48, DQ1 =48, DQ2 =48, DQ3 =48
4213 00:24:48.054426 DQ4 =52, DQ5 =40, DQ6 =60, DQ7 =56
4214 00:24:48.057848 DQ8 =32, DQ9 =20, DQ10 =36, DQ11 =32
4215 00:24:48.061226 DQ12 =44, DQ13 =40, DQ14 =48, DQ15 =44
4216 00:24:48.061565
4217 00:24:48.061843
4218 00:24:48.071267 [DQSOSCAuto] RK0, (LSB)MR18= 0x625c, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 391 ps
4219 00:24:48.074738 CH0 RK0: MR19=808, MR18=625C
4220 00:24:48.077533 CH0_RK0: MR19=0x808, MR18=0x625C, DQSOSC=391, MR23=63, INC=171, DEC=114
4221 00:24:48.081070
4222 00:24:48.084747 ----->DramcWriteLeveling(PI) begin...
4223 00:24:48.085114 ==
4224 00:24:48.087749 Dram Type= 6, Freq= 0, CH_0, rank 1
4225 00:24:48.091426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4226 00:24:48.091896 ==
4227 00:24:48.094244 Write leveling (Byte 0): 35 => 35
4228 00:24:48.097976 Write leveling (Byte 1): 31 => 31
4229 00:24:48.101088 DramcWriteLeveling(PI) end<-----
4230 00:24:48.101511
4231 00:24:48.101825 ==
4232 00:24:48.104484 Dram Type= 6, Freq= 0, CH_0, rank 1
4233 00:24:48.107481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4234 00:24:48.107914 ==
4235 00:24:48.111120 [Gating] SW mode calibration
4236 00:24:48.117844 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4237 00:24:48.124430 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4238 00:24:48.127929 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4239 00:24:48.130991 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4240 00:24:48.137613 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4241 00:24:48.141093 0 9 12 | B1->B0 | 3333 3232 | 1 0 | (1 1) (0 1)
4242 00:24:48.144287 0 9 16 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
4243 00:24:48.147981 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4244 00:24:48.154402 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4245 00:24:48.157578 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4246 00:24:48.161144 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4247 00:24:48.167707 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4248 00:24:48.170766 0 10 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 1)
4249 00:24:48.174323 0 10 12 | B1->B0 | 3030 3737 | 1 1 | (0 0) (0 0)
4250 00:24:48.180681 0 10 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
4251 00:24:48.183832 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4252 00:24:48.187125 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4253 00:24:48.193764 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4254 00:24:48.197586 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4255 00:24:48.200612 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4256 00:24:48.207338 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4257 00:24:48.210665 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4258 00:24:48.213746 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 00:24:48.220380 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 00:24:48.223953 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 00:24:48.227135 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 00:24:48.233656 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 00:24:48.237112 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 00:24:48.240500 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4265 00:24:48.247135 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4266 00:24:48.250563 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4267 00:24:48.253773 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4268 00:24:48.260496 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4269 00:24:48.263612 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4270 00:24:48.266764 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4271 00:24:48.273547 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4272 00:24:48.277132 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4273 00:24:48.280128 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4274 00:24:48.286636 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4275 00:24:48.286993 Total UI for P1: 0, mck2ui 16
4276 00:24:48.290507 best dqsien dly found for B0: ( 0, 13, 14)
4277 00:24:48.293374 Total UI for P1: 0, mck2ui 16
4278 00:24:48.296785 best dqsien dly found for B1: ( 0, 13, 14)
4279 00:24:48.303333 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4280 00:24:48.307105 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4281 00:24:48.307645
4282 00:24:48.310291 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4283 00:24:48.313561 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4284 00:24:48.316846 [Gating] SW calibration Done
4285 00:24:48.317459 ==
4286 00:24:48.319906 Dram Type= 6, Freq= 0, CH_0, rank 1
4287 00:24:48.323347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4288 00:24:48.323851 ==
4289 00:24:48.326881 RX Vref Scan: 0
4290 00:24:48.327400
4291 00:24:48.327932 RX Vref 0 -> 0, step: 1
4292 00:24:48.328368
4293 00:24:48.329961 RX Delay -230 -> 252, step: 16
4294 00:24:48.333390 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4295 00:24:48.340178 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4296 00:24:48.343244 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4297 00:24:48.347014 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4298 00:24:48.350225 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4299 00:24:48.353521 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4300 00:24:48.360228 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4301 00:24:48.363165 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4302 00:24:48.366805 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4303 00:24:48.370191 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4304 00:24:48.376659 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4305 00:24:48.379816 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4306 00:24:48.383248 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4307 00:24:48.386795 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4308 00:24:48.393247 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4309 00:24:48.396609 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4310 00:24:48.396996 ==
4311 00:24:48.399956 Dram Type= 6, Freq= 0, CH_0, rank 1
4312 00:24:48.402924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4313 00:24:48.403272 ==
4314 00:24:48.406247 DQS Delay:
4315 00:24:48.406570 DQS0 = 0, DQS1 = 0
4316 00:24:48.406852 DQM Delay:
4317 00:24:48.409870 DQM0 = 47, DQM1 = 42
4318 00:24:48.410189 DQ Delay:
4319 00:24:48.412936 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =41
4320 00:24:48.416568 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4321 00:24:48.419569 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4322 00:24:48.422997 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =49
4323 00:24:48.423488
4324 00:24:48.423910
4325 00:24:48.424192 ==
4326 00:24:48.426516 Dram Type= 6, Freq= 0, CH_0, rank 1
4327 00:24:48.433122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4328 00:24:48.433479 ==
4329 00:24:48.433783
4330 00:24:48.434063
4331 00:24:48.434358 TX Vref Scan disable
4332 00:24:48.436852 == TX Byte 0 ==
4333 00:24:48.439846 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4334 00:24:48.443252 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4335 00:24:48.446561 == TX Byte 1 ==
4336 00:24:48.450023 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4337 00:24:48.456477 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4338 00:24:48.456976 ==
4339 00:24:48.459853 Dram Type= 6, Freq= 0, CH_0, rank 1
4340 00:24:48.463176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4341 00:24:48.463659 ==
4342 00:24:48.464089
4343 00:24:48.464513
4344 00:24:48.466290 TX Vref Scan disable
4345 00:24:48.469834 == TX Byte 0 ==
4346 00:24:48.473180 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4347 00:24:48.476309 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4348 00:24:48.479890 == TX Byte 1 ==
4349 00:24:48.482935 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4350 00:24:48.486421 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4351 00:24:48.486881
4352 00:24:48.487307 [DATLAT]
4353 00:24:48.489615 Freq=600, CH0 RK1
4354 00:24:48.489959
4355 00:24:48.490376 DATLAT Default: 0x9
4356 00:24:48.493121 0, 0xFFFF, sum = 0
4357 00:24:48.496546 1, 0xFFFF, sum = 0
4358 00:24:48.497023 2, 0xFFFF, sum = 0
4359 00:24:48.499840 3, 0xFFFF, sum = 0
4360 00:24:48.500201 4, 0xFFFF, sum = 0
4361 00:24:48.503362 5, 0xFFFF, sum = 0
4362 00:24:48.503709 6, 0xFFFF, sum = 0
4363 00:24:48.506332 7, 0xFFFF, sum = 0
4364 00:24:48.506683 8, 0x0, sum = 1
4365 00:24:48.509801 9, 0x0, sum = 2
4366 00:24:48.510149 10, 0x0, sum = 3
4367 00:24:48.510459 11, 0x0, sum = 4
4368 00:24:48.512965 best_step = 9
4369 00:24:48.513313
4370 00:24:48.513598 ==
4371 00:24:48.516263 Dram Type= 6, Freq= 0, CH_0, rank 1
4372 00:24:48.519780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4373 00:24:48.520269 ==
4374 00:24:48.522723 RX Vref Scan: 0
4375 00:24:48.523235
4376 00:24:48.523726 RX Vref 0 -> 0, step: 1
4377 00:24:48.526206
4378 00:24:48.526759 RX Delay -163 -> 252, step: 8
4379 00:24:48.533887 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4380 00:24:48.537210 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4381 00:24:48.540258 iDelay=205, Bit 2, Center 44 (-99 ~ 188) 288
4382 00:24:48.543850 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4383 00:24:48.547227 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4384 00:24:48.553699 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4385 00:24:48.557187 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4386 00:24:48.560058 iDelay=205, Bit 7, Center 52 (-91 ~ 196) 288
4387 00:24:48.563539 iDelay=205, Bit 8, Center 36 (-107 ~ 180) 288
4388 00:24:48.570088 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4389 00:24:48.573396 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4390 00:24:48.576728 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4391 00:24:48.580303 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4392 00:24:48.583601 iDelay=205, Bit 13, Center 44 (-99 ~ 188) 288
4393 00:24:48.589910 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4394 00:24:48.593384 iDelay=205, Bit 15, Center 48 (-91 ~ 188) 280
4395 00:24:48.593738 ==
4396 00:24:48.596256 Dram Type= 6, Freq= 0, CH_0, rank 1
4397 00:24:48.599952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4398 00:24:48.600392 ==
4399 00:24:48.603268 DQS Delay:
4400 00:24:48.603595 DQS0 = 0, DQS1 = 0
4401 00:24:48.606420 DQM Delay:
4402 00:24:48.606727 DQM0 = 48, DQM1 = 41
4403 00:24:48.607020 DQ Delay:
4404 00:24:48.610007 DQ0 =48, DQ1 =48, DQ2 =44, DQ3 =44
4405 00:24:48.613321 DQ4 =48, DQ5 =40, DQ6 =60, DQ7 =52
4406 00:24:48.616572 DQ8 =36, DQ9 =28, DQ10 =40, DQ11 =32
4407 00:24:48.619940 DQ12 =48, DQ13 =44, DQ14 =52, DQ15 =48
4408 00:24:48.620343
4409 00:24:48.620647
4410 00:24:48.629786 [DQSOSCAuto] RK1, (LSB)MR18= 0x6734, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 390 ps
4411 00:24:48.633221 CH0 RK1: MR19=808, MR18=6734
4412 00:24:48.636399 CH0_RK1: MR19=0x808, MR18=0x6734, DQSOSC=390, MR23=63, INC=172, DEC=114
4413 00:24:48.640047 [RxdqsGatingPostProcess] freq 600
4414 00:24:48.646624 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4415 00:24:48.650196 Pre-setting of DQS Precalculation
4416 00:24:48.653202 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4417 00:24:48.653779 ==
4418 00:24:48.656689 Dram Type= 6, Freq= 0, CH_1, rank 0
4419 00:24:48.663146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4420 00:24:48.663685 ==
4421 00:24:48.666377 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4422 00:24:48.673016 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4423 00:24:48.676375 [CA 0] Center 35 (5~66) winsize 62
4424 00:24:48.679981 [CA 1] Center 35 (5~66) winsize 62
4425 00:24:48.682982 [CA 2] Center 34 (3~65) winsize 63
4426 00:24:48.686586 [CA 3] Center 33 (3~64) winsize 62
4427 00:24:48.689648 [CA 4] Center 34 (3~65) winsize 63
4428 00:24:48.693014 [CA 5] Center 33 (3~64) winsize 62
4429 00:24:48.693475
4430 00:24:48.696514 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4431 00:24:48.697045
4432 00:24:48.700112 [CATrainingPosCal] consider 1 rank data
4433 00:24:48.702895 u2DelayCellTimex100 = 270/100 ps
4434 00:24:48.706438 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4435 00:24:48.712988 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4436 00:24:48.716368 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
4437 00:24:48.719693 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4438 00:24:48.723040 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4439 00:24:48.726153 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4440 00:24:48.726708
4441 00:24:48.729586 CA PerBit enable=1, Macro0, CA PI delay=33
4442 00:24:48.730102
4443 00:24:48.732842 [CBTSetCACLKResult] CA Dly = 33
4444 00:24:48.733247 CS Dly: 5 (0~36)
4445 00:24:48.736072 ==
4446 00:24:48.736476 Dram Type= 6, Freq= 0, CH_1, rank 1
4447 00:24:48.742724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4448 00:24:48.743249 ==
4449 00:24:48.746191 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4450 00:24:48.752915 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4451 00:24:48.756567 [CA 0] Center 35 (5~66) winsize 62
4452 00:24:48.759673 [CA 1] Center 35 (5~66) winsize 62
4453 00:24:48.763152 [CA 2] Center 34 (4~65) winsize 62
4454 00:24:48.766794 [CA 3] Center 34 (4~65) winsize 62
4455 00:24:48.769804 [CA 4] Center 34 (4~64) winsize 61
4456 00:24:48.773330 [CA 5] Center 33 (3~64) winsize 62
4457 00:24:48.773849
4458 00:24:48.776491 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4459 00:24:48.777010
4460 00:24:48.779749 [CATrainingPosCal] consider 2 rank data
4461 00:24:48.783302 u2DelayCellTimex100 = 270/100 ps
4462 00:24:48.786622 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4463 00:24:48.790047 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4464 00:24:48.796521 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4465 00:24:48.799940 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4466 00:24:48.803037 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4467 00:24:48.806653 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4468 00:24:48.806978
4469 00:24:48.809669 CA PerBit enable=1, Macro0, CA PI delay=33
4470 00:24:48.809999
4471 00:24:48.813228 [CBTSetCACLKResult] CA Dly = 33
4472 00:24:48.813594 CS Dly: 5 (0~36)
4473 00:24:48.813913
4474 00:24:48.816489 ----->DramcWriteLeveling(PI) begin...
4475 00:24:48.819764 ==
4476 00:24:48.820259 Dram Type= 6, Freq= 0, CH_1, rank 0
4477 00:24:48.826648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4478 00:24:48.827144 ==
4479 00:24:48.829683 Write leveling (Byte 0): 27 => 27
4480 00:24:48.833016 Write leveling (Byte 1): 31 => 31
4481 00:24:48.836696 DramcWriteLeveling(PI) end<-----
4482 00:24:48.837101
4483 00:24:48.837575 ==
4484 00:24:48.839503 Dram Type= 6, Freq= 0, CH_1, rank 0
4485 00:24:48.843038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4486 00:24:48.843603 ==
4487 00:24:48.846702 [Gating] SW mode calibration
4488 00:24:48.853274 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4489 00:24:48.856387 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4490 00:24:48.862910 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4491 00:24:48.866536 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4492 00:24:48.869378 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4493 00:24:48.876056 0 9 12 | B1->B0 | 2f2f 2d2d | 0 1 | (1 0) (1 1)
4494 00:24:48.879728 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4495 00:24:48.883093 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4496 00:24:48.889370 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4497 00:24:48.892920 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4498 00:24:48.895935 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4499 00:24:48.902693 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4500 00:24:48.905961 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4501 00:24:48.909152 0 10 12 | B1->B0 | 3d3d 3b3b | 0 1 | (0 0) (0 0)
4502 00:24:48.916221 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4503 00:24:48.919186 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4504 00:24:48.922565 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4505 00:24:48.929448 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4506 00:24:48.932514 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4507 00:24:48.935982 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4508 00:24:48.942721 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4509 00:24:48.945847 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4510 00:24:48.948998 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4511 00:24:48.955522 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4512 00:24:48.959295 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4513 00:24:48.962347 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4514 00:24:48.968800 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4515 00:24:48.972483 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4516 00:24:48.975411 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4517 00:24:48.982265 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4518 00:24:48.985846 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4519 00:24:48.989239 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4520 00:24:48.995759 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4521 00:24:48.998860 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4522 00:24:49.002246 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4523 00:24:49.009190 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4524 00:24:49.012168 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4525 00:24:49.015402 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4526 00:24:49.018744 Total UI for P1: 0, mck2ui 16
4527 00:24:49.022146 best dqsien dly found for B0: ( 0, 13, 8)
4528 00:24:49.025714 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4529 00:24:49.028622 Total UI for P1: 0, mck2ui 16
4530 00:24:49.032324 best dqsien dly found for B1: ( 0, 13, 12)
4531 00:24:49.035714 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4532 00:24:49.042281 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4533 00:24:49.042693
4534 00:24:49.045596 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4535 00:24:49.048966 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4536 00:24:49.052259 [Gating] SW calibration Done
4537 00:24:49.052620 ==
4538 00:24:49.055490 Dram Type= 6, Freq= 0, CH_1, rank 0
4539 00:24:49.058664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4540 00:24:49.058998 ==
4541 00:24:49.059298 RX Vref Scan: 0
4542 00:24:49.062184
4543 00:24:49.062524 RX Vref 0 -> 0, step: 1
4544 00:24:49.062810
4545 00:24:49.065325 RX Delay -230 -> 252, step: 16
4546 00:24:49.068741 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4547 00:24:49.075411 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4548 00:24:49.078779 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4549 00:24:49.081919 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4550 00:24:49.085151 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4551 00:24:49.088663 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4552 00:24:49.095135 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4553 00:24:49.098575 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4554 00:24:49.101767 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4555 00:24:49.105119 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4556 00:24:49.111806 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4557 00:24:49.115183 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4558 00:24:49.118601 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4559 00:24:49.121296 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4560 00:24:49.127730 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4561 00:24:49.130928 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4562 00:24:49.131002 ==
4563 00:24:49.134319 Dram Type= 6, Freq= 0, CH_1, rank 0
4564 00:24:49.137654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4565 00:24:49.137724 ==
4566 00:24:49.140831 DQS Delay:
4567 00:24:49.140894 DQS0 = 0, DQS1 = 0
4568 00:24:49.140951 DQM Delay:
4569 00:24:49.144589 DQM0 = 50, DQM1 = 42
4570 00:24:49.144681 DQ Delay:
4571 00:24:49.147535 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =49
4572 00:24:49.150846 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4573 00:24:49.154215 DQ8 =25, DQ9 =33, DQ10 =41, DQ11 =41
4574 00:24:49.157470 DQ12 =57, DQ13 =49, DQ14 =41, DQ15 =49
4575 00:24:49.157535
4576 00:24:49.157590
4577 00:24:49.157642 ==
4578 00:24:49.160902 Dram Type= 6, Freq= 0, CH_1, rank 0
4579 00:24:49.167327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4580 00:24:49.167392 ==
4581 00:24:49.167451
4582 00:24:49.167501
4583 00:24:49.167551 TX Vref Scan disable
4584 00:24:49.170974 == TX Byte 0 ==
4585 00:24:49.174500 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4586 00:24:49.180953 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4587 00:24:49.181037 == TX Byte 1 ==
4588 00:24:49.184615 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4589 00:24:49.191236 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4590 00:24:49.191314 ==
4591 00:24:49.194445 Dram Type= 6, Freq= 0, CH_1, rank 0
4592 00:24:49.197593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4593 00:24:49.197691 ==
4594 00:24:49.197786
4595 00:24:49.197846
4596 00:24:49.200811 TX Vref Scan disable
4597 00:24:49.204322 == TX Byte 0 ==
4598 00:24:49.207832 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4599 00:24:49.211150 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4600 00:24:49.214138 == TX Byte 1 ==
4601 00:24:49.217566 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4602 00:24:49.221207 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4603 00:24:49.221285
4604 00:24:49.221345 [DATLAT]
4605 00:24:49.224249 Freq=600, CH1 RK0
4606 00:24:49.224329
4607 00:24:49.224389 DATLAT Default: 0x9
4608 00:24:49.227670 0, 0xFFFF, sum = 0
4609 00:24:49.227744 1, 0xFFFF, sum = 0
4610 00:24:49.231308 2, 0xFFFF, sum = 0
4611 00:24:49.231374 3, 0xFFFF, sum = 0
4612 00:24:49.234434 4, 0xFFFF, sum = 0
4613 00:24:49.237662 5, 0xFFFF, sum = 0
4614 00:24:49.237725 6, 0xFFFF, sum = 0
4615 00:24:49.240909 7, 0xFFFF, sum = 0
4616 00:24:49.240972 8, 0x0, sum = 1
4617 00:24:49.241025 9, 0x0, sum = 2
4618 00:24:49.244496 10, 0x0, sum = 3
4619 00:24:49.244584 11, 0x0, sum = 4
4620 00:24:49.247677 best_step = 9
4621 00:24:49.247739
4622 00:24:49.247790 ==
4623 00:24:49.251025 Dram Type= 6, Freq= 0, CH_1, rank 0
4624 00:24:49.254334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4625 00:24:49.254405 ==
4626 00:24:49.257679 RX Vref Scan: 1
4627 00:24:49.257742
4628 00:24:49.257795 RX Vref 0 -> 0, step: 1
4629 00:24:49.257847
4630 00:24:49.260852 RX Delay -179 -> 252, step: 8
4631 00:24:49.260916
4632 00:24:49.264484 Set Vref, RX VrefLevel [Byte0]: 52
4633 00:24:49.267533 [Byte1]: 50
4634 00:24:49.271619
4635 00:24:49.271687 Final RX Vref Byte 0 = 52 to rank0
4636 00:24:49.274745 Final RX Vref Byte 1 = 50 to rank0
4637 00:24:49.278275 Final RX Vref Byte 0 = 52 to rank1
4638 00:24:49.281829 Final RX Vref Byte 1 = 50 to rank1==
4639 00:24:49.284691 Dram Type= 6, Freq= 0, CH_1, rank 0
4640 00:24:49.291507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4641 00:24:49.291575 ==
4642 00:24:49.291634 DQS Delay:
4643 00:24:49.291687 DQS0 = 0, DQS1 = 0
4644 00:24:49.295030 DQM Delay:
4645 00:24:49.295093 DQM0 = 48, DQM1 = 40
4646 00:24:49.298321 DQ Delay:
4647 00:24:49.301701 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4648 00:24:49.301766 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =44
4649 00:24:49.304910 DQ8 =28, DQ9 =28, DQ10 =44, DQ11 =32
4650 00:24:49.311870 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =48
4651 00:24:49.311942
4652 00:24:49.311998
4653 00:24:49.318420 [DQSOSCAuto] RK0, (LSB)MR18= 0x4d74, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4654 00:24:49.321761 CH1 RK0: MR19=808, MR18=4D74
4655 00:24:49.328590 CH1_RK0: MR19=0x808, MR18=0x4D74, DQSOSC=388, MR23=63, INC=174, DEC=116
4656 00:24:49.328692
4657 00:24:49.331390 ----->DramcWriteLeveling(PI) begin...
4658 00:24:49.331459 ==
4659 00:24:49.334850 Dram Type= 6, Freq= 0, CH_1, rank 1
4660 00:24:49.337943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4661 00:24:49.338007 ==
4662 00:24:49.341328 Write leveling (Byte 0): 28 => 28
4663 00:24:49.344683 Write leveling (Byte 1): 28 => 28
4664 00:24:49.348125 DramcWriteLeveling(PI) end<-----
4665 00:24:49.348193
4666 00:24:49.348248 ==
4667 00:24:49.351613 Dram Type= 6, Freq= 0, CH_1, rank 1
4668 00:24:49.354723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4669 00:24:49.354802 ==
4670 00:24:49.358207 [Gating] SW mode calibration
4671 00:24:49.364618 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4672 00:24:49.371035 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4673 00:24:49.374825 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4674 00:24:49.378246 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4675 00:24:49.384409 0 9 8 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
4676 00:24:49.388016 0 9 12 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 0)
4677 00:24:49.391372 0 9 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4678 00:24:49.397852 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4679 00:24:49.401024 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4680 00:24:49.404629 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4681 00:24:49.410996 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4682 00:24:49.414641 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4683 00:24:49.417971 0 10 8 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
4684 00:24:49.424261 0 10 12 | B1->B0 | 4242 3333 | 0 0 | (0 0) (0 0)
4685 00:24:49.427702 0 10 16 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
4686 00:24:49.431314 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4687 00:24:49.437793 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4688 00:24:49.440868 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4689 00:24:49.444419 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4690 00:24:49.451016 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4691 00:24:49.454412 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4692 00:24:49.457704 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4693 00:24:49.464068 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4694 00:24:49.467829 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4695 00:24:49.470828 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4696 00:24:49.477502 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4697 00:24:49.481254 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4698 00:24:49.484629 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4699 00:24:49.487705 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4700 00:24:49.494568 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4701 00:24:49.497710 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4702 00:24:49.501223 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4703 00:24:49.507907 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4704 00:24:49.510978 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4705 00:24:49.514217 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4706 00:24:49.520904 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4707 00:24:49.524320 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4708 00:24:49.527873 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4709 00:24:49.534558 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4710 00:24:49.537569 Total UI for P1: 0, mck2ui 16
4711 00:24:49.541021 best dqsien dly found for B0: ( 0, 13, 12)
4712 00:24:49.541088 Total UI for P1: 0, mck2ui 16
4713 00:24:49.547552 best dqsien dly found for B1: ( 0, 13, 12)
4714 00:24:49.551055 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4715 00:24:49.554173 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4716 00:24:49.554264
4717 00:24:49.557668 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4718 00:24:49.560694 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4719 00:24:49.563988 [Gating] SW calibration Done
4720 00:24:49.564054 ==
4721 00:24:49.567205 Dram Type= 6, Freq= 0, CH_1, rank 1
4722 00:24:49.570909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4723 00:24:49.570977 ==
4724 00:24:49.573940 RX Vref Scan: 0
4725 00:24:49.574003
4726 00:24:49.574055 RX Vref 0 -> 0, step: 1
4727 00:24:49.577210
4728 00:24:49.577272 RX Delay -230 -> 252, step: 16
4729 00:24:49.583774 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4730 00:24:49.587731 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4731 00:24:49.590991 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4732 00:24:49.593803 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4733 00:24:49.597317 iDelay=218, Bit 4, Center 57 (-86 ~ 201) 288
4734 00:24:49.604329 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4735 00:24:49.607434 iDelay=218, Bit 6, Center 57 (-86 ~ 201) 288
4736 00:24:49.610486 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4737 00:24:49.613912 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4738 00:24:49.617492 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4739 00:24:49.624156 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4740 00:24:49.627184 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4741 00:24:49.630778 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4742 00:24:49.634007 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4743 00:24:49.640601 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4744 00:24:49.643883 iDelay=218, Bit 15, Center 65 (-86 ~ 217) 304
4745 00:24:49.643950 ==
4746 00:24:49.647251 Dram Type= 6, Freq= 0, CH_1, rank 1
4747 00:24:49.650787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4748 00:24:49.650853 ==
4749 00:24:49.653948 DQS Delay:
4750 00:24:49.654014 DQS0 = 0, DQS1 = 0
4751 00:24:49.654070 DQM Delay:
4752 00:24:49.657412 DQM0 = 52, DQM1 = 47
4753 00:24:49.657474 DQ Delay:
4754 00:24:49.660543 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4755 00:24:49.663699 DQ4 =57, DQ5 =65, DQ6 =57, DQ7 =49
4756 00:24:49.667201 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4757 00:24:49.670813 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =65
4758 00:24:49.670878
4759 00:24:49.670934
4760 00:24:49.670985 ==
4761 00:24:49.673648 Dram Type= 6, Freq= 0, CH_1, rank 1
4762 00:24:49.680335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4763 00:24:49.680405 ==
4764 00:24:49.680463
4765 00:24:49.680519
4766 00:24:49.680570 TX Vref Scan disable
4767 00:24:49.684083 == TX Byte 0 ==
4768 00:24:49.687663 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4769 00:24:49.693990 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4770 00:24:49.694059 == TX Byte 1 ==
4771 00:24:49.697552 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4772 00:24:49.704005 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4773 00:24:49.704072 ==
4774 00:24:49.707434 Dram Type= 6, Freq= 0, CH_1, rank 1
4775 00:24:49.711090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4776 00:24:49.711153 ==
4777 00:24:49.711208
4778 00:24:49.711263
4779 00:24:49.713996 TX Vref Scan disable
4780 00:24:49.714060 == TX Byte 0 ==
4781 00:24:49.720587 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4782 00:24:49.724211 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4783 00:24:49.724287 == TX Byte 1 ==
4784 00:24:49.730860 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4785 00:24:49.734190 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4786 00:24:49.734256
4787 00:24:49.734312 [DATLAT]
4788 00:24:49.737649 Freq=600, CH1 RK1
4789 00:24:49.737713
4790 00:24:49.737766 DATLAT Default: 0x9
4791 00:24:49.740599 0, 0xFFFF, sum = 0
4792 00:24:49.740690 1, 0xFFFF, sum = 0
4793 00:24:49.744110 2, 0xFFFF, sum = 0
4794 00:24:49.744175 3, 0xFFFF, sum = 0
4795 00:24:49.747109 4, 0xFFFF, sum = 0
4796 00:24:49.750723 5, 0xFFFF, sum = 0
4797 00:24:49.750785 6, 0xFFFF, sum = 0
4798 00:24:49.754346 7, 0xFFFF, sum = 0
4799 00:24:49.754412 8, 0x0, sum = 1
4800 00:24:49.754466 9, 0x0, sum = 2
4801 00:24:49.757271 10, 0x0, sum = 3
4802 00:24:49.757331 11, 0x0, sum = 4
4803 00:24:49.760807 best_step = 9
4804 00:24:49.760869
4805 00:24:49.760925 ==
4806 00:24:49.763980 Dram Type= 6, Freq= 0, CH_1, rank 1
4807 00:24:49.767167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4808 00:24:49.767228 ==
4809 00:24:49.770540 RX Vref Scan: 0
4810 00:24:49.770601
4811 00:24:49.770657 RX Vref 0 -> 0, step: 1
4812 00:24:49.770707
4813 00:24:49.774165 RX Delay -163 -> 252, step: 8
4814 00:24:49.781012 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4815 00:24:49.784374 iDelay=205, Bit 1, Center 44 (-91 ~ 180) 272
4816 00:24:49.787701 iDelay=205, Bit 2, Center 40 (-99 ~ 180) 280
4817 00:24:49.790987 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4818 00:24:49.794530 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4819 00:24:49.800859 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4820 00:24:49.804191 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4821 00:24:49.807524 iDelay=205, Bit 7, Center 48 (-91 ~ 188) 280
4822 00:24:49.811147 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4823 00:24:49.814289 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4824 00:24:49.820922 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4825 00:24:49.824191 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4826 00:24:49.827926 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4827 00:24:49.830874 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4828 00:24:49.837789 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4829 00:24:49.840662 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4830 00:24:49.840779 ==
4831 00:24:49.844423 Dram Type= 6, Freq= 0, CH_1, rank 1
4832 00:24:49.847490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4833 00:24:49.847563 ==
4834 00:24:49.850594 DQS Delay:
4835 00:24:49.850679 DQS0 = 0, DQS1 = 0
4836 00:24:49.850753 DQM Delay:
4837 00:24:49.854103 DQM0 = 49, DQM1 = 42
4838 00:24:49.854170 DQ Delay:
4839 00:24:49.857717 DQ0 =56, DQ1 =44, DQ2 =40, DQ3 =44
4840 00:24:49.860909 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4841 00:24:49.864393 DQ8 =32, DQ9 =32, DQ10 =44, DQ11 =36
4842 00:24:49.867460 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =52
4843 00:24:49.867526
4844 00:24:49.867581
4845 00:24:49.877612 [DQSOSCAuto] RK1, (LSB)MR18= 0x5f26, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 391 ps
4846 00:24:49.877683 CH1 RK1: MR19=808, MR18=5F26
4847 00:24:49.884372 CH1_RK1: MR19=0x808, MR18=0x5F26, DQSOSC=391, MR23=63, INC=171, DEC=114
4848 00:24:49.887527 [RxdqsGatingPostProcess] freq 600
4849 00:24:49.894273 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4850 00:24:49.897711 Pre-setting of DQS Precalculation
4851 00:24:49.901132 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4852 00:24:49.907329 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4853 00:24:49.917213 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4854 00:24:49.917311
4855 00:24:49.917394
4856 00:24:49.920886 [Calibration Summary] 1200 Mbps
4857 00:24:49.920973 CH 0, Rank 0
4858 00:24:49.923870 SW Impedance : PASS
4859 00:24:49.923932 DUTY Scan : NO K
4860 00:24:49.927348 ZQ Calibration : PASS
4861 00:24:49.927418 Jitter Meter : NO K
4862 00:24:49.930778 CBT Training : PASS
4863 00:24:49.933858 Write leveling : PASS
4864 00:24:49.933925 RX DQS gating : PASS
4865 00:24:49.937600 RX DQ/DQS(RDDQC) : PASS
4866 00:24:49.940920 TX DQ/DQS : PASS
4867 00:24:49.940985 RX DATLAT : PASS
4868 00:24:49.943950 RX DQ/DQS(Engine): PASS
4869 00:24:49.947271 TX OE : NO K
4870 00:24:49.947334 All Pass.
4871 00:24:49.947388
4872 00:24:49.947440 CH 0, Rank 1
4873 00:24:49.950328 SW Impedance : PASS
4874 00:24:49.953825 DUTY Scan : NO K
4875 00:24:49.953887 ZQ Calibration : PASS
4876 00:24:49.956923 Jitter Meter : NO K
4877 00:24:49.960415 CBT Training : PASS
4878 00:24:49.960476 Write leveling : PASS
4879 00:24:49.963417 RX DQS gating : PASS
4880 00:24:49.966990 RX DQ/DQS(RDDQC) : PASS
4881 00:24:49.967056 TX DQ/DQS : PASS
4882 00:24:49.970515 RX DATLAT : PASS
4883 00:24:49.973856 RX DQ/DQS(Engine): PASS
4884 00:24:49.973917 TX OE : NO K
4885 00:24:49.973970 All Pass.
4886 00:24:49.976844
4887 00:24:49.976909 CH 1, Rank 0
4888 00:24:49.980098 SW Impedance : PASS
4889 00:24:49.980160 DUTY Scan : NO K
4890 00:24:49.983575 ZQ Calibration : PASS
4891 00:24:49.983635 Jitter Meter : NO K
4892 00:24:49.987091 CBT Training : PASS
4893 00:24:49.990325 Write leveling : PASS
4894 00:24:49.990391 RX DQS gating : PASS
4895 00:24:49.993339 RX DQ/DQS(RDDQC) : PASS
4896 00:24:49.996711 TX DQ/DQS : PASS
4897 00:24:49.996784 RX DATLAT : PASS
4898 00:24:50.000292 RX DQ/DQS(Engine): PASS
4899 00:24:50.003682 TX OE : NO K
4900 00:24:50.003756 All Pass.
4901 00:24:50.003814
4902 00:24:50.003867 CH 1, Rank 1
4903 00:24:50.006926 SW Impedance : PASS
4904 00:24:50.010230 DUTY Scan : NO K
4905 00:24:50.010298 ZQ Calibration : PASS
4906 00:24:50.013204 Jitter Meter : NO K
4907 00:24:50.016798 CBT Training : PASS
4908 00:24:50.016865 Write leveling : PASS
4909 00:24:50.020220 RX DQS gating : PASS
4910 00:24:50.023834 RX DQ/DQS(RDDQC) : PASS
4911 00:24:50.023900 TX DQ/DQS : PASS
4912 00:24:50.026755 RX DATLAT : PASS
4913 00:24:50.030237 RX DQ/DQS(Engine): PASS
4914 00:24:50.030306 TX OE : NO K
4915 00:24:50.030362 All Pass.
4916 00:24:50.030414
4917 00:24:50.033721 DramC Write-DBI off
4918 00:24:50.036764 PER_BANK_REFRESH: Hybrid Mode
4919 00:24:50.036833 TX_TRACKING: ON
4920 00:24:50.046615 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4921 00:24:50.050128 [FAST_K] Save calibration result to emmc
4922 00:24:50.053383 dramc_set_vcore_voltage set vcore to 662500
4923 00:24:50.056815 Read voltage for 933, 3
4924 00:24:50.056884 Vio18 = 0
4925 00:24:50.060205 Vcore = 662500
4926 00:24:50.060273 Vdram = 0
4927 00:24:50.060329 Vddq = 0
4928 00:24:50.060382 Vmddr = 0
4929 00:24:50.066649 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4930 00:24:50.069952 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4931 00:24:50.073389 MEM_TYPE=3, freq_sel=17
4932 00:24:50.076537 sv_algorithm_assistance_LP4_1600
4933 00:24:50.079930 ============ PULL DRAM RESETB DOWN ============
4934 00:24:50.086937 ========== PULL DRAM RESETB DOWN end =========
4935 00:24:50.089873 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4936 00:24:50.093367 ===================================
4937 00:24:50.096776 LPDDR4 DRAM CONFIGURATION
4938 00:24:50.100264 ===================================
4939 00:24:50.100333 EX_ROW_EN[0] = 0x0
4940 00:24:50.103295 EX_ROW_EN[1] = 0x0
4941 00:24:50.103365 LP4Y_EN = 0x0
4942 00:24:50.106864 WORK_FSP = 0x0
4943 00:24:50.106931 WL = 0x3
4944 00:24:50.110005 RL = 0x3
4945 00:24:50.110069 BL = 0x2
4946 00:24:50.113259 RPST = 0x0
4947 00:24:50.113323 RD_PRE = 0x0
4948 00:24:50.116700 WR_PRE = 0x1
4949 00:24:50.116809 WR_PST = 0x0
4950 00:24:50.120182 DBI_WR = 0x0
4951 00:24:50.123178 DBI_RD = 0x0
4952 00:24:50.123242 OTF = 0x1
4953 00:24:50.126695 ===================================
4954 00:24:50.129720 ===================================
4955 00:24:50.129786 ANA top config
4956 00:24:50.133193 ===================================
4957 00:24:50.136736 DLL_ASYNC_EN = 0
4958 00:24:50.139713 ALL_SLAVE_EN = 1
4959 00:24:50.143333 NEW_RANK_MODE = 1
4960 00:24:50.143401 DLL_IDLE_MODE = 1
4961 00:24:50.146404 LP45_APHY_COMB_EN = 1
4962 00:24:50.149764 TX_ODT_DIS = 1
4963 00:24:50.153416 NEW_8X_MODE = 1
4964 00:24:50.156754 ===================================
4965 00:24:50.159778 ===================================
4966 00:24:50.163120 data_rate = 1866
4967 00:24:50.166548 CKR = 1
4968 00:24:50.166613 DQ_P2S_RATIO = 8
4969 00:24:50.169643 ===================================
4970 00:24:50.172661 CA_P2S_RATIO = 8
4971 00:24:50.176133 DQ_CA_OPEN = 0
4972 00:24:50.179867 DQ_SEMI_OPEN = 0
4973 00:24:50.183087 CA_SEMI_OPEN = 0
4974 00:24:50.186014 CA_FULL_RATE = 0
4975 00:24:50.186077 DQ_CKDIV4_EN = 1
4976 00:24:50.189750 CA_CKDIV4_EN = 1
4977 00:24:50.192768 CA_PREDIV_EN = 0
4978 00:24:50.196348 PH8_DLY = 0
4979 00:24:50.199831 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4980 00:24:50.202976 DQ_AAMCK_DIV = 4
4981 00:24:50.203039 CA_AAMCK_DIV = 4
4982 00:24:50.206345 CA_ADMCK_DIV = 4
4983 00:24:50.209350 DQ_TRACK_CA_EN = 0
4984 00:24:50.212961 CA_PICK = 933
4985 00:24:50.216392 CA_MCKIO = 933
4986 00:24:50.219257 MCKIO_SEMI = 0
4987 00:24:50.222562 PLL_FREQ = 3732
4988 00:24:50.222627 DQ_UI_PI_RATIO = 32
4989 00:24:50.225905 CA_UI_PI_RATIO = 0
4990 00:24:50.229264 ===================================
4991 00:24:50.232662 ===================================
4992 00:24:50.235817 memory_type:LPDDR4
4993 00:24:50.239368 GP_NUM : 10
4994 00:24:50.239436 SRAM_EN : 1
4995 00:24:50.242701 MD32_EN : 0
4996 00:24:50.246294 ===================================
4997 00:24:50.246359 [ANA_INIT] >>>>>>>>>>>>>>
4998 00:24:50.249287 <<<<<< [CONFIGURE PHASE]: ANA_TX
4999 00:24:50.252852 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5000 00:24:50.255821 ===================================
5001 00:24:50.259234 data_rate = 1866,PCW = 0X8f00
5002 00:24:50.262565 ===================================
5003 00:24:50.266096 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5004 00:24:50.272546 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5005 00:24:50.279025 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5006 00:24:50.282436 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5007 00:24:50.286106 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5008 00:24:50.289353 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5009 00:24:50.292372 [ANA_INIT] flow start
5010 00:24:50.292440 [ANA_INIT] PLL >>>>>>>>
5011 00:24:50.295939 [ANA_INIT] PLL <<<<<<<<
5012 00:24:50.299050 [ANA_INIT] MIDPI >>>>>>>>
5013 00:24:50.299114 [ANA_INIT] MIDPI <<<<<<<<
5014 00:24:50.302391 [ANA_INIT] DLL >>>>>>>>
5015 00:24:50.305830 [ANA_INIT] flow end
5016 00:24:50.308850 ============ LP4 DIFF to SE enter ============
5017 00:24:50.312349 ============ LP4 DIFF to SE exit ============
5018 00:24:50.315848 [ANA_INIT] <<<<<<<<<<<<<
5019 00:24:50.318881 [Flow] Enable top DCM control >>>>>
5020 00:24:50.322166 [Flow] Enable top DCM control <<<<<
5021 00:24:50.325718 Enable DLL master slave shuffle
5022 00:24:50.329017 ==============================================================
5023 00:24:50.332205 Gating Mode config
5024 00:24:50.338773 ==============================================================
5025 00:24:50.338841 Config description:
5026 00:24:50.348878 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5027 00:24:50.355439 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5028 00:24:50.358870 SELPH_MODE 0: By rank 1: By Phase
5029 00:24:50.365879 ==============================================================
5030 00:24:50.369477 GAT_TRACK_EN = 1
5031 00:24:50.372334 RX_GATING_MODE = 2
5032 00:24:50.375898 RX_GATING_TRACK_MODE = 2
5033 00:24:50.378983 SELPH_MODE = 1
5034 00:24:50.382408 PICG_EARLY_EN = 1
5035 00:24:50.385503 VALID_LAT_VALUE = 1
5036 00:24:50.388828 ==============================================================
5037 00:24:50.392327 Enter into Gating configuration >>>>
5038 00:24:50.395889 Exit from Gating configuration <<<<
5039 00:24:50.398856 Enter into DVFS_PRE_config >>>>>
5040 00:24:50.408909 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5041 00:24:50.412301 Exit from DVFS_PRE_config <<<<<
5042 00:24:50.415414 Enter into PICG configuration >>>>
5043 00:24:50.418732 Exit from PICG configuration <<<<
5044 00:24:50.422258 [RX_INPUT] configuration >>>>>
5045 00:24:50.425637 [RX_INPUT] configuration <<<<<
5046 00:24:50.432225 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5047 00:24:50.435297 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5048 00:24:50.442217 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5049 00:24:50.448579 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5050 00:24:50.455279 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5051 00:24:50.462271 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5052 00:24:50.465356 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5053 00:24:50.468847 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5054 00:24:50.472071 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5055 00:24:50.478707 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5056 00:24:50.482152 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5057 00:24:50.485557 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5058 00:24:50.488932 ===================================
5059 00:24:50.492319 LPDDR4 DRAM CONFIGURATION
5060 00:24:50.495522 ===================================
5061 00:24:50.495600 EX_ROW_EN[0] = 0x0
5062 00:24:50.498916 EX_ROW_EN[1] = 0x0
5063 00:24:50.498995 LP4Y_EN = 0x0
5064 00:24:50.501960 WORK_FSP = 0x0
5065 00:24:50.502037 WL = 0x3
5066 00:24:50.505522 RL = 0x3
5067 00:24:50.508566 BL = 0x2
5068 00:24:50.508643 RPST = 0x0
5069 00:24:50.511890 RD_PRE = 0x0
5070 00:24:50.511966 WR_PRE = 0x1
5071 00:24:50.515083 WR_PST = 0x0
5072 00:24:50.515160 DBI_WR = 0x0
5073 00:24:50.518430 DBI_RD = 0x0
5074 00:24:50.518508 OTF = 0x1
5075 00:24:50.521956 ===================================
5076 00:24:50.525474 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5077 00:24:50.531734 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5078 00:24:50.535244 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5079 00:24:50.538803 ===================================
5080 00:24:50.542230 LPDDR4 DRAM CONFIGURATION
5081 00:24:50.545146 ===================================
5082 00:24:50.545212 EX_ROW_EN[0] = 0x10
5083 00:24:50.548582 EX_ROW_EN[1] = 0x0
5084 00:24:50.548672 LP4Y_EN = 0x0
5085 00:24:50.551576 WORK_FSP = 0x0
5086 00:24:50.551640 WL = 0x3
5087 00:24:50.554942 RL = 0x3
5088 00:24:50.555004 BL = 0x2
5089 00:24:50.558337 RPST = 0x0
5090 00:24:50.561794 RD_PRE = 0x0
5091 00:24:50.561897 WR_PRE = 0x1
5092 00:24:50.564896 WR_PST = 0x0
5093 00:24:50.564973 DBI_WR = 0x0
5094 00:24:50.568320 DBI_RD = 0x0
5095 00:24:50.568397 OTF = 0x1
5096 00:24:50.571527 ===================================
5097 00:24:50.578406 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5098 00:24:50.581843 nWR fixed to 30
5099 00:24:50.585264 [ModeRegInit_LP4] CH0 RK0
5100 00:24:50.585341 [ModeRegInit_LP4] CH0 RK1
5101 00:24:50.588879 [ModeRegInit_LP4] CH1 RK0
5102 00:24:50.592282 [ModeRegInit_LP4] CH1 RK1
5103 00:24:50.592359 match AC timing 9
5104 00:24:50.598787 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5105 00:24:50.602299 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5106 00:24:50.605501 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5107 00:24:50.612164 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5108 00:24:50.614969 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5109 00:24:50.615047 ==
5110 00:24:50.618525 Dram Type= 6, Freq= 0, CH_0, rank 0
5111 00:24:50.621913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5112 00:24:50.621991 ==
5113 00:24:50.628510 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5114 00:24:50.635291 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5115 00:24:50.638289 [CA 0] Center 38 (7~69) winsize 63
5116 00:24:50.641846 [CA 1] Center 38 (8~69) winsize 62
5117 00:24:50.645443 [CA 2] Center 35 (5~66) winsize 62
5118 00:24:50.648431 [CA 3] Center 35 (5~65) winsize 61
5119 00:24:50.651960 [CA 4] Center 34 (4~65) winsize 62
5120 00:24:50.655355 [CA 5] Center 33 (3~64) winsize 62
5121 00:24:50.655418
5122 00:24:50.658448 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5123 00:24:50.658511
5124 00:24:50.662004 [CATrainingPosCal] consider 1 rank data
5125 00:24:50.665042 u2DelayCellTimex100 = 270/100 ps
5126 00:24:50.668411 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5127 00:24:50.672017 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5128 00:24:50.675172 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5129 00:24:50.678449 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5130 00:24:50.681870 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5131 00:24:50.684959 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5132 00:24:50.688898
5133 00:24:50.692066 CA PerBit enable=1, Macro0, CA PI delay=33
5134 00:24:50.692132
5135 00:24:50.695188 [CBTSetCACLKResult] CA Dly = 33
5136 00:24:50.695250 CS Dly: 7 (0~38)
5137 00:24:50.695307 ==
5138 00:24:50.698802 Dram Type= 6, Freq= 0, CH_0, rank 1
5139 00:24:50.701861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5140 00:24:50.701927 ==
5141 00:24:50.708533 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5142 00:24:50.715190 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5143 00:24:50.718464 [CA 0] Center 38 (8~69) winsize 62
5144 00:24:50.721923 [CA 1] Center 38 (8~69) winsize 62
5145 00:24:50.724959 [CA 2] Center 36 (6~66) winsize 61
5146 00:24:50.728307 [CA 3] Center 35 (5~66) winsize 62
5147 00:24:50.732100 [CA 4] Center 34 (4~65) winsize 62
5148 00:24:50.734905 [CA 5] Center 34 (4~65) winsize 62
5149 00:24:50.734971
5150 00:24:50.738400 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5151 00:24:50.738464
5152 00:24:50.741884 [CATrainingPosCal] consider 2 rank data
5153 00:24:50.745032 u2DelayCellTimex100 = 270/100 ps
5154 00:24:50.748686 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5155 00:24:50.751695 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5156 00:24:50.755078 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5157 00:24:50.758645 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5158 00:24:50.761760 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5159 00:24:50.768406 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5160 00:24:50.768473
5161 00:24:50.771903 CA PerBit enable=1, Macro0, CA PI delay=34
5162 00:24:50.771966
5163 00:24:50.775136 [CBTSetCACLKResult] CA Dly = 34
5164 00:24:50.775198 CS Dly: 7 (0~39)
5165 00:24:50.775250
5166 00:24:50.778558 ----->DramcWriteLeveling(PI) begin...
5167 00:24:50.778624 ==
5168 00:24:50.781897 Dram Type= 6, Freq= 0, CH_0, rank 0
5169 00:24:50.785215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5170 00:24:50.788445 ==
5171 00:24:50.788505 Write leveling (Byte 0): 33 => 33
5172 00:24:50.791723 Write leveling (Byte 1): 28 => 28
5173 00:24:50.795091 DramcWriteLeveling(PI) end<-----
5174 00:24:50.795155
5175 00:24:50.795209 ==
5176 00:24:50.798271 Dram Type= 6, Freq= 0, CH_0, rank 0
5177 00:24:50.804680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5178 00:24:50.804790 ==
5179 00:24:50.804845 [Gating] SW mode calibration
5180 00:24:50.814762 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5181 00:24:50.818576 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5182 00:24:50.824894 0 14 0 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
5183 00:24:50.828329 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5184 00:24:50.831712 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5185 00:24:50.834868 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5186 00:24:50.841425 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5187 00:24:50.844917 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5188 00:24:50.848320 0 14 24 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 1)
5189 00:24:50.855215 0 14 28 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
5190 00:24:50.858242 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5191 00:24:50.861699 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5192 00:24:50.868148 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5193 00:24:50.871734 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5194 00:24:50.875254 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5195 00:24:50.881797 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5196 00:24:50.885161 0 15 24 | B1->B0 | 2323 2b2a | 0 1 | (0 0) (0 0)
5197 00:24:50.888344 0 15 28 | B1->B0 | 2727 4646 | 1 0 | (0 0) (0 0)
5198 00:24:50.894946 1 0 0 | B1->B0 | 4545 4646 | 1 0 | (0 0) (0 0)
5199 00:24:50.898289 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5200 00:24:50.901498 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5201 00:24:50.908271 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5202 00:24:50.911895 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5203 00:24:50.914811 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5204 00:24:50.921439 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5205 00:24:50.925017 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5206 00:24:50.928108 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5207 00:24:50.931484 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5208 00:24:50.938177 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5209 00:24:50.941264 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5210 00:24:50.944827 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5211 00:24:50.951774 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5212 00:24:50.955107 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5213 00:24:50.957931 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5214 00:24:50.964950 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5215 00:24:50.968291 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5216 00:24:50.971298 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5217 00:24:50.978032 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5218 00:24:50.981602 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5219 00:24:50.984536 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5220 00:24:50.991336 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5221 00:24:50.994804 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5222 00:24:50.998453 Total UI for P1: 0, mck2ui 16
5223 00:24:51.001507 best dqsien dly found for B0: ( 1, 2, 24)
5224 00:24:51.004976 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5225 00:24:51.011483 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5226 00:24:51.011603 Total UI for P1: 0, mck2ui 16
5227 00:24:51.014458 best dqsien dly found for B1: ( 1, 2, 30)
5228 00:24:51.021302 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5229 00:24:51.024810 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5230 00:24:51.024879
5231 00:24:51.028119 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5232 00:24:51.031509 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5233 00:24:51.034434 [Gating] SW calibration Done
5234 00:24:51.034505 ==
5235 00:24:51.037913 Dram Type= 6, Freq= 0, CH_0, rank 0
5236 00:24:51.041502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5237 00:24:51.041581 ==
5238 00:24:51.044587 RX Vref Scan: 0
5239 00:24:51.044664
5240 00:24:51.044762 RX Vref 0 -> 0, step: 1
5241 00:24:51.044819
5242 00:24:51.048207 RX Delay -80 -> 252, step: 8
5243 00:24:51.051187 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5244 00:24:51.058037 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5245 00:24:51.061260 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5246 00:24:51.064335 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5247 00:24:51.067764 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5248 00:24:51.071247 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5249 00:24:51.074764 iDelay=208, Bit 6, Center 119 (32 ~ 207) 176
5250 00:24:51.081327 iDelay=208, Bit 7, Center 119 (32 ~ 207) 176
5251 00:24:51.084431 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5252 00:24:51.087947 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5253 00:24:51.091324 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5254 00:24:51.094321 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5255 00:24:51.097802 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5256 00:24:51.104225 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5257 00:24:51.107910 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5258 00:24:51.110950 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5259 00:24:51.111028 ==
5260 00:24:51.114408 Dram Type= 6, Freq= 0, CH_0, rank 0
5261 00:24:51.117817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5262 00:24:51.117895 ==
5263 00:24:51.121433 DQS Delay:
5264 00:24:51.121510 DQS0 = 0, DQS1 = 0
5265 00:24:51.121571 DQM Delay:
5266 00:24:51.124625 DQM0 = 106, DQM1 = 90
5267 00:24:51.124730 DQ Delay:
5268 00:24:51.127576 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5269 00:24:51.131080 DQ4 =107, DQ5 =95, DQ6 =119, DQ7 =119
5270 00:24:51.134347 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5271 00:24:51.137779 DQ12 =91, DQ13 =91, DQ14 =99, DQ15 =99
5272 00:24:51.137857
5273 00:24:51.137918
5274 00:24:51.140930 ==
5275 00:24:51.144134 Dram Type= 6, Freq= 0, CH_0, rank 0
5276 00:24:51.147915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5277 00:24:51.147991 ==
5278 00:24:51.148055
5279 00:24:51.148109
5280 00:24:51.151002 TX Vref Scan disable
5281 00:24:51.151070 == TX Byte 0 ==
5282 00:24:51.154442 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5283 00:24:51.160817 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5284 00:24:51.160888 == TX Byte 1 ==
5285 00:24:51.164556 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5286 00:24:51.170620 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5287 00:24:51.170706 ==
5288 00:24:51.174099 Dram Type= 6, Freq= 0, CH_0, rank 0
5289 00:24:51.177689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5290 00:24:51.177758 ==
5291 00:24:51.177819
5292 00:24:51.177872
5293 00:24:51.180784 TX Vref Scan disable
5294 00:24:51.184294 == TX Byte 0 ==
5295 00:24:51.187537 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5296 00:24:51.191026 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5297 00:24:51.194160 == TX Byte 1 ==
5298 00:24:51.197552 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5299 00:24:51.201087 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5300 00:24:51.201165
5301 00:24:51.201227 [DATLAT]
5302 00:24:51.204127 Freq=933, CH0 RK0
5303 00:24:51.204204
5304 00:24:51.207479 DATLAT Default: 0xd
5305 00:24:51.207556 0, 0xFFFF, sum = 0
5306 00:24:51.210829 1, 0xFFFF, sum = 0
5307 00:24:51.210902 2, 0xFFFF, sum = 0
5308 00:24:51.214288 3, 0xFFFF, sum = 0
5309 00:24:51.214361 4, 0xFFFF, sum = 0
5310 00:24:51.217547 5, 0xFFFF, sum = 0
5311 00:24:51.217612 6, 0xFFFF, sum = 0
5312 00:24:51.220730 7, 0xFFFF, sum = 0
5313 00:24:51.220797 8, 0xFFFF, sum = 0
5314 00:24:51.224146 9, 0xFFFF, sum = 0
5315 00:24:51.224211 10, 0x0, sum = 1
5316 00:24:51.227303 11, 0x0, sum = 2
5317 00:24:51.227383 12, 0x0, sum = 3
5318 00:24:51.230750 13, 0x0, sum = 4
5319 00:24:51.230819 best_step = 11
5320 00:24:51.230872
5321 00:24:51.230923 ==
5322 00:24:51.234265 Dram Type= 6, Freq= 0, CH_0, rank 0
5323 00:24:51.237411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5324 00:24:51.240864 ==
5325 00:24:51.240934 RX Vref Scan: 1
5326 00:24:51.240993
5327 00:24:51.244279 RX Vref 0 -> 0, step: 1
5328 00:24:51.244344
5329 00:24:51.244402 RX Delay -53 -> 252, step: 4
5330 00:24:51.247698
5331 00:24:51.247796 Set Vref, RX VrefLevel [Byte0]: 59
5332 00:24:51.250924 [Byte1]: 49
5333 00:24:51.255698
5334 00:24:51.255771 Final RX Vref Byte 0 = 59 to rank0
5335 00:24:51.259384 Final RX Vref Byte 1 = 49 to rank0
5336 00:24:51.262520 Final RX Vref Byte 0 = 59 to rank1
5337 00:24:51.265868 Final RX Vref Byte 1 = 49 to rank1==
5338 00:24:51.269079 Dram Type= 6, Freq= 0, CH_0, rank 0
5339 00:24:51.275221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5340 00:24:51.275301 ==
5341 00:24:51.275360 DQS Delay:
5342 00:24:51.275416 DQS0 = 0, DQS1 = 0
5343 00:24:51.278598 DQM Delay:
5344 00:24:51.278690 DQM0 = 108, DQM1 = 92
5345 00:24:51.282404 DQ Delay:
5346 00:24:51.285361 DQ0 =106, DQ1 =106, DQ2 =104, DQ3 =106
5347 00:24:51.289060 DQ4 =108, DQ5 =98, DQ6 =120, DQ7 =116
5348 00:24:51.292256 DQ8 =86, DQ9 =78, DQ10 =92, DQ11 =90
5349 00:24:51.295323 DQ12 =96, DQ13 =94, DQ14 =104, DQ15 =98
5350 00:24:51.295390
5351 00:24:51.295498
5352 00:24:51.301926 [DQSOSCAuto] RK0, (LSB)MR18= 0x231f, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 410 ps
5353 00:24:51.305557 CH0 RK0: MR19=505, MR18=231F
5354 00:24:51.312063 CH0_RK0: MR19=0x505, MR18=0x231F, DQSOSC=410, MR23=63, INC=64, DEC=42
5355 00:24:51.312147
5356 00:24:51.315460 ----->DramcWriteLeveling(PI) begin...
5357 00:24:51.315539 ==
5358 00:24:51.318630 Dram Type= 6, Freq= 0, CH_0, rank 1
5359 00:24:51.322001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5360 00:24:51.322111 ==
5361 00:24:51.325448 Write leveling (Byte 0): 33 => 33
5362 00:24:51.328882 Write leveling (Byte 1): 30 => 30
5363 00:24:51.332133 DramcWriteLeveling(PI) end<-----
5364 00:24:51.332210
5365 00:24:51.332301 ==
5366 00:24:51.335165 Dram Type= 6, Freq= 0, CH_0, rank 1
5367 00:24:51.338678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5368 00:24:51.341989 ==
5369 00:24:51.342113 [Gating] SW mode calibration
5370 00:24:51.351954 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5371 00:24:51.355132 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5372 00:24:51.358477 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5373 00:24:51.365199 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5374 00:24:51.368267 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5375 00:24:51.371879 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5376 00:24:51.378859 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5377 00:24:51.381822 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5378 00:24:51.385314 0 14 24 | B1->B0 | 3434 2f2f | 0 0 | (0 0) (0 1)
5379 00:24:51.391552 0 14 28 | B1->B0 | 2626 2525 | 0 0 | (0 0) (1 0)
5380 00:24:51.395190 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5381 00:24:51.398518 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5382 00:24:51.405241 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5383 00:24:51.408254 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5384 00:24:51.412050 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5385 00:24:51.418488 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5386 00:24:51.422058 0 15 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5387 00:24:51.425120 0 15 28 | B1->B0 | 3939 4040 | 0 1 | (0 0) (0 0)
5388 00:24:51.428586 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5389 00:24:51.435455 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5390 00:24:51.438643 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5391 00:24:51.441786 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5392 00:24:51.448731 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5393 00:24:51.452111 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5394 00:24:51.454971 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5395 00:24:51.461769 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5396 00:24:51.465332 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5397 00:24:51.468280 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5398 00:24:51.475246 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5399 00:24:51.478313 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5400 00:24:51.481725 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5401 00:24:51.488055 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5402 00:24:51.491780 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5403 00:24:51.494904 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5404 00:24:51.501711 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5405 00:24:51.505189 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5406 00:24:51.508167 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5407 00:24:51.515288 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5408 00:24:51.518349 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5409 00:24:51.522125 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5410 00:24:51.528500 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5411 00:24:51.531988 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5412 00:24:51.534896 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5413 00:24:51.538164 Total UI for P1: 0, mck2ui 16
5414 00:24:51.541809 best dqsien dly found for B0: ( 1, 2, 28)
5415 00:24:51.545127 Total UI for P1: 0, mck2ui 16
5416 00:24:51.548219 best dqsien dly found for B1: ( 1, 2, 28)
5417 00:24:51.551854 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5418 00:24:51.554834 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5419 00:24:51.554910
5420 00:24:51.558158 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5421 00:24:51.564929 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5422 00:24:51.565007 [Gating] SW calibration Done
5423 00:24:51.565066 ==
5424 00:24:51.568455 Dram Type= 6, Freq= 0, CH_0, rank 1
5425 00:24:51.574798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5426 00:24:51.574899 ==
5427 00:24:51.574991 RX Vref Scan: 0
5428 00:24:51.575074
5429 00:24:51.578525 RX Vref 0 -> 0, step: 1
5430 00:24:51.578598
5431 00:24:51.581806 RX Delay -80 -> 252, step: 8
5432 00:24:51.584814 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5433 00:24:51.588354 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5434 00:24:51.591404 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5435 00:24:51.594759 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5436 00:24:51.601539 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5437 00:24:51.604640 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5438 00:24:51.607750 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5439 00:24:51.611425 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5440 00:24:51.615087 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5441 00:24:51.618049 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5442 00:24:51.624661 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5443 00:24:51.628220 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5444 00:24:51.631250 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5445 00:24:51.634680 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5446 00:24:51.638218 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5447 00:24:51.641298 iDelay=208, Bit 15, Center 95 (8 ~ 183) 176
5448 00:24:51.644694 ==
5449 00:24:51.647867 Dram Type= 6, Freq= 0, CH_0, rank 1
5450 00:24:51.651475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5451 00:24:51.651548 ==
5452 00:24:51.651613 DQS Delay:
5453 00:24:51.654553 DQS0 = 0, DQS1 = 0
5454 00:24:51.654620 DQM Delay:
5455 00:24:51.658155 DQM0 = 104, DQM1 = 89
5456 00:24:51.658225 DQ Delay:
5457 00:24:51.661561 DQ0 =103, DQ1 =103, DQ2 =99, DQ3 =99
5458 00:24:51.664446 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =111
5459 00:24:51.667974 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =83
5460 00:24:51.671631 DQ12 =91, DQ13 =91, DQ14 =99, DQ15 =95
5461 00:24:51.671700
5462 00:24:51.671757
5463 00:24:51.671810 ==
5464 00:24:51.674995 Dram Type= 6, Freq= 0, CH_0, rank 1
5465 00:24:51.677994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5466 00:24:51.678064 ==
5467 00:24:51.678128
5468 00:24:51.678183
5469 00:24:51.681607 TX Vref Scan disable
5470 00:24:51.684686 == TX Byte 0 ==
5471 00:24:51.687901 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5472 00:24:51.691299 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5473 00:24:51.694708 == TX Byte 1 ==
5474 00:24:51.698058 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5475 00:24:51.701205 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5476 00:24:51.701272 ==
5477 00:24:51.704884 Dram Type= 6, Freq= 0, CH_0, rank 1
5478 00:24:51.710946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5479 00:24:51.711016 ==
5480 00:24:51.711088
5481 00:24:51.711161
5482 00:24:51.711212 TX Vref Scan disable
5483 00:24:51.715543 == TX Byte 0 ==
5484 00:24:51.718227 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5485 00:24:51.722184 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5486 00:24:51.725164 == TX Byte 1 ==
5487 00:24:51.728330 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5488 00:24:51.735042 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5489 00:24:51.735121
5490 00:24:51.735181 [DATLAT]
5491 00:24:51.735237 Freq=933, CH0 RK1
5492 00:24:51.735290
5493 00:24:51.738812 DATLAT Default: 0xb
5494 00:24:51.738936 0, 0xFFFF, sum = 0
5495 00:24:51.741908 1, 0xFFFF, sum = 0
5496 00:24:51.741986 2, 0xFFFF, sum = 0
5497 00:24:51.744970 3, 0xFFFF, sum = 0
5498 00:24:51.748625 4, 0xFFFF, sum = 0
5499 00:24:51.748712 5, 0xFFFF, sum = 0
5500 00:24:51.751604 6, 0xFFFF, sum = 0
5501 00:24:51.751697 7, 0xFFFF, sum = 0
5502 00:24:51.755231 8, 0xFFFF, sum = 0
5503 00:24:51.755325 9, 0xFFFF, sum = 0
5504 00:24:51.758484 10, 0x0, sum = 1
5505 00:24:51.758571 11, 0x0, sum = 2
5506 00:24:51.758631 12, 0x0, sum = 3
5507 00:24:51.761629 13, 0x0, sum = 4
5508 00:24:51.761696 best_step = 11
5509 00:24:51.761758
5510 00:24:51.764909 ==
5511 00:24:51.764977 Dram Type= 6, Freq= 0, CH_0, rank 1
5512 00:24:51.771532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5513 00:24:51.771601 ==
5514 00:24:51.771659 RX Vref Scan: 0
5515 00:24:51.771712
5516 00:24:51.775361 RX Vref 0 -> 0, step: 1
5517 00:24:51.775433
5518 00:24:51.778303 RX Delay -53 -> 252, step: 4
5519 00:24:51.782077 iDelay=199, Bit 0, Center 104 (19 ~ 190) 172
5520 00:24:51.788239 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5521 00:24:51.792141 iDelay=199, Bit 2, Center 102 (19 ~ 186) 168
5522 00:24:51.794906 iDelay=199, Bit 3, Center 100 (19 ~ 182) 164
5523 00:24:51.798632 iDelay=199, Bit 4, Center 104 (19 ~ 190) 172
5524 00:24:51.801863 iDelay=199, Bit 5, Center 98 (15 ~ 182) 168
5525 00:24:51.804932 iDelay=199, Bit 6, Center 112 (27 ~ 198) 172
5526 00:24:51.811750 iDelay=199, Bit 7, Center 110 (23 ~ 198) 176
5527 00:24:51.815150 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5528 00:24:51.818505 iDelay=199, Bit 9, Center 80 (-1 ~ 162) 164
5529 00:24:51.821640 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5530 00:24:51.825434 iDelay=199, Bit 11, Center 92 (11 ~ 174) 164
5531 00:24:51.831738 iDelay=199, Bit 12, Center 96 (11 ~ 182) 172
5532 00:24:51.835226 iDelay=199, Bit 13, Center 94 (11 ~ 178) 168
5533 00:24:51.838237 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5534 00:24:51.841683 iDelay=199, Bit 15, Center 100 (19 ~ 182) 164
5535 00:24:51.841762 ==
5536 00:24:51.844986 Dram Type= 6, Freq= 0, CH_0, rank 1
5537 00:24:51.851403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5538 00:24:51.851479 ==
5539 00:24:51.851539 DQS Delay:
5540 00:24:51.851594 DQS0 = 0, DQS1 = 0
5541 00:24:51.855138 DQM Delay:
5542 00:24:51.855210 DQM0 = 104, DQM1 = 92
5543 00:24:51.858130 DQ Delay:
5544 00:24:51.861589 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =100
5545 00:24:51.864828 DQ4 =104, DQ5 =98, DQ6 =112, DQ7 =110
5546 00:24:51.868179 DQ8 =84, DQ9 =80, DQ10 =94, DQ11 =92
5547 00:24:51.871456 DQ12 =96, DQ13 =94, DQ14 =100, DQ15 =100
5548 00:24:51.871552
5549 00:24:51.871627
5550 00:24:51.878253 [DQSOSCAuto] RK1, (LSB)MR18= 0x2c0d, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 408 ps
5551 00:24:51.881830 CH0 RK1: MR19=505, MR18=2C0D
5552 00:24:51.888172 CH0_RK1: MR19=0x505, MR18=0x2C0D, DQSOSC=408, MR23=63, INC=65, DEC=43
5553 00:24:51.891306 [RxdqsGatingPostProcess] freq 933
5554 00:24:51.898082 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5555 00:24:51.898157 best DQS0 dly(2T, 0.5T) = (0, 10)
5556 00:24:51.901306 best DQS1 dly(2T, 0.5T) = (0, 10)
5557 00:24:51.905211 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5558 00:24:51.908063 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5559 00:24:51.911804 best DQS0 dly(2T, 0.5T) = (0, 10)
5560 00:24:51.915069 best DQS1 dly(2T, 0.5T) = (0, 10)
5561 00:24:51.918096 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5562 00:24:51.921803 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5563 00:24:51.924854 Pre-setting of DQS Precalculation
5564 00:24:51.928512 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5565 00:24:51.931664 ==
5566 00:24:51.934656 Dram Type= 6, Freq= 0, CH_1, rank 0
5567 00:24:51.938360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5568 00:24:51.938440 ==
5569 00:24:51.941588 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5570 00:24:51.948362 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5571 00:24:51.952013 [CA 0] Center 37 (7~68) winsize 62
5572 00:24:51.954919 [CA 1] Center 37 (7~68) winsize 62
5573 00:24:51.958237 [CA 2] Center 36 (6~66) winsize 61
5574 00:24:51.961756 [CA 3] Center 35 (5~65) winsize 61
5575 00:24:51.965397 [CA 4] Center 35 (5~65) winsize 61
5576 00:24:51.968391 [CA 5] Center 34 (4~65) winsize 62
5577 00:24:51.968474
5578 00:24:51.972172 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5579 00:24:51.972243
5580 00:24:51.975119 [CATrainingPosCal] consider 1 rank data
5581 00:24:51.978578 u2DelayCellTimex100 = 270/100 ps
5582 00:24:51.982138 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5583 00:24:51.985288 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5584 00:24:51.992006 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5585 00:24:51.995862 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5586 00:24:51.998900 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5587 00:24:52.002082 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
5588 00:24:52.002162
5589 00:24:52.005371 CA PerBit enable=1, Macro0, CA PI delay=34
5590 00:24:52.005451
5591 00:24:52.008478 [CBTSetCACLKResult] CA Dly = 34
5592 00:24:52.008558 CS Dly: 6 (0~37)
5593 00:24:52.008619 ==
5594 00:24:52.011962 Dram Type= 6, Freq= 0, CH_1, rank 1
5595 00:24:52.018908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5596 00:24:52.018988 ==
5597 00:24:52.021797 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5598 00:24:52.028549 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5599 00:24:52.032078 [CA 0] Center 38 (8~68) winsize 61
5600 00:24:52.035724 [CA 1] Center 38 (7~69) winsize 63
5601 00:24:52.038688 [CA 2] Center 36 (6~66) winsize 61
5602 00:24:52.041797 [CA 3] Center 35 (5~65) winsize 61
5603 00:24:52.045511 [CA 4] Center 35 (5~65) winsize 61
5604 00:24:52.048897 [CA 5] Center 35 (5~65) winsize 61
5605 00:24:52.048968
5606 00:24:52.052232 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5607 00:24:52.052302
5608 00:24:52.055113 [CATrainingPosCal] consider 2 rank data
5609 00:24:52.058567 u2DelayCellTimex100 = 270/100 ps
5610 00:24:52.062001 CA0 delay=38 (8~68),Diff = 3 PI (18 cell)
5611 00:24:52.065561 CA1 delay=37 (7~68),Diff = 2 PI (12 cell)
5612 00:24:52.072016 CA2 delay=36 (6~66),Diff = 1 PI (6 cell)
5613 00:24:52.075139 CA3 delay=35 (5~65),Diff = 0 PI (0 cell)
5614 00:24:52.078328 CA4 delay=35 (5~65),Diff = 0 PI (0 cell)
5615 00:24:52.081959 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
5616 00:24:52.082038
5617 00:24:52.085272 CA PerBit enable=1, Macro0, CA PI delay=35
5618 00:24:52.085350
5619 00:24:52.088498 [CBTSetCACLKResult] CA Dly = 35
5620 00:24:52.088577 CS Dly: 7 (0~39)
5621 00:24:52.088639
5622 00:24:52.091857 ----->DramcWriteLeveling(PI) begin...
5623 00:24:52.095256 ==
5624 00:24:52.095336 Dram Type= 6, Freq= 0, CH_1, rank 0
5625 00:24:52.101954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5626 00:24:52.102033 ==
5627 00:24:52.105498 Write leveling (Byte 0): 29 => 29
5628 00:24:52.108447 Write leveling (Byte 1): 29 => 29
5629 00:24:52.111885 DramcWriteLeveling(PI) end<-----
5630 00:24:52.111963
5631 00:24:52.112022 ==
5632 00:24:52.115555 Dram Type= 6, Freq= 0, CH_1, rank 0
5633 00:24:52.118579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5634 00:24:52.118657 ==
5635 00:24:52.121641 [Gating] SW mode calibration
5636 00:24:52.128369 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5637 00:24:52.131951 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5638 00:24:52.138735 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5639 00:24:52.141659 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5640 00:24:52.145295 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5641 00:24:52.151520 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5642 00:24:52.154728 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5643 00:24:52.158187 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5644 00:24:52.164874 0 14 24 | B1->B0 | 3131 3030 | 0 0 | (0 1) (0 1)
5645 00:24:52.168215 0 14 28 | B1->B0 | 2424 2727 | 0 0 | (0 0) (0 0)
5646 00:24:52.171864 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5647 00:24:52.178587 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5648 00:24:52.181469 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5649 00:24:52.185055 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5650 00:24:52.191632 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5651 00:24:52.194960 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5652 00:24:52.198051 0 15 24 | B1->B0 | 2a2a 2828 | 0 0 | (0 0) (0 0)
5653 00:24:52.205001 0 15 28 | B1->B0 | 3c3c 4343 | 0 0 | (0 0) (0 0)
5654 00:24:52.208205 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5655 00:24:52.211495 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5656 00:24:52.218316 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5657 00:24:52.221242 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5658 00:24:52.224956 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5659 00:24:52.231609 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5660 00:24:52.235078 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5661 00:24:52.238253 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5662 00:24:52.241764 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5663 00:24:52.248308 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5664 00:24:52.251318 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5665 00:24:52.254746 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5666 00:24:52.261217 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5667 00:24:52.264735 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5668 00:24:52.268221 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5669 00:24:52.274813 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5670 00:24:52.278289 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5671 00:24:52.281470 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5672 00:24:52.287990 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5673 00:24:52.291478 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5674 00:24:52.294793 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5675 00:24:52.301101 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5676 00:24:52.304650 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5677 00:24:52.307971 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5678 00:24:52.310963 Total UI for P1: 0, mck2ui 16
5679 00:24:52.314805 best dqsien dly found for B0: ( 1, 2, 22)
5680 00:24:52.317968 Total UI for P1: 0, mck2ui 16
5681 00:24:52.321229 best dqsien dly found for B1: ( 1, 2, 24)
5682 00:24:52.324587 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5683 00:24:52.327635 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5684 00:24:52.327704
5685 00:24:52.334461 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5686 00:24:52.338059 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5687 00:24:52.338135 [Gating] SW calibration Done
5688 00:24:52.341144 ==
5689 00:24:52.344686 Dram Type= 6, Freq= 0, CH_1, rank 0
5690 00:24:52.347763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5691 00:24:52.347830 ==
5692 00:24:52.347887 RX Vref Scan: 0
5693 00:24:52.347940
5694 00:24:52.351325 RX Vref 0 -> 0, step: 1
5695 00:24:52.351387
5696 00:24:52.354394 RX Delay -80 -> 252, step: 8
5697 00:24:52.357941 iDelay=208, Bit 0, Center 111 (24 ~ 199) 176
5698 00:24:52.361227 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5699 00:24:52.364195 iDelay=208, Bit 2, Center 95 (8 ~ 183) 176
5700 00:24:52.371044 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5701 00:24:52.374311 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5702 00:24:52.378060 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5703 00:24:52.381250 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5704 00:24:52.384482 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5705 00:24:52.387947 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5706 00:24:52.391164 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5707 00:24:52.398074 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5708 00:24:52.401374 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5709 00:24:52.404712 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5710 00:24:52.408049 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5711 00:24:52.410979 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5712 00:24:52.417635 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5713 00:24:52.417734 ==
5714 00:24:52.421308 Dram Type= 6, Freq= 0, CH_1, rank 0
5715 00:24:52.424479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5716 00:24:52.424575 ==
5717 00:24:52.424666 DQS Delay:
5718 00:24:52.427877 DQS0 = 0, DQS1 = 0
5719 00:24:52.427977 DQM Delay:
5720 00:24:52.430929 DQM0 = 103, DQM1 = 95
5721 00:24:52.431027 DQ Delay:
5722 00:24:52.434706 DQ0 =111, DQ1 =95, DQ2 =95, DQ3 =99
5723 00:24:52.438018 DQ4 =99, DQ5 =111, DQ6 =115, DQ7 =99
5724 00:24:52.441083 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =87
5725 00:24:52.444336 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =99
5726 00:24:52.444437
5727 00:24:52.444526
5728 00:24:52.444614 ==
5729 00:24:52.447548 Dram Type= 6, Freq= 0, CH_1, rank 0
5730 00:24:52.451387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5731 00:24:52.454564 ==
5732 00:24:52.454644
5733 00:24:52.454704
5734 00:24:52.454759 TX Vref Scan disable
5735 00:24:52.457833 == TX Byte 0 ==
5736 00:24:52.461185 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5737 00:24:52.464149 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5738 00:24:52.467755 == TX Byte 1 ==
5739 00:24:52.471112 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5740 00:24:52.474586 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5741 00:24:52.477609 ==
5742 00:24:52.480738 Dram Type= 6, Freq= 0, CH_1, rank 0
5743 00:24:52.484501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5744 00:24:52.484580 ==
5745 00:24:52.484641
5746 00:24:52.484697
5747 00:24:52.487457 TX Vref Scan disable
5748 00:24:52.487535 == TX Byte 0 ==
5749 00:24:52.494342 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5750 00:24:52.497263 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5751 00:24:52.497342 == TX Byte 1 ==
5752 00:24:52.503819 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5753 00:24:52.507261 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5754 00:24:52.507339
5755 00:24:52.507415 [DATLAT]
5756 00:24:52.510800 Freq=933, CH1 RK0
5757 00:24:52.510874
5758 00:24:52.510933 DATLAT Default: 0xd
5759 00:24:52.514082 0, 0xFFFF, sum = 0
5760 00:24:52.514153 1, 0xFFFF, sum = 0
5761 00:24:52.517160 2, 0xFFFF, sum = 0
5762 00:24:52.517225 3, 0xFFFF, sum = 0
5763 00:24:52.520716 4, 0xFFFF, sum = 0
5764 00:24:52.520795 5, 0xFFFF, sum = 0
5765 00:24:52.523680 6, 0xFFFF, sum = 0
5766 00:24:52.523786 7, 0xFFFF, sum = 0
5767 00:24:52.527255 8, 0xFFFF, sum = 0
5768 00:24:52.530328 9, 0xFFFF, sum = 0
5769 00:24:52.530430 10, 0x0, sum = 1
5770 00:24:52.530519 11, 0x0, sum = 2
5771 00:24:52.533823 12, 0x0, sum = 3
5772 00:24:52.533921 13, 0x0, sum = 4
5773 00:24:52.536899 best_step = 11
5774 00:24:52.537002
5775 00:24:52.537091 ==
5776 00:24:52.540511 Dram Type= 6, Freq= 0, CH_1, rank 0
5777 00:24:52.543779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5778 00:24:52.543878 ==
5779 00:24:52.546813 RX Vref Scan: 1
5780 00:24:52.546913
5781 00:24:52.546999 RX Vref 0 -> 0, step: 1
5782 00:24:52.550453
5783 00:24:52.550549 RX Delay -53 -> 252, step: 4
5784 00:24:52.550636
5785 00:24:52.553881 Set Vref, RX VrefLevel [Byte0]: 52
5786 00:24:52.556979 [Byte1]: 50
5787 00:24:52.561141
5788 00:24:52.561238 Final RX Vref Byte 0 = 52 to rank0
5789 00:24:52.564528 Final RX Vref Byte 1 = 50 to rank0
5790 00:24:52.567682 Final RX Vref Byte 0 = 52 to rank1
5791 00:24:52.571287 Final RX Vref Byte 1 = 50 to rank1==
5792 00:24:52.574872 Dram Type= 6, Freq= 0, CH_1, rank 0
5793 00:24:52.581415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5794 00:24:52.581527 ==
5795 00:24:52.581616 DQS Delay:
5796 00:24:52.581709 DQS0 = 0, DQS1 = 0
5797 00:24:52.584516 DQM Delay:
5798 00:24:52.584597 DQM0 = 104, DQM1 = 97
5799 00:24:52.588007 DQ Delay:
5800 00:24:52.591299 DQ0 =108, DQ1 =98, DQ2 =96, DQ3 =102
5801 00:24:52.594446 DQ4 =104, DQ5 =112, DQ6 =114, DQ7 =100
5802 00:24:52.597469 DQ8 =86, DQ9 =86, DQ10 =102, DQ11 =92
5803 00:24:52.600931 DQ12 =108, DQ13 =102, DQ14 =104, DQ15 =102
5804 00:24:52.601028
5805 00:24:52.601121
5806 00:24:52.607753 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e36, (MSB)MR19= 0x505, tDQSOscB0 = 404 ps tDQSOscB1 = 412 ps
5807 00:24:52.611294 CH1 RK0: MR19=505, MR18=1E36
5808 00:24:52.617529 CH1_RK0: MR19=0x505, MR18=0x1E36, DQSOSC=404, MR23=63, INC=66, DEC=44
5809 00:24:52.617702
5810 00:24:52.620910 ----->DramcWriteLeveling(PI) begin...
5811 00:24:52.621004 ==
5812 00:24:52.624298 Dram Type= 6, Freq= 0, CH_1, rank 1
5813 00:24:52.627498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5814 00:24:52.627606 ==
5815 00:24:52.631009 Write leveling (Byte 0): 28 => 28
5816 00:24:52.634420 Write leveling (Byte 1): 27 => 27
5817 00:24:52.637810 DramcWriteLeveling(PI) end<-----
5818 00:24:52.637884
5819 00:24:52.637945 ==
5820 00:24:52.640881 Dram Type= 6, Freq= 0, CH_1, rank 1
5821 00:24:52.647698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5822 00:24:52.647799 ==
5823 00:24:52.647889 [Gating] SW mode calibration
5824 00:24:52.657806 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5825 00:24:52.660758 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5826 00:24:52.664489 0 14 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5827 00:24:52.671014 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5828 00:24:52.674179 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5829 00:24:52.677328 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5830 00:24:52.684106 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5831 00:24:52.687443 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
5832 00:24:52.690513 0 14 24 | B1->B0 | 3232 3333 | 1 1 | (1 0) (1 1)
5833 00:24:52.697375 0 14 28 | B1->B0 | 2828 3030 | 0 0 | (0 0) (0 1)
5834 00:24:52.700727 0 15 0 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5835 00:24:52.703990 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5836 00:24:52.710661 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5837 00:24:52.713856 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5838 00:24:52.717521 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5839 00:24:52.723784 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5840 00:24:52.727283 0 15 24 | B1->B0 | 2e2e 2424 | 0 0 | (0 0) (0 0)
5841 00:24:52.730729 0 15 28 | B1->B0 | 3e3e 3838 | 0 0 | (0 0) (0 0)
5842 00:24:52.737338 1 0 0 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
5843 00:24:52.740758 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5844 00:24:52.743878 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5845 00:24:52.750735 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5846 00:24:52.753953 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5847 00:24:52.757544 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5848 00:24:52.763901 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5849 00:24:52.767358 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5850 00:24:52.770434 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5851 00:24:52.777405 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5852 00:24:52.780576 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5853 00:24:52.783644 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5854 00:24:52.787337 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5855 00:24:52.793744 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5856 00:24:52.797292 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5857 00:24:52.800460 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5858 00:24:52.806975 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5859 00:24:52.810283 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5860 00:24:52.813972 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5861 00:24:52.820375 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5862 00:24:52.823486 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5863 00:24:52.826961 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5864 00:24:52.833796 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5865 00:24:52.836829 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5866 00:24:52.840475 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5867 00:24:52.843906 Total UI for P1: 0, mck2ui 16
5868 00:24:52.847243 best dqsien dly found for B0: ( 1, 2, 26)
5869 00:24:52.850594 Total UI for P1: 0, mck2ui 16
5870 00:24:52.853815 best dqsien dly found for B1: ( 1, 2, 26)
5871 00:24:52.856904 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5872 00:24:52.860521 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5873 00:24:52.860610
5874 00:24:52.866522 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5875 00:24:52.870253 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5876 00:24:52.870322 [Gating] SW calibration Done
5877 00:24:52.873320 ==
5878 00:24:52.876511 Dram Type= 6, Freq= 0, CH_1, rank 1
5879 00:24:52.880196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5880 00:24:52.880287 ==
5881 00:24:52.880371 RX Vref Scan: 0
5882 00:24:52.880453
5883 00:24:52.883709 RX Vref 0 -> 0, step: 1
5884 00:24:52.883796
5885 00:24:52.886645 RX Delay -80 -> 252, step: 8
5886 00:24:52.889919 iDelay=200, Bit 0, Center 107 (24 ~ 191) 168
5887 00:24:52.893309 iDelay=200, Bit 1, Center 99 (16 ~ 183) 168
5888 00:24:52.896533 iDelay=200, Bit 2, Center 87 (0 ~ 175) 176
5889 00:24:52.903533 iDelay=200, Bit 3, Center 103 (16 ~ 191) 176
5890 00:24:52.906779 iDelay=200, Bit 4, Center 103 (16 ~ 191) 176
5891 00:24:52.909842 iDelay=200, Bit 5, Center 111 (24 ~ 199) 176
5892 00:24:52.913546 iDelay=200, Bit 6, Center 111 (24 ~ 199) 176
5893 00:24:52.916469 iDelay=200, Bit 7, Center 103 (16 ~ 191) 176
5894 00:24:52.923589 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5895 00:24:52.926814 iDelay=200, Bit 9, Center 83 (-8 ~ 175) 184
5896 00:24:52.930293 iDelay=200, Bit 10, Center 95 (8 ~ 183) 176
5897 00:24:52.933288 iDelay=200, Bit 11, Center 87 (-8 ~ 183) 192
5898 00:24:52.936976 iDelay=200, Bit 12, Center 107 (16 ~ 199) 184
5899 00:24:52.939923 iDelay=200, Bit 13, Center 103 (16 ~ 191) 176
5900 00:24:52.946701 iDelay=200, Bit 14, Center 103 (8 ~ 199) 192
5901 00:24:52.949880 iDelay=200, Bit 15, Center 103 (8 ~ 199) 192
5902 00:24:52.949972 ==
5903 00:24:52.953314 Dram Type= 6, Freq= 0, CH_1, rank 1
5904 00:24:52.956919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5905 00:24:52.956990 ==
5906 00:24:52.960239 DQS Delay:
5907 00:24:52.960331 DQS0 = 0, DQS1 = 0
5908 00:24:52.960413 DQM Delay:
5909 00:24:52.963357 DQM0 = 103, DQM1 = 95
5910 00:24:52.963446 DQ Delay:
5911 00:24:52.966709 DQ0 =107, DQ1 =99, DQ2 =87, DQ3 =103
5912 00:24:52.969811 DQ4 =103, DQ5 =111, DQ6 =111, DQ7 =103
5913 00:24:52.973469 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5914 00:24:52.976508 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =103
5915 00:24:52.980209
5916 00:24:52.980310
5917 00:24:52.980394 ==
5918 00:24:52.983435 Dram Type= 6, Freq= 0, CH_1, rank 1
5919 00:24:52.986497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5920 00:24:52.986572 ==
5921 00:24:52.986634
5922 00:24:52.986763
5923 00:24:52.989783 TX Vref Scan disable
5924 00:24:52.989845 == TX Byte 0 ==
5925 00:24:52.996555 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5926 00:24:52.999954 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5927 00:24:53.000051 == TX Byte 1 ==
5928 00:24:53.006425 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5929 00:24:53.010103 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5930 00:24:53.010192 ==
5931 00:24:53.013068 Dram Type= 6, Freq= 0, CH_1, rank 1
5932 00:24:53.016532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5933 00:24:53.016626 ==
5934 00:24:53.016739
5935 00:24:53.016833
5936 00:24:53.020075 TX Vref Scan disable
5937 00:24:53.023008 == TX Byte 0 ==
5938 00:24:53.026639 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5939 00:24:53.029673 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5940 00:24:53.033073 == TX Byte 1 ==
5941 00:24:53.036549 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5942 00:24:53.039628 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5943 00:24:53.039719
5944 00:24:53.043021 [DATLAT]
5945 00:24:53.043108 Freq=933, CH1 RK1
5946 00:24:53.043199
5947 00:24:53.046719 DATLAT Default: 0xb
5948 00:24:53.046811 0, 0xFFFF, sum = 0
5949 00:24:53.049794 1, 0xFFFF, sum = 0
5950 00:24:53.049870 2, 0xFFFF, sum = 0
5951 00:24:53.053023 3, 0xFFFF, sum = 0
5952 00:24:53.053092 4, 0xFFFF, sum = 0
5953 00:24:53.056403 5, 0xFFFF, sum = 0
5954 00:24:53.056495 6, 0xFFFF, sum = 0
5955 00:24:53.059911 7, 0xFFFF, sum = 0
5956 00:24:53.060004 8, 0xFFFF, sum = 0
5957 00:24:53.063084 9, 0xFFFF, sum = 0
5958 00:24:53.063163 10, 0x0, sum = 1
5959 00:24:53.066544 11, 0x0, sum = 2
5960 00:24:53.066619 12, 0x0, sum = 3
5961 00:24:53.069979 13, 0x0, sum = 4
5962 00:24:53.070045 best_step = 11
5963 00:24:53.070099
5964 00:24:53.070172 ==
5965 00:24:53.072900 Dram Type= 6, Freq= 0, CH_1, rank 1
5966 00:24:53.076295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5967 00:24:53.079779 ==
5968 00:24:53.079868 RX Vref Scan: 0
5969 00:24:53.079949
5970 00:24:53.083222 RX Vref 0 -> 0, step: 1
5971 00:24:53.083310
5972 00:24:53.086472 RX Delay -53 -> 252, step: 4
5973 00:24:53.089615 iDelay=199, Bit 0, Center 108 (31 ~ 186) 156
5974 00:24:53.093033 iDelay=199, Bit 1, Center 98 (19 ~ 178) 160
5975 00:24:53.096598 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5976 00:24:53.103192 iDelay=199, Bit 3, Center 102 (19 ~ 186) 168
5977 00:24:53.106261 iDelay=199, Bit 4, Center 106 (27 ~ 186) 160
5978 00:24:53.109837 iDelay=199, Bit 5, Center 114 (31 ~ 198) 168
5979 00:24:53.112865 iDelay=199, Bit 6, Center 112 (31 ~ 194) 164
5980 00:24:53.116329 iDelay=199, Bit 7, Center 102 (23 ~ 182) 160
5981 00:24:53.122762 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5982 00:24:53.126293 iDelay=199, Bit 9, Center 88 (7 ~ 170) 164
5983 00:24:53.129463 iDelay=199, Bit 10, Center 98 (15 ~ 182) 168
5984 00:24:53.132866 iDelay=199, Bit 11, Center 92 (7 ~ 178) 172
5985 00:24:53.135953 iDelay=199, Bit 12, Center 104 (19 ~ 190) 172
5986 00:24:53.142801 iDelay=199, Bit 13, Center 104 (19 ~ 190) 172
5987 00:24:53.146246 iDelay=199, Bit 14, Center 104 (19 ~ 190) 172
5988 00:24:53.149598 iDelay=199, Bit 15, Center 106 (19 ~ 194) 176
5989 00:24:53.149665 ==
5990 00:24:53.152802 Dram Type= 6, Freq= 0, CH_1, rank 1
5991 00:24:53.156312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5992 00:24:53.156405 ==
5993 00:24:53.159437 DQS Delay:
5994 00:24:53.159524 DQS0 = 0, DQS1 = 0
5995 00:24:53.162681 DQM Delay:
5996 00:24:53.162768 DQM0 = 104, DQM1 = 97
5997 00:24:53.162849 DQ Delay:
5998 00:24:53.166186 DQ0 =108, DQ1 =98, DQ2 =94, DQ3 =102
5999 00:24:53.169551 DQ4 =106, DQ5 =114, DQ6 =112, DQ7 =102
6000 00:24:53.173109 DQ8 =84, DQ9 =88, DQ10 =98, DQ11 =92
6001 00:24:53.179281 DQ12 =104, DQ13 =104, DQ14 =104, DQ15 =106
6002 00:24:53.179372
6003 00:24:53.179456
6004 00:24:53.186234 [DQSOSCAuto] RK1, (LSB)MR18= 0x21fe, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 411 ps
6005 00:24:53.189239 CH1 RK1: MR19=504, MR18=21FE
6006 00:24:53.195959 CH1_RK1: MR19=0x504, MR18=0x21FE, DQSOSC=411, MR23=63, INC=64, DEC=42
6007 00:24:53.199489 [RxdqsGatingPostProcess] freq 933
6008 00:24:53.203037 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6009 00:24:53.205984 best DQS0 dly(2T, 0.5T) = (0, 10)
6010 00:24:53.209348 best DQS1 dly(2T, 0.5T) = (0, 10)
6011 00:24:53.212913 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6012 00:24:53.216034 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6013 00:24:53.219263 best DQS0 dly(2T, 0.5T) = (0, 10)
6014 00:24:53.222898 best DQS1 dly(2T, 0.5T) = (0, 10)
6015 00:24:53.226281 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6016 00:24:53.229335 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6017 00:24:53.232530 Pre-setting of DQS Precalculation
6018 00:24:53.235928 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6019 00:24:53.242685 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6020 00:24:53.252451 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6021 00:24:53.252545
6022 00:24:53.252629
6023 00:24:53.255796 [Calibration Summary] 1866 Mbps
6024 00:24:53.255884 CH 0, Rank 0
6025 00:24:53.259402 SW Impedance : PASS
6026 00:24:53.259466 DUTY Scan : NO K
6027 00:24:53.262515 ZQ Calibration : PASS
6028 00:24:53.265779 Jitter Meter : NO K
6029 00:24:53.265866 CBT Training : PASS
6030 00:24:53.269139 Write leveling : PASS
6031 00:24:53.269203 RX DQS gating : PASS
6032 00:24:53.272373 RX DQ/DQS(RDDQC) : PASS
6033 00:24:53.275917 TX DQ/DQS : PASS
6034 00:24:53.275980 RX DATLAT : PASS
6035 00:24:53.279094 RX DQ/DQS(Engine): PASS
6036 00:24:53.282491 TX OE : NO K
6037 00:24:53.282560 All Pass.
6038 00:24:53.282614
6039 00:24:53.282665 CH 0, Rank 1
6040 00:24:53.285814 SW Impedance : PASS
6041 00:24:53.288940 DUTY Scan : NO K
6042 00:24:53.289004 ZQ Calibration : PASS
6043 00:24:53.292426 Jitter Meter : NO K
6044 00:24:53.296086 CBT Training : PASS
6045 00:24:53.296174 Write leveling : PASS
6046 00:24:53.299133 RX DQS gating : PASS
6047 00:24:53.302710 RX DQ/DQS(RDDQC) : PASS
6048 00:24:53.302774 TX DQ/DQS : PASS
6049 00:24:53.305957 RX DATLAT : PASS
6050 00:24:53.308908 RX DQ/DQS(Engine): PASS
6051 00:24:53.308989 TX OE : NO K
6052 00:24:53.309082 All Pass.
6053 00:24:53.312802
6054 00:24:53.312871 CH 1, Rank 0
6055 00:24:53.315584 SW Impedance : PASS
6056 00:24:53.315674 DUTY Scan : NO K
6057 00:24:53.319247 ZQ Calibration : PASS
6058 00:24:53.319336 Jitter Meter : NO K
6059 00:24:53.322279 CBT Training : PASS
6060 00:24:53.325870 Write leveling : PASS
6061 00:24:53.325959 RX DQS gating : PASS
6062 00:24:53.329453 RX DQ/DQS(RDDQC) : PASS
6063 00:24:53.332446 TX DQ/DQS : PASS
6064 00:24:53.332539 RX DATLAT : PASS
6065 00:24:53.335940 RX DQ/DQS(Engine): PASS
6066 00:24:53.339081 TX OE : NO K
6067 00:24:53.339203 All Pass.
6068 00:24:53.339301
6069 00:24:53.339380 CH 1, Rank 1
6070 00:24:53.342142 SW Impedance : PASS
6071 00:24:53.345589 DUTY Scan : NO K
6072 00:24:53.345699 ZQ Calibration : PASS
6073 00:24:53.348904 Jitter Meter : NO K
6074 00:24:53.352181 CBT Training : PASS
6075 00:24:53.352274 Write leveling : PASS
6076 00:24:53.355854 RX DQS gating : PASS
6077 00:24:53.359154 RX DQ/DQS(RDDQC) : PASS
6078 00:24:53.359244 TX DQ/DQS : PASS
6079 00:24:53.362846 RX DATLAT : PASS
6080 00:24:53.362938 RX DQ/DQS(Engine): PASS
6081 00:24:53.365867 TX OE : NO K
6082 00:24:53.365935 All Pass.
6083 00:24:53.365988
6084 00:24:53.368841 DramC Write-DBI off
6085 00:24:53.372271 PER_BANK_REFRESH: Hybrid Mode
6086 00:24:53.372358 TX_TRACKING: ON
6087 00:24:53.382348 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6088 00:24:53.385945 [FAST_K] Save calibration result to emmc
6089 00:24:53.389001 dramc_set_vcore_voltage set vcore to 650000
6090 00:24:53.392583 Read voltage for 400, 6
6091 00:24:53.392676 Vio18 = 0
6092 00:24:53.392750 Vcore = 650000
6093 00:24:53.395921 Vdram = 0
6094 00:24:53.395987 Vddq = 0
6095 00:24:53.396045 Vmddr = 0
6096 00:24:53.402460 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6097 00:24:53.405972 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6098 00:24:53.409142 MEM_TYPE=3, freq_sel=20
6099 00:24:53.412519 sv_algorithm_assistance_LP4_800
6100 00:24:53.415777 ============ PULL DRAM RESETB DOWN ============
6101 00:24:53.419248 ========== PULL DRAM RESETB DOWN end =========
6102 00:24:53.426121 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6103 00:24:53.429181 ===================================
6104 00:24:53.432389 LPDDR4 DRAM CONFIGURATION
6105 00:24:53.435946 ===================================
6106 00:24:53.436036 EX_ROW_EN[0] = 0x0
6107 00:24:53.439467 EX_ROW_EN[1] = 0x0
6108 00:24:53.439554 LP4Y_EN = 0x0
6109 00:24:53.442852 WORK_FSP = 0x0
6110 00:24:53.442958 WL = 0x2
6111 00:24:53.445988 RL = 0x2
6112 00:24:53.446096 BL = 0x2
6113 00:24:53.449219 RPST = 0x0
6114 00:24:53.449313 RD_PRE = 0x0
6115 00:24:53.452937 WR_PRE = 0x1
6116 00:24:53.453006 WR_PST = 0x0
6117 00:24:53.455746 DBI_WR = 0x0
6118 00:24:53.455839 DBI_RD = 0x0
6119 00:24:53.459078 OTF = 0x1
6120 00:24:53.462864 ===================================
6121 00:24:53.465703 ===================================
6122 00:24:53.465769 ANA top config
6123 00:24:53.469170 ===================================
6124 00:24:53.472829 DLL_ASYNC_EN = 0
6125 00:24:53.475879 ALL_SLAVE_EN = 1
6126 00:24:53.479265 NEW_RANK_MODE = 1
6127 00:24:53.479359 DLL_IDLE_MODE = 1
6128 00:24:53.482592 LP45_APHY_COMB_EN = 1
6129 00:24:53.485845 TX_ODT_DIS = 1
6130 00:24:53.488935 NEW_8X_MODE = 1
6131 00:24:53.492556 ===================================
6132 00:24:53.495967 ===================================
6133 00:24:53.499349 data_rate = 800
6134 00:24:53.499433 CKR = 1
6135 00:24:53.502492 DQ_P2S_RATIO = 4
6136 00:24:53.505761 ===================================
6137 00:24:53.509361 CA_P2S_RATIO = 4
6138 00:24:53.512650 DQ_CA_OPEN = 0
6139 00:24:53.515879 DQ_SEMI_OPEN = 1
6140 00:24:53.519231 CA_SEMI_OPEN = 1
6141 00:24:53.519322 CA_FULL_RATE = 0
6142 00:24:53.522660 DQ_CKDIV4_EN = 0
6143 00:24:53.525815 CA_CKDIV4_EN = 1
6144 00:24:53.528991 CA_PREDIV_EN = 0
6145 00:24:53.532271 PH8_DLY = 0
6146 00:24:53.535508 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6147 00:24:53.535601 DQ_AAMCK_DIV = 0
6148 00:24:53.538997 CA_AAMCK_DIV = 0
6149 00:24:53.542355 CA_ADMCK_DIV = 4
6150 00:24:53.545487 DQ_TRACK_CA_EN = 0
6151 00:24:53.549190 CA_PICK = 800
6152 00:24:53.552177 CA_MCKIO = 400
6153 00:24:53.555645 MCKIO_SEMI = 400
6154 00:24:53.555738 PLL_FREQ = 3016
6155 00:24:53.559263 DQ_UI_PI_RATIO = 32
6156 00:24:53.562197 CA_UI_PI_RATIO = 32
6157 00:24:53.565539 ===================================
6158 00:24:53.568833 ===================================
6159 00:24:53.572221 memory_type:LPDDR4
6160 00:24:53.572321 GP_NUM : 10
6161 00:24:53.575552 SRAM_EN : 1
6162 00:24:53.578695 MD32_EN : 0
6163 00:24:53.582094 ===================================
6164 00:24:53.582189 [ANA_INIT] >>>>>>>>>>>>>>
6165 00:24:53.585668 <<<<<< [CONFIGURE PHASE]: ANA_TX
6166 00:24:53.588613 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6167 00:24:53.592198 ===================================
6168 00:24:53.595254 data_rate = 800,PCW = 0X7400
6169 00:24:53.598941 ===================================
6170 00:24:53.601887 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6171 00:24:53.608542 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6172 00:24:53.618667 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6173 00:24:53.625189 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6174 00:24:53.628726 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6175 00:24:53.632053 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6176 00:24:53.632148 [ANA_INIT] flow start
6177 00:24:53.635270 [ANA_INIT] PLL >>>>>>>>
6178 00:24:53.638613 [ANA_INIT] PLL <<<<<<<<
6179 00:24:53.638712 [ANA_INIT] MIDPI >>>>>>>>
6180 00:24:53.642020 [ANA_INIT] MIDPI <<<<<<<<
6181 00:24:53.645467 [ANA_INIT] DLL >>>>>>>>
6182 00:24:53.645558 [ANA_INIT] flow end
6183 00:24:53.652100 ============ LP4 DIFF to SE enter ============
6184 00:24:53.655236 ============ LP4 DIFF to SE exit ============
6185 00:24:53.655329 [ANA_INIT] <<<<<<<<<<<<<
6186 00:24:53.658863 [Flow] Enable top DCM control >>>>>
6187 00:24:53.662487 [Flow] Enable top DCM control <<<<<
6188 00:24:53.665381 Enable DLL master slave shuffle
6189 00:24:53.671919 ==============================================================
6190 00:24:53.672018 Gating Mode config
6191 00:24:53.678964 ==============================================================
6192 00:24:53.682029 Config description:
6193 00:24:53.691779 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6194 00:24:53.698698 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6195 00:24:53.702231 SELPH_MODE 0: By rank 1: By Phase
6196 00:24:53.708363 ==============================================================
6197 00:24:53.711946 GAT_TRACK_EN = 0
6198 00:24:53.715580 RX_GATING_MODE = 2
6199 00:24:53.715671 RX_GATING_TRACK_MODE = 2
6200 00:24:53.718486 SELPH_MODE = 1
6201 00:24:53.722249 PICG_EARLY_EN = 1
6202 00:24:53.725385 VALID_LAT_VALUE = 1
6203 00:24:53.731808 ==============================================================
6204 00:24:53.735241 Enter into Gating configuration >>>>
6205 00:24:53.738627 Exit from Gating configuration <<<<
6206 00:24:53.742060 Enter into DVFS_PRE_config >>>>>
6207 00:24:53.751883 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6208 00:24:53.754867 Exit from DVFS_PRE_config <<<<<
6209 00:24:53.758356 Enter into PICG configuration >>>>
6210 00:24:53.761901 Exit from PICG configuration <<<<
6211 00:24:53.764968 [RX_INPUT] configuration >>>>>
6212 00:24:53.768459 [RX_INPUT] configuration <<<<<
6213 00:24:53.771602 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6214 00:24:53.778515 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6215 00:24:53.785267 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6216 00:24:53.788269 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6217 00:24:53.795111 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6218 00:24:53.801638 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6219 00:24:53.804989 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6220 00:24:53.811994 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6221 00:24:53.815251 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6222 00:24:53.818364 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6223 00:24:53.821838 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6224 00:24:53.828607 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6225 00:24:53.831743 ===================================
6226 00:24:53.831839 LPDDR4 DRAM CONFIGURATION
6227 00:24:53.834842 ===================================
6228 00:24:53.838158 EX_ROW_EN[0] = 0x0
6229 00:24:53.841700 EX_ROW_EN[1] = 0x0
6230 00:24:53.841799 LP4Y_EN = 0x0
6231 00:24:53.845095 WORK_FSP = 0x0
6232 00:24:53.845195 WL = 0x2
6233 00:24:53.848302 RL = 0x2
6234 00:24:53.848391 BL = 0x2
6235 00:24:53.851342 RPST = 0x0
6236 00:24:53.851431 RD_PRE = 0x0
6237 00:24:53.854841 WR_PRE = 0x1
6238 00:24:53.854938 WR_PST = 0x0
6239 00:24:53.858354 DBI_WR = 0x0
6240 00:24:53.858444 DBI_RD = 0x0
6241 00:24:53.861457 OTF = 0x1
6242 00:24:53.864845 ===================================
6243 00:24:53.868355 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6244 00:24:53.871436 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6245 00:24:53.877983 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6246 00:24:53.881711 ===================================
6247 00:24:53.881811 LPDDR4 DRAM CONFIGURATION
6248 00:24:53.884543 ===================================
6249 00:24:53.888264 EX_ROW_EN[0] = 0x10
6250 00:24:53.891436 EX_ROW_EN[1] = 0x0
6251 00:24:53.891511 LP4Y_EN = 0x0
6252 00:24:53.894945 WORK_FSP = 0x0
6253 00:24:53.895043 WL = 0x2
6254 00:24:53.897890 RL = 0x2
6255 00:24:53.897980 BL = 0x2
6256 00:24:53.901374 RPST = 0x0
6257 00:24:53.901466 RD_PRE = 0x0
6258 00:24:53.904535 WR_PRE = 0x1
6259 00:24:53.904627 WR_PST = 0x0
6260 00:24:53.907994 DBI_WR = 0x0
6261 00:24:53.908086 DBI_RD = 0x0
6262 00:24:53.911349 OTF = 0x1
6263 00:24:53.914832 ===================================
6264 00:24:53.921361 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6265 00:24:53.924607 nWR fixed to 30
6266 00:24:53.924700 [ModeRegInit_LP4] CH0 RK0
6267 00:24:53.927778 [ModeRegInit_LP4] CH0 RK1
6268 00:24:53.931346 [ModeRegInit_LP4] CH1 RK0
6269 00:24:53.931440 [ModeRegInit_LP4] CH1 RK1
6270 00:24:53.934800 match AC timing 19
6271 00:24:53.937866 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6272 00:24:53.941288 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6273 00:24:53.947949 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6274 00:24:53.951715 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6275 00:24:53.958032 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6276 00:24:53.958130 ==
6277 00:24:53.961328 Dram Type= 6, Freq= 0, CH_0, rank 0
6278 00:24:53.964471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6279 00:24:53.964562 ==
6280 00:24:53.971201 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6281 00:24:53.974799 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6282 00:24:53.977814 [CA 0] Center 36 (8~64) winsize 57
6283 00:24:53.981547 [CA 1] Center 36 (8~64) winsize 57
6284 00:24:53.984528 [CA 2] Center 36 (8~64) winsize 57
6285 00:24:53.988209 [CA 3] Center 36 (8~64) winsize 57
6286 00:24:53.991566 [CA 4] Center 36 (8~64) winsize 57
6287 00:24:53.994756 [CA 5] Center 36 (8~64) winsize 57
6288 00:24:53.994846
6289 00:24:53.997723 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6290 00:24:53.997813
6291 00:24:54.001304 [CATrainingPosCal] consider 1 rank data
6292 00:24:54.004388 u2DelayCellTimex100 = 270/100 ps
6293 00:24:54.007945 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6294 00:24:54.010921 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6295 00:24:54.014537 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6296 00:24:54.021456 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6297 00:24:54.024632 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6298 00:24:54.027812 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6299 00:24:54.027904
6300 00:24:54.031122 CA PerBit enable=1, Macro0, CA PI delay=36
6301 00:24:54.031217
6302 00:24:54.034291 [CBTSetCACLKResult] CA Dly = 36
6303 00:24:54.034381 CS Dly: 1 (0~32)
6304 00:24:54.034465 ==
6305 00:24:54.037539 Dram Type= 6, Freq= 0, CH_0, rank 1
6306 00:24:54.044094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6307 00:24:54.044190 ==
6308 00:24:54.047533 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6309 00:24:54.054431 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6310 00:24:54.057478 [CA 0] Center 36 (8~64) winsize 57
6311 00:24:54.060774 [CA 1] Center 36 (8~64) winsize 57
6312 00:24:54.064306 [CA 2] Center 36 (8~64) winsize 57
6313 00:24:54.067463 [CA 3] Center 36 (8~64) winsize 57
6314 00:24:54.070927 [CA 4] Center 36 (8~64) winsize 57
6315 00:24:54.074060 [CA 5] Center 36 (8~64) winsize 57
6316 00:24:54.074158
6317 00:24:54.077483 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6318 00:24:54.077552
6319 00:24:54.081106 [CATrainingPosCal] consider 2 rank data
6320 00:24:54.084589 u2DelayCellTimex100 = 270/100 ps
6321 00:24:54.087590 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6322 00:24:54.091246 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6323 00:24:54.094251 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6324 00:24:54.097312 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6325 00:24:54.101055 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6326 00:24:54.104010 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6327 00:24:54.107565
6328 00:24:54.111140 CA PerBit enable=1, Macro0, CA PI delay=36
6329 00:24:54.111230
6330 00:24:54.114325 [CBTSetCACLKResult] CA Dly = 36
6331 00:24:54.114396 CS Dly: 1 (0~32)
6332 00:24:54.114455
6333 00:24:54.117469 ----->DramcWriteLeveling(PI) begin...
6334 00:24:54.117533 ==
6335 00:24:54.121079 Dram Type= 6, Freq= 0, CH_0, rank 0
6336 00:24:54.124100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6337 00:24:54.124212 ==
6338 00:24:54.127554 Write leveling (Byte 0): 40 => 8
6339 00:24:54.130892 Write leveling (Byte 1): 32 => 0
6340 00:24:54.134399 DramcWriteLeveling(PI) end<-----
6341 00:24:54.134490
6342 00:24:54.134572 ==
6343 00:24:54.137957 Dram Type= 6, Freq= 0, CH_0, rank 0
6344 00:24:54.141001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6345 00:24:54.144371 ==
6346 00:24:54.144464 [Gating] SW mode calibration
6347 00:24:54.154165 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6348 00:24:54.157354 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6349 00:24:54.160888 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6350 00:24:54.167563 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6351 00:24:54.171153 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6352 00:24:54.173982 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6353 00:24:54.180775 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6354 00:24:54.184317 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6355 00:24:54.187310 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6356 00:24:54.194476 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6357 00:24:54.197548 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6358 00:24:54.200850 Total UI for P1: 0, mck2ui 16
6359 00:24:54.204403 best dqsien dly found for B0: ( 0, 14, 24)
6360 00:24:54.207344 Total UI for P1: 0, mck2ui 16
6361 00:24:54.210922 best dqsien dly found for B1: ( 0, 14, 24)
6362 00:24:54.214476 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6363 00:24:54.217421 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6364 00:24:54.217485
6365 00:24:54.220500 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6366 00:24:54.224153 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6367 00:24:54.227285 [Gating] SW calibration Done
6368 00:24:54.227379 ==
6369 00:24:54.230791 Dram Type= 6, Freq= 0, CH_0, rank 0
6370 00:24:54.234047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6371 00:24:54.234145 ==
6372 00:24:54.237636 RX Vref Scan: 0
6373 00:24:54.237727
6374 00:24:54.240594 RX Vref 0 -> 0, step: 1
6375 00:24:54.240682
6376 00:24:54.243978 RX Delay -410 -> 252, step: 16
6377 00:24:54.247074 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6378 00:24:54.250567 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6379 00:24:54.254172 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6380 00:24:54.260503 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6381 00:24:54.263890 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6382 00:24:54.267207 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6383 00:24:54.270522 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6384 00:24:54.277382 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6385 00:24:54.280859 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6386 00:24:54.284422 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6387 00:24:54.287190 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6388 00:24:54.293851 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6389 00:24:54.297202 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6390 00:24:54.300724 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6391 00:24:54.304441 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6392 00:24:54.310717 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6393 00:24:54.310809 ==
6394 00:24:54.313804 Dram Type= 6, Freq= 0, CH_0, rank 0
6395 00:24:54.317316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6396 00:24:54.317412 ==
6397 00:24:54.317495 DQS Delay:
6398 00:24:54.320331 DQS0 = 27, DQS1 = 43
6399 00:24:54.320403 DQM Delay:
6400 00:24:54.323941 DQM0 = 12, DQM1 = 12
6401 00:24:54.324029 DQ Delay:
6402 00:24:54.327450 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6403 00:24:54.330544 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6404 00:24:54.333674 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6405 00:24:54.337146 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6406 00:24:54.337236
6407 00:24:54.337326
6408 00:24:54.337405 ==
6409 00:24:54.340677 Dram Type= 6, Freq= 0, CH_0, rank 0
6410 00:24:54.343642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6411 00:24:54.343734 ==
6412 00:24:54.343819
6413 00:24:54.343897
6414 00:24:54.347032 TX Vref Scan disable
6415 00:24:54.347150 == TX Byte 0 ==
6416 00:24:54.353674 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6417 00:24:54.356922 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6418 00:24:54.357015 == TX Byte 1 ==
6419 00:24:54.363590 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6420 00:24:54.367140 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6421 00:24:54.367228 ==
6422 00:24:54.370170 Dram Type= 6, Freq= 0, CH_0, rank 0
6423 00:24:54.373610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6424 00:24:54.373697 ==
6425 00:24:54.373787
6426 00:24:54.373867
6427 00:24:54.377094 TX Vref Scan disable
6428 00:24:54.380348 == TX Byte 0 ==
6429 00:24:54.383684 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6430 00:24:54.386952 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6431 00:24:54.390263 == TX Byte 1 ==
6432 00:24:54.393643 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6433 00:24:54.396837 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6434 00:24:54.396939
6435 00:24:54.397023 [DATLAT]
6436 00:24:54.400098 Freq=400, CH0 RK0
6437 00:24:54.400175
6438 00:24:54.400232 DATLAT Default: 0xf
6439 00:24:54.403373 0, 0xFFFF, sum = 0
6440 00:24:54.407027 1, 0xFFFF, sum = 0
6441 00:24:54.407119 2, 0xFFFF, sum = 0
6442 00:24:54.410189 3, 0xFFFF, sum = 0
6443 00:24:54.410292 4, 0xFFFF, sum = 0
6444 00:24:54.413739 5, 0xFFFF, sum = 0
6445 00:24:54.413814 6, 0xFFFF, sum = 0
6446 00:24:54.416846 7, 0xFFFF, sum = 0
6447 00:24:54.416937 8, 0xFFFF, sum = 0
6448 00:24:54.420312 9, 0xFFFF, sum = 0
6449 00:24:54.420401 10, 0xFFFF, sum = 0
6450 00:24:54.423303 11, 0xFFFF, sum = 0
6451 00:24:54.423393 12, 0xFFFF, sum = 0
6452 00:24:54.426827 13, 0x0, sum = 1
6453 00:24:54.426916 14, 0x0, sum = 2
6454 00:24:54.429775 15, 0x0, sum = 3
6455 00:24:54.429864 16, 0x0, sum = 4
6456 00:24:54.433360 best_step = 14
6457 00:24:54.433450
6458 00:24:54.433540 ==
6459 00:24:54.436503 Dram Type= 6, Freq= 0, CH_0, rank 0
6460 00:24:54.440170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6461 00:24:54.440262 ==
6462 00:24:54.443511 RX Vref Scan: 1
6463 00:24:54.443599
6464 00:24:54.443680 RX Vref 0 -> 0, step: 1
6465 00:24:54.443764
6466 00:24:54.446526 RX Delay -327 -> 252, step: 8
6467 00:24:54.446634
6468 00:24:54.449882 Set Vref, RX VrefLevel [Byte0]: 59
6469 00:24:54.453520 [Byte1]: 49
6470 00:24:54.457699
6471 00:24:54.457789 Final RX Vref Byte 0 = 59 to rank0
6472 00:24:54.460733 Final RX Vref Byte 1 = 49 to rank0
6473 00:24:54.464331 Final RX Vref Byte 0 = 59 to rank1
6474 00:24:54.467352 Final RX Vref Byte 1 = 49 to rank1==
6475 00:24:54.470956 Dram Type= 6, Freq= 0, CH_0, rank 0
6476 00:24:54.477664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6477 00:24:54.477736 ==
6478 00:24:54.477794 DQS Delay:
6479 00:24:54.480930 DQS0 = 28, DQS1 = 48
6480 00:24:54.481024 DQM Delay:
6481 00:24:54.481085 DQM0 = 11, DQM1 = 15
6482 00:24:54.484042 DQ Delay:
6483 00:24:54.487426 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6484 00:24:54.487518 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6485 00:24:54.490757 DQ8 =8, DQ9 =0, DQ10 =12, DQ11 =8
6486 00:24:54.494232 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =24
6487 00:24:54.494325
6488 00:24:54.497133
6489 00:24:54.503756 [DQSOSCAuto] RK0, (LSB)MR18= 0xb0a8, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 387 ps
6490 00:24:54.507207 CH0 RK0: MR19=C0C, MR18=B0A8
6491 00:24:54.513732 CH0_RK0: MR19=0xC0C, MR18=0xB0A8, DQSOSC=387, MR23=63, INC=394, DEC=262
6492 00:24:54.513803 ==
6493 00:24:54.517223 Dram Type= 6, Freq= 0, CH_0, rank 1
6494 00:24:54.520693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6495 00:24:54.520799 ==
6496 00:24:54.524210 [Gating] SW mode calibration
6497 00:24:54.530947 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6498 00:24:54.533948 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6499 00:24:54.540626 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6500 00:24:54.543791 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6501 00:24:54.547255 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6502 00:24:54.554115 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6503 00:24:54.557265 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6504 00:24:54.560610 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6505 00:24:54.567458 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6506 00:24:54.570587 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6507 00:24:54.574081 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6508 00:24:54.577148 Total UI for P1: 0, mck2ui 16
6509 00:24:54.580608 best dqsien dly found for B0: ( 0, 14, 24)
6510 00:24:54.583873 Total UI for P1: 0, mck2ui 16
6511 00:24:54.587623 best dqsien dly found for B1: ( 0, 14, 24)
6512 00:24:54.590637 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6513 00:24:54.594125 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6514 00:24:54.594223
6515 00:24:54.600982 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6516 00:24:54.604203 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6517 00:24:54.607498 [Gating] SW calibration Done
6518 00:24:54.607592 ==
6519 00:24:54.610672 Dram Type= 6, Freq= 0, CH_0, rank 1
6520 00:24:54.614122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6521 00:24:54.614236 ==
6522 00:24:54.614328 RX Vref Scan: 0
6523 00:24:54.614385
6524 00:24:54.617214 RX Vref 0 -> 0, step: 1
6525 00:24:54.617296
6526 00:24:54.620374 RX Delay -410 -> 252, step: 16
6527 00:24:54.623932 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6528 00:24:54.630579 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6529 00:24:54.633977 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6530 00:24:54.637052 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6531 00:24:54.640728 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6532 00:24:54.647347 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6533 00:24:54.650290 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6534 00:24:54.653805 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6535 00:24:54.657372 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6536 00:24:54.660782 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6537 00:24:54.667002 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6538 00:24:54.670221 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6539 00:24:54.673897 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6540 00:24:54.680437 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6541 00:24:54.683865 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6542 00:24:54.686992 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6543 00:24:54.687150 ==
6544 00:24:54.690409 Dram Type= 6, Freq= 0, CH_0, rank 1
6545 00:24:54.693528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6546 00:24:54.697007 ==
6547 00:24:54.697081 DQS Delay:
6548 00:24:54.697152 DQS0 = 27, DQS1 = 43
6549 00:24:54.700394 DQM Delay:
6550 00:24:54.700464 DQM0 = 9, DQM1 = 15
6551 00:24:54.703771 DQ Delay:
6552 00:24:54.703873 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6553 00:24:54.706875 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6554 00:24:54.710459 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6555 00:24:54.713237 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6556 00:24:54.713320
6557 00:24:54.713379
6558 00:24:54.713434 ==
6559 00:24:54.716851 Dram Type= 6, Freq= 0, CH_0, rank 1
6560 00:24:54.723422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6561 00:24:54.723525 ==
6562 00:24:54.723616
6563 00:24:54.723698
6564 00:24:54.723787 TX Vref Scan disable
6565 00:24:54.726809 == TX Byte 0 ==
6566 00:24:54.730191 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6567 00:24:54.733397 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6568 00:24:54.736589 == TX Byte 1 ==
6569 00:24:54.739725 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6570 00:24:54.743166 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6571 00:24:54.743268 ==
6572 00:24:54.746662 Dram Type= 6, Freq= 0, CH_0, rank 1
6573 00:24:54.753333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6574 00:24:54.753411 ==
6575 00:24:54.753488
6576 00:24:54.753571
6577 00:24:54.756379 TX Vref Scan disable
6578 00:24:54.756471 == TX Byte 0 ==
6579 00:24:54.759833 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6580 00:24:54.763178 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6581 00:24:54.766332 == TX Byte 1 ==
6582 00:24:54.770013 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6583 00:24:54.772926 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6584 00:24:54.776081
6585 00:24:54.776177 [DATLAT]
6586 00:24:54.776263 Freq=400, CH0 RK1
6587 00:24:54.776357
6588 00:24:54.779654 DATLAT Default: 0xe
6589 00:24:54.779750 0, 0xFFFF, sum = 0
6590 00:24:54.782824 1, 0xFFFF, sum = 0
6591 00:24:54.782925 2, 0xFFFF, sum = 0
6592 00:24:54.786474 3, 0xFFFF, sum = 0
6593 00:24:54.786550 4, 0xFFFF, sum = 0
6594 00:24:54.789366 5, 0xFFFF, sum = 0
6595 00:24:54.792848 6, 0xFFFF, sum = 0
6596 00:24:54.792937 7, 0xFFFF, sum = 0
6597 00:24:54.796389 8, 0xFFFF, sum = 0
6598 00:24:54.796484 9, 0xFFFF, sum = 0
6599 00:24:54.799491 10, 0xFFFF, sum = 0
6600 00:24:54.799562 11, 0xFFFF, sum = 0
6601 00:24:54.802833 12, 0xFFFF, sum = 0
6602 00:24:54.802902 13, 0x0, sum = 1
6603 00:24:54.806286 14, 0x0, sum = 2
6604 00:24:54.806368 15, 0x0, sum = 3
6605 00:24:54.809703 16, 0x0, sum = 4
6606 00:24:54.809775 best_step = 14
6607 00:24:54.809832
6608 00:24:54.809903 ==
6609 00:24:54.812720 Dram Type= 6, Freq= 0, CH_0, rank 1
6610 00:24:54.816467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6611 00:24:54.816555 ==
6612 00:24:54.819362 RX Vref Scan: 0
6613 00:24:54.819502
6614 00:24:54.823078 RX Vref 0 -> 0, step: 1
6615 00:24:54.823175
6616 00:24:54.823266 RX Delay -327 -> 252, step: 8
6617 00:24:54.831626 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6618 00:24:54.834728 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6619 00:24:54.838500 iDelay=217, Bit 2, Center -24 (-247 ~ 200) 448
6620 00:24:54.841429 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6621 00:24:54.847988 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6622 00:24:54.851307 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6623 00:24:54.854965 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6624 00:24:54.857967 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6625 00:24:54.864609 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6626 00:24:54.868042 iDelay=217, Bit 9, Center -44 (-271 ~ 184) 456
6627 00:24:54.871208 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6628 00:24:54.874699 iDelay=217, Bit 11, Center -36 (-263 ~ 192) 456
6629 00:24:54.881477 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6630 00:24:54.885203 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6631 00:24:54.888299 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6632 00:24:54.891434 iDelay=217, Bit 15, Center -24 (-247 ~ 200) 448
6633 00:24:54.895296 ==
6634 00:24:54.895417 Dram Type= 6, Freq= 0, CH_0, rank 1
6635 00:24:54.901703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6636 00:24:54.901816 ==
6637 00:24:54.901910 DQS Delay:
6638 00:24:54.905176 DQS0 = 28, DQS1 = 44
6639 00:24:54.905267 DQM Delay:
6640 00:24:54.908254 DQM0 = 10, DQM1 = 14
6641 00:24:54.908350 DQ Delay:
6642 00:24:54.911639 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =4
6643 00:24:54.915266 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6644 00:24:54.918263 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6645 00:24:54.921872 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6646 00:24:54.921953
6647 00:24:54.922013
6648 00:24:54.928291 [DQSOSCAuto] RK1, (LSB)MR18= 0xc074, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 386 ps
6649 00:24:54.931828 CH0 RK1: MR19=C0C, MR18=C074
6650 00:24:54.938228 CH0_RK1: MR19=0xC0C, MR18=0xC074, DQSOSC=386, MR23=63, INC=396, DEC=264
6651 00:24:54.941627 [RxdqsGatingPostProcess] freq 400
6652 00:24:54.944743 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6653 00:24:54.947901 best DQS0 dly(2T, 0.5T) = (0, 10)
6654 00:24:54.951685 best DQS1 dly(2T, 0.5T) = (0, 10)
6655 00:24:54.954685 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6656 00:24:54.958077 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6657 00:24:54.961329 best DQS0 dly(2T, 0.5T) = (0, 10)
6658 00:24:54.964696 best DQS1 dly(2T, 0.5T) = (0, 10)
6659 00:24:54.968097 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6660 00:24:54.971299 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6661 00:24:54.974875 Pre-setting of DQS Precalculation
6662 00:24:54.977896 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6663 00:24:54.981143 ==
6664 00:24:54.981229 Dram Type= 6, Freq= 0, CH_1, rank 0
6665 00:24:54.987653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6666 00:24:54.987757 ==
6667 00:24:54.991183 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6668 00:24:54.997794 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6669 00:24:55.001063 [CA 0] Center 36 (8~64) winsize 57
6670 00:24:55.004691 [CA 1] Center 36 (8~64) winsize 57
6671 00:24:55.007762 [CA 2] Center 36 (8~64) winsize 57
6672 00:24:55.011234 [CA 3] Center 36 (8~64) winsize 57
6673 00:24:55.014756 [CA 4] Center 36 (8~64) winsize 57
6674 00:24:55.017926 [CA 5] Center 36 (8~64) winsize 57
6675 00:24:55.018008
6676 00:24:55.020855 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6677 00:24:55.020935
6678 00:24:55.024334 [CATrainingPosCal] consider 1 rank data
6679 00:24:55.027716 u2DelayCellTimex100 = 270/100 ps
6680 00:24:55.031014 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6681 00:24:55.034606 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6682 00:24:55.037550 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6683 00:24:55.041084 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6684 00:24:55.044070 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6685 00:24:55.050871 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6686 00:24:55.050951
6687 00:24:55.054454 CA PerBit enable=1, Macro0, CA PI delay=36
6688 00:24:55.054533
6689 00:24:55.057401 [CBTSetCACLKResult] CA Dly = 36
6690 00:24:55.057480 CS Dly: 1 (0~32)
6691 00:24:55.057542 ==
6692 00:24:55.061013 Dram Type= 6, Freq= 0, CH_1, rank 1
6693 00:24:55.064209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6694 00:24:55.067733 ==
6695 00:24:55.070737 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6696 00:24:55.077489 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6697 00:24:55.080727 [CA 0] Center 36 (8~64) winsize 57
6698 00:24:55.084473 [CA 1] Center 36 (8~64) winsize 57
6699 00:24:55.087428 [CA 2] Center 36 (8~64) winsize 57
6700 00:24:55.091015 [CA 3] Center 36 (8~64) winsize 57
6701 00:24:55.094216 [CA 4] Center 36 (8~64) winsize 57
6702 00:24:55.097875 [CA 5] Center 36 (8~64) winsize 57
6703 00:24:55.097954
6704 00:24:55.100800 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6705 00:24:55.100879
6706 00:24:55.104240 [CATrainingPosCal] consider 2 rank data
6707 00:24:55.107739 u2DelayCellTimex100 = 270/100 ps
6708 00:24:55.110796 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6709 00:24:55.114352 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6710 00:24:55.117623 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6711 00:24:55.120599 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6712 00:24:55.124150 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6713 00:24:55.127205 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6714 00:24:55.127283
6715 00:24:55.130742 CA PerBit enable=1, Macro0, CA PI delay=36
6716 00:24:55.130821
6717 00:24:55.134134 [CBTSetCACLKResult] CA Dly = 36
6718 00:24:55.137686 CS Dly: 1 (0~32)
6719 00:24:55.137765
6720 00:24:55.140788 ----->DramcWriteLeveling(PI) begin...
6721 00:24:55.140870 ==
6722 00:24:55.144282 Dram Type= 6, Freq= 0, CH_1, rank 0
6723 00:24:55.147367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6724 00:24:55.147446 ==
6725 00:24:55.150723 Write leveling (Byte 0): 40 => 8
6726 00:24:55.154017 Write leveling (Byte 1): 32 => 0
6727 00:24:55.157466 DramcWriteLeveling(PI) end<-----
6728 00:24:55.157544
6729 00:24:55.157605 ==
6730 00:24:55.160596 Dram Type= 6, Freq= 0, CH_1, rank 0
6731 00:24:55.163729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6732 00:24:55.163824 ==
6733 00:24:55.167193 [Gating] SW mode calibration
6734 00:24:55.173846 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6735 00:24:55.180754 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6736 00:24:55.183691 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6737 00:24:55.190252 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6738 00:24:55.193628 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6739 00:24:55.196964 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6740 00:24:55.203834 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6741 00:24:55.207151 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6742 00:24:55.210469 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6743 00:24:55.216936 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6744 00:24:55.220487 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6745 00:24:55.223917 Total UI for P1: 0, mck2ui 16
6746 00:24:55.226881 best dqsien dly found for B0: ( 0, 14, 24)
6747 00:24:55.230243 Total UI for P1: 0, mck2ui 16
6748 00:24:55.233809 best dqsien dly found for B1: ( 0, 14, 24)
6749 00:24:55.236682 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6750 00:24:55.240395 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6751 00:24:55.240472
6752 00:24:55.243381 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6753 00:24:55.246971 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6754 00:24:55.250116 [Gating] SW calibration Done
6755 00:24:55.250193 ==
6756 00:24:55.253610 Dram Type= 6, Freq= 0, CH_1, rank 0
6757 00:24:55.256826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6758 00:24:55.256905 ==
6759 00:24:55.260105 RX Vref Scan: 0
6760 00:24:55.260182
6761 00:24:55.263618 RX Vref 0 -> 0, step: 1
6762 00:24:55.263695
6763 00:24:55.263755 RX Delay -410 -> 252, step: 16
6764 00:24:55.270376 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6765 00:24:55.273461 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6766 00:24:55.276891 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6767 00:24:55.280431 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6768 00:24:55.286927 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6769 00:24:55.290446 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6770 00:24:55.293465 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6771 00:24:55.296963 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6772 00:24:55.303490 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6773 00:24:55.307277 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6774 00:24:55.310199 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6775 00:24:55.313590 iDelay=230, Bit 11, Center -19 (-250 ~ 213) 464
6776 00:24:55.320429 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6777 00:24:55.323754 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6778 00:24:55.326744 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6779 00:24:55.330251 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6780 00:24:55.333836 ==
6781 00:24:55.336877 Dram Type= 6, Freq= 0, CH_1, rank 0
6782 00:24:55.340232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6783 00:24:55.340310 ==
6784 00:24:55.340369 DQS Delay:
6785 00:24:55.343561 DQS0 = 19, DQS1 = 43
6786 00:24:55.343639 DQM Delay:
6787 00:24:55.347192 DQM0 = 1, DQM1 = 20
6788 00:24:55.347269 DQ Delay:
6789 00:24:55.350152 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6790 00:24:55.353664 DQ4 =0, DQ5 =0, DQ6 =8, DQ7 =0
6791 00:24:55.356793 DQ8 =0, DQ9 =0, DQ10 =24, DQ11 =24
6792 00:24:55.360346 DQ12 =32, DQ13 =24, DQ14 =24, DQ15 =32
6793 00:24:55.360438
6794 00:24:55.360522
6795 00:24:55.360603 ==
6796 00:24:55.363372 Dram Type= 6, Freq= 0, CH_1, rank 0
6797 00:24:55.366998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6798 00:24:55.367091 ==
6799 00:24:55.367179
6800 00:24:55.367347
6801 00:24:55.370007 TX Vref Scan disable
6802 00:24:55.370112 == TX Byte 0 ==
6803 00:24:55.376714 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6804 00:24:55.380201 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6805 00:24:55.380301 == TX Byte 1 ==
6806 00:24:55.383689 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6807 00:24:55.390158 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6808 00:24:55.390253 ==
6809 00:24:55.393737 Dram Type= 6, Freq= 0, CH_1, rank 0
6810 00:24:55.396612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6811 00:24:55.396711 ==
6812 00:24:55.396788
6813 00:24:55.396857
6814 00:24:55.400206 TX Vref Scan disable
6815 00:24:55.400303 == TX Byte 0 ==
6816 00:24:55.406804 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6817 00:24:55.410197 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6818 00:24:55.410299 == TX Byte 1 ==
6819 00:24:55.417284 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6820 00:24:55.420239 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6821 00:24:55.420342
6822 00:24:55.420427 [DATLAT]
6823 00:24:55.423633 Freq=400, CH1 RK0
6824 00:24:55.423730
6825 00:24:55.423825 DATLAT Default: 0xf
6826 00:24:55.426604 0, 0xFFFF, sum = 0
6827 00:24:55.426703 1, 0xFFFF, sum = 0
6828 00:24:55.430107 2, 0xFFFF, sum = 0
6829 00:24:55.430208 3, 0xFFFF, sum = 0
6830 00:24:55.433448 4, 0xFFFF, sum = 0
6831 00:24:55.433555 5, 0xFFFF, sum = 0
6832 00:24:55.436713 6, 0xFFFF, sum = 0
6833 00:24:55.436815 7, 0xFFFF, sum = 0
6834 00:24:55.440101 8, 0xFFFF, sum = 0
6835 00:24:55.440203 9, 0xFFFF, sum = 0
6836 00:24:55.443663 10, 0xFFFF, sum = 0
6837 00:24:55.443756 11, 0xFFFF, sum = 0
6838 00:24:55.446662 12, 0xFFFF, sum = 0
6839 00:24:55.446765 13, 0x0, sum = 1
6840 00:24:55.450092 14, 0x0, sum = 2
6841 00:24:55.450191 15, 0x0, sum = 3
6842 00:24:55.453637 16, 0x0, sum = 4
6843 00:24:55.453731 best_step = 14
6844 00:24:55.453816
6845 00:24:55.453915 ==
6846 00:24:55.456712 Dram Type= 6, Freq= 0, CH_1, rank 0
6847 00:24:55.463372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6848 00:24:55.463476 ==
6849 00:24:55.463563 RX Vref Scan: 1
6850 00:24:55.463652
6851 00:24:55.466869 RX Vref 0 -> 0, step: 1
6852 00:24:55.466968
6853 00:24:55.470216 RX Delay -327 -> 252, step: 8
6854 00:24:55.470291
6855 00:24:55.473182 Set Vref, RX VrefLevel [Byte0]: 52
6856 00:24:55.476647 [Byte1]: 50
6857 00:24:55.479718
6858 00:24:55.479816 Final RX Vref Byte 0 = 52 to rank0
6859 00:24:55.483477 Final RX Vref Byte 1 = 50 to rank0
6860 00:24:55.486517 Final RX Vref Byte 0 = 52 to rank1
6861 00:24:55.490094 Final RX Vref Byte 1 = 50 to rank1==
6862 00:24:55.493311 Dram Type= 6, Freq= 0, CH_1, rank 0
6863 00:24:55.499823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6864 00:24:55.499923 ==
6865 00:24:55.500009 DQS Delay:
6866 00:24:55.503366 DQS0 = 32, DQS1 = 40
6867 00:24:55.503444 DQM Delay:
6868 00:24:55.503502 DQM0 = 12, DQM1 = 13
6869 00:24:55.506186 DQ Delay:
6870 00:24:55.509895 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
6871 00:24:55.509971 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6872 00:24:55.513106 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6873 00:24:55.516420 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6874 00:24:55.516496
6875 00:24:55.519894
6876 00:24:55.526140 [DQSOSCAuto] RK0, (LSB)MR18= 0x96d0, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6877 00:24:55.529793 CH1 RK0: MR19=C0C, MR18=96D0
6878 00:24:55.536340 CH1_RK0: MR19=0xC0C, MR18=0x96D0, DQSOSC=384, MR23=63, INC=400, DEC=267
6879 00:24:55.536439 ==
6880 00:24:55.539722 Dram Type= 6, Freq= 0, CH_1, rank 1
6881 00:24:55.542690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6882 00:24:55.542767 ==
6883 00:24:55.546224 [Gating] SW mode calibration
6884 00:24:55.552732 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6885 00:24:55.559370 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6886 00:24:55.562464 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6887 00:24:55.565879 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6888 00:24:55.572459 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6889 00:24:55.575603 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6890 00:24:55.579007 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6891 00:24:55.585857 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6892 00:24:55.588946 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6893 00:24:55.592584 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6894 00:24:55.599080 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6895 00:24:55.599157 Total UI for P1: 0, mck2ui 16
6896 00:24:55.605523 best dqsien dly found for B0: ( 0, 14, 24)
6897 00:24:55.605601 Total UI for P1: 0, mck2ui 16
6898 00:24:55.609178 best dqsien dly found for B1: ( 0, 14, 24)
6899 00:24:55.615827 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6900 00:24:55.618683 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6901 00:24:55.618761
6902 00:24:55.622359 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6903 00:24:55.625367 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6904 00:24:55.628584 [Gating] SW calibration Done
6905 00:24:55.628677 ==
6906 00:24:55.631844 Dram Type= 6, Freq= 0, CH_1, rank 1
6907 00:24:55.635341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6908 00:24:55.635420 ==
6909 00:24:55.638749 RX Vref Scan: 0
6910 00:24:55.638825
6911 00:24:55.638885 RX Vref 0 -> 0, step: 1
6912 00:24:55.638940
6913 00:24:55.642187 RX Delay -410 -> 252, step: 16
6914 00:24:55.648356 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6915 00:24:55.651813 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6916 00:24:55.654959 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6917 00:24:55.658718 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6918 00:24:55.664874 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6919 00:24:55.668451 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6920 00:24:55.671821 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6921 00:24:55.675040 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6922 00:24:55.681873 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6923 00:24:55.685041 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6924 00:24:55.688289 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6925 00:24:55.691734 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6926 00:24:55.698375 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6927 00:24:55.701454 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6928 00:24:55.705027 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6929 00:24:55.708241 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6930 00:24:55.711487 ==
6931 00:24:55.711568 Dram Type= 6, Freq= 0, CH_1, rank 1
6932 00:24:55.718381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6933 00:24:55.718463 ==
6934 00:24:55.718525 DQS Delay:
6935 00:24:55.722135 DQS0 = 35, DQS1 = 43
6936 00:24:55.722215 DQM Delay:
6937 00:24:55.724978 DQM0 = 16, DQM1 = 19
6938 00:24:55.725058 DQ Delay:
6939 00:24:55.728039 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6940 00:24:55.731489 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =16
6941 00:24:55.734902 DQ8 =0, DQ9 =8, DQ10 =24, DQ11 =16
6942 00:24:55.738143 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =32
6943 00:24:55.738220
6944 00:24:55.738280
6945 00:24:55.738335 ==
6946 00:24:55.741368 Dram Type= 6, Freq= 0, CH_1, rank 1
6947 00:24:55.744860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6948 00:24:55.744939 ==
6949 00:24:55.744999
6950 00:24:55.745053
6951 00:24:55.748062 TX Vref Scan disable
6952 00:24:55.748138 == TX Byte 0 ==
6953 00:24:55.754822 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6954 00:24:55.757958 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6955 00:24:55.758060 == TX Byte 1 ==
6956 00:24:55.764476 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6957 00:24:55.767954 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6958 00:24:55.768053 ==
6959 00:24:55.771608 Dram Type= 6, Freq= 0, CH_1, rank 1
6960 00:24:55.774570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6961 00:24:55.774641 ==
6962 00:24:55.774698
6963 00:24:55.774751
6964 00:24:55.778160 TX Vref Scan disable
6965 00:24:55.778226 == TX Byte 0 ==
6966 00:24:55.784973 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6967 00:24:55.787954 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6968 00:24:55.788031 == TX Byte 1 ==
6969 00:24:55.794842 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6970 00:24:55.798500 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6971 00:24:55.798580
6972 00:24:55.798649 [DATLAT]
6973 00:24:55.801224 Freq=400, CH1 RK1
6974 00:24:55.801302
6975 00:24:55.801363 DATLAT Default: 0xe
6976 00:24:55.804734 0, 0xFFFF, sum = 0
6977 00:24:55.804840 1, 0xFFFF, sum = 0
6978 00:24:55.807862 2, 0xFFFF, sum = 0
6979 00:24:55.807942 3, 0xFFFF, sum = 0
6980 00:24:55.811371 4, 0xFFFF, sum = 0
6981 00:24:55.811451 5, 0xFFFF, sum = 0
6982 00:24:55.814904 6, 0xFFFF, sum = 0
6983 00:24:55.814983 7, 0xFFFF, sum = 0
6984 00:24:55.818067 8, 0xFFFF, sum = 0
6985 00:24:55.818147 9, 0xFFFF, sum = 0
6986 00:24:55.821205 10, 0xFFFF, sum = 0
6987 00:24:55.824733 11, 0xFFFF, sum = 0
6988 00:24:55.824813 12, 0xFFFF, sum = 0
6989 00:24:55.828272 13, 0x0, sum = 1
6990 00:24:55.828383 14, 0x0, sum = 2
6991 00:24:55.828473 15, 0x0, sum = 3
6992 00:24:55.831289 16, 0x0, sum = 4
6993 00:24:55.831368 best_step = 14
6994 00:24:55.831429
6995 00:24:55.831486 ==
6996 00:24:55.834686 Dram Type= 6, Freq= 0, CH_1, rank 1
6997 00:24:55.841264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6998 00:24:55.841344 ==
6999 00:24:55.841405 RX Vref Scan: 0
7000 00:24:55.841461
7001 00:24:55.844454 RX Vref 0 -> 0, step: 1
7002 00:24:55.844533
7003 00:24:55.847986 RX Delay -327 -> 252, step: 8
7004 00:24:55.854843 iDelay=217, Bit 0, Center -16 (-231 ~ 200) 432
7005 00:24:55.858159 iDelay=217, Bit 1, Center -28 (-247 ~ 192) 440
7006 00:24:55.861095 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
7007 00:24:55.864729 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
7008 00:24:55.871166 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
7009 00:24:55.874505 iDelay=217, Bit 5, Center -12 (-239 ~ 216) 456
7010 00:24:55.877817 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
7011 00:24:55.881220 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
7012 00:24:55.888086 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
7013 00:24:55.891076 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
7014 00:24:55.894676 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
7015 00:24:55.897843 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
7016 00:24:55.904580 iDelay=217, Bit 12, Center -16 (-239 ~ 208) 448
7017 00:24:55.907824 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
7018 00:24:55.910982 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
7019 00:24:55.917610 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
7020 00:24:55.917710 ==
7021 00:24:55.921258 Dram Type= 6, Freq= 0, CH_1, rank 1
7022 00:24:55.924476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7023 00:24:55.924554 ==
7024 00:24:55.924613 DQS Delay:
7025 00:24:55.927954 DQS0 = 32, DQS1 = 36
7026 00:24:55.928030 DQM Delay:
7027 00:24:55.931073 DQM0 = 12, DQM1 = 12
7028 00:24:55.931150 DQ Delay:
7029 00:24:55.934645 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
7030 00:24:55.937714 DQ4 =16, DQ5 =20, DQ6 =20, DQ7 =12
7031 00:24:55.941518 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =8
7032 00:24:55.944459 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =24
7033 00:24:55.944536
7034 00:24:55.944595
7035 00:24:55.951055 [DQSOSCAuto] RK1, (LSB)MR18= 0xae57, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 388 ps
7036 00:24:55.954703 CH1 RK1: MR19=C0C, MR18=AE57
7037 00:24:55.961044 CH1_RK1: MR19=0xC0C, MR18=0xAE57, DQSOSC=388, MR23=63, INC=392, DEC=261
7038 00:24:55.964202 [RxdqsGatingPostProcess] freq 400
7039 00:24:55.967717 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7040 00:24:55.970801 best DQS0 dly(2T, 0.5T) = (0, 10)
7041 00:24:55.974099 best DQS1 dly(2T, 0.5T) = (0, 10)
7042 00:24:55.977454 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7043 00:24:55.980977 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7044 00:24:55.984180 best DQS0 dly(2T, 0.5T) = (0, 10)
7045 00:24:55.987587 best DQS1 dly(2T, 0.5T) = (0, 10)
7046 00:24:55.990539 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7047 00:24:55.994212 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7048 00:24:55.997709 Pre-setting of DQS Precalculation
7049 00:24:56.000850 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7050 00:24:56.010922 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7051 00:24:56.017213 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7052 00:24:56.017293
7053 00:24:56.017353
7054 00:24:56.020844 [Calibration Summary] 800 Mbps
7055 00:24:56.020924 CH 0, Rank 0
7056 00:24:56.023868 SW Impedance : PASS
7057 00:24:56.023975 DUTY Scan : NO K
7058 00:24:56.027588 ZQ Calibration : PASS
7059 00:24:56.030735 Jitter Meter : NO K
7060 00:24:56.030829 CBT Training : PASS
7061 00:24:56.033931 Write leveling : PASS
7062 00:24:56.037141 RX DQS gating : PASS
7063 00:24:56.037218 RX DQ/DQS(RDDQC) : PASS
7064 00:24:56.041005 TX DQ/DQS : PASS
7065 00:24:56.044158 RX DATLAT : PASS
7066 00:24:56.044235 RX DQ/DQS(Engine): PASS
7067 00:24:56.047271 TX OE : NO K
7068 00:24:56.047350 All Pass.
7069 00:24:56.047414
7070 00:24:56.050930 CH 0, Rank 1
7071 00:24:56.051023 SW Impedance : PASS
7072 00:24:56.053939 DUTY Scan : NO K
7073 00:24:56.057522 ZQ Calibration : PASS
7074 00:24:56.057627 Jitter Meter : NO K
7075 00:24:56.060655 CBT Training : PASS
7076 00:24:56.060755 Write leveling : NO K
7077 00:24:56.063739 RX DQS gating : PASS
7078 00:24:56.067462 RX DQ/DQS(RDDQC) : PASS
7079 00:24:56.067542 TX DQ/DQS : PASS
7080 00:24:56.070552 RX DATLAT : PASS
7081 00:24:56.073767 RX DQ/DQS(Engine): PASS
7082 00:24:56.073861 TX OE : NO K
7083 00:24:56.077122 All Pass.
7084 00:24:56.077229
7085 00:24:56.077288 CH 1, Rank 0
7086 00:24:56.080693 SW Impedance : PASS
7087 00:24:56.080825 DUTY Scan : NO K
7088 00:24:56.083700 ZQ Calibration : PASS
7089 00:24:56.087360 Jitter Meter : NO K
7090 00:24:56.087439 CBT Training : PASS
7091 00:24:56.090373 Write leveling : PASS
7092 00:24:56.094151 RX DQS gating : PASS
7093 00:24:56.094299 RX DQ/DQS(RDDQC) : PASS
7094 00:24:56.097030 TX DQ/DQS : PASS
7095 00:24:56.100361 RX DATLAT : PASS
7096 00:24:56.100497 RX DQ/DQS(Engine): PASS
7097 00:24:56.103760 TX OE : NO K
7098 00:24:56.103892 All Pass.
7099 00:24:56.103983
7100 00:24:56.107029 CH 1, Rank 1
7101 00:24:56.107157 SW Impedance : PASS
7102 00:24:56.110470 DUTY Scan : NO K
7103 00:24:56.113484 ZQ Calibration : PASS
7104 00:24:56.113609 Jitter Meter : NO K
7105 00:24:56.116821 CBT Training : PASS
7106 00:24:56.116935 Write leveling : NO K
7107 00:24:56.120225 RX DQS gating : PASS
7108 00:24:56.123743 RX DQ/DQS(RDDQC) : PASS
7109 00:24:56.123836 TX DQ/DQS : PASS
7110 00:24:56.127297 RX DATLAT : PASS
7111 00:24:56.130403 RX DQ/DQS(Engine): PASS
7112 00:24:56.130495 TX OE : NO K
7113 00:24:56.134065 All Pass.
7114 00:24:56.134180
7115 00:24:56.134271 DramC Write-DBI off
7116 00:24:56.137134 PER_BANK_REFRESH: Hybrid Mode
7117 00:24:56.137214 TX_TRACKING: ON
7118 00:24:56.147142 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7119 00:24:56.150645 [FAST_K] Save calibration result to emmc
7120 00:24:56.153729 dramc_set_vcore_voltage set vcore to 725000
7121 00:24:56.156832 Read voltage for 1600, 0
7122 00:24:56.156911 Vio18 = 0
7123 00:24:56.160352 Vcore = 725000
7124 00:24:56.160431 Vdram = 0
7125 00:24:56.160492 Vddq = 0
7126 00:24:56.163360 Vmddr = 0
7127 00:24:56.166884 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7128 00:24:56.173382 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7129 00:24:56.173462 MEM_TYPE=3, freq_sel=13
7130 00:24:56.176878 sv_algorithm_assistance_LP4_3733
7131 00:24:56.183840 ============ PULL DRAM RESETB DOWN ============
7132 00:24:56.186821 ========== PULL DRAM RESETB DOWN end =========
7133 00:24:56.190530 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7134 00:24:56.193392 ===================================
7135 00:24:56.196803 LPDDR4 DRAM CONFIGURATION
7136 00:24:56.199908 ===================================
7137 00:24:56.199980 EX_ROW_EN[0] = 0x0
7138 00:24:56.203342 EX_ROW_EN[1] = 0x0
7139 00:24:56.206885 LP4Y_EN = 0x0
7140 00:24:56.206979 WORK_FSP = 0x1
7141 00:24:56.210477 WL = 0x5
7142 00:24:56.210571 RL = 0x5
7143 00:24:56.213585 BL = 0x2
7144 00:24:56.213682 RPST = 0x0
7145 00:24:56.216694 RD_PRE = 0x0
7146 00:24:56.216792 WR_PRE = 0x1
7147 00:24:56.220017 WR_PST = 0x1
7148 00:24:56.220086 DBI_WR = 0x0
7149 00:24:56.223464 DBI_RD = 0x0
7150 00:24:56.223561 OTF = 0x1
7151 00:24:56.226835 ===================================
7152 00:24:56.230487 ===================================
7153 00:24:56.233479 ANA top config
7154 00:24:56.237033 ===================================
7155 00:24:56.237110 DLL_ASYNC_EN = 0
7156 00:24:56.240055 ALL_SLAVE_EN = 0
7157 00:24:56.243779 NEW_RANK_MODE = 1
7158 00:24:56.246929 DLL_IDLE_MODE = 1
7159 00:24:56.247008 LP45_APHY_COMB_EN = 1
7160 00:24:56.250371 TX_ODT_DIS = 0
7161 00:24:56.253315 NEW_8X_MODE = 1
7162 00:24:56.256714 ===================================
7163 00:24:56.260213 ===================================
7164 00:24:56.263609 data_rate = 3200
7165 00:24:56.267006 CKR = 1
7166 00:24:56.270386 DQ_P2S_RATIO = 8
7167 00:24:56.273367 ===================================
7168 00:24:56.273442 CA_P2S_RATIO = 8
7169 00:24:56.277079 DQ_CA_OPEN = 0
7170 00:24:56.280627 DQ_SEMI_OPEN = 0
7171 00:24:56.283841 CA_SEMI_OPEN = 0
7172 00:24:56.287043 CA_FULL_RATE = 0
7173 00:24:56.287119 DQ_CKDIV4_EN = 0
7174 00:24:56.290472 CA_CKDIV4_EN = 0
7175 00:24:56.293407 CA_PREDIV_EN = 0
7176 00:24:56.297083 PH8_DLY = 12
7177 00:24:56.300295 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7178 00:24:56.303386 DQ_AAMCK_DIV = 4
7179 00:24:56.303461 CA_AAMCK_DIV = 4
7180 00:24:56.307124 CA_ADMCK_DIV = 4
7181 00:24:56.310299 DQ_TRACK_CA_EN = 0
7182 00:24:56.313563 CA_PICK = 1600
7183 00:24:56.316929 CA_MCKIO = 1600
7184 00:24:56.319905 MCKIO_SEMI = 0
7185 00:24:56.323557 PLL_FREQ = 3068
7186 00:24:56.326689 DQ_UI_PI_RATIO = 32
7187 00:24:56.326759 CA_UI_PI_RATIO = 0
7188 00:24:56.329993 ===================================
7189 00:24:56.333450 ===================================
7190 00:24:56.336928 memory_type:LPDDR4
7191 00:24:56.340004 GP_NUM : 10
7192 00:24:56.340075 SRAM_EN : 1
7193 00:24:56.343465 MD32_EN : 0
7194 00:24:56.346645 ===================================
7195 00:24:56.349737 [ANA_INIT] >>>>>>>>>>>>>>
7196 00:24:56.353265 <<<<<< [CONFIGURE PHASE]: ANA_TX
7197 00:24:56.356517 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7198 00:24:56.360040 ===================================
7199 00:24:56.360113 data_rate = 3200,PCW = 0X7600
7200 00:24:56.363405 ===================================
7201 00:24:56.366632 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7202 00:24:56.373047 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7203 00:24:56.379906 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7204 00:24:56.383453 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7205 00:24:56.386697 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7206 00:24:56.389676 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7207 00:24:56.393325 [ANA_INIT] flow start
7208 00:24:56.393404 [ANA_INIT] PLL >>>>>>>>
7209 00:24:56.396630 [ANA_INIT] PLL <<<<<<<<
7210 00:24:56.400114 [ANA_INIT] MIDPI >>>>>>>>
7211 00:24:56.403488 [ANA_INIT] MIDPI <<<<<<<<
7212 00:24:56.403576 [ANA_INIT] DLL >>>>>>>>
7213 00:24:56.406640 [ANA_INIT] DLL <<<<<<<<
7214 00:24:56.406714 [ANA_INIT] flow end
7215 00:24:56.413054 ============ LP4 DIFF to SE enter ============
7216 00:24:56.416600 ============ LP4 DIFF to SE exit ============
7217 00:24:56.419900 [ANA_INIT] <<<<<<<<<<<<<
7218 00:24:56.423416 [Flow] Enable top DCM control >>>>>
7219 00:24:56.426494 [Flow] Enable top DCM control <<<<<
7220 00:24:56.430044 Enable DLL master slave shuffle
7221 00:24:56.432950 ==============================================================
7222 00:24:56.436651 Gating Mode config
7223 00:24:56.439554 ==============================================================
7224 00:24:56.443209 Config description:
7225 00:24:56.453028 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7226 00:24:56.459556 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7227 00:24:56.463171 SELPH_MODE 0: By rank 1: By Phase
7228 00:24:56.469875 ==============================================================
7229 00:24:56.473291 GAT_TRACK_EN = 1
7230 00:24:56.476611 RX_GATING_MODE = 2
7231 00:24:56.479508 RX_GATING_TRACK_MODE = 2
7232 00:24:56.482944 SELPH_MODE = 1
7233 00:24:56.486586 PICG_EARLY_EN = 1
7234 00:24:56.486673 VALID_LAT_VALUE = 1
7235 00:24:56.493294 ==============================================================
7236 00:24:56.496308 Enter into Gating configuration >>>>
7237 00:24:56.499399 Exit from Gating configuration <<<<
7238 00:24:56.502671 Enter into DVFS_PRE_config >>>>>
7239 00:24:56.512853 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7240 00:24:56.516166 Exit from DVFS_PRE_config <<<<<
7241 00:24:56.519574 Enter into PICG configuration >>>>
7242 00:24:56.522521 Exit from PICG configuration <<<<
7243 00:24:56.525860 [RX_INPUT] configuration >>>>>
7244 00:24:56.529470 [RX_INPUT] configuration <<<<<
7245 00:24:56.532482 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7246 00:24:56.539804 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7247 00:24:56.545862 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7248 00:24:56.552481 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7249 00:24:56.558900 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7250 00:24:56.565654 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7251 00:24:56.569203 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7252 00:24:56.572382 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7253 00:24:56.575902 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7254 00:24:56.582624 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7255 00:24:56.585613 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7256 00:24:56.589166 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7257 00:24:56.592352 ===================================
7258 00:24:56.595409 LPDDR4 DRAM CONFIGURATION
7259 00:24:56.599020 ===================================
7260 00:24:56.599111 EX_ROW_EN[0] = 0x0
7261 00:24:56.602560 EX_ROW_EN[1] = 0x0
7262 00:24:56.602655 LP4Y_EN = 0x0
7263 00:24:56.605701 WORK_FSP = 0x1
7264 00:24:56.605776 WL = 0x5
7265 00:24:56.609029 RL = 0x5
7266 00:24:56.612234 BL = 0x2
7267 00:24:56.612342 RPST = 0x0
7268 00:24:56.615731 RD_PRE = 0x0
7269 00:24:56.615807 WR_PRE = 0x1
7270 00:24:56.619075 WR_PST = 0x1
7271 00:24:56.619142 DBI_WR = 0x0
7272 00:24:56.622444 DBI_RD = 0x0
7273 00:24:56.622530 OTF = 0x1
7274 00:24:56.625757 ===================================
7275 00:24:56.629208 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7276 00:24:56.632688 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7277 00:24:56.638780 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7278 00:24:56.642249 ===================================
7279 00:24:56.645611 LPDDR4 DRAM CONFIGURATION
7280 00:24:56.649042 ===================================
7281 00:24:56.649124 EX_ROW_EN[0] = 0x10
7282 00:24:56.652118 EX_ROW_EN[1] = 0x0
7283 00:24:56.652182 LP4Y_EN = 0x0
7284 00:24:56.655616 WORK_FSP = 0x1
7285 00:24:56.655714 WL = 0x5
7286 00:24:56.658757 RL = 0x5
7287 00:24:56.658825 BL = 0x2
7288 00:24:56.662264 RPST = 0x0
7289 00:24:56.662357 RD_PRE = 0x0
7290 00:24:56.665357 WR_PRE = 0x1
7291 00:24:56.665451 WR_PST = 0x1
7292 00:24:56.668958 DBI_WR = 0x0
7293 00:24:56.672569 DBI_RD = 0x0
7294 00:24:56.672648 OTF = 0x1
7295 00:24:56.675824 ===================================
7296 00:24:56.682380 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7297 00:24:56.682460 ==
7298 00:24:56.685540 Dram Type= 6, Freq= 0, CH_0, rank 0
7299 00:24:56.689009 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7300 00:24:56.689088 ==
7301 00:24:56.692162 [Duty_Offset_Calibration]
7302 00:24:56.692239 B0:2 B1:0 CA:1
7303 00:24:56.692302
7304 00:24:56.695271 [DutyScan_Calibration_Flow] k_type=0
7305 00:24:56.705877
7306 00:24:56.705970 ==CLK 0==
7307 00:24:56.709456 Final CLK duty delay cell = -4
7308 00:24:56.712465 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7309 00:24:56.715825 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7310 00:24:56.719399 [-4] AVG Duty = 4906%(X100)
7311 00:24:56.719514
7312 00:24:56.722730 CH0 CLK Duty spec in!! Max-Min= 187%
7313 00:24:56.725988 [DutyScan_Calibration_Flow] ====Done====
7314 00:24:56.726083
7315 00:24:56.729305 [DutyScan_Calibration_Flow] k_type=1
7316 00:24:56.745438
7317 00:24:56.745525 ==DQS 0 ==
7318 00:24:56.748506 Final DQS duty delay cell = 0
7319 00:24:56.752037 [0] MAX Duty = 5249%(X100), DQS PI = 34
7320 00:24:56.755138 [0] MIN Duty = 4938%(X100), DQS PI = 62
7321 00:24:56.758654 [0] AVG Duty = 5093%(X100)
7322 00:24:56.758731
7323 00:24:56.758791 ==DQS 1 ==
7324 00:24:56.762083 Final DQS duty delay cell = -4
7325 00:24:56.765106 [-4] MAX Duty = 5125%(X100), DQS PI = 30
7326 00:24:56.768264 [-4] MIN Duty = 4844%(X100), DQS PI = 4
7327 00:24:56.771856 [-4] AVG Duty = 4984%(X100)
7328 00:24:56.771930
7329 00:24:56.774910 CH0 DQS 0 Duty spec in!! Max-Min= 311%
7330 00:24:56.774997
7331 00:24:56.778239 CH0 DQS 1 Duty spec in!! Max-Min= 281%
7332 00:24:56.781903 [DutyScan_Calibration_Flow] ====Done====
7333 00:24:56.781970
7334 00:24:56.784899 [DutyScan_Calibration_Flow] k_type=3
7335 00:24:56.802651
7336 00:24:56.802722 ==DQM 0 ==
7337 00:24:56.806001 Final DQM duty delay cell = 0
7338 00:24:56.809433 [0] MAX Duty = 5093%(X100), DQS PI = 24
7339 00:24:56.812954 [0] MIN Duty = 4813%(X100), DQS PI = 2
7340 00:24:56.813056 [0] AVG Duty = 4953%(X100)
7341 00:24:56.815949
7342 00:24:56.816039 ==DQM 1 ==
7343 00:24:56.819427 Final DQM duty delay cell = 0
7344 00:24:56.822693 [0] MAX Duty = 5249%(X100), DQS PI = 44
7345 00:24:56.826066 [0] MIN Duty = 5000%(X100), DQS PI = 18
7346 00:24:56.826158 [0] AVG Duty = 5124%(X100)
7347 00:24:56.829323
7348 00:24:56.832744 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7349 00:24:56.832849
7350 00:24:56.836111 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7351 00:24:56.839581 [DutyScan_Calibration_Flow] ====Done====
7352 00:24:56.839657
7353 00:24:56.842957 [DutyScan_Calibration_Flow] k_type=2
7354 00:24:56.860171
7355 00:24:56.860241 ==DQ 0 ==
7356 00:24:56.863486 Final DQ duty delay cell = 0
7357 00:24:56.866869 [0] MAX Duty = 5124%(X100), DQS PI = 34
7358 00:24:56.869998 [0] MIN Duty = 5000%(X100), DQS PI = 0
7359 00:24:56.870067 [0] AVG Duty = 5062%(X100)
7360 00:24:56.870124
7361 00:24:56.873170 ==DQ 1 ==
7362 00:24:56.876592 Final DQ duty delay cell = 0
7363 00:24:56.879630 [0] MAX Duty = 4969%(X100), DQS PI = 52
7364 00:24:56.883272 [0] MIN Duty = 4875%(X100), DQS PI = 0
7365 00:24:56.883338 [0] AVG Duty = 4922%(X100)
7366 00:24:56.883400
7367 00:24:56.886683 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7368 00:24:56.886760
7369 00:24:56.889929 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7370 00:24:56.896607 [DutyScan_Calibration_Flow] ====Done====
7371 00:24:56.896691 ==
7372 00:24:56.899844 Dram Type= 6, Freq= 0, CH_1, rank 0
7373 00:24:56.903453 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7374 00:24:56.903523 ==
7375 00:24:56.906493 [Duty_Offset_Calibration]
7376 00:24:56.906559 B0:0 B1:-1 CA:2
7377 00:24:56.906620
7378 00:24:56.909970 [DutyScan_Calibration_Flow] k_type=0
7379 00:24:56.919839
7380 00:24:56.919906 ==CLK 0==
7381 00:24:56.923020 Final CLK duty delay cell = 0
7382 00:24:56.926220 [0] MAX Duty = 5156%(X100), DQS PI = 12
7383 00:24:56.929813 [0] MIN Duty = 4906%(X100), DQS PI = 46
7384 00:24:56.933275 [0] AVG Duty = 5031%(X100)
7385 00:24:56.933343
7386 00:24:56.936423 CH1 CLK Duty spec in!! Max-Min= 250%
7387 00:24:56.939744 [DutyScan_Calibration_Flow] ====Done====
7388 00:24:56.939838
7389 00:24:56.942679 [DutyScan_Calibration_Flow] k_type=1
7390 00:24:56.959650
7391 00:24:56.959746 ==DQS 0 ==
7392 00:24:56.963044 Final DQS duty delay cell = 0
7393 00:24:56.966460 [0] MAX Duty = 5093%(X100), DQS PI = 24
7394 00:24:56.969930 [0] MIN Duty = 4969%(X100), DQS PI = 2
7395 00:24:56.970024 [0] AVG Duty = 5031%(X100)
7396 00:24:56.973339
7397 00:24:56.973433 ==DQS 1 ==
7398 00:24:56.976405 Final DQS duty delay cell = 0
7399 00:24:56.979871 [0] MAX Duty = 5187%(X100), DQS PI = 2
7400 00:24:56.982970 [0] MIN Duty = 4844%(X100), DQS PI = 32
7401 00:24:56.983048 [0] AVG Duty = 5015%(X100)
7402 00:24:56.986523
7403 00:24:56.989570 CH1 DQS 0 Duty spec in!! Max-Min= 124%
7404 00:24:56.989647
7405 00:24:56.993262 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7406 00:24:56.996222 [DutyScan_Calibration_Flow] ====Done====
7407 00:24:56.996296
7408 00:24:56.999873 [DutyScan_Calibration_Flow] k_type=3
7409 00:24:57.017348
7410 00:24:57.017426 ==DQM 0 ==
7411 00:24:57.020720 Final DQM duty delay cell = 4
7412 00:24:57.023645 [4] MAX Duty = 5125%(X100), DQS PI = 8
7413 00:24:57.027263 [4] MIN Duty = 4969%(X100), DQS PI = 32
7414 00:24:57.027346 [4] AVG Duty = 5047%(X100)
7415 00:24:57.030472
7416 00:24:57.030545 ==DQM 1 ==
7417 00:24:57.033899 Final DQM duty delay cell = 0
7418 00:24:57.037311 [0] MAX Duty = 5281%(X100), DQS PI = 58
7419 00:24:57.040469 [0] MIN Duty = 4876%(X100), DQS PI = 34
7420 00:24:57.043847 [0] AVG Duty = 5078%(X100)
7421 00:24:57.043917
7422 00:24:57.047341 CH1 DQM 0 Duty spec in!! Max-Min= 156%
7423 00:24:57.047410
7424 00:24:57.050661 CH1 DQM 1 Duty spec in!! Max-Min= 405%
7425 00:24:57.053860 [DutyScan_Calibration_Flow] ====Done====
7426 00:24:57.053933
7427 00:24:57.057053 [DutyScan_Calibration_Flow] k_type=2
7428 00:24:57.074048
7429 00:24:57.074125 ==DQ 0 ==
7430 00:24:57.077773 Final DQ duty delay cell = 0
7431 00:24:57.080917 [0] MAX Duty = 5062%(X100), DQS PI = 18
7432 00:24:57.084533 [0] MIN Duty = 4969%(X100), DQS PI = 0
7433 00:24:57.084626 [0] AVG Duty = 5015%(X100)
7434 00:24:57.084736
7435 00:24:57.087592 ==DQ 1 ==
7436 00:24:57.091037 Final DQ duty delay cell = 0
7437 00:24:57.094211 [0] MAX Duty = 5062%(X100), DQS PI = 0
7438 00:24:57.097973 [0] MIN Duty = 4813%(X100), DQS PI = 34
7439 00:24:57.098039 [0] AVG Duty = 4937%(X100)
7440 00:24:57.098093
7441 00:24:57.100872 CH1 DQ 0 Duty spec in!! Max-Min= 93%
7442 00:24:57.100937
7443 00:24:57.104494 CH1 DQ 1 Duty spec in!! Max-Min= 249%
7444 00:24:57.110934 [DutyScan_Calibration_Flow] ====Done====
7445 00:24:57.114613 nWR fixed to 30
7446 00:24:57.114686 [ModeRegInit_LP4] CH0 RK0
7447 00:24:57.117511 [ModeRegInit_LP4] CH0 RK1
7448 00:24:57.121068 [ModeRegInit_LP4] CH1 RK0
7449 00:24:57.121133 [ModeRegInit_LP4] CH1 RK1
7450 00:24:57.124225 match AC timing 5
7451 00:24:57.127176 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7452 00:24:57.130583 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7453 00:24:57.137415 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7454 00:24:57.140529 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7455 00:24:57.147255 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7456 00:24:57.147327 [MiockJmeterHQA]
7457 00:24:57.147391
7458 00:24:57.150633 [DramcMiockJmeter] u1RxGatingPI = 0
7459 00:24:57.153834 0 : 4254, 4029
7460 00:24:57.153907 4 : 4368, 4139
7461 00:24:57.153965 8 : 4252, 4027
7462 00:24:57.157234 12 : 4253, 4026
7463 00:24:57.157315 16 : 4252, 4027
7464 00:24:57.160582 20 : 4253, 4026
7465 00:24:57.160650 24 : 4255, 4029
7466 00:24:57.163781 28 : 4252, 4027
7467 00:24:57.163855 32 : 4253, 4026
7468 00:24:57.163912 36 : 4366, 4139
7469 00:24:57.167317 40 : 4253, 4027
7470 00:24:57.167387 44 : 4255, 4029
7471 00:24:57.170303 48 : 4252, 4027
7472 00:24:57.170378 52 : 4361, 4137
7473 00:24:57.173890 56 : 4250, 4026
7474 00:24:57.173967 60 : 4360, 4138
7475 00:24:57.176959 64 : 4250, 4027
7476 00:24:57.177034 68 : 4250, 4027
7477 00:24:57.177098 72 : 4250, 4027
7478 00:24:57.180277 76 : 4252, 4029
7479 00:24:57.180357 80 : 4361, 4137
7480 00:24:57.183301 84 : 4252, 4027
7481 00:24:57.183376 88 : 4360, 3592
7482 00:24:57.186766 92 : 4250, 0
7483 00:24:57.186839 96 : 4361, 0
7484 00:24:57.186899 100 : 4250, 0
7485 00:24:57.189962 104 : 4253, 0
7486 00:24:57.190033 108 : 4250, 0
7487 00:24:57.193474 112 : 4250, 0
7488 00:24:57.193550 116 : 4253, 0
7489 00:24:57.193607 120 : 4361, 0
7490 00:24:57.196994 124 : 4250, 0
7491 00:24:57.197061 128 : 4250, 0
7492 00:24:57.200124 132 : 4250, 0
7493 00:24:57.200202 136 : 4361, 0
7494 00:24:57.200261 140 : 4360, 0
7495 00:24:57.203598 144 : 4250, 0
7496 00:24:57.203673 148 : 4250, 0
7497 00:24:57.203728 152 : 4363, 0
7498 00:24:57.206713 156 : 4250, 0
7499 00:24:57.206780 160 : 4250, 0
7500 00:24:57.210132 164 : 4250, 0
7501 00:24:57.210199 168 : 4250, 0
7502 00:24:57.210255 172 : 4250, 0
7503 00:24:57.213817 176 : 4250, 0
7504 00:24:57.213889 180 : 4252, 0
7505 00:24:57.216866 184 : 4250, 0
7506 00:24:57.216941 188 : 4360, 0
7507 00:24:57.216998 192 : 4361, 0
7508 00:24:57.219951 196 : 4250, 0
7509 00:24:57.220019 200 : 4250, 3
7510 00:24:57.223553 204 : 4250, 2578
7511 00:24:57.223614 208 : 4360, 4137
7512 00:24:57.227076 212 : 4361, 4137
7513 00:24:57.227146 216 : 4248, 4025
7514 00:24:57.227208 220 : 4363, 4139
7515 00:24:57.230164 224 : 4361, 4137
7516 00:24:57.230231 228 : 4250, 4027
7517 00:24:57.233655 232 : 4250, 4027
7518 00:24:57.233721 236 : 4253, 4029
7519 00:24:57.236890 240 : 4250, 4026
7520 00:24:57.236968 244 : 4250, 4026
7521 00:24:57.240097 248 : 4250, 4027
7522 00:24:57.240168 252 : 4253, 4029
7523 00:24:57.243593 256 : 4250, 4027
7524 00:24:57.243660 260 : 4361, 4137
7525 00:24:57.246887 264 : 4361, 4137
7526 00:24:57.246965 268 : 4250, 4026
7527 00:24:57.249856 272 : 4363, 4139
7528 00:24:57.249931 276 : 4361, 4137
7529 00:24:57.249989 280 : 4250, 4026
7530 00:24:57.253117 284 : 4250, 4027
7531 00:24:57.253183 288 : 4253, 4029
7532 00:24:57.256311 292 : 4250, 4027
7533 00:24:57.256383 296 : 4250, 4027
7534 00:24:57.259969 300 : 4250, 4027
7535 00:24:57.260048 304 : 4253, 4029
7536 00:24:57.263396 308 : 4250, 4027
7537 00:24:57.263469 312 : 4360, 3965
7538 00:24:57.266751 316 : 4361, 1969
7539 00:24:57.266830
7540 00:24:57.266888 MIOCK jitter meter ch=0
7541 00:24:57.266942
7542 00:24:57.269946 1T = (316-92) = 224 dly cells
7543 00:24:57.276308 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7544 00:24:57.276383 ==
7545 00:24:57.279849 Dram Type= 6, Freq= 0, CH_0, rank 0
7546 00:24:57.282866 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7547 00:24:57.282951 ==
7548 00:24:57.289678 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7549 00:24:57.293010 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7550 00:24:57.296548 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7551 00:24:57.303182 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7552 00:24:57.312876 [CA 0] Center 43 (13~73) winsize 61
7553 00:24:57.316037 [CA 1] Center 43 (13~73) winsize 61
7554 00:24:57.319147 [CA 2] Center 38 (8~68) winsize 61
7555 00:24:57.322806 [CA 3] Center 37 (8~67) winsize 60
7556 00:24:57.326390 [CA 4] Center 36 (6~66) winsize 61
7557 00:24:57.329920 [CA 5] Center 35 (5~65) winsize 61
7558 00:24:57.330009
7559 00:24:57.332959 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7560 00:24:57.333026
7561 00:24:57.335934 [CATrainingPosCal] consider 1 rank data
7562 00:24:57.339316 u2DelayCellTimex100 = 290/100 ps
7563 00:24:57.342810 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7564 00:24:57.349267 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7565 00:24:57.352656 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7566 00:24:57.355747 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7567 00:24:57.359322 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7568 00:24:57.362348 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7569 00:24:57.362415
7570 00:24:57.365925 CA PerBit enable=1, Macro0, CA PI delay=35
7571 00:24:57.366004
7572 00:24:57.368962 [CBTSetCACLKResult] CA Dly = 35
7573 00:24:57.372425 CS Dly: 10 (0~41)
7574 00:24:57.375786 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7575 00:24:57.379240 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7576 00:24:57.379318 ==
7577 00:24:57.382765 Dram Type= 6, Freq= 0, CH_0, rank 1
7578 00:24:57.385976 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7579 00:24:57.389205 ==
7580 00:24:57.392253 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7581 00:24:57.395642 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7582 00:24:57.402223 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7583 00:24:57.408818 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7584 00:24:57.416365 [CA 0] Center 43 (13~73) winsize 61
7585 00:24:57.419443 [CA 1] Center 43 (13~73) winsize 61
7586 00:24:57.422997 [CA 2] Center 37 (8~67) winsize 60
7587 00:24:57.426034 [CA 3] Center 38 (8~68) winsize 61
7588 00:24:57.429527 [CA 4] Center 36 (6~66) winsize 61
7589 00:24:57.432665 [CA 5] Center 36 (6~66) winsize 61
7590 00:24:57.432792
7591 00:24:57.436317 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7592 00:24:57.436423
7593 00:24:57.439885 [CATrainingPosCal] consider 2 rank data
7594 00:24:57.442862 u2DelayCellTimex100 = 290/100 ps
7595 00:24:57.446265 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7596 00:24:57.452847 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7597 00:24:57.456288 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7598 00:24:57.459653 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7599 00:24:57.462649 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7600 00:24:57.466286 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7601 00:24:57.466365
7602 00:24:57.469681 CA PerBit enable=1, Macro0, CA PI delay=35
7603 00:24:57.469774
7604 00:24:57.473014 [CBTSetCACLKResult] CA Dly = 35
7605 00:24:57.475994 CS Dly: 11 (0~43)
7606 00:24:57.479772 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7607 00:24:57.482765 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7608 00:24:57.482884
7609 00:24:57.486301 ----->DramcWriteLeveling(PI) begin...
7610 00:24:57.486378 ==
7611 00:24:57.489563 Dram Type= 6, Freq= 0, CH_0, rank 0
7612 00:24:57.492688 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7613 00:24:57.495948 ==
7614 00:24:57.496025 Write leveling (Byte 0): 34 => 34
7615 00:24:57.499241 Write leveling (Byte 1): 30 => 30
7616 00:24:57.502803 DramcWriteLeveling(PI) end<-----
7617 00:24:57.502879
7618 00:24:57.502937 ==
7619 00:24:57.505993 Dram Type= 6, Freq= 0, CH_0, rank 0
7620 00:24:57.512625 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7621 00:24:57.512733 ==
7622 00:24:57.512797 [Gating] SW mode calibration
7623 00:24:57.522899 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7624 00:24:57.525899 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7625 00:24:57.532403 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7626 00:24:57.536078 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7627 00:24:57.539175 1 4 8 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (1 1)
7628 00:24:57.542842 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7629 00:24:57.549314 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7630 00:24:57.552782 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7631 00:24:57.555786 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7632 00:24:57.562837 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7633 00:24:57.565896 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7634 00:24:57.569167 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7635 00:24:57.575790 1 5 8 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
7636 00:24:57.579316 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7637 00:24:57.582559 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7638 00:24:57.589294 1 5 20 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
7639 00:24:57.592675 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7640 00:24:57.596119 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7641 00:24:57.602574 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7642 00:24:57.605799 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7643 00:24:57.609002 1 6 8 | B1->B0 | 2323 3f3f | 0 0 | (0 0) (0 0)
7644 00:24:57.615940 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7645 00:24:57.619410 1 6 16 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
7646 00:24:57.622619 1 6 20 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
7647 00:24:57.629383 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7648 00:24:57.632457 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7649 00:24:57.635538 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7650 00:24:57.642234 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7651 00:24:57.645923 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7652 00:24:57.648949 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7653 00:24:57.655769 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7654 00:24:57.658875 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7655 00:24:57.662276 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7656 00:24:57.665940 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7657 00:24:57.672062 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7658 00:24:57.675790 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7659 00:24:57.679205 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7660 00:24:57.685832 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7661 00:24:57.689061 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7662 00:24:57.692540 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7663 00:24:57.699043 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7664 00:24:57.702299 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7665 00:24:57.705787 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7666 00:24:57.712373 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7667 00:24:57.715695 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7668 00:24:57.719044 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7669 00:24:57.725740 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7670 00:24:57.725818 Total UI for P1: 0, mck2ui 16
7671 00:24:57.732344 best dqsien dly found for B0: ( 1, 9, 10)
7672 00:24:57.735853 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7673 00:24:57.738795 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7674 00:24:57.742285 Total UI for P1: 0, mck2ui 16
7675 00:24:57.745478 best dqsien dly found for B1: ( 1, 9, 20)
7676 00:24:57.748438 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7677 00:24:57.752085 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7678 00:24:57.752163
7679 00:24:57.758705 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7680 00:24:57.761722 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7681 00:24:57.765267 [Gating] SW calibration Done
7682 00:24:57.765362 ==
7683 00:24:57.768814 Dram Type= 6, Freq= 0, CH_0, rank 0
7684 00:24:57.771756 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7685 00:24:57.771834 ==
7686 00:24:57.771894 RX Vref Scan: 0
7687 00:24:57.771950
7688 00:24:57.775385 RX Vref 0 -> 0, step: 1
7689 00:24:57.775485
7690 00:24:57.778427 RX Delay 0 -> 252, step: 8
7691 00:24:57.781499 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
7692 00:24:57.785033 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7693 00:24:57.788270 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7694 00:24:57.794864 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7695 00:24:57.798503 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7696 00:24:57.801586 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
7697 00:24:57.804982 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7698 00:24:57.808237 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7699 00:24:57.814666 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7700 00:24:57.818053 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7701 00:24:57.821248 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7702 00:24:57.824787 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
7703 00:24:57.831360 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7704 00:24:57.834622 iDelay=200, Bit 13, Center 127 (80 ~ 175) 96
7705 00:24:57.837988 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7706 00:24:57.841625 iDelay=200, Bit 15, Center 131 (80 ~ 183) 104
7707 00:24:57.841703 ==
7708 00:24:57.844519 Dram Type= 6, Freq= 0, CH_0, rank 0
7709 00:24:57.848075 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7710 00:24:57.851652 ==
7711 00:24:57.851742 DQS Delay:
7712 00:24:57.851831 DQS0 = 0, DQS1 = 0
7713 00:24:57.854676 DQM Delay:
7714 00:24:57.854754 DQM0 = 138, DQM1 = 126
7715 00:24:57.857868 DQ Delay:
7716 00:24:57.861244 DQ0 =139, DQ1 =139, DQ2 =135, DQ3 =135
7717 00:24:57.864691 DQ4 =139, DQ5 =127, DQ6 =147, DQ7 =147
7718 00:24:57.867798 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =123
7719 00:24:57.871383 DQ12 =131, DQ13 =127, DQ14 =139, DQ15 =131
7720 00:24:57.871461
7721 00:24:57.871523
7722 00:24:57.871578 ==
7723 00:24:57.874839 Dram Type= 6, Freq= 0, CH_0, rank 0
7724 00:24:57.878077 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7725 00:24:57.878157 ==
7726 00:24:57.878217
7727 00:24:57.881162
7728 00:24:57.881240 TX Vref Scan disable
7729 00:24:57.884632 == TX Byte 0 ==
7730 00:24:57.887819 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7731 00:24:57.891528 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7732 00:24:57.894593 == TX Byte 1 ==
7733 00:24:57.897954 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7734 00:24:57.901094 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7735 00:24:57.901183 ==
7736 00:24:57.904445 Dram Type= 6, Freq= 0, CH_0, rank 0
7737 00:24:57.911046 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7738 00:24:57.911141 ==
7739 00:24:57.924046
7740 00:24:57.927033 TX Vref early break, caculate TX vref
7741 00:24:57.930639 TX Vref=16, minBit 5, minWin=22, winSum=377
7742 00:24:57.933825 TX Vref=18, minBit 4, minWin=23, winSum=387
7743 00:24:57.937134 TX Vref=20, minBit 12, minWin=23, winSum=398
7744 00:24:57.940474 TX Vref=22, minBit 4, minWin=24, winSum=409
7745 00:24:57.943853 TX Vref=24, minBit 12, minWin=24, winSum=415
7746 00:24:57.950262 TX Vref=26, minBit 12, minWin=25, winSum=425
7747 00:24:57.953894 TX Vref=28, minBit 2, minWin=25, winSum=427
7748 00:24:57.957307 TX Vref=30, minBit 0, minWin=26, winSum=427
7749 00:24:57.960397 TX Vref=32, minBit 1, minWin=24, winSum=411
7750 00:24:57.963763 TX Vref=34, minBit 1, minWin=24, winSum=406
7751 00:24:57.967193 TX Vref=36, minBit 0, minWin=24, winSum=394
7752 00:24:57.973519 [TxChooseVref] Worse bit 0, Min win 26, Win sum 427, Final Vref 30
7753 00:24:57.973595
7754 00:24:57.977063 Final TX Range 0 Vref 30
7755 00:24:57.977157
7756 00:24:57.977240 ==
7757 00:24:57.980552 Dram Type= 6, Freq= 0, CH_0, rank 0
7758 00:24:57.983608 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7759 00:24:57.983703 ==
7760 00:24:57.986659
7761 00:24:57.986760
7762 00:24:57.986840 TX Vref Scan disable
7763 00:24:57.993203 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7764 00:24:57.993280 == TX Byte 0 ==
7765 00:24:57.996741 u2DelayCellOfst[0]=13 cells (4 PI)
7766 00:24:58.000243 u2DelayCellOfst[1]=20 cells (6 PI)
7767 00:24:58.003263 u2DelayCellOfst[2]=13 cells (4 PI)
7768 00:24:58.006825 u2DelayCellOfst[3]=13 cells (4 PI)
7769 00:24:58.009918 u2DelayCellOfst[4]=10 cells (3 PI)
7770 00:24:58.013496 u2DelayCellOfst[5]=0 cells (0 PI)
7771 00:24:58.016532 u2DelayCellOfst[6]=16 cells (5 PI)
7772 00:24:58.020149 u2DelayCellOfst[7]=16 cells (5 PI)
7773 00:24:58.023222 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7774 00:24:58.026622 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7775 00:24:58.030060 == TX Byte 1 ==
7776 00:24:58.033436 u2DelayCellOfst[8]=0 cells (0 PI)
7777 00:24:58.036784 u2DelayCellOfst[9]=0 cells (0 PI)
7778 00:24:58.040265 u2DelayCellOfst[10]=6 cells (2 PI)
7779 00:24:58.040342 u2DelayCellOfst[11]=3 cells (1 PI)
7780 00:24:58.043223 u2DelayCellOfst[12]=10 cells (3 PI)
7781 00:24:58.046999 u2DelayCellOfst[13]=10 cells (3 PI)
7782 00:24:58.049933 u2DelayCellOfst[14]=13 cells (4 PI)
7783 00:24:58.053456 u2DelayCellOfst[15]=10 cells (3 PI)
7784 00:24:58.060209 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7785 00:24:58.063177 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7786 00:24:58.063270 DramC Write-DBI on
7787 00:24:58.063337 ==
7788 00:24:58.066802 Dram Type= 6, Freq= 0, CH_0, rank 0
7789 00:24:58.073245 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7790 00:24:58.073315 ==
7791 00:24:58.073377
7792 00:24:58.073431
7793 00:24:58.073483 TX Vref Scan disable
7794 00:24:58.077487 == TX Byte 0 ==
7795 00:24:58.080956 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
7796 00:24:58.083862 == TX Byte 1 ==
7797 00:24:58.087360 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7798 00:24:58.090621 DramC Write-DBI off
7799 00:24:58.090686
7800 00:24:58.090742 [DATLAT]
7801 00:24:58.090823 Freq=1600, CH0 RK0
7802 00:24:58.090901
7803 00:24:58.094258 DATLAT Default: 0xf
7804 00:24:58.094322 0, 0xFFFF, sum = 0
7805 00:24:58.097696 1, 0xFFFF, sum = 0
7806 00:24:58.097759 2, 0xFFFF, sum = 0
7807 00:24:58.100666 3, 0xFFFF, sum = 0
7808 00:24:58.104317 4, 0xFFFF, sum = 0
7809 00:24:58.104381 5, 0xFFFF, sum = 0
7810 00:24:58.107330 6, 0xFFFF, sum = 0
7811 00:24:58.107419 7, 0xFFFF, sum = 0
7812 00:24:58.110950 8, 0xFFFF, sum = 0
7813 00:24:58.111043 9, 0xFFFF, sum = 0
7814 00:24:58.114488 10, 0xFFFF, sum = 0
7815 00:24:58.114598 11, 0xFFFF, sum = 0
7816 00:24:58.117663 12, 0xFFFF, sum = 0
7817 00:24:58.117754 13, 0xFFFF, sum = 0
7818 00:24:58.120663 14, 0x0, sum = 1
7819 00:24:58.120761 15, 0x0, sum = 2
7820 00:24:58.124377 16, 0x0, sum = 3
7821 00:24:58.124470 17, 0x0, sum = 4
7822 00:24:58.127831 best_step = 15
7823 00:24:58.127920
7824 00:24:58.128008 ==
7825 00:24:58.130799 Dram Type= 6, Freq= 0, CH_0, rank 0
7826 00:24:58.134173 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7827 00:24:58.134295 ==
7828 00:24:58.134381 RX Vref Scan: 1
7829 00:24:58.134457
7830 00:24:58.137571 Set Vref Range= 24 -> 127
7831 00:24:58.137663
7832 00:24:58.141053 RX Vref 24 -> 127, step: 1
7833 00:24:58.141123
7834 00:24:58.144447 RX Delay 19 -> 252, step: 4
7835 00:24:58.144518
7836 00:24:58.147867 Set Vref, RX VrefLevel [Byte0]: 24
7837 00:24:58.151090 [Byte1]: 24
7838 00:24:58.151157
7839 00:24:58.154284 Set Vref, RX VrefLevel [Byte0]: 25
7840 00:24:58.157681 [Byte1]: 25
7841 00:24:58.157761
7842 00:24:58.160855 Set Vref, RX VrefLevel [Byte0]: 26
7843 00:24:58.164364 [Byte1]: 26
7844 00:24:58.167609
7845 00:24:58.167679 Set Vref, RX VrefLevel [Byte0]: 27
7846 00:24:58.171196 [Byte1]: 27
7847 00:24:58.175405
7848 00:24:58.175472 Set Vref, RX VrefLevel [Byte0]: 28
7849 00:24:58.178546 [Byte1]: 28
7850 00:24:58.182961
7851 00:24:58.183038 Set Vref, RX VrefLevel [Byte0]: 29
7852 00:24:58.186251 [Byte1]: 29
7853 00:24:58.190580
7854 00:24:58.190657 Set Vref, RX VrefLevel [Byte0]: 30
7855 00:24:58.193977 [Byte1]: 30
7856 00:24:58.198226
7857 00:24:58.198303 Set Vref, RX VrefLevel [Byte0]: 31
7858 00:24:58.201759 [Byte1]: 31
7859 00:24:58.205806
7860 00:24:58.205882 Set Vref, RX VrefLevel [Byte0]: 32
7861 00:24:58.208897 [Byte1]: 32
7862 00:24:58.213379
7863 00:24:58.213456 Set Vref, RX VrefLevel [Byte0]: 33
7864 00:24:58.216545 [Byte1]: 33
7865 00:24:58.220638
7866 00:24:58.220729 Set Vref, RX VrefLevel [Byte0]: 34
7867 00:24:58.224323 [Byte1]: 34
7868 00:24:58.228267
7869 00:24:58.228335 Set Vref, RX VrefLevel [Byte0]: 35
7870 00:24:58.231495 [Byte1]: 35
7871 00:24:58.235954
7872 00:24:58.236023 Set Vref, RX VrefLevel [Byte0]: 36
7873 00:24:58.239390 [Byte1]: 36
7874 00:24:58.243500
7875 00:24:58.243573 Set Vref, RX VrefLevel [Byte0]: 37
7876 00:24:58.246866 [Byte1]: 37
7877 00:24:58.250989
7878 00:24:58.251058 Set Vref, RX VrefLevel [Byte0]: 38
7879 00:24:58.254409 [Byte1]: 38
7880 00:24:58.258873
7881 00:24:58.258940 Set Vref, RX VrefLevel [Byte0]: 39
7882 00:24:58.262079 [Byte1]: 39
7883 00:24:58.265997
7884 00:24:58.266066 Set Vref, RX VrefLevel [Byte0]: 40
7885 00:24:58.269596 [Byte1]: 40
7886 00:24:58.273640
7887 00:24:58.276931 Set Vref, RX VrefLevel [Byte0]: 41
7888 00:24:58.276999 [Byte1]: 41
7889 00:24:58.281181
7890 00:24:58.281249 Set Vref, RX VrefLevel [Byte0]: 42
7891 00:24:58.284880 [Byte1]: 42
7892 00:24:58.289152
7893 00:24:58.289219 Set Vref, RX VrefLevel [Byte0]: 43
7894 00:24:58.292261 [Byte1]: 43
7895 00:24:58.296712
7896 00:24:58.296831 Set Vref, RX VrefLevel [Byte0]: 44
7897 00:24:58.299725 [Byte1]: 44
7898 00:24:58.304089
7899 00:24:58.304157 Set Vref, RX VrefLevel [Byte0]: 45
7900 00:24:58.307224 [Byte1]: 45
7901 00:24:58.311778
7902 00:24:58.311845 Set Vref, RX VrefLevel [Byte0]: 46
7903 00:24:58.314774 [Byte1]: 46
7904 00:24:58.319593
7905 00:24:58.319660 Set Vref, RX VrefLevel [Byte0]: 47
7906 00:24:58.322517 [Byte1]: 47
7907 00:24:58.326660
7908 00:24:58.326728 Set Vref, RX VrefLevel [Byte0]: 48
7909 00:24:58.330083 [Byte1]: 48
7910 00:24:58.334236
7911 00:24:58.334303 Set Vref, RX VrefLevel [Byte0]: 49
7912 00:24:58.337850 [Byte1]: 49
7913 00:24:58.341735
7914 00:24:58.341832 Set Vref, RX VrefLevel [Byte0]: 50
7915 00:24:58.345195 [Byte1]: 50
7916 00:24:58.349424
7917 00:24:58.349517 Set Vref, RX VrefLevel [Byte0]: 51
7918 00:24:58.352531 [Byte1]: 51
7919 00:24:58.356875
7920 00:24:58.356954 Set Vref, RX VrefLevel [Byte0]: 52
7921 00:24:58.360470 [Byte1]: 52
7922 00:24:58.364819
7923 00:24:58.364891 Set Vref, RX VrefLevel [Byte0]: 53
7924 00:24:58.367601 [Byte1]: 53
7925 00:24:58.372285
7926 00:24:58.372357 Set Vref, RX VrefLevel [Byte0]: 54
7927 00:24:58.375319 [Byte1]: 54
7928 00:24:58.380033
7929 00:24:58.380102 Set Vref, RX VrefLevel [Byte0]: 55
7930 00:24:58.382985 [Byte1]: 55
7931 00:24:58.387565
7932 00:24:58.387635 Set Vref, RX VrefLevel [Byte0]: 56
7933 00:24:58.390771 [Byte1]: 56
7934 00:24:58.394786
7935 00:24:58.394857 Set Vref, RX VrefLevel [Byte0]: 57
7936 00:24:58.398204 [Byte1]: 57
7937 00:24:58.402361
7938 00:24:58.402432 Set Vref, RX VrefLevel [Byte0]: 58
7939 00:24:58.405513 [Byte1]: 58
7940 00:24:58.410054
7941 00:24:58.410127 Set Vref, RX VrefLevel [Byte0]: 59
7942 00:24:58.413562 [Byte1]: 59
7943 00:24:58.417735
7944 00:24:58.417804 Set Vref, RX VrefLevel [Byte0]: 60
7945 00:24:58.420813 [Byte1]: 60
7946 00:24:58.425397
7947 00:24:58.425466 Set Vref, RX VrefLevel [Byte0]: 61
7948 00:24:58.428673 [Byte1]: 61
7949 00:24:58.432688
7950 00:24:58.432804 Set Vref, RX VrefLevel [Byte0]: 62
7951 00:24:58.435854 [Byte1]: 62
7952 00:24:58.440331
7953 00:24:58.440411 Set Vref, RX VrefLevel [Byte0]: 63
7954 00:24:58.443948 [Byte1]: 63
7955 00:24:58.447892
7956 00:24:58.447961 Set Vref, RX VrefLevel [Byte0]: 64
7957 00:24:58.451313 [Byte1]: 64
7958 00:24:58.455445
7959 00:24:58.455551 Set Vref, RX VrefLevel [Byte0]: 65
7960 00:24:58.458571 [Byte1]: 65
7961 00:24:58.462827
7962 00:24:58.462941 Set Vref, RX VrefLevel [Byte0]: 66
7963 00:24:58.466333 [Byte1]: 66
7964 00:24:58.470411
7965 00:24:58.470506 Set Vref, RX VrefLevel [Byte0]: 67
7966 00:24:58.473944 [Byte1]: 67
7967 00:24:58.478174
7968 00:24:58.478276 Set Vref, RX VrefLevel [Byte0]: 68
7969 00:24:58.481809 [Byte1]: 68
7970 00:24:58.485745
7971 00:24:58.485851 Set Vref, RX VrefLevel [Byte0]: 69
7972 00:24:58.489368 [Byte1]: 69
7973 00:24:58.493091
7974 00:24:58.493166 Set Vref, RX VrefLevel [Byte0]: 70
7975 00:24:58.496618 [Byte1]: 70
7976 00:24:58.500625
7977 00:24:58.500746 Set Vref, RX VrefLevel [Byte0]: 71
7978 00:24:58.504256 [Byte1]: 71
7979 00:24:58.508587
7980 00:24:58.508701 Set Vref, RX VrefLevel [Byte0]: 72
7981 00:24:58.511944 [Byte1]: 72
7982 00:24:58.516197
7983 00:24:58.516280 Set Vref, RX VrefLevel [Byte0]: 73
7984 00:24:58.519705 [Byte1]: 73
7985 00:24:58.523858
7986 00:24:58.523933 Set Vref, RX VrefLevel [Byte0]: 74
7987 00:24:58.526950 [Byte1]: 74
7988 00:24:58.531631
7989 00:24:58.531704 Set Vref, RX VrefLevel [Byte0]: 75
7990 00:24:58.534632 [Byte1]: 75
7991 00:24:58.538792
7992 00:24:58.538868 Set Vref, RX VrefLevel [Byte0]: 76
7993 00:24:58.542260 [Byte1]: 76
7994 00:24:58.546394
7995 00:24:58.546475 Set Vref, RX VrefLevel [Byte0]: 77
7996 00:24:58.550041 [Byte1]: 77
7997 00:24:58.554085
7998 00:24:58.554164 Set Vref, RX VrefLevel [Byte0]: 78
7999 00:24:58.557377 [Byte1]: 78
8000 00:24:58.561645
8001 00:24:58.561725 Set Vref, RX VrefLevel [Byte0]: 79
8002 00:24:58.564570 [Byte1]: 79
8003 00:24:58.569256
8004 00:24:58.569336 Final RX Vref Byte 0 = 58 to rank0
8005 00:24:58.572667 Final RX Vref Byte 1 = 63 to rank0
8006 00:24:58.575885 Final RX Vref Byte 0 = 58 to rank1
8007 00:24:58.578935 Final RX Vref Byte 1 = 63 to rank1==
8008 00:24:58.582427 Dram Type= 6, Freq= 0, CH_0, rank 0
8009 00:24:58.588986 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8010 00:24:58.589066 ==
8011 00:24:58.589146 DQS Delay:
8012 00:24:58.592572 DQS0 = 0, DQS1 = 0
8013 00:24:58.592651 DQM Delay:
8014 00:24:58.592746 DQM0 = 135, DQM1 = 123
8015 00:24:58.595761 DQ Delay:
8016 00:24:58.598765 DQ0 =136, DQ1 =138, DQ2 =132, DQ3 =132
8017 00:24:58.602153 DQ4 =138, DQ5 =124, DQ6 =142, DQ7 =144
8018 00:24:58.605629 DQ8 =116, DQ9 =110, DQ10 =126, DQ11 =120
8019 00:24:58.609032 DQ12 =126, DQ13 =128, DQ14 =134, DQ15 =130
8020 00:24:58.609124
8021 00:24:58.609213
8022 00:24:58.609299
8023 00:24:58.612441 [DramC_TX_OE_Calibration] TA2
8024 00:24:58.615493 Original DQ_B0 (3 6) =30, OEN = 27
8025 00:24:58.618796 Original DQ_B1 (3 6) =30, OEN = 27
8026 00:24:58.622288 24, 0x0, End_B0=24 End_B1=24
8027 00:24:58.622366 25, 0x0, End_B0=25 End_B1=25
8028 00:24:58.625731 26, 0x0, End_B0=26 End_B1=26
8029 00:24:58.628658 27, 0x0, End_B0=27 End_B1=27
8030 00:24:58.632196 28, 0x0, End_B0=28 End_B1=28
8031 00:24:58.635305 29, 0x0, End_B0=29 End_B1=29
8032 00:24:58.635384 30, 0x0, End_B0=30 End_B1=30
8033 00:24:58.638872 31, 0x4141, End_B0=30 End_B1=30
8034 00:24:58.641997 Byte0 end_step=30 best_step=27
8035 00:24:58.645684 Byte1 end_step=30 best_step=27
8036 00:24:58.648568 Byte0 TX OE(2T, 0.5T) = (3, 3)
8037 00:24:58.652035 Byte1 TX OE(2T, 0.5T) = (3, 3)
8038 00:24:58.652112
8039 00:24:58.652171
8040 00:24:58.658783 [DQSOSCAuto] RK0, (LSB)MR18= 0x201f, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
8041 00:24:58.661823 CH0 RK0: MR19=303, MR18=201F
8042 00:24:58.668744 CH0_RK0: MR19=0x303, MR18=0x201F, DQSOSC=393, MR23=63, INC=23, DEC=15
8043 00:24:58.668822
8044 00:24:58.672053 ----->DramcWriteLeveling(PI) begin...
8045 00:24:58.672132 ==
8046 00:24:58.675304 Dram Type= 6, Freq= 0, CH_0, rank 1
8047 00:24:58.678526 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8048 00:24:58.678604 ==
8049 00:24:58.681798 Write leveling (Byte 0): 38 => 38
8050 00:24:58.685516 Write leveling (Byte 1): 32 => 32
8051 00:24:58.688527 DramcWriteLeveling(PI) end<-----
8052 00:24:58.688603
8053 00:24:58.688662 ==
8054 00:24:58.691864 Dram Type= 6, Freq= 0, CH_0, rank 1
8055 00:24:58.695089 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8056 00:24:58.695167 ==
8057 00:24:58.698821 [Gating] SW mode calibration
8058 00:24:58.705493 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8059 00:24:58.711944 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8060 00:24:58.714973 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8061 00:24:58.718304 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8062 00:24:58.725365 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8063 00:24:58.728257 1 4 12 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
8064 00:24:58.732006 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8065 00:24:58.738503 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8066 00:24:58.741552 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8067 00:24:58.745222 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8068 00:24:58.751925 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8069 00:24:58.755432 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8070 00:24:58.758576 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8071 00:24:58.765040 1 5 12 | B1->B0 | 3333 2a2a | 0 0 | (0 1) (1 0)
8072 00:24:58.768414 1 5 16 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
8073 00:24:58.771791 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8074 00:24:58.778247 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8075 00:24:58.782092 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8076 00:24:58.784879 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8077 00:24:58.791661 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8078 00:24:58.794707 1 6 8 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
8079 00:24:58.798234 1 6 12 | B1->B0 | 3030 4646 | 1 0 | (0 0) (0 0)
8080 00:24:58.805198 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8081 00:24:58.808340 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8082 00:24:58.811878 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8083 00:24:58.818207 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8084 00:24:58.821586 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8085 00:24:58.824588 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8086 00:24:58.828364 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8087 00:24:58.834846 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8088 00:24:58.838339 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8089 00:24:58.841722 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8090 00:24:58.848620 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8091 00:24:58.851873 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8092 00:24:58.855059 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8093 00:24:58.861613 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8094 00:24:58.864885 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8095 00:24:58.868469 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8096 00:24:58.875292 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8097 00:24:58.878238 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8098 00:24:58.881419 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8099 00:24:58.888369 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8100 00:24:58.892149 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8101 00:24:58.894978 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8102 00:24:58.901503 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8103 00:24:58.905157 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8104 00:24:58.908042 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8105 00:24:58.914723 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8106 00:24:58.914800 Total UI for P1: 0, mck2ui 16
8107 00:24:58.918163 best dqsien dly found for B0: ( 1, 9, 12)
8108 00:24:58.921626 Total UI for P1: 0, mck2ui 16
8109 00:24:58.924855 best dqsien dly found for B1: ( 1, 9, 14)
8110 00:24:58.928493 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8111 00:24:58.934592 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8112 00:24:58.934686
8113 00:24:58.938094 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8114 00:24:58.941391 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8115 00:24:58.944588 [Gating] SW calibration Done
8116 00:24:58.944668 ==
8117 00:24:58.948135 Dram Type= 6, Freq= 0, CH_0, rank 1
8118 00:24:58.951072 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8119 00:24:58.951147 ==
8120 00:24:58.954356 RX Vref Scan: 0
8121 00:24:58.954425
8122 00:24:58.954481 RX Vref 0 -> 0, step: 1
8123 00:24:58.954542
8124 00:24:58.958059 RX Delay 0 -> 252, step: 8
8125 00:24:58.960944 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8126 00:24:58.968027 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8127 00:24:58.971244 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8128 00:24:58.974240 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8129 00:24:58.977665 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8130 00:24:58.981207 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8131 00:24:58.984477 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8132 00:24:58.991183 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8133 00:24:58.994147 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8134 00:24:58.997719 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8135 00:24:59.000958 iDelay=200, Bit 10, Center 127 (80 ~ 175) 96
8136 00:24:59.007460 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8137 00:24:59.011063 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8138 00:24:59.014224 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8139 00:24:59.017756 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8140 00:24:59.020778 iDelay=200, Bit 15, Center 131 (80 ~ 183) 104
8141 00:24:59.020860 ==
8142 00:24:59.024417 Dram Type= 6, Freq= 0, CH_0, rank 1
8143 00:24:59.030850 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8144 00:24:59.030937 ==
8145 00:24:59.031016 DQS Delay:
8146 00:24:59.034294 DQS0 = 0, DQS1 = 0
8147 00:24:59.034383 DQM Delay:
8148 00:24:59.037796 DQM0 = 136, DQM1 = 125
8149 00:24:59.037912 DQ Delay:
8150 00:24:59.040906 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =131
8151 00:24:59.044022 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8152 00:24:59.047201 DQ8 =115, DQ9 =111, DQ10 =127, DQ11 =123
8153 00:24:59.050777 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
8154 00:24:59.050849
8155 00:24:59.050932
8156 00:24:59.051003 ==
8157 00:24:59.054370 Dram Type= 6, Freq= 0, CH_0, rank 1
8158 00:24:59.060627 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8159 00:24:59.060728 ==
8160 00:24:59.060803
8161 00:24:59.060873
8162 00:24:59.060943 TX Vref Scan disable
8163 00:24:59.064215 == TX Byte 0 ==
8164 00:24:59.067706 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
8165 00:24:59.071140 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8166 00:24:59.074344 == TX Byte 1 ==
8167 00:24:59.077575 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
8168 00:24:59.083999 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
8169 00:24:59.084079 ==
8170 00:24:59.087533 Dram Type= 6, Freq= 0, CH_0, rank 1
8171 00:24:59.090882 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8172 00:24:59.090962 ==
8173 00:24:59.104643
8174 00:24:59.108262 TX Vref early break, caculate TX vref
8175 00:24:59.111270 TX Vref=16, minBit 0, minWin=23, winSum=385
8176 00:24:59.114856 TX Vref=18, minBit 3, minWin=23, winSum=393
8177 00:24:59.117997 TX Vref=20, minBit 8, minWin=23, winSum=400
8178 00:24:59.121570 TX Vref=22, minBit 11, minWin=24, winSum=410
8179 00:24:59.125053 TX Vref=24, minBit 0, minWin=25, winSum=417
8180 00:24:59.131567 TX Vref=26, minBit 2, minWin=25, winSum=428
8181 00:24:59.135063 TX Vref=28, minBit 2, minWin=26, winSum=429
8182 00:24:59.137996 TX Vref=30, minBit 2, minWin=26, winSum=428
8183 00:24:59.141786 TX Vref=32, minBit 0, minWin=25, winSum=417
8184 00:24:59.144831 TX Vref=34, minBit 0, minWin=24, winSum=407
8185 00:24:59.148281 TX Vref=36, minBit 2, minWin=24, winSum=402
8186 00:24:59.154682 [TxChooseVref] Worse bit 2, Min win 26, Win sum 429, Final Vref 28
8187 00:24:59.154765
8188 00:24:59.158489 Final TX Range 0 Vref 28
8189 00:24:59.158569
8190 00:24:59.158648 ==
8191 00:24:59.161385 Dram Type= 6, Freq= 0, CH_0, rank 1
8192 00:24:59.164526 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8193 00:24:59.164629 ==
8194 00:24:59.164731
8195 00:24:59.164804
8196 00:24:59.167904 TX Vref Scan disable
8197 00:24:59.174634 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8198 00:24:59.174714 == TX Byte 0 ==
8199 00:24:59.177859 u2DelayCellOfst[0]=13 cells (4 PI)
8200 00:24:59.181262 u2DelayCellOfst[1]=20 cells (6 PI)
8201 00:24:59.184757 u2DelayCellOfst[2]=13 cells (4 PI)
8202 00:24:59.187776 u2DelayCellOfst[3]=13 cells (4 PI)
8203 00:24:59.191298 u2DelayCellOfst[4]=10 cells (3 PI)
8204 00:24:59.194404 u2DelayCellOfst[5]=0 cells (0 PI)
8205 00:24:59.197659 u2DelayCellOfst[6]=20 cells (6 PI)
8206 00:24:59.200925 u2DelayCellOfst[7]=20 cells (6 PI)
8207 00:24:59.204260 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8208 00:24:59.207809 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8209 00:24:59.211383 == TX Byte 1 ==
8210 00:24:59.214446 u2DelayCellOfst[8]=0 cells (0 PI)
8211 00:24:59.217501 u2DelayCellOfst[9]=0 cells (0 PI)
8212 00:24:59.221077 u2DelayCellOfst[10]=6 cells (2 PI)
8213 00:24:59.221157 u2DelayCellOfst[11]=3 cells (1 PI)
8214 00:24:59.224613 u2DelayCellOfst[12]=13 cells (4 PI)
8215 00:24:59.227735 u2DelayCellOfst[13]=13 cells (4 PI)
8216 00:24:59.231273 u2DelayCellOfst[14]=13 cells (4 PI)
8217 00:24:59.234810 u2DelayCellOfst[15]=13 cells (4 PI)
8218 00:24:59.238052 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8219 00:24:59.244864 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
8220 00:24:59.244945 DramC Write-DBI on
8221 00:24:59.245024 ==
8222 00:24:59.247944 Dram Type= 6, Freq= 0, CH_0, rank 1
8223 00:24:59.254757 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8224 00:24:59.254837 ==
8225 00:24:59.254915
8226 00:24:59.254988
8227 00:24:59.255059 TX Vref Scan disable
8228 00:24:59.258321 == TX Byte 0 ==
8229 00:24:59.262029 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8230 00:24:59.264940 == TX Byte 1 ==
8231 00:24:59.268344 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
8232 00:24:59.271773 DramC Write-DBI off
8233 00:24:59.271854
8234 00:24:59.271931 [DATLAT]
8235 00:24:59.272004 Freq=1600, CH0 RK1
8236 00:24:59.272075
8237 00:24:59.274882 DATLAT Default: 0xf
8238 00:24:59.274961 0, 0xFFFF, sum = 0
8239 00:24:59.278573 1, 0xFFFF, sum = 0
8240 00:24:59.278654 2, 0xFFFF, sum = 0
8241 00:24:59.281677 3, 0xFFFF, sum = 0
8242 00:24:59.284991 4, 0xFFFF, sum = 0
8243 00:24:59.285084 5, 0xFFFF, sum = 0
8244 00:24:59.288248 6, 0xFFFF, sum = 0
8245 00:24:59.288332 7, 0xFFFF, sum = 0
8246 00:24:59.291603 8, 0xFFFF, sum = 0
8247 00:24:59.291678 9, 0xFFFF, sum = 0
8248 00:24:59.294739 10, 0xFFFF, sum = 0
8249 00:24:59.294824 11, 0xFFFF, sum = 0
8250 00:24:59.298349 12, 0xFFFF, sum = 0
8251 00:24:59.298439 13, 0xFFFF, sum = 0
8252 00:24:59.301878 14, 0x0, sum = 1
8253 00:24:59.301960 15, 0x0, sum = 2
8254 00:24:59.305117 16, 0x0, sum = 3
8255 00:24:59.305203 17, 0x0, sum = 4
8256 00:24:59.308241 best_step = 15
8257 00:24:59.308309
8258 00:24:59.308377 ==
8259 00:24:59.311766 Dram Type= 6, Freq= 0, CH_0, rank 1
8260 00:24:59.314783 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8261 00:24:59.314859 ==
8262 00:24:59.314929 RX Vref Scan: 0
8263 00:24:59.318349
8264 00:24:59.318424 RX Vref 0 -> 0, step: 1
8265 00:24:59.318493
8266 00:24:59.321485 RX Delay 11 -> 252, step: 4
8267 00:24:59.324801 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8268 00:24:59.331573 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8269 00:24:59.335020 iDelay=191, Bit 2, Center 128 (79 ~ 178) 100
8270 00:24:59.338567 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8271 00:24:59.341464 iDelay=191, Bit 4, Center 134 (87 ~ 182) 96
8272 00:24:59.344951 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8273 00:24:59.348149 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8274 00:24:59.354974 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8275 00:24:59.358308 iDelay=191, Bit 8, Center 114 (67 ~ 162) 96
8276 00:24:59.361564 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8277 00:24:59.364991 iDelay=191, Bit 10, Center 126 (79 ~ 174) 96
8278 00:24:59.368007 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8279 00:24:59.374820 iDelay=191, Bit 12, Center 128 (79 ~ 178) 100
8280 00:24:59.378113 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8281 00:24:59.381393 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8282 00:24:59.384973 iDelay=191, Bit 15, Center 130 (79 ~ 182) 104
8283 00:24:59.385057 ==
8284 00:24:59.388373 Dram Type= 6, Freq= 0, CH_0, rank 1
8285 00:24:59.394905 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8286 00:24:59.395000 ==
8287 00:24:59.395073 DQS Delay:
8288 00:24:59.398306 DQS0 = 0, DQS1 = 0
8289 00:24:59.398381 DQM Delay:
8290 00:24:59.398440 DQM0 = 132, DQM1 = 123
8291 00:24:59.401413 DQ Delay:
8292 00:24:59.404674 DQ0 =132, DQ1 =136, DQ2 =128, DQ3 =130
8293 00:24:59.408157 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =138
8294 00:24:59.411626 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =120
8295 00:24:59.414801 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =130
8296 00:24:59.414872
8297 00:24:59.414931
8298 00:24:59.414986
8299 00:24:59.418264 [DramC_TX_OE_Calibration] TA2
8300 00:24:59.421179 Original DQ_B0 (3 6) =30, OEN = 27
8301 00:24:59.424943 Original DQ_B1 (3 6) =30, OEN = 27
8302 00:24:59.427972 24, 0x0, End_B0=24 End_B1=24
8303 00:24:59.428097 25, 0x0, End_B0=25 End_B1=25
8304 00:24:59.431456 26, 0x0, End_B0=26 End_B1=26
8305 00:24:59.434625 27, 0x0, End_B0=27 End_B1=27
8306 00:24:59.438265 28, 0x0, End_B0=28 End_B1=28
8307 00:24:59.441334 29, 0x0, End_B0=29 End_B1=29
8308 00:24:59.441414 30, 0x0, End_B0=30 End_B1=30
8309 00:24:59.444913 31, 0x4141, End_B0=30 End_B1=30
8310 00:24:59.448035 Byte0 end_step=30 best_step=27
8311 00:24:59.451367 Byte1 end_step=30 best_step=27
8312 00:24:59.454866 Byte0 TX OE(2T, 0.5T) = (3, 3)
8313 00:24:59.454950 Byte1 TX OE(2T, 0.5T) = (3, 3)
8314 00:24:59.458173
8315 00:24:59.458252
8316 00:24:59.464723 [DQSOSCAuto] RK1, (LSB)MR18= 0x210e, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 393 ps
8317 00:24:59.468215 CH0 RK1: MR19=303, MR18=210E
8318 00:24:59.474953 CH0_RK1: MR19=0x303, MR18=0x210E, DQSOSC=393, MR23=63, INC=23, DEC=15
8319 00:24:59.478065 [RxdqsGatingPostProcess] freq 1600
8320 00:24:59.481491 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8321 00:24:59.484878 best DQS0 dly(2T, 0.5T) = (1, 1)
8322 00:24:59.488103 best DQS1 dly(2T, 0.5T) = (1, 1)
8323 00:24:59.491527 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8324 00:24:59.494541 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8325 00:24:59.498011 best DQS0 dly(2T, 0.5T) = (1, 1)
8326 00:24:59.501181 best DQS1 dly(2T, 0.5T) = (1, 1)
8327 00:24:59.504536 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8328 00:24:59.507805 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8329 00:24:59.511148 Pre-setting of DQS Precalculation
8330 00:24:59.514624 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8331 00:24:59.514751 ==
8332 00:24:59.517880 Dram Type= 6, Freq= 0, CH_1, rank 0
8333 00:24:59.521264 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8334 00:24:59.521343 ==
8335 00:24:59.527863 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8336 00:24:59.531308 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8337 00:24:59.537939 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8338 00:24:59.541302 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8339 00:24:59.551118 [CA 0] Center 40 (11~70) winsize 60
8340 00:24:59.554246 [CA 1] Center 41 (11~71) winsize 61
8341 00:24:59.557837 [CA 2] Center 37 (8~67) winsize 60
8342 00:24:59.560834 [CA 3] Center 36 (6~66) winsize 61
8343 00:24:59.564482 [CA 4] Center 36 (7~66) winsize 60
8344 00:24:59.567944 [CA 5] Center 36 (6~66) winsize 61
8345 00:24:59.568022
8346 00:24:59.571099 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8347 00:24:59.571176
8348 00:24:59.574074 [CATrainingPosCal] consider 1 rank data
8349 00:24:59.577556 u2DelayCellTimex100 = 290/100 ps
8350 00:24:59.584291 CA0 delay=40 (11~70),Diff = 4 PI (13 cell)
8351 00:24:59.587319 CA1 delay=41 (11~71),Diff = 5 PI (16 cell)
8352 00:24:59.590862 CA2 delay=37 (8~67),Diff = 1 PI (3 cell)
8353 00:24:59.594105 CA3 delay=36 (6~66),Diff = 0 PI (0 cell)
8354 00:24:59.597400 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
8355 00:24:59.600929 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
8356 00:24:59.601007
8357 00:24:59.603793 CA PerBit enable=1, Macro0, CA PI delay=36
8358 00:24:59.603859
8359 00:24:59.607654 [CBTSetCACLKResult] CA Dly = 36
8360 00:24:59.610505 CS Dly: 8 (0~39)
8361 00:24:59.614154 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8362 00:24:59.617539 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8363 00:24:59.617616 ==
8364 00:24:59.620496 Dram Type= 6, Freq= 0, CH_1, rank 1
8365 00:24:59.623862 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8366 00:24:59.627144 ==
8367 00:24:59.630642 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8368 00:24:59.633754 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8369 00:24:59.640460 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8370 00:24:59.643968 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8371 00:24:59.654153 [CA 0] Center 42 (13~72) winsize 60
8372 00:24:59.657790 [CA 1] Center 42 (12~72) winsize 61
8373 00:24:59.660675 [CA 2] Center 38 (9~68) winsize 60
8374 00:24:59.664440 [CA 3] Center 38 (9~67) winsize 59
8375 00:24:59.668026 [CA 4] Center 38 (9~67) winsize 59
8376 00:24:59.670902 [CA 5] Center 37 (7~67) winsize 61
8377 00:24:59.670995
8378 00:24:59.673976 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8379 00:24:59.674052
8380 00:24:59.677344 [CATrainingPosCal] consider 2 rank data
8381 00:24:59.681078 u2DelayCellTimex100 = 290/100 ps
8382 00:24:59.684444 CA0 delay=41 (13~70),Diff = 5 PI (16 cell)
8383 00:24:59.690842 CA1 delay=41 (12~71),Diff = 5 PI (16 cell)
8384 00:24:59.694240 CA2 delay=38 (9~67),Diff = 2 PI (6 cell)
8385 00:24:59.697185 CA3 delay=37 (9~66),Diff = 1 PI (3 cell)
8386 00:24:59.700805 CA4 delay=37 (9~66),Diff = 1 PI (3 cell)
8387 00:24:59.704491 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8388 00:24:59.704562
8389 00:24:59.707481 CA PerBit enable=1, Macro0, CA PI delay=36
8390 00:24:59.707557
8391 00:24:59.710792 [CBTSetCACLKResult] CA Dly = 36
8392 00:24:59.710897 CS Dly: 9 (0~42)
8393 00:24:59.717611 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8394 00:24:59.720570 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8395 00:24:59.720657
8396 00:24:59.723956 ----->DramcWriteLeveling(PI) begin...
8397 00:24:59.724033 ==
8398 00:24:59.727482 Dram Type= 6, Freq= 0, CH_1, rank 0
8399 00:24:59.730842 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8400 00:24:59.730918 ==
8401 00:24:59.734005 Write leveling (Byte 0): 26 => 26
8402 00:24:59.737332 Write leveling (Byte 1): 27 => 27
8403 00:24:59.740713 DramcWriteLeveling(PI) end<-----
8404 00:24:59.740811
8405 00:24:59.740870 ==
8406 00:24:59.744357 Dram Type= 6, Freq= 0, CH_1, rank 0
8407 00:24:59.750884 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8408 00:24:59.750957 ==
8409 00:24:59.751027 [Gating] SW mode calibration
8410 00:24:59.760660 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8411 00:24:59.764271 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8412 00:24:59.767493 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8413 00:24:59.773948 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8414 00:24:59.777535 1 4 8 | B1->B0 | 2b2b 3030 | 1 0 | (1 1) (0 0)
8415 00:24:59.780673 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8416 00:24:59.787159 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8417 00:24:59.790453 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8418 00:24:59.794097 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8419 00:24:59.800517 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8420 00:24:59.803884 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8421 00:24:59.807203 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8422 00:24:59.813794 1 5 8 | B1->B0 | 2828 2424 | 1 0 | (1 0) (1 0)
8423 00:24:59.817193 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8424 00:24:59.820298 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8425 00:24:59.827129 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8426 00:24:59.830613 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8427 00:24:59.833685 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8428 00:24:59.840311 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8429 00:24:59.843623 1 6 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8430 00:24:59.847163 1 6 8 | B1->B0 | 3636 3c3c | 0 0 | (0 0) (0 0)
8431 00:24:59.853948 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8432 00:24:59.857328 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8433 00:24:59.860295 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8434 00:24:59.866847 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8435 00:24:59.870473 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8436 00:24:59.873636 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8437 00:24:59.880069 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8438 00:24:59.883638 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8439 00:24:59.886726 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8440 00:24:59.889970 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8441 00:24:59.897046 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8442 00:24:59.900215 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8443 00:24:59.903627 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8444 00:24:59.909823 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8445 00:24:59.913453 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8446 00:24:59.916770 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8447 00:24:59.923595 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8448 00:24:59.926927 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8449 00:24:59.929979 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8450 00:24:59.936389 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8451 00:24:59.939882 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8452 00:24:59.943397 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8453 00:24:59.949893 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8454 00:24:59.953007 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8455 00:24:59.956416 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8456 00:24:59.960079 Total UI for P1: 0, mck2ui 16
8457 00:24:59.963733 best dqsien dly found for B0: ( 1, 9, 6)
8458 00:24:59.966748 Total UI for P1: 0, mck2ui 16
8459 00:24:59.969794 best dqsien dly found for B1: ( 1, 9, 8)
8460 00:24:59.973424 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8461 00:24:59.976696 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8462 00:24:59.976769
8463 00:24:59.980014 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8464 00:24:59.986385 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8465 00:24:59.986462 [Gating] SW calibration Done
8466 00:24:59.990028 ==
8467 00:24:59.990098 Dram Type= 6, Freq= 0, CH_1, rank 0
8468 00:24:59.996732 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8469 00:24:59.996805 ==
8470 00:24:59.996863 RX Vref Scan: 0
8471 00:24:59.996918
8472 00:25:00.000194 RX Vref 0 -> 0, step: 1
8473 00:25:00.000263
8474 00:25:00.003188 RX Delay 0 -> 252, step: 8
8475 00:25:00.006609 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8476 00:25:00.009704 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8477 00:25:00.013144 iDelay=200, Bit 2, Center 127 (80 ~ 175) 96
8478 00:25:00.016468 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8479 00:25:00.023229 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8480 00:25:00.026419 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8481 00:25:00.029818 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8482 00:25:00.033161 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8483 00:25:00.036398 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8484 00:25:00.043414 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8485 00:25:00.046694 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8486 00:25:00.049922 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8487 00:25:00.053491 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8488 00:25:00.056673 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8489 00:25:00.063219 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8490 00:25:00.066838 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8491 00:25:00.066917 ==
8492 00:25:00.069785 Dram Type= 6, Freq= 0, CH_1, rank 0
8493 00:25:00.073052 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8494 00:25:00.073131 ==
8495 00:25:00.076483 DQS Delay:
8496 00:25:00.076562 DQS0 = 0, DQS1 = 0
8497 00:25:00.076622 DQM Delay:
8498 00:25:00.080010 DQM0 = 138, DQM1 = 129
8499 00:25:00.080089 DQ Delay:
8500 00:25:00.083113 DQ0 =143, DQ1 =135, DQ2 =127, DQ3 =139
8501 00:25:00.086663 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8502 00:25:00.089814 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8503 00:25:00.096416 DQ12 =139, DQ13 =135, DQ14 =135, DQ15 =135
8504 00:25:00.096498
8505 00:25:00.096559
8506 00:25:00.096615 ==
8507 00:25:00.099902 Dram Type= 6, Freq= 0, CH_1, rank 0
8508 00:25:00.103136 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8509 00:25:00.103216 ==
8510 00:25:00.103277
8511 00:25:00.103333
8512 00:25:00.106541 TX Vref Scan disable
8513 00:25:00.106621 == TX Byte 0 ==
8514 00:25:00.112976 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8515 00:25:00.116504 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8516 00:25:00.116583 == TX Byte 1 ==
8517 00:25:00.123394 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8518 00:25:00.126277 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8519 00:25:00.126357 ==
8520 00:25:00.129665 Dram Type= 6, Freq= 0, CH_1, rank 0
8521 00:25:00.133310 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8522 00:25:00.133416 ==
8523 00:25:00.146745
8524 00:25:00.149918 TX Vref early break, caculate TX vref
8525 00:25:00.153149 TX Vref=16, minBit 10, minWin=21, winSum=371
8526 00:25:00.156691 TX Vref=18, minBit 10, minWin=22, winSum=383
8527 00:25:00.159865 TX Vref=20, minBit 10, minWin=23, winSum=392
8528 00:25:00.163382 TX Vref=22, minBit 10, minWin=24, winSum=406
8529 00:25:00.166557 TX Vref=24, minBit 10, minWin=23, winSum=411
8530 00:25:00.173551 TX Vref=26, minBit 10, minWin=24, winSum=419
8531 00:25:00.176666 TX Vref=28, minBit 14, minWin=25, winSum=425
8532 00:25:00.180302 TX Vref=30, minBit 0, minWin=25, winSum=417
8533 00:25:00.183391 TX Vref=32, minBit 9, minWin=24, winSum=407
8534 00:25:00.186417 TX Vref=34, minBit 5, minWin=24, winSum=398
8535 00:25:00.193122 [TxChooseVref] Worse bit 14, Min win 25, Win sum 425, Final Vref 28
8536 00:25:00.193194
8537 00:25:00.196158 Final TX Range 0 Vref 28
8538 00:25:00.196228
8539 00:25:00.196285 ==
8540 00:25:00.199436 Dram Type= 6, Freq= 0, CH_1, rank 0
8541 00:25:00.203037 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8542 00:25:00.203108 ==
8543 00:25:00.203171
8544 00:25:00.203227
8545 00:25:00.206587 TX Vref Scan disable
8546 00:25:00.212964 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8547 00:25:00.213036 == TX Byte 0 ==
8548 00:25:00.216057 u2DelayCellOfst[0]=13 cells (4 PI)
8549 00:25:00.219854 u2DelayCellOfst[1]=10 cells (3 PI)
8550 00:25:00.222789 u2DelayCellOfst[2]=0 cells (0 PI)
8551 00:25:00.226219 u2DelayCellOfst[3]=3 cells (1 PI)
8552 00:25:00.229737 u2DelayCellOfst[4]=6 cells (2 PI)
8553 00:25:00.232757 u2DelayCellOfst[5]=16 cells (5 PI)
8554 00:25:00.236452 u2DelayCellOfst[6]=16 cells (5 PI)
8555 00:25:00.239632 u2DelayCellOfst[7]=3 cells (1 PI)
8556 00:25:00.242741 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8557 00:25:00.246216 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8558 00:25:00.249226 == TX Byte 1 ==
8559 00:25:00.252780 u2DelayCellOfst[8]=0 cells (0 PI)
8560 00:25:00.252855 u2DelayCellOfst[9]=3 cells (1 PI)
8561 00:25:00.255895 u2DelayCellOfst[10]=10 cells (3 PI)
8562 00:25:00.259529 u2DelayCellOfst[11]=3 cells (1 PI)
8563 00:25:00.262813 u2DelayCellOfst[12]=13 cells (4 PI)
8564 00:25:00.265983 u2DelayCellOfst[13]=16 cells (5 PI)
8565 00:25:00.269618 u2DelayCellOfst[14]=16 cells (5 PI)
8566 00:25:00.272439 u2DelayCellOfst[15]=16 cells (5 PI)
8567 00:25:00.275834 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8568 00:25:00.282812 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8569 00:25:00.282891 DramC Write-DBI on
8570 00:25:00.282951 ==
8571 00:25:00.285870 Dram Type= 6, Freq= 0, CH_1, rank 0
8572 00:25:00.292429 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8573 00:25:00.292528 ==
8574 00:25:00.292612
8575 00:25:00.292693
8576 00:25:00.292765 TX Vref Scan disable
8577 00:25:00.296471 == TX Byte 0 ==
8578 00:25:00.299591 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8579 00:25:00.303247 == TX Byte 1 ==
8580 00:25:00.306324 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8581 00:25:00.309702 DramC Write-DBI off
8582 00:25:00.309771
8583 00:25:00.309833 [DATLAT]
8584 00:25:00.309888 Freq=1600, CH1 RK0
8585 00:25:00.309944
8586 00:25:00.312883 DATLAT Default: 0xf
8587 00:25:00.312948 0, 0xFFFF, sum = 0
8588 00:25:00.316629 1, 0xFFFF, sum = 0
8589 00:25:00.319571 2, 0xFFFF, sum = 0
8590 00:25:00.319660 3, 0xFFFF, sum = 0
8591 00:25:00.323013 4, 0xFFFF, sum = 0
8592 00:25:00.323081 5, 0xFFFF, sum = 0
8593 00:25:00.326419 6, 0xFFFF, sum = 0
8594 00:25:00.326490 7, 0xFFFF, sum = 0
8595 00:25:00.329332 8, 0xFFFF, sum = 0
8596 00:25:00.329399 9, 0xFFFF, sum = 0
8597 00:25:00.332788 10, 0xFFFF, sum = 0
8598 00:25:00.332857 11, 0xFFFF, sum = 0
8599 00:25:00.335881 12, 0xFFFF, sum = 0
8600 00:25:00.335952 13, 0xFFFF, sum = 0
8601 00:25:00.339504 14, 0x0, sum = 1
8602 00:25:00.339578 15, 0x0, sum = 2
8603 00:25:00.342655 16, 0x0, sum = 3
8604 00:25:00.342729 17, 0x0, sum = 4
8605 00:25:00.346139 best_step = 15
8606 00:25:00.346208
8607 00:25:00.346279 ==
8608 00:25:00.349519 Dram Type= 6, Freq= 0, CH_1, rank 0
8609 00:25:00.352977 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8610 00:25:00.353046 ==
8611 00:25:00.356128 RX Vref Scan: 1
8612 00:25:00.356195
8613 00:25:00.356252 Set Vref Range= 24 -> 127
8614 00:25:00.356305
8615 00:25:00.359387 RX Vref 24 -> 127, step: 1
8616 00:25:00.359455
8617 00:25:00.362679 RX Delay 19 -> 252, step: 4
8618 00:25:00.362743
8619 00:25:00.366157 Set Vref, RX VrefLevel [Byte0]: 24
8620 00:25:00.369894 [Byte1]: 24
8621 00:25:00.369967
8622 00:25:00.372626 Set Vref, RX VrefLevel [Byte0]: 25
8623 00:25:00.376293 [Byte1]: 25
8624 00:25:00.376365
8625 00:25:00.379171 Set Vref, RX VrefLevel [Byte0]: 26
8626 00:25:00.382611 [Byte1]: 26
8627 00:25:00.386469
8628 00:25:00.386537 Set Vref, RX VrefLevel [Byte0]: 27
8629 00:25:00.389923 [Byte1]: 27
8630 00:25:00.394352
8631 00:25:00.394446 Set Vref, RX VrefLevel [Byte0]: 28
8632 00:25:00.397525 [Byte1]: 28
8633 00:25:00.401610
8634 00:25:00.401683 Set Vref, RX VrefLevel [Byte0]: 29
8635 00:25:00.405215 [Byte1]: 29
8636 00:25:00.409174
8637 00:25:00.409239 Set Vref, RX VrefLevel [Byte0]: 30
8638 00:25:00.412828 [Byte1]: 30
8639 00:25:00.416820
8640 00:25:00.416886 Set Vref, RX VrefLevel [Byte0]: 31
8641 00:25:00.420419 [Byte1]: 31
8642 00:25:00.424486
8643 00:25:00.424554 Set Vref, RX VrefLevel [Byte0]: 32
8644 00:25:00.427838 [Byte1]: 32
8645 00:25:00.431780
8646 00:25:00.431849 Set Vref, RX VrefLevel [Byte0]: 33
8647 00:25:00.435232 [Byte1]: 33
8648 00:25:00.439746
8649 00:25:00.439851 Set Vref, RX VrefLevel [Byte0]: 34
8650 00:25:00.442893 [Byte1]: 34
8651 00:25:00.447331
8652 00:25:00.447438 Set Vref, RX VrefLevel [Byte0]: 35
8653 00:25:00.450487 [Byte1]: 35
8654 00:25:00.454806
8655 00:25:00.454881 Set Vref, RX VrefLevel [Byte0]: 36
8656 00:25:00.457880 [Byte1]: 36
8657 00:25:00.462176
8658 00:25:00.462252 Set Vref, RX VrefLevel [Byte0]: 37
8659 00:25:00.465536 [Byte1]: 37
8660 00:25:00.469693
8661 00:25:00.469785 Set Vref, RX VrefLevel [Byte0]: 38
8662 00:25:00.473269 [Byte1]: 38
8663 00:25:00.477486
8664 00:25:00.477583 Set Vref, RX VrefLevel [Byte0]: 39
8665 00:25:00.480678 [Byte1]: 39
8666 00:25:00.484824
8667 00:25:00.484892 Set Vref, RX VrefLevel [Byte0]: 40
8668 00:25:00.488344 [Byte1]: 40
8669 00:25:00.492674
8670 00:25:00.492760 Set Vref, RX VrefLevel [Byte0]: 41
8671 00:25:00.496090 [Byte1]: 41
8672 00:25:00.500301
8673 00:25:00.500378 Set Vref, RX VrefLevel [Byte0]: 42
8674 00:25:00.503317 [Byte1]: 42
8675 00:25:00.507879
8676 00:25:00.507955 Set Vref, RX VrefLevel [Byte0]: 43
8677 00:25:00.510939 [Byte1]: 43
8678 00:25:00.515372
8679 00:25:00.515442 Set Vref, RX VrefLevel [Byte0]: 44
8680 00:25:00.518788 [Byte1]: 44
8681 00:25:00.522942
8682 00:25:00.523012 Set Vref, RX VrefLevel [Byte0]: 45
8683 00:25:00.526529 [Byte1]: 45
8684 00:25:00.530347
8685 00:25:00.530416 Set Vref, RX VrefLevel [Byte0]: 46
8686 00:25:00.534036 [Byte1]: 46
8687 00:25:00.538278
8688 00:25:00.538376 Set Vref, RX VrefLevel [Byte0]: 47
8689 00:25:00.541309 [Byte1]: 47
8690 00:25:00.545462
8691 00:25:00.545530 Set Vref, RX VrefLevel [Byte0]: 48
8692 00:25:00.548997 [Byte1]: 48
8693 00:25:00.553119
8694 00:25:00.553190 Set Vref, RX VrefLevel [Byte0]: 49
8695 00:25:00.556641 [Byte1]: 49
8696 00:25:00.560801
8697 00:25:00.560873 Set Vref, RX VrefLevel [Byte0]: 50
8698 00:25:00.564242 [Byte1]: 50
8699 00:25:00.568598
8700 00:25:00.568684 Set Vref, RX VrefLevel [Byte0]: 51
8701 00:25:00.571785 [Byte1]: 51
8702 00:25:00.575820
8703 00:25:00.575918 Set Vref, RX VrefLevel [Byte0]: 52
8704 00:25:00.579261 [Byte1]: 52
8705 00:25:00.583520
8706 00:25:00.583594 Set Vref, RX VrefLevel [Byte0]: 53
8707 00:25:00.586730 [Byte1]: 53
8708 00:25:00.591143
8709 00:25:00.591215 Set Vref, RX VrefLevel [Byte0]: 54
8710 00:25:00.594590 [Byte1]: 54
8711 00:25:00.598614
8712 00:25:00.598685 Set Vref, RX VrefLevel [Byte0]: 55
8713 00:25:00.601867 [Byte1]: 55
8714 00:25:00.606457
8715 00:25:00.606526 Set Vref, RX VrefLevel [Byte0]: 56
8716 00:25:00.609728 [Byte1]: 56
8717 00:25:00.614142
8718 00:25:00.614212 Set Vref, RX VrefLevel [Byte0]: 57
8719 00:25:00.617114 [Byte1]: 57
8720 00:25:00.621280
8721 00:25:00.621350 Set Vref, RX VrefLevel [Byte0]: 58
8722 00:25:00.624918 [Byte1]: 58
8723 00:25:00.628846
8724 00:25:00.628912 Set Vref, RX VrefLevel [Byte0]: 59
8725 00:25:00.632272 [Byte1]: 59
8726 00:25:00.636725
8727 00:25:00.636808 Set Vref, RX VrefLevel [Byte0]: 60
8728 00:25:00.639666 [Byte1]: 60
8729 00:25:00.644141
8730 00:25:00.644239 Set Vref, RX VrefLevel [Byte0]: 61
8731 00:25:00.647271 [Byte1]: 61
8732 00:25:00.651783
8733 00:25:00.651878 Set Vref, RX VrefLevel [Byte0]: 62
8734 00:25:00.654880 [Byte1]: 62
8735 00:25:00.659472
8736 00:25:00.659538 Set Vref, RX VrefLevel [Byte0]: 63
8737 00:25:00.662807 [Byte1]: 63
8738 00:25:00.666920
8739 00:25:00.666988 Set Vref, RX VrefLevel [Byte0]: 64
8740 00:25:00.669939 [Byte1]: 64
8741 00:25:00.674416
8742 00:25:00.674483 Set Vref, RX VrefLevel [Byte0]: 65
8743 00:25:00.677720 [Byte1]: 65
8744 00:25:00.681868
8745 00:25:00.681937 Set Vref, RX VrefLevel [Byte0]: 66
8746 00:25:00.685243 [Byte1]: 66
8747 00:25:00.689473
8748 00:25:00.689539 Set Vref, RX VrefLevel [Byte0]: 67
8749 00:25:00.692788 [Byte1]: 67
8750 00:25:00.697015
8751 00:25:00.697083 Set Vref, RX VrefLevel [Byte0]: 68
8752 00:25:00.700475 [Byte1]: 68
8753 00:25:00.704654
8754 00:25:00.704744 Set Vref, RX VrefLevel [Byte0]: 69
8755 00:25:00.707877 [Byte1]: 69
8756 00:25:00.712060
8757 00:25:00.712159 Set Vref, RX VrefLevel [Byte0]: 70
8758 00:25:00.715459 [Byte1]: 70
8759 00:25:00.719931
8760 00:25:00.720009 Set Vref, RX VrefLevel [Byte0]: 71
8761 00:25:00.723055 [Byte1]: 71
8762 00:25:00.727171
8763 00:25:00.727248 Set Vref, RX VrefLevel [Byte0]: 72
8764 00:25:00.730879 [Byte1]: 72
8765 00:25:00.735018
8766 00:25:00.735095 Set Vref, RX VrefLevel [Byte0]: 73
8767 00:25:00.738283 [Byte1]: 73
8768 00:25:00.742739
8769 00:25:00.742816 Set Vref, RX VrefLevel [Byte0]: 74
8770 00:25:00.745667 [Byte1]: 74
8771 00:25:00.750260
8772 00:25:00.750337 Final RX Vref Byte 0 = 52 to rank0
8773 00:25:00.753500 Final RX Vref Byte 1 = 62 to rank0
8774 00:25:00.757101 Final RX Vref Byte 0 = 52 to rank1
8775 00:25:00.760072 Final RX Vref Byte 1 = 62 to rank1==
8776 00:25:00.763686 Dram Type= 6, Freq= 0, CH_1, rank 0
8777 00:25:00.770400 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8778 00:25:00.770479 ==
8779 00:25:00.770539 DQS Delay:
8780 00:25:00.770594 DQS0 = 0, DQS1 = 0
8781 00:25:00.773508 DQM Delay:
8782 00:25:00.773625 DQM0 = 133, DQM1 = 129
8783 00:25:00.776828 DQ Delay:
8784 00:25:00.779863 DQ0 =136, DQ1 =128, DQ2 =122, DQ3 =132
8785 00:25:00.783535 DQ4 =132, DQ5 =144, DQ6 =144, DQ7 =130
8786 00:25:00.786828 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =122
8787 00:25:00.789957 DQ12 =140, DQ13 =134, DQ14 =136, DQ15 =134
8788 00:25:00.790034
8789 00:25:00.790093
8790 00:25:00.790151
8791 00:25:00.793404 [DramC_TX_OE_Calibration] TA2
8792 00:25:00.796674 Original DQ_B0 (3 6) =30, OEN = 27
8793 00:25:00.799577 Original DQ_B1 (3 6) =30, OEN = 27
8794 00:25:00.803376 24, 0x0, End_B0=24 End_B1=24
8795 00:25:00.803454 25, 0x0, End_B0=25 End_B1=25
8796 00:25:00.806544 26, 0x0, End_B0=26 End_B1=26
8797 00:25:00.809979 27, 0x0, End_B0=27 End_B1=27
8798 00:25:00.813381 28, 0x0, End_B0=28 End_B1=28
8799 00:25:00.816819 29, 0x0, End_B0=29 End_B1=29
8800 00:25:00.816896 30, 0x0, End_B0=30 End_B1=30
8801 00:25:00.819871 31, 0x4141, End_B0=30 End_B1=30
8802 00:25:00.823120 Byte0 end_step=30 best_step=27
8803 00:25:00.826740 Byte1 end_step=30 best_step=27
8804 00:25:00.829655 Byte0 TX OE(2T, 0.5T) = (3, 3)
8805 00:25:00.833018 Byte1 TX OE(2T, 0.5T) = (3, 3)
8806 00:25:00.833094
8807 00:25:00.833175
8808 00:25:00.839797 [DQSOSCAuto] RK0, (LSB)MR18= 0x1927, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
8809 00:25:00.843175 CH1 RK0: MR19=303, MR18=1927
8810 00:25:00.849668 CH1_RK0: MR19=0x303, MR18=0x1927, DQSOSC=390, MR23=63, INC=24, DEC=16
8811 00:25:00.849746
8812 00:25:00.852856 ----->DramcWriteLeveling(PI) begin...
8813 00:25:00.852958 ==
8814 00:25:00.856306 Dram Type= 6, Freq= 0, CH_1, rank 1
8815 00:25:00.859829 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8816 00:25:00.859907 ==
8817 00:25:00.862882 Write leveling (Byte 0): 24 => 24
8818 00:25:00.866574 Write leveling (Byte 1): 27 => 27
8819 00:25:00.869685 DramcWriteLeveling(PI) end<-----
8820 00:25:00.869761
8821 00:25:00.869820 ==
8822 00:25:00.872929 Dram Type= 6, Freq= 0, CH_1, rank 1
8823 00:25:00.875953 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8824 00:25:00.876031 ==
8825 00:25:00.879404 [Gating] SW mode calibration
8826 00:25:00.886104 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8827 00:25:00.892713 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8828 00:25:00.895822 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8829 00:25:00.902975 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8830 00:25:00.906023 1 4 8 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
8831 00:25:00.909752 1 4 12 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
8832 00:25:00.913006 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8833 00:25:00.919707 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8834 00:25:00.922697 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8835 00:25:00.925975 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8836 00:25:00.932887 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8837 00:25:00.935813 1 5 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8838 00:25:00.939279 1 5 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 0)
8839 00:25:00.946035 1 5 12 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (1 0)
8840 00:25:00.949367 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8841 00:25:00.952387 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8842 00:25:00.959292 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8843 00:25:00.962818 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8844 00:25:00.965797 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8845 00:25:00.972591 1 6 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8846 00:25:00.975963 1 6 8 | B1->B0 | 4646 2323 | 0 0 | (0 0) (0 0)
8847 00:25:00.979411 1 6 12 | B1->B0 | 4646 4141 | 0 0 | (0 0) (0 0)
8848 00:25:00.985391 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8849 00:25:00.989114 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8850 00:25:00.992710 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8851 00:25:00.998803 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8852 00:25:01.002420 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8853 00:25:01.005636 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8854 00:25:01.012208 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8855 00:25:01.015366 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8856 00:25:01.018865 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8857 00:25:01.025976 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8858 00:25:01.029317 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8859 00:25:01.032359 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8860 00:25:01.035750 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8861 00:25:01.042241 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8862 00:25:01.045894 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8863 00:25:01.049367 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8864 00:25:01.055718 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8865 00:25:01.058692 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8866 00:25:01.062324 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8867 00:25:01.068980 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8868 00:25:01.072578 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8869 00:25:01.075444 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8870 00:25:01.082373 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8871 00:25:01.085232 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8872 00:25:01.088698 Total UI for P1: 0, mck2ui 16
8873 00:25:01.091837 best dqsien dly found for B1: ( 1, 9, 8)
8874 00:25:01.095542 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8875 00:25:01.098791 Total UI for P1: 0, mck2ui 16
8876 00:25:01.102250 best dqsien dly found for B0: ( 1, 9, 10)
8877 00:25:01.105356 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8878 00:25:01.108861 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8879 00:25:01.108961
8880 00:25:01.115496 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8881 00:25:01.118849 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8882 00:25:01.121926 [Gating] SW calibration Done
8883 00:25:01.122003 ==
8884 00:25:01.125132 Dram Type= 6, Freq= 0, CH_1, rank 1
8885 00:25:01.128679 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8886 00:25:01.128832 ==
8887 00:25:01.128919 RX Vref Scan: 0
8888 00:25:01.128977
8889 00:25:01.131727 RX Vref 0 -> 0, step: 1
8890 00:25:01.131818
8891 00:25:01.135176 RX Delay 0 -> 252, step: 8
8892 00:25:01.138870 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8893 00:25:01.142041 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8894 00:25:01.145059 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8895 00:25:01.151962 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8896 00:25:01.155387 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8897 00:25:01.158466 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8898 00:25:01.162072 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8899 00:25:01.164893 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
8900 00:25:01.172013 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8901 00:25:01.175083 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8902 00:25:01.178327 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8903 00:25:01.181745 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8904 00:25:01.185301 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8905 00:25:01.192130 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8906 00:25:01.195190 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8907 00:25:01.198688 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8908 00:25:01.198765 ==
8909 00:25:01.201789 Dram Type= 6, Freq= 0, CH_1, rank 1
8910 00:25:01.205388 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8911 00:25:01.205466 ==
8912 00:25:01.208513 DQS Delay:
8913 00:25:01.208590 DQS0 = 0, DQS1 = 0
8914 00:25:01.211940 DQM Delay:
8915 00:25:01.212017 DQM0 = 137, DQM1 = 133
8916 00:25:01.212077 DQ Delay:
8917 00:25:01.218120 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8918 00:25:01.221417 DQ4 =135, DQ5 =147, DQ6 =143, DQ7 =139
8919 00:25:01.225184 DQ8 =115, DQ9 =119, DQ10 =135, DQ11 =127
8920 00:25:01.228160 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8921 00:25:01.228274
8922 00:25:01.228360
8923 00:25:01.228440 ==
8924 00:25:01.231570 Dram Type= 6, Freq= 0, CH_1, rank 1
8925 00:25:01.234833 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8926 00:25:01.234926 ==
8927 00:25:01.234988
8928 00:25:01.235058
8929 00:25:01.238099 TX Vref Scan disable
8930 00:25:01.241561 == TX Byte 0 ==
8931 00:25:01.244929 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8932 00:25:01.248238 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8933 00:25:01.251523 == TX Byte 1 ==
8934 00:25:01.254676 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8935 00:25:01.258204 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8936 00:25:01.258278 ==
8937 00:25:01.261569 Dram Type= 6, Freq= 0, CH_1, rank 1
8938 00:25:01.264559 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8939 00:25:01.267841 ==
8940 00:25:01.280200
8941 00:25:01.283672 TX Vref early break, caculate TX vref
8942 00:25:01.287229 TX Vref=16, minBit 9, minWin=23, winSum=388
8943 00:25:01.290524 TX Vref=18, minBit 12, minWin=23, winSum=396
8944 00:25:01.293775 TX Vref=20, minBit 9, minWin=24, winSum=406
8945 00:25:01.296851 TX Vref=22, minBit 9, minWin=24, winSum=415
8946 00:25:01.300412 TX Vref=24, minBit 12, minWin=25, winSum=421
8947 00:25:01.306824 TX Vref=26, minBit 9, minWin=25, winSum=422
8948 00:25:01.310350 TX Vref=28, minBit 15, minWin=25, winSum=425
8949 00:25:01.313529 TX Vref=30, minBit 0, minWin=25, winSum=418
8950 00:25:01.317011 TX Vref=32, minBit 2, minWin=25, winSum=415
8951 00:25:01.320085 TX Vref=34, minBit 0, minWin=24, winSum=405
8952 00:25:01.326971 TX Vref=36, minBit 10, minWin=23, winSum=394
8953 00:25:01.330369 [TxChooseVref] Worse bit 15, Min win 25, Win sum 425, Final Vref 28
8954 00:25:01.330447
8955 00:25:01.333425 Final TX Range 0 Vref 28
8956 00:25:01.333519
8957 00:25:01.333610 ==
8958 00:25:01.337053 Dram Type= 6, Freq= 0, CH_1, rank 1
8959 00:25:01.339924 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8960 00:25:01.340003 ==
8961 00:25:01.343436
8962 00:25:01.343512
8963 00:25:01.343572 TX Vref Scan disable
8964 00:25:01.349850 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8965 00:25:01.349942 == TX Byte 0 ==
8966 00:25:01.353518 u2DelayCellOfst[0]=13 cells (4 PI)
8967 00:25:01.356852 u2DelayCellOfst[1]=10 cells (3 PI)
8968 00:25:01.359981 u2DelayCellOfst[2]=0 cells (0 PI)
8969 00:25:01.363363 u2DelayCellOfst[3]=3 cells (1 PI)
8970 00:25:01.366643 u2DelayCellOfst[4]=6 cells (2 PI)
8971 00:25:01.370121 u2DelayCellOfst[5]=16 cells (5 PI)
8972 00:25:01.373363 u2DelayCellOfst[6]=16 cells (5 PI)
8973 00:25:01.376781 u2DelayCellOfst[7]=3 cells (1 PI)
8974 00:25:01.379885 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8975 00:25:01.383471 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8976 00:25:01.386471 == TX Byte 1 ==
8977 00:25:01.389879 u2DelayCellOfst[8]=0 cells (0 PI)
8978 00:25:01.393424 u2DelayCellOfst[9]=3 cells (1 PI)
8979 00:25:01.396374 u2DelayCellOfst[10]=10 cells (3 PI)
8980 00:25:01.396452 u2DelayCellOfst[11]=3 cells (1 PI)
8981 00:25:01.400059 u2DelayCellOfst[12]=13 cells (4 PI)
8982 00:25:01.403558 u2DelayCellOfst[13]=16 cells (5 PI)
8983 00:25:01.406551 u2DelayCellOfst[14]=20 cells (6 PI)
8984 00:25:01.410085 u2DelayCellOfst[15]=20 cells (6 PI)
8985 00:25:01.416367 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8986 00:25:01.419943 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8987 00:25:01.420021 DramC Write-DBI on
8988 00:25:01.420081 ==
8989 00:25:01.423005 Dram Type= 6, Freq= 0, CH_1, rank 1
8990 00:25:01.429720 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8991 00:25:01.429799 ==
8992 00:25:01.429859
8993 00:25:01.429914
8994 00:25:01.429966 TX Vref Scan disable
8995 00:25:01.433845 == TX Byte 0 ==
8996 00:25:01.437266 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8997 00:25:01.440433 == TX Byte 1 ==
8998 00:25:01.444030 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8999 00:25:01.447069 DramC Write-DBI off
9000 00:25:01.447146
9001 00:25:01.447206 [DATLAT]
9002 00:25:01.447261 Freq=1600, CH1 RK1
9003 00:25:01.447314
9004 00:25:01.450574 DATLAT Default: 0xf
9005 00:25:01.450651 0, 0xFFFF, sum = 0
9006 00:25:01.453620 1, 0xFFFF, sum = 0
9007 00:25:01.453699 2, 0xFFFF, sum = 0
9008 00:25:01.457115 3, 0xFFFF, sum = 0
9009 00:25:01.460390 4, 0xFFFF, sum = 0
9010 00:25:01.460468 5, 0xFFFF, sum = 0
9011 00:25:01.463895 6, 0xFFFF, sum = 0
9012 00:25:01.463974 7, 0xFFFF, sum = 0
9013 00:25:01.467426 8, 0xFFFF, sum = 0
9014 00:25:01.467522 9, 0xFFFF, sum = 0
9015 00:25:01.470773 10, 0xFFFF, sum = 0
9016 00:25:01.470851 11, 0xFFFF, sum = 0
9017 00:25:01.473710 12, 0xFFFF, sum = 0
9018 00:25:01.473788 13, 0xFFFF, sum = 0
9019 00:25:01.477307 14, 0x0, sum = 1
9020 00:25:01.477386 15, 0x0, sum = 2
9021 00:25:01.480599 16, 0x0, sum = 3
9022 00:25:01.480679 17, 0x0, sum = 4
9023 00:25:01.483683 best_step = 15
9024 00:25:01.483759
9025 00:25:01.483818 ==
9026 00:25:01.486927 Dram Type= 6, Freq= 0, CH_1, rank 1
9027 00:25:01.490273 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9028 00:25:01.490351 ==
9029 00:25:01.490410 RX Vref Scan: 0
9030 00:25:01.493912
9031 00:25:01.493989 RX Vref 0 -> 0, step: 1
9032 00:25:01.494048
9033 00:25:01.497241 RX Delay 19 -> 252, step: 4
9034 00:25:01.500144 iDelay=195, Bit 0, Center 136 (95 ~ 178) 84
9035 00:25:01.506824 iDelay=195, Bit 1, Center 130 (87 ~ 174) 88
9036 00:25:01.510289 iDelay=195, Bit 2, Center 118 (71 ~ 166) 96
9037 00:25:01.513419 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
9038 00:25:01.517046 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
9039 00:25:01.520050 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
9040 00:25:01.523698 iDelay=195, Bit 6, Center 142 (95 ~ 190) 96
9041 00:25:01.530443 iDelay=195, Bit 7, Center 130 (83 ~ 178) 96
9042 00:25:01.533320 iDelay=195, Bit 8, Center 114 (67 ~ 162) 96
9043 00:25:01.537013 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
9044 00:25:01.540015 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
9045 00:25:01.543470 iDelay=195, Bit 11, Center 126 (75 ~ 178) 104
9046 00:25:01.550288 iDelay=195, Bit 12, Center 140 (91 ~ 190) 100
9047 00:25:01.553561 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9048 00:25:01.556851 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
9049 00:25:01.560509 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
9050 00:25:01.560586 ==
9051 00:25:01.563625 Dram Type= 6, Freq= 0, CH_1, rank 1
9052 00:25:01.570120 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9053 00:25:01.570200 ==
9054 00:25:01.570263 DQS Delay:
9055 00:25:01.570320 DQS0 = 0, DQS1 = 0
9056 00:25:01.573714 DQM Delay:
9057 00:25:01.573791 DQM0 = 133, DQM1 = 130
9058 00:25:01.576617 DQ Delay:
9059 00:25:01.580109 DQ0 =136, DQ1 =130, DQ2 =118, DQ3 =130
9060 00:25:01.583509 DQ4 =134, DQ5 =146, DQ6 =142, DQ7 =130
9061 00:25:01.586759 DQ8 =114, DQ9 =118, DQ10 =130, DQ11 =126
9062 00:25:01.590320 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =138
9063 00:25:01.590413
9064 00:25:01.590473
9065 00:25:01.590527
9066 00:25:01.593273 [DramC_TX_OE_Calibration] TA2
9067 00:25:01.596849 Original DQ_B0 (3 6) =30, OEN = 27
9068 00:25:01.600000 Original DQ_B1 (3 6) =30, OEN = 27
9069 00:25:01.603416 24, 0x0, End_B0=24 End_B1=24
9070 00:25:01.603495 25, 0x0, End_B0=25 End_B1=25
9071 00:25:01.606766 26, 0x0, End_B0=26 End_B1=26
9072 00:25:01.610033 27, 0x0, End_B0=27 End_B1=27
9073 00:25:01.613305 28, 0x0, End_B0=28 End_B1=28
9074 00:25:01.613384 29, 0x0, End_B0=29 End_B1=29
9075 00:25:01.616885 30, 0x0, End_B0=30 End_B1=30
9076 00:25:01.620225 31, 0x4141, End_B0=30 End_B1=30
9077 00:25:01.623316 Byte0 end_step=30 best_step=27
9078 00:25:01.626948 Byte1 end_step=30 best_step=27
9079 00:25:01.630012 Byte0 TX OE(2T, 0.5T) = (3, 3)
9080 00:25:01.630090 Byte1 TX OE(2T, 0.5T) = (3, 3)
9081 00:25:01.630150
9082 00:25:01.633638
9083 00:25:01.640246 [DQSOSCAuto] RK1, (LSB)MR18= 0x1b06, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 396 ps
9084 00:25:01.643322 CH1 RK1: MR19=303, MR18=1B06
9085 00:25:01.650286 CH1_RK1: MR19=0x303, MR18=0x1B06, DQSOSC=396, MR23=63, INC=23, DEC=15
9086 00:25:01.653491 [RxdqsGatingPostProcess] freq 1600
9087 00:25:01.656794 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9088 00:25:01.660185 best DQS0 dly(2T, 0.5T) = (1, 1)
9089 00:25:01.663435 best DQS1 dly(2T, 0.5T) = (1, 1)
9090 00:25:01.666933 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9091 00:25:01.669989 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9092 00:25:01.673687 best DQS0 dly(2T, 0.5T) = (1, 1)
9093 00:25:01.677083 best DQS1 dly(2T, 0.5T) = (1, 1)
9094 00:25:01.680155 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9095 00:25:01.683572 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9096 00:25:01.683651 Pre-setting of DQS Precalculation
9097 00:25:01.690456 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9098 00:25:01.696922 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9099 00:25:01.703241 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9100 00:25:01.703332
9101 00:25:01.703405
9102 00:25:01.706702 [Calibration Summary] 3200 Mbps
9103 00:25:01.710011 CH 0, Rank 0
9104 00:25:01.710078 SW Impedance : PASS
9105 00:25:01.713564 DUTY Scan : NO K
9106 00:25:01.716791 ZQ Calibration : PASS
9107 00:25:01.716860 Jitter Meter : NO K
9108 00:25:01.719931 CBT Training : PASS
9109 00:25:01.723116 Write leveling : PASS
9110 00:25:01.723182 RX DQS gating : PASS
9111 00:25:01.726588 RX DQ/DQS(RDDQC) : PASS
9112 00:25:01.726663 TX DQ/DQS : PASS
9113 00:25:01.729804 RX DATLAT : PASS
9114 00:25:01.733272 RX DQ/DQS(Engine): PASS
9115 00:25:01.733343 TX OE : PASS
9116 00:25:01.736864 All Pass.
9117 00:25:01.736934
9118 00:25:01.737006 CH 0, Rank 1
9119 00:25:01.740051 SW Impedance : PASS
9120 00:25:01.740119 DUTY Scan : NO K
9121 00:25:01.743498 ZQ Calibration : PASS
9122 00:25:01.746721 Jitter Meter : NO K
9123 00:25:01.746797 CBT Training : PASS
9124 00:25:01.750221 Write leveling : PASS
9125 00:25:01.753235 RX DQS gating : PASS
9126 00:25:01.753306 RX DQ/DQS(RDDQC) : PASS
9127 00:25:01.756911 TX DQ/DQS : PASS
9128 00:25:01.759952 RX DATLAT : PASS
9129 00:25:01.760023 RX DQ/DQS(Engine): PASS
9130 00:25:01.763750 TX OE : PASS
9131 00:25:01.763845 All Pass.
9132 00:25:01.763919
9133 00:25:01.766701 CH 1, Rank 0
9134 00:25:01.766769 SW Impedance : PASS
9135 00:25:01.769890 DUTY Scan : NO K
9136 00:25:01.769961 ZQ Calibration : PASS
9137 00:25:01.773050 Jitter Meter : NO K
9138 00:25:01.776605 CBT Training : PASS
9139 00:25:01.776676 Write leveling : PASS
9140 00:25:01.780172 RX DQS gating : PASS
9141 00:25:01.783162 RX DQ/DQS(RDDQC) : PASS
9142 00:25:01.783232 TX DQ/DQS : PASS
9143 00:25:01.786485 RX DATLAT : PASS
9144 00:25:01.789783 RX DQ/DQS(Engine): PASS
9145 00:25:01.789879 TX OE : PASS
9146 00:25:01.792903 All Pass.
9147 00:25:01.792975
9148 00:25:01.793047 CH 1, Rank 1
9149 00:25:01.796737 SW Impedance : PASS
9150 00:25:01.796841 DUTY Scan : NO K
9151 00:25:01.799813 ZQ Calibration : PASS
9152 00:25:01.803201 Jitter Meter : NO K
9153 00:25:01.803270 CBT Training : PASS
9154 00:25:01.806725 Write leveling : PASS
9155 00:25:01.809869 RX DQS gating : PASS
9156 00:25:01.809937 RX DQ/DQS(RDDQC) : PASS
9157 00:25:01.813132 TX DQ/DQS : PASS
9158 00:25:01.816273 RX DATLAT : PASS
9159 00:25:01.816345 RX DQ/DQS(Engine): PASS
9160 00:25:01.820343 TX OE : PASS
9161 00:25:01.820415 All Pass.
9162 00:25:01.820488
9163 00:25:01.822861 DramC Write-DBI on
9164 00:25:01.826466 PER_BANK_REFRESH: Hybrid Mode
9165 00:25:01.826541 TX_TRACKING: ON
9166 00:25:01.836163 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9167 00:25:01.842735 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9168 00:25:01.849780 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9169 00:25:01.852894 [FAST_K] Save calibration result to emmc
9170 00:25:01.855970 sync common calibartion params.
9171 00:25:01.859685 sync cbt_mode0:1, 1:1
9172 00:25:01.862713 dram_init: ddr_geometry: 2
9173 00:25:01.862785 dram_init: ddr_geometry: 2
9174 00:25:01.866236 dram_init: ddr_geometry: 2
9175 00:25:01.869274 0:dram_rank_size:100000000
9176 00:25:01.869347 1:dram_rank_size:100000000
9177 00:25:01.876288 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9178 00:25:01.879505 DFS_SHUFFLE_HW_MODE: ON
9179 00:25:01.883047 dramc_set_vcore_voltage set vcore to 725000
9180 00:25:01.886030 Read voltage for 1600, 0
9181 00:25:01.886114 Vio18 = 0
9182 00:25:01.886188 Vcore = 725000
9183 00:25:01.889660 Vdram = 0
9184 00:25:01.889742 Vddq = 0
9185 00:25:01.889811 Vmddr = 0
9186 00:25:01.892800 switch to 3200 Mbps bootup
9187 00:25:01.892867 [DramcRunTimeConfig]
9188 00:25:01.896296 PHYPLL
9189 00:25:01.896362 DPM_CONTROL_AFTERK: ON
9190 00:25:01.899532 PER_BANK_REFRESH: ON
9191 00:25:01.902590 REFRESH_OVERHEAD_REDUCTION: ON
9192 00:25:01.902660 CMD_PICG_NEW_MODE: OFF
9193 00:25:01.905856 XRTWTW_NEW_MODE: ON
9194 00:25:01.905952 XRTRTR_NEW_MODE: ON
9195 00:25:01.909157 TX_TRACKING: ON
9196 00:25:01.909239 RDSEL_TRACKING: OFF
9197 00:25:01.912539 DQS Precalculation for DVFS: ON
9198 00:25:01.915962 RX_TRACKING: OFF
9199 00:25:01.916059 HW_GATING DBG: ON
9200 00:25:01.919309 ZQCS_ENABLE_LP4: ON
9201 00:25:01.919420 RX_PICG_NEW_MODE: ON
9202 00:25:01.922361 TX_PICG_NEW_MODE: ON
9203 00:25:01.922446 ENABLE_RX_DCM_DPHY: ON
9204 00:25:01.925940 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9205 00:25:01.929229 DUMMY_READ_FOR_TRACKING: OFF
9206 00:25:01.932617 !!! SPM_CONTROL_AFTERK: OFF
9207 00:25:01.936172 !!! SPM could not control APHY
9208 00:25:01.936267 IMPEDANCE_TRACKING: ON
9209 00:25:01.939557 TEMP_SENSOR: ON
9210 00:25:01.939659 HW_SAVE_FOR_SR: OFF
9211 00:25:01.942733 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9212 00:25:01.945807 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9213 00:25:01.949236 Read ODT Tracking: ON
9214 00:25:01.952644 Refresh Rate DeBounce: ON
9215 00:25:01.952756 DFS_NO_QUEUE_FLUSH: ON
9216 00:25:01.955646 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9217 00:25:01.959283 ENABLE_DFS_RUNTIME_MRW: OFF
9218 00:25:01.962547 DDR_RESERVE_NEW_MODE: ON
9219 00:25:01.962636 MR_CBT_SWITCH_FREQ: ON
9220 00:25:01.965857 =========================
9221 00:25:01.984523 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9222 00:25:01.988088 dram_init: ddr_geometry: 2
9223 00:25:02.006304 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9224 00:25:02.009581 dram_init: dram init end (result: 0)
9225 00:25:02.016287 DRAM-K: Full calibration passed in 24524 msecs
9226 00:25:02.019459 MRC: failed to locate region type 0.
9227 00:25:02.019536 DRAM rank0 size:0x100000000,
9228 00:25:02.022888 DRAM rank1 size=0x100000000
9229 00:25:02.032784 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9230 00:25:02.039454 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9231 00:25:02.045815 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9232 00:25:02.052631 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9233 00:25:02.056027 DRAM rank0 size:0x100000000,
9234 00:25:02.059487 DRAM rank1 size=0x100000000
9235 00:25:02.059562 CBMEM:
9236 00:25:02.062511 IMD: root @ 0xfffff000 254 entries.
9237 00:25:02.066018 IMD: root @ 0xffffec00 62 entries.
9238 00:25:02.069150 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9239 00:25:02.072253 WARNING: RO_VPD is uninitialized or empty.
9240 00:25:02.078776 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9241 00:25:02.086474 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9242 00:25:02.099029 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9243 00:25:02.110269 BS: romstage times (exec / console): total (unknown) / 24018 ms
9244 00:25:02.110347
9245 00:25:02.110422
9246 00:25:02.120309 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9247 00:25:02.123727 ARM64: Exception handlers installed.
9248 00:25:02.127282 ARM64: Testing exception
9249 00:25:02.130047 ARM64: Done test exception
9250 00:25:02.130137 Enumerating buses...
9251 00:25:02.133450 Show all devs... Before device enumeration.
9252 00:25:02.136880 Root Device: enabled 1
9253 00:25:02.139960 CPU_CLUSTER: 0: enabled 1
9254 00:25:02.140043 CPU: 00: enabled 1
9255 00:25:02.143500 Compare with tree...
9256 00:25:02.143595 Root Device: enabled 1
9257 00:25:02.146696 CPU_CLUSTER: 0: enabled 1
9258 00:25:02.150143 CPU: 00: enabled 1
9259 00:25:02.150231 Root Device scanning...
9260 00:25:02.153636 scan_static_bus for Root Device
9261 00:25:02.157261 CPU_CLUSTER: 0 enabled
9262 00:25:02.160314 scan_static_bus for Root Device done
9263 00:25:02.163655 scan_bus: bus Root Device finished in 8 msecs
9264 00:25:02.163733 done
9265 00:25:02.170302 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9266 00:25:02.173587 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9267 00:25:02.180299 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9268 00:25:02.183758 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9269 00:25:02.186776 Allocating resources...
9270 00:25:02.189906 Reading resources...
9271 00:25:02.193482 Root Device read_resources bus 0 link: 0
9272 00:25:02.193560 DRAM rank0 size:0x100000000,
9273 00:25:02.197036 DRAM rank1 size=0x100000000
9274 00:25:02.200008 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9275 00:25:02.203271 CPU: 00 missing read_resources
9276 00:25:02.206675 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9277 00:25:02.213559 Root Device read_resources bus 0 link: 0 done
9278 00:25:02.213654 Done reading resources.
9279 00:25:02.219863 Show resources in subtree (Root Device)...After reading.
9280 00:25:02.223317 Root Device child on link 0 CPU_CLUSTER: 0
9281 00:25:02.226735 CPU_CLUSTER: 0 child on link 0 CPU: 00
9282 00:25:02.236896 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9283 00:25:02.236984 CPU: 00
9284 00:25:02.240102 Root Device assign_resources, bus 0 link: 0
9285 00:25:02.243549 CPU_CLUSTER: 0 missing set_resources
9286 00:25:02.246531 Root Device assign_resources, bus 0 link: 0 done
9287 00:25:02.250054 Done setting resources.
9288 00:25:02.256656 Show resources in subtree (Root Device)...After assigning values.
9289 00:25:02.260057 Root Device child on link 0 CPU_CLUSTER: 0
9290 00:25:02.263218 CPU_CLUSTER: 0 child on link 0 CPU: 00
9291 00:25:02.273275 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9292 00:25:02.273354 CPU: 00
9293 00:25:02.276687 Done allocating resources.
9294 00:25:02.280009 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9295 00:25:02.283252 Enabling resources...
9296 00:25:02.283345 done.
9297 00:25:02.289915 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9298 00:25:02.290049 Initializing devices...
9299 00:25:02.292926 Root Device init
9300 00:25:02.293003 init hardware done!
9301 00:25:02.296717 0x00000018: ctrlr->caps
9302 00:25:02.299610 52.000 MHz: ctrlr->f_max
9303 00:25:02.299691 0.400 MHz: ctrlr->f_min
9304 00:25:02.302793 0x40ff8080: ctrlr->voltages
9305 00:25:02.302874 sclk: 390625
9306 00:25:02.306603 Bus Width = 1
9307 00:25:02.306682 sclk: 390625
9308 00:25:02.309833 Bus Width = 1
9309 00:25:02.309912 Early init status = 3
9310 00:25:02.316361 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9311 00:25:02.319604 in-header: 03 fc 00 00 01 00 00 00
9312 00:25:02.319709 in-data: 00
9313 00:25:02.326179 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9314 00:25:02.329287 in-header: 03 fd 00 00 00 00 00 00
9315 00:25:02.332597 in-data:
9316 00:25:02.335915 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9317 00:25:02.339554 in-header: 03 fc 00 00 01 00 00 00
9318 00:25:02.342941 in-data: 00
9319 00:25:02.345855 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9320 00:25:02.350850 in-header: 03 fd 00 00 00 00 00 00
9321 00:25:02.354205 in-data:
9322 00:25:02.357925 [SSUSB] Setting up USB HOST controller...
9323 00:25:02.360675 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9324 00:25:02.364048 [SSUSB] phy power-on done.
9325 00:25:02.367455 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9326 00:25:02.374514 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9327 00:25:02.377641 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9328 00:25:02.384278 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9329 00:25:02.390893 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9330 00:25:02.397451 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9331 00:25:02.404070 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9332 00:25:02.410854 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9333 00:25:02.414196 SPM: binary array size = 0x9dc
9334 00:25:02.417577 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9335 00:25:02.423800 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9336 00:25:02.430985 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9337 00:25:02.434066 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9338 00:25:02.440698 configure_display: Starting display init
9339 00:25:02.474169 anx7625_power_on_init: Init interface.
9340 00:25:02.477634 anx7625_disable_pd_protocol: Disabled PD feature.
9341 00:25:02.480662 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9342 00:25:02.508646 anx7625_start_dp_work: Secure OCM version=00
9343 00:25:02.511871 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9344 00:25:02.526634 sp_tx_get_edid_block: EDID Block = 1
9345 00:25:02.629163 Extracted contents:
9346 00:25:02.632863 header: 00 ff ff ff ff ff ff 00
9347 00:25:02.635770 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9348 00:25:02.639055 version: 01 04
9349 00:25:02.642660 basic params: 95 1f 11 78 0a
9350 00:25:02.645682 chroma info: 76 90 94 55 54 90 27 21 50 54
9351 00:25:02.649179 established: 00 00 00
9352 00:25:02.656049 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9353 00:25:02.659461 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9354 00:25:02.666057 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9355 00:25:02.672130 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9356 00:25:02.678615 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9357 00:25:02.682111 extensions: 00
9358 00:25:02.682190 checksum: fb
9359 00:25:02.682251
9360 00:25:02.685340 Manufacturer: IVO Model 57d Serial Number 0
9361 00:25:02.688701 Made week 0 of 2020
9362 00:25:02.692237 EDID version: 1.4
9363 00:25:02.692338 Digital display
9364 00:25:02.695345 6 bits per primary color channel
9365 00:25:02.695419 DisplayPort interface
9366 00:25:02.698966 Maximum image size: 31 cm x 17 cm
9367 00:25:02.702040 Gamma: 220%
9368 00:25:02.702119 Check DPMS levels
9369 00:25:02.705467 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9370 00:25:02.712245 First detailed timing is preferred timing
9371 00:25:02.712324 Established timings supported:
9372 00:25:02.715003 Standard timings supported:
9373 00:25:02.718619 Detailed timings
9374 00:25:02.721819 Hex of detail: 383680a07038204018303c0035ae10000019
9375 00:25:02.728434 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9376 00:25:02.731973 0780 0798 07c8 0820 hborder 0
9377 00:25:02.735513 0438 043b 0447 0458 vborder 0
9378 00:25:02.738479 -hsync -vsync
9379 00:25:02.738581 Did detailed timing
9380 00:25:02.745089 Hex of detail: 000000000000000000000000000000000000
9381 00:25:02.748518 Manufacturer-specified data, tag 0
9382 00:25:02.751872 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9383 00:25:02.754917 ASCII string: InfoVision
9384 00:25:02.758372 Hex of detail: 000000fe00523134304e574635205248200a
9385 00:25:02.761910 ASCII string: R140NWF5 RH
9386 00:25:02.761978 Checksum
9387 00:25:02.765045 Checksum: 0xfb (valid)
9388 00:25:02.768718 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9389 00:25:02.771549 DSI data_rate: 832800000 bps
9390 00:25:02.778246 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9391 00:25:02.781837 anx7625_parse_edid: pixelclock(138800).
9392 00:25:02.785239 hactive(1920), hsync(48), hfp(24), hbp(88)
9393 00:25:02.788194 vactive(1080), vsync(12), vfp(3), vbp(17)
9394 00:25:02.791659 anx7625_dsi_config: config dsi.
9395 00:25:02.798184 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9396 00:25:02.811289 anx7625_dsi_config: success to config DSI
9397 00:25:02.814748 anx7625_dp_start: MIPI phy setup OK.
9398 00:25:02.818229 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9399 00:25:02.821088 mtk_ddp_mode_set invalid vrefresh 60
9400 00:25:02.824649 main_disp_path_setup
9401 00:25:02.824740 ovl_layer_smi_id_en
9402 00:25:02.828284 ovl_layer_smi_id_en
9403 00:25:02.828374 ccorr_config
9404 00:25:02.828455 aal_config
9405 00:25:02.831328 gamma_config
9406 00:25:02.831429 postmask_config
9407 00:25:02.834984 dither_config
9408 00:25:02.837919 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9409 00:25:02.844351 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9410 00:25:02.847813 Root Device init finished in 552 msecs
9411 00:25:02.847910 CPU_CLUSTER: 0 init
9412 00:25:02.857903 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9413 00:25:02.861068 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9414 00:25:02.864620 APU_MBOX 0x190000b0 = 0x10001
9415 00:25:02.867759 APU_MBOX 0x190001b0 = 0x10001
9416 00:25:02.871229 APU_MBOX 0x190005b0 = 0x10001
9417 00:25:02.874239 APU_MBOX 0x190006b0 = 0x10001
9418 00:25:02.877964 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9419 00:25:02.890265 read SPI 0x539f4 0xe237: 6246 us, 9271 KB/s, 74.168 Mbps
9420 00:25:02.902658 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9421 00:25:02.909583 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9422 00:25:02.920866 read SPI 0x61c74 0xe8ef: 6411 us, 9301 KB/s, 74.408 Mbps
9423 00:25:02.929929 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9424 00:25:02.933591 CPU_CLUSTER: 0 init finished in 81 msecs
9425 00:25:02.936693 Devices initialized
9426 00:25:02.940251 Show all devs... After init.
9427 00:25:02.940353 Root Device: enabled 1
9428 00:25:02.943296 CPU_CLUSTER: 0: enabled 1
9429 00:25:02.946896 CPU: 00: enabled 1
9430 00:25:02.950487 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9431 00:25:02.953333 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9432 00:25:02.957022 ELOG: NV offset 0x57f000 size 0x1000
9433 00:25:02.963271 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9434 00:25:02.970361 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9435 00:25:02.973498 ELOG: Event(17) added with size 13 at 2024-06-21 00:25:02 UTC
9436 00:25:02.976955 out: cmd=0x121: 03 db 21 01 00 00 00 00
9437 00:25:02.980472 in-header: 03 55 00 00 2c 00 00 00
9438 00:25:02.993639 in-data: ea 70 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9439 00:25:03.000350 ELOG: Event(A1) added with size 10 at 2024-06-21 00:25:02 UTC
9440 00:25:03.007097 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9441 00:25:03.013559 ELOG: Event(A0) added with size 9 at 2024-06-21 00:25:02 UTC
9442 00:25:03.017001 elog_add_boot_reason: Logged dev mode boot
9443 00:25:03.020209 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9444 00:25:03.023722 Finalize devices...
9445 00:25:03.023819 Devices finalized
9446 00:25:03.030239 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9447 00:25:03.033812 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9448 00:25:03.036938 in-header: 03 07 00 00 08 00 00 00
9449 00:25:03.039975 in-data: aa e4 47 04 13 02 00 00
9450 00:25:03.043452 Chrome EC: UHEPI supported
9451 00:25:03.050077 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9452 00:25:03.053326 in-header: 03 a9 00 00 08 00 00 00
9453 00:25:03.056773 in-data: 84 60 60 08 00 00 00 00
9454 00:25:03.063482 ELOG: Event(91) added with size 10 at 2024-06-21 00:25:02 UTC
9455 00:25:03.066463 Chrome EC: clear events_b mask to 0x0000000020004000
9456 00:25:03.073252 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9457 00:25:03.078010 in-header: 03 fd 00 00 00 00 00 00
9458 00:25:03.081085 in-data:
9459 00:25:03.084898 BS: BS_WRITE_TABLES entry times (exec / console): 4 / 46 ms
9460 00:25:03.087883 Writing coreboot table at 0xffe64000
9461 00:25:03.091272 0. 000000000010a000-0000000000113fff: RAMSTAGE
9462 00:25:03.097957 1. 0000000040000000-00000000400fffff: RAM
9463 00:25:03.101017 2. 0000000040100000-000000004032afff: RAMSTAGE
9464 00:25:03.104560 3. 000000004032b000-00000000545fffff: RAM
9465 00:25:03.108002 4. 0000000054600000-000000005465ffff: BL31
9466 00:25:03.110868 5. 0000000054660000-00000000ffe63fff: RAM
9467 00:25:03.117579 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9468 00:25:03.121070 7. 0000000100000000-000000023fffffff: RAM
9469 00:25:03.124126 Passing 5 GPIOs to payload:
9470 00:25:03.127572 NAME | PORT | POLARITY | VALUE
9471 00:25:03.134585 EC in RW | 0x000000aa | low | undefined
9472 00:25:03.137623 EC interrupt | 0x00000005 | low | undefined
9473 00:25:03.141143 TPM interrupt | 0x000000ab | high | undefined
9474 00:25:03.147457 SD card detect | 0x00000011 | high | undefined
9475 00:25:03.150968 speaker enable | 0x00000093 | high | undefined
9476 00:25:03.154217 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9477 00:25:03.157421 in-header: 03 f9 00 00 02 00 00 00
9478 00:25:03.160946 in-data: 02 00
9479 00:25:03.164440 ADC[4]: Raw value=901401 ID=7
9480 00:25:03.164509 ADC[3]: Raw value=213179 ID=1
9481 00:25:03.167419 RAM Code: 0x71
9482 00:25:03.170727 ADC[6]: Raw value=74502 ID=0
9483 00:25:03.170831 ADC[5]: Raw value=212441 ID=1
9484 00:25:03.174309 SKU Code: 0x1
9485 00:25:03.177319 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 7ff2
9486 00:25:03.180922 coreboot table: 964 bytes.
9487 00:25:03.183979 IMD ROOT 0. 0xfffff000 0x00001000
9488 00:25:03.187513 IMD SMALL 1. 0xffffe000 0x00001000
9489 00:25:03.190588 RO MCACHE 2. 0xffffc000 0x00001104
9490 00:25:03.194265 CONSOLE 3. 0xfff7c000 0x00080000
9491 00:25:03.197298 FMAP 4. 0xfff7b000 0x00000452
9492 00:25:03.200894 TIME STAMP 5. 0xfff7a000 0x00000910
9493 00:25:03.203936 VBOOT WORK 6. 0xfff66000 0x00014000
9494 00:25:03.207370 RAMOOPS 7. 0xffe66000 0x00100000
9495 00:25:03.210506 COREBOOT 8. 0xffe64000 0x00002000
9496 00:25:03.213920 IMD small region:
9497 00:25:03.217505 IMD ROOT 0. 0xffffec00 0x00000400
9498 00:25:03.220556 VPD 1. 0xffffeb80 0x0000006c
9499 00:25:03.224059 MMC STATUS 2. 0xffffeb60 0x00000004
9500 00:25:03.227062 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9501 00:25:03.233911 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9502 00:25:03.274516 read SPI 0x3990ec 0x4f1b0: 34846 us, 9298 KB/s, 74.384 Mbps
9503 00:25:03.277880 Checking segment from ROM address 0x40100000
9504 00:25:03.281011 Checking segment from ROM address 0x4010001c
9505 00:25:03.287571 Loading segment from ROM address 0x40100000
9506 00:25:03.287645 code (compression=0)
9507 00:25:03.297877 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9508 00:25:03.304445 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9509 00:25:03.304518 it's not compressed!
9510 00:25:03.311185 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9511 00:25:03.314316 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9512 00:25:03.334727 Loading segment from ROM address 0x4010001c
9513 00:25:03.334800 Entry Point 0x80000000
9514 00:25:03.338234 Loaded segments
9515 00:25:03.341633 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9516 00:25:03.348254 Jumping to boot code at 0x80000000(0xffe64000)
9517 00:25:03.354840 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9518 00:25:03.361594 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9519 00:25:03.369090 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9520 00:25:03.372716 Checking segment from ROM address 0x40100000
9521 00:25:03.376031 Checking segment from ROM address 0x4010001c
9522 00:25:03.382276 Loading segment from ROM address 0x40100000
9523 00:25:03.382375 code (compression=1)
9524 00:25:03.389310 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9525 00:25:03.399196 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9526 00:25:03.399270 using LZMA
9527 00:25:03.407879 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9528 00:25:03.414424 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9529 00:25:03.418036 Loading segment from ROM address 0x4010001c
9530 00:25:03.418107 Entry Point 0x54601000
9531 00:25:03.420985 Loaded segments
9532 00:25:03.424569 NOTICE: MT8192 bl31_setup
9533 00:25:03.431019 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9534 00:25:03.434545 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9535 00:25:03.437860 WARNING: region 0:
9536 00:25:03.440880 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9537 00:25:03.440950 WARNING: region 1:
9538 00:25:03.448204 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9539 00:25:03.451313 WARNING: region 2:
9540 00:25:03.454437 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9541 00:25:03.458138 WARNING: region 3:
9542 00:25:03.461554 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9543 00:25:03.464514 WARNING: region 4:
9544 00:25:03.471298 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9545 00:25:03.471383 WARNING: region 5:
9546 00:25:03.474716 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9547 00:25:03.478036 WARNING: region 6:
9548 00:25:03.481335 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9549 00:25:03.484366 WARNING: region 7:
9550 00:25:03.487678 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9551 00:25:03.494181 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9552 00:25:03.497779 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9553 00:25:03.500884 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9554 00:25:03.507903 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9555 00:25:03.510964 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9556 00:25:03.514483 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9557 00:25:03.521102 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9558 00:25:03.524253 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9559 00:25:03.531130 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9560 00:25:03.534289 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9561 00:25:03.537983 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9562 00:25:03.544166 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9563 00:25:03.547985 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9564 00:25:03.550795 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9565 00:25:03.557959 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9566 00:25:03.560862 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9567 00:25:03.567759 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9568 00:25:03.571058 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9569 00:25:03.574121 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9570 00:25:03.580847 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9571 00:25:03.584280 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9572 00:25:03.587846 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9573 00:25:03.594152 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9574 00:25:03.597485 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9575 00:25:03.604366 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9576 00:25:03.607458 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9577 00:25:03.611045 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9578 00:25:03.617897 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9579 00:25:03.620960 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9580 00:25:03.627813 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9581 00:25:03.630947 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9582 00:25:03.634140 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9583 00:25:03.640680 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9584 00:25:03.644116 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9585 00:25:03.647819 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9586 00:25:03.650895 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9587 00:25:03.658049 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9588 00:25:03.660887 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9589 00:25:03.664507 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9590 00:25:03.667548 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9591 00:25:03.674170 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9592 00:25:03.677639 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9593 00:25:03.681205 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9594 00:25:03.684344 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9595 00:25:03.690913 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9596 00:25:03.694008 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9597 00:25:03.697577 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9598 00:25:03.700782 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9599 00:25:03.707360 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9600 00:25:03.710958 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9601 00:25:03.717452 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9602 00:25:03.720616 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9603 00:25:03.727307 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9604 00:25:03.730793 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9605 00:25:03.733935 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9606 00:25:03.740711 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9607 00:25:03.743881 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9608 00:25:03.750977 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9609 00:25:03.753942 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9610 00:25:03.760681 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9611 00:25:03.763808 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9612 00:25:03.770946 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9613 00:25:03.773911 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9614 00:25:03.777380 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9615 00:25:03.783869 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9616 00:25:03.786992 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9617 00:25:03.793775 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9618 00:25:03.797136 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9619 00:25:03.803888 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9620 00:25:03.807361 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9621 00:25:03.810244 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9622 00:25:03.816931 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9623 00:25:03.820587 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9624 00:25:03.827422 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9625 00:25:03.830428 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9626 00:25:03.836984 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9627 00:25:03.840398 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9628 00:25:03.843812 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9629 00:25:03.850526 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9630 00:25:03.853441 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9631 00:25:03.860176 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9632 00:25:03.863983 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9633 00:25:03.870440 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9634 00:25:03.873564 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9635 00:25:03.877060 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9636 00:25:03.883481 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9637 00:25:03.887236 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9638 00:25:03.894021 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9639 00:25:03.896860 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9640 00:25:03.903543 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9641 00:25:03.907290 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9642 00:25:03.910301 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9643 00:25:03.916815 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9644 00:25:03.920421 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9645 00:25:03.926924 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9646 00:25:03.930279 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9647 00:25:03.936799 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9648 00:25:03.940297 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9649 00:25:03.943294 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9650 00:25:03.946640 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9651 00:25:03.953239 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9652 00:25:03.956714 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9653 00:25:03.959929 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9654 00:25:03.966660 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9655 00:25:03.969643 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9656 00:25:03.976875 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9657 00:25:03.979698 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9658 00:25:03.983350 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9659 00:25:03.989700 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9660 00:25:03.993329 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9661 00:25:03.999930 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9662 00:25:04.003323 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9663 00:25:04.006550 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9664 00:25:04.013095 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9665 00:25:04.016625 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9666 00:25:04.022970 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9667 00:25:04.026505 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9668 00:25:04.029661 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9669 00:25:04.036453 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9670 00:25:04.039575 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9671 00:25:04.043036 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9672 00:25:04.046654 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9673 00:25:04.049892 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9674 00:25:04.056535 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9675 00:25:04.060030 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9676 00:25:04.062872 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9677 00:25:04.069562 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9678 00:25:04.072952 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9679 00:25:04.080027 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9680 00:25:04.083087 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9681 00:25:04.086682 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9682 00:25:04.093288 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9683 00:25:04.096650 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9684 00:25:04.103125 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9685 00:25:04.106257 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9686 00:25:04.109935 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9687 00:25:04.116190 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9688 00:25:04.119817 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9689 00:25:04.126385 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9690 00:25:04.129582 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9691 00:25:04.133218 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9692 00:25:04.139338 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9693 00:25:04.142623 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9694 00:25:04.149458 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9695 00:25:04.152846 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9696 00:25:04.156327 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9697 00:25:04.162827 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9698 00:25:04.166363 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9699 00:25:04.169354 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9700 00:25:04.176065 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9701 00:25:04.179682 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9702 00:25:04.186189 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9703 00:25:04.189487 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9704 00:25:04.192866 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9705 00:25:04.199416 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9706 00:25:04.202582 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9707 00:25:04.209678 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9708 00:25:04.212862 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9709 00:25:04.215863 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9710 00:25:04.222549 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9711 00:25:04.226306 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9712 00:25:04.229295 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9713 00:25:04.236004 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9714 00:25:04.239552 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9715 00:25:04.246066 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9716 00:25:04.249260 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9717 00:25:04.252540 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9718 00:25:04.259055 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9719 00:25:04.262740 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9720 00:25:04.269210 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9721 00:25:04.272627 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9722 00:25:04.275837 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9723 00:25:04.282433 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9724 00:25:04.285851 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9725 00:25:04.288990 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9726 00:25:04.295649 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9727 00:25:04.299234 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9728 00:25:04.305661 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9729 00:25:04.309218 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9730 00:25:04.312559 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9731 00:25:04.319080 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9732 00:25:04.322742 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9733 00:25:04.328998 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9734 00:25:04.332526 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9735 00:25:04.335779 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9736 00:25:04.342151 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9737 00:25:04.345889 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9738 00:25:04.352446 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9739 00:25:04.355368 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9740 00:25:04.358749 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9741 00:25:04.365696 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9742 00:25:04.368821 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9743 00:25:04.375807 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9744 00:25:04.378841 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9745 00:25:04.382401 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9746 00:25:04.388920 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9747 00:25:04.391932 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9748 00:25:04.398669 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9749 00:25:04.402224 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9750 00:25:04.408908 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9751 00:25:04.412337 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9752 00:25:04.415684 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9753 00:25:04.422212 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9754 00:25:04.425316 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9755 00:25:04.431910 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9756 00:25:04.435353 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9757 00:25:04.438963 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9758 00:25:04.445373 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9759 00:25:04.448670 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9760 00:25:04.455255 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9761 00:25:04.458691 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9762 00:25:04.465426 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9763 00:25:04.468719 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9764 00:25:04.471911 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9765 00:25:04.478301 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9766 00:25:04.481913 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9767 00:25:04.488427 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9768 00:25:04.492033 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9769 00:25:04.495073 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9770 00:25:04.502218 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9771 00:25:04.505324 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9772 00:25:04.511716 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9773 00:25:04.515182 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9774 00:25:04.518737 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9775 00:25:04.525298 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9776 00:25:04.528819 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9777 00:25:04.535468 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9778 00:25:04.538546 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9779 00:25:04.541958 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9780 00:25:04.548426 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9781 00:25:04.551955 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9782 00:25:04.554994 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9783 00:25:04.558442 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9784 00:25:04.565499 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9785 00:25:04.568918 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9786 00:25:04.571675 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9787 00:25:04.578583 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9788 00:25:04.581674 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9789 00:25:04.585058 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9790 00:25:04.591532 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9791 00:25:04.595138 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9792 00:25:04.601653 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9793 00:25:04.605014 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9794 00:25:04.608420 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9795 00:25:04.614996 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9796 00:25:04.618471 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9797 00:25:04.621854 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9798 00:25:04.628420 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9799 00:25:04.631653 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9800 00:25:04.634761 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9801 00:25:04.641393 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9802 00:25:04.645026 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9803 00:25:04.651683 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9804 00:25:04.655266 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9805 00:25:04.658438 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9806 00:25:04.664969 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9807 00:25:04.669257 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9808 00:25:04.671670 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9809 00:25:04.678273 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9810 00:25:04.681530 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9811 00:25:04.687937 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9812 00:25:04.691691 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9813 00:25:04.694728 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9814 00:25:04.701359 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9815 00:25:04.704906 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9816 00:25:04.708011 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9817 00:25:04.714697 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9818 00:25:04.717980 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9819 00:25:04.721457 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9820 00:25:04.727914 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9821 00:25:04.731443 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9822 00:25:04.734423 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9823 00:25:04.738007 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9824 00:25:04.741467 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9825 00:25:04.747959 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9826 00:25:04.751052 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9827 00:25:04.754759 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9828 00:25:04.757739 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9829 00:25:04.764506 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9830 00:25:04.767596 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9831 00:25:04.771273 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9832 00:25:04.777845 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9833 00:25:04.781069 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9834 00:25:04.784342 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9835 00:25:04.791406 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9836 00:25:04.794612 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9837 00:25:04.801281 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9838 00:25:04.804588 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9839 00:25:04.807977 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9840 00:25:04.814562 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9841 00:25:04.817971 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9842 00:25:04.824491 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9843 00:25:04.828188 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9844 00:25:04.831317 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9845 00:25:04.837815 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9846 00:25:04.841146 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9847 00:25:04.847874 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9848 00:25:04.850898 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9849 00:25:04.854525 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9850 00:25:04.861085 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9851 00:25:04.864229 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9852 00:25:04.870809 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9853 00:25:04.874271 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9854 00:25:04.880848 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9855 00:25:04.884299 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9856 00:25:04.887557 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9857 00:25:04.894191 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9858 00:25:04.897707 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9859 00:25:04.904082 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9860 00:25:04.907413 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9861 00:25:04.910809 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9862 00:25:04.917545 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9863 00:25:04.920872 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9864 00:25:04.927497 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9865 00:25:04.930424 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9866 00:25:04.934182 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9867 00:25:04.940819 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9868 00:25:04.944200 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9869 00:25:04.950531 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9870 00:25:04.954209 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9871 00:25:04.961004 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9872 00:25:04.963863 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9873 00:25:04.967461 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9874 00:25:04.973932 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9875 00:25:04.977203 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9876 00:25:04.980858 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9877 00:25:04.987473 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9878 00:25:04.990420 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9879 00:25:04.997524 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9880 00:25:05.000461 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9881 00:25:05.004223 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9882 00:25:05.010829 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9883 00:25:05.013895 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9884 00:25:05.020458 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9885 00:25:05.023882 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9886 00:25:05.030873 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9887 00:25:05.034073 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9888 00:25:05.037112 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9889 00:25:05.043836 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9890 00:25:05.047495 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9891 00:25:05.054319 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9892 00:25:05.057483 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9893 00:25:05.060477 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9894 00:25:05.067354 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9895 00:25:05.070537 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9896 00:25:05.073881 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9897 00:25:05.080576 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9898 00:25:05.084002 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9899 00:25:05.090710 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9900 00:25:05.093749 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9901 00:25:05.100460 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9902 00:25:05.103803 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9903 00:25:05.107089 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9904 00:25:05.113825 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9905 00:25:05.116934 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9906 00:25:05.123626 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9907 00:25:05.127174 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9908 00:25:05.133770 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9909 00:25:05.137104 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9910 00:25:05.140524 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9911 00:25:05.146688 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9912 00:25:05.150248 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9913 00:25:05.156873 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9914 00:25:05.160438 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9915 00:25:05.167029 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9916 00:25:05.170239 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9917 00:25:05.173865 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9918 00:25:05.180067 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9919 00:25:05.183728 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9920 00:25:05.190332 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9921 00:25:05.193412 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9922 00:25:05.200529 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9923 00:25:05.203655 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9924 00:25:05.206916 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9925 00:25:05.213260 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9926 00:25:05.216691 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9927 00:25:05.223239 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9928 00:25:05.226757 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9929 00:25:05.233330 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9930 00:25:05.236799 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9931 00:25:05.240010 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9932 00:25:05.246956 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9933 00:25:05.250010 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9934 00:25:05.256536 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9935 00:25:05.259671 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9936 00:25:05.266357 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9937 00:25:05.269969 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9938 00:25:05.273461 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9939 00:25:05.280004 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9940 00:25:05.283109 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9941 00:25:05.289765 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9942 00:25:05.293435 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9943 00:25:05.300074 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9944 00:25:05.303111 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9945 00:25:05.306853 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9946 00:25:05.313039 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9947 00:25:05.316166 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9948 00:25:05.322725 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9949 00:25:05.326220 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9950 00:25:05.332757 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9951 00:25:05.335983 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9952 00:25:05.342839 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9953 00:25:05.346101 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9954 00:25:05.349583 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9955 00:25:05.356163 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9956 00:25:05.359194 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9957 00:25:05.366142 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9958 00:25:05.369479 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9959 00:25:05.376084 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9960 00:25:05.379130 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9961 00:25:05.385617 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9962 00:25:05.388961 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9963 00:25:05.395914 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9964 00:25:05.398849 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9965 00:25:05.405510 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9966 00:25:05.408691 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9967 00:25:05.415721 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9968 00:25:05.418826 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9969 00:25:05.425278 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9970 00:25:05.428959 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9971 00:25:05.435498 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9972 00:25:05.438937 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9973 00:25:05.445394 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9974 00:25:05.448868 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9975 00:25:05.455196 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9976 00:25:05.458307 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9977 00:25:05.465099 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9978 00:25:05.468748 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9979 00:25:05.475599 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9980 00:25:05.478619 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9981 00:25:05.485368 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9982 00:25:05.488936 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9983 00:25:05.495142 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9984 00:25:05.498557 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9985 00:25:05.501778 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9986 00:25:05.505218 INFO: [APUAPC] vio 0
9987 00:25:05.508782 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9988 00:25:05.515468 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9989 00:25:05.518977 INFO: [APUAPC] D0_APC_0: 0x400510
9990 00:25:05.521940 INFO: [APUAPC] D0_APC_1: 0x0
9991 00:25:05.525523 INFO: [APUAPC] D0_APC_2: 0x1540
9992 00:25:05.525599 INFO: [APUAPC] D0_APC_3: 0x0
9993 00:25:05.528935 INFO: [APUAPC] D1_APC_0: 0xffffffff
9994 00:25:05.532228 INFO: [APUAPC] D1_APC_1: 0xffffffff
9995 00:25:05.535523 INFO: [APUAPC] D1_APC_2: 0x3fffff
9996 00:25:05.538617 INFO: [APUAPC] D1_APC_3: 0x0
9997 00:25:05.542016 INFO: [APUAPC] D2_APC_0: 0xffffffff
9998 00:25:05.545412 INFO: [APUAPC] D2_APC_1: 0xffffffff
9999 00:25:05.548892 INFO: [APUAPC] D2_APC_2: 0x3fffff
10000 00:25:05.552237 INFO: [APUAPC] D2_APC_3: 0x0
10001 00:25:05.555240 INFO: [APUAPC] D3_APC_0: 0xffffffff
10002 00:25:05.558839 INFO: [APUAPC] D3_APC_1: 0xffffffff
10003 00:25:05.562076 INFO: [APUAPC] D3_APC_2: 0x3fffff
10004 00:25:05.565384 INFO: [APUAPC] D3_APC_3: 0x0
10005 00:25:05.568786 INFO: [APUAPC] D4_APC_0: 0xffffffff
10006 00:25:05.572261 INFO: [APUAPC] D4_APC_1: 0xffffffff
10007 00:25:05.575578 INFO: [APUAPC] D4_APC_2: 0x3fffff
10008 00:25:05.578661 INFO: [APUAPC] D4_APC_3: 0x0
10009 00:25:05.582191 INFO: [APUAPC] D5_APC_0: 0xffffffff
10010 00:25:05.585421 INFO: [APUAPC] D5_APC_1: 0xffffffff
10011 00:25:05.588551 INFO: [APUAPC] D5_APC_2: 0x3fffff
10012 00:25:05.591989 INFO: [APUAPC] D5_APC_3: 0x0
10013 00:25:05.595007 INFO: [APUAPC] D6_APC_0: 0xffffffff
10014 00:25:05.598756 INFO: [APUAPC] D6_APC_1: 0xffffffff
10015 00:25:05.602264 INFO: [APUAPC] D6_APC_2: 0x3fffff
10016 00:25:05.605353 INFO: [APUAPC] D6_APC_3: 0x0
10017 00:25:05.608665 INFO: [APUAPC] D7_APC_0: 0xffffffff
10018 00:25:05.611799 INFO: [APUAPC] D7_APC_1: 0xffffffff
10019 00:25:05.615377 INFO: [APUAPC] D7_APC_2: 0x3fffff
10020 00:25:05.618483 INFO: [APUAPC] D7_APC_3: 0x0
10021 00:25:05.622014 INFO: [APUAPC] D8_APC_0: 0xffffffff
10022 00:25:05.625005 INFO: [APUAPC] D8_APC_1: 0xffffffff
10023 00:25:05.628613 INFO: [APUAPC] D8_APC_2: 0x3fffff
10024 00:25:05.631559 INFO: [APUAPC] D8_APC_3: 0x0
10025 00:25:05.635190 INFO: [APUAPC] D9_APC_0: 0xffffffff
10026 00:25:05.638117 INFO: [APUAPC] D9_APC_1: 0xffffffff
10027 00:25:05.641685 INFO: [APUAPC] D9_APC_2: 0x3fffff
10028 00:25:05.645176 INFO: [APUAPC] D9_APC_3: 0x0
10029 00:25:05.648211 INFO: [APUAPC] D10_APC_0: 0xffffffff
10030 00:25:05.651657 INFO: [APUAPC] D10_APC_1: 0xffffffff
10031 00:25:05.655147 INFO: [APUAPC] D10_APC_2: 0x3fffff
10032 00:25:05.658309 INFO: [APUAPC] D10_APC_3: 0x0
10033 00:25:05.661829 INFO: [APUAPC] D11_APC_0: 0xffffffff
10034 00:25:05.664827 INFO: [APUAPC] D11_APC_1: 0xffffffff
10035 00:25:05.668528 INFO: [APUAPC] D11_APC_2: 0x3fffff
10036 00:25:05.671854 INFO: [APUAPC] D11_APC_3: 0x0
10037 00:25:05.674839 INFO: [APUAPC] D12_APC_0: 0xffffffff
10038 00:25:05.678335 INFO: [APUAPC] D12_APC_1: 0xffffffff
10039 00:25:05.681352 INFO: [APUAPC] D12_APC_2: 0x3fffff
10040 00:25:05.684653 INFO: [APUAPC] D12_APC_3: 0x0
10041 00:25:05.687982 INFO: [APUAPC] D13_APC_0: 0xffffffff
10042 00:25:05.691632 INFO: [APUAPC] D13_APC_1: 0xffffffff
10043 00:25:05.694942 INFO: [APUAPC] D13_APC_2: 0x3fffff
10044 00:25:05.698404 INFO: [APUAPC] D13_APC_3: 0x0
10045 00:25:05.701502 INFO: [APUAPC] D14_APC_0: 0xffffffff
10046 00:25:05.704981 INFO: [APUAPC] D14_APC_1: 0xffffffff
10047 00:25:05.707974 INFO: [APUAPC] D14_APC_2: 0x3fffff
10048 00:25:05.711176 INFO: [APUAPC] D14_APC_3: 0x0
10049 00:25:05.714890 INFO: [APUAPC] D15_APC_0: 0xffffffff
10050 00:25:05.718343 INFO: [APUAPC] D15_APC_1: 0xffffffff
10051 00:25:05.721472 INFO: [APUAPC] D15_APC_2: 0x3fffff
10052 00:25:05.724572 INFO: [APUAPC] D15_APC_3: 0x0
10053 00:25:05.728210 INFO: [APUAPC] APC_CON: 0x4
10054 00:25:05.728289 INFO: [NOCDAPC] D0_APC_0: 0x0
10055 00:25:05.731224 INFO: [NOCDAPC] D0_APC_1: 0x0
10056 00:25:05.734873 INFO: [NOCDAPC] D1_APC_0: 0x0
10057 00:25:05.737961 INFO: [NOCDAPC] D1_APC_1: 0xfff
10058 00:25:05.741314 INFO: [NOCDAPC] D2_APC_0: 0x0
10059 00:25:05.745091 INFO: [NOCDAPC] D2_APC_1: 0xfff
10060 00:25:05.747995 INFO: [NOCDAPC] D3_APC_0: 0x0
10061 00:25:05.751415 INFO: [NOCDAPC] D3_APC_1: 0xfff
10062 00:25:05.754577 INFO: [NOCDAPC] D4_APC_0: 0x0
10063 00:25:05.758242 INFO: [NOCDAPC] D4_APC_1: 0xfff
10064 00:25:05.761248 INFO: [NOCDAPC] D5_APC_0: 0x0
10065 00:25:05.761310 INFO: [NOCDAPC] D5_APC_1: 0xfff
10066 00:25:05.765031 INFO: [NOCDAPC] D6_APC_0: 0x0
10067 00:25:05.767969 INFO: [NOCDAPC] D6_APC_1: 0xfff
10068 00:25:05.771593 INFO: [NOCDAPC] D7_APC_0: 0x0
10069 00:25:05.774706 INFO: [NOCDAPC] D7_APC_1: 0xfff
10070 00:25:05.777938 INFO: [NOCDAPC] D8_APC_0: 0x0
10071 00:25:05.781225 INFO: [NOCDAPC] D8_APC_1: 0xfff
10072 00:25:05.784544 INFO: [NOCDAPC] D9_APC_0: 0x0
10073 00:25:05.788146 INFO: [NOCDAPC] D9_APC_1: 0xfff
10074 00:25:05.791667 INFO: [NOCDAPC] D10_APC_0: 0x0
10075 00:25:05.794467 INFO: [NOCDAPC] D10_APC_1: 0xfff
10076 00:25:05.794548 INFO: [NOCDAPC] D11_APC_0: 0x0
10077 00:25:05.798087 INFO: [NOCDAPC] D11_APC_1: 0xfff
10078 00:25:05.801308 INFO: [NOCDAPC] D12_APC_0: 0x0
10079 00:25:05.804858 INFO: [NOCDAPC] D12_APC_1: 0xfff
10080 00:25:05.807724 INFO: [NOCDAPC] D13_APC_0: 0x0
10081 00:25:05.811475 INFO: [NOCDAPC] D13_APC_1: 0xfff
10082 00:25:05.814274 INFO: [NOCDAPC] D14_APC_0: 0x0
10083 00:25:05.817719 INFO: [NOCDAPC] D14_APC_1: 0xfff
10084 00:25:05.821291 INFO: [NOCDAPC] D15_APC_0: 0x0
10085 00:25:05.824852 INFO: [NOCDAPC] D15_APC_1: 0xfff
10086 00:25:05.827776 INFO: [NOCDAPC] APC_CON: 0x4
10087 00:25:05.830899 INFO: [APUAPC] set_apusys_apc done
10088 00:25:05.834441 INFO: [DEVAPC] devapc_init done
10089 00:25:05.838016 INFO: GICv3 without legacy support detected.
10090 00:25:05.841078 INFO: ARM GICv3 driver initialized in EL3
10091 00:25:05.844648 INFO: Maximum SPI INTID supported: 639
10092 00:25:05.847881 INFO: BL31: Initializing runtime services
10093 00:25:05.854446 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10094 00:25:05.857830 INFO: SPM: enable CPC mode
10095 00:25:05.864231 INFO: mcdi ready for mcusys-off-idle and system suspend
10096 00:25:05.867811 INFO: BL31: Preparing for EL3 exit to normal world
10097 00:25:05.871319 INFO: Entry point address = 0x80000000
10098 00:25:05.874411 INFO: SPSR = 0x8
10099 00:25:05.879006
10100 00:25:05.879074
10101 00:25:05.879130
10102 00:25:05.882628 Starting depthcharge on Spherion...
10103 00:25:05.882695
10104 00:25:05.882749 Wipe memory regions:
10105 00:25:05.882808
10106 00:25:05.883441 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10107 00:25:05.883535 start: 2.2.4 bootloader-commands (timeout 00:04:20) [common]
10108 00:25:05.883614 Setting prompt string to ['asurada:']
10109 00:25:05.883690 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:20)
10110 00:25:05.885619 [0x00000040000000, 0x00000054600000)
10111 00:25:06.007497
10112 00:25:06.007601 [0x00000054660000, 0x00000080000000)
10113 00:25:06.268605
10114 00:25:06.268742 [0x000000821a7280, 0x000000ffe64000)
10115 00:25:07.012988
10116 00:25:07.013117 [0x00000100000000, 0x00000240000000)
10117 00:25:08.902994
10118 00:25:08.906562 Initializing XHCI USB controller at 0x11200000.
10119 00:25:09.944804
10120 00:25:09.947771 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10121 00:25:09.947845
10122 00:25:09.947904
10123 00:25:09.948177 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10125 00:25:10.048466 asurada: tftpboot 192.168.201.1 14479188/tftp-deploy-57w3ztgi/kernel/image.itb 14479188/tftp-deploy-57w3ztgi/kernel/cmdline
10126 00:25:10.048631 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10127 00:25:10.048781 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:16)
10128 00:25:10.052805 tftpboot 192.168.201.1 14479188/tftp-deploy-57w3ztgi/kernel/image.ittp-deploy-57w3ztgi/kernel/cmdline
10129 00:25:10.052911
10130 00:25:10.053009 Waiting for link
10131 00:25:10.211192
10132 00:25:10.211294 R8152: Initializing
10133 00:25:10.211358
10134 00:25:10.214195 Version 9 (ocp_data = 6010)
10135 00:25:10.214271
10136 00:25:10.217779 R8152: Done initializing
10137 00:25:10.217855
10138 00:25:10.217914 Adding net device
10139 00:25:12.167026
10140 00:25:12.167595 done.
10141 00:25:12.167935
10142 00:25:12.168244 MAC: 00:e0:4c:72:2d:d6
10143 00:25:12.168543
10144 00:25:12.169749 Sending DHCP discover... done.
10145 00:25:12.170185
10146 00:25:12.173349 Waiting for reply... done.
10147 00:25:12.173851
10148 00:25:12.176382 Sending DHCP request... done.
10149 00:25:12.176933
10150 00:25:12.180081 Waiting for reply... done.
10151 00:25:12.180588
10152 00:25:12.180982 My ip is 192.168.201.21
10153 00:25:12.181304
10154 00:25:12.183315 The DHCP server ip is 192.168.201.1
10155 00:25:12.183748
10156 00:25:12.190104 TFTP server IP predefined by user: 192.168.201.1
10157 00:25:12.190531
10158 00:25:12.196818 Bootfile predefined by user: 14479188/tftp-deploy-57w3ztgi/kernel/image.itb
10159 00:25:12.197303
10160 00:25:12.197609 Sending tftp read request... done.
10161 00:25:12.199677
10162 00:25:12.206347 Waiting for the transfer...
10163 00:25:12.206814
10164 00:25:12.516322 00000000 ################################################################
10165 00:25:12.516446
10166 00:25:12.779094 00080000 ################################################################
10167 00:25:12.779210
10168 00:25:13.062833 00100000 ################################################################
10169 00:25:13.062948
10170 00:25:13.359854 00180000 ################################################################
10171 00:25:13.359962
10172 00:25:13.633024 00200000 ################################################################
10173 00:25:13.633166
10174 00:25:13.883098 00280000 ################################################################
10175 00:25:13.883213
10176 00:25:14.141956 00300000 ################################################################
10177 00:25:14.142066
10178 00:25:14.390679 00380000 ################################################################
10179 00:25:14.390807
10180 00:25:14.639749 00400000 ################################################################
10181 00:25:14.639865
10182 00:25:14.890883 00480000 ################################################################
10183 00:25:14.891023
10184 00:25:15.158380 00500000 ################################################################
10185 00:25:15.158500
10186 00:25:15.419588 00580000 ################################################################
10187 00:25:15.419721
10188 00:25:15.692461 00600000 ################################################################
10189 00:25:15.692575
10190 00:25:15.945410 00680000 ################################################################
10191 00:25:15.945520
10192 00:25:16.238386 00700000 ################################################################
10193 00:25:16.238499
10194 00:25:16.513567 00780000 ################################################################
10195 00:25:16.513681
10196 00:25:16.763145 00800000 ################################################################
10197 00:25:16.763260
10198 00:25:17.033174 00880000 ################################################################
10199 00:25:17.033439
10200 00:25:17.317785 00900000 ################################################################
10201 00:25:17.317905
10202 00:25:17.597181 00980000 ################################################################
10203 00:25:17.597295
10204 00:25:17.854276 00a00000 ################################################################
10205 00:25:17.854407
10206 00:25:18.120245 00a80000 ################################################################
10207 00:25:18.120358
10208 00:25:18.402999 00b00000 ################################################################
10209 00:25:18.403142
10210 00:25:18.673200 00b80000 ################################################################
10211 00:25:18.673324
10212 00:25:18.935530 00c00000 ################################################################
10213 00:25:18.935652
10214 00:25:19.193424 00c80000 ################################################################
10215 00:25:19.193542
10216 00:25:19.458409 00d00000 ################################################################
10217 00:25:19.458539
10218 00:25:19.714012 00d80000 ################################################################
10219 00:25:19.714173
10220 00:25:19.970044 00e00000 ################################################################
10221 00:25:19.970175
10222 00:25:20.237140 00e80000 ################################################################
10223 00:25:20.237255
10224 00:25:20.492458 00f00000 ################################################################
10225 00:25:20.492582
10226 00:25:20.756687 00f80000 ################################################################
10227 00:25:20.756806
10228 00:25:21.017933 01000000 ################################################################
10229 00:25:21.018047
10230 00:25:21.294267 01080000 ################################################################
10231 00:25:21.294389
10232 00:25:21.566281 01100000 ################################################################
10233 00:25:21.566406
10234 00:25:21.823828 01180000 ################################################################
10235 00:25:21.823947
10236 00:25:22.105486 01200000 ################################################################
10237 00:25:22.105610
10238 00:25:22.372904 01280000 ################################################################
10239 00:25:22.373017
10240 00:25:22.640749 01300000 ################################################################
10241 00:25:22.640868
10242 00:25:22.921752 01380000 ################################################################
10243 00:25:22.921879
10244 00:25:23.193932 01400000 ################################################################
10245 00:25:23.194047
10246 00:25:23.454457 01480000 ################################################################
10247 00:25:23.454568
10248 00:25:23.746259 01500000 ################################################################
10249 00:25:23.746367
10250 00:25:24.014233 01580000 ################################################################
10251 00:25:24.014350
10252 00:25:24.283799 01600000 ################################################################
10253 00:25:24.283915
10254 00:25:24.568411 01680000 ################################################################
10255 00:25:24.568527
10256 00:25:24.828326 01700000 ################################################################
10257 00:25:24.828464
10258 00:25:25.091455 01780000 ################################################################
10259 00:25:25.091570
10260 00:25:25.347420 01800000 ################################################################
10261 00:25:25.347537
10262 00:25:25.601389 01880000 ################################################################
10263 00:25:25.601500
10264 00:25:25.874335 01900000 ################################################################
10265 00:25:25.874452
10266 00:25:26.155241 01980000 ################################################################
10267 00:25:26.155374
10268 00:25:26.426622 01a00000 ################################################################
10269 00:25:26.426785
10270 00:25:26.698481 01a80000 ################################################################
10271 00:25:26.698634
10272 00:25:26.964578 01b00000 ################################################################
10273 00:25:26.964693
10274 00:25:27.225103 01b80000 ################################################################
10275 00:25:27.225217
10276 00:25:27.490136 01c00000 ################################################################
10277 00:25:27.490300
10278 00:25:27.759520 01c80000 ################################################################
10279 00:25:27.759636
10280 00:25:28.021721 01d00000 ################################################################
10281 00:25:28.021835
10282 00:25:28.291328 01d80000 ################################################################
10283 00:25:28.291444
10284 00:25:28.511373 01e00000 ######################################################### done.
10285 00:25:28.511504
10286 00:25:28.514646 The bootfile was 31920710 bytes long.
10287 00:25:28.514724
10288 00:25:28.518365 Sending tftp read request... done.
10289 00:25:28.518443
10290 00:25:28.521146 Waiting for the transfer...
10291 00:25:28.521224
10292 00:25:28.524549 00000000 # done.
10293 00:25:28.524658
10294 00:25:28.531473 Command line loaded dynamically from TFTP file: 14479188/tftp-deploy-57w3ztgi/kernel/cmdline
10295 00:25:28.531641
10296 00:25:28.554364 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14479188/extract-nfsrootfs-0_775cf7,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10297 00:25:28.554519
10298 00:25:28.554630 Loading FIT.
10299 00:25:28.554734
10300 00:25:28.557734 Image ramdisk-1 has 18746529 bytes.
10301 00:25:28.557895
10302 00:25:28.561074 Image fdt-1 has 47258 bytes.
10303 00:25:28.561235
10304 00:25:28.564741 Image kernel-1 has 13124896 bytes.
10305 00:25:28.565272
10306 00:25:28.574643 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10307 00:25:28.575082
10308 00:25:28.590766 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10309 00:25:28.591215
10310 00:25:28.594681 Choosing best match conf-1 for compat google,spherion-rev2.
10311 00:25:28.599847
10312 00:25:28.604839 Connected to device vid:did:rid of 1ae0:0028:00
10313 00:25:28.612646
10314 00:25:28.615799 tpm_get_response: command 0x17b, return code 0x0
10315 00:25:28.616192
10316 00:25:28.619264 ec_init: CrosEC protocol v3 supported (256, 248)
10317 00:25:28.623315
10318 00:25:28.626798 tpm_cleanup: add release locality here.
10319 00:25:28.627185
10320 00:25:28.627486 Shutting down all USB controllers.
10321 00:25:28.627791
10322 00:25:28.630494 Removing current net device
10323 00:25:28.630973
10324 00:25:28.636762 Exiting depthcharge with code 4 at timestamp: 52078720
10325 00:25:28.637227
10326 00:25:28.640505 LZMA decompressing kernel-1 to 0x821a6718
10327 00:25:28.641032
10328 00:25:28.643422 LZMA decompressing kernel-1 to 0x40000000
10329 00:25:30.259302
10330 00:25:30.259440 jumping to kernel
10331 00:25:30.260252 end: 2.2.4 bootloader-commands (duration 00:00:24) [common]
10332 00:25:30.260345 start: 2.2.5 auto-login-action (timeout 00:03:56) [common]
10333 00:25:30.260413 Setting prompt string to ['Linux version [0-9]']
10334 00:25:30.260478 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10335 00:25:30.260540 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10336 00:25:30.341662
10337 00:25:30.344420 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10338 00:25:30.348089 start: 2.2.5.1 login-action (timeout 00:03:56) [common]
10339 00:25:30.348184 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10340 00:25:30.348253 Setting prompt string to []
10341 00:25:30.348327 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10342 00:25:30.348394 Using line separator: #'\n'#
10343 00:25:30.348449 No login prompt set.
10344 00:25:30.348506 Parsing kernel messages
10345 00:25:30.348556 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10346 00:25:30.348654 [login-action] Waiting for messages, (timeout 00:03:56)
10347 00:25:30.348737 Waiting using forced prompt support (timeout 00:01:58)
10348 00:25:30.368001 [ 0.000000] Linux version 6.1.94-cip23 (KernelCI@build-j239242-arm64-gcc-10-defconfig-arm64-chromebook-c5lwc) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Jun 21 00:04:56 UTC 2024
10349 00:25:30.370924 [ 0.000000] random: crng init done
10350 00:25:30.377687 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10351 00:25:30.377765 [ 0.000000] efi: UEFI not found.
10352 00:25:30.387784 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10353 00:25:30.394168 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10354 00:25:30.403898 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10355 00:25:30.414007 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10356 00:25:30.420660 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10357 00:25:30.426959 [ 0.000000] printk: bootconsole [mtk8250] enabled
10358 00:25:30.433498 [ 0.000000] NUMA: No NUMA configuration found
10359 00:25:30.440346 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10360 00:25:30.443731 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10361 00:25:30.446731 [ 0.000000] Zone ranges:
10362 00:25:30.453762 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10363 00:25:30.456929 [ 0.000000] DMA32 empty
10364 00:25:30.463446 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10365 00:25:30.466477 [ 0.000000] Movable zone start for each node
10366 00:25:30.469843 [ 0.000000] Early memory node ranges
10367 00:25:30.476792 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10368 00:25:30.483313 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10369 00:25:30.490027 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10370 00:25:30.496499 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10371 00:25:30.499773 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10372 00:25:30.509757 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10373 00:25:30.565847 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10374 00:25:30.572502 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10375 00:25:30.578681 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10376 00:25:30.582247 [ 0.000000] psci: probing for conduit method from DT.
10377 00:25:30.588925 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10378 00:25:30.592106 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10379 00:25:30.598679 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10380 00:25:30.601933 [ 0.000000] psci: SMC Calling Convention v1.2
10381 00:25:30.608408 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10382 00:25:30.611956 [ 0.000000] Detected VIPT I-cache on CPU0
10383 00:25:30.618401 [ 0.000000] CPU features: detected: GIC system register CPU interface
10384 00:25:30.625282 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10385 00:25:30.631960 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10386 00:25:30.638384 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10387 00:25:30.645303 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10388 00:25:30.654910 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10389 00:25:30.657973 [ 0.000000] alternatives: applying boot alternatives
10390 00:25:30.664882 [ 0.000000] Fallback order for Node 0: 0
10391 00:25:30.671385 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10392 00:25:30.674485 [ 0.000000] Policy zone: Normal
10393 00:25:30.697970 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14479188/extract-nfsrootfs-0_775cf7,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10394 00:25:30.707819 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10395 00:25:30.718557 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10396 00:25:30.728601 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10397 00:25:30.735171 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10398 00:25:30.738739 <6>[ 0.000000] software IO TLB: area num 8.
10399 00:25:30.794863 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10400 00:25:30.944205 <6>[ 0.000000] Memory: 7945756K/8385536K available (18112K kernel code, 4120K rwdata, 22648K rodata, 8512K init, 616K bss, 407012K reserved, 32768K cma-reserved)
10401 00:25:30.950780 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10402 00:25:30.957372 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10403 00:25:30.960774 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10404 00:25:30.967573 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10405 00:25:30.973938 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10406 00:25:30.977409 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10407 00:25:30.987534 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10408 00:25:30.994100 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10409 00:25:31.000582 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10410 00:25:31.006948 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10411 00:25:31.010529 <6>[ 0.000000] GICv3: 608 SPIs implemented
10412 00:25:31.013561 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10413 00:25:31.020557 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10414 00:25:31.023788 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10415 00:25:31.030367 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10416 00:25:31.043452 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10417 00:25:31.053589 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10418 00:25:31.063508 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10419 00:25:31.070989 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10420 00:25:31.083917 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10421 00:25:31.090483 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10422 00:25:31.097348 <6>[ 0.009174] Console: colour dummy device 80x25
10423 00:25:31.106889 <6>[ 0.013933] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10424 00:25:31.113802 <6>[ 0.024376] pid_max: default: 32768 minimum: 301
10425 00:25:31.116946 <6>[ 0.029247] LSM: Security Framework initializing
10426 00:25:31.123887 <6>[ 0.034184] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10427 00:25:31.133426 <6>[ 0.041990] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10428 00:25:31.140505 <6>[ 0.051403] cblist_init_generic: Setting adjustable number of callback queues.
10429 00:25:31.146873 <6>[ 0.058846] cblist_init_generic: Setting shift to 3 and lim to 1.
10430 00:25:31.156843 <6>[ 0.065186] cblist_init_generic: Setting adjustable number of callback queues.
10431 00:25:31.163749 <6>[ 0.072614] cblist_init_generic: Setting shift to 3 and lim to 1.
10432 00:25:31.166565 <6>[ 0.079015] rcu: Hierarchical SRCU implementation.
10433 00:25:31.174269 <6>[ 0.084031] rcu: Max phase no-delay instances is 1000.
10434 00:25:31.180257 <6>[ 0.091067] EFI services will not be available.
10435 00:25:31.183531 <6>[ 0.096025] smp: Bringing up secondary CPUs ...
10436 00:25:31.191872 <6>[ 0.101105] Detected VIPT I-cache on CPU1
10437 00:25:31.197961 <6>[ 0.101176] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10438 00:25:31.204828 <6>[ 0.101209] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10439 00:25:31.207839 <6>[ 0.101549] Detected VIPT I-cache on CPU2
10440 00:25:31.217825 <6>[ 0.101602] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10441 00:25:31.224327 <6>[ 0.101619] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10442 00:25:31.227849 <6>[ 0.101879] Detected VIPT I-cache on CPU3
10443 00:25:31.234315 <6>[ 0.101927] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10444 00:25:31.241056 <6>[ 0.101941] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10445 00:25:31.244327 <6>[ 0.102244] CPU features: detected: Spectre-v4
10446 00:25:31.251094 <6>[ 0.102250] CPU features: detected: Spectre-BHB
10447 00:25:31.253972 <6>[ 0.102255] Detected PIPT I-cache on CPU4
10448 00:25:31.260610 <6>[ 0.102313] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10449 00:25:31.267369 <6>[ 0.102331] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10450 00:25:31.273825 <6>[ 0.102620] Detected PIPT I-cache on CPU5
10451 00:25:31.280805 <6>[ 0.102683] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10452 00:25:31.287334 <6>[ 0.102700] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10453 00:25:31.290414 <6>[ 0.102980] Detected PIPT I-cache on CPU6
10454 00:25:31.297482 <6>[ 0.103046] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10455 00:25:31.303555 <6>[ 0.103062] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10456 00:25:31.310309 <6>[ 0.103356] Detected PIPT I-cache on CPU7
10457 00:25:31.316836 <6>[ 0.103422] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10458 00:25:31.323535 <6>[ 0.103438] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10459 00:25:31.326995 <6>[ 0.103486] smp: Brought up 1 node, 8 CPUs
10460 00:25:31.333790 <6>[ 0.244854] SMP: Total of 8 processors activated.
10461 00:25:31.336859 <6>[ 0.249776] CPU features: detected: 32-bit EL0 Support
10462 00:25:31.346785 <6>[ 0.255172] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10463 00:25:31.353296 <6>[ 0.263973] CPU features: detected: Common not Private translations
10464 00:25:31.359944 <6>[ 0.270449] CPU features: detected: CRC32 instructions
10465 00:25:31.363270 <6>[ 0.275834] CPU features: detected: RCpc load-acquire (LDAPR)
10466 00:25:31.369907 <6>[ 0.281794] CPU features: detected: LSE atomic instructions
10467 00:25:31.376284 <6>[ 0.287576] CPU features: detected: Privileged Access Never
10468 00:25:31.383260 <6>[ 0.293356] CPU features: detected: RAS Extension Support
10469 00:25:31.389604 <6>[ 0.298964] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10470 00:25:31.393257 <6>[ 0.306183] CPU: All CPU(s) started at EL2
10471 00:25:31.399289 <6>[ 0.310500] alternatives: applying system-wide alternatives
10472 00:25:31.409464 <6>[ 0.321369] devtmpfs: initialized
10473 00:25:31.424500 <6>[ 0.330186] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10474 00:25:31.431542 <6>[ 0.340149] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10475 00:25:31.438230 <6>[ 0.348167] pinctrl core: initialized pinctrl subsystem
10476 00:25:31.441743 <6>[ 0.354843] DMI not present or invalid.
10477 00:25:31.447975 <6>[ 0.359251] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10478 00:25:31.457890 <6>[ 0.366106] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10479 00:25:31.464134 <6>[ 0.373691] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10480 00:25:31.474387 <6>[ 0.381915] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10481 00:25:31.477380 <6>[ 0.390156] audit: initializing netlink subsys (disabled)
10482 00:25:31.487765 <5>[ 0.395849] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10483 00:25:31.493835 <6>[ 0.396562] thermal_sys: Registered thermal governor 'step_wise'
10484 00:25:31.500663 <6>[ 0.403819] thermal_sys: Registered thermal governor 'power_allocator'
10485 00:25:31.503834 <6>[ 0.410075] cpuidle: using governor menu
10486 00:25:31.510814 <6>[ 0.421030] NET: Registered PF_QIPCRTR protocol family
10487 00:25:31.517180 <6>[ 0.426518] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10488 00:25:31.523890 <6>[ 0.433623] ASID allocator initialised with 32768 entries
10489 00:25:31.527152 <6>[ 0.440197] Serial: AMBA PL011 UART driver
10490 00:25:31.537249 <4>[ 0.449034] Trying to register duplicate clock ID: 134
10491 00:25:31.595247 <6>[ 0.510607] KASLR enabled
10492 00:25:31.609655 <6>[ 0.518315] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10493 00:25:31.616408 <6>[ 0.525331] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10494 00:25:31.622680 <6>[ 0.531821] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10495 00:25:31.629689 <6>[ 0.538826] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10496 00:25:31.636226 <6>[ 0.545313] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10497 00:25:31.642656 <6>[ 0.552318] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10498 00:25:31.649096 <6>[ 0.558803] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10499 00:25:31.656035 <6>[ 0.565809] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10500 00:25:31.658896 <6>[ 0.573319] ACPI: Interpreter disabled.
10501 00:25:31.667861 <6>[ 0.579732] iommu: Default domain type: Translated
10502 00:25:31.674447 <6>[ 0.584846] iommu: DMA domain TLB invalidation policy: strict mode
10503 00:25:31.677698 <5>[ 0.591509] SCSI subsystem initialized
10504 00:25:31.684333 <6>[ 0.595672] usbcore: registered new interface driver usbfs
10505 00:25:31.691053 <6>[ 0.601405] usbcore: registered new interface driver hub
10506 00:25:31.694106 <6>[ 0.606957] usbcore: registered new device driver usb
10507 00:25:31.701107 <6>[ 0.613051] pps_core: LinuxPPS API ver. 1 registered
10508 00:25:31.710825 <6>[ 0.618247] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10509 00:25:31.714284 <6>[ 0.627594] PTP clock support registered
10510 00:25:31.717310 <6>[ 0.631834] EDAC MC: Ver: 3.0.0
10511 00:25:31.724929 <6>[ 0.636983] FPGA manager framework
10512 00:25:31.728095 <6>[ 0.640668] Advanced Linux Sound Architecture Driver Initialized.
10513 00:25:31.731831 <6>[ 0.647438] vgaarb: loaded
10514 00:25:31.738706 <6>[ 0.650601] clocksource: Switched to clocksource arch_sys_counter
10515 00:25:31.745205 <5>[ 0.657038] VFS: Disk quotas dquot_6.6.0
10516 00:25:31.751979 <6>[ 0.661225] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10517 00:25:31.755237 <6>[ 0.668411] pnp: PnP ACPI: disabled
10518 00:25:31.763265 <6>[ 0.675201] NET: Registered PF_INET protocol family
10519 00:25:31.773004 <6>[ 0.680809] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10520 00:25:31.784543 <6>[ 0.693102] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10521 00:25:31.794497 <6>[ 0.701917] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10522 00:25:31.801014 <6>[ 0.709886] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10523 00:25:31.810932 <6>[ 0.718587] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10524 00:25:31.817653 <6>[ 0.728328] TCP: Hash tables configured (established 65536 bind 65536)
10525 00:25:31.824435 <6>[ 0.735194] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10526 00:25:31.834089 <6>[ 0.742394] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10527 00:25:31.841007 <6>[ 0.750097] NET: Registered PF_UNIX/PF_LOCAL protocol family
10528 00:25:31.843794 <6>[ 0.756189] RPC: Registered named UNIX socket transport module.
10529 00:25:31.850261 <6>[ 0.762335] RPC: Registered udp transport module.
10530 00:25:31.853792 <6>[ 0.767268] RPC: Registered tcp transport module.
10531 00:25:31.860039 <6>[ 0.772199] RPC: Registered tcp NFSv4.1 backchannel transport module.
10532 00:25:31.866862 <6>[ 0.778864] PCI: CLS 0 bytes, default 64
10533 00:25:31.870397 <6>[ 0.783254] Unpacking initramfs...
10534 00:25:31.887043 <6>[ 0.795168] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10535 00:25:31.897179 <6>[ 0.803836] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10536 00:25:31.900090 <6>[ 0.812627] kvm [1]: IPA Size Limit: 40 bits
10537 00:25:31.906794 <6>[ 0.817156] kvm [1]: GICv3: no GICV resource entry
10538 00:25:31.910075 <6>[ 0.822177] kvm [1]: disabling GICv2 emulation
10539 00:25:31.916541 <6>[ 0.826865] kvm [1]: GIC system register CPU interface enabled
10540 00:25:31.920332 <6>[ 0.833037] kvm [1]: vgic interrupt IRQ18
10541 00:25:31.926362 <6>[ 0.837391] kvm [1]: VHE mode initialized successfully
10542 00:25:31.932993 <5>[ 0.843851] Initialise system trusted keyrings
10543 00:25:31.939446 <6>[ 0.848664] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10544 00:25:31.947346 <6>[ 0.858671] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10545 00:25:31.953683 <5>[ 0.865078] NFS: Registering the id_resolver key type
10546 00:25:31.957198 <5>[ 0.870382] Key type id_resolver registered
10547 00:25:31.963541 <5>[ 0.874795] Key type id_legacy registered
10548 00:25:31.970337 <6>[ 0.879075] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10549 00:25:31.976594 <6>[ 0.885996] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10550 00:25:31.983732 <6>[ 0.893701] 9p: Installing v9fs 9p2000 file system support
10551 00:25:32.019323 <5>[ 0.931241] Key type asymmetric registered
10552 00:25:32.022965 <5>[ 0.935572] Asymmetric key parser 'x509' registered
10553 00:25:32.032591 <6>[ 0.940710] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10554 00:25:32.035843 <6>[ 0.948321] io scheduler mq-deadline registered
10555 00:25:32.039503 <6>[ 0.953081] io scheduler kyber registered
10556 00:25:32.058340 <6>[ 0.970279] EINJ: ACPI disabled.
10557 00:25:32.091491 <4>[ 0.996612] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10558 00:25:32.100892 <4>[ 1.007248] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10559 00:25:32.116246 <6>[ 1.028456] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10560 00:25:32.124259 <6>[ 1.036514] printk: console [ttyS0] disabled
10561 00:25:32.152436 <6>[ 1.061160] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10562 00:25:32.158974 <6>[ 1.070638] printk: console [ttyS0] enabled
10563 00:25:32.162191 <6>[ 1.070638] printk: console [ttyS0] enabled
10564 00:25:32.169046 <6>[ 1.079532] printk: bootconsole [mtk8250] disabled
10565 00:25:32.172306 <6>[ 1.079532] printk: bootconsole [mtk8250] disabled
10566 00:25:32.178650 <6>[ 1.090922] SuperH (H)SCI(F) driver initialized
10567 00:25:32.181934 <6>[ 1.096196] msm_serial: driver initialized
10568 00:25:32.196447 <6>[ 1.105157] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10569 00:25:32.206430 <6>[ 1.113714] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10570 00:25:32.212953 <6>[ 1.122258] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10571 00:25:32.223156 <6>[ 1.130886] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10572 00:25:32.233254 <6>[ 1.139592] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10573 00:25:32.239339 <6>[ 1.148305] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10574 00:25:32.249213 <6>[ 1.156853] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10575 00:25:32.256025 <6>[ 1.165662] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10576 00:25:32.265694 <6>[ 1.174203] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10577 00:25:32.277756 <6>[ 1.189897] loop: module loaded
10578 00:25:32.284173 <6>[ 1.195879] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10579 00:25:32.306869 <4>[ 1.219241] mtk-pmic-keys: Failed to locate of_node [id: -1]
10580 00:25:32.313769 <6>[ 1.226122] megasas: 07.719.03.00-rc1
10581 00:25:32.323774 <6>[ 1.235669] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10582 00:25:32.332332 <6>[ 1.244190] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10583 00:25:32.348910 <6>[ 1.260618] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10584 00:25:32.403962 <6>[ 1.309554] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10585 00:25:32.662124 <6>[ 1.574352] Freeing initrd memory: 18300K
10586 00:25:32.673811 <6>[ 1.585856] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10587 00:25:32.684741 <6>[ 1.596922] tun: Universal TUN/TAP device driver, 1.6
10588 00:25:32.688237 <6>[ 1.602999] thunder_xcv, ver 1.0
10589 00:25:32.691373 <6>[ 1.606493] thunder_bgx, ver 1.0
10590 00:25:32.694484 <6>[ 1.609995] nicpf, ver 1.0
10591 00:25:32.705200 <6>[ 1.614013] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10592 00:25:32.708570 <6>[ 1.621489] hns3: Copyright (c) 2017 Huawei Corporation.
10593 00:25:32.711819 <6>[ 1.627076] hclge is initializing
10594 00:25:32.718555 <6>[ 1.630660] e1000: Intel(R) PRO/1000 Network Driver
10595 00:25:32.725074 <6>[ 1.635790] e1000: Copyright (c) 1999-2006 Intel Corporation.
10596 00:25:32.728545 <6>[ 1.641804] e1000e: Intel(R) PRO/1000 Network Driver
10597 00:25:32.735248 <6>[ 1.647020] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10598 00:25:32.741709 <6>[ 1.653205] igb: Intel(R) Gigabit Ethernet Network Driver
10599 00:25:32.748330 <6>[ 1.658854] igb: Copyright (c) 2007-2014 Intel Corporation.
10600 00:25:32.755901 <6>[ 1.664689] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10601 00:25:32.758959 <6>[ 1.671207] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10602 00:25:32.766009 <6>[ 1.677669] sky2: driver version 1.30
10603 00:25:32.772818 <6>[ 1.682588] usbcore: registered new device driver r8152-cfgselector
10604 00:25:32.779241 <6>[ 1.689134] usbcore: registered new interface driver r8152
10605 00:25:32.782567 <6>[ 1.694949] VFIO - User Level meta-driver version: 0.3
10606 00:25:32.791567 <6>[ 1.703162] usbcore: registered new interface driver usb-storage
10607 00:25:32.798169 <6>[ 1.709606] usbcore: registered new device driver onboard-usb-hub
10608 00:25:32.807187 <6>[ 1.718763] mt6397-rtc mt6359-rtc: registered as rtc0
10609 00:25:32.817176 <6>[ 1.724227] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-21T00:25:32 UTC (1718929532)
10610 00:25:32.820333 <6>[ 1.733785] i2c_dev: i2c /dev entries driver
10611 00:25:32.834051 <4>[ 1.745774] cpu cpu0: supply cpu not found, using dummy regulator
10612 00:25:32.840454 <4>[ 1.752217] cpu cpu1: supply cpu not found, using dummy regulator
10613 00:25:32.847122 <4>[ 1.758628] cpu cpu2: supply cpu not found, using dummy regulator
10614 00:25:32.854451 <4>[ 1.765034] cpu cpu3: supply cpu not found, using dummy regulator
10615 00:25:32.860841 <4>[ 1.771432] cpu cpu4: supply cpu not found, using dummy regulator
10616 00:25:32.867305 <4>[ 1.777834] cpu cpu5: supply cpu not found, using dummy regulator
10617 00:25:32.873776 <4>[ 1.784245] cpu cpu6: supply cpu not found, using dummy regulator
10618 00:25:32.880141 <4>[ 1.790647] cpu cpu7: supply cpu not found, using dummy regulator
10619 00:25:32.900955 <6>[ 1.812281] cpu cpu0: EM: created perf domain
10620 00:25:32.903652 <6>[ 1.817199] cpu cpu4: EM: created perf domain
10621 00:25:32.911073 <6>[ 1.822825] sdhci: Secure Digital Host Controller Interface driver
10622 00:25:32.917859 <6>[ 1.829255] sdhci: Copyright(c) Pierre Ossman
10623 00:25:32.924575 <6>[ 1.834213] Synopsys Designware Multimedia Card Interface Driver
10624 00:25:32.930944 <6>[ 1.840840] sdhci-pltfm: SDHCI platform and OF driver helper
10625 00:25:32.934198 <6>[ 1.840881] mmc0: CQHCI version 5.10
10626 00:25:32.941227 <6>[ 1.850876] ledtrig-cpu: registered to indicate activity on CPUs
10627 00:25:32.947955 <6>[ 1.857896] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10628 00:25:32.954386 <6>[ 1.864954] usbcore: registered new interface driver usbhid
10629 00:25:32.957852 <6>[ 1.870792] usbhid: USB HID core driver
10630 00:25:32.964258 <6>[ 1.874993] spi_master spi0: will run message pump with realtime priority
10631 00:25:33.010110 <6>[ 1.915496] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10632 00:25:33.028917 <6>[ 1.930900] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10633 00:25:33.035468 <6>[ 1.946692] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x15c14
10634 00:25:33.042775 <6>[ 1.947174] cros-ec-spi spi0.0: Chrome EC device registered
10635 00:25:33.045963 <6>[ 1.958738] mmc0: Command Queue Engine enabled
10636 00:25:33.052552 <6>[ 1.963446] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10637 00:25:33.059458 <6>[ 1.970846] mmcblk0: mmc0:0001 DA4128 116 GiB
10638 00:25:33.065950 <6>[ 1.971923] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10639 00:25:33.073060 <6>[ 1.980833] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10640 00:25:33.079471 <6>[ 1.985782] NET: Registered PF_PACKET protocol family
10641 00:25:33.082506 <6>[ 1.993299] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10642 00:25:33.089423 <6>[ 1.996170] 9pnet: Installing 9P2000 support
10643 00:25:33.092399 <6>[ 2.002218] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10644 00:25:33.099116 <5>[ 2.005861] Key type dns_resolver registered
10645 00:25:33.106264 <6>[ 2.011936] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10646 00:25:33.109213 <6>[ 2.016047] registered taskstats version 1
10647 00:25:33.112867 <5>[ 2.026511] Loading compiled-in X.509 certificates
10648 00:25:33.143256 <4>[ 2.048854] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10649 00:25:33.153062 <4>[ 2.059507] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10650 00:25:33.163393 <6>[ 2.075625] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10651 00:25:33.170590 <6>[ 2.082524] xhci-mtk 11200000.usb: xHCI Host Controller
10652 00:25:33.176959 <6>[ 2.088015] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10653 00:25:33.187337 <6>[ 2.095854] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10654 00:25:33.193612 <6>[ 2.105277] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10655 00:25:33.200489 <6>[ 2.111360] xhci-mtk 11200000.usb: xHCI Host Controller
10656 00:25:33.206654 <6>[ 2.116835] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10657 00:25:33.213528 <6>[ 2.124482] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10658 00:25:33.220623 <6>[ 2.132123] hub 1-0:1.0: USB hub found
10659 00:25:33.223678 <6>[ 2.136132] hub 1-0:1.0: 1 port detected
10660 00:25:33.230415 <6>[ 2.140405] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10661 00:25:33.236851 <6>[ 2.148940] hub 2-0:1.0: USB hub found
10662 00:25:33.240351 <6>[ 2.152945] hub 2-0:1.0: 1 port detected
10663 00:25:33.247372 <6>[ 2.159561] mtk-msdc 11f70000.mmc: Got CD GPIO
10664 00:25:33.260452 <6>[ 2.169427] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10665 00:25:33.270539 <6>[ 2.177831] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10666 00:25:33.277090 <6>[ 2.186256] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10667 00:25:33.287421 <6>[ 2.194602] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10668 00:25:33.294248 <6>[ 2.202941] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10669 00:25:33.304378 <6>[ 2.211279] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10670 00:25:33.310813 <6>[ 2.219616] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10671 00:25:33.320877 <6>[ 2.227954] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10672 00:25:33.327542 <6>[ 2.236292] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10673 00:25:33.337823 <6>[ 2.244630] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10674 00:25:33.344781 <6>[ 2.252967] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10675 00:25:33.354671 <6>[ 2.261306] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10676 00:25:33.361406 <6>[ 2.269651] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10677 00:25:33.370968 <6>[ 2.277989] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10678 00:25:33.377685 <6>[ 2.286328] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10679 00:25:33.384638 <6>[ 2.295043] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10680 00:25:33.390940 <6>[ 2.302221] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10681 00:25:33.397666 <6>[ 2.309040] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10682 00:25:33.403864 <6>[ 2.315810] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10683 00:25:33.414285 <6>[ 2.322755] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10684 00:25:33.421022 <6>[ 2.329630] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10685 00:25:33.431065 <6>[ 2.338783] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10686 00:25:33.440500 <6>[ 2.347903] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10687 00:25:33.450545 <6>[ 2.357196] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10688 00:25:33.460794 <6>[ 2.366665] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10689 00:25:33.467252 <6>[ 2.376132] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10690 00:25:33.477141 <6>[ 2.385253] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10691 00:25:33.487014 <6>[ 2.394719] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10692 00:25:33.496980 <6>[ 2.403839] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10693 00:25:33.506738 <6>[ 2.413133] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10694 00:25:33.516633 <6>[ 2.423293] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10695 00:25:33.526863 <6>[ 2.434966] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10696 00:25:33.534630 <6>[ 2.446109] Trying to probe devices needed for running init ...
10697 00:25:33.545117 <3>[ 2.453364] mt8192-audio 11210000.syscon:mt8192-afe-pcm: could not get audiosys reset:-517
10698 00:25:33.630594 <6>[ 2.539138] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10699 00:25:33.660146 <6>[ 2.572128] hub 2-1:1.0: USB hub found
10700 00:25:33.663518 <6>[ 2.576646] hub 2-1:1.0: 3 ports detected
10701 00:25:33.674394 <6>[ 2.586184] hub 2-1:1.0: USB hub found
10702 00:25:33.677987 <6>[ 2.590584] hub 2-1:1.0: 3 ports detected
10703 00:25:33.782385 <6>[ 2.690832] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10704 00:25:33.936892 <6>[ 2.848868] hub 1-1:1.0: USB hub found
10705 00:25:33.940369 <6>[ 2.853355] hub 1-1:1.0: 4 ports detected
10706 00:25:33.952149 <6>[ 2.864224] hub 1-1:1.0: USB hub found
10707 00:25:33.955526 <6>[ 2.868633] hub 1-1:1.0: 4 ports detected
10708 00:25:34.018098 <6>[ 2.927099] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10709 00:25:34.126480 <6>[ 3.035565] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10710 00:25:34.162683 <4>[ 3.071239] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10711 00:25:34.171988 <4>[ 3.080366] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10712 00:25:34.211280 <6>[ 3.123864] r8152 2-1.3:1.0 eth0: v1.12.13
10713 00:25:34.285632 <6>[ 3.194855] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10714 00:25:34.418475 <6>[ 3.330878] hub 1-1.4:1.0: USB hub found
10715 00:25:34.421908 <6>[ 3.335559] hub 1-1.4:1.0: 2 ports detected
10716 00:25:34.434538 <6>[ 3.346444] hub 1-1.4:1.0: USB hub found
10717 00:25:34.437613 <6>[ 3.351058] hub 1-1.4:1.0: 2 ports detected
10718 00:25:34.733850 <6>[ 3.642891] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10719 00:25:34.925797 <6>[ 3.834892] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10720 00:25:35.944321 <6>[ 4.856598] r8152 2-1.3:1.0 eth0: carrier on
10721 00:25:38.062511 <5>[ 4.878652] Sending DHCP requests .., OK
10722 00:25:38.068881 <6>[ 6.979179] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.21
10723 00:25:38.072014 <6>[ 6.987473] IP-Config: Complete:
10724 00:25:38.085343 <6>[ 6.990973] device=eth0, hwaddr=00:e0:4c:72:2d:d6, ipaddr=192.168.201.21, mask=255.255.255.0, gw=192.168.201.1
10725 00:25:38.091848 <6>[ 7.001683] host=mt8192-asurada-spherion-r0-cbg-1, domain=lava-rack, nis-domain=(none)
10726 00:25:38.098419 <6>[ 7.010299] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10727 00:25:38.105386 <6>[ 7.010308] nameserver0=192.168.201.1
10728 00:25:38.108814 <6>[ 7.022437] clk: Disabling unused clocks
10729 00:25:38.111876 <6>[ 7.027966] ALSA device list:
10730 00:25:38.118644 <6>[ 7.031250] No soundcards found.
10731 00:25:38.126166 <6>[ 7.039144] Freeing unused kernel memory: 8512K
10732 00:25:38.129636 <6>[ 7.044041] Run /init as init process
10733 00:25:38.139399 Loading, please wait...
10734 00:25:38.164505 Starting systemd-udevd version 252.22-1~deb12u1
10735 00:25:38.421762 <6>[ 7.330873] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10736 00:25:38.428184 <6>[ 7.330874] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10737 00:25:38.439093 <6>[ 7.348421] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10738 00:25:38.449363 <6>[ 7.350768] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10739 00:25:38.452322 <6>[ 7.351411] remoteproc remoteproc0: scp is available
10740 00:25:38.458918 <6>[ 7.351462] remoteproc remoteproc0: powering up scp
10741 00:25:38.465644 <6>[ 7.351470] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10742 00:25:38.472507 <6>[ 7.351498] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10743 00:25:38.479333 <6>[ 7.363860] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10744 00:25:38.488662 <6>[ 7.365320] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10745 00:25:38.495349 <6>[ 7.370526] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10746 00:25:38.505209 <3>[ 7.377728] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10747 00:25:38.514682 <4>[ 7.384349] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10748 00:25:38.521251 <3>[ 7.390080] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10749 00:25:38.531132 <6>[ 7.398371] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10750 00:25:38.537752 <3>[ 7.406735] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10751 00:25:38.544579 <4>[ 7.410039] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10752 00:25:38.551247 <6>[ 7.410696] mc: Linux media interface: v0.10
10753 00:25:38.557774 <6>[ 7.414369] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10754 00:25:38.564511 <4>[ 7.419009] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10755 00:25:38.574338 <6>[ 7.423375] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10756 00:25:38.581001 <3>[ 7.425680] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10757 00:25:38.591366 <3>[ 7.425697] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10758 00:25:38.597467 <3>[ 7.425703] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10759 00:25:38.607460 <3>[ 7.425713] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10760 00:25:38.614240 <3>[ 7.425722] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10761 00:25:38.620853 <3>[ 7.425767] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10762 00:25:38.630581 <3>[ 7.425823] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10763 00:25:38.637435 <3>[ 7.425828] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10764 00:25:38.647288 <3>[ 7.425831] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10765 00:25:38.653825 <3>[ 7.425877] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10766 00:25:38.663913 <3>[ 7.425882] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10767 00:25:38.670253 <3>[ 7.425886] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10768 00:25:38.680481 <3>[ 7.425889] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10769 00:25:38.687075 <3>[ 7.425892] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10770 00:25:38.693693 <3>[ 7.425915] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10771 00:25:38.700006 <6>[ 7.440439] videodev: Linux video capture interface: v2.00
10772 00:25:38.706796 <6>[ 7.447765] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10773 00:25:38.716729 <6>[ 7.447773] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10774 00:25:38.726862 <6>[ 7.447786] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10775 00:25:38.733128 <6>[ 7.456247] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10776 00:25:38.743201 <6>[ 7.476701] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10777 00:25:38.749814 <6>[ 7.476711] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10778 00:25:38.756470 <6>[ 7.493054] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10779 00:25:38.763036 <6>[ 7.495971] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10780 00:25:38.769576 <6>[ 7.495980] pci_bus 0000:00: root bus resource [bus 00-ff]
10781 00:25:38.776090 <6>[ 7.495988] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10782 00:25:38.785950 <6>[ 7.495994] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10783 00:25:38.792499 <6>[ 7.496035] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10784 00:25:38.799390 <6>[ 7.496059] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10785 00:25:38.806034 <6>[ 7.496175] pci 0000:00:00.0: supports D1 D2
10786 00:25:38.812700 <6>[ 7.496179] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10787 00:25:38.819300 <6>[ 7.498191] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10788 00:25:38.825774 <6>[ 7.498352] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10789 00:25:38.832621 <6>[ 7.498385] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10790 00:25:38.842213 <6>[ 7.498407] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10791 00:25:38.848739 <6>[ 7.498426] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10792 00:25:38.852255 <6>[ 7.498548] pci 0000:01:00.0: supports D1 D2
10793 00:25:38.858955 <6>[ 7.498552] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10794 00:25:38.865327 <6>[ 7.499508] remoteproc remoteproc0: remote processor scp is now up
10795 00:25:38.871848 <6>[ 7.510786] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10796 00:25:38.881940 <4>[ 7.511792] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10797 00:25:38.888285 <4>[ 7.511792] Fallback method does not support PEC.
10798 00:25:38.894971 <6>[ 7.517536] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10799 00:25:38.904691 <6>[ 7.523846] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10800 00:25:38.915122 <6>[ 7.533280] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10801 00:25:38.921752 <6>[ 7.539978] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10802 00:25:38.928156 <6>[ 7.539995] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10803 00:25:38.938178 <6>[ 7.542844] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10804 00:25:38.948005 <6>[ 7.548725] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10805 00:25:38.954861 <6>[ 7.556158] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10806 00:25:38.957937 <6>[ 7.589148] Bluetooth: Core ver 2.22
10807 00:25:38.968137 <6>[ 7.596661] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10808 00:25:38.974508 <6>[ 7.604740] NET: Registered PF_BLUETOOTH protocol family
10809 00:25:38.977857 <6>[ 7.612806] pci 0000:00:00.0: PCI bridge to [bus 01]
10810 00:25:38.984598 <6>[ 7.618503] Bluetooth: HCI device and connection manager initialized
10811 00:25:38.994470 <6>[ 7.626329] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10812 00:25:39.001450 <6>[ 7.627644] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10813 00:25:39.011110 <6>[ 7.628821] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10814 00:25:39.017590 <6>[ 7.628930] usbcore: registered new interface driver uvcvideo
10815 00:25:39.024650 <6>[ 7.634147] Bluetooth: HCI socket layer initialized
10816 00:25:39.031154 <6>[ 7.643469] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10817 00:25:39.034239 <6>[ 7.650905] Bluetooth: L2CAP socket layer initialized
10818 00:25:39.040776 <6>[ 7.659930] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10819 00:25:39.047314 <6>[ 7.666458] Bluetooth: SCO socket layer initialized
10820 00:25:39.054139 <6>[ 7.666960] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10821 00:25:39.057771 <6>[ 7.675126] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10822 00:25:39.064287 <6>[ 7.730010] usbcore: registered new interface driver btusb
10823 00:25:39.074188 <4>[ 7.730578] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10824 00:25:39.080255 <3>[ 7.730586] Bluetooth: hci0: Failed to load firmware file (-2)
10825 00:25:39.087273 <3>[ 7.730600] Bluetooth: hci0: Failed to set up firmware (-2)
10826 00:25:39.097180 <4>[ 7.730606] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10827 00:25:39.106908 <5>[ 7.761565] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10828 00:25:39.131748 <5>[ 8.041059] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10829 00:25:39.137887 <5>[ 8.048172] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10830 00:25:39.148078 <4>[ 8.056602] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10831 00:25:39.151060 <6>[ 8.065475] cfg80211: failed to load regulatory.db
10832 00:25:39.192250 <6>[ 8.101720] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10833 00:25:39.198576 <6>[ 8.109217] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10834 00:25:39.223248 <6>[ 8.136105] mt7921e 0000:01:00.0: ASIC revision: 79610010
10835 00:25:39.324920 <6>[ 8.234575] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10836 00:25:39.328462 <6>[ 8.234575]
10837 00:25:39.331591 Begin: Loading essential drivers ... done.
10838 00:25:39.334977 Begin: Running /scripts/init-premount ... done.
10839 00:25:39.341669 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10840 00:25:39.351691 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10841 00:25:39.354756 Device /sys/class/net/eth0 found
10842 00:25:39.354848 done.
10843 00:25:39.361427 Begin: Waiting up to 180 secs for any network device to become available ... done.
10844 00:25:39.390318 IP-Config: eth0 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10845 00:25:39.396729 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10846 00:25:39.403118 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10847 00:25:39.410086 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10848 00:25:39.416622 host : mt8192-asurada-spherion-r0-cbg-1
10849 00:25:39.422868 domain : lava-rack
10850 00:25:39.426502 rootserver: 192.168.201.1 rootpath:
10851 00:25:39.426571 filename :
10852 00:25:39.429807 done.
10853 00:25:39.433200 Begin: Running /scripts/nfs-bottom ... done.
10854 00:25:39.453784 Begin: Running /scripts/init-bottom ... done.
10855 00:25:39.593162 <6>[ 8.503015] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10856 00:25:40.737856 <6>[ 9.650664] NET: Registered PF_INET6 protocol family
10857 00:25:40.744737 <6>[ 9.657945] Segment Routing with IPv6
10858 00:25:40.748087 <6>[ 9.661941] In-situ OAM (IOAM) with IPv6
10859 00:25:40.913159 <30>[ 9.799683] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10860 00:25:40.919828 <30>[ 9.832843] systemd[1]: Detected architecture arm64.
10861 00:25:40.927475
10862 00:25:40.930241 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10863 00:25:40.930335
10864 00:25:40.954802 <30>[ 9.867889] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10865 00:25:41.884394 <30>[ 10.794078] systemd[1]: Queued start job for default target graphical.target.
10866 00:25:41.929927 <30>[ 10.839930] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10867 00:25:41.936948 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10868 00:25:41.958739 <30>[ 10.868820] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10869 00:25:41.968995 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10870 00:25:41.986826 <30>[ 10.896663] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10871 00:25:41.996823 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10872 00:25:42.015269 <30>[ 10.925080] systemd[1]: Created slice user.slice - User and Session Slice.
10873 00:25:42.021678 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10874 00:25:42.045204 <30>[ 10.951769] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10875 00:25:42.054900 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10876 00:25:42.076621 <30>[ 10.983159] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10877 00:25:42.083366 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10878 00:25:42.111873 <30>[ 11.011527] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10879 00:25:42.121717 <30>[ 11.031441] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10880 00:25:42.128324 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10881 00:25:42.145167 <30>[ 11.055271] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10882 00:25:42.155028 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10883 00:25:42.173386 <30>[ 11.083401] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10884 00:25:42.183329 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10885 00:25:42.197698 <30>[ 11.111017] systemd[1]: Reached target paths.target - Path Units.
10886 00:25:42.207730 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10887 00:25:42.224888 <30>[ 11.134925] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10888 00:25:42.231582 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10889 00:25:42.245821 <30>[ 11.158886] systemd[1]: Reached target slices.target - Slice Units.
10890 00:25:42.255568 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10891 00:25:42.270454 <30>[ 11.183409] systemd[1]: Reached target swap.target - Swaps.
10892 00:25:42.277007 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10893 00:25:42.297325 <30>[ 11.207424] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10894 00:25:42.307352 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10895 00:25:42.326167 <30>[ 11.235868] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10896 00:25:42.335743 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10897 00:25:42.356111 <30>[ 11.265896] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10898 00:25:42.365733 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10899 00:25:42.382379 <30>[ 11.292343] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10900 00:25:42.392637 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10901 00:25:42.409730 <30>[ 11.319688] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10902 00:25:42.416229 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10903 00:25:42.434491 <30>[ 11.344390] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10904 00:25:42.444442 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10905 00:25:42.464173 <30>[ 11.373954] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10906 00:25:42.473837 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10907 00:25:42.489905 <30>[ 11.399365] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10908 00:25:42.499187 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10909 00:25:42.553285 <30>[ 11.463129] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10910 00:25:42.559872 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10911 00:25:42.581348 <30>[ 11.491596] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10912 00:25:42.588042 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10913 00:25:42.615551 <30>[ 11.525477] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10914 00:25:42.622239 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10915 00:25:42.647992 <30>[ 11.551268] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10916 00:25:42.662576 <30>[ 11.572451] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10917 00:25:42.672386 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10918 00:25:42.695021 <30>[ 11.604874] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10919 00:25:42.701789 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10920 00:25:42.726800 <30>[ 11.636455] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10921 00:25:42.732957 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10922 00:25:42.758664 <30>[ 11.668736] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10923 00:25:42.768542 Startin<6>[ 11.678456] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10924 00:25:42.775082 g [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10925 00:25:42.798996 <30>[ 11.708535] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10926 00:25:42.808648 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10927 00:25:42.830395 <30>[ 11.740552] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10928 00:25:42.837272 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10929 00:25:42.862715 <30>[ 11.772438] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10930 00:25:42.869007 Startin<6>[ 11.781249] fuse: init (API version 7.37)
10931 00:25:42.875548 g [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10932 00:25:42.903011 <30>[ 11.812614] systemd[1]: Starting systemd-journald.service - Journal Service...
10933 00:25:42.909271 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10934 00:25:42.940622 <30>[ 11.850668] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10935 00:25:42.947375 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10936 00:25:42.975115 <30>[ 11.881739] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10937 00:25:42.981512 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10938 00:25:43.007643 <30>[ 11.917759] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10939 00:25:43.017934 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10940 00:25:43.043313 <30>[ 11.953078] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10941 00:25:43.049603 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10942 00:25:43.077823 <30>[ 11.987774] systemd[1]: Started systemd-journald.service - Journal Service.
10943 00:25:43.084852 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10944 00:25:43.105586 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10945 00:25:43.122242 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10946 00:25:43.141760 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10947 00:25:43.163426 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10948 00:25:43.183388 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10949 00:25:43.203425 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10950 00:25:43.218139 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10951 00:25:43.238352 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10952 00:25:43.259777 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10953 00:25:43.279879 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10954 00:25:43.298680 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10955 00:25:43.318525 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10956 00:25:43.338867 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10957 00:25:43.359825 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10958 00:25:43.414213 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10959 00:25:43.435798 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10960 00:25:43.455597 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10961 00:25:43.479120 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10962 00:25:43.514294 Starting [0;1;39msystemd-sysctl.se…c<46>[ 12.424521] systemd-journald[312]: Received client request to flush runtime journal.
10963 00:25:43.517613 e[0m - Apply Kernel Variables...
10964 00:25:43.579285 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10965 00:25:43.835375 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10966 00:25:43.854672 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10967 00:25:43.873696 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10968 00:25:43.894815 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10969 00:25:44.469019 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10970 00:25:44.917293 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10971 00:25:44.938730 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10972 00:25:44.990314 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10973 00:25:45.063788 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10974 00:25:45.081113 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10975 00:25:45.096720 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10976 00:25:45.141994 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10977 00:25:45.170099 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10978 00:25:45.360231 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10979 00:25:45.431910 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10980 00:25:45.452522 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10981 00:25:45.486196 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10982 00:25:45.651580 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10983 00:25:45.674498 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10984 00:25:45.791189 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10985 00:25:45.805824 <6>[ 14.719294] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10986 00:25:45.851414 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10987 00:25:45.894951 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10988 00:25:45.913105 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10989 00:25:46.003054 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10990 00:25:46.027140 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10991 00:25:46.088893 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10992 00:25:46.115796 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10993 00:25:46.138617 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10994 00:25:46.162115 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10995 00:25:46.178952 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10996 00:25:46.197083 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10997 00:25:46.213467 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10998 00:25:46.229404 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10999 00:25:46.253321 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11000 00:25:46.271789 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11001 00:25:46.288950 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11002 00:25:46.319013 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11003 00:25:46.340396 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11004 00:25:46.356979 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11005 00:25:46.375761 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11006 00:25:46.393994 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11007 00:25:46.400314 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11008 00:25:46.439761 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11009 00:25:46.474089 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11010 00:25:46.553224 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11011 00:25:46.580002 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11012 00:25:46.647468 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11013 00:25:46.699596 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11014 00:25:46.746395 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11015 00:25:46.762053 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11016 00:25:46.778418 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11017 00:25:46.814838 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11018 00:25:46.975516 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11019 00:25:46.991269 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11020 00:25:47.008669 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11021 00:25:47.069389 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11022 00:25:47.104940 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11023 00:25:47.183985
11024 00:25:47.187502 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11025 00:25:47.187608
11026 00:25:47.190895 debian-bookworm-arm64 login: root (automatic login)
11027 00:25:47.191012
11028 00:25:47.490068 Linux debian-bookworm-arm64 6.1.94-cip23 #1 SMP PREEMPT Fri Jun 21 00:04:56 UTC 2024 aarch64
11029 00:25:47.490647
11030 00:25:47.496742 The programs included with the Debian GNU/Linux system are free software;
11031 00:25:47.503142 the exact distribution terms for each program are described in the
11032 00:25:47.506779 individual files in /usr/share/doc/*/copyright.
11033 00:25:47.506856
11034 00:25:47.513325 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11035 00:25:47.516142 permitted by applicable law.
11036 00:25:48.490826 Matched prompt #10: / #
11038 00:25:48.491973 Setting prompt string to ['/ #']
11039 00:25:48.492438 end: 2.2.5.1 login-action (duration 00:00:18) [common]
11041 00:25:48.493483 end: 2.2.5 auto-login-action (duration 00:00:18) [common]
11042 00:25:48.493939 start: 2.2.6 expect-shell-connection (timeout 00:03:38) [common]
11043 00:25:48.494306 Setting prompt string to ['/ #']
11044 00:25:48.494619 Forcing a shell prompt, looking for ['/ #']
11046 00:25:48.545410 / #
11047 00:25:48.546079 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11048 00:25:48.546469 Waiting using forced prompt support (timeout 00:02:30)
11049 00:25:48.551794
11050 00:25:48.552657 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11051 00:25:48.553233 start: 2.2.7 export-device-env (timeout 00:03:38) [common]
11053 00:25:48.654703 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14479188/extract-nfsrootfs-0_775cf7'
11054 00:25:48.661072 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14479188/extract-nfsrootfs-0_775cf7'
11056 00:25:48.762787 / # export NFS_SERVER_IP='192.168.201.1'
11057 00:25:48.769604 export NFS_SERVER_IP='192.168.201.1'
11058 00:25:48.770498 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11059 00:25:48.771069 end: 2.2 depthcharge-retry (duration 00:01:23) [common]
11060 00:25:48.771635 end: 2 depthcharge-action (duration 00:01:23) [common]
11061 00:25:48.772183 start: 3 lava-test-retry (timeout 00:07:57) [common]
11062 00:25:48.772775 start: 3.1 lava-test-shell (timeout 00:07:57) [common]
11063 00:25:48.773210 Using namespace: common
11065 00:25:48.874575 / # #
11066 00:25:48.875225 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11067 00:25:48.880616 #
11068 00:25:48.881444 Using /lava-14479188
11070 00:25:48.982523 / # export SHELL=/bin/bash
11071 00:25:48.989223 export SHELL=/bin/bash
11073 00:25:49.090822 / # . /lava-14479188/environment
11074 00:25:49.097007 . /lava-14479188/environment
11076 00:25:49.205223 / # /lava-14479188/bin/lava-test-runner /lava-14479188/0
11077 00:25:49.205873 Test shell timeout: 10s (minimum of the action and connection timeout)
11078 00:25:49.212138 /lava-14479188/bin/lava-test-runner /lava-14479188/0
11079 00:25:49.488220 + export TESTRUN_ID=0_timesync-off
11080 00:25:49.490614 + TESTRUN_ID=0_timesync-off
11081 00:25:49.494344 + cd /lava-14479188/0/tests/0_timesync-off
11082 00:25:49.497031 ++ cat uuid
11083 00:25:49.503387 + UUID=14479188_1.6.2.3.1
11084 00:25:49.503834 + set +x
11085 00:25:49.510039 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14479188_1.6.2.3.1>
11086 00:25:49.510754 Received signal: <STARTRUN> 0_timesync-off 14479188_1.6.2.3.1
11087 00:25:49.511242 Starting test lava.0_timesync-off (14479188_1.6.2.3.1)
11088 00:25:49.511772 Skipping test definition patterns.
11089 00:25:49.513581 + systemctl stop systemd-timesyncd
11090 00:25:49.588521 + set +x
11091 00:25:49.591679 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14479188_1.6.2.3.1>
11092 00:25:49.592309 Received signal: <ENDRUN> 0_timesync-off 14479188_1.6.2.3.1
11093 00:25:49.592686 Ending use of test pattern.
11094 00:25:49.593016 Ending test lava.0_timesync-off (14479188_1.6.2.3.1), duration 0.08
11096 00:25:49.671952 + export TESTRUN_ID=1_kselftest-dt
11097 00:25:49.674988 + TESTRUN_ID=1_kselftest-dt
11098 00:25:49.678685 + cd /lava-14479188/0/tests/1_kselftest-dt
11099 00:25:49.681595 ++ cat uuid
11100 00:25:49.686094 + UUID=14479188_1.6.2.3.5
11101 00:25:49.686484 + set +x
11102 00:25:49.692588 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 14479188_1.6.2.3.5>
11103 00:25:49.693291 Received signal: <STARTRUN> 1_kselftest-dt 14479188_1.6.2.3.5
11104 00:25:49.693645 Starting test lava.1_kselftest-dt (14479188_1.6.2.3.5)
11105 00:25:49.694011 Skipping test definition patterns.
11106 00:25:49.696161 + cd ./automated/linux/kselftest/
11107 00:25:49.719167 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.94-cip23/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11108 00:25:49.761791 INFO: install_deps skipped
11109 00:25:50.258038 --2024-06-21 00:25:49-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.94-cip23/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11110 00:25:50.265177 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11111 00:25:50.390622 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11112 00:25:50.518257 HTTP request sent, awaiting response... 200 OK
11113 00:25:50.521287 Length: 1642760 (1.6M) [application/octet-stream]
11114 00:25:50.525366 Saving to: 'kselftest_armhf.tar.gz'
11115 00:25:50.525797
11116 00:25:50.526133
11117 00:25:50.774526 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
11118 00:25:51.031110 kselftest_armhf.tar 2%[ ] 47.81K 188KB/s
11119 00:25:51.333114 kselftest_armhf.tar 13%[=> ] 217.50K 427KB/s
11120 00:25:51.467301 kselftest_armhf.tar 50%[=========> ] 809.99K 1001KB/s
11121 00:25:51.473685 kselftest_armhf.tar 100%[===================>] 1.57M 1.66MB/s in 0.9s
11122 00:25:51.473774
11123 00:25:51.617428 2024-06-21 00:25:51 (1.66 MB/s) - 'kselftest_armhf.tar.gz' saved [1642760/1642760]
11124 00:25:51.617553
11125 00:25:56.088940 skiplist:
11126 00:25:56.092522 ========================================
11127 00:25:56.095432 ========================================
11128 00:25:56.168980 ============== Tests to run ===============
11129 00:25:56.172575 ===========End Tests to run ===============
11130 00:25:56.177979 shardfile-dt fail
11131 00:25:56.200391 ./kselftest.sh: 131: cannot open /lava-14479188/0/tests/1_kselftest-dt/automated/linux/kselftest/output/kselftest.txt: No such file
11132 00:25:56.204071 + ../../utils/send-to-lava.sh ./output/result.txt
11133 00:25:56.263275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=fail>
11134 00:25:56.263393 + set +x
11135 00:25:56.263657 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=fail
11137 00:25:56.270345 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 14479188_1.6.2.3.5>
11138 00:25:56.270422 <LAVA_TEST_RUNNER EXIT>
11139 00:25:56.270654 Received signal: <ENDRUN> 1_kselftest-dt 14479188_1.6.2.3.5
11140 00:25:56.270747 Ending use of test pattern.
11141 00:25:56.270832 Ending test lava.1_kselftest-dt (14479188_1.6.2.3.5), duration 6.58
11143 00:25:56.271153 ok: lava_test_shell seems to have completed
11144 00:25:56.271268 shardfile-dt: fail
11145 00:25:56.271379 end: 3.1 lava-test-shell (duration 00:00:07) [common]
11146 00:25:56.271488 end: 3 lava-test-retry (duration 00:00:07) [common]
11147 00:25:56.271593 start: 4 finalize (timeout 00:07:50) [common]
11148 00:25:56.271702 start: 4.1 power-off (timeout 00:00:30) [common]
11149 00:25:56.271925 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-1', '--port=1', '--command=off']
11150 00:25:58.367892 >> Command sent successfully.
11151 00:25:58.374536 Returned 0 in 2 seconds
11152 00:25:58.475226 end: 4.1 power-off (duration 00:00:02) [common]
11154 00:25:58.476500 start: 4.2 read-feedback (timeout 00:07:48) [common]
11155 00:25:58.477741 Listened to connection for namespace 'common' for up to 1s
11156 00:25:58.478505 Listened to connection for namespace 'common' for up to 1s
11157 00:25:59.478529 Finalising connection for namespace 'common'
11158 00:25:59.479201 Disconnecting from shell: Finalise
11159 00:25:59.479616 / #
11160 00:25:59.580594 end: 4.2 read-feedback (duration 00:00:01) [common]
11161 00:25:59.581337 end: 4 finalize (duration 00:00:03) [common]
11162 00:25:59.581998 Cleaning after the job
11163 00:25:59.582593 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14479188/tftp-deploy-57w3ztgi/ramdisk
11164 00:25:59.586845 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14479188/tftp-deploy-57w3ztgi/kernel
11165 00:25:59.597171 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14479188/tftp-deploy-57w3ztgi/dtb
11166 00:25:59.597331 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14479188/tftp-deploy-57w3ztgi/nfsrootfs
11167 00:25:59.661236 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14479188/tftp-deploy-57w3ztgi/modules
11168 00:25:59.667577 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14479188
11169 00:26:00.223956 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14479188
11170 00:26:00.224139 Job finished correctly