Boot log: mt8192-asurada-spherion-r0
- Errors: 3
- Kernel Errors: 35
- Boot result: FAIL
- Warnings: 1
- Kernel Warnings: 25
1 00:25:56.148810 lava-dispatcher, installed at version: 2024.03
2 00:25:56.149002 start: 0 validate
3 00:25:56.149134 Start time: 2024-06-21 00:25:56.149125+00:00 (UTC)
4 00:25:56.149249 Using caching service: 'http://localhost/cache/?uri=%s'
5 00:25:56.149378 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 00:25:56.413312 Using caching service: 'http://localhost/cache/?uri=%s'
7 00:25:56.413482 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.94-cip23%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 00:25:56.662649 Using caching service: 'http://localhost/cache/?uri=%s'
9 00:25:56.662826 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.94-cip23%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 00:25:56.921676 Using caching service: 'http://localhost/cache/?uri=%s'
11 00:25:56.922397 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 00:25:57.176616 Using caching service: 'http://localhost/cache/?uri=%s'
13 00:25:57.177407 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.94-cip23%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 00:25:57.446857 validate duration: 1.30
16 00:25:57.448464 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 00:25:57.449082 start: 1.1 download-retry (timeout 00:10:00) [common]
18 00:25:57.449584 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 00:25:57.450221 Not decompressing ramdisk as can be used compressed.
20 00:25:57.450725 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 00:25:57.451160 saving as /var/lib/lava/dispatcher/tmp/14479210/tftp-deploy-rkh18ac3/ramdisk/initrd.cpio.gz
22 00:25:57.451537 total size: 5628169 (5 MB)
23 00:25:57.456741 progress 0 % (0 MB)
24 00:25:57.465178 progress 5 % (0 MB)
25 00:25:57.471474 progress 10 % (0 MB)
26 00:25:57.475495 progress 15 % (0 MB)
27 00:25:57.479253 progress 20 % (1 MB)
28 00:25:57.482355 progress 25 % (1 MB)
29 00:25:57.485231 progress 30 % (1 MB)
30 00:25:57.487975 progress 35 % (1 MB)
31 00:25:57.490120 progress 40 % (2 MB)
32 00:25:57.492536 progress 45 % (2 MB)
33 00:25:57.494435 progress 50 % (2 MB)
34 00:25:57.496540 progress 55 % (2 MB)
35 00:25:57.498532 progress 60 % (3 MB)
36 00:25:57.500214 progress 65 % (3 MB)
37 00:25:57.502114 progress 70 % (3 MB)
38 00:25:57.503674 progress 75 % (4 MB)
39 00:25:57.505370 progress 80 % (4 MB)
40 00:25:57.506904 progress 85 % (4 MB)
41 00:25:57.508520 progress 90 % (4 MB)
42 00:25:57.510063 progress 95 % (5 MB)
43 00:25:57.511471 progress 100 % (5 MB)
44 00:25:57.511681 5 MB downloaded in 0.06 s (89.21 MB/s)
45 00:25:57.511833 end: 1.1.1 http-download (duration 00:00:00) [common]
47 00:25:57.512080 end: 1.1 download-retry (duration 00:00:00) [common]
48 00:25:57.512168 start: 1.2 download-retry (timeout 00:10:00) [common]
49 00:25:57.512254 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 00:25:57.512387 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.94-cip23/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 00:25:57.512469 saving as /var/lib/lava/dispatcher/tmp/14479210/tftp-deploy-rkh18ac3/kernel/Image
52 00:25:57.512531 total size: 54813184 (52 MB)
53 00:25:57.512593 No compression specified
54 00:25:57.513653 progress 0 % (0 MB)
55 00:25:57.527423 progress 5 % (2 MB)
56 00:25:57.541261 progress 10 % (5 MB)
57 00:25:57.554988 progress 15 % (7 MB)
58 00:25:57.568836 progress 20 % (10 MB)
59 00:25:57.582487 progress 25 % (13 MB)
60 00:25:57.596030 progress 30 % (15 MB)
61 00:25:57.609689 progress 35 % (18 MB)
62 00:25:57.623496 progress 40 % (20 MB)
63 00:25:57.637192 progress 45 % (23 MB)
64 00:25:57.651025 progress 50 % (26 MB)
65 00:25:57.664870 progress 55 % (28 MB)
66 00:25:57.678674 progress 60 % (31 MB)
67 00:25:57.692356 progress 65 % (34 MB)
68 00:25:57.705923 progress 70 % (36 MB)
69 00:25:57.719755 progress 75 % (39 MB)
70 00:25:57.733690 progress 80 % (41 MB)
71 00:25:57.747418 progress 85 % (44 MB)
72 00:25:57.761215 progress 90 % (47 MB)
73 00:25:57.774975 progress 95 % (49 MB)
74 00:25:57.788424 progress 100 % (52 MB)
75 00:25:57.788653 52 MB downloaded in 0.28 s (189.32 MB/s)
76 00:25:57.788803 end: 1.2.1 http-download (duration 00:00:00) [common]
78 00:25:57.789045 end: 1.2 download-retry (duration 00:00:00) [common]
79 00:25:57.789133 start: 1.3 download-retry (timeout 00:10:00) [common]
80 00:25:57.789219 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 00:25:57.789356 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.94-cip23/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 00:25:57.789426 saving as /var/lib/lava/dispatcher/tmp/14479210/tftp-deploy-rkh18ac3/dtb/mt8192-asurada-spherion-r0.dtb
83 00:25:57.789487 total size: 47258 (0 MB)
84 00:25:57.789549 No compression specified
85 00:25:57.790719 progress 69 % (0 MB)
86 00:25:57.790995 progress 100 % (0 MB)
87 00:25:57.791149 0 MB downloaded in 0.00 s (27.16 MB/s)
88 00:25:57.791270 end: 1.3.1 http-download (duration 00:00:00) [common]
90 00:25:57.791496 end: 1.3 download-retry (duration 00:00:00) [common]
91 00:25:57.791582 start: 1.4 download-retry (timeout 00:10:00) [common]
92 00:25:57.791665 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 00:25:57.791775 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 00:25:57.791843 saving as /var/lib/lava/dispatcher/tmp/14479210/tftp-deploy-rkh18ac3/nfsrootfs/full.rootfs.tar
95 00:25:57.791905 total size: 120894716 (115 MB)
96 00:25:57.791967 Using unxz to decompress xz
97 00:25:57.795978 progress 0 % (0 MB)
98 00:25:58.141807 progress 5 % (5 MB)
99 00:25:58.492246 progress 10 % (11 MB)
100 00:25:58.837194 progress 15 % (17 MB)
101 00:25:59.164189 progress 20 % (23 MB)
102 00:25:59.462085 progress 25 % (28 MB)
103 00:25:59.848291 progress 30 % (34 MB)
104 00:26:00.220860 progress 35 % (40 MB)
105 00:26:00.393804 progress 40 % (46 MB)
106 00:26:00.574437 progress 45 % (51 MB)
107 00:26:00.884398 progress 50 % (57 MB)
108 00:26:01.255289 progress 55 % (63 MB)
109 00:26:01.602024 progress 60 % (69 MB)
110 00:26:01.942838 progress 65 % (74 MB)
111 00:26:02.286012 progress 70 % (80 MB)
112 00:26:02.644471 progress 75 % (86 MB)
113 00:26:02.986331 progress 80 % (92 MB)
114 00:26:03.323802 progress 85 % (98 MB)
115 00:26:03.675713 progress 90 % (103 MB)
116 00:26:04.001484 progress 95 % (109 MB)
117 00:26:04.372067 progress 100 % (115 MB)
118 00:26:04.377311 115 MB downloaded in 6.59 s (17.51 MB/s)
119 00:26:04.377561 end: 1.4.1 http-download (duration 00:00:07) [common]
121 00:26:04.377834 end: 1.4 download-retry (duration 00:00:07) [common]
122 00:26:04.377929 start: 1.5 download-retry (timeout 00:09:53) [common]
123 00:26:04.378017 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 00:26:04.378174 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.94-cip23/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 00:26:04.378244 saving as /var/lib/lava/dispatcher/tmp/14479210/tftp-deploy-rkh18ac3/modules/modules.tar
126 00:26:04.378306 total size: 8618924 (8 MB)
127 00:26:04.378370 Using unxz to decompress xz
128 00:26:04.382352 progress 0 % (0 MB)
129 00:26:04.401965 progress 5 % (0 MB)
130 00:26:04.426202 progress 10 % (0 MB)
131 00:26:04.451377 progress 15 % (1 MB)
132 00:26:04.475665 progress 20 % (1 MB)
133 00:26:04.500538 progress 25 % (2 MB)
134 00:26:04.524944 progress 30 % (2 MB)
135 00:26:04.549735 progress 35 % (2 MB)
136 00:26:04.573705 progress 40 % (3 MB)
137 00:26:04.597782 progress 45 % (3 MB)
138 00:26:04.621335 progress 50 % (4 MB)
139 00:26:04.645674 progress 55 % (4 MB)
140 00:26:04.669799 progress 60 % (4 MB)
141 00:26:04.693059 progress 65 % (5 MB)
142 00:26:04.720573 progress 70 % (5 MB)
143 00:26:04.745371 progress 75 % (6 MB)
144 00:26:04.768604 progress 80 % (6 MB)
145 00:26:04.791790 progress 85 % (7 MB)
146 00:26:04.814965 progress 90 % (7 MB)
147 00:26:04.842679 progress 95 % (7 MB)
148 00:26:04.872526 progress 100 % (8 MB)
149 00:26:04.877109 8 MB downloaded in 0.50 s (16.48 MB/s)
150 00:26:04.877361 end: 1.5.1 http-download (duration 00:00:00) [common]
152 00:26:04.877633 end: 1.5 download-retry (duration 00:00:00) [common]
153 00:26:04.877730 start: 1.6 prepare-tftp-overlay (timeout 00:09:53) [common]
154 00:26:04.877825 start: 1.6.1 extract-nfsrootfs (timeout 00:09:53) [common]
155 00:26:08.382943 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14479210/extract-nfsrootfs-u_uwlwfy
156 00:26:08.383147 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 00:26:08.383252 start: 1.6.2 lava-overlay (timeout 00:09:49) [common]
158 00:26:08.383427 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14479210/lava-overlay-f9x6dn26
159 00:26:08.383563 makedir: /var/lib/lava/dispatcher/tmp/14479210/lava-overlay-f9x6dn26/lava-14479210/bin
160 00:26:08.383667 makedir: /var/lib/lava/dispatcher/tmp/14479210/lava-overlay-f9x6dn26/lava-14479210/tests
161 00:26:08.383767 makedir: /var/lib/lava/dispatcher/tmp/14479210/lava-overlay-f9x6dn26/lava-14479210/results
162 00:26:08.383868 Creating /var/lib/lava/dispatcher/tmp/14479210/lava-overlay-f9x6dn26/lava-14479210/bin/lava-add-keys
163 00:26:08.384011 Creating /var/lib/lava/dispatcher/tmp/14479210/lava-overlay-f9x6dn26/lava-14479210/bin/lava-add-sources
164 00:26:08.384139 Creating /var/lib/lava/dispatcher/tmp/14479210/lava-overlay-f9x6dn26/lava-14479210/bin/lava-background-process-start
165 00:26:08.384266 Creating /var/lib/lava/dispatcher/tmp/14479210/lava-overlay-f9x6dn26/lava-14479210/bin/lava-background-process-stop
166 00:26:08.384390 Creating /var/lib/lava/dispatcher/tmp/14479210/lava-overlay-f9x6dn26/lava-14479210/bin/lava-common-functions
167 00:26:08.384516 Creating /var/lib/lava/dispatcher/tmp/14479210/lava-overlay-f9x6dn26/lava-14479210/bin/lava-echo-ipv4
168 00:26:08.384638 Creating /var/lib/lava/dispatcher/tmp/14479210/lava-overlay-f9x6dn26/lava-14479210/bin/lava-install-packages
169 00:26:08.384761 Creating /var/lib/lava/dispatcher/tmp/14479210/lava-overlay-f9x6dn26/lava-14479210/bin/lava-installed-packages
170 00:26:08.384885 Creating /var/lib/lava/dispatcher/tmp/14479210/lava-overlay-f9x6dn26/lava-14479210/bin/lava-os-build
171 00:26:08.385007 Creating /var/lib/lava/dispatcher/tmp/14479210/lava-overlay-f9x6dn26/lava-14479210/bin/lava-probe-channel
172 00:26:08.385130 Creating /var/lib/lava/dispatcher/tmp/14479210/lava-overlay-f9x6dn26/lava-14479210/bin/lava-probe-ip
173 00:26:08.385251 Creating /var/lib/lava/dispatcher/tmp/14479210/lava-overlay-f9x6dn26/lava-14479210/bin/lava-target-ip
174 00:26:08.385372 Creating /var/lib/lava/dispatcher/tmp/14479210/lava-overlay-f9x6dn26/lava-14479210/bin/lava-target-mac
175 00:26:08.385492 Creating /var/lib/lava/dispatcher/tmp/14479210/lava-overlay-f9x6dn26/lava-14479210/bin/lava-target-storage
176 00:26:08.385614 Creating /var/lib/lava/dispatcher/tmp/14479210/lava-overlay-f9x6dn26/lava-14479210/bin/lava-test-case
177 00:26:08.385737 Creating /var/lib/lava/dispatcher/tmp/14479210/lava-overlay-f9x6dn26/lava-14479210/bin/lava-test-event
178 00:26:08.385857 Creating /var/lib/lava/dispatcher/tmp/14479210/lava-overlay-f9x6dn26/lava-14479210/bin/lava-test-feedback
179 00:26:08.385977 Creating /var/lib/lava/dispatcher/tmp/14479210/lava-overlay-f9x6dn26/lava-14479210/bin/lava-test-raise
180 00:26:08.386098 Creating /var/lib/lava/dispatcher/tmp/14479210/lava-overlay-f9x6dn26/lava-14479210/bin/lava-test-reference
181 00:26:08.386266 Creating /var/lib/lava/dispatcher/tmp/14479210/lava-overlay-f9x6dn26/lava-14479210/bin/lava-test-runner
182 00:26:08.386389 Creating /var/lib/lava/dispatcher/tmp/14479210/lava-overlay-f9x6dn26/lava-14479210/bin/lava-test-set
183 00:26:08.386513 Creating /var/lib/lava/dispatcher/tmp/14479210/lava-overlay-f9x6dn26/lava-14479210/bin/lava-test-shell
184 00:26:08.386637 Updating /var/lib/lava/dispatcher/tmp/14479210/lava-overlay-f9x6dn26/lava-14479210/bin/lava-add-keys (debian)
185 00:26:08.386786 Updating /var/lib/lava/dispatcher/tmp/14479210/lava-overlay-f9x6dn26/lava-14479210/bin/lava-add-sources (debian)
186 00:26:08.386923 Updating /var/lib/lava/dispatcher/tmp/14479210/lava-overlay-f9x6dn26/lava-14479210/bin/lava-install-packages (debian)
187 00:26:08.387060 Updating /var/lib/lava/dispatcher/tmp/14479210/lava-overlay-f9x6dn26/lava-14479210/bin/lava-installed-packages (debian)
188 00:26:08.387195 Updating /var/lib/lava/dispatcher/tmp/14479210/lava-overlay-f9x6dn26/lava-14479210/bin/lava-os-build (debian)
189 00:26:08.387313 Creating /var/lib/lava/dispatcher/tmp/14479210/lava-overlay-f9x6dn26/lava-14479210/environment
190 00:26:08.387410 LAVA metadata
191 00:26:08.387478 - LAVA_JOB_ID=14479210
192 00:26:08.387540 - LAVA_DISPATCHER_IP=192.168.201.1
193 00:26:08.387638 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:49) [common]
194 00:26:08.387704 skipped lava-vland-overlay
195 00:26:08.387776 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 00:26:08.387854 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:49) [common]
197 00:26:08.387916 skipped lava-multinode-overlay
198 00:26:08.387986 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 00:26:08.388079 start: 1.6.2.3 test-definition (timeout 00:09:49) [common]
200 00:26:08.388152 Loading test definitions
201 00:26:08.388240 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:49) [common]
202 00:26:08.388310 Using /lava-14479210 at stage 0
203 00:26:08.388588 uuid=14479210_1.6.2.3.1 testdef=None
204 00:26:08.388675 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 00:26:08.388760 start: 1.6.2.3.2 test-overlay (timeout 00:09:49) [common]
206 00:26:08.389210 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 00:26:08.389433 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:49) [common]
209 00:26:08.389981 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 00:26:08.390425 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:49) [common]
212 00:26:08.390958 runner path: /var/lib/lava/dispatcher/tmp/14479210/lava-overlay-f9x6dn26/lava-14479210/0/tests/0_timesync-off test_uuid 14479210_1.6.2.3.1
213 00:26:08.391114 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 00:26:08.391338 start: 1.6.2.3.5 git-repo-action (timeout 00:09:49) [common]
216 00:26:08.391410 Using /lava-14479210 at stage 0
217 00:26:08.391506 Fetching tests from https://github.com/kernelci/test-definitions.git
218 00:26:08.391593 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14479210/lava-overlay-f9x6dn26/lava-14479210/0/tests/1_kselftest-rtc'
219 00:26:10.403540 Running '/usr/bin/git checkout kernelci.org
220 00:26:10.549242 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14479210/lava-overlay-f9x6dn26/lava-14479210/0/tests/1_kselftest-rtc/automated/linux/kselftest/kselftest.yaml
221 00:26:10.550096 uuid=14479210_1.6.2.3.5 testdef=None
222 00:26:10.550319 end: 1.6.2.3.5 git-repo-action (duration 00:00:02) [common]
224 00:26:10.550570 start: 1.6.2.3.6 test-overlay (timeout 00:09:47) [common]
225 00:26:10.551313 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 00:26:10.551571 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:47) [common]
228 00:26:10.552566 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 00:26:10.552808 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:47) [common]
231 00:26:10.553726 runner path: /var/lib/lava/dispatcher/tmp/14479210/lava-overlay-f9x6dn26/lava-14479210/0/tests/1_kselftest-rtc test_uuid 14479210_1.6.2.3.5
232 00:26:10.553817 BOARD='mt8192-asurada-spherion-r0'
233 00:26:10.553883 BRANCH='cip'
234 00:26:10.553945 SKIPFILE='/dev/null'
235 00:26:10.554004 SKIP_INSTALL='True'
236 00:26:10.554060 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.94-cip23/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 00:26:10.554119 TST_CASENAME=''
238 00:26:10.554202 TST_CMDFILES='rtc'
239 00:26:10.554357 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 00:26:10.554561 Creating lava-test-runner.conf files
242 00:26:10.554624 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14479210/lava-overlay-f9x6dn26/lava-14479210/0 for stage 0
243 00:26:10.554716 - 0_timesync-off
244 00:26:10.554785 - 1_kselftest-rtc
245 00:26:10.554879 end: 1.6.2.3 test-definition (duration 00:00:02) [common]
246 00:26:10.554966 start: 1.6.2.4 compress-overlay (timeout 00:09:47) [common]
247 00:26:18.129600 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 00:26:18.129751 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:39) [common]
249 00:26:18.129844 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 00:26:18.129946 end: 1.6.2 lava-overlay (duration 00:00:10) [common]
251 00:26:18.130036 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:39) [common]
252 00:26:18.296757 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 00:26:18.297195 start: 1.6.4 extract-modules (timeout 00:09:39) [common]
254 00:26:18.297374 extracting modules file /var/lib/lava/dispatcher/tmp/14479210/tftp-deploy-rkh18ac3/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14479210/extract-nfsrootfs-u_uwlwfy
255 00:26:18.527328 extracting modules file /var/lib/lava/dispatcher/tmp/14479210/tftp-deploy-rkh18ac3/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14479210/extract-overlay-ramdisk-cmclc2d_/ramdisk
256 00:26:18.764698 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 00:26:18.764868 start: 1.6.5 apply-overlay-tftp (timeout 00:09:39) [common]
258 00:26:18.764975 [common] Applying overlay to NFS
259 00:26:18.765049 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14479210/compress-overlay-k5ju8kdw/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14479210/extract-nfsrootfs-u_uwlwfy
260 00:26:19.678712 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 00:26:19.678882 start: 1.6.6 configure-preseed-file (timeout 00:09:38) [common]
262 00:26:19.678978 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 00:26:19.679068 start: 1.6.7 compress-ramdisk (timeout 00:09:38) [common]
264 00:26:19.679149 Building ramdisk /var/lib/lava/dispatcher/tmp/14479210/extract-overlay-ramdisk-cmclc2d_/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14479210/extract-overlay-ramdisk-cmclc2d_/ramdisk
265 00:26:19.985539 >> 130487 blocks
266 00:26:22.046266 rename /var/lib/lava/dispatcher/tmp/14479210/extract-overlay-ramdisk-cmclc2d_/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14479210/tftp-deploy-rkh18ac3/ramdisk/ramdisk.cpio.gz
267 00:26:22.046731 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 00:26:22.046906 start: 1.6.8 prepare-kernel (timeout 00:09:35) [common]
269 00:26:22.047057 start: 1.6.8.1 prepare-fit (timeout 00:09:35) [common]
270 00:26:22.047206 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14479210/tftp-deploy-rkh18ac3/kernel/Image']
271 00:26:35.251015 Returned 0 in 13 seconds
272 00:26:35.351988 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14479210/tftp-deploy-rkh18ac3/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14479210/tftp-deploy-rkh18ac3/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14479210/tftp-deploy-rkh18ac3/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14479210/tftp-deploy-rkh18ac3/kernel/image.itb
273 00:26:35.730014 output: FIT description: Kernel Image image with one or more FDT blobs
274 00:26:35.730438 output: Created: Fri Jun 21 01:26:35 2024
275 00:26:35.730541 output: Image 0 (kernel-1)
276 00:26:35.730634 output: Description:
277 00:26:35.730728 output: Created: Fri Jun 21 01:26:35 2024
278 00:26:35.730841 output: Type: Kernel Image
279 00:26:35.731062 output: Compression: lzma compressed
280 00:26:35.731173 output: Data Size: 13124896 Bytes = 12817.28 KiB = 12.52 MiB
281 00:26:35.731273 output: Architecture: AArch64
282 00:26:35.731355 output: OS: Linux
283 00:26:35.731448 output: Load Address: 0x00000000
284 00:26:35.731533 output: Entry Point: 0x00000000
285 00:26:35.731617 output: Hash algo: crc32
286 00:26:35.731701 output: Hash value: ab2f7826
287 00:26:35.731783 output: Image 1 (fdt-1)
288 00:26:35.731868 output: Description: mt8192-asurada-spherion-r0
289 00:26:35.731951 output: Created: Fri Jun 21 01:26:35 2024
290 00:26:35.732036 output: Type: Flat Device Tree
291 00:26:35.732118 output: Compression: uncompressed
292 00:26:35.732201 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
293 00:26:35.732283 output: Architecture: AArch64
294 00:26:35.732365 output: Hash algo: crc32
295 00:26:35.732447 output: Hash value: 0f8e4d2e
296 00:26:35.732540 output: Image 2 (ramdisk-1)
297 00:26:35.732631 output: Description: unavailable
298 00:26:35.732708 output: Created: Fri Jun 21 01:26:35 2024
299 00:26:35.732800 output: Type: RAMDisk Image
300 00:26:35.732892 output: Compression: Unknown Compression
301 00:26:35.732983 output: Data Size: 18748499 Bytes = 18309.08 KiB = 17.88 MiB
302 00:26:35.733075 output: Architecture: AArch64
303 00:26:35.733167 output: OS: Linux
304 00:26:35.733258 output: Load Address: unavailable
305 00:26:35.733349 output: Entry Point: unavailable
306 00:26:35.733441 output: Hash algo: crc32
307 00:26:35.733533 output: Hash value: 9d0fe13b
308 00:26:35.733623 output: Default Configuration: 'conf-1'
309 00:26:35.733714 output: Configuration 0 (conf-1)
310 00:26:35.733806 output: Description: mt8192-asurada-spherion-r0
311 00:26:35.733897 output: Kernel: kernel-1
312 00:26:35.733988 output: Init Ramdisk: ramdisk-1
313 00:26:35.734079 output: FDT: fdt-1
314 00:26:35.734179 output: Loadables: kernel-1
315 00:26:35.734310 output:
316 00:26:35.734568 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
317 00:26:35.734712 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
318 00:26:35.734858 end: 1.6 prepare-tftp-overlay (duration 00:00:31) [common]
319 00:26:35.734973 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:22) [common]
320 00:26:35.735091 No LXC device requested
321 00:26:35.735190 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 00:26:35.735301 start: 1.8 deploy-device-env (timeout 00:09:22) [common]
323 00:26:35.735394 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 00:26:35.735502 Checking files for TFTP limit of 4294967296 bytes.
325 00:26:35.736172 end: 1 tftp-deploy (duration 00:00:38) [common]
326 00:26:35.736317 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 00:26:35.736448 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 00:26:35.736629 substitutions:
329 00:26:35.736730 - {DTB}: 14479210/tftp-deploy-rkh18ac3/dtb/mt8192-asurada-spherion-r0.dtb
330 00:26:35.736833 - {INITRD}: 14479210/tftp-deploy-rkh18ac3/ramdisk/ramdisk.cpio.gz
331 00:26:35.736932 - {KERNEL}: 14479210/tftp-deploy-rkh18ac3/kernel/Image
332 00:26:35.737029 - {LAVA_MAC}: None
333 00:26:35.737127 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14479210/extract-nfsrootfs-u_uwlwfy
334 00:26:35.737223 - {NFS_SERVER_IP}: 192.168.201.1
335 00:26:35.737319 - {PRESEED_CONFIG}: None
336 00:26:35.737417 - {PRESEED_LOCAL}: None
337 00:26:35.737512 - {RAMDISK}: 14479210/tftp-deploy-rkh18ac3/ramdisk/ramdisk.cpio.gz
338 00:26:35.737610 - {ROOT_PART}: None
339 00:26:35.737706 - {ROOT}: None
340 00:26:35.737801 - {SERVER_IP}: 192.168.201.1
341 00:26:35.737895 - {TEE}: None
342 00:26:35.737990 Parsed boot commands:
343 00:26:35.738085 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 00:26:35.738331 Parsed boot commands: tftpboot 192.168.201.1 14479210/tftp-deploy-rkh18ac3/kernel/image.itb 14479210/tftp-deploy-rkh18ac3/kernel/cmdline
345 00:26:35.738456 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 00:26:35.738586 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 00:26:35.738720 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 00:26:35.738848 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 00:26:35.738955 Not connected, no need to disconnect.
350 00:26:35.739073 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 00:26:35.739199 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 00:26:35.739302 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-9'
353 00:26:35.742999 Setting prompt string to ['lava-test: # ']
354 00:26:35.743399 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 00:26:35.743518 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 00:26:35.743634 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 00:26:35.743740 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 00:26:35.743935 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-9']
359 00:26:49.698382 Returned 0 in 13 seconds
360 00:26:49.799687 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
362 00:26:49.801477 end: 2.2.2 reset-device (duration 00:00:14) [common]
363 00:26:49.802224 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
364 00:26:49.802789 Setting prompt string to 'Starting depthcharge on Spherion...'
365 00:26:49.803258 Changing prompt to 'Starting depthcharge on Spherion...'
366 00:26:49.803744 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
367 00:26:49.806085 [Enter `^Ec?' for help]
368 00:26:49.806651
369 00:26:49.807173 F0: 102B 0000
370 00:26:49.807768
371 00:26:49.808280 F3: 1001 0000 [0200]
372 00:26:49.808762
373 00:26:49.809281 F3: 1001 0000
374 00:26:49.809748
375 00:26:49.810361 F7: 102D 0000
376 00:26:49.810819
377 00:26:49.811335 F1: 0000 0000
378 00:26:49.811775
379 00:26:49.812206 V0: 0000 0000 [0001]
380 00:26:49.812635
381 00:26:49.813059 00: 0007 8000
382 00:26:49.813518
383 00:26:49.813946 01: 0000 0000
384 00:26:49.814550
385 00:26:49.814995 BP: 0C00 0209 [0000]
386 00:26:49.815472
387 00:26:49.815902 G0: 1182 0000
388 00:26:49.816327
389 00:26:49.816748 EC: 0000 0021 [4000]
390 00:26:49.817173
391 00:26:49.817655 S7: 0000 0000 [0000]
392 00:26:49.818232
393 00:26:49.818781 CC: 0000 0000 [0001]
394 00:26:49.819324
395 00:26:49.819797 T0: 0000 0040 [010F]
396 00:26:49.820221
397 00:26:49.820644 Jump to BL
398 00:26:49.821102
399 00:26:49.821563
400 00:26:49.821982
401 00:26:49.822552 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
402 00:26:49.823112 ARM64: Exception handlers installed.
403 00:26:49.823581 ARM64: Testing exception
404 00:26:49.824010 ARM64: Done test exception
405 00:26:49.824470 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
406 00:26:49.824901 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
407 00:26:49.825333 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
408 00:26:49.825806 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
409 00:26:49.826293 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
410 00:26:49.826801 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
411 00:26:49.827213 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
412 00:26:49.827608 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
413 00:26:49.828017 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
414 00:26:49.828430 WDT: Last reset was cold boot
415 00:26:49.828820 SPI1(PAD0) initialized at 2873684 Hz
416 00:26:49.829211 SPI5(PAD0) initialized at 992727 Hz
417 00:26:49.829628 VBOOT: Loading verstage.
418 00:26:49.830020 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
419 00:26:49.830542 FMAP: Found "FLASH" version 1.1 at 0x20000.
420 00:26:49.831160 FMAP: base = 0x0 size = 0x800000 #areas = 25
421 00:26:49.831537 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
422 00:26:49.831797 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
423 00:26:49.832018 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
424 00:26:49.832228 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
425 00:26:49.832433
426 00:26:49.832634
427 00:26:49.832836 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
428 00:26:49.833040 ARM64: Exception handlers installed.
429 00:26:49.833242 ARM64: Testing exception
430 00:26:49.833458 ARM64: Done test exception
431 00:26:49.833658 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
432 00:26:49.833857 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
433 00:26:49.834057 Probing TPM: . done!
434 00:26:49.834330 TPM ready after 0 ms
435 00:26:49.834536 Connected to device vid:did:rid of 1ae0:0028:00
436 00:26:49.834736 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
437 00:26:49.834940 Initialized TPM device CR50 revision 0
438 00:26:49.835138 tlcl_send_startup: Startup return code is 0
439 00:26:49.835338 TPM: setup succeeded
440 00:26:49.835601 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
441 00:26:49.835931 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
442 00:26:49.836145 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
443 00:26:49.836327 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
444 00:26:49.836479 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
445 00:26:49.836631 in-header: 03 07 00 00 08 00 00 00
446 00:26:49.836780 in-data: aa e4 47 04 13 02 00 00
447 00:26:49.836929 Chrome EC: UHEPI supported
448 00:26:49.837078 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
449 00:26:49.837234 in-header: 03 a9 00 00 08 00 00 00
450 00:26:49.837385 in-data: 84 60 60 08 00 00 00 00
451 00:26:49.837603 Phase 1
452 00:26:49.837816 FMAP: area GBB found @ 3f5000 (12032 bytes)
453 00:26:49.838026 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
454 00:26:49.838280 VB2:vb2_check_recovery() Recovery was requested manually
455 00:26:49.838490 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
456 00:26:49.838696 Recovery requested (1009000e)
457 00:26:49.838902 TPM: Extending digest for VBOOT: boot mode into PCR 0
458 00:26:49.839160 tlcl_extend: response is 0
459 00:26:49.839445 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
460 00:26:49.839643 tlcl_extend: response is 0
461 00:26:49.839849 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
462 00:26:49.840109 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
463 00:26:49.840369 BS: bootblock times (exec / console): total (unknown) / 148 ms
464 00:26:49.840574
465 00:26:49.840800
466 00:26:49.841005 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
467 00:26:49.841222 ARM64: Exception handlers installed.
468 00:26:49.841441 ARM64: Testing exception
469 00:26:49.841607 ARM64: Done test exception
470 00:26:49.841773 pmic_efuse_setting: Set efuses in 11 msecs
471 00:26:49.841981 pmwrap_interface_init: Select PMIF_VLD_RDY
472 00:26:49.842202 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
473 00:26:49.842614 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
474 00:26:49.842771 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
475 00:26:49.842946 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
476 00:26:49.843114 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
477 00:26:49.843280 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
478 00:26:49.843457 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
479 00:26:49.843667 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
480 00:26:49.843897 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
481 00:26:49.844056 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
482 00:26:49.844222 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
483 00:26:49.844431 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
484 00:26:49.844596 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
485 00:26:49.844827 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
486 00:26:49.844972 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
487 00:26:49.845115 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
488 00:26:49.845261 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
489 00:26:49.845394 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
490 00:26:49.845577 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
491 00:26:49.845745 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
492 00:26:49.845911 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
493 00:26:49.846120 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
494 00:26:49.846346 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
495 00:26:49.846523 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
496 00:26:49.846699 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
497 00:26:49.846876 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
498 00:26:49.847078 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
499 00:26:49.847254 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
500 00:26:49.847443 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
501 00:26:49.847595 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
502 00:26:49.847735 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
503 00:26:49.847874 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
504 00:26:49.848013 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
505 00:26:49.848151 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
506 00:26:49.848323 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
507 00:26:49.848497 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
508 00:26:49.848636 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
509 00:26:49.848810 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
510 00:26:49.848947 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
511 00:26:49.849085 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
512 00:26:49.849221 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
513 00:26:49.849359 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
514 00:26:49.849522 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
515 00:26:49.849698 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
516 00:26:49.849872 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
517 00:26:49.850010 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
518 00:26:49.850197 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
519 00:26:49.850361 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
520 00:26:49.850501 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
521 00:26:49.850639 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
522 00:26:49.850777 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
523 00:26:49.850952 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
524 00:26:49.851128 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
525 00:26:49.851268 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
526 00:26:49.851419 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
527 00:26:49.851571 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
528 00:26:49.851690 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
529 00:26:49.851809 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
530 00:26:49.851928 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
531 00:26:49.852077 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x2b
532 00:26:49.852227 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
533 00:26:49.852377 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
534 00:26:49.852526 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
535 00:26:49.852676 [RTC]rtc_get_frequency_meter,154: input=15, output=835
536 00:26:49.852825 [RTC]rtc_get_frequency_meter,154: input=7, output=708
537 00:26:49.852975 [RTC]rtc_get_frequency_meter,154: input=11, output=772
538 00:26:49.853123 [RTC]rtc_get_frequency_meter,154: input=13, output=804
539 00:26:49.853273 [RTC]rtc_get_frequency_meter,154: input=12, output=788
540 00:26:49.853422 [RTC]rtc_get_frequency_meter,154: input=12, output=788
541 00:26:49.853569 [RTC]rtc_get_frequency_meter,154: input=13, output=805
542 00:26:49.853717 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
543 00:26:49.854083 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
544 00:26:49.854250 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
545 00:26:49.854407 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
546 00:26:49.854559 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
547 00:26:49.854718 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
548 00:26:49.854871 ADC[4]: Raw value=903400 ID=7
549 00:26:49.855023 ADC[3]: Raw value=213652 ID=1
550 00:26:49.855174 RAM Code: 0x71
551 00:26:49.855325 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
552 00:26:49.855477 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
553 00:26:49.855632 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
554 00:26:49.855785 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
555 00:26:49.855936 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
556 00:26:49.856088 in-header: 03 07 00 00 08 00 00 00
557 00:26:49.856246 in-data: aa e4 47 04 13 02 00 00
558 00:26:49.856377 Chrome EC: UHEPI supported
559 00:26:49.856508 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
560 00:26:49.856639 in-header: 03 a9 00 00 08 00 00 00
561 00:26:49.856769 in-data: 84 60 60 08 00 00 00 00
562 00:26:49.856899 MRC: failed to locate region type 0.
563 00:26:49.857030 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
564 00:26:49.857177 DRAM-K: Running full calibration
565 00:26:49.857310 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
566 00:26:49.857443 header.status = 0x0
567 00:26:49.857574 header.version = 0x6 (expected: 0x6)
568 00:26:49.857705 header.size = 0xd00 (expected: 0xd00)
569 00:26:49.857835 header.flags = 0x0
570 00:26:49.857965 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
571 00:26:49.858097 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
572 00:26:49.858243 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
573 00:26:49.858377 dram_init: ddr_geometry: 2
574 00:26:49.858509 [EMI] MDL number = 2
575 00:26:49.858640 [EMI] Get MDL freq = 0
576 00:26:49.858771 dram_init: ddr_type: 0
577 00:26:49.858902 is_discrete_lpddr4: 1
578 00:26:49.859032 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
579 00:26:49.859163
580 00:26:49.859293
581 00:26:49.859423 [Bian_co] ETT version 0.0.0.1
582 00:26:49.859554 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
583 00:26:49.859685
584 00:26:49.859815 dramc_set_vcore_voltage set vcore to 650000
585 00:26:49.859947 Read voltage for 800, 4
586 00:26:49.860090 Vio18 = 0
587 00:26:49.860230 Vcore = 650000
588 00:26:49.860354 Vdram = 0
589 00:26:49.860486 Vddq = 0
590 00:26:49.860607 Vmddr = 0
591 00:26:49.860725 dram_init: config_dvfs: 1
592 00:26:49.860856 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
593 00:26:49.860995 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
594 00:26:49.861127 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
595 00:26:49.861265 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
596 00:26:49.861382 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
597 00:26:49.861499 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
598 00:26:49.861616 MEM_TYPE=3, freq_sel=18
599 00:26:49.861732 sv_algorithm_assistance_LP4_1600
600 00:26:49.861847 ============ PULL DRAM RESETB DOWN ============
601 00:26:49.861968 ========== PULL DRAM RESETB DOWN end =========
602 00:26:49.862085 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
603 00:26:49.862210 ===================================
604 00:26:49.862329 LPDDR4 DRAM CONFIGURATION
605 00:26:49.862446 ===================================
606 00:26:49.862563 EX_ROW_EN[0] = 0x0
607 00:26:49.862679 EX_ROW_EN[1] = 0x0
608 00:26:49.862794 LP4Y_EN = 0x0
609 00:26:49.862910 WORK_FSP = 0x0
610 00:26:49.863027 WL = 0x2
611 00:26:49.863142 RL = 0x2
612 00:26:49.863258 BL = 0x2
613 00:26:49.863374 RPST = 0x0
614 00:26:49.863489 RD_PRE = 0x0
615 00:26:49.863604 WR_PRE = 0x1
616 00:26:49.863731 WR_PST = 0x0
617 00:26:49.863847 DBI_WR = 0x0
618 00:26:49.863963 DBI_RD = 0x0
619 00:26:49.864082 OTF = 0x1
620 00:26:49.864200 ===================================
621 00:26:49.864319 ===================================
622 00:26:49.864435 ANA top config
623 00:26:49.864552 ===================================
624 00:26:49.864668 DLL_ASYNC_EN = 0
625 00:26:49.864784 ALL_SLAVE_EN = 1
626 00:26:49.864900 NEW_RANK_MODE = 1
627 00:26:49.865018 DLL_IDLE_MODE = 1
628 00:26:49.865133 LP45_APHY_COMB_EN = 1
629 00:26:49.865249 TX_ODT_DIS = 1
630 00:26:49.865365 NEW_8X_MODE = 1
631 00:26:49.865481 ===================================
632 00:26:49.865597 ===================================
633 00:26:49.865713 data_rate = 1600
634 00:26:49.865828 CKR = 1
635 00:26:49.865943 DQ_P2S_RATIO = 8
636 00:26:49.866058 ===================================
637 00:26:49.866184 CA_P2S_RATIO = 8
638 00:26:49.866309 DQ_CA_OPEN = 0
639 00:26:49.866414 DQ_SEMI_OPEN = 0
640 00:26:49.866519 CA_SEMI_OPEN = 0
641 00:26:49.866624 CA_FULL_RATE = 0
642 00:26:49.866729 DQ_CKDIV4_EN = 1
643 00:26:49.866843 CA_CKDIV4_EN = 1
644 00:26:49.866948 CA_PREDIV_EN = 0
645 00:26:49.867052 PH8_DLY = 0
646 00:26:49.867155 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
647 00:26:49.867259 DQ_AAMCK_DIV = 4
648 00:26:49.867362 CA_AAMCK_DIV = 4
649 00:26:49.867466 CA_ADMCK_DIV = 4
650 00:26:49.867569 DQ_TRACK_CA_EN = 0
651 00:26:49.867672 CA_PICK = 800
652 00:26:49.867776 CA_MCKIO = 800
653 00:26:49.867880 MCKIO_SEMI = 0
654 00:26:49.867983 PLL_FREQ = 3068
655 00:26:49.868087 DQ_UI_PI_RATIO = 32
656 00:26:49.868190 CA_UI_PI_RATIO = 0
657 00:26:49.868294 ===================================
658 00:26:49.868399 ===================================
659 00:26:49.868503 memory_type:LPDDR4
660 00:26:49.868607 GP_NUM : 10
661 00:26:49.868711 SRAM_EN : 1
662 00:26:49.868814 MD32_EN : 0
663 00:26:49.869138 ===================================
664 00:26:49.869245 [ANA_INIT] >>>>>>>>>>>>>>
665 00:26:49.869364 <<<<<< [CONFIGURE PHASE]: ANA_TX
666 00:26:49.869474 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
667 00:26:49.869582 ===================================
668 00:26:49.869688 data_rate = 1600,PCW = 0X7600
669 00:26:49.869793 ===================================
670 00:26:49.869899 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
671 00:26:49.870004 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
672 00:26:49.870109 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
673 00:26:49.870227 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
674 00:26:49.870346 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
675 00:26:49.870452 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
676 00:26:49.870558 [ANA_INIT] flow start
677 00:26:49.870664 [ANA_INIT] PLL >>>>>>>>
678 00:26:49.870769 [ANA_INIT] PLL <<<<<<<<
679 00:26:49.870873 [ANA_INIT] MIDPI >>>>>>>>
680 00:26:49.870978 [ANA_INIT] MIDPI <<<<<<<<
681 00:26:49.871082 [ANA_INIT] DLL >>>>>>>>
682 00:26:49.871187 [ANA_INIT] flow end
683 00:26:49.871302 ============ LP4 DIFF to SE enter ============
684 00:26:49.871414 ============ LP4 DIFF to SE exit ============
685 00:26:49.871510 [ANA_INIT] <<<<<<<<<<<<<
686 00:26:49.871605 [Flow] Enable top DCM control >>>>>
687 00:26:49.871700 [Flow] Enable top DCM control <<<<<
688 00:26:49.871795 Enable DLL master slave shuffle
689 00:26:49.871890 ==============================================================
690 00:26:49.871985 Gating Mode config
691 00:26:49.872080 ==============================================================
692 00:26:49.872175 Config description:
693 00:26:49.872271 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
694 00:26:49.872368 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
695 00:26:49.872464 SELPH_MODE 0: By rank 1: By Phase
696 00:26:49.872585 ==============================================================
697 00:26:49.872687 GAT_TRACK_EN = 1
698 00:26:49.872785 RX_GATING_MODE = 2
699 00:26:49.872882 RX_GATING_TRACK_MODE = 2
700 00:26:49.872979 SELPH_MODE = 1
701 00:26:49.873075 PICG_EARLY_EN = 1
702 00:26:49.873171 VALID_LAT_VALUE = 1
703 00:26:49.873249 ==============================================================
704 00:26:49.873356 Enter into Gating configuration >>>>
705 00:26:49.873453 Exit from Gating configuration <<<<
706 00:26:49.873549 Enter into DVFS_PRE_config >>>>>
707 00:26:49.873655 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
708 00:26:49.873757 Exit from DVFS_PRE_config <<<<<
709 00:26:49.873853 Enter into PICG configuration >>>>
710 00:26:49.873949 Exit from PICG configuration <<<<
711 00:26:49.874045 [RX_INPUT] configuration >>>>>
712 00:26:49.874141 [RX_INPUT] configuration <<<<<
713 00:26:49.874243 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
714 00:26:49.874340 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
715 00:26:49.874436 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
716 00:26:49.874532 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
717 00:26:49.874629 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
718 00:26:49.874724 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
719 00:26:49.874820 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
720 00:26:49.874916 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
721 00:26:49.875011 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
722 00:26:49.875107 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
723 00:26:49.875202 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
724 00:26:49.875302 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
725 00:26:49.875413 ===================================
726 00:26:49.875509 LPDDR4 DRAM CONFIGURATION
727 00:26:49.875610 ===================================
728 00:26:49.875706 EX_ROW_EN[0] = 0x0
729 00:26:49.875802 EX_ROW_EN[1] = 0x0
730 00:26:49.875897 LP4Y_EN = 0x0
731 00:26:49.875992 WORK_FSP = 0x0
732 00:26:49.876087 WL = 0x2
733 00:26:49.876182 RL = 0x2
734 00:26:49.876292 BL = 0x2
735 00:26:49.876384 RPST = 0x0
736 00:26:49.876477 RD_PRE = 0x0
737 00:26:49.876569 WR_PRE = 0x1
738 00:26:49.876672 WR_PST = 0x0
739 00:26:49.876764 DBI_WR = 0x0
740 00:26:49.876857 DBI_RD = 0x0
741 00:26:49.876950 OTF = 0x1
742 00:26:49.877042 ===================================
743 00:26:49.877136 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
744 00:26:49.877228 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
745 00:26:49.877322 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
746 00:26:49.877415 ===================================
747 00:26:49.877508 LPDDR4 DRAM CONFIGURATION
748 00:26:49.877600 ===================================
749 00:26:49.877693 EX_ROW_EN[0] = 0x10
750 00:26:49.877785 EX_ROW_EN[1] = 0x0
751 00:26:49.877877 LP4Y_EN = 0x0
752 00:26:49.877969 WORK_FSP = 0x0
753 00:26:49.878061 WL = 0x2
754 00:26:49.878153 RL = 0x2
755 00:26:49.878291 BL = 0x2
756 00:26:49.878384 RPST = 0x0
757 00:26:49.878477 RD_PRE = 0x0
758 00:26:49.878570 WR_PRE = 0x1
759 00:26:49.878662 WR_PST = 0x0
760 00:26:49.878754 DBI_WR = 0x0
761 00:26:49.878847 DBI_RD = 0x0
762 00:26:49.878939 OTF = 0x1
763 00:26:49.879032 ===================================
764 00:26:49.879126 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
765 00:26:49.879219 nWR fixed to 40
766 00:26:49.879312 [ModeRegInit_LP4] CH0 RK0
767 00:26:49.879405 [ModeRegInit_LP4] CH0 RK1
768 00:26:49.879497 [ModeRegInit_LP4] CH1 RK0
769 00:26:49.879590 [ModeRegInit_LP4] CH1 RK1
770 00:26:49.879682 match AC timing 13
771 00:26:49.879975 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
772 00:26:49.880072 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
773 00:26:49.880169 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
774 00:26:49.880266 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
775 00:26:49.880362 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
776 00:26:49.880456 [EMI DOE] emi_dcm 0
777 00:26:49.880551 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
778 00:26:49.880644 ==
779 00:26:49.880739 Dram Type= 6, Freq= 0, CH_0, rank 0
780 00:26:49.880833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 00:26:49.880927 ==
782 00:26:49.881021 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
783 00:26:49.881115 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
784 00:26:49.881209 [CA 0] Center 37 (7~68) winsize 62
785 00:26:49.881302 [CA 1] Center 37 (7~68) winsize 62
786 00:26:49.881397 [CA 2] Center 34 (4~65) winsize 62
787 00:26:49.881491 [CA 3] Center 34 (4~65) winsize 62
788 00:26:49.881585 [CA 4] Center 33 (3~64) winsize 62
789 00:26:49.881678 [CA 5] Center 33 (3~64) winsize 62
790 00:26:49.881771
791 00:26:49.881864 [CmdBusTrainingLP45] Vref(ca) range 1: 32
792 00:26:49.881957
793 00:26:49.882051 [CATrainingPosCal] consider 1 rank data
794 00:26:49.882145 u2DelayCellTimex100 = 270/100 ps
795 00:26:49.882290 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
796 00:26:49.882384 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
797 00:26:49.882480 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
798 00:26:49.882575 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
799 00:26:49.882669 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
800 00:26:49.882762 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
801 00:26:49.882855
802 00:26:49.882947 CA PerBit enable=1, Macro0, CA PI delay=33
803 00:26:49.883040
804 00:26:49.883133 [CBTSetCACLKResult] CA Dly = 33
805 00:26:49.883228 CS Dly: 6 (0~37)
806 00:26:49.883324 ==
807 00:26:49.883417 Dram Type= 6, Freq= 0, CH_0, rank 1
808 00:26:49.883511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
809 00:26:49.883616 ==
810 00:26:49.883710 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
811 00:26:49.883806 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
812 00:26:49.883900 [CA 0] Center 37 (6~68) winsize 63
813 00:26:49.883993 [CA 1] Center 37 (7~68) winsize 62
814 00:26:49.884087 [CA 2] Center 34 (4~65) winsize 62
815 00:26:49.884181 [CA 3] Center 34 (4~65) winsize 62
816 00:26:49.884275 [CA 4] Center 33 (3~64) winsize 62
817 00:26:49.884368 [CA 5] Center 33 (2~64) winsize 63
818 00:26:49.884460
819 00:26:49.884553 [CmdBusTrainingLP45] Vref(ca) range 1: 34
820 00:26:49.884646
821 00:26:49.884738 [CATrainingPosCal] consider 2 rank data
822 00:26:49.884832 u2DelayCellTimex100 = 270/100 ps
823 00:26:49.884927 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
824 00:26:49.885019 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
825 00:26:49.885112 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
826 00:26:49.885208 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
827 00:26:49.885302 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
828 00:26:49.885394 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
829 00:26:49.885487
830 00:26:49.885579 CA PerBit enable=1, Macro0, CA PI delay=33
831 00:26:49.885672
832 00:26:49.885764 [CBTSetCACLKResult] CA Dly = 33
833 00:26:49.885857 CS Dly: 6 (0~38)
834 00:26:49.885949
835 00:26:49.886042 ----->DramcWriteLeveling(PI) begin...
836 00:26:49.886140 ==
837 00:26:49.886272 Dram Type= 6, Freq= 0, CH_0, rank 0
838 00:26:49.886366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
839 00:26:49.886440 ==
840 00:26:49.886534 Write leveling (Byte 0): 31 => 31
841 00:26:49.886638 Write leveling (Byte 1): 29 => 29
842 00:26:49.886731 DramcWriteLeveling(PI) end<-----
843 00:26:49.886825
844 00:26:49.886918 ==
845 00:26:49.887011 Dram Type= 6, Freq= 0, CH_0, rank 0
846 00:26:49.887105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
847 00:26:49.887200 ==
848 00:26:49.887294 [Gating] SW mode calibration
849 00:26:49.887387 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
850 00:26:49.887482 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
851 00:26:49.887577 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
852 00:26:49.887671 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
853 00:26:49.887765 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
854 00:26:49.887858 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 00:26:49.887952 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 00:26:49.888045 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 00:26:49.888137 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 00:26:49.888230 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 00:26:49.888325 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 00:26:49.888418 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 00:26:49.888510 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 00:26:49.888603 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 00:26:49.888697 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 00:26:49.888791 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 00:26:49.888884 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 00:26:49.888976 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 00:26:49.889069 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 00:26:49.889164 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
869 00:26:49.889257 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
870 00:26:49.889350 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
871 00:26:49.889442 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 00:26:49.889535 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 00:26:49.889627 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 00:26:49.889719 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 00:26:49.889812 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 00:26:49.889904 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 00:26:49.889996 0 9 8 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
878 00:26:49.890088 0 9 12 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
879 00:26:49.890429 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
880 00:26:49.890525 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
881 00:26:49.890623 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 00:26:49.890726 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 00:26:49.890835 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 00:26:49.890931 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
885 00:26:49.891026 0 10 8 | B1->B0 | 3434 2626 | 0 0 | (0 1) (1 0)
886 00:26:49.891120 0 10 12 | B1->B0 | 2727 2323 | 1 0 | (1 0) (1 0)
887 00:26:49.891214 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
888 00:26:49.891307 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 00:26:49.891401 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 00:26:49.891497 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 00:26:49.891591 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 00:26:49.891685 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 00:26:49.891778 0 11 8 | B1->B0 | 2727 3b3b | 1 0 | (1 1) (0 0)
894 00:26:49.891874 0 11 12 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
895 00:26:49.891968 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
896 00:26:49.892062 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
897 00:26:49.892155 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 00:26:49.892247 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 00:26:49.892340 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 00:26:49.892433 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 00:26:49.892526 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
902 00:26:49.892619 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 00:26:49.892712 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
904 00:26:49.892805 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 00:26:49.892897 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 00:26:49.892990 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 00:26:49.893082 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 00:26:49.893174 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 00:26:49.893267 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 00:26:49.893360 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 00:26:49.893461 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 00:26:49.893570 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 00:26:49.893665 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 00:26:49.893759 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 00:26:49.893854 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 00:26:49.893947 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 00:26:49.894041 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
918 00:26:49.894133 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
919 00:26:49.894271 Total UI for P1: 0, mck2ui 16
920 00:26:49.894366 best dqsien dly found for B0: ( 0, 14, 8)
921 00:26:49.894462 Total UI for P1: 0, mck2ui 16
922 00:26:49.894556 best dqsien dly found for B1: ( 0, 14, 8)
923 00:26:49.894649 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
924 00:26:49.894743 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
925 00:26:49.894837
926 00:26:49.894930 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
927 00:26:49.895023 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
928 00:26:49.895116 [Gating] SW calibration Done
929 00:26:49.895209 ==
930 00:26:49.895302 Dram Type= 6, Freq= 0, CH_0, rank 0
931 00:26:49.895395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
932 00:26:49.895489 ==
933 00:26:49.895583 RX Vref Scan: 0
934 00:26:49.895675
935 00:26:49.895768 RX Vref 0 -> 0, step: 1
936 00:26:49.895861
937 00:26:49.895953 RX Delay -130 -> 252, step: 16
938 00:26:49.896047 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
939 00:26:49.896140 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
940 00:26:49.896232 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
941 00:26:49.896325 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
942 00:26:49.896428 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
943 00:26:49.896521 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
944 00:26:49.896612 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
945 00:26:49.896704 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
946 00:26:49.896796 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
947 00:26:49.896888 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
948 00:26:49.896987 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
949 00:26:49.897083 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
950 00:26:49.897178 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
951 00:26:49.897271 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
952 00:26:49.897363 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
953 00:26:49.897456 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
954 00:26:49.897548 ==
955 00:26:49.897643 Dram Type= 6, Freq= 0, CH_0, rank 0
956 00:26:49.897736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
957 00:26:49.897830 ==
958 00:26:49.897922 DQS Delay:
959 00:26:49.898015 DQS0 = 0, DQS1 = 0
960 00:26:49.898107 DQM Delay:
961 00:26:49.898262 DQM0 = 84, DQM1 = 71
962 00:26:49.898358 DQ Delay:
963 00:26:49.898452 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
964 00:26:49.898545 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =93
965 00:26:49.898638 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
966 00:26:49.898730 DQ12 =77, DQ13 =77, DQ14 =85, DQ15 =77
967 00:26:49.898824
968 00:26:49.898917
969 00:26:49.899009 ==
970 00:26:49.899102 Dram Type= 6, Freq= 0, CH_0, rank 0
971 00:26:49.899197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
972 00:26:49.899292 ==
973 00:26:49.899385
974 00:26:49.899477
975 00:26:49.899570 TX Vref Scan disable
976 00:26:49.899662 == TX Byte 0 ==
977 00:26:49.899756 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
978 00:26:49.899860 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
979 00:26:49.899956 == TX Byte 1 ==
980 00:26:49.900050 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
981 00:26:49.900143 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
982 00:26:49.900236 ==
983 00:26:49.900329 Dram Type= 6, Freq= 0, CH_0, rank 0
984 00:26:49.900422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
985 00:26:49.900517 ==
986 00:26:49.900610 TX Vref=22, minBit 5, minWin=27, winSum=443
987 00:26:49.900899 TX Vref=24, minBit 5, minWin=27, winSum=445
988 00:26:49.900994 TX Vref=26, minBit 5, minWin=27, winSum=444
989 00:26:49.901090 TX Vref=28, minBit 10, minWin=27, winSum=446
990 00:26:49.901185 TX Vref=30, minBit 10, minWin=27, winSum=447
991 00:26:49.901280 TX Vref=32, minBit 9, minWin=26, winSum=440
992 00:26:49.901374 [TxChooseVref] Worse bit 10, Min win 27, Win sum 447, Final Vref 30
993 00:26:49.901468
994 00:26:49.901561 Final TX Range 1 Vref 30
995 00:26:49.901655
996 00:26:49.901748 ==
997 00:26:49.901841 Dram Type= 6, Freq= 0, CH_0, rank 0
998 00:26:49.901934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
999 00:26:49.902028 ==
1000 00:26:49.902120
1001 00:26:49.902221
1002 00:26:49.902314 TX Vref Scan disable
1003 00:26:49.902407 == TX Byte 0 ==
1004 00:26:49.902499 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1005 00:26:49.902593 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1006 00:26:49.902686 == TX Byte 1 ==
1007 00:26:49.902778 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1008 00:26:49.902873 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1009 00:26:49.902965
1010 00:26:49.903057 [DATLAT]
1011 00:26:49.903161 Freq=800, CH0 RK0
1012 00:26:49.903257
1013 00:26:49.903349 DATLAT Default: 0xa
1014 00:26:49.903442 0, 0xFFFF, sum = 0
1015 00:26:49.903537 1, 0xFFFF, sum = 0
1016 00:26:49.903632 2, 0xFFFF, sum = 0
1017 00:26:49.903727 3, 0xFFFF, sum = 0
1018 00:26:49.903821 4, 0xFFFF, sum = 0
1019 00:26:49.903915 5, 0xFFFF, sum = 0
1020 00:26:49.904012 6, 0xFFFF, sum = 0
1021 00:26:49.904117 7, 0xFFFF, sum = 0
1022 00:26:49.904211 8, 0xFFFF, sum = 0
1023 00:26:49.904305 9, 0x0, sum = 1
1024 00:26:49.904401 10, 0x0, sum = 2
1025 00:26:49.904505 11, 0x0, sum = 3
1026 00:26:49.904602 12, 0x0, sum = 4
1027 00:26:49.904698 best_step = 10
1028 00:26:49.904792
1029 00:26:49.904885 ==
1030 00:26:49.904978 Dram Type= 6, Freq= 0, CH_0, rank 0
1031 00:26:49.905071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1032 00:26:49.905166 ==
1033 00:26:49.905259 RX Vref Scan: 1
1034 00:26:49.905352
1035 00:26:49.905444 Set Vref Range= 32 -> 127
1036 00:26:49.905536
1037 00:26:49.905628 RX Vref 32 -> 127, step: 1
1038 00:26:49.905720
1039 00:26:49.905812 RX Delay -111 -> 252, step: 8
1040 00:26:49.905903
1041 00:26:49.905996 Set Vref, RX VrefLevel [Byte0]: 32
1042 00:26:49.906102 [Byte1]: 32
1043 00:26:49.906209
1044 00:26:49.906303 Set Vref, RX VrefLevel [Byte0]: 33
1045 00:26:49.906398 [Byte1]: 33
1046 00:26:49.906501
1047 00:26:49.906593 Set Vref, RX VrefLevel [Byte0]: 34
1048 00:26:49.906685 [Byte1]: 34
1049 00:26:49.906776
1050 00:26:49.906868 Set Vref, RX VrefLevel [Byte0]: 35
1051 00:26:49.906960 [Byte1]: 35
1052 00:26:49.907052
1053 00:26:49.907143 Set Vref, RX VrefLevel [Byte0]: 36
1054 00:26:49.907235 [Byte1]: 36
1055 00:26:49.907327
1056 00:26:49.907418 Set Vref, RX VrefLevel [Byte0]: 37
1057 00:26:49.907509 [Byte1]: 37
1058 00:26:49.907601
1059 00:26:49.907692 Set Vref, RX VrefLevel [Byte0]: 38
1060 00:26:49.907783 [Byte1]: 38
1061 00:26:49.907874
1062 00:26:49.907965 Set Vref, RX VrefLevel [Byte0]: 39
1063 00:26:49.908060 [Byte1]: 39
1064 00:26:49.908159
1065 00:26:49.908250 Set Vref, RX VrefLevel [Byte0]: 40
1066 00:26:49.908341 [Byte1]: 40
1067 00:26:49.908432
1068 00:26:49.908523 Set Vref, RX VrefLevel [Byte0]: 41
1069 00:26:49.908614 [Byte1]: 41
1070 00:26:49.908705
1071 00:26:49.908797 Set Vref, RX VrefLevel [Byte0]: 42
1072 00:26:49.908889 [Byte1]: 42
1073 00:26:49.908980
1074 00:26:49.909070 Set Vref, RX VrefLevel [Byte0]: 43
1075 00:26:49.909160 [Byte1]: 43
1076 00:26:49.909251
1077 00:26:49.909341 Set Vref, RX VrefLevel [Byte0]: 44
1078 00:26:49.909433 [Byte1]: 44
1079 00:26:49.909524
1080 00:26:49.909615 Set Vref, RX VrefLevel [Byte0]: 45
1081 00:26:49.909706 [Byte1]: 45
1082 00:26:49.909806
1083 00:26:49.909898 Set Vref, RX VrefLevel [Byte0]: 46
1084 00:26:49.909989 [Byte1]: 46
1085 00:26:49.910091
1086 00:26:49.910229 Set Vref, RX VrefLevel [Byte0]: 47
1087 00:26:49.910322 [Byte1]: 47
1088 00:26:49.910414
1089 00:26:49.910505 Set Vref, RX VrefLevel [Byte0]: 48
1090 00:26:49.910603 [Byte1]: 48
1091 00:26:49.910686
1092 00:26:49.910778 Set Vref, RX VrefLevel [Byte0]: 49
1093 00:26:49.910851 [Byte1]: 49
1094 00:26:49.910943
1095 00:26:49.911034 Set Vref, RX VrefLevel [Byte0]: 50
1096 00:26:49.911126 [Byte1]: 50
1097 00:26:49.911218
1098 00:26:49.911294 Set Vref, RX VrefLevel [Byte0]: 51
1099 00:26:49.911368 [Byte1]: 51
1100 00:26:49.911460
1101 00:26:49.911532 Set Vref, RX VrefLevel [Byte0]: 52
1102 00:26:49.911623 [Byte1]: 52
1103 00:26:49.911715
1104 00:26:49.911806 Set Vref, RX VrefLevel [Byte0]: 53
1105 00:26:49.911899 [Byte1]: 53
1106 00:26:49.911991
1107 00:26:49.912082 Set Vref, RX VrefLevel [Byte0]: 54
1108 00:26:49.912174 [Byte1]: 54
1109 00:26:49.912265
1110 00:26:49.912356 Set Vref, RX VrefLevel [Byte0]: 55
1111 00:26:49.912447 [Byte1]: 55
1112 00:26:49.912538
1113 00:26:49.912629 Set Vref, RX VrefLevel [Byte0]: 56
1114 00:26:49.912720 [Byte1]: 56
1115 00:26:49.912810
1116 00:26:49.912901 Set Vref, RX VrefLevel [Byte0]: 57
1117 00:26:49.912992 [Byte1]: 57
1118 00:26:49.913083
1119 00:26:49.913175 Set Vref, RX VrefLevel [Byte0]: 58
1120 00:26:49.913275 [Byte1]: 58
1121 00:26:49.913367
1122 00:26:49.913458 Set Vref, RX VrefLevel [Byte0]: 59
1123 00:26:49.913554 [Byte1]: 59
1124 00:26:49.913660
1125 00:26:49.913751 Set Vref, RX VrefLevel [Byte0]: 60
1126 00:26:49.913843 [Byte1]: 60
1127 00:26:49.913942
1128 00:26:49.914033 Set Vref, RX VrefLevel [Byte0]: 61
1129 00:26:49.914126 [Byte1]: 61
1130 00:26:49.914258
1131 00:26:49.914351 Set Vref, RX VrefLevel [Byte0]: 62
1132 00:26:49.914423 [Byte1]: 62
1133 00:26:49.914498
1134 00:26:49.914589 Set Vref, RX VrefLevel [Byte0]: 63
1135 00:26:49.914661 [Byte1]: 63
1136 00:26:49.914753
1137 00:26:49.914844 Set Vref, RX VrefLevel [Byte0]: 64
1138 00:26:49.914935 [Byte1]: 64
1139 00:26:49.915027
1140 00:26:49.915119 Set Vref, RX VrefLevel [Byte0]: 65
1141 00:26:49.915210 [Byte1]: 65
1142 00:26:49.915301
1143 00:26:49.915392 Set Vref, RX VrefLevel [Byte0]: 66
1144 00:26:49.915484 [Byte1]: 66
1145 00:26:49.915576
1146 00:26:49.915672 Set Vref, RX VrefLevel [Byte0]: 67
1147 00:26:49.915776 [Byte1]: 67
1148 00:26:49.915868
1149 00:26:49.915960 Set Vref, RX VrefLevel [Byte0]: 68
1150 00:26:49.916051 [Byte1]: 68
1151 00:26:49.916142
1152 00:26:49.916233 Set Vref, RX VrefLevel [Byte0]: 69
1153 00:26:49.916333 [Byte1]: 69
1154 00:26:49.916425
1155 00:26:49.916713 Set Vref, RX VrefLevel [Byte0]: 70
1156 00:26:49.916809 [Byte1]: 70
1157 00:26:49.916903
1158 00:26:49.916996 Set Vref, RX VrefLevel [Byte0]: 71
1159 00:26:49.917088 [Byte1]: 71
1160 00:26:49.917181
1161 00:26:49.917273 Set Vref, RX VrefLevel [Byte0]: 72
1162 00:26:49.917365 [Byte1]: 72
1163 00:26:49.917459
1164 00:26:49.917551 Set Vref, RX VrefLevel [Byte0]: 73
1165 00:26:49.917642 [Byte1]: 73
1166 00:26:49.917734
1167 00:26:49.917825 Set Vref, RX VrefLevel [Byte0]: 74
1168 00:26:49.917916 [Byte1]: 74
1169 00:26:49.918008
1170 00:26:49.918100 Set Vref, RX VrefLevel [Byte0]: 75
1171 00:26:49.918238 [Byte1]: 75
1172 00:26:49.918333
1173 00:26:49.918425 Set Vref, RX VrefLevel [Byte0]: 76
1174 00:26:49.918517 [Byte1]: 76
1175 00:26:49.918608
1176 00:26:49.918700 Set Vref, RX VrefLevel [Byte0]: 77
1177 00:26:49.918791 [Byte1]: 77
1178 00:26:49.918882
1179 00:26:49.918975 Set Vref, RX VrefLevel [Byte0]: 78
1180 00:26:49.919069 [Byte1]: 78
1181 00:26:49.919161
1182 00:26:49.919252 Set Vref, RX VrefLevel [Byte0]: 79
1183 00:26:49.919343 [Byte1]: 79
1184 00:26:49.919435
1185 00:26:49.919525 Set Vref, RX VrefLevel [Byte0]: 80
1186 00:26:49.919618 [Byte1]: 80
1187 00:26:49.919709
1188 00:26:49.919800 Set Vref, RX VrefLevel [Byte0]: 81
1189 00:26:49.919905 [Byte1]: 81
1190 00:26:49.919997
1191 00:26:49.920089 Set Vref, RX VrefLevel [Byte0]: 82
1192 00:26:49.920180 [Byte1]: 82
1193 00:26:49.920271
1194 00:26:49.920361 Final RX Vref Byte 0 = 68 to rank0
1195 00:26:49.920455 Final RX Vref Byte 1 = 53 to rank0
1196 00:26:49.920547 Final RX Vref Byte 0 = 68 to rank1
1197 00:26:49.920638 Final RX Vref Byte 1 = 53 to rank1==
1198 00:26:49.920729 Dram Type= 6, Freq= 0, CH_0, rank 0
1199 00:26:49.920823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1200 00:26:49.920917 ==
1201 00:26:49.921009 DQS Delay:
1202 00:26:49.921100 DQS0 = 0, DQS1 = 0
1203 00:26:49.921191 DQM Delay:
1204 00:26:49.921283 DQM0 = 88, DQM1 = 76
1205 00:26:49.921374 DQ Delay:
1206 00:26:49.921465 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =84
1207 00:26:49.921556 DQ4 =88, DQ5 =76, DQ6 =100, DQ7 =96
1208 00:26:49.921647 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1209 00:26:49.921741 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1210 00:26:49.921832
1211 00:26:49.921924
1212 00:26:49.922015 [DQSOSCAuto] RK0, (LSB)MR18= 0x482a, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 391 ps
1213 00:26:49.922107 CH0 RK0: MR19=606, MR18=482A
1214 00:26:49.922209 CH0_RK0: MR19=0x606, MR18=0x482A, DQSOSC=391, MR23=63, INC=96, DEC=64
1215 00:26:49.922302
1216 00:26:49.922394 ----->DramcWriteLeveling(PI) begin...
1217 00:26:49.922493 ==
1218 00:26:49.922585 Dram Type= 6, Freq= 0, CH_0, rank 1
1219 00:26:49.922679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1220 00:26:49.922771 ==
1221 00:26:49.922863 Write leveling (Byte 0): 33 => 33
1222 00:26:49.922946 Write leveling (Byte 1): 30 => 30
1223 00:26:49.923021 DramcWriteLeveling(PI) end<-----
1224 00:26:49.923124
1225 00:26:49.923215 ==
1226 00:26:49.923307 Dram Type= 6, Freq= 0, CH_0, rank 1
1227 00:26:49.923398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1228 00:26:49.923490 ==
1229 00:26:49.923581 [Gating] SW mode calibration
1230 00:26:49.923673 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1231 00:26:49.923767 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1232 00:26:49.923875 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1233 00:26:49.923967 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1234 00:26:49.924061 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1235 00:26:49.924155 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 00:26:49.924247 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 00:26:49.924339 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 00:26:49.924430 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 00:26:49.924521 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 00:26:49.924613 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 00:26:49.924705 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 00:26:49.924796 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 00:26:49.924887 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 00:26:49.924978 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 00:26:49.925069 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 00:26:49.925160 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 00:26:49.925252 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 00:26:49.925342 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 00:26:49.925433 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 00:26:49.925524 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1251 00:26:49.925615 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1252 00:26:49.925706 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 00:26:49.925797 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 00:26:49.925888 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1255 00:26:49.925998 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 00:26:49.926100 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 00:26:49.926231 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1258 00:26:49.926324 0 9 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
1259 00:26:49.926415 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1260 00:26:49.926508 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1261 00:26:49.926600 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1262 00:26:49.926691 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1263 00:26:49.926783 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1264 00:26:49.926874 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1265 00:26:49.926964 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
1266 00:26:49.927057 0 10 8 | B1->B0 | 3030 2828 | 1 0 | (0 1) (0 0)
1267 00:26:49.927149 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1268 00:26:49.927240 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1269 00:26:49.927331 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1270 00:26:49.927620 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1271 00:26:49.927716 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1272 00:26:49.927811 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1273 00:26:49.927906 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1274 00:26:49.928016 0 11 8 | B1->B0 | 2b2b 3a3a | 0 0 | (0 0) (1 1)
1275 00:26:49.928109 0 11 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
1276 00:26:49.928201 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1277 00:26:49.928294 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1278 00:26:49.928385 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1279 00:26:49.928477 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1280 00:26:49.928568 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1281 00:26:49.928660 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1282 00:26:49.928751 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1283 00:26:49.928843 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1284 00:26:49.928934 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1285 00:26:49.929026 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1286 00:26:49.929119 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1287 00:26:49.929211 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1288 00:26:49.929312 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1289 00:26:49.929404 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1290 00:26:49.929497 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1291 00:26:49.929590 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1292 00:26:49.929682 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1293 00:26:49.929774 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1294 00:26:49.929865 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1295 00:26:49.929956 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1296 00:26:49.930047 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1297 00:26:49.930140 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1298 00:26:49.930278 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1299 00:26:49.930371 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1300 00:26:49.930463 Total UI for P1: 0, mck2ui 16
1301 00:26:49.930556 best dqsien dly found for B0: ( 0, 14, 8)
1302 00:26:49.930649 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1303 00:26:49.930741 Total UI for P1: 0, mck2ui 16
1304 00:26:49.930833 best dqsien dly found for B1: ( 0, 14, 10)
1305 00:26:49.930925 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1306 00:26:49.931017 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1307 00:26:49.931108
1308 00:26:49.931199 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1309 00:26:49.931290 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1310 00:26:49.931381 [Gating] SW calibration Done
1311 00:26:49.931472 ==
1312 00:26:49.931564 Dram Type= 6, Freq= 0, CH_0, rank 1
1313 00:26:49.931656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1314 00:26:49.931748 ==
1315 00:26:49.931839 RX Vref Scan: 0
1316 00:26:49.931930
1317 00:26:49.932020 RX Vref 0 -> 0, step: 1
1318 00:26:49.932112
1319 00:26:49.932202 RX Delay -130 -> 252, step: 16
1320 00:26:49.932294 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1321 00:26:49.932385 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1322 00:26:49.932476 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1323 00:26:49.932568 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1324 00:26:49.932669 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1325 00:26:49.932762 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1326 00:26:49.932853 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1327 00:26:49.932943 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1328 00:26:49.933036 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1329 00:26:49.933127 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1330 00:26:49.933218 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1331 00:26:49.933311 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1332 00:26:49.933404 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1333 00:26:49.933494 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1334 00:26:49.933585 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1335 00:26:49.933680 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1336 00:26:49.933785 ==
1337 00:26:49.933877 Dram Type= 6, Freq= 0, CH_0, rank 1
1338 00:26:49.933968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1339 00:26:49.934060 ==
1340 00:26:49.934154 DQS Delay:
1341 00:26:49.934251 DQS0 = 0, DQS1 = 0
1342 00:26:49.934343 DQM Delay:
1343 00:26:49.934434 DQM0 = 85, DQM1 = 77
1344 00:26:49.934527 DQ Delay:
1345 00:26:49.934619 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77
1346 00:26:49.934711 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =101
1347 00:26:49.934803 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1348 00:26:49.934894 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1349 00:26:49.934987
1350 00:26:49.935078
1351 00:26:49.935169 ==
1352 00:26:49.935261 Dram Type= 6, Freq= 0, CH_0, rank 1
1353 00:26:49.935354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1354 00:26:49.935447 ==
1355 00:26:49.935539
1356 00:26:49.935630
1357 00:26:49.935721 TX Vref Scan disable
1358 00:26:49.935830 == TX Byte 0 ==
1359 00:26:49.935923 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1360 00:26:49.936016 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1361 00:26:49.936129 == TX Byte 1 ==
1362 00:26:49.936220 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1363 00:26:49.936311 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1364 00:26:49.936406 ==
1365 00:26:49.936498 Dram Type= 6, Freq= 0, CH_0, rank 1
1366 00:26:49.936590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1367 00:26:49.936680 ==
1368 00:26:49.936768 TX Vref=22, minBit 3, minWin=27, winSum=446
1369 00:26:49.936855 TX Vref=24, minBit 8, minWin=27, winSum=446
1370 00:26:49.936940 TX Vref=26, minBit 9, minWin=27, winSum=448
1371 00:26:49.937024 TX Vref=28, minBit 8, minWin=27, winSum=448
1372 00:26:49.937108 TX Vref=30, minBit 9, minWin=27, winSum=449
1373 00:26:49.937193 TX Vref=32, minBit 8, minWin=27, winSum=447
1374 00:26:49.937277 [TxChooseVref] Worse bit 9, Min win 27, Win sum 449, Final Vref 30
1375 00:26:49.937364
1376 00:26:49.937448 Final TX Range 1 Vref 30
1377 00:26:49.937531
1378 00:26:49.937615 ==
1379 00:26:49.937699 Dram Type= 6, Freq= 0, CH_0, rank 1
1380 00:26:49.937788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1381 00:26:49.937880 ==
1382 00:26:49.937963
1383 00:26:49.938047
1384 00:26:49.938130 TX Vref Scan disable
1385 00:26:49.938462 == TX Byte 0 ==
1386 00:26:49.938558 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1387 00:26:49.938648 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1388 00:26:49.938734 == TX Byte 1 ==
1389 00:26:49.938820 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1390 00:26:49.938906 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1391 00:26:49.938990
1392 00:26:49.939073 [DATLAT]
1393 00:26:49.939156 Freq=800, CH0 RK1
1394 00:26:49.939242
1395 00:26:49.939325 DATLAT Default: 0xa
1396 00:26:49.939408 0, 0xFFFF, sum = 0
1397 00:26:49.939504 1, 0xFFFF, sum = 0
1398 00:26:49.939591 2, 0xFFFF, sum = 0
1399 00:26:49.939675 3, 0xFFFF, sum = 0
1400 00:26:49.939758 4, 0xFFFF, sum = 0
1401 00:26:49.939860 5, 0xFFFF, sum = 0
1402 00:26:49.939945 6, 0xFFFF, sum = 0
1403 00:26:49.940032 7, 0xFFFF, sum = 0
1404 00:26:49.940116 8, 0xFFFF, sum = 0
1405 00:26:49.940201 9, 0x0, sum = 1
1406 00:26:49.940285 10, 0x0, sum = 2
1407 00:26:49.940369 11, 0x0, sum = 3
1408 00:26:49.940453 12, 0x0, sum = 4
1409 00:26:49.940536 best_step = 10
1410 00:26:49.940618
1411 00:26:49.940703 ==
1412 00:26:49.940786 Dram Type= 6, Freq= 0, CH_0, rank 1
1413 00:26:49.940869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1414 00:26:49.940954 ==
1415 00:26:49.941036 RX Vref Scan: 0
1416 00:26:49.941119
1417 00:26:49.941200 RX Vref 0 -> 0, step: 1
1418 00:26:49.941282
1419 00:26:49.941362 RX Delay -111 -> 252, step: 8
1420 00:26:49.941446 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1421 00:26:49.941530 iDelay=217, Bit 1, Center 88 (-23 ~ 200) 224
1422 00:26:49.941613 iDelay=217, Bit 2, Center 80 (-31 ~ 192) 224
1423 00:26:49.941695 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
1424 00:26:49.941778 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
1425 00:26:49.941873 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1426 00:26:49.941955 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1427 00:26:49.942037 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1428 00:26:49.942118 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
1429 00:26:49.942231 iDelay=217, Bit 9, Center 64 (-47 ~ 176) 224
1430 00:26:49.942328 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1431 00:26:49.942409 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
1432 00:26:49.942491 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1433 00:26:49.942590 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1434 00:26:49.942709 iDelay=217, Bit 14, Center 88 (-23 ~ 200) 224
1435 00:26:49.942823 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1436 00:26:49.942939 ==
1437 00:26:49.943041 Dram Type= 6, Freq= 0, CH_0, rank 1
1438 00:26:49.943126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1439 00:26:49.943209 ==
1440 00:26:49.943293 DQS Delay:
1441 00:26:49.943373 DQS0 = 0, DQS1 = 0
1442 00:26:49.943450 DQM Delay:
1443 00:26:49.943526 DQM0 = 85, DQM1 = 77
1444 00:26:49.943604 DQ Delay:
1445 00:26:49.943681 DQ0 =84, DQ1 =88, DQ2 =80, DQ3 =84
1446 00:26:49.943759 DQ4 =84, DQ5 =76, DQ6 =92, DQ7 =96
1447 00:26:49.943852 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1448 00:26:49.943939 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =84
1449 00:26:49.944020
1450 00:26:49.944099
1451 00:26:49.944178 [DQSOSCAuto] RK1, (LSB)MR18= 0x4006, (MSB)MR19= 0x606, tDQSOscB0 = 408 ps tDQSOscB1 = 393 ps
1452 00:26:49.944258 CH0 RK1: MR19=606, MR18=4006
1453 00:26:49.944337 CH0_RK1: MR19=0x606, MR18=0x4006, DQSOSC=393, MR23=63, INC=95, DEC=63
1454 00:26:49.944418 [RxdqsGatingPostProcess] freq 800
1455 00:26:49.944513 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1456 00:26:49.944599 Pre-setting of DQS Precalculation
1457 00:26:49.944682 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1458 00:26:49.944774 ==
1459 00:26:49.944870 Dram Type= 6, Freq= 0, CH_1, rank 0
1460 00:26:49.944967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1461 00:26:49.945066 ==
1462 00:26:49.945163 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1463 00:26:49.945264 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1464 00:26:49.945370 [CA 0] Center 36 (6~67) winsize 62
1465 00:26:49.945466 [CA 1] Center 36 (6~67) winsize 62
1466 00:26:49.945553 [CA 2] Center 34 (4~65) winsize 62
1467 00:26:49.945640 [CA 3] Center 34 (3~65) winsize 63
1468 00:26:49.945725 [CA 4] Center 34 (4~65) winsize 62
1469 00:26:49.945808 [CA 5] Center 34 (3~65) winsize 63
1470 00:26:49.945892
1471 00:26:49.945974 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1472 00:26:49.946069
1473 00:26:49.946152 [CATrainingPosCal] consider 1 rank data
1474 00:26:49.946278 u2DelayCellTimex100 = 270/100 ps
1475 00:26:49.946364 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1476 00:26:49.946448 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1477 00:26:49.946531 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1478 00:26:49.946614 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1479 00:26:49.946698 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1480 00:26:49.946782 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1481 00:26:49.946863
1482 00:26:49.946946 CA PerBit enable=1, Macro0, CA PI delay=34
1483 00:26:49.947028
1484 00:26:49.947109 [CBTSetCACLKResult] CA Dly = 34
1485 00:26:49.947190 CS Dly: 4 (0~35)
1486 00:26:49.947271 ==
1487 00:26:49.947353 Dram Type= 6, Freq= 0, CH_1, rank 1
1488 00:26:49.947435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1489 00:26:49.947517 ==
1490 00:26:49.947599 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1491 00:26:49.947682 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1492 00:26:49.947764 [CA 0] Center 36 (6~67) winsize 62
1493 00:26:49.947846 [CA 1] Center 36 (6~67) winsize 62
1494 00:26:49.947928 [CA 2] Center 34 (4~65) winsize 62
1495 00:26:49.948009 [CA 3] Center 34 (3~65) winsize 63
1496 00:26:49.948091 [CA 4] Center 34 (4~65) winsize 62
1497 00:26:49.948172 [CA 5] Center 34 (3~65) winsize 63
1498 00:26:49.948253
1499 00:26:49.948334 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1500 00:26:49.948415
1501 00:26:49.948496 [CATrainingPosCal] consider 2 rank data
1502 00:26:49.948577 u2DelayCellTimex100 = 270/100 ps
1503 00:26:49.948659 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1504 00:26:49.948741 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1505 00:26:49.948822 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1506 00:26:49.948904 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1507 00:26:49.948986 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1508 00:26:49.949068 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1509 00:26:49.949149
1510 00:26:49.949230 CA PerBit enable=1, Macro0, CA PI delay=34
1511 00:26:49.949311
1512 00:26:49.949392 [CBTSetCACLKResult] CA Dly = 34
1513 00:26:49.949473 CS Dly: 5 (0~38)
1514 00:26:49.949572
1515 00:26:49.949654 ----->DramcWriteLeveling(PI) begin...
1516 00:26:49.949737 ==
1517 00:26:49.949818 Dram Type= 6, Freq= 0, CH_1, rank 0
1518 00:26:49.950094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1519 00:26:49.950157 ==
1520 00:26:49.950222 Write leveling (Byte 0): 28 => 28
1521 00:26:49.950276 Write leveling (Byte 1): 30 => 30
1522 00:26:49.950329 DramcWriteLeveling(PI) end<-----
1523 00:26:49.950382
1524 00:26:49.950435 ==
1525 00:26:49.950487 Dram Type= 6, Freq= 0, CH_1, rank 0
1526 00:26:49.950539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1527 00:26:49.950592 ==
1528 00:26:49.950644 [Gating] SW mode calibration
1529 00:26:49.950697 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1530 00:26:49.950749 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1531 00:26:49.950802 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1532 00:26:49.950855 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1533 00:26:49.950908 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 00:26:49.950960 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 00:26:49.951012 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 00:26:49.951064 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 00:26:49.951116 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 00:26:49.951168 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 00:26:49.951219 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 00:26:49.951271 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 00:26:49.951323 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 00:26:49.951374 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 00:26:49.951426 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 00:26:49.951479 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 00:26:49.951530 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 00:26:49.951593 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 00:26:49.951645 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1548 00:26:49.951697 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1549 00:26:49.951749 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1550 00:26:49.951801 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 00:26:49.951853 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 00:26:49.951904 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 00:26:49.951956 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 00:26:49.952008 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 00:26:49.952060 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 00:26:49.952112 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 00:26:49.952164 0 9 8 | B1->B0 | 3131 3333 | 0 0 | (0 0) (0 0)
1558 00:26:49.952217 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1559 00:26:49.952269 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1560 00:26:49.952321 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1561 00:26:49.952373 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1562 00:26:49.952425 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1563 00:26:49.952477 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1564 00:26:49.952538 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 0) (1 0)
1565 00:26:49.952592 0 10 8 | B1->B0 | 2d2d 2b2b | 0 0 | (1 1) (0 0)
1566 00:26:49.952644 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1567 00:26:49.952695 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1568 00:26:49.952748 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1569 00:26:49.952799 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1570 00:26:49.952851 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1571 00:26:49.952903 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1572 00:26:49.952956 0 11 4 | B1->B0 | 2828 2929 | 1 0 | (0 0) (0 0)
1573 00:26:49.953007 0 11 8 | B1->B0 | 3838 4040 | 0 1 | (0 0) (0 0)
1574 00:26:49.953060 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1575 00:26:49.953111 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1576 00:26:49.953164 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1577 00:26:49.953216 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1578 00:26:49.953268 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1579 00:26:49.953320 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1580 00:26:49.953373 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1581 00:26:49.953425 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1582 00:26:49.953476 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1583 00:26:49.953529 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1584 00:26:49.953596 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1585 00:26:49.953649 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1586 00:26:49.953701 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1587 00:26:49.953753 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1588 00:26:49.953805 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1589 00:26:49.953857 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1590 00:26:49.953909 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1591 00:26:49.953962 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1592 00:26:49.954014 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1593 00:26:49.954066 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1594 00:26:49.954117 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1595 00:26:49.954180 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1596 00:26:49.954305 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1597 00:26:49.954387 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1598 00:26:49.954468 Total UI for P1: 0, mck2ui 16
1599 00:26:49.954551 best dqsien dly found for B0: ( 0, 14, 4)
1600 00:26:49.954633 Total UI for P1: 0, mck2ui 16
1601 00:26:49.954715 best dqsien dly found for B1: ( 0, 14, 6)
1602 00:26:49.954798 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1603 00:26:49.954862 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1604 00:26:49.954916
1605 00:26:49.955158 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1606 00:26:49.955218 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1607 00:26:49.955272 [Gating] SW calibration Done
1608 00:26:49.955324 ==
1609 00:26:49.955377 Dram Type= 6, Freq= 0, CH_1, rank 0
1610 00:26:49.955430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1611 00:26:49.955482 ==
1612 00:26:49.955539 RX Vref Scan: 0
1613 00:26:49.955598
1614 00:26:49.955650 RX Vref 0 -> 0, step: 1
1615 00:26:49.955703
1616 00:26:49.955765 RX Delay -130 -> 252, step: 16
1617 00:26:49.955818 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1618 00:26:49.955870 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1619 00:26:49.955923 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1620 00:26:49.955975 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1621 00:26:49.956028 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1622 00:26:49.956080 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1623 00:26:49.956132 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1624 00:26:49.956184 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1625 00:26:49.956236 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1626 00:26:49.956288 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1627 00:26:49.956340 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1628 00:26:49.956392 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1629 00:26:49.956445 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1630 00:26:49.956497 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1631 00:26:49.956549 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1632 00:26:49.956601 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1633 00:26:49.956654 ==
1634 00:26:49.956706 Dram Type= 6, Freq= 0, CH_1, rank 0
1635 00:26:49.956758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1636 00:26:49.956811 ==
1637 00:26:49.956862 DQS Delay:
1638 00:26:49.956914 DQS0 = 0, DQS1 = 0
1639 00:26:49.956966 DQM Delay:
1640 00:26:49.957017 DQM0 = 89, DQM1 = 79
1641 00:26:49.957069 DQ Delay:
1642 00:26:49.957121 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1643 00:26:49.957173 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1644 00:26:49.957225 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1645 00:26:49.957277 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1646 00:26:49.957329
1647 00:26:49.957380
1648 00:26:49.957432 ==
1649 00:26:49.957484 Dram Type= 6, Freq= 0, CH_1, rank 0
1650 00:26:49.957540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1651 00:26:49.957603 ==
1652 00:26:49.957657
1653 00:26:49.957709
1654 00:26:49.957760 TX Vref Scan disable
1655 00:26:49.957811 == TX Byte 0 ==
1656 00:26:49.957863 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1657 00:26:49.957916 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1658 00:26:49.957967 == TX Byte 1 ==
1659 00:26:49.958019 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1660 00:26:49.958071 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1661 00:26:49.958123 ==
1662 00:26:49.958209 Dram Type= 6, Freq= 0, CH_1, rank 0
1663 00:26:49.958277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1664 00:26:49.958329 ==
1665 00:26:49.958381 TX Vref=22, minBit 11, minWin=26, winSum=444
1666 00:26:49.958434 TX Vref=24, minBit 8, minWin=27, winSum=447
1667 00:26:49.958486 TX Vref=26, minBit 8, minWin=27, winSum=450
1668 00:26:49.958539 TX Vref=28, minBit 9, minWin=27, winSum=450
1669 00:26:49.958594 TX Vref=30, minBit 9, minWin=27, winSum=451
1670 00:26:49.958658 TX Vref=32, minBit 8, minWin=27, winSum=447
1671 00:26:49.958748 [TxChooseVref] Worse bit 9, Min win 27, Win sum 451, Final Vref 30
1672 00:26:49.958809
1673 00:26:49.958862 Final TX Range 1 Vref 30
1674 00:26:49.958915
1675 00:26:49.958975 ==
1676 00:26:49.959029 Dram Type= 6, Freq= 0, CH_1, rank 0
1677 00:26:49.959082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1678 00:26:49.959155 ==
1679 00:26:49.959208
1680 00:26:49.959260
1681 00:26:49.959314 TX Vref Scan disable
1682 00:26:49.959367 == TX Byte 0 ==
1683 00:26:49.959419 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1684 00:26:49.959472 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1685 00:26:49.959528 == TX Byte 1 ==
1686 00:26:49.959597 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1687 00:26:49.959700 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1688 00:26:49.959781
1689 00:26:49.959862 [DATLAT]
1690 00:26:49.959942 Freq=800, CH1 RK0
1691 00:26:49.960023
1692 00:26:49.960104 DATLAT Default: 0xa
1693 00:26:49.960185 0, 0xFFFF, sum = 0
1694 00:26:49.960278 1, 0xFFFF, sum = 0
1695 00:26:49.960366 2, 0xFFFF, sum = 0
1696 00:26:49.960423 3, 0xFFFF, sum = 0
1697 00:26:49.960477 4, 0xFFFF, sum = 0
1698 00:26:49.960531 5, 0xFFFF, sum = 0
1699 00:26:49.960584 6, 0xFFFF, sum = 0
1700 00:26:49.960638 7, 0xFFFF, sum = 0
1701 00:26:49.960691 8, 0xFFFF, sum = 0
1702 00:26:49.960744 9, 0x0, sum = 1
1703 00:26:49.960797 10, 0x0, sum = 2
1704 00:26:49.960851 11, 0x0, sum = 3
1705 00:26:49.960904 12, 0x0, sum = 4
1706 00:26:49.960957 best_step = 10
1707 00:26:49.961009
1708 00:26:49.961060 ==
1709 00:26:49.961113 Dram Type= 6, Freq= 0, CH_1, rank 0
1710 00:26:49.961164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1711 00:26:49.961217 ==
1712 00:26:49.961269 RX Vref Scan: 1
1713 00:26:49.961322
1714 00:26:49.961374 Set Vref Range= 32 -> 127
1715 00:26:49.961426
1716 00:26:49.961478 RX Vref 32 -> 127, step: 1
1717 00:26:49.961530
1718 00:26:49.961593 RX Delay -95 -> 252, step: 8
1719 00:26:49.961646
1720 00:26:49.961698 Set Vref, RX VrefLevel [Byte0]: 32
1721 00:26:49.961750 [Byte1]: 32
1722 00:26:49.961802
1723 00:26:49.961854 Set Vref, RX VrefLevel [Byte0]: 33
1724 00:26:49.961906 [Byte1]: 33
1725 00:26:49.961959
1726 00:26:49.962010 Set Vref, RX VrefLevel [Byte0]: 34
1727 00:26:49.962062 [Byte1]: 34
1728 00:26:49.962115
1729 00:26:49.962176 Set Vref, RX VrefLevel [Byte0]: 35
1730 00:26:49.962270 [Byte1]: 35
1731 00:26:49.962322
1732 00:26:49.962374 Set Vref, RX VrefLevel [Byte0]: 36
1733 00:26:49.962436 [Byte1]: 36
1734 00:26:49.962490
1735 00:26:49.962542 Set Vref, RX VrefLevel [Byte0]: 37
1736 00:26:49.962594 [Byte1]: 37
1737 00:26:49.962646
1738 00:26:49.962698 Set Vref, RX VrefLevel [Byte0]: 38
1739 00:26:49.962750 [Byte1]: 38
1740 00:26:49.962802
1741 00:26:49.962854 Set Vref, RX VrefLevel [Byte0]: 39
1742 00:26:49.962906 [Byte1]: 39
1743 00:26:49.962958
1744 00:26:49.963010 Set Vref, RX VrefLevel [Byte0]: 40
1745 00:26:49.963063 [Byte1]: 40
1746 00:26:49.963114
1747 00:26:49.963166 Set Vref, RX VrefLevel [Byte0]: 41
1748 00:26:49.963218 [Byte1]: 41
1749 00:26:49.963270
1750 00:26:49.963322 Set Vref, RX VrefLevel [Byte0]: 42
1751 00:26:49.963373 [Byte1]: 42
1752 00:26:49.963425
1753 00:26:49.963483 Set Vref, RX VrefLevel [Byte0]: 43
1754 00:26:49.963539 [Byte1]: 43
1755 00:26:49.963600
1756 00:26:49.963654 Set Vref, RX VrefLevel [Byte0]: 44
1757 00:26:49.963707 [Byte1]: 44
1758 00:26:49.963759
1759 00:26:49.963811 Set Vref, RX VrefLevel [Byte0]: 45
1760 00:26:49.963863 [Byte1]: 45
1761 00:26:49.963915
1762 00:26:49.964163 Set Vref, RX VrefLevel [Byte0]: 46
1763 00:26:49.964222 [Byte1]: 46
1764 00:26:49.964275
1765 00:26:49.964328 Set Vref, RX VrefLevel [Byte0]: 47
1766 00:26:49.964381 [Byte1]: 47
1767 00:26:49.964433
1768 00:26:49.964485 Set Vref, RX VrefLevel [Byte0]: 48
1769 00:26:49.964537 [Byte1]: 48
1770 00:26:49.964589
1771 00:26:49.964641 Set Vref, RX VrefLevel [Byte0]: 49
1772 00:26:49.964692 [Byte1]: 49
1773 00:26:49.964745
1774 00:26:49.964796 Set Vref, RX VrefLevel [Byte0]: 50
1775 00:26:49.964848 [Byte1]: 50
1776 00:26:49.964899
1777 00:26:49.964951 Set Vref, RX VrefLevel [Byte0]: 51
1778 00:26:49.965003 [Byte1]: 51
1779 00:26:49.965055
1780 00:26:49.965106 Set Vref, RX VrefLevel [Byte0]: 52
1781 00:26:49.965158 [Byte1]: 52
1782 00:26:49.965210
1783 00:26:49.965262 Set Vref, RX VrefLevel [Byte0]: 53
1784 00:26:49.965314 [Byte1]: 53
1785 00:26:49.965367
1786 00:26:49.965418 Set Vref, RX VrefLevel [Byte0]: 54
1787 00:26:49.965470 [Byte1]: 54
1788 00:26:49.965522
1789 00:26:49.965590 Set Vref, RX VrefLevel [Byte0]: 55
1790 00:26:49.965643 [Byte1]: 55
1791 00:26:49.965695
1792 00:26:49.965747 Set Vref, RX VrefLevel [Byte0]: 56
1793 00:26:49.965798 [Byte1]: 56
1794 00:26:49.965850
1795 00:26:49.965902 Set Vref, RX VrefLevel [Byte0]: 57
1796 00:26:49.965954 [Byte1]: 57
1797 00:26:49.966005
1798 00:26:49.966056 Set Vref, RX VrefLevel [Byte0]: 58
1799 00:26:49.966109 [Byte1]: 58
1800 00:26:49.966168
1801 00:26:49.966259 Set Vref, RX VrefLevel [Byte0]: 59
1802 00:26:49.966311 [Byte1]: 59
1803 00:26:49.966363
1804 00:26:49.966415 Set Vref, RX VrefLevel [Byte0]: 60
1805 00:26:49.966467 [Byte1]: 60
1806 00:26:49.966518
1807 00:26:49.966570 Set Vref, RX VrefLevel [Byte0]: 61
1808 00:26:49.966622 [Byte1]: 61
1809 00:26:49.966674
1810 00:26:49.966726 Set Vref, RX VrefLevel [Byte0]: 62
1811 00:26:49.966778 [Byte1]: 62
1812 00:26:49.966829
1813 00:26:49.966881 Set Vref, RX VrefLevel [Byte0]: 63
1814 00:26:49.966932 [Byte1]: 63
1815 00:26:49.966984
1816 00:26:49.967036 Set Vref, RX VrefLevel [Byte0]: 64
1817 00:26:49.967088 [Byte1]: 64
1818 00:26:49.967140
1819 00:26:49.967192 Set Vref, RX VrefLevel [Byte0]: 65
1820 00:26:49.967243 [Byte1]: 65
1821 00:26:49.967295
1822 00:26:49.967347 Set Vref, RX VrefLevel [Byte0]: 66
1823 00:26:49.967399 [Byte1]: 66
1824 00:26:49.967451
1825 00:26:49.967502 Set Vref, RX VrefLevel [Byte0]: 67
1826 00:26:49.967557 [Byte1]: 67
1827 00:26:49.967616
1828 00:26:49.967668 Set Vref, RX VrefLevel [Byte0]: 68
1829 00:26:49.967720 [Byte1]: 68
1830 00:26:49.967771
1831 00:26:49.967823 Set Vref, RX VrefLevel [Byte0]: 69
1832 00:26:49.967875 [Byte1]: 69
1833 00:26:49.967927
1834 00:26:49.967978 Set Vref, RX VrefLevel [Byte0]: 70
1835 00:26:49.968029 [Byte1]: 70
1836 00:26:49.968081
1837 00:26:49.968133 Set Vref, RX VrefLevel [Byte0]: 71
1838 00:26:49.968184 [Byte1]: 71
1839 00:26:49.968236
1840 00:26:49.968287 Set Vref, RX VrefLevel [Byte0]: 72
1841 00:26:49.968340 [Byte1]: 72
1842 00:26:49.968391
1843 00:26:49.968442 Set Vref, RX VrefLevel [Byte0]: 73
1844 00:26:49.968494 [Byte1]: 73
1845 00:26:49.968546
1846 00:26:49.968598 Set Vref, RX VrefLevel [Byte0]: 74
1847 00:26:49.968650 [Byte1]: 74
1848 00:26:49.968701
1849 00:26:49.968752 Final RX Vref Byte 0 = 52 to rank0
1850 00:26:49.968805 Final RX Vref Byte 1 = 63 to rank0
1851 00:26:49.968857 Final RX Vref Byte 0 = 52 to rank1
1852 00:26:49.968909 Final RX Vref Byte 1 = 63 to rank1==
1853 00:26:49.968961 Dram Type= 6, Freq= 0, CH_1, rank 0
1854 00:26:49.969013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1855 00:26:49.969065 ==
1856 00:26:49.969126 DQS Delay:
1857 00:26:49.969179 DQS0 = 0, DQS1 = 0
1858 00:26:49.969231 DQM Delay:
1859 00:26:49.969282 DQM0 = 86, DQM1 = 79
1860 00:26:49.969334 DQ Delay:
1861 00:26:49.969386 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =80
1862 00:26:49.969439 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =84
1863 00:26:49.969490 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1864 00:26:49.969546 DQ12 =88, DQ13 =84, DQ14 =88, DQ15 =88
1865 00:26:49.969611
1866 00:26:49.969715
1867 00:26:49.969827 [DQSOSCAuto] RK0, (LSB)MR18= 0x3622, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
1868 00:26:49.969915 CH1 RK0: MR19=606, MR18=3622
1869 00:26:49.969999 CH1_RK0: MR19=0x606, MR18=0x3622, DQSOSC=396, MR23=63, INC=94, DEC=62
1870 00:26:49.970081
1871 00:26:49.970168 ----->DramcWriteLeveling(PI) begin...
1872 00:26:49.970257 ==
1873 00:26:49.970316 Dram Type= 6, Freq= 0, CH_1, rank 1
1874 00:26:49.970379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1875 00:26:49.970461 ==
1876 00:26:49.970516 Write leveling (Byte 0): 28 => 28
1877 00:26:49.970569 Write leveling (Byte 1): 32 => 32
1878 00:26:49.970621 DramcWriteLeveling(PI) end<-----
1879 00:26:49.970674
1880 00:26:49.970725 ==
1881 00:26:49.970777 Dram Type= 6, Freq= 0, CH_1, rank 1
1882 00:26:49.970830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1883 00:26:49.970883 ==
1884 00:26:49.970935 [Gating] SW mode calibration
1885 00:26:49.970987 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1886 00:26:49.971041 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1887 00:26:49.971093 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1888 00:26:49.971146 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1889 00:26:49.971199 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 00:26:49.971251 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 00:26:49.971303 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 00:26:49.971355 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 00:26:49.971407 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 00:26:49.971459 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 00:26:49.971515 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 00:26:49.971567 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 00:26:49.971619 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 00:26:49.971676 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 00:26:49.971735 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 00:26:49.971820 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 00:26:49.972091 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 00:26:49.972155 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 00:26:49.972210 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 00:26:49.972277 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1905 00:26:49.972331 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1906 00:26:49.972383 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 00:26:49.972446 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 00:26:49.972510 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 00:26:49.972564 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 00:26:49.972625 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1911 00:26:49.972678 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1912 00:26:49.972731 0 9 4 | B1->B0 | 2322 2323 | 1 0 | (0 0) (0 0)
1913 00:26:49.972786 0 9 8 | B1->B0 | 3434 2626 | 1 1 | (1 1) (1 1)
1914 00:26:49.972839 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1915 00:26:49.972891 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1916 00:26:49.972945 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1917 00:26:49.973027 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1918 00:26:49.973109 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1919 00:26:49.973193 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1920 00:26:49.973275 0 10 4 | B1->B0 | 3333 3333 | 0 1 | (0 1) (1 1)
1921 00:26:49.973357 0 10 8 | B1->B0 | 2727 2f2f | 0 0 | (0 0) (0 0)
1922 00:26:49.973439 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1923 00:26:49.973521 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1924 00:26:49.973603 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1925 00:26:49.973684 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1926 00:26:49.973766 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1927 00:26:49.973848 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1928 00:26:49.973930 0 11 4 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
1929 00:26:49.974011 0 11 8 | B1->B0 | 3f3f 3535 | 0 0 | (0 0) (0 0)
1930 00:26:49.974093 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1931 00:26:49.974208 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1932 00:26:49.974306 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1933 00:26:49.974388 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1934 00:26:49.974470 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1935 00:26:49.974552 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1936 00:26:49.974634 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1937 00:26:49.974716 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 00:26:49.974797 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 00:26:49.974879 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1940 00:26:49.974961 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1941 00:26:49.975043 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1942 00:26:49.975125 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1943 00:26:49.975206 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1944 00:26:49.975288 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1945 00:26:49.975370 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1946 00:26:49.975461 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1947 00:26:49.975544 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1948 00:26:49.975626 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1949 00:26:49.975709 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1950 00:26:49.975791 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1951 00:26:49.975872 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1952 00:26:49.975954 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1953 00:26:49.976035 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1954 00:26:49.976117 Total UI for P1: 0, mck2ui 16
1955 00:26:49.976199 best dqsien dly found for B1: ( 0, 14, 4)
1956 00:26:49.976281 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1957 00:26:49.976362 Total UI for P1: 0, mck2ui 16
1958 00:26:49.976444 best dqsien dly found for B0: ( 0, 14, 8)
1959 00:26:49.976526 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1960 00:26:49.976608 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1961 00:26:49.976689
1962 00:26:49.976770 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1963 00:26:49.976852 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1964 00:26:49.976933 [Gating] SW calibration Done
1965 00:26:49.977014 ==
1966 00:26:49.977095 Dram Type= 6, Freq= 0, CH_1, rank 1
1967 00:26:49.977177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1968 00:26:49.977259 ==
1969 00:26:49.977340 RX Vref Scan: 0
1970 00:26:49.977424
1971 00:26:49.977513 RX Vref 0 -> 0, step: 1
1972 00:26:49.977594
1973 00:26:49.977675 RX Delay -130 -> 252, step: 16
1974 00:26:49.977756 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1975 00:26:49.977838 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1976 00:26:49.977920 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1977 00:26:49.978001 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1978 00:26:49.978083 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1979 00:26:49.978174 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1980 00:26:49.978299 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1981 00:26:49.978381 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1982 00:26:49.978462 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1983 00:26:49.978544 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1984 00:26:49.978626 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1985 00:26:49.978717 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1986 00:26:49.978799 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1987 00:26:50.120568 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1988 00:26:50.121183 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1989 00:26:50.121560 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1990 00:26:50.121906 ==
1991 00:26:50.122272 Dram Type= 6, Freq= 0, CH_1, rank 1
1992 00:26:50.122605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1993 00:26:50.123326 ==
1994 00:26:50.123681 DQS Delay:
1995 00:26:50.124002 DQS0 = 0, DQS1 = 0
1996 00:26:50.124317 DQM Delay:
1997 00:26:50.124627 DQM0 = 86, DQM1 = 79
1998 00:26:50.125011 DQ Delay:
1999 00:26:50.125385 DQ0 =85, DQ1 =77, DQ2 =77, DQ3 =77
2000 00:26:50.125700 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
2001 00:26:50.126006 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
2002 00:26:50.126363 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
2003 00:26:50.126673
2004 00:26:50.127013
2005 00:26:50.127322 ==
2006 00:26:50.127622 Dram Type= 6, Freq= 0, CH_1, rank 1
2007 00:26:50.127924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2008 00:26:50.128230 ==
2009 00:26:50.128532
2010 00:26:50.128846
2011 00:26:50.129205 TX Vref Scan disable
2012 00:26:50.129513 == TX Byte 0 ==
2013 00:26:50.129814 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2014 00:26:50.130113 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2015 00:26:50.130576 == TX Byte 1 ==
2016 00:26:50.130896 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
2017 00:26:50.131204 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
2018 00:26:50.131503 ==
2019 00:26:50.131803 Dram Type= 6, Freq= 0, CH_1, rank 1
2020 00:26:50.132104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2021 00:26:50.132409 ==
2022 00:26:50.132723 TX Vref=22, minBit 8, minWin=26, winSum=444
2023 00:26:50.133027 TX Vref=24, minBit 8, minWin=27, winSum=446
2024 00:26:50.133331 TX Vref=26, minBit 8, minWin=27, winSum=452
2025 00:26:50.133633 TX Vref=28, minBit 8, minWin=27, winSum=450
2026 00:26:50.133931 TX Vref=30, minBit 8, minWin=27, winSum=449
2027 00:26:50.134281 TX Vref=32, minBit 8, minWin=27, winSum=449
2028 00:26:50.134599 [TxChooseVref] Worse bit 8, Min win 27, Win sum 452, Final Vref 26
2029 00:26:50.134905
2030 00:26:50.135201 Final TX Range 1 Vref 26
2031 00:26:50.135502
2032 00:26:50.135799 ==
2033 00:26:50.136097 Dram Type= 6, Freq= 0, CH_1, rank 1
2034 00:26:50.136395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2035 00:26:50.136698 ==
2036 00:26:50.137041
2037 00:26:50.137365
2038 00:26:50.137660 TX Vref Scan disable
2039 00:26:50.137960 == TX Byte 0 ==
2040 00:26:50.138298 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2041 00:26:50.138608 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2042 00:26:50.138909 == TX Byte 1 ==
2043 00:26:50.139296 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
2044 00:26:50.139606 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
2045 00:26:50.139908
2046 00:26:50.140204 [DATLAT]
2047 00:26:50.140500 Freq=800, CH1 RK1
2048 00:26:50.140802
2049 00:26:50.141100 DATLAT Default: 0xa
2050 00:26:50.141398 0, 0xFFFF, sum = 0
2051 00:26:50.141703 1, 0xFFFF, sum = 0
2052 00:26:50.142007 2, 0xFFFF, sum = 0
2053 00:26:50.142371 3, 0xFFFF, sum = 0
2054 00:26:50.142678 4, 0xFFFF, sum = 0
2055 00:26:50.142980 5, 0xFFFF, sum = 0
2056 00:26:50.143366 6, 0xFFFF, sum = 0
2057 00:26:50.143689 7, 0xFFFF, sum = 0
2058 00:26:50.143993 8, 0xFFFF, sum = 0
2059 00:26:50.144296 9, 0x0, sum = 1
2060 00:26:50.144599 10, 0x0, sum = 2
2061 00:26:50.144905 11, 0x0, sum = 3
2062 00:26:50.145203 12, 0x0, sum = 4
2063 00:26:50.145442 best_step = 10
2064 00:26:50.145654
2065 00:26:50.145861 ==
2066 00:26:50.146074 Dram Type= 6, Freq= 0, CH_1, rank 1
2067 00:26:50.146323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2068 00:26:50.146541 ==
2069 00:26:50.146751 RX Vref Scan: 0
2070 00:26:50.146961
2071 00:26:50.147315 RX Vref 0 -> 0, step: 1
2072 00:26:50.147554
2073 00:26:50.147771 RX Delay -95 -> 252, step: 8
2074 00:26:50.147988 iDelay=217, Bit 0, Center 88 (-23 ~ 200) 224
2075 00:26:50.148203 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2076 00:26:50.148415 iDelay=217, Bit 2, Center 80 (-31 ~ 192) 224
2077 00:26:50.148629 iDelay=217, Bit 3, Center 84 (-23 ~ 192) 216
2078 00:26:50.148842 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2079 00:26:50.149054 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2080 00:26:50.149263 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2081 00:26:50.149475 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2082 00:26:50.149685 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2083 00:26:50.149915 iDelay=217, Bit 9, Center 68 (-47 ~ 184) 232
2084 00:26:50.150287 iDelay=217, Bit 10, Center 84 (-31 ~ 200) 232
2085 00:26:50.150457 iDelay=217, Bit 11, Center 72 (-39 ~ 184) 224
2086 00:26:50.150618 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
2087 00:26:50.150775 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2088 00:26:50.150934 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2089 00:26:50.151090 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2090 00:26:50.151245 ==
2091 00:26:50.151401 Dram Type= 6, Freq= 0, CH_1, rank 1
2092 00:26:50.151558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2093 00:26:50.151718 ==
2094 00:26:50.151875 DQS Delay:
2095 00:26:50.152031 DQS0 = 0, DQS1 = 0
2096 00:26:50.152190 DQM Delay:
2097 00:26:50.152348 DQM0 = 87, DQM1 = 79
2098 00:26:50.152507 DQ Delay:
2099 00:26:50.152663 DQ0 =88, DQ1 =80, DQ2 =80, DQ3 =84
2100 00:26:50.152821 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2101 00:26:50.152979 DQ8 =68, DQ9 =68, DQ10 =84, DQ11 =72
2102 00:26:50.153136 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
2103 00:26:50.153292
2104 00:26:50.153448
2105 00:26:50.153606 [DQSOSCAuto] RK1, (LSB)MR18= 0x1d16, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 402 ps
2106 00:26:50.153767 CH1 RK1: MR19=606, MR18=1D16
2107 00:26:50.153924 CH1_RK1: MR19=0x606, MR18=0x1D16, DQSOSC=402, MR23=63, INC=91, DEC=60
2108 00:26:50.154082 [RxdqsGatingPostProcess] freq 800
2109 00:26:50.154268 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2110 00:26:50.154430 Pre-setting of DQS Precalculation
2111 00:26:50.154588 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2112 00:26:50.154747 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2113 00:26:50.154907 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2114 00:26:50.155066
2115 00:26:50.155233
2116 00:26:50.155357 [Calibration Summary] 1600 Mbps
2117 00:26:50.155483 CH 0, Rank 0
2118 00:26:50.155607 SW Impedance : PASS
2119 00:26:50.155732 DUTY Scan : NO K
2120 00:26:50.155855 ZQ Calibration : PASS
2121 00:26:50.155980 Jitter Meter : NO K
2122 00:26:50.156105 CBT Training : PASS
2123 00:26:50.156230 Write leveling : PASS
2124 00:26:50.156353 RX DQS gating : PASS
2125 00:26:50.156478 RX DQ/DQS(RDDQC) : PASS
2126 00:26:50.156602 TX DQ/DQS : PASS
2127 00:26:50.156727 RX DATLAT : PASS
2128 00:26:50.156850 RX DQ/DQS(Engine): PASS
2129 00:26:50.156974 TX OE : NO K
2130 00:26:50.157099 All Pass.
2131 00:26:50.157223
2132 00:26:50.157346 CH 0, Rank 1
2133 00:26:50.157470 SW Impedance : PASS
2134 00:26:50.157593 DUTY Scan : NO K
2135 00:26:50.157717 ZQ Calibration : PASS
2136 00:26:50.157840 Jitter Meter : NO K
2137 00:26:50.157964 CBT Training : PASS
2138 00:26:50.158088 Write leveling : PASS
2139 00:26:50.158251 RX DQS gating : PASS
2140 00:26:50.158645 RX DQ/DQS(RDDQC) : PASS
2141 00:26:50.158793 TX DQ/DQS : PASS
2142 00:26:50.158922 RX DATLAT : PASS
2143 00:26:50.159046 RX DQ/DQS(Engine): PASS
2144 00:26:50.159171 TX OE : NO K
2145 00:26:50.159296 All Pass.
2146 00:26:50.159420
2147 00:26:50.159543 CH 1, Rank 0
2148 00:26:50.159668 SW Impedance : PASS
2149 00:26:50.159794 DUTY Scan : NO K
2150 00:26:50.159919 ZQ Calibration : PASS
2151 00:26:50.160043 Jitter Meter : NO K
2152 00:26:50.160168 CBT Training : PASS
2153 00:26:50.160292 Write leveling : PASS
2154 00:26:50.160395 RX DQS gating : PASS
2155 00:26:50.160497 RX DQ/DQS(RDDQC) : PASS
2156 00:26:50.160600 TX DQ/DQS : PASS
2157 00:26:50.160703 RX DATLAT : PASS
2158 00:26:50.160901 RX DQ/DQS(Engine): PASS
2159 00:26:50.161025 TX OE : NO K
2160 00:26:50.161133 All Pass.
2161 00:26:50.161237
2162 00:26:50.161341 CH 1, Rank 1
2163 00:26:50.161449 SW Impedance : PASS
2164 00:26:50.161554 DUTY Scan : NO K
2165 00:26:50.161656 ZQ Calibration : PASS
2166 00:26:50.161761 Jitter Meter : NO K
2167 00:26:50.161864 CBT Training : PASS
2168 00:26:50.161968 Write leveling : PASS
2169 00:26:50.162070 RX DQS gating : PASS
2170 00:26:50.162189 RX DQ/DQS(RDDQC) : PASS
2171 00:26:50.162296 TX DQ/DQS : PASS
2172 00:26:50.162401 RX DATLAT : PASS
2173 00:26:50.162505 RX DQ/DQS(Engine): PASS
2174 00:26:50.162607 TX OE : NO K
2175 00:26:50.162710 All Pass.
2176 00:26:50.162813
2177 00:26:50.162915 DramC Write-DBI off
2178 00:26:50.163016 PER_BANK_REFRESH: Hybrid Mode
2179 00:26:50.163117 TX_TRACKING: ON
2180 00:26:50.163221 [GetDramInforAfterCalByMRR] Vendor 6.
2181 00:26:50.163324 [GetDramInforAfterCalByMRR] Revision 606.
2182 00:26:50.163426 [GetDramInforAfterCalByMRR] Revision 2 0.
2183 00:26:50.163528 MR0 0x3b3b
2184 00:26:50.163631 MR8 0x5151
2185 00:26:50.163735 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2186 00:26:50.163839
2187 00:26:50.163939 MR0 0x3b3b
2188 00:26:50.164042 MR8 0x5151
2189 00:26:50.164145 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2190 00:26:50.164249
2191 00:26:50.164351 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2192 00:26:50.164458 [FAST_K] Save calibration result to emmc
2193 00:26:50.164561 [FAST_K] Save calibration result to emmc
2194 00:26:50.164664 dram_init: config_dvfs: 1
2195 00:26:50.164767 dramc_set_vcore_voltage set vcore to 662500
2196 00:26:50.164871 Read voltage for 1200, 2
2197 00:26:50.164980 Vio18 = 0
2198 00:26:50.165097 Vcore = 662500
2199 00:26:50.165210 Vdram = 0
2200 00:26:50.165344 Vddq = 0
2201 00:26:50.165449 Vmddr = 0
2202 00:26:50.165538 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2203 00:26:50.165627 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2204 00:26:50.165718 MEM_TYPE=3, freq_sel=15
2205 00:26:50.165807 sv_algorithm_assistance_LP4_1600
2206 00:26:50.165894 ============ PULL DRAM RESETB DOWN ============
2207 00:26:50.165982 ========== PULL DRAM RESETB DOWN end =========
2208 00:26:50.166072 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2209 00:26:50.166170 ===================================
2210 00:26:50.166264 LPDDR4 DRAM CONFIGURATION
2211 00:26:50.166353 ===================================
2212 00:26:50.166441 EX_ROW_EN[0] = 0x0
2213 00:26:50.166529 EX_ROW_EN[1] = 0x0
2214 00:26:50.166617 LP4Y_EN = 0x0
2215 00:26:50.166705 WORK_FSP = 0x0
2216 00:26:50.166792 WL = 0x4
2217 00:26:50.166880 RL = 0x4
2218 00:26:50.166968 BL = 0x2
2219 00:26:50.167056 RPST = 0x0
2220 00:26:50.167144 RD_PRE = 0x0
2221 00:26:50.167231 WR_PRE = 0x1
2222 00:26:50.167319 WR_PST = 0x0
2223 00:26:50.167406 DBI_WR = 0x0
2224 00:26:50.167492 DBI_RD = 0x0
2225 00:26:50.167580 OTF = 0x1
2226 00:26:50.167667 ===================================
2227 00:26:50.167770 ===================================
2228 00:26:50.167903 ANA top config
2229 00:26:50.167995 ===================================
2230 00:26:50.168084 DLL_ASYNC_EN = 0
2231 00:26:50.168174 ALL_SLAVE_EN = 0
2232 00:26:50.168262 NEW_RANK_MODE = 1
2233 00:26:50.168352 DLL_IDLE_MODE = 1
2234 00:26:50.168440 LP45_APHY_COMB_EN = 1
2235 00:26:50.168529 TX_ODT_DIS = 1
2236 00:26:50.168617 NEW_8X_MODE = 1
2237 00:26:50.168705 ===================================
2238 00:26:50.168793 ===================================
2239 00:26:50.168882 data_rate = 2400
2240 00:26:50.168970 CKR = 1
2241 00:26:50.169058 DQ_P2S_RATIO = 8
2242 00:26:50.169145 ===================================
2243 00:26:50.169234 CA_P2S_RATIO = 8
2244 00:26:50.169321 DQ_CA_OPEN = 0
2245 00:26:50.169408 DQ_SEMI_OPEN = 0
2246 00:26:50.169494 CA_SEMI_OPEN = 0
2247 00:26:50.169582 CA_FULL_RATE = 0
2248 00:26:50.169670 DQ_CKDIV4_EN = 0
2249 00:26:50.169758 CA_CKDIV4_EN = 0
2250 00:26:50.169845 CA_PREDIV_EN = 0
2251 00:26:50.169932 PH8_DLY = 17
2252 00:26:50.170020 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2253 00:26:50.170109 DQ_AAMCK_DIV = 4
2254 00:26:50.170222 CA_AAMCK_DIV = 4
2255 00:26:50.170300 CA_ADMCK_DIV = 4
2256 00:26:50.170377 DQ_TRACK_CA_EN = 0
2257 00:26:50.170453 CA_PICK = 1200
2258 00:26:50.170530 CA_MCKIO = 1200
2259 00:26:50.170607 MCKIO_SEMI = 0
2260 00:26:50.170699 PLL_FREQ = 2366
2261 00:26:50.170777 DQ_UI_PI_RATIO = 32
2262 00:26:50.170854 CA_UI_PI_RATIO = 0
2263 00:26:50.170931 ===================================
2264 00:26:50.171008 ===================================
2265 00:26:50.171086 memory_type:LPDDR4
2266 00:26:50.171161 GP_NUM : 10
2267 00:26:50.171238 SRAM_EN : 1
2268 00:26:50.171315 MD32_EN : 0
2269 00:26:50.171391 ===================================
2270 00:26:50.171468 [ANA_INIT] >>>>>>>>>>>>>>
2271 00:26:50.171544 <<<<<< [CONFIGURE PHASE]: ANA_TX
2272 00:26:50.171622 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2273 00:26:50.171699 ===================================
2274 00:26:50.171776 data_rate = 2400,PCW = 0X5b00
2275 00:26:50.171852 ===================================
2276 00:26:50.171929 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2277 00:26:50.172007 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2278 00:26:50.172083 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2279 00:26:50.172161 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2280 00:26:50.172239 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2281 00:26:50.172529 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2282 00:26:50.172616 [ANA_INIT] flow start
2283 00:26:50.172715 [ANA_INIT] PLL >>>>>>>>
2284 00:26:50.172830 [ANA_INIT] PLL <<<<<<<<
2285 00:26:50.172929 [ANA_INIT] MIDPI >>>>>>>>
2286 00:26:50.173008 [ANA_INIT] MIDPI <<<<<<<<
2287 00:26:50.173087 [ANA_INIT] DLL >>>>>>>>
2288 00:26:50.173165 [ANA_INIT] DLL <<<<<<<<
2289 00:26:50.173242 [ANA_INIT] flow end
2290 00:26:50.173320 ============ LP4 DIFF to SE enter ============
2291 00:26:50.173398 ============ LP4 DIFF to SE exit ============
2292 00:26:50.173476 [ANA_INIT] <<<<<<<<<<<<<
2293 00:26:50.173553 [Flow] Enable top DCM control >>>>>
2294 00:26:50.173630 [Flow] Enable top DCM control <<<<<
2295 00:26:50.173707 Enable DLL master slave shuffle
2296 00:26:50.173783 ==============================================================
2297 00:26:50.173861 Gating Mode config
2298 00:26:50.173938 ==============================================================
2299 00:26:50.174014 Config description:
2300 00:26:50.174091 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2301 00:26:50.174184 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2302 00:26:50.174266 SELPH_MODE 0: By rank 1: By Phase
2303 00:26:50.174344 ==============================================================
2304 00:26:50.174422 GAT_TRACK_EN = 1
2305 00:26:50.174500 RX_GATING_MODE = 2
2306 00:26:50.174577 RX_GATING_TRACK_MODE = 2
2307 00:26:50.174653 SELPH_MODE = 1
2308 00:26:50.174730 PICG_EARLY_EN = 1
2309 00:26:50.174807 VALID_LAT_VALUE = 1
2310 00:26:50.174885 ==============================================================
2311 00:26:50.174962 Enter into Gating configuration >>>>
2312 00:26:50.175039 Exit from Gating configuration <<<<
2313 00:26:50.175116 Enter into DVFS_PRE_config >>>>>
2314 00:26:50.175223 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2315 00:26:50.175330 Exit from DVFS_PRE_config <<<<<
2316 00:26:50.175402 Enter into PICG configuration >>>>
2317 00:26:50.175472 Exit from PICG configuration <<<<
2318 00:26:50.175540 [RX_INPUT] configuration >>>>>
2319 00:26:50.175609 [RX_INPUT] configuration <<<<<
2320 00:26:50.175677 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2321 00:26:50.175747 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2322 00:26:50.175816 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2323 00:26:50.175886 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2324 00:26:50.175955 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2325 00:26:50.176024 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2326 00:26:50.176092 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2327 00:26:50.176161 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2328 00:26:50.176230 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2329 00:26:50.176299 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2330 00:26:50.176366 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2331 00:26:50.176435 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2332 00:26:50.176504 ===================================
2333 00:26:50.176573 LPDDR4 DRAM CONFIGURATION
2334 00:26:50.176640 ===================================
2335 00:26:50.176708 EX_ROW_EN[0] = 0x0
2336 00:26:50.176776 EX_ROW_EN[1] = 0x0
2337 00:26:50.176844 LP4Y_EN = 0x0
2338 00:26:50.176912 WORK_FSP = 0x0
2339 00:26:50.176979 WL = 0x4
2340 00:26:50.177048 RL = 0x4
2341 00:26:50.177116 BL = 0x2
2342 00:26:50.177183 RPST = 0x0
2343 00:26:50.177251 RD_PRE = 0x0
2344 00:26:50.177319 WR_PRE = 0x1
2345 00:26:50.177386 WR_PST = 0x0
2346 00:26:50.177454 DBI_WR = 0x0
2347 00:26:50.177521 DBI_RD = 0x0
2348 00:26:50.177589 OTF = 0x1
2349 00:26:50.177658 ===================================
2350 00:26:50.177726 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2351 00:26:50.177794 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2352 00:26:50.177863 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2353 00:26:50.177931 ===================================
2354 00:26:50.177999 LPDDR4 DRAM CONFIGURATION
2355 00:26:50.178067 ===================================
2356 00:26:50.178135 EX_ROW_EN[0] = 0x10
2357 00:26:50.178216 EX_ROW_EN[1] = 0x0
2358 00:26:50.178286 LP4Y_EN = 0x0
2359 00:26:50.178354 WORK_FSP = 0x0
2360 00:26:50.178422 WL = 0x4
2361 00:26:50.178491 RL = 0x4
2362 00:26:50.178558 BL = 0x2
2363 00:26:50.178626 RPST = 0x0
2364 00:26:50.178693 RD_PRE = 0x0
2365 00:26:50.178761 WR_PRE = 0x1
2366 00:26:50.178828 WR_PST = 0x0
2367 00:26:50.178894 DBI_WR = 0x0
2368 00:26:50.178961 DBI_RD = 0x0
2369 00:26:50.179028 OTF = 0x1
2370 00:26:50.179096 ===================================
2371 00:26:50.179163 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2372 00:26:50.179232 ==
2373 00:26:50.179300 Dram Type= 6, Freq= 0, CH_0, rank 0
2374 00:26:50.179368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2375 00:26:50.179435 ==
2376 00:26:50.179503 [Duty_Offset_Calibration]
2377 00:26:50.179570 B0:1 B1:-1 CA:0
2378 00:26:50.179637
2379 00:26:50.179704 [DutyScan_Calibration_Flow] k_type=0
2380 00:26:50.179771
2381 00:26:50.179838 ==CLK 0==
2382 00:26:50.179905 Final CLK duty delay cell = 0
2383 00:26:50.179973 [0] MAX Duty = 5094%(X100), DQS PI = 16
2384 00:26:50.180040 [0] MIN Duty = 4875%(X100), DQS PI = 8
2385 00:26:50.180108 [0] AVG Duty = 4984%(X100)
2386 00:26:50.180175
2387 00:26:50.180252 CH0 CLK Duty spec in!! Max-Min= 219%
2388 00:26:50.180313 [DutyScan_Calibration_Flow] ====Done====
2389 00:26:50.180374
2390 00:26:50.180434 [DutyScan_Calibration_Flow] k_type=1
2391 00:26:50.180495
2392 00:26:50.180554 ==DQS 0 ==
2393 00:26:50.180614 Final DQS duty delay cell = -4
2394 00:26:50.180675 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2395 00:26:50.180736 [-4] MIN Duty = 4875%(X100), DQS PI = 54
2396 00:26:50.180796 [-4] AVG Duty = 4968%(X100)
2397 00:26:50.180857
2398 00:26:50.180917 ==DQS 1 ==
2399 00:26:50.180977 Final DQS duty delay cell = 0
2400 00:26:50.181038 [0] MAX Duty = 5124%(X100), DQS PI = 4
2401 00:26:50.181299 [0] MIN Duty = 5000%(X100), DQS PI = 22
2402 00:26:50.181371 [0] AVG Duty = 5062%(X100)
2403 00:26:50.181433
2404 00:26:50.181496 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2405 00:26:50.181558
2406 00:26:50.181619 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2407 00:26:50.181680 [DutyScan_Calibration_Flow] ====Done====
2408 00:26:50.181741
2409 00:26:50.181801 [DutyScan_Calibration_Flow] k_type=3
2410 00:26:50.181862
2411 00:26:50.181923 ==DQM 0 ==
2412 00:26:50.181983 Final DQM duty delay cell = 0
2413 00:26:50.182045 [0] MAX Duty = 5062%(X100), DQS PI = 18
2414 00:26:50.182106 [0] MIN Duty = 4875%(X100), DQS PI = 6
2415 00:26:50.182176 [0] AVG Duty = 4968%(X100)
2416 00:26:50.182240
2417 00:26:50.182301 ==DQM 1 ==
2418 00:26:50.182369 Final DQM duty delay cell = 4
2419 00:26:50.182433 [4] MAX Duty = 5187%(X100), DQS PI = 32
2420 00:26:50.182495 [4] MIN Duty = 5000%(X100), DQS PI = 22
2421 00:26:50.182556 [4] AVG Duty = 5093%(X100)
2422 00:26:50.182617
2423 00:26:50.182676 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2424 00:26:50.182738
2425 00:26:50.182798 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2426 00:26:50.182858 [DutyScan_Calibration_Flow] ====Done====
2427 00:26:50.182920
2428 00:26:50.182980 [DutyScan_Calibration_Flow] k_type=2
2429 00:26:50.183041
2430 00:26:50.183101 ==DQ 0 ==
2431 00:26:50.183162 Final DQ duty delay cell = -4
2432 00:26:50.183222 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2433 00:26:50.183284 [-4] MIN Duty = 4875%(X100), DQS PI = 50
2434 00:26:50.183345 [-4] AVG Duty = 4953%(X100)
2435 00:26:50.183406
2436 00:26:50.183466 ==DQ 1 ==
2437 00:26:50.183527 Final DQ duty delay cell = -4
2438 00:26:50.183589 [-4] MAX Duty = 4969%(X100), DQS PI = 52
2439 00:26:50.183650 [-4] MIN Duty = 4876%(X100), DQS PI = 14
2440 00:26:50.183711 [-4] AVG Duty = 4922%(X100)
2441 00:26:50.183771
2442 00:26:50.183831 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2443 00:26:50.183892
2444 00:26:50.183952 CH0 DQ 1 Duty spec in!! Max-Min= 93%
2445 00:26:50.184013 [DutyScan_Calibration_Flow] ====Done====
2446 00:26:50.184074 ==
2447 00:26:50.184136 Dram Type= 6, Freq= 0, CH_1, rank 0
2448 00:26:50.184197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2449 00:26:50.184258 ==
2450 00:26:50.184319 [Duty_Offset_Calibration]
2451 00:26:50.184379 B0:-1 B1:1 CA:1
2452 00:26:50.184439
2453 00:26:50.184500 [DutyScan_Calibration_Flow] k_type=0
2454 00:26:50.184560
2455 00:26:50.184647 ==CLK 0==
2456 00:26:50.184756 Final CLK duty delay cell = 0
2457 00:26:50.184852 [0] MAX Duty = 5156%(X100), DQS PI = 22
2458 00:26:50.184917 [0] MIN Duty = 4969%(X100), DQS PI = 60
2459 00:26:50.184979 [0] AVG Duty = 5062%(X100)
2460 00:26:50.185041
2461 00:26:50.185102 CH1 CLK Duty spec in!! Max-Min= 187%
2462 00:26:50.185163 [DutyScan_Calibration_Flow] ====Done====
2463 00:26:50.185236
2464 00:26:50.185291 [DutyScan_Calibration_Flow] k_type=1
2465 00:26:50.185347
2466 00:26:50.185402 ==DQS 0 ==
2467 00:26:50.185456 Final DQS duty delay cell = 0
2468 00:26:50.185512 [0] MAX Duty = 5125%(X100), DQS PI = 50
2469 00:26:50.185567 [0] MIN Duty = 4875%(X100), DQS PI = 8
2470 00:26:50.185622 [0] AVG Duty = 5000%(X100)
2471 00:26:50.185676
2472 00:26:50.185730 ==DQS 1 ==
2473 00:26:50.185786 Final DQS duty delay cell = 0
2474 00:26:50.185841 [0] MAX Duty = 5062%(X100), DQS PI = 10
2475 00:26:50.185896 [0] MIN Duty = 4969%(X100), DQS PI = 56
2476 00:26:50.185951 [0] AVG Duty = 5015%(X100)
2477 00:26:50.186006
2478 00:26:50.186060 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2479 00:26:50.186115
2480 00:26:50.186175 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2481 00:26:50.186233 [DutyScan_Calibration_Flow] ====Done====
2482 00:26:50.186288
2483 00:26:50.186343 [DutyScan_Calibration_Flow] k_type=3
2484 00:26:50.186397
2485 00:26:50.186452 ==DQM 0 ==
2486 00:26:50.186507 Final DQM duty delay cell = -4
2487 00:26:50.186563 [-4] MAX Duty = 5031%(X100), DQS PI = 18
2488 00:26:50.186618 [-4] MIN Duty = 4844%(X100), DQS PI = 6
2489 00:26:50.186673 [-4] AVG Duty = 4937%(X100)
2490 00:26:50.186728
2491 00:26:50.186783 ==DQM 1 ==
2492 00:26:50.186838 Final DQM duty delay cell = 0
2493 00:26:50.186893 [0] MAX Duty = 5187%(X100), DQS PI = 8
2494 00:26:50.186949 [0] MIN Duty = 4969%(X100), DQS PI = 28
2495 00:26:50.187004 [0] AVG Duty = 5078%(X100)
2496 00:26:50.187060
2497 00:26:50.187115 CH1 DQM 0 Duty spec in!! Max-Min= 187%
2498 00:26:50.187170
2499 00:26:50.187224 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2500 00:26:50.187279 [DutyScan_Calibration_Flow] ====Done====
2501 00:26:50.187334
2502 00:26:50.187388 [DutyScan_Calibration_Flow] k_type=2
2503 00:26:50.187443
2504 00:26:50.187498 ==DQ 0 ==
2505 00:26:50.187553 Final DQ duty delay cell = 0
2506 00:26:50.187608 [0] MAX Duty = 5187%(X100), DQS PI = 30
2507 00:26:50.187663 [0] MIN Duty = 4907%(X100), DQS PI = 6
2508 00:26:50.187718 [0] AVG Duty = 5047%(X100)
2509 00:26:50.187773
2510 00:26:50.187828 ==DQ 1 ==
2511 00:26:50.187883 Final DQ duty delay cell = 0
2512 00:26:50.187938 [0] MAX Duty = 5124%(X100), DQS PI = 10
2513 00:26:50.187993 [0] MIN Duty = 4969%(X100), DQS PI = 0
2514 00:26:50.188048 [0] AVG Duty = 5046%(X100)
2515 00:26:50.188103
2516 00:26:50.188158 CH1 DQ 0 Duty spec in!! Max-Min= 280%
2517 00:26:50.188214
2518 00:26:50.188268 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2519 00:26:50.188323 [DutyScan_Calibration_Flow] ====Done====
2520 00:26:50.188379 nWR fixed to 30
2521 00:26:50.188434 [ModeRegInit_LP4] CH0 RK0
2522 00:26:50.188489 [ModeRegInit_LP4] CH0 RK1
2523 00:26:50.188544 [ModeRegInit_LP4] CH1 RK0
2524 00:26:50.188599 [ModeRegInit_LP4] CH1 RK1
2525 00:26:50.188654 match AC timing 7
2526 00:26:50.188708 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2527 00:26:50.188766 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2528 00:26:50.188825 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2529 00:26:50.188917 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2530 00:26:50.188976 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2531 00:26:50.189033 ==
2532 00:26:50.189088 Dram Type= 6, Freq= 0, CH_0, rank 0
2533 00:26:50.189144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2534 00:26:50.189200 ==
2535 00:26:50.189256 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2536 00:26:50.189312 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2537 00:26:50.189368 [CA 0] Center 39 (9~70) winsize 62
2538 00:26:50.189423 [CA 1] Center 39 (9~70) winsize 62
2539 00:26:50.189478 [CA 2] Center 35 (5~66) winsize 62
2540 00:26:50.189534 [CA 3] Center 35 (5~65) winsize 61
2541 00:26:50.189589 [CA 4] Center 33 (3~64) winsize 62
2542 00:26:50.189644 [CA 5] Center 33 (4~63) winsize 60
2543 00:26:50.189699
2544 00:26:50.189754 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2545 00:26:50.189809
2546 00:26:50.189864 [CATrainingPosCal] consider 1 rank data
2547 00:26:50.189920 u2DelayCellTimex100 = 270/100 ps
2548 00:26:50.189975 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2549 00:26:50.190030 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2550 00:26:50.190085 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2551 00:26:50.190340 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2552 00:26:50.190400 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2553 00:26:50.190455 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2554 00:26:50.190509
2555 00:26:50.190562 CA PerBit enable=1, Macro0, CA PI delay=33
2556 00:26:50.190615
2557 00:26:50.190669 [CBTSetCACLKResult] CA Dly = 33
2558 00:26:50.190722 CS Dly: 8 (0~39)
2559 00:26:50.190775 ==
2560 00:26:50.190828 Dram Type= 6, Freq= 0, CH_0, rank 1
2561 00:26:50.190881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2562 00:26:50.190934 ==
2563 00:26:50.190986 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2564 00:26:50.191039 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2565 00:26:50.191096 [CA 0] Center 39 (9~70) winsize 62
2566 00:26:50.191186 [CA 1] Center 39 (9~70) winsize 62
2567 00:26:50.191242 [CA 2] Center 35 (5~66) winsize 62
2568 00:26:50.191296 [CA 3] Center 34 (4~65) winsize 62
2569 00:26:50.191348 [CA 4] Center 33 (3~64) winsize 62
2570 00:26:50.191402 [CA 5] Center 33 (3~63) winsize 61
2571 00:26:50.191455
2572 00:26:50.191508 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2573 00:26:50.191560
2574 00:26:50.191612 [CATrainingPosCal] consider 2 rank data
2575 00:26:50.191664 u2DelayCellTimex100 = 270/100 ps
2576 00:26:50.191717 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2577 00:26:50.191770 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2578 00:26:50.191822 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2579 00:26:50.191875 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2580 00:26:50.191927 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2581 00:26:50.191980 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2582 00:26:50.192032
2583 00:26:50.192084 CA PerBit enable=1, Macro0, CA PI delay=33
2584 00:26:50.192137
2585 00:26:50.192189 [CBTSetCACLKResult] CA Dly = 33
2586 00:26:50.192241 CS Dly: 9 (0~41)
2587 00:26:50.192293
2588 00:26:50.192345 ----->DramcWriteLeveling(PI) begin...
2589 00:26:50.192399 ==
2590 00:26:50.192451 Dram Type= 6, Freq= 0, CH_0, rank 0
2591 00:26:50.192504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2592 00:26:50.192557 ==
2593 00:26:50.192609 Write leveling (Byte 0): 32 => 32
2594 00:26:50.192662 Write leveling (Byte 1): 29 => 29
2595 00:26:50.192719 DramcWriteLeveling(PI) end<-----
2596 00:26:50.192774
2597 00:26:50.192826 ==
2598 00:26:50.192879 Dram Type= 6, Freq= 0, CH_0, rank 0
2599 00:26:50.192931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2600 00:26:50.192984 ==
2601 00:26:50.193036 [Gating] SW mode calibration
2602 00:26:50.193089 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2603 00:26:50.193142 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2604 00:26:50.193196 0 15 0 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
2605 00:26:50.193249 0 15 4 | B1->B0 | 2322 3434 | 1 1 | (0 0) (1 1)
2606 00:26:50.193302 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2607 00:26:50.193355 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2608 00:26:50.193408 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2609 00:26:50.193461 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2610 00:26:50.193514 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2611 00:26:50.193567 0 15 28 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
2612 00:26:50.193620 1 0 0 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
2613 00:26:50.193673 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2614 00:26:50.193726 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2615 00:26:50.193779 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2616 00:26:50.193832 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2617 00:26:50.193885 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2618 00:26:50.193937 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2619 00:26:50.193989 1 0 28 | B1->B0 | 2323 3737 | 0 1 | (0 0) (0 0)
2620 00:26:50.194042 1 1 0 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
2621 00:26:50.194095 1 1 4 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
2622 00:26:50.194148 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2623 00:26:50.194246 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2624 00:26:50.194300 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2625 00:26:50.194353 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2626 00:26:50.194406 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2627 00:26:50.194458 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2628 00:26:50.194511 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2629 00:26:50.194564 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2630 00:26:50.194617 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2631 00:26:50.194669 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2632 00:26:50.194722 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2633 00:26:50.194775 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2634 00:26:50.194827 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2635 00:26:50.194880 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2636 00:26:50.194933 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2637 00:26:50.194986 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2638 00:26:50.195038 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2639 00:26:50.195091 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2640 00:26:50.195144 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2641 00:26:50.195196 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2642 00:26:50.195250 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2643 00:26:50.195303 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2644 00:26:50.195355 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2645 00:26:50.195408 Total UI for P1: 0, mck2ui 16
2646 00:26:50.195461 best dqsien dly found for B0: ( 1, 3, 28)
2647 00:26:50.195515 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2648 00:26:50.195568 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2649 00:26:50.195620 Total UI for P1: 0, mck2ui 16
2650 00:26:50.195673 best dqsien dly found for B1: ( 1, 4, 2)
2651 00:26:50.195726 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2652 00:26:50.195779 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2653 00:26:50.195832
2654 00:26:50.195884 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2655 00:26:50.196128 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2656 00:26:50.196188 [Gating] SW calibration Done
2657 00:26:50.196242 ==
2658 00:26:50.196295 Dram Type= 6, Freq= 0, CH_0, rank 0
2659 00:26:50.196355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2660 00:26:50.196454 ==
2661 00:26:50.196569 RX Vref Scan: 0
2662 00:26:50.196640
2663 00:26:50.196695 RX Vref 0 -> 0, step: 1
2664 00:26:50.196749
2665 00:26:50.196802 RX Delay -40 -> 252, step: 8
2666 00:26:50.196855 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2667 00:26:50.196914 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2668 00:26:50.196973 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2669 00:26:50.197026 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2670 00:26:50.197079 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2671 00:26:50.197132 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2672 00:26:50.197184 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2673 00:26:50.197237 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2674 00:26:50.197290 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2675 00:26:50.197343 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2676 00:26:50.197395 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2677 00:26:50.197448 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2678 00:26:50.197500 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2679 00:26:50.197553 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2680 00:26:50.197606 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2681 00:26:50.197658 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2682 00:26:50.197710 ==
2683 00:26:50.197762 Dram Type= 6, Freq= 0, CH_0, rank 0
2684 00:26:50.197815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2685 00:26:50.197868 ==
2686 00:26:50.197921 DQS Delay:
2687 00:26:50.197974 DQS0 = 0, DQS1 = 0
2688 00:26:50.198026 DQM Delay:
2689 00:26:50.198078 DQM0 = 119, DQM1 = 107
2690 00:26:50.198131 DQ Delay:
2691 00:26:50.198216 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2692 00:26:50.198285 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2693 00:26:50.198338 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
2694 00:26:50.198391 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2695 00:26:50.198444
2696 00:26:50.198496
2697 00:26:50.198548 ==
2698 00:26:50.198600 Dram Type= 6, Freq= 0, CH_0, rank 0
2699 00:26:50.198653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2700 00:26:50.198706 ==
2701 00:26:50.198759
2702 00:26:50.198810
2703 00:26:50.198862 TX Vref Scan disable
2704 00:26:50.198914 == TX Byte 0 ==
2705 00:26:50.198967 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2706 00:26:50.199019 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2707 00:26:50.199072 == TX Byte 1 ==
2708 00:26:50.199124 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2709 00:26:50.199177 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2710 00:26:50.199229 ==
2711 00:26:50.199281 Dram Type= 6, Freq= 0, CH_0, rank 0
2712 00:26:50.199334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2713 00:26:50.199387 ==
2714 00:26:50.199439 TX Vref=22, minBit 0, minWin=26, winSum=418
2715 00:26:50.199492 TX Vref=24, minBit 1, minWin=25, winSum=421
2716 00:26:50.199545 TX Vref=26, minBit 1, minWin=26, winSum=426
2717 00:26:50.199598 TX Vref=28, minBit 10, minWin=25, winSum=430
2718 00:26:50.199650 TX Vref=30, minBit 5, minWin=26, winSum=433
2719 00:26:50.199703 TX Vref=32, minBit 5, minWin=26, winSum=429
2720 00:26:50.199756 [TxChooseVref] Worse bit 5, Min win 26, Win sum 433, Final Vref 30
2721 00:26:50.199810
2722 00:26:50.199862 Final TX Range 1 Vref 30
2723 00:26:50.199915
2724 00:26:50.199967 ==
2725 00:26:50.200019 Dram Type= 6, Freq= 0, CH_0, rank 0
2726 00:26:50.200072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2727 00:26:50.200124 ==
2728 00:26:50.200176
2729 00:26:50.200229
2730 00:26:50.200281 TX Vref Scan disable
2731 00:26:50.200333 == TX Byte 0 ==
2732 00:26:50.200386 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2733 00:26:50.200439 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2734 00:26:50.200492 == TX Byte 1 ==
2735 00:26:50.200543 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2736 00:26:50.200597 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2737 00:26:50.200650
2738 00:26:50.200704 [DATLAT]
2739 00:26:50.200760 Freq=1200, CH0 RK0
2740 00:26:50.200813
2741 00:26:50.200865 DATLAT Default: 0xd
2742 00:26:50.200918 0, 0xFFFF, sum = 0
2743 00:26:50.200971 1, 0xFFFF, sum = 0
2744 00:26:50.201025 2, 0xFFFF, sum = 0
2745 00:26:50.201078 3, 0xFFFF, sum = 0
2746 00:26:50.201132 4, 0xFFFF, sum = 0
2747 00:26:50.201185 5, 0xFFFF, sum = 0
2748 00:26:50.201238 6, 0xFFFF, sum = 0
2749 00:26:50.201291 7, 0xFFFF, sum = 0
2750 00:26:50.201344 8, 0xFFFF, sum = 0
2751 00:26:50.201397 9, 0xFFFF, sum = 0
2752 00:26:50.201450 10, 0xFFFF, sum = 0
2753 00:26:50.201503 11, 0xFFFF, sum = 0
2754 00:26:50.201556 12, 0x0, sum = 1
2755 00:26:50.201609 13, 0x0, sum = 2
2756 00:26:50.201662 14, 0x0, sum = 3
2757 00:26:50.201715 15, 0x0, sum = 4
2758 00:26:50.201768 best_step = 13
2759 00:26:50.201820
2760 00:26:50.201872 ==
2761 00:26:50.201923 Dram Type= 6, Freq= 0, CH_0, rank 0
2762 00:26:50.201975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2763 00:26:50.202028 ==
2764 00:26:50.202080 RX Vref Scan: 1
2765 00:26:50.202133
2766 00:26:50.202219 Set Vref Range= 32 -> 127
2767 00:26:50.202286
2768 00:26:50.202338 RX Vref 32 -> 127, step: 1
2769 00:26:50.202391
2770 00:26:50.202442 RX Delay -21 -> 252, step: 4
2771 00:26:50.202495
2772 00:26:50.202547 Set Vref, RX VrefLevel [Byte0]: 32
2773 00:26:50.202600 [Byte1]: 32
2774 00:26:50.202652
2775 00:26:50.202704 Set Vref, RX VrefLevel [Byte0]: 33
2776 00:26:50.202757 [Byte1]: 33
2777 00:26:50.202809
2778 00:26:50.202861 Set Vref, RX VrefLevel [Byte0]: 34
2779 00:26:50.202913 [Byte1]: 34
2780 00:26:50.202965
2781 00:26:50.203017 Set Vref, RX VrefLevel [Byte0]: 35
2782 00:26:50.203069 [Byte1]: 35
2783 00:26:50.203121
2784 00:26:50.203173 Set Vref, RX VrefLevel [Byte0]: 36
2785 00:26:50.203226 [Byte1]: 36
2786 00:26:50.203278
2787 00:26:50.203329 Set Vref, RX VrefLevel [Byte0]: 37
2788 00:26:50.203381 [Byte1]: 37
2789 00:26:50.203434
2790 00:26:50.203485 Set Vref, RX VrefLevel [Byte0]: 38
2791 00:26:50.203537 [Byte1]: 38
2792 00:26:50.203590
2793 00:26:50.203642 Set Vref, RX VrefLevel [Byte0]: 39
2794 00:26:50.203694 [Byte1]: 39
2795 00:26:50.203746
2796 00:26:50.203798 Set Vref, RX VrefLevel [Byte0]: 40
2797 00:26:50.203850 [Byte1]: 40
2798 00:26:50.203902
2799 00:26:50.203953 Set Vref, RX VrefLevel [Byte0]: 41
2800 00:26:50.204005 [Byte1]: 41
2801 00:26:50.204058
2802 00:26:50.204110 Set Vref, RX VrefLevel [Byte0]: 42
2803 00:26:50.204162 [Byte1]: 42
2804 00:26:50.204214
2805 00:26:50.204266 Set Vref, RX VrefLevel [Byte0]: 43
2806 00:26:50.204319 [Byte1]: 43
2807 00:26:50.204371
2808 00:26:50.204424 Set Vref, RX VrefLevel [Byte0]: 44
2809 00:26:50.204476 [Byte1]: 44
2810 00:26:50.204528
2811 00:26:50.204779 Set Vref, RX VrefLevel [Byte0]: 45
2812 00:26:50.204875 [Byte1]: 45
2813 00:26:50.204935
2814 00:26:50.204990 Set Vref, RX VrefLevel [Byte0]: 46
2815 00:26:50.205044 [Byte1]: 46
2816 00:26:50.205098
2817 00:26:50.205151 Set Vref, RX VrefLevel [Byte0]: 47
2818 00:26:50.205205 [Byte1]: 47
2819 00:26:50.205257
2820 00:26:50.205310 Set Vref, RX VrefLevel [Byte0]: 48
2821 00:26:50.205364 [Byte1]: 48
2822 00:26:50.205416
2823 00:26:50.205469 Set Vref, RX VrefLevel [Byte0]: 49
2824 00:26:50.205522 [Byte1]: 49
2825 00:26:50.205575
2826 00:26:50.205627 Set Vref, RX VrefLevel [Byte0]: 50
2827 00:26:50.205680 [Byte1]: 50
2828 00:26:50.205732
2829 00:26:50.205784 Set Vref, RX VrefLevel [Byte0]: 51
2830 00:26:50.205837 [Byte1]: 51
2831 00:26:50.205893
2832 00:26:50.205946 Set Vref, RX VrefLevel [Byte0]: 52
2833 00:26:50.205999 [Byte1]: 52
2834 00:26:50.206052
2835 00:26:50.206104 Set Vref, RX VrefLevel [Byte0]: 53
2836 00:26:50.206157 [Byte1]: 53
2837 00:26:50.206257
2838 00:26:50.206309 Set Vref, RX VrefLevel [Byte0]: 54
2839 00:26:50.206362 [Byte1]: 54
2840 00:26:50.206415
2841 00:26:50.206467 Set Vref, RX VrefLevel [Byte0]: 55
2842 00:26:50.206520 [Byte1]: 55
2843 00:26:50.206573
2844 00:26:50.206625 Set Vref, RX VrefLevel [Byte0]: 56
2845 00:26:50.206678 [Byte1]: 56
2846 00:26:50.206752
2847 00:26:50.206806 Set Vref, RX VrefLevel [Byte0]: 57
2848 00:26:50.206860 [Byte1]: 57
2849 00:26:50.206913
2850 00:26:50.206965 Set Vref, RX VrefLevel [Byte0]: 58
2851 00:26:50.207019 [Byte1]: 58
2852 00:26:50.207073
2853 00:26:50.207125 Set Vref, RX VrefLevel [Byte0]: 59
2854 00:26:50.207178 [Byte1]: 59
2855 00:26:50.207230
2856 00:26:50.207282 Set Vref, RX VrefLevel [Byte0]: 60
2857 00:26:50.207335 [Byte1]: 60
2858 00:26:50.207387
2859 00:26:50.207439 Set Vref, RX VrefLevel [Byte0]: 61
2860 00:26:50.207491 [Byte1]: 61
2861 00:26:50.207544
2862 00:26:50.207596 Set Vref, RX VrefLevel [Byte0]: 62
2863 00:26:50.207648 [Byte1]: 62
2864 00:26:50.207700
2865 00:26:50.207753 Set Vref, RX VrefLevel [Byte0]: 63
2866 00:26:50.207806 [Byte1]: 63
2867 00:26:50.207858
2868 00:26:50.207910 Set Vref, RX VrefLevel [Byte0]: 64
2869 00:26:50.207963 [Byte1]: 64
2870 00:26:50.208016
2871 00:26:50.208068 Set Vref, RX VrefLevel [Byte0]: 65
2872 00:26:50.208122 [Byte1]: 65
2873 00:26:50.208174
2874 00:26:50.208226 Set Vref, RX VrefLevel [Byte0]: 66
2875 00:26:50.208279 [Byte1]: 66
2876 00:26:50.208332
2877 00:26:50.208384 Set Vref, RX VrefLevel [Byte0]: 67
2878 00:26:50.208436 [Byte1]: 67
2879 00:26:50.208489
2880 00:26:50.208542 Set Vref, RX VrefLevel [Byte0]: 68
2881 00:26:50.208595 [Byte1]: 68
2882 00:26:50.208648
2883 00:26:50.208700 Set Vref, RX VrefLevel [Byte0]: 69
2884 00:26:50.208758 [Byte1]: 69
2885 00:26:50.208812
2886 00:26:50.208864 Set Vref, RX VrefLevel [Byte0]: 70
2887 00:26:50.208916 [Byte1]: 70
2888 00:26:50.208968
2889 00:26:50.209020 Set Vref, RX VrefLevel [Byte0]: 71
2890 00:26:50.209073 [Byte1]: 71
2891 00:26:50.209125
2892 00:26:50.209177 Set Vref, RX VrefLevel [Byte0]: 72
2893 00:26:50.209236 [Byte1]: 72
2894 00:26:50.209289
2895 00:26:50.209377 Set Vref, RX VrefLevel [Byte0]: 73
2896 00:26:50.209436 [Byte1]: 73
2897 00:26:50.209491
2898 00:26:50.209544 Set Vref, RX VrefLevel [Byte0]: 74
2899 00:26:50.209597 [Byte1]: 74
2900 00:26:50.209650
2901 00:26:50.209703 Set Vref, RX VrefLevel [Byte0]: 75
2902 00:26:50.209755 [Byte1]: 75
2903 00:26:50.209808
2904 00:26:50.209861 Set Vref, RX VrefLevel [Byte0]: 76
2905 00:26:50.209913 [Byte1]: 76
2906 00:26:50.209966
2907 00:26:50.210019 Set Vref, RX VrefLevel [Byte0]: 77
2908 00:26:50.210072 [Byte1]: 77
2909 00:26:50.210125
2910 00:26:50.210184 Set Vref, RX VrefLevel [Byte0]: 78
2911 00:26:50.210269 [Byte1]: 78
2912 00:26:50.210321
2913 00:26:50.210374 Set Vref, RX VrefLevel [Byte0]: 79
2914 00:26:50.210427 [Byte1]: 79
2915 00:26:50.210479
2916 00:26:50.210531 Final RX Vref Byte 0 = 58 to rank0
2917 00:26:50.210584 Final RX Vref Byte 1 = 58 to rank0
2918 00:26:50.210637 Final RX Vref Byte 0 = 58 to rank1
2919 00:26:50.210690 Final RX Vref Byte 1 = 58 to rank1==
2920 00:26:50.210742 Dram Type= 6, Freq= 0, CH_0, rank 0
2921 00:26:50.210796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2922 00:26:50.210849 ==
2923 00:26:50.210901 DQS Delay:
2924 00:26:50.210954 DQS0 = 0, DQS1 = 0
2925 00:26:50.211006 DQM Delay:
2926 00:26:50.211059 DQM0 = 118, DQM1 = 108
2927 00:26:50.211111 DQ Delay:
2928 00:26:50.211164 DQ0 =116, DQ1 =120, DQ2 =116, DQ3 =114
2929 00:26:50.211217 DQ4 =120, DQ5 =110, DQ6 =126, DQ7 =126
2930 00:26:50.211270 DQ8 =96, DQ9 =94, DQ10 =112, DQ11 =104
2931 00:26:50.211322 DQ12 =114, DQ13 =112, DQ14 =122, DQ15 =114
2932 00:26:50.211375
2933 00:26:50.211427
2934 00:26:50.211479 [DQSOSCAuto] RK0, (LSB)MR18= 0x10fb, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 403 ps
2935 00:26:50.211533 CH0 RK0: MR19=403, MR18=10FB
2936 00:26:50.211586 CH0_RK0: MR19=0x403, MR18=0x10FB, DQSOSC=403, MR23=63, INC=40, DEC=26
2937 00:26:50.211639
2938 00:26:50.211691 ----->DramcWriteLeveling(PI) begin...
2939 00:26:50.211744 ==
2940 00:26:50.211797 Dram Type= 6, Freq= 0, CH_0, rank 1
2941 00:26:50.211849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2942 00:26:50.211902 ==
2943 00:26:50.211955 Write leveling (Byte 0): 33 => 33
2944 00:26:50.212007 Write leveling (Byte 1): 30 => 30
2945 00:26:50.212060 DramcWriteLeveling(PI) end<-----
2946 00:26:50.212112
2947 00:26:50.212163 ==
2948 00:26:50.212216 Dram Type= 6, Freq= 0, CH_0, rank 1
2949 00:26:50.212268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2950 00:26:50.212322 ==
2951 00:26:50.212375 [Gating] SW mode calibration
2952 00:26:50.212427 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2953 00:26:50.212480 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2954 00:26:50.212533 0 15 0 | B1->B0 | 2323 3232 | 1 1 | (0 0) (0 0)
2955 00:26:50.212586 0 15 4 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
2956 00:26:50.212639 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2957 00:26:50.212692 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2958 00:26:50.212777 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2959 00:26:50.213047 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2960 00:26:50.213111 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2961 00:26:50.213166 0 15 28 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
2962 00:26:50.213220 1 0 0 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
2963 00:26:50.213274 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2964 00:26:50.213327 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2965 00:26:50.213381 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2966 00:26:50.213434 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2967 00:26:50.213486 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2968 00:26:50.213539 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2969 00:26:50.213593 1 0 28 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
2970 00:26:50.213645 1 1 0 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
2971 00:26:50.213698 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2972 00:26:50.213752 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2973 00:26:50.213804 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2974 00:26:50.213857 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2975 00:26:50.213910 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2976 00:26:50.213962 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2977 00:26:50.214015 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2978 00:26:50.214067 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2979 00:26:50.214120 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2980 00:26:50.214204 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2981 00:26:50.214273 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2982 00:26:50.214325 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2983 00:26:50.214378 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2984 00:26:50.214431 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2985 00:26:50.214484 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2986 00:26:50.214536 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2987 00:26:50.214589 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2988 00:26:50.214642 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2989 00:26:50.214694 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2990 00:26:50.214747 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2991 00:26:50.214799 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2992 00:26:50.214852 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2993 00:26:50.214905 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2994 00:26:50.214957 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2995 00:26:50.215010 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2996 00:26:50.215062 Total UI for P1: 0, mck2ui 16
2997 00:26:50.215115 best dqsien dly found for B0: ( 1, 3, 28)
2998 00:26:50.215168 Total UI for P1: 0, mck2ui 16
2999 00:26:50.215220 best dqsien dly found for B1: ( 1, 4, 0)
3000 00:26:50.215273 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3001 00:26:50.215326 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
3002 00:26:50.215378
3003 00:26:50.215431 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3004 00:26:50.215483 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
3005 00:26:50.215536 [Gating] SW calibration Done
3006 00:26:50.533557 ==
3007 00:26:50.534065 Dram Type= 6, Freq= 0, CH_0, rank 1
3008 00:26:50.534526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3009 00:26:50.535145 ==
3010 00:26:50.535687 RX Vref Scan: 0
3011 00:26:50.536274
3012 00:26:50.536803 RX Vref 0 -> 0, step: 1
3013 00:26:50.537429
3014 00:26:50.537886 RX Delay -40 -> 252, step: 8
3015 00:26:50.538236 iDelay=200, Bit 0, Center 115 (48 ~ 183) 136
3016 00:26:50.538549 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
3017 00:26:50.538845 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
3018 00:26:50.539132 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3019 00:26:50.539416 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3020 00:26:50.539695 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
3021 00:26:50.539973 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3022 00:26:50.540250 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
3023 00:26:50.540528 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3024 00:26:50.540805 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3025 00:26:50.541083 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3026 00:26:50.541357 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3027 00:26:50.541632 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3028 00:26:50.541909 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3029 00:26:50.542415 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3030 00:26:50.542966 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3031 00:26:50.543284 ==
3032 00:26:50.543573 Dram Type= 6, Freq= 0, CH_0, rank 1
3033 00:26:50.543855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3034 00:26:50.544135 ==
3035 00:26:50.544525 DQS Delay:
3036 00:26:50.544818 DQS0 = 0, DQS1 = 0
3037 00:26:50.545098 DQM Delay:
3038 00:26:50.545371 DQM0 = 118, DQM1 = 108
3039 00:26:50.545645 DQ Delay:
3040 00:26:50.545919 DQ0 =115, DQ1 =119, DQ2 =111, DQ3 =115
3041 00:26:50.546226 DQ4 =119, DQ5 =111, DQ6 =127, DQ7 =127
3042 00:26:50.546511 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
3043 00:26:50.546788 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
3044 00:26:50.547062
3045 00:26:50.547336
3046 00:26:50.547611 ==
3047 00:26:50.548150 Dram Type= 6, Freq= 0, CH_0, rank 1
3048 00:26:50.548664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3049 00:26:50.549078 ==
3050 00:26:50.549642
3051 00:26:50.550003
3052 00:26:50.550379 TX Vref Scan disable
3053 00:26:50.550681 == TX Byte 0 ==
3054 00:26:50.550966 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3055 00:26:50.551252 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3056 00:26:50.551535 == TX Byte 1 ==
3057 00:26:50.551911 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3058 00:26:50.552218 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3059 00:26:50.552815 ==
3060 00:26:50.553267 Dram Type= 6, Freq= 0, CH_0, rank 1
3061 00:26:50.553570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3062 00:26:50.553860 ==
3063 00:26:50.554137 TX Vref=22, minBit 0, minWin=26, winSum=420
3064 00:26:50.554462 TX Vref=24, minBit 5, minWin=25, winSum=423
3065 00:26:50.554828 TX Vref=26, minBit 1, minWin=26, winSum=429
3066 00:26:50.555123 TX Vref=28, minBit 1, minWin=26, winSum=435
3067 00:26:50.555890 TX Vref=30, minBit 4, minWin=27, winSum=440
3068 00:26:50.556380 TX Vref=32, minBit 10, minWin=26, winSum=435
3069 00:26:50.556607 [TxChooseVref] Worse bit 4, Min win 27, Win sum 440, Final Vref 30
3070 00:26:50.556821
3071 00:26:50.557028 Final TX Range 1 Vref 30
3072 00:26:50.557234
3073 00:26:50.557433 ==
3074 00:26:50.557668 Dram Type= 6, Freq= 0, CH_0, rank 1
3075 00:26:50.557886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3076 00:26:50.558088 ==
3077 00:26:50.558322
3078 00:26:50.558522
3079 00:26:50.558718 TX Vref Scan disable
3080 00:26:50.558916 == TX Byte 0 ==
3081 00:26:50.559113 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3082 00:26:50.559313 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3083 00:26:50.559508 == TX Byte 1 ==
3084 00:26:50.559741 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3085 00:26:50.560190 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3086 00:26:50.560498
3087 00:26:50.560705 [DATLAT]
3088 00:26:50.560906 Freq=1200, CH0 RK1
3089 00:26:50.561105
3090 00:26:50.561284 DATLAT Default: 0xd
3091 00:26:50.561432 0, 0xFFFF, sum = 0
3092 00:26:50.561582 1, 0xFFFF, sum = 0
3093 00:26:50.561734 2, 0xFFFF, sum = 0
3094 00:26:50.561884 3, 0xFFFF, sum = 0
3095 00:26:50.562032 4, 0xFFFF, sum = 0
3096 00:26:50.562200 5, 0xFFFF, sum = 0
3097 00:26:50.562354 6, 0xFFFF, sum = 0
3098 00:26:50.562502 7, 0xFFFF, sum = 0
3099 00:26:50.562650 8, 0xFFFF, sum = 0
3100 00:26:50.562808 9, 0xFFFF, sum = 0
3101 00:26:50.562960 10, 0xFFFF, sum = 0
3102 00:26:50.563108 11, 0xFFFF, sum = 0
3103 00:26:50.563257 12, 0x0, sum = 1
3104 00:26:50.563407 13, 0x0, sum = 2
3105 00:26:50.563556 14, 0x0, sum = 3
3106 00:26:50.563704 15, 0x0, sum = 4
3107 00:26:50.563854 best_step = 13
3108 00:26:50.563999
3109 00:26:50.564144 ==
3110 00:26:50.564291 Dram Type= 6, Freq= 0, CH_0, rank 1
3111 00:26:50.564438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3112 00:26:50.564586 ==
3113 00:26:50.564730 RX Vref Scan: 0
3114 00:26:50.564876
3115 00:26:50.565023 RX Vref 0 -> 0, step: 1
3116 00:26:50.565170
3117 00:26:50.565368 RX Delay -21 -> 252, step: 4
3118 00:26:50.565617 iDelay=199, Bit 0, Center 114 (51 ~ 178) 128
3119 00:26:50.565868 iDelay=199, Bit 1, Center 118 (47 ~ 190) 144
3120 00:26:50.566133 iDelay=199, Bit 2, Center 110 (43 ~ 178) 136
3121 00:26:50.566315 iDelay=199, Bit 3, Center 114 (43 ~ 186) 144
3122 00:26:50.566439 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3123 00:26:50.566560 iDelay=199, Bit 5, Center 110 (43 ~ 178) 136
3124 00:26:50.566680 iDelay=199, Bit 6, Center 126 (55 ~ 198) 144
3125 00:26:50.566801 iDelay=199, Bit 7, Center 124 (55 ~ 194) 140
3126 00:26:50.566920 iDelay=199, Bit 8, Center 98 (31 ~ 166) 136
3127 00:26:50.567040 iDelay=199, Bit 9, Center 94 (27 ~ 162) 136
3128 00:26:50.567159 iDelay=199, Bit 10, Center 112 (47 ~ 178) 132
3129 00:26:50.567278 iDelay=199, Bit 11, Center 102 (35 ~ 170) 136
3130 00:26:50.567397 iDelay=199, Bit 12, Center 116 (51 ~ 182) 132
3131 00:26:50.567516 iDelay=199, Bit 13, Center 114 (51 ~ 178) 128
3132 00:26:50.567635 iDelay=199, Bit 14, Center 122 (59 ~ 186) 128
3133 00:26:50.567753 iDelay=199, Bit 15, Center 116 (51 ~ 182) 132
3134 00:26:50.567872 ==
3135 00:26:50.567990 Dram Type= 6, Freq= 0, CH_0, rank 1
3136 00:26:50.568109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3137 00:26:50.568228 ==
3138 00:26:50.568346 DQS Delay:
3139 00:26:50.568464 DQS0 = 0, DQS1 = 0
3140 00:26:50.568581 DQM Delay:
3141 00:26:50.568699 DQM0 = 116, DQM1 = 109
3142 00:26:50.568816 DQ Delay:
3143 00:26:50.568933 DQ0 =114, DQ1 =118, DQ2 =110, DQ3 =114
3144 00:26:50.569051 DQ4 =116, DQ5 =110, DQ6 =126, DQ7 =124
3145 00:26:50.569169 DQ8 =98, DQ9 =94, DQ10 =112, DQ11 =102
3146 00:26:50.569288 DQ12 =116, DQ13 =114, DQ14 =122, DQ15 =116
3147 00:26:50.569407
3148 00:26:50.569523
3149 00:26:50.569642 [DQSOSCAuto] RK1, (LSB)MR18= 0xfe9, (MSB)MR19= 0x403, tDQSOscB0 = 419 ps tDQSOscB1 = 404 ps
3150 00:26:50.569761 CH0 RK1: MR19=403, MR18=FE9
3151 00:26:50.569879 CH0_RK1: MR19=0x403, MR18=0xFE9, DQSOSC=404, MR23=63, INC=40, DEC=26
3152 00:26:50.569998 [RxdqsGatingPostProcess] freq 1200
3153 00:26:50.570117 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3154 00:26:50.570256 best DQS0 dly(2T, 0.5T) = (0, 11)
3155 00:26:50.570377 best DQS1 dly(2T, 0.5T) = (0, 12)
3156 00:26:50.570496 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3157 00:26:50.570615 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3158 00:26:50.570733 best DQS0 dly(2T, 0.5T) = (0, 11)
3159 00:26:50.570852 best DQS1 dly(2T, 0.5T) = (0, 12)
3160 00:26:50.570970 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3161 00:26:50.571089 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3162 00:26:50.571207 Pre-setting of DQS Precalculation
3163 00:26:50.571322 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3164 00:26:50.571422 ==
3165 00:26:50.571520 Dram Type= 6, Freq= 0, CH_1, rank 0
3166 00:26:50.571619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3167 00:26:50.571719 ==
3168 00:26:50.571817 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3169 00:26:50.571918 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3170 00:26:50.572017 [CA 0] Center 37 (8~67) winsize 60
3171 00:26:50.572115 [CA 1] Center 37 (7~68) winsize 62
3172 00:26:50.572213 [CA 2] Center 34 (4~65) winsize 62
3173 00:26:50.572311 [CA 3] Center 33 (3~64) winsize 62
3174 00:26:50.572410 [CA 4] Center 34 (4~64) winsize 61
3175 00:26:50.572508 [CA 5] Center 33 (3~64) winsize 62
3176 00:26:50.572607
3177 00:26:50.572704 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3178 00:26:50.572802
3179 00:26:50.572900 [CATrainingPosCal] consider 1 rank data
3180 00:26:50.573000 u2DelayCellTimex100 = 270/100 ps
3181 00:26:50.573098 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3182 00:26:50.573197 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3183 00:26:50.573296 CA2 delay=34 (4~65),Diff = 1 PI (4 cell)
3184 00:26:50.573394 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3185 00:26:50.573493 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3186 00:26:50.573590 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3187 00:26:50.573688
3188 00:26:50.573785 CA PerBit enable=1, Macro0, CA PI delay=33
3189 00:26:50.573884
3190 00:26:50.573981 [CBTSetCACLKResult] CA Dly = 33
3191 00:26:50.574079 CS Dly: 5 (0~36)
3192 00:26:50.574190 ==
3193 00:26:50.574292 Dram Type= 6, Freq= 0, CH_1, rank 1
3194 00:26:50.574392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3195 00:26:50.574492 ==
3196 00:26:50.574591 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3197 00:26:50.574691 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3198 00:26:50.574791 [CA 0] Center 37 (7~68) winsize 62
3199 00:26:50.574890 [CA 1] Center 38 (8~68) winsize 61
3200 00:26:50.574990 [CA 2] Center 34 (4~65) winsize 62
3201 00:26:50.575328 [CA 3] Center 33 (3~64) winsize 62
3202 00:26:50.575441 [CA 4] Center 34 (3~65) winsize 63
3203 00:26:50.575565 [CA 5] Center 33 (3~64) winsize 62
3204 00:26:50.575716
3205 00:26:50.575820 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3206 00:26:50.575937
3207 00:26:50.576049 [CATrainingPosCal] consider 2 rank data
3208 00:26:50.576151 u2DelayCellTimex100 = 270/100 ps
3209 00:26:50.576261 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3210 00:26:50.576347 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3211 00:26:50.576433 CA2 delay=34 (4~65),Diff = 1 PI (4 cell)
3212 00:26:50.576518 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3213 00:26:50.576603 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3214 00:26:50.576688 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3215 00:26:50.576773
3216 00:26:50.576858 CA PerBit enable=1, Macro0, CA PI delay=33
3217 00:26:50.576944
3218 00:26:50.577028 [CBTSetCACLKResult] CA Dly = 33
3219 00:26:50.577113 CS Dly: 7 (0~40)
3220 00:26:50.577197
3221 00:26:50.577282 ----->DramcWriteLeveling(PI) begin...
3222 00:26:50.577368 ==
3223 00:26:50.577473 Dram Type= 6, Freq= 0, CH_1, rank 0
3224 00:26:50.577562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3225 00:26:50.577648 ==
3226 00:26:50.577733 Write leveling (Byte 0): 25 => 25
3227 00:26:50.577820 Write leveling (Byte 1): 27 => 27
3228 00:26:50.577905 DramcWriteLeveling(PI) end<-----
3229 00:26:50.577991
3230 00:26:50.578075 ==
3231 00:26:50.578174 Dram Type= 6, Freq= 0, CH_1, rank 0
3232 00:26:50.578271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3233 00:26:50.578359 ==
3234 00:26:50.578444 [Gating] SW mode calibration
3235 00:26:50.578529 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3236 00:26:50.578615 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3237 00:26:50.578701 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3238 00:26:50.578787 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3239 00:26:50.578872 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3240 00:26:50.578957 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3241 00:26:50.579043 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3242 00:26:50.579128 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3243 00:26:50.579213 0 15 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
3244 00:26:50.579298 0 15 28 | B1->B0 | 2424 2323 | 0 0 | (1 0) (1 0)
3245 00:26:50.579386 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3246 00:26:50.579485 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3247 00:26:50.579574 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3248 00:26:50.579660 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3249 00:26:50.579746 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3250 00:26:50.579831 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3251 00:26:50.579915 1 0 24 | B1->B0 | 2424 3737 | 0 1 | (1 1) (0 0)
3252 00:26:50.580000 1 0 28 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3253 00:26:50.580085 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3254 00:26:50.580170 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3255 00:26:50.580254 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3256 00:26:50.580340 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3257 00:26:50.580424 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3258 00:26:50.580510 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3259 00:26:50.580595 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3260 00:26:50.580680 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3261 00:26:50.580764 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3262 00:26:50.580850 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3263 00:26:50.580934 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3264 00:26:50.581020 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3265 00:26:50.581104 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3266 00:26:50.581189 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3267 00:26:50.581276 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3268 00:26:50.581351 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3269 00:26:50.581424 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3270 00:26:50.581498 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3271 00:26:50.581572 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3272 00:26:50.581647 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3273 00:26:50.581721 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3274 00:26:50.581795 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3275 00:26:50.581869 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3276 00:26:50.581943 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3277 00:26:50.582016 Total UI for P1: 0, mck2ui 16
3278 00:26:50.582091 best dqsien dly found for B0: ( 1, 3, 22)
3279 00:26:50.582175 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3280 00:26:50.582255 Total UI for P1: 0, mck2ui 16
3281 00:26:50.582330 best dqsien dly found for B1: ( 1, 3, 28)
3282 00:26:50.582405 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3283 00:26:50.582480 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3284 00:26:50.582554
3285 00:26:50.582628 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3286 00:26:50.582703 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3287 00:26:50.582776 [Gating] SW calibration Done
3288 00:26:50.582851 ==
3289 00:26:50.582925 Dram Type= 6, Freq= 0, CH_1, rank 0
3290 00:26:50.582999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3291 00:26:50.583074 ==
3292 00:26:50.583149 RX Vref Scan: 0
3293 00:26:50.583222
3294 00:26:50.583296 RX Vref 0 -> 0, step: 1
3295 00:26:50.583399
3296 00:26:50.583477 RX Delay -40 -> 252, step: 8
3297 00:26:50.583552 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3298 00:26:50.583627 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3299 00:26:50.583703 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3300 00:26:50.583778 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3301 00:26:50.583851 iDelay=208, Bit 4, Center 111 (40 ~ 183) 144
3302 00:26:50.583926 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3303 00:26:50.584000 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3304 00:26:50.584074 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3305 00:26:50.584358 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3306 00:26:50.584441 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3307 00:26:50.584516 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3308 00:26:50.584592 iDelay=208, Bit 11, Center 95 (24 ~ 167) 144
3309 00:26:50.584667 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3310 00:26:50.584742 iDelay=208, Bit 13, Center 115 (40 ~ 191) 152
3311 00:26:50.584817 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3312 00:26:50.584891 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3313 00:26:50.584965 ==
3314 00:26:50.585040 Dram Type= 6, Freq= 0, CH_1, rank 0
3315 00:26:50.585114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3316 00:26:50.585189 ==
3317 00:26:50.585263 DQS Delay:
3318 00:26:50.585336 DQS0 = 0, DQS1 = 0
3319 00:26:50.585412 DQM Delay:
3320 00:26:50.585485 DQM0 = 117, DQM1 = 108
3321 00:26:50.585559 DQ Delay:
3322 00:26:50.585651 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =115
3323 00:26:50.585731 DQ4 =111, DQ5 =131, DQ6 =123, DQ7 =115
3324 00:26:50.585806 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =95
3325 00:26:50.585881 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =119
3326 00:26:50.585955
3327 00:26:50.586029
3328 00:26:50.586102 ==
3329 00:26:50.586189 Dram Type= 6, Freq= 0, CH_1, rank 0
3330 00:26:50.586276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3331 00:26:50.586343 ==
3332 00:26:50.586409
3333 00:26:50.586474
3334 00:26:50.586540 TX Vref Scan disable
3335 00:26:50.586606 == TX Byte 0 ==
3336 00:26:50.586672 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3337 00:26:50.586739 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3338 00:26:50.586805 == TX Byte 1 ==
3339 00:26:50.586871 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3340 00:26:50.586938 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3341 00:26:50.587005 ==
3342 00:26:50.587070 Dram Type= 6, Freq= 0, CH_1, rank 0
3343 00:26:50.587137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3344 00:26:50.587203 ==
3345 00:26:50.587270 TX Vref=22, minBit 10, minWin=24, winSum=415
3346 00:26:50.587336 TX Vref=24, minBit 9, minWin=25, winSum=418
3347 00:26:50.587402 TX Vref=26, minBit 9, minWin=25, winSum=430
3348 00:26:50.587468 TX Vref=28, minBit 9, minWin=25, winSum=431
3349 00:26:50.587533 TX Vref=30, minBit 9, minWin=25, winSum=425
3350 00:26:50.587599 TX Vref=32, minBit 9, minWin=25, winSum=424
3351 00:26:50.587665 [TxChooseVref] Worse bit 9, Min win 25, Win sum 431, Final Vref 28
3352 00:26:50.587731
3353 00:26:50.587797 Final TX Range 1 Vref 28
3354 00:26:50.587863
3355 00:26:50.587928 ==
3356 00:26:50.587994 Dram Type= 6, Freq= 0, CH_1, rank 0
3357 00:26:50.588059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3358 00:26:50.588126 ==
3359 00:26:50.588191
3360 00:26:50.588257
3361 00:26:50.588322 TX Vref Scan disable
3362 00:26:50.588387 == TX Byte 0 ==
3363 00:26:50.588453 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3364 00:26:50.588518 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3365 00:26:50.588584 == TX Byte 1 ==
3366 00:26:50.588648 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3367 00:26:50.588713 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3368 00:26:50.588778
3369 00:26:50.588843 [DATLAT]
3370 00:26:50.588908 Freq=1200, CH1 RK0
3371 00:26:50.588973
3372 00:26:50.589037 DATLAT Default: 0xd
3373 00:26:50.589102 0, 0xFFFF, sum = 0
3374 00:26:50.589169 1, 0xFFFF, sum = 0
3375 00:26:50.589236 2, 0xFFFF, sum = 0
3376 00:26:50.589302 3, 0xFFFF, sum = 0
3377 00:26:50.589402 4, 0xFFFF, sum = 0
3378 00:26:50.589518 5, 0xFFFF, sum = 0
3379 00:26:50.589621 6, 0xFFFF, sum = 0
3380 00:26:50.589692 7, 0xFFFF, sum = 0
3381 00:26:50.589761 8, 0xFFFF, sum = 0
3382 00:26:50.589828 9, 0xFFFF, sum = 0
3383 00:26:50.589899 10, 0xFFFF, sum = 0
3384 00:26:50.589967 11, 0xFFFF, sum = 0
3385 00:26:50.590034 12, 0x0, sum = 1
3386 00:26:50.590100 13, 0x0, sum = 2
3387 00:26:50.590178 14, 0x0, sum = 3
3388 00:26:50.590248 15, 0x0, sum = 4
3389 00:26:50.590314 best_step = 13
3390 00:26:50.590380
3391 00:26:50.590446 ==
3392 00:26:50.590513 Dram Type= 6, Freq= 0, CH_1, rank 0
3393 00:26:50.590580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3394 00:26:50.590646 ==
3395 00:26:50.590712 RX Vref Scan: 1
3396 00:26:50.590778
3397 00:26:50.590844 Set Vref Range= 32 -> 127
3398 00:26:50.590909
3399 00:26:50.590975 RX Vref 32 -> 127, step: 1
3400 00:26:50.591040
3401 00:26:50.591106 RX Delay -21 -> 252, step: 4
3402 00:26:50.591171
3403 00:26:50.591248 Set Vref, RX VrefLevel [Byte0]: 32
3404 00:26:50.591308 [Byte1]: 32
3405 00:26:50.591367
3406 00:26:50.591427 Set Vref, RX VrefLevel [Byte0]: 33
3407 00:26:50.591486 [Byte1]: 33
3408 00:26:50.591545
3409 00:26:50.591604 Set Vref, RX VrefLevel [Byte0]: 34
3410 00:26:50.591662 [Byte1]: 34
3411 00:26:50.591721
3412 00:26:50.591780 Set Vref, RX VrefLevel [Byte0]: 35
3413 00:26:50.591838 [Byte1]: 35
3414 00:26:50.591897
3415 00:26:50.591956 Set Vref, RX VrefLevel [Byte0]: 36
3416 00:26:50.592019 [Byte1]: 36
3417 00:26:50.592138
3418 00:26:50.592278 Set Vref, RX VrefLevel [Byte0]: 37
3419 00:26:50.592376 [Byte1]: 37
3420 00:26:50.592441
3421 00:26:50.592502 Set Vref, RX VrefLevel [Byte0]: 38
3422 00:26:50.592562 [Byte1]: 38
3423 00:26:50.592622
3424 00:26:50.592682 Set Vref, RX VrefLevel [Byte0]: 39
3425 00:26:50.592742 [Byte1]: 39
3426 00:26:50.592801
3427 00:26:50.592860 Set Vref, RX VrefLevel [Byte0]: 40
3428 00:26:50.592919 [Byte1]: 40
3429 00:26:50.592978
3430 00:26:50.593037 Set Vref, RX VrefLevel [Byte0]: 41
3431 00:26:50.593096 [Byte1]: 41
3432 00:26:50.593155
3433 00:26:50.593214 Set Vref, RX VrefLevel [Byte0]: 42
3434 00:26:50.593273 [Byte1]: 42
3435 00:26:50.593332
3436 00:26:50.593391 Set Vref, RX VrefLevel [Byte0]: 43
3437 00:26:50.593449 [Byte1]: 43
3438 00:26:50.593508
3439 00:26:50.593567 Set Vref, RX VrefLevel [Byte0]: 44
3440 00:26:50.593626 [Byte1]: 44
3441 00:26:50.593686
3442 00:26:50.593744 Set Vref, RX VrefLevel [Byte0]: 45
3443 00:26:50.593803 [Byte1]: 45
3444 00:26:50.593862
3445 00:26:50.593921 Set Vref, RX VrefLevel [Byte0]: 46
3446 00:26:50.593980 [Byte1]: 46
3447 00:26:50.594039
3448 00:26:50.594098 Set Vref, RX VrefLevel [Byte0]: 47
3449 00:26:50.594158 [Byte1]: 47
3450 00:26:50.594228
3451 00:26:50.594287 Set Vref, RX VrefLevel [Byte0]: 48
3452 00:26:50.594346 [Byte1]: 48
3453 00:26:50.594405
3454 00:26:50.594463 Set Vref, RX VrefLevel [Byte0]: 49
3455 00:26:50.594522 [Byte1]: 49
3456 00:26:50.594581
3457 00:26:50.594640 Set Vref, RX VrefLevel [Byte0]: 50
3458 00:26:50.594699 [Byte1]: 50
3459 00:26:50.594757
3460 00:26:50.594816 Set Vref, RX VrefLevel [Byte0]: 51
3461 00:26:50.594874 [Byte1]: 51
3462 00:26:50.594933
3463 00:26:50.595129 Set Vref, RX VrefLevel [Byte0]: 52
3464 00:26:50.595262 [Byte1]: 52
3465 00:26:50.595353
3466 00:26:50.595416 Set Vref, RX VrefLevel [Byte0]: 53
3467 00:26:50.595678 [Byte1]: 53
3468 00:26:50.595780
3469 00:26:50.595845 Set Vref, RX VrefLevel [Byte0]: 54
3470 00:26:50.595907 [Byte1]: 54
3471 00:26:50.595968
3472 00:26:50.596028 Set Vref, RX VrefLevel [Byte0]: 55
3473 00:26:50.596088 [Byte1]: 55
3474 00:26:50.596148
3475 00:26:50.596207 Set Vref, RX VrefLevel [Byte0]: 56
3476 00:26:50.596276 [Byte1]: 56
3477 00:26:50.596330
3478 00:26:50.596384 Set Vref, RX VrefLevel [Byte0]: 57
3479 00:26:50.596438 [Byte1]: 57
3480 00:26:50.596492
3481 00:26:50.596546 Set Vref, RX VrefLevel [Byte0]: 58
3482 00:26:50.596599 [Byte1]: 58
3483 00:26:50.596653
3484 00:26:50.596706 Set Vref, RX VrefLevel [Byte0]: 59
3485 00:26:50.596760 [Byte1]: 59
3486 00:26:50.596814
3487 00:26:50.596867 Set Vref, RX VrefLevel [Byte0]: 60
3488 00:26:50.596921 [Byte1]: 60
3489 00:26:50.596975
3490 00:26:50.597029 Set Vref, RX VrefLevel [Byte0]: 61
3491 00:26:50.597084 [Byte1]: 61
3492 00:26:50.597138
3493 00:26:50.597191 Set Vref, RX VrefLevel [Byte0]: 62
3494 00:26:50.597245 [Byte1]: 62
3495 00:26:50.597298
3496 00:26:50.597352 Set Vref, RX VrefLevel [Byte0]: 63
3497 00:26:50.597434 [Byte1]: 63
3498 00:26:50.597603
3499 00:26:50.597701 Set Vref, RX VrefLevel [Byte0]: 64
3500 00:26:50.597761 [Byte1]: 64
3501 00:26:50.597817
3502 00:26:50.597871 Set Vref, RX VrefLevel [Byte0]: 65
3503 00:26:50.597925 [Byte1]: 65
3504 00:26:50.597980
3505 00:26:50.598034 Set Vref, RX VrefLevel [Byte0]: 66
3506 00:26:50.598089 [Byte1]: 66
3507 00:26:50.598142
3508 00:26:50.598219 Set Vref, RX VrefLevel [Byte0]: 67
3509 00:26:50.598316 [Byte1]: 67
3510 00:26:50.598455
3511 00:26:50.598550 Set Vref, RX VrefLevel [Byte0]: 68
3512 00:26:50.598609 [Byte1]: 68
3513 00:26:50.598665
3514 00:26:50.598720 Final RX Vref Byte 0 = 48 to rank0
3515 00:26:50.598775 Final RX Vref Byte 1 = 52 to rank0
3516 00:26:50.598830 Final RX Vref Byte 0 = 48 to rank1
3517 00:26:50.598885 Final RX Vref Byte 1 = 52 to rank1==
3518 00:26:50.598940 Dram Type= 6, Freq= 0, CH_1, rank 0
3519 00:26:50.598994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3520 00:26:50.599048 ==
3521 00:26:50.599103 DQS Delay:
3522 00:26:50.599156 DQS0 = 0, DQS1 = 0
3523 00:26:50.599210 DQM Delay:
3524 00:26:50.599264 DQM0 = 115, DQM1 = 110
3525 00:26:50.599318 DQ Delay:
3526 00:26:50.599371 DQ0 =118, DQ1 =110, DQ2 =108, DQ3 =112
3527 00:26:50.599425 DQ4 =114, DQ5 =126, DQ6 =126, DQ7 =112
3528 00:26:50.599479 DQ8 =98, DQ9 =102, DQ10 =112, DQ11 =98
3529 00:26:50.599533 DQ12 =116, DQ13 =116, DQ14 =120, DQ15 =118
3530 00:26:50.599587
3531 00:26:50.599657
3532 00:26:50.599712 [DQSOSCAuto] RK0, (LSB)MR18= 0x6f9, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 407 ps
3533 00:26:50.599769 CH1 RK0: MR19=403, MR18=6F9
3534 00:26:50.599824 CH1_RK0: MR19=0x403, MR18=0x6F9, DQSOSC=407, MR23=63, INC=39, DEC=26
3535 00:26:50.599878
3536 00:26:50.599932 ----->DramcWriteLeveling(PI) begin...
3537 00:26:50.599988 ==
3538 00:26:50.600042 Dram Type= 6, Freq= 0, CH_1, rank 1
3539 00:26:50.600097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3540 00:26:50.600151 ==
3541 00:26:50.600206 Write leveling (Byte 0): 24 => 24
3542 00:26:50.600260 Write leveling (Byte 1): 28 => 28
3543 00:26:50.600314 DramcWriteLeveling(PI) end<-----
3544 00:26:50.600367
3545 00:26:50.600421 ==
3546 00:26:50.600474 Dram Type= 6, Freq= 0, CH_1, rank 1
3547 00:26:50.600528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3548 00:26:50.600583 ==
3549 00:26:50.600636 [Gating] SW mode calibration
3550 00:26:50.600690 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3551 00:26:50.600745 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3552 00:26:50.600799 0 15 0 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
3553 00:26:50.600853 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3554 00:26:50.600907 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3555 00:26:50.600960 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3556 00:26:50.601014 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3557 00:26:50.601068 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3558 00:26:50.601122 0 15 24 | B1->B0 | 3333 3434 | 1 1 | (1 0) (1 0)
3559 00:26:50.601176 0 15 28 | B1->B0 | 2323 2525 | 0 0 | (1 0) (0 0)
3560 00:26:50.601241 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3561 00:26:50.601294 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3562 00:26:50.601346 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3563 00:26:50.601399 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3564 00:26:50.601452 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3565 00:26:50.601504 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3566 00:26:50.601557 1 0 24 | B1->B0 | 3b3b 2525 | 0 0 | (0 0) (0 0)
3567 00:26:50.601609 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3568 00:26:50.601662 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3569 00:26:50.601715 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3570 00:26:50.601768 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3571 00:26:50.601821 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3572 00:26:50.601874 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3573 00:26:50.601927 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3574 00:26:50.601979 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3575 00:26:50.602032 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3576 00:26:50.602085 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3577 00:26:50.602138 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3578 00:26:50.602229 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3579 00:26:50.602283 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3580 00:26:50.602336 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3581 00:26:50.602388 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3582 00:26:50.602441 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3583 00:26:50.602494 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3584 00:26:50.602547 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3585 00:26:50.602599 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3586 00:26:50.602844 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3587 00:26:50.602903 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3588 00:26:50.602958 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3589 00:26:50.603011 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3590 00:26:50.603064 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3591 00:26:50.603117 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3592 00:26:50.603170 Total UI for P1: 0, mck2ui 16
3593 00:26:50.603260 best dqsien dly found for B1: ( 1, 3, 24)
3594 00:26:50.603322 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3595 00:26:50.603376 Total UI for P1: 0, mck2ui 16
3596 00:26:50.603450 best dqsien dly found for B0: ( 1, 3, 26)
3597 00:26:50.603506 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3598 00:26:50.603560 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3599 00:26:50.603618
3600 00:26:50.603688 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3601 00:26:50.603777 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3602 00:26:50.603834 [Gating] SW calibration Done
3603 00:26:50.603889 ==
3604 00:26:50.603944 Dram Type= 6, Freq= 0, CH_1, rank 1
3605 00:26:50.603997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3606 00:26:50.604051 ==
3607 00:26:50.604104 RX Vref Scan: 0
3608 00:26:50.604157
3609 00:26:50.604209 RX Vref 0 -> 0, step: 1
3610 00:26:50.604275
3611 00:26:50.604329 RX Delay -40 -> 252, step: 8
3612 00:26:50.604454 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3613 00:26:50.604577 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3614 00:26:50.604658 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3615 00:26:50.604715 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3616 00:26:50.604769 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3617 00:26:50.604823 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3618 00:26:50.604876 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3619 00:26:50.604928 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3620 00:26:50.604981 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3621 00:26:50.605034 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3622 00:26:50.605087 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3623 00:26:50.605140 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3624 00:26:50.605192 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3625 00:26:50.605245 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3626 00:26:50.605298 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3627 00:26:50.605350 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3628 00:26:50.605402 ==
3629 00:26:50.605455 Dram Type= 6, Freq= 0, CH_1, rank 1
3630 00:26:50.605507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3631 00:26:50.605560 ==
3632 00:26:50.605613 DQS Delay:
3633 00:26:50.605708 DQS0 = 0, DQS1 = 0
3634 00:26:50.605845 DQM Delay:
3635 00:26:50.605945 DQM0 = 116, DQM1 = 110
3636 00:26:50.606030 DQ Delay:
3637 00:26:50.606113 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3638 00:26:50.606252 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =115
3639 00:26:50.606309 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3640 00:26:50.606364 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3641 00:26:50.606418
3642 00:26:50.606470
3643 00:26:50.606523 ==
3644 00:26:50.606576 Dram Type= 6, Freq= 0, CH_1, rank 1
3645 00:26:50.606630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3646 00:26:50.606682 ==
3647 00:26:50.606738
3648 00:26:50.606823
3649 00:26:50.606880 TX Vref Scan disable
3650 00:26:50.606934 == TX Byte 0 ==
3651 00:26:50.606996 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3652 00:26:50.607058 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3653 00:26:50.607111 == TX Byte 1 ==
3654 00:26:50.607164 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3655 00:26:50.607217 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3656 00:26:50.607269 ==
3657 00:26:50.607322 Dram Type= 6, Freq= 0, CH_1, rank 1
3658 00:26:50.607375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3659 00:26:50.607428 ==
3660 00:26:50.607481 TX Vref=22, minBit 9, minWin=25, winSum=425
3661 00:26:50.607534 TX Vref=24, minBit 9, minWin=25, winSum=429
3662 00:26:50.607587 TX Vref=26, minBit 9, minWin=26, winSum=436
3663 00:26:50.607639 TX Vref=28, minBit 9, minWin=26, winSum=436
3664 00:26:50.607692 TX Vref=30, minBit 9, minWin=26, winSum=435
3665 00:26:50.607744 TX Vref=32, minBit 9, minWin=26, winSum=436
3666 00:26:50.607797 [TxChooseVref] Worse bit 9, Min win 26, Win sum 436, Final Vref 26
3667 00:26:50.607849
3668 00:26:50.607901 Final TX Range 1 Vref 26
3669 00:26:50.607953
3670 00:26:50.608005 ==
3671 00:26:50.608076 Dram Type= 6, Freq= 0, CH_1, rank 1
3672 00:26:50.608130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3673 00:26:50.608183 ==
3674 00:26:50.608235
3675 00:26:50.608287
3676 00:26:50.608340 TX Vref Scan disable
3677 00:26:50.608392 == TX Byte 0 ==
3678 00:26:50.608445 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3679 00:26:50.608498 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3680 00:26:50.608550 == TX Byte 1 ==
3681 00:26:50.608603 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3682 00:26:50.608655 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3683 00:26:50.608708
3684 00:26:50.608759 [DATLAT]
3685 00:26:50.608812 Freq=1200, CH1 RK1
3686 00:26:50.608866
3687 00:26:50.608919 DATLAT Default: 0xd
3688 00:26:50.608971 0, 0xFFFF, sum = 0
3689 00:26:50.609026 1, 0xFFFF, sum = 0
3690 00:26:50.609090 2, 0xFFFF, sum = 0
3691 00:26:50.609145 3, 0xFFFF, sum = 0
3692 00:26:50.609199 4, 0xFFFF, sum = 0
3693 00:26:50.609252 5, 0xFFFF, sum = 0
3694 00:26:50.609306 6, 0xFFFF, sum = 0
3695 00:26:50.609358 7, 0xFFFF, sum = 0
3696 00:26:50.609412 8, 0xFFFF, sum = 0
3697 00:26:50.609464 9, 0xFFFF, sum = 0
3698 00:26:50.609517 10, 0xFFFF, sum = 0
3699 00:26:50.609571 11, 0xFFFF, sum = 0
3700 00:26:50.609624 12, 0x0, sum = 1
3701 00:26:50.609677 13, 0x0, sum = 2
3702 00:26:50.609730 14, 0x0, sum = 3
3703 00:26:50.609784 15, 0x0, sum = 4
3704 00:26:50.609837 best_step = 13
3705 00:26:50.609890
3706 00:26:50.609942 ==
3707 00:26:50.609994 Dram Type= 6, Freq= 0, CH_1, rank 1
3708 00:26:50.610047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3709 00:26:50.610100 ==
3710 00:26:50.610153 RX Vref Scan: 0
3711 00:26:50.610247
3712 00:26:50.610300 RX Vref 0 -> 0, step: 1
3713 00:26:50.610352
3714 00:26:50.610404 RX Delay -21 -> 252, step: 4
3715 00:26:50.610457 iDelay=199, Bit 0, Center 120 (55 ~ 186) 132
3716 00:26:50.610510 iDelay=199, Bit 1, Center 112 (47 ~ 178) 132
3717 00:26:50.610563 iDelay=199, Bit 2, Center 106 (43 ~ 170) 128
3718 00:26:50.610615 iDelay=199, Bit 3, Center 114 (51 ~ 178) 128
3719 00:26:50.610668 iDelay=199, Bit 4, Center 114 (47 ~ 182) 136
3720 00:26:50.610721 iDelay=199, Bit 5, Center 126 (59 ~ 194) 136
3721 00:26:50.610773 iDelay=199, Bit 6, Center 130 (63 ~ 198) 136
3722 00:26:50.610825 iDelay=199, Bit 7, Center 116 (51 ~ 182) 132
3723 00:26:50.610878 iDelay=199, Bit 8, Center 96 (31 ~ 162) 132
3724 00:26:50.611128 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3725 00:26:50.611187 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3726 00:26:50.611241 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3727 00:26:50.611295 iDelay=199, Bit 12, Center 118 (51 ~ 186) 136
3728 00:26:50.611348 iDelay=199, Bit 13, Center 118 (51 ~ 186) 136
3729 00:26:50.611402 iDelay=199, Bit 14, Center 116 (51 ~ 182) 132
3730 00:26:50.611454 iDelay=199, Bit 15, Center 118 (51 ~ 186) 136
3731 00:26:50.611506 ==
3732 00:26:50.611559 Dram Type= 6, Freq= 0, CH_1, rank 1
3733 00:26:50.611612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3734 00:26:50.611665 ==
3735 00:26:50.611717 DQS Delay:
3736 00:26:50.611770 DQS0 = 0, DQS1 = 0
3737 00:26:50.611822 DQM Delay:
3738 00:26:50.611875 DQM0 = 117, DQM1 = 109
3739 00:26:50.611927 DQ Delay:
3740 00:26:50.611979 DQ0 =120, DQ1 =112, DQ2 =106, DQ3 =114
3741 00:26:50.612032 DQ4 =114, DQ5 =126, DQ6 =130, DQ7 =116
3742 00:26:50.612084 DQ8 =96, DQ9 =100, DQ10 =110, DQ11 =100
3743 00:26:50.612138 DQ12 =118, DQ13 =118, DQ14 =116, DQ15 =118
3744 00:26:50.612190
3745 00:26:50.612242
3746 00:26:50.612294 [DQSOSCAuto] RK1, (LSB)MR18= 0xf2ed, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 415 ps
3747 00:26:50.612348 CH1 RK1: MR19=303, MR18=F2ED
3748 00:26:50.612401 CH1_RK1: MR19=0x303, MR18=0xF2ED, DQSOSC=415, MR23=63, INC=38, DEC=25
3749 00:26:50.612454 [RxdqsGatingPostProcess] freq 1200
3750 00:26:50.612506 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3751 00:26:50.612559 best DQS0 dly(2T, 0.5T) = (0, 11)
3752 00:26:50.612611 best DQS1 dly(2T, 0.5T) = (0, 11)
3753 00:26:50.612663 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3754 00:26:50.612715 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3755 00:26:50.612768 best DQS0 dly(2T, 0.5T) = (0, 11)
3756 00:26:50.612820 best DQS1 dly(2T, 0.5T) = (0, 11)
3757 00:26:50.612873 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3758 00:26:50.612925 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3759 00:26:50.612977 Pre-setting of DQS Precalculation
3760 00:26:50.613029 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3761 00:26:50.613082 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3762 00:26:50.613135 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3763 00:26:50.613188
3764 00:26:50.613240
3765 00:26:50.613293 [Calibration Summary] 2400 Mbps
3766 00:26:50.613345 CH 0, Rank 0
3767 00:26:50.613397 SW Impedance : PASS
3768 00:26:50.613449 DUTY Scan : NO K
3769 00:26:50.613501 ZQ Calibration : PASS
3770 00:26:50.613554 Jitter Meter : NO K
3771 00:26:50.613614 CBT Training : PASS
3772 00:26:50.613749 Write leveling : PASS
3773 00:26:50.613871 RX DQS gating : PASS
3774 00:26:50.613967 RX DQ/DQS(RDDQC) : PASS
3775 00:26:50.614051 TX DQ/DQS : PASS
3776 00:26:50.614135 RX DATLAT : PASS
3777 00:26:50.614209 RX DQ/DQS(Engine): PASS
3778 00:26:50.614264 TX OE : NO K
3779 00:26:50.614317 All Pass.
3780 00:26:50.614371
3781 00:26:50.614423 CH 0, Rank 1
3782 00:26:50.614476 SW Impedance : PASS
3783 00:26:50.614529 DUTY Scan : NO K
3784 00:26:50.614581 ZQ Calibration : PASS
3785 00:26:50.614634 Jitter Meter : NO K
3786 00:26:50.614686 CBT Training : PASS
3787 00:26:50.614738 Write leveling : PASS
3788 00:26:50.614791 RX DQS gating : PASS
3789 00:26:50.614844 RX DQ/DQS(RDDQC) : PASS
3790 00:26:50.614896 TX DQ/DQS : PASS
3791 00:26:50.614948 RX DATLAT : PASS
3792 00:26:50.615001 RX DQ/DQS(Engine): PASS
3793 00:26:50.615053 TX OE : NO K
3794 00:26:50.615105 All Pass.
3795 00:26:50.615158
3796 00:26:50.615210 CH 1, Rank 0
3797 00:26:50.615262 SW Impedance : PASS
3798 00:26:50.615314 DUTY Scan : NO K
3799 00:26:50.615366 ZQ Calibration : PASS
3800 00:26:50.615419 Jitter Meter : NO K
3801 00:26:50.615471 CBT Training : PASS
3802 00:26:50.615524 Write leveling : PASS
3803 00:26:50.615575 RX DQS gating : PASS
3804 00:26:50.615628 RX DQ/DQS(RDDQC) : PASS
3805 00:26:50.615680 TX DQ/DQS : PASS
3806 00:26:50.615732 RX DATLAT : PASS
3807 00:26:50.615783 RX DQ/DQS(Engine): PASS
3808 00:26:50.615835 TX OE : NO K
3809 00:26:50.615888 All Pass.
3810 00:26:50.615940
3811 00:26:50.615992 CH 1, Rank 1
3812 00:26:50.616044 SW Impedance : PASS
3813 00:26:50.616096 DUTY Scan : NO K
3814 00:26:50.616149 ZQ Calibration : PASS
3815 00:26:50.616201 Jitter Meter : NO K
3816 00:26:50.616253 CBT Training : PASS
3817 00:26:50.616305 Write leveling : PASS
3818 00:26:50.616357 RX DQS gating : PASS
3819 00:26:50.616409 RX DQ/DQS(RDDQC) : PASS
3820 00:26:50.616461 TX DQ/DQS : PASS
3821 00:26:50.616513 RX DATLAT : PASS
3822 00:26:50.616565 RX DQ/DQS(Engine): PASS
3823 00:26:50.616618 TX OE : NO K
3824 00:26:50.616670 All Pass.
3825 00:26:50.616722
3826 00:26:50.616774 DramC Write-DBI off
3827 00:26:50.616826 PER_BANK_REFRESH: Hybrid Mode
3828 00:26:50.616878 TX_TRACKING: ON
3829 00:26:50.616930 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3830 00:26:50.616983 [FAST_K] Save calibration result to emmc
3831 00:26:50.617036 dramc_set_vcore_voltage set vcore to 650000
3832 00:26:50.617088 Read voltage for 600, 5
3833 00:26:50.617141 Vio18 = 0
3834 00:26:50.617193 Vcore = 650000
3835 00:26:50.617245 Vdram = 0
3836 00:26:50.617298 Vddq = 0
3837 00:26:50.617349 Vmddr = 0
3838 00:26:50.617402 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3839 00:26:50.617454 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3840 00:26:50.617507 MEM_TYPE=3, freq_sel=19
3841 00:26:50.617560 sv_algorithm_assistance_LP4_1600
3842 00:26:50.617612 ============ PULL DRAM RESETB DOWN ============
3843 00:26:50.617665 ========== PULL DRAM RESETB DOWN end =========
3844 00:26:50.617718 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3845 00:26:50.617771 ===================================
3846 00:26:50.617824 LPDDR4 DRAM CONFIGURATION
3847 00:26:50.617876 ===================================
3848 00:26:50.617929 EX_ROW_EN[0] = 0x0
3849 00:26:50.617981 EX_ROW_EN[1] = 0x0
3850 00:26:50.618033 LP4Y_EN = 0x0
3851 00:26:50.618086 WORK_FSP = 0x0
3852 00:26:50.618141 WL = 0x2
3853 00:26:50.618205 RL = 0x2
3854 00:26:50.618259 BL = 0x2
3855 00:26:50.618311 RPST = 0x0
3856 00:26:50.618363 RD_PRE = 0x0
3857 00:26:50.618415 WR_PRE = 0x1
3858 00:26:50.618467 WR_PST = 0x0
3859 00:26:50.618519 DBI_WR = 0x0
3860 00:26:50.618571 DBI_RD = 0x0
3861 00:26:50.618623 OTF = 0x1
3862 00:26:50.618677 ===================================
3863 00:26:50.618729 ===================================
3864 00:26:50.618782 ANA top config
3865 00:26:50.618834 ===================================
3866 00:26:50.618886 DLL_ASYNC_EN = 0
3867 00:26:50.619129 ALL_SLAVE_EN = 1
3868 00:26:50.619189 NEW_RANK_MODE = 1
3869 00:26:50.619244 DLL_IDLE_MODE = 1
3870 00:26:50.619298 LP45_APHY_COMB_EN = 1
3871 00:26:50.619350 TX_ODT_DIS = 1
3872 00:26:50.619403 NEW_8X_MODE = 1
3873 00:26:50.619456 ===================================
3874 00:26:50.619509 ===================================
3875 00:26:50.619562 data_rate = 1200
3876 00:26:50.619615 CKR = 1
3877 00:26:50.619667 DQ_P2S_RATIO = 8
3878 00:26:50.619720 ===================================
3879 00:26:50.619773 CA_P2S_RATIO = 8
3880 00:26:50.619826 DQ_CA_OPEN = 0
3881 00:26:50.619878 DQ_SEMI_OPEN = 0
3882 00:26:50.619931 CA_SEMI_OPEN = 0
3883 00:26:50.619983 CA_FULL_RATE = 0
3884 00:26:50.620036 DQ_CKDIV4_EN = 1
3885 00:26:50.620088 CA_CKDIV4_EN = 1
3886 00:26:50.620140 CA_PREDIV_EN = 0
3887 00:26:50.620192 PH8_DLY = 0
3888 00:26:50.620245 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3889 00:26:50.620297 DQ_AAMCK_DIV = 4
3890 00:26:50.620349 CA_AAMCK_DIV = 4
3891 00:26:50.620402 CA_ADMCK_DIV = 4
3892 00:26:50.620454 DQ_TRACK_CA_EN = 0
3893 00:26:50.620506 CA_PICK = 600
3894 00:26:50.620558 CA_MCKIO = 600
3895 00:26:50.620610 MCKIO_SEMI = 0
3896 00:26:50.620663 PLL_FREQ = 2288
3897 00:26:50.620715 DQ_UI_PI_RATIO = 32
3898 00:26:50.620767 CA_UI_PI_RATIO = 0
3899 00:26:50.620820 ===================================
3900 00:26:50.620873 ===================================
3901 00:26:50.620935 memory_type:LPDDR4
3902 00:26:50.621018 GP_NUM : 10
3903 00:26:50.621073 SRAM_EN : 1
3904 00:26:50.621126 MD32_EN : 0
3905 00:26:50.621195 ===================================
3906 00:26:50.621252 [ANA_INIT] >>>>>>>>>>>>>>
3907 00:26:50.621305 <<<<<< [CONFIGURE PHASE]: ANA_TX
3908 00:26:50.621358 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3909 00:26:50.621411 ===================================
3910 00:26:50.621465 data_rate = 1200,PCW = 0X5800
3911 00:26:50.621517 ===================================
3912 00:26:50.621569 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3913 00:26:50.621623 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3914 00:26:50.621677 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3915 00:26:50.621730 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3916 00:26:50.621782 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3917 00:26:50.621835 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3918 00:26:50.621888 [ANA_INIT] flow start
3919 00:26:50.621940 [ANA_INIT] PLL >>>>>>>>
3920 00:26:50.621992 [ANA_INIT] PLL <<<<<<<<
3921 00:26:50.622045 [ANA_INIT] MIDPI >>>>>>>>
3922 00:26:50.622097 [ANA_INIT] MIDPI <<<<<<<<
3923 00:26:50.622149 [ANA_INIT] DLL >>>>>>>>
3924 00:26:50.622252 [ANA_INIT] flow end
3925 00:26:50.622305 ============ LP4 DIFF to SE enter ============
3926 00:26:50.622358 ============ LP4 DIFF to SE exit ============
3927 00:26:50.622411 [ANA_INIT] <<<<<<<<<<<<<
3928 00:26:50.622463 [Flow] Enable top DCM control >>>>>
3929 00:26:50.622516 [Flow] Enable top DCM control <<<<<
3930 00:26:50.622569 Enable DLL master slave shuffle
3931 00:26:50.622622 ==============================================================
3932 00:26:50.622675 Gating Mode config
3933 00:26:50.622728 ==============================================================
3934 00:26:50.622781 Config description:
3935 00:26:50.622833 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3936 00:26:50.622887 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3937 00:26:50.622940 SELPH_MODE 0: By rank 1: By Phase
3938 00:26:50.623003 ==============================================================
3939 00:26:50.623057 GAT_TRACK_EN = 1
3940 00:26:50.623110 RX_GATING_MODE = 2
3941 00:26:50.623163 RX_GATING_TRACK_MODE = 2
3942 00:26:50.623216 SELPH_MODE = 1
3943 00:26:50.623269 PICG_EARLY_EN = 1
3944 00:26:50.623322 VALID_LAT_VALUE = 1
3945 00:26:50.623375 ==============================================================
3946 00:26:50.623428 Enter into Gating configuration >>>>
3947 00:26:50.623548 Exit from Gating configuration <<<<
3948 00:26:50.623686 Enter into DVFS_PRE_config >>>>>
3949 00:26:50.623771 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3950 00:26:50.623829 Exit from DVFS_PRE_config <<<<<
3951 00:26:50.623884 Enter into PICG configuration >>>>
3952 00:26:50.623938 Exit from PICG configuration <<<<
3953 00:26:50.623991 [RX_INPUT] configuration >>>>>
3954 00:26:50.624044 [RX_INPUT] configuration <<<<<
3955 00:26:50.624097 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3956 00:26:50.624151 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3957 00:26:50.624204 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3958 00:26:50.624257 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3959 00:26:50.624310 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3960 00:26:50.624363 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3961 00:26:50.624416 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3962 00:26:50.624469 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3963 00:26:50.624522 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3964 00:26:50.624575 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3965 00:26:50.624628 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3966 00:26:50.624681 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3967 00:26:50.624733 ===================================
3968 00:26:50.624822 LPDDR4 DRAM CONFIGURATION
3969 00:26:50.625077 ===================================
3970 00:26:50.625164 EX_ROW_EN[0] = 0x0
3971 00:26:50.625222 EX_ROW_EN[1] = 0x0
3972 00:26:50.625276 LP4Y_EN = 0x0
3973 00:26:50.625330 WORK_FSP = 0x0
3974 00:26:50.625383 WL = 0x2
3975 00:26:50.625436 RL = 0x2
3976 00:26:50.625490 BL = 0x2
3977 00:26:50.625555 RPST = 0x0
3978 00:26:50.625611 RD_PRE = 0x0
3979 00:26:50.628510 WR_PRE = 0x1
3980 00:26:50.628577 WR_PST = 0x0
3981 00:26:50.631909 DBI_WR = 0x0
3982 00:26:50.632076 DBI_RD = 0x0
3983 00:26:50.635383 OTF = 0x1
3984 00:26:50.638508 ===================================
3985 00:26:50.642063 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3986 00:26:50.645319 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3987 00:26:50.651828 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3988 00:26:50.655640 ===================================
3989 00:26:50.658398 LPDDR4 DRAM CONFIGURATION
3990 00:26:50.658527 ===================================
3991 00:26:50.661538 EX_ROW_EN[0] = 0x10
3992 00:26:50.665299 EX_ROW_EN[1] = 0x0
3993 00:26:50.665453 LP4Y_EN = 0x0
3994 00:26:50.668580 WORK_FSP = 0x0
3995 00:26:50.668750 WL = 0x2
3996 00:26:50.671771 RL = 0x2
3997 00:26:50.671954 BL = 0x2
3998 00:26:50.674788 RPST = 0x0
3999 00:26:50.674889 RD_PRE = 0x0
4000 00:26:50.677985 WR_PRE = 0x1
4001 00:26:50.678087 WR_PST = 0x0
4002 00:26:50.681800 DBI_WR = 0x0
4003 00:26:50.681989 DBI_RD = 0x0
4004 00:26:50.758410 OTF = 0x1
4005 00:26:50.758941 ===================================
4006 00:26:50.759318 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4007 00:26:50.759666 nWR fixed to 30
4008 00:26:50.760007 [ModeRegInit_LP4] CH0 RK0
4009 00:26:50.760343 [ModeRegInit_LP4] CH0 RK1
4010 00:26:50.760802 [ModeRegInit_LP4] CH1 RK0
4011 00:26:50.761210 [ModeRegInit_LP4] CH1 RK1
4012 00:26:50.761514 match AC timing 17
4013 00:26:50.761804 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
4014 00:26:50.762092 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4015 00:26:50.762432 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
4016 00:26:50.762862 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
4017 00:26:50.763362 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
4018 00:26:50.763723 ==
4019 00:26:50.764022 Dram Type= 6, Freq= 0, CH_0, rank 0
4020 00:26:50.764315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4021 00:26:50.764602 ==
4022 00:26:50.764884 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4023 00:26:50.765166 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4024 00:26:50.765449 [CA 0] Center 36 (6~66) winsize 61
4025 00:26:50.765740 [CA 1] Center 36 (6~66) winsize 61
4026 00:26:50.766091 [CA 2] Center 34 (4~65) winsize 62
4027 00:26:50.766436 [CA 3] Center 34 (3~65) winsize 63
4028 00:26:50.767214 [CA 4] Center 34 (4~64) winsize 61
4029 00:26:50.770393 [CA 5] Center 33 (3~64) winsize 62
4030 00:26:50.770822
4031 00:26:50.773692 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4032 00:26:50.774139
4033 00:26:50.777086 [CATrainingPosCal] consider 1 rank data
4034 00:26:50.780495 u2DelayCellTimex100 = 270/100 ps
4035 00:26:50.783569 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4036 00:26:50.786942 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4037 00:26:50.790736 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4038 00:26:50.797102 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4039 00:26:50.800725 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4040 00:26:50.804080 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4041 00:26:50.804504
4042 00:26:50.806983 CA PerBit enable=1, Macro0, CA PI delay=33
4043 00:26:50.807291
4044 00:26:50.810382 [CBTSetCACLKResult] CA Dly = 33
4045 00:26:50.810687 CS Dly: 5 (0~36)
4046 00:26:50.810928 ==
4047 00:26:50.813306 Dram Type= 6, Freq= 0, CH_0, rank 1
4048 00:26:50.820602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4049 00:26:50.821104 ==
4050 00:26:50.823563 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4051 00:26:50.830284 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4052 00:26:50.833663 [CA 0] Center 35 (5~66) winsize 62
4053 00:26:50.837040 [CA 1] Center 36 (6~66) winsize 61
4054 00:26:50.840171 [CA 2] Center 34 (3~65) winsize 63
4055 00:26:50.843660 [CA 3] Center 33 (3~64) winsize 62
4056 00:26:50.847094 [CA 4] Center 33 (3~64) winsize 62
4057 00:26:50.850569 [CA 5] Center 33 (3~64) winsize 62
4058 00:26:50.851136
4059 00:26:50.853710 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4060 00:26:50.854212
4061 00:26:50.856852 [CATrainingPosCal] consider 2 rank data
4062 00:26:50.860282 u2DelayCellTimex100 = 270/100 ps
4063 00:26:50.863504 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4064 00:26:50.870116 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4065 00:26:50.873482 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4066 00:26:50.876336 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4067 00:26:50.879968 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4068 00:26:50.883516 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4069 00:26:50.883992
4070 00:26:50.886394 CA PerBit enable=1, Macro0, CA PI delay=33
4071 00:26:50.886866
4072 00:26:50.890028 [CBTSetCACLKResult] CA Dly = 33
4073 00:26:50.893592 CS Dly: 5 (0~36)
4074 00:26:50.894065
4075 00:26:50.896502 ----->DramcWriteLeveling(PI) begin...
4076 00:26:50.896984 ==
4077 00:26:50.899445 Dram Type= 6, Freq= 0, CH_0, rank 0
4078 00:26:50.903095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4079 00:26:50.903666 ==
4080 00:26:50.906645 Write leveling (Byte 0): 32 => 32
4081 00:26:50.909653 Write leveling (Byte 1): 29 => 29
4082 00:26:50.913255 DramcWriteLeveling(PI) end<-----
4083 00:26:50.913732
4084 00:26:50.914108 ==
4085 00:26:50.916438 Dram Type= 6, Freq= 0, CH_0, rank 0
4086 00:26:50.919236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4087 00:26:50.919724 ==
4088 00:26:50.922538 [Gating] SW mode calibration
4089 00:26:50.929376 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4090 00:26:50.936149 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4091 00:26:50.939327 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4092 00:26:50.942608 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4093 00:26:50.949013 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4094 00:26:50.952325 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4095 00:26:50.955371 0 9 16 | B1->B0 | 2f2f 2727 | 0 0 | (1 1) (0 0)
4096 00:26:50.962096 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4097 00:26:50.965569 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4098 00:26:50.968738 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4099 00:26:50.975491 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4100 00:26:50.978679 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4101 00:26:50.982427 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4102 00:26:50.988612 0 10 12 | B1->B0 | 2424 2a2a | 0 0 | (0 0) (0 0)
4103 00:26:50.991798 0 10 16 | B1->B0 | 3535 3f3f | 0 0 | (0 0) (0 0)
4104 00:26:50.994996 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4105 00:26:51.001768 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4106 00:26:51.005097 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4107 00:26:51.008096 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4108 00:26:51.014618 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4109 00:26:51.018030 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4110 00:26:51.024806 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4111 00:26:51.027837 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4112 00:26:51.031301 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4113 00:26:51.037782 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4114 00:26:51.041301 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4115 00:26:51.044049 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4116 00:26:51.050720 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4117 00:26:51.054111 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4118 00:26:51.057169 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4119 00:26:51.063784 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4120 00:26:51.067043 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4121 00:26:51.070629 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4122 00:26:51.077011 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4123 00:26:51.080154 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4124 00:26:51.083964 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4125 00:26:51.090591 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4126 00:26:51.093557 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4127 00:26:51.096888 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4128 00:26:51.100320 Total UI for P1: 0, mck2ui 16
4129 00:26:51.103796 best dqsien dly found for B0: ( 0, 13, 12)
4130 00:26:51.110331 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4131 00:26:51.110911 Total UI for P1: 0, mck2ui 16
4132 00:26:51.113277 best dqsien dly found for B1: ( 0, 13, 16)
4133 00:26:51.120451 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4134 00:26:51.123034 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4135 00:26:51.123548
4136 00:26:51.126651 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4137 00:26:51.129804 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4138 00:26:51.133143 [Gating] SW calibration Done
4139 00:26:51.133951 ==
4140 00:26:51.136526 Dram Type= 6, Freq= 0, CH_0, rank 0
4141 00:26:51.139890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4142 00:26:51.140400 ==
4143 00:26:51.143310 RX Vref Scan: 0
4144 00:26:51.143808
4145 00:26:51.144208 RX Vref 0 -> 0, step: 1
4146 00:26:51.144800
4147 00:26:51.146642 RX Delay -230 -> 252, step: 16
4148 00:26:51.154029 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4149 00:26:51.157033 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4150 00:26:51.159777 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4151 00:26:51.163526 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4152 00:26:51.166209 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4153 00:26:51.172636 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4154 00:26:51.176243 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4155 00:26:51.179353 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4156 00:26:51.182721 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4157 00:26:51.189730 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4158 00:26:51.192633 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4159 00:26:51.195805 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4160 00:26:51.199230 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4161 00:26:51.206114 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4162 00:26:51.209131 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4163 00:26:51.212836 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4164 00:26:51.213412 ==
4165 00:26:51.215970 Dram Type= 6, Freq= 0, CH_0, rank 0
4166 00:26:51.219319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4167 00:26:51.222798 ==
4168 00:26:51.223365 DQS Delay:
4169 00:26:51.223937 DQS0 = 0, DQS1 = 0
4170 00:26:51.225815 DQM Delay:
4171 00:26:51.226310 DQM0 = 41, DQM1 = 32
4172 00:26:51.228894 DQ Delay:
4173 00:26:51.229368 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =33
4174 00:26:51.232138 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4175 00:26:51.235420 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4176 00:26:51.238946 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4177 00:26:51.242314
4178 00:26:51.242874
4179 00:26:51.243316 ==
4180 00:26:51.245692 Dram Type= 6, Freq= 0, CH_0, rank 0
4181 00:26:51.248847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4182 00:26:51.249440 ==
4183 00:26:51.249818
4184 00:26:51.250209
4185 00:26:51.252031 TX Vref Scan disable
4186 00:26:51.252503 == TX Byte 0 ==
4187 00:26:51.258813 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4188 00:26:51.261876 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4189 00:26:51.262490 == TX Byte 1 ==
4190 00:26:51.268517 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4191 00:26:51.271774 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4192 00:26:51.272264 ==
4193 00:26:51.275603 Dram Type= 6, Freq= 0, CH_0, rank 0
4194 00:26:51.278363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4195 00:26:51.278842 ==
4196 00:26:51.279221
4197 00:26:51.279569
4198 00:26:51.281424 TX Vref Scan disable
4199 00:26:51.284995 == TX Byte 0 ==
4200 00:26:51.288526 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4201 00:26:51.295522 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4202 00:26:51.296240 == TX Byte 1 ==
4203 00:26:51.298013 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4204 00:26:51.304819 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4205 00:26:51.305406
4206 00:26:51.305783 [DATLAT]
4207 00:26:51.306131 Freq=600, CH0 RK0
4208 00:26:51.306518
4209 00:26:51.307952 DATLAT Default: 0x9
4210 00:26:51.308605 0, 0xFFFF, sum = 0
4211 00:26:51.311290 1, 0xFFFF, sum = 0
4212 00:26:51.315152 2, 0xFFFF, sum = 0
4213 00:26:51.315788 3, 0xFFFF, sum = 0
4214 00:26:51.318248 4, 0xFFFF, sum = 0
4215 00:26:51.318763 5, 0xFFFF, sum = 0
4216 00:26:51.321280 6, 0xFFFF, sum = 0
4217 00:26:51.321759 7, 0xFFFF, sum = 0
4218 00:26:51.324686 8, 0x0, sum = 1
4219 00:26:51.325162 9, 0x0, sum = 2
4220 00:26:51.327814 10, 0x0, sum = 3
4221 00:26:51.328271 11, 0x0, sum = 4
4222 00:26:51.328615 best_step = 9
4223 00:26:51.328929
4224 00:26:51.331237 ==
4225 00:26:51.334773 Dram Type= 6, Freq= 0, CH_0, rank 0
4226 00:26:51.337768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4227 00:26:51.338219 ==
4228 00:26:51.338569 RX Vref Scan: 1
4229 00:26:51.338889
4230 00:26:51.341205 RX Vref 0 -> 0, step: 1
4231 00:26:51.341941
4232 00:26:51.344422 RX Delay -179 -> 252, step: 8
4233 00:26:51.344961
4234 00:26:51.347939 Set Vref, RX VrefLevel [Byte0]: 58
4235 00:26:51.350784 [Byte1]: 58
4236 00:26:51.351320
4237 00:26:51.354103 Final RX Vref Byte 0 = 58 to rank0
4238 00:26:51.357451 Final RX Vref Byte 1 = 58 to rank0
4239 00:26:51.360946 Final RX Vref Byte 0 = 58 to rank1
4240 00:26:51.363953 Final RX Vref Byte 1 = 58 to rank1==
4241 00:26:51.367072 Dram Type= 6, Freq= 0, CH_0, rank 0
4242 00:26:51.373469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4243 00:26:51.373901 ==
4244 00:26:51.374300 DQS Delay:
4245 00:26:51.374630 DQS0 = 0, DQS1 = 0
4246 00:26:51.376912 DQM Delay:
4247 00:26:51.377381 DQM0 = 43, DQM1 = 32
4248 00:26:51.380528 DQ Delay:
4249 00:26:51.383706 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4250 00:26:51.387446 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =52
4251 00:26:51.390216 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =24
4252 00:26:51.393760 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4253 00:26:51.394228
4254 00:26:51.394581
4255 00:26:51.400388 [DQSOSCAuto] RK0, (LSB)MR18= 0x6941, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 390 ps
4256 00:26:51.403608 CH0 RK0: MR19=808, MR18=6941
4257 00:26:51.410259 CH0_RK0: MR19=0x808, MR18=0x6941, DQSOSC=390, MR23=63, INC=172, DEC=114
4258 00:26:51.410736
4259 00:26:51.413524 ----->DramcWriteLeveling(PI) begin...
4260 00:26:51.413962 ==
4261 00:26:51.416463 Dram Type= 6, Freq= 0, CH_0, rank 1
4262 00:26:51.419816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4263 00:26:51.420253 ==
4264 00:26:51.423164 Write leveling (Byte 0): 34 => 34
4265 00:26:51.426815 Write leveling (Byte 1): 29 => 29
4266 00:26:51.430062 DramcWriteLeveling(PI) end<-----
4267 00:26:51.430522
4268 00:26:51.430866 ==
4269 00:26:51.432959 Dram Type= 6, Freq= 0, CH_0, rank 1
4270 00:26:51.437045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4271 00:26:51.437605 ==
4272 00:26:51.439644 [Gating] SW mode calibration
4273 00:26:51.446544 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4274 00:26:51.453604 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4275 00:26:51.456347 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4276 00:26:51.462611 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4277 00:26:51.465949 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4278 00:26:51.469204 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4279 00:26:51.475709 0 9 16 | B1->B0 | 2f2f 2626 | 1 1 | (1 0) (1 0)
4280 00:26:51.479603 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4281 00:26:51.482520 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4282 00:26:51.488971 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4283 00:26:51.492155 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4284 00:26:51.495927 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4285 00:26:51.502350 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4286 00:26:51.505757 0 10 12 | B1->B0 | 2424 2626 | 1 0 | (0 0) (0 0)
4287 00:26:51.508923 0 10 16 | B1->B0 | 3d3d 3c3c | 0 1 | (0 0) (0 0)
4288 00:26:51.515972 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4289 00:26:51.519193 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4290 00:26:51.522017 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4291 00:26:51.528729 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4292 00:26:51.531980 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4293 00:26:51.535078 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4294 00:26:51.541906 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4295 00:26:51.545476 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4296 00:26:51.548782 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4297 00:26:51.554800 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4298 00:26:51.558556 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4299 00:26:51.562001 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4300 00:26:51.568572 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4301 00:26:51.571450 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4302 00:26:51.574711 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4303 00:26:51.581501 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4304 00:26:51.584906 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4305 00:26:51.588273 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4306 00:26:51.594808 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4307 00:26:51.597771 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4308 00:26:51.600941 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4309 00:26:51.608317 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4310 00:26:51.611943 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4311 00:26:51.614209 Total UI for P1: 0, mck2ui 16
4312 00:26:51.617663 best dqsien dly found for B0: ( 0, 13, 10)
4313 00:26:51.621556 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4314 00:26:51.627968 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4315 00:26:51.628552 Total UI for P1: 0, mck2ui 16
4316 00:26:51.634414 best dqsien dly found for B1: ( 0, 13, 14)
4317 00:26:51.638002 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4318 00:26:51.641413 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4319 00:26:51.641955
4320 00:26:51.644180 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4321 00:26:51.647699 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4322 00:26:51.650479 [Gating] SW calibration Done
4323 00:26:51.650948 ==
4324 00:26:51.653997 Dram Type= 6, Freq= 0, CH_0, rank 1
4325 00:26:51.657632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4326 00:26:51.658223 ==
4327 00:26:51.660608 RX Vref Scan: 0
4328 00:26:51.661064
4329 00:26:51.663461 RX Vref 0 -> 0, step: 1
4330 00:26:51.663898
4331 00:26:51.664338 RX Delay -230 -> 252, step: 16
4332 00:26:51.670287 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4333 00:26:51.673702 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4334 00:26:51.677006 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4335 00:26:51.680533 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4336 00:26:51.687226 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4337 00:26:51.690059 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4338 00:26:51.693481 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4339 00:26:51.696979 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4340 00:26:51.699940 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4341 00:26:51.706778 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4342 00:26:51.709904 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4343 00:26:51.713373 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4344 00:26:51.716701 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4345 00:26:51.723875 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4346 00:26:51.726915 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4347 00:26:51.729764 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4348 00:26:51.730330 ==
4349 00:26:51.733150 Dram Type= 6, Freq= 0, CH_0, rank 1
4350 00:26:51.740261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4351 00:26:51.740795 ==
4352 00:26:51.741204 DQS Delay:
4353 00:26:51.741530 DQS0 = 0, DQS1 = 0
4354 00:26:51.743080 DQM Delay:
4355 00:26:51.743690 DQM0 = 42, DQM1 = 35
4356 00:26:51.746099 DQ Delay:
4357 00:26:51.749501 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =33
4358 00:26:51.753011 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4359 00:26:51.756175 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =33
4360 00:26:51.759013 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4361 00:26:51.759535
4362 00:26:51.759886
4363 00:26:51.760201 ==
4364 00:26:51.762658 Dram Type= 6, Freq= 0, CH_0, rank 1
4365 00:26:51.765901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4366 00:26:51.766471 ==
4367 00:26:51.766928
4368 00:26:51.767260
4369 00:26:51.769187 TX Vref Scan disable
4370 00:26:51.772407 == TX Byte 0 ==
4371 00:26:51.775935 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4372 00:26:51.779385 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4373 00:26:51.782565 == TX Byte 1 ==
4374 00:26:51.786002 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4375 00:26:51.789138 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4376 00:26:51.789465 ==
4377 00:26:51.792196 Dram Type= 6, Freq= 0, CH_0, rank 1
4378 00:26:51.795268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4379 00:26:51.798876 ==
4380 00:26:51.799305
4381 00:26:51.799643
4382 00:26:51.799954 TX Vref Scan disable
4383 00:26:51.802882 == TX Byte 0 ==
4384 00:26:51.806289 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4385 00:26:51.812876 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4386 00:26:51.813304 == TX Byte 1 ==
4387 00:26:51.816444 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4388 00:26:51.822993 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4389 00:26:51.823425
4390 00:26:51.823758 [DATLAT]
4391 00:26:51.824074 Freq=600, CH0 RK1
4392 00:26:51.824380
4393 00:26:51.826071 DATLAT Default: 0x9
4394 00:26:51.826563 0, 0xFFFF, sum = 0
4395 00:26:51.829287 1, 0xFFFF, sum = 0
4396 00:26:51.832782 2, 0xFFFF, sum = 0
4397 00:26:51.833216 3, 0xFFFF, sum = 0
4398 00:26:51.836305 4, 0xFFFF, sum = 0
4399 00:26:51.836736 5, 0xFFFF, sum = 0
4400 00:26:51.839467 6, 0xFFFF, sum = 0
4401 00:26:51.839901 7, 0xFFFF, sum = 0
4402 00:26:51.842550 8, 0x0, sum = 1
4403 00:26:51.843146 9, 0x0, sum = 2
4404 00:26:51.846213 10, 0x0, sum = 3
4405 00:26:51.846658 11, 0x0, sum = 4
4406 00:26:51.847007 best_step = 9
4407 00:26:51.847324
4408 00:26:51.849612 ==
4409 00:26:51.853043 Dram Type= 6, Freq= 0, CH_0, rank 1
4410 00:26:51.855699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4411 00:26:51.856194 ==
4412 00:26:51.856540 RX Vref Scan: 0
4413 00:26:51.856862
4414 00:26:51.859135 RX Vref 0 -> 0, step: 1
4415 00:26:51.859564
4416 00:26:51.862245 RX Delay -195 -> 252, step: 8
4417 00:26:51.868966 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4418 00:26:51.871954 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4419 00:26:51.875358 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4420 00:26:51.879050 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4421 00:26:51.885429 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4422 00:26:51.888853 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4423 00:26:51.891794 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4424 00:26:51.895068 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4425 00:26:51.898874 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4426 00:26:51.905367 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4427 00:26:51.908875 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4428 00:26:51.912143 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4429 00:26:51.915047 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4430 00:26:51.921493 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4431 00:26:51.925526 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4432 00:26:51.928402 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4433 00:26:51.928834 ==
4434 00:26:51.931590 Dram Type= 6, Freq= 0, CH_0, rank 1
4435 00:26:51.934744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4436 00:26:51.938025 ==
4437 00:26:51.938496 DQS Delay:
4438 00:26:51.938843 DQS0 = 0, DQS1 = 0
4439 00:26:51.941297 DQM Delay:
4440 00:26:51.941724 DQM0 = 41, DQM1 = 35
4441 00:26:51.944547 DQ Delay:
4442 00:26:51.947951 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =40
4443 00:26:51.948380 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4444 00:26:51.951430 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =28
4445 00:26:51.957832 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =40
4446 00:26:51.958318
4447 00:26:51.958678
4448 00:26:51.964348 [DQSOSCAuto] RK1, (LSB)MR18= 0x6215, (MSB)MR19= 0x808, tDQSOscB0 = 405 ps tDQSOscB1 = 391 ps
4449 00:26:51.968176 CH0 RK1: MR19=808, MR18=6215
4450 00:26:51.974409 CH0_RK1: MR19=0x808, MR18=0x6215, DQSOSC=391, MR23=63, INC=171, DEC=114
4451 00:26:51.977758 [RxdqsGatingPostProcess] freq 600
4452 00:26:51.981469 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4453 00:26:51.984208 Pre-setting of DQS Precalculation
4454 00:26:51.991065 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4455 00:26:51.991498 ==
4456 00:26:51.994286 Dram Type= 6, Freq= 0, CH_1, rank 0
4457 00:26:51.997840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4458 00:26:51.998409 ==
4459 00:26:52.004432 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4460 00:26:52.010561 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4461 00:26:52.013687 [CA 0] Center 35 (5~66) winsize 62
4462 00:26:52.017086 [CA 1] Center 36 (6~66) winsize 61
4463 00:26:52.020525 [CA 2] Center 34 (4~65) winsize 62
4464 00:26:52.023781 [CA 3] Center 33 (3~64) winsize 62
4465 00:26:52.026968 [CA 4] Center 34 (4~64) winsize 61
4466 00:26:52.030208 [CA 5] Center 33 (3~64) winsize 62
4467 00:26:52.030654
4468 00:26:52.033208 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4469 00:26:52.033663
4470 00:26:52.036660 [CATrainingPosCal] consider 1 rank data
4471 00:26:52.040003 u2DelayCellTimex100 = 270/100 ps
4472 00:26:52.043485 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4473 00:26:52.046675 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4474 00:26:52.049904 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4475 00:26:52.053199 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4476 00:26:52.056708 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4477 00:26:52.059670 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4478 00:26:52.063103
4479 00:26:52.066567 CA PerBit enable=1, Macro0, CA PI delay=33
4480 00:26:52.067094
4481 00:26:52.069498 [CBTSetCACLKResult] CA Dly = 33
4482 00:26:52.070028 CS Dly: 5 (0~36)
4483 00:26:52.070538 ==
4484 00:26:52.073166 Dram Type= 6, Freq= 0, CH_1, rank 1
4485 00:26:52.076516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4486 00:26:52.076949 ==
4487 00:26:52.082875 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4488 00:26:52.089914 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4489 00:26:52.092852 [CA 0] Center 35 (5~66) winsize 62
4490 00:26:52.096340 [CA 1] Center 36 (6~66) winsize 61
4491 00:26:52.099617 [CA 2] Center 34 (4~65) winsize 62
4492 00:26:52.102710 [CA 3] Center 34 (4~65) winsize 62
4493 00:26:52.105795 [CA 4] Center 34 (4~65) winsize 62
4494 00:26:52.109154 [CA 5] Center 34 (3~65) winsize 63
4495 00:26:52.109588
4496 00:26:52.112956 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4497 00:26:52.113496
4498 00:26:52.115686 [CATrainingPosCal] consider 2 rank data
4499 00:26:52.119277 u2DelayCellTimex100 = 270/100 ps
4500 00:26:52.122147 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4501 00:26:52.125741 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4502 00:26:52.129250 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4503 00:26:52.135703 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4504 00:26:52.139594 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4505 00:26:52.142015 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4506 00:26:52.142493
4507 00:26:52.145444 CA PerBit enable=1, Macro0, CA PI delay=33
4508 00:26:52.145866
4509 00:26:52.148608 [CBTSetCACLKResult] CA Dly = 33
4510 00:26:52.149091 CS Dly: 5 (0~37)
4511 00:26:52.149532
4512 00:26:52.152434 ----->DramcWriteLeveling(PI) begin...
4513 00:26:52.155426 ==
4514 00:26:52.158953 Dram Type= 6, Freq= 0, CH_1, rank 0
4515 00:26:52.161902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4516 00:26:52.162548 ==
4517 00:26:52.165281 Write leveling (Byte 0): 29 => 29
4518 00:26:52.168149 Write leveling (Byte 1): 29 => 29
4519 00:26:52.171629 DramcWriteLeveling(PI) end<-----
4520 00:26:52.172103
4521 00:26:52.172480 ==
4522 00:26:52.175085 Dram Type= 6, Freq= 0, CH_1, rank 0
4523 00:26:52.178098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4524 00:26:52.178568 ==
4525 00:26:52.181558 [Gating] SW mode calibration
4526 00:26:52.188108 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4527 00:26:52.194474 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4528 00:26:52.198316 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4529 00:26:52.201443 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4530 00:26:52.207926 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4531 00:26:52.211102 0 9 12 | B1->B0 | 2f2f 2e2e | 1 0 | (1 0) (0 0)
4532 00:26:52.214240 0 9 16 | B1->B0 | 2323 2323 | 1 0 | (1 0) (0 0)
4533 00:26:52.220856 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4534 00:26:52.224403 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4535 00:26:52.227775 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4536 00:26:52.233898 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4537 00:26:52.237165 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4538 00:26:52.240631 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4539 00:26:52.247865 0 10 12 | B1->B0 | 3131 3b3b | 0 0 | (0 0) (1 1)
4540 00:26:52.251135 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4541 00:26:52.254235 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4542 00:26:52.260838 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4543 00:26:52.263791 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4544 00:26:52.267339 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4545 00:26:52.273782 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4546 00:26:52.277176 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4547 00:26:52.280221 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4548 00:26:52.286916 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4549 00:26:52.290203 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4550 00:26:52.293734 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4551 00:26:52.300180 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4552 00:26:52.303561 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4553 00:26:52.306705 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4554 00:26:52.313635 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4555 00:26:52.316701 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4556 00:26:52.319848 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4557 00:26:52.326441 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4558 00:26:52.330330 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4559 00:26:52.333243 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4560 00:26:52.340016 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4561 00:26:52.343413 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4562 00:26:52.346428 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4563 00:26:52.352964 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4564 00:26:52.353492 Total UI for P1: 0, mck2ui 16
4565 00:26:52.359746 best dqsien dly found for B0: ( 0, 13, 10)
4566 00:26:52.363349 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4567 00:26:52.366782 Total UI for P1: 0, mck2ui 16
4568 00:26:52.369601 best dqsien dly found for B1: ( 0, 13, 14)
4569 00:26:52.372627 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4570 00:26:52.376623 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4571 00:26:52.377173
4572 00:26:52.379366 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4573 00:26:52.382806 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4574 00:26:52.386142 [Gating] SW calibration Done
4575 00:26:52.386614 ==
4576 00:26:52.389534 Dram Type= 6, Freq= 0, CH_1, rank 0
4577 00:26:52.395799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4578 00:26:52.396294 ==
4579 00:26:52.396647 RX Vref Scan: 0
4580 00:26:52.396971
4581 00:26:52.399280 RX Vref 0 -> 0, step: 1
4582 00:26:52.399709
4583 00:26:52.402427 RX Delay -230 -> 252, step: 16
4584 00:26:52.405641 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4585 00:26:52.409077 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4586 00:26:52.412117 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4587 00:26:52.418851 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4588 00:26:52.422221 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4589 00:26:52.425726 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4590 00:26:52.428771 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4591 00:26:52.435698 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4592 00:26:52.438603 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4593 00:26:52.441796 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4594 00:26:52.445414 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4595 00:26:52.451704 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4596 00:26:52.455439 iDelay=218, Bit 12, Center 41 (-134 ~ 217) 352
4597 00:26:52.458240 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4598 00:26:52.461718 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4599 00:26:52.468276 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4600 00:26:52.468918 ==
4601 00:26:52.471402 Dram Type= 6, Freq= 0, CH_1, rank 0
4602 00:26:52.474747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4603 00:26:52.475227 ==
4604 00:26:52.475610 DQS Delay:
4605 00:26:52.478567 DQS0 = 0, DQS1 = 0
4606 00:26:52.479039 DQM Delay:
4607 00:26:52.482109 DQM0 = 46, DQM1 = 34
4608 00:26:52.482730 DQ Delay:
4609 00:26:52.484928 DQ0 =57, DQ1 =41, DQ2 =33, DQ3 =41
4610 00:26:52.488159 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4611 00:26:52.491498 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4612 00:26:52.495146 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =49
4613 00:26:52.495668
4614 00:26:52.496053
4615 00:26:52.496444 ==
4616 00:26:52.498365 Dram Type= 6, Freq= 0, CH_1, rank 0
4617 00:26:52.501293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4618 00:26:52.501725 ==
4619 00:26:52.502067
4620 00:26:52.504644
4621 00:26:52.505073 TX Vref Scan disable
4622 00:26:52.507905 == TX Byte 0 ==
4623 00:26:52.511522 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4624 00:26:52.514518 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4625 00:26:52.517921 == TX Byte 1 ==
4626 00:26:52.521051 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4627 00:26:52.524817 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4628 00:26:52.525346 ==
4629 00:26:52.527505 Dram Type= 6, Freq= 0, CH_1, rank 0
4630 00:26:52.534609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4631 00:26:52.535040 ==
4632 00:26:52.535384
4633 00:26:52.535700
4634 00:26:52.536002 TX Vref Scan disable
4635 00:26:52.538784 == TX Byte 0 ==
4636 00:26:52.542269 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4637 00:26:52.548934 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4638 00:26:52.549457 == TX Byte 1 ==
4639 00:26:52.552591 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4640 00:26:52.558711 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4641 00:26:52.559216
4642 00:26:52.559559 [DATLAT]
4643 00:26:52.559939 Freq=600, CH1 RK0
4644 00:26:52.560257
4645 00:26:52.561883 DATLAT Default: 0x9
4646 00:26:52.565443 0, 0xFFFF, sum = 0
4647 00:26:52.565972 1, 0xFFFF, sum = 0
4648 00:26:52.568492 2, 0xFFFF, sum = 0
4649 00:26:52.568926 3, 0xFFFF, sum = 0
4650 00:26:52.571721 4, 0xFFFF, sum = 0
4651 00:26:52.572157 5, 0xFFFF, sum = 0
4652 00:26:52.575379 6, 0xFFFF, sum = 0
4653 00:26:52.575835 7, 0xFFFF, sum = 0
4654 00:26:52.578846 8, 0x0, sum = 1
4655 00:26:52.579281 9, 0x0, sum = 2
4656 00:26:52.581689 10, 0x0, sum = 3
4657 00:26:52.582124 11, 0x0, sum = 4
4658 00:26:52.582512 best_step = 9
4659 00:26:52.582832
4660 00:26:52.585259 ==
4661 00:26:52.588461 Dram Type= 6, Freq= 0, CH_1, rank 0
4662 00:26:52.591401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4663 00:26:52.591842 ==
4664 00:26:52.592188 RX Vref Scan: 1
4665 00:26:52.592512
4666 00:26:52.595143 RX Vref 0 -> 0, step: 1
4667 00:26:52.595709
4668 00:26:52.598146 RX Delay -195 -> 252, step: 8
4669 00:26:52.598624
4670 00:26:52.601401 Set Vref, RX VrefLevel [Byte0]: 48
4671 00:26:52.604707 [Byte1]: 52
4672 00:26:52.605228
4673 00:26:52.608204 Final RX Vref Byte 0 = 48 to rank0
4674 00:26:52.611345 Final RX Vref Byte 1 = 52 to rank0
4675 00:26:52.614695 Final RX Vref Byte 0 = 48 to rank1
4676 00:26:52.617952 Final RX Vref Byte 1 = 52 to rank1==
4677 00:26:52.621600 Dram Type= 6, Freq= 0, CH_1, rank 0
4678 00:26:52.627779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4679 00:26:52.628298 ==
4680 00:26:52.628642 DQS Delay:
4681 00:26:52.628957 DQS0 = 0, DQS1 = 0
4682 00:26:52.630839 DQM Delay:
4683 00:26:52.631284 DQM0 = 47, DQM1 = 37
4684 00:26:52.634357 DQ Delay:
4685 00:26:52.637818 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44
4686 00:26:52.641265 DQ4 =44, DQ5 =56, DQ6 =56, DQ7 =44
4687 00:26:52.644759 DQ8 =28, DQ9 =28, DQ10 =40, DQ11 =28
4688 00:26:52.647879 DQ12 =44, DQ13 =44, DQ14 =40, DQ15 =44
4689 00:26:52.648448
4690 00:26:52.648788
4691 00:26:52.654091 [DQSOSCAuto] RK0, (LSB)MR18= 0x5236, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 394 ps
4692 00:26:52.657520 CH1 RK0: MR19=808, MR18=5236
4693 00:26:52.664207 CH1_RK0: MR19=0x808, MR18=0x5236, DQSOSC=394, MR23=63, INC=168, DEC=112
4694 00:26:52.664800
4695 00:26:52.667548 ----->DramcWriteLeveling(PI) begin...
4696 00:26:52.668095 ==
4697 00:26:52.670516 Dram Type= 6, Freq= 0, CH_1, rank 1
4698 00:26:52.673888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4699 00:26:52.674473 ==
4700 00:26:52.677295 Write leveling (Byte 0): 29 => 29
4701 00:26:52.680447 Write leveling (Byte 1): 29 => 29
4702 00:26:52.683504 DramcWriteLeveling(PI) end<-----
4703 00:26:52.683967
4704 00:26:52.684330 ==
4705 00:26:52.686912 Dram Type= 6, Freq= 0, CH_1, rank 1
4706 00:26:52.690075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4707 00:26:52.693965 ==
4708 00:26:52.694656 [Gating] SW mode calibration
4709 00:26:52.703227 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4710 00:26:52.707395 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4711 00:26:52.709755 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4712 00:26:52.716652 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4713 00:26:52.719816 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4714 00:26:52.723059 0 9 12 | B1->B0 | 3333 3333 | 0 0 | (1 0) (0 1)
4715 00:26:52.729824 0 9 16 | B1->B0 | 2424 2626 | 0 0 | (0 0) (0 0)
4716 00:26:52.732992 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4717 00:26:52.736180 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4718 00:26:52.742884 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4719 00:26:52.746197 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4720 00:26:52.749603 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4721 00:26:52.756230 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4722 00:26:52.759889 0 10 12 | B1->B0 | 3737 2626 | 0 0 | (0 0) (0 0)
4723 00:26:52.762591 0 10 16 | B1->B0 | 4545 4242 | 0 0 | (0 0) (0 0)
4724 00:26:52.769204 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4725 00:26:52.772660 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4726 00:26:52.775798 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4727 00:26:52.782012 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4728 00:26:52.785389 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4729 00:26:52.788867 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4730 00:26:52.795410 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4731 00:26:52.798948 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4732 00:26:52.802287 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4733 00:26:52.808808 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4734 00:26:52.811893 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4735 00:26:52.815430 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4736 00:26:52.822021 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4737 00:26:52.826063 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4738 00:26:52.828609 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4739 00:26:52.835269 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4740 00:26:52.838710 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4741 00:26:52.841731 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4742 00:26:52.848338 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4743 00:26:52.851527 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4744 00:26:52.855061 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4745 00:26:52.861666 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4746 00:26:52.864796 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4747 00:26:52.868176 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4748 00:26:52.871804 Total UI for P1: 0, mck2ui 16
4749 00:26:52.874609 best dqsien dly found for B0: ( 0, 13, 14)
4750 00:26:52.877773 Total UI for P1: 0, mck2ui 16
4751 00:26:52.881336 best dqsien dly found for B1: ( 0, 13, 14)
4752 00:26:52.887915 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4753 00:26:52.890988 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4754 00:26:52.891418
4755 00:26:52.894221 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4756 00:26:52.897479 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4757 00:26:52.900711 [Gating] SW calibration Done
4758 00:26:52.901140 ==
4759 00:26:52.904392 Dram Type= 6, Freq= 0, CH_1, rank 1
4760 00:26:52.907769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4761 00:26:52.908207 ==
4762 00:26:52.911364 RX Vref Scan: 0
4763 00:26:52.911857
4764 00:26:52.912311 RX Vref 0 -> 0, step: 1
4765 00:26:52.912641
4766 00:26:52.914884 RX Delay -230 -> 252, step: 16
4767 00:26:52.917729 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4768 00:26:52.924348 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4769 00:26:52.927708 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4770 00:26:52.930640 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4771 00:26:52.933768 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4772 00:26:52.940581 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4773 00:26:52.943668 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4774 00:26:52.946786 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4775 00:26:52.950108 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4776 00:26:52.956780 iDelay=218, Bit 9, Center 33 (-134 ~ 201) 336
4777 00:26:52.960176 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4778 00:26:52.963779 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4779 00:26:52.966602 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4780 00:26:52.973410 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4781 00:26:52.976736 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4782 00:26:52.979987 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4783 00:26:52.980414 ==
4784 00:26:52.983419 Dram Type= 6, Freq= 0, CH_1, rank 1
4785 00:26:52.986484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4786 00:26:52.989855 ==
4787 00:26:52.990359 DQS Delay:
4788 00:26:52.990713 DQS0 = 0, DQS1 = 0
4789 00:26:52.993395 DQM Delay:
4790 00:26:52.993811 DQM0 = 42, DQM1 = 39
4791 00:26:52.996320 DQ Delay:
4792 00:26:52.996773 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4793 00:26:52.999684 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =33
4794 00:26:53.002754 DQ8 =25, DQ9 =33, DQ10 =33, DQ11 =25
4795 00:26:53.006686 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4796 00:26:53.007204
4797 00:26:53.009741
4798 00:26:53.010312 ==
4799 00:26:53.012732 Dram Type= 6, Freq= 0, CH_1, rank 1
4800 00:26:53.016549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4801 00:26:53.017095 ==
4802 00:26:53.017443
4803 00:26:53.017751
4804 00:26:53.019584 TX Vref Scan disable
4805 00:26:53.020131 == TX Byte 0 ==
4806 00:26:53.025872 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4807 00:26:53.029458 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4808 00:26:53.030016 == TX Byte 1 ==
4809 00:26:53.035605 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4810 00:26:53.039155 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4811 00:26:53.039578 ==
4812 00:26:53.042701 Dram Type= 6, Freq= 0, CH_1, rank 1
4813 00:26:53.045702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4814 00:26:53.046128 ==
4815 00:26:53.046523
4816 00:26:53.046837
4817 00:26:53.049702 TX Vref Scan disable
4818 00:26:53.052612 == TX Byte 0 ==
4819 00:26:53.056074 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4820 00:26:53.062337 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4821 00:26:53.062923 == TX Byte 1 ==
4822 00:26:53.065846 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4823 00:26:53.072181 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4824 00:26:53.072643
4825 00:26:53.072981 [DATLAT]
4826 00:26:53.073293 Freq=600, CH1 RK1
4827 00:26:53.073589
4828 00:26:53.075691 DATLAT Default: 0x9
4829 00:26:53.076126 0, 0xFFFF, sum = 0
4830 00:26:53.078721 1, 0xFFFF, sum = 0
4831 00:26:53.081858 2, 0xFFFF, sum = 0
4832 00:26:53.082463 3, 0xFFFF, sum = 0
4833 00:26:53.085524 4, 0xFFFF, sum = 0
4834 00:26:53.085949 5, 0xFFFF, sum = 0
4835 00:26:53.088724 6, 0xFFFF, sum = 0
4836 00:26:53.089183 7, 0xFFFF, sum = 0
4837 00:26:53.092168 8, 0x0, sum = 1
4838 00:26:53.092593 9, 0x0, sum = 2
4839 00:26:53.092995 10, 0x0, sum = 3
4840 00:26:53.095575 11, 0x0, sum = 4
4841 00:26:53.096001 best_step = 9
4842 00:26:53.096333
4843 00:26:53.096638 ==
4844 00:26:53.098962 Dram Type= 6, Freq= 0, CH_1, rank 1
4845 00:26:53.105118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4846 00:26:53.105561 ==
4847 00:26:53.105952 RX Vref Scan: 0
4848 00:26:53.106392
4849 00:26:53.108614 RX Vref 0 -> 0, step: 1
4850 00:26:53.109042
4851 00:26:53.112075 RX Delay -179 -> 252, step: 8
4852 00:26:53.115210 iDelay=213, Bit 0, Center 48 (-99 ~ 196) 296
4853 00:26:53.121967 iDelay=213, Bit 1, Center 40 (-107 ~ 188) 296
4854 00:26:53.124926 iDelay=213, Bit 2, Center 32 (-115 ~ 180) 296
4855 00:26:53.128780 iDelay=213, Bit 3, Center 40 (-107 ~ 188) 296
4856 00:26:53.131984 iDelay=213, Bit 4, Center 44 (-107 ~ 196) 304
4857 00:26:53.138282 iDelay=213, Bit 5, Center 56 (-91 ~ 204) 296
4858 00:26:53.141510 iDelay=213, Bit 6, Center 60 (-91 ~ 212) 304
4859 00:26:53.145004 iDelay=213, Bit 7, Center 44 (-107 ~ 196) 304
4860 00:26:53.148491 iDelay=213, Bit 8, Center 24 (-131 ~ 180) 312
4861 00:26:53.151836 iDelay=213, Bit 9, Center 24 (-131 ~ 180) 312
4862 00:26:53.158001 iDelay=213, Bit 10, Center 36 (-115 ~ 188) 304
4863 00:26:53.161386 iDelay=213, Bit 11, Center 24 (-131 ~ 180) 312
4864 00:26:53.164548 iDelay=213, Bit 12, Center 48 (-107 ~ 204) 312
4865 00:26:53.171226 iDelay=213, Bit 13, Center 44 (-107 ~ 196) 304
4866 00:26:53.174427 iDelay=213, Bit 14, Center 44 (-107 ~ 196) 304
4867 00:26:53.177516 iDelay=213, Bit 15, Center 48 (-107 ~ 204) 312
4868 00:26:53.178051 ==
4869 00:26:53.180788 Dram Type= 6, Freq= 0, CH_1, rank 1
4870 00:26:53.184083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4871 00:26:53.184588 ==
4872 00:26:53.187528 DQS Delay:
4873 00:26:53.187958 DQS0 = 0, DQS1 = 0
4874 00:26:53.190671 DQM Delay:
4875 00:26:53.191103 DQM0 = 45, DQM1 = 36
4876 00:26:53.194274 DQ Delay:
4877 00:26:53.194815 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4878 00:26:53.197397 DQ4 =44, DQ5 =56, DQ6 =60, DQ7 =44
4879 00:26:53.200734 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =24
4880 00:26:53.203876 DQ12 =48, DQ13 =44, DQ14 =44, DQ15 =48
4881 00:26:53.204484
4882 00:26:53.207477
4883 00:26:53.214326 [DQSOSCAuto] RK1, (LSB)MR18= 0x2a1e, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 401 ps
4884 00:26:53.217848 CH1 RK1: MR19=808, MR18=2A1E
4885 00:26:53.223701 CH1_RK1: MR19=0x808, MR18=0x2A1E, DQSOSC=401, MR23=63, INC=163, DEC=108
4886 00:26:53.227517 [RxdqsGatingPostProcess] freq 600
4887 00:26:53.230699 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4888 00:26:53.233476 Pre-setting of DQS Precalculation
4889 00:26:53.240443 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4890 00:26:53.247088 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4891 00:26:53.253721 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4892 00:26:53.254236
4893 00:26:53.254632
4894 00:26:53.256598 [Calibration Summary] 1200 Mbps
4895 00:26:53.257097 CH 0, Rank 0
4896 00:26:53.260515 SW Impedance : PASS
4897 00:26:53.263251 DUTY Scan : NO K
4898 00:26:53.263731 ZQ Calibration : PASS
4899 00:26:53.267073 Jitter Meter : NO K
4900 00:26:53.269958 CBT Training : PASS
4901 00:26:53.270465 Write leveling : PASS
4902 00:26:53.273339 RX DQS gating : PASS
4903 00:26:53.276723 RX DQ/DQS(RDDQC) : PASS
4904 00:26:53.277196 TX DQ/DQS : PASS
4905 00:26:53.279933 RX DATLAT : PASS
4906 00:26:53.282771 RX DQ/DQS(Engine): PASS
4907 00:26:53.283202 TX OE : NO K
4908 00:26:53.283552 All Pass.
4909 00:26:53.286279
4910 00:26:53.286709 CH 0, Rank 1
4911 00:26:53.289515 SW Impedance : PASS
4912 00:26:53.289947 DUTY Scan : NO K
4913 00:26:53.293043 ZQ Calibration : PASS
4914 00:26:53.296251 Jitter Meter : NO K
4915 00:26:53.296694 CBT Training : PASS
4916 00:26:53.299329 Write leveling : PASS
4917 00:26:53.299762 RX DQS gating : PASS
4918 00:26:53.303087 RX DQ/DQS(RDDQC) : PASS
4919 00:26:53.306496 TX DQ/DQS : PASS
4920 00:26:53.306929 RX DATLAT : PASS
4921 00:26:53.309356 RX DQ/DQS(Engine): PASS
4922 00:26:53.312557 TX OE : NO K
4923 00:26:53.313037 All Pass.
4924 00:26:53.313388
4925 00:26:53.313709 CH 1, Rank 0
4926 00:26:53.316019 SW Impedance : PASS
4927 00:26:53.319368 DUTY Scan : NO K
4928 00:26:53.319799 ZQ Calibration : PASS
4929 00:26:53.322815 Jitter Meter : NO K
4930 00:26:53.326004 CBT Training : PASS
4931 00:26:53.326480 Write leveling : PASS
4932 00:26:53.329470 RX DQS gating : PASS
4933 00:26:53.332553 RX DQ/DQS(RDDQC) : PASS
4934 00:26:53.333091 TX DQ/DQS : PASS
4935 00:26:53.335722 RX DATLAT : PASS
4936 00:26:53.339128 RX DQ/DQS(Engine): PASS
4937 00:26:53.339606 TX OE : NO K
4938 00:26:53.342681 All Pass.
4939 00:26:53.343109
4940 00:26:53.343449 CH 1, Rank 1
4941 00:26:53.345975 SW Impedance : PASS
4942 00:26:53.346440 DUTY Scan : NO K
4943 00:26:53.349364 ZQ Calibration : PASS
4944 00:26:53.352411 Jitter Meter : NO K
4945 00:26:53.352939 CBT Training : PASS
4946 00:26:53.356175 Write leveling : PASS
4947 00:26:53.359147 RX DQS gating : PASS
4948 00:26:53.359681 RX DQ/DQS(RDDQC) : PASS
4949 00:26:53.361993 TX DQ/DQS : PASS
4950 00:26:53.365453 RX DATLAT : PASS
4951 00:26:53.365881 RX DQ/DQS(Engine): PASS
4952 00:26:53.368814 TX OE : NO K
4953 00:26:53.369247 All Pass.
4954 00:26:53.369587
4955 00:26:53.372285 DramC Write-DBI off
4956 00:26:53.375245 PER_BANK_REFRESH: Hybrid Mode
4957 00:26:53.375679 TX_TRACKING: ON
4958 00:26:53.385165 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4959 00:26:53.388911 [FAST_K] Save calibration result to emmc
4960 00:26:53.392407 dramc_set_vcore_voltage set vcore to 662500
4961 00:26:53.395154 Read voltage for 933, 3
4962 00:26:53.395631 Vio18 = 0
4963 00:26:53.396043 Vcore = 662500
4964 00:26:53.398686 Vdram = 0
4965 00:26:53.399158 Vddq = 0
4966 00:26:53.399532 Vmddr = 0
4967 00:26:53.405206 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4968 00:26:53.408412 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4969 00:26:53.411266 MEM_TYPE=3, freq_sel=17
4970 00:26:53.414716 sv_algorithm_assistance_LP4_1600
4971 00:26:53.418153 ============ PULL DRAM RESETB DOWN ============
4972 00:26:53.421812 ========== PULL DRAM RESETB DOWN end =========
4973 00:26:53.427918 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4974 00:26:53.431826 ===================================
4975 00:26:53.432345 LPDDR4 DRAM CONFIGURATION
4976 00:26:53.434598 ===================================
4977 00:26:53.437859 EX_ROW_EN[0] = 0x0
4978 00:26:53.441289 EX_ROW_EN[1] = 0x0
4979 00:26:53.441719 LP4Y_EN = 0x0
4980 00:26:53.444403 WORK_FSP = 0x0
4981 00:26:53.444837 WL = 0x3
4982 00:26:53.447747 RL = 0x3
4983 00:26:53.448335 BL = 0x2
4984 00:26:53.450991 RPST = 0x0
4985 00:26:53.451460 RD_PRE = 0x0
4986 00:26:53.454453 WR_PRE = 0x1
4987 00:26:53.454924 WR_PST = 0x0
4988 00:26:53.457902 DBI_WR = 0x0
4989 00:26:53.458367 DBI_RD = 0x0
4990 00:26:53.461150 OTF = 0x1
4991 00:26:53.464243 ===================================
4992 00:26:53.467959 ===================================
4993 00:26:53.468491 ANA top config
4994 00:26:53.471078 ===================================
4995 00:26:53.474467 DLL_ASYNC_EN = 0
4996 00:26:53.477862 ALL_SLAVE_EN = 1
4997 00:26:53.481394 NEW_RANK_MODE = 1
4998 00:26:53.481963 DLL_IDLE_MODE = 1
4999 00:26:53.484804 LP45_APHY_COMB_EN = 1
5000 00:26:53.488449 TX_ODT_DIS = 1
5001 00:26:53.491123 NEW_8X_MODE = 1
5002 00:26:53.494318 ===================================
5003 00:26:53.497760 ===================================
5004 00:26:53.501058 data_rate = 1866
5005 00:26:53.504103 CKR = 1
5006 00:26:53.504535 DQ_P2S_RATIO = 8
5007 00:26:53.507632 ===================================
5008 00:26:53.510626 CA_P2S_RATIO = 8
5009 00:26:53.513972 DQ_CA_OPEN = 0
5010 00:26:53.517715 DQ_SEMI_OPEN = 0
5011 00:26:53.520898 CA_SEMI_OPEN = 0
5012 00:26:53.523696 CA_FULL_RATE = 0
5013 00:26:53.524130 DQ_CKDIV4_EN = 1
5014 00:26:53.527396 CA_CKDIV4_EN = 1
5015 00:26:53.530095 CA_PREDIV_EN = 0
5016 00:26:53.533686 PH8_DLY = 0
5017 00:26:53.536835 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
5018 00:26:53.540556 DQ_AAMCK_DIV = 4
5019 00:26:53.540987 CA_AAMCK_DIV = 4
5020 00:26:53.543652 CA_ADMCK_DIV = 4
5021 00:26:53.546882 DQ_TRACK_CA_EN = 0
5022 00:26:53.550105 CA_PICK = 933
5023 00:26:53.553517 CA_MCKIO = 933
5024 00:26:53.557059 MCKIO_SEMI = 0
5025 00:26:53.560046 PLL_FREQ = 3732
5026 00:26:53.560492 DQ_UI_PI_RATIO = 32
5027 00:26:53.563496 CA_UI_PI_RATIO = 0
5028 00:26:53.567137 ===================================
5029 00:26:53.569964 ===================================
5030 00:26:53.573086 memory_type:LPDDR4
5031 00:26:53.576559 GP_NUM : 10
5032 00:26:53.576993 SRAM_EN : 1
5033 00:26:53.579765 MD32_EN : 0
5034 00:26:53.583087 ===================================
5035 00:26:53.586776 [ANA_INIT] >>>>>>>>>>>>>>
5036 00:26:53.587306 <<<<<< [CONFIGURE PHASE]: ANA_TX
5037 00:26:53.593472 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5038 00:26:53.596434 ===================================
5039 00:26:53.596905 data_rate = 1866,PCW = 0X8f00
5040 00:26:53.600169 ===================================
5041 00:26:53.602773 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5042 00:26:53.609653 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5043 00:26:53.616383 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5044 00:26:53.619611 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5045 00:26:53.622771 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5046 00:26:53.626321 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5047 00:26:53.629570 [ANA_INIT] flow start
5048 00:26:53.630133 [ANA_INIT] PLL >>>>>>>>
5049 00:26:53.632570 [ANA_INIT] PLL <<<<<<<<
5050 00:26:53.635779 [ANA_INIT] MIDPI >>>>>>>>
5051 00:26:53.639220 [ANA_INIT] MIDPI <<<<<<<<
5052 00:26:53.639697 [ANA_INIT] DLL >>>>>>>>
5053 00:26:53.642628 [ANA_INIT] flow end
5054 00:26:53.646256 ============ LP4 DIFF to SE enter ============
5055 00:26:53.649342 ============ LP4 DIFF to SE exit ============
5056 00:26:53.652444 [ANA_INIT] <<<<<<<<<<<<<
5057 00:26:53.655576 [Flow] Enable top DCM control >>>>>
5058 00:26:53.659007 [Flow] Enable top DCM control <<<<<
5059 00:26:53.662270 Enable DLL master slave shuffle
5060 00:26:53.669158 ==============================================================
5061 00:26:53.669641 Gating Mode config
5062 00:26:53.675273 ==============================================================
5063 00:26:53.675831 Config description:
5064 00:26:53.685421 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5065 00:26:53.692191 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5066 00:26:53.698538 SELPH_MODE 0: By rank 1: By Phase
5067 00:26:53.705379 ==============================================================
5068 00:26:53.705932 GAT_TRACK_EN = 1
5069 00:26:53.708574 RX_GATING_MODE = 2
5070 00:26:53.711707 RX_GATING_TRACK_MODE = 2
5071 00:26:53.715643 SELPH_MODE = 1
5072 00:26:53.718801 PICG_EARLY_EN = 1
5073 00:26:53.721789 VALID_LAT_VALUE = 1
5074 00:26:53.728683 ==============================================================
5075 00:26:53.731868 Enter into Gating configuration >>>>
5076 00:26:53.734937 Exit from Gating configuration <<<<
5077 00:26:53.738154 Enter into DVFS_PRE_config >>>>>
5078 00:26:53.748221 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5079 00:26:53.751912 Exit from DVFS_PRE_config <<<<<
5080 00:26:53.754542 Enter into PICG configuration >>>>
5081 00:26:53.758045 Exit from PICG configuration <<<<
5082 00:26:53.761568 [RX_INPUT] configuration >>>>>
5083 00:26:53.764880 [RX_INPUT] configuration <<<<<
5084 00:26:53.768214 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5085 00:26:53.774946 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5086 00:26:53.781348 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5087 00:26:53.784465 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5088 00:26:53.790842 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5089 00:26:53.797698 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5090 00:26:53.800735 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5091 00:26:53.807768 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5092 00:26:53.810527 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5093 00:26:53.814102 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5094 00:26:53.817540 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5095 00:26:53.824105 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5096 00:26:53.827115 ===================================
5097 00:26:53.830385 LPDDR4 DRAM CONFIGURATION
5098 00:26:53.833786 ===================================
5099 00:26:53.834293 EX_ROW_EN[0] = 0x0
5100 00:26:53.836978 EX_ROW_EN[1] = 0x0
5101 00:26:53.837523 LP4Y_EN = 0x0
5102 00:26:53.840558 WORK_FSP = 0x0
5103 00:26:53.841048 WL = 0x3
5104 00:26:53.844091 RL = 0x3
5105 00:26:53.844613 BL = 0x2
5106 00:26:53.846625 RPST = 0x0
5107 00:26:53.847057 RD_PRE = 0x0
5108 00:26:53.849900 WR_PRE = 0x1
5109 00:26:53.850354 WR_PST = 0x0
5110 00:26:53.853556 DBI_WR = 0x0
5111 00:26:53.857142 DBI_RD = 0x0
5112 00:26:53.857663 OTF = 0x1
5113 00:26:53.859992 ===================================
5114 00:26:53.863365 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5115 00:26:53.866709 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5116 00:26:53.873193 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5117 00:26:53.876981 ===================================
5118 00:26:53.879649 LPDDR4 DRAM CONFIGURATION
5119 00:26:53.882840 ===================================
5120 00:26:53.883319 EX_ROW_EN[0] = 0x10
5121 00:26:53.886477 EX_ROW_EN[1] = 0x0
5122 00:26:53.886950 LP4Y_EN = 0x0
5123 00:26:53.889668 WORK_FSP = 0x0
5124 00:26:53.890145 WL = 0x3
5125 00:26:53.893317 RL = 0x3
5126 00:26:53.893789 BL = 0x2
5127 00:26:53.896125 RPST = 0x0
5128 00:26:53.896602 RD_PRE = 0x0
5129 00:26:53.899344 WR_PRE = 0x1
5130 00:26:53.899777 WR_PST = 0x0
5131 00:26:53.902661 DBI_WR = 0x0
5132 00:26:53.905942 DBI_RD = 0x0
5133 00:26:53.906478 OTF = 0x1
5134 00:26:53.909691 ===================================
5135 00:26:53.915847 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5136 00:26:53.919688 nWR fixed to 30
5137 00:26:53.922964 [ModeRegInit_LP4] CH0 RK0
5138 00:26:53.923396 [ModeRegInit_LP4] CH0 RK1
5139 00:26:53.926341 [ModeRegInit_LP4] CH1 RK0
5140 00:26:53.929255 [ModeRegInit_LP4] CH1 RK1
5141 00:26:53.929685 match AC timing 9
5142 00:26:53.936196 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5143 00:26:53.939484 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5144 00:26:53.942538 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5145 00:26:53.949451 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5146 00:26:53.952985 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5147 00:26:53.953458 ==
5148 00:26:53.955686 Dram Type= 6, Freq= 0, CH_0, rank 0
5149 00:26:53.959159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5150 00:26:53.959734 ==
5151 00:26:53.965698 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5152 00:26:53.972743 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5153 00:26:53.975958 [CA 0] Center 37 (7~68) winsize 62
5154 00:26:53.979150 [CA 1] Center 37 (7~68) winsize 62
5155 00:26:53.982248 [CA 2] Center 34 (4~65) winsize 62
5156 00:26:53.985748 [CA 3] Center 35 (5~65) winsize 61
5157 00:26:53.988597 [CA 4] Center 33 (3~64) winsize 62
5158 00:26:53.992310 [CA 5] Center 33 (3~63) winsize 61
5159 00:26:53.992777
5160 00:26:53.995525 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5161 00:26:53.995998
5162 00:26:53.998758 [CATrainingPosCal] consider 1 rank data
5163 00:26:54.001902 u2DelayCellTimex100 = 270/100 ps
5164 00:26:54.005695 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5165 00:26:54.008825 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5166 00:26:54.011720 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5167 00:26:54.015229 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5168 00:26:54.022063 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5169 00:26:54.025280 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5170 00:26:54.025709
5171 00:26:54.028671 CA PerBit enable=1, Macro0, CA PI delay=33
5172 00:26:54.029193
5173 00:26:54.032230 [CBTSetCACLKResult] CA Dly = 33
5174 00:26:54.032752 CS Dly: 7 (0~38)
5175 00:26:54.033096 ==
5176 00:26:54.035169 Dram Type= 6, Freq= 0, CH_0, rank 1
5177 00:26:54.041526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5178 00:26:54.042099 ==
5179 00:26:54.044966 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5180 00:26:54.051336 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5181 00:26:54.054778 [CA 0] Center 37 (7~68) winsize 62
5182 00:26:54.058410 [CA 1] Center 37 (7~68) winsize 62
5183 00:26:54.061618 [CA 2] Center 34 (4~65) winsize 62
5184 00:26:54.064532 [CA 3] Center 35 (5~65) winsize 61
5185 00:26:54.067689 [CA 4] Center 33 (3~64) winsize 62
5186 00:26:54.071559 [CA 5] Center 33 (3~63) winsize 61
5187 00:26:54.072070
5188 00:26:54.074267 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5189 00:26:54.074694
5190 00:26:54.077478 [CATrainingPosCal] consider 2 rank data
5191 00:26:54.081039 u2DelayCellTimex100 = 270/100 ps
5192 00:26:54.087969 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5193 00:26:54.090548 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5194 00:26:54.094225 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5195 00:26:54.097261 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5196 00:26:54.100586 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5197 00:26:54.103873 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5198 00:26:54.104348
5199 00:26:54.107209 CA PerBit enable=1, Macro0, CA PI delay=33
5200 00:26:54.107687
5201 00:26:54.110303 [CBTSetCACLKResult] CA Dly = 33
5202 00:26:54.113647 CS Dly: 7 (0~39)
5203 00:26:54.114228
5204 00:26:54.117160 ----->DramcWriteLeveling(PI) begin...
5205 00:26:54.117723 ==
5206 00:26:54.120593 Dram Type= 6, Freq= 0, CH_0, rank 0
5207 00:26:54.123848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5208 00:26:54.124328 ==
5209 00:26:54.127140 Write leveling (Byte 0): 32 => 32
5210 00:26:54.130516 Write leveling (Byte 1): 31 => 31
5211 00:26:54.133731 DramcWriteLeveling(PI) end<-----
5212 00:26:54.134482
5213 00:26:54.134874 ==
5214 00:26:54.137014 Dram Type= 6, Freq= 0, CH_0, rank 0
5215 00:26:54.139871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5216 00:26:54.140350 ==
5217 00:26:54.143464 [Gating] SW mode calibration
5218 00:26:54.149621 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5219 00:26:54.156596 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5220 00:26:54.159833 0 14 0 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
5221 00:26:54.166062 0 14 4 | B1->B0 | 2e2e 3434 | 1 1 | (0 0) (1 1)
5222 00:26:54.169750 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5223 00:26:54.172935 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5224 00:26:54.179772 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5225 00:26:54.182620 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5226 00:26:54.185690 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5227 00:26:54.192559 0 14 28 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
5228 00:26:54.195857 0 15 0 | B1->B0 | 3131 2323 | 0 0 | (0 1) (1 0)
5229 00:26:54.199035 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5230 00:26:54.205760 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5231 00:26:54.208777 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5232 00:26:54.212181 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5233 00:26:54.219003 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5234 00:26:54.222486 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5235 00:26:54.225186 0 15 28 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
5236 00:26:54.232546 1 0 0 | B1->B0 | 3030 4444 | 0 0 | (0 0) (0 0)
5237 00:26:54.235302 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5238 00:26:54.238309 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5239 00:26:54.245022 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5240 00:26:54.248517 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5241 00:26:54.251860 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5242 00:26:54.258367 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5243 00:26:54.261157 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5244 00:26:54.264551 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5245 00:26:54.271642 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5246 00:26:54.274805 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5247 00:26:54.277973 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5248 00:26:54.284076 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5249 00:26:54.287647 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5250 00:26:54.291188 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5251 00:26:54.297560 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5252 00:26:54.301371 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5253 00:26:54.304324 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5254 00:26:54.310838 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5255 00:26:54.314291 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5256 00:26:54.317344 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5257 00:26:54.323887 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5258 00:26:54.327169 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5259 00:26:54.330571 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5260 00:26:54.336930 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5261 00:26:54.340611 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5262 00:26:54.343883 Total UI for P1: 0, mck2ui 16
5263 00:26:54.346955 best dqsien dly found for B0: ( 1, 2, 30)
5264 00:26:54.350146 Total UI for P1: 0, mck2ui 16
5265 00:26:54.353632 best dqsien dly found for B1: ( 1, 3, 0)
5266 00:26:54.356755 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5267 00:26:54.360068 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5268 00:26:54.360492
5269 00:26:54.363629 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5270 00:26:54.367086 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5271 00:26:54.370131 [Gating] SW calibration Done
5272 00:26:54.370702 ==
5273 00:26:54.373451 Dram Type= 6, Freq= 0, CH_0, rank 0
5274 00:26:54.380044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5275 00:26:54.380642 ==
5276 00:26:54.380995 RX Vref Scan: 0
5277 00:26:54.381477
5278 00:26:54.383594 RX Vref 0 -> 0, step: 1
5279 00:26:54.384034
5280 00:26:54.386513 RX Delay -80 -> 252, step: 8
5281 00:26:54.390156 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5282 00:26:54.393410 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5283 00:26:54.396590 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5284 00:26:54.399564 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5285 00:26:54.406494 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5286 00:26:54.409805 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5287 00:26:54.412884 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5288 00:26:54.416422 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5289 00:26:54.419423 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5290 00:26:54.422806 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5291 00:26:54.429283 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5292 00:26:54.432550 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5293 00:26:54.436257 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5294 00:26:54.439297 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5295 00:26:54.442775 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5296 00:26:54.449113 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5297 00:26:54.449546 ==
5298 00:26:54.452919 Dram Type= 6, Freq= 0, CH_0, rank 0
5299 00:26:54.456304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5300 00:26:54.456841 ==
5301 00:26:54.457192 DQS Delay:
5302 00:26:54.459198 DQS0 = 0, DQS1 = 0
5303 00:26:54.459740 DQM Delay:
5304 00:26:54.462541 DQM0 = 97, DQM1 = 87
5305 00:26:54.463154 DQ Delay:
5306 00:26:54.465736 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =91
5307 00:26:54.469158 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5308 00:26:54.472482 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5309 00:26:54.475442 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =95
5310 00:26:54.475873
5311 00:26:54.476210
5312 00:26:54.476519 ==
5313 00:26:54.478959 Dram Type= 6, Freq= 0, CH_0, rank 0
5314 00:26:54.485478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5315 00:26:54.485909 ==
5316 00:26:54.486290
5317 00:26:54.486614
5318 00:26:54.486923 TX Vref Scan disable
5319 00:26:54.488721 == TX Byte 0 ==
5320 00:26:54.491955 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5321 00:26:54.495449 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5322 00:26:54.498522 == TX Byte 1 ==
5323 00:26:54.502139 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5324 00:26:54.505526 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5325 00:26:54.508953 ==
5326 00:26:54.511987 Dram Type= 6, Freq= 0, CH_0, rank 0
5327 00:26:54.515233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5328 00:26:54.515708 ==
5329 00:26:54.516083
5330 00:26:54.516424
5331 00:26:54.518214 TX Vref Scan disable
5332 00:26:54.518681 == TX Byte 0 ==
5333 00:26:54.524785 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5334 00:26:54.528323 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5335 00:26:54.528752 == TX Byte 1 ==
5336 00:26:54.534966 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5337 00:26:54.537971 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5338 00:26:54.538457
5339 00:26:54.538806 [DATLAT]
5340 00:26:54.541724 Freq=933, CH0 RK0
5341 00:26:54.542153
5342 00:26:54.542523 DATLAT Default: 0xd
5343 00:26:54.544646 0, 0xFFFF, sum = 0
5344 00:26:54.548178 1, 0xFFFF, sum = 0
5345 00:26:54.548735 2, 0xFFFF, sum = 0
5346 00:26:54.551400 3, 0xFFFF, sum = 0
5347 00:26:54.551950 4, 0xFFFF, sum = 0
5348 00:26:54.555403 5, 0xFFFF, sum = 0
5349 00:26:54.555957 6, 0xFFFF, sum = 0
5350 00:26:54.557811 7, 0xFFFF, sum = 0
5351 00:26:54.558268 8, 0xFFFF, sum = 0
5352 00:26:54.561438 9, 0xFFFF, sum = 0
5353 00:26:54.561874 10, 0x0, sum = 1
5354 00:26:54.564576 11, 0x0, sum = 2
5355 00:26:54.565011 12, 0x0, sum = 3
5356 00:26:54.567838 13, 0x0, sum = 4
5357 00:26:54.568370 best_step = 11
5358 00:26:54.568708
5359 00:26:54.569022 ==
5360 00:26:54.570761 Dram Type= 6, Freq= 0, CH_0, rank 0
5361 00:26:54.574391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5362 00:26:54.577414 ==
5363 00:26:54.577833 RX Vref Scan: 1
5364 00:26:54.578189
5365 00:26:54.580609 RX Vref 0 -> 0, step: 1
5366 00:26:54.581044
5367 00:26:54.584009 RX Delay -61 -> 252, step: 4
5368 00:26:54.584430
5369 00:26:54.584762 Set Vref, RX VrefLevel [Byte0]: 58
5370 00:26:54.587504 [Byte1]: 58
5371 00:26:54.592267
5372 00:26:54.592560 Final RX Vref Byte 0 = 58 to rank0
5373 00:26:54.595492 Final RX Vref Byte 1 = 58 to rank0
5374 00:26:54.598946 Final RX Vref Byte 0 = 58 to rank1
5375 00:26:54.602239 Final RX Vref Byte 1 = 58 to rank1==
5376 00:26:54.605189 Dram Type= 6, Freq= 0, CH_0, rank 0
5377 00:26:54.611862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5378 00:26:54.612161 ==
5379 00:26:54.612398 DQS Delay:
5380 00:26:54.615625 DQS0 = 0, DQS1 = 0
5381 00:26:54.616019 DQM Delay:
5382 00:26:54.616261 DQM0 = 96, DQM1 = 87
5383 00:26:54.618834 DQ Delay:
5384 00:26:54.622228 DQ0 =94, DQ1 =98, DQ2 =92, DQ3 =92
5385 00:26:54.625784 DQ4 =96, DQ5 =88, DQ6 =104, DQ7 =106
5386 00:26:54.628900 DQ8 =80, DQ9 =76, DQ10 =86, DQ11 =84
5387 00:26:54.632355 DQ12 =92, DQ13 =88, DQ14 =96, DQ15 =94
5388 00:26:54.632919
5389 00:26:54.633287
5390 00:26:54.638545 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f15, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 407 ps
5391 00:26:54.642011 CH0 RK0: MR19=505, MR18=2F15
5392 00:26:54.648469 CH0_RK0: MR19=0x505, MR18=0x2F15, DQSOSC=407, MR23=63, INC=65, DEC=43
5393 00:26:54.649045
5394 00:26:54.651769 ----->DramcWriteLeveling(PI) begin...
5395 00:26:54.652329 ==
5396 00:26:54.655199 Dram Type= 6, Freq= 0, CH_0, rank 1
5397 00:26:54.658202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5398 00:26:54.658670 ==
5399 00:26:54.662084 Write leveling (Byte 0): 35 => 35
5400 00:26:54.665339 Write leveling (Byte 1): 33 => 33
5401 00:26:54.668122 DramcWriteLeveling(PI) end<-----
5402 00:26:54.668582
5403 00:26:54.668953 ==
5404 00:26:54.671350 Dram Type= 6, Freq= 0, CH_0, rank 1
5405 00:26:54.675489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5406 00:26:54.678096 ==
5407 00:26:54.678590 [Gating] SW mode calibration
5408 00:26:54.688187 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5409 00:26:54.691518 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5410 00:26:54.694758 0 14 0 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
5411 00:26:54.701217 0 14 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5412 00:26:54.704537 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5413 00:26:54.707820 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5414 00:26:54.714874 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5415 00:26:54.718064 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5416 00:26:54.721501 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5417 00:26:54.727914 0 14 28 | B1->B0 | 3434 2f2f | 0 0 | (0 0) (0 0)
5418 00:26:54.731116 0 15 0 | B1->B0 | 2d2d 2525 | 1 0 | (0 1) (0 0)
5419 00:26:54.734631 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5420 00:26:54.741121 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5421 00:26:54.744298 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5422 00:26:54.747590 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5423 00:26:54.754036 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5424 00:26:54.757297 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5425 00:26:54.760662 0 15 28 | B1->B0 | 2424 3131 | 0 0 | (0 0) (0 0)
5426 00:26:54.767309 1 0 0 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
5427 00:26:54.771091 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5428 00:26:54.773963 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5429 00:26:54.780962 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5430 00:26:54.783607 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5431 00:26:54.786911 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5432 00:26:54.793988 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5433 00:26:54.796945 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5434 00:26:54.800154 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5435 00:26:54.806845 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5436 00:26:54.810576 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5437 00:26:54.813642 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5438 00:26:54.820091 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5439 00:26:54.823395 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5440 00:26:54.826384 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5441 00:26:54.833309 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5442 00:26:54.836766 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5443 00:26:54.839733 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5444 00:26:54.846598 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5445 00:26:54.849770 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5446 00:26:54.853380 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5447 00:26:54.859418 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5448 00:26:54.862647 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5449 00:26:54.865856 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5450 00:26:54.873090 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5451 00:26:54.876626 Total UI for P1: 0, mck2ui 16
5452 00:26:54.879876 best dqsien dly found for B0: ( 1, 2, 30)
5453 00:26:54.882955 Total UI for P1: 0, mck2ui 16
5454 00:26:54.885785 best dqsien dly found for B1: ( 1, 2, 30)
5455 00:26:54.889258 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5456 00:26:54.892424 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5457 00:26:54.892899
5458 00:26:54.896025 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5459 00:26:54.898947 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5460 00:26:54.902668 [Gating] SW calibration Done
5461 00:26:54.903141 ==
5462 00:26:54.905537 Dram Type= 6, Freq= 0, CH_0, rank 1
5463 00:26:54.909399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5464 00:26:54.909970 ==
5465 00:26:54.912997 RX Vref Scan: 0
5466 00:26:54.913565
5467 00:26:54.913940 RX Vref 0 -> 0, step: 1
5468 00:26:54.915605
5469 00:26:54.916075 RX Delay -80 -> 252, step: 8
5470 00:26:54.922220 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5471 00:26:54.925839 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5472 00:26:54.928762 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5473 00:26:54.932167 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5474 00:26:54.935330 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5475 00:26:54.939108 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5476 00:26:54.945299 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5477 00:26:54.948484 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5478 00:26:54.951733 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5479 00:26:54.954920 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5480 00:26:54.958871 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5481 00:26:54.964775 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5482 00:26:54.968908 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5483 00:26:54.971626 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5484 00:26:54.975112 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5485 00:26:54.978583 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5486 00:26:54.979166 ==
5487 00:26:54.981961 Dram Type= 6, Freq= 0, CH_0, rank 1
5488 00:26:54.988372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5489 00:26:54.988868 ==
5490 00:26:54.989378 DQS Delay:
5491 00:26:54.991253 DQS0 = 0, DQS1 = 0
5492 00:26:54.991720 DQM Delay:
5493 00:26:54.992097 DQM0 = 96, DQM1 = 89
5494 00:26:54.994869 DQ Delay:
5495 00:26:54.998257 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5496 00:26:55.001232 DQ4 =95, DQ5 =87, DQ6 =103, DQ7 =107
5497 00:26:55.004571 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =87
5498 00:26:55.008042 DQ12 =91, DQ13 =95, DQ14 =99, DQ15 =95
5499 00:26:55.008467
5500 00:26:55.008797
5501 00:26:55.009105 ==
5502 00:26:55.011571 Dram Type= 6, Freq= 0, CH_0, rank 1
5503 00:26:55.014437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5504 00:26:55.014869 ==
5505 00:26:55.015206
5506 00:26:55.015516
5507 00:26:55.018413 TX Vref Scan disable
5508 00:26:55.020991 == TX Byte 0 ==
5509 00:26:55.024872 Update DQ dly =719 (2 ,6, 15) DQ OEN =(2 ,3)
5510 00:26:55.027890 Update DQM dly =719 (2 ,6, 15) DQM OEN =(2 ,3)
5511 00:26:55.031178 == TX Byte 1 ==
5512 00:26:55.034306 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5513 00:26:55.037764 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5514 00:26:55.038277 ==
5515 00:26:55.040882 Dram Type= 6, Freq= 0, CH_0, rank 1
5516 00:26:55.044593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5517 00:26:55.047569 ==
5518 00:26:55.048212
5519 00:26:55.048607
5520 00:26:55.048956 TX Vref Scan disable
5521 00:26:55.051159 == TX Byte 0 ==
5522 00:26:55.054656 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5523 00:26:55.061151 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5524 00:26:55.061621 == TX Byte 1 ==
5525 00:26:55.064802 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5526 00:26:55.071092 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5527 00:26:55.071671
5528 00:26:55.072043 [DATLAT]
5529 00:26:55.072393 Freq=933, CH0 RK1
5530 00:26:55.072729
5531 00:26:55.074565 DATLAT Default: 0xb
5532 00:26:55.078085 0, 0xFFFF, sum = 0
5533 00:26:55.078697 1, 0xFFFF, sum = 0
5534 00:26:55.081142 2, 0xFFFF, sum = 0
5535 00:26:55.081717 3, 0xFFFF, sum = 0
5536 00:26:55.084265 4, 0xFFFF, sum = 0
5537 00:26:55.084792 5, 0xFFFF, sum = 0
5538 00:26:55.087494 6, 0xFFFF, sum = 0
5539 00:26:55.087971 7, 0xFFFF, sum = 0
5540 00:26:55.090345 8, 0xFFFF, sum = 0
5541 00:26:55.090825 9, 0xFFFF, sum = 0
5542 00:26:55.093862 10, 0x0, sum = 1
5543 00:26:55.094558 11, 0x0, sum = 2
5544 00:26:55.097257 12, 0x0, sum = 3
5545 00:26:55.097842 13, 0x0, sum = 4
5546 00:26:55.100989 best_step = 11
5547 00:26:55.101459
5548 00:26:55.101830 ==
5549 00:26:55.103587 Dram Type= 6, Freq= 0, CH_0, rank 1
5550 00:26:55.107374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5551 00:26:55.107803 ==
5552 00:26:55.108146 RX Vref Scan: 0
5553 00:26:55.110244
5554 00:26:55.110669 RX Vref 0 -> 0, step: 1
5555 00:26:55.111013
5556 00:26:55.113516 RX Delay -61 -> 252, step: 4
5557 00:26:55.120760 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5558 00:26:55.123365 iDelay=203, Bit 1, Center 96 (-1 ~ 194) 196
5559 00:26:55.126955 iDelay=203, Bit 2, Center 90 (-1 ~ 182) 184
5560 00:26:55.130509 iDelay=203, Bit 3, Center 94 (-1 ~ 190) 192
5561 00:26:55.133613 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5562 00:26:55.139890 iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192
5563 00:26:55.143192 iDelay=203, Bit 6, Center 106 (11 ~ 202) 192
5564 00:26:55.146594 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5565 00:26:55.149656 iDelay=203, Bit 8, Center 80 (-13 ~ 174) 188
5566 00:26:55.153142 iDelay=203, Bit 9, Center 76 (-17 ~ 170) 188
5567 00:26:55.159712 iDelay=203, Bit 10, Center 90 (-5 ~ 186) 192
5568 00:26:55.162696 iDelay=203, Bit 11, Center 82 (-9 ~ 174) 184
5569 00:26:55.166401 iDelay=203, Bit 12, Center 90 (-5 ~ 186) 192
5570 00:26:55.169577 iDelay=203, Bit 13, Center 92 (-1 ~ 186) 188
5571 00:26:55.172703 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5572 00:26:55.179959 iDelay=203, Bit 15, Center 92 (-1 ~ 186) 188
5573 00:26:55.180491 ==
5574 00:26:55.183396 Dram Type= 6, Freq= 0, CH_0, rank 1
5575 00:26:55.186206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5576 00:26:55.186649 ==
5577 00:26:55.186991 DQS Delay:
5578 00:26:55.189532 DQS0 = 0, DQS1 = 0
5579 00:26:55.189963 DQM Delay:
5580 00:26:55.192594 DQM0 = 95, DQM1 = 87
5581 00:26:55.193019 DQ Delay:
5582 00:26:55.196301 DQ0 =92, DQ1 =96, DQ2 =90, DQ3 =94
5583 00:26:55.199406 DQ4 =96, DQ5 =86, DQ6 =106, DQ7 =104
5584 00:26:55.202683 DQ8 =80, DQ9 =76, DQ10 =90, DQ11 =82
5585 00:26:55.205983 DQ12 =90, DQ13 =92, DQ14 =96, DQ15 =92
5586 00:26:55.206489
5587 00:26:55.206829
5588 00:26:55.212879 [DQSOSCAuto] RK1, (LSB)MR18= 0x27f8, (MSB)MR19= 0x504, tDQSOscB0 = 424 ps tDQSOscB1 = 409 ps
5589 00:26:55.216111 CH0 RK1: MR19=504, MR18=27F8
5590 00:26:55.222308 CH0_RK1: MR19=0x504, MR18=0x27F8, DQSOSC=409, MR23=63, INC=64, DEC=43
5591 00:26:55.226007 [RxdqsGatingPostProcess] freq 933
5592 00:26:55.232874 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5593 00:26:55.236050 best DQS0 dly(2T, 0.5T) = (0, 10)
5594 00:26:55.238852 best DQS1 dly(2T, 0.5T) = (0, 11)
5595 00:26:55.242272 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5596 00:26:55.245677 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5597 00:26:55.246146 best DQS0 dly(2T, 0.5T) = (0, 10)
5598 00:26:55.249568 best DQS1 dly(2T, 0.5T) = (0, 10)
5599 00:26:55.252849 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5600 00:26:55.255550 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5601 00:26:55.259211 Pre-setting of DQS Precalculation
5602 00:26:55.265671 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5603 00:26:55.266145 ==
5604 00:26:55.268998 Dram Type= 6, Freq= 0, CH_1, rank 0
5605 00:26:55.272258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5606 00:26:55.272688 ==
5607 00:26:55.278870 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5608 00:26:55.285565 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5609 00:26:55.288567 [CA 0] Center 37 (7~67) winsize 61
5610 00:26:55.291922 [CA 1] Center 36 (6~67) winsize 62
5611 00:26:55.295515 [CA 2] Center 34 (4~65) winsize 62
5612 00:26:55.298391 [CA 3] Center 33 (3~64) winsize 62
5613 00:26:55.301646 [CA 4] Center 34 (4~64) winsize 61
5614 00:26:55.305349 [CA 5] Center 33 (3~64) winsize 62
5615 00:26:55.305918
5616 00:26:55.308529 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5617 00:26:55.309001
5618 00:26:55.312010 [CATrainingPosCal] consider 1 rank data
5619 00:26:55.314944 u2DelayCellTimex100 = 270/100 ps
5620 00:26:55.318326 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5621 00:26:55.321862 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5622 00:26:55.325191 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5623 00:26:55.328219 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5624 00:26:55.331901 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5625 00:26:55.334548 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5626 00:26:55.334975
5627 00:26:55.341332 CA PerBit enable=1, Macro0, CA PI delay=33
5628 00:26:55.341837
5629 00:26:55.342208 [CBTSetCACLKResult] CA Dly = 33
5630 00:26:55.344858 CS Dly: 6 (0~37)
5631 00:26:55.345283 ==
5632 00:26:55.347773 Dram Type= 6, Freq= 0, CH_1, rank 1
5633 00:26:55.351245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5634 00:26:55.351684 ==
5635 00:26:55.357658 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5636 00:26:55.364438 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5637 00:26:55.367761 [CA 0] Center 36 (6~67) winsize 62
5638 00:26:55.371205 [CA 1] Center 37 (7~67) winsize 61
5639 00:26:55.374070 [CA 2] Center 34 (4~65) winsize 62
5640 00:26:55.377755 [CA 3] Center 33 (3~64) winsize 62
5641 00:26:55.380925 [CA 4] Center 34 (4~65) winsize 62
5642 00:26:55.384209 [CA 5] Center 33 (3~64) winsize 62
5643 00:26:55.384637
5644 00:26:55.387527 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5645 00:26:55.387962
5646 00:26:55.390775 [CATrainingPosCal] consider 2 rank data
5647 00:26:55.394261 u2DelayCellTimex100 = 270/100 ps
5648 00:26:55.397546 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5649 00:26:55.400787 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5650 00:26:55.404304 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5651 00:26:55.407150 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5652 00:26:55.414014 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5653 00:26:55.417437 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5654 00:26:55.417928
5655 00:26:55.420580 CA PerBit enable=1, Macro0, CA PI delay=33
5656 00:26:55.421151
5657 00:26:55.423901 [CBTSetCACLKResult] CA Dly = 33
5658 00:26:55.424669 CS Dly: 7 (0~39)
5659 00:26:55.425070
5660 00:26:55.426900 ----->DramcWriteLeveling(PI) begin...
5661 00:26:55.427393 ==
5662 00:26:55.430341 Dram Type= 6, Freq= 0, CH_1, rank 0
5663 00:26:55.437539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5664 00:26:55.438110 ==
5665 00:26:55.440458 Write leveling (Byte 0): 27 => 27
5666 00:26:55.443615 Write leveling (Byte 1): 28 => 28
5667 00:26:55.444084 DramcWriteLeveling(PI) end<-----
5668 00:26:55.444455
5669 00:26:55.446823 ==
5670 00:26:55.447489 Dram Type= 6, Freq= 0, CH_1, rank 0
5671 00:26:55.453802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5672 00:26:55.454407 ==
5673 00:26:55.456888 [Gating] SW mode calibration
5674 00:26:55.463510 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5675 00:26:55.466665 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5676 00:26:55.473662 0 14 0 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
5677 00:26:55.476791 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5678 00:26:55.480424 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5679 00:26:55.486613 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5680 00:26:55.489930 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5681 00:26:55.493842 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5682 00:26:55.499690 0 14 24 | B1->B0 | 3434 3333 | 0 0 | (0 1) (0 1)
5683 00:26:55.502926 0 14 28 | B1->B0 | 2d2d 2727 | 0 0 | (0 0) (0 0)
5684 00:26:55.506228 0 15 0 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
5685 00:26:55.512788 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5686 00:26:55.516192 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5687 00:26:55.519326 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5688 00:26:55.525890 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5689 00:26:55.529096 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5690 00:26:55.532804 0 15 24 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
5691 00:26:55.539034 0 15 28 | B1->B0 | 3232 3c3c | 1 0 | (1 1) (0 0)
5692 00:26:55.542277 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5693 00:26:55.546319 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5694 00:26:55.552464 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5695 00:26:55.555832 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5696 00:26:55.559112 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5697 00:26:55.565664 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5698 00:26:55.568961 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5699 00:26:55.571947 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5700 00:26:55.579053 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5701 00:26:55.581935 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5702 00:26:55.585304 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5703 00:26:55.591869 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5704 00:26:55.595509 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5705 00:26:55.598632 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5706 00:26:55.605400 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5707 00:26:55.608184 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5708 00:26:55.612123 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5709 00:26:55.618508 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5710 00:26:55.621947 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5711 00:26:55.624750 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5712 00:26:55.631589 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5713 00:26:55.634608 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5714 00:26:55.637874 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5715 00:26:55.644460 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5716 00:26:55.648453 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5717 00:26:55.650963 Total UI for P1: 0, mck2ui 16
5718 00:26:55.654281 best dqsien dly found for B0: ( 1, 2, 28)
5719 00:26:55.657487 Total UI for P1: 0, mck2ui 16
5720 00:26:55.661329 best dqsien dly found for B1: ( 1, 2, 28)
5721 00:26:55.664393 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5722 00:26:55.667612 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5723 00:26:55.668036
5724 00:26:55.670759 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5725 00:26:55.677671 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5726 00:26:55.678095 [Gating] SW calibration Done
5727 00:26:55.678554 ==
5728 00:26:55.680508 Dram Type= 6, Freq= 0, CH_1, rank 0
5729 00:26:55.687004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5730 00:26:55.687438 ==
5731 00:26:55.687778 RX Vref Scan: 0
5732 00:26:55.688092
5733 00:26:55.690503 RX Vref 0 -> 0, step: 1
5734 00:26:55.690949
5735 00:26:55.693966 RX Delay -80 -> 252, step: 8
5736 00:26:55.697192 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5737 00:26:55.700201 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5738 00:26:55.703498 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5739 00:26:55.706904 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5740 00:26:55.713610 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5741 00:26:55.716769 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5742 00:26:55.720220 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5743 00:26:55.723005 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5744 00:26:55.726220 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5745 00:26:55.733390 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5746 00:26:55.736390 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5747 00:26:55.739661 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5748 00:26:55.743056 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5749 00:26:55.746404 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5750 00:26:55.753022 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5751 00:26:55.755871 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5752 00:26:55.756043 ==
5753 00:26:55.759963 Dram Type= 6, Freq= 0, CH_1, rank 0
5754 00:26:55.762877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5755 00:26:55.763164 ==
5756 00:26:55.766329 DQS Delay:
5757 00:26:55.766570 DQS0 = 0, DQS1 = 0
5758 00:26:55.766760 DQM Delay:
5759 00:26:55.769732 DQM0 = 100, DQM1 = 90
5760 00:26:55.770028 DQ Delay:
5761 00:26:55.772663 DQ0 =107, DQ1 =95, DQ2 =95, DQ3 =95
5762 00:26:55.775940 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5763 00:26:55.779713 DQ8 =75, DQ9 =83, DQ10 =91, DQ11 =79
5764 00:26:55.782699 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5765 00:26:55.783170
5766 00:26:55.783532
5767 00:26:55.783872 ==
5768 00:26:55.785949 Dram Type= 6, Freq= 0, CH_1, rank 0
5769 00:26:55.792463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5770 00:26:55.792932 ==
5771 00:26:55.793356
5772 00:26:55.793700
5773 00:26:55.794029 TX Vref Scan disable
5774 00:26:55.796507 == TX Byte 0 ==
5775 00:26:55.799662 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5776 00:26:55.806300 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5777 00:26:55.806887 == TX Byte 1 ==
5778 00:26:55.809576 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5779 00:26:55.816490 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5780 00:26:55.816958 ==
5781 00:26:55.819404 Dram Type= 6, Freq= 0, CH_1, rank 0
5782 00:26:55.822571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5783 00:26:55.823041 ==
5784 00:26:55.823409
5785 00:26:55.823744
5786 00:26:55.825972 TX Vref Scan disable
5787 00:26:55.826588 == TX Byte 0 ==
5788 00:26:55.832667 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5789 00:26:55.836119 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5790 00:26:55.839296 == TX Byte 1 ==
5791 00:26:55.842589 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5792 00:26:55.846091 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5793 00:26:55.846701
5794 00:26:55.847068 [DATLAT]
5795 00:26:55.849154 Freq=933, CH1 RK0
5796 00:26:55.849753
5797 00:26:55.852016 DATLAT Default: 0xd
5798 00:26:55.852475 0, 0xFFFF, sum = 0
5799 00:26:55.855277 1, 0xFFFF, sum = 0
5800 00:26:55.855750 2, 0xFFFF, sum = 0
5801 00:26:55.858441 3, 0xFFFF, sum = 0
5802 00:26:55.859058 4, 0xFFFF, sum = 0
5803 00:26:55.862193 5, 0xFFFF, sum = 0
5804 00:26:55.862668 6, 0xFFFF, sum = 0
5805 00:26:55.865451 7, 0xFFFF, sum = 0
5806 00:26:55.865981 8, 0xFFFF, sum = 0
5807 00:26:55.868699 9, 0xFFFF, sum = 0
5808 00:26:55.869165 10, 0x0, sum = 1
5809 00:26:55.872170 11, 0x0, sum = 2
5810 00:26:55.872739 12, 0x0, sum = 3
5811 00:26:55.875278 13, 0x0, sum = 4
5812 00:26:55.875749 best_step = 11
5813 00:26:55.876115
5814 00:26:55.876448 ==
5815 00:26:55.878687 Dram Type= 6, Freq= 0, CH_1, rank 0
5816 00:26:55.881921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5817 00:26:55.885185 ==
5818 00:26:55.885706 RX Vref Scan: 1
5819 00:26:55.886046
5820 00:26:55.888183 RX Vref 0 -> 0, step: 1
5821 00:26:55.888604
5822 00:26:55.892007 RX Delay -69 -> 252, step: 4
5823 00:26:55.892532
5824 00:26:55.895288 Set Vref, RX VrefLevel [Byte0]: 48
5825 00:26:55.895710 [Byte1]: 52
5826 00:26:55.900716
5827 00:26:55.901268 Final RX Vref Byte 0 = 48 to rank0
5828 00:26:55.903287 Final RX Vref Byte 1 = 52 to rank0
5829 00:26:55.906694 Final RX Vref Byte 0 = 48 to rank1
5830 00:26:55.910215 Final RX Vref Byte 1 = 52 to rank1==
5831 00:26:55.913310 Dram Type= 6, Freq= 0, CH_1, rank 0
5832 00:26:55.920202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5833 00:26:55.920625 ==
5834 00:26:55.920957 DQS Delay:
5835 00:26:55.923125 DQS0 = 0, DQS1 = 0
5836 00:26:55.923541 DQM Delay:
5837 00:26:55.923873 DQM0 = 100, DQM1 = 94
5838 00:26:55.926674 DQ Delay:
5839 00:26:55.929904 DQ0 =106, DQ1 =94, DQ2 =92, DQ3 =98
5840 00:26:55.933075 DQ4 =98, DQ5 =112, DQ6 =110, DQ7 =96
5841 00:26:55.936493 DQ8 =82, DQ9 =86, DQ10 =94, DQ11 =86
5842 00:26:55.939899 DQ12 =102, DQ13 =100, DQ14 =104, DQ15 =102
5843 00:26:55.940357
5844 00:26:55.940696
5845 00:26:55.946202 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a0a, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 413 ps
5846 00:26:55.949567 CH1 RK0: MR19=505, MR18=1A0A
5847 00:26:55.956149 CH1_RK0: MR19=0x505, MR18=0x1A0A, DQSOSC=413, MR23=63, INC=63, DEC=42
5848 00:26:55.956782
5849 00:26:55.959429 ----->DramcWriteLeveling(PI) begin...
5850 00:26:55.959897 ==
5851 00:26:55.962773 Dram Type= 6, Freq= 0, CH_1, rank 1
5852 00:26:55.966082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5853 00:26:55.969489 ==
5854 00:26:55.972588 Write leveling (Byte 0): 25 => 25
5855 00:26:55.973155 Write leveling (Byte 1): 30 => 30
5856 00:26:55.976171 DramcWriteLeveling(PI) end<-----
5857 00:26:55.976729
5858 00:26:55.977095 ==
5859 00:26:55.979183 Dram Type= 6, Freq= 0, CH_1, rank 1
5860 00:26:55.986247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5861 00:26:55.986820 ==
5862 00:26:55.988707 [Gating] SW mode calibration
5863 00:26:55.995548 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5864 00:26:55.998989 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5865 00:26:56.005498 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5866 00:26:56.008750 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5867 00:26:56.011759 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5868 00:26:56.018905 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5869 00:26:56.021706 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5870 00:26:56.024686 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5871 00:26:56.031335 0 14 24 | B1->B0 | 3232 3434 | 1 0 | (1 0) (0 0)
5872 00:26:56.034868 0 14 28 | B1->B0 | 2727 2f2f | 0 0 | (0 0) (0 1)
5873 00:26:56.038058 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5874 00:26:56.044399 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5875 00:26:56.047772 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5876 00:26:56.051239 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5877 00:26:56.057556 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5878 00:26:56.061185 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5879 00:26:56.064032 0 15 24 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
5880 00:26:56.071248 0 15 28 | B1->B0 | 4141 3939 | 0 0 | (0 0) (0 0)
5881 00:26:56.074117 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5882 00:26:56.077727 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5883 00:26:56.083923 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5884 00:26:56.087093 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5885 00:26:56.090516 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5886 00:26:56.097315 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5887 00:26:56.100508 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5888 00:26:56.104017 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5889 00:26:56.110786 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5890 00:26:56.113894 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5891 00:26:56.117260 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5892 00:26:56.123861 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5893 00:26:56.127220 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5894 00:26:56.130391 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5895 00:26:56.136930 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5896 00:26:56.140331 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5897 00:26:56.143474 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5898 00:26:56.150025 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5899 00:26:56.153350 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5900 00:26:56.157132 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5901 00:26:56.163500 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5902 00:26:56.167015 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5903 00:26:56.170513 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5904 00:26:56.176426 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5905 00:26:56.179864 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5906 00:26:56.183431 Total UI for P1: 0, mck2ui 16
5907 00:26:56.186605 best dqsien dly found for B0: ( 1, 2, 28)
5908 00:26:56.190024 Total UI for P1: 0, mck2ui 16
5909 00:26:56.192986 best dqsien dly found for B1: ( 1, 2, 26)
5910 00:26:56.196427 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5911 00:26:56.199716 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5912 00:26:56.199808
5913 00:26:56.203172 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5914 00:26:56.206300 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5915 00:26:56.209809 [Gating] SW calibration Done
5916 00:26:56.209911 ==
5917 00:26:56.212825 Dram Type= 6, Freq= 0, CH_1, rank 1
5918 00:26:56.216150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5919 00:26:56.219728 ==
5920 00:26:56.219811 RX Vref Scan: 0
5921 00:26:56.219878
5922 00:26:56.223077 RX Vref 0 -> 0, step: 1
5923 00:26:56.223161
5924 00:26:56.226067 RX Delay -80 -> 252, step: 8
5925 00:26:56.229337 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5926 00:26:56.232605 iDelay=208, Bit 1, Center 91 (0 ~ 183) 184
5927 00:26:56.235941 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5928 00:26:56.239296 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5929 00:26:56.242866 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5930 00:26:56.249800 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5931 00:26:56.252685 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5932 00:26:56.256121 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5933 00:26:56.259162 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5934 00:26:56.262429 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5935 00:26:56.269066 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5936 00:26:56.272584 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5937 00:26:56.275787 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5938 00:26:56.279414 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5939 00:26:56.281987 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5940 00:26:56.289028 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5941 00:26:56.289237 ==
5942 00:26:56.292418 Dram Type= 6, Freq= 0, CH_1, rank 1
5943 00:26:56.295656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5944 00:26:56.295842 ==
5945 00:26:56.295955 DQS Delay:
5946 00:26:56.298467 DQS0 = 0, DQS1 = 0
5947 00:26:56.298610 DQM Delay:
5948 00:26:56.302140 DQM0 = 99, DQM1 = 90
5949 00:26:56.302380 DQ Delay:
5950 00:26:56.305364 DQ0 =103, DQ1 =91, DQ2 =91, DQ3 =99
5951 00:26:56.308566 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5952 00:26:56.311819 DQ8 =75, DQ9 =79, DQ10 =95, DQ11 =79
5953 00:26:56.315488 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =99
5954 00:26:56.315779
5955 00:26:56.315952
5956 00:26:56.316101 ==
5957 00:26:56.318526 Dram Type= 6, Freq= 0, CH_1, rank 1
5958 00:26:56.321682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5959 00:26:56.321927 ==
5960 00:26:56.325639
5961 00:26:56.326030
5962 00:26:56.326306 TX Vref Scan disable
5963 00:26:56.329003 == TX Byte 0 ==
5964 00:26:56.331880 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5965 00:26:56.335163 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5966 00:26:56.338739 == TX Byte 1 ==
5967 00:26:56.342084 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5968 00:26:56.345054 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5969 00:26:56.348553 ==
5970 00:26:56.349119 Dram Type= 6, Freq= 0, CH_1, rank 1
5971 00:26:56.355540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5972 00:26:56.356107 ==
5973 00:26:56.356486
5974 00:26:56.356832
5975 00:26:56.358104 TX Vref Scan disable
5976 00:26:56.358638 == TX Byte 0 ==
5977 00:26:56.365261 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5978 00:26:56.368848 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5979 00:26:56.369423 == TX Byte 1 ==
5980 00:26:56.374794 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5981 00:26:56.377757 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5982 00:26:56.378298
5983 00:26:56.378686 [DATLAT]
5984 00:26:56.381539 Freq=933, CH1 RK1
5985 00:26:56.382035
5986 00:26:56.382444 DATLAT Default: 0xb
5987 00:26:56.384837 0, 0xFFFF, sum = 0
5988 00:26:56.385415 1, 0xFFFF, sum = 0
5989 00:26:56.387942 2, 0xFFFF, sum = 0
5990 00:26:56.391029 3, 0xFFFF, sum = 0
5991 00:26:56.391720 4, 0xFFFF, sum = 0
5992 00:26:56.394358 5, 0xFFFF, sum = 0
5993 00:26:56.394839 6, 0xFFFF, sum = 0
5994 00:26:56.397456 7, 0xFFFF, sum = 0
5995 00:26:56.397934 8, 0xFFFF, sum = 0
5996 00:26:56.401148 9, 0xFFFF, sum = 0
5997 00:26:56.401722 10, 0x0, sum = 1
5998 00:26:56.404294 11, 0x0, sum = 2
5999 00:26:56.404868 12, 0x0, sum = 3
6000 00:26:56.407473 13, 0x0, sum = 4
6001 00:26:56.407955 best_step = 11
6002 00:26:56.408379
6003 00:26:56.408729 ==
6004 00:26:56.410938 Dram Type= 6, Freq= 0, CH_1, rank 1
6005 00:26:56.413905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6006 00:26:56.414432 ==
6007 00:26:56.417394 RX Vref Scan: 0
6008 00:26:56.417855
6009 00:26:56.420823 RX Vref 0 -> 0, step: 1
6010 00:26:56.421320
6011 00:26:56.421700 RX Delay -69 -> 252, step: 4
6012 00:26:56.428809 iDelay=207, Bit 0, Center 106 (19 ~ 194) 176
6013 00:26:56.431775 iDelay=207, Bit 1, Center 96 (11 ~ 182) 172
6014 00:26:56.435403 iDelay=207, Bit 2, Center 90 (3 ~ 178) 176
6015 00:26:56.438435 iDelay=207, Bit 3, Center 98 (15 ~ 182) 168
6016 00:26:56.442374 iDelay=207, Bit 4, Center 98 (7 ~ 190) 184
6017 00:26:56.448519 iDelay=207, Bit 5, Center 110 (23 ~ 198) 176
6018 00:26:56.451578 iDelay=207, Bit 6, Center 114 (23 ~ 206) 184
6019 00:26:56.455029 iDelay=207, Bit 7, Center 98 (7 ~ 190) 184
6020 00:26:56.458257 iDelay=207, Bit 8, Center 82 (-9 ~ 174) 184
6021 00:26:56.461541 iDelay=207, Bit 9, Center 82 (-9 ~ 174) 184
6022 00:26:56.464724 iDelay=207, Bit 10, Center 94 (3 ~ 186) 184
6023 00:26:56.471577 iDelay=207, Bit 11, Center 84 (-5 ~ 174) 180
6024 00:26:56.475099 iDelay=207, Bit 12, Center 104 (15 ~ 194) 180
6025 00:26:56.478345 iDelay=207, Bit 13, Center 100 (7 ~ 194) 188
6026 00:26:56.481468 iDelay=207, Bit 14, Center 102 (15 ~ 190) 176
6027 00:26:56.487948 iDelay=207, Bit 15, Center 104 (15 ~ 194) 180
6028 00:26:56.488494 ==
6029 00:26:56.491153 Dram Type= 6, Freq= 0, CH_1, rank 1
6030 00:26:56.494385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6031 00:26:56.494931 ==
6032 00:26:56.495315 DQS Delay:
6033 00:26:56.497457 DQS0 = 0, DQS1 = 0
6034 00:26:56.497919 DQM Delay:
6035 00:26:56.500842 DQM0 = 101, DQM1 = 94
6036 00:26:56.501303 DQ Delay:
6037 00:26:56.504055 DQ0 =106, DQ1 =96, DQ2 =90, DQ3 =98
6038 00:26:56.507670 DQ4 =98, DQ5 =110, DQ6 =114, DQ7 =98
6039 00:26:56.510760 DQ8 =82, DQ9 =82, DQ10 =94, DQ11 =84
6040 00:26:56.514344 DQ12 =104, DQ13 =100, DQ14 =102, DQ15 =104
6041 00:26:56.514890
6042 00:26:56.515535
6043 00:26:56.523887 [DQSOSCAuto] RK1, (LSB)MR18= 0x7ff, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 419 ps
6044 00:26:56.526869 CH1 RK1: MR19=504, MR18=7FF
6045 00:26:56.530398 CH1_RK1: MR19=0x504, MR18=0x7FF, DQSOSC=419, MR23=63, INC=61, DEC=41
6046 00:26:56.533455 [RxdqsGatingPostProcess] freq 933
6047 00:26:56.540579 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6048 00:26:56.543608 best DQS0 dly(2T, 0.5T) = (0, 10)
6049 00:26:56.546836 best DQS1 dly(2T, 0.5T) = (0, 10)
6050 00:26:56.550071 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6051 00:26:56.553274 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6052 00:26:56.556995 best DQS0 dly(2T, 0.5T) = (0, 10)
6053 00:26:56.560036 best DQS1 dly(2T, 0.5T) = (0, 10)
6054 00:26:56.563078 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6055 00:26:56.566495 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6056 00:26:56.570329 Pre-setting of DQS Precalculation
6057 00:26:56.573268 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6058 00:26:56.579639 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6059 00:26:56.586903 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6060 00:26:56.587469
6061 00:26:56.590141
6062 00:26:56.590931 [Calibration Summary] 1866 Mbps
6063 00:26:56.593025 CH 0, Rank 0
6064 00:26:56.593491 SW Impedance : PASS
6065 00:26:56.596200 DUTY Scan : NO K
6066 00:26:56.599876 ZQ Calibration : PASS
6067 00:26:56.600479 Jitter Meter : NO K
6068 00:26:56.602719 CBT Training : PASS
6069 00:26:56.606263 Write leveling : PASS
6070 00:26:56.606815 RX DQS gating : PASS
6071 00:26:56.609291 RX DQ/DQS(RDDQC) : PASS
6072 00:26:56.613037 TX DQ/DQS : PASS
6073 00:26:56.613613 RX DATLAT : PASS
6074 00:26:56.616321 RX DQ/DQS(Engine): PASS
6075 00:26:56.619424 TX OE : NO K
6076 00:26:56.619897 All Pass.
6077 00:26:56.620326
6078 00:26:56.620868 CH 0, Rank 1
6079 00:26:56.623098 SW Impedance : PASS
6080 00:26:56.626018 DUTY Scan : NO K
6081 00:26:56.626521 ZQ Calibration : PASS
6082 00:26:56.629495 Jitter Meter : NO K
6083 00:26:56.632687 CBT Training : PASS
6084 00:26:56.633248 Write leveling : PASS
6085 00:26:56.636289 RX DQS gating : PASS
6086 00:26:56.636895 RX DQ/DQS(RDDQC) : PASS
6087 00:26:56.639532 TX DQ/DQS : PASS
6088 00:26:56.642730 RX DATLAT : PASS
6089 00:26:56.643201 RX DQ/DQS(Engine): PASS
6090 00:26:56.645691 TX OE : NO K
6091 00:26:56.646192 All Pass.
6092 00:26:56.646691
6093 00:26:56.649176 CH 1, Rank 0
6094 00:26:56.649642 SW Impedance : PASS
6095 00:26:56.652430 DUTY Scan : NO K
6096 00:26:56.655749 ZQ Calibration : PASS
6097 00:26:56.656318 Jitter Meter : NO K
6098 00:26:56.658843 CBT Training : PASS
6099 00:26:56.662151 Write leveling : PASS
6100 00:26:56.662662 RX DQS gating : PASS
6101 00:26:56.665441 RX DQ/DQS(RDDQC) : PASS
6102 00:26:56.668902 TX DQ/DQS : PASS
6103 00:26:56.669376 RX DATLAT : PASS
6104 00:26:56.671992 RX DQ/DQS(Engine): PASS
6105 00:26:56.675598 TX OE : NO K
6106 00:26:56.676179 All Pass.
6107 00:26:56.676729
6108 00:26:56.677149 CH 1, Rank 1
6109 00:26:56.678785 SW Impedance : PASS
6110 00:26:56.682090 DUTY Scan : NO K
6111 00:26:56.682542 ZQ Calibration : PASS
6112 00:26:56.685236 Jitter Meter : NO K
6113 00:26:56.688964 CBT Training : PASS
6114 00:26:56.689502 Write leveling : PASS
6115 00:26:56.691939 RX DQS gating : PASS
6116 00:26:56.695086 RX DQ/DQS(RDDQC) : PASS
6117 00:26:56.695668 TX DQ/DQS : PASS
6118 00:26:56.698587 RX DATLAT : PASS
6119 00:26:56.702050 RX DQ/DQS(Engine): PASS
6120 00:26:56.702500 TX OE : NO K
6121 00:26:56.702841 All Pass.
6122 00:26:56.704888
6123 00:26:56.705307 DramC Write-DBI off
6124 00:26:56.708145 PER_BANK_REFRESH: Hybrid Mode
6125 00:26:56.708578 TX_TRACKING: ON
6126 00:26:56.718266 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6127 00:26:56.721366 [FAST_K] Save calibration result to emmc
6128 00:26:56.724316 dramc_set_vcore_voltage set vcore to 650000
6129 00:26:56.728299 Read voltage for 400, 6
6130 00:26:56.728720 Vio18 = 0
6131 00:26:56.731161 Vcore = 650000
6132 00:26:56.731580 Vdram = 0
6133 00:26:56.731914 Vddq = 0
6134 00:26:56.734529 Vmddr = 0
6135 00:26:56.737905 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6136 00:26:56.744559 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6137 00:26:56.745009 MEM_TYPE=3, freq_sel=20
6138 00:26:56.747787 sv_algorithm_assistance_LP4_800
6139 00:26:56.754601 ============ PULL DRAM RESETB DOWN ============
6140 00:26:56.757924 ========== PULL DRAM RESETB DOWN end =========
6141 00:26:56.761051 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6142 00:26:56.764559 ===================================
6143 00:26:56.767721 LPDDR4 DRAM CONFIGURATION
6144 00:26:56.770980 ===================================
6145 00:26:56.771404 EX_ROW_EN[0] = 0x0
6146 00:26:56.774472 EX_ROW_EN[1] = 0x0
6147 00:26:56.777655 LP4Y_EN = 0x0
6148 00:26:56.778072 WORK_FSP = 0x0
6149 00:26:56.780884 WL = 0x2
6150 00:26:56.781337 RL = 0x2
6151 00:26:56.784214 BL = 0x2
6152 00:26:56.784667 RPST = 0x0
6153 00:26:56.787685 RD_PRE = 0x0
6154 00:26:56.788193 WR_PRE = 0x1
6155 00:26:56.790977 WR_PST = 0x0
6156 00:26:56.791414 DBI_WR = 0x0
6157 00:26:56.793767 DBI_RD = 0x0
6158 00:26:56.794210 OTF = 0x1
6159 00:26:56.797124 ===================================
6160 00:26:56.800486 ===================================
6161 00:26:56.804136 ANA top config
6162 00:26:56.807265 ===================================
6163 00:26:56.807688 DLL_ASYNC_EN = 0
6164 00:26:56.810681 ALL_SLAVE_EN = 1
6165 00:26:56.813701 NEW_RANK_MODE = 1
6166 00:26:56.817225 DLL_IDLE_MODE = 1
6167 00:26:56.820304 LP45_APHY_COMB_EN = 1
6168 00:26:56.820723 TX_ODT_DIS = 1
6169 00:26:56.823517 NEW_8X_MODE = 1
6170 00:26:56.827485 ===================================
6171 00:26:56.830442 ===================================
6172 00:26:56.833562 data_rate = 800
6173 00:26:56.836863 CKR = 1
6174 00:26:56.840183 DQ_P2S_RATIO = 4
6175 00:26:56.843903 ===================================
6176 00:26:56.846928 CA_P2S_RATIO = 4
6177 00:26:56.847469 DQ_CA_OPEN = 0
6178 00:26:56.849903 DQ_SEMI_OPEN = 1
6179 00:26:56.853816 CA_SEMI_OPEN = 1
6180 00:26:56.856695 CA_FULL_RATE = 0
6181 00:26:56.860756 DQ_CKDIV4_EN = 0
6182 00:26:56.863301 CA_CKDIV4_EN = 1
6183 00:26:56.863725 CA_PREDIV_EN = 0
6184 00:26:56.866586 PH8_DLY = 0
6185 00:26:56.869768 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6186 00:26:56.873540 DQ_AAMCK_DIV = 0
6187 00:26:56.876803 CA_AAMCK_DIV = 0
6188 00:26:56.879865 CA_ADMCK_DIV = 4
6189 00:26:56.880298 DQ_TRACK_CA_EN = 0
6190 00:26:56.883027 CA_PICK = 800
6191 00:26:56.886658 CA_MCKIO = 400
6192 00:26:56.889901 MCKIO_SEMI = 400
6193 00:26:56.893263 PLL_FREQ = 3016
6194 00:26:56.896332 DQ_UI_PI_RATIO = 32
6195 00:26:56.899636 CA_UI_PI_RATIO = 32
6196 00:26:56.903053 ===================================
6197 00:26:56.905949 ===================================
6198 00:26:56.909196 memory_type:LPDDR4
6199 00:26:56.909902 GP_NUM : 10
6200 00:26:56.912586 SRAM_EN : 1
6201 00:26:56.913043 MD32_EN : 0
6202 00:26:56.916086 ===================================
6203 00:26:56.919349 [ANA_INIT] >>>>>>>>>>>>>>
6204 00:26:56.922842 <<<<<< [CONFIGURE PHASE]: ANA_TX
6205 00:26:56.925712 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6206 00:26:56.929655 ===================================
6207 00:26:56.932929 data_rate = 800,PCW = 0X7400
6208 00:26:56.936310 ===================================
6209 00:26:56.939742 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6210 00:26:56.942520 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6211 00:26:56.955584 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6212 00:26:56.959450 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6213 00:26:56.962426 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6214 00:26:56.965509 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6215 00:26:56.968721 [ANA_INIT] flow start
6216 00:26:56.971886 [ANA_INIT] PLL >>>>>>>>
6217 00:26:56.972308 [ANA_INIT] PLL <<<<<<<<
6218 00:26:56.975274 [ANA_INIT] MIDPI >>>>>>>>
6219 00:26:56.978649 [ANA_INIT] MIDPI <<<<<<<<
6220 00:26:56.982379 [ANA_INIT] DLL >>>>>>>>
6221 00:26:56.983055 [ANA_INIT] flow end
6222 00:26:56.985451 ============ LP4 DIFF to SE enter ============
6223 00:26:56.992012 ============ LP4 DIFF to SE exit ============
6224 00:26:56.992602 [ANA_INIT] <<<<<<<<<<<<<
6225 00:26:56.995439 [Flow] Enable top DCM control >>>>>
6226 00:26:56.998753 [Flow] Enable top DCM control <<<<<
6227 00:26:57.001884 Enable DLL master slave shuffle
6228 00:26:57.008641 ==============================================================
6229 00:26:57.009231 Gating Mode config
6230 00:26:57.015006 ==============================================================
6231 00:26:57.018746 Config description:
6232 00:26:57.028568 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6233 00:26:57.034973 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6234 00:26:57.038334 SELPH_MODE 0: By rank 1: By Phase
6235 00:26:57.045195 ==============================================================
6236 00:26:57.048268 GAT_TRACK_EN = 0
6237 00:26:57.051106 RX_GATING_MODE = 2
6238 00:26:57.054456 RX_GATING_TRACK_MODE = 2
6239 00:26:57.054942 SELPH_MODE = 1
6240 00:26:57.057961 PICG_EARLY_EN = 1
6241 00:26:57.061404 VALID_LAT_VALUE = 1
6242 00:26:57.067745 ==============================================================
6243 00:26:57.071116 Enter into Gating configuration >>>>
6244 00:26:57.074245 Exit from Gating configuration <<<<
6245 00:26:57.077450 Enter into DVFS_PRE_config >>>>>
6246 00:26:57.087643 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6247 00:26:57.090640 Exit from DVFS_PRE_config <<<<<
6248 00:26:57.094113 Enter into PICG configuration >>>>
6249 00:26:57.097213 Exit from PICG configuration <<<<
6250 00:26:57.100840 [RX_INPUT] configuration >>>>>
6251 00:26:57.104004 [RX_INPUT] configuration <<<<<
6252 00:26:57.106983 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6253 00:26:57.113864 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6254 00:26:57.120628 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6255 00:26:57.127245 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6256 00:26:57.133870 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6257 00:26:57.137452 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6258 00:26:57.143740 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6259 00:26:57.146827 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6260 00:26:57.150132 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6261 00:26:57.153833 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6262 00:26:57.160349 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6263 00:26:57.163786 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6264 00:26:57.166915 ===================================
6265 00:26:57.170636 LPDDR4 DRAM CONFIGURATION
6266 00:26:57.173750 ===================================
6267 00:26:57.174354 EX_ROW_EN[0] = 0x0
6268 00:26:57.176738 EX_ROW_EN[1] = 0x0
6269 00:26:57.177208 LP4Y_EN = 0x0
6270 00:26:57.180251 WORK_FSP = 0x0
6271 00:26:57.180824 WL = 0x2
6272 00:26:57.183720 RL = 0x2
6273 00:26:57.186988 BL = 0x2
6274 00:26:57.187454 RPST = 0x0
6275 00:26:57.189727 RD_PRE = 0x0
6276 00:26:57.190232 WR_PRE = 0x1
6277 00:26:57.193709 WR_PST = 0x0
6278 00:26:57.194482 DBI_WR = 0x0
6279 00:26:57.196459 DBI_RD = 0x0
6280 00:26:57.196923 OTF = 0x1
6281 00:26:57.200015 ===================================
6282 00:26:57.203527 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6283 00:26:57.210318 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6284 00:26:57.213316 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6285 00:26:57.216415 ===================================
6286 00:26:57.219482 LPDDR4 DRAM CONFIGURATION
6287 00:26:57.223052 ===================================
6288 00:26:57.223522 EX_ROW_EN[0] = 0x10
6289 00:26:57.226492 EX_ROW_EN[1] = 0x0
6290 00:26:57.227059 LP4Y_EN = 0x0
6291 00:26:57.229692 WORK_FSP = 0x0
6292 00:26:57.230280 WL = 0x2
6293 00:26:57.233067 RL = 0x2
6294 00:26:57.236545 BL = 0x2
6295 00:26:57.237345 RPST = 0x0
6296 00:26:57.239602 RD_PRE = 0x0
6297 00:26:57.240073 WR_PRE = 0x1
6298 00:26:57.243112 WR_PST = 0x0
6299 00:26:57.243681 DBI_WR = 0x0
6300 00:26:57.245964 DBI_RD = 0x0
6301 00:26:57.246549 OTF = 0x1
6302 00:26:57.249393 ===================================
6303 00:26:57.256079 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6304 00:26:57.260492 nWR fixed to 30
6305 00:26:57.263290 [ModeRegInit_LP4] CH0 RK0
6306 00:26:57.263779 [ModeRegInit_LP4] CH0 RK1
6307 00:26:57.266694 [ModeRegInit_LP4] CH1 RK0
6308 00:26:57.270089 [ModeRegInit_LP4] CH1 RK1
6309 00:26:57.270749 match AC timing 19
6310 00:26:57.276720 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6311 00:26:57.279605 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6312 00:26:57.282813 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6313 00:26:57.289307 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6314 00:26:57.293109 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6315 00:26:57.293671 ==
6316 00:26:57.295938 Dram Type= 6, Freq= 0, CH_0, rank 0
6317 00:26:57.299307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6318 00:26:57.302234 ==
6319 00:26:57.305904 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6320 00:26:57.312330 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6321 00:26:57.315541 [CA 0] Center 36 (8~64) winsize 57
6322 00:26:57.319035 [CA 1] Center 36 (8~64) winsize 57
6323 00:26:57.321984 [CA 2] Center 36 (8~64) winsize 57
6324 00:26:57.325131 [CA 3] Center 36 (8~64) winsize 57
6325 00:26:57.328480 [CA 4] Center 36 (8~64) winsize 57
6326 00:26:57.332016 [CA 5] Center 36 (8~64) winsize 57
6327 00:26:57.332598
6328 00:26:57.335076 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6329 00:26:57.335604
6330 00:26:57.338645 [CATrainingPosCal] consider 1 rank data
6331 00:26:57.341812 u2DelayCellTimex100 = 270/100 ps
6332 00:26:57.345296 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6333 00:26:57.348304 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6334 00:26:57.352136 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6335 00:26:57.355023 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6336 00:26:57.358110 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6337 00:26:57.361387 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6338 00:26:57.365157
6339 00:26:57.368381 CA PerBit enable=1, Macro0, CA PI delay=36
6340 00:26:57.368907
6341 00:26:57.371824 [CBTSetCACLKResult] CA Dly = 36
6342 00:26:57.372243 CS Dly: 1 (0~32)
6343 00:26:57.372580 ==
6344 00:26:57.374735 Dram Type= 6, Freq= 0, CH_0, rank 1
6345 00:26:57.378382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6346 00:26:57.378891 ==
6347 00:26:57.384867 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6348 00:26:57.391352 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6349 00:26:57.394914 [CA 0] Center 36 (8~64) winsize 57
6350 00:26:57.398024 [CA 1] Center 36 (8~64) winsize 57
6351 00:26:57.401586 [CA 2] Center 36 (8~64) winsize 57
6352 00:26:57.404464 [CA 3] Center 36 (8~64) winsize 57
6353 00:26:57.408197 [CA 4] Center 36 (8~64) winsize 57
6354 00:26:57.411511 [CA 5] Center 36 (8~64) winsize 57
6355 00:26:57.411945
6356 00:26:57.414489 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6357 00:26:57.414924
6358 00:26:57.418072 [CATrainingPosCal] consider 2 rank data
6359 00:26:57.421466 u2DelayCellTimex100 = 270/100 ps
6360 00:26:57.424847 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6361 00:26:57.428102 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6362 00:26:57.430897 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6363 00:26:57.434017 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6364 00:26:57.437933 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6365 00:26:57.440659 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6366 00:26:57.441274
6367 00:26:57.447336 CA PerBit enable=1, Macro0, CA PI delay=36
6368 00:26:57.447757
6369 00:26:57.448090 [CBTSetCACLKResult] CA Dly = 36
6370 00:26:57.450500 CS Dly: 1 (0~32)
6371 00:26:57.450925
6372 00:26:57.453825 ----->DramcWriteLeveling(PI) begin...
6373 00:26:57.454295 ==
6374 00:26:57.457363 Dram Type= 6, Freq= 0, CH_0, rank 0
6375 00:26:57.460759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6376 00:26:57.461303 ==
6377 00:26:57.463828 Write leveling (Byte 0): 40 => 8
6378 00:26:57.467103 Write leveling (Byte 1): 32 => 0
6379 00:26:57.470371 DramcWriteLeveling(PI) end<-----
6380 00:26:57.470794
6381 00:26:57.471133 ==
6382 00:26:57.473429 Dram Type= 6, Freq= 0, CH_0, rank 0
6383 00:26:57.476822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6384 00:26:57.480398 ==
6385 00:26:57.480830 [Gating] SW mode calibration
6386 00:26:57.490220 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6387 00:26:57.493462 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6388 00:26:57.496927 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6389 00:26:57.503190 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6390 00:26:57.506492 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6391 00:26:57.510130 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6392 00:26:57.516318 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6393 00:26:57.519788 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6394 00:26:57.523106 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6395 00:26:57.529629 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6396 00:26:57.533093 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6397 00:26:57.536243 Total UI for P1: 0, mck2ui 16
6398 00:26:57.539961 best dqsien dly found for B0: ( 0, 14, 24)
6399 00:26:57.542962 Total UI for P1: 0, mck2ui 16
6400 00:26:57.546130 best dqsien dly found for B1: ( 0, 14, 24)
6401 00:26:57.549525 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6402 00:26:57.552806 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6403 00:26:57.553277
6404 00:26:57.556158 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6405 00:26:57.562515 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6406 00:26:57.563066 [Gating] SW calibration Done
6407 00:26:57.563611 ==
6408 00:26:57.565744 Dram Type= 6, Freq= 0, CH_0, rank 0
6409 00:26:57.572263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6410 00:26:57.572568 ==
6411 00:26:57.572807 RX Vref Scan: 0
6412 00:26:57.573030
6413 00:26:57.575909 RX Vref 0 -> 0, step: 1
6414 00:26:57.576273
6415 00:26:57.578839 RX Delay -410 -> 252, step: 16
6416 00:26:57.582086 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6417 00:26:57.585090 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6418 00:26:57.592308 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6419 00:26:57.595074 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6420 00:26:57.598510 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6421 00:26:57.601700 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6422 00:26:57.608157 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6423 00:26:57.611845 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6424 00:26:57.615031 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6425 00:26:57.618039 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6426 00:26:57.624995 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6427 00:26:57.628434 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6428 00:26:57.631363 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6429 00:26:57.637873 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6430 00:26:57.641048 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6431 00:26:57.644571 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6432 00:26:57.644655 ==
6433 00:26:57.647890 Dram Type= 6, Freq= 0, CH_0, rank 0
6434 00:26:57.651187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6435 00:26:57.654648 ==
6436 00:26:57.654731 DQS Delay:
6437 00:26:57.654797 DQS0 = 43, DQS1 = 59
6438 00:26:57.658192 DQM Delay:
6439 00:26:57.658289 DQM0 = 9, DQM1 = 11
6440 00:26:57.660936 DQ Delay:
6441 00:26:57.661020 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =0
6442 00:26:57.664342 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6443 00:26:57.667446 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6444 00:26:57.670761 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6445 00:26:57.670860
6446 00:26:57.670926
6447 00:26:57.674455 ==
6448 00:26:57.677731 Dram Type= 6, Freq= 0, CH_0, rank 0
6449 00:26:57.681049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6450 00:26:57.681133 ==
6451 00:26:57.681200
6452 00:26:57.681260
6453 00:26:57.683831 TX Vref Scan disable
6454 00:26:57.683914 == TX Byte 0 ==
6455 00:26:57.687317 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6456 00:26:57.693745 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6457 00:26:57.693830 == TX Byte 1 ==
6458 00:26:57.697442 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6459 00:26:57.703988 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6460 00:26:57.704077 ==
6461 00:26:57.707216 Dram Type= 6, Freq= 0, CH_0, rank 0
6462 00:26:57.710365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6463 00:26:57.710450 ==
6464 00:26:57.710516
6465 00:26:57.710577
6466 00:26:57.713815 TX Vref Scan disable
6467 00:26:57.713936 == TX Byte 0 ==
6468 00:26:57.720777 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6469 00:26:57.723879 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6470 00:26:57.723964 == TX Byte 1 ==
6471 00:26:57.730418 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6472 00:26:57.733749 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6473 00:26:57.733838
6474 00:26:57.733903 [DATLAT]
6475 00:26:57.737174 Freq=400, CH0 RK0
6476 00:26:57.737258
6477 00:26:57.737324 DATLAT Default: 0xf
6478 00:26:57.740064 0, 0xFFFF, sum = 0
6479 00:26:57.740149 1, 0xFFFF, sum = 0
6480 00:26:57.743345 2, 0xFFFF, sum = 0
6481 00:26:57.743430 3, 0xFFFF, sum = 0
6482 00:26:57.747051 4, 0xFFFF, sum = 0
6483 00:26:57.747137 5, 0xFFFF, sum = 0
6484 00:26:57.750128 6, 0xFFFF, sum = 0
6485 00:26:57.750251 7, 0xFFFF, sum = 0
6486 00:26:57.753802 8, 0xFFFF, sum = 0
6487 00:26:57.753888 9, 0xFFFF, sum = 0
6488 00:26:57.757119 10, 0xFFFF, sum = 0
6489 00:26:57.757203 11, 0xFFFF, sum = 0
6490 00:26:57.760161 12, 0xFFFF, sum = 0
6491 00:26:57.760245 13, 0x0, sum = 1
6492 00:26:57.763726 14, 0x0, sum = 2
6493 00:26:57.763811 15, 0x0, sum = 3
6494 00:26:57.766876 16, 0x0, sum = 4
6495 00:26:57.766960 best_step = 14
6496 00:26:57.767025
6497 00:26:57.767086 ==
6498 00:26:57.769791 Dram Type= 6, Freq= 0, CH_0, rank 0
6499 00:26:57.776439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6500 00:26:57.776524 ==
6501 00:26:57.776590 RX Vref Scan: 1
6502 00:26:57.776650
6503 00:26:57.780042 RX Vref 0 -> 0, step: 1
6504 00:26:57.780125
6505 00:26:57.783197 RX Delay -359 -> 252, step: 8
6506 00:26:57.783280
6507 00:26:57.786634 Set Vref, RX VrefLevel [Byte0]: 58
6508 00:26:57.790083 [Byte1]: 58
6509 00:26:57.793321
6510 00:26:57.793403 Final RX Vref Byte 0 = 58 to rank0
6511 00:26:57.796503 Final RX Vref Byte 1 = 58 to rank0
6512 00:26:57.800273 Final RX Vref Byte 0 = 58 to rank1
6513 00:26:57.803053 Final RX Vref Byte 1 = 58 to rank1==
6514 00:26:57.806723 Dram Type= 6, Freq= 0, CH_0, rank 0
6515 00:26:57.813053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6516 00:26:57.813138 ==
6517 00:26:57.813205 DQS Delay:
6518 00:26:57.816333 DQS0 = 48, DQS1 = 60
6519 00:26:57.816416 DQM Delay:
6520 00:26:57.816482 DQM0 = 11, DQM1 = 10
6521 00:26:57.819514 DQ Delay:
6522 00:26:57.822926 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6523 00:26:57.826507 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6524 00:26:57.826591 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6525 00:26:57.833081 DQ12 =16, DQ13 =12, DQ14 =20, DQ15 =20
6526 00:26:57.833164
6527 00:26:57.833231
6528 00:26:57.839658 [DQSOSCAuto] RK0, (LSB)MR18= 0xc083, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 386 ps
6529 00:26:57.842718 CH0 RK0: MR19=C0C, MR18=C083
6530 00:26:57.849478 CH0_RK0: MR19=0xC0C, MR18=0xC083, DQSOSC=386, MR23=63, INC=396, DEC=264
6531 00:26:57.849567 ==
6532 00:26:57.852629 Dram Type= 6, Freq= 0, CH_0, rank 1
6533 00:26:57.855890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6534 00:26:57.855974 ==
6535 00:26:57.859170 [Gating] SW mode calibration
6536 00:26:57.865763 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6537 00:26:57.872456 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6538 00:26:57.876013 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6539 00:26:57.879204 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6540 00:26:57.885841 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6541 00:26:57.889098 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6542 00:26:57.892393 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6543 00:26:57.898796 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6544 00:26:57.902077 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6545 00:26:57.905337 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6546 00:26:57.912161 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6547 00:26:57.915372 Total UI for P1: 0, mck2ui 16
6548 00:26:57.918516 best dqsien dly found for B0: ( 0, 14, 24)
6549 00:26:57.918601 Total UI for P1: 0, mck2ui 16
6550 00:26:57.925229 best dqsien dly found for B1: ( 0, 14, 24)
6551 00:26:57.928553 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6552 00:26:57.931846 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6553 00:26:57.931929
6554 00:26:57.935143 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6555 00:26:57.938350 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6556 00:26:57.941897 [Gating] SW calibration Done
6557 00:26:57.941980 ==
6558 00:26:57.944792 Dram Type= 6, Freq= 0, CH_0, rank 1
6559 00:26:57.948141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6560 00:26:57.948245 ==
6561 00:26:57.951417 RX Vref Scan: 0
6562 00:26:57.951501
6563 00:26:57.954724 RX Vref 0 -> 0, step: 1
6564 00:26:57.954807
6565 00:26:57.954873 RX Delay -410 -> 252, step: 16
6566 00:26:57.961770 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6567 00:26:57.964741 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6568 00:26:57.967981 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6569 00:26:57.974771 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6570 00:26:57.977885 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6571 00:26:57.982027 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6572 00:26:57.984839 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6573 00:26:57.991347 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6574 00:26:57.994492 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6575 00:26:57.997938 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6576 00:26:58.001243 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6577 00:26:58.008006 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6578 00:26:58.011165 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6579 00:26:58.014420 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6580 00:26:58.017735 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6581 00:26:58.024419 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6582 00:26:58.024535 ==
6583 00:26:58.027623 Dram Type= 6, Freq= 0, CH_0, rank 1
6584 00:26:58.031310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6585 00:26:58.031416 ==
6586 00:26:58.031509 DQS Delay:
6587 00:26:58.033968 DQS0 = 43, DQS1 = 59
6588 00:26:58.034126 DQM Delay:
6589 00:26:58.037391 DQM0 = 11, DQM1 = 15
6590 00:26:58.037474 DQ Delay:
6591 00:26:58.040843 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6592 00:26:58.043883 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24
6593 00:26:58.047400 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6594 00:26:58.050906 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6595 00:26:58.050990
6596 00:26:58.051056
6597 00:26:58.051136 ==
6598 00:26:58.054006 Dram Type= 6, Freq= 0, CH_0, rank 1
6599 00:26:58.057111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6600 00:26:58.057195 ==
6601 00:26:58.060370
6602 00:26:58.060452
6603 00:26:58.060517 TX Vref Scan disable
6604 00:26:58.064108 == TX Byte 0 ==
6605 00:26:58.067226 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6606 00:26:58.070129 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6607 00:26:58.073632 == TX Byte 1 ==
6608 00:26:58.076808 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6609 00:26:58.080196 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6610 00:26:58.080287 ==
6611 00:26:58.083842 Dram Type= 6, Freq= 0, CH_0, rank 1
6612 00:26:58.086858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6613 00:26:58.090114 ==
6614 00:26:58.090235
6615 00:26:58.090302
6616 00:26:58.090363 TX Vref Scan disable
6617 00:26:58.093296 == TX Byte 0 ==
6618 00:26:58.096436 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6619 00:26:58.099832 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6620 00:26:58.103280 == TX Byte 1 ==
6621 00:26:58.106717 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6622 00:26:58.109950 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6623 00:26:58.110035
6624 00:26:58.112876 [DATLAT]
6625 00:26:58.112959 Freq=400, CH0 RK1
6626 00:26:58.113025
6627 00:26:58.116063 DATLAT Default: 0xe
6628 00:26:58.116146 0, 0xFFFF, sum = 0
6629 00:26:58.119323 1, 0xFFFF, sum = 0
6630 00:26:58.119407 2, 0xFFFF, sum = 0
6631 00:26:58.123253 3, 0xFFFF, sum = 0
6632 00:26:58.123337 4, 0xFFFF, sum = 0
6633 00:26:58.126123 5, 0xFFFF, sum = 0
6634 00:26:58.126278 6, 0xFFFF, sum = 0
6635 00:26:58.129282 7, 0xFFFF, sum = 0
6636 00:26:58.129385 8, 0xFFFF, sum = 0
6637 00:26:58.132710 9, 0xFFFF, sum = 0
6638 00:26:58.135999 10, 0xFFFF, sum = 0
6639 00:26:58.136084 11, 0xFFFF, sum = 0
6640 00:26:58.139279 12, 0xFFFF, sum = 0
6641 00:26:58.139363 13, 0x0, sum = 1
6642 00:26:58.142470 14, 0x0, sum = 2
6643 00:26:58.142555 15, 0x0, sum = 3
6644 00:26:58.145770 16, 0x0, sum = 4
6645 00:26:58.145854 best_step = 14
6646 00:26:58.145985
6647 00:26:58.146087 ==
6648 00:26:58.149349 Dram Type= 6, Freq= 0, CH_0, rank 1
6649 00:26:58.152326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6650 00:26:58.152428 ==
6651 00:26:58.155639 RX Vref Scan: 0
6652 00:26:58.155721
6653 00:26:58.159388 RX Vref 0 -> 0, step: 1
6654 00:26:58.159471
6655 00:26:58.159536 RX Delay -359 -> 252, step: 8
6656 00:26:58.167992 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6657 00:26:58.171232 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6658 00:26:58.174342 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6659 00:26:58.181120 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6660 00:26:58.184255 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6661 00:26:58.187585 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6662 00:26:58.190983 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6663 00:26:58.197759 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6664 00:26:58.200917 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6665 00:26:58.204411 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6666 00:26:58.207613 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6667 00:26:58.213868 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6668 00:26:58.217325 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6669 00:26:58.220755 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6670 00:26:58.223930 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6671 00:26:58.230745 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6672 00:26:58.230870 ==
6673 00:26:58.233952 Dram Type= 6, Freq= 0, CH_0, rank 1
6674 00:26:58.237228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6675 00:26:58.237313 ==
6676 00:26:58.237378 DQS Delay:
6677 00:26:58.240588 DQS0 = 44, DQS1 = 60
6678 00:26:58.240672 DQM Delay:
6679 00:26:58.243687 DQM0 = 7, DQM1 = 14
6680 00:26:58.243782 DQ Delay:
6681 00:26:58.247125 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =4
6682 00:26:58.250453 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6683 00:26:58.253611 DQ8 =4, DQ9 =0, DQ10 =20, DQ11 =8
6684 00:26:58.257171 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6685 00:26:58.257254
6686 00:26:58.257319
6687 00:26:58.263513 [DQSOSCAuto] RK1, (LSB)MR18= 0xb03e, (MSB)MR19= 0xc0c, tDQSOscB0 = 402 ps tDQSOscB1 = 387 ps
6688 00:26:58.266709 CH0 RK1: MR19=C0C, MR18=B03E
6689 00:26:58.273651 CH0_RK1: MR19=0xC0C, MR18=0xB03E, DQSOSC=387, MR23=63, INC=394, DEC=262
6690 00:26:58.276922 [RxdqsGatingPostProcess] freq 400
6691 00:26:58.284024 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6692 00:26:58.286601 best DQS0 dly(2T, 0.5T) = (0, 10)
6693 00:26:58.286686 best DQS1 dly(2T, 0.5T) = (0, 10)
6694 00:26:58.290157 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6695 00:26:58.293275 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6696 00:26:58.296846 best DQS0 dly(2T, 0.5T) = (0, 10)
6697 00:26:58.299671 best DQS1 dly(2T, 0.5T) = (0, 10)
6698 00:26:58.303078 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6699 00:26:58.306732 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6700 00:26:58.309629 Pre-setting of DQS Precalculation
6701 00:26:58.316155 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6702 00:26:58.316245 ==
6703 00:26:58.319515 Dram Type= 6, Freq= 0, CH_1, rank 0
6704 00:26:58.322882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6705 00:26:58.322967 ==
6706 00:26:58.329311 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6707 00:26:58.336094 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6708 00:26:58.339476 [CA 0] Center 36 (8~64) winsize 57
6709 00:26:58.339563 [CA 1] Center 36 (8~64) winsize 57
6710 00:26:58.342716 [CA 2] Center 36 (8~64) winsize 57
6711 00:26:58.346074 [CA 3] Center 36 (8~64) winsize 57
6712 00:26:58.349076 [CA 4] Center 36 (8~64) winsize 57
6713 00:26:58.352343 [CA 5] Center 36 (8~64) winsize 57
6714 00:26:58.352427
6715 00:26:58.355777 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6716 00:26:58.359004
6717 00:26:58.362097 [CATrainingPosCal] consider 1 rank data
6718 00:26:58.362272 u2DelayCellTimex100 = 270/100 ps
6719 00:26:58.368808 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6720 00:26:58.372821 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6721 00:26:58.375542 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6722 00:26:58.378661 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6723 00:26:58.382257 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6724 00:26:58.385423 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6725 00:26:58.385506
6726 00:26:58.388769 CA PerBit enable=1, Macro0, CA PI delay=36
6727 00:26:58.388853
6728 00:26:58.392184 [CBTSetCACLKResult] CA Dly = 36
6729 00:26:58.395285 CS Dly: 1 (0~32)
6730 00:26:58.395367 ==
6731 00:26:58.398812 Dram Type= 6, Freq= 0, CH_1, rank 1
6732 00:26:58.401837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6733 00:26:58.401922 ==
6734 00:26:58.408979 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6735 00:26:58.411694 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6736 00:26:58.415057 [CA 0] Center 36 (8~64) winsize 57
6737 00:26:58.418355 [CA 1] Center 36 (8~64) winsize 57
6738 00:26:58.422092 [CA 2] Center 36 (8~64) winsize 57
6739 00:26:58.424941 [CA 3] Center 36 (8~64) winsize 57
6740 00:26:58.428384 [CA 4] Center 36 (8~64) winsize 57
6741 00:26:58.431934 [CA 5] Center 36 (8~64) winsize 57
6742 00:26:58.432017
6743 00:26:58.434989 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6744 00:26:58.435084
6745 00:26:58.438121 [CATrainingPosCal] consider 2 rank data
6746 00:26:58.441713 u2DelayCellTimex100 = 270/100 ps
6747 00:26:58.444792 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6748 00:26:58.451478 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6749 00:26:58.454873 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6750 00:26:58.458370 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6751 00:26:58.461546 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6752 00:26:58.464599 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6753 00:26:58.464684
6754 00:26:58.467887 CA PerBit enable=1, Macro0, CA PI delay=36
6755 00:26:58.467970
6756 00:26:58.471341 [CBTSetCACLKResult] CA Dly = 36
6757 00:26:58.471426 CS Dly: 1 (0~32)
6758 00:26:58.474745
6759 00:26:58.477656 ----->DramcWriteLeveling(PI) begin...
6760 00:26:58.477740 ==
6761 00:26:58.481506 Dram Type= 6, Freq= 0, CH_1, rank 0
6762 00:26:58.484627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6763 00:26:58.484711 ==
6764 00:26:58.487857 Write leveling (Byte 0): 40 => 8
6765 00:26:58.490916 Write leveling (Byte 1): 40 => 8
6766 00:26:58.494484 DramcWriteLeveling(PI) end<-----
6767 00:26:58.494567
6768 00:26:58.494632 ==
6769 00:26:58.497856 Dram Type= 6, Freq= 0, CH_1, rank 0
6770 00:26:58.500754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6771 00:26:58.500840 ==
6772 00:26:58.504250 [Gating] SW mode calibration
6773 00:26:58.510749 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6774 00:26:58.517326 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6775 00:26:58.520955 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6776 00:26:58.523920 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6777 00:26:58.530628 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6778 00:26:58.533711 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6779 00:26:58.536969 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6780 00:26:58.543809 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6781 00:26:58.546943 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6782 00:26:58.550480 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6783 00:26:58.556734 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6784 00:26:58.556818 Total UI for P1: 0, mck2ui 16
6785 00:26:58.563506 best dqsien dly found for B0: ( 0, 14, 24)
6786 00:26:58.563592 Total UI for P1: 0, mck2ui 16
6787 00:26:58.570086 best dqsien dly found for B1: ( 0, 14, 24)
6788 00:26:58.573513 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6789 00:26:58.576807 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6790 00:26:58.576891
6791 00:26:58.580065 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6792 00:26:58.583243 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6793 00:26:58.586553 [Gating] SW calibration Done
6794 00:26:58.586636 ==
6795 00:26:58.590071 Dram Type= 6, Freq= 0, CH_1, rank 0
6796 00:26:58.592980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6797 00:26:58.593065 ==
6798 00:26:58.596307 RX Vref Scan: 0
6799 00:26:58.596390
6800 00:26:58.599765 RX Vref 0 -> 0, step: 1
6801 00:26:58.599849
6802 00:26:58.599914 RX Delay -410 -> 252, step: 16
6803 00:26:58.606270 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6804 00:26:58.609533 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6805 00:26:58.612942 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6806 00:26:58.619530 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6807 00:26:58.622646 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6808 00:26:58.625972 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6809 00:26:58.629244 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6810 00:26:58.636024 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6811 00:26:58.639169 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6812 00:26:58.642625 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6813 00:26:58.646054 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6814 00:26:58.652366 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6815 00:26:58.655797 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6816 00:26:58.659238 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6817 00:26:58.662474 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6818 00:26:58.668956 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6819 00:26:58.669043 ==
6820 00:26:58.672770 Dram Type= 6, Freq= 0, CH_1, rank 0
6821 00:26:58.675750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6822 00:26:58.675835 ==
6823 00:26:58.675901 DQS Delay:
6824 00:26:58.679061 DQS0 = 43, DQS1 = 51
6825 00:26:58.679144 DQM Delay:
6826 00:26:58.682511 DQM0 = 12, DQM1 = 14
6827 00:26:58.682594 DQ Delay:
6828 00:26:58.685477 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6829 00:26:58.688514 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6830 00:26:58.692086 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6831 00:26:58.695328 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6832 00:26:58.695411
6833 00:26:58.695476
6834 00:26:58.695536 ==
6835 00:26:58.698356 Dram Type= 6, Freq= 0, CH_1, rank 0
6836 00:26:58.702054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6837 00:26:58.702138 ==
6838 00:26:58.704956
6839 00:26:58.705038
6840 00:26:58.705102 TX Vref Scan disable
6841 00:26:58.708332 == TX Byte 0 ==
6842 00:26:58.711568 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6843 00:26:58.715145 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6844 00:26:58.718301 == TX Byte 1 ==
6845 00:26:58.721603 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6846 00:26:58.725369 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6847 00:26:58.725499 ==
6848 00:26:58.728143 Dram Type= 6, Freq= 0, CH_1, rank 0
6849 00:26:58.731895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6850 00:26:58.734620 ==
6851 00:26:58.734703
6852 00:26:58.734767
6853 00:26:58.734830 TX Vref Scan disable
6854 00:26:58.737906 == TX Byte 0 ==
6855 00:26:58.741295 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6856 00:26:58.744516 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6857 00:26:58.747909 == TX Byte 1 ==
6858 00:26:58.751112 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6859 00:26:58.754579 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6860 00:26:58.754662
6861 00:26:58.758129 [DATLAT]
6862 00:26:58.758247 Freq=400, CH1 RK0
6863 00:26:58.758315
6864 00:26:58.761483 DATLAT Default: 0xf
6865 00:26:58.761566 0, 0xFFFF, sum = 0
6866 00:26:58.764314 1, 0xFFFF, sum = 0
6867 00:26:58.764398 2, 0xFFFF, sum = 0
6868 00:26:58.767609 3, 0xFFFF, sum = 0
6869 00:26:58.767693 4, 0xFFFF, sum = 0
6870 00:26:58.770978 5, 0xFFFF, sum = 0
6871 00:26:58.771063 6, 0xFFFF, sum = 0
6872 00:26:58.774476 7, 0xFFFF, sum = 0
6873 00:26:58.774560 8, 0xFFFF, sum = 0
6874 00:26:58.777681 9, 0xFFFF, sum = 0
6875 00:26:58.777765 10, 0xFFFF, sum = 0
6876 00:26:58.780972 11, 0xFFFF, sum = 0
6877 00:26:58.784286 12, 0xFFFF, sum = 0
6878 00:26:58.784370 13, 0x0, sum = 1
6879 00:26:58.784437 14, 0x0, sum = 2
6880 00:26:58.788016 15, 0x0, sum = 3
6881 00:26:58.788100 16, 0x0, sum = 4
6882 00:26:58.790808 best_step = 14
6883 00:26:58.790891
6884 00:26:58.790957 ==
6885 00:26:58.794208 Dram Type= 6, Freq= 0, CH_1, rank 0
6886 00:26:58.797574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6887 00:26:58.797659 ==
6888 00:26:58.800804 RX Vref Scan: 1
6889 00:26:58.800888
6890 00:26:58.800953 RX Vref 0 -> 0, step: 1
6891 00:26:58.801014
6892 00:26:58.804086 RX Delay -343 -> 252, step: 8
6893 00:26:58.804206
6894 00:26:58.807863 Set Vref, RX VrefLevel [Byte0]: 48
6895 00:26:58.810599 [Byte1]: 52
6896 00:26:58.815711
6897 00:26:58.815795 Final RX Vref Byte 0 = 48 to rank0
6898 00:26:58.819291 Final RX Vref Byte 1 = 52 to rank0
6899 00:26:58.822423 Final RX Vref Byte 0 = 48 to rank1
6900 00:26:58.825430 Final RX Vref Byte 1 = 52 to rank1==
6901 00:26:58.828836 Dram Type= 6, Freq= 0, CH_1, rank 0
6902 00:26:58.835435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6903 00:26:58.835523 ==
6904 00:26:58.835589 DQS Delay:
6905 00:26:58.838871 DQS0 = 44, DQS1 = 56
6906 00:26:58.838954 DQM Delay:
6907 00:26:58.839020 DQM0 = 8, DQM1 = 12
6908 00:26:58.842238 DQ Delay:
6909 00:26:58.845320 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6910 00:26:58.845403 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =4
6911 00:26:58.848896 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6912 00:26:58.852305 DQ12 =24, DQ13 =16, DQ14 =20, DQ15 =20
6913 00:26:58.852390
6914 00:26:58.855665
6915 00:26:58.861762 [DQSOSCAuto] RK0, (LSB)MR18= 0x956c, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 391 ps
6916 00:26:58.865050 CH1 RK0: MR19=C0C, MR18=956C
6917 00:26:58.871941 CH1_RK0: MR19=0xC0C, MR18=0x956C, DQSOSC=391, MR23=63, INC=386, DEC=257
6918 00:26:58.872025 ==
6919 00:26:58.874831 Dram Type= 6, Freq= 0, CH_1, rank 1
6920 00:26:58.878325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6921 00:26:58.878410 ==
6922 00:26:58.881742 [Gating] SW mode calibration
6923 00:26:58.888128 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6924 00:26:58.894683 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6925 00:26:58.898022 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6926 00:26:58.901263 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6927 00:26:58.908137 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6928 00:26:58.911240 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6929 00:26:58.914915 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6930 00:26:58.921358 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6931 00:26:58.924360 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6932 00:26:58.927893 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6933 00:26:58.934303 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6934 00:26:58.934386 Total UI for P1: 0, mck2ui 16
6935 00:26:58.941513 best dqsien dly found for B0: ( 0, 14, 24)
6936 00:26:58.941597 Total UI for P1: 0, mck2ui 16
6937 00:26:58.947652 best dqsien dly found for B1: ( 0, 14, 24)
6938 00:26:58.951054 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6939 00:26:58.954581 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6940 00:26:58.954663
6941 00:26:58.957459 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6942 00:26:58.960669 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6943 00:26:58.963843 [Gating] SW calibration Done
6944 00:26:58.963941 ==
6945 00:26:58.967382 Dram Type= 6, Freq= 0, CH_1, rank 1
6946 00:26:58.970882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6947 00:26:58.970991 ==
6948 00:26:58.973811 RX Vref Scan: 0
6949 00:26:58.973894
6950 00:26:58.973958 RX Vref 0 -> 0, step: 1
6951 00:26:58.977063
6952 00:26:58.977145 RX Delay -410 -> 252, step: 16
6953 00:26:58.983869 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6954 00:26:58.986994 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6955 00:26:58.990522 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6956 00:26:58.993759 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6957 00:26:59.000472 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6958 00:26:59.003723 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6959 00:26:59.006835 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6960 00:26:59.010350 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6961 00:26:59.017162 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6962 00:26:59.020280 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6963 00:26:59.023886 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6964 00:26:59.029845 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6965 00:26:59.033428 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6966 00:26:59.036809 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6967 00:26:59.039758 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6968 00:26:59.046690 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6969 00:26:59.046773 ==
6970 00:26:59.049767 Dram Type= 6, Freq= 0, CH_1, rank 1
6971 00:26:59.052980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6972 00:26:59.053063 ==
6973 00:26:59.053129 DQS Delay:
6974 00:26:59.056707 DQS0 = 51, DQS1 = 51
6975 00:26:59.056790 DQM Delay:
6976 00:26:59.059595 DQM0 = 19, DQM1 = 13
6977 00:26:59.059710 DQ Delay:
6978 00:26:59.062910 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6979 00:26:59.066376 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6980 00:26:59.069620 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6981 00:26:59.072993 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6982 00:26:59.073077
6983 00:26:59.073142
6984 00:26:59.073202 ==
6985 00:26:59.076340 Dram Type= 6, Freq= 0, CH_1, rank 1
6986 00:26:59.079366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6987 00:26:59.079450 ==
6988 00:26:59.083122
6989 00:26:59.083205
6990 00:26:59.083270 TX Vref Scan disable
6991 00:26:59.086365 == TX Byte 0 ==
6992 00:26:59.089688 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6993 00:26:59.092801 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6994 00:26:59.096010 == TX Byte 1 ==
6995 00:26:59.099271 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6996 00:26:59.102551 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6997 00:26:59.102637 ==
6998 00:26:59.105907 Dram Type= 6, Freq= 0, CH_1, rank 1
6999 00:26:59.109271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7000 00:26:59.112693 ==
7001 00:26:59.112776
7002 00:26:59.112840
7003 00:26:59.112900 TX Vref Scan disable
7004 00:26:59.115803 == TX Byte 0 ==
7005 00:26:59.119147 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
7006 00:26:59.122407 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
7007 00:26:59.125987 == TX Byte 1 ==
7008 00:26:59.128929 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
7009 00:26:59.132869 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
7010 00:26:59.132957
7011 00:26:59.135966 [DATLAT]
7012 00:26:59.136047 Freq=400, CH1 RK1
7013 00:26:59.136114
7014 00:26:59.139141 DATLAT Default: 0xe
7015 00:26:59.139224 0, 0xFFFF, sum = 0
7016 00:26:59.142489 1, 0xFFFF, sum = 0
7017 00:26:59.142574 2, 0xFFFF, sum = 0
7018 00:26:59.145569 3, 0xFFFF, sum = 0
7019 00:26:59.145653 4, 0xFFFF, sum = 0
7020 00:26:59.149076 5, 0xFFFF, sum = 0
7021 00:26:59.149161 6, 0xFFFF, sum = 0
7022 00:26:59.152501 7, 0xFFFF, sum = 0
7023 00:26:59.152587 8, 0xFFFF, sum = 0
7024 00:26:59.155507 9, 0xFFFF, sum = 0
7025 00:26:59.155592 10, 0xFFFF, sum = 0
7026 00:26:59.158706 11, 0xFFFF, sum = 0
7027 00:26:59.158791 12, 0xFFFF, sum = 0
7028 00:26:59.162525 13, 0x0, sum = 1
7029 00:26:59.162610 14, 0x0, sum = 2
7030 00:26:59.165403 15, 0x0, sum = 3
7031 00:26:59.165487 16, 0x0, sum = 4
7032 00:26:59.168549 best_step = 14
7033 00:26:59.168633
7034 00:26:59.168698 ==
7035 00:26:59.171758 Dram Type= 6, Freq= 0, CH_1, rank 1
7036 00:26:59.175202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7037 00:26:59.175287 ==
7038 00:26:59.178149 RX Vref Scan: 0
7039 00:26:59.178270
7040 00:26:59.178336 RX Vref 0 -> 0, step: 1
7041 00:26:59.181826
7042 00:26:59.181908 RX Delay -343 -> 252, step: 8
7043 00:26:59.189892 iDelay=225, Bit 0, Center -32 (-271 ~ 208) 480
7044 00:26:59.193511 iDelay=225, Bit 1, Center -44 (-287 ~ 200) 488
7045 00:26:59.197043 iDelay=225, Bit 2, Center -48 (-287 ~ 192) 480
7046 00:26:59.203573 iDelay=225, Bit 3, Center -40 (-279 ~ 200) 480
7047 00:26:59.206613 iDelay=225, Bit 4, Center -40 (-287 ~ 208) 496
7048 00:26:59.209824 iDelay=225, Bit 5, Center -28 (-271 ~ 216) 488
7049 00:26:59.213117 iDelay=225, Bit 6, Center -24 (-271 ~ 224) 496
7050 00:26:59.219694 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
7051 00:26:59.223004 iDelay=225, Bit 8, Center -56 (-303 ~ 192) 496
7052 00:26:59.226285 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
7053 00:26:59.230148 iDelay=225, Bit 10, Center -48 (-295 ~ 200) 496
7054 00:26:59.235990 iDelay=225, Bit 11, Center -52 (-295 ~ 192) 488
7055 00:26:59.239266 iDelay=225, Bit 12, Center -36 (-287 ~ 216) 504
7056 00:26:59.243164 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
7057 00:26:59.246064 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
7058 00:26:59.252741 iDelay=225, Bit 15, Center -36 (-287 ~ 216) 504
7059 00:26:59.252826 ==
7060 00:26:59.255970 Dram Type= 6, Freq= 0, CH_1, rank 1
7061 00:26:59.259913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7062 00:26:59.259999 ==
7063 00:26:59.260065 DQS Delay:
7064 00:26:59.262736 DQS0 = 48, DQS1 = 56
7065 00:26:59.262819 DQM Delay:
7066 00:26:59.266289 DQM0 = 11, DQM1 = 10
7067 00:26:59.266371 DQ Delay:
7068 00:26:59.269485 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
7069 00:26:59.272523 DQ4 =8, DQ5 =20, DQ6 =24, DQ7 =8
7070 00:26:59.275662 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
7071 00:26:59.279325 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
7072 00:26:59.279434
7073 00:26:59.279528
7074 00:26:59.285874 [DQSOSCAuto] RK1, (LSB)MR18= 0x6554, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 397 ps
7075 00:26:59.289092 CH1 RK1: MR19=C0C, MR18=6554
7076 00:26:59.295948 CH1_RK1: MR19=0xC0C, MR18=0x6554, DQSOSC=397, MR23=63, INC=374, DEC=249
7077 00:26:59.298987 [RxdqsGatingPostProcess] freq 400
7078 00:26:59.305412 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7079 00:26:59.308823 best DQS0 dly(2T, 0.5T) = (0, 10)
7080 00:26:59.312246 best DQS1 dly(2T, 0.5T) = (0, 10)
7081 00:26:59.315203 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7082 00:26:59.318519 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7083 00:26:59.321781 best DQS0 dly(2T, 0.5T) = (0, 10)
7084 00:26:59.321863 best DQS1 dly(2T, 0.5T) = (0, 10)
7085 00:26:59.325177 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7086 00:26:59.328511 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7087 00:26:59.332210 Pre-setting of DQS Precalculation
7088 00:26:59.338436 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7089 00:26:59.345198 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7090 00:26:59.351649 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7091 00:26:59.351765
7092 00:26:59.351861
7093 00:26:59.354636 [Calibration Summary] 800 Mbps
7094 00:26:59.358143 CH 0, Rank 0
7095 00:26:59.358250 SW Impedance : PASS
7096 00:26:59.361626 DUTY Scan : NO K
7097 00:26:59.364498 ZQ Calibration : PASS
7098 00:26:59.364600 Jitter Meter : NO K
7099 00:26:59.368380 CBT Training : PASS
7100 00:26:59.368489 Write leveling : PASS
7101 00:26:59.371200 RX DQS gating : PASS
7102 00:26:59.374663 RX DQ/DQS(RDDQC) : PASS
7103 00:26:59.374747 TX DQ/DQS : PASS
7104 00:26:59.377830 RX DATLAT : PASS
7105 00:26:59.380979 RX DQ/DQS(Engine): PASS
7106 00:26:59.381088 TX OE : NO K
7107 00:26:59.384463 All Pass.
7108 00:26:59.384545
7109 00:26:59.384611 CH 0, Rank 1
7110 00:26:59.387542 SW Impedance : PASS
7111 00:26:59.387625 DUTY Scan : NO K
7112 00:26:59.391007 ZQ Calibration : PASS
7113 00:26:59.394499 Jitter Meter : NO K
7114 00:26:59.394607 CBT Training : PASS
7115 00:26:59.397738 Write leveling : NO K
7116 00:26:59.401040 RX DQS gating : PASS
7117 00:26:59.401124 RX DQ/DQS(RDDQC) : PASS
7118 00:26:59.404307 TX DQ/DQS : PASS
7119 00:26:59.407273 RX DATLAT : PASS
7120 00:26:59.407372 RX DQ/DQS(Engine): PASS
7121 00:26:59.411250 TX OE : NO K
7122 00:26:59.411332 All Pass.
7123 00:26:59.411398
7124 00:26:59.414011 CH 1, Rank 0
7125 00:26:59.414094 SW Impedance : PASS
7126 00:26:59.417715 DUTY Scan : NO K
7127 00:26:59.421060 ZQ Calibration : PASS
7128 00:26:59.421142 Jitter Meter : NO K
7129 00:26:59.424283 CBT Training : PASS
7130 00:26:59.427785 Write leveling : PASS
7131 00:26:59.427868 RX DQS gating : PASS
7132 00:26:59.430678 RX DQ/DQS(RDDQC) : PASS
7133 00:26:59.430762 TX DQ/DQS : PASS
7134 00:26:59.434275 RX DATLAT : PASS
7135 00:26:59.437222 RX DQ/DQS(Engine): PASS
7136 00:26:59.437304 TX OE : NO K
7137 00:26:59.440455 All Pass.
7138 00:26:59.440562
7139 00:26:59.440655 CH 1, Rank 1
7140 00:26:59.444127 SW Impedance : PASS
7141 00:26:59.444210 DUTY Scan : NO K
7142 00:26:59.447193 ZQ Calibration : PASS
7143 00:26:59.451052 Jitter Meter : NO K
7144 00:26:59.451135 CBT Training : PASS
7145 00:26:59.453859 Write leveling : NO K
7146 00:26:59.457131 RX DQS gating : PASS
7147 00:26:59.457214 RX DQ/DQS(RDDQC) : PASS
7148 00:26:59.460215 TX DQ/DQS : PASS
7149 00:26:59.463812 RX DATLAT : PASS
7150 00:26:59.463895 RX DQ/DQS(Engine): PASS
7151 00:26:59.467134 TX OE : NO K
7152 00:26:59.467218 All Pass.
7153 00:26:59.467284
7154 00:26:59.470293 DramC Write-DBI off
7155 00:26:59.473476 PER_BANK_REFRESH: Hybrid Mode
7156 00:26:59.473558 TX_TRACKING: ON
7157 00:26:59.483499 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7158 00:26:59.486905 [FAST_K] Save calibration result to emmc
7159 00:26:59.490521 dramc_set_vcore_voltage set vcore to 725000
7160 00:26:59.493358 Read voltage for 1600, 0
7161 00:26:59.493441 Vio18 = 0
7162 00:26:59.493506 Vcore = 725000
7163 00:26:59.496698 Vdram = 0
7164 00:26:59.496780 Vddq = 0
7165 00:26:59.496845 Vmddr = 0
7166 00:26:59.503468 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7167 00:26:59.506889 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7168 00:26:59.510082 MEM_TYPE=3, freq_sel=13
7169 00:26:59.513448 sv_algorithm_assistance_LP4_3733
7170 00:26:59.516723 ============ PULL DRAM RESETB DOWN ============
7171 00:26:59.523608 ========== PULL DRAM RESETB DOWN end =========
7172 00:26:59.526504 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7173 00:26:59.529964 ===================================
7174 00:26:59.533025 LPDDR4 DRAM CONFIGURATION
7175 00:26:59.536916 ===================================
7176 00:26:59.536998 EX_ROW_EN[0] = 0x0
7177 00:26:59.539611 EX_ROW_EN[1] = 0x0
7178 00:26:59.539693 LP4Y_EN = 0x0
7179 00:26:59.542881 WORK_FSP = 0x1
7180 00:26:59.542963 WL = 0x5
7181 00:26:59.546472 RL = 0x5
7182 00:26:59.546554 BL = 0x2
7183 00:26:59.549806 RPST = 0x0
7184 00:26:59.549887 RD_PRE = 0x0
7185 00:26:59.553276 WR_PRE = 0x1
7186 00:26:59.556267 WR_PST = 0x1
7187 00:26:59.556349 DBI_WR = 0x0
7188 00:26:59.559514 DBI_RD = 0x0
7189 00:26:59.559597 OTF = 0x1
7190 00:26:59.562756 ===================================
7191 00:26:59.566399 ===================================
7192 00:26:59.569237 ANA top config
7193 00:26:59.572813 ===================================
7194 00:26:59.572896 DLL_ASYNC_EN = 0
7195 00:26:59.576294 ALL_SLAVE_EN = 0
7196 00:26:59.579067 NEW_RANK_MODE = 1
7197 00:26:59.582387 DLL_IDLE_MODE = 1
7198 00:26:59.582469 LP45_APHY_COMB_EN = 1
7199 00:26:59.585731 TX_ODT_DIS = 0
7200 00:26:59.589025 NEW_8X_MODE = 1
7201 00:26:59.592680 ===================================
7202 00:26:59.595984 ===================================
7203 00:26:59.599129 data_rate = 3200
7204 00:26:59.602104 CKR = 1
7205 00:26:59.605287 DQ_P2S_RATIO = 8
7206 00:26:59.608773 ===================================
7207 00:26:59.608856 CA_P2S_RATIO = 8
7208 00:26:59.612380 DQ_CA_OPEN = 0
7209 00:26:59.615352 DQ_SEMI_OPEN = 0
7210 00:26:59.619058 CA_SEMI_OPEN = 0
7211 00:26:59.622127 CA_FULL_RATE = 0
7212 00:26:59.625493 DQ_CKDIV4_EN = 0
7213 00:26:59.625575 CA_CKDIV4_EN = 0
7214 00:26:59.628505 CA_PREDIV_EN = 0
7215 00:26:59.632015 PH8_DLY = 12
7216 00:26:59.635312 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7217 00:26:59.638746 DQ_AAMCK_DIV = 4
7218 00:26:59.641948 CA_AAMCK_DIV = 4
7219 00:26:59.645373 CA_ADMCK_DIV = 4
7220 00:26:59.645456 DQ_TRACK_CA_EN = 0
7221 00:26:59.648447 CA_PICK = 1600
7222 00:26:59.651529 CA_MCKIO = 1600
7223 00:26:59.655018 MCKIO_SEMI = 0
7224 00:26:59.658147 PLL_FREQ = 3068
7225 00:26:59.661274 DQ_UI_PI_RATIO = 32
7226 00:26:59.664940 CA_UI_PI_RATIO = 0
7227 00:26:59.667819 ===================================
7228 00:26:59.671626 ===================================
7229 00:26:59.671710 memory_type:LPDDR4
7230 00:26:59.675076 GP_NUM : 10
7231 00:26:59.677939 SRAM_EN : 1
7232 00:26:59.678020 MD32_EN : 0
7233 00:26:59.681244 ===================================
7234 00:26:59.684849 [ANA_INIT] >>>>>>>>>>>>>>
7235 00:26:59.687959 <<<<<< [CONFIGURE PHASE]: ANA_TX
7236 00:26:59.691119 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7237 00:26:59.694520 ===================================
7238 00:26:59.697657 data_rate = 3200,PCW = 0X7600
7239 00:26:59.701156 ===================================
7240 00:26:59.704174 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7241 00:26:59.707721 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7242 00:26:59.714042 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7243 00:26:59.717428 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7244 00:26:59.724107 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7245 00:26:59.727348 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7246 00:26:59.727432 [ANA_INIT] flow start
7247 00:26:59.730662 [ANA_INIT] PLL >>>>>>>>
7248 00:26:59.733942 [ANA_INIT] PLL <<<<<<<<
7249 00:26:59.734024 [ANA_INIT] MIDPI >>>>>>>>
7250 00:26:59.737246 [ANA_INIT] MIDPI <<<<<<<<
7251 00:26:59.740729 [ANA_INIT] DLL >>>>>>>>
7252 00:26:59.740811 [ANA_INIT] DLL <<<<<<<<
7253 00:26:59.744060 [ANA_INIT] flow end
7254 00:26:59.747264 ============ LP4 DIFF to SE enter ============
7255 00:26:59.750851 ============ LP4 DIFF to SE exit ============
7256 00:26:59.754031 [ANA_INIT] <<<<<<<<<<<<<
7257 00:26:59.757133 [Flow] Enable top DCM control >>>>>
7258 00:26:59.760222 [Flow] Enable top DCM control <<<<<
7259 00:26:59.763672 Enable DLL master slave shuffle
7260 00:26:59.770750 ==============================================================
7261 00:26:59.770834 Gating Mode config
7262 00:26:59.777111 ==============================================================
7263 00:26:59.777195 Config description:
7264 00:26:59.786846 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7265 00:26:59.793703 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7266 00:26:59.800202 SELPH_MODE 0: By rank 1: By Phase
7267 00:26:59.806973 ==============================================================
7268 00:26:59.807062 GAT_TRACK_EN = 1
7269 00:26:59.810100 RX_GATING_MODE = 2
7270 00:26:59.813424 RX_GATING_TRACK_MODE = 2
7271 00:26:59.816612 SELPH_MODE = 1
7272 00:26:59.820099 PICG_EARLY_EN = 1
7273 00:26:59.823221 VALID_LAT_VALUE = 1
7274 00:26:59.829833 ==============================================================
7275 00:26:59.833202 Enter into Gating configuration >>>>
7276 00:26:59.836319 Exit from Gating configuration <<<<
7277 00:26:59.840454 Enter into DVFS_PRE_config >>>>>
7278 00:26:59.849370 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7279 00:26:59.852922 Exit from DVFS_PRE_config <<<<<
7280 00:26:59.856000 Enter into PICG configuration >>>>
7281 00:26:59.859470 Exit from PICG configuration <<<<
7282 00:26:59.862686 [RX_INPUT] configuration >>>>>
7283 00:26:59.865775 [RX_INPUT] configuration <<<<<
7284 00:26:59.869620 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7285 00:26:59.876226 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7286 00:26:59.882467 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7287 00:26:59.885669 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7288 00:26:59.892544 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7289 00:26:59.899097 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7290 00:26:59.902449 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7291 00:26:59.909265 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7292 00:26:59.912437 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7293 00:26:59.915749 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7294 00:26:59.918979 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7295 00:26:59.925394 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7296 00:26:59.928548 ===================================
7297 00:26:59.928635 LPDDR4 DRAM CONFIGURATION
7298 00:26:59.932051 ===================================
7299 00:26:59.935400 EX_ROW_EN[0] = 0x0
7300 00:26:59.938794 EX_ROW_EN[1] = 0x0
7301 00:26:59.938877 LP4Y_EN = 0x0
7302 00:26:59.942078 WORK_FSP = 0x1
7303 00:26:59.942167 WL = 0x5
7304 00:26:59.945076 RL = 0x5
7305 00:26:59.945159 BL = 0x2
7306 00:26:59.948448 RPST = 0x0
7307 00:26:59.948531 RD_PRE = 0x0
7308 00:26:59.951663 WR_PRE = 0x1
7309 00:26:59.951745 WR_PST = 0x1
7310 00:26:59.954856 DBI_WR = 0x0
7311 00:26:59.954939 DBI_RD = 0x0
7312 00:26:59.958030 OTF = 0x1
7313 00:26:59.961433 ===================================
7314 00:26:59.965092 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7315 00:26:59.968074 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7316 00:26:59.974800 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7317 00:26:59.978112 ===================================
7318 00:26:59.981113 LPDDR4 DRAM CONFIGURATION
7319 00:26:59.984517 ===================================
7320 00:26:59.984600 EX_ROW_EN[0] = 0x10
7321 00:26:59.987721 EX_ROW_EN[1] = 0x0
7322 00:26:59.987803 LP4Y_EN = 0x0
7323 00:26:59.991170 WORK_FSP = 0x1
7324 00:26:59.991251 WL = 0x5
7325 00:26:59.994680 RL = 0x5
7326 00:26:59.994761 BL = 0x2
7327 00:26:59.997655 RPST = 0x0
7328 00:26:59.997736 RD_PRE = 0x0
7329 00:27:00.000868 WR_PRE = 0x1
7330 00:27:00.000951 WR_PST = 0x1
7331 00:27:00.004535 DBI_WR = 0x0
7332 00:27:00.007683 DBI_RD = 0x0
7333 00:27:00.007767 OTF = 0x1
7334 00:27:00.011140 ===================================
7335 00:27:00.017467 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7336 00:27:00.017551 ==
7337 00:27:00.021031 Dram Type= 6, Freq= 0, CH_0, rank 0
7338 00:27:00.024417 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7339 00:27:00.024502 ==
7340 00:27:00.027745 [Duty_Offset_Calibration]
7341 00:27:00.027829 B0:1 B1:-1 CA:0
7342 00:27:00.030994
7343 00:27:00.033966 [DutyScan_Calibration_Flow] k_type=0
7344 00:27:00.042203
7345 00:27:00.042289 ==CLK 0==
7346 00:27:00.045430 Final CLK duty delay cell = 0
7347 00:27:00.048775 [0] MAX Duty = 5124%(X100), DQS PI = 22
7348 00:27:00.052176 [0] MIN Duty = 4907%(X100), DQS PI = 4
7349 00:27:00.052260 [0] AVG Duty = 5015%(X100)
7350 00:27:00.055407
7351 00:27:00.058586 CH0 CLK Duty spec in!! Max-Min= 217%
7352 00:27:00.061759 [DutyScan_Calibration_Flow] ====Done====
7353 00:27:00.061843
7354 00:27:00.065031 [DutyScan_Calibration_Flow] k_type=1
7355 00:27:00.081698
7356 00:27:00.081794 ==DQS 0 ==
7357 00:27:00.084405 Final DQS duty delay cell = -4
7358 00:27:00.088161 [-4] MAX Duty = 4969%(X100), DQS PI = 20
7359 00:27:00.091190 [-4] MIN Duty = 4844%(X100), DQS PI = 10
7360 00:27:00.094698 [-4] AVG Duty = 4906%(X100)
7361 00:27:00.094782
7362 00:27:00.094847 ==DQS 1 ==
7363 00:27:00.097972 Final DQS duty delay cell = 0
7364 00:27:00.101072 [0] MAX Duty = 5156%(X100), DQS PI = 2
7365 00:27:00.104503 [0] MIN Duty = 5000%(X100), DQS PI = 18
7366 00:27:00.107728 [0] AVG Duty = 5078%(X100)
7367 00:27:00.107812
7368 00:27:00.110969 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7369 00:27:00.111053
7370 00:27:00.114090 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7371 00:27:00.117482 [DutyScan_Calibration_Flow] ====Done====
7372 00:27:00.117564
7373 00:27:00.120718 [DutyScan_Calibration_Flow] k_type=3
7374 00:27:00.139047
7375 00:27:00.139146 ==DQM 0 ==
7376 00:27:00.142111 Final DQM duty delay cell = 0
7377 00:27:00.145456 [0] MAX Duty = 5093%(X100), DQS PI = 20
7378 00:27:00.148690 [0] MIN Duty = 4875%(X100), DQS PI = 10
7379 00:27:00.151958 [0] AVG Duty = 4984%(X100)
7380 00:27:00.152066
7381 00:27:00.152160 ==DQM 1 ==
7382 00:27:00.155429 Final DQM duty delay cell = 0
7383 00:27:00.158898 [0] MAX Duty = 5000%(X100), DQS PI = 6
7384 00:27:00.162237 [0] MIN Duty = 4813%(X100), DQS PI = 20
7385 00:27:00.165077 [0] AVG Duty = 4906%(X100)
7386 00:27:00.165159
7387 00:27:00.168539 CH0 DQM 0 Duty spec in!! Max-Min= 218%
7388 00:27:00.168621
7389 00:27:00.171845 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7390 00:27:00.175283 [DutyScan_Calibration_Flow] ====Done====
7391 00:27:00.175366
7392 00:27:00.178437 [DutyScan_Calibration_Flow] k_type=2
7393 00:27:00.195028
7394 00:27:00.195115 ==DQ 0 ==
7395 00:27:00.198391 Final DQ duty delay cell = -4
7396 00:27:00.201847 [-4] MAX Duty = 5031%(X100), DQS PI = 24
7397 00:27:00.205036 [-4] MIN Duty = 4876%(X100), DQS PI = 50
7398 00:27:00.208617 [-4] AVG Duty = 4953%(X100)
7399 00:27:00.208724
7400 00:27:00.208791 ==DQ 1 ==
7401 00:27:00.211944 Final DQ duty delay cell = 0
7402 00:27:00.214766 [0] MAX Duty = 5125%(X100), DQS PI = 4
7403 00:27:00.218373 [0] MIN Duty = 4969%(X100), DQS PI = 38
7404 00:27:00.221756 [0] AVG Duty = 5047%(X100)
7405 00:27:00.221838
7406 00:27:00.225223 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7407 00:27:00.225306
7408 00:27:00.228100 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7409 00:27:00.231387 [DutyScan_Calibration_Flow] ====Done====
7410 00:27:00.231515 ==
7411 00:27:00.234702 Dram Type= 6, Freq= 0, CH_1, rank 0
7412 00:27:00.238275 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7413 00:27:00.238358 ==
7414 00:27:00.241318 [Duty_Offset_Calibration]
7415 00:27:00.241399 B0:-1 B1:1 CA:2
7416 00:27:00.241464
7417 00:27:00.244478 [DutyScan_Calibration_Flow] k_type=0
7418 00:27:00.255762
7419 00:27:00.255846 ==CLK 0==
7420 00:27:00.258990 Final CLK duty delay cell = 0
7421 00:27:00.262472 [0] MAX Duty = 5156%(X100), DQS PI = 22
7422 00:27:00.265616 [0] MIN Duty = 5062%(X100), DQS PI = 0
7423 00:27:00.268576 [0] AVG Duty = 5109%(X100)
7424 00:27:00.268659
7425 00:27:00.271946 CH1 CLK Duty spec in!! Max-Min= 94%
7426 00:27:00.275707 [DutyScan_Calibration_Flow] ====Done====
7427 00:27:00.275789
7428 00:27:00.278568 [DutyScan_Calibration_Flow] k_type=1
7429 00:27:00.295569
7430 00:27:00.295658 ==DQS 0 ==
7431 00:27:00.298721 Final DQS duty delay cell = 0
7432 00:27:00.301774 [0] MAX Duty = 5124%(X100), DQS PI = 20
7433 00:27:00.305257 [0] MIN Duty = 4907%(X100), DQS PI = 40
7434 00:27:00.308797 [0] AVG Duty = 5015%(X100)
7435 00:27:00.308878
7436 00:27:00.308943 ==DQS 1 ==
7437 00:27:00.311685 Final DQS duty delay cell = 0
7438 00:27:00.314979 [0] MAX Duty = 5062%(X100), DQS PI = 0
7439 00:27:00.318170 [0] MIN Duty = 4969%(X100), DQS PI = 24
7440 00:27:00.321531 [0] AVG Duty = 5015%(X100)
7441 00:27:00.321614
7442 00:27:00.324949 CH1 DQS 0 Duty spec in!! Max-Min= 217%
7443 00:27:00.325032
7444 00:27:00.328458 CH1 DQS 1 Duty spec in!! Max-Min= 93%
7445 00:27:00.331424 [DutyScan_Calibration_Flow] ====Done====
7446 00:27:00.331516
7447 00:27:00.334720 [DutyScan_Calibration_Flow] k_type=3
7448 00:27:00.351966
7449 00:27:00.352053 ==DQM 0 ==
7450 00:27:00.355183 Final DQM duty delay cell = 0
7451 00:27:00.358565 [0] MAX Duty = 5187%(X100), DQS PI = 6
7452 00:27:00.361812 [0] MIN Duty = 5031%(X100), DQS PI = 38
7453 00:27:00.365159 [0] AVG Duty = 5109%(X100)
7454 00:27:00.365241
7455 00:27:00.365307 ==DQM 1 ==
7456 00:27:00.368821 Final DQM duty delay cell = 0
7457 00:27:00.371944 [0] MAX Duty = 5187%(X100), DQS PI = 34
7458 00:27:00.375295 [0] MIN Duty = 4969%(X100), DQS PI = 0
7459 00:27:00.378425 [0] AVG Duty = 5078%(X100)
7460 00:27:00.378508
7461 00:27:00.381603 CH1 DQM 0 Duty spec in!! Max-Min= 156%
7462 00:27:00.381685
7463 00:27:00.385000 CH1 DQM 1 Duty spec in!! Max-Min= 218%
7464 00:27:00.388359 [DutyScan_Calibration_Flow] ====Done====
7465 00:27:00.388442
7466 00:27:00.391328 [DutyScan_Calibration_Flow] k_type=2
7467 00:27:00.409054
7468 00:27:00.409148 ==DQ 0 ==
7469 00:27:00.412180 Final DQ duty delay cell = 0
7470 00:27:00.415579 [0] MAX Duty = 5156%(X100), DQS PI = 0
7471 00:27:00.418843 [0] MIN Duty = 4906%(X100), DQS PI = 40
7472 00:27:00.421608 [0] AVG Duty = 5031%(X100)
7473 00:27:00.421690
7474 00:27:00.421755 ==DQ 1 ==
7475 00:27:00.425185 Final DQ duty delay cell = 0
7476 00:27:00.428433 [0] MAX Duty = 5125%(X100), DQS PI = 40
7477 00:27:00.431610 [0] MIN Duty = 4969%(X100), DQS PI = 0
7478 00:27:00.434951 [0] AVG Duty = 5047%(X100)
7479 00:27:00.435034
7480 00:27:00.438505 CH1 DQ 0 Duty spec in!! Max-Min= 250%
7481 00:27:00.438589
7482 00:27:00.441502 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7483 00:27:00.444676 [DutyScan_Calibration_Flow] ====Done====
7484 00:27:00.448243 nWR fixed to 30
7485 00:27:00.451095 [ModeRegInit_LP4] CH0 RK0
7486 00:27:00.451178 [ModeRegInit_LP4] CH0 RK1
7487 00:27:00.454369 [ModeRegInit_LP4] CH1 RK0
7488 00:27:00.457697 [ModeRegInit_LP4] CH1 RK1
7489 00:27:00.457780 match AC timing 5
7490 00:27:00.464655 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7491 00:27:00.467723 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7492 00:27:00.471083 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7493 00:27:00.477819 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7494 00:27:00.481124 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7495 00:27:00.481208 [MiockJmeterHQA]
7496 00:27:00.481272
7497 00:27:00.484212 [DramcMiockJmeter] u1RxGatingPI = 0
7498 00:27:00.488122 0 : 4252, 4027
7499 00:27:00.488206 4 : 4363, 4137
7500 00:27:00.491314 8 : 4253, 4027
7501 00:27:00.491399 12 : 4363, 4138
7502 00:27:00.494619 16 : 4254, 4029
7503 00:27:00.494703 20 : 4363, 4138
7504 00:27:00.494769 24 : 4252, 4026
7505 00:27:00.497876 28 : 4252, 4027
7506 00:27:00.497959 32 : 4252, 4027
7507 00:27:00.501288 36 : 4252, 4027
7508 00:27:00.501371 40 : 4363, 4138
7509 00:27:00.504103 44 : 4250, 4026
7510 00:27:00.504190 48 : 4250, 4027
7511 00:27:00.507798 52 : 4250, 4027
7512 00:27:00.507883 56 : 4250, 4027
7513 00:27:00.507950 60 : 4250, 4027
7514 00:27:00.510535 64 : 4360, 4137
7515 00:27:00.510618 68 : 4361, 4137
7516 00:27:00.514019 72 : 4361, 4137
7517 00:27:00.514104 76 : 4249, 4027
7518 00:27:00.517440 80 : 4252, 4030
7519 00:27:00.517524 84 : 4249, 4027
7520 00:27:00.520597 88 : 4250, 4023
7521 00:27:00.520682 92 : 4361, 161
7522 00:27:00.520748 96 : 4252, 0
7523 00:27:00.523838 100 : 4365, 0
7524 00:27:00.523922 104 : 4361, 0
7525 00:27:00.527185 108 : 4250, 0
7526 00:27:00.527269 112 : 4255, 0
7527 00:27:00.527336 116 : 4250, 0
7528 00:27:00.530719 120 : 4250, 0
7529 00:27:00.530879 124 : 4255, 0
7530 00:27:00.533778 128 : 4249, 0
7531 00:27:00.533862 132 : 4250, 0
7532 00:27:00.533928 136 : 4253, 0
7533 00:27:00.537005 140 : 4250, 0
7534 00:27:00.537089 144 : 4249, 0
7535 00:27:00.537156 148 : 4255, 0
7536 00:27:00.540048 152 : 4361, 0
7537 00:27:00.540132 156 : 4250, 0
7538 00:27:00.543574 160 : 4360, 0
7539 00:27:00.543659 164 : 4250, 0
7540 00:27:00.543726 168 : 4252, 0
7541 00:27:00.546702 172 : 4360, 0
7542 00:27:00.546785 176 : 4250, 0
7543 00:27:00.550505 180 : 4250, 0
7544 00:27:00.550588 184 : 4360, 0
7545 00:27:00.550656 188 : 4250, 0
7546 00:27:00.553746 192 : 4250, 0
7547 00:27:00.553830 196 : 4250, 0
7548 00:27:00.556686 200 : 4255, 0
7549 00:27:00.556770 204 : 4361, 0
7550 00:27:00.556836 208 : 4250, 0
7551 00:27:00.560295 212 : 4360, 0
7552 00:27:00.560379 216 : 4249, 0
7553 00:27:00.563532 220 : 4250, 0
7554 00:27:00.563615 224 : 4360, 85
7555 00:27:00.563682 228 : 4250, 3306
7556 00:27:00.566740 232 : 4250, 4027
7557 00:27:00.566825 236 : 4250, 4027
7558 00:27:00.570154 240 : 4361, 4137
7559 00:27:00.570277 244 : 4360, 4137
7560 00:27:00.573168 248 : 4250, 4027
7561 00:27:00.573267 252 : 4360, 4138
7562 00:27:00.576314 256 : 4250, 4027
7563 00:27:00.576399 260 : 4249, 4027
7564 00:27:00.579696 264 : 4250, 4027
7565 00:27:00.579780 268 : 4363, 4140
7566 00:27:00.582939 272 : 4250, 4027
7567 00:27:00.583023 276 : 4249, 4027
7568 00:27:00.586628 280 : 4360, 4138
7569 00:27:00.586712 284 : 4250, 4026
7570 00:27:00.589630 288 : 4250, 4027
7571 00:27:00.589714 292 : 4361, 4137
7572 00:27:00.589781 296 : 4360, 4137
7573 00:27:00.592881 300 : 4250, 4026
7574 00:27:00.592965 304 : 4250, 4027
7575 00:27:00.596019 308 : 4250, 4027
7576 00:27:00.596104 312 : 4249, 4027
7577 00:27:00.599590 316 : 4249, 4027
7578 00:27:00.599674 320 : 4255, 4031
7579 00:27:00.602597 324 : 4250, 4027
7580 00:27:00.602683 328 : 4250, 4027
7581 00:27:00.606144 332 : 4250, 4026
7582 00:27:00.606255 336 : 4253, 3912
7583 00:27:00.609605 340 : 4250, 2185
7584 00:27:00.609688 344 : 4363, 6
7585 00:27:00.609757
7586 00:27:00.612756 MIOCK jitter meter ch=0
7587 00:27:00.612840
7588 00:27:00.616212 1T = (344-92) = 252 dly cells
7589 00:27:00.619216 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7590 00:27:00.619299 ==
7591 00:27:00.623133 Dram Type= 6, Freq= 0, CH_0, rank 0
7592 00:27:00.629442 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7593 00:27:00.629527 ==
7594 00:27:00.632589 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7595 00:27:00.639429 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7596 00:27:00.642402 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7597 00:27:00.649288 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7598 00:27:00.660156 [CA 0] Center 43 (13~74) winsize 62
7599 00:27:00.660259 [CA 1] Center 43 (13~74) winsize 62
7600 00:27:00.663379 [CA 2] Center 39 (10~69) winsize 60
7601 00:27:00.666573 [CA 3] Center 39 (9~69) winsize 61
7602 00:27:00.669813 [CA 4] Center 37 (8~66) winsize 59
7603 00:27:00.673337 [CA 5] Center 36 (7~66) winsize 60
7604 00:27:00.673421
7605 00:27:00.676419 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7606 00:27:00.679663
7607 00:27:00.683039 [CATrainingPosCal] consider 1 rank data
7608 00:27:00.683122 u2DelayCellTimex100 = 258/100 ps
7609 00:27:00.689547 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7610 00:27:00.693136 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7611 00:27:00.696117 CA2 delay=39 (10~69),Diff = 3 PI (11 cell)
7612 00:27:00.699528 CA3 delay=39 (9~69),Diff = 3 PI (11 cell)
7613 00:27:00.703161 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7614 00:27:00.706159 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7615 00:27:00.706282
7616 00:27:00.709569 CA PerBit enable=1, Macro0, CA PI delay=36
7617 00:27:00.712959
7618 00:27:00.713042 [CBTSetCACLKResult] CA Dly = 36
7619 00:27:00.716147 CS Dly: 12 (0~43)
7620 00:27:00.719420 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7621 00:27:00.722575 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7622 00:27:00.726032 ==
7623 00:27:00.729145 Dram Type= 6, Freq= 0, CH_0, rank 1
7624 00:27:00.732776 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7625 00:27:00.732861 ==
7626 00:27:00.735919 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7627 00:27:00.742647 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7628 00:27:00.745627 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7629 00:27:00.752098 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7630 00:27:00.760928 [CA 0] Center 43 (13~74) winsize 62
7631 00:27:00.764129 [CA 1] Center 44 (14~74) winsize 61
7632 00:27:00.767533 [CA 2] Center 38 (9~68) winsize 60
7633 00:27:00.770637 [CA 3] Center 38 (9~68) winsize 60
7634 00:27:00.774209 [CA 4] Center 36 (7~66) winsize 60
7635 00:27:00.777509 [CA 5] Center 36 (6~66) winsize 61
7636 00:27:00.777591
7637 00:27:00.780377 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7638 00:27:00.780461
7639 00:27:00.786921 [CATrainingPosCal] consider 2 rank data
7640 00:27:00.787011 u2DelayCellTimex100 = 258/100 ps
7641 00:27:00.793690 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7642 00:27:00.797322 CA1 delay=44 (14~74),Diff = 8 PI (30 cell)
7643 00:27:00.800285 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7644 00:27:00.803720 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7645 00:27:00.806951 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7646 00:27:00.810185 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7647 00:27:00.810309
7648 00:27:00.813615 CA PerBit enable=1, Macro0, CA PI delay=36
7649 00:27:00.813700
7650 00:27:00.816683 [CBTSetCACLKResult] CA Dly = 36
7651 00:27:00.819919 CS Dly: 12 (0~43)
7652 00:27:00.823490 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7653 00:27:00.826585 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7654 00:27:00.826668
7655 00:27:00.830005 ----->DramcWriteLeveling(PI) begin...
7656 00:27:00.830089 ==
7657 00:27:00.832927 Dram Type= 6, Freq= 0, CH_0, rank 0
7658 00:27:00.839876 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7659 00:27:00.839962 ==
7660 00:27:00.843390 Write leveling (Byte 0): 35 => 35
7661 00:27:00.846131 Write leveling (Byte 1): 27 => 27
7662 00:27:00.849502 DramcWriteLeveling(PI) end<-----
7663 00:27:00.849586
7664 00:27:00.849652 ==
7665 00:27:00.853107 Dram Type= 6, Freq= 0, CH_0, rank 0
7666 00:27:00.856251 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7667 00:27:00.856336 ==
7668 00:27:00.859278 [Gating] SW mode calibration
7669 00:27:00.865759 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7670 00:27:00.872503 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7671 00:27:00.875841 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7672 00:27:00.879159 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7673 00:27:00.885677 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7674 00:27:00.889143 1 4 12 | B1->B0 | 2323 2b2a | 0 1 | (0 0) (0 0)
7675 00:27:00.892848 1 4 16 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7676 00:27:00.898981 1 4 20 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
7677 00:27:00.902553 1 4 24 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
7678 00:27:00.905494 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7679 00:27:00.912195 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7680 00:27:00.915273 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7681 00:27:00.918427 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7682 00:27:00.925025 1 5 12 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (1 0)
7683 00:27:00.928522 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7684 00:27:00.931753 1 5 20 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
7685 00:27:00.938691 1 5 24 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
7686 00:27:00.941774 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7687 00:27:00.944971 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7688 00:27:00.952178 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7689 00:27:00.955129 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7690 00:27:00.957995 1 6 12 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7691 00:27:00.965109 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7692 00:27:00.968230 1 6 20 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
7693 00:27:00.971646 1 6 24 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
7694 00:27:00.977980 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7695 00:27:00.981137 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7696 00:27:00.984786 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7697 00:27:00.991208 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7698 00:27:00.994848 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7699 00:27:00.997584 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7700 00:27:01.004188 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7701 00:27:01.009754 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7702 00:27:01.010883 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7703 00:27:01.017596 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7704 00:27:01.020852 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7705 00:27:01.024441 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7706 00:27:01.030549 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7707 00:27:01.034199 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7708 00:27:01.037098 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7709 00:27:01.043917 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7710 00:27:01.047160 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7711 00:27:01.050157 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7712 00:27:01.057199 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7713 00:27:01.060060 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7714 00:27:01.063388 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7715 00:27:01.066669 Total UI for P1: 0, mck2ui 16
7716 00:27:01.070006 best dqsien dly found for B0: ( 1, 9, 10)
7717 00:27:01.076797 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7718 00:27:01.079943 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7719 00:27:01.083061 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7720 00:27:01.086608 Total UI for P1: 0, mck2ui 16
7721 00:27:01.089940 best dqsien dly found for B1: ( 1, 9, 18)
7722 00:27:01.093211 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7723 00:27:01.096489 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7724 00:27:01.096571
7725 00:27:01.102860 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7726 00:27:01.106046 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7727 00:27:01.109337 [Gating] SW calibration Done
7728 00:27:01.109421 ==
7729 00:27:01.113122 Dram Type= 6, Freq= 0, CH_0, rank 0
7730 00:27:01.116062 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7731 00:27:01.116159 ==
7732 00:27:01.116227 RX Vref Scan: 0
7733 00:27:01.119435
7734 00:27:01.119518 RX Vref 0 -> 0, step: 1
7735 00:27:01.119583
7736 00:27:01.122794 RX Delay 0 -> 252, step: 8
7737 00:27:01.126323 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7738 00:27:01.129310 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
7739 00:27:01.135619 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7740 00:27:01.139217 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7741 00:27:01.142369 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7742 00:27:01.145513 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7743 00:27:01.148919 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
7744 00:27:01.155427 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7745 00:27:01.158793 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7746 00:27:01.162276 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7747 00:27:01.165817 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7748 00:27:01.168840 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7749 00:27:01.175415 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7750 00:27:01.178784 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7751 00:27:01.182198 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7752 00:27:01.185420 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7753 00:27:01.185504 ==
7754 00:27:01.188530 Dram Type= 6, Freq= 0, CH_0, rank 0
7755 00:27:01.195228 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7756 00:27:01.195312 ==
7757 00:27:01.195378 DQS Delay:
7758 00:27:01.198572 DQS0 = 0, DQS1 = 0
7759 00:27:01.198682 DQM Delay:
7760 00:27:01.201783 DQM0 = 134, DQM1 = 126
7761 00:27:01.201901 DQ Delay:
7762 00:27:01.204787 DQ0 =135, DQ1 =135, DQ2 =131, DQ3 =131
7763 00:27:01.208255 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =147
7764 00:27:01.211620 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =119
7765 00:27:01.214991 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =131
7766 00:27:01.215074
7767 00:27:01.215140
7768 00:27:01.215201 ==
7769 00:27:01.217972 Dram Type= 6, Freq= 0, CH_0, rank 0
7770 00:27:01.224732 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7771 00:27:01.224818 ==
7772 00:27:01.224903
7773 00:27:01.224983
7774 00:27:01.225060 TX Vref Scan disable
7775 00:27:01.228960 == TX Byte 0 ==
7776 00:27:01.231765 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7777 00:27:01.238077 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7778 00:27:01.238209 == TX Byte 1 ==
7779 00:27:01.241531 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7780 00:27:01.248112 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7781 00:27:01.248238 ==
7782 00:27:01.251166 Dram Type= 6, Freq= 0, CH_0, rank 0
7783 00:27:01.254662 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7784 00:27:01.254745 ==
7785 00:27:01.268151
7786 00:27:01.271375 TX Vref early break, caculate TX vref
7787 00:27:01.274740 TX Vref=16, minBit 4, minWin=22, winSum=372
7788 00:27:01.277624 TX Vref=18, minBit 4, minWin=22, winSum=376
7789 00:27:01.280918 TX Vref=20, minBit 0, minWin=23, winSum=390
7790 00:27:01.284187 TX Vref=22, minBit 4, minWin=24, winSum=404
7791 00:27:01.287955 TX Vref=24, minBit 3, minWin=24, winSum=409
7792 00:27:01.294156 TX Vref=26, minBit 0, minWin=25, winSum=412
7793 00:27:01.297848 TX Vref=28, minBit 4, minWin=24, winSum=412
7794 00:27:01.300729 TX Vref=30, minBit 0, minWin=24, winSum=411
7795 00:27:01.303806 TX Vref=32, minBit 0, minWin=24, winSum=401
7796 00:27:01.307441 TX Vref=34, minBit 1, minWin=23, winSum=386
7797 00:27:01.314106 [TxChooseVref] Worse bit 0, Min win 25, Win sum 412, Final Vref 26
7798 00:27:01.314232
7799 00:27:01.317359 Final TX Range 0 Vref 26
7800 00:27:01.317442
7801 00:27:01.317509 ==
7802 00:27:01.320626 Dram Type= 6, Freq= 0, CH_0, rank 0
7803 00:27:01.323890 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7804 00:27:01.323974 ==
7805 00:27:01.324040
7806 00:27:01.324100
7807 00:27:01.327345 TX Vref Scan disable
7808 00:27:01.334070 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7809 00:27:01.334155 == TX Byte 0 ==
7810 00:27:01.337344 u2DelayCellOfst[0]=15 cells (4 PI)
7811 00:27:01.340175 u2DelayCellOfst[1]=18 cells (5 PI)
7812 00:27:01.343453 u2DelayCellOfst[2]=15 cells (4 PI)
7813 00:27:01.346691 u2DelayCellOfst[3]=15 cells (4 PI)
7814 00:27:01.350041 u2DelayCellOfst[4]=11 cells (3 PI)
7815 00:27:01.353654 u2DelayCellOfst[5]=0 cells (0 PI)
7816 00:27:01.356805 u2DelayCellOfst[6]=22 cells (6 PI)
7817 00:27:01.359993 u2DelayCellOfst[7]=18 cells (5 PI)
7818 00:27:01.363474 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7819 00:27:01.366471 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7820 00:27:01.369821 == TX Byte 1 ==
7821 00:27:01.373180 u2DelayCellOfst[8]=0 cells (0 PI)
7822 00:27:01.376377 u2DelayCellOfst[9]=0 cells (0 PI)
7823 00:27:01.379577 u2DelayCellOfst[10]=7 cells (2 PI)
7824 00:27:01.382900 u2DelayCellOfst[11]=0 cells (0 PI)
7825 00:27:01.386223 u2DelayCellOfst[12]=11 cells (3 PI)
7826 00:27:01.386307 u2DelayCellOfst[13]=7 cells (2 PI)
7827 00:27:01.389742 u2DelayCellOfst[14]=15 cells (4 PI)
7828 00:27:01.392786 u2DelayCellOfst[15]=7 cells (2 PI)
7829 00:27:01.399688 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7830 00:27:01.402538 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7831 00:27:01.402622 DramC Write-DBI on
7832 00:27:01.406301 ==
7833 00:27:01.409745 Dram Type= 6, Freq= 0, CH_0, rank 0
7834 00:27:01.412755 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7835 00:27:01.412839 ==
7836 00:27:01.412904
7837 00:27:01.412966
7838 00:27:01.415960 TX Vref Scan disable
7839 00:27:01.416043 == TX Byte 0 ==
7840 00:27:01.422456 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7841 00:27:01.422542 == TX Byte 1 ==
7842 00:27:01.425999 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7843 00:27:01.429456 DramC Write-DBI off
7844 00:27:01.429540
7845 00:27:01.429607 [DATLAT]
7846 00:27:01.432666 Freq=1600, CH0 RK0
7847 00:27:01.432790
7848 00:27:01.432865 DATLAT Default: 0xf
7849 00:27:01.435831 0, 0xFFFF, sum = 0
7850 00:27:01.435915 1, 0xFFFF, sum = 0
7851 00:27:01.439175 2, 0xFFFF, sum = 0
7852 00:27:01.439259 3, 0xFFFF, sum = 0
7853 00:27:01.442305 4, 0xFFFF, sum = 0
7854 00:27:01.446077 5, 0xFFFF, sum = 0
7855 00:27:01.446184 6, 0xFFFF, sum = 0
7856 00:27:01.449047 7, 0xFFFF, sum = 0
7857 00:27:01.449131 8, 0xFFFF, sum = 0
7858 00:27:01.452198 9, 0xFFFF, sum = 0
7859 00:27:01.452283 10, 0xFFFF, sum = 0
7860 00:27:01.455673 11, 0xFFFF, sum = 0
7861 00:27:01.455758 12, 0xFFFF, sum = 0
7862 00:27:01.458761 13, 0xFFFF, sum = 0
7863 00:27:01.458846 14, 0x0, sum = 1
7864 00:27:01.462469 15, 0x0, sum = 2
7865 00:27:01.462554 16, 0x0, sum = 3
7866 00:27:01.465359 17, 0x0, sum = 4
7867 00:27:01.465443 best_step = 15
7868 00:27:01.465508
7869 00:27:01.465570 ==
7870 00:27:01.468518 Dram Type= 6, Freq= 0, CH_0, rank 0
7871 00:27:01.475145 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7872 00:27:01.475229 ==
7873 00:27:01.475295 RX Vref Scan: 1
7874 00:27:01.475356
7875 00:27:01.478857 Set Vref Range= 24 -> 127
7876 00:27:01.478939
7877 00:27:01.481743 RX Vref 24 -> 127, step: 1
7878 00:27:01.481825
7879 00:27:01.481890 RX Delay 11 -> 252, step: 4
7880 00:27:01.481951
7881 00:27:01.485559 Set Vref, RX VrefLevel [Byte0]: 24
7882 00:27:01.488529 [Byte1]: 24
7883 00:27:01.492635
7884 00:27:01.492717 Set Vref, RX VrefLevel [Byte0]: 25
7885 00:27:01.495961 [Byte1]: 25
7886 00:27:01.500273
7887 00:27:01.500356 Set Vref, RX VrefLevel [Byte0]: 26
7888 00:27:01.503368 [Byte1]: 26
7889 00:27:01.507854
7890 00:27:01.507941 Set Vref, RX VrefLevel [Byte0]: 27
7891 00:27:01.511289 [Byte1]: 27
7892 00:27:01.515140
7893 00:27:01.515223 Set Vref, RX VrefLevel [Byte0]: 28
7894 00:27:01.518581 [Byte1]: 28
7895 00:27:01.522948
7896 00:27:01.523031 Set Vref, RX VrefLevel [Byte0]: 29
7897 00:27:01.526052 [Byte1]: 29
7898 00:27:01.530396
7899 00:27:01.530480 Set Vref, RX VrefLevel [Byte0]: 30
7900 00:27:01.533893 [Byte1]: 30
7901 00:27:01.538386
7902 00:27:01.538470 Set Vref, RX VrefLevel [Byte0]: 31
7903 00:27:01.541552 [Byte1]: 31
7904 00:27:01.545627
7905 00:27:01.545710 Set Vref, RX VrefLevel [Byte0]: 32
7906 00:27:01.549130 [Byte1]: 32
7907 00:27:01.553387
7908 00:27:01.553469 Set Vref, RX VrefLevel [Byte0]: 33
7909 00:27:01.556764 [Byte1]: 33
7910 00:27:01.561134
7911 00:27:01.561217 Set Vref, RX VrefLevel [Byte0]: 34
7912 00:27:01.564284 [Byte1]: 34
7913 00:27:01.568948
7914 00:27:01.569032 Set Vref, RX VrefLevel [Byte0]: 35
7915 00:27:01.571809 [Byte1]: 35
7916 00:27:01.576314
7917 00:27:01.576397 Set Vref, RX VrefLevel [Byte0]: 36
7918 00:27:01.579965 [Byte1]: 36
7919 00:27:01.583812
7920 00:27:01.583894 Set Vref, RX VrefLevel [Byte0]: 37
7921 00:27:01.587397 [Byte1]: 37
7922 00:27:01.591741
7923 00:27:01.591823 Set Vref, RX VrefLevel [Byte0]: 38
7924 00:27:01.594860 [Byte1]: 38
7925 00:27:01.599364
7926 00:27:01.599445 Set Vref, RX VrefLevel [Byte0]: 39
7927 00:27:01.602398 [Byte1]: 39
7928 00:27:01.606733
7929 00:27:01.606816 Set Vref, RX VrefLevel [Byte0]: 40
7930 00:27:01.610140 [Byte1]: 40
7931 00:27:01.614641
7932 00:27:01.614724 Set Vref, RX VrefLevel [Byte0]: 41
7933 00:27:01.617874 [Byte1]: 41
7934 00:27:01.621824
7935 00:27:01.621907 Set Vref, RX VrefLevel [Byte0]: 42
7936 00:27:01.625900 [Byte1]: 42
7937 00:27:01.629694
7938 00:27:01.629776 Set Vref, RX VrefLevel [Byte0]: 43
7939 00:27:01.632982 [Byte1]: 43
7940 00:27:01.636983
7941 00:27:01.637066 Set Vref, RX VrefLevel [Byte0]: 44
7942 00:27:01.640661 [Byte1]: 44
7943 00:27:01.644666
7944 00:27:01.644748 Set Vref, RX VrefLevel [Byte0]: 45
7945 00:27:01.648240 [Byte1]: 45
7946 00:27:01.652349
7947 00:27:01.652432 Set Vref, RX VrefLevel [Byte0]: 46
7948 00:27:01.655744 [Byte1]: 46
7949 00:27:01.660056
7950 00:27:01.660138 Set Vref, RX VrefLevel [Byte0]: 47
7951 00:27:01.663176 [Byte1]: 47
7952 00:27:01.667970
7953 00:27:01.668057 Set Vref, RX VrefLevel [Byte0]: 48
7954 00:27:01.670875 [Byte1]: 48
7955 00:27:01.675242
7956 00:27:01.675325 Set Vref, RX VrefLevel [Byte0]: 49
7957 00:27:01.678495 [Byte1]: 49
7958 00:27:01.682713
7959 00:27:01.682795 Set Vref, RX VrefLevel [Byte0]: 50
7960 00:27:01.686353 [Byte1]: 50
7961 00:27:01.690439
7962 00:27:01.690521 Set Vref, RX VrefLevel [Byte0]: 51
7963 00:27:01.694049 [Byte1]: 51
7964 00:27:01.698396
7965 00:27:01.698478 Set Vref, RX VrefLevel [Byte0]: 52
7966 00:27:01.701476 [Byte1]: 52
7967 00:27:01.705576
7968 00:27:01.705722 Set Vref, RX VrefLevel [Byte0]: 53
7969 00:27:01.708963 [Byte1]: 53
7970 00:27:01.713052
7971 00:27:01.713134 Set Vref, RX VrefLevel [Byte0]: 54
7972 00:27:01.716876 [Byte1]: 54
7973 00:27:01.720751
7974 00:27:01.720833 Set Vref, RX VrefLevel [Byte0]: 55
7975 00:27:01.724020 [Byte1]: 55
7976 00:27:01.728858
7977 00:27:01.728942 Set Vref, RX VrefLevel [Byte0]: 56
7978 00:27:01.731711 [Byte1]: 56
7979 00:27:01.736209
7980 00:27:01.736292 Set Vref, RX VrefLevel [Byte0]: 57
7981 00:27:01.739281 [Byte1]: 57
7982 00:27:01.743418
7983 00:27:01.743500 Set Vref, RX VrefLevel [Byte0]: 58
7984 00:27:01.747343 [Byte1]: 58
7985 00:27:01.751931
7986 00:27:01.752014 Set Vref, RX VrefLevel [Byte0]: 59
7987 00:27:01.754625 [Byte1]: 59
7988 00:27:01.759219
7989 00:27:01.759346 Set Vref, RX VrefLevel [Byte0]: 60
7990 00:27:01.762202 [Byte1]: 60
7991 00:27:01.766809
7992 00:27:01.766891 Set Vref, RX VrefLevel [Byte0]: 61
7993 00:27:01.769986 [Byte1]: 61
7994 00:27:01.774219
7995 00:27:01.774302 Set Vref, RX VrefLevel [Byte0]: 62
7996 00:27:01.777573 [Byte1]: 62
7997 00:27:01.781800
7998 00:27:01.781882 Set Vref, RX VrefLevel [Byte0]: 63
7999 00:27:01.785374 [Byte1]: 63
8000 00:27:01.789449
8001 00:27:01.789532 Set Vref, RX VrefLevel [Byte0]: 64
8002 00:27:01.792792 [Byte1]: 64
8003 00:27:01.796945
8004 00:27:01.797027 Set Vref, RX VrefLevel [Byte0]: 65
8005 00:27:01.800237 [Byte1]: 65
8006 00:27:01.804632
8007 00:27:01.804718 Set Vref, RX VrefLevel [Byte0]: 66
8008 00:27:01.808111 [Byte1]: 66
8009 00:27:01.812158
8010 00:27:01.812243 Set Vref, RX VrefLevel [Byte0]: 67
8011 00:27:01.815728 [Byte1]: 67
8012 00:27:01.820148
8013 00:27:01.820231 Set Vref, RX VrefLevel [Byte0]: 68
8014 00:27:01.823500 [Byte1]: 68
8015 00:27:01.827520
8016 00:27:01.827637 Set Vref, RX VrefLevel [Byte0]: 69
8017 00:27:01.830615 [Byte1]: 69
8018 00:27:01.835445
8019 00:27:01.835529 Set Vref, RX VrefLevel [Byte0]: 70
8020 00:27:01.838902 [Byte1]: 70
8021 00:27:01.843037
8022 00:27:01.843121 Set Vref, RX VrefLevel [Byte0]: 71
8023 00:27:01.845866 [Byte1]: 71
8024 00:27:01.850088
8025 00:27:01.850230 Set Vref, RX VrefLevel [Byte0]: 72
8026 00:27:01.853650 [Byte1]: 72
8027 00:27:01.858083
8028 00:27:01.858190 Set Vref, RX VrefLevel [Byte0]: 73
8029 00:27:01.861242 [Byte1]: 73
8030 00:27:01.865615
8031 00:27:01.865698 Set Vref, RX VrefLevel [Byte0]: 74
8032 00:27:01.868650 [Byte1]: 74
8033 00:27:01.872900
8034 00:27:01.872982 Set Vref, RX VrefLevel [Byte0]: 75
8035 00:27:01.876632 [Byte1]: 75
8036 00:27:01.881016
8037 00:27:01.881099 Set Vref, RX VrefLevel [Byte0]: 76
8038 00:27:01.884045 [Byte1]: 76
8039 00:27:01.888432
8040 00:27:01.888515 Set Vref, RX VrefLevel [Byte0]: 77
8041 00:27:01.891427 [Byte1]: 77
8042 00:27:01.895864
8043 00:27:01.895947 Set Vref, RX VrefLevel [Byte0]: 78
8044 00:27:01.902413 [Byte1]: 78
8045 00:27:01.902496
8046 00:27:01.906027 Set Vref, RX VrefLevel [Byte0]: 79
8047 00:27:01.909298 [Byte1]: 79
8048 00:27:01.909410
8049 00:27:01.912690 Set Vref, RX VrefLevel [Byte0]: 80
8050 00:27:01.915824 [Byte1]: 80
8051 00:27:01.918942
8052 00:27:01.919024 Final RX Vref Byte 0 = 61 to rank0
8053 00:27:01.922528 Final RX Vref Byte 1 = 60 to rank0
8054 00:27:01.925410 Final RX Vref Byte 0 = 61 to rank1
8055 00:27:01.928670 Final RX Vref Byte 1 = 60 to rank1==
8056 00:27:01.932220 Dram Type= 6, Freq= 0, CH_0, rank 0
8057 00:27:01.938841 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8058 00:27:01.938927 ==
8059 00:27:01.938993 DQS Delay:
8060 00:27:01.941862 DQS0 = 0, DQS1 = 0
8061 00:27:01.941945 DQM Delay:
8062 00:27:01.942011 DQM0 = 132, DQM1 = 123
8063 00:27:01.945165 DQ Delay:
8064 00:27:01.948623 DQ0 =130, DQ1 =132, DQ2 =128, DQ3 =130
8065 00:27:01.951937 DQ4 =132, DQ5 =122, DQ6 =140, DQ7 =142
8066 00:27:01.955463 DQ8 =116, DQ9 =112, DQ10 =124, DQ11 =118
8067 00:27:01.958736 DQ12 =128, DQ13 =128, DQ14 =134, DQ15 =128
8068 00:27:01.958819
8069 00:27:01.958886
8070 00:27:01.958945
8071 00:27:01.961939 [DramC_TX_OE_Calibration] TA2
8072 00:27:01.965054 Original DQ_B0 (3 6) =30, OEN = 27
8073 00:27:01.968648 Original DQ_B1 (3 6) =30, OEN = 27
8074 00:27:01.971613 24, 0x0, End_B0=24 End_B1=24
8075 00:27:01.971698 25, 0x0, End_B0=25 End_B1=25
8076 00:27:01.974803 26, 0x0, End_B0=26 End_B1=26
8077 00:27:01.978503 27, 0x0, End_B0=27 End_B1=27
8078 00:27:01.981501 28, 0x0, End_B0=28 End_B1=28
8079 00:27:01.985058 29, 0x0, End_B0=29 End_B1=29
8080 00:27:01.985143 30, 0x0, End_B0=30 End_B1=30
8081 00:27:01.988161 31, 0x5151, End_B0=30 End_B1=30
8082 00:27:01.991566 Byte0 end_step=30 best_step=27
8083 00:27:01.995022 Byte1 end_step=30 best_step=27
8084 00:27:01.998245 Byte0 TX OE(2T, 0.5T) = (3, 3)
8085 00:27:02.001355 Byte1 TX OE(2T, 0.5T) = (3, 3)
8086 00:27:02.001438
8087 00:27:02.001504
8088 00:27:02.007844 [DQSOSCAuto] RK0, (LSB)MR18= 0x2011, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 393 ps
8089 00:27:02.011244 CH0 RK0: MR19=303, MR18=2011
8090 00:27:02.017834 CH0_RK0: MR19=0x303, MR18=0x2011, DQSOSC=393, MR23=63, INC=23, DEC=15
8091 00:27:02.017945
8092 00:27:02.021253 ----->DramcWriteLeveling(PI) begin...
8093 00:27:02.021338 ==
8094 00:27:02.024930 Dram Type= 6, Freq= 0, CH_0, rank 1
8095 00:27:02.027669 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8096 00:27:02.027752 ==
8097 00:27:02.031073 Write leveling (Byte 0): 35 => 35
8098 00:27:02.034329 Write leveling (Byte 1): 29 => 29
8099 00:27:02.037441 DramcWriteLeveling(PI) end<-----
8100 00:27:02.037557
8101 00:27:02.037626 ==
8102 00:27:02.040909 Dram Type= 6, Freq= 0, CH_0, rank 1
8103 00:27:02.044166 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8104 00:27:02.047571 ==
8105 00:27:02.047653 [Gating] SW mode calibration
8106 00:27:02.057196 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8107 00:27:02.060897 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8108 00:27:02.063766 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8109 00:27:02.070553 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8110 00:27:02.073781 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8111 00:27:02.077113 1 4 12 | B1->B0 | 2323 2525 | 0 1 | (0 0) (1 1)
8112 00:27:02.083560 1 4 16 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
8113 00:27:02.087191 1 4 20 | B1->B0 | 3332 3434 | 1 1 | (0 0) (1 1)
8114 00:27:02.089896 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8115 00:27:02.096977 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8116 00:27:02.100271 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8117 00:27:02.103343 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8118 00:27:02.109898 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8119 00:27:02.113110 1 5 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
8120 00:27:02.116410 1 5 16 | B1->B0 | 3434 2626 | 1 0 | (1 1) (1 0)
8121 00:27:02.123227 1 5 20 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
8122 00:27:02.126602 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8123 00:27:02.130041 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8124 00:27:02.136286 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8125 00:27:02.139634 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8126 00:27:02.143144 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8127 00:27:02.149492 1 6 12 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (1 1)
8128 00:27:02.153111 1 6 16 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
8129 00:27:02.156528 1 6 20 | B1->B0 | 3d3d 4646 | 0 0 | (1 1) (0 0)
8130 00:27:02.162561 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8131 00:27:02.166001 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8132 00:27:02.169393 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8133 00:27:02.176286 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8134 00:27:02.178952 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8135 00:27:02.182563 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8136 00:27:02.189120 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8137 00:27:02.192609 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8138 00:27:02.195670 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8139 00:27:02.202224 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8140 00:27:02.205657 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8141 00:27:02.208670 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8142 00:27:02.215385 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8143 00:27:02.218954 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8144 00:27:02.222486 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8145 00:27:02.228712 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8146 00:27:02.232025 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8147 00:27:02.235158 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8148 00:27:02.241745 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8149 00:27:02.245236 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8150 00:27:02.248741 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8151 00:27:02.255482 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8152 00:27:02.259420 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8153 00:27:02.261802 Total UI for P1: 0, mck2ui 16
8154 00:27:02.265316 best dqsien dly found for B0: ( 1, 9, 10)
8155 00:27:02.268471 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8156 00:27:02.271664 Total UI for P1: 0, mck2ui 16
8157 00:27:02.275201 best dqsien dly found for B1: ( 1, 9, 16)
8158 00:27:02.278565 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8159 00:27:02.281853 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8160 00:27:02.281935
8161 00:27:02.288309 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8162 00:27:02.291399 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8163 00:27:02.295040 [Gating] SW calibration Done
8164 00:27:02.295123 ==
8165 00:27:02.297980 Dram Type= 6, Freq= 0, CH_0, rank 1
8166 00:27:02.301421 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8167 00:27:02.301504 ==
8168 00:27:02.301570 RX Vref Scan: 0
8169 00:27:02.304673
8170 00:27:02.304781 RX Vref 0 -> 0, step: 1
8171 00:27:02.304875
8172 00:27:02.308236 RX Delay 0 -> 252, step: 8
8173 00:27:02.311255 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8174 00:27:02.314454 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8175 00:27:02.321237 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8176 00:27:02.324592 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8177 00:27:02.327750 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8178 00:27:02.331069 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8179 00:27:02.334422 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8180 00:27:02.341156 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8181 00:27:02.344259 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8182 00:27:02.347571 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8183 00:27:02.350820 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8184 00:27:02.354360 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8185 00:27:02.361095 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8186 00:27:02.364019 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8187 00:27:02.367824 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8188 00:27:02.370644 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8189 00:27:02.370728 ==
8190 00:27:02.374159 Dram Type= 6, Freq= 0, CH_0, rank 1
8191 00:27:02.380595 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8192 00:27:02.380678 ==
8193 00:27:02.380744 DQS Delay:
8194 00:27:02.384019 DQS0 = 0, DQS1 = 0
8195 00:27:02.384102 DQM Delay:
8196 00:27:02.387544 DQM0 = 133, DQM1 = 127
8197 00:27:02.387627 DQ Delay:
8198 00:27:02.390653 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =131
8199 00:27:02.393796 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8200 00:27:02.397260 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8201 00:27:02.400267 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =135
8202 00:27:02.400350
8203 00:27:02.400416
8204 00:27:02.400476 ==
8205 00:27:02.403681 Dram Type= 6, Freq= 0, CH_0, rank 1
8206 00:27:02.410444 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8207 00:27:02.410531 ==
8208 00:27:02.410641
8209 00:27:02.410702
8210 00:27:02.410761 TX Vref Scan disable
8211 00:27:02.413776 == TX Byte 0 ==
8212 00:27:02.417204 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8213 00:27:02.423963 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8214 00:27:02.424047 == TX Byte 1 ==
8215 00:27:02.427364 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8216 00:27:02.433834 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8217 00:27:02.433919 ==
8218 00:27:02.437141 Dram Type= 6, Freq= 0, CH_0, rank 1
8219 00:27:02.440039 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8220 00:27:02.440123 ==
8221 00:27:02.453312
8222 00:27:02.456484 TX Vref early break, caculate TX vref
8223 00:27:02.459916 TX Vref=16, minBit 1, minWin=22, winSum=378
8224 00:27:02.463446 TX Vref=18, minBit 1, minWin=23, winSum=392
8225 00:27:02.466150 TX Vref=20, minBit 0, minWin=24, winSum=396
8226 00:27:02.469613 TX Vref=22, minBit 1, minWin=24, winSum=405
8227 00:27:02.474988 TX Vref=24, minBit 1, minWin=24, winSum=414
8228 00:27:02.479498 TX Vref=26, minBit 1, minWin=24, winSum=417
8229 00:27:02.482674 TX Vref=28, minBit 1, minWin=24, winSum=411
8230 00:27:02.486621 TX Vref=30, minBit 0, minWin=24, winSum=409
8231 00:27:02.489418 TX Vref=32, minBit 5, minWin=23, winSum=398
8232 00:27:02.492580 TX Vref=34, minBit 1, minWin=22, winSum=386
8233 00:27:02.499327 [TxChooseVref] Worse bit 1, Min win 24, Win sum 417, Final Vref 26
8234 00:27:02.499412
8235 00:27:02.502633 Final TX Range 0 Vref 26
8236 00:27:02.502717
8237 00:27:02.502783 ==
8238 00:27:02.505499 Dram Type= 6, Freq= 0, CH_0, rank 1
8239 00:27:02.509129 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8240 00:27:02.509213 ==
8241 00:27:02.509280
8242 00:27:02.512294
8243 00:27:02.512377 TX Vref Scan disable
8244 00:27:02.518993 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8245 00:27:02.519077 == TX Byte 0 ==
8246 00:27:02.522706 u2DelayCellOfst[0]=11 cells (3 PI)
8247 00:27:02.525872 u2DelayCellOfst[1]=15 cells (4 PI)
8248 00:27:02.528816 u2DelayCellOfst[2]=11 cells (3 PI)
8249 00:27:02.532366 u2DelayCellOfst[3]=15 cells (4 PI)
8250 00:27:02.535364 u2DelayCellOfst[4]=7 cells (2 PI)
8251 00:27:02.538884 u2DelayCellOfst[5]=0 cells (0 PI)
8252 00:27:02.541992 u2DelayCellOfst[6]=18 cells (5 PI)
8253 00:27:02.545383 u2DelayCellOfst[7]=15 cells (4 PI)
8254 00:27:02.548859 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8255 00:27:02.552003 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8256 00:27:02.555513 == TX Byte 1 ==
8257 00:27:02.558536 u2DelayCellOfst[8]=0 cells (0 PI)
8258 00:27:02.561845 u2DelayCellOfst[9]=3 cells (1 PI)
8259 00:27:02.565016 u2DelayCellOfst[10]=7 cells (2 PI)
8260 00:27:02.568852 u2DelayCellOfst[11]=3 cells (1 PI)
8261 00:27:02.568936 u2DelayCellOfst[12]=15 cells (4 PI)
8262 00:27:02.571940 u2DelayCellOfst[13]=15 cells (4 PI)
8263 00:27:02.575017 u2DelayCellOfst[14]=18 cells (5 PI)
8264 00:27:02.578593 u2DelayCellOfst[15]=11 cells (3 PI)
8265 00:27:02.584849 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8266 00:27:02.587976 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8267 00:27:02.588060 DramC Write-DBI on
8268 00:27:02.591763 ==
8269 00:27:02.594773 Dram Type= 6, Freq= 0, CH_0, rank 1
8270 00:27:02.598343 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8271 00:27:02.598427 ==
8272 00:27:02.598493
8273 00:27:02.598553
8274 00:27:02.601252 TX Vref Scan disable
8275 00:27:02.601334 == TX Byte 0 ==
8276 00:27:02.607937 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8277 00:27:02.608027 == TX Byte 1 ==
8278 00:27:02.611340 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8279 00:27:02.614607 DramC Write-DBI off
8280 00:27:02.614690
8281 00:27:02.614757 [DATLAT]
8282 00:27:02.618088 Freq=1600, CH0 RK1
8283 00:27:02.618200
8284 00:27:02.618281 DATLAT Default: 0xf
8285 00:27:02.621507 0, 0xFFFF, sum = 0
8286 00:27:02.621591 1, 0xFFFF, sum = 0
8287 00:27:02.624518 2, 0xFFFF, sum = 0
8288 00:27:02.624602 3, 0xFFFF, sum = 0
8289 00:27:02.628331 4, 0xFFFF, sum = 0
8290 00:27:02.631335 5, 0xFFFF, sum = 0
8291 00:27:02.631420 6, 0xFFFF, sum = 0
8292 00:27:02.634379 7, 0xFFFF, sum = 0
8293 00:27:02.634465 8, 0xFFFF, sum = 0
8294 00:27:02.638006 9, 0xFFFF, sum = 0
8295 00:27:02.638091 10, 0xFFFF, sum = 0
8296 00:27:02.640636 11, 0xFFFF, sum = 0
8297 00:27:02.640721 12, 0xFFFF, sum = 0
8298 00:27:02.644114 13, 0xFFFF, sum = 0
8299 00:27:02.644199 14, 0x0, sum = 1
8300 00:27:02.647619 15, 0x0, sum = 2
8301 00:27:02.647704 16, 0x0, sum = 3
8302 00:27:02.650703 17, 0x0, sum = 4
8303 00:27:02.650788 best_step = 15
8304 00:27:02.650855
8305 00:27:02.650917 ==
8306 00:27:02.654382 Dram Type= 6, Freq= 0, CH_0, rank 1
8307 00:27:02.660973 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8308 00:27:02.661057 ==
8309 00:27:02.661124 RX Vref Scan: 0
8310 00:27:02.661186
8311 00:27:02.663835 RX Vref 0 -> 0, step: 1
8312 00:27:02.663918
8313 00:27:02.667544 RX Delay 11 -> 252, step: 4
8314 00:27:02.670924 iDelay=195, Bit 0, Center 128 (79 ~ 178) 100
8315 00:27:02.673791 iDelay=195, Bit 1, Center 134 (83 ~ 186) 104
8316 00:27:02.677089 iDelay=195, Bit 2, Center 126 (75 ~ 178) 104
8317 00:27:02.683697 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8318 00:27:02.687117 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
8319 00:27:02.690271 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8320 00:27:02.693774 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8321 00:27:02.697067 iDelay=195, Bit 7, Center 138 (87 ~ 190) 104
8322 00:27:02.703634 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8323 00:27:02.706907 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8324 00:27:02.709940 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8325 00:27:02.713378 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8326 00:27:02.719892 iDelay=195, Bit 12, Center 130 (79 ~ 182) 104
8327 00:27:02.723456 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8328 00:27:02.726665 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8329 00:27:02.729632 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8330 00:27:02.729717 ==
8331 00:27:02.733146 Dram Type= 6, Freq= 0, CH_0, rank 1
8332 00:27:02.740070 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8333 00:27:02.740159 ==
8334 00:27:02.740226 DQS Delay:
8335 00:27:02.740287 DQS0 = 0, DQS1 = 0
8336 00:27:02.743057 DQM Delay:
8337 00:27:02.743142 DQM0 = 130, DQM1 = 125
8338 00:27:02.746296 DQ Delay:
8339 00:27:02.750002 DQ0 =128, DQ1 =134, DQ2 =126, DQ3 =128
8340 00:27:02.752772 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =138
8341 00:27:02.756265 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =120
8342 00:27:02.759685 DQ12 =130, DQ13 =132, DQ14 =136, DQ15 =132
8343 00:27:02.759771
8344 00:27:02.759838
8345 00:27:02.759899
8346 00:27:02.763098 [DramC_TX_OE_Calibration] TA2
8347 00:27:02.766438 Original DQ_B0 (3 6) =30, OEN = 27
8348 00:27:02.769725 Original DQ_B1 (3 6) =30, OEN = 27
8349 00:27:02.772828 24, 0x0, End_B0=24 End_B1=24
8350 00:27:02.772912 25, 0x0, End_B0=25 End_B1=25
8351 00:27:02.776085 26, 0x0, End_B0=26 End_B1=26
8352 00:27:02.779881 27, 0x0, End_B0=27 End_B1=27
8353 00:27:02.782585 28, 0x0, End_B0=28 End_B1=28
8354 00:27:02.785902 29, 0x0, End_B0=29 End_B1=29
8355 00:27:02.785987 30, 0x0, End_B0=30 End_B1=30
8356 00:27:02.789375 31, 0x4141, End_B0=30 End_B1=30
8357 00:27:02.792818 Byte0 end_step=30 best_step=27
8358 00:27:02.796173 Byte1 end_step=30 best_step=27
8359 00:27:02.799220 Byte0 TX OE(2T, 0.5T) = (3, 3)
8360 00:27:02.802655 Byte1 TX OE(2T, 0.5T) = (3, 3)
8361 00:27:02.802738
8362 00:27:02.802802
8363 00:27:02.809429 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f01, (MSB)MR19= 0x303, tDQSOscB0 = 409 ps tDQSOscB1 = 394 ps
8364 00:27:02.812653 CH0 RK1: MR19=303, MR18=1F01
8365 00:27:02.818986 CH0_RK1: MR19=0x303, MR18=0x1F01, DQSOSC=394, MR23=63, INC=23, DEC=15
8366 00:27:02.822534 [RxdqsGatingPostProcess] freq 1600
8367 00:27:02.825574 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8368 00:27:02.828835 best DQS0 dly(2T, 0.5T) = (1, 1)
8369 00:27:02.832187 best DQS1 dly(2T, 0.5T) = (1, 1)
8370 00:27:02.835491 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8371 00:27:02.838792 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8372 00:27:02.842086 best DQS0 dly(2T, 0.5T) = (1, 1)
8373 00:27:02.845563 best DQS1 dly(2T, 0.5T) = (1, 1)
8374 00:27:02.848723 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8375 00:27:02.852127 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8376 00:27:02.855306 Pre-setting of DQS Precalculation
8377 00:27:02.858506 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8378 00:27:02.858584 ==
8379 00:27:02.861895 Dram Type= 6, Freq= 0, CH_1, rank 0
8380 00:27:02.868199 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8381 00:27:02.868276 ==
8382 00:27:02.871608 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8383 00:27:02.878446 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8384 00:27:02.881938 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8385 00:27:02.888393 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8386 00:27:02.895934 [CA 0] Center 41 (12~71) winsize 60
8387 00:27:02.899284 [CA 1] Center 42 (12~72) winsize 61
8388 00:27:02.902455 [CA 2] Center 37 (8~66) winsize 59
8389 00:27:02.905859 [CA 3] Center 36 (7~65) winsize 59
8390 00:27:02.908997 [CA 4] Center 37 (8~66) winsize 59
8391 00:27:02.912700 [CA 5] Center 36 (7~66) winsize 60
8392 00:27:02.912782
8393 00:27:02.915591 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8394 00:27:02.915673
8395 00:27:02.919307 [CATrainingPosCal] consider 1 rank data
8396 00:27:02.922136 u2DelayCellTimex100 = 258/100 ps
8397 00:27:02.929221 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8398 00:27:02.932090 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8399 00:27:02.935626 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8400 00:27:02.938790 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8401 00:27:02.942051 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8402 00:27:02.945294 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8403 00:27:02.945378
8404 00:27:02.948752 CA PerBit enable=1, Macro0, CA PI delay=36
8405 00:27:02.948835
8406 00:27:02.951890 [CBTSetCACLKResult] CA Dly = 36
8407 00:27:02.954864 CS Dly: 9 (0~40)
8408 00:27:02.958676 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8409 00:27:02.961745 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8410 00:27:02.961827 ==
8411 00:27:02.964815 Dram Type= 6, Freq= 0, CH_1, rank 1
8412 00:27:02.971664 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8413 00:27:02.971751 ==
8414 00:27:02.975017 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8415 00:27:02.981317 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8416 00:27:02.984819 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8417 00:27:02.991299 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8418 00:27:02.999193 [CA 0] Center 42 (12~72) winsize 61
8419 00:27:03.002420 [CA 1] Center 42 (13~72) winsize 60
8420 00:27:03.005779 [CA 2] Center 37 (8~67) winsize 60
8421 00:27:03.009204 [CA 3] Center 37 (8~66) winsize 59
8422 00:27:03.012162 [CA 4] Center 37 (8~67) winsize 60
8423 00:27:03.015397 [CA 5] Center 37 (7~67) winsize 61
8424 00:27:03.015478
8425 00:27:03.019096 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8426 00:27:03.019176
8427 00:27:03.022279 [CATrainingPosCal] consider 2 rank data
8428 00:27:03.025399 u2DelayCellTimex100 = 258/100 ps
8429 00:27:03.032301 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8430 00:27:03.035891 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8431 00:27:03.038517 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8432 00:27:03.042183 CA3 delay=36 (8~65),Diff = 0 PI (0 cell)
8433 00:27:03.045184 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8434 00:27:03.048657 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8435 00:27:03.048740
8436 00:27:03.051777 CA PerBit enable=1, Macro0, CA PI delay=36
8437 00:27:03.051859
8438 00:27:03.055347 [CBTSetCACLKResult] CA Dly = 36
8439 00:27:03.058519 CS Dly: 10 (0~43)
8440 00:27:03.061811 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8441 00:27:03.065188 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8442 00:27:03.065291
8443 00:27:03.068340 ----->DramcWriteLeveling(PI) begin...
8444 00:27:03.068423 ==
8445 00:27:03.071719 Dram Type= 6, Freq= 0, CH_1, rank 0
8446 00:27:03.078048 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8447 00:27:03.078137 ==
8448 00:27:03.081446 Write leveling (Byte 0): 23 => 23
8449 00:27:03.084558 Write leveling (Byte 1): 27 => 27
8450 00:27:03.087799 DramcWriteLeveling(PI) end<-----
8451 00:27:03.087887
8452 00:27:03.087953 ==
8453 00:27:03.091242 Dram Type= 6, Freq= 0, CH_1, rank 0
8454 00:27:03.094841 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8455 00:27:03.094942 ==
8456 00:27:03.098248 [Gating] SW mode calibration
8457 00:27:03.104642 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8458 00:27:03.111218 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8459 00:27:03.114140 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8460 00:27:03.117789 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8461 00:27:03.120831 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8462 00:27:03.127977 1 4 12 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
8463 00:27:03.130773 1 4 16 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8464 00:27:03.134533 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8465 00:27:03.140619 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8466 00:27:03.144322 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8467 00:27:03.150499 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8468 00:27:03.154021 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8469 00:27:03.157269 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8470 00:27:03.163999 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
8471 00:27:03.167132 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8472 00:27:03.170874 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8473 00:27:03.173627 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8474 00:27:03.180272 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8475 00:27:03.183785 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8476 00:27:03.187073 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8477 00:27:03.193321 1 6 8 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
8478 00:27:03.196946 1 6 12 | B1->B0 | 3333 4646 | 1 0 | (0 0) (0 0)
8479 00:27:03.199916 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8480 00:27:03.206422 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8481 00:27:03.210219 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8482 00:27:03.213470 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8483 00:27:03.220045 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8484 00:27:03.223193 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8485 00:27:03.226458 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8486 00:27:03.233074 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8487 00:27:03.236705 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8488 00:27:03.239898 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8489 00:27:03.246522 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8490 00:27:03.249768 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8491 00:27:03.253248 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8492 00:27:03.259680 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8493 00:27:03.263143 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8494 00:27:03.266142 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8495 00:27:03.272598 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8496 00:27:03.276112 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8497 00:27:03.279811 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8498 00:27:03.286399 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8499 00:27:03.288999 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8500 00:27:03.292654 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8501 00:27:03.299366 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8502 00:27:03.302795 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8503 00:27:03.306064 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8504 00:27:03.309137 Total UI for P1: 0, mck2ui 16
8505 00:27:03.312653 best dqsien dly found for B0: ( 1, 9, 10)
8506 00:27:03.319327 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8507 00:27:03.322115 Total UI for P1: 0, mck2ui 16
8508 00:27:03.325821 best dqsien dly found for B1: ( 1, 9, 14)
8509 00:27:03.329031 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8510 00:27:03.332305 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8511 00:27:03.332388
8512 00:27:03.335354 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8513 00:27:03.339392 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8514 00:27:03.341827 [Gating] SW calibration Done
8515 00:27:03.341909 ==
8516 00:27:03.345605 Dram Type= 6, Freq= 0, CH_1, rank 0
8517 00:27:03.348384 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8518 00:27:03.348466 ==
8519 00:27:03.351853 RX Vref Scan: 0
8520 00:27:03.351935
8521 00:27:03.355029 RX Vref 0 -> 0, step: 1
8522 00:27:03.355111
8523 00:27:03.355177 RX Delay 0 -> 252, step: 8
8524 00:27:03.361685 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8525 00:27:03.364750 iDelay=208, Bit 1, Center 135 (88 ~ 183) 96
8526 00:27:03.368062 iDelay=208, Bit 2, Center 131 (80 ~ 183) 104
8527 00:27:03.371784 iDelay=208, Bit 3, Center 139 (88 ~ 191) 104
8528 00:27:03.374851 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8529 00:27:03.381813 iDelay=208, Bit 5, Center 155 (104 ~ 207) 104
8530 00:27:03.384629 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8531 00:27:03.388110 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8532 00:27:03.391481 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8533 00:27:03.398158 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8534 00:27:03.401339 iDelay=208, Bit 10, Center 127 (72 ~ 183) 112
8535 00:27:03.404509 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8536 00:27:03.407592 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8537 00:27:03.411522 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8538 00:27:03.417667 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8539 00:27:03.420802 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8540 00:27:03.420886 ==
8541 00:27:03.424313 Dram Type= 6, Freq= 0, CH_1, rank 0
8542 00:27:03.427929 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8543 00:27:03.428013 ==
8544 00:27:03.430994 DQS Delay:
8545 00:27:03.431078 DQS0 = 0, DQS1 = 0
8546 00:27:03.431144 DQM Delay:
8547 00:27:03.434601 DQM0 = 140, DQM1 = 129
8548 00:27:03.434700 DQ Delay:
8549 00:27:03.437259 DQ0 =143, DQ1 =135, DQ2 =131, DQ3 =139
8550 00:27:03.441027 DQ4 =135, DQ5 =155, DQ6 =147, DQ7 =135
8551 00:27:03.447270 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =123
8552 00:27:03.451065 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =139
8553 00:27:03.451149
8554 00:27:03.451214
8555 00:27:03.451274 ==
8556 00:27:03.454358 Dram Type= 6, Freq= 0, CH_1, rank 0
8557 00:27:03.457416 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8558 00:27:03.457499 ==
8559 00:27:03.457565
8560 00:27:03.457624
8561 00:27:03.460505 TX Vref Scan disable
8562 00:27:03.463892 == TX Byte 0 ==
8563 00:27:03.467427 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8564 00:27:03.470497 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8565 00:27:03.473444 == TX Byte 1 ==
8566 00:27:03.476751 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8567 00:27:03.480597 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8568 00:27:03.480680 ==
8569 00:27:03.483631 Dram Type= 6, Freq= 0, CH_1, rank 0
8570 00:27:03.486990 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8571 00:27:03.490127 ==
8572 00:27:03.501565
8573 00:27:03.505162 TX Vref early break, caculate TX vref
8574 00:27:03.508360 TX Vref=16, minBit 0, minWin=22, winSum=377
8575 00:27:03.511495 TX Vref=18, minBit 0, minWin=23, winSum=387
8576 00:27:03.514768 TX Vref=20, minBit 0, minWin=22, winSum=395
8577 00:27:03.518275 TX Vref=22, minBit 0, minWin=24, winSum=408
8578 00:27:03.521239 TX Vref=24, minBit 0, minWin=24, winSum=415
8579 00:27:03.528064 TX Vref=26, minBit 0, minWin=24, winSum=423
8580 00:27:03.531228 TX Vref=28, minBit 0, minWin=25, winSum=420
8581 00:27:03.534481 TX Vref=30, minBit 1, minWin=23, winSum=414
8582 00:27:03.537649 TX Vref=32, minBit 0, minWin=23, winSum=404
8583 00:27:03.541042 TX Vref=34, minBit 1, minWin=23, winSum=399
8584 00:27:03.547787 [TxChooseVref] Worse bit 0, Min win 25, Win sum 420, Final Vref 28
8585 00:27:03.547878
8586 00:27:03.550810 Final TX Range 0 Vref 28
8587 00:27:03.550896
8588 00:27:03.550982 ==
8589 00:27:03.554433 Dram Type= 6, Freq= 0, CH_1, rank 0
8590 00:27:03.557829 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8591 00:27:03.557921 ==
8592 00:27:03.558006
8593 00:27:03.558106
8594 00:27:03.561124 TX Vref Scan disable
8595 00:27:03.567608 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8596 00:27:03.567695 == TX Byte 0 ==
8597 00:27:03.570773 u2DelayCellOfst[0]=18 cells (5 PI)
8598 00:27:03.574113 u2DelayCellOfst[1]=11 cells (3 PI)
8599 00:27:03.577788 u2DelayCellOfst[2]=0 cells (0 PI)
8600 00:27:03.580810 u2DelayCellOfst[3]=3 cells (1 PI)
8601 00:27:03.584242 u2DelayCellOfst[4]=7 cells (2 PI)
8602 00:27:03.587438 u2DelayCellOfst[5]=18 cells (5 PI)
8603 00:27:03.590528 u2DelayCellOfst[6]=18 cells (5 PI)
8604 00:27:03.593943 u2DelayCellOfst[7]=3 cells (1 PI)
8605 00:27:03.597164 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8606 00:27:03.600294 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8607 00:27:03.603650 == TX Byte 1 ==
8608 00:27:03.607089 u2DelayCellOfst[8]=0 cells (0 PI)
8609 00:27:03.607237 u2DelayCellOfst[9]=3 cells (1 PI)
8610 00:27:03.610296 u2DelayCellOfst[10]=11 cells (3 PI)
8611 00:27:03.613713 u2DelayCellOfst[11]=3 cells (1 PI)
8612 00:27:03.616977 u2DelayCellOfst[12]=15 cells (4 PI)
8613 00:27:03.620447 u2DelayCellOfst[13]=18 cells (5 PI)
8614 00:27:03.623421 u2DelayCellOfst[14]=18 cells (5 PI)
8615 00:27:03.626645 u2DelayCellOfst[15]=18 cells (5 PI)
8616 00:27:03.633312 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8617 00:27:03.636617 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8618 00:27:03.636747 DramC Write-DBI on
8619 00:27:03.636842 ==
8620 00:27:03.640473 Dram Type= 6, Freq= 0, CH_1, rank 0
8621 00:27:03.646428 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8622 00:27:03.646513 ==
8623 00:27:03.646579
8624 00:27:03.646639
8625 00:27:03.646696 TX Vref Scan disable
8626 00:27:03.650498 == TX Byte 0 ==
8627 00:27:03.653769 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8628 00:27:03.657464 == TX Byte 1 ==
8629 00:27:03.660740 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8630 00:27:03.663888 DramC Write-DBI off
8631 00:27:03.663974
8632 00:27:03.664039 [DATLAT]
8633 00:27:03.664101 Freq=1600, CH1 RK0
8634 00:27:03.664161
8635 00:27:03.667188 DATLAT Default: 0xf
8636 00:27:03.667272 0, 0xFFFF, sum = 0
8637 00:27:03.670515 1, 0xFFFF, sum = 0
8638 00:27:03.673916 2, 0xFFFF, sum = 0
8639 00:27:03.674001 3, 0xFFFF, sum = 0
8640 00:27:03.677247 4, 0xFFFF, sum = 0
8641 00:27:03.677333 5, 0xFFFF, sum = 0
8642 00:27:03.680593 6, 0xFFFF, sum = 0
8643 00:27:03.680678 7, 0xFFFF, sum = 0
8644 00:27:03.683548 8, 0xFFFF, sum = 0
8645 00:27:03.683633 9, 0xFFFF, sum = 0
8646 00:27:03.686817 10, 0xFFFF, sum = 0
8647 00:27:03.686902 11, 0xFFFF, sum = 0
8648 00:27:03.690089 12, 0xFFFF, sum = 0
8649 00:27:03.690182 13, 0xFFFF, sum = 0
8650 00:27:03.693678 14, 0x0, sum = 1
8651 00:27:03.693763 15, 0x0, sum = 2
8652 00:27:03.696965 16, 0x0, sum = 3
8653 00:27:03.697049 17, 0x0, sum = 4
8654 00:27:03.700012 best_step = 15
8655 00:27:03.700095
8656 00:27:03.700160 ==
8657 00:27:03.703766 Dram Type= 6, Freq= 0, CH_1, rank 0
8658 00:27:03.706771 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8659 00:27:03.706858 ==
8660 00:27:03.709922 RX Vref Scan: 1
8661 00:27:03.710007
8662 00:27:03.710088 Set Vref Range= 24 -> 127
8663 00:27:03.710153
8664 00:27:03.713373 RX Vref 24 -> 127, step: 1
8665 00:27:03.713457
8666 00:27:03.716650 RX Delay 11 -> 252, step: 4
8667 00:27:03.716734
8668 00:27:03.719797 Set Vref, RX VrefLevel [Byte0]: 24
8669 00:27:03.723218 [Byte1]: 24
8670 00:27:03.723302
8671 00:27:03.726409 Set Vref, RX VrefLevel [Byte0]: 25
8672 00:27:03.729811 [Byte1]: 25
8673 00:27:03.733431
8674 00:27:03.733515 Set Vref, RX VrefLevel [Byte0]: 26
8675 00:27:03.737120 [Byte1]: 26
8676 00:27:03.741305
8677 00:27:03.741388 Set Vref, RX VrefLevel [Byte0]: 27
8678 00:27:03.744390 [Byte1]: 27
8679 00:27:03.748733
8680 00:27:03.748818 Set Vref, RX VrefLevel [Byte0]: 28
8681 00:27:03.751759 [Byte1]: 28
8682 00:27:03.756012
8683 00:27:03.756096 Set Vref, RX VrefLevel [Byte0]: 29
8684 00:27:03.759663 [Byte1]: 29
8685 00:27:03.763665
8686 00:27:03.763748 Set Vref, RX VrefLevel [Byte0]: 30
8687 00:27:03.767499 [Byte1]: 30
8688 00:27:03.771442
8689 00:27:03.771527 Set Vref, RX VrefLevel [Byte0]: 31
8690 00:27:03.774978 [Byte1]: 31
8691 00:27:03.778945
8692 00:27:03.782129 Set Vref, RX VrefLevel [Byte0]: 32
8693 00:27:03.785638 [Byte1]: 32
8694 00:27:03.785722
8695 00:27:03.788613 Set Vref, RX VrefLevel [Byte0]: 33
8696 00:27:03.792478 [Byte1]: 33
8697 00:27:03.792562
8698 00:27:03.795266 Set Vref, RX VrefLevel [Byte0]: 34
8699 00:27:03.798493 [Byte1]: 34
8700 00:27:03.802048
8701 00:27:03.802132 Set Vref, RX VrefLevel [Byte0]: 35
8702 00:27:03.805505 [Byte1]: 35
8703 00:27:03.809807
8704 00:27:03.809892 Set Vref, RX VrefLevel [Byte0]: 36
8705 00:27:03.812684 [Byte1]: 36
8706 00:27:03.817000
8707 00:27:03.817085 Set Vref, RX VrefLevel [Byte0]: 37
8708 00:27:03.820302 [Byte1]: 37
8709 00:27:03.824779
8710 00:27:03.824863 Set Vref, RX VrefLevel [Byte0]: 38
8711 00:27:03.828270 [Byte1]: 38
8712 00:27:03.832958
8713 00:27:03.833042 Set Vref, RX VrefLevel [Byte0]: 39
8714 00:27:03.836082 [Byte1]: 39
8715 00:27:03.839901
8716 00:27:03.839987 Set Vref, RX VrefLevel [Byte0]: 40
8717 00:27:03.843787 [Byte1]: 40
8718 00:27:03.847734
8719 00:27:03.847818 Set Vref, RX VrefLevel [Byte0]: 41
8720 00:27:03.850988 [Byte1]: 41
8721 00:27:03.855158
8722 00:27:03.855242 Set Vref, RX VrefLevel [Byte0]: 42
8723 00:27:03.858459 [Byte1]: 42
8724 00:27:03.863061
8725 00:27:03.863146 Set Vref, RX VrefLevel [Byte0]: 43
8726 00:27:03.866106 [Byte1]: 43
8727 00:27:03.870723
8728 00:27:03.870810 Set Vref, RX VrefLevel [Byte0]: 44
8729 00:27:03.874134 [Byte1]: 44
8730 00:27:03.877880
8731 00:27:03.877964 Set Vref, RX VrefLevel [Byte0]: 45
8732 00:27:03.881815 [Byte1]: 45
8733 00:27:03.885588
8734 00:27:03.885670 Set Vref, RX VrefLevel [Byte0]: 46
8735 00:27:03.888839 [Byte1]: 46
8736 00:27:03.893676
8737 00:27:03.893760 Set Vref, RX VrefLevel [Byte0]: 47
8738 00:27:03.897049 [Byte1]: 47
8739 00:27:03.900817
8740 00:27:03.900900 Set Vref, RX VrefLevel [Byte0]: 48
8741 00:27:03.904361 [Byte1]: 48
8742 00:27:03.908922
8743 00:27:03.909016 Set Vref, RX VrefLevel [Byte0]: 49
8744 00:27:03.911916 [Byte1]: 49
8745 00:27:03.916409
8746 00:27:03.916492 Set Vref, RX VrefLevel [Byte0]: 50
8747 00:27:03.919571 [Byte1]: 50
8748 00:27:03.924148
8749 00:27:03.924231 Set Vref, RX VrefLevel [Byte0]: 51
8750 00:27:03.927258 [Byte1]: 51
8751 00:27:03.931265
8752 00:27:03.931348 Set Vref, RX VrefLevel [Byte0]: 52
8753 00:27:03.934803 [Byte1]: 52
8754 00:27:03.938817
8755 00:27:03.938899 Set Vref, RX VrefLevel [Byte0]: 53
8756 00:27:03.942080 [Byte1]: 53
8757 00:27:03.946442
8758 00:27:03.946524 Set Vref, RX VrefLevel [Byte0]: 54
8759 00:27:03.949645 [Byte1]: 54
8760 00:27:03.954084
8761 00:27:03.954177 Set Vref, RX VrefLevel [Byte0]: 55
8762 00:27:03.957545 [Byte1]: 55
8763 00:27:03.962090
8764 00:27:03.962196 Set Vref, RX VrefLevel [Byte0]: 56
8765 00:27:03.965128 [Byte1]: 56
8766 00:27:03.969629
8767 00:27:03.969712 Set Vref, RX VrefLevel [Byte0]: 57
8768 00:27:03.972915 [Byte1]: 57
8769 00:27:03.976870
8770 00:27:03.976952 Set Vref, RX VrefLevel [Byte0]: 58
8771 00:27:03.980731 [Byte1]: 58
8772 00:27:03.984478
8773 00:27:03.984561 Set Vref, RX VrefLevel [Byte0]: 59
8774 00:27:03.987722 [Byte1]: 59
8775 00:27:03.992063
8776 00:27:03.992146 Set Vref, RX VrefLevel [Byte0]: 60
8777 00:27:03.995745 [Byte1]: 60
8778 00:27:04.000072
8779 00:27:04.000156 Set Vref, RX VrefLevel [Byte0]: 61
8780 00:27:04.003252 [Byte1]: 61
8781 00:27:04.007618
8782 00:27:04.007702 Set Vref, RX VrefLevel [Byte0]: 62
8783 00:27:04.014308 [Byte1]: 62
8784 00:27:04.014392
8785 00:27:04.017236 Set Vref, RX VrefLevel [Byte0]: 63
8786 00:27:04.020614 [Byte1]: 63
8787 00:27:04.020698
8788 00:27:04.024232 Set Vref, RX VrefLevel [Byte0]: 64
8789 00:27:04.027113 [Byte1]: 64
8790 00:27:04.027195
8791 00:27:04.030797 Set Vref, RX VrefLevel [Byte0]: 65
8792 00:27:04.033822 [Byte1]: 65
8793 00:27:04.038014
8794 00:27:04.038101 Set Vref, RX VrefLevel [Byte0]: 66
8795 00:27:04.041395 [Byte1]: 66
8796 00:27:04.045918
8797 00:27:04.046000 Set Vref, RX VrefLevel [Byte0]: 67
8798 00:27:04.049157 [Byte1]: 67
8799 00:27:04.053119
8800 00:27:04.053201 Set Vref, RX VrefLevel [Byte0]: 68
8801 00:27:04.056784 [Byte1]: 68
8802 00:27:04.060911
8803 00:27:04.060994 Set Vref, RX VrefLevel [Byte0]: 69
8804 00:27:04.064299 [Byte1]: 69
8805 00:27:04.068389
8806 00:27:04.068470 Set Vref, RX VrefLevel [Byte0]: 70
8807 00:27:04.072057 [Byte1]: 70
8808 00:27:04.076148
8809 00:27:04.076231 Set Vref, RX VrefLevel [Byte0]: 71
8810 00:27:04.079509 [Byte1]: 71
8811 00:27:04.083579
8812 00:27:04.083661 Set Vref, RX VrefLevel [Byte0]: 72
8813 00:27:04.086741 [Byte1]: 72
8814 00:27:04.091236
8815 00:27:04.091319 Set Vref, RX VrefLevel [Byte0]: 73
8816 00:27:04.094864 [Byte1]: 73
8817 00:27:04.099110
8818 00:27:04.099193 Final RX Vref Byte 0 = 55 to rank0
8819 00:27:04.102319 Final RX Vref Byte 1 = 59 to rank0
8820 00:27:04.105549 Final RX Vref Byte 0 = 55 to rank1
8821 00:27:04.108764 Final RX Vref Byte 1 = 59 to rank1==
8822 00:27:04.112296 Dram Type= 6, Freq= 0, CH_1, rank 0
8823 00:27:04.118559 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8824 00:27:04.118670 ==
8825 00:27:04.118764 DQS Delay:
8826 00:27:04.121633 DQS0 = 0, DQS1 = 0
8827 00:27:04.121741 DQM Delay:
8828 00:27:04.121836 DQM0 = 135, DQM1 = 128
8829 00:27:04.125271 DQ Delay:
8830 00:27:04.128433 DQ0 =142, DQ1 =130, DQ2 =126, DQ3 =132
8831 00:27:04.131879 DQ4 =132, DQ5 =148, DQ6 =146, DQ7 =130
8832 00:27:04.135116 DQ8 =114, DQ9 =116, DQ10 =130, DQ11 =116
8833 00:27:04.138488 DQ12 =136, DQ13 =138, DQ14 =136, DQ15 =138
8834 00:27:04.138571
8835 00:27:04.138637
8836 00:27:04.138697
8837 00:27:04.141599 [DramC_TX_OE_Calibration] TA2
8838 00:27:04.145059 Original DQ_B0 (3 6) =30, OEN = 27
8839 00:27:04.148340 Original DQ_B1 (3 6) =30, OEN = 27
8840 00:27:04.151458 24, 0x0, End_B0=24 End_B1=24
8841 00:27:04.151542 25, 0x0, End_B0=25 End_B1=25
8842 00:27:04.154839 26, 0x0, End_B0=26 End_B1=26
8843 00:27:04.158124 27, 0x0, End_B0=27 End_B1=27
8844 00:27:04.161322 28, 0x0, End_B0=28 End_B1=28
8845 00:27:04.164915 29, 0x0, End_B0=29 End_B1=29
8846 00:27:04.165026 30, 0x0, End_B0=30 End_B1=30
8847 00:27:04.168129 31, 0x4141, End_B0=30 End_B1=30
8848 00:27:04.171427 Byte0 end_step=30 best_step=27
8849 00:27:04.174852 Byte1 end_step=30 best_step=27
8850 00:27:04.178254 Byte0 TX OE(2T, 0.5T) = (3, 3)
8851 00:27:04.181535 Byte1 TX OE(2T, 0.5T) = (3, 3)
8852 00:27:04.181617
8853 00:27:04.181706
8854 00:27:04.187895 [DQSOSCAuto] RK0, (LSB)MR18= 0x190f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
8855 00:27:04.191052 CH1 RK0: MR19=303, MR18=190F
8856 00:27:04.197697 CH1_RK0: MR19=0x303, MR18=0x190F, DQSOSC=397, MR23=63, INC=23, DEC=15
8857 00:27:04.197807
8858 00:27:04.201306 ----->DramcWriteLeveling(PI) begin...
8859 00:27:04.201393 ==
8860 00:27:04.204535 Dram Type= 6, Freq= 0, CH_1, rank 1
8861 00:27:04.207583 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8862 00:27:04.207668 ==
8863 00:27:04.210995 Write leveling (Byte 0): 23 => 23
8864 00:27:04.214138 Write leveling (Byte 1): 29 => 29
8865 00:27:04.217476 DramcWriteLeveling(PI) end<-----
8866 00:27:04.217559
8867 00:27:04.217624 ==
8868 00:27:04.221145 Dram Type= 6, Freq= 0, CH_1, rank 1
8869 00:27:04.224013 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8870 00:27:04.227242 ==
8871 00:27:04.227325 [Gating] SW mode calibration
8872 00:27:04.237521 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8873 00:27:04.241116 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8874 00:27:04.244273 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8875 00:27:04.250272 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8876 00:27:04.253545 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8877 00:27:04.256817 1 4 12 | B1->B0 | 2a2a 2323 | 0 0 | (1 1) (0 0)
8878 00:27:04.263688 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8879 00:27:04.266618 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8880 00:27:04.270527 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8881 00:27:04.276756 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8882 00:27:04.280123 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8883 00:27:04.283327 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8884 00:27:04.290094 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8885 00:27:04.293397 1 5 12 | B1->B0 | 2d2d 3333 | 0 1 | (1 0) (1 0)
8886 00:27:04.296810 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8887 00:27:04.303067 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8888 00:27:04.306443 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8889 00:27:04.309856 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8890 00:27:04.316520 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8891 00:27:04.319399 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8892 00:27:04.323021 1 6 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8893 00:27:04.329571 1 6 12 | B1->B0 | 3939 2323 | 1 1 | (0 0) (0 0)
8894 00:27:04.332796 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8895 00:27:04.336268 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8896 00:27:04.342707 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8897 00:27:04.346334 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8898 00:27:04.349438 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8899 00:27:04.356140 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8900 00:27:04.359420 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8901 00:27:04.362730 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8902 00:27:04.369124 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8903 00:27:04.372148 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8904 00:27:04.375887 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8905 00:27:04.382463 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8906 00:27:04.385839 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8907 00:27:04.388754 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8908 00:27:04.395526 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8909 00:27:04.398406 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8910 00:27:04.401823 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8911 00:27:04.408522 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8912 00:27:04.411786 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8913 00:27:04.415453 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8914 00:27:04.422352 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8915 00:27:04.425090 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8916 00:27:04.428467 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8917 00:27:04.435059 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8918 00:27:04.438491 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8919 00:27:04.441605 Total UI for P1: 0, mck2ui 16
8920 00:27:04.444928 best dqsien dly found for B1: ( 1, 9, 10)
8921 00:27:04.448330 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8922 00:27:04.451766 Total UI for P1: 0, mck2ui 16
8923 00:27:04.454793 best dqsien dly found for B0: ( 1, 9, 14)
8924 00:27:04.457857 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8925 00:27:04.464742 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8926 00:27:04.464831
8927 00:27:04.467927 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8928 00:27:04.471261 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8929 00:27:04.474574 [Gating] SW calibration Done
8930 00:27:04.474659 ==
8931 00:27:04.477672 Dram Type= 6, Freq= 0, CH_1, rank 1
8932 00:27:04.481079 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8933 00:27:04.481164 ==
8934 00:27:04.484399 RX Vref Scan: 0
8935 00:27:04.484483
8936 00:27:04.484549 RX Vref 0 -> 0, step: 1
8937 00:27:04.484610
8938 00:27:04.487650 RX Delay 0 -> 252, step: 8
8939 00:27:04.491123 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8940 00:27:04.494756 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8941 00:27:04.501335 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8942 00:27:04.504131 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8943 00:27:04.507914 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8944 00:27:04.511147 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8945 00:27:04.514348 iDelay=208, Bit 6, Center 151 (96 ~ 207) 112
8946 00:27:04.520737 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8947 00:27:04.524389 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8948 00:27:04.527554 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8949 00:27:04.530651 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8950 00:27:04.537395 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8951 00:27:04.540912 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8952 00:27:04.543849 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8953 00:27:04.546996 iDelay=208, Bit 14, Center 131 (72 ~ 191) 120
8954 00:27:04.550858 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8955 00:27:04.553637 ==
8956 00:27:04.557198 Dram Type= 6, Freq= 0, CH_1, rank 1
8957 00:27:04.560203 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8958 00:27:04.560288 ==
8959 00:27:04.560356 DQS Delay:
8960 00:27:04.563537 DQS0 = 0, DQS1 = 0
8961 00:27:04.563621 DQM Delay:
8962 00:27:04.566942 DQM0 = 138, DQM1 = 128
8963 00:27:04.567026 DQ Delay:
8964 00:27:04.570332 DQ0 =143, DQ1 =135, DQ2 =123, DQ3 =135
8965 00:27:04.573997 DQ4 =135, DQ5 =151, DQ6 =151, DQ7 =135
8966 00:27:04.576647 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8967 00:27:04.580088 DQ12 =139, DQ13 =139, DQ14 =131, DQ15 =139
8968 00:27:04.580171
8969 00:27:04.580237
8970 00:27:04.583277 ==
8971 00:27:04.586453 Dram Type= 6, Freq= 0, CH_1, rank 1
8972 00:27:04.589800 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8973 00:27:04.589884 ==
8974 00:27:04.589950
8975 00:27:04.590010
8976 00:27:04.593063 TX Vref Scan disable
8977 00:27:04.593146 == TX Byte 0 ==
8978 00:27:04.596399 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8979 00:27:04.602846 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8980 00:27:04.602931 == TX Byte 1 ==
8981 00:27:04.609692 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8982 00:27:04.612621 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8983 00:27:04.612705 ==
8984 00:27:04.616054 Dram Type= 6, Freq= 0, CH_1, rank 1
8985 00:27:04.619287 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8986 00:27:04.619371 ==
8987 00:27:04.633317
8988 00:27:04.636550 TX Vref early break, caculate TX vref
8989 00:27:04.640226 TX Vref=16, minBit 1, minWin=22, winSum=382
8990 00:27:04.642886 TX Vref=18, minBit 0, minWin=23, winSum=396
8991 00:27:04.646742 TX Vref=20, minBit 0, minWin=24, winSum=399
8992 00:27:04.649504 TX Vref=22, minBit 0, minWin=24, winSum=409
8993 00:27:04.652671 TX Vref=24, minBit 0, minWin=24, winSum=413
8994 00:27:04.659648 TX Vref=26, minBit 13, minWin=25, winSum=426
8995 00:27:04.662940 TX Vref=28, minBit 0, minWin=25, winSum=420
8996 00:27:04.666137 TX Vref=30, minBit 0, minWin=24, winSum=415
8997 00:27:04.669438 TX Vref=32, minBit 0, minWin=24, winSum=409
8998 00:27:04.672520 TX Vref=34, minBit 0, minWin=23, winSum=401
8999 00:27:04.679527 [TxChooseVref] Worse bit 13, Min win 25, Win sum 426, Final Vref 26
9000 00:27:04.679608
9001 00:27:04.682587 Final TX Range 0 Vref 26
9002 00:27:04.682695
9003 00:27:04.682804 ==
9004 00:27:04.686075 Dram Type= 6, Freq= 0, CH_1, rank 1
9005 00:27:04.689229 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9006 00:27:04.689312 ==
9007 00:27:04.689378
9008 00:27:04.689439
9009 00:27:04.692579 TX Vref Scan disable
9010 00:27:04.699201 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
9011 00:27:04.699297 == TX Byte 0 ==
9012 00:27:04.702382 u2DelayCellOfst[0]=18 cells (5 PI)
9013 00:27:04.705674 u2DelayCellOfst[1]=11 cells (3 PI)
9014 00:27:04.709151 u2DelayCellOfst[2]=0 cells (0 PI)
9015 00:27:04.712035 u2DelayCellOfst[3]=7 cells (2 PI)
9016 00:27:04.715786 u2DelayCellOfst[4]=7 cells (2 PI)
9017 00:27:04.719212 u2DelayCellOfst[5]=22 cells (6 PI)
9018 00:27:04.722050 u2DelayCellOfst[6]=22 cells (6 PI)
9019 00:27:04.725486 u2DelayCellOfst[7]=3 cells (1 PI)
9020 00:27:04.728698 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
9021 00:27:04.731926 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
9022 00:27:04.735250 == TX Byte 1 ==
9023 00:27:04.738607 u2DelayCellOfst[8]=0 cells (0 PI)
9024 00:27:04.741694 u2DelayCellOfst[9]=3 cells (1 PI)
9025 00:27:04.745442 u2DelayCellOfst[10]=15 cells (4 PI)
9026 00:27:04.748171 u2DelayCellOfst[11]=3 cells (1 PI)
9027 00:27:04.751478 u2DelayCellOfst[12]=15 cells (4 PI)
9028 00:27:04.751553 u2DelayCellOfst[13]=15 cells (4 PI)
9029 00:27:04.755116 u2DelayCellOfst[14]=18 cells (5 PI)
9030 00:27:04.758436 u2DelayCellOfst[15]=18 cells (5 PI)
9031 00:27:04.764641 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
9032 00:27:04.768196 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
9033 00:27:04.768273 DramC Write-DBI on
9034 00:27:04.771955 ==
9035 00:27:04.774527 Dram Type= 6, Freq= 0, CH_1, rank 1
9036 00:27:04.778017 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9037 00:27:04.778121 ==
9038 00:27:04.778240
9039 00:27:04.778317
9040 00:27:04.781627 TX Vref Scan disable
9041 00:27:04.781729 == TX Byte 0 ==
9042 00:27:04.787883 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
9043 00:27:04.787990 == TX Byte 1 ==
9044 00:27:04.791092 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
9045 00:27:04.794862 DramC Write-DBI off
9046 00:27:04.794943
9047 00:27:04.795013 [DATLAT]
9048 00:27:04.797967 Freq=1600, CH1 RK1
9049 00:27:04.798078
9050 00:27:04.798195 DATLAT Default: 0xf
9051 00:27:04.801036 0, 0xFFFF, sum = 0
9052 00:27:04.801146 1, 0xFFFF, sum = 0
9053 00:27:04.804423 2, 0xFFFF, sum = 0
9054 00:27:04.804506 3, 0xFFFF, sum = 0
9055 00:27:04.807805 4, 0xFFFF, sum = 0
9056 00:27:04.811256 5, 0xFFFF, sum = 0
9057 00:27:04.811341 6, 0xFFFF, sum = 0
9058 00:27:04.814297 7, 0xFFFF, sum = 0
9059 00:27:04.814382 8, 0xFFFF, sum = 0
9060 00:27:04.817832 9, 0xFFFF, sum = 0
9061 00:27:04.817916 10, 0xFFFF, sum = 0
9062 00:27:04.820918 11, 0xFFFF, sum = 0
9063 00:27:04.821004 12, 0xFFFF, sum = 0
9064 00:27:04.824273 13, 0xFFFF, sum = 0
9065 00:27:04.824379 14, 0x0, sum = 1
9066 00:27:04.827998 15, 0x0, sum = 2
9067 00:27:04.828102 16, 0x0, sum = 3
9068 00:27:04.830978 17, 0x0, sum = 4
9069 00:27:04.831062 best_step = 15
9070 00:27:04.831126
9071 00:27:04.831186 ==
9072 00:27:04.834069 Dram Type= 6, Freq= 0, CH_1, rank 1
9073 00:27:04.837779 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9074 00:27:04.840990 ==
9075 00:27:04.841072 RX Vref Scan: 0
9076 00:27:04.841143
9077 00:27:04.844107 RX Vref 0 -> 0, step: 1
9078 00:27:04.844221
9079 00:27:04.847240 RX Delay 11 -> 252, step: 4
9080 00:27:04.850717 iDelay=199, Bit 0, Center 140 (87 ~ 194) 108
9081 00:27:04.854102 iDelay=199, Bit 1, Center 128 (75 ~ 182) 108
9082 00:27:04.857163 iDelay=199, Bit 2, Center 122 (67 ~ 178) 112
9083 00:27:04.863970 iDelay=199, Bit 3, Center 132 (83 ~ 182) 100
9084 00:27:04.867157 iDelay=199, Bit 4, Center 134 (79 ~ 190) 112
9085 00:27:04.870571 iDelay=199, Bit 5, Center 146 (95 ~ 198) 104
9086 00:27:04.874090 iDelay=199, Bit 6, Center 146 (95 ~ 198) 104
9087 00:27:04.877248 iDelay=199, Bit 7, Center 132 (83 ~ 182) 100
9088 00:27:04.883553 iDelay=199, Bit 8, Center 112 (55 ~ 170) 116
9089 00:27:04.886992 iDelay=199, Bit 9, Center 114 (59 ~ 170) 112
9090 00:27:04.890171 iDelay=199, Bit 10, Center 126 (71 ~ 182) 112
9091 00:27:04.893401 iDelay=199, Bit 11, Center 118 (67 ~ 170) 104
9092 00:27:04.900057 iDelay=199, Bit 12, Center 136 (83 ~ 190) 108
9093 00:27:04.903207 iDelay=199, Bit 13, Center 134 (79 ~ 190) 112
9094 00:27:04.906296 iDelay=199, Bit 14, Center 134 (79 ~ 190) 112
9095 00:27:04.909654 iDelay=199, Bit 15, Center 138 (83 ~ 194) 112
9096 00:27:04.909778 ==
9097 00:27:04.913016 Dram Type= 6, Freq= 0, CH_1, rank 1
9098 00:27:04.919504 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9099 00:27:04.919622 ==
9100 00:27:04.919726 DQS Delay:
9101 00:27:04.923272 DQS0 = 0, DQS1 = 0
9102 00:27:04.923385 DQM Delay:
9103 00:27:04.923489 DQM0 = 135, DQM1 = 126
9104 00:27:04.926095 DQ Delay:
9105 00:27:04.929522 DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =132
9106 00:27:04.932657 DQ4 =134, DQ5 =146, DQ6 =146, DQ7 =132
9107 00:27:04.936204 DQ8 =112, DQ9 =114, DQ10 =126, DQ11 =118
9108 00:27:04.939607 DQ12 =136, DQ13 =134, DQ14 =134, DQ15 =138
9109 00:27:04.939723
9110 00:27:04.939828
9111 00:27:04.939927
9112 00:27:04.942573 [DramC_TX_OE_Calibration] TA2
9113 00:27:04.945755 Original DQ_B0 (3 6) =30, OEN = 27
9114 00:27:04.949295 Original DQ_B1 (3 6) =30, OEN = 27
9115 00:27:04.952533 24, 0x0, End_B0=24 End_B1=24
9116 00:27:04.955966 25, 0x0, End_B0=25 End_B1=25
9117 00:27:04.956081 26, 0x0, End_B0=26 End_B1=26
9118 00:27:04.959020 27, 0x0, End_B0=27 End_B1=27
9119 00:27:04.962343 28, 0x0, End_B0=28 End_B1=28
9120 00:27:04.965804 29, 0x0, End_B0=29 End_B1=29
9121 00:27:04.965921 30, 0x0, End_B0=30 End_B1=30
9122 00:27:04.969176 31, 0x4141, End_B0=30 End_B1=30
9123 00:27:04.972188 Byte0 end_step=30 best_step=27
9124 00:27:04.975447 Byte1 end_step=30 best_step=27
9125 00:27:04.978782 Byte0 TX OE(2T, 0.5T) = (3, 3)
9126 00:27:04.982082 Byte1 TX OE(2T, 0.5T) = (3, 3)
9127 00:27:04.982237
9128 00:27:04.982340
9129 00:27:04.989204 [DQSOSCAuto] RK1, (LSB)MR18= 0xc0a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 403 ps
9130 00:27:04.992181 CH1 RK1: MR19=303, MR18=C0A
9131 00:27:04.998820 CH1_RK1: MR19=0x303, MR18=0xC0A, DQSOSC=403, MR23=63, INC=22, DEC=15
9132 00:27:05.002401 [RxdqsGatingPostProcess] freq 1600
9133 00:27:05.005110 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9134 00:27:05.008638 best DQS0 dly(2T, 0.5T) = (1, 1)
9135 00:27:05.011839 best DQS1 dly(2T, 0.5T) = (1, 1)
9136 00:27:05.014874 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9137 00:27:05.018318 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9138 00:27:05.021811 best DQS0 dly(2T, 0.5T) = (1, 1)
9139 00:27:05.025474 best DQS1 dly(2T, 0.5T) = (1, 1)
9140 00:27:05.028613 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9141 00:27:05.031889 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9142 00:27:05.034891 Pre-setting of DQS Precalculation
9143 00:27:05.038007 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9144 00:27:05.044903 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9145 00:27:05.054726 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9146 00:27:05.054842
9147 00:27:05.054947
9148 00:27:05.057928 [Calibration Summary] 3200 Mbps
9149 00:27:05.058042 CH 0, Rank 0
9150 00:27:05.061527 SW Impedance : PASS
9151 00:27:05.061643 DUTY Scan : NO K
9152 00:27:05.064773 ZQ Calibration : PASS
9153 00:27:05.068206 Jitter Meter : NO K
9154 00:27:05.068319 CBT Training : PASS
9155 00:27:05.071293 Write leveling : PASS
9156 00:27:05.074606 RX DQS gating : PASS
9157 00:27:05.074721 RX DQ/DQS(RDDQC) : PASS
9158 00:27:05.078253 TX DQ/DQS : PASS
9159 00:27:05.081332 RX DATLAT : PASS
9160 00:27:05.081449 RX DQ/DQS(Engine): PASS
9161 00:27:05.084575 TX OE : PASS
9162 00:27:05.084740 All Pass.
9163 00:27:05.084844
9164 00:27:05.087838 CH 0, Rank 1
9165 00:27:05.087977 SW Impedance : PASS
9166 00:27:05.091020 DUTY Scan : NO K
9167 00:27:05.094481 ZQ Calibration : PASS
9168 00:27:05.094594 Jitter Meter : NO K
9169 00:27:05.097750 CBT Training : PASS
9170 00:27:05.097861 Write leveling : PASS
9171 00:27:05.101024 RX DQS gating : PASS
9172 00:27:05.104563 RX DQ/DQS(RDDQC) : PASS
9173 00:27:05.104680 TX DQ/DQS : PASS
9174 00:27:05.107972 RX DATLAT : PASS
9175 00:27:05.110656 RX DQ/DQS(Engine): PASS
9176 00:27:05.110768 TX OE : PASS
9177 00:27:05.114127 All Pass.
9178 00:27:05.114277
9179 00:27:05.114379 CH 1, Rank 0
9180 00:27:05.117520 SW Impedance : PASS
9181 00:27:05.117633 DUTY Scan : NO K
9182 00:27:05.120881 ZQ Calibration : PASS
9183 00:27:05.124046 Jitter Meter : NO K
9184 00:27:05.124168 CBT Training : PASS
9185 00:27:05.127163 Write leveling : PASS
9186 00:27:05.130698 RX DQS gating : PASS
9187 00:27:05.130784 RX DQ/DQS(RDDQC) : PASS
9188 00:27:05.133992 TX DQ/DQS : PASS
9189 00:27:05.137258 RX DATLAT : PASS
9190 00:27:05.137377 RX DQ/DQS(Engine): PASS
9191 00:27:05.140733 TX OE : PASS
9192 00:27:05.140818 All Pass.
9193 00:27:05.140905
9194 00:27:05.143634 CH 1, Rank 1
9195 00:27:05.143719 SW Impedance : PASS
9196 00:27:05.147472 DUTY Scan : NO K
9197 00:27:05.150381 ZQ Calibration : PASS
9198 00:27:05.150466 Jitter Meter : NO K
9199 00:27:05.153657 CBT Training : PASS
9200 00:27:05.157290 Write leveling : PASS
9201 00:27:05.157375 RX DQS gating : PASS
9202 00:27:05.160346 RX DQ/DQS(RDDQC) : PASS
9203 00:27:05.163891 TX DQ/DQS : PASS
9204 00:27:05.163978 RX DATLAT : PASS
9205 00:27:05.167346 RX DQ/DQS(Engine): PASS
9206 00:27:05.167432 TX OE : PASS
9207 00:27:05.170311 All Pass.
9208 00:27:05.170396
9209 00:27:05.170483 DramC Write-DBI on
9210 00:27:05.173305 PER_BANK_REFRESH: Hybrid Mode
9211 00:27:05.176891 TX_TRACKING: ON
9212 00:27:05.183488 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9213 00:27:05.193498 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9214 00:27:05.200001 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9215 00:27:05.203351 [FAST_K] Save calibration result to emmc
9216 00:27:05.206515 sync common calibartion params.
9217 00:27:05.209535 sync cbt_mode0:1, 1:1
9218 00:27:05.209651 dram_init: ddr_geometry: 2
9219 00:27:05.212855 dram_init: ddr_geometry: 2
9220 00:27:05.216027 dram_init: ddr_geometry: 2
9221 00:27:05.216141 0:dram_rank_size:100000000
9222 00:27:05.219444 1:dram_rank_size:100000000
9223 00:27:05.226012 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9224 00:27:05.229076 DFS_SHUFFLE_HW_MODE: ON
9225 00:27:05.232567 dramc_set_vcore_voltage set vcore to 725000
9226 00:27:05.232681 Read voltage for 1600, 0
9227 00:27:05.235941 Vio18 = 0
9228 00:27:05.236056 Vcore = 725000
9229 00:27:05.236159 Vdram = 0
9230 00:27:05.239306 Vddq = 0
9231 00:27:05.239398 Vmddr = 0
9232 00:27:05.242459 switch to 3200 Mbps bootup
9233 00:27:05.242545 [DramcRunTimeConfig]
9234 00:27:05.245621 PHYPLL
9235 00:27:05.245707 DPM_CONTROL_AFTERK: ON
9236 00:27:05.249318 PER_BANK_REFRESH: ON
9237 00:27:05.252045 REFRESH_OVERHEAD_REDUCTION: ON
9238 00:27:05.252132 CMD_PICG_NEW_MODE: OFF
9239 00:27:05.255546 XRTWTW_NEW_MODE: ON
9240 00:27:05.255631 XRTRTR_NEW_MODE: ON
9241 00:27:05.258888 TX_TRACKING: ON
9242 00:27:05.258978 RDSEL_TRACKING: OFF
9243 00:27:05.262097 DQS Precalculation for DVFS: ON
9244 00:27:05.265470 RX_TRACKING: OFF
9245 00:27:05.265556 HW_GATING DBG: ON
9246 00:27:05.268926 ZQCS_ENABLE_LP4: ON
9247 00:27:05.269035 RX_PICG_NEW_MODE: ON
9248 00:27:05.272498 TX_PICG_NEW_MODE: ON
9249 00:27:05.272586 ENABLE_RX_DCM_DPHY: ON
9250 00:27:05.275432 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9251 00:27:05.278959 DUMMY_READ_FOR_TRACKING: OFF
9252 00:27:05.282011 !!! SPM_CONTROL_AFTERK: OFF
9253 00:27:05.285200 !!! SPM could not control APHY
9254 00:27:05.285287 IMPEDANCE_TRACKING: ON
9255 00:27:05.288659 TEMP_SENSOR: ON
9256 00:27:05.288755 HW_SAVE_FOR_SR: OFF
9257 00:27:05.292048 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9258 00:27:05.295251 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9259 00:27:05.298592 Read ODT Tracking: ON
9260 00:27:05.302224 Refresh Rate DeBounce: ON
9261 00:27:05.302311 DFS_NO_QUEUE_FLUSH: ON
9262 00:27:05.305013 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9263 00:27:05.309058 ENABLE_DFS_RUNTIME_MRW: OFF
9264 00:27:05.311866 DDR_RESERVE_NEW_MODE: ON
9265 00:27:05.311953 MR_CBT_SWITCH_FREQ: ON
9266 00:27:05.315073 =========================
9267 00:27:05.334051 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9268 00:27:05.337486 dram_init: ddr_geometry: 2
9269 00:27:05.355594 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9270 00:27:05.359020 dram_init: dram init end (result: 0)
9271 00:27:05.365713 DRAM-K: Full calibration passed in 24652 msecs
9272 00:27:05.368428 MRC: failed to locate region type 0.
9273 00:27:05.368515 DRAM rank0 size:0x100000000,
9274 00:27:05.371980 DRAM rank1 size=0x100000000
9275 00:27:05.381792 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9276 00:27:05.388160 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9277 00:27:05.398416 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9278 00:27:05.404763 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9279 00:27:05.404851 DRAM rank0 size:0x100000000,
9280 00:27:05.408226 DRAM rank1 size=0x100000000
9281 00:27:05.408351 CBMEM:
9282 00:27:05.411060 IMD: root @ 0xfffff000 254 entries.
9283 00:27:05.414715 IMD: root @ 0xffffec00 62 entries.
9284 00:27:05.421416 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9285 00:27:05.424681 WARNING: RO_VPD is uninitialized or empty.
9286 00:27:05.428122 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9287 00:27:05.435664 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9288 00:27:05.448532 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9289 00:27:05.459779 BS: romstage times (exec / console): total (unknown) / 24138 ms
9290 00:27:05.459869
9291 00:27:05.459955
9292 00:27:05.469671 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9293 00:27:05.473113 ARM64: Exception handlers installed.
9294 00:27:05.476368 ARM64: Testing exception
9295 00:27:05.479317 ARM64: Done test exception
9296 00:27:05.479403 Enumerating buses...
9297 00:27:05.482826 Show all devs... Before device enumeration.
9298 00:27:05.485964 Root Device: enabled 1
9299 00:27:05.489714 CPU_CLUSTER: 0: enabled 1
9300 00:27:05.489798 CPU: 00: enabled 1
9301 00:27:05.493033 Compare with tree...
9302 00:27:05.493118 Root Device: enabled 1
9303 00:27:05.496243 CPU_CLUSTER: 0: enabled 1
9304 00:27:05.499843 CPU: 00: enabled 1
9305 00:27:05.499930 Root Device scanning...
9306 00:27:05.502792 scan_static_bus for Root Device
9307 00:27:05.506138 CPU_CLUSTER: 0 enabled
9308 00:27:05.509533 scan_static_bus for Root Device done
9309 00:27:05.512663 scan_bus: bus Root Device finished in 8 msecs
9310 00:27:05.512749 done
9311 00:27:05.519243 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9312 00:27:05.522749 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9313 00:27:05.529233 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9314 00:27:05.532461 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9315 00:27:05.535715 Allocating resources...
9316 00:27:05.539140 Reading resources...
9317 00:27:05.542371 Root Device read_resources bus 0 link: 0
9318 00:27:05.542457 DRAM rank0 size:0x100000000,
9319 00:27:05.546068 DRAM rank1 size=0x100000000
9320 00:27:05.549067 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9321 00:27:05.552146 CPU: 00 missing read_resources
9322 00:27:05.559207 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9323 00:27:05.562398 Root Device read_resources bus 0 link: 0 done
9324 00:27:05.562484 Done reading resources.
9325 00:27:05.569101 Show resources in subtree (Root Device)...After reading.
9326 00:27:05.572374 Root Device child on link 0 CPU_CLUSTER: 0
9327 00:27:05.575570 CPU_CLUSTER: 0 child on link 0 CPU: 00
9328 00:27:05.585315 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9329 00:27:05.585430 CPU: 00
9330 00:27:05.588590 Root Device assign_resources, bus 0 link: 0
9331 00:27:05.591896 CPU_CLUSTER: 0 missing set_resources
9332 00:27:05.598752 Root Device assign_resources, bus 0 link: 0 done
9333 00:27:05.598837 Done setting resources.
9334 00:27:05.605480 Show resources in subtree (Root Device)...After assigning values.
9335 00:27:05.608569 Root Device child on link 0 CPU_CLUSTER: 0
9336 00:27:05.611862 CPU_CLUSTER: 0 child on link 0 CPU: 00
9337 00:27:05.621842 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9338 00:27:05.621937 CPU: 00
9339 00:27:05.624968 Done allocating resources.
9340 00:27:05.631481 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9341 00:27:05.631565 Enabling resources...
9342 00:27:05.631631 done.
9343 00:27:05.638063 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9344 00:27:05.641481 Initializing devices...
9345 00:27:05.641565 Root Device init
9346 00:27:05.644708 init hardware done!
9347 00:27:05.644791 0x00000018: ctrlr->caps
9348 00:27:05.648067 52.000 MHz: ctrlr->f_max
9349 00:27:05.651461 0.400 MHz: ctrlr->f_min
9350 00:27:05.651546 0x40ff8080: ctrlr->voltages
9351 00:27:05.654476 sclk: 390625
9352 00:27:05.654558 Bus Width = 1
9353 00:27:05.654639 sclk: 390625
9354 00:27:05.657730 Bus Width = 1
9355 00:27:05.661662 Early init status = 3
9356 00:27:05.665097 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9357 00:27:05.667871 in-header: 03 fc 00 00 01 00 00 00
9358 00:27:05.671373 in-data: 00
9359 00:27:05.674483 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9360 00:27:05.679095 in-header: 03 fd 00 00 00 00 00 00
9361 00:27:05.682390 in-data:
9362 00:27:05.685689 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9363 00:27:05.690079 in-header: 03 fc 00 00 01 00 00 00
9364 00:27:05.693393 in-data: 00
9365 00:27:05.697078 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9366 00:27:05.702437 in-header: 03 fd 00 00 00 00 00 00
9367 00:27:05.705479 in-data:
9368 00:27:05.708753 [SSUSB] Setting up USB HOST controller...
9369 00:27:05.712315 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9370 00:27:05.715395 [SSUSB] phy power-on done.
9371 00:27:05.718624 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9372 00:27:05.725193 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9373 00:27:05.728674 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9374 00:27:05.735357 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9375 00:27:05.741543 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9376 00:27:05.748006 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9377 00:27:05.754757 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9378 00:27:05.761131 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9379 00:27:05.764716 SPM: binary array size = 0x9dc
9380 00:27:05.771046 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9381 00:27:05.774501 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9382 00:27:05.784231 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9383 00:27:05.787751 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9384 00:27:05.790838 configure_display: Starting display init
9385 00:27:05.825597 anx7625_power_on_init: Init interface.
9386 00:27:05.829011 anx7625_disable_pd_protocol: Disabled PD feature.
9387 00:27:05.831914 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9388 00:27:05.859794 anx7625_start_dp_work: Secure OCM version=00
9389 00:27:05.863317 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9390 00:27:05.878569 sp_tx_get_edid_block: EDID Block = 1
9391 00:27:05.980704 Extracted contents:
9392 00:27:05.983894 header: 00 ff ff ff ff ff ff 00
9393 00:27:05.987541 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9394 00:27:05.990702 version: 01 04
9395 00:27:05.993996 basic params: 95 1f 11 78 0a
9396 00:27:05.997217 chroma info: 76 90 94 55 54 90 27 21 50 54
9397 00:27:06.000682 established: 00 00 00
9398 00:27:06.007040 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9399 00:27:06.013646 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9400 00:27:06.016844 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9401 00:27:06.023631 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9402 00:27:06.029946 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9403 00:27:06.033186 extensions: 00
9404 00:27:06.033270 checksum: fb
9405 00:27:06.033336
9406 00:27:06.039781 Manufacturer: IVO Model 57d Serial Number 0
9407 00:27:06.039865 Made week 0 of 2020
9408 00:27:06.043103 EDID version: 1.4
9409 00:27:06.043186 Digital display
9410 00:27:06.046386 6 bits per primary color channel
9411 00:27:06.046471 DisplayPort interface
9412 00:27:06.049655 Maximum image size: 31 cm x 17 cm
9413 00:27:06.053036 Gamma: 220%
9414 00:27:06.053118 Check DPMS levels
9415 00:27:06.059683 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9416 00:27:06.063677 First detailed timing is preferred timing
9417 00:27:06.063761 Established timings supported:
9418 00:27:06.066388 Standard timings supported:
9419 00:27:06.069716 Detailed timings
9420 00:27:06.072893 Hex of detail: 383680a07038204018303c0035ae10000019
9421 00:27:06.079866 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9422 00:27:06.082899 0780 0798 07c8 0820 hborder 0
9423 00:27:06.086463 0438 043b 0447 0458 vborder 0
9424 00:27:06.089463 -hsync -vsync
9425 00:27:06.089546 Did detailed timing
9426 00:27:06.096192 Hex of detail: 000000000000000000000000000000000000
9427 00:27:06.099371 Manufacturer-specified data, tag 0
9428 00:27:06.102722 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9429 00:27:06.106271 ASCII string: InfoVision
9430 00:27:06.109730 Hex of detail: 000000fe00523134304e574635205248200a
9431 00:27:06.113074 ASCII string: R140NWF5 RH
9432 00:27:06.113157 Checksum
9433 00:27:06.116350 Checksum: 0xfb (valid)
9434 00:27:06.119594 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9435 00:27:06.122836 DSI data_rate: 832800000 bps
9436 00:27:06.129041 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9437 00:27:06.132721 anx7625_parse_edid: pixelclock(138800).
9438 00:27:06.136008 hactive(1920), hsync(48), hfp(24), hbp(88)
9439 00:27:06.139084 vactive(1080), vsync(12), vfp(3), vbp(17)
9440 00:27:06.142509 anx7625_dsi_config: config dsi.
9441 00:27:06.149372 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9442 00:27:06.162595 anx7625_dsi_config: success to config DSI
9443 00:27:06.165887 anx7625_dp_start: MIPI phy setup OK.
9444 00:27:06.169349 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9445 00:27:06.172557 mtk_ddp_mode_set invalid vrefresh 60
9446 00:27:06.175808 main_disp_path_setup
9447 00:27:06.175891 ovl_layer_smi_id_en
9448 00:27:06.178968 ovl_layer_smi_id_en
9449 00:27:06.179056 ccorr_config
9450 00:27:06.179121 aal_config
9451 00:27:06.182098 gamma_config
9452 00:27:06.182238 postmask_config
9453 00:27:06.185865 dither_config
9454 00:27:06.188833 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9455 00:27:06.195191 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9456 00:27:06.199019 Root Device init finished in 554 msecs
9457 00:27:06.201845 CPU_CLUSTER: 0 init
9458 00:27:06.208404 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9459 00:27:06.215437 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9460 00:27:06.215537 APU_MBOX 0x190000b0 = 0x10001
9461 00:27:06.218561 APU_MBOX 0x190001b0 = 0x10001
9462 00:27:06.222057 APU_MBOX 0x190005b0 = 0x10001
9463 00:27:06.225212 APU_MBOX 0x190006b0 = 0x10001
9464 00:27:06.231438 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9465 00:27:06.241693 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9466 00:27:06.254370 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9467 00:27:06.260696 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9468 00:27:06.272326 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9469 00:27:06.281306 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9470 00:27:06.285019 CPU_CLUSTER: 0 init finished in 81 msecs
9471 00:27:06.287924 Devices initialized
9472 00:27:06.291186 Show all devs... After init.
9473 00:27:06.291272 Root Device: enabled 1
9474 00:27:06.294559 CPU_CLUSTER: 0: enabled 1
9475 00:27:06.297732 CPU: 00: enabled 1
9476 00:27:06.301474 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9477 00:27:06.305192 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9478 00:27:06.307994 ELOG: NV offset 0x57f000 size 0x1000
9479 00:27:06.314531 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9480 00:27:06.321011 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9481 00:27:06.324300 ELOG: Event(17) added with size 13 at 2024-06-21 00:27:06 UTC
9482 00:27:06.330994 out: cmd=0x121: 03 db 21 01 00 00 00 00
9483 00:27:06.334581 in-header: 03 b7 00 00 2c 00 00 00
9484 00:27:06.347625 in-data: 86 72 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9485 00:27:06.351339 ELOG: Event(A1) added with size 10 at 2024-06-21 00:27:06 UTC
9486 00:27:06.357760 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9487 00:27:06.363872 ELOG: Event(A0) added with size 9 at 2024-06-21 00:27:06 UTC
9488 00:27:06.367869 elog_add_boot_reason: Logged dev mode boot
9489 00:27:06.374140 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9490 00:27:06.374236 Finalize devices...
9491 00:27:06.377579 Devices finalized
9492 00:27:06.381032 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9493 00:27:06.383876 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9494 00:27:06.386991 in-header: 03 07 00 00 08 00 00 00
9495 00:27:06.390783 in-data: aa e4 47 04 13 02 00 00
9496 00:27:06.393890 Chrome EC: UHEPI supported
9497 00:27:06.400508 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9498 00:27:06.403631 in-header: 03 a9 00 00 08 00 00 00
9499 00:27:06.407016 in-data: 84 60 60 08 00 00 00 00
9500 00:27:06.413373 ELOG: Event(91) added with size 10 at 2024-06-21 00:27:06 UTC
9501 00:27:06.416930 ELOG: Event(16) added with size 11 at 2024-06-21 00:27:06 UTC
9502 00:27:06.500559 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9503 00:27:06.503868 Chrome EC: clear events_b mask to 0x0000000020004000
9504 00:27:06.510460 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9505 00:27:06.514682 in-header: 03 fd 00 00 00 00 00 00
9506 00:27:06.518439 in-data:
9507 00:27:06.521511 BS: BS_WRITE_TABLES entry times (exec / console): 80 / 56 ms
9508 00:27:06.524568 Writing coreboot table at 0xffe64000
9509 00:27:06.531611 0. 000000000010a000-0000000000113fff: RAMSTAGE
9510 00:27:06.535208 1. 0000000040000000-00000000400fffff: RAM
9511 00:27:06.537730 2. 0000000040100000-000000004032afff: RAMSTAGE
9512 00:27:06.541344 3. 000000004032b000-00000000545fffff: RAM
9513 00:27:06.544982 4. 0000000054600000-000000005465ffff: BL31
9514 00:27:06.548362 5. 0000000054660000-00000000ffe63fff: RAM
9515 00:27:06.554482 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9516 00:27:06.557560 7. 0000000100000000-000000023fffffff: RAM
9517 00:27:06.561170 Passing 5 GPIOs to payload:
9518 00:27:06.564392 NAME | PORT | POLARITY | VALUE
9519 00:27:06.570941 EC in RW | 0x000000aa | low | undefined
9520 00:27:06.574339 EC interrupt | 0x00000005 | low | undefined
9521 00:27:06.580918 TPM interrupt | 0x000000ab | high | undefined
9522 00:27:06.583922 SD card detect | 0x00000011 | high | undefined
9523 00:27:06.587515 speaker enable | 0x00000093 | high | undefined
9524 00:27:06.590978 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9525 00:27:06.594088 in-header: 03 f9 00 00 02 00 00 00
9526 00:27:06.597326 in-data: 02 00
9527 00:27:06.600896 ADC[4]: Raw value=903031 ID=7
9528 00:27:06.604128 ADC[3]: Raw value=212912 ID=1
9529 00:27:06.604226 RAM Code: 0x71
9530 00:27:06.607674 ADC[6]: Raw value=75036 ID=0
9531 00:27:06.610647 ADC[5]: Raw value=212912 ID=1
9532 00:27:06.610744 SKU Code: 0x1
9533 00:27:06.617125 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 9c60
9534 00:27:06.617246 coreboot table: 964 bytes.
9535 00:27:06.620735 IMD ROOT 0. 0xfffff000 0x00001000
9536 00:27:06.624107 IMD SMALL 1. 0xffffe000 0x00001000
9537 00:27:06.627623 RO MCACHE 2. 0xffffc000 0x00001104
9538 00:27:06.630735 CONSOLE 3. 0xfff7c000 0x00080000
9539 00:27:06.633978 FMAP 4. 0xfff7b000 0x00000452
9540 00:27:06.637406 TIME STAMP 5. 0xfff7a000 0x00000910
9541 00:27:06.640739 VBOOT WORK 6. 0xfff66000 0x00014000
9542 00:27:06.643774 RAMOOPS 7. 0xffe66000 0x00100000
9543 00:27:06.646988 COREBOOT 8. 0xffe64000 0x00002000
9544 00:27:06.650369 IMD small region:
9545 00:27:06.653850 IMD ROOT 0. 0xffffec00 0x00000400
9546 00:27:06.657365 VPD 1. 0xffffeb80 0x0000006c
9547 00:27:06.660571 MMC STATUS 2. 0xffffeb60 0x00000004
9548 00:27:06.663663 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9549 00:27:06.670361 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9550 00:27:06.711545 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9551 00:27:06.714787 Checking segment from ROM address 0x40100000
9552 00:27:06.721973 Checking segment from ROM address 0x4010001c
9553 00:27:06.724800 Loading segment from ROM address 0x40100000
9554 00:27:06.724892 code (compression=0)
9555 00:27:06.735033 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9556 00:27:06.741423 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9557 00:27:06.741524 it's not compressed!
9558 00:27:06.747943 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9559 00:27:06.754370 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9560 00:27:06.772188 Loading segment from ROM address 0x4010001c
9561 00:27:06.772285 Entry Point 0x80000000
9562 00:27:06.775559 Loaded segments
9563 00:27:06.778846 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9564 00:27:06.785958 Jumping to boot code at 0x80000000(0xffe64000)
9565 00:27:06.791926 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9566 00:27:06.798779 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9567 00:27:06.806649 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9568 00:27:06.809792 Checking segment from ROM address 0x40100000
9569 00:27:06.813257 Checking segment from ROM address 0x4010001c
9570 00:27:06.820160 Loading segment from ROM address 0x40100000
9571 00:27:06.820254 code (compression=1)
9572 00:27:06.826446 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9573 00:27:06.836017 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9574 00:27:06.836161 using LZMA
9575 00:27:06.845064 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9576 00:27:06.852000 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9577 00:27:06.854917 Loading segment from ROM address 0x4010001c
9578 00:27:06.855004 Entry Point 0x54601000
9579 00:27:06.858489 Loaded segments
9580 00:27:06.861530 NOTICE: MT8192 bl31_setup
9581 00:27:06.868686 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9582 00:27:06.871899 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9583 00:27:06.875120 WARNING: region 0:
9584 00:27:06.878902 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9585 00:27:06.878989 WARNING: region 1:
9586 00:27:06.884996 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9587 00:27:06.888427 WARNING: region 2:
9588 00:27:06.891572 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9589 00:27:06.895308 WARNING: region 3:
9590 00:27:06.898664 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9591 00:27:06.902114 WARNING: region 4:
9592 00:27:06.908399 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9593 00:27:06.908488 WARNING: region 5:
9594 00:27:06.911813 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9595 00:27:06.915126 WARNING: region 6:
9596 00:27:06.918131 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9597 00:27:06.921851 WARNING: region 7:
9598 00:27:06.924743 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9599 00:27:06.931754 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9600 00:27:06.934867 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9601 00:27:06.941302 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9602 00:27:06.944579 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9603 00:27:06.947744 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9604 00:27:06.954827 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9605 00:27:06.957683 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9606 00:27:06.961491 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9607 00:27:06.967543 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9608 00:27:06.971212 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9609 00:27:06.977858 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9610 00:27:06.981209 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9611 00:27:06.984274 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9612 00:27:06.990900 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9613 00:27:06.994450 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9614 00:27:06.997665 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9615 00:27:07.004047 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9616 00:27:07.007442 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9617 00:27:07.014144 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9618 00:27:07.017277 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9619 00:27:07.020561 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9620 00:27:07.027011 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9621 00:27:07.030533 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9622 00:27:07.037006 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9623 00:27:07.040355 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9624 00:27:07.043514 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9625 00:27:07.050264 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9626 00:27:07.053823 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9627 00:27:07.060099 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9628 00:27:07.063242 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9629 00:27:07.070003 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9630 00:27:07.073307 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9631 00:27:07.076414 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9632 00:27:07.080136 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9633 00:27:07.086502 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9634 00:27:07.090064 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9635 00:27:07.093000 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9636 00:27:07.096347 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9637 00:27:07.102888 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9638 00:27:07.106079 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9639 00:27:07.109992 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9640 00:27:07.112537 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9641 00:27:07.119377 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9642 00:27:07.123202 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9643 00:27:07.126282 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9644 00:27:07.132729 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9645 00:27:07.135804 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9646 00:27:07.139360 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9647 00:27:07.145870 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9648 00:27:07.149380 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9649 00:27:07.152585 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9650 00:27:07.159130 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9651 00:27:07.162704 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9652 00:27:07.169322 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9653 00:27:07.172504 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9654 00:27:07.179053 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9655 00:27:07.182823 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9656 00:27:07.185567 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9657 00:27:07.192003 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9658 00:27:07.195683 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9659 00:27:07.202027 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9660 00:27:07.205611 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9661 00:27:07.211981 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9662 00:27:07.215446 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9663 00:27:07.221701 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9664 00:27:07.225855 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9665 00:27:07.228415 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9666 00:27:07.235627 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9667 00:27:07.238643 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9668 00:27:07.244949 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9669 00:27:07.248567 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9670 00:27:07.254964 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9671 00:27:07.258294 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9672 00:27:07.264756 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9673 00:27:07.268072 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9674 00:27:07.271343 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9675 00:27:07.277998 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9676 00:27:07.281721 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9677 00:27:07.287865 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9678 00:27:07.291341 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9679 00:27:07.297962 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9680 00:27:07.301042 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9681 00:27:07.307825 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9682 00:27:07.311257 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9683 00:27:07.314775 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9684 00:27:07.320949 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9685 00:27:07.324515 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9686 00:27:07.331361 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9687 00:27:07.334586 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9688 00:27:07.340862 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9689 00:27:07.344179 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9690 00:27:07.347457 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9691 00:27:07.354513 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9692 00:27:07.357430 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9693 00:27:07.363999 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9694 00:27:07.367580 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9695 00:27:07.374050 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9696 00:27:07.377291 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9697 00:27:07.380975 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9698 00:27:07.383775 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9699 00:27:07.390402 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9700 00:27:07.393710 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9701 00:27:07.397161 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9702 00:27:07.403688 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9703 00:27:07.407096 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9704 00:27:07.413899 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9705 00:27:07.417363 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9706 00:27:07.420601 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9707 00:27:07.426986 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9708 00:27:07.430123 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9709 00:27:07.436824 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9710 00:27:07.440374 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9711 00:27:07.446709 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9712 00:27:07.450406 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9713 00:27:07.453747 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9714 00:27:07.460193 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9715 00:27:07.463348 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9716 00:27:07.466856 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9717 00:27:07.473316 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9718 00:27:07.476694 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9719 00:27:07.479987 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9720 00:27:07.483512 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9721 00:27:07.490330 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9722 00:27:07.493088 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9723 00:27:07.496482 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9724 00:27:07.503273 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9725 00:27:07.506218 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9726 00:27:07.513141 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9727 00:27:07.516470 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9728 00:27:07.519376 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9729 00:27:07.526147 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9730 00:27:07.529604 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9731 00:27:07.533056 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9732 00:27:07.539357 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9733 00:27:07.542777 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9734 00:27:07.549569 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9735 00:27:07.552702 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9736 00:27:07.556206 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9737 00:27:07.562860 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9738 00:27:07.565862 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9739 00:27:07.572767 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9740 00:27:07.575905 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9741 00:27:07.578975 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9742 00:27:07.585961 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9743 00:27:07.589041 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9744 00:27:07.595549 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9745 00:27:07.598800 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9746 00:27:07.602139 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9747 00:27:07.608711 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9748 00:27:07.612075 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9749 00:27:07.618847 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9750 00:27:07.622016 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9751 00:27:07.625328 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9752 00:27:07.632154 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9753 00:27:07.635395 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9754 00:27:07.642038 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9755 00:27:07.645172 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9756 00:27:07.648649 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9757 00:27:07.655233 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9758 00:27:07.658677 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9759 00:27:07.664781 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9760 00:27:07.668257 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9761 00:27:07.671922 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9762 00:27:07.677876 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9763 00:27:07.681266 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9764 00:27:07.687856 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9765 00:27:07.691207 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9766 00:27:07.694141 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9767 00:27:07.701227 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9768 00:27:07.704188 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9769 00:27:07.711219 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9770 00:27:07.714353 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9771 00:27:07.717477 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9772 00:27:07.724384 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9773 00:27:07.727522 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9774 00:27:07.734359 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9775 00:27:07.737469 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9776 00:27:07.740867 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9777 00:27:07.747229 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9778 00:27:07.750654 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9779 00:27:07.757462 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9780 00:27:07.760641 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9781 00:27:07.763751 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9782 00:27:07.771005 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9783 00:27:07.773793 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9784 00:27:07.780370 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9785 00:27:07.783948 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9786 00:27:07.787140 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9787 00:27:07.793498 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9788 00:27:07.796861 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9789 00:27:07.803844 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9790 00:27:07.806673 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9791 00:27:07.813487 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9792 00:27:07.817221 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9793 00:27:07.820346 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9794 00:27:07.826631 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9795 00:27:07.829721 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9796 00:27:07.836809 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9797 00:27:07.839891 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9798 00:27:07.846790 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9799 00:27:07.849814 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9800 00:27:07.852977 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9801 00:27:07.859764 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9802 00:27:07.863250 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9803 00:27:07.869766 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9804 00:27:07.873245 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9805 00:27:07.876235 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9806 00:27:07.883074 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9807 00:27:07.886379 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9808 00:27:07.892557 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9809 00:27:07.896181 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9810 00:27:07.902471 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9811 00:27:07.906085 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9812 00:27:07.909294 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9813 00:27:07.915667 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9814 00:27:07.919164 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9815 00:27:07.925872 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9816 00:27:07.928997 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9817 00:27:07.936195 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9818 00:27:07.939454 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9819 00:27:07.942556 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9820 00:27:07.949099 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9821 00:27:07.952466 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9822 00:27:07.959239 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9823 00:27:07.962068 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9824 00:27:07.968896 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9825 00:27:07.971783 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9826 00:27:07.975137 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9827 00:27:07.982100 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9828 00:27:07.985083 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9829 00:27:07.988376 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9830 00:27:07.991575 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9831 00:27:07.998439 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9832 00:27:08.001849 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9833 00:27:08.004846 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9834 00:27:08.011519 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9835 00:27:08.014641 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9836 00:27:08.021331 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9837 00:27:08.024666 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9838 00:27:08.028058 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9839 00:27:08.034595 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9840 00:27:08.038008 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9841 00:27:08.041353 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9842 00:27:08.048058 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9843 00:27:08.051398 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9844 00:27:08.054267 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9845 00:27:08.061009 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9846 00:27:08.064584 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9847 00:27:08.068044 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9848 00:27:08.074428 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9849 00:27:08.077996 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9850 00:27:08.084657 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9851 00:27:08.087710 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9852 00:27:08.090775 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9853 00:27:08.097359 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9854 00:27:08.101094 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9855 00:27:08.107588 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9856 00:27:08.110806 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9857 00:27:08.114149 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9858 00:27:08.120700 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9859 00:27:08.124450 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9860 00:27:08.127651 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9861 00:27:08.133981 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9862 00:27:08.137211 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9863 00:27:08.140519 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9864 00:27:08.147150 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9865 00:27:08.150453 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9866 00:27:08.157183 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9867 00:27:08.160447 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9868 00:27:08.163811 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9869 00:27:08.167115 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9870 00:27:08.170568 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9871 00:27:08.177115 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9872 00:27:08.180478 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9873 00:27:08.183761 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9874 00:27:08.187059 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9875 00:27:08.193687 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9876 00:27:08.197431 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9877 00:27:08.200360 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9878 00:27:08.203775 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9879 00:27:08.210555 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9880 00:27:08.213927 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9881 00:27:08.216893 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9882 00:27:08.223653 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9883 00:27:08.227209 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9884 00:27:08.233838 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9885 00:27:08.236743 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9886 00:27:08.243313 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9887 00:27:08.246518 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9888 00:27:08.249760 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9889 00:27:08.256908 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9890 00:27:08.259734 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9891 00:27:08.266169 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9892 00:27:08.269675 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9893 00:27:08.276288 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9894 00:27:08.279554 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9895 00:27:08.283144 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9896 00:27:08.289362 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9897 00:27:08.292753 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9898 00:27:08.299399 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9899 00:27:08.302510 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9900 00:27:08.309391 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9901 00:27:08.312661 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9902 00:27:08.315744 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9903 00:27:08.322741 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9904 00:27:08.325420 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9905 00:27:08.332290 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9906 00:27:08.335447 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9907 00:27:08.339438 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9908 00:27:08.345659 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9909 00:27:08.348819 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9910 00:27:08.355696 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9911 00:27:08.358859 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9912 00:27:08.362003 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9913 00:27:08.369037 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9914 00:27:08.372063 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9915 00:27:08.378632 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9916 00:27:08.382124 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9917 00:27:08.388634 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9918 00:27:08.392344 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9919 00:27:08.395248 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9920 00:27:08.401871 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9921 00:27:08.405076 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9922 00:27:08.411918 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9923 00:27:08.415278 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9924 00:27:08.418096 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9925 00:27:08.424927 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9926 00:27:08.428063 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9927 00:27:08.434697 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9928 00:27:08.438146 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9929 00:27:08.441716 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9930 00:27:08.448325 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9931 00:27:08.451936 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9932 00:27:08.458481 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9933 00:27:08.461579 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9934 00:27:08.467960 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9935 00:27:08.471231 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9936 00:27:08.474625 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9937 00:27:08.481603 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9938 00:27:08.484744 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9939 00:27:08.491645 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9940 00:27:08.494578 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9941 00:27:08.498126 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9942 00:27:08.504819 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9943 00:27:08.508250 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9944 00:27:08.514359 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9945 00:27:08.517949 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9946 00:27:08.521306 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9947 00:27:08.527539 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9948 00:27:08.530971 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9949 00:27:08.537769 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9950 00:27:08.541386 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9951 00:27:08.548266 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9952 00:27:08.550868 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9953 00:27:08.554066 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9954 00:27:08.560815 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9955 00:27:08.564053 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9956 00:27:08.570930 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9957 00:27:08.574663 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9958 00:27:08.580940 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9959 00:27:08.583980 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9960 00:27:08.587212 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9961 00:27:08.594063 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9962 00:27:08.597363 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9963 00:27:08.604401 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9964 00:27:08.607018 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9965 00:27:08.614009 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9966 00:27:08.617465 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9967 00:27:08.623653 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9968 00:27:08.627238 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9969 00:27:08.630589 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9970 00:27:08.637219 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9971 00:27:08.640739 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9972 00:27:08.647034 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9973 00:27:08.650068 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9974 00:27:08.657170 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9975 00:27:08.660627 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9976 00:27:08.663919 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9977 00:27:08.670069 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9978 00:27:08.673602 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9979 00:27:08.679732 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9980 00:27:08.683331 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9981 00:27:08.689959 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9982 00:27:08.693166 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9983 00:27:08.699809 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9984 00:27:08.703179 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9985 00:27:08.706408 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9986 00:27:08.712933 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9987 00:27:08.716491 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9988 00:27:08.723131 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9989 00:27:08.726611 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9990 00:27:08.733545 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9991 00:27:08.736009 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9992 00:27:08.742811 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9993 00:27:08.746399 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9994 00:27:08.749235 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9995 00:27:08.755872 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9996 00:27:08.759473 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9997 00:27:08.766022 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9998 00:27:08.769233 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9999 00:27:08.776116 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
10000 00:27:08.779078 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
10001 00:27:08.782921 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
10002 00:27:08.789735 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
10003 00:27:08.792484 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
10004 00:27:08.799053 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
10005 00:27:08.802369 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
10006 00:27:08.809069 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
10007 00:27:08.811973 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
10008 00:27:08.818862 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
10009 00:27:08.821885 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
10010 00:27:08.828868 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
10011 00:27:08.832477 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
10012 00:27:08.838443 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
10013 00:27:08.842243 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
10014 00:27:08.849012 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
10015 00:27:08.851796 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
10016 00:27:08.858752 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
10017 00:27:08.862047 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
10018 00:27:08.867975 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
10019 00:27:08.871477 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
10020 00:27:08.877978 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
10021 00:27:08.881772 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
10022 00:27:08.888068 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
10023 00:27:08.891037 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
10024 00:27:08.897819 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
10025 00:27:08.901419 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
10026 00:27:08.907879 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
10027 00:27:08.910672 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
10028 00:27:08.917642 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
10029 00:27:08.920714 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
10030 00:27:08.927373 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
10031 00:27:08.931052 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
10032 00:27:08.937523 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
10033 00:27:08.940895 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
10034 00:27:08.944457 INFO: [APUAPC] vio 0
10035 00:27:08.947446 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
10036 00:27:08.953841 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
10037 00:27:08.957075 INFO: [APUAPC] D0_APC_0: 0x400510
10038 00:27:08.957615 INFO: [APUAPC] D0_APC_1: 0x0
10039 00:27:08.960392 INFO: [APUAPC] D0_APC_2: 0x1540
10040 00:27:08.963729 INFO: [APUAPC] D0_APC_3: 0x0
10041 00:27:08.966901 INFO: [APUAPC] D1_APC_0: 0xffffffff
10042 00:27:08.970235 INFO: [APUAPC] D1_APC_1: 0xffffffff
10043 00:27:08.973784 INFO: [APUAPC] D1_APC_2: 0x3fffff
10044 00:27:08.976766 INFO: [APUAPC] D1_APC_3: 0x0
10045 00:27:08.980071 INFO: [APUAPC] D2_APC_0: 0xffffffff
10046 00:27:08.983481 INFO: [APUAPC] D2_APC_1: 0xffffffff
10047 00:27:08.986938 INFO: [APUAPC] D2_APC_2: 0x3fffff
10048 00:27:08.990062 INFO: [APUAPC] D2_APC_3: 0x0
10049 00:27:08.993196 INFO: [APUAPC] D3_APC_0: 0xffffffff
10050 00:27:08.996709 INFO: [APUAPC] D3_APC_1: 0xffffffff
10051 00:27:08.999822 INFO: [APUAPC] D3_APC_2: 0x3fffff
10052 00:27:09.002975 INFO: [APUAPC] D3_APC_3: 0x0
10053 00:27:09.006712 INFO: [APUAPC] D4_APC_0: 0xffffffff
10054 00:27:09.009600 INFO: [APUAPC] D4_APC_1: 0xffffffff
10055 00:27:09.013155 INFO: [APUAPC] D4_APC_2: 0x3fffff
10056 00:27:09.016919 INFO: [APUAPC] D4_APC_3: 0x0
10057 00:27:09.019838 INFO: [APUAPC] D5_APC_0: 0xffffffff
10058 00:27:09.022919 INFO: [APUAPC] D5_APC_1: 0xffffffff
10059 00:27:09.026452 INFO: [APUAPC] D5_APC_2: 0x3fffff
10060 00:27:09.029269 INFO: [APUAPC] D5_APC_3: 0x0
10061 00:27:09.032982 INFO: [APUAPC] D6_APC_0: 0xffffffff
10062 00:27:09.035987 INFO: [APUAPC] D6_APC_1: 0xffffffff
10063 00:27:09.039412 INFO: [APUAPC] D6_APC_2: 0x3fffff
10064 00:27:09.042977 INFO: [APUAPC] D6_APC_3: 0x0
10065 00:27:09.046576 INFO: [APUAPC] D7_APC_0: 0xffffffff
10066 00:27:09.049190 INFO: [APUAPC] D7_APC_1: 0xffffffff
10067 00:27:09.052661 INFO: [APUAPC] D7_APC_2: 0x3fffff
10068 00:27:09.056271 INFO: [APUAPC] D7_APC_3: 0x0
10069 00:27:09.059284 INFO: [APUAPC] D8_APC_0: 0xffffffff
10070 00:27:09.063057 INFO: [APUAPC] D8_APC_1: 0xffffffff
10071 00:27:09.065914 INFO: [APUAPC] D8_APC_2: 0x3fffff
10072 00:27:09.069178 INFO: [APUAPC] D8_APC_3: 0x0
10073 00:27:09.072158 INFO: [APUAPC] D9_APC_0: 0xffffffff
10074 00:27:09.075550 INFO: [APUAPC] D9_APC_1: 0xffffffff
10075 00:27:09.079462 INFO: [APUAPC] D9_APC_2: 0x3fffff
10076 00:27:09.082640 INFO: [APUAPC] D9_APC_3: 0x0
10077 00:27:09.085493 INFO: [APUAPC] D10_APC_0: 0xffffffff
10078 00:27:09.089173 INFO: [APUAPC] D10_APC_1: 0xffffffff
10079 00:27:09.092103 INFO: [APUAPC] D10_APC_2: 0x3fffff
10080 00:27:09.095616 INFO: [APUAPC] D10_APC_3: 0x0
10081 00:27:09.098620 INFO: [APUAPC] D11_APC_0: 0xffffffff
10082 00:27:09.102022 INFO: [APUAPC] D11_APC_1: 0xffffffff
10083 00:27:09.105384 INFO: [APUAPC] D11_APC_2: 0x3fffff
10084 00:27:09.108947 INFO: [APUAPC] D11_APC_3: 0x0
10085 00:27:09.112426 INFO: [APUAPC] D12_APC_0: 0xffffffff
10086 00:27:09.115256 INFO: [APUAPC] D12_APC_1: 0xffffffff
10087 00:27:09.118285 INFO: [APUAPC] D12_APC_2: 0x3fffff
10088 00:27:09.121723 INFO: [APUAPC] D12_APC_3: 0x0
10089 00:27:09.125086 INFO: [APUAPC] D13_APC_0: 0xffffffff
10090 00:27:09.128090 INFO: [APUAPC] D13_APC_1: 0xffffffff
10091 00:27:09.131868 INFO: [APUAPC] D13_APC_2: 0x3fffff
10092 00:27:09.134805 INFO: [APUAPC] D13_APC_3: 0x0
10093 00:27:09.138105 INFO: [APUAPC] D14_APC_0: 0xffffffff
10094 00:27:09.141492 INFO: [APUAPC] D14_APC_1: 0xffffffff
10095 00:27:09.144957 INFO: [APUAPC] D14_APC_2: 0x3fffff
10096 00:27:09.147919 INFO: [APUAPC] D14_APC_3: 0x0
10097 00:27:09.151240 INFO: [APUAPC] D15_APC_0: 0xffffffff
10098 00:27:09.154229 INFO: [APUAPC] D15_APC_1: 0xffffffff
10099 00:27:09.157719 INFO: [APUAPC] D15_APC_2: 0x3fffff
10100 00:27:09.161140 INFO: [APUAPC] D15_APC_3: 0x0
10101 00:27:09.164617 INFO: [APUAPC] APC_CON: 0x4
10102 00:27:09.167949 INFO: [NOCDAPC] D0_APC_0: 0x0
10103 00:27:09.171040 INFO: [NOCDAPC] D0_APC_1: 0x0
10104 00:27:09.174667 INFO: [NOCDAPC] D1_APC_0: 0x0
10105 00:27:09.177409 INFO: [NOCDAPC] D1_APC_1: 0xfff
10106 00:27:09.180696 INFO: [NOCDAPC] D2_APC_0: 0x0
10107 00:27:09.180878 INFO: [NOCDAPC] D2_APC_1: 0xfff
10108 00:27:09.184238 INFO: [NOCDAPC] D3_APC_0: 0x0
10109 00:27:09.187464 INFO: [NOCDAPC] D3_APC_1: 0xfff
10110 00:27:09.191025 INFO: [NOCDAPC] D4_APC_0: 0x0
10111 00:27:09.194278 INFO: [NOCDAPC] D4_APC_1: 0xfff
10112 00:27:09.197568 INFO: [NOCDAPC] D5_APC_0: 0x0
10113 00:27:09.200642 INFO: [NOCDAPC] D5_APC_1: 0xfff
10114 00:27:09.204262 INFO: [NOCDAPC] D6_APC_0: 0x0
10115 00:27:09.207658 INFO: [NOCDAPC] D6_APC_1: 0xfff
10116 00:27:09.210815 INFO: [NOCDAPC] D7_APC_0: 0x0
10117 00:27:09.214222 INFO: [NOCDAPC] D7_APC_1: 0xfff
10118 00:27:09.214612 INFO: [NOCDAPC] D8_APC_0: 0x0
10119 00:27:09.217705 INFO: [NOCDAPC] D8_APC_1: 0xfff
10120 00:27:09.221239 INFO: [NOCDAPC] D9_APC_0: 0x0
10121 00:27:09.224625 INFO: [NOCDAPC] D9_APC_1: 0xfff
10122 00:27:09.227562 INFO: [NOCDAPC] D10_APC_0: 0x0
10123 00:27:09.230934 INFO: [NOCDAPC] D10_APC_1: 0xfff
10124 00:27:09.233956 INFO: [NOCDAPC] D11_APC_0: 0x0
10125 00:27:09.237075 INFO: [NOCDAPC] D11_APC_1: 0xfff
10126 00:27:09.240483 INFO: [NOCDAPC] D12_APC_0: 0x0
10127 00:27:09.243828 INFO: [NOCDAPC] D12_APC_1: 0xfff
10128 00:27:09.247227 INFO: [NOCDAPC] D13_APC_0: 0x0
10129 00:27:09.250868 INFO: [NOCDAPC] D13_APC_1: 0xfff
10130 00:27:09.253606 INFO: [NOCDAPC] D14_APC_0: 0x0
10131 00:27:09.257095 INFO: [NOCDAPC] D14_APC_1: 0xfff
10132 00:27:09.260371 INFO: [NOCDAPC] D15_APC_0: 0x0
10133 00:27:09.260591 INFO: [NOCDAPC] D15_APC_1: 0xfff
10134 00:27:09.263748 INFO: [NOCDAPC] APC_CON: 0x4
10135 00:27:09.266846 INFO: [APUAPC] set_apusys_apc done
10136 00:27:09.269870 INFO: [DEVAPC] devapc_init done
10137 00:27:09.276878 INFO: GICv3 without legacy support detected.
10138 00:27:09.280360 INFO: ARM GICv3 driver initialized in EL3
10139 00:27:09.283659 INFO: Maximum SPI INTID supported: 639
10140 00:27:09.287194 INFO: BL31: Initializing runtime services
10141 00:27:09.293444 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10142 00:27:09.296623 INFO: SPM: enable CPC mode
10143 00:27:09.300334 INFO: mcdi ready for mcusys-off-idle and system suspend
10144 00:27:09.306367 INFO: BL31: Preparing for EL3 exit to normal world
10145 00:27:09.310018 INFO: Entry point address = 0x80000000
10146 00:27:09.310242 INFO: SPSR = 0x8
10147 00:27:09.316696
10148 00:27:09.316895
10149 00:27:09.316999
10150 00:27:09.320205 Starting depthcharge on Spherion...
10151 00:27:09.320353
10152 00:27:09.320455 Wipe memory regions:
10153 00:27:09.320553
10154 00:27:09.321380 end: 2.2.3 depthcharge-start (duration 00:00:20) [common]
10155 00:27:09.321552 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
10156 00:27:09.321683 Setting prompt string to ['asurada:']
10157 00:27:09.321811 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
10158 00:27:09.323417 [0x00000040000000, 0x00000054600000)
10159 00:27:09.444751
10160 00:27:09.444999 [0x00000054660000, 0x00000080000000)
10161 00:27:09.704914
10162 00:27:09.705081 [0x000000821a7280, 0x000000ffe64000)
10163 00:27:10.448563
10164 00:27:10.448719 [0x00000100000000, 0x00000240000000)
10165 00:27:12.338099
10166 00:27:12.341306 Initializing XHCI USB controller at 0x11200000.
10167 00:27:13.379930
10168 00:27:13.382683 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10169 00:27:13.382772
10170 00:27:13.382837
10171 00:27:13.383119 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10173 00:27:13.483485 asurada: tftpboot 192.168.201.1 14479210/tftp-deploy-rkh18ac3/kernel/image.itb 14479210/tftp-deploy-rkh18ac3/kernel/cmdline
10174 00:27:13.483635 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10175 00:27:13.483718 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:22)
10176 00:27:13.487758 tftpboot 192.168.201.1 14479210/tftp-deploy-rkh18ac3/kernel/image.ittp-deploy-rkh18ac3/kernel/cmdline
10177 00:27:13.487853
10178 00:27:13.487919 Waiting for link
10179 00:27:13.646031
10180 00:27:13.646174 R8152: Initializing
10181 00:27:13.646273
10182 00:27:13.649233 Version 6 (ocp_data = 5c30)
10183 00:27:13.649316
10184 00:27:13.652318 R8152: Done initializing
10185 00:27:13.652401
10186 00:27:13.652477 Adding net device
10187 00:27:15.558771
10188 00:27:15.558926 done.
10189 00:27:15.558995
10190 00:27:15.559056 MAC: 00:e0:4c:68:02:81
10191 00:27:15.559114
10192 00:27:15.562074 Sending DHCP discover... done.
10193 00:27:15.562187
10194 00:27:25.275651 Waiting for reply... R8152: Bulk read error 0xffffffbf
10195 00:27:25.275814
10196 00:27:25.279037 Receive failed.
10197 00:27:25.279136
10198 00:27:25.279203 done.
10199 00:27:25.279263
10200 00:27:25.282541 Sending DHCP request... done.
10201 00:27:25.282636
10202 00:27:25.285645 Waiting for reply... done.
10203 00:27:25.285733
10204 00:27:25.285799 My ip is 192.168.201.14
10205 00:27:25.285860
10206 00:27:25.288830 The DHCP server ip is 192.168.201.1
10207 00:27:25.288916
10208 00:27:25.295678 TFTP server IP predefined by user: 192.168.201.1
10209 00:27:25.295782
10210 00:27:25.302103 Bootfile predefined by user: 14479210/tftp-deploy-rkh18ac3/kernel/image.itb
10211 00:27:25.302252
10212 00:27:25.305273 Sending tftp read request... done.
10213 00:27:25.305366
10214 00:27:25.309546 Waiting for the transfer...
10215 00:27:25.309638
10216 00:27:25.876830 00000000 ################################################################
10217 00:27:25.876986
10218 00:27:26.434725 00080000 ################################################################
10219 00:27:26.434888
10220 00:27:26.997274 00100000 ################################################################
10221 00:27:26.997432
10222 00:27:27.562176 00180000 ################################################################
10223 00:27:27.562354
10224 00:27:28.127696 00200000 ################################################################
10225 00:27:28.127858
10226 00:27:28.700254 00280000 ################################################################
10227 00:27:28.700413
10228 00:27:29.269537 00300000 ################################################################
10229 00:27:29.269696
10230 00:27:29.828194 00380000 ################################################################
10231 00:27:29.828379
10232 00:27:30.402436 00400000 ################################################################
10233 00:27:30.402592
10234 00:27:30.960872 00480000 ################################################################
10235 00:27:30.961036
10236 00:27:31.509151 00500000 ################################################################
10237 00:27:31.509326
10238 00:27:32.081584 00580000 ################################################################
10239 00:27:32.081746
10240 00:27:32.647137 00600000 ################################################################
10241 00:27:32.647299
10242 00:27:33.212642 00680000 ################################################################
10243 00:27:33.212860
10244 00:27:33.775030 00700000 ################################################################
10245 00:27:33.775189
10246 00:27:34.334624 00780000 ################################################################
10247 00:27:34.334781
10248 00:27:34.894233 00800000 ################################################################
10249 00:27:34.894396
10250 00:27:35.452367 00880000 ################################################################
10251 00:27:35.452524
10252 00:27:36.037827 00900000 ################################################################
10253 00:27:36.037985
10254 00:27:36.627784 00980000 ################################################################
10255 00:27:36.627936
10256 00:27:37.294568 00a00000 ################################################################
10257 00:27:37.295171
10258 00:27:38.008583 00a80000 ################################################################
10259 00:27:38.009128
10260 00:27:38.723832 00b00000 ################################################################
10261 00:27:38.724394
10262 00:27:39.440819 00b80000 ################################################################
10263 00:27:39.441338
10264 00:27:40.152715 00c00000 ################################################################
10265 00:27:40.153265
10266 00:27:40.868637 00c80000 ################################################################
10267 00:27:40.869266
10268 00:27:41.525751 00d00000 ################################################################
10269 00:27:41.525930
10270 00:27:42.148637 00d80000 ################################################################
10271 00:27:42.149330
10272 00:27:42.872217 00e00000 ################################################################
10273 00:27:42.872767
10274 00:27:43.546537 00e80000 ################################################################
10275 00:27:43.547066
10276 00:27:44.240592 00f00000 ################################################################
10277 00:27:44.241354
10278 00:27:44.948464 00f80000 ################################################################
10279 00:27:44.949012
10280 00:27:45.662532 01000000 ################################################################
10281 00:27:45.663107
10282 00:27:46.367430 01080000 ################################################################
10283 00:27:46.368001
10284 00:27:47.054488 01100000 ################################################################
10285 00:27:47.055101
10286 00:27:47.749069 01180000 ################################################################
10287 00:27:47.749613
10288 00:27:48.424226 01200000 ################################################################
10289 00:27:48.424780
10290 00:27:49.117118 01280000 ################################################################
10291 00:27:49.117660
10292 00:27:49.796729 01300000 ################################################################
10293 00:27:49.797293
10294 00:27:50.497924 01380000 ################################################################
10295 00:27:50.498568
10296 00:27:51.199924 01400000 ################################################################
10297 00:27:51.200472
10298 00:27:51.913669 01480000 ################################################################
10299 00:27:51.914224
10300 00:27:52.580187 01500000 ################################################################
10301 00:27:52.580812
10302 00:27:53.289144 01580000 ################################################################
10303 00:27:53.289743
10304 00:27:53.993604 01600000 ################################################################
10305 00:27:53.994217
10306 00:27:54.684374 01680000 ################################################################
10307 00:27:54.684895
10308 00:27:55.308339 01700000 ################################################################
10309 00:27:55.308850
10310 00:27:55.974650 01780000 ################################################################
10311 00:27:55.974904
10312 00:27:56.646724 01800000 ################################################################
10313 00:27:56.647234
10314 00:27:57.337017 01880000 ################################################################
10315 00:27:57.337534
10316 00:27:58.034870 01900000 ################################################################
10317 00:27:58.035391
10318 00:27:58.721012 01980000 ################################################################
10319 00:27:58.721529
10320 00:27:59.407623 01a00000 ################################################################
10321 00:27:59.408037
10322 00:28:00.076572 01a80000 ################################################################
10323 00:28:00.077140
10324 00:28:00.767233 01b00000 ################################################################
10325 00:28:00.767984
10326 00:28:01.424325 01b80000 ################################################################
10327 00:28:01.424856
10328 00:28:02.069934 01c00000 ################################################################
10329 00:28:02.070561
10330 00:28:02.613615 01c80000 ################################################################
10331 00:28:02.613771
10332 00:28:03.152762 01d00000 ################################################################
10333 00:28:03.152916
10334 00:28:03.700611 01d80000 ################################################################
10335 00:28:03.700748
10336 00:28:04.191492 01e00000 ######################################################### done.
10337 00:28:04.191637
10338 00:28:04.194522 The bootfile was 31922686 bytes long.
10339 00:28:04.194610
10340 00:28:04.197854 Sending tftp read request... done.
10341 00:28:04.197963
10342 00:28:04.198065 Waiting for the transfer...
10343 00:28:04.198170
10344 00:28:04.201393 00000000 # done.
10345 00:28:04.201480
10346 00:28:04.207875 Command line loaded dynamically from TFTP file: 14479210/tftp-deploy-rkh18ac3/kernel/cmdline
10347 00:28:04.207961
10348 00:28:04.230826 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14479210/extract-nfsrootfs-u_uwlwfy,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10349 00:28:04.230920
10350 00:28:04.231005 Loading FIT.
10351 00:28:04.234063
10352 00:28:04.234179 Image ramdisk-1 has 18748499 bytes.
10353 00:28:04.234266
10354 00:28:04.237422 Image fdt-1 has 47258 bytes.
10355 00:28:04.237507
10356 00:28:04.241014 Image kernel-1 has 13124896 bytes.
10357 00:28:04.241098
10358 00:28:04.250670 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10359 00:28:04.250755
10360 00:28:04.267266 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10361 00:28:04.267356
10362 00:28:04.273761 Choosing best match conf-1 for compat google,spherion-rev2.
10363 00:28:04.277244
10364 00:28:04.281489 Connected to device vid:did:rid of 1ae0:0028:00
10365 00:28:04.288631
10366 00:28:04.292008 tpm_get_response: command 0x17b, return code 0x0
10367 00:28:04.292092
10368 00:28:04.295141 ec_init: CrosEC protocol v3 supported (256, 248)
10369 00:28:04.299372
10370 00:28:04.302717 tpm_cleanup: add release locality here.
10371 00:28:04.302801
10372 00:28:04.302886 Shutting down all USB controllers.
10373 00:28:04.306008
10374 00:28:04.306093 Removing current net device
10375 00:28:04.306228
10376 00:28:04.312443 Exiting depthcharge with code 4 at timestamp: 84552397
10377 00:28:04.312528
10378 00:28:04.315711 LZMA decompressing kernel-1 to 0x821a6718
10379 00:28:04.315796
10380 00:28:04.318991 LZMA decompressing kernel-1 to 0x40000000
10381 00:28:05.935326
10382 00:28:05.935523 jumping to kernel
10383 00:28:05.936097 end: 2.2.4 bootloader-commands (duration 00:00:57) [common]
10384 00:28:05.936209 start: 2.2.5 auto-login-action (timeout 00:03:30) [common]
10385 00:28:05.936295 Setting prompt string to ['Linux version [0-9]']
10386 00:28:05.936378 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10387 00:28:05.936483 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10388 00:28:06.017445
10389 00:28:06.020949 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10390 00:28:06.024054 start: 2.2.5.1 login-action (timeout 00:03:30) [common]
10391 00:28:06.024184 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10392 00:28:06.024286 Setting prompt string to []
10393 00:28:06.024407 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10394 00:28:06.024515 Using line separator: #'\n'#
10395 00:28:06.024606 No login prompt set.
10396 00:28:06.024734 Parsing kernel messages
10397 00:28:06.024850 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10398 00:28:06.025075 [login-action] Waiting for messages, (timeout 00:03:30)
10399 00:28:06.025206 Waiting using forced prompt support (timeout 00:01:45)
10400 00:28:06.043501 [ 0.000000] Linux version 6.1.94-cip23 (KernelCI@build-j239242-arm64-gcc-10-defconfig-arm64-chromebook-c5lwc) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Jun 21 00:04:56 UTC 2024
10401 00:28:06.046799 [ 0.000000] random: crng init done
10402 00:28:06.053956 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10403 00:28:06.057074 [ 0.000000] efi: UEFI not found.
10404 00:28:06.063645 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10405 00:28:06.073812 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10406 00:28:06.080464 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10407 00:28:06.090349 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10408 00:28:06.096512 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10409 00:28:06.103152 [ 0.000000] printk: bootconsole [mtk8250] enabled
10410 00:28:06.110052 [ 0.000000] NUMA: No NUMA configuration found
10411 00:28:06.116467 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10412 00:28:06.123229 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10413 00:28:06.123649 [ 0.000000] Zone ranges:
10414 00:28:06.129763 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10415 00:28:06.133112 [ 0.000000] DMA32 empty
10416 00:28:06.139455 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10417 00:28:06.142833 [ 0.000000] Movable zone start for each node
10418 00:28:06.146268 [ 0.000000] Early memory node ranges
10419 00:28:06.152856 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10420 00:28:06.159371 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10421 00:28:06.165598 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10422 00:28:06.172185 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10423 00:28:06.178971 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10424 00:28:06.185427 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10425 00:28:06.242790 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10426 00:28:06.249262 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10427 00:28:06.255466 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10428 00:28:06.258831 [ 0.000000] psci: probing for conduit method from DT.
10429 00:28:06.265504 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10430 00:28:06.268887 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10431 00:28:06.275604 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10432 00:28:06.278430 [ 0.000000] psci: SMC Calling Convention v1.2
10433 00:28:06.285437 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10434 00:28:06.288863 [ 0.000000] Detected VIPT I-cache on CPU0
10435 00:28:06.295190 [ 0.000000] CPU features: detected: GIC system register CPU interface
10436 00:28:06.301871 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10437 00:28:06.308323 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10438 00:28:06.314908 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10439 00:28:06.324786 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10440 00:28:06.331307 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10441 00:28:06.334653 [ 0.000000] alternatives: applying boot alternatives
10442 00:28:06.341024 [ 0.000000] Fallback order for Node 0: 0
10443 00:28:06.347792 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10444 00:28:06.350911 [ 0.000000] Policy zone: Normal
10445 00:28:06.374124 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14479210/extract-nfsrootfs-u_uwlwfy,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10446 00:28:06.383796 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10447 00:28:06.395243 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10448 00:28:06.405135 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10449 00:28:06.411848 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10450 00:28:06.415378 <6>[ 0.000000] software IO TLB: area num 8.
10451 00:28:06.473160 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10452 00:28:06.621902 <6>[ 0.000000] Memory: 7945752K/8385536K available (18112K kernel code, 4120K rwdata, 22648K rodata, 8512K init, 616K bss, 407016K reserved, 32768K cma-reserved)
10453 00:28:06.628563 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10454 00:28:06.635254 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10455 00:28:06.638617 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10456 00:28:06.645153 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10457 00:28:06.651500 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10458 00:28:06.655024 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10459 00:28:06.664927 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10460 00:28:06.671711 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10461 00:28:06.678158 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10462 00:28:06.684711 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10463 00:28:06.687776 <6>[ 0.000000] GICv3: 608 SPIs implemented
10464 00:28:06.691184 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10465 00:28:06.697453 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10466 00:28:06.700872 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10467 00:28:06.707687 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10468 00:28:06.721106 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10469 00:28:06.733956 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10470 00:28:06.740506 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10471 00:28:06.748627 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10472 00:28:06.762063 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10473 00:28:06.768310 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10474 00:28:06.775309 <6>[ 0.009175] Console: colour dummy device 80x25
10475 00:28:06.784962 <6>[ 0.013935] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10476 00:28:06.791526 <6>[ 0.024376] pid_max: default: 32768 minimum: 301
10477 00:28:06.794714 <6>[ 0.029247] LSM: Security Framework initializing
10478 00:28:06.801904 <6>[ 0.034186] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10479 00:28:06.811183 <6>[ 0.042047] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10480 00:28:06.821467 <6>[ 0.051508] cblist_init_generic: Setting adjustable number of callback queues.
10481 00:28:06.824439 <6>[ 0.058996] cblist_init_generic: Setting shift to 3 and lim to 1.
10482 00:28:06.834469 <6>[ 0.065334] cblist_init_generic: Setting adjustable number of callback queues.
10483 00:28:06.841095 <6>[ 0.072760] cblist_init_generic: Setting shift to 3 and lim to 1.
10484 00:28:06.844536 <6>[ 0.079198] rcu: Hierarchical SRCU implementation.
10485 00:28:06.850688 <6>[ 0.084213] rcu: Max phase no-delay instances is 1000.
10486 00:28:06.857217 <6>[ 0.091241] EFI services will not be available.
10487 00:28:06.860252 <6>[ 0.096229] smp: Bringing up secondary CPUs ...
10488 00:28:06.869365 <6>[ 0.101280] Detected VIPT I-cache on CPU1
10489 00:28:06.875619 <6>[ 0.101350] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10490 00:28:06.882271 <6>[ 0.101380] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10491 00:28:06.885543 <6>[ 0.101714] Detected VIPT I-cache on CPU2
10492 00:28:06.895714 <6>[ 0.101763] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10493 00:28:06.902065 <6>[ 0.101778] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10494 00:28:06.905156 <6>[ 0.102030] Detected VIPT I-cache on CPU3
10495 00:28:06.911689 <6>[ 0.102077] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10496 00:28:06.918506 <6>[ 0.102090] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10497 00:28:06.925006 <6>[ 0.102394] CPU features: detected: Spectre-v4
10498 00:28:06.928388 <6>[ 0.102400] CPU features: detected: Spectre-BHB
10499 00:28:06.932021 <6>[ 0.102405] Detected PIPT I-cache on CPU4
10500 00:28:06.938170 <6>[ 0.102461] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10501 00:28:06.948478 <6>[ 0.102477] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10502 00:28:06.951746 <6>[ 0.102768] Detected PIPT I-cache on CPU5
10503 00:28:06.958148 <6>[ 0.102830] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10504 00:28:06.964607 <6>[ 0.102847] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10505 00:28:06.967887 <6>[ 0.103128] Detected PIPT I-cache on CPU6
10506 00:28:06.977889 <6>[ 0.103193] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10507 00:28:06.984704 <6>[ 0.103209] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10508 00:28:06.987469 <6>[ 0.103504] Detected PIPT I-cache on CPU7
10509 00:28:06.994325 <6>[ 0.103567] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10510 00:28:07.001158 <6>[ 0.103583] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10511 00:28:07.004628 <6>[ 0.103631] smp: Brought up 1 node, 8 CPUs
10512 00:28:07.010812 <6>[ 0.245115] SMP: Total of 8 processors activated.
10513 00:28:07.017440 <6>[ 0.250036] CPU features: detected: 32-bit EL0 Support
10514 00:28:07.024243 <6>[ 0.255432] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10515 00:28:07.030288 <6>[ 0.264240] CPU features: detected: Common not Private translations
10516 00:28:07.037403 <6>[ 0.270756] CPU features: detected: CRC32 instructions
10517 00:28:07.043612 <6>[ 0.276141] CPU features: detected: RCpc load-acquire (LDAPR)
10518 00:28:07.047016 <6>[ 0.282138] CPU features: detected: LSE atomic instructions
10519 00:28:07.053905 <6>[ 0.287920] CPU features: detected: Privileged Access Never
10520 00:28:07.060069 <6>[ 0.293700] CPU features: detected: RAS Extension Support
10521 00:28:07.067108 <6>[ 0.299344] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10522 00:28:07.070312 <6>[ 0.306570] CPU: All CPU(s) started at EL2
10523 00:28:07.076556 <6>[ 0.310886] alternatives: applying system-wide alternatives
10524 00:28:07.087118 <6>[ 0.321739] devtmpfs: initialized
10525 00:28:07.102611 <6>[ 0.330682] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10526 00:28:07.109211 <6>[ 0.340643] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10527 00:28:07.115980 <6>[ 0.348664] pinctrl core: initialized pinctrl subsystem
10528 00:28:07.119216 <6>[ 0.355342] DMI not present or invalid.
10529 00:28:07.125738 <6>[ 0.359753] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10530 00:28:07.135995 <6>[ 0.366621] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10531 00:28:07.142156 <6>[ 0.374203] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10532 00:28:07.152110 <6>[ 0.382425] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10533 00:28:07.155595 <6>[ 0.390668] audit: initializing netlink subsys (disabled)
10534 00:28:07.165438 <5>[ 0.396363] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10535 00:28:07.172290 <6>[ 0.397079] thermal_sys: Registered thermal governor 'step_wise'
10536 00:28:07.178971 <6>[ 0.404331] thermal_sys: Registered thermal governor 'power_allocator'
10537 00:28:07.182498 <6>[ 0.410588] cpuidle: using governor menu
10538 00:28:07.188435 <6>[ 0.421550] NET: Registered PF_QIPCRTR protocol family
10539 00:28:07.195114 <6>[ 0.427035] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10540 00:28:07.201409 <6>[ 0.434139] ASID allocator initialised with 32768 entries
10541 00:28:07.204878 <6>[ 0.440725] Serial: AMBA PL011 UART driver
10542 00:28:07.214952 <4>[ 0.449590] Trying to register duplicate clock ID: 134
10543 00:28:07.275072 <6>[ 0.512715] KASLR enabled
10544 00:28:07.289299 <6>[ 0.520482] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10545 00:28:07.296082 <6>[ 0.527495] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10546 00:28:07.302749 <6>[ 0.533986] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10547 00:28:07.308946 <6>[ 0.540993] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10548 00:28:07.316031 <6>[ 0.547480] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10549 00:28:07.321978 <6>[ 0.554484] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10550 00:28:07.328820 <6>[ 0.560972] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10551 00:28:07.335381 <6>[ 0.567975] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10552 00:28:07.338574 <6>[ 0.575468] ACPI: Interpreter disabled.
10553 00:28:07.347710 <6>[ 0.581913] iommu: Default domain type: Translated
10554 00:28:07.353688 <6>[ 0.587028] iommu: DMA domain TLB invalidation policy: strict mode
10555 00:28:07.357499 <5>[ 0.593694] SCSI subsystem initialized
10556 00:28:07.364178 <6>[ 0.597860] usbcore: registered new interface driver usbfs
10557 00:28:07.370925 <6>[ 0.603591] usbcore: registered new interface driver hub
10558 00:28:07.374144 <6>[ 0.609142] usbcore: registered new device driver usb
10559 00:28:07.380609 <6>[ 0.615245] pps_core: LinuxPPS API ver. 1 registered
10560 00:28:07.390447 <6>[ 0.620439] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10561 00:28:07.394040 <6>[ 0.629787] PTP clock support registered
10562 00:28:07.397344 <6>[ 0.634030] EDAC MC: Ver: 3.0.0
10563 00:28:07.404676 <6>[ 0.639194] FPGA manager framework
10564 00:28:07.411399 <6>[ 0.642879] Advanced Linux Sound Architecture Driver Initialized.
10565 00:28:07.414371 <6>[ 0.649656] vgaarb: loaded
10566 00:28:07.421261 <6>[ 0.652819] clocksource: Switched to clocksource arch_sys_counter
10567 00:28:07.424293 <5>[ 0.659241] VFS: Disk quotas dquot_6.6.0
10568 00:28:07.430811 <6>[ 0.663425] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10569 00:28:07.433955 <6>[ 0.670615] pnp: PnP ACPI: disabled
10570 00:28:07.442478 <6>[ 0.677311] NET: Registered PF_INET protocol family
10571 00:28:07.452724 <6>[ 0.682901] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10572 00:28:07.463825 <6>[ 0.695225] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10573 00:28:07.474070 <6>[ 0.704040] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10574 00:28:07.481071 <6>[ 0.712009] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10575 00:28:07.487087 <6>[ 0.720710] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10576 00:28:07.499147 <6>[ 0.730460] TCP: Hash tables configured (established 65536 bind 65536)
10577 00:28:07.505633 <6>[ 0.737331] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10578 00:28:07.512229 <6>[ 0.744530] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10579 00:28:07.518871 <6>[ 0.752234] NET: Registered PF_UNIX/PF_LOCAL protocol family
10580 00:28:07.525580 <6>[ 0.758386] RPC: Registered named UNIX socket transport module.
10581 00:28:07.528754 <6>[ 0.764540] RPC: Registered udp transport module.
10582 00:28:07.535350 <6>[ 0.769473] RPC: Registered tcp transport module.
10583 00:28:07.541807 <6>[ 0.774406] RPC: Registered tcp NFSv4.1 backchannel transport module.
10584 00:28:07.544997 <6>[ 0.781071] PCI: CLS 0 bytes, default 64
10585 00:28:07.548560 <6>[ 0.785381] Unpacking initramfs...
10586 00:28:07.570477 <6>[ 0.801513] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10587 00:28:07.579944 <6>[ 0.810138] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10588 00:28:07.583525 <6>[ 0.818964] kvm [1]: IPA Size Limit: 40 bits
10589 00:28:07.590012 <6>[ 0.823488] kvm [1]: GICv3: no GICV resource entry
10590 00:28:07.593297 <6>[ 0.828508] kvm [1]: disabling GICv2 emulation
10591 00:28:07.600059 <6>[ 0.833210] kvm [1]: GIC system register CPU interface enabled
10592 00:28:07.603564 <6>[ 0.839364] kvm [1]: vgic interrupt IRQ18
10593 00:28:07.609822 <6>[ 0.843716] kvm [1]: VHE mode initialized successfully
10594 00:28:07.616473 <5>[ 0.850100] Initialise system trusted keyrings
10595 00:28:07.623061 <6>[ 0.854935] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10596 00:28:07.630346 <6>[ 0.865007] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10597 00:28:07.637002 <5>[ 0.871447] NFS: Registering the id_resolver key type
10598 00:28:07.640596 <5>[ 0.876754] Key type id_resolver registered
10599 00:28:07.647171 <5>[ 0.881168] Key type id_legacy registered
10600 00:28:07.653557 <6>[ 0.885446] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10601 00:28:07.660292 <6>[ 0.892366] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10602 00:28:07.666922 <6>[ 0.900141] 9p: Installing v9fs 9p2000 file system support
10603 00:28:07.704384 <5>[ 0.938752] Key type asymmetric registered
10604 00:28:07.707976 <5>[ 0.943087] Asymmetric key parser 'x509' registered
10605 00:28:07.717485 <6>[ 0.948235] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10606 00:28:07.721016 <6>[ 0.955847] io scheduler mq-deadline registered
10607 00:28:07.724334 <6>[ 0.960624] io scheduler kyber registered
10608 00:28:07.743152 <6>[ 0.977611] EINJ: ACPI disabled.
10609 00:28:07.775981 <4>[ 1.003999] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10610 00:28:07.785829 <4>[ 1.014648] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10611 00:28:07.801695 <6>[ 1.036176] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10612 00:28:07.809452 <6>[ 1.044279] printk: console [ttyS0] disabled
10613 00:28:07.837871 <6>[ 1.068917] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10614 00:28:07.844330 <6>[ 1.078381] printk: console [ttyS0] enabled
10615 00:28:07.848056 <6>[ 1.078381] printk: console [ttyS0] enabled
10616 00:28:07.854628 <6>[ 1.087274] printk: bootconsole [mtk8250] disabled
10617 00:28:07.857167 <6>[ 1.087274] printk: bootconsole [mtk8250] disabled
10618 00:28:07.863874 <6>[ 1.098619] SuperH (H)SCI(F) driver initialized
10619 00:28:07.866988 <6>[ 1.103906] msm_serial: driver initialized
10620 00:28:07.881778 <6>[ 1.112984] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10621 00:28:07.891823 <6>[ 1.121536] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10622 00:28:07.897972 <6>[ 1.130080] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10623 00:28:07.907792 <6>[ 1.138708] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10624 00:28:07.917821 <6>[ 1.147414] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10625 00:28:07.924310 <6>[ 1.156128] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10626 00:28:07.934339 <6>[ 1.164669] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10627 00:28:07.940765 <6>[ 1.173498] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10628 00:28:07.950583 <6>[ 1.182041] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10629 00:28:07.963071 <6>[ 1.197559] loop: module loaded
10630 00:28:07.969381 <6>[ 1.203567] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10631 00:28:07.992177 <4>[ 1.227053] mtk-pmic-keys: Failed to locate of_node [id: -1]
10632 00:28:07.999545 <6>[ 1.234128] megasas: 07.719.03.00-rc1
10633 00:28:08.009348 <6>[ 1.243865] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10634 00:28:08.021621 <6>[ 1.256196] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10635 00:28:08.037819 <6>[ 1.272553] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10636 00:28:08.098012 <6>[ 1.326058] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10637 00:28:08.374786 <6>[ 1.609484] Freeing initrd memory: 18304K
10638 00:28:08.386307 <6>[ 1.621126] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10639 00:28:08.397622 <6>[ 1.632012] tun: Universal TUN/TAP device driver, 1.6
10640 00:28:08.400783 <6>[ 1.638092] thunder_xcv, ver 1.0
10641 00:28:08.404516 <6>[ 1.641601] thunder_bgx, ver 1.0
10642 00:28:08.407205 <6>[ 1.645117] nicpf, ver 1.0
10643 00:28:08.418206 <6>[ 1.649133] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10644 00:28:08.420983 <6>[ 1.656610] hns3: Copyright (c) 2017 Huawei Corporation.
10645 00:28:08.427624 <6>[ 1.662197] hclge is initializing
10646 00:28:08.431188 <6>[ 1.665776] e1000: Intel(R) PRO/1000 Network Driver
10647 00:28:08.437505 <6>[ 1.670907] e1000: Copyright (c) 1999-2006 Intel Corporation.
10648 00:28:08.440821 <6>[ 1.676920] e1000e: Intel(R) PRO/1000 Network Driver
10649 00:28:08.447534 <6>[ 1.682136] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10650 00:28:08.454464 <6>[ 1.688326] igb: Intel(R) Gigabit Ethernet Network Driver
10651 00:28:08.460850 <6>[ 1.693976] igb: Copyright (c) 2007-2014 Intel Corporation.
10652 00:28:08.467542 <6>[ 1.699812] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10653 00:28:08.473915 <6>[ 1.706330] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10654 00:28:08.477379 <6>[ 1.712791] sky2: driver version 1.30
10655 00:28:08.484320 <6>[ 1.717732] usbcore: registered new device driver r8152-cfgselector
10656 00:28:08.490391 <6>[ 1.724270] usbcore: registered new interface driver r8152
10657 00:28:08.497044 <6>[ 1.730082] VFIO - User Level meta-driver version: 0.3
10658 00:28:08.503815 <6>[ 1.738354] usbcore: registered new interface driver usb-storage
10659 00:28:08.510580 <6>[ 1.744795] usbcore: registered new device driver onboard-usb-hub
10660 00:28:08.519030 <6>[ 1.753925] mt6397-rtc mt6359-rtc: registered as rtc0
10661 00:28:08.529370 <6>[ 1.759391] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-21T00:28:08 UTC (1718929688)
10662 00:28:08.532301 <6>[ 1.768958] i2c_dev: i2c /dev entries driver
10663 00:28:08.546302 <4>[ 1.780903] cpu cpu0: supply cpu not found, using dummy regulator
10664 00:28:08.553207 <4>[ 1.787344] cpu cpu1: supply cpu not found, using dummy regulator
10665 00:28:08.559583 <4>[ 1.793748] cpu cpu2: supply cpu not found, using dummy regulator
10666 00:28:08.566054 <4>[ 1.800147] cpu cpu3: supply cpu not found, using dummy regulator
10667 00:28:08.572930 <4>[ 1.806541] cpu cpu4: supply cpu not found, using dummy regulator
10668 00:28:08.579731 <4>[ 1.812939] cpu cpu5: supply cpu not found, using dummy regulator
10669 00:28:08.586302 <4>[ 1.819355] cpu cpu6: supply cpu not found, using dummy regulator
10670 00:28:08.592708 <4>[ 1.825750] cpu cpu7: supply cpu not found, using dummy regulator
10671 00:28:08.611590 <6>[ 1.846382] cpu cpu0: EM: created perf domain
10672 00:28:08.615187 <6>[ 1.851325] cpu cpu4: EM: created perf domain
10673 00:28:08.622102 <6>[ 1.856917] sdhci: Secure Digital Host Controller Interface driver
10674 00:28:08.629043 <6>[ 1.863349] sdhci: Copyright(c) Pierre Ossman
10675 00:28:08.635827 <6>[ 1.868303] Synopsys Designware Multimedia Card Interface Driver
10676 00:28:08.642097 <6>[ 1.874941] sdhci-pltfm: SDHCI platform and OF driver helper
10677 00:28:08.645544 <6>[ 1.874956] mmc0: CQHCI version 5.10
10678 00:28:08.651900 <6>[ 1.884857] ledtrig-cpu: registered to indicate activity on CPUs
10679 00:28:08.658821 <6>[ 1.891813] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10680 00:28:08.665458 <6>[ 1.898861] usbcore: registered new interface driver usbhid
10681 00:28:08.668410 <6>[ 1.904684] usbhid: USB HID core driver
10682 00:28:08.675087 <6>[ 1.908881] spi_master spi0: will run message pump with realtime priority
10683 00:28:08.720754 <6>[ 1.948658] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10684 00:28:08.736203 <6>[ 1.964003] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10685 00:28:08.742868 <6>[ 1.974952] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x16014
10686 00:28:08.750124 <6>[ 1.985089] cros-ec-spi spi0.0: Chrome EC device registered
10687 00:28:08.756812 <6>[ 1.991123] mmc0: Command Queue Engine enabled
10688 00:28:08.763893 <6>[ 1.995899] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10689 00:28:08.770114 <6>[ 2.003673] mmcblk0: mmc0:0001 DA4128 116 GiB
10690 00:28:08.781273 <6>[ 2.015584] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10691 00:28:08.790501 <6>[ 2.018979] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10692 00:28:08.797594 <6>[ 2.022905] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10693 00:28:08.800967 <6>[ 2.032171] NET: Registered PF_PACKET protocol family
10694 00:28:08.807356 <6>[ 2.036830] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10695 00:28:08.810851 <6>[ 2.041427] 9pnet: Installing 9P2000 support
10696 00:28:08.817437 <6>[ 2.047248] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10697 00:28:08.823984 <5>[ 2.051133] Key type dns_resolver registered
10698 00:28:08.827344 <6>[ 2.062627] registered taskstats version 1
10699 00:28:08.833725 <5>[ 2.066996] Loading compiled-in X.509 certificates
10700 00:28:08.861277 <4>[ 2.089546] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10701 00:28:08.871349 <4>[ 2.100491] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10702 00:28:08.887065 <6>[ 2.121641] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10703 00:28:08.894024 <6>[ 2.128631] xhci-mtk 11200000.usb: xHCI Host Controller
10704 00:28:08.900875 <6>[ 2.134160] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10705 00:28:08.910834 <6>[ 2.142032] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10706 00:28:08.917959 <6>[ 2.151471] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10707 00:28:08.924313 <6>[ 2.157683] xhci-mtk 11200000.usb: xHCI Host Controller
10708 00:28:08.930595 <6>[ 2.163168] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10709 00:28:08.937301 <6>[ 2.170825] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10710 00:28:08.944417 <6>[ 2.178651] hub 1-0:1.0: USB hub found
10711 00:28:08.947244 <6>[ 2.182699] hub 1-0:1.0: 1 port detected
10712 00:28:08.957059 <6>[ 2.187013] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10713 00:28:08.960624 <6>[ 2.195767] hub 2-0:1.0: USB hub found
10714 00:28:08.964129 <6>[ 2.199810] hub 2-0:1.0: 1 port detected
10715 00:28:08.972569 <6>[ 2.207100] mtk-msdc 11f70000.mmc: Got CD GPIO
10716 00:28:08.990356 <6>[ 2.221500] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10717 00:28:09.000214 <6>[ 2.229968] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10718 00:28:09.006475 <6>[ 2.238311] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10719 00:28:09.016791 <6>[ 2.246673] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10720 00:28:09.023163 <6>[ 2.255013] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10721 00:28:09.033041 <6>[ 2.263365] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10722 00:28:09.040293 <6>[ 2.271703] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10723 00:28:09.049821 <6>[ 2.280053] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10724 00:28:09.056381 <6>[ 2.288391] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10725 00:28:09.066551 <6>[ 2.296740] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10726 00:28:09.072868 <6>[ 2.305082] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10727 00:28:09.082516 <6>[ 2.313432] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10728 00:28:09.089631 <6>[ 2.321770] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10729 00:28:09.099248 <6>[ 2.330119] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10730 00:28:09.105759 <6>[ 2.338457] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10731 00:28:09.112319 <6>[ 2.347148] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10732 00:28:09.119743 <6>[ 2.354314] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10733 00:28:09.126589 <6>[ 2.361130] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10734 00:28:09.136533 <6>[ 2.367902] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10735 00:28:09.142901 <6>[ 2.374830] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10736 00:28:09.149318 <6>[ 2.381690] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10737 00:28:09.159377 <6>[ 2.390820] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10738 00:28:09.169140 <6>[ 2.399941] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10739 00:28:09.179330 <6>[ 2.409234] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10740 00:28:09.189501 <6>[ 2.418703] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10741 00:28:09.198935 <6>[ 2.428170] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10742 00:28:09.205899 <6>[ 2.437290] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10743 00:28:09.215435 <6>[ 2.446756] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10744 00:28:09.225545 <6>[ 2.455875] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10745 00:28:09.235439 <6>[ 2.465173] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10746 00:28:09.245577 <6>[ 2.475355] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10747 00:28:09.255050 <6>[ 2.486809] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10748 00:28:09.262711 <6>[ 2.497732] Trying to probe devices needed for running init ...
10749 00:28:09.273394 <3>[ 2.505056] mt8192-audio 11210000.syscon:mt8192-afe-pcm: could not get audiosys reset:-517
10750 00:28:09.353619 <6>[ 2.585149] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10751 00:28:09.382241 <6>[ 2.616901] hub 2-1:1.0: USB hub found
10752 00:28:09.385380 <6>[ 2.621413] hub 2-1:1.0: 3 ports detected
10753 00:28:09.396377 <6>[ 2.630961] hub 2-1:1.0: USB hub found
10754 00:28:09.399172 <6>[ 2.635330] hub 2-1:1.0: 3 ports detected
10755 00:28:09.505214 <6>[ 2.737038] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10756 00:28:09.660192 <6>[ 2.895028] hub 1-1:1.0: USB hub found
10757 00:28:09.663544 <6>[ 2.899518] hub 1-1:1.0: 4 ports detected
10758 00:28:09.676307 <6>[ 2.911035] hub 1-1:1.0: USB hub found
10759 00:28:09.679767 <6>[ 2.915425] hub 1-1:1.0: 4 ports detected
10760 00:28:09.738268 <6>[ 2.969350] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10761 00:28:09.846403 <6>[ 3.077778] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10762 00:28:09.882525 <4>[ 3.114111] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10763 00:28:09.892541 <4>[ 3.123220] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10764 00:28:09.927208 <6>[ 3.162110] r8152 2-1.3:1.0 eth0: v1.12.13
10765 00:28:10.005829 <6>[ 3.237108] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10766 00:28:10.138360 <6>[ 3.373099] hub 1-1.4:1.0: USB hub found
10767 00:28:10.141839 <6>[ 3.377771] hub 1-1.4:1.0: 2 ports detected
10768 00:28:10.154445 <6>[ 3.389205] hub 1-1.4:1.0: USB hub found
10769 00:28:10.157889 <6>[ 3.393807] hub 1-1.4:1.0: 2 ports detected
10770 00:28:10.453741 <6>[ 3.685133] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10771 00:28:10.649353 <6>[ 3.881155] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10772 00:28:11.553864 <6>[ 4.788900] r8152 2-1.3:1.0 eth0: carrier on
10773 00:28:13.853920 <5>[ 4.813089] Sending DHCP requests .., OK
10774 00:28:13.860387 <6>[ 7.093277] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10775 00:28:13.863619 <6>[ 7.101580] IP-Config: Complete:
10776 00:28:13.877282 <6>[ 7.105075] device=eth0, hwaddr=00:e0:4c:68:02:81, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10777 00:28:13.883749 <6>[ 7.115786] host=mt8192-asurada-spherion-r0-cbg-9, domain=lava-rack, nis-domain=(none)
10778 00:28:13.890197 <6>[ 7.124401] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10779 00:28:13.897031 <6>[ 7.124411] nameserver0=192.168.201.1
10780 00:28:13.900546 <6>[ 7.136530] clk: Disabling unused clocks
10781 00:28:13.903726 <6>[ 7.142254] ALSA device list:
10782 00:28:13.910287 <6>[ 7.145499] No soundcards found.
10783 00:28:13.918078 <6>[ 7.153015] Freeing unused kernel memory: 8512K
10784 00:28:13.921091 <6>[ 7.157992] Run /init as init process
10785 00:28:13.930519 Loading, please wait...
10786 00:28:13.959622 Starting systemd-udevd version 252.22-1~deb12u1
10787 00:28:14.204245 <6>[ 7.436200] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10788 00:28:14.210692 <6>[ 7.437425] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10789 00:28:14.229603 <6>[ 7.461562] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10790 00:28:14.233201 <6>[ 7.465634] remoteproc remoteproc0: scp is available
10791 00:28:14.242782 <6>[ 7.467782] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10792 00:28:14.249097 <6>[ 7.467792] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10793 00:28:14.259465 <4>[ 7.467961] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10794 00:28:14.266122 <6>[ 7.468613] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10795 00:28:14.275833 <6>[ 7.468618] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10796 00:28:14.282315 <6>[ 7.468911] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10797 00:28:14.291833 <6>[ 7.468938] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10798 00:28:14.298510 <6>[ 7.468947] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10799 00:28:14.308360 <6>[ 7.468967] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10800 00:28:14.318776 <6>[ 7.469468] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10801 00:28:14.321508 <6>[ 7.474662] remoteproc remoteproc0: powering up scp
10802 00:28:14.331465 <6>[ 7.483697] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10803 00:28:14.338554 <6>[ 7.490345] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10804 00:28:14.344642 <6>[ 7.490393] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10805 00:28:14.351719 <4>[ 7.494556] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10806 00:28:14.358035 <6>[ 7.517286] mc: Linux media interface: v0.10
10807 00:28:14.364984 <3>[ 7.524124] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10808 00:28:14.371518 <4>[ 7.534270] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10809 00:28:14.381239 <3>[ 7.539543] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10810 00:28:14.387608 <6>[ 7.549361] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10811 00:28:14.394117 <6>[ 7.549470] videodev: Linux video capture interface: v2.00
10812 00:28:14.401331 <3>[ 7.557583] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10813 00:28:14.411514 <6>[ 7.614343] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10814 00:28:14.418276 <6>[ 7.617458] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10815 00:28:14.428162 <3>[ 7.620779] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10816 00:28:14.435473 <6>[ 7.620896] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10817 00:28:14.438349 <6>[ 7.620905] pci_bus 0000:00: root bus resource [bus 00-ff]
10818 00:28:14.444924 <6>[ 7.620913] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10819 00:28:14.455006 <6>[ 7.620916] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10820 00:28:14.461358 <6>[ 7.620967] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10821 00:28:14.471345 <6>[ 7.620985] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10822 00:28:14.474756 <6>[ 7.621068] pci 0000:00:00.0: supports D1 D2
10823 00:28:14.481534 <6>[ 7.621070] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10824 00:28:14.491341 <6>[ 7.622135] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10825 00:28:14.498381 <6>[ 7.622202] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10826 00:28:14.504542 <6>[ 7.622226] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10827 00:28:14.511323 <6>[ 7.622244] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10828 00:28:14.517677 <6>[ 7.622258] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10829 00:28:14.524441 <6>[ 7.622362] pci 0000:01:00.0: supports D1 D2
10830 00:28:14.531016 <6>[ 7.622363] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10831 00:28:14.537577 <6>[ 7.628276] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10832 00:28:14.547256 <6>[ 7.628547] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10833 00:28:14.557255 <6>[ 7.630009] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10834 00:28:14.563846 <4>[ 7.631033] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10835 00:28:14.570308 <4>[ 7.631033] Fallback method does not support PEC.
10836 00:28:14.576830 <6>[ 7.631880] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10837 00:28:14.586787 <3>[ 7.634127] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10838 00:28:14.594085 <6>[ 7.636870] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10839 00:28:14.600502 <6>[ 7.636907] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10840 00:28:14.610185 <6>[ 7.636911] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10841 00:28:14.616885 <6>[ 7.636918] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10842 00:28:14.623378 <6>[ 7.636931] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10843 00:28:14.633200 <6>[ 7.636944] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10844 00:28:14.636488 <6>[ 7.636956] pci 0000:00:00.0: PCI bridge to [bus 01]
10845 00:28:14.646347 <6>[ 7.636961] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10846 00:28:14.652985 <6>[ 7.637073] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10847 00:28:14.659524 <6>[ 7.637505] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10848 00:28:14.662790 <6>[ 7.637879] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10849 00:28:14.669960 <6>[ 7.642434] remoteproc remoteproc0: remote processor scp is now up
10850 00:28:14.679470 <3>[ 7.646386] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10851 00:28:14.686075 <3>[ 7.652164] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10852 00:28:14.696064 <6>[ 7.660310] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10853 00:28:14.706101 <3>[ 7.667260] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10854 00:28:14.712422 <3>[ 7.667264] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10855 00:28:14.722661 <3>[ 7.667286] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10856 00:28:14.729134 <3>[ 7.669679] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10857 00:28:14.738781 <5>[ 7.699557] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10858 00:28:14.745619 <3>[ 7.703187] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10859 00:28:14.748850 <6>[ 7.715853] Bluetooth: Core ver 2.22
10860 00:28:14.758974 <3>[ 7.722043] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10861 00:28:14.765421 <3>[ 7.722047] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10862 00:28:14.771853 <5>[ 7.726314] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10863 00:28:14.781705 <5>[ 7.726762] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10864 00:28:14.788536 <4>[ 7.726846] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10865 00:28:14.794943 <6>[ 7.726854] cfg80211: failed to load regulatory.db
10866 00:28:14.801839 <6>[ 7.730375] NET: Registered PF_BLUETOOTH protocol family
10867 00:28:14.808289 <3>[ 7.736602] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10868 00:28:14.815288 <6>[ 7.738403] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10869 00:28:14.827784 <6>[ 7.739966] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10870 00:28:14.834827 <6>[ 7.740197] usbcore: registered new interface driver uvcvideo
10871 00:28:14.841027 <6>[ 7.744028] Bluetooth: HCI device and connection manager initialized
10872 00:28:14.844591 <6>[ 7.744051] Bluetooth: HCI socket layer initialized
10873 00:28:14.854153 <3>[ 7.751513] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10874 00:28:14.857488 <6>[ 7.758984] Bluetooth: L2CAP socket layer initialized
10875 00:28:14.864156 <6>[ 7.759001] Bluetooth: SCO socket layer initialized
10876 00:28:14.870762 <3>[ 7.763552] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10877 00:28:14.877669 <6>[ 7.771508] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10878 00:28:14.887233 <3>[ 7.778894] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10879 00:28:14.893946 <6>[ 7.834187] usbcore: registered new interface driver btusb
10880 00:28:14.903968 <4>[ 7.835622] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10881 00:28:14.910828 <3>[ 7.835645] Bluetooth: hci0: Failed to load firmware file (-2)
10882 00:28:14.913597 <3>[ 7.835652] Bluetooth: hci0: Failed to set up firmware (-2)
10883 00:28:14.927187 <4>[ 7.835660] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10884 00:28:14.933434 <3>[ 7.841089] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10885 00:28:14.940238 <3>[ 7.841129] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10886 00:28:14.950301 <6>[ 7.853725] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10887 00:28:14.956748 <6>[ 8.189374] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10888 00:28:14.980522 <6>[ 8.216029] mt7921e 0000:01:00.0: ASIC revision: 79610010
10889 00:28:15.084303 <6>[ 8.316599] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10890 00:28:15.087706 <6>[ 8.316599]
10891 00:28:15.091079 Begin: Loading essential drivers ... done.
10892 00:28:15.097500 Begin: Running /scripts/init-premount ... done.
10893 00:28:15.104422 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10894 00:28:15.110919 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10895 00:28:15.113968 Device /sys/class/net/eth0 found
10896 00:28:15.114051 done.
10897 00:28:15.123760 Begin: Waiting up to 180 secs for any network device to become available ... done.
10898 00:28:15.165649 IP-Config: eth0 hardware address 00:e0:4c:68:02:81 mtu 1500 DHCP
10899 00:28:15.172827 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10900 00:28:15.179059 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10901 00:28:15.185363 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10902 00:28:15.192270 host : mt8192-asurada-spherion-r0-cbg-9
10903 00:28:15.198572 domain : lava-rack
10904 00:28:15.202299 rootserver: 192.168.201.1 rootpath:
10905 00:28:15.205362 filename :
10906 00:28:15.303926 done.
10907 00:28:15.311410 Begin: Running /scripts/nfs-bottom ... done.
10908 00:28:15.331936 Begin: Running /scripts/init-bottom ... done.
10909 00:28:15.351916 <6>[ 8.583880] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10910 00:28:16.699485 <6>[ 9.934897] NET: Registered PF_INET6 protocol family
10911 00:28:16.707083 <6>[ 9.942454] Segment Routing with IPv6
10912 00:28:16.709868 <6>[ 9.946416] In-situ OAM (IOAM) with IPv6
10913 00:28:16.881885 <30>[ 10.090855] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10914 00:28:16.888231 <30>[ 10.123983] systemd[1]: Detected architecture arm64.
10915 00:28:16.897316
10916 00:28:16.900730 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10917 00:28:16.900817
10918 00:28:16.927333 <30>[ 10.162718] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10919 00:28:18.028196 <30>[ 11.260445] systemd[1]: Queued start job for default target graphical.target.
10920 00:28:18.070106 <30>[ 11.302041] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10921 00:28:18.076631 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10922 00:28:18.098900 <30>[ 11.330851] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10923 00:28:18.108617 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10924 00:28:18.126732 <30>[ 11.358804] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10925 00:28:18.136502 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10926 00:28:18.154891 <30>[ 11.386428] systemd[1]: Created slice user.slice - User and Session Slice.
10927 00:28:18.161091 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10928 00:28:18.185584 <30>[ 11.413887] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10929 00:28:18.194945 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10930 00:28:18.212479 <30>[ 11.441359] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10931 00:28:18.219582 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10932 00:28:18.248172 <30>[ 11.469784] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10933 00:28:18.258211 <30>[ 11.489703] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10934 00:28:18.264332 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10935 00:28:18.281599 <30>[ 11.513494] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10936 00:28:18.291309 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10937 00:28:18.309909 <30>[ 11.541547] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10938 00:28:18.319212 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10939 00:28:18.334475 <30>[ 11.569651] systemd[1]: Reached target paths.target - Path Units.
10940 00:28:18.344437 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10941 00:28:18.361666 <30>[ 11.593605] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10942 00:28:18.368077 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10943 00:28:18.382117 <30>[ 11.617097] systemd[1]: Reached target slices.target - Slice Units.
10944 00:28:18.391929 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10945 00:28:18.406662 <30>[ 11.641607] systemd[1]: Reached target swap.target - Swaps.
10946 00:28:18.412771 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10947 00:28:18.434033 <30>[ 11.665637] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10948 00:28:18.443740 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10949 00:28:18.462681 <30>[ 11.694142] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10950 00:28:18.472368 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10951 00:28:18.492801 <30>[ 11.724660] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10952 00:28:18.502868 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10953 00:28:18.519518 <30>[ 11.750739] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10954 00:28:18.529107 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10955 00:28:18.546257 <30>[ 11.777938] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10956 00:28:18.552806 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10957 00:28:18.574594 <30>[ 11.806815] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10958 00:28:18.584746 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10959 00:28:18.605692 <30>[ 11.837646] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10960 00:28:18.615464 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10961 00:28:18.633933 <30>[ 11.865648] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10962 00:28:18.643533 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10963 00:28:18.701821 <30>[ 11.933405] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10964 00:28:18.708177 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10965 00:28:18.730247 <30>[ 11.961863] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10966 00:28:18.736263 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10967 00:28:18.762042 <30>[ 11.994235] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10968 00:28:18.768523 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10969 00:28:18.795483 <30>[ 12.021369] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10970 00:28:18.845356 <30>[ 12.077652] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10971 00:28:18.855000 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10972 00:28:18.878666 <30>[ 12.110981] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10973 00:28:18.889180 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10974 00:28:18.937692 <30>[ 12.169704] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10975 00:28:18.944427 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10976 00:28:18.970996 <30>[ 12.203162] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10977 00:28:18.977300 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10978 00:28:18.996123 <6>[ 12.228120] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10979 00:28:19.011164 <30>[ 12.243032] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10980 00:28:19.020689 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10981 00:28:19.065517 <30>[ 12.297839] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10982 00:28:19.072343 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10983 00:28:19.096325 <30>[ 12.328460] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10984 00:28:19.102989 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10985 00:28:19.110214 <6>[ 12.345958] fuse: init (API version 7.37)
10986 00:28:19.130223 <30>[ 12.362343] systemd[1]: Starting systemd-journald.service - Journal Service...
10987 00:28:19.136723 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10988 00:28:19.172227 <30>[ 12.403957] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10989 00:28:19.178142 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10990 00:28:19.204779 <30>[ 12.433510] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10991 00:28:19.211346 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10992 00:28:19.258103 <30>[ 12.490002] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10993 00:28:19.267617 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10994 00:28:19.288990 <30>[ 12.520691] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10995 00:28:19.305275 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug Al<3>[ 12.534718] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10996 00:28:19.305724 l udev Devices...
10997 00:28:19.331202 <30>[ 12.562533] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10998 00:28:19.337336 <3>[ 12.565642] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10999 00:28:19.347114 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
11000 00:28:19.366148 <30>[ 12.597551] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
11001 00:28:19.375696 <3>[ 12.605216] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11002 00:28:19.382212 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
11003 00:28:19.401345 <30>[ 12.633371] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
11004 00:28:19.407953 <3>[ 12.634861] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11005 00:28:19.418225 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
11006 00:28:19.438238 <3>[ 12.670321] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11007 00:28:19.450020 <30>[ 12.681944] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
11008 00:28:19.460232 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
11009 00:28:19.466680 <3>[ 12.699384] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11010 00:28:19.477576 <30>[ 12.710015] systemd[1]: modprobe@configfs.service: Deactivated successfully.
11011 00:28:19.488021 <30>[ 12.717975] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
11012 00:28:19.494459 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
11013 00:28:19.513046 <3>[ 12.744829] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11014 00:28:19.523402 <30>[ 12.755477] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
11015 00:28:19.529794 <30>[ 12.763755] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
11016 00:28:19.544004 [[0;32m OK [0m] Finished [0;1;39mmodprobe@d<3>[ 12.774885] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11017 00:28:19.550407 m_mod.s…e[0m - Load Kernel Module dm_mod.
11018 00:28:19.566353 <30>[ 12.798150] systemd[1]: modprobe@drm.service: Deactivated successfully.
11019 00:28:19.573171 <30>[ 12.805831] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
11020 00:28:19.582964 <3>[ 12.806441] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11021 00:28:19.589546 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
11022 00:28:19.610994 <30>[ 12.842937] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
11023 00:28:19.617961 <3>[ 12.847513] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11024 00:28:19.627792 <30>[ 12.851251] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
11025 00:28:19.637504 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
11026 00:28:19.648830 <3>[ 12.880905] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11027 00:28:19.659415 <30>[ 12.891482] systemd[1]: modprobe@fuse.service: Deactivated successfully.
11028 00:28:19.666539 <30>[ 12.899366] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
11029 00:28:19.680451 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m <3>[ 12.912441] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11030 00:28:19.683083 - Load Kernel Module fuse.
11031 00:28:19.702292 <30>[ 12.934336] systemd[1]: modprobe@loop.service: Deactivated successfully.
11032 00:28:19.709136 <30>[ 12.941829] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
11033 00:28:19.718900 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
11034 00:28:19.732350 <3>[ 12.963939] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11035 00:28:19.738861 <3>[ 12.964926] power_supply sbs-5-000b: driver failed to report `temp' property: -6
11036 00:28:19.748902 <30>[ 12.974610] systemd[1]: Finished systemd-modules-load.service - Load Kernel Modules.
11037 00:28:19.762705 <4>[ 12.980414] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
11038 00:28:19.772464 <3>[ 13.004124] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -6
11039 00:28:19.779321 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
11040 00:28:19.803005 <30>[ 13.031310] systemd[1]: Finished systemd-network-generator.service - Generate network units from Kernel command line.
11041 00:28:19.809549 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
11042 00:28:19.829780 <30>[ 13.061782] systemd[1]: Finished systemd-remount-fs.service - Remount Root and Kernel File Systems.
11043 00:28:19.840135 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
11044 00:28:19.857583 <30>[ 13.089873] systemd[1]: Started systemd-journald.service - Journal Service.
11045 00:28:19.864353 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
11046 00:28:19.885600 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
11047 00:28:19.904311 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
11048 00:28:19.945832 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
11049 00:28:19.970712 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
11050 00:28:19.992559 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
11051 00:28:20.014578 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
11052 00:28:20.040976 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
11053 00:28:20.069531 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users..<46>[ 13.302340] systemd-journald[309]: Received client request to flush runtime journal.
11054 00:28:20.069643 .
11055 00:28:20.098362 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
11056 00:28:20.118061 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
11057 00:28:20.138329 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
11058 00:28:20.158975 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
11059 00:28:20.859298 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
11060 00:28:20.909727 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
11061 00:28:21.514797 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
11062 00:28:21.561032 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
11063 00:28:21.576971 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
11064 00:28:21.596791 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
11065 00:28:21.645849 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
11066 00:28:21.670391 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
11067 00:28:21.895239 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11068 00:28:21.943497 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11069 00:28:22.019074 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11070 00:28:22.315751 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11071 00:28:22.341644 <6>[ 15.577926] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11072 00:28:22.370778 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11073 00:28:22.442740 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11074 00:28:22.506372 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11075 00:28:22.557124 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11076 00:28:22.577766 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11077 00:28:22.602393 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11078 00:28:22.625121 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11079 00:28:22.681273 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11080 00:28:22.694339 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11081 00:28:22.757332 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11082 00:28:22.780750 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11083 00:28:22.833961 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11084 00:28:22.971964 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11085 00:28:22.988843 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11086 00:28:23.004807 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11087 00:28:23.025050 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11088 00:28:23.052170 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11089 00:28:23.073171 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11090 00:28:23.089562 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11091 00:28:23.114264 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11092 00:28:23.137481 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11093 00:28:23.157156 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11094 00:28:23.175677 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11095 00:28:23.192759 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11096 00:28:23.199479 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11097 00:28:23.239187 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11098 00:28:23.272459 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11099 00:28:23.381040 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11100 00:28:23.394970 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11101 00:28:23.587569 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11102 00:28:23.637205 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11103 00:28:23.656222 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11104 00:28:23.672725 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11105 00:28:23.692616 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11106 00:28:23.709968 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11107 00:28:23.747020 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11108 00:28:23.767629 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11109 00:28:23.785814 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11110 00:28:23.839732 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11111 00:28:23.889077 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11112 00:28:23.989444
11113 00:28:23.992697 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11114 00:28:23.993134
11115 00:28:23.996129 debian-bookworm-arm64 login: root (automatic login)
11116 00:28:23.996546
11117 00:28:24.334847 Linux debian-bookworm-arm64 6.1.94-cip23 #1 SMP PREEMPT Fri Jun 21 00:04:56 UTC 2024 aarch64
11118 00:28:24.335363
11119 00:28:24.341457 The programs included with the Debian GNU/Linux system are free software;
11120 00:28:24.347653 the exact distribution terms for each program are described in the
11121 00:28:24.351289 individual files in /usr/share/doc/*/copyright.
11122 00:28:24.351738
11123 00:28:24.357577 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11124 00:28:24.360879 permitted by applicable law.
11125 00:28:25.583879 Matched prompt #10: / #
11127 00:28:25.585059 Setting prompt string to ['/ #']
11128 00:28:25.585501 end: 2.2.5.1 login-action (duration 00:00:20) [common]
11130 00:28:25.586558 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
11131 00:28:25.587016 start: 2.2.6 expect-shell-connection (timeout 00:03:10) [common]
11132 00:28:25.587384 Setting prompt string to ['/ #']
11133 00:28:25.587696 Forcing a shell prompt, looking for ['/ #']
11135 00:28:25.638451 / #
11136 00:28:25.639097 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11137 00:28:25.639529 Waiting using forced prompt support (timeout 00:02:30)
11138 00:28:25.644370
11139 00:28:25.645245 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11140 00:28:25.645811 start: 2.2.7 export-device-env (timeout 00:03:10) [common]
11142 00:28:25.747301 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14479210/extract-nfsrootfs-u_uwlwfy'
11143 00:28:25.753737 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14479210/extract-nfsrootfs-u_uwlwfy'
11145 00:28:25.855482 / # export NFS_SERVER_IP='192.168.201.1'
11146 00:28:25.861525 export NFS_SERVER_IP='192.168.201.1'
11147 00:28:25.861864 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11148 00:28:25.861995 end: 2.2 depthcharge-retry (duration 00:01:50) [common]
11149 00:28:25.862119 end: 2 depthcharge-action (duration 00:01:50) [common]
11150 00:28:25.862262 start: 3 lava-test-retry (timeout 00:07:32) [common]
11151 00:28:25.862349 start: 3.1 lava-test-shell (timeout 00:07:32) [common]
11152 00:28:25.862428 Using namespace: common
11154 00:28:25.963004 / # #
11155 00:28:25.963672 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11156 00:28:25.969884 #
11157 00:28:25.970885 Using /lava-14479210
11159 00:28:26.072090 / # export SHELL=/bin/bash
11160 00:28:26.078621 export SHELL=/bin/bash
11162 00:28:26.180358 / # . /lava-14479210/environment
11163 00:28:26.187113 . /lava-14479210/environment
11165 00:28:26.295762 / # /lava-14479210/bin/lava-test-runner /lava-14479210/0
11166 00:28:26.296398 Test shell timeout: 10s (minimum of the action and connection timeout)
11167 00:28:26.302384 /lava-14479210/bin/lava-test-runner /lava-14479210/0
11168 00:28:26.627571 + export TESTRUN_ID=0_timesync-off
11169 00:28:26.630755 + TESTRUN_ID=0_timesync-off
11170 00:28:26.633665 + cd /lava-14479210/0/tests/0_timesync-off
11171 00:28:26.636960 ++ cat uuid
11172 00:28:26.646235 + UUID=14479210_1.6.2.3.1
11173 00:28:26.646662 + set +x
11174 00:28:26.653233 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14479210_1.6.2.3.1>
11175 00:28:26.653932 Received signal: <STARTRUN> 0_timesync-off 14479210_1.6.2.3.1
11176 00:28:26.654367 Starting test lava.0_timesync-off (14479210_1.6.2.3.1)
11177 00:28:26.654805 Skipping test definition patterns.
11178 00:28:26.656149 + systemctl stop systemd-timesyncd
11179 00:28:26.732658 + set +x
11180 00:28:26.736059 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14479210_1.6.2.3.1>
11181 00:28:26.736763 Received signal: <ENDRUN> 0_timesync-off 14479210_1.6.2.3.1
11182 00:28:26.737176 Ending use of test pattern.
11183 00:28:26.737495 Ending test lava.0_timesync-off (14479210_1.6.2.3.1), duration 0.08
11185 00:28:26.837005 + export TESTRUN_ID=1_kselftest-rtc
11186 00:28:26.840108 + TESTRUN_ID=1_kselftest-rtc
11187 00:28:26.843397 + cd /lava-14479210/0/tests/1_kselftest-rtc
11188 00:28:26.846308 ++ cat uuid
11189 00:28:26.855685 + UUID=14479210_1.6.2.3.5
11190 00:28:26.856173 + set +x
11191 00:28:26.862788 <LAVA_SIGNAL_STARTRUN 1_kselftest-rtc 14479210_1.6.2.3.5>
11192 00:28:26.863527 Received signal: <STARTRUN> 1_kselftest-rtc 14479210_1.6.2.3.5
11193 00:28:26.863955 Starting test lava.1_kselftest-rtc (14479210_1.6.2.3.5)
11194 00:28:26.864361 Skipping test definition patterns.
11195 00:28:26.865853 + cd ./automated/linux/kselftest/
11196 00:28:26.892397 + ./kselftest.sh -c rtc -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.94-cip23/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11197 00:28:26.954004 INFO: install_deps skipped
11198 00:28:27.476851 --2024-06-21 00:28:27-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.94-cip23/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11199 00:28:27.487189 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11200 00:28:27.615943 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11201 00:28:27.743938 HTTP request sent, awaiting response... 200 OK
11202 00:28:27.747518 Length: 1642760 (1.6M) [application/octet-stream]
11203 00:28:27.750355 Saving to: 'kselftest_armhf.tar.gz'
11204 00:28:27.750825
11205 00:28:27.751195
11206 00:28:28.000461 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
11207 00:28:28.257445 kselftest_armhf.tar 2%[ ] 44.98K 176KB/s
11208 00:28:28.574495 kselftest_armhf.tar 13%[=> ] 217.50K 424KB/s
11209 00:28:28.878894 kselftest_armhf.tar 53%[=========> ] 863.72K 1.02MB/s
11210 00:28:28.885516 kselftest_armhf.tar 96%[==================> ] 1.52M 1.34MB/s
11211 00:28:28.891744 kselftest_armhf.tar 100%[===================>] 1.57M 1.38MB/s in 1.1s
11212 00:28:28.892452
11213 00:28:29.030573 2024-06-21 00:28:28 (1.38 MB/s) - 'kselftest_armhf.tar.gz' saved [1642760/1642760]
11214 00:28:29.030880
11215 00:28:34.304235 skiplist:
11216 00:28:34.307266 ========================================
11217 00:28:34.310575 ========================================
11218 00:28:34.363676 rtc:rtctest
11219 00:28:34.387615 ============== Tests to run ===============
11220 00:28:34.390654 rtc:rtctest
11221 00:28:34.393779 ===========End Tests to run ===============
11222 00:28:34.399246 shardfile-rtc pass
11223 00:28:34.538847 <12>[ 27.776773] kselftest: Running tests in rtc
11224 00:28:34.549326 TAP version 13
11225 00:28:34.565041 1..1
11226 00:28:34.600353 # selftests: rtc: rtctest
11227 00:28:35.091827 # TAP version 13
11228 00:28:35.092355 # 1..8
11229 00:28:35.095118 # # Starting 8 tests from 2 test cases.
11230 00:28:35.098548 # # RUN rtc.date_read ...
11231 00:28:35.105089 # # rtctest.c:49:date_read:Current RTC date/time is 21/06/2024 00:28:34.
11232 00:28:35.108228 # # OK rtc.date_read
11233 00:28:35.111827 # ok 1 rtc.date_read
11234 00:28:35.115089 # # RUN rtc.date_read_loop ...
11235 00:28:35.124628 # # rtctest.c:88:date_read_loop:Continuously reading RTC time for 30s (with 11ms breaks after every read).
11236 00:28:44.731448 <6>[ 37.973091] vpu: disabling
11237 00:28:44.734454 <6>[ 37.976187] vproc2: disabling
11238 00:28:44.738352 <6>[ 37.979963] vproc1: disabling
11239 00:28:44.742449 <6>[ 37.983939] vaud18: disabling
11240 00:28:44.749259 <6>[ 37.987645] vsram_others: disabling
11241 00:28:44.752471 <6>[ 37.991777] va09: disabling
11242 00:28:44.756062 <6>[ 37.995307] vsram_md: disabling
11243 00:28:44.759015 <6>[ 37.999073] Vgpu: disabling
11244 00:29:04.864687 # # rtctest.c:115:date_read_loop:Performed 2612 RTC time reads.
11245 00:29:04.867885 # # OK rtc.date_read_loop
11246 00:29:04.871118 # ok 2 rtc.date_read_loop
11247 00:29:04.874632 # # RUN rtc.uie_read ...
11248 00:29:07.840752 # # OK rtc.uie_read
11249 00:29:07.843454 # ok 3 rtc.uie_read
11250 00:29:07.846572 # # RUN rtc.uie_select ...
11251 00:29:10.840109 # # OK rtc.uie_select
11252 00:29:10.843525 # ok 4 rtc.uie_select
11253 00:29:10.846577 # # RUN rtc.alarm_alm_set ...
11254 00:29:10.852909 # # rtctest.c:202:alarm_alm_set:Alarm time now set to 00:29:14.
11255 00:29:10.856950 # # rtctest.c:207:alarm_alm_set:Expected -1 (-1) != rc (-1)
11256 00:29:10.863123 # # alarm_alm_set: Test terminated by assertion
11257 00:29:10.866331 # # FAIL rtc.alarm_alm_set
11258 00:29:10.869564 # not ok 5 rtc.alarm_alm_set
11259 00:29:10.873031 # # RUN rtc.alarm_wkalm_set ...
11260 00:29:10.879682 # # rtctest.c:258:alarm_wkalm_set:Alarm time now set to 21/06/2024 00:29:14.
11261 00:35:57.862594 Marking unfinished test run as failed
11264 00:35:57.864605 end: 3.1 lava-test-shell (duration 00:07:32) [common]
11266 00:35:57.866119 lava-test-retry failed: 1 of 1 attempts. 'lava-test-shell timed out after 452 seconds'
11268 00:35:57.867487 end: 3 lava-test-retry (duration 00:07:32) [common]
11270 00:35:57.868756 Cleaning after the job
11271 00:35:57.869193 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14479210/tftp-deploy-rkh18ac3/ramdisk
11272 00:35:57.878583 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14479210/tftp-deploy-rkh18ac3/kernel
11273 00:35:57.912127 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14479210/tftp-deploy-rkh18ac3/dtb
11274 00:35:57.912444 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14479210/tftp-deploy-rkh18ac3/nfsrootfs
11275 00:35:57.977224 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14479210/tftp-deploy-rkh18ac3/modules
11276 00:35:57.982506 start: 4.1 power-off (timeout 00:00:30) [common]
11277 00:35:57.982881 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-9', '--port=1', '--command=off']
11278 00:35:58.183092 >> Command sent successfully.
11279 00:35:58.185527 Returned 0 in 0 seconds
11280 00:35:58.286326 end: 4.1 power-off (duration 00:00:00) [common]
11282 00:35:58.287703 start: 4.2 read-feedback (timeout 00:10:00) [common]
11283 00:35:58.289010 Listened to connection for namespace 'common' for up to 1s
11284 00:35:59.289641 Finalising connection for namespace 'common'
11285 00:35:59.290446 Disconnecting from shell: Finalise
11286 00:35:59.391504 end: 4.2 read-feedback (duration 00:00:01) [common]
11287 00:35:59.392147 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14479210
11288 00:36:00.002715 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14479210
11289 00:36:00.002915 TestError: A test failed to run, look at the error message.