Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 21
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
1 00:26:24.646389 lava-dispatcher, installed at version: 2024.03
2 00:26:24.646619 start: 0 validate
3 00:26:24.646739 Start time: 2024-06-21 00:26:24.646733+00:00 (UTC)
4 00:26:24.646877 Using caching service: 'http://localhost/cache/?uri=%s'
5 00:26:24.647018 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 00:26:24.910202 Using caching service: 'http://localhost/cache/?uri=%s'
7 00:26:24.910389 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.94-cip23%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 00:26:25.166771 Using caching service: 'http://localhost/cache/?uri=%s'
9 00:26:25.166990 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.94-cip23%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 00:26:25.422309 Using caching service: 'http://localhost/cache/?uri=%s'
11 00:26:25.422474 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 00:26:25.671179 Using caching service: 'http://localhost/cache/?uri=%s'
13 00:26:25.671354 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.94-cip23%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 00:26:25.927973 validate duration: 1.28
16 00:26:25.928283 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 00:26:25.928426 start: 1.1 download-retry (timeout 00:10:00) [common]
18 00:26:25.928575 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 00:26:25.928801 Not decompressing ramdisk as can be used compressed.
20 00:26:25.928912 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 00:26:25.928988 saving as /var/lib/lava/dispatcher/tmp/14479216/tftp-deploy-t4ydc2e7/ramdisk/initrd.cpio.gz
22 00:26:25.929066 total size: 5628169 (5 MB)
23 00:26:25.930207 progress 0 % (0 MB)
24 00:26:25.931842 progress 5 % (0 MB)
25 00:26:25.933426 progress 10 % (0 MB)
26 00:26:25.934880 progress 15 % (0 MB)
27 00:26:25.936644 progress 20 % (1 MB)
28 00:26:25.938210 progress 25 % (1 MB)
29 00:26:25.940033 progress 30 % (1 MB)
30 00:26:25.941590 progress 35 % (1 MB)
31 00:26:25.942979 progress 40 % (2 MB)
32 00:26:25.944567 progress 45 % (2 MB)
33 00:26:25.946172 progress 50 % (2 MB)
34 00:26:25.947699 progress 55 % (2 MB)
35 00:26:25.949334 progress 60 % (3 MB)
36 00:26:25.950700 progress 65 % (3 MB)
37 00:26:25.952281 progress 70 % (3 MB)
38 00:26:25.953779 progress 75 % (4 MB)
39 00:26:25.955371 progress 80 % (4 MB)
40 00:26:25.956858 progress 85 % (4 MB)
41 00:26:25.958581 progress 90 % (4 MB)
42 00:26:25.960137 progress 95 % (5 MB)
43 00:26:25.961603 progress 100 % (5 MB)
44 00:26:25.961831 5 MB downloaded in 0.03 s (163.86 MB/s)
45 00:26:25.962007 end: 1.1.1 http-download (duration 00:00:00) [common]
47 00:26:25.962281 end: 1.1 download-retry (duration 00:00:00) [common]
48 00:26:25.962378 start: 1.2 download-retry (timeout 00:10:00) [common]
49 00:26:25.962470 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 00:26:25.962624 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.94-cip23/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 00:26:25.962715 saving as /var/lib/lava/dispatcher/tmp/14479216/tftp-deploy-t4ydc2e7/kernel/Image
52 00:26:25.962804 total size: 54813184 (52 MB)
53 00:26:25.962895 No compression specified
54 00:26:25.964392 progress 0 % (0 MB)
55 00:26:25.978193 progress 5 % (2 MB)
56 00:26:25.992173 progress 10 % (5 MB)
57 00:26:26.005987 progress 15 % (7 MB)
58 00:26:26.019904 progress 20 % (10 MB)
59 00:26:26.033966 progress 25 % (13 MB)
60 00:26:26.047731 progress 30 % (15 MB)
61 00:26:26.061539 progress 35 % (18 MB)
62 00:26:26.075315 progress 40 % (20 MB)
63 00:26:26.089080 progress 45 % (23 MB)
64 00:26:26.103086 progress 50 % (26 MB)
65 00:26:26.116766 progress 55 % (28 MB)
66 00:26:26.130393 progress 60 % (31 MB)
67 00:26:26.144103 progress 65 % (34 MB)
68 00:26:26.157789 progress 70 % (36 MB)
69 00:26:26.171491 progress 75 % (39 MB)
70 00:26:26.185116 progress 80 % (41 MB)
71 00:26:26.198726 progress 85 % (44 MB)
72 00:26:26.212499 progress 90 % (47 MB)
73 00:26:26.226181 progress 95 % (49 MB)
74 00:26:26.239640 progress 100 % (52 MB)
75 00:26:26.239901 52 MB downloaded in 0.28 s (188.65 MB/s)
76 00:26:26.240055 end: 1.2.1 http-download (duration 00:00:00) [common]
78 00:26:26.240268 end: 1.2 download-retry (duration 00:00:00) [common]
79 00:26:26.240351 start: 1.3 download-retry (timeout 00:10:00) [common]
80 00:26:26.240428 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 00:26:26.240563 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.94-cip23/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 00:26:26.240626 saving as /var/lib/lava/dispatcher/tmp/14479216/tftp-deploy-t4ydc2e7/dtb/mt8192-asurada-spherion-r0.dtb
83 00:26:26.240680 total size: 47258 (0 MB)
84 00:26:26.240779 No compression specified
85 00:26:26.241857 progress 69 % (0 MB)
86 00:26:26.242118 progress 100 % (0 MB)
87 00:26:26.242269 0 MB downloaded in 0.00 s (28.41 MB/s)
88 00:26:26.242383 end: 1.3.1 http-download (duration 00:00:00) [common]
90 00:26:26.242586 end: 1.3 download-retry (duration 00:00:00) [common]
91 00:26:26.242664 start: 1.4 download-retry (timeout 00:10:00) [common]
92 00:26:26.242740 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 00:26:26.242846 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 00:26:26.242907 saving as /var/lib/lava/dispatcher/tmp/14479216/tftp-deploy-t4ydc2e7/nfsrootfs/full.rootfs.tar
95 00:26:26.242960 total size: 120894716 (115 MB)
96 00:26:26.243014 Using unxz to decompress xz
97 00:26:26.244214 progress 0 % (0 MB)
98 00:26:26.579977 progress 5 % (5 MB)
99 00:26:26.921428 progress 10 % (11 MB)
100 00:26:27.271762 progress 15 % (17 MB)
101 00:26:27.593323 progress 20 % (23 MB)
102 00:26:27.893459 progress 25 % (28 MB)
103 00:26:28.236193 progress 30 % (34 MB)
104 00:26:28.553802 progress 35 % (40 MB)
105 00:26:28.721226 progress 40 % (46 MB)
106 00:26:28.900974 progress 45 % (51 MB)
107 00:26:29.203827 progress 50 % (57 MB)
108 00:26:29.553843 progress 55 % (63 MB)
109 00:26:29.885953 progress 60 % (69 MB)
110 00:26:30.226536 progress 65 % (74 MB)
111 00:26:30.564233 progress 70 % (80 MB)
112 00:26:30.906853 progress 75 % (86 MB)
113 00:26:31.238362 progress 80 % (92 MB)
114 00:26:31.569694 progress 85 % (98 MB)
115 00:26:31.903225 progress 90 % (103 MB)
116 00:26:32.220490 progress 95 % (109 MB)
117 00:26:32.584843 progress 100 % (115 MB)
118 00:26:32.591630 115 MB downloaded in 6.35 s (18.16 MB/s)
119 00:26:32.591779 end: 1.4.1 http-download (duration 00:00:06) [common]
121 00:26:32.591989 end: 1.4 download-retry (duration 00:00:06) [common]
122 00:26:32.592069 start: 1.5 download-retry (timeout 00:09:53) [common]
123 00:26:32.592144 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 00:26:32.592269 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.94-cip23/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 00:26:32.592329 saving as /var/lib/lava/dispatcher/tmp/14479216/tftp-deploy-t4ydc2e7/modules/modules.tar
126 00:26:32.592382 total size: 8618924 (8 MB)
127 00:26:32.592435 Using unxz to decompress xz
128 00:26:32.593732 progress 0 % (0 MB)
129 00:26:32.612817 progress 5 % (0 MB)
130 00:26:32.635976 progress 10 % (0 MB)
131 00:26:32.660917 progress 15 % (1 MB)
132 00:26:32.685657 progress 20 % (1 MB)
133 00:26:32.710934 progress 25 % (2 MB)
134 00:26:32.735502 progress 30 % (2 MB)
135 00:26:32.761184 progress 35 % (2 MB)
136 00:26:32.785264 progress 40 % (3 MB)
137 00:26:32.808732 progress 45 % (3 MB)
138 00:26:32.831521 progress 50 % (4 MB)
139 00:26:32.855265 progress 55 % (4 MB)
140 00:26:32.878882 progress 60 % (4 MB)
141 00:26:32.901882 progress 65 % (5 MB)
142 00:26:32.928825 progress 70 % (5 MB)
143 00:26:32.952984 progress 75 % (6 MB)
144 00:26:32.976176 progress 80 % (6 MB)
145 00:26:32.999036 progress 85 % (7 MB)
146 00:26:33.021987 progress 90 % (7 MB)
147 00:26:33.048394 progress 95 % (7 MB)
148 00:26:33.076459 progress 100 % (8 MB)
149 00:26:33.080837 8 MB downloaded in 0.49 s (16.83 MB/s)
150 00:26:33.080999 end: 1.5.1 http-download (duration 00:00:00) [common]
152 00:26:33.081214 end: 1.5 download-retry (duration 00:00:00) [common]
153 00:26:33.081294 start: 1.6 prepare-tftp-overlay (timeout 00:09:53) [common]
154 00:26:33.081373 start: 1.6.1 extract-nfsrootfs (timeout 00:09:53) [common]
155 00:26:36.637005 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14479216/extract-nfsrootfs-72fyp65p
156 00:26:36.637194 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 00:26:36.637288 start: 1.6.2 lava-overlay (timeout 00:09:49) [common]
158 00:26:36.637440 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14479216/lava-overlay-i1d83tyd
159 00:26:36.637563 makedir: /var/lib/lava/dispatcher/tmp/14479216/lava-overlay-i1d83tyd/lava-14479216/bin
160 00:26:36.637656 makedir: /var/lib/lava/dispatcher/tmp/14479216/lava-overlay-i1d83tyd/lava-14479216/tests
161 00:26:36.637743 makedir: /var/lib/lava/dispatcher/tmp/14479216/lava-overlay-i1d83tyd/lava-14479216/results
162 00:26:36.637826 Creating /var/lib/lava/dispatcher/tmp/14479216/lava-overlay-i1d83tyd/lava-14479216/bin/lava-add-keys
163 00:26:36.637953 Creating /var/lib/lava/dispatcher/tmp/14479216/lava-overlay-i1d83tyd/lava-14479216/bin/lava-add-sources
164 00:26:36.638071 Creating /var/lib/lava/dispatcher/tmp/14479216/lava-overlay-i1d83tyd/lava-14479216/bin/lava-background-process-start
165 00:26:36.638187 Creating /var/lib/lava/dispatcher/tmp/14479216/lava-overlay-i1d83tyd/lava-14479216/bin/lava-background-process-stop
166 00:26:36.638311 Creating /var/lib/lava/dispatcher/tmp/14479216/lava-overlay-i1d83tyd/lava-14479216/bin/lava-common-functions
167 00:26:36.638426 Creating /var/lib/lava/dispatcher/tmp/14479216/lava-overlay-i1d83tyd/lava-14479216/bin/lava-echo-ipv4
168 00:26:36.638544 Creating /var/lib/lava/dispatcher/tmp/14479216/lava-overlay-i1d83tyd/lava-14479216/bin/lava-install-packages
169 00:26:36.638655 Creating /var/lib/lava/dispatcher/tmp/14479216/lava-overlay-i1d83tyd/lava-14479216/bin/lava-installed-packages
170 00:26:36.638766 Creating /var/lib/lava/dispatcher/tmp/14479216/lava-overlay-i1d83tyd/lava-14479216/bin/lava-os-build
171 00:26:36.638876 Creating /var/lib/lava/dispatcher/tmp/14479216/lava-overlay-i1d83tyd/lava-14479216/bin/lava-probe-channel
172 00:26:36.638986 Creating /var/lib/lava/dispatcher/tmp/14479216/lava-overlay-i1d83tyd/lava-14479216/bin/lava-probe-ip
173 00:26:36.639097 Creating /var/lib/lava/dispatcher/tmp/14479216/lava-overlay-i1d83tyd/lava-14479216/bin/lava-target-ip
174 00:26:36.639206 Creating /var/lib/lava/dispatcher/tmp/14479216/lava-overlay-i1d83tyd/lava-14479216/bin/lava-target-mac
175 00:26:36.639316 Creating /var/lib/lava/dispatcher/tmp/14479216/lava-overlay-i1d83tyd/lava-14479216/bin/lava-target-storage
176 00:26:36.639428 Creating /var/lib/lava/dispatcher/tmp/14479216/lava-overlay-i1d83tyd/lava-14479216/bin/lava-test-case
177 00:26:36.639538 Creating /var/lib/lava/dispatcher/tmp/14479216/lava-overlay-i1d83tyd/lava-14479216/bin/lava-test-event
178 00:26:36.639646 Creating /var/lib/lava/dispatcher/tmp/14479216/lava-overlay-i1d83tyd/lava-14479216/bin/lava-test-feedback
179 00:26:36.639756 Creating /var/lib/lava/dispatcher/tmp/14479216/lava-overlay-i1d83tyd/lava-14479216/bin/lava-test-raise
180 00:26:36.639864 Creating /var/lib/lava/dispatcher/tmp/14479216/lava-overlay-i1d83tyd/lava-14479216/bin/lava-test-reference
181 00:26:36.639973 Creating /var/lib/lava/dispatcher/tmp/14479216/lava-overlay-i1d83tyd/lava-14479216/bin/lava-test-runner
182 00:26:36.640083 Creating /var/lib/lava/dispatcher/tmp/14479216/lava-overlay-i1d83tyd/lava-14479216/bin/lava-test-set
183 00:26:36.640192 Creating /var/lib/lava/dispatcher/tmp/14479216/lava-overlay-i1d83tyd/lava-14479216/bin/lava-test-shell
184 00:26:36.640304 Updating /var/lib/lava/dispatcher/tmp/14479216/lava-overlay-i1d83tyd/lava-14479216/bin/lava-add-keys (debian)
185 00:26:36.640439 Updating /var/lib/lava/dispatcher/tmp/14479216/lava-overlay-i1d83tyd/lava-14479216/bin/lava-add-sources (debian)
186 00:26:36.640562 Updating /var/lib/lava/dispatcher/tmp/14479216/lava-overlay-i1d83tyd/lava-14479216/bin/lava-install-packages (debian)
187 00:26:36.640683 Updating /var/lib/lava/dispatcher/tmp/14479216/lava-overlay-i1d83tyd/lava-14479216/bin/lava-installed-packages (debian)
188 00:26:36.640812 Updating /var/lib/lava/dispatcher/tmp/14479216/lava-overlay-i1d83tyd/lava-14479216/bin/lava-os-build (debian)
189 00:26:36.640919 Creating /var/lib/lava/dispatcher/tmp/14479216/lava-overlay-i1d83tyd/lava-14479216/environment
190 00:26:36.641002 LAVA metadata
191 00:26:36.641068 - LAVA_JOB_ID=14479216
192 00:26:36.641123 - LAVA_DISPATCHER_IP=192.168.201.1
193 00:26:36.641215 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:49) [common]
194 00:26:36.641271 skipped lava-vland-overlay
195 00:26:36.641349 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 00:26:36.641420 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:49) [common]
197 00:26:36.641472 skipped lava-multinode-overlay
198 00:26:36.641535 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 00:26:36.641605 start: 1.6.2.3 test-definition (timeout 00:09:49) [common]
200 00:26:36.641666 Loading test definitions
201 00:26:36.641739 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:49) [common]
202 00:26:36.641796 Using /lava-14479216 at stage 0
203 00:26:36.642064 uuid=14479216_1.6.2.3.1 testdef=None
204 00:26:36.642143 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 00:26:36.642217 start: 1.6.2.3.2 test-overlay (timeout 00:09:49) [common]
206 00:26:36.642616 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 00:26:36.642819 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:49) [common]
209 00:26:36.643324 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 00:26:36.643539 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:49) [common]
212 00:26:36.644030 runner path: /var/lib/lava/dispatcher/tmp/14479216/lava-overlay-i1d83tyd/lava-14479216/0/tests/0_timesync-off test_uuid 14479216_1.6.2.3.1
213 00:26:36.644173 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 00:26:36.644375 start: 1.6.2.3.5 git-repo-action (timeout 00:09:49) [common]
216 00:26:36.644439 Using /lava-14479216 at stage 0
217 00:26:36.644525 Fetching tests from https://github.com/kernelci/test-definitions.git
218 00:26:36.644600 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14479216/lava-overlay-i1d83tyd/lava-14479216/0/tests/1_kselftest-tpm2'
219 00:26:38.694411 Running '/usr/bin/git checkout kernelci.org
220 00:26:38.840253 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14479216/lava-overlay-i1d83tyd/lava-14479216/0/tests/1_kselftest-tpm2/automated/linux/kselftest/kselftest.yaml
221 00:26:38.840656 uuid=14479216_1.6.2.3.5 testdef=None
222 00:26:38.840802 end: 1.6.2.3.5 git-repo-action (duration 00:00:02) [common]
224 00:26:38.840998 start: 1.6.2.3.6 test-overlay (timeout 00:09:47) [common]
225 00:26:38.841635 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 00:26:38.841839 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:47) [common]
228 00:26:38.842701 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 00:26:38.842916 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:47) [common]
231 00:26:38.843850 runner path: /var/lib/lava/dispatcher/tmp/14479216/lava-overlay-i1d83tyd/lava-14479216/0/tests/1_kselftest-tpm2 test_uuid 14479216_1.6.2.3.5
232 00:26:38.843949 BOARD='mt8192-asurada-spherion-r0'
233 00:26:38.844010 BRANCH='cip'
234 00:26:38.844065 SKIPFILE='/dev/null'
235 00:26:38.844117 SKIP_INSTALL='True'
236 00:26:38.844167 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.94-cip23/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 00:26:38.844219 TST_CASENAME=''
238 00:26:38.844268 TST_CMDFILES='tpm2'
239 00:26:38.844401 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 00:26:38.844583 Creating lava-test-runner.conf files
242 00:26:38.844638 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14479216/lava-overlay-i1d83tyd/lava-14479216/0 for stage 0
243 00:26:38.844742 - 0_timesync-off
244 00:26:38.844815 - 1_kselftest-tpm2
245 00:26:38.844903 end: 1.6.2.3 test-definition (duration 00:00:02) [common]
246 00:26:38.844980 start: 1.6.2.4 compress-overlay (timeout 00:09:47) [common]
247 00:26:45.918799 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 00:26:45.918929 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:40) [common]
249 00:26:45.919017 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 00:26:45.919103 end: 1.6.2 lava-overlay (duration 00:00:09) [common]
251 00:26:45.919191 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:40) [common]
252 00:26:46.078621 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 00:26:46.078763 start: 1.6.4 extract-modules (timeout 00:09:40) [common]
254 00:26:46.078842 extracting modules file /var/lib/lava/dispatcher/tmp/14479216/tftp-deploy-t4ydc2e7/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14479216/extract-nfsrootfs-72fyp65p
255 00:26:46.303471 extracting modules file /var/lib/lava/dispatcher/tmp/14479216/tftp-deploy-t4ydc2e7/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14479216/extract-overlay-ramdisk-1m25c5vz/ramdisk
256 00:26:46.527964 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 00:26:46.528099 start: 1.6.5 apply-overlay-tftp (timeout 00:09:39) [common]
258 00:26:46.528179 [common] Applying overlay to NFS
259 00:26:46.528240 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14479216/compress-overlay-qyv0p0of/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14479216/extract-nfsrootfs-72fyp65p
260 00:26:47.360643 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 00:26:47.360901 start: 1.6.6 configure-preseed-file (timeout 00:09:39) [common]
262 00:26:47.360985 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 00:26:47.361064 start: 1.6.7 compress-ramdisk (timeout 00:09:39) [common]
264 00:26:47.361132 Building ramdisk /var/lib/lava/dispatcher/tmp/14479216/extract-overlay-ramdisk-1m25c5vz/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14479216/extract-overlay-ramdisk-1m25c5vz/ramdisk
265 00:26:47.667977 >> 130487 blocks
266 00:26:49.697288 rename /var/lib/lava/dispatcher/tmp/14479216/extract-overlay-ramdisk-1m25c5vz/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14479216/tftp-deploy-t4ydc2e7/ramdisk/ramdisk.cpio.gz
267 00:26:49.697517 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 00:26:49.697648 start: 1.6.8 prepare-kernel (timeout 00:09:36) [common]
269 00:26:49.697763 start: 1.6.8.1 prepare-fit (timeout 00:09:36) [common]
270 00:26:49.697878 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14479216/tftp-deploy-t4ydc2e7/kernel/Image']
271 00:27:03.663137 Returned 0 in 13 seconds
272 00:27:03.763650 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14479216/tftp-deploy-t4ydc2e7/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14479216/tftp-deploy-t4ydc2e7/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14479216/tftp-deploy-t4ydc2e7/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14479216/tftp-deploy-t4ydc2e7/kernel/image.itb
273 00:27:04.159398 output: FIT description: Kernel Image image with one or more FDT blobs
274 00:27:04.159530 output: Created: Fri Jun 21 01:27:04 2024
275 00:27:04.159600 output: Image 0 (kernel-1)
276 00:27:04.159660 output: Description:
277 00:27:04.159723 output: Created: Fri Jun 21 01:27:04 2024
278 00:27:04.159780 output: Type: Kernel Image
279 00:27:04.159838 output: Compression: lzma compressed
280 00:27:04.159898 output: Data Size: 13124896 Bytes = 12817.28 KiB = 12.52 MiB
281 00:27:04.159956 output: Architecture: AArch64
282 00:27:04.160010 output: OS: Linux
283 00:27:04.160064 output: Load Address: 0x00000000
284 00:27:04.160116 output: Entry Point: 0x00000000
285 00:27:04.160169 output: Hash algo: crc32
286 00:27:04.160222 output: Hash value: ab2f7826
287 00:27:04.160274 output: Image 1 (fdt-1)
288 00:27:04.160324 output: Description: mt8192-asurada-spherion-r0
289 00:27:04.160373 output: Created: Fri Jun 21 01:27:04 2024
290 00:27:04.160425 output: Type: Flat Device Tree
291 00:27:04.160473 output: Compression: uncompressed
292 00:27:04.160523 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
293 00:27:04.160571 output: Architecture: AArch64
294 00:27:04.160621 output: Hash algo: crc32
295 00:27:04.160669 output: Hash value: 0f8e4d2e
296 00:27:04.160757 output: Image 2 (ramdisk-1)
297 00:27:04.160807 output: Description: unavailable
298 00:27:04.160855 output: Created: Fri Jun 21 01:27:04 2024
299 00:27:04.160904 output: Type: RAMDisk Image
300 00:27:04.160953 output: Compression: uncompressed
301 00:27:04.161001 output: Data Size: 18747625 Bytes = 18308.23 KiB = 17.88 MiB
302 00:27:04.161048 output: Architecture: AArch64
303 00:27:04.161096 output: OS: Linux
304 00:27:04.161143 output: Load Address: unavailable
305 00:27:04.161208 output: Entry Point: unavailable
306 00:27:04.161287 output: Hash algo: crc32
307 00:27:04.161380 output: Hash value: 53fcac96
308 00:27:04.161427 output: Default Configuration: 'conf-1'
309 00:27:04.161474 output: Configuration 0 (conf-1)
310 00:27:04.161521 output: Description: mt8192-asurada-spherion-r0
311 00:27:04.161569 output: Kernel: kernel-1
312 00:27:04.161616 output: Init Ramdisk: ramdisk-1
313 00:27:04.161664 output: FDT: fdt-1
314 00:27:04.161712 output: Loadables: kernel-1
315 00:27:04.161760 output:
316 00:27:04.161900 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
317 00:27:04.161992 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
318 00:27:04.162083 end: 1.6 prepare-tftp-overlay (duration 00:00:31) [common]
319 00:27:04.162164 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:22) [common]
320 00:27:04.162241 No LXC device requested
321 00:27:04.162317 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 00:27:04.162394 start: 1.8 deploy-device-env (timeout 00:09:22) [common]
323 00:27:04.162464 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 00:27:04.162525 Checking files for TFTP limit of 4294967296 bytes.
325 00:27:04.162969 end: 1 tftp-deploy (duration 00:00:38) [common]
326 00:27:04.163067 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 00:27:04.163150 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 00:27:04.163261 substitutions:
329 00:27:04.163335 - {DTB}: 14479216/tftp-deploy-t4ydc2e7/dtb/mt8192-asurada-spherion-r0.dtb
330 00:27:04.163394 - {INITRD}: 14479216/tftp-deploy-t4ydc2e7/ramdisk/ramdisk.cpio.gz
331 00:27:04.163448 - {KERNEL}: 14479216/tftp-deploy-t4ydc2e7/kernel/Image
332 00:27:04.163498 - {LAVA_MAC}: None
333 00:27:04.163549 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14479216/extract-nfsrootfs-72fyp65p
334 00:27:04.163599 - {NFS_SERVER_IP}: 192.168.201.1
335 00:27:04.163648 - {PRESEED_CONFIG}: None
336 00:27:04.163705 - {PRESEED_LOCAL}: None
337 00:27:04.163755 - {RAMDISK}: 14479216/tftp-deploy-t4ydc2e7/ramdisk/ramdisk.cpio.gz
338 00:27:04.163804 - {ROOT_PART}: None
339 00:27:04.163853 - {ROOT}: None
340 00:27:04.163902 - {SERVER_IP}: 192.168.201.1
341 00:27:04.163950 - {TEE}: None
342 00:27:04.163999 Parsed boot commands:
343 00:27:04.164046 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 00:27:04.164196 Parsed boot commands: tftpboot 192.168.201.1 14479216/tftp-deploy-t4ydc2e7/kernel/image.itb 14479216/tftp-deploy-t4ydc2e7/kernel/cmdline
345 00:27:04.164281 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 00:27:04.164357 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 00:27:04.164439 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 00:27:04.164515 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 00:27:04.164577 Not connected, no need to disconnect.
350 00:27:04.164644 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 00:27:04.164741 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 00:27:04.164819 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-1'
353 00:27:04.168125 Setting prompt string to ['lava-test: # ']
354 00:27:04.168448 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 00:27:04.168551 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 00:27:04.168665 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 00:27:04.168791 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 00:27:04.168980 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-1', '--port=1', '--command=reboot']
359 00:27:13.325893 >> Command sent successfully.
360 00:27:13.329121 Returned 0 in 9 seconds
361 00:27:13.429425 end: 2.2.2.1 pdu-reboot (duration 00:00:09) [common]
363 00:27:13.429694 end: 2.2.2 reset-device (duration 00:00:09) [common]
364 00:27:13.429794 start: 2.2.3 depthcharge-start (timeout 00:04:51) [common]
365 00:27:13.429879 Setting prompt string to 'Starting depthcharge on Spherion...'
366 00:27:13.429941 Changing prompt to 'Starting depthcharge on Spherion...'
367 00:27:13.430003 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 00:27:13.430341 [Enter `^Ec?' for help]
369 00:27:14.721469
370 00:27:14.721604
371 00:27:14.721670 F0: 102B 0000
372 00:27:14.721735
373 00:27:14.721796 F3: 1001 0000 [0200]
374 00:27:14.724539
375 00:27:14.724652 F3: 1001 0000
376 00:27:14.724765
377 00:27:14.724856 F7: 102D 0000
378 00:27:14.724933
379 00:27:14.728131 F1: 0000 0000
380 00:27:14.728213
381 00:27:14.728279 V0: 0000 0000 [0001]
382 00:27:14.728339
383 00:27:14.731099 00: 0007 8000
384 00:27:14.731179
385 00:27:14.731239 01: 0000 0000
386 00:27:14.731296
387 00:27:14.734816 BP: 0C00 0209 [0000]
388 00:27:14.734897
389 00:27:14.734957 G0: 1182 0000
390 00:27:14.735013
391 00:27:14.737833 EC: 0000 0021 [4000]
392 00:27:14.737912
393 00:27:14.737978 S7: 0000 0000 [0000]
394 00:27:14.738034
395 00:27:14.741419 CC: 0000 0000 [0001]
396 00:27:14.741501
397 00:27:14.741563 T0: 0000 0040 [010F]
398 00:27:14.741620
399 00:27:14.744411 Jump to BL
400 00:27:14.744489
401 00:27:14.768607
402 00:27:14.768769
403 00:27:14.775381 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
404 00:27:14.779321 ARM64: Exception handlers installed.
405 00:27:14.782556 ARM64: Testing exception
406 00:27:14.786143 ARM64: Done test exception
407 00:27:14.793909 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
408 00:27:14.800889 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
409 00:27:14.808125 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
410 00:27:14.819998 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
411 00:27:14.827544 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
412 00:27:14.834927 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
413 00:27:14.845698 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
414 00:27:14.852427 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
415 00:27:14.872104 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
416 00:27:14.876034 WDT: Last reset was cold boot
417 00:27:14.879813 SPI1(PAD0) initialized at 2873684 Hz
418 00:27:14.883105 SPI5(PAD0) initialized at 992727 Hz
419 00:27:14.883206 VBOOT: Loading verstage.
420 00:27:14.890216 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
421 00:27:14.894563 FMAP: Found "FLASH" version 1.1 at 0x20000.
422 00:27:14.898189 FMAP: base = 0x0 size = 0x800000 #areas = 25
423 00:27:14.901702 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
424 00:27:14.909712 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
425 00:27:14.916542 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
426 00:27:14.926914 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
427 00:27:14.927056
428 00:27:14.927166
429 00:27:14.934691 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
430 00:27:14.938488 ARM64: Exception handlers installed.
431 00:27:14.941987 ARM64: Testing exception
432 00:27:14.946210 ARM64: Done test exception
433 00:27:14.949873 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
434 00:27:14.952934 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
435 00:27:14.968089 Probing TPM: . done!
436 00:27:14.968166 TPM ready after 0 ms
437 00:27:14.973375 Connected to device vid:did:rid of 1ae0:0028:00
438 00:27:14.980935 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
439 00:27:15.044251 Initialized TPM device CR50 revision 0
440 00:27:15.049887 tlcl_send_startup: Startup return code is 0
441 00:27:15.058523 TPM: setup succeeded
442 00:27:15.074006 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
443 00:27:15.081843 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
444 00:27:15.092366 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
445 00:27:15.102088 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
446 00:27:15.105145 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
447 00:27:15.108820 in-header: 03 07 00 00 08 00 00 00
448 00:27:15.112166 in-data: aa e4 47 04 13 02 00 00
449 00:27:15.115247 Chrome EC: UHEPI supported
450 00:27:15.122259 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
451 00:27:15.125372 in-header: 03 a9 00 00 08 00 00 00
452 00:27:15.128698 in-data: 84 60 60 08 00 00 00 00
453 00:27:15.128813 Phase 1
454 00:27:15.132122 FMAP: area GBB found @ 3f5000 (12032 bytes)
455 00:27:15.138701 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
456 00:27:15.145251 VB2:vb2_check_recovery() Recovery was requested manually
457 00:27:15.148742 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
458 00:27:15.151770 Recovery requested (1009000e)
459 00:27:15.159376 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 00:27:15.165057 tlcl_extend: response is 0
461 00:27:15.174991 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 00:27:15.178471 tlcl_extend: response is 0
463 00:27:15.185081 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 00:27:15.205506 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
465 00:27:15.212620 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 00:27:15.212697
467 00:27:15.212798
468 00:27:15.222383 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 00:27:15.225553 ARM64: Exception handlers installed.
470 00:27:15.228972 ARM64: Testing exception
471 00:27:15.229049 ARM64: Done test exception
472 00:27:15.251280 pmic_efuse_setting: Set efuses in 11 msecs
473 00:27:15.254839 pmwrap_interface_init: Select PMIF_VLD_RDY
474 00:27:15.261261 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 00:27:15.264822 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 00:27:15.271433 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 00:27:15.275060 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 00:27:15.281529 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 00:27:15.284670 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 00:27:15.287854 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 00:27:15.294776 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 00:27:15.297966 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 00:27:15.304668 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 00:27:15.308071 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 00:27:15.311491 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 00:27:15.318103 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 00:27:15.324920 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 00:27:15.328232 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 00:27:15.334791 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 00:27:15.341507 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 00:27:15.344871 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 00:27:15.351615 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 00:27:15.358260 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 00:27:15.361879 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 00:27:15.368469 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 00:27:15.374990 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 00:27:15.378528 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 00:27:15.385138 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 00:27:15.391768 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 00:27:15.394800 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 00:27:15.401990 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 00:27:15.404964 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 00:27:15.411404 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 00:27:15.414996 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 00:27:15.419306 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 00:27:15.426232 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 00:27:15.429565 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 00:27:15.436661 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 00:27:15.440596 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 00:27:15.447050 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 00:27:15.450529 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 00:27:15.453669 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 00:27:15.457385 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 00:27:15.464254 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 00:27:15.467922 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 00:27:15.471019 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 00:27:15.477691 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 00:27:15.481257 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 00:27:15.484495 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 00:27:15.487941 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 00:27:15.494556 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 00:27:15.497639 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 00:27:15.501180 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 00:27:15.507784 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 00:27:15.514250 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
526 00:27:15.520972 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 00:27:15.527793 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 00:27:15.534304 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 00:27:15.544151 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 00:27:15.547375 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 00:27:15.554526 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 00:27:15.557961 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 00:27:15.564516 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x27
534 00:27:15.570845 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 00:27:15.574316 [RTC]rtc_osc_init,62: osc32con val = 0xde70
536 00:27:15.577841 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 00:27:15.588606 [RTC]rtc_get_frequency_meter,154: input=15, output=772
538 00:27:15.597963 [RTC]rtc_get_frequency_meter,154: input=23, output=960
539 00:27:15.607468 [RTC]rtc_get_frequency_meter,154: input=19, output=864
540 00:27:15.617049 [RTC]rtc_get_frequency_meter,154: input=17, output=820
541 00:27:15.626565 [RTC]rtc_get_frequency_meter,154: input=16, output=796
542 00:27:15.629998 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
543 00:27:15.636663 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
544 00:27:15.639815 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
545 00:27:15.643132 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
546 00:27:15.646677 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
547 00:27:15.650042 ADC[4]: Raw value=903245 ID=7
548 00:27:15.653346 ADC[3]: Raw value=213179 ID=1
549 00:27:15.653423 RAM Code: 0x71
550 00:27:15.659932 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
551 00:27:15.663435 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
552 00:27:15.673183 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
553 00:27:15.679840 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
554 00:27:15.683387 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
555 00:27:15.686434 in-header: 03 07 00 00 08 00 00 00
556 00:27:15.690064 in-data: aa e4 47 04 13 02 00 00
557 00:27:15.693187 Chrome EC: UHEPI supported
558 00:27:15.699844 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
559 00:27:15.703502 in-header: 03 a9 00 00 08 00 00 00
560 00:27:15.706591 in-data: 84 60 60 08 00 00 00 00
561 00:27:15.710043 MRC: failed to locate region type 0.
562 00:27:15.716576 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
563 00:27:15.716678 DRAM-K: Running full calibration
564 00:27:15.723700 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
565 00:27:15.726912 header.status = 0x0
566 00:27:15.730370 header.version = 0x6 (expected: 0x6)
567 00:27:15.733397 header.size = 0xd00 (expected: 0xd00)
568 00:27:15.733474 header.flags = 0x0
569 00:27:15.739908 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
570 00:27:15.758410 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
571 00:27:15.765540 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
572 00:27:15.768593 dram_init: ddr_geometry: 2
573 00:27:15.772011 [EMI] MDL number = 2
574 00:27:15.772089 [EMI] Get MDL freq = 0
575 00:27:15.775493 dram_init: ddr_type: 0
576 00:27:15.775570 is_discrete_lpddr4: 1
577 00:27:15.778816 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
578 00:27:15.778892
579 00:27:15.778953
580 00:27:15.782182 [Bian_co] ETT version 0.0.0.1
581 00:27:15.788818 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
582 00:27:15.788896
583 00:27:15.792101 dramc_set_vcore_voltage set vcore to 650000
584 00:27:15.792177 Read voltage for 800, 4
585 00:27:15.795313 Vio18 = 0
586 00:27:15.795414 Vcore = 650000
587 00:27:15.795502 Vdram = 0
588 00:27:15.799014 Vddq = 0
589 00:27:15.799091 Vmddr = 0
590 00:27:15.802141 dram_init: config_dvfs: 1
591 00:27:15.805742 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
592 00:27:15.812023 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
593 00:27:15.815512 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
594 00:27:15.818726 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
595 00:27:15.822157 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
596 00:27:15.825760 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
597 00:27:15.828650 MEM_TYPE=3, freq_sel=18
598 00:27:15.832311 sv_algorithm_assistance_LP4_1600
599 00:27:15.835421 ============ PULL DRAM RESETB DOWN ============
600 00:27:15.839105 ========== PULL DRAM RESETB DOWN end =========
601 00:27:15.845775 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
602 00:27:15.849036 ===================================
603 00:27:15.849142 LPDDR4 DRAM CONFIGURATION
604 00:27:15.852121 ===================================
605 00:27:15.855570 EX_ROW_EN[0] = 0x0
606 00:27:15.859273 EX_ROW_EN[1] = 0x0
607 00:27:15.859368 LP4Y_EN = 0x0
608 00:27:15.862413 WORK_FSP = 0x0
609 00:27:15.862507 WL = 0x2
610 00:27:15.866072 RL = 0x2
611 00:27:15.866142 BL = 0x2
612 00:27:15.869160 RPST = 0x0
613 00:27:15.869255 RD_PRE = 0x0
614 00:27:15.872515 WR_PRE = 0x1
615 00:27:15.872595 WR_PST = 0x0
616 00:27:15.875788 DBI_WR = 0x0
617 00:27:15.875857 DBI_RD = 0x0
618 00:27:15.878912 OTF = 0x1
619 00:27:15.882246 ===================================
620 00:27:15.885828 ===================================
621 00:27:15.885923 ANA top config
622 00:27:15.889204 ===================================
623 00:27:15.892309 DLL_ASYNC_EN = 0
624 00:27:15.895586 ALL_SLAVE_EN = 1
625 00:27:15.895664 NEW_RANK_MODE = 1
626 00:27:15.899193 DLL_IDLE_MODE = 1
627 00:27:15.902530 LP45_APHY_COMB_EN = 1
628 00:27:15.905554 TX_ODT_DIS = 1
629 00:27:15.908977 NEW_8X_MODE = 1
630 00:27:15.912746 ===================================
631 00:27:15.912835 ===================================
632 00:27:15.915844 data_rate = 1600
633 00:27:15.919181 CKR = 1
634 00:27:15.922255 DQ_P2S_RATIO = 8
635 00:27:15.925828 ===================================
636 00:27:15.929246 CA_P2S_RATIO = 8
637 00:27:15.932830 DQ_CA_OPEN = 0
638 00:27:15.935778 DQ_SEMI_OPEN = 0
639 00:27:15.935871 CA_SEMI_OPEN = 0
640 00:27:15.939288 CA_FULL_RATE = 0
641 00:27:15.942334 DQ_CKDIV4_EN = 1
642 00:27:15.945788 CA_CKDIV4_EN = 1
643 00:27:15.949316 CA_PREDIV_EN = 0
644 00:27:15.949381 PH8_DLY = 0
645 00:27:15.952350 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
646 00:27:15.955769 DQ_AAMCK_DIV = 4
647 00:27:15.959023 CA_AAMCK_DIV = 4
648 00:27:15.962616 CA_ADMCK_DIV = 4
649 00:27:15.965892 DQ_TRACK_CA_EN = 0
650 00:27:15.965986 CA_PICK = 800
651 00:27:15.969434 CA_MCKIO = 800
652 00:27:15.972591 MCKIO_SEMI = 0
653 00:27:15.975988 PLL_FREQ = 3068
654 00:27:15.979626 DQ_UI_PI_RATIO = 32
655 00:27:15.982496 CA_UI_PI_RATIO = 0
656 00:27:15.986201 ===================================
657 00:27:15.989252 ===================================
658 00:27:15.989344 memory_type:LPDDR4
659 00:27:15.992736 GP_NUM : 10
660 00:27:15.996140 SRAM_EN : 1
661 00:27:15.996230 MD32_EN : 0
662 00:27:15.999274 ===================================
663 00:27:16.002640 [ANA_INIT] >>>>>>>>>>>>>>
664 00:27:16.006096 <<<<<< [CONFIGURE PHASE]: ANA_TX
665 00:27:16.009467 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
666 00:27:16.012844 ===================================
667 00:27:16.015944 data_rate = 1600,PCW = 0X7600
668 00:27:16.020142 ===================================
669 00:27:16.022854 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
670 00:27:16.026474 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
671 00:27:16.033013 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
672 00:27:16.036539 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
673 00:27:16.039560 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
674 00:27:16.043058 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
675 00:27:16.046173 [ANA_INIT] flow start
676 00:27:16.049665 [ANA_INIT] PLL >>>>>>>>
677 00:27:16.049753 [ANA_INIT] PLL <<<<<<<<
678 00:27:16.053287 [ANA_INIT] MIDPI >>>>>>>>
679 00:27:16.056245 [ANA_INIT] MIDPI <<<<<<<<
680 00:27:16.056337 [ANA_INIT] DLL >>>>>>>>
681 00:27:16.059819 [ANA_INIT] flow end
682 00:27:16.062922 ============ LP4 DIFF to SE enter ============
683 00:27:16.066305 ============ LP4 DIFF to SE exit ============
684 00:27:16.069780 [ANA_INIT] <<<<<<<<<<<<<
685 00:27:16.072835 [Flow] Enable top DCM control >>>>>
686 00:27:16.076615 [Flow] Enable top DCM control <<<<<
687 00:27:16.079679 Enable DLL master slave shuffle
688 00:27:16.086202 ==============================================================
689 00:27:16.086271 Gating Mode config
690 00:27:16.092943 ==============================================================
691 00:27:16.093013 Config description:
692 00:27:16.104275 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
693 00:27:16.112279 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
694 00:27:16.115913 SELPH_MODE 0: By rank 1: By Phase
695 00:27:16.119576 ==============================================================
696 00:27:16.122959 GAT_TRACK_EN = 1
697 00:27:16.127147 RX_GATING_MODE = 2
698 00:27:16.130617 RX_GATING_TRACK_MODE = 2
699 00:27:16.134021 SELPH_MODE = 1
700 00:27:16.137250 PICG_EARLY_EN = 1
701 00:27:16.140670 VALID_LAT_VALUE = 1
702 00:27:16.143702 ==============================================================
703 00:27:16.147234 Enter into Gating configuration >>>>
704 00:27:16.150985 Exit from Gating configuration <<<<
705 00:27:16.153932 Enter into DVFS_PRE_config >>>>>
706 00:27:16.163899 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
707 00:27:16.167525 Exit from DVFS_PRE_config <<<<<
708 00:27:16.170994 Enter into PICG configuration >>>>
709 00:27:16.174098 Exit from PICG configuration <<<<
710 00:27:16.177188 [RX_INPUT] configuration >>>>>
711 00:27:16.180744 [RX_INPUT] configuration <<<<<
712 00:27:16.184363 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
713 00:27:16.190744 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
714 00:27:16.197600 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
715 00:27:16.204186 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
716 00:27:16.210636 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
717 00:27:16.217466 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
718 00:27:16.220433 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
719 00:27:16.223909 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
720 00:27:16.227506 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
721 00:27:16.230640 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
722 00:27:16.237605 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
723 00:27:16.240906 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
724 00:27:16.244052 ===================================
725 00:27:16.247525 LPDDR4 DRAM CONFIGURATION
726 00:27:16.251015 ===================================
727 00:27:16.251092 EX_ROW_EN[0] = 0x0
728 00:27:16.254349 EX_ROW_EN[1] = 0x0
729 00:27:16.254425 LP4Y_EN = 0x0
730 00:27:16.257827 WORK_FSP = 0x0
731 00:27:16.257904 WL = 0x2
732 00:27:16.261134 RL = 0x2
733 00:27:16.261211 BL = 0x2
734 00:27:16.264815 RPST = 0x0
735 00:27:16.264892 RD_PRE = 0x0
736 00:27:16.267252 WR_PRE = 0x1
737 00:27:16.267352 WR_PST = 0x0
738 00:27:16.270686 DBI_WR = 0x0
739 00:27:16.270762 DBI_RD = 0x0
740 00:27:16.274389 OTF = 0x1
741 00:27:16.277369 ===================================
742 00:27:16.280815 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
743 00:27:16.283956 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
744 00:27:16.290980 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
745 00:27:16.293977 ===================================
746 00:27:16.294054 LPDDR4 DRAM CONFIGURATION
747 00:27:16.297593 ===================================
748 00:27:16.301114 EX_ROW_EN[0] = 0x10
749 00:27:16.304509 EX_ROW_EN[1] = 0x0
750 00:27:16.304586 LP4Y_EN = 0x0
751 00:27:16.307691 WORK_FSP = 0x0
752 00:27:16.307767 WL = 0x2
753 00:27:16.310868 RL = 0x2
754 00:27:16.310944 BL = 0x2
755 00:27:16.314610 RPST = 0x0
756 00:27:16.314686 RD_PRE = 0x0
757 00:27:16.317526 WR_PRE = 0x1
758 00:27:16.317603 WR_PST = 0x0
759 00:27:16.320905 DBI_WR = 0x0
760 00:27:16.320984 DBI_RD = 0x0
761 00:27:16.324504 OTF = 0x1
762 00:27:16.327521 ===================================
763 00:27:16.334563 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
764 00:27:16.337619 nWR fixed to 40
765 00:27:16.337697 [ModeRegInit_LP4] CH0 RK0
766 00:27:16.340893 [ModeRegInit_LP4] CH0 RK1
767 00:27:16.344292 [ModeRegInit_LP4] CH1 RK0
768 00:27:16.347749 [ModeRegInit_LP4] CH1 RK1
769 00:27:16.347826 match AC timing 13
770 00:27:16.351175 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
771 00:27:16.357763 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
772 00:27:16.360966 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
773 00:27:16.364635 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
774 00:27:16.371265 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
775 00:27:16.371357 [EMI DOE] emi_dcm 0
776 00:27:16.377527 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
777 00:27:16.377620 ==
778 00:27:16.381085 Dram Type= 6, Freq= 0, CH_0, rank 0
779 00:27:16.384492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
780 00:27:16.384584 ==
781 00:27:16.387834 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
782 00:27:16.394362 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
783 00:27:16.404828 [CA 0] Center 37 (7~68) winsize 62
784 00:27:16.407760 [CA 1] Center 38 (7~69) winsize 63
785 00:27:16.411253 [CA 2] Center 35 (5~66) winsize 62
786 00:27:16.414685 [CA 3] Center 35 (5~66) winsize 62
787 00:27:16.418396 [CA 4] Center 34 (4~65) winsize 62
788 00:27:16.421890 [CA 5] Center 33 (3~64) winsize 62
789 00:27:16.421969
790 00:27:16.425461 [CmdBusTrainingLP45] Vref(ca) range 1: 30
791 00:27:16.425538
792 00:27:16.428330 [CATrainingPosCal] consider 1 rank data
793 00:27:16.432025 u2DelayCellTimex100 = 270/100 ps
794 00:27:16.435419 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
795 00:27:16.438521 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
796 00:27:16.442227 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
797 00:27:16.445309 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
798 00:27:16.451793 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
799 00:27:16.455402 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
800 00:27:16.455479
801 00:27:16.458547 CA PerBit enable=1, Macro0, CA PI delay=33
802 00:27:16.458624
803 00:27:16.461889 [CBTSetCACLKResult] CA Dly = 33
804 00:27:16.461966 CS Dly: 5 (0~36)
805 00:27:16.462026 ==
806 00:27:16.465588 Dram Type= 6, Freq= 0, CH_0, rank 1
807 00:27:16.468976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
808 00:27:16.472198 ==
809 00:27:16.475347 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
810 00:27:16.481902 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
811 00:27:16.490929 [CA 0] Center 38 (7~69) winsize 63
812 00:27:16.494480 [CA 1] Center 38 (7~69) winsize 63
813 00:27:16.497907 [CA 2] Center 36 (6~67) winsize 62
814 00:27:16.500898 [CA 3] Center 35 (5~66) winsize 62
815 00:27:16.504112 [CA 4] Center 35 (4~66) winsize 63
816 00:27:16.507603 [CA 5] Center 34 (4~65) winsize 62
817 00:27:16.507681
818 00:27:16.510815 [CmdBusTrainingLP45] Vref(ca) range 1: 34
819 00:27:16.510892
820 00:27:16.514255 [CATrainingPosCal] consider 2 rank data
821 00:27:16.517826 u2DelayCellTimex100 = 270/100 ps
822 00:27:16.520823 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
823 00:27:16.524089 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
824 00:27:16.531205 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
825 00:27:16.534335 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
826 00:27:16.537781 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
827 00:27:16.540903 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
828 00:27:16.540980
829 00:27:16.544464 CA PerBit enable=1, Macro0, CA PI delay=34
830 00:27:16.544541
831 00:27:16.547501 [CBTSetCACLKResult] CA Dly = 34
832 00:27:16.547578 CS Dly: 6 (0~38)
833 00:27:16.547639
834 00:27:16.551063 ----->DramcWriteLeveling(PI) begin...
835 00:27:16.554562 ==
836 00:27:16.554648 Dram Type= 6, Freq= 0, CH_0, rank 0
837 00:27:16.561132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
838 00:27:16.561211 ==
839 00:27:16.564624 Write leveling (Byte 0): 33 => 33
840 00:27:16.567825 Write leveling (Byte 1): 32 => 32
841 00:27:16.567902 DramcWriteLeveling(PI) end<-----
842 00:27:16.571167
843 00:27:16.571244 ==
844 00:27:16.574560 Dram Type= 6, Freq= 0, CH_0, rank 0
845 00:27:16.577750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
846 00:27:16.577835 ==
847 00:27:16.581340 [Gating] SW mode calibration
848 00:27:16.588073 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
849 00:27:16.591655 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
850 00:27:16.597669 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
851 00:27:16.601293 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
852 00:27:16.604189 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
853 00:27:16.611169 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 00:27:16.614562 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 00:27:16.617726 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 00:27:16.624851 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 00:27:16.627853 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 00:27:16.631157 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 00:27:16.637772 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 00:27:16.641320 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 00:27:16.644923 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 00:27:16.647976 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 00:27:16.654500 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 00:27:16.658140 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 00:27:16.661176 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 00:27:16.667893 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
867 00:27:16.671392 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
868 00:27:16.674556 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 00:27:16.682443 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 00:27:16.685601 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 00:27:16.688956 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 00:27:16.692308 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 00:27:16.699020 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 00:27:16.702636 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 00:27:16.706210 0 9 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
876 00:27:16.712782 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
877 00:27:16.716037 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
878 00:27:16.719606 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
879 00:27:16.726191 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
880 00:27:16.729920 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
881 00:27:16.732861 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 00:27:16.736410 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 00:27:16.743081 0 10 4 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 0)
884 00:27:16.746327 0 10 8 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
885 00:27:16.749671 0 10 12 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
886 00:27:16.756500 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
887 00:27:16.759742 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
888 00:27:16.763177 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 00:27:16.769919 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 00:27:16.773407 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 00:27:16.776512 0 11 4 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
892 00:27:16.783135 0 11 8 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
893 00:27:16.786709 0 11 12 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
894 00:27:16.790469 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
895 00:27:16.796987 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
896 00:27:16.799722 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
897 00:27:16.803043 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 00:27:16.806340 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 00:27:16.813233 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
900 00:27:16.816882 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
901 00:27:16.819755 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 00:27:16.826534 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 00:27:16.829587 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 00:27:16.833309 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 00:27:16.839916 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 00:27:16.843272 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 00:27:16.846645 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 00:27:16.853482 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 00:27:16.856575 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 00:27:16.859990 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 00:27:16.866596 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 00:27:16.870088 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 00:27:16.873299 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 00:27:16.880400 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 00:27:16.883339 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
916 00:27:16.887166 Total UI for P1: 0, mck2ui 16
917 00:27:16.890203 best dqsien dly found for B0: ( 0, 14, 2)
918 00:27:16.893725 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
919 00:27:16.896842 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
920 00:27:16.900319 Total UI for P1: 0, mck2ui 16
921 00:27:16.903777 best dqsien dly found for B1: ( 0, 14, 6)
922 00:27:16.907073 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
923 00:27:16.910373 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
924 00:27:16.910823
925 00:27:16.917177 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
926 00:27:16.920152 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
927 00:27:16.920616 [Gating] SW calibration Done
928 00:27:16.923378 ==
929 00:27:16.926980 Dram Type= 6, Freq= 0, CH_0, rank 0
930 00:27:16.930422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
931 00:27:16.931048 ==
932 00:27:16.931455 RX Vref Scan: 0
933 00:27:16.931947
934 00:27:16.933716 RX Vref 0 -> 0, step: 1
935 00:27:16.934421
936 00:27:16.937101 RX Delay -130 -> 252, step: 16
937 00:27:16.940385 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
938 00:27:16.943939 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
939 00:27:16.947403 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
940 00:27:16.953978 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
941 00:27:16.956975 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
942 00:27:16.960452 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
943 00:27:16.964068 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
944 00:27:16.967207 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
945 00:27:16.973974 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
946 00:27:16.977022 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
947 00:27:16.980553 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
948 00:27:16.983736 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
949 00:27:16.987322 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
950 00:27:16.993793 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
951 00:27:16.997060 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
952 00:27:17.000170 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
953 00:27:17.000262 ==
954 00:27:17.003295 Dram Type= 6, Freq= 0, CH_0, rank 0
955 00:27:17.006860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
956 00:27:17.006933 ==
957 00:27:17.009987 DQS Delay:
958 00:27:17.010052 DQS0 = 0, DQS1 = 0
959 00:27:17.013248 DQM Delay:
960 00:27:17.013319 DQM0 = 89, DQM1 = 78
961 00:27:17.013377 DQ Delay:
962 00:27:17.016603 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
963 00:27:17.020370 DQ4 =85, DQ5 =77, DQ6 =101, DQ7 =101
964 00:27:17.023657 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =77
965 00:27:17.026770 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =85
966 00:27:17.026861
967 00:27:17.026944
968 00:27:17.030194 ==
969 00:27:17.033367 Dram Type= 6, Freq= 0, CH_0, rank 0
970 00:27:17.037060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
971 00:27:17.037130 ==
972 00:27:17.037188
973 00:27:17.037248
974 00:27:17.040367 TX Vref Scan disable
975 00:27:17.040435 == TX Byte 0 ==
976 00:27:17.043912 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
977 00:27:17.050294 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
978 00:27:17.050371 == TX Byte 1 ==
979 00:27:17.053284 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
980 00:27:17.060196 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
981 00:27:17.060266 ==
982 00:27:17.063696 Dram Type= 6, Freq= 0, CH_0, rank 0
983 00:27:17.066745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
984 00:27:17.066810 ==
985 00:27:17.080204 TX Vref=22, minBit 6, minWin=27, winSum=441
986 00:27:17.083325 TX Vref=24, minBit 6, minWin=27, winSum=441
987 00:27:17.086611 TX Vref=26, minBit 8, minWin=27, winSum=449
988 00:27:17.090084 TX Vref=28, minBit 8, minWin=27, winSum=451
989 00:27:17.093367 TX Vref=30, minBit 8, minWin=27, winSum=457
990 00:27:17.096757 TX Vref=32, minBit 5, minWin=28, winSum=459
991 00:27:17.103317 [TxChooseVref] Worse bit 5, Min win 28, Win sum 459, Final Vref 32
992 00:27:17.103385
993 00:27:17.106859 Final TX Range 1 Vref 32
994 00:27:17.106928
995 00:27:17.106984 ==
996 00:27:17.109868 Dram Type= 6, Freq= 0, CH_0, rank 0
997 00:27:17.113342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
998 00:27:17.113415 ==
999 00:27:17.113470
1000 00:27:17.116339
1001 00:27:17.116398 TX Vref Scan disable
1002 00:27:17.119967 == TX Byte 0 ==
1003 00:27:17.123265 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1004 00:27:17.129965 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1005 00:27:17.130041 == TX Byte 1 ==
1006 00:27:17.133348 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1007 00:27:17.139788 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1008 00:27:17.139865
1009 00:27:17.139926 [DATLAT]
1010 00:27:17.139980 Freq=800, CH0 RK0
1011 00:27:17.140037
1012 00:27:17.143379 DATLAT Default: 0xa
1013 00:27:17.143442 0, 0xFFFF, sum = 0
1014 00:27:17.146863 1, 0xFFFF, sum = 0
1015 00:27:17.146951 2, 0xFFFF, sum = 0
1016 00:27:17.149805 3, 0xFFFF, sum = 0
1017 00:27:17.149867 4, 0xFFFF, sum = 0
1018 00:27:17.153117 5, 0xFFFF, sum = 0
1019 00:27:17.153185 6, 0xFFFF, sum = 0
1020 00:27:17.156660 7, 0xFFFF, sum = 0
1021 00:27:17.159962 8, 0xFFFF, sum = 0
1022 00:27:17.160057 9, 0x0, sum = 1
1023 00:27:17.160142 10, 0x0, sum = 2
1024 00:27:17.163473 11, 0x0, sum = 3
1025 00:27:17.163537 12, 0x0, sum = 4
1026 00:27:17.166591 best_step = 10
1027 00:27:17.166656
1028 00:27:17.166716 ==
1029 00:27:17.170136 Dram Type= 6, Freq= 0, CH_0, rank 0
1030 00:27:17.173480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1031 00:27:17.173553 ==
1032 00:27:17.176701 RX Vref Scan: 1
1033 00:27:17.176837
1034 00:27:17.176922 Set Vref Range= 32 -> 127
1035 00:27:17.177002
1036 00:27:17.180296 RX Vref 32 -> 127, step: 1
1037 00:27:17.180362
1038 00:27:17.183281 RX Delay -95 -> 252, step: 8
1039 00:27:17.183346
1040 00:27:17.186749 Set Vref, RX VrefLevel [Byte0]: 32
1041 00:27:17.190064 [Byte1]: 32
1042 00:27:17.190135
1043 00:27:17.193217 Set Vref, RX VrefLevel [Byte0]: 33
1044 00:27:17.196904 [Byte1]: 33
1045 00:27:17.200223
1046 00:27:17.200290 Set Vref, RX VrefLevel [Byte0]: 34
1047 00:27:17.203791 [Byte1]: 34
1048 00:27:17.208014
1049 00:27:17.208082 Set Vref, RX VrefLevel [Byte0]: 35
1050 00:27:17.211149 [Byte1]: 35
1051 00:27:17.215675
1052 00:27:17.215741 Set Vref, RX VrefLevel [Byte0]: 36
1053 00:27:17.218889 [Byte1]: 36
1054 00:27:17.222848
1055 00:27:17.222917 Set Vref, RX VrefLevel [Byte0]: 37
1056 00:27:17.226466 [Byte1]: 37
1057 00:27:17.230591
1058 00:27:17.230659 Set Vref, RX VrefLevel [Byte0]: 38
1059 00:27:17.233846 [Byte1]: 38
1060 00:27:17.238027
1061 00:27:17.238089 Set Vref, RX VrefLevel [Byte0]: 39
1062 00:27:17.241552 [Byte1]: 39
1063 00:27:17.245744
1064 00:27:17.245818 Set Vref, RX VrefLevel [Byte0]: 40
1065 00:27:17.248873 [Byte1]: 40
1066 00:27:17.253460
1067 00:27:17.253525 Set Vref, RX VrefLevel [Byte0]: 41
1068 00:27:17.256803 [Byte1]: 41
1069 00:27:17.260948
1070 00:27:17.261019 Set Vref, RX VrefLevel [Byte0]: 42
1071 00:27:17.264260 [Byte1]: 42
1072 00:27:17.268461
1073 00:27:17.268541 Set Vref, RX VrefLevel [Byte0]: 43
1074 00:27:17.271921 [Byte1]: 43
1075 00:27:17.275926
1076 00:27:17.275991 Set Vref, RX VrefLevel [Byte0]: 44
1077 00:27:17.279731 [Byte1]: 44
1078 00:27:17.283904
1079 00:27:17.283999 Set Vref, RX VrefLevel [Byte0]: 45
1080 00:27:17.287234 [Byte1]: 45
1081 00:27:17.291449
1082 00:27:17.291516 Set Vref, RX VrefLevel [Byte0]: 46
1083 00:27:17.294640 [Byte1]: 46
1084 00:27:17.299179
1085 00:27:17.299243 Set Vref, RX VrefLevel [Byte0]: 47
1086 00:27:17.302277 [Byte1]: 47
1087 00:27:17.306555
1088 00:27:17.306624 Set Vref, RX VrefLevel [Byte0]: 48
1089 00:27:17.310020 [Byte1]: 48
1090 00:27:17.314044
1091 00:27:17.314110 Set Vref, RX VrefLevel [Byte0]: 49
1092 00:27:17.317577 [Byte1]: 49
1093 00:27:17.322091
1094 00:27:17.322229 Set Vref, RX VrefLevel [Byte0]: 50
1095 00:27:17.328168 [Byte1]: 50
1096 00:27:17.328238
1097 00:27:17.331660 Set Vref, RX VrefLevel [Byte0]: 51
1098 00:27:17.335148 [Byte1]: 51
1099 00:27:17.335218
1100 00:27:17.338479 Set Vref, RX VrefLevel [Byte0]: 52
1101 00:27:17.341885 [Byte1]: 52
1102 00:27:17.341956
1103 00:27:17.345074 Set Vref, RX VrefLevel [Byte0]: 53
1104 00:27:17.348090 [Byte1]: 53
1105 00:27:17.352041
1106 00:27:17.352107 Set Vref, RX VrefLevel [Byte0]: 54
1107 00:27:17.355615 [Byte1]: 54
1108 00:27:17.359920
1109 00:27:17.359988 Set Vref, RX VrefLevel [Byte0]: 55
1110 00:27:17.363336 [Byte1]: 55
1111 00:27:17.367232
1112 00:27:17.367297 Set Vref, RX VrefLevel [Byte0]: 56
1113 00:27:17.370469 [Byte1]: 56
1114 00:27:17.375082
1115 00:27:17.375151 Set Vref, RX VrefLevel [Byte0]: 57
1116 00:27:17.378067 [Byte1]: 57
1117 00:27:17.382477
1118 00:27:17.382542 Set Vref, RX VrefLevel [Byte0]: 58
1119 00:27:17.385915 [Byte1]: 58
1120 00:27:17.390208
1121 00:27:17.390272 Set Vref, RX VrefLevel [Byte0]: 59
1122 00:27:17.393323 [Byte1]: 59
1123 00:27:17.397931
1124 00:27:17.398001 Set Vref, RX VrefLevel [Byte0]: 60
1125 00:27:17.400846 [Byte1]: 60
1126 00:27:17.405314
1127 00:27:17.405377 Set Vref, RX VrefLevel [Byte0]: 61
1128 00:27:17.408501 [Byte1]: 61
1129 00:27:17.413054
1130 00:27:17.413141 Set Vref, RX VrefLevel [Byte0]: 62
1131 00:27:17.416015 [Byte1]: 62
1132 00:27:17.420769
1133 00:27:17.420839 Set Vref, RX VrefLevel [Byte0]: 63
1134 00:27:17.423831 [Byte1]: 63
1135 00:27:17.428072
1136 00:27:17.428135 Set Vref, RX VrefLevel [Byte0]: 64
1137 00:27:17.431539 [Byte1]: 64
1138 00:27:17.436043
1139 00:27:17.436117 Set Vref, RX VrefLevel [Byte0]: 65
1140 00:27:17.438800 [Byte1]: 65
1141 00:27:17.443554
1142 00:27:17.443627 Set Vref, RX VrefLevel [Byte0]: 66
1143 00:27:17.446576 [Byte1]: 66
1144 00:27:17.450880
1145 00:27:17.450957 Set Vref, RX VrefLevel [Byte0]: 67
1146 00:27:17.454237 [Byte1]: 67
1147 00:27:17.458235
1148 00:27:17.458378 Set Vref, RX VrefLevel [Byte0]: 68
1149 00:27:17.461699 [Byte1]: 68
1150 00:27:17.466312
1151 00:27:17.466383 Set Vref, RX VrefLevel [Byte0]: 69
1152 00:27:17.469292 [Byte1]: 69
1153 00:27:17.473562
1154 00:27:17.473629 Set Vref, RX VrefLevel [Byte0]: 70
1155 00:27:17.476953 [Byte1]: 70
1156 00:27:17.481475
1157 00:27:17.481548 Set Vref, RX VrefLevel [Byte0]: 71
1158 00:27:17.484699 [Byte1]: 71
1159 00:27:17.488915
1160 00:27:17.488987 Set Vref, RX VrefLevel [Byte0]: 72
1161 00:27:17.492323 [Byte1]: 72
1162 00:27:17.496638
1163 00:27:17.496772 Set Vref, RX VrefLevel [Byte0]: 73
1164 00:27:17.499804 [Byte1]: 73
1165 00:27:17.504339
1166 00:27:17.504407 Set Vref, RX VrefLevel [Byte0]: 74
1167 00:27:17.507393 [Byte1]: 74
1168 00:27:17.511538
1169 00:27:17.511627 Set Vref, RX VrefLevel [Byte0]: 75
1170 00:27:17.514899 [Byte1]: 75
1171 00:27:17.519091
1172 00:27:17.519162 Set Vref, RX VrefLevel [Byte0]: 76
1173 00:27:17.523012 [Byte1]: 76
1174 00:27:17.527047
1175 00:27:17.527113 Final RX Vref Byte 0 = 62 to rank0
1176 00:27:17.530205 Final RX Vref Byte 1 = 56 to rank0
1177 00:27:17.533760 Final RX Vref Byte 0 = 62 to rank1
1178 00:27:17.536862 Final RX Vref Byte 1 = 56 to rank1==
1179 00:27:17.540318 Dram Type= 6, Freq= 0, CH_0, rank 0
1180 00:27:17.543747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1181 00:27:17.547566 ==
1182 00:27:17.547635 DQS Delay:
1183 00:27:17.547697 DQS0 = 0, DQS1 = 0
1184 00:27:17.550620 DQM Delay:
1185 00:27:17.550687 DQM0 = 93, DQM1 = 82
1186 00:27:17.553898 DQ Delay:
1187 00:27:17.553962 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1188 00:27:17.557133 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1189 00:27:17.560611 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =76
1190 00:27:17.564109 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =88
1191 00:27:17.567267
1192 00:27:17.567333
1193 00:27:17.574197 [DQSOSCAuto] RK0, (LSB)MR18= 0x3e3a, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
1194 00:27:17.577300 CH0 RK0: MR19=606, MR18=3E3A
1195 00:27:17.584313 CH0_RK0: MR19=0x606, MR18=0x3E3A, DQSOSC=394, MR23=63, INC=95, DEC=63
1196 00:27:17.584382
1197 00:27:17.587152 ----->DramcWriteLeveling(PI) begin...
1198 00:27:17.587230 ==
1199 00:27:17.590663 Dram Type= 6, Freq= 0, CH_0, rank 1
1200 00:27:17.594389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1201 00:27:17.594456 ==
1202 00:27:17.597207 Write leveling (Byte 0): 33 => 33
1203 00:27:17.600821 Write leveling (Byte 1): 28 => 28
1204 00:27:17.604012 DramcWriteLeveling(PI) end<-----
1205 00:27:17.604086
1206 00:27:17.604163 ==
1207 00:27:17.607497 Dram Type= 6, Freq= 0, CH_0, rank 1
1208 00:27:17.610934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1209 00:27:17.611007 ==
1210 00:27:17.613908 [Gating] SW mode calibration
1211 00:27:17.621009 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1212 00:27:17.627767 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1213 00:27:17.630886 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1214 00:27:17.634030 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1215 00:27:17.640694 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1216 00:27:17.684956 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 00:27:17.685549 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 00:27:17.685617 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 00:27:17.685867 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 00:27:17.685981 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 00:27:17.686255 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 00:27:17.686353 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 00:27:17.686436 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 00:27:17.686537 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 00:27:17.686639 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 00:27:17.695575 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 00:27:17.695707 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 00:27:17.698993 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 00:27:17.702015 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 00:27:17.705627 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1231 00:27:17.708777 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 00:27:17.715503 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 00:27:17.718796 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 00:27:17.721996 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 00:27:17.725455 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 00:27:17.731912 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 00:27:17.735595 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 00:27:17.738650 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 00:27:17.745720 0 9 8 | B1->B0 | 2e2e 3434 | 1 0 | (0 0) (0 0)
1240 00:27:17.748851 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1241 00:27:17.752298 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1242 00:27:17.758696 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1243 00:27:17.762345 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1244 00:27:17.765943 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1245 00:27:17.772591 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1246 00:27:17.775786 0 10 4 | B1->B0 | 3434 2f2f | 0 1 | (0 0) (1 0)
1247 00:27:17.778848 0 10 8 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
1248 00:27:17.785885 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 00:27:17.788857 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 00:27:17.792435 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 00:27:17.796097 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 00:27:17.802234 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 00:27:17.806208 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 00:27:17.809161 0 11 4 | B1->B0 | 2727 3333 | 0 0 | (0 0) (0 0)
1255 00:27:17.815835 0 11 8 | B1->B0 | 3a3a 4646 | 0 0 | (1 1) (0 0)
1256 00:27:17.819471 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1257 00:27:17.822333 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1258 00:27:17.829317 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1259 00:27:17.832860 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1260 00:27:17.836013 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1261 00:27:17.842647 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1262 00:27:17.845842 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1263 00:27:17.849256 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1264 00:27:17.856222 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1265 00:27:17.859254 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 00:27:17.862658 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 00:27:17.866227 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 00:27:17.872745 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 00:27:17.876168 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 00:27:17.879582 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 00:27:17.886141 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 00:27:17.889827 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 00:27:17.892850 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 00:27:17.899532 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 00:27:17.902907 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 00:27:17.906348 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 00:27:17.912755 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 00:27:17.916215 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1279 00:27:17.919767 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1280 00:27:17.926381 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1281 00:27:17.926457 Total UI for P1: 0, mck2ui 16
1282 00:27:17.929505 best dqsien dly found for B0: ( 0, 14, 6)
1283 00:27:17.932983 Total UI for P1: 0, mck2ui 16
1284 00:27:17.936466 best dqsien dly found for B1: ( 0, 14, 6)
1285 00:27:17.939917 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1286 00:27:17.942928 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1287 00:27:17.946569
1288 00:27:17.949809 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1289 00:27:17.953050 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1290 00:27:17.956398 [Gating] SW calibration Done
1291 00:27:17.956487 ==
1292 00:27:17.959642 Dram Type= 6, Freq= 0, CH_0, rank 1
1293 00:27:17.963167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1294 00:27:17.963236 ==
1295 00:27:17.963295 RX Vref Scan: 0
1296 00:27:17.963348
1297 00:27:17.966708 RX Vref 0 -> 0, step: 1
1298 00:27:17.966773
1299 00:27:17.969841 RX Delay -130 -> 252, step: 16
1300 00:27:17.973437 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1301 00:27:17.976306 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1302 00:27:17.983326 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1303 00:27:17.986280 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1304 00:27:17.989664 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1305 00:27:17.993514 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1306 00:27:17.996537 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1307 00:27:18.003128 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1308 00:27:18.006665 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1309 00:27:18.010138 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
1310 00:27:18.013232 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1311 00:27:18.016688 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1312 00:27:18.023347 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1313 00:27:18.027024 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
1314 00:27:18.029996 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1315 00:27:18.033550 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
1316 00:27:18.033614 ==
1317 00:27:18.036670 Dram Type= 6, Freq= 0, CH_0, rank 1
1318 00:27:18.039962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1319 00:27:18.043751 ==
1320 00:27:18.043817 DQS Delay:
1321 00:27:18.043877 DQS0 = 0, DQS1 = 0
1322 00:27:18.046633 DQM Delay:
1323 00:27:18.046701 DQM0 = 89, DQM1 = 80
1324 00:27:18.050259 DQ Delay:
1325 00:27:18.050322 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =77
1326 00:27:18.053782 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
1327 00:27:18.056685 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
1328 00:27:18.060039 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
1329 00:27:18.060113
1330 00:27:18.063430
1331 00:27:18.063498 ==
1332 00:27:18.066857 Dram Type= 6, Freq= 0, CH_0, rank 1
1333 00:27:18.070228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1334 00:27:18.070296 ==
1335 00:27:18.070352
1336 00:27:18.070406
1337 00:27:18.073447 TX Vref Scan disable
1338 00:27:18.073512 == TX Byte 0 ==
1339 00:27:18.080667 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1340 00:27:18.083434 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1341 00:27:18.083507 == TX Byte 1 ==
1342 00:27:18.090549 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1343 00:27:18.093525 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1344 00:27:18.093597 ==
1345 00:27:18.096846 Dram Type= 6, Freq= 0, CH_0, rank 1
1346 00:27:18.100157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1347 00:27:18.100266 ==
1348 00:27:18.114363 TX Vref=22, minBit 11, minWin=26, winSum=444
1349 00:27:18.117962 TX Vref=24, minBit 8, minWin=27, winSum=451
1350 00:27:18.120972 TX Vref=26, minBit 1, minWin=27, winSum=450
1351 00:27:18.124459 TX Vref=28, minBit 8, minWin=27, winSum=452
1352 00:27:18.127910 TX Vref=30, minBit 4, minWin=28, winSum=457
1353 00:27:18.131044 TX Vref=32, minBit 8, minWin=27, winSum=454
1354 00:27:18.137866 [TxChooseVref] Worse bit 4, Min win 28, Win sum 457, Final Vref 30
1355 00:27:18.137933
1356 00:27:18.141407 Final TX Range 1 Vref 30
1357 00:27:18.141472
1358 00:27:18.141533 ==
1359 00:27:18.144519 Dram Type= 6, Freq= 0, CH_0, rank 1
1360 00:27:18.148057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1361 00:27:18.148127 ==
1362 00:27:18.148185
1363 00:27:18.148236
1364 00:27:18.151108 TX Vref Scan disable
1365 00:27:18.154867 == TX Byte 0 ==
1366 00:27:18.157958 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1367 00:27:18.161394 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1368 00:27:18.164606 == TX Byte 1 ==
1369 00:27:18.168099 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1370 00:27:18.171134 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1371 00:27:18.171201
1372 00:27:18.174559 [DATLAT]
1373 00:27:18.174628 Freq=800, CH0 RK1
1374 00:27:18.174686
1375 00:27:18.178118 DATLAT Default: 0xa
1376 00:27:18.178181 0, 0xFFFF, sum = 0
1377 00:27:18.181377 1, 0xFFFF, sum = 0
1378 00:27:18.181468 2, 0xFFFF, sum = 0
1379 00:27:18.184844 3, 0xFFFF, sum = 0
1380 00:27:18.184909 4, 0xFFFF, sum = 0
1381 00:27:18.188273 5, 0xFFFF, sum = 0
1382 00:27:18.188340 6, 0xFFFF, sum = 0
1383 00:27:18.191339 7, 0xFFFF, sum = 0
1384 00:27:18.191410 8, 0xFFFF, sum = 0
1385 00:27:18.194909 9, 0x0, sum = 1
1386 00:27:18.194978 10, 0x0, sum = 2
1387 00:27:18.198276 11, 0x0, sum = 3
1388 00:27:18.198346 12, 0x0, sum = 4
1389 00:27:18.201760 best_step = 10
1390 00:27:18.201831
1391 00:27:18.201885 ==
1392 00:27:18.205236 Dram Type= 6, Freq= 0, CH_0, rank 1
1393 00:27:18.208043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1394 00:27:18.208110 ==
1395 00:27:18.211723 RX Vref Scan: 0
1396 00:27:18.211794
1397 00:27:18.211849 RX Vref 0 -> 0, step: 1
1398 00:27:18.211902
1399 00:27:18.215177 RX Delay -95 -> 252, step: 8
1400 00:27:18.221835 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1401 00:27:18.224812 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1402 00:27:18.228505 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1403 00:27:18.231475 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1404 00:27:18.234812 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1405 00:27:18.238344 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1406 00:27:18.244834 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1407 00:27:18.248284 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1408 00:27:18.251791 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1409 00:27:18.255286 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1410 00:27:18.258064 iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208
1411 00:27:18.264805 iDelay=209, Bit 11, Center 80 (-23 ~ 184) 208
1412 00:27:18.268451 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1413 00:27:18.271540 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1414 00:27:18.275049 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1415 00:27:18.278393 iDelay=209, Bit 15, Center 88 (-15 ~ 192) 208
1416 00:27:18.281566 ==
1417 00:27:18.285170 Dram Type= 6, Freq= 0, CH_0, rank 1
1418 00:27:18.288410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1419 00:27:18.288480 ==
1420 00:27:18.288535 DQS Delay:
1421 00:27:18.291566 DQS0 = 0, DQS1 = 0
1422 00:27:18.291635 DQM Delay:
1423 00:27:18.295267 DQM0 = 90, DQM1 = 81
1424 00:27:18.295335 DQ Delay:
1425 00:27:18.298273 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =84
1426 00:27:18.301882 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1427 00:27:18.305439 DQ8 =76, DQ9 =68, DQ10 =80, DQ11 =80
1428 00:27:18.308430 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =88
1429 00:27:18.308523
1430 00:27:18.308607
1431 00:27:18.315313 [DQSOSCAuto] RK1, (LSB)MR18= 0x4822, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 391 ps
1432 00:27:18.318337 CH0 RK1: MR19=606, MR18=4822
1433 00:27:18.325014 CH0_RK1: MR19=0x606, MR18=0x4822, DQSOSC=391, MR23=63, INC=96, DEC=64
1434 00:27:18.328507 [RxdqsGatingPostProcess] freq 800
1435 00:27:18.331519 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1436 00:27:18.335031 Pre-setting of DQS Precalculation
1437 00:27:18.341814 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1438 00:27:18.341891 ==
1439 00:27:18.345193 Dram Type= 6, Freq= 0, CH_1, rank 0
1440 00:27:18.348360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1441 00:27:18.348455 ==
1442 00:27:18.355101 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1443 00:27:18.361602 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1444 00:27:18.369625 [CA 0] Center 36 (6~67) winsize 62
1445 00:27:18.372817 [CA 1] Center 36 (6~67) winsize 62
1446 00:27:18.376220 [CA 2] Center 34 (4~65) winsize 62
1447 00:27:18.379815 [CA 3] Center 34 (3~65) winsize 63
1448 00:27:18.383366 [CA 4] Center 34 (4~65) winsize 62
1449 00:27:18.386287 [CA 5] Center 34 (3~65) winsize 63
1450 00:27:18.386355
1451 00:27:18.389340 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1452 00:27:18.389412
1453 00:27:18.392666 [CATrainingPosCal] consider 1 rank data
1454 00:27:18.396211 u2DelayCellTimex100 = 270/100 ps
1455 00:27:18.399558 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1456 00:27:18.402905 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1457 00:27:18.409642 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1458 00:27:18.412765 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1459 00:27:18.416318 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1460 00:27:18.419515 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1461 00:27:18.419603
1462 00:27:18.422741 CA PerBit enable=1, Macro0, CA PI delay=34
1463 00:27:18.422817
1464 00:27:18.426290 [CBTSetCACLKResult] CA Dly = 34
1465 00:27:18.426361 CS Dly: 5 (0~36)
1466 00:27:18.426418 ==
1467 00:27:18.429544 Dram Type= 6, Freq= 0, CH_1, rank 1
1468 00:27:18.436173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1469 00:27:18.436264 ==
1470 00:27:18.439638 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1471 00:27:18.446254 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1472 00:27:18.455543 [CA 0] Center 36 (6~67) winsize 62
1473 00:27:18.458920 [CA 1] Center 37 (6~68) winsize 63
1474 00:27:18.462005 [CA 2] Center 35 (4~66) winsize 63
1475 00:27:18.465819 [CA 3] Center 34 (4~65) winsize 62
1476 00:27:18.468857 [CA 4] Center 34 (4~65) winsize 62
1477 00:27:18.472204 [CA 5] Center 34 (3~65) winsize 63
1478 00:27:18.472269
1479 00:27:18.475483 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1480 00:27:18.475557
1481 00:27:18.479229 [CATrainingPosCal] consider 2 rank data
1482 00:27:18.482299 u2DelayCellTimex100 = 270/100 ps
1483 00:27:18.485753 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1484 00:27:18.488768 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1485 00:27:18.495688 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1486 00:27:18.498775 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1487 00:27:18.502291 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1488 00:27:18.505744 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1489 00:27:18.505824
1490 00:27:18.509005 CA PerBit enable=1, Macro0, CA PI delay=34
1491 00:27:18.509075
1492 00:27:18.512229 [CBTSetCACLKResult] CA Dly = 34
1493 00:27:18.512302 CS Dly: 5 (0~37)
1494 00:27:18.512365
1495 00:27:18.516002 ----->DramcWriteLeveling(PI) begin...
1496 00:27:18.516087 ==
1497 00:27:18.519012 Dram Type= 6, Freq= 0, CH_1, rank 0
1498 00:27:18.526053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1499 00:27:18.526134 ==
1500 00:27:18.529294 Write leveling (Byte 0): 27 => 27
1501 00:27:18.532521 Write leveling (Byte 1): 29 => 29
1502 00:27:18.532613 DramcWriteLeveling(PI) end<-----
1503 00:27:18.536100
1504 00:27:18.536172 ==
1505 00:27:18.539164 Dram Type= 6, Freq= 0, CH_1, rank 0
1506 00:27:18.542710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1507 00:27:18.542777 ==
1508 00:27:18.545759 [Gating] SW mode calibration
1509 00:27:18.552998 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1510 00:27:18.555811 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1511 00:27:18.562836 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1512 00:27:18.566154 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 00:27:18.569246 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1514 00:27:18.575852 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 00:27:18.579358 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 00:27:18.582609 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 00:27:18.589335 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 00:27:18.592486 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 00:27:18.595673 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 00:27:18.602754 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 00:27:18.606205 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 00:27:18.609388 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 00:27:18.612994 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 00:27:18.619187 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 00:27:18.622693 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 00:27:18.626015 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 00:27:18.632411 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1528 00:27:18.635902 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1529 00:27:18.639091 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 00:27:18.645651 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 00:27:18.649285 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 00:27:18.652217 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 00:27:18.659194 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 00:27:18.662294 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 00:27:18.665957 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 00:27:18.672536 0 9 4 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
1537 00:27:18.675698 0 9 8 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1538 00:27:18.679323 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1539 00:27:18.685867 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1540 00:27:18.689277 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1541 00:27:18.692531 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1542 00:27:18.699318 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1543 00:27:18.702512 0 10 0 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
1544 00:27:18.706021 0 10 4 | B1->B0 | 2f2f 2626 | 0 0 | (1 1) (1 0)
1545 00:27:18.709274 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 00:27:18.715851 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 00:27:18.719469 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 00:27:18.722568 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 00:27:18.729326 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 00:27:18.732461 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 00:27:18.735655 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 00:27:18.742554 0 11 4 | B1->B0 | 2d2d 3636 | 0 0 | (0 0) (0 0)
1553 00:27:18.746470 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1554 00:27:18.749164 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1555 00:27:18.756105 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1556 00:27:18.759213 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1557 00:27:18.762754 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1558 00:27:18.769273 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1559 00:27:18.772884 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1560 00:27:18.776438 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1561 00:27:18.782584 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1562 00:27:18.786293 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 00:27:18.789255 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 00:27:18.792812 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 00:27:18.799545 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 00:27:18.802619 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 00:27:18.806235 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 00:27:18.812563 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 00:27:18.816139 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 00:27:18.819227 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 00:27:18.826190 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 00:27:18.829267 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 00:27:18.832500 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 00:27:18.839512 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 00:27:18.842713 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 00:27:18.846289 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1577 00:27:18.852839 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1578 00:27:18.852910 Total UI for P1: 0, mck2ui 16
1579 00:27:18.859247 best dqsien dly found for B0: ( 0, 14, 4)
1580 00:27:18.859316 Total UI for P1: 0, mck2ui 16
1581 00:27:18.862972 best dqsien dly found for B1: ( 0, 14, 6)
1582 00:27:18.869312 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1583 00:27:18.873081 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1584 00:27:18.873157
1585 00:27:18.876145 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1586 00:27:18.879690 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1587 00:27:18.882709 [Gating] SW calibration Done
1588 00:27:18.882778 ==
1589 00:27:18.886205 Dram Type= 6, Freq= 0, CH_1, rank 0
1590 00:27:18.889852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1591 00:27:18.889928 ==
1592 00:27:18.889985 RX Vref Scan: 0
1593 00:27:18.890042
1594 00:27:18.892935 RX Vref 0 -> 0, step: 1
1595 00:27:18.893000
1596 00:27:18.896451 RX Delay -130 -> 252, step: 16
1597 00:27:18.900134 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1598 00:27:18.903012 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1599 00:27:18.909806 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1600 00:27:18.913091 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1601 00:27:18.916401 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1602 00:27:18.919523 iDelay=222, Bit 5, Center 101 (-2 ~ 205) 208
1603 00:27:18.923164 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1604 00:27:18.929970 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1605 00:27:18.933021 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1606 00:27:18.936411 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1607 00:27:18.939800 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1608 00:27:18.943290 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1609 00:27:18.949741 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1610 00:27:18.952826 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1611 00:27:18.956482 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1612 00:27:18.959932 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1613 00:27:18.960009 ==
1614 00:27:18.963076 Dram Type= 6, Freq= 0, CH_1, rank 0
1615 00:27:18.969818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1616 00:27:18.969895 ==
1617 00:27:18.969954 DQS Delay:
1618 00:27:18.970010 DQS0 = 0, DQS1 = 0
1619 00:27:18.972847 DQM Delay:
1620 00:27:18.972923 DQM0 = 92, DQM1 = 87
1621 00:27:18.976514 DQ Delay:
1622 00:27:18.979626 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1623 00:27:18.983210 DQ4 =93, DQ5 =101, DQ6 =101, DQ7 =93
1624 00:27:18.986372 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =77
1625 00:27:18.989447 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1626 00:27:18.989523
1627 00:27:18.989582
1628 00:27:18.989637 ==
1629 00:27:18.992776 Dram Type= 6, Freq= 0, CH_1, rank 0
1630 00:27:18.996518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1631 00:27:18.996595 ==
1632 00:27:18.996654
1633 00:27:18.996732
1634 00:27:19.000013 TX Vref Scan disable
1635 00:27:19.000089 == TX Byte 0 ==
1636 00:27:19.006343 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1637 00:27:19.009675 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1638 00:27:19.009752 == TX Byte 1 ==
1639 00:27:19.016395 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1640 00:27:19.019735 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1641 00:27:19.019818 ==
1642 00:27:19.023375 Dram Type= 6, Freq= 0, CH_1, rank 0
1643 00:27:19.026543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1644 00:27:19.026701 ==
1645 00:27:19.040315 TX Vref=22, minBit 15, minWin=26, winSum=444
1646 00:27:19.043797 TX Vref=24, minBit 8, minWin=27, winSum=451
1647 00:27:19.046850 TX Vref=26, minBit 15, minWin=27, winSum=453
1648 00:27:19.050662 TX Vref=28, minBit 15, minWin=27, winSum=456
1649 00:27:19.053559 TX Vref=30, minBit 1, minWin=28, winSum=457
1650 00:27:19.060477 TX Vref=32, minBit 15, minWin=27, winSum=457
1651 00:27:19.063710 [TxChooseVref] Worse bit 1, Min win 28, Win sum 457, Final Vref 30
1652 00:27:19.063852
1653 00:27:19.067352 Final TX Range 1 Vref 30
1654 00:27:19.067530
1655 00:27:19.067651 ==
1656 00:27:19.070673 Dram Type= 6, Freq= 0, CH_1, rank 0
1657 00:27:19.073848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1658 00:27:19.074028 ==
1659 00:27:19.076997
1660 00:27:19.077151
1661 00:27:19.077243 TX Vref Scan disable
1662 00:27:19.080535 == TX Byte 0 ==
1663 00:27:19.083845 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1664 00:27:19.087661 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1665 00:27:19.090544 == TX Byte 1 ==
1666 00:27:19.094082 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1667 00:27:19.097662 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1668 00:27:19.100938
1669 00:27:19.101273 [DATLAT]
1670 00:27:19.101460 Freq=800, CH1 RK0
1671 00:27:19.101630
1672 00:27:19.104178 DATLAT Default: 0xa
1673 00:27:19.104461 0, 0xFFFF, sum = 0
1674 00:27:19.107688 1, 0xFFFF, sum = 0
1675 00:27:19.107971 2, 0xFFFF, sum = 0
1676 00:27:19.110737 3, 0xFFFF, sum = 0
1677 00:27:19.111351 4, 0xFFFF, sum = 0
1678 00:27:19.114336 5, 0xFFFF, sum = 0
1679 00:27:19.115056 6, 0xFFFF, sum = 0
1680 00:27:19.117434 7, 0xFFFF, sum = 0
1681 00:27:19.120926 8, 0xFFFF, sum = 0
1682 00:27:19.121661 9, 0x0, sum = 1
1683 00:27:19.122320 10, 0x0, sum = 2
1684 00:27:19.124012 11, 0x0, sum = 3
1685 00:27:19.124737 12, 0x0, sum = 4
1686 00:27:19.127337 best_step = 10
1687 00:27:19.128042
1688 00:27:19.128697 ==
1689 00:27:19.130820 Dram Type= 6, Freq= 0, CH_1, rank 0
1690 00:27:19.134220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1691 00:27:19.134921 ==
1692 00:27:19.137440 RX Vref Scan: 1
1693 00:27:19.138147
1694 00:27:19.138761 Set Vref Range= 32 -> 127
1695 00:27:19.139208
1696 00:27:19.140768 RX Vref 32 -> 127, step: 1
1697 00:27:19.141239
1698 00:27:19.144189 RX Delay -79 -> 252, step: 8
1699 00:27:19.144541
1700 00:27:19.147297 Set Vref, RX VrefLevel [Byte0]: 32
1701 00:27:19.150705 [Byte1]: 32
1702 00:27:19.150982
1703 00:27:19.154267 Set Vref, RX VrefLevel [Byte0]: 33
1704 00:27:19.157304 [Byte1]: 33
1705 00:27:19.160810
1706 00:27:19.161024 Set Vref, RX VrefLevel [Byte0]: 34
1707 00:27:19.163860 [Byte1]: 34
1708 00:27:19.167813
1709 00:27:19.167940 Set Vref, RX VrefLevel [Byte0]: 35
1710 00:27:19.171489 [Byte1]: 35
1711 00:27:19.175786
1712 00:27:19.175914 Set Vref, RX VrefLevel [Byte0]: 36
1713 00:27:19.179153 [Byte1]: 36
1714 00:27:19.183376
1715 00:27:19.183469 Set Vref, RX VrefLevel [Byte0]: 37
1716 00:27:19.186434 [Byte1]: 37
1717 00:27:19.190766
1718 00:27:19.191127 Set Vref, RX VrefLevel [Byte0]: 38
1719 00:27:19.194145 [Byte1]: 38
1720 00:27:19.198578
1721 00:27:19.198939 Set Vref, RX VrefLevel [Byte0]: 39
1722 00:27:19.202265 [Byte1]: 39
1723 00:27:19.205869
1724 00:27:19.206238 Set Vref, RX VrefLevel [Byte0]: 40
1725 00:27:19.209254 [Byte1]: 40
1726 00:27:19.213699
1727 00:27:19.214112 Set Vref, RX VrefLevel [Byte0]: 41
1728 00:27:19.216738 [Byte1]: 41
1729 00:27:19.221298
1730 00:27:19.221977 Set Vref, RX VrefLevel [Byte0]: 42
1731 00:27:19.224504 [Byte1]: 42
1732 00:27:19.228918
1733 00:27:19.229455 Set Vref, RX VrefLevel [Byte0]: 43
1734 00:27:19.232074 [Byte1]: 43
1735 00:27:19.236642
1736 00:27:19.237180 Set Vref, RX VrefLevel [Byte0]: 44
1737 00:27:19.239801 [Byte1]: 44
1738 00:27:19.243927
1739 00:27:19.244431 Set Vref, RX VrefLevel [Byte0]: 45
1740 00:27:19.247182 [Byte1]: 45
1741 00:27:19.251246
1742 00:27:19.251821 Set Vref, RX VrefLevel [Byte0]: 46
1743 00:27:19.254473 [Byte1]: 46
1744 00:27:19.259075
1745 00:27:19.259627 Set Vref, RX VrefLevel [Byte0]: 47
1746 00:27:19.262235 [Byte1]: 47
1747 00:27:19.266848
1748 00:27:19.267374 Set Vref, RX VrefLevel [Byte0]: 48
1749 00:27:19.269769 [Byte1]: 48
1750 00:27:19.274481
1751 00:27:19.275008 Set Vref, RX VrefLevel [Byte0]: 49
1752 00:27:19.277476 [Byte1]: 49
1753 00:27:19.281564
1754 00:27:19.282087 Set Vref, RX VrefLevel [Byte0]: 50
1755 00:27:19.284872 [Byte1]: 50
1756 00:27:19.289434
1757 00:27:19.289965 Set Vref, RX VrefLevel [Byte0]: 51
1758 00:27:19.292506 [Byte1]: 51
1759 00:27:19.296527
1760 00:27:19.296831 Set Vref, RX VrefLevel [Byte0]: 52
1761 00:27:19.299801 [Byte1]: 52
1762 00:27:19.303706
1763 00:27:19.303836 Set Vref, RX VrefLevel [Byte0]: 53
1764 00:27:19.307250 [Byte1]: 53
1765 00:27:19.311700
1766 00:27:19.311846 Set Vref, RX VrefLevel [Byte0]: 54
1767 00:27:19.314587 [Byte1]: 54
1768 00:27:19.319203
1769 00:27:19.319300 Set Vref, RX VrefLevel [Byte0]: 55
1770 00:27:19.322425 [Byte1]: 55
1771 00:27:19.326505
1772 00:27:19.326599 Set Vref, RX VrefLevel [Byte0]: 56
1773 00:27:19.330339 [Byte1]: 56
1774 00:27:19.334431
1775 00:27:19.334988 Set Vref, RX VrefLevel [Byte0]: 57
1776 00:27:19.337854 [Byte1]: 57
1777 00:27:19.342004
1778 00:27:19.342548 Set Vref, RX VrefLevel [Byte0]: 58
1779 00:27:19.345040 [Byte1]: 58
1780 00:27:19.349826
1781 00:27:19.350365 Set Vref, RX VrefLevel [Byte0]: 59
1782 00:27:19.352817 [Byte1]: 59
1783 00:27:19.356981
1784 00:27:19.357582 Set Vref, RX VrefLevel [Byte0]: 60
1785 00:27:19.360377 [Byte1]: 60
1786 00:27:19.364805
1787 00:27:19.365526 Set Vref, RX VrefLevel [Byte0]: 61
1788 00:27:19.367976 [Byte1]: 61
1789 00:27:19.372219
1790 00:27:19.372960 Set Vref, RX VrefLevel [Byte0]: 62
1791 00:27:19.375493 [Byte1]: 62
1792 00:27:19.379892
1793 00:27:19.380257 Set Vref, RX VrefLevel [Byte0]: 63
1794 00:27:19.382892 [Byte1]: 63
1795 00:27:19.386971
1796 00:27:19.387249 Set Vref, RX VrefLevel [Byte0]: 64
1797 00:27:19.390359 [Byte1]: 64
1798 00:27:19.394400
1799 00:27:19.394605 Set Vref, RX VrefLevel [Byte0]: 65
1800 00:27:19.397998 [Byte1]: 65
1801 00:27:19.401998
1802 00:27:19.402178 Set Vref, RX VrefLevel [Byte0]: 66
1803 00:27:19.405555 [Byte1]: 66
1804 00:27:19.409561
1805 00:27:19.409704 Set Vref, RX VrefLevel [Byte0]: 67
1806 00:27:19.413012 [Byte1]: 67
1807 00:27:19.417189
1808 00:27:19.417291 Set Vref, RX VrefLevel [Byte0]: 68
1809 00:27:19.420484 [Byte1]: 68
1810 00:27:19.424628
1811 00:27:19.424775 Set Vref, RX VrefLevel [Byte0]: 69
1812 00:27:19.428477 [Byte1]: 69
1813 00:27:19.432241
1814 00:27:19.432337 Set Vref, RX VrefLevel [Byte0]: 70
1815 00:27:19.435643 [Byte1]: 70
1816 00:27:19.439491
1817 00:27:19.439593 Set Vref, RX VrefLevel [Byte0]: 71
1818 00:27:19.442965 [Byte1]: 71
1819 00:27:19.447452
1820 00:27:19.447548 Set Vref, RX VrefLevel [Byte0]: 72
1821 00:27:19.450497 [Byte1]: 72
1822 00:27:19.455318
1823 00:27:19.455794 Set Vref, RX VrefLevel [Byte0]: 73
1824 00:27:19.458385 [Byte1]: 73
1825 00:27:19.462850
1826 00:27:19.463366 Set Vref, RX VrefLevel [Byte0]: 74
1827 00:27:19.465784 [Byte1]: 74
1828 00:27:19.470307
1829 00:27:19.470800 Set Vref, RX VrefLevel [Byte0]: 75
1830 00:27:19.473769 [Byte1]: 75
1831 00:27:19.477799
1832 00:27:19.478357 Set Vref, RX VrefLevel [Byte0]: 76
1833 00:27:19.481255 [Byte1]: 76
1834 00:27:19.485571
1835 00:27:19.485962 Set Vref, RX VrefLevel [Byte0]: 77
1836 00:27:19.488647 [Byte1]: 77
1837 00:27:19.493056
1838 00:27:19.493442 Set Vref, RX VrefLevel [Byte0]: 78
1839 00:27:19.495951 [Byte1]: 78
1840 00:27:19.500755
1841 00:27:19.501153 Final RX Vref Byte 0 = 51 to rank0
1842 00:27:19.503654 Final RX Vref Byte 1 = 63 to rank0
1843 00:27:19.507313 Final RX Vref Byte 0 = 51 to rank1
1844 00:27:19.510405 Final RX Vref Byte 1 = 63 to rank1==
1845 00:27:19.513976 Dram Type= 6, Freq= 0, CH_1, rank 0
1846 00:27:19.517290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1847 00:27:19.520398 ==
1848 00:27:19.520734 DQS Delay:
1849 00:27:19.521019 DQS0 = 0, DQS1 = 0
1850 00:27:19.523752 DQM Delay:
1851 00:27:19.523939 DQM0 = 92, DQM1 = 83
1852 00:27:19.526974 DQ Delay:
1853 00:27:19.530358 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =88
1854 00:27:19.533901 DQ4 =92, DQ5 =104, DQ6 =100, DQ7 =88
1855 00:27:19.534025 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =80
1856 00:27:19.540106 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
1857 00:27:19.540234
1858 00:27:19.540318
1859 00:27:19.546735 [DQSOSCAuto] RK0, (LSB)MR18= 0x314d, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
1860 00:27:19.550277 CH1 RK0: MR19=606, MR18=314D
1861 00:27:19.556779 CH1_RK0: MR19=0x606, MR18=0x314D, DQSOSC=390, MR23=63, INC=97, DEC=64
1862 00:27:19.556854
1863 00:27:19.560451 ----->DramcWriteLeveling(PI) begin...
1864 00:27:19.560562 ==
1865 00:27:19.563517 Dram Type= 6, Freq= 0, CH_1, rank 1
1866 00:27:19.567047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1867 00:27:19.567122 ==
1868 00:27:19.570413 Write leveling (Byte 0): 28 => 28
1869 00:27:19.573560 Write leveling (Byte 1): 28 => 28
1870 00:27:19.576944 DramcWriteLeveling(PI) end<-----
1871 00:27:19.577013
1872 00:27:19.577070 ==
1873 00:27:19.580630 Dram Type= 6, Freq= 0, CH_1, rank 1
1874 00:27:19.583742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1875 00:27:19.583814 ==
1876 00:27:19.587157 [Gating] SW mode calibration
1877 00:27:19.594103 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1878 00:27:19.600470 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1879 00:27:19.604006 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1880 00:27:19.607773 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1881 00:27:19.614779 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 00:27:19.617713 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 00:27:19.621153 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 00:27:19.627804 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 00:27:19.631663 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 00:27:19.634869 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 00:27:19.637938 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 00:27:19.644569 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 00:27:19.648128 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 00:27:19.651562 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 00:27:19.658525 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 00:27:19.661399 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 00:27:19.664737 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 00:27:19.671735 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 00:27:19.674847 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1896 00:27:19.678474 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1897 00:27:19.684871 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 00:27:19.687978 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 00:27:19.691656 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 00:27:19.694813 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 00:27:19.701303 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 00:27:19.704680 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 00:27:19.707998 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 00:27:19.714356 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 00:27:19.718001 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1906 00:27:19.721098 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1907 00:27:19.727945 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1908 00:27:19.731079 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1909 00:27:19.734822 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1910 00:27:19.741206 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1911 00:27:19.745248 0 10 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1912 00:27:19.748634 0 10 4 | B1->B0 | 2b2b 3030 | 1 0 | (1 1) (0 0)
1913 00:27:19.755311 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1914 00:27:19.758618 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1915 00:27:19.761793 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1916 00:27:19.765535 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1917 00:27:19.772034 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1918 00:27:19.775327 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1919 00:27:19.778955 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1920 00:27:19.785467 0 11 4 | B1->B0 | 3333 3131 | 0 0 | (0 0) (0 0)
1921 00:27:19.788873 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1922 00:27:19.791785 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1923 00:27:19.798933 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1924 00:27:19.801961 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1925 00:27:19.805565 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1926 00:27:19.811956 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1927 00:27:19.815265 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1928 00:27:19.818840 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1929 00:27:19.825446 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 00:27:19.828888 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 00:27:19.831801 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 00:27:19.835431 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 00:27:19.841955 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 00:27:19.845418 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 00:27:19.851651 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 00:27:19.854976 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 00:27:19.858674 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 00:27:19.861608 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 00:27:19.868588 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1940 00:27:19.871514 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1941 00:27:19.874849 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1942 00:27:19.881877 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1943 00:27:19.885190 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1944 00:27:19.888629 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1945 00:27:19.895056 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1946 00:27:19.895231 Total UI for P1: 0, mck2ui 16
1947 00:27:19.902116 best dqsien dly found for B0: ( 0, 14, 4)
1948 00:27:19.902325 Total UI for P1: 0, mck2ui 16
1949 00:27:19.905167 best dqsien dly found for B1: ( 0, 14, 6)
1950 00:27:19.912307 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1951 00:27:19.915249 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1952 00:27:19.915503
1953 00:27:19.918777 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1954 00:27:19.922004 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1955 00:27:19.925152 [Gating] SW calibration Done
1956 00:27:19.925427 ==
1957 00:27:19.928592 Dram Type= 6, Freq= 0, CH_1, rank 1
1958 00:27:19.932067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1959 00:27:19.932693 ==
1960 00:27:19.933159 RX Vref Scan: 0
1961 00:27:19.935595
1962 00:27:19.936130 RX Vref 0 -> 0, step: 1
1963 00:27:19.936842
1964 00:27:19.938701 RX Delay -130 -> 252, step: 16
1965 00:27:19.942294 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1966 00:27:19.945162 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1967 00:27:19.952120 iDelay=206, Bit 2, Center 85 (-18 ~ 189) 208
1968 00:27:19.955738 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1969 00:27:19.958722 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1970 00:27:19.962394 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1971 00:27:19.965667 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1972 00:27:19.972083 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1973 00:27:19.975423 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1974 00:27:19.978725 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1975 00:27:19.981997 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1976 00:27:19.985419 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1977 00:27:19.992313 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1978 00:27:19.995474 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1979 00:27:19.999155 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1980 00:27:20.002315 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1981 00:27:20.002725 ==
1982 00:27:20.005599 Dram Type= 6, Freq= 0, CH_1, rank 1
1983 00:27:20.009095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1984 00:27:20.012638 ==
1985 00:27:20.013053 DQS Delay:
1986 00:27:20.013366 DQS0 = 0, DQS1 = 0
1987 00:27:20.015742 DQM Delay:
1988 00:27:20.016062 DQM0 = 90, DQM1 = 84
1989 00:27:20.018900 DQ Delay:
1990 00:27:20.019318 DQ0 =93, DQ1 =85, DQ2 =85, DQ3 =93
1991 00:27:20.022147 DQ4 =93, DQ5 =93, DQ6 =93, DQ7 =85
1992 00:27:20.025654 DQ8 =69, DQ9 =77, DQ10 =85, DQ11 =77
1993 00:27:20.029140 DQ12 =93, DQ13 =93, DQ14 =85, DQ15 =93
1994 00:27:20.029496
1995 00:27:20.032744
1996 00:27:20.033092 ==
1997 00:27:20.035742 Dram Type= 6, Freq= 0, CH_1, rank 1
1998 00:27:20.039284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1999 00:27:20.039635 ==
2000 00:27:20.039990
2001 00:27:20.040262
2002 00:27:20.042351 TX Vref Scan disable
2003 00:27:20.042681 == TX Byte 0 ==
2004 00:27:20.046071 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2005 00:27:20.052413 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2006 00:27:20.052816 == TX Byte 1 ==
2007 00:27:20.056302 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2008 00:27:20.062249 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2009 00:27:20.062644 ==
2010 00:27:20.066199 Dram Type= 6, Freq= 0, CH_1, rank 1
2011 00:27:20.069139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2012 00:27:20.069537 ==
2013 00:27:20.082252 TX Vref=22, minBit 3, minWin=27, winSum=448
2014 00:27:20.085996 TX Vref=24, minBit 13, minWin=27, winSum=452
2015 00:27:20.089439 TX Vref=26, minBit 15, minWin=27, winSum=456
2016 00:27:20.092776 TX Vref=28, minBit 8, minWin=28, winSum=460
2017 00:27:20.095650 TX Vref=30, minBit 8, minWin=28, winSum=461
2018 00:27:20.099024 TX Vref=32, minBit 8, minWin=28, winSum=459
2019 00:27:20.106066 [TxChooseVref] Worse bit 8, Min win 28, Win sum 461, Final Vref 30
2020 00:27:20.106460
2021 00:27:20.109185 Final TX Range 1 Vref 30
2022 00:27:20.109575
2023 00:27:20.109878 ==
2024 00:27:20.112406 Dram Type= 6, Freq= 0, CH_1, rank 1
2025 00:27:20.116049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2026 00:27:20.116443 ==
2027 00:27:20.116778
2028 00:27:20.117064
2029 00:27:20.119047 TX Vref Scan disable
2030 00:27:20.122694 == TX Byte 0 ==
2031 00:27:20.125759 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2032 00:27:20.129068 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2033 00:27:20.132391 == TX Byte 1 ==
2034 00:27:20.135602 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2035 00:27:20.138967 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2036 00:27:20.139044
2037 00:27:20.142541 [DATLAT]
2038 00:27:20.142617 Freq=800, CH1 RK1
2039 00:27:20.142678
2040 00:27:20.145664 DATLAT Default: 0xa
2041 00:27:20.145740 0, 0xFFFF, sum = 0
2042 00:27:20.149274 1, 0xFFFF, sum = 0
2043 00:27:20.149352 2, 0xFFFF, sum = 0
2044 00:27:20.152345 3, 0xFFFF, sum = 0
2045 00:27:20.152424 4, 0xFFFF, sum = 0
2046 00:27:20.155722 5, 0xFFFF, sum = 0
2047 00:27:20.155800 6, 0xFFFF, sum = 0
2048 00:27:20.159052 7, 0xFFFF, sum = 0
2049 00:27:20.159130 8, 0xFFFF, sum = 0
2050 00:27:20.162676 9, 0x0, sum = 1
2051 00:27:20.162754 10, 0x0, sum = 2
2052 00:27:20.165893 11, 0x0, sum = 3
2053 00:27:20.165971 12, 0x0, sum = 4
2054 00:27:20.169286 best_step = 10
2055 00:27:20.169362
2056 00:27:20.169421 ==
2057 00:27:20.172735 Dram Type= 6, Freq= 0, CH_1, rank 1
2058 00:27:20.175690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2059 00:27:20.175768 ==
2060 00:27:20.178943 RX Vref Scan: 0
2061 00:27:20.179019
2062 00:27:20.179079 RX Vref 0 -> 0, step: 1
2063 00:27:20.179134
2064 00:27:20.182436 RX Delay -95 -> 252, step: 8
2065 00:27:20.185854 iDelay=209, Bit 0, Center 96 (-7 ~ 200) 208
2066 00:27:20.192547 iDelay=209, Bit 1, Center 88 (-15 ~ 192) 208
2067 00:27:20.195995 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2068 00:27:20.199108 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2069 00:27:20.202694 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
2070 00:27:20.206051 iDelay=209, Bit 5, Center 100 (-7 ~ 208) 216
2071 00:27:20.212272 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2072 00:27:20.215705 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2073 00:27:20.219102 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2074 00:27:20.222455 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2075 00:27:20.225897 iDelay=209, Bit 10, Center 88 (-23 ~ 200) 224
2076 00:27:20.232559 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2077 00:27:20.235822 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2078 00:27:20.239470 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2079 00:27:20.242379 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2080 00:27:20.245902 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
2081 00:27:20.249364 ==
2082 00:27:20.249440 Dram Type= 6, Freq= 0, CH_1, rank 1
2083 00:27:20.255690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2084 00:27:20.255767 ==
2085 00:27:20.255827 DQS Delay:
2086 00:27:20.259064 DQS0 = 0, DQS1 = 0
2087 00:27:20.259141 DQM Delay:
2088 00:27:20.262686 DQM0 = 91, DQM1 = 83
2089 00:27:20.262763 DQ Delay:
2090 00:27:20.265693 DQ0 =96, DQ1 =88, DQ2 =80, DQ3 =88
2091 00:27:20.269638 DQ4 =92, DQ5 =100, DQ6 =96, DQ7 =88
2092 00:27:20.272652 DQ8 =68, DQ9 =72, DQ10 =88, DQ11 =80
2093 00:27:20.275963 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =92
2094 00:27:20.276039
2095 00:27:20.276099
2096 00:27:20.282698 [DQSOSCAuto] RK1, (LSB)MR18= 0x3d12, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
2097 00:27:20.285957 CH1 RK1: MR19=606, MR18=3D12
2098 00:27:20.292972 CH1_RK1: MR19=0x606, MR18=0x3D12, DQSOSC=394, MR23=63, INC=95, DEC=63
2099 00:27:20.296213 [RxdqsGatingPostProcess] freq 800
2100 00:27:20.299423 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2101 00:27:20.302921 Pre-setting of DQS Precalculation
2102 00:27:20.309615 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2103 00:27:20.316224 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2104 00:27:20.322893 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2105 00:27:20.323035
2106 00:27:20.323144
2107 00:27:20.326547 [Calibration Summary] 1600 Mbps
2108 00:27:20.326715 CH 0, Rank 0
2109 00:27:20.329732 SW Impedance : PASS
2110 00:27:20.333677 DUTY Scan : NO K
2111 00:27:20.333937 ZQ Calibration : PASS
2112 00:27:20.336458 Jitter Meter : NO K
2113 00:27:20.339957 CBT Training : PASS
2114 00:27:20.340264 Write leveling : PASS
2115 00:27:20.343639 RX DQS gating : PASS
2116 00:27:20.346933 RX DQ/DQS(RDDQC) : PASS
2117 00:27:20.347475 TX DQ/DQS : PASS
2118 00:27:20.350181 RX DATLAT : PASS
2119 00:27:20.350679 RX DQ/DQS(Engine): PASS
2120 00:27:20.353334 TX OE : NO K
2121 00:27:20.353767 All Pass.
2122 00:27:20.354197
2123 00:27:20.356876 CH 0, Rank 1
2124 00:27:20.357453 SW Impedance : PASS
2125 00:27:20.360245 DUTY Scan : NO K
2126 00:27:20.363332 ZQ Calibration : PASS
2127 00:27:20.363821 Jitter Meter : NO K
2128 00:27:20.366741 CBT Training : PASS
2129 00:27:20.369963 Write leveling : PASS
2130 00:27:20.370547 RX DQS gating : PASS
2131 00:27:20.373510 RX DQ/DQS(RDDQC) : PASS
2132 00:27:20.376887 TX DQ/DQS : PASS
2133 00:27:20.377426 RX DATLAT : PASS
2134 00:27:20.379965 RX DQ/DQS(Engine): PASS
2135 00:27:20.383565 TX OE : NO K
2136 00:27:20.383993 All Pass.
2137 00:27:20.384307
2138 00:27:20.384615 CH 1, Rank 0
2139 00:27:20.386798 SW Impedance : PASS
2140 00:27:20.389969 DUTY Scan : NO K
2141 00:27:20.390361 ZQ Calibration : PASS
2142 00:27:20.393276 Jitter Meter : NO K
2143 00:27:20.393670 CBT Training : PASS
2144 00:27:20.396947 Write leveling : PASS
2145 00:27:20.400139 RX DQS gating : PASS
2146 00:27:20.400527 RX DQ/DQS(RDDQC) : PASS
2147 00:27:20.403811 TX DQ/DQS : PASS
2148 00:27:20.406787 RX DATLAT : PASS
2149 00:27:20.407172 RX DQ/DQS(Engine): PASS
2150 00:27:20.410517 TX OE : NO K
2151 00:27:20.410911 All Pass.
2152 00:27:20.411212
2153 00:27:20.413512 CH 1, Rank 1
2154 00:27:20.413953 SW Impedance : PASS
2155 00:27:20.416952 DUTY Scan : NO K
2156 00:27:20.420458 ZQ Calibration : PASS
2157 00:27:20.420888 Jitter Meter : NO K
2158 00:27:20.423478 CBT Training : PASS
2159 00:27:20.426781 Write leveling : PASS
2160 00:27:20.427167 RX DQS gating : PASS
2161 00:27:20.430119 RX DQ/DQS(RDDQC) : PASS
2162 00:27:20.430516 TX DQ/DQS : PASS
2163 00:27:20.433761 RX DATLAT : PASS
2164 00:27:20.436964 RX DQ/DQS(Engine): PASS
2165 00:27:20.437354 TX OE : NO K
2166 00:27:20.440320 All Pass.
2167 00:27:20.440731
2168 00:27:20.441058 DramC Write-DBI off
2169 00:27:20.443645 PER_BANK_REFRESH: Hybrid Mode
2170 00:27:20.446955 TX_TRACKING: ON
2171 00:27:20.450164 [GetDramInforAfterCalByMRR] Vendor 6.
2172 00:27:20.453753 [GetDramInforAfterCalByMRR] Revision 606.
2173 00:27:20.456673 [GetDramInforAfterCalByMRR] Revision 2 0.
2174 00:27:20.457103 MR0 0x3b3b
2175 00:27:20.457409 MR8 0x5151
2176 00:27:20.463776 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2177 00:27:20.464252
2178 00:27:20.464587 MR0 0x3b3b
2179 00:27:20.464953 MR8 0x5151
2180 00:27:20.466822 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2181 00:27:20.467254
2182 00:27:20.477338 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2183 00:27:20.480179 [FAST_K] Save calibration result to emmc
2184 00:27:20.483817 [FAST_K] Save calibration result to emmc
2185 00:27:20.487480 dram_init: config_dvfs: 1
2186 00:27:20.490489 dramc_set_vcore_voltage set vcore to 662500
2187 00:27:20.493628 Read voltage for 1200, 2
2188 00:27:20.494062 Vio18 = 0
2189 00:27:20.494399 Vcore = 662500
2190 00:27:20.497092 Vdram = 0
2191 00:27:20.497570 Vddq = 0
2192 00:27:20.497906 Vmddr = 0
2193 00:27:20.503772 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2194 00:27:20.507034 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2195 00:27:20.510359 MEM_TYPE=3, freq_sel=15
2196 00:27:20.513963 sv_algorithm_assistance_LP4_1600
2197 00:27:20.517267 ============ PULL DRAM RESETB DOWN ============
2198 00:27:20.520515 ========== PULL DRAM RESETB DOWN end =========
2199 00:27:20.527034 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2200 00:27:20.530589 ===================================
2201 00:27:20.531040 LPDDR4 DRAM CONFIGURATION
2202 00:27:20.533654 ===================================
2203 00:27:20.537156 EX_ROW_EN[0] = 0x0
2204 00:27:20.540274 EX_ROW_EN[1] = 0x0
2205 00:27:20.540744 LP4Y_EN = 0x0
2206 00:27:20.544003 WORK_FSP = 0x0
2207 00:27:20.544434 WL = 0x4
2208 00:27:20.547083 RL = 0x4
2209 00:27:20.547657 BL = 0x2
2210 00:27:20.550658 RPST = 0x0
2211 00:27:20.551168 RD_PRE = 0x0
2212 00:27:20.554062 WR_PRE = 0x1
2213 00:27:20.554496 WR_PST = 0x0
2214 00:27:20.557447 DBI_WR = 0x0
2215 00:27:20.557878 DBI_RD = 0x0
2216 00:27:20.560425 OTF = 0x1
2217 00:27:20.564002 ===================================
2218 00:27:20.567369 ===================================
2219 00:27:20.567803 ANA top config
2220 00:27:20.570487 ===================================
2221 00:27:20.573906 DLL_ASYNC_EN = 0
2222 00:27:20.577125 ALL_SLAVE_EN = 0
2223 00:27:20.577653 NEW_RANK_MODE = 1
2224 00:27:20.580741 DLL_IDLE_MODE = 1
2225 00:27:20.583540 LP45_APHY_COMB_EN = 1
2226 00:27:20.586965 TX_ODT_DIS = 1
2227 00:27:20.590588 NEW_8X_MODE = 1
2228 00:27:20.593636 ===================================
2229 00:27:20.597171 ===================================
2230 00:27:20.597562 data_rate = 2400
2231 00:27:20.600146 CKR = 1
2232 00:27:20.603848 DQ_P2S_RATIO = 8
2233 00:27:20.607414 ===================================
2234 00:27:20.610485 CA_P2S_RATIO = 8
2235 00:27:20.613754 DQ_CA_OPEN = 0
2236 00:27:20.617256 DQ_SEMI_OPEN = 0
2237 00:27:20.617661 CA_SEMI_OPEN = 0
2238 00:27:20.620551 CA_FULL_RATE = 0
2239 00:27:20.623870 DQ_CKDIV4_EN = 0
2240 00:27:20.627246 CA_CKDIV4_EN = 0
2241 00:27:20.630470 CA_PREDIV_EN = 0
2242 00:27:20.634523 PH8_DLY = 17
2243 00:27:20.635043 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2244 00:27:20.637362 DQ_AAMCK_DIV = 4
2245 00:27:20.640467 CA_AAMCK_DIV = 4
2246 00:27:20.644147 CA_ADMCK_DIV = 4
2247 00:27:20.647333 DQ_TRACK_CA_EN = 0
2248 00:27:20.650602 CA_PICK = 1200
2249 00:27:20.651006 CA_MCKIO = 1200
2250 00:27:20.653826 MCKIO_SEMI = 0
2251 00:27:20.657644 PLL_FREQ = 2366
2252 00:27:20.660697 DQ_UI_PI_RATIO = 32
2253 00:27:20.663947 CA_UI_PI_RATIO = 0
2254 00:27:20.667416 ===================================
2255 00:27:20.670801 ===================================
2256 00:27:20.674353 memory_type:LPDDR4
2257 00:27:20.674742 GP_NUM : 10
2258 00:27:20.677395 SRAM_EN : 1
2259 00:27:20.677788 MD32_EN : 0
2260 00:27:20.681022 ===================================
2261 00:27:20.683986 [ANA_INIT] >>>>>>>>>>>>>>
2262 00:27:20.687514 <<<<<< [CONFIGURE PHASE]: ANA_TX
2263 00:27:20.690565 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2264 00:27:20.694232 ===================================
2265 00:27:20.697451 data_rate = 2400,PCW = 0X5b00
2266 00:27:20.700967 ===================================
2267 00:27:20.704265 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2268 00:27:20.707718 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2269 00:27:20.714298 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2270 00:27:20.717794 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2271 00:27:20.720781 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2272 00:27:20.724214 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2273 00:27:20.727367 [ANA_INIT] flow start
2274 00:27:20.730779 [ANA_INIT] PLL >>>>>>>>
2275 00:27:20.731172 [ANA_INIT] PLL <<<<<<<<
2276 00:27:20.734132 [ANA_INIT] MIDPI >>>>>>>>
2277 00:27:20.737626 [ANA_INIT] MIDPI <<<<<<<<
2278 00:27:20.741230 [ANA_INIT] DLL >>>>>>>>
2279 00:27:20.741621 [ANA_INIT] DLL <<<<<<<<
2280 00:27:20.744237 [ANA_INIT] flow end
2281 00:27:20.747421 ============ LP4 DIFF to SE enter ============
2282 00:27:20.750988 ============ LP4 DIFF to SE exit ============
2283 00:27:20.754339 [ANA_INIT] <<<<<<<<<<<<<
2284 00:27:20.757549 [Flow] Enable top DCM control >>>>>
2285 00:27:20.760635 [Flow] Enable top DCM control <<<<<
2286 00:27:20.764387 Enable DLL master slave shuffle
2287 00:27:20.770633 ==============================================================
2288 00:27:20.771029 Gating Mode config
2289 00:27:20.777396 ==============================================================
2290 00:27:20.777793 Config description:
2291 00:27:20.787413 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2292 00:27:20.794256 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2293 00:27:20.800763 SELPH_MODE 0: By rank 1: By Phase
2294 00:27:20.804203 ==============================================================
2295 00:27:20.807408 GAT_TRACK_EN = 1
2296 00:27:20.810906 RX_GATING_MODE = 2
2297 00:27:20.814098 RX_GATING_TRACK_MODE = 2
2298 00:27:20.817760 SELPH_MODE = 1
2299 00:27:20.820661 PICG_EARLY_EN = 1
2300 00:27:20.824131 VALID_LAT_VALUE = 1
2301 00:27:20.827322 ==============================================================
2302 00:27:20.830957 Enter into Gating configuration >>>>
2303 00:27:20.833966 Exit from Gating configuration <<<<
2304 00:27:20.837375 Enter into DVFS_PRE_config >>>>>
2305 00:27:20.850499 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2306 00:27:20.854211 Exit from DVFS_PRE_config <<<<<
2307 00:27:20.854603 Enter into PICG configuration >>>>
2308 00:27:20.857216 Exit from PICG configuration <<<<
2309 00:27:20.860768 [RX_INPUT] configuration >>>>>
2310 00:27:20.864000 [RX_INPUT] configuration <<<<<
2311 00:27:20.870526 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2312 00:27:20.874101 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2313 00:27:20.880824 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2314 00:27:20.887295 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2315 00:27:20.894171 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2316 00:27:20.900604 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2317 00:27:20.904211 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2318 00:27:20.907703 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2319 00:27:20.910788 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2320 00:27:20.917291 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2321 00:27:20.920931 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2322 00:27:20.923961 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2323 00:27:20.927500 ===================================
2324 00:27:20.931020 LPDDR4 DRAM CONFIGURATION
2325 00:27:20.934101 ===================================
2326 00:27:20.934495 EX_ROW_EN[0] = 0x0
2327 00:27:20.937694 EX_ROW_EN[1] = 0x0
2328 00:27:20.938085 LP4Y_EN = 0x0
2329 00:27:20.940816 WORK_FSP = 0x0
2330 00:27:20.944408 WL = 0x4
2331 00:27:20.944840 RL = 0x4
2332 00:27:20.947573 BL = 0x2
2333 00:27:20.947964 RPST = 0x0
2334 00:27:20.951325 RD_PRE = 0x0
2335 00:27:20.951713 WR_PRE = 0x1
2336 00:27:20.954190 WR_PST = 0x0
2337 00:27:20.954575 DBI_WR = 0x0
2338 00:27:20.957430 DBI_RD = 0x0
2339 00:27:20.957820 OTF = 0x1
2340 00:27:20.961012 ===================================
2341 00:27:20.964343 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2342 00:27:20.970997 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2343 00:27:20.974496 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2344 00:27:20.977569 ===================================
2345 00:27:20.981072 LPDDR4 DRAM CONFIGURATION
2346 00:27:20.984278 ===================================
2347 00:27:20.984848 EX_ROW_EN[0] = 0x10
2348 00:27:20.987683 EX_ROW_EN[1] = 0x0
2349 00:27:20.988075 LP4Y_EN = 0x0
2350 00:27:20.991212 WORK_FSP = 0x0
2351 00:27:20.991632 WL = 0x4
2352 00:27:20.994416 RL = 0x4
2353 00:27:20.994823 BL = 0x2
2354 00:27:20.997710 RPST = 0x0
2355 00:27:20.998100 RD_PRE = 0x0
2356 00:27:21.001240 WR_PRE = 0x1
2357 00:27:21.001642 WR_PST = 0x0
2358 00:27:21.004329 DBI_WR = 0x0
2359 00:27:21.004896 DBI_RD = 0x0
2360 00:27:21.007976 OTF = 0x1
2361 00:27:21.011465 ===================================
2362 00:27:21.017660 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2363 00:27:21.018061 ==
2364 00:27:21.021437 Dram Type= 6, Freq= 0, CH_0, rank 0
2365 00:27:21.024984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2366 00:27:21.025423 ==
2367 00:27:21.028164 [Duty_Offset_Calibration]
2368 00:27:21.028586 B0:2 B1:0 CA:1
2369 00:27:21.028989
2370 00:27:21.031129 [DutyScan_Calibration_Flow] k_type=0
2371 00:27:21.041223
2372 00:27:21.041612 ==CLK 0==
2373 00:27:21.044118 Final CLK duty delay cell = -4
2374 00:27:21.047720 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2375 00:27:21.050645 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2376 00:27:21.053862 [-4] AVG Duty = 4953%(X100)
2377 00:27:21.054029
2378 00:27:21.057280 CH0 CLK Duty spec in!! Max-Min= 156%
2379 00:27:21.060742 [DutyScan_Calibration_Flow] ====Done====
2380 00:27:21.060911
2381 00:27:21.063862 [DutyScan_Calibration_Flow] k_type=1
2382 00:27:21.079594
2383 00:27:21.079672 ==DQS 0 ==
2384 00:27:21.082510 Final DQS duty delay cell = 0
2385 00:27:21.085862 [0] MAX Duty = 5187%(X100), DQS PI = 30
2386 00:27:21.089116 [0] MIN Duty = 4938%(X100), DQS PI = 0
2387 00:27:21.089207 [0] AVG Duty = 5062%(X100)
2388 00:27:21.092950
2389 00:27:21.093338 ==DQS 1 ==
2390 00:27:21.096653 Final DQS duty delay cell = -4
2391 00:27:21.100116 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2392 00:27:21.102938 [-4] MIN Duty = 4907%(X100), DQS PI = 8
2393 00:27:21.106554 [-4] AVG Duty = 5015%(X100)
2394 00:27:21.107060
2395 00:27:21.109873 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2396 00:27:21.110265
2397 00:27:21.113436 CH0 DQS 1 Duty spec in!! Max-Min= 217%
2398 00:27:21.116629 [DutyScan_Calibration_Flow] ====Done====
2399 00:27:21.117093
2400 00:27:21.120014 [DutyScan_Calibration_Flow] k_type=3
2401 00:27:21.136512
2402 00:27:21.137086 ==DQM 0 ==
2403 00:27:21.139994 Final DQM duty delay cell = 0
2404 00:27:21.143163 [0] MAX Duty = 5062%(X100), DQS PI = 24
2405 00:27:21.146687 [0] MIN Duty = 4813%(X100), DQS PI = 0
2406 00:27:21.147291 [0] AVG Duty = 4937%(X100)
2407 00:27:21.150066
2408 00:27:21.150580 ==DQM 1 ==
2409 00:27:21.153130 Final DQM duty delay cell = 0
2410 00:27:21.156741 [0] MAX Duty = 5187%(X100), DQS PI = 48
2411 00:27:21.160077 [0] MIN Duty = 5000%(X100), DQS PI = 12
2412 00:27:21.160649 [0] AVG Duty = 5093%(X100)
2413 00:27:21.161183
2414 00:27:21.166732 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2415 00:27:21.167176
2416 00:27:21.169827 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2417 00:27:21.173348 [DutyScan_Calibration_Flow] ====Done====
2418 00:27:21.173735
2419 00:27:21.176399 [DutyScan_Calibration_Flow] k_type=2
2420 00:27:21.192610
2421 00:27:21.192919 ==DQ 0 ==
2422 00:27:21.196069 Final DQ duty delay cell = -4
2423 00:27:21.199532 [-4] MAX Duty = 5031%(X100), DQS PI = 34
2424 00:27:21.203077 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2425 00:27:21.206184 [-4] AVG Duty = 4953%(X100)
2426 00:27:21.206475
2427 00:27:21.206721 ==DQ 1 ==
2428 00:27:21.209648 Final DQ duty delay cell = 4
2429 00:27:21.212700 [4] MAX Duty = 5093%(X100), DQS PI = 4
2430 00:27:21.215845 [4] MIN Duty = 5031%(X100), DQS PI = 0
2431 00:27:21.215921 [4] AVG Duty = 5062%(X100)
2432 00:27:21.215989
2433 00:27:21.219321 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2434 00:27:21.222980
2435 00:27:21.226654 CH0 DQ 1 Duty spec in!! Max-Min= 62%
2436 00:27:21.230093 [DutyScan_Calibration_Flow] ====Done====
2437 00:27:21.230594 ==
2438 00:27:21.232984 Dram Type= 6, Freq= 0, CH_1, rank 0
2439 00:27:21.236615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2440 00:27:21.237068 ==
2441 00:27:21.240071 [Duty_Offset_Calibration]
2442 00:27:21.240460 B0:0 B1:-1 CA:2
2443 00:27:21.240805
2444 00:27:21.243232 [DutyScan_Calibration_Flow] k_type=0
2445 00:27:21.253348
2446 00:27:21.253783 ==CLK 0==
2447 00:27:21.256375 Final CLK duty delay cell = 0
2448 00:27:21.260315 [0] MAX Duty = 5156%(X100), DQS PI = 16
2449 00:27:21.262801 [0] MIN Duty = 4938%(X100), DQS PI = 44
2450 00:27:21.266370 [0] AVG Duty = 5047%(X100)
2451 00:27:21.266755
2452 00:27:21.269434 CH1 CLK Duty spec in!! Max-Min= 218%
2453 00:27:21.273190 [DutyScan_Calibration_Flow] ====Done====
2454 00:27:21.273572
2455 00:27:21.276262 [DutyScan_Calibration_Flow] k_type=1
2456 00:27:21.292605
2457 00:27:21.293086 ==DQS 0 ==
2458 00:27:21.295666 Final DQS duty delay cell = 0
2459 00:27:21.299244 [0] MAX Duty = 5093%(X100), DQS PI = 24
2460 00:27:21.302685 [0] MIN Duty = 4969%(X100), DQS PI = 0
2461 00:27:21.303141 [0] AVG Duty = 5031%(X100)
2462 00:27:21.303550
2463 00:27:21.306135 ==DQS 1 ==
2464 00:27:21.309575 Final DQS duty delay cell = 0
2465 00:27:21.313054 [0] MAX Duty = 5156%(X100), DQS PI = 0
2466 00:27:21.316216 [0] MIN Duty = 4844%(X100), DQS PI = 36
2467 00:27:21.316602 [0] AVG Duty = 5000%(X100)
2468 00:27:21.316940
2469 00:27:21.319463 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2470 00:27:21.322942
2471 00:27:21.326002 CH1 DQS 1 Duty spec in!! Max-Min= 312%
2472 00:27:21.329794 [DutyScan_Calibration_Flow] ====Done====
2473 00:27:21.330183
2474 00:27:21.332455 [DutyScan_Calibration_Flow] k_type=3
2475 00:27:21.349075
2476 00:27:21.349465 ==DQM 0 ==
2477 00:27:21.352596 Final DQM duty delay cell = 4
2478 00:27:21.355736 [4] MAX Duty = 5093%(X100), DQS PI = 22
2479 00:27:21.359219 [4] MIN Duty = 4907%(X100), DQS PI = 46
2480 00:27:21.359617 [4] AVG Duty = 5000%(X100)
2481 00:27:21.362408
2482 00:27:21.362794 ==DQM 1 ==
2483 00:27:21.365847 Final DQM duty delay cell = -4
2484 00:27:21.369300 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2485 00:27:21.372776 [-4] MIN Duty = 4720%(X100), DQS PI = 36
2486 00:27:21.376010 [-4] AVG Duty = 4860%(X100)
2487 00:27:21.376489
2488 00:27:21.379259 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2489 00:27:21.379735
2490 00:27:21.382685 CH1 DQM 1 Duty spec in!! Max-Min= 280%
2491 00:27:21.385908 [DutyScan_Calibration_Flow] ====Done====
2492 00:27:21.386379
2493 00:27:21.389627 [DutyScan_Calibration_Flow] k_type=2
2494 00:27:21.406102
2495 00:27:21.406653 ==DQ 0 ==
2496 00:27:21.409372 Final DQ duty delay cell = 0
2497 00:27:21.413142 [0] MAX Duty = 5062%(X100), DQS PI = 20
2498 00:27:21.416738 [0] MIN Duty = 4938%(X100), DQS PI = 0
2499 00:27:21.417218 [0] AVG Duty = 5000%(X100)
2500 00:27:21.417648
2501 00:27:21.419589 ==DQ 1 ==
2502 00:27:21.422993 Final DQ duty delay cell = 0
2503 00:27:21.425974 [0] MAX Duty = 5031%(X100), DQS PI = 2
2504 00:27:21.429450 [0] MIN Duty = 4813%(X100), DQS PI = 34
2505 00:27:21.429907 [0] AVG Duty = 4922%(X100)
2506 00:27:21.430226
2507 00:27:21.432935 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2508 00:27:21.433398
2509 00:27:21.436126 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2510 00:27:21.442445 [DutyScan_Calibration_Flow] ====Done====
2511 00:27:21.446187 nWR fixed to 30
2512 00:27:21.446618 [ModeRegInit_LP4] CH0 RK0
2513 00:27:21.449411 [ModeRegInit_LP4] CH0 RK1
2514 00:27:21.453068 [ModeRegInit_LP4] CH1 RK0
2515 00:27:21.453471 [ModeRegInit_LP4] CH1 RK1
2516 00:27:21.456334 match AC timing 7
2517 00:27:21.459546 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2518 00:27:21.463022 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2519 00:27:21.469660 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2520 00:27:21.472802 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2521 00:27:21.479521 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2522 00:27:21.480000 ==
2523 00:27:21.483217 Dram Type= 6, Freq= 0, CH_0, rank 0
2524 00:27:21.486169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2525 00:27:21.486622 ==
2526 00:27:21.492990 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2527 00:27:21.496463 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
2528 00:27:21.506390 [CA 0] Center 38 (8~69) winsize 62
2529 00:27:21.509299 [CA 1] Center 38 (7~69) winsize 63
2530 00:27:21.512596 [CA 2] Center 35 (5~66) winsize 62
2531 00:27:21.515963 [CA 3] Center 34 (4~65) winsize 62
2532 00:27:21.519179 [CA 4] Center 34 (4~65) winsize 62
2533 00:27:21.522777 [CA 5] Center 33 (3~63) winsize 61
2534 00:27:21.523251
2535 00:27:21.525860 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2536 00:27:21.526347
2537 00:27:21.529369 [CATrainingPosCal] consider 1 rank data
2538 00:27:21.532540 u2DelayCellTimex100 = 270/100 ps
2539 00:27:21.536054 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2540 00:27:21.539070 CA1 delay=38 (7~69),Diff = 5 PI (24 cell)
2541 00:27:21.542847 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2542 00:27:21.549169 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
2543 00:27:21.552568 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2544 00:27:21.555981 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2545 00:27:21.556437
2546 00:27:21.559392 CA PerBit enable=1, Macro0, CA PI delay=33
2547 00:27:21.559965
2548 00:27:21.562805 [CBTSetCACLKResult] CA Dly = 33
2549 00:27:21.563239 CS Dly: 6 (0~37)
2550 00:27:21.563573 ==
2551 00:27:21.566008 Dram Type= 6, Freq= 0, CH_0, rank 1
2552 00:27:21.572927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2553 00:27:21.573511 ==
2554 00:27:21.576318 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2555 00:27:21.582970 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2556 00:27:21.591774 [CA 0] Center 39 (8~70) winsize 63
2557 00:27:21.595064 [CA 1] Center 38 (8~69) winsize 62
2558 00:27:21.598350 [CA 2] Center 35 (5~66) winsize 62
2559 00:27:21.601752 [CA 3] Center 35 (5~66) winsize 62
2560 00:27:21.605088 [CA 4] Center 34 (4~65) winsize 62
2561 00:27:21.608619 [CA 5] Center 34 (4~64) winsize 61
2562 00:27:21.609180
2563 00:27:21.612228 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2564 00:27:21.612799
2565 00:27:21.614941 [CATrainingPosCal] consider 2 rank data
2566 00:27:21.618546 u2DelayCellTimex100 = 270/100 ps
2567 00:27:21.622066 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2568 00:27:21.624974 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2569 00:27:21.628488 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2570 00:27:21.634786 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2571 00:27:21.638526 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2572 00:27:21.641725 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2573 00:27:21.642164
2574 00:27:21.644947 CA PerBit enable=1, Macro0, CA PI delay=33
2575 00:27:21.645477
2576 00:27:21.648228 [CBTSetCACLKResult] CA Dly = 33
2577 00:27:21.648663 CS Dly: 7 (0~39)
2578 00:27:21.649087
2579 00:27:21.651561 ----->DramcWriteLeveling(PI) begin...
2580 00:27:21.651904 ==
2581 00:27:21.654877 Dram Type= 6, Freq= 0, CH_0, rank 0
2582 00:27:21.661445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2583 00:27:21.661867 ==
2584 00:27:21.664765 Write leveling (Byte 0): 34 => 34
2585 00:27:21.668423 Write leveling (Byte 1): 30 => 30
2586 00:27:21.668924 DramcWriteLeveling(PI) end<-----
2587 00:27:21.669187
2588 00:27:21.671305 ==
2589 00:27:21.675026 Dram Type= 6, Freq= 0, CH_0, rank 0
2590 00:27:21.677937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2591 00:27:21.678121 ==
2592 00:27:21.681626 [Gating] SW mode calibration
2593 00:27:21.687995 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2594 00:27:21.691654 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2595 00:27:21.698289 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2596 00:27:21.701393 0 15 4 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
2597 00:27:21.705033 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2598 00:27:21.711489 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2599 00:27:21.715112 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2600 00:27:21.718167 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2601 00:27:21.724826 0 15 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
2602 00:27:21.728376 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
2603 00:27:21.731312 1 0 0 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (0 0)
2604 00:27:21.738154 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2605 00:27:21.741318 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2606 00:27:21.745123 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2607 00:27:21.748087 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2608 00:27:21.754834 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2609 00:27:21.758086 1 0 24 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
2610 00:27:21.761242 1 0 28 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
2611 00:27:21.768410 1 1 0 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
2612 00:27:21.771600 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2613 00:27:21.774942 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2614 00:27:21.781648 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2615 00:27:21.784855 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2616 00:27:21.788102 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2617 00:27:21.795141 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2618 00:27:21.798143 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2619 00:27:21.801824 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2620 00:27:21.807974 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 00:27:21.811617 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 00:27:21.814647 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 00:27:21.821772 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 00:27:21.824897 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 00:27:21.827924 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 00:27:21.834877 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 00:27:21.837956 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2628 00:27:21.841654 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2629 00:27:21.845030 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2630 00:27:21.851596 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2631 00:27:21.854932 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2632 00:27:21.858300 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2633 00:27:21.864967 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2634 00:27:21.868491 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2635 00:27:21.871386 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2636 00:27:21.874971 Total UI for P1: 0, mck2ui 16
2637 00:27:21.878135 best dqsien dly found for B0: ( 1, 3, 26)
2638 00:27:21.885138 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2639 00:27:21.885242 Total UI for P1: 0, mck2ui 16
2640 00:27:21.891486 best dqsien dly found for B1: ( 1, 3, 30)
2641 00:27:21.895159 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2642 00:27:21.898240 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2643 00:27:21.898319
2644 00:27:21.901582 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2645 00:27:21.905025 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2646 00:27:21.908447 [Gating] SW calibration Done
2647 00:27:21.908523 ==
2648 00:27:21.911418 Dram Type= 6, Freq= 0, CH_0, rank 0
2649 00:27:21.915085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2650 00:27:21.915163 ==
2651 00:27:21.918154 RX Vref Scan: 0
2652 00:27:21.918230
2653 00:27:21.918289 RX Vref 0 -> 0, step: 1
2654 00:27:21.918344
2655 00:27:21.921952 RX Delay -40 -> 252, step: 8
2656 00:27:21.924897 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
2657 00:27:21.931802 iDelay=208, Bit 1, Center 123 (56 ~ 191) 136
2658 00:27:21.935259 iDelay=208, Bit 2, Center 119 (48 ~ 191) 144
2659 00:27:21.938686 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
2660 00:27:21.942060 iDelay=208, Bit 4, Center 127 (56 ~ 199) 144
2661 00:27:21.945460 iDelay=208, Bit 5, Center 115 (48 ~ 183) 136
2662 00:27:21.948673 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
2663 00:27:21.955721 iDelay=208, Bit 7, Center 127 (56 ~ 199) 144
2664 00:27:21.958836 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
2665 00:27:21.962210 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
2666 00:27:21.965377 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
2667 00:27:21.968967 iDelay=208, Bit 11, Center 107 (40 ~ 175) 136
2668 00:27:21.975387 iDelay=208, Bit 12, Center 115 (48 ~ 183) 136
2669 00:27:21.978851 iDelay=208, Bit 13, Center 115 (48 ~ 183) 136
2670 00:27:21.982411 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
2671 00:27:21.985675 iDelay=208, Bit 15, Center 115 (48 ~ 183) 136
2672 00:27:21.986142 ==
2673 00:27:21.988795 Dram Type= 6, Freq= 0, CH_0, rank 0
2674 00:27:21.996138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2675 00:27:21.996625 ==
2676 00:27:21.997103 DQS Delay:
2677 00:27:21.997517 DQS0 = 0, DQS1 = 0
2678 00:27:21.998808 DQM Delay:
2679 00:27:21.999208 DQM0 = 123, DQM1 = 110
2680 00:27:22.001959 DQ Delay:
2681 00:27:22.005709 DQ0 =123, DQ1 =123, DQ2 =119, DQ3 =119
2682 00:27:22.009093 DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =127
2683 00:27:22.012132 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2684 00:27:22.015649 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2685 00:27:22.016140
2686 00:27:22.016547
2687 00:27:22.016976 ==
2688 00:27:22.018693 Dram Type= 6, Freq= 0, CH_0, rank 0
2689 00:27:22.022399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2690 00:27:22.022882 ==
2691 00:27:22.023289
2692 00:27:22.025473
2693 00:27:22.025871 TX Vref Scan disable
2694 00:27:22.029217 == TX Byte 0 ==
2695 00:27:22.032067 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2696 00:27:22.035634 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2697 00:27:22.038627 == TX Byte 1 ==
2698 00:27:22.042198 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2699 00:27:22.045792 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2700 00:27:22.046180 ==
2701 00:27:22.048832 Dram Type= 6, Freq= 0, CH_0, rank 0
2702 00:27:22.055336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2703 00:27:22.055812 ==
2704 00:27:22.065962 TX Vref=22, minBit 0, minWin=23, winSum=399
2705 00:27:22.069844 TX Vref=24, minBit 3, minWin=24, winSum=408
2706 00:27:22.072804 TX Vref=26, minBit 0, minWin=24, winSum=412
2707 00:27:22.076241 TX Vref=28, minBit 7, minWin=24, winSum=416
2708 00:27:22.079643 TX Vref=30, minBit 4, minWin=25, winSum=421
2709 00:27:22.083274 TX Vref=32, minBit 1, minWin=24, winSum=418
2710 00:27:22.089639 [TxChooseVref] Worse bit 4, Min win 25, Win sum 421, Final Vref 30
2711 00:27:22.090033
2712 00:27:22.093385 Final TX Range 1 Vref 30
2713 00:27:22.093874
2714 00:27:22.094206 ==
2715 00:27:22.096176 Dram Type= 6, Freq= 0, CH_0, rank 0
2716 00:27:22.099449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2717 00:27:22.099844 ==
2718 00:27:22.100152
2719 00:27:22.100452
2720 00:27:22.102820 TX Vref Scan disable
2721 00:27:22.106762 == TX Byte 0 ==
2722 00:27:22.109446 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2723 00:27:22.112804 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2724 00:27:22.116076 == TX Byte 1 ==
2725 00:27:22.119732 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2726 00:27:22.123080 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2727 00:27:22.123560
2728 00:27:22.126669 [DATLAT]
2729 00:27:22.127188 Freq=1200, CH0 RK0
2730 00:27:22.127512
2731 00:27:22.130012 DATLAT Default: 0xd
2732 00:27:22.130527 0, 0xFFFF, sum = 0
2733 00:27:22.132830 1, 0xFFFF, sum = 0
2734 00:27:22.133229 2, 0xFFFF, sum = 0
2735 00:27:22.136491 3, 0xFFFF, sum = 0
2736 00:27:22.136952 4, 0xFFFF, sum = 0
2737 00:27:22.139490 5, 0xFFFF, sum = 0
2738 00:27:22.139885 6, 0xFFFF, sum = 0
2739 00:27:22.143212 7, 0xFFFF, sum = 0
2740 00:27:22.143606 8, 0xFFFF, sum = 0
2741 00:27:22.146596 9, 0xFFFF, sum = 0
2742 00:27:22.147116 10, 0xFFFF, sum = 0
2743 00:27:22.149824 11, 0xFFFF, sum = 0
2744 00:27:22.153036 12, 0x0, sum = 1
2745 00:27:22.153432 13, 0x0, sum = 2
2746 00:27:22.153786 14, 0x0, sum = 3
2747 00:27:22.156515 15, 0x0, sum = 4
2748 00:27:22.157003 best_step = 13
2749 00:27:22.157311
2750 00:27:22.157590 ==
2751 00:27:22.159677 Dram Type= 6, Freq= 0, CH_0, rank 0
2752 00:27:22.166238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2753 00:27:22.166676 ==
2754 00:27:22.167023 RX Vref Scan: 1
2755 00:27:22.167313
2756 00:27:22.169980 Set Vref Range= 32 -> 127
2757 00:27:22.170470
2758 00:27:22.173088 RX Vref 32 -> 127, step: 1
2759 00:27:22.173494
2760 00:27:22.176558 RX Delay -13 -> 252, step: 4
2761 00:27:22.177035
2762 00:27:22.179613 Set Vref, RX VrefLevel [Byte0]: 32
2763 00:27:22.180007 [Byte1]: 32
2764 00:27:22.183971
2765 00:27:22.184360 Set Vref, RX VrefLevel [Byte0]: 33
2766 00:27:22.187490 [Byte1]: 33
2767 00:27:22.192435
2768 00:27:22.192984 Set Vref, RX VrefLevel [Byte0]: 34
2769 00:27:22.195764 [Byte1]: 34
2770 00:27:22.200207
2771 00:27:22.200597 Set Vref, RX VrefLevel [Byte0]: 35
2772 00:27:22.203435 [Byte1]: 35
2773 00:27:22.208007
2774 00:27:22.208445 Set Vref, RX VrefLevel [Byte0]: 36
2775 00:27:22.211608 [Byte1]: 36
2776 00:27:22.216272
2777 00:27:22.216815 Set Vref, RX VrefLevel [Byte0]: 37
2778 00:27:22.219577 [Byte1]: 37
2779 00:27:22.223855
2780 00:27:22.224247 Set Vref, RX VrefLevel [Byte0]: 38
2781 00:27:22.227236 [Byte1]: 38
2782 00:27:22.231696
2783 00:27:22.232133 Set Vref, RX VrefLevel [Byte0]: 39
2784 00:27:22.234989 [Byte1]: 39
2785 00:27:22.239389
2786 00:27:22.239798 Set Vref, RX VrefLevel [Byte0]: 40
2787 00:27:22.243027 [Byte1]: 40
2788 00:27:22.247740
2789 00:27:22.248200 Set Vref, RX VrefLevel [Byte0]: 41
2790 00:27:22.250795 [Byte1]: 41
2791 00:27:22.255759
2792 00:27:22.256248 Set Vref, RX VrefLevel [Byte0]: 42
2793 00:27:22.258543 [Byte1]: 42
2794 00:27:22.263597
2795 00:27:22.264077 Set Vref, RX VrefLevel [Byte0]: 43
2796 00:27:22.266295 [Byte1]: 43
2797 00:27:22.271649
2798 00:27:22.272124 Set Vref, RX VrefLevel [Byte0]: 44
2799 00:27:22.274621 [Byte1]: 44
2800 00:27:22.279386
2801 00:27:22.279863 Set Vref, RX VrefLevel [Byte0]: 45
2802 00:27:22.282897 [Byte1]: 45
2803 00:27:22.287323
2804 00:27:22.287715 Set Vref, RX VrefLevel [Byte0]: 46
2805 00:27:22.290244 [Byte1]: 46
2806 00:27:22.294649
2807 00:27:22.295239 Set Vref, RX VrefLevel [Byte0]: 47
2808 00:27:22.298064 [Byte1]: 47
2809 00:27:22.302626
2810 00:27:22.303026 Set Vref, RX VrefLevel [Byte0]: 48
2811 00:27:22.305871 [Byte1]: 48
2812 00:27:22.310541
2813 00:27:22.310930 Set Vref, RX VrefLevel [Byte0]: 49
2814 00:27:22.313969 [Byte1]: 49
2815 00:27:22.318833
2816 00:27:22.319317 Set Vref, RX VrefLevel [Byte0]: 50
2817 00:27:22.321855 [Byte1]: 50
2818 00:27:22.326388
2819 00:27:22.326830 Set Vref, RX VrefLevel [Byte0]: 51
2820 00:27:22.329918 [Byte1]: 51
2821 00:27:22.334014
2822 00:27:22.334427 Set Vref, RX VrefLevel [Byte0]: 52
2823 00:27:22.337695 [Byte1]: 52
2824 00:27:22.342173
2825 00:27:22.342587 Set Vref, RX VrefLevel [Byte0]: 53
2826 00:27:22.345245 [Byte1]: 53
2827 00:27:22.350173
2828 00:27:22.350575 Set Vref, RX VrefLevel [Byte0]: 54
2829 00:27:22.353304 [Byte1]: 54
2830 00:27:22.358262
2831 00:27:22.358777 Set Vref, RX VrefLevel [Byte0]: 55
2832 00:27:22.361129 [Byte1]: 55
2833 00:27:22.365628
2834 00:27:22.366060 Set Vref, RX VrefLevel [Byte0]: 56
2835 00:27:22.369161 [Byte1]: 56
2836 00:27:22.373381
2837 00:27:22.373781 Set Vref, RX VrefLevel [Byte0]: 57
2838 00:27:22.377197 [Byte1]: 57
2839 00:27:22.382012
2840 00:27:22.382411 Set Vref, RX VrefLevel [Byte0]: 58
2841 00:27:22.384872 [Byte1]: 58
2842 00:27:22.389599
2843 00:27:22.390049 Set Vref, RX VrefLevel [Byte0]: 59
2844 00:27:22.392590 [Byte1]: 59
2845 00:27:22.397367
2846 00:27:22.397764 Set Vref, RX VrefLevel [Byte0]: 60
2847 00:27:22.401197 [Byte1]: 60
2848 00:27:22.405058
2849 00:27:22.405462 Set Vref, RX VrefLevel [Byte0]: 61
2850 00:27:22.408794 [Byte1]: 61
2851 00:27:22.413448
2852 00:27:22.413849 Set Vref, RX VrefLevel [Byte0]: 62
2853 00:27:22.416585 [Byte1]: 62
2854 00:27:22.421308
2855 00:27:22.421862 Set Vref, RX VrefLevel [Byte0]: 63
2856 00:27:22.424531 [Byte1]: 63
2857 00:27:22.429001
2858 00:27:22.429495 Set Vref, RX VrefLevel [Byte0]: 64
2859 00:27:22.431960 [Byte1]: 64
2860 00:27:22.436866
2861 00:27:22.437256 Set Vref, RX VrefLevel [Byte0]: 65
2862 00:27:22.440092 [Byte1]: 65
2863 00:27:22.444664
2864 00:27:22.445318 Set Vref, RX VrefLevel [Byte0]: 66
2865 00:27:22.448022 [Byte1]: 66
2866 00:27:22.452795
2867 00:27:22.453194 Set Vref, RX VrefLevel [Byte0]: 67
2868 00:27:22.455798 [Byte1]: 67
2869 00:27:22.460480
2870 00:27:22.460984 Set Vref, RX VrefLevel [Byte0]: 68
2871 00:27:22.463910 [Byte1]: 68
2872 00:27:22.468465
2873 00:27:22.468963 Set Vref, RX VrefLevel [Byte0]: 69
2874 00:27:22.471722 [Byte1]: 69
2875 00:27:22.476255
2876 00:27:22.476643 Set Vref, RX VrefLevel [Byte0]: 70
2877 00:27:22.479979 [Byte1]: 70
2878 00:27:22.483840
2879 00:27:22.484233 Set Vref, RX VrefLevel [Byte0]: 71
2880 00:27:22.487228 [Byte1]: 71
2881 00:27:22.491791
2882 00:27:22.492178 Final RX Vref Byte 0 = 60 to rank0
2883 00:27:22.495225 Final RX Vref Byte 1 = 48 to rank0
2884 00:27:22.498903 Final RX Vref Byte 0 = 60 to rank1
2885 00:27:22.502004 Final RX Vref Byte 1 = 48 to rank1==
2886 00:27:22.505003 Dram Type= 6, Freq= 0, CH_0, rank 0
2887 00:27:22.511957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2888 00:27:22.512127 ==
2889 00:27:22.512260 DQS Delay:
2890 00:27:22.512382 DQS0 = 0, DQS1 = 0
2891 00:27:22.515319 DQM Delay:
2892 00:27:22.515459 DQM0 = 123, DQM1 = 109
2893 00:27:22.518544 DQ Delay:
2894 00:27:22.521663 DQ0 =122, DQ1 =122, DQ2 =120, DQ3 =120
2895 00:27:22.525099 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2896 00:27:22.528536 DQ8 =100, DQ9 =94, DQ10 =110, DQ11 =106
2897 00:27:22.531770 DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =116
2898 00:27:22.531877
2899 00:27:22.531952
2900 00:27:22.538292 [DQSOSCAuto] RK0, (LSB)MR18= 0xa06, (MSB)MR19= 0x404, tDQSOscB0 = 407 ps tDQSOscB1 = 406 ps
2901 00:27:22.541931 CH0 RK0: MR19=404, MR18=A06
2902 00:27:22.548530 CH0_RK0: MR19=0x404, MR18=0xA06, DQSOSC=406, MR23=63, INC=39, DEC=26
2903 00:27:22.548667
2904 00:27:22.551729 ----->DramcWriteLeveling(PI) begin...
2905 00:27:22.551826 ==
2906 00:27:22.555198 Dram Type= 6, Freq= 0, CH_0, rank 1
2907 00:27:22.558196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2908 00:27:22.558309 ==
2909 00:27:22.561873 Write leveling (Byte 0): 34 => 34
2910 00:27:22.565225 Write leveling (Byte 1): 29 => 29
2911 00:27:22.568618 DramcWriteLeveling(PI) end<-----
2912 00:27:22.568721
2913 00:27:22.568784 ==
2914 00:27:22.571820 Dram Type= 6, Freq= 0, CH_0, rank 1
2915 00:27:22.574969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2916 00:27:22.578402 ==
2917 00:27:22.578479 [Gating] SW mode calibration
2918 00:27:22.584950 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2919 00:27:22.591924 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2920 00:27:22.595114 0 15 0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
2921 00:27:22.602189 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2922 00:27:22.605434 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2923 00:27:22.609042 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2924 00:27:22.615582 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2925 00:27:22.619060 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2926 00:27:22.622001 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2927 00:27:22.625667 0 15 28 | B1->B0 | 3333 2d2d | 1 1 | (1 0) (1 0)
2928 00:27:22.632351 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
2929 00:27:22.635860 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2930 00:27:22.638833 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2931 00:27:22.645319 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2932 00:27:22.648853 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2933 00:27:22.652332 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2934 00:27:22.658888 1 0 24 | B1->B0 | 2525 2525 | 1 1 | (0 0) (0 0)
2935 00:27:22.662069 1 0 28 | B1->B0 | 3d3d 4343 | 0 0 | (0 0) (0 0)
2936 00:27:22.665652 1 1 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
2937 00:27:22.672047 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2938 00:27:22.675478 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2939 00:27:22.679016 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2940 00:27:22.685578 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2941 00:27:22.689064 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2942 00:27:22.692447 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2943 00:27:22.699072 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2944 00:27:22.702201 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
2945 00:27:22.705524 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2946 00:27:22.708922 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2947 00:27:22.715465 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2948 00:27:22.718584 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2949 00:27:22.721859 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2950 00:27:22.728584 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2951 00:27:22.731710 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2952 00:27:22.735293 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2953 00:27:22.742280 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2954 00:27:22.745344 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2955 00:27:22.748883 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2956 00:27:22.755142 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2957 00:27:22.758735 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2958 00:27:22.762068 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2959 00:27:22.769082 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2960 00:27:22.771897 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2961 00:27:22.775386 Total UI for P1: 0, mck2ui 16
2962 00:27:22.778904 best dqsien dly found for B0: ( 1, 3, 26)
2963 00:27:22.782222 Total UI for P1: 0, mck2ui 16
2964 00:27:22.785737 best dqsien dly found for B1: ( 1, 3, 30)
2965 00:27:22.788924 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2966 00:27:22.792367 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2967 00:27:22.792444
2968 00:27:22.795400 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2969 00:27:22.798945 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2970 00:27:22.802106 [Gating] SW calibration Done
2971 00:27:22.802184 ==
2972 00:27:22.805635 Dram Type= 6, Freq= 0, CH_0, rank 1
2973 00:27:22.809095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2974 00:27:22.809176 ==
2975 00:27:22.812534 RX Vref Scan: 0
2976 00:27:22.812611
2977 00:27:22.815575 RX Vref 0 -> 0, step: 1
2978 00:27:22.815652
2979 00:27:22.815712 RX Delay -40 -> 252, step: 8
2980 00:27:22.821966 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2981 00:27:22.825346 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2982 00:27:22.828913 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2983 00:27:22.832406 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2984 00:27:22.835344 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2985 00:27:22.842345 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2986 00:27:22.845476 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2987 00:27:22.848871 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2988 00:27:22.852379 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2989 00:27:22.855415 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2990 00:27:22.862173 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2991 00:27:22.865940 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2992 00:27:22.868961 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2993 00:27:22.872232 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2994 00:27:22.875495 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2995 00:27:22.882379 iDelay=200, Bit 15, Center 111 (48 ~ 175) 128
2996 00:27:22.882466 ==
2997 00:27:22.885843 Dram Type= 6, Freq= 0, CH_0, rank 1
2998 00:27:22.889049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2999 00:27:22.889128 ==
3000 00:27:22.889188 DQS Delay:
3001 00:27:22.892324 DQS0 = 0, DQS1 = 0
3002 00:27:22.892401 DQM Delay:
3003 00:27:22.895764 DQM0 = 120, DQM1 = 108
3004 00:27:22.895865 DQ Delay:
3005 00:27:22.899564 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
3006 00:27:22.902508 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
3007 00:27:22.905968 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
3008 00:27:22.909437 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
3009 00:27:22.909517
3010 00:27:22.909577
3011 00:27:22.909633 ==
3012 00:27:22.912431 Dram Type= 6, Freq= 0, CH_0, rank 1
3013 00:27:22.919525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3014 00:27:22.919609 ==
3015 00:27:22.919670
3016 00:27:22.919724
3017 00:27:22.919777 TX Vref Scan disable
3018 00:27:22.922480 == TX Byte 0 ==
3019 00:27:22.925973 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3020 00:27:22.929327 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3021 00:27:22.932403 == TX Byte 1 ==
3022 00:27:22.936113 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3023 00:27:22.939330 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3024 00:27:22.942423 ==
3025 00:27:22.945955 Dram Type= 6, Freq= 0, CH_0, rank 1
3026 00:27:22.948974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3027 00:27:22.949054 ==
3028 00:27:22.961020 TX Vref=22, minBit 0, minWin=24, winSum=406
3029 00:27:22.964182 TX Vref=24, minBit 0, minWin=24, winSum=415
3030 00:27:22.967613 TX Vref=26, minBit 0, minWin=24, winSum=418
3031 00:27:22.970993 TX Vref=28, minBit 0, minWin=25, winSum=419
3032 00:27:22.974011 TX Vref=30, minBit 1, minWin=25, winSum=423
3033 00:27:22.977759 TX Vref=32, minBit 1, minWin=24, winSum=423
3034 00:27:22.984336 [TxChooseVref] Worse bit 1, Min win 25, Win sum 423, Final Vref 30
3035 00:27:22.984427
3036 00:27:22.987634 Final TX Range 1 Vref 30
3037 00:27:22.987718
3038 00:27:22.987780 ==
3039 00:27:22.990873 Dram Type= 6, Freq= 0, CH_0, rank 1
3040 00:27:22.993963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3041 00:27:22.994043 ==
3042 00:27:22.997243
3043 00:27:22.997320
3044 00:27:22.997380 TX Vref Scan disable
3045 00:27:23.000591 == TX Byte 0 ==
3046 00:27:23.003983 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3047 00:27:23.010654 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3048 00:27:23.010738 == TX Byte 1 ==
3049 00:27:23.013603 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3050 00:27:23.020448 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3051 00:27:23.020535
3052 00:27:23.020596 [DATLAT]
3053 00:27:23.020652 Freq=1200, CH0 RK1
3054 00:27:23.020713
3055 00:27:23.024115 DATLAT Default: 0xd
3056 00:27:23.027139 0, 0xFFFF, sum = 0
3057 00:27:23.027219 1, 0xFFFF, sum = 0
3058 00:27:23.030280 2, 0xFFFF, sum = 0
3059 00:27:23.030359 3, 0xFFFF, sum = 0
3060 00:27:23.033640 4, 0xFFFF, sum = 0
3061 00:27:23.033745 5, 0xFFFF, sum = 0
3062 00:27:23.037140 6, 0xFFFF, sum = 0
3063 00:27:23.037220 7, 0xFFFF, sum = 0
3064 00:27:23.040274 8, 0xFFFF, sum = 0
3065 00:27:23.040352 9, 0xFFFF, sum = 0
3066 00:27:23.043879 10, 0xFFFF, sum = 0
3067 00:27:23.043962 11, 0xFFFF, sum = 0
3068 00:27:23.046929 12, 0x0, sum = 1
3069 00:27:23.047008 13, 0x0, sum = 2
3070 00:27:23.050464 14, 0x0, sum = 3
3071 00:27:23.050553 15, 0x0, sum = 4
3072 00:27:23.053460 best_step = 13
3073 00:27:23.053538
3074 00:27:23.053599 ==
3075 00:27:23.056923 Dram Type= 6, Freq= 0, CH_0, rank 1
3076 00:27:23.060415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3077 00:27:23.060494 ==
3078 00:27:23.060555 RX Vref Scan: 0
3079 00:27:23.063497
3080 00:27:23.063575 RX Vref 0 -> 0, step: 1
3081 00:27:23.063636
3082 00:27:23.067160 RX Delay -21 -> 252, step: 4
3083 00:27:23.070054 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3084 00:27:23.076698 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3085 00:27:23.080196 iDelay=195, Bit 2, Center 116 (51 ~ 182) 132
3086 00:27:23.083725 iDelay=195, Bit 3, Center 114 (47 ~ 182) 136
3087 00:27:23.087124 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3088 00:27:23.090184 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3089 00:27:23.097031 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3090 00:27:23.100295 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
3091 00:27:23.103404 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3092 00:27:23.106531 iDelay=195, Bit 9, Center 92 (27 ~ 158) 132
3093 00:27:23.110007 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3094 00:27:23.116441 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3095 00:27:23.120126 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3096 00:27:23.123519 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3097 00:27:23.126409 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3098 00:27:23.133249 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3099 00:27:23.133340 ==
3100 00:27:23.136260 Dram Type= 6, Freq= 0, CH_0, rank 1
3101 00:27:23.139664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3102 00:27:23.139747 ==
3103 00:27:23.139808 DQS Delay:
3104 00:27:23.143329 DQS0 = 0, DQS1 = 0
3105 00:27:23.143435 DQM Delay:
3106 00:27:23.146379 DQM0 = 119, DQM1 = 107
3107 00:27:23.146458 DQ Delay:
3108 00:27:23.149569 DQ0 =118, DQ1 =122, DQ2 =116, DQ3 =114
3109 00:27:23.153162 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =124
3110 00:27:23.156158 DQ8 =98, DQ9 =92, DQ10 =110, DQ11 =106
3111 00:27:23.159725 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =114
3112 00:27:23.159820
3113 00:27:23.159904
3114 00:27:23.169836 [DQSOSCAuto] RK1, (LSB)MR18= 0xdf5, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 405 ps
3115 00:27:23.172959 CH0 RK1: MR19=403, MR18=DF5
3116 00:27:23.176351 CH0_RK1: MR19=0x403, MR18=0xDF5, DQSOSC=405, MR23=63, INC=39, DEC=26
3117 00:27:23.179432 [RxdqsGatingPostProcess] freq 1200
3118 00:27:23.186073 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3119 00:27:23.189656 best DQS0 dly(2T, 0.5T) = (0, 11)
3120 00:27:23.192996 best DQS1 dly(2T, 0.5T) = (0, 11)
3121 00:27:23.196472 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3122 00:27:23.199590 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3123 00:27:23.202940 best DQS0 dly(2T, 0.5T) = (0, 11)
3124 00:27:23.206275 best DQS1 dly(2T, 0.5T) = (0, 11)
3125 00:27:23.209689 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3126 00:27:23.212958 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3127 00:27:23.213040 Pre-setting of DQS Precalculation
3128 00:27:23.219763 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3129 00:27:23.219853 ==
3130 00:27:23.222558 Dram Type= 6, Freq= 0, CH_1, rank 0
3131 00:27:23.226321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3132 00:27:23.226403 ==
3133 00:27:23.233009 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3134 00:27:23.239412 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3135 00:27:23.246810 [CA 0] Center 37 (7~68) winsize 62
3136 00:27:23.250466 [CA 1] Center 37 (7~68) winsize 62
3137 00:27:23.253480 [CA 2] Center 35 (5~65) winsize 61
3138 00:27:23.257007 [CA 3] Center 34 (4~65) winsize 62
3139 00:27:23.259988 [CA 4] Center 34 (4~64) winsize 61
3140 00:27:23.263415 [CA 5] Center 33 (3~64) winsize 62
3141 00:27:23.263496
3142 00:27:23.266869 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3143 00:27:23.266947
3144 00:27:23.269915 [CATrainingPosCal] consider 1 rank data
3145 00:27:23.273491 u2DelayCellTimex100 = 270/100 ps
3146 00:27:23.276657 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3147 00:27:23.280016 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3148 00:27:23.286821 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3149 00:27:23.290246 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3150 00:27:23.293246 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3151 00:27:23.296681 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3152 00:27:23.296808
3153 00:27:23.299787 CA PerBit enable=1, Macro0, CA PI delay=33
3154 00:27:23.299867
3155 00:27:23.303384 [CBTSetCACLKResult] CA Dly = 33
3156 00:27:23.303462 CS Dly: 5 (0~36)
3157 00:27:23.306820 ==
3158 00:27:23.306902 Dram Type= 6, Freq= 0, CH_1, rank 1
3159 00:27:23.313377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3160 00:27:23.313465 ==
3161 00:27:23.316815 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3162 00:27:23.323328 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3163 00:27:23.332482 [CA 0] Center 38 (8~68) winsize 61
3164 00:27:23.336053 [CA 1] Center 37 (7~68) winsize 62
3165 00:27:23.339191 [CA 2] Center 35 (5~66) winsize 62
3166 00:27:23.342237 [CA 3] Center 34 (4~65) winsize 62
3167 00:27:23.345711 [CA 4] Center 34 (4~65) winsize 62
3168 00:27:23.349157 [CA 5] Center 33 (3~64) winsize 62
3169 00:27:23.349238
3170 00:27:23.352256 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3171 00:27:23.352339
3172 00:27:23.355874 [CATrainingPosCal] consider 2 rank data
3173 00:27:23.358916 u2DelayCellTimex100 = 270/100 ps
3174 00:27:23.362430 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3175 00:27:23.365882 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3176 00:27:23.372374 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3177 00:27:23.375906 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3178 00:27:23.378978 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3179 00:27:23.382554 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3180 00:27:23.382627
3181 00:27:23.385920 CA PerBit enable=1, Macro0, CA PI delay=33
3182 00:27:23.385992
3183 00:27:23.388942 [CBTSetCACLKResult] CA Dly = 33
3184 00:27:23.389009 CS Dly: 6 (0~39)
3185 00:27:23.389071
3186 00:27:23.392551 ----->DramcWriteLeveling(PI) begin...
3187 00:27:23.396010 ==
3188 00:27:23.396103 Dram Type= 6, Freq= 0, CH_1, rank 0
3189 00:27:23.402277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3190 00:27:23.402386 ==
3191 00:27:23.405760 Write leveling (Byte 0): 25 => 25
3192 00:27:23.409181 Write leveling (Byte 1): 28 => 28
3193 00:27:23.412327 DramcWriteLeveling(PI) end<-----
3194 00:27:23.412422
3195 00:27:23.412505 ==
3196 00:27:23.415682 Dram Type= 6, Freq= 0, CH_1, rank 0
3197 00:27:23.419163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3198 00:27:23.419235 ==
3199 00:27:23.422172 [Gating] SW mode calibration
3200 00:27:23.428987 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3201 00:27:23.432352 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3202 00:27:23.439131 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3203 00:27:23.442005 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3204 00:27:23.445841 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3205 00:27:23.452094 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3206 00:27:23.455496 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3207 00:27:23.459085 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3208 00:27:23.465807 0 15 24 | B1->B0 | 2b2b 2424 | 0 0 | (0 0) (1 0)
3209 00:27:23.468869 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3210 00:27:23.472205 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3211 00:27:23.479392 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3212 00:27:23.482469 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3213 00:27:23.485611 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3214 00:27:23.492113 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3215 00:27:23.495402 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3216 00:27:23.499025 1 0 24 | B1->B0 | 3838 4141 | 1 1 | (0 0) (0 0)
3217 00:27:23.505399 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3218 00:27:23.509043 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3219 00:27:23.512037 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3220 00:27:23.518807 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3221 00:27:23.521933 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3222 00:27:23.525621 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3223 00:27:23.532106 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3224 00:27:23.535591 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3225 00:27:23.538789 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3226 00:27:23.542146 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3227 00:27:23.548662 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3228 00:27:23.552083 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3229 00:27:23.555445 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3230 00:27:23.562497 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3231 00:27:23.565565 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3232 00:27:23.568631 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3233 00:27:23.575513 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3234 00:27:23.578841 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3235 00:27:23.581839 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3236 00:27:23.588868 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3237 00:27:23.592011 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3238 00:27:23.595518 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3239 00:27:23.602072 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3240 00:27:23.605528 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3241 00:27:23.608645 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3242 00:27:23.612080 Total UI for P1: 0, mck2ui 16
3243 00:27:23.615326 best dqsien dly found for B0: ( 1, 3, 22)
3244 00:27:23.622070 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3245 00:27:23.622186 Total UI for P1: 0, mck2ui 16
3246 00:27:23.628461 best dqsien dly found for B1: ( 1, 3, 26)
3247 00:27:23.631616 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3248 00:27:23.635063 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3249 00:27:23.635141
3250 00:27:23.638931 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3251 00:27:23.641695 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3252 00:27:23.645386 [Gating] SW calibration Done
3253 00:27:23.645472 ==
3254 00:27:23.648817 Dram Type= 6, Freq= 0, CH_1, rank 0
3255 00:27:23.651680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3256 00:27:23.651778 ==
3257 00:27:23.655109 RX Vref Scan: 0
3258 00:27:23.655205
3259 00:27:23.655289 RX Vref 0 -> 0, step: 1
3260 00:27:23.655373
3261 00:27:23.658760 RX Delay -40 -> 252, step: 8
3262 00:27:23.661630 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3263 00:27:23.668710 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3264 00:27:23.671964 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3265 00:27:23.675372 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3266 00:27:23.678564 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3267 00:27:23.681946 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3268 00:27:23.685075 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3269 00:27:23.692082 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3270 00:27:23.695118 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3271 00:27:23.698439 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3272 00:27:23.701994 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3273 00:27:23.705154 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3274 00:27:23.711684 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3275 00:27:23.715060 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3276 00:27:23.718501 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3277 00:27:23.721841 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3278 00:27:23.721922 ==
3279 00:27:23.725221 Dram Type= 6, Freq= 0, CH_1, rank 0
3280 00:27:23.731875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3281 00:27:23.731975 ==
3282 00:27:23.732038 DQS Delay:
3283 00:27:23.734704 DQS0 = 0, DQS1 = 0
3284 00:27:23.734785 DQM Delay:
3285 00:27:23.738343 DQM0 = 119, DQM1 = 112
3286 00:27:23.738435 DQ Delay:
3287 00:27:23.741805 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3288 00:27:23.744783 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =119
3289 00:27:23.748154 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3290 00:27:23.751351 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3291 00:27:23.751466
3292 00:27:23.751525
3293 00:27:23.751595 ==
3294 00:27:23.754795 Dram Type= 6, Freq= 0, CH_1, rank 0
3295 00:27:23.758160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3296 00:27:23.761834 ==
3297 00:27:23.761920
3298 00:27:23.762014
3299 00:27:23.762071 TX Vref Scan disable
3300 00:27:23.764933 == TX Byte 0 ==
3301 00:27:23.767952 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3302 00:27:23.771454 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3303 00:27:23.774633 == TX Byte 1 ==
3304 00:27:23.777992 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3305 00:27:23.781561 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3306 00:27:23.784925 ==
3307 00:27:23.787991 Dram Type= 6, Freq= 0, CH_1, rank 0
3308 00:27:23.791376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3309 00:27:23.791481 ==
3310 00:27:23.802323 TX Vref=22, minBit 7, minWin=24, winSum=399
3311 00:27:23.805856 TX Vref=24, minBit 1, minWin=24, winSum=405
3312 00:27:23.808931 TX Vref=26, minBit 3, minWin=24, winSum=407
3313 00:27:23.812453 TX Vref=28, minBit 10, minWin=24, winSum=415
3314 00:27:23.815612 TX Vref=30, minBit 10, minWin=25, winSum=416
3315 00:27:23.822404 TX Vref=32, minBit 11, minWin=25, winSum=423
3316 00:27:23.825596 [TxChooseVref] Worse bit 11, Min win 25, Win sum 423, Final Vref 32
3317 00:27:23.825683
3318 00:27:23.829049 Final TX Range 1 Vref 32
3319 00:27:23.829128
3320 00:27:23.829190 ==
3321 00:27:23.832104 Dram Type= 6, Freq= 0, CH_1, rank 0
3322 00:27:23.835782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3323 00:27:23.838902 ==
3324 00:27:23.838979
3325 00:27:23.839040
3326 00:27:23.839096 TX Vref Scan disable
3327 00:27:23.842324 == TX Byte 0 ==
3328 00:27:23.845820 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3329 00:27:23.852353 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3330 00:27:23.852445 == TX Byte 1 ==
3331 00:27:23.855857 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3332 00:27:23.862259 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3333 00:27:23.862364
3334 00:27:23.862427 [DATLAT]
3335 00:27:23.862483 Freq=1200, CH1 RK0
3336 00:27:23.862538
3337 00:27:23.865795 DATLAT Default: 0xd
3338 00:27:23.865877 0, 0xFFFF, sum = 0
3339 00:27:23.868780 1, 0xFFFF, sum = 0
3340 00:27:23.868860 2, 0xFFFF, sum = 0
3341 00:27:23.872407 3, 0xFFFF, sum = 0
3342 00:27:23.875855 4, 0xFFFF, sum = 0
3343 00:27:23.875936 5, 0xFFFF, sum = 0
3344 00:27:23.878818 6, 0xFFFF, sum = 0
3345 00:27:23.878902 7, 0xFFFF, sum = 0
3346 00:27:23.882257 8, 0xFFFF, sum = 0
3347 00:27:23.882337 9, 0xFFFF, sum = 0
3348 00:27:23.885728 10, 0xFFFF, sum = 0
3349 00:27:23.885812 11, 0xFFFF, sum = 0
3350 00:27:23.888919 12, 0x0, sum = 1
3351 00:27:23.889001 13, 0x0, sum = 2
3352 00:27:23.892380 14, 0x0, sum = 3
3353 00:27:23.892460 15, 0x0, sum = 4
3354 00:27:23.895834 best_step = 13
3355 00:27:23.895914
3356 00:27:23.895976 ==
3357 00:27:23.899447 Dram Type= 6, Freq= 0, CH_1, rank 0
3358 00:27:23.902366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3359 00:27:23.902477 ==
3360 00:27:23.902541 RX Vref Scan: 1
3361 00:27:23.902598
3362 00:27:23.905667 Set Vref Range= 32 -> 127
3363 00:27:23.905746
3364 00:27:23.909021 RX Vref 32 -> 127, step: 1
3365 00:27:23.909100
3366 00:27:23.912587 RX Delay -13 -> 252, step: 4
3367 00:27:23.912688
3368 00:27:23.915464 Set Vref, RX VrefLevel [Byte0]: 32
3369 00:27:23.919064 [Byte1]: 32
3370 00:27:23.919143
3371 00:27:23.922357 Set Vref, RX VrefLevel [Byte0]: 33
3372 00:27:23.925865 [Byte1]: 33
3373 00:27:23.929101
3374 00:27:23.929185 Set Vref, RX VrefLevel [Byte0]: 34
3375 00:27:23.932042 [Byte1]: 34
3376 00:27:23.937212
3377 00:27:23.937294 Set Vref, RX VrefLevel [Byte0]: 35
3378 00:27:23.939924 [Byte1]: 35
3379 00:27:23.944564
3380 00:27:23.944672 Set Vref, RX VrefLevel [Byte0]: 36
3381 00:27:23.948120 [Byte1]: 36
3382 00:27:23.952316
3383 00:27:23.952428 Set Vref, RX VrefLevel [Byte0]: 37
3384 00:27:23.956086 [Byte1]: 37
3385 00:27:23.960240
3386 00:27:23.960330 Set Vref, RX VrefLevel [Byte0]: 38
3387 00:27:23.963784 [Byte1]: 38
3388 00:27:23.968220
3389 00:27:23.968306 Set Vref, RX VrefLevel [Byte0]: 39
3390 00:27:23.971854 [Byte1]: 39
3391 00:27:23.976037
3392 00:27:23.976118 Set Vref, RX VrefLevel [Byte0]: 40
3393 00:27:23.979639 [Byte1]: 40
3394 00:27:23.983977
3395 00:27:23.984058 Set Vref, RX VrefLevel [Byte0]: 41
3396 00:27:23.987603 [Byte1]: 41
3397 00:27:23.992108
3398 00:27:23.992189 Set Vref, RX VrefLevel [Byte0]: 42
3399 00:27:23.995078 [Byte1]: 42
3400 00:27:24.000099
3401 00:27:24.000180 Set Vref, RX VrefLevel [Byte0]: 43
3402 00:27:24.003052 [Byte1]: 43
3403 00:27:24.007627
3404 00:27:24.007707 Set Vref, RX VrefLevel [Byte0]: 44
3405 00:27:24.011172 [Byte1]: 44
3406 00:27:24.015518
3407 00:27:24.015599 Set Vref, RX VrefLevel [Byte0]: 45
3408 00:27:24.019050 [Byte1]: 45
3409 00:27:24.023581
3410 00:27:24.023659 Set Vref, RX VrefLevel [Byte0]: 46
3411 00:27:24.026792 [Byte1]: 46
3412 00:27:24.031281
3413 00:27:24.031367 Set Vref, RX VrefLevel [Byte0]: 47
3414 00:27:24.034817 [Byte1]: 47
3415 00:27:24.039582
3416 00:27:24.039667 Set Vref, RX VrefLevel [Byte0]: 48
3417 00:27:24.042553 [Byte1]: 48
3418 00:27:24.046917
3419 00:27:24.046999 Set Vref, RX VrefLevel [Byte0]: 49
3420 00:27:24.050550 [Byte1]: 49
3421 00:27:24.054977
3422 00:27:24.055059 Set Vref, RX VrefLevel [Byte0]: 50
3423 00:27:24.058472 [Byte1]: 50
3424 00:27:24.062744
3425 00:27:24.062824 Set Vref, RX VrefLevel [Byte0]: 51
3426 00:27:24.066431 [Byte1]: 51
3427 00:27:24.070729
3428 00:27:24.070812 Set Vref, RX VrefLevel [Byte0]: 52
3429 00:27:24.074272 [Byte1]: 52
3430 00:27:24.078526
3431 00:27:24.078608 Set Vref, RX VrefLevel [Byte0]: 53
3432 00:27:24.082117 [Byte1]: 53
3433 00:27:24.086609
3434 00:27:24.086692 Set Vref, RX VrefLevel [Byte0]: 54
3435 00:27:24.090240 [Byte1]: 54
3436 00:27:24.094499
3437 00:27:24.094602 Set Vref, RX VrefLevel [Byte0]: 55
3438 00:27:24.097969 [Byte1]: 55
3439 00:27:24.102462
3440 00:27:24.102547 Set Vref, RX VrefLevel [Byte0]: 56
3441 00:27:24.105468 [Byte1]: 56
3442 00:27:24.110102
3443 00:27:24.110182 Set Vref, RX VrefLevel [Byte0]: 57
3444 00:27:24.113618 [Byte1]: 57
3445 00:27:24.117913
3446 00:27:24.117994 Set Vref, RX VrefLevel [Byte0]: 58
3447 00:27:24.121457 [Byte1]: 58
3448 00:27:24.126196
3449 00:27:24.126279 Set Vref, RX VrefLevel [Byte0]: 59
3450 00:27:24.129615 [Byte1]: 59
3451 00:27:24.133926
3452 00:27:24.134030 Set Vref, RX VrefLevel [Byte0]: 60
3453 00:27:24.137419 [Byte1]: 60
3454 00:27:24.141556
3455 00:27:24.141636 Set Vref, RX VrefLevel [Byte0]: 61
3456 00:27:24.144945 [Byte1]: 61
3457 00:27:24.149554
3458 00:27:24.149636 Set Vref, RX VrefLevel [Byte0]: 62
3459 00:27:24.153148 [Byte1]: 62
3460 00:27:24.157861
3461 00:27:24.157941 Set Vref, RX VrefLevel [Byte0]: 63
3462 00:27:24.161043 [Byte1]: 63
3463 00:27:24.165546
3464 00:27:24.165626 Set Vref, RX VrefLevel [Byte0]: 64
3465 00:27:24.168860 [Byte1]: 64
3466 00:27:24.173386
3467 00:27:24.173470 Set Vref, RX VrefLevel [Byte0]: 65
3468 00:27:24.177000 [Byte1]: 65
3469 00:27:24.181175
3470 00:27:24.181280 Set Vref, RX VrefLevel [Byte0]: 66
3471 00:27:24.184837 [Byte1]: 66
3472 00:27:24.189020
3473 00:27:24.189126 Set Vref, RX VrefLevel [Byte0]: 67
3474 00:27:24.192577 [Byte1]: 67
3475 00:27:24.196991
3476 00:27:24.197076 Final RX Vref Byte 0 = 51 to rank0
3477 00:27:24.200486 Final RX Vref Byte 1 = 51 to rank0
3478 00:27:24.203835 Final RX Vref Byte 0 = 51 to rank1
3479 00:27:24.206737 Final RX Vref Byte 1 = 51 to rank1==
3480 00:27:24.210508 Dram Type= 6, Freq= 0, CH_1, rank 0
3481 00:27:24.216928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3482 00:27:24.217054 ==
3483 00:27:24.217144 DQS Delay:
3484 00:27:24.217226 DQS0 = 0, DQS1 = 0
3485 00:27:24.220379 DQM Delay:
3486 00:27:24.220484 DQM0 = 119, DQM1 = 111
3487 00:27:24.223412 DQ Delay:
3488 00:27:24.227006 DQ0 =122, DQ1 =112, DQ2 =112, DQ3 =118
3489 00:27:24.230084 DQ4 =118, DQ5 =128, DQ6 =128, DQ7 =116
3490 00:27:24.233608 DQ8 =102, DQ9 =98, DQ10 =114, DQ11 =104
3491 00:27:24.236989 DQ12 =122, DQ13 =118, DQ14 =118, DQ15 =118
3492 00:27:24.237068
3493 00:27:24.237127
3494 00:27:24.246598 [DQSOSCAuto] RK0, (LSB)MR18= 0x114, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 409 ps
3495 00:27:24.246732 CH1 RK0: MR19=404, MR18=114
3496 00:27:24.253554 CH1_RK0: MR19=0x404, MR18=0x114, DQSOSC=402, MR23=63, INC=40, DEC=27
3497 00:27:24.253646
3498 00:27:24.256594 ----->DramcWriteLeveling(PI) begin...
3499 00:27:24.256672 ==
3500 00:27:24.260251 Dram Type= 6, Freq= 0, CH_1, rank 1
3501 00:27:24.263291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3502 00:27:24.267001 ==
3503 00:27:24.267081 Write leveling (Byte 0): 25 => 25
3504 00:27:24.270032 Write leveling (Byte 1): 31 => 31
3505 00:27:24.273620 DramcWriteLeveling(PI) end<-----
3506 00:27:24.273699
3507 00:27:24.273758 ==
3508 00:27:24.277025 Dram Type= 6, Freq= 0, CH_1, rank 1
3509 00:27:24.283471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3510 00:27:24.283557 ==
3511 00:27:24.283621 [Gating] SW mode calibration
3512 00:27:24.293495 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3513 00:27:24.296631 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3514 00:27:24.300124 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3515 00:27:24.306716 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3516 00:27:24.310094 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3517 00:27:24.313556 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3518 00:27:24.319780 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3519 00:27:24.323165 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3520 00:27:24.326499 0 15 24 | B1->B0 | 2b2b 3434 | 1 0 | (1 0) (0 1)
3521 00:27:24.333200 0 15 28 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
3522 00:27:24.336467 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3523 00:27:24.339845 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3524 00:27:24.346994 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3525 00:27:24.350081 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3526 00:27:24.353054 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3527 00:27:24.359754 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3528 00:27:24.363355 1 0 24 | B1->B0 | 3f3f 2f2f | 0 0 | (0 0) (0 0)
3529 00:27:24.366390 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3530 00:27:24.373118 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3531 00:27:24.376518 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3532 00:27:24.379489 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3533 00:27:24.386399 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3534 00:27:24.390031 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3535 00:27:24.393145 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3536 00:27:24.399944 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3537 00:27:24.403059 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3538 00:27:24.406568 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3539 00:27:24.413369 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3540 00:27:24.416731 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3541 00:27:24.419694 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3542 00:27:24.423071 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3543 00:27:24.429770 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3544 00:27:24.433060 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3545 00:27:24.436614 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3546 00:27:24.443177 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3547 00:27:24.446557 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3548 00:27:24.449954 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3549 00:27:24.456571 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3550 00:27:24.459609 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3551 00:27:24.463177 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3552 00:27:24.469851 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3553 00:27:24.473382 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3554 00:27:24.476468 Total UI for P1: 0, mck2ui 16
3555 00:27:24.479588 best dqsien dly found for B0: ( 1, 3, 24)
3556 00:27:24.483082 Total UI for P1: 0, mck2ui 16
3557 00:27:24.486557 best dqsien dly found for B1: ( 1, 3, 24)
3558 00:27:24.489636 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3559 00:27:24.493098 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3560 00:27:24.493177
3561 00:27:24.496384 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3562 00:27:24.499766 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3563 00:27:24.503209 [Gating] SW calibration Done
3564 00:27:24.503291 ==
3565 00:27:24.506578 Dram Type= 6, Freq= 0, CH_1, rank 1
3566 00:27:24.509615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3567 00:27:24.513103 ==
3568 00:27:24.513183 RX Vref Scan: 0
3569 00:27:24.513244
3570 00:27:24.516444 RX Vref 0 -> 0, step: 1
3571 00:27:24.516521
3572 00:27:24.516581 RX Delay -40 -> 252, step: 8
3573 00:27:24.523245 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3574 00:27:24.526521 iDelay=200, Bit 1, Center 111 (48 ~ 175) 128
3575 00:27:24.530092 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3576 00:27:24.533066 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3577 00:27:24.536408 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
3578 00:27:24.542923 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3579 00:27:24.546415 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3580 00:27:24.549456 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3581 00:27:24.553006 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3582 00:27:24.556458 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3583 00:27:24.563041 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
3584 00:27:24.566009 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3585 00:27:24.569478 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3586 00:27:24.572633 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3587 00:27:24.579304 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3588 00:27:24.582972 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3589 00:27:24.583056 ==
3590 00:27:24.585976 Dram Type= 6, Freq= 0, CH_1, rank 1
3591 00:27:24.589321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3592 00:27:24.589400 ==
3593 00:27:24.589460 DQS Delay:
3594 00:27:24.592647 DQS0 = 0, DQS1 = 0
3595 00:27:24.592748 DQM Delay:
3596 00:27:24.596240 DQM0 = 120, DQM1 = 111
3597 00:27:24.596317 DQ Delay:
3598 00:27:24.599277 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =123
3599 00:27:24.602912 DQ4 =123, DQ5 =131, DQ6 =127, DQ7 =115
3600 00:27:24.605801 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =103
3601 00:27:24.609459 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =123
3602 00:27:24.612736
3603 00:27:24.612857
3604 00:27:24.612915 ==
3605 00:27:24.616116 Dram Type= 6, Freq= 0, CH_1, rank 1
3606 00:27:24.619094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3607 00:27:24.619174 ==
3608 00:27:24.619233
3609 00:27:24.619287
3610 00:27:24.622640 TX Vref Scan disable
3611 00:27:24.622718 == TX Byte 0 ==
3612 00:27:24.628999 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3613 00:27:24.632456 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3614 00:27:24.632578 == TX Byte 1 ==
3615 00:27:24.638929 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3616 00:27:24.642443 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3617 00:27:24.642541 ==
3618 00:27:24.645695 Dram Type= 6, Freq= 0, CH_1, rank 1
3619 00:27:24.649234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3620 00:27:24.649370 ==
3621 00:27:24.661878 TX Vref=22, minBit 1, minWin=24, winSum=415
3622 00:27:24.665400 TX Vref=24, minBit 1, minWin=25, winSum=423
3623 00:27:24.668450 TX Vref=26, minBit 3, minWin=25, winSum=423
3624 00:27:24.671980 TX Vref=28, minBit 3, minWin=26, winSum=425
3625 00:27:24.675013 TX Vref=30, minBit 1, minWin=26, winSum=425
3626 00:27:24.678322 TX Vref=32, minBit 15, minWin=25, winSum=429
3627 00:27:24.685417 [TxChooseVref] Worse bit 3, Min win 26, Win sum 425, Final Vref 28
3628 00:27:24.685512
3629 00:27:24.688438 Final TX Range 1 Vref 28
3630 00:27:24.688515
3631 00:27:24.688573 ==
3632 00:27:24.691990 Dram Type= 6, Freq= 0, CH_1, rank 1
3633 00:27:24.695102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3634 00:27:24.695180 ==
3635 00:27:24.695239
3636 00:27:24.698163
3637 00:27:24.698241 TX Vref Scan disable
3638 00:27:24.701849 == TX Byte 0 ==
3639 00:27:24.704741 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3640 00:27:24.708409 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3641 00:27:24.711459 == TX Byte 1 ==
3642 00:27:24.714931 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3643 00:27:24.718118 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3644 00:27:24.721646
3645 00:27:24.721724 [DATLAT]
3646 00:27:24.721784 Freq=1200, CH1 RK1
3647 00:27:24.721841
3648 00:27:24.724898 DATLAT Default: 0xd
3649 00:27:24.724976 0, 0xFFFF, sum = 0
3650 00:27:24.728199 1, 0xFFFF, sum = 0
3651 00:27:24.728278 2, 0xFFFF, sum = 0
3652 00:27:24.731607 3, 0xFFFF, sum = 0
3653 00:27:24.731686 4, 0xFFFF, sum = 0
3654 00:27:24.735181 5, 0xFFFF, sum = 0
3655 00:27:24.738434 6, 0xFFFF, sum = 0
3656 00:27:24.738514 7, 0xFFFF, sum = 0
3657 00:27:24.741812 8, 0xFFFF, sum = 0
3658 00:27:24.741894 9, 0xFFFF, sum = 0
3659 00:27:24.745161 10, 0xFFFF, sum = 0
3660 00:27:24.745246 11, 0xFFFF, sum = 0
3661 00:27:24.747985 12, 0x0, sum = 1
3662 00:27:24.748064 13, 0x0, sum = 2
3663 00:27:24.751381 14, 0x0, sum = 3
3664 00:27:24.751460 15, 0x0, sum = 4
3665 00:27:24.751521 best_step = 13
3666 00:27:24.754960
3667 00:27:24.755038 ==
3668 00:27:24.758081 Dram Type= 6, Freq= 0, CH_1, rank 1
3669 00:27:24.761882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3670 00:27:24.761975 ==
3671 00:27:24.762037 RX Vref Scan: 0
3672 00:27:24.762093
3673 00:27:24.764581 RX Vref 0 -> 0, step: 1
3674 00:27:24.764680
3675 00:27:24.767776 RX Delay -13 -> 252, step: 4
3676 00:27:24.771310 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3677 00:27:24.777791 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3678 00:27:24.781411 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3679 00:27:24.784941 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3680 00:27:24.788056 iDelay=195, Bit 4, Center 120 (59 ~ 182) 124
3681 00:27:24.791661 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3682 00:27:24.798157 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3683 00:27:24.801361 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3684 00:27:24.804820 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3685 00:27:24.807882 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3686 00:27:24.811448 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3687 00:27:24.818027 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3688 00:27:24.821196 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3689 00:27:24.824729 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3690 00:27:24.828208 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3691 00:27:24.831275 iDelay=195, Bit 15, Center 122 (59 ~ 186) 128
3692 00:27:24.831383 ==
3693 00:27:24.834594 Dram Type= 6, Freq= 0, CH_1, rank 1
3694 00:27:24.841833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3695 00:27:24.841986 ==
3696 00:27:24.842080 DQS Delay:
3697 00:27:24.844808 DQS0 = 0, DQS1 = 0
3698 00:27:24.844912 DQM Delay:
3699 00:27:24.848250 DQM0 = 119, DQM1 = 112
3700 00:27:24.848352 DQ Delay:
3701 00:27:24.851478 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =118
3702 00:27:24.854644 DQ4 =120, DQ5 =130, DQ6 =126, DQ7 =116
3703 00:27:24.858215 DQ8 =98, DQ9 =102, DQ10 =112, DQ11 =106
3704 00:27:24.861446 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =122
3705 00:27:24.861554
3706 00:27:24.861646
3707 00:27:24.871547 [DQSOSCAuto] RK1, (LSB)MR18= 0xaef, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 406 ps
3708 00:27:24.871685 CH1 RK1: MR19=403, MR18=AEF
3709 00:27:24.878262 CH1_RK1: MR19=0x403, MR18=0xAEF, DQSOSC=406, MR23=63, INC=39, DEC=26
3710 00:27:24.881374 [RxdqsGatingPostProcess] freq 1200
3711 00:27:24.888080 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3712 00:27:24.891543 best DQS0 dly(2T, 0.5T) = (0, 11)
3713 00:27:24.895022 best DQS1 dly(2T, 0.5T) = (0, 11)
3714 00:27:24.898058 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3715 00:27:24.898160 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3716 00:27:24.901603 best DQS0 dly(2T, 0.5T) = (0, 11)
3717 00:27:24.905032 best DQS1 dly(2T, 0.5T) = (0, 11)
3718 00:27:24.908039 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3719 00:27:24.911917 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3720 00:27:24.914800 Pre-setting of DQS Precalculation
3721 00:27:24.921510 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3722 00:27:24.928115 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3723 00:27:24.934755 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3724 00:27:24.934875
3725 00:27:24.934964
3726 00:27:24.938305 [Calibration Summary] 2400 Mbps
3727 00:27:24.938408 CH 0, Rank 0
3728 00:27:24.941295 SW Impedance : PASS
3729 00:27:24.944941 DUTY Scan : NO K
3730 00:27:24.945048 ZQ Calibration : PASS
3731 00:27:24.948056 Jitter Meter : NO K
3732 00:27:24.951300 CBT Training : PASS
3733 00:27:24.951403 Write leveling : PASS
3734 00:27:24.954753 RX DQS gating : PASS
3735 00:27:24.958309 RX DQ/DQS(RDDQC) : PASS
3736 00:27:24.958419 TX DQ/DQS : PASS
3737 00:27:24.961597 RX DATLAT : PASS
3738 00:27:24.961699 RX DQ/DQS(Engine): PASS
3739 00:27:24.964948 TX OE : NO K
3740 00:27:24.965050 All Pass.
3741 00:27:24.965138
3742 00:27:24.967949 CH 0, Rank 1
3743 00:27:24.968047 SW Impedance : PASS
3744 00:27:24.971348 DUTY Scan : NO K
3745 00:27:24.974649 ZQ Calibration : PASS
3746 00:27:24.974751 Jitter Meter : NO K
3747 00:27:24.977803 CBT Training : PASS
3748 00:27:24.981272 Write leveling : PASS
3749 00:27:24.981376 RX DQS gating : PASS
3750 00:27:24.984643 RX DQ/DQS(RDDQC) : PASS
3751 00:27:24.987863 TX DQ/DQS : PASS
3752 00:27:24.987970 RX DATLAT : PASS
3753 00:27:24.991412 RX DQ/DQS(Engine): PASS
3754 00:27:24.994484 TX OE : NO K
3755 00:27:24.994584 All Pass.
3756 00:27:24.994672
3757 00:27:24.994757 CH 1, Rank 0
3758 00:27:24.998093 SW Impedance : PASS
3759 00:27:25.001077 DUTY Scan : NO K
3760 00:27:25.001175 ZQ Calibration : PASS
3761 00:27:25.004664 Jitter Meter : NO K
3762 00:27:25.007754 CBT Training : PASS
3763 00:27:25.007854 Write leveling : PASS
3764 00:27:25.011318 RX DQS gating : PASS
3765 00:27:25.011417 RX DQ/DQS(RDDQC) : PASS
3766 00:27:25.014813 TX DQ/DQS : PASS
3767 00:27:25.017927 RX DATLAT : PASS
3768 00:27:25.018026 RX DQ/DQS(Engine): PASS
3769 00:27:25.021463 TX OE : NO K
3770 00:27:25.021561 All Pass.
3771 00:27:25.021646
3772 00:27:25.024447 CH 1, Rank 1
3773 00:27:25.024544 SW Impedance : PASS
3774 00:27:25.027902 DUTY Scan : NO K
3775 00:27:25.030968 ZQ Calibration : PASS
3776 00:27:25.031067 Jitter Meter : NO K
3777 00:27:25.034497 CBT Training : PASS
3778 00:27:25.037871 Write leveling : PASS
3779 00:27:25.037973 RX DQS gating : PASS
3780 00:27:25.040921 RX DQ/DQS(RDDQC) : PASS
3781 00:27:25.044497 TX DQ/DQS : PASS
3782 00:27:25.044626 RX DATLAT : PASS
3783 00:27:25.047557 RX DQ/DQS(Engine): PASS
3784 00:27:25.051121 TX OE : NO K
3785 00:27:25.051198 All Pass.
3786 00:27:25.051257
3787 00:27:25.051312 DramC Write-DBI off
3788 00:27:25.054160 PER_BANK_REFRESH: Hybrid Mode
3789 00:27:25.057457 TX_TRACKING: ON
3790 00:27:25.064435 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3791 00:27:25.067879 [FAST_K] Save calibration result to emmc
3792 00:27:25.074649 dramc_set_vcore_voltage set vcore to 650000
3793 00:27:25.074759 Read voltage for 600, 5
3794 00:27:25.077563 Vio18 = 0
3795 00:27:25.077641 Vcore = 650000
3796 00:27:25.077700 Vdram = 0
3797 00:27:25.081048 Vddq = 0
3798 00:27:25.081125 Vmddr = 0
3799 00:27:25.084343 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3800 00:27:25.091280 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3801 00:27:25.094251 MEM_TYPE=3, freq_sel=19
3802 00:27:25.094333 sv_algorithm_assistance_LP4_1600
3803 00:27:25.100897 ============ PULL DRAM RESETB DOWN ============
3804 00:27:25.104320 ========== PULL DRAM RESETB DOWN end =========
3805 00:27:25.107786 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3806 00:27:25.110798 ===================================
3807 00:27:25.114340 LPDDR4 DRAM CONFIGURATION
3808 00:27:25.117446 ===================================
3809 00:27:25.120898 EX_ROW_EN[0] = 0x0
3810 00:27:25.120977 EX_ROW_EN[1] = 0x0
3811 00:27:25.124602 LP4Y_EN = 0x0
3812 00:27:25.124680 WORK_FSP = 0x0
3813 00:27:25.127474 WL = 0x2
3814 00:27:25.127550 RL = 0x2
3815 00:27:25.131053 BL = 0x2
3816 00:27:25.131130 RPST = 0x0
3817 00:27:25.134203 RD_PRE = 0x0
3818 00:27:25.134281 WR_PRE = 0x1
3819 00:27:25.137721 WR_PST = 0x0
3820 00:27:25.137798 DBI_WR = 0x0
3821 00:27:25.140896 DBI_RD = 0x0
3822 00:27:25.140973 OTF = 0x1
3823 00:27:25.144077 ===================================
3824 00:27:25.147615 ===================================
3825 00:27:25.151113 ANA top config
3826 00:27:25.154062 ===================================
3827 00:27:25.157588 DLL_ASYNC_EN = 0
3828 00:27:25.157668 ALL_SLAVE_EN = 1
3829 00:27:25.160604 NEW_RANK_MODE = 1
3830 00:27:25.164066 DLL_IDLE_MODE = 1
3831 00:27:25.167591 LP45_APHY_COMB_EN = 1
3832 00:27:25.170606 TX_ODT_DIS = 1
3833 00:27:25.170685 NEW_8X_MODE = 1
3834 00:27:25.174036 ===================================
3835 00:27:25.177578 ===================================
3836 00:27:25.180714 data_rate = 1200
3837 00:27:25.183853 CKR = 1
3838 00:27:25.187320 DQ_P2S_RATIO = 8
3839 00:27:25.190783 ===================================
3840 00:27:25.193889 CA_P2S_RATIO = 8
3841 00:27:25.197357 DQ_CA_OPEN = 0
3842 00:27:25.197438 DQ_SEMI_OPEN = 0
3843 00:27:25.200411 CA_SEMI_OPEN = 0
3844 00:27:25.203850 CA_FULL_RATE = 0
3845 00:27:25.206958 DQ_CKDIV4_EN = 1
3846 00:27:25.210615 CA_CKDIV4_EN = 1
3847 00:27:25.213722 CA_PREDIV_EN = 0
3848 00:27:25.213800 PH8_DLY = 0
3849 00:27:25.217166 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3850 00:27:25.220215 DQ_AAMCK_DIV = 4
3851 00:27:25.223884 CA_AAMCK_DIV = 4
3852 00:27:25.226782 CA_ADMCK_DIV = 4
3853 00:27:25.230068 DQ_TRACK_CA_EN = 0
3854 00:27:25.230167 CA_PICK = 600
3855 00:27:25.233462 CA_MCKIO = 600
3856 00:27:25.237089 MCKIO_SEMI = 0
3857 00:27:25.240201 PLL_FREQ = 2288
3858 00:27:25.243328 DQ_UI_PI_RATIO = 32
3859 00:27:25.246818 CA_UI_PI_RATIO = 0
3860 00:27:25.250432 ===================================
3861 00:27:25.253483 ===================================
3862 00:27:25.253562 memory_type:LPDDR4
3863 00:27:25.257061 GP_NUM : 10
3864 00:27:25.259938 SRAM_EN : 1
3865 00:27:25.260014 MD32_EN : 0
3866 00:27:25.263524 ===================================
3867 00:27:25.266541 [ANA_INIT] >>>>>>>>>>>>>>
3868 00:27:25.270074 <<<<<< [CONFIGURE PHASE]: ANA_TX
3869 00:27:25.273175 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3870 00:27:25.276979 ===================================
3871 00:27:25.279917 data_rate = 1200,PCW = 0X5800
3872 00:27:25.283399 ===================================
3873 00:27:25.286472 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3874 00:27:25.289953 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3875 00:27:25.296839 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3876 00:27:25.299666 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3877 00:27:25.303134 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3878 00:27:25.309829 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3879 00:27:25.309948 [ANA_INIT] flow start
3880 00:27:25.313328 [ANA_INIT] PLL >>>>>>>>
3881 00:27:25.316265 [ANA_INIT] PLL <<<<<<<<
3882 00:27:25.316371 [ANA_INIT] MIDPI >>>>>>>>
3883 00:27:25.319611 [ANA_INIT] MIDPI <<<<<<<<
3884 00:27:25.322963 [ANA_INIT] DLL >>>>>>>>
3885 00:27:25.323067 [ANA_INIT] flow end
3886 00:27:25.326161 ============ LP4 DIFF to SE enter ============
3887 00:27:25.332666 ============ LP4 DIFF to SE exit ============
3888 00:27:25.332788 [ANA_INIT] <<<<<<<<<<<<<
3889 00:27:25.336284 [Flow] Enable top DCM control >>>>>
3890 00:27:25.339815 [Flow] Enable top DCM control <<<<<
3891 00:27:25.342841 Enable DLL master slave shuffle
3892 00:27:25.349565 ==============================================================
3893 00:27:25.349691 Gating Mode config
3894 00:27:25.356336 ==============================================================
3895 00:27:25.359326 Config description:
3896 00:27:25.369090 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3897 00:27:25.376021 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3898 00:27:25.379233 SELPH_MODE 0: By rank 1: By Phase
3899 00:27:25.386008 ==============================================================
3900 00:27:25.389026 GAT_TRACK_EN = 1
3901 00:27:25.392374 RX_GATING_MODE = 2
3902 00:27:25.395830 RX_GATING_TRACK_MODE = 2
3903 00:27:25.395936 SELPH_MODE = 1
3904 00:27:25.398864 PICG_EARLY_EN = 1
3905 00:27:25.402512 VALID_LAT_VALUE = 1
3906 00:27:25.408819 ==============================================================
3907 00:27:25.412390 Enter into Gating configuration >>>>
3908 00:27:25.415791 Exit from Gating configuration <<<<
3909 00:27:25.418767 Enter into DVFS_PRE_config >>>>>
3910 00:27:25.429170 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3911 00:27:25.432286 Exit from DVFS_PRE_config <<<<<
3912 00:27:25.435525 Enter into PICG configuration >>>>
3913 00:27:25.439089 Exit from PICG configuration <<<<
3914 00:27:25.442455 [RX_INPUT] configuration >>>>>
3915 00:27:25.445729 [RX_INPUT] configuration <<<<<
3916 00:27:25.448834 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3917 00:27:25.455464 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3918 00:27:25.462251 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3919 00:27:25.468927 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3920 00:27:25.472474 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3921 00:27:25.478957 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3922 00:27:25.482471 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3923 00:27:25.488608 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3924 00:27:25.492057 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3925 00:27:25.495494 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3926 00:27:25.498945 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3927 00:27:25.505417 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3928 00:27:25.509072 ===================================
3929 00:27:25.509180 LPDDR4 DRAM CONFIGURATION
3930 00:27:25.512367 ===================================
3931 00:27:25.515388 EX_ROW_EN[0] = 0x0
3932 00:27:25.518600 EX_ROW_EN[1] = 0x0
3933 00:27:25.518701 LP4Y_EN = 0x0
3934 00:27:25.521886 WORK_FSP = 0x0
3935 00:27:25.521985 WL = 0x2
3936 00:27:25.525196 RL = 0x2
3937 00:27:25.525331 BL = 0x2
3938 00:27:25.529035 RPST = 0x0
3939 00:27:25.529135 RD_PRE = 0x0
3940 00:27:25.532397 WR_PRE = 0x1
3941 00:27:25.532495 WR_PST = 0x0
3942 00:27:25.535311 DBI_WR = 0x0
3943 00:27:25.535411 DBI_RD = 0x0
3944 00:27:25.538997 OTF = 0x1
3945 00:27:25.541995 ===================================
3946 00:27:25.545362 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3947 00:27:25.548622 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3948 00:27:25.555312 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3949 00:27:25.558923 ===================================
3950 00:27:25.559008 LPDDR4 DRAM CONFIGURATION
3951 00:27:25.561910 ===================================
3952 00:27:25.565497 EX_ROW_EN[0] = 0x10
3953 00:27:25.568570 EX_ROW_EN[1] = 0x0
3954 00:27:25.568648 LP4Y_EN = 0x0
3955 00:27:25.571824 WORK_FSP = 0x0
3956 00:27:25.571900 WL = 0x2
3957 00:27:25.575481 RL = 0x2
3958 00:27:25.575558 BL = 0x2
3959 00:27:25.578642 RPST = 0x0
3960 00:27:25.578735 RD_PRE = 0x0
3961 00:27:25.581938 WR_PRE = 0x1
3962 00:27:25.582017 WR_PST = 0x0
3963 00:27:25.585589 DBI_WR = 0x0
3964 00:27:25.585667 DBI_RD = 0x0
3965 00:27:25.588851 OTF = 0x1
3966 00:27:25.591940 ===================================
3967 00:27:25.598682 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3968 00:27:25.601858 nWR fixed to 30
3969 00:27:25.601944 [ModeRegInit_LP4] CH0 RK0
3970 00:27:25.605404 [ModeRegInit_LP4] CH0 RK1
3971 00:27:25.608297 [ModeRegInit_LP4] CH1 RK0
3972 00:27:25.611860 [ModeRegInit_LP4] CH1 RK1
3973 00:27:25.611942 match AC timing 17
3974 00:27:25.614904 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3975 00:27:25.621896 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3976 00:27:25.625286 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3977 00:27:25.632010 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3978 00:27:25.635194 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3979 00:27:25.635303 ==
3980 00:27:25.638460 Dram Type= 6, Freq= 0, CH_0, rank 0
3981 00:27:25.641963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3982 00:27:25.642070 ==
3983 00:27:25.648402 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3984 00:27:25.655141 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3985 00:27:25.658585 [CA 0] Center 36 (5~67) winsize 63
3986 00:27:25.661477 [CA 1] Center 36 (6~67) winsize 62
3987 00:27:25.664910 [CA 2] Center 34 (4~65) winsize 62
3988 00:27:25.668256 [CA 3] Center 34 (3~65) winsize 63
3989 00:27:25.671410 [CA 4] Center 33 (3~64) winsize 62
3990 00:27:25.674955 [CA 5] Center 33 (3~64) winsize 62
3991 00:27:25.675061
3992 00:27:25.678254 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3993 00:27:25.678355
3994 00:27:25.681907 [CATrainingPosCal] consider 1 rank data
3995 00:27:25.685275 u2DelayCellTimex100 = 270/100 ps
3996 00:27:25.688233 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
3997 00:27:25.692182 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3998 00:27:25.694816 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3999 00:27:25.698297 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4000 00:27:25.701440 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4001 00:27:25.704928 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4002 00:27:25.705031
4003 00:27:25.708272 CA PerBit enable=1, Macro0, CA PI delay=33
4004 00:27:25.708371
4005 00:27:25.711817 [CBTSetCACLKResult] CA Dly = 33
4006 00:27:25.715225 CS Dly: 5 (0~36)
4007 00:27:25.715327 ==
4008 00:27:25.718252 Dram Type= 6, Freq= 0, CH_0, rank 1
4009 00:27:25.721771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4010 00:27:25.721872 ==
4011 00:27:25.728164 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4012 00:27:25.735250 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4013 00:27:25.738322 [CA 0] Center 36 (6~67) winsize 62
4014 00:27:25.741901 [CA 1] Center 36 (6~67) winsize 62
4015 00:27:25.745055 [CA 2] Center 35 (5~66) winsize 62
4016 00:27:25.748305 [CA 3] Center 34 (4~65) winsize 62
4017 00:27:25.751463 [CA 4] Center 34 (3~65) winsize 63
4018 00:27:25.754825 [CA 5] Center 34 (3~65) winsize 63
4019 00:27:25.754933
4020 00:27:25.758181 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4021 00:27:25.758285
4022 00:27:25.761946 [CATrainingPosCal] consider 2 rank data
4023 00:27:25.764634 u2DelayCellTimex100 = 270/100 ps
4024 00:27:25.768356 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
4025 00:27:25.771288 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
4026 00:27:25.774698 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
4027 00:27:25.778130 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4028 00:27:25.781694 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4029 00:27:25.784860 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4030 00:27:25.784964
4031 00:27:25.791728 CA PerBit enable=1, Macro0, CA PI delay=33
4032 00:27:25.791843
4033 00:27:25.791931 [CBTSetCACLKResult] CA Dly = 33
4034 00:27:25.794831 CS Dly: 5 (0~36)
4035 00:27:25.794932
4036 00:27:25.798469 ----->DramcWriteLeveling(PI) begin...
4037 00:27:25.798570 ==
4038 00:27:25.801444 Dram Type= 6, Freq= 0, CH_0, rank 0
4039 00:27:25.805174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4040 00:27:25.805276 ==
4041 00:27:25.808472 Write leveling (Byte 0): 32 => 32
4042 00:27:25.811591 Write leveling (Byte 1): 32 => 32
4043 00:27:25.815028 DramcWriteLeveling(PI) end<-----
4044 00:27:25.815128
4045 00:27:25.815215 ==
4046 00:27:25.818385 Dram Type= 6, Freq= 0, CH_0, rank 0
4047 00:27:25.822035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4048 00:27:25.822136 ==
4049 00:27:25.825084 [Gating] SW mode calibration
4050 00:27:25.831548 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4051 00:27:25.838311 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4052 00:27:25.841340 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4053 00:27:25.848393 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4054 00:27:25.851351 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4055 00:27:25.854887 0 9 12 | B1->B0 | 3333 2f2f | 1 1 | (1 1) (1 1)
4056 00:27:25.861371 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
4057 00:27:25.864904 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4058 00:27:25.868388 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4059 00:27:25.871379 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4060 00:27:25.878170 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4061 00:27:25.881713 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4062 00:27:25.885030 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4063 00:27:25.891262 0 10 12 | B1->B0 | 2323 3938 | 0 1 | (0 0) (0 0)
4064 00:27:25.895054 0 10 16 | B1->B0 | 3939 4646 | 1 0 | (0 0) (0 0)
4065 00:27:25.898381 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4066 00:27:25.904956 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4067 00:27:25.908326 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4068 00:27:25.911248 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4069 00:27:25.917891 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4070 00:27:25.921340 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4071 00:27:25.924804 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4072 00:27:25.931366 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 00:27:25.934766 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 00:27:25.938021 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 00:27:25.944681 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 00:27:25.947817 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4077 00:27:25.951264 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4078 00:27:25.957843 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4079 00:27:25.961260 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4080 00:27:25.964710 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4081 00:27:25.971194 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4082 00:27:25.974385 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4083 00:27:25.977938 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4084 00:27:25.984402 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4085 00:27:25.987813 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4086 00:27:25.991297 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4087 00:27:25.997774 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4088 00:27:26.001269 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4089 00:27:26.004285 Total UI for P1: 0, mck2ui 16
4090 00:27:26.007846 best dqsien dly found for B0: ( 0, 13, 10)
4091 00:27:26.011242 Total UI for P1: 0, mck2ui 16
4092 00:27:26.014267 best dqsien dly found for B1: ( 0, 13, 12)
4093 00:27:26.017702 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4094 00:27:26.021287 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4095 00:27:26.021391
4096 00:27:26.024432 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4097 00:27:26.027785 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4098 00:27:26.031365 [Gating] SW calibration Done
4099 00:27:26.031469 ==
4100 00:27:26.034415 Dram Type= 6, Freq= 0, CH_0, rank 0
4101 00:27:26.037981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4102 00:27:26.038087 ==
4103 00:27:26.040936 RX Vref Scan: 0
4104 00:27:26.041036
4105 00:27:26.044601 RX Vref 0 -> 0, step: 1
4106 00:27:26.044708
4107 00:27:26.044830 RX Delay -230 -> 252, step: 16
4108 00:27:26.051193 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4109 00:27:26.054306 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4110 00:27:26.057819 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4111 00:27:26.060814 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4112 00:27:26.067769 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4113 00:27:26.070935 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4114 00:27:26.074541 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4115 00:27:26.077396 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4116 00:27:26.081079 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4117 00:27:26.087293 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4118 00:27:26.091149 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4119 00:27:26.094207 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4120 00:27:26.097643 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4121 00:27:26.104113 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4122 00:27:26.107418 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4123 00:27:26.110890 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4124 00:27:26.110974 ==
4125 00:27:26.114426 Dram Type= 6, Freq= 0, CH_0, rank 0
4126 00:27:26.117388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4127 00:27:26.120926 ==
4128 00:27:26.121007 DQS Delay:
4129 00:27:26.121069 DQS0 = 0, DQS1 = 0
4130 00:27:26.124413 DQM Delay:
4131 00:27:26.124493 DQM0 = 50, DQM1 = 40
4132 00:27:26.127516 DQ Delay:
4133 00:27:26.127596 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =41
4134 00:27:26.130930 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4135 00:27:26.134551 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =33
4136 00:27:26.137367 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =49
4137 00:27:26.137479
4138 00:27:26.137541
4139 00:27:26.141103 ==
4140 00:27:26.144098 Dram Type= 6, Freq= 0, CH_0, rank 0
4141 00:27:26.147489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4142 00:27:26.147581 ==
4143 00:27:26.147645
4144 00:27:26.147702
4145 00:27:26.150862 TX Vref Scan disable
4146 00:27:26.150943 == TX Byte 0 ==
4147 00:27:26.157904 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4148 00:27:26.160939 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4149 00:27:26.161059 == TX Byte 1 ==
4150 00:27:26.167486 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4151 00:27:26.170735 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4152 00:27:26.170825 ==
4153 00:27:26.174158 Dram Type= 6, Freq= 0, CH_0, rank 0
4154 00:27:26.177316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4155 00:27:26.177397 ==
4156 00:27:26.177458
4157 00:27:26.177514
4158 00:27:26.180986 TX Vref Scan disable
4159 00:27:26.184020 == TX Byte 0 ==
4160 00:27:26.187224 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4161 00:27:26.190581 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4162 00:27:26.193834 == TX Byte 1 ==
4163 00:27:26.197369 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4164 00:27:26.200413 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4165 00:27:26.200512
4166 00:27:26.204296 [DATLAT]
4167 00:27:26.204369 Freq=600, CH0 RK0
4168 00:27:26.204427
4169 00:27:26.207129 DATLAT Default: 0x9
4170 00:27:26.207210 0, 0xFFFF, sum = 0
4171 00:27:26.210838 1, 0xFFFF, sum = 0
4172 00:27:26.210923 2, 0xFFFF, sum = 0
4173 00:27:26.214139 3, 0xFFFF, sum = 0
4174 00:27:26.214222 4, 0xFFFF, sum = 0
4175 00:27:26.217766 5, 0xFFFF, sum = 0
4176 00:27:26.217850 6, 0xFFFF, sum = 0
4177 00:27:26.220773 7, 0xFFFF, sum = 0
4178 00:27:26.220858 8, 0x0, sum = 1
4179 00:27:26.224224 9, 0x0, sum = 2
4180 00:27:26.224305 10, 0x0, sum = 3
4181 00:27:26.227356 11, 0x0, sum = 4
4182 00:27:26.227439 best_step = 9
4183 00:27:26.227500
4184 00:27:26.227557 ==
4185 00:27:26.230861 Dram Type= 6, Freq= 0, CH_0, rank 0
4186 00:27:26.233908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4187 00:27:26.233995 ==
4188 00:27:26.237368 RX Vref Scan: 1
4189 00:27:26.237451
4190 00:27:26.241002 RX Vref 0 -> 0, step: 1
4191 00:27:26.241089
4192 00:27:26.241151 RX Delay -179 -> 252, step: 8
4193 00:27:26.244057
4194 00:27:26.244136 Set Vref, RX VrefLevel [Byte0]: 60
4195 00:27:26.247086 [Byte1]: 48
4196 00:27:26.252020
4197 00:27:26.252109 Final RX Vref Byte 0 = 60 to rank0
4198 00:27:26.255286 Final RX Vref Byte 1 = 48 to rank0
4199 00:27:26.258856 Final RX Vref Byte 0 = 60 to rank1
4200 00:27:26.262470 Final RX Vref Byte 1 = 48 to rank1==
4201 00:27:26.265418 Dram Type= 6, Freq= 0, CH_0, rank 0
4202 00:27:26.271963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4203 00:27:26.272055 ==
4204 00:27:26.272119 DQS Delay:
4205 00:27:26.272176 DQS0 = 0, DQS1 = 0
4206 00:27:26.275319 DQM Delay:
4207 00:27:26.275399 DQM0 = 49, DQM1 = 37
4208 00:27:26.278860 DQ Delay:
4209 00:27:26.281897 DQ0 =48, DQ1 =48, DQ2 =48, DQ3 =44
4210 00:27:26.285490 DQ4 =52, DQ5 =40, DQ6 =60, DQ7 =56
4211 00:27:26.285573 DQ8 =32, DQ9 =20, DQ10 =36, DQ11 =32
4212 00:27:26.292074 DQ12 =44, DQ13 =40, DQ14 =48, DQ15 =44
4213 00:27:26.292162
4214 00:27:26.292224
4215 00:27:26.298878 [DQSOSCAuto] RK0, (LSB)MR18= 0x635d, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 391 ps
4216 00:27:26.301954 CH0 RK0: MR19=808, MR18=635D
4217 00:27:26.308538 CH0_RK0: MR19=0x808, MR18=0x635D, DQSOSC=391, MR23=63, INC=171, DEC=114
4218 00:27:26.308627
4219 00:27:26.311999 ----->DramcWriteLeveling(PI) begin...
4220 00:27:26.312079 ==
4221 00:27:26.315768 Dram Type= 6, Freq= 0, CH_0, rank 1
4222 00:27:26.318684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4223 00:27:26.318767 ==
4224 00:27:26.322039 Write leveling (Byte 0): 33 => 33
4225 00:27:26.325744 Write leveling (Byte 1): 32 => 32
4226 00:27:26.328850 DramcWriteLeveling(PI) end<-----
4227 00:27:26.328930
4228 00:27:26.328991 ==
4229 00:27:26.332358 Dram Type= 6, Freq= 0, CH_0, rank 1
4230 00:27:26.335548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4231 00:27:26.335629 ==
4232 00:27:26.338939 [Gating] SW mode calibration
4233 00:27:26.345443 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4234 00:27:26.352081 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4235 00:27:26.355508 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4236 00:27:26.358790 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4237 00:27:26.365552 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4238 00:27:26.368623 0 9 12 | B1->B0 | 3131 3131 | 0 0 | (0 0) (0 1)
4239 00:27:26.372216 0 9 16 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
4240 00:27:26.378832 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4241 00:27:26.382404 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4242 00:27:26.385419 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4243 00:27:26.392011 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4244 00:27:26.395208 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4245 00:27:26.398838 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4246 00:27:26.405357 0 10 12 | B1->B0 | 2c2c 3333 | 0 0 | (0 0) (0 0)
4247 00:27:26.408897 0 10 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
4248 00:27:26.411852 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4249 00:27:26.418792 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4250 00:27:26.421939 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4251 00:27:26.425388 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4252 00:27:26.432293 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4253 00:27:26.435262 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4254 00:27:26.438445 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4255 00:27:26.445244 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4256 00:27:26.448901 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 00:27:26.451762 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 00:27:26.455357 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 00:27:26.461827 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 00:27:26.465207 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 00:27:26.468466 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 00:27:26.475440 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 00:27:26.478663 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 00:27:26.481888 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4265 00:27:26.488433 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4266 00:27:26.492088 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4267 00:27:26.495133 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4268 00:27:26.501822 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4269 00:27:26.504919 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4270 00:27:26.508385 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4271 00:27:26.515130 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4272 00:27:26.518113 Total UI for P1: 0, mck2ui 16
4273 00:27:26.521591 best dqsien dly found for B0: ( 0, 13, 12)
4274 00:27:26.525122 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4275 00:27:26.528191 Total UI for P1: 0, mck2ui 16
4276 00:27:26.531546 best dqsien dly found for B1: ( 0, 13, 14)
4277 00:27:26.534993 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4278 00:27:26.538447 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4279 00:27:26.538528
4280 00:27:26.541498 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4281 00:27:26.544893 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4282 00:27:26.548084 [Gating] SW calibration Done
4283 00:27:26.548168 ==
4284 00:27:26.551749 Dram Type= 6, Freq= 0, CH_0, rank 1
4285 00:27:26.558198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4286 00:27:26.558292 ==
4287 00:27:26.558353 RX Vref Scan: 0
4288 00:27:26.558409
4289 00:27:26.561382 RX Vref 0 -> 0, step: 1
4290 00:27:26.561459
4291 00:27:26.564918 RX Delay -230 -> 252, step: 16
4292 00:27:26.567900 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4293 00:27:26.571366 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4294 00:27:26.574561 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4295 00:27:26.581257 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4296 00:27:26.584752 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4297 00:27:26.588248 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4298 00:27:26.591259 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4299 00:27:26.594834 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4300 00:27:26.601432 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4301 00:27:26.604385 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4302 00:27:26.608076 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4303 00:27:26.611571 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4304 00:27:26.618057 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4305 00:27:26.621320 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4306 00:27:26.624828 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4307 00:27:26.627726 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4308 00:27:26.627806 ==
4309 00:27:26.631467 Dram Type= 6, Freq= 0, CH_0, rank 1
4310 00:27:26.637943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4311 00:27:26.638034 ==
4312 00:27:26.638096 DQS Delay:
4313 00:27:26.641164 DQS0 = 0, DQS1 = 0
4314 00:27:26.641241 DQM Delay:
4315 00:27:26.641301 DQM0 = 49, DQM1 = 42
4316 00:27:26.644545 DQ Delay:
4317 00:27:26.647955 DQ0 =41, DQ1 =57, DQ2 =41, DQ3 =49
4318 00:27:26.651512 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4319 00:27:26.654604 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =41
4320 00:27:26.658215 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =49
4321 00:27:26.658300
4322 00:27:26.658360
4323 00:27:26.658414 ==
4324 00:27:26.661209 Dram Type= 6, Freq= 0, CH_0, rank 1
4325 00:27:26.664673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4326 00:27:26.664795 ==
4327 00:27:26.664856
4328 00:27:26.664911
4329 00:27:26.667931 TX Vref Scan disable
4330 00:27:26.670957 == TX Byte 0 ==
4331 00:27:26.674738 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4332 00:27:26.677562 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4333 00:27:26.681166 == TX Byte 1 ==
4334 00:27:26.684151 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4335 00:27:26.687798 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4336 00:27:26.687880 ==
4337 00:27:26.691002 Dram Type= 6, Freq= 0, CH_0, rank 1
4338 00:27:26.694174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4339 00:27:26.697343 ==
4340 00:27:26.697421
4341 00:27:26.697481
4342 00:27:26.697537 TX Vref Scan disable
4343 00:27:26.701465 == TX Byte 0 ==
4344 00:27:26.704433 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4345 00:27:26.711090 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4346 00:27:26.711171 == TX Byte 1 ==
4347 00:27:26.714725 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4348 00:27:26.721300 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4349 00:27:26.721388
4350 00:27:26.721450 [DATLAT]
4351 00:27:26.721505 Freq=600, CH0 RK1
4352 00:27:26.721559
4353 00:27:26.724429 DATLAT Default: 0x9
4354 00:27:26.724507 0, 0xFFFF, sum = 0
4355 00:27:26.728283 1, 0xFFFF, sum = 0
4356 00:27:26.728362 2, 0xFFFF, sum = 0
4357 00:27:26.731110 3, 0xFFFF, sum = 0
4358 00:27:26.734767 4, 0xFFFF, sum = 0
4359 00:27:26.734848 5, 0xFFFF, sum = 0
4360 00:27:26.738009 6, 0xFFFF, sum = 0
4361 00:27:26.738089 7, 0xFFFF, sum = 0
4362 00:27:26.738150 8, 0x0, sum = 1
4363 00:27:26.741586 9, 0x0, sum = 2
4364 00:27:26.741668 10, 0x0, sum = 3
4365 00:27:26.744440 11, 0x0, sum = 4
4366 00:27:26.744520 best_step = 9
4367 00:27:26.744580
4368 00:27:26.744635 ==
4369 00:27:26.747841 Dram Type= 6, Freq= 0, CH_0, rank 1
4370 00:27:26.754771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4371 00:27:26.754881 ==
4372 00:27:26.754944 RX Vref Scan: 0
4373 00:27:26.755001
4374 00:27:26.757789 RX Vref 0 -> 0, step: 1
4375 00:27:26.757868
4376 00:27:26.761266 RX Delay -179 -> 252, step: 8
4377 00:27:26.764802 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4378 00:27:26.771274 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4379 00:27:26.774611 iDelay=205, Bit 2, Center 44 (-99 ~ 188) 288
4380 00:27:26.777789 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4381 00:27:26.781024 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4382 00:27:26.784375 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4383 00:27:26.791360 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4384 00:27:26.794458 iDelay=205, Bit 7, Center 56 (-91 ~ 204) 296
4385 00:27:26.797824 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4386 00:27:26.801457 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4387 00:27:26.804479 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4388 00:27:26.811034 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4389 00:27:26.814699 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4390 00:27:26.817711 iDelay=205, Bit 13, Center 44 (-99 ~ 188) 288
4391 00:27:26.821276 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4392 00:27:26.827906 iDelay=205, Bit 15, Center 44 (-99 ~ 188) 288
4393 00:27:26.828000 ==
4394 00:27:26.831086 Dram Type= 6, Freq= 0, CH_0, rank 1
4395 00:27:26.834597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4396 00:27:26.834681 ==
4397 00:27:26.834742 DQS Delay:
4398 00:27:26.837636 DQS0 = 0, DQS1 = 0
4399 00:27:26.837715 DQM Delay:
4400 00:27:26.841293 DQM0 = 48, DQM1 = 39
4401 00:27:26.841373 DQ Delay:
4402 00:27:26.844368 DQ0 =48, DQ1 =48, DQ2 =44, DQ3 =44
4403 00:27:26.847588 DQ4 =48, DQ5 =40, DQ6 =60, DQ7 =56
4404 00:27:26.850867 DQ8 =32, DQ9 =28, DQ10 =40, DQ11 =32
4405 00:27:26.854384 DQ12 =48, DQ13 =44, DQ14 =48, DQ15 =44
4406 00:27:26.854467
4407 00:27:26.854527
4408 00:27:26.861026 [DQSOSCAuto] RK1, (LSB)MR18= 0x6735, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 390 ps
4409 00:27:26.864113 CH0 RK1: MR19=808, MR18=6735
4410 00:27:26.870811 CH0_RK1: MR19=0x808, MR18=0x6735, DQSOSC=390, MR23=63, INC=172, DEC=114
4411 00:27:26.874526 [RxdqsGatingPostProcess] freq 600
4412 00:27:26.881004 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4413 00:27:26.881097 Pre-setting of DQS Precalculation
4414 00:27:26.887579 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4415 00:27:26.887691 ==
4416 00:27:26.890719 Dram Type= 6, Freq= 0, CH_1, rank 0
4417 00:27:26.894412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4418 00:27:26.894496 ==
4419 00:27:26.900725 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4420 00:27:26.907402 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4421 00:27:26.910994 [CA 0] Center 35 (5~66) winsize 62
4422 00:27:26.914038 [CA 1] Center 35 (5~66) winsize 62
4423 00:27:26.917649 [CA 2] Center 34 (4~65) winsize 62
4424 00:27:26.920677 [CA 3] Center 33 (3~64) winsize 62
4425 00:27:26.924384 [CA 4] Center 34 (3~65) winsize 63
4426 00:27:26.927330 [CA 5] Center 33 (3~64) winsize 62
4427 00:27:26.927414
4428 00:27:26.930835 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4429 00:27:26.930943
4430 00:27:26.934326 [CATrainingPosCal] consider 1 rank data
4431 00:27:26.937415 u2DelayCellTimex100 = 270/100 ps
4432 00:27:26.940736 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4433 00:27:26.944260 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4434 00:27:26.947346 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4435 00:27:26.950607 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4436 00:27:26.954310 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4437 00:27:26.957575 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4438 00:27:26.957691
4439 00:27:26.963961 CA PerBit enable=1, Macro0, CA PI delay=33
4440 00:27:26.964097
4441 00:27:26.964187 [CBTSetCACLKResult] CA Dly = 33
4442 00:27:26.967598 CS Dly: 4 (0~35)
4443 00:27:26.967679 ==
4444 00:27:26.970607 Dram Type= 6, Freq= 0, CH_1, rank 1
4445 00:27:26.974214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4446 00:27:26.974300 ==
4447 00:27:26.981040 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4448 00:27:26.987467 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4449 00:27:26.990852 [CA 0] Center 35 (5~66) winsize 62
4450 00:27:26.994292 [CA 1] Center 35 (5~66) winsize 62
4451 00:27:26.997924 [CA 2] Center 34 (4~65) winsize 62
4452 00:27:27.000723 [CA 3] Center 34 (4~65) winsize 62
4453 00:27:27.004102 [CA 4] Center 34 (4~65) winsize 62
4454 00:27:27.007847 [CA 5] Center 34 (3~65) winsize 63
4455 00:27:27.007933
4456 00:27:27.010787 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4457 00:27:27.010868
4458 00:27:27.013904 [CATrainingPosCal] consider 2 rank data
4459 00:27:27.017567 u2DelayCellTimex100 = 270/100 ps
4460 00:27:27.020622 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4461 00:27:27.024206 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4462 00:27:27.027656 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4463 00:27:27.030633 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4464 00:27:27.033830 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4465 00:27:27.037371 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4466 00:27:27.037455
4467 00:27:27.044157 CA PerBit enable=1, Macro0, CA PI delay=33
4468 00:27:27.044243
4469 00:27:27.047194 [CBTSetCACLKResult] CA Dly = 33
4470 00:27:27.047273 CS Dly: 4 (0~36)
4471 00:27:27.047334
4472 00:27:27.050617 ----->DramcWriteLeveling(PI) begin...
4473 00:27:27.050699 ==
4474 00:27:27.054033 Dram Type= 6, Freq= 0, CH_1, rank 0
4475 00:27:27.057376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4476 00:27:27.057459 ==
4477 00:27:27.060579 Write leveling (Byte 0): 28 => 28
4478 00:27:27.063705 Write leveling (Byte 1): 29 => 29
4479 00:27:27.067116 DramcWriteLeveling(PI) end<-----
4480 00:27:27.067197
4481 00:27:27.067258 ==
4482 00:27:27.070624 Dram Type= 6, Freq= 0, CH_1, rank 0
4483 00:27:27.076970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4484 00:27:27.077058 ==
4485 00:27:27.077121 [Gating] SW mode calibration
4486 00:27:27.087057 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4487 00:27:27.090643 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4488 00:27:27.094087 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4489 00:27:27.100888 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4490 00:27:27.103746 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4491 00:27:27.107095 0 9 12 | B1->B0 | 2f2f 2e2e | 1 1 | (1 1) (1 0)
4492 00:27:27.113666 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4493 00:27:27.117277 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4494 00:27:27.120454 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4495 00:27:27.127236 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4496 00:27:27.130382 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4497 00:27:27.134091 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4498 00:27:27.140674 0 10 8 | B1->B0 | 2424 2b2b | 0 0 | (0 0) (0 0)
4499 00:27:27.143853 0 10 12 | B1->B0 | 3535 3939 | 0 0 | (0 0) (0 0)
4500 00:27:27.147368 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4501 00:27:27.153960 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4502 00:27:27.156989 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4503 00:27:27.160601 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4504 00:27:27.166913 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4505 00:27:27.170389 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4506 00:27:27.173622 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4507 00:27:27.177216 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 00:27:27.183991 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 00:27:27.187077 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 00:27:27.190581 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4511 00:27:27.197207 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4512 00:27:27.200629 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4513 00:27:27.204024 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4514 00:27:27.210278 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4515 00:27:27.213779 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4516 00:27:27.217275 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4517 00:27:27.223705 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4518 00:27:27.226936 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4519 00:27:27.230561 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4520 00:27:27.237010 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4521 00:27:27.240572 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4522 00:27:27.243692 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4523 00:27:27.250353 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4524 00:27:27.250448 Total UI for P1: 0, mck2ui 16
4525 00:27:27.253917 best dqsien dly found for B0: ( 0, 13, 10)
4526 00:27:27.260602 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4527 00:27:27.263879 Total UI for P1: 0, mck2ui 16
4528 00:27:27.267013 best dqsien dly found for B1: ( 0, 13, 12)
4529 00:27:27.270569 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4530 00:27:27.274011 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4531 00:27:27.274097
4532 00:27:27.277459 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4533 00:27:27.280813 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4534 00:27:27.283916 [Gating] SW calibration Done
4535 00:27:27.284020 ==
4536 00:27:27.287050 Dram Type= 6, Freq= 0, CH_1, rank 0
4537 00:27:27.290471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4538 00:27:27.290554 ==
4539 00:27:27.294030 RX Vref Scan: 0
4540 00:27:27.294111
4541 00:27:27.297050 RX Vref 0 -> 0, step: 1
4542 00:27:27.297131
4543 00:27:27.297212 RX Delay -230 -> 252, step: 16
4544 00:27:27.303696 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4545 00:27:27.307414 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4546 00:27:27.310324 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4547 00:27:27.313692 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4548 00:27:27.320636 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4549 00:27:27.324047 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4550 00:27:27.327370 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4551 00:27:27.330389 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4552 00:27:27.333892 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4553 00:27:27.340698 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4554 00:27:27.343941 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4555 00:27:27.347530 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4556 00:27:27.350485 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4557 00:27:27.356939 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4558 00:27:27.360586 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4559 00:27:27.363595 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4560 00:27:27.363675 ==
4561 00:27:27.367178 Dram Type= 6, Freq= 0, CH_1, rank 0
4562 00:27:27.370612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4563 00:27:27.370694 ==
4564 00:27:27.374017 DQS Delay:
4565 00:27:27.374097 DQS0 = 0, DQS1 = 0
4566 00:27:27.376978 DQM Delay:
4567 00:27:27.377057 DQM0 = 54, DQM1 = 46
4568 00:27:27.377117 DQ Delay:
4569 00:27:27.380504 DQ0 =57, DQ1 =49, DQ2 =49, DQ3 =49
4570 00:27:27.383679 DQ4 =49, DQ5 =65, DQ6 =65, DQ7 =49
4571 00:27:27.387163 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4572 00:27:27.390396 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4573 00:27:27.390477
4574 00:27:27.390537
4575 00:27:27.393498 ==
4576 00:27:27.393577 Dram Type= 6, Freq= 0, CH_1, rank 0
4577 00:27:27.400424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4578 00:27:27.400518 ==
4579 00:27:27.400581
4580 00:27:27.400638
4581 00:27:27.403511 TX Vref Scan disable
4582 00:27:27.403590 == TX Byte 0 ==
4583 00:27:27.407075 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4584 00:27:27.413940 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4585 00:27:27.414028 == TX Byte 1 ==
4586 00:27:27.417113 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4587 00:27:27.423553 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4588 00:27:27.423642 ==
4589 00:27:27.427004 Dram Type= 6, Freq= 0, CH_1, rank 0
4590 00:27:27.430312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4591 00:27:27.430391 ==
4592 00:27:27.430451
4593 00:27:27.430506
4594 00:27:27.433384 TX Vref Scan disable
4595 00:27:27.436901 == TX Byte 0 ==
4596 00:27:27.440402 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4597 00:27:27.443837 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4598 00:27:27.446937 == TX Byte 1 ==
4599 00:27:27.450285 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4600 00:27:27.453813 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4601 00:27:27.453891
4602 00:27:27.456839 [DATLAT]
4603 00:27:27.456915 Freq=600, CH1 RK0
4604 00:27:27.456976
4605 00:27:27.460317 DATLAT Default: 0x9
4606 00:27:27.460394 0, 0xFFFF, sum = 0
4607 00:27:27.463358 1, 0xFFFF, sum = 0
4608 00:27:27.463435 2, 0xFFFF, sum = 0
4609 00:27:27.467133 3, 0xFFFF, sum = 0
4610 00:27:27.467210 4, 0xFFFF, sum = 0
4611 00:27:27.470044 5, 0xFFFF, sum = 0
4612 00:27:27.470122 6, 0xFFFF, sum = 0
4613 00:27:27.473376 7, 0xFFFF, sum = 0
4614 00:27:27.473453 8, 0x0, sum = 1
4615 00:27:27.476732 9, 0x0, sum = 2
4616 00:27:27.476827 10, 0x0, sum = 3
4617 00:27:27.480272 11, 0x0, sum = 4
4618 00:27:27.480338 best_step = 9
4619 00:27:27.480394
4620 00:27:27.480448 ==
4621 00:27:27.483884 Dram Type= 6, Freq= 0, CH_1, rank 0
4622 00:27:27.486929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4623 00:27:27.487007 ==
4624 00:27:27.490140 RX Vref Scan: 1
4625 00:27:27.490217
4626 00:27:27.493657 RX Vref 0 -> 0, step: 1
4627 00:27:27.493734
4628 00:27:27.493793 RX Delay -163 -> 252, step: 8
4629 00:27:27.493850
4630 00:27:27.497068 Set Vref, RX VrefLevel [Byte0]: 51
4631 00:27:27.500002 [Byte1]: 51
4632 00:27:27.504659
4633 00:27:27.504773 Final RX Vref Byte 0 = 51 to rank0
4634 00:27:27.508089 Final RX Vref Byte 1 = 51 to rank0
4635 00:27:27.511639 Final RX Vref Byte 0 = 51 to rank1
4636 00:27:27.514667 Final RX Vref Byte 1 = 51 to rank1==
4637 00:27:27.518066 Dram Type= 6, Freq= 0, CH_1, rank 0
4638 00:27:27.524638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4639 00:27:27.524736 ==
4640 00:27:27.524810 DQS Delay:
4641 00:27:27.524867 DQS0 = 0, DQS1 = 0
4642 00:27:27.528232 DQM Delay:
4643 00:27:27.528310 DQM0 = 48, DQM1 = 41
4644 00:27:27.531305 DQ Delay:
4645 00:27:27.534998 DQ0 =52, DQ1 =48, DQ2 =36, DQ3 =44
4646 00:27:27.535076 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =44
4647 00:27:27.538488 DQ8 =28, DQ9 =28, DQ10 =44, DQ11 =36
4648 00:27:27.541426 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =48
4649 00:27:27.544613
4650 00:27:27.544690
4651 00:27:27.551406 [DQSOSCAuto] RK0, (LSB)MR18= 0x5178, (MSB)MR19= 0x808, tDQSOscB0 = 387 ps tDQSOscB1 = 394 ps
4652 00:27:27.554823 CH1 RK0: MR19=808, MR18=5178
4653 00:27:27.561653 CH1_RK0: MR19=0x808, MR18=0x5178, DQSOSC=387, MR23=63, INC=175, DEC=116
4654 00:27:27.561731
4655 00:27:27.564949 ----->DramcWriteLeveling(PI) begin...
4656 00:27:27.565028 ==
4657 00:27:27.567983 Dram Type= 6, Freq= 0, CH_1, rank 1
4658 00:27:27.571661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4659 00:27:27.571739 ==
4660 00:27:27.575121 Write leveling (Byte 0): 31 => 31
4661 00:27:27.578246 Write leveling (Byte 1): 31 => 31
4662 00:27:27.581477 DramcWriteLeveling(PI) end<-----
4663 00:27:27.581554
4664 00:27:27.581614 ==
4665 00:27:27.584674 Dram Type= 6, Freq= 0, CH_1, rank 1
4666 00:27:27.588218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4667 00:27:27.588296 ==
4668 00:27:27.591309 [Gating] SW mode calibration
4669 00:27:27.598433 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4670 00:27:27.604757 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4671 00:27:27.608120 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4672 00:27:27.611445 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4673 00:27:27.617783 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4674 00:27:27.621630 0 9 12 | B1->B0 | 2c2c 3232 | 0 1 | (1 1) (1 0)
4675 00:27:27.624678 0 9 16 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
4676 00:27:27.631529 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4677 00:27:27.634771 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4678 00:27:27.638307 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4679 00:27:27.644470 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4680 00:27:27.648037 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4681 00:27:27.651619 0 10 8 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
4682 00:27:27.657785 0 10 12 | B1->B0 | 3939 2c2c | 0 0 | (0 0) (0 0)
4683 00:27:27.661142 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4684 00:27:27.664592 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4685 00:27:27.671371 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4686 00:27:27.674407 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4687 00:27:27.677882 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4688 00:27:27.684355 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4689 00:27:27.687907 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4690 00:27:27.691504 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4691 00:27:27.694610 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4692 00:27:27.701121 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4693 00:27:27.704698 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4694 00:27:27.707785 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4695 00:27:27.714730 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4696 00:27:27.718051 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4697 00:27:27.721251 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4698 00:27:27.727908 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4699 00:27:27.731054 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4700 00:27:27.734682 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4701 00:27:27.741188 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4702 00:27:27.744095 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4703 00:27:27.747833 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4704 00:27:27.754172 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4705 00:27:27.757658 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4706 00:27:27.761088 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4707 00:27:27.764075 Total UI for P1: 0, mck2ui 16
4708 00:27:27.767815 best dqsien dly found for B0: ( 0, 13, 8)
4709 00:27:27.770664 Total UI for P1: 0, mck2ui 16
4710 00:27:27.774298 best dqsien dly found for B1: ( 0, 13, 10)
4711 00:27:27.777473 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4712 00:27:27.780489 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4713 00:27:27.780566
4714 00:27:27.787533 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4715 00:27:27.790950 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4716 00:27:27.791028 [Gating] SW calibration Done
4717 00:27:27.794088 ==
4718 00:27:27.797588 Dram Type= 6, Freq= 0, CH_1, rank 1
4719 00:27:27.800612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4720 00:27:27.800691 ==
4721 00:27:27.800798 RX Vref Scan: 0
4722 00:27:27.800854
4723 00:27:27.804197 RX Vref 0 -> 0, step: 1
4724 00:27:27.804274
4725 00:27:27.807282 RX Delay -230 -> 252, step: 16
4726 00:27:27.810697 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4727 00:27:27.814290 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4728 00:27:27.820336 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4729 00:27:27.823700 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4730 00:27:27.826995 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4731 00:27:27.830317 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4732 00:27:27.837038 iDelay=218, Bit 6, Center 49 (-102 ~ 201) 304
4733 00:27:27.840101 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4734 00:27:27.843520 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4735 00:27:27.846916 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4736 00:27:27.850002 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4737 00:27:27.856978 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4738 00:27:27.860344 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4739 00:27:27.863543 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4740 00:27:27.867072 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4741 00:27:27.873638 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4742 00:27:27.873720 ==
4743 00:27:27.877020 Dram Type= 6, Freq= 0, CH_1, rank 1
4744 00:27:27.879940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4745 00:27:27.880017 ==
4746 00:27:27.880078 DQS Delay:
4747 00:27:27.883271 DQS0 = 0, DQS1 = 0
4748 00:27:27.883348 DQM Delay:
4749 00:27:27.886661 DQM0 = 49, DQM1 = 44
4750 00:27:27.886738 DQ Delay:
4751 00:27:27.890163 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4752 00:27:27.893371 DQ4 =49, DQ5 =57, DQ6 =49, DQ7 =49
4753 00:27:27.896401 DQ8 =25, DQ9 =33, DQ10 =41, DQ11 =41
4754 00:27:27.899957 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4755 00:27:27.900035
4756 00:27:27.900094
4757 00:27:27.900149 ==
4758 00:27:27.902941 Dram Type= 6, Freq= 0, CH_1, rank 1
4759 00:27:27.906491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4760 00:27:27.909657 ==
4761 00:27:27.909733
4762 00:27:27.909793
4763 00:27:27.909849 TX Vref Scan disable
4764 00:27:27.913061 == TX Byte 0 ==
4765 00:27:27.916476 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4766 00:27:27.923158 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4767 00:27:27.923249 == TX Byte 1 ==
4768 00:27:27.926167 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4769 00:27:27.933157 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4770 00:27:27.933253 ==
4771 00:27:27.936463 Dram Type= 6, Freq= 0, CH_1, rank 1
4772 00:27:27.939811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4773 00:27:27.939900 ==
4774 00:27:27.939961
4775 00:27:27.940017
4776 00:27:27.942811 TX Vref Scan disable
4777 00:27:27.946305 == TX Byte 0 ==
4778 00:27:27.949601 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4779 00:27:27.952821 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4780 00:27:27.956144 == TX Byte 1 ==
4781 00:27:27.959568 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4782 00:27:27.963165 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4783 00:27:27.963256
4784 00:27:27.963318 [DATLAT]
4785 00:27:27.966451 Freq=600, CH1 RK1
4786 00:27:27.966532
4787 00:27:27.966613 DATLAT Default: 0x9
4788 00:27:27.969653 0, 0xFFFF, sum = 0
4789 00:27:27.969750 1, 0xFFFF, sum = 0
4790 00:27:27.972604 2, 0xFFFF, sum = 0
4791 00:27:27.976074 3, 0xFFFF, sum = 0
4792 00:27:27.976168 4, 0xFFFF, sum = 0
4793 00:27:27.979593 5, 0xFFFF, sum = 0
4794 00:27:27.979718 6, 0xFFFF, sum = 0
4795 00:27:27.982837 7, 0xFFFF, sum = 0
4796 00:27:27.982933 8, 0x0, sum = 1
4797 00:27:27.983116 9, 0x0, sum = 2
4798 00:27:27.986315 10, 0x0, sum = 3
4799 00:27:27.986476 11, 0x0, sum = 4
4800 00:27:27.989696 best_step = 9
4801 00:27:27.989804
4802 00:27:27.989891 ==
4803 00:27:27.992764 Dram Type= 6, Freq= 0, CH_1, rank 1
4804 00:27:27.996282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4805 00:27:27.996397 ==
4806 00:27:27.999276 RX Vref Scan: 0
4807 00:27:27.999419
4808 00:27:27.999505 RX Vref 0 -> 0, step: 1
4809 00:27:27.999587
4810 00:27:28.002795 RX Delay -179 -> 252, step: 8
4811 00:27:28.009805 iDelay=205, Bit 0, Center 52 (-83 ~ 188) 272
4812 00:27:28.013391 iDelay=205, Bit 1, Center 44 (-91 ~ 180) 272
4813 00:27:28.016986 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4814 00:27:28.019899 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4815 00:27:28.023409 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4816 00:27:28.030058 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4817 00:27:28.033584 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4818 00:27:28.036621 iDelay=205, Bit 7, Center 48 (-91 ~ 188) 280
4819 00:27:28.039977 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4820 00:27:28.043319 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4821 00:27:28.050138 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4822 00:27:28.053600 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4823 00:27:28.056907 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4824 00:27:28.060254 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4825 00:27:28.066744 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4826 00:27:28.070261 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4827 00:27:28.070342 ==
4828 00:27:28.073578 Dram Type= 6, Freq= 0, CH_1, rank 1
4829 00:27:28.076589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4830 00:27:28.076691 ==
4831 00:27:28.079915 DQS Delay:
4832 00:27:28.079993 DQS0 = 0, DQS1 = 0
4833 00:27:28.080053 DQM Delay:
4834 00:27:28.083435 DQM0 = 48, DQM1 = 44
4835 00:27:28.083513 DQ Delay:
4836 00:27:28.086488 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4837 00:27:28.090042 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4838 00:27:28.093050 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36
4839 00:27:28.096448 DQ12 =48, DQ13 =52, DQ14 =48, DQ15 =56
4840 00:27:28.096526
4841 00:27:28.096586
4842 00:27:28.106756 [DQSOSCAuto] RK1, (LSB)MR18= 0x591f, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
4843 00:27:28.106857 CH1 RK1: MR19=808, MR18=591F
4844 00:27:28.113152 CH1_RK1: MR19=0x808, MR18=0x591F, DQSOSC=393, MR23=63, INC=169, DEC=113
4845 00:27:28.116645 [RxdqsGatingPostProcess] freq 600
4846 00:27:28.123213 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4847 00:27:28.126769 Pre-setting of DQS Precalculation
4848 00:27:28.129876 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4849 00:27:28.136624 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4850 00:27:28.146289 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4851 00:27:28.146395
4852 00:27:28.146455
4853 00:27:28.149840 [Calibration Summary] 1200 Mbps
4854 00:27:28.149919 CH 0, Rank 0
4855 00:27:28.152998 SW Impedance : PASS
4856 00:27:28.153077 DUTY Scan : NO K
4857 00:27:28.156314 ZQ Calibration : PASS
4858 00:27:28.156416 Jitter Meter : NO K
4859 00:27:28.159990 CBT Training : PASS
4860 00:27:28.163071 Write leveling : PASS
4861 00:27:28.163150 RX DQS gating : PASS
4862 00:27:28.166131 RX DQ/DQS(RDDQC) : PASS
4863 00:27:28.169609 TX DQ/DQS : PASS
4864 00:27:28.169688 RX DATLAT : PASS
4865 00:27:28.173200 RX DQ/DQS(Engine): PASS
4866 00:27:28.176347 TX OE : NO K
4867 00:27:28.176426 All Pass.
4868 00:27:28.176487
4869 00:27:28.176544 CH 0, Rank 1
4870 00:27:28.179659 SW Impedance : PASS
4871 00:27:28.182976 DUTY Scan : NO K
4872 00:27:28.183054 ZQ Calibration : PASS
4873 00:27:28.186490 Jitter Meter : NO K
4874 00:27:28.189394 CBT Training : PASS
4875 00:27:28.189472 Write leveling : PASS
4876 00:27:28.193006 RX DQS gating : PASS
4877 00:27:28.196308 RX DQ/DQS(RDDQC) : PASS
4878 00:27:28.196386 TX DQ/DQS : PASS
4879 00:27:28.199642 RX DATLAT : PASS
4880 00:27:28.199720 RX DQ/DQS(Engine): PASS
4881 00:27:28.203173 TX OE : NO K
4882 00:27:28.203251 All Pass.
4883 00:27:28.203311
4884 00:27:28.206292 CH 1, Rank 0
4885 00:27:28.206370 SW Impedance : PASS
4886 00:27:28.209915 DUTY Scan : NO K
4887 00:27:28.212936 ZQ Calibration : PASS
4888 00:27:28.213014 Jitter Meter : NO K
4889 00:27:28.216360 CBT Training : PASS
4890 00:27:28.219570 Write leveling : PASS
4891 00:27:28.219648 RX DQS gating : PASS
4892 00:27:28.222752 RX DQ/DQS(RDDQC) : PASS
4893 00:27:28.225998 TX DQ/DQS : PASS
4894 00:27:28.226082 RX DATLAT : PASS
4895 00:27:28.229545 RX DQ/DQS(Engine): PASS
4896 00:27:28.232955 TX OE : NO K
4897 00:27:28.233034 All Pass.
4898 00:27:28.233094
4899 00:27:28.233150 CH 1, Rank 1
4900 00:27:28.236047 SW Impedance : PASS
4901 00:27:28.239573 DUTY Scan : NO K
4902 00:27:28.239652 ZQ Calibration : PASS
4903 00:27:28.242820 Jitter Meter : NO K
4904 00:27:28.246379 CBT Training : PASS
4905 00:27:28.246457 Write leveling : PASS
4906 00:27:28.249548 RX DQS gating : PASS
4907 00:27:28.249626 RX DQ/DQS(RDDQC) : PASS
4908 00:27:28.253015 TX DQ/DQS : PASS
4909 00:27:28.255952 RX DATLAT : PASS
4910 00:27:28.256029 RX DQ/DQS(Engine): PASS
4911 00:27:28.259197 TX OE : NO K
4912 00:27:28.259275 All Pass.
4913 00:27:28.259336
4914 00:27:28.262849 DramC Write-DBI off
4915 00:27:28.266322 PER_BANK_REFRESH: Hybrid Mode
4916 00:27:28.266400 TX_TRACKING: ON
4917 00:27:28.276328 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4918 00:27:28.279554 [FAST_K] Save calibration result to emmc
4919 00:27:28.283001 dramc_set_vcore_voltage set vcore to 662500
4920 00:27:28.286149 Read voltage for 933, 3
4921 00:27:28.286226 Vio18 = 0
4922 00:27:28.286287 Vcore = 662500
4923 00:27:28.289670 Vdram = 0
4924 00:27:28.289748 Vddq = 0
4925 00:27:28.289809 Vmddr = 0
4926 00:27:28.296659 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4927 00:27:28.299516 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4928 00:27:28.302720 MEM_TYPE=3, freq_sel=17
4929 00:27:28.306728 sv_algorithm_assistance_LP4_1600
4930 00:27:28.309820 ============ PULL DRAM RESETB DOWN ============
4931 00:27:28.312888 ========== PULL DRAM RESETB DOWN end =========
4932 00:27:28.319440 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4933 00:27:28.323026 ===================================
4934 00:27:28.323104 LPDDR4 DRAM CONFIGURATION
4935 00:27:28.326121 ===================================
4936 00:27:28.329917 EX_ROW_EN[0] = 0x0
4937 00:27:28.332900 EX_ROW_EN[1] = 0x0
4938 00:27:28.332978 LP4Y_EN = 0x0
4939 00:27:28.336246 WORK_FSP = 0x0
4940 00:27:28.336323 WL = 0x3
4941 00:27:28.339728 RL = 0x3
4942 00:27:28.339806 BL = 0x2
4943 00:27:28.342643 RPST = 0x0
4944 00:27:28.342720 RD_PRE = 0x0
4945 00:27:28.346119 WR_PRE = 0x1
4946 00:27:28.346197 WR_PST = 0x0
4947 00:27:28.349793 DBI_WR = 0x0
4948 00:27:28.349870 DBI_RD = 0x0
4949 00:27:28.352952 OTF = 0x1
4950 00:27:28.356042 ===================================
4951 00:27:28.359584 ===================================
4952 00:27:28.359662 ANA top config
4953 00:27:28.363086 ===================================
4954 00:27:28.366021 DLL_ASYNC_EN = 0
4955 00:27:28.369396 ALL_SLAVE_EN = 1
4956 00:27:28.372789 NEW_RANK_MODE = 1
4957 00:27:28.372868 DLL_IDLE_MODE = 1
4958 00:27:28.376326 LP45_APHY_COMB_EN = 1
4959 00:27:28.379320 TX_ODT_DIS = 1
4960 00:27:28.383060 NEW_8X_MODE = 1
4961 00:27:28.386040 ===================================
4962 00:27:28.389338 ===================================
4963 00:27:28.392832 data_rate = 1866
4964 00:27:28.392910 CKR = 1
4965 00:27:28.396302 DQ_P2S_RATIO = 8
4966 00:27:28.399509 ===================================
4967 00:27:28.402824 CA_P2S_RATIO = 8
4968 00:27:28.406041 DQ_CA_OPEN = 0
4969 00:27:28.409412 DQ_SEMI_OPEN = 0
4970 00:27:28.412669 CA_SEMI_OPEN = 0
4971 00:27:28.412785 CA_FULL_RATE = 0
4972 00:27:28.415974 DQ_CKDIV4_EN = 1
4973 00:27:28.419093 CA_CKDIV4_EN = 1
4974 00:27:28.422597 CA_PREDIV_EN = 0
4975 00:27:28.425689 PH8_DLY = 0
4976 00:27:28.429093 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4977 00:27:28.429171 DQ_AAMCK_DIV = 4
4978 00:27:28.432722 CA_AAMCK_DIV = 4
4979 00:27:28.435816 CA_ADMCK_DIV = 4
4980 00:27:28.439333 DQ_TRACK_CA_EN = 0
4981 00:27:28.442410 CA_PICK = 933
4982 00:27:28.445588 CA_MCKIO = 933
4983 00:27:28.445666 MCKIO_SEMI = 0
4984 00:27:28.448962 PLL_FREQ = 3732
4985 00:27:28.452412 DQ_UI_PI_RATIO = 32
4986 00:27:28.455996 CA_UI_PI_RATIO = 0
4987 00:27:28.458973 ===================================
4988 00:27:28.462412 ===================================
4989 00:27:28.465570 memory_type:LPDDR4
4990 00:27:28.465647 GP_NUM : 10
4991 00:27:28.469129 SRAM_EN : 1
4992 00:27:28.472577 MD32_EN : 0
4993 00:27:28.475490 ===================================
4994 00:27:28.475568 [ANA_INIT] >>>>>>>>>>>>>>
4995 00:27:28.479000 <<<<<< [CONFIGURE PHASE]: ANA_TX
4996 00:27:28.482335 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4997 00:27:28.485577 ===================================
4998 00:27:28.488902 data_rate = 1866,PCW = 0X8f00
4999 00:27:28.492489 ===================================
5000 00:27:28.495402 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5001 00:27:28.502645 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5002 00:27:28.505646 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5003 00:27:28.512370 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5004 00:27:28.515646 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5005 00:27:28.518759 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5006 00:27:28.518838 [ANA_INIT] flow start
5007 00:27:28.522329 [ANA_INIT] PLL >>>>>>>>
5008 00:27:28.525645 [ANA_INIT] PLL <<<<<<<<
5009 00:27:28.525723 [ANA_INIT] MIDPI >>>>>>>>
5010 00:27:28.528569 [ANA_INIT] MIDPI <<<<<<<<
5011 00:27:28.532037 [ANA_INIT] DLL >>>>>>>>
5012 00:27:28.532114 [ANA_INIT] flow end
5013 00:27:28.538805 ============ LP4 DIFF to SE enter ============
5014 00:27:28.541855 ============ LP4 DIFF to SE exit ============
5015 00:27:28.545578 [ANA_INIT] <<<<<<<<<<<<<
5016 00:27:28.548628 [Flow] Enable top DCM control >>>>>
5017 00:27:28.552052 [Flow] Enable top DCM control <<<<<
5018 00:27:28.555346 Enable DLL master slave shuffle
5019 00:27:28.558822 ==============================================================
5020 00:27:28.561890 Gating Mode config
5021 00:27:28.565339 ==============================================================
5022 00:27:28.568568 Config description:
5023 00:27:28.578541 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5024 00:27:28.585074 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5025 00:27:28.588397 SELPH_MODE 0: By rank 1: By Phase
5026 00:27:28.595108 ==============================================================
5027 00:27:28.598618 GAT_TRACK_EN = 1
5028 00:27:28.601798 RX_GATING_MODE = 2
5029 00:27:28.605140 RX_GATING_TRACK_MODE = 2
5030 00:27:28.608375 SELPH_MODE = 1
5031 00:27:28.612023 PICG_EARLY_EN = 1
5032 00:27:28.612100 VALID_LAT_VALUE = 1
5033 00:27:28.618573 ==============================================================
5034 00:27:28.621957 Enter into Gating configuration >>>>
5035 00:27:28.624914 Exit from Gating configuration <<<<
5036 00:27:28.628518 Enter into DVFS_PRE_config >>>>>
5037 00:27:28.638456 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5038 00:27:28.641599 Exit from DVFS_PRE_config <<<<<
5039 00:27:28.645105 Enter into PICG configuration >>>>
5040 00:27:28.648582 Exit from PICG configuration <<<<
5041 00:27:28.652075 [RX_INPUT] configuration >>>>>
5042 00:27:28.655084 [RX_INPUT] configuration <<<<<
5043 00:27:28.658304 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5044 00:27:28.664952 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5045 00:27:28.671986 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5046 00:27:28.678345 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5047 00:27:28.685076 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5048 00:27:28.688262 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5049 00:27:28.694948 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5050 00:27:28.698219 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5051 00:27:28.701832 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5052 00:27:28.704950 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5053 00:27:28.711672 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5054 00:27:28.715133 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5055 00:27:28.718360 ===================================
5056 00:27:28.721858 LPDDR4 DRAM CONFIGURATION
5057 00:27:28.724878 ===================================
5058 00:27:28.724956 EX_ROW_EN[0] = 0x0
5059 00:27:28.728261 EX_ROW_EN[1] = 0x0
5060 00:27:28.728339 LP4Y_EN = 0x0
5061 00:27:28.731717 WORK_FSP = 0x0
5062 00:27:28.731794 WL = 0x3
5063 00:27:28.734720 RL = 0x3
5064 00:27:28.734797 BL = 0x2
5065 00:27:28.738218 RPST = 0x0
5066 00:27:28.738295 RD_PRE = 0x0
5067 00:27:28.741539 WR_PRE = 0x1
5068 00:27:28.741616 WR_PST = 0x0
5069 00:27:28.745028 DBI_WR = 0x0
5070 00:27:28.745106 DBI_RD = 0x0
5071 00:27:28.748107 OTF = 0x1
5072 00:27:28.751576 ===================================
5073 00:27:28.755186 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5074 00:27:28.758202 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5075 00:27:28.764927 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5076 00:27:28.768128 ===================================
5077 00:27:28.768210 LPDDR4 DRAM CONFIGURATION
5078 00:27:28.771626 ===================================
5079 00:27:28.774697 EX_ROW_EN[0] = 0x10
5080 00:27:28.778316 EX_ROW_EN[1] = 0x0
5081 00:27:28.778395 LP4Y_EN = 0x0
5082 00:27:28.781739 WORK_FSP = 0x0
5083 00:27:28.781817 WL = 0x3
5084 00:27:28.784836 RL = 0x3
5085 00:27:28.784915 BL = 0x2
5086 00:27:28.788007 RPST = 0x0
5087 00:27:28.788084 RD_PRE = 0x0
5088 00:27:28.791416 WR_PRE = 0x1
5089 00:27:28.791493 WR_PST = 0x0
5090 00:27:28.795096 DBI_WR = 0x0
5091 00:27:28.795175 DBI_RD = 0x0
5092 00:27:28.798025 OTF = 0x1
5093 00:27:28.801755 ===================================
5094 00:27:28.808555 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5095 00:27:28.811578 nWR fixed to 30
5096 00:27:28.811661 [ModeRegInit_LP4] CH0 RK0
5097 00:27:28.815073 [ModeRegInit_LP4] CH0 RK1
5098 00:27:28.818330 [ModeRegInit_LP4] CH1 RK0
5099 00:27:28.821419 [ModeRegInit_LP4] CH1 RK1
5100 00:27:28.821497 match AC timing 9
5101 00:27:28.828092 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5102 00:27:28.831404 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5103 00:27:28.834835 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5104 00:27:28.841361 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5105 00:27:28.844677 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5106 00:27:28.844795 ==
5107 00:27:28.847941 Dram Type= 6, Freq= 0, CH_0, rank 0
5108 00:27:28.851410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5109 00:27:28.851493 ==
5110 00:27:28.858035 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5111 00:27:28.864518 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5112 00:27:28.867888 [CA 0] Center 38 (7~69) winsize 63
5113 00:27:28.871587 [CA 1] Center 38 (7~69) winsize 63
5114 00:27:28.874625 [CA 2] Center 35 (5~66) winsize 62
5115 00:27:28.877692 [CA 3] Center 34 (4~65) winsize 62
5116 00:27:28.881215 [CA 4] Center 34 (4~65) winsize 62
5117 00:27:28.884312 [CA 5] Center 33 (3~64) winsize 62
5118 00:27:28.884390
5119 00:27:28.888032 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5120 00:27:28.888110
5121 00:27:28.891485 [CATrainingPosCal] consider 1 rank data
5122 00:27:28.894583 u2DelayCellTimex100 = 270/100 ps
5123 00:27:28.897498 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5124 00:27:28.901113 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5125 00:27:28.904426 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5126 00:27:28.907506 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5127 00:27:28.911094 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5128 00:27:28.914166 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5129 00:27:28.914245
5130 00:27:28.920685 CA PerBit enable=1, Macro0, CA PI delay=33
5131 00:27:28.920792
5132 00:27:28.924289 [CBTSetCACLKResult] CA Dly = 33
5133 00:27:28.924366 CS Dly: 7 (0~38)
5134 00:27:28.924426 ==
5135 00:27:28.927413 Dram Type= 6, Freq= 0, CH_0, rank 1
5136 00:27:28.930906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5137 00:27:28.930985 ==
5138 00:27:28.937412 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5139 00:27:28.944087 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5140 00:27:28.947587 [CA 0] Center 38 (8~69) winsize 62
5141 00:27:28.950985 [CA 1] Center 38 (8~69) winsize 62
5142 00:27:28.954421 [CA 2] Center 36 (6~66) winsize 61
5143 00:27:28.957492 [CA 3] Center 35 (5~66) winsize 62
5144 00:27:28.961029 [CA 4] Center 34 (4~65) winsize 62
5145 00:27:28.964079 [CA 5] Center 34 (4~65) winsize 62
5146 00:27:28.964157
5147 00:27:28.967385 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5148 00:27:28.967462
5149 00:27:28.970769 [CATrainingPosCal] consider 2 rank data
5150 00:27:28.973902 u2DelayCellTimex100 = 270/100 ps
5151 00:27:28.977399 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5152 00:27:28.980467 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5153 00:27:28.984102 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5154 00:27:28.987626 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5155 00:27:28.990834 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5156 00:27:28.993905 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5157 00:27:28.997391
5158 00:27:29.000679 CA PerBit enable=1, Macro0, CA PI delay=34
5159 00:27:29.000795
5160 00:27:29.004040 [CBTSetCACLKResult] CA Dly = 34
5161 00:27:29.004120 CS Dly: 7 (0~39)
5162 00:27:29.004180
5163 00:27:29.007627 ----->DramcWriteLeveling(PI) begin...
5164 00:27:29.007707 ==
5165 00:27:29.010620 Dram Type= 6, Freq= 0, CH_0, rank 0
5166 00:27:29.014075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5167 00:27:29.017082 ==
5168 00:27:29.017161 Write leveling (Byte 0): 33 => 33
5169 00:27:29.020939 Write leveling (Byte 1): 31 => 31
5170 00:27:29.023661 DramcWriteLeveling(PI) end<-----
5171 00:27:29.023761
5172 00:27:29.023824 ==
5173 00:27:29.027267 Dram Type= 6, Freq= 0, CH_0, rank 0
5174 00:27:29.033639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5175 00:27:29.033752 ==
5176 00:27:29.033841 [Gating] SW mode calibration
5177 00:27:29.043609 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5178 00:27:29.047047 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5179 00:27:29.054115 0 14 0 | B1->B0 | 2f2e 3434 | 1 1 | (0 0) (1 1)
5180 00:27:29.057049 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5181 00:27:29.060417 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5182 00:27:29.063868 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5183 00:27:29.070533 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5184 00:27:29.073891 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5185 00:27:29.077013 0 14 24 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
5186 00:27:29.083594 0 14 28 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
5187 00:27:29.087174 0 15 0 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
5188 00:27:29.090175 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5189 00:27:29.097032 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5190 00:27:29.100438 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5191 00:27:29.103968 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5192 00:27:29.110478 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5193 00:27:29.113484 0 15 24 | B1->B0 | 2323 3030 | 0 1 | (0 0) (0 0)
5194 00:27:29.117004 0 15 28 | B1->B0 | 2d2d 4545 | 0 0 | (0 0) (0 0)
5195 00:27:29.123557 1 0 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5196 00:27:29.126980 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5197 00:27:29.130359 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5198 00:27:29.137192 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5199 00:27:29.140624 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5200 00:27:29.143902 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5201 00:27:29.150376 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5202 00:27:29.153537 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5203 00:27:29.157318 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5204 00:27:29.163562 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5205 00:27:29.167095 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5206 00:27:29.170422 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5207 00:27:29.173673 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5208 00:27:29.180492 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5209 00:27:29.183590 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5210 00:27:29.187036 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5211 00:27:29.193562 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5212 00:27:29.197138 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5213 00:27:29.200140 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5214 00:27:29.206827 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5215 00:27:29.209928 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5216 00:27:29.213711 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5217 00:27:29.220146 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5218 00:27:29.223274 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5219 00:27:29.226819 Total UI for P1: 0, mck2ui 16
5220 00:27:29.229855 best dqsien dly found for B0: ( 1, 2, 24)
5221 00:27:29.233083 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5222 00:27:29.236821 Total UI for P1: 0, mck2ui 16
5223 00:27:29.239735 best dqsien dly found for B1: ( 1, 2, 30)
5224 00:27:29.243144 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5225 00:27:29.246764 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5226 00:27:29.246878
5227 00:27:29.253274 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5228 00:27:29.256439 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5229 00:27:29.259999 [Gating] SW calibration Done
5230 00:27:29.260079 ==
5231 00:27:29.263119 Dram Type= 6, Freq= 0, CH_0, rank 0
5232 00:27:29.266494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5233 00:27:29.266581 ==
5234 00:27:29.266643 RX Vref Scan: 0
5235 00:27:29.266700
5236 00:27:29.269711 RX Vref 0 -> 0, step: 1
5237 00:27:29.269783
5238 00:27:29.273040 RX Delay -80 -> 252, step: 8
5239 00:27:29.276432 iDelay=208, Bit 0, Center 111 (24 ~ 199) 176
5240 00:27:29.279904 iDelay=208, Bit 1, Center 111 (24 ~ 199) 176
5241 00:27:29.286318 iDelay=208, Bit 2, Center 107 (24 ~ 191) 168
5242 00:27:29.289840 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5243 00:27:29.292848 iDelay=208, Bit 4, Center 111 (24 ~ 199) 176
5244 00:27:29.296539 iDelay=208, Bit 5, Center 103 (16 ~ 191) 176
5245 00:27:29.300042 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5246 00:27:29.306283 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5247 00:27:29.309889 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5248 00:27:29.313386 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5249 00:27:29.316442 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5250 00:27:29.319894 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5251 00:27:29.323066 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5252 00:27:29.326578 iDelay=208, Bit 13, Center 95 (8 ~ 183) 176
5253 00:27:29.333306 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5254 00:27:29.336308 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5255 00:27:29.336388 ==
5256 00:27:29.339793 Dram Type= 6, Freq= 0, CH_0, rank 0
5257 00:27:29.343269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5258 00:27:29.343348 ==
5259 00:27:29.346286 DQS Delay:
5260 00:27:29.346370 DQS0 = 0, DQS1 = 0
5261 00:27:29.346433 DQM Delay:
5262 00:27:29.349783 DQM0 = 109, DQM1 = 92
5263 00:27:29.349862 DQ Delay:
5264 00:27:29.353331 DQ0 =111, DQ1 =111, DQ2 =107, DQ3 =103
5265 00:27:29.356455 DQ4 =111, DQ5 =103, DQ6 =115, DQ7 =115
5266 00:27:29.360251 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5267 00:27:29.363269 DQ12 =95, DQ13 =95, DQ14 =103, DQ15 =103
5268 00:27:29.363345
5269 00:27:29.363418
5270 00:27:29.366762 ==
5271 00:27:29.369867 Dram Type= 6, Freq= 0, CH_0, rank 0
5272 00:27:29.373178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5273 00:27:29.373253 ==
5274 00:27:29.373313
5275 00:27:29.373377
5276 00:27:29.376408 TX Vref Scan disable
5277 00:27:29.376486 == TX Byte 0 ==
5278 00:27:29.383064 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5279 00:27:29.386688 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5280 00:27:29.386767 == TX Byte 1 ==
5281 00:27:29.393594 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5282 00:27:29.396787 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5283 00:27:29.396877 ==
5284 00:27:29.399835 Dram Type= 6, Freq= 0, CH_0, rank 0
5285 00:27:29.403454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5286 00:27:29.403542 ==
5287 00:27:29.403608
5288 00:27:29.403669
5289 00:27:29.406473 TX Vref Scan disable
5290 00:27:29.410091 == TX Byte 0 ==
5291 00:27:29.413274 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5292 00:27:29.416791 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5293 00:27:29.419770 == TX Byte 1 ==
5294 00:27:29.423487 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5295 00:27:29.426529 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5296 00:27:29.426613
5297 00:27:29.429785 [DATLAT]
5298 00:27:29.429862 Freq=933, CH0 RK0
5299 00:27:29.429924
5300 00:27:29.433343 DATLAT Default: 0xd
5301 00:27:29.433423 0, 0xFFFF, sum = 0
5302 00:27:29.436371 1, 0xFFFF, sum = 0
5303 00:27:29.436450 2, 0xFFFF, sum = 0
5304 00:27:29.439940 3, 0xFFFF, sum = 0
5305 00:27:29.440029 4, 0xFFFF, sum = 0
5306 00:27:29.443086 5, 0xFFFF, sum = 0
5307 00:27:29.443171 6, 0xFFFF, sum = 0
5308 00:27:29.446475 7, 0xFFFF, sum = 0
5309 00:27:29.446546 8, 0xFFFF, sum = 0
5310 00:27:29.449664 9, 0xFFFF, sum = 0
5311 00:27:29.449744 10, 0x0, sum = 1
5312 00:27:29.453187 11, 0x0, sum = 2
5313 00:27:29.453271 12, 0x0, sum = 3
5314 00:27:29.456160 13, 0x0, sum = 4
5315 00:27:29.456240 best_step = 11
5316 00:27:29.456300
5317 00:27:29.456364 ==
5318 00:27:29.459755 Dram Type= 6, Freq= 0, CH_0, rank 0
5319 00:27:29.462622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5320 00:27:29.466033 ==
5321 00:27:29.466127 RX Vref Scan: 1
5322 00:27:29.466190
5323 00:27:29.469554 RX Vref 0 -> 0, step: 1
5324 00:27:29.469634
5325 00:27:29.473035 RX Delay -53 -> 252, step: 4
5326 00:27:29.473114
5327 00:27:29.476411 Set Vref, RX VrefLevel [Byte0]: 60
5328 00:27:29.479711 [Byte1]: 48
5329 00:27:29.479787
5330 00:27:29.482861 Final RX Vref Byte 0 = 60 to rank0
5331 00:27:29.486213 Final RX Vref Byte 1 = 48 to rank0
5332 00:27:29.489795 Final RX Vref Byte 0 = 60 to rank1
5333 00:27:29.492650 Final RX Vref Byte 1 = 48 to rank1==
5334 00:27:29.495918 Dram Type= 6, Freq= 0, CH_0, rank 0
5335 00:27:29.499405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5336 00:27:29.499484 ==
5337 00:27:29.499555 DQS Delay:
5338 00:27:29.502966 DQS0 = 0, DQS1 = 0
5339 00:27:29.503055 DQM Delay:
5340 00:27:29.506029 DQM0 = 108, DQM1 = 92
5341 00:27:29.506112 DQ Delay:
5342 00:27:29.509500 DQ0 =106, DQ1 =108, DQ2 =104, DQ3 =106
5343 00:27:29.512896 DQ4 =108, DQ5 =98, DQ6 =120, DQ7 =114
5344 00:27:29.515933 DQ8 =84, DQ9 =76, DQ10 =92, DQ11 =92
5345 00:27:29.519571 DQ12 =96, DQ13 =94, DQ14 =104, DQ15 =100
5346 00:27:29.519649
5347 00:27:29.519709
5348 00:27:29.529443 [DQSOSCAuto] RK0, (LSB)MR18= 0x231e, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 410 ps
5349 00:27:29.532966 CH0 RK0: MR19=505, MR18=231E
5350 00:27:29.535996 CH0_RK0: MR19=0x505, MR18=0x231E, DQSOSC=410, MR23=63, INC=64, DEC=42
5351 00:27:29.539536
5352 00:27:29.542667 ----->DramcWriteLeveling(PI) begin...
5353 00:27:29.542758 ==
5354 00:27:29.546252 Dram Type= 6, Freq= 0, CH_0, rank 1
5355 00:27:29.549358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5356 00:27:29.549431 ==
5357 00:27:29.552639 Write leveling (Byte 0): 32 => 32
5358 00:27:29.556507 Write leveling (Byte 1): 27 => 27
5359 00:27:29.559518 DramcWriteLeveling(PI) end<-----
5360 00:27:29.559598
5361 00:27:29.559659 ==
5362 00:27:29.562730 Dram Type= 6, Freq= 0, CH_0, rank 1
5363 00:27:29.566173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5364 00:27:29.566253 ==
5365 00:27:29.569590 [Gating] SW mode calibration
5366 00:27:29.576241 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5367 00:27:29.582637 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5368 00:27:29.585756 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5369 00:27:29.589265 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5370 00:27:29.595919 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5371 00:27:29.599300 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5372 00:27:29.602853 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5373 00:27:29.606315 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5374 00:27:29.612719 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
5375 00:27:29.616170 0 14 28 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
5376 00:27:29.619278 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5377 00:27:29.626108 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5378 00:27:29.629164 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5379 00:27:29.632826 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5380 00:27:29.639531 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5381 00:27:29.642536 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5382 00:27:29.646343 0 15 24 | B1->B0 | 2424 2d2c | 0 1 | (0 0) (0 0)
5383 00:27:29.652850 0 15 28 | B1->B0 | 3d3d 4545 | 0 0 | (0 0) (0 0)
5384 00:27:29.655924 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5385 00:27:29.659456 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5386 00:27:29.666120 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5387 00:27:29.669166 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5388 00:27:29.672627 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5389 00:27:29.679343 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5390 00:27:29.682516 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5391 00:27:29.685816 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5392 00:27:29.692544 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 00:27:29.695744 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 00:27:29.699420 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 00:27:29.705743 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 00:27:29.709432 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5397 00:27:29.712607 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5398 00:27:29.718939 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5399 00:27:29.722512 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5400 00:27:29.725886 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5401 00:27:29.729316 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5402 00:27:29.736054 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5403 00:27:29.739256 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5404 00:27:29.742195 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5405 00:27:29.748928 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5406 00:27:29.752607 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5407 00:27:29.755556 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5408 00:27:29.762506 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5409 00:27:29.765628 Total UI for P1: 0, mck2ui 16
5410 00:27:29.769132 best dqsien dly found for B0: ( 1, 2, 26)
5411 00:27:29.769228 Total UI for P1: 0, mck2ui 16
5412 00:27:29.775411 best dqsien dly found for B1: ( 1, 2, 28)
5413 00:27:29.778621 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5414 00:27:29.781901 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5415 00:27:29.781999
5416 00:27:29.785353 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5417 00:27:29.788633 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5418 00:27:29.792075 [Gating] SW calibration Done
5419 00:27:29.792166 ==
5420 00:27:29.795288 Dram Type= 6, Freq= 0, CH_0, rank 1
5421 00:27:29.798854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5422 00:27:29.798922 ==
5423 00:27:29.801899 RX Vref Scan: 0
5424 00:27:29.801970
5425 00:27:29.802028 RX Vref 0 -> 0, step: 1
5426 00:27:29.802082
5427 00:27:29.805423 RX Delay -80 -> 252, step: 8
5428 00:27:29.811899 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5429 00:27:29.815387 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5430 00:27:29.818709 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5431 00:27:29.822149 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5432 00:27:29.825155 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5433 00:27:29.828571 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5434 00:27:29.832101 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5435 00:27:29.838638 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5436 00:27:29.842034 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5437 00:27:29.845521 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5438 00:27:29.848926 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5439 00:27:29.851989 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5440 00:27:29.858475 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5441 00:27:29.862070 iDelay=208, Bit 13, Center 95 (8 ~ 183) 176
5442 00:27:29.865277 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5443 00:27:29.868821 iDelay=208, Bit 15, Center 95 (8 ~ 183) 176
5444 00:27:29.868893 ==
5445 00:27:29.871845 Dram Type= 6, Freq= 0, CH_0, rank 1
5446 00:27:29.875339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5447 00:27:29.875434 ==
5448 00:27:29.878737 DQS Delay:
5449 00:27:29.878834 DQS0 = 0, DQS1 = 0
5450 00:27:29.881929 DQM Delay:
5451 00:27:29.882014 DQM0 = 105, DQM1 = 90
5452 00:27:29.882075 DQ Delay:
5453 00:27:29.885510 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5454 00:27:29.888839 DQ4 =107, DQ5 =99, DQ6 =115, DQ7 =111
5455 00:27:29.891824 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5456 00:27:29.895622 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =95
5457 00:27:29.895698
5458 00:27:29.898554
5459 00:27:29.898629 ==
5460 00:27:29.901854 Dram Type= 6, Freq= 0, CH_0, rank 1
5461 00:27:29.905312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5462 00:27:29.905390 ==
5463 00:27:29.905461
5464 00:27:29.905519
5465 00:27:29.908413 TX Vref Scan disable
5466 00:27:29.908515 == TX Byte 0 ==
5467 00:27:29.915333 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5468 00:27:29.918568 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5469 00:27:29.918668 == TX Byte 1 ==
5470 00:27:29.925312 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5471 00:27:29.928442 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5472 00:27:29.928533 ==
5473 00:27:29.931915 Dram Type= 6, Freq= 0, CH_0, rank 1
5474 00:27:29.935277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5475 00:27:29.935346 ==
5476 00:27:29.935402
5477 00:27:29.935455
5478 00:27:29.938204 TX Vref Scan disable
5479 00:27:29.941752 == TX Byte 0 ==
5480 00:27:29.944759 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5481 00:27:29.948520 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5482 00:27:29.951397 == TX Byte 1 ==
5483 00:27:29.955111 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5484 00:27:29.958410 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5485 00:27:29.958524
5486 00:27:29.961909 [DATLAT]
5487 00:27:29.962010 Freq=933, CH0 RK1
5488 00:27:29.962105
5489 00:27:29.964901 DATLAT Default: 0xb
5490 00:27:29.965041 0, 0xFFFF, sum = 0
5491 00:27:29.968481 1, 0xFFFF, sum = 0
5492 00:27:29.968579 2, 0xFFFF, sum = 0
5493 00:27:29.971571 3, 0xFFFF, sum = 0
5494 00:27:29.971669 4, 0xFFFF, sum = 0
5495 00:27:29.974999 5, 0xFFFF, sum = 0
5496 00:27:29.975094 6, 0xFFFF, sum = 0
5497 00:27:29.978054 7, 0xFFFF, sum = 0
5498 00:27:29.978150 8, 0xFFFF, sum = 0
5499 00:27:29.981416 9, 0xFFFF, sum = 0
5500 00:27:29.981515 10, 0x0, sum = 1
5501 00:27:29.985009 11, 0x0, sum = 2
5502 00:27:29.985081 12, 0x0, sum = 3
5503 00:27:29.988601 13, 0x0, sum = 4
5504 00:27:29.988696 best_step = 11
5505 00:27:29.988803
5506 00:27:29.988866 ==
5507 00:27:29.991652 Dram Type= 6, Freq= 0, CH_0, rank 1
5508 00:27:29.998418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5509 00:27:29.998493 ==
5510 00:27:29.998553 RX Vref Scan: 0
5511 00:27:29.998619
5512 00:27:30.001749 RX Vref 0 -> 0, step: 1
5513 00:27:30.001813
5514 00:27:30.004693 RX Delay -53 -> 252, step: 4
5515 00:27:30.008099 iDelay=199, Bit 0, Center 102 (15 ~ 190) 176
5516 00:27:30.011536 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5517 00:27:30.017811 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5518 00:27:30.021127 iDelay=199, Bit 3, Center 98 (15 ~ 182) 168
5519 00:27:30.024649 iDelay=199, Bit 4, Center 104 (19 ~ 190) 172
5520 00:27:30.027976 iDelay=199, Bit 5, Center 96 (11 ~ 182) 172
5521 00:27:30.031209 iDelay=199, Bit 6, Center 112 (27 ~ 198) 172
5522 00:27:30.037731 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5523 00:27:30.041085 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5524 00:27:30.044549 iDelay=199, Bit 9, Center 80 (-1 ~ 162) 164
5525 00:27:30.047743 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5526 00:27:30.051188 iDelay=199, Bit 11, Center 92 (11 ~ 174) 164
5527 00:27:30.057785 iDelay=199, Bit 12, Center 96 (11 ~ 182) 172
5528 00:27:30.061488 iDelay=199, Bit 13, Center 96 (15 ~ 178) 164
5529 00:27:30.064519 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5530 00:27:30.068064 iDelay=199, Bit 15, Center 98 (15 ~ 182) 168
5531 00:27:30.068160 ==
5532 00:27:30.071254 Dram Type= 6, Freq= 0, CH_0, rank 1
5533 00:27:30.074337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5534 00:27:30.077958 ==
5535 00:27:30.078086 DQS Delay:
5536 00:27:30.078189 DQS0 = 0, DQS1 = 0
5537 00:27:30.081001 DQM Delay:
5538 00:27:30.081118 DQM0 = 104, DQM1 = 92
5539 00:27:30.084398 DQ Delay:
5540 00:27:30.088033 DQ0 =102, DQ1 =106, DQ2 =102, DQ3 =98
5541 00:27:30.090997 DQ4 =104, DQ5 =96, DQ6 =112, DQ7 =112
5542 00:27:30.094603 DQ8 =84, DQ9 =80, DQ10 =94, DQ11 =92
5543 00:27:30.097631 DQ12 =96, DQ13 =96, DQ14 =100, DQ15 =98
5544 00:27:30.097750
5545 00:27:30.097846
5546 00:27:30.104164 [DQSOSCAuto] RK1, (LSB)MR18= 0x2908, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 408 ps
5547 00:27:30.107881 CH0 RK1: MR19=505, MR18=2908
5548 00:27:30.114420 CH0_RK1: MR19=0x505, MR18=0x2908, DQSOSC=408, MR23=63, INC=65, DEC=43
5549 00:27:30.117819 [RxdqsGatingPostProcess] freq 933
5550 00:27:30.121020 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5551 00:27:30.124654 best DQS0 dly(2T, 0.5T) = (0, 10)
5552 00:27:30.127564 best DQS1 dly(2T, 0.5T) = (0, 10)
5553 00:27:30.131186 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5554 00:27:30.134253 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5555 00:27:30.137766 best DQS0 dly(2T, 0.5T) = (0, 10)
5556 00:27:30.140938 best DQS1 dly(2T, 0.5T) = (0, 10)
5557 00:27:30.143987 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5558 00:27:30.147293 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5559 00:27:30.151048 Pre-setting of DQS Precalculation
5560 00:27:30.154041 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5561 00:27:30.154137 ==
5562 00:27:30.157454 Dram Type= 6, Freq= 0, CH_1, rank 0
5563 00:27:30.164247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5564 00:27:30.164341 ==
5565 00:27:30.167217 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5566 00:27:30.174213 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5567 00:27:30.177239 [CA 0] Center 36 (6~67) winsize 62
5568 00:27:30.180970 [CA 1] Center 37 (6~68) winsize 63
5569 00:27:30.184049 [CA 2] Center 35 (5~66) winsize 62
5570 00:27:30.187134 [CA 3] Center 34 (4~65) winsize 62
5571 00:27:30.190502 [CA 4] Center 34 (4~65) winsize 62
5572 00:27:30.193648 [CA 5] Center 34 (4~64) winsize 61
5573 00:27:30.193743
5574 00:27:30.197155 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5575 00:27:30.197232
5576 00:27:30.200483 [CATrainingPosCal] consider 1 rank data
5577 00:27:30.203721 u2DelayCellTimex100 = 270/100 ps
5578 00:27:30.207389 CA0 delay=36 (6~67),Diff = 2 PI (12 cell)
5579 00:27:30.213999 CA1 delay=37 (6~68),Diff = 3 PI (18 cell)
5580 00:27:30.217379 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5581 00:27:30.220816 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5582 00:27:30.223848 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5583 00:27:30.226996 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5584 00:27:30.227073
5585 00:27:30.230604 CA PerBit enable=1, Macro0, CA PI delay=34
5586 00:27:30.230685
5587 00:27:30.234108 [CBTSetCACLKResult] CA Dly = 34
5588 00:27:30.234191 CS Dly: 5 (0~36)
5589 00:27:30.237088 ==
5590 00:27:30.237167 Dram Type= 6, Freq= 0, CH_1, rank 1
5591 00:27:30.244065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5592 00:27:30.244153 ==
5593 00:27:30.247153 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5594 00:27:30.253831 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5595 00:27:30.257420 [CA 0] Center 37 (7~68) winsize 62
5596 00:27:30.260723 [CA 1] Center 37 (7~68) winsize 62
5597 00:27:30.263788 [CA 2] Center 35 (5~66) winsize 62
5598 00:27:30.267351 [CA 3] Center 35 (5~65) winsize 61
5599 00:27:30.270610 [CA 4] Center 35 (5~65) winsize 61
5600 00:27:30.273657 [CA 5] Center 34 (4~65) winsize 62
5601 00:27:30.273738
5602 00:27:30.277215 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5603 00:27:30.277296
5604 00:27:30.280456 [CATrainingPosCal] consider 2 rank data
5605 00:27:30.283736 u2DelayCellTimex100 = 270/100 ps
5606 00:27:30.287315 CA0 delay=37 (7~67),Diff = 3 PI (18 cell)
5607 00:27:30.293926 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5608 00:27:30.297309 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5609 00:27:30.300471 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5610 00:27:30.303927 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5611 00:27:30.307154 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5612 00:27:30.307232
5613 00:27:30.310580 CA PerBit enable=1, Macro0, CA PI delay=34
5614 00:27:30.310679
5615 00:27:30.313692 [CBTSetCACLKResult] CA Dly = 34
5616 00:27:30.313783 CS Dly: 6 (0~38)
5617 00:27:30.313857
5618 00:27:30.317289 ----->DramcWriteLeveling(PI) begin...
5619 00:27:30.320546 ==
5620 00:27:30.323950 Dram Type= 6, Freq= 0, CH_1, rank 0
5621 00:27:30.327406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5622 00:27:30.327486 ==
5623 00:27:30.330510 Write leveling (Byte 0): 28 => 28
5624 00:27:30.333574 Write leveling (Byte 1): 28 => 28
5625 00:27:30.337205 DramcWriteLeveling(PI) end<-----
5626 00:27:30.337281
5627 00:27:30.337341 ==
5628 00:27:30.340481 Dram Type= 6, Freq= 0, CH_1, rank 0
5629 00:27:30.343654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5630 00:27:30.343730 ==
5631 00:27:30.347244 [Gating] SW mode calibration
5632 00:27:30.353768 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5633 00:27:30.360266 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5634 00:27:30.363767 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5635 00:27:30.367181 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5636 00:27:30.373407 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5637 00:27:30.377025 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5638 00:27:30.380019 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5639 00:27:30.383251 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5640 00:27:30.390619 0 14 24 | B1->B0 | 3333 2f2f | 0 0 | (0 1) (0 1)
5641 00:27:30.393394 0 14 28 | B1->B0 | 2525 2424 | 0 0 | (0 0) (1 0)
5642 00:27:30.396920 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5643 00:27:30.403556 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5644 00:27:30.406997 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5645 00:27:30.410060 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5646 00:27:30.416856 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5647 00:27:30.420425 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5648 00:27:30.423416 0 15 24 | B1->B0 | 2626 2c2c | 0 0 | (0 0) (0 0)
5649 00:27:30.430395 0 15 28 | B1->B0 | 3c3c 4242 | 0 0 | (0 0) (0 0)
5650 00:27:30.433389 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5651 00:27:30.436685 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5652 00:27:30.443396 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5653 00:27:30.446828 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5654 00:27:30.450436 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5655 00:27:30.456910 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5656 00:27:30.459971 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5657 00:27:30.463331 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5658 00:27:30.470134 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5659 00:27:30.473803 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5660 00:27:30.476928 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5661 00:27:30.483579 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5662 00:27:30.486695 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5663 00:27:30.490135 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5664 00:27:30.493125 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5665 00:27:30.500021 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5666 00:27:30.503402 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5667 00:27:30.506565 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5668 00:27:30.513491 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5669 00:27:30.517024 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5670 00:27:30.520137 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5671 00:27:30.526689 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5672 00:27:30.530303 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5673 00:27:30.533392 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5674 00:27:30.537161 Total UI for P1: 0, mck2ui 16
5675 00:27:30.540220 best dqsien dly found for B0: ( 1, 2, 22)
5676 00:27:30.546768 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5677 00:27:30.547123 Total UI for P1: 0, mck2ui 16
5678 00:27:30.553781 best dqsien dly found for B1: ( 1, 2, 26)
5679 00:27:30.556799 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5680 00:27:30.560298 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5681 00:27:30.560651
5682 00:27:30.563733 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5683 00:27:30.566931 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5684 00:27:30.570176 [Gating] SW calibration Done
5685 00:27:30.570531 ==
5686 00:27:30.573688 Dram Type= 6, Freq= 0, CH_1, rank 0
5687 00:27:30.576619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5688 00:27:30.577011 ==
5689 00:27:30.580068 RX Vref Scan: 0
5690 00:27:30.580424
5691 00:27:30.580701 RX Vref 0 -> 0, step: 1
5692 00:27:30.581004
5693 00:27:30.583485 RX Delay -80 -> 252, step: 8
5694 00:27:30.589879 iDelay=208, Bit 0, Center 107 (24 ~ 191) 168
5695 00:27:30.593363 iDelay=208, Bit 1, Center 99 (16 ~ 183) 168
5696 00:27:30.596120 iDelay=208, Bit 2, Center 99 (16 ~ 183) 168
5697 00:27:30.599783 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5698 00:27:30.602800 iDelay=208, Bit 4, Center 103 (16 ~ 191) 176
5699 00:27:30.606201 iDelay=208, Bit 5, Center 115 (32 ~ 199) 168
5700 00:27:30.612929 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5701 00:27:30.615971 iDelay=208, Bit 7, Center 103 (16 ~ 191) 176
5702 00:27:30.619339 iDelay=208, Bit 8, Center 91 (0 ~ 183) 184
5703 00:27:30.622721 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5704 00:27:30.626272 iDelay=208, Bit 10, Center 103 (16 ~ 191) 176
5705 00:27:30.629253 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5706 00:27:30.636368 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5707 00:27:30.639363 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5708 00:27:30.643048 iDelay=208, Bit 14, Center 107 (16 ~ 199) 184
5709 00:27:30.646190 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5710 00:27:30.646266 ==
5711 00:27:30.649751 Dram Type= 6, Freq= 0, CH_1, rank 0
5712 00:27:30.656112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5713 00:27:30.656190 ==
5714 00:27:30.656251 DQS Delay:
5715 00:27:30.659246 DQS0 = 0, DQS1 = 0
5716 00:27:30.659323 DQM Delay:
5717 00:27:30.662689 DQM0 = 105, DQM1 = 99
5718 00:27:30.662767 DQ Delay:
5719 00:27:30.666486 DQ0 =107, DQ1 =99, DQ2 =99, DQ3 =103
5720 00:27:30.669226 DQ4 =103, DQ5 =115, DQ6 =115, DQ7 =103
5721 00:27:30.672517 DQ8 =91, DQ9 =87, DQ10 =103, DQ11 =91
5722 00:27:30.676185 DQ12 =107, DQ13 =107, DQ14 =107, DQ15 =103
5723 00:27:30.676281
5724 00:27:30.676355
5725 00:27:30.676423 ==
5726 00:27:30.679202 Dram Type= 6, Freq= 0, CH_1, rank 0
5727 00:27:30.682629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5728 00:27:30.682737 ==
5729 00:27:30.685947
5730 00:27:30.686059
5731 00:27:30.686147 TX Vref Scan disable
5732 00:27:30.689550 == TX Byte 0 ==
5733 00:27:30.692643 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5734 00:27:30.696095 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5735 00:27:30.699103 == TX Byte 1 ==
5736 00:27:30.702765 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5737 00:27:30.705899 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5738 00:27:30.705976 ==
5739 00:27:30.709398 Dram Type= 6, Freq= 0, CH_1, rank 0
5740 00:27:30.715823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5741 00:27:30.715900 ==
5742 00:27:30.715960
5743 00:27:30.716015
5744 00:27:30.716067 TX Vref Scan disable
5745 00:27:30.720427 == TX Byte 0 ==
5746 00:27:30.723426 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5747 00:27:30.727012 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5748 00:27:30.730037 == TX Byte 1 ==
5749 00:27:30.733651 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5750 00:27:30.740163 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5751 00:27:30.740261
5752 00:27:30.740335 [DATLAT]
5753 00:27:30.740405 Freq=933, CH1 RK0
5754 00:27:30.740472
5755 00:27:30.743212 DATLAT Default: 0xd
5756 00:27:30.743308 0, 0xFFFF, sum = 0
5757 00:27:30.746982 1, 0xFFFF, sum = 0
5758 00:27:30.747087 2, 0xFFFF, sum = 0
5759 00:27:30.749943 3, 0xFFFF, sum = 0
5760 00:27:30.753126 4, 0xFFFF, sum = 0
5761 00:27:30.753243 5, 0xFFFF, sum = 0
5762 00:27:30.756591 6, 0xFFFF, sum = 0
5763 00:27:30.756733 7, 0xFFFF, sum = 0
5764 00:27:30.760247 8, 0xFFFF, sum = 0
5765 00:27:30.760390 9, 0xFFFF, sum = 0
5766 00:27:30.763213 10, 0x0, sum = 1
5767 00:27:30.763358 11, 0x0, sum = 2
5768 00:27:30.763472 12, 0x0, sum = 3
5769 00:27:30.767016 13, 0x0, sum = 4
5770 00:27:30.767180 best_step = 11
5771 00:27:30.767306
5772 00:27:30.770115 ==
5773 00:27:30.770300 Dram Type= 6, Freq= 0, CH_1, rank 0
5774 00:27:30.777049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5775 00:27:30.777273 ==
5776 00:27:30.777449 RX Vref Scan: 1
5777 00:27:30.777611
5778 00:27:30.780253 RX Vref 0 -> 0, step: 1
5779 00:27:30.780527
5780 00:27:30.783602 RX Delay -45 -> 252, step: 4
5781 00:27:30.783875
5782 00:27:30.787414 Set Vref, RX VrefLevel [Byte0]: 51
5783 00:27:30.790315 [Byte1]: 51
5784 00:27:30.790668
5785 00:27:30.793977 Final RX Vref Byte 0 = 51 to rank0
5786 00:27:30.797281 Final RX Vref Byte 1 = 51 to rank0
5787 00:27:30.800582 Final RX Vref Byte 0 = 51 to rank1
5788 00:27:30.804099 Final RX Vref Byte 1 = 51 to rank1==
5789 00:27:30.807245 Dram Type= 6, Freq= 0, CH_1, rank 0
5790 00:27:30.810309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5791 00:27:30.810674 ==
5792 00:27:30.813799 DQS Delay:
5793 00:27:30.814158 DQS0 = 0, DQS1 = 0
5794 00:27:30.814435 DQM Delay:
5795 00:27:30.817191 DQM0 = 107, DQM1 = 100
5796 00:27:30.817547 DQ Delay:
5797 00:27:30.820175 DQ0 =110, DQ1 =102, DQ2 =100, DQ3 =106
5798 00:27:30.823757 DQ4 =108, DQ5 =114, DQ6 =116, DQ7 =104
5799 00:27:30.826920 DQ8 =90, DQ9 =90, DQ10 =104, DQ11 =94
5800 00:27:30.833387 DQ12 =110, DQ13 =104, DQ14 =106, DQ15 =106
5801 00:27:30.833743
5802 00:27:30.834015
5803 00:27:30.840154 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a33, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 413 ps
5804 00:27:30.843345 CH1 RK0: MR19=505, MR18=1A33
5805 00:27:30.850087 CH1_RK0: MR19=0x505, MR18=0x1A33, DQSOSC=405, MR23=63, INC=66, DEC=44
5806 00:27:30.850447
5807 00:27:30.853835 ----->DramcWriteLeveling(PI) begin...
5808 00:27:30.854233 ==
5809 00:27:30.856786 Dram Type= 6, Freq= 0, CH_1, rank 1
5810 00:27:30.860303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5811 00:27:30.860693 ==
5812 00:27:30.863353 Write leveling (Byte 0): 28 => 28
5813 00:27:30.867172 Write leveling (Byte 1): 29 => 29
5814 00:27:30.870201 DramcWriteLeveling(PI) end<-----
5815 00:27:30.870592
5816 00:27:30.870894 ==
5817 00:27:30.873454 Dram Type= 6, Freq= 0, CH_1, rank 1
5818 00:27:30.876781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5819 00:27:30.877174 ==
5820 00:27:30.880419 [Gating] SW mode calibration
5821 00:27:30.886971 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5822 00:27:30.893630 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5823 00:27:30.896619 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5824 00:27:30.903144 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5825 00:27:30.906669 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5826 00:27:30.910190 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5827 00:27:30.916418 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5828 00:27:30.920245 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5829 00:27:30.923197 0 14 24 | B1->B0 | 3030 3333 | 0 1 | (0 0) (1 0)
5830 00:27:30.926772 0 14 28 | B1->B0 | 2626 2f2f | 1 1 | (0 0) (0 0)
5831 00:27:30.933520 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5832 00:27:30.936811 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5833 00:27:30.940310 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5834 00:27:30.946470 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5835 00:27:30.949684 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5836 00:27:30.953221 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5837 00:27:30.959843 0 15 24 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
5838 00:27:30.963328 0 15 28 | B1->B0 | 3d3d 3535 | 0 0 | (0 0) (1 1)
5839 00:27:30.966245 1 0 0 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
5840 00:27:30.973359 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5841 00:27:30.976888 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5842 00:27:30.979965 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5843 00:27:30.986784 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5844 00:27:30.990070 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5845 00:27:30.993268 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5846 00:27:30.999759 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5847 00:27:31.002968 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5848 00:27:31.006583 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5849 00:27:31.012800 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5850 00:27:31.015837 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5851 00:27:31.019098 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5852 00:27:31.025892 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5853 00:27:31.029522 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5854 00:27:31.032600 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5855 00:27:31.039331 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5856 00:27:31.042760 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5857 00:27:31.046017 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5858 00:27:31.052554 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5859 00:27:31.055640 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5860 00:27:31.059325 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5861 00:27:31.062487 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5862 00:27:31.069134 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5863 00:27:31.072373 Total UI for P1: 0, mck2ui 16
5864 00:27:31.075952 best dqsien dly found for B0: ( 1, 2, 24)
5865 00:27:31.079616 Total UI for P1: 0, mck2ui 16
5866 00:27:31.082584 best dqsien dly found for B1: ( 1, 2, 26)
5867 00:27:31.085715 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5868 00:27:31.089273 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5869 00:27:31.089389
5870 00:27:31.092262 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5871 00:27:31.095976 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5872 00:27:31.098966 [Gating] SW calibration Done
5873 00:27:31.099043 ==
5874 00:27:31.102388 Dram Type= 6, Freq= 0, CH_1, rank 1
5875 00:27:31.105608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5876 00:27:31.105686 ==
5877 00:27:31.108982 RX Vref Scan: 0
5878 00:27:31.109060
5879 00:27:31.109135 RX Vref 0 -> 0, step: 1
5880 00:27:31.112318
5881 00:27:31.112410 RX Delay -80 -> 252, step: 8
5882 00:27:31.119209 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
5883 00:27:31.122846 iDelay=200, Bit 1, Center 99 (16 ~ 183) 168
5884 00:27:31.126011 iDelay=200, Bit 2, Center 95 (16 ~ 175) 160
5885 00:27:31.129172 iDelay=200, Bit 3, Center 103 (16 ~ 191) 176
5886 00:27:31.132177 iDelay=200, Bit 4, Center 103 (16 ~ 191) 176
5887 00:27:31.135785 iDelay=200, Bit 5, Center 115 (32 ~ 199) 168
5888 00:27:31.142390 iDelay=200, Bit 6, Center 107 (24 ~ 191) 168
5889 00:27:31.145540 iDelay=200, Bit 7, Center 103 (16 ~ 191) 176
5890 00:27:31.148956 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5891 00:27:31.152631 iDelay=200, Bit 9, Center 87 (0 ~ 175) 176
5892 00:27:31.155757 iDelay=200, Bit 10, Center 99 (16 ~ 183) 168
5893 00:27:31.162229 iDelay=200, Bit 11, Center 91 (0 ~ 183) 184
5894 00:27:31.165662 iDelay=200, Bit 12, Center 107 (16 ~ 199) 184
5895 00:27:31.168767 iDelay=200, Bit 13, Center 103 (16 ~ 191) 176
5896 00:27:31.172553 iDelay=200, Bit 14, Center 103 (16 ~ 191) 176
5897 00:27:31.175567 iDelay=200, Bit 15, Center 107 (16 ~ 199) 184
5898 00:27:31.179127 ==
5899 00:27:31.179253 Dram Type= 6, Freq= 0, CH_1, rank 1
5900 00:27:31.185649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5901 00:27:31.185792 ==
5902 00:27:31.185904 DQS Delay:
5903 00:27:31.188629 DQS0 = 0, DQS1 = 0
5904 00:27:31.188802 DQM Delay:
5905 00:27:31.192010 DQM0 = 104, DQM1 = 97
5906 00:27:31.192171 DQ Delay:
5907 00:27:31.195245 DQ0 =111, DQ1 =99, DQ2 =95, DQ3 =103
5908 00:27:31.198773 DQ4 =103, DQ5 =115, DQ6 =107, DQ7 =103
5909 00:27:31.202377 DQ8 =83, DQ9 =87, DQ10 =99, DQ11 =91
5910 00:27:31.205671 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5911 00:27:31.205951
5912 00:27:31.206166
5913 00:27:31.206366 ==
5914 00:27:31.209203 Dram Type= 6, Freq= 0, CH_1, rank 1
5915 00:27:31.212691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5916 00:27:31.215819 ==
5917 00:27:31.216208
5918 00:27:31.216506
5919 00:27:31.216826 TX Vref Scan disable
5920 00:27:31.218934 == TX Byte 0 ==
5921 00:27:31.222491 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5922 00:27:31.225772 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5923 00:27:31.229335 == TX Byte 1 ==
5924 00:27:31.232636 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5925 00:27:31.236128 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5926 00:27:31.236623 ==
5927 00:27:31.239592 Dram Type= 6, Freq= 0, CH_1, rank 1
5928 00:27:31.245841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5929 00:27:31.246244 ==
5930 00:27:31.246548
5931 00:27:31.246835
5932 00:27:31.247105 TX Vref Scan disable
5933 00:27:31.250274 == TX Byte 0 ==
5934 00:27:31.253831 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5935 00:27:31.259750 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5936 00:27:31.260148 == TX Byte 1 ==
5937 00:27:31.263467 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5938 00:27:31.270128 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5939 00:27:31.270526
5940 00:27:31.270827 [DATLAT]
5941 00:27:31.271110 Freq=933, CH1 RK1
5942 00:27:31.271382
5943 00:27:31.273281 DATLAT Default: 0xb
5944 00:27:31.273674 0, 0xFFFF, sum = 0
5945 00:27:31.276895 1, 0xFFFF, sum = 0
5946 00:27:31.277286 2, 0xFFFF, sum = 0
5947 00:27:31.279911 3, 0xFFFF, sum = 0
5948 00:27:31.283520 4, 0xFFFF, sum = 0
5949 00:27:31.283915 5, 0xFFFF, sum = 0
5950 00:27:31.286969 6, 0xFFFF, sum = 0
5951 00:27:31.287449 7, 0xFFFF, sum = 0
5952 00:27:31.289809 8, 0xFFFF, sum = 0
5953 00:27:31.290203 9, 0xFFFF, sum = 0
5954 00:27:31.293287 10, 0x0, sum = 1
5955 00:27:31.293738 11, 0x0, sum = 2
5956 00:27:31.294051 12, 0x0, sum = 3
5957 00:27:31.296624 13, 0x0, sum = 4
5958 00:27:31.297050 best_step = 11
5959 00:27:31.297358
5960 00:27:31.300222 ==
5961 00:27:31.300611 Dram Type= 6, Freq= 0, CH_1, rank 1
5962 00:27:31.306483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5963 00:27:31.306950 ==
5964 00:27:31.307257 RX Vref Scan: 0
5965 00:27:31.307543
5966 00:27:31.310059 RX Vref 0 -> 0, step: 1
5967 00:27:31.310444
5968 00:27:31.313007 RX Delay -53 -> 252, step: 4
5969 00:27:31.316478 iDelay=199, Bit 0, Center 112 (39 ~ 186) 148
5970 00:27:31.322872 iDelay=199, Bit 1, Center 102 (27 ~ 178) 152
5971 00:27:31.326415 iDelay=199, Bit 2, Center 96 (23 ~ 170) 148
5972 00:27:31.329658 iDelay=199, Bit 3, Center 106 (27 ~ 186) 160
5973 00:27:31.333205 iDelay=199, Bit 4, Center 108 (31 ~ 186) 156
5974 00:27:31.336163 iDelay=199, Bit 5, Center 118 (39 ~ 198) 160
5975 00:27:31.343256 iDelay=199, Bit 6, Center 116 (39 ~ 194) 156
5976 00:27:31.346631 iDelay=199, Bit 7, Center 106 (31 ~ 182) 152
5977 00:27:31.349835 iDelay=199, Bit 8, Center 90 (11 ~ 170) 160
5978 00:27:31.353500 iDelay=199, Bit 9, Center 90 (11 ~ 170) 160
5979 00:27:31.356577 iDelay=199, Bit 10, Center 100 (19 ~ 182) 164
5980 00:27:31.359878 iDelay=199, Bit 11, Center 96 (15 ~ 178) 164
5981 00:27:31.366420 iDelay=199, Bit 12, Center 110 (31 ~ 190) 160
5982 00:27:31.369878 iDelay=199, Bit 13, Center 106 (27 ~ 186) 160
5983 00:27:31.373301 iDelay=199, Bit 14, Center 112 (31 ~ 194) 164
5984 00:27:31.376036 iDelay=199, Bit 15, Center 112 (31 ~ 194) 164
5985 00:27:31.376525 ==
5986 00:27:31.379742 Dram Type= 6, Freq= 0, CH_1, rank 1
5987 00:27:31.386218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5988 00:27:31.386795 ==
5989 00:27:31.387289 DQS Delay:
5990 00:27:31.389397 DQS0 = 0, DQS1 = 0
5991 00:27:31.389852 DQM Delay:
5992 00:27:31.393100 DQM0 = 108, DQM1 = 102
5993 00:27:31.393491 DQ Delay:
5994 00:27:31.396557 DQ0 =112, DQ1 =102, DQ2 =96, DQ3 =106
5995 00:27:31.399821 DQ4 =108, DQ5 =118, DQ6 =116, DQ7 =106
5996 00:27:31.403196 DQ8 =90, DQ9 =90, DQ10 =100, DQ11 =96
5997 00:27:31.406621 DQ12 =110, DQ13 =106, DQ14 =112, DQ15 =112
5998 00:27:31.407098
5999 00:27:31.407405
6000 00:27:31.416109 [DQSOSCAuto] RK1, (LSB)MR18= 0x22ff, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 411 ps
6001 00:27:31.416512 CH1 RK1: MR19=504, MR18=22FF
6002 00:27:31.422887 CH1_RK1: MR19=0x504, MR18=0x22FF, DQSOSC=411, MR23=63, INC=64, DEC=42
6003 00:27:31.426153 [RxdqsGatingPostProcess] freq 933
6004 00:27:31.432967 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6005 00:27:31.436514 best DQS0 dly(2T, 0.5T) = (0, 10)
6006 00:27:31.439157 best DQS1 dly(2T, 0.5T) = (0, 10)
6007 00:27:31.443231 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6008 00:27:31.445896 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6009 00:27:31.449205 best DQS0 dly(2T, 0.5T) = (0, 10)
6010 00:27:31.449597 best DQS1 dly(2T, 0.5T) = (0, 10)
6011 00:27:31.452549 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6012 00:27:31.456144 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6013 00:27:31.459276 Pre-setting of DQS Precalculation
6014 00:27:31.466217 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6015 00:27:31.472207 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6016 00:27:31.478853 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6017 00:27:31.479311
6018 00:27:31.479617
6019 00:27:31.482355 [Calibration Summary] 1866 Mbps
6020 00:27:31.482873 CH 0, Rank 0
6021 00:27:31.485650 SW Impedance : PASS
6022 00:27:31.489059 DUTY Scan : NO K
6023 00:27:31.489448 ZQ Calibration : PASS
6024 00:27:31.492183 Jitter Meter : NO K
6025 00:27:31.495904 CBT Training : PASS
6026 00:27:31.496292 Write leveling : PASS
6027 00:27:31.498880 RX DQS gating : PASS
6028 00:27:31.502529 RX DQ/DQS(RDDQC) : PASS
6029 00:27:31.502973 TX DQ/DQS : PASS
6030 00:27:31.505885 RX DATLAT : PASS
6031 00:27:31.509114 RX DQ/DQS(Engine): PASS
6032 00:27:31.509507 TX OE : NO K
6033 00:27:31.512197 All Pass.
6034 00:27:31.512583
6035 00:27:31.512920 CH 0, Rank 1
6036 00:27:31.515703 SW Impedance : PASS
6037 00:27:31.516098 DUTY Scan : NO K
6038 00:27:31.519183 ZQ Calibration : PASS
6039 00:27:31.522252 Jitter Meter : NO K
6040 00:27:31.522643 CBT Training : PASS
6041 00:27:31.526032 Write leveling : PASS
6042 00:27:31.526512 RX DQS gating : PASS
6043 00:27:31.529330 RX DQ/DQS(RDDQC) : PASS
6044 00:27:31.532573 TX DQ/DQS : PASS
6045 00:27:31.533076 RX DATLAT : PASS
6046 00:27:31.535981 RX DQ/DQS(Engine): PASS
6047 00:27:31.539204 TX OE : NO K
6048 00:27:31.539596 All Pass.
6049 00:27:31.539902
6050 00:27:31.540182 CH 1, Rank 0
6051 00:27:31.542711 SW Impedance : PASS
6052 00:27:31.545841 DUTY Scan : NO K
6053 00:27:31.546311 ZQ Calibration : PASS
6054 00:27:31.548902 Jitter Meter : NO K
6055 00:27:31.552175 CBT Training : PASS
6056 00:27:31.552568 Write leveling : PASS
6057 00:27:31.555586 RX DQS gating : PASS
6058 00:27:31.559034 RX DQ/DQS(RDDQC) : PASS
6059 00:27:31.559449 TX DQ/DQS : PASS
6060 00:27:31.562290 RX DATLAT : PASS
6061 00:27:31.565499 RX DQ/DQS(Engine): PASS
6062 00:27:31.565891 TX OE : NO K
6063 00:27:31.566201 All Pass.
6064 00:27:31.568992
6065 00:27:31.569382 CH 1, Rank 1
6066 00:27:31.572486 SW Impedance : PASS
6067 00:27:31.572911 DUTY Scan : NO K
6068 00:27:31.575606 ZQ Calibration : PASS
6069 00:27:31.576004 Jitter Meter : NO K
6070 00:27:31.578905 CBT Training : PASS
6071 00:27:31.582437 Write leveling : PASS
6072 00:27:31.582829 RX DQS gating : PASS
6073 00:27:31.585406 RX DQ/DQS(RDDQC) : PASS
6074 00:27:31.589334 TX DQ/DQS : PASS
6075 00:27:31.589817 RX DATLAT : PASS
6076 00:27:31.592470 RX DQ/DQS(Engine): PASS
6077 00:27:31.595578 TX OE : NO K
6078 00:27:31.596069 All Pass.
6079 00:27:31.596387
6080 00:27:31.598879 DramC Write-DBI off
6081 00:27:31.599308 PER_BANK_REFRESH: Hybrid Mode
6082 00:27:31.602689 TX_TRACKING: ON
6083 00:27:31.609037 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6084 00:27:31.615211 [FAST_K] Save calibration result to emmc
6085 00:27:31.618782 dramc_set_vcore_voltage set vcore to 650000
6086 00:27:31.619176 Read voltage for 400, 6
6087 00:27:31.621993 Vio18 = 0
6088 00:27:31.622377 Vcore = 650000
6089 00:27:31.622680 Vdram = 0
6090 00:27:31.625608 Vddq = 0
6091 00:27:31.625996 Vmddr = 0
6092 00:27:31.628671 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6093 00:27:31.635538 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6094 00:27:31.638780 MEM_TYPE=3, freq_sel=20
6095 00:27:31.642185 sv_algorithm_assistance_LP4_800
6096 00:27:31.645313 ============ PULL DRAM RESETB DOWN ============
6097 00:27:31.648981 ========== PULL DRAM RESETB DOWN end =========
6098 00:27:31.652150 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6099 00:27:31.655553 ===================================
6100 00:27:31.658631 LPDDR4 DRAM CONFIGURATION
6101 00:27:31.662178 ===================================
6102 00:27:31.665401 EX_ROW_EN[0] = 0x0
6103 00:27:31.665792 EX_ROW_EN[1] = 0x0
6104 00:27:31.668831 LP4Y_EN = 0x0
6105 00:27:31.669226 WORK_FSP = 0x0
6106 00:27:31.672571 WL = 0x2
6107 00:27:31.673022 RL = 0x2
6108 00:27:31.675325 BL = 0x2
6109 00:27:31.675713 RPST = 0x0
6110 00:27:31.678671 RD_PRE = 0x0
6111 00:27:31.679061 WR_PRE = 0x1
6112 00:27:31.682007 WR_PST = 0x0
6113 00:27:31.682421 DBI_WR = 0x0
6114 00:27:31.685375 DBI_RD = 0x0
6115 00:27:31.688673 OTF = 0x1
6116 00:27:31.692218 ===================================
6117 00:27:31.692617 ===================================
6118 00:27:31.695453 ANA top config
6119 00:27:31.698651 ===================================
6120 00:27:31.702182 DLL_ASYNC_EN = 0
6121 00:27:31.702577 ALL_SLAVE_EN = 1
6122 00:27:31.705164 NEW_RANK_MODE = 1
6123 00:27:31.708862 DLL_IDLE_MODE = 1
6124 00:27:31.711974 LP45_APHY_COMB_EN = 1
6125 00:27:31.715328 TX_ODT_DIS = 1
6126 00:27:31.715721 NEW_8X_MODE = 1
6127 00:27:31.718615 ===================================
6128 00:27:31.722292 ===================================
6129 00:27:31.725293 data_rate = 800
6130 00:27:31.728805 CKR = 1
6131 00:27:31.731799 DQ_P2S_RATIO = 4
6132 00:27:31.735399 ===================================
6133 00:27:31.738464 CA_P2S_RATIO = 4
6134 00:27:31.741951 DQ_CA_OPEN = 0
6135 00:27:31.742428 DQ_SEMI_OPEN = 1
6136 00:27:31.745084 CA_SEMI_OPEN = 1
6137 00:27:31.748662 CA_FULL_RATE = 0
6138 00:27:31.751767 DQ_CKDIV4_EN = 0
6139 00:27:31.755229 CA_CKDIV4_EN = 1
6140 00:27:31.755629 CA_PREDIV_EN = 0
6141 00:27:31.758815 PH8_DLY = 0
6142 00:27:31.761894 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6143 00:27:31.765404 DQ_AAMCK_DIV = 0
6144 00:27:31.768602 CA_AAMCK_DIV = 0
6145 00:27:31.771956 CA_ADMCK_DIV = 4
6146 00:27:31.772394 DQ_TRACK_CA_EN = 0
6147 00:27:31.775192 CA_PICK = 800
6148 00:27:31.778767 CA_MCKIO = 400
6149 00:27:31.782098 MCKIO_SEMI = 400
6150 00:27:31.785195 PLL_FREQ = 3016
6151 00:27:31.788789 DQ_UI_PI_RATIO = 32
6152 00:27:31.792278 CA_UI_PI_RATIO = 32
6153 00:27:31.795731 ===================================
6154 00:27:31.798785 ===================================
6155 00:27:31.799192 memory_type:LPDDR4
6156 00:27:31.802132 GP_NUM : 10
6157 00:27:31.805219 SRAM_EN : 1
6158 00:27:31.805612 MD32_EN : 0
6159 00:27:31.808616 ===================================
6160 00:27:31.812095 [ANA_INIT] >>>>>>>>>>>>>>
6161 00:27:31.815375 <<<<<< [CONFIGURE PHASE]: ANA_TX
6162 00:27:31.818598 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6163 00:27:31.821775 ===================================
6164 00:27:31.825637 data_rate = 800,PCW = 0X7400
6165 00:27:31.828503 ===================================
6166 00:27:31.832059 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6167 00:27:31.835144 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6168 00:27:31.848412 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6169 00:27:31.851474 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6170 00:27:31.854529 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6171 00:27:31.858286 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6172 00:27:31.861490 [ANA_INIT] flow start
6173 00:27:31.861569 [ANA_INIT] PLL >>>>>>>>
6174 00:27:31.865028 [ANA_INIT] PLL <<<<<<<<
6175 00:27:31.868766 [ANA_INIT] MIDPI >>>>>>>>
6176 00:27:31.871962 [ANA_INIT] MIDPI <<<<<<<<
6177 00:27:31.872116 [ANA_INIT] DLL >>>>>>>>
6178 00:27:31.874761 [ANA_INIT] flow end
6179 00:27:31.878336 ============ LP4 DIFF to SE enter ============
6180 00:27:31.881592 ============ LP4 DIFF to SE exit ============
6181 00:27:31.885014 [ANA_INIT] <<<<<<<<<<<<<
6182 00:27:31.888414 [Flow] Enable top DCM control >>>>>
6183 00:27:31.891634 [Flow] Enable top DCM control <<<<<
6184 00:27:31.895417 Enable DLL master slave shuffle
6185 00:27:31.898283 ==============================================================
6186 00:27:31.902050 Gating Mode config
6187 00:27:31.908532 ==============================================================
6188 00:27:31.908744 Config description:
6189 00:27:31.918599 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6190 00:27:31.925118 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6191 00:27:31.932077 SELPH_MODE 0: By rank 1: By Phase
6192 00:27:31.935092 ==============================================================
6193 00:27:31.938547 GAT_TRACK_EN = 0
6194 00:27:31.941684 RX_GATING_MODE = 2
6195 00:27:31.945145 RX_GATING_TRACK_MODE = 2
6196 00:27:31.948571 SELPH_MODE = 1
6197 00:27:31.951660 PICG_EARLY_EN = 1
6198 00:27:31.955299 VALID_LAT_VALUE = 1
6199 00:27:31.958210 ==============================================================
6200 00:27:31.961980 Enter into Gating configuration >>>>
6201 00:27:31.965441 Exit from Gating configuration <<<<
6202 00:27:31.968503 Enter into DVFS_PRE_config >>>>>
6203 00:27:31.981819 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6204 00:27:31.985005 Exit from DVFS_PRE_config <<<<<
6205 00:27:31.985404 Enter into PICG configuration >>>>
6206 00:27:31.988499 Exit from PICG configuration <<<<
6207 00:27:31.991453 [RX_INPUT] configuration >>>>>
6208 00:27:31.995229 [RX_INPUT] configuration <<<<<
6209 00:27:32.001775 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6210 00:27:32.004801 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6211 00:27:32.011817 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6212 00:27:32.018283 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6213 00:27:32.025010 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6214 00:27:32.031975 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6215 00:27:32.035039 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6216 00:27:32.038307 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6217 00:27:32.041527 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6218 00:27:32.048143 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6219 00:27:32.051506 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6220 00:27:32.054987 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6221 00:27:32.058290 ===================================
6222 00:27:32.061410 LPDDR4 DRAM CONFIGURATION
6223 00:27:32.064643 ===================================
6224 00:27:32.065093 EX_ROW_EN[0] = 0x0
6225 00:27:32.068056 EX_ROW_EN[1] = 0x0
6226 00:27:32.071598 LP4Y_EN = 0x0
6227 00:27:32.071992 WORK_FSP = 0x0
6228 00:27:32.074553 WL = 0x2
6229 00:27:32.074949 RL = 0x2
6230 00:27:32.078159 BL = 0x2
6231 00:27:32.078551 RPST = 0x0
6232 00:27:32.081168 RD_PRE = 0x0
6233 00:27:32.081565 WR_PRE = 0x1
6234 00:27:32.084837 WR_PST = 0x0
6235 00:27:32.085232 DBI_WR = 0x0
6236 00:27:32.087758 DBI_RD = 0x0
6237 00:27:32.088037 OTF = 0x1
6238 00:27:32.091214 ===================================
6239 00:27:32.094336 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6240 00:27:32.100967 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6241 00:27:32.104216 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6242 00:27:32.107874 ===================================
6243 00:27:32.111112 LPDDR4 DRAM CONFIGURATION
6244 00:27:32.114630 ===================================
6245 00:27:32.114738 EX_ROW_EN[0] = 0x10
6246 00:27:32.117511 EX_ROW_EN[1] = 0x0
6247 00:27:32.121098 LP4Y_EN = 0x0
6248 00:27:32.121184 WORK_FSP = 0x0
6249 00:27:32.124316 WL = 0x2
6250 00:27:32.124402 RL = 0x2
6251 00:27:32.127440 BL = 0x2
6252 00:27:32.127520 RPST = 0x0
6253 00:27:32.130980 RD_PRE = 0x0
6254 00:27:32.131056 WR_PRE = 0x1
6255 00:27:32.134605 WR_PST = 0x0
6256 00:27:32.134682 DBI_WR = 0x0
6257 00:27:32.137933 DBI_RD = 0x0
6258 00:27:32.138076 OTF = 0x1
6259 00:27:32.140975 ===================================
6260 00:27:32.148113 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6261 00:27:32.151625 nWR fixed to 30
6262 00:27:32.155064 [ModeRegInit_LP4] CH0 RK0
6263 00:27:32.155141 [ModeRegInit_LP4] CH0 RK1
6264 00:27:32.158393 [ModeRegInit_LP4] CH1 RK0
6265 00:27:32.161626 [ModeRegInit_LP4] CH1 RK1
6266 00:27:32.161743 match AC timing 19
6267 00:27:32.168222 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6268 00:27:32.171285 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6269 00:27:32.174682 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6270 00:27:32.181223 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6271 00:27:32.184536 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6272 00:27:32.184628 ==
6273 00:27:32.188066 Dram Type= 6, Freq= 0, CH_0, rank 0
6274 00:27:32.191520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6275 00:27:32.191637 ==
6276 00:27:32.198130 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6277 00:27:32.204977 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6278 00:27:32.208321 [CA 0] Center 36 (8~64) winsize 57
6279 00:27:32.211614 [CA 1] Center 36 (8~64) winsize 57
6280 00:27:32.215105 [CA 2] Center 36 (8~64) winsize 57
6281 00:27:32.215521 [CA 3] Center 36 (8~64) winsize 57
6282 00:27:32.218389 [CA 4] Center 36 (8~64) winsize 57
6283 00:27:32.221504 [CA 5] Center 36 (8~64) winsize 57
6284 00:27:32.222000
6285 00:27:32.225054 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6286 00:27:32.228082
6287 00:27:32.231752 [CATrainingPosCal] consider 1 rank data
6288 00:27:32.234850 u2DelayCellTimex100 = 270/100 ps
6289 00:27:32.238365 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6290 00:27:32.241407 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6291 00:27:32.245160 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6292 00:27:32.248246 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6293 00:27:32.251812 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6294 00:27:32.254854 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6295 00:27:32.255382
6296 00:27:32.258289 CA PerBit enable=1, Macro0, CA PI delay=36
6297 00:27:32.258702
6298 00:27:32.261896 [CBTSetCACLKResult] CA Dly = 36
6299 00:27:32.264802 CS Dly: 1 (0~32)
6300 00:27:32.265212 ==
6301 00:27:32.268037 Dram Type= 6, Freq= 0, CH_0, rank 1
6302 00:27:32.271556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6303 00:27:32.271964 ==
6304 00:27:32.278104 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6305 00:27:32.281701 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6306 00:27:32.284974 [CA 0] Center 36 (8~64) winsize 57
6307 00:27:32.288385 [CA 1] Center 36 (8~64) winsize 57
6308 00:27:32.291767 [CA 2] Center 36 (8~64) winsize 57
6309 00:27:32.295118 [CA 3] Center 36 (8~64) winsize 57
6310 00:27:32.298566 [CA 4] Center 36 (8~64) winsize 57
6311 00:27:32.301652 [CA 5] Center 36 (8~64) winsize 57
6312 00:27:32.302062
6313 00:27:32.305053 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6314 00:27:32.305438
6315 00:27:32.308479 [CATrainingPosCal] consider 2 rank data
6316 00:27:32.311907 u2DelayCellTimex100 = 270/100 ps
6317 00:27:32.314896 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6318 00:27:32.318379 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6319 00:27:32.321362 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6320 00:27:32.325225 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6321 00:27:32.331569 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6322 00:27:32.334957 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6323 00:27:32.335179
6324 00:27:32.337841 CA PerBit enable=1, Macro0, CA PI delay=36
6325 00:27:32.338018
6326 00:27:32.341368 [CBTSetCACLKResult] CA Dly = 36
6327 00:27:32.341547 CS Dly: 1 (0~32)
6328 00:27:32.341720
6329 00:27:32.344515 ----->DramcWriteLeveling(PI) begin...
6330 00:27:32.344694 ==
6331 00:27:32.348218 Dram Type= 6, Freq= 0, CH_0, rank 0
6332 00:27:32.354618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6333 00:27:32.354795 ==
6334 00:27:32.358339 Write leveling (Byte 0): 40 => 8
6335 00:27:32.358517 Write leveling (Byte 1): 32 => 0
6336 00:27:32.361385 DramcWriteLeveling(PI) end<-----
6337 00:27:32.361632
6338 00:27:32.361769 ==
6339 00:27:32.364379 Dram Type= 6, Freq= 0, CH_0, rank 0
6340 00:27:32.371409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6341 00:27:32.371492 ==
6342 00:27:32.374436 [Gating] SW mode calibration
6343 00:27:32.381272 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6344 00:27:32.384399 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6345 00:27:32.390934 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6346 00:27:32.394268 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6347 00:27:32.397690 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6348 00:27:32.404303 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6349 00:27:32.407648 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6350 00:27:32.410887 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6351 00:27:32.417464 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6352 00:27:32.420809 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6353 00:27:32.423930 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6354 00:27:32.427642 Total UI for P1: 0, mck2ui 16
6355 00:27:32.430724 best dqsien dly found for B0: ( 0, 14, 24)
6356 00:27:32.434247 Total UI for P1: 0, mck2ui 16
6357 00:27:32.437708 best dqsien dly found for B1: ( 0, 14, 24)
6358 00:27:32.440756 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6359 00:27:32.443916 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6360 00:27:32.444047
6361 00:27:32.451007 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6362 00:27:32.454242 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6363 00:27:32.454410 [Gating] SW calibration Done
6364 00:27:32.457526 ==
6365 00:27:32.457722 Dram Type= 6, Freq= 0, CH_0, rank 0
6366 00:27:32.464023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6367 00:27:32.464258 ==
6368 00:27:32.464452 RX Vref Scan: 0
6369 00:27:32.464616
6370 00:27:32.467590 RX Vref 0 -> 0, step: 1
6371 00:27:32.467884
6372 00:27:32.470693 RX Delay -410 -> 252, step: 16
6373 00:27:32.474201 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6374 00:27:32.477497 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6375 00:27:32.483993 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6376 00:27:32.487615 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6377 00:27:32.490811 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6378 00:27:32.493821 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6379 00:27:32.500482 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6380 00:27:32.504144 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6381 00:27:32.506969 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6382 00:27:32.510671 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6383 00:27:32.517048 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6384 00:27:32.520578 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6385 00:27:32.523980 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6386 00:27:32.526884 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6387 00:27:32.533792 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6388 00:27:32.537318 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6389 00:27:32.537395 ==
6390 00:27:32.540228 Dram Type= 6, Freq= 0, CH_0, rank 0
6391 00:27:32.544101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6392 00:27:32.544178 ==
6393 00:27:32.547005 DQS Delay:
6394 00:27:32.547083 DQS0 = 27, DQS1 = 43
6395 00:27:32.550062 DQM Delay:
6396 00:27:32.550138 DQM0 = 11, DQM1 = 11
6397 00:27:32.553664 DQ Delay:
6398 00:27:32.553741 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6399 00:27:32.557007 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6400 00:27:32.560063 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6401 00:27:32.563634 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6402 00:27:32.563711
6403 00:27:32.563770
6404 00:27:32.563824 ==
6405 00:27:32.567010 Dram Type= 6, Freq= 0, CH_0, rank 0
6406 00:27:32.573687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6407 00:27:32.573765 ==
6408 00:27:32.573825
6409 00:27:32.573880
6410 00:27:32.573932 TX Vref Scan disable
6411 00:27:32.576850 == TX Byte 0 ==
6412 00:27:32.580437 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6413 00:27:32.583746 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6414 00:27:32.586899 == TX Byte 1 ==
6415 00:27:32.590309 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6416 00:27:32.593560 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6417 00:27:32.596949 ==
6418 00:27:32.597026 Dram Type= 6, Freq= 0, CH_0, rank 0
6419 00:27:32.603618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6420 00:27:32.603718 ==
6421 00:27:32.603780
6422 00:27:32.603835
6423 00:27:32.603888 TX Vref Scan disable
6424 00:27:32.606681 == TX Byte 0 ==
6425 00:27:32.610223 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6426 00:27:32.613935 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6427 00:27:32.616942 == TX Byte 1 ==
6428 00:27:32.620025 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6429 00:27:32.623534 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6430 00:27:32.626744
6431 00:27:32.626843 [DATLAT]
6432 00:27:32.626936 Freq=400, CH0 RK0
6433 00:27:32.627022
6434 00:27:32.630369 DATLAT Default: 0xf
6435 00:27:32.630469 0, 0xFFFF, sum = 0
6436 00:27:32.633518 1, 0xFFFF, sum = 0
6437 00:27:32.633595 2, 0xFFFF, sum = 0
6438 00:27:32.636926 3, 0xFFFF, sum = 0
6439 00:27:32.637004 4, 0xFFFF, sum = 0
6440 00:27:32.640349 5, 0xFFFF, sum = 0
6441 00:27:32.643585 6, 0xFFFF, sum = 0
6442 00:27:32.643692 7, 0xFFFF, sum = 0
6443 00:27:32.646835 8, 0xFFFF, sum = 0
6444 00:27:32.646913 9, 0xFFFF, sum = 0
6445 00:27:32.650214 10, 0xFFFF, sum = 0
6446 00:27:32.650331 11, 0xFFFF, sum = 0
6447 00:27:32.653792 12, 0xFFFF, sum = 0
6448 00:27:32.653874 13, 0x0, sum = 1
6449 00:27:32.656922 14, 0x0, sum = 2
6450 00:27:32.657002 15, 0x0, sum = 3
6451 00:27:32.660073 16, 0x0, sum = 4
6452 00:27:32.660154 best_step = 14
6453 00:27:32.660232
6454 00:27:32.660305 ==
6455 00:27:32.663107 Dram Type= 6, Freq= 0, CH_0, rank 0
6456 00:27:32.666418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6457 00:27:32.666522 ==
6458 00:27:32.670035 RX Vref Scan: 1
6459 00:27:32.670130
6460 00:27:32.673609 RX Vref 0 -> 0, step: 1
6461 00:27:32.673707
6462 00:27:32.673802 RX Delay -327 -> 252, step: 8
6463 00:27:32.676546
6464 00:27:32.676666 Set Vref, RX VrefLevel [Byte0]: 60
6465 00:27:32.679764 [Byte1]: 48
6466 00:27:32.685368
6467 00:27:32.685449 Final RX Vref Byte 0 = 60 to rank0
6468 00:27:32.688448 Final RX Vref Byte 1 = 48 to rank0
6469 00:27:32.692134 Final RX Vref Byte 0 = 60 to rank1
6470 00:27:32.695303 Final RX Vref Byte 1 = 48 to rank1==
6471 00:27:32.699112 Dram Type= 6, Freq= 0, CH_0, rank 0
6472 00:27:32.705160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6473 00:27:32.705239 ==
6474 00:27:32.705300 DQS Delay:
6475 00:27:32.708687 DQS0 = 28, DQS1 = 48
6476 00:27:32.708799 DQM Delay:
6477 00:27:32.708856 DQM0 = 11, DQM1 = 15
6478 00:27:32.711846 DQ Delay:
6479 00:27:32.715225 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6480 00:27:32.715291 DQ4 =12, DQ5 =0, DQ6 =24, DQ7 =20
6481 00:27:32.718474 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6482 00:27:32.722041 DQ12 =20, DQ13 =16, DQ14 =28, DQ15 =24
6483 00:27:32.722118
6484 00:27:32.725069
6485 00:27:32.731777 [DQSOSCAuto] RK0, (LSB)MR18= 0xb1a9, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 387 ps
6486 00:27:32.735070 CH0 RK0: MR19=C0C, MR18=B1A9
6487 00:27:32.741880 CH0_RK0: MR19=0xC0C, MR18=0xB1A9, DQSOSC=387, MR23=63, INC=394, DEC=262
6488 00:27:32.741958 ==
6489 00:27:32.744883 Dram Type= 6, Freq= 0, CH_0, rank 1
6490 00:27:32.748464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6491 00:27:32.748570 ==
6492 00:27:32.751584 [Gating] SW mode calibration
6493 00:27:32.758341 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6494 00:27:32.765087 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6495 00:27:32.768521 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6496 00:27:32.771640 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6497 00:27:32.774934 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6498 00:27:32.781674 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6499 00:27:32.785356 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6500 00:27:32.788342 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6501 00:27:32.795028 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6502 00:27:32.798804 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6503 00:27:32.801992 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6504 00:27:32.805194 Total UI for P1: 0, mck2ui 16
6505 00:27:32.808346 best dqsien dly found for B0: ( 0, 14, 24)
6506 00:27:32.811879 Total UI for P1: 0, mck2ui 16
6507 00:27:32.815004 best dqsien dly found for B1: ( 0, 14, 24)
6508 00:27:32.818327 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6509 00:27:32.821878 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6510 00:27:32.824867
6511 00:27:32.828555 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6512 00:27:32.831465 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6513 00:27:32.835026 [Gating] SW calibration Done
6514 00:27:32.835103 ==
6515 00:27:32.838368 Dram Type= 6, Freq= 0, CH_0, rank 1
6516 00:27:32.841213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6517 00:27:32.841290 ==
6518 00:27:32.841350 RX Vref Scan: 0
6519 00:27:32.844679
6520 00:27:32.844761 RX Vref 0 -> 0, step: 1
6521 00:27:32.844821
6522 00:27:32.848278 RX Delay -410 -> 252, step: 16
6523 00:27:32.851620 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6524 00:27:32.858313 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6525 00:27:32.861299 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6526 00:27:32.864992 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6527 00:27:32.867878 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6528 00:27:32.874909 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6529 00:27:32.878191 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6530 00:27:32.881555 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6531 00:27:32.884905 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6532 00:27:32.891608 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6533 00:27:32.894929 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6534 00:27:32.898221 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6535 00:27:32.901583 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6536 00:27:32.908295 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6537 00:27:32.911399 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6538 00:27:32.914714 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6539 00:27:32.914792 ==
6540 00:27:32.918190 Dram Type= 6, Freq= 0, CH_0, rank 1
6541 00:27:32.921739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6542 00:27:32.924717 ==
6543 00:27:32.924795 DQS Delay:
6544 00:27:32.924857 DQS0 = 27, DQS1 = 43
6545 00:27:32.928321 DQM Delay:
6546 00:27:32.928397 DQM0 = 9, DQM1 = 14
6547 00:27:32.931406 DQ Delay:
6548 00:27:32.931488 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6549 00:27:32.934859 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6550 00:27:32.938318 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6551 00:27:32.941529 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =16
6552 00:27:32.941618
6553 00:27:32.941741
6554 00:27:32.941852 ==
6555 00:27:32.944574 Dram Type= 6, Freq= 0, CH_0, rank 1
6556 00:27:32.951349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6557 00:27:32.951421 ==
6558 00:27:32.951479
6559 00:27:32.951536
6560 00:27:32.951608 TX Vref Scan disable
6561 00:27:32.955124 == TX Byte 0 ==
6562 00:27:32.958002 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6563 00:27:32.961171 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6564 00:27:32.964780 == TX Byte 1 ==
6565 00:27:32.967979 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6566 00:27:32.971111 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6567 00:27:32.971189 ==
6568 00:27:32.974561 Dram Type= 6, Freq= 0, CH_0, rank 1
6569 00:27:32.981099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6570 00:27:32.981189 ==
6571 00:27:32.981259
6572 00:27:32.981324
6573 00:27:32.981385 TX Vref Scan disable
6574 00:27:32.984654 == TX Byte 0 ==
6575 00:27:32.987977 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6576 00:27:32.991185 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6577 00:27:32.994767 == TX Byte 1 ==
6578 00:27:32.997746 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6579 00:27:33.001379 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6580 00:27:33.001506
6581 00:27:33.004520 [DATLAT]
6582 00:27:33.004621 Freq=400, CH0 RK1
6583 00:27:33.004733
6584 00:27:33.008464 DATLAT Default: 0xe
6585 00:27:33.008567 0, 0xFFFF, sum = 0
6586 00:27:33.011513 1, 0xFFFF, sum = 0
6587 00:27:33.011592 2, 0xFFFF, sum = 0
6588 00:27:33.014516 3, 0xFFFF, sum = 0
6589 00:27:33.014619 4, 0xFFFF, sum = 0
6590 00:27:33.018019 5, 0xFFFF, sum = 0
6591 00:27:33.018104 6, 0xFFFF, sum = 0
6592 00:27:33.021687 7, 0xFFFF, sum = 0
6593 00:27:33.021778 8, 0xFFFF, sum = 0
6594 00:27:33.025023 9, 0xFFFF, sum = 0
6595 00:27:33.025101 10, 0xFFFF, sum = 0
6596 00:27:33.027953 11, 0xFFFF, sum = 0
6597 00:27:33.031547 12, 0xFFFF, sum = 0
6598 00:27:33.031626 13, 0x0, sum = 1
6599 00:27:33.031687 14, 0x0, sum = 2
6600 00:27:33.034789 15, 0x0, sum = 3
6601 00:27:33.034892 16, 0x0, sum = 4
6602 00:27:33.038341 best_step = 14
6603 00:27:33.038419
6604 00:27:33.038479 ==
6605 00:27:33.041482 Dram Type= 6, Freq= 0, CH_0, rank 1
6606 00:27:33.045034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6607 00:27:33.045112 ==
6608 00:27:33.048024 RX Vref Scan: 0
6609 00:27:33.048100
6610 00:27:33.048160 RX Vref 0 -> 0, step: 1
6611 00:27:33.048216
6612 00:27:33.051573 RX Delay -327 -> 252, step: 8
6613 00:27:33.059717 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6614 00:27:33.062813 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6615 00:27:33.065832 iDelay=217, Bit 2, Center -24 (-247 ~ 200) 448
6616 00:27:33.069255 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6617 00:27:33.075956 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6618 00:27:33.079303 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6619 00:27:33.082744 iDelay=217, Bit 6, Center -12 (-239 ~ 216) 456
6620 00:27:33.086030 iDelay=217, Bit 7, Center -12 (-239 ~ 216) 456
6621 00:27:33.092656 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6622 00:27:33.095788 iDelay=217, Bit 9, Center -40 (-263 ~ 184) 448
6623 00:27:33.099105 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6624 00:27:33.105680 iDelay=217, Bit 11, Center -36 (-263 ~ 192) 456
6625 00:27:33.109165 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6626 00:27:33.112561 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6627 00:27:33.115585 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6628 00:27:33.122269 iDelay=217, Bit 15, Center -20 (-239 ~ 200) 440
6629 00:27:33.122347 ==
6630 00:27:33.125693 Dram Type= 6, Freq= 0, CH_0, rank 1
6631 00:27:33.128821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6632 00:27:33.128929 ==
6633 00:27:33.129018 DQS Delay:
6634 00:27:33.132166 DQS0 = 28, DQS1 = 40
6635 00:27:33.132261 DQM Delay:
6636 00:27:33.135821 DQM0 = 9, DQM1 = 11
6637 00:27:33.135898 DQ Delay:
6638 00:27:33.138924 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =4
6639 00:27:33.142312 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6640 00:27:33.145636 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6641 00:27:33.149162 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =20
6642 00:27:33.149263
6643 00:27:33.149358
6644 00:27:33.155989 [DQSOSCAuto] RK1, (LSB)MR18= 0xb96c, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 386 ps
6645 00:27:33.158890 CH0 RK1: MR19=C0C, MR18=B96C
6646 00:27:33.165749 CH0_RK1: MR19=0xC0C, MR18=0xB96C, DQSOSC=386, MR23=63, INC=396, DEC=264
6647 00:27:33.169612 [RxdqsGatingPostProcess] freq 400
6648 00:27:33.175553 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6649 00:27:33.175663 best DQS0 dly(2T, 0.5T) = (0, 10)
6650 00:27:33.178997 best DQS1 dly(2T, 0.5T) = (0, 10)
6651 00:27:33.182374 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6652 00:27:33.185975 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6653 00:27:33.188888 best DQS0 dly(2T, 0.5T) = (0, 10)
6654 00:27:33.192472 best DQS1 dly(2T, 0.5T) = (0, 10)
6655 00:27:33.195594 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6656 00:27:33.199215 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6657 00:27:33.202329 Pre-setting of DQS Precalculation
6658 00:27:33.205698 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6659 00:27:33.209295 ==
6660 00:27:33.212252 Dram Type= 6, Freq= 0, CH_1, rank 0
6661 00:27:33.215716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6662 00:27:33.215834 ==
6663 00:27:33.219126 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6664 00:27:33.225790 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6665 00:27:33.229053 [CA 0] Center 36 (8~64) winsize 57
6666 00:27:33.232411 [CA 1] Center 36 (8~64) winsize 57
6667 00:27:33.235767 [CA 2] Center 36 (8~64) winsize 57
6668 00:27:33.238829 [CA 3] Center 36 (8~64) winsize 57
6669 00:27:33.242456 [CA 4] Center 36 (8~64) winsize 57
6670 00:27:33.245861 [CA 5] Center 36 (8~64) winsize 57
6671 00:27:33.245982
6672 00:27:33.249056 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6673 00:27:33.249136
6674 00:27:33.252211 [CATrainingPosCal] consider 1 rank data
6675 00:27:33.255814 u2DelayCellTimex100 = 270/100 ps
6676 00:27:33.258905 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6677 00:27:33.262362 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6678 00:27:33.265595 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6679 00:27:33.269058 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6680 00:27:33.272108 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6681 00:27:33.278965 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6682 00:27:33.279047
6683 00:27:33.282084 CA PerBit enable=1, Macro0, CA PI delay=36
6684 00:27:33.282183
6685 00:27:33.285851 [CBTSetCACLKResult] CA Dly = 36
6686 00:27:33.285946 CS Dly: 1 (0~32)
6687 00:27:33.286026 ==
6688 00:27:33.289063 Dram Type= 6, Freq= 0, CH_1, rank 1
6689 00:27:33.292242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6690 00:27:33.295295 ==
6691 00:27:33.298801 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6692 00:27:33.305467 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6693 00:27:33.308945 [CA 0] Center 36 (8~64) winsize 57
6694 00:27:33.312094 [CA 1] Center 36 (8~64) winsize 57
6695 00:27:33.315456 [CA 2] Center 36 (8~64) winsize 57
6696 00:27:33.318660 [CA 3] Center 36 (8~64) winsize 57
6697 00:27:33.321796 [CA 4] Center 36 (8~64) winsize 57
6698 00:27:33.325171 [CA 5] Center 36 (8~64) winsize 57
6699 00:27:33.325276
6700 00:27:33.328429 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6701 00:27:33.328526
6702 00:27:33.332147 [CATrainingPosCal] consider 2 rank data
6703 00:27:33.335207 u2DelayCellTimex100 = 270/100 ps
6704 00:27:33.338369 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6705 00:27:33.342239 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6706 00:27:33.345413 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6707 00:27:33.348640 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6708 00:27:33.351931 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6709 00:27:33.355115 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6710 00:27:33.355213
6711 00:27:33.358571 CA PerBit enable=1, Macro0, CA PI delay=36
6712 00:27:33.358667
6713 00:27:33.361828 [CBTSetCACLKResult] CA Dly = 36
6714 00:27:33.365049 CS Dly: 1 (0~32)
6715 00:27:33.365149
6716 00:27:33.368907 ----->DramcWriteLeveling(PI) begin...
6717 00:27:33.369017 ==
6718 00:27:33.372057 Dram Type= 6, Freq= 0, CH_1, rank 0
6719 00:27:33.375212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6720 00:27:33.375310 ==
6721 00:27:33.378333 Write leveling (Byte 0): 40 => 8
6722 00:27:33.381934 Write leveling (Byte 1): 32 => 0
6723 00:27:33.385114 DramcWriteLeveling(PI) end<-----
6724 00:27:33.385203
6725 00:27:33.385294 ==
6726 00:27:33.388680 Dram Type= 6, Freq= 0, CH_1, rank 0
6727 00:27:33.391776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6728 00:27:33.391855 ==
6729 00:27:33.394898 [Gating] SW mode calibration
6730 00:27:33.402010 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6731 00:27:33.408588 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6732 00:27:33.412037 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6733 00:27:33.418252 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6734 00:27:33.421700 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6735 00:27:33.425011 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6736 00:27:33.431517 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6737 00:27:33.434836 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6738 00:27:33.438424 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6739 00:27:33.441476 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6740 00:27:33.448261 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6741 00:27:33.451782 Total UI for P1: 0, mck2ui 16
6742 00:27:33.454724 best dqsien dly found for B0: ( 0, 14, 24)
6743 00:27:33.458472 Total UI for P1: 0, mck2ui 16
6744 00:27:33.461328 best dqsien dly found for B1: ( 0, 14, 24)
6745 00:27:33.464697 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6746 00:27:33.467920 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6747 00:27:33.467998
6748 00:27:33.471344 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6749 00:27:33.474839 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6750 00:27:33.478215 [Gating] SW calibration Done
6751 00:27:33.478293 ==
6752 00:27:33.481482 Dram Type= 6, Freq= 0, CH_1, rank 0
6753 00:27:33.484546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6754 00:27:33.484624 ==
6755 00:27:33.488119 RX Vref Scan: 0
6756 00:27:33.488197
6757 00:27:33.491299 RX Vref 0 -> 0, step: 1
6758 00:27:33.491377
6759 00:27:33.491437 RX Delay -410 -> 252, step: 16
6760 00:27:33.497991 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6761 00:27:33.501426 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6762 00:27:33.505147 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6763 00:27:33.508313 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6764 00:27:33.514569 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6765 00:27:33.518239 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6766 00:27:33.521394 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6767 00:27:33.524975 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6768 00:27:33.531297 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6769 00:27:33.534632 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6770 00:27:33.538204 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6771 00:27:33.541629 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6772 00:27:33.548126 iDelay=230, Bit 12, Center -19 (-266 ~ 229) 496
6773 00:27:33.551189 iDelay=230, Bit 13, Center -11 (-250 ~ 229) 480
6774 00:27:33.554732 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6775 00:27:33.561434 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6776 00:27:33.561510 ==
6777 00:27:33.564657 Dram Type= 6, Freq= 0, CH_1, rank 0
6778 00:27:33.567681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6779 00:27:33.567780 ==
6780 00:27:33.567869 DQS Delay:
6781 00:27:33.571382 DQS0 = 27, DQS1 = 43
6782 00:27:33.571474 DQM Delay:
6783 00:27:33.574800 DQM0 = 4, DQM1 = 17
6784 00:27:33.574889 DQ Delay:
6785 00:27:33.577745 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6786 00:27:33.581292 DQ4 =0, DQ5 =8, DQ6 =16, DQ7 =0
6787 00:27:33.584795 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6788 00:27:33.587937 DQ12 =24, DQ13 =32, DQ14 =16, DQ15 =24
6789 00:27:33.588033
6790 00:27:33.588116
6791 00:27:33.588231 ==
6792 00:27:33.591533 Dram Type= 6, Freq= 0, CH_1, rank 0
6793 00:27:33.594497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6794 00:27:33.594573 ==
6795 00:27:33.594632
6796 00:27:33.594686
6797 00:27:33.598173 TX Vref Scan disable
6798 00:27:33.598249 == TX Byte 0 ==
6799 00:27:33.604761 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6800 00:27:33.608001 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6801 00:27:33.608077 == TX Byte 1 ==
6802 00:27:33.614599 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6803 00:27:33.617962 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6804 00:27:33.618039 ==
6805 00:27:33.621136 Dram Type= 6, Freq= 0, CH_1, rank 0
6806 00:27:33.624874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6807 00:27:33.624953 ==
6808 00:27:33.625015
6809 00:27:33.625070
6810 00:27:33.627887 TX Vref Scan disable
6811 00:27:33.627964 == TX Byte 0 ==
6812 00:27:33.634882 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6813 00:27:33.637819 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6814 00:27:33.637897 == TX Byte 1 ==
6815 00:27:33.644686 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6816 00:27:33.647962 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6817 00:27:33.648045
6818 00:27:33.648109 [DATLAT]
6819 00:27:33.652133 Freq=400, CH1 RK0
6820 00:27:33.652285
6821 00:27:33.652361 DATLAT Default: 0xf
6822 00:27:33.654991 0, 0xFFFF, sum = 0
6823 00:27:33.655146 1, 0xFFFF, sum = 0
6824 00:27:33.658106 2, 0xFFFF, sum = 0
6825 00:27:33.658239 3, 0xFFFF, sum = 0
6826 00:27:33.661061 4, 0xFFFF, sum = 0
6827 00:27:33.661159 5, 0xFFFF, sum = 0
6828 00:27:33.664607 6, 0xFFFF, sum = 0
6829 00:27:33.664749 7, 0xFFFF, sum = 0
6830 00:27:33.668373 8, 0xFFFF, sum = 0
6831 00:27:33.671263 9, 0xFFFF, sum = 0
6832 00:27:33.671379 10, 0xFFFF, sum = 0
6833 00:27:33.674380 11, 0xFFFF, sum = 0
6834 00:27:33.674507 12, 0xFFFF, sum = 0
6835 00:27:33.678389 13, 0x0, sum = 1
6836 00:27:33.678785 14, 0x0, sum = 2
6837 00:27:33.681364 15, 0x0, sum = 3
6838 00:27:33.681757 16, 0x0, sum = 4
6839 00:27:33.682065 best_step = 14
6840 00:27:33.682343
6841 00:27:33.684664 ==
6842 00:27:33.688238 Dram Type= 6, Freq= 0, CH_1, rank 0
6843 00:27:33.691223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6844 00:27:33.691612 ==
6845 00:27:33.691917 RX Vref Scan: 1
6846 00:27:33.692197
6847 00:27:33.694772 RX Vref 0 -> 0, step: 1
6848 00:27:33.695159
6849 00:27:33.698208 RX Delay -327 -> 252, step: 8
6850 00:27:33.698655
6851 00:27:33.701209 Set Vref, RX VrefLevel [Byte0]: 51
6852 00:27:33.704835 [Byte1]: 51
6853 00:27:33.708388
6854 00:27:33.708831 Final RX Vref Byte 0 = 51 to rank0
6855 00:27:33.712095 Final RX Vref Byte 1 = 51 to rank0
6856 00:27:33.715524 Final RX Vref Byte 0 = 51 to rank1
6857 00:27:33.718766 Final RX Vref Byte 1 = 51 to rank1==
6858 00:27:33.721212 Dram Type= 6, Freq= 0, CH_1, rank 0
6859 00:27:33.727964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6860 00:27:33.728377 ==
6861 00:27:33.728851 DQS Delay:
6862 00:27:33.731442 DQS0 = 32, DQS1 = 40
6863 00:27:33.731849 DQM Delay:
6864 00:27:33.732274 DQM0 = 11, DQM1 = 12
6865 00:27:33.734956 DQ Delay:
6866 00:27:33.738367 DQ0 =12, DQ1 =12, DQ2 =0, DQ3 =8
6867 00:27:33.738773 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
6868 00:27:33.741310 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6869 00:27:33.744504 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =20
6870 00:27:33.745074
6871 00:27:33.745573
6872 00:27:33.754818 [DQSOSCAuto] RK0, (LSB)MR18= 0x9ad5, (MSB)MR19= 0xc0c, tDQSOscB0 = 383 ps tDQSOscB1 = 390 ps
6873 00:27:33.758169 CH1 RK0: MR19=C0C, MR18=9AD5
6874 00:27:33.765135 CH1_RK0: MR19=0xC0C, MR18=0x9AD5, DQSOSC=383, MR23=63, INC=402, DEC=268
6875 00:27:33.765542 ==
6876 00:27:33.768114 Dram Type= 6, Freq= 0, CH_1, rank 1
6877 00:27:33.771102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6878 00:27:33.771492 ==
6879 00:27:33.775025 [Gating] SW mode calibration
6880 00:27:33.781364 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6881 00:27:33.784847 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6882 00:27:33.791684 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6883 00:27:33.794778 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6884 00:27:33.797753 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6885 00:27:33.804761 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6886 00:27:33.807943 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6887 00:27:33.811504 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6888 00:27:33.818242 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6889 00:27:33.821494 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6890 00:27:33.824497 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6891 00:27:33.828044 Total UI for P1: 0, mck2ui 16
6892 00:27:33.831417 best dqsien dly found for B0: ( 0, 14, 24)
6893 00:27:33.834513 Total UI for P1: 0, mck2ui 16
6894 00:27:33.838055 best dqsien dly found for B1: ( 0, 14, 24)
6895 00:27:33.841267 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6896 00:27:33.844505 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6897 00:27:33.844987
6898 00:27:33.851170 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6899 00:27:33.854857 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6900 00:27:33.855276 [Gating] SW calibration Done
6901 00:27:33.858136 ==
6902 00:27:33.861285 Dram Type= 6, Freq= 0, CH_1, rank 1
6903 00:27:33.864462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6904 00:27:33.865069 ==
6905 00:27:33.865622 RX Vref Scan: 0
6906 00:27:33.866010
6907 00:27:33.868087 RX Vref 0 -> 0, step: 1
6908 00:27:33.868606
6909 00:27:33.871095 RX Delay -410 -> 252, step: 16
6910 00:27:33.874522 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6911 00:27:33.881463 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6912 00:27:33.884417 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6913 00:27:33.888019 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6914 00:27:33.890974 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6915 00:27:33.897995 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6916 00:27:33.900814 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6917 00:27:33.904394 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6918 00:27:33.907918 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6919 00:27:33.914344 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6920 00:27:33.917616 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6921 00:27:33.920933 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6922 00:27:33.924331 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6923 00:27:33.931293 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6924 00:27:33.934355 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6925 00:27:33.937675 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6926 00:27:33.937960 ==
6927 00:27:33.940816 Dram Type= 6, Freq= 0, CH_1, rank 1
6928 00:27:33.944004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6929 00:27:33.947372 ==
6930 00:27:33.947452 DQS Delay:
6931 00:27:33.947531 DQS0 = 35, DQS1 = 43
6932 00:27:33.950426 DQM Delay:
6933 00:27:33.950506 DQM0 = 17, DQM1 = 19
6934 00:27:33.953661 DQ Delay:
6935 00:27:33.957421 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6936 00:27:33.957500 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =16
6937 00:27:33.960347 DQ8 =0, DQ9 =8, DQ10 =24, DQ11 =16
6938 00:27:33.963659 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =32
6939 00:27:33.966887
6940 00:27:33.966989
6941 00:27:33.967085 ==
6942 00:27:33.970249 Dram Type= 6, Freq= 0, CH_1, rank 1
6943 00:27:33.973695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6944 00:27:33.973776 ==
6945 00:27:33.973854
6946 00:27:33.973927
6947 00:27:33.976919 TX Vref Scan disable
6948 00:27:33.976999 == TX Byte 0 ==
6949 00:27:33.980240 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6950 00:27:33.987078 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6951 00:27:33.987158 == TX Byte 1 ==
6952 00:27:33.990582 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6953 00:27:33.996888 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6954 00:27:33.996987 ==
6955 00:27:34.000117 Dram Type= 6, Freq= 0, CH_1, rank 1
6956 00:27:34.003285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6957 00:27:34.003377 ==
6958 00:27:34.003460
6959 00:27:34.003539
6960 00:27:34.006983 TX Vref Scan disable
6961 00:27:34.007047 == TX Byte 0 ==
6962 00:27:34.010189 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6963 00:27:34.016888 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6964 00:27:34.016965 == TX Byte 1 ==
6965 00:27:34.020287 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6966 00:27:34.026844 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6967 00:27:34.026936
6968 00:27:34.027023 [DATLAT]
6969 00:27:34.027104 Freq=400, CH1 RK1
6970 00:27:34.027183
6971 00:27:34.029857 DATLAT Default: 0xe
6972 00:27:34.033508 0, 0xFFFF, sum = 0
6973 00:27:34.033606 1, 0xFFFF, sum = 0
6974 00:27:34.036674 2, 0xFFFF, sum = 0
6975 00:27:34.036809 3, 0xFFFF, sum = 0
6976 00:27:34.040259 4, 0xFFFF, sum = 0
6977 00:27:34.040352 5, 0xFFFF, sum = 0
6978 00:27:34.043512 6, 0xFFFF, sum = 0
6979 00:27:34.043603 7, 0xFFFF, sum = 0
6980 00:27:34.046573 8, 0xFFFF, sum = 0
6981 00:27:34.046663 9, 0xFFFF, sum = 0
6982 00:27:34.050173 10, 0xFFFF, sum = 0
6983 00:27:34.050261 11, 0xFFFF, sum = 0
6984 00:27:34.053514 12, 0xFFFF, sum = 0
6985 00:27:34.053580 13, 0x0, sum = 1
6986 00:27:34.056758 14, 0x0, sum = 2
6987 00:27:34.056823 15, 0x0, sum = 3
6988 00:27:34.059901 16, 0x0, sum = 4
6989 00:27:34.059964 best_step = 14
6990 00:27:34.060029
6991 00:27:34.060084 ==
6992 00:27:34.063195 Dram Type= 6, Freq= 0, CH_1, rank 1
6993 00:27:34.066758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6994 00:27:34.069910 ==
6995 00:27:34.070003 RX Vref Scan: 0
6996 00:27:34.070086
6997 00:27:34.073261 RX Vref 0 -> 0, step: 1
6998 00:27:34.073431
6999 00:27:34.076385 RX Delay -327 -> 252, step: 8
7000 00:27:34.083186 iDelay=217, Bit 0, Center -16 (-231 ~ 200) 432
7001 00:27:34.086708 iDelay=217, Bit 1, Center -28 (-247 ~ 192) 440
7002 00:27:34.090196 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
7003 00:27:34.093426 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
7004 00:27:34.096949 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
7005 00:27:34.103199 iDelay=217, Bit 5, Center -12 (-239 ~ 216) 456
7006 00:27:34.106411 iDelay=217, Bit 6, Center -16 (-239 ~ 208) 448
7007 00:27:34.109980 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
7008 00:27:34.113322 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
7009 00:27:34.120073 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
7010 00:27:34.123180 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
7011 00:27:34.126242 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
7012 00:27:34.133359 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
7013 00:27:34.136539 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
7014 00:27:34.140249 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
7015 00:27:34.143193 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
7016 00:27:34.143293 ==
7017 00:27:34.146278 Dram Type= 6, Freq= 0, CH_1, rank 1
7018 00:27:34.153158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7019 00:27:34.153234 ==
7020 00:27:34.153309 DQS Delay:
7021 00:27:34.156482 DQS0 = 32, DQS1 = 36
7022 00:27:34.156548 DQM Delay:
7023 00:27:34.159511 DQM0 = 12, DQM1 = 12
7024 00:27:34.159589 DQ Delay:
7025 00:27:34.162929 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =12
7026 00:27:34.166322 DQ4 =16, DQ5 =20, DQ6 =16, DQ7 =12
7027 00:27:34.169678 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =8
7028 00:27:34.173048 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =24
7029 00:27:34.173126
7030 00:27:34.173202
7031 00:27:34.179792 [DQSOSCAuto] RK1, (LSB)MR18= 0xaf57, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 388 ps
7032 00:27:34.182757 CH1 RK1: MR19=C0C, MR18=AF57
7033 00:27:34.189845 CH1_RK1: MR19=0xC0C, MR18=0xAF57, DQSOSC=388, MR23=63, INC=392, DEC=261
7034 00:27:34.192888 [RxdqsGatingPostProcess] freq 400
7035 00:27:34.196050 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7036 00:27:34.199628 best DQS0 dly(2T, 0.5T) = (0, 10)
7037 00:27:34.203126 best DQS1 dly(2T, 0.5T) = (0, 10)
7038 00:27:34.206289 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7039 00:27:34.209872 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7040 00:27:34.212947 best DQS0 dly(2T, 0.5T) = (0, 10)
7041 00:27:34.215959 best DQS1 dly(2T, 0.5T) = (0, 10)
7042 00:27:34.219465 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7043 00:27:34.222917 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7044 00:27:34.226024 Pre-setting of DQS Precalculation
7045 00:27:34.230843 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7046 00:27:34.236217 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7047 00:27:34.246130 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7048 00:27:34.246234
7049 00:27:34.246406
7050 00:27:34.249525 [Calibration Summary] 800 Mbps
7051 00:27:34.249625 CH 0, Rank 0
7052 00:27:34.252872 SW Impedance : PASS
7053 00:27:34.252945 DUTY Scan : NO K
7054 00:27:34.256336 ZQ Calibration : PASS
7055 00:27:34.259440 Jitter Meter : NO K
7056 00:27:34.259551 CBT Training : PASS
7057 00:27:34.262985 Write leveling : PASS
7058 00:27:34.263095 RX DQS gating : PASS
7059 00:27:34.266176 RX DQ/DQS(RDDQC) : PASS
7060 00:27:34.269428 TX DQ/DQS : PASS
7061 00:27:34.269507 RX DATLAT : PASS
7062 00:27:34.272859 RX DQ/DQS(Engine): PASS
7063 00:27:34.275859 TX OE : NO K
7064 00:27:34.275953 All Pass.
7065 00:27:34.276029
7066 00:27:34.276086 CH 0, Rank 1
7067 00:27:34.279325 SW Impedance : PASS
7068 00:27:34.282872 DUTY Scan : NO K
7069 00:27:34.282983 ZQ Calibration : PASS
7070 00:27:34.286041 Jitter Meter : NO K
7071 00:27:34.289473 CBT Training : PASS
7072 00:27:34.289554 Write leveling : NO K
7073 00:27:34.292973 RX DQS gating : PASS
7074 00:27:34.296221 RX DQ/DQS(RDDQC) : PASS
7075 00:27:34.296298 TX DQ/DQS : PASS
7076 00:27:34.299530 RX DATLAT : PASS
7077 00:27:34.299613 RX DQ/DQS(Engine): PASS
7078 00:27:34.302935 TX OE : NO K
7079 00:27:34.303026 All Pass.
7080 00:27:34.303095
7081 00:27:34.306724 CH 1, Rank 0
7082 00:27:34.306821 SW Impedance : PASS
7083 00:27:34.309583 DUTY Scan : NO K
7084 00:27:34.312900 ZQ Calibration : PASS
7085 00:27:34.313005 Jitter Meter : NO K
7086 00:27:34.316374 CBT Training : PASS
7087 00:27:34.320094 Write leveling : PASS
7088 00:27:34.320210 RX DQS gating : PASS
7089 00:27:34.323072 RX DQ/DQS(RDDQC) : PASS
7090 00:27:34.326177 TX DQ/DQS : PASS
7091 00:27:34.326306 RX DATLAT : PASS
7092 00:27:34.329720 RX DQ/DQS(Engine): PASS
7093 00:27:34.332892 TX OE : NO K
7094 00:27:34.333055 All Pass.
7095 00:27:34.333180
7096 00:27:34.333296 CH 1, Rank 1
7097 00:27:34.335993 SW Impedance : PASS
7098 00:27:34.339554 DUTY Scan : NO K
7099 00:27:34.339744 ZQ Calibration : PASS
7100 00:27:34.342956 Jitter Meter : NO K
7101 00:27:34.346472 CBT Training : PASS
7102 00:27:34.346698 Write leveling : NO K
7103 00:27:34.349886 RX DQS gating : PASS
7104 00:27:34.350165 RX DQ/DQS(RDDQC) : PASS
7105 00:27:34.353141 TX DQ/DQS : PASS
7106 00:27:34.356424 RX DATLAT : PASS
7107 00:27:34.356821 RX DQ/DQS(Engine): PASS
7108 00:27:34.359765 TX OE : NO K
7109 00:27:34.360163 All Pass.
7110 00:27:34.360471
7111 00:27:34.363401 DramC Write-DBI off
7112 00:27:34.366416 PER_BANK_REFRESH: Hybrid Mode
7113 00:27:34.367070 TX_TRACKING: ON
7114 00:27:34.376389 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7115 00:27:34.379853 [FAST_K] Save calibration result to emmc
7116 00:27:34.383235 dramc_set_vcore_voltage set vcore to 725000
7117 00:27:34.386667 Read voltage for 1600, 0
7118 00:27:34.387127 Vio18 = 0
7119 00:27:34.387590 Vcore = 725000
7120 00:27:34.389580 Vdram = 0
7121 00:27:34.390124 Vddq = 0
7122 00:27:34.390597 Vmddr = 0
7123 00:27:34.396442 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7124 00:27:34.400110 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7125 00:27:34.403251 MEM_TYPE=3, freq_sel=13
7126 00:27:34.406351 sv_algorithm_assistance_LP4_3733
7127 00:27:34.409819 ============ PULL DRAM RESETB DOWN ============
7128 00:27:34.416292 ========== PULL DRAM RESETB DOWN end =========
7129 00:27:34.420004 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7130 00:27:34.423172 ===================================
7131 00:27:34.426903 LPDDR4 DRAM CONFIGURATION
7132 00:27:34.429898 ===================================
7133 00:27:34.430291 EX_ROW_EN[0] = 0x0
7134 00:27:34.433349 EX_ROW_EN[1] = 0x0
7135 00:27:34.433746 LP4Y_EN = 0x0
7136 00:27:34.436350 WORK_FSP = 0x1
7137 00:27:34.436785 WL = 0x5
7138 00:27:34.440070 RL = 0x5
7139 00:27:34.440465 BL = 0x2
7140 00:27:34.443019 RPST = 0x0
7141 00:27:34.443412 RD_PRE = 0x0
7142 00:27:34.446487 WR_PRE = 0x1
7143 00:27:34.446885 WR_PST = 0x1
7144 00:27:34.449611 DBI_WR = 0x0
7145 00:27:34.449999 DBI_RD = 0x0
7146 00:27:34.452765 OTF = 0x1
7147 00:27:34.456289 ===================================
7148 00:27:34.459724 ===================================
7149 00:27:34.460114 ANA top config
7150 00:27:34.463133 ===================================
7151 00:27:34.466174 DLL_ASYNC_EN = 0
7152 00:27:34.469440 ALL_SLAVE_EN = 0
7153 00:27:34.472886 NEW_RANK_MODE = 1
7154 00:27:34.473283 DLL_IDLE_MODE = 1
7155 00:27:34.476094 LP45_APHY_COMB_EN = 1
7156 00:27:34.479688 TX_ODT_DIS = 0
7157 00:27:34.482788 NEW_8X_MODE = 1
7158 00:27:34.486219 ===================================
7159 00:27:34.489655 ===================================
7160 00:27:34.492915 data_rate = 3200
7161 00:27:34.496103 CKR = 1
7162 00:27:34.496488 DQ_P2S_RATIO = 8
7163 00:27:34.499591 ===================================
7164 00:27:34.502809 CA_P2S_RATIO = 8
7165 00:27:34.505735 DQ_CA_OPEN = 0
7166 00:27:34.509333 DQ_SEMI_OPEN = 0
7167 00:27:34.512858 CA_SEMI_OPEN = 0
7168 00:27:34.515970 CA_FULL_RATE = 0
7169 00:27:34.516360 DQ_CKDIV4_EN = 0
7170 00:27:34.519498 CA_CKDIV4_EN = 0
7171 00:27:34.522613 CA_PREDIV_EN = 0
7172 00:27:34.526609 PH8_DLY = 12
7173 00:27:34.529749 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7174 00:27:34.530138 DQ_AAMCK_DIV = 4
7175 00:27:34.532804 CA_AAMCK_DIV = 4
7176 00:27:34.535766 CA_ADMCK_DIV = 4
7177 00:27:34.539637 DQ_TRACK_CA_EN = 0
7178 00:27:34.542998 CA_PICK = 1600
7179 00:27:34.546012 CA_MCKIO = 1600
7180 00:27:34.549179 MCKIO_SEMI = 0
7181 00:27:34.552654 PLL_FREQ = 3068
7182 00:27:34.553066 DQ_UI_PI_RATIO = 32
7183 00:27:34.555392 CA_UI_PI_RATIO = 0
7184 00:27:34.559322 ===================================
7185 00:27:34.562264 ===================================
7186 00:27:34.565821 memory_type:LPDDR4
7187 00:27:34.569298 GP_NUM : 10
7188 00:27:34.569376 SRAM_EN : 1
7189 00:27:34.572194 MD32_EN : 0
7190 00:27:34.576039 ===================================
7191 00:27:34.576116 [ANA_INIT] >>>>>>>>>>>>>>
7192 00:27:34.579218 <<<<<< [CONFIGURE PHASE]: ANA_TX
7193 00:27:34.582260 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7194 00:27:34.585734 ===================================
7195 00:27:34.588927 data_rate = 3200,PCW = 0X7600
7196 00:27:34.592370 ===================================
7197 00:27:34.595705 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7198 00:27:34.602414 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7199 00:27:34.605307 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7200 00:27:34.612399 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7201 00:27:34.615553 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7202 00:27:34.618888 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7203 00:27:34.622004 [ANA_INIT] flow start
7204 00:27:34.622082 [ANA_INIT] PLL >>>>>>>>
7205 00:27:34.625574 [ANA_INIT] PLL <<<<<<<<
7206 00:27:34.629166 [ANA_INIT] MIDPI >>>>>>>>
7207 00:27:34.629241 [ANA_INIT] MIDPI <<<<<<<<
7208 00:27:34.631992 [ANA_INIT] DLL >>>>>>>>
7209 00:27:34.635609 [ANA_INIT] DLL <<<<<<<<
7210 00:27:34.635684 [ANA_INIT] flow end
7211 00:27:34.641907 ============ LP4 DIFF to SE enter ============
7212 00:27:34.645418 ============ LP4 DIFF to SE exit ============
7213 00:27:34.645494 [ANA_INIT] <<<<<<<<<<<<<
7214 00:27:34.648431 [Flow] Enable top DCM control >>>>>
7215 00:27:34.652055 [Flow] Enable top DCM control <<<<<
7216 00:27:34.655184 Enable DLL master slave shuffle
7217 00:27:34.662263 ==============================================================
7218 00:27:34.665345 Gating Mode config
7219 00:27:34.669090 ==============================================================
7220 00:27:34.671770 Config description:
7221 00:27:34.681817 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7222 00:27:34.688792 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7223 00:27:34.692340 SELPH_MODE 0: By rank 1: By Phase
7224 00:27:34.698598 ==============================================================
7225 00:27:34.702041 GAT_TRACK_EN = 1
7226 00:27:34.705303 RX_GATING_MODE = 2
7227 00:27:34.705700 RX_GATING_TRACK_MODE = 2
7228 00:27:34.708990 SELPH_MODE = 1
7229 00:27:34.712440 PICG_EARLY_EN = 1
7230 00:27:34.715390 VALID_LAT_VALUE = 1
7231 00:27:34.722284 ==============================================================
7232 00:27:34.725191 Enter into Gating configuration >>>>
7233 00:27:34.728746 Exit from Gating configuration <<<<
7234 00:27:34.732295 Enter into DVFS_PRE_config >>>>>
7235 00:27:34.741931 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7236 00:27:34.745469 Exit from DVFS_PRE_config <<<<<
7237 00:27:34.748616 Enter into PICG configuration >>>>
7238 00:27:34.752224 Exit from PICG configuration <<<<
7239 00:27:34.755162 [RX_INPUT] configuration >>>>>
7240 00:27:34.758619 [RX_INPUT] configuration <<<<<
7241 00:27:34.762363 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7242 00:27:34.768678 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7243 00:27:34.775460 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7244 00:27:34.781856 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7245 00:27:34.785383 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7246 00:27:34.792026 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7247 00:27:34.795473 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7248 00:27:34.802161 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7249 00:27:34.805081 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7250 00:27:34.808623 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7251 00:27:34.812149 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7252 00:27:34.818779 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7253 00:27:34.822009 ===================================
7254 00:27:34.822399 LPDDR4 DRAM CONFIGURATION
7255 00:27:34.825268 ===================================
7256 00:27:34.828528 EX_ROW_EN[0] = 0x0
7257 00:27:34.832236 EX_ROW_EN[1] = 0x0
7258 00:27:34.832783 LP4Y_EN = 0x0
7259 00:27:34.835534 WORK_FSP = 0x1
7260 00:27:34.836023 WL = 0x5
7261 00:27:34.838498 RL = 0x5
7262 00:27:34.838886 BL = 0x2
7263 00:27:34.842005 RPST = 0x0
7264 00:27:34.842467 RD_PRE = 0x0
7265 00:27:34.845074 WR_PRE = 0x1
7266 00:27:34.845465 WR_PST = 0x1
7267 00:27:34.848528 DBI_WR = 0x0
7268 00:27:34.848946 DBI_RD = 0x0
7269 00:27:34.851694 OTF = 0x1
7270 00:27:34.855406 ===================================
7271 00:27:34.858384 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7272 00:27:34.862042 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7273 00:27:34.868929 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7274 00:27:34.872066 ===================================
7275 00:27:34.872455 LPDDR4 DRAM CONFIGURATION
7276 00:27:34.875463 ===================================
7277 00:27:34.878879 EX_ROW_EN[0] = 0x10
7278 00:27:34.881631 EX_ROW_EN[1] = 0x0
7279 00:27:34.882015 LP4Y_EN = 0x0
7280 00:27:34.885105 WORK_FSP = 0x1
7281 00:27:34.885490 WL = 0x5
7282 00:27:34.888454 RL = 0x5
7283 00:27:34.888878 BL = 0x2
7284 00:27:34.891797 RPST = 0x0
7285 00:27:34.892179 RD_PRE = 0x0
7286 00:27:34.895042 WR_PRE = 0x1
7287 00:27:34.895428 WR_PST = 0x1
7288 00:27:34.898527 DBI_WR = 0x0
7289 00:27:34.898918 DBI_RD = 0x0
7290 00:27:34.901518 OTF = 0x1
7291 00:27:34.905275 ===================================
7292 00:27:34.911931 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7293 00:27:34.912318 ==
7294 00:27:34.915004 Dram Type= 6, Freq= 0, CH_0, rank 0
7295 00:27:34.918330 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7296 00:27:34.918756 ==
7297 00:27:34.921959 [Duty_Offset_Calibration]
7298 00:27:34.922345 B0:2 B1:0 CA:1
7299 00:27:34.922661
7300 00:27:34.925040 [DutyScan_Calibration_Flow] k_type=0
7301 00:27:34.934197
7302 00:27:34.934272 ==CLK 0==
7303 00:27:34.937593 Final CLK duty delay cell = -4
7304 00:27:34.940738 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7305 00:27:34.944665 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7306 00:27:34.944779 [-4] AVG Duty = 4922%(X100)
7307 00:27:34.947468
7308 00:27:34.951083 CH0 CLK Duty spec in!! Max-Min= 218%
7309 00:27:34.954071 [DutyScan_Calibration_Flow] ====Done====
7310 00:27:34.954150
7311 00:27:34.957617 [DutyScan_Calibration_Flow] k_type=1
7312 00:27:34.973365
7313 00:27:34.973442 ==DQS 0 ==
7314 00:27:34.976671 Final DQS duty delay cell = 0
7315 00:27:34.980351 [0] MAX Duty = 5249%(X100), DQS PI = 32
7316 00:27:34.983461 [0] MIN Duty = 4969%(X100), DQS PI = 0
7317 00:27:34.983538 [0] AVG Duty = 5109%(X100)
7318 00:27:34.986810
7319 00:27:34.986885 ==DQS 1 ==
7320 00:27:34.990130 Final DQS duty delay cell = -4
7321 00:27:34.993646 [-4] MAX Duty = 5125%(X100), DQS PI = 30
7322 00:27:34.996461 [-4] MIN Duty = 4844%(X100), DQS PI = 4
7323 00:27:35.000044 [-4] AVG Duty = 4984%(X100)
7324 00:27:35.000119
7325 00:27:35.003257 CH0 DQS 0 Duty spec in!! Max-Min= 280%
7326 00:27:35.003333
7327 00:27:35.006787 CH0 DQS 1 Duty spec in!! Max-Min= 281%
7328 00:27:35.009796 [DutyScan_Calibration_Flow] ====Done====
7329 00:27:35.009872
7330 00:27:35.013149 [DutyScan_Calibration_Flow] k_type=3
7331 00:27:35.030784
7332 00:27:35.030859 ==DQM 0 ==
7333 00:27:35.034324 Final DQM duty delay cell = 0
7334 00:27:35.037307 [0] MAX Duty = 5124%(X100), DQS PI = 26
7335 00:27:35.040720 [0] MIN Duty = 4813%(X100), DQS PI = 50
7336 00:27:35.044234 [0] AVG Duty = 4968%(X100)
7337 00:27:35.044310
7338 00:27:35.044368 ==DQM 1 ==
7339 00:27:35.047434 Final DQM duty delay cell = 0
7340 00:27:35.050561 [0] MAX Duty = 5249%(X100), DQS PI = 30
7341 00:27:35.054007 [0] MIN Duty = 5000%(X100), DQS PI = 18
7342 00:27:35.057557 [0] AVG Duty = 5124%(X100)
7343 00:27:35.057633
7344 00:27:35.060737 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7345 00:27:35.060828
7346 00:27:35.064158 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7347 00:27:35.067468 [DutyScan_Calibration_Flow] ====Done====
7348 00:27:35.067544
7349 00:27:35.070850 [DutyScan_Calibration_Flow] k_type=2
7350 00:27:35.087932
7351 00:27:35.088011 ==DQ 0 ==
7352 00:27:35.091532 Final DQ duty delay cell = 0
7353 00:27:35.095182 [0] MAX Duty = 5124%(X100), DQS PI = 34
7354 00:27:35.097963 [0] MIN Duty = 5000%(X100), DQS PI = 0
7355 00:27:35.098040 [0] AVG Duty = 5062%(X100)
7356 00:27:35.098099
7357 00:27:35.101564 ==DQ 1 ==
7358 00:27:35.104682 Final DQ duty delay cell = 0
7359 00:27:35.108266 [0] MAX Duty = 4938%(X100), DQS PI = 8
7360 00:27:35.111692 [0] MIN Duty = 4875%(X100), DQS PI = 0
7361 00:27:35.111768 [0] AVG Duty = 4906%(X100)
7362 00:27:35.111828
7363 00:27:35.114715 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7364 00:27:35.114792
7365 00:27:35.118407 CH0 DQ 1 Duty spec in!! Max-Min= 63%
7366 00:27:35.124670 [DutyScan_Calibration_Flow] ====Done====
7367 00:27:35.124761 ==
7368 00:27:35.128286 Dram Type= 6, Freq= 0, CH_1, rank 0
7369 00:27:35.131396 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7370 00:27:35.131472 ==
7371 00:27:35.134568 [Duty_Offset_Calibration]
7372 00:27:35.134642 B0:0 B1:-1 CA:2
7373 00:27:35.134700
7374 00:27:35.137954 [DutyScan_Calibration_Flow] k_type=0
7375 00:27:35.148309
7376 00:27:35.148384 ==CLK 0==
7377 00:27:35.151159 Final CLK duty delay cell = 0
7378 00:27:35.154428 [0] MAX Duty = 5156%(X100), DQS PI = 10
7379 00:27:35.158164 [0] MIN Duty = 4906%(X100), DQS PI = 46
7380 00:27:35.161380 [0] AVG Duty = 5031%(X100)
7381 00:27:35.161455
7382 00:27:35.164478 CH1 CLK Duty spec in!! Max-Min= 250%
7383 00:27:35.168003 [DutyScan_Calibration_Flow] ====Done====
7384 00:27:35.168078
7385 00:27:35.170988 [DutyScan_Calibration_Flow] k_type=1
7386 00:27:35.187952
7387 00:27:35.188028 ==DQS 0 ==
7388 00:27:35.191330 Final DQS duty delay cell = 0
7389 00:27:35.194577 [0] MAX Duty = 5093%(X100), DQS PI = 24
7390 00:27:35.198156 [0] MIN Duty = 4969%(X100), DQS PI = 2
7391 00:27:35.198231 [0] AVG Duty = 5031%(X100)
7392 00:27:35.201141
7393 00:27:35.201216 ==DQS 1 ==
7394 00:27:35.204820 Final DQS duty delay cell = 0
7395 00:27:35.207887 [0] MAX Duty = 5187%(X100), DQS PI = 0
7396 00:27:35.211095 [0] MIN Duty = 4844%(X100), DQS PI = 32
7397 00:27:35.211186 [0] AVG Duty = 5015%(X100)
7398 00:27:35.214653
7399 00:27:35.218048 CH1 DQS 0 Duty spec in!! Max-Min= 124%
7400 00:27:35.218123
7401 00:27:35.221039 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7402 00:27:35.224443 [DutyScan_Calibration_Flow] ====Done====
7403 00:27:35.224518
7404 00:27:35.227516 [DutyScan_Calibration_Flow] k_type=3
7405 00:27:35.245213
7406 00:27:35.245294 ==DQM 0 ==
7407 00:27:35.249022 Final DQM duty delay cell = 4
7408 00:27:35.252026 [4] MAX Duty = 5125%(X100), DQS PI = 22
7409 00:27:35.255643 [4] MIN Duty = 4969%(X100), DQS PI = 44
7410 00:27:35.258667 [4] AVG Duty = 5047%(X100)
7411 00:27:35.258741
7412 00:27:35.258799 ==DQM 1 ==
7413 00:27:35.262154 Final DQM duty delay cell = 0
7414 00:27:35.265369 [0] MAX Duty = 5281%(X100), DQS PI = 58
7415 00:27:35.269113 [0] MIN Duty = 4875%(X100), DQS PI = 36
7416 00:27:35.269188 [0] AVG Duty = 5078%(X100)
7417 00:27:35.271973
7418 00:27:35.275593 CH1 DQM 0 Duty spec in!! Max-Min= 156%
7419 00:27:35.275669
7420 00:27:35.278608 CH1 DQM 1 Duty spec in!! Max-Min= 406%
7421 00:27:35.282267 [DutyScan_Calibration_Flow] ====Done====
7422 00:27:35.282343
7423 00:27:35.285279 [DutyScan_Calibration_Flow] k_type=2
7424 00:27:35.302236
7425 00:27:35.302330 ==DQ 0 ==
7426 00:27:35.305894 Final DQ duty delay cell = 0
7427 00:27:35.309185 [0] MAX Duty = 5062%(X100), DQS PI = 20
7428 00:27:35.312099 [0] MIN Duty = 4969%(X100), DQS PI = 0
7429 00:27:35.312213 [0] AVG Duty = 5015%(X100)
7430 00:27:35.312300
7431 00:27:35.315516 ==DQ 1 ==
7432 00:27:35.318915 Final DQ duty delay cell = 0
7433 00:27:35.322426 [0] MAX Duty = 5062%(X100), DQS PI = 2
7434 00:27:35.325685 [0] MIN Duty = 4813%(X100), DQS PI = 34
7435 00:27:35.325826 [0] AVG Duty = 4937%(X100)
7436 00:27:35.325937
7437 00:27:35.328977 CH1 DQ 0 Duty spec in!! Max-Min= 93%
7438 00:27:35.329134
7439 00:27:35.332641 CH1 DQ 1 Duty spec in!! Max-Min= 249%
7440 00:27:35.339069 [DutyScan_Calibration_Flow] ====Done====
7441 00:27:35.342764 nWR fixed to 30
7442 00:27:35.343148 [ModeRegInit_LP4] CH0 RK0
7443 00:27:35.345822 [ModeRegInit_LP4] CH0 RK1
7444 00:27:35.349332 [ModeRegInit_LP4] CH1 RK0
7445 00:27:35.349716 [ModeRegInit_LP4] CH1 RK1
7446 00:27:35.352796 match AC timing 5
7447 00:27:35.355990 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7448 00:27:35.359571 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7449 00:27:35.366200 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7450 00:27:35.369363 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7451 00:27:35.375906 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7452 00:27:35.376295 [MiockJmeterHQA]
7453 00:27:35.376623
7454 00:27:35.379502 [DramcMiockJmeter] u1RxGatingPI = 0
7455 00:27:35.382260 0 : 4252, 4027
7456 00:27:35.382647 4 : 4253, 4027
7457 00:27:35.382952 8 : 4253, 4027
7458 00:27:35.385995 12 : 4252, 4027
7459 00:27:35.386385 16 : 4252, 4026
7460 00:27:35.389399 20 : 4363, 4138
7461 00:27:35.389787 24 : 4252, 4027
7462 00:27:35.392697 28 : 4363, 4137
7463 00:27:35.393123 32 : 4252, 4027
7464 00:27:35.393432 36 : 4253, 4026
7465 00:27:35.396155 40 : 4252, 4027
7466 00:27:35.396543 44 : 4255, 4029
7467 00:27:35.399106 48 : 4253, 4026
7468 00:27:35.399587 52 : 4252, 4027
7469 00:27:35.402207 56 : 4366, 4139
7470 00:27:35.402596 60 : 4252, 4027
7471 00:27:35.405878 64 : 4252, 4029
7472 00:27:35.406325 68 : 4250, 4027
7473 00:27:35.406629 72 : 4363, 4140
7474 00:27:35.409372 76 : 4250, 4027
7475 00:27:35.409761 80 : 4360, 4138
7476 00:27:35.412438 84 : 4252, 4030
7477 00:27:35.412960 88 : 4250, 3546
7478 00:27:35.415905 92 : 4250, 0
7479 00:27:35.416297 96 : 4360, 0
7480 00:27:35.416639 100 : 4252, 0
7481 00:27:35.418946 104 : 4252, 0
7482 00:27:35.419335 108 : 4360, 0
7483 00:27:35.419639 112 : 4250, 0
7484 00:27:35.422194 116 : 4250, 0
7485 00:27:35.422599 120 : 4250, 0
7486 00:27:35.425728 124 : 4360, 0
7487 00:27:35.426123 128 : 4360, 0
7488 00:27:35.426429 132 : 4250, 0
7489 00:27:35.429217 136 : 4250, 0
7490 00:27:35.429609 140 : 4250, 0
7491 00:27:35.432545 144 : 4252, 0
7492 00:27:35.432962 148 : 4250, 0
7493 00:27:35.433265 152 : 4250, 0
7494 00:27:35.435693 156 : 4252, 0
7495 00:27:35.436082 160 : 4360, 0
7496 00:27:35.438856 164 : 4250, 0
7497 00:27:35.439347 168 : 4250, 0
7498 00:27:35.439668 172 : 4250, 0
7499 00:27:35.442349 176 : 4361, 0
7500 00:27:35.442736 180 : 4360, 0
7501 00:27:35.443035 184 : 4250, 0
7502 00:27:35.445753 188 : 4250, 0
7503 00:27:35.446143 192 : 4250, 0
7504 00:27:35.449069 196 : 4252, 0
7505 00:27:35.449541 200 : 4250, 6
7506 00:27:35.452432 204 : 4250, 2564
7507 00:27:35.452858 208 : 4255, 4029
7508 00:27:35.453171 212 : 4360, 4138
7509 00:27:35.455437 216 : 4250, 4027
7510 00:27:35.455871 220 : 4250, 4026
7511 00:27:35.459008 224 : 4361, 4137
7512 00:27:35.459395 228 : 4363, 4138
7513 00:27:35.462288 232 : 4250, 4027
7514 00:27:35.462680 236 : 4363, 4140
7515 00:27:35.465439 240 : 4250, 4026
7516 00:27:35.465829 244 : 4250, 4027
7517 00:27:35.469136 248 : 4249, 4027
7518 00:27:35.469529 252 : 4252, 4029
7519 00:27:35.472131 256 : 4250, 4026
7520 00:27:35.472524 260 : 4250, 4027
7521 00:27:35.475857 264 : 4249, 4027
7522 00:27:35.476247 268 : 4252, 4029
7523 00:27:35.476552 272 : 4250, 4026
7524 00:27:35.478670 276 : 4361, 4137
7525 00:27:35.479114 280 : 4363, 4140
7526 00:27:35.482173 284 : 4249, 4027
7527 00:27:35.482565 288 : 4363, 4140
7528 00:27:35.485467 292 : 4250, 4026
7529 00:27:35.485855 296 : 4250, 4027
7530 00:27:35.488602 300 : 4249, 4027
7531 00:27:35.489031 304 : 4252, 4029
7532 00:27:35.492341 308 : 4250, 4026
7533 00:27:35.492760 312 : 4250, 3928
7534 00:27:35.495435 316 : 4250, 1819
7535 00:27:35.495822
7536 00:27:35.496118 MIOCK jitter meter ch=0
7537 00:27:35.496396
7538 00:27:35.498991 1T = (316-92) = 224 dly cells
7539 00:27:35.505223 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7540 00:27:35.505615 ==
7541 00:27:35.508755 Dram Type= 6, Freq= 0, CH_0, rank 0
7542 00:27:35.512162 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7543 00:27:35.512551 ==
7544 00:27:35.518358 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7545 00:27:35.521885 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7546 00:27:35.524913 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7547 00:27:35.531324 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7548 00:27:35.541101 [CA 0] Center 42 (12~73) winsize 62
7549 00:27:35.544400 [CA 1] Center 42 (12~72) winsize 61
7550 00:27:35.548074 [CA 2] Center 37 (7~67) winsize 61
7551 00:27:35.551067 [CA 3] Center 37 (7~67) winsize 61
7552 00:27:35.554317 [CA 4] Center 36 (6~66) winsize 61
7553 00:27:35.557592 [CA 5] Center 35 (5~65) winsize 61
7554 00:27:35.557687
7555 00:27:35.561011 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7556 00:27:35.561087
7557 00:27:35.564482 [CATrainingPosCal] consider 1 rank data
7558 00:27:35.567798 u2DelayCellTimex100 = 290/100 ps
7559 00:27:35.571059 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7560 00:27:35.577849 CA1 delay=42 (12~72),Diff = 7 PI (23 cell)
7561 00:27:35.580845 CA2 delay=37 (7~67),Diff = 2 PI (6 cell)
7562 00:27:35.584133 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7563 00:27:35.587681 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7564 00:27:35.590760 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7565 00:27:35.590836
7566 00:27:35.594247 CA PerBit enable=1, Macro0, CA PI delay=35
7567 00:27:35.594323
7568 00:27:35.597553 [CBTSetCACLKResult] CA Dly = 35
7569 00:27:35.601061 CS Dly: 10 (0~41)
7570 00:27:35.604166 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7571 00:27:35.607512 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7572 00:27:35.607589 ==
7573 00:27:35.610780 Dram Type= 6, Freq= 0, CH_0, rank 1
7574 00:27:35.613984 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7575 00:27:35.617545 ==
7576 00:27:35.620620 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7577 00:27:35.624025 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7578 00:27:35.630679 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7579 00:27:35.637190 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7580 00:27:35.644376 [CA 0] Center 43 (13~73) winsize 61
7581 00:27:35.647737 [CA 1] Center 43 (13~73) winsize 61
7582 00:27:35.651418 [CA 2] Center 38 (8~68) winsize 61
7583 00:27:35.654306 [CA 3] Center 37 (8~67) winsize 60
7584 00:27:35.657967 [CA 4] Center 36 (6~66) winsize 61
7585 00:27:35.661353 [CA 5] Center 36 (6~66) winsize 61
7586 00:27:35.661436
7587 00:27:35.664657 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7588 00:27:35.664770
7589 00:27:35.668041 [CATrainingPosCal] consider 2 rank data
7590 00:27:35.671225 u2DelayCellTimex100 = 290/100 ps
7591 00:27:35.674542 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7592 00:27:35.681305 CA1 delay=42 (13~72),Diff = 7 PI (23 cell)
7593 00:27:35.684618 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7594 00:27:35.688121 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7595 00:27:35.691368 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7596 00:27:35.694362 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7597 00:27:35.694524
7598 00:27:35.698060 CA PerBit enable=1, Macro0, CA PI delay=35
7599 00:27:35.698293
7600 00:27:35.701100 [CBTSetCACLKResult] CA Dly = 35
7601 00:27:35.704844 CS Dly: 11 (0~43)
7602 00:27:35.707482 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7603 00:27:35.711522 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7604 00:27:35.711879
7605 00:27:35.714707 ----->DramcWriteLeveling(PI) begin...
7606 00:27:35.715066 ==
7607 00:27:35.718151 Dram Type= 6, Freq= 0, CH_0, rank 0
7608 00:27:35.721499 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7609 00:27:35.724829 ==
7610 00:27:35.725356 Write leveling (Byte 0): 37 => 37
7611 00:27:35.728610 Write leveling (Byte 1): 31 => 31
7612 00:27:35.731488 DramcWriteLeveling(PI) end<-----
7613 00:27:35.731998
7614 00:27:35.732336 ==
7615 00:27:35.735105 Dram Type= 6, Freq= 0, CH_0, rank 0
7616 00:27:35.741396 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7617 00:27:35.741910 ==
7618 00:27:35.744692 [Gating] SW mode calibration
7619 00:27:35.751382 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7620 00:27:35.755211 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7621 00:27:35.761536 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7622 00:27:35.764487 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7623 00:27:35.768500 1 4 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
7624 00:27:35.774921 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7625 00:27:35.777546 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7626 00:27:35.781289 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7627 00:27:35.784651 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7628 00:27:35.790891 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7629 00:27:35.794576 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7630 00:27:35.798332 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7631 00:27:35.804487 1 5 8 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
7632 00:27:35.807835 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7633 00:27:35.811365 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7634 00:27:35.818061 1 5 20 | B1->B0 | 2b2b 2323 | 0 0 | (0 1) (0 0)
7635 00:27:35.821284 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7636 00:27:35.824530 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7637 00:27:35.831191 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7638 00:27:35.834752 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7639 00:27:35.837672 1 6 8 | B1->B0 | 2323 3d3d | 0 0 | (0 0) (0 0)
7640 00:27:35.844694 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7641 00:27:35.848302 1 6 16 | B1->B0 | 2e2e 4646 | 1 0 | (0 0) (0 0)
7642 00:27:35.851363 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7643 00:27:35.858109 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7644 00:27:35.861424 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7645 00:27:35.864380 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7646 00:27:35.871314 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7647 00:27:35.874292 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7648 00:27:35.877875 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7649 00:27:35.881232 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7650 00:27:35.887986 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7651 00:27:35.890828 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7652 00:27:35.894179 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7653 00:27:35.900827 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7654 00:27:35.904661 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7655 00:27:35.907532 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7656 00:27:35.914598 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7657 00:27:35.917634 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7658 00:27:35.921280 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7659 00:27:35.927321 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7660 00:27:35.930904 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7661 00:27:35.933970 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7662 00:27:35.940677 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7663 00:27:35.944490 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7664 00:27:35.947829 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7665 00:27:35.954623 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7666 00:27:35.955139 Total UI for P1: 0, mck2ui 16
7667 00:27:35.961150 best dqsien dly found for B0: ( 1, 9, 10)
7668 00:27:35.964779 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7669 00:27:35.967669 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7670 00:27:35.971176 Total UI for P1: 0, mck2ui 16
7671 00:27:35.974515 best dqsien dly found for B1: ( 1, 9, 18)
7672 00:27:35.977385 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7673 00:27:35.980816 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7674 00:27:35.981250
7675 00:27:35.987710 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7676 00:27:35.990741 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7677 00:27:35.991260 [Gating] SW calibration Done
7678 00:27:35.994016 ==
7679 00:27:35.997369 Dram Type= 6, Freq= 0, CH_0, rank 0
7680 00:27:36.000770 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7681 00:27:36.001291 ==
7682 00:27:36.001632 RX Vref Scan: 0
7683 00:27:36.002046
7684 00:27:36.004237 RX Vref 0 -> 0, step: 1
7685 00:27:36.004671
7686 00:27:36.007355 RX Delay 0 -> 252, step: 8
7687 00:27:36.010715 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
7688 00:27:36.014088 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7689 00:27:36.017239 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7690 00:27:36.023847 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7691 00:27:36.027765 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7692 00:27:36.030876 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7693 00:27:36.034420 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7694 00:27:36.037043 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7695 00:27:36.040600 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7696 00:27:36.047202 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7697 00:27:36.050954 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7698 00:27:36.054560 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
7699 00:27:36.057650 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7700 00:27:36.063889 iDelay=200, Bit 13, Center 131 (88 ~ 175) 88
7701 00:27:36.067364 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7702 00:27:36.070752 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7703 00:27:36.071189 ==
7704 00:27:36.073753 Dram Type= 6, Freq= 0, CH_0, rank 0
7705 00:27:36.077160 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7706 00:27:36.077681 ==
7707 00:27:36.080311 DQS Delay:
7708 00:27:36.080782 DQS0 = 0, DQS1 = 0
7709 00:27:36.083393 DQM Delay:
7710 00:27:36.083925 DQM0 = 138, DQM1 = 127
7711 00:27:36.084370 DQ Delay:
7712 00:27:36.086708 DQ0 =139, DQ1 =139, DQ2 =135, DQ3 =135
7713 00:27:36.093317 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =147
7714 00:27:36.096695 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =123
7715 00:27:36.099921 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7716 00:27:36.100575
7717 00:27:36.101174
7718 00:27:36.101708 ==
7719 00:27:36.103445 Dram Type= 6, Freq= 0, CH_0, rank 0
7720 00:27:36.106486 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7721 00:27:36.106979 ==
7722 00:27:36.107305
7723 00:27:36.107801
7724 00:27:36.109748 TX Vref Scan disable
7725 00:27:36.113355 == TX Byte 0 ==
7726 00:27:36.116736 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7727 00:27:36.119945 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7728 00:27:36.123324 == TX Byte 1 ==
7729 00:27:36.126580 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7730 00:27:36.129563 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7731 00:27:36.130015 ==
7732 00:27:36.132904 Dram Type= 6, Freq= 0, CH_0, rank 0
7733 00:27:36.136746 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7734 00:27:36.139648 ==
7735 00:27:36.151108
7736 00:27:36.154387 TX Vref early break, caculate TX vref
7737 00:27:36.158011 TX Vref=16, minBit 12, minWin=22, winSum=375
7738 00:27:36.161169 TX Vref=18, minBit 6, minWin=23, winSum=384
7739 00:27:36.164597 TX Vref=20, minBit 1, minWin=24, winSum=395
7740 00:27:36.167663 TX Vref=22, minBit 10, minWin=24, winSum=404
7741 00:27:36.171202 TX Vref=24, minBit 0, minWin=25, winSum=416
7742 00:27:36.177776 TX Vref=26, minBit 2, minWin=25, winSum=418
7743 00:27:36.181098 TX Vref=28, minBit 0, minWin=26, winSum=430
7744 00:27:36.184775 TX Vref=30, minBit 0, minWin=26, winSum=424
7745 00:27:36.187949 TX Vref=32, minBit 2, minWin=25, winSum=417
7746 00:27:36.191385 TX Vref=34, minBit 7, minWin=24, winSum=407
7747 00:27:36.197988 [TxChooseVref] Worse bit 0, Min win 26, Win sum 430, Final Vref 28
7748 00:27:36.198138
7749 00:27:36.200887 Final TX Range 0 Vref 28
7750 00:27:36.201035
7751 00:27:36.201149 ==
7752 00:27:36.204391 Dram Type= 6, Freq= 0, CH_0, rank 0
7753 00:27:36.207796 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7754 00:27:36.207906 ==
7755 00:27:36.207991
7756 00:27:36.208069
7757 00:27:36.211190 TX Vref Scan disable
7758 00:27:36.217653 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7759 00:27:36.217741 == TX Byte 0 ==
7760 00:27:36.220791 u2DelayCellOfst[0]=13 cells (4 PI)
7761 00:27:36.224555 u2DelayCellOfst[1]=16 cells (5 PI)
7762 00:27:36.227436 u2DelayCellOfst[2]=13 cells (4 PI)
7763 00:27:36.231471 u2DelayCellOfst[3]=13 cells (4 PI)
7764 00:27:36.234096 u2DelayCellOfst[4]=10 cells (3 PI)
7765 00:27:36.237825 u2DelayCellOfst[5]=0 cells (0 PI)
7766 00:27:36.240916 u2DelayCellOfst[6]=20 cells (6 PI)
7767 00:27:36.244446 u2DelayCellOfst[7]=16 cells (5 PI)
7768 00:27:36.247432 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7769 00:27:36.250993 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7770 00:27:36.254382 == TX Byte 1 ==
7771 00:27:36.254461 u2DelayCellOfst[8]=0 cells (0 PI)
7772 00:27:36.257488 u2DelayCellOfst[9]=0 cells (0 PI)
7773 00:27:36.260970 u2DelayCellOfst[10]=6 cells (2 PI)
7774 00:27:36.263858 u2DelayCellOfst[11]=3 cells (1 PI)
7775 00:27:36.267434 u2DelayCellOfst[12]=10 cells (3 PI)
7776 00:27:36.271018 u2DelayCellOfst[13]=10 cells (3 PI)
7777 00:27:36.274102 u2DelayCellOfst[14]=13 cells (4 PI)
7778 00:27:36.277735 u2DelayCellOfst[15]=10 cells (3 PI)
7779 00:27:36.280949 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7780 00:27:36.287646 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7781 00:27:36.287763 DramC Write-DBI on
7782 00:27:36.287854 ==
7783 00:27:36.290621 Dram Type= 6, Freq= 0, CH_0, rank 0
7784 00:27:36.294234 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7785 00:27:36.297254 ==
7786 00:27:36.297401
7787 00:27:36.297516
7788 00:27:36.297621 TX Vref Scan disable
7789 00:27:36.300937 == TX Byte 0 ==
7790 00:27:36.304368 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7791 00:27:36.307392 == TX Byte 1 ==
7792 00:27:36.310913 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7793 00:27:36.311239 DramC Write-DBI off
7794 00:27:36.314168
7795 00:27:36.314411 [DATLAT]
7796 00:27:36.314599 Freq=1600, CH0 RK0
7797 00:27:36.314774
7798 00:27:36.317773 DATLAT Default: 0xf
7799 00:27:36.318190 0, 0xFFFF, sum = 0
7800 00:27:36.321045 1, 0xFFFF, sum = 0
7801 00:27:36.321354 2, 0xFFFF, sum = 0
7802 00:27:36.324230 3, 0xFFFF, sum = 0
7803 00:27:36.324536 4, 0xFFFF, sum = 0
7804 00:27:36.328324 5, 0xFFFF, sum = 0
7805 00:27:36.328934 6, 0xFFFF, sum = 0
7806 00:27:36.331280 7, 0xFFFF, sum = 0
7807 00:27:36.334890 8, 0xFFFF, sum = 0
7808 00:27:36.335296 9, 0xFFFF, sum = 0
7809 00:27:36.337902 10, 0xFFFF, sum = 0
7810 00:27:36.338307 11, 0xFFFF, sum = 0
7811 00:27:36.341408 12, 0xFFFF, sum = 0
7812 00:27:36.342069 13, 0xFFFF, sum = 0
7813 00:27:36.344734 14, 0x0, sum = 1
7814 00:27:36.345160 15, 0x0, sum = 2
7815 00:27:36.348186 16, 0x0, sum = 3
7816 00:27:36.348587 17, 0x0, sum = 4
7817 00:27:36.348992 best_step = 15
7818 00:27:36.351560
7819 00:27:36.351949 ==
7820 00:27:36.354666 Dram Type= 6, Freq= 0, CH_0, rank 0
7821 00:27:36.358159 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7822 00:27:36.358554 ==
7823 00:27:36.358862 RX Vref Scan: 1
7824 00:27:36.359142
7825 00:27:36.361034 Set Vref Range= 24 -> 127
7826 00:27:36.361471
7827 00:27:36.364145 RX Vref 24 -> 127, step: 1
7828 00:27:36.364443
7829 00:27:36.367654 RX Delay 19 -> 252, step: 4
7830 00:27:36.367864
7831 00:27:36.371045 Set Vref, RX VrefLevel [Byte0]: 24
7832 00:27:36.374056 [Byte1]: 24
7833 00:27:36.374284
7834 00:27:36.377581 Set Vref, RX VrefLevel [Byte0]: 25
7835 00:27:36.382625 [Byte1]: 25
7836 00:27:36.382751
7837 00:27:36.384249 Set Vref, RX VrefLevel [Byte0]: 26
7838 00:27:36.387393 [Byte1]: 26
7839 00:27:36.390934
7840 00:27:36.391045 Set Vref, RX VrefLevel [Byte0]: 27
7841 00:27:36.394158 [Byte1]: 27
7842 00:27:36.398705
7843 00:27:36.398846 Set Vref, RX VrefLevel [Byte0]: 28
7844 00:27:36.401953 [Byte1]: 28
7845 00:27:36.406268
7846 00:27:36.406408 Set Vref, RX VrefLevel [Byte0]: 29
7847 00:27:36.409545 [Byte1]: 29
7848 00:27:36.413904
7849 00:27:36.414012 Set Vref, RX VrefLevel [Byte0]: 30
7850 00:27:36.417133 [Byte1]: 30
7851 00:27:36.421452
7852 00:27:36.421558 Set Vref, RX VrefLevel [Byte0]: 31
7853 00:27:36.424544 [Byte1]: 31
7854 00:27:36.428728
7855 00:27:36.428837 Set Vref, RX VrefLevel [Byte0]: 32
7856 00:27:36.432288 [Byte1]: 32
7857 00:27:36.436568
7858 00:27:36.436723 Set Vref, RX VrefLevel [Byte0]: 33
7859 00:27:36.439905 [Byte1]: 33
7860 00:27:36.443997
7861 00:27:36.444143 Set Vref, RX VrefLevel [Byte0]: 34
7862 00:27:36.447385 [Byte1]: 34
7863 00:27:36.451624
7864 00:27:36.451801 Set Vref, RX VrefLevel [Byte0]: 35
7865 00:27:36.454957 [Byte1]: 35
7866 00:27:36.459149
7867 00:27:36.459353 Set Vref, RX VrefLevel [Byte0]: 36
7868 00:27:36.462876 [Byte1]: 36
7869 00:27:36.467052
7870 00:27:36.467450 Set Vref, RX VrefLevel [Byte0]: 37
7871 00:27:36.470098 [Byte1]: 37
7872 00:27:36.474304
7873 00:27:36.474614 Set Vref, RX VrefLevel [Byte0]: 38
7874 00:27:36.477724 [Byte1]: 38
7875 00:27:36.482054
7876 00:27:36.482368 Set Vref, RX VrefLevel [Byte0]: 39
7877 00:27:36.485531 [Byte1]: 39
7878 00:27:36.490023
7879 00:27:36.490335 Set Vref, RX VrefLevel [Byte0]: 40
7880 00:27:36.493014 [Byte1]: 40
7881 00:27:36.497142
7882 00:27:36.497325 Set Vref, RX VrefLevel [Byte0]: 41
7883 00:27:36.500539 [Byte1]: 41
7884 00:27:36.504687
7885 00:27:36.504874 Set Vref, RX VrefLevel [Byte0]: 42
7886 00:27:36.507853 [Byte1]: 42
7887 00:27:36.512449
7888 00:27:36.512631 Set Vref, RX VrefLevel [Byte0]: 43
7889 00:27:36.515287 [Byte1]: 43
7890 00:27:36.519861
7891 00:27:36.519939 Set Vref, RX VrefLevel [Byte0]: 44
7892 00:27:36.523068 [Byte1]: 44
7893 00:27:36.527077
7894 00:27:36.527154 Set Vref, RX VrefLevel [Byte0]: 45
7895 00:27:36.530598 [Byte1]: 45
7896 00:27:36.535311
7897 00:27:36.535388 Set Vref, RX VrefLevel [Byte0]: 46
7898 00:27:36.538136 [Byte1]: 46
7899 00:27:36.542314
7900 00:27:36.542391 Set Vref, RX VrefLevel [Byte0]: 47
7901 00:27:36.545794 [Byte1]: 47
7902 00:27:36.549955
7903 00:27:36.550035 Set Vref, RX VrefLevel [Byte0]: 48
7904 00:27:36.553365 [Byte1]: 48
7905 00:27:36.557562
7906 00:27:36.557640 Set Vref, RX VrefLevel [Byte0]: 49
7907 00:27:36.561039 [Byte1]: 49
7908 00:27:36.565277
7909 00:27:36.565354 Set Vref, RX VrefLevel [Byte0]: 50
7910 00:27:36.568332 [Byte1]: 50
7911 00:27:36.572897
7912 00:27:36.572975 Set Vref, RX VrefLevel [Byte0]: 51
7913 00:27:36.575868 [Byte1]: 51
7914 00:27:36.580037
7915 00:27:36.580114 Set Vref, RX VrefLevel [Byte0]: 52
7916 00:27:36.583420 [Byte1]: 52
7917 00:27:36.587597
7918 00:27:36.587673 Set Vref, RX VrefLevel [Byte0]: 53
7919 00:27:36.591406 [Byte1]: 53
7920 00:27:36.595416
7921 00:27:36.595493 Set Vref, RX VrefLevel [Byte0]: 54
7922 00:27:36.599071 [Byte1]: 54
7923 00:27:36.603034
7924 00:27:36.603111 Set Vref, RX VrefLevel [Byte0]: 55
7925 00:27:36.606489 [Byte1]: 55
7926 00:27:36.610632
7927 00:27:36.610712 Set Vref, RX VrefLevel [Byte0]: 56
7928 00:27:36.613932 [Byte1]: 56
7929 00:27:36.618004
7930 00:27:36.618084 Set Vref, RX VrefLevel [Byte0]: 57
7931 00:27:36.621586 [Byte1]: 57
7932 00:27:36.625590
7933 00:27:36.625670 Set Vref, RX VrefLevel [Byte0]: 58
7934 00:27:36.629070 [Byte1]: 58
7935 00:27:36.633461
7936 00:27:36.633541 Set Vref, RX VrefLevel [Byte0]: 59
7937 00:27:36.636554 [Byte1]: 59
7938 00:27:36.641031
7939 00:27:36.641127 Set Vref, RX VrefLevel [Byte0]: 60
7940 00:27:36.644469 [Byte1]: 60
7941 00:27:36.648173
7942 00:27:36.648252 Set Vref, RX VrefLevel [Byte0]: 61
7943 00:27:36.651663 [Byte1]: 61
7944 00:27:36.656275
7945 00:27:36.656354 Set Vref, RX VrefLevel [Byte0]: 62
7946 00:27:36.659422 [Byte1]: 62
7947 00:27:36.663909
7948 00:27:36.663988 Set Vref, RX VrefLevel [Byte0]: 63
7949 00:27:36.667232 [Byte1]: 63
7950 00:27:36.671359
7951 00:27:36.671438 Set Vref, RX VrefLevel [Byte0]: 64
7952 00:27:36.674652 [Byte1]: 64
7953 00:27:36.678956
7954 00:27:36.679036 Set Vref, RX VrefLevel [Byte0]: 65
7955 00:27:36.681844 [Byte1]: 65
7956 00:27:36.686203
7957 00:27:36.686285 Set Vref, RX VrefLevel [Byte0]: 66
7958 00:27:36.690040 [Byte1]: 66
7959 00:27:36.694096
7960 00:27:36.694192 Set Vref, RX VrefLevel [Byte0]: 67
7961 00:27:36.697210 [Byte1]: 67
7962 00:27:36.701208
7963 00:27:36.701285 Set Vref, RX VrefLevel [Byte0]: 68
7964 00:27:36.704848 [Byte1]: 68
7965 00:27:36.708962
7966 00:27:36.709038 Set Vref, RX VrefLevel [Byte0]: 69
7967 00:27:36.712575 [Byte1]: 69
7968 00:27:36.716937
7969 00:27:36.717014 Set Vref, RX VrefLevel [Byte0]: 70
7970 00:27:36.719815 [Byte1]: 70
7971 00:27:36.724225
7972 00:27:36.727517 Set Vref, RX VrefLevel [Byte0]: 71
7973 00:27:36.727597 [Byte1]: 71
7974 00:27:36.731736
7975 00:27:36.731815 Set Vref, RX VrefLevel [Byte0]: 72
7976 00:27:36.734985 [Byte1]: 72
7977 00:27:36.739029
7978 00:27:36.739109 Set Vref, RX VrefLevel [Byte0]: 73
7979 00:27:36.742482 [Byte1]: 73
7980 00:27:36.746857
7981 00:27:36.746960 Set Vref, RX VrefLevel [Byte0]: 74
7982 00:27:36.750035 [Byte1]: 74
7983 00:27:36.754690
7984 00:27:36.754770 Set Vref, RX VrefLevel [Byte0]: 75
7985 00:27:36.757686 [Byte1]: 75
7986 00:27:36.762145
7987 00:27:36.762224 Set Vref, RX VrefLevel [Byte0]: 76
7988 00:27:36.765168 [Byte1]: 76
7989 00:27:36.769745
7990 00:27:36.769824 Set Vref, RX VrefLevel [Byte0]: 77
7991 00:27:36.772638 [Byte1]: 77
7992 00:27:36.777061
7993 00:27:36.777140 Set Vref, RX VrefLevel [Byte0]: 78
7994 00:27:36.780215 [Byte1]: 78
7995 00:27:36.784585
7996 00:27:36.784691 Set Vref, RX VrefLevel [Byte0]: 79
7997 00:27:36.788086 [Byte1]: 79
7998 00:27:36.792104
7999 00:27:36.792183 Final RX Vref Byte 0 = 60 to rank0
8000 00:27:36.795694 Final RX Vref Byte 1 = 63 to rank0
8001 00:27:36.799223 Final RX Vref Byte 0 = 60 to rank1
8002 00:27:36.802570 Final RX Vref Byte 1 = 63 to rank1==
8003 00:27:36.805347 Dram Type= 6, Freq= 0, CH_0, rank 0
8004 00:27:36.812475 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8005 00:27:36.812555 ==
8006 00:27:36.812651 DQS Delay:
8007 00:27:36.812775 DQS0 = 0, DQS1 = 0
8008 00:27:36.815861 DQM Delay:
8009 00:27:36.815940 DQM0 = 136, DQM1 = 124
8010 00:27:36.818973 DQ Delay:
8011 00:27:36.821958 DQ0 =136, DQ1 =138, DQ2 =132, DQ3 =132
8012 00:27:36.825508 DQ4 =138, DQ5 =124, DQ6 =146, DQ7 =144
8013 00:27:36.829151 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =118
8014 00:27:36.832305 DQ12 =126, DQ13 =128, DQ14 =134, DQ15 =134
8015 00:27:36.832384
8016 00:27:36.832463
8017 00:27:36.832536
8018 00:27:36.835773 [DramC_TX_OE_Calibration] TA2
8019 00:27:36.838754 Original DQ_B0 (3 6) =30, OEN = 27
8020 00:27:36.842259 Original DQ_B1 (3 6) =30, OEN = 27
8021 00:27:36.845719 24, 0x0, End_B0=24 End_B1=24
8022 00:27:36.845800 25, 0x0, End_B0=25 End_B1=25
8023 00:27:36.848760 26, 0x0, End_B0=26 End_B1=26
8024 00:27:36.852357 27, 0x0, End_B0=27 End_B1=27
8025 00:27:36.855551 28, 0x0, End_B0=28 End_B1=28
8026 00:27:36.855632 29, 0x0, End_B0=29 End_B1=29
8027 00:27:36.858794 30, 0x0, End_B0=30 End_B1=30
8028 00:27:36.861914 31, 0x4141, End_B0=30 End_B1=30
8029 00:27:36.865454 Byte0 end_step=30 best_step=27
8030 00:27:36.868878 Byte1 end_step=30 best_step=27
8031 00:27:36.871970 Byte0 TX OE(2T, 0.5T) = (3, 3)
8032 00:27:36.872049 Byte1 TX OE(2T, 0.5T) = (3, 3)
8033 00:27:36.875568
8034 00:27:36.875649
8035 00:27:36.882358 [DQSOSCAuto] RK0, (LSB)MR18= 0x211f, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
8036 00:27:36.885259 CH0 RK0: MR19=303, MR18=211F
8037 00:27:36.892259 CH0_RK0: MR19=0x303, MR18=0x211F, DQSOSC=393, MR23=63, INC=23, DEC=15
8038 00:27:36.892337
8039 00:27:36.895523 ----->DramcWriteLeveling(PI) begin...
8040 00:27:36.895601 ==
8041 00:27:36.898802 Dram Type= 6, Freq= 0, CH_0, rank 1
8042 00:27:36.902332 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8043 00:27:36.902408 ==
8044 00:27:36.905490 Write leveling (Byte 0): 39 => 39
8045 00:27:36.909091 Write leveling (Byte 1): 29 => 29
8046 00:27:36.912303 DramcWriteLeveling(PI) end<-----
8047 00:27:36.912379
8048 00:27:36.912468 ==
8049 00:27:36.915362 Dram Type= 6, Freq= 0, CH_0, rank 1
8050 00:27:36.919094 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8051 00:27:36.919198 ==
8052 00:27:36.921942 [Gating] SW mode calibration
8053 00:27:36.928637 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8054 00:27:36.935317 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8055 00:27:36.938753 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8056 00:27:36.941731 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8057 00:27:36.948570 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8058 00:27:36.951632 1 4 12 | B1->B0 | 2323 302f | 1 1 | (1 1) (0 0)
8059 00:27:36.955284 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8060 00:27:36.961811 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8061 00:27:36.964992 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8062 00:27:36.968673 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8063 00:27:36.975305 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8064 00:27:36.978431 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8065 00:27:36.981976 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8066 00:27:36.988028 1 5 12 | B1->B0 | 3434 2a2a | 1 0 | (1 0) (1 0)
8067 00:27:36.991479 1 5 16 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
8068 00:27:36.995034 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8069 00:27:37.001395 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8070 00:27:37.004928 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8071 00:27:37.008359 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8072 00:27:37.015101 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8073 00:27:37.018647 1 6 8 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
8074 00:27:37.021700 1 6 12 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
8075 00:27:37.028248 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8076 00:27:37.031841 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8077 00:27:37.034884 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8078 00:27:37.038273 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8079 00:27:37.044984 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8080 00:27:37.048165 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8081 00:27:37.051767 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8082 00:27:37.058012 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8083 00:27:37.061315 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8084 00:27:37.064907 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8085 00:27:37.071691 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8086 00:27:37.074696 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8087 00:27:37.077955 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8088 00:27:37.085082 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8089 00:27:37.088055 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8090 00:27:37.091363 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8091 00:27:37.098379 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8092 00:27:37.101525 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8093 00:27:37.104911 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8094 00:27:37.111236 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8095 00:27:37.114880 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8096 00:27:37.118368 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8097 00:27:37.124929 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8098 00:27:37.128261 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8099 00:27:37.131504 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8100 00:27:37.134993 Total UI for P1: 0, mck2ui 16
8101 00:27:37.138116 best dqsien dly found for B0: ( 1, 9, 10)
8102 00:27:37.141782 Total UI for P1: 0, mck2ui 16
8103 00:27:37.145150 best dqsien dly found for B1: ( 1, 9, 12)
8104 00:27:37.148321 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8105 00:27:37.151741 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8106 00:27:37.151864
8107 00:27:37.154785 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8108 00:27:37.161515 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8109 00:27:37.161715 [Gating] SW calibration Done
8110 00:27:37.161808 ==
8111 00:27:37.164644 Dram Type= 6, Freq= 0, CH_0, rank 1
8112 00:27:37.171648 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8113 00:27:37.171776 ==
8114 00:27:37.171852 RX Vref Scan: 0
8115 00:27:37.171911
8116 00:27:37.174714 RX Vref 0 -> 0, step: 1
8117 00:27:37.174805
8118 00:27:37.178335 RX Delay 0 -> 252, step: 8
8119 00:27:37.181209 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8120 00:27:37.184560 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8121 00:27:37.188276 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8122 00:27:37.191457 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8123 00:27:37.198211 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8124 00:27:37.201237 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8125 00:27:37.204846 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8126 00:27:37.207847 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8127 00:27:37.211295 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8128 00:27:37.217853 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8129 00:27:37.221816 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8130 00:27:37.224529 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8131 00:27:37.228155 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
8132 00:27:37.234729 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8133 00:27:37.237879 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8134 00:27:37.241364 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8135 00:27:37.241472 ==
8136 00:27:37.244995 Dram Type= 6, Freq= 0, CH_0, rank 1
8137 00:27:37.247976 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8138 00:27:37.248059 ==
8139 00:27:37.251547 DQS Delay:
8140 00:27:37.251617 DQS0 = 0, DQS1 = 0
8141 00:27:37.251674 DQM Delay:
8142 00:27:37.254595 DQM0 = 135, DQM1 = 125
8143 00:27:37.254664 DQ Delay:
8144 00:27:37.257803 DQ0 =135, DQ1 =135, DQ2 =135, DQ3 =131
8145 00:27:37.261180 DQ4 =135, DQ5 =127, DQ6 =143, DQ7 =143
8146 00:27:37.267853 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =123
8147 00:27:37.271185 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
8148 00:27:37.271260
8149 00:27:37.271318
8150 00:27:37.271372 ==
8151 00:27:37.274754 Dram Type= 6, Freq= 0, CH_0, rank 1
8152 00:27:37.277727 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8153 00:27:37.277815 ==
8154 00:27:37.277875
8155 00:27:37.277928
8156 00:27:37.281314 TX Vref Scan disable
8157 00:27:37.284662 == TX Byte 0 ==
8158 00:27:37.287749 Update DQ dly =995 (3 ,6, 35) DQ OEN =(3 ,3)
8159 00:27:37.291285 Update DQM dly =995 (3 ,6, 35) DQM OEN =(3 ,3)
8160 00:27:37.294612 == TX Byte 1 ==
8161 00:27:37.297935 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8162 00:27:37.301432 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8163 00:27:37.301549 ==
8164 00:27:37.304861 Dram Type= 6, Freq= 0, CH_0, rank 1
8165 00:27:37.307912 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8166 00:27:37.307999 ==
8167 00:27:37.323247
8168 00:27:37.326529 TX Vref early break, caculate TX vref
8169 00:27:37.329594 TX Vref=16, minBit 8, minWin=22, winSum=387
8170 00:27:37.333043 TX Vref=18, minBit 0, minWin=24, winSum=396
8171 00:27:37.336183 TX Vref=20, minBit 1, minWin=24, winSum=405
8172 00:27:37.339926 TX Vref=22, minBit 8, minWin=24, winSum=409
8173 00:27:37.343087 TX Vref=24, minBit 0, minWin=25, winSum=418
8174 00:27:37.349559 TX Vref=26, minBit 4, minWin=26, winSum=431
8175 00:27:37.352797 TX Vref=28, minBit 0, minWin=26, winSum=434
8176 00:27:37.356267 TX Vref=30, minBit 0, minWin=26, winSum=427
8177 00:27:37.359790 TX Vref=32, minBit 13, minWin=25, winSum=418
8178 00:27:37.362870 TX Vref=34, minBit 0, minWin=25, winSum=411
8179 00:27:37.369651 [TxChooseVref] Worse bit 0, Min win 26, Win sum 434, Final Vref 28
8180 00:27:37.369725
8181 00:27:37.372868 Final TX Range 0 Vref 28
8182 00:27:37.372940
8183 00:27:37.373018 ==
8184 00:27:37.376480 Dram Type= 6, Freq= 0, CH_0, rank 1
8185 00:27:37.379818 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8186 00:27:37.379891 ==
8187 00:27:37.379951
8188 00:27:37.380006
8189 00:27:37.383180 TX Vref Scan disable
8190 00:27:37.389667 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8191 00:27:37.389751 == TX Byte 0 ==
8192 00:27:37.392835 u2DelayCellOfst[0]=13 cells (4 PI)
8193 00:27:37.396351 u2DelayCellOfst[1]=16 cells (5 PI)
8194 00:27:37.399453 u2DelayCellOfst[2]=13 cells (4 PI)
8195 00:27:37.402697 u2DelayCellOfst[3]=13 cells (4 PI)
8196 00:27:37.406306 u2DelayCellOfst[4]=10 cells (3 PI)
8197 00:27:37.409326 u2DelayCellOfst[5]=0 cells (0 PI)
8198 00:27:37.412978 u2DelayCellOfst[6]=16 cells (5 PI)
8199 00:27:37.416054 u2DelayCellOfst[7]=16 cells (5 PI)
8200 00:27:37.419653 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8201 00:27:37.422617 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8202 00:27:37.425917 == TX Byte 1 ==
8203 00:27:37.425994 u2DelayCellOfst[8]=0 cells (0 PI)
8204 00:27:37.429371 u2DelayCellOfst[9]=3 cells (1 PI)
8205 00:27:37.432901 u2DelayCellOfst[10]=6 cells (2 PI)
8206 00:27:37.435936 u2DelayCellOfst[11]=3 cells (1 PI)
8207 00:27:37.439540 u2DelayCellOfst[12]=13 cells (4 PI)
8208 00:27:37.442660 u2DelayCellOfst[13]=10 cells (3 PI)
8209 00:27:37.446081 u2DelayCellOfst[14]=13 cells (4 PI)
8210 00:27:37.449548 u2DelayCellOfst[15]=10 cells (3 PI)
8211 00:27:37.452835 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8212 00:27:37.459458 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8213 00:27:37.459677 DramC Write-DBI on
8214 00:27:37.459754 ==
8215 00:27:37.462437 Dram Type= 6, Freq= 0, CH_0, rank 1
8216 00:27:37.466125 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8217 00:27:37.469101 ==
8218 00:27:37.469233
8219 00:27:37.469395
8220 00:27:37.469489 TX Vref Scan disable
8221 00:27:37.472841 == TX Byte 0 ==
8222 00:27:37.476347 Update DQM dly =738 (2 ,6, 34) DQM OEN =(3 ,3)
8223 00:27:37.479948 == TX Byte 1 ==
8224 00:27:37.482873 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8225 00:27:37.486480 DramC Write-DBI off
8226 00:27:37.486626
8227 00:27:37.486720 [DATLAT]
8228 00:27:37.486806 Freq=1600, CH0 RK1
8229 00:27:37.486890
8230 00:27:37.489554 DATLAT Default: 0xf
8231 00:27:37.489653 0, 0xFFFF, sum = 0
8232 00:27:37.492747 1, 0xFFFF, sum = 0
8233 00:27:37.492866 2, 0xFFFF, sum = 0
8234 00:27:37.496036 3, 0xFFFF, sum = 0
8235 00:27:37.499664 4, 0xFFFF, sum = 0
8236 00:27:37.499761 5, 0xFFFF, sum = 0
8237 00:27:37.502841 6, 0xFFFF, sum = 0
8238 00:27:37.502935 7, 0xFFFF, sum = 0
8239 00:27:37.506082 8, 0xFFFF, sum = 0
8240 00:27:37.506169 9, 0xFFFF, sum = 0
8241 00:27:37.509266 10, 0xFFFF, sum = 0
8242 00:27:37.509366 11, 0xFFFF, sum = 0
8243 00:27:37.512839 12, 0xFFFF, sum = 0
8244 00:27:37.512910 13, 0xFFFF, sum = 0
8245 00:27:37.515917 14, 0x0, sum = 1
8246 00:27:37.516000 15, 0x0, sum = 2
8247 00:27:37.519343 16, 0x0, sum = 3
8248 00:27:37.519452 17, 0x0, sum = 4
8249 00:27:37.522508 best_step = 15
8250 00:27:37.522585
8251 00:27:37.522647 ==
8252 00:27:37.526026 Dram Type= 6, Freq= 0, CH_0, rank 1
8253 00:27:37.529610 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8254 00:27:37.529692 ==
8255 00:27:37.529753 RX Vref Scan: 0
8256 00:27:37.532548
8257 00:27:37.532645 RX Vref 0 -> 0, step: 1
8258 00:27:37.532742
8259 00:27:37.536094 RX Delay 11 -> 252, step: 4
8260 00:27:37.539330 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8261 00:27:37.545989 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8262 00:27:37.549281 iDelay=191, Bit 2, Center 128 (79 ~ 178) 100
8263 00:27:37.552924 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8264 00:27:37.556021 iDelay=191, Bit 4, Center 132 (83 ~ 182) 100
8265 00:27:37.559427 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8266 00:27:37.565850 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8267 00:27:37.569076 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8268 00:27:37.572632 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8269 00:27:37.575772 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8270 00:27:37.579231 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8271 00:27:37.585914 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8272 00:27:37.589170 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8273 00:27:37.592698 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8274 00:27:37.595775 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8275 00:27:37.599296 iDelay=191, Bit 15, Center 128 (75 ~ 182) 108
8276 00:27:37.602446 ==
8277 00:27:37.602541 Dram Type= 6, Freq= 0, CH_0, rank 1
8278 00:27:37.609406 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8279 00:27:37.609507 ==
8280 00:27:37.609576 DQS Delay:
8281 00:27:37.612269 DQS0 = 0, DQS1 = 0
8282 00:27:37.612350 DQM Delay:
8283 00:27:37.615500 DQM0 = 132, DQM1 = 123
8284 00:27:37.615615 DQ Delay:
8285 00:27:37.619026 DQ0 =132, DQ1 =136, DQ2 =128, DQ3 =130
8286 00:27:37.622258 DQ4 =132, DQ5 =124, DQ6 =140, DQ7 =138
8287 00:27:37.625565 DQ8 =116, DQ9 =110, DQ10 =124, DQ11 =120
8288 00:27:37.628727 DQ12 =126, DQ13 =128, DQ14 =132, DQ15 =128
8289 00:27:37.628813
8290 00:27:37.628878
8291 00:27:37.628939
8292 00:27:37.632314 [DramC_TX_OE_Calibration] TA2
8293 00:27:37.635717 Original DQ_B0 (3 6) =30, OEN = 27
8294 00:27:37.638959 Original DQ_B1 (3 6) =30, OEN = 27
8295 00:27:37.642083 24, 0x0, End_B0=24 End_B1=24
8296 00:27:37.645596 25, 0x0, End_B0=25 End_B1=25
8297 00:27:37.645675 26, 0x0, End_B0=26 End_B1=26
8298 00:27:37.648963 27, 0x0, End_B0=27 End_B1=27
8299 00:27:37.652220 28, 0x0, End_B0=28 End_B1=28
8300 00:27:37.655577 29, 0x0, End_B0=29 End_B1=29
8301 00:27:37.658641 30, 0x0, End_B0=30 End_B1=30
8302 00:27:37.658740 31, 0x4545, End_B0=30 End_B1=30
8303 00:27:37.662123 Byte0 end_step=30 best_step=27
8304 00:27:37.665366 Byte1 end_step=30 best_step=27
8305 00:27:37.668553 Byte0 TX OE(2T, 0.5T) = (3, 3)
8306 00:27:37.671948 Byte1 TX OE(2T, 0.5T) = (3, 3)
8307 00:27:37.672026
8308 00:27:37.672113
8309 00:27:37.678711 [DQSOSCAuto] RK1, (LSB)MR18= 0x2311, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 392 ps
8310 00:27:37.682283 CH0 RK1: MR19=303, MR18=2311
8311 00:27:37.688865 CH0_RK1: MR19=0x303, MR18=0x2311, DQSOSC=392, MR23=63, INC=24, DEC=16
8312 00:27:37.691956 [RxdqsGatingPostProcess] freq 1600
8313 00:27:37.698572 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8314 00:27:37.698691 best DQS0 dly(2T, 0.5T) = (1, 1)
8315 00:27:37.702025 best DQS1 dly(2T, 0.5T) = (1, 1)
8316 00:27:37.705605 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8317 00:27:37.708542 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8318 00:27:37.711725 best DQS0 dly(2T, 0.5T) = (1, 1)
8319 00:27:37.715339 best DQS1 dly(2T, 0.5T) = (1, 1)
8320 00:27:37.718861 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8321 00:27:37.721977 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8322 00:27:37.724936 Pre-setting of DQS Precalculation
8323 00:27:37.728440 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8324 00:27:37.728537 ==
8325 00:27:37.731783 Dram Type= 6, Freq= 0, CH_1, rank 0
8326 00:27:37.738392 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8327 00:27:37.738483 ==
8328 00:27:37.741814 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8329 00:27:37.748495 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8330 00:27:37.751745 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8331 00:27:37.758108 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8332 00:27:37.765920 [CA 0] Center 40 (11~70) winsize 60
8333 00:27:37.769491 [CA 1] Center 41 (11~71) winsize 61
8334 00:27:37.772375 [CA 2] Center 37 (8~67) winsize 60
8335 00:27:37.775769 [CA 3] Center 36 (7~66) winsize 60
8336 00:27:37.779297 [CA 4] Center 36 (7~66) winsize 60
8337 00:27:37.782379 [CA 5] Center 36 (6~66) winsize 61
8338 00:27:37.782455
8339 00:27:37.785864 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8340 00:27:37.785940
8341 00:27:37.789480 [CATrainingPosCal] consider 1 rank data
8342 00:27:37.792554 u2DelayCellTimex100 = 290/100 ps
8343 00:27:37.796186 CA0 delay=40 (11~70),Diff = 4 PI (13 cell)
8344 00:27:37.802756 CA1 delay=41 (11~71),Diff = 5 PI (16 cell)
8345 00:27:37.805811 CA2 delay=37 (8~67),Diff = 1 PI (3 cell)
8346 00:27:37.809335 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8347 00:27:37.812357 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
8348 00:27:37.815783 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
8349 00:27:37.815859
8350 00:27:37.819385 CA PerBit enable=1, Macro0, CA PI delay=36
8351 00:27:37.819486
8352 00:27:37.822532 [CBTSetCACLKResult] CA Dly = 36
8353 00:27:37.822608 CS Dly: 9 (0~40)
8354 00:27:37.829003 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8355 00:27:37.832556 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8356 00:27:37.832633 ==
8357 00:27:37.836048 Dram Type= 6, Freq= 0, CH_1, rank 1
8358 00:27:37.839256 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8359 00:27:37.839333 ==
8360 00:27:37.846001 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8361 00:27:37.849169 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8362 00:27:37.855802 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8363 00:27:37.859361 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8364 00:27:37.868802 [CA 0] Center 42 (13~71) winsize 59
8365 00:27:37.872352 [CA 1] Center 42 (13~71) winsize 59
8366 00:27:37.875753 [CA 2] Center 37 (8~67) winsize 60
8367 00:27:37.878822 [CA 3] Center 37 (8~67) winsize 60
8368 00:27:37.882176 [CA 4] Center 37 (8~67) winsize 60
8369 00:27:37.885616 [CA 5] Center 37 (7~67) winsize 61
8370 00:27:37.885691
8371 00:27:37.888961 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8372 00:27:37.889037
8373 00:27:37.892112 [CATrainingPosCal] consider 2 rank data
8374 00:27:37.895528 u2DelayCellTimex100 = 290/100 ps
8375 00:27:37.898729 CA0 delay=41 (13~70),Diff = 5 PI (16 cell)
8376 00:27:37.905609 CA1 delay=42 (13~71),Diff = 6 PI (20 cell)
8377 00:27:37.909207 CA2 delay=37 (8~67),Diff = 1 PI (3 cell)
8378 00:27:37.912640 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8379 00:27:37.915682 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8380 00:27:37.918816 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8381 00:27:37.918891
8382 00:27:37.922522 CA PerBit enable=1, Macro0, CA PI delay=36
8383 00:27:37.922597
8384 00:27:37.925915 [CBTSetCACLKResult] CA Dly = 36
8385 00:27:37.925991 CS Dly: 10 (0~42)
8386 00:27:37.932733 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8387 00:27:37.935844 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8388 00:27:37.935919
8389 00:27:37.938907 ----->DramcWriteLeveling(PI) begin...
8390 00:27:37.938984 ==
8391 00:27:37.942416 Dram Type= 6, Freq= 0, CH_1, rank 0
8392 00:27:37.945572 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8393 00:27:37.945648 ==
8394 00:27:37.949080 Write leveling (Byte 0): 23 => 23
8395 00:27:37.952542 Write leveling (Byte 1): 28 => 28
8396 00:27:37.955805 DramcWriteLeveling(PI) end<-----
8397 00:27:37.955880
8398 00:27:37.955938 ==
8399 00:27:37.958733 Dram Type= 6, Freq= 0, CH_1, rank 0
8400 00:27:37.965920 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8401 00:27:37.965996 ==
8402 00:27:37.966054 [Gating] SW mode calibration
8403 00:27:37.975518 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8404 00:27:37.979301 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8405 00:27:37.982371 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8406 00:27:37.988928 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8407 00:27:37.992339 1 4 8 | B1->B0 | 2828 2d2d | 0 0 | (0 0) (0 0)
8408 00:27:37.995687 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8409 00:27:38.002262 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8410 00:27:38.005797 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8411 00:27:38.008780 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8412 00:27:38.015291 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8413 00:27:38.018987 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8414 00:27:38.021931 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8415 00:27:38.028970 1 5 8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (1 0)
8416 00:27:38.032095 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8417 00:27:38.035212 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8418 00:27:38.041851 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8419 00:27:38.045430 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8420 00:27:38.048412 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8421 00:27:38.055295 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8422 00:27:38.058683 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8423 00:27:38.062087 1 6 8 | B1->B0 | 3535 3e3e | 0 0 | (0 0) (0 0)
8424 00:27:38.068550 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8425 00:27:38.072143 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8426 00:27:38.075215 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8427 00:27:38.081854 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8428 00:27:38.085202 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8429 00:27:38.088669 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8430 00:27:38.095340 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8431 00:27:38.098681 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8432 00:27:38.102061 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8433 00:27:38.105261 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8434 00:27:38.111768 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8435 00:27:38.115209 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8436 00:27:38.118271 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8437 00:27:38.125368 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8438 00:27:38.128491 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8439 00:27:38.132033 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8440 00:27:38.138487 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8441 00:27:38.141937 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8442 00:27:38.145018 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8443 00:27:38.151604 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8444 00:27:38.154903 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8445 00:27:38.158603 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8446 00:27:38.165132 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8447 00:27:38.168343 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8448 00:27:38.171713 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8449 00:27:38.175135 Total UI for P1: 0, mck2ui 16
8450 00:27:38.178208 best dqsien dly found for B0: ( 1, 9, 6)
8451 00:27:38.185197 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8452 00:27:38.185276 Total UI for P1: 0, mck2ui 16
8453 00:27:38.191842 best dqsien dly found for B1: ( 1, 9, 10)
8454 00:27:38.194806 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8455 00:27:38.198095 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8456 00:27:38.198171
8457 00:27:38.201563 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8458 00:27:38.205037 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8459 00:27:38.208040 [Gating] SW calibration Done
8460 00:27:38.208116 ==
8461 00:27:38.211552 Dram Type= 6, Freq= 0, CH_1, rank 0
8462 00:27:38.214868 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8463 00:27:38.214944 ==
8464 00:27:38.218079 RX Vref Scan: 0
8465 00:27:38.218155
8466 00:27:38.218214 RX Vref 0 -> 0, step: 1
8467 00:27:38.218269
8468 00:27:38.221583 RX Delay 0 -> 252, step: 8
8469 00:27:38.224961 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8470 00:27:38.228227 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8471 00:27:38.234816 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8472 00:27:38.238413 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8473 00:27:38.241567 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8474 00:27:38.244706 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8475 00:27:38.248404 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8476 00:27:38.255144 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8477 00:27:38.258168 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8478 00:27:38.261599 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8479 00:27:38.264728 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8480 00:27:38.268087 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8481 00:27:38.275058 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8482 00:27:38.278395 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8483 00:27:38.281607 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8484 00:27:38.285316 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8485 00:27:38.285457 ==
8486 00:27:38.288327 Dram Type= 6, Freq= 0, CH_1, rank 0
8487 00:27:38.291586 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8488 00:27:38.295214 ==
8489 00:27:38.295398 DQS Delay:
8490 00:27:38.295542 DQS0 = 0, DQS1 = 0
8491 00:27:38.298297 DQM Delay:
8492 00:27:38.298519 DQM0 = 137, DQM1 = 130
8493 00:27:38.301770 DQ Delay:
8494 00:27:38.305230 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =139
8495 00:27:38.308440 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8496 00:27:38.311850 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8497 00:27:38.315148 DQ12 =139, DQ13 =135, DQ14 =139, DQ15 =135
8498 00:27:38.315538
8499 00:27:38.315842
8500 00:27:38.316121 ==
8501 00:27:38.318583 Dram Type= 6, Freq= 0, CH_1, rank 0
8502 00:27:38.321836 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8503 00:27:38.321918 ==
8504 00:27:38.324629
8505 00:27:38.324737
8506 00:27:38.324803 TX Vref Scan disable
8507 00:27:38.327987 == TX Byte 0 ==
8508 00:27:38.331604 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8509 00:27:38.334661 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8510 00:27:38.338136 == TX Byte 1 ==
8511 00:27:38.341535 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8512 00:27:38.344682 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8513 00:27:38.344812 ==
8514 00:27:38.348386 Dram Type= 6, Freq= 0, CH_1, rank 0
8515 00:27:38.354888 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8516 00:27:38.355033 ==
8517 00:27:38.366713
8518 00:27:38.369610 TX Vref early break, caculate TX vref
8519 00:27:38.373321 TX Vref=16, minBit 10, minWin=21, winSum=370
8520 00:27:38.376741 TX Vref=18, minBit 10, minWin=22, winSum=379
8521 00:27:38.380110 TX Vref=20, minBit 10, minWin=22, winSum=384
8522 00:27:38.383816 TX Vref=22, minBit 10, minWin=23, winSum=394
8523 00:27:38.389864 TX Vref=24, minBit 10, minWin=23, winSum=405
8524 00:27:38.393528 TX Vref=26, minBit 10, minWin=24, winSum=414
8525 00:27:38.396686 TX Vref=28, minBit 12, minWin=25, winSum=421
8526 00:27:38.400124 TX Vref=30, minBit 10, minWin=25, winSum=419
8527 00:27:38.403262 TX Vref=32, minBit 11, minWin=23, winSum=402
8528 00:27:38.406948 TX Vref=34, minBit 11, minWin=23, winSum=395
8529 00:27:38.413172 [TxChooseVref] Worse bit 12, Min win 25, Win sum 421, Final Vref 28
8530 00:27:38.413565
8531 00:27:38.416998 Final TX Range 0 Vref 28
8532 00:27:38.417419
8533 00:27:38.417733 ==
8534 00:27:38.420063 Dram Type= 6, Freq= 0, CH_1, rank 0
8535 00:27:38.423638 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8536 00:27:38.424036 ==
8537 00:27:38.424346
8538 00:27:38.426687
8539 00:27:38.427073 TX Vref Scan disable
8540 00:27:38.433287 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8541 00:27:38.433681 == TX Byte 0 ==
8542 00:27:38.436400 u2DelayCellOfst[0]=16 cells (5 PI)
8543 00:27:38.439405 u2DelayCellOfst[1]=10 cells (3 PI)
8544 00:27:38.442709 u2DelayCellOfst[2]=0 cells (0 PI)
8545 00:27:38.446210 u2DelayCellOfst[3]=3 cells (1 PI)
8546 00:27:38.450059 u2DelayCellOfst[4]=6 cells (2 PI)
8547 00:27:38.452947 u2DelayCellOfst[5]=16 cells (5 PI)
8548 00:27:38.456598 u2DelayCellOfst[6]=16 cells (5 PI)
8549 00:27:38.459603 u2DelayCellOfst[7]=3 cells (1 PI)
8550 00:27:38.462903 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8551 00:27:38.466050 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8552 00:27:38.469566 == TX Byte 1 ==
8553 00:27:38.472911 u2DelayCellOfst[8]=0 cells (0 PI)
8554 00:27:38.472987 u2DelayCellOfst[9]=3 cells (1 PI)
8555 00:27:38.475969 u2DelayCellOfst[10]=10 cells (3 PI)
8556 00:27:38.479614 u2DelayCellOfst[11]=3 cells (1 PI)
8557 00:27:38.482863 u2DelayCellOfst[12]=16 cells (5 PI)
8558 00:27:38.486084 u2DelayCellOfst[13]=16 cells (5 PI)
8559 00:27:38.489607 u2DelayCellOfst[14]=20 cells (6 PI)
8560 00:27:38.492540 u2DelayCellOfst[15]=16 cells (5 PI)
8561 00:27:38.499465 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8562 00:27:38.502529 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8563 00:27:38.502609 DramC Write-DBI on
8564 00:27:38.502670 ==
8565 00:27:38.505896 Dram Type= 6, Freq= 0, CH_1, rank 0
8566 00:27:38.512638 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8567 00:27:38.512726 ==
8568 00:27:38.512813
8569 00:27:38.512870
8570 00:27:38.512924 TX Vref Scan disable
8571 00:27:38.516666 == TX Byte 0 ==
8572 00:27:38.520002 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8573 00:27:38.522834 == TX Byte 1 ==
8574 00:27:38.526320 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8575 00:27:38.530048 DramC Write-DBI off
8576 00:27:38.530135
8577 00:27:38.530199 [DATLAT]
8578 00:27:38.530259 Freq=1600, CH1 RK0
8579 00:27:38.530317
8580 00:27:38.533144 DATLAT Default: 0xf
8581 00:27:38.533235 0, 0xFFFF, sum = 0
8582 00:27:38.536147 1, 0xFFFF, sum = 0
8583 00:27:38.539549 2, 0xFFFF, sum = 0
8584 00:27:38.539648 3, 0xFFFF, sum = 0
8585 00:27:38.543081 4, 0xFFFF, sum = 0
8586 00:27:38.543190 5, 0xFFFF, sum = 0
8587 00:27:38.546644 6, 0xFFFF, sum = 0
8588 00:27:38.546764 7, 0xFFFF, sum = 0
8589 00:27:38.549773 8, 0xFFFF, sum = 0
8590 00:27:38.549890 9, 0xFFFF, sum = 0
8591 00:27:38.553252 10, 0xFFFF, sum = 0
8592 00:27:38.553383 11, 0xFFFF, sum = 0
8593 00:27:38.556736 12, 0xFFFF, sum = 0
8594 00:27:38.556883 13, 0xFFFF, sum = 0
8595 00:27:38.559777 14, 0x0, sum = 1
8596 00:27:38.559923 15, 0x0, sum = 2
8597 00:27:38.563477 16, 0x0, sum = 3
8598 00:27:38.563653 17, 0x0, sum = 4
8599 00:27:38.566715 best_step = 15
8600 00:27:38.566916
8601 00:27:38.567070 ==
8602 00:27:38.569769 Dram Type= 6, Freq= 0, CH_1, rank 0
8603 00:27:38.573521 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8604 00:27:38.573717 ==
8605 00:27:38.573930 RX Vref Scan: 1
8606 00:27:38.576925
8607 00:27:38.577265 Set Vref Range= 24 -> 127
8608 00:27:38.577582
8609 00:27:38.579939 RX Vref 24 -> 127, step: 1
8610 00:27:38.580263
8611 00:27:38.583579 RX Delay 19 -> 252, step: 4
8612 00:27:38.583876
8613 00:27:38.586763 Set Vref, RX VrefLevel [Byte0]: 24
8614 00:27:38.590091 [Byte1]: 24
8615 00:27:38.590483
8616 00:27:38.593274 Set Vref, RX VrefLevel [Byte0]: 25
8617 00:27:38.596837 [Byte1]: 25
8618 00:27:38.597347
8619 00:27:38.599960 Set Vref, RX VrefLevel [Byte0]: 26
8620 00:27:38.603527 [Byte1]: 26
8621 00:27:38.607440
8622 00:27:38.607972 Set Vref, RX VrefLevel [Byte0]: 27
8623 00:27:38.610616 [Byte1]: 27
8624 00:27:38.614370
8625 00:27:38.614446 Set Vref, RX VrefLevel [Byte0]: 28
8626 00:27:38.617918 [Byte1]: 28
8627 00:27:38.622108
8628 00:27:38.622188 Set Vref, RX VrefLevel [Byte0]: 29
8629 00:27:38.625346 [Byte1]: 29
8630 00:27:38.629584
8631 00:27:38.629659 Set Vref, RX VrefLevel [Byte0]: 30
8632 00:27:38.633210 [Byte1]: 30
8633 00:27:38.637100
8634 00:27:38.637175 Set Vref, RX VrefLevel [Byte0]: 31
8635 00:27:38.640314 [Byte1]: 31
8636 00:27:38.644983
8637 00:27:38.645058 Set Vref, RX VrefLevel [Byte0]: 32
8638 00:27:38.647950 [Byte1]: 32
8639 00:27:38.652375
8640 00:27:38.652451 Set Vref, RX VrefLevel [Byte0]: 33
8641 00:27:38.655464 [Byte1]: 33
8642 00:27:38.659982
8643 00:27:38.660057 Set Vref, RX VrefLevel [Byte0]: 34
8644 00:27:38.662894 [Byte1]: 34
8645 00:27:38.667550
8646 00:27:38.667626 Set Vref, RX VrefLevel [Byte0]: 35
8647 00:27:38.671058 [Byte1]: 35
8648 00:27:38.675148
8649 00:27:38.675224 Set Vref, RX VrefLevel [Byte0]: 36
8650 00:27:38.678172 [Byte1]: 36
8651 00:27:38.682560
8652 00:27:38.682637 Set Vref, RX VrefLevel [Byte0]: 37
8653 00:27:38.685847 [Byte1]: 37
8654 00:27:38.690312
8655 00:27:38.690389 Set Vref, RX VrefLevel [Byte0]: 38
8656 00:27:38.693413 [Byte1]: 38
8657 00:27:38.697646
8658 00:27:38.697738 Set Vref, RX VrefLevel [Byte0]: 39
8659 00:27:38.701075 [Byte1]: 39
8660 00:27:38.705603
8661 00:27:38.705681 Set Vref, RX VrefLevel [Byte0]: 40
8662 00:27:38.708593 [Byte1]: 40
8663 00:27:38.712656
8664 00:27:38.712784 Set Vref, RX VrefLevel [Byte0]: 41
8665 00:27:38.716184 [Byte1]: 41
8666 00:27:38.720341
8667 00:27:38.720418 Set Vref, RX VrefLevel [Byte0]: 42
8668 00:27:38.723809 [Byte1]: 42
8669 00:27:38.727764
8670 00:27:38.727841 Set Vref, RX VrefLevel [Byte0]: 43
8671 00:27:38.731255 [Byte1]: 43
8672 00:27:38.735655
8673 00:27:38.735733 Set Vref, RX VrefLevel [Byte0]: 44
8674 00:27:38.739213 [Byte1]: 44
8675 00:27:38.743277
8676 00:27:38.743355 Set Vref, RX VrefLevel [Byte0]: 45
8677 00:27:38.746327 [Byte1]: 45
8678 00:27:38.750588
8679 00:27:38.750665 Set Vref, RX VrefLevel [Byte0]: 46
8680 00:27:38.753899 [Byte1]: 46
8681 00:27:38.758086
8682 00:27:38.758163 Set Vref, RX VrefLevel [Byte0]: 47
8683 00:27:38.761561 [Byte1]: 47
8684 00:27:38.765714
8685 00:27:38.765791 Set Vref, RX VrefLevel [Byte0]: 48
8686 00:27:38.769258 [Byte1]: 48
8687 00:27:38.773732
8688 00:27:38.773811 Set Vref, RX VrefLevel [Byte0]: 49
8689 00:27:38.776512 [Byte1]: 49
8690 00:27:38.781043
8691 00:27:38.781123 Set Vref, RX VrefLevel [Byte0]: 50
8692 00:27:38.784047 [Byte1]: 50
8693 00:27:38.788560
8694 00:27:38.788662 Set Vref, RX VrefLevel [Byte0]: 51
8695 00:27:38.791764 [Byte1]: 51
8696 00:27:38.796405
8697 00:27:38.796481 Set Vref, RX VrefLevel [Byte0]: 52
8698 00:27:38.799408 [Byte1]: 52
8699 00:27:38.803605
8700 00:27:38.803706 Set Vref, RX VrefLevel [Byte0]: 53
8701 00:27:38.806831 [Byte1]: 53
8702 00:27:38.811382
8703 00:27:38.811459 Set Vref, RX VrefLevel [Byte0]: 54
8704 00:27:38.814787 [Byte1]: 54
8705 00:27:38.818842
8706 00:27:38.818918 Set Vref, RX VrefLevel [Byte0]: 55
8707 00:27:38.822016 [Byte1]: 55
8708 00:27:38.826579
8709 00:27:38.826656 Set Vref, RX VrefLevel [Byte0]: 56
8710 00:27:38.829643 [Byte1]: 56
8711 00:27:38.833710
8712 00:27:38.833786 Set Vref, RX VrefLevel [Byte0]: 57
8713 00:27:38.837223 [Byte1]: 57
8714 00:27:38.841776
8715 00:27:38.841852 Set Vref, RX VrefLevel [Byte0]: 58
8716 00:27:38.844774 [Byte1]: 58
8717 00:27:38.849236
8718 00:27:38.849312 Set Vref, RX VrefLevel [Byte0]: 59
8719 00:27:38.852331 [Byte1]: 59
8720 00:27:38.856582
8721 00:27:38.856679 Set Vref, RX VrefLevel [Byte0]: 60
8722 00:27:38.859888 [Byte1]: 60
8723 00:27:38.864548
8724 00:27:38.864615 Set Vref, RX VrefLevel [Byte0]: 61
8725 00:27:38.867446 [Byte1]: 61
8726 00:27:38.871603
8727 00:27:38.871668 Set Vref, RX VrefLevel [Byte0]: 62
8728 00:27:38.875104 [Byte1]: 62
8729 00:27:38.879285
8730 00:27:38.879396 Set Vref, RX VrefLevel [Byte0]: 63
8731 00:27:38.883016 [Byte1]: 63
8732 00:27:38.887082
8733 00:27:38.887153 Set Vref, RX VrefLevel [Byte0]: 64
8734 00:27:38.890339 [Byte1]: 64
8735 00:27:38.894820
8736 00:27:38.894891 Set Vref, RX VrefLevel [Byte0]: 65
8737 00:27:38.897890 [Byte1]: 65
8738 00:27:38.902182
8739 00:27:38.902253 Set Vref, RX VrefLevel [Byte0]: 66
8740 00:27:38.905507 [Byte1]: 66
8741 00:27:38.909718
8742 00:27:38.909797 Set Vref, RX VrefLevel [Byte0]: 67
8743 00:27:38.913035 [Byte1]: 67
8744 00:27:38.917240
8745 00:27:38.917309 Set Vref, RX VrefLevel [Byte0]: 68
8746 00:27:38.920293 [Byte1]: 68
8747 00:27:38.925113
8748 00:27:38.925190 Set Vref, RX VrefLevel [Byte0]: 69
8749 00:27:38.928022 [Byte1]: 69
8750 00:27:38.932177
8751 00:27:38.932254 Set Vref, RX VrefLevel [Byte0]: 70
8752 00:27:38.935859 [Byte1]: 70
8753 00:27:38.939887
8754 00:27:38.939966 Set Vref, RX VrefLevel [Byte0]: 71
8755 00:27:38.943243 [Byte1]: 71
8756 00:27:38.947664
8757 00:27:38.947741 Set Vref, RX VrefLevel [Byte0]: 72
8758 00:27:38.950662 [Byte1]: 72
8759 00:27:38.955273
8760 00:27:38.955350 Set Vref, RX VrefLevel [Byte0]: 73
8761 00:27:38.958239 [Byte1]: 73
8762 00:27:38.962666
8763 00:27:38.962742 Set Vref, RX VrefLevel [Byte0]: 74
8764 00:27:38.965820 [Byte1]: 74
8765 00:27:38.969948
8766 00:27:38.973491 Final RX Vref Byte 0 = 59 to rank0
8767 00:27:38.973598 Final RX Vref Byte 1 = 63 to rank0
8768 00:27:38.977018 Final RX Vref Byte 0 = 59 to rank1
8769 00:27:38.980065 Final RX Vref Byte 1 = 63 to rank1==
8770 00:27:38.983663 Dram Type= 6, Freq= 0, CH_1, rank 0
8771 00:27:38.990324 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8772 00:27:38.990407 ==
8773 00:27:38.990474 DQS Delay:
8774 00:27:38.993691 DQS0 = 0, DQS1 = 0
8775 00:27:38.993771 DQM Delay:
8776 00:27:38.993829 DQM0 = 134, DQM1 = 129
8777 00:27:38.996628 DQ Delay:
8778 00:27:38.999867 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =132
8779 00:27:39.003436 DQ4 =132, DQ5 =144, DQ6 =146, DQ7 =132
8780 00:27:39.006646 DQ8 =116, DQ9 =120, DQ10 =134, DQ11 =122
8781 00:27:39.009670 DQ12 =140, DQ13 =134, DQ14 =136, DQ15 =136
8782 00:27:39.009749
8783 00:27:39.009809
8784 00:27:39.009864
8785 00:27:39.013283 [DramC_TX_OE_Calibration] TA2
8786 00:27:39.016658 Original DQ_B0 (3 6) =30, OEN = 27
8787 00:27:39.020264 Original DQ_B1 (3 6) =30, OEN = 27
8788 00:27:39.023399 24, 0x0, End_B0=24 End_B1=24
8789 00:27:39.023472 25, 0x0, End_B0=25 End_B1=25
8790 00:27:39.026680 26, 0x0, End_B0=26 End_B1=26
8791 00:27:39.029801 27, 0x0, End_B0=27 End_B1=27
8792 00:27:39.033648 28, 0x0, End_B0=28 End_B1=28
8793 00:27:39.036558 29, 0x0, End_B0=29 End_B1=29
8794 00:27:39.036655 30, 0x0, End_B0=30 End_B1=30
8795 00:27:39.040224 31, 0x5151, End_B0=30 End_B1=30
8796 00:27:39.043290 Byte0 end_step=30 best_step=27
8797 00:27:39.046457 Byte1 end_step=30 best_step=27
8798 00:27:39.049830 Byte0 TX OE(2T, 0.5T) = (3, 3)
8799 00:27:39.053267 Byte1 TX OE(2T, 0.5T) = (3, 3)
8800 00:27:39.053342
8801 00:27:39.053402
8802 00:27:39.059987 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a28, (MSB)MR19= 0x303, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
8803 00:27:39.063550 CH1 RK0: MR19=303, MR18=1A28
8804 00:27:39.070006 CH1_RK0: MR19=0x303, MR18=0x1A28, DQSOSC=389, MR23=63, INC=24, DEC=16
8805 00:27:39.070081
8806 00:27:39.073476 ----->DramcWriteLeveling(PI) begin...
8807 00:27:39.073555 ==
8808 00:27:39.076672 Dram Type= 6, Freq= 0, CH_1, rank 1
8809 00:27:39.079699 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8810 00:27:39.079825 ==
8811 00:27:39.083512 Write leveling (Byte 0): 26 => 26
8812 00:27:39.086561 Write leveling (Byte 1): 28 => 28
8813 00:27:39.090206 DramcWriteLeveling(PI) end<-----
8814 00:27:39.090271
8815 00:27:39.090332 ==
8816 00:27:39.093253 Dram Type= 6, Freq= 0, CH_1, rank 1
8817 00:27:39.096835 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8818 00:27:39.096897 ==
8819 00:27:39.099879 [Gating] SW mode calibration
8820 00:27:39.106613 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8821 00:27:39.112972 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8822 00:27:39.116346 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8823 00:27:39.119869 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8824 00:27:39.126578 1 4 8 | B1->B0 | 3131 2323 | 1 0 | (1 1) (0 0)
8825 00:27:39.129607 1 4 12 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (0 0)
8826 00:27:39.132893 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8827 00:27:39.139283 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8828 00:27:39.142997 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8829 00:27:39.146125 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8830 00:27:39.152942 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8831 00:27:39.156394 1 5 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8832 00:27:39.159451 1 5 8 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 0)
8833 00:27:39.166396 1 5 12 | B1->B0 | 2323 3333 | 0 0 | (1 0) (0 1)
8834 00:27:39.169775 1 5 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8835 00:27:39.173008 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8836 00:27:39.179696 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8837 00:27:39.182715 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8838 00:27:39.186300 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8839 00:27:39.192965 1 6 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8840 00:27:39.196112 1 6 8 | B1->B0 | 4343 2525 | 0 0 | (1 1) (0 0)
8841 00:27:39.199694 1 6 12 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
8842 00:27:39.206288 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8843 00:27:39.209626 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8844 00:27:39.212688 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8845 00:27:39.216251 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8846 00:27:39.222778 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8847 00:27:39.226319 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8848 00:27:39.229537 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8849 00:27:39.236190 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8850 00:27:39.239400 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8851 00:27:39.242769 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8852 00:27:39.249382 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8853 00:27:39.252656 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8854 00:27:39.256266 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8855 00:27:39.262833 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8856 00:27:39.266305 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8857 00:27:39.269375 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8858 00:27:39.276352 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8859 00:27:39.279228 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8860 00:27:39.282775 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8861 00:27:39.289451 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8862 00:27:39.292538 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8863 00:27:39.296266 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8864 00:27:39.302558 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8865 00:27:39.305935 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8866 00:27:39.309481 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8867 00:27:39.312690 Total UI for P1: 0, mck2ui 16
8868 00:27:39.316044 best dqsien dly found for B0: ( 1, 9, 10)
8869 00:27:39.319199 Total UI for P1: 0, mck2ui 16
8870 00:27:39.322843 best dqsien dly found for B1: ( 1, 9, 10)
8871 00:27:39.326107 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8872 00:27:39.329215 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8873 00:27:39.329276
8874 00:27:39.332795 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8875 00:27:39.339379 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8876 00:27:39.339444 [Gating] SW calibration Done
8877 00:27:39.342537 ==
8878 00:27:39.342598 Dram Type= 6, Freq= 0, CH_1, rank 1
8879 00:27:39.349468 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8880 00:27:39.349533 ==
8881 00:27:39.349591 RX Vref Scan: 0
8882 00:27:39.349644
8883 00:27:39.352536 RX Vref 0 -> 0, step: 1
8884 00:27:39.352597
8885 00:27:39.355699 RX Delay 0 -> 252, step: 8
8886 00:27:39.359161 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8887 00:27:39.362552 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8888 00:27:39.365538 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8889 00:27:39.372195 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8890 00:27:39.375495 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8891 00:27:39.378938 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8892 00:27:39.382197 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8893 00:27:39.385698 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8894 00:27:39.392352 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8895 00:27:39.395770 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8896 00:27:39.398947 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8897 00:27:39.402581 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8898 00:27:39.405506 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8899 00:27:39.412224 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8900 00:27:39.415771 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8901 00:27:39.418887 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8902 00:27:39.418950 ==
8903 00:27:39.422291 Dram Type= 6, Freq= 0, CH_1, rank 1
8904 00:27:39.425807 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8905 00:27:39.425871 ==
8906 00:27:39.429021 DQS Delay:
8907 00:27:39.429086 DQS0 = 0, DQS1 = 0
8908 00:27:39.432154 DQM Delay:
8909 00:27:39.432215 DQM0 = 135, DQM1 = 132
8910 00:27:39.432268 DQ Delay:
8911 00:27:39.435685 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8912 00:27:39.442347 DQ4 =135, DQ5 =147, DQ6 =139, DQ7 =135
8913 00:27:39.445468 DQ8 =115, DQ9 =119, DQ10 =135, DQ11 =127
8914 00:27:39.448663 DQ12 =143, DQ13 =139, DQ14 =139, DQ15 =143
8915 00:27:39.448747
8916 00:27:39.448802
8917 00:27:39.448857 ==
8918 00:27:39.452008 Dram Type= 6, Freq= 0, CH_1, rank 1
8919 00:27:39.455469 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8920 00:27:39.455533 ==
8921 00:27:39.455585
8922 00:27:39.455636
8923 00:27:39.459115 TX Vref Scan disable
8924 00:27:39.462148 == TX Byte 0 ==
8925 00:27:39.465575 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8926 00:27:39.468777 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8927 00:27:39.472032 == TX Byte 1 ==
8928 00:27:39.475669 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8929 00:27:39.478626 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8930 00:27:39.478689 ==
8931 00:27:39.482164 Dram Type= 6, Freq= 0, CH_1, rank 1
8932 00:27:39.485610 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8933 00:27:39.488489 ==
8934 00:27:39.500916
8935 00:27:39.503894 TX Vref early break, caculate TX vref
8936 00:27:39.507454 TX Vref=16, minBit 9, minWin=22, winSum=381
8937 00:27:39.510655 TX Vref=18, minBit 12, minWin=22, winSum=390
8938 00:27:39.514240 TX Vref=20, minBit 13, minWin=23, winSum=396
8939 00:27:39.517280 TX Vref=22, minBit 8, minWin=24, winSum=406
8940 00:27:39.521014 TX Vref=24, minBit 9, minWin=24, winSum=411
8941 00:27:39.527196 TX Vref=26, minBit 9, minWin=24, winSum=417
8942 00:27:39.530761 TX Vref=28, minBit 8, minWin=25, winSum=419
8943 00:27:39.534236 TX Vref=30, minBit 10, minWin=24, winSum=416
8944 00:27:39.537291 TX Vref=32, minBit 10, minWin=24, winSum=408
8945 00:27:39.540642 TX Vref=34, minBit 9, minWin=24, winSum=402
8946 00:27:39.544191 TX Vref=36, minBit 8, minWin=22, winSum=392
8947 00:27:39.550769 [TxChooseVref] Worse bit 8, Min win 25, Win sum 419, Final Vref 28
8948 00:27:39.550835
8949 00:27:39.554422 Final TX Range 0 Vref 28
8950 00:27:39.554505
8951 00:27:39.554560 ==
8952 00:27:39.557499 Dram Type= 6, Freq= 0, CH_1, rank 1
8953 00:27:39.560874 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8954 00:27:39.560941 ==
8955 00:27:39.560995
8956 00:27:39.563737
8957 00:27:39.563798 TX Vref Scan disable
8958 00:27:39.570856 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8959 00:27:39.570930 == TX Byte 0 ==
8960 00:27:39.573933 u2DelayCellOfst[0]=16 cells (5 PI)
8961 00:27:39.577309 u2DelayCellOfst[1]=13 cells (4 PI)
8962 00:27:39.580503 u2DelayCellOfst[2]=0 cells (0 PI)
8963 00:27:39.583852 u2DelayCellOfst[3]=6 cells (2 PI)
8964 00:27:39.587074 u2DelayCellOfst[4]=10 cells (3 PI)
8965 00:27:39.590548 u2DelayCellOfst[5]=20 cells (6 PI)
8966 00:27:39.594097 u2DelayCellOfst[6]=20 cells (6 PI)
8967 00:27:39.597473 u2DelayCellOfst[7]=6 cells (2 PI)
8968 00:27:39.600525 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8969 00:27:39.604102 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8970 00:27:39.607336 == TX Byte 1 ==
8971 00:27:39.610406 u2DelayCellOfst[8]=0 cells (0 PI)
8972 00:27:39.614139 u2DelayCellOfst[9]=3 cells (1 PI)
8973 00:27:39.614216 u2DelayCellOfst[10]=10 cells (3 PI)
8974 00:27:39.617126 u2DelayCellOfst[11]=6 cells (2 PI)
8975 00:27:39.620868 u2DelayCellOfst[12]=13 cells (4 PI)
8976 00:27:39.623781 u2DelayCellOfst[13]=16 cells (5 PI)
8977 00:27:39.627331 u2DelayCellOfst[14]=20 cells (6 PI)
8978 00:27:39.630716 u2DelayCellOfst[15]=20 cells (6 PI)
8979 00:27:39.633843 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8980 00:27:39.640684 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8981 00:27:39.640803 DramC Write-DBI on
8982 00:27:39.640866 ==
8983 00:27:39.643959 Dram Type= 6, Freq= 0, CH_1, rank 1
8984 00:27:39.650702 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8985 00:27:39.650775 ==
8986 00:27:39.650834
8987 00:27:39.650893
8988 00:27:39.650946 TX Vref Scan disable
8989 00:27:39.654126 == TX Byte 0 ==
8990 00:27:39.657743 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8991 00:27:39.660733 == TX Byte 1 ==
8992 00:27:39.664480 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8993 00:27:39.667547 DramC Write-DBI off
8994 00:27:39.667614
8995 00:27:39.667671 [DATLAT]
8996 00:27:39.667724 Freq=1600, CH1 RK1
8997 00:27:39.667776
8998 00:27:39.671024 DATLAT Default: 0xf
8999 00:27:39.671088 0, 0xFFFF, sum = 0
9000 00:27:39.674288 1, 0xFFFF, sum = 0
9001 00:27:39.677296 2, 0xFFFF, sum = 0
9002 00:27:39.677367 3, 0xFFFF, sum = 0
9003 00:27:39.680839 4, 0xFFFF, sum = 0
9004 00:27:39.680934 5, 0xFFFF, sum = 0
9005 00:27:39.684211 6, 0xFFFF, sum = 0
9006 00:27:39.684278 7, 0xFFFF, sum = 0
9007 00:27:39.687736 8, 0xFFFF, sum = 0
9008 00:27:39.687803 9, 0xFFFF, sum = 0
9009 00:27:39.690773 10, 0xFFFF, sum = 0
9010 00:27:39.690843 11, 0xFFFF, sum = 0
9011 00:27:39.694285 12, 0xFFFF, sum = 0
9012 00:27:39.694358 13, 0xFFFF, sum = 0
9013 00:27:39.697324 14, 0x0, sum = 1
9014 00:27:39.697390 15, 0x0, sum = 2
9015 00:27:39.700996 16, 0x0, sum = 3
9016 00:27:39.701059 17, 0x0, sum = 4
9017 00:27:39.704054 best_step = 15
9018 00:27:39.704120
9019 00:27:39.704174 ==
9020 00:27:39.707771 Dram Type= 6, Freq= 0, CH_1, rank 1
9021 00:27:39.710699 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9022 00:27:39.710761 ==
9023 00:27:39.714340 RX Vref Scan: 0
9024 00:27:39.714402
9025 00:27:39.714457 RX Vref 0 -> 0, step: 1
9026 00:27:39.714509
9027 00:27:39.717468 RX Delay 19 -> 252, step: 4
9028 00:27:39.721101 iDelay=195, Bit 0, Center 136 (91 ~ 182) 92
9029 00:27:39.727143 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
9030 00:27:39.730806 iDelay=195, Bit 2, Center 120 (71 ~ 170) 100
9031 00:27:39.733941 iDelay=195, Bit 3, Center 132 (83 ~ 182) 100
9032 00:27:39.737315 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
9033 00:27:39.740637 iDelay=195, Bit 5, Center 144 (99 ~ 190) 92
9034 00:27:39.743925 iDelay=195, Bit 6, Center 140 (91 ~ 190) 100
9035 00:27:39.750515 iDelay=195, Bit 7, Center 132 (83 ~ 182) 100
9036 00:27:39.753811 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
9037 00:27:39.757728 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
9038 00:27:39.760661 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
9039 00:27:39.764091 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
9040 00:27:39.770721 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
9041 00:27:39.773815 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9042 00:27:39.777350 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
9043 00:27:39.780643 iDelay=195, Bit 15, Center 142 (91 ~ 194) 104
9044 00:27:39.780800 ==
9045 00:27:39.784304 Dram Type= 6, Freq= 0, CH_1, rank 1
9046 00:27:39.790231 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9047 00:27:39.790297 ==
9048 00:27:39.790356 DQS Delay:
9049 00:27:39.793879 DQS0 = 0, DQS1 = 0
9050 00:27:39.793942 DQM Delay:
9051 00:27:39.797284 DQM0 = 133, DQM1 = 130
9052 00:27:39.797343 DQ Delay:
9053 00:27:39.800327 DQ0 =136, DQ1 =130, DQ2 =120, DQ3 =132
9054 00:27:39.803854 DQ4 =134, DQ5 =144, DQ6 =140, DQ7 =132
9055 00:27:39.807350 DQ8 =112, DQ9 =118, DQ10 =130, DQ11 =124
9056 00:27:39.810358 DQ12 =138, DQ13 =138, DQ14 =138, DQ15 =142
9057 00:27:39.810427
9058 00:27:39.810482
9059 00:27:39.810533
9060 00:27:39.813854 [DramC_TX_OE_Calibration] TA2
9061 00:27:39.817374 Original DQ_B0 (3 6) =30, OEN = 27
9062 00:27:39.820385 Original DQ_B1 (3 6) =30, OEN = 27
9063 00:27:39.824011 24, 0x0, End_B0=24 End_B1=24
9064 00:27:39.824072 25, 0x0, End_B0=25 End_B1=25
9065 00:27:39.827002 26, 0x0, End_B0=26 End_B1=26
9066 00:27:39.830223 27, 0x0, End_B0=27 End_B1=27
9067 00:27:39.833897 28, 0x0, End_B0=28 End_B1=28
9068 00:27:39.837339 29, 0x0, End_B0=29 End_B1=29
9069 00:27:39.837399 30, 0x0, End_B0=30 End_B1=30
9070 00:27:39.840349 31, 0x4141, End_B0=30 End_B1=30
9071 00:27:39.843770 Byte0 end_step=30 best_step=27
9072 00:27:39.846954 Byte1 end_step=30 best_step=27
9073 00:27:39.850337 Byte0 TX OE(2T, 0.5T) = (3, 3)
9074 00:27:39.853449 Byte1 TX OE(2T, 0.5T) = (3, 3)
9075 00:27:39.853509
9076 00:27:39.853562
9077 00:27:39.860457 [DQSOSCAuto] RK1, (LSB)MR18= 0x1b07, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 396 ps
9078 00:27:39.863864 CH1 RK1: MR19=303, MR18=1B07
9079 00:27:39.870462 CH1_RK1: MR19=0x303, MR18=0x1B07, DQSOSC=396, MR23=63, INC=23, DEC=15
9080 00:27:39.873954 [RxdqsGatingPostProcess] freq 1600
9081 00:27:39.876906 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9082 00:27:39.880558 best DQS0 dly(2T, 0.5T) = (1, 1)
9083 00:27:39.883474 best DQS1 dly(2T, 0.5T) = (1, 1)
9084 00:27:39.886888 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9085 00:27:39.890439 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9086 00:27:39.893542 best DQS0 dly(2T, 0.5T) = (1, 1)
9087 00:27:39.897035 best DQS1 dly(2T, 0.5T) = (1, 1)
9088 00:27:39.899956 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9089 00:27:39.903589 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9090 00:27:39.907126 Pre-setting of DQS Precalculation
9091 00:27:39.910170 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9092 00:27:39.917160 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9093 00:27:39.923734 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9094 00:27:39.926655
9095 00:27:39.926718
9096 00:27:39.926773 [Calibration Summary] 3200 Mbps
9097 00:27:39.930337 CH 0, Rank 0
9098 00:27:39.930397 SW Impedance : PASS
9099 00:27:39.933308 DUTY Scan : NO K
9100 00:27:39.936998 ZQ Calibration : PASS
9101 00:27:39.937058 Jitter Meter : NO K
9102 00:27:39.939974 CBT Training : PASS
9103 00:27:39.943751 Write leveling : PASS
9104 00:27:39.943813 RX DQS gating : PASS
9105 00:27:39.946682 RX DQ/DQS(RDDQC) : PASS
9106 00:27:39.950180 TX DQ/DQS : PASS
9107 00:27:39.950245 RX DATLAT : PASS
9108 00:27:39.953330 RX DQ/DQS(Engine): PASS
9109 00:27:39.956845 TX OE : PASS
9110 00:27:39.956912 All Pass.
9111 00:27:39.956967
9112 00:27:39.957019 CH 0, Rank 1
9113 00:27:39.960022 SW Impedance : PASS
9114 00:27:39.963483 DUTY Scan : NO K
9115 00:27:39.963546 ZQ Calibration : PASS
9116 00:27:39.966791 Jitter Meter : NO K
9117 00:27:39.970159 CBT Training : PASS
9118 00:27:39.970218 Write leveling : PASS
9119 00:27:39.973136 RX DQS gating : PASS
9120 00:27:39.973195 RX DQ/DQS(RDDQC) : PASS
9121 00:27:39.976497 TX DQ/DQS : PASS
9122 00:27:39.979858 RX DATLAT : PASS
9123 00:27:39.979917 RX DQ/DQS(Engine): PASS
9124 00:27:39.983579 TX OE : PASS
9125 00:27:39.983646 All Pass.
9126 00:27:39.983701
9127 00:27:39.986438 CH 1, Rank 0
9128 00:27:39.986499 SW Impedance : PASS
9129 00:27:39.990035 DUTY Scan : NO K
9130 00:27:39.993537 ZQ Calibration : PASS
9131 00:27:39.993597 Jitter Meter : NO K
9132 00:27:39.996334 CBT Training : PASS
9133 00:27:39.999734 Write leveling : PASS
9134 00:27:39.999793 RX DQS gating : PASS
9135 00:27:40.003189 RX DQ/DQS(RDDQC) : PASS
9136 00:27:40.006735 TX DQ/DQS : PASS
9137 00:27:40.006797 RX DATLAT : PASS
9138 00:27:40.009832 RX DQ/DQS(Engine): PASS
9139 00:27:40.013224 TX OE : PASS
9140 00:27:40.013284 All Pass.
9141 00:27:40.013335
9142 00:27:40.013388 CH 1, Rank 1
9143 00:27:40.016352 SW Impedance : PASS
9144 00:27:40.019979 DUTY Scan : NO K
9145 00:27:40.020039 ZQ Calibration : PASS
9146 00:27:40.022898 Jitter Meter : NO K
9147 00:27:40.026781 CBT Training : PASS
9148 00:27:40.026840 Write leveling : PASS
9149 00:27:40.029717 RX DQS gating : PASS
9150 00:27:40.029781 RX DQ/DQS(RDDQC) : PASS
9151 00:27:40.033036 TX DQ/DQS : PASS
9152 00:27:40.036307 RX DATLAT : PASS
9153 00:27:40.036377 RX DQ/DQS(Engine): PASS
9154 00:27:40.039889 TX OE : PASS
9155 00:27:40.039952 All Pass.
9156 00:27:40.040004
9157 00:27:40.043046 DramC Write-DBI on
9158 00:27:40.046625 PER_BANK_REFRESH: Hybrid Mode
9159 00:27:40.046686 TX_TRACKING: ON
9160 00:27:40.056305 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9161 00:27:40.063107 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9162 00:27:40.069679 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9163 00:27:40.073047 [FAST_K] Save calibration result to emmc
9164 00:27:40.076291 sync common calibartion params.
9165 00:27:40.079612 sync cbt_mode0:1, 1:1
9166 00:27:40.083319 dram_init: ddr_geometry: 2
9167 00:27:40.083393 dram_init: ddr_geometry: 2
9168 00:27:40.086589 dram_init: ddr_geometry: 2
9169 00:27:40.089594 0:dram_rank_size:100000000
9170 00:27:40.093308 1:dram_rank_size:100000000
9171 00:27:40.096286 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9172 00:27:40.099690 DFS_SHUFFLE_HW_MODE: ON
9173 00:27:40.103003 dramc_set_vcore_voltage set vcore to 725000
9174 00:27:40.106832 Read voltage for 1600, 0
9175 00:27:40.106902 Vio18 = 0
9176 00:27:40.106960 Vcore = 725000
9177 00:27:40.109779 Vdram = 0
9178 00:27:40.109841 Vddq = 0
9179 00:27:40.109897 Vmddr = 0
9180 00:27:40.112810 switch to 3200 Mbps bootup
9181 00:27:40.116444 [DramcRunTimeConfig]
9182 00:27:40.116530 PHYPLL
9183 00:27:40.116615 DPM_CONTROL_AFTERK: ON
9184 00:27:40.119559 PER_BANK_REFRESH: ON
9185 00:27:40.123109 REFRESH_OVERHEAD_REDUCTION: ON
9186 00:27:40.123178 CMD_PICG_NEW_MODE: OFF
9187 00:27:40.126525 XRTWTW_NEW_MODE: ON
9188 00:27:40.126604 XRTRTR_NEW_MODE: ON
9189 00:27:40.129504 TX_TRACKING: ON
9190 00:27:40.129580 RDSEL_TRACKING: OFF
9191 00:27:40.133067 DQS Precalculation for DVFS: ON
9192 00:27:40.136521 RX_TRACKING: OFF
9193 00:27:40.136621 HW_GATING DBG: ON
9194 00:27:40.139820 ZQCS_ENABLE_LP4: ON
9195 00:27:40.139896 RX_PICG_NEW_MODE: ON
9196 00:27:40.143276 TX_PICG_NEW_MODE: ON
9197 00:27:40.146519 ENABLE_RX_DCM_DPHY: ON
9198 00:27:40.146618 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9199 00:27:40.149572 DUMMY_READ_FOR_TRACKING: OFF
9200 00:27:40.153210 !!! SPM_CONTROL_AFTERK: OFF
9201 00:27:40.156564 !!! SPM could not control APHY
9202 00:27:40.156640 IMPEDANCE_TRACKING: ON
9203 00:27:40.159803 TEMP_SENSOR: ON
9204 00:27:40.159878 HW_SAVE_FOR_SR: OFF
9205 00:27:40.162850 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9206 00:27:40.169462 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9207 00:27:40.169539 Read ODT Tracking: ON
9208 00:27:40.172966 Refresh Rate DeBounce: ON
9209 00:27:40.173042 DFS_NO_QUEUE_FLUSH: ON
9210 00:27:40.175990 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9211 00:27:40.179298 ENABLE_DFS_RUNTIME_MRW: OFF
9212 00:27:40.182897 DDR_RESERVE_NEW_MODE: ON
9213 00:27:40.183010 MR_CBT_SWITCH_FREQ: ON
9214 00:27:40.185861 =========================
9215 00:27:40.205616 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9216 00:27:40.208665 dram_init: ddr_geometry: 2
9217 00:27:40.227078 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9218 00:27:40.230355 dram_init: dram init end (result: 0)
9219 00:27:40.236629 DRAM-K: Full calibration passed in 24506 msecs
9220 00:27:40.240370 MRC: failed to locate region type 0.
9221 00:27:40.240447 DRAM rank0 size:0x100000000,
9222 00:27:40.243481 DRAM rank1 size=0x100000000
9223 00:27:40.253586 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9224 00:27:40.260449 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9225 00:27:40.266805 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9226 00:27:40.273764 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9227 00:27:40.276851 DRAM rank0 size:0x100000000,
9228 00:27:40.280197 DRAM rank1 size=0x100000000
9229 00:27:40.280310 CBMEM:
9230 00:27:40.284026 IMD: root @ 0xfffff000 254 entries.
9231 00:27:40.286663 IMD: root @ 0xffffec00 62 entries.
9232 00:27:40.290238 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9233 00:27:40.293675 WARNING: RO_VPD is uninitialized or empty.
9234 00:27:40.300108 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9235 00:27:40.306816 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9236 00:27:40.319848 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9237 00:27:40.331126 BS: romstage times (exec / console): total (unknown) / 24005 ms
9238 00:27:40.331228
9239 00:27:40.331300
9240 00:27:40.341359 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9241 00:27:40.344820 ARM64: Exception handlers installed.
9242 00:27:40.347816 ARM64: Testing exception
9243 00:27:40.350959 ARM64: Done test exception
9244 00:27:40.351039 Enumerating buses...
9245 00:27:40.354496 Show all devs... Before device enumeration.
9246 00:27:40.357698 Root Device: enabled 1
9247 00:27:40.361276 CPU_CLUSTER: 0: enabled 1
9248 00:27:40.361355 CPU: 00: enabled 1
9249 00:27:40.364416 Compare with tree...
9250 00:27:40.364494 Root Device: enabled 1
9251 00:27:40.367588 CPU_CLUSTER: 0: enabled 1
9252 00:27:40.371120 CPU: 00: enabled 1
9253 00:27:40.371198 Root Device scanning...
9254 00:27:40.374549 scan_static_bus for Root Device
9255 00:27:40.377557 CPU_CLUSTER: 0 enabled
9256 00:27:40.381126 scan_static_bus for Root Device done
9257 00:27:40.384261 scan_bus: bus Root Device finished in 8 msecs
9258 00:27:40.384362 done
9259 00:27:40.391298 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9260 00:27:40.394301 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9261 00:27:40.400812 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9262 00:27:40.404176 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9263 00:27:40.407650 Allocating resources...
9264 00:27:40.410710 Reading resources...
9265 00:27:40.414278 Root Device read_resources bus 0 link: 0
9266 00:27:40.414379 DRAM rank0 size:0x100000000,
9267 00:27:40.417748 DRAM rank1 size=0x100000000
9268 00:27:40.420793 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9269 00:27:40.424434 CPU: 00 missing read_resources
9270 00:27:40.427380 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9271 00:27:40.434253 Root Device read_resources bus 0 link: 0 done
9272 00:27:40.434354 Done reading resources.
9273 00:27:40.440534 Show resources in subtree (Root Device)...After reading.
9274 00:27:40.444039 Root Device child on link 0 CPU_CLUSTER: 0
9275 00:27:40.447210 CPU_CLUSTER: 0 child on link 0 CPU: 00
9276 00:27:40.457516 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9277 00:27:40.457599 CPU: 00
9278 00:27:40.460584 Root Device assign_resources, bus 0 link: 0
9279 00:27:40.464195 CPU_CLUSTER: 0 missing set_resources
9280 00:27:40.470529 Root Device assign_resources, bus 0 link: 0 done
9281 00:27:40.470608 Done setting resources.
9282 00:27:40.476935 Show resources in subtree (Root Device)...After assigning values.
9283 00:27:40.480248 Root Device child on link 0 CPU_CLUSTER: 0
9284 00:27:40.483764 CPU_CLUSTER: 0 child on link 0 CPU: 00
9285 00:27:40.493715 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9286 00:27:40.493795 CPU: 00
9287 00:27:40.497155 Done allocating resources.
9288 00:27:40.500174 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9289 00:27:40.503880 Enabling resources...
9290 00:27:40.503958 done.
9291 00:27:40.510519 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9292 00:27:40.510599 Initializing devices...
9293 00:27:40.513496 Root Device init
9294 00:27:40.513574 init hardware done!
9295 00:27:40.516957 0x00000018: ctrlr->caps
9296 00:27:40.520514 52.000 MHz: ctrlr->f_max
9297 00:27:40.520618 0.400 MHz: ctrlr->f_min
9298 00:27:40.523637 0x40ff8080: ctrlr->voltages
9299 00:27:40.523716 sclk: 390625
9300 00:27:40.527205 Bus Width = 1
9301 00:27:40.527282 sclk: 390625
9302 00:27:40.530218 Bus Width = 1
9303 00:27:40.530296 Early init status = 3
9304 00:27:40.536825 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9305 00:27:40.540410 in-header: 03 fc 00 00 01 00 00 00
9306 00:27:40.540489 in-data: 00
9307 00:27:40.547040 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9308 00:27:40.551239 in-header: 03 fd 00 00 00 00 00 00
9309 00:27:40.554522 in-data:
9310 00:27:40.557776 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9311 00:27:40.562589 in-header: 03 fc 00 00 01 00 00 00
9312 00:27:40.565490 in-data: 00
9313 00:27:40.569190 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9314 00:27:40.574589 in-header: 03 fd 00 00 00 00 00 00
9315 00:27:40.578078 in-data:
9316 00:27:40.581332 [SSUSB] Setting up USB HOST controller...
9317 00:27:40.584544 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9318 00:27:40.588019 [SSUSB] phy power-on done.
9319 00:27:40.591072 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9320 00:27:40.597792 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9321 00:27:40.601130 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9322 00:27:40.607777 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9323 00:27:40.614508 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9324 00:27:40.621170 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9325 00:27:40.627397 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9326 00:27:40.634490 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9327 00:27:40.637446 SPM: binary array size = 0x9dc
9328 00:27:40.640901 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9329 00:27:40.647701 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9330 00:27:40.654282 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9331 00:27:40.657759 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9332 00:27:40.663943 configure_display: Starting display init
9333 00:27:40.697963 anx7625_power_on_init: Init interface.
9334 00:27:40.701193 anx7625_disable_pd_protocol: Disabled PD feature.
9335 00:27:40.704495 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9336 00:27:40.732380 anx7625_start_dp_work: Secure OCM version=00
9337 00:27:40.735713 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9338 00:27:40.750315 sp_tx_get_edid_block: EDID Block = 1
9339 00:27:40.853218 Extracted contents:
9340 00:27:40.856292 header: 00 ff ff ff ff ff ff 00
9341 00:27:40.859775 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9342 00:27:40.863219 version: 01 04
9343 00:27:40.866189 basic params: 95 1f 11 78 0a
9344 00:27:40.869834 chroma info: 76 90 94 55 54 90 27 21 50 54
9345 00:27:40.872683 established: 00 00 00
9346 00:27:40.879743 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9347 00:27:40.883113 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9348 00:27:40.889324 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9349 00:27:40.896098 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9350 00:27:40.903116 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9351 00:27:40.906150 extensions: 00
9352 00:27:40.906228 checksum: fb
9353 00:27:40.906288
9354 00:27:40.909682 Manufacturer: IVO Model 57d Serial Number 0
9355 00:27:40.912994 Made week 0 of 2020
9356 00:27:40.913065 EDID version: 1.4
9357 00:27:40.916344 Digital display
9358 00:27:40.919232 6 bits per primary color channel
9359 00:27:40.919302 DisplayPort interface
9360 00:27:40.922793 Maximum image size: 31 cm x 17 cm
9361 00:27:40.926163 Gamma: 220%
9362 00:27:40.926236 Check DPMS levels
9363 00:27:40.929165 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9364 00:27:40.932755 First detailed timing is preferred timing
9365 00:27:40.936333 Established timings supported:
9366 00:27:40.939265 Standard timings supported:
9367 00:27:40.939342 Detailed timings
9368 00:27:40.946348 Hex of detail: 383680a07038204018303c0035ae10000019
9369 00:27:40.949615 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9370 00:27:40.955829 0780 0798 07c8 0820 hborder 0
9371 00:27:40.959310 0438 043b 0447 0458 vborder 0
9372 00:27:40.959388 -hsync -vsync
9373 00:27:40.962652 Did detailed timing
9374 00:27:40.966026 Hex of detail: 000000000000000000000000000000000000
9375 00:27:40.969264 Manufacturer-specified data, tag 0
9376 00:27:40.976266 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9377 00:27:40.976346 ASCII string: InfoVision
9378 00:27:40.982225 Hex of detail: 000000fe00523134304e574635205248200a
9379 00:27:40.985654 ASCII string: R140NWF5 RH
9380 00:27:40.985740 Checksum
9381 00:27:40.985805 Checksum: 0xfb (valid)
9382 00:27:40.992202 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9383 00:27:40.995598 DSI data_rate: 832800000 bps
9384 00:27:40.998991 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9385 00:27:41.005772 anx7625_parse_edid: pixelclock(138800).
9386 00:27:41.008720 hactive(1920), hsync(48), hfp(24), hbp(88)
9387 00:27:41.012208 vactive(1080), vsync(12), vfp(3), vbp(17)
9388 00:27:41.015665 anx7625_dsi_config: config dsi.
9389 00:27:41.022020 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9390 00:27:41.034703 anx7625_dsi_config: success to config DSI
9391 00:27:41.038019 anx7625_dp_start: MIPI phy setup OK.
9392 00:27:41.042033 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9393 00:27:41.044937 mtk_ddp_mode_set invalid vrefresh 60
9394 00:27:41.048362 main_disp_path_setup
9395 00:27:41.048434 ovl_layer_smi_id_en
9396 00:27:41.051821 ovl_layer_smi_id_en
9397 00:27:41.051892 ccorr_config
9398 00:27:41.051948 aal_config
9399 00:27:41.054785 gamma_config
9400 00:27:41.054867 postmask_config
9401 00:27:41.058164 dither_config
9402 00:27:41.061499 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9403 00:27:41.068387 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9404 00:27:41.071636 Root Device init finished in 554 msecs
9405 00:27:41.071709 CPU_CLUSTER: 0 init
9406 00:27:41.081393 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9407 00:27:41.084857 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9408 00:27:41.087898 APU_MBOX 0x190000b0 = 0x10001
9409 00:27:41.091403 APU_MBOX 0x190001b0 = 0x10001
9410 00:27:41.094919 APU_MBOX 0x190005b0 = 0x10001
9411 00:27:41.098267 APU_MBOX 0x190006b0 = 0x10001
9412 00:27:41.101414 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9413 00:27:41.114286 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9414 00:27:41.126594 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9415 00:27:41.133074 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9416 00:27:41.144537 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9417 00:27:41.153872 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9418 00:27:41.157069 CPU_CLUSTER: 0 init finished in 81 msecs
9419 00:27:41.160478 Devices initialized
9420 00:27:41.163867 Show all devs... After init.
9421 00:27:41.163948 Root Device: enabled 1
9422 00:27:41.167393 CPU_CLUSTER: 0: enabled 1
9423 00:27:41.170602 CPU: 00: enabled 1
9424 00:27:41.173556 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9425 00:27:41.176967 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9426 00:27:41.180287 ELOG: NV offset 0x57f000 size 0x1000
9427 00:27:41.187055 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9428 00:27:41.193600 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9429 00:27:41.197265 ELOG: Event(17) added with size 13 at 2024-06-21 00:27:40 UTC
9430 00:27:41.200193 out: cmd=0x121: 03 db 21 01 00 00 00 00
9431 00:27:41.203958 in-header: 03 7d 00 00 2c 00 00 00
9432 00:27:41.217152 in-data: c1 71 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9433 00:27:41.224123 ELOG: Event(A1) added with size 10 at 2024-06-21 00:27:40 UTC
9434 00:27:41.230592 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9435 00:27:41.237501 ELOG: Event(A0) added with size 9 at 2024-06-21 00:27:40 UTC
9436 00:27:41.240944 elog_add_boot_reason: Logged dev mode boot
9437 00:27:41.244267 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9438 00:27:41.247203 Finalize devices...
9439 00:27:41.247292 Devices finalized
9440 00:27:41.254090 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9441 00:27:41.257403 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9442 00:27:41.260564 in-header: 03 07 00 00 08 00 00 00
9443 00:27:41.263860 in-data: aa e4 47 04 13 02 00 00
9444 00:27:41.267088 Chrome EC: UHEPI supported
9445 00:27:41.273888 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9446 00:27:41.277138 in-header: 03 a9 00 00 08 00 00 00
9447 00:27:41.280507 in-data: 84 60 60 08 00 00 00 00
9448 00:27:41.284001 ELOG: Event(91) added with size 10 at 2024-06-21 00:27:40 UTC
9449 00:27:41.290457 Chrome EC: clear events_b mask to 0x0000000020004000
9450 00:27:41.296887 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9451 00:27:41.301034 in-header: 03 fd 00 00 00 00 00 00
9452 00:27:41.304472 in-data:
9453 00:27:41.307936 BS: BS_WRITE_TABLES entry times (exec / console): 4 / 46 ms
9454 00:27:41.310946 Writing coreboot table at 0xffe64000
9455 00:27:41.314662 0. 000000000010a000-0000000000113fff: RAMSTAGE
9456 00:27:41.321118 1. 0000000040000000-00000000400fffff: RAM
9457 00:27:41.324402 2. 0000000040100000-000000004032afff: RAMSTAGE
9458 00:27:41.327987 3. 000000004032b000-00000000545fffff: RAM
9459 00:27:41.330970 4. 0000000054600000-000000005465ffff: BL31
9460 00:27:41.334565 5. 0000000054660000-00000000ffe63fff: RAM
9461 00:27:41.340957 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9462 00:27:41.344542 7. 0000000100000000-000000023fffffff: RAM
9463 00:27:41.347921 Passing 5 GPIOs to payload:
9464 00:27:41.350911 NAME | PORT | POLARITY | VALUE
9465 00:27:41.357562 EC in RW | 0x000000aa | low | undefined
9466 00:27:41.361074 EC interrupt | 0x00000005 | low | undefined
9467 00:27:41.364497 TPM interrupt | 0x000000ab | high | undefined
9468 00:27:41.371077 SD card detect | 0x00000011 | high | undefined
9469 00:27:41.374840 speaker enable | 0x00000093 | high | undefined
9470 00:27:41.377740 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9471 00:27:41.381076 in-header: 03 f9 00 00 02 00 00 00
9472 00:27:41.384479 in-data: 02 00
9473 00:27:41.387821 ADC[4]: Raw value=900663 ID=7
9474 00:27:41.387915 ADC[3]: Raw value=212810 ID=1
9475 00:27:41.390834 RAM Code: 0x71
9476 00:27:41.394277 ADC[6]: Raw value=74502 ID=0
9477 00:27:41.394343 ADC[5]: Raw value=212072 ID=1
9478 00:27:41.397706 SKU Code: 0x1
9479 00:27:41.400792 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 55fa
9480 00:27:41.404480 coreboot table: 964 bytes.
9481 00:27:41.407517 IMD ROOT 0. 0xfffff000 0x00001000
9482 00:27:41.411007 IMD SMALL 1. 0xffffe000 0x00001000
9483 00:27:41.414050 RO MCACHE 2. 0xffffc000 0x00001104
9484 00:27:41.417490 CONSOLE 3. 0xfff7c000 0x00080000
9485 00:27:41.421048 FMAP 4. 0xfff7b000 0x00000452
9486 00:27:41.424366 TIME STAMP 5. 0xfff7a000 0x00000910
9487 00:27:41.427409 VBOOT WORK 6. 0xfff66000 0x00014000
9488 00:27:41.430826 RAMOOPS 7. 0xffe66000 0x00100000
9489 00:27:41.434074 COREBOOT 8. 0xffe64000 0x00002000
9490 00:27:41.437602 IMD small region:
9491 00:27:41.440978 IMD ROOT 0. 0xffffec00 0x00000400
9492 00:27:41.445820 VPD 1. 0xffffeb80 0x0000006c
9493 00:27:41.447467 MMC STATUS 2. 0xffffeb60 0x00000004
9494 00:27:41.450815 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9495 00:27:41.457724 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9496 00:27:41.498051 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9497 00:27:41.501488 Checking segment from ROM address 0x40100000
9498 00:27:41.504534 Checking segment from ROM address 0x4010001c
9499 00:27:41.511460 Loading segment from ROM address 0x40100000
9500 00:27:41.511540 code (compression=0)
9501 00:27:41.521383 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9502 00:27:41.528255 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9503 00:27:41.528341 it's not compressed!
9504 00:27:41.534693 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9505 00:27:41.537987 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9506 00:27:41.558254 Loading segment from ROM address 0x4010001c
9507 00:27:41.558391 Entry Point 0x80000000
9508 00:27:41.561611 Loaded segments
9509 00:27:41.564971 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9510 00:27:41.571810 Jumping to boot code at 0x80000000(0xffe64000)
9511 00:27:41.578166 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9512 00:27:41.585012 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9513 00:27:41.593025 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9514 00:27:41.596314 Checking segment from ROM address 0x40100000
9515 00:27:41.599771 Checking segment from ROM address 0x4010001c
9516 00:27:41.606264 Loading segment from ROM address 0x40100000
9517 00:27:41.606354 code (compression=1)
9518 00:27:41.612983 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9519 00:27:41.622654 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9520 00:27:41.622741 using LZMA
9521 00:27:41.631282 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9522 00:27:41.637949 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9523 00:27:41.641297 Loading segment from ROM address 0x4010001c
9524 00:27:41.641418 Entry Point 0x54601000
9525 00:27:41.644670 Loaded segments
9526 00:27:41.648014 NOTICE: MT8192 bl31_setup
9527 00:27:41.654650 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9528 00:27:41.657881 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9529 00:27:41.661442 WARNING: region 0:
9530 00:27:41.664753 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9531 00:27:41.664882 WARNING: region 1:
9532 00:27:41.671578 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9533 00:27:41.674538 WARNING: region 2:
9534 00:27:41.677920 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9535 00:27:41.681332 WARNING: region 3:
9536 00:27:41.684582 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9537 00:27:41.688192 WARNING: region 4:
9538 00:27:41.694769 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9539 00:27:41.694850 WARNING: region 5:
9540 00:27:41.698158 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9541 00:27:41.701587 WARNING: region 6:
9542 00:27:41.704599 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9543 00:27:41.708559 WARNING: region 7:
9544 00:27:41.711262 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9545 00:27:41.718182 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9546 00:27:41.721396 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9547 00:27:41.724726 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9548 00:27:41.731721 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9549 00:27:41.734533 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9550 00:27:41.738132 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9551 00:27:41.744632 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9552 00:27:41.748065 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9553 00:27:41.754927 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9554 00:27:41.757800 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9555 00:27:41.761196 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9556 00:27:41.767744 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9557 00:27:41.770977 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9558 00:27:41.774713 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9559 00:27:41.781224 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9560 00:27:41.784749 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9561 00:27:41.790954 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9562 00:27:41.794433 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9563 00:27:41.798027 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9564 00:27:41.804448 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9565 00:27:41.808096 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9566 00:27:41.811192 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9567 00:27:41.817937 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9568 00:27:41.821060 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9569 00:27:41.827576 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9570 00:27:41.831014 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9571 00:27:41.834456 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9572 00:27:41.841365 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9573 00:27:41.844625 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9574 00:27:41.851297 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9575 00:27:41.854422 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9576 00:27:41.857651 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9577 00:27:41.864998 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9578 00:27:41.867521 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9579 00:27:41.870887 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9580 00:27:41.874242 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9581 00:27:41.880799 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9582 00:27:41.884066 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9583 00:27:41.887186 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9584 00:27:41.890564 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9585 00:27:41.897374 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9586 00:27:41.900902 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9587 00:27:41.904497 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9588 00:27:41.907850 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9589 00:27:41.914112 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9590 00:27:41.917327 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9591 00:27:41.920657 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9592 00:27:41.927382 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9593 00:27:41.930510 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9594 00:27:41.934052 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9595 00:27:41.940637 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9596 00:27:41.943739 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9597 00:27:41.950568 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9598 00:27:41.953663 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9599 00:27:41.960403 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9600 00:27:41.963878 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9601 00:27:41.967370 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9602 00:27:41.973658 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9603 00:27:41.976927 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9604 00:27:41.983547 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9605 00:27:41.987057 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9606 00:27:41.993739 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9607 00:27:41.996842 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9608 00:27:42.003647 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9609 00:27:42.006851 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9610 00:27:42.010197 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9611 00:27:42.016734 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9612 00:27:42.020297 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9613 00:27:42.026778 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9614 00:27:42.030232 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9615 00:27:42.036729 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9616 00:27:42.040028 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9617 00:27:42.043673 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9618 00:27:42.050021 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9619 00:27:42.053305 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9620 00:27:42.060158 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9621 00:27:42.063198 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9622 00:27:42.069952 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9623 00:27:42.073418 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9624 00:27:42.080095 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9625 00:27:42.083442 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9626 00:27:42.086405 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9627 00:27:42.093434 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9628 00:27:42.096588 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9629 00:27:42.103176 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9630 00:27:42.106335 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9631 00:27:42.113066 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9632 00:27:42.116716 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9633 00:27:42.119751 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9634 00:27:42.126576 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9635 00:27:42.130105 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9636 00:27:42.136818 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9637 00:27:42.139681 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9638 00:27:42.146542 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9639 00:27:42.149789 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9640 00:27:42.153233 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9641 00:27:42.160101 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9642 00:27:42.163331 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9643 00:27:42.166563 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9644 00:27:42.170074 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9645 00:27:42.176331 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9646 00:27:42.179826 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9647 00:27:42.186758 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9648 00:27:42.189866 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9649 00:27:42.193136 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9650 00:27:42.200111 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9651 00:27:42.203134 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9652 00:27:42.206476 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9653 00:27:42.213103 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9654 00:27:42.216613 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9655 00:27:42.223425 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9656 00:27:42.226540 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9657 00:27:42.233080 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9658 00:27:42.236541 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9659 00:27:42.239808 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9660 00:27:42.246758 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9661 00:27:42.249703 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9662 00:27:42.253201 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9663 00:27:42.259825 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9664 00:27:42.263201 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9665 00:27:42.266193 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9666 00:27:42.269659 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9667 00:27:42.273052 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9668 00:27:42.279944 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9669 00:27:42.283249 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9670 00:27:42.289929 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9671 00:27:42.292864 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9672 00:27:42.296352 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9673 00:27:42.302800 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9674 00:27:42.306235 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9675 00:27:42.313059 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9676 00:27:42.316320 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9677 00:27:42.319289 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9678 00:27:42.325952 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9679 00:27:42.329294 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9680 00:27:42.336344 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9681 00:27:42.339479 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9682 00:27:42.342606 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9683 00:27:42.349607 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9684 00:27:42.352891 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9685 00:27:42.356272 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9686 00:27:42.362594 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9687 00:27:42.365972 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9688 00:27:42.372832 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9689 00:27:42.376428 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9690 00:27:42.379310 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9691 00:27:42.386157 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9692 00:27:42.389258 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9693 00:27:42.396014 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9694 00:27:42.399173 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9695 00:27:42.402623 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9696 00:27:42.409462 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9697 00:27:42.413042 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9698 00:27:42.416046 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9699 00:27:42.422680 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9700 00:27:42.426081 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9701 00:27:42.432509 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9702 00:27:42.436032 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9703 00:27:42.439304 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9704 00:27:42.445698 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9705 00:27:42.449045 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9706 00:27:42.455661 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9707 00:27:42.459210 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9708 00:27:42.462673 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9709 00:27:42.469286 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9710 00:27:42.472638 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9711 00:27:42.475969 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9712 00:27:42.482424 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9713 00:27:42.485953 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9714 00:27:42.492473 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9715 00:27:42.495871 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9716 00:27:42.499370 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9717 00:27:42.505709 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9718 00:27:42.509029 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9719 00:27:42.516208 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9720 00:27:42.518952 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9721 00:27:42.522448 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9722 00:27:42.529245 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9723 00:27:42.532271 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9724 00:27:42.535614 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9725 00:27:42.542109 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9726 00:27:42.545676 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9727 00:27:42.552552 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9728 00:27:42.555683 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9729 00:27:42.559176 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9730 00:27:42.565800 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9731 00:27:42.568890 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9732 00:27:42.575731 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9733 00:27:42.578885 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9734 00:27:42.585683 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9735 00:27:42.588799 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9736 00:27:42.592216 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9737 00:27:42.598818 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9738 00:27:42.602295 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9739 00:27:42.608674 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9740 00:27:42.612285 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9741 00:27:42.615294 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9742 00:27:42.622524 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9743 00:27:42.625286 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9744 00:27:42.632130 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9745 00:27:42.635500 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9746 00:27:42.638873 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9747 00:27:42.645260 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9748 00:27:42.648638 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9749 00:27:42.655732 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9750 00:27:42.658754 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9751 00:27:42.665275 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9752 00:27:42.668594 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9753 00:27:42.672196 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9754 00:27:42.678610 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9755 00:27:42.681946 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9756 00:27:42.689041 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9757 00:27:42.692214 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9758 00:27:42.695602 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9759 00:27:42.702229 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9760 00:27:42.705664 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9761 00:27:42.712180 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9762 00:27:42.715266 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9763 00:27:42.718606 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9764 00:27:42.725477 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9765 00:27:42.728811 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9766 00:27:42.735212 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9767 00:27:42.738768 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9768 00:27:42.745518 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9769 00:27:42.748889 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9770 00:27:42.751897 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9771 00:27:42.758903 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9772 00:27:42.761943 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9773 00:27:42.769005 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9774 00:27:42.772153 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9775 00:27:42.775554 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9776 00:27:42.778523 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9777 00:27:42.782272 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9778 00:27:42.788787 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9779 00:27:42.791993 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9780 00:27:42.795262 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9781 00:27:42.801611 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9782 00:27:42.805127 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9783 00:27:42.808616 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9784 00:27:42.815523 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9785 00:27:42.818518 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9786 00:27:42.824820 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9787 00:27:42.828262 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9788 00:27:42.831884 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9789 00:27:42.838895 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9790 00:27:42.841686 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9791 00:27:42.845131 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9792 00:27:42.851817 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9793 00:27:42.855106 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9794 00:27:42.858718 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9795 00:27:42.865139 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9796 00:27:42.868206 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9797 00:27:42.875026 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9798 00:27:42.878340 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9799 00:27:42.881769 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9800 00:27:42.888165 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9801 00:27:42.891889 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9802 00:27:42.895155 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9803 00:27:42.901877 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9804 00:27:42.904989 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9805 00:27:42.911790 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9806 00:27:42.915124 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9807 00:27:42.918296 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9808 00:27:42.925282 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9809 00:27:42.928281 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9810 00:27:42.931750 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9811 00:27:42.938464 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9812 00:27:42.941699 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9813 00:27:42.944955 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9814 00:27:42.951545 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9815 00:27:42.955014 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9816 00:27:42.958348 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9817 00:27:42.961994 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9818 00:27:42.964897 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9819 00:27:42.971689 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9820 00:27:42.975137 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9821 00:27:42.978341 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9822 00:27:42.981694 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9823 00:27:42.988733 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9824 00:27:42.992081 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9825 00:27:42.994991 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9826 00:27:42.998355 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9827 00:27:43.004945 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9828 00:27:43.008549 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9829 00:27:43.014910 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9830 00:27:43.018386 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9831 00:27:43.025147 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9832 00:27:43.028129 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9833 00:27:43.031601 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9834 00:27:43.038198 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9835 00:27:43.041746 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9836 00:27:43.047963 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9837 00:27:43.051316 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9838 00:27:43.054702 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9839 00:27:43.061415 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9840 00:27:43.064784 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9841 00:27:43.071748 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9842 00:27:43.074649 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9843 00:27:43.078154 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9844 00:27:43.084643 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9845 00:27:43.087916 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9846 00:27:43.094865 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9847 00:27:43.098219 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9848 00:27:43.104548 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9849 00:27:43.108168 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9850 00:27:43.111604 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9851 00:27:43.118330 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9852 00:27:43.121328 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9853 00:27:43.124919 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9854 00:27:43.131521 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9855 00:27:43.134581 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9856 00:27:43.141343 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9857 00:27:43.144993 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9858 00:27:43.147834 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9859 00:27:43.154948 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9860 00:27:43.157944 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9861 00:27:43.164527 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9862 00:27:43.167962 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9863 00:27:43.174927 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9864 00:27:43.178335 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9865 00:27:43.181342 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9866 00:27:43.188018 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9867 00:27:43.191349 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9868 00:27:43.198236 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9869 00:27:43.201297 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9870 00:27:43.204597 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9871 00:27:43.211202 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9872 00:27:43.214922 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9873 00:27:43.221596 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9874 00:27:43.224542 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9875 00:27:43.227966 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9876 00:27:43.234689 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9877 00:27:43.238226 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9878 00:27:43.244961 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9879 00:27:43.248099 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9880 00:27:43.251297 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9881 00:27:43.258330 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9882 00:27:43.261016 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9883 00:27:43.267894 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9884 00:27:43.271216 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9885 00:27:43.274563 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9886 00:27:43.281051 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9887 00:27:43.284554 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9888 00:27:43.291309 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9889 00:27:43.294556 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9890 00:27:43.298098 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9891 00:27:43.304544 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9892 00:27:43.307866 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9893 00:27:43.314657 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9894 00:27:43.318354 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9895 00:27:43.321564 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9896 00:27:43.328324 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9897 00:27:43.331167 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9898 00:27:43.337919 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9899 00:27:43.341880 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9900 00:27:43.344606 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9901 00:27:43.351342 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9902 00:27:43.354557 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9903 00:27:43.361382 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9904 00:27:43.365159 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9905 00:27:43.371359 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9906 00:27:43.375065 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9907 00:27:43.378101 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9908 00:27:43.384662 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9909 00:27:43.388289 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9910 00:27:43.394741 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9911 00:27:43.398192 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9912 00:27:43.404573 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9913 00:27:43.407821 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9914 00:27:43.411154 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9915 00:27:43.417849 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9916 00:27:43.421269 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9917 00:27:43.428171 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9918 00:27:43.431206 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9919 00:27:43.437721 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9920 00:27:43.441327 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9921 00:27:43.447569 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9922 00:27:43.451009 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9923 00:27:43.454603 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9924 00:27:43.461021 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9925 00:27:43.464302 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9926 00:27:43.471080 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9927 00:27:43.474394 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9928 00:27:43.480923 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9929 00:27:43.484137 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9930 00:27:43.487609 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9931 00:27:43.494524 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9932 00:27:43.497598 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9933 00:27:43.504245 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9934 00:27:43.507778 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9935 00:27:43.514229 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9936 00:27:43.517306 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9937 00:27:43.523751 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9938 00:27:43.527245 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9939 00:27:43.530836 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9940 00:27:43.537095 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9941 00:27:43.540535 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9942 00:27:43.547453 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9943 00:27:43.550638 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9944 00:27:43.557134 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9945 00:27:43.560482 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9946 00:27:43.563909 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9947 00:27:43.570680 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9948 00:27:43.573984 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9949 00:27:43.580535 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9950 00:27:43.583469 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9951 00:27:43.590486 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9952 00:27:43.593830 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9953 00:27:43.597218 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9954 00:27:43.603576 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9955 00:27:43.607146 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9956 00:27:43.613523 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9957 00:27:43.617232 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9958 00:27:43.623719 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9959 00:27:43.626904 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9960 00:27:43.633946 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9961 00:27:43.636957 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9962 00:27:43.643937 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9963 00:27:43.647243 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9964 00:27:43.653604 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9965 00:27:43.656941 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9966 00:27:43.663906 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9967 00:27:43.666872 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9968 00:27:43.673873 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9969 00:27:43.677266 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9970 00:27:43.683831 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9971 00:27:43.687310 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9972 00:27:43.693849 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9973 00:27:43.697231 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9974 00:27:43.703851 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9975 00:27:43.707217 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9976 00:27:43.713899 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9977 00:27:43.717029 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9978 00:27:43.723970 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9979 00:27:43.726891 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9980 00:27:43.726968 INFO: [APUAPC] vio 0
9981 00:27:43.734480 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9982 00:27:43.738208 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9983 00:27:43.741037 INFO: [APUAPC] D0_APC_0: 0x400510
9984 00:27:43.744530 INFO: [APUAPC] D0_APC_1: 0x0
9985 00:27:43.747697 INFO: [APUAPC] D0_APC_2: 0x1540
9986 00:27:43.750983 INFO: [APUAPC] D0_APC_3: 0x0
9987 00:27:43.754456 INFO: [APUAPC] D1_APC_0: 0xffffffff
9988 00:27:43.757728 INFO: [APUAPC] D1_APC_1: 0xffffffff
9989 00:27:43.760961 INFO: [APUAPC] D1_APC_2: 0x3fffff
9990 00:27:43.764458 INFO: [APUAPC] D1_APC_3: 0x0
9991 00:27:43.767542 INFO: [APUAPC] D2_APC_0: 0xffffffff
9992 00:27:43.770955 INFO: [APUAPC] D2_APC_1: 0xffffffff
9993 00:27:43.774429 INFO: [APUAPC] D2_APC_2: 0x3fffff
9994 00:27:43.777951 INFO: [APUAPC] D2_APC_3: 0x0
9995 00:27:43.781552 INFO: [APUAPC] D3_APC_0: 0xffffffff
9996 00:27:43.784636 INFO: [APUAPC] D3_APC_1: 0xffffffff
9997 00:27:43.787898 INFO: [APUAPC] D3_APC_2: 0x3fffff
9998 00:27:43.790985 INFO: [APUAPC] D3_APC_3: 0x0
9999 00:27:43.794370 INFO: [APUAPC] D4_APC_0: 0xffffffff
10000 00:27:43.797784 INFO: [APUAPC] D4_APC_1: 0xffffffff
10001 00:27:43.801274 INFO: [APUAPC] D4_APC_2: 0x3fffff
10002 00:27:43.801351 INFO: [APUAPC] D4_APC_3: 0x0
10003 00:27:43.804597 INFO: [APUAPC] D5_APC_0: 0xffffffff
10004 00:27:43.807594 INFO: [APUAPC] D5_APC_1: 0xffffffff
10005 00:27:43.811241 INFO: [APUAPC] D5_APC_2: 0x3fffff
10006 00:27:43.814464 INFO: [APUAPC] D5_APC_3: 0x0
10007 00:27:43.818109 INFO: [APUAPC] D6_APC_0: 0xffffffff
10008 00:27:43.821374 INFO: [APUAPC] D6_APC_1: 0xffffffff
10009 00:27:43.824398 INFO: [APUAPC] D6_APC_2: 0x3fffff
10010 00:27:43.827677 INFO: [APUAPC] D6_APC_3: 0x0
10011 00:27:43.830874 INFO: [APUAPC] D7_APC_0: 0xffffffff
10012 00:27:43.834328 INFO: [APUAPC] D7_APC_1: 0xffffffff
10013 00:27:43.837966 INFO: [APUAPC] D7_APC_2: 0x3fffff
10014 00:27:43.841082 INFO: [APUAPC] D7_APC_3: 0x0
10015 00:27:43.844357 INFO: [APUAPC] D8_APC_0: 0xffffffff
10016 00:27:43.847424 INFO: [APUAPC] D8_APC_1: 0xffffffff
10017 00:27:43.851138 INFO: [APUAPC] D8_APC_2: 0x3fffff
10018 00:27:43.854197 INFO: [APUAPC] D8_APC_3: 0x0
10019 00:27:43.857856 INFO: [APUAPC] D9_APC_0: 0xffffffff
10020 00:27:43.861011 INFO: [APUAPC] D9_APC_1: 0xffffffff
10021 00:27:43.864343 INFO: [APUAPC] D9_APC_2: 0x3fffff
10022 00:27:43.868188 INFO: [APUAPC] D9_APC_3: 0x0
10023 00:27:43.871064 INFO: [APUAPC] D10_APC_0: 0xffffffff
10024 00:27:43.874127 INFO: [APUAPC] D10_APC_1: 0xffffffff
10025 00:27:43.877625 INFO: [APUAPC] D10_APC_2: 0x3fffff
10026 00:27:43.881146 INFO: [APUAPC] D10_APC_3: 0x0
10027 00:27:43.884586 INFO: [APUAPC] D11_APC_0: 0xffffffff
10028 00:27:43.887524 INFO: [APUAPC] D11_APC_1: 0xffffffff
10029 00:27:43.890970 INFO: [APUAPC] D11_APC_2: 0x3fffff
10030 00:27:43.894038 INFO: [APUAPC] D11_APC_3: 0x0
10031 00:27:43.897667 INFO: [APUAPC] D12_APC_0: 0xffffffff
10032 00:27:43.900696 INFO: [APUAPC] D12_APC_1: 0xffffffff
10033 00:27:43.904338 INFO: [APUAPC] D12_APC_2: 0x3fffff
10034 00:27:43.907717 INFO: [APUAPC] D12_APC_3: 0x0
10035 00:27:43.910763 INFO: [APUAPC] D13_APC_0: 0xffffffff
10036 00:27:43.914163 INFO: [APUAPC] D13_APC_1: 0xffffffff
10037 00:27:43.917798 INFO: [APUAPC] D13_APC_2: 0x3fffff
10038 00:27:43.920676 INFO: [APUAPC] D13_APC_3: 0x0
10039 00:27:43.924306 INFO: [APUAPC] D14_APC_0: 0xffffffff
10040 00:27:43.927358 INFO: [APUAPC] D14_APC_1: 0xffffffff
10041 00:27:43.930781 INFO: [APUAPC] D14_APC_2: 0x3fffff
10042 00:27:43.934187 INFO: [APUAPC] D14_APC_3: 0x0
10043 00:27:43.937542 INFO: [APUAPC] D15_APC_0: 0xffffffff
10044 00:27:43.940573 INFO: [APUAPC] D15_APC_1: 0xffffffff
10045 00:27:43.943855 INFO: [APUAPC] D15_APC_2: 0x3fffff
10046 00:27:43.947286 INFO: [APUAPC] D15_APC_3: 0x0
10047 00:27:43.950670 INFO: [APUAPC] APC_CON: 0x4
10048 00:27:43.954100 INFO: [NOCDAPC] D0_APC_0: 0x0
10049 00:27:43.957475 INFO: [NOCDAPC] D0_APC_1: 0x0
10050 00:27:43.960423 INFO: [NOCDAPC] D1_APC_0: 0x0
10051 00:27:43.960499 INFO: [NOCDAPC] D1_APC_1: 0xfff
10052 00:27:43.963851 INFO: [NOCDAPC] D2_APC_0: 0x0
10053 00:27:43.967261 INFO: [NOCDAPC] D2_APC_1: 0xfff
10054 00:27:43.970727 INFO: [NOCDAPC] D3_APC_0: 0x0
10055 00:27:43.974088 INFO: [NOCDAPC] D3_APC_1: 0xfff
10056 00:27:43.977164 INFO: [NOCDAPC] D4_APC_0: 0x0
10057 00:27:43.980573 INFO: [NOCDAPC] D4_APC_1: 0xfff
10058 00:27:43.984255 INFO: [NOCDAPC] D5_APC_0: 0x0
10059 00:27:43.987133 INFO: [NOCDAPC] D5_APC_1: 0xfff
10060 00:27:43.990562 INFO: [NOCDAPC] D6_APC_0: 0x0
10061 00:27:43.993974 INFO: [NOCDAPC] D6_APC_1: 0xfff
10062 00:27:43.994050 INFO: [NOCDAPC] D7_APC_0: 0x0
10063 00:27:43.997480 INFO: [NOCDAPC] D7_APC_1: 0xfff
10064 00:27:44.001038 INFO: [NOCDAPC] D8_APC_0: 0x0
10065 00:27:44.003878 INFO: [NOCDAPC] D8_APC_1: 0xfff
10066 00:27:44.007426 INFO: [NOCDAPC] D9_APC_0: 0x0
10067 00:27:44.010650 INFO: [NOCDAPC] D9_APC_1: 0xfff
10068 00:27:44.014253 INFO: [NOCDAPC] D10_APC_0: 0x0
10069 00:27:44.017690 INFO: [NOCDAPC] D10_APC_1: 0xfff
10070 00:27:44.020838 INFO: [NOCDAPC] D11_APC_0: 0x0
10071 00:27:44.023823 INFO: [NOCDAPC] D11_APC_1: 0xfff
10072 00:27:44.027327 INFO: [NOCDAPC] D12_APC_0: 0x0
10073 00:27:44.030656 INFO: [NOCDAPC] D12_APC_1: 0xfff
10074 00:27:44.030732 INFO: [NOCDAPC] D13_APC_0: 0x0
10075 00:27:44.034199 INFO: [NOCDAPC] D13_APC_1: 0xfff
10076 00:27:44.037712 INFO: [NOCDAPC] D14_APC_0: 0x0
10077 00:27:44.040519 INFO: [NOCDAPC] D14_APC_1: 0xfff
10078 00:27:44.043915 INFO: [NOCDAPC] D15_APC_0: 0x0
10079 00:27:44.047558 INFO: [NOCDAPC] D15_APC_1: 0xfff
10080 00:27:44.050511 INFO: [NOCDAPC] APC_CON: 0x4
10081 00:27:44.053829 INFO: [APUAPC] set_apusys_apc done
10082 00:27:44.057640 INFO: [DEVAPC] devapc_init done
10083 00:27:44.060669 INFO: GICv3 without legacy support detected.
10084 00:27:44.064107 INFO: ARM GICv3 driver initialized in EL3
10085 00:27:44.067589 INFO: Maximum SPI INTID supported: 639
10086 00:27:44.074203 INFO: BL31: Initializing runtime services
10087 00:27:44.077298 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10088 00:27:44.080785 INFO: SPM: enable CPC mode
10089 00:27:44.087473 INFO: mcdi ready for mcusys-off-idle and system suspend
10090 00:27:44.090659 INFO: BL31: Preparing for EL3 exit to normal world
10091 00:27:44.094016 INFO: Entry point address = 0x80000000
10092 00:27:44.097645 INFO: SPSR = 0x8
10093 00:27:44.102706
10094 00:27:44.102781
10095 00:27:44.102840
10096 00:27:44.106171 Starting depthcharge on Spherion...
10097 00:27:44.106247
10098 00:27:44.106306 Wipe memory regions:
10099 00:27:44.106361
10100 00:27:44.106977 end: 2.2.3 depthcharge-start (duration 00:00:31) [common]
10101 00:27:44.107072 start: 2.2.4 bootloader-commands (timeout 00:04:20) [common]
10102 00:27:44.107142 Setting prompt string to ['asurada:']
10103 00:27:44.107216 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:20)
10104 00:27:44.109146 [0x00000040000000, 0x00000054600000)
10105 00:27:44.231456
10106 00:27:44.231552 [0x00000054660000, 0x00000080000000)
10107 00:27:44.491970
10108 00:27:44.492090 [0x000000821a7280, 0x000000ffe64000)
10109 00:27:45.236877
10110 00:27:45.236997 [0x00000100000000, 0x00000240000000)
10111 00:27:47.127031
10112 00:27:47.130272 Initializing XHCI USB controller at 0x11200000.
10113 00:27:48.168665
10114 00:27:48.171675 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10115 00:27:48.171758
10116 00:27:48.171819
10117 00:27:48.172087 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10119 00:27:48.272434 asurada: tftpboot 192.168.201.1 14479216/tftp-deploy-t4ydc2e7/kernel/image.itb 14479216/tftp-deploy-t4ydc2e7/kernel/cmdline
10120 00:27:48.272603 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10121 00:27:48.272686 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:16)
10122 00:27:48.276780 tftpboot 192.168.201.1 14479216/tftp-deploy-t4ydc2e7/kernel/image.ittp-deploy-t4ydc2e7/kernel/cmdline
10123 00:27:48.276859
10124 00:27:48.276919 Waiting for link
10125 00:27:48.434937
10126 00:27:48.435042 R8152: Initializing
10127 00:27:48.435106
10128 00:27:48.438002 Version 9 (ocp_data = 6010)
10129 00:27:48.438079
10130 00:27:48.441369 R8152: Done initializing
10131 00:27:48.441446
10132 00:27:48.441505 Adding net device
10133 00:27:50.389913
10134 00:27:50.390030 done.
10135 00:27:50.390092
10136 00:27:50.390149 MAC: 00:e0:4c:72:2d:d6
10137 00:27:50.390204
10138 00:27:50.393358 Sending DHCP discover... done.
10139 00:27:50.393437
10140 00:27:50.396643 Waiting for reply... done.
10141 00:27:50.396761
10142 00:27:50.399803 Sending DHCP request... done.
10143 00:27:50.399880
10144 00:27:50.399940 Waiting for reply... done.
10145 00:27:50.399996
10146 00:27:50.403333 My ip is 192.168.201.21
10147 00:27:50.403409
10148 00:27:50.406857 The DHCP server ip is 192.168.201.1
10149 00:27:50.406934
10150 00:27:50.410023 TFTP server IP predefined by user: 192.168.201.1
10151 00:27:50.410100
10152 00:27:50.416696 Bootfile predefined by user: 14479216/tftp-deploy-t4ydc2e7/kernel/image.itb
10153 00:27:50.416811
10154 00:27:50.419757 Sending tftp read request... done.
10155 00:27:50.419833
10156 00:27:50.423227 Waiting for the transfer...
10157 00:27:50.423307
10158 00:27:50.685003 00000000 ################################################################
10159 00:27:50.685120
10160 00:27:50.929913 00080000 ################################################################
10161 00:27:50.930029
10162 00:27:51.177705 00100000 ################################################################
10163 00:27:51.177817
10164 00:27:51.420018 00180000 ################################################################
10165 00:27:51.420133
10166 00:27:51.664405 00200000 ################################################################
10167 00:27:51.664526
10168 00:27:51.906769 00280000 ################################################################
10169 00:27:51.906898
10170 00:27:52.155316 00300000 ################################################################
10171 00:27:52.155432
10172 00:27:52.406254 00380000 ################################################################
10173 00:27:52.406364
10174 00:27:52.647549 00400000 ################################################################
10175 00:27:52.647691
10176 00:27:52.888017 00480000 ################################################################
10177 00:27:52.888128
10178 00:27:53.137146 00500000 ################################################################
10179 00:27:53.137281
10180 00:27:53.398911 00580000 ################################################################
10181 00:27:53.399048
10182 00:27:53.652542 00600000 ################################################################
10183 00:27:53.652670
10184 00:27:53.896039 00680000 ################################################################
10185 00:27:53.896166
10186 00:27:54.146250 00700000 ################################################################
10187 00:27:54.146371
10188 00:27:54.397061 00780000 ################################################################
10189 00:27:54.397177
10190 00:27:54.664344 00800000 ################################################################
10191 00:27:54.664463
10192 00:27:54.928454 00880000 ################################################################
10193 00:27:54.928570
10194 00:27:55.198602 00900000 ################################################################
10195 00:27:55.198752
10196 00:27:55.455974 00980000 ################################################################
10197 00:27:55.456090
10198 00:27:55.717609 00a00000 ################################################################
10199 00:27:55.717733
10200 00:27:55.969191 00a80000 ################################################################
10201 00:27:55.969322
10202 00:27:56.221992 00b00000 ################################################################
10203 00:27:56.222103
10204 00:27:56.476411 00b80000 ################################################################
10205 00:27:56.476529
10206 00:27:56.731003 00c00000 ################################################################
10207 00:27:56.731120
10208 00:27:56.982224 00c80000 ################################################################
10209 00:27:56.982372
10210 00:27:57.235444 00d00000 ################################################################
10211 00:27:57.235562
10212 00:27:57.484906 00d80000 ################################################################
10213 00:27:57.485041
10214 00:27:57.735939 00e00000 ################################################################
10215 00:27:57.736058
10216 00:27:57.989067 00e80000 ################################################################
10217 00:27:57.989184
10218 00:27:58.259815 00f00000 ################################################################
10219 00:27:58.259923
10220 00:27:58.506706 00f80000 ################################################################
10221 00:27:58.506847
10222 00:27:58.757667 01000000 ################################################################
10223 00:27:58.757783
10224 00:27:59.024897 01080000 ################################################################
10225 00:27:59.025045
10226 00:27:59.285564 01100000 ################################################################
10227 00:27:59.285672
10228 00:27:59.537492 01180000 ################################################################
10229 00:27:59.537608
10230 00:27:59.789452 01200000 ################################################################
10231 00:27:59.789582
10232 00:28:00.043775 01280000 ################################################################
10233 00:28:00.043890
10234 00:28:00.297987 01300000 ################################################################
10235 00:28:00.298102
10236 00:28:00.552632 01380000 ################################################################
10237 00:28:00.552821
10238 00:28:00.802864 01400000 ################################################################
10239 00:28:00.803020
10240 00:28:01.064524 01480000 ################################################################
10241 00:28:01.064668
10242 00:28:01.315976 01500000 ################################################################
10243 00:28:01.316092
10244 00:28:01.571246 01580000 ################################################################
10245 00:28:01.571373
10246 00:28:01.823543 01600000 ################################################################
10247 00:28:01.823683
10248 00:28:02.075068 01680000 ################################################################
10249 00:28:02.075219
10250 00:28:02.324426 01700000 ################################################################
10251 00:28:02.324567
10252 00:28:02.575564 01780000 ################################################################
10253 00:28:02.575699
10254 00:28:02.828839 01800000 ################################################################
10255 00:28:02.828979
10256 00:28:03.109793 01880000 ################################################################
10257 00:28:03.109908
10258 00:28:03.377639 01900000 ################################################################
10259 00:28:03.377749
10260 00:28:03.678680 01980000 ################################################################
10261 00:28:03.678819
10262 00:28:03.972791 01a00000 ################################################################
10263 00:28:03.972904
10264 00:28:04.270546 01a80000 ################################################################
10265 00:28:04.270659
10266 00:28:04.568310 01b00000 ################################################################
10267 00:28:04.568440
10268 00:28:04.859164 01b80000 ################################################################
10269 00:28:04.859296
10270 00:28:05.159919 01c00000 ################################################################
10271 00:28:05.160034
10272 00:28:05.432015 01c80000 ################################################################
10273 00:28:05.432136
10274 00:28:05.703670 01d00000 ################################################################
10275 00:28:05.703804
10276 00:28:05.967919 01d80000 ################################################################
10277 00:28:05.968041
10278 00:28:06.195877 01e00000 ######################################################### done.
10279 00:28:06.195989
10280 00:28:06.198719 The bootfile was 31921806 bytes long.
10281 00:28:06.198799
10282 00:28:06.202313 Sending tftp read request... done.
10283 00:28:06.202395
10284 00:28:06.202477 Waiting for the transfer...
10285 00:28:06.202536
10286 00:28:06.205959 00000000 # done.
10287 00:28:06.206046
10288 00:28:06.211960 Command line loaded dynamically from TFTP file: 14479216/tftp-deploy-t4ydc2e7/kernel/cmdline
10289 00:28:06.212038
10290 00:28:06.235400 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14479216/extract-nfsrootfs-72fyp65p,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10291 00:28:06.235517
10292 00:28:06.235612 Loading FIT.
10293 00:28:06.235701
10294 00:28:06.238387 Image ramdisk-1 has 18747625 bytes.
10295 00:28:06.238468
10296 00:28:06.241807 Image fdt-1 has 47258 bytes.
10297 00:28:06.241879
10298 00:28:06.245218 Image kernel-1 has 13124896 bytes.
10299 00:28:06.245289
10300 00:28:06.255225 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10301 00:28:06.255313
10302 00:28:06.271530 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10303 00:28:06.271605
10304 00:28:06.278419 Choosing best match conf-1 for compat google,spherion-rev2.
10305 00:28:06.278491
10306 00:28:06.286054 Connected to device vid:did:rid of 1ae0:0028:00
10307 00:28:06.294230
10308 00:28:06.297842 tpm_get_response: command 0x17b, return code 0x0
10309 00:28:06.297920
10310 00:28:06.301329 ec_init: CrosEC protocol v3 supported (256, 248)
10311 00:28:06.304666
10312 00:28:06.308117 tpm_cleanup: add release locality here.
10313 00:28:06.308206
10314 00:28:06.308275 Shutting down all USB controllers.
10315 00:28:06.311290
10316 00:28:06.311379 Removing current net device
10317 00:28:06.311448
10318 00:28:06.318454 Exiting depthcharge with code 4 at timestamp: 51546192
10319 00:28:06.318561
10320 00:28:06.321684 LZMA decompressing kernel-1 to 0x821a6718
10321 00:28:06.321800
10322 00:28:06.324558 LZMA decompressing kernel-1 to 0x40000000
10323 00:28:07.942189
10324 00:28:07.942708 jumping to kernel
10325 00:28:07.944443 end: 2.2.4 bootloader-commands (duration 00:00:24) [common]
10326 00:28:07.944969 start: 2.2.5 auto-login-action (timeout 00:03:56) [common]
10327 00:28:07.945361 Setting prompt string to ['Linux version [0-9]']
10328 00:28:07.945721 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10329 00:28:07.946085 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10330 00:28:08.024576
10331 00:28:08.028113 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10332 00:28:08.031609 start: 2.2.5.1 login-action (timeout 00:03:56) [common]
10333 00:28:08.031727 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10334 00:28:08.031813 Setting prompt string to []
10335 00:28:08.031906 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10336 00:28:08.031991 Using line separator: #'\n'#
10337 00:28:08.032081 No login prompt set.
10338 00:28:08.032154 Parsing kernel messages
10339 00:28:08.032252 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10340 00:28:08.032383 [login-action] Waiting for messages, (timeout 00:03:56)
10341 00:28:08.032472 Waiting using forced prompt support (timeout 00:01:58)
10342 00:28:08.051285 [ 0.000000] Linux version 6.1.94-cip23 (KernelCI@build-j239242-arm64-gcc-10-defconfig-arm64-chromebook-c5lwc) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Jun 21 00:04:56 UTC 2024
10343 00:28:08.054410 [ 0.000000] random: crng init done
10344 00:28:08.060943 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10345 00:28:08.064545 [ 0.000000] efi: UEFI not found.
10346 00:28:08.070746 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10347 00:28:08.078060 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10348 00:28:08.087818 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10349 00:28:08.097553 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10350 00:28:08.104070 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10351 00:28:08.110776 [ 0.000000] printk: bootconsole [mtk8250] enabled
10352 00:28:08.117355 [ 0.000000] NUMA: No NUMA configuration found
10353 00:28:08.123861 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10354 00:28:08.127402 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10355 00:28:08.130459 [ 0.000000] Zone ranges:
10356 00:28:08.137335 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10357 00:28:08.140491 [ 0.000000] DMA32 empty
10358 00:28:08.147501 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10359 00:28:08.150930 [ 0.000000] Movable zone start for each node
10360 00:28:08.153780 [ 0.000000] Early memory node ranges
10361 00:28:08.160342 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10362 00:28:08.167200 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10363 00:28:08.173617 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10364 00:28:08.180759 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10365 00:28:08.187153 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10366 00:28:08.193594 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10367 00:28:08.249775 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10368 00:28:08.256329 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10369 00:28:08.262398 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10370 00:28:08.265605 [ 0.000000] psci: probing for conduit method from DT.
10371 00:28:08.272445 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10372 00:28:08.275609 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10373 00:28:08.282534 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10374 00:28:08.285491 [ 0.000000] psci: SMC Calling Convention v1.2
10375 00:28:08.292221 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10376 00:28:08.296313 [ 0.000000] Detected VIPT I-cache on CPU0
10377 00:28:08.302814 [ 0.000000] CPU features: detected: GIC system register CPU interface
10378 00:28:08.309199 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10379 00:28:08.315837 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10380 00:28:08.322537 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10381 00:28:08.331766 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10382 00:28:08.338811 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10383 00:28:08.341709 [ 0.000000] alternatives: applying boot alternatives
10384 00:28:08.348487 [ 0.000000] Fallback order for Node 0: 0
10385 00:28:08.354839 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10386 00:28:08.358048 [ 0.000000] Policy zone: Normal
10387 00:28:08.380936 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14479216/extract-nfsrootfs-72fyp65p,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10388 00:28:08.391066 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10389 00:28:08.401894 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10390 00:28:08.411409 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10391 00:28:08.418177 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10392 00:28:08.421657 <6>[ 0.000000] software IO TLB: area num 8.
10393 00:28:08.478428 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10394 00:28:08.627930 <6>[ 0.000000] Memory: 7945748K/8385536K available (18112K kernel code, 4120K rwdata, 22648K rodata, 8512K init, 616K bss, 407020K reserved, 32768K cma-reserved)
10395 00:28:08.634666 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10396 00:28:08.640840 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10397 00:28:08.644227 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10398 00:28:08.650509 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10399 00:28:08.656948 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10400 00:28:08.660526 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10401 00:28:08.670564 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10402 00:28:08.676995 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10403 00:28:08.683122 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10404 00:28:08.690046 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10405 00:28:08.693124 <6>[ 0.000000] GICv3: 608 SPIs implemented
10406 00:28:08.696694 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10407 00:28:08.703183 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10408 00:28:08.706775 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10409 00:28:08.713311 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10410 00:28:08.726262 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10411 00:28:08.739299 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10412 00:28:08.746084 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10413 00:28:08.753671 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10414 00:28:08.767092 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10415 00:28:08.773839 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10416 00:28:08.780382 <6>[ 0.009186] Console: colour dummy device 80x25
10417 00:28:08.790150 <6>[ 0.013915] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10418 00:28:08.797010 <6>[ 0.024356] pid_max: default: 32768 minimum: 301
10419 00:28:08.800075 <6>[ 0.029220] LSM: Security Framework initializing
10420 00:28:08.806678 <6>[ 0.034157] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10421 00:28:08.816648 <6>[ 0.041971] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10422 00:28:08.823442 <6>[ 0.051391] cblist_init_generic: Setting adjustable number of callback queues.
10423 00:28:08.830388 <6>[ 0.058834] cblist_init_generic: Setting shift to 3 and lim to 1.
10424 00:28:08.840445 <6>[ 0.065172] cblist_init_generic: Setting adjustable number of callback queues.
10425 00:28:08.843496 <6>[ 0.072645] cblist_init_generic: Setting shift to 3 and lim to 1.
10426 00:28:08.850003 <6>[ 0.079048] rcu: Hierarchical SRCU implementation.
10427 00:28:08.856672 <6>[ 0.084063] rcu: Max phase no-delay instances is 1000.
10428 00:28:08.863227 <6>[ 0.091097] EFI services will not be available.
10429 00:28:08.866571 <6>[ 0.096054] smp: Bringing up secondary CPUs ...
10430 00:28:08.874461 <6>[ 0.101104] Detected VIPT I-cache on CPU1
10431 00:28:08.881267 <6>[ 0.101175] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10432 00:28:08.887742 <6>[ 0.101206] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10433 00:28:08.890668 <6>[ 0.101549] Detected VIPT I-cache on CPU2
10434 00:28:08.897727 <6>[ 0.101602] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10435 00:28:08.907434 <6>[ 0.101620] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10436 00:28:08.910731 <6>[ 0.101882] Detected VIPT I-cache on CPU3
10437 00:28:08.917356 <6>[ 0.101929] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10438 00:28:08.924244 <6>[ 0.101942] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10439 00:28:08.927193 <6>[ 0.102247] CPU features: detected: Spectre-v4
10440 00:28:08.933997 <6>[ 0.102253] CPU features: detected: Spectre-BHB
10441 00:28:08.937366 <6>[ 0.102259] Detected PIPT I-cache on CPU4
10442 00:28:08.944036 <6>[ 0.102318] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10443 00:28:08.950704 <6>[ 0.102334] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10444 00:28:08.957410 <6>[ 0.102630] Detected PIPT I-cache on CPU5
10445 00:28:08.963637 <6>[ 0.102693] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10446 00:28:08.970111 <6>[ 0.102709] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10447 00:28:08.973945 <6>[ 0.102990] Detected PIPT I-cache on CPU6
10448 00:28:08.980467 <6>[ 0.103054] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10449 00:28:08.986808 <6>[ 0.103070] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10450 00:28:08.993647 <6>[ 0.103369] Detected PIPT I-cache on CPU7
10451 00:28:09.000269 <6>[ 0.103435] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10452 00:28:09.007014 <6>[ 0.103451] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10453 00:28:09.010286 <6>[ 0.103499] smp: Brought up 1 node, 8 CPUs
10454 00:28:09.017041 <6>[ 0.244795] SMP: Total of 8 processors activated.
10455 00:28:09.020570 <6>[ 0.249716] CPU features: detected: 32-bit EL0 Support
10456 00:28:09.030207 <6>[ 0.255080] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10457 00:28:09.036572 <6>[ 0.263881] CPU features: detected: Common not Private translations
10458 00:28:09.040091 <6>[ 0.270357] CPU features: detected: CRC32 instructions
10459 00:28:09.046856 <6>[ 0.275742] CPU features: detected: RCpc load-acquire (LDAPR)
10460 00:28:09.053810 <6>[ 0.281739] CPU features: detected: LSE atomic instructions
10461 00:28:09.060023 <6>[ 0.287556] CPU features: detected: Privileged Access Never
10462 00:28:09.063322 <6>[ 0.293336] CPU features: detected: RAS Extension Support
10463 00:28:09.073271 <6>[ 0.298980] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10464 00:28:09.076714 <6>[ 0.306198] CPU: All CPU(s) started at EL2
10465 00:28:09.082955 <6>[ 0.310514] alternatives: applying system-wide alternatives
10466 00:28:09.092300 <6>[ 0.321376] devtmpfs: initialized
10467 00:28:09.108156 <6>[ 0.330359] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10468 00:28:09.114570 <6>[ 0.340319] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10469 00:28:09.117879 <6>[ 0.348026] pinctrl core: initialized pinctrl subsystem
10470 00:28:09.125802 <6>[ 0.354709] DMI not present or invalid.
10471 00:28:09.132248 <6>[ 0.359123] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10472 00:28:09.138937 <6>[ 0.365988] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10473 00:28:09.148977 <6>[ 0.373574] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10474 00:28:09.155612 <6>[ 0.381795] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10475 00:28:09.162013 <6>[ 0.390037] audit: initializing netlink subsys (disabled)
10476 00:28:09.168538 <5>[ 0.395728] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10477 00:28:09.175650 <6>[ 0.396448] thermal_sys: Registered thermal governor 'step_wise'
10478 00:28:09.181944 <6>[ 0.403694] thermal_sys: Registered thermal governor 'power_allocator'
10479 00:28:09.188345 <6>[ 0.409948] cpuidle: using governor menu
10480 00:28:09.191683 <6>[ 0.420907] NET: Registered PF_QIPCRTR protocol family
10481 00:28:09.198566 <6>[ 0.426391] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10482 00:28:09.205564 <6>[ 0.433496] ASID allocator initialised with 32768 entries
10483 00:28:09.211665 <6>[ 0.440078] Serial: AMBA PL011 UART driver
10484 00:28:09.219949 <4>[ 0.448923] Trying to register duplicate clock ID: 134
10485 00:28:09.278881 <6>[ 0.510570] KASLR enabled
10486 00:28:09.293155 <6>[ 0.518342] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10487 00:28:09.299733 <6>[ 0.525355] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10488 00:28:09.306336 <6>[ 0.531844] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10489 00:28:09.312876 <6>[ 0.538849] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10490 00:28:09.319684 <6>[ 0.545339] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10491 00:28:09.326347 <6>[ 0.552342] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10492 00:28:09.332678 <6>[ 0.558829] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10493 00:28:09.339178 <6>[ 0.565833] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10494 00:28:09.342461 <6>[ 0.573349] ACPI: Interpreter disabled.
10495 00:28:09.351221 <6>[ 0.579770] iommu: Default domain type: Translated
10496 00:28:09.357675 <6>[ 0.584884] iommu: DMA domain TLB invalidation policy: strict mode
10497 00:28:09.361197 <5>[ 0.591543] SCSI subsystem initialized
10498 00:28:09.367629 <6>[ 0.595706] usbcore: registered new interface driver usbfs
10499 00:28:09.374294 <6>[ 0.601440] usbcore: registered new interface driver hub
10500 00:28:09.377408 <6>[ 0.606993] usbcore: registered new device driver usb
10501 00:28:09.384599 <6>[ 0.613093] pps_core: LinuxPPS API ver. 1 registered
10502 00:28:09.394387 <6>[ 0.618287] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10503 00:28:09.397845 <6>[ 0.627636] PTP clock support registered
10504 00:28:09.400655 <6>[ 0.631879] EDAC MC: Ver: 3.0.0
10505 00:28:09.408657 <6>[ 0.637039] FPGA manager framework
10506 00:28:09.415026 <6>[ 0.640728] Advanced Linux Sound Architecture Driver Initialized.
10507 00:28:09.418768 <6>[ 0.647505] vgaarb: loaded
10508 00:28:09.424955 <6>[ 0.650659] clocksource: Switched to clocksource arch_sys_counter
10509 00:28:09.428385 <5>[ 0.657097] VFS: Disk quotas dquot_6.6.0
10510 00:28:09.434781 <6>[ 0.661281] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10511 00:28:09.438415 <6>[ 0.668469] pnp: PnP ACPI: disabled
10512 00:28:09.446659 <6>[ 0.675174] NET: Registered PF_INET protocol family
10513 00:28:09.456865 <6>[ 0.680765] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10514 00:28:09.467987 <6>[ 0.693082] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10515 00:28:09.477619 <6>[ 0.701897] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10516 00:28:09.484524 <6>[ 0.709870] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10517 00:28:09.490986 <6>[ 0.718573] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10518 00:28:09.502856 <6>[ 0.728330] TCP: Hash tables configured (established 65536 bind 65536)
10519 00:28:09.509663 <6>[ 0.735197] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10520 00:28:09.516106 <6>[ 0.742396] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10521 00:28:09.522864 <6>[ 0.750072] NET: Registered PF_UNIX/PF_LOCAL protocol family
10522 00:28:09.529344 <6>[ 0.756225] RPC: Registered named UNIX socket transport module.
10523 00:28:09.533135 <6>[ 0.762379] RPC: Registered udp transport module.
10524 00:28:09.539172 <6>[ 0.767313] RPC: Registered tcp transport module.
10525 00:28:09.545495 <6>[ 0.772246] RPC: Registered tcp NFSv4.1 backchannel transport module.
10526 00:28:09.548876 <6>[ 0.778912] PCI: CLS 0 bytes, default 64
10527 00:28:09.552572 <6>[ 0.783248] Unpacking initramfs...
10528 00:28:09.577966 <6>[ 0.802758] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10529 00:28:09.587704 <6>[ 0.811434] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10530 00:28:09.591111 <6>[ 0.820287] kvm [1]: IPA Size Limit: 40 bits
10531 00:28:09.597186 <6>[ 0.824815] kvm [1]: GICv3: no GICV resource entry
10532 00:28:09.600665 <6>[ 0.829836] kvm [1]: disabling GICv2 emulation
10533 00:28:09.607901 <6>[ 0.834524] kvm [1]: GIC system register CPU interface enabled
10534 00:28:09.610398 <6>[ 0.840699] kvm [1]: vgic interrupt IRQ18
10535 00:28:09.617272 <6>[ 0.845056] kvm [1]: VHE mode initialized successfully
10536 00:28:09.623834 <5>[ 0.851451] Initialise system trusted keyrings
10537 00:28:09.630580 <6>[ 0.856290] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10538 00:28:09.638225 <6>[ 0.866373] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10539 00:28:09.644355 <5>[ 0.872791] NFS: Registering the id_resolver key type
10540 00:28:09.647925 <5>[ 0.878093] Key type id_resolver registered
10541 00:28:09.654018 <5>[ 0.882507] Key type id_legacy registered
10542 00:28:09.661018 <6>[ 0.886786] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10543 00:28:09.667715 <6>[ 0.893708] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10544 00:28:09.674554 <6>[ 0.901420] 9p: Installing v9fs 9p2000 file system support
10545 00:28:09.711254 <5>[ 0.939525] Key type asymmetric registered
10546 00:28:09.714412 <5>[ 0.943855] Asymmetric key parser 'x509' registered
10547 00:28:09.724256 <6>[ 0.948991] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10548 00:28:09.727395 <6>[ 0.956609] io scheduler mq-deadline registered
10549 00:28:09.730619 <6>[ 0.961388] io scheduler kyber registered
10550 00:28:09.749338 <6>[ 0.978209] EINJ: ACPI disabled.
10551 00:28:09.781811 <4>[ 1.004234] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10552 00:28:09.791608 <4>[ 1.014846] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10553 00:28:09.806388 <6>[ 1.035569] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10554 00:28:09.814551 <6>[ 1.043606] printk: console [ttyS0] disabled
10555 00:28:09.843453 <6>[ 1.068245] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10556 00:28:09.849766 <6>[ 1.077714] printk: console [ttyS0] enabled
10557 00:28:09.852575 <6>[ 1.077714] printk: console [ttyS0] enabled
10558 00:28:09.859827 <6>[ 1.086607] printk: bootconsole [mtk8250] disabled
10559 00:28:09.862890 <6>[ 1.086607] printk: bootconsole [mtk8250] disabled
10560 00:28:09.869499 <6>[ 1.097618] SuperH (H)SCI(F) driver initialized
10561 00:28:09.872870 <6>[ 1.102907] msm_serial: driver initialized
10562 00:28:09.885889 <6>[ 1.111799] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10563 00:28:09.896077 <6>[ 1.120346] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10564 00:28:09.902466 <6>[ 1.128888] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10565 00:28:09.912498 <6>[ 1.137515] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10566 00:28:09.922599 <6>[ 1.146222] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10567 00:28:09.929129 <6>[ 1.154944] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10568 00:28:09.939143 <6>[ 1.163484] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10569 00:28:09.945626 <6>[ 1.172287] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10570 00:28:09.955748 <6>[ 1.180830] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10571 00:28:09.967739 <6>[ 1.196670] loop: module loaded
10572 00:28:09.974136 <6>[ 1.202625] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10573 00:28:09.997129 <4>[ 1.226178] mtk-pmic-keys: Failed to locate of_node [id: -1]
10574 00:28:10.003730 <6>[ 1.233062] megasas: 07.719.03.00-rc1
10575 00:28:10.013523 <6>[ 1.242604] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10576 00:28:10.021002 <6>[ 1.250071] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10577 00:28:10.037892 <6>[ 1.266762] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10578 00:28:10.094601 <6>[ 1.316924] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10579 00:28:10.341018 <6>[ 1.570531] Freeing initrd memory: 18304K
10580 00:28:10.352947 <6>[ 1.582032] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10581 00:28:10.363907 <6>[ 1.593008] tun: Universal TUN/TAP device driver, 1.6
10582 00:28:10.367361 <6>[ 1.599088] thunder_xcv, ver 1.0
10583 00:28:10.370670 <6>[ 1.602586] thunder_bgx, ver 1.0
10584 00:28:10.373631 <6>[ 1.606083] nicpf, ver 1.0
10585 00:28:10.384636 <6>[ 1.610121] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10586 00:28:10.387618 <6>[ 1.617597] hns3: Copyright (c) 2017 Huawei Corporation.
10587 00:28:10.390816 <6>[ 1.623186] hclge is initializing
10588 00:28:10.398044 <6>[ 1.626767] e1000: Intel(R) PRO/1000 Network Driver
10589 00:28:10.404626 <6>[ 1.631896] e1000: Copyright (c) 1999-2006 Intel Corporation.
10590 00:28:10.408065 <6>[ 1.637907] e1000e: Intel(R) PRO/1000 Network Driver
10591 00:28:10.414630 <6>[ 1.643122] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10592 00:28:10.421658 <6>[ 1.649307] igb: Intel(R) Gigabit Ethernet Network Driver
10593 00:28:10.428026 <6>[ 1.654956] igb: Copyright (c) 2007-2014 Intel Corporation.
10594 00:28:10.434396 <6>[ 1.660793] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10595 00:28:10.441527 <6>[ 1.667311] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10596 00:28:10.444317 <6>[ 1.673777] sky2: driver version 1.30
10597 00:28:10.450862 <6>[ 1.678707] usbcore: registered new device driver r8152-cfgselector
10598 00:28:10.458237 <6>[ 1.685242] usbcore: registered new interface driver r8152
10599 00:28:10.461290 <6>[ 1.691060] VFIO - User Level meta-driver version: 0.3
10600 00:28:10.470328 <6>[ 1.699299] usbcore: registered new interface driver usb-storage
10601 00:28:10.477155 <6>[ 1.705742] usbcore: registered new device driver onboard-usb-hub
10602 00:28:10.486298 <6>[ 1.714896] mt6397-rtc mt6359-rtc: registered as rtc0
10603 00:28:10.496388 <6>[ 1.720362] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-21T00:28:10 UTC (1718929690)
10604 00:28:10.499284 <6>[ 1.729926] i2c_dev: i2c /dev entries driver
10605 00:28:10.513082 <4>[ 1.741956] cpu cpu0: supply cpu not found, using dummy regulator
10606 00:28:10.519657 <4>[ 1.748382] cpu cpu1: supply cpu not found, using dummy regulator
10607 00:28:10.526854 <4>[ 1.754789] cpu cpu2: supply cpu not found, using dummy regulator
10608 00:28:10.533081 <4>[ 1.761190] cpu cpu3: supply cpu not found, using dummy regulator
10609 00:28:10.539391 <4>[ 1.767608] cpu cpu4: supply cpu not found, using dummy regulator
10610 00:28:10.546198 <4>[ 1.774027] cpu cpu5: supply cpu not found, using dummy regulator
10611 00:28:10.552934 <4>[ 1.780424] cpu cpu6: supply cpu not found, using dummy regulator
10612 00:28:10.559798 <4>[ 1.786825] cpu cpu7: supply cpu not found, using dummy regulator
10613 00:28:10.579011 <6>[ 1.807462] cpu cpu0: EM: created perf domain
10614 00:28:10.582043 <6>[ 1.812407] cpu cpu4: EM: created perf domain
10615 00:28:10.589505 <6>[ 1.818044] sdhci: Secure Digital Host Controller Interface driver
10616 00:28:10.596328 <6>[ 1.824476] sdhci: Copyright(c) Pierre Ossman
10617 00:28:10.603107 <6>[ 1.829430] Synopsys Designware Multimedia Card Interface Driver
10618 00:28:10.610057 <6>[ 1.836066] sdhci-pltfm: SDHCI platform and OF driver helper
10619 00:28:10.612926 <6>[ 1.836117] mmc0: CQHCI version 5.10
10620 00:28:10.619270 <6>[ 1.846018] ledtrig-cpu: registered to indicate activity on CPUs
10621 00:28:10.625827 <6>[ 1.853155] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10622 00:28:10.632795 <6>[ 1.860203] usbcore: registered new interface driver usbhid
10623 00:28:10.635888 <6>[ 1.866025] usbhid: USB HID core driver
10624 00:28:10.642325 <6>[ 1.870233] spi_master spi0: will run message pump with realtime priority
10625 00:28:10.693219 <6>[ 1.915086] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10626 00:28:10.712105 <6>[ 1.930614] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10627 00:28:10.715743 <6>[ 1.940514] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x17414
10628 00:28:10.722763 <6>[ 1.946456] cros-ec-spi spi0.0: Chrome EC device registered
10629 00:28:10.726178 <6>[ 1.956014] mmc0: Command Queue Engine enabled
10630 00:28:10.732865 <6>[ 1.960749] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10631 00:28:10.739726 <6>[ 1.968177] mmcblk0: mmc0:0001 DA4128 116 GiB
10632 00:28:10.749664 <6>[ 1.971366] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10633 00:28:10.752810 <6>[ 1.976542] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10634 00:28:10.759523 <6>[ 1.983373] NET: Registered PF_PACKET protocol family
10635 00:28:10.765765 <6>[ 1.989558] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10636 00:28:10.769000 <6>[ 1.993485] 9pnet: Installing 9P2000 support
10637 00:28:10.775747 <6>[ 1.999324] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10638 00:28:10.779397 <5>[ 2.003181] Key type dns_resolver registered
10639 00:28:10.785909 <6>[ 2.008996] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10640 00:28:10.789125 <6>[ 2.013402] registered taskstats version 1
10641 00:28:10.795856 <5>[ 2.023775] Loading compiled-in X.509 certificates
10642 00:28:10.822934 <4>[ 2.045448] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10643 00:28:10.832971 <4>[ 2.056161] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10644 00:28:10.847447 <6>[ 2.076260] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10645 00:28:10.854292 <6>[ 2.083205] xhci-mtk 11200000.usb: xHCI Host Controller
10646 00:28:10.861097 <6>[ 2.088742] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10647 00:28:10.870626 <6>[ 2.096602] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10648 00:28:10.877416 <6>[ 2.106032] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10649 00:28:10.884214 <6>[ 2.112210] xhci-mtk 11200000.usb: xHCI Host Controller
10650 00:28:10.890891 <6>[ 2.117701] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10651 00:28:10.897805 <6>[ 2.125367] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10652 00:28:10.904473 <6>[ 2.133160] hub 1-0:1.0: USB hub found
10653 00:28:10.908020 <6>[ 2.137197] hub 1-0:1.0: 1 port detected
10654 00:28:10.914297 <6>[ 2.141490] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10655 00:28:10.921240 <6>[ 2.150153] hub 2-0:1.0: USB hub found
10656 00:28:10.924209 <6>[ 2.154182] hub 2-0:1.0: 1 port detected
10657 00:28:10.932346 <6>[ 2.161529] mtk-msdc 11f70000.mmc: Got CD GPIO
10658 00:28:10.945169 <6>[ 2.170606] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10659 00:28:10.955152 <6>[ 2.178986] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10660 00:28:10.961679 <6>[ 2.187327] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10661 00:28:10.971631 <6>[ 2.195664] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10662 00:28:10.978056 <6>[ 2.204003] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10663 00:28:10.988117 <6>[ 2.212341] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10664 00:28:10.994762 <6>[ 2.220682] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10665 00:28:11.004970 <6>[ 2.229021] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10666 00:28:11.011698 <6>[ 2.237362] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10667 00:28:11.021649 <6>[ 2.245700] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10668 00:28:11.028468 <6>[ 2.254038] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10669 00:28:11.038403 <6>[ 2.262389] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10670 00:28:11.045398 <6>[ 2.270729] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10671 00:28:11.054843 <6>[ 2.279067] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10672 00:28:11.061706 <6>[ 2.287408] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10673 00:28:11.067989 <6>[ 2.296127] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10674 00:28:11.074949 <6>[ 2.303284] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10675 00:28:11.081345 <6>[ 2.310096] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10676 00:28:11.088083 <6>[ 2.316874] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10677 00:28:11.098580 <6>[ 2.323847] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10678 00:28:11.104897 <6>[ 2.330705] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10679 00:28:11.114982 <6>[ 2.339834] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10680 00:28:11.124629 <6>[ 2.348956] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10681 00:28:11.134736 <6>[ 2.358251] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10682 00:28:11.144600 <6>[ 2.367722] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10683 00:28:11.151338 <6>[ 2.377189] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10684 00:28:11.161164 <6>[ 2.386309] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10685 00:28:11.171007 <6>[ 2.395775] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10686 00:28:11.180978 <6>[ 2.404894] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10687 00:28:11.191619 <6>[ 2.414188] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10688 00:28:11.201175 <6>[ 2.424348] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10689 00:28:11.210808 <6>[ 2.436342] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10690 00:28:11.218805 <6>[ 2.447513] Trying to probe devices needed for running init ...
10691 00:28:11.229406 <3>[ 2.454813] mt8192-audio 11210000.syscon:mt8192-afe-pcm: could not get audiosys reset:-517
10692 00:28:11.333426 <6>[ 2.558939] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10693 00:28:11.488377 <6>[ 2.716930] hub 1-1:1.0: USB hub found
10694 00:28:11.491360 <6>[ 2.721452] hub 1-1:1.0: 4 ports detected
10695 00:28:11.503913 <6>[ 2.732410] hub 1-1:1.0: USB hub found
10696 00:28:11.507005 <6>[ 2.736792] hub 1-1:1.0: 4 ports detected
10697 00:28:11.613420 <6>[ 2.839144] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10698 00:28:11.640047 <6>[ 2.868956] hub 2-1:1.0: USB hub found
10699 00:28:11.643138 <6>[ 2.873483] hub 2-1:1.0: 3 ports detected
10700 00:28:11.655753 <6>[ 2.884491] hub 2-1:1.0: USB hub found
10701 00:28:11.658951 <6>[ 2.888935] hub 2-1:1.0: 3 ports detected
10702 00:28:11.829102 <6>[ 3.054981] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10703 00:28:11.961765 <6>[ 3.190407] hub 1-1.4:1.0: USB hub found
10704 00:28:11.964648 <6>[ 3.195031] hub 1-1.4:1.0: 2 ports detected
10705 00:28:11.976248 <6>[ 3.205272] hub 1-1.4:1.0: USB hub found
10706 00:28:11.979408 <6>[ 3.209783] hub 1-1.4:1.0: 2 ports detected
10707 00:28:12.049385 <6>[ 3.275067] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10708 00:28:12.157774 <6>[ 3.383621] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10709 00:28:12.194344 <4>[ 3.420121] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10710 00:28:12.204377 <4>[ 3.429243] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10711 00:28:12.251336 <6>[ 3.480351] r8152 2-1.3:1.0 eth0: v1.12.13
10712 00:28:12.281250 <6>[ 3.506804] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10713 00:28:12.473120 <6>[ 3.698998] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10714 00:28:13.851963 <6>[ 5.081701] r8152 2-1.3:1.0 eth0: carrier on
10715 00:28:16.128848 <5>[ 5.110723] Sending DHCP requests .., OK
10716 00:28:16.135382 <6>[ 7.363016] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.21
10717 00:28:16.138979 <6>[ 7.371308] IP-Config: Complete:
10718 00:28:16.152225 <6>[ 7.374804] device=eth0, hwaddr=00:e0:4c:72:2d:d6, ipaddr=192.168.201.21, mask=255.255.255.0, gw=192.168.201.1
10719 00:28:16.158709 <6>[ 7.385526] host=mt8192-asurada-spherion-r0-cbg-1, domain=lava-rack, nis-domain=(none)
10720 00:28:16.165595 <6>[ 7.394147] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10721 00:28:16.172358 <6>[ 7.394156] nameserver0=192.168.201.1
10722 00:28:16.175390 <6>[ 7.406310] clk: Disabling unused clocks
10723 00:28:16.178732 <6>[ 7.411616] ALSA device list:
10724 00:28:16.185533 <6>[ 7.414934] No soundcards found.
10725 00:28:16.192660 <6>[ 7.422274] Freeing unused kernel memory: 8512K
10726 00:28:16.195784 <6>[ 7.427262] Run /init as init process
10727 00:28:16.205413 Loading, please wait...
10728 00:28:16.233598 Starting systemd-udevd version 252.22-1~deb12u1
10729 00:28:16.512309 <6>[ 7.738270] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10730 00:28:16.518819 <6>[ 7.744067] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10731 00:28:16.528552 <6>[ 7.751758] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10732 00:28:16.535380 <6>[ 7.758058] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10733 00:28:16.541791 <6>[ 7.761770] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10734 00:28:16.548512 <6>[ 7.761841] remoteproc remoteproc0: scp is available
10735 00:28:16.551851 <6>[ 7.761909] remoteproc remoteproc0: powering up scp
10736 00:28:16.561752 <6>[ 7.761915] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10737 00:28:16.568630 <6>[ 7.761943] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10738 00:28:16.575049 <6>[ 7.769578] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10739 00:28:16.585148 <4>[ 7.777543] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10740 00:28:16.594855 <6>[ 7.782428] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10741 00:28:16.601517 <6>[ 7.788187] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10742 00:28:16.611895 <3>[ 7.789144] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10743 00:28:16.617914 <3>[ 7.789162] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10744 00:28:16.628348 <3>[ 7.789171] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10745 00:28:16.634519 <4>[ 7.799945] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10746 00:28:16.641253 <6>[ 7.801820] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10747 00:28:16.651419 <3>[ 7.802031] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10748 00:28:16.657805 <3>[ 7.802044] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10749 00:28:16.667615 <3>[ 7.802048] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10750 00:28:16.674262 <3>[ 7.802059] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10751 00:28:16.684756 <3>[ 7.802064] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10752 00:28:16.687767 <6>[ 7.805480] mc: Linux media interface: v0.10
10753 00:28:16.697438 <3>[ 7.820240] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10754 00:28:16.704073 <4>[ 7.820660] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10755 00:28:16.710391 <6>[ 7.829200] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10756 00:28:16.717599 <6>[ 7.833952] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10757 00:28:16.724261 <6>[ 7.834279] videodev: Linux video capture interface: v2.00
10758 00:28:16.733953 <3>[ 7.837461] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10759 00:28:16.740469 <6>[ 7.845234] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10760 00:28:16.750555 <3>[ 7.853684] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10761 00:28:16.757086 <6>[ 7.861519] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10762 00:28:16.767171 <6>[ 7.861527] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10763 00:28:16.773647 <6>[ 7.920085] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10764 00:28:16.780149 <3>[ 7.922591] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10765 00:28:16.787028 <6>[ 7.922622] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10766 00:28:16.796730 <6>[ 7.922670] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10767 00:28:16.803370 <6>[ 7.922681] remoteproc remoteproc0: remote processor scp is now up
10768 00:28:16.813429 <6>[ 7.925315] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10769 00:28:16.823859 <6>[ 7.925902] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10770 00:28:16.826840 <6>[ 7.930633] pci_bus 0000:00: root bus resource [bus 00-ff]
10771 00:28:16.836965 <6>[ 7.932876] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10772 00:28:16.843423 <6>[ 7.936291] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10773 00:28:16.853153 <3>[ 7.938353] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10774 00:28:16.860074 <6>[ 7.945837] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10775 00:28:16.869668 <6>[ 7.945841] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10776 00:28:16.879390 <6>[ 7.951259] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10777 00:28:16.886207 <3>[ 7.953569] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10778 00:28:16.893112 <6>[ 7.959870] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10779 00:28:16.899557 <3>[ 7.967330] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10780 00:28:16.909620 <6>[ 7.975470] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10781 00:28:16.916164 <3>[ 7.983722] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10782 00:28:16.919549 <6>[ 7.984231] Bluetooth: Core ver 2.22
10783 00:28:16.926108 <6>[ 7.984298] NET: Registered PF_BLUETOOTH protocol family
10784 00:28:16.932657 <6>[ 7.984300] Bluetooth: HCI device and connection manager initialized
10785 00:28:16.938970 <6>[ 7.984318] Bluetooth: HCI socket layer initialized
10786 00:28:16.942828 <6>[ 7.984322] Bluetooth: L2CAP socket layer initialized
10787 00:28:16.949309 <6>[ 7.984329] Bluetooth: SCO socket layer initialized
10788 00:28:16.952723 <6>[ 7.991469] pci 0000:00:00.0: supports D1 D2
10789 00:28:16.959366 <3>[ 8.000524] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10790 00:28:16.969396 <6>[ 8.001430] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10791 00:28:16.979088 <6>[ 8.002474] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10792 00:28:16.985356 <6>[ 8.002558] usbcore: registered new interface driver uvcvideo
10793 00:28:16.991987 <6>[ 8.007379] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10794 00:28:17.002120 <3>[ 8.015513] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10795 00:28:17.008894 <6>[ 8.023771] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10796 00:28:17.018372 <4>[ 8.031023] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10797 00:28:17.021719 <4>[ 8.031023] Fallback method does not support PEC.
10798 00:28:17.028385 <6>[ 8.031803] usbcore: registered new interface driver btusb
10799 00:28:17.038125 <4>[ 8.032844] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10800 00:28:17.045371 <3>[ 8.032855] Bluetooth: hci0: Failed to load firmware file (-2)
10801 00:28:17.051547 <3>[ 8.032858] Bluetooth: hci0: Failed to set up firmware (-2)
10802 00:28:17.061723 <4>[ 8.032861] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10803 00:28:17.068096 <6>[ 8.037582] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10804 00:28:17.074525 <6>[ 8.048199] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10805 00:28:17.081920 <6>[ 8.056576] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10806 00:28:17.088259 <6>[ 8.316308] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10807 00:28:17.098296 <6>[ 8.323795] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10808 00:28:17.101387 <6>[ 8.331372] pci 0000:01:00.0: supports D1 D2
10809 00:28:17.108331 <6>[ 8.335891] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10810 00:28:17.132783 <6>[ 8.358977] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10811 00:28:17.139520 <6>[ 8.365894] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10812 00:28:17.145789 <6>[ 8.373974] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10813 00:28:17.155975 <6>[ 8.381972] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10814 00:28:17.162520 <6>[ 8.389973] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10815 00:28:17.172396 <6>[ 8.397974] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10816 00:28:17.175638 <6>[ 8.405976] pci 0000:00:00.0: PCI bridge to [bus 01]
10817 00:28:17.185879 <6>[ 8.411192] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10818 00:28:17.191958 <6>[ 8.419309] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10819 00:28:17.198810 <6>[ 8.426163] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10820 00:28:17.205322 <6>[ 8.432952] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10821 00:28:17.219759 <5>[ 8.446225] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10822 00:28:17.245231 <5>[ 8.470852] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10823 00:28:17.251173 <5>[ 8.478346] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10824 00:28:17.261052 <4>[ 8.486922] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10825 00:28:17.267944 <6>[ 8.495880] cfg80211: failed to load regulatory.db
10826 00:28:17.314763 <6>[ 8.541153] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10827 00:28:17.321626 <6>[ 8.548661] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10828 00:28:17.345766 <6>[ 8.575372] mt7921e 0000:01:00.0: ASIC revision: 79610010
10829 00:28:17.449212 <6>[ 8.675586] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10830 00:28:17.452467 <6>[ 8.675586]
10831 00:28:17.459577 Begin: Loading essential drivers ... done.
10832 00:28:17.462914 Begin: Running /scripts/init-premount ... done.
10833 00:28:17.469514 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10834 00:28:17.479218 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10835 00:28:17.482735 Device /sys/class/net/eth0 found
10836 00:28:17.483129 done.
10837 00:28:17.489598 Begin: Waiting up to 180 secs for any network device to become available ... done.
10838 00:28:17.513087 IP-Config: eth0 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10839 00:28:17.520108 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10840 00:28:17.526734 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10841 00:28:17.532982 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10842 00:28:17.540128 host : mt8192-asurada-spherion-r0-cbg-1
10843 00:28:17.546421 domain : lava-rack
10844 00:28:17.549770 rootserver: 192.168.201.1 rootpath:
10845 00:28:17.550225 filename :
10846 00:28:17.569252 done.
10847 00:28:17.576751 Begin: Running /scripts/nfs-bottom ... done.
10848 00:28:17.590035 Begin: Running /scripts/init-bottom ... done.
10849 00:28:17.716653 <6>[ 8.942856] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10850 00:28:18.907258 <6>[ 10.137449] NET: Registered PF_INET6 protocol family
10851 00:28:18.914792 <6>[ 10.144909] Segment Routing with IPv6
10852 00:28:18.917805 <6>[ 10.148900] In-situ OAM (IOAM) with IPv6
10853 00:28:19.081453 <30>[ 10.285212] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10854 00:28:19.088489 <30>[ 10.318401] systemd[1]: Detected architecture arm64.
10855 00:28:19.095515
10856 00:28:19.098493 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10857 00:28:19.098584
10858 00:28:19.122731 <30>[ 10.352097] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10859 00:28:20.147506 <30>[ 11.373894] systemd[1]: Queued start job for default target graphical.target.
10860 00:28:20.201454 <30>[ 11.427760] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10861 00:28:20.208212 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10862 00:28:20.230451 <30>[ 11.456726] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10863 00:28:20.239771 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10864 00:28:20.258282 <30>[ 11.484661] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10865 00:28:20.268296 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10866 00:28:20.286766 <30>[ 11.513066] systemd[1]: Created slice user.slice - User and Session Slice.
10867 00:28:20.293284 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10868 00:28:20.316389 <30>[ 11.539294] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10869 00:28:20.322776 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10870 00:28:20.344470 <30>[ 11.567192] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10871 00:28:20.350437 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10872 00:28:20.379075 <30>[ 11.595605] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10873 00:28:20.388999 <30>[ 11.615511] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10874 00:28:20.395932 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10875 00:28:20.412934 <30>[ 11.638957] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10876 00:28:20.419619 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10877 00:28:20.436305 <30>[ 11.663007] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10878 00:28:20.446127 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10879 00:28:20.461103 <30>[ 11.691038] systemd[1]: Reached target paths.target - Path Units.
10880 00:28:20.471357 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10881 00:28:20.488852 <30>[ 11.715398] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10882 00:28:20.495415 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10883 00:28:20.509278 <30>[ 11.738954] systemd[1]: Reached target slices.target - Slice Units.
10884 00:28:20.519020 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10885 00:28:20.533592 <30>[ 11.763463] systemd[1]: Reached target swap.target - Swaps.
10886 00:28:20.539964 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10887 00:28:20.561117 <30>[ 11.787478] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10888 00:28:20.571117 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10889 00:28:20.589058 <30>[ 11.815427] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10890 00:28:20.599136 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10891 00:28:20.619784 <30>[ 11.846304] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10892 00:28:20.629941 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10893 00:28:20.646341 <30>[ 11.872519] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10894 00:28:20.656352 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10895 00:28:20.673666 <30>[ 11.899651] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10896 00:28:20.679786 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10897 00:28:20.698176 <30>[ 11.924457] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10898 00:28:20.707908 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10899 00:28:20.727219 <30>[ 11.954022] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10900 00:28:20.737266 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10901 00:28:20.753385 <30>[ 11.979450] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10902 00:28:20.763188 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10903 00:28:20.820755 <30>[ 12.047167] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10904 00:28:20.827136 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10905 00:28:20.849212 <30>[ 12.075688] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10906 00:28:20.855490 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10907 00:28:20.882416 <30>[ 12.108963] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10908 00:28:20.888964 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10909 00:28:20.915867 <30>[ 12.135398] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10910 00:28:20.977404 <30>[ 12.203834] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10911 00:28:20.987449 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10912 00:28:21.009303 <30>[ 12.235989] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10913 00:28:21.015828 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10914 00:28:21.042195 <30>[ 12.268627] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10915 00:28:21.048659 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10916 00:28:21.084751 <6>[ 12.311079] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10917 00:28:21.113377 <30>[ 12.339777] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10918 00:28:21.120268 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10919 00:28:21.146405 <30>[ 12.372806] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10920 00:28:21.156044 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10921 00:28:21.182369 <30>[ 12.408610] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10922 00:28:21.188674 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10923 00:28:21.214130 <30>[ 12.440614] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10924 00:28:21.220469 Startin<6>[ 12.449383] fuse: init (API version 7.37)
10925 00:28:21.227072 g [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10926 00:28:21.258022 <30>[ 12.484706] systemd[1]: Starting systemd-journald.service - Journal Service...
10927 00:28:21.264537 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10928 00:28:21.325563 <30>[ 12.552124] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10929 00:28:21.332342 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10930 00:28:21.359872 <30>[ 12.583241] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10931 00:28:21.366266 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10932 00:28:21.389034 <30>[ 12.615887] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10933 00:28:21.398874 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10934 00:28:21.426518 <30>[ 12.653221] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10935 00:28:21.433009 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10936 00:28:21.465192 <30>[ 12.691876] systemd[1]: Started systemd-journald.service - Journal Service.
10937 00:28:21.471430 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10938 00:28:21.501019 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10939 00:28:21.520587 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10940 00:28:21.536566 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10941 00:28:21.554612 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10942 00:28:21.574663 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10943 00:28:21.594712 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10944 00:28:21.618066 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10945 00:28:21.637604 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10946 00:28:21.658676 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10947 00:28:21.679955 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10948 00:28:21.698850 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10949 00:28:21.718476 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10950 00:28:21.738395 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10951 00:28:21.762717 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10952 00:28:21.813944 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10953 00:28:21.838814 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10954 00:28:21.900667 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10955 00:28:21.923100 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10956 00:28:21.949257 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10957 00:28:21.977189 <46>[ 13.204180] systemd-journald[308]: Received client request to flush runtime journal.
10958 00:28:22.013508 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10959 00:28:22.310008 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10960 00:28:22.328693 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10961 00:28:22.348583 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10962 00:28:22.369588 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10963 00:28:22.389677 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10964 00:28:23.126549 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10965 00:28:23.176849 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10966 00:28:23.444139 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10967 00:28:23.550868 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10968 00:28:23.568749 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10969 00:28:23.584233 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10970 00:28:23.625155 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10971 00:28:23.652387 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10972 00:28:23.851448 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10973 00:28:23.899301 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10974 00:28:23.967736 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10975 00:28:24.026335 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10976 00:28:24.157591 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10977 00:28:24.188450 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10978 00:28:24.305653 <6>[ 15.536035] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10979 00:28:24.432173 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10980 00:28:24.475208 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10981 00:28:24.491891 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10982 00:28:24.508372 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10983 00:28:24.545049 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10984 00:28:24.565652 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10985 00:28:24.585229 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10986 00:28:24.619743 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10987 00:28:24.637146 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10988 00:28:24.655880 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10989 00:28:24.676066 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10990 00:28:24.696182 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10991 00:28:24.724577 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
10992 00:28:24.747559 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
10993 00:28:24.764726 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
10994 00:28:24.783685 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
10995 00:28:24.803657 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10996 00:28:24.820078 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10997 00:28:24.838062 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10998 00:28:24.855971 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10999 00:28:24.872856 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11000 00:28:24.917010 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11001 00:28:24.997297 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11002 00:28:25.047014 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11003 00:28:25.076968 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11004 00:28:25.108251 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11005 00:28:25.139342 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11006 00:28:25.178246 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11007 00:28:25.232483 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11008 00:28:25.251427 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11009 00:28:25.271649 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11010 00:28:25.293217 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11011 00:28:25.333782 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11012 00:28:25.449019 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11013 00:28:25.472336 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11014 00:28:25.493265 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11015 00:28:25.549862 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11016 00:28:25.627723 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11017 00:28:25.721364
11018 00:28:25.724906 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11019 00:28:25.725337
11020 00:28:25.727757 debian-bookworm-arm64 login: root (automatic login)
11021 00:28:25.728190
11022 00:28:26.019428 Linux debian-bookworm-arm64 6.1.94-cip23 #1 SMP PREEMPT Fri Jun 21 00:04:56 UTC 2024 aarch64
11023 00:28:26.019573
11024 00:28:26.025719 The programs included with the Debian GNU/Linux system are free software;
11025 00:28:26.032955 the exact distribution terms for each program are described in the
11026 00:28:26.035999 individual files in /usr/share/doc/*/copyright.
11027 00:28:26.036075
11028 00:28:26.042323 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11029 00:28:26.045776 permitted by applicable law.
11030 00:28:27.084081 Matched prompt #10: / #
11032 00:28:27.085209 Setting prompt string to ['/ #']
11033 00:28:27.085713 end: 2.2.5.1 login-action (duration 00:00:19) [common]
11035 00:28:27.086624 end: 2.2.5 auto-login-action (duration 00:00:19) [common]
11036 00:28:27.087033 start: 2.2.6 expect-shell-connection (timeout 00:03:37) [common]
11037 00:28:27.087369 Setting prompt string to ['/ #']
11038 00:28:27.087657 Forcing a shell prompt, looking for ['/ #']
11040 00:28:27.138518 / #
11041 00:28:27.139194 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11042 00:28:27.139612 Waiting using forced prompt support (timeout 00:02:30)
11043 00:28:27.144461
11044 00:28:27.145411 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11045 00:28:27.145944 start: 2.2.7 export-device-env (timeout 00:03:37) [common]
11047 00:28:27.247328 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14479216/extract-nfsrootfs-72fyp65p'
11048 00:28:27.253786 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14479216/extract-nfsrootfs-72fyp65p'
11050 00:28:27.355421 / # export NFS_SERVER_IP='192.168.201.1'
11051 00:28:27.362328 export NFS_SERVER_IP='192.168.201.1'
11052 00:28:27.363204 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11053 00:28:27.363706 end: 2.2 depthcharge-retry (duration 00:01:23) [common]
11054 00:28:27.364185 end: 2 depthcharge-action (duration 00:01:23) [common]
11055 00:28:27.364646 start: 3 lava-test-retry (timeout 00:07:59) [common]
11056 00:28:27.365148 start: 3.1 lava-test-shell (timeout 00:07:59) [common]
11057 00:28:27.365532 Using namespace: common
11059 00:28:27.466786 / # #
11060 00:28:27.467451 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11061 00:28:27.473356 #
11062 00:28:27.474183 Using /lava-14479216
11064 00:28:27.575355 / # export SHELL=/bin/bash
11065 00:28:27.581907 export SHELL=/bin/bash
11067 00:28:27.683601 / # . /lava-14479216/environment
11068 00:28:27.690201 . /lava-14479216/environment
11070 00:28:27.797121 / # /lava-14479216/bin/lava-test-runner /lava-14479216/0
11071 00:28:27.797739 Test shell timeout: 10s (minimum of the action and connection timeout)
11072 00:28:27.803524 /lava-14479216/bin/lava-test-runner /lava-14479216/0
11073 00:28:28.051900 + export TESTRUN_ID=0_timesync-off
11074 00:28:28.055289 + TESTRUN_ID=0_timesync-off
11075 00:28:28.058727 + cd /lava-14479216/0/tests/0_timesync-off
11076 00:28:28.061707 ++ cat uuid
11077 00:28:28.065191 + UUID=14479216_1.6.2.3.1
11078 00:28:28.065269 + set +x
11079 00:28:28.071884 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14479216_1.6.2.3.1>
11080 00:28:28.072143 Received signal: <STARTRUN> 0_timesync-off 14479216_1.6.2.3.1
11081 00:28:28.072216 Starting test lava.0_timesync-off (14479216_1.6.2.3.1)
11082 00:28:28.072301 Skipping test definition patterns.
11083 00:28:28.074946 + systemctl stop systemd-timesyncd
11084 00:28:28.151940 + set +x
11085 00:28:28.155301 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14479216_1.6.2.3.1>
11086 00:28:28.155585 Received signal: <ENDRUN> 0_timesync-off 14479216_1.6.2.3.1
11087 00:28:28.155691 Ending use of test pattern.
11088 00:28:28.155771 Ending test lava.0_timesync-off (14479216_1.6.2.3.1), duration 0.08
11090 00:28:28.228080 + export TESTRUN_ID=1_kselftest-tpm2
11091 00:28:28.231220 + TESTRUN_ID=1_kselftest-tpm2
11092 00:28:28.238355 + cd /lava-14479216/0/tests/1_kselftest-tpm2
11093 00:28:28.238757 ++ cat uuid
11094 00:28:28.242517 + UUID=14479216_1.6.2.3.5
11095 00:28:28.242914 + set +x
11096 00:28:28.249333 <LAVA_SIGNAL_STARTRUN 1_kselftest-tpm2 14479216_1.6.2.3.5>
11097 00:28:28.249974 Received signal: <STARTRUN> 1_kselftest-tpm2 14479216_1.6.2.3.5
11098 00:28:28.250309 Starting test lava.1_kselftest-tpm2 (14479216_1.6.2.3.5)
11099 00:28:28.250666 Skipping test definition patterns.
11100 00:28:28.252407 + cd ./automated/linux/kselftest/
11101 00:28:28.279152 + ./kselftest.sh -c tpm2 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.94-cip23/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11102 00:28:28.319693 INFO: install_deps skipped
11103 00:28:28.812377 --2024-06-21 00:28:28-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.94-cip23/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11104 00:28:28.830726 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11105 00:28:28.959809 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11106 00:28:29.089153 HTTP request sent, awaiting response... 200 OK
11107 00:28:29.091915 Length: 1642760 (1.6M) [application/octet-stream]
11108 00:28:29.095064 Saving to: 'kselftest_armhf.tar.gz'
11109 00:28:29.095672
11110 00:28:29.096140
11111 00:28:29.346158 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
11112 00:28:29.603421 kselftest_armhf.tar 3%[ ] 49.22K 192KB/s
11113 00:28:30.038290 kselftest_armhf.tar 13%[=> ] 217.50K 423KB/s
11114 00:28:30.044630 kselftest_armhf.tar 48%[========> ] 771.81K 813KB/s
11115 00:28:30.051022 kselftest_armhf.tar 100%[===================>] 1.57M 1.64MB/s in 1.0s
11116 00:28:30.051449
11117 00:28:30.196446 2024-06-21 00:28:30 (1.64 MB/s) - 'kselftest_armhf.tar.gz' saved [1642760/1642760]
11118 00:28:30.196755
11119 00:28:34.159441 skiplist:
11120 00:28:34.162563 ========================================
11121 00:28:34.165879 ========================================
11122 00:28:34.202073 tpm2:test_smoke.sh
11123 00:28:34.205498 tpm2:test_space.sh
11124 00:28:34.219797 ============== Tests to run ===============
11125 00:28:34.219929 tpm2:test_smoke.sh
11126 00:28:34.223216 tpm2:test_space.sh
11127 00:28:34.226705 ===========End Tests to run ===============
11128 00:28:34.226789 shardfile-tpm2 pass
11129 00:28:34.321270 <12>[ 25.553201] kselftest: Running tests in tpm2
11130 00:28:34.329512 TAP version 13
11131 00:28:34.342959 1..2
11132 00:28:34.371111 # selftests: tpm2: test_smoke.sh
11133 00:28:36.137255 # test_read_partial_overwrite (tpm2_tests.SmokeTest.test_read_partial_overwrite) ... ERROR
11134 00:28:36.144118 # test_read_partial_resp (tpm2_tests.SmokeTest.test_read_partial_resp) ... ERROR
11135 00:28:36.150473 # Exception ignored in: <function Client.__del__ at 0xffff9ad3ccc0>
11136 00:28:36.153679 # Traceback (most recent call last):
11137 00:28:36.164083 # File "/lava-14479216/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11138 00:28:36.164600 # if self.tpm:
11139 00:28:36.167372 # ^^^^^^^^
11140 00:28:36.170576 # AttributeError: 'Client' object has no attribute 'tpm'
11141 00:28:36.177042 # test_seal_with_auth (tpm2_tests.SmokeTest.test_seal_with_auth) ... ERROR
11142 00:28:36.184161 # Exception ignored in: <function Client.__del__ at 0xffff9ad3ccc0>
11143 00:28:36.187366 # Traceback (most recent call last):
11144 00:28:36.197479 # File "/lava-14479216/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11145 00:28:36.197993 # if self.tpm:
11146 00:28:36.201053 # ^^^^^^^^
11147 00:28:36.204178 # AttributeError: 'Client' object has no attribute 'tpm'
11148 00:28:36.211075 # test_seal_with_policy (tpm2_tests.SmokeTest.test_seal_with_policy) ... ERROR
11149 00:28:36.217331 # Exception ignored in: <function Client.__del__ at 0xffff9ad3ccc0>
11150 00:28:36.220916 # Traceback (most recent call last):
11151 00:28:36.230760 # File "/lava-14479216/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11152 00:28:36.233739 # if self.tpm:
11153 00:28:36.234166 # ^^^^^^^^
11154 00:28:36.240537 # AttributeError: 'Client' object has no attribute 'tpm'
11155 00:28:36.247032 # test_seal_with_too_long_auth (tpm2_tests.SmokeTest.test_seal_with_too_long_auth) ... ERROR
11156 00:28:36.253708 # Exception ignored in: <function Client.__del__ at 0xffff9ad3ccc0>
11157 00:28:36.257412 # Traceback (most recent call last):
11158 00:28:36.267112 # File "/lava-14479216/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11159 00:28:36.267807 # if self.tpm:
11160 00:28:36.270500 # ^^^^^^^^
11161 00:28:36.273789 # AttributeError: 'Client' object has no attribute 'tpm'
11162 00:28:36.280361 # test_send_two_cmds (tpm2_tests.SmokeTest.test_send_two_cmds) ... ERROR
11163 00:28:36.287255 # Exception ignored in: <function Client.__del__ at 0xffff9ad3ccc0>
11164 00:28:36.290511 # Traceback (most recent call last):
11165 00:28:36.300595 # File "/lava-14479216/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11166 00:28:36.304037 # if self.tpm:
11167 00:28:36.304545 # ^^^^^^^^
11168 00:28:36.310164 # AttributeError: 'Client' object has no attribute 'tpm'
11169 00:28:36.313871 # test_too_short_cmd (tpm2_tests.SmokeTest.test_too_short_cmd) ... ERROR
11170 00:28:36.320143 # Exception ignored in: <function Client.__del__ at 0xffff9ad3ccc0>
11171 00:28:36.323692 # Traceback (most recent call last):
11172 00:28:36.333724 # File "/lava-14479216/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11173 00:28:36.337088 # if self.tpm:
11174 00:28:36.337213 # ^^^^^^^^
11175 00:28:36.343825 # AttributeError: 'Client' object has no attribute 'tpm'
11176 00:28:36.350362 # test_unseal_with_wrong_auth (tpm2_tests.SmokeTest.test_unseal_with_wrong_auth) ... ERROR
11177 00:28:36.356700 # Exception ignored in: <function Client.__del__ at 0xffff9ad3ccc0>
11178 00:28:36.360292 # Traceback (most recent call last):
11179 00:28:36.370002 # File "/lava-14479216/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11180 00:28:36.370279 # if self.tpm:
11181 00:28:36.373686 # ^^^^^^^^
11182 00:28:36.377005 # AttributeError: 'Client' object has no attribute 'tpm'
11183 00:28:36.387077 # test_unseal_with_wrong_policy (tpm2_tests.SmokeTest.test_unseal_with_wrong_policy) ... ERROR
11184 00:28:36.394092 # Exception ignored in: <function Client.__del__ at 0xffff9ad3ccc0>
11185 00:28:36.397142 # Traceback (most recent call last):
11186 00:28:36.407195 # File "/lava-14479216/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11187 00:28:36.407750 # if self.tpm:
11188 00:28:36.410434 # ^^^^^^^^
11189 00:28:36.413687 # AttributeError: 'Client' object has no attribute 'tpm'
11190 00:28:36.414077 #
11191 00:28:36.423680 # ======================================================================
11192 00:28:36.430182 # ERROR: test_read_partial_overwrite (tpm2_tests.SmokeTest.test_read_partial_overwrite)
11193 00:28:36.436335 # ----------------------------------------------------------------------
11194 00:28:36.440043 # Traceback (most recent call last):
11195 00:28:36.449790 # File "/lava-14479216/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 16, in setUp
11196 00:28:36.453391 # self.root_key = self.client.create_root_key()
11197 00:28:36.456567 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11198 00:28:36.469487 # File "/lava-14479216/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11199 00:28:36.473264 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11200 00:28:36.479710 # ^^^^^^^^^^^^^^^^^^
11201 00:28:36.489903 # File "/lava-14479216/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11202 00:28:36.493259 # raise ProtocolError(cc, rc)
11203 00:28:36.496314 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11204 00:28:36.496406 #
11205 00:28:36.503360 # ======================================================================
11206 00:28:36.510189 # ERROR: test_read_partial_resp (tpm2_tests.SmokeTest.test_read_partial_resp)
11207 00:28:36.516609 # ----------------------------------------------------------------------
11208 00:28:36.520182 # Traceback (most recent call last):
11209 00:28:36.530085 # File "/lava-14479216/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11210 00:28:36.533445 # self.client = tpm2.Client()
11211 00:28:36.536857 # ^^^^^^^^^^^^^
11212 00:28:36.547131 # File "/lava-14479216/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11213 00:28:36.550259 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11214 00:28:36.557076 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11215 00:28:36.559989 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11216 00:28:36.563540 #
11217 00:28:36.570155 # ======================================================================
11218 00:28:36.573626 # ERROR: test_seal_with_auth (tpm2_tests.SmokeTest.test_seal_with_auth)
11219 00:28:36.579964 # ----------------------------------------------------------------------
11220 00:28:36.583598 # Traceback (most recent call last):
11221 00:28:36.593495 # File "/lava-14479216/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11222 00:28:36.596880 # self.client = tpm2.Client()
11223 00:28:36.600004 # ^^^^^^^^^^^^^
11224 00:28:36.610175 # File "/lava-14479216/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11225 00:28:36.616628 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11226 00:28:36.619966 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11227 00:28:36.626844 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11228 00:28:36.627233 #
11229 00:28:36.633465 # ======================================================================
11230 00:28:36.640353 # ERROR: test_seal_with_policy (tpm2_tests.SmokeTest.test_seal_with_policy)
11231 00:28:36.647070 # ----------------------------------------------------------------------
11232 00:28:36.650399 # Traceback (most recent call last):
11233 00:28:36.660021 # File "/lava-14479216/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11234 00:28:36.663710 # self.client = tpm2.Client()
11235 00:28:36.664184 # ^^^^^^^^^^^^^
11236 00:28:36.673688 # File "/lava-14479216/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11237 00:28:36.680269 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11238 00:28:36.683520 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11239 00:28:36.689997 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11240 00:28:36.690391 #
11241 00:28:36.696271 # ======================================================================
11242 00:28:36.703170 # ERROR: test_seal_with_too_long_auth (tpm2_tests.SmokeTest.test_seal_with_too_long_auth)
11243 00:28:36.709822 # ----------------------------------------------------------------------
11244 00:28:36.713251 # Traceback (most recent call last):
11245 00:28:36.725243 # File "/lava-14479216/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11246 00:28:36.728987 # self.client = tpm2.Client()
11247 00:28:36.729498 # ^^^^^^^^^^^^^
11248 00:28:36.740427 # File "/lava-14479216/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11249 00:28:36.743748 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11250 00:28:36.755198 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11251 00:28:36.758438 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11252 00:28:36.758951 #
11253 00:28:36.761878 # ======================================================================
11254 00:28:36.767474 # ERROR: test_send_two_cmds (tpm2_tests.SmokeTest.test_send_two_cmds)
11255 00:28:36.773787 # ----------------------------------------------------------------------
11256 00:28:36.777185 # Traceback (most recent call last):
11257 00:28:36.787280 # File "/lava-14479216/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11258 00:28:36.790793 # self.client = tpm2.Client()
11259 00:28:36.793831 # ^^^^^^^^^^^^^
11260 00:28:36.803767 # File "/lava-14479216/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11261 00:28:36.809961 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11262 00:28:36.813432 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11263 00:28:36.820125 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11264 00:28:36.820637 #
11265 00:28:36.826965 # ======================================================================
11266 00:28:36.830097 # ERROR: test_too_short_cmd (tpm2_tests.SmokeTest.test_too_short_cmd)
11267 00:28:36.837103 # ----------------------------------------------------------------------
11268 00:28:36.840286 # Traceback (most recent call last):
11269 00:28:36.850363 # File "/lava-14479216/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11270 00:28:36.853597 # self.client = tpm2.Client()
11271 00:28:36.856620 # ^^^^^^^^^^^^^
11272 00:28:36.866704 # File "/lava-14479216/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11273 00:28:36.873675 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11274 00:28:36.876960 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11275 00:28:36.883654 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11276 00:28:36.884166 #
11277 00:28:36.890306 # ======================================================================
11278 00:28:36.897196 # ERROR: test_unseal_with_wrong_auth (tpm2_tests.SmokeTest.test_unseal_with_wrong_auth)
11279 00:28:36.903718 # ----------------------------------------------------------------------
11280 00:28:36.907543 # Traceback (most recent call last):
11281 00:28:36.916692 # File "/lava-14479216/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11282 00:28:36.920295 # self.client = tpm2.Client()
11283 00:28:36.923564 # ^^^^^^^^^^^^^
11284 00:28:36.933429 # File "/lava-14479216/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11285 00:28:36.936835 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11286 00:28:36.943362 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11287 00:28:36.947221 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11288 00:28:36.947744 #
11289 00:28:36.953491 # ======================================================================
11290 00:28:36.963319 # ERROR: test_unseal_with_wrong_policy (tpm2_tests.SmokeTest.test_unseal_with_wrong_policy)
11291 00:28:36.970193 # ----------------------------------------------------------------------
11292 00:28:36.973588 # Traceback (most recent call last):
11293 00:28:36.983242 # File "/lava-14479216/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11294 00:28:36.986508 # self.client = tpm2.Client()
11295 00:28:36.989878 # ^^^^^^^^^^^^^
11296 00:28:36.996794 # File "/lava-14479216/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11297 00:28:37.003404 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11298 00:28:37.006725 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11299 00:28:37.013657 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11300 00:28:37.014160 #
11301 00:28:37.019916 # ----------------------------------------------------------------------
11302 00:28:37.023518 # Ran 9 tests in 0.045s
11303 00:28:37.023951 #
11304 00:28:37.024292 # FAILED (errors=9)
11305 00:28:37.030051 # test_async (tpm2_tests.AsyncTest.test_async) ... ok
11306 00:28:37.036974 # test_flush_invalid_context (tpm2_tests.AsyncTest.test_flush_invalid_context) ... ok
11307 00:28:37.037472 #
11308 00:28:37.043430 # ----------------------------------------------------------------------
11309 00:28:37.046839 # Ran 2 tests in 0.025s
11310 00:28:37.047275 #
11311 00:28:37.047613 # OK
11312 00:28:37.049908 ok 1 selftests: tpm2: test_smoke.sh
11313 00:28:37.053303 # selftests: tpm2: test_space.sh
11314 00:28:37.060005 # test_flush_context (tpm2_tests.SpaceTest.test_flush_context) ... ERROR
11315 00:28:37.066592 # test_get_handles (tpm2_tests.SpaceTest.test_get_handles) ... ERROR
11316 00:28:37.070314 # test_invalid_cc (tpm2_tests.SpaceTest.test_invalid_cc) ... ERROR
11317 00:28:37.076791 # test_make_two_spaces (tpm2_tests.SpaceTest.test_make_two_spaces) ... ERROR
11318 00:28:37.077313 #
11319 00:28:37.083058 # ======================================================================
11320 00:28:37.090142 # ERROR: test_flush_context (tpm2_tests.SpaceTest.test_flush_context)
11321 00:28:37.096692 # ----------------------------------------------------------------------
11322 00:28:37.099783 # Traceback (most recent call last):
11323 00:28:37.113084 # File "/lava-14479216/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 261, in test_flush_context
11324 00:28:37.116829 # root1 = space1.create_root_key()
11325 00:28:37.120343 # ^^^^^^^^^^^^^^^^^^^^^^^^
11326 00:28:37.130173 # File "/lava-14479216/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11327 00:28:37.133253 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11328 00:28:37.140004 # ^^^^^^^^^^^^^^^^^^
11329 00:28:37.150562 # File "/lava-14479216/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11330 00:28:37.153456 # raise ProtocolError(cc, rc)
11331 00:28:37.156889 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11332 00:28:37.160335 #
11333 00:28:37.163651 # ======================================================================
11334 00:28:37.169929 # ERROR: test_get_handles (tpm2_tests.SpaceTest.test_get_handles)
11335 00:28:37.176544 # ----------------------------------------------------------------------
11336 00:28:37.180009 # Traceback (most recent call last):
11337 00:28:37.190087 # File "/lava-14479216/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 271, in test_get_handles
11338 00:28:37.193659 # space1.create_root_key()
11339 00:28:37.203527 # File "/lava-14479216/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11340 00:28:37.210030 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11341 00:28:37.213202 # ^^^^^^^^^^^^^^^^^^
11342 00:28:37.223725 # File "/lava-14479216/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11343 00:28:37.226729 # raise ProtocolError(cc, rc)
11344 00:28:37.233316 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11345 00:28:37.233878 #
11346 00:28:37.240141 # ======================================================================
11347 00:28:37.246664 # ERROR: test_invalid_cc (tpm2_tests.SpaceTest.test_invalid_cc)
11348 00:28:37.253296 # ----------------------------------------------------------------------
11349 00:28:37.257015 # Traceback (most recent call last):
11350 00:28:37.266818 # File "/lava-14479216/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 290, in test_invalid_cc
11351 00:28:37.270070 # root1 = space1.create_root_key()
11352 00:28:37.273845 # ^^^^^^^^^^^^^^^^^^^^^^^^
11353 00:28:37.283714 # File "/lava-14479216/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11354 00:28:37.290227 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11355 00:28:37.293841 # ^^^^^^^^^^^^^^^^^^
11356 00:28:37.303588 # File "/lava-14479216/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11357 00:28:37.306941 # raise ProtocolError(cc, rc)
11358 00:28:37.313645 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11359 00:28:37.314270 #
11360 00:28:37.320095 # ======================================================================
11361 00:28:37.327040 # ERROR: test_make_two_spaces (tpm2_tests.SpaceTest.test_make_two_spaces)
11362 00:28:37.333353 # ----------------------------------------------------------------------
11363 00:28:37.337036 # Traceback (most recent call last):
11364 00:28:37.346669 # File "/lava-14479216/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 247, in test_make_two_spaces
11365 00:28:37.350242 # root1 = space1.create_root_key()
11366 00:28:37.353616 # ^^^^^^^^^^^^^^^^^^^^^^^^
11367 00:28:37.367025 # File "/lava-14479216/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11368 00:28:37.370231 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11369 00:28:37.377014 # ^^^^^^^^^^^^^^^^^^
11370 00:28:37.386544 # File "/lava-14479216/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11371 00:28:37.389808 # raise ProtocolError(cc, rc)
11372 00:28:37.393598 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11373 00:28:37.393996 #
11374 00:28:37.399750 # ----------------------------------------------------------------------
11375 00:28:37.402970 # Ran 4 tests in 0.060s
11376 00:28:37.403047 #
11377 00:28:37.406452 # FAILED (errors=4)
11378 00:28:37.409546 not ok 2 selftests: tpm2: test_space.sh # exit=1
11379 00:28:37.741790 tpm2_test_smoke_sh pass
11380 00:28:37.745176 tpm2_test_space_sh fail
11381 00:28:37.814578 + ../../utils/send-to-lava.sh ./output/result.txt
11382 00:28:37.882772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-tpm2 RESULT=pass>
11383 00:28:37.883566 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-tpm2 RESULT=pass
11385 00:28:37.934259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass>
11386 00:28:37.934967 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass
11388 00:28:37.985146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_space_sh RESULT=fail>
11389 00:28:37.985781 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_space_sh RESULT=fail
11391 00:28:37.988586 + set +x
11392 00:28:37.992396 <LAVA_SIGNAL_ENDRUN 1_kselftest-tpm2 14479216_1.6.2.3.5>
11393 00:28:37.993063 Received signal: <ENDRUN> 1_kselftest-tpm2 14479216_1.6.2.3.5
11394 00:28:37.993411 Ending use of test pattern.
11395 00:28:37.993704 Ending test lava.1_kselftest-tpm2 (14479216_1.6.2.3.5), duration 9.74
11397 00:28:37.995121 <LAVA_TEST_RUNNER EXIT>
11398 00:28:37.995754 ok: lava_test_shell seems to have completed
11399 00:28:37.996263 shardfile-tpm2: pass
tpm2_test_smoke_sh: pass
tpm2_test_space_sh: fail
11400 00:28:37.996667 end: 3.1 lava-test-shell (duration 00:00:11) [common]
11401 00:28:37.997232 end: 3 lava-test-retry (duration 00:00:11) [common]
11402 00:28:37.997653 start: 4 finalize (timeout 00:07:48) [common]
11403 00:28:37.998055 start: 4.1 power-off (timeout 00:00:30) [common]
11404 00:28:37.998699 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-1', '--port=1', '--command=off']
11405 00:28:40.108025 >> Command sent successfully.
11406 00:28:40.122867 Returned 0 in 2 seconds
11407 00:28:40.224320 end: 4.1 power-off (duration 00:00:02) [common]
11409 00:28:40.225784 start: 4.2 read-feedback (timeout 00:07:46) [common]
11410 00:28:40.226912 Listened to connection for namespace 'common' for up to 1s
11411 00:28:41.227781 Finalising connection for namespace 'common'
11412 00:28:41.228622 Disconnecting from shell: Finalise
11413 00:28:41.229090 / #
11414 00:28:41.330077 end: 4.2 read-feedback (duration 00:00:01) [common]
11415 00:28:41.330751 end: 4 finalize (duration 00:00:03) [common]
11416 00:28:41.331372 Cleaning after the job
11417 00:28:41.331890 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14479216/tftp-deploy-t4ydc2e7/ramdisk
11418 00:28:41.336981 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14479216/tftp-deploy-t4ydc2e7/kernel
11419 00:28:41.346834 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14479216/tftp-deploy-t4ydc2e7/dtb
11420 00:28:41.346989 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14479216/tftp-deploy-t4ydc2e7/nfsrootfs
11421 00:28:41.406780 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14479216/tftp-deploy-t4ydc2e7/modules
11422 00:28:41.412200 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14479216
11423 00:28:41.962664 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14479216
11424 00:28:41.962840 Job finished correctly