Boot log: mt8183-kukui-jacuzzi-juniper-sku16
- Errors: 0
- Kernel Errors: 46
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 87
1 01:53:37.556397 lava-dispatcher, installed at version: 2024.03
2 01:53:37.556614 start: 0 validate
3 01:53:37.556728 Start time: 2024-06-21 01:53:37.556719+00:00 (UTC)
4 01:53:37.556852 Using caching service: 'http://localhost/cache/?uri=%s'
5 01:53:37.556987 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-libcamera%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 01:53:37.813468 Using caching service: 'http://localhost/cache/?uri=%s'
7 01:53:37.813649 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.94-cip23%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 01:53:38.064461 Using caching service: 'http://localhost/cache/?uri=%s'
9 01:53:38.065333 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.94-cip23%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8183-kukui-jacuzzi-juniper-sku16.dtb exists
10 01:53:38.318411 Using caching service: 'http://localhost/cache/?uri=%s'
11 01:53:38.319067 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-libcamera%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 01:53:38.581150 Using caching service: 'http://localhost/cache/?uri=%s'
13 01:53:38.581936 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.94-cip23%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 01:53:38.848491 validate duration: 1.29
16 01:53:38.850158 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 01:53:38.850865 start: 1.1 download-retry (timeout 00:10:00) [common]
18 01:53:38.851434 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 01:53:38.852359 Not decompressing ramdisk as can be used compressed.
20 01:53:38.853090 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-libcamera/20240313.0/arm64/initrd.cpio.gz
21 01:53:38.853490 saving as /var/lib/lava/dispatcher/tmp/14479155/tftp-deploy-8daa0ozx/ramdisk/initrd.cpio.gz
22 01:53:38.854051 total size: 5628151 (5 MB)
23 01:53:38.858980 progress 0 % (0 MB)
24 01:53:38.864471 progress 5 % (0 MB)
25 01:53:38.868517 progress 10 % (0 MB)
26 01:53:38.871555 progress 15 % (0 MB)
27 01:53:38.874500 progress 20 % (1 MB)
28 01:53:38.877037 progress 25 % (1 MB)
29 01:53:38.879579 progress 30 % (1 MB)
30 01:53:38.882037 progress 35 % (1 MB)
31 01:53:38.883965 progress 40 % (2 MB)
32 01:53:38.886112 progress 45 % (2 MB)
33 01:53:38.887895 progress 50 % (2 MB)
34 01:53:38.889833 progress 55 % (2 MB)
35 01:53:38.891693 progress 60 % (3 MB)
36 01:53:38.893307 progress 65 % (3 MB)
37 01:53:38.895076 progress 70 % (3 MB)
38 01:53:38.896617 progress 75 % (4 MB)
39 01:53:38.898304 progress 80 % (4 MB)
40 01:53:38.899750 progress 85 % (4 MB)
41 01:53:38.901309 progress 90 % (4 MB)
42 01:53:38.902910 progress 95 % (5 MB)
43 01:53:38.904336 progress 100 % (5 MB)
44 01:53:38.904569 5 MB downloaded in 0.05 s (106.24 MB/s)
45 01:53:38.904769 end: 1.1.1 http-download (duration 00:00:00) [common]
47 01:53:38.905073 end: 1.1 download-retry (duration 00:00:00) [common]
48 01:53:38.905193 start: 1.2 download-retry (timeout 00:10:00) [common]
49 01:53:38.905309 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 01:53:38.905481 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.94-cip23/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 01:53:38.905603 saving as /var/lib/lava/dispatcher/tmp/14479155/tftp-deploy-8daa0ozx/kernel/Image
52 01:53:38.905692 total size: 54813184 (52 MB)
53 01:53:38.905781 No compression specified
54 01:53:38.907257 progress 0 % (0 MB)
55 01:53:38.921290 progress 5 % (2 MB)
56 01:53:38.935594 progress 10 % (5 MB)
57 01:53:38.949746 progress 15 % (7 MB)
58 01:53:38.963940 progress 20 % (10 MB)
59 01:53:38.978465 progress 25 % (13 MB)
60 01:53:38.992498 progress 30 % (15 MB)
61 01:53:39.007347 progress 35 % (18 MB)
62 01:53:39.021792 progress 40 % (20 MB)
63 01:53:39.035545 progress 45 % (23 MB)
64 01:53:39.049742 progress 50 % (26 MB)
65 01:53:39.064227 progress 55 % (28 MB)
66 01:53:39.078555 progress 60 % (31 MB)
67 01:53:39.093019 progress 65 % (34 MB)
68 01:53:39.107436 progress 70 % (36 MB)
69 01:53:39.122138 progress 75 % (39 MB)
70 01:53:39.136403 progress 80 % (41 MB)
71 01:53:39.150685 progress 85 % (44 MB)
72 01:53:39.164749 progress 90 % (47 MB)
73 01:53:39.178821 progress 95 % (49 MB)
74 01:53:39.192962 progress 100 % (52 MB)
75 01:53:39.193217 52 MB downloaded in 0.29 s (181.81 MB/s)
76 01:53:39.193417 end: 1.2.1 http-download (duration 00:00:00) [common]
78 01:53:39.193806 end: 1.2 download-retry (duration 00:00:00) [common]
79 01:53:39.193914 start: 1.3 download-retry (timeout 00:10:00) [common]
80 01:53:39.194016 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 01:53:39.194169 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.94-cip23/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dtb
82 01:53:39.194236 saving as /var/lib/lava/dispatcher/tmp/14479155/tftp-deploy-8daa0ozx/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb
83 01:53:39.194292 total size: 57695 (0 MB)
84 01:53:39.194348 No compression specified
85 01:53:39.195885 progress 56 % (0 MB)
86 01:53:39.196169 progress 100 % (0 MB)
87 01:53:39.196395 0 MB downloaded in 0.00 s (26.20 MB/s)
88 01:53:39.196563 end: 1.3.1 http-download (duration 00:00:00) [common]
90 01:53:39.196922 end: 1.3 download-retry (duration 00:00:00) [common]
91 01:53:39.197025 start: 1.4 download-retry (timeout 00:10:00) [common]
92 01:53:39.197129 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 01:53:39.197263 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-libcamera/20240313.0/arm64/full.rootfs.tar.xz
94 01:53:39.197347 saving as /var/lib/lava/dispatcher/tmp/14479155/tftp-deploy-8daa0ozx/nfsrootfs/full.rootfs.tar
95 01:53:39.197426 total size: 69067788 (65 MB)
96 01:53:39.197506 Using unxz to decompress xz
97 01:53:39.198816 progress 0 % (0 MB)
98 01:53:39.385407 progress 5 % (3 MB)
99 01:53:39.584428 progress 10 % (6 MB)
100 01:53:39.778424 progress 15 % (9 MB)
101 01:53:39.941949 progress 20 % (13 MB)
102 01:53:40.123849 progress 25 % (16 MB)
103 01:53:40.323150 progress 30 % (19 MB)
104 01:53:40.447517 progress 35 % (23 MB)
105 01:53:40.546237 progress 40 % (26 MB)
106 01:53:40.750183 progress 45 % (29 MB)
107 01:53:40.953911 progress 50 % (32 MB)
108 01:53:41.152116 progress 55 % (36 MB)
109 01:53:41.361717 progress 60 % (39 MB)
110 01:53:41.548352 progress 65 % (42 MB)
111 01:53:41.743968 progress 70 % (46 MB)
112 01:53:41.929750 progress 75 % (49 MB)
113 01:53:42.134190 progress 80 % (52 MB)
114 01:53:42.310413 progress 85 % (56 MB)
115 01:53:42.499328 progress 90 % (59 MB)
116 01:53:42.700890 progress 95 % (62 MB)
117 01:53:42.907239 progress 100 % (65 MB)
118 01:53:42.913288 65 MB downloaded in 3.72 s (17.73 MB/s)
119 01:53:42.913451 end: 1.4.1 http-download (duration 00:00:04) [common]
121 01:53:42.913786 end: 1.4 download-retry (duration 00:00:04) [common]
122 01:53:42.913894 start: 1.5 download-retry (timeout 00:09:56) [common]
123 01:53:42.914021 start: 1.5.1 http-download (timeout 00:09:56) [common]
124 01:53:42.914153 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.94-cip23/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 01:53:42.914219 saving as /var/lib/lava/dispatcher/tmp/14479155/tftp-deploy-8daa0ozx/modules/modules.tar
126 01:53:42.914273 total size: 8618924 (8 MB)
127 01:53:42.914329 Using unxz to decompress xz
128 01:53:42.915968 progress 0 % (0 MB)
129 01:53:42.935327 progress 5 % (0 MB)
130 01:53:42.958689 progress 10 % (0 MB)
131 01:53:42.982774 progress 15 % (1 MB)
132 01:53:43.007340 progress 20 % (1 MB)
133 01:53:43.031991 progress 25 % (2 MB)
134 01:53:43.055620 progress 30 % (2 MB)
135 01:53:43.079748 progress 35 % (2 MB)
136 01:53:43.103285 progress 40 % (3 MB)
137 01:53:43.127083 progress 45 % (3 MB)
138 01:53:43.150984 progress 50 % (4 MB)
139 01:53:43.174743 progress 55 % (4 MB)
140 01:53:43.200140 progress 60 % (4 MB)
141 01:53:43.224464 progress 65 % (5 MB)
142 01:53:43.253817 progress 70 % (5 MB)
143 01:53:43.279109 progress 75 % (6 MB)
144 01:53:43.303587 progress 80 % (6 MB)
145 01:53:43.327647 progress 85 % (7 MB)
146 01:53:43.352174 progress 90 % (7 MB)
147 01:53:43.379894 progress 95 % (7 MB)
148 01:53:43.408269 progress 100 % (8 MB)
149 01:53:43.412709 8 MB downloaded in 0.50 s (16.49 MB/s)
150 01:53:43.412870 end: 1.5.1 http-download (duration 00:00:00) [common]
152 01:53:43.413084 end: 1.5 download-retry (duration 00:00:00) [common]
153 01:53:43.413163 start: 1.6 prepare-tftp-overlay (timeout 00:09:55) [common]
154 01:53:43.413240 start: 1.6.1 extract-nfsrootfs (timeout 00:09:55) [common]
155 01:53:45.021266 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14479155/extract-nfsrootfs-t4oh8com
156 01:53:45.021441 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 01:53:45.021531 start: 1.6.2 lava-overlay (timeout 00:09:54) [common]
158 01:53:45.021827 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14479155/lava-overlay-52ldeykd
159 01:53:45.021944 makedir: /var/lib/lava/dispatcher/tmp/14479155/lava-overlay-52ldeykd/lava-14479155/bin
160 01:53:45.022042 makedir: /var/lib/lava/dispatcher/tmp/14479155/lava-overlay-52ldeykd/lava-14479155/tests
161 01:53:45.022143 makedir: /var/lib/lava/dispatcher/tmp/14479155/lava-overlay-52ldeykd/lava-14479155/results
162 01:53:45.022227 Creating /var/lib/lava/dispatcher/tmp/14479155/lava-overlay-52ldeykd/lava-14479155/bin/lava-add-keys
163 01:53:45.022352 Creating /var/lib/lava/dispatcher/tmp/14479155/lava-overlay-52ldeykd/lava-14479155/bin/lava-add-sources
164 01:53:45.022496 Creating /var/lib/lava/dispatcher/tmp/14479155/lava-overlay-52ldeykd/lava-14479155/bin/lava-background-process-start
165 01:53:45.022616 Creating /var/lib/lava/dispatcher/tmp/14479155/lava-overlay-52ldeykd/lava-14479155/bin/lava-background-process-stop
166 01:53:45.022742 Creating /var/lib/lava/dispatcher/tmp/14479155/lava-overlay-52ldeykd/lava-14479155/bin/lava-common-functions
167 01:53:45.022858 Creating /var/lib/lava/dispatcher/tmp/14479155/lava-overlay-52ldeykd/lava-14479155/bin/lava-echo-ipv4
168 01:53:45.022974 Creating /var/lib/lava/dispatcher/tmp/14479155/lava-overlay-52ldeykd/lava-14479155/bin/lava-install-packages
169 01:53:45.023087 Creating /var/lib/lava/dispatcher/tmp/14479155/lava-overlay-52ldeykd/lava-14479155/bin/lava-installed-packages
170 01:53:45.023199 Creating /var/lib/lava/dispatcher/tmp/14479155/lava-overlay-52ldeykd/lava-14479155/bin/lava-os-build
171 01:53:45.023330 Creating /var/lib/lava/dispatcher/tmp/14479155/lava-overlay-52ldeykd/lava-14479155/bin/lava-probe-channel
172 01:53:45.023443 Creating /var/lib/lava/dispatcher/tmp/14479155/lava-overlay-52ldeykd/lava-14479155/bin/lava-probe-ip
173 01:53:45.023556 Creating /var/lib/lava/dispatcher/tmp/14479155/lava-overlay-52ldeykd/lava-14479155/bin/lava-target-ip
174 01:53:45.023669 Creating /var/lib/lava/dispatcher/tmp/14479155/lava-overlay-52ldeykd/lava-14479155/bin/lava-target-mac
175 01:53:45.023790 Creating /var/lib/lava/dispatcher/tmp/14479155/lava-overlay-52ldeykd/lava-14479155/bin/lava-target-storage
176 01:53:45.023907 Creating /var/lib/lava/dispatcher/tmp/14479155/lava-overlay-52ldeykd/lava-14479155/bin/lava-test-case
177 01:53:45.024020 Creating /var/lib/lava/dispatcher/tmp/14479155/lava-overlay-52ldeykd/lava-14479155/bin/lava-test-event
178 01:53:45.024132 Creating /var/lib/lava/dispatcher/tmp/14479155/lava-overlay-52ldeykd/lava-14479155/bin/lava-test-feedback
179 01:53:45.024244 Creating /var/lib/lava/dispatcher/tmp/14479155/lava-overlay-52ldeykd/lava-14479155/bin/lava-test-raise
180 01:53:45.024354 Creating /var/lib/lava/dispatcher/tmp/14479155/lava-overlay-52ldeykd/lava-14479155/bin/lava-test-reference
181 01:53:45.024471 Creating /var/lib/lava/dispatcher/tmp/14479155/lava-overlay-52ldeykd/lava-14479155/bin/lava-test-runner
182 01:53:45.024594 Creating /var/lib/lava/dispatcher/tmp/14479155/lava-overlay-52ldeykd/lava-14479155/bin/lava-test-set
183 01:53:45.024779 Creating /var/lib/lava/dispatcher/tmp/14479155/lava-overlay-52ldeykd/lava-14479155/bin/lava-test-shell
184 01:53:45.024933 Updating /var/lib/lava/dispatcher/tmp/14479155/lava-overlay-52ldeykd/lava-14479155/bin/lava-install-packages (oe)
185 01:53:45.025072 Updating /var/lib/lava/dispatcher/tmp/14479155/lava-overlay-52ldeykd/lava-14479155/bin/lava-installed-packages (oe)
186 01:53:45.025189 Creating /var/lib/lava/dispatcher/tmp/14479155/lava-overlay-52ldeykd/lava-14479155/environment
187 01:53:45.025275 LAVA metadata
188 01:53:45.025341 - LAVA_JOB_ID=14479155
189 01:53:45.025398 - LAVA_DISPATCHER_IP=192.168.201.1
190 01:53:45.025492 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:54) [common]
191 01:53:45.025582 skipped lava-vland-overlay
192 01:53:45.025675 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 01:53:45.025746 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:54) [common]
194 01:53:45.025801 skipped lava-multinode-overlay
195 01:53:45.025867 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 01:53:45.025937 start: 1.6.2.3 test-definition (timeout 00:09:54) [common]
197 01:53:45.025999 Loading test definitions
198 01:53:45.026084 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:54) [common]
199 01:53:45.026142 Using /lava-14479155 at stage 0
200 01:53:45.026422 uuid=14479155_1.6.2.3.1 testdef=None
201 01:53:45.026503 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 01:53:45.026577 start: 1.6.2.3.2 test-overlay (timeout 00:09:54) [common]
203 01:53:45.027010 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 01:53:45.027210 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:54) [common]
206 01:53:45.027772 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 01:53:45.027980 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:54) [common]
209 01:53:45.028513 runner path: /var/lib/lava/dispatcher/tmp/14479155/lava-overlay-52ldeykd/lava-14479155/0/tests/0_lc-compliance test_uuid 14479155_1.6.2.3.1
210 01:53:45.028657 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 01:53:45.028905 Creating lava-test-runner.conf files
213 01:53:45.028982 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14479155/lava-overlay-52ldeykd/lava-14479155/0 for stage 0
214 01:53:45.029091 - 0_lc-compliance
215 01:53:45.029184 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
216 01:53:45.029262 start: 1.6.2.4 compress-overlay (timeout 00:09:54) [common]
217 01:53:45.034662 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
218 01:53:45.034755 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:54) [common]
219 01:53:45.034833 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
220 01:53:45.034910 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
221 01:53:45.034987 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:54) [common]
222 01:53:45.195514 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
223 01:53:45.195660 start: 1.6.4 extract-modules (timeout 00:09:54) [common]
224 01:53:45.195740 extracting modules file /var/lib/lava/dispatcher/tmp/14479155/tftp-deploy-8daa0ozx/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14479155/extract-nfsrootfs-t4oh8com
225 01:53:45.416537 extracting modules file /var/lib/lava/dispatcher/tmp/14479155/tftp-deploy-8daa0ozx/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14479155/extract-overlay-ramdisk-zx_8eojc/ramdisk
226 01:53:45.645062 end: 1.6.4 extract-modules (duration 00:00:00) [common]
227 01:53:45.645205 start: 1.6.5 apply-overlay-tftp (timeout 00:09:53) [common]
228 01:53:45.645287 [common] Applying overlay to NFS
229 01:53:45.645347 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14479155/compress-overlay-7p9oz19t/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14479155/extract-nfsrootfs-t4oh8com
230 01:53:45.651638 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
231 01:53:45.651734 start: 1.6.6 configure-preseed-file (timeout 00:09:53) [common]
232 01:53:45.651814 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
233 01:53:45.651890 start: 1.6.7 compress-ramdisk (timeout 00:09:53) [common]
234 01:53:45.651954 Building ramdisk /var/lib/lava/dispatcher/tmp/14479155/extract-overlay-ramdisk-zx_8eojc/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14479155/extract-overlay-ramdisk-zx_8eojc/ramdisk
235 01:53:45.996791 >> 130487 blocks
236 01:53:48.070654 rename /var/lib/lava/dispatcher/tmp/14479155/extract-overlay-ramdisk-zx_8eojc/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14479155/tftp-deploy-8daa0ozx/ramdisk/ramdisk.cpio.gz
237 01:53:48.070820 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
238 01:53:48.070908 start: 1.6.8 prepare-kernel (timeout 00:09:51) [common]
239 01:53:48.070987 start: 1.6.8.1 prepare-fit (timeout 00:09:51) [common]
240 01:53:48.071066 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14479155/tftp-deploy-8daa0ozx/kernel/Image']
241 01:54:01.487210 Returned 0 in 13 seconds
242 01:54:01.587759 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14479155/tftp-deploy-8daa0ozx/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14479155/tftp-deploy-8daa0ozx/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb -i /var/lib/lava/dispatcher/tmp/14479155/tftp-deploy-8daa0ozx/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14479155/tftp-deploy-8daa0ozx/kernel/image.itb
243 01:54:02.004775 output: FIT description: Kernel Image image with one or more FDT blobs
244 01:54:02.004912 output: Created: Fri Jun 21 02:54:01 2024
245 01:54:02.004976 output: Image 0 (kernel-1)
246 01:54:02.005033 output: Description:
247 01:54:02.005085 output: Created: Fri Jun 21 02:54:01 2024
248 01:54:02.005141 output: Type: Kernel Image
249 01:54:02.005197 output: Compression: lzma compressed
250 01:54:02.005256 output: Data Size: 13124896 Bytes = 12817.28 KiB = 12.52 MiB
251 01:54:02.005312 output: Architecture: AArch64
252 01:54:02.005366 output: OS: Linux
253 01:54:02.005420 output: Load Address: 0x00000000
254 01:54:02.005476 output: Entry Point: 0x00000000
255 01:54:02.005531 output: Hash algo: crc32
256 01:54:02.005629 output: Hash value: ab2f7826
257 01:54:02.005682 output: Image 1 (fdt-1)
258 01:54:02.005735 output: Description: mt8183-kukui-jacuzzi-juniper-sku16
259 01:54:02.005785 output: Created: Fri Jun 21 02:54:01 2024
260 01:54:02.005839 output: Type: Flat Device Tree
261 01:54:02.005891 output: Compression: uncompressed
262 01:54:02.005941 output: Data Size: 57695 Bytes = 56.34 KiB = 0.06 MiB
263 01:54:02.005990 output: Architecture: AArch64
264 01:54:02.006039 output: Hash algo: crc32
265 01:54:02.006089 output: Hash value: a9713552
266 01:54:02.006136 output: Image 2 (ramdisk-1)
267 01:54:02.006183 output: Description: unavailable
268 01:54:02.006230 output: Created: Fri Jun 21 02:54:01 2024
269 01:54:02.006278 output: Type: RAMDisk Image
270 01:54:02.006325 output: Compression: uncompressed
271 01:54:02.006372 output: Data Size: 18748413 Bytes = 18309.00 KiB = 17.88 MiB
272 01:54:02.006420 output: Architecture: AArch64
273 01:54:02.006467 output: OS: Linux
274 01:54:02.006514 output: Load Address: unavailable
275 01:54:02.006561 output: Entry Point: unavailable
276 01:54:02.006609 output: Hash algo: crc32
277 01:54:02.006656 output: Hash value: 3eb39b9c
278 01:54:02.006703 output: Default Configuration: 'conf-1'
279 01:54:02.006750 output: Configuration 0 (conf-1)
280 01:54:02.006796 output: Description: mt8183-kukui-jacuzzi-juniper-sku16
281 01:54:02.006844 output: Kernel: kernel-1
282 01:54:02.006891 output: Init Ramdisk: ramdisk-1
283 01:54:02.006939 output: FDT: fdt-1
284 01:54:02.006986 output: Loadables: kernel-1
285 01:54:02.007033 output:
286 01:54:02.007170 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
287 01:54:02.007256 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
288 01:54:02.007345 end: 1.6 prepare-tftp-overlay (duration 00:00:19) [common]
289 01:54:02.007427 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:37) [common]
290 01:54:02.007495 No LXC device requested
291 01:54:02.007565 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
292 01:54:02.007641 start: 1.8 deploy-device-env (timeout 00:09:37) [common]
293 01:54:02.007709 end: 1.8 deploy-device-env (duration 00:00:00) [common]
294 01:54:02.007772 Checking files for TFTP limit of 4294967296 bytes.
295 01:54:02.008288 end: 1 tftp-deploy (duration 00:00:23) [common]
296 01:54:02.008389 start: 2 depthcharge-action (timeout 00:05:00) [common]
297 01:54:02.008472 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
298 01:54:02.008583 substitutions:
299 01:54:02.008645 - {DTB}: 14479155/tftp-deploy-8daa0ozx/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb
300 01:54:02.008702 - {INITRD}: 14479155/tftp-deploy-8daa0ozx/ramdisk/ramdisk.cpio.gz
301 01:54:02.008756 - {KERNEL}: 14479155/tftp-deploy-8daa0ozx/kernel/Image
302 01:54:02.008807 - {LAVA_MAC}: None
303 01:54:02.008856 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14479155/extract-nfsrootfs-t4oh8com
304 01:54:02.008906 - {NFS_SERVER_IP}: 192.168.201.1
305 01:54:02.008954 - {PRESEED_CONFIG}: None
306 01:54:02.009010 - {PRESEED_LOCAL}: None
307 01:54:02.009061 - {RAMDISK}: 14479155/tftp-deploy-8daa0ozx/ramdisk/ramdisk.cpio.gz
308 01:54:02.009110 - {ROOT_PART}: None
309 01:54:02.009158 - {ROOT}: None
310 01:54:02.009205 - {SERVER_IP}: 192.168.201.1
311 01:54:02.009253 - {TEE}: None
312 01:54:02.009301 Parsed boot commands:
313 01:54:02.009347 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
314 01:54:02.009496 Parsed boot commands: tftpboot 192.168.201.1 14479155/tftp-deploy-8daa0ozx/kernel/image.itb 14479155/tftp-deploy-8daa0ozx/kernel/cmdline
315 01:54:02.009604 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
316 01:54:02.009696 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
317 01:54:02.009778 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
318 01:54:02.009856 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
319 01:54:02.009917 Not connected, no need to disconnect.
320 01:54:02.009982 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
321 01:54:02.010056 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
322 01:54:02.010114 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8183-kukui-jacuzzi-juniper-sku16-cbg-4'
323 01:54:02.013601 Setting prompt string to ['lava-test: # ']
324 01:54:02.014055 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
325 01:54:02.014181 end: 2.2.1 reset-connection (duration 00:00:00) [common]
326 01:54:02.014315 start: 2.2.2 reset-device (timeout 00:05:00) [common]
327 01:54:02.014403 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
328 01:54:02.014590 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8183-kukui-jacuzzi-juniper-sku16-cbg-4', '--port=1', '--command=reboot']
329 01:54:11.185382 >> Command sent successfully.
330 01:54:11.198998 Returned 0 in 9 seconds
331 01:54:11.300399 end: 2.2.2.1 pdu-reboot (duration 00:00:09) [common]
333 01:54:11.302112 end: 2.2.2 reset-device (duration 00:00:09) [common]
334 01:54:11.302948 start: 2.2.3 depthcharge-start (timeout 00:04:51) [common]
335 01:54:11.303457 Setting prompt string to 'Starting depthcharge on Juniper...'
336 01:54:11.303814 Changing prompt to 'Starting depthcharge on Juniper...'
337 01:54:11.304191 depthcharge-start: Wait for prompt Starting depthcharge on Juniper... (timeout 00:05:00)
338 01:54:11.305960 [Enter `^Ec?' for help]
339 01:54:17.971894 [DL] 00000000 00000000 010701
340 01:54:17.976806
341 01:54:17.977243
342 01:54:17.977628 F0: 102B 0000
343 01:54:17.977988
344 01:54:17.978475 F3: 1006 0033 [0200]
345 01:54:17.980349
346 01:54:17.980797 F3: 4001 00E0 [0200]
347 01:54:17.981164
348 01:54:17.981497 F3: 0000 0000
349 01:54:17.981898
350 01:54:17.983525 V0: 0000 0000 [0001]
351 01:54:17.984063
352 01:54:17.984421 00: 1027 0002
353 01:54:17.984961
354 01:54:17.986928 01: 0000 0000
355 01:54:17.987377
356 01:54:17.987713 BP: 0C00 0251 [0000]
357 01:54:17.988035
358 01:54:17.990022 G0: 1182 0000
359 01:54:17.990406
360 01:54:17.990706 EC: 0004 0000 [0001]
361 01:54:17.990988
362 01:54:17.993347 S7: 0000 0000 [0000]
363 01:54:17.993768
364 01:54:17.996712 CC: 0000 0000 [0001]
365 01:54:17.997113
366 01:54:17.997412 T0: 0000 00DB [000F]
367 01:54:17.997742
368 01:54:17.998013 Jump to BL
369 01:54:17.998271
370 01:54:18.033152
371 01:54:18.033693
372 01:54:18.042494 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 verstage starting (log level: 8)...
373 01:54:18.045921 ARM64: Exception handlers installed.
374 01:54:18.046429 ARM64: Testing exception
375 01:54:18.048983 ARM64: Done test exception
376 01:54:18.053221 WDT: Last reset was cold boot
377 01:54:18.056287 SPI0(PAD0) initialized at 992727 Hz
378 01:54:18.059371 FMAP: area RW_NVRAM found @ 554000 (8192 bytes)
379 01:54:18.059973 Manufacturer: ef
380 01:54:18.066427 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
381 01:54:18.079259 Probing TPM: . done!
382 01:54:18.079764 TPM ready after 0 ms
383 01:54:18.086606 Connected to device vid:did:rid of 1ae0:0028:00
384 01:54:18.092923 Firmware version: B2-C:0 RO_A:0.0.12/bf248b9d RW_B:0.5.171/cr50_v2.94_mp.164-2fb1dd676c
385 01:54:18.127867 Initialized TPM device CR50 revision 0
386 01:54:18.139000 tlcl_send_startup: Startup return code is 0
387 01:54:18.139504 TPM: setup succeeded
388 01:54:18.146893 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x1007 return code 0
389 01:54:18.150979 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
390 01:54:18.154095 in-header: 03 19 00 00 08 00 00 00
391 01:54:18.156991 in-data: a2 e0 47 00 13 00 00 00
392 01:54:18.160586 Chrome EC: UHEPI supported
393 01:54:18.167300 out: cmd=0xa4: 03 5d a4 00 00 00 0c 00 00 01 00 00 f4 fb 00 00 00 00 00 00
394 01:54:18.170388 in-header: 03 a1 00 00 08 00 00 00
395 01:54:18.173720 in-data: 84 60 60 10 00 00 00 00
396 01:54:18.174160 Phase 1
397 01:54:18.176858 FMAP: area GBB found @ 3f5000 (12032 bytes)
398 01:54:18.183379 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x0 / 0x0
399 01:54:18.190107 VB2:vb2_check_recovery() Recovery was requested manually
400 01:54:18.193527 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x0
401 01:54:18.200140 Recovery requested (1009000e)
402 01:54:18.206207 tlcl_extend: response is 0
403 01:54:18.214383 tlcl_extend: response is 0
404 01:54:18.239262
405 01:54:18.239758
406 01:54:18.249520 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 romstage starting (log level: 8)...
407 01:54:18.252227 ARM64: Exception handlers installed.
408 01:54:18.252731 ARM64: Testing exception
409 01:54:18.255403 ARM64: Done test exception
410 01:54:18.271173 [RTC]rtc_enable_dcxo,41: con=0x482, osc32con=0x9a6d, sec=0x2023
411 01:54:18.277911 [RTC]rtc_check_state,142: con=482, pwrkey1=a357, pwrkey2=67d2
412 01:54:18.281511 [RTC]rtc_eosc_cali,157: PMIC_RG_FQMTR_CKSEL=0x4a
413 01:54:18.289517 [RTC]rtc_get_frequency_meter,134: input=0xf, output=822
414 01:54:18.296479 [RTC]rtc_get_frequency_meter,134: input=0x7, output=697
415 01:54:18.303281 [RTC]rtc_get_frequency_meter,134: input=0xb, output=760
416 01:54:18.310536 [RTC]rtc_get_frequency_meter,134: input=0xd, output=791
417 01:54:18.316967 [RTC]rtc_get_frequency_meter,134: input=0xe, output=807
418 01:54:18.324592 [RTC]rtc_get_frequency_meter,134: input=0xd, output=791
419 01:54:18.331192 [RTC]rtc_get_frequency_meter,134: input=0xe, output=806
420 01:54:18.337673 [RTC]rtc_osc_init,208: EOSC32 cali val = 0x9a6d
421 01:54:18.341013 [RTC]rtc_boot_common,186: irqsta=0, bbpu=0, con=482
422 01:54:18.344271 [RTC]rtc_bbpu_power_on,373: rtc_write_trigger=1
423 01:54:18.351363 [RTC]rtc_bbpu_power_on,376: done BBPU=0x9
424 01:54:18.354503 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
425 01:54:18.356949 in-header: 03 19 00 00 08 00 00 00
426 01:54:18.360607 in-data: a2 e0 47 00 13 00 00 00
427 01:54:18.361041 Chrome EC: UHEPI supported
428 01:54:18.367033 out: cmd=0xa4: 03 5d a4 00 00 00 0c 00 00 01 00 00 f4 fb 00 00 00 00 00 00
429 01:54:18.370283 in-header: 03 a1 00 00 08 00 00 00
430 01:54:18.374172 in-data: 84 60 60 10 00 00 00 00
431 01:54:18.376935 Skip loading cached calibration data
432 01:54:18.383713 out: cmd=0xa4: 03 7f a4 00 00 00 0c 00 00 01 00 00 d0 ff ff ff 00 00 00 00
433 01:54:18.386904 in-header: 03 a1 00 00 08 00 00 00
434 01:54:18.390215 in-data: 84 60 60 10 00 00 00 00
435 01:54:18.397120 out: cmd=0xa4: 03 79 a4 00 00 00 0c 00 00 01 00 00 f0 7e 11 00 84 60 60 10
436 01:54:18.400299 in-header: 03 a1 00 00 08 00 00 00
437 01:54:18.404082 in-data: 84 60 60 10 00 00 00 00
438 01:54:18.406426 ADC[3]: Raw value=213827 ID=1
439 01:54:18.406913 Manufacturer: ef
440 01:54:18.413651 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
441 01:54:18.416648 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
442 01:54:18.419832 CBFS @ 21000 size 3d4000
443 01:54:18.426795 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
444 01:54:18.430617 CBFS: Locating 'sdram-lpddr4x-H9HCNNNCPMALHR-4GB'
445 01:54:18.432931 CBFS: Found @ offset 3c700 size 44
446 01:54:18.437008 DRAM-K: Full Calibration
447 01:54:18.440059 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
448 01:54:18.442935 CBFS @ 21000 size 3d4000
449 01:54:18.445989 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
450 01:54:18.449892 CBFS: Locating 'fallback/dram'
451 01:54:18.453045 CBFS: Found @ offset 24b00 size 12268
452 01:54:18.482597 read SPI 0x45b44 0x1224c: 22774 us, 3263 KB/s, 26.104 Mbps
453 01:54:18.485468 ddr_geometry: 1, config: 0x0
454 01:54:18.488900 header.status = 0x0
455 01:54:18.492225 header.magic = 0x44524d4b (expected: 0x44524d4b)
456 01:54:18.495149 header.version = 0x5 (expected: 0x5)
457 01:54:18.498998 header.size = 0x8f0 (expected: 0x8f0)
458 01:54:18.499505 header.config = 0x0
459 01:54:18.502166 header.flags = 0x0
460 01:54:18.505328 header.checksum = 0x0
461 01:54:18.512105 dram_init: MediaTek DRAM firmware version: 1.5.0, accepting param version 5
462 01:54:18.515019 Set DRAM voltage: vdram1 = 1125000, vddq = 600000
463 01:54:18.521324 Get DRAM voltage to vdram1 = 1125000, vddq = 600000
464 01:54:18.521964 ddr_geometry:1
465 01:54:18.524593 [EMI] new MDL number = 1
466 01:54:18.525028 dram_cbt_mode_extern: 0
467 01:54:18.527903 dram_cbt_mode [RK0]: 0, [RK1]: 0
468 01:54:18.535270 Rank info: 0 emi_setting_index: 1 CONA[0xf053f154]
469 01:54:18.535683
470 01:54:18.536157
471 01:54:18.537752 [Bianco] ETT version 0.0.0.1
472 01:54:18.541157 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
473 01:54:18.541746
474 01:54:18.544459 vSetVcoreByFreq with vcore:762500, freq=1600
475 01:54:18.544856
476 01:54:18.548212 [DramcInit]
477 01:54:18.551706 AutoRefreshCKEOff AutoREF OFF
478 01:54:18.552140 DDRPhyPLLSetting-CKEOFF
479 01:54:18.554314 DDRPhyPLLSetting-CKEON
480 01:54:18.554724
481 01:54:18.555258 Enable WDQS
482 01:54:18.559152 [ModeRegInit_LP4] CH0 RK0
483 01:54:18.562409 Write Rank0 MR13 =0x18
484 01:54:18.562945 Write Rank0 MR12 =0x5d
485 01:54:18.565518 Write Rank0 MR1 =0x56
486 01:54:18.569389 Write Rank0 MR2 =0x1a
487 01:54:18.569821 Write Rank0 MR11 =0x0
488 01:54:18.572771 Write Rank0 MR22 =0x38
489 01:54:18.575484 Write Rank0 MR14 =0x5d
490 01:54:18.575874 Write Rank0 MR3 =0x30
491 01:54:18.578835 Write Rank0 MR13 =0x58
492 01:54:18.579238 Write Rank0 MR12 =0x5d
493 01:54:18.582392 Write Rank0 MR1 =0x56
494 01:54:18.585759 Write Rank0 MR2 =0x2d
495 01:54:18.586232 Write Rank0 MR11 =0x23
496 01:54:18.588799 Write Rank0 MR22 =0x34
497 01:54:18.592366 Write Rank0 MR14 =0x10
498 01:54:18.592837 Write Rank0 MR3 =0x30
499 01:54:18.595678 Write Rank0 MR13 =0xd8
500 01:54:18.596149 [ModeRegInit_LP4] CH0 RK1
501 01:54:18.599077 Write Rank1 MR13 =0x18
502 01:54:18.602086 Write Rank1 MR12 =0x5d
503 01:54:18.602481 Write Rank1 MR1 =0x56
504 01:54:18.605803 Write Rank1 MR2 =0x1a
505 01:54:18.606274 Write Rank1 MR11 =0x0
506 01:54:18.608699 Write Rank1 MR22 =0x38
507 01:54:18.612066 Write Rank1 MR14 =0x5d
508 01:54:18.612458 Write Rank1 MR3 =0x30
509 01:54:18.615235 Write Rank1 MR13 =0x58
510 01:54:18.618546 Write Rank1 MR12 =0x5d
511 01:54:18.619024 Write Rank1 MR1 =0x56
512 01:54:18.621687 Write Rank1 MR2 =0x2d
513 01:54:18.622156 Write Rank1 MR11 =0x23
514 01:54:18.625016 Write Rank1 MR22 =0x34
515 01:54:18.627930 Write Rank1 MR14 =0x10
516 01:54:18.628277 Write Rank1 MR3 =0x30
517 01:54:18.631737 Write Rank1 MR13 =0xd8
518 01:54:18.634597 [ModeRegInit_LP4] CH1 RK0
519 01:54:18.634995 Write Rank0 MR13 =0x18
520 01:54:18.638628 Write Rank0 MR12 =0x5d
521 01:54:18.641491 Write Rank0 MR1 =0x56
522 01:54:18.641956 Write Rank0 MR2 =0x1a
523 01:54:18.645099 Write Rank0 MR11 =0x0
524 01:54:18.645617 Write Rank0 MR22 =0x38
525 01:54:18.648049 Write Rank0 MR14 =0x5d
526 01:54:18.651647 Write Rank0 MR3 =0x30
527 01:54:18.652117 Write Rank0 MR13 =0x58
528 01:54:18.654458 Write Rank0 MR12 =0x5d
529 01:54:18.654929 Write Rank0 MR1 =0x56
530 01:54:18.658090 Write Rank0 MR2 =0x2d
531 01:54:18.661305 Write Rank0 MR11 =0x23
532 01:54:18.661748 Write Rank0 MR22 =0x34
533 01:54:18.664610 Write Rank0 MR14 =0x10
534 01:54:18.668055 Write Rank0 MR3 =0x30
535 01:54:18.668449 Write Rank0 MR13 =0xd8
536 01:54:18.671218 [ModeRegInit_LP4] CH1 RK1
537 01:54:18.671651 Write Rank1 MR13 =0x18
538 01:54:18.674135 Write Rank1 MR12 =0x5d
539 01:54:18.677720 Write Rank1 MR1 =0x56
540 01:54:18.678201 Write Rank1 MR2 =0x1a
541 01:54:18.681275 Write Rank1 MR11 =0x0
542 01:54:18.684288 Write Rank1 MR22 =0x38
543 01:54:18.684690 Write Rank1 MR14 =0x5d
544 01:54:18.687724 Write Rank1 MR3 =0x30
545 01:54:18.688129 Write Rank1 MR13 =0x58
546 01:54:18.690971 Write Rank1 MR12 =0x5d
547 01:54:18.694042 Write Rank1 MR1 =0x56
548 01:54:18.694435 Write Rank1 MR2 =0x2d
549 01:54:18.697587 Write Rank1 MR11 =0x23
550 01:54:18.698068 Write Rank1 MR22 =0x34
551 01:54:18.700987 Write Rank1 MR14 =0x10
552 01:54:18.704217 Write Rank1 MR3 =0x30
553 01:54:18.704688 Write Rank1 MR13 =0xd8
554 01:54:18.707256 match AC timing 3
555 01:54:18.717609 [DdrUpdateACTimingReg] Freq = 1600, tRFCab = 141, tRFCab_05T = 0, TXREFCNT = 159, tRFCpb = 65, tRFCpb_05T = 0
556 01:54:18.718091 [MiockJmeterHQA]
557 01:54:18.720557 vSetVcoreByFreq with vcore:762500, freq=1600
558 01:54:18.827439
559 01:54:18.827942 MIOCK jitter meter ch=0
560 01:54:18.828273
561 01:54:18.830949 1T = (102-19) = 83 dly cells
562 01:54:18.837684 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 753/100 ps
563 01:54:18.840742 vSetVcoreByFreq with vcore:725000, freq=1200
564 01:54:18.941004
565 01:54:18.941508 MIOCK jitter meter ch=0
566 01:54:18.942008
567 01:54:18.944212 1T = (97-18) = 79 dly cells
568 01:54:18.952125 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 791/100 ps
569 01:54:18.954627 vSetVcoreByFreq with vcore:725000, freq=800
570 01:54:19.054566
571 01:54:19.055074 MIOCK jitter meter ch=0
572 01:54:19.055413
573 01:54:19.057681 1T = (97-18) = 79 dly cells
574 01:54:19.064139 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 791/100 ps
575 01:54:19.067535 vSetVcoreByFreq with vcore:762500, freq=1600
576 01:54:19.071575 vSetVcoreByFreq with vcore:762500, freq=1600
577 01:54:19.072085
578 01:54:19.072421 K DRVP
579 01:54:19.074064 1. OCD DRVP=0 CALOUT=0
580 01:54:19.077113 1. OCD DRVP=1 CALOUT=0
581 01:54:19.077597 1. OCD DRVP=2 CALOUT=0
582 01:54:19.080302 1. OCD DRVP=3 CALOUT=0
583 01:54:19.083961 1. OCD DRVP=4 CALOUT=0
584 01:54:19.084472 1. OCD DRVP=5 CALOUT=0
585 01:54:19.087581 1. OCD DRVP=6 CALOUT=0
586 01:54:19.088097 1. OCD DRVP=7 CALOUT=0
587 01:54:19.090318 1. OCD DRVP=8 CALOUT=1
588 01:54:19.090786
589 01:54:19.093599 1. OCD DRVP calibration OK! DRVP=8
590 01:54:19.094045
591 01:54:19.094385
592 01:54:19.094696
593 01:54:19.095058 K ODTN
594 01:54:19.097381 3. OCD ODTN=0 ,CALOUT=1
595 01:54:19.100106 3. OCD ODTN=1 ,CALOUT=1
596 01:54:19.100548 3. OCD ODTN=2 ,CALOUT=1
597 01:54:19.103511 3. OCD ODTN=3 ,CALOUT=1
598 01:54:19.106832 3. OCD ODTN=4 ,CALOUT=1
599 01:54:19.107434 3. OCD ODTN=5 ,CALOUT=1
600 01:54:19.110310 3. OCD ODTN=6 ,CALOUT=1
601 01:54:19.113459 3. OCD ODTN=7 ,CALOUT=0
602 01:54:19.113932
603 01:54:19.116966 3. OCD ODTN calibration OK! ODTN=7
604 01:54:19.117409
605 01:54:19.120080 [SwImpedanceCal] DRVP=8, DRVN=9, ODTN=7
606 01:54:19.123230 term_option=0, Reg: DRVP=8, DRVN=7, ODTN=15
607 01:54:19.129883 term_option=0, Reg: DRVP=8, DRVN=7, ODTN=15 (After Adjust)
608 01:54:19.130409
609 01:54:19.130752 K DRVP
610 01:54:19.131065 1. OCD DRVP=0 CALOUT=0
611 01:54:19.133033 1. OCD DRVP=1 CALOUT=0
612 01:54:19.136267 1. OCD DRVP=2 CALOUT=0
613 01:54:19.136715 1. OCD DRVP=3 CALOUT=0
614 01:54:19.140232 1. OCD DRVP=4 CALOUT=0
615 01:54:19.143125 1. OCD DRVP=5 CALOUT=0
616 01:54:19.143567 1. OCD DRVP=6 CALOUT=0
617 01:54:19.146988 1. OCD DRVP=7 CALOUT=0
618 01:54:19.147502 1. OCD DRVP=8 CALOUT=0
619 01:54:19.150368 1. OCD DRVP=9 CALOUT=1
620 01:54:19.150890
621 01:54:19.153633 1. OCD DRVP calibration OK! DRVP=9
622 01:54:19.154161
623 01:54:19.154498
624 01:54:19.154806
625 01:54:19.155107 K ODTN
626 01:54:19.157035 3. OCD ODTN=0 ,CALOUT=1
627 01:54:19.160059 3. OCD ODTN=1 ,CALOUT=1
628 01:54:19.160500 3. OCD ODTN=2 ,CALOUT=1
629 01:54:19.163625 3. OCD ODTN=3 ,CALOUT=1
630 01:54:19.165994 3. OCD ODTN=4 ,CALOUT=1
631 01:54:19.166441 3. OCD ODTN=5 ,CALOUT=1
632 01:54:19.169477 3. OCD ODTN=6 ,CALOUT=1
633 01:54:19.172950 3. OCD ODTN=7 ,CALOUT=1
634 01:54:19.173472 3. OCD ODTN=8 ,CALOUT=1
635 01:54:19.175995 3. OCD ODTN=9 ,CALOUT=1
636 01:54:19.179755 3. OCD ODTN=10 ,CALOUT=1
637 01:54:19.180199 3. OCD ODTN=11 ,CALOUT=1
638 01:54:19.182755 3. OCD ODTN=12 ,CALOUT=1
639 01:54:19.186209 3. OCD ODTN=13 ,CALOUT=0
640 01:54:19.186769
641 01:54:19.189463 3. OCD ODTN calibration OK! ODTN=13
642 01:54:19.190059
643 01:54:19.192585 [SwImpedanceCal] DRVP=9, DRVN=9, ODTN=13
644 01:54:19.195778 term_option=1, Reg: DRVP=9, DRVN=9, ODTN=13
645 01:54:19.202299 term_option=1, Reg: DRVP=9, DRVN=9, ODTN=13 (After Adjust)
646 01:54:19.202735
647 01:54:19.203073 [DramcInit]
648 01:54:19.206114 AutoRefreshCKEOff AutoREF OFF
649 01:54:19.209262 DDRPhyPLLSetting-CKEOFF
650 01:54:19.209683 DDRPhyPLLSetting-CKEON
651 01:54:19.209996
652 01:54:19.213925 Enable WDQS
653 01:54:19.214388 ==
654 01:54:19.215733 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
655 01:54:19.220066 fsp= 1, odt_onoff= 1, Byte mode= 0
656 01:54:19.220537 ==
657 01:54:19.222251 [Duty_Offset_Calibration]
658 01:54:19.222643
659 01:54:19.225533 ===========================
660 01:54:19.225955 B0:2 B1:2 CA:1
661 01:54:19.247851 ==
662 01:54:19.250730 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
663 01:54:19.254564 fsp= 1, odt_onoff= 1, Byte mode= 0
664 01:54:19.255078 ==
665 01:54:19.257508 [Duty_Offset_Calibration]
666 01:54:19.257965
667 01:54:19.260775 ===========================
668 01:54:19.261208 B0:0 B1:0 CA:0
669 01:54:19.293334 [ModeRegInit_LP4] CH0 RK0
670 01:54:19.296674 Write Rank0 MR13 =0x18
671 01:54:19.297180 Write Rank0 MR12 =0x5d
672 01:54:19.299612 Write Rank0 MR1 =0x56
673 01:54:19.303229 Write Rank0 MR2 =0x1a
674 01:54:19.303738 Write Rank0 MR11 =0x0
675 01:54:19.306496 Write Rank0 MR22 =0x38
676 01:54:19.310060 Write Rank0 MR14 =0x5d
677 01:54:19.310573 Write Rank0 MR3 =0x30
678 01:54:19.313337 Write Rank0 MR13 =0x58
679 01:54:19.313893 Write Rank0 MR12 =0x5d
680 01:54:19.316458 Write Rank0 MR1 =0x56
681 01:54:19.319761 Write Rank0 MR2 =0x2d
682 01:54:19.320195 Write Rank0 MR11 =0x23
683 01:54:19.323022 Write Rank0 MR22 =0x34
684 01:54:19.323453 Write Rank0 MR14 =0x10
685 01:54:19.326153 Write Rank0 MR3 =0x30
686 01:54:19.329525 Write Rank0 MR13 =0xd8
687 01:54:19.330065 [ModeRegInit_LP4] CH0 RK1
688 01:54:19.332567 Write Rank1 MR13 =0x18
689 01:54:19.335880 Write Rank1 MR12 =0x5d
690 01:54:19.336315 Write Rank1 MR1 =0x56
691 01:54:19.339173 Write Rank1 MR2 =0x1a
692 01:54:19.339682 Write Rank1 MR11 =0x0
693 01:54:19.342174 Write Rank1 MR22 =0x38
694 01:54:19.345398 Write Rank1 MR14 =0x5d
695 01:54:19.345853 Write Rank1 MR3 =0x30
696 01:54:19.349288 Write Rank1 MR13 =0x58
697 01:54:19.352401 Write Rank1 MR12 =0x5d
698 01:54:19.352834 Write Rank1 MR1 =0x56
699 01:54:19.355678 Write Rank1 MR2 =0x2d
700 01:54:19.356112 Write Rank1 MR11 =0x23
701 01:54:19.358890 Write Rank1 MR22 =0x34
702 01:54:19.362000 Write Rank1 MR14 =0x10
703 01:54:19.362423 Write Rank1 MR3 =0x30
704 01:54:19.365398 Write Rank1 MR13 =0xd8
705 01:54:19.368980 [ModeRegInit_LP4] CH1 RK0
706 01:54:19.369372 Write Rank0 MR13 =0x18
707 01:54:19.372104 Write Rank0 MR12 =0x5d
708 01:54:19.372528 Write Rank0 MR1 =0x56
709 01:54:19.375002 Write Rank0 MR2 =0x1a
710 01:54:19.378557 Write Rank0 MR11 =0x0
711 01:54:19.378951 Write Rank0 MR22 =0x38
712 01:54:19.382121 Write Rank0 MR14 =0x5d
713 01:54:19.384855 Write Rank0 MR3 =0x30
714 01:54:19.385245 Write Rank0 MR13 =0x58
715 01:54:19.388730 Write Rank0 MR12 =0x5d
716 01:54:19.389123 Write Rank0 MR1 =0x56
717 01:54:19.391900 Write Rank0 MR2 =0x2d
718 01:54:19.395243 Write Rank0 MR11 =0x23
719 01:54:19.395716 Write Rank0 MR22 =0x34
720 01:54:19.398254 Write Rank0 MR14 =0x10
721 01:54:19.401471 Write Rank0 MR3 =0x30
722 01:54:19.401995 Write Rank0 MR13 =0xd8
723 01:54:19.405410 [ModeRegInit_LP4] CH1 RK1
724 01:54:19.405956 Write Rank1 MR13 =0x18
725 01:54:19.408135 Write Rank1 MR12 =0x5d
726 01:54:19.411650 Write Rank1 MR1 =0x56
727 01:54:19.412120 Write Rank1 MR2 =0x1a
728 01:54:19.414794 Write Rank1 MR11 =0x0
729 01:54:19.417984 Write Rank1 MR22 =0x38
730 01:54:19.418375 Write Rank1 MR14 =0x5d
731 01:54:19.421361 Write Rank1 MR3 =0x30
732 01:54:19.421853 Write Rank1 MR13 =0x58
733 01:54:19.424653 Write Rank1 MR12 =0x5d
734 01:54:19.428239 Write Rank1 MR1 =0x56
735 01:54:19.428707 Write Rank1 MR2 =0x2d
736 01:54:19.431616 Write Rank1 MR11 =0x23
737 01:54:19.432082 Write Rank1 MR22 =0x34
738 01:54:19.434380 Write Rank1 MR14 =0x10
739 01:54:19.438119 Write Rank1 MR3 =0x30
740 01:54:19.438582 Write Rank1 MR13 =0xd8
741 01:54:19.440903 match AC timing 3
742 01:54:19.451538 [DdrUpdateACTimingReg] Freq = 1600, tRFCab = 141, tRFCab_05T = 0, TXREFCNT = 159, tRFCpb = 65, tRFCpb_05T = 0
743 01:54:19.452039 DramC Write-DBI off
744 01:54:19.454701 DramC Read-DBI off
745 01:54:19.455169 Write Rank0 MR13 =0x59
746 01:54:19.458041 ==
747 01:54:19.461287 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
748 01:54:19.464337 fsp= 1, odt_onoff= 1, Byte mode= 0
749 01:54:19.464732 ==
750 01:54:19.467772 === u2Vref_new: 0x56 --> 0x2d
751 01:54:19.471566 === u2Vref_new: 0x58 --> 0x38
752 01:54:19.473959 === u2Vref_new: 0x5a --> 0x39
753 01:54:19.477264 === u2Vref_new: 0x5c --> 0x3c
754 01:54:19.480851 === u2Vref_new: 0x5e --> 0x3d
755 01:54:19.484076 === u2Vref_new: 0x60 --> 0xa0
756 01:54:19.487761 [CA 0] Center 34 (6~63) winsize 58
757 01:54:19.490370 [CA 1] Center 35 (8~63) winsize 56
758 01:54:19.493793 [CA 2] Center 30 (1~59) winsize 59
759 01:54:19.494189 [CA 3] Center 25 (-3~53) winsize 57
760 01:54:19.497180 [CA 4] Center 25 (-2~53) winsize 56
761 01:54:19.500562 [CA 5] Center 31 (2~60) winsize 59
762 01:54:19.501077
763 01:54:19.507065 [CATrainingPosCal] consider 1 rank data
764 01:54:19.507568 u2DelayCellTimex100 = 753/100 ps
765 01:54:19.513610 CA0 delay=34 (6~63),Diff = 9 PI (11 cell)
766 01:54:19.516727 CA1 delay=35 (8~63),Diff = 10 PI (12 cell)
767 01:54:19.520222 CA2 delay=30 (1~59),Diff = 5 PI (6 cell)
768 01:54:19.523389 CA3 delay=25 (-3~53),Diff = 0 PI (0 cell)
769 01:54:19.526553 CA4 delay=25 (-2~53),Diff = 0 PI (0 cell)
770 01:54:19.530073 CA5 delay=31 (2~60),Diff = 6 PI (7 cell)
771 01:54:19.530530
772 01:54:19.533440 CA PerBit enable=1, Macro0, CA PI delay=25
773 01:54:19.536715 === u2Vref_new: 0x5e --> 0x3d
774 01:54:19.537149
775 01:54:19.540327 Vref(ca) range 1: 30
776 01:54:19.540875
777 01:54:19.541218 CS Dly= 8 (39-0-32)
778 01:54:19.543363 Write Rank0 MR13 =0xd8
779 01:54:19.547003 Write Rank0 MR13 =0xd8
780 01:54:19.547523 Write Rank0 MR12 =0x5e
781 01:54:19.550109 Write Rank1 MR13 =0x59
782 01:54:19.550538 ==
783 01:54:19.556637 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
784 01:54:19.557143 fsp= 1, odt_onoff= 1, Byte mode= 0
785 01:54:19.559429 ==
786 01:54:19.559863 === u2Vref_new: 0x56 --> 0x2d
787 01:54:19.562767 === u2Vref_new: 0x58 --> 0x38
788 01:54:19.566103 === u2Vref_new: 0x5a --> 0x39
789 01:54:19.569353 === u2Vref_new: 0x5c --> 0x3c
790 01:54:19.572969 === u2Vref_new: 0x5e --> 0x3d
791 01:54:19.576265 === u2Vref_new: 0x60 --> 0xa0
792 01:54:19.579495 [CA 0] Center 35 (8~63) winsize 56
793 01:54:19.582676 [CA 1] Center 35 (7~63) winsize 57
794 01:54:19.585959 [CA 2] Center 31 (2~60) winsize 59
795 01:54:19.589382 [CA 3] Center 26 (-2~54) winsize 57
796 01:54:19.592537 [CA 4] Center 26 (-2~54) winsize 57
797 01:54:19.595833 [CA 5] Center 32 (3~61) winsize 59
798 01:54:19.596410
799 01:54:19.599187 [CATrainingPosCal] consider 2 rank data
800 01:54:19.602520 u2DelayCellTimex100 = 753/100 ps
801 01:54:19.605835 CA0 delay=35 (8~63),Diff = 10 PI (12 cell)
802 01:54:19.608810 CA1 delay=35 (8~63),Diff = 10 PI (12 cell)
803 01:54:19.612442 CA2 delay=30 (2~59),Diff = 5 PI (6 cell)
804 01:54:19.615596 CA3 delay=25 (-2~53),Diff = 0 PI (0 cell)
805 01:54:19.622135 CA4 delay=25 (-2~53),Diff = 0 PI (0 cell)
806 01:54:19.625498 CA5 delay=31 (3~60),Diff = 6 PI (7 cell)
807 01:54:19.626128
808 01:54:19.628851 CA PerBit enable=1, Macro0, CA PI delay=25
809 01:54:19.631902 === u2Vref_new: 0x5e --> 0x3d
810 01:54:19.632450
811 01:54:19.632888 Vref(ca) range 1: 30
812 01:54:19.633308
813 01:54:19.635292 CS Dly= 7 (38-0-32)
814 01:54:19.638733 Write Rank1 MR13 =0xd8
815 01:54:19.639120 Write Rank1 MR13 =0xd8
816 01:54:19.641966 Write Rank1 MR12 =0x5e
817 01:54:19.645156 [RankSwap] Rank num 2, (Multi 1), Rank 0
818 01:54:19.648330 Write Rank0 MR2 =0xad
819 01:54:19.648715 [Write Leveling]
820 01:54:19.652095 delay byte0 byte1 byte2 byte3
821 01:54:19.652478
822 01:54:19.652776 10 0 0
823 01:54:19.655287 11 0 0
824 01:54:19.655762 12 0 0
825 01:54:19.658649 13 0 0
826 01:54:19.659124 14 0 0
827 01:54:19.659438 15 0 0
828 01:54:19.662046 16 0 0
829 01:54:19.662519 17 0 0
830 01:54:19.665085 18 0 0
831 01:54:19.665477 19 0 0
832 01:54:19.668313 20 0 0
833 01:54:19.668737 21 0 0
834 01:54:19.669242 22 0 0
835 01:54:19.672068 23 0 ff
836 01:54:19.672540 24 0 ff
837 01:54:19.674861 25 0 ff
838 01:54:19.675256 26 0 ff
839 01:54:19.678707 27 0 ff
840 01:54:19.679108 28 0 ff
841 01:54:19.681196 29 0 ff
842 01:54:19.681626 30 0 ff
843 01:54:19.682053 31 0 ff
844 01:54:19.684525 32 ff ff
845 01:54:19.685113 33 ff ff
846 01:54:19.687719 34 ff ff
847 01:54:19.688115 35 ff ff
848 01:54:19.691039 36 ff ff
849 01:54:19.691439 37 ff ff
850 01:54:19.695187 38 ff ff
851 01:54:19.698218 pass bytecount = 0xff (0xff: all bytes pass)
852 01:54:19.698610
853 01:54:19.698915 DQS0 dly: 32
854 01:54:19.701139 DQS1 dly: 23
855 01:54:19.701637 Write Rank0 MR2 =0x2d
856 01:54:19.705159 [RankSwap] Rank num 2, (Multi 1), Rank 0
857 01:54:19.708266 Write Rank0 MR1 =0xd6
858 01:54:19.708733 [Gating]
859 01:54:19.709035 ==
860 01:54:19.714313 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
861 01:54:19.718082 fsp= 1, odt_onoff= 1, Byte mode= 0
862 01:54:19.718669 ==
863 01:54:19.721251 3 1 0 |3534 2c2b |(11 11)(11 11) |(0 0)(1 1)| 0
864 01:54:19.727695 3 1 4 |3534 2c2b |(11 11)(11 11) |(0 0)(1 1)| 0
865 01:54:19.730980 3 1 8 |3534 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
866 01:54:19.734302 3 1 12 |3534 2c2b |(11 11)(11 11) |(1 1)(1 1)| 0
867 01:54:19.741078 3 1 16 |3534 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
868 01:54:19.744371 3 1 20 |3534 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
869 01:54:19.747647 3 1 24 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
870 01:54:19.753696 3 1 28 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
871 01:54:19.757246 3 2 0 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
872 01:54:19.760116 3 2 4 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
873 01:54:19.766768 3 2 8 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
874 01:54:19.770468 3 2 12 |3534 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
875 01:54:19.773418 3 2 16 |707 1818 |(11 11)(11 11) |(1 1)(0 0)| 0
876 01:54:19.780261 3 2 20 |3d3d 1818 |(11 11)(11 11) |(1 1)(0 0)| 0
877 01:54:19.783204 3 2 24 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
878 01:54:19.786416 3 2 28 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
879 01:54:19.789752 3 3 0 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
880 01:54:19.796991 3 3 4 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
881 01:54:19.800588 3 3 8 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
882 01:54:19.802960 3 3 12 |3d3d 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
883 01:54:19.809539 3 3 16 |202 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
884 01:54:19.813342 3 3 20 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
885 01:54:19.816065 [Byte 1] Lead/lag falling Transition (3, 3, 20)
886 01:54:19.822542 3 3 24 |3534 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
887 01:54:19.825919 [Byte 0] Lead/lag Transition tap number (1)
888 01:54:19.829223 3 3 28 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
889 01:54:19.835945 3 4 0 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
890 01:54:19.839528 3 4 4 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
891 01:54:19.842579 3 4 8 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
892 01:54:19.846138 3 4 12 |201 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
893 01:54:19.852445 3 4 16 |e0e 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
894 01:54:19.856083 3 4 20 |3d3d 706 |(11 11)(11 11) |(1 1)(1 1)| 0
895 01:54:19.859140 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
896 01:54:19.865667 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
897 01:54:19.868622 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
898 01:54:19.872276 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
899 01:54:19.878797 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
900 01:54:19.881953 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
901 01:54:19.884965 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
902 01:54:19.891661 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
903 01:54:19.894855 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
904 01:54:19.898242 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
905 01:54:19.904893 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
906 01:54:19.908126 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
907 01:54:19.911247 [Byte 0] Lead/lag falling Transition (3, 6, 4)
908 01:54:19.918154 [Byte 1] Lead/lag falling Transition (3, 6, 4)
909 01:54:19.921612 3 6 8 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 0)| 0
910 01:54:19.924371 [Byte 0] Lead/lag Transition tap number (2)
911 01:54:19.928178 3 6 12 |3e3d 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
912 01:54:19.935115 [Byte 1] Lead/lag Transition tap number (3)
913 01:54:19.937612 3 6 16 |3a3a 3e3d |(1 1)(11 11) |(0 0)(0 0)| 0
914 01:54:19.940871 3 6 20 |4646 606 |(0 0)(11 11) |(0 0)(0 0)| 0
915 01:54:19.944161 [Byte 0]First pass (3, 6, 20)
916 01:54:19.947713 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
917 01:54:19.950664 [Byte 1]First pass (3, 6, 24)
918 01:54:19.953926 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
919 01:54:19.957284 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
920 01:54:19.964521 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
921 01:54:19.967275 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
922 01:54:19.971020 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
923 01:54:19.973698 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
924 01:54:19.977045 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
925 01:54:19.983996 3 7 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
926 01:54:19.986761 All bytes gating window > 1UI, Early break!
927 01:54:19.987198
928 01:54:19.990536 best DQS0 dly(2T, 0.5T, PI) = (3, 6, 8)
929 01:54:19.991029
930 01:54:19.993924 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 10)
931 01:54:19.994358
932 01:54:19.994693
933 01:54:19.995005
934 01:54:19.997285 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 8)
935 01:54:19.997768
936 01:54:20.003873 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 10)
937 01:54:20.004467
938 01:54:20.004779
939 01:54:20.005063 Write Rank0 MR1 =0x56
940 01:54:20.005330
941 01:54:20.007042 best RODT dly(2T, 0.5T) = (2, 3)
942 01:54:20.007515
943 01:54:20.010067 best RODT dly(2T, 0.5T) = (2, 3)
944 01:54:20.010461 ==
945 01:54:20.017081 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
946 01:54:20.020197 fsp= 1, odt_onoff= 1, Byte mode= 0
947 01:54:20.020667 ==
948 01:54:20.023288 Start DQ dly to find pass range UseTestEngine =0
949 01:54:20.026950 x-axis: bit #, y-axis: DQ dly (-127~63)
950 01:54:20.030208 RX Vref Scan = 0
951 01:54:20.033604 -26, [0] xxxxxxxx xxxxxxxx [MSB]
952 01:54:20.036457 -25, [0] xxxxxxxx xxxxxxxx [MSB]
953 01:54:20.036874 -24, [0] xxxxxxxx xxxxxxxx [MSB]
954 01:54:20.039916 -23, [0] xxxxxxxx xxxxxxxx [MSB]
955 01:54:20.043820 -22, [0] xxxxxxxx xxxxxxxx [MSB]
956 01:54:20.046406 -21, [0] xxxxxxxx xxxxxxxx [MSB]
957 01:54:20.049998 -20, [0] xxxxxxxx xxxxxxxx [MSB]
958 01:54:20.052960 -19, [0] xxxxxxxx xxxxxxxx [MSB]
959 01:54:20.056216 -18, [0] xxxxxxxx xxxxxxxx [MSB]
960 01:54:20.059989 -17, [0] xxxxxxxx xxxxxxxx [MSB]
961 01:54:20.062912 -16, [0] xxxxxxxx xxxxxxxx [MSB]
962 01:54:20.063331 -15, [0] xxxxxxxx xxxxxxxx [MSB]
963 01:54:20.066382 -14, [0] xxxxxxxx xxxxxxxx [MSB]
964 01:54:20.069496 -13, [0] xxxxxxxx xxxxxxxx [MSB]
965 01:54:20.072884 -12, [0] xxxxxxxx xxxxxxxx [MSB]
966 01:54:20.075883 -11, [0] xxxxxxxx xxxxxxxx [MSB]
967 01:54:20.079014 -10, [0] xxxxxxxx xxxxxxxx [MSB]
968 01:54:20.082382 -9, [0] xxxxxxxx xxxxxxxx [MSB]
969 01:54:20.086051 -8, [0] xxxxxxxx xxxxxxxx [MSB]
970 01:54:20.089536 -7, [0] xxxxxxxx xxxxxxxx [MSB]
971 01:54:20.090068 -6, [0] xxxxxxxx xxxxxxxx [MSB]
972 01:54:20.092579 -5, [0] xxxxxxxx xxxxxxxx [MSB]
973 01:54:20.095509 -4, [0] xxxxxxxx xxxxxxxx [MSB]
974 01:54:20.098871 -3, [0] xxxoxxxx xxxxxxxx [MSB]
975 01:54:20.101954 -2, [0] xxxoxxxx oxxxxxxx [MSB]
976 01:54:20.105503 -1, [0] xxxoxxxx oxxoxxxx [MSB]
977 01:54:20.108642 0, [0] xxxoxxxx oxxoxxxx [MSB]
978 01:54:20.109051 1, [0] xxxoxoox ooxooxxx [MSB]
979 01:54:20.111820 2, [0] xxxoxoox ooxoooxx [MSB]
980 01:54:20.115306 3, [0] xxxoxooo ooxoooox [MSB]
981 01:54:20.118308 4, [0] xoxoxooo ooxoooox [MSB]
982 01:54:20.121660 5, [0] xoxooooo ooxooooo [MSB]
983 01:54:20.124741 6, [0] xooooooo ooxooooo [MSB]
984 01:54:20.125176 7, [0] oooooooo ooxooooo [MSB]
985 01:54:20.128818 32, [0] oooxoooo oooooooo [MSB]
986 01:54:20.132181 33, [0] oooxoxoo oooooooo [MSB]
987 01:54:20.135710 34, [0] oooxoxoo xooooooo [MSB]
988 01:54:20.138939 35, [0] oooxoxoo xooooooo [MSB]
989 01:54:20.141693 36, [0] oooxoxoo xxoxxooo [MSB]
990 01:54:20.144863 37, [0] oooxoxxo xxoxxxxo [MSB]
991 01:54:20.148371 38, [0] oooxoxxx xxoxxxxo [MSB]
992 01:54:20.148891 39, [0] xxoxoxxx xxoxxxxo [MSB]
993 01:54:20.151251 40, [0] xxoxoxxx xxoxxxxo [MSB]
994 01:54:20.154328 41, [0] xxxxxxxx xxoxxxxx [MSB]
995 01:54:20.158036 42, [0] xxxxxxxx xxoxxxxx [MSB]
996 01:54:20.161249 43, [0] xxxxxxxx xxxxxxxx [MSB]
997 01:54:20.164929 iDelay=43, Bit 0, Center 22 (7 ~ 38) 32
998 01:54:20.168116 iDelay=43, Bit 1, Center 21 (4 ~ 38) 35
999 01:54:20.171046 iDelay=43, Bit 2, Center 23 (6 ~ 40) 35
1000 01:54:20.174301 iDelay=43, Bit 3, Center 14 (-3 ~ 31) 35
1001 01:54:20.177509 iDelay=43, Bit 4, Center 22 (5 ~ 40) 36
1002 01:54:20.181151 iDelay=43, Bit 5, Center 16 (1 ~ 32) 32
1003 01:54:20.184452 iDelay=43, Bit 6, Center 18 (1 ~ 36) 36
1004 01:54:20.187446 iDelay=43, Bit 7, Center 20 (3 ~ 37) 35
1005 01:54:20.194445 iDelay=43, Bit 8, Center 15 (-2 ~ 33) 36
1006 01:54:20.198055 iDelay=43, Bit 9, Center 18 (1 ~ 35) 35
1007 01:54:20.201380 iDelay=43, Bit 10, Center 25 (8 ~ 42) 35
1008 01:54:20.204630 iDelay=43, Bit 11, Center 17 (-1 ~ 35) 37
1009 01:54:20.207949 iDelay=43, Bit 12, Center 18 (1 ~ 35) 35
1010 01:54:20.210858 iDelay=43, Bit 13, Center 19 (2 ~ 36) 35
1011 01:54:20.214450 iDelay=43, Bit 14, Center 19 (3 ~ 36) 34
1012 01:54:20.217623 iDelay=43, Bit 15, Center 22 (5 ~ 40) 36
1013 01:54:20.218148 ==
1014 01:54:20.223761 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1015 01:54:20.227253 fsp= 1, odt_onoff= 1, Byte mode= 0
1016 01:54:20.227702 ==
1017 01:54:20.228141 DQS Delay:
1018 01:54:20.230189 DQS0 = 0, DQS1 = 0
1019 01:54:20.230636 DQM Delay:
1020 01:54:20.234609 DQM0 = 19, DQM1 = 19
1021 01:54:20.235129 DQ Delay:
1022 01:54:20.237481 DQ0 =22, DQ1 =21, DQ2 =23, DQ3 =14
1023 01:54:20.240578 DQ4 =22, DQ5 =16, DQ6 =18, DQ7 =20
1024 01:54:20.243304 DQ8 =15, DQ9 =18, DQ10 =25, DQ11 =17
1025 01:54:20.246723 DQ12 =18, DQ13 =19, DQ14 =19, DQ15 =22
1026 01:54:20.247183
1027 01:54:20.247616
1028 01:54:20.250981 DramC Write-DBI off
1029 01:54:20.251499 ==
1030 01:54:20.253402 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1031 01:54:20.256798 fsp= 1, odt_onoff= 1, Byte mode= 0
1032 01:54:20.257317 ==
1033 01:54:20.260164 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
1034 01:54:20.260718
1035 01:54:20.263649 Begin, DQ Scan Range 919~1175
1036 01:54:20.264097
1037 01:54:20.264538
1038 01:54:20.266549 TX Vref Scan disable
1039 01:54:20.269793 919 |3 4 23|[0] xxxxxxxx xxxxxxxx [MSB]
1040 01:54:20.273139 920 |3 4 24|[0] xxxxxxxx xxxxxxxx [MSB]
1041 01:54:20.276598 921 |3 4 25|[0] xxxxxxxx xxxxxxxx [MSB]
1042 01:54:20.280087 922 |3 4 26|[0] xxxxxxxx xxxxxxxx [MSB]
1043 01:54:20.283601 923 |3 4 27|[0] xxxxxxxx xxxxxxxx [MSB]
1044 01:54:20.286108 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB]
1045 01:54:20.293325 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
1046 01:54:20.296961 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
1047 01:54:20.299795 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
1048 01:54:20.303549 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
1049 01:54:20.306032 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
1050 01:54:20.309238 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
1051 01:54:20.312519 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
1052 01:54:20.315792 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
1053 01:54:20.318898 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
1054 01:54:20.322125 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
1055 01:54:20.325474 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
1056 01:54:20.329154 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
1057 01:54:20.332356 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
1058 01:54:20.339429 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
1059 01:54:20.342337 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
1060 01:54:20.345727 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
1061 01:54:20.349249 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
1062 01:54:20.352271 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
1063 01:54:20.355587 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
1064 01:54:20.358804 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
1065 01:54:20.362107 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
1066 01:54:20.365433 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
1067 01:54:20.368237 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
1068 01:54:20.371879 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
1069 01:54:20.374951 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
1070 01:54:20.379104 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
1071 01:54:20.381942 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
1072 01:54:20.388197 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
1073 01:54:20.391995 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
1074 01:54:20.394878 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
1075 01:54:20.399254 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
1076 01:54:20.402663 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1077 01:54:20.404858 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1078 01:54:20.408336 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1079 01:54:20.411768 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1080 01:54:20.414473 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1081 01:54:20.417967 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1082 01:54:20.421422 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
1083 01:54:20.424697 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
1084 01:54:20.428148 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
1085 01:54:20.431517 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
1086 01:54:20.434847 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
1087 01:54:20.437698 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
1088 01:54:20.441374 968 |3 6 8|[0] xxxxxxxx oxxxxxxx [MSB]
1089 01:54:20.444633 969 |3 6 9|[0] xxxxxxxx oxxoxxxx [MSB]
1090 01:54:20.451123 970 |3 6 10|[0] xxxxxxxx ooxoxxxx [MSB]
1091 01:54:20.454114 971 |3 6 11|[0] xxxxxxxx ooxooxox [MSB]
1092 01:54:20.457401 972 |3 6 12|[0] xxxxxxxx ooxoooox [MSB]
1093 01:54:20.461021 973 |3 6 13|[0] xxxxxxxx ooxoooox [MSB]
1094 01:54:20.464016 974 |3 6 14|[0] xxxxxxxx ooxooooo [MSB]
1095 01:54:20.467616 975 |3 6 15|[0] xxxxxxxx oooooooo [MSB]
1096 01:54:20.470646 976 |3 6 16|[0] xxxxxxxx oooooooo [MSB]
1097 01:54:20.473952 977 |3 6 17|[0] xxxxxxxx oooooooo [MSB]
1098 01:54:20.477393 978 |3 6 18|[0] xxxxxxxx oooooooo [MSB]
1099 01:54:20.480768 979 |3 6 19|[0] xxxoxoox oooooooo [MSB]
1100 01:54:20.484048 980 |3 6 20|[0] xoxooooo oooooooo [MSB]
1101 01:54:20.487780 981 |3 6 21|[0] xooooooo oooooooo [MSB]
1102 01:54:20.494070 987 |3 6 27|[0] oooooooo xooxoooo [MSB]
1103 01:54:20.497392 988 |3 6 28|[0] oooooooo xooxoooo [MSB]
1104 01:54:20.501134 989 |3 6 29|[0] oooooooo xxxxxxxx [MSB]
1105 01:54:20.504346 990 |3 6 30|[0] oooooooo xxxxxxxx [MSB]
1106 01:54:20.507724 991 |3 6 31|[0] oooooooo xxxxxxxx [MSB]
1107 01:54:20.510746 992 |3 6 32|[0] oooooooo xxxxxxxx [MSB]
1108 01:54:20.514132 993 |3 6 33|[0] oooooooo xxxxxxxx [MSB]
1109 01:54:20.517127 994 |3 6 34|[0] oooooooo xxxxxxxx [MSB]
1110 01:54:20.520471 995 |3 6 35|[0] oooxoooo xxxxxxxx [MSB]
1111 01:54:20.524120 996 |3 6 36|[0] oooxoooo xxxxxxxx [MSB]
1112 01:54:20.526981 997 |3 6 37|[0] oooxoxoo xxxxxxxx [MSB]
1113 01:54:20.530270 998 |3 6 38|[0] oooxoxoo xxxxxxxx [MSB]
1114 01:54:20.533722 999 |3 6 39|[0] xxxxxxxx xxxxxxxx [MSB]
1115 01:54:20.539593 Byte0, DQ PI dly=988, DQM PI dly= 988
1116 01:54:20.542987 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 28)
1117 01:54:20.543443
1118 01:54:20.546471 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 28)
1119 01:54:20.546909
1120 01:54:20.550134 Byte1, DQ PI dly=979, DQM PI dly= 979
1121 01:54:20.556281 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 19)
1122 01:54:20.556721
1123 01:54:20.560257 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 19)
1124 01:54:20.560765
1125 01:54:20.561107 ==
1126 01:54:20.566504 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1127 01:54:20.569849 fsp= 1, odt_onoff= 1, Byte mode= 0
1128 01:54:20.570357 ==
1129 01:54:20.572862 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
1130 01:54:20.573296
1131 01:54:20.576214 Begin, DQ Scan Range 955~1019
1132 01:54:20.576643 Write Rank0 MR14 =0x0
1133 01:54:20.586128
1134 01:54:20.586636 CH=0, VrefRange= 0, VrefLevel = 0
1135 01:54:20.592380 TX Bit0 (984~998) 15 991, Bit8 (973~982) 10 977,
1136 01:54:20.595961 TX Bit1 (983~994) 12 988, Bit9 (973~983) 11 978,
1137 01:54:20.602526 TX Bit2 (983~996) 14 989, Bit10 (977~989) 13 983,
1138 01:54:20.606057 TX Bit3 (977~991) 15 984, Bit11 (973~982) 10 977,
1139 01:54:20.608980 TX Bit4 (983~992) 10 987, Bit12 (974~984) 11 979,
1140 01:54:20.615862 TX Bit5 (980~991) 12 985, Bit13 (974~983) 10 978,
1141 01:54:20.619154 TX Bit6 (981~992) 12 986, Bit14 (974~987) 14 980,
1142 01:54:20.625630 TX Bit7 (983~992) 10 987, Bit15 (975~989) 15 982,
1143 01:54:20.626155
1144 01:54:20.626548 Write Rank0 MR14 =0x2
1145 01:54:20.634838
1146 01:54:20.635345 CH=0, VrefRange= 0, VrefLevel = 2
1147 01:54:20.641328 TX Bit0 (984~998) 15 991, Bit8 (972~982) 11 977,
1148 01:54:20.645026 TX Bit1 (982~996) 15 989, Bit9 (973~984) 12 978,
1149 01:54:20.651266 TX Bit2 (983~997) 15 990, Bit10 (976~989) 14 982,
1150 01:54:20.654583 TX Bit3 (977~991) 15 984, Bit11 (972~982) 11 977,
1151 01:54:20.657950 TX Bit4 (983~993) 11 988, Bit12 (973~984) 12 978,
1152 01:54:20.664469 TX Bit5 (980~991) 12 985, Bit13 (974~984) 11 979,
1153 01:54:20.667811 TX Bit6 (981~994) 14 987, Bit14 (974~988) 15 981,
1154 01:54:20.674355 TX Bit7 (982~994) 13 988, Bit15 (975~990) 16 982,
1155 01:54:20.674740
1156 01:54:20.675034 Write Rank0 MR14 =0x4
1157 01:54:20.683200
1158 01:54:20.683593 CH=0, VrefRange= 0, VrefLevel = 4
1159 01:54:20.689703 TX Bit0 (984~998) 15 991, Bit8 (972~983) 12 977,
1160 01:54:20.693337 TX Bit1 (982~997) 16 989, Bit9 (973~984) 12 978,
1161 01:54:20.700013 TX Bit2 (983~998) 16 990, Bit10 (976~990) 15 983,
1162 01:54:20.703936 TX Bit3 (976~991) 16 983, Bit11 (972~983) 12 977,
1163 01:54:20.706339 TX Bit4 (982~994) 13 988, Bit12 (973~985) 13 979,
1164 01:54:20.713188 TX Bit5 (979~992) 14 985, Bit13 (973~984) 12 978,
1165 01:54:20.764207 TX Bit6 (980~994) 15 987, Bit14 (973~988) 16 980,
1166 01:54:20.764988 TX Bit7 (982~994) 13 988, Bit15 (975~991) 17 983,
1167 01:54:20.765322
1168 01:54:20.765662 Write Rank0 MR14 =0x6
1169 01:54:20.765947
1170 01:54:20.766214 CH=0, VrefRange= 0, VrefLevel = 6
1171 01:54:20.766552 TX Bit0 (983~998) 16 990, Bit8 (970~983) 14 976,
1172 01:54:20.766825 TX Bit1 (982~998) 17 990, Bit9 (973~985) 13 979,
1173 01:54:20.767084 TX Bit2 (982~998) 17 990, Bit10 (975~990) 16 982,
1174 01:54:20.767343 TX Bit3 (976~992) 17 984, Bit11 (972~983) 12 977,
1175 01:54:20.767595 TX Bit4 (982~995) 14 988, Bit12 (973~986) 14 979,
1176 01:54:20.767846 TX Bit5 (979~993) 15 986, Bit13 (973~985) 13 979,
1177 01:54:20.768102 TX Bit6 (979~995) 17 987, Bit14 (973~989) 17 981,
1178 01:54:20.773332 TX Bit7 (982~995) 14 988, Bit15 (974~991) 18 982,
1179 01:54:20.773792
1180 01:54:20.776616 Write Rank0 MR14 =0x8
1181 01:54:20.781285
1182 01:54:20.781750 CH=0, VrefRange= 0, VrefLevel = 8
1183 01:54:20.787550 TX Bit0 (983~999) 17 991, Bit8 (970~983) 14 976,
1184 01:54:20.790796 TX Bit1 (981~998) 18 989, Bit9 (972~986) 15 979,
1185 01:54:20.797692 TX Bit2 (983~999) 17 991, Bit10 (975~991) 17 983,
1186 01:54:20.801080 TX Bit3 (976~992) 17 984, Bit11 (971~984) 14 977,
1187 01:54:20.804250 TX Bit4 (981~996) 16 988, Bit12 (972~986) 15 979,
1188 01:54:20.810578 TX Bit5 (978~993) 16 985, Bit13 (973~985) 13 979,
1189 01:54:20.813916 TX Bit6 (979~996) 18 987, Bit14 (972~989) 18 980,
1190 01:54:20.820749 TX Bit7 (981~997) 17 989, Bit15 (974~991) 18 982,
1191 01:54:20.821247
1192 01:54:20.821632 Write Rank0 MR14 =0xa
1193 01:54:20.830299
1194 01:54:20.833295 CH=0, VrefRange= 0, VrefLevel = 10
1195 01:54:20.836742 TX Bit0 (983~999) 17 991, Bit8 (969~984) 16 976,
1196 01:54:20.840596 TX Bit1 (981~999) 19 990, Bit9 (972~987) 16 979,
1197 01:54:20.847190 TX Bit2 (982~999) 18 990, Bit10 (975~991) 17 983,
1198 01:54:20.849803 TX Bit3 (976~993) 18 984, Bit11 (971~984) 14 977,
1199 01:54:20.853336 TX Bit4 (981~997) 17 989, Bit12 (972~988) 17 980,
1200 01:54:20.859741 TX Bit5 (978~994) 17 986, Bit13 (972~987) 16 979,
1201 01:54:20.863303 TX Bit6 (978~997) 20 987, Bit14 (972~989) 18 980,
1202 01:54:20.869681 TX Bit7 (981~997) 17 989, Bit15 (974~992) 19 983,
1203 01:54:20.870196
1204 01:54:20.870531 Write Rank0 MR14 =0xc
1205 01:54:20.878771
1206 01:54:20.882853 CH=0, VrefRange= 0, VrefLevel = 12
1207 01:54:20.885463 TX Bit0 (982~1000) 19 991, Bit8 (969~985) 17 977,
1208 01:54:20.888935 TX Bit1 (980~999) 20 989, Bit9 (972~988) 17 980,
1209 01:54:20.895289 TX Bit2 (982~999) 18 990, Bit10 (975~992) 18 983,
1210 01:54:20.898601 TX Bit3 (976~993) 18 984, Bit11 (970~985) 16 977,
1211 01:54:20.901869 TX Bit4 (980~998) 19 989, Bit12 (971~989) 19 980,
1212 01:54:20.908942 TX Bit5 (977~995) 19 986, Bit13 (972~988) 17 980,
1213 01:54:20.911880 TX Bit6 (978~997) 20 987, Bit14 (972~990) 19 981,
1214 01:54:20.918740 TX Bit7 (980~998) 19 989, Bit15 (974~992) 19 983,
1215 01:54:20.919257
1216 01:54:20.919640 Write Rank0 MR14 =0xe
1217 01:54:20.928155
1218 01:54:20.931550 CH=0, VrefRange= 0, VrefLevel = 14
1219 01:54:20.934907 TX Bit0 (982~1000) 19 991, Bit8 (968~986) 19 977,
1220 01:54:20.938265 TX Bit1 (980~999) 20 989, Bit9 (971~989) 19 980,
1221 01:54:20.945241 TX Bit2 (982~1000) 19 991, Bit10 (975~993) 19 984,
1222 01:54:20.947809 TX Bit3 (976~994) 19 985, Bit11 (970~986) 17 978,
1223 01:54:20.951573 TX Bit4 (980~998) 19 989, Bit12 (971~989) 19 980,
1224 01:54:20.957982 TX Bit5 (977~995) 19 986, Bit13 (972~988) 17 980,
1225 01:54:20.961322 TX Bit6 (978~998) 21 988, Bit14 (971~990) 20 980,
1226 01:54:20.967574 TX Bit7 (980~998) 19 989, Bit15 (974~993) 20 983,
1227 01:54:20.968085
1228 01:54:20.968420 Write Rank0 MR14 =0x10
1229 01:54:20.977730
1230 01:54:20.980966 CH=0, VrefRange= 0, VrefLevel = 16
1231 01:54:20.984634 TX Bit0 (982~1001) 20 991, Bit8 (968~986) 19 977,
1232 01:54:20.987934 TX Bit1 (981~1000) 20 990, Bit9 (970~989) 20 979,
1233 01:54:20.994769 TX Bit2 (981~1000) 20 990, Bit10 (974~994) 21 984,
1234 01:54:20.998153 TX Bit3 (975~994) 20 984, Bit11 (969~987) 19 978,
1235 01:54:21.001034 TX Bit4 (979~998) 20 988, Bit12 (970~989) 20 979,
1236 01:54:21.007790 TX Bit5 (977~997) 21 987, Bit13 (971~988) 18 979,
1237 01:54:21.010387 TX Bit6 (978~998) 21 988, Bit14 (971~991) 21 981,
1238 01:54:21.017401 TX Bit7 (979~999) 21 989, Bit15 (974~993) 20 983,
1239 01:54:21.018163
1240 01:54:21.020735 wait MRW command Rank0 MR14 =0x12 fired (1)
1241 01:54:21.021167 Write Rank0 MR14 =0x12
1242 01:54:21.031298
1243 01:54:21.034751 CH=0, VrefRange= 0, VrefLevel = 18
1244 01:54:21.038246 TX Bit0 (982~1001) 20 991, Bit8 (968~987) 20 977,
1245 01:54:21.041503 TX Bit1 (979~1000) 22 989, Bit9 (970~989) 20 979,
1246 01:54:21.048149 TX Bit2 (981~1001) 21 991, Bit10 (974~994) 21 984,
1247 01:54:21.051534 TX Bit3 (975~995) 21 985, Bit11 (969~988) 20 978,
1248 01:54:21.054303 TX Bit4 (979~999) 21 989, Bit12 (971~990) 20 980,
1249 01:54:21.061227 TX Bit5 (977~997) 21 987, Bit13 (971~989) 19 980,
1250 01:54:21.064289 TX Bit6 (977~998) 22 987, Bit14 (971~991) 21 981,
1251 01:54:21.071285 TX Bit7 (979~999) 21 989, Bit15 (973~994) 22 983,
1252 01:54:21.071795
1253 01:54:21.072129 Write Rank0 MR14 =0x14
1254 01:54:21.081187
1255 01:54:21.084628 CH=0, VrefRange= 0, VrefLevel = 20
1256 01:54:21.087561 TX Bit0 (982~1002) 21 992, Bit8 (967~988) 22 977,
1257 01:54:21.090915 TX Bit1 (979~1001) 23 990, Bit9 (969~989) 21 979,
1258 01:54:21.097986 TX Bit2 (980~1001) 22 990, Bit10 (974~996) 23 985,
1259 01:54:21.101316 TX Bit3 (975~996) 22 985, Bit11 (969~989) 21 979,
1260 01:54:21.104711 TX Bit4 (978~999) 22 988, Bit12 (970~990) 21 980,
1261 01:54:21.111134 TX Bit5 (977~998) 22 987, Bit13 (970~990) 21 980,
1262 01:54:21.114127 TX Bit6 (977~999) 23 988, Bit14 (970~991) 22 980,
1263 01:54:21.120596 TX Bit7 (978~999) 22 988, Bit15 (973~995) 23 984,
1264 01:54:21.121112
1265 01:54:21.121453 Write Rank0 MR14 =0x16
1266 01:54:21.130558
1267 01:54:21.133872 CH=0, VrefRange= 0, VrefLevel = 22
1268 01:54:21.137388 TX Bit0 (981~1002) 22 991, Bit8 (967~989) 23 978,
1269 01:54:21.140929 TX Bit1 (979~1001) 23 990, Bit9 (969~990) 22 979,
1270 01:54:21.146990 TX Bit2 (980~1001) 22 990, Bit10 (974~996) 23 985,
1271 01:54:21.150544 TX Bit3 (975~996) 22 985, Bit11 (968~989) 22 978,
1272 01:54:21.157166 TX Bit4 (978~1000) 23 989, Bit12 (969~991) 23 980,
1273 01:54:21.160046 TX Bit5 (977~998) 22 987, Bit13 (970~990) 21 980,
1274 01:54:21.163187 TX Bit6 (977~999) 23 988, Bit14 (970~992) 23 981,
1275 01:54:21.170495 TX Bit7 (978~1000) 23 989, Bit15 (973~996) 24 984,
1276 01:54:21.171007
1277 01:54:21.171345 Write Rank0 MR14 =0x18
1278 01:54:21.180965
1279 01:54:21.184260 CH=0, VrefRange= 0, VrefLevel = 24
1280 01:54:21.187521 TX Bit0 (980~1003) 24 991, Bit8 (967~989) 23 978,
1281 01:54:21.190808 TX Bit1 (978~1001) 24 989, Bit9 (968~990) 23 979,
1282 01:54:21.197434 TX Bit2 (979~1003) 25 991, Bit10 (974~996) 23 985,
1283 01:54:21.200498 TX Bit3 (974~996) 23 985, Bit11 (967~989) 23 978,
1284 01:54:21.204129 TX Bit4 (978~1000) 23 989, Bit12 (969~991) 23 980,
1285 01:54:21.210540 TX Bit5 (976~998) 23 987, Bit13 (969~990) 22 979,
1286 01:54:21.213845 TX Bit6 (977~999) 23 988, Bit14 (969~992) 24 980,
1287 01:54:21.220369 TX Bit7 (978~1000) 23 989, Bit15 (973~996) 24 984,
1288 01:54:21.220863
1289 01:54:21.221195 Write Rank0 MR14 =0x1a
1290 01:54:21.231082
1291 01:54:21.234164 CH=0, VrefRange= 0, VrefLevel = 26
1292 01:54:21.237932 TX Bit0 (980~1003) 24 991, Bit8 (967~989) 23 978,
1293 01:54:21.240946 TX Bit1 (978~1002) 25 990, Bit9 (968~991) 24 979,
1294 01:54:21.247390 TX Bit2 (979~1003) 25 991, Bit10 (973~997) 25 985,
1295 01:54:21.250841 TX Bit3 (974~997) 24 985, Bit11 (967~990) 24 978,
1296 01:54:21.257533 TX Bit4 (978~1000) 23 989, Bit12 (969~991) 23 980,
1297 01:54:21.260685 TX Bit5 (976~999) 24 987, Bit13 (969~991) 23 980,
1298 01:54:21.263872 TX Bit6 (976~1000) 25 988, Bit14 (969~993) 25 981,
1299 01:54:21.270657 TX Bit7 (978~1000) 23 989, Bit15 (972~996) 25 984,
1300 01:54:21.271184
1301 01:54:21.271527 Write Rank0 MR14 =0x1c
1302 01:54:21.281057
1303 01:54:21.284740 CH=0, VrefRange= 0, VrefLevel = 28
1304 01:54:21.288253 TX Bit0 (979~1004) 26 991, Bit8 (966~990) 25 978,
1305 01:54:21.291423 TX Bit1 (978~1002) 25 990, Bit9 (968~991) 24 979,
1306 01:54:21.298029 TX Bit2 (979~1003) 25 991, Bit10 (974~997) 24 985,
1307 01:54:21.301662 TX Bit3 (974~998) 25 986, Bit11 (967~990) 24 978,
1308 01:54:21.307962 TX Bit4 (977~1001) 25 989, Bit12 (968~992) 25 980,
1309 01:54:21.310852 TX Bit5 (976~999) 24 987, Bit13 (969~991) 23 980,
1310 01:54:21.314073 TX Bit6 (976~1000) 25 988, Bit14 (969~993) 25 981,
1311 01:54:21.320451 TX Bit7 (978~1001) 24 989, Bit15 (973~996) 24 984,
1312 01:54:21.320880
1313 01:54:21.321224 Write Rank0 MR14 =0x1e
1314 01:54:21.331779
1315 01:54:21.334896 CH=0, VrefRange= 0, VrefLevel = 30
1316 01:54:21.338464 TX Bit0 (980~1005) 26 992, Bit8 (966~989) 24 977,
1317 01:54:21.341529 TX Bit1 (978~1003) 26 990, Bit9 (967~990) 24 978,
1318 01:54:21.348320 TX Bit2 (980~1004) 25 992, Bit10 (973~997) 25 985,
1319 01:54:21.351453 TX Bit3 (974~997) 24 985, Bit11 (967~990) 24 978,
1320 01:54:21.358337 TX Bit4 (977~1001) 25 989, Bit12 (968~991) 24 979,
1321 01:54:21.361135 TX Bit5 (976~999) 24 987, Bit13 (968~991) 24 979,
1322 01:54:21.364747 TX Bit6 (976~1000) 25 988, Bit14 (969~993) 25 981,
1323 01:54:21.371315 TX Bit7 (978~1001) 24 989, Bit15 (973~996) 24 984,
1324 01:54:21.371696
1325 01:54:21.371937 Write Rank0 MR14 =0x20
1326 01:54:21.382177
1327 01:54:21.385303 CH=0, VrefRange= 0, VrefLevel = 32
1328 01:54:21.388807 TX Bit0 (980~1005) 26 992, Bit8 (966~989) 24 977,
1329 01:54:21.391811 TX Bit1 (978~1003) 26 990, Bit9 (967~990) 24 978,
1330 01:54:21.398288 TX Bit2 (980~1004) 25 992, Bit10 (973~997) 25 985,
1331 01:54:21.401528 TX Bit3 (974~997) 24 985, Bit11 (967~990) 24 978,
1332 01:54:21.408536 TX Bit4 (977~1001) 25 989, Bit12 (968~991) 24 979,
1333 01:54:21.411598 TX Bit5 (976~999) 24 987, Bit13 (968~991) 24 979,
1334 01:54:21.415431 TX Bit6 (976~1000) 25 988, Bit14 (969~993) 25 981,
1335 01:54:21.422018 TX Bit7 (978~1001) 24 989, Bit15 (973~996) 24 984,
1336 01:54:21.422464
1337 01:54:21.422790 Write Rank0 MR14 =0x22
1338 01:54:21.432642
1339 01:54:21.435890 CH=0, VrefRange= 0, VrefLevel = 34
1340 01:54:21.439197 TX Bit0 (980~1005) 26 992, Bit8 (966~989) 24 977,
1341 01:54:21.442448 TX Bit1 (978~1003) 26 990, Bit9 (967~990) 24 978,
1342 01:54:21.449057 TX Bit2 (980~1004) 25 992, Bit10 (973~997) 25 985,
1343 01:54:21.452683 TX Bit3 (974~997) 24 985, Bit11 (967~990) 24 978,
1344 01:54:21.455488 TX Bit4 (977~1001) 25 989, Bit12 (968~991) 24 979,
1345 01:54:21.462223 TX Bit5 (976~999) 24 987, Bit13 (968~991) 24 979,
1346 01:54:21.465429 TX Bit6 (976~1000) 25 988, Bit14 (969~993) 25 981,
1347 01:54:21.472047 TX Bit7 (978~1001) 24 989, Bit15 (973~996) 24 984,
1348 01:54:21.472545
1349 01:54:21.472878 Write Rank0 MR14 =0x24
1350 01:54:21.483186
1351 01:54:21.485914 CH=0, VrefRange= 0, VrefLevel = 36
1352 01:54:21.489372 TX Bit0 (980~1005) 26 992, Bit8 (966~989) 24 977,
1353 01:54:21.492102 TX Bit1 (978~1003) 26 990, Bit9 (967~990) 24 978,
1354 01:54:21.499027 TX Bit2 (980~1004) 25 992, Bit10 (973~997) 25 985,
1355 01:54:21.502158 TX Bit3 (974~997) 24 985, Bit11 (967~990) 24 978,
1356 01:54:21.508947 TX Bit4 (977~1001) 25 989, Bit12 (968~991) 24 979,
1357 01:54:21.511934 TX Bit5 (976~999) 24 987, Bit13 (968~991) 24 979,
1358 01:54:21.515555 TX Bit6 (976~1000) 25 988, Bit14 (969~993) 25 981,
1359 01:54:21.521912 TX Bit7 (978~1001) 24 989, Bit15 (973~996) 24 984,
1360 01:54:21.522363
1361 01:54:21.522707
1362 01:54:21.525524 TX Vref found, early break! 367< 373
1363 01:54:21.528693 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =753/100 ps
1364 01:54:21.531719 u1DelayCellOfst[0]=9 cells (7 PI)
1365 01:54:21.535218 u1DelayCellOfst[1]=6 cells (5 PI)
1366 01:54:21.538200 u1DelayCellOfst[2]=9 cells (7 PI)
1367 01:54:21.541846 u1DelayCellOfst[3]=0 cells (0 PI)
1368 01:54:21.544908 u1DelayCellOfst[4]=5 cells (4 PI)
1369 01:54:21.548122 u1DelayCellOfst[5]=2 cells (2 PI)
1370 01:54:21.551748 u1DelayCellOfst[6]=3 cells (3 PI)
1371 01:54:21.554748 u1DelayCellOfst[7]=5 cells (4 PI)
1372 01:54:21.558414 Byte0, DQ PI dly=985, DQM PI dly= 988
1373 01:54:21.561795 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 25)
1374 01:54:21.562315
1375 01:54:21.565219 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 25)
1376 01:54:21.565789
1377 01:54:21.568645 u1DelayCellOfst[8]=0 cells (0 PI)
1378 01:54:21.571789 u1DelayCellOfst[9]=1 cells (1 PI)
1379 01:54:21.575253 u1DelayCellOfst[10]=10 cells (8 PI)
1380 01:54:21.578164 u1DelayCellOfst[11]=1 cells (1 PI)
1381 01:54:21.581339 u1DelayCellOfst[12]=2 cells (2 PI)
1382 01:54:21.585347 u1DelayCellOfst[13]=2 cells (2 PI)
1383 01:54:21.588403 u1DelayCellOfst[14]=5 cells (4 PI)
1384 01:54:21.591437 u1DelayCellOfst[15]=9 cells (7 PI)
1385 01:54:21.594472 Byte1, DQ PI dly=977, DQM PI dly= 981
1386 01:54:21.598056 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 17)
1387 01:54:21.598540
1388 01:54:21.601534 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 17)
1389 01:54:21.604439
1390 01:54:21.604875 Write Rank0 MR14 =0x1e
1391 01:54:21.605216
1392 01:54:21.607966 Final TX Range 0 Vref 30
1393 01:54:21.608400
1394 01:54:21.614233 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
1395 01:54:21.614630
1396 01:54:21.621259 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
1397 01:54:21.627902 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
1398 01:54:21.634481 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
1399 01:54:21.637792 Write Rank0 MR3 =0xb0
1400 01:54:21.638309 DramC Write-DBI on
1401 01:54:21.638652 ==
1402 01:54:21.644230 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1403 01:54:21.647169 fsp= 1, odt_onoff= 1, Byte mode= 0
1404 01:54:21.647602 ==
1405 01:54:21.650903 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
1406 01:54:21.651419
1407 01:54:21.653677 Begin, DQ Scan Range 701~765
1408 01:54:21.654106
1409 01:54:21.654439
1410 01:54:21.657164 TX Vref Scan disable
1411 01:54:21.660832 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1412 01:54:21.664074 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1413 01:54:21.667124 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1414 01:54:21.670410 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1415 01:54:21.673928 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1416 01:54:21.677248 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
1417 01:54:21.680167 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
1418 01:54:21.683731 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
1419 01:54:21.686702 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
1420 01:54:21.690285 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
1421 01:54:21.693524 711 |2 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
1422 01:54:21.696674 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
1423 01:54:21.699944 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
1424 01:54:21.706792 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
1425 01:54:21.709850 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
1426 01:54:21.712842 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
1427 01:54:21.716648 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB]
1428 01:54:21.720030 718 |2 6 14|[0] xxxxxxxx oooooooo [MSB]
1429 01:54:21.723465 719 |2 6 15|[0] xxxxxxxx oooooooo [MSB]
1430 01:54:21.725892 720 |2 6 16|[0] xxxxxxxx oooooooo [MSB]
1431 01:54:21.733218 736 |2 6 32|[0] oooooooo xxxxxxxx [MSB]
1432 01:54:21.736424 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
1433 01:54:21.739814 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
1434 01:54:21.743101 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
1435 01:54:21.746380 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
1436 01:54:21.749598 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
1437 01:54:21.753718 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
1438 01:54:21.756521 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
1439 01:54:21.759690 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB]
1440 01:54:21.762938 745 |2 6 41|[0] oooooooo xxxxxxxx [MSB]
1441 01:54:21.766909 746 |2 6 42|[0] oooooooo xxxxxxxx [MSB]
1442 01:54:21.770146 747 |2 6 43|[0] oooooooo xxxxxxxx [MSB]
1443 01:54:21.772702 748 |2 6 44|[0] xxxxxxxx xxxxxxxx [MSB]
1444 01:54:21.776706 Byte0, DQ PI dly=734, DQM PI dly= 734
1445 01:54:21.783403 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 30)
1446 01:54:21.783880
1447 01:54:21.786038 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 30)
1448 01:54:21.786436
1449 01:54:21.789290 Byte1, DQ PI dly=723, DQM PI dly= 723
1450 01:54:21.796146 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 19)
1451 01:54:21.796535
1452 01:54:21.799917 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 19)
1453 01:54:21.800316
1454 01:54:21.806161 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
1455 01:54:21.812698 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
1456 01:54:21.819137 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
1457 01:54:21.822490 Write Rank0 MR3 =0x30
1458 01:54:21.822878 DramC Write-DBI off
1459 01:54:21.823181
1460 01:54:21.825649 [DATLAT]
1461 01:54:21.829446 Freq=1600, CH0 RK0, use_rxtx_scan=0
1462 01:54:21.829894
1463 01:54:21.830198 DATLAT Default: 0xf
1464 01:54:21.832691 7, 0xFFFF, sum=0
1465 01:54:21.833170 8, 0xFFFF, sum=0
1466 01:54:21.836007 9, 0xFFFF, sum=0
1467 01:54:21.836404 10, 0xFFFF, sum=0
1468 01:54:21.839302 11, 0xFFFF, sum=0
1469 01:54:21.839708 12, 0xFFFF, sum=0
1470 01:54:21.842835 13, 0xFFFF, sum=0
1471 01:54:21.843315 14, 0x0, sum=1
1472 01:54:21.843624 15, 0x0, sum=2
1473 01:54:21.846337 16, 0x0, sum=3
1474 01:54:21.846933 17, 0x0, sum=4
1475 01:54:21.852893 pattern=2 first_step=14 total pass=5 best_step=16
1476 01:54:21.853366 ==
1477 01:54:21.855263 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1478 01:54:21.858850 fsp= 1, odt_onoff= 1, Byte mode= 0
1479 01:54:21.859326 ==
1480 01:54:21.865246 Start DQ dly to find pass range UseTestEngine =1
1481 01:54:21.868791 x-axis: bit #, y-axis: DQ dly (-127~63)
1482 01:54:21.869307 RX Vref Scan = 1
1483 01:54:21.983917
1484 01:54:21.984420 RX Vref found, early break!
1485 01:54:21.984751
1486 01:54:21.990457 Final RX Vref 11, apply to both rank0 and 1
1487 01:54:21.990969 ==
1488 01:54:21.993504 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1489 01:54:21.996964 fsp= 1, odt_onoff= 1, Byte mode= 0
1490 01:54:21.997494 ==
1491 01:54:21.997878 DQS Delay:
1492 01:54:22.000186 DQS0 = 0, DQS1 = 0
1493 01:54:22.000696 DQM Delay:
1494 01:54:22.003596 DQM0 = 19, DQM1 = 19
1495 01:54:22.004048 DQ Delay:
1496 01:54:22.007103 DQ0 =22, DQ1 =22, DQ2 =23, DQ3 =15
1497 01:54:22.010093 DQ4 =21, DQ5 =16, DQ6 =19, DQ7 =20
1498 01:54:22.013328 DQ8 =15, DQ9 =17, DQ10 =25, DQ11 =16
1499 01:54:22.016942 DQ12 =19, DQ13 =18, DQ14 =19, DQ15 =23
1500 01:54:22.017453
1501 01:54:22.017837
1502 01:54:22.018147
1503 01:54:22.020005 [DramC_TX_OE_Calibration] TA2
1504 01:54:22.023408 Original DQ_B0 (3 6) =30, OEN = 27
1505 01:54:22.026979 Original DQ_B1 (3 6) =30, OEN = 27
1506 01:54:22.030163 23, 0x0, End_B0=23 End_B1=23
1507 01:54:22.033018 24, 0x0, End_B0=24 End_B1=24
1508 01:54:22.033536 25, 0x0, End_B0=25 End_B1=25
1509 01:54:22.036457 26, 0x0, End_B0=26 End_B1=26
1510 01:54:22.040264 27, 0x0, End_B0=27 End_B1=27
1511 01:54:22.043369 28, 0x0, End_B0=28 End_B1=28
1512 01:54:22.043887 29, 0x0, End_B0=29 End_B1=29
1513 01:54:22.046673 30, 0x0, End_B0=30 End_B1=30
1514 01:54:22.049887 31, 0xFFFF, End_B0=30 End_B1=30
1515 01:54:22.056002 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
1516 01:54:22.059527 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
1517 01:54:22.059984
1518 01:54:22.060327
1519 01:54:22.062747 Write Rank0 MR23 =0x3f
1520 01:54:22.063185 [DQSOSC]
1521 01:54:22.073240 [DQSOSCAuto] RK0, (LSB)MR18= 0xacac, (MSB)MR19= 0x202, tDQSOscB0 = 460 ps tDQSOscB1 = 460 ps
1522 01:54:22.079757 CH0_RK0: MR19=0x202, MR18=0xACAC, DQSOSC=460, MR23=63, INC=11, DEC=17
1523 01:54:22.080251 Write Rank0 MR23 =0x3f
1524 01:54:22.082556 [DQSOSC]
1525 01:54:22.089325 [DQSOSCAuto] RK0, (LSB)MR18= 0xaeae, (MSB)MR19= 0x202, tDQSOscB0 = 459 ps tDQSOscB1 = 459 ps
1526 01:54:22.092356 CH0 RK0: MR19=202, MR18=AEAE
1527 01:54:22.096343 [RankSwap] Rank num 2, (Multi 1), Rank 1
1528 01:54:22.098850 Write Rank0 MR2 =0xad
1529 01:54:22.099277 [Write Leveling]
1530 01:54:22.101942 delay byte0 byte1 byte2 byte3
1531 01:54:22.102372
1532 01:54:22.102706 10 0 0
1533 01:54:22.105430 11 0 0
1534 01:54:22.105914 12 0 0
1535 01:54:22.108891 13 0 0
1536 01:54:22.109326 14 0 0
1537 01:54:22.111811 15 0 0
1538 01:54:22.112375 16 0 0
1539 01:54:22.112839 17 0 0
1540 01:54:22.115116 18 0 0
1541 01:54:22.115513 19 0 0
1542 01:54:22.118409 20 0 0
1543 01:54:22.118803 21 0 0
1544 01:54:22.121704 22 0 ff
1545 01:54:22.122103 23 0 ff
1546 01:54:22.122411 24 0 ff
1547 01:54:22.125324 25 0 ff
1548 01:54:22.125855 26 0 ff
1549 01:54:22.128388 27 0 ff
1550 01:54:22.128797 28 0 ff
1551 01:54:22.131989 29 0 ff
1552 01:54:22.132467 30 0 ff
1553 01:54:22.132780 31 0 ff
1554 01:54:22.135030 32 ff ff
1555 01:54:22.135426 33 ff ff
1556 01:54:22.138504 34 ff ff
1557 01:54:22.138982 35 ff ff
1558 01:54:22.141695 36 ff ff
1559 01:54:22.142091 37 ff ff
1560 01:54:22.145021 38 ff ff
1561 01:54:22.148802 pass bytecount = 0xff (0xff: all bytes pass)
1562 01:54:22.149274
1563 01:54:22.149621 DQS0 dly: 32
1564 01:54:22.152115 DQS1 dly: 22
1565 01:54:22.152586 Write Rank0 MR2 =0x2d
1566 01:54:22.155281 [RankSwap] Rank num 2, (Multi 1), Rank 0
1567 01:54:22.158436 Write Rank1 MR1 =0xd6
1568 01:54:22.158823 [Gating]
1569 01:54:22.159126 ==
1570 01:54:22.164889 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1571 01:54:22.168416 fsp= 1, odt_onoff= 1, Byte mode= 0
1572 01:54:22.168806 ==
1573 01:54:22.171593 3 1 0 |3534 2c2b |(11 11)(11 11) |(0 0)(1 1)| 0
1574 01:54:22.178255 3 1 4 |3534 2c2b |(11 11)(11 11) |(0 0)(1 1)| 0
1575 01:54:22.181622 3 1 8 |3534 2c2b |(11 11)(11 11) |(0 0)(1 1)| 0
1576 01:54:22.185051 3 1 12 |3534 2c2b |(11 11)(11 11) |(1 1)(0 0)| 0
1577 01:54:22.191447 3 1 16 |3534 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
1578 01:54:22.194693 3 1 20 |3534 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
1579 01:54:22.197631 3 1 24 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
1580 01:54:22.204570 3 1 28 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
1581 01:54:22.208203 3 2 0 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
1582 01:54:22.211230 3 2 4 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
1583 01:54:22.218130 3 2 8 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
1584 01:54:22.221045 3 2 12 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
1585 01:54:22.224920 3 2 16 |3534 2c2b |(11 11)(11 11) |(1 1)(0 0)| 0
1586 01:54:22.228377 3 2 20 |e0e 2c2c |(11 11)(11 0) |(1 1)(0 0)| 0
1587 01:54:22.234767 3 2 24 |3d3d 1818 |(11 11)(11 11) |(1 1)(0 0)| 0
1588 01:54:22.237813 3 2 28 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
1589 01:54:22.240768 3 3 0 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
1590 01:54:22.247027 3 3 4 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
1591 01:54:22.251102 3 3 8 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
1592 01:54:22.254290 3 3 12 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
1593 01:54:22.261104 3 3 16 |3d3d 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
1594 01:54:22.264367 3 3 20 |403 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
1595 01:54:22.267547 3 3 24 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
1596 01:54:22.270531 [Byte 0] Lead/lag Transition tap number (1)
1597 01:54:22.277215 [Byte 1] Lead/lag falling Transition (3, 3, 24)
1598 01:54:22.280764 3 3 28 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1599 01:54:22.283440 3 4 0 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1600 01:54:22.290166 3 4 4 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1601 01:54:22.294034 3 4 8 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
1602 01:54:22.297001 3 4 12 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
1603 01:54:22.303471 3 4 16 |505 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
1604 01:54:22.306966 3 4 20 |2323 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
1605 01:54:22.310458 3 4 24 |3d3d 908 |(11 11)(11 11) |(1 1)(1 1)| 0
1606 01:54:22.317021 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1607 01:54:22.320512 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1608 01:54:22.323925 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1609 01:54:22.329875 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1610 01:54:22.333193 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1611 01:54:22.336463 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1612 01:54:22.342714 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1613 01:54:22.345910 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1614 01:54:22.349645 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1615 01:54:22.356030 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1616 01:54:22.359793 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1617 01:54:22.362505 [Byte 0] Lead/lag falling Transition (3, 6, 4)
1618 01:54:22.366323 3 6 8 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
1619 01:54:22.372958 [Byte 1] Lead/lag falling Transition (3, 6, 8)
1620 01:54:22.375735 3 6 12 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 0)| 0
1621 01:54:22.379211 [Byte 0] Lead/lag Transition tap number (3)
1622 01:54:22.385614 3 6 16 |3e3d 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
1623 01:54:22.388836 [Byte 1] Lead/lag Transition tap number (3)
1624 01:54:22.392419 3 6 20 |606 3e3d |(11 11)(11 11) |(0 0)(0 0)| 0
1625 01:54:22.395907 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1626 01:54:22.398946 [Byte 0]First pass (3, 6, 24)
1627 01:54:22.402252 [Byte 1]First pass (3, 6, 24)
1628 01:54:22.405386 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1629 01:54:22.408917 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1630 01:54:22.412149 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1631 01:54:22.418751 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1632 01:54:22.422421 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1633 01:54:22.425638 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1634 01:54:22.429038 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1635 01:54:22.434956 3 7 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1636 01:54:22.438297 All bytes gating window > 1UI, Early break!
1637 01:54:22.438812
1638 01:54:22.441299 best DQS0 dly(2T, 0.5T, PI) = (3, 6, 10)
1639 01:54:22.441831
1640 01:54:22.445128 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 14)
1641 01:54:22.445677
1642 01:54:22.446017
1643 01:54:22.446322
1644 01:54:22.448106 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 10)
1645 01:54:22.451612
1646 01:54:22.454969 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 14)
1647 01:54:22.455478
1648 01:54:22.455814
1649 01:54:22.456130 Write Rank1 MR1 =0x56
1650 01:54:22.456428
1651 01:54:22.458040 best RODT dly(2T, 0.5T) = (2, 3)
1652 01:54:22.458468
1653 01:54:22.461699 best RODT dly(2T, 0.5T) = (2, 3)
1654 01:54:22.462223 ==
1655 01:54:22.467742 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1656 01:54:22.471063 fsp= 1, odt_onoff= 1, Byte mode= 0
1657 01:54:22.471494 ==
1658 01:54:22.474411 Start DQ dly to find pass range UseTestEngine =0
1659 01:54:22.477506 x-axis: bit #, y-axis: DQ dly (-127~63)
1660 01:54:22.481248 RX Vref Scan = 0
1661 01:54:22.484259 -26, [0] xxxxxxxx xxxxxxxx [MSB]
1662 01:54:22.488379 -25, [0] xxxxxxxx xxxxxxxx [MSB]
1663 01:54:22.488902 -24, [0] xxxxxxxx xxxxxxxx [MSB]
1664 01:54:22.491255 -23, [0] xxxxxxxx xxxxxxxx [MSB]
1665 01:54:22.494763 -22, [0] xxxxxxxx xxxxxxxx [MSB]
1666 01:54:22.497768 -21, [0] xxxxxxxx xxxxxxxx [MSB]
1667 01:54:22.500907 -20, [0] xxxxxxxx xxxxxxxx [MSB]
1668 01:54:22.504238 -19, [0] xxxxxxxx xxxxxxxx [MSB]
1669 01:54:22.508028 -18, [0] xxxxxxxx xxxxxxxx [MSB]
1670 01:54:22.510391 -17, [0] xxxxxxxx xxxxxxxx [MSB]
1671 01:54:22.513964 -16, [0] xxxxxxxx xxxxxxxx [MSB]
1672 01:54:22.516812 -15, [0] xxxxxxxx xxxxxxxx [MSB]
1673 01:54:22.517254 -14, [0] xxxxxxxx xxxxxxxx [MSB]
1674 01:54:22.520543 -13, [0] xxxxxxxx xxxxxxxx [MSB]
1675 01:54:22.523817 -12, [0] xxxxxxxx xxxxxxxx [MSB]
1676 01:54:22.526684 -11, [0] xxxxxxxx xxxxxxxx [MSB]
1677 01:54:22.530096 -10, [0] xxxxxxxx xxxxxxxx [MSB]
1678 01:54:22.533625 -9, [0] xxxxxxxx xxxxxxxx [MSB]
1679 01:54:22.536909 -8, [0] xxxxxxxx xxxxxxxx [MSB]
1680 01:54:22.540402 -7, [0] xxxxxxxx xxxxxxxx [MSB]
1681 01:54:22.540855 -6, [0] xxxxxxxx xxxxxxxx [MSB]
1682 01:54:22.544082 -5, [0] xxxxxxxx xxxxxxxx [MSB]
1683 01:54:22.547238 -4, [0] xxxxxxxx xxxxxxxx [MSB]
1684 01:54:22.550294 -3, [0] xxxxxxxx xxxxxxxx [MSB]
1685 01:54:22.553851 -2, [0] xxxoxxxx xxxxxxxx [MSB]
1686 01:54:22.557277 -1, [0] xxxoxxxx xxxxxxxx [MSB]
1687 01:54:22.560492 0, [0] xxxoxoox oxxoxxxx [MSB]
1688 01:54:22.561011 1, [0] xxxoxooo oxxoxxxx [MSB]
1689 01:54:22.563783 2, [0] xxxoxooo oxxoxxxx [MSB]
1690 01:54:22.566907 3, [0] xxxooooo ooxoxxxx [MSB]
1691 01:54:22.570050 4, [0] ooxooooo ooxoooxx [MSB]
1692 01:54:22.573630 5, [0] oooooooo ooxoooox [MSB]
1693 01:54:22.576893 6, [0] oooooooo ooxooooo [MSB]
1694 01:54:22.577429 7, [0] oooooooo ooxooooo [MSB]
1695 01:54:22.579999 8, [0] oooooooo ooxooooo [MSB]
1696 01:54:22.583258 32, [0] oooxoooo oooooooo [MSB]
1697 01:54:22.586377 33, [0] oooxoxoo oooooooo [MSB]
1698 01:54:22.590010 34, [0] oooxoxoo xooooooo [MSB]
1699 01:54:22.593164 35, [0] oooxoxoo xooxoooo [MSB]
1700 01:54:22.596951 36, [0] oooxoxoo xooxxooo [MSB]
1701 01:54:22.597465 37, [0] oooxoxxx xxoxxxxo [MSB]
1702 01:54:22.599774 38, [0] xooxoxxx xxoxxxxo [MSB]
1703 01:54:22.603413 39, [0] xxoxoxxx xxoxxxxo [MSB]
1704 01:54:22.606289 40, [0] xxxxoxxx xxoxxxxo [MSB]
1705 01:54:22.609783 41, [0] xxxxxxxx xxoxxxxx [MSB]
1706 01:54:22.613445 42, [0] xxxxxxxx xxoxxxxx [MSB]
1707 01:54:22.616363 43, [0] xxxxxxxx xxxxxxxx [MSB]
1708 01:54:22.620175 iDelay=43, Bit 0, Center 20 (4 ~ 37) 34
1709 01:54:22.623126 iDelay=43, Bit 1, Center 21 (4 ~ 38) 35
1710 01:54:22.626298 iDelay=43, Bit 2, Center 22 (5 ~ 39) 35
1711 01:54:22.629691 iDelay=43, Bit 3, Center 14 (-2 ~ 31) 34
1712 01:54:22.632726 iDelay=43, Bit 4, Center 21 (3 ~ 40) 38
1713 01:54:22.636844 iDelay=43, Bit 5, Center 16 (0 ~ 32) 33
1714 01:54:22.639879 iDelay=43, Bit 6, Center 18 (0 ~ 36) 37
1715 01:54:22.642678 iDelay=43, Bit 7, Center 18 (1 ~ 36) 36
1716 01:54:22.646316 iDelay=43, Bit 8, Center 16 (0 ~ 33) 34
1717 01:54:22.649150 iDelay=43, Bit 9, Center 19 (3 ~ 36) 34
1718 01:54:22.652515 iDelay=43, Bit 10, Center 25 (9 ~ 42) 34
1719 01:54:22.656311 iDelay=43, Bit 11, Center 17 (0 ~ 34) 35
1720 01:54:22.662176 iDelay=43, Bit 12, Center 19 (4 ~ 35) 32
1721 01:54:22.665713 iDelay=43, Bit 13, Center 20 (4 ~ 36) 33
1722 01:54:22.669067 iDelay=43, Bit 14, Center 20 (5 ~ 36) 32
1723 01:54:22.672348 iDelay=43, Bit 15, Center 23 (6 ~ 40) 35
1724 01:54:22.672788 ==
1725 01:54:22.675720 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1726 01:54:22.678852 fsp= 1, odt_onoff= 1, Byte mode= 0
1727 01:54:22.679290 ==
1728 01:54:22.682026 DQS Delay:
1729 01:54:22.682463 DQS0 = 0, DQS1 = 0
1730 01:54:22.685289 DQM Delay:
1731 01:54:22.685965 DQM0 = 18, DQM1 = 19
1732 01:54:22.686500 DQ Delay:
1733 01:54:22.688809 DQ0 =20, DQ1 =21, DQ2 =22, DQ3 =14
1734 01:54:22.692339 DQ4 =21, DQ5 =16, DQ6 =18, DQ7 =18
1735 01:54:22.695371 DQ8 =16, DQ9 =19, DQ10 =25, DQ11 =17
1736 01:54:22.698742 DQ12 =19, DQ13 =20, DQ14 =20, DQ15 =23
1737 01:54:22.699171
1738 01:54:22.702088
1739 01:54:22.702516 DramC Write-DBI off
1740 01:54:22.702848 ==
1741 01:54:22.709209 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1742 01:54:22.712490 fsp= 1, odt_onoff= 1, Byte mode= 0
1743 01:54:22.713009 ==
1744 01:54:22.715099 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
1745 01:54:22.715533
1746 01:54:22.718380 Begin, DQ Scan Range 918~1174
1747 01:54:22.718812
1748 01:54:22.719144
1749 01:54:22.722107 TX Vref Scan disable
1750 01:54:22.725473 918 |3 4 22|[0] xxxxxxxx xxxxxxxx [MSB]
1751 01:54:22.729234 919 |3 4 23|[0] xxxxxxxx xxxxxxxx [MSB]
1752 01:54:22.732058 920 |3 4 24|[0] xxxxxxxx xxxxxxxx [MSB]
1753 01:54:22.735266 921 |3 4 25|[0] xxxxxxxx xxxxxxxx [MSB]
1754 01:54:22.738139 922 |3 4 26|[0] xxxxxxxx xxxxxxxx [MSB]
1755 01:54:22.741667 923 |3 4 27|[0] xxxxxxxx xxxxxxxx [MSB]
1756 01:54:22.745178 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB]
1757 01:54:22.748835 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
1758 01:54:22.751614 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
1759 01:54:22.755147 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
1760 01:54:22.758207 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
1761 01:54:22.761274 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
1762 01:54:22.767714 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
1763 01:54:22.771227 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
1764 01:54:22.774673 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
1765 01:54:22.778011 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
1766 01:54:22.781062 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
1767 01:54:22.783982 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
1768 01:54:22.787661 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
1769 01:54:22.790926 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
1770 01:54:22.793910 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
1771 01:54:22.797645 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
1772 01:54:22.800972 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
1773 01:54:22.804069 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
1774 01:54:22.807145 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
1775 01:54:22.810793 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
1776 01:54:22.817104 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
1777 01:54:22.821000 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
1778 01:54:22.823861 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
1779 01:54:22.827180 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
1780 01:54:22.830298 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
1781 01:54:22.833868 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
1782 01:54:22.837423 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
1783 01:54:22.840593 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
1784 01:54:22.843845 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
1785 01:54:22.847228 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
1786 01:54:22.850273 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
1787 01:54:22.853742 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
1788 01:54:22.856982 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1789 01:54:22.860223 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1790 01:54:22.866669 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1791 01:54:22.869811 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1792 01:54:22.873248 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1793 01:54:22.876475 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1794 01:54:22.879995 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
1795 01:54:22.883406 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
1796 01:54:22.886576 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
1797 01:54:22.889881 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
1798 01:54:22.893353 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
1799 01:54:22.896349 967 |3 6 7|[0] xxxxxxxx oxxoxxxx [MSB]
1800 01:54:22.899569 968 |3 6 8|[0] xxxxxxxx oxxoxxxx [MSB]
1801 01:54:22.902918 969 |3 6 9|[0] xxxxxxxx oxxoooxx [MSB]
1802 01:54:22.906225 970 |3 6 10|[0] xxxxxxxx ooxoooox [MSB]
1803 01:54:22.909937 971 |3 6 11|[0] xxxxxxxx ooxoooox [MSB]
1804 01:54:22.913324 972 |3 6 12|[0] xxxxxxxx ooxoooox [MSB]
1805 01:54:22.916217 973 |3 6 13|[0] xxxxxxxx ooxooooo [MSB]
1806 01:54:22.919666 974 |3 6 14|[0] xxxxxxxx oooooooo [MSB]
1807 01:54:22.926164 975 |3 6 15|[0] xxxxxxxx oooooooo [MSB]
1808 01:54:22.929786 976 |3 6 16|[0] xxxxxxxx oooooooo [MSB]
1809 01:54:22.933258 977 |3 6 17|[0] xxxxxxxx oooooooo [MSB]
1810 01:54:22.936046 978 |3 6 18|[0] xxxxxxxx oooooooo [MSB]
1811 01:54:22.939483 979 |3 6 19|[0] xxxoxooo oooooooo [MSB]
1812 01:54:22.942499 980 |3 6 20|[0] xoxooooo oooooooo [MSB]
1813 01:54:22.945744 981 |3 6 21|[0] xoxooooo oooooooo [MSB]
1814 01:54:22.949196 987 |3 6 27|[0] oooooooo xooxoooo [MSB]
1815 01:54:22.952005 988 |3 6 28|[0] oooooooo xxoxoooo [MSB]
1816 01:54:22.955505 989 |3 6 29|[0] oooooooo xxxxxxxx [MSB]
1817 01:54:22.958864 990 |3 6 30|[0] oooooooo xxxxxxxx [MSB]
1818 01:54:22.966191 991 |3 6 31|[0] oooooooo xxxxxxxx [MSB]
1819 01:54:22.969297 992 |3 6 32|[0] oooooooo xxxxxxxx [MSB]
1820 01:54:22.972859 993 |3 6 33|[0] oooooooo xxxxxxxx [MSB]
1821 01:54:22.975796 994 |3 6 34|[0] oooooooo xxxxxxxx [MSB]
1822 01:54:22.978396 995 |3 6 35|[0] oooooooo xxxxxxxx [MSB]
1823 01:54:22.982478 996 |3 6 36|[0] oooxoooo xxxxxxxx [MSB]
1824 01:54:22.984978 997 |3 6 37|[0] oooxoooo xxxxxxxx [MSB]
1825 01:54:22.988844 998 |3 6 38|[0] oooxoooo xxxxxxxx [MSB]
1826 01:54:22.992015 999 |3 6 39|[0] oooxoxoo xxxxxxxx [MSB]
1827 01:54:22.995273 1000 |3 6 40|[0] oooxoxxo xxxxxxxx [MSB]
1828 01:54:22.998358 1001 |3 6 41|[0] xxxxxxxx xxxxxxxx [MSB]
1829 01:54:23.001400 Byte0, DQ PI dly=989, DQM PI dly= 989
1830 01:54:23.008283 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 29)
1831 01:54:23.008805
1832 01:54:23.011635 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 29)
1833 01:54:23.012150
1834 01:54:23.015031 Byte1, DQ PI dly=978, DQM PI dly= 978
1835 01:54:23.018054 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 18)
1836 01:54:23.018573
1837 01:54:23.025000 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 18)
1838 01:54:23.025519
1839 01:54:23.025921 ==
1840 01:54:23.027909 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1841 01:54:23.031391 fsp= 1, odt_onoff= 1, Byte mode= 0
1842 01:54:23.031822 ==
1843 01:54:23.038143 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
1844 01:54:23.038802
1845 01:54:23.041166 Begin, DQ Scan Range 954~1018
1846 01:54:23.041750 Write Rank1 MR14 =0x0
1847 01:54:23.050659
1848 01:54:23.051158 CH=0, VrefRange= 0, VrefLevel = 0
1849 01:54:23.057435 TX Bit0 (984~997) 14 990, Bit8 (969~981) 13 975,
1850 01:54:23.060688 TX Bit1 (983~995) 13 989, Bit9 (973~982) 10 977,
1851 01:54:23.066966 TX Bit2 (985~996) 12 990, Bit10 (975~989) 15 982,
1852 01:54:23.070531 TX Bit3 (977~991) 15 984, Bit11 (971~981) 11 976,
1853 01:54:23.073975 TX Bit4 (984~996) 13 990, Bit12 (973~983) 11 978,
1854 01:54:23.080544 TX Bit5 (980~992) 13 986, Bit13 (973~984) 12 978,
1855 01:54:23.083752 TX Bit6 (981~993) 13 987, Bit14 (973~985) 13 979,
1856 01:54:23.090477 TX Bit7 (983~996) 14 989, Bit15 (975~987) 13 981,
1857 01:54:23.090916
1858 01:54:23.091257 Write Rank1 MR14 =0x2
1859 01:54:23.099816
1860 01:54:23.100324 CH=0, VrefRange= 0, VrefLevel = 2
1861 01:54:23.106264 TX Bit0 (984~998) 15 991, Bit8 (969~982) 14 975,
1862 01:54:23.109284 TX Bit1 (983~996) 14 989, Bit9 (973~983) 11 978,
1863 01:54:23.116132 TX Bit2 (984~998) 15 991, Bit10 (975~989) 15 982,
1864 01:54:23.119346 TX Bit3 (977~991) 15 984, Bit11 (971~982) 12 976,
1865 01:54:23.122760 TX Bit4 (983~996) 14 989, Bit12 (973~984) 12 978,
1866 01:54:23.129206 TX Bit5 (980~993) 14 986, Bit13 (972~984) 13 978,
1867 01:54:23.132505 TX Bit6 (980~994) 15 987, Bit14 (972~986) 15 979,
1868 01:54:23.138950 TX Bit7 (982~997) 16 989, Bit15 (975~988) 14 981,
1869 01:54:23.139408
1870 01:54:23.139718 Write Rank1 MR14 =0x4
1871 01:54:23.149290
1872 01:54:23.149859 CH=0, VrefRange= 0, VrefLevel = 4
1873 01:54:23.155278 TX Bit0 (984~998) 15 991, Bit8 (968~982) 15 975,
1874 01:54:23.158575 TX Bit1 (983~998) 16 990, Bit9 (972~983) 12 977,
1875 01:54:23.165389 TX Bit2 (984~999) 16 991, Bit10 (975~990) 16 982,
1876 01:54:23.168689 TX Bit3 (977~991) 15 984, Bit11 (970~982) 13 976,
1877 01:54:23.171693 TX Bit4 (982~997) 16 989, Bit12 (972~984) 13 978,
1878 01:54:23.178182 TX Bit5 (979~994) 16 986, Bit13 (972~985) 14 978,
1879 01:54:23.181839 TX Bit6 (979~994) 16 986, Bit14 (972~987) 16 979,
1880 01:54:23.188286 TX Bit7 (981~998) 18 989, Bit15 (975~988) 14 981,
1881 01:54:23.188861
1882 01:54:23.189206 Write Rank1 MR14 =0x6
1883 01:54:23.198138
1884 01:54:23.198685 CH=0, VrefRange= 0, VrefLevel = 6
1885 01:54:23.204627 TX Bit0 (984~999) 16 991, Bit8 (969~983) 15 976,
1886 01:54:23.207962 TX Bit1 (982~998) 17 990, Bit9 (972~984) 13 978,
1887 01:54:23.213896 TX Bit2 (984~999) 16 991, Bit10 (975~990) 16 982,
1888 01:54:23.217666 TX Bit3 (977~992) 16 984, Bit11 (970~982) 13 976,
1889 01:54:23.220749 TX Bit4 (982~998) 17 990, Bit12 (971~985) 15 978,
1890 01:54:23.227058 TX Bit5 (979~994) 16 986, Bit13 (971~986) 16 978,
1891 01:54:23.230401 TX Bit6 (979~996) 18 987, Bit14 (972~988) 17 980,
1892 01:54:23.237377 TX Bit7 (981~999) 19 990, Bit15 (974~989) 16 981,
1893 01:54:23.237898
1894 01:54:23.238259 Write Rank1 MR14 =0x8
1895 01:54:23.247170
1896 01:54:23.247682 CH=0, VrefRange= 0, VrefLevel = 8
1897 01:54:23.253704 TX Bit0 (983~999) 17 991, Bit8 (967~983) 17 975,
1898 01:54:23.256829 TX Bit1 (982~999) 18 990, Bit9 (970~984) 15 977,
1899 01:54:23.264077 TX Bit2 (984~999) 16 991, Bit10 (974~991) 18 982,
1900 01:54:23.266656 TX Bit3 (977~992) 16 984, Bit11 (969~983) 15 976,
1901 01:54:23.269966 TX Bit4 (982~999) 18 990, Bit12 (971~986) 16 978,
1902 01:54:23.276897 TX Bit5 (979~996) 18 987, Bit13 (971~987) 17 979,
1903 01:54:23.280539 TX Bit6 (979~997) 19 988, Bit14 (971~989) 19 980,
1904 01:54:23.283741 TX Bit7 (980~999) 20 989, Bit15 (974~989) 16 981,
1905 01:54:23.284177
1906 01:54:23.290008 wait MRW command Rank1 MR14 =0xa fired (1)
1907 01:54:23.290522 Write Rank1 MR14 =0xa
1908 01:54:23.300212
1909 01:54:23.303351 CH=0, VrefRange= 0, VrefLevel = 10
1910 01:54:23.306907 TX Bit0 (984~1000) 17 992, Bit8 (968~984) 17 976,
1911 01:54:23.310316 TX Bit1 (982~999) 18 990, Bit9 (971~985) 15 978,
1912 01:54:23.316591 TX Bit2 (983~1000) 18 991, Bit10 (974~991) 18 982,
1913 01:54:23.320028 TX Bit3 (977~993) 17 985, Bit11 (968~984) 17 976,
1914 01:54:23.323449 TX Bit4 (982~999) 18 990, Bit12 (970~986) 17 978,
1915 01:54:23.329963 TX Bit5 (978~996) 19 987, Bit13 (971~987) 17 979,
1916 01:54:23.332876 TX Bit6 (978~997) 20 987, Bit14 (971~989) 19 980,
1917 01:54:23.339645 TX Bit7 (980~1000) 21 990, Bit15 (974~990) 17 982,
1918 01:54:23.340147
1919 01:54:23.340485 Write Rank1 MR14 =0xc
1920 01:54:23.349630
1921 01:54:23.352706 CH=0, VrefRange= 0, VrefLevel = 12
1922 01:54:23.356211 TX Bit0 (983~1000) 18 991, Bit8 (967~984) 18 975,
1923 01:54:23.359130 TX Bit1 (981~1000) 20 990, Bit9 (971~987) 17 979,
1924 01:54:23.365723 TX Bit2 (983~1000) 18 991, Bit10 (974~992) 19 983,
1925 01:54:23.369009 TX Bit3 (976~993) 18 984, Bit11 (968~984) 17 976,
1926 01:54:23.372062 TX Bit4 (981~999) 19 990, Bit12 (970~987) 18 978,
1927 01:54:23.379521 TX Bit5 (978~997) 20 987, Bit13 (970~988) 19 979,
1928 01:54:23.382150 TX Bit6 (978~998) 21 988, Bit14 (970~989) 20 979,
1929 01:54:23.389206 TX Bit7 (980~1000) 21 990, Bit15 (974~990) 17 982,
1930 01:54:23.389677
1931 01:54:23.390018 Write Rank1 MR14 =0xe
1932 01:54:23.399441
1933 01:54:23.402295 CH=0, VrefRange= 0, VrefLevel = 14
1934 01:54:23.405540 TX Bit0 (983~1000) 18 991, Bit8 (967~985) 19 976,
1935 01:54:23.409267 TX Bit1 (980~1000) 21 990, Bit9 (971~987) 17 979,
1936 01:54:23.415593 TX Bit2 (983~1000) 18 991, Bit10 (974~992) 19 983,
1937 01:54:23.418929 TX Bit3 (976~994) 19 985, Bit11 (968~985) 18 976,
1938 01:54:23.422365 TX Bit4 (981~999) 19 990, Bit12 (970~988) 19 979,
1939 01:54:23.428959 TX Bit5 (978~998) 21 988, Bit13 (970~989) 20 979,
1940 01:54:23.432344 TX Bit6 (978~999) 22 988, Bit14 (970~990) 21 980,
1941 01:54:23.438885 TX Bit7 (980~1000) 21 990, Bit15 (974~990) 17 982,
1942 01:54:23.439449
1943 01:54:23.439807 Write Rank1 MR14 =0x10
1944 01:54:23.449008
1945 01:54:23.452284 CH=0, VrefRange= 0, VrefLevel = 16
1946 01:54:23.455541 TX Bit0 (983~1001) 19 992, Bit8 (966~985) 20 975,
1947 01:54:23.458868 TX Bit1 (980~1000) 21 990, Bit9 (969~988) 20 978,
1948 01:54:23.465353 TX Bit2 (983~1001) 19 992, Bit10 (973~993) 21 983,
1949 01:54:23.468918 TX Bit3 (976~995) 20 985, Bit11 (967~986) 20 976,
1950 01:54:23.472021 TX Bit4 (980~1000) 21 990, Bit12 (969~989) 21 979,
1951 01:54:23.479005 TX Bit5 (977~998) 22 987, Bit13 (969~989) 21 979,
1952 01:54:23.481995 TX Bit6 (978~999) 22 988, Bit14 (970~990) 21 980,
1953 01:54:23.488581 TX Bit7 (979~1001) 23 990, Bit15 (974~991) 18 982,
1954 01:54:23.489018
1955 01:54:23.489351 Write Rank1 MR14 =0x12
1956 01:54:23.499098
1957 01:54:23.502209 CH=0, VrefRange= 0, VrefLevel = 18
1958 01:54:23.505979 TX Bit0 (982~1002) 21 992, Bit8 (966~987) 22 976,
1959 01:54:23.509758 TX Bit1 (980~1001) 22 990, Bit9 (969~988) 20 978,
1960 01:54:23.516198 TX Bit2 (982~1001) 20 991, Bit10 (973~994) 22 983,
1961 01:54:23.519235 TX Bit3 (975~996) 22 985, Bit11 (967~986) 20 976,
1962 01:54:23.521976 TX Bit4 (979~1000) 22 989, Bit12 (968~989) 22 978,
1963 01:54:23.528439 TX Bit5 (977~998) 22 987, Bit13 (968~990) 23 979,
1964 01:54:23.532516 TX Bit6 (978~999) 22 988, Bit14 (969~990) 22 979,
1965 01:54:23.538430 TX Bit7 (978~1001) 24 989, Bit15 (973~991) 19 982,
1966 01:54:23.538941
1967 01:54:23.539279 Write Rank1 MR14 =0x14
1968 01:54:23.549743
1969 01:54:23.553085 CH=0, VrefRange= 0, VrefLevel = 20
1970 01:54:23.556461 TX Bit0 (982~1002) 21 992, Bit8 (966~988) 23 977,
1971 01:54:23.559376 TX Bit1 (980~1001) 22 990, Bit9 (968~988) 21 978,
1972 01:54:23.566285 TX Bit2 (982~1002) 21 992, Bit10 (973~994) 22 983,
1973 01:54:23.569568 TX Bit3 (975~997) 23 986, Bit11 (967~987) 21 977,
1974 01:54:23.576110 TX Bit4 (979~1001) 23 990, Bit12 (968~989) 22 978,
1975 01:54:23.579200 TX Bit5 (977~999) 23 988, Bit13 (968~990) 23 979,
1976 01:54:23.582412 TX Bit6 (977~1000) 24 988, Bit14 (969~991) 23 980,
1977 01:54:23.588844 TX Bit7 (979~1001) 23 990, Bit15 (973~992) 20 982,
1978 01:54:23.589282
1979 01:54:23.589650 Write Rank1 MR14 =0x16
1980 01:54:23.599770
1981 01:54:23.603375 CH=0, VrefRange= 0, VrefLevel = 22
1982 01:54:23.606233 TX Bit0 (982~1003) 22 992, Bit8 (966~988) 23 977,
1983 01:54:23.609258 TX Bit1 (979~1002) 24 990, Bit9 (968~989) 22 978,
1984 01:54:23.616013 TX Bit2 (981~1002) 22 991, Bit10 (973~995) 23 984,
1985 01:54:23.619963 TX Bit3 (975~997) 23 986, Bit11 (967~988) 22 977,
1986 01:54:23.626124 TX Bit4 (978~1002) 25 990, Bit12 (968~990) 23 979,
1987 01:54:23.629505 TX Bit5 (977~999) 23 988, Bit13 (968~990) 23 979,
1988 01:54:23.632580 TX Bit6 (977~1000) 24 988, Bit14 (969~991) 23 980,
1989 01:54:23.639100 TX Bit7 (978~1002) 25 990, Bit15 (973~993) 21 983,
1990 01:54:23.639599
1991 01:54:23.640031 Write Rank1 MR14 =0x18
1992 01:54:23.651056
1993 01:54:23.654142 CH=0, VrefRange= 0, VrefLevel = 24
1994 01:54:23.656718 TX Bit0 (981~1004) 24 992, Bit8 (966~988) 23 977,
1995 01:54:23.659922 TX Bit1 (979~1003) 25 991, Bit9 (968~989) 22 978,
1996 01:54:23.666770 TX Bit2 (981~1003) 23 992, Bit10 (972~995) 24 983,
1997 01:54:23.670235 TX Bit3 (975~997) 23 986, Bit11 (966~988) 23 977,
1998 01:54:23.676572 TX Bit4 (978~1002) 25 990, Bit12 (968~990) 23 979,
1999 01:54:23.679719 TX Bit5 (977~999) 23 988, Bit13 (967~990) 24 978,
2000 01:54:23.682940 TX Bit6 (977~1001) 25 989, Bit14 (968~991) 24 979,
2001 01:54:23.689773 TX Bit7 (978~1003) 26 990, Bit15 (972~993) 22 982,
2002 01:54:23.690414
2003 01:54:23.690775 Write Rank1 MR14 =0x1a
2004 01:54:23.700720
2005 01:54:23.704337 CH=0, VrefRange= 0, VrefLevel = 26
2006 01:54:23.707581 TX Bit0 (981~1003) 23 992, Bit8 (965~989) 25 977,
2007 01:54:23.711567 TX Bit1 (979~1003) 25 991, Bit9 (968~990) 23 979,
2008 01:54:23.717612 TX Bit2 (980~1004) 25 992, Bit10 (973~996) 24 984,
2009 01:54:23.720513 TX Bit3 (975~998) 24 986, Bit11 (966~989) 24 977,
2010 01:54:23.724502 TX Bit4 (978~1002) 25 990, Bit12 (967~990) 24 978,
2011 01:54:23.730979 TX Bit5 (977~1000) 24 988, Bit13 (967~990) 24 978,
2012 01:54:23.734047 TX Bit6 (977~1001) 25 989, Bit14 (968~991) 24 979,
2013 01:54:23.740776 TX Bit7 (978~1003) 26 990, Bit15 (972~995) 24 983,
2014 01:54:23.741288
2015 01:54:23.741676 Write Rank1 MR14 =0x1c
2016 01:54:23.752223
2017 01:54:23.754919 CH=0, VrefRange= 0, VrefLevel = 28
2018 01:54:23.758211 TX Bit0 (981~1005) 25 993, Bit8 (965~988) 24 976,
2019 01:54:23.761501 TX Bit1 (979~1004) 26 991, Bit9 (967~989) 23 978,
2020 01:54:23.768593 TX Bit2 (980~1004) 25 992, Bit10 (972~996) 25 984,
2021 01:54:23.771494 TX Bit3 (975~998) 24 986, Bit11 (966~989) 24 977,
2022 01:54:23.775079 TX Bit4 (978~1002) 25 990, Bit12 (967~990) 24 978,
2023 01:54:23.781422 TX Bit5 (976~1000) 25 988, Bit13 (967~989) 23 978,
2024 01:54:23.784775 TX Bit6 (977~1001) 25 989, Bit14 (968~991) 24 979,
2025 01:54:23.791506 TX Bit7 (978~1003) 26 990, Bit15 (972~994) 23 983,
2026 01:54:23.791994
2027 01:54:23.792338 Write Rank1 MR14 =0x1e
2028 01:54:23.802714
2029 01:54:23.806084 CH=0, VrefRange= 0, VrefLevel = 30
2030 01:54:23.809221 TX Bit0 (981~1005) 25 993, Bit8 (965~988) 24 976,
2031 01:54:23.812689 TX Bit1 (979~1004) 26 991, Bit9 (967~989) 23 978,
2032 01:54:23.818694 TX Bit2 (980~1004) 25 992, Bit10 (972~996) 25 984,
2033 01:54:23.821834 TX Bit3 (975~998) 24 986, Bit11 (966~989) 24 977,
2034 01:54:23.828937 TX Bit4 (978~1002) 25 990, Bit12 (967~990) 24 978,
2035 01:54:23.832058 TX Bit5 (976~1000) 25 988, Bit13 (967~989) 23 978,
2036 01:54:23.835063 TX Bit6 (977~1001) 25 989, Bit14 (968~991) 24 979,
2037 01:54:23.841684 TX Bit7 (978~1003) 26 990, Bit15 (972~994) 23 983,
2038 01:54:23.842089
2039 01:54:23.842556 Write Rank1 MR14 =0x20
2040 01:54:23.853122
2041 01:54:23.856685 CH=0, VrefRange= 0, VrefLevel = 32
2042 01:54:23.859731 TX Bit0 (981~1005) 25 993, Bit8 (965~988) 24 976,
2043 01:54:23.863256 TX Bit1 (979~1004) 26 991, Bit9 (967~989) 23 978,
2044 01:54:23.869225 TX Bit2 (980~1004) 25 992, Bit10 (972~996) 25 984,
2045 01:54:23.872487 TX Bit3 (975~998) 24 986, Bit11 (966~989) 24 977,
2046 01:54:23.879287 TX Bit4 (978~1002) 25 990, Bit12 (967~990) 24 978,
2047 01:54:23.882489 TX Bit5 (976~1000) 25 988, Bit13 (967~989) 23 978,
2048 01:54:23.885914 TX Bit6 (977~1001) 25 989, Bit14 (968~991) 24 979,
2049 01:54:23.892696 TX Bit7 (978~1003) 26 990, Bit15 (972~994) 23 983,
2050 01:54:23.893095
2051 01:54:23.893402 Write Rank1 MR14 =0x22
2052 01:54:23.904174
2053 01:54:23.907737 CH=0, VrefRange= 0, VrefLevel = 34
2054 01:54:23.911055 TX Bit0 (981~1005) 25 993, Bit8 (965~988) 24 976,
2055 01:54:23.913957 TX Bit1 (979~1004) 26 991, Bit9 (967~989) 23 978,
2056 01:54:23.920673 TX Bit2 (980~1004) 25 992, Bit10 (972~996) 25 984,
2057 01:54:23.924084 TX Bit3 (975~998) 24 986, Bit11 (966~989) 24 977,
2058 01:54:23.930748 TX Bit4 (978~1002) 25 990, Bit12 (967~990) 24 978,
2059 01:54:23.934031 TX Bit5 (976~1000) 25 988, Bit13 (967~989) 23 978,
2060 01:54:23.937186 TX Bit6 (977~1001) 25 989, Bit14 (968~991) 24 979,
2061 01:54:23.943574 TX Bit7 (978~1003) 26 990, Bit15 (972~994) 23 983,
2062 01:54:23.944049
2063 01:54:23.944415
2064 01:54:23.946701 TX Vref found, early break! 364< 371
2065 01:54:23.950214 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =753/100 ps
2066 01:54:23.953500 u1DelayCellOfst[0]=9 cells (7 PI)
2067 01:54:23.956645 u1DelayCellOfst[1]=6 cells (5 PI)
2068 01:54:23.960394 u1DelayCellOfst[2]=7 cells (6 PI)
2069 01:54:23.964231 u1DelayCellOfst[3]=0 cells (0 PI)
2070 01:54:23.967514 u1DelayCellOfst[4]=5 cells (4 PI)
2071 01:54:23.970303 u1DelayCellOfst[5]=2 cells (2 PI)
2072 01:54:23.970713 u1DelayCellOfst[6]=3 cells (3 PI)
2073 01:54:23.973649 u1DelayCellOfst[7]=5 cells (4 PI)
2074 01:54:23.976996 Byte0, DQ PI dly=986, DQM PI dly= 989
2075 01:54:23.983610 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 26)
2076 01:54:23.984034
2077 01:54:23.986978 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 26)
2078 01:54:23.987378
2079 01:54:23.990199 u1DelayCellOfst[8]=0 cells (0 PI)
2080 01:54:23.993655 u1DelayCellOfst[9]=2 cells (2 PI)
2081 01:54:23.996997 u1DelayCellOfst[10]=10 cells (8 PI)
2082 01:54:24.000021 u1DelayCellOfst[11]=1 cells (1 PI)
2083 01:54:24.003358 u1DelayCellOfst[12]=2 cells (2 PI)
2084 01:54:24.006810 u1DelayCellOfst[13]=2 cells (2 PI)
2085 01:54:24.009394 u1DelayCellOfst[14]=3 cells (3 PI)
2086 01:54:24.012641 u1DelayCellOfst[15]=9 cells (7 PI)
2087 01:54:24.015925 Byte1, DQ PI dly=976, DQM PI dly= 980
2088 01:54:24.019854 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 16)
2089 01:54:24.019985
2090 01:54:24.022541 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 16)
2091 01:54:24.022680
2092 01:54:24.025827 Write Rank1 MR14 =0x1c
2093 01:54:24.025919
2094 01:54:24.029162 Final TX Range 0 Vref 28
2095 01:54:24.029248
2096 01:54:24.036556 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
2097 01:54:24.036706
2098 01:54:24.042906 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
2099 01:54:24.049372 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2100 01:54:24.056651 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2101 01:54:24.058861 Write Rank1 MR3 =0xb0
2102 01:54:24.058988 DramC Write-DBI on
2103 01:54:24.059071 ==
2104 01:54:24.065635 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2105 01:54:24.069115 fsp= 1, odt_onoff= 1, Byte mode= 0
2106 01:54:24.069289 ==
2107 01:54:24.072571 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
2108 01:54:24.072733
2109 01:54:24.076376 Begin, DQ Scan Range 700~764
2110 01:54:24.076567
2111 01:54:24.076673
2112 01:54:24.078987 TX Vref Scan disable
2113 01:54:24.083009 700 |2 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
2114 01:54:24.085707 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
2115 01:54:24.088867 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
2116 01:54:24.092093 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
2117 01:54:24.095638 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
2118 01:54:24.099173 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
2119 01:54:24.102595 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
2120 01:54:24.106086 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
2121 01:54:24.109349 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
2122 01:54:24.112993 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
2123 01:54:24.116177 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
2124 01:54:24.119424 711 |2 6 7|[0] xxxxxxxx oooooooo [MSB]
2125 01:54:24.122177 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
2126 01:54:24.125502 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
2127 01:54:24.128737 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
2128 01:54:24.135014 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
2129 01:54:24.138773 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
2130 01:54:24.141732 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB]
2131 01:54:24.144930 718 |2 6 14|[0] xxxxxxxx oooooooo [MSB]
2132 01:54:24.148210 719 |2 6 15|[0] xxxxxxxx oooooooo [MSB]
2133 01:54:24.152043 720 |2 6 16|[0] xxxxxxxx oooooooo [MSB]
2134 01:54:24.155433 721 |2 6 17|[0] xxxxxxxx oooooooo [MSB]
2135 01:54:24.161869 735 |2 6 31|[0] oooooooo xxxxxxxx [MSB]
2136 01:54:24.165635 736 |2 6 32|[0] oooooooo xxxxxxxx [MSB]
2137 01:54:24.168840 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
2138 01:54:24.171817 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
2139 01:54:24.175404 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
2140 01:54:24.178519 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
2141 01:54:24.182099 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
2142 01:54:24.185382 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
2143 01:54:24.188406 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
2144 01:54:24.191672 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB]
2145 01:54:24.195357 745 |2 6 41|[0] oooooooo xxxxxxxx [MSB]
2146 01:54:24.198451 746 |2 6 42|[0] oooooooo xxxxxxxx [MSB]
2147 01:54:24.201839 747 |2 6 43|[0] oooooooo xxxxxxxx [MSB]
2148 01:54:24.208069 748 |2 6 44|[0] xxxxxxxx xxxxxxxx [MSB]
2149 01:54:24.211735 Byte0, DQ PI dly=734, DQM PI dly= 734
2150 01:54:24.214405 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 30)
2151 01:54:24.214846
2152 01:54:24.218079 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 30)
2153 01:54:24.218521
2154 01:54:24.221536 Byte1, DQ PI dly=722, DQM PI dly= 722
2155 01:54:24.227682 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 18)
2156 01:54:24.228195
2157 01:54:24.231211 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 18)
2158 01:54:24.231650
2159 01:54:24.238263 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
2160 01:54:24.245005 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2161 01:54:24.251454 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2162 01:54:24.255281 Write Rank1 MR3 =0x30
2163 01:54:24.255807 DramC Write-DBI off
2164 01:54:24.256148
2165 01:54:24.256459 [DATLAT]
2166 01:54:24.258251 Freq=1600, CH0 RK1, use_rxtx_scan=0
2167 01:54:24.258688
2168 01:54:24.261514 DATLAT Default: 0x10
2169 01:54:24.264764 7, 0xFFFF, sum=0
2170 01:54:24.265206 8, 0xFFFF, sum=0
2171 01:54:24.265627 9, 0xFFFF, sum=0
2172 01:54:24.268185 10, 0xFFFF, sum=0
2173 01:54:24.268706 11, 0xFFFF, sum=0
2174 01:54:24.271640 12, 0xFFFF, sum=0
2175 01:54:24.272160 13, 0xFFFF, sum=0
2176 01:54:24.274647 14, 0x0, sum=1
2177 01:54:24.275093 15, 0x0, sum=2
2178 01:54:24.277880 16, 0x0, sum=3
2179 01:54:24.278321 17, 0x0, sum=4
2180 01:54:24.281234 pattern=2 first_step=14 total pass=5 best_step=16
2181 01:54:24.285039 ==
2182 01:54:24.288169 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2183 01:54:24.291247 fsp= 1, odt_onoff= 1, Byte mode= 0
2184 01:54:24.291733 ==
2185 01:54:24.294966 Start DQ dly to find pass range UseTestEngine =1
2186 01:54:24.298131 x-axis: bit #, y-axis: DQ dly (-127~63)
2187 01:54:24.301388 RX Vref Scan = 0
2188 01:54:24.305058 -26, [0] xxxxxxxx xxxxxxxx [MSB]
2189 01:54:24.308207 -25, [0] xxxxxxxx xxxxxxxx [MSB]
2190 01:54:24.311599 -24, [0] xxxxxxxx xxxxxxxx [MSB]
2191 01:54:24.312115 -23, [0] xxxxxxxx xxxxxxxx [MSB]
2192 01:54:24.314396 -22, [0] xxxxxxxx xxxxxxxx [MSB]
2193 01:54:24.317925 -21, [0] xxxxxxxx xxxxxxxx [MSB]
2194 01:54:24.321125 -20, [0] xxxxxxxx xxxxxxxx [MSB]
2195 01:54:24.324338 -19, [0] xxxxxxxx xxxxxxxx [MSB]
2196 01:54:24.327404 -18, [0] xxxxxxxx xxxxxxxx [MSB]
2197 01:54:24.331093 -17, [0] xxxxxxxx xxxxxxxx [MSB]
2198 01:54:24.334635 -16, [0] xxxxxxxx xxxxxxxx [MSB]
2199 01:54:24.337241 -15, [0] xxxxxxxx xxxxxxxx [MSB]
2200 01:54:24.337796 -14, [0] xxxxxxxx xxxxxxxx [MSB]
2201 01:54:24.341401 -13, [0] xxxxxxxx xxxxxxxx [MSB]
2202 01:54:24.345805 -12, [0] xxxxxxxx xxxxxxxx [MSB]
2203 01:54:24.347672 -11, [0] xxxxxxxx xxxxxxxx [MSB]
2204 01:54:24.351931 -10, [0] xxxxxxxx xxxxxxxx [MSB]
2205 01:54:24.355163 -9, [0] xxxxxxxx xxxxxxxx [MSB]
2206 01:54:24.357665 -8, [0] xxxxxxxx xxxxxxxx [MSB]
2207 01:54:24.360226 -7, [0] xxxxxxxx xxxxxxxx [MSB]
2208 01:54:24.360664 -6, [0] xxxxxxxx xxxxxxxx [MSB]
2209 01:54:24.363685 -5, [0] xxxxxxxx xxxxxxxx [MSB]
2210 01:54:24.367188 -4, [0] xxxxxxxx xxxxxxxx [MSB]
2211 01:54:24.371088 -3, [0] xxxoxxxx xxxxxxxx [MSB]
2212 01:54:24.374204 -2, [0] xxxoxxxx xxxxxxxx [MSB]
2213 01:54:24.377011 -1, [0] xxxoxxxx xxxxxxxx [MSB]
2214 01:54:24.380194 0, [0] xxxoxoxx oxxoxxxx [MSB]
2215 01:54:24.380712 1, [0] xxxoxoox oxxoxxxx [MSB]
2216 01:54:24.383273 2, [0] xoxoxoox ooxoxxxx [MSB]
2217 01:54:24.386403 3, [0] xoxoxoox ooxoooxx [MSB]
2218 01:54:24.390068 4, [0] ooooxooo ooxoooxx [MSB]
2219 01:54:24.393471 5, [0] oooooooo ooxoooox [MSB]
2220 01:54:24.396940 6, [0] oooooooo ooxooooo [MSB]
2221 01:54:24.397377 7, [0] oooooooo ooxooooo [MSB]
2222 01:54:24.400129 8, [0] oooooooo ooxooooo [MSB]
2223 01:54:24.404886 32, [0] oooxoooo oooooooo [MSB]
2224 01:54:24.408318 33, [0] oooxoxoo oooooooo [MSB]
2225 01:54:24.411653 34, [0] oooxoxoo xooxoooo [MSB]
2226 01:54:24.414757 35, [0] oooxoxoo xooxoooo [MSB]
2227 01:54:24.417936 36, [0] oooxoxxo xxoxoooo [MSB]
2228 01:54:24.421100 37, [0] oooxoxxx xxoxxxoo [MSB]
2229 01:54:24.424607 38, [0] oooxoxxx xxoxxxxo [MSB]
2230 01:54:24.425128 39, [0] xooxxxxx xxoxxxxo [MSB]
2231 01:54:24.427886 40, [0] xxoxxxxx xxoxxxxo [MSB]
2232 01:54:24.430969 41, [0] xxxxxxxx xxoxxxxx [MSB]
2233 01:54:24.434140 42, [0] xxxxxxxx xxoxxxxx [MSB]
2234 01:54:24.437629 43, [0] xxxxxxxx xxxxxxxx [MSB]
2235 01:54:24.440839 iDelay=43, Bit 0, Center 21 (4 ~ 38) 35
2236 01:54:24.444111 iDelay=43, Bit 1, Center 20 (2 ~ 39) 38
2237 01:54:24.447156 iDelay=43, Bit 2, Center 22 (4 ~ 40) 37
2238 01:54:24.450594 iDelay=43, Bit 3, Center 14 (-3 ~ 31) 35
2239 01:54:24.453950 iDelay=43, Bit 4, Center 21 (5 ~ 38) 34
2240 01:54:24.457364 iDelay=43, Bit 5, Center 16 (0 ~ 32) 33
2241 01:54:24.460711 iDelay=43, Bit 6, Center 18 (1 ~ 35) 35
2242 01:54:24.466938 iDelay=43, Bit 7, Center 20 (4 ~ 36) 33
2243 01:54:24.470332 iDelay=43, Bit 8, Center 16 (0 ~ 33) 34
2244 01:54:24.474028 iDelay=43, Bit 9, Center 18 (2 ~ 35) 34
2245 01:54:24.477036 iDelay=43, Bit 10, Center 25 (9 ~ 42) 34
2246 01:54:24.480242 iDelay=43, Bit 11, Center 16 (0 ~ 33) 34
2247 01:54:24.483308 iDelay=43, Bit 12, Center 19 (3 ~ 36) 34
2248 01:54:24.486834 iDelay=43, Bit 13, Center 19 (3 ~ 36) 34
2249 01:54:24.490038 iDelay=43, Bit 14, Center 21 (5 ~ 37) 33
2250 01:54:24.493616 iDelay=43, Bit 15, Center 23 (6 ~ 40) 35
2251 01:54:24.494068 ==
2252 01:54:24.500180 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2253 01:54:24.503291 fsp= 1, odt_onoff= 1, Byte mode= 0
2254 01:54:24.503813 ==
2255 01:54:24.504257 DQS Delay:
2256 01:54:24.506704 DQS0 = 0, DQS1 = 0
2257 01:54:24.507148 DQM Delay:
2258 01:54:24.509530 DQM0 = 19, DQM1 = 19
2259 01:54:24.510009 DQ Delay:
2260 01:54:24.513025 DQ0 =21, DQ1 =20, DQ2 =22, DQ3 =14
2261 01:54:24.516758 DQ4 =21, DQ5 =16, DQ6 =18, DQ7 =20
2262 01:54:24.519440 DQ8 =16, DQ9 =18, DQ10 =25, DQ11 =16
2263 01:54:24.522839 DQ12 =19, DQ13 =19, DQ14 =21, DQ15 =23
2264 01:54:24.523281
2265 01:54:24.523713
2266 01:54:24.524120
2267 01:54:24.526163 [DramC_TX_OE_Calibration] TA2
2268 01:54:24.529294 Original DQ_B0 (3 6) =30, OEN = 27
2269 01:54:24.533102 Original DQ_B1 (3 6) =30, OEN = 27
2270 01:54:24.536053 23, 0x0, End_B0=23 End_B1=23
2271 01:54:24.536506 24, 0x0, End_B0=24 End_B1=24
2272 01:54:24.539591 25, 0x0, End_B0=25 End_B1=25
2273 01:54:24.542720 26, 0x0, End_B0=26 End_B1=26
2274 01:54:24.546160 27, 0x0, End_B0=27 End_B1=27
2275 01:54:24.546612 28, 0x0, End_B0=28 End_B1=28
2276 01:54:24.549447 29, 0x0, End_B0=29 End_B1=29
2277 01:54:24.552676 30, 0x0, End_B0=30 End_B1=30
2278 01:54:24.555941 31, 0xFFFF, End_B0=30 End_B1=30
2279 01:54:24.562348 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
2280 01:54:24.565899 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
2281 01:54:24.566420
2282 01:54:24.566857
2283 01:54:24.568846 Write Rank1 MR23 =0x3f
2284 01:54:24.569305 [DQSOSC]
2285 01:54:24.579046 [DQSOSCAuto] RK1, (LSB)MR18= 0xaeae, (MSB)MR19= 0x202, tDQSOscB0 = 459 ps tDQSOscB1 = 459 ps
2286 01:54:24.582594 CH0_RK1: MR19=0x202, MR18=0xAEAE, DQSOSC=459, MR23=63, INC=11, DEC=17
2287 01:54:24.585475 Write Rank1 MR23 =0x3f
2288 01:54:24.585957 [DQSOSC]
2289 01:54:24.595552 [DQSOSCAuto] RK1, (LSB)MR18= 0xb0b0, (MSB)MR19= 0x202, tDQSOscB0 = 457 ps tDQSOscB1 = 457 ps
2290 01:54:24.598956 CH0 RK1: MR19=202, MR18=B0B0
2291 01:54:24.602015 [RxdqsGatingPostProcess] freq 1600
2292 01:54:24.605590 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
2293 01:54:24.608819 Rank: 0
2294 01:54:24.609327 best DQS0 dly(2T, 0.5T) = (2, 6)
2295 01:54:24.612128 best DQS1 dly(2T, 0.5T) = (2, 6)
2296 01:54:24.615531 best DQS0 P1 dly(2T, 0.5T) = (3, 2)
2297 01:54:24.618433 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
2298 01:54:24.618861 Rank: 1
2299 01:54:24.621496 best DQS0 dly(2T, 0.5T) = (2, 6)
2300 01:54:24.625256 best DQS1 dly(2T, 0.5T) = (2, 6)
2301 01:54:24.628817 best DQS0 P1 dly(2T, 0.5T) = (3, 2)
2302 01:54:24.631967 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
2303 01:54:24.638048 TX_dly_DQSgated check: min 2 max 3, ChangeDQSINCTL=-1
2304 01:54:24.641306 DQSINCTL=5, RANKINCTL=3, u4XRTR2R=9
2305 01:54:24.644896 [DualRankRxdatlatCal] RK0: 16, RK1: 16, Final_Datlat 16
2306 01:54:24.647992 Write Rank0 MR13 =0x59
2307 01:54:24.648423 ==
2308 01:54:24.651754 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2309 01:54:24.654855 fsp= 1, odt_onoff= 1, Byte mode= 0
2310 01:54:24.655390 ==
2311 01:54:24.657672 === u2Vref_new: 0x56 --> 0x3a
2312 01:54:24.661173 === u2Vref_new: 0x58 --> 0x58
2313 01:54:24.664651 === u2Vref_new: 0x5a --> 0x5a
2314 01:54:24.667530 === u2Vref_new: 0x5c --> 0x78
2315 01:54:24.670941 === u2Vref_new: 0x5e --> 0x7a
2316 01:54:24.674318 === u2Vref_new: 0x60 --> 0x90
2317 01:54:24.677491 [CA 0] Center 37 (11~63) winsize 53
2318 01:54:24.680736 [CA 1] Center 36 (10~63) winsize 54
2319 01:54:24.683901 [CA 2] Center 35 (7~63) winsize 57
2320 01:54:24.687199 [CA 3] Center 35 (7~63) winsize 57
2321 01:54:24.690535 [CA 4] Center 34 (6~63) winsize 58
2322 01:54:24.693565 [CA 5] Center 28 (0~57) winsize 58
2323 01:54:24.693782
2324 01:54:24.696888 [CATrainingPosCal] consider 1 rank data
2325 01:54:24.700252 u2DelayCellTimex100 = 753/100 ps
2326 01:54:24.703513 CA0 delay=37 (11~63),Diff = 9 PI (11 cell)
2327 01:54:24.706908 CA1 delay=36 (10~63),Diff = 8 PI (10 cell)
2328 01:54:24.710596 CA2 delay=35 (7~63),Diff = 7 PI (9 cell)
2329 01:54:24.713929 CA3 delay=35 (7~63),Diff = 7 PI (9 cell)
2330 01:54:24.717286 CA4 delay=34 (6~63),Diff = 6 PI (7 cell)
2331 01:54:24.723953 CA5 delay=28 (0~57),Diff = 0 PI (0 cell)
2332 01:54:24.724358
2333 01:54:24.727195 CA PerBit enable=1, Macro0, CA PI delay=28
2334 01:54:24.730325 === u2Vref_new: 0x60 --> 0x90
2335 01:54:24.730775
2336 01:54:24.731103 Vref(ca) range 1: 32
2337 01:54:24.731407
2338 01:54:24.733339 CS Dly= 11 (42-0-32)
2339 01:54:24.733813 Write Rank0 MR13 =0xd8
2340 01:54:24.736928 Write Rank0 MR13 =0xd8
2341 01:54:24.740408 Write Rank0 MR12 =0x60
2342 01:54:24.740910 Write Rank1 MR13 =0x59
2343 01:54:24.741236 ==
2344 01:54:24.746895 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
2345 01:54:24.750415 fsp= 1, odt_onoff= 1, Byte mode= 0
2346 01:54:24.750918 ==
2347 01:54:24.753670 === u2Vref_new: 0x56 --> 0x3a
2348 01:54:24.757204 === u2Vref_new: 0x58 --> 0x58
2349 01:54:24.760590 === u2Vref_new: 0x5a --> 0x5a
2350 01:54:24.763546 === u2Vref_new: 0x5c --> 0x78
2351 01:54:24.766281 === u2Vref_new: 0x5e --> 0x7a
2352 01:54:24.766794 === u2Vref_new: 0x60 --> 0x90
2353 01:54:24.770078 [CA 0] Center 37 (11~63) winsize 53
2354 01:54:24.773130 [CA 1] Center 37 (11~63) winsize 53
2355 01:54:24.776564 [CA 2] Center 35 (7~63) winsize 57
2356 01:54:24.779809 [CA 3] Center 34 (6~63) winsize 58
2357 01:54:24.783208 [CA 4] Center 34 (6~63) winsize 58
2358 01:54:24.786744 [CA 5] Center 28 (-1~57) winsize 59
2359 01:54:24.787258
2360 01:54:24.790756 [CATrainingPosCal] consider 2 rank data
2361 01:54:24.792990 u2DelayCellTimex100 = 753/100 ps
2362 01:54:24.796689 CA0 delay=37 (11~63),Diff = 9 PI (11 cell)
2363 01:54:24.799572 CA1 delay=37 (11~63),Diff = 9 PI (11 cell)
2364 01:54:24.806038 CA2 delay=35 (7~63),Diff = 7 PI (9 cell)
2365 01:54:24.809325 CA3 delay=35 (7~63),Diff = 7 PI (9 cell)
2366 01:54:24.813032 CA4 delay=34 (6~63),Diff = 6 PI (7 cell)
2367 01:54:24.816782 CA5 delay=28 (0~57),Diff = 0 PI (0 cell)
2368 01:54:24.817326
2369 01:54:24.820012 CA PerBit enable=1, Macro0, CA PI delay=28
2370 01:54:24.822713 === u2Vref_new: 0x5c --> 0x78
2371 01:54:24.823138
2372 01:54:24.825725 Vref(ca) range 1: 28
2373 01:54:24.826150
2374 01:54:24.826478 CS Dly= 9 (40-0-32)
2375 01:54:24.829229 Write Rank1 MR13 =0xd8
2376 01:54:24.829917 Write Rank1 MR13 =0xd8
2377 01:54:24.832435 Write Rank1 MR12 =0x5c
2378 01:54:24.836154 [RankSwap] Rank num 2, (Multi 1), Rank 0
2379 01:54:24.838971 Write Rank0 MR2 =0xad
2380 01:54:24.839688 [Write Leveling]
2381 01:54:24.842642 delay byte0 byte1 byte2 byte3
2382 01:54:24.843211
2383 01:54:24.845261 10 0 0
2384 01:54:24.845816 11 0 0
2385 01:54:24.846213 12 0 0
2386 01:54:24.848684 13 0 0
2387 01:54:24.849226 14 0 0
2388 01:54:24.851973 15 0 0
2389 01:54:24.852484 16 0 0
2390 01:54:24.855164 17 0 0
2391 01:54:24.855697 18 0 0
2392 01:54:24.856085 19 0 0
2393 01:54:24.858568 20 0 0
2394 01:54:24.859126 21 0 0
2395 01:54:24.861908 22 0 0
2396 01:54:24.862389 23 0 0
2397 01:54:24.862812 24 0 0
2398 01:54:24.865106 25 0 0
2399 01:54:24.865635 26 0 0
2400 01:54:24.868283 27 0 0
2401 01:54:24.868663 28 0 0
2402 01:54:24.871656 29 0 0
2403 01:54:24.871930 30 0 0
2404 01:54:24.872144 31 0 0
2405 01:54:24.874824 32 0 0
2406 01:54:24.875119 33 0 ff
2407 01:54:24.878820 34 0 ff
2408 01:54:24.879213 35 ff ff
2409 01:54:24.881421 36 ff ff
2410 01:54:24.881840 37 ff ff
2411 01:54:24.885313 38 ff ff
2412 01:54:24.885737 39 ff ff
2413 01:54:24.888620 40 ff ff
2414 01:54:24.889019 41 ff ff
2415 01:54:24.891896 pass bytecount = 0xff (0xff: all bytes pass)
2416 01:54:24.892411
2417 01:54:24.895136 DQS0 dly: 35
2418 01:54:24.895708 DQS1 dly: 33
2419 01:54:24.898497 Write Rank0 MR2 =0x2d
2420 01:54:24.901856 [RankSwap] Rank num 2, (Multi 1), Rank 0
2421 01:54:24.902268 Write Rank0 MR1 =0xd6
2422 01:54:24.905253 [Gating]
2423 01:54:24.905688 ==
2424 01:54:24.907978 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2425 01:54:24.911048 fsp= 1, odt_onoff= 1, Byte mode= 0
2426 01:54:24.911538 ==
2427 01:54:24.918056 3 1 0 |2c2b 302 |(11 11)(11 11) |(1 1)(1 1)| 0
2428 01:54:24.921454 3 1 4 |2c2b 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2429 01:54:24.924382 3 1 8 |2c2b 3535 |(11 11)(11 11) |(1 1)(1 1)| 0
2430 01:54:24.928128 3 1 12 |2c2b 3535 |(11 11)(11 11) |(1 1)(0 0)| 0
2431 01:54:24.934429 3 1 16 |2c2b 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2432 01:54:24.937686 [Byte 0] Lead/lag falling Transition (3, 1, 16)
2433 01:54:24.941084 3 1 20 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 0)| 0
2434 01:54:24.948923 3 1 24 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 0)| 0
2435 01:54:24.951509 3 1 28 |2c2b 3534 |(11 11)(11 11) |(1 0)(1 1)| 0
2436 01:54:24.954356 3 2 0 |2c2b 606 |(11 11)(11 11) |(1 0)(1 1)| 0
2437 01:54:24.960439 3 2 4 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 0)| 0
2438 01:54:24.964179 3 2 8 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 0)| 0
2439 01:54:24.967595 3 2 12 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 0)| 0
2440 01:54:24.973639 3 2 16 |2c2b 3433 |(11 11)(11 11) |(1 0)(0 0)| 0
2441 01:54:24.977082 3 2 20 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 0)| 0
2442 01:54:24.980189 3 2 24 |404 3434 |(11 11)(11 11) |(1 0)(0 0)| 0
2443 01:54:24.986936 [Byte 0] Lead/lag Transition tap number (11)
2444 01:54:24.990174 3 2 28 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
2445 01:54:24.993705 3 3 0 |3534 505 |(11 11)(11 11) |(0 0)(1 1)| 0
2446 01:54:25.000448 3 3 4 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
2447 01:54:25.003448 3 3 8 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
2448 01:54:25.006979 3 3 12 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
2449 01:54:25.013457 3 3 16 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
2450 01:54:25.016946 3 3 20 |3534 908 |(11 11)(11 11) |(0 0)(1 1)| 0
2451 01:54:25.020084 [Byte 1] Lead/lag Transition tap number (1)
2452 01:54:25.023102 3 3 24 |3534 3d3c |(11 11)(11 11) |(1 1)(0 0)| 0
2453 01:54:25.029910 3 3 28 |3534 3c3c |(11 11)(10 10) |(1 1)(1 1)| 0
2454 01:54:25.033220 3 4 0 |3534 808 |(11 11)(11 11) |(0 0)(1 1)| 0
2455 01:54:25.036293 3 4 4 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
2456 01:54:25.043377 3 4 8 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
2457 01:54:25.046217 3 4 12 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
2458 01:54:25.049455 3 4 16 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
2459 01:54:25.056368 3 4 20 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
2460 01:54:25.059696 3 4 24 |807 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2461 01:54:25.062798 3 4 28 |3d3d 807 |(11 11)(11 11) |(1 1)(0 1)| 0
2462 01:54:25.069412 3 5 0 |3d3d 403 |(11 11)(11 11) |(1 1)(1 1)| 0
2463 01:54:25.072547 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2464 01:54:25.075964 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2465 01:54:25.082681 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2466 01:54:25.085356 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2467 01:54:25.088768 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2468 01:54:25.095560 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2469 01:54:25.099419 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2470 01:54:25.102059 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2471 01:54:25.108939 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2472 01:54:25.112222 3 6 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2473 01:54:25.115031 3 6 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2474 01:54:25.121017 3 6 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2475 01:54:25.124442 [Byte 0] Lead/lag falling Transition (3, 6, 16)
2476 01:54:25.127976 3 6 20 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
2477 01:54:25.130948 3 6 24 |202 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
2478 01:54:25.138043 [Byte 0] Lead/lag Transition tap number (3)
2479 01:54:25.140648 [Byte 1] Lead/lag Transition tap number (1)
2480 01:54:25.144587 3 6 28 |3232 202 |(11 11)(11 11) |(0 0)(0 0)| 0
2481 01:54:25.147326 3 7 0 |4646 403 |(0 0)(11 11) |(0 0)(0 0)| 0
2482 01:54:25.150708 [Byte 0]First pass (3, 7, 0)
2483 01:54:25.153952 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2484 01:54:25.157651 [Byte 1]First pass (3, 7, 4)
2485 01:54:25.160590 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2486 01:54:25.167061 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2487 01:54:25.170297 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2488 01:54:25.173540 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2489 01:54:25.176993 3 7 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2490 01:54:25.183813 3 7 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2491 01:54:25.186897 4 0 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2492 01:54:25.190159 4 0 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2493 01:54:25.193361 All bytes gating window > 1UI, Early break!
2494 01:54:25.193862
2495 01:54:25.196379 best DQS0 dly(2T, 0.5T, PI) = (3, 6, 22)
2496 01:54:25.196788
2497 01:54:25.199932 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 26)
2498 01:54:25.203360
2499 01:54:25.203753
2500 01:54:25.204076
2501 01:54:25.206577 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 22)
2502 01:54:25.206960
2503 01:54:25.210061 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 26)
2504 01:54:25.210457
2505 01:54:25.210755
2506 01:54:25.213054 Write Rank0 MR1 =0x56
2507 01:54:25.213460
2508 01:54:25.216190 best RODT dly(2T, 0.5T) = (2, 3)
2509 01:54:25.216770
2510 01:54:25.220303 best RODT dly(2T, 0.5T) = (2, 3)
2511 01:54:25.220761 ==
2512 01:54:25.223437 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2513 01:54:25.226382 fsp= 1, odt_onoff= 1, Byte mode= 0
2514 01:54:25.226771 ==
2515 01:54:25.233039 Start DQ dly to find pass range UseTestEngine =0
2516 01:54:25.236120 x-axis: bit #, y-axis: DQ dly (-127~63)
2517 01:54:25.236512 RX Vref Scan = 0
2518 01:54:25.239033 -26, [0] xxxxxxxx xxxxxxxx [MSB]
2519 01:54:25.242434 -25, [0] xxxxxxxx xxxxxxxx [MSB]
2520 01:54:25.245713 -24, [0] xxxxxxxx xxxxxxxx [MSB]
2521 01:54:25.248944 -23, [0] xxxxxxxx xxxxxxxx [MSB]
2522 01:54:25.252174 -22, [0] xxxxxxxx xxxxxxxx [MSB]
2523 01:54:25.255510 -21, [0] xxxxxxxx xxxxxxxx [MSB]
2524 01:54:25.255914 -20, [0] xxxxxxxx xxxxxxxx [MSB]
2525 01:54:25.258877 -19, [0] xxxxxxxx xxxxxxxx [MSB]
2526 01:54:25.262297 -18, [0] xxxxxxxx xxxxxxxx [MSB]
2527 01:54:25.265462 -17, [0] xxxxxxxx xxxxxxxx [MSB]
2528 01:54:25.268937 -16, [0] xxxxxxxx xxxxxxxx [MSB]
2529 01:54:25.271857 -15, [0] xxxxxxxx xxxxxxxx [MSB]
2530 01:54:25.275594 -14, [0] xxxxxxxx xxxxxxxx [MSB]
2531 01:54:25.278318 -13, [0] xxxxxxxx xxxxxxxx [MSB]
2532 01:54:25.282039 -12, [0] xxxxxxxx xxxxxxxx [MSB]
2533 01:54:25.285344 -11, [0] xxxxxxxx xxxxxxxx [MSB]
2534 01:54:25.285794 -10, [0] xxxxxxxx xxxxxxxx [MSB]
2535 01:54:25.288126 -9, [0] xxxxxxxx xxxxxxxx [MSB]
2536 01:54:25.291414 -8, [0] xxxxxxxx xxxxxxxx [MSB]
2537 01:54:25.295071 -7, [0] xxxxxxxx xxxxxxxx [MSB]
2538 01:54:25.298355 -6, [0] xxxxxxxx xxxxxxxx [MSB]
2539 01:54:25.301271 -5, [0] xxxxxxxx xxxxxxxx [MSB]
2540 01:54:25.304640 -4, [0] xxxxxxxx xxxxxxxo [MSB]
2541 01:54:25.305034 -3, [0] xxxxxxxx xxxxxxxo [MSB]
2542 01:54:25.307733 -2, [0] xxxxxxxx xxxxxxxo [MSB]
2543 01:54:25.311577 -1, [0] xxxxxxxx xxxxxxxo [MSB]
2544 01:54:25.314850 0, [0] xxxxxxxx xoxxxxxo [MSB]
2545 01:54:25.317615 1, [0] xxxxxxxx ooxxxxxo [MSB]
2546 01:54:25.321479 2, [0] xxxoxxxx ooxxxxxo [MSB]
2547 01:54:25.324706 3, [0] xoooxxxx oooxxxxo [MSB]
2548 01:54:25.325102 4, [0] xoooxxxo ooooxxxo [MSB]
2549 01:54:25.327322 5, [0] xooooxxo oooooooo [MSB]
2550 01:54:25.330871 6, [0] xooooxxo oooooooo [MSB]
2551 01:54:25.334160 7, [0] xooooooo oooooooo [MSB]
2552 01:54:25.337512 32, [0] oooooooo ooooooox [MSB]
2553 01:54:25.340499 33, [0] oooxoooo ooooooox [MSB]
2554 01:54:25.344504 34, [0] oooxoooo ooooooox [MSB]
2555 01:54:25.344922 35, [0] oooxoooo xoooooox [MSB]
2556 01:54:25.347235 36, [0] ooxxoooo xxooooox [MSB]
2557 01:54:25.350846 37, [0] ooxxoooo xxooooox [MSB]
2558 01:54:25.353845 38, [0] ooxxooox xxooooox [MSB]
2559 01:54:25.357400 39, [0] xxxxxoox xxooxoox [MSB]
2560 01:54:25.360736 40, [0] xxxxxoox xxxoxoox [MSB]
2561 01:54:25.363698 41, [0] xxxxxxxx xxxxxxxx [MSB]
2562 01:54:25.366619 iDelay=41, Bit 0, Center 23 (8 ~ 38) 31
2563 01:54:25.370126 iDelay=41, Bit 1, Center 20 (3 ~ 38) 36
2564 01:54:25.373258 iDelay=41, Bit 2, Center 19 (3 ~ 35) 33
2565 01:54:25.376543 iDelay=41, Bit 3, Center 17 (2 ~ 32) 31
2566 01:54:25.380342 iDelay=41, Bit 4, Center 21 (5 ~ 38) 34
2567 01:54:25.383583 iDelay=41, Bit 5, Center 23 (7 ~ 40) 34
2568 01:54:25.386267 iDelay=41, Bit 6, Center 23 (7 ~ 40) 34
2569 01:54:25.390223 iDelay=41, Bit 7, Center 20 (4 ~ 37) 34
2570 01:54:25.393235 iDelay=41, Bit 8, Center 17 (1 ~ 34) 34
2571 01:54:25.396414 iDelay=41, Bit 9, Center 17 (0 ~ 35) 36
2572 01:54:25.402844 iDelay=41, Bit 10, Center 21 (3 ~ 39) 37
2573 01:54:25.406438 iDelay=41, Bit 11, Center 22 (4 ~ 40) 37
2574 01:54:25.409379 iDelay=41, Bit 12, Center 21 (5 ~ 38) 34
2575 01:54:25.413097 iDelay=41, Bit 13, Center 22 (5 ~ 40) 36
2576 01:54:25.416350 iDelay=41, Bit 14, Center 22 (5 ~ 40) 36
2577 01:54:25.419579 iDelay=41, Bit 15, Center 13 (-4 ~ 31) 36
2578 01:54:25.419979 ==
2579 01:54:25.425828 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2580 01:54:25.429375 fsp= 1, odt_onoff= 1, Byte mode= 0
2581 01:54:25.429821 ==
2582 01:54:25.430239 DQS Delay:
2583 01:54:25.432583 DQS0 = 0, DQS1 = 0
2584 01:54:25.433012 DQM Delay:
2585 01:54:25.433407 DQM0 = 20, DQM1 = 19
2586 01:54:25.435854 DQ Delay:
2587 01:54:25.439287 DQ0 =23, DQ1 =20, DQ2 =19, DQ3 =17
2588 01:54:25.442631 DQ4 =21, DQ5 =23, DQ6 =23, DQ7 =20
2589 01:54:25.445984 DQ8 =17, DQ9 =17, DQ10 =21, DQ11 =22
2590 01:54:25.449427 DQ12 =21, DQ13 =22, DQ14 =22, DQ15 =13
2591 01:54:25.449859
2592 01:54:25.450162
2593 01:54:25.450444 DramC Write-DBI off
2594 01:54:25.450712 ==
2595 01:54:25.455250 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2596 01:54:25.458547 fsp= 1, odt_onoff= 1, Byte mode= 0
2597 01:54:25.458940 ==
2598 01:54:25.462521 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
2599 01:54:25.462996
2600 01:54:25.465640 Begin, DQ Scan Range 929~1185
2601 01:54:25.466053
2602 01:54:25.466359
2603 01:54:25.468803 TX Vref Scan disable
2604 01:54:25.472149 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
2605 01:54:25.475340 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
2606 01:54:25.478447 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
2607 01:54:25.481864 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
2608 01:54:25.484952 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
2609 01:54:25.488084 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
2610 01:54:25.491682 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
2611 01:54:25.497829 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
2612 01:54:25.501040 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
2613 01:54:25.504763 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
2614 01:54:25.508108 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
2615 01:54:25.511435 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
2616 01:54:25.514448 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
2617 01:54:25.517677 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
2618 01:54:25.520927 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
2619 01:54:25.524493 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
2620 01:54:25.527347 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
2621 01:54:25.530433 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
2622 01:54:25.534260 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
2623 01:54:25.537342 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
2624 01:54:25.543720 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
2625 01:54:25.547101 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
2626 01:54:25.550364 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
2627 01:54:25.553640 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
2628 01:54:25.556900 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
2629 01:54:25.560210 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
2630 01:54:25.563690 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
2631 01:54:25.566978 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
2632 01:54:25.570247 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
2633 01:54:25.573521 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
2634 01:54:25.576720 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
2635 01:54:25.580177 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
2636 01:54:25.583403 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
2637 01:54:25.586640 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
2638 01:54:25.593057 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
2639 01:54:25.596384 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
2640 01:54:25.599872 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
2641 01:54:25.602818 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
2642 01:54:25.606039 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
2643 01:54:25.609700 968 |3 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
2644 01:54:25.612908 969 |3 6 9|[0] xxxxxxxx xxxxxxxx [MSB]
2645 01:54:25.616251 970 |3 6 10|[0] xxxxxxxx xxxxxxxx [MSB]
2646 01:54:25.619495 971 |3 6 11|[0] xxxxxxxx xxxxxxxx [MSB]
2647 01:54:25.622671 972 |3 6 12|[0] xxxxxxxx xxxxxxxx [MSB]
2648 01:54:25.626560 973 |3 6 13|[0] xxxxxxxx xxxxxxxx [MSB]
2649 01:54:25.629444 974 |3 6 14|[0] xxxxxxxx xxxxxxxx [MSB]
2650 01:54:25.632244 975 |3 6 15|[0] xxxxxxxx xxxxxxxx [MSB]
2651 01:54:25.635669 976 |3 6 16|[0] xxxxxxxx xxxxxxxx [MSB]
2652 01:54:25.638856 977 |3 6 17|[0] xxxxxxxx xxxxxxxx [MSB]
2653 01:54:25.642771 978 |3 6 18|[0] xxxxxxxx xxxxxxxx [MSB]
2654 01:54:25.649225 979 |3 6 19|[0] xxxxxxxx xxxxxxxx [MSB]
2655 01:54:25.652716 980 |3 6 20|[0] xxxxxxxx oxxxxxxo [MSB]
2656 01:54:25.656116 981 |3 6 21|[0] xxxxxxxx ooxxxxxo [MSB]
2657 01:54:25.658828 982 |3 6 22|[0] xxxxxxxx ooxxxxxo [MSB]
2658 01:54:25.662378 983 |3 6 23|[0] xxxxxxxx ooxxxxxo [MSB]
2659 01:54:25.665458 984 |3 6 24|[0] xxxxxxxx oooxoxoo [MSB]
2660 01:54:25.669017 995 |3 6 35|[0] oooooooo ooooooox [MSB]
2661 01:54:25.675666 996 |3 6 36|[0] oooooooo ooooooox [MSB]
2662 01:54:25.678793 997 |3 6 37|[0] oooooooo ooooooox [MSB]
2663 01:54:25.682126 998 |3 6 38|[0] oooooooo ooooooox [MSB]
2664 01:54:25.685149 999 |3 6 39|[0] oooooooo oxooooox [MSB]
2665 01:54:25.688382 1000 |3 6 40|[0] oooooooo oxooooox [MSB]
2666 01:54:25.692156 1001 |3 6 41|[0] oooooooo xxxxxxxx [MSB]
2667 01:54:25.695222 1002 |3 6 42|[0] oooxoooo xxxxxxxx [MSB]
2668 01:54:25.698513 1003 |3 6 43|[0] oooxoooo xxxxxxxx [MSB]
2669 01:54:25.701502 1004 |3 6 44|[0] oooxoooo xxxxxxxx [MSB]
2670 01:54:25.704743 1005 |3 6 45|[0] ooxxoooo xxxxxxxx [MSB]
2671 01:54:25.711513 1006 |3 6 46|[0] ooxxooox xxxxxxxx [MSB]
2672 01:54:25.714562 1007 |3 6 47|[0] xxxxxxxx xxxxxxxx [MSB]
2673 01:54:25.717936 Byte0, DQ PI dly=994, DQM PI dly= 994
2674 01:54:25.721275 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 34)
2675 01:54:25.721867
2676 01:54:25.724623 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 34)
2677 01:54:25.725097
2678 01:54:25.727609 Byte1, DQ PI dly=989, DQM PI dly= 989
2679 01:54:25.734287 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 29)
2680 01:54:25.734754
2681 01:54:25.737396 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 29)
2682 01:54:25.737932
2683 01:54:25.738388 ==
2684 01:54:25.744472 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2685 01:54:25.747580 fsp= 1, odt_onoff= 1, Byte mode= 0
2686 01:54:25.747984 ==
2687 01:54:25.750725 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
2688 01:54:25.751128
2689 01:54:25.753919 Begin, DQ Scan Range 965~1029
2690 01:54:25.757006 Write Rank0 MR14 =0x0
2691 01:54:25.763117
2692 01:54:25.766375 CH=1, VrefRange= 0, VrefLevel = 0
2693 01:54:25.769720 TX Bit0 (986~1003) 18 994, Bit8 (984~994) 11 989,
2694 01:54:25.772875 TX Bit1 (985~1002) 18 993, Bit9 (984~993) 10 988,
2695 01:54:25.779475 TX Bit2 (984~998) 15 991, Bit10 (986~998) 13 992,
2696 01:54:25.782773 TX Bit3 (984~995) 12 989, Bit11 (987~997) 11 992,
2697 01:54:25.789281 TX Bit4 (986~1001) 16 993, Bit12 (986~997) 12 991,
2698 01:54:25.792482 TX Bit5 (986~1002) 17 994, Bit13 (987~997) 11 992,
2699 01:54:25.795845 TX Bit6 (986~1002) 17 994, Bit14 (986~994) 9 990,
2700 01:54:25.802408 TX Bit7 (986~1000) 15 993, Bit15 (981~989) 9 985,
2701 01:54:25.802796
2702 01:54:25.805610 wait MRW command Rank0 MR14 =0x2 fired (1)
2703 01:54:25.808782 Write Rank0 MR14 =0x2
2704 01:54:25.815986
2705 01:54:25.816369 CH=1, VrefRange= 0, VrefLevel = 2
2706 01:54:25.822663 TX Bit0 (986~1004) 19 995, Bit8 (983~994) 12 988,
2707 01:54:25.825883 TX Bit1 (985~1003) 19 994, Bit9 (984~994) 11 989,
2708 01:54:25.832291 TX Bit2 (984~999) 16 991, Bit10 (985~999) 15 992,
2709 01:54:25.835536 TX Bit3 (984~997) 14 990, Bit11 (987~998) 12 992,
2710 01:54:25.838811 TX Bit4 (985~1002) 18 993, Bit12 (986~998) 13 992,
2711 01:54:25.845243 TX Bit5 (986~1004) 19 995, Bit13 (987~998) 12 992,
2712 01:54:25.848193 TX Bit6 (985~1003) 19 994, Bit14 (986~995) 10 990,
2713 01:54:25.855383 TX Bit7 (985~1001) 17 993, Bit15 (981~991) 11 986,
2714 01:54:25.855772
2715 01:54:25.856072 Write Rank0 MR14 =0x4
2716 01:54:25.864647
2717 01:54:25.865031 CH=1, VrefRange= 0, VrefLevel = 4
2718 01:54:25.870941 TX Bit0 (986~1005) 20 995, Bit8 (984~995) 12 989,
2719 01:54:25.874507 TX Bit1 (985~1004) 20 994, Bit9 (984~994) 11 989,
2720 01:54:25.880597 TX Bit2 (984~999) 16 991, Bit10 (985~1000) 16 992,
2721 01:54:25.883880 TX Bit3 (983~997) 15 990, Bit11 (986~999) 14 992,
2722 01:54:25.887465 TX Bit4 (985~1003) 19 994, Bit12 (986~999) 14 992,
2723 01:54:25.894328 TX Bit5 (986~1004) 19 995, Bit13 (986~999) 14 992,
2724 01:54:25.897197 TX Bit6 (985~1004) 20 994, Bit14 (986~995) 10 990,
2725 01:54:25.904015 TX Bit7 (985~1001) 17 993, Bit15 (980~992) 13 986,
2726 01:54:25.904418
2727 01:54:25.904814 Write Rank0 MR14 =0x6
2728 01:54:25.912994
2729 01:54:25.913394 CH=1, VrefRange= 0, VrefLevel = 6
2730 01:54:25.920204 TX Bit0 (986~1005) 20 995, Bit8 (983~995) 13 989,
2731 01:54:25.923297 TX Bit1 (985~1005) 21 995, Bit9 (983~995) 13 989,
2732 01:54:25.929328 TX Bit2 (984~1000) 17 992, Bit10 (985~1000) 16 992,
2733 01:54:25.933114 TX Bit3 (982~998) 17 990, Bit11 (985~1000) 16 992,
2734 01:54:25.939689 TX Bit4 (985~1004) 20 994, Bit12 (985~1000) 16 992,
2735 01:54:25.942868 TX Bit5 (986~1005) 20 995, Bit13 (986~1000) 15 993,
2736 01:54:25.949526 TX Bit6 (985~1005) 21 995, Bit14 (985~996) 12 990,
2737 01:54:25.952673 TX Bit7 (985~1003) 19 994, Bit15 (979~992) 14 985,
2738 01:54:25.953068
2739 01:54:25.955883 Write Rank0 MR14 =0x8
2740 01:54:25.962870
2741 01:54:25.963265 CH=1, VrefRange= 0, VrefLevel = 8
2742 01:54:25.969503 TX Bit0 (986~1006) 21 996, Bit8 (982~996) 15 989,
2743 01:54:25.973049 TX Bit1 (984~1005) 22 994, Bit9 (982~995) 14 988,
2744 01:54:25.978803 TX Bit2 (984~1001) 18 992, Bit10 (985~1001) 17 993,
2745 01:54:25.982178 TX Bit3 (982~998) 17 990, Bit11 (986~1000) 15 993,
2746 01:54:25.989241 TX Bit4 (985~1005) 21 995, Bit12 (985~1000) 16 992,
2747 01:54:25.992182 TX Bit5 (985~1005) 21 995, Bit13 (986~1000) 15 993,
2748 01:54:25.995552 TX Bit6 (985~1005) 21 995, Bit14 (985~998) 14 991,
2749 01:54:26.001803 TX Bit7 (985~1004) 20 994, Bit15 (979~993) 15 986,
2750 01:54:26.001882
2751 01:54:26.004770 Write Rank0 MR14 =0xa
2752 01:54:26.011828
2753 01:54:26.015486 CH=1, VrefRange= 0, VrefLevel = 10
2754 01:54:26.018009 TX Bit0 (985~1006) 22 995, Bit8 (981~997) 17 989,
2755 01:54:26.021462 TX Bit1 (985~1005) 21 995, Bit9 (983~996) 14 989,
2756 01:54:26.027966 TX Bit2 (983~1002) 20 992, Bit10 (985~1001) 17 993,
2757 01:54:26.031020 TX Bit3 (982~999) 18 990, Bit11 (985~1001) 17 993,
2758 01:54:26.038024 TX Bit4 (985~1005) 21 995, Bit12 (986~1001) 16 993,
2759 01:54:26.041182 TX Bit5 (985~1005) 21 995, Bit13 (986~1001) 16 993,
2760 01:54:26.044437 TX Bit6 (985~1005) 21 995, Bit14 (985~999) 15 992,
2761 01:54:26.051196 TX Bit7 (985~1004) 20 994, Bit15 (979~993) 15 986,
2762 01:54:26.051272
2763 01:54:26.054454 Write Rank0 MR14 =0xc
2764 01:54:26.060866
2765 01:54:26.064702 CH=1, VrefRange= 0, VrefLevel = 12
2766 01:54:26.067784 TX Bit0 (985~1006) 22 995, Bit8 (981~997) 17 989,
2767 01:54:26.071200 TX Bit1 (984~1006) 23 995, Bit9 (982~997) 16 989,
2768 01:54:26.077226 TX Bit2 (983~1003) 21 993, Bit10 (984~1001) 18 992,
2769 01:54:26.080731 TX Bit3 (982~1000) 19 991, Bit11 (986~1001) 16 993,
2770 01:54:26.087585 TX Bit4 (984~1005) 22 994, Bit12 (985~1001) 17 993,
2771 01:54:26.090291 TX Bit5 (985~1006) 22 995, Bit13 (986~1001) 16 993,
2772 01:54:26.097606 TX Bit6 (985~1005) 21 995, Bit14 (985~1000) 16 992,
2773 01:54:26.100373 TX Bit7 (985~1005) 21 995, Bit15 (978~994) 17 986,
2774 01:54:26.100488
2775 01:54:26.103589 Write Rank0 MR14 =0xe
2776 01:54:26.110762
2777 01:54:26.114150 CH=1, VrefRange= 0, VrefLevel = 14
2778 01:54:26.117272 TX Bit0 (985~1007) 23 996, Bit8 (982~999) 18 990,
2779 01:54:26.120765 TX Bit1 (984~1006) 23 995, Bit9 (982~997) 16 989,
2780 01:54:26.127168 TX Bit2 (983~1003) 21 993, Bit10 (984~1002) 19 993,
2781 01:54:26.130676 TX Bit3 (981~1000) 20 990, Bit11 (985~1002) 18 993,
2782 01:54:26.136977 TX Bit4 (984~1005) 22 994, Bit12 (984~1001) 18 992,
2783 01:54:26.140156 TX Bit5 (985~1006) 22 995, Bit13 (985~1001) 17 993,
2784 01:54:26.143790 TX Bit6 (985~1006) 22 995, Bit14 (985~1000) 16 992,
2785 01:54:26.150505 TX Bit7 (985~1005) 21 995, Bit15 (978~994) 17 986,
2786 01:54:26.150597
2787 01:54:26.153088 Write Rank0 MR14 =0x10
2788 01:54:26.160405
2789 01:54:26.164211 CH=1, VrefRange= 0, VrefLevel = 16
2790 01:54:26.167637 TX Bit0 (985~1007) 23 996, Bit8 (980~1000) 21 990,
2791 01:54:26.170416 TX Bit1 (984~1006) 23 995, Bit9 (981~998) 18 989,
2792 01:54:26.176964 TX Bit2 (983~1004) 22 993, Bit10 (984~1002) 19 993,
2793 01:54:26.180317 TX Bit3 (981~1001) 21 991, Bit11 (985~1002) 18 993,
2794 01:54:26.187015 TX Bit4 (984~1006) 23 995, Bit12 (985~1002) 18 993,
2795 01:54:26.190148 TX Bit5 (985~1006) 22 995, Bit13 (985~1002) 18 993,
2796 01:54:26.196785 TX Bit6 (984~1006) 23 995, Bit14 (984~1001) 18 992,
2797 01:54:26.200198 TX Bit7 (984~1005) 22 994, Bit15 (978~995) 18 986,
2798 01:54:26.200305
2799 01:54:26.202861 Write Rank0 MR14 =0x12
2800 01:54:26.210592
2801 01:54:26.214011 CH=1, VrefRange= 0, VrefLevel = 18
2802 01:54:26.217029 TX Bit0 (985~1007) 23 996, Bit8 (980~1000) 21 990,
2803 01:54:26.220535 TX Bit1 (984~1007) 24 995, Bit9 (981~999) 19 990,
2804 01:54:26.227030 TX Bit2 (983~1005) 23 994, Bit10 (984~1002) 19 993,
2805 01:54:26.230033 TX Bit3 (980~1001) 22 990, Bit11 (985~1002) 18 993,
2806 01:54:26.236804 TX Bit4 (984~1006) 23 995, Bit12 (984~1002) 19 993,
2807 01:54:26.239835 TX Bit5 (985~1007) 23 996, Bit13 (985~1002) 18 993,
2808 01:54:26.246908 TX Bit6 (984~1007) 24 995, Bit14 (984~1001) 18 992,
2809 01:54:26.250057 TX Bit7 (984~1006) 23 995, Bit15 (978~995) 18 986,
2810 01:54:26.250133
2811 01:54:26.253022 Write Rank0 MR14 =0x14
2812 01:54:26.260627
2813 01:54:26.264234 CH=1, VrefRange= 0, VrefLevel = 20
2814 01:54:26.267263 TX Bit0 (985~1008) 24 996, Bit8 (980~1000) 21 990,
2815 01:54:26.270212 TX Bit1 (984~1007) 24 995, Bit9 (980~1000) 21 990,
2816 01:54:26.277149 TX Bit2 (982~1005) 24 993, Bit10 (983~1003) 21 993,
2817 01:54:26.280264 TX Bit3 (980~1002) 23 991, Bit11 (985~1003) 19 994,
2818 01:54:26.286965 TX Bit4 (984~1006) 23 995, Bit12 (984~1003) 20 993,
2819 01:54:26.290298 TX Bit5 (985~1007) 23 996, Bit13 (985~1002) 18 993,
2820 01:54:26.296563 TX Bit6 (984~1007) 24 995, Bit14 (984~1001) 18 992,
2821 01:54:26.299815 TX Bit7 (984~1006) 23 995, Bit15 (978~995) 18 986,
2822 01:54:26.299923
2823 01:54:26.303121 Write Rank0 MR14 =0x16
2824 01:54:26.311143
2825 01:54:26.313949 CH=1, VrefRange= 0, VrefLevel = 22
2826 01:54:26.317232 TX Bit0 (984~1008) 25 996, Bit8 (979~1001) 23 990,
2827 01:54:26.320639 TX Bit1 (983~1007) 25 995, Bit9 (979~1000) 22 989,
2828 01:54:26.327257 TX Bit2 (982~1005) 24 993, Bit10 (983~1003) 21 993,
2829 01:54:26.330690 TX Bit3 (979~1003) 25 991, Bit11 (983~1003) 21 993,
2830 01:54:26.337359 TX Bit4 (984~1007) 24 995, Bit12 (984~1003) 20 993,
2831 01:54:26.340498 TX Bit5 (984~1007) 24 995, Bit13 (985~1003) 19 994,
2832 01:54:26.346593 TX Bit6 (984~1007) 24 995, Bit14 (984~1002) 19 993,
2833 01:54:26.349980 TX Bit7 (984~1006) 23 995, Bit15 (977~996) 20 986,
2834 01:54:26.350057
2835 01:54:26.353234 Write Rank0 MR14 =0x18
2836 01:54:26.361324
2837 01:54:26.364379 CH=1, VrefRange= 0, VrefLevel = 24
2838 01:54:26.367641 TX Bit0 (984~1009) 26 996, Bit8 (979~1001) 23 990,
2839 01:54:26.371104 TX Bit1 (983~1007) 25 995, Bit9 (979~1001) 23 990,
2840 01:54:26.377386 TX Bit2 (982~1006) 25 994, Bit10 (982~1003) 22 992,
2841 01:54:26.380715 TX Bit3 (979~1004) 26 991, Bit11 (984~1004) 21 994,
2842 01:54:26.387154 TX Bit4 (983~1007) 25 995, Bit12 (983~1003) 21 993,
2843 01:54:26.390716 TX Bit5 (984~1008) 25 996, Bit13 (984~1003) 20 993,
2844 01:54:26.397215 TX Bit6 (984~1007) 24 995, Bit14 (982~1002) 21 992,
2845 01:54:26.400160 TX Bit7 (984~1006) 23 995, Bit15 (977~997) 21 987,
2846 01:54:26.400240
2847 01:54:26.404385 Write Rank0 MR14 =0x1a
2848 01:54:26.411830
2849 01:54:26.414675 CH=1, VrefRange= 0, VrefLevel = 26
2850 01:54:26.417858 TX Bit0 (984~1009) 26 996, Bit8 (979~1001) 23 990,
2851 01:54:26.421149 TX Bit1 (983~1008) 26 995, Bit9 (979~1001) 23 990,
2852 01:54:26.427585 TX Bit2 (981~1006) 26 993, Bit10 (982~1004) 23 993,
2853 01:54:26.431017 TX Bit3 (979~1004) 26 991, Bit11 (984~1004) 21 994,
2854 01:54:26.437900 TX Bit4 (983~1008) 26 995, Bit12 (984~1004) 21 994,
2855 01:54:26.440570 TX Bit5 (984~1008) 25 996, Bit13 (984~1004) 21 994,
2856 01:54:26.447107 TX Bit6 (983~1008) 26 995, Bit14 (983~1002) 20 992,
2857 01:54:26.450420 TX Bit7 (983~1007) 25 995, Bit15 (976~998) 23 987,
2858 01:54:26.450497
2859 01:54:26.453841 Write Rank0 MR14 =0x1c
2860 01:54:26.461776
2861 01:54:26.465204 CH=1, VrefRange= 0, VrefLevel = 28
2862 01:54:26.468717 TX Bit0 (984~1009) 26 996, Bit8 (979~1002) 24 990,
2863 01:54:26.471497 TX Bit1 (983~1008) 26 995, Bit9 (979~1001) 23 990,
2864 01:54:26.478447 TX Bit2 (981~1006) 26 993, Bit10 (982~1003) 22 992,
2865 01:54:26.481539 TX Bit3 (979~1004) 26 991, Bit11 (983~1004) 22 993,
2866 01:54:26.488207 TX Bit4 (983~1008) 26 995, Bit12 (984~1004) 21 994,
2867 01:54:26.491420 TX Bit5 (984~1008) 25 996, Bit13 (984~1004) 21 994,
2868 01:54:26.497864 TX Bit6 (983~1008) 26 995, Bit14 (981~1003) 23 992,
2869 01:54:26.501015 TX Bit7 (983~1007) 25 995, Bit15 (976~999) 24 987,
2870 01:54:26.501086
2871 01:54:26.504536 Write Rank0 MR14 =0x1e
2872 01:54:26.512388
2873 01:54:26.515625 CH=1, VrefRange= 0, VrefLevel = 30
2874 01:54:26.518536 TX Bit0 (984~1010) 27 997, Bit8 (979~1001) 23 990,
2875 01:54:26.522048 TX Bit1 (983~1008) 26 995, Bit9 (979~1001) 23 990,
2876 01:54:26.528752 TX Bit2 (981~1006) 26 993, Bit10 (982~1003) 22 992,
2877 01:54:26.532075 TX Bit3 (978~1005) 28 991, Bit11 (983~1003) 21 993,
2878 01:54:26.538764 TX Bit4 (984~1008) 25 996, Bit12 (984~1004) 21 994,
2879 01:54:26.542113 TX Bit5 (984~1009) 26 996, Bit13 (984~1004) 21 994,
2880 01:54:26.548064 TX Bit6 (983~1009) 27 996, Bit14 (982~1003) 22 992,
2881 01:54:26.551727 TX Bit7 (983~1007) 25 995, Bit15 (976~999) 24 987,
2882 01:54:26.551796
2883 01:54:26.554952 Write Rank0 MR14 =0x20
2884 01:54:26.563019
2885 01:54:26.566271 CH=1, VrefRange= 0, VrefLevel = 32
2886 01:54:26.568898 TX Bit0 (984~1010) 27 997, Bit8 (979~1001) 23 990,
2887 01:54:26.572814 TX Bit1 (983~1008) 26 995, Bit9 (979~1001) 23 990,
2888 01:54:26.579248 TX Bit2 (981~1006) 26 993, Bit10 (982~1003) 22 992,
2889 01:54:26.582186 TX Bit3 (978~1005) 28 991, Bit11 (983~1003) 21 993,
2890 01:54:26.588774 TX Bit4 (984~1008) 25 996, Bit12 (984~1004) 21 994,
2891 01:54:26.591967 TX Bit5 (984~1009) 26 996, Bit13 (984~1004) 21 994,
2892 01:54:26.598757 TX Bit6 (983~1009) 27 996, Bit14 (982~1003) 22 992,
2893 01:54:26.602306 TX Bit7 (983~1007) 25 995, Bit15 (976~999) 24 987,
2894 01:54:26.602374
2895 01:54:26.605241 Write Rank0 MR14 =0x22
2896 01:54:26.613211
2897 01:54:26.616445 CH=1, VrefRange= 0, VrefLevel = 34
2898 01:54:26.619667 TX Bit0 (984~1010) 27 997, Bit8 (979~1001) 23 990,
2899 01:54:26.622872 TX Bit1 (983~1008) 26 995, Bit9 (979~1001) 23 990,
2900 01:54:26.630018 TX Bit2 (981~1006) 26 993, Bit10 (982~1003) 22 992,
2901 01:54:26.632732 TX Bit3 (978~1005) 28 991, Bit11 (983~1003) 21 993,
2902 01:54:26.639529 TX Bit4 (984~1008) 25 996, Bit12 (984~1004) 21 994,
2903 01:54:26.642574 TX Bit5 (984~1009) 26 996, Bit13 (984~1004) 21 994,
2904 01:54:26.649323 TX Bit6 (983~1009) 27 996, Bit14 (982~1003) 22 992,
2905 01:54:26.652376 TX Bit7 (983~1007) 25 995, Bit15 (976~999) 24 987,
2906 01:54:26.652440
2907 01:54:26.655482 Write Rank0 MR14 =0x24
2908 01:54:26.663032
2909 01:54:26.666349 CH=1, VrefRange= 0, VrefLevel = 36
2910 01:54:26.669754 TX Bit0 (984~1010) 27 997, Bit8 (979~1001) 23 990,
2911 01:54:26.673300 TX Bit1 (983~1008) 26 995, Bit9 (979~1001) 23 990,
2912 01:54:26.679931 TX Bit2 (981~1006) 26 993, Bit10 (982~1003) 22 992,
2913 01:54:26.683305 TX Bit3 (978~1005) 28 991, Bit11 (983~1003) 21 993,
2914 01:54:26.689468 TX Bit4 (984~1008) 25 996, Bit12 (984~1004) 21 994,
2915 01:54:26.692939 TX Bit5 (984~1009) 26 996, Bit13 (984~1004) 21 994,
2916 01:54:26.699237 TX Bit6 (983~1009) 27 996, Bit14 (982~1003) 22 992,
2917 01:54:26.702514 TX Bit7 (983~1007) 25 995, Bit15 (976~999) 24 987,
2918 01:54:26.702702
2919 01:54:26.702815
2920 01:54:26.705916 TX Vref found, early break! 354< 367
2921 01:54:26.712728 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =753/100 ps
2922 01:54:26.712810 u1DelayCellOfst[0]=7 cells (6 PI)
2923 01:54:26.715711 u1DelayCellOfst[1]=5 cells (4 PI)
2924 01:54:26.719498 u1DelayCellOfst[2]=2 cells (2 PI)
2925 01:54:26.722612 u1DelayCellOfst[3]=0 cells (0 PI)
2926 01:54:26.725701 u1DelayCellOfst[4]=6 cells (5 PI)
2927 01:54:26.728956 u1DelayCellOfst[5]=6 cells (5 PI)
2928 01:54:26.733058 u1DelayCellOfst[6]=6 cells (5 PI)
2929 01:54:26.735659 u1DelayCellOfst[7]=5 cells (4 PI)
2930 01:54:26.739337 Byte0, DQ PI dly=991, DQM PI dly= 994
2931 01:54:26.742522 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 31)
2932 01:54:26.743004
2933 01:54:26.748423 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 31)
2934 01:54:26.748955
2935 01:54:26.751278 u1DelayCellOfst[8]=3 cells (3 PI)
2936 01:54:26.755293 u1DelayCellOfst[9]=3 cells (3 PI)
2937 01:54:26.755372 u1DelayCellOfst[10]=6 cells (5 PI)
2938 01:54:26.758396 u1DelayCellOfst[11]=7 cells (6 PI)
2939 01:54:26.761231 u1DelayCellOfst[12]=9 cells (7 PI)
2940 01:54:26.764775 u1DelayCellOfst[13]=9 cells (7 PI)
2941 01:54:26.768102 u1DelayCellOfst[14]=6 cells (5 PI)
2942 01:54:26.771366 u1DelayCellOfst[15]=0 cells (0 PI)
2943 01:54:26.774748 Byte1, DQ PI dly=987, DQM PI dly= 990
2944 01:54:26.781397 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 27)
2945 01:54:26.781811
2946 01:54:26.784436 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 27)
2947 01:54:26.784761
2948 01:54:26.787763 Write Rank0 MR14 =0x1e
2949 01:54:26.788087
2950 01:54:26.788373 Final TX Range 0 Vref 30
2951 01:54:26.788659
2952 01:54:26.794291 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
2953 01:54:26.794639
2954 01:54:26.801295 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
2955 01:54:26.811068 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2956 01:54:26.817756 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2957 01:54:26.818159 Write Rank0 MR3 =0xb0
2958 01:54:26.821089 DramC Write-DBI on
2959 01:54:26.821480 ==
2960 01:54:26.824292 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2961 01:54:26.827272 fsp= 1, odt_onoff= 1, Byte mode= 0
2962 01:54:26.827668 ==
2963 01:54:26.833910 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
2964 01:54:26.834303
2965 01:54:26.837596 Begin, DQ Scan Range 710~774
2966 01:54:26.838102
2967 01:54:26.838520
2968 01:54:26.838817 TX Vref Scan disable
2969 01:54:26.840440 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
2970 01:54:26.843843 711 |2 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
2971 01:54:26.847150 712 |2 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
2972 01:54:26.853780 713 |2 6 9|[0] xxxxxxxx xxxxxxxx [MSB]
2973 01:54:26.856905 714 |2 6 10|[0] xxxxxxxx xxxxxxxx [MSB]
2974 01:54:26.860190 715 |2 6 11|[0] xxxxxxxx xxxxxxxx [MSB]
2975 01:54:26.863501 716 |2 6 12|[0] xxxxxxxx xxxxxxxx [MSB]
2976 01:54:26.866920 717 |2 6 13|[0] xxxxxxxx xxxxxxxx [MSB]
2977 01:54:26.869821 718 |2 6 14|[0] xxxxxxxx xxxxxxxx [MSB]
2978 01:54:26.873092 719 |2 6 15|[0] xxxxxxxx xxxxxxxx [MSB]
2979 01:54:26.876459 720 |2 6 16|[0] xxxxxxxx xxxxxxxx [MSB]
2980 01:54:26.879848 721 |2 6 17|[0] xxxxxxxx xxxxxxxx [MSB]
2981 01:54:26.883297 722 |2 6 18|[0] xxxxxxxx xxxxxxxx [MSB]
2982 01:54:26.886763 723 |2 6 19|[0] xxxxxxxx oooooooo [MSB]
2983 01:54:26.889723 724 |2 6 20|[0] xxxxxxxx oooooooo [MSB]
2984 01:54:26.893040 725 |2 6 21|[0] xxxxxxxx oooooooo [MSB]
2985 01:54:26.899413 726 |2 6 22|[0] xxxxxxxx oooooooo [MSB]
2986 01:54:26.902640 727 |2 6 23|[0] xxxxxxxx oooooooo [MSB]
2987 01:54:26.908747 747 |2 6 43|[0] oooooooo xxxxxxxx [MSB]
2988 01:54:26.912342 748 |2 6 44|[0] oooooooo xxxxxxxx [MSB]
2989 01:54:26.915258 749 |2 6 45|[0] oooooooo xxxxxxxx [MSB]
2990 01:54:26.918983 750 |2 6 46|[0] oooooooo xxxxxxxx [MSB]
2991 01:54:26.922062 751 |2 6 47|[0] oooooooo xxxxxxxx [MSB]
2992 01:54:26.925160 752 |2 6 48|[0] oooooooo xxxxxxxx [MSB]
2993 01:54:26.928518 753 |2 6 49|[0] oooooooo xxxxxxxx [MSB]
2994 01:54:26.931705 754 |2 6 50|[0] oooooooo xxxxxxxx [MSB]
2995 01:54:26.934921 755 |2 6 51|[0] xxxxxxxx xxxxxxxx [MSB]
2996 01:54:26.938143 Byte0, DQ PI dly=741, DQM PI dly= 741
2997 01:54:26.944705 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 37)
2998 01:54:26.944781
2999 01:54:26.948195 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 37)
3000 01:54:26.948295
3001 01:54:26.951693 Byte1, DQ PI dly=734, DQM PI dly= 734
3002 01:54:26.954731 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 30)
3003 01:54:26.954808
3004 01:54:26.961034 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 30)
3005 01:54:26.961111
3006 01:54:26.967729 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
3007 01:54:26.974431 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3008 01:54:26.980968 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3009 01:54:26.984188 Write Rank0 MR3 =0x30
3010 01:54:26.984264 DramC Write-DBI off
3011 01:54:26.984323
3012 01:54:26.984376 [DATLAT]
3013 01:54:26.988283 Freq=1600, CH1 RK0, use_rxtx_scan=0
3014 01:54:26.988360
3015 01:54:26.990997 DATLAT Default: 0xf
3016 01:54:26.993784 7, 0xFFFF, sum=0
3017 01:54:26.993861 8, 0xFFFF, sum=0
3018 01:54:26.993921 9, 0xFFFF, sum=0
3019 01:54:26.997456 10, 0xFFFF, sum=0
3020 01:54:26.997533 11, 0xFFFF, sum=0
3021 01:54:27.000448 12, 0xFFFF, sum=0
3022 01:54:27.000525 13, 0xFFFF, sum=0
3023 01:54:27.003792 14, 0x0, sum=1
3024 01:54:27.003954 15, 0x0, sum=2
3025 01:54:27.007164 16, 0x0, sum=3
3026 01:54:27.007236 17, 0x0, sum=4
3027 01:54:27.010715 pattern=2 first_step=14 total pass=5 best_step=16
3028 01:54:27.013985 ==
3029 01:54:27.017328 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
3030 01:54:27.020452 fsp= 1, odt_onoff= 1, Byte mode= 0
3031 01:54:27.020520 ==
3032 01:54:27.023375 Start DQ dly to find pass range UseTestEngine =1
3033 01:54:27.030155 x-axis: bit #, y-axis: DQ dly (-127~63)
3034 01:54:27.030257 RX Vref Scan = 1
3035 01:54:27.144973
3036 01:54:27.145100 RX Vref found, early break!
3037 01:54:27.145162
3038 01:54:27.151705 Final RX Vref 11, apply to both rank0 and 1
3039 01:54:27.151779 ==
3040 01:54:27.154858 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
3041 01:54:27.158067 fsp= 1, odt_onoff= 1, Byte mode= 0
3042 01:54:27.158134 ==
3043 01:54:27.161199 DQS Delay:
3044 01:54:27.161262 DQS0 = 0, DQS1 = 0
3045 01:54:27.161324 DQM Delay:
3046 01:54:27.164833 DQM0 = 20, DQM1 = 19
3047 01:54:27.164927 DQ Delay:
3048 01:54:27.167853 DQ0 =22, DQ1 =20, DQ2 =19, DQ3 =16
3049 01:54:27.171101 DQ4 =20, DQ5 =22, DQ6 =24, DQ7 =21
3050 01:54:27.174457 DQ8 =17, DQ9 =17, DQ10 =21, DQ11 =21
3051 01:54:27.177723 DQ12 =22, DQ13 =21, DQ14 =22, DQ15 =14
3052 01:54:27.177786
3053 01:54:27.177848
3054 01:54:27.177900
3055 01:54:27.181274 [DramC_TX_OE_Calibration] TA2
3056 01:54:27.184471 Original DQ_B0 (3 6) =30, OEN = 27
3057 01:54:27.187852 Original DQ_B1 (3 6) =30, OEN = 27
3058 01:54:27.191086 23, 0x0, End_B0=23 End_B1=23
3059 01:54:27.194413 24, 0x0, End_B0=24 End_B1=24
3060 01:54:27.194475 25, 0x0, End_B0=25 End_B1=25
3061 01:54:27.197020 26, 0x0, End_B0=26 End_B1=26
3062 01:54:27.200521 27, 0x0, End_B0=27 End_B1=27
3063 01:54:27.203729 28, 0x0, End_B0=28 End_B1=28
3064 01:54:27.206870 29, 0x0, End_B0=29 End_B1=29
3065 01:54:27.206938 30, 0x0, End_B0=30 End_B1=30
3066 01:54:27.210186 31, 0xFFFF, End_B0=30 End_B1=30
3067 01:54:27.216920 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3068 01:54:27.223218 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3069 01:54:27.223285
3070 01:54:27.223340
3071 01:54:27.223392 Write Rank0 MR23 =0x3f
3072 01:54:27.226898 [DQSOSC]
3073 01:54:27.233637 [DQSOSCAuto] RK0, (LSB)MR18= 0xacac, (MSB)MR19= 0x202, tDQSOscB0 = 460 ps tDQSOscB1 = 460 ps
3074 01:54:27.239567 CH1_RK0: MR19=0x202, MR18=0xACAC, DQSOSC=460, MR23=63, INC=11, DEC=17
3075 01:54:27.243179 Write Rank0 MR23 =0x3f
3076 01:54:27.243246 [DQSOSC]
3077 01:54:27.249627 [DQSOSCAuto] RK0, (LSB)MR18= 0xaeae, (MSB)MR19= 0x202, tDQSOscB0 = 459 ps tDQSOscB1 = 459 ps
3078 01:54:27.253001 CH1 RK0: MR19=202, MR18=AEAE
3079 01:54:27.256163 [RankSwap] Rank num 2, (Multi 1), Rank 1
3080 01:54:27.259657 Write Rank0 MR2 =0xad
3081 01:54:27.259725 [Write Leveling]
3082 01:54:27.262656 delay byte0 byte1 byte2 byte3
3083 01:54:27.262733
3084 01:54:27.265739 10 0 0
3085 01:54:27.265821 11 0 0
3086 01:54:27.269067 12 0 0
3087 01:54:27.269134 13 0 0
3088 01:54:27.269189 14 0 0
3089 01:54:27.272667 15 0 0
3090 01:54:27.272761 16 0 0
3091 01:54:27.275680 17 0 0
3092 01:54:27.275758 18 0 0
3093 01:54:27.275815 19 0 0
3094 01:54:27.279241 20 0 0
3095 01:54:27.279309 21 0 0
3096 01:54:27.282236 22 0 0
3097 01:54:27.282319 23 0 0
3098 01:54:27.285536 24 0 0
3099 01:54:27.285685 25 0 0
3100 01:54:27.285743 26 0 0
3101 01:54:27.288754 27 0 0
3102 01:54:27.288818 28 0 0
3103 01:54:27.292321 29 0 ff
3104 01:54:27.292389 30 0 ff
3105 01:54:27.295577 31 0 ff
3106 01:54:27.295639 32 0 ff
3107 01:54:27.298853 33 0 ff
3108 01:54:27.298920 34 0 ff
3109 01:54:27.298977 35 ff ff
3110 01:54:27.302389 36 ff ff
3111 01:54:27.302478 37 ff ff
3112 01:54:27.305675 38 ff ff
3113 01:54:27.305738 39 ff ff
3114 01:54:27.308695 40 ff ff
3115 01:54:27.308760 41 ff ff
3116 01:54:27.312035 pass bytecount = 0xff (0xff: all bytes pass)
3117 01:54:27.315474
3118 01:54:27.315541 DQS0 dly: 35
3119 01:54:27.315594 DQS1 dly: 29
3120 01:54:27.318766 Write Rank0 MR2 =0x2d
3121 01:54:27.322145 [RankSwap] Rank num 2, (Multi 1), Rank 0
3122 01:54:27.324971 Write Rank1 MR1 =0xd6
3123 01:54:27.325031 [Gating]
3124 01:54:27.325082 ==
3125 01:54:27.328036 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3126 01:54:27.331766 fsp= 1, odt_onoff= 1, Byte mode= 0
3127 01:54:27.335023 ==
3128 01:54:27.338418 3 1 0 |2c2b 3434 |(11 11)(11 11) |(1 1)(1 1)| 0
3129 01:54:27.341798 3 1 4 |2c2b 3535 |(11 11)(11 11) |(1 1)(0 0)| 0
3130 01:54:27.344741 3 1 8 |2c2b 3535 |(11 11)(0 0) |(1 1)(0 0)| 0
3131 01:54:27.351251 3 1 12 |2c2b 605 |(11 11)(11 11) |(0 0)(0 0)| 0
3132 01:54:27.354610 3 1 16 |2c2b 3635 |(11 11)(11 11) |(1 0)(1 1)| 0
3133 01:54:27.357892 3 1 20 |2c2b 3535 |(11 11)(0 0) |(1 0)(1 1)| 0
3134 01:54:27.364396 3 1 24 |2c2b 3636 |(11 11)(10 10) |(1 0)(1 1)| 0
3135 01:54:27.367561 3 1 28 |2c2b 3535 |(11 11)(1 1) |(1 0)(0 0)| 0
3136 01:54:27.371281 3 2 0 |2c2b 3434 |(11 11)(11 11) |(1 0)(0 0)| 0
3137 01:54:27.377542 3 2 4 |2c2b 1e1e |(11 11)(11 11) |(1 0)(0 0)| 0
3138 01:54:27.380737 3 2 8 |2c2b 3333 |(11 11)(10 10) |(1 0)(0 0)| 0
3139 01:54:27.384296 3 2 12 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 0)| 0
3140 01:54:27.390620 3 2 16 |2c2b 3332 |(11 11)(11 11) |(1 0)(0 0)| 0
3141 01:54:27.394354 3 2 20 |404 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
3142 01:54:27.396951 3 2 24 |1716 3434 |(11 11)(0 1) |(0 0)(1 1)| 0
3143 01:54:27.400189 [Byte 1] Lead/lag Transition tap number (1)
3144 01:54:27.406920 3 2 28 |3534 1312 |(11 11)(11 11) |(0 0)(0 0)| 0
3145 01:54:27.410302 3 3 0 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
3146 01:54:27.413803 3 3 4 |3534 3d3c |(11 11)(11 11) |(0 0)(1 1)| 0
3147 01:54:27.420136 3 3 8 |3534 3c3b |(11 11)(11 11) |(0 0)(1 1)| 0
3148 01:54:27.423403 3 3 12 |3534 c0c |(11 11)(11 11) |(0 0)(1 1)| 0
3149 01:54:27.426745 3 3 16 |3534 202 |(11 11)(11 11) |(1 1)(1 1)| 0
3150 01:54:27.433320 3 3 20 |3534 908 |(11 11)(11 11) |(1 1)(1 1)| 0
3151 01:54:27.436275 [Byte 0] Lead/lag Transition tap number (1)
3152 01:54:27.440047 3 3 24 |3534 3d3d |(11 11)(0 0) |(0 0)(1 1)| 0
3153 01:54:27.443418 3 3 28 |3534 1716 |(11 11)(11 11) |(0 0)(1 1)| 0
3154 01:54:27.449964 3 4 0 |3534 3534 |(11 11)(11 11) |(0 0)(1 1)| 0
3155 01:54:27.453034 [Byte 1] Lead/lag Transition tap number (1)
3156 01:54:27.456429 3 4 4 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
3157 01:54:27.462479 3 4 8 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
3158 01:54:27.465857 3 4 12 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
3159 01:54:27.469616 3 4 16 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
3160 01:54:27.476063 3 4 20 |201 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
3161 01:54:27.479422 3 4 24 |908 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
3162 01:54:27.482644 3 4 28 |3d3d 201 |(11 11)(11 11) |(1 1)(1 1)| 0
3163 01:54:27.485911 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3164 01:54:27.492260 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3165 01:54:27.495349 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3166 01:54:27.498914 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3167 01:54:27.505643 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3168 01:54:27.508720 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3169 01:54:27.512054 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3170 01:54:27.518558 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3171 01:54:27.521760 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3172 01:54:27.525243 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3173 01:54:27.531490 3 6 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3174 01:54:27.534656 [Byte 0] Lead/lag falling Transition (3, 6, 8)
3175 01:54:27.537908 3 6 12 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
3176 01:54:27.544793 3 6 16 |3e3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
3177 01:54:27.548049 [Byte 0] Lead/lag Transition tap number (3)
3178 01:54:27.551408 [Byte 1] Lead/lag falling Transition (3, 6, 16)
3179 01:54:27.554283 3 6 20 |404 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
3180 01:54:27.561047 [Byte 1] Lead/lag Transition tap number (2)
3181 01:54:27.564437 3 6 24 |4646 605 |(0 0)(11 11) |(0 0)(0 0)| 0
3182 01:54:27.567889 [Byte 0]First pass (3, 6, 24)
3183 01:54:27.571486 3 6 28 |4646 2020 |(0 0)(11 11) |(0 0)(0 0)| 0
3184 01:54:27.574503 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3185 01:54:27.577670 [Byte 1]First pass (3, 7, 0)
3186 01:54:27.581025 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3187 01:54:27.584265 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3188 01:54:27.590538 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3189 01:54:27.593894 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3190 01:54:27.597468 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3191 01:54:27.600428 3 7 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3192 01:54:27.607361 3 7 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3193 01:54:27.610850 4 0 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3194 01:54:27.613829 All bytes gating window > 1UI, Early break!
3195 01:54:27.614084
3196 01:54:27.616995 best DQS0 dly(2T, 0.5T, PI) = (3, 6, 14)
3197 01:54:27.617362
3198 01:54:27.620755 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 20)
3199 01:54:27.621064
3200 01:54:27.621332
3201 01:54:27.624238
3202 01:54:27.627271 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 14)
3203 01:54:27.627639
3204 01:54:27.630077 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 20)
3205 01:54:27.630427
3206 01:54:27.630731
3207 01:54:27.633510 Write Rank1 MR1 =0x56
3208 01:54:27.634251
3209 01:54:27.636601 best RODT dly(2T, 0.5T) = (2, 3)
3210 01:54:27.637080
3211 01:54:27.639850 best RODT dly(2T, 0.5T) = (2, 3)
3212 01:54:27.640348 ==
3213 01:54:27.642780 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3214 01:54:27.646253 fsp= 1, odt_onoff= 1, Byte mode= 0
3215 01:54:27.646329 ==
3216 01:54:27.649631 Start DQ dly to find pass range UseTestEngine =0
3217 01:54:27.656126 x-axis: bit #, y-axis: DQ dly (-127~63)
3218 01:54:27.656226 RX Vref Scan = 0
3219 01:54:27.659223 -26, [0] xxxxxxxx xxxxxxxx [MSB]
3220 01:54:27.662665 -25, [0] xxxxxxxx xxxxxxxx [MSB]
3221 01:54:27.665743 -24, [0] xxxxxxxx xxxxxxxx [MSB]
3222 01:54:27.668903 -23, [0] xxxxxxxx xxxxxxxx [MSB]
3223 01:54:27.672187 -22, [0] xxxxxxxx xxxxxxxx [MSB]
3224 01:54:27.672265 -21, [0] xxxxxxxx xxxxxxxx [MSB]
3225 01:54:27.675374 -20, [0] xxxxxxxx xxxxxxxx [MSB]
3226 01:54:27.679261 -19, [0] xxxxxxxx xxxxxxxx [MSB]
3227 01:54:27.681893 -18, [0] xxxxxxxx xxxxxxxx [MSB]
3228 01:54:27.685335 -17, [0] xxxxxxxx xxxxxxxx [MSB]
3229 01:54:27.689209 -16, [0] xxxxxxxx xxxxxxxx [MSB]
3230 01:54:27.691715 -15, [0] xxxxxxxx xxxxxxxx [MSB]
3231 01:54:27.695563 -14, [0] xxxxxxxx xxxxxxxx [MSB]
3232 01:54:27.698774 -13, [0] xxxxxxxx xxxxxxxx [MSB]
3233 01:54:27.698853 -12, [0] xxxxxxxx xxxxxxxx [MSB]
3234 01:54:27.702272 -11, [0] xxxxxxxx xxxxxxxx [MSB]
3235 01:54:27.705494 -10, [0] xxxxxxxx xxxxxxxx [MSB]
3236 01:54:27.708824 -9, [0] xxxxxxxx xxxxxxxx [MSB]
3237 01:54:27.711960 -8, [0] xxxxxxxx xxxxxxxx [MSB]
3238 01:54:27.715031 -7, [0] xxxxxxxx xxxxxxxx [MSB]
3239 01:54:27.718632 -6, [0] xxxxxxxx xxxxxxxx [MSB]
3240 01:54:27.721869 -5, [0] xxxxxxxx xxxxxxxx [MSB]
3241 01:54:27.721947 -4, [0] xxxxxxxx xxxxxxxx [MSB]
3242 01:54:27.725040 -3, [0] xxxxxxxx xxxxxxxx [MSB]
3243 01:54:27.728540 -2, [0] xxxxxxxx xxxxxxxx [MSB]
3244 01:54:27.731609 -1, [0] xxxxxxxx xxxxxxxo [MSB]
3245 01:54:27.734884 0, [0] xxxoxxxx xxxxxxxo [MSB]
3246 01:54:27.738334 1, [0] xxxoxxxx xxxxxxxo [MSB]
3247 01:54:27.741655 2, [0] xxxoxxxx ooxxxxxo [MSB]
3248 01:54:27.741733 3, [0] xooooxxo oooxxxxo [MSB]
3249 01:54:27.744797 4, [0] xooooxxo oooxxxxo [MSB]
3250 01:54:27.747920 5, [0] xooooxxo oooxxxxo [MSB]
3251 01:54:27.751268 6, [0] xooooxoo oooxxxoo [MSB]
3252 01:54:27.754502 32, [0] oooxoooo ooooooox [MSB]
3253 01:54:27.757694 33, [0] oooxoooo ooooooox [MSB]
3254 01:54:27.761257 34, [0] oooxoooo xoooooox [MSB]
3255 01:54:27.761365 35, [0] ooxxoooo xoooooox [MSB]
3256 01:54:27.764245 36, [0] ooxxoooo xxooooox [MSB]
3257 01:54:27.767712 37, [0] ooxxoooo xxooooox [MSB]
3258 01:54:27.771196 38, [0] xxxxooox xxooxoox [MSB]
3259 01:54:27.774184 39, [0] xxxxxoox xxxoxoox [MSB]
3260 01:54:27.777776 40, [0] xxxxxoox xxxoxxox [MSB]
3261 01:54:27.780801 41, [0] xxxxxxxx xxxxxxxx [MSB]
3262 01:54:27.783863 iDelay=41, Bit 0, Center 22 (7 ~ 37) 31
3263 01:54:27.787085 iDelay=41, Bit 1, Center 20 (3 ~ 37) 35
3264 01:54:27.790316 iDelay=41, Bit 2, Center 18 (3 ~ 34) 32
3265 01:54:27.794126 iDelay=41, Bit 3, Center 15 (0 ~ 31) 32
3266 01:54:27.797369 iDelay=41, Bit 4, Center 20 (3 ~ 38) 36
3267 01:54:27.800513 iDelay=41, Bit 5, Center 23 (7 ~ 40) 34
3268 01:54:27.803867 iDelay=41, Bit 6, Center 23 (6 ~ 40) 35
3269 01:54:27.807077 iDelay=41, Bit 7, Center 20 (3 ~ 37) 35
3270 01:54:27.810408 iDelay=41, Bit 8, Center 17 (2 ~ 33) 32
3271 01:54:27.813743 iDelay=41, Bit 9, Center 18 (2 ~ 35) 34
3272 01:54:27.819750 iDelay=41, Bit 10, Center 20 (3 ~ 38) 36
3273 01:54:27.823422 iDelay=41, Bit 11, Center 23 (7 ~ 40) 34
3274 01:54:27.826462 iDelay=41, Bit 12, Center 22 (7 ~ 37) 31
3275 01:54:27.829802 iDelay=41, Bit 13, Center 23 (7 ~ 39) 33
3276 01:54:27.832962 iDelay=41, Bit 14, Center 23 (6 ~ 40) 35
3277 01:54:27.836246 iDelay=41, Bit 15, Center 15 (-1 ~ 31) 33
3278 01:54:27.836322 ==
3279 01:54:27.842852 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3280 01:54:27.846214 fsp= 1, odt_onoff= 1, Byte mode= 0
3281 01:54:27.846292 ==
3282 01:54:27.846351 DQS Delay:
3283 01:54:27.849670 DQS0 = 0, DQS1 = 0
3284 01:54:27.849771 DQM Delay:
3285 01:54:27.852561 DQM0 = 20, DQM1 = 20
3286 01:54:27.852639 DQ Delay:
3287 01:54:27.855837 DQ0 =22, DQ1 =20, DQ2 =18, DQ3 =15
3288 01:54:27.859125 DQ4 =20, DQ5 =23, DQ6 =23, DQ7 =20
3289 01:54:27.862292 DQ8 =17, DQ9 =18, DQ10 =20, DQ11 =23
3290 01:54:27.865670 DQ12 =22, DQ13 =23, DQ14 =23, DQ15 =15
3291 01:54:27.865777
3292 01:54:27.865870
3293 01:54:27.865954 DramC Write-DBI off
3294 01:54:27.866035 ==
3295 01:54:27.872115 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3296 01:54:27.875601 fsp= 1, odt_onoff= 1, Byte mode= 0
3297 01:54:27.875677 ==
3298 01:54:27.878684 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
3299 01:54:27.878784
3300 01:54:27.881804 Begin, DQ Scan Range 925~1181
3301 01:54:27.881881
3302 01:54:27.881940
3303 01:54:27.885315 TX Vref Scan disable
3304 01:54:27.888794 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
3305 01:54:27.892107 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
3306 01:54:27.895043 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
3307 01:54:27.898245 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
3308 01:54:27.901735 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
3309 01:54:27.905132 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
3310 01:54:27.908213 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
3311 01:54:27.914841 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
3312 01:54:27.917948 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
3313 01:54:27.921247 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
3314 01:54:27.924541 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
3315 01:54:27.928319 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
3316 01:54:27.931496 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
3317 01:54:27.934425 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
3318 01:54:27.937583 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
3319 01:54:27.940851 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
3320 01:54:27.944559 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
3321 01:54:27.947624 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
3322 01:54:27.950812 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
3323 01:54:27.954226 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
3324 01:54:27.961052 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
3325 01:54:27.963829 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
3326 01:54:27.967362 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
3327 01:54:27.971060 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
3328 01:54:27.974050 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
3329 01:54:27.977462 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
3330 01:54:27.980188 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
3331 01:54:27.983428 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
3332 01:54:27.986760 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
3333 01:54:27.990032 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
3334 01:54:27.993710 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
3335 01:54:27.996880 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
3336 01:54:28.000260 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
3337 01:54:28.006877 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
3338 01:54:28.010042 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
3339 01:54:28.013035 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
3340 01:54:28.016999 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
3341 01:54:28.020028 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
3342 01:54:28.022939 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
3343 01:54:28.026448 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
3344 01:54:28.029795 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
3345 01:54:28.032873 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
3346 01:54:28.036233 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
3347 01:54:28.039548 968 |3 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
3348 01:54:28.042649 969 |3 6 9|[0] xxxxxxxx xxxxxxxx [MSB]
3349 01:54:28.045950 970 |3 6 10|[0] xxxxxxxx xxxxxxxx [MSB]
3350 01:54:28.049011 971 |3 6 11|[0] xxxxxxxx xxxxxxxx [MSB]
3351 01:54:28.052560 972 |3 6 12|[0] xxxxxxxx xxxxxxxo [MSB]
3352 01:54:28.056211 973 |3 6 13|[0] xxxxxxxx xxxxxxxo [MSB]
3353 01:54:28.062489 974 |3 6 14|[0] xxxxxxxx oxxxxxxo [MSB]
3354 01:54:28.065524 975 |3 6 15|[0] xxxxxxxx ooxxxxxo [MSB]
3355 01:54:28.068906 976 |3 6 16|[0] xxxxxxxx ooxxxxxo [MSB]
3356 01:54:28.072182 977 |3 6 17|[0] xxxxxxxx oooxxxxo [MSB]
3357 01:54:28.075482 978 |3 6 18|[0] xxxxxxxx oooooooo [MSB]
3358 01:54:28.078556 979 |3 6 19|[0] xxxxxxxx oooooooo [MSB]
3359 01:54:28.081947 980 |3 6 20|[0] xxxxxxxx oooooooo [MSB]
3360 01:54:28.085249 981 |3 6 21|[0] xxxxxxxx oooooooo [MSB]
3361 01:54:28.088516 982 |3 6 22|[0] xxxxxxxx oooooooo [MSB]
3362 01:54:28.091764 983 |3 6 23|[0] xxxxxxxx oooooooo [MSB]
3363 01:54:28.095256 984 |3 6 24|[0] xooooooo oooooooo [MSB]
3364 01:54:28.102493 992 |3 6 32|[0] oooooooo ooooooox [MSB]
3365 01:54:28.105241 993 |3 6 33|[0] oooooooo oxooooox [MSB]
3366 01:54:28.108660 994 |3 6 34|[0] oooooooo oxooooox [MSB]
3367 01:54:28.111775 995 |3 6 35|[0] oooooooo xxooooox [MSB]
3368 01:54:28.115674 996 |3 6 36|[0] oooooooo xxxxxxxx [MSB]
3369 01:54:28.118952 997 |3 6 37|[0] oooooooo xxxxxxxx [MSB]
3370 01:54:28.122007 998 |3 6 38|[0] oooooooo xxxxxxxx [MSB]
3371 01:54:28.125355 999 |3 6 39|[0] oooooooo xxxxxxxx [MSB]
3372 01:54:28.128675 1000 |3 6 40|[0] oooxoooo xxxxxxxx [MSB]
3373 01:54:28.131906 1001 |3 6 41|[0] oooxoooo xxxxxxxx [MSB]
3374 01:54:28.135185 1002 |3 6 42|[0] oooxoooo xxxxxxxx [MSB]
3375 01:54:28.141236 1003 |3 6 43|[0] oooxoooo xxxxxxxx [MSB]
3376 01:54:28.144633 1004 |3 6 44|[0] ooxxoooo xxxxxxxx [MSB]
3377 01:54:28.148518 1005 |3 6 45|[0] ooxxoooo xxxxxxxx [MSB]
3378 01:54:28.151136 1006 |3 6 46|[0] xxxxxxxx xxxxxxxx [MSB]
3379 01:54:28.154805 Byte0, DQ PI dly=993, DQM PI dly= 993
3380 01:54:28.157707 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 33)
3381 01:54:28.157783
3382 01:54:28.164512 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 33)
3383 01:54:28.164589
3384 01:54:28.167812 Byte1, DQ PI dly=983, DQM PI dly= 983
3385 01:54:28.170984 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 23)
3386 01:54:28.171086
3387 01:54:28.174160 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 23)
3388 01:54:28.174240
3389 01:54:28.174300 ==
3390 01:54:28.181140 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3391 01:54:28.184357 fsp= 1, odt_onoff= 1, Byte mode= 0
3392 01:54:28.184436 ==
3393 01:54:28.187272 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
3394 01:54:28.187351
3395 01:54:28.190473 Begin, DQ Scan Range 959~1023
3396 01:54:28.193771 Write Rank1 MR14 =0x0
3397 01:54:28.201766
3398 01:54:28.201843 CH=1, VrefRange= 0, VrefLevel = 0
3399 01:54:28.208208 TX Bit0 (986~1000) 15 993, Bit8 (977~991) 15 984,
3400 01:54:28.211782 TX Bit1 (985~999) 15 992, Bit9 (978~988) 11 983,
3401 01:54:28.217780 TX Bit2 (984~998) 15 991, Bit10 (979~992) 14 985,
3402 01:54:28.221498 TX Bit3 (982~995) 14 988, Bit11 (981~992) 12 986,
3403 01:54:28.224370 TX Bit4 (985~999) 15 992, Bit12 (980~992) 13 986,
3404 01:54:28.231303 TX Bit5 (986~1000) 15 993, Bit13 (981~993) 13 987,
3405 01:54:28.234654 TX Bit6 (985~1000) 16 992, Bit14 (980~992) 13 986,
3406 01:54:28.240704 TX Bit7 (985~1000) 16 992, Bit15 (974~985) 12 979,
3407 01:54:28.240780
3408 01:54:28.240846 Write Rank1 MR14 =0x2
3409 01:54:28.250648
3410 01:54:28.250735 CH=1, VrefRange= 0, VrefLevel = 2
3411 01:54:28.257270 TX Bit0 (986~1001) 16 993, Bit8 (977~991) 15 984,
3412 01:54:28.260892 TX Bit1 (985~999) 15 992, Bit9 (977~988) 12 982,
3413 01:54:28.267127 TX Bit2 (983~999) 17 991, Bit10 (979~993) 15 986,
3414 01:54:28.270159 TX Bit3 (982~996) 15 989, Bit11 (980~993) 14 986,
3415 01:54:28.273145 TX Bit4 (985~1000) 16 992, Bit12 (980~993) 14 986,
3416 01:54:28.279891 TX Bit5 (986~1000) 15 993, Bit13 (980~994) 15 987,
3417 01:54:28.283585 TX Bit6 (985~1000) 16 992, Bit14 (979~992) 14 985,
3418 01:54:28.289819 TX Bit7 (985~1000) 16 992, Bit15 (973~985) 13 979,
3419 01:54:28.289896
3420 01:54:28.289998 Write Rank1 MR14 =0x4
3421 01:54:28.299787
3422 01:54:28.299863 CH=1, VrefRange= 0, VrefLevel = 4
3423 01:54:28.305836 TX Bit0 (985~1001) 17 993, Bit8 (976~992) 17 984,
3424 01:54:28.309344 TX Bit1 (985~1000) 16 992, Bit9 (977~990) 14 983,
3425 01:54:28.316229 TX Bit2 (984~999) 16 991, Bit10 (979~993) 15 986,
3426 01:54:28.319156 TX Bit3 (981~997) 17 989, Bit11 (980~994) 15 987,
3427 01:54:28.325448 TX Bit4 (985~1001) 17 993, Bit12 (980~993) 14 986,
3428 01:54:28.328709 TX Bit5 (985~1001) 17 993, Bit13 (980~994) 15 987,
3429 01:54:28.332280 TX Bit6 (984~1001) 18 992, Bit14 (979~993) 15 986,
3430 01:54:28.338686 TX Bit7 (985~1001) 17 993, Bit15 (973~986) 14 979,
3431 01:54:28.338763
3432 01:54:28.338823 Write Rank1 MR14 =0x6
3433 01:54:28.348699
3434 01:54:28.348764 CH=1, VrefRange= 0, VrefLevel = 6
3435 01:54:28.355196 TX Bit0 (985~1002) 18 993, Bit8 (976~992) 17 984,
3436 01:54:28.358488 TX Bit1 (984~1001) 18 992, Bit9 (976~991) 16 983,
3437 01:54:28.365397 TX Bit2 (983~1000) 18 991, Bit10 (978~994) 17 986,
3438 01:54:28.368684 TX Bit3 (981~998) 18 989, Bit11 (979~994) 16 986,
3439 01:54:28.375208 TX Bit4 (984~1002) 19 993, Bit12 (980~994) 15 987,
3440 01:54:28.378318 TX Bit5 (985~1002) 18 993, Bit13 (979~996) 18 987,
3441 01:54:28.382029 TX Bit6 (984~1002) 19 993, Bit14 (979~993) 15 986,
3442 01:54:28.388472 TX Bit7 (985~1002) 18 993, Bit15 (972~987) 16 979,
3443 01:54:28.388564
3444 01:54:28.388648 Write Rank1 MR14 =0x8
3445 01:54:28.399068
3446 01:54:28.399132 CH=1, VrefRange= 0, VrefLevel = 8
3447 01:54:28.405348 TX Bit0 (985~1004) 20 994, Bit8 (976~992) 17 984,
3448 01:54:28.408588 TX Bit1 (984~1002) 19 993, Bit9 (977~991) 15 984,
3449 01:54:28.415168 TX Bit2 (983~1000) 18 991, Bit10 (978~994) 17 986,
3450 01:54:28.418235 TX Bit3 (981~998) 18 989, Bit11 (979~995) 17 987,
3451 01:54:28.425141 TX Bit4 (984~1002) 19 993, Bit12 (979~995) 17 987,
3452 01:54:28.428201 TX Bit5 (985~1003) 19 994, Bit13 (979~996) 18 987,
3453 01:54:28.431529 TX Bit6 (984~1003) 20 993, Bit14 (978~994) 17 986,
3454 01:54:28.437975 TX Bit7 (984~1003) 20 993, Bit15 (972~988) 17 980,
3455 01:54:28.438062
3456 01:54:28.438122 Write Rank1 MR14 =0xa
3457 01:54:28.448137
3458 01:54:28.451421 CH=1, VrefRange= 0, VrefLevel = 10
3459 01:54:28.454791 TX Bit0 (985~1004) 20 994, Bit8 (976~993) 18 984,
3460 01:54:28.458035 TX Bit1 (984~1003) 20 993, Bit9 (976~992) 17 984,
3461 01:54:28.464538 TX Bit2 (983~1001) 19 992, Bit10 (978~994) 17 986,
3462 01:54:28.467682 TX Bit3 (980~999) 20 989, Bit11 (979~996) 18 987,
3463 01:54:28.474281 TX Bit4 (984~1003) 20 993, Bit12 (978~996) 19 987,
3464 01:54:28.477538 TX Bit5 (985~1004) 20 994, Bit13 (979~997) 19 988,
3465 01:54:28.480857 TX Bit6 (984~1004) 21 994, Bit14 (978~994) 17 986,
3466 01:54:28.487487 TX Bit7 (984~1003) 20 993, Bit15 (972~990) 19 981,
3467 01:54:28.487553
3468 01:54:28.487609 Write Rank1 MR14 =0xc
3469 01:54:28.498347
3470 01:54:28.501670 CH=1, VrefRange= 0, VrefLevel = 12
3471 01:54:28.505058 TX Bit0 (985~1005) 21 995, Bit8 (976~993) 18 984,
3472 01:54:28.508274 TX Bit1 (984~1004) 21 994, Bit9 (976~992) 17 984,
3473 01:54:28.514443 TX Bit2 (982~1002) 21 992, Bit10 (978~995) 18 986,
3474 01:54:28.518262 TX Bit3 (980~999) 20 989, Bit11 (978~997) 20 987,
3475 01:54:28.524135 TX Bit4 (984~1004) 21 994, Bit12 (978~996) 19 987,
3476 01:54:28.527451 TX Bit5 (985~1005) 21 995, Bit13 (979~998) 20 988,
3477 01:54:28.531028 TX Bit6 (984~1004) 21 994, Bit14 (978~995) 18 986,
3478 01:54:28.537250 TX Bit7 (984~1004) 21 994, Bit15 (972~990) 19 981,
3479 01:54:28.537320
3480 01:54:28.537394 Write Rank1 MR14 =0xe
3481 01:54:28.548340
3482 01:54:28.551225 CH=1, VrefRange= 0, VrefLevel = 14
3483 01:54:28.554734 TX Bit0 (985~1005) 21 995, Bit8 (974~993) 20 983,
3484 01:54:28.558335 TX Bit1 (984~1004) 21 994, Bit9 (975~992) 18 983,
3485 01:54:28.564383 TX Bit2 (983~1002) 20 992, Bit10 (977~996) 20 986,
3486 01:54:28.568060 TX Bit3 (979~999) 21 989, Bit11 (978~997) 20 987,
3487 01:54:28.574492 TX Bit4 (984~1005) 22 994, Bit12 (978~997) 20 987,
3488 01:54:28.577961 TX Bit5 (984~1005) 22 994, Bit13 (978~998) 21 988,
3489 01:54:28.581207 TX Bit6 (984~1005) 22 994, Bit14 (977~995) 19 986,
3490 01:54:28.587178 TX Bit7 (984~1004) 21 994, Bit15 (971~991) 21 981,
3491 01:54:28.587255
3492 01:54:28.587315 Write Rank1 MR14 =0x10
3493 01:54:28.598539
3494 01:54:28.601579 CH=1, VrefRange= 0, VrefLevel = 16
3495 01:54:28.604727 TX Bit0 (985~1006) 22 995, Bit8 (975~994) 20 984,
3496 01:54:28.608114 TX Bit1 (984~1005) 22 994, Bit9 (975~992) 18 983,
3497 01:54:28.615224 TX Bit2 (982~1003) 22 992, Bit10 (977~997) 21 987,
3498 01:54:28.618076 TX Bit3 (979~1000) 22 989, Bit11 (978~998) 21 988,
3499 01:54:28.624816 TX Bit4 (983~1005) 23 994, Bit12 (978~998) 21 988,
3500 01:54:28.628146 TX Bit5 (984~1006) 23 995, Bit13 (978~999) 22 988,
3501 01:54:28.631381 TX Bit6 (984~1005) 22 994, Bit14 (977~997) 21 987,
3502 01:54:28.637954 TX Bit7 (984~1005) 22 994, Bit15 (971~991) 21 981,
3503 01:54:28.638030
3504 01:54:28.638090 Write Rank1 MR14 =0x12
3505 01:54:28.648447
3506 01:54:28.652085 CH=1, VrefRange= 0, VrefLevel = 18
3507 01:54:28.655256 TX Bit0 (984~1006) 23 995, Bit8 (974~995) 22 984,
3508 01:54:28.658735 TX Bit1 (983~1005) 23 994, Bit9 (974~993) 20 983,
3509 01:54:28.665273 TX Bit2 (981~1003) 23 992, Bit10 (977~998) 22 987,
3510 01:54:28.668191 TX Bit3 (978~1001) 24 989, Bit11 (977~999) 23 988,
3511 01:54:28.675261 TX Bit4 (983~1005) 23 994, Bit12 (978~998) 21 988,
3512 01:54:28.677999 TX Bit5 (984~1006) 23 995, Bit13 (978~999) 22 988,
3513 01:54:28.681725 TX Bit6 (983~1006) 24 994, Bit14 (977~998) 22 987,
3514 01:54:28.687722 TX Bit7 (984~1005) 22 994, Bit15 (971~992) 22 981,
3515 01:54:28.687822
3516 01:54:28.691000 Write Rank1 MR14 =0x14
3517 01:54:28.698674
3518 01:54:28.702420 CH=1, VrefRange= 0, VrefLevel = 20
3519 01:54:28.705633 TX Bit0 (984~1006) 23 995, Bit8 (973~995) 23 984,
3520 01:54:28.708902 TX Bit1 (983~1006) 24 994, Bit9 (974~993) 20 983,
3521 01:54:28.715168 TX Bit2 (980~1005) 26 992, Bit10 (977~998) 22 987,
3522 01:54:28.718422 TX Bit3 (978~1001) 24 989, Bit11 (977~999) 23 988,
3523 01:54:28.725191 TX Bit4 (983~1006) 24 994, Bit12 (977~999) 23 988,
3524 01:54:28.728648 TX Bit5 (984~1006) 23 995, Bit13 (978~999) 22 988,
3525 01:54:28.731726 TX Bit6 (983~1006) 24 994, Bit14 (976~998) 23 987,
3526 01:54:28.738402 TX Bit7 (983~1006) 24 994, Bit15 (971~992) 22 981,
3527 01:54:28.738479
3528 01:54:28.738538 Write Rank1 MR14 =0x16
3529 01:54:28.748903
3530 01:54:28.752223 CH=1, VrefRange= 0, VrefLevel = 22
3531 01:54:28.755560 TX Bit0 (984~1006) 23 995, Bit8 (973~996) 24 984,
3532 01:54:28.759216 TX Bit1 (983~1006) 24 994, Bit9 (973~994) 22 983,
3533 01:54:28.765163 TX Bit2 (980~1005) 26 992, Bit10 (976~999) 24 987,
3534 01:54:28.768927 TX Bit3 (978~1002) 25 990, Bit11 (977~999) 23 988,
3535 01:54:28.775631 TX Bit4 (982~1006) 25 994, Bit12 (977~999) 23 988,
3536 01:54:28.778878 TX Bit5 (984~1006) 23 995, Bit13 (977~1000) 24 988,
3537 01:54:28.781570 TX Bit6 (983~1006) 24 994, Bit14 (977~998) 22 987,
3538 01:54:28.788920 TX Bit7 (983~1006) 24 994, Bit15 (971~992) 22 981,
3539 01:54:28.789011
3540 01:54:28.791602 Write Rank1 MR14 =0x18
3541 01:54:28.799504
3542 01:54:28.802935 CH=1, VrefRange= 0, VrefLevel = 24
3543 01:54:28.806307 TX Bit0 (984~1007) 24 995, Bit8 (972~996) 25 984,
3544 01:54:28.809466 TX Bit1 (983~1006) 24 994, Bit9 (973~994) 22 983,
3545 01:54:28.815970 TX Bit2 (981~1005) 25 993, Bit10 (976~999) 24 987,
3546 01:54:28.819401 TX Bit3 (978~1002) 25 990, Bit11 (976~999) 24 987,
3547 01:54:28.825632 TX Bit4 (982~1006) 25 994, Bit12 (977~1000) 24 988,
3548 01:54:28.829167 TX Bit5 (984~1007) 24 995, Bit13 (977~1000) 24 988,
3549 01:54:28.832696 TX Bit6 (983~1006) 24 994, Bit14 (976~999) 24 987,
3550 01:54:28.839108 TX Bit7 (984~1006) 23 995, Bit15 (971~993) 23 982,
3551 01:54:28.839179
3552 01:54:28.842342 Write Rank1 MR14 =0x1a
3553 01:54:28.850283
3554 01:54:28.853830 CH=1, VrefRange= 0, VrefLevel = 26
3555 01:54:28.857023 TX Bit0 (984~1007) 24 995, Bit8 (972~996) 25 984,
3556 01:54:28.860243 TX Bit1 (982~1006) 25 994, Bit9 (972~994) 23 983,
3557 01:54:28.867004 TX Bit2 (980~1005) 26 992, Bit10 (975~999) 25 987,
3558 01:54:28.869915 TX Bit3 (978~1003) 26 990, Bit11 (976~1000) 25 988,
3559 01:54:28.876354 TX Bit4 (982~1007) 26 994, Bit12 (977~1000) 24 988,
3560 01:54:28.879547 TX Bit5 (984~1007) 24 995, Bit13 (977~1000) 24 988,
3561 01:54:28.886187 TX Bit6 (982~1006) 25 994, Bit14 (976~999) 24 987,
3562 01:54:28.889524 TX Bit7 (983~1006) 24 994, Bit15 (970~993) 24 981,
3563 01:54:28.889647
3564 01:54:28.892772 Write Rank1 MR14 =0x1c
3565 01:54:28.901178
3566 01:54:28.904424 CH=1, VrefRange= 0, VrefLevel = 28
3567 01:54:28.907614 TX Bit0 (984~1007) 24 995, Bit8 (972~996) 25 984,
3568 01:54:28.910852 TX Bit1 (982~1006) 25 994, Bit9 (972~995) 24 983,
3569 01:54:28.917139 TX Bit2 (979~1006) 28 992, Bit10 (975~1000) 26 987,
3570 01:54:28.920896 TX Bit3 (978~1003) 26 990, Bit11 (976~999) 24 987,
3571 01:54:28.926910 TX Bit4 (982~1006) 25 994, Bit12 (976~1000) 25 988,
3572 01:54:28.930203 TX Bit5 (983~1007) 25 995, Bit13 (977~1000) 24 988,
3573 01:54:28.937051 TX Bit6 (982~1007) 26 994, Bit14 (975~1000) 26 987,
3574 01:54:28.939999 TX Bit7 (982~1007) 26 994, Bit15 (970~993) 24 981,
3575 01:54:28.940076
3576 01:54:28.943343 Write Rank1 MR14 =0x1e
3577 01:54:28.951572
3578 01:54:28.954778 CH=1, VrefRange= 0, VrefLevel = 30
3579 01:54:28.958473 TX Bit0 (984~1007) 24 995, Bit8 (972~996) 25 984,
3580 01:54:28.961339 TX Bit1 (982~1006) 25 994, Bit9 (972~995) 24 983,
3581 01:54:28.968390 TX Bit2 (979~1006) 28 992, Bit10 (975~1000) 26 987,
3582 01:54:28.971817 TX Bit3 (978~1003) 26 990, Bit11 (976~999) 24 987,
3583 01:54:28.978180 TX Bit4 (982~1006) 25 994, Bit12 (976~1000) 25 988,
3584 01:54:28.981275 TX Bit5 (983~1007) 25 995, Bit13 (977~1000) 24 988,
3585 01:54:28.987703 TX Bit6 (982~1007) 26 994, Bit14 (975~1000) 26 987,
3586 01:54:28.991194 TX Bit7 (982~1007) 26 994, Bit15 (970~993) 24 981,
3587 01:54:28.991271
3588 01:54:28.994483 Write Rank1 MR14 =0x20
3589 01:54:29.002466
3590 01:54:29.005791 CH=1, VrefRange= 0, VrefLevel = 32
3591 01:54:29.009347 TX Bit0 (984~1007) 24 995, Bit8 (972~996) 25 984,
3592 01:54:29.012676 TX Bit1 (982~1006) 25 994, Bit9 (972~995) 24 983,
3593 01:54:29.019042 TX Bit2 (979~1006) 28 992, Bit10 (975~1000) 26 987,
3594 01:54:29.022289 TX Bit3 (978~1003) 26 990, Bit11 (976~999) 24 987,
3595 01:54:29.028736 TX Bit4 (982~1006) 25 994, Bit12 (976~1000) 25 988,
3596 01:54:29.032026 TX Bit5 (983~1007) 25 995, Bit13 (977~1000) 24 988,
3597 01:54:29.035915 TX Bit6 (982~1007) 26 994, Bit14 (975~1000) 26 987,
3598 01:54:29.042003 TX Bit7 (982~1007) 26 994, Bit15 (970~993) 24 981,
3599 01:54:29.042080
3600 01:54:29.045155 Write Rank1 MR14 =0x22
3601 01:54:29.053510
3602 01:54:29.056930 CH=1, VrefRange= 0, VrefLevel = 34
3603 01:54:29.060550 TX Bit0 (984~1007) 24 995, Bit8 (972~996) 25 984,
3604 01:54:29.063566 TX Bit1 (982~1006) 25 994, Bit9 (972~995) 24 983,
3605 01:54:29.070015 TX Bit2 (979~1006) 28 992, Bit10 (975~1000) 26 987,
3606 01:54:29.073094 TX Bit3 (978~1003) 26 990, Bit11 (976~999) 24 987,
3607 01:54:29.079910 TX Bit4 (982~1006) 25 994, Bit12 (976~1000) 25 988,
3608 01:54:29.083467 TX Bit5 (983~1007) 25 995, Bit13 (977~1000) 24 988,
3609 01:54:29.086431 TX Bit6 (982~1007) 26 994, Bit14 (975~1000) 26 987,
3610 01:54:29.093265 TX Bit7 (982~1007) 26 994, Bit15 (970~993) 24 981,
3611 01:54:29.093342
3612 01:54:29.096531 Write Rank1 MR14 =0x24
3613 01:54:29.104568
3614 01:54:29.107866 CH=1, VrefRange= 0, VrefLevel = 36
3615 01:54:29.111207 TX Bit0 (984~1007) 24 995, Bit8 (972~996) 25 984,
3616 01:54:29.114507 TX Bit1 (982~1006) 25 994, Bit9 (972~995) 24 983,
3617 01:54:29.120880 TX Bit2 (979~1006) 28 992, Bit10 (975~1000) 26 987,
3618 01:54:29.124076 TX Bit3 (978~1003) 26 990, Bit11 (976~999) 24 987,
3619 01:54:29.130560 TX Bit4 (982~1006) 25 994, Bit12 (976~1000) 25 988,
3620 01:54:29.133829 TX Bit5 (983~1007) 25 995, Bit13 (977~1000) 24 988,
3621 01:54:29.137121 TX Bit6 (982~1007) 26 994, Bit14 (975~1000) 26 987,
3622 01:54:29.143653 TX Bit7 (982~1007) 26 994, Bit15 (970~993) 24 981,
3623 01:54:29.143767
3624 01:54:29.143827
3625 01:54:29.147264 TX Vref found, early break! 378< 382
3626 01:54:29.150523 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =753/100 ps
3627 01:54:29.153688 u1DelayCellOfst[0]=6 cells (5 PI)
3628 01:54:29.157306 u1DelayCellOfst[1]=5 cells (4 PI)
3629 01:54:29.159979 u1DelayCellOfst[2]=2 cells (2 PI)
3630 01:54:29.163892 u1DelayCellOfst[3]=0 cells (0 PI)
3631 01:54:29.167138 u1DelayCellOfst[4]=5 cells (4 PI)
3632 01:54:29.169796 u1DelayCellOfst[5]=6 cells (5 PI)
3633 01:54:29.173184 u1DelayCellOfst[6]=5 cells (4 PI)
3634 01:54:29.176879 u1DelayCellOfst[7]=5 cells (4 PI)
3635 01:54:29.180182 Byte0, DQ PI dly=990, DQM PI dly= 992
3636 01:54:29.183283 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 30)
3637 01:54:29.183363
3638 01:54:29.189896 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 30)
3639 01:54:29.189977
3640 01:54:29.193345 u1DelayCellOfst[8]=3 cells (3 PI)
3641 01:54:29.193424 u1DelayCellOfst[9]=2 cells (2 PI)
3642 01:54:29.196321 u1DelayCellOfst[10]=7 cells (6 PI)
3643 01:54:29.199291 u1DelayCellOfst[11]=7 cells (6 PI)
3644 01:54:29.202903 u1DelayCellOfst[12]=9 cells (7 PI)
3645 01:54:29.206283 u1DelayCellOfst[13]=9 cells (7 PI)
3646 01:54:29.209414 u1DelayCellOfst[14]=7 cells (6 PI)
3647 01:54:29.212583 u1DelayCellOfst[15]=0 cells (0 PI)
3648 01:54:29.215746 Byte1, DQ PI dly=981, DQM PI dly= 984
3649 01:54:29.219010 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 21)
3650 01:54:29.222750
3651 01:54:29.225798 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 21)
3652 01:54:29.225876
3653 01:54:29.225935 Write Rank1 MR14 =0x1c
3654 01:54:29.229338
3655 01:54:29.229438 Final TX Range 0 Vref 28
3656 01:54:29.229523
3657 01:54:29.235760 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
3658 01:54:29.235838
3659 01:54:29.242294 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3660 01:54:29.248913 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3661 01:54:29.258851 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3662 01:54:29.258928 Write Rank1 MR3 =0xb0
3663 01:54:29.261810 DramC Write-DBI on
3664 01:54:29.261886 ==
3665 01:54:29.264839 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3666 01:54:29.268643 fsp= 1, odt_onoff= 1, Byte mode= 0
3667 01:54:29.268721 ==
3668 01:54:29.274770 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
3669 01:54:29.274846
3670 01:54:29.274906 Begin, DQ Scan Range 704~768
3671 01:54:29.278110
3672 01:54:29.278185
3673 01:54:29.278244 TX Vref Scan disable
3674 01:54:29.281754 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
3675 01:54:29.285115 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
3676 01:54:29.287835 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
3677 01:54:29.291114 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
3678 01:54:29.294401 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
3679 01:54:29.300951 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
3680 01:54:29.304190 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
3681 01:54:29.307730 711 |2 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
3682 01:54:29.310767 712 |2 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
3683 01:54:29.314314 713 |2 6 9|[0] xxxxxxxx xxxxxxxx [MSB]
3684 01:54:29.317815 714 |2 6 10|[0] xxxxxxxx xxxxxxxx [MSB]
3685 01:54:29.320904 715 |2 6 11|[0] xxxxxxxx xxxxxxxx [MSB]
3686 01:54:29.324311 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
3687 01:54:29.327548 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB]
3688 01:54:29.331035 718 |2 6 14|[0] xxxxxxxx oooooooo [MSB]
3689 01:54:29.333999 719 |2 6 15|[0] xxxxxxxx oooooooo [MSB]
3690 01:54:29.336925 720 |2 6 16|[0] xxxxxxxx oooooooo [MSB]
3691 01:54:29.340570 721 |2 6 17|[0] xxxxxxxx oooooooo [MSB]
3692 01:54:29.344060 722 |2 6 18|[0] xxxxxxxx oooooooo [MSB]
3693 01:54:29.350634 723 |2 6 19|[0] xxxxxxxx oooooooo [MSB]
3694 01:54:29.353875 724 |2 6 20|[0] xxxxxxxx oooooooo [MSB]
3695 01:54:29.357198 725 |2 6 21|[0] xxxxxxxx oooooooo [MSB]
3696 01:54:29.360322 726 |2 6 22|[0] xxxxxxxx oooooooo [MSB]
3697 01:54:29.367072 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
3698 01:54:29.370190 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB]
3699 01:54:29.373231 745 |2 6 41|[0] oooooooo xxxxxxxx [MSB]
3700 01:54:29.376846 746 |2 6 42|[0] oooooooo xxxxxxxx [MSB]
3701 01:54:29.380404 747 |2 6 43|[0] oooooooo xxxxxxxx [MSB]
3702 01:54:29.383450 748 |2 6 44|[0] oooooooo xxxxxxxx [MSB]
3703 01:54:29.386877 749 |2 6 45|[0] oooooooo xxxxxxxx [MSB]
3704 01:54:29.390085 750 |2 6 46|[0] oooooooo xxxxxxxx [MSB]
3705 01:54:29.393377 751 |2 6 47|[0] oooooooo xxxxxxxx [MSB]
3706 01:54:29.396053 752 |2 6 48|[0] oooooooo xxxxxxxx [MSB]
3707 01:54:29.399327 753 |2 6 49|[0] xxxxxxxx xxxxxxxx [MSB]
3708 01:54:29.402729 Byte0, DQ PI dly=739, DQM PI dly= 739
3709 01:54:29.409209 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 35)
3710 01:54:29.409317
3711 01:54:29.412464 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 35)
3712 01:54:29.412563
3713 01:54:29.416207 Byte1, DQ PI dly=729, DQM PI dly= 729
3714 01:54:29.419447 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 25)
3715 01:54:29.422721
3716 01:54:29.426065 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 25)
3717 01:54:29.426134
3718 01:54:29.432117 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
3719 01:54:29.439110 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3720 01:54:29.445726 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3721 01:54:29.448880 Write Rank1 MR3 =0x30
3722 01:54:29.448956 DramC Write-DBI off
3723 01:54:29.449014
3724 01:54:29.451854 [DATLAT]
3725 01:54:29.455413 Freq=1600, CH1 RK1, use_rxtx_scan=0
3726 01:54:29.455490
3727 01:54:29.455548 DATLAT Default: 0x10
3728 01:54:29.458289 7, 0xFFFF, sum=0
3729 01:54:29.458366 8, 0xFFFF, sum=0
3730 01:54:29.461880 9, 0xFFFF, sum=0
3731 01:54:29.461973 10, 0xFFFF, sum=0
3732 01:54:29.464848 11, 0xFFFF, sum=0
3733 01:54:29.464931 12, 0xFFFF, sum=0
3734 01:54:29.468301 13, 0xFFFF, sum=0
3735 01:54:29.468390 14, 0x0, sum=1
3736 01:54:29.468460 15, 0x0, sum=2
3737 01:54:29.471692 16, 0x0, sum=3
3738 01:54:29.471781 17, 0x0, sum=4
3739 01:54:29.478327 pattern=2 first_step=14 total pass=5 best_step=16
3740 01:54:29.478404 ==
3741 01:54:29.481360 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3742 01:54:29.484962 fsp= 1, odt_onoff= 1, Byte mode= 0
3743 01:54:29.485039 ==
3744 01:54:29.491024 Start DQ dly to find pass range UseTestEngine =1
3745 01:54:29.494472 x-axis: bit #, y-axis: DQ dly (-127~63)
3746 01:54:29.494549 RX Vref Scan = 0
3747 01:54:29.498176 -26, [0] xxxxxxxx xxxxxxxx [MSB]
3748 01:54:29.501494 -25, [0] xxxxxxxx xxxxxxxx [MSB]
3749 01:54:29.505019 -24, [0] xxxxxxxx xxxxxxxx [MSB]
3750 01:54:29.508672 -23, [0] xxxxxxxx xxxxxxxx [MSB]
3751 01:54:29.512170 -22, [0] xxxxxxxx xxxxxxxx [MSB]
3752 01:54:29.512647 -21, [0] xxxxxxxx xxxxxxxx [MSB]
3753 01:54:29.515430 -20, [0] xxxxxxxx xxxxxxxx [MSB]
3754 01:54:29.518294 -19, [0] xxxxxxxx xxxxxxxx [MSB]
3755 01:54:29.521336 -18, [0] xxxxxxxx xxxxxxxx [MSB]
3756 01:54:29.524400 -17, [0] xxxxxxxx xxxxxxxx [MSB]
3757 01:54:29.528341 -16, [0] xxxxxxxx xxxxxxxx [MSB]
3758 01:54:29.531632 -15, [0] xxxxxxxx xxxxxxxx [MSB]
3759 01:54:29.534327 -14, [0] xxxxxxxx xxxxxxxx [MSB]
3760 01:54:29.537761 -13, [0] xxxxxxxx xxxxxxxx [MSB]
3761 01:54:29.540854 -12, [0] xxxxxxxx xxxxxxxx [MSB]
3762 01:54:29.541446 -11, [0] xxxxxxxx xxxxxxxx [MSB]
3763 01:54:29.543985 -10, [0] xxxxxxxx xxxxxxxx [MSB]
3764 01:54:29.547912 -9, [0] xxxxxxxx xxxxxxxx [MSB]
3765 01:54:29.550609 -8, [0] xxxxxxxx xxxxxxxx [MSB]
3766 01:54:29.553828 -7, [0] xxxxxxxx xxxxxxxx [MSB]
3767 01:54:29.557286 -6, [0] xxxxxxxx xxxxxxxx [MSB]
3768 01:54:29.560697 -5, [0] xxxxxxxx xxxxxxxx [MSB]
3769 01:54:29.563917 -4, [0] xxxxxxxx xxxxxxxx [MSB]
3770 01:54:29.564380 -3, [0] xxxxxxxx xxxxxxxx [MSB]
3771 01:54:29.567175 -2, [0] xxxxxxxx xxxxxxxo [MSB]
3772 01:54:29.570523 -1, [0] xxxxxxxx xxxxxxxo [MSB]
3773 01:54:29.574064 0, [0] xxxoxxxx xxxxxxxo [MSB]
3774 01:54:29.576977 1, [0] xxxoxxxx ooxxxxxo [MSB]
3775 01:54:29.580859 2, [0] xoooxxxx ooxxxxxo [MSB]
3776 01:54:29.581257 3, [0] xooooxxx ooxxxxxo [MSB]
3777 01:54:29.583971 4, [0] xooooxxo oooxxxxo [MSB]
3778 01:54:29.586758 5, [0] ooooooxo oooxxxxo [MSB]
3779 01:54:29.589915 6, [0] ooooooxo ooooxooo [MSB]
3780 01:54:29.594080 32, [0] oooxoooo ooooooox [MSB]
3781 01:54:29.597290 33, [0] oooxoooo ooooooox [MSB]
3782 01:54:29.600336 34, [0] oooxoooo ooooooox [MSB]
3783 01:54:29.604159 35, [0] ooxxoooo xxooooox [MSB]
3784 01:54:29.607474 36, [0] ooxxoooo xxooooox [MSB]
3785 01:54:29.610418 37, [0] ooxxoooo xxooooox [MSB]
3786 01:54:29.613434 38, [0] oxxxooox xxxoooox [MSB]
3787 01:54:29.613890 39, [0] xxxxxoox xxxoxxox [MSB]
3788 01:54:29.616796 40, [0] xxxxxoox xxxxxxxx [MSB]
3789 01:54:29.620407 41, [0] xxxxxxxx xxxxxxxx [MSB]
3790 01:54:29.623414 iDelay=41, Bit 0, Center 21 (5 ~ 38) 34
3791 01:54:29.627165 iDelay=41, Bit 1, Center 19 (2 ~ 37) 36
3792 01:54:29.630462 iDelay=41, Bit 2, Center 18 (2 ~ 34) 33
3793 01:54:29.633601 iDelay=41, Bit 3, Center 15 (0 ~ 31) 32
3794 01:54:29.640573 iDelay=41, Bit 4, Center 20 (3 ~ 38) 36
3795 01:54:29.643085 iDelay=41, Bit 5, Center 22 (5 ~ 40) 36
3796 01:54:29.646361 iDelay=41, Bit 6, Center 23 (7 ~ 40) 34
3797 01:54:29.650041 iDelay=41, Bit 7, Center 20 (4 ~ 37) 34
3798 01:54:29.653535 iDelay=41, Bit 8, Center 17 (1 ~ 34) 34
3799 01:54:29.657001 iDelay=41, Bit 9, Center 17 (1 ~ 34) 34
3800 01:54:29.659971 iDelay=41, Bit 10, Center 20 (4 ~ 37) 34
3801 01:54:29.663583 iDelay=41, Bit 11, Center 22 (6 ~ 39) 34
3802 01:54:29.666507 iDelay=41, Bit 12, Center 22 (7 ~ 38) 32
3803 01:54:29.669521 iDelay=41, Bit 13, Center 22 (6 ~ 38) 33
3804 01:54:29.672679 iDelay=41, Bit 14, Center 22 (6 ~ 39) 34
3805 01:54:29.679747 iDelay=41, Bit 15, Center 14 (-2 ~ 31) 34
3806 01:54:29.680384 ==
3807 01:54:29.682847 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3808 01:54:29.685993 fsp= 1, odt_onoff= 1, Byte mode= 0
3809 01:54:29.686429 ==
3810 01:54:29.689490 DQS Delay:
3811 01:54:29.690065 DQS0 = 0, DQS1 = 0
3812 01:54:29.690411 DQM Delay:
3813 01:54:29.692177 DQM0 = 19, DQM1 = 19
3814 01:54:29.692609 DQ Delay:
3815 01:54:29.695540 DQ0 =21, DQ1 =19, DQ2 =18, DQ3 =15
3816 01:54:29.698916 DQ4 =20, DQ5 =22, DQ6 =23, DQ7 =20
3817 01:54:29.702243 DQ8 =17, DQ9 =17, DQ10 =20, DQ11 =22
3818 01:54:29.706003 DQ12 =22, DQ13 =22, DQ14 =22, DQ15 =14
3819 01:54:29.706529
3820 01:54:29.707005
3821 01:54:29.707461
3822 01:54:29.709111 [DramC_TX_OE_Calibration] TA2
3823 01:54:29.711963 Original DQ_B0 (3 6) =30, OEN = 27
3824 01:54:29.715830 Original DQ_B1 (3 6) =30, OEN = 27
3825 01:54:29.718891 23, 0x0, End_B0=23 End_B1=23
3826 01:54:29.722443 24, 0x0, End_B0=24 End_B1=24
3827 01:54:29.722966 25, 0x0, End_B0=25 End_B1=25
3828 01:54:29.725096 26, 0x0, End_B0=26 End_B1=26
3829 01:54:29.728488 27, 0x0, End_B0=27 End_B1=27
3830 01:54:29.731725 28, 0x0, End_B0=28 End_B1=28
3831 01:54:29.735081 29, 0x0, End_B0=29 End_B1=29
3832 01:54:29.735525 30, 0x0, End_B0=30 End_B1=30
3833 01:54:29.738494 31, 0xFFFF, End_B0=30 End_B1=30
3834 01:54:29.744893 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3835 01:54:29.751215 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3836 01:54:29.751607
3837 01:54:29.751909
3838 01:54:29.752189 Write Rank1 MR23 =0x3f
3839 01:54:29.754523 [DQSOSC]
3840 01:54:29.761233 [DQSOSCAuto] RK1, (LSB)MR18= 0xb2b2, (MSB)MR19= 0x202, tDQSOscB0 = 456 ps tDQSOscB1 = 456 ps
3841 01:54:29.768252 CH1_RK1: MR19=0x202, MR18=0xB2B2, DQSOSC=456, MR23=63, INC=11, DEC=17
3842 01:54:29.771415 Write Rank1 MR23 =0x3f
3843 01:54:29.771845 [DQSOSC]
3844 01:54:29.777436 [DQSOSCAuto] RK1, (LSB)MR18= 0xb1b1, (MSB)MR19= 0x202, tDQSOscB0 = 457 ps tDQSOscB1 = 457 ps
3845 01:54:29.781048 CH1 RK1: MR19=202, MR18=B1B1
3846 01:54:29.784137 [RxdqsGatingPostProcess] freq 1600
3847 01:54:29.790886 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
3848 01:54:29.791401 Rank: 0
3849 01:54:29.794216 best DQS0 dly(2T, 0.5T) = (2, 6)
3850 01:54:29.797624 best DQS1 dly(2T, 0.5T) = (2, 6)
3851 01:54:29.800609 best DQS0 P1 dly(2T, 0.5T) = (3, 2)
3852 01:54:29.804202 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
3853 01:54:29.804717 Rank: 1
3854 01:54:29.807244 best DQS0 dly(2T, 0.5T) = (2, 6)
3855 01:54:29.810742 best DQS1 dly(2T, 0.5T) = (2, 6)
3856 01:54:29.813961 best DQS0 P1 dly(2T, 0.5T) = (3, 2)
3857 01:54:29.817185 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
3858 01:54:29.820706 TX_dly_DQSgated check: min 2 max 3, ChangeDQSINCTL=-1
3859 01:54:29.824113 DQSINCTL=5, RANKINCTL=3, u4XRTR2R=9
3860 01:54:29.830255 [DualRankRxdatlatCal] RK0: 16, RK1: 16, Final_Datlat 16
3861 01:54:29.830760
3862 01:54:29.831095
3863 01:54:29.833179 [Calibration Summary] Freqency 1600
3864 01:54:29.833658 CH 0, Rank 0
3865 01:54:29.834007 All Pass.
3866 01:54:29.834316
3867 01:54:29.836885 CH 0, Rank 1
3868 01:54:29.837398 All Pass.
3869 01:54:29.837814
3870 01:54:29.839868 CH 1, Rank 0
3871 01:54:29.840296 All Pass.
3872 01:54:29.840631
3873 01:54:29.840943 CH 1, Rank 1
3874 01:54:29.842999 All Pass.
3875 01:54:29.843430
3876 01:54:29.849499 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3877 01:54:29.856246 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3878 01:54:29.863266 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3879 01:54:29.863708 Write Rank0 MR3 =0xb0
3880 01:54:29.869524 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3881 01:54:29.879312 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3882 01:54:29.886077 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3883 01:54:29.886589 Write Rank1 MR3 =0xb0
3884 01:54:29.892247 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3885 01:54:29.898740 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3886 01:54:29.908482 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3887 01:54:29.909058 Write Rank0 MR3 =0xb0
3888 01:54:29.915332 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3889 01:54:29.922047 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3890 01:54:29.928439 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3891 01:54:29.931942 Write Rank1 MR3 =0xb0
3892 01:54:29.935035 DramC Write-DBI on
3893 01:54:29.938584 [GetDramInforAfterCalByMRR] Vendor 6.
3894 01:54:29.941909 [GetDramInforAfterCalByMRR] Revision 505.
3895 01:54:29.942435 MR8 1111
3896 01:54:29.944476 CH0, RK0, DieNum 1, Density 80000000, RKsize 80000000.
3897 01:54:29.948543 MR8 1111
3898 01:54:29.951686 CH0, RK1, DieNum 1, Density 80000000, RKsize 80000000.
3899 01:54:29.952212 MR8 1111
3900 01:54:29.958233 CH1, RK0, DieNum 1, Density 80000000, RKsize 80000000.
3901 01:54:29.958758 MR8 1111
3902 01:54:29.964683 CH1, RK1, DieNum 1, Density 80000000, RKsize 80000000.
3903 01:54:29.970852 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 119, TRFCpb 44, TRFCpb_05T 0
3904 01:54:29.974661 Write Rank0 MR13 =0xd0
3905 01:54:29.977764 Write Rank1 MR13 =0xd0
3906 01:54:29.978194 Write Rank0 MR13 =0xd0
3907 01:54:29.981297 Write Rank1 MR13 =0xd0
3908 01:54:29.984447 Save calibration result to emmc
3909 01:54:29.984988
3910 01:54:29.985327
3911 01:54:29.987370 [DramcModeReg_Check] Freq_1600, FSP_1
3912 01:54:29.987799 FSP_1, CH_0, RK0
3913 01:54:29.990654 Write Rank0 MR13 =0xd8
3914 01:54:29.993703 MR12 = 0x5e (global = 0x5e) match
3915 01:54:29.997434 MR14 = 0x1e (global = 0x1e) match
3916 01:54:29.997992 FSP_1, CH_0, RK1
3917 01:54:30.000775 Write Rank1 MR13 =0xd8
3918 01:54:30.003496 MR12 = 0x5e (global = 0x5e) match
3919 01:54:30.006891 MR14 = 0x1c (global = 0x1c) match
3920 01:54:30.007376 FSP_1, CH_1, RK0
3921 01:54:30.010107 Write Rank0 MR13 =0xd8
3922 01:54:30.013384 MR12 = 0x60 (global = 0x60) match
3923 01:54:30.016849 MR14 = 0x1e (global = 0x1e) match
3924 01:54:30.020477 FSP_1, CH_1, RK1
3925 01:54:30.020988 Write Rank1 MR13 =0xd8
3926 01:54:30.023397 MR12 = 0x5c (global = 0x5c) match
3927 01:54:30.026461 MR14 = 0x1c (global = 0x1c) match
3928 01:54:30.026890
3929 01:54:30.030341 [MEM_TEST] 02: After DFS, before run time config
3930 01:54:30.042426 [MEM_TEST] Rank 0 OK.(uiFixedAddr 0x40000000, Pass count =16384, Fail count =0)
3931 01:54:30.042942
3932 01:54:30.043275 [TA2_TEST]
3933 01:54:30.043583 === TA2 HW
3934 01:54:30.045617 TA2 PAT: XTALK
3935 01:54:30.049396 HW channel(0) Rank(0), TA2 pass, pass_cnt:1, err_cnt:0
3936 01:54:30.055474 HW channel(0) Rank(1), TA2 pass, pass_cnt:2, err_cnt:0
3937 01:54:30.058558 HW channel(1) Rank(0), TA2 pass, pass_cnt:3, err_cnt:0
3938 01:54:30.065370 HW channel(1) Rank(1), TA2 pass, pass_cnt:4, err_cnt:0
3939 01:54:30.065938
3940 01:54:30.066376
3941 01:54:30.066783 Settings after calibration
3942 01:54:30.068360
3943 01:54:30.068795 [DramcRunTimeConfig]
3944 01:54:30.071370 TransferPLLToSPMControl - MODE SW PHYPLL
3945 01:54:30.074804 TX_TRACKING: ON
3946 01:54:30.075323 RX_TRACKING: ON
3947 01:54:30.075762 HW_GATING: ON
3948 01:54:30.078568 HW_GATING DBG: OFF
3949 01:54:30.079012 ddr_geometry:1
3950 01:54:30.081389 ddr_geometry:1
3951 01:54:30.081879 ddr_geometry:1
3952 01:54:30.084921 ddr_geometry:1
3953 01:54:30.085433 ddr_geometry:1
3954 01:54:30.088008 ddr_geometry:1
3955 01:54:30.088446 ddr_geometry:1
3956 01:54:30.088879 ddr_geometry:1
3957 01:54:30.091246 High Freq DUMMY_READ_FOR_TRACKING: ON
3958 01:54:30.094645 ZQCS_ENABLE_LP4: OFF
3959 01:54:30.098299 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
3960 01:54:30.101202 DUMMY_READ_FOR_DQS_GATING_RETRY: OFF
3961 01:54:30.104528 SPM_CONTROL_AFTERK: ON
3962 01:54:30.105039 IMPEDANCE_TRACKING: ON
3963 01:54:30.107469 TEMP_SENSOR: ON
3964 01:54:30.107913 PER_BANK_REFRESH: ON
3965 01:54:30.111180 HW_SAVE_FOR_SR: ON
3966 01:54:30.113870 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3967 01:54:30.117382 CLK_FREE_FUN_FOR_DRAMC_PSEL: ON
3968 01:54:30.120570 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: ON
3969 01:54:30.121085 Read ODT Tracking: ON
3970 01:54:30.123876 =========================
3971 01:54:30.124303
3972 01:54:30.124633 [TA2_TEST]
3973 01:54:30.127688 === TA2 HW
3974 01:54:30.130350 HW channel(0) Rank(0), TA2 pass, pass_cnt:5, err_cnt:0
3975 01:54:30.136932 HW channel(0) Rank(1), TA2 pass, pass_cnt:6, err_cnt:0
3976 01:54:30.140365 HW channel(1) Rank(0), TA2 pass, pass_cnt:7, err_cnt:0
3977 01:54:30.147138 HW channel(1) Rank(1), TA2 pass, pass_cnt:8, err_cnt:0
3978 01:54:30.147584
3979 01:54:30.150339 [MEM_TEST] 03: After run time config
3980 01:54:30.160424 [MEM_TEST] Rank 0 OK.(uiFixedAddr 0x40000000, Pass count =16384, Fail count =0)
3981 01:54:30.163385 [complex_mem_test] start addr:0x40024000, len:131072
3982 01:54:30.368144 1st complex R/W mem test pass
3983 01:54:30.374042 save_calibration_params with freq_sel:1, frequency:1600, _MappingFreqArray:0
3984 01:54:30.377987 sync preloader write leveling
3985 01:54:30.380812 sync preloader cbt_mr12
3986 01:54:30.383887 sync preloader cbt_clk_dly
3987 01:54:30.384345 sync preloader cbt_cmd_dly
3988 01:54:30.387359 sync preloader cbt_cs
3989 01:54:30.390650 sync preloader cbt_ca_perbit_delay
3990 01:54:30.393857 sync preloader clk_delay
3991 01:54:30.394298 sync preloader dqs_delay
3992 01:54:30.397135 sync preloader u1Gating2T_Save
3993 01:54:30.400658 sync preloader u1Gating05T_Save
3994 01:54:30.404074 sync preloader u1Gatingfine_tune_Save
3995 01:54:30.406802 sync preloader u1Gatingucpass_count_Save
3996 01:54:30.410261 sync preloader u1TxWindowPerbitVref_Save
3997 01:54:30.413576 sync preloader u1TxCenter_min_Save
3998 01:54:30.416855 sync preloader u1TxCenter_max_Save
3999 01:54:30.420384 sync preloader u1Txwin_center_Save
4000 01:54:30.423243 sync preloader u1Txfirst_pass_Save
4001 01:54:30.426513 sync preloader u1Txlast_pass_Save
4002 01:54:30.430383 sync preloader u1RxDatlat_Save
4003 01:54:30.433440 sync preloader u1RxWinPerbitVref_Save
4004 01:54:30.436808 sync preloader u1RxWinPerbitDQ_firsbypass_Save
4005 01:54:30.440233 sync preloader u1RxWinPerbitDQ_lastbypass_Save
4006 01:54:30.443302 sync preloader delay_cell_unit
4007 01:54:30.450044 save_calibration_params with freq_sel:3, frequency:1200, _MappingFreqArray:1
4008 01:54:30.452927 sync preloader write leveling
4009 01:54:30.456279 sync preloader cbt_mr12
4010 01:54:30.456706 sync preloader cbt_clk_dly
4011 01:54:30.459956 sync preloader cbt_cmd_dly
4012 01:54:30.462872 sync preloader cbt_cs
4013 01:54:30.466125 sync preloader cbt_ca_perbit_delay
4014 01:54:30.466625 sync preloader clk_delay
4015 01:54:30.469977 sync preloader dqs_delay
4016 01:54:30.473187 sync preloader u1Gating2T_Save
4017 01:54:30.476665 sync preloader u1Gating05T_Save
4018 01:54:30.479188 sync preloader u1Gatingfine_tune_Save
4019 01:54:30.482545 sync preloader u1Gatingucpass_count_Save
4020 01:54:30.486120 sync preloader u1TxWindowPerbitVref_Save
4021 01:54:30.489461 sync preloader u1TxCenter_min_Save
4022 01:54:30.492314 sync preloader u1TxCenter_max_Save
4023 01:54:30.496083 sync preloader u1Txwin_center_Save
4024 01:54:30.499394 sync preloader u1Txfirst_pass_Save
4025 01:54:30.502782 sync preloader u1Txlast_pass_Save
4026 01:54:30.503292 sync preloader u1RxDatlat_Save
4027 01:54:30.508802 sync preloader u1RxWinPerbitVref_Save
4028 01:54:30.512388 sync preloader u1RxWinPerbitDQ_firsbypass_Save
4029 01:54:30.515450 sync preloader u1RxWinPerbitDQ_lastbypass_Save
4030 01:54:30.519054 sync preloader delay_cell_unit
4031 01:54:30.525445 save_calibration_params with freq_sel:5, frequency:800, _MappingFreqArray:2
4032 01:54:30.528600 sync preloader write leveling
4033 01:54:30.529130 sync preloader cbt_mr12
4034 01:54:30.531964 sync preloader cbt_clk_dly
4035 01:54:30.534909 sync preloader cbt_cmd_dly
4036 01:54:30.535416 sync preloader cbt_cs
4037 01:54:30.538364 sync preloader cbt_ca_perbit_delay
4038 01:54:30.541663 sync preloader clk_delay
4039 01:54:30.544625 sync preloader dqs_delay
4040 01:54:30.548084 sync preloader u1Gating2T_Save
4041 01:54:30.548666 sync preloader u1Gating05T_Save
4042 01:54:30.551602 sync preloader u1Gatingfine_tune_Save
4043 01:54:30.558096 sync preloader u1Gatingucpass_count_Save
4044 01:54:30.562032 sync preloader u1TxWindowPerbitVref_Save
4045 01:54:30.564862 sync preloader u1TxCenter_min_Save
4046 01:54:30.568170 sync preloader u1TxCenter_max_Save
4047 01:54:30.571032 sync preloader u1Txwin_center_Save
4048 01:54:30.571475 sync preloader u1Txfirst_pass_Save
4049 01:54:30.574702 sync preloader u1Txlast_pass_Save
4050 01:54:30.578200 sync preloader u1RxDatlat_Save
4051 01:54:30.581440 sync preloader u1RxWinPerbitVref_Save
4052 01:54:30.587803 sync preloader u1RxWinPerbitDQ_firsbypass_Save
4053 01:54:30.591036 sync preloader u1RxWinPerbitDQ_lastbypass_Save
4054 01:54:30.594077 sync preloader delay_cell_unit
4055 01:54:30.597410 just_for_test_dump_coreboot_params dump all params
4056 01:54:30.597892 dump source = 0x0
4057 01:54:30.601077 dump params frequency:1600
4058 01:54:30.604332 dump params rank number:2
4059 01:54:30.604848
4060 01:54:30.607593 dump params write leveling
4061 01:54:30.610880 write leveling[0][0][0] = 0x20
4062 01:54:30.611401 write leveling[0][0][1] = 0x17
4063 01:54:30.613888 write leveling[0][1][0] = 0x20
4064 01:54:30.616967 write leveling[0][1][1] = 0x16
4065 01:54:30.620698 write leveling[1][0][0] = 0x23
4066 01:54:30.623659 write leveling[1][0][1] = 0x21
4067 01:54:30.626834 write leveling[1][1][0] = 0x23
4068 01:54:30.627276 write leveling[1][1][1] = 0x1d
4069 01:54:30.629983 dump params cbt_cs
4070 01:54:30.633322 cbt_cs[0][0] = 0x7
4071 01:54:30.633821 cbt_cs[0][1] = 0x7
4072 01:54:30.636950 cbt_cs[1][0] = 0xa
4073 01:54:30.637468 cbt_cs[1][1] = 0xa
4074 01:54:30.639919 dump params cbt_mr12
4075 01:54:30.640440 cbt_mr12[0][0] = 0x1e
4076 01:54:30.643687 cbt_mr12[0][1] = 0x1e
4077 01:54:30.646323 cbt_mr12[1][0] = 0x20
4078 01:54:30.646818 cbt_mr12[1][1] = 0x1c
4079 01:54:30.649659 dump params tx window
4080 01:54:30.653376 tx_center_min[0][0][0] = 985
4081 01:54:30.653855 tx_center_max[0][0][0] = 992
4082 01:54:30.656526 tx_center_min[0][0][1] = 977
4083 01:54:30.659735 tx_center_max[0][0][1] = 985
4084 01:54:30.663131 tx_center_min[0][1][0] = 986
4085 01:54:30.665845 tx_center_max[0][1][0] = 993
4086 01:54:30.666276 tx_center_min[0][1][1] = 976
4087 01:54:30.669624 tx_center_max[0][1][1] = 984
4088 01:54:30.673085 tx_center_min[1][0][0] = 991
4089 01:54:30.676455 tx_center_max[1][0][0] = 997
4090 01:54:30.679358 tx_center_min[1][0][1] = 987
4091 01:54:30.679786 tx_center_max[1][0][1] = 994
4092 01:54:30.682323 tx_center_min[1][1][0] = 990
4093 01:54:30.685836 tx_center_max[1][1][0] = 995
4094 01:54:30.689137 tx_center_min[1][1][1] = 981
4095 01:54:30.692615 tx_center_max[1][1][1] = 988
4096 01:54:30.693137 dump params tx window
4097 01:54:30.695647 tx_win_center[0][0][0] = 992
4098 01:54:30.699119 tx_first_pass[0][0][0] = 980
4099 01:54:30.702177 tx_last_pass[0][0][0] = 1005
4100 01:54:30.702606 tx_win_center[0][0][1] = 990
4101 01:54:30.705780 tx_first_pass[0][0][1] = 978
4102 01:54:30.708937 tx_last_pass[0][0][1] = 1003
4103 01:54:30.712549 tx_win_center[0][0][2] = 992
4104 01:54:30.715891 tx_first_pass[0][0][2] = 980
4105 01:54:30.716401 tx_last_pass[0][0][2] = 1004
4106 01:54:30.718342 tx_win_center[0][0][3] = 985
4107 01:54:30.722023 tx_first_pass[0][0][3] = 974
4108 01:54:30.725341 tx_last_pass[0][0][3] = 997
4109 01:54:30.728797 tx_win_center[0][0][4] = 989
4110 01:54:30.729337 tx_first_pass[0][0][4] = 977
4111 01:54:30.731971 tx_last_pass[0][0][4] = 1001
4112 01:54:30.735077 tx_win_center[0][0][5] = 987
4113 01:54:30.738312 tx_first_pass[0][0][5] = 976
4114 01:54:30.738758 tx_last_pass[0][0][5] = 999
4115 01:54:30.741594 tx_win_center[0][0][6] = 988
4116 01:54:30.744792 tx_first_pass[0][0][6] = 976
4117 01:54:30.748641 tx_last_pass[0][0][6] = 1000
4118 01:54:30.751420 tx_win_center[0][0][7] = 989
4119 01:54:30.751864 tx_first_pass[0][0][7] = 978
4120 01:54:30.754708 tx_last_pass[0][0][7] = 1001
4121 01:54:30.757779 tx_win_center[0][0][8] = 977
4122 01:54:30.761055 tx_first_pass[0][0][8] = 966
4123 01:54:30.765501 tx_last_pass[0][0][8] = 989
4124 01:54:30.766077 tx_win_center[0][0][9] = 978
4125 01:54:30.768313 tx_first_pass[0][0][9] = 967
4126 01:54:30.771147 tx_last_pass[0][0][9] = 990
4127 01:54:30.774483 tx_win_center[0][0][10] = 985
4128 01:54:30.777644 tx_first_pass[0][0][10] = 973
4129 01:54:30.778181 tx_last_pass[0][0][10] = 997
4130 01:54:30.780647 tx_win_center[0][0][11] = 978
4131 01:54:30.783963 tx_first_pass[0][0][11] = 967
4132 01:54:30.787419 tx_last_pass[0][0][11] = 990
4133 01:54:30.790512 tx_win_center[0][0][12] = 979
4134 01:54:30.793955 tx_first_pass[0][0][12] = 968
4135 01:54:30.794416 tx_last_pass[0][0][12] = 991
4136 01:54:30.796992 tx_win_center[0][0][13] = 979
4137 01:54:30.800780 tx_first_pass[0][0][13] = 968
4138 01:54:30.804067 tx_last_pass[0][0][13] = 991
4139 01:54:30.807136 tx_win_center[0][0][14] = 981
4140 01:54:30.807644 tx_first_pass[0][0][14] = 969
4141 01:54:30.810461 tx_last_pass[0][0][14] = 993
4142 01:54:30.813851 tx_win_center[0][0][15] = 984
4143 01:54:30.816979 tx_first_pass[0][0][15] = 973
4144 01:54:30.820635 tx_last_pass[0][0][15] = 996
4145 01:54:30.821150 tx_win_center[0][1][0] = 993
4146 01:54:30.823928 tx_first_pass[0][1][0] = 981
4147 01:54:30.826940 tx_last_pass[0][1][0] = 1005
4148 01:54:30.830453 tx_win_center[0][1][1] = 991
4149 01:54:30.832991 tx_first_pass[0][1][1] = 979
4150 01:54:30.833433 tx_last_pass[0][1][1] = 1004
4151 01:54:30.836242 tx_win_center[0][1][2] = 992
4152 01:54:30.839830 tx_first_pass[0][1][2] = 980
4153 01:54:30.843008 tx_last_pass[0][1][2] = 1004
4154 01:54:30.846704 tx_win_center[0][1][3] = 986
4155 01:54:30.847152 tx_first_pass[0][1][3] = 975
4156 01:54:30.849327 tx_last_pass[0][1][3] = 998
4157 01:54:30.852927 tx_win_center[0][1][4] = 990
4158 01:54:30.856007 tx_first_pass[0][1][4] = 978
4159 01:54:30.859345 tx_last_pass[0][1][4] = 1002
4160 01:54:30.859872 tx_win_center[0][1][5] = 988
4161 01:54:30.862716 tx_first_pass[0][1][5] = 976
4162 01:54:30.866331 tx_last_pass[0][1][5] = 1000
4163 01:54:30.869706 tx_win_center[0][1][6] = 989
4164 01:54:30.872643 tx_first_pass[0][1][6] = 977
4165 01:54:30.873152 tx_last_pass[0][1][6] = 1001
4166 01:54:30.875542 tx_win_center[0][1][7] = 990
4167 01:54:30.878878 tx_first_pass[0][1][7] = 978
4168 01:54:30.882906 tx_last_pass[0][1][7] = 1003
4169 01:54:30.886041 tx_win_center[0][1][8] = 976
4170 01:54:30.886563 tx_first_pass[0][1][8] = 965
4171 01:54:30.889070 tx_last_pass[0][1][8] = 988
4172 01:54:30.892394 tx_win_center[0][1][9] = 978
4173 01:54:30.895178 tx_first_pass[0][1][9] = 967
4174 01:54:30.898711 tx_last_pass[0][1][9] = 989
4175 01:54:30.899154 tx_win_center[0][1][10] = 984
4176 01:54:30.902126 tx_first_pass[0][1][10] = 972
4177 01:54:30.905924 tx_last_pass[0][1][10] = 996
4178 01:54:30.908936 tx_win_center[0][1][11] = 977
4179 01:54:30.911491 tx_first_pass[0][1][11] = 966
4180 01:54:30.911934 tx_last_pass[0][1][11] = 989
4181 01:54:30.914754 tx_win_center[0][1][12] = 978
4182 01:54:30.918390 tx_first_pass[0][1][12] = 967
4183 01:54:30.921958 tx_last_pass[0][1][12] = 990
4184 01:54:30.925096 tx_win_center[0][1][13] = 978
4185 01:54:30.927925 tx_first_pass[0][1][13] = 967
4186 01:54:30.928377 tx_last_pass[0][1][13] = 989
4187 01:54:30.931442 tx_win_center[0][1][14] = 979
4188 01:54:30.934389 tx_first_pass[0][1][14] = 968
4189 01:54:30.937621 tx_last_pass[0][1][14] = 991
4190 01:54:30.941808 tx_win_center[0][1][15] = 983
4191 01:54:30.942381 tx_first_pass[0][1][15] = 972
4192 01:54:30.944639 tx_last_pass[0][1][15] = 994
4193 01:54:30.947791 tx_win_center[1][0][0] = 997
4194 01:54:30.950864 tx_first_pass[1][0][0] = 984
4195 01:54:30.954118 tx_last_pass[1][0][0] = 1010
4196 01:54:30.954558 tx_win_center[1][0][1] = 995
4197 01:54:30.957696 tx_first_pass[1][0][1] = 983
4198 01:54:30.961116 tx_last_pass[1][0][1] = 1008
4199 01:54:30.964394 tx_win_center[1][0][2] = 993
4200 01:54:30.967800 tx_first_pass[1][0][2] = 981
4201 01:54:30.968323 tx_last_pass[1][0][2] = 1006
4202 01:54:30.970932 tx_win_center[1][0][3] = 991
4203 01:54:30.974350 tx_first_pass[1][0][3] = 978
4204 01:54:30.977664 tx_last_pass[1][0][3] = 1005
4205 01:54:30.980693 tx_win_center[1][0][4] = 996
4206 01:54:30.981215 tx_first_pass[1][0][4] = 984
4207 01:54:30.983875 tx_last_pass[1][0][4] = 1008
4208 01:54:30.986933 tx_win_center[1][0][5] = 996
4209 01:54:30.990179 tx_first_pass[1][0][5] = 984
4210 01:54:30.994010 tx_last_pass[1][0][5] = 1009
4211 01:54:30.994532 tx_win_center[1][0][6] = 996
4212 01:54:30.997291 tx_first_pass[1][0][6] = 983
4213 01:54:31.000560 tx_last_pass[1][0][6] = 1009
4214 01:54:31.003825 tx_win_center[1][0][7] = 995
4215 01:54:31.006717 tx_first_pass[1][0][7] = 983
4216 01:54:31.007165 tx_last_pass[1][0][7] = 1007
4217 01:54:31.010043 tx_win_center[1][0][8] = 990
4218 01:54:31.013649 tx_first_pass[1][0][8] = 979
4219 01:54:31.016550 tx_last_pass[1][0][8] = 1001
4220 01:54:31.020120 tx_win_center[1][0][9] = 990
4221 01:54:31.020640 tx_first_pass[1][0][9] = 979
4222 01:54:31.022845 tx_last_pass[1][0][9] = 1001
4223 01:54:31.026581 tx_win_center[1][0][10] = 992
4224 01:54:31.030032 tx_first_pass[1][0][10] = 982
4225 01:54:31.033545 tx_last_pass[1][0][10] = 1003
4226 01:54:31.034033 tx_win_center[1][0][11] = 993
4227 01:54:31.036113 tx_first_pass[1][0][11] = 983
4228 01:54:31.039135 tx_last_pass[1][0][11] = 1003
4229 01:54:31.042497 tx_win_center[1][0][12] = 994
4230 01:54:31.046123 tx_first_pass[1][0][12] = 984
4231 01:54:31.049053 tx_last_pass[1][0][12] = 1004
4232 01:54:31.049496 tx_win_center[1][0][13] = 994
4233 01:54:31.052251 tx_first_pass[1][0][13] = 984
4234 01:54:31.056029 tx_last_pass[1][0][13] = 1004
4235 01:54:31.059189 tx_win_center[1][0][14] = 992
4236 01:54:31.062427 tx_first_pass[1][0][14] = 982
4237 01:54:31.066224 tx_last_pass[1][0][14] = 1003
4238 01:54:31.066744 tx_win_center[1][0][15] = 987
4239 01:54:31.068865 tx_first_pass[1][0][15] = 976
4240 01:54:31.072533 tx_last_pass[1][0][15] = 999
4241 01:54:31.075662 tx_win_center[1][1][0] = 995
4242 01:54:31.079557 tx_first_pass[1][1][0] = 984
4243 01:54:31.080412 tx_last_pass[1][1][0] = 1007
4244 01:54:31.081862 tx_win_center[1][1][1] = 994
4245 01:54:31.085332 tx_first_pass[1][1][1] = 982
4246 01:54:31.088766 tx_last_pass[1][1][1] = 1006
4247 01:54:31.091490 tx_win_center[1][1][2] = 992
4248 01:54:31.091926 tx_first_pass[1][1][2] = 979
4249 01:54:31.095427 tx_last_pass[1][1][2] = 1006
4250 01:54:31.098555 tx_win_center[1][1][3] = 990
4251 01:54:31.101689 tx_first_pass[1][1][3] = 978
4252 01:54:31.105050 tx_last_pass[1][1][3] = 1003
4253 01:54:31.105452 tx_win_center[1][1][4] = 994
4254 01:54:31.108326 tx_first_pass[1][1][4] = 982
4255 01:54:31.111448 tx_last_pass[1][1][4] = 1006
4256 01:54:31.114692 tx_win_center[1][1][5] = 995
4257 01:54:31.118049 tx_first_pass[1][1][5] = 983
4258 01:54:31.118437 tx_last_pass[1][1][5] = 1007
4259 01:54:31.121296 tx_win_center[1][1][6] = 994
4260 01:54:31.124608 tx_first_pass[1][1][6] = 982
4261 01:54:31.127747 tx_last_pass[1][1][6] = 1007
4262 01:54:31.128136 tx_win_center[1][1][7] = 994
4263 01:54:31.131444 tx_first_pass[1][1][7] = 982
4264 01:54:31.134710 tx_last_pass[1][1][7] = 1007
4265 01:54:31.137830 tx_win_center[1][1][8] = 984
4266 01:54:31.141115 tx_first_pass[1][1][8] = 972
4267 01:54:31.141517 tx_last_pass[1][1][8] = 996
4268 01:54:31.144417 tx_win_center[1][1][9] = 983
4269 01:54:31.148147 tx_first_pass[1][1][9] = 972
4270 01:54:31.151118 tx_last_pass[1][1][9] = 995
4271 01:54:31.154027 tx_win_center[1][1][10] = 987
4272 01:54:31.154561 tx_first_pass[1][1][10] = 975
4273 01:54:31.157676 tx_last_pass[1][1][10] = 1000
4274 01:54:31.160647 tx_win_center[1][1][11] = 987
4275 01:54:31.163853 tx_first_pass[1][1][11] = 976
4276 01:54:31.167280 tx_last_pass[1][1][11] = 999
4277 01:54:31.170419 tx_win_center[1][1][12] = 988
4278 01:54:31.170816 tx_first_pass[1][1][12] = 976
4279 01:54:31.173611 tx_last_pass[1][1][12] = 1000
4280 01:54:31.177244 tx_win_center[1][1][13] = 988
4281 01:54:31.180209 tx_first_pass[1][1][13] = 977
4282 01:54:31.183834 tx_last_pass[1][1][13] = 1000
4283 01:54:31.186874 tx_win_center[1][1][14] = 987
4284 01:54:31.187264 tx_first_pass[1][1][14] = 975
4285 01:54:31.189931 tx_last_pass[1][1][14] = 1000
4286 01:54:31.193813 tx_win_center[1][1][15] = 981
4287 01:54:31.196689 tx_first_pass[1][1][15] = 970
4288 01:54:31.199791 tx_last_pass[1][1][15] = 993
4289 01:54:31.200205 dump params rx window
4290 01:54:31.203320 rx_firspass[0][0][0] = 6
4291 01:54:31.206452 rx_lastpass[0][0][0] = 38
4292 01:54:31.206856 rx_firspass[0][0][1] = 6
4293 01:54:31.209758 rx_lastpass[0][0][1] = 36
4294 01:54:31.212924 rx_firspass[0][0][2] = 6
4295 01:54:31.213318 rx_lastpass[0][0][2] = 37
4296 01:54:31.217100 rx_firspass[0][0][3] = 0
4297 01:54:31.219536 rx_lastpass[0][0][3] = 29
4298 01:54:31.222484 rx_firspass[0][0][4] = 6
4299 01:54:31.223006 rx_lastpass[0][0][4] = 35
4300 01:54:31.225744 rx_firspass[0][0][5] = 1
4301 01:54:31.229212 rx_lastpass[0][0][5] = 32
4302 01:54:31.229691 rx_firspass[0][0][6] = 5
4303 01:54:31.232483 rx_lastpass[0][0][6] = 32
4304 01:54:31.235742 rx_firspass[0][0][7] = 7
4305 01:54:31.239416 rx_lastpass[0][0][7] = 35
4306 01:54:31.239807 rx_firspass[0][0][8] = 0
4307 01:54:31.242690 rx_lastpass[0][0][8] = 30
4308 01:54:31.245944 rx_firspass[0][0][9] = 1
4309 01:54:31.246333 rx_lastpass[0][0][9] = 31
4310 01:54:31.249230 rx_firspass[0][0][10] = 9
4311 01:54:31.252586 rx_lastpass[0][0][10] = 39
4312 01:54:31.255853 rx_firspass[0][0][11] = 2
4313 01:54:31.256236 rx_lastpass[0][0][11] = 30
4314 01:54:31.259044 rx_firspass[0][0][12] = 2
4315 01:54:31.262291 rx_lastpass[0][0][12] = 32
4316 01:54:31.265295 rx_firspass[0][0][13] = 3
4317 01:54:31.265719 rx_lastpass[0][0][13] = 32
4318 01:54:31.268423 rx_firspass[0][0][14] = 3
4319 01:54:31.272344 rx_lastpass[0][0][14] = 35
4320 01:54:31.275512 rx_firspass[0][0][15] = 7
4321 01:54:31.275963 rx_lastpass[0][0][15] = 36
4322 01:54:31.278565 rx_firspass[0][1][0] = 4
4323 01:54:31.281868 rx_lastpass[0][1][0] = 38
4324 01:54:31.282090 rx_firspass[0][1][1] = 2
4325 01:54:31.284460 rx_lastpass[0][1][1] = 39
4326 01:54:31.287697 rx_firspass[0][1][2] = 4
4327 01:54:31.291549 rx_lastpass[0][1][2] = 40
4328 01:54:31.291701 rx_firspass[0][1][3] = -3
4329 01:54:31.294546 rx_lastpass[0][1][3] = 31
4330 01:54:31.298066 rx_firspass[0][1][4] = 5
4331 01:54:31.298204 rx_lastpass[0][1][4] = 38
4332 01:54:31.301076 rx_firspass[0][1][5] = 0
4333 01:54:31.304359 rx_lastpass[0][1][5] = 32
4334 01:54:31.304502 rx_firspass[0][1][6] = 1
4335 01:54:31.308114 rx_lastpass[0][1][6] = 35
4336 01:54:31.311558 rx_firspass[0][1][7] = 4
4337 01:54:31.314336 rx_lastpass[0][1][7] = 36
4338 01:54:31.314483 rx_firspass[0][1][8] = 0
4339 01:54:31.317942 rx_lastpass[0][1][8] = 33
4340 01:54:31.320998 rx_firspass[0][1][9] = 2
4341 01:54:31.321135 rx_lastpass[0][1][9] = 35
4342 01:54:31.324326 rx_firspass[0][1][10] = 9
4343 01:54:31.327441 rx_lastpass[0][1][10] = 42
4344 01:54:31.330887 rx_firspass[0][1][11] = 0
4345 01:54:31.331037 rx_lastpass[0][1][11] = 33
4346 01:54:31.334040 rx_firspass[0][1][12] = 3
4347 01:54:31.338139 rx_lastpass[0][1][12] = 36
4348 01:54:31.340449 rx_firspass[0][1][13] = 3
4349 01:54:31.340675 rx_lastpass[0][1][13] = 36
4350 01:54:31.343682 rx_firspass[0][1][14] = 5
4351 01:54:31.347393 rx_lastpass[0][1][14] = 37
4352 01:54:31.350379 rx_firspass[0][1][15] = 6
4353 01:54:31.350732 rx_lastpass[0][1][15] = 40
4354 01:54:31.353951 rx_firspass[1][0][0] = 4
4355 01:54:31.356878 rx_lastpass[1][0][0] = 39
4356 01:54:31.357267 rx_firspass[1][0][1] = 4
4357 01:54:31.360298 rx_lastpass[1][0][1] = 36
4358 01:54:31.364119 rx_firspass[1][0][2] = 5
4359 01:54:31.366798 rx_lastpass[1][0][2] = 35
4360 01:54:31.367113 rx_firspass[1][0][3] = -1
4361 01:54:31.370016 rx_lastpass[1][0][3] = 33
4362 01:54:31.373674 rx_firspass[1][0][4] = 5
4363 01:54:31.376759 rx_lastpass[1][0][4] = 35
4364 01:54:31.377071 rx_firspass[1][0][5] = 7
4365 01:54:31.380096 rx_lastpass[1][0][5] = 38
4366 01:54:31.383503 rx_firspass[1][0][6] = 10
4367 01:54:31.383887 rx_lastpass[1][0][6] = 38
4368 01:54:31.386717 rx_firspass[1][0][7] = 6
4369 01:54:31.390000 rx_lastpass[1][0][7] = 36
4370 01:54:31.390388 rx_firspass[1][0][8] = 1
4371 01:54:31.393270 rx_lastpass[1][0][8] = 32
4372 01:54:31.396514 rx_firspass[1][0][9] = 2
4373 01:54:31.399805 rx_lastpass[1][0][9] = 31
4374 01:54:31.400279 rx_firspass[1][0][10] = 6
4375 01:54:31.402775 rx_lastpass[1][0][10] = 35
4376 01:54:31.405705 rx_firspass[1][0][11] = 7
4377 01:54:31.409097 rx_lastpass[1][0][11] = 35
4378 01:54:31.409663 rx_firspass[1][0][12] = 6
4379 01:54:31.412579 rx_lastpass[1][0][12] = 36
4380 01:54:31.415574 rx_firspass[1][0][13] = 7
4381 01:54:31.418963 rx_lastpass[1][0][13] = 35
4382 01:54:31.419348 rx_firspass[1][0][14] = 7
4383 01:54:31.422269 rx_lastpass[1][0][14] = 36
4384 01:54:31.425479 rx_firspass[1][0][15] = 0
4385 01:54:31.428981 rx_lastpass[1][0][15] = 28
4386 01:54:31.429365 rx_firspass[1][1][0] = 5
4387 01:54:31.432137 rx_lastpass[1][1][0] = 38
4388 01:54:31.435568 rx_firspass[1][1][1] = 2
4389 01:54:31.435954 rx_lastpass[1][1][1] = 37
4390 01:54:31.438840 rx_firspass[1][1][2] = 2
4391 01:54:31.441940 rx_lastpass[1][1][2] = 34
4392 01:54:31.445238 rx_firspass[1][1][3] = 0
4393 01:54:31.445664 rx_lastpass[1][1][3] = 31
4394 01:54:31.448427 rx_firspass[1][1][4] = 3
4395 01:54:31.451662 rx_lastpass[1][1][4] = 38
4396 01:54:31.452169 rx_firspass[1][1][5] = 5
4397 01:54:31.455153 rx_lastpass[1][1][5] = 40
4398 01:54:31.457982 rx_firspass[1][1][6] = 7
4399 01:54:31.461669 rx_lastpass[1][1][6] = 40
4400 01:54:31.462057 rx_firspass[1][1][7] = 4
4401 01:54:31.465375 rx_lastpass[1][1][7] = 37
4402 01:54:31.468169 rx_firspass[1][1][8] = 1
4403 01:54:31.468609 rx_lastpass[1][1][8] = 34
4404 01:54:31.471471 rx_firspass[1][1][9] = 1
4405 01:54:31.474782 rx_lastpass[1][1][9] = 34
4406 01:54:31.475555 rx_firspass[1][1][10] = 4
4407 01:54:31.477683 rx_lastpass[1][1][10] = 37
4408 01:54:31.481041 rx_firspass[1][1][11] = 6
4409 01:54:31.484737 rx_lastpass[1][1][11] = 39
4410 01:54:31.485131 rx_firspass[1][1][12] = 7
4411 01:54:31.487499 rx_lastpass[1][1][12] = 38
4412 01:54:31.490716 rx_firspass[1][1][13] = 6
4413 01:54:31.494197 rx_lastpass[1][1][13] = 38
4414 01:54:31.494581 rx_firspass[1][1][14] = 6
4415 01:54:31.497646 rx_lastpass[1][1][14] = 39
4416 01:54:31.500919 rx_firspass[1][1][15] = -2
4417 01:54:31.504181 rx_lastpass[1][1][15] = 31
4418 01:54:31.504564 dump params clk_delay
4419 01:54:31.507525 clk_delay[0] = 1
4420 01:54:31.507908 clk_delay[1] = 0
4421 01:54:31.510716 dump params dqs_delay
4422 01:54:31.511098 dqs_delay[0][0] = 0
4423 01:54:31.513831 dqs_delay[0][1] = 0
4424 01:54:31.516945 dqs_delay[1][0] = -1
4425 01:54:31.517322 dqs_delay[1][1] = 0
4426 01:54:31.520854 dump params delay_cell_unit = 753
4427 01:54:31.521313 dump source = 0x0
4428 01:54:31.524241 dump params frequency:1200
4429 01:54:31.527341 dump params rank number:2
4430 01:54:31.527727
4431 01:54:31.530529 dump params write leveling
4432 01:54:31.533966 write leveling[0][0][0] = 0x0
4433 01:54:31.534469 write leveling[0][0][1] = 0x0
4434 01:54:31.536775 write leveling[0][1][0] = 0x0
4435 01:54:31.539980 write leveling[0][1][1] = 0x0
4436 01:54:31.543023 write leveling[1][0][0] = 0x0
4437 01:54:31.546673 write leveling[1][0][1] = 0x0
4438 01:54:31.547097 write leveling[1][1][0] = 0x0
4439 01:54:31.550503 write leveling[1][1][1] = 0x0
4440 01:54:31.553603 dump params cbt_cs
4441 01:54:31.554120 cbt_cs[0][0] = 0x0
4442 01:54:31.556728 cbt_cs[0][1] = 0x0
4443 01:54:31.557148 cbt_cs[1][0] = 0x0
4444 01:54:31.559902 cbt_cs[1][1] = 0x0
4445 01:54:31.562687 dump params cbt_mr12
4446 01:54:31.563106 cbt_mr12[0][0] = 0x0
4447 01:54:31.566222 cbt_mr12[0][1] = 0x0
4448 01:54:31.566718 cbt_mr12[1][0] = 0x0
4449 01:54:31.569707 cbt_mr12[1][1] = 0x0
4450 01:54:31.570207 dump params tx window
4451 01:54:31.572563 tx_center_min[0][0][0] = 0
4452 01:54:31.575672 tx_center_max[0][0][0] = 0
4453 01:54:31.579924 tx_center_min[0][0][1] = 0
4454 01:54:31.580427 tx_center_max[0][0][1] = 0
4455 01:54:31.582936 tx_center_min[0][1][0] = 0
4456 01:54:31.586139 tx_center_max[0][1][0] = 0
4457 01:54:31.589597 tx_center_min[0][1][1] = 0
4458 01:54:31.590106 tx_center_max[0][1][1] = 0
4459 01:54:31.592829 tx_center_min[1][0][0] = 0
4460 01:54:31.595976 tx_center_max[1][0][0] = 0
4461 01:54:31.599170 tx_center_min[1][0][1] = 0
4462 01:54:31.599615 tx_center_max[1][0][1] = 0
4463 01:54:31.602324 tx_center_min[1][1][0] = 0
4464 01:54:31.605884 tx_center_max[1][1][0] = 0
4465 01:54:31.608655 tx_center_min[1][1][1] = 0
4466 01:54:31.609155 tx_center_max[1][1][1] = 0
4467 01:54:31.612127 dump params tx window
4468 01:54:31.615191 tx_win_center[0][0][0] = 0
4469 01:54:31.618903 tx_first_pass[0][0][0] = 0
4470 01:54:31.619330 tx_last_pass[0][0][0] = 0
4471 01:54:31.621972 tx_win_center[0][0][1] = 0
4472 01:54:31.625038 tx_first_pass[0][0][1] = 0
4473 01:54:31.625595 tx_last_pass[0][0][1] = 0
4474 01:54:31.628585 tx_win_center[0][0][2] = 0
4475 01:54:31.631512 tx_first_pass[0][0][2] = 0
4476 01:54:31.634841 tx_last_pass[0][0][2] = 0
4477 01:54:31.635463 tx_win_center[0][0][3] = 0
4478 01:54:31.638080 tx_first_pass[0][0][3] = 0
4479 01:54:31.641733 tx_last_pass[0][0][3] = 0
4480 01:54:31.645142 tx_win_center[0][0][4] = 0
4481 01:54:31.645711 tx_first_pass[0][0][4] = 0
4482 01:54:31.648299 tx_last_pass[0][0][4] = 0
4483 01:54:31.651586 tx_win_center[0][0][5] = 0
4484 01:54:31.654638 tx_first_pass[0][0][5] = 0
4485 01:54:31.655079 tx_last_pass[0][0][5] = 0
4486 01:54:31.658073 tx_win_center[0][0][6] = 0
4487 01:54:31.661701 tx_first_pass[0][0][6] = 0
4488 01:54:31.664877 tx_last_pass[0][0][6] = 0
4489 01:54:31.665397 tx_win_center[0][0][7] = 0
4490 01:54:31.668291 tx_first_pass[0][0][7] = 0
4491 01:54:31.671702 tx_last_pass[0][0][7] = 0
4492 01:54:31.672222 tx_win_center[0][0][8] = 0
4493 01:54:31.674125 tx_first_pass[0][0][8] = 0
4494 01:54:31.677542 tx_last_pass[0][0][8] = 0
4495 01:54:31.680616 tx_win_center[0][0][9] = 0
4496 01:54:31.681082 tx_first_pass[0][0][9] = 0
4497 01:54:31.684381 tx_last_pass[0][0][9] = 0
4498 01:54:31.687413 tx_win_center[0][0][10] = 0
4499 01:54:31.690854 tx_first_pass[0][0][10] = 0
4500 01:54:31.691283 tx_last_pass[0][0][10] = 0
4501 01:54:31.694287 tx_win_center[0][0][11] = 0
4502 01:54:31.697794 tx_first_pass[0][0][11] = 0
4503 01:54:31.701036 tx_last_pass[0][0][11] = 0
4504 01:54:31.701544 tx_win_center[0][0][12] = 0
4505 01:54:31.704332 tx_first_pass[0][0][12] = 0
4506 01:54:31.707592 tx_last_pass[0][0][12] = 0
4507 01:54:31.710176 tx_win_center[0][0][13] = 0
4508 01:54:31.713372 tx_first_pass[0][0][13] = 0
4509 01:54:31.713907 tx_last_pass[0][0][13] = 0
4510 01:54:31.717348 tx_win_center[0][0][14] = 0
4511 01:54:31.720169 tx_first_pass[0][0][14] = 0
4512 01:54:31.723197 tx_last_pass[0][0][14] = 0
4513 01:54:31.723635 tx_win_center[0][0][15] = 0
4514 01:54:31.726319 tx_first_pass[0][0][15] = 0
4515 01:54:31.730414 tx_last_pass[0][0][15] = 0
4516 01:54:31.733160 tx_win_center[0][1][0] = 0
4517 01:54:31.733695 tx_first_pass[0][1][0] = 0
4518 01:54:31.736504 tx_last_pass[0][1][0] = 0
4519 01:54:31.740085 tx_win_center[0][1][1] = 0
4520 01:54:31.743132 tx_first_pass[0][1][1] = 0
4521 01:54:31.743568 tx_last_pass[0][1][1] = 0
4522 01:54:31.746595 tx_win_center[0][1][2] = 0
4523 01:54:31.749644 tx_first_pass[0][1][2] = 0
4524 01:54:31.752950 tx_last_pass[0][1][2] = 0
4525 01:54:31.753453 tx_win_center[0][1][3] = 0
4526 01:54:31.755894 tx_first_pass[0][1][3] = 0
4527 01:54:31.759288 tx_last_pass[0][1][3] = 0
4528 01:54:31.759935 tx_win_center[0][1][4] = 0
4529 01:54:31.762559 tx_first_pass[0][1][4] = 0
4530 01:54:31.766034 tx_last_pass[0][1][4] = 0
4531 01:54:31.768873 tx_win_center[0][1][5] = 0
4532 01:54:31.769393 tx_first_pass[0][1][5] = 0
4533 01:54:31.772452 tx_last_pass[0][1][5] = 0
4534 01:54:31.775779 tx_win_center[0][1][6] = 0
4535 01:54:31.778885 tx_first_pass[0][1][6] = 0
4536 01:54:31.779318 tx_last_pass[0][1][6] = 0
4537 01:54:31.782058 tx_win_center[0][1][7] = 0
4538 01:54:31.785776 tx_first_pass[0][1][7] = 0
4539 01:54:31.788926 tx_last_pass[0][1][7] = 0
4540 01:54:31.789349 tx_win_center[0][1][8] = 0
4541 01:54:31.791860 tx_first_pass[0][1][8] = 0
4542 01:54:31.795857 tx_last_pass[0][1][8] = 0
4543 01:54:31.798328 tx_win_center[0][1][9] = 0
4544 01:54:31.798922 tx_first_pass[0][1][9] = 0
4545 01:54:31.801706 tx_last_pass[0][1][9] = 0
4546 01:54:31.805033 tx_win_center[0][1][10] = 0
4547 01:54:31.808334 tx_first_pass[0][1][10] = 0
4548 01:54:31.808737 tx_last_pass[0][1][10] = 0
4549 01:54:31.811776 tx_win_center[0][1][11] = 0
4550 01:54:31.815044 tx_first_pass[0][1][11] = 0
4551 01:54:31.817906 tx_last_pass[0][1][11] = 0
4552 01:54:31.818470 tx_win_center[0][1][12] = 0
4553 01:54:31.821584 tx_first_pass[0][1][12] = 0
4554 01:54:31.825009 tx_last_pass[0][1][12] = 0
4555 01:54:31.828423 tx_win_center[0][1][13] = 0
4556 01:54:31.828895 tx_first_pass[0][1][13] = 0
4557 01:54:31.831490 tx_last_pass[0][1][13] = 0
4558 01:54:31.834858 tx_win_center[0][1][14] = 0
4559 01:54:31.838243 tx_first_pass[0][1][14] = 0
4560 01:54:31.838709 tx_last_pass[0][1][14] = 0
4561 01:54:31.841460 tx_win_center[0][1][15] = 0
4562 01:54:31.844881 tx_first_pass[0][1][15] = 0
4563 01:54:31.847672 tx_last_pass[0][1][15] = 0
4564 01:54:31.848103 tx_win_center[1][0][0] = 0
4565 01:54:31.851636 tx_first_pass[1][0][0] = 0
4566 01:54:31.854828 tx_last_pass[1][0][0] = 0
4567 01:54:31.858040 tx_win_center[1][0][1] = 0
4568 01:54:31.858476 tx_first_pass[1][0][1] = 0
4569 01:54:31.861262 tx_last_pass[1][0][1] = 0
4570 01:54:31.864046 tx_win_center[1][0][2] = 0
4571 01:54:31.867482 tx_first_pass[1][0][2] = 0
4572 01:54:31.867991 tx_last_pass[1][0][2] = 0
4573 01:54:31.871032 tx_win_center[1][0][3] = 0
4574 01:54:31.874148 tx_first_pass[1][0][3] = 0
4575 01:54:31.877542 tx_last_pass[1][0][3] = 0
4576 01:54:31.878015 tx_win_center[1][0][4] = 0
4577 01:54:31.880779 tx_first_pass[1][0][4] = 0
4578 01:54:31.884194 tx_last_pass[1][0][4] = 0
4579 01:54:31.884702 tx_win_center[1][0][5] = 0
4580 01:54:31.887007 tx_first_pass[1][0][5] = 0
4581 01:54:31.890500 tx_last_pass[1][0][5] = 0
4582 01:54:31.894854 tx_win_center[1][0][6] = 0
4583 01:54:31.895285 tx_first_pass[1][0][6] = 0
4584 01:54:31.896857 tx_last_pass[1][0][6] = 0
4585 01:54:31.900811 tx_win_center[1][0][7] = 0
4586 01:54:31.903672 tx_first_pass[1][0][7] = 0
4587 01:54:31.904101 tx_last_pass[1][0][7] = 0
4588 01:54:31.906990 tx_win_center[1][0][8] = 0
4589 01:54:31.910040 tx_first_pass[1][0][8] = 0
4590 01:54:31.913207 tx_last_pass[1][0][8] = 0
4591 01:54:31.913676 tx_win_center[1][0][9] = 0
4592 01:54:31.916425 tx_first_pass[1][0][9] = 0
4593 01:54:31.919424 tx_last_pass[1][0][9] = 0
4594 01:54:31.922846 tx_win_center[1][0][10] = 0
4595 01:54:31.923265 tx_first_pass[1][0][10] = 0
4596 01:54:31.926432 tx_last_pass[1][0][10] = 0
4597 01:54:31.930005 tx_win_center[1][0][11] = 0
4598 01:54:31.933121 tx_first_pass[1][0][11] = 0
4599 01:54:31.933515 tx_last_pass[1][0][11] = 0
4600 01:54:31.936574 tx_win_center[1][0][12] = 0
4601 01:54:31.939145 tx_first_pass[1][0][12] = 0
4602 01:54:31.943062 tx_last_pass[1][0][12] = 0
4603 01:54:31.943550 tx_win_center[1][0][13] = 0
4604 01:54:31.945824 tx_first_pass[1][0][13] = 0
4605 01:54:31.949185 tx_last_pass[1][0][13] = 0
4606 01:54:31.952799 tx_win_center[1][0][14] = 0
4607 01:54:31.953193 tx_first_pass[1][0][14] = 0
4608 01:54:31.956026 tx_last_pass[1][0][14] = 0
4609 01:54:31.959003 tx_win_center[1][0][15] = 0
4610 01:54:31.962390 tx_first_pass[1][0][15] = 0
4611 01:54:31.962788 tx_last_pass[1][0][15] = 0
4612 01:54:31.965837 tx_win_center[1][1][0] = 0
4613 01:54:31.969081 tx_first_pass[1][1][0] = 0
4614 01:54:31.972410 tx_last_pass[1][1][0] = 0
4615 01:54:31.972847 tx_win_center[1][1][1] = 0
4616 01:54:31.975703 tx_first_pass[1][1][1] = 0
4617 01:54:31.978942 tx_last_pass[1][1][1] = 0
4618 01:54:31.982111 tx_win_center[1][1][2] = 0
4619 01:54:31.982507 tx_first_pass[1][1][2] = 0
4620 01:54:31.985361 tx_last_pass[1][1][2] = 0
4621 01:54:31.988703 tx_win_center[1][1][3] = 0
4622 01:54:31.992102 tx_first_pass[1][1][3] = 0
4623 01:54:31.992496 tx_last_pass[1][1][3] = 0
4624 01:54:31.995417 tx_win_center[1][1][4] = 0
4625 01:54:31.998622 tx_first_pass[1][1][4] = 0
4626 01:54:32.001937 tx_last_pass[1][1][4] = 0
4627 01:54:32.002334 tx_win_center[1][1][5] = 0
4628 01:54:32.004954 tx_first_pass[1][1][5] = 0
4629 01:54:32.008513 tx_last_pass[1][1][5] = 0
4630 01:54:32.008906 tx_win_center[1][1][6] = 0
4631 01:54:32.011611 tx_first_pass[1][1][6] = 0
4632 01:54:32.014985 tx_last_pass[1][1][6] = 0
4633 01:54:32.018138 tx_win_center[1][1][7] = 0
4634 01:54:32.018844 tx_first_pass[1][1][7] = 0
4635 01:54:32.021383 tx_last_pass[1][1][7] = 0
4636 01:54:32.025386 tx_win_center[1][1][8] = 0
4637 01:54:32.027895 tx_first_pass[1][1][8] = 0
4638 01:54:32.028381 tx_last_pass[1][1][8] = 0
4639 01:54:32.031418 tx_win_center[1][1][9] = 0
4640 01:54:32.034814 tx_first_pass[1][1][9] = 0
4641 01:54:32.038253 tx_last_pass[1][1][9] = 0
4642 01:54:32.038672 tx_win_center[1][1][10] = 0
4643 01:54:32.041584 tx_first_pass[1][1][10] = 0
4644 01:54:32.044418 tx_last_pass[1][1][10] = 0
4645 01:54:32.048134 tx_win_center[1][1][11] = 0
4646 01:54:32.048671 tx_first_pass[1][1][11] = 0
4647 01:54:32.051001 tx_last_pass[1][1][11] = 0
4648 01:54:32.054246 tx_win_center[1][1][12] = 0
4649 01:54:32.057656 tx_first_pass[1][1][12] = 0
4650 01:54:32.058055 tx_last_pass[1][1][12] = 0
4651 01:54:32.060891 tx_win_center[1][1][13] = 0
4652 01:54:32.063945 tx_first_pass[1][1][13] = 0
4653 01:54:32.067451 tx_last_pass[1][1][13] = 0
4654 01:54:32.068028 tx_win_center[1][1][14] = 0
4655 01:54:32.070404 tx_first_pass[1][1][14] = 0
4656 01:54:32.074084 tx_last_pass[1][1][14] = 0
4657 01:54:32.077321 tx_win_center[1][1][15] = 0
4658 01:54:32.080573 tx_first_pass[1][1][15] = 0
4659 01:54:32.080968 tx_last_pass[1][1][15] = 0
4660 01:54:32.083736 dump params rx window
4661 01:54:32.087162 rx_firspass[0][0][0] = 0
4662 01:54:32.087614 rx_lastpass[0][0][0] = 0
4663 01:54:32.090297 rx_firspass[0][0][1] = 0
4664 01:54:32.093526 rx_lastpass[0][0][1] = 0
4665 01:54:32.093958 rx_firspass[0][0][2] = 0
4666 01:54:32.096933 rx_lastpass[0][0][2] = 0
4667 01:54:32.100207 rx_firspass[0][0][3] = 0
4668 01:54:32.100765 rx_lastpass[0][0][3] = 0
4669 01:54:32.103466 rx_firspass[0][0][4] = 0
4670 01:54:32.106742 rx_lastpass[0][0][4] = 0
4671 01:54:32.110002 rx_firspass[0][0][5] = 0
4672 01:54:32.110420 rx_lastpass[0][0][5] = 0
4673 01:54:32.113068 rx_firspass[0][0][6] = 0
4674 01:54:32.116511 rx_lastpass[0][0][6] = 0
4675 01:54:32.116923 rx_firspass[0][0][7] = 0
4676 01:54:32.120147 rx_lastpass[0][0][7] = 0
4677 01:54:32.123366 rx_firspass[0][0][8] = 0
4678 01:54:32.124043 rx_lastpass[0][0][8] = 0
4679 01:54:32.126354 rx_firspass[0][0][9] = 0
4680 01:54:32.129622 rx_lastpass[0][0][9] = 0
4681 01:54:32.130034 rx_firspass[0][0][10] = 0
4682 01:54:32.132943 rx_lastpass[0][0][10] = 0
4683 01:54:32.136139 rx_firspass[0][0][11] = 0
4684 01:54:32.139814 rx_lastpass[0][0][11] = 0
4685 01:54:32.140343 rx_firspass[0][0][12] = 0
4686 01:54:32.143097 rx_lastpass[0][0][12] = 0
4687 01:54:32.146223 rx_firspass[0][0][13] = 0
4688 01:54:32.149535 rx_lastpass[0][0][13] = 0
4689 01:54:32.150035 rx_firspass[0][0][14] = 0
4690 01:54:32.152793 rx_lastpass[0][0][14] = 0
4691 01:54:32.156190 rx_firspass[0][0][15] = 0
4692 01:54:32.156712 rx_lastpass[0][0][15] = 0
4693 01:54:32.159330 rx_firspass[0][1][0] = 0
4694 01:54:32.162981 rx_lastpass[0][1][0] = 0
4695 01:54:32.165836 rx_firspass[0][1][1] = 0
4696 01:54:32.166364 rx_lastpass[0][1][1] = 0
4697 01:54:32.169642 rx_firspass[0][1][2] = 0
4698 01:54:32.172615 rx_lastpass[0][1][2] = 0
4699 01:54:32.173027 rx_firspass[0][1][3] = 0
4700 01:54:32.175490 rx_lastpass[0][1][3] = 0
4701 01:54:32.179085 rx_firspass[0][1][4] = 0
4702 01:54:32.179701 rx_lastpass[0][1][4] = 0
4703 01:54:32.182271 rx_firspass[0][1][5] = 0
4704 01:54:32.185196 rx_lastpass[0][1][5] = 0
4705 01:54:32.188678 rx_firspass[0][1][6] = 0
4706 01:54:32.189087 rx_lastpass[0][1][6] = 0
4707 01:54:32.191689 rx_firspass[0][1][7] = 0
4708 01:54:32.195217 rx_lastpass[0][1][7] = 0
4709 01:54:32.195797 rx_firspass[0][1][8] = 0
4710 01:54:32.198231 rx_lastpass[0][1][8] = 0
4711 01:54:32.201727 rx_firspass[0][1][9] = 0
4712 01:54:32.202111 rx_lastpass[0][1][9] = 0
4713 01:54:32.204761 rx_firspass[0][1][10] = 0
4714 01:54:32.208163 rx_lastpass[0][1][10] = 0
4715 01:54:32.211608 rx_firspass[0][1][11] = 0
4716 01:54:32.211993 rx_lastpass[0][1][11] = 0
4717 01:54:32.214992 rx_firspass[0][1][12] = 0
4718 01:54:32.218169 rx_lastpass[0][1][12] = 0
4719 01:54:32.218663 rx_firspass[0][1][13] = 0
4720 01:54:32.221381 rx_lastpass[0][1][13] = 0
4721 01:54:32.224570 rx_firspass[0][1][14] = 0
4722 01:54:32.228213 rx_lastpass[0][1][14] = 0
4723 01:54:32.228833 rx_firspass[0][1][15] = 0
4724 01:54:32.231418 rx_lastpass[0][1][15] = 0
4725 01:54:32.234658 rx_firspass[1][0][0] = 0
4726 01:54:32.237693 rx_lastpass[1][0][0] = 0
4727 01:54:32.238177 rx_firspass[1][0][1] = 0
4728 01:54:32.241356 rx_lastpass[1][0][1] = 0
4729 01:54:32.244054 rx_firspass[1][0][2] = 0
4730 01:54:32.244527 rx_lastpass[1][0][2] = 0
4731 01:54:32.247460 rx_firspass[1][0][3] = 0
4732 01:54:32.250752 rx_lastpass[1][0][3] = 0
4733 01:54:32.251233 rx_firspass[1][0][4] = 0
4734 01:54:32.254081 rx_lastpass[1][0][4] = 0
4735 01:54:32.257422 rx_firspass[1][0][5] = 0
4736 01:54:32.257841 rx_lastpass[1][0][5] = 0
4737 01:54:32.260738 rx_firspass[1][0][6] = 0
4738 01:54:32.263883 rx_lastpass[1][0][6] = 0
4739 01:54:32.267371 rx_firspass[1][0][7] = 0
4740 01:54:32.267897 rx_lastpass[1][0][7] = 0
4741 01:54:32.270866 rx_firspass[1][0][8] = 0
4742 01:54:32.273746 rx_lastpass[1][0][8] = 0
4743 01:54:32.274281 rx_firspass[1][0][9] = 0
4744 01:54:32.277039 rx_lastpass[1][0][9] = 0
4745 01:54:32.280243 rx_firspass[1][0][10] = 0
4746 01:54:32.283647 rx_lastpass[1][0][10] = 0
4747 01:54:32.284032 rx_firspass[1][0][11] = 0
4748 01:54:32.286635 rx_lastpass[1][0][11] = 0
4749 01:54:32.290458 rx_firspass[1][0][12] = 0
4750 01:54:32.290842 rx_lastpass[1][0][12] = 0
4751 01:54:32.293106 rx_firspass[1][0][13] = 0
4752 01:54:32.296462 rx_lastpass[1][0][13] = 0
4753 01:54:32.299684 rx_firspass[1][0][14] = 0
4754 01:54:32.300068 rx_lastpass[1][0][14] = 0
4755 01:54:32.303205 rx_firspass[1][0][15] = 0
4756 01:54:32.306595 rx_lastpass[1][0][15] = 0
4757 01:54:32.306979 rx_firspass[1][1][0] = 0
4758 01:54:32.309417 rx_lastpass[1][1][0] = 0
4759 01:54:32.312698 rx_firspass[1][1][1] = 0
4760 01:54:32.316333 rx_lastpass[1][1][1] = 0
4761 01:54:32.316716 rx_firspass[1][1][2] = 0
4762 01:54:32.319836 rx_lastpass[1][1][2] = 0
4763 01:54:32.322378 rx_firspass[1][1][3] = 0
4764 01:54:32.322453 rx_lastpass[1][1][3] = 0
4765 01:54:32.325760 rx_firspass[1][1][4] = 0
4766 01:54:32.329126 rx_lastpass[1][1][4] = 0
4767 01:54:32.329227 rx_firspass[1][1][5] = 0
4768 01:54:32.332735 rx_lastpass[1][1][5] = 0
4769 01:54:32.335972 rx_firspass[1][1][6] = 0
4770 01:54:32.336068 rx_lastpass[1][1][6] = 0
4771 01:54:32.339125 rx_firspass[1][1][7] = 0
4772 01:54:32.342381 rx_lastpass[1][1][7] = 0
4773 01:54:32.345362 rx_firspass[1][1][8] = 0
4774 01:54:32.345460 rx_lastpass[1][1][8] = 0
4775 01:54:32.349186 rx_firspass[1][1][9] = 0
4776 01:54:32.352224 rx_lastpass[1][1][9] = 0
4777 01:54:32.352331 rx_firspass[1][1][10] = 0
4778 01:54:32.355260 rx_lastpass[1][1][10] = 0
4779 01:54:32.358553 rx_firspass[1][1][11] = 0
4780 01:54:32.361821 rx_lastpass[1][1][11] = 0
4781 01:54:32.361994 rx_firspass[1][1][12] = 0
4782 01:54:32.365062 rx_lastpass[1][1][12] = 0
4783 01:54:32.368435 rx_firspass[1][1][13] = 0
4784 01:54:32.368523 rx_lastpass[1][1][13] = 0
4785 01:54:32.371891 rx_firspass[1][1][14] = 0
4786 01:54:32.375278 rx_lastpass[1][1][14] = 0
4787 01:54:32.378478 rx_firspass[1][1][15] = 0
4788 01:54:32.378581 rx_lastpass[1][1][15] = 0
4789 01:54:32.381550 dump params clk_delay
4790 01:54:32.381632 clk_delay[0] = 0
4791 01:54:32.384935 clk_delay[1] = 0
4792 01:54:32.388156 dump params dqs_delay
4793 01:54:32.388245 dqs_delay[0][0] = 0
4794 01:54:32.391423 dqs_delay[0][1] = 0
4795 01:54:32.391486 dqs_delay[1][0] = 0
4796 01:54:32.394719 dqs_delay[1][1] = 0
4797 01:54:32.398404 dump params delay_cell_unit = 753
4798 01:54:32.398498 dump source = 0x0
4799 01:54:32.400943 dump params frequency:800
4800 01:54:32.404273 dump params rank number:2
4801 01:54:32.404361
4802 01:54:32.404443 dump params write leveling
4803 01:54:32.407456 write leveling[0][0][0] = 0x0
4804 01:54:32.410739 write leveling[0][0][1] = 0x0
4805 01:54:32.413977 write leveling[0][1][0] = 0x0
4806 01:54:32.417386 write leveling[0][1][1] = 0x0
4807 01:54:32.417474 write leveling[1][0][0] = 0x0
4808 01:54:32.420568 write leveling[1][0][1] = 0x0
4809 01:54:32.424194 write leveling[1][1][0] = 0x0
4810 01:54:32.427182 write leveling[1][1][1] = 0x0
4811 01:54:32.427246 dump params cbt_cs
4812 01:54:32.430674 cbt_cs[0][0] = 0x0
4813 01:54:32.430741 cbt_cs[0][1] = 0x0
4814 01:54:32.433842 cbt_cs[1][0] = 0x0
4815 01:54:32.437080 cbt_cs[1][1] = 0x0
4816 01:54:32.437171 dump params cbt_mr12
4817 01:54:32.440662 cbt_mr12[0][0] = 0x0
4818 01:54:32.440734 cbt_mr12[0][1] = 0x0
4819 01:54:32.443653 cbt_mr12[1][0] = 0x0
4820 01:54:32.443738 cbt_mr12[1][1] = 0x0
4821 01:54:32.447022 dump params tx window
4822 01:54:32.450311 tx_center_min[0][0][0] = 0
4823 01:54:32.453467 tx_center_max[0][0][0] = 0
4824 01:54:32.453582 tx_center_min[0][0][1] = 0
4825 01:54:32.456638 tx_center_max[0][0][1] = 0
4826 01:54:32.460028 tx_center_min[0][1][0] = 0
4827 01:54:32.463246 tx_center_max[0][1][0] = 0
4828 01:54:32.463314 tx_center_min[0][1][1] = 0
4829 01:54:32.466922 tx_center_max[0][1][1] = 0
4830 01:54:32.470057 tx_center_min[1][0][0] = 0
4831 01:54:32.473256 tx_center_max[1][0][0] = 0
4832 01:54:32.473347 tx_center_min[1][0][1] = 0
4833 01:54:32.476533 tx_center_max[1][0][1] = 0
4834 01:54:32.479759 tx_center_min[1][1][0] = 0
4835 01:54:32.482916 tx_center_max[1][1][0] = 0
4836 01:54:32.483007 tx_center_min[1][1][1] = 0
4837 01:54:32.486706 tx_center_max[1][1][1] = 0
4838 01:54:32.489400 dump params tx window
4839 01:54:32.489513 tx_win_center[0][0][0] = 0
4840 01:54:32.492824 tx_first_pass[0][0][0] = 0
4841 01:54:32.496131 tx_last_pass[0][0][0] = 0
4842 01:54:32.499539 tx_win_center[0][0][1] = 0
4843 01:54:32.499701 tx_first_pass[0][0][1] = 0
4844 01:54:32.503021 tx_last_pass[0][0][1] = 0
4845 01:54:32.506619 tx_win_center[0][0][2] = 0
4846 01:54:32.509957 tx_first_pass[0][0][2] = 0
4847 01:54:32.510146 tx_last_pass[0][0][2] = 0
4848 01:54:32.513155 tx_win_center[0][0][3] = 0
4849 01:54:32.516521 tx_first_pass[0][0][3] = 0
4850 01:54:32.516728 tx_last_pass[0][0][3] = 0
4851 01:54:32.519084 tx_win_center[0][0][4] = 0
4852 01:54:32.522378 tx_first_pass[0][0][4] = 0
4853 01:54:32.525819 tx_last_pass[0][0][4] = 0
4854 01:54:32.526074 tx_win_center[0][0][5] = 0
4855 01:54:32.529176 tx_first_pass[0][0][5] = 0
4856 01:54:32.532509 tx_last_pass[0][0][5] = 0
4857 01:54:32.536218 tx_win_center[0][0][6] = 0
4858 01:54:32.536574 tx_first_pass[0][0][6] = 0
4859 01:54:32.539537 tx_last_pass[0][0][6] = 0
4860 01:54:32.542430 tx_win_center[0][0][7] = 0
4861 01:54:32.546172 tx_first_pass[0][0][7] = 0
4862 01:54:32.546597 tx_last_pass[0][0][7] = 0
4863 01:54:32.548917 tx_win_center[0][0][8] = 0
4864 01:54:32.552888 tx_first_pass[0][0][8] = 0
4865 01:54:32.553395 tx_last_pass[0][0][8] = 0
4866 01:54:32.555953 tx_win_center[0][0][9] = 0
4867 01:54:32.559219 tx_first_pass[0][0][9] = 0
4868 01:54:32.562429 tx_last_pass[0][0][9] = 0
4869 01:54:32.562900 tx_win_center[0][0][10] = 0
4870 01:54:32.565247 tx_first_pass[0][0][10] = 0
4871 01:54:32.569252 tx_last_pass[0][0][10] = 0
4872 01:54:32.571900 tx_win_center[0][0][11] = 0
4873 01:54:32.575138 tx_first_pass[0][0][11] = 0
4874 01:54:32.575646 tx_last_pass[0][0][11] = 0
4875 01:54:32.578692 tx_win_center[0][0][12] = 0
4876 01:54:32.581955 tx_first_pass[0][0][12] = 0
4877 01:54:32.585304 tx_last_pass[0][0][12] = 0
4878 01:54:32.585947 tx_win_center[0][0][13] = 0
4879 01:54:32.588832 tx_first_pass[0][0][13] = 0
4880 01:54:32.592005 tx_last_pass[0][0][13] = 0
4881 01:54:32.595181 tx_win_center[0][0][14] = 0
4882 01:54:32.595611 tx_first_pass[0][0][14] = 0
4883 01:54:32.598552 tx_last_pass[0][0][14] = 0
4884 01:54:32.601620 tx_win_center[0][0][15] = 0
4885 01:54:32.604644 tx_first_pass[0][0][15] = 0
4886 01:54:32.605248 tx_last_pass[0][0][15] = 0
4887 01:54:32.608740 tx_win_center[0][1][0] = 0
4888 01:54:32.611212 tx_first_pass[0][1][0] = 0
4889 01:54:32.614871 tx_last_pass[0][1][0] = 0
4890 01:54:32.615402 tx_win_center[0][1][1] = 0
4891 01:54:32.618234 tx_first_pass[0][1][1] = 0
4892 01:54:32.621576 tx_last_pass[0][1][1] = 0
4893 01:54:32.624843 tx_win_center[0][1][2] = 0
4894 01:54:32.625356 tx_first_pass[0][1][2] = 0
4895 01:54:32.628211 tx_last_pass[0][1][2] = 0
4896 01:54:32.631267 tx_win_center[0][1][3] = 0
4897 01:54:32.634079 tx_first_pass[0][1][3] = 0
4898 01:54:32.634614 tx_last_pass[0][1][3] = 0
4899 01:54:32.637311 tx_win_center[0][1][4] = 0
4900 01:54:32.641090 tx_first_pass[0][1][4] = 0
4901 01:54:32.641488 tx_last_pass[0][1][4] = 0
4902 01:54:32.644054 tx_win_center[0][1][5] = 0
4903 01:54:32.647376 tx_first_pass[0][1][5] = 0
4904 01:54:32.650855 tx_last_pass[0][1][5] = 0
4905 01:54:32.651242 tx_win_center[0][1][6] = 0
4906 01:54:32.653683 tx_first_pass[0][1][6] = 0
4907 01:54:32.657365 tx_last_pass[0][1][6] = 0
4908 01:54:32.660679 tx_win_center[0][1][7] = 0
4909 01:54:32.661149 tx_first_pass[0][1][7] = 0
4910 01:54:32.663919 tx_last_pass[0][1][7] = 0
4911 01:54:32.667128 tx_win_center[0][1][8] = 0
4912 01:54:32.670371 tx_first_pass[0][1][8] = 0
4913 01:54:32.670844 tx_last_pass[0][1][8] = 0
4914 01:54:32.673738 tx_win_center[0][1][9] = 0
4915 01:54:32.677246 tx_first_pass[0][1][9] = 0
4916 01:54:32.677847 tx_last_pass[0][1][9] = 0
4917 01:54:32.680476 tx_win_center[0][1][10] = 0
4918 01:54:32.683716 tx_first_pass[0][1][10] = 0
4919 01:54:32.687038 tx_last_pass[0][1][10] = 0
4920 01:54:32.690068 tx_win_center[0][1][11] = 0
4921 01:54:32.690454 tx_first_pass[0][1][11] = 0
4922 01:54:32.693527 tx_last_pass[0][1][11] = 0
4923 01:54:32.696866 tx_win_center[0][1][12] = 0
4924 01:54:32.699628 tx_first_pass[0][1][12] = 0
4925 01:54:32.700139 tx_last_pass[0][1][12] = 0
4926 01:54:32.702808 tx_win_center[0][1][13] = 0
4927 01:54:32.706612 tx_first_pass[0][1][13] = 0
4928 01:54:32.709626 tx_last_pass[0][1][13] = 0
4929 01:54:32.710042 tx_win_center[0][1][14] = 0
4930 01:54:32.712805 tx_first_pass[0][1][14] = 0
4931 01:54:32.716050 tx_last_pass[0][1][14] = 0
4932 01:54:32.720056 tx_win_center[0][1][15] = 0
4933 01:54:32.720442 tx_first_pass[0][1][15] = 0
4934 01:54:32.722970 tx_last_pass[0][1][15] = 0
4935 01:54:32.726511 tx_win_center[1][0][0] = 0
4936 01:54:32.729140 tx_first_pass[1][0][0] = 0
4937 01:54:32.729709 tx_last_pass[1][0][0] = 0
4938 01:54:32.732886 tx_win_center[1][0][1] = 0
4939 01:54:32.736054 tx_first_pass[1][0][1] = 0
4940 01:54:32.739550 tx_last_pass[1][0][1] = 0
4941 01:54:32.739933 tx_win_center[1][0][2] = 0
4942 01:54:32.742912 tx_first_pass[1][0][2] = 0
4943 01:54:32.745969 tx_last_pass[1][0][2] = 0
4944 01:54:32.748884 tx_win_center[1][0][3] = 0
4945 01:54:32.749402 tx_first_pass[1][0][3] = 0
4946 01:54:32.752125 tx_last_pass[1][0][3] = 0
4947 01:54:32.755390 tx_win_center[1][0][4] = 0
4948 01:54:32.758629 tx_first_pass[1][0][4] = 0
4949 01:54:32.759032 tx_last_pass[1][0][4] = 0
4950 01:54:32.762449 tx_win_center[1][0][5] = 0
4951 01:54:32.765597 tx_first_pass[1][0][5] = 0
4952 01:54:32.765984 tx_last_pass[1][0][5] = 0
4953 01:54:32.768987 tx_win_center[1][0][6] = 0
4954 01:54:32.772117 tx_first_pass[1][0][6] = 0
4955 01:54:32.775540 tx_last_pass[1][0][6] = 0
4956 01:54:32.775924 tx_win_center[1][0][7] = 0
4957 01:54:32.778242 tx_first_pass[1][0][7] = 0
4958 01:54:32.781803 tx_last_pass[1][0][7] = 0
4959 01:54:32.784880 tx_win_center[1][0][8] = 0
4960 01:54:32.785272 tx_first_pass[1][0][8] = 0
4961 01:54:32.788277 tx_last_pass[1][0][8] = 0
4962 01:54:32.791528 tx_win_center[1][0][9] = 0
4963 01:54:32.794621 tx_first_pass[1][0][9] = 0
4964 01:54:32.795123 tx_last_pass[1][0][9] = 0
4965 01:54:32.797996 tx_win_center[1][0][10] = 0
4966 01:54:32.801144 tx_first_pass[1][0][10] = 0
4967 01:54:32.804771 tx_last_pass[1][0][10] = 0
4968 01:54:32.805155 tx_win_center[1][0][11] = 0
4969 01:54:32.808051 tx_first_pass[1][0][11] = 0
4970 01:54:32.811558 tx_last_pass[1][0][11] = 0
4971 01:54:32.814505 tx_win_center[1][0][12] = 0
4972 01:54:32.814944 tx_first_pass[1][0][12] = 0
4973 01:54:32.818135 tx_last_pass[1][0][12] = 0
4974 01:54:32.820917 tx_win_center[1][0][13] = 0
4975 01:54:32.824319 tx_first_pass[1][0][13] = 0
4976 01:54:32.824706 tx_last_pass[1][0][13] = 0
4977 01:54:32.828021 tx_win_center[1][0][14] = 0
4978 01:54:32.830975 tx_first_pass[1][0][14] = 0
4979 01:54:32.834173 tx_last_pass[1][0][14] = 0
4980 01:54:32.834557 tx_win_center[1][0][15] = 0
4981 01:54:32.837803 tx_first_pass[1][0][15] = 0
4982 01:54:32.840473 tx_last_pass[1][0][15] = 0
4983 01:54:32.843849 tx_win_center[1][1][0] = 0
4984 01:54:32.847309 tx_first_pass[1][1][0] = 0
4985 01:54:32.847701 tx_last_pass[1][1][0] = 0
4986 01:54:32.851111 tx_win_center[1][1][1] = 0
4987 01:54:32.854178 tx_first_pass[1][1][1] = 0
4988 01:54:32.854571 tx_last_pass[1][1][1] = 0
4989 01:54:32.857507 tx_win_center[1][1][2] = 0
4990 01:54:32.860448 tx_first_pass[1][1][2] = 0
4991 01:54:32.864004 tx_last_pass[1][1][2] = 0
4992 01:54:32.864520 tx_win_center[1][1][3] = 0
4993 01:54:32.866778 tx_first_pass[1][1][3] = 0
4994 01:54:32.870015 tx_last_pass[1][1][3] = 0
4995 01:54:32.873321 tx_win_center[1][1][4] = 0
4996 01:54:32.873761 tx_first_pass[1][1][4] = 0
4997 01:54:32.876711 tx_last_pass[1][1][4] = 0
4998 01:54:32.880100 tx_win_center[1][1][5] = 0
4999 01:54:32.883713 tx_first_pass[1][1][5] = 0
5000 01:54:32.884102 tx_last_pass[1][1][5] = 0
5001 01:54:32.886767 tx_win_center[1][1][6] = 0
5002 01:54:32.890116 tx_first_pass[1][1][6] = 0
5003 01:54:32.892942 tx_last_pass[1][1][6] = 0
5004 01:54:32.893399 tx_win_center[1][1][7] = 0
5005 01:54:32.896155 tx_first_pass[1][1][7] = 0
5006 01:54:32.899512 tx_last_pass[1][1][7] = 0
5007 01:54:32.899983 tx_win_center[1][1][8] = 0
5008 01:54:32.903012 tx_first_pass[1][1][8] = 0
5009 01:54:32.906323 tx_last_pass[1][1][8] = 0
5010 01:54:32.909178 tx_win_center[1][1][9] = 0
5011 01:54:32.909597 tx_first_pass[1][1][9] = 0
5012 01:54:32.912439 tx_last_pass[1][1][9] = 0
5013 01:54:32.915759 tx_win_center[1][1][10] = 0
5014 01:54:32.918997 tx_first_pass[1][1][10] = 0
5015 01:54:32.919387 tx_last_pass[1][1][10] = 0
5016 01:54:32.922315 tx_win_center[1][1][11] = 0
5017 01:54:32.925638 tx_first_pass[1][1][11] = 0
5018 01:54:32.929440 tx_last_pass[1][1][11] = 0
5019 01:54:32.929891 tx_win_center[1][1][12] = 0
5020 01:54:32.932138 tx_first_pass[1][1][12] = 0
5021 01:54:32.935613 tx_last_pass[1][1][12] = 0
5022 01:54:32.939055 tx_win_center[1][1][13] = 0
5023 01:54:32.942421 tx_first_pass[1][1][13] = 0
5024 01:54:32.942810 tx_last_pass[1][1][13] = 0
5025 01:54:32.945520 tx_win_center[1][1][14] = 0
5026 01:54:32.948861 tx_first_pass[1][1][14] = 0
5027 01:54:32.952329 tx_last_pass[1][1][14] = 0
5028 01:54:32.952787 tx_win_center[1][1][15] = 0
5029 01:54:32.955481 tx_first_pass[1][1][15] = 0
5030 01:54:32.958788 tx_last_pass[1][1][15] = 0
5031 01:54:32.959179 dump params rx window
5032 01:54:32.961692 rx_firspass[0][0][0] = 0
5033 01:54:32.964957 rx_lastpass[0][0][0] = 0
5034 01:54:32.968425 rx_firspass[0][0][1] = 0
5035 01:54:32.968813 rx_lastpass[0][0][1] = 0
5036 01:54:32.971710 rx_firspass[0][0][2] = 0
5037 01:54:32.974922 rx_lastpass[0][0][2] = 0
5038 01:54:32.975309 rx_firspass[0][0][3] = 0
5039 01:54:32.978376 rx_lastpass[0][0][3] = 0
5040 01:54:32.981841 rx_firspass[0][0][4] = 0
5041 01:54:32.982231 rx_lastpass[0][0][4] = 0
5042 01:54:32.984886 rx_firspass[0][0][5] = 0
5043 01:54:32.988446 rx_lastpass[0][0][5] = 0
5044 01:54:32.991317 rx_firspass[0][0][6] = 0
5045 01:54:32.991704 rx_lastpass[0][0][6] = 0
5046 01:54:32.994521 rx_firspass[0][0][7] = 0
5047 01:54:32.997974 rx_lastpass[0][0][7] = 0
5048 01:54:32.998365 rx_firspass[0][0][8] = 0
5049 01:54:33.000693 rx_lastpass[0][0][8] = 0
5050 01:54:33.004336 rx_firspass[0][0][9] = 0
5051 01:54:33.004728 rx_lastpass[0][0][9] = 0
5052 01:54:33.007522 rx_firspass[0][0][10] = 0
5053 01:54:33.010967 rx_lastpass[0][0][10] = 0
5054 01:54:33.014106 rx_firspass[0][0][11] = 0
5055 01:54:33.014498 rx_lastpass[0][0][11] = 0
5056 01:54:33.017080 rx_firspass[0][0][12] = 0
5057 01:54:33.020406 rx_lastpass[0][0][12] = 0
5058 01:54:33.023717 rx_firspass[0][0][13] = 0
5059 01:54:33.024104 rx_lastpass[0][0][13] = 0
5060 01:54:33.027086 rx_firspass[0][0][14] = 0
5061 01:54:33.030292 rx_lastpass[0][0][14] = 0
5062 01:54:33.030680 rx_firspass[0][0][15] = 0
5063 01:54:33.033381 rx_lastpass[0][0][15] = 0
5064 01:54:33.036652 rx_firspass[0][1][0] = 0
5065 01:54:33.039747 rx_lastpass[0][1][0] = 0
5066 01:54:33.040215 rx_firspass[0][1][1] = 0
5067 01:54:33.043518 rx_lastpass[0][1][1] = 0
5068 01:54:33.046796 rx_firspass[0][1][2] = 0
5069 01:54:33.047185 rx_lastpass[0][1][2] = 0
5070 01:54:33.050142 rx_firspass[0][1][3] = 0
5071 01:54:33.053226 rx_lastpass[0][1][3] = 0
5072 01:54:33.053823 rx_firspass[0][1][4] = 0
5073 01:54:33.056972 rx_lastpass[0][1][4] = 0
5074 01:54:33.060291 rx_firspass[0][1][5] = 0
5075 01:54:33.062971 rx_lastpass[0][1][5] = 0
5076 01:54:33.063360 rx_firspass[0][1][6] = 0
5077 01:54:33.067356 rx_lastpass[0][1][6] = 0
5078 01:54:33.069671 rx_firspass[0][1][7] = 0
5079 01:54:33.070066 rx_lastpass[0][1][7] = 0
5080 01:54:33.073386 rx_firspass[0][1][8] = 0
5081 01:54:33.076146 rx_lastpass[0][1][8] = 0
5082 01:54:33.076538 rx_firspass[0][1][9] = 0
5083 01:54:33.079662 rx_lastpass[0][1][9] = 0
5084 01:54:33.083509 rx_firspass[0][1][10] = 0
5085 01:54:33.086310 rx_lastpass[0][1][10] = 0
5086 01:54:33.086699 rx_firspass[0][1][11] = 0
5087 01:54:33.089485 rx_lastpass[0][1][11] = 0
5088 01:54:33.092980 rx_firspass[0][1][12] = 0
5089 01:54:33.093452 rx_lastpass[0][1][12] = 0
5090 01:54:33.096377 rx_firspass[0][1][13] = 0
5091 01:54:33.099404 rx_lastpass[0][1][13] = 0
5092 01:54:33.102691 rx_firspass[0][1][14] = 0
5093 01:54:33.103081 rx_lastpass[0][1][14] = 0
5094 01:54:33.106475 rx_firspass[0][1][15] = 0
5095 01:54:33.109264 rx_lastpass[0][1][15] = 0
5096 01:54:33.109782 rx_firspass[1][0][0] = 0
5097 01:54:33.112408 rx_lastpass[1][0][0] = 0
5098 01:54:33.116008 rx_firspass[1][0][1] = 0
5099 01:54:33.118904 rx_lastpass[1][0][1] = 0
5100 01:54:33.119294 rx_firspass[1][0][2] = 0
5101 01:54:33.122267 rx_lastpass[1][0][2] = 0
5102 01:54:33.125464 rx_firspass[1][0][3] = 0
5103 01:54:33.125884 rx_lastpass[1][0][3] = 0
5104 01:54:33.128995 rx_firspass[1][0][4] = 0
5105 01:54:33.132389 rx_lastpass[1][0][4] = 0
5106 01:54:33.132775 rx_firspass[1][0][5] = 0
5107 01:54:33.135340 rx_lastpass[1][0][5] = 0
5108 01:54:33.138617 rx_firspass[1][0][6] = 0
5109 01:54:33.141637 rx_lastpass[1][0][6] = 0
5110 01:54:33.142019 rx_firspass[1][0][7] = 0
5111 01:54:33.144978 rx_lastpass[1][0][7] = 0
5112 01:54:33.148312 rx_firspass[1][0][8] = 0
5113 01:54:33.148700 rx_lastpass[1][0][8] = 0
5114 01:54:33.151406 rx_firspass[1][0][9] = 0
5115 01:54:33.155421 rx_lastpass[1][0][9] = 0
5116 01:54:33.155889 rx_firspass[1][0][10] = 0
5117 01:54:33.158679 rx_lastpass[1][0][10] = 0
5118 01:54:33.161706 rx_firspass[1][0][11] = 0
5119 01:54:33.165252 rx_lastpass[1][0][11] = 0
5120 01:54:33.165692 rx_firspass[1][0][12] = 0
5121 01:54:33.168048 rx_lastpass[1][0][12] = 0
5122 01:54:33.171503 rx_firspass[1][0][13] = 0
5123 01:54:33.171975 rx_lastpass[1][0][13] = 0
5124 01:54:33.174704 rx_firspass[1][0][14] = 0
5125 01:54:33.178112 rx_lastpass[1][0][14] = 0
5126 01:54:33.181515 rx_firspass[1][0][15] = 0
5127 01:54:33.182022 rx_lastpass[1][0][15] = 0
5128 01:54:33.184568 rx_firspass[1][1][0] = 0
5129 01:54:33.188226 rx_lastpass[1][1][0] = 0
5130 01:54:33.188703 rx_firspass[1][1][1] = 0
5131 01:54:33.191225 rx_lastpass[1][1][1] = 0
5132 01:54:33.194271 rx_firspass[1][1][2] = 0
5133 01:54:33.197686 rx_lastpass[1][1][2] = 0
5134 01:54:33.198176 rx_firspass[1][1][3] = 0
5135 01:54:33.200647 rx_lastpass[1][1][3] = 0
5136 01:54:33.204329 rx_firspass[1][1][4] = 0
5137 01:54:33.204798 rx_lastpass[1][1][4] = 0
5138 01:54:33.207622 rx_firspass[1][1][5] = 0
5139 01:54:33.210863 rx_lastpass[1][1][5] = 0
5140 01:54:33.211334 rx_firspass[1][1][6] = 0
5141 01:54:33.213890 rx_lastpass[1][1][6] = 0
5142 01:54:33.217612 rx_firspass[1][1][7] = 0
5143 01:54:33.220555 rx_lastpass[1][1][7] = 0
5144 01:54:33.220943 rx_firspass[1][1][8] = 0
5145 01:54:33.223844 rx_lastpass[1][1][8] = 0
5146 01:54:33.227257 rx_firspass[1][1][9] = 0
5147 01:54:33.227644 rx_lastpass[1][1][9] = 0
5148 01:54:33.230509 rx_firspass[1][1][10] = 0
5149 01:54:33.233783 rx_lastpass[1][1][10] = 0
5150 01:54:33.234259 rx_firspass[1][1][11] = 0
5151 01:54:33.236882 rx_lastpass[1][1][11] = 0
5152 01:54:33.240270 rx_firspass[1][1][12] = 0
5153 01:54:33.243843 rx_lastpass[1][1][12] = 0
5154 01:54:33.244315 rx_firspass[1][1][13] = 0
5155 01:54:33.246812 rx_lastpass[1][1][13] = 0
5156 01:54:33.250000 rx_firspass[1][1][14] = 0
5157 01:54:33.253717 rx_lastpass[1][1][14] = 0
5158 01:54:33.254190 rx_firspass[1][1][15] = 0
5159 01:54:33.256584 rx_lastpass[1][1][15] = 0
5160 01:54:33.259663 dump params clk_delay
5161 01:54:33.260064 clk_delay[0] = 0
5162 01:54:33.263093 clk_delay[1] = 0
5163 01:54:33.263487 dump params dqs_delay
5164 01:54:33.266123 dqs_delay[0][0] = 0
5165 01:54:33.266514 dqs_delay[0][1] = 0
5166 01:54:33.269888 dqs_delay[1][0] = 0
5167 01:54:33.270275 dqs_delay[1][1] = 0
5168 01:54:33.273112 dump params delay_cell_unit = 753
5169 01:54:33.276213 mt_set_emi_preloader end
5170 01:54:33.279445 [mt_mem_init] dram size: 0x100000000, rank number: 2
5171 01:54:33.286009 [complex_mem_test] start addr:0x40000000, len:20480
5172 01:54:33.322085 [mt_mem_init] preloader addr:0x40000000 complex R/W mem test pass : 0
5173 01:54:33.328616 [complex_mem_test] start addr:0x80000000, len:20480
5174 01:54:33.364609 [mt_mem_init] preloader addr:0x80000000 complex R/W mem test pass : 0
5175 01:54:33.370719 [complex_mem_test] start addr:0xc0000000, len:20480
5176 01:54:33.406656 [mt_mem_init] preloader addr:0xc0000000 complex R/W mem test pass : 0
5177 01:54:33.413916 [complex_mem_test] start addr:0x56000000, len:8192
5178 01:54:33.429360 [MEM] 1st complex R/W mem test pass (start addr:0x56000000)
5179 01:54:33.429488 ddr_geometry:1
5180 01:54:33.435937 [complex_mem_test] start addr:0x80000000, len:8192
5181 01:54:33.453487 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
5182 01:54:33.456951 dram_init: dram init end (result: 0)
5183 01:54:33.463611 Successfully loaded DRAM blobs and ran DRAM calibration
5184 01:54:33.473945 Mapping address range [0000000040000000:0000000140000000) as cacheable | read-write | non-secure | normal
5185 01:54:33.474472 CBMEM:
5186 01:54:33.477254 IMD: root @ 00000000fffff000 254 entries.
5187 01:54:33.480062 IMD: root @ 00000000ffffec00 62 entries.
5188 01:54:33.486550 VBOOT: copying vboot_working_data (256 bytes) to CBMEM...
5189 01:54:33.493407 out: cmd=0xa4: 03 6c a4 00 00 00 0c 00 00 01 00 00 50 7f 11 00 00 00 00 00
5190 01:54:33.496445 in-header: 03 a1 00 00 08 00 00 00
5191 01:54:33.499754 in-data: 84 60 60 10 00 00 00 00
5192 01:54:33.503105 Chrome EC: clear events_b mask to 0x0000000020004000
5193 01:54:33.513723 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
5194 01:54:33.514224 in-header: 03 fd 00 00 00 00 00 00
5195 01:54:33.517076 in-data:
5196 01:54:33.521013 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5197 01:54:33.523451 CBFS @ 21000 size 3d4000
5198 01:54:33.527065 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5199 01:54:33.530044 CBFS: Locating 'fallback/ramstage'
5200 01:54:33.533649 CBFS: Found @ offset 10d40 size d563
5201 01:54:33.556079 read SPI 0x31d94 0xd547: 16639 us, 3281 KB/s, 26.248 Mbps
5202 01:54:33.567941 Accumulated console time in romstage 13571 ms
5203 01:54:33.568510
5204 01:54:33.568857
5205 01:54:33.577581 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 ramstage starting (log level: 8)...
5206 01:54:33.580952 ARM64: Exception handlers installed.
5207 01:54:33.581388 ARM64: Testing exception
5208 01:54:33.584117 ARM64: Done test exception
5209 01:54:33.587633 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
5210 01:54:33.590810 Manufacturer: ef
5211 01:54:33.597713 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
5212 01:54:33.600797 WARNING: RO_VPD is uninitialized or empty.
5213 01:54:33.604152 FMAP: area RW_VPD found @ 550000 (16384 bytes)
5214 01:54:33.607481 FMAP: area RW_VPD found @ 550000 (16384 bytes)
5215 01:54:33.617657 read SPI 0x550600 0x3a00: 4531 us, 3276 KB/s, 26.208 Mbps
5216 01:54:33.621213 BS: BS_PRE_DEVICE times (ms): entry 0 run 0 exit 0
5217 01:54:33.627832 BS: BS_DEV_INIT_CHIPS times (ms): entry 0 run 0 exit 0
5218 01:54:33.628341 Enumerating buses...
5219 01:54:33.633595 Show all devs... Before device enumeration.
5220 01:54:33.634045 Root Device: enabled 1
5221 01:54:33.637237 CPU_CLUSTER: 0: enabled 1
5222 01:54:33.640601 CPU: 00: enabled 1
5223 01:54:33.641132 Compare with tree...
5224 01:54:33.643970 Root Device: enabled 1
5225 01:54:33.644500 CPU_CLUSTER: 0: enabled 1
5226 01:54:33.646891 CPU: 00: enabled 1
5227 01:54:33.650128 Root Device scanning...
5228 01:54:33.653756 root_dev_scan_bus for Root Device
5229 01:54:33.654262 CPU_CLUSTER: 0 enabled
5230 01:54:33.656740 root_dev_scan_bus for Root Device done
5231 01:54:33.663131 scan_bus: scanning of bus Root Device took 10689 usecs
5232 01:54:33.663587 done
5233 01:54:33.666726 BS: BS_DEV_ENUMERATE times (ms): entry 0 run 0 exit 0
5234 01:54:33.670228 Allocating resources...
5235 01:54:33.673434 Reading resources...
5236 01:54:33.676904 Root Device read_resources bus 0 link: 0
5237 01:54:33.679900 CPU_CLUSTER: 0 read_resources bus 0 link: 0
5238 01:54:33.682969 CPU: 00 missing read_resources
5239 01:54:33.686076 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
5240 01:54:33.689283 Root Device read_resources bus 0 link: 0 done
5241 01:54:33.693127 Done reading resources.
5242 01:54:33.696059 Show resources in subtree (Root Device)...After reading.
5243 01:54:33.702585 Root Device child on link 0 CPU_CLUSTER: 0
5244 01:54:33.705939 CPU_CLUSTER: 0 child on link 0 CPU: 00
5245 01:54:33.712547 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
5246 01:54:33.716017 CPU: 00
5247 01:54:33.716582 Setting resources...
5248 01:54:33.722514 Root Device assign_resources, bus 0 link: 0
5249 01:54:33.725340 CPU_CLUSTER: 0 missing set_resources
5250 01:54:33.729185 Root Device assign_resources, bus 0 link: 0
5251 01:54:33.729743 Done setting resources.
5252 01:54:33.735247 Show resources in subtree (Root Device)...After assigning values.
5253 01:54:33.738660 Root Device child on link 0 CPU_CLUSTER: 0
5254 01:54:33.741824 CPU_CLUSTER: 0 child on link 0 CPU: 00
5255 01:54:33.751870 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
5256 01:54:33.752447 CPU: 00
5257 01:54:33.754919 Done allocating resources.
5258 01:54:33.761671 BS: BS_DEV_RESOURCES times (ms): entry 0 run 0 exit 0
5259 01:54:33.762186 Enabling resources...
5260 01:54:33.762532 done.
5261 01:54:33.768096 BS: BS_DEV_ENABLE times (ms): entry 0 run 0 exit 0
5262 01:54:33.768528 Initializing devices...
5263 01:54:33.771924 Root Device init ...
5264 01:54:33.774828 mainboard_init: Starting display init.
5265 01:54:33.778028 ADC[4]: Raw value=75908 ID=0
5266 01:54:33.800535 anx7625_power_on_init: Init interface.
5267 01:54:33.803698 anx7625_disable_pd_protocol: Disabled PD feature.
5268 01:54:33.809780 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
5269 01:54:33.856791 anx7625_start_dp_work: Secure OCM version=00
5270 01:54:33.860118 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
5271 01:54:33.877931 sp_tx_get_edid_block: EDID Block = 1
5272 01:54:33.994803 Extracted contents:
5273 01:54:33.998268 header: 00 ff ff ff ff ff ff 00
5274 01:54:34.001461 serial number: 06 af 5c 14 00 00 00 00 00 1a
5275 01:54:34.004516 version: 01 04
5276 01:54:34.008001 basic params: 95 1a 0e 78 02
5277 01:54:34.011362 chroma info: 99 85 95 55 56 92 28 22 50 54
5278 01:54:34.014728 established: 00 00 00
5279 01:54:34.021502 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
5280 01:54:34.027477 descriptor 1: ce 1d 56 ea 50 00 1a 30 30 20 46 00 00 90 10 00 00 18
5281 01:54:34.030863 descriptor 2: 00 00 00 0f 00 00 00 00 00 00 00 00 00 00 00 00 00 20
5282 01:54:34.037483 descriptor 3: 00 00 00 fe 00 41 55 4f 0a 20 20 20 20 20 20 20 20 20
5283 01:54:34.043757 descriptor 4: 00 00 00 fe 00 42 31 31 36 58 41 42 30 31 2e 34 20 0a
5284 01:54:34.047180 extensions: 00
5285 01:54:34.047608 checksum: ae
5286 01:54:34.047946
5287 01:54:34.054168 Manufacturer: AUO Model 145c Serial Number 0
5288 01:54:34.054682 Made week 0 of 2016
5289 01:54:34.057352 EDID version: 1.4
5290 01:54:34.057924 Digital display
5291 01:54:34.060206 6 bits per primary color channel
5292 01:54:34.063131 DisplayPort interface
5293 01:54:34.063207 Maximum image size: 26 cm x 14 cm
5294 01:54:34.066674 Gamma: 220%
5295 01:54:34.066813 Check DPMS levels
5296 01:54:34.069934 Supported color formats: RGB 4:4:4
5297 01:54:34.073183 First detailed timing is preferred timing
5298 01:54:34.076330 Established timings supported:
5299 01:54:34.079462 Standard timings supported:
5300 01:54:34.082976 Detailed timings
5301 01:54:34.086128 Hex of detail: ce1d56ea50001a3030204600009010000018
5302 01:54:34.089659 Detailed mode (IN HEX): Clock 76300 KHz, 100 mm x 90 mm
5303 01:54:34.096147 0556 0586 05a6 0640 hborder 0
5304 01:54:34.099319 0300 0304 030a 031a vborder 0
5305 01:54:34.102864 -hsync -vsync
5306 01:54:34.103092 Did detailed timing
5307 01:54:34.109397 Hex of detail: 0000000f0000000000000000000000000020
5308 01:54:34.112747 Manufacturer-specified data, tag 15
5309 01:54:34.116520 Hex of detail: 000000fe0041554f0a202020202020202020
5310 01:54:34.117028 ASCII string: AUO
5311 01:54:34.122734 Hex of detail: 000000fe004231313658414230312e34200a
5312 01:54:34.125692 ASCII string: B116XAB01.4
5313 01:54:34.126121 Checksum
5314 01:54:34.126454 Checksum: 0xae (valid)
5315 01:54:34.132592 get_active_panel: Found ID 1: 'AUO B116XAB01.4 ' 1366x768@0Hz
5316 01:54:34.135718 DSI data_rate: 457800000 bps
5317 01:54:34.142383 anx7625_parse_edid: set default k value to 0x3d for panel
5318 01:54:34.145773 anx7625_parse_edid: pixelclock(76300).
5319 01:54:34.148358 hactive(1366), hsync(32), hfp(48), hbp(154)
5320 01:54:34.151905 vactive(768), vsync(6), vfp(4), vbp(16)
5321 01:54:34.155832 anx7625_dsi_config: config dsi.
5322 01:54:34.162627 anx7625_dsi_video_config: compute M(12500992), N(552960), divider(8).
5323 01:54:34.183939 anx7625_dsi_config: success to config DSI
5324 01:54:34.187119 anx7625_dp_start: MIPI phy setup OK.
5325 01:54:34.190277 [SSUSB] Setting up USB HOST controller...
5326 01:54:34.193444 [SSUSB] u3phy_ports_enable u2p:1, u3p:0
5327 01:54:34.196904 [SSUSB] phy power-on done.
5328 01:54:34.201230 out: cmd=0xf: 03 da 0f 00 00 00 04 00 10 00 00 00
5329 01:54:34.204254 in-header: 03 fc 01 00 00 00 00 00
5330 01:54:34.204680 in-data:
5331 01:54:34.210524 handle_proto3_response: EC response with error code: 1
5332 01:54:34.211027 SPM: pcm index = 1
5333 01:54:34.217295 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5334 01:54:34.217833 CBFS @ 21000 size 3d4000
5335 01:54:34.223710 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5336 01:54:34.227312 CBFS: Locating 'pcm_allinone_lp4_3200.bin'
5337 01:54:34.230831 CBFS: Found @ offset 1e7c0 size 1026
5338 01:54:34.237254 read SPI 0x3f808 0x1026: 1271 us, 3252 KB/s, 26.016 Mbps
5339 01:54:34.240645 SPM: binary array size = 2988
5340 01:54:34.243390 SPM: version = pcm_allinone_v1.17.2_20180829
5341 01:54:34.246947 SPM binary loaded in 32 msecs
5342 01:54:34.255455 spm_kick_im_to_fetch: ptr = 000000004021eec2
5343 01:54:34.258374 spm_kick_im_to_fetch: len = 2988
5344 01:54:34.258801 SPM: spm_kick_pcm_to_run
5345 01:54:34.262039 SPM: spm_kick_pcm_to_run done
5346 01:54:34.265291 SPM: spm_init done in 52 msecs
5347 01:54:34.268401 Root Device init finished in 495375 usecs
5348 01:54:34.271815 CPU_CLUSTER: 0 init ...
5349 01:54:34.281518 Mapping address range [0000000000200000:0000000000280000) as cacheable | read-write | secure | device
5350 01:54:34.284762 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5351 01:54:34.288106 CBFS @ 21000 size 3d4000
5352 01:54:34.291534 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5353 01:54:34.294776 CBFS: Locating 'sspm.bin'
5354 01:54:34.298016 CBFS: Found @ offset 208c0 size 41cb
5355 01:54:34.308726 read SPI 0x418f8 0x41cb: 5142 us, 3275 KB/s, 26.200 Mbps
5356 01:54:34.316476 CPU_CLUSTER: 0 init finished in 42799 usecs
5357 01:54:34.316976 Devices initialized
5358 01:54:34.319889 Show all devs... After init.
5359 01:54:34.322987 Root Device: enabled 1
5360 01:54:34.323412 CPU_CLUSTER: 0: enabled 1
5361 01:54:34.326492 CPU: 00: enabled 1
5362 01:54:34.329808 BS: BS_DEV_INIT times (ms): entry 0 run 224 exit 0
5363 01:54:34.336153 FMAP: area RW_ELOG found @ 558000 (4096 bytes)
5364 01:54:34.339039 ELOG: NV offset 0x558000 size 0x1000
5365 01:54:34.342831 read SPI 0x558000 0x1000: 1264 us, 3240 KB/s, 25.920 Mbps
5366 01:54:34.349232 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
5367 01:54:34.356050 ELOG: Event(17) added with size 13 at 2024-06-21 01:54:34 UTC
5368 01:54:34.358923 out: cmd=0x121: 03 db 21 01 00 00 00 00
5369 01:54:34.362179 in-header: 03 a9 00 00 2c 00 00 00
5370 01:54:34.375803 in-data: 2d 4b 00 00 00 00 00 00 02 10 00 00 06 80 00 00 f5 0b 01 00 06 80 00 00 fb 36 02 00 06 80 00 00 f7 63 01 00 06 80 00 00 a4 51 02 00
5371 01:54:34.379660 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
5372 01:54:34.382244 in-header: 03 19 00 00 08 00 00 00
5373 01:54:34.385702 in-data: a2 e0 47 00 13 00 00 00
5374 01:54:34.386274 Chrome EC: UHEPI supported
5375 01:54:34.395285 out: cmd=0xa4: 03 54 a4 00 00 00 0c 00 00 01 00 00 f8 ff 01 00 00 00 00 00
5376 01:54:34.398332 in-header: 03 e1 00 00 08 00 00 00
5377 01:54:34.398762 in-data: 84 20 60 10 00 00 00 00
5378 01:54:34.404896 FMAP: area RW_NVRAM found @ 554000 (8192 bytes)
5379 01:54:34.411749 out: cmd=0xa4: 03 c9 a4 00 00 00 0c 00 00 01 00 00 00 20 23 40 00 00 00 00
5380 01:54:34.414943 in-header: 03 e1 00 00 08 00 00 00
5381 01:54:34.418193 in-data: 84 20 60 10 00 00 00 00
5382 01:54:34.421926 ELOG: Event(A1) added with size 10 at 2024-06-21 01:54:34 UTC
5383 01:54:34.428585 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
5384 01:54:34.435130 ELOG: Event(A0) added with size 9 at 2024-06-21 01:54:34 UTC
5385 01:54:34.438272 elog_add_boot_reason: Logged dev mode boot
5386 01:54:34.440943 Finalize devices...
5387 01:54:34.441374 Devices finalized
5388 01:54:34.447407 BS: BS_POST_DEVICE times (ms): entry 2 run 0 exit 0
5389 01:54:34.451264 BS: BS_OS_RESUME_CHECK times (ms): entry 0 run 0 exit 0
5390 01:54:34.457670 ELOG: Event(91) added with size 10 at 2024-06-21 01:54:34 UTC
5391 01:54:34.460830 Writing coreboot table at 0xffeda000
5392 01:54:34.464145 0. 0000000000114000-000000000011efff: RAMSTAGE
5393 01:54:34.467364 1. 0000000040000000-000000004023cfff: RAMSTAGE
5394 01:54:34.474043 2. 000000004023d000-00000000545fffff: RAM
5395 01:54:34.477465 3. 0000000054600000-000000005465ffff: BL31
5396 01:54:34.480826 4. 0000000054660000-00000000ffed9fff: RAM
5397 01:54:34.487476 5. 00000000ffeda000-00000000ffffffff: CONFIGURATION TABLES
5398 01:54:34.490860 6. 0000000100000000-000000013fffffff: RAM
5399 01:54:34.491242 Passing 5 GPIOs to payload:
5400 01:54:34.496989 NAME | PORT | POLARITY | VALUE
5401 01:54:34.500248 write protect | 0x00000096 | low | high
5402 01:54:34.507163 EC in RW | 0x000000b1 | high | undefined
5403 01:54:34.510385 EC interrupt | 0x00000097 | low | undefined
5404 01:54:34.517046 TPM interrupt | 0x00000099 | high | undefined
5405 01:54:34.520447 speaker enable | 0x000000af | high | undefined
5406 01:54:34.523304 out: cmd=0x6: 03 f7 06 00 00 00 00 00
5407 01:54:34.526591 in-header: 03 f7 00 00 02 00 00 00
5408 01:54:34.529892 in-data: 04 00
5409 01:54:34.530377 Board ID: 4
5410 01:54:34.533697 ADC[3]: Raw value=213471 ID=1
5411 01:54:34.534166 RAM code: 1
5412 01:54:34.534473 SKU ID: 16
5413 01:54:34.540576 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5414 01:54:34.541062 CBFS @ 21000 size 3d4000
5415 01:54:34.546845 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5416 01:54:34.552750 Wrote coreboot table at: 00000000ffeda000, 0x394 bytes, checksum 2997
5417 01:54:34.556399 coreboot table: 940 bytes.
5418 01:54:34.559363 IMD ROOT 0. 00000000fffff000 00001000
5419 01:54:34.562465 IMD SMALL 1. 00000000ffffe000 00001000
5420 01:54:34.565688 CONSOLE 2. 00000000fffde000 00020000
5421 01:54:34.569353 FMAP 3. 00000000fffdd000 0000047c
5422 01:54:34.572457 TIME STAMP 4. 00000000fffdc000 00000910
5423 01:54:34.576129 RAMOOPS 5. 00000000ffedc000 00100000
5424 01:54:34.578765 COREBOOT 6. 00000000ffeda000 00002000
5425 01:54:34.582006 IMD small region:
5426 01:54:34.586261 IMD ROOT 0. 00000000ffffec00 00000400
5427 01:54:34.589066 VBOOT WORK 1. 00000000ffffeb00 00000100
5428 01:54:34.592744 EC HOSTEVENT 2. 00000000ffffeae0 00000008
5429 01:54:34.598777 VPD 3. 00000000ffffea60 0000006c
5430 01:54:34.602119 BS: BS_WRITE_TABLES times (ms): entry 0 run 0 exit 0
5431 01:54:34.608955 out: cmd=0xa4: 03 95 a4 00 00 00 0c 00 00 01 00 00 24 32 21 40 00 00 00 00
5432 01:54:34.612309 in-header: 03 e1 00 00 08 00 00 00
5433 01:54:34.615261 in-data: 84 20 60 10 00 00 00 00
5434 01:54:34.618556 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5435 01:54:34.621741 CBFS @ 21000 size 3d4000
5436 01:54:34.628485 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5437 01:54:34.629000 CBFS: Locating 'fallback/payload'
5438 01:54:34.638323 CBFS: Found @ offset dc040 size 439a0
5439 01:54:34.726136 read SPI 0xfd078 0x439a0: 84379 us, 3281 KB/s, 26.248 Mbps
5440 01:54:34.729043 Checking segment from ROM address 0x0000000040003a00
5441 01:54:34.735958 Checking segment from ROM address 0x0000000040003a1c
5442 01:54:34.739004 Loading segment from ROM address 0x0000000040003a00
5443 01:54:34.742429 code (compression=0)
5444 01:54:34.752457 New segment dstaddr 0x0000000080000000 memsize 0x11994a0 srcaddr 0x0000000040003a38 filesize 0x43968
5445 01:54:34.758441 Loading Segment: addr: 0x0000000080000000 memsz: 0x00000000011994a0 filesz: 0x0000000000043968
5446 01:54:34.761959 it's not compressed!
5447 01:54:34.766124 [ 0x80000000, 80043968, 0x811994a0) <- 40003a38
5448 01:54:34.771569 Clearing Segment: addr: 0x0000000080043968 memsz: 0x0000000001155b38
5449 01:54:34.780796 Loading segment from ROM address 0x0000000040003a1c
5450 01:54:34.783874 Entry Point 0x0000000080000000
5451 01:54:34.784390 Loaded segments
5452 01:54:34.790161 BS: BS_PAYLOAD_LOAD times (ms): entry 0 run 92 exit 0
5453 01:54:34.793352 Jumping to boot code at 0000000080000000(00000000ffeda000)
5454 01:54:34.803499 CPU0: stack: 0000000000114000 - 0000000000118000, lowest used address 0000000000117540, stack used: 2752 bytes
5455 01:54:34.809870 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5456 01:54:34.810398 CBFS @ 21000 size 3d4000
5457 01:54:34.816458 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5458 01:54:34.820074 CBFS: Locating 'fallback/bl31'
5459 01:54:34.823028 CBFS: Found @ offset 36dc0 size 5820
5460 01:54:34.834945 read SPI 0x57de8 0x5820: 6880 us, 3279 KB/s, 26.232 Mbps
5461 01:54:34.837380 Checking segment from ROM address 0x0000000040003a00
5462 01:54:34.843984 Checking segment from ROM address 0x0000000040003a1c
5463 01:54:34.847259 Loading segment from ROM address 0x0000000040003a00
5464 01:54:34.850560 code (compression=1)
5465 01:54:34.860270 New segment dstaddr 0x0000000054600000 memsize 0x29000 srcaddr 0x0000000040003a38 filesize 0x57e8
5466 01:54:34.866565 Loading Segment: addr: 0x0000000054600000 memsz: 0x0000000000029000 filesz: 0x00000000000057e8
5467 01:54:34.867005 using LZMA
5468 01:54:34.875874 [ 0x54600000, 5460f420, 0x54629000) <- 40003a38
5469 01:54:34.882850 Clearing Segment: addr: 0x000000005460f420 memsz: 0x0000000000019be0
5470 01:54:34.885537 Loading segment from ROM address 0x0000000040003a1c
5471 01:54:34.889180 Entry Point 0x0000000054601000
5472 01:54:34.889609 Loaded segments
5473 01:54:34.892238 NOTICE: MT8183 bl31_setup
5474 01:54:34.899690 NOTICE: BL31: v2.1(debug):v2.1-806-g3addeb68c
5475 01:54:34.903155 NOTICE: BL31: Built : Sun Jan 30 03:25:20 UTC 2022
5476 01:54:34.906357 INFO: [DEVAPC] dump DEVAPC registers:
5477 01:54:34.916131 INFO: [DEVAPC] (INFRA)D0_APC_0 = 0x0, (INFRA)D1_APC_0 = 0xfcfffffc, (INFRA)D2_APC_0 = 0x0
5478 01:54:34.922593 INFO: [DEVAPC] (INFRA)D0_APC_1 = 0x0, (INFRA)D1_APC_1 = 0xffffffff, (INFRA)D2_APC_1 = 0x0
5479 01:54:34.932348 INFO: [DEVAPC] (INFRA)D0_APC_2 = 0x0, (INFRA)D1_APC_2 = 0xffffffff, (INFRA)D2_APC_2 = 0x0
5480 01:54:34.939029 INFO: [DEVAPC] (INFRA)D0_APC_3 = 0x0, (INFRA)D1_APC_3 = 0xffffffff, (INFRA)D2_APC_3 = 0x0
5481 01:54:34.949450 INFO: [DEVAPC] (INFRA)D0_APC_4 = 0x80000000, (INFRA)D1_APC_4 = 0xffffffff, (INFRA)D2_APC_4 = 0x0
5482 01:54:34.955500 INFO: [DEVAPC] (INFRA)D0_APC_5 = 0x2aaa, (INFRA)D1_APC_5 = 0xfcff3fff, (INFRA)D2_APC_5 = 0x0
5483 01:54:34.965518 INFO: [DEVAPC] (INFRA)D0_APC_6 = 0x0, (INFRA)D1_APC_6 = 0xffffffff, (INFRA)D2_APC_6 = 0x0
5484 01:54:34.972248 INFO: [DEVAPC] (INFRA)D0_APC_7 = 0x0, (INFRA)D1_APC_7 = 0xffffffff, (INFRA)D2_APC_7 = 0x0
5485 01:54:34.982115 INFO: [DEVAPC] (INFRA)D0_APC_8 = 0x0, (INFRA)D1_APC_8 = 0xffffffff, (INFRA)D2_APC_8 = 0x0
5486 01:54:34.988532 INFO: [DEVAPC] (INFRA)D0_APC_9 = 0x0, (INFRA)D1_APC_9 = 0xffffffff, (INFRA)D2_APC_9 = 0x0
5487 01:54:34.998167 INFO: [DEVAPC] (INFRA)D0_APC_10 = 0x0, (INFRA)D1_APC_10 = 0xffffffff, (INFRA)D2_APC_10 = 0x0
5488 01:54:35.005115 INFO: [DEVAPC] (INFRA)D0_APC_11 = 0x0, (INFRA)D1_APC_11 = 0xffffffff, (INFRA)D2_APC_11 = 0x0
5489 01:54:35.015008 INFO: [DEVAPC] (INFRA)D0_APC_12 = 0x0, (INFRA)D1_APC_12 = 0xff, (INFRA)D2_APC_12 = 0x0
5490 01:54:35.021747 INFO: [DEVAPC] (MM)D0_APC_0 = 0x0, (MM)D1_APC_0 = 0xffc000ff, (MM)D2_APC_0 = 0x0
5491 01:54:35.028098 INFO: [DEVAPC] (MM)D0_APC_1 = 0x0, (MM)D1_APC_1 = 0x3fffffff, (MM)D2_APC_1 = 0x0
5492 01:54:35.034271 INFO: [DEVAPC] (MM)D0_APC_2 = 0x0, (MM)D1_APC_2 = 0xcffff33c, (MM)D2_APC_2 = 0x0
5493 01:54:35.044234 INFO: [DEVAPC] (MM)D0_APC_3 = 0x0, (MM)D1_APC_3 = 0x3ccfc0ff, (MM)D2_APC_3 = 0x0
5494 01:54:35.050809 INFO: [DEVAPC] (MM)D0_APC_4 = 0x0, (MM)D1_APC_4 = 0xffff0000, (MM)D2_APC_4 = 0x0
5495 01:54:35.057104 INFO: [DEVAPC] (MM)D0_APC_5 = 0x0, (MM)D1_APC_5 = 0xffffffff, (MM)D2_APC_5 = 0x0
5496 01:54:35.063639 INFO: [DEVAPC] (MM)D0_APC_6 = 0x0, (MM)D1_APC_6 = 0xffffffff, (MM)D2_APC_6 = 0x0
5497 01:54:35.073991 INFO: [DEVAPC] (MM)D0_APC_7 = 0x0, (MM)D1_APC_7 = 0xffffffff, (MM)D2_APC_7 = 0x0
5498 01:54:35.080496 INFO: [DEVAPC] (MM)D0_APC_8 = 0x0, (MM)D1_APC_8 = 0x3ffffff, (MM)D2_APC_8 = 0x0
5499 01:54:35.083305 INFO: [DEVAPC] MAS_DOM_0 = 0x1
5500 01:54:35.086703 INFO: [DEVAPC] MAS_DOM_1 = 0x200
5501 01:54:35.090236 INFO: [DEVAPC] MAS_DOM_2 = 0x0
5502 01:54:35.093268 INFO: [DEVAPC] MAS_DOM_3 = 0x2000
5503 01:54:35.096922 INFO: [DEVAPC] MAS_SEC_0 = 0x8000000
5504 01:54:35.103096 INFO: [DEVAPC] (INFRA)MAS_DOMAIN_REMAP_0 = 0x88, (INFRA)MAS_DOMAIN_REMAP_1 = 0x0
5505 01:54:35.106971 INFO: [DEVAPC] (MM)MAS_DOMAIN_REMAP_0 = 0x24
5506 01:54:35.110105 WARNING: region 0:
5507 01:54:35.113240 WARNING: apc:0x168, sa:0x0, ea:0xfff
5508 01:54:35.113797 WARNING: region 1:
5509 01:54:35.119613 WARNING: apc:0x140, sa:0x1000, ea:0x128f
5510 01:54:35.120124 WARNING: region 2:
5511 01:54:35.122637 WARNING: apc:0x168, sa:0x1290, ea:0x1fff
5512 01:54:35.126196 WARNING: region 3:
5513 01:54:35.129586 WARNING: apc:0x168, sa:0x2000, ea:0xbfff
5514 01:54:35.130110 WARNING: region 4:
5515 01:54:35.136191 WARNING: apc:0x168, sa:0xc000, ea:0x1ffff
5516 01:54:35.136689 WARNING: region 5:
5517 01:54:35.138937 WARNING: apc:0x0, sa:0x0, ea:0x0
5518 01:54:35.139374 WARNING: region 6:
5519 01:54:35.142224 WARNING: apc:0x0, sa:0x0, ea:0x0
5520 01:54:35.145639 WARNING: region 7:
5521 01:54:35.149537 WARNING: apc:0x0, sa:0x0, ea:0x0
5522 01:54:35.155958 INFO: GICv3 without legacy support detected. ARM GICv3 driver initialized in EL3
5523 01:54:35.159007 INFO: SPM: enable SPMC mode
5524 01:54:35.161959 NOTICE: spm_boot_init() start
5525 01:54:35.165485 NOTICE: spm_boot_init() end
5526 01:54:35.168968 INFO: BL31: Initializing runtime services
5527 01:54:35.175596 INFO: BL31: cortex_a53: CPU workaround for 855873 was applied
5528 01:54:35.179012 INFO: BL31: Preparing for EL3 exit to normal world
5529 01:54:35.182363 INFO: Entry point address = 0x80000000
5530 01:54:35.184916 INFO: SPSR = 0x8
5531 01:54:35.206477
5532 01:54:35.206977
5533 01:54:35.207311
5534 01:54:35.209781 Starting depthcharge on Juniper...
5535 01:54:35.210288
5536 01:54:35.211976 end: 2.2.3 depthcharge-start (duration 00:00:24) [common]
5537 01:54:35.212614 start: 2.2.4 bootloader-commands (timeout 00:04:27) [common]
5538 01:54:35.213035 Setting prompt string to ['jacuzzi:']
5539 01:54:35.213589 bootloader-commands: Wait for prompt ['jacuzzi:'] (timeout 00:04:27)
5540 01:54:35.214423 vboot_handoff: creating legacy vboot_handoff structure
5541 01:54:35.214799
5542 01:54:35.215901 ec_init(0): CrosEC protocol v3 supported (544, 544)
5543 01:54:35.219263
5544 01:54:35.219769 Wipe memory regions:
5545 01:54:35.220112
5546 01:54:35.222687 [0x00000040000000, 0x00000054600000)
5547 01:54:35.265447
5548 01:54:35.266005 [0x00000054660000, 0x00000080000000)
5549 01:54:35.357394
5550 01:54:35.357930 [0x000000811994a0, 0x000000ffeda000)
5551 01:54:35.617051
5552 01:54:35.617649 [0x00000100000000, 0x00000140000000)
5553 01:54:35.749765
5554 01:54:35.753130 Initializing XHCI USB controller at 0x11200000.
5555 01:54:35.776656
5556 01:54:35.779478 [firmware-jacuzzi-12573.B-collabora] Jun 8 2022 08:18:54
5557 01:54:35.779914
5558 01:54:35.780261
5559 01:54:35.781160 Setting prompt string to ['jacuzzi:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5561 01:54:35.882585 jacuzzi: tftpboot 192.168.201.1 14479155/tftp-deploy-8daa0ozx/kernel/image.itb 14479155/tftp-deploy-8daa0ozx/kernel/cmdline
5562 01:54:35.883302 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5563 01:54:35.883831 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:26)
5564 01:54:35.888610 tftpboot 192.168.201.1 14479155/tftp-deploy-8daa0ozx/kernel/image.itbtp-deploy-8daa0ozx/kernel/cmdline
5565 01:54:35.889133
5566 01:54:35.889478 Waiting for link
5567 01:54:36.290239
5568 01:54:36.290759 R8152: Initializing
5569 01:54:36.291109
5570 01:54:36.293318 Version 9 (ocp_data = 6010)
5571 01:54:36.293885
5572 01:54:36.296443 R8152: Done initializing
5573 01:54:36.296877
5574 01:54:36.297217 Adding net device
5575 01:54:36.682122
5576 01:54:36.682634 done.
5577 01:54:36.682976
5578 01:54:36.683291 MAC: 00:e0:4c:72:3d:a6
5579 01:54:36.683591
5580 01:54:36.685513 Sending DHCP discover... done.
5581 01:54:36.686127
5582 01:54:36.688763 Waiting for reply... done.
5583 01:54:36.689229
5584 01:54:36.691615 Sending DHCP request... done.
5585 01:54:36.692051
5586 01:54:36.698410 Waiting for reply... done.
5587 01:54:36.698934
5588 01:54:36.699277 My ip is 192.168.201.20
5589 01:54:36.699593
5590 01:54:36.701721 The DHCP server ip is 192.168.201.1
5591 01:54:36.702163
5592 01:54:36.708323 TFTP server IP predefined by user: 192.168.201.1
5593 01:54:36.708849
5594 01:54:36.714382 Bootfile predefined by user: 14479155/tftp-deploy-8daa0ozx/kernel/image.itb
5595 01:54:36.714984
5596 01:54:36.717898 Sending tftp read request... done.
5597 01:54:36.718419
5598 01:54:36.725427 Waiting for the transfer...
5599 01:54:36.726002
5600 01:54:37.118311 00000000 ################################################################
5601 01:54:37.118439
5602 01:54:37.387931 00080000 ################################################################
5603 01:54:37.388062
5604 01:54:37.675190 00100000 ################################################################
5605 01:54:37.675315
5606 01:54:37.965080 00180000 ################################################################
5607 01:54:37.965196
5608 01:54:38.253460 00200000 ################################################################
5609 01:54:38.253635
5610 01:54:38.522772 00280000 ################################################################
5611 01:54:38.522917
5612 01:54:38.777343 00300000 ################################################################
5613 01:54:38.777491
5614 01:54:39.043439 00380000 ################################################################
5615 01:54:39.043566
5616 01:54:39.323207 00400000 ################################################################
5617 01:54:39.323337
5618 01:54:39.616844 00480000 ################################################################
5619 01:54:39.616976
5620 01:54:39.907446 00500000 ################################################################
5621 01:54:39.907576
5622 01:54:40.205734 00580000 ################################################################
5623 01:54:40.205864
5624 01:54:40.502985 00600000 ################################################################
5625 01:54:40.503114
5626 01:54:40.795593 00680000 ################################################################
5627 01:54:40.795721
5628 01:54:41.048545 00700000 ################################################################
5629 01:54:41.048694
5630 01:54:41.302020 00780000 ################################################################
5631 01:54:41.302142
5632 01:54:41.601320 00800000 ################################################################
5633 01:54:41.601530
5634 01:54:41.961636 00880000 ################################################################
5635 01:54:41.962112
5636 01:54:42.312694 00900000 ################################################################
5637 01:54:42.312821
5638 01:54:42.600657 00980000 ################################################################
5639 01:54:42.600785
5640 01:54:42.865761 00a00000 ################################################################
5641 01:54:42.865888
5642 01:54:43.126646 00a80000 ################################################################
5643 01:54:43.126776
5644 01:54:43.391458 00b00000 ################################################################
5645 01:54:43.391585
5646 01:54:43.667127 00b80000 ################################################################
5647 01:54:43.667255
5648 01:54:43.932454 00c00000 ################################################################
5649 01:54:43.932617
5650 01:54:44.210733 00c80000 ################################################################
5651 01:54:44.210861
5652 01:54:44.481781 00d00000 ################################################################
5653 01:54:44.481908
5654 01:54:44.740655 00d80000 ################################################################
5655 01:54:44.740782
5656 01:54:45.005667 00e00000 ################################################################
5657 01:54:45.005787
5658 01:54:45.262733 00e80000 ################################################################
5659 01:54:45.262859
5660 01:54:45.526357 00f00000 ################################################################
5661 01:54:45.526505
5662 01:54:45.784785 00f80000 ################################################################
5663 01:54:45.784922
5664 01:54:46.054969 01000000 ################################################################
5665 01:54:46.055093
5666 01:54:46.319372 01080000 ################################################################
5667 01:54:46.319500
5668 01:54:46.605093 01100000 ################################################################
5669 01:54:46.605220
5670 01:54:46.892730 01180000 ################################################################
5671 01:54:46.892864
5672 01:54:47.181042 01200000 ################################################################
5673 01:54:47.181167
5674 01:54:47.458604 01280000 ################################################################
5675 01:54:47.458731
5676 01:54:47.725077 01300000 ################################################################
5677 01:54:47.725195
5678 01:54:47.991488 01380000 ################################################################
5679 01:54:47.991612
5680 01:54:48.281314 01400000 ################################################################
5681 01:54:48.281439
5682 01:54:48.568608 01480000 ################################################################
5683 01:54:48.568735
5684 01:54:48.829031 01500000 ################################################################
5685 01:54:48.829159
5686 01:54:49.089311 01580000 ################################################################
5687 01:54:49.089455
5688 01:54:49.344642 01600000 ################################################################
5689 01:54:49.344761
5690 01:54:49.596901 01680000 ################################################################
5691 01:54:49.597022
5692 01:54:49.885866 01700000 ################################################################
5693 01:54:49.885990
5694 01:54:50.146558 01780000 ################################################################
5695 01:54:50.146677
5696 01:54:50.425302 01800000 ################################################################
5697 01:54:50.425427
5698 01:54:50.725451 01880000 ################################################################
5699 01:54:50.725611
5700 01:54:51.006979 01900000 ################################################################
5701 01:54:51.007102
5702 01:54:51.264929 01980000 ################################################################
5703 01:54:51.265047
5704 01:54:51.546574 01a00000 ################################################################
5705 01:54:51.546687
5706 01:54:51.803042 01a80000 ################################################################
5707 01:54:51.803176
5708 01:54:52.056339 01b00000 ################################################################
5709 01:54:52.056474
5710 01:54:52.310204 01b80000 ################################################################
5711 01:54:52.310343
5712 01:54:52.563138 01c00000 ################################################################
5713 01:54:52.563268
5714 01:54:52.816457 01c80000 ################################################################
5715 01:54:52.816587
5716 01:54:53.069884 01d00000 ################################################################
5717 01:54:53.070025
5718 01:54:53.323208 01d80000 ################################################################
5719 01:54:53.323338
5720 01:54:53.552149 01e00000 ########################################################### done.
5721 01:54:53.552276
5722 01:54:53.555105 The bootfile was 31933046 bytes long.
5723 01:54:53.555184
5724 01:54:53.558309 Sending tftp read request... done.
5725 01:54:53.558386
5726 01:54:53.561731 Waiting for the transfer...
5727 01:54:53.561809
5728 01:54:53.561869 00000000 # done.
5729 01:54:53.561926
5730 01:54:53.568266 Command line loaded dynamically from TFTP file: 14479155/tftp-deploy-8daa0ozx/kernel/cmdline
5731 01:54:53.571817
5732 01:54:53.594581 The command line is: earlyprintk=ttyS0,115200n8 console=tty1 console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14479155/extract-nfsrootfs-t4oh8com,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
5733 01:54:53.594663
5734 01:54:53.597641 Loading FIT.
5735 01:54:53.597716
5736 01:54:53.601180 Image ramdisk-1 has 18748413 bytes.
5737 01:54:53.601256
5738 01:54:53.601315 Image fdt-1 has 57695 bytes.
5739 01:54:53.601369
5740 01:54:53.604519 Image kernel-1 has 13124896 bytes.
5741 01:54:53.604595
5742 01:54:53.614406 Compat preference: google,juniper-rev4-sku16 google,juniper-sku16 google,juniper-rev4 google,juniper
5743 01:54:53.614483
5744 01:54:53.627034 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,juniper-sku16 (match) google,juniper mediatek,mt8183
5745 01:54:53.627114
5746 01:54:53.630871 Choosing best match conf-1 for compat google,juniper-sku16.
5747 01:54:53.635540
5748 01:54:53.640621 Connected to device vid:did:rid of 1ae0:0028:00
5749 01:54:53.648625
5750 01:54:53.652042 tpm_get_response: command 0x17b, return code 0x0
5751 01:54:53.652119
5752 01:54:53.655227 tpm_cleanup: add release locality here.
5753 01:54:53.655304
5754 01:54:53.658367 Shutting down all USB controllers.
5755 01:54:53.658444
5756 01:54:53.661498 Removing current net device
5757 01:54:53.661597
5758 01:54:53.665218 Exiting depthcharge with code 4 at timestamp: 35656034
5759 01:54:53.665295
5760 01:54:53.668181 LZMA decompressing kernel-1 to 0x80193568
5761 01:54:53.671434
5762 01:54:53.674647 LZMA decompressing kernel-1 to 0x40000000
5763 01:54:55.538726
5764 01:54:55.538844 jumping to kernel
5765 01:54:55.539316 end: 2.2.4 bootloader-commands (duration 00:00:20) [common]
5766 01:54:55.539408 start: 2.2.5 auto-login-action (timeout 00:04:06) [common]
5767 01:54:55.539477 Setting prompt string to ['Linux version [0-9]']
5768 01:54:55.539539 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5769 01:54:55.539601 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
5770 01:54:55.614068
5771 01:54:55.617475 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
5772 01:54:55.621173 start: 2.2.5.1 login-action (timeout 00:04:06) [common]
5773 01:54:55.621272 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
5774 01:54:55.621342 Setting prompt string to []
5775 01:54:55.621420 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
5776 01:54:55.621486 Using line separator: #'\n'#
5777 01:54:55.621541 No login prompt set.
5778 01:54:55.621610 Parsing kernel messages
5779 01:54:55.621667 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
5780 01:54:55.621771 [login-action] Waiting for messages, (timeout 00:04:06)
5781 01:54:55.621837 Waiting using forced prompt support (timeout 00:02:03)
5782 01:54:55.640776 [ 0.000000] Linux version 6.1.94-cip23 (KernelCI@build-j239242-arm64-gcc-10-defconfig-arm64-chromebook-c5lwc) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Jun 21 00:04:56 UTC 2024
5783 01:54:55.644076 [ 0.000000] random: crng init done
5784 01:54:55.650073 [ 0.000000] Machine model: Google juniper sku16 board
5785 01:54:55.653511 [ 0.000000] efi: UEFI not found.
5786 01:54:55.660235 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
5787 01:54:55.669888 [ 0.000000] OF: reserved mem: initialized node memory@50000000, compatible id shared-dma-pool
5788 01:54:55.676706 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
5789 01:54:55.680032 [ 0.000000] printk: bootconsole [mtk8250] enabled
5790 01:54:55.689138 [ 0.000000] NUMA: No NUMA configuration found
5791 01:54:55.695735 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
5792 01:54:55.702372 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7bea00-0x13f7c0fff]
5793 01:54:55.702449 [ 0.000000] Zone ranges:
5794 01:54:55.708651 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
5795 01:54:55.712132 [ 0.000000] DMA32 empty
5796 01:54:55.718547 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
5797 01:54:55.721996 [ 0.000000] Movable zone start for each node
5798 01:54:55.725371 [ 0.000000] Early memory node ranges
5799 01:54:55.732017 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
5800 01:54:55.738124 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
5801 01:54:55.744778 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
5802 01:54:55.751615 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
5803 01:54:55.758286 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
5804 01:54:55.764315 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
5805 01:54:55.781433 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
5806 01:54:55.788173 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
5807 01:54:55.794771 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
5808 01:54:55.797856 [ 0.000000] psci: probing for conduit method from DT.
5809 01:54:55.804320 [ 0.000000] psci: PSCIv1.1 detected in firmware.
5810 01:54:55.807640 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
5811 01:54:55.814419 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
5812 01:54:55.817729 [ 0.000000] psci: SMC Calling Convention v1.1
5813 01:54:55.824087 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
5814 01:54:55.827191 [ 0.000000] Detected VIPT I-cache on CPU0
5815 01:54:55.833965 [ 0.000000] CPU features: detected: GIC system register CPU interface
5816 01:54:55.840762 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
5817 01:54:55.846930 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
5818 01:54:55.853725 [ 0.000000] CPU features: detected: ARM erratum 845719
5819 01:54:55.856963 [ 0.000000] alternatives: applying boot alternatives
5820 01:54:55.863533 [ 0.000000] Fallback order for Node 0: 0
5821 01:54:55.870212 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
5822 01:54:55.873617 [ 0.000000] Policy zone: Normal
5823 01:54:55.899611 [ 0.000000] Kernel command line: earlyprintk=ttyS0,115200n8 console=tty1 console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14479155/extract-nfsrootfs-t4oh8com,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
5824 01:54:55.912714 <5>[ 0.000000] Unknown kernel command line parameters "earlyprintk=ttyS0,115200n8 tftpserverip=192.168.201.1", will be passed to user space.
5825 01:54:55.919330 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
5826 01:54:55.929423 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
5827 01:54:55.935913 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
5828 01:54:55.938968 <6>[ 0.000000] software IO TLB: area num 8.
5829 01:54:55.964856 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
5830 01:54:56.022939 <6>[ 0.000000] Memory: 3896764K/4191232K available (18112K kernel code, 4120K rwdata, 22648K rodata, 8512K init, 616K bss, 261700K reserved, 32768K cma-reserved)
5831 01:54:56.028927 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
5832 01:54:56.035981 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
5833 01:54:56.039497 <6>[ 0.000000] rcu: RCU event tracing is enabled.
5834 01:54:56.045755 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
5835 01:54:56.052248 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
5836 01:54:56.058869 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
5837 01:54:56.065488 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
5838 01:54:56.071678 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
5839 01:54:56.078617 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
5840 01:54:56.088050 <6>[ 0.000000] GIC: enabling workaround for GICv3: Mediatek Chromebook GICR save problem
5841 01:54:56.091922 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
5842 01:54:56.098269 <6>[ 0.000000] GICv3: 640 SPIs implemented
5843 01:54:56.101713 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
5844 01:54:56.105093 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
5845 01:54:56.111232 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
5846 01:54:56.118376 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c100000
5847 01:54:56.130906 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@1[1] /cpus/cpu@2[2] /cpus/cpu@3[3] }
5848 01:54:56.141086 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@100[4] /cpus/cpu@101[5] /cpus/cpu@102[6] /cpus/cpu@103[7] }
5849 01:54:56.147870 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
5850 01:54:56.159983 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
5851 01:54:56.173233 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
5852 01:54:56.179218 <6>[ 0.000001] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
5853 01:54:56.186102 <6>[ 0.009468] Console: colour dummy device 80x25
5854 01:54:56.190102 <6>[ 0.014513] printk: console [tty1] enabled
5855 01:54:56.203331 <6>[ 0.018903] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
5856 01:54:56.205961 <6>[ 0.029368] pid_max: default: 32768 minimum: 301
5857 01:54:56.209482 <6>[ 0.034251] LSM: Security Framework initializing
5858 01:54:56.219251 <6>[ 0.039166] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
5859 01:54:56.225642 <6>[ 0.046789] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
5860 01:54:56.232779 <4>[ 0.055643] cacheinfo: Unable to detect cache hierarchy for CPU 0
5861 01:54:56.242517 <6>[ 0.062271] cblist_init_generic: Setting adjustable number of callback queues.
5862 01:54:56.249148 <6>[ 0.069718] cblist_init_generic: Setting shift to 3 and lim to 1.
5863 01:54:56.255631 <6>[ 0.076070] cblist_init_generic: Setting adjustable number of callback queues.
5864 01:54:56.262386 <6>[ 0.083515] cblist_init_generic: Setting shift to 3 and lim to 1.
5865 01:54:56.265787 <6>[ 0.089914] rcu: Hierarchical SRCU implementation.
5866 01:54:56.271982 <6>[ 0.094941] rcu: Max phase no-delay instances is 1000.
5867 01:54:56.279801 <6>[ 0.102866] EFI services will not be available.
5868 01:54:56.283129 <6>[ 0.107814] smp: Bringing up secondary CPUs ...
5869 01:54:56.293339 <6>[ 0.113039] Detected VIPT I-cache on CPU1
5870 01:54:56.300151 <4>[ 0.113087] cacheinfo: Unable to detect cache hierarchy for CPU 1
5871 01:54:56.307156 <6>[ 0.113095] GICv3: CPU1: found redistributor 1 region 0:0x000000000c120000
5872 01:54:56.313165 <6>[ 0.113127] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
5873 01:54:56.316886 <6>[ 0.113607] Detected VIPT I-cache on CPU2
5874 01:54:56.323049 <4>[ 0.113640] cacheinfo: Unable to detect cache hierarchy for CPU 2
5875 01:54:56.329442 <6>[ 0.113645] GICv3: CPU2: found redistributor 2 region 0:0x000000000c140000
5876 01:54:56.336098 <6>[ 0.113657] CPU2: Booted secondary processor 0x0000000002 [0x410fd034]
5877 01:54:56.342732 <6>[ 0.114104] Detected VIPT I-cache on CPU3
5878 01:54:56.349562 <4>[ 0.114133] cacheinfo: Unable to detect cache hierarchy for CPU 3
5879 01:54:56.355887 <6>[ 0.114138] GICv3: CPU3: found redistributor 3 region 0:0x000000000c160000
5880 01:54:56.362482 <6>[ 0.114149] CPU3: Booted secondary processor 0x0000000003 [0x410fd034]
5881 01:54:56.365515 <6>[ 0.114725] CPU features: detected: Spectre-v2
5882 01:54:56.372215 <6>[ 0.114736] CPU features: detected: Spectre-BHB
5883 01:54:56.375680 <6>[ 0.114740] CPU features: detected: ARM erratum 858921
5884 01:54:56.382437 <6>[ 0.114745] Detected VIPT I-cache on CPU4
5885 01:54:56.385582 <4>[ 0.114793] cacheinfo: Unable to detect cache hierarchy for CPU 4
5886 01:54:56.395169 <6>[ 0.114800] GICv3: CPU4: found redistributor 100 region 0:0x000000000c180000
5887 01:54:56.401649 <6>[ 0.114809] arch_timer: Enabling local workaround for ARM erratum 858921
5888 01:54:56.405288 <6>[ 0.114819] arch_timer: CPU4: Trapping CNTVCT access
5889 01:54:56.412375 <6>[ 0.114827] CPU4: Booted secondary processor 0x0000000100 [0x410fd092]
5890 01:54:56.418366 <6>[ 0.115312] Detected VIPT I-cache on CPU5
5891 01:54:56.424947 <4>[ 0.115352] cacheinfo: Unable to detect cache hierarchy for CPU 5
5892 01:54:56.431468 <6>[ 0.115358] GICv3: CPU5: found redistributor 101 region 0:0x000000000c1a0000
5893 01:54:56.438352 <6>[ 0.115365] arch_timer: Enabling local workaround for ARM erratum 858921
5894 01:54:56.444529 <6>[ 0.115371] arch_timer: CPU5: Trapping CNTVCT access
5895 01:54:56.450973 <6>[ 0.115376] CPU5: Booted secondary processor 0x0000000101 [0x410fd092]
5896 01:54:56.454366 <6>[ 0.115812] Detected VIPT I-cache on CPU6
5897 01:54:56.461288 <4>[ 0.115858] cacheinfo: Unable to detect cache hierarchy for CPU 6
5898 01:54:56.467413 <6>[ 0.115865] GICv3: CPU6: found redistributor 102 region 0:0x000000000c1c0000
5899 01:54:56.474245 <6>[ 0.115872] arch_timer: Enabling local workaround for ARM erratum 858921
5900 01:54:56.481166 <6>[ 0.115878] arch_timer: CPU6: Trapping CNTVCT access
5901 01:54:56.487667 <6>[ 0.115883] CPU6: Booted secondary processor 0x0000000102 [0x410fd092]
5902 01:54:56.490922 <6>[ 0.116412] Detected VIPT I-cache on CPU7
5903 01:54:56.496970 <4>[ 0.116457] cacheinfo: Unable to detect cache hierarchy for CPU 7
5904 01:54:56.504098 <6>[ 0.116463] GICv3: CPU7: found redistributor 103 region 0:0x000000000c1e0000
5905 01:54:56.510617 <6>[ 0.116470] arch_timer: Enabling local workaround for ARM erratum 858921
5906 01:54:56.516901 <6>[ 0.116476] arch_timer: CPU7: Trapping CNTVCT access
5907 01:54:56.523527 <6>[ 0.116481] CPU7: Booted secondary processor 0x0000000103 [0x410fd092]
5908 01:54:56.527052 <6>[ 0.116529] smp: Brought up 1 node, 8 CPUs
5909 01:54:56.533177 <6>[ 0.355442] SMP: Total of 8 processors activated.
5910 01:54:56.536899 <6>[ 0.360377] CPU features: detected: 32-bit EL0 Support
5911 01:54:56.543084 <6>[ 0.365756] CPU features: detected: 32-bit EL1 Support
5912 01:54:56.550006 <6>[ 0.371125] CPU features: detected: CRC32 instructions
5913 01:54:56.553173 <6>[ 0.376550] CPU: All CPU(s) started at EL2
5914 01:54:56.560093 <6>[ 0.380888] alternatives: applying system-wide alternatives
5915 01:54:56.563415 <6>[ 0.388908] devtmpfs: initialized
5916 01:54:56.578224 <6>[ 0.397862] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
5917 01:54:56.588425 <6>[ 0.407811] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
5918 01:54:56.594259 <6>[ 0.415541] pinctrl core: initialized pinctrl subsystem
5919 01:54:56.597890 <6>[ 0.422641] DMI not present or invalid.
5920 01:54:56.604518 <6>[ 0.427010] NET: Registered PF_NETLINK/PF_ROUTE protocol family
5921 01:54:56.614106 <6>[ 0.433917] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
5922 01:54:56.620893 <6>[ 0.441447] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
5923 01:54:56.631002 <6>[ 0.449697] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
5924 01:54:56.637275 <6>[ 0.457875] audit: initializing netlink subsys (disabled)
5925 01:54:56.643549 <5>[ 0.463577] audit: type=2000 audit(0.328:1): state=initialized audit_enabled=0 res=1
5926 01:54:56.650302 <6>[ 0.464542] thermal_sys: Registered thermal governor 'step_wise'
5927 01:54:56.657074 <6>[ 0.471544] thermal_sys: Registered thermal governor 'power_allocator'
5928 01:54:56.660138 <6>[ 0.477842] cpuidle: using governor menu
5929 01:54:56.666548 <6>[ 0.488803] NET: Registered PF_QIPCRTR protocol family
5930 01:54:56.673526 <6>[ 0.494296] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
5931 01:54:56.679642 <6>[ 0.501392] ASID allocator initialised with 32768 entries
5932 01:54:56.682854 <6>[ 0.508151] Serial: AMBA PL011 UART driver
5933 01:54:56.695220 <4>[ 0.518534] Trying to register duplicate clock ID: 113
5934 01:54:56.754532 <6>[ 0.574595] platform 14014000.dsi: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
5935 01:54:56.769707 <6>[ 0.588906] platform panel: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
5936 01:54:56.772147 <6>[ 0.598650] KASLR enabled
5937 01:54:56.786885 <6>[ 0.606680] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
5938 01:54:56.793646 <6>[ 0.613681] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
5939 01:54:56.800258 <6>[ 0.620158] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
5940 01:54:56.807171 <6>[ 0.627149] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
5941 01:54:56.813561 <6>[ 0.633622] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
5942 01:54:56.820013 <6>[ 0.640612] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
5943 01:54:56.826540 <6>[ 0.647085] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
5944 01:54:56.833089 <6>[ 0.654075] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
5945 01:54:56.835931 <6>[ 0.661638] ACPI: Interpreter disabled.
5946 01:54:56.846370 <6>[ 0.669604] iommu: Default domain type: Translated
5947 01:54:56.852995 <6>[ 0.674711] iommu: DMA domain TLB invalidation policy: strict mode
5948 01:54:56.856495 <5>[ 0.681345] SCSI subsystem initialized
5949 01:54:56.863092 <6>[ 0.685763] usbcore: registered new interface driver usbfs
5950 01:54:56.869954 <6>[ 0.691491] usbcore: registered new interface driver hub
5951 01:54:56.872684 <6>[ 0.697033] usbcore: registered new device driver usb
5952 01:54:56.880356 <6>[ 0.703329] pps_core: LinuxPPS API ver. 1 registered
5953 01:54:56.890361 <6>[ 0.708514] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
5954 01:54:56.893463 <6>[ 0.717838] PTP clock support registered
5955 01:54:56.896804 <6>[ 0.722090] EDAC MC: Ver: 3.0.0
5956 01:54:56.904357 <6>[ 0.727711] FPGA manager framework
5957 01:54:56.911354 <6>[ 0.731394] Advanced Linux Sound Architecture Driver Initialized.
5958 01:54:56.914542 <6>[ 0.738147] vgaarb: loaded
5959 01:54:56.921088 <6>[ 0.741278] clocksource: Switched to clocksource arch_sys_counter
5960 01:54:56.924496 <5>[ 0.747707] VFS: Disk quotas dquot_6.6.0
5961 01:54:56.930662 <6>[ 0.751882] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
5962 01:54:56.934275 <6>[ 0.759057] pnp: PnP ACPI: disabled
5963 01:54:56.943108 <6>[ 0.765949] NET: Registered PF_INET protocol family
5964 01:54:56.949358 <6>[ 0.771179] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
5965 01:54:56.961146 <6>[ 0.781094] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
5966 01:54:56.971117 <6>[ 0.789849] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
5967 01:54:56.977572 <6>[ 0.797800] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
5968 01:54:56.984248 <6>[ 0.806032] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
5969 01:54:56.994406 <6>[ 0.814129] TCP: Hash tables configured (established 32768 bind 32768)
5970 01:54:57.001124 <6>[ 0.820957] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
5971 01:54:57.007627 <6>[ 0.827930] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
5972 01:54:57.014138 <6>[ 0.835409] NET: Registered PF_UNIX/PF_LOCAL protocol family
5973 01:54:57.020274 <6>[ 0.841504] RPC: Registered named UNIX socket transport module.
5974 01:54:57.023854 <6>[ 0.847647] RPC: Registered udp transport module.
5975 01:54:57.030355 <6>[ 0.852572] RPC: Registered tcp transport module.
5976 01:54:57.037143 <6>[ 0.857494] RPC: Registered tcp NFSv4.1 backchannel transport module.
5977 01:54:57.040096 <6>[ 0.864146] PCI: CLS 0 bytes, default 64
5978 01:54:57.043543 <6>[ 0.868429] Unpacking initramfs...
5979 01:54:57.062277 <6>[ 0.881863] hw perfevents: enabled with armv8_cortex_a53 PMU driver, 7 counters available
5980 01:54:57.071930 <6>[ 0.890553] hw perfevents: enabled with armv8_cortex_a73 PMU driver, 7 counters available
5981 01:54:57.075288 <6>[ 0.899462] kvm [1]: IPA Size Limit: 40 bits
5982 01:54:57.083123 <6>[ 0.905815] kvm [1]: vgic-v2@c420000
5983 01:54:57.086319 <6>[ 0.909646] kvm [1]: GIC system register CPU interface enabled
5984 01:54:57.092629 <6>[ 0.915835] kvm [1]: vgic interrupt IRQ18
5985 01:54:57.096061 <6>[ 0.920206] kvm [1]: Hyp mode initialized successfully
5986 01:54:57.103534 <5>[ 0.926564] Initialise system trusted keyrings
5987 01:54:57.110247 <6>[ 0.931414] workingset: timestamp_bits=42 max_order=20 bucket_order=0
5988 01:54:57.118489 <6>[ 0.941384] squashfs: version 4.0 (2009/01/31) Phillip Lougher
5989 01:54:57.125191 <5>[ 0.947798] NFS: Registering the id_resolver key type
5990 01:54:57.128181 <5>[ 0.953104] Key type id_resolver registered
5991 01:54:57.134631 <5>[ 0.957516] Key type id_legacy registered
5992 01:54:57.141170 <6>[ 0.961814] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
5993 01:54:57.147967 <6>[ 0.968736] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
5994 01:54:57.154719 <6>[ 0.976477] 9p: Installing v9fs 9p2000 file system support
5995 01:54:57.183319 <5>[ 1.005961] Key type asymmetric registered
5996 01:54:57.186320 <5>[ 1.010305] Asymmetric key parser 'x509' registered
5997 01:54:57.195678 <6>[ 1.015455] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
5998 01:54:57.199194 <6>[ 1.023072] io scheduler mq-deadline registered
5999 01:54:57.202688 <6>[ 1.027829] io scheduler kyber registered
6000 01:54:57.225605 <6>[ 1.048515] EINJ: ACPI disabled.
6001 01:54:57.231803 <4>[ 1.052281] of_fixed_factor_clk: probe of fixed-factor-clock-13m failed with error -17
6002 01:54:57.270463 <6>[ 1.093167] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
6003 01:54:57.278905 <6>[ 1.101658] printk: console [ttyS0] disabled
6004 01:54:57.306882 <6>[ 1.126308] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 242, base_baud = 1625000) is a ST16650V2
6005 01:54:57.313025 <6>[ 1.135780] printk: console [ttyS0] enabled
6006 01:54:57.316456 <6>[ 1.135780] printk: console [ttyS0] enabled
6007 01:54:57.323252 <6>[ 1.144702] printk: bootconsole [mtk8250] disabled
6008 01:54:57.326198 <6>[ 1.144702] printk: bootconsole [mtk8250] disabled
6009 01:54:57.336015 <3>[ 1.155231] mt8183-pinctrl 10005000.pinctrl: pin_config_group_set op failed for group 47
6010 01:54:57.342629 <3>[ 1.163614] mt6577-uart 11003000.serial: Error applying setting, reverse things back
6011 01:54:57.372094 <6>[ 1.192013] 11003000.serial: ttyS1 at MMIO 0x11003000 (irq = 243, base_baud = 1625000) is a ST16650V2
6012 01:54:57.378920 <6>[ 1.201667] serial serial0: tty port ttyS1 registered
6013 01:54:57.385231 <6>[ 1.208261] SuperH (H)SCI(F) driver initialized
6014 01:54:57.388835 <6>[ 1.213795] msm_serial: driver initialized
6015 01:54:57.404344 <6>[ 1.224120] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14008000
6016 01:54:57.414304 <6>[ 1.232722] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14009000
6017 01:54:57.420497 <6>[ 1.241310] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@1400a000
6018 01:54:57.430540 <6>[ 1.249884] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@1400b000
6019 01:54:57.440661 <6>[ 1.258543] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@1400c000
6020 01:54:57.446648 <6>[ 1.267207] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@1400e000
6021 01:54:57.456740 <6>[ 1.275947] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400f000
6022 01:54:57.466955 <6>[ 1.284688] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@14010000
6023 01:54:57.473659 <6>[ 1.293267] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@14011000
6024 01:54:57.483509 <6>[ 1.302089] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/dsi@14014000
6025 01:54:57.491440 <4>[ 1.314491] cacheinfo: Unable to detect cache hierarchy for CPU 0
6026 01:54:57.500652 <6>[ 1.323869] loop: module loaded
6027 01:54:57.512967 <6>[ 1.335801] vsim1: Bringing 1800000uV into 2700000-2700000uV
6028 01:54:57.530928 <6>[ 1.353820] megasas: 07.719.03.00-rc1
6029 01:54:57.539356 <6>[ 1.362634] spi-nor spi1.0: w25q64dw (8192 Kbytes)
6030 01:54:57.549578 <6>[ 1.372652] tpm_tis_spi spi0.0: TPM ready IRQ confirmed on attempt 2
6031 01:54:57.566638 <6>[ 1.389361] tpm_tis_spi spi0.0: 2.0 TPM (device-id 0x28, rev-id 0)
6032 01:54:57.623247 <6>[ 1.439369] tpm_tis_spi spi0.0: Cr50 firmware version: B2-C:0 RO_A:0.0.12/bf248b9d RW_B:0.5.171/cr50_v2.94_mp.164-2fb1d
6033 01:54:57.667068 <6>[ 1.490207] Freeing initrd memory: 18304K
6034 01:54:57.682353 <4>[ 1.502012] sysfs: cannot create duplicate filename '/bus/platform/devices/fixed-factor-clock-13m'
6035 01:54:57.689201 <4>[ 1.511240] CPU: 4 PID: 1 Comm: swapper/0 Not tainted 6.1.94-cip23 #1
6036 01:54:57.696073 <4>[ 1.517937] Hardware name: Google juniper sku16 board (DT)
6037 01:54:57.698883 <4>[ 1.523676] Call trace:
6038 01:54:57.702045 <4>[ 1.526377] dump_backtrace.part.0+0xe0/0xf0
6039 01:54:57.705505 <4>[ 1.530914] show_stack+0x18/0x30
6040 01:54:57.712179 <4>[ 1.534486] dump_stack_lvl+0x68/0x84
6041 01:54:57.715548 <4>[ 1.538407] dump_stack+0x18/0x34
6042 01:54:57.718416 <4>[ 1.541977] sysfs_warn_dup+0x64/0x80
6043 01:54:57.721817 <4>[ 1.545899] sysfs_do_create_link_sd+0xf0/0x100
6044 01:54:57.725101 <4>[ 1.550684] sysfs_create_link+0x20/0x40
6045 01:54:57.732048 <4>[ 1.554860] bus_add_device+0x68/0x10c
6046 01:54:57.735405 <4>[ 1.558866] device_add+0x364/0x7cc
6047 01:54:57.738785 <4>[ 1.562609] of_device_add+0x44/0x60
6048 01:54:57.745338 <4>[ 1.566443] of_platform_device_create_pdata+0x90/0x120
6049 01:54:57.748347 <4>[ 1.571925] of_platform_bus_create+0x170/0x370
6050 01:54:57.751730 <4>[ 1.576709] of_platform_populate+0x50/0xfc
6051 01:54:57.758688 <4>[ 1.581146] parse_mtd_partitions+0x1dc/0x510
6052 01:54:57.761631 <4>[ 1.585759] mtd_device_parse_register+0xf0/0x2e4
6053 01:54:57.768608 <4>[ 1.590717] spi_nor_probe+0x21c/0x2f0
6054 01:54:57.771828 <4>[ 1.594723] spi_mem_probe+0x6c/0xb0
6055 01:54:57.775344 <4>[ 1.598556] spi_probe+0x84/0xe4
6056 01:54:57.778588 <4>[ 1.602037] really_probe+0xbc/0x2e0
6057 01:54:57.782236 <4>[ 1.605868] __driver_probe_device+0x78/0x11c
6058 01:54:57.788399 <4>[ 1.610480] driver_probe_device+0xd8/0x160
6059 01:54:57.791822 <4>[ 1.614918] __device_attach_driver+0xb8/0x134
6060 01:54:57.794709 <4>[ 1.619617] bus_for_each_drv+0x78/0xd0
6061 01:54:57.801386 <4>[ 1.623707] __device_attach+0xa8/0x1c0
6062 01:54:57.804963 <4>[ 1.627798] device_initial_probe+0x14/0x20
6063 01:54:57.808036 <4>[ 1.632236] bus_probe_device+0x9c/0xa4
6064 01:54:57.811126 <4>[ 1.636327] device_add+0x3d0/0x7cc
6065 01:54:57.815037 <4>[ 1.640069] __spi_add_device+0x78/0x120
6066 01:54:57.821662 <4>[ 1.644247] spi_add_device+0x40/0x7c
6067 01:54:57.824368 <4>[ 1.648164] spi_register_controller+0x610/0xad0
6068 01:54:57.831270 <4>[ 1.653037] devm_spi_register_controller+0x4c/0xa4
6069 01:54:57.834948 <4>[ 1.658170] mtk_spi_probe+0x3f8/0x650
6070 01:54:57.838314 <4>[ 1.662175] platform_probe+0x68/0xe0
6071 01:54:57.840921 <4>[ 1.666093] really_probe+0xbc/0x2e0
6072 01:54:57.847822 <4>[ 1.669923] __driver_probe_device+0x78/0x11c
6073 01:54:57.851162 <4>[ 1.674534] driver_probe_device+0xd8/0x160
6074 01:54:57.854562 <4>[ 1.678972] __driver_attach+0x94/0x19c
6075 01:54:57.857948 <4>[ 1.683063] bus_for_each_dev+0x70/0xd0
6076 01:54:57.864727 <4>[ 1.687153] driver_attach+0x24/0x30
6077 01:54:57.867705 <4>[ 1.690983] bus_add_driver+0x154/0x20c
6078 01:54:57.870691 <4>[ 1.695073] driver_register+0x78/0x130
6079 01:54:57.877482 <4>[ 1.699164] __platform_driver_register+0x28/0x34
6080 01:54:57.881034 <4>[ 1.704123] mtk_spi_driver_init+0x1c/0x28
6081 01:54:57.883989 <4>[ 1.708477] do_one_initcall+0x50/0x1d0
6082 01:54:57.890707 <4>[ 1.712567] kernel_init_freeable+0x21c/0x288
6083 01:54:57.894162 <4>[ 1.717180] kernel_init+0x24/0x12c
6084 01:54:57.897083 <4>[ 1.720925] ret_from_fork+0x10/0x20
6085 01:54:57.906876 <6>[ 1.729790] tun: Universal TUN/TAP device driver, 1.6
6086 01:54:57.910206 <6>[ 1.736077] thunder_xcv, ver 1.0
6087 01:54:57.916489 <6>[ 1.739597] thunder_bgx, ver 1.0
6088 01:54:57.916565 <6>[ 1.743100] nicpf, ver 1.0
6089 01:54:57.927719 <6>[ 1.747476] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
6090 01:54:57.931144 <6>[ 1.754961] hns3: Copyright (c) 2017 Huawei Corporation.
6091 01:54:57.938100 <6>[ 1.760562] hclge is initializing
6092 01:54:57.940779 <6>[ 1.764148] e1000: Intel(R) PRO/1000 Network Driver
6093 01:54:57.947562 <6>[ 1.769282] e1000: Copyright (c) 1999-2006 Intel Corporation.
6094 01:54:57.954434 <6>[ 1.775306] e1000e: Intel(R) PRO/1000 Network Driver
6095 01:54:57.957488 <6>[ 1.780527] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
6096 01:54:57.964090 <6>[ 1.786720] igb: Intel(R) Gigabit Ethernet Network Driver
6097 01:54:57.970679 <6>[ 1.792377] igb: Copyright (c) 2007-2014 Intel Corporation.
6098 01:54:57.977479 <6>[ 1.798225] igbvf: Intel(R) Gigabit Virtual Function Network Driver
6099 01:54:57.983899 <6>[ 1.804748] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
6100 01:54:57.987130 <6>[ 1.811301] sky2: driver version 1.30
6101 01:54:57.993907 <6>[ 1.816554] usbcore: registered new device driver r8152-cfgselector
6102 01:54:58.000943 <6>[ 1.823098] usbcore: registered new interface driver r8152
6103 01:54:58.006899 <6>[ 1.828935] VFIO - User Level meta-driver version: 0.3
6104 01:54:58.013538 <6>[ 1.836717] mtu3 11201000.usb: uwk - reg:0x420, version:101
6105 01:54:58.020369 <4>[ 1.842589] mtu3 11201000.usb: supply vbus not found, using dummy regulator
6106 01:54:58.026598 <6>[ 1.849859] mtu3 11201000.usb: dr_mode: 1, drd: auto
6107 01:54:58.033673 <6>[ 1.855085] mtu3 11201000.usb: u2p_dis_msk: 0, u3p_dis_msk: 0
6108 01:54:58.037144 <6>[ 1.861285] mtu3 11201000.usb: usb3-drd: 0
6109 01:54:58.047235 <6>[ 1.866849] mtu3 11201000.usb: xHCI platform device register success...
6110 01:54:58.053295 <4>[ 1.875529] xhci-mtk 11200000.usb: supply vbus not found, using dummy regulator
6111 01:54:58.060240 <6>[ 1.883454] xhci-mtk 11200000.usb: xHCI Host Controller
6112 01:54:58.067240 <6>[ 1.888959] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
6113 01:54:58.074127 <6>[ 1.896688] xhci-mtk 11200000.usb: USB3 root hub has no ports
6114 01:54:58.083717 <6>[ 1.902697] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
6115 01:54:58.089959 <6>[ 1.912120] xhci-mtk 11200000.usb: irq 253, io mem 0x11200000
6116 01:54:58.097391 <6>[ 1.918197] xhci-mtk 11200000.usb: xHCI Host Controller
6117 01:54:58.103473 <6>[ 1.923685] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
6118 01:54:58.110197 <6>[ 1.931345] xhci-mtk 11200000.usb: Host supports USB 3.0 SuperSpeed
6119 01:54:58.113533 <6>[ 1.938191] hub 1-0:1.0: USB hub found
6120 01:54:58.116892 <6>[ 1.942221] hub 1-0:1.0: 1 port detected
6121 01:54:58.127549 <6>[ 1.947585] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
6122 01:54:58.130978 <6>[ 1.956213] hub 2-0:1.0: USB hub found
6123 01:54:58.140989 <3>[ 1.960241] hub 2-0:1.0: config failed, hub doesn't have any ports! (err -19)
6124 01:54:58.147543 <6>[ 1.968132] usbcore: registered new interface driver usb-storage
6125 01:54:58.154176 <6>[ 1.974742] usbcore: registered new device driver onboard-usb-hub
6126 01:54:58.169912 <4>[ 1.989379] onboard-usb-hub 11200000.usb:hub@1: supply vdd not found, using dummy regulator
6127 01:54:58.178757 <6>[ 2.001694] mt6397-rtc mt6358-rtc: registered as rtc0
6128 01:54:58.188676 <6>[ 2.007173] mt6397-rtc mt6358-rtc: setting system clock to 2024-06-21T01:54:58 UTC (1718934898)
6129 01:54:58.195356 <6>[ 2.017061] i2c_dev: i2c /dev entries driver
6130 01:54:58.205286 <6>[ 2.023479] platform panel: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
6131 01:54:58.211394 <6>[ 2.031797] platform 14014000.dsi: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
6132 01:54:58.218582 <6>[ 2.040705] i2c 4-0058: Fixed dependency cycle(s) with /panel
6133 01:54:58.224659 <6>[ 2.046738] i2c 4-0058: Fixed dependency cycle(s) with /soc/dsi@14014000
6134 01:54:58.243458 <6>[ 2.066228] cpu cpu0: EM: created perf domain
6135 01:54:58.253231 <6>[ 2.071748] cpufreq: cpufreq_online: CPU4: Running at unlisted initial frequency: 1199999 KHz, changing to: 1248000 KHz
6136 01:54:58.260271 <6>[ 2.083032] cpu cpu4: EM: created perf domain
6137 01:54:58.267400 <6>[ 2.090108] sdhci: Secure Digital Host Controller Interface driver
6138 01:54:58.273659 <6>[ 2.096564] sdhci: Copyright(c) Pierre Ossman
6139 01:54:58.280375 <6>[ 2.101982] Synopsys Designware Multimedia Card Interface Driver
6140 01:54:58.287036 <6>[ 2.102534] mtk-msdc 11240000.mmc: allocated mmc-pwrseq
6141 01:54:58.290474 <6>[ 2.109038] sdhci-pltfm: SDHCI platform and OF driver helper
6142 01:54:58.299457 <6>[ 2.122317] ledtrig-cpu: registered to indicate activity on CPUs
6143 01:54:58.307324 <6>[ 2.130145] usbcore: registered new interface driver usbhid
6144 01:54:58.313712 <6>[ 2.135992] usbhid: USB HID core driver
6145 01:54:58.321147 <6>[ 2.140274] spi_master spi2: will run message pump with realtime priority
6146 01:54:58.328235 <4>[ 2.140288] i2c_hid_of 2-002c: supply vdd not found, using dummy regulator
6147 01:54:58.334321 <4>[ 2.154545] i2c_hid_of 2-002c: supply vddl not found, using dummy regulator
6148 01:54:58.347882 <6>[ 2.160381] input: cros_ec as /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:keyboard-controller/input/input0
6149 01:54:58.363963 <6>[ 2.177201] input: cros_ec_buttons as /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:keyboard-controller/input/input1
6150 01:54:58.370850 <4>[ 2.189499] mmc1: queuing unknown CIS tuple 0x01 [d9 01 ff] (3 bytes)
6151 01:54:58.374201 <6>[ 2.191763] cros-ec-spi spi2.0: Chrome EC device registered
6152 01:54:58.388664 <4>[ 2.208657] mmc1: queuing unknown CIS tuple 0x1a [01 01 00 02 07] (5 bytes)
6153 01:54:58.401289 <4>[ 2.221049] mmc1: queuing unknown CIS tuple 0x1b [c1 41 30 30 ff ff 32 00] (8 bytes)
6154 01:54:58.407913 <4>[ 2.230196] mmc1: queuing unknown CIS tuple 0x14 [] (0 bytes)
6155 01:54:58.419955 <6>[ 2.243300] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x11c14
6156 01:54:58.429002 <6>[ 2.251824] mmc0: new HS400 MMC card at address 0001
6157 01:54:58.436243 <6>[ 2.259217] mmcblk0: mmc0:0001 DA4032 29.1 GiB
6158 01:54:58.442562 <6>[ 2.262199] mmc1: new ultra high speed SDR104 SDIO card at address 0001
6159 01:54:58.455285 <6>[ 2.275139] mt6358-sound mt6358-sound: mt6358_platform_driver_probe(), dev name mt6358-sound
6160 01:54:58.463747 <6>[ 2.286816] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
6161 01:54:58.477011 <6>[ 2.288390] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6162 01:54:58.480575 <6>[ 2.294415] mmcblk0boot0: mmc0:0001 DA4032 4.00 MiB
6163 01:54:58.493365 <6>[ 2.301915] input: hid-over-i2c 06CB:CDB5 Mouse as /devices/platform/soc/11009000.i2c/i2c-2/2-002c/0018:06CB:CDB5.0001/input/input2
6164 01:54:58.503488 <6>[ 2.302208] hid-generic 0018:06CB:CDB5.0001: input: I2C HID v1.00 Mouse [hid-over-i2c 06CB:CDB5] on 2-002c
6165 01:54:58.506769 <6>[ 2.305340] NET: Registered PF_PACKET protocol family
6166 01:54:58.513908 <6>[ 2.310865] mmcblk0boot1: mmc0:0001 DA4032 4.00 MiB
6167 01:54:58.516638 <6>[ 2.321036] 9pnet: Installing 9P2000 support
6168 01:54:58.523059 <6>[ 2.331977] mmcblk0rpmb: mmc0:0001 DA4032 16.0 MiB, chardev (507:0)
6169 01:54:58.529909 <5>[ 2.336203] Key type dns_resolver registered
6170 01:54:58.533091 <6>[ 2.357398] registered taskstats version 1
6171 01:54:58.539678 <5>[ 2.361777] Loading compiled-in X.509 certificates
6172 01:54:58.546504 <6>[ 2.365462] usb 1-1: new high-speed USB device number 2 using xhci-mtk
6173 01:54:58.589540 <3>[ 2.409016] anx7625 4-0058: [drm:anx7625_link_bridge] *ERROR* fail to parse DT for panel : -517
6174 01:54:58.620868 <6>[ 2.436781] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6175 01:54:58.631316 <6>[ 2.451163] mtk-iommu 10205000.iommu: bound 14017000.larb (ops mtk_smi_larb_component_ops)
6176 01:54:58.641784 <6>[ 2.459739] mtk-iommu 10205000.iommu: bound 16010000.larb (ops mtk_smi_larb_component_ops)
6177 01:54:58.648005 <6>[ 2.468396] mtk-iommu 10205000.iommu: bound 1502f000.larb (ops mtk_smi_larb_component_ops)
6178 01:54:58.657999 <6>[ 2.477056] mtk-iommu 10205000.iommu: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
6179 01:54:58.667676 <6>[ 2.485662] mtk-iommu 10205000.iommu: bound 17010000.larb (ops mtk_smi_larb_component_ops)
6180 01:54:58.674486 <6>[ 2.494207] mtk-iommu 10205000.iommu: bound 15021000.larb (ops mtk_smi_larb_component_ops)
6181 01:54:58.684411 <6>[ 2.502741] mtk-iommu 10205000.iommu: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
6182 01:54:58.691320 <6>[ 2.512376] mediatek-disp-ovl 14008000.ovl: Adding to iommu group 0
6183 01:54:58.697341 <6>[ 2.519927] mediatek-disp-ovl 14009000.ovl: Adding to iommu group 0
6184 01:54:58.704102 <6>[ 2.527224] mediatek-disp-ovl 1400a000.ovl: Adding to iommu group 0
6185 01:54:58.711112 <6>[ 2.533000] hub 1-1:1.0: USB hub found
6186 01:54:58.717463 <6>[ 2.534524] mediatek-disp-rdma 1400b000.rdma: Adding to iommu group 0
6187 01:54:58.720899 <6>[ 2.538372] hub 1-1:1.0: 3 ports detected
6188 01:54:58.727084 <6>[ 2.545199] mediatek-disp-rdma 1400c000.rdma: Adding to iommu group 0
6189 01:54:58.734208 <6>[ 2.557092] panfrost 13040000.gpu: clock rate = 511999970
6190 01:54:58.743971 <6>[ 2.562798] panfrost 13040000.gpu: [drm:panfrost_devfreq_init] More than 1 supply is not supported yet
6191 01:54:58.754325 <6>[ 2.572970] panfrost 13040000.gpu: mali-g72 id 0x6221 major 0x0 minor 0x3 status 0x0
6192 01:54:58.760247 <6>[ 2.580979] panfrost 13040000.gpu: features: 00000000,000004f7, issues: 00000000,00000400
6193 01:54:58.773503 <6>[ 2.589412] panfrost 13040000.gpu: Features: L2:0x07120206 Shader:0x00000000 Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7
6194 01:54:58.780163 <6>[ 2.601495] panfrost 13040000.gpu: shader_present=0x7 l2_present=0x1
6195 01:54:58.791216 <6>[ 2.611227] [drm] Initialized panfrost 1.2.0 20180908 for 13040000.gpu on minor 0
6196 01:54:58.801241 <6>[ 2.620057] mediatek-drm mediatek-drm.1.auto: bound 14008000.ovl (ops mtk_disp_ovl_component_ops)
6197 01:54:58.811382 <6>[ 2.629210] mediatek-drm mediatek-drm.1.auto: bound 14009000.ovl (ops mtk_disp_ovl_component_ops)
6198 01:54:58.821172 <6>[ 2.638339] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ovl (ops mtk_disp_ovl_component_ops)
6199 01:54:58.827879 <6>[ 2.647467] mediatek-drm mediatek-drm.1.auto: bound 1400b000.rdma (ops mtk_disp_rdma_component_ops)
6200 01:54:58.837500 <6>[ 2.656766] mediatek-drm mediatek-drm.1.auto: bound 1400c000.rdma (ops mtk_disp_rdma_component_ops)
6201 01:54:58.847370 <6>[ 2.666066] mediatek-drm mediatek-drm.1.auto: bound 1400e000.color (ops mtk_disp_color_component_ops)
6202 01:54:58.857145 <6>[ 2.675539] mediatek-drm mediatek-drm.1.auto: bound 1400f000.ccorr (ops mtk_disp_ccorr_component_ops)
6203 01:54:58.867176 <6>[ 2.685012] mediatek-drm mediatek-drm.1.auto: bound 14010000.aal (ops mtk_disp_aal_component_ops)
6204 01:54:58.876652 <6>[ 2.694139] mediatek-drm mediatek-drm.1.auto: bound 14011000.gamma (ops mtk_disp_gamma_component_ops)
6205 01:54:58.946950 <6>[ 2.766489] mediatek-drm mediatek-drm.1.auto: bound 14014000.dsi (ops mtk_dsi_component_ops)
6206 01:54:58.956360 <6>[ 2.775358] mediatek-drm mediatek-drm.1.auto: Not creating crtc 1 because component 10 is disabled or missing
6207 01:54:58.966888 <6>[ 2.786820] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 1
6208 01:54:59.025455 <6>[ 2.845314] usb 1-1.2: new high-speed USB device number 3 using xhci-mtk
6209 01:54:59.668300 <6>[ 3.033637] r8152-cfgselector 1-1.2: reset high-speed USB device number 3 using xhci-mtk
6210 01:54:59.678013 <4>[ 3.150522] r8152 1-1.2:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
6211 01:54:59.684443 <4>[ 3.150540] r8152 1-1.2:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
6212 01:54:59.691181 <6>[ 3.199487] r8152 1-1.2:1.0 eth0: v1.12.13
6213 01:54:59.698135 <6>[ 3.281306] usb 1-1.3: new high-speed USB device number 4 using xhci-mtk
6214 01:54:59.704892 <6>[ 3.471333] Console: switching to colour frame buffer device 170x48
6215 01:54:59.711582 <6>[ 3.531983] mediatek-drm mediatek-drm.1.auto: [drm] fb0: mediatekdrmfb frame buffer device
6216 01:54:59.733620 <6>[ 3.549216] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6217 01:54:59.750269 <6>[ 3.566238] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6218 01:54:59.756513 <6>[ 3.578546] input: wifi-wakeup as /devices/platform/wifi-wakeup/input/input4
6219 01:54:59.767253 <6>[ 3.586675] input: volume-buttons as /devices/platform/volume-buttons/input/input5
6220 01:54:59.777283 <6>[ 3.593347] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6221 01:54:59.796927 <6>[ 3.612585] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6222 01:55:01.063771 <6>[ 4.886184] r8152 1-1.2:1.0 eth0: carrier on
6223 01:55:03.586430 <5>[ 4.913303] Sending DHCP requests .., OK
6224 01:55:03.593072 <6>[ 7.413620] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.20
6225 01:55:03.596286 <6>[ 7.422052] IP-Config: Complete:
6226 01:55:03.609344 <6>[ 7.425622] device=eth0, hwaddr=00:e0:4c:72:3d:a6, ipaddr=192.168.201.20, mask=255.255.255.0, gw=192.168.201.1
6227 01:55:03.618790 <6>[ 7.436523] host=mt8183-kukui-jacuzzi-juniper-sku16-cbg-4, domain=lava-rack, nis-domain=(none)
6228 01:55:03.631266 <6>[ 7.450799] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
6229 01:55:03.639550 <6>[ 7.450810] nameserver0=192.168.201.1
6230 01:55:03.647911 <6>[ 7.470611] clk: Disabling unused clocks
6231 01:55:03.652563 <6>[ 7.478559] ALSA device list:
6232 01:55:03.661788 <6>[ 7.484598] No soundcards found.
6233 01:55:03.670576 <6>[ 7.493664] Freeing unused kernel memory: 8512K
6234 01:55:03.677740 <6>[ 7.500804] Run /init as init process
6235 01:55:03.688688 Loading, please wait...
6236 01:55:03.724318 Starting systemd-udevd version 252.22-1~deb12u1
6237 01:55:04.069707 <3>[ 7.892529] thermal_sys: Failed to find 'trips' node
6238 01:55:04.079725 <3>[ 7.892776] mt8183-pinctrl 10005000.pinctrl: pin GPIO7 already requested by 2-002c; cannot claim for 2-0015
6239 01:55:04.089946 <6>[ 7.892980] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
6240 01:55:04.096500 <3>[ 7.897799] thermal_sys: Failed to find trip points for thermal-sensor1 id=0
6241 01:55:04.102754 <3>[ 7.897811] generic-adc-thermal thermal-sensor1: Thermal zone sensor register failed: -22
6242 01:55:04.112683 <4>[ 7.897815] generic-adc-thermal: probe of thermal-sensor1 failed with error -22
6243 01:55:04.119276 <3>[ 7.907826] mt8183-pinctrl 10005000.pinctrl: pin-7 (2-0015) status -22
6244 01:55:04.126031 <4>[ 7.908193] elants_i2c 0-0010: supply vcc33 not found, using dummy regulator
6245 01:55:04.132913 <4>[ 7.908284] elants_i2c 0-0010: supply vccio not found, using dummy regulator
6246 01:55:04.139545 <3>[ 7.918955] thermal_sys: Failed to find 'trips' node
6247 01:55:04.149404 <3>[ 7.923144] mt8183-pinctrl 10005000.pinctrl: could not request pin 7 (GPIO7) from group GPIO7 on device pinctrl_paris
6248 01:55:04.155660 <6>[ 7.923364] mc: Linux media interface: v0.10
6249 01:55:04.162365 <6>[ 7.924326] sbs-battery 12-000b: sbs-battery: battery gas gauge device registered
6250 01:55:04.169082 <3>[ 7.924972] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6251 01:55:04.179199 <3>[ 7.924988] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6252 01:55:04.189181 <3>[ 7.924997] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6253 01:55:04.199440 <3>[ 7.925197] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6254 01:55:04.205786 <3>[ 7.925207] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6255 01:55:04.216410 <3>[ 7.925215] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6256 01:55:04.226531 <3>[ 7.925224] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6257 01:55:04.232364 <3>[ 7.925231] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6258 01:55:04.242585 <3>[ 7.925458] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6259 01:55:04.248967 <3>[ 7.931579] thermal_sys: Failed to find trip points for thermal-sensor2 id=0
6260 01:55:04.256211 <3>[ 7.939151] elan_i2c 2-0015: Error applying setting, reverse things back
6261 01:55:04.265772 <3>[ 7.945941] generic-adc-thermal thermal-sensor2: Thermal zone sensor register failed: -22
6262 01:55:04.272142 <5>[ 7.957457] cfg80211: Loading compiled-in X.509 certificates for regulatory database
6263 01:55:04.282608 <4>[ 7.960557] generic-adc-thermal: probe of thermal-sensor2 failed with error -22
6264 01:55:04.288892 <6>[ 7.978880] cs_system_cfg: CoreSight Configuration manager initialised
6265 01:55:04.295552 <6>[ 7.980514] videodev: Linux video capture interface: v2.00
6266 01:55:04.309604 <4>[ 7.983936] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: No cache defaults, reading back from HW
6267 01:55:04.315953 <5>[ 7.984802] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
6268 01:55:04.322638 <5>[ 7.985342] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
6269 01:55:04.332711 <4>[ 7.985431] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
6270 01:55:04.335885 <6>[ 7.985440] cfg80211: failed to load regulatory.db
6271 01:55:04.345779 <6>[ 8.038856] input: Elan Touchscreen as /devices/platform/soc/11007000.i2c/i2c-0/0-0010/input/input6
6272 01:55:04.355607 <6>[ 8.045022] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 20
6273 01:55:04.365484 <6>[ 8.062710] coresight-cpu-debug d410000.cpu-debug: Coresight debug-CPU0 initialized
6274 01:55:04.368409 <3>[ 8.063046] mtk-scp 10500000.scp: invalid resource
6275 01:55:04.375470 <6>[ 8.063113] mtk-scp 10500000.scp: assigned reserved memory node memory@50000000
6276 01:55:04.381957 <6>[ 8.065764] remoteproc remoteproc0: scp is available
6277 01:55:04.392405 <4>[ 8.065890] remoteproc remoteproc0: Direct firmware load for scp.img failed with error -2
6278 01:55:04.399292 Begin: Loading e<6>[ 8.065900] remoteproc remoteproc0: powering up scp
6279 01:55:04.402669 ssential drivers ... done.
6280 01:55:04.412687 Begi<4>[ 8.065933] remoteproc remoteproc0: Direct firmware load for scp.img failed with error -2
6281 01:55:04.422755 n: Running /scripts/init-premoun<3>[ 8.065940] remoteproc remoteproc0: request_firmware failed: -2
6282 01:55:04.422833 t ... done.
6283 01:55:04.436164 Begin: Mounting roo<6>[ 8.072701] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6284 01:55:04.445815 t file system ... Begin: Running<6>[ 8.078887] coresight-cpu-debug d510000.cpu-debug: Coresight debug-CPU1 initialized
6285 01:55:04.449033 /scripts/nfs-top ... done.
6286 01:55:04.462247 Beg<3>[ 8.086388] debugfs: Directory '11220000.audio-controller:mt8183-afe-pcm' with parent 'mt8183_mt6358_ts3a227_max98357' already present!
6287 01:55:04.473322 in: Running /scr<6>[ 8.094171] coresight-cpu-debug d610000.cpu-debug: Coresight debug-CPU2 initialized
6288 01:55:04.473399 <6>[ 8.094280] Bluetooth: Core ver 2.22
6289 01:55:04.479910 ipts/nfs-premoun<6>[ 8.094333] NET: Registered PF_BLUETOOTH protocol family
6290 01:55:04.486154 <6>[ 8.094335] Bluetooth: HCI device and connection manager initialized
6291 01:55:04.493072 t ... Waiting up<6>[ 8.094347] Bluetooth: HCI socket layer initialized
6292 01:55:04.499682 <6>[ 8.094352] Bluetooth: L2CAP socket layer initialized
6293 01:55:04.506453 to 60 secs for any ethernet to <6>[ 8.094359] Bluetooth: SCO socket layer initialized
6294 01:55:04.509856 become available
6295 01:55:04.516747 Device /sys/cl<6>[ 8.110742] usb 1-1.3: Found UVC 1.00 device HD WebCam (04f2:b567)
6296 01:55:04.519987 ass/net/eth0 found
6297 01:55:04.520064 done.
6298 01:55:04.526174 Begin<6>[ 8.111339] coresight-cpu-debug d710000.cpu-debug: Coresight debug-CPU3 initialized
6299 01:55:04.536102 : Waiting up to 180 secs for any<6>[ 8.112081] mtk-mdp3 14001000.dma-controller0: Adding to iommu group 0
6300 01:55:04.546334 network device to become availa<6>[ 8.112144] mtk-jpeg 17030000.venc_jpg: Adding to iommu group 0
6301 01:55:04.546413 ble ... done.
6302 01:55:04.556136 <6>[ 8.112717] mtk-jpeg 17030000.venc_jpg: mtk-jpeg-enc device registered as /dev/video0 (81,0)
6303 01:55:04.566797 <6>[ 8.113609] mtk-mdp3 14001000.dma-controller0: Driver registered as /dev/video1
6304 01:55:04.570124 <6>[ 8.125732] Bluetooth: HCI UART driver ver 2.3
6305 01:55:04.581205 <6>[ 8.135729] coresight-cpu-debug d810000.cpu-debug: Coresight debug-CPU4 initialized
6306 01:55:04.594929 <6>[ 8.136203] input: HD WebCam: HD WebCam as /devices/platform/soc/11201000.usb/11200000.usb/usb1/1-1/1-1.3/1-1.3:1.0/input/input8
6307 01:55:04.602693 <6>[ 8.136343] usbcore: registered new interface driver uvcvideo
6308 01:55:04.610985 <6>[ 8.142245] Bluetooth: HCI UART protocol H4 registered
6309 01:55:04.618839 <6>[ 8.142284] Bluetooth: HCI UART protocol LL registered
6310 01:55:04.629420 <6>[ 8.151028] coresight-cpu-debug d910000.cpu-debug: Coresight debug-CPU5 initialized
6311 01:55:04.636097 <6>[ 8.159499] Bluetooth: HCI UART protocol Three-wire (H5) registered
6312 01:55:04.649996 <6>[ 8.166681] ath10k_sdio mmc1:0001:1: qca6174 hw3.2 sdio target 0x05030000 chip_id 0x00000000 sub 0000:0000
6313 01:55:04.656594 <6>[ 8.173846] coresight-cpu-debug da10000.cpu-debug: Coresight debug-CPU6 initialized
6314 01:55:04.664274 <6>[ 8.174326] Bluetooth: HCI UART protocol Broadcom registered
6315 01:55:04.671895 <6>[ 8.174348] Bluetooth: HCI UART protocol QCA registered
6316 01:55:04.678809 <6>[ 8.174362] Bluetooth: HCI UART protocol Marvell registered
6317 01:55:04.686722 <6>[ 8.175227] Bluetooth: hci0: setting up ROME/QCA6390
6318 01:55:04.696318 <6>[ 8.183874] ath10k_sdio mmc1:0001:1: kconfig debug 0 debugfs 0 tracing 0 dfs 0 testmode 0
6319 01:55:04.706269 <6>[ 8.191896] coresight-cpu-debug db10000.cpu-debug: Coresight debug-CPU7 initialized
6320 01:55:04.719656 <6>[ 8.197247] ath10k_sdio mmc1:0001:1: firmware ver WLAN.RMH.4.4.1-00174 api 6 features wowlan,ignore-otp,mfp crc32 7319fa77
6321 01:55:04.729624 <4>[ 8.279127] sbs-battery 12-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
6322 01:55:04.732787 <4>[ 8.279127] Fallback method does not support PEC.
6323 01:55:04.747895 <3>[ 8.290040] mt8183_mt6358_ts3a227 mt8183-sound: ASoC: driver name too long 'mt8183_mt6358_ts3a227_max98357' -> 'mt8183_mt6358_t'
6324 01:55:04.757214 <3>[ 8.300675] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6325 01:55:04.768120 <3>[ 8.304213] debugfs: File 'Playback' in directory 'dapm' already present!
6326 01:55:04.779088 <3>[ 8.315270] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6327 01:55:04.790338 <3>[ 8.315712] debugfs: File 'Capture' in directory 'dapm' already present!
6328 01:55:04.796400 <3>[ 8.392326] Bluetooth: hci0: Frame reassembly failed (-84)
6329 01:55:04.810631 <6>[ 8.398372] input: mt8183_mt6358_ts3a227_max98357 Headset Jack as /devices/platform/mt8183-sound/sound/card0/input7
6330 01:55:04.820372 <6>[ 8.564257] ath10k_sdio mmc1:0001:1: board_file api 2 bmi_id 0:4 crc32 d2863f91
6331 01:55:04.864194 <6>[ 8.686796] Bluetooth: hci0: QCA Product ID :0x00000008
6332 01:55:04.879321 IP-Config: eth0 hardware address 00:e0:4c:72:3d:a6 mtu 1500 DHCP
6333 01:55:04.906066 IP-Config: eth0 complete (dhcp from 192.168.201.1):
6334 01:55:04.919103 address: 192.168.201.20 broadcast: 192.168.201.255 netmask: 255.255.255.0
6335 01:55:04.929782 gateway: 192.168.201.1 dns0 : 192<6>[ 8.752328] Bluetooth: hci0: QCA SOC Version :0x00000044
6336 01:55:04.939775 .168.201.1 dns1 : 0.0.0.0 <6>[ 8.761715] Bluetooth: hci0: QCA ROM Version :0x00000302
6337 01:55:04.943181
6338 01:55:04.949812 host : mt8183-kukui-<6>[ 8.770733] Bluetooth: hci0: QCA Patch Version:0x00000111
6339 01:55:04.959380 jacuzzi-juniper-sku16-cbg-4 <6>[ 8.779589] Bluetooth: hci0: QCA controller version 0x00440302
6340 01:55:04.962355
6341 01:55:04.969260 domain : l<6>[ 8.788871] Bluetooth: hci0: QCA Downloading qca/rampatch_00440302.bin
6342 01:55:04.982385 ava-rack <4>[ 8.798989] bluetooth hci0: Direct firmware load for qca/rampatch_00440302.bin failed with error -2
6343 01:55:04.992098 <3>[ 8.809950] Bluetooth: hci0: QCA Failed to request file: qca/rampatch_00440302.bin (-2)
6344 01:55:04.992177
6345 01:55:04.998644 <3>[ 8.819564] Bluetooth: hci0: QCA Failed to download patch (-2)
6346 01:55:04.998746
6347 01:55:05.002132 rootserver: 192.168.201.1 rootpath:
6348 01:55:05.002210 filename :
6349 01:55:05.005167 done.
6350 01:55:05.008347 Begin: Running /scripts/nfs-bottom ... done.
6351 01:55:05.021770 Begin: Running /scripts/init-bottom ... done.
6352 01:55:05.332346 <6>[ 9.151910] ath10k_sdio mmc1:0001:1: htt-ver 3.87 wmi-op 4 htt-op 3 cal otp max-sta 32 raw 0 hwcrypto 1
6353 01:55:05.416412 <4>[ 9.236170] mmc1: queuing unknown CIS tuple 0x01 [d9 01 ff] (3 bytes)
6354 01:55:05.436918 <4>[ 9.255794] mmc1: queuing unknown CIS tuple 0x1a [01 01 00 02 07] (5 bytes)
6355 01:55:05.451442 <4>[ 9.271069] mmc1: queuing unknown CIS tuple 0x1b [c1 41 30 30 ff ff 32 00] (8 bytes)
6356 01:55:05.461420 <4>[ 9.284540] mmc1: queuing unknown CIS tuple 0x14 [] (0 bytes)
6357 01:55:06.306604 <6>[ 10.129182] NET: Registered PF_INET6 protocol family
6358 01:55:06.318683 <6>[ 10.141669] Segment Routing with IPv6
6359 01:55:06.326855 <6>[ 10.150096] In-situ OAM (IOAM) with IPv6
6360 01:55:06.503117 <30>[ 10.296721] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
6361 01:55:06.520822 <30>[ 10.343972] systemd[1]: Detected architecture arm64.
6362 01:55:06.532241
6363 01:55:06.535317 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
6364 01:55:06.535393
6365 01:55:06.560617 <30>[ 10.383402] systemd[1]: Hostname set to <debian-bookworm-arm64>.
6366 01:55:07.495045 <30>[ 11.314416] systemd[1]: Queued start job for default target graphical.target.
6367 01:55:07.530669 <30>[ 11.350323] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
6368 01:55:07.543190 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
6369 01:55:07.564171 <30>[ 11.383543] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
6370 01:55:07.577310 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
6371 01:55:07.596241 <30>[ 11.415717] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
6372 01:55:07.610966 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
6373 01:55:07.626942 <30>[ 11.446845] systemd[1]: Created slice user.slice - User and Session Slice.
6374 01:55:07.639635 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
6375 01:55:07.661867 <30>[ 11.477863] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
6376 01:55:07.675007 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
6377 01:55:07.697420 <30>[ 11.513696] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
6378 01:55:07.710060 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
6379 01:55:07.736269 <30>[ 11.545643] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
6380 01:55:07.755859 <30>[ 11.575644] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
6381 01:55:07.763886 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
6382 01:55:07.781718 <30>[ 11.601470] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
6383 01:55:07.794709 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
6384 01:55:07.813853 <30>[ 11.633545] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
6385 01:55:07.828948 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
6386 01:55:07.842927 <30>[ 11.665555] systemd[1]: Reached target paths.target - Path Units.
6387 01:55:07.857254 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
6388 01:55:07.873933 <30>[ 11.693466] systemd[1]: Reached target remote-fs.target - Remote File Systems.
6389 01:55:07.886221 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
6390 01:55:07.898742 <30>[ 11.721449] systemd[1]: Reached target slices.target - Slice Units.
6391 01:55:07.913167 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
6392 01:55:07.926594 <30>[ 11.749506] systemd[1]: Reached target swap.target - Swaps.
6393 01:55:07.937519 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
6394 01:55:07.958120 <30>[ 11.777519] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
6395 01:55:07.971600 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
6396 01:55:07.990118 <30>[ 11.809914] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
6397 01:55:08.003847 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
6398 01:55:08.024758 <30>[ 11.844143] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
6399 01:55:08.038057 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
6400 01:55:08.056653 <30>[ 11.876441] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
6401 01:55:08.070733 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
6402 01:55:08.090559 <30>[ 11.910248] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
6403 01:55:08.103225 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
6404 01:55:08.124243 <30>[ 11.943303] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
6405 01:55:08.137160 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
6406 01:55:08.156383 <30>[ 11.976300] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
6407 01:55:08.170255 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
6408 01:55:08.186937 <30>[ 12.006064] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
6409 01:55:08.199397 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
6410 01:55:08.246034 <30>[ 12.065703] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
6411 01:55:08.258141 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
6412 01:55:08.270852 <30>[ 12.090592] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
6413 01:55:08.284281 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
6414 01:55:08.334409 <30>[ 12.154092] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
6415 01:55:08.345866 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
6416 01:55:08.369412 <30>[ 12.182159] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
6417 01:55:08.394325 <30>[ 12.213445] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
6418 01:55:08.407422 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
6419 01:55:08.432037 <30>[ 12.251607] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
6420 01:55:08.444312 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
6421 01:55:08.467179 <30>[ 12.286441] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
6422 01:55:08.477685 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
6423 01:55:08.502924 <30>[ 12.322467] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
6424 01:55:08.517143 Starting [0;1;39mmodprobe@drm.service<6>[ 12.335852] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
6425 01:55:08.520285 [0m - Load Kernel Module drm...
6426 01:55:08.549027 <30>[ 12.368109] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
6427 01:55:08.563216 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
6428 01:55:08.592774 <30>[ 12.412037] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
6429 01:55:08.606959 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
6430 01:55:08.631004 <30>[ 12.450711] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
6431 01:55:08.643467 Starting [0;1;39mmodprobe@loop.ser…e<6>[ 12.467053] fuse: init (API version 7.37)
6432 01:55:08.646789 [0m - Load Kernel Module loop...
6433 01:55:08.676781 <30>[ 12.496021] systemd[1]: Starting systemd-journald.service - Journal Service...
6434 01:55:08.689095 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
6435 01:55:08.714867 <30>[ 12.534238] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
6436 01:55:08.726311 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
6437 01:55:08.755323 <30>[ 12.571223] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
6438 01:55:08.766538 Starting [0;1;39msystemd-network-g… units from Kernel command line...
6439 01:55:08.788093 <30>[ 12.607512] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
6440 01:55:08.800922 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
6441 01:55:08.855025 <30>[ 12.674720] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
6442 01:55:08.867450 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
6443 01:55:08.892991 <30>[ 12.712481] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
6444 01:55:08.903066 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
6445 01:55:08.919702 <30>[ 12.738168] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
6446 01:55:08.925771 <3>[ 12.740789] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6447 01:55:08.944171 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue <3>[ 12.762104] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6448 01:55:08.944256 File System.
6449 01:55:08.962568 <3>[ 12.781663] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6450 01:55:08.970277 <30>[ 12.782879] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
6451 01:55:08.980060 <3>[ 12.797012] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6452 01:55:08.993889 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
6453 01:55:09.000384 <3>[ 12.820326] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6454 01:55:09.019754 <3>[ 12.838708] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6455 01:55:09.037291 <3>[ 12.856421] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6456 01:55:09.044516 <30>[ 12.858405] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
6457 01:55:09.056313 <3>[ 12.874288] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6458 01:55:09.068443 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
6459 01:55:09.087237 <30>[ 12.906829] systemd[1]: Started systemd-journald.service - Journal Service.
6460 01:55:09.097096 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
6461 01:55:09.119923 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
6462 01:55:09.141162 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
6463 01:55:09.160280 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
6464 01:55:09.184802 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
6465 01:55:09.204389 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
6466 01:55:09.224661 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
6467 01:55:09.243804 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
6468 01:55:09.263350 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
6469 01:55:09.283522 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
6470 01:55:09.304644 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
6471 01:55:09.358293 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
6472 01:55:09.379736 <4>[ 13.192869] synth uevent: /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:i2c-tunnel/i2c-12/12-000b/power_supply/sbs-12-000b: failed to send uevent
6473 01:55:09.390765 <3>[ 13.210585] power_supply sbs-12-000b: uevent: failed to send synthetic uevent: -5
6474 01:55:09.398357 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
6475 01:55:09.424618 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
6476 01:55:09.449995 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
6477 01:55:09.476502 <46>[ 13.295618] systemd-journald[317]: Received client request to flush runtime journal.
6478 01:55:09.493998 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
6479 01:55:09.518225 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
6480 01:55:09.799754 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
6481 01:55:09.819982 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
6482 01:55:09.838976 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
6483 01:55:09.860417 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
6484 01:55:10.253429 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
6485 01:55:10.915779 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
6486 01:55:10.935309 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
6487 01:55:10.983246 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
6488 01:55:11.048515 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
6489 01:55:11.066955 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
6490 01:55:11.086325 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
6491 01:55:11.131327 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
6492 01:55:11.159626 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
6493 01:55:11.381345 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
6494 01:55:11.399320 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
6495 01:55:11.454233 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
6496 01:55:11.598829 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
6497 01:55:11.621381 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
6498 01:55:11.684011 [[0;32m OK [<4>[ 15.503068] power_supply_show_property: 4 callbacks suppressed
6499 01:55:11.691785 0m] Found device<3>[ 15.503094] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6500 01:55:11.701590 [0;1;39mdev-tt<3>[ 15.508286] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6501 01:55:11.711774 yS0.device[0m -<3>[ 15.515830] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6502 01:55:11.711855 /dev/ttyS0.
6503 01:55:11.729845 <3>[ 15.548820] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6504 01:55:11.743833 <3>[ 15.563419] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6505 01:55:11.758800 <3>[ 15.577994] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6506 01:55:11.774702 <3>[ 15.594047] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6507 01:55:11.789623 <3>[ 15.608611] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6508 01:55:11.804872 <3>[ 15.623593] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6509 01:55:11.819290 <3>[ 15.638471] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6510 01:55:11.911216 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
6511 01:55:11.972047 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
6512 01:55:11.990735 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
6513 01:55:12.006333 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
6514 01:55:12.023131 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
6515 01:55:12.055107 Starting [0;1;39msystemd-backlight…ess of backlight:backlight_lcd0...
6516 01:55:12.074634 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
6517 01:55:12.095310 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
6518 01:55:12.119286 <46>[ 15.939000] systemd-journald[317]: Time jumped backwards, rotating.
6519 01:55:12.130380 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of backlight:backlight_lcd0.
6520 01:55:12.153506 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
6521 01:55:12.171135 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
6522 01:55:12.186656 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
6523 01:55:12.202119 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
6524 01:55:12.924133 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
6525 01:55:13.255126 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
6526 01:55:13.275785 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
6527 01:55:13.635347 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
6528 01:55:13.660934 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
6529 01:55:13.678383 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
6530 01:55:13.696340 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
6531 01:55:13.714713 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
6532 01:55:13.730455 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
6533 01:55:13.778659 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
6534 01:55:13.812698 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
6535 01:55:13.895211 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
6536 01:55:13.921312 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
6537 01:55:13.942397 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
6538 01:55:14.088661 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
6539 01:55:14.143819 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
6540 01:55:14.199357 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
6541 01:55:14.219133 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
6542 01:55:14.230077 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
6543 01:55:14.247104 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
6544 01:55:14.276538 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
6545 01:55:14.297415 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
6546 01:55:14.317233 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
6547 01:55:14.341390 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
6548 01:55:14.389906 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
6549 01:55:14.440304 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
6550 01:55:14.512147
6551 01:55:14.515441 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
6552 01:55:14.515525
6553 01:55:14.518169 debian-bookworm-arm64 login: root (automatic login)
6554 01:55:14.518239
6555 01:55:14.772036 Linux debian-bookworm-arm64 6.1.94-cip23 #1 SMP PREEMPT Fri Jun 21 00:04:56 UTC 2024 aarch64
6556 01:55:14.772163
6557 01:55:14.778073 The programs included with the Debian GNU/Linux system are free software;
6558 01:55:14.784761 the exact distribution terms for each program are described in the
6559 01:55:14.788051 individual files in /usr/share/doc/*/copyright.
6560 01:55:14.788120
6561 01:55:14.795009 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
6562 01:55:14.798158 permitted by applicable law.
6563 01:55:14.841914 Matched prompt #10: / #
6565 01:55:14.842126 Setting prompt string to ['/ #']
6566 01:55:14.842215 end: 2.2.5.1 login-action (duration 00:00:19) [common]
6568 01:55:14.842390 end: 2.2.5 auto-login-action (duration 00:00:19) [common]
6569 01:55:14.842477 start: 2.2.6 expect-shell-connection (timeout 00:03:47) [common]
6570 01:55:14.842542 Setting prompt string to ['/ #']
6571 01:55:14.842598 Forcing a shell prompt, looking for ['/ #']
6573 01:55:14.892798 / #
6574 01:55:14.892961 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
6575 01:55:14.893054 Waiting using forced prompt support (timeout 00:02:30)
6576 01:55:14.897496
6577 01:55:14.897789 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
6578 01:55:14.897900 start: 2.2.7 export-device-env (timeout 00:03:47) [common]
6580 01:55:14.998173 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14479155/extract-nfsrootfs-t4oh8com'
6581 01:55:15.003934 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14479155/extract-nfsrootfs-t4oh8com'
6583 01:55:15.104451 / # export NFS_SERVER_IP='192.168.201.1'
6584 01:55:15.108972 export NFS_SERVER_IP='192.168.201.1'
6585 01:55:15.109244 end: 2.2.7 export-device-env (duration 00:00:00) [common]
6586 01:55:15.109334 end: 2.2 depthcharge-retry (duration 00:01:13) [common]
6587 01:55:15.109424 end: 2 depthcharge-action (duration 00:01:13) [common]
6588 01:55:15.109507 start: 3 lava-test-retry (timeout 00:30:00) [common]
6589 01:55:15.109600 start: 3.1 lava-test-shell (timeout 00:30:00) [common]
6590 01:55:15.109668 Using namespace: common
6592 01:55:15.209958 / # #
6593 01:55:15.210150 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:30:00)
6594 01:55:15.214717 #
6595 01:55:15.214992 Using /lava-14479155
6597 01:55:15.315337 / # export SHELL=/bin/sh
6598 01:55:15.320141 export SHELL=/bin/sh
6600 01:55:15.420689 / # . /lava-14479155/environment
6601 01:55:15.425965 . /lava-14479155/environment
6603 01:55:15.531446 / # /lava-14479155/bin/lava-test-runner /lava-14479155/0
6604 01:55:15.532037 Test shell timeout: 10s (minimum of the action and connection timeout)
6605 01:55:15.537594 /lava-14479155/bin/lava-test-runner /lava-14479155/0
6606 01:55:15.718579 + export TESTRUN_ID=0_lc-compliance
6607 01:55:15.725385 + cd /lava-14479155/0/tests/0_lc-compliance
6608 01:55:15.725466 + cat uuid
6609 01:55:15.728070 + UUID=14479155_1.6.2.3.1
6610 01:55:15.728136 + set +x
6611 01:55:15.735275 <LAVA_SIGNAL_STARTRUN 0_lc-compliance 14479155_1.6.2.3.1>
6612 01:55:15.735525 Received signal: <STARTRUN> 0_lc-compliance 14479155_1.6.2.3.1
6613 01:55:15.735590 Starting test lava.0_lc-compliance (14479155_1.6.2.3.1)
6614 01:55:15.735667 Skipping test definition patterns.
6615 01:55:15.738085 + /usr/bin/lc-compliance-parser.sh
6616 01:55:17.375818 [0:00:21.050389847] [429] [1;32m INFO [1;37mCamera [1;34mcamera_manager.cpp:284 [0mlibcamera v0.0.0+1-01935edb
6617 01:55:17.382464 Using camera /base/soc/usb@11201000/usb@11200000/hub@1-1.3:1.0-04f2:b567
6618 01:55:17.434643 [0:00:21.108944770] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6619 01:55:17.437772 [==========] Running 120 tests from 1 test suite.
6620 01:55:17.490387 [----------] Global test environment set-up.
6621 01:55:17.507331 [0:00:21.182188231] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6622 01:55:17.559572 [----------] 120 tests from CaptureTests/SingleStream
6623 01:55:17.586062 [0:00:21.260583462] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6624 01:55:17.613442 [ RUN ] CaptureTests/SingleStream.Capture/Raw_1
6625 01:55:17.652626 [0:00:21.327394924] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6626 01:55:17.665997 <LAVA_SIGNAL_TESTSET START CaptureTests/SingleStream>
6627 01:55:17.666252 Received signal: <TESTSET> START CaptureTests/SingleStream
6628 01:55:17.666326 Starting test_set CaptureTests/SingleStream
6629 01:55:17.669105 Camera needs 4 requests, can't test only 1
6630 01:55:17.727599 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
6631 01:55:17.779251
6632 01:55:17.837213 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_1 (72 ms)
6633 01:55:17.914287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_1 RESULT=skip>
6634 01:55:17.914568 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_1 RESULT=skip
6636 01:55:17.924783 [ RUN ] CaptureTests/SingleStream.Capture/Raw_2
6637 01:55:17.961106 Camera needs 4 requests, can't test only 2
6638 01:55:18.025045 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
6639 01:55:18.083840
6640 01:55:18.142233 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_2 (64 ms)
6641 01:55:18.199246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_2 RESULT=skip>
6642 01:55:18.199499 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_2 RESULT=skip
6644 01:55:18.212651 [ RUN ] CaptureTests/SingleStream.Capture/Raw_3
6645 01:55:18.251292 Camera needs 4 requests, can't test only 3
6646 01:55:18.280129 [0:00:21.954944078] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6647 01:55:18.306440 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
6648 01:55:18.362080
6649 01:55:18.422723 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_3 (81 ms)
6650 01:55:18.484934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_3 RESULT=skip>
6651 01:55:18.485198 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_3 RESULT=skip
6653 01:55:18.496430 [ RUN ] CaptureTests/SingleStream.Capture/Raw_5
6654 01:55:18.535531 [ OK ] CaptureTests/SingleStream.Capture/Raw_5 (470 ms)
6655 01:55:18.601458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_5 RESULT=pass>
6656 01:55:18.601761 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_5 RESULT=pass
6658 01:55:18.612373 [ RUN ] CaptureTests/SingleStream.Capture/Raw_8
6659 01:55:18.790718 [ OK ] CaptureTests/SingleStream.Capture/Raw_8 (714 ms)
6660 01:55:18.849493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_8 RESULT=pass>
6661 01:55:18.849832 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_8 RESULT=pass
6663 01:55:18.860336 [ RUN ] CaptureTests/SingleStream.Capture/Raw_13
6664 01:55:18.891704 [0:00:22.566430616] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6665 01:55:19.567723 [ OK ] CaptureTests/SingleStream.Capture/Raw_13 (776 ms)
6666 01:55:19.612217 [0:00:23.286567001] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6667 01:55:19.640653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_13 RESULT=pass>
6668 01:55:19.640916 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_13 RESULT=pass
6670 01:55:19.653524 [ RUN ] CaptureTests/SingleStream.Capture/Raw_21
6671 01:55:21.007129 [ OK ] CaptureTests/SingleStream.Capture/Raw_21 (1439 ms)
6672 01:55:21.052102 [0:00:24.726585385] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6673 01:55:21.083156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_21 RESULT=pass>
6674 01:55:21.083430 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_21 RESULT=pass
6676 01:55:21.100879 [ RUN ] CaptureTests/SingleStream.Capture/Raw_34
6677 01:55:24.818928 [ OK ] CaptureTests/SingleStream.Capture/Raw_34 (3811 ms)
6678 01:55:24.863426 [0:00:28.537707924] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6679 01:55:24.903894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_34 RESULT=pass>
6680 01:55:24.904235 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_34 RESULT=pass
6682 01:55:24.919432 [ RUN ] CaptureTests/SingleStream.Capture/Raw_55
6683 01:55:30.721789 [ OK ] CaptureTests/SingleStream.Capture/Raw_55 (5902 ms)
6684 01:55:30.767509 [0:00:34.440062848] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6685 01:55:30.818985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_55 RESULT=pass>
6686 01:55:30.819676 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_55 RESULT=pass
6688 01:55:30.837444 [ RUN ] CaptureTests/SingleStream.Capture/Raw_89
6689 01:55:34.168652 <6>[ 37.993919] vaux18: disabling
6690 01:55:34.171864 <6>[ 37.997460] vio28: disabling
6691 01:55:40.016511 [ OK ] CaptureTests/SingleStream.Capture/Raw_89 (9294 ms)
6692 01:55:40.061059 [0:00:43.735349310] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6693 01:55:40.092748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_89 RESULT=pass>
6694 01:55:40.093004 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_89 RESULT=pass
6696 01:55:40.107758 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_1
6697 01:55:40.124721 [0:00:43.798745463] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6698 01:55:40.159374 Camera needs 4 requests, can't test only 1
6699 01:55:40.189106 [0:00:43.862654540] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6700 01:55:40.240063 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
6701 01:55:40.249939 [0:00:43.925622310] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6702 01:55:40.317361
6703 01:55:40.392655 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_1 (62 ms)
6704 01:55:40.476380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip>
6705 01:55:40.476678 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip
6707 01:55:40.490531 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_2
6708 01:55:40.534343 Camera needs 4 requests, can't test only 2
6709 01:55:40.618689 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
6710 01:55:40.695712
6711 01:55:40.778211 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_2 (63 ms)
6712 01:55:40.873034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip>
6713 01:55:40.873707 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip
6715 01:55:40.888552 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_3
6716 01:55:40.942735 Camera needs 4 requests, can't test only 3
6717 01:55:41.023096 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
6718 01:55:41.101321
6719 01:55:41.184903 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_3 (63 ms)
6720 01:55:41.269893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip>
6721 01:55:41.270386 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip
6723 01:55:41.283256 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_5
6724 01:55:41.779720 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_5 (1573 ms)
6725 01:55:41.823674 [0:00:45.497965310] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6726 01:55:41.879881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass>
6727 01:55:41.880196 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass
6729 01:55:41.897148 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_8
6730 01:55:42.999779 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_8 (1219 ms)
6731 01:55:43.043231 [0:00:46.717158771] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6732 01:55:43.081670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass>
6733 01:55:43.082017 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass
6735 01:55:43.093598 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_13
6736 01:55:44.718620 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_13 (1719 ms)
6737 01:55:44.762665 [0:00:48.436536387] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6738 01:55:44.801226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass>
6739 01:55:44.801485 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass
6741 01:55:44.814198 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_21
6742 01:55:47.234486 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_21 (2515 ms)
6743 01:55:47.278952 [0:00:50.951905772] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6744 01:55:47.330304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass>
6745 01:55:47.331017 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass
6747 01:55:47.347731 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_34
6748 01:55:51.047271 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_34 (3812 ms)
6749 01:55:51.092028 [0:00:54.765565387] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6750 01:55:51.137705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass>
6751 01:55:51.138343 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass
6753 01:55:51.152403 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_55
6754 01:55:56.951460 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_55 (5904 ms)
6755 01:55:56.996571 [0:01:00.670479926] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6756 01:55:57.026358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass>
6757 01:55:57.026651 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass
6759 01:55:57.038793 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_89
6760 01:56:06.249268 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_89 (9297 ms)
6761 01:56:06.295776 [0:01:09.969282311] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6762 01:56:06.327061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass>
6763 01:56:06.327377 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass
6765 01:56:06.341037 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_1
6766 01:56:06.363905 [0:01:10.037606850] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6767 01:56:06.383734 Camera needs 4 requests, can't test only 1
6768 01:56:06.430675 [0:01:10.104078542] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6769 01:56:06.439302 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
6770 01:56:06.495366 [0:01:10.169167927] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6771 01:56:06.495503
6772 01:56:06.556094 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_1 (66 ms)
6773 01:56:06.626791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip>
6774 01:56:06.627110 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip
6776 01:56:06.639409 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_2
6777 01:56:06.681757 Camera needs 4 requests, can't test only 2
6778 01:56:06.738679 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
6779 01:56:06.800990
6780 01:56:06.858943 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_2 (67 ms)
6781 01:56:06.923348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip>
6782 01:56:06.923672 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip
6784 01:56:06.935837 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_3
6785 01:56:06.978044 Camera needs 4 requests, can't test only 3
6786 01:56:07.033628 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
6787 01:56:07.091753
6788 01:56:07.154269 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_3 (67 ms)
6789 01:56:07.228132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip>
6790 01:56:07.228432 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip
6792 01:56:07.239868 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_5
6793 01:56:08.016051 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_5 (1564 ms)
6794 01:56:08.060512 [0:01:11.734015773] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6795 01:56:08.098314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass>
6796 01:56:08.098605 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass
6798 01:56:08.111293 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_8
6799 01:56:09.234786 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_8 (1218 ms)
6800 01:56:09.279608 [0:01:12.953016619] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6801 01:56:09.311628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass>
6802 01:56:09.311916 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass
6804 01:56:09.324704 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_13
6805 01:56:10.960502 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_13 (1721 ms)
6806 01:56:11.000660 [0:01:14.674290696] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6807 01:56:11.024502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass>
6808 01:56:11.024762 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass
6810 01:56:11.037751 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_21
6811 01:56:13.476125 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_21 (2515 ms)
6812 01:56:13.516752 [0:01:17.189665773] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6813 01:56:13.551305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass>
6814 01:56:13.551622 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass
6816 01:56:13.562904 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_34
6817 01:56:17.287597 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_34 (3811 ms)
6818 01:56:17.328686 [0:01:21.002071158] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6819 01:56:17.369440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass>
6820 01:56:17.369782 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass
6822 01:56:17.383304 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_55
6823 01:56:23.193286 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_55 (5904 ms)
6824 01:56:23.235308 [0:01:26.908160928] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6825 01:56:23.283985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass>
6826 01:56:23.284638 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass
6828 01:56:23.298157 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_89
6829 01:56:32.491982 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_89 (9298 ms)
6830 01:56:32.534284 [0:01:36.207368620] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6831 01:56:32.573874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass>
6832 01:56:32.574133 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass
6834 01:56:32.585319 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_1
6835 01:56:32.597757 [0:01:36.270718082] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6836 01:56:32.627110 Camera needs 4 requests, can't test only 1
6837 01:56:32.663238 [0:01:36.336057390] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6838 01:56:32.710575 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
6839 01:56:32.735599 [0:01:36.408242390] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6840 01:56:32.781974
6841 01:56:32.858979 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_1 (64 ms)
6842 01:56:32.943972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip>
6843 01:56:32.944261 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip
6845 01:56:32.956464 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_2
6846 01:56:33.004986 Camera needs 4 requests, can't test only 2
6847 01:56:33.082944 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
6848 01:56:33.156765
6849 01:56:33.241619 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_2 (63 ms)
6850 01:56:33.335605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip>
6851 01:56:33.336300 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip
6853 01:56:33.350836 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_3
6854 01:56:33.404411 Camera needs 4 requests, can't test only 3
6855 01:56:33.474610 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
6856 01:56:33.547734
6857 01:56:33.628272 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_3 (70 ms)
6858 01:56:33.705460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip>
6859 01:56:33.705760 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip
6861 01:56:33.720235 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_5
6862 01:56:34.255746 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_5 (1568 ms)
6863 01:56:34.302683 [0:01:37.975640082] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6864 01:56:34.331851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass>
6865 01:56:34.332109 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass
6867 01:56:34.344418 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_8
6868 01:56:35.478830 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_8 (1222 ms)
6869 01:56:35.523367 [0:01:39.196241774] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6870 01:56:35.543577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass>
6871 01:56:35.543828 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass
6873 01:56:35.555215 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_13
6874 01:56:37.198303 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_13 (1719 ms)
6875 01:56:37.243560 [0:01:40.916131928] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6876 01:56:37.267390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass>
6877 01:56:37.267644 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass
6879 01:56:37.279917 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_21
6880 01:56:39.714085 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_21 (2515 ms)
6881 01:56:39.759228 [0:01:43.431866852] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6882 01:56:39.775184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass>
6883 01:56:39.775439 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass
6885 01:56:39.787314 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_34
6886 01:56:43.527261 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_34 (3813 ms)
6887 01:56:43.573054 [0:01:47.245935313] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6888 01:56:43.591833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass>
6889 01:56:43.592135 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass
6891 01:56:43.601909 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_55
6892 01:56:49.432719 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_55 (5905 ms)
6893 01:56:49.477522 [0:01:53.150594160] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6894 01:56:49.498855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass>
6895 01:56:49.499142 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass
6897 01:56:49.511452 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_89
6898 01:56:58.729000 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_89 (9295 ms)
6899 01:56:58.774614 [0:02:02.446971314] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6900 01:56:58.796398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass>
6901 01:56:58.796670 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass
6903 01:56:58.808779 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_1
6904 01:56:58.838019 [0:02:02.510456237] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6905 01:56:58.850043 Camera needs 4 requests, can't test only 1
6906 01:56:58.904508 [0:02:02.576652391] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6907 01:56:58.907102 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
6908 01:56:58.970099 [0:02:02.642611699] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6909 01:56:58.974604
6910 01:56:59.041054 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_1 (63 ms)
6911 01:56:59.119728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip>
6912 01:56:59.120015 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip
6914 01:56:59.133858 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_2
6915 01:56:59.183398 Camera needs 4 requests, can't test only 2
6916 01:56:59.256326 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
6917 01:56:59.322701
6918 01:56:59.397329 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_2 (64 ms)
6919 01:56:59.474693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip>
6920 01:56:59.475048 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip
6922 01:56:59.488513 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_3
6923 01:56:59.538567 Camera needs 4 requests, can't test only 3
6924 01:56:59.605354 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
6925 01:56:59.668037
6926 01:56:59.736980 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_3 (67 ms)
6927 01:56:59.809708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip>
6928 01:56:59.809986 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip
6930 01:56:59.823767 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_5
6931 01:57:02.238403 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_5 (3313 ms)
6932 01:57:02.283367 [0:02:05.955657161] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6933 01:57:02.311729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass>
6934 01:57:02.312361 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass
6936 01:57:02.329274 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_8
6937 01:57:05.801897 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_8 (3562 ms)
6938 01:57:05.846723 [0:02:09.518779161] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6939 01:57:05.897195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass>
6940 01:57:05.897890 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass
6942 01:57:05.912276 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_13
6943 01:57:10.860443 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_13 (5058 ms)
6944 01:57:10.905189 [0:02:14.577019084] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6945 01:57:10.945430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass>
6946 01:57:10.946149 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass
6948 01:57:10.962473 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_21
6949 01:57:18.306393 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_21 (7446 ms)
6950 01:57:18.351127 [0:02:22.023161239] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6951 01:57:18.376718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass>
6952 01:57:18.376971 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass
6954 01:57:18.389516 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_34
6955 01:57:29.641651 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_34 (11334 ms)
6956 01:57:29.685953 [0:02:33.357891778] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6957 01:57:29.715248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass>
6958 01:57:29.715512 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass
6960 01:57:29.728623 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_55
6961 01:57:47.263816 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_55 (17618 ms)
6962 01:57:47.306060 [0:02:50.976994933] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6963 01:57:47.352234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass>
6964 01:57:47.352920 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass
6966 01:57:47.368967 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_89
6967 01:58:15.052928 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_89 (27792 ms)
6968 01:58:15.097893 [0:03:18.768946319] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6969 01:58:15.123046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass>
6970 01:58:15.123405 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass
6972 01:58:15.133572 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1
6973 01:58:15.160717 [0:03:18.831428550] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6974 01:58:15.169675 Camera needs 4 requests, can't test only 1
6975 01:58:15.222844 [0:03:18.893961396] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6976 01:58:15.226476 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
6977 01:58:15.267342
6978 01:58:15.285108 [0:03:18.956361088] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6979 01:58:15.327315 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1 (62 ms)
6980 01:58:15.386471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip>
6981 01:58:15.386783 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip
6983 01:58:15.395187 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2
6984 01:58:15.432307 Camera needs 4 requests, can't test only 2
6985 01:58:15.485618 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
6986 01:58:15.535521
6987 01:58:15.595145 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2 (63 ms)
6988 01:58:15.657836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip>
6989 01:58:15.658135 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip
6991 01:58:15.665086 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3
6992 01:58:15.702613 Camera needs 4 requests, can't test only 3
6993 01:58:15.755195 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
6994 01:58:15.804506
6995 01:58:15.869218 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3 (61 ms)
6996 01:58:15.935881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip>
6997 01:58:15.936184 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip
6999 01:58:15.943185 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5
7000 01:58:18.558458 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5 (3314 ms)
7001 01:58:18.603119 [0:03:22.273930319] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7002 01:58:18.642762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass>
7003 01:58:18.643046 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass
7005 01:58:18.651536 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8
7006 01:58:22.128501 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8 (3569 ms)
7007 01:58:22.172280 [0:03:25.842626550] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7008 01:58:22.209349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass>
7009 01:58:22.210091 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass
7011 01:58:22.219151 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13
7012 01:58:27.190660 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13 (5061 ms)
7013 01:58:27.230939 [0:03:30.901622627] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7014 01:58:27.279401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass>
7015 01:58:27.280195 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass
7017 01:58:27.293577 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21
7018 01:58:34.636651 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21 (7446 ms)
7019 01:58:34.677732 [0:03:38.347935474] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7020 01:58:34.696423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass>
7021 01:58:34.696715 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass
7023 01:58:34.706041 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34
7024 01:58:45.971662 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34 (11334 ms)
7025 01:58:46.012243 [0:03:49.682314090] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7026 01:58:46.048281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass>
7027 01:58:46.048537 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass
7029 01:58:46.056766 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55
7030 01:59:03.581338 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55 (17609 ms)
7031 01:59:03.622703 [0:04:07.291981014] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7032 01:59:03.652671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass>
7033 01:59:03.653522 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass
7035 01:59:03.662849 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89
7036 01:59:31.367547 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89 (27785 ms)
7037 01:59:31.408771 [0:04:35.078260323] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7038 01:59:31.432510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass>
7039 01:59:31.432801 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass
7041 01:59:31.440650 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1
7042 01:59:31.471195 [0:04:35.140635939] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7043 01:59:31.474351 Camera needs 4 requests, can't test only 1
7044 01:59:31.535080 [0:04:35.203962708] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7045 01:59:31.538311 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
7046 01:59:31.581661
7047 01:59:31.598303 [0:04:35.267431785] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7048 01:59:31.642945 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1 (61 ms)
7049 01:59:31.702230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip>
7050 01:59:31.702528 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip
7052 01:59:31.709832 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2
7053 01:59:31.744077 Camera needs 4 requests, can't test only 2
7054 01:59:31.794122 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
7055 01:59:31.844770
7056 01:59:31.904803 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2 (63 ms)
7057 01:59:31.960652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip>
7058 01:59:31.960940 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip
7060 01:59:31.969266 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3
7061 01:59:32.009782 Camera needs 4 requests, can't test only 3
7062 01:59:32.060389 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
7063 01:59:32.109133
7064 01:59:32.166131 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3 (62 ms)
7065 01:59:32.232657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip>
7066 01:59:32.232960 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip
7068 01:59:32.241984 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5
7069 01:59:34.878619 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5 (3322 ms)
7070 01:59:34.919492 [0:04:38.589205631] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7071 01:59:34.939996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass>
7072 01:59:34.940284 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass
7074 01:59:34.950038 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8
7075 01:59:38.446656 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8 (3568 ms)
7076 01:59:38.488386 [0:04:42.157613170] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7077 01:59:38.510408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass>
7078 01:59:38.510686 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass
7080 01:59:38.518590 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13
7081 01:59:43.512978 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13 (5065 ms)
7082 01:59:43.554796 [0:04:47.223452324] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7083 01:59:43.579093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass>
7084 01:59:43.579372 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass
7086 01:59:43.588090 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21
7087 01:59:50.961933 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21 (7448 ms)
7088 01:59:51.003819 [0:04:54.672980940] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7089 01:59:51.029727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass>
7090 01:59:51.030046 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass
7092 01:59:51.038109 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34
7093 02:00:02.298681 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34 (11335 ms)
7094 02:00:02.339449 [0:05:06.008087325] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7095 02:00:02.366648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass>
7096 02:00:02.366937 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass
7098 02:00:02.379489 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55
7099 02:00:19.909591 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55 (17610 ms)
7100 02:00:19.950297 [0:05:23.618575634] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7101 02:00:19.974324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass>
7102 02:00:19.974612 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass
7104 02:00:19.984210 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89
7105 02:00:47.695933 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89 (27785 ms)
7106 02:00:47.736545 [0:05:51.404641943] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7107 02:00:47.771074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass>
7108 02:00:47.771428 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass
7110 02:00:47.779026 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1
7111 02:00:47.800025 [0:05:51.467722559] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7112 02:00:47.818446 Camera needs 4 requests, can't test only 1
7113 02:00:47.864095 [0:05:51.532105251] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7114 02:00:47.872080 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
7115 02:00:47.930100 [0:05:51.597665251] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7116 02:00:47.930274
7117 02:00:47.997505 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1 (62 ms)
7118 02:00:48.058121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip>
7119 02:00:48.058469 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip
7121 02:00:48.067090 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2
7122 02:00:48.106211 Camera needs 4 requests, can't test only 2
7123 02:00:48.161965 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
7124 02:00:48.218005
7125 02:00:48.278806 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2 (62 ms)
7126 02:00:48.339209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip>
7127 02:00:48.339544 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip
7129 02:00:48.347615 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3
7130 02:00:48.387224 Camera needs 4 requests, can't test only 3
7131 02:00:48.445231 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
7132 02:00:48.499689
7133 02:00:48.562453 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3 (67 ms)
7134 02:00:48.627864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip>
7135 02:00:48.628200 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip
7137 02:00:48.635592 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5
7138 02:00:51.199759 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5 (3312 ms)
7139 02:00:51.242504 [0:05:54.910405097] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7140 02:00:51.277900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass>
7141 02:00:51.278199 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass
7143 02:00:51.288024 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8
7144 02:00:54.767321 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8 (3566 ms)
7145 02:00:54.809377 [0:05:58.476843713] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7146 02:00:54.841375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass>
7147 02:00:54.841746 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass
7149 02:00:54.849473 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13
7150 02:00:59.827081 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13 (5059 ms)
7151 02:00:59.868032 [0:06:03.535252175] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7152 02:00:59.912976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass>
7153 02:00:59.913868 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass
7155 02:00:59.924485 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21
7156 02:01:07.275176 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21 (7448 ms)
7157 02:01:07.317322 [0:06:10.984968868] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7158 02:01:07.348198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass>
7159 02:01:07.348526 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass
7161 02:01:07.357462 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34
7162 02:01:18.612868 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34 (11336 ms)
7163 02:01:18.655980 [0:06:22.322901330] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7164 02:01:18.681228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass>
7165 02:01:18.681497 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass
7167 02:01:18.690006 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55
7168 02:01:36.227621 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55 (17614 ms)
7169 02:01:36.268490 [0:06:39.935302331] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7170 02:01:36.304266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass>
7171 02:01:36.304530 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass
7173 02:01:36.314187 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89
7174 02:02:04.014799 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89 (27786 ms)
7175 02:02:04.055211 [0:07:07.721678179] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7176 02:02:04.103329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass>
7177 02:02:04.103624 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass
7179 02:02:04.113104 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_1
7180 02:02:04.536222 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_1 (525 ms)
7181 02:02:04.611632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass>
7182 02:02:04.611916 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass
7184 02:02:04.624618 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_2
7185 02:02:04.801515 [0:07:08.467390948] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7186 02:02:05.382743 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_2 (846 ms)
7187 02:02:05.461281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass>
7188 02:02:05.461590 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass
7190 02:02:05.474540 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_3
7191 02:02:05.548300 [0:07:09.214816717] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7192 02:02:06.227172 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_3 (843 ms)
7193 02:02:06.295708 [0:07:09.962191948] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7194 02:02:06.302434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass>
7195 02:02:06.302690 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass
7197 02:02:06.316364 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_5
7198 02:02:07.173723 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_5 (946 ms)
7199 02:02:07.218190 [0:07:10.884222333] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7200 02:02:07.288615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass>
7201 02:02:07.288900 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass
7203 02:02:07.301135 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_8
7204 02:02:08.394810 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_8 (1221 ms)
7205 02:02:08.438927 [0:07:12.105319179] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7206 02:02:08.474398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass>
7207 02:02:08.474726 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass
7209 02:02:08.486825 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_13
7210 02:02:10.113950 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_13 (1719 ms)
7211 02:02:10.158537 [0:07:13.824725871] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7212 02:02:10.187664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass>
7213 02:02:10.187921 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass
7215 02:02:10.201168 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_21
7216 02:02:12.630418 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_21 (2514 ms)
7217 02:02:12.674946 [0:07:16.341157641] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7218 02:02:12.702343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass>
7219 02:02:12.702629 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass
7221 02:02:12.714377 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_34
7222 02:02:16.443737 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_34 (3814 ms)
7223 02:02:16.490535 [0:07:20.156782026] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7224 02:02:16.523438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass>
7225 02:02:16.523739 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass
7227 02:02:16.536820 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_55
7228 02:02:22.353920 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_55 (5908 ms)
7229 02:02:22.398500 [0:07:26.064218949] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7230 02:02:22.429961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass>
7231 02:02:22.430231 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass
7233 02:02:22.443089 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_89
7234 02:02:31.651023 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_89 (9297 ms)
7235 02:02:31.695665 [0:07:35.361092642] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7236 02:02:31.729900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass>
7237 02:02:31.730207 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass
7239 02:02:31.743692 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1
7240 02:02:32.181244 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1 (526 ms)
7241 02:02:32.250652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass>
7242 02:02:32.250955 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass
7244 02:02:32.260608 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2
7245 02:02:32.443232 [0:07:36.108845026] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7246 02:02:33.028765 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2 (846 ms)
7247 02:02:33.100416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass>
7248 02:02:33.100721 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass
7250 02:02:33.109208 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3
7251 02:02:33.191065 [0:07:36.856837565] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7252 02:02:33.872645 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3 (844 ms)
7253 02:02:33.934166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass>
7254 02:02:33.934465 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass
7256 02:02:33.943520 [0:07:37.604271873] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7257 02:02:33.950233 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5
7258 02:02:34.821258 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5 (947 ms)
7259 02:02:34.861886 [0:07:38.527184334] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7260 02:02:34.897857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass>
7261 02:02:34.898147 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass
7263 02:02:34.909002 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8
7264 02:02:36.042291 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8 (1221 ms)
7265 02:02:36.083265 [0:07:39.748643796] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7266 02:02:36.120472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass>
7267 02:02:36.120752 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass
7269 02:02:36.128742 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13
7270 02:02:37.765035 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13 (1722 ms)
7271 02:02:37.805045 [0:07:41.470906027] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7272 02:02:37.842171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass>
7273 02:02:37.842460 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass
7275 02:02:37.852930 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21
7276 02:02:40.282826 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21 (2517 ms)
7277 02:02:40.323399 [0:07:43.988564489] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7278 02:02:40.359033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass>
7279 02:02:40.359303 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass
7281 02:02:40.368329 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34
7282 02:02:44.097571 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34 (3815 ms)
7283 02:02:44.139141 [0:07:47.804391181] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7284 02:02:44.167206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass>
7285 02:02:44.167463 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass
7287 02:02:44.177309 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55
7288 02:02:50.002798 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55 (5904 ms)
7289 02:02:50.043593 [0:07:53.708796951] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7290 02:02:50.083671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass>
7291 02:02:50.084476 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass
7293 02:02:50.096603 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89
7294 02:02:59.296100 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89 (9293 ms)
7295 02:02:59.337681 [0:08:03.002962567] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7296 02:02:59.364318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass>
7297 02:02:59.364608 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass
7299 02:02:59.375556 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1
7300 02:02:59.822494 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1 (525 ms)
7301 02:02:59.902053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass>
7302 02:02:59.902342 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass
7304 02:02:59.911719 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2
7305 02:03:00.083609 [0:08:03.748402105] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7306 02:03:00.669084 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2 (846 ms)
7307 02:03:00.751700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass>
7308 02:03:00.752534 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass
7310 02:03:00.763961 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3
7311 02:03:00.830695 [0:08:04.495302413] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7312 02:03:01.509780 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3 (840 ms)
7313 02:03:01.575779 [0:08:05.240583874] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7314 02:03:01.586830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass>
7315 02:03:01.587552 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass
7317 02:03:01.601096 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5
7318 02:03:02.454475 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5 (945 ms)
7319 02:03:02.495449 [0:08:06.160826490] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7320 02:03:02.529885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass>
7321 02:03:02.530156 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass
7323 02:03:02.539556 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8
7324 02:03:03.677484 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8 (1222 ms)
7325 02:03:03.718837 [0:08:07.383573721] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7326 02:03:03.750621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass>
7327 02:03:03.751236 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass
7329 02:03:03.759213 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13
7330 02:03:05.399905 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13 (1722 ms)
7331 02:03:05.440684 [0:08:09.105489798] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7332 02:03:05.486533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass>
7333 02:03:05.486791 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass
7335 02:03:05.495909 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21
7336 02:03:07.918204 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21 (2517 ms)
7337 02:03:07.958481 [0:08:11.623482490] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7338 02:03:07.994206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass>
7339 02:03:07.994614 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass
7341 02:03:08.004505 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34
7342 02:03:11.731295 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34 (3813 ms)
7343 02:03:11.772769 [0:08:15.437069875] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7344 02:03:11.821237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass>
7345 02:03:11.822064 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass
7347 02:03:11.833079 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55
7348 02:03:17.637035 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55 (5904 ms)
7349 02:03:17.677865 [0:08:21.342319106] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7350 02:03:17.719441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass>
7351 02:03:17.720119 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass
7353 02:03:17.729989 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89
7354 02:03:26.934046 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89 (9296 ms)
7355 02:03:26.975296 [0:08:30.638991107] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7356 02:03:27.013791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass>
7357 02:03:27.014581 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass
7359 02:03:27.025705 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1
7360 02:03:27.457195 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1 (523 ms)
7361 02:03:27.527628 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass
7363 02:03:27.530367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass>
7364 02:03:27.540339 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2
7365 02:03:27.719235 [0:08:31.383056337] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7366 02:03:28.303345 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2 (846 ms)
7367 02:03:28.359131 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass
7369 02:03:28.362056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass>
7370 02:03:28.370142 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3
7371 02:03:28.466028 [0:08:32.130432338] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7372 02:03:29.151265 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3 (847 ms)
7373 02:03:29.213475 [0:08:32.877610953] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7374 02:03:29.221150 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass
7376 02:03:29.224280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass>
7377 02:03:29.231915 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5
7378 02:03:30.098480 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5 (946 ms)
7379 02:03:30.141902 [0:08:33.805942030] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7380 02:03:30.193769 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass
7382 02:03:30.196519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass>
7383 02:03:30.206727 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8
7384 02:03:31.323485 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8 (1225 ms)
7385 02:03:31.364575 [0:08:35.029367722] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7386 02:03:31.400092 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass
7388 02:03:31.403195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass>
7389 02:03:31.413129 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13
7390 02:03:33.045982 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13 (1722 ms)
7391 02:03:33.087463 [0:08:36.751608722] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7392 02:03:33.126408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass>
7393 02:03:33.127078 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass
7395 02:03:33.138500 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21
7396 02:03:35.563926 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21 (2517 ms)
7397 02:03:35.605372 [0:08:39.269382492] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7398 02:03:35.637742 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass
7400 02:03:35.640101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass>
7401 02:03:35.651922 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34
7402 02:03:39.378862 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34 (3814 ms)
7403 02:03:39.420109 [0:08:43.083586954] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7404 02:03:39.464670 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass
7406 02:03:39.467618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass>
7407 02:03:39.479349 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55
7408 02:03:45.284290 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55 (5905 ms)
7409 02:03:45.325399 [0:08:48.989400492] [429] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7410 02:03:45.382511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass>
7411 02:03:45.383187 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass
7413 02:03:45.393707 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89
7414 02:03:54.582532 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89 (9298 ms)
7415 02:03:54.660395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass>
7416 02:03:54.661067 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass
7418 02:03:54.674888 [----------] 120 tests from CaptureTests/SingleStream (517179 ms total)
7419 02:03:54.759068
7420 02:03:54.834960 [----------] Global test environment tear-down
7421 02:03:54.919007 [==========] 120 tests from 1 test suite ran. (517179 ms total)
7422 02:03:55.000532 <LAVA_SIGNAL_TESTSET STOP>
7423 02:03:55.001210 Received signal: <TESTSET> STOP
7424 02:03:55.001728 Closing test_set CaptureTests/SingleStream
7425 02:03:55.003639 + set +x
7426 02:03:55.007091 <LAVA_SIGNAL_ENDRUN 0_lc-compliance 14479155_1.6.2.3.1>
7427 02:03:55.007653 Received signal: <ENDRUN> 0_lc-compliance 14479155_1.6.2.3.1
7428 02:03:55.008016 Ending use of test pattern.
7429 02:03:55.008297 Ending test lava.0_lc-compliance (14479155_1.6.2.3.1), duration 519.27
7431 02:03:55.010915 <LAVA_TEST_RUNNER EXIT>
7432 02:03:55.011647 ok: lava_test_shell seems to have completed
7433 02:03:55.020321 Capture/Raw_1:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_13:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_2:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_21:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_3:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_34:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_5:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_55:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_8:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_89:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
7434 02:03:55.021319 end: 3.1 lava-test-shell (duration 00:08:40) [common]
7435 02:03:55.021791 end: 3 lava-test-retry (duration 00:08:40) [common]
7436 02:03:55.022237 start: 4 finalize (timeout 00:10:00) [common]
7437 02:03:55.022642 start: 4.1 power-off (timeout 00:00:30) [common]
7438 02:03:55.023289 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8183-kukui-jacuzzi-juniper-sku16-cbg-4', '--port=1', '--command=off']
7439 02:03:57.142141 >> Command sent successfully.
7440 02:03:57.151680 Returned 0 in 2 seconds
7441 02:03:57.252447 end: 4.1 power-off (duration 00:00:02) [common]
7443 02:03:57.253937 start: 4.2 read-feedback (timeout 00:09:58) [common]
7444 02:03:57.255116 Listened to connection for namespace 'common' for up to 1s
7445 02:03:58.255903 Finalising connection for namespace 'common'
7446 02:03:58.256603 Disconnecting from shell: Finalise
7447 02:03:58.257038 / #
7448 02:03:58.358143 end: 4.2 read-feedback (duration 00:00:01) [common]
7449 02:03:58.358862 end: 4 finalize (duration 00:00:03) [common]
7450 02:03:58.359493 Cleaning after the job
7451 02:03:58.359998 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14479155/tftp-deploy-8daa0ozx/ramdisk
7452 02:03:58.370284 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14479155/tftp-deploy-8daa0ozx/kernel
7453 02:03:58.405854 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14479155/tftp-deploy-8daa0ozx/dtb
7454 02:03:58.406178 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14479155/tftp-deploy-8daa0ozx/nfsrootfs
7455 02:03:58.453685 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14479155/tftp-deploy-8daa0ozx/modules
7456 02:03:58.459322 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14479155
7457 02:03:58.711096 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14479155
7458 02:03:58.711263 Job finished correctly